From f424b0ac943176327d154b2c0d86efa699570cd5 Mon Sep 17 00:00:00 2001 From: Davide Garberi Date: Thu, 22 Aug 2019 02:27:05 +0200 Subject: [PATCH 001/226] drivers: platform: Add support for Xiaomi SM8150 platform Change-Id: I3bbfd60dfa0dea0abf080d35fd3d6d14dec6e094 Signed-off-by: firebird11 --- drivers/platform/Kconfig | 2 ++ drivers/platform/xiaomi/Kconfig | 54 +++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 drivers/platform/xiaomi/Kconfig diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig index e29f6c2ad1b7..ad9aeefe95fd 100644 --- a/drivers/platform/Kconfig +++ b/drivers/platform/Kconfig @@ -10,3 +10,5 @@ source "drivers/platform/goldfish/Kconfig" source "drivers/platform/chrome/Kconfig" source "drivers/platform/msm/Kconfig" + +source "drivers/platform/xiaomi/Kconfig" diff --git a/drivers/platform/xiaomi/Kconfig b/drivers/platform/xiaomi/Kconfig new file mode 100644 index 000000000000..5ff3df1d020a --- /dev/null +++ b/drivers/platform/xiaomi/Kconfig @@ -0,0 +1,54 @@ +# Xiaomi configuration options + +config MACH_XIAOMI + bool "Xiaomi device" + depends on ARCH_QCOM + help + Support for Xiaomi products + +config MACH_XIAOMI_SM8150 + bool "Xiaomi SM8150" + depends on ARCH_QCOM + select MACH_XIAOMI + help + Support for Xiaomi SM8150 devices + +menu "Xiaomi board selection" + +config MACH_XIAOMI_ANDROMEDA + bool "Xiaomi andromeda board" + select MACH_XIAOMI_SM8150 + help + Support for Mi MIX 3 5G + +config MACH_XIAOMI_CEPHEUS + bool "Xiaomi cepheus board" + select MACH_XIAOMI_SM8150 + help + Support for Mi 9 + +config MACH_XIAOMI_CRUX + bool "Xiaomi crux board" + select MACH_XIAOMI_SM8150 + help + Support for Mi 9 Pro 5G + +config MACH_XIAOMI_NABU + bool "Xiaomi nabu board" + select MACH_XIAOMI_SM8150 + help + Support for Xiaomi Pad 5 + +config MACH_XIAOMI_RAPHAEL + bool "Xiaomi raphael board" + select MACH_XIAOMI_SM8150 + help + Support for Redmi K20 Pro/Mi 9T Pro + +config MACH_XIAOMI_VAYU + bool "Xiaomi vayu board" + select MACH_XIAOMI_SM8150 + help + Support for POCO X3 Pro + +endmenu From f33e2eb1674dd4b52db7089333f6ae6c7a4c4d21 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 02:13:59 +0200 Subject: [PATCH 002/226] arch: arm64: configs: xiaomi: Initial config fragments Change-Id: I8a757f09beede0238c7ac53627382a4c81d54509 Signed-off-by: firebird11 --- arch/arm64/configs/vendor/xiaomi/andromeda.config | 0 arch/arm64/configs/vendor/xiaomi/cepheus.config | 0 arch/arm64/configs/vendor/xiaomi/crux.config | 0 arch/arm64/configs/vendor/xiaomi/nabu.config | 0 arch/arm64/configs/vendor/xiaomi/raphael.config | 0 arch/arm64/configs/vendor/xiaomi/sm8150-common.config | 0 arch/arm64/configs/vendor/xiaomi/vayu.config | 0 7 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 arch/arm64/configs/vendor/xiaomi/andromeda.config create mode 100644 arch/arm64/configs/vendor/xiaomi/cepheus.config create mode 100644 arch/arm64/configs/vendor/xiaomi/crux.config create mode 100644 arch/arm64/configs/vendor/xiaomi/nabu.config create mode 100644 arch/arm64/configs/vendor/xiaomi/raphael.config create mode 100644 arch/arm64/configs/vendor/xiaomi/sm8150-common.config create mode 100644 arch/arm64/configs/vendor/xiaomi/vayu.config diff --git a/arch/arm64/configs/vendor/xiaomi/andromeda.config b/arch/arm64/configs/vendor/xiaomi/andromeda.config new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/arch/arm64/configs/vendor/xiaomi/cepheus.config b/arch/arm64/configs/vendor/xiaomi/cepheus.config new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/arch/arm64/configs/vendor/xiaomi/crux.config b/arch/arm64/configs/vendor/xiaomi/crux.config new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/arch/arm64/configs/vendor/xiaomi/nabu.config b/arch/arm64/configs/vendor/xiaomi/nabu.config new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/arch/arm64/configs/vendor/xiaomi/raphael.config b/arch/arm64/configs/vendor/xiaomi/raphael.config new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/arch/arm64/configs/vendor/xiaomi/vayu.config b/arch/arm64/configs/vendor/xiaomi/vayu.config new file mode 100644 index 000000000000..e69de29bb2d1 From f78f55fb209e2fe7292ce9303cd2d0fd9b27fab3 Mon Sep 17 00:00:00 2001 From: Davide Garberi Date: Sat, 29 Feb 2020 11:15:26 +0100 Subject: [PATCH 003/226] arch: arm64: configs: xiaomi: Enable CONFIG_BUILD_ARM64_DT_OVERLAY Change-Id: I25959ef7eec025a5506cb6de863c09555a1dd4ce Signed-off-by: firebird11 --- arch/arm64/configs/vendor/xiaomi/sm8150-common.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config index e69de29bb2d1..420bd53feb26 100644 --- a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config +++ b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config @@ -0,0 +1,2 @@ +# DTBO +CONFIG_BUILD_ARM64_DT_OVERLAY=y From 06fdd6356748b63f4fd162390970baefa2a1502b Mon Sep 17 00:00:00 2001 From: Luca Stefani Date: Sat, 1 Aug 2020 08:52:53 +0200 Subject: [PATCH 004/226] arch: arm64: configs: xiaomi: Enable QCACLD Change-Id: I22b3d3adf31c95a91275d0c795403b4097201430 Signed-off-by: firebird11 --- arch/arm64/configs/vendor/xiaomi/sm8150-common.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config index 420bd53feb26..53dd505736a2 100644 --- a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config +++ b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config @@ -1,2 +1,5 @@ # DTBO CONFIG_BUILD_ARM64_DT_OVERLAY=y + +# QCACLD +CONFIG_QCA_CLD_WLAN=y From 4e6baa35700aa7647a2a3649bf3dd29f08b8dc2f Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 02:18:19 +0200 Subject: [PATCH 005/226] arch: arm64: configs: xiaomi: Enable exFAT Change-Id: Ib7eb7141986625b0d01f989ae00493ddc3c4a9b8 Signed-off-by: firebird11 --- arch/arm64/configs/vendor/xiaomi/sm8150-common.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config index 53dd505736a2..06a15cb7c89e 100644 --- a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config +++ b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config @@ -3,3 +3,6 @@ CONFIG_BUILD_ARM64_DT_OVERLAY=y # QCACLD CONFIG_QCA_CLD_WLAN=y + +# exFAT +CONFIG_EXFAT_FS=y From fa961314ddaaac6dd88f2e5c46a1ce2047a1574c Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Thu, 25 Apr 2024 00:50:18 +0200 Subject: [PATCH 006/226] arch: arm64: configs: xiaomi: Enable EROFS Change-Id: If2d1802f013ea3a549868b2f280d4f4b63ed49f2 Signed-off-by: firebird11 --- arch/arm64/configs/vendor/xiaomi/sm8150-common.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config index 06a15cb7c89e..78436de13ed3 100644 --- a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config +++ b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config @@ -6,3 +6,6 @@ CONFIG_QCA_CLD_WLAN=y # exFAT CONFIG_EXFAT_FS=y + +# EROFS +CONFIG_EROFS_FS=y From 04fd3b5018729dab7aedd4d6fc8efab93cc065ad Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 00:56:55 +0100 Subject: [PATCH 007/226] arch: arm64: configs: xiaomi: Enable device-specific platform Change-Id: Iadb079c5f1d654226276dd1d316e324968fa1e92 Signed-off-by: firebird11 --- arch/arm64/configs/vendor/xiaomi/andromeda.config | 2 ++ arch/arm64/configs/vendor/xiaomi/cepheus.config | 2 ++ arch/arm64/configs/vendor/xiaomi/crux.config | 2 ++ arch/arm64/configs/vendor/xiaomi/nabu.config | 2 ++ arch/arm64/configs/vendor/xiaomi/raphael.config | 2 ++ arch/arm64/configs/vendor/xiaomi/vayu.config | 2 ++ 6 files changed, 12 insertions(+) diff --git a/arch/arm64/configs/vendor/xiaomi/andromeda.config b/arch/arm64/configs/vendor/xiaomi/andromeda.config index e69de29bb2d1..6981d04735d1 100644 --- a/arch/arm64/configs/vendor/xiaomi/andromeda.config +++ b/arch/arm64/configs/vendor/xiaomi/andromeda.config @@ -0,0 +1,2 @@ +# Platform +CONFIG_MACH_XIAOMI_ANDROMEDA=y diff --git a/arch/arm64/configs/vendor/xiaomi/cepheus.config b/arch/arm64/configs/vendor/xiaomi/cepheus.config index e69de29bb2d1..b237760c457f 100644 --- a/arch/arm64/configs/vendor/xiaomi/cepheus.config +++ b/arch/arm64/configs/vendor/xiaomi/cepheus.config @@ -0,0 +1,2 @@ +# Platform +CONFIG_MACH_XIAOMI_CEPHEUS=y diff --git a/arch/arm64/configs/vendor/xiaomi/crux.config b/arch/arm64/configs/vendor/xiaomi/crux.config index e69de29bb2d1..0611ff82cdd4 100644 --- a/arch/arm64/configs/vendor/xiaomi/crux.config +++ b/arch/arm64/configs/vendor/xiaomi/crux.config @@ -0,0 +1,2 @@ +# Platform +CONFIG_MACH_XIAOMI_CRUX=y diff --git a/arch/arm64/configs/vendor/xiaomi/nabu.config b/arch/arm64/configs/vendor/xiaomi/nabu.config index e69de29bb2d1..39bd6a435189 100644 --- a/arch/arm64/configs/vendor/xiaomi/nabu.config +++ b/arch/arm64/configs/vendor/xiaomi/nabu.config @@ -0,0 +1,2 @@ +# Platform +CONFIG_MACH_XIAOMI_NABU=y diff --git a/arch/arm64/configs/vendor/xiaomi/raphael.config b/arch/arm64/configs/vendor/xiaomi/raphael.config index e69de29bb2d1..89de85dcf84d 100644 --- a/arch/arm64/configs/vendor/xiaomi/raphael.config +++ b/arch/arm64/configs/vendor/xiaomi/raphael.config @@ -0,0 +1,2 @@ +# Platform +CONFIG_MACH_XIAOMI_RAPHAEL=y diff --git a/arch/arm64/configs/vendor/xiaomi/vayu.config b/arch/arm64/configs/vendor/xiaomi/vayu.config index e69de29bb2d1..96c16e9b2cf6 100644 --- a/arch/arm64/configs/vendor/xiaomi/vayu.config +++ b/arch/arm64/configs/vendor/xiaomi/vayu.config @@ -0,0 +1,2 @@ +# Platform +CONFIG_MACH_XIAOMI_VAYU=y From 0d7aae768df3a5a07ab7c610d81086d77a6ea27d Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 4 Jul 2022 17:15:29 +0200 Subject: [PATCH 008/226] arch: arm64: boot: dts: qcom: Import overlayed dts * From cepheus-q-oss + vayu-r-oss + nabu-r-oss Change-Id: I6774472882f5d402718724ae6c78b3605fd293c0 Signed-off-by: firebird11 --- arch/arm64/boot/dts/qcom/Makefile | 39 + .../dts/qcom/andromeda-sm8150-overlay.dts | 34 + .../dts/qcom/andromeda-sm8150-p1-overlay.dts | 36 + .../qcom/andromeda-sm8150-p1_1-overlay.dts | 36 + .../dts/qcom/andromeda-sm8150-p2-overlay.dts | 36 + .../qcom/andromeda-sm8150-p2_1-overlay.dts | 36 + .../qcom/andromeda-sm8150-p2_2-overlay.dts | 36 + .../qcom/andromeda-sm8150-p2_21-overlay.dts | 36 + .../qcom/andromeda-sm8150-p2_22-overlay.dts | 36 + .../boot/dts/qcom/cepheus-sm8150-overlay.dts | 29 + .../boot/dts/qcom/crux-sm8150-overlay.dts | 33 + .../boot/dts/qcom/nabu-sm8150-overlay.dts | 29 + arch/arm64/boot/dts/qcom/pm8150l.dtsi | 12 +- .../boot/dts/qcom/raphael-sm8150-overlay.dts | 29 + .../boot/dts/qcom/sm8150-sde-display.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150-v2-xiaomi.dts | 23 + arch/arm64/boot/dts/qcom/sm8150-xiaomi.dts | 23 + .../arm64/boot/dts/qcom/sm8150p-v2-xiaomi.dts | 23 + arch/arm64/boot/dts/qcom/sm8150p-xiaomi.dts | 23 + .../boot/dts/qcom/vayu-sm8150-overlay.dts | 29 + .../dts/qcom/xiaomi/base/sm8150-audio.dtsi | 13 + .../dts/qcom/xiaomi/base/sm8150-camera.dtsi | 23 + .../dts/qcom/xiaomi/base/sm8150-pcie.dtsi | 5 + .../dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi | 148 ++ .../qcom/xiaomi/base/sm8150-regulator.dtsi | 5 + .../boot/dts/qcom/xiaomi/base/sm8150.dtsi | 87 + .../boot/dts/qcom/xiaomi/base/trusty.dtsi | 28 + .../andromeda/andromeda-audio-overlay.dtsi | 76 + .../andromeda/andromeda-pinctrl-p1.dtsi | 125 ++ .../andromeda/andromeda-pinctrl-p1_1.dtsi | 2 + .../andromeda/andromeda-pinctrl-p2.dtsi | 2 + .../andromeda/andromeda-pinctrl-p2_1.dtsi | 2 + .../andromeda/andromeda-pinctrl-p2_2.dtsi | 2 + .../andromeda/andromeda-pinctrl-p2_21.dtsi | 2 + .../andromeda/andromeda-pinctrl-p2_22.dtsi | 2 + .../overlay/andromeda/andromeda-pinctrl.dtsi | 534 +++++ .../andromeda-sm8150-camera-sensor.dtsi | 494 ++++ .../andromeda/andromeda-sm8150-p1.dtsi | 39 + .../andromeda/andromeda-sm8150-p1_1.dtsi | 9 + .../andromeda/andromeda-sm8150-p2.dtsi | 6 + .../andromeda/andromeda-sm8150-p2_1.dtsi | 6 + .../andromeda/andromeda-sm8150-p2_2.dtsi | 6 + .../andromeda/andromeda-sm8150-p2_21.dtsi | 6 + .../andromeda/andromeda-sm8150-p2_22.dtsi | 6 + .../overlay/andromeda/andromeda-sm8150.dtsi | 659 ++++++ .../cepheus/cepheus-audio-overlay.dtsi | 76 + .../overlay/cepheus/cepheus-pinctrl.dtsi | 539 +++++ .../cepheus-sm8150-camera-sensor-mtp.dtsi | 532 +++++ .../overlay/cepheus/cepheus-sm8150.dtsi | 697 ++++++ .../batterydata-E5G-coslight-3700mah.dtsi | 136 ++ .../battery/batterydata-F1-atl-3300mah.dtsi | 156 ++ .../batterydata-F1-coslight-3300mah.dtsi | 156 ++ .../battery/batterydata-F11-gyu-4000mah.dtsi | 159 ++ .../battery/batterydata-F11-sun-4000mah.dtsi | 159 ++ .../fg-gen4-batterydata-alium-3600mah.dtsi | 160 ++ ...fg-gen4-batterydata-alium-3600mah_E5G.dtsi | 158 ++ ...gen4-batterydata-nabu-sunwoda-8720mah.dtsi | 153 ++ .../fg-gen4-batterydata-vayu-NVT-5160mah.dtsi | 153 ++ ...gen4-batterydata-vayu-sunwoda-5160mah.dtsi | 153 ++ .../dsi-panel-j20s-36-02-0a-lcd-dsc-vid.dtsi | 334 +++ .../dsi-panel-j20s-42-02-0b-lcd-dsc-vid.dtsi | 318 +++ .../display/dsi-panel-k82-36-02-0b-video.dtsi | 367 +++ .../display/dsi-panel-k82-42-02-0a-video.dtsi | 381 ++++ .../dsi-panel-samsung-fhd-ea8076-cmd.dtsi | 253 +++ .../dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi | 254 +++ ...dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi | 254 +++ ...i-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi | 254 +++ ...dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi | 254 +++ .../dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi | 277 +++ .../display/dsi-panel-ss-fhd-ea8076-cmd.dtsi | 242 ++ .../dsi-panel-ss-fhd-ea8076-global-cmd.dtsi | 242 ++ .../dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi | 163 ++ .../dsi-panel-tianma-fhd-nt36672a-video.dtsi | 387 ++++ ...dsi-panel-visionox-fhd-r66456-f11-cmd.dtsi | 167 ++ .../qcom/xiaomi/overlay/common/pm8150.dtsi | 35 + .../qcom/xiaomi/overlay/common/pm8150b.dtsi | 33 + .../qcom/xiaomi/overlay/common/pm8150l.dtsi | 59 + .../overlay/common/sm8150-audio-overlay.dtsi | 57 + .../overlay/common/sm8150-pmic-overlay.dtsi | 28 + .../overlay/common/sm8150-sde-display.dtsi | 532 +++++ .../qcom/xiaomi/overlay/common/smb1390.dtsi | 15 + .../common/xiaomi-sdx50-sm8150-common.dtsi | 407 ++++ .../overlay/common/xiaomi-sm8150-common.dtsi | 527 +++++ .../overlay/crux/crux-audio-overlay.dtsi | 74 + .../xiaomi/overlay/crux/crux-pinctrl.dtsi | 796 +++++++ .../crux/crux-sm8150-camera-sensor-mtp.dtsi | 537 +++++ .../qcom/xiaomi/overlay/crux/crux-sm8150.dtsi | 1004 +++++++++ .../overlay/nabu/nabu-audio-overlay.dtsi | 51 + .../xiaomi/overlay/nabu/nabu-pinctrl.dtsi | 904 ++++++++ .../nabu/nabu-sm8150-camera-sensor-mtp.dtsi | 244 ++ .../qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi | 1275 +++++++++++ .../raphael/raphael-audio-overlay.dtsi | 39 + .../overlay/raphael/raphael-pinctrl.dtsi | 608 +++++ .../raphael/raphael-sm8150-camera-sensor.dtsi | 483 ++++ .../overlay/raphael/raphael-sm8150.dtsi | 736 ++++++ .../overlay/vayu/vayu-audio-overlay.dtsi | 48 + .../xiaomi/overlay/vayu/vayu-pinctrl.dtsi | 617 +++++ .../vayu/vayu-sm8150-camera-sensor-mtp.dtsi | 507 +++++ .../qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi | 1979 +++++++++++++++++ include/uapi/linux/input-event-codes.h | 6 + 100 files changed, 21995 insertions(+), 7 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-p1-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-p1_1-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-p2-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_1-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_2-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_21-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_22-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/cepheus-sm8150-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/crux-sm8150-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/nabu-sm8150-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/raphael-sm8150-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8150-v2-xiaomi.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8150-xiaomi.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8150p-v2-xiaomi.dts create mode 100644 arch/arm64/boot/dts/qcom/sm8150p-xiaomi.dts create mode 100644 arch/arm64/boot/dts/qcom/vayu-sm8150-overlay.dts create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-audio.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-camera.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pcie.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-regulator.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/base/trusty.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1_1.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_1.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_2.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_21.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_22.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1_1.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_1.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_2.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_21.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_22.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150-camera-sensor-mtp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-E5G-coslight-3700mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-atl-3300mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-coslight-3300mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-gyu-4000mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-sun-4000mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah_E5G.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-nabu-sunwoda-8720mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-NVT-5160mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-sunwoda-5160mah.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-36-02-0a-lcd-dsc-vid.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-42-02-0b-lcd-dsc-vid.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-tianma-fhd-nt36672a-video.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-visionox-fhd-r66456-f11-cmd.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150b.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150l.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-pmic-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-sde-display.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/smb1390.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sdx50-sm8150-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sm8150-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150-camera-sensor-mtp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150-camera-sensor-mtp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150-camera-sensor.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-audio-overlay.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150-camera-sensor-mtp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4d75cff64e43..af8661d62c1f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,4 +1,41 @@ # SPDX-License-Identifier: GPL-2.0 +ifeq ($(CONFIG_MACH_XIAOMI),y) + +ifeq ($(CONFIG_MACH_XIAOMI_SM8150),y) +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SM8150) += \ + andromeda-sm8150-overlay.dtbo \ + andromeda-sm8150-p1-overlay.dtbo \ + andromeda-sm8150-p1_1-overlay.dtbo \ + andromeda-sm8150-p2-overlay.dtbo \ + andromeda-sm8150-p2_1-overlay.dtbo \ + andromeda-sm8150-p2_2-overlay.dtbo \ + andromeda-sm8150-p2_21-overlay.dtbo \ + andromeda-sm8150-p2_22-overlay.dtbo \ + cepheus-sm8150-overlay.dtbo \ + crux-sm8150-overlay.dtbo \ + nabu-sm8150-overlay.dtbo \ + raphael-sm8150-overlay.dtbo \ + vayu-sm8150-overlay.dtbo + +andromeda-sm8150-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +andromeda-sm8150-p1-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +andromeda-sm8150-p1_1-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +andromeda-sm8150-p2-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +andromeda-sm8150-p2_1-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +andromeda-sm8150-p2_2-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +andromeda-sm8150-p2_21-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +andromeda-sm8150-p2_22-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +cepheus-sm8150-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +crux-sm8150-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +nabu-sm8150-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +raphael-sm8150-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +vayu-sm8150-overlay.dtbo-base := sm8150-xiaomi.dtb sm8150-v2-xiaomi.dtb sm8150p-xiaomi.dtb sm8150p-v2-xiaomi.dtb +endif # CONFIG_BUILD_ARM64_DT_OVERLAY +endif # CONFIG_MACH_XIAOMI_SM8150 + +else # CONFIG_MACH_XIAOMI + ifeq ($(TARGET_BOARD_TYPE),auto) ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SM8150) += \ @@ -588,6 +625,8 @@ endif endif +endif # CONFIG_MACH_XIAOMI + ifeq ($(CONFIG_ARM64),y) always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-overlay.dts new file mode 100644 index 000000000000..3ad6b24cf95d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-overlay.dts @@ -0,0 +1,34 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-sm8150.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x27 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-p1-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p1-overlay.dts new file mode 100644 index 000000000000..4babe5db12c5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p1-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "xiaomi/overlay/andromeda/andromeda-sm8150-p1.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-pinctrl-p1.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x28 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-p1_1-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p1_1-overlay.dts new file mode 100644 index 000000000000..dc4947679af7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p1_1-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "xiaomi/overlay/andromeda/andromeda-sm8150-p1_1.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-pinctrl-p1_1.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x2b 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2-overlay.dts new file mode 100644 index 000000000000..3ba628d2b6f7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "xiaomi/overlay/andromeda/andromeda-sm8150-p2.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-pinctrl-p2.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x29 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_1-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_1-overlay.dts new file mode 100644 index 000000000000..f28dab8c4852 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_1-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "xiaomi/overlay/andromeda/andromeda-sm8150-p2_1.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-pinctrl-p2_1.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x2c 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_2-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_2-overlay.dts new file mode 100644 index 000000000000..f94584c4f4c0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_2-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "xiaomi/overlay/andromeda/andromeda-sm8150-p2_2.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-pinctrl-p2_2.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x2d 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_21-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_21-overlay.dts new file mode 100644 index 000000000000..5155ccfa4a7a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_21-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "xiaomi/overlay/andromeda/andromeda-sm8150-p2_21.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-pinctrl-p2_21.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x2e 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_22-overlay.dts b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_22-overlay.dts new file mode 100644 index 000000000000..38aa96ec0a75 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/andromeda-sm8150-p2_22-overlay.dts @@ -0,0 +1,36 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi" + +#include "xiaomi/overlay/andromeda/andromeda-sm8150-p2_22.dtsi" +#include "xiaomi/overlay/andromeda/andromeda-pinctrl-p2_22.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M ANDROMEDA"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x2f 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/cepheus-sm8150-overlay.dts b/arch/arm64/boot/dts/qcom/cepheus-sm8150-overlay.dts new file mode 100644 index 000000000000..a3b5361e657b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/cepheus-sm8150-overlay.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/cepheus/cepheus-sm8150.dtsi" +#include "xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi" + +/ { + model = "CEPHEUS"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <37 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/crux-sm8150-overlay.dts b/arch/arm64/boot/dts/qcom/crux-sm8150-overlay.dts new file mode 100644 index 000000000000..a27fdcd6d6c5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/crux-sm8150-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/crux/crux-sm8150.dtsi" +#include "xiaomi/overlay/crux/crux-audio-overlay.dtsi" +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" + +/ { + model = "SDX50M CRUX"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x2B 0x1>; + +}; + diff --git a/arch/arm64/boot/dts/qcom/nabu-sm8150-overlay.dts b/arch/arm64/boot/dts/qcom/nabu-sm8150-overlay.dts new file mode 100644 index 000000000000..bb0eb37e5217 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/nabu-sm8150-overlay.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/nabu/nabu-sm8150.dtsi" +#include "xiaomi/overlay/nabu/nabu-audio-overlay.dtsi" + +/ { + model = "NABU"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <48 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 3586af695f4f..b764ca015f11 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -334,7 +334,7 @@ qcom,num-lpg-channels = <3>; qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100 90 80 70 60 50 40 30 20 10 0>; - lpg1 { + pwm_lpg1: lpg1 { qcom,lpg-chan-id = <1>; qcom,ramp-step-ms = <100>; qcom,ramp-pause-hi-count = <2>; @@ -345,7 +345,7 @@ qcom,ramp-pattern-repeat; }; - lpg2 { + pwm_lpg2: lpg2 { qcom,lpg-chan-id = <2>; qcom,ramp-step-ms = <100>; qcom,ramp-pause-hi-count = <2>; @@ -356,7 +356,7 @@ qcom,ramp-pattern-repeat; }; - lpg3 { + pwm_lpg3: lpg3 { qcom,lpg-chan-id = <3>; qcom,ramp-step-ms = <100>; qcom,ramp-pause-hi-count = <2>; @@ -379,19 +379,19 @@ pm8150l_rgb_led: qcom,leds@d000 { compatible = "qcom,tri-led"; reg = <0xd000 0x100>; - red { + red_led: red { label = "red"; pwms = <&pm8150l_lpg 0 1000000>; led-sources = <0>; linux,default-trigger = "timer"; }; - green { + green_led: green { label = "green"; pwms = <&pm8150l_lpg 1 1000000>; led-sources = <1>; linux,default-trigger = "timer"; }; - blue { + blue_led: blue { label = "blue"; pwms = <&pm8150l_lpg 2 1000000>; led-sources = <2>; diff --git a/arch/arm64/boot/dts/qcom/raphael-sm8150-overlay.dts b/arch/arm64/boot/dts/qcom/raphael-sm8150-overlay.dts new file mode 100644 index 000000000000..e3b35255216d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/raphael-sm8150-overlay.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/raphael/raphael-sm8150.dtsi" +#include "xiaomi/overlay/raphael/raphael-audio-overlay.dtsi" + +/ { + model = "RAPHAEL"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <40 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi index ddcd25ac1273..9e82bea8c132 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi @@ -561,7 +561,7 @@ &sde_dp { qcom,dp-usbpd-detection = <&pm8150b_pdphy>; qcom,ext-disp = <&ext_disp>; - qcom,dp-aux-switch = <&fsa4480>; + /* qcom,dp-aux-switch = <&fsa4480>; */ qcom,usbplug-cc-gpio = <&tlmm 38 0>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2-xiaomi.dts b/arch/arm64/boot/dts/qcom/sm8150-v2-xiaomi.dts new file mode 100644 index 000000000000..47c6db4cffeb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-v2-xiaomi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150-v2.dtsi" +#include "xiaomi/base/sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 v2 SoC"; + compatible = "qcom,sm8150"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-xiaomi.dts b/arch/arm64/boot/dts/qcom/sm8150-xiaomi.dts new file mode 100644 index 000000000000..b804a396c922 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-xiaomi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150.dtsi" +#include "xiaomi/base/sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 v1 SoC"; + compatible = "qcom,sm8150"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150p-v2-xiaomi.dts b/arch/arm64/boot/dts/qcom/sm8150p-v2-xiaomi.dts new file mode 100644 index 000000000000..470042197d16 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150p-v2-xiaomi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p-v2.dtsi" +#include "xiaomi/base/sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v2 SoC"; + compatible = "qcom,sm8150p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150p-xiaomi.dts b/arch/arm64/boot/dts/qcom/sm8150p-xiaomi.dts new file mode 100644 index 000000000000..f7d46f5dd1bf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150p-xiaomi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p.dtsi" +#include "xiaomi/base/sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v1 SoC"; + compatible = "qcom,sm8150p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/vayu-sm8150-overlay.dts b/arch/arm64/boot/dts/qcom/vayu-sm8150-overlay.dts new file mode 100644 index 000000000000..0e0129d3d871 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/vayu-sm8150-overlay.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "xiaomi/overlay/vayu/vayu-sm8150.dtsi" +#include "xiaomi/overlay/vayu/vayu-audio-overlay.dtsi" + +/ { + model = "VAYU"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <47 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-audio.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-audio.dtsi new file mode 100644 index 000000000000..b923803e5fb0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-audio.dtsi @@ -0,0 +1,13 @@ +&snd_934x { + qcom,msm-mbhc-usbc-audio-supported = <1>; +}; + +&snd_934x { + /delete-property/ fsa4480-i2c-handle; +}; + +/* +&fsa4480 { + reg = <0x42>; +}; +*/ diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-camera.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-camera.dtsi new file mode 100644 index 000000000000..34705a761b0d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-camera.dtsi @@ -0,0 +1,23 @@ +&i2c_freq_100Khz_cci0 { + hw-scl-stretch-en = <1>; +}; + +&i2c_freq_400Khz_cci0 { + hw-scl-stretch-en = <1>; +}; + +&i2c_freq_custom_cci0 { + hw-scl-stretch-en = <0>; +}; + +&i2c_freq_100Khz_cci1 { + hw-scl-stretch-en = <1>; +}; + +&i2c_freq_400Khz_cci1 { + hw-scl-stretch-en = <1>; +}; + +&i2c_freq_custom_cci1 { + hw-scl-stretch-en = <0>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pcie.dtsi new file mode 100644 index 000000000000..137b831ca704 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pcie.dtsi @@ -0,0 +1,5 @@ +&pcie0 { + pinctrl-0 = <&pcie0_clkreq_default>; + /delete-property/ perst-gpio; + /delete-property/ wake-gpio; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi new file mode 100644 index 000000000000..444d383a00a3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi @@ -0,0 +1,148 @@ +&ts_int_suspend { + config { + input-enable; + }; +}; + +&ts_reset_suspend { + config { + /delete-property/ bias-pull-down; + bias-disable; + output-low; + }; +}; + +/delete-node/ &pcie0_perst_default; +/delete-node/ &pcie0_wake_default; + +&nfc_enable_active { + mux { + pins = "gpio41", "gpio48"; + }; + + config { + pins = "gpio41", "gpio48"; + }; +}; + +&nfc_enable_suspend { + mux { + pins = "gpio41", "gpio48"; + }; + + config { + pins = "gpio41", "gpio48"; + }; +}; + +&quat_aux_pcm_sleep { + mux { + function = "func2"; + }; +}; + +&quat_aux_pcm_active { + mux { + function = "func2"; + }; +}; + +&quat_aux_pcm_din_sleep { + mux { + function = "func2"; + }; +}; + +&quat_aux_pcm_din_active { + mux { + function = "func2"; + }; +}; + +&quat_aux_pcm_dout_sleep { + mux { + function = "func2"; + }; +}; + +&quat_aux_pcm_dout_active { + mux { + function = "func2"; + }; +}; + +&tlmm { + tert_tdm { + cs35l41_int_default: cs35l41_int_default { + mux { + pins = "gpio10"; + function = "gpio"; + }; + config { + pins = "gpio10"; + bias-pull-up; + drive-strength = <8>; + input-enable; + }; + }; + }; +}; + +&tlmm { + /* USB C analog configuration */ + wcd_usbc_analog_en1 { + wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle { + mux { + pins = "gpio35"; + function = "gpio"; + }; + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active { + mux { + pins = "gpio35"; + function = "gpio"; + }; + config { + pins = "gpio35"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en2 { + wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle { + mux { + pins = "gpio58"; + function = "gpio"; + }; + config { + pins = "gpio58"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active { + mux { + pins = "gpio58"; + function = "gpio"; + }; + config { + pins = "gpio58"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-regulator.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-regulator.dtsi new file mode 100644 index 000000000000..6aedd1ecfa4b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-regulator.dtsi @@ -0,0 +1,5 @@ +&pm8150_l13 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi new file mode 100644 index 000000000000..bf0f93ebbec2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi @@ -0,0 +1,87 @@ +/ { + aliases { + spi1 = &qupv3_se1_spi; + }; +}; + +&shared_meta { + parts = "vbmeta,boot,system,vendor,dtbo"; +}; + +&android_q_fstab { + odm { + status = "disabled"; + }; + vendor { + fsmgr_flags = "wait,avb"; + }; +}; + +&reserved_memory { + xbl_dump_mem: xbl_dump_mem { + no-map; + reg = <0x0 0x85d00000 0x0 0x100000>; + }; +}; + +&pil_adsp_mem { + reg = <0x0 0x8be00000 0x0 0x2200000>; +}; + +&pil_modem_mem { + reg = <0x0 0x8e000000 0x0 0x9600000>; +}; + +&pil_video_mem { + reg = <0x0 0x97600000 0x0 0x500000>; +}; + +&pil_slpi_mem { + reg = <0x0 0x97b00000 0x0 0x1400000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x98f00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x98f10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x98f15000 0x0 0x2000>; +}; + +&pil_spss_mem { + reg = <0x0 0x99000000 0x0 0x100000>; +}; + +&pil_cdsp_mem { + reg = <0x0 0x99100000 0x0 0x1400000>; +}; + +&disp_rdump_memory { + status = "disabled"; +}; + +#include "trusty.dtsi" + +&qcom_seecom { + reg = <0x87900000 0x3E00000>; +}; + +&qcom_smcinvoke { + reg = <0x87900000 0x3E00000>; +}; + +&soc { + qcom,rmtfs_sharedmem@0 { + reg = <0x0 0x300000>; + }; +}; + +#include "sm8150-audio.dtsi" +#include "sm8150-camera.dtsi" +#include "sm8150-pcie.dtsi" +#include "sm8150-pinctrl.dtsi" +#include "sm8150-regulator.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/trusty.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/trusty.dtsi new file mode 100644 index 000000000000..5d054de89e9f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/trusty.dtsi @@ -0,0 +1,28 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + trusty { + #size-cells = <0x2>; + #address-cells = <0x2>; + ranges; + compatible = "android,trusty-smc-v1"; + log { + compatible = "android,trusty-log-v1"; + }; + virtio { + compatible = "android,trusty-virtio-v1"; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi new file mode 100644 index 000000000000..a243e7d415ae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/sm8150-audio-overlay.dtsi" + + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "MIC BIAS2", "Headset Mic", + "AMIC2_EXT_0", "MIC BIAS2", + "MIC BIAS4", "ANCLeft Headset Mic", + "AMIC2_EXT_1", "MIC BIAS4", + "MIC BIAS1", "ANCRight Headset Mic", + "AMIC3", "MIC BIAS1", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "ANCRight Headset Mic", + "AMIC1", "MIC BIAS4", + "MIC BIAS4", "ANCLeft Headset Mic"; + + qcom,uart-audio-sw-gpio = <&sbu_uart_en>; + qcom,adc2-switch-gpio = <&adc2_switch_gpio>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,fsa4476-gpio-support = <1>; + qcom,usbc-analog-en1-gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2-gpio = <&tlmm 35 0>; + + pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", + "quat_tdm_enable", "quat_tdm_disable", + "aud_active", "aud_sleep"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; + pinctrl-4 = <&wcd_usbc_analog_en2_active>; + pinctrl-5 = <&wcd_usbc_analog_en2_idle>; +}; + +&soc { + sbu_uart_en: msm_cdc_pinctrl@25 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sbu_uart_en_active>; + pinctrl-1 = <&sbu_uart_en_idle>; + }; + + adc2_switch_gpio: msm_cdc_pinctrl@130 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&adc2_switch_gpio_active>; + pinctrl-1 = <&adc2_switch_gpio_idle>; + }; + + wcd_usbc_analog_en1_gpio: msm_cdc_pinctrl@152 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en1_active>; + pinctrl-1 = <&wcd_usbc_analog_en1_idle>; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1.dtsi new file mode 100644 index 000000000000..8608642bee99 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1.dtsi @@ -0,0 +1,125 @@ +/*for E5 5G pinctrl*/ + +&tlmm { + + nfc { + nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active { + /* active state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio36", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend { + /* sleep state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio36", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + ai_key_ctrl { + ai_key_active { + mux { + pins = "gpio41"; + function = "gpio"; + }; + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + + }; + + ai_key_idle { + mux { + pins = "gpio41"; + function = "gpio"; + }; + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1_1.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1_1.dtsi new file mode 100644 index 000000000000..b7a31e8b2aae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p1_1.dtsi @@ -0,0 +1,2 @@ +/*for E5 5G pinctrl*/ +#include "andromeda-pinctrl-p1.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2.dtsi new file mode 100644 index 000000000000..549da08e5a9b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2.dtsi @@ -0,0 +1,2 @@ +/*for E5 5G pinctrl*/ +#include "andromeda-pinctrl-p1_1.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_1.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_1.dtsi new file mode 100644 index 000000000000..b81dd3abfcd4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_1.dtsi @@ -0,0 +1,2 @@ +/*for E5 5G pinctrl*/ +#include "andromeda-pinctrl-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_2.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_2.dtsi new file mode 100644 index 000000000000..b81dd3abfcd4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_2.dtsi @@ -0,0 +1,2 @@ +/*for E5 5G pinctrl*/ +#include "andromeda-pinctrl-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_21.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_21.dtsi new file mode 100644 index 000000000000..b81dd3abfcd4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_21.dtsi @@ -0,0 +1,2 @@ +/*for E5 5G pinctrl*/ +#include "andromeda-pinctrl-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_22.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_22.dtsi new file mode 100644 index 000000000000..b81dd3abfcd4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl-p2_22.dtsi @@ -0,0 +1,2 @@ +/*for E5 5G pinctrl*/ +#include "andromeda-pinctrl-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi new file mode 100644 index 000000000000..6bf9122c3e6c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi @@ -0,0 +1,534 @@ +/*for E5 5G pinctrl*/ + +&tlmm { + + /* GPIO_119 : FP_RESET_N */ + msm_gpio_119: msm_gpio_119 { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + /* GPIO_119 : FP_RESET_N, state device active*/ + msm_gpio_119_output_high: msm_gpio_119_output_high { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + cam_sensor_active_wide: cam_sensor_active_wide { + /* WIDE RESET DVDDEN AVDDEN 1.8AVDDEN */ + mux { + pins = "gpio28", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_wide: cam_sensor_suspend_wide { + /* WIDE RESET DVDDEN AVDDEN 1.8AVDDEN */ + mux { + pins = "gpio28", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_tele: cam_sensor_active_tele { + /* TELE RESET DVDDEN AVDDEN */ + mux { + pins = "gpio30", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_tele: cam_sensor_suspend_tele { + /* TELE RESET DVDDEN AVDDEN */ + mux { + pins = "gpio30", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_front: cam_sensor_active_front { + /* FRONT RESET DVDDEN, AVDDEN */ + mux { + pins = "gpio12", "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio32"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_front: cam_sensor_suspend_front { + /* FRONT RESET DVDDEN, AVDDEN */ + mux { + pins = "gpio12", "gpio32"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_ultra: cam_sensor_active_ultra { + /* ULTRA RESET DVDDEN AVDDEN */ + mux { + pins = "gpio23", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio33"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_ultra: cam_sensor_suspend_ultra { + /* ULTRA RESET DVDDEN AVDDEN */ + mux { + pins = "gpio23", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_actuator_wide_en: cam_actuator_wide_en { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_actuator_tele_en: cam_actuator_tele_en { + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_viodd_en: cam_sensor_viodd_en { + mux { + pins = "gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + adc2_switch_gpio_ctrl { + adc2_switch_gpio_idle: adc2_switch_idle { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + adc2_switch_gpio_active: adc2_switch_active { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + sbu_uart_en_ctrl { + sbu_uart_en_idle: uart_audio_en_idle { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + sbu_uart_en_active: uart_audio_en_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio41", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio41", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + ai_key_ctrl { + ai_key_active_default: ai_key_active { + mux { + pins = "gpio36"; + function = "gpio"; + }; + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + + }; + + ai_key_idle_default: ai_key_idle { + mux { + pins = "gpio36"; + function = "gpio"; + }; + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + }; + + wcd_usbc_analog_en1 { + wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle { + mux { + pins = "gpio152"; + function = "gpio"; + }; + config { + pins = "gpio152"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active { + mux { + pins = "gpio152"; + function = "gpio"; + }; + config { + pins = "gpio152"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + wcd_usbc_analog_en2 { + wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle { + mux { + pins = "gpio35"; + function = "gpio"; + }; + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active { + mux { + pins = "gpio35"; + function = "gpio"; + }; + config { + pins = "gpio35"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + +}; + +&cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-camera-sensor.dtsi new file mode 100644 index 000000000000..964a7597f8b8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-camera-sensor.dtsi @@ -0,0 +1,494 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pm8150l_switch0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; +}; + +&pm8150l_switch1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + com,default-led-trigger = "switch1_trigger"; +}; + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash2>; + torch-source = <&pm8150l_torch2>; + switch-source = <&pm8150l_switch1>; + status = "ok"; + }; + + led_flash_front_aux: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash2>; + torch-source = <&pm8150l_torch2>; + switch-source = <&pm8150l_switch1>; + status = "ok"; + }; + + wide_actuator_regulator: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "actuator_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_actuator_wide_en>; + vin-supply = <&pm8150l_bob>; + }; + + tele_actuator_regulator: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "actuator_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 31 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_actuator_tele_en>; + vin-supply = <&pm8150l_bob>; + }; + + camera_viodd_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_viodd_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 34 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_viodd_en>; + vin-supply = <&pm8150_s4>; + }; + + camera_ois_regulator: gpio-regulator@3 { + compatible = "regulator-fixed"; + reg = <0x03 0x00>; + regulator-name = "camera_ois_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 24 0>; + vin-supply = <&pm8150_s4>; + }; +}; + +&cam_cci1 { + cell-index = <1>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&wide_actuator_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&tele_actuator_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&camera_ois_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_wide>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_wide>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + + sensor-mode = <0>; + cci-master = <0>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_tele>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_tele>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + + sensor-mode = <0>; + cci-master = <0>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0 >; + rgltr-max-voltage = <1800000 0 >; + rgltr-load-current = <1000 0 >; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK2"; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_aux: qcom,eeprom@3 { + cell-index = <3>; + reg = <0x03>; + compatible = "qcom,eeprom"; + slave-addr = <0xA2>; + i2c-freq-mode = <1>; + cam_vio-supply = <&camera_viodd_ldo>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_ultra>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_ultra>; + gpios = <&tlmm 16 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK3"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + ois-src = <&ois_rear>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&pm8150_l17>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0 2856000>; + rgltr-max-voltage = <1800000 4000000 1352000 0 3008000>; + rgltr-load-current = <1000 80000 1200000 0 10000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_wide>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_wide>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET_W", + "CAM_VDD0_EN"; + sensor-mode = <0>; + cci-master = <0>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&pm8150_l17>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0 2856000>; + rgltr-max-voltage = <1800000 4000000 1352000 0 3008000>; + rgltr-load-current = <1000 80000 1200000 0 1000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_tele>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_tele>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET_T", + "CAM_VDD1_EN"; + sensor-mode = <0>; + cci-master = <1>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_front>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&pm8150_l17>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0 2856000>; + rgltr-max-voltage = <1800000 4000000 1352000 0 3008000>; + rgltr-load-current = <1000 80000 1200000 0 1000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&tlmm 32 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET_F", + "CAM_VDD2_EN"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_front_aux>; + eeprom-src = <&eeprom_front_aux>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 0>; + rgltr-max-voltage = <1800000 4000000 0>; + rgltr-load-current = <1000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_ultra>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_ultra>; + + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&tlmm 33 0>; + gpio-standby = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_PWD_U", + "CAM_VDD3_EN"; + sensor-mode = <0>; + cci-master = <0>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1.dtsi new file mode 100644 index 000000000000..075fad8a0371 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1.dtsi @@ -0,0 +1,39 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-sm8150.dtsi" +&soc { + gpio_keys { + pinctrl-0 = <&ai_key_active_default>; + ai_key { + label = "ai_key"; + gpios = <&tlmm 41 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <39>; + }; + }; +}; +&qupv3_se9_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 36 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + //qcom,nq-esepwr = <&tlmm 42 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1_1.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1_1.dtsi new file mode 100644 index 000000000000..3c441a515ab5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p1_1.dtsi @@ -0,0 +1,9 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-sm8150-p1.dtsi" +&dsi_samsung_fhd_ea8076_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2.dtsi new file mode 100644 index 000000000000..5e907d4f7f5a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2.dtsi @@ -0,0 +1,6 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-sm8150-p1_1.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_1.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_1.dtsi new file mode 100644 index 000000000000..d6ab8778539f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_1.dtsi @@ -0,0 +1,6 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-sm8150-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_2.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_2.dtsi new file mode 100644 index 000000000000..d6ab8778539f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_2.dtsi @@ -0,0 +1,6 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-sm8150-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_21.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_21.dtsi new file mode 100644 index 000000000000..d6ab8778539f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_21.dtsi @@ -0,0 +1,6 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-sm8150-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_22.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_22.dtsi new file mode 100644 index 000000000000..d6ab8778539f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150-p2_22.dtsi @@ -0,0 +1,6 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-sm8150-p2.dtsi" diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150.dtsi new file mode 100644 index 000000000000..c5cb203bf7b5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-sm8150.dtsi @@ -0,0 +1,659 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like E5 5G and so and) +*/ + +#include "andromeda-pinctrl.dtsi" +#include "../common/xiaomi-sdx50-sm8150-common.dtsi" + +#include "andromeda-sm8150-camera-sensor.dtsi" + +&soc { + touch_vddio_vreg: touch_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 37 0>; + }; + vdd_boost_vreg: vdd_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-always-on; + gpio = <&pm8150b_gpios 5 0>; + }; + disp_vci_vreg: disp_vci_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 7 0>; + }; + + fp_vdd_vreg: fp_vdd_vreg { + compatible = "regulator-fixed"; + regulator-name = "fp_vdd_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 92 0>; + regulator-always-on; + }; + fingerprint_fpc { + status = "ok"; + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <118 0x0>; + fpc,gpio_irq = <&tlmm 118 0x0>; + /* fpc,enable-on-boot; */ + /* fpc,enable-wakeup; */ + + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active"; + + pinctrl-0 = <&msm_gpio_119>; + pinctrl-1 = <&msm_gpio_119_output_high>; + }; + pcie0: qcom,pcie@1c00000 { + status = "disabled"; + }; + + gpio_keys { + pinctrl-0 = <&ai_key_active_default>; + ai_key { + label = "ai_key"; + gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <39>; + }; + }; + +}; + +&sde_dsi { + vcie-supply = <&disp_vci_vreg>; +}; + +&pm8150l_lpg { + qcom,lut-patterns = <0 1 1 1 1 0>; +}; + +&pwm_lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <400>; + qcom,ramp-pause-hi-count = <0>; + qcom,ramp-pause-lo-count = <0>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <5>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; +}; + +&red_led { + label = "white"; +}; + +&green_led { + status = "disabled"; +}; + +&blue_led { + status = "disabled"; +}; + +&qcom_qbt1000 { + status = "disabled"; +}; + +&qcom_seecom { + reg = <0x87900000 0x3E00000>; +}; + +&qcom_smcinvoke { + reg = <0x87900000 0x3E00000>; +}; + +&qupv3_se4_i2c { + status = "ok"; + + fsa4480@43 { + status = "disabled"; + }; +}; + +&qupv3_se8_i2c { + status = "ok"; + /*smart PA*/ + tas2557@4c{ + compatible = "ti,tas2557"; + reg = <0x4c>; + ti,cdc-reset-gpio = <&tlmm 59 0>; + ti,irq-gpio = <&tlmm 115 0>; + ti,i2s-bits = <16>; + ti,bypass-tmax = <0>; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2008>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + vdd-supply = <&pm8150l_l1>; + avdd-supply = <&touch_vddio_vreg>; + fts,pwr-reg-name = "avdd"; + fts,bus-reg-name = "vdd"; + fts,irq-gpio = <&tlmm 122 0x2008>; + fts,irq-gpio-name = "fts_irq"; + fts,reset-gpio-enable; + fts,reset-gpio = <&tlmm 54 0x00>; + fts,reset-gpio-name = "fts_rst"; + fts,irq-flags = <0x2008>; /* IRQF_ONESHOT | IRQF_TRIGGER_LOW */ + fts,x-max = <1080>; + fts,y-max = <2340>; + fts,default-fw-name = "st_fts_e5.ftb"; + fts,config-array-size = <1>; + fts,dump-click-count; + fts,disable-fw-update; + fts,touch-up-threshold-min = <40>; + fts,touch-up-threshold-max = <120>; + fts,touch-up-threshold-def = <80>; + fts,touch-tolerance-min = <5>; + fts,touch-tolerance-max = <35>; + fts,touch-tolerance-def = <25>; + fts,touch-wgh-min-def = <1>; + fts,touch-wgh-min-max = <15>; + fts,touch-wgh-min-min = <0>; + fts,touch-wgh-max-def = <5>; + fts,touch-wgh-max-max = <15>; + fts,touch-wgh-max-min = <0>; + fts,touch-wgh-step-def = <1>; + fts,touch-wgh-step-max = <2>; + fts,touch-wgh-step-min = <0>; + fts,edgefilter-leftrigt-def = <45>; + fts,edgefilter-topbottom-def = <0>; + fts,edgefilter-top-ingamemode = <0>; + fts,edgefilter-bottom-ingamemode = <0>; + fts,edgefilter-area-step1 = <100>; + fts,edgefilter-area-step2 = <170>; + fts,edgefilter-area-step3 = <250>; + fts,cfg_0 { + fts,tp-vendor = <0x52>; + fts,fw-name = "st_fts_e5.ftb"; + fts,limit-name = "stm_fts_production_limits.csv"; + fts,clicknum-file-name = "fts+sdc"; + }; + }; +}; + +&vendor { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "../common/battery/batterydata-E5G-coslight-3700mah.dtsi" + #include "../common/battery/fg-gen4-batterydata-alium-3600mah_E5G.dtsi" + }; +}; + +&pm8150b_fg { + qcom,battery-data = <&mtp_batterydata>; + qcom,rapid-soc-dec-en; + qcom,fg-sys-term-current = <(-300)>; + qcom,fg-cutoff-voltage = <3400>; + qcom,fg-cutoff-current = <200>; + qcom,fg-empty-voltage = <3100>; + qcom,fg-batt-temp-delta = <6>; + qcom,fg-force-load-profile; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <1>; + qcom,usb-icl-ua = <2800000>; + qcom,fcc-max-ua = <3700000>; + qcom,fv-max-uv = <4450000>; + qcom,auto-recharge-soc = <99>; + qcom,chg-term-src = <1>; + qcom,chg-term-current-ma = <(-220)>; + qcom,thermal-mitigation = <3000000 2800000 2600000 2400000 2200000 2100000 2000000 + 1800000 1600000 1500000 1400000 1200000 1000000 900000 + 800000 500000>; + qcom,thermal-mitigation-icl + = <2800000 2700000 2600000 2400000 2200000 2100000 2000000 + 1800000 1800000 1800000 1700000 1600000 1500000 1300000 + 1000000 750000>; + qcom,thermal-mitigation-dcp + = <1800000 1800000 1800000 1800000 1800000 1800000 1800000 + 1800000 1800000 1700000 1600000 1400000 1200000 1100000 + 1100000 1000000>; + qcom,thermal-mitigation-qc2 + = <1500000 1500000 1500000 1500000 1450000 1400000 1350000 + 1300000 1150000 1100000 1000000 900000 850000 750000 + 650000 500000>; + qcom,thermal-fcc-qc3-normal + = <3200000 3000000 2800000 2600000 2500000 2400000 2300000 + 2200000 2100000 1800000 1600000 1400000 1200000 1000000 + 750000 750000>; + qcom,thermal-fcc-qc3-cp + = <3600000 3500000 3400000 3300000 3200000 3200000 3200000 + 3200000 3200000 2800000 2400000 2200000 2000000 1300000 + 750000 700000>; + qcom,thermal-fcc-qc3-classb-cp + = <3700000 3700000 3700000 3700000 3700000 3700000 3700000 + 3700000 3700000 3600000 3400000 3200000 3000000 2200000 + 2000000 700000>; + qcom,thermal-mitigation-pd-base + = <3000000 2800000 2600000 2400000 2200000 2000000 1800000 + 1600000 1600000 1400000 1200000 1100000 1050000 1000000 + 950000 500000>; + qcom,thermal-fcc-pps-cp + = <3700000 3700000 3700000 3700000 3700000 3700000 3700000 + 3700000 3700000 3600000 3400000 3200000 3000000 2200000 + 2000000 700000>; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp"; + qcom,battery-data = <&mtp_batterydata>; + dpdm-supply = <&usb2_phy0>; + qcom,distinguish-qc-class-ab; + qcom,lpd-disable; + qcom,sw-jeita-enable; + qcom,wd-bark-time-secs = <16>; +}; + +&ext_5v_boost { + status = "ok"; +}; + +&pm8150b_pdphy { + vbus-supply = <&ext_5v_boost>; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x33 0x70 + 0x2c 0x74>; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + cam_therm0 { + reg = ; + label = "cam_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + cam_therm1 { + reg = ; + label = "cam_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + cam_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + cam_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <2800>; + qcom,play-rate-us = <5102>; + + wf_0 { + /* CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_2 { + /* TICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_3 { + /* THUD */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_4 { + /* POP */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-brake-pattern = [03 03 01 00]; + qcom,wf-play-rate-us = <5102>; + }; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi new file mode 100644 index 000000000000..7877060e5e35 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/sm8150-audio-overlay.dtsi" + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2_EXT_0", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC2_EXT_1", "MIC BIAS1", + "MIC BIAS1", "Headset Mic2", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC4", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS4", + "MIC BIAS4", "Analog Mic5"; + + qcom,uart-audio-sw-gpio = <&sbu_uart_en>; + qcom,adc2-switch-gpio = <&adc2_switch_gpio>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,fsa4476-gpio-support = <1>; + qcom,usbc-analog-en1-gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2-gpio = <&tlmm 58 0>; + + pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", + "quat_tdm_enable", "quat_tdm_disable", + "aud_active", "aud_sleep"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; + pinctrl-4 = <&wcd_usbc_analog_en2_active>; + pinctrl-5 = <&wcd_usbc_analog_en2_idle>; +}; + +&soc { + sbu_uart_en: msm_cdc_pinctrl@25 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sbu_uart_en_active>; + pinctrl-1 = <&sbu_uart_en_idle>; + }; + + adc2_switch_gpio: msm_cdc_pinctrl@142 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&adc2_switch_gpio_active>; + pinctrl-1 = <&adc2_switch_gpio_idle>; + }; + + wcd_usbc_analog_en1_gpio: msm_cdc_pinctrl@49 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en1_active>; + pinctrl-1 = <&wcd_usbc_analog_en1_idle>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-pinctrl.dtsi new file mode 100644 index 000000000000..7aeb99e672df --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-pinctrl.dtsi @@ -0,0 +1,539 @@ +/*for xiaomi pinctrl*/ +&tlmm { + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio122", "gpio12"; + function = "gpio"; + }; + config { + pins = "gpio122", "gpio12"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + config { + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + idt { + idt_int_active: idt_int_active { + /* active state */ + mux { + /* GPIO 78 idt Read Interrupt */ + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_int_suspend: idt_int_suspend { + /* sleep state */ + mux { + /* GPIO 78 idt Read Interrupt */ + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_enable_active: idt_enable_active { + /* active state */ + mux { + /* GPIO 36 idt enable pin */ + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + idt_enable_suspend: idt_enable_suspend { + /* sleep state */ + mux { + /* GPIO 36 idt enable pin */ + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + adc2_switch_gpio_ctrl { + adc2_switch_gpio_idle: adc2_switch_idle { + mux { + pins = "gpio142"; + function = "gpio"; + }; + config { + pins = "gpio142"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + adc2_switch_gpio_active: adc2_switch_active { + mux { + pins = "gpio142"; + function = "gpio"; + }; + config { + pins = "gpio142"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + sbu_uart_en_ctrl { + sbu_uart_en_idle: uart_audio_en_idle { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + sbu_uart_en_active: uart_audio_en_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + ai_key_ctrl { + ai_key_active_default: ai_key_active { + mux { + pins = "gpio97"; + function = "gpio"; + }; + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + + }; + + ai_key_idle_default: ai_key_idle { + mux { + pins = "gpio97"; + function = "gpio"; + }; + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + }; + + pcie1 { + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio103"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio103"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + +}; +//camera voltage start +&cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio30", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio59"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio30", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio59"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +//camera voltage end diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..3f716ecc360a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150-camera-sensor-mtp.dtsi @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux1: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + wled-flash-support; + flash-source = <&wled_flash>; + torch-source = <&wled_torch>; + switch-source = <&wled_switch>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + camera_viodd_ldo: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "camera_viodd_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 132 0>; + vin-supply = <&pm8150_s4>; + }; + + actuator_rear_regulator: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "actuator_rear_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 24 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_rear_aux_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "actuator_rear_aux_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 152 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_ultra_ldo: gpio-regulator@3 { + compatible = "regulator-fixed"; + reg = <0x03 0x00>; + regulator-name = "actuator_ultra_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 95 0>; + vin-supply = <&pm8150l_bob>; + }; +}; + +&cam_cci1 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_aux_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_front: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_aux_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_ultra_rear: qcom,actuator@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&actuator_ultra_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150_s5>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1904000 2856000 0>; + rgltr-max-voltage = <1800000 2040000 3008000 0>; + rgltr-load-current = <180000 112000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 59 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150_s5>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1904000 2856000 0>; + rgltr-max-voltage = <1800000 2040000 3008000 0>; + rgltr-load-current = <180000 112000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 59 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_ultra: qcom,eeprom@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,eeprom"; + qcom,slave-addr = <0xa0>; + qcom,num-blocks = <1>; + qcom,page0 = <0 0 0 0 0 0 >; + qcom,poll0 = <0 0 0 0 0 0>; + qcom,mem0 = <8192 0x0 2 0 1 0>; + qcom,cam-power-seq-type = "cam_vio"; + qcom,cam-power-seq-val = <1>; + qcom,cam-power-seq-cfg-val = <1>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 300000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_iris>; + gpios = <&tlmm 13 0>,//mclk + <&tlmm 28 0>,//reset + <&tlmm 94 0>;//vana,vdig + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VDIG3"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 3000000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 30000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>,//mclk + <&tlmm 54 0>,//reset + //<&tlmm 132 0>,//vio + <&tlmm 118 0>;//vana,vidg + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150_s5>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1904000 2856000 0>; + rgltr-max-voltage = <1800000 2040000 3008000 0>; + rgltr-load-current = <180000 112000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 59 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux1>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vdig-supply = <&pm8150_l17>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 3000000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 300000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 16 0>,//mclk + <&tlmm 23 0>,//reset + <&tlmm 29 0>;//vana,vdig + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + //led-flash-src = <&led_flash_front>; + cam_vio-supply = <&camera_viodd_ldo>; + //cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 3000000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 30000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>,//mclk + <&tlmm 54 0>,//reset + //<&tlmm 132 0>,//vio + <&tlmm 118 0>;//vana,vidg + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + +qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_ultra_rear>; + eeprom-src = <&eeprom_rear_ultra>; + led-flash-src = <&led_flash_rear_aux2>; + cam_vio-supply = <&camera_viodd_ldo>; + //cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 300000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_iris>; + gpios = <&tlmm 13 0>,//mclk + <&tlmm 28 0>,//reset + <&tlmm 94 0>;//vana,vdig + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VDIG3"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi new file mode 100644 index 000000000000..5a3a024b5cff --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi @@ -0,0 +1,697 @@ +/* +this file is for attribution only of cepheus +And public attribution of xiaomi platforms(like F1 and so and) +*/ +#include "cepheus-pinctrl.dtsi" +#include "../common/xiaomi-sm8150-common.dtsi" +#include "cepheus-sm8150-camera-sensor-mtp.dtsi" + +#include "../common/smb1390.dtsi" + +&vendor { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "../common/battery/batterydata-F1-atl-3300mah.dtsi" + #include "../common/battery/batterydata-F1-coslight-3300mah.dtsi" + #include "../common/battery/fg-gen4-batterydata-alium-3600mah.dtsi" + }; +}; + +&pm8150b_fg { + qcom,battery-data = <&mtp_batterydata>; + qcom,rapid-soc-dec-en; + qcom,fg-sys-term-current = <(-400)>; + qcom,fg-cutoff-voltage = <3400>; + qcom,fg-cutoff-current = <200>; + qcom,fg-empty-voltage = <3100>; + qcom,fg-batt-temp-delta = <6>; + qcom,fg-force-load-profile; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <1>; + qcom,usb-icl-ua = <2800000>; + qcom,fcc-max-ua = <4800000>; + qcom,fv-max-uv = <4400000>; + qcom,dc-icl-ua = <1000000>; + qcom,auto-recharge-soc = <99>; + qcom,chg-term-src = <1>; + qcom,chg-term-current-ma = <(-220)>; + qcom,thermal-mitigation = <3000000 2800000 2600000 2400000 2200000 2100000 2000000 + 1800000 1600000 1500000 1400000 1200000 1000000 900000 + 800000 500000>; + qcom,thermal-mitigation-icl + = <2800000 2700000 2600000 2400000 2400000 2400000 2400000 + 2400000 2400000 2100000 1900000 1700000 1500000 1300000 + 1000000 750000>; + qcom,thermal-mitigation-dcp + = <1800000 1800000 1800000 1800000 1800000 1800000 1800000 + 1800000 1800000 1700000 1600000 1400000 1200000 1100000 + 1100000 1000000>; + qcom,thermal-mitigation-qc2 + = <1500000 1500000 1500000 1500000 1450000 1400000 1350000 + 1300000 1300000 1200000 1000000 900000 850000 750000 + 650000 500000>; + qcom,thermal-fcc-qc3-normal + = <3200000 3000000 2800000 2600000 2500000 2400000 2300000 + 2200000 2100000 1800000 1600000 1400000 1200000 1000000 + 750000 750000>; + qcom,thermal-fcc-qc3-cp + = <3600000 3600000 3600000 3600000 3200000 3200000 3200000 + 3200000 3100000 2800000 2400000 2200000 2000000 1300000 + 750000 700000>; + qcom,thermal-fcc-qc3-classb-cp + = <4800000 4700000 4600000 4500000 4400000 4200000 4200000 + 4200000 4000000 3600000 3400000 3200000 3000000 2200000 + 1000000 700000>; + qcom,thermal-mitigation-pd-base + = <3000000 2800000 2600000 2500000 2500000 2500000 2500000 + 2500000 2500000 2400000 2200000 2000000 1600000 1300000 + 1000000 500000>; + qcom,thermal-fcc-pps-cp + = <4800000 4700000 4600000 4500000 4400000 4200000 4200000 + 4200000 4000000 3600000 3400000 3200000 3000000 2200000 + 1000000 750000>; + qcom,thermal-mitigation-dc + = <2100000 2000000 1800000 1600000 1400000 1200000 1100000 + 1000000 900000 800000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-epp + = <1200000 1200000 1200000 1100000 1100000 1000000 1000000 + 1000000 900000 700000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-bpp-qc3 + = <1400000 1300000 1200000 1200000 1100000 1000000 900000 + 800000 700000 700000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-bpp-qc2 + = <1100000 1100000 1100000 1100000 1100000 1000000 1000000 + 1000000 700000 700000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-bpp + = <800000 800000 800000 800000 800000 800000 800000 + 800000 800000 700000 700000 600000 500000 400000 + 300000 200000>; + + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp"; + qcom,battery-data = <&mtp_batterydata>; + dpdm-supply = <&usb2_phy0>; + qcom,distinguish-qc-class-ab; + qcom,lpd-disable; + qcom,sw-jeita-enable; + qcom,wd-bark-time-secs = <16>; + qcom,support-wireless; + qcom,dynamic-fv-enable; +}; + +&ext_5v_boost { + status = "ok"; +}; + +&pm8150b_pdphy { + vbus-supply = <&ext_5v_boost>; +}; + +&qupv3_se4_i2c { + status = "ok"; + tas2557@4c { + compatible = "ti,tas2557"; + reg = <0x4c>; + //ti,cdc-reset-gpio = <&tlmm 59 0>; + ti,irq-gpio = <&tlmm 60 0>; + ti,i2s-bits = <16>; + ti,bypass-tmax = <0>; + }; + + fsa4480@43 { + status = "disabled"; + }; + + cs35l41@40 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + cs,cdc-reset-gpio = <&tlmm 89 0x01>; + reg = <0x40>; + pinctrl-names = "cs35l41_irq_default"; + pinctrl-0 = <&cs35l41_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <10 8>; + + cirrus,temp-warn_threshold = <3>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; + }; + +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x84 0x70 + 0x2c 0x74>; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&soc { + touch_vddio_vreg: touch_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 84 0>; + }; + + vdd_boost_vreg: vdd_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-always-on; + gpio = <&pm8150b_gpios 5 0>; + }; + + disp_vci_vreg: disp_vci_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 21 0>; + }; + + fingerprint_goodix { + compatible = "goodix,fingerprint"; + goodix,gpio-reset = <&tlmm 37 0x0>; + goodix,gpio-irq = <&tlmm 120 0x0>; + fp-gpio-pwr = <&tlmm 125 0>; + status = "ok"; + }; + + gpio_keys { + pinctrl-0 = <&ai_key_active_default>; + ai_key { + label = "ai_key"; + gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <39>; + gpio-key,level-trigger; + }; + }; + + xiaomi_touch { + compatible = "xiaomi-touch"; + status = "ok"; + touch,name = "xiaomi-touch"; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2008>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + vdd-supply = <&touch_vddio_vreg>; + avdd-supply = <&pm8150l_l1>; + fts,pwr-reg-name = "avdd"; + fts,bus-reg-name = "vdd"; + fts,irq-gpio = <&tlmm 122 0x2008>; + fts,irq-gpio-name = "fts_irq"; + fts,reset-gpio-enable; + fts,reset-gpio = <&tlmm 12 0x00>; + fts,reset-gpio-name = "fts_rst"; + fts,irq-flags = <0x2008>; /* IRQF_ONESHOT | IRQF_TRIGGER_LOW */ + fts,x-max = <1080>; + fts,y-max = <2340>; + fts,default-fw-name = "st_fts_f1.ftb"; + fts,config-array-size = <1>; + fts,dump-click-count; + fts,cfg_0 { + fts,tp-vendor = <0x48>; + fts,fw-name = "st_fts_f1.ftb"; + fts,limit-name = "stm_fts_production_limits.csv"; + fts,clicknum-file-name = "fts+sdc"; + }; + }; +}; + +&qupv3_se4_i2c { + status = "ok"; + idtp9220: idtp9220@3b { + compatible = "idt,p9220"; + reg = <0x3b>; + idt,irq = <&tlmm 90 0x00>; + idt,enable = <&tlmm 104 0x00>; + idt,wpc-det = <&pm8150b_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "idt_active", "idt_suspend"; + pinctrl-0 = <&power_good_default>; + pinctrl-1 = <&idt_int_active &idt_enable_active>; + pinctrl-2 = <&idt_int_suspend &idt_enable_suspend>; + }; +}; + + +&qupv3_se1_spi { + status = "ok"; + irled@0 { + compatible = "ir-spi"; + reg = <0x0>; + status = "ok"; + spi-max-frequency = <19200000>; + }; +}; + +&pm8150l_lpg { + qcom,lut-patterns = <0 1 2 3 4 5 7 9 11 13 15 + 13 11 9 7 5 4 3 2 1 0>; +}; + +&pwm_lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; +}; + +&red_led { + label = "white"; +}; + +&green_led { + status = "disabled"; +}; + +&blue_led { + status = "disabled"; +}; + +&sde_dsi { + vcie-supply = <&disp_vci_vreg>; +}; + +&dsi_samsung_fhd_ea8076_f1mp_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; +}; + +&dsi_samsung_fhd_ea8076_f1p2_2_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; +}; + +&dsi_samsung_fhd_ea8076_f1p2_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + cam_therm0 { + reg = ; + label = "cam_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + cam_therm1 { + reg = ; + label = "cam_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + cam_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + cam_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <2800>; + qcom,play-rate-us = <5102>; + + wf_0 { + /* CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_2 { + /* TICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_3 { + /* THUD */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_4 { + /* POP */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-brake-pattern = [03 03 01 00]; + qcom,wf-play-rate-us = <5102>; + }; +}; + +&soc { + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi_cp"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-E5G-coslight-3700mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-E5G-coslight-3700mah.dtsi new file mode 100644 index 000000000000..ff2a37519ffd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-E5G-coslight-3700mah.dtsi @@ -0,0 +1,136 @@ + +qcom,3811462_xiaomi_bm3gcos_3700mah_slave_jan3rd2019 { + qcom,profile-revision = <24>; + /* #3811462_Xiaomi_BM3Gcos_3700mAh_Slave_Jan3rd2019*/ + qcom,fastchg-current-ma = <3700>; + qcom,jeita-fcc-ranges = <0 50 370000 + 51 100 1110000 + 101 150 1850000 + 151 450 3700000 + 451 580 1850000>; + qcom,jeita-fv-ranges = <0 50 4450000 + 51 100 4450000 + 101 150 4450000 + 151 450 4450000 + 451 580 4100000>; + qcom,max-voltage-uv = <4450000>; + qcom,fg-cc-cv-threshold-mv = <4440>; + qcom,nom-batt-capacity-mah = <3800>; + qcom,batt-id-kohm = <100>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "e5g_cos"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0x4a 0x15 0x95 0x12>; + qcom,rslow-low-coeffs = <0x9f 0x06 0x70 0x1a>; + qcom,checksum = <0xB9FD>; + qcom,gui-version = "PM855GUI - 1.0.0.13"; + qcom,fg-profile-data = [ + 09 00 99 EA + EF ED 05 F2 + B6 07 00 00 + 69 BD 45 83 + 01 80 15 8C + 8C 80 09 80 + 13 00 4A 15 + 95 12 1B 06 + EB F3 CE 07 + 32 00 76 EA + 01 E4 5B DA + D1 02 95 E5 + 67 BD 1E 2A + 26 0B 64 D3 + 60 00 4C 00 + 4F 00 43 00 + 2F 00 31 00 + 35 00 3E 00 + 40 00 48 00 + 43 00 60 00 + 42 00 4F 00 + 58 00 52 00 + 4F 00 9C 00 + 6C 64 5B 00 + 5E 00 74 00 + 60 F0 57 00 + 5F 00 83 10 + 67 10 67 00 + AD 20 76 40 + 68 60 64 09 + 71 00 D8 00 + C3 1E 6D 0E + C1 03 23 04 + 82 1C 36 0B + 8E 0D F4 22 + E4 1A 5B 42 + 23 5C 46 02 + 5A 11 33 1F + ED 05 61 0A + 6C FE C8 1C + 49 FA 24 05 + 69 03 2B 17 + FE 23 76 44 + 26 52 6A 13 + 40 1F F7 ED + 4C E2 0F ED + DE 1C 4D E3 + FB 04 C5 BB + A7 17 66 83 + 37 85 1F A3 + 7C A8 09 80 + 54 FA BF 0D + 8F FA 91 04 + 00 00 D7 D5 + 66 EA 02 10 + 5D E2 7B CC + 41 01 0F F0 + BF BC 91 03 + CD 04 E6 00 + CE 07 32 00 + 81 01 A3 02 + 2F 05 29 02 + F7 02 F3 05 + C3 06 AA 02 + F0 03 50 00 + 3F 00 41 00 + 40 64 40 00 + 3D 08 40 10 + 3C 08 3F 00 + 54 00 79 08 + 5C 08 48 00 + 58 28 58 50 + 61 70 6F 07 + 4F 00 57 00 + 57 08 67 00 + FF 00 57 00 + 51 10 5F 10 + 61 00 78 28 + 91 48 5D 58 + 5D 0D 50 00 + 5B 00 FF 08 + D8 00 B5 22 + 03 05 BD 12 + A2 15 3F 1D + 60 22 F4 4C + 6D 5B 93 18 + D0 03 03 04 + D6 02 7D 0E + 3F 0A 43 20 + D8 04 34 03 + 96 05 D3 1C + 04 03 E9 05 + 58 02 74 18 + 0A 02 AF 05 + A5 03 6B 00 + A0 1F 54 05 + 16 03 80 05 + A6 1C 56 03 + 7F 05 03 03 + 7E 18 C6 03 + F2 05 1D 03 + 5F 00 88 01 + C0 00 FA 00 + 67 0F 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-atl-3300mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-atl-3300mah.dtsi new file mode 100644 index 000000000000..e749822f0db0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-atl-3300mah.dtsi @@ -0,0 +1,156 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,scud { + qcom,profile-revision = <24>; + /* #3675702_Xiaomi_F1sun_3300mAh_averaged_MasterSlave_Oct22nd2018*/ + qcom,fastchg-current-ma = <4800>; + qcom,jeita-fcc-ranges = <0 50 300000 + 51 100 1600000 + 101 150 3200000 + 151 450 4800000 + 451 580 1600000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 580 4100000>; + qcom,step-chg-ranges = <3600000 4200000 3000000 + 4201000 4300000 3000000 + 4301000 4340000 2500000>; + qcom,dynamic-fv-ranges = <0 100 4400000 + 101 200 4380000 + 201 300 4360000 + 301 400 4340000 + 401 500 4340000>; + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,nom-batt-capacity-mah = <3300>; + qcom,batt-id-kohm = <68>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "f1_atl"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0x85 0x01 0x71 0x13>; + qcom,rslow-low-coeffs = <0xc6 0x15 0x65 0x02>; + qcom,checksum = <0xBE6A>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + A9 1F 09 EA + 30 D4 F1 DA + 38 D5 00 00 + 5A BD 85 8A + FA 87 7F A4 + 75 92 06 81 + 1B FC 85 01 + 71 13 39 FC + 86 01 CE 1F + 32 0A 5D EB + DA ED B1 D4 + 2D 0A 69 D4 + 27 BD E8 1A + AB FB 8F BA + 60 00 4E FC + 47 FD 44 F4 + 33 33 30 10 + 35 0B 43 00 + 40 01 43 00 + 43 00 60 00 + 37 00 3C 00 + 46 00 40 00 + 39 00 76 00 + 5C 64 46 00 + 3F 00 3D 08 + 60 00 4C 00 + 49 00 57 10 + 4D 10 47 00 + 86 28 5E 48 + 4F 60 46 0D + 4E 00 D8 F8 + FE 1F 0C 0D + D4 FA 17 06 + 89 1C 32 0B + C5 0D 67 2A + 18 17 85 42 + 1E 5D 45 02 + 6C 10 36 1F + 09 04 31 0A + 25 FD DD 1C + 05 02 A3 05 + BE 02 3F 17 + 1C 22 05 44 + 91 52 70 12 + 60 1F DE E5 + 4D CA E9 A4 + E5 1C 7D C9 + 8C 05 08 BB + 1C 17 D9 8B + BF 84 BF 93 + 83 A0 09 80 + D3 03 01 05 + 21 FC 8D FA + 00 F8 59 D5 + FF EA F6 07 + DD F3 10 CD + 92 18 16 F0 + 2F D7 26 02 + 57 05 2B 02 + CE 01 32 00 + 15 03 28 03 + D9 05 44 07 + 43 02 94 04 + 55 03 8F 05 + 51 03 49 00 + 3A 00 42 00 + 43 64 48 00 + 4C 00 42 08 + 49 00 4A 00 + 49 00 3B 10 + 3A 10 3A 00 + 4A 20 4C 48 + 56 58 64 0E + 42 00 4D 00 + 58 08 61 00 + 50 00 3F 00 + 3F 10 4F 10 + 4C 00 5B 20 + 6D 40 48 58 + 54 0F 59 00 + 50 00 31 08 + D8 00 9F 20 + C9 04 F1 0A + ED 0D D7 1C + 19 23 F5 45 + 17 52 71 18 + D6 03 FA 05 + F6 02 73 12 + 3F 0A DC 1F + 6D 05 A4 02 + 1C 06 C0 1C + 0E 03 EC 05 + 44 02 7A 18 + 81 03 8E 04 + 5B 02 6A 00 + 2D 20 03 05 + FC 02 C3 05 + E3 1C 1C 02 + BA 05 80 02 + 92 18 EF 02 + 90 05 CD 02 + 7C 00 3B 01 + C0 00 FA 00 + BB 0C 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-coslight-3300mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-coslight-3300mah.dtsi new file mode 100644 index 000000000000..6af436c42516 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F1-coslight-3300mah.dtsi @@ -0,0 +1,156 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,coslight { + qcom,profile-revision = <24>; + /* #3675676_Xiaomi_F1cos_3300mAh_averaged_MasterSlave_Oct22nd2018*/ + qcom,fastchg-current-ma = <4800>; + qcom,jeita-fcc-ranges = <0 50 300000 + 51 100 1600000 + 101 150 3200000 + 151 450 4800000 + 451 580 1600000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 580 4100000>; + qcom,step-chg-ranges = <3600000 4200000 3000000 + 4201000 4300000 3000000 + 4301000 4340000 2500000>; + qcom,dynamic-fv-ranges = <0 100 4400000 + 101 200 4380000 + 201 300 4360000 + 301 400 4340000 + 401 500 4340000>; + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,nom-batt-capacity-mah = <3300>; + qcom,batt-id-kohm = <100>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "f1_cos"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xe4 0x04 0x3a 0x12>; + qcom,rslow-low-coeffs = <0x21 0x15 0x15 0x06>; + qcom,checksum = <0xC822>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + A9 1F 6C EA + 8F E5 33 EA + 8C E5 00 00 + C4 BC AC 8A + FC 87 EC 82 + 71 87 10 80 + 20 FC E4 04 + 3A 12 C9 04 + 0F 02 CE 1F + 32 0A FB EB + 65 ED 6E DC + F6 0A FA DC + 38 C5 3A 12 + 84 02 D1 D3 + 60 00 36 FC + 3D FD 3E F4 + 38 33 30 10 + 33 0B 37 00 + 3F 01 47 00 + 4D 00 60 00 + 36 00 3B 00 + 3D 00 38 00 + 35 00 6A 00 + 4D 64 42 00 + 3F F8 42 00 + 60 F0 55 00 + 5E 00 84 08 + 64 08 5D 00 + BB 20 7D 40 + 67 58 60 10 + 6C 00 D8 F8 + 05 1F EF 04 + 76 EB 6A 04 + D2 1C 6D 0A + F9 0C 5E 2B + 96 18 55 4B + CD 5C 20 02 + 6A 0F 86 1E + E3 05 A8 02 + 42 04 C5 1C + 78 02 9C 04 + FD 03 AC 17 + 1E 22 D0 45 + 19 5B 5F 11 + AB 1E C3 EE + FC CA 59 C7 + DE 1C A1 C9 + E4 04 AA BB + 92 17 D8 93 + 78 84 37 A2 + 78 A0 09 80 + 46 02 82 04 + 66 05 FF FB + 00 F8 68 DC + 06 EA F3 FF + 77 E3 FA C4 + 15 18 16 00 + 0E E7 FE 02 + F3 05 CB 02 + CE 01 32 00 + 15 03 CA 02 + D1 05 5B 03 + 27 04 F4 03 + 9D 03 94 02 + D2 05 54 00 + 3F 00 40 00 + 44 64 47 00 + 46 E8 47 F8 + 49 E8 48 00 + 4A 00 45 10 + 4F 10 3E 00 + 49 28 4B 48 + 53 58 62 0D + 40 00 4E F8 + 52 00 58 F8 + 4D 00 47 00 + 43 10 54 10 + 52 00 66 28 + 7E 48 4D 60 + 5D 0D 5E 00 + 50 F8 36 00 + D8 F0 A7 1E + 12 04 6F 0A + 87 0A E3 1C + 43 23 A7 45 + 95 5A 8C 18 + 08 02 B3 05 + 9E 03 5A 10 + 3F 0A 6B 1F + 33 04 E7 03 + D7 05 B6 1C + 4B 03 A7 05 + 92 02 6D 18 + 15 02 8D 05 + 00 02 64 00 + 05 1F EF 04 + 76 03 6A 04 + D2 1C 6D 02 + F9 04 5E 03 + 96 18 55 03 + CD 04 20 02 + 6A 00 56 01 + C0 00 FA 00 + F0 0C 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-gyu-4000mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-gyu-4000mah.dtsi new file mode 100644 index 000000000000..ec564aafcb64 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-gyu-4000mah.dtsi @@ -0,0 +1,159 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,gyu{ + qcom,profile-revision = <24>; + /* #3927828_Xiaomi_F11gyu_4000mAh_averaged_MasterSlave_2019*/ + qcom,fastchg-current-ma = <5100>; + qcom,jeita-fcc-ranges = <0 50 390000 + 51 100 1100000 + 101 150 2700000 + 151 450 5100000 + 451 580 1900000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 580 4100000>; + qcom,step-chg-ranges = <3000000 3100000 1000000 + 3101000 3200000 1000000 + 3201000 3300000 1000000 + 3301000 4200000 5100000 + 4201000 4400000 4000000>; + qcom,dynamic-fv-ranges = <0 100 4400000 + 101 200 4380000 + 201 300 4360000 + 301 400 4340000 + 401 500 4340000>; + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,nom-batt-capacity-mah = <4000>; + qcom,batt-id-kohm = <100>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "f11_gyu"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0x12 0x0c 0x6a 0x02>; + qcom,rslow-low-coeffs = <0x4e 0x15 0x4a 0x06>; + qcom,checksum = <0xD688>; + qcom,gui-version = "PM855GUI - 1.0.0.13"; + qcom,fg-profile-data = [ + 09 00 46 00 + 2D DC 99 E3 + FB E5 00 00 + 7C BD 24 8A + FC 87 02 8D + E7 82 FD 87 + 22 00 12 0C + 6A 02 58 05 + A1 FB CE 07 + 32 00 5F EB + DF ED 2F CD + C1 02 4D D3 + 36 AB 44 1A + E7 FA 52 BD + 60 00 39 00 + 3F 00 41 00 + 39 00 34 00 + 35 00 3B 00 + 43 00 4F 00 + 5A 00 60 00 + 3C 00 3F 00 + 3D 00 36 00 + 33 00 5C 00 + 4D 64 43 00 + 43 00 41 08 + 60 00 52 00 + 4F 00 5B 10 + 4E 10 44 00 + 85 28 60 48 + 52 60 4C 0B + 4B 00 D8 00 + C9 1F 69 0D + 60 02 AD 06 + 82 1C 35 0B + C5 0D 5C 22 + 13 17 F0 42 + 0B 54 A9 03 + 6C 12 36 1F + F4 FD 40 0A + 85 FE D8 1C + 1A 02 65 05 + 0B 0B 17 18 + 4D 23 2A 45 + 59 53 6D 12 + 12 1F 39 EC + 24 CA 2F C5 + D6 1C B4 C9 + 97 04 0B BA + BF 17 81 8B + F9 84 95 93 + 77 A0 09 80 + 16 FA 6D 04 + 24 02 05 02 + 00 F8 4C DD + C5 EA F8 FF + 07 E2 C2 BD + 78 18 16 F8 + B3 D5 38 02 + 85 06 1C 01 + CE 07 32 00 + 07 03 79 02 + 06 05 41 03 + 26 02 4F 04 + 63 02 89 02 + CD 05 53 00 + 3F 00 40 00 + 42 64 45 00 + 46 F8 47 00 + 49 00 47 00 + 49 00 41 08 + 4F 08 3F 00 + 46 20 49 48 + 50 58 5D 0E + 40 00 46 00 + 4E 08 56 F8 + 49 00 46 00 + 3B 10 48 10 + 4B 00 5C 28 + 6C 48 48 58 + 53 0D 4D 00 + 47 00 33 08 + D8 F8 8D 1F + 8F 04 56 0B + 35 0F F6 1C + CD 22 69 44 + AF 5B 96 18 + ED 03 D8 05 + 45 03 6E 0F + 3F 0A E4 1F + 64 05 A5 02 + 3F 04 BB 1C + 38 03 BC 05 + 7A 02 7F 18 + 0F 02 94 05 + F4 03 68 00 + 97 1F 99 05 + 99 02 31 04 + C2 1C A8 02 + 92 04 D5 03 + 96 18 66 03 + A4 04 4D 02 + 6B 00 58 01 + C0 00 FA 00 + A9 0F 00 00 + ]; +}; + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-sun-4000mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-sun-4000mah.dtsi new file mode 100644 index 000000000000..b446defee8ec --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/batterydata-F11-sun-4000mah.dtsi @@ -0,0 +1,159 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,sun { + qcom,profile-revision = <24>; + /* #3827828_Xiaomi_F11sun_4000mAh_averaged_MasterSlave_Jan23rd2019*/ + qcom,fastchg-current-ma = <5100>; + qcom,jeita-fcc-ranges = <0 50 390000 + 51 100 1100000 + 101 150 2700000 + 151 450 5100000 + 451 580 1900000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 580 4100000>; + qcom,step-chg-ranges = <3000000 3100000 1000000 + 3101000 3200000 1000000 + 3201000 3300000 1000000 + 3301000 4200000 5100000 + 4201000 4400000 4000000>; + qcom,dynamic-fv-ranges = <0 100 4400000 + 101 200 4380000 + 201 300 4360000 + 301 400 4340000 + 401 500 4340000>; + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,nom-batt-capacity-mah = <4000>; + qcom,batt-id-kohm = <68>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "f11_sun"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xae 0xe3 0x0e 0x13>; + qcom,rslow-low-coeffs = <0x58 0x15 0x1a 0xec>; + qcom,checksum = <0x585A>; + qcom,gui-version = "PM855GUI - 1.0.0.13"; + qcom,fg-profile-data = [ + 09 00 D1 E3 + 5B D4 39 DB + 83 D4 00 00 + F8 BD A8 83 + FB 87 01 A5 + 2A 9A 91 80 + 1D 00 AE E3 + 0E 13 FE 05 + 0C 02 CE 07 + 32 00 89 00 + 92 ED 75 E5 + EC 03 96 E4 + 7F C5 A6 13 + 1E 02 45 D2 + 60 00 44 00 + 42 00 42 00 + 38 00 32 00 + 37 00 3F 00 + 3F 00 43 00 + 45 00 60 00 + 31 00 35 00 + 3F 00 3A 00 + 34 00 63 00 + 52 64 42 00 + 3C 00 3C 08 + 60 F8 51 00 + 4B 00 53 10 + 44 10 40 00 + 70 28 54 48 + 4A 60 46 0D + 43 00 D8 00 + BC 1F 69 0D + 7E 02 E7 FC + 8C 1C 29 03 + CB 0D 62 22 + 95 17 4E 42 + 5F 55 12 02 + 6A 13 C5 1F + 68 05 9C 02 + 33 F6 EA 1C + 7B 03 72 04 + 0F 0A 81 17 + 71 23 42 45 + FF 52 7E 12 + A5 1E AF E6 + 68 CB 07 CC + D4 1C B9 D1 + 9C 04 0A B2 + D1 17 74 83 + 05 85 87 83 + 72 A0 09 80 + A4 03 9B FD + 7A FD 90 FA + 00 00 18 CC + 8B EB FB EF + EE E2 E0 C4 + B5 18 17 F0 + 92 D7 8D 03 + FB 05 5B 02 + CE 07 32 00 + 7F 01 46 05 + C4 05 C1 02 + B6 03 E6 05 + 48 03 1A 03 + 07 05 49 00 + 3D 00 43 00 + 44 64 49 00 + 4B 00 43 08 + 4A F8 49 00 + 48 00 3E 10 + 3E 10 39 00 + 44 28 47 48 + 51 60 5D 0D + 3E 00 49 00 + 4F 08 50 F8 + 3C 00 3F 00 + 39 10 45 10 + 45 00 57 20 + 62 40 45 58 + 4F 0F 45 00 + 39 F8 23 08 + D8 F8 F2 1F + 94 05 5B 0A + ED 0C C4 1C + 66 23 A2 45 + 80 52 65 18 + 20 02 80 05 + 0A 02 69 10 + 3F 0A D1 1F + 88 05 89 02 + 71 04 C1 1C + 0C 03 F4 05 + 36 02 7A 18 + 9E 03 51 04 + 9B 02 6A 00 + 4E 1F 0D 04 + 3F 02 DF 04 + C0 1C 9C 02 + C4 04 97 03 + 90 18 36 03 + 06 05 D4 03 + 6B 00 43 01 + C0 00 FA 00 + 8B 0F 00 00 + ]; +}; + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah.dtsi new file mode 100644 index 000000000000..cf398ae46599 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah.dtsi @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +qcom,alium_860_89032_0000_3600mah_averaged_masterslave_sep24th2018 { + /* #Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Sept24th2018*/ + qcom,max-voltage-uv = <4400000>; + qcom,fastchg-current-ma = <4800>; + qcom,jeita-fcc-ranges = <0 50 300000 + 51 100 1600000 + 101 150 3200000 + 151 450 4800000 + 451 580 1600000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 580 4100000>; + qcom,step-chg-ranges = <3600000 4200000 3000000 + 4201000 4300000 3000000 + 4301000 4340000 2500000>; + qcom,nom-batt-capacity-mah = <3300>; + qcom,batt-id-kohm = <300>; + /* COLD = 0 DegC, HOT = 45 DegC */ + /* qcom,jeita-hard-thresholds = <0x58cd 0x20b8>; */ + /* COOL = 10 DegC, WARM = 40 DegC */ + /* qcom,jeita-soft-thresholds = <0x4ccc 0x25e3>; */ + /* COLD hys = 13 DegC, WARM hys = 37 DegC */ + /*qcom,jeita-soft-hys-thresholds = <0x48d4 0x2943>; + qcom,jeita-soft-fcc-ua = <2500000 2500000>; + qcom,jeita-soft-fv-uv = <4250000 4250000>;*/ + qcom,ocv-based-step-chg; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,battery-type = "itech_3000mah"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah_E5G.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah_E5G.dtsi new file mode 100644 index 000000000000..f4dd321ba524 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-alium-3600mah_E5G.dtsi @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +qcom,alium_860_89032_0000_3600mah_averaged_masterslave_sep24th2018 { + /* #Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Sept24th2018*/ + qcom,max-voltage-uv = <4450000>; + qcom,fastchg-current-ma = <3700>; + qcom,jeita-fcc-ranges = <0 50 370000 + 51 100 1110000 + 101 150 1850000 + 151 450 3700000 + 451 580 1850000>; + qcom,jeita-fv-ranges = <0 50 4450000 + 51 100 4450000 + 101 150 4450000 + 151 450 4450000 + 451 580 4100000>; + qcom,nom-batt-capacity-mah = <3800>; + qcom,batt-id-kohm = <100>; + /* COLD = 0 DegC, HOT = 45 DegC */ + /* qcom,jeita-hard-thresholds = <0x58cd 0x20b8>; */ + /* COOL = 10 DegC, WARM = 40 DegC */ + /* qcom,jeita-soft-thresholds = <0x4ccc 0x25e3>; */ + /* COLD hys = 13 DegC, WARM hys = 37 DegC */ + /*qcom,jeita-soft-hys-thresholds = <0x48d4 0x2943>; + qcom,jeita-soft-fcc-ua = <2500000 2500000>; + qcom,jeita-soft-fv-uv = <4250000 4250000>;*/ + qcom,ocv-based-step-chg; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4440>; + qcom,battery-type = "itech_3700mah"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-nabu-sunwoda-8720mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-nabu-sunwoda-8720mah.dtsi new file mode 100644 index 000000000000..c152f8ed1934 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-nabu-sunwoda-8720mah.dtsi @@ -0,0 +1,153 @@ +qcom,5119583_xiaomi_k82_p86120aa1_8720mah_averaged_masterslave_apr8th2021 { + qcom,profile-revision = <24>; + /* #5119583_XIAOMI_K82_8720mAH_averaged_MasterSlave_Apr8th2021*/ + qcom,max-voltage-uv = <4480000>; + qcom,fastchg-current-ma = <5900>; + qcom,jeita-fcc-ranges = <(-100) 0 820000 + 1 50 820000 + 51 100 2500000 + 101 150 5964000 + 151 480 5900000 + 481 590 4260000>; + qcom,jeita-fv-ranges = <(-100) 0 4450000 + 1 50 4450000 + 51 100 4450000 + 101 150 4450000 + 151 480 4480000 + 481 600 4100000>; +// qcom,step-chg-ranges = <3001000 4150000 6000000 +// 4150001 4230000 6000000 +// 4230001 4350000 6000000 +// 4350001 4400000 6000000 +// 4400001 4430000 6000000 +// 4430001 4480000 4000000>; +// qcom,taper-fcc; + qcom,jeita-too-hot = <590>; + qcom,jeita-too-cold = <(-100)>; + qcom,jeita-warm-th= <480>; + qcom,jeita-cool-th= <150>; + qcom,use-bq-pump; + mi,six-pin-battery; + qcom,ffc-low-temp-term-current-ma = <(-1278)>; + qcom,ffc-high-temp-term-current-ma = <(-1363)>; + qcom,fg-cc-cv-threshold-mv = <4450>; + qcom,fg-ffc-cc-cv-threshold-mv = <4480>; + qcom,nom-batt-capacity-mah = <8720>; + qcom,batt-id-kohm = <10>; + qcom,battery-beta = <3800>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "K82_sunwoda_8720mah"; + qcom,therm-coefficients = <0x2319 0xcb5 0xdb70 0xc48e 0x856b>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0x33 0xfc 0xe8 0x12>; + qcom,rslow-low-coeffs = <0x36 0x05 0xc4 0x12>; + qcom,checksum = <0xBEEA>; + qcom,gui-version = "PM855GUI - 1.0.0.14"; + qcom,fg-profile-data = [ + 09 00 9B DB + 1B D5 75 DA + 68 D5 00 00 + 99 B5 42 83 + FA 87 1E 93 + 02 8D EA 87 + 18 00 33 FC + E8 12 C5 04 + 50 02 CE 07 + 32 00 11 EA + BB E4 48 E3 + 5E 0B B5 E2 + 1D AC 12 22 + C9 FA 3A CC + 60 00 40 00 + 3F 00 38 00 + 2C 00 2D 00 + 3A 00 46 00 + 41 00 46 00 + 3E 00 60 00 + 44 00 3B 00 + 4B 00 47 00 + 3D 00 8C 00 + 59 64 4B 00 + 49 00 4C 08 + 60 00 4C 00 + 4F 00 6F 10 + 5E 10 57 00 + A3 28 6B 48 + 5B 60 54 0C + 58 00 D8 08 + 06 20 B1 14 + 6F 0B 51 FD + 4B 1C AE 03 + 5B 05 F7 2A + B6 17 51 42 + 2A 5D 68 02 + 66 12 54 23 + AD 0C DE 12 + 9D 0D F3 1C + 21 FB 58 FD + 50 03 FE 16 + 09 2A 76 44 + 18 5A 95 11 + 9E 24 29 DC + 21 C3 72 C5 + F3 1C 97 AA + FB 04 2D B2 + 0A 17 12 82 + 4A 84 43 8A + A4 90 09 80 + 48 03 13 05 + 87 02 D7 05 + 00 00 FB CD + 78 E2 FC 07 + 17 EA 39 CD + 1D 18 15 08 + 80 ED 35 03 + 76 05 A7 01 + CE 07 32 00 + 9E 01 EE 05 + 5C 05 1C 03 + D4 05 0E 02 + BD 03 9D 02 + C6 05 48 00 + 39 00 42 00 + 44 64 45 00 + 49 00 40 08 + 40 00 44 00 + 44 00 3B 10 + 3F 10 3F 00 + 53 28 54 48 + 57 58 62 0D + 43 00 48 00 + 52 08 54 00 + 43 00 47 00 + 49 10 59 10 + 51 00 5F 20 + 75 40 49 58 + 56 0F 5D 00 + 4C 08 31 10 + D8 08 FC 20 + 54 FC 6D 03 + 67 0D C7 1C + 62 23 C5 45 + 4B 52 63 18 + 0F 02 AC 05 + A9 03 72 12 + 3F 0A 6B 20 + 93 04 89 03 + 20 05 BE 1C + 3C 03 C0 05 + 85 02 77 18 + A0 03 51 04 + 9A 02 6A 00 + 35 22 4D 05 + 7A 02 EB 05 + FB 1C AF 03 + 82 04 0B 02 + 86 18 17 03 + 59 05 23 03 + 8A 00 92 00 + C0 00 FA 00 + F0 21 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-NVT-5160mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-NVT-5160mah.dtsi new file mode 100644 index 000000000000..732853672c91 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-NVT-5160mah.dtsi @@ -0,0 +1,153 @@ +qcom,xiaomi_j20s_nvt_5160mah_averaged_masterslave_aug26th2019 { + qcom,profile-revision = <24>; + /* #4174016_Xiaomi_J20S_5160mAh_averaged_MasterSlave_Aug26th2019*/ + qcom,max-voltage-uv = <4475000>; + qcom,fastchg-current-ma = <5900>; + qcom,jeita-fcc-ranges = <(-100) 0 500000 + 1 50 1000000 + 51 100 2500000 + 101 150 4000000 + 151 450 5900000 + 451 580 2500000>; + qcom,jeita-fv-ranges = <(-100) 0 4450000 + 1 50 4450000 + 51 100 4450000 + 101 150 4450000 + 151 450 4475000 + 451 600 4100000>; + qcom,step-chg-ranges = <3001000 4150000 5900000 + 4150001 4230000 5900000 + 4230001 4350000 5400000 + 4350001 4400000 5400000 + 4400001 4430000 5400000 + 4430001 4475000 4000000>; + qcom,taper-fcc; + qcom,jeita-too-hot = <590>; + qcom,jeita-too-cold = <(-100)>; + qcom,jeita-warm-th= <450>; + qcom,jeita-cool-th= <150>; + qcom,use-bq-pump; + mi,six-pin-battery; + qcom,ffc-low-temp-term-current-ma = <(-723)>; + qcom,ffc-high-temp-term-current-ma = <(-774)>; + qcom,fg-cc-cv-threshold-mv = <4440>; + qcom,fg-ffc-cc-cv-threshold-mv = <4490>; + qcom,nom-batt-capacity-mah = <5160>; + qcom,batt-id-kohm = <100>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "J20S_nvt_5160mah"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0x3c 0x05 0x2a 0x0b>; + qcom,rslow-low-coeffs = <0xe7 0x00 0x6a 0x12>; + qcom,checksum = <0x65B6>; + qcom,gui-version = "PM855GUI - 1.0.0.14"; + qcom,fg-profile-data = [ + 09 00 6B E2 + D8 DD C7 DB + FD DD 00 00 + FD B4 92 83 + FA 87 9C 80 + 06 8D 19 80 + 20 00 3C 05 + 2A 0B BF 04 + 44 02 CE 07 + 32 00 6C EA + 29 E4 A4 DB + C8 03 54 DD + 9F 86 4B 23 + 4D 0A 88 D5 + 60 00 41 00 + 45 00 3D 00 + 2E 00 30 00 + 39 00 43 00 + 40 00 44 00 + 3D 00 60 00 + 39 00 36 00 + 47 00 40 00 + 3A 00 79 00 + 52 64 45 00 + 46 00 47 10 + 60 00 47 00 + 4C 08 71 10 + 5C 10 53 00 + 99 28 6A 48 + 5B 60 53 0C + 4E 00 D8 08 + 7D 20 0B 14 + 03 0A AD FC + 36 1C 0D 02 + F5 0C 66 23 + FA 17 3F 42 + 28 5D 83 02 + 66 11 41 22 + 2B 0D 96 12 + D2 05 F0 1C + 6B 03 B5 04 + 05 02 B4 17 + CD 23 83 44 + 2F 5A 8A 11 + 0C 21 DE E5 + 15 C2 8D AC + E2 1C A2 C1 + 2C 05 92 B3 + 63 17 DF 83 + 8C 84 1A A2 + 87 A0 09 80 + 3C 02 5B 04 + 1C 05 54 FB + 00 00 5C BD + FC E2 FC 07 + 1D E2 D3 C5 + 10 18 19 00 + A7 E6 33 03 + 9A 05 1F 03 + CE 07 32 00 + 96 01 BE 05 + 0F 05 27 03 + 67 04 6E 03 + AE 02 2B 03 + 38 05 55 00 + 3A 00 42 00 + 44 64 46 00 + 4C 00 42 08 + 43 00 46 00 + 47 08 3B 10 + 43 10 3E 00 + 52 28 54 50 + 5A 68 64 0A + 47 00 4C 00 + 56 10 55 00 + 46 00 4B 00 + 45 10 59 10 + 52 00 62 20 + 77 40 4C 58 + 59 0E 5B 00 + 50 08 2E 10 + D8 08 83 20 + B0 04 4E 0B + 6B 0D 9F 1C + 02 22 0F 45 + 34 53 23 18 + D1 02 D7 05 + 4D 02 66 11 + 3F 0A D1 20 + 08 04 02 02 + 9E 04 C4 1C + 33 03 C8 05 + 7B 02 86 18 + B6 03 18 04 + DB 02 6C 00 + 04 22 59 05 + 7E 02 DD 05 + F3 1C 02 02 + F2 05 61 02 + 98 18 34 03 + 17 05 A4 03 + 85 00 C2 00 + C0 00 FA 00 + 64 14 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-sunwoda-5160mah.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-sunwoda-5160mah.dtsi new file mode 100644 index 000000000000..165a4be41364 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/battery/fg-gen4-batterydata-vayu-sunwoda-5160mah.dtsi @@ -0,0 +1,153 @@ +qcom,xiaomi_j20s_sunwoda_5160mah_averaged_masterslave_aug26th2019 { + qcom,profile-revision = <24>; + /* #4174016_Xiaomi_J20S_5160mAh_averaged_MasterSlave_Aug26th2019*/ + qcom,max-voltage-uv = <4475000>; + qcom,fastchg-current-ma = <5900>; + qcom,jeita-fcc-ranges = <(-100) 0 500000 + 1 50 1000000 + 51 100 2500000 + 101 150 4000000 + 151 450 5900000 + 451 580 2500000>; + qcom,jeita-fv-ranges = <(-100) 0 4450000 + 1 50 4450000 + 51 100 4450000 + 101 150 4450000 + 151 450 4475000 + 451 600 4100000>; + qcom,step-chg-ranges = <3001000 4150000 5900000 + 4150001 4230000 5900000 + 4230001 4350000 5400000 + 4350001 4400000 5400000 + 4400001 4430000 5400000 + 4430001 4475000 4000000>; + qcom,taper-fcc; + qcom,jeita-too-hot = <590>; + qcom,jeita-too-cold = <(-100)>; + qcom,jeita-warm-th= <450>; + qcom,jeita-cool-th= <150>; + qcom,use-bq-pump; + mi,six-pin-battery; + qcom,ffc-low-temp-term-current-ma = <(-723)>; + qcom,ffc-high-temp-term-current-ma = <(-774)>; + qcom,fg-cc-cv-threshold-mv = <4440>; + qcom,fg-ffc-cc-cv-threshold-mv = <4490>; + qcom,nom-batt-capacity-mah = <5160>; + qcom,batt-id-kohm = <100>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,battery-type = "J20S_sunwoda_5160mah"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0x71 0x04 0x9c 0x12>; + qcom,rslow-low-coeffs = <0x9d 0x15 0x4c 0x02>; + qcom,checksum = <0x7304>; + qcom,gui-version = "PM855GUI - 1.0.0.14"; + qcom,fg-profile-data = [ + 09 00 8B E2 + 99 D4 2B DB + 9D D4 00 00 + 95 B4 2D 83 + FD 87 E3 9D + 61 86 4B 80 + 24 00 71 04 + 9C 12 05 FC + EE F3 CE 07 + 32 00 B1 EA + FC ED 33 DA + 2E 12 37 DB + 8B BC 31 12 + E8 01 63 C5 + 60 00 49 00 + 4B 00 48 00 + 31 00 2F 00 + 37 00 40 00 + 3E 00 43 00 + 38 00 60 00 + 35 00 3B 00 + 4D 00 44 00 + 3A 00 71 00 + 57 64 49 00 + 44 08 40 10 + 60 08 47 00 + 43 08 58 10 + 55 10 45 00 + 8B 28 62 48 + 4E 60 44 0C + 41 00 D8 08 + 16 21 97 15 + 60 0A F9 FD + 1A 1C 20 02 + DF 04 70 23 + 0E 17 A9 42 + 9D 54 FF 02 + 69 15 B0 23 + 63 0C 28 13 + 48 05 F3 1C + 15 03 66 05 + 5F 03 EA 16 + 8C 23 5D 45 + AD 52 93 14 + 22 21 C4 E5 + 35 C2 3A B4 + D6 1C A9 C9 + 27 05 A1 B3 + 49 17 70 8B + 53 85 D9 9A + 86 A0 09 80 + 77 FA 99 FC + 29 FC 27 F2 + 00 F8 42 DC + 29 E2 FA F7 + B1 E2 77 BD + 44 18 1A 00 + 6D D4 D9 03 + 11 05 C3 02 + CE 07 32 00 + 01 03 C7 02 + 68 04 86 02 + 87 02 E1 05 + 38 02 43 01 + 69 04 46 00 + 38 00 44 00 + 44 64 48 00 + 4F 08 46 10 + 46 00 47 00 + 46 00 41 08 + 41 10 3D 00 + 53 20 52 40 + 5D 58 69 0F + 48 00 52 08 + 5E 10 62 00 + 4E 00 44 00 + 42 10 54 10 + 4B 00 5E 20 + 75 40 46 50 + 56 10 5E 00 + 5A 08 3B 10 + D8 08 3E 22 + 5A FD 5D 02 + 1E 0C C9 1C + 26 23 02 44 + 08 52 66 18 + 98 03 77 04 + 6B 02 7C 13 + 3F 0A CD 20 + F7 05 19 02 + 5E 04 A6 1C + 74 03 8E 05 + C0 02 65 18 + 4F 03 F7 04 + E4 03 6A 00 + EF 22 CB 04 + F1 02 67 05 + EB 1C E7 03 + 3E 04 34 02 + 89 18 E4 02 + A8 05 A0 02 + 8A 00 BF 00 + C0 00 FA 00 + 22 14 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-36-02-0a-lcd-dsc-vid.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-36-02-0a-lcd-dsc-vid.dtsi new file mode 100644 index 000000000000..7caf6f84bcac --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-36-02-0a-lcd-dsc-vid.dtsi @@ -0,0 +1,334 @@ +/* Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&mdss_mdp { + dsi_j20s_36_02_0a_video: qcom,mdss_dsi_j20s_36_02_0a_dsc_video { + qcom,mdss-dsi-panel-name = "xiaomi 36 02 0a video mode dsc dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "xiaomi 36 02 0a VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; + qcom,ulps-enabled; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <70>; + qcom,mdss-pan-physical-height-dimension = <154>; + qcom,mdss-dsi-tx-eot-append; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,disp-panel-offon-mode-enabled; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + /* qcom,mdss-dsi-qsync-min-refresh-rate = <60>; */ + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <120 90 60 50 48 30>; + + qcom,dispparam-enabled; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-front-porch = <67>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-v-back-porch = <30>; + qcom,mdss-dsi-v-front-porch = <33>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + /* DDIC Initical Code */ + 15 00 00 00 00 00 02 FF 24 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 4D 02 + 15 00 00 00 00 00 02 4E 30 + 15 00 00 00 00 00 02 4F 30 + 15 00 00 00 00 00 02 53 30 + 15 00 00 00 00 00 02 7A 01 + 15 00 00 00 00 00 02 7B 8C + 15 00 00 00 00 00 02 7D 05 + 15 00 00 00 00 00 02 80 05 + 15 00 00 00 00 00 02 81 05 + 15 00 00 00 00 00 02 A0 0C + 15 00 00 00 00 00 02 A2 0C + 15 00 00 00 00 00 02 A3 01 + 15 00 00 00 00 00 02 A4 05 + 15 00 00 00 00 00 02 A5 05 + 15 00 00 00 00 00 02 C4 80 + 15 00 00 00 00 00 02 C6 C0 + 15 01 00 00 00 00 02 E9 02 + 15 00 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 DA 00 + 15 00 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 F1 04 + 15 00 00 00 00 00 02 FF 2B + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 B7 08 + 15 00 00 00 00 00 02 B8 1A + 15 01 00 00 00 00 02 C0 04 + 15 00 00 00 00 00 02 FF F0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 1C 01 + 15 01 00 00 00 00 02 33 01 + /* CABC Setting */ + 15 00 00 00 00 00 02 FF 23 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 00 80 + 15 00 00 00 00 00 02 01 84 + 15 00 00 00 00 00 02 05 2D + 15 00 00 00 00 00 02 06 00 + 15 00 00 00 00 00 02 07 00 + 15 00 00 00 00 00 02 08 01 + 15 00 00 00 00 00 02 09 45 + 15 00 00 00 00 00 02 11 01 + 15 00 00 00 00 00 02 12 95 + 15 00 00 00 00 00 02 15 68 + 15 00 00 00 00 00 02 16 0B + 15 00 00 00 00 00 02 29 0A + 15 00 00 00 00 00 02 30 FF + 15 00 00 00 00 00 02 31 FE + 15 00 00 00 00 00 02 32 FD + 15 00 00 00 00 00 02 33 FB + 15 00 00 00 00 00 02 34 F8 + 15 00 00 00 00 00 02 35 F5 + 15 00 00 00 00 00 02 36 F3 + 15 00 00 00 00 00 02 37 F2 + 15 00 00 00 00 00 02 38 F2 + 15 00 00 00 00 00 02 39 F2 + 15 00 00 00 00 00 02 3A EF + 15 00 00 00 00 00 02 3B EC + 15 00 00 00 00 00 02 3D E9 + 15 00 00 00 00 00 02 3F E5 + 15 00 00 00 00 00 02 40 E5 + 15 00 00 00 00 00 02 41 E5 + 15 00 00 00 00 00 02 2A 13 + 15 00 00 00 00 00 02 45 FF + 15 00 00 00 00 00 02 46 F4 + 15 00 00 00 00 00 02 47 E7 + 15 00 00 00 00 00 02 48 DA + 15 00 00 00 00 00 02 49 CD + 15 00 00 00 00 00 02 4A C0 + 15 00 00 00 00 00 02 4B B3 + 15 00 00 00 00 00 02 4C B2 + 15 00 00 00 00 00 02 4D B2 + 15 00 00 00 00 00 02 4E B2 + 15 00 00 00 00 00 02 4F 99 + 15 00 00 00 00 00 02 50 80 + 15 00 00 00 00 00 02 51 68 + 15 00 00 00 00 00 02 52 66 + 15 00 00 00 00 00 02 53 66 + 15 00 00 00 00 00 02 54 66 + 15 00 00 00 00 00 02 2B 0E + 15 00 00 00 00 00 02 58 FF + 15 00 00 00 00 00 02 59 FB + 15 00 00 00 00 00 02 5A F7 + 15 00 00 00 00 00 02 5B F3 + 15 00 00 00 00 00 02 5C EF + 15 00 00 00 00 00 02 5D E3 + 15 00 00 00 00 00 02 5E DA + 15 00 00 00 00 00 02 5F D8 + 15 00 00 00 00 00 02 60 D8 + 15 00 00 00 00 00 02 61 D8 + 15 00 00 00 00 00 02 62 CB + 15 00 00 00 00 00 02 63 BF + 15 00 00 00 00 00 02 64 B3 + 15 00 00 00 00 00 02 65 B2 + 15 00 00 00 00 00 02 66 B2 + 15 01 00 00 00 00 02 67 B2 + /* ESD Setting */ + 15 00 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 40 20 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 C0 03 + 39 00 00 00 00 00 03 51 0D B5 + 15 01 00 00 00 00 02 53 24 + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 46 00 02 11 00 + 15 01 00 00 00 00 02 29 00 + 15 00 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 3F 01 + 15 00 00 00 00 00 02 43 08 + 15 00 00 00 00 00 02 40 25 + 15 01 00 00 00 00 02 FF 10]; + qcom,mdss-dsi-post-off-command = [ + 15 00 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 3F 00 + 15 00 00 00 00 00 02 FF 10 + 05 00 00 00 00 00 02 28 00 + 05 01 00 00 46 00 02 10 00]; + qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; + qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-post-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; + + + qcom,mdss-dsi-dispparam-cabcuion-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 01 + ]; + qcom,mdss-dsi-dispparam-cabcstillon-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 02 + ]; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 03 + ]; + qcom,mdss-dsi-dispparam-cabcoff-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 00 + ]; + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [ + 15 00 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0E A0]; + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [ + 15 00 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 FF FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [ + 15 00 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0D B5]; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x11>; + qcom,mdss-dsc-scr-version = <0x0>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; + +&dsi_j20s_36_02_0a_video { + mi,feature-enabled; + mi,is-tddi-flag; + mi,mdss-panel-on-dimming-delay = <120>; + mi,esd-err-irq-gpio = <&tlmm 24 0x2002>; /* trig-flags: falling-0x0002 rasing-0x0001*/ + mi,mdss-dsi-panel-xy-coordinate = <0x6 0x3>; + mi,mdss-dsi-panel-max-luminance = <0x6 0x4>; + mi,mdss-dsi-panel-status-value-ignore; + mi,esd-check-interval = <3000>; + mi,mdss-panel-idle-time = <1100>; + mi,mdss-panel-idle-fps = <50>; + //mi,mdss-dsi-pan-enable-smart-fps; + mi,mdss-dsi-dfps-dec-vfp-list = <20 0 20 0 0 0 + 0 0 0 0 0 0>; + mi,mdss-dsi-dfps-dec-hfp-list = <0 0 0 0 0 0 + 4 0 4 0 0 0>; + mi,mdss-dsi-post-off-msleep = <20>; + + qcom,mdss-dsi-display-timings { + timing@0{ + mi,mdss-dsi-read-lockdown-info-command = [ + 15 00 00 00 00 00 02 FF 21 + 06 01 00 00 00 00 01 F1]; + mi,mdss-dsi-read-lockdown-info-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-cabcuion-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 01 + ]; + mi,mdss-dsi-cabcuion-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabcstillon-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 02 + ]; + mi,mdss-dsi-cabcstillon-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabcmovieon-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 03 + ]; + mi,mdss-dsi-cabcmovieon-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabcoff-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 00 + ]; + mi,mdss-dsi-cabcoff-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabc-dimmming-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 53 2C + ]; + mi,mdss-dsi-cabc-dimmming-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-xy-coordinate-command = [ + 15 00 00 00 00 00 02 FF 10 + 06 01 00 00 00 00 01 A1]; + mi,mdss-dsi-xy-coordinate-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-max-luminance-write-command = [ + 15 01 00 00 00 00 02 FF 10]; + mi,mdss-dsi-max-luminance-write-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-max-luminance-read-command = [ + 06 01 00 00 00 00 01 A1]; + mi,mdss-dsi-max-luminance-read-command-state = "dsi_lp_mode"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-42-02-0b-lcd-dsc-vid.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-42-02-0b-lcd-dsc-vid.dtsi new file mode 100644 index 000000000000..c9421342f92b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-j20s-42-02-0b-lcd-dsc-vid.dtsi @@ -0,0 +1,318 @@ +/* Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&mdss_mdp { + dsi_j20s_42_02_0b_video: qcom,mdss_dsi_j20s_42_02_0b_dsc_video { + qcom,mdss-dsi-panel-name = "xiaomi 42 02 0b video mode dsc dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "xiaomi 42 02 0b VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; + qcom,ulps-enabled; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <70>; + qcom,mdss-pan-physical-height-dimension = <154>; + qcom,mdss-dsi-tx-eot-append; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,disp-panel-offon-mode-enabled; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + /* qcom,mdss-dsi-qsync-min-refresh-rate = <60>; */ + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <120 90 60 50 48 30>; + + qcom,dispparam-enabled; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-front-porch = <67>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-v-back-porch = <30>; + qcom,mdss-dsi-v-front-porch = <33>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + /* DDIC Initical Code */ + 15 00 00 00 00 00 02 FF 20 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 EE 60 + 15 01 00 00 00 00 02 EF 06 + /* CABC Setting */ + 15 00 00 00 00 00 02 FF 23 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 00 80 + 15 00 00 00 00 00 02 01 84 + 15 00 00 00 00 00 02 05 2D + 15 00 00 00 00 00 02 06 00 + 15 00 00 00 00 00 02 07 00 + 15 00 00 00 00 00 02 08 01 + 15 00 00 00 00 00 02 09 45 + 15 00 00 00 00 00 02 11 01 + 15 00 00 00 00 00 02 12 95 + 15 00 00 00 00 00 02 15 68 + 15 00 00 00 00 00 02 16 0B + 15 00 00 00 00 00 02 29 0A + 15 00 00 00 00 00 02 30 FF + 15 00 00 00 00 00 02 31 FE + 15 00 00 00 00 00 02 32 FD + 15 00 00 00 00 00 02 33 FB + 15 00 00 00 00 00 02 34 F8 + 15 00 00 00 00 00 02 35 F5 + 15 00 00 00 00 00 02 36 F3 + 15 00 00 00 00 00 02 37 F2 + 15 00 00 00 00 00 02 38 F2 + 15 00 00 00 00 00 02 39 F2 + 15 00 00 00 00 00 02 3A EF + 15 00 00 00 00 00 02 3B EC + 15 00 00 00 00 00 02 3D E9 + 15 00 00 00 00 00 02 3F E5 + 15 00 00 00 00 00 02 40 E5 + 15 00 00 00 00 00 02 41 E5 + 15 00 00 00 00 00 02 2A 13 + 15 00 00 00 00 00 02 45 FF + 15 00 00 00 00 00 02 46 F4 + 15 00 00 00 00 00 02 47 E7 + 15 00 00 00 00 00 02 48 DA + 15 00 00 00 00 00 02 49 CD + 15 00 00 00 00 00 02 4A C0 + 15 00 00 00 00 00 02 4B B3 + 15 00 00 00 00 00 02 4C B2 + 15 00 00 00 00 00 02 4D B2 + 15 00 00 00 00 00 02 4E B2 + 15 00 00 00 00 00 02 4F 99 + 15 00 00 00 00 00 02 50 80 + 15 00 00 00 00 00 02 51 68 + 15 00 00 00 00 00 02 52 66 + 15 00 00 00 00 00 02 53 66 + 15 00 00 00 00 00 02 54 66 + 15 00 00 00 00 00 02 2B 0E + 15 00 00 00 00 00 02 58 FF + 15 00 00 00 00 00 02 59 FB + 15 00 00 00 00 00 02 5A F7 + 15 00 00 00 00 00 02 5B F3 + 15 00 00 00 00 00 02 5C EF + 15 00 00 00 00 00 02 5D E3 + 15 00 00 00 00 00 02 5E DA + 15 00 00 00 00 00 02 5F D8 + 15 00 00 00 00 00 02 60 D8 + 15 00 00 00 00 00 02 61 D8 + 15 00 00 00 00 00 02 62 CB + 15 00 00 00 00 00 02 63 BF + 15 00 00 00 00 00 02 64 B3 + 15 00 00 00 00 00 02 65 B2 + 15 00 00 00 00 00 02 66 B2 + 15 01 00 00 00 00 02 67 B2 + + /*decrease MUX EQ for desense*/ + 15 00 00 00 00 00 02 FF 20 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 1F C0 + 15 00 00 00 00 00 02 20 C0 + + 15 00 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 D6 80 + 15 00 00 00 00 00 02 D7 02 + 15 00 00 00 00 00 02 DD 02 + + /* ESD Setting */ + 15 00 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 40 20 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 C0 03 + 39 00 00 00 00 00 03 51 0D B5 + 15 01 00 00 00 00 02 53 24 + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 46 00 02 11 00 + 15 01 00 00 00 00 02 29 00 + 15 00 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 3F 01 + 15 00 00 00 00 00 02 43 08 + 15 00 00 00 00 00 02 40 25 + 15 01 00 00 00 00 02 FF 10]; + qcom,mdss-dsi-post-off-command = [ + 15 00 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 3F 00 + 15 00 00 00 00 00 02 FF 10 + 05 00 00 00 00 00 02 28 00 + 05 01 00 00 46 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-post-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; + qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; + + + qcom,mdss-dsi-dispparam-cabcuion-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 01 + ]; + qcom,mdss-dsi-dispparam-cabcstillon-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 02 + ]; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 03 + ]; + qcom,mdss-dsi-dispparam-cabcoff-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 00 + ]; + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [ + 15 00 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0E A0]; + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [ + 15 00 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 FF FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [ + 15 00 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0D B5]; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x11>; + qcom,mdss-dsc-scr-version = <0x0>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; + +&dsi_j20s_42_02_0b_video { + mi,feature-enabled; + mi,is-tddi-flag; + mi,mdss-panel-on-dimming-delay = <120>; + mi,esd-err-irq-gpio = <&tlmm 24 0x2002>; /* trig-flags: falling-0x0002 rasing-0x0001*/ + mi,mdss-dsi-panel-xy-coordinate = <0x6 0x3>; + mi,mdss-dsi-panel-max-luminance = <0x6 0x4>; + mi,mdss-dsi-panel-status-value-ignore; + mi,esd-check-interval = <3000>; + mi,mdss-panel-idle-time = <1100>; + mi,mdss-panel-idle-fps = <50>; +// mi,mdss-dsi-pan-enable-smart-fps; + mi,mdss-dsi-dfps-dec-vfp-list = <20 0 20 0 0 0 + 0 0 0 0 0 0>; + mi,mdss-dsi-dfps-dec-hfp-list = <0 0 0 0 0 0 + 4 0 4 0 0 0>; + mi,mdss-dsi-post-off-msleep = <20>; + + qcom,mdss-dsi-display-timings { + timing@0{ + mi,mdss-dsi-read-lockdown-info-command = [ + 15 00 00 00 00 00 02 FF 21 + 06 01 00 00 00 00 01 F1]; + mi,mdss-dsi-read-lockdown-info-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-cabcuion-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 01 + ]; + mi,mdss-dsi-cabcuion-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabcstillon-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 02 + ]; + mi,mdss-dsi-cabcstillon-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabcmovieon-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 03 + ]; + mi,mdss-dsi-cabcmovieon-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabcoff-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 55 00 + ]; + mi,mdss-dsi-cabcoff-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-cabc-dimmming-command = [ + 15 00 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 53 2C + ]; + mi,mdss-dsi-cabc-dimmming-command-state = "dsi_hs_mode"; + + mi,mdss-dsi-xy-coordinate-command = [ + 15 00 00 00 00 00 02 FF 10 + 06 01 00 00 00 00 01 A1]; + mi,mdss-dsi-xy-coordinate-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-max-luminance-write-command = [ + 15 01 00 00 00 00 02 FF 10]; + mi,mdss-dsi-max-luminance-write-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-max-luminance-read-command = [ + 06 01 00 00 00 00 01 A1]; + mi,mdss-dsi-max-luminance-read-command-state = "dsi_lp_mode"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi new file mode 100644 index 000000000000..536baccd575a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi @@ -0,0 +1,367 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&mdss_mdp { + dsi_k82_36_02_0b_dual_cphy_video: qcom,mdss_dsi_k82_36_02_0b_dual_cphy_video { + qcom,mdss-dsi-panel-name = "xiaomi 36 02 0b video mode dual dsi cphy panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "xiaomi 36 02 0b VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0 12>, <1 12>, <0 12>, <1 12>; + qcom,mdss-pan-physical-width-dimension = <1474>; + qcom,mdss-pan-physical-height-dimension = <2359>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,cmd-sync-wait-broadcast; + qcom,panel-cphy-mode; + qcom,mdss-dsi-cphy-strength; + mi,cphy-esd-check; + mi,is-tddi-flag; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <120 60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <800>; // 1600/2 + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-front-porch = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <168>; + qcom,mdss-dsi-v-front-porch = <26>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command= [ + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 B9 05 + 15 00 00 00 00 00 02 FF 20 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 18 40 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 B9 02 + /*CABC start*/ + 15 00 00 00 00 00 02 FF 23 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 00 80 + 15 00 00 00 00 00 02 01 84 + 15 00 00 00 00 00 02 05 2D + 15 00 00 00 00 00 02 06 00 + 15 00 00 00 00 00 02 07 00 + 15 00 00 00 00 00 02 08 01 + 15 00 00 00 00 00 02 09 45 + 15 00 00 00 00 00 02 11 02 + 15 00 00 00 00 00 02 12 80 + 15 00 00 00 00 00 02 15 83 + 15 01 00 00 00 00 02 16 0C + 15 00 00 00 00 00 02 29 0A + 15 00 00 00 00 00 02 30 FF + 15 00 00 00 00 00 02 31 FE + 15 00 00 00 00 00 02 32 FD + 15 00 00 00 00 00 02 33 FB + 15 00 00 00 00 00 02 34 F8 + 15 00 00 00 00 00 02 35 F5 + 15 00 00 00 00 00 02 36 F3 + 15 00 00 00 00 00 02 37 F2 + 15 00 00 00 00 00 02 38 F2 + 15 00 00 00 00 00 02 39 F2 + 15 00 00 00 00 00 02 3A EF + 15 00 00 00 00 00 02 3B EC + 15 00 00 00 00 00 02 3D E9 + 15 00 00 00 00 00 02 3F E5 + 15 00 00 00 00 00 02 40 E5 + 15 00 00 00 00 00 02 41 E5 + 15 00 00 00 00 00 02 2A 13 + 15 01 00 00 00 00 02 45 FF + 15 00 00 00 00 00 02 46 F4 + 15 00 00 00 00 00 02 47 E7 + 15 00 00 00 00 00 02 48 DA + 15 00 00 00 00 00 02 49 CD + 15 00 00 00 00 00 02 4A C0 + 15 00 00 00 00 00 02 4B B3 + 15 00 00 00 00 00 02 4C B2 + 15 00 00 00 00 00 02 4D B2 + 15 00 00 00 00 00 02 4E B2 + 15 00 00 00 00 00 02 4F 99 + 15 00 00 00 00 00 02 50 80 + 15 00 00 00 00 00 02 51 68 + 15 00 00 00 00 00 02 52 66 + 15 00 00 00 00 00 02 53 66 + 15 00 00 00 00 00 02 54 66 + 15 01 00 00 00 00 02 2B 0E + 15 00 00 00 00 00 02 58 FF + 15 00 00 00 00 00 02 59 FB + 15 00 00 00 00 00 02 5A F7 + 15 00 00 00 00 00 02 5B F3 + 15 00 00 00 00 00 02 5C EF + 15 00 00 00 00 00 02 5D E3 + 15 00 00 00 00 00 02 5E DA + 15 00 00 00 00 00 02 5F D8 + 15 00 00 00 00 00 02 60 D8 + 15 00 00 00 00 00 02 61 D8 + 15 00 00 00 00 00 02 62 CB + 15 00 00 00 00 00 02 63 BF + 15 00 00 00 00 00 02 64 B3 + 15 00 00 00 00 00 02 65 B2 + 15 00 00 00 00 00 02 66 B2 + 15 01 00 00 00 00 02 67 B2 + /*CABC end*/ + /*ESD start*/ + 15 00 00 00 00 00 02 FF F0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 84 08 + 15 00 00 00 00 00 02 85 0C + 15 00 00 00 00 00 02 FF 20 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 51 00 + 15 00 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 91 1F + 15 00 00 00 00 00 02 92 0F + 15 00 00 00 00 00 02 93 01 + 15 00 00 00 00 00 02 94 18 + 15 01 00 00 00 00 02 95 03 + 15 00 00 00 00 00 02 96 01 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 B0 01 + 15 00 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 19 1F + 15 00 00 00 00 00 02 1B 1B + 15 00 00 00 00 00 02 FF 24 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 B8 28 + 15 00 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 D0 31 + 15 00 00 00 00 00 02 DE 80 + 15 00 00 00 00 00 02 DF 02 + 15 00 00 00 00 00 02 D1 20 + 15 00 00 00 00 00 02 D2 30 + 15 01 00 00 00 00 02 D4 08 + /*ESD end*/ + /*OSC start*/ + 15 00 00 00 00 00 02 FF 26 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 00 81 + 15 00 00 00 00 00 02 01 B0 + 15 00 00 00 00 00 02 FF 22 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 6F 01 + 15 00 00 00 00 00 02 70 11 + 15 00 00 00 00 00 02 73 01 + 15 00 00 00 00 00 02 74 46 + 15 00 00 00 00 00 02 A0 3F + 15 00 00 00 00 00 02 A9 50 + 15 00 00 00 00 00 02 AA 28 + 15 00 00 00 00 00 02 AB 28 + 15 01 00 00 00 00 02 AD 10 + 15 00 00 00 00 00 02 B8 00 + 15 00 00 00 00 00 02 B9 46 + 15 00 00 00 00 00 02 BA 8C + 15 00 00 00 00 00 02 BB 46 + 15 00 00 00 00 00 02 BE 0A + 15 00 00 00 00 00 02 BF 46 + 15 00 00 00 00 00 02 C0 0A + 15 00 00 00 00 00 02 C1 56 + 15 00 00 00 00 00 02 C2 00 + 15 00 00 00 00 00 02 C5 00 + 15 00 00 00 00 00 02 C6 00 + 15 01 00 00 00 00 02 C7 30 + 15 00 00 00 00 00 02 CA 00 + 15 00 00 00 00 00 02 CB 3C + 15 00 00 00 00 00 02 CE 00 + 15 00 00 00 00 00 02 CF 00 + 15 00 00 00 00 00 02 D0 38 + 15 00 00 00 00 00 02 D3 08 + 15 00 00 00 00 00 02 D4 3D + 15 00 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 BC 01 + 15 00 00 00 00 00 02 BD 1C + 15 00 00 00 00 00 02 FF 2A + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 9A 03 + /*OSC end*/ + 15 00 00 00 00 00 02 FF D0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 00 32 + 15 00 00 00 00 00 02 02 FF + 15 00 00 00 00 00 02 09 FF + 15 00 00 00 00 00 02 53 22 + 15 00 00 00 00 00 02 54 02 + 15 00 00 00 00 00 02 1C 99 + 15 00 00 00 00 00 02 1D 09 + 15 00 00 00 00 00 02 FF E0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 14 60 + 15 00 00 00 00 00 02 16 C0 + 15 00 00 00 00 00 02 4F 02 + 15 01 00 00 00 00 02 FF F0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 3A 08 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 BB 13 + 39 00 00 00 00 00 06 3B 03 AC 1A 04 04 + 15 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 51 0F FF + 15 01 00 00 00 00 02 53 2C + 05 01 00 00 46 00 02 11 00 + 15 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 46 00 02 10 00]; + qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; + qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-pen-120hz-command = [ + 15 00 00 00 00 00 02 FF 2A + 15 00 00 00 00 00 02 23 0D + 15 01 00 00 00 00 02 FF 10]; + qcom,mdss-dsi-dispparam-pen-60hz-command = [ + 15 00 00 00 00 00 02 FF 2A + 15 00 00 00 00 00 02 23 0C + 15 01 00 00 00 00 02 FF 10]; + qcom,mdss-dsi-dispparam-pen-120hz-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-pen-60hz-command-state = "dsi_lp_mode"; + + /* max brightness 85% */ + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [ + 15 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0F FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = "dsi_lp_mode"; + /* max brightness 91% */ + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [ + 15 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0F FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [ + 15 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0F FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; + +&dsi_k82_36_02_0b_dual_cphy_video { + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + qcom,esd-err-irq-gpio = <&tlmm 37 0x2002>; /* trig-flags: falling-0x0002 rasing-0x0001*/ + mi,mdss-dsi-panel-xy-coordinate = <0x3 0x3>; + mi,mdss-dsi-panel-max-luminance = <0x3 0x4>; + qcom,mdss-dsi-display-timings { + timing@0{ + mi,mdss-dsi-read-lockdown-info-command = [ + 15 01 00 00 00 00 02 FF 22 + 06 01 00 00 00 00 01 01 + 06 01 00 00 00 00 01 02 + 06 01 00 00 00 00 01 03 + 06 01 00 00 00 00 01 04 + 06 01 00 00 00 00 01 05 + 06 01 00 00 00 00 01 06 + 06 01 00 00 00 00 01 07 + 06 01 00 00 00 00 01 08]; + mi,mdss-dsi-read-lockdown-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcuion-command = [ + 15 01 00 00 00 00 02 55 01 + ]; + qcom,mdss-dsi-dispparam-cabcstillon-command = [ + 15 01 00 00 00 00 02 55 02 + ]; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [ + 15 01 00 00 00 00 02 55 03 + ]; + qcom,mdss-dsi-dispparam-cabcoff-command = [ + 15 01 00 00 00 00 02 55 00 + ]; + qcom,mdss-dsi-dispparam-dimmingon-command = [ + /* CABC DIMMING ON */ + 15 01 00 00 00 00 02 53 2C + ]; + qcom,mdss-dsi-dispparam-dimmingoff-command = [ + 15 01 00 00 00 00 02 53 24 + ]; + + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + mi,mdss-dsi-esd-check-read-command = [ + /* esd detect */ + 15 01 00 00 00 00 02 FF 27 + 15 01 00 00 00 00 02 D1 28 + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 53 2C + ]; + mi,mdss-dsi-esd-check-read-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-xy-coordinate-command = [ + 15 01 00 00 00 00 02 FF 10 + 06 01 00 00 00 00 01 A1 + ]; + qcom,mdss-dsi-dispparam-xy-coordinate-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-max-luminance-write-command = [ + 15 01 00 00 00 00 02 FF 10]; + mi,mdss-dsi-max-luminance-write-command-state = "dsi_lp_mode"; + mi,mdss-dsi-max-luminance-read-command = [ + 06 01 00 00 00 00 01 A1]; + mi,mdss-dsi-max-luminance-read-command-state = "dsi_lp_mode"; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi new file mode 100644 index 000000000000..22c3e689801b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi @@ -0,0 +1,381 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&mdss_mdp { + dsi_k82_42_02_0a_dual_cphy_video: qcom,mdss_dsi_k82_42_02_0a_dual_cphy_video { + qcom,mdss-dsi-panel-name = "xiaomi 42 02 0a video mode dual dsi cphy panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "xiaomi 42 02 0a VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0 12>, <1 12>, <0 12>, <1 12>; + qcom,mdss-pan-physical-width-dimension = <1474>; + qcom,mdss-pan-physical-height-dimension = <2359>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-rx-eot-ignore; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,cmd-sync-wait-broadcast; + qcom,panel-cphy-mode; + qcom,mdss-dsi-cphy-strength; + mi,cphy-esd-check; + mi,is-tddi-flag; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,dsi-supported-dfps-list = <120 60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <800>; // 1600/2 + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-front-porch = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <168>; + qcom,mdss-dsi-v-front-porch = <26>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command= [ + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 B9 05 + 15 00 00 00 00 00 02 FF 20 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 18 40 + 15 01 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 B9 02 + 15 00 00 00 00 00 02 FF D0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 02 AF + 15 00 00 00 00 00 02 00 30 + 15 00 00 00 00 00 02 09 EE + 15 00 00 00 00 00 02 1C 99 + 15 01 00 00 00 00 02 1D 09 + 15 00 00 00 00 00 02 FF F0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 3A 08 + 15 00 00 00 00 00 02 FF E0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 4F 02 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 35 00 + /* CABC SETTING CFG Start*/ + 15 00 00 00 00 00 02 FF 23 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 00 80 + 15 00 00 00 00 00 02 01 84 + 15 00 00 00 00 00 02 05 2D + 15 00 00 00 00 00 02 06 00 + 15 00 00 00 00 00 02 07 00 + 15 00 00 00 00 00 02 08 01 + 15 00 00 00 00 00 02 09 45 + 15 00 00 00 00 00 02 11 02 + 15 00 00 00 00 00 02 12 80 + 15 00 00 00 00 00 02 15 83 + 15 00 00 00 00 00 02 16 0C + 15 01 00 00 00 00 02 29 0A + 15 00 00 00 00 00 02 30 FF + 15 00 00 00 00 00 02 31 FE + 15 00 00 00 00 00 02 32 FD + 15 00 00 00 00 00 02 33 FB + 15 00 00 00 00 00 02 34 F8 + 15 00 00 00 00 00 02 35 F5 + 15 00 00 00 00 00 02 36 F3 + 15 00 00 00 00 00 02 37 F2 + 15 00 00 00 00 00 02 38 F2 + 15 00 00 00 00 00 02 39 F2 + 15 00 00 00 00 00 02 3A EF + 15 00 00 00 00 00 02 3B EC + 15 00 00 00 00 00 02 3D E9 + 15 00 00 00 00 00 02 3F E5 + 15 00 00 00 00 00 02 40 E5 + 15 01 00 00 00 00 02 41 E5 + 15 00 00 00 00 00 02 2A 13 + 15 00 00 00 00 00 02 45 FF + 15 00 00 00 00 00 02 46 F4 + 15 00 00 00 00 00 02 47 E7 + 15 00 00 00 00 00 02 48 DA + 15 00 00 00 00 00 02 49 CD + 15 00 00 00 00 00 02 4A C0 + 15 00 00 00 00 00 02 4B B3 + 15 00 00 00 00 00 02 4C B2 + 15 00 00 00 00 00 02 4D B2 + 15 00 00 00 00 00 02 4E B2 + 15 00 00 00 00 00 02 4F 99 + 15 00 00 00 00 00 02 50 80 + 15 00 00 00 00 00 02 51 68 + 15 00 00 00 00 00 02 52 66 + 15 00 00 00 00 00 02 53 66 + 15 01 00 00 00 00 02 54 66 + 15 00 00 00 00 00 02 2B 0E + 15 00 00 00 00 00 02 58 FF + 15 00 00 00 00 00 02 59 FB + 15 00 00 00 00 00 02 5A F7 + 15 00 00 00 00 00 02 5B F3 + 15 00 00 00 00 00 02 5C EF + 15 00 00 00 00 00 02 5D E3 + 15 00 00 00 00 00 02 5E DA + 15 00 00 00 00 00 02 5F D8 + 15 00 00 00 00 00 02 60 D8 + 15 00 00 00 00 00 02 61 D8 + 15 00 00 00 00 00 02 62 CB + 15 00 00 00 00 00 02 63 BF + 15 00 00 00 00 00 02 64 B3 + 15 00 00 00 00 00 02 65 B2 + 15 00 00 00 00 00 02 66 B2 + 15 00 00 00 00 00 02 67 B2 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 39 00 00 00 00 00 03 51 0F FF + 15 01 00 00 00 00 02 53 24 + /* CABC SETTING CFG END */ + 15 00 00 00 00 00 02 55 00 + 15 00 00 00 00 00 02 BB 13 + 39 01 00 00 00 00 06 3B 03 AC 1A 04 04 + /* 30HZ pen code Start*/ + 15 00 00 00 00 00 02 FF 2A + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 25 46 + 15 00 00 00 00 00 02 30 46 + 15 00 00 00 00 00 02 39 46 + 15 00 00 00 00 00 02 FF 26 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 01 B0 + 15 00 00 00 00 00 02 19 10 + 15 00 00 00 00 00 02 1A E0 + 15 00 00 00 00 00 02 1B 10 + 15 00 00 00 00 00 02 1C 00 + 15 00 00 00 00 00 02 2A 10 + 15 01 00 00 00 00 02 2B E0 + /* 30HZ pen code END*/ + /* ESD code*/ + 15 01 00 00 00 00 02 FF 26 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 01 B0 + 15 01 00 00 00 00 02 FF F0 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 84 08 + 15 00 00 00 00 00 02 85 0C + 15 01 00 00 00 00 02 FF 20 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 91 1F + 15 00 00 00 00 00 02 92 0F + 15 00 00 00 00 00 02 93 01 + 15 00 00 00 00 00 02 94 18 + 15 00 00 00 00 00 02 95 03 + 15 00 00 00 00 00 02 96 01 + 15 01 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 19 1F + 15 00 00 00 00 00 02 1B 1B + 15 01 00 00 00 00 02 FF 24 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 B8 28 + 15 01 00 00 00 00 02 FF 27 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 D0 31 + 15 00 00 00 00 00 02 DE 80 + 15 00 00 00 00 00 02 DF 02 + 15 00 00 00 00 00 02 D1 20 + 15 01 00 00 00 00 02 D4 08 + 15 00 00 00 00 00 02 FF 26 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 00 81 + 15 00 00 00 00 00 02 01 B0 + 15 01 00 00 00 00 02 FF 22 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 6F 01 + 15 00 00 00 00 00 02 70 11 + 15 00 00 00 00 00 02 73 01 + 15 00 00 00 00 00 02 74 4D + 15 00 00 00 00 00 02 A0 3F + 15 00 00 00 00 00 02 A9 50 + 15 00 00 00 00 00 02 AA 28 + 15 00 00 00 00 00 02 AB 28 + 15 00 00 00 00 00 02 AD 10 + 15 00 00 00 00 00 02 B8 00 + 15 00 00 00 00 00 02 B9 4B + 15 01 00 00 00 00 02 BA 96 + 15 00 00 00 00 00 02 BB 4B + 15 00 00 00 00 00 02 BE 07 + 15 00 00 00 00 00 02 BF 4B + 15 00 00 00 00 00 02 C0 07 + 15 00 00 00 00 00 02 C1 5C + 15 00 00 00 00 00 02 C2 00 + 15 00 00 00 00 00 02 C5 00 + 15 00 00 00 00 00 02 C6 3F + 15 00 00 00 00 00 02 C7 00 + 15 00 00 00 00 00 02 CA 08 + 15 00 00 00 00 00 02 CB 40 + 15 00 00 00 00 00 02 CE 00 + 15 01 00 00 00 00 02 CF 08 + 15 00 00 00 00 00 02 D0 40 + 15 00 00 00 00 00 02 D3 08 + 15 00 00 00 00 00 02 D4 40 + 15 00 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 BC 01 + 15 00 00 00 00 00 02 BD 1C + 15 00 00 00 00 00 02 FF 2A + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 9A 03 + 15 01 00 00 00 00 02 FF 10 + 05 01 00 00 46 00 02 11 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 46 00 02 10 00]; + qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; + qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-pen-120hz-command = [ + 15 00 00 00 00 00 02 FF 2A + 15 00 00 00 00 00 02 23 0D + 15 01 00 00 00 00 02 FF 10]; + qcom,mdss-dsi-dispparam-pen-60hz-command = [ + 15 00 00 00 00 00 02 FF 2A + 15 00 00 00 00 00 02 23 0C + 15 01 00 00 00 00 02 FF 10]; + qcom,mdss-dsi-dispparam-pen-120hz-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-pen-60hz-command-state = "dsi_lp_mode"; + + /* max brightness 85% */ + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [ + 15 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0F FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command-state = "dsi_lp_mode"; + /* max brightness 91% */ + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command = [ + 15 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0F FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-l2-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command = [ + 15 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 03 51 0F FF]; + qcom,mdss-dsi-dispparam-lcd-hbm-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; + +&dsi_k82_42_02_0a_dual_cphy_video { + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + qcom,esd-err-irq-gpio = <&tlmm 37 0x2002>; /* trig-flags: falling-0x0002 rasing-0x0001*/ + mi,mdss-dsi-panel-xy-coordinate = <0x3 0x3>; + mi,mdss-dsi-panel-max-luminance = <0x3 0x4>; + qcom,mdss-dsi-display-timings { + timing@0{ + mi,mdss-dsi-read-lockdown-info-command = [ + 15 01 00 00 00 00 02 FF 22 + 06 01 00 00 00 00 01 01 + 06 01 00 00 00 00 01 02 + 06 01 00 00 00 00 01 03 + 06 01 00 00 00 00 01 04 + 06 01 00 00 00 00 01 05 + 06 01 00 00 00 00 01 06 + 06 01 00 00 00 00 01 07 + 06 01 00 00 00 00 01 08]; + mi,mdss-dsi-read-lockdown-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcuion-command = [ + 15 01 00 00 00 00 02 55 01 + ]; + qcom,mdss-dsi-dispparam-cabcstillon-command = [ + 15 01 00 00 00 00 02 55 02 + ]; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [ + 15 01 00 00 00 00 02 55 03 + ]; + qcom,mdss-dsi-dispparam-cabcoff-command = [ + 15 01 00 00 00 00 02 55 00 + ]; + qcom,mdss-dsi-dispparam-dimmingon-command = [ + /* CABC DIMMING ON */ + 15 01 00 00 00 00 02 53 2C + ]; + qcom,mdss-dsi-dispparam-dimmingoff-command = [ + 15 01 00 00 00 00 02 53 24 + ]; + + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + mi,mdss-dsi-esd-check-read-command = [ + /* esd detect */ + 15 01 00 00 00 00 02 FF 27 + 15 01 00 00 00 00 02 D1 28 + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 53 2C + ]; + mi,mdss-dsi-esd-check-read-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-xy-coordinate-command = [ + 15 01 00 00 00 00 02 FF 10 + 06 01 00 00 00 00 01 A1 + ]; + qcom,mdss-dsi-dispparam-xy-coordinate-command-state = "dsi_lp_mode"; + + mi,mdss-dsi-max-luminance-write-command = [ + 15 01 00 00 00 00 02 FF 10]; + mi,mdss-dsi-max-luminance-write-command-state = "dsi_lp_mode"; + mi,mdss-dsi-max-luminance-read-command = [ + 06 01 00 00 00 00 01 A1]; + mi,mdss-dsi-max-luminance-read-command-state = "dsi_lp_mode"; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi new file mode 100644 index 000000000000..db08ebcd43f0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi @@ -0,0 +1,253 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_samsung_fhd_ea8076_cmd: qcom,mdss_dsi_samsung_fhd_ea8076_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + qcom,disp-doze-backlight-threshold = <8>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 27 0x2002>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + /* delay 2ms for VCI1 power */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 FF 10 + 39 00 00 00 00 00 02 B0 2F + 39 00 00 00 00 00 02 D1 01 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 03 FC A5 A5 + /* Sleep Out */ + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + /* TE OUT(Vsync On) */ + 39 00 00 00 00 00 02 35 00 + /* DBV Smooth Transition */ + 39 00 00 00 00 00 03 B7 01 4B + /* Timing set */ + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 03 D9 88 2E + /* Edge Dimming */ + 39 00 00 00 00 00 02 B0 09 + 39 00 00 00 00 00 02 D8 00 + 39 01 00 00 00 00 03 F0 A5 A5 + /* Page Address Set */ + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + /* ERR_FG Setting */ + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + /* OFC Setting 82.6Mhz*/ + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 B8 BB 2A 00 1A B8 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + /* Display On */ + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + /* AOD ON Sequence (Normal To AOD HBM) */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 00 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + /* AOD ON Sequence (Normal To AOD LBM) */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 00 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + /* AOD OFF Sequence (AOD To Normal) */ + 05 01 00 00 22 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod2norm-command = [39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B2 00 40 + 39 00 00 00 00 00 02 B0 04 + 39 00 00 00 00 00 02 B2 80 + 39 00 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod2norm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 CB 0B 01 0B EC 03 05 08 CF 14 FA FA E7 05 EE EE F2 00 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi new file mode 100644 index 000000000000..3c1462365a3c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi @@ -0,0 +1,254 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_samsung_fhd_ea8076_f1_cmd: qcom,mdss_dsi_samsung_fhd_ea8076_f1_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <200>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-off-dimming-delay = <85>; + + qcom,elvss_dimming_check_enable; + qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 B0 07]; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 FF 10 + 39 00 00 00 00 00 02 B0 2F + 39 01 00 00 00 00 02 D1 01 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 06 + 39 00 00 00 00 00 02 B7 10 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 23 + 39 00 00 00 00 00 02 D1 33 + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 A6 37 BE 00 1A B8 + 39 00 00 00 00 00 0C D9 14 00 00 8F 6E 00 00 8F 2E 6E 34 + 39 00 00 00 00 00 6D C0 31 01 03 00 06 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 40 3D 00 5E 00 00 00 20 07 20 30 58 00 00 00 00 00 00 E0 0B 75 D8 00 00 00 00 FC 00 00 00 F6 97 0F 6D E6 CD 05 21 8B EC ED ED ED 0D 3F 60 00 67 FD 6D 51 BC DD DD 00 00 07 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 70 2F 00 00 03 2E 3C 20 E0 00 00 00 00 00 06 8C + 39 01 00 00 00 00 02 C0 31 + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 22 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 CB 0B 01 0B EC 03 05 08 CF 14 FA FA E7 05 EE EE F2 00 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi new file mode 100644 index 000000000000..42c7ecc8ea2b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi @@ -0,0 +1,254 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_samsung_fhd_ea8076_f1mp_cmd: qcom,mdss_dsi_samsung_fhd_ea8076_f1mp_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <200>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-off-dimming-delay = <85>; + + qcom,elvss_dimming_check_enable; + qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 B0 07]; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 FF 10 + 39 00 00 00 00 00 02 B0 2F + 39 01 00 00 00 00 02 D1 01 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 06 + 39 00 00 00 00 00 02 B7 10 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 23 + 39 00 00 00 00 00 02 D1 33 + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 A6 37 BE 00 1A B8 + 39 00 00 00 00 00 0C D9 14 00 00 8F 6E 00 00 8F 2E 6E 34 + 39 00 00 00 00 00 6D C0 31 01 03 00 06 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 40 3D 00 5E 00 00 00 20 07 20 30 58 00 00 00 00 00 00 E0 0B 75 D8 00 00 00 00 FC 00 00 00 F6 97 0F 6D E6 CD 05 21 8B EC ED ED ED 0D 3F 60 00 67 FD 6D 51 BC DD DD 00 00 07 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 70 2F 00 00 03 2E 3C 20 E0 00 00 00 00 00 06 8C + 39 01 00 00 00 00 02 C0 31 + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 22 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 CB 0B 01 0B EC 03 05 08 CF 14 FA FA E7 05 EE EE F2 00 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi new file mode 100644 index 000000000000..437185f1b1a1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi @@ -0,0 +1,254 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_samsung_fhd_ea8076_f1p2_2_cmd: qcom,mdss_dsi_samsung_fhd_ea8076_f1p2_2_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <200>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-off-dimming-delay = <85>; + + qcom,elvss_dimming_check_enable; + qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 B0 07]; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 FF 10 + 39 00 00 00 00 00 02 B0 2F + 39 01 00 00 00 00 02 D1 01 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 06 + 39 00 00 00 00 00 02 B7 10 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 24 + 39 00 00 00 00 00 02 D1 33 + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 A6 37 BE 00 1A B8 + 39 00 00 00 00 00 0C D9 14 00 00 8F 6E 00 00 8F 2E 6E 34 + 39 00 00 00 00 00 6D C0 31 01 03 00 06 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 40 3D 00 5E 00 00 00 20 07 20 30 58 00 00 00 00 00 00 E0 0B 75 D8 00 00 00 00 FC 00 00 00 F6 97 0F 6D E6 CD 05 21 8B EC ED ED ED 0D 3F 60 00 67 FD 6D 51 BC DD DD 00 00 07 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 70 2F 00 00 03 2E 3C 20 E0 00 00 00 00 00 06 8C + 39 01 00 00 00 00 02 C0 31 + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 22 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 CB 0B 01 0B EC 03 05 08 CF 14 FA FA E7 05 EE EE F2 00 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi new file mode 100644 index 000000000000..15821d208877 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi @@ -0,0 +1,254 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_samsung_fhd_ea8076_f1p2_cmd: qcom,mdss_dsi_samsung_fhd_ea8076_f1p2_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <200>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-off-dimming-delay = <85>; + + qcom,elvss_dimming_check_enable; + qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 B0 07]; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 FF 10 + 39 00 00 00 00 00 02 B0 2F + 39 01 00 00 00 00 02 D1 01 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 06 + 39 00 00 00 00 00 02 B7 10 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 23 + 39 00 00 00 00 00 02 D1 33 + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 A6 37 BE 00 1A B8 + 39 00 00 00 00 00 0C D9 14 00 00 8F 6E 00 00 8F 2E 6E 34 + 39 00 00 00 00 00 6D C0 31 01 03 00 06 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 40 3D 00 5E 00 00 00 20 07 20 30 58 00 00 00 00 00 00 E0 0B 75 D8 00 00 00 00 FC 00 00 00 F6 97 0F 6D E6 CD 05 21 8B EC ED ED ED 0D 3F 60 00 67 FD 6D 51 BC DD DD 00 00 07 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 70 2F 00 00 03 2E 3C 20 E0 00 00 00 00 00 06 8C + 39 01 00 00 00 00 02 C0 31 + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 22 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 CB 0B 01 0B EC 03 05 08 CF 14 FA FA E7 05 EE EE F2 00 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi new file mode 100644 index 000000000000..c8b8191aaccb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi @@ -0,0 +1,277 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_samsung_fhd_ea8076_f1s_cmd: qcom,mdss_dsi_samsung_fhd_ea8076_f1s_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <200>; + qcom,mdss-dsi-panel-dc-threshold = <610>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + + qcom,elvss_dimming_check_enable; + qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 B0 07]; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + /* WHITE POINT COMMAND */ + qcom,mdss-dsi-panel-white-point-read-length = <8>; + qcom,mdss-dsi-dispparam-whitepoint-read-command = [06 01 00 01 00 00 01 EF]; + qcom,mdss-dsi-dispparam-whitepoint-read-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <88>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1110000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 FF 10 + 39 00 00 00 00 00 02 B0 2F + 39 01 00 00 00 00 02 D1 01 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 06 + 39 00 00 00 00 00 02 B7 10 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 FC 5A 5A + + /* OSC frequency to 91.8M/89.8M */ + 39 00 00 00 00 00 02 B0 23 + 39 00 00 00 00 00 02 D1 2C + /*39 00 00 00 00 00 0C E9 11 55 A6 75 A3 A6 37 BE 00 1A B8*/ + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 A9 EB 71 00 1A B8 + 39 00 00 00 00 00 0C D9 14 00 00 8F 6E 00 00 8F 2E 6E 34 + 39 00 00 00 00 00 6D C0 31 01 03 00 06 00 00 00 00 00 00 00 00 00 00 00 00 50 00 00 40 3D 00 5E 00 00 00 20 07 20 30 58 00 00 00 00 00 00 E0 0B 75 D8 00 00 00 00 FC 00 00 00 F6 97 0F 6D E6 CD 05 21 8B EC ED ED ED 0D 3F 60 00 67 FD 6D 51 BC DD DD 00 00 07 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 70 2F 00 00 03 2E 3C 20 E0 00 00 00 00 00 06 8C + 39 01 00 00 00 00 02 C0 31 + /* ESD config */ + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 22 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 CB 0B 01 0B EC 03 05 08 CF 14 FA FA E7 05 EE EE F2 00 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-flat-on-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 1D BE 82 29 00 00 00 30 30 30 40 40 40 4B 4B 4B 50 50 50 5C 4D 89 9B 73 00 33 69 12 7A 70 + 39 01 00 00 00 00 02 F7 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-flat-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-flat-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 1D BE 82 09 00 00 00 30 30 30 40 40 40 4B 4B 4B 50 50 50 5C 4D 89 CB B8 00 33 69 12 7A 70 + 39 01 00 00 00 00 02 F7 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-flat-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi new file mode 100644 index 000000000000..45b9d84193d4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi @@ -0,0 +1,242 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_ss_fhd_ea8076_cmd: qcom,mdss_dsi_ss_fhd_ea8076_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + /* trig-flags: falling-0x0002 rasing-0x0001 */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-off-dimming-delay = <85>; + + qcom,elvss_dimming_check_enable; + qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 B0 07]; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 B7 01 4B + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A /* esd */ + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 23 //osc + 39 00 00 00 00 00 02 D1 0F + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 B9 A1 4A 00 1A B8 + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 10 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 D2 0A 05 1A E6 00 04 07 F5 0C DC DB E8 0F DD EE E9 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi new file mode 100644 index 000000000000..ffcca35361db --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi @@ -0,0 +1,242 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_ss_fhd_ea8076_global_cmd: qcom,mdss_dsi_ss_fhd_ea8076_global_cmd { + qcom,mdss-dsi-panel-name = "samsung ea8076 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "SAMSUNG FHD EA8076 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + /* trig-flags: falling-0x0002 rasing-0x0001 */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-off-dimming-delay = <85>; + + qcom,elvss_dimming_check_enable; + qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command = [39 01 00 00 00 00 02 B0 07]; + qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; + qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <27>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1103000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0A 00 02 11 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 B7 01 4B + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 05 2B 00 00 09 23 + 39 00 00 00 00 00 03 F0 5A 5A /* esd */ + 39 00 00 00 00 00 03 FC 5A 5A + 39 00 00 00 00 00 02 B0 23 //osc + 39 00 00 00 00 00 02 D1 11 + 39 00 00 00 00 00 0C E9 11 55 A6 75 A3 B9 A1 4A 00 1A B8 + 39 00 00 00 00 00 07 E1 00 00 02 02 42 02 + 39 00 00 00 00 00 07 E2 00 00 00 00 00 00 + 39 00 00 00 00 00 02 B0 0C + 39 00 00 00 00 00 02 E1 19 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + 39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 43 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 D4 8B + 39 00 00 00 00 00 02 B0 A5 + 39 00 00 00 00 00 02 C7 00 + 39 00 00 00 00 00 02 B0 69 + 39 00 00 00 00 00 03 B9 08 8F + 39 01 00 00 00 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 10 00 02 28 00 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + /* CRC Enable + sRGB mode */ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 BD 02 00 14 D1 00 04 07 AA 0C EC CB C8 0F DD D9 E4 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + /* CRC Enable + DCI-P3 mode */ + 39 01 00 00 00 00 02 81 91 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Enable */ + 39 01 00 00 00 00 02 B1 00 + /* Set Offset P2*/ + 39 01 00 00 00 00 02 B0 01 + /* CRC LUT(sRGB mode) */ + 39 01 00 00 00 00 16 B1 AE 0C 05 3F C6 14 05 07 AA 4A DD C8 C3 14 C0 E8 DC 19 FF F4 D9 + /* Set Offset P23*/ + 39 01 00 00 00 00 02 B0 16 + /* CRC LUT(DCI-P3 mode) */ + 39 01 00 00 00 00 16 B1 D2 0A 05 1A E6 00 04 07 F5 0C DC DB E8 0F DD EE E9 05 FF FF FF + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + /* CRC Disable (Normal mode) */ + 39 01 00 00 00 00 02 81 00 + 39 01 00 00 00 00 03 F0 5A 5A + /* CRC Bypass */ + 39 01 00 00 00 00 02 B1 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi new file mode 100644 index 000000000000..e0041d04d281 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi @@ -0,0 +1,163 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_ss_notch_fhd_ea8074_cmd: qcom,mdss_dsi_ss_notch_fhd_ea8074_cmd { + qcom,mdss-dsi-panel-name = "ss notch fhd cmd dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-model = "SS NOTCH FHD EA8074 CMD PANEL"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <1 1>, <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <142>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + //qcom,esd-err-irq-gpio = <&tlmm 52 0x2002>; /* trig-flags: falling-0x0002 rasing-0x0001*/ + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2248>; + qcom,mdss-dsi-h-front-porch = <56>; + qcom,mdss-dsi-h-back-porch = <56>; + qcom,mdss-dsi-h-pulse-width = <18>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <24>; + qcom,mdss-dsi-v-front-porch = <26>; + qcom,mdss-dsi-v-pulse-width = <12>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0a 00 02 11 00 + 39 00 00 00 00 00 05 2B 00 00 08 c7 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 05 + 39 00 00 00 00 00 02 B1 10 + 39 00 00 00 00 00 02 B0 02 + 39 00 00 00 00 00 05 D5 02 17 54 14 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 51 00 00 + 39 00 00 00 00 00 02 53 20 + 39 01 00 00 6E 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 ef b0 + 39 00 00 00 00 00 02 b0 17 + 39 00 00 00 00 00 04 E3 00 00 00 + 39 01 00 00 01 00 02 53 22 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 ef b0 + 39 00 00 00 00 00 02 b0 17 + 39 00 00 00 00 00 04 E3 00 00 00 + 39 01 00 00 01 00 02 53 23 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 00 00 02 28 00 + 39 00 00 00 00 00 03 51 00 00 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 b0 17 + 39 00 00 00 00 00 04 E3 86 80 01 + 39 00 00 00 00 00 02 53 28 + 39 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 e8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [39 00 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B2 00 40 + 39 00 00 00 00 00 02 B0 04 + 39 00 00 00 00 00 02 B2 80 + 39 00 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B2 00 10 + 39 00 00 00 00 00 02 B0 04 + 39 00 00 00 00 00 02 B2 00 + 39 00 00 00 00 00 02 F7 03 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 02 53 e0]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod2norm-command = [39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B2 00 40 + 39 00 00 00 00 00 02 B0 04 + 39 00 00 00 00 00 02 B2 80 + 39 00 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod2norm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-tianma-fhd-nt36672a-video.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-tianma-fhd-nt36672a-video.dtsi new file mode 100644 index 000000000000..be6ecd084189 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-tianma-fhd-nt36672a-video.dtsi @@ -0,0 +1,387 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_tianma_fhd_nt36672a_video: qcom,mdss_dsi_tianma_fhd_nt36672a_video { + qcom,mdss-dsi-panel-name = "tianma fhd vide dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "TIANMA FHD NT36672A VIDE PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + +// + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0x0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <136>; + qcom,cont-splash-enabled; + qcom,mdss-dsi-tx-eot-append; + qcom,esd-err-irq-gpio = <&tlmm 5 0x2001>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <44>;//debug + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <15>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + /* skin enhancement mode */ + 15 01 00 00 00 00 02 FF 22 + 15 00 00 00 00 00 02 00 40 + 15 00 00 00 00 00 02 01 C0 + 15 00 00 00 00 00 02 02 40 + 15 00 00 00 00 00 02 03 40 + 15 00 00 00 00 00 02 04 40 + 15 00 00 00 00 00 02 05 40 + 15 00 00 00 00 00 02 06 40 + 15 00 00 00 00 00 02 07 40 + 15 00 00 00 00 00 02 08 40 + 15 00 00 00 00 00 02 09 40 + 15 00 00 00 00 00 02 0A 40 + 15 00 00 00 00 00 02 0B 40 + 15 00 00 00 00 00 02 0C 40 + 15 00 00 00 00 00 02 0D 40 + 15 00 00 00 00 00 02 0E 40 + 15 00 00 00 00 00 02 0F 40 + 15 00 00 00 00 00 02 10 40 + 15 00 00 00 00 00 02 11 50 + 15 00 00 00 00 00 02 12 60 + 15 00 00 00 00 00 02 13 70 + 15 00 00 00 00 00 02 14 58 + 15 00 00 00 00 00 02 15 68 + 15 00 00 00 00 00 02 16 78 + 15 01 00 00 00 00 02 17 77 + 15 00 00 00 00 00 02 18 39 + 15 00 00 00 00 00 02 19 2D + 15 00 00 00 00 00 02 1A 2E + 15 00 00 00 00 00 02 1B 32 + 15 00 00 00 00 00 02 1C 37 + 15 00 00 00 00 00 02 1D 3A + 15 00 00 00 00 00 02 1E 40 + 15 00 00 00 00 00 02 1F 40 + 15 00 00 00 00 00 02 20 40 + 15 00 00 00 00 00 02 21 40 + 15 00 00 00 00 00 02 22 40 + 15 00 00 00 00 00 02 23 40 + 15 00 00 00 00 00 02 24 40 + 15 00 00 00 00 00 02 25 40 + 15 00 00 00 00 00 02 26 40 + 15 00 00 00 00 00 02 27 40 + 15 00 00 00 00 00 02 28 40 + 15 00 00 00 00 00 02 2D 00 + 15 00 00 00 00 00 02 2F 40 + 15 00 00 00 00 00 02 30 40 + 15 00 00 00 00 00 02 31 40 + 15 00 00 00 00 00 02 32 40 + 15 00 00 00 00 00 02 33 40 + 15 00 00 00 00 00 02 34 40 + 15 01 00 00 00 00 02 35 40 + 15 00 00 00 00 00 02 36 40 + 15 00 00 00 00 00 02 37 40 + 15 00 00 00 00 00 02 38 40 + 15 00 00 00 00 00 02 39 40 + 15 00 00 00 00 00 02 3A 40 + 15 00 00 00 00 00 02 3B 40 + 15 00 00 00 00 00 02 3D 40 + 15 00 00 00 00 00 02 3F 40 + 15 00 00 00 00 00 02 40 40 + 15 00 00 00 00 00 02 41 40 + 15 00 00 00 00 00 02 42 40 + 15 00 00 00 00 00 02 43 40 + 15 00 00 00 00 00 02 44 40 + 15 00 00 00 00 00 02 45 40 + 15 00 00 00 00 00 02 46 40 + 15 00 00 00 00 00 02 47 40 + 15 00 00 00 00 00 02 48 40 + 15 00 00 00 00 00 02 49 40 + 15 00 00 00 00 00 02 4A 40 + 15 00 00 00 00 00 02 4B 40 + 15 00 00 00 00 00 02 4C 40 + 15 00 00 00 00 00 02 4D 40 + 15 00 00 00 00 00 02 4E 40 + 15 00 00 00 00 00 02 4F 40 + 15 01 00 00 00 00 02 50 40 + 15 00 00 00 00 00 02 51 40 + 15 00 00 00 00 00 02 52 40 + 15 00 00 00 00 00 02 53 01 + 15 00 00 00 00 00 02 54 01 + 15 00 00 00 00 00 02 55 FE + 15 00 00 00 00 00 02 56 77 + 15 00 00 00 00 00 02 58 CD + 15 00 00 00 00 00 02 59 D0 + 15 00 00 00 00 00 02 5A D0 + 15 00 00 00 00 00 02 5B 50 + 15 00 00 00 00 00 02 5C 50 + 15 00 00 00 00 00 02 5D 50 + 15 00 00 00 00 00 02 5E 50 + 15 00 00 00 00 00 02 5F 50 + 15 00 00 00 00 00 02 60 50 + 15 00 00 00 00 00 02 61 50 + 15 00 00 00 00 00 02 62 50 + 15 00 00 00 00 00 02 63 50 + 15 00 00 00 00 00 02 64 50 + 15 00 00 00 00 00 02 65 50 + 15 00 00 00 00 00 02 66 50 + 15 00 00 00 00 00 02 67 50 + 15 00 00 00 00 00 02 68 50 + 15 00 00 00 00 00 02 69 50 + 15 01 00 00 00 00 02 6A 50 + 15 00 00 00 00 00 02 6B 50 + 15 00 00 00 00 00 02 6C 50 + 15 00 00 00 00 00 02 6D 50 + 15 00 00 00 00 00 02 6E 50 + 15 00 00 00 00 00 02 6F 50 + 15 00 00 00 00 00 02 70 07 + 15 00 00 00 00 00 02 71 00 + 15 00 00 00 00 00 02 72 00 + 15 00 00 00 00 00 02 73 00 + 15 00 00 00 00 00 02 74 06 + 15 00 00 00 00 00 02 75 0C + 15 00 00 00 00 00 02 76 03 + 15 00 00 00 00 00 02 77 09 + 15 00 00 00 00 00 02 78 0F + 15 00 00 00 00 00 02 79 68 + 15 00 00 00 00 00 02 7A 88 + 15 00 00 00 00 00 02 7C 80 + 15 00 00 00 00 00 02 7D 80 + 15 00 00 00 00 00 02 7E 80 + 15 00 00 00 00 00 02 7F 00 + 15 00 00 00 00 00 02 80 00 + 15 00 00 00 00 00 02 81 00 + 15 00 00 00 00 00 02 83 01 + 15 00 00 00 00 00 02 84 00 + 15 01 00 00 00 00 02 85 80 + 15 00 00 00 00 00 02 86 80 + 15 00 00 00 00 00 02 87 80 + 15 00 00 00 00 00 02 88 40 + 15 00 00 00 00 00 02 89 91 + 15 00 00 00 00 00 02 8A 98 + 15 00 00 00 00 00 02 8B 80 + 15 00 00 00 00 00 02 8C 80 + 15 00 00 00 00 00 02 8D 80 + 15 00 00 00 00 00 02 8E 80 + 15 00 00 00 00 00 02 8F 80 + 15 00 00 00 00 00 02 90 80 + 15 00 00 00 00 00 02 91 80 + 15 00 00 00 00 00 02 92 80 + 15 00 00 00 00 00 02 93 80 + 15 00 00 00 00 00 02 94 80 + 15 00 00 00 00 00 02 95 80 + 15 00 00 00 00 00 02 96 80 + 15 00 00 00 00 00 02 97 80 + 15 00 00 00 00 00 02 98 80 + 15 00 00 00 00 00 02 99 80 + 15 00 00 00 00 00 02 9A 80 + 15 00 00 00 00 00 02 9B 80 + 15 00 00 00 00 00 02 9C 80 + 15 00 00 00 00 00 02 9D 80 + 15 01 00 00 00 00 02 9E 80 + 15 00 00 00 00 00 02 9F 80 + 15 00 00 00 00 00 02 A0 8A + 15 00 00 00 00 00 02 A2 80 + 15 00 00 00 00 00 02 A6 80 + 15 00 00 00 00 00 02 A7 80 + 15 00 00 00 00 00 02 A9 80 + 15 00 00 00 00 00 02 AA 80 + 15 00 00 00 00 00 02 AB 80 + 15 00 00 00 00 00 02 AC 80 + 15 00 00 00 00 00 02 AD 80 + 15 00 00 00 00 00 02 AE 80 + 15 00 00 00 00 00 02 AF 80 + 15 00 00 00 00 00 02 B7 76 + 15 00 00 00 00 00 02 B8 76 + 15 00 00 00 00 00 02 B9 05 + 15 00 00 00 00 00 02 BA 0D + 15 00 00 00 00 00 02 BB 14 + 15 00 00 00 00 00 02 BC 0F + 15 00 00 00 00 00 02 BD 18 + 15 00 00 00 00 00 02 BE 1F + 15 00 00 00 00 00 02 BF 05 + 15 00 00 00 00 00 02 C0 0D + 15 00 00 00 00 00 02 C1 14 + 15 00 00 00 00 00 02 C2 03 + 15 01 00 00 00 00 02 C3 07 + 15 00 00 00 00 00 02 C4 0A + 15 00 00 00 00 00 02 C5 A0 + 15 00 00 00 00 00 02 C6 55 + 15 00 00 00 00 00 02 C7 FF + 15 00 00 00 00 00 02 C8 39 + 15 00 00 00 00 00 02 C9 44 + 15 00 00 00 00 00 02 CA 12 + 15 00 00 00 00 00 02 CD 80 + 15 00 00 00 00 00 02 DB 80 + 15 00 00 00 00 00 02 DC 80 + 15 00 00 00 00 00 02 DD 80 + 15 00 00 00 00 00 02 E0 80 + 15 00 00 00 00 00 02 E1 80 + 15 00 00 00 00 00 02 E2 80 + 15 00 00 00 00 00 02 E3 80 + 15 00 00 00 00 00 02 E4 80 + 15 00 00 00 00 00 02 E5 40 + 15 00 00 00 00 00 02 E6 40 + 15 00 00 00 00 00 02 E7 40 + 15 00 00 00 00 00 02 E8 40 + 15 00 00 00 00 00 02 E9 40 + 15 00 00 00 00 00 02 EA 40 + 15 00 00 00 00 00 02 EB 40 + 15 00 00 00 00 00 02 EC 40 + 15 00 00 00 00 00 02 ED 40 + 15 00 00 00 00 00 02 EE 40 + 15 00 00 00 00 00 02 EF 40 + 15 00 00 00 00 00 02 F0 40 + 15 00 00 00 00 00 02 F1 40 + 15 00 00 00 00 00 02 F2 40 + 15 00 00 00 00 00 02 F3 40 + 15 00 00 00 00 00 02 F4 40 + 15 00 00 00 00 00 02 F5 40 + 15 00 00 00 00 00 02 F6 40 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 FF 23 + 15 00 00 00 00 00 02 FB 01 + /* dimming enable */ + 15 00 00 00 00 00 02 01 84 + 15 00 00 00 00 00 02 05 2D + 15 00 00 00 00 00 02 06 00 + /* resolution 1080*2246 */ + 15 00 00 00 00 00 02 11 01 + 15 00 00 00 00 00 02 12 7B + 15 00 00 00 00 00 02 15 6F + 15 00 00 00 00 00 02 16 0B + /* UI mode */ + 15 00 00 00 00 00 02 29 0A + 15 00 00 00 00 00 02 30 FF + 15 00 00 00 00 00 02 31 FF + 15 00 00 00 00 00 02 32 FF + 15 00 00 00 00 00 02 33 FF + 15 00 00 00 00 00 02 34 FF + 15 00 00 00 00 00 02 35 FF + 15 00 00 00 00 00 02 36 FF + 15 00 00 00 00 00 02 37 FF + 15 00 00 00 00 00 02 38 FC + 15 01 00 00 00 00 02 39 F8 + 15 00 00 00 00 00 02 3A F4 + 15 00 00 00 00 00 02 3B F1 + 15 00 00 00 00 00 02 3D EE + 15 00 00 00 00 00 02 3F EB + 15 00 00 00 00 00 02 40 E8 + 15 00 00 00 00 00 02 41 E5 + /* STILL mode */ + 15 00 00 00 00 00 02 2A 13 + 15 00 00 00 00 00 02 45 FF + 15 00 00 00 00 00 02 46 FF + 15 00 00 00 00 00 02 47 FF + 15 00 00 00 00 00 02 48 FF + 15 00 00 00 00 00 02 49 FF + 15 00 00 00 00 00 02 4A FF + 15 00 00 00 00 00 02 4B FF + 15 00 00 00 00 00 02 4C FF + 15 00 00 00 00 00 02 4D ED + 15 00 00 00 00 00 02 4E D5 + 15 00 00 00 00 00 02 4F BF + 15 00 00 00 00 00 02 50 A6 + 15 01 00 00 00 00 02 51 96 + 15 00 00 00 00 00 02 52 86 + 15 00 00 00 00 00 02 53 76 + 15 00 00 00 00 00 02 54 66 + /* MOVING mode */ + 15 00 00 00 00 00 02 2B 0E + 15 00 00 00 00 00 02 58 FF + 15 00 00 00 00 00 02 59 FF + 15 00 00 00 00 00 02 5A FF + 15 00 00 00 00 00 02 5B FF + 15 00 00 00 00 00 02 5C FF + 15 00 00 00 00 00 02 5D FF + 15 00 00 00 00 00 02 5E FF + 15 00 00 00 00 00 02 5F FF + 15 00 00 00 00 00 02 60 F6 + 15 00 00 00 00 00 02 61 EA + 15 00 00 00 00 00 02 62 E1 + 15 00 00 00 00 00 02 63 D8 + 15 00 00 00 00 00 02 64 CE + 15 00 00 00 00 00 02 65 C3 + 15 00 00 00 00 00 02 66 BA + 15 01 00 00 00 00 02 67 B3 + 15 01 00 00 00 00 02 FF 25 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 05 04 + 15 01 00 00 00 00 02 FF 26 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 1C AF + 15 01 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 51 FF + 15 00 00 00 00 00 02 53 24 + 15 00 00 00 00 00 02 55 00 + 05 01 00 00 00 00 02 29 00 + 05 01 00 00 46 00 02 11 00 + 15 01 00 00 00 00 02 FF 24 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 C3 01 + 15 00 00 00 00 00 02 C4 55 + 15 00 00 00 00 00 02 C5 55 + 15 01 00 00 00 00 02 FF 10 + ]; + + qcom,mdss-dsi-off-command = [ + 15 01 00 00 00 00 02 FF 24 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 C3 00 + 15 01 00 00 00 00 02 FF 10 + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 3C 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-visionox-fhd-r66456-f11-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-visionox-fhd-r66456-f11-cmd.dtsi new file mode 100644 index 000000000000..d11acb5b345f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-visionox-fhd-r66456-f11-cmd.dtsi @@ -0,0 +1,167 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_visionox_fhd_r66456_f11_cmd: qcom,mdss_dsi_visionox_fhd_r66456_f11_cmd { + qcom,mdss-dsi-panel-name = "visionox r66456 fhd cmd dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "VISIONOX FHD R66456 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,ulps-enabled; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-brightness-remap; + qcom,mdss-brightness-max-level = <2047>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-dcs-type-ss; + qcom,mdss-dsi-reset-sequence = <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <147>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,dispparam-enabled; + qcom,mdss-panel-on-dimming-delay = <120>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; + + qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-off-dimming-delay = <85>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <64>; + qcom,mdss-dsi-h-back-porch = <64>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <64>; + qcom,mdss-dsi-v-front-porch = <64>; + qcom,mdss-dsi-v-pulse-width = <20>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-jitter = <0x5 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 B0 00 + 39 00 00 00 00 00 2C BB 59 FF FF FF EF CF AB 87 63 3F 4A 48 46 44 42 40 3E 3C 3A 64 00 FF FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 00 02 02 42 00 + 39 00 00 00 00 00 03 D4 00 8D + 39 00 00 00 00 00 02 FA 0F + 39 01 00 00 00 00 02 B0 80 + /* NVM load control */ + 39 00 00 00 00 00 02 E6 00 + /* TE Control*/ + 39 00 00 00 00 00 02 35 00 + /* SET Column Start Adress*/ + 39 00 00 00 00 00 05 2A 00 00 04 37 + /* SET Row Start Adress*/ + 39 00 00 00 00 00 05 2B 00 00 09 23 + /* brightness control */ + 39 00 00 00 00 00 03 51 01 00 + /* sleep out */ + 05 01 00 00 6E 00 02 11 00 + /* display on */ + 05 01 00 00 00 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 02 88 00 + 39 01 00 00 00 00 02 53 E0]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-doze-hbm-command = [ + 39 00 00 00 00 00 03 51 00 FF + 39 01 00 00 00 00 02 88 01]; + qcom,mdss-dsi-doze-lbm-command = [ + 39 00 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 88 01]; + qcom,mdss-dsi-nolp-command = [ + 39 00 00 00 00 00 02 88 00]; + qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 01];/* 50% */ + qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 40% */ + qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 03];/* 30% */ + qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; + qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; + qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; + + + qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; + qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + /* + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ + ]; + qcom,mdss-dsi-dispparam-crc-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command = [ + ]; + qcom,mdss-dsi-dispparam-crc-dcip3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-off-command = [ + ]; + qcom,mdss-dsi-dispparam-crc-off-command-state = "dsi_lp_mode"; + */ + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150.dtsi new file mode 100644 index 000000000000..6b2f14bcefc6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150.dtsi @@ -0,0 +1,35 @@ +&spmi_bus { + qcom,pm8150@0 { + qcom,power-on@800 { + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <62500>; + + qcom,pon_1 { + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <4480>; + qcom,s2-timer = <2000>; + qcom,s2-type = <0x7>; + }; + + qcom,pon_3 { + qcom,pon-type = ; + qcom,support-reset = <1>; + qcom,pull-up = <1>; + qcom,s1-timer = <1352>; + qcom,s2-timer = <2000>; + qcom,s2-type = <0x1>; + qcom,use-bark; + }; + }; + }; +}; + +&pm8150_rtc { + qcom,qpnp-rtc-alarm-pwrup = <1>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150b.dtsi new file mode 100644 index 000000000000..684a1284886d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150b.dtsi @@ -0,0 +1,33 @@ +&pm8150b_gpios { + interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>, + <0x2 0xc1 0 IRQ_TYPE_NONE>, + <0x2 0xc4 0 IRQ_TYPE_NONE>, + <0x2 0xc5 0 IRQ_TYPE_NONE>, + <0x2 0xc6 0 IRQ_TYPE_NONE>, + <0x2 0xc7 0 IRQ_TYPE_NONE>, + <0x2 0xc8 0 IRQ_TYPE_NONE>, + <0x2 0xc9 0 IRQ_TYPE_NONE>, + <0x2 0xca 0 IRQ_TYPE_NONE>, + <0x2 0xcb 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150b_gpio1", "pm8150b_gpio2", + "pm8150b_gpio5", "pm8150b_gpio6", + "pm8150b_gpio7", + "pm8150b_gpio8", "pm8150b_gpio9", + "pm8150b_gpio10", "pm8150b_gpio11", + "pm8150b_gpio12"; + qcom,gpios-disallowed = <3 4>; +}; + +&ibat_lvl0 { + temperature = <5500>; +}; + +&ibat_lvl1 { + temperature = <8000>; +}; + +&thermal_zones { + soc { + disable-thermal-zone; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150l.dtsi new file mode 100644 index 000000000000..a0544c78b85e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/pm8150l.dtsi @@ -0,0 +1,59 @@ +&pm8150l_gpios { + interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>, + <0x4 0xc1 0 IRQ_TYPE_NONE>, + <0x4 0xc2 0 IRQ_TYPE_NONE>, + <0x4 0xc3 0 IRQ_TYPE_NONE>, + <0x4 0xc4 0 IRQ_TYPE_NONE>, + <0x4 0xc5 0 IRQ_TYPE_NONE>, + <0x4 0xc6 0 IRQ_TYPE_NONE>, + <0x4 0xc7 0 IRQ_TYPE_NONE>, + <0x4 0xc8 0 IRQ_TYPE_NONE>, + <0x4 0xc9 0 IRQ_TYPE_NONE>, + <0x4 0xca 0 IRQ_TYPE_NONE>, + <0x4 0xcb 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150l_gpio1", "pm8150l_gpio2", + "pm8150l_gpio3", "pm8150l_gpio4", + "pm8150l_gpio5", "pm8150l_gpio6", + "pm8150l_gpio7", + "pm8150l_gpio8", "pm8150l_gpio9", + "pm8150l_gpio10", "pm8150l_gpio11", + "pm8150l_gpio12"; + /delete-property/ qcom,gpios-disallowed; +}; + +&pm8150l_adc_tm { + io-channels = <&pm8150l_vadc ADC_AMUX_THM1_PU2>, + <&pm8150l_vadc ADC_AMUX_THM2_PU2>, + <&pm8150l_vadc ADC_GPIO3_PU2>; +}; + +&pm8150l_flash2 { + status = "ok"; +}; + +&pm8150l_torch2 { + status = "ok"; +}; + +&flash_led { + pm8150l_flashlight: qcom,flashlight { + label = "flash"; + qcom,led-name = "flashlight"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flashlight_trigger"; + qcom,id = <3>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; +}; + +&pm8150l_pwm { + status = "disabled"; +}; + +&red_led { + /delete-property/ linux,default-trigger; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-audio-overlay.dtsi new file mode 100644 index 000000000000..f92cf102314c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-audio-overlay.dtsi @@ -0,0 +1,57 @@ +#include "../../../sm8150-audio-overlay.dtsi" + +&snd_9360 { + status = "disabled"; +}; + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS3", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + + qcom,wsa-max-devs = <0>; + + pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", + "quat_tdm_enable", "quat_tdm_disable"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active + &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; +}; + +&wcd934x_cdc { + qcom,cdc-micbias1-mv = <2700>; + qcom,cdc-micbias3-mv = <2700>; + qcom,cdc-micbias4-mv = <2700>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-pmic-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-pmic-overlay.dtsi new file mode 100644 index 000000000000..28c6e41ad394 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-pmic-overlay.dtsi @@ -0,0 +1,28 @@ +#include "../../../sm8150-pmic-overlay.dtsi" + +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +&pm8150b_gpios { + otg_vbus_boost { + otg_vbus_boost_default: otg_vbus_boost_default { + pins = "gpio12"; + function = "normal"; + output-low; + power-source = <0>; + }; + }; + + power_good { + /*Get the DC Power Good signal*/ + power_good_default: power_good_default { + pins = "gpio7"; + function = "normal"; + qcom,drive-strength = <2>; /* 2 MA */ + bias-disable; /* NO pull */ + power-source = <1>; + input-enable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-sde-display.dtsi new file mode 100644 index 000000000000..be96cd1252af --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/sm8150-sde-display.dtsi @@ -0,0 +1,532 @@ +#include "../../../sm8150-sde-display.dtsi" + +#include "display/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi" +#include "display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi" +#include "display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi" +#include "display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi" +#include "display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi" +#include "display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi" +#include "display/dsi-panel-tianma-fhd-nt36672a-video.dtsi" +#include "display/dsi-panel-ss-fhd-ea8076-cmd.dtsi" +#include "display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi" +#include "display/dsi-panel-visionox-fhd-r66456-f11-cmd.dtsi" +#include "display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi" +#include "display/dsi-panel-j20s-36-02-0a-lcd-dsc-vid.dtsi" +#include "display/dsi-panel-j20s-42-02-0b-lcd-dsc-vid.dtsi" +#include "display/dsi-panel-k82-42-02-0a-video.dtsi" +#include "display/dsi-panel-k82-36-02-0b-video.dtsi" + +&display_panel_avdd_eldo { + status = "disabled"; +}; + +&soc { + dsi_amoled_panel_pwr_supply: dsi_amoled_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + //qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <10>; + qcom,supply-pre-off-sleep = <10>; + }; + }; + + dsi_amoled_panel_pwr_external_supply: dsi_amoled_panel_pwr_external_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + //qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vcie"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <10>; + qcom,supply-pre-off-sleep = <10>; + }; + }; + + dsi_panel_pwr_supply_k82_vddio: dsi_panel_pwr_supply_k82_vddio { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + qcom,supply-post-off-sleep = <10>; + }; + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "enp"; + qcom,supply-min-voltage = <5500000>; + qcom,supply-max-voltage = <5500000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-on-sleep = <10>; + qcom,supply-post-off-sleep = <10>; + }; + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "enn"; + qcom,supply-min-voltage = <5500000>; + qcom,supply-max-voltage = <5500000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-on-sleep = <10>; + qcom,supply-post-off-sleep = <10>; + }; + }; +}; + +&soc { + dsi_ss_ea8074_fhd_cmd_display: qcom,dsi-display@24 { + label = "dsi_ss_ea8074_fhd_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_ss_notch_fhd_ea8074_cmd>; + }; + + dsi_samsung_fhd_ea8076_cmd_display: qcom,dsi-display@25 { + label = "dsi_samsung_fhd_ea8076_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_samsung_fhd_ea8076_cmd>; + }; + + dsi_samsung_fhd_ea8076_f1_cmd_display: qcom,dsi-display@26 { + label = "dsi_samsung_fhd_ea8076_f1_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_samsung_fhd_ea8076_f1_cmd>; + }; + + dsi_samsung_fhd_ea8076_f1mp_cmd_display: qcom,dsi-display@27 { + label = "dsi_samsung_fhd_ea8076_f1mp_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_samsung_fhd_ea8076_f1mp_cmd>; + }; + + dsi_samsung_fhd_ea8076_f1p2_2_cmd_display: qcom,dsi-display@28 { + label = "dsi_samsung_fhd_ea8076_f1p2_2_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_samsung_fhd_ea8076_f1p2_2_cmd>; + }; + + dsi_samsung_fhd_ea8076_f1p2_cmd_display: qcom,dsi-display@29 { + label = "dsi_samsung_fhd_ea8076_f1p2_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_samsung_fhd_ea8076_f1p2_cmd>; + }; + + dsi_tianma_fhd_nt36672a_video_display: qcom,dsi-display@30 { + label = "dsi_tianma_fhd_nt36672a_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_tianma_fhd_nt36672a_video>; + }; + + dsi_ss_fhd_ea8076_cmd_display: qcom,dsi-display@31 { + label = "dsi_ss_fhd_ea8076_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_ss_fhd_ea8076_cmd>; + }; + + dsi_visionox_fhd_r66456_f11_cmd_display: qcom,dsi-display@32 { + label = "dsi_visionox_fhd_r66456_f11_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_visionox_fhd_r66456_f11_cmd>; + }; + + dsi_ss_fhd_ea8076_global_cmd_display: qcom,dsi-display@33 { + label = "dsi_ss_fhd_ea8076_global_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_ss_fhd_ea8076_global_cmd>; + }; + + dsi_samsung_fhd_ea8076_f1s_cmd_display: qcom,dsi-display@34 { + label = "dsi_samsung_fhd_ea8076_f1s_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_samsung_fhd_ea8076_f1s_cmd>; + }; + + dsi_j20s_36_02_0a_video_display: qcom,dsi-display@35{ + label = "dsi_j20s_36_02_0a_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,ulps-enabled; + qcom,dsi-panel = <&dsi_j20s_36_02_0a_video>; + }; + + dsi_j20s_42_02_0b_video_display: qcom,dsi-display@36 { + label = "dsi_j20s_42_02_0b_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + qcom,ulps-enabled; + qcom,dsi-panel = <&dsi_j20s_42_02_0b_video>; + }; + + dsi_k82_42_02_0a_dual_cphy_vid_display: qcom,dsi-display@37 { + label = "dsi_k82_42_02_0a_dual_cphy_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + + qcom,dsi-panel = <&dsi_k82_42_02_0a_dual_cphy_video>; + }; + + dsi_k82_36_02_0b_dual_cphy_vid_display: qcom,dsi-display@38 { + label = "dsi_k82_36_02_0b_dual_cphy_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "cphy_byte_clk0", "cphy_pixel_clk0"; + + qcom,dsi-panel = <&dsi_k82_36_02_0b_dual_cphy_video>; + }; +}; + +&sde_dsi { + /delete-property/ vdd-supply; + vci-supply = <&pm8150_l13>; + + qcom,dsi-display-list = + <&dsi_sharp_4k_dsc_video_display + &dsi_sharp_4k_dsc_cmd_display + &dsi_sharp_1080_cmd_display + &dsi_dual_sharp_1080_120hz_cmd_display + &dsi_dual_nt35597_truly_video_display + &dsi_dual_nt35597_truly_cmd_display + &dsi_nt35597_truly_dsc_cmd_display + &dsi_nt35597_truly_dsc_video_display + &dsi_sim_vid_display + &dsi_dual_sim_vid_display + &dsi_sim_cmd_display + &dsi_dual_sim_cmd_display + &dsi_sim_dsc_375_cmd_display + &dsi_dual_sim_dsc_375_cmd_display + &dsi_sw43404_amoled_cmd_display + &dsi_nt35695b_truly_fhd_cmd_display + &dsi_nt35695b_truly_fhd_video_display + &dsi_sw43404_amoled_video_display + &dsi_sw43404_amoled_fhd_plus_cmd_display + &dsi_ss_ea8074_fhd_cmd_display + &dsi_samsung_fhd_ea8076_cmd_display + &dsi_samsung_fhd_ea8076_f1_cmd_display + &dsi_samsung_fhd_ea8076_f1mp_cmd_display + &dsi_samsung_fhd_ea8076_f1p2_2_cmd_display + &dsi_samsung_fhd_ea8076_f1p2_cmd_display + &dsi_tianma_fhd_nt36672a_video_display + &dsi_dual_nt36850_truly_cmd_display + &dsi_ss_fhd_ea8076_cmd_display + &dsi_visionox_fhd_r66456_f11_cmd_display + &dsi_ss_fhd_ea8076_global_cmd_display + &dsi_samsung_fhd_ea8076_f1s_cmd_display + &dsi_rm69299_visionox_amoled_vid_display + &dsi_j20s_36_02_0a_video_display + &dsi_j20s_42_02_0b_video_display + &dsi_k82_42_02_0a_dual_cphy_vid_display + &dsi_k82_36_02_0b_dual_cphy_vid_display>; +}; + +&sde_dsi1 { + /delete-property/ vdd-supply; +}; + +/* +&sde_dp { + /delete-property/ qcom,dp-aux-switch; +}; +*/ + +&dsi_ss_notch_fhd_ea8074_cmd { + qcom,mdss-dsi-t-clk-post = <0x19>; + qcom,mdss-dsi-t-clk-pre = <0x1C>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 08 09 25 23 09 + 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_samsung_fhd_ea8076_cmd { + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_samsung_fhd_ea8076_f1_cmd { + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_samsung_fhd_ea8076_f1mp_cmd { + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_samsung_fhd_ea8076_f1p2_cmd { + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_samsung_fhd_ea8076_f1p2_2_cmd { + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_tianma_fhd_nt36672a_video { + qcom,mdss-dsi-t-clk-post = <0x18>; + qcom,mdss-dsi-t-clk-pre = <0x1B>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 25 22 09 + 08 06 03 04 00 1B 18]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ss_fhd_ea8076_cmd { + qcom,mdss-dsi-t-clk-post = <0x0F>; + qcom,mdss-dsi-t-clk-pre = <0x37>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_visionox_fhd_r66456_f11_cmd { + qcom,mdss-dsi-t-clk-post = <0x0F>; + qcom,mdss-dsi-t-clk-pre = <0x37>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ss_fhd_ea8076_global_cmd { + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A + 0A 06 03 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_samsung_fhd_ea8076_f1s_cmd { + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-clk-strength = <0xFF>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A + 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_j20s_36_02_0a_video { + qcom,mdss-dsi-t-clk-post = <0x17>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,mdss-dsi-display-timings { + /* 60 Hz */ + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_j20s_42_02_0b_video { + qcom,mdss-dsi-t-clk-post = <0x17>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,mdss-dsi-display-timings { + /* 120 Hz */ + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_k82_42_02_0a_dual_cphy_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 27 2B 0A + 19 0A 02 04 00 00 00]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; +&dsi_k82_36_02_0b_dual_cphy_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 27 2B 0A + 19 0A 02 04 00 00 00]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/smb1390.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/smb1390.dtsi new file mode 100644 index 000000000000..471e1db26a75 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/smb1390.dtsi @@ -0,0 +1,15 @@ +&qupv3_se4_i2c { + #include "../../../smb1390.dtsi" +}; + +&smb1390_slave { + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1390_slave"; + interrupt-controller; + #interrupt-cells = <3>; +}; + +&smb1390_slave_charger { + interrupt-parent = <&smb1390_slave>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sdx50-sm8150-common.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sdx50-sm8150-common.dtsi new file mode 100644 index 000000000000..d2eea3d10995 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sdx50-sm8150-common.dtsi @@ -0,0 +1,407 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "sm8150-pmic-overlay.dtsi" +#include "sm8150-sde-display.dtsi" +#include "../../../sm8150-thermal-overlay.dtsi" + +#include "../common/smb1390.dtsi" + +&qupv3_se4_i2c { +#include "../../../smb1355.dtsi" +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm8150_l7>; + qca,bt-vdd-pa-supply = <&pm8150l_l2>; + qca,bt-vdd-ldo-supply = <&pm8150l_l11>; + + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + + qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + }; + + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; + vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_default + &usb2_id_det_default + &usb2_vbus_boost_default>; + }; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + ext_5v_boost: ext_5v_boost { + compatible = "regulator-fixed"; + status = "disabled"; + regulator-name = "ext_5v_boost"; + gpio = <&pm8150b_gpios 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-enable-ramp-delay = <1600>; + + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_boost_default>; + }; + + qcom_qbt1000: qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clock-frequency = <25000000>; + qcom,ipc-gpio = <&tlmm 118 0>; + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default>; + qcom,finger-detect-gpio = <&pm8150_gpios 1 0>; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_samsung_fhd_ea8076_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_samsung_fhd_ea8076_f1s_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 11 0>; +}; + +&dsi_samsung_fhd_ea8076_cmd_display { + qcom,dsi-display-active; +}; + +&qupv3_se9_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 41 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + //qcom,nq-esepwr = <&tlmm 42 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; + vdda-pll-supply = <&pm8150l_l3>; + vdda-phy-max-microamp = <90200>; + vdda-pll-max-microamp = <19000>; + + status = "ok"; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&pm8150l_wled { + qcom,string-cfg= <7>; + qcom,leds-per-string = <6>; + status = "ok"; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&pm8150b_fg { + qcom,battery-data = <&mtp_batterydata>; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&sdhc_2 { + vdd-supply = <&pm8150l_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150l_l6>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + + cd-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&wil6210 { + status = "ok"; +}; + +&mhi_0 { + mhi,fw-name = "debug.mbn"; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <3>; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "mid_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp"; + qcom,battery-data = <&mtp_batterydata>; + qcom,sw-jeita-enable; + qcom,wd-bark-time-secs = <16>; +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb_qmp_phy { + status = "ok"; +}; + +&smb1355 { + status = "ok"; +}; + +&smb1355_charger { + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "charger_temp"; + status = "ok"; +}; + +&reserved_memory { + ramdump_fb_mem: ramdump_fb_region@af000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0xaf000000 0 0x1000000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sm8150-common.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sm8150-common.dtsi new file mode 100644 index 000000000000..9516bb174226 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/xiaomi-sm8150-common.dtsi @@ -0,0 +1,527 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "sm8150-pmic-overlay.dtsi" +#include "sm8150-sde-display.dtsi" +#include "../../../sm8150-thermal-overlay.dtsi" + +&qupv3_se12_2uart { + status = "ok"; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm8150_l7>; + qca,bt-vdd-pa-supply = <&pm8150l_l2>; + qca,bt-vdd-ldo-supply = <&pm8150l_l11>; + + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + + qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; + vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_default + &usb2_id_det_default + &usb2_vbus_boost_default>; + }; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + + }; + + ext_5v_boost: ext_5v_boost { + compatible = "regulator-fixed"; + status = "disabled"; + regulator-name = "ext_5v_boost"; + gpio = <&pm8150b_gpios 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-enable-ramp-delay = <1600>; + + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_boost_default>; + }; + + qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clock-frequency = <25000000>; +/* qcom,ipc-gpio = <&tlmm 118 0>; */ + qcom,finger-detect-gpio = <&pm8150_gpios 1 0>; + status = "disabled"; + }; + + wdog: qcom,wdt@17c10000 { + qcom,bark-time = <20000>; + qcom,pet-time = <15000>; + }; +}; + + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_ss_notch_fhd_ea8074_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_samsung_fhd_ea8076_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_samsung_fhd_ea8076_f1_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_samsung_fhd_ea8076_f1mp_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_samsung_fhd_ea8076_f1p2_2_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_samsung_fhd_ea8076_f1p2_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_tianma_fhd_nt36672a_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; +// qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_ss_fhd_ea8076_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_ss_fhd_ea8076_global_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_visionox_fhd_r66456_f11_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <256>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + //qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_j20s_36_02_0a_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_j20s_42_02_0b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_k82_42_02_0a_dual_cphy_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_k82_vddio>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-brightness-max-level = <2047>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_k82_36_02_0b_dual_cphy_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_k82_vddio>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,mdss-dsi-bl-min-level = <2>; + qcom,mdss-dsi-bl-max-level = <2047>; + qcom,mdss-brightness-max-level = <2047>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&qupv3_se9_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 103 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + //qcom,nq-esepwr = <&tlmm 42 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&dsi_sim_vid_display { + qcom,dsi-display-active; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; + vdda-pll-supply = <&pm8150l_l3>; + vdda-phy-max-microamp = <90200>; + vdda-pll-max-microamp = <19000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150l_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150l_l6>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + + cd-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + + status = "disabled"; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&pm8150l_wled { + qcom,string-cfg= <7>; + qcom,leds-per-string = <6>; + status = "ok"; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&pm8150b_charger { + io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp"; +}; + +&wil6210 { + status = "ok"; +}; + +&mhi_0 { + mhi,fw-name = "debug.mbn"; +}; + +&pcie0 { + qcom,no-l1-supported; +}; + +&usb1 { + /*extcon = <&extcon_usb1>;*/ + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb_qmp_phy { + status = "ok"; +}; + +&reserved_memory { + ramdump_fb_mem: ramdump_fb_region@af000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0xaf000000 0 0x1000000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi new file mode 100644 index 000000000000..5d5c471561aa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/sm8150-audio-overlay.dtsi" + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC4", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS4", + "MIC BIAS4", "Analog Mic5"; + + qcom,uart-audio-sw-gpio = <&sbu_uart_en>; + /* qcom,adc2-switch-gpio = <&adc2_switch_gpio>; */ + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,fsa4476-gpio-support = <1>; + qcom,usbc-analog-en1-gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2-gpio = <&tlmm 32 0>; + + pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", + "quat_tdm_enable", "quat_tdm_disable", + "aud_active", "aud_sleep"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; + pinctrl-4 = <&wcd_usbc_analog_en2_active>; + pinctrl-5 = <&wcd_usbc_analog_en2_idle>; +}; + +&soc { + sbu_uart_en: msm_cdc_pinctrl@25 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sbu_uart_en_active>; + pinctrl-1 = <&sbu_uart_en_idle>; + }; + + adc2_switch_gpio: msm_cdc_pinctrl@142 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&adc2_switch_gpio_active>; + pinctrl-1 = <&adc2_switch_gpio_idle>; + }; + + wcd_usbc_analog_en1_gpio: msm_cdc_pinctrl@35 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en1_active>; + pinctrl-1 = <&wcd_usbc_analog_en1_idle>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi new file mode 100644 index 000000000000..4155e541eab1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi @@ -0,0 +1,796 @@ +/*for F1X pinctrl*/ + +&tlmm { + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio122", "gpio12", "gpio31"; + function = "gpio"; + }; + config { + pins = "gpio122", "gpio12", "gpio31"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + config { + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + /* GPIO_119 : FP_RESET_N */ + msm_gpio_119: msm_gpio_119 { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + /* GPIO_119 : FP_RESET_N, state device active*/ + msm_gpio_119_output_high: msm_gpio_119_output_high { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + /* GPIO_6 : AW8697_RESET_N */ + msm_gpio_6: msm_gpio_6 { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + /* GPIO_6 : AW8697_RESET_N, state device active*/ + msm_gpio_6_output_high: msm_gpio_6_output_high { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + /* GPIO_27 : AW8697_INTERRUPT_N */ + msm_gpio_27: msm_gpio_27 { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + txon_enable_active: txon_enable_active { + /* active state */ + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; + + txon_enable_suspend: txon_enable_suspend { + /* sleep state */ + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + nu_int_active: nu_int_active { + /* active state */ + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + nu_int_suspend: nu_int_suspend { + /* sleep state */ + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + nu_sleep_active: nu_sleep_active { + /* active state */ + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + nu_sleep_suspend: nu_sleep_suspend { + /* sleep state */ + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + ln8282_enable_active: ln8282_enable_active { + mux { + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + ln8282_enable_suspend: ln8282_enable_suspend { + mux { + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; + + halo7221_enable_active: halo7221_enable_active { + mux { + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; + halo7221_enable_suspend: halo7221_enable_suspend { + mux { + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + idt { + idt_int_active: idt_int_active { + /* active state */ + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_int_suspend: idt_int_suspend { + /* sleep state */ + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_enable_active: idt_enable_active { + /* active state */ + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + idt_enable_suspend: idt_enable_suspend { + /* sleep state */ + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + adc2_switch_gpio_ctrl { + adc2_switch_gpio_idle: adc2_switch_idle { + mux { + pins = "gpio134"; + function = "gpio"; + }; + config { + pins = "gpio134"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + adc2_switch_gpio_active: adc2_switch_active { + mux { + pins = "gpio134"; + function = "gpio"; + }; + config { + pins = "gpio134"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + vbus_disable { + vbus_disable_active: usb_vbus_active { + /* active state */ + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + output-high; + + }; + }; + + vbus_disable_suspend: usb_vbus_suspend { + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + output-low; + }; + }; + }; + + sbu_uart_en_ctrl { + sbu_uart_en_idle: uart_audio_en_idle { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + sbu_uart_en_active: uart_audio_en_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 36: NFC ENABLE 42:ESE Enable */ + pins = "gpio36", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 36: NFC ENABLE 42:ESE Enable */ + pins = "gpio36", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + wcd_usbc_analog_en2 { + wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle { + mux { + pins = "gpio32"; + function = "gpio"; + }; + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active { + mux { + pins = "gpio32"; + function = "gpio"; + }; + config { + pins = "gpio32"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; +}; + + +//camera voltage start +&cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio30", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio59"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio30", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio59"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +//camera voltage end diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..fc4332cb1d7a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150-camera-sensor-mtp.dtsi @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux1: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + wled-flash-support; + flash-source = <&wled_flash>; + torch-source = <&wled_torch>; + switch-source = <&wled_switch>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + camera_viodd_ldo: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "camera_viodd_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 132 0>; + vin-supply = <&pm8150_s4>; + }; + + actuator_rear_regulator: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "actuator_rear_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 24 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_rear_aux_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "actuator_rear_aux_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 152 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_ultra_ldo: gpio-regulator@3 { + compatible = "regulator-fixed"; + reg = <0x03 0x00>; + regulator-name = "actuator_ultra_ldo"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 95 0>; + vin-supply = <&pm8150l_bob>; + }; +}; + +&cam_cci1 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_aux_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_front: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_aux_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_ultra_rear: qcom,actuator@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&actuator_ultra_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150_s5>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1904000 2856000 0>; + rgltr-max-voltage = <1800000 2040000 3008000 0>; + rgltr-load-current = <180000 112000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 59 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150_s5>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1904000 2856000 0>; + rgltr-max-voltage = <1800000 2040000 3008000 0>; + rgltr-load-current = <180000 112000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 59 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_ultra: qcom,eeprom@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,eeprom"; + qcom,slave-addr = <0xa0>; + qcom,num-blocks = <1>; + qcom,page0 = <0 0 0 0 0 0 >; + qcom,poll0 = <0 0 0 0 0 0>; + qcom,mem0 = <8192 0x0 2 0 1 0>; + qcom,cam-power-seq-type = "cam_vio"; + qcom,cam-power-seq-val = <1>; + qcom,cam-power-seq-cfg-val = <1>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 300000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk0_suspend &cam_sensor_suspend_iris>; + gpios = <&tlmm 13 0>,//mclk + <&tlmm 28 0>,//reset + <&tlmm 94 0>;//vana,vdig + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VDIG3"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 3000000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 30000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>,//mclk + <&tlmm 54 0>,//reset + //<&tlmm 132 0>,//vio + <&tlmm 118 0>;//vana,vidg + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150_s5>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1904000 2856000 0>; + rgltr-max-voltage = <1800000 2040000 3008000 0>; + rgltr-load-current = <180000 112000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 59 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux1>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vdig-supply = <&pm8150_l17>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 3000000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 300000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 16 0>,//mclk + <&tlmm 23 0>,//reset + <&tlmm 29 0>;//vana,vdig + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + //led-flash-src = <&led_flash_front>; + cam_vio-supply = <&camera_viodd_ldo>; + //cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 3000000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 30000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>,//mclk + <&tlmm 54 0>,//reset + //<&tlmm 132 0>,//vio + <&tlmm 118 0>;//vana,vidg + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + +qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_ultra_rear>; + eeprom-src = <&eeprom_rear_ultra>; + led-flash-src = <&led_flash_rear_aux2>; + cam_vio-supply = <&camera_viodd_ldo>; + //cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_l17>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk";//, "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3000000 0>; + rgltr-load-current = <180000 2000000 300000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_iris>; + gpios = <&tlmm 13 0>,//mclk + <&tlmm 28 0>,//reset + <&tlmm 94 0>;//vana,vdig + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VDIG3"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + +}; + +&cam_cci1 { + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci3_active>; + pinctrl-1 = <&cci3_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 34 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi new file mode 100644 index 000000000000..13907b71874d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi @@ -0,0 +1,1004 @@ +/* +this file is for attribution only of andromeda +And public attribution of xiaomi platforms(like F1X and so and) +*/ + +#include "crux-pinctrl.dtsi" +#include "../common/xiaomi-sdx50-sm8150-common.dtsi" + +#include "crux-sm8150-camera-sensor-mtp.dtsi" + +&soc { + touch_vddio_vreg: touch_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 31 0>; + }; + vdd_boost_vreg: vdd_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-always-on; + gpio = <&pm8150b_gpios 5 0>; + }; + disp_vci_vreg: disp_vci_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 7 0>; + }; + + fingerprint_goodix { + compatible = "goodix,fingerprint"; + goodix,gpio-reset = <&tlmm 37 0x0>; + goodix,gpio-irq = <&tlmm 120 0x0>; + /* fp-gpio-pwr = <&tlmm 125 0>; */ + status = "ok"; + }; + fp_vdd_vreg: fp_vdd_vreg { + compatible = "regulator-fixed"; + regulator-name = "fp_vdd_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 125 0>; + regulator-always-on; + }; + fingerprint_fpc { + status = "ok"; + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <118 0x0>; + fpc,gpio_irq = <&tlmm 118 0x0>; + /* fpc,enable-on-boot; */ + /* fpc,enable-wakeup; */ + + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active"; + + pinctrl-0 = <&msm_gpio_119>; + pinctrl-1 = <&msm_gpio_119_output_high>; + }; + pcie0: qcom,pcie@1c00000 { + status = "disabled"; + }; + + disp_vci_vreg_f1x: disp_vci_vreg_f1x { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 21 0>; + }; + xiaomi_touch { + compatible = "xiaomi-touch"; + status = "ok"; + touch,name = "xiaomi-touch"; + }; + thermal_message: thermal-message { + board-sensor = "VIRTUAL-SENSOR"; + }; +}; + +&sde_dsi { + vcie-supply = <&disp_vci_vreg_f1x>; +}; + +&pm8150l_lpg { + qcom,lut-patterns = <0 1 2 3 4 5 7 9 11 13 15 + 13 11 9 7 5 4 3 2 1 0>; +}; + +&pwm_lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; +}; + +&red_led { + label = "white"; +}; + +&green_led { + status = "disabled"; +}; + +&blue_led { + status = "disabled"; +}; + +&qcom_qbt1000 { + status = "disabled"; +}; + +&qcom_seecom { + reg = <0x87900000 0x3E00000>; +}; + +&qcom_smcinvoke { + reg = <0x87900000 0x3E00000>; +}; + +&qupv3_se4_i2c { + status = "ok"; + + fsa4480@43 { + status = "disabled"; + }; +}; + +&qupv3_se8_i2c { + status = "ok"; + /*smart PA*/ + tas2557@4c{ + compatible = "ti,tas2557"; + reg = <0x4c>; + //ti,cdc-reset-gpio = <&tlmm 59 0>; + ti,irq-gpio = <&tlmm 115 0>; + ti,i2s-bits = <16>; + ti,bypass-tmax = <0>; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2008>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + avdd-supply = <&pm8150l_l1>; + vdd-supply = <&touch_vddio_vreg>; + fts,pwr-reg-name = "avdd"; + fts,bus-reg-name = "vdd"; + fts,irq-gpio = <&tlmm 122 0x2008>; + fts,irq-gpio-name = "fts_irq"; + fts,reset-gpio-enable; + fts,reset-gpio = <&tlmm 12 0x00>; + fts,reset-gpio-name = "fts_rst"; + fts,irq-flags = <0x2008>; /* IRQF_ONESHOT | IRQF_TRIGGER_LOW */ + fts,x-max = <1080>; + fts,y-max = <2340>; + fts,default-fw-name = "st_fts_f1x.ftb"; + fts,config-array-size = <1>; + fts,dump-click-count; + fts,touch-up-threshold-min = <40>; + fts,touch-up-threshold-max = <120>; + fts,touch-up-threshold-def = <80>; + fts,touch-tolerance-min = <5>; + fts,touch-tolerance-max = <35>; + fts,touch-tolerance-def = <25>; + fts,edgefilter-leftrigt-def = <45>; + fts,edgefilter-topbottom-def = <0>; + fts,edgefilter-top-ingamemode = <65>; + fts,edgefilter-bottom-ingamemode = <0>; + fts,edgefilter-area-step1 = <100>; + fts,edgefilter-area-step2 = <150>; + fts,edgefilter-area-step3 = <250>; + fts,touch-idletime-min = <0>; + fts,touch-idletime-max = <12750>; + fts,touch-idletime-def = <12450>; + fts,cfg_0 { + fts,tp-vendor = <0x48>; + fts,fw-name = "st_fts_f1x.ftb"; + fts,limit-name = "stm_fts_production_limits.csv"; + fts,clicknum-file-name = "fts+sdc"; + }; + }; + goodix@5d { + compatible = "goodix,gt9885"; + reg = <0x5d>; + status = "ok"; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2800>; + vtouch-source-supply = <&vdd_boost_vreg>; + vtouch-supply = <&touch_vddio_vreg>; + iotouch-supply = <&pm8150l_l1>; + vtouch-load = <600000>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + goodix,reset-gpio = <&tlmm 12 0x0>; + goodix,irq-gpio = <&tlmm 122 0x2800>; + goodix,irq-flags = <2>; /* 1:trigger rising, 2:trigger falling;*/ + goodix,panel-max-id = <10>; + goodix,panel-max-x = <1079>; + goodix,panel-max-y = <2339>; + goodix,panel-max-w = <127>; + goodix,panel-max-p = <127>; + goodix,panel-max-fod = <127>; + /* goodix,panel-key-map = <158 172 217>; */ /*KEY_BACK, KEY_HOMEPAGE, KEY_SEARCH*/ + goodix,power-on-delay-us = <300000>; /*300ms*/ + goodix,power-off-delay-us = <5000>; + goodix,cfg-name = "goodix_gt9885_cfg_f1u.bin"; + /* goodix,swap-axis; */ + /* goodix,pen-enable; */ + /* goodix,key-of-pen = <331 332>; */ /*BTN_STYLUS, BTN_STYLUS2*/ + sensor1 { + normal-cfg = [ + ]; + goodix,fw-name = "goodix_gt9885_fw_f1u.bin"; + }; + }; +}; + +&pm8150b_fg { + qcom,battery-data = <&mtp_batterydata>; + qcom,rapid-soc-dec-en; + qcom,fg-sys-term-current = <(-300)>; + qcom,fg-cutoff-voltage = <3400>; + qcom,fg-cutoff-current = <200>; + qcom,fg-empty-voltage = <3100>; + qcom,fg-batt-temp-delta = <6>; + qcom,fg-force-load-profile; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&vendor { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "../common/battery/batterydata-F1-atl-3300mah.dtsi" + #include "../common/battery/batterydata-F1-coslight-3300mah.dtsi" + #include "../common/battery/fg-gen4-batterydata-alium-3600mah.dtsi" + }; +}; + +&pm8150_gpios { + vbus_disable { + vbus_disable_default: vbus_disable_default { + pins = "gpio10"; + function = "normal"; + output-low; + power-source = <1>; /* 1.8V input supply */ + }; + }; +}; + +&pm8150b_charger { + qcom,cp-mode = <2>; + qcom,sec-charger-config = <1>; + qcom,usb-icl-ua = <4000000>; + qcom,fcc-max-ua = <8000000>; + qcom,fv-max-uv = <4480000>; + qcom,dc-icl-ua = <500000>; + qcom,auto-recharge-vbat-mv = <4380>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,chg-term-src = <1>; + qcom,chg-term-current-ma = <(-220)>; + qcom,chg-term-base-current-ma = <50>; + qcom,thermal-mitigation = <3000000 2800000 2600000 2400000 2200000 2100000 2000000 + 1800000 1600000 1500000 1400000 1200000 1000000 900000 + 800000 500000>; + qcom,thermal-mitigation-icl + = <2800000 2700000 2600000 2400000 2400000 2400000 2400000 + 2400000 2400000 2100000 1900000 1700000 1500000 1300000 + 1000000 750000>; + qcom,thermal-mitigation-dcp + = <1800000 1800000 1800000 1800000 1800000 1800000 1800000 + 1800000 1800000 1700000 1600000 1400000 1200000 1100000 + 1100000 1000000>; + qcom,thermal-mitigation-qc2 + = <1500000 1500000 1500000 1500000 1450000 1400000 1350000 + 1300000 1300000 1200000 1000000 900000 850000 750000 + 650000 500000>; + qcom,thermal-fcc-qc3-normal + = <3200000 3000000 2800000 2600000 2500000 2400000 2300000 + 2200000 2100000 1800000 1600000 1400000 1200000 1000000 + 750000 750000>; + qcom,thermal-fcc-qc3-cp + = <3600000 3600000 3600000 3600000 3200000 3200000 3200000 + 3200000 3100000 2800000 2400000 2200000 2000000 1300000 + 750000 700000>; + qcom,thermal-fcc-qc3-classb-cp + = <4800000 4700000 4600000 4500000 4400000 4200000 4200000 + 4200000 4000000 3600000 3400000 3200000 3000000 2200000 + 1000000 700000>; + qcom,thermal-mitigation-pd-base + = <4000000 3600000 3200000 2800000 2800000 2800000 2800000 + 2800000 2800000 2400000 2400000 2000000 1600000 1300000 + 1000000 500000>; + qcom,thermal-fcc-pps-cp + = <8000000 7500000 7000000 6500000 6000000 5500000 5350000 + 4500000 4000000 3500000 3000000 3000000 3000000 2000000 + 1500000 100000>; + qcom,thermal-mitigation-dc + = <3100000 2200000 1800000 1600000 1400000 1200000 1100000 + 1000000 900000 800000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-epp + = <1200000 1200000 1200000 1100000 1100000 1000000 1000000 + 1000000 900000 700000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-bpp-qc3 + = <1400000 1300000 1200000 1200000 1100000 1000000 900000 + 800000 700000 700000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-bpp-qc2 + = <1100000 1100000 1100000 1100000 1100000 1000000 1000000 + 1000000 700000 700000 700000 600000 500000 400000 + 300000 200000>; + qcom,thermal-mitigation-bpp + = <700000 700000 700000 700000 700000 700000 700000 + 700000 700000 600000 600000 500000 400000 300000 + 200000 200000>; + qcom,thermal-mitigation-dc-20w + = <2200000 1400000 1300000 1200000 700000 600000 500000 + 400000 400000 400000 400000 400000 400000 400000 + 400000 400000>; + + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_AMUX_THM3_PU2>; + + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp", + "conn_therm"; + + qcom,battery-data = <&mtp_batterydata>; + dpdm-supply = <&usb2_phy0>; + qcom,distinguish-qc-class-ab; + qcom,wd-bark-time-secs = <16>; + qcom,support-wireless; + qcom,support-conn-therm; + qcom,support-ext-fg; + + vbus-disable-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&vbus_disable_default>; +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "smb1390_therm"; + qcom,parallel-output-mode = <2>; + status = "ok"; +}; + +&smb1390_slave { + status = "ok"; +}; + +&smb1390_slave_charger { + status = "ok"; +}; + + + +&ext_5v_boost { + status = "ok"; +}; + +&pm8150b_pdphy { + vbus-supply = <&ext_5v_boost>; + mi,pd_curr_limit = <1>; + mi,pd_max_curr_limit = <4000000>; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x33 0x70 + 0x2c 0x74>; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + cam_therm0 { + reg = ; + label = "cam_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + cam_therm1 { + reg = ; + label = "cam_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + cam_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + cam_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&qupv3_se4_i2c { + status = "ok"; + bq27z561@55 { + compatible = "ti,bq27z561"; + reg = <0x55>; + bq,charge-full-design = <4000000>; + bq,recharge-voltage = <4380>; + bq,soc_decimal_rate = < + 0 38 + 10 35 + 20 33 + 30 33 + 40 33 + 50 33 + 60 33 + 70 30 + 80 25 + 90 20 + 95 10 + 99 5 >; + bq,cold_thermal_seq = < + 1 0 100 1700 + 2 (-300) 0 1000 >; + }; + + fsa4480@43 { + status = "disabled"; + }; + + cs35l41@40 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + cs,cdc-reset-gpio = <&tlmm 89 0x01>; + reg = <0x40>; + pinctrl-names = "cs35l41_irq_default"; + pinctrl-0 = <&cs35l41_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <10 8>; + + cirrus,temp-warn_threshold = <3>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; + /* + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + interrupt-parent = <&tlmm>; + interrupts = <11 8>; + reset-gpios = <&tlmm 7 0x01>; + VA-supply = <&pm8998_s4>; + VP-supply = <&audio_vsys>; + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; + */ + }; +}; + +&dsi_samsung_fhd_ea8076_f1s_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ + qcom,esd-err-irq-gpio = <&tlmm 101 0x2002>; +}; + +//&dsi_visionox_fhd_rm692a9_f1u_cmd { +// qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ +// qcom,esd-err-irq-gpio = <&tlmm 101 0x2002>; +//}; + +&qupv3_se1_spi { + status = "ok"; + irled@0 { + compatible = "ir-spi"; + reg = <0x0>; + status = "ok"; + spi-max-frequency = <19200000>; + }; +}; + +&qupv3_se7_i2c { + status = "ok"; + aw8697_haptic@5A { + compatible = "awinic,aw8697_haptic"; + reg = <0x5A>; + reset-gpio = <&tlmm 6 0>; + irq-gpio = <&tlmm 27 0>; + vib_mode = < 0 >; /*mode: RAM mode->0; CONT mode -> 1*/ + vib_f0_pre = < 1700 >; + vib_f0_cali_percen = < 7 >; + vib_cont_drv_lev = < 88 >; + vib_cont_drv_lvl_ov = < 88 >; + vib_cont_td = < 0xf06c >; + vib_cont_zc_thr = < 0x08f8 >; /*hq 0x08F8 */ + vib_cont_num_brk = < 3 >; + vib_f0_coeff = < 260 >; /*Don't modify it 2.604167*/ + vib_f0_trace_parameter = < 9 3 1 31 >; + vib_bemf_config = < 0 0x08 0x03 0xf8 >; + vib_sw_brake = < 0x2c >; + vib_tset = < 0x12 >; + vib_r_spare = < 0x68 >; + vib_bstdbg = < 0x30 0xeb 0xd4 0 0 0 >; + vib_effect_id_boundary = < 10 >; + vib_effect_max = < 170 >; + vib_trig_config = < 0 1 0 1 2 + 0 1 0 1 2 + 0 1 0 1 2 >; + vib_bst_vol_default = < 0x1b >; + vib_bst_vol_ram = < 0x1b >; + vib_bst_vol_rtp = < 0x16 >; + vib_rtp_time = < 20 20 20 20 20 20 20 20 20000 15000 + 15000 20000 25000 15000 30000 25000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 20000 20000 20000 20000 20000 + 20000 20000 20000 20000 20000 >; + pinctrl-names = "aw8697_reset_reset","aw8697_reset_active","aw8697_interrupt_active"; + pinctrl-0 = <&msm_gpio_6>; + pinctrl-1 = <&msm_gpio_6_output_high>; + pinctrl-2 = <&msm_gpio_27>; + status = "ok"; + wf_0 { + /*CLICK*/ + qcom,effect-id = <0>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_1 { + /*DOUBLE CLICK*/ + qcom,effect-id = <1>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_2 { + /*TICK*/ + qcom,effect-id = <2>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_3 { + /*THUD*/ + qcom,effect-id = <3>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_4 { + /*POP*/ + qcom,effect-id = <4>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <28000>; + }; + wf_5 { + /*HEAVY CLICK*/ + qcom,effect-id = <5>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-brake-pattern = [03 03 01 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_6 { + /*id 6*/ + qcom,effect-id = <6>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_7 { + /*id 7*/ + qcom,effect-id = <7>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_8 { + /*id 8*/ + qcom,effect-id = <8>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + wf_9 { + /*id 9*/ + qcom,effect-id = <9>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <20000>; + }; + }; + + rx1619@61 { + compatible = "nuvolta,wl_charger_rx1619"; + reg = <0x61>; + rx,irq_gpio = <&tlmm 90 0x00>; + rx,tx_on_gpio = <&tlmm 130 0x00>; + rx,wpc-det = <&pm8150b_gpios 7 GPIO_ACTIVE_HIGH>; + rx,enable = <&tlmm 7 0x00>; + pinctrl-names = "default","nu_active","nu_suspend"; + pinctrl-0 = <&power_good_default>; + pinctrl-1 = <&nu_int_active &txon_enable_active &nu_sleep_active>; + pinctrl-2 = <&nu_int_suspend &txon_enable_suspend &nu_sleep_suspend>; + }; + rx1619@67 { + compatible = "nuvolta,wl_rx1619_trim"; + reg = <0x67>; + }; + ln8282@55 { + compatible = "lionsemi,ln8282"; + reg = <0x55>; + ln,enable = <&tlmm 41 0x00>; + ln,irq = <&tlmm 92 0x00>; + pinctrl-names = "ln8282_active","ln8282_suspend"; + pinctrl-0 = <&ln8282_enable_active>; + pinctrl-1 = <&ln8282_enable_suspend>; + }; + idtp9220: idtp9220@3b { + compatible = "idt,p9220"; + reg = <0x3b>; + idt,irq = <&tlmm 90 0x00>; + idt,enable = <&tlmm 7 0x00>; + idt,reverse-enable = <&tlmm 130 0x00>; + idt,wpc-det = <&pm8150b_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "idt_active", "idt_suspend"; + pinctrl-0 = <&power_good_default>; + pinctrl-1 = <&idt_int_active &idt_enable_active>; + pinctrl-2 = <&idt_int_suspend &idt_enable_suspend>; + }; + halo7221@1b { + compatible = "halo7221,halo7221_cp"; + reg = <0x1b>; + halo,enable = <&tlmm 41 0x00>; + pinctrl-names = "halo7221_active","halo7221_suspend"; + pinctrl-0 = <&halo7221_enable_active>; + pinctrl-1 = <&halo7221_enable_suspend>; + }; +}; + +&ssc_sensors { + qcom,firmware-name = "slpi_cr"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8150_l9>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <700000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-audio-overlay.dtsi new file mode 100644 index 000000000000..859a74896ba7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-audio-overlay.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/sm8150-audio-overlay.dtsi" + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC1", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC3", "MIC BIAS4", + "MIC BIAS4", "Analog Mic5"; + + qcom,wsa-max-devs = <0>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <2600>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + fsa4480-i2c-handle = <&fsa4480>; + pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", + "quat_tdm_enable", "quat_tdm_disable"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active &quat_tdm_din_active>; + pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep &quat_tdm_din_sleep>; +}; + +&wcd934x_cdc { + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <2750>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-pinctrl.dtsi new file mode 100644 index 000000000000..9b468dee741c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-pinctrl.dtsi @@ -0,0 +1,904 @@ +/*for xiaomi pinctrl*/ +&tlmm { + /* display_panel_enp +5V */ + display_panel_enp_default: display_panel_enp_default { + mux { + pins = "gpio114"; + function = "gpio"; + }; + config { + pins = "gpio114"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + /* display_panel_enn -5V */ + display_panel_enn_default: display_panel_enn_default { + mux { + pins = "gpio115"; + function = "gpio"; + }; + config { + pins = "gpio115"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio23", "gpio24", "gpio25"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio23", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + bq2597x { + bq2597x_master_int_default: bq2597x_master_int_default { + /* active state */ + mux { + /* GPIO 36 is used for bq25970 master ic interrupt usage */ + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + bq2597x_master_int_suspend: bq2597x_master_int_suspend { + /* sleep state */ + mux { + /* GPIO 36 is used for bq25970 master ic interrupt usage */ + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + }; + + onewire_gpio_active: onewire_gpio_active { + mux { + pins = "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; /* No PULL */ + }; + }; + + onewire_gpio_sleep: onewire_gpio_sleep { + mux { + pins = "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + onewire_gpio_slave_active: onewire_gpio_slave_active { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; /* No PULL */ + }; + }; + + onewire_gpio_slave_sleep: onewire_gpio_slave_sleep { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio122", "gpio12"; + function = "gpio"; + }; + config { + pins = "gpio122", "gpio12"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + config { + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + adc2_switch_gpio_ctrl { + adc2_switch_gpio_idle: adc2_switch_idle { + mux { + pins = "gpio142"; + function = "gpio"; + }; + config { + pins = "gpio142"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + adc2_switch_gpio_active: adc2_switch_active { + mux { + pins = "gpio142"; + function = "gpio"; + }; + config { + pins = "gpio142"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + hall { + hall_intr3_active: hall_intr3_active { + /* active state */ + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + hall_intr3_suspend: hall_intr3_suspend { + /* sleep state */ + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + hall_intr4_active: hall_intr4_active { + /* active state */ + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + hall_intr4_suspend: hall_intr4_suspend { + /* sleep state */ + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + }; + + idt { + idt_int_active: idt_int_active { + /* active state */ + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_int_suspend: idt_int_suspend { + /* sleep state */ + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + txon_enable_active: txon_enable_active { + /* active state */ + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <16>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + txon_enable_suspend: txon_enable_suspend { + /* sleep state */ + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <16>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + power_good_active: power_good_active { + /* active state */ + mux { + pins = "gpio94"; + function = "gpio"; + }; + config { + pins = "gpio94"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + input-enable; + }; + + }; + + power_good_suspend: power_good_suspend { + /* active state */ + mux { + pins = "gpio94"; + function = "gpio"; + }; + config { + pins = "gpio94"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + reverse_booset_enable_active: reverse_booset_enable__active { + /* active state */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <16>; + bias-pull-down; + output-low; + }; + }; + + reverse_booset_enable_suspend: reverse_booset_enable_suspend { + /* sleep state */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <16>; + bias-pull-down; + output-low; + }; + }; + }; + + sbu_uart_en_ctrl { + sbu_uart_en_idle: uart_audio_en_idle { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + sbu_uart_en_active: uart_audio_en_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + + pcie1 { + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio102"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio102"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + cam_sensor_active_macro: cam_sensor_active_macro { + /* RESET macro */ + mux { + pins = "gpio27", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_macro: cam_sensor_suspend_macro { + /* RESET MACRO */ + mux { + pins = "gpio27", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + test_mode_ctrl_irq { + ant_sub_ctrl_irq: ant_sub_ctrl_irq { + mux { + pins = "gpio81"; + function = "gpio"; + }; + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + ant_top_ctrl_irq: ant_top_ctrl_irq { + mux { + pins = "gpio133"; + function = "gpio"; + }; + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + }; + + xiaomi_keyboard_mcu { + xiaomi_keyboard_suspend: xiaomi_keyboard_suspend { + mux { + pins = "gpio4"; + function = "gpio"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + xiaomi_keyboard_active: xiaomi_keyboard_active { + mux { + pins = "gpio4"; + function = "gpio"; + }; + + config { + pins = "gpio4"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + +}; + +//camera voltage start +&cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <6>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <6>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio30", "gpio31"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio30", "gpio31"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; +&cam_sensor_active_macro { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio27","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27","gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_macro { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio27","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27","gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + + +//camera voltage end + + +&fsa_usbc_ana_en { + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; + + + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..a1f282917a65 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150-camera-sensor-mtp.dtsi @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&cam_cci1 { + status = "disable"; +}; + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0>; + torch-source = <&pm8150l_torch0>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; + + actuator_rear_regulator: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "actuator_rear_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 29 0>; + vin-supply = <&pm8150l_bob>; + }; + + camera_wide_vdig_ldo: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "camera_wide_vdig_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm8150l_gpios 3 0>; + vin-supply = <&pm8150_s4>; + }; + + camera_front_vdig_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_front_vdig_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 12 0>; + vin-supply = <&pm8150_s4>; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&actuator_rear_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 14 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + //ov13b10 + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&camera_wide_vdig_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana","cam_vdig", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 1200000 0>; + rgltr-max-voltage = <1800000 4000000 1200000 0>; + rgltr-load-current = <180000 2000000 100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 11 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + //ov8856 + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x2>; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&camera_wide_vdig_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 1200000 0>; + rgltr-max-voltage = <1800000 4000000 1200000 0>; + rgltr-load-current = <180000 2000000 100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 31 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi new file mode 100644 index 000000000000..06be84bc688d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi @@ -0,0 +1,1275 @@ +/* +this file is for attribution only of vayu +And public attribution of xiaomi platforms(like J20S and so and) +*/ +#include "nabu-pinctrl.dtsi" +#include "../common/xiaomi-sm8150-common.dtsi" +#include "nabu-sm8150-camera-sensor-mtp.dtsi" + +&ufshc_mem { + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; + qcom,vccq-parent-supply = <&pm8150l_s8>; + qcom,vccq-parent-max-microamp = <210000>; + vccq-supply = <&pm8150_l9>; + vccq-max-microamp = <700000>; + wb-support; +}; + +#include "../common/smb1390.dtsi" + + + +&pm8150b_fg { + qcom,battery-data = <&nabu_batterydata>; + qcom,rapid-soc-dec-en; + qcom,soc-scale-mode-en; + qcom,five-pin-battery; + qcom,soc-hi-res; + qcom,soc_decimal_rate = < + 0 38 + 10 35 + 20 33 + 30 33 + 40 33 + 50 33 + 60 33 + 70 30 + 80 25 + 90 20 + 95 10 >; + qcom,ki-coeff-low-chg = <315>; + qcom,ki-coeff-med-chg = <183>; + qcom,fg-sys-term-current = <(-500)>; + qcom,fg-ffc-sys-term-current = <(-1530)>; + qcom,fg-cutoff-voltage = <3400>; + qcom,fg-cutoff-current = <200>; + qcom,fg-empty-voltage = <3100>; + qcom,soc-scale-vbatt-mv = <3600>; + qcom,fg-batt-temp-delta = <6>; + qcom,fg-force-load-profile; + qcom,shutdown-delay-enable; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 96>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; + qcom,ki-coeff-chg-med-hi-thresh-ma = <1000>; + qcom,ki-coeff-chg-low-med-thresh-ma = <500>; + qcom,ffc-ki-coeff-chg-med-hi-thresh-ma = <3900>; + qcom,ffc-ki-coeff-chg-low-med-thresh-ma = <3500>; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <0>; + qcom,usb-icl-ua = <3000000>; + qcom,fcc-max-ua = <5900000>; + qcom,fv-max-uv = <4470000>; + qcom,non-fcc-fv-max-uv = <4450000>; + //qcom,chg-warm-th= <450>; + //qcom,chg-cool-th= <150>; + qcom,auto-recharge-soc = <99>; + qcom,chg-term-src = <1>; + qcom,chg-term-current-ma = <(-400)>; + mi,use-bq-pump; + qcom,usbpd-phandle = <&pm8150b_pdphy>; + qcom,battery-data = <&nabu_batterydata>; + //mi,six-pin-step-chg-params = <4250000 6000000 + // 4450000 5400000 + // 4480000 4000000>; + //mi,six-pin-step-chg; + //mi,six-pin-soc-th = <45>; + mi,fcc-batt-unverify-ua = <2000000>; + mi,support-ffc; + qcom,support-wireless; + mi,support-qc3p5-without-smb; + qcom,disable-suspend-on-collapse; + qcom,thermal-mitigation = <3000000 2800000 2600000 2400000 2200000 2100000 2000000 + 1800000 1600000 1500000 1400000 1200000 1000000 900000 + 800000 500000>; + qcom,thermal-mitigation-icl + = <2800000 2700000 2600000 2400000 2200000 2100000 2000000 + 1800000 1600000 1500000 1400000 1300000 1200000 1100000 + 950000 750000>; + qcom,thermal-mitigation-dcp + = <1800000 1800000 1800000 1800000 1800000 1800000 1800000 + 1800000 1800000 1700000 1600000 1400000 1200000 1100000 + 1100000 1000000>; + qcom,thermal-mitigation-qc2 + = <1500000 1500000 1500000 1500000 1450000 1400000 1350000 + 1300000 1150000 1100000 1000000 900000 850000 750000 + 650000 500000>; + qcom,thermal-fcc-qc3-normal + = <3200000 3000000 2800000 2600000 2500000 2400000 2300000 + 2200000 2100000 1800000 1600000 1400000 1200000 1000000 + 750000 750000>; + qcom,thermal-fcc-pps-cp + = <6000000 5700000 5475000 5250000 5025000 4800000 4575000 + 4350000 4100000 3500000 3000000 2400000 2000000 1500000 + 1000000 500000>; + qcom,thermal-fcc-qc3-cp + = <4800000 4600000 4400000 4200000 4000000 3800000 3600000 + 3400000 3000000 2600000 2400000 2200000 2000000 1300000 + 1000000 300000>; + qcom,thermal-fcc-qc3-classb-cp + = <5100000 4700000 4300000 4000000 3600000 3500000 3400000 + 3400000 3400000 3200000 2500000 2200000 2000000 1300000 + 1000000 300000>; + qcom,thermal-mitigation-pd-base + = <3000000 2800000 2600000 2400000 2200000 2000000 1800000 + 1600000 1600000 1400000 1200000 1100000 1050000 1000000 + 950000 500000>; + qcom,thermal-mitigation-voice + = <6000000 2200000 2200000 1000000 1000000 800000 800000 + 800000 800000 700000 700000 600000 600000 600000 + 500000 400000>; + + + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp"; +// qcom,battery-data = <&mtp_batterydata>; + dpdm-supply = <&usb2_phy0>; + qcom,distinguish-qc-class-ab; + qcom,lpd-disable; + qcom,sw-jeita-enable; +// qcom,step-charging-enable; + qcom,wd-bark-time-secs = <16>; +}; + +&ext_5v_boost { + status = "disable"; +}; + +&pm8150b_pdphy { + mi,non-qcom-pps-ctrl; +}; + +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + bq25970-standalone@66 { + compatible = "ti,bq2597x-standalone"; + reg = <0x66>; + interrupt-parent = <&tlmm>; + interrupts = <36 0x2002>; + pinctrl-names = "default"; + pinctrl-0 = <&bq2597x_master_int_default &bq2597x_master_int_suspend>; + + /*ti,bq2597x,bat-ovp-disable;*/ + ti,bq2597x,bat-ovp-alarm-disable; + ti,bq2597x,bat-ocp-disable; + ti,bq2597x,bat-ocp-alarm-disable; + ti,bq2597x,bat-ucp-alarm-disable; + ti,bq2597x,bat-ucp-disable; + + /*ti,bq2597x,bus-ovp-alarm-disable; + ti,bq2597x,bus-ocp-disable; + ti,bq2597x,bus-ocp-alarm-disable;*/ + ti,bq2597x,bat-therm-disable; + ti,bq2597x,bus-therm-disable; + ti,bq2597x,die-therm-disable; + + ti,bq2597x,bat-ovp-threshold = <4550>; + ti,bq2597x,bat-ovp-alarm-threshold = <4525>; + //ti,bq2597x,bat-ocp-threshold = <8000>; + //ti,bq2597x,bat-ocp-alarm-threshold = <7500>; + + ti,bq2597x,bus-ovp-threshold = <12000>; + ti,bq2597x,bus-ovp-alarm-threshold = <11000>; + ti,bq2597x,bus-ocp-threshold = <3750>; + ti,bq2597x,bus-ocp-alarm-threshold = <3500>; + + //ti,bq2597x,bat-ucp-alarm-threshold = <2000>; + + ti,bq2597x,bat-therm-threshold = <0x15>;/*4.1%*/ + ti,bq2597x,bus-therm-threshold = <0x15>;/*4.1%*/ + ti,bq2597x,die-therm-threshold = <145>; + + ti,bq2597x,ac-ovp-threshold = <14>; + //ti,bq2597x,sense-resistor-mohm = <2>; + + }; + + ln8000_charger@51 { + compatible = "lionsemi,ln8000"; + reg = <0x51>; + /* bank */ + //irq-gpios = <&tlmm 55 0x2002>; + + //interrupt-parent = <&tlmm>; + //interrupts = <55 0x2002>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bq2597x_int_default &bq2597x_int_suspend>; + ln8000_charger,irq_index = <296>; + /* device configuration */ + ln8000_charger,bat-ovp-threshold = <4560>; + ln8000_charger,bat-ovp-alarm-threshold = <4525>; + ln8000_charger,bus-ovp-threshold = <13000>; + ln8000_charger,bus-ovp-alarm-threshold = <11000>; + ln8000_charger,bus-ocp-threshold = <3750>; + ln8000_charger,bus-ocp-alarm-threshold = <3500>; + ln8000_charger,ntc-alarm-cfg = <226>; + /* protection enable/disable flags + * vbat-ovp-disable + * vbat-reg-disable + * iin-ocp-disable + * iin-reg-disable + * tbus-mon-disable + * tbat-mon-disable + * tdie-prot-disable + * tdie-reg-disable + * revcurr-prot-disable + */ + ln8000_charger,tdie-prot-disable; + ln8000_charger,tbus-mon-disable; + ln8000_charger,tbat-mon-disable; + ln8000_charger,iin-ocp-disable; + ln8000_charger,iin-reg-disable; + ln8000_charger,tdie-reg-disable; + ln8000_charger,vbat-reg-disable; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + idtp9418: idtp9418@3b { + compatible = "idt,p9418"; + status = "ok"; + reg = <0x3b>; + idt,irq = <&tlmm 95 0x00>; + hall,int3 = <&tlmm 101 0x00>; + hall,int4 = <&tlmm 134 0x00>; + idt,reverse-enable = <&tlmm 3 0x00>; + idt,reverse-booset-enable = <&tlmm 47 0x00>; + idt,wpc-det = <&tlmm 94 GPIO_ACTIVE_HIGH>; + pinctrl-names = "idt_active", "idt_suspend"; + pinctrl-0 = <&idt_int_active &hall_intr3_active &hall_intr4_active &txon_enable_active &power_good_active &reverse_booset_enable_active>; + pinctrl-1 = <&idt_int_suspend &hall_intr3_suspend &hall_intr4_suspend &txon_enable_suspend &power_good_suspend &reverse_booset_enable_suspend>; + }; +}; + +&soc { + cp_qc30 { + compatible = "xiaomi,cp-qc30"; + status = "ok"; + mi,qc3-bat-volt-max = <4420>; + mi,qc3-bat-curr-max = <3600>; + mi,qc3-bus-volt-max = <12000>; + mi,qc3-bus-curr-max = <2100>; + mi,qc3-battery-warm-th = <450>; + mi,use-qcom-gauge; + mi,support-qc3p5-without-smb; + //mi,cp-sec-enable; + }; + + usbpd_pm { + compatible = "xiaomi,usbpd-pm"; + status = "ok"; + mi,pd-bat-volt-max = <4500>; + mi,pd-ffc-bat-volt-max = <4480>; + mi,pd-bat-curr-max = <6000>; + mi,pd-bus-volt-max = <12000>; + mi,pd-bus-curr-max = <3000>; + mi,pd-non-ffc-bat-volt-max = <4450>; + mi,pd-bus-curr-compensate = <0>; + mi,pd-battery-warm-th = <450>; + mi,use-qcom-gauge; + //mi,cp-sec-enable; + }; + + qcom,rmnet-ipa { + status = "disabled"; + }; + + ipa_hw: qcom,ipa@1e00000 { + status = "disabled"; + }; + + onewire_gpio: onewire_gpio { + compatible = "xiaomi,onewire_gpio"; + label = "xm_onewire"; + xiaomi,version = <1>; + xiaomi,ow_gpio = <&tlmm 5 0x00>; + mi,onewire-gpio-cfg-addr = <0x03D05000 0x4>; + xiaomi,gpio_number = <5>; + pinctrl-names = "onewire_active", "onewire_sleep"; + pinctrl-0 = <&onewire_gpio_active>; + pinctrl-1 = <&onewire_gpio_sleep>; + status = "ok"; + }; + + onewire_slave_gpio: onewire_slave_gpio { + compatible = "xiaomi,onewire_slave_gpio"; + label = "xm_slave_onewire"; + xiaomi,version = <1>; + xiaomi,ow_gpio = <&tlmm 10 0x00>; + mi,onewire-gpio-cfg-addr = <0x0390A000 0x4>; + xiaomi,gpio_number = <10>; + pinctrl-names = "onewire_slave_active", "onewire_slave_sleep"; + pinctrl-0 = <&onewire_gpio_slave_active>; + pinctrl-1 = <&onewire_gpio_slave_sleep>; + status = "ok"; + }; + + nabu_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "../common/battery/fg-gen4-batterydata-nabu-sunwoda-8720mah.dtsi" + }; + + maxim_ds28e16: maxim_ds28e16 { + compatible = "maxim,ds28e16"; + label = "max_ds28e16"; + maxim,version = <1>; + status = "ok"; + }; + + maxim_ds28e16_slave: maxim_ds28e16_slave { + compatible = "maxim,ds28e16_slave"; + label = "max_ds28e16_slave"; + maxim,version = <1>; + status = "ok"; + }; +}; + +&qupv3_se7_i2c { + status = "ok"; + /*speaker UL*/ + cs35l41@43 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + reset-gpios = <&tlmm 92 0>; + reg = <0x43>; + interrupt-parent = <&tlmm>; + interrupts = <93 8>; + cirrus,temp-warn_threshold = <3>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,fast-switch = "TL-music.txt", "TL-voice.txt", "TL-voip.txt", "TL-misc.txt"; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; + }; + + /*speaker UR*/ + cs35l41@41 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + reset-gpios = <&tlmm 92 0>; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <90 8>; + cirrus,temp-warn_threshold = <3>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,fast-switch = "TR-music.txt", "TR-voice.txt", "TR-voip.txt", "TR-misc.txt"; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; + }; + + /*speaker DL*/ + cs35l41@42 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + reset-gpios = <&tlmm 92 0>; + reg = <0x42>; + interrupt-parent = <&tlmm>; + interrupts = <91 8>; + cirrus,temp-warn_threshold = <3>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,fast-switch = "BL-music.txt", "BL-voice.txt", "BL-voip.txt", "BL-misc.txt"; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; + }; + + /*speaker DR*/ + cs35l41@40 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + reset-gpios = <&tlmm 92 0>; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <81 8>; + cirrus,temp-warn_threshold = <3>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,fast-switch = "BR-music.txt", "BR-voice.txt", "BR-voip.txt", "BR-misc.txt"; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; + }; +}; + + + +&smb1390 { + status = "disabled"; +}; + +&smb1390_charger { + status = "disabled"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x04 0x70 + 0x2c 0x74>; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb1 { + status = "ok"; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb_qmp_phy { + status = "ok"; +}; + +&soc { + touch_vddio_vreg: touch_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 100 0>; + }; + + vdd_boost_vreg: vdd_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-always-on; + gpio = <&pm8150b_gpios 5 0>; + }; + + fingerprint_goodix { + compatible = "goodix,fingerprint"; + goodix,gpio-reset = <&tlmm 37 0x0>; + goodix,gpio-irq = <&tlmm 120 0x0>; + //goodix.gpio_pwr = <&tlmm 125 0x0>; + //fp_vdd_vreg = <&pm8150l_l7>; + status = "ok"; + }; + + + fingerprint_fpc { + compatible = "fpc,fpc1020"; + fpc,gpio_rst = <&tlmm 37 0x0>; + fpc,gpio_irq = <&tlmm 120 0x0>; + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active", + "fpc1020_irq_active"; + + pinctrl-0 = <&msm_gpio_37>; + pinctrl-1 = <&msm_gpio_37_output_high>; + pinctrl-2 = <&msm_gpio_120>; + status = "ok"; + }; + + + xiaomi_touch { + compatible = "xiaomi-touch"; + status = "ok"; + touch,name = "xiaomi-touch"; + }; + + testing_mode { + compatible = "modem,testing-mode"; + status-gpio = <&tlmm 81 0x00>, + <&tlmm 133 0x00>; + debounce-time = <30>; + pinctrl-names = "default"; + pinctrl-0 = <&ant_sub_ctrl_irq &ant_top_ctrl_irq>; + }; +}; + +&soc { + display_panel_enp: display_gpio_regulator_enp { + compatible = "regulator-fixed"; + regulator-name = "display_panel_enp"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 114 0>; + enable-active-high; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_enp_default>; + }; + display_panel_enn: display_gpio_regulator_enn { + compatible = "regulator-fixed"; + regulator-name = "display_panel_enn"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 115 0>; + enable-active-high; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_enn_default>; + }; + xiaomi_keyboard { + compatible = "xiaomi,keyboard"; + pinctrl-names = "pm_kb_active", "pm_kb_suspend"; + pinctrl-0 = <&xiaomi_keyboard_active>; + pinctrl-1 = <&xiaomi_keyboard_suspend>; + xiaomi-keyboard,rst-gpio = <&tlmm 49 0x00>; + xiaomi-keyboard,in-irq-gpio = <&tlmm 41 0x2001>; + xiaomi-keyboard,vdd-gpio = <&tlmm 82 0x00>; + status = "ok"; + }; +}; + +/* K82 Backlight Driver SE 11 pin mappings */ +&qupv3_se0_i2c { + status = "ok"; + ktz8866@11 { + compatible = "ktz,ktz8866"; + status = "ok"; + reg = <0x11>; + ktz8866,hwen-gpio = <&tlmm 27 0x00>; + ktz8866,enp-gpio = <&tlmm 114 0x00>; + ktz8866,enn-gpio = <&tlmm 115 0x00>; + }; +}; +&pm8150a_amoled { + status = "disabled"; +}; + +&pm8150l_lcdb { + status = "disabled"; +}; + +&pm8150l_wled { + status = "disabled"; + qcom,string-cfg = <7>; +}; + +&sde_dsi { + enp-supply = <&display_panel_enp>; + enn-supply = <&display_panel_enn>; +}; + +&dsi_k82_42_02_0a_dual_cphy_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_k82_vddio>; +}; + +&dsi_k82_36_02_0b_dual_cphy_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_k82_vddio>; +}; + +&red_led { + label = "white"; +}; + +&green_led { + status = "disabled"; +}; + +&blue_led { + status = "disabled"; +}; + +&dsi_k82_42_02_0a_dual_cphy_vid_display { + qcom,dsi-display-active; +}; + +&dsi_sim_vid_display { + /delete-property/ qcom,dsi-display-active; +}; + +/*Touch SPI state init*/ +&qupv3_se18_spi_active { + mux { + pins = "gpio23", "gpio24", "gpio25"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; +}; + +&qupv3_se18_spi_sleep { + mux { + pins = "gpio23", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; +}; + +/*IC int pin, rst pin init*/ +&tlmm { + ts_mux { + ts_int_active: ts_int_active { + mux { + pins = "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio39"; + drive-strength = <16>; + bias-pull-down; + }; + }; +/* + ts_reset_active: ts_reset_active { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-pull-up; + }; + }; +*/ + ts_cs_active: ts_cs_active { + mux { + pins = "gpio26"; + function = "qup18"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + ts_cs_suspend: ts_cs_suspend { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-pull-down; + output-low; + }; + }; + }; +}; + +&ts_int_suspend { + mux { + pins = "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio39"; + drive-strength = <16>; + bias-disable; + input-enable; + }; +}; + +/* +&ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-disable; + }; +}; +*/ + +&qupv3_se18_spi { + status = "ok"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + novatek@0 { + compatible = "novatek,NVT-ts-spi"; + reg = <0>; //Same as CS ID + status = "ok"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_cs_active>; + pinctrl-1 = <&ts_cs_suspend>; + spi-max-frequency = <9600000>; //4800000,9600000,15000000,19200000 + //novatek,reset-gpio = <&tlmm 75 0x00>; + novatek,irq-gpio = <&tlmm 39 0x2001>; + + novatek,pen-support; + novatek,wgp-stylus; + + /* 523 */ + novatek,swrst-n8-addr = <0x03F0FE>; + novatek,spi-rd-fast-addr = <0x03F310>; + + /* MP */ + novatek,mp-support-dt; + /*new touch faeature default param*/ + novatek,touch-game-param-config1 = <2 2 1 2 1>; + novatek,touch-game-param-config2 = <2 2 2 2 1>; + novatek,touch-game-param-config3 = <2 2 3 2 1>; + + novatek,config-array-size = <2>; + novatek,cfg_0 { + novatek,display-maker = <0x42>; + novatek,fw-name = "novatek_nt36523_fw01.bin"; + novatek,mp-name = "novatek_nt36523_mp01.bin"; + }; + novatek,cfg_1 { + novatek,display-maker = <0x36>; + novatek,fw-name = "novatek_nt36523_fw02.bin"; + novatek,mp-name = "novatek_nt36523_mp02.bin"; + }; + + }; +}; + + +&qupv3_se9_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 102 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + //qcom,nq-esepwr = <&tlmm 42 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&qupv3_se1_spi { + status = "ok"; + irled@0 { + compatible = "ir-spi"; + reg = <0x0>; + status = "ok"; + spi-max-frequency = <19200000>; + }; +}; + +&pm8150l_lpg { + qcom,lut-patterns = <0 1 2 3 4 5 7 9 11 13 15 + 13 11 9 7 5 4 3 2 1 0>; +}; + +&pwm_lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&pm8150l_backlight_therm_default>; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + cam_therm0 { + reg = ; + label = "cam_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + cam_therm1 { + reg = ; + label = "cam_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + backlight_therm { + reg = ; + label = "backlight_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_gpios { + pm8150l_backlight_therm { + pm8150l_backlight_therm_default: pm8150l_backlight_therm_default { + pins = "gpio7"; + bias-high-impedance;/* DISABLE GPIO7 for ADC*/ + }; + }; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + io-channels = <&pm8150l_vadc ADC_AMUX_THM1_PU2>, + <&pm8150l_vadc ADC_AMUX_THM2_PU2>, + <&pm8150l_vadc ADC_GPIO3_PU2>; + + cam_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + cam_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + backlight_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + modem1_xo {//place close to pm8150b + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + charger_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + flash_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + backlight_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_GPIO3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <2800>; + qcom,play-rate-us = <5102>; + + wf_0 { + /* CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_2 { + /* TICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_3 { + /* THUD */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_4 { + /* POP */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-brake-pattern = [03 03 01 00]; + qcom,wf-play-rate-us = <5102>; + }; +}; + +&soc { + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi_nb"; + }; + + gpio_keys { + hall_key { + label = "hall_key"; + gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = <0>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + hall_key1 { + label = "hall_key1"; + gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = <1>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + + thermal_message: thermal-message { + board-sensor = "VIRTUAL-SENSOR"; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + status = "ok"; + }; + +&tlmm { + /* GPIO_37 : FP_RESET_N */ + msm_gpio_37: msm_gpio_37 { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + /* GPIO_37 : FP_RESET_N, state device active*/ + msm_gpio_37_output_high: msm_gpio_37_output_high { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + /* GPIO_120 : FP_INT_N */ + msm_gpio_120: msm_gpio_120 { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&pm8150l_gpios { + /* WIDE VDIG ENABLE */ + cam_sensor_wide_vdig_enable: cam_sensor_wide_vdig_enable { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + output-low; + }; + + cam_sensor_wide_vdig_disable: cam_sensor_wide_vdig_disable { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + output-low; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-audio-overlay.dtsi new file mode 100644 index 000000000000..68d020d5ddda --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-audio-overlay.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/sm8150-audio-overlay.dtsi" + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS4", + "MIC BIAS4", "Analog Mic5"; + + qcom,wsa-max-devs = <0>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-usbc-audio-supported = <0>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-pinctrl.dtsi new file mode 100644 index 000000000000..09bc52610904 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-pinctrl.dtsi @@ -0,0 +1,608 @@ +/*for xiaomi pinctrl*/ +&tlmm { + idt { + idt_int_active: idt_int_active { + /* active state */ + mux { + /* GPIO 78 idt Read Interrupt */ + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_int_suspend: idt_int_suspend { + /* sleep state */ + mux { + /* GPIO 78 idt Read Interrupt */ + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_enable_active: idt_enable_active { + /* active state */ + mux { + /* GPIO 36 idt enable pin */ + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + idt_enable_suspend: idt_enable_suspend { + /* sleep state */ + mux { + /* GPIO 36 idt enable pin */ + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + fp_mux { + fp_active: fp_active { + mux { + pins = "gpio118"; + function = "gpio"; + }; + config { + pins = "gpio118"; + drive-strength = <8>; + bias-disable; + }; + }; + + fp_suspend: fp_suspend { + mux { + pins = "gpio118"; + function = "gpio"; + }; + config { + pins = "gpio118"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* GPIO_37 : FP_RESET_N */ + msm_gpio_37: msm_gpio_37 { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + /* GPIO_37 : FP_RESET_N, state device active*/ + msm_gpio_37_output_high: msm_gpio_37_output_high { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + /* GPIO_118 : FP_INT_N */ + msm_gpio_118: msm_gpio_118 { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + smartpa_int_active: smartpa_int_active { + /* active state */ + mux { + /* GPIO 141 Interrupt */ + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + smartpa_int_suspend: smartpa_int_suspend { + /* sleep state */ + mux { + /* GPIO 141 Interrupt */ + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + smartpa_enable_active: smartpa_enable_active { + /* active state */ + mux { + /* GPIO 59 rst pin */ + pins = "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio59"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + smartpa_enable_suspend: smartpa_enable_suspend { + /* sleep state */ + mux { + /* GPIO 59 rst pin */ + pins = "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio59"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + }; + /*touchpanel*/ + pmx_ts_active { + tp_active: tp_active { + mux { + pins = "gpio122", "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio122", "gpio54"; + drive-strength = <16>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + tp_int_suspend: tp_int_suspend { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <16>; + input-enable; + slew-rate = <0>; + bias-pull-up = <00>; + }; + }; + }; + + pmx_ts_reset_suspend { + tp_reset_suspend: tp_reset_suspend { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <16>; + slew-rate = <1>; + bias-disable; + output-high; + }; + }; + }; + + + akm09970_irq { + akm_irq_active: akm_irq_active { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; /* No PULL */ + }; + }; + + akm_irq_suspend: akm_irq_suspend { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + akm09970_reset { + akm_reset_active: akm_reset_active { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; /* No PULL */ + output-low; + }; + }; + + akm_reset_suspend: akm_reset_suspend { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + motor_gpio_default: motor_gpio_default { + mux { + pins = "gpio9", "gpio21", "gpio33", "gpio35", "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio21", "gpio33", "gpio35", "gpio130"; + bias-pull-up; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_wide: cam_sensor_active_wide { + /* WIDE RESET DVDDEN */ + mux { + pins = "gpio28", "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio90"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_wide: cam_sensor_suspend_wide { + /* WIDE RESET DVDDEN AVDDEN 1.8AVDDEN */ + mux { + pins = "gpio28", "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio90"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_tele: cam_sensor_active_tele { + /* TELE RESET DVDDEN */ + mux { + pins = "gpio30", "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio93"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_tele: cam_sensor_suspend_tele { + /* TELE RESET DVDDEN */ + mux { + pins = "gpio30", "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio93"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_ultra: cam_sensor_active_ultra { + /* ULTRA RESET DVDDEN */ + mux { + pins = "gpio23", "gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_ultra: cam_sensor_suspend_ultra { + /* ULTRA RESET DVDDEN */ + mux { + pins = "gpio23", "gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_front: cam_sensor_active_front { + /* FRONT RESET DVDDEN */ + mux { + pins = "gpio12", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio95"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_front: cam_sensor_suspend_front { + /* FRONT RESET DVDDEN */ + mux { + pins = "gpio12", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio95"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_actuator_wide_en: cam_actuator_wide_en { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_actuator_tele_en: cam_actuator_tele_en { + mux { + pins = "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio84"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_viodd_en: cam_sensor_viodd_en { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio6", "gpio7", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio5"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio6", "gpio7", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio5"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + pcie1 { + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio103"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio103"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150-camera-sensor.dtsi new file mode 100644 index 000000000000..ceb6c189bcaa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150-camera-sensor.dtsi @@ -0,0 +1,483 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +/* + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + wled-flash-support; + flash-source = <&wled_flash>; + torch-source = <&wled_torch>; + switch-source = <&wled_switch>; + status = "ok"; + }; + + led_flash_iris: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash1>; + torch-source = <&pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + };*/ + + wide_actuator_regulator: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "actuator_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 83 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_actuator_wide_en>; + vin-supply = <&pm8150l_bob>; + }; + + tele_actuator_regulator: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "actuator_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 84 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_actuator_tele_en>; + vin-supply = <&pm8150l_bob>; + }; + + camera_viodd_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_viodd_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 97 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_viodd_en>; + vin-supply = <&pm8150_s4>; + }; +}; + +&pm8150_l17 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <3100000>; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&wide_actuator_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&tele_actuator_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vaf-supply = <&wide_actuator_regulator>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 0>; + rgltr-max-voltage = <1800000 2800000 0>; + rgltr-load-current = <1000 1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_wide>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_wide>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + sensor-mode = <0>; + cci-master = <0>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vaf-supply = <&tele_actuator_regulator>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vaf", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 0>; + rgltr-max-voltage = <1800000 2800000 0>; + rgltr-load-current = <1000 1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_tele>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_tele>; + gpios = <&tlmm 14 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK1"; + sensor-mode = <0>; + cci-master = <1>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&pm8150_s5>; + cam_v_custom2-supply = <&pm8150_l17>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1", "cam_v_custom2"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0 1904000 3100000>; + rgltr-max-voltage = <1800000 4000000 1352000 0 2040000 3100000>; + rgltr-load-current = <1000 80000 1200000 0 10000 1000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_wide>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_wide>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 90 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAMW_RESET", + "CAMW_VDIG_EN"; + sensor-mode = <0>; + cci-master = <0>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&pm8150_l17>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0 3100000>; + rgltr-max-voltage = <1800000 4000000 1352000 0 3100000>; + rgltr-load-current = <1000 80000 1200000 0 1000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_tele>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_tele>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAMT_RESET", + "CAMT_VDIG_EN"; + sensor-mode = <0>; + cci-master = <1>; + cci-device = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&pm8150_l17>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0 3100000>; + rgltr-max-voltage = <1800000 4000000 1352000 0 3100000>; + rgltr-load-current = <1000 80000 1200000 0 1000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&tlmm 95 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAMF_RESET", + "CAMF_VDIG_EN"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&cam_cci1 { + status = "ok"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 32 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + eeprom_ultra: qcom,eeprom@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&camera_viodd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_ultra>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_ultra>; + + gpios = <&tlmm 16 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK3"; + sensor-mode = <0>; + cci-master = <0>; + cci-device = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_ultra>; + cam_vio-supply = <&camera_viodd_ldo>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom1-supply = <&pm8150_l17>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0 3100000>; + rgltr-max-voltage = <1800000 4000000 1352000 0 3100000>; + rgltr-load-current = <1000 80000 1200000 0 1000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_ultra>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_ultra>; + + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&tlmm 34 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAMU_RESET", + "CAMU_VDIG_EN"; + sensor-mode = <0>; + cci-master = <0>; + cci-device = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150.dtsi new file mode 100644 index 000000000000..31b245e7c25b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/raphael/raphael-sm8150.dtsi @@ -0,0 +1,736 @@ +/* +this file is for attribution only of davinci +And public attribution of xiaomi platforms(like F1 and so and) +*/ +#include "raphael-pinctrl.dtsi" +#include "../common/xiaomi-sm8150-common.dtsi" + +#include "raphael-sm8150-camera-sensor.dtsi" + +#include "../common/smb1390.dtsi" + + +&vendor { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "../common/battery/batterydata-F11-sun-4000mah.dtsi" + #include "../common/battery/batterydata-F11-gyu-4000mah.dtsi" + }; +}; + +&pm8150b_fg { + qcom,battery-data = <&mtp_batterydata>; + qcom,rapid-soc-dec-en; + qcom,fg-sys-term-current = <(-300)>; + qcom,fg-cutoff-voltage = <3400>; + qcom,fg-cutoff-current = <200>; + qcom,fg-empty-voltage = <3100>; + qcom,fg-batt-temp-delta = <6>; + qcom,fg-force-load-profile; + qcom,five-pin-battery; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <1>; + qcom,usb-icl-ua = <2800000>; + qcom,fcc-max-ua = <5100000>; + qcom,fv-max-uv = <4400000>; + qcom,auto-recharge-soc = <99>; + qcom,chg-term-src = <1>; + qcom,chg-term-current-ma = <(-220)>; + qcom,thermal-mitigation = <3000000 2800000 2600000 2400000 2200000 2100000 2000000 + 1800000 1600000 1500000 1400000 1200000 1000000 900000 + 800000 500000>; + qcom,thermal-mitigation-icl + = <2800000 2700000 2600000 2400000 2400000 2400000 2400000 + 2400000 2400000 2100000 1900000 1700000 1500000 1300000 + 1000000 750000>; + qcom,thermal-mitigation-dcp + = <1800000 1800000 1800000 1800000 1800000 1800000 1800000 + 1800000 1800000 1700000 1600000 1400000 1200000 1100000 + 1100000 1000000>; + qcom,thermal-mitigation-qc2 + = <1500000 1500000 1500000 1500000 1450000 1400000 1350000 + 1300000 1300000 1200000 1000000 900000 850000 750000 + 650000 500000>; + qcom,thermal-fcc-qc3-normal + = <3200000 3000000 2800000 2600000 2500000 2400000 2300000 + 2200000 2100000 1800000 1600000 1400000 1200000 1000000 + 750000 750000>; + qcom,thermal-fcc-qc3-cp + = <3600000 3600000 3600000 3500000 3400000 3300000 3300000 + 3200000 3100000 2800000 2400000 2200000 2000000 1300000 + 1000000 700000>; + qcom,thermal-fcc-qc3-classb-cp + = <5100000 4800000 4600000 4400000 4200000 4000000 4000000 + 4000000 4000000 3600000 3400000 3200000 3000000 2200000 + 1000000 700000>; + qcom,thermal-mitigation-pd-base + = <3000000 2800000 2600000 2500000 2500000 2500000 2500000 + 2500000 2500000 2400000 2200000 2000000 1600000 1300000 + 1000000 500000>; + qcom,thermal-fcc-pps-cp + = <5100000 5000000 4900000 4800000 4600000 4400000 4200000 + 4000000 3800000 3600000 3400000 3200000 3000000 2200000 + 1000000 500000>; + qcom,thermal-mitigation-dc + = <2200000 2000000 1800000 1600000 1400000 1200000 1100000 + 1000000 900000 800000 700000 600000 500000 400000 + 300000 200000>; + qcom,lpd_hwversion + = <43200 53600 100000 121000 232000 300000 562000 900000>; + + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150l_vadc ADC_GPIO1_PU2>, + <&pm8150l_vadc ADC_GPIO2_PU2>; + + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp", + "hw_version_gpio5", + "project_gpio6"; + + qcom,battery-data = <&mtp_batterydata>; + dpdm-supply = <&usb2_phy0>; + qcom,distinguish-qc-class-ab; + //qcom,lpd-enable; + qcom,lpd-disable; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + qcom,wd-bark-time-secs = <16>; +}; + +&qupv3_se1_i2c { + status = "ok"; + tfa98xx@34 { + compatible = "nxp,tfa98xx"; + reset-gpio = <&tlmm 59 0>; + irq-gpio = <&tlmm 141 0>; + interrupt-parent = <&tlmm>; + interrupts = <141 0>; + interrupt-names = "smartpa_irq"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&smartpa_int_active &smartpa_enable_active>; + pinctrl-1 = <&smartpa_int_suspend &smartpa_enable_suspend>; + reg = <0x34>; + status = "ok"; + }; +}; + +&pm8150l_pwm { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; + fsa4480@43 { + status = "disabled"; + }; + + akm09970@c { + compatible = "akm,akm09970"; + reg = <0xC>; + interrupt-parent = <&tlmm>; + interrupts = <120 0>; + akm,gpio-reset = <&tlmm 11 0x00>; + akm,gpio-irq = <&tlmm 27 0x00>; + akm,measure-freq-hz = <100>; + vdd-supply = <&pm8150l_l8>; + + pinctrl-names = "akm09970_gpio_active", "akm09970_gpio_suspend"; + pinctrl-0 = <&akm_irq_active &akm_reset_active>; + pinctrl-1 = <&akm_irq_suspend &akm_reset_suspend>; + status = "ok"; + }; +}; + +&soc { + ti,drv8846@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "ti,drv8846"; + pwms = <&pm8150l_pwm 1 1000000>; + motor,gpio-mode0 = <&tlmm 21 0x00>; + motor,gpio-mode1 = <&tlmm 33 0x00>; + motor,gpio-sleep = <&tlmm 35 0x00>; + motor,gpio-dir = <&tlmm 9 0x00>; + motor,gpio-pwren = <&tlmm 130 0x00>; + + motor,rampup-pwm-period-ns = <625000>; + motor,rampup-duration-ms = <50>; + motor,high-pwm-period-ns = <52083>; + motor,high-duration-ms = <720>; + motor,rampdown-pwm-period-ns = <625000>; + motor,rampdown-duration-ms = <50>; + motor,step-mode = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm_out_gpio10_default &motor_gpio_default>; + status = "ok"; + }; + + simtray { + compatible = "xiaomi,simtray-status"; + status-gpio = <&tlmm 112 0x00>; + }; +}; + +&pm8150l_gpios { + pwm_out_gpio10 { + pwm_out_gpio10_default: pwm_out_gpio10_default { + pins = "gpio10"; + function = "func1"; + bias-disable; + power-source = <1>; + output-low; + qcom,drive-strength = <3>; + drive-push-pull; + }; + }; +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x83 0x70 + 0x2c 0x74>; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&soc { + touch_vddio_vreg: touch_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + //gpio = <&tlmm 99 0>; + }; + + vdd_boost_vreg: vdd_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-always-on; + gpio = <&pm8150b_gpios 5 0>; + }; + + fingerprint_goodix { + compatible = "goodix,fingerprint"; + goodix,gpio-reset = <&tlmm 37 0x0>; + goodix,gpio-irq = <&tlmm 118 0x0>; + fp-gpio-pwr = <&tlmm 125 0>; + status = "ok"; + }; + + xiaomi_touch { + compatible = "xiaomi-touch"; + status = "ok"; + touch,name = "xiaomi-touch"; + }; + + disp_vci_vreg: disp_vci_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 99 0>; + }; +}; + +&qupv3_se19_i2c { + status = "ok"; + goodix@5d { + compatible = "goodix,gt9889"; + reg = <0x5d>; + status = "ok"; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2800>; + //vtouch-supply = <&pm660l_l8>; + //iotouch-supply = <&pm660_l13>; + vtouch-load = <600000>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend"; + pinctrl-0 = <&tp_active>; + pinctrl-1 = <&tp_int_suspend &tp_reset_suspend>; + goodix,reset-gpio = <&tlmm 54 0x0>; + goodix,irq-gpio = <&tlmm 122 0x2800>; + goodix,vdd-gpio = <&tlmm 98 0x0>; /* 3v3 */ + goodix,avdd-gpio = <&tlmm 100 0x0>; /* 1v8 */ + goodix,irq-flags = <2>; /* 1:trigger rising, 2:trigger falling;*/ + goodix,panel-max-id = <10>; + goodix,panel-max-x = <1079>; + goodix,panel-max-y = <2339>; + goodix,panel-max-w = <127>; + goodix,panel-max-p = <127>; + goodix,panel-max-fod = <127>; + /* goodix,panel-key-map = <158 172 217>; */ /*KEY_BACK, KEY_HOMEPAGE, KEY_SEARCH*/ + goodix,power-on-delay-us = <300000>; /*300ms*/ + goodix,power-off-delay-us = <5000>; + goodix,cfg-name = "goodix_gt9886_cfg_f11.bin"; + normal-cfg = [ + ]; + /* goodix,swap-axis; */ + /* goodix,pen-enable; */ + /* goodix,key-of-pen = <331 332>; */ /*BTN_STYLUS, BTN_STYLUS2*/ + sensor0 { + goodix,limit-name = "goodix_gt9886_limit_f11_second.tporder"; + goodix,fw-name = "goodix_gt9886_fw_f11.bin"; + goodix,x2x; + goodix,y2y; + }; + sensor1 { + goodix,limit-name = "goodix_gt9886_limit_f11_first.tporder"; + goodix,fw-name = "goodix_gt9886_fw_f11.bin"; + }; + }; +}; + + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + cam_therm0 { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + cam_therm1 { + reg = ; + label = "skin_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + hw_version_gpio5 { + reg = ; + label = "hw_version_gpio5"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + project_gpio6 { + reg = ; + label = "project_gpio6"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_adc_tm { + io-channels = <&pm8150b_vadc ADC_AMUX_THM1_PU2>, + <&pm8150b_vadc ADC_AMUX_THM2_PU2>; + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + pm8150b-wp-therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + cam_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + cam_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm8150b_haptics { + qcom,actuator-type = "erm"; + qcom,vmax-mv = <3000>; + + wf_0 { + /* CLICK */ + qcom,effect-id = <0>; + qcom,wf-vmax-mv = <3000>; + qcom,wf-pattern = [3e 3e 3e]; + qcom,wf-brake-pattern = [01 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,effect-id = <1>; + qcom,wf-vmax-mv = <3000>; + qcom,wf-pattern = [7e 7e 02 02 02 02 02 02]; + qcom,wf-repeat-count = <2>; + qcom,wf-s-repeat-count = <1>; + qcom,lra-auto-resonance-disable; + }; + wf_2 { + /* TICK */ + qcom,effect-id = <2>; + qcom,wf-vmax-mv = <3000>; + qcom,wf-pattern = [7e 7e]; + qcom,lra-auto-resonance-disable; + }; + wf_3 { + /* THUD */ + qcom,effect-id = <3>; + qcom,wf-vmax-mv = <3000>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,lra-auto-resonance-disable; + }; + wf_4 { + /* POP */ + qcom,effect-id = <4>; + qcom,wf-vmax-mv = <3000>; + qcom,wf-pattern = [7e 7e]; + qcom,lra-auto-resonance-disable; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,effect-id = <5>; + qcom,wf-vmax-mv = <3000>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-brake-pattern = [03 00 00 00]; + qcom,lra-auto-resonance-disable; + }; +}; + +&pm8150l_lpg { + qcom,lut-pattern-switch; + qcom,lut-patterns = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 + 12 11 10 9 8 7 6 5 4 3 2 1 0>; + qcom,lut-patterns-camera = <0 1 3 5 8 10 12 15 18 22 26 32 38 44 50 60 72 82 90 96 98 99 100 + 99 98 96 90 82 72 60 50 44 38 32 26 22 18 15 12 10 8 5 3 1 0>; +}; + +&pwm_lpg2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <70>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <30>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <26>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; +}; + +&pwm_lpg3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <70>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <30>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <26>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; +}; + +&red_led { + status = "disabled"; +}; + +&pm8150l_wled { + qcom,string-cfg= <15>;// if use 2 string, the number is 3 + qcom,leds-per-string = <5>; + status = "ok"; +}; + +&sde_dsi { + vcie-supply = <&disp_vci_vreg>; +}; + +&soc { + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi_rp"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-audio-overlay.dtsi new file mode 100644 index 000000000000..932345af8fc4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-audio-overlay.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../common/sm8150-audio-overlay.dtsi" + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS4", + "MIC BIAS4", "Analog Mic5"; + + qcom,wsa-max-devs = <0>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-usbc-audio-supported = <0>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <2600>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; +}; + +&wcd934x_cdc { + qcom,cdc-micbias1-mv = <2700>; + qcom,cdc-micbias2-mv = <2700>; + qcom,cdc-micbias3-mv = <2700>; + qcom,cdc-micbias4-mv = <2700>; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-pinctrl.dtsi new file mode 100644 index 000000000000..4909875dcadf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-pinctrl.dtsi @@ -0,0 +1,617 @@ +/*for xiaomi pinctrl*/ +&tlmm { + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + bq2597x { + bq2597x_master_int_default: bq2597x_master_int_default { + /* active state */ + mux { + /* GPIO 10 is used for bq25970 master ic interrupt usage */ + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + bq2597x_master_int_suspend: bq2597x_master_int_suspend { + /* sleep state */ + mux { + /* GPIO 10 is used for bq25970 master ic interrupt usage */ + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + }; + + onewire_gpio_active: onewire_gpio_active { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; /* No PULL */ + }; + }; + + onewire_gpio_sleep: onewire_gpio_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio122", "gpio12"; + function = "gpio"; + }; + config { + pins = "gpio122", "gpio12"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + config { + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + adc2_switch_gpio_ctrl { + adc2_switch_gpio_idle: adc2_switch_idle { + mux { + pins = "gpio142"; + function = "gpio"; + }; + config { + pins = "gpio142"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + adc2_switch_gpio_active: adc2_switch_active { + mux { + pins = "gpio142"; + function = "gpio"; + }; + config { + pins = "gpio142"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + sbu_uart_en_ctrl { + sbu_uart_en_idle: uart_audio_en_idle { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + sbu_uart_en_active: uart_audio_en_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + config { + pins = "gpio25"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + + pcie1 { + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio102"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio48", "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio102"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + cam_sensor_active_macro: cam_sensor_active_macro { + /* RESET macro */ + mux { + pins = "gpio27", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_macro: cam_sensor_suspend_macro { + /* RESET MACRO */ + mux { + pins = "gpio27", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + test_mode_ctrl_irq { + ant_sub_ctrl_irq: ant_sub_ctrl_irq { + mux { + pins = "gpio81"; + function = "gpio"; + }; + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + ant_top_ctrl_irq: ant_top_ctrl_irq { + mux { + pins = "gpio133"; + function = "gpio"; + }; + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + }; +}; + +//camera voltage start +&cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio30", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio59"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio30", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio59"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_rear_aux { + /* RESET REARAUX, VANA REARAUX */ + mux { + pins = "gpio23", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_front { + /* RESET FRONT, VANA FRONT*/ + mux { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + function = "gpio"; + }; + + config { + //pins = "gpio54","gpio132","gpio118"; + pins = "gpio54","gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_active_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_iris { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio28","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; +&cam_sensor_active_macro { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio27","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27","gpio94"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_suspend_macro { + /* RESET ULTRA, VANA VDIG ULTRA*/ + mux { + pins = "gpio27","gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio27","gpio94"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +//camera voltage end diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..0919672f22d8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150-camera-sensor-mtp.dtsi @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux1: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + wled-flash-support; + flash-source = <&wled_flash>; + torch-source = <&wled_torch>; + switch-source = <&wled_switch>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + actuator_rear_regulator: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "actuator_rear_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 24 0>; + vin-supply = <&pm8150l_bob>; + }; + +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio","cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + + }; + //imx582 + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150_s5>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + cam_v_custom2-supply = <&pm8150l_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom2"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 1904000 1352000 0 3008000>; + rgltr-max-voltage = <1800000 2040000 1352000 0 4000000>; + rgltr-load-current = <180000 112000 120000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 59 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + //s5k3t2 + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x2>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 1352000 0>; + rgltr-max-voltage = <1800000 4000000 1352000 0>; + rgltr-load-current = <1000 80000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 13 0>, + <&tlmm 54 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&cam_cci1 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 0>; + rgltr-max-voltage = <1800000 4000000 0>; + rgltr-load-current = <180000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 15 0>, + <&tlmm 23 0>, + <&tlmm 94 0>, + <&tlmm 125 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-standby = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1", + "CAM_PWDN1"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + + }; + + eeprom_rear_ultra: qcom,eeprom@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <1000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_iris>; + gpios = <&tlmm 16 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_macro: qcom,eeprom@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <180000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_macro>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_macro>; + gpios = <&tlmm 16 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK4"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + //ov02b1b + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 0>; + rgltr-max-voltage = <1800000 4000000 0>; + rgltr-load-current = <180000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 15 0>, + <&tlmm 23 0>, + <&tlmm 94 0>, + <&tlmm 125 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-standby = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1", + "CAM_PWDN1"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + //ov8856 + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x3>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_ultra>; + led-flash-src = <&led_flash_rear_aux1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 1352000 0>; + rgltr-max-voltage = <1800000 4000000 1352000 0>; + rgltr-load-current = <1000 80000 12000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_iris>; + gpios = <&tlmm 16 0>, + <&tlmm 28 0>, + <&tlmm 94 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + //hi259 + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_macro>; + led-flash-src = <&led_flash_rear_aux2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 3008000 0>; + rgltr-max-voltage = <1800000 4000000 0>; + rgltr-load-current = <180000 112000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_macro>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_macro>; + gpios = <&tlmm 16 0>, + <&tlmm 27 0>, + <&tlmm 94 0>, + <&tlmm 84 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-standby = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4", + "CAM_PWDN4"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi new file mode 100644 index 000000000000..795454af9060 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi @@ -0,0 +1,1979 @@ +/* +this file is for attribution only of vayu +And public attribution of xiaomi platforms(like J20S and so and) +*/ +#include "vayu-pinctrl.dtsi" +#include "../common/xiaomi-sm8150-common.dtsi" +#include "vayu-sm8150-camera-sensor-mtp.dtsi" + +&ufshc_mem { + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; + qcom,vccq-parent-supply = <&pm8150l_s8>; + qcom,vccq-parent-max-microamp = <210000>; + vccq-supply = <&pm8150_l9>; + vccq-max-microamp = <700000>; +}; + +#include "../common/smb1390.dtsi" + + + +&pm8150b_fg { + qcom,battery-data = <&vayu_batterydata>; + qcom,rapid-soc-dec-en; + qcom,soc-scale-mode-en; + qcom,five-pin-battery; + qcom,soc-hi-res; + qcom,soc_decimal_rate = < + 0 38 + 10 35 + 20 33 + 30 33 + 40 33 + 50 33 + 60 33 + 70 30 + 80 25 + 90 20 + 95 10 >; + qcom,ki-coeff-low-chg = <315>; + qcom,ki-coeff-med-chg = <183>; + qcom,fg-sys-term-current = <(-300)>; + qcom,fg-ffc-sys-term-current = <(-1160)>; + qcom,fg-cutoff-voltage = <3400>; + qcom,fg-cutoff-current = <200>; + qcom,fg-empty-voltage = <3100>; + qcom,soc-scale-vbatt-mv = <3600>; + qcom,fg-batt-temp-delta = <6>; + qcom,fg-force-load-profile; + qcom,shutdown-delay-enable; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; + qcom,ki-coeff-chg-med-hi-thresh-ma = <1000>; + qcom,ki-coeff-chg-low-med-thresh-ma = <500>; + qcom,ffc-ki-coeff-chg-med-hi-thresh-ma = <3900>; + qcom,ffc-ki-coeff-chg-low-med-thresh-ma = <3500>; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <0>; + qcom,usb-icl-ua = <3000000>; + qcom,fcc-max-ua = <5900000>; + qcom,fv-max-uv = <4475000>; + qcom,non-fcc-fv-max-uv = <4450000>; + //qcom,chg-warm-th= <450>; + //qcom,chg-cool-th= <150>; + qcom,auto-recharge-soc = <99>; + qcom,chg-term-src = <1>; + qcom,chg-term-current-ma = <(-200)>; + mi,use-bq-pump; + qcom,usbpd-phandle = <&pm8150b_pdphy>; + qcom,battery-data = <&vayu_batterydata>; + //mi,six-pin-step-chg-params = <4250000 6000000 + // 4450000 5400000 + // 4480000 4000000>; + //mi,six-pin-step-chg; + //mi,six-pin-soc-th = <45>; + mi,fcc-batt-unverify-ua = <2000000>; + mi,support-ffc; + qcom,disable-suspend-on-collapse; + qcom,thermal-mitigation = <3000000 2800000 2600000 2400000 2200000 2100000 2000000 + 1800000 1600000 1500000 1400000 1200000 1000000 900000 + 800000 500000>; + qcom,thermal-mitigation-icl + = <2800000 2700000 2600000 2400000 2200000 2100000 2000000 + 2000000 2000000 2000000 2000000 2000000 2000000 2000000 + 2000000 2000000>; + qcom,thermal-mitigation-dcp + = <1800000 1800000 1800000 1800000 1800000 1800000 1800000 + 1800000 1800000 1700000 1600000 1400000 1200000 1100000 + 1100000 1000000>; + qcom,thermal-mitigation-qc2 + = <1500000 1500000 1500000 1500000 1450000 1400000 1350000 + 1300000 1150000 1100000 1000000 900000 850000 750000 + 650000 500000>; + qcom,thermal-fcc-qc3-normal + = <3200000 3000000 2800000 2600000 2500000 2400000 2300000 + 2200000 2100000 1800000 1600000 1400000 1200000 1000000 + 750000 750000>; + qcom,thermal-fcc-qc3-cp + = <3600000 3600000 3600000 3600000 3200000 3200000 3200000 + 3200000 3100000 2800000 2400000 2200000 2000000 1300000 + 750000 300000>; + qcom,thermal-fcc-qc3-classb-cp + = <4800000 4700000 4600000 4500000 4400000 4200000 4200000 + 4200000 4000000 3600000 3400000 3200000 3000000 2200000 + 1000000 300000>; + qcom,thermal-mitigation-pd-base + = <3000000 2800000 2600000 2500000 2500000 2500000 2500000 + 2500000 2500000 2400000 2200000 2000000 1600000 1300000 + 1000000 500000>; + qcom,thermal-fcc-pps-cp + = <4800000 4700000 4600000 4500000 4400000 4200000 4200000 + 4200000 4000000 3600000 3400000 3200000 3000000 2200000 + 1000000 300000>; + qcom,thermal-fcc-pps-bq + = <6000000 5700000 5475000 5250000 5025000 4800000 4575000 + 4350000 4100000 3500000 3000000 2400000 2000000 1500000 + 1000000 500000>; + qcom,thermal-fcc-qc3-cp + = <4800000 4600000 4400000 4200000 4000000 3800000 3600000 + 3400000 3000000 2600000 2400000 2200000 2000000 1300000 + 1000000 300000>; + qcom,thermal-fcc-qc3-classb-cp + = <5100000 4700000 4300000 4000000 3600000 3500000 3400000 + 3400000 3400000 3200000 2500000 2200000 2000000 1300000 + 1000000 300000>; + qcom,thermal-mitigation-pd-base + = <3000000 2800000 2600000 2400000 2200000 2000000 1800000 + 1600000 1600000 1400000 1200000 1100000 1050000 1000000 + 950000 500000>; + qcom,thermal-mitigation-voice + = <6000000 2200000 2200000 1000000 1000000 800000 800000 + 800000 800000 700000 700000 600000 600000 600000 + 500000 400000>; + + + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp"; +// qcom,battery-data = <&mtp_batterydata>; + dpdm-supply = <&usb2_phy0>; + qcom,distinguish-qc-class-ab; + qcom,lpd-disable; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + qcom,wd-bark-time-secs = <16>; +}; + +&ext_5v_boost { + status = "disable"; +}; + +&pm8150b_pdphy { + mi,non-qcom-pps-ctrl; +}; + +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + bq25970-standalone@66 { + compatible = "ti,bq2597x-standalone"; + reg = <0x66>; + interrupt-parent = <&tlmm>; + interrupts = <10 0x2002>; + pinctrl-names = "default"; + pinctrl-0 = <&bq2597x_master_int_default &bq2597x_master_int_suspend>; + + /*ti,bq2597x,bat-ovp-disable;*/ + ti,bq2597x,bat-ovp-alarm-disable; + ti,bq2597x,bat-ocp-disable; + ti,bq2597x,bat-ocp-alarm-disable; + ti,bq2597x,bat-ucp-alarm-disable; + ti,bq2597x,bat-ucp-disable; + + /*ti,bq2597x,bus-ovp-alarm-disable; + ti,bq2597x,bus-ocp-disable; + ti,bq2597x,bus-ocp-alarm-disable;*/ + ti,bq2597x,bat-therm-disable; + ti,bq2597x,bus-therm-disable; + ti,bq2597x,die-therm-disable; + + ti,bq2597x,bat-ovp-threshold = <4550>; + ti,bq2597x,bat-ovp-alarm-threshold = <4525>; + //ti,bq2597x,bat-ocp-threshold = <8000>; + //ti,bq2597x,bat-ocp-alarm-threshold = <7500>; + + ti,bq2597x,bus-ovp-threshold = <12000>; + ti,bq2597x,bus-ovp-alarm-threshold = <11000>; + ti,bq2597x,bus-ocp-threshold = <3750>; + ti,bq2597x,bus-ocp-alarm-threshold = <3500>; + + //ti,bq2597x,bat-ucp-alarm-threshold = <2000>; + + ti,bq2597x,bat-therm-threshold = <0x15>;/*4.1%*/ + ti,bq2597x,bus-therm-threshold = <0x15>;/*4.1%*/ + ti,bq2597x,die-therm-threshold = <145>; + + ti,bq2597x,ac-ovp-threshold = <14>; + //ti,bq2597x,sense-resistor-mohm = <2>; + + }; +}; + +&soc { + cp_qc30 { + compatible = "xiaomi,cp-qc30"; + status = "ok"; + mi,qc3-bat-volt-max = <4420>; + mi,qc3-bat-curr-max = <3600>; + mi,qc3-bus-volt-max = <12000>; + mi,qc3-bus-curr-max = <2100>; + mi,qc3-battery-warm-th = <450>; + mi,use-qcom-gauge; + //mi,cp-sec-enable; + }; + + usbpd_pm { + compatible = "xiaomi,usbpd-pm"; + status = "ok"; + mi,pd-bat-volt-max = <4500>; + mi,pd-ffc-bat-volt-max = <4480>; + mi,pd-bat-curr-max = <6000>; + mi,pd-bus-volt-max = <12000>; + mi,pd-bus-curr-max = <3000>; + mi,pd-non-ffc-bat-volt-max = <4450>; + mi,pd-bus-curr-compensate = <0>; + mi,pd-battery-warm-th = <450>; + mi,use-qcom-gauge; + //mi,cp-sec-enable; + }; + + onewire_gpio: onewire_gpio { + compatible = "xiaomi,onewire_gpio"; + label = "xm_onewire"; + xiaomi,version = <1>; + xiaomi,ow_gpio = <&tlmm 21 0x00>; + mi,onewire-gpio-cfg-addr = <0x03515000 0x4>; + xiaomi,gpio_number = <21>; + pinctrl-names = "onewire_active", "onewire_sleep"; + pinctrl-0 = <&onewire_gpio_active>; + pinctrl-1 = <&onewire_gpio_sleep>; + status = "ok"; + }; + vayu_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "../common/battery/fg-gen4-batterydata-vayu-NVT-5160mah.dtsi" + #include "../common/battery/fg-gen4-batterydata-vayu-sunwoda-5160mah.dtsi" + }; + + maxim_ds28e16: maxim_ds28e16 { + compatible = "maxim,ds28e16"; + label = "max_ds28e16"; + maxim,version = <1>; + status = "ok"; + }; + + simtray { + compatible = "xiaomi,simtray-status"; + status-gpio = <&tlmm 112 0x00>; + }; +}; + +&qupv3_se4_i2c { + status = "ok"; + tas2557@4c { + status = "disabled"; + compatible = "ti,tas2557"; + reg = <0x4c>; + //ti,cdc-reset-gpio = <&tlmm 59 0>; + ti,irq-gpio = <&tlmm 60 0>; + ti,i2s-bits = <16>; + ti,bypass-tmax = <0>; + }; + + fsa4480@43 { + status = "disabled"; + }; + + cs35l41@40 { + status = "disabled"; + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + cs,cdc-reset-gpio = <&tlmm 89 0x01>; + reg = <0x40>; + pinctrl-names = "cs35l41_irq_default"; + pinctrl-0 = <&cs35l41_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <10 8>; + + cirrus,temp-warn_threshold = <3>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; +/* + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + interrupt-parent = <&tlmm>; + interrupts = <11 8>; + reset-gpios = <&tlmm 7 0x01>; + VA-supply = <&pm8998_s4>; + VP-supply = <&audio_vsys>; + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x4>; + cirrus,gpio-output-enable; + }; +*/ + }; +}; + +&qupv3_se7_i2c { + status = "ok"; + tas256x:tas256x@4c { + #sound-dai-cells = <0>; + compatible = "ti,tas256x";/*or "ti,tas2564" or "ti,tas256x" */ + reg = <0x4c>;//register tas256x_i2c_driver + ti,left-channel = <0x4d>; //receiver address + ti,right-channel = <0x4c>; //speaker address + ti,channels = <2>; /* channel number */ + ti,reset-gpio = <&tlmm 89 0>; //SPKR_RST1 + ti,reset-gpio2 = <&tlmm 92 0>; //SPKR_RST2 + pinctrl-names = "default"; + //pinctrl-0 = <&reset_stat_default>; + //ti,reset-gpio = <&pm6150l_gpios 8 GPIO_ACTIVE_LOW>; + ti,irq-gpio = <&tlmm 90 0>;//spkr_int1 left + ti,irq-gpio2 = <&tlmm 91 0>;//spkr_int2 right + status = "ok"; + ti,iv-width = <16>; + ti,vbat-mon = <0>; + }; +}; + +&smb1390 { + status = "disabled"; +}; + +&smb1390_charger { + status = "disabled"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x84 0x70 + 0x2c 0x74>; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&soc { + touch_vddio_vreg: touch_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 100 0>; + }; + + vdd_boost_vreg: vdd_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_boost_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-always-on; + gpio = <&pm8150b_gpios 5 0>; + }; + + disp_vci_vreg: disp_vci_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 21 0>; + }; + + fingerprint_goodix { + compatible = "goodix,fingerprint"; + goodix,gpio-reset = <&tlmm 37 0x0>; + goodix,gpio-irq = <&tlmm 120 0x0>; + //goodix.gpio_pwr = <&tlmm 125 0x0>; + //fp_vdd_vreg = <&pm8150l_l7>; + status = "ok"; + }; + + + fingerprint_fpc { + compatible = "fpc,fpc1020"; + fpc,gpio_rst = <&tlmm 37 0x0>; + fpc,gpio_irq = <&tlmm 120 0x0>; + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active", + "fpc1020_irq_active"; + + pinctrl-0 = <&msm_gpio_37>; + pinctrl-1 = <&msm_gpio_37_output_high>; + pinctrl-2 = <&msm_gpio_120>; + status = "ok"; + }; + + + xiaomi_touch { + compatible = "xiaomi-touch"; + status = "ok"; + touch,name = "xiaomi-touch"; + }; + + testing_mode { + compatible = "modem,testing-mode"; + status-gpio = <&tlmm 81 0x00>, + <&tlmm 133 0x00>; + debounce-time = <30>; + pinctrl-names = "default"; + pinctrl-0 = <&ant_sub_ctrl_irq &ant_top_ctrl_irq>; + }; +}; + +/*Touch SPI state init*/ +&qupv3_se17_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <6>; + // bias-disable; + bias-pull-down; + }; +}; + +&qupv3_se17_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <6>; + bias-pull-down; + }; +}; + +&qupv3_se17_spi { + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; +}; + +/*IC int pin, rst pin init*/ +&tlmm { + ts_mux { + ts_int_active: ts_int_active { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + ts_reset_active: ts_reset_active { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ts_cs_active: ts_cs_active { + mux { + pins = "gpio58"; + function = "qup17"; + }; + + config { + pins = "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + ts_cs_suspend: ts_cs_suspend { + mux { + pins = "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio58"; + drive-strength = <6>; + bias-pull-down; + output-low; + }; + }; + }; +}; + +&ts_int_suspend { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <16>; + bias-disable; + input-enable; + }; +}; + +&ts_reset_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-disable; + }; +}; + +&qupv3_se17_spi { + status = "ok"; + touch_spi@0 { + compatible = "xiaomi,spi-for-tp"; + reg = <0>; + status = "ok"; + spi-max-frequency = <10000000>; //10M + }; +}; + +/* Novatek device tree node */ +&soc { + ts_novatek { + compatible = "novatek,NVT-ts-spi"; + status = "ok"; + spi-max-frequency = <10000000>; /*4800000,9600000,15000000,19200000 10M*/ + novatek,reset-gpio = <&tlmm 12 0x00>; + novatek,irq-gpio = <&tlmm 122 0x2001>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active &ts_cs_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend &ts_cs_suspend>; + /* 672 */ + /*novatek,swrst-n8-addr = <0x01F01A>;*/ + /* 672A */ + novatek,swrst-n8-addr = <0x03F0FE>; + novatek,spi-rd-fast-addr = <0x03F310>; + /* MP */ + novatek,mp-support-dt; + novatek,config-array-size = <2>; + novatek,cfg_0 { + novatek,tp-vendor = <0x46>; + novatek,display-maker = <0x36>; + novatek,fw-name = "j20s_novatek_ts_fw01.bin"; + novatek,mp-name = "j20s_novatek_ts_mp01.bin"; + novatek,clicknum-file-name = "nvt+tianma"; + }; + novatek,cfg_1 { + novatek,tp-vendor = <0x53>; + novatek,display-maker = <0x42>; + novatek,fw-name = "j20s_novatek_ts_fw02.bin"; + novatek,mp-name = "j20s_novatek_ts_mp02.bin"; + novatek,clicknum-file-name = "nvt+csot"; + }; + /* for Xiaomi J20S 672C CSOT6.67" module */ + novatek-mp-criteria-594B@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "novatek-mp-criteria-594B"; + /* MP Config */ + IC_X_CFG_SIZE = <18>; + IC_Y_CFG_SIZE = <36>; + IC_KEY_CFG_SIZE = <4>; + X_Channel = <18>; + Y_Channel = <36>; + AIN_X = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17>; + AIN_Y = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 + 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35>; + AIN_KEY = <0 1 2 0xFF>; + /* MP Criteria */ + PS_Config_Lmt_Short_Rawdata_P = < + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008>; + + PS_Config_Lmt_Short_Rawdata_N = < + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 + 10000 10000 10000>; + + PS_Config_Lmt_Open_Rawdata_P = < + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 + 5120 5120 5120>; + + PS_Config_Lmt_Open_Rawdata_N = < + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) + (-511) (-511) (-511)>; + + PS_Config_Lmt_FW_Rawdata_P = < + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 3840 + 3840 3840 3840>; + + PS_Config_Lmt_FW_Rawdata_N = < + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 + 240 240 240>; + + PS_Config_Lmt_FW_CC_P = < + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 + 314 314 314>; + + PS_Config_Lmt_FW_CC_N = < + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0>; + + PS_Config_Lmt_FW_Diff_P = < + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75>; + + PS_Config_Lmt_FW_Diff_N = < + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75)>; + + PS_Config_Diff_Test_Frame = <50>; + }; + + /* for Xiaomi J20S 672C TM6.67" module */ + novatek-mp-criteria-594A@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "novatek-mp-criteria-594A"; + + /* MP Config */ + IC_X_CFG_SIZE = <16>; + IC_Y_CFG_SIZE = <36>; + IC_KEY_CFG_SIZE = <4>; + X_Channel = <16>; + Y_Channel = <36>; + AIN_X = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + AIN_Y = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 + 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35>; + AIN_KEY = <0 1 2 0xFF>; + + /* MP Criteria */ + PS_Config_Lmt_Short_Rawdata_P = < + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 + 14008 14008 14008>; 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+ + PS_Config_Lmt_FW_CC_N = < + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0>; + + PS_Config_Lmt_FW_Diff_P = < + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 + 75 75 75>; + + PS_Config_Lmt_FW_Diff_N = < + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) + (-75) (-75) (-75)>; + + PS_Config_Diff_Test_Frame = <50>; + }; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2008>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + vdd-supply = <&touch_vddio_vreg>; + avdd-supply = <&pm8150l_l1>; + fts,pwr-reg-name = "avdd"; + fts,bus-reg-name = "vdd"; + fts,irq-gpio = <&tlmm 122 0x2008>; + fts,irq-gpio-name = "fts_irq"; + fts,reset-gpio-enable; + fts,reset-gpio = <&tlmm 12 0x00>; + fts,reset-gpio-name = "fts_rst"; + fts,irq-flags = <0x2008>; // IRQF_ONESHOT | IRQF_TRIGGER_LOW + fts,x-max = <1080>; + fts,y-max = <2340>; + fts,default-fw-name = "st_fts_f1.ftb"; + fts,config-array-size = <1>; + fts,dump-click-count; + fts,touch-up-threshold-min = <40>; + fts,touch-up-threshold-max = <120>; + fts,touch-up-threshold-def = <80>; + fts,touch-tolerance-min = <5>; + fts,touch-tolerance-max = <35>; + fts,touch-tolerance-def = <25>; + fts,touch-wgh-min-def = <1>; + fts,touch-wgh-min-max = <15>; + fts,touch-wgh-min-min = <0>; + fts,touch-wgh-max-def = <5>; + fts,touch-wgh-max-max = <15>; + fts,touch-wgh-max-min = <0>; + fts,touch-wgh-step-def = <1>; + fts,touch-wgh-step-max = <2>; + fts,touch-wgh-step-min = <0>; + fts,edgefilter-leftrigt-def = <45>; + fts,edgefilter-topbottom-def = <0>; + fts,edgefilter-top-ingamemode = <0>; + fts,edgefilter-bottom-ingamemode = <0>; + fts,edgefilter-area-step1 = <100>; + fts,edgefilter-area-step2 = <170>; + fts,edgefilter-area-step3 = <250>; + fts,cfg_0 { + fts,tp-vendor = <0x48>; + fts,fw-name = "st_fts_f1.ftb"; + fts,limit-name = "stm_fts_production_limits.csv"; + fts,clicknum-file-name = "fts+sdc"; + }; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 102 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + //qcom,nq-esepwr = <&tlmm 42 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&qupv3_se1_spi { + status = "ok"; + irled@0 { + compatible = "ir-spi"; + reg = <0x0>; + status = "ok"; + spi-max-frequency = <19200000>; + }; +}; + +&pm8150l_lpg { + qcom,lut-patterns = <0 1 2 3 4 5 7 9 11 13 15 + 13 11 9 7 5 4 3 2 1 0>; +}; + +&pwm_lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; +}; + +&red_led { + label = "white"; +}; + +&green_led { + status = "disabled"; +}; + +&blue_led { + status = "disabled"; +}; + +&mdss_mdp { + clock-rate = <0 0 0 0 345000000 19200000 300000000 19200000>; +}; + + +&sde_dsi { + vcie-supply = <&disp_vci_vreg>; +}; + +&dsi_samsung_fhd_ea8076_f1mp_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; +}; + +&dsi_samsung_fhd_ea8076_f1p2_2_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; +}; + +&dsi_samsung_fhd_ea8076_f1p2_cmd { + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_external_supply>; +}; + +&dsi_j20s_36_02_0a_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_j20s_42_02_0b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&pm8150l_wled { + status = "okay"; + qcom,string-cfg = <7>; + qcom,ovp = <28000>; + qcom,fs-current-limit = <22500>; + qcom,cabc-sel = <1>; +}; + + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + cam_therm0 { + reg = ; + label = "cam_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + cam_therm1 { + reg = ; + label = "cam_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + cam_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + cam_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <2800>; + qcom,play-rate-us = <5102>; + + wf_0 { + /* CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_2 { + /* TICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 3e]; + qcom,wf-brake-pattern = [03 01 01 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_3 { + /* THUD */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_4 { + /* POP */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e]; + qcom,wf-brake-pattern = [02 01 00 00]; + qcom,wf-play-rate-us = <5102>; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-brake-pattern = [03 03 01 00]; + qcom,wf-play-rate-us = <5102>; + }; +}; + +&soc { + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi_vy"; + }; + + thermal_message: thermal-message { + board-sensor = "quiet_therm"; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + status = "ok"; + }; + +&tlmm { + /* GPIO_37 : FP_RESET_N */ + msm_gpio_37: msm_gpio_37 { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + /* GPIO_37 : FP_RESET_N, state device active*/ + msm_gpio_37_output_high: msm_gpio_37_output_high { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + /* GPIO_120 : FP_INT_N */ + msm_gpio_120: msm_gpio_120 { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + diff --git a/include/uapi/linux/input-event-codes.h b/include/uapi/linux/input-event-codes.h index 18ae64ebd2c1..dae4dde06926 100644 --- a/include/uapi/linux/input-event-codes.h +++ b/include/uapi/linux/input-event-codes.h @@ -639,6 +639,12 @@ #define KEY_UNMUTE 0x274 #define KEY_FASTREVERSE 0x275 #define KEY_SLOWREVERSE 0x276 + +/* + * AI KEY + */ +#define KEY_AI 0x2b1 + /* * Control a data application associated with the currently viewed channel, * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) From 05f3cbfe2170b3b202440433ae9591eab58adb2b Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Thu, 23 Jun 2022 03:27:16 +0200 Subject: [PATCH 009/226] arch: arm64: boot: dts: qcom: xiaomi: Adapt analog USB-C for newer audio drivers Change-Id: Icb4ca6cadf5caed7d79dd04a4291fee98d4dca35 Signed-off-by: firebird11 --- .../boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi | 6 +++--- .../andromeda/andromeda-audio-overlay.dtsi | 15 ++++++++++----- .../overlay/andromeda/andromeda-pinctrl.dtsi | 6 +++--- .../overlay/cepheus/cepheus-audio-overlay.dtsi | 15 ++++++++++----- .../xiaomi/overlay/crux/crux-audio-overlay.dtsi | 15 ++++++++++----- .../qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi | 6 +++--- 6 files changed, 39 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi index 444d383a00a3..ec7306e17938 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150-pinctrl.dtsi @@ -118,8 +118,8 @@ }; }; - wcd_usbc_analog_en2 { - wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle { + wcd_usbc_analog_en2n { + wcd_usbc_analog_en2n_idle: wcd_usbc_ana_en2n_idle { mux { pins = "gpio58"; function = "gpio"; @@ -132,7 +132,7 @@ }; }; - wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active { + wcd_usbc_analog_en2n_active: wcd_usbc_ana_en2n_active { mux { pins = "gpio58"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi index a243e7d415ae..b3ea6495be41 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-audio-overlay.dtsi @@ -37,18 +37,16 @@ qcom,adc2-switch-gpio = <&adc2_switch_gpio>; qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,fsa4476-gpio-support = <1>; - qcom,usbc-analog-en1-gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en1_gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2_n_gpio = <&wcd_usbc_analog_en2n_gpio>; qcom,usbc-analog-en2-gpio = <&tlmm 35 0>; pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", - "quat_tdm_enable", "quat_tdm_disable", - "aud_active", "aud_sleep"; + "quat_tdm_enable", "quat_tdm_disable"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active>; pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; - pinctrl-4 = <&wcd_usbc_analog_en2_active>; - pinctrl-5 = <&wcd_usbc_analog_en2_idle>; }; &soc { @@ -73,4 +71,11 @@ pinctrl-1 = <&wcd_usbc_analog_en1_idle>; }; + wcd_usbc_analog_en2n_gpio: msm_cdc_pinctrl_usbc_audio_en2 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en2n_active>; + pinctrl-1 = <&wcd_usbc_analog_en2n_idle>; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi index 6bf9122c3e6c..309558a92cd5 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/andromeda/andromeda-pinctrl.dtsi @@ -391,8 +391,8 @@ }; }; - wcd_usbc_analog_en2 { - wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle { + wcd_usbc_analog_en2n { + wcd_usbc_analog_en2n_idle: wcd_usbc_ana_en2n_idle { mux { pins = "gpio35"; function = "gpio"; @@ -405,7 +405,7 @@ }; }; - wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active { + wcd_usbc_analog_en2n_active: wcd_usbc_ana_en2n_active { mux { pins = "gpio35"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi index 7877060e5e35..d36f44af1498 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-audio-overlay.dtsi @@ -38,18 +38,16 @@ qcom,adc2-switch-gpio = <&adc2_switch_gpio>; qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,fsa4476-gpio-support = <1>; - qcom,usbc-analog-en1-gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en1_gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2_n_gpio = <&wcd_usbc_analog_en2n_gpio>; qcom,usbc-analog-en2-gpio = <&tlmm 58 0>; pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", - "quat_tdm_enable", "quat_tdm_disable", - "aud_active", "aud_sleep"; + "quat_tdm_enable", "quat_tdm_disable"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active>; pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; - pinctrl-4 = <&wcd_usbc_analog_en2_active>; - pinctrl-5 = <&wcd_usbc_analog_en2_idle>; }; &soc { @@ -73,4 +71,11 @@ pinctrl-0 = <&wcd_usbc_analog_en1_active>; pinctrl-1 = <&wcd_usbc_analog_en1_idle>; }; + + wcd_usbc_analog_en2n_gpio: msm_cdc_pinctrl_usbc_audio_en2 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en2n_active>; + pinctrl-1 = <&wcd_usbc_analog_en2n_idle>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi index 5d5c471561aa..81046219851a 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-audio-overlay.dtsi @@ -36,18 +36,16 @@ /* qcom,adc2-switch-gpio = <&adc2_switch_gpio>; */ qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,fsa4476-gpio-support = <1>; - qcom,usbc-analog-en1-gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en1_gpio = <&wcd_usbc_analog_en1_gpio>; + qcom,usbc-analog-en2_n_gpio = <&wcd_usbc_analog_en2n_gpio>; qcom,usbc-analog-en2-gpio = <&tlmm 32 0>; pinctrl-names = "quat_mi2s_enable", "quat_mi2s_disable", - "quat_tdm_enable", "quat_tdm_disable", - "aud_active", "aud_sleep"; + "quat_tdm_enable", "quat_tdm_disable"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; pinctrl-1 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; pinctrl-2 = <&quat_tdm_active &quat_tdm_dout_active>; pinctrl-3 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; - pinctrl-4 = <&wcd_usbc_analog_en2_active>; - pinctrl-5 = <&wcd_usbc_analog_en2_idle>; }; &soc { @@ -71,4 +69,11 @@ pinctrl-0 = <&wcd_usbc_analog_en1_active>; pinctrl-1 = <&wcd_usbc_analog_en1_idle>; }; + + wcd_usbc_analog_en2n_gpio: msm_cdc_pinctrl_usbc_audio_en2 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd_usbc_analog_en2n_active>; + pinctrl-1 = <&wcd_usbc_analog_en2n_idle>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi index 4155e541eab1..1106980222e3 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-pinctrl.dtsi @@ -505,8 +505,8 @@ }; }; - wcd_usbc_analog_en2 { - wcd_usbc_analog_en2_idle: wcd_usbc_ana_en2_idle { + wcd_usbc_analog_en2n { + wcd_usbc_analog_en2n_idle: wcd_usbc_ana_en2n_idle { mux { pins = "gpio32"; function = "gpio"; @@ -519,7 +519,7 @@ }; }; - wcd_usbc_analog_en2_active: wcd_usbc_ana_en2_active { + wcd_usbc_analog_en2n_active: wcd_usbc_ana_en2n_active { mux { pins = "gpio32"; function = "gpio"; From 60a7e680f3dcdea262bc91a3f519b6d06c0a6d86 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 10 Jul 2022 16:09:00 +0200 Subject: [PATCH 010/226] arch: arm64: boot: dts: qcom: xiaomi: vayu: Add ln8000 support * Extracted from stock dtbo Change-Id: I79733a52cddc8bb011ef679bf317babb5055fe0f Signed-off-by: firebird11 --- .../qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi index 795454af9060..b65899889e98 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi @@ -215,6 +215,26 @@ And public attribution of xiaomi platforms(like J20S and so and) //ti,bq2597x,sense-resistor-mohm = <2>; }; + + ln8000_charger@51 { + compatible = "lionsemi,ln8000"; + reg = <0x51>; + ln8000_charger,irq_index = <0x128>; + ln8000_charger,bat-ovp-threshold = <0x11d0>; + ln8000_charger,bat-ovp-alarm-threshold = <0x11ad>; + ln8000_charger,bus-ovp-threshold = <0x32c8>; + ln8000_charger,bus-ovp-alarm-threshold = <0x2af8>; + ln8000_charger,bus-ocp-threshold = <0xea6>; + ln8000_charger,bus-ocp-alarm-threshold = <0xdac>; + ln8000_charger,ntc-alarm-cfg = <0xe2>; + ln8000_charger,tdie-prot-disable; + ln8000_charger,tbus-mon-disable; + ln8000_charger,tbat-mon-disable; + ln8000_charger,iin-ocp-disable; + ln8000_charger,iin-reg-disable; + ln8000_charger,tdie-reg-disable; + ln8000_charger,vbat-reg-disable; + }; }; &soc { From 66e45d6a13d333182229eac31d5629e8403ea6a4 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 16 Apr 2024 23:53:57 +0200 Subject: [PATCH 011/226] arch: arm64: boot: dts: qcom: xiaomi: nabu: Remove fingerprint bindings nabu doesn't have fingerprint, thanks Xiaomi Change-Id: Ide1fa63add29925e219f7b8c88d0ff225b9b11d4 Signed-off-by: firebird11 --- .../qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi | 25 ------------------- 1 file changed, 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi index 06be84bc688d..f31136085341 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi @@ -488,31 +488,6 @@ And public attribution of xiaomi platforms(like J20S and so and) gpio = <&pm8150b_gpios 5 0>; }; - fingerprint_goodix { - compatible = "goodix,fingerprint"; - goodix,gpio-reset = <&tlmm 37 0x0>; - goodix,gpio-irq = <&tlmm 120 0x0>; - //goodix.gpio_pwr = <&tlmm 125 0x0>; - //fp_vdd_vreg = <&pm8150l_l7>; - status = "ok"; - }; - - - fingerprint_fpc { - compatible = "fpc,fpc1020"; - fpc,gpio_rst = <&tlmm 37 0x0>; - fpc,gpio_irq = <&tlmm 120 0x0>; - pinctrl-names = "fpc1020_reset_reset", - "fpc1020_reset_active", - "fpc1020_irq_active"; - - pinctrl-0 = <&msm_gpio_37>; - pinctrl-1 = <&msm_gpio_37_output_high>; - pinctrl-2 = <&msm_gpio_120>; - status = "ok"; - }; - - xiaomi_touch { compatible = "xiaomi-touch"; status = "ok"; From 966750614612ceb6abaab7662eb7b170caeca94c Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 00:58:45 +0100 Subject: [PATCH 012/226] drivers: char: Import Xiaomi changes Change-Id: I25159512098a4af867382e81d03f46b509e3763e Signed-off-by: firebird11 --- drivers/char/adsprpc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 0957d29a6ee2..0417cf13313e 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -4619,15 +4619,32 @@ static int fastrpc_probe(struct platform_device *pdev) if (range.addr && !of_property_read_bool(dev->of_node, "restrict-access")) { int srcVM[1] = {VMID_HLOS}; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int destVM[4] = {VMID_HLOS, VMID_MSS_MSA, VMID_SSC_Q6, + VMID_ADSP_Q6}; +#else int destVM[3] = {VMID_HLOS, VMID_SSC_Q6, VMID_ADSP_Q6}; +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int destVMperm[4] = {PERM_READ | PERM_WRITE | PERM_EXEC, +#else int destVMperm[3] = {PERM_READ | PERM_WRITE | PERM_EXEC, +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 + PERM_READ | PERM_WRITE | PERM_EXEC, +#endif PERM_READ | PERM_WRITE | PERM_EXEC, PERM_READ | PERM_WRITE | PERM_EXEC, }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + VERIFY(err, !hyp_assign_phys(range.addr, range.size, + srcVM, 1, destVM, destVMperm, 4)); +#else VERIFY(err, !hyp_assign_phys(range.addr, range.size, srcVM, 1, destVM, destVMperm, 3)); +#endif if (err) goto bail; me->range.addr = range.addr; From 61fa7ef584aacc6a2252f1e4cb688b800ae73b33 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 29 Jan 2024 20:59:38 +0100 Subject: [PATCH 013/226] drivers: clk: qcom: mdss: Import Xiaomi changes Change-Id: I19de141ce55d00ea1af4473025e35e1049ede365 Signed-off-by: firebird11 --- drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c index dacb68ca8e1f..831db0488804 100644 --- a/drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c +++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c @@ -554,6 +554,12 @@ static void dsi_pll_setup_config(struct dsi_pll_7nm *pll, config->enable_ssc = rsc->ssc_en; config->ssc_center = rsc->ssc_center; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (pll->cphy_enabled) { + config->enable_ssc = false; + } +#endif + if (config->enable_ssc) { if (rsc->ssc_freq) config->ssc_freq = rsc->ssc_freq; From 3699fa68f7f4b025ebe31a32e62df97d13c034ac Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 17:22:59 +0200 Subject: [PATCH 014/226] drivers: cpufreq: Import Xiaomi changes Change-Id: Ic287243d1ea995dc014f1e57f828d2e5ac09f0f9 Signed-off-by: firebird11 --- drivers/cpufreq/cpufreq.c | 6 ++++++ include/linux/cpufreq.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index ea51a776c6ca..a8ef00ab1a07 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2267,6 +2267,12 @@ static int cpufreq_set_policy(struct cpufreq_policy *policy, blocking_notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_INCOMPATIBLE, new_policy); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* the adjusted frequency should not exceed thermal limit */ + blocking_notifier_call_chain(&cpufreq_policy_notifier_list, + CPUFREQ_THERMAL, new_policy); +#endif + /* * verify the cpu speed can be set within this limit, which might be * different to the first one diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index ed0ff1538049..f1ca2468f8a0 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -429,6 +429,9 @@ static inline void cpufreq_resume(void) {} /* Policy Notifiers */ #define CPUFREQ_ADJUST (0) #define CPUFREQ_NOTIFY (1) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CPUFREQ_THERMAL (2) +#endif #define CPUFREQ_INCOMPATIBLE (6) #ifdef CONFIG_CPU_FREQ From 8c14852617c5fb6780d7fe208196f9b5cd43d584 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 2 Dec 2019 03:49:20 +0100 Subject: [PATCH 015/226] drivers: gpu: drm: msm: extend qcom drm notifier Change-Id: Id266a34b20403a9f3ef445902730f293712bf260 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 15 ++++++++++++++- drivers/gpu/drm/msm/msm_atomic.c | 3 ++- include/linux/msm_drm_notify.h | 5 +++++ 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 5dc4961d0a8e..893d1c8d47e3 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -19,6 +19,8 @@ #include #include +#include + #include "msm_drv.h" #include "sde_connector.h" #include "msm_mmu.h" @@ -1058,6 +1060,8 @@ int dsi_display_set_power(struct drm_connector *connector, int power_mode, void *disp) { struct dsi_display *display = disp; + struct msm_drm_notifier notify_data; + int event = power_mode; int rc = 0; if (!display || !display->panel) { @@ -1065,17 +1069,26 @@ int dsi_display_set_power(struct drm_connector *connector, return -EINVAL; } + notify_data.data = &event; + switch (power_mode) { case SDE_MODE_DPMS_LP1: + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ify_data); rc = dsi_panel_set_lp1(display->panel); + msm_drm_notifier_call_chain(MSM_DRM_EVENT_BLANK, ¬ify_data); break; case SDE_MODE_DPMS_LP2: + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ify_data); rc = dsi_panel_set_lp2(display->panel); + msm_drm_notifier_call_chain(MSM_DRM_EVENT_BLANK, ¬ify_data); break; case SDE_MODE_DPMS_ON: if (display->panel->power_mode == SDE_MODE_DPMS_LP1 || - display->panel->power_mode == SDE_MODE_DPMS_LP2) + display->panel->power_mode == SDE_MODE_DPMS_LP2) { + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ify_data); rc = dsi_panel_set_nolp(display->panel); + msm_drm_notifier_call_chain(MSM_DRM_EVENT_BLANK, ¬ify_data); + } break; case SDE_MODE_DPMS_OFF: default: diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 39f1e7c3b4c0..d681a20d2080 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -73,11 +73,12 @@ EXPORT_SYMBOL(msm_drm_unregister_client); * @v: notifier data, inculde display id and display blank * event(unblank or power down). */ -static int msm_drm_notifier_call_chain(unsigned long val, void *v) +int msm_drm_notifier_call_chain(unsigned long val, void *v) { return blocking_notifier_call_chain(&msm_drm_notifier_list, val, v); } +EXPORT_SYMBOL(msm_drm_notifier_call_chain); /* block until specified crtcs are no longer pending update, and * atomically mark them as pending update diff --git a/include/linux/msm_drm_notify.h b/include/linux/msm_drm_notify.h index 924ba852c99c..4f9b32662ad5 100644 --- a/include/linux/msm_drm_notify.h +++ b/include/linux/msm_drm_notify.h @@ -23,6 +23,10 @@ enum { /* panel: power on */ MSM_DRM_BLANK_UNBLANK, + MSM_DRM_BLANK_LP1, + MSM_DRM_BLANK_LP2, + MSM_DRM_BLANK_STANDBY, + MSM_DRM_BLANK_SUSPEND, /* panel: power off */ MSM_DRM_BLANK_POWERDOWN, }; @@ -42,4 +46,5 @@ struct msm_drm_notifier { int msm_drm_register_client(struct notifier_block *nb); int msm_drm_unregister_client(struct notifier_block *nb); +int msm_drm_notifier_call_chain(unsigned long val, void *v); #endif From 76417ed2b8997edf713eae3829bf2ba315139fbe Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 8 Jul 2019 01:54:18 +0200 Subject: [PATCH 016/226] drivers: gpu: drm: msm: handle ss dcs type Change-Id: I0a707338911a937afe1bdb4562da1ef102c5a59e Signed-off-by: firebird11 --- drivers/gpu/drm/drm_mipi_dsi.c | 14 ++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 9 ++++++++- drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 1 + include/drm/drm_mipi_dsi.h | 2 ++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 4b31f35dcc49..4aa005b5c40c 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -1058,6 +1058,20 @@ int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline) } EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_scanline); +int mipi_dsi_dcs_set_display_brightness_ss(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = { brightness >> 8, brightness & 0xff }; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} + /** * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of the * display diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index eb96af4751b1..10ad5fa1164d 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -623,7 +623,11 @@ static int dsi_panel_update_backlight(struct dsi_panel *panel, if (panel->bl_config.bl_inverted_dbv) bl_lvl = (((bl_lvl & 0xff) << 8) | (bl_lvl >> 8)); - rc = mipi_dsi_dcs_set_display_brightness(dsi, bl_lvl); + if (panel->bl_config.dcs_type_ss) + rc = mipi_dsi_dcs_set_display_brightness_ss(dsi, bl_lvl); + else + rc = mipi_dsi_dcs_set_display_brightness(dsi, bl_lvl); + if (rc < 0) pr_err("failed to update dcs backlight:%d\n", bl_lvl); @@ -2272,6 +2276,9 @@ static int dsi_panel_parse_bl_config(struct dsi_panel *panel) panel->bl_config.type = DSI_BACKLIGHT_UNKNOWN; } + panel->bl_config.dcs_type_ss = utils->read_bool(utils->data, + "qcom,mdss-dsi-bl-dcs-type-ss"); + data = utils->get_property(utils->data, "qcom,bl-update-flag", NULL); if (!data) { panel->bl_config.bl_update = BL_UPDATE_NONE; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index 2ed6f0980dea..fcf1ba3db846 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -121,6 +121,7 @@ struct dsi_backlight_config { bool bl_inverted_dbv; int en_gpio; + bool dcs_type_ss; /* PWM params */ struct pwm_device *pwm_bl; bool pwm_enabled; diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index d80635d66bef..1e090439b7a4 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -286,6 +286,8 @@ int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format); int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline); int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, u16 brightness); +int mipi_dsi_dcs_set_display_brightness_ss(struct mipi_dsi_device *dsi, + u16 brightness); int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, u16 *brightness); int mipi_dsi_dcs_set_display_brightness_large(struct mipi_dsi_device *dsi, From 1a871b690131be9e1f0a3c669ee69123a2633653 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 8 Jul 2019 01:56:43 +0200 Subject: [PATCH 017/226] drivers: gpu: drm: msm: modify lp11 mode logic Change-Id: I630f67c0d2ec1537ef236fb8363ee84f13e953d4 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 33 +++++++++++++++++---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 10ad5fa1164d..63b71103751a 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -447,6 +447,10 @@ static int dsi_panel_power_on(struct dsi_panel *panel) goto error_disable_vregs; } + /* If LP11_INIT is set, skip panel reset here*/ + if (panel->lp11_init) + goto exit; + rc = dsi_panel_reset(panel); if (rc) { pr_err("[%s] failed to reset panel, rc=%d\n", panel->name, rc); @@ -3817,9 +3821,11 @@ int dsi_panel_pre_prepare(struct dsi_panel *panel) mutex_lock(&panel->panel_lock); +#if 0 /* If LP11_INIT is set, panel will be powered up during prepare() */ if (panel->lp11_init) goto error; +#endif rc = dsi_panel_power_on(panel); if (rc) { @@ -3967,12 +3973,19 @@ int dsi_panel_prepare(struct dsi_panel *panel) mutex_lock(&panel->panel_lock); if (panel->lp11_init) { +#if 0 rc = dsi_panel_power_on(panel); if (rc) { pr_err("[%s] panel power on failed, rc=%d\n", panel->name, rc); goto error; } +#endif + rc = dsi_panel_reset(panel); + if (rc) { + pr_err("[%s] failed to reset panel, rc=%d\n", panel->name, rc); + goto error; + } } rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_PRE_ON); @@ -4387,6 +4400,14 @@ int dsi_panel_unprepare(struct dsi_panel *panel) goto error; } + if (!panel->lp11_init) { + rc = dsi_panel_power_off(panel); + if (rc) { + pr_err("[%s] panel power_Off failed, rc=%d\n", + panel->name, rc); + goto error; + } + } error: mutex_unlock(&panel->panel_lock); return rc; @@ -4403,11 +4424,13 @@ int dsi_panel_post_unprepare(struct dsi_panel *panel) mutex_lock(&panel->panel_lock); - rc = dsi_panel_power_off(panel); - if (rc) { - pr_err("[%s] panel power_Off failed, rc=%d\n", - panel->name, rc); - goto error; + if (panel->lp11_init) { + rc = dsi_panel_power_off(panel); + if (rc) { + pr_err("[%s] panel power_Off failed, rc=%d\n", + panel->name, rc); + goto error; + } } error: mutex_unlock(&panel->panel_lock); From 9e8a5f0b3f3cc4eabebc60a254e7e8b7ce2c7a64 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Sun, 5 Apr 2020 22:41:58 +0200 Subject: [PATCH 018/226] drivers: gpu: drm: msm: dsi-staging: create empty attributes group Change-Id: I974643cb245f76e66b208f7e18601cbb3d90ae62 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 893d1c8d47e3..0889cb8f3a7e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -5044,11 +5044,22 @@ static int dsi_display_validate_split_link(struct dsi_display *display) return rc; } +static struct attribute *display_fs_attrs[] = { + NULL, +}; +static struct attribute_group display_fs_attrs_group = { + .attrs = display_fs_attrs, +}; + static int dsi_display_sysfs_init(struct dsi_display *display) { int rc = 0; struct device *dev = &display->pdev->dev; + rc = sysfs_create_group(&dev->kobj, &display_fs_attrs_group); + if (rc) + pr_err("failed to create display device attributes"); + if (display->panel->panel_mode == DSI_OP_CMD_MODE) rc = sysfs_create_group(&dev->kobj, &dynamic_dsi_clock_fs_attrs_group); From 1762e70bc84785ca4c45b18179eb3f8d5173bcb4 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Thu, 21 May 2020 02:06:33 +0300 Subject: [PATCH 019/226] drivers: gpu: drm: msm: sde: translate zpos property to fod property Change-Id: I7e8562ed3eda675d160d6dabee7e568a1a72e849 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/sde/sde_plane.c | 44 +++++++++++++++-------------- 2 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index f9460152091e..4bf2972595ea 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -103,6 +103,7 @@ enum msm_mdp_plane_property { /* range properties */ PLANE_PROP_ZPOS = PLANE_PROP_BLOBCOUNT, + PLANE_PROP_FOD, PLANE_PROP_ALPHA, PLANE_PROP_COLOR_FILL, PLANE_PROP_H_DECIMATE, diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 686d50391236..7e6887476cb9 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -3976,6 +3976,7 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, case PLANE_PROP_ALPHA: case PLANE_PROP_INPUT_FENCE: case PLANE_PROP_BLEND_OP: + case PLANE_PROP_FOD: /* no special action required */ break; case PLANE_PROP_FB_TRANSLATION_MODE: @@ -4381,8 +4382,6 @@ static void _sde_plane_install_properties(struct drm_plane *plane, const struct sde_format_extended *format_list; struct sde_kms_info *info; struct sde_plane *psde = to_sde_plane(plane); - int zpos_max = 255; - int zpos_def = 0; char feature_name[256]; if (!plane || !psde) { @@ -4399,24 +4398,11 @@ static void _sde_plane_install_properties(struct drm_plane *plane, psde->catalog = catalog; - if (sde_is_custom_client()) { - if (catalog->mixer_count && - catalog->mixer[0].sblk->maxblendstages) { - zpos_max = catalog->mixer[0].sblk->maxblendstages - 1; - - if (catalog->has_base_layer && - (zpos_max > SDE_STAGE_MAX - 1)) - zpos_max = SDE_STAGE_MAX - 1; - else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1) - zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1; - } - } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) { - /* reserve zpos == 0 for primary planes */ - zpos_def = drm_plane_index(plane) + 1; - } - msm_property_install_range(&psde->property_info, "zpos", - 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS); + 0x0, 0, INT_MAX, 0, PLANE_PROP_ZPOS); + + msm_property_install_range(&psde->property_info, "fod", + 0x0, 0, INT_MAX, 0, PLANE_PROP_FOD); msm_property_install_range(&psde->property_info, "alpha", 0x0, 0, 255, 255, PLANE_PROP_ALPHA); @@ -4855,6 +4841,8 @@ static int sde_plane_atomic_set_property(struct drm_plane *plane, { struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL; struct sde_plane_state *pstate; + struct drm_property *fod_property; + uint64_t fod_val = 0; int idx, ret = -EINVAL; SDE_DEBUG_PLANE(psde, "\n"); @@ -4865,11 +4853,25 @@ static int sde_plane_atomic_set_property(struct drm_plane *plane, SDE_ERROR_PLANE(psde, "invalid state\n"); } else { pstate = to_sde_plane_state(state); + idx = msm_property_index(&psde->property_info, + property); + if (idx == PLANE_PROP_ZPOS) { + if (val & 0x20000000u) { + val &= ~0x20000000u; + fod_val = 1; + } + + fod_property = psde->property_info. + property_array[PLANE_PROP_FOD]; + ret = msm_property_atomic_set(&psde->property_info, + &pstate->property_state, + fod_property, fod_val); + if (ret) + SDE_ERROR("failed to set fod prop"); + } ret = msm_property_atomic_set(&psde->property_info, &pstate->property_state, property, val); if (!ret) { - idx = msm_property_index(&psde->property_info, - property); switch (idx) { case PLANE_PROP_INPUT_FENCE: _sde_plane_set_input_fence(psde, pstate, val); From 4f39124396486672e7fddde4879bde1c9f60fab9 Mon Sep 17 00:00:00 2001 From: DevriesL Date: Mon, 31 Dec 2018 21:42:21 +0800 Subject: [PATCH 020/226] drivers: gpu: drm: msm: dsi-staging: add get_main_display Change-Id: Id670875adc18659521c424a716cf0ef194f9627f Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 7 +++++++ drivers/gpu/drm/msm/dsi-staging/dsi_display.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 0889cb8f3a7e..3694720b94ed 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -61,6 +61,8 @@ static const struct of_device_id dsi_display_dt_match[] = { {} }; +struct dsi_display *primary_display; + static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display, u32 mask, bool enable) { @@ -6435,6 +6437,7 @@ int dsi_display_get_modes(struct dsi_display *display, exit: *out_modes = display->modes; rc = 0; + primary_display = display; error: if (rc) @@ -7828,6 +7831,10 @@ int dsi_display_unprepare(struct dsi_display *display) return rc; } +struct dsi_display *get_main_display(void) { + return primary_display; +} + static int __init dsi_display_register(void) { dsi_phy_drv_register(); diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 7bf06a243c5a..694304fd722b 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -712,4 +712,6 @@ int dsi_display_cont_splash_config(void *display); int dsi_display_get_panel_vfp(void *display, int h_active, int v_active); +struct dsi_display *get_main_display(void); + #endif /* _DSI_DISPLAY_H_ */ From 703edf72133eba9b355890dc03661d62e06c482f Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 25 May 2020 13:21:16 +0200 Subject: [PATCH 021/226] drivers: gpu: drm: msm: dsi-staging: add dsi_panel_get_backlight Change-Id: Ifab7f9b0a7fbe5846c24c611a16cfcb7f29684dc Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 63b71103751a..3fd8f3056dc1 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -689,6 +689,11 @@ static int dsi_panel_update_pwm_backlight(struct dsi_panel *panel, return rc; } +static u32 dsi_panel_get_backlight(struct dsi_panel *panel) +{ + return panel->bl_config.bl_level; +} + int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) { int rc = 0; From 60eef6e311b231ca65b9c669e07ac0ee43afa821 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 6 Apr 2020 01:02:05 +0200 Subject: [PATCH 022/226] drivers: gpu: drm: msm: implement fod handling Change-Id: Id29333eb3b5282b25c52ff14492622bd12e1ee79 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_defs.h | 2 + drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 117 ++++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 13 +++ drivers/gpu/drm/msm/sde/sde_connector.c | 35 ++++++ drivers/gpu/drm/msm/sde/sde_crtc.c | 87 +++++++++++++++ drivers/gpu/drm/msm/sde/sde_crtc.h | 1 + drivers/gpu/drm/msm/sde/sde_plane.c | 12 ++ drivers/gpu/drm/msm/sde/sde_plane.h | 2 + 8 files changed, 269 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index 3613e8e1588b..c1817b9612f8 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -308,6 +308,8 @@ enum dsi_cmd_set_type { DSI_CMD_SET_POST_TIMING_SWITCH, DSI_CMD_SET_QSYNC_ON, DSI_CMD_SET_QSYNC_OFF, + DSI_CMD_SET_DISP_HBM_FOD_ON, + DSI_CMD_SET_DISP_HBM_FOD_OFF, DSI_CMD_SET_MAX }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 3fd8f3056dc1..896be2ff23b0 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -694,6 +694,53 @@ static u32 dsi_panel_get_backlight(struct dsi_panel *panel) return panel->bl_config.bl_level; } +static u32 interpolate(uint32_t x, uint32_t xa, uint32_t xb, uint32_t ya, uint32_t yb) +{ + return ya - (ya - yb) * (x - xa) / (xb - xa); +} + +u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) +{ + u32 brightness = dsi_panel_get_backlight(panel); + int i; + + if (!panel->fod_dim_lut) + return 0; + + for (i = 0; i < panel->fod_dim_lut_count; i++) + if (panel->fod_dim_lut[i].brightness >= brightness) + break; + + if (i == 0) + return panel->fod_dim_lut[i].alpha; + + if (i == panel->fod_dim_lut_count) + return panel->fod_dim_lut[i - 1].alpha; + + return interpolate(brightness, + panel->fod_dim_lut[i - 1].brightness, panel->fod_dim_lut[i].brightness, + panel->fod_dim_lut[i - 1].alpha, panel->fod_dim_lut[i].alpha); +} + +int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status) +{ + int rc = 0; + + if (status) { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_DISP_HBM_FOD_ON); + if (rc) + pr_err("[%s] failed to send DSI_CMD_SET_DISP_HBM_FOD_ON cmd, rc=%d\n", + panel->name, rc); + } else { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_DISP_HBM_FOD_OFF); + if (rc) + pr_err("[%s] failed to send DSI_CMD_SET_DISP_HBM_FOD_OFF cmd, rc=%d\n", + panel->name, rc); + } + + return rc; +} + int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) { int rc = 0; @@ -1762,6 +1809,8 @@ const char *cmd_set_prop_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-post-mode-switch-on-command", "qcom,mdss-dsi-qsync-on-commands", "qcom,mdss-dsi-qsync-off-commands", + "qcom,mdss-dsi-dispparam-hbm-fod-on-command", + "qcom,mdss-dsi-dispparam-hbm-fod-off-command", }; const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { @@ -1788,6 +1837,8 @@ const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-post-mode-switch-on-command-state", "qcom,mdss-dsi-qsync-on-commands-state", "qcom,mdss-dsi-qsync-off-commands-state", + "qcom,mdss-dsi-dispparam-hbm-fod-on-command-state", + "qcom,mdss-dsi-dispparam-hbm-fod-off-command-state", }; static int dsi_panel_get_cmd_pkt_count(const char *data, u32 length, u32 *cnt) @@ -2254,6 +2305,68 @@ static int dsi_panel_parse_bl_pwm_config(struct dsi_panel *panel) return rc; } +static int dsi_panel_parse_fod_dim_lut(struct dsi_panel *panel, + struct dsi_parser_utils *utils) +{ + struct brightness_alpha_pair *lut; + u32 *array; + int count; + int len; + int rc; + int i; + + len = utils->count_u32_elems(utils->data, "qcom,disp-fod-dim-lut"); + if (len <= 0 || len % BRIGHTNESS_ALPHA_PAIR_LEN) { + pr_err("[%s] invalid number of elements, rc=%d\n", + panel->name, rc); + rc = -EINVAL; + goto count_fail; + } + + array = kcalloc(len, sizeof(u32), GFP_KERNEL); + if (!array) { + pr_err("[%s] failed to allocate memory, rc=%d\n", + panel->name, rc); + rc = -ENOMEM; + goto alloc_array_fail; + } + + rc = utils->read_u32_array(utils->data, + "qcom,disp-fod-dim-lut", array, len); + if (rc) { + pr_err("[%s] failed to allocate memory, rc=%d\n", + panel->name, rc); + goto read_fail; + } + + count = len / BRIGHTNESS_ALPHA_PAIR_LEN; + lut = kcalloc(count, sizeof(*lut), GFP_KERNEL); + if (!lut) { + rc = -ENOMEM; + goto alloc_lut_fail; + } + + for (i = 0; i < count; i++) { + struct brightness_alpha_pair *pair = &lut[i]; + pair->brightness = array[i * BRIGHTNESS_ALPHA_PAIR_LEN + 0]; + pair->alpha = array[i * BRIGHTNESS_ALPHA_PAIR_LEN + 1]; + } + + panel->fod_dim_lut = lut; + panel->fod_dim_lut_count = count; + +alloc_lut_fail: +read_fail: + kfree(array); +alloc_array_fail: +count_fail: + if (rc) { + panel->fod_dim_lut = NULL; + panel->fod_dim_lut_count = 0; + } + return rc; +} + static int dsi_panel_parse_bl_config(struct dsi_panel *panel) { int rc = 0; @@ -2343,6 +2456,10 @@ static int dsi_panel_parse_bl_config(struct dsi_panel *panel) panel->bl_config.bl_inverted_dbv = utils->read_bool(utils->data, "qcom,mdss-dsi-bl-inverted-dbv"); + rc = dsi_panel_parse_fod_dim_lut(panel, utils); + if (rc) + pr_err("[%s failed to parse fod dim lut\n", panel->name); + if (panel->bl_config.type == DSI_BACKLIGHT_PWM) { rc = dsi_panel_parse_bl_pwm_config(panel); if (rc) { diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index fcf1ba3db846..d36d69006282 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -169,6 +169,12 @@ struct drm_panel_esd_config { u32 groups; }; +#define BRIGHTNESS_ALPHA_PAIR_LEN 2 +struct brightness_alpha_pair { + u32 brightness; + u32 alpha; +}; + struct dsi_panel { const char *name; const char *type; @@ -219,6 +225,9 @@ struct dsi_panel { bool sync_broadcast_en; int power_mode; enum dsi_panel_physical_type panel_type; + + struct brightness_alpha_pair *fod_dim_lut; + u32 fod_dim_lut_count; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -339,4 +348,8 @@ int dsi_panel_parse_esd_reg_read_configs(struct dsi_panel *panel); void dsi_panel_ext_bridge_put(struct dsi_panel *panel); +int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status); + +u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel); + #endif /* _DSI_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index d0f36c7a00bf..5e909b003f15 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -583,6 +583,39 @@ static int _sde_connector_update_dirty_properties( return 0; } +void sde_connector_update_fod_hbm(struct drm_connector *connector) +{ + static atomic_t effective_status = ATOMIC_INIT(false); + struct sde_crtc_state *cstate; + struct sde_connector *c_conn; + struct dsi_display *display; + bool status; + + if (!connector) { + SDE_ERROR("invalid connector\n"); + return; + } + + c_conn = to_sde_connector(connector); + if (c_conn->connector_type != DRM_MODE_CONNECTOR_DSI) + return; + + display = (struct dsi_display *) c_conn->display; + + if (!c_conn->encoder || !c_conn->encoder->crtc || + !c_conn->encoder->crtc->state) + return; + + cstate = to_sde_crtc_state(c_conn->encoder->crtc->state); + status = cstate->fod_dim_layer != NULL; + if (atomic_xchg(&effective_status, status) == status) + return; + + mutex_lock(&display->panel->panel_lock); + dsi_panel_set_fod_hbm(display->panel, status); + mutex_unlock(&display->panel->panel_lock); +} + int sde_connector_pre_kickoff(struct drm_connector *connector) { struct sde_connector *c_conn; @@ -616,6 +649,8 @@ int sde_connector_pre_kickoff(struct drm_connector *connector) SDE_EVT32_VERBOSE(connector->base.id); + sde_connector_update_fod_hbm(connector); + rc = c_conn->ops.pre_kickoff(connector, c_conn->display, ¶ms); end: diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index f39c40c86b98..39e8d9605b0c 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -42,6 +42,7 @@ #include "sde_power_handle.h" #include "sde_core_perf.h" #include "sde_trace.h" +#include "dsi_display.h" #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4) #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2) @@ -2187,6 +2188,10 @@ static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc, for (i = 0; i < cstate->num_dim_layers; i++) _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc, mixer, &cstate->dim_layer[i]); + + if (cstate->fod_dim_layer) + _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc, + mixer, cstate->fod_dim_layer); } _sde_crtc_program_lm_output_roi(crtc); @@ -5301,6 +5306,86 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, return 0; } +static struct sde_hw_dim_layer* sde_crtc_setup_fod_dim_layer( + struct sde_crtc_state *cstate, + uint32_t stage) +{ + struct drm_crtc_state *crtc_state = &cstate->base; + struct drm_display_mode *mode = &crtc_state->adjusted_mode; + struct sde_hw_dim_layer *dim_layer = NULL; + struct dsi_display *display; + struct sde_kms *kms; + uint32_t layer_stage; + uint32_t alpha; + + kms = _sde_crtc_get_kms(crtc_state->crtc); + if (!kms || !kms->catalog) { + SDE_ERROR("Invalid kms\n"); + goto error; + } + + layer_stage = SDE_STAGE_0 + stage; + if (layer_stage >= kms->catalog->mixer[0].sblk->maxblendstages) { + SDE_ERROR("Stage too large %u vs max %u\n", layer_stage, + kms->catalog->mixer[0].sblk->maxblendstages); + goto error; + } + + if (cstate->num_dim_layers == SDE_MAX_DIM_LAYERS) { + SDE_ERROR("Max dim layers reached\n"); + goto error; + } + + display = get_main_display(); + if (!display || !display->panel) { + SDE_ERROR("Invalid primary display\n"); + goto error; + } + + mutex_lock(&display->panel->panel_lock); + alpha = dsi_panel_get_fod_dim_alpha(display->panel); + mutex_unlock(&display->panel->panel_lock); + + dim_layer = &cstate->dim_layer[cstate->num_dim_layers]; + dim_layer->flags = SDE_DRM_DIM_LAYER_INCLUSIVE; + dim_layer->stage = layer_stage; + dim_layer->rect.x = 0; + dim_layer->rect.y = 0; + dim_layer->rect.w = mode->hdisplay; + dim_layer->rect.h = mode->vdisplay; + dim_layer->color_fill = + (struct sde_mdss_color) {0, 0, 0, alpha}; + +error: + return dim_layer; +} + +static void sde_crtc_fod_atomic_check(struct sde_crtc_state *cstate, + struct plane_state *pstates, int cnt) +{ + uint32_t dim_layer_stage; + int plane_idx; + + for (plane_idx = 0; plane_idx < cnt; plane_idx++) + if (sde_plane_is_fod_layer(pstates[plane_idx].drm_pstate)) + break; + + if (plane_idx == cnt) { + cstate->fod_dim_layer = NULL; + } else { + dim_layer_stage = pstates[plane_idx].stage; + cstate->fod_dim_layer = sde_crtc_setup_fod_dim_layer(cstate, + dim_layer_stage); + } + + if (!cstate->fod_dim_layer) + return; + + for (plane_idx = 0; plane_idx < cnt; plane_idx++) + if (pstates[plane_idx].stage >= dim_layer_stage) + pstates[plane_idx].stage++; +} + static int sde_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -5496,6 +5581,8 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, } } + sde_crtc_fod_atomic_check(cstate, pstates, cnt); + /* assign mixer stages based on sorted zpos property */ if (cnt > 0) sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h index 0357ab4f4dfe..b4f52df21cc7 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.h +++ b/drivers/gpu/drm/msm/sde/sde_crtc.h @@ -422,6 +422,7 @@ struct sde_crtc_state { uint64_t input_fence_timeout_ns; uint32_t num_dim_layers; struct sde_hw_dim_layer dim_layer[SDE_MAX_DIM_LAYERS]; + struct sde_hw_dim_layer *fod_dim_layer; uint32_t num_ds; uint32_t num_ds_enabled; bool ds_dirty; diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 7e6887476cb9..5fe08e3afe29 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -4298,6 +4298,18 @@ static void _sde_plane_atomic_disable(struct drm_plane *plane, SDE_SSPP_RECT_SOLO, SDE_SSPP_MULTIRECT_NONE); } +int sde_plane_is_fod_layer(const struct drm_plane_state *drm_state) +{ + struct sde_plane_state *pstate; + + if (!drm_state) + return 0; + + pstate = to_sde_plane_state(drm_state); + + return sde_plane_get_property(pstate, PLANE_PROP_FOD); +} + static void sde_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { diff --git a/drivers/gpu/drm/msm/sde/sde_plane.h b/drivers/gpu/drm/msm/sde/sde_plane.h index b128fb9475cc..bd8b633e2375 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.h +++ b/drivers/gpu/drm/msm/sde/sde_plane.h @@ -398,4 +398,6 @@ void sde_plane_clear_ubwc_error(struct drm_plane *plane); void sde_plane_setup_src_split_order(struct drm_plane *plane, enum sde_sspp_multirect_index rect_mode, bool enable); +int sde_plane_is_fod_layer(const struct drm_plane_state *drm_state); + #endif /* _SDE_PLANE_H_ */ From 4061cecd09ca6ccb72d7db9bc3792575929add41 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Thu, 28 May 2020 23:04:27 +0200 Subject: [PATCH 023/226] drivers: gpu: drm: msm: notify sysfs for fod ui changes Change-Id: I5559a9cfe00af58847e089764452a24c39830e20 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 30 +++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_display.h | 4 +++ drivers/gpu/drm/msm/sde/sde_connector.c | 2 ++ 3 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 3694720b94ed..63cdcf175538 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -5046,7 +5046,29 @@ static int dsi_display_validate_split_link(struct dsi_display *display) return rc; } +static ssize_t sysfs_fod_ui_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dsi_display *display; + bool status; + + display = dev_get_drvdata(dev); + if (!display) { + pr_err("Invalid display\n"); + return -EINVAL; + } + + status = atomic_read(&display->fod_ui); + + return snprintf(buf, PAGE_SIZE, "%d\n", status); +} + +static DEVICE_ATTR(fod_ui, 0444, + sysfs_fod_ui_read, + NULL); + static struct attribute *display_fs_attrs[] = { + &dev_attr_fod_ui.attr, NULL, }; static struct attribute_group display_fs_attrs_group = { @@ -5082,6 +5104,13 @@ static int dsi_display_sysfs_deinit(struct dsi_display *display) } +void dsi_display_set_fod_ui(struct dsi_display *display, bool status) +{ + struct device *dev = &display->pdev->dev; + atomic_set(&display->fod_ui, status); + sysfs_notify(&dev->kobj, NULL, "fod_ui"); +} + /** * dsi_display_bind - bind dsi device with controlling device * @dev: Pointer to base of platform device @@ -5378,6 +5407,7 @@ static void dsi_display_unbind(struct device *dev, } atomic_set(&display->clkrate_change_pending, 0); + atomic_set(&display->fod_ui, false); (void)dsi_display_sysfs_deinit(display); (void)dsi_display_debugfs_deinit(display); diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 694304fd722b..73d8b5ac29dd 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -281,6 +281,8 @@ struct dsi_display { struct dsi_display_boot_param *boot_disp; u32 te_source; + + atomic_t fod_ui; }; int dsi_display_dev_probe(struct platform_device *pdev); @@ -714,4 +716,6 @@ int dsi_display_get_panel_vfp(void *display, struct dsi_display *get_main_display(void); +void dsi_display_set_fod_ui(struct dsi_display *display, bool status); + #endif /* _DSI_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index 5e909b003f15..30a9dbd1d18a 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -614,6 +614,8 @@ void sde_connector_update_fod_hbm(struct drm_connector *connector) mutex_lock(&display->panel->panel_lock); dsi_panel_set_fod_hbm(display->panel, status); mutex_unlock(&display->panel->panel_lock); + + dsi_display_set_fod_ui(display, status); } int sde_connector_pre_kickoff(struct drm_connector *connector) From 762e0dd6dec664d740b8aafc27b14f0c3464be53 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 8 Jun 2020 17:16:57 +0200 Subject: [PATCH 024/226] drivers: gpu: drm: msm: dsi-staging: cleanup notifier implementation Change-Id: If60a789b666cd2c5ab767406d2aeabb03f38ba5b Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 63cdcf175538..d4fc8b2c094c 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -1063,7 +1063,6 @@ int dsi_display_set_power(struct drm_connector *connector, { struct dsi_display *display = disp; struct msm_drm_notifier notify_data; - int event = power_mode; int rc = 0; if (!display || !display->panel) { @@ -1071,7 +1070,8 @@ int dsi_display_set_power(struct drm_connector *connector, return -EINVAL; } - notify_data.data = &event; + notify_data.data = &power_mode; + notify_data.id = MSM_DRM_PRIMARY_DISPLAY; switch (power_mode) { case SDE_MODE_DPMS_LP1: From 67b764adca6da401367347794490b0435361eb89 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 8 Jun 2020 17:06:19 +0200 Subject: [PATCH 025/226] drivers: gpu: drm: msm: atomic: do not trigger drm notifier Change-Id: I185253d2dab8f4f88b38e95e5ac2332667b6a011 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/msm_atomic.c | 41 ++------------------------------ 1 file changed, 2 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index d681a20d2080..8d00a9652ea9 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -218,8 +218,7 @@ msm_disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) struct drm_connector_state *old_conn_state; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; - struct msm_drm_notifier notifier_data; - int i, blank; + int i; SDE_ATRACE_BEGIN("msm_disable"); for_each_connector_in_state(old_state, connector, old_conn_state, i) { @@ -259,14 +258,6 @@ msm_disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) DRM_DEBUG_ATOMIC("disabling [ENCODER:%d:%s]\n", encoder->base.id, encoder->name); - if (connector->state->crtc && - connector->state->crtc->state->active_changed) { - blank = MSM_DRM_BLANK_POWERDOWN; - notifier_data.data = ␣ - notifier_data.id = crtc_idx; - msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, - ¬ifier_data); - } /* * Each encoder has at most one connector (since we always steal * it away), so we won't call disable hooks twice. @@ -282,12 +273,6 @@ msm_disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) funcs->dpms(encoder, DRM_MODE_DPMS_OFF); drm_bridge_post_disable(encoder->bridge); - if (connector->state->crtc && - connector->state->crtc->state->active_changed) { - DRM_DEBUG_ATOMIC("Notify blank\n"); - msm_drm_notifier_call_chain(MSM_DRM_EVENT_BLANK, - ¬ifier_data); - } } for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { @@ -428,12 +413,10 @@ static void msm_atomic_helper_commit_modeset_enables(struct drm_device *dev, struct drm_crtc_state *new_crtc_state; struct drm_connector *connector; struct drm_connector_state *new_conn_state; - struct msm_drm_notifier notifier_data; struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; int bridge_enable_count = 0; - int i, blank; - bool splash = false; + int i; SDE_ATRACE_BEGIN("msm_enable"); for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, @@ -493,19 +476,6 @@ static void msm_atomic_helper_commit_modeset_enables(struct drm_device *dev, DRM_DEBUG_ATOMIC("enabling [ENCODER:%d:%s]\n", encoder->base.id, encoder->name); - if (kms && kms->funcs && kms->funcs->check_for_splash) - splash = kms->funcs->check_for_splash(kms); - - if (splash || (connector->state->crtc && - connector->state->crtc->state->active_changed)) { - blank = MSM_DRM_BLANK_UNBLANK; - notifier_data.data = ␣ - notifier_data.id = - connector->state->crtc->index; - DRM_DEBUG_ATOMIC("Notify early unblank\n"); - msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, - ¬ifier_data); - } /* * Each encoder has at most one connector (since we always steal * it away), so we won't call enable hooks twice. @@ -554,13 +524,6 @@ static void msm_atomic_helper_commit_modeset_enables(struct drm_device *dev, encoder->base.id, encoder->name); drm_bridge_enable(encoder->bridge); - - if (splash || (connector->state->crtc && - connector->state->crtc->state->active_changed)) { - DRM_DEBUG_ATOMIC("Notify unblank\n"); - msm_drm_notifier_call_chain(MSM_DRM_EVENT_BLANK, - ¬ifier_data); - } } SDE_ATRACE_END("msm_enable"); } From e6ee6bb777835c4760ddf3ef02b80859cf9e2195 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 8 Jun 2020 17:18:11 +0200 Subject: [PATCH 026/226] drivers: gpu: drm: msm: dsi-staging: trigger drm notifier Change-Id: I225b36292f96eafb0703e3f0701f924f20b186d5 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_drm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c index 3e4de45ea5b2..6a1f452dcb0a 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c @@ -14,6 +14,8 @@ #define pr_fmt(fmt) "dsi-drm:[%s] " fmt, __func__ +#include + #include #include @@ -172,6 +174,8 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) { int rc = 0; struct dsi_bridge *c_bridge = to_dsi_bridge(bridge); + struct msm_drm_notifier notify_data; + int power_mode; if (!bridge) { pr_err("Invalid params\n"); @@ -186,6 +190,11 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) if (bridge->encoder->crtc->state->active_changed) atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0); + power_mode = sde_connector_get_lp(c_bridge->display->drm_conn); + notify_data.data = &power_mode; + notify_data.id = MSM_DRM_PRIMARY_DISPLAY; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ify_data); + /* By this point mode should have been validated through mode_fixup */ rc = dsi_display_set_mode(c_bridge->display, &(c_bridge->dsi_mode), 0x0); @@ -221,6 +230,8 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) } SDE_ATRACE_END("dsi_display_enable"); + msm_drm_notifier_call_chain(MSM_DRM_EVENT_BLANK, ¬ify_data); + rc = dsi_display_splash_res_cleanup(c_bridge->display); if (rc) pr_err("Continuous splash pipeline cleanup failed, rc=%d\n", @@ -292,12 +303,19 @@ static void dsi_bridge_post_disable(struct drm_bridge *bridge) { int rc = 0; struct dsi_bridge *c_bridge = to_dsi_bridge(bridge); + struct msm_drm_notifier notify_data; + int power_mode; if (!bridge) { pr_err("Invalid params\n"); return; } + power_mode = sde_connector_get_lp(c_bridge->display->drm_conn); + notify_data.data = &power_mode; + notify_data.id = MSM_DRM_PRIMARY_DISPLAY; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ify_data); + SDE_ATRACE_BEGIN("dsi_bridge_post_disable"); SDE_ATRACE_BEGIN("dsi_display_disable"); rc = dsi_display_disable(c_bridge->display); @@ -317,6 +335,8 @@ static void dsi_bridge_post_disable(struct drm_bridge *bridge) return; } SDE_ATRACE_END("dsi_bridge_post_disable"); + + msm_drm_notifier_call_chain(MSM_DRM_EVENT_BLANK, ¬ify_data); } static void dsi_bridge_mode_set(struct drm_bridge *bridge, From c13076bcf7ab732cc6d7f17fdb0603975542879c Mon Sep 17 00:00:00 2001 From: Pig Date: Fri, 14 Aug 2020 20:06:43 +0800 Subject: [PATCH 027/226] drivers: gpu: drm: msm: Export FOD_PRESSED_LAYER_ZORDER to uapi Change-Id: I5b25d19fab3a2901948d639c785165e70786f4ab Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_plane.c | 4 ++-- include/uapi/drm/sde_drm.h | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 5fe08e3afe29..285ebf05394b 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -4868,8 +4868,8 @@ static int sde_plane_atomic_set_property(struct drm_plane *plane, idx = msm_property_index(&psde->property_info, property); if (idx == PLANE_PROP_ZPOS) { - if (val & 0x20000000u) { - val &= ~0x20000000u; + if (val & FOD_PRESSED_LAYER_ZORDER) { + val &= ~FOD_PRESSED_LAYER_ZORDER; fod_val = 1; } diff --git a/include/uapi/drm/sde_drm.h b/include/uapi/drm/sde_drm.h index d241a307f4ec..7676aaed21dc 100644 --- a/include/uapi/drm/sde_drm.h +++ b/include/uapi/drm/sde_drm.h @@ -495,4 +495,9 @@ struct sde_drm_roi_misr_v1 { #define SDE_RECOVERY_CAPTURE 1 #define SDE_RECOVERY_HARD_RESET 2 +/** + * sde fod dim layer + */ +#define FOD_PRESSED_LAYER_ZORDER 0x20000000u + #endif /* _SDE_DRM_H_ */ From 5565d2feaaed840e1c45c57b14d41588b30b509d Mon Sep 17 00:00:00 2001 From: GuaiYiHu Date: Thu, 13 Aug 2020 12:25:09 +0800 Subject: [PATCH 028/226] drivers: gpu: drm: msm: sde: Increase sde stage to map zpos changes * Another stage should be added, otherwise fingerprint payment won't work in some apps like Alipay and Jingdong. Change-Id: Ibbd928b6d75c17f9c6c2e8b6f72b2d17aa48eb94 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_hw_mdss.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h index bd3ef45df834..fbbec709a569 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h @@ -174,6 +174,7 @@ enum sde_stage { SDE_STAGE_8, SDE_STAGE_9, SDE_STAGE_10, + SDE_STAGE_11, SDE_STAGE_MAX }; enum sde_dspp { From a8e372c0d914fd136fe0a5d457a7e57512996b3a Mon Sep 17 00:00:00 2001 From: Demon000 Date: Tue, 18 Feb 2020 23:00:01 +0200 Subject: [PATCH 029/226] arch: arm64: boot: dts: qcom: ea8076: move fod hbm commands to their proper place Change-Id: Ia8a6cd27fbf63aeadbe2577cfb56b9d56fe0687c Signed-off-by: firebird11 --- .../dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi | 45 ++++++++++--------- ...dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi | 45 ++++++++++--------- ...i-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi | 45 ++++++++++--------- ...dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi | 45 ++++++++++--------- .../dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi | 45 ++++++++++--------- .../display/dsi-panel-ss-fhd-ea8076-cmd.dtsi | 45 ++++++++++--------- .../dsi-panel-ss-fhd-ea8076-global-cmd.dtsi | 45 ++++++++++--------- 7 files changed, 161 insertions(+), 154 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi index 3c1462365a3c..36343965a01f 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi @@ -72,28 +72,6 @@ qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; qcom,mdss-dsi-display-timings { timing@0{ @@ -248,6 +226,29 @@ 39 01 00 00 01 00 03 F0 A5 A5]; qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi index 42c7ecc8ea2b..76e9564aa8a9 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi @@ -72,28 +72,6 @@ qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; qcom,mdss-dsi-display-timings { timing@0{ @@ -248,6 +226,29 @@ 39 01 00 00 01 00 03 F0 A5 A5]; qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi index 437185f1b1a1..04444e5ac51c 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi @@ -72,28 +72,6 @@ qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; qcom,mdss-dsi-display-timings { timing@0{ @@ -248,6 +226,29 @@ 39 01 00 00 01 00 03 F0 A5 A5]; qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi index 15821d208877..76e961997e9f 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi @@ -72,28 +72,6 @@ qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; qcom,mdss-dsi-display-timings { timing@0{ @@ -248,6 +226,29 @@ 39 01 00 00 01 00 03 F0 A5 A5]; qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi index c8b8191aaccb..d01da4830701 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi @@ -72,28 +72,6 @@ qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; /* WHITE POINT COMMAND */ qcom,mdss-dsi-panel-white-point-read-length = <8>; @@ -271,6 +249,29 @@ ]; qcom,mdss-dsi-dispparam-flat-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi index 45b9d84193d4..582642725c12 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi @@ -73,28 +73,6 @@ qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; qcom,mdss-dsi-display-timings { timing@0{ @@ -236,6 +214,29 @@ 39 01 00 00 01 00 03 F0 A5 A5]; qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi index ffcca35361db..4f66145f9f4c 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi @@ -73,28 +73,6 @@ qcom,mdss-dsi-dispparam-elvss-dimming-offset-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-elvss-dimming-read-command = [06 01 00 01 00 00 01 B7]; qcom,mdss-dsi-dispparam-elvss-dimming-read-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; qcom,mdss-dsi-display-timings { timing@0{ @@ -236,6 +214,29 @@ 39 01 00 00 01 00 03 F0 A5 A5]; qcom,mdss-dsi-dispparam-elvss-dimming-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ + 39 01 00 00 00 00 02 53 20 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 4B + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 49 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 03 + 39 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 02 B0 07 + 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 01 00 02 53 E0 + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 B7 01 43 + 39 01 00 00 01 00 03 F0 A5 A5]; + qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; }; From c581571d6eb0b75e8c90f3d9915366bb62d1d166 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Tue, 18 Feb 2020 23:03:10 +0200 Subject: [PATCH 030/226] arch: arm64: boot: dts: qcom: ea8076: disable dc dimming during fod hbm commands Change-Id: If7d461b5f0a02118c5307b962a507269e1fdce71 Signed-off-by: firebird11 --- .../common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi | 2 +- .../common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi | 2 +- .../display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi | 2 +- .../common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi | 2 +- .../common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi | 4 ++-- .../overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi | 2 +- .../common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi index 36343965a01f..b0b7d5341540 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi @@ -242,7 +242,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 00 00 00 00 00 03 F0 A5 A5 39 01 00 00 01 00 02 53 E0 39 00 00 00 00 00 03 F0 5A 5A diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi index 76e9564aa8a9..75bf0dd6e661 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi @@ -242,7 +242,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 00 00 00 00 00 03 F0 A5 A5 39 01 00 00 01 00 02 53 E0 39 00 00 00 00 00 03 F0 5A 5A diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi index 04444e5ac51c..9110a4e77e8c 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi @@ -242,7 +242,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 00 00 00 00 00 03 F0 A5 A5 39 01 00 00 01 00 02 53 E0 39 00 00 00 00 00 03 F0 5A 5A diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi index 76e961997e9f..47082c5b33ab 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi @@ -242,7 +242,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 00 00 00 00 00 03 F0 A5 A5 39 01 00 00 01 00 02 53 E0 39 00 00 00 00 00 03 F0 5A 5A diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi index d01da4830701..1ece198956d7 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi @@ -257,7 +257,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 49 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 01 00 00 01 00 03 F0 A5 A5]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ @@ -265,7 +265,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 00 00 00 00 00 03 F0 A5 A5 39 01 00 00 01 00 02 53 E0 39 00 00 00 00 00 03 F0 5A 5A diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi index 582642725c12..fc1deae7f851 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi @@ -230,7 +230,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 00 00 00 00 00 03 F0 A5 A5 39 01 00 00 01 00 02 53 E0 39 00 00 00 00 00 03 F0 5A 5A diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi index 4f66145f9f4c..1c0e690d7696 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi @@ -230,7 +230,7 @@ 39 00 00 00 00 00 02 B0 03 39 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 + 39 00 00 00 00 00 02 B7 11 39 00 00 00 00 00 03 F0 A5 A5 39 01 00 00 01 00 02 53 E0 39 00 00 00 00 00 03 F0 5A 5A From ec6072e824ee7e6da94b2eceeb93a7d67bcb6d07 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Mon, 25 May 2020 13:11:09 +0200 Subject: [PATCH 031/226] arch: arm64: boot: dts: qcom: ea8076: define fod dim lut Change-Id: I760efba8aedc2bd52a77ca6b2c076cfdf23e11b2 Signed-off-by: firebird11 --- .../dsi-panel-samsung-fhd-ea8076-cmd.dtsi | 25 +++++++++++++++++++ .../dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi | 24 ++++++++++++++++++ ...dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi | 24 ++++++++++++++++++ ...i-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi | 24 ++++++++++++++++++ ...dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi | 24 ++++++++++++++++++ .../dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi | 24 ++++++++++++++++++ .../display/dsi-panel-ss-fhd-ea8076-cmd.dtsi | 24 ++++++++++++++++++ .../dsi-panel-ss-fhd-ea8076-global-cmd.dtsi | 24 ++++++++++++++++++ 8 files changed, 193 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi index db08ebcd43f0..6978a2fdcc1f 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi @@ -61,6 +61,31 @@ qcom,dispparam-enabled; qcom,mdss-panel-on-dimming-delay = <120>; qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; + /* IRQF_ONESHOT | IRQF_TRIGGER_FALLING */ qcom,esd-err-irq-gpio = <&tlmm 27 0x2002>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi index b0b7d5341540..e587d934028b 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi @@ -65,6 +65,30 @@ qcom,disp-doze-backlight-threshold = <8>; qcom,disp-fod-off-dimming-delay = <85>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; qcom,elvss_dimming_check_enable; qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi index 75bf0dd6e661..db0ab4a29c63 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi @@ -65,6 +65,30 @@ qcom,disp-doze-backlight-threshold = <8>; qcom,disp-fod-off-dimming-delay = <85>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; qcom,elvss_dimming_check_enable; qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi index 9110a4e77e8c..c2cc615f2764 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi @@ -65,6 +65,30 @@ qcom,disp-doze-backlight-threshold = <8>; qcom,disp-fod-off-dimming-delay = <85>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; qcom,elvss_dimming_check_enable; qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi index 47082c5b33ab..715f89abad99 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi @@ -65,6 +65,30 @@ qcom,disp-doze-backlight-threshold = <8>; qcom,disp-fod-off-dimming-delay = <85>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; qcom,elvss_dimming_check_enable; qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi index 1ece198956d7..2bcc28432799 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi @@ -65,6 +65,30 @@ qcom,esd-err-irq-gpio = <&tlmm 5 0x2002>; qcom,disp-doze-backlight-threshold = <8>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; qcom,elvss_dimming_check_enable; qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi index fc1deae7f851..cd4a9eacc79f 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi @@ -66,6 +66,30 @@ qcom,disp-doze-backlight-threshold = <8>; qcom,disp-fod-off-dimming-delay = <85>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; qcom,elvss_dimming_check_enable; qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi index 1c0e690d7696..d937de2f65d2 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi @@ -66,6 +66,30 @@ qcom,disp-doze-backlight-threshold = <8>; qcom,disp-fod-off-dimming-delay = <85>; + qcom,disp-fod-dim-lut = < + /* brightness, alpha */ + 0 0xFF + 4 0xEB + 8 0xEA + 12 0xE9 + 13 0xE8 + 20 0xE5 + 24 0xE3 + 30 0xE0 + 68 0xD0 + 133 0xC0 + 218 0xB0 + 328 0xA0 + 486 0x90 + 642 0x80 + 832 0x70 + 1043 0x60 + 1267 0x50 + 1500 0x40 + 1770 0x30 + 2000 0x24 + 2047 0x21 + >; qcom,elvss_dimming_check_enable; qcom,mdss-dsi-panel-elvss-dimming-read-length = <1>; From 62cb49dd30b4de3ab5bbf7a7422b148061634c06 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Tue, 26 May 2020 13:01:43 +0200 Subject: [PATCH 032/226] arch: arm64: boot: dts: qcom: ea8076: optimize HBM commands for in-kernel dimming * remove commands not necessary * use short writes where possible * add waits to compensate for the time it takes for the display to react Change-Id: I85aced1022a544c5386f87fcf97fcb97aac1c129 Signed-off-by: firebird11 --- .../dsi-panel-samsung-fhd-ea8076-cmd.dtsi | 22 ++++++------------- .../dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi | 20 ++++------------- ...dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi | 20 ++++------------- ...i-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi | 20 ++++------------- ...dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi | 20 ++++------------- .../dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi | 20 ++++------------- .../display/dsi-panel-ss-fhd-ea8076-cmd.dtsi | 20 ++++------------- .../dsi-panel-ss-fhd-ea8076-global-cmd.dtsi | 20 ++++------------- 8 files changed, 35 insertions(+), 127 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi index 6978a2fdcc1f..2ac5ce46c238 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-cmd.dtsi @@ -199,22 +199,14 @@ qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 01 00 00 01 00 03 F0 A5 A5]; - qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_lp_mode"; + 15 01 00 00 10 00 02 53 20]; + qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 01 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 + 39 00 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-hbm-fod2norm-command = [39 00 00 00 00 00 03 F0 5A 5A 39 00 00 00 00 00 03 B2 00 40 diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi index e587d934028b..894fb94ffdf7 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1-cmd.dtsi @@ -252,26 +252,14 @@ qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 20]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi index db0ab4a29c63..297b26708ef9 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1mp-cmd.dtsi @@ -252,26 +252,14 @@ qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 20]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi index c2cc615f2764..b9a0a4d5877b 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-2-cmd.dtsi @@ -252,26 +252,14 @@ qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 20]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi index 715f89abad99..e607bdc1e905 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1p2-cmd.dtsi @@ -252,26 +252,14 @@ qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 20]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi index 2bcc28432799..64f128a19cd0 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-samsung-fhd-ea8076-f1s-cmd.dtsi @@ -275,26 +275,14 @@ qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 20]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi index cd4a9eacc79f..2530a8ddf8af 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-cmd.dtsi @@ -240,26 +240,14 @@ qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 20]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi index d937de2f65d2..67830a12f0c4 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-ss-fhd-ea8076-global-cmd.dtsi @@ -240,26 +240,14 @@ qcom,mdss-dsi-h-sync-pulse = <0>; qcom,mdss-dsi-dispparam-hbm-fod-off-command = [ - 39 01 00 00 00 00 02 53 20 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 4B - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 49 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 91 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 20]; qcom,mdss-dsi-dispparam-hbm-fod-off-command-state = "dsi_hs_mode"; qcom,mdss-dsi-dispparam-hbm-fod-on-command = [ 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 03 - 39 00 00 00 00 00 02 B7 C9 - 39 00 00 00 00 00 02 B0 07 - 39 00 00 00 00 00 02 B7 11 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B7 C9 39 00 00 00 00 00 03 F0 A5 A5 - 39 01 00 00 01 00 02 53 E0 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 03 B7 01 43 - 39 01 00 00 01 00 03 F0 A5 A5]; + 15 01 00 00 10 00 02 53 E0]; qcom,mdss-dsi-dispparam-hbm-fod-on-command-state = "dsi_hs_mode"; }; }; From 51e78f94bf95ec8ac0fbe102a2947d1a8ae0588d Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 16 Apr 2024 01:45:41 +0200 Subject: [PATCH 033/226] drivers: gpu: drm: msm: Add R_EARLY_EVENT_BLANK notification Change-Id: I229a619f169dec96834ba3412e853f8bdc03b7fa Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_drm.c | 8 ++++++++ include/linux/msm_drm_notify.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c index 6a1f452dcb0a..967c48af01df 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c @@ -276,11 +276,19 @@ static void dsi_bridge_disable(struct drm_bridge *bridge) struct dsi_display *display; struct dsi_bridge *c_bridge = to_dsi_bridge(bridge); int private_flags; + struct msm_drm_notifier notify_data; + int power_mode; if (!bridge) { pr_err("Invalid params\n"); return; } + + power_mode = sde_connector_get_lp(c_bridge->display->drm_conn); + notify_data.data = &power_mode; + notify_data.id = MSM_DRM_PRIMARY_DISPLAY; + msm_drm_notifier_call_chain(MSM_DRM_R_EARLY_EVENT_BLANK, ¬ify_data); + display = c_bridge->display; private_flags = diff --git a/include/linux/msm_drm_notify.h b/include/linux/msm_drm_notify.h index 4f9b32662ad5..ab04119ed504 100644 --- a/include/linux/msm_drm_notify.h +++ b/include/linux/msm_drm_notify.h @@ -19,6 +19,8 @@ #define MSM_DRM_EVENT_BLANK 0x01 /* A hardware display blank early change occurred */ #define MSM_DRM_EARLY_EVENT_BLANK 0x02 +/* A hardware display blank early change occurred */ +#define MSM_DRM_R_EARLY_EVENT_BLANK 0x03 enum { /* panel: power on */ From 7510ad3aee7494a4a3f0c68ecdc125ce542b318a Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 24 Apr 2024 19:09:51 +0200 Subject: [PATCH 034/226] drivers: gpu: drm: msm: Add cphy_strength support Change-Id: Ifaf8d2b874f2a7e8399f2b450a1003049e32f5eb Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_defs.h | 1 + drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 2 ++ drivers/gpu/drm/msm/dsi-staging/dsi_phy.c | 1 + drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h | 1 + drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c | 8 ++++++++ 5 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index c1817b9612f8..a5b502ef3cf5 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -509,6 +509,7 @@ struct dsi_host_common_cfg { bool force_hs_clk_lane; enum dsi_phy_type phy_type; struct dsi_split_link_config split_link; + bool cphy_strength; }; /** diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 896be2ff23b0..5f8f0db6a0d0 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -1278,6 +1278,8 @@ static int dsi_panel_parse_misc_host_config(struct dsi_host_common_cfg *host, "qcom,panel-cphy-mode"); host->phy_type = panel_cphy_mode ? DSI_PHY_TYPE_CPHY : DSI_PHY_TYPE_DPHY; + host->cphy_strength = utils->read_bool(utils->data, + "qcom,mdss-dsi-cphy-strength"); return 0; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c index 7444b27c9805..c49c327d61df 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c @@ -925,6 +925,7 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, phy->dst_format = config->common_config.dst_format; phy->cfg.pll_source = pll_source; phy->cfg.bit_clk_rate_hz = config->bit_clk_rate_hz; + phy->cfg.cphy_strength = config->common_config.cphy_strength; /** * If PHY timing parameters are not present in panel dtsi file, diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h index e1353631361e..ef9876e780ba 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h @@ -111,6 +111,7 @@ struct dsi_phy_cfg { bool force_clk_lane_hs; enum dsi_phy_type phy_type; unsigned long bit_clk_rate_hz; + bool cphy_strength; }; struct dsi_phy_hw; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c index f9abd95ce73a..e5339f9c1d0a 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c @@ -188,6 +188,14 @@ static void dsi_phy_hw_cphy_enable(struct dsi_phy_hw *phy, DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL, 0x3c); DSI_W32(phy, DSIPHY_CMN_GLBL_LPTX_STR_CTRL, 0x55); + if (cfg->cphy_strength) { + DSI_W32(phy, DSIPHY_CMN_VREG_CTRL_0, 0x50); + DSI_W32(phy, DSIPHY_CMN_VREG_CTRL_1, 0x54); + DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL, 0x1F); + DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL, 0x1F); + DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL, 0x1F); + } + /* Remove power down from all blocks */ DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x7f); From 7cbea5efc8838c88074f08f22fa05b85995e334b Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 24 Apr 2024 21:30:29 +0200 Subject: [PATCH 035/226] drivers: gpu: drm: msm: Add CPHY ESD check command support Change-Id: I48691ad19b5376d3fbcf8cb64e2d05bcd3fb9606 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_defs.h | 1 + drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 50 +++++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 5 +++ 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index a5b502ef3cf5..7e2369ef3776 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -310,6 +310,7 @@ enum dsi_cmd_set_type { DSI_CMD_SET_QSYNC_OFF, DSI_CMD_SET_DISP_HBM_FOD_ON, DSI_CMD_SET_DISP_HBM_FOD_OFF, + DSI_CMD_SET_ESD_CHECK, DSI_CMD_SET_MAX }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 5f8f0db6a0d0..26bca47e7978 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -23,6 +23,7 @@ #include "dsi_panel.h" #include "dsi_ctrl_hw.h" #include "dsi_parser.h" +#include "dsi_display.h" /** * topology is currently defined by a set of following 3 values: @@ -741,10 +742,30 @@ int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status) return rc; } +int dsi_panel_set_esd_check(struct dsi_panel *panel) { + int rc = 0; + + if (!panel->cphy_esd_check) + return 0; + + if (!panel->panel_initialized) { + pr_debug("[%s] panel not initialized\n", panel->name); + return 0; + } + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_ESD_CHECK); + if (rc) + pr_err("[%s] failed to send DSI_CMD_SET_ESD_CHECK cmd, rc=%d\n", + panel->name, rc); + + return rc; +} + int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) { int rc = 0; struct dsi_backlight_config *bl = &panel->bl_config; + u32 last_backlight = dsi_panel_get_backlight(panel); if (panel->host_config.ext_bridge_num) return 0; @@ -767,6 +788,10 @@ int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) rc = -ENOTSUPP; } + if (last_backlight == 0 && panel->cphy_esd_check) { + schedule_delayed_work(&panel->esd_work, msecs_to_jiffies(300)); + } + return rc; } @@ -1813,6 +1838,7 @@ const char *cmd_set_prop_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-qsync-off-commands", "qcom,mdss-dsi-dispparam-hbm-fod-on-command", "qcom,mdss-dsi-dispparam-hbm-fod-off-command", + "qcom,mdss-dsi-esd-check-read-command", }; const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { @@ -1841,6 +1867,7 @@ const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-qsync-off-commands-state", "qcom,mdss-dsi-dispparam-hbm-fod-on-command-state", "qcom,mdss-dsi-dispparam-hbm-fod-off-command-state", + "qcom,mdss-dsi-esd-check-read-command-state", }; static int dsi_panel_get_cmd_pkt_count(const char *data, u32 length, u32 *cnt) @@ -2137,6 +2164,10 @@ static int dsi_panel_parse_misc_features(struct dsi_panel *panel) panel->lp11_init = utils->read_bool(utils->data, "qcom,mdss-dsi-lp11-init"); + + panel->cphy_esd_check = utils->read_bool(utils->data, + "qcom,cphy-esd-check"); + return 0; } @@ -3406,6 +3437,23 @@ static void dsi_panel_update_util(struct dsi_panel *panel, utils->node = panel->panel_of_node; } +static void dsi_panel_esd_enable_delayed_work(struct work_struct *work) +{ + struct dsi_panel *panel = container_of(work, + struct dsi_panel, esd_work.work); + struct dsi_display *display = NULL; + struct mipi_dsi_host *host = panel->host; + + if (host) + display = container_of(host, struct dsi_display, host); + + if (display) { + mutex_lock(&panel->panel_lock); + dsi_panel_set_esd_check(panel); + mutex_unlock(&panel->panel_lock); + } +} + struct dsi_panel *dsi_panel_get(struct device *parent, struct device_node *of_node, struct device_node *parser_node, @@ -3516,6 +3564,8 @@ struct dsi_panel *dsi_panel_get(struct device *parent, if (rc) pr_debug("failed to parse esd config, rc=%d\n", rc); + INIT_DELAYED_WORK(&panel->esd_work, dsi_panel_esd_enable_delayed_work); + panel->power_mode = SDE_MODE_DPMS_OFF; drm_panel_init(&panel->drm_panel); mutex_init(&panel->panel_lock); diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index d36d69006282..8f852bc31315 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -228,6 +228,9 @@ struct dsi_panel { struct brightness_alpha_pair *fod_dim_lut; u32 fod_dim_lut_count; + + bool cphy_esd_check; + struct delayed_work esd_work; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -352,4 +355,6 @@ int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status); u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel); +int dsi_panel_set_esd_check(struct dsi_panel *panel); + #endif /* _DSI_PANEL_H_ */ From 025fd03371cd83e19dfd9bcbbab6885d3ffb1551 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 24 Apr 2024 21:31:46 +0200 Subject: [PATCH 036/226] arch: arm64: boot: dts: qcom: xiaomi: Rename CPHY ESD check commands Change-Id: I3f48d2693fa51d91364f26d151301a4ebde504a3 Signed-off-by: firebird11 --- .../common/display/dsi-panel-k82-36-02-0b-video.dtsi | 6 +++--- .../common/display/dsi-panel-k82-42-02-0a-video.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi index 536baccd575a..b289133bdbe0 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi @@ -48,7 +48,7 @@ qcom,cmd-sync-wait-broadcast; qcom,panel-cphy-mode; qcom,mdss-dsi-cphy-strength; - mi,cphy-esd-check; + qcom,cphy-esd-check; mi,is-tddi-flag; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = @@ -339,14 +339,14 @@ qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; - mi,mdss-dsi-esd-check-read-command = [ + qcom,mdss-dsi-esd-check-read-command = [ /* esd detect */ 15 01 00 00 00 00 02 FF 27 15 01 00 00 00 00 02 D1 28 15 01 00 00 00 00 02 FF 10 15 01 00 00 00 00 02 53 2C ]; - mi,mdss-dsi-esd-check-read-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-esd-check-read-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-xy-coordinate-command = [ 15 01 00 00 00 00 02 FF 10 diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi index 22c3e689801b..4b86cc134fec 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi @@ -48,7 +48,7 @@ qcom,cmd-sync-wait-broadcast; qcom,panel-cphy-mode; qcom,mdss-dsi-cphy-strength; - mi,cphy-esd-check; + qcom,cphy-esd-check; mi,is-tddi-flag; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = @@ -354,14 +354,14 @@ qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; - mi,mdss-dsi-esd-check-read-command = [ + qcom,mdss-dsi-esd-check-read-command = [ /* esd detect */ 15 01 00 00 00 00 02 FF 27 15 01 00 00 00 00 02 D1 28 15 01 00 00 00 00 02 FF 10 15 01 00 00 00 00 02 53 2C ]; - mi,mdss-dsi-esd-check-read-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-esd-check-read-command-state = "dsi_lp_mode"; qcom,mdss-dsi-dispparam-xy-coordinate-command = [ 15 01 00 00 00 00 02 FF 10 From e4a4ce2d1762ebbca830ca027696528c347040b1 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 24 Apr 2024 23:51:19 +0200 Subject: [PATCH 037/226] drivers: gpu: drm: msm: Implement pen FPS sync Change-Id: I8ae2f6a201bb00343c6f28a7b0dca493fdc560c8 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_defs.h | 3 + drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 61 +++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 5 ++ drivers/gpu/drm/msm/sde/sde_encoder.c | 65 +++++++++++++++++++++ drivers/gpu/drm/msm/sde/sde_encoder.h | 7 +++ 5 files changed, 141 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index 7e2369ef3776..d93655f8562a 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -311,6 +311,9 @@ enum dsi_cmd_set_type { DSI_CMD_SET_DISP_HBM_FOD_ON, DSI_CMD_SET_DISP_HBM_FOD_OFF, DSI_CMD_SET_ESD_CHECK, + DSI_CMD_SET_SYNC_PEN_30HZ, + DSI_CMD_SET_SYNC_PEN_60HZ, + DSI_CMD_SET_SYNC_PEN_120HZ, DSI_CMD_SET_MAX }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 26bca47e7978..cd69ff775c3e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -761,6 +761,50 @@ int dsi_panel_set_esd_check(struct dsi_panel *panel) { return rc; } +int dsi_panel_sync_pen_fps(struct dsi_panel *panel, + struct dsi_display_mode *adj_mode) +{ + int rc = 0; + u32 refresh_rate; + enum dsi_cmd_set_type sync_pen_cmd_type; + + if (!panel || !adj_mode) { + pr_err("invalid params\n"); + return -EINVAL; + } + + if (!panel->sync_pen_fps) { + pr_warn_once("[%s] sync pen fps called when disabled\n", panel->name); + return 0; + } + + refresh_rate = adj_mode->timing.refresh_rate; + + switch (refresh_rate) { + case 30: + sync_pen_cmd_type = DSI_CMD_SET_SYNC_PEN_30HZ; + break; + case 60: + sync_pen_cmd_type = DSI_CMD_SET_SYNC_PEN_60HZ; + break; + case 120: + sync_pen_cmd_type = DSI_CMD_SET_SYNC_PEN_120HZ; + break; + default: + pr_err("[%s] unsupported refresh rate %d\n", + panel->name, refresh_rate); + return -EINVAL; + break; + } + + rc = dsi_panel_tx_cmd_set(panel, sync_pen_cmd_type); + if (rc) + pr_err("[%s] failed to send DSI_CMD_SET_SYNC_PEN_%dHZ cmd, rc=%d\n", + panel->name, refresh_rate, rc); + + return rc; +} + int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) { int rc = 0; @@ -1839,6 +1883,9 @@ const char *cmd_set_prop_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-dispparam-hbm-fod-on-command", "qcom,mdss-dsi-dispparam-hbm-fod-off-command", "qcom,mdss-dsi-esd-check-read-command", + "qcom,mdss-dsi-sync-pen-30hz-command", + "qcom,mdss-dsi-sync-pen-60hz-command", + "qcom,mdss-dsi-sync-pen-120hz-command", }; const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { @@ -1868,6 +1915,9 @@ const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-dispparam-hbm-fod-on-command-state", "qcom,mdss-dsi-dispparam-hbm-fod-off-command-state", "qcom,mdss-dsi-esd-check-read-command-state", + "qcom,mdss-dsi-sync-pen-30hz-command-state", + "qcom,mdss-dsi-sync-pen-60hz-command-state", + "qcom,mdss-dsi-sync-pen-120hz-command-state", }; static int dsi_panel_get_cmd_pkt_count(const char *data, u32 length, u32 *cnt) @@ -2168,6 +2218,9 @@ static int dsi_panel_parse_misc_features(struct dsi_panel *panel) panel->cphy_esd_check = utils->read_bool(utils->data, "qcom,cphy-esd-check"); + panel->sync_pen_fps = utils->read_bool(utils->data, + "qcom,sync-pen-fps"); + return 0; } @@ -4486,6 +4539,14 @@ int dsi_panel_post_enable(struct dsi_panel *panel) goto error; } error: + if (panel->sync_pen_fps) { + rc = dsi_panel_sync_pen_fps(panel, panel->cur_mode); + if (rc) { + pr_err("[%s] failed to update TP fps code setting, rc=%d\n", + panel->name, rc); + } + } + mutex_unlock(&panel->panel_lock); return rc; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index 8f852bc31315..aa64c4e753b7 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -231,6 +231,8 @@ struct dsi_panel { bool cphy_esd_check; struct delayed_work esd_work; + + bool sync_pen_fps; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -357,4 +359,7 @@ u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel); int dsi_panel_set_esd_check(struct dsi_panel *panel); +int dsi_panel_sync_pen_fps(struct dsi_panel *panel, + struct dsi_display_mode *adj_mode); + #endif /* _DSI_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c index 0b8daa3b9f01..32fe1f7039b8 100644 --- a/drivers/gpu/drm/msm/sde/sde_encoder.c +++ b/drivers/gpu/drm/msm/sde/sde_encoder.c @@ -39,6 +39,7 @@ #include "sde_core_irq.h" #include "sde_hw_top.h" #include "sde_hw_qdss.h" +#include "dsi_drm.h" #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\ (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) @@ -4811,6 +4812,9 @@ void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error) struct sde_encoder_phys *phys; ktime_t wakeup_time; unsigned int i; + struct dsi_bridge *bridge = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_display_mode adj_mode; if (!drm_enc) { SDE_ERROR("invalid encoder\n"); @@ -4825,6 +4829,22 @@ void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error) if (is_error) _sde_encoder_reset_ctl_hw(drm_enc); + if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI + && drm_enc->bridge) + bridge = container_of(drm_enc->bridge, struct dsi_bridge, base); + + if (bridge) { + adj_mode = bridge->dsi_mode; + dsi_display = bridge->display; + + if (dsi_display && dsi_display->panel + && dsi_display->panel->sync_pen_fps + && adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) { + mutex_lock(&dsi_display->panel->panel_lock); + sde_encoder_vid_wait_for_active(drm_enc); + } + } + /* All phys encs are ready to go, trigger the kickoff */ _sde_encoder_kickoff_phys(sde_enc); @@ -4842,6 +4862,13 @@ void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error) nsecs_to_jiffies(ktime_to_ns(wakeup_time))); } + if (dsi_display && dsi_display->panel + && dsi_display->panel->sync_pen_fps + && adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) { + dsi_panel_sync_pen_fps(dsi_display->panel, &adj_mode); + mutex_unlock(&dsi_display->panel->panel_lock); + } + SDE_ATRACE_END("encoder_kickoff"); } @@ -5560,6 +5587,44 @@ struct drm_encoder *sde_encoder_init( return sde_encoder_init_with_ops(dev, disp_info, NULL); } +int sde_encoder_vid_wait_for_active( + struct drm_encoder *drm_enc) +{ + struct drm_display_mode mode; + struct sde_encoder_virt *sde_enc = NULL; + u32 ln_cnt, min_ln_cnt, active_mark_region; + u32 i, retry = 15; + + if (!drm_enc) { + SDE_ERROR("invalid encoder\n"); + return -EINVAL; + } + + sde_enc = to_sde_encoder_virt(drm_enc); + + for (i = 0; i < sde_enc->num_phys_encs; i++) { + struct sde_encoder_phys *phys = sde_enc->phys_encs[i]; + + if (!phys || (phys->ops.is_master && !phys->ops.is_master(phys))) + continue; + + mode = phys->cached_mode; + min_ln_cnt = (mode.vtotal - mode.vsync_start) + + (mode.vsync_end - mode.vsync_start); + active_mark_region = mode.vdisplay + min_ln_cnt - mode.vdisplay / 4; + + while (retry) { + ln_cnt = phys->ops.get_line_count(phys); + if ((ln_cnt > min_ln_cnt) && (ln_cnt < active_mark_region)) + return 0; + + udelay(2000); + retry--; + } + } + return -EINVAL; +} + int sde_encoder_wait_for_event(struct drm_encoder *drm_enc, enum msm_event_wait event) { diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h index eb0415ed5553..5e6c24ca49f0 100644 --- a/drivers/gpu/drm/msm/sde/sde_encoder.h +++ b/drivers/gpu/drm/msm/sde/sde_encoder.h @@ -355,4 +355,11 @@ int sde_encoder_get_ctlstart_timeout_state(struct drm_encoder *enc); */ void sde_encoder_trigger_early_wakeup(struct drm_encoder *drm_enc); +/** + * sde_encoder_vid_wait_for_active - wait Vactive region for some mark region + * @drm_enc: Pointer to drm encoder structure + * @Return: non zero value if wait timeout occurred + */ +int sde_encoder_vid_wait_for_active(struct drm_encoder *enc); + #endif /* __SDE_ENCODER_H__ */ From b6b94465874c10c1eec8c849f8cf25d113322a5f Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Thu, 25 Apr 2024 00:21:12 +0200 Subject: [PATCH 038/226] arch: arm64: boot: dts: qcom: xiaomi: Adapt pen FPS values Change-Id: I4fe06e4fad2c09685acd89c97a5dda99df558def Signed-off-by: firebird11 --- .../common/display/dsi-panel-k82-36-02-0b-video.dtsi | 9 +++++---- .../common/display/dsi-panel-k82-42-02-0a-video.dtsi | 9 +++++---- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi index b289133bdbe0..90b7af7b72e0 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-36-02-0b-video.dtsi @@ -49,6 +49,7 @@ qcom,panel-cphy-mode; qcom,mdss-dsi-cphy-strength; qcom,cphy-esd-check; + qcom,sync-pen-fps; mi,is-tddi-flag; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = @@ -264,16 +265,16 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-pen-120hz-command = [ + qcom,mdss-dsi-sync-pen-120hz-command = [ 15 00 00 00 00 00 02 FF 2A 15 00 00 00 00 00 02 23 0D 15 01 00 00 00 00 02 FF 10]; - qcom,mdss-dsi-dispparam-pen-60hz-command = [ + qcom,mdss-dsi-sync-pen-60hz-command = [ 15 00 00 00 00 00 02 FF 2A 15 00 00 00 00 00 02 23 0C 15 01 00 00 00 00 02 FF 10]; - qcom,mdss-dsi-dispparam-pen-120hz-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-dispparam-pen-60hz-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-sync-pen-120hz-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-sync-pen-60hz-command-state = "dsi_lp_mode"; /* max brightness 85% */ qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [ diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi index 4b86cc134fec..651b814864cf 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/display/dsi-panel-k82-42-02-0a-video.dtsi @@ -49,6 +49,7 @@ qcom,panel-cphy-mode; qcom,mdss-dsi-cphy-strength; qcom,cphy-esd-check; + qcom,sync-pen-fps; mi,is-tddi-flag; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = @@ -279,16 +280,16 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-dispparam-pen-120hz-command = [ + qcom,mdss-dsi-sync-pen-120hz-command = [ 15 00 00 00 00 00 02 FF 2A 15 00 00 00 00 00 02 23 0D 15 01 00 00 00 00 02 FF 10]; - qcom,mdss-dsi-dispparam-pen-60hz-command = [ + qcom,mdss-dsi-sync-pen-60hz-command = [ 15 00 00 00 00 00 02 FF 2A 15 00 00 00 00 00 02 23 0C 15 01 00 00 00 00 02 FF 10]; - qcom,mdss-dsi-dispparam-pen-120hz-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-dispparam-pen-60hz-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-sync-pen-120hz-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-sync-pen-60hz-command-state = "dsi_lp_mode"; /* max brightness 85% */ qcom,mdss-dsi-dispparam-lcd-hbm-l1-on-command = [ From 50a1b4b1f9e38a08685515db50940b5d6ead6017 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Thu, 25 Apr 2024 00:20:39 +0200 Subject: [PATCH 039/226] drivers: gpu: drm: msm: Import Xiaomi changes * From nabu-r-oss Change-Id: Ic797d9c0534114a8298a260a66e7f7ecdc211e37 Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_defs.h | 3 + drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 44 +- drivers/gpu/drm/msm/dsi-staging/dsi_display.h | 13 + drivers/gpu/drm/msm/dsi-staging/dsi_drm.c | 8 + drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 410 ++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 47 ++ .../gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c | 5 + drivers/gpu/drm/msm/sde/sde_connector.c | 83 ++++ 8 files changed, 610 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index d93655f8562a..016be31d2732 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -314,6 +314,9 @@ enum dsi_cmd_set_type { DSI_CMD_SET_SYNC_PEN_30HZ, DSI_CMD_SET_SYNC_PEN_60HZ, DSI_CMD_SET_SYNC_PEN_120HZ, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + DSI_CMD_SET_MI_READ_LOCKDOWN_INFO, +#endif DSI_CMD_SET_MAX }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index d4fc8b2c094c..4db608879026 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -245,7 +245,7 @@ int dsi_display_set_backlight(struct drm_connector *connector, return rc; } -static int dsi_display_cmd_engine_enable(struct dsi_display *display) +int dsi_display_cmd_engine_enable(struct dsi_display *display) { int rc = 0; int i; @@ -289,7 +289,7 @@ static int dsi_display_cmd_engine_enable(struct dsi_display *display) return rc; } -static int dsi_display_cmd_engine_disable(struct dsi_display *display) +int dsi_display_cmd_engine_disable(struct dsi_display *display) { int rc = 0; int i; @@ -475,7 +475,7 @@ static void dsi_display_register_te_irq(struct dsi_display *display) } /* Allocate memory for cmd dma tx buffer */ -static int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display) +int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display) { int rc = 0, cnt = 0; struct dsi_display_ctrl *display_ctrl; @@ -5544,6 +5544,9 @@ int dsi_display_dev_probe(struct platform_device *pdev) display->pdev = pdev; display->boot_disp = boot_disp; display->dsi_type = dsi_type; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + display->is_first_boot = true; +#endif dsi_display_parse_cmdline_topology(display, index); @@ -7585,6 +7588,17 @@ int dsi_display_enable(struct dsi_display *display) display->panel->panel_initialized = true; pr_debug("cont splash enabled, display enable not required\n"); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (display->panel->is_tddi_flag) { + rc = dsi_panel_lockdowninfo_param_read(display->panel); + if (!rc) { + pr_err("[%s] failed to read lockdowninfo para, rc=%d\n", + display->name, rc); + } + } +#endif + return 0; } @@ -7865,6 +7879,30 @@ struct dsi_display *get_main_display(void) { return primary_display; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int dsi_display_esd_irq_ctrl(struct dsi_display *display, + bool enable) +{ + int ret = 0; + + if (!display) { + pr_err("Invalid parameters\n"); + return -EINVAL; + } + + mutex_lock(&display->display_lock); + + ret = dsi_panel_esd_irq_ctrl(display->panel, enable); + if (ret) + pr_err("[%s] failed to set esd irq, rc=%d\n", + display->name, ret); + + mutex_unlock(&display->display_lock); + + return ret; +} +#endif + static int __init dsi_display_register(void) { dsi_phy_drv_register(); diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 73d8b5ac29dd..0331f097321e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -202,6 +202,9 @@ struct dsi_display { struct drm_connector *ext_conn; const char *name; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool is_first_boot; +#endif const char *display_type; const char *dsi_type; struct list_head list; @@ -718,4 +721,14 @@ struct dsi_display *get_main_display(void); void dsi_display_set_fod_ui(struct dsi_display *display, bool status); +int dsi_display_cmd_engine_enable(struct dsi_display *display); + +int dsi_display_cmd_engine_disable(struct dsi_display *display); + +int dsi_host_alloc_cmd_tx_buffer(struct dsi_display *display); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int dsi_display_esd_irq_ctrl(struct dsi_display *display, bool enable); +#endif + #endif /* _DSI_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c index 967c48af01df..a78010ebb908 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c @@ -268,6 +268,10 @@ static void dsi_bridge_enable(struct drm_bridge *bridge) sde_connector_schedule_status_work(display->drm_conn, true); } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + dsi_display_esd_irq_ctrl(display, true); +#endif } static void dsi_bridge_disable(struct drm_bridge *bridge) @@ -291,6 +295,10 @@ static void dsi_bridge_disable(struct drm_bridge *bridge) display = c_bridge->display; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + dsi_display_esd_irq_ctrl(display, false); +#endif + private_flags = bridge->encoder->crtc->state->adjusted_mode.private_flags; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index cd69ff775c3e..450f1ac0a369 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -25,6 +25,10 @@ #include "dsi_parser.h" #include "dsi_display.h" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#include "../../../../../kernel/irq/internals.h" +#endif + /** * topology is currently defined by a set of following 3 values: * 1. num of layer mixers @@ -436,7 +440,20 @@ static int dsi_panel_power_on(struct dsi_panel *panel) { int rc = 0; +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) rc = dsi_pwr_enable_regulator(&panel->power_info, true); +#else + if (panel->is_tddi_flag) { + if (!panel->tddi_doubleclick_flag || panel->panel_dead_flag) { + rc = dsi_pwr_enable_regulator(&panel->power_info, true); + if (panel->panel_dead_flag) + panel->panel_dead_flag = false; + } + } else { + rc = dsi_pwr_enable_regulator(&panel->power_info, true); + } +#endif + if (rc) { pr_err("[%s] failed to enable vregs, rc=%d\n", panel->name, rc); goto exit; @@ -483,8 +500,20 @@ static int dsi_panel_power_off(struct dsi_panel *panel) if (gpio_is_valid(panel->reset_config.disp_en_gpio)) gpio_set_value(panel->reset_config.disp_en_gpio, 0); +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) if (gpio_is_valid(panel->reset_config.reset_gpio)) gpio_set_value(panel->reset_config.reset_gpio, 0); +#else + if (panel->is_tddi_flag) { + if (!panel->tddi_doubleclick_flag || panel->panel_dead_flag) { + if (gpio_is_valid(panel->reset_config.reset_gpio)) + gpio_set_value(panel->reset_config.reset_gpio, 0); + } + } else { + if (gpio_is_valid(panel->reset_config.reset_gpio)) + gpio_set_value(panel->reset_config.reset_gpio, 0); + } +#endif if (gpio_is_valid(panel->reset_config.lcd_mode_sel_gpio)) gpio_set_value(panel->reset_config.lcd_mode_sel_gpio, 0); @@ -495,9 +524,23 @@ static int dsi_panel_power_off(struct dsi_panel *panel) rc); } +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) rc = dsi_pwr_enable_regulator(&panel->power_info, false); if (rc) pr_err("[%s] failed to enable vregs, rc=%d\n", panel->name, rc); +#else + if (panel->is_tddi_flag) { + if(!panel->tddi_doubleclick_flag || panel->panel_dead_flag) { + rc = dsi_pwr_enable_regulator(&panel->power_info, false); + if (rc) + pr_err("[%s] failed to enable vregs, rc=%d\n", panel->name, rc); + } + } else { + rc = dsi_pwr_enable_regulator(&panel->power_info, false); + if (rc) + pr_err("[%s] failed to enable vregs, rc=%d\n", panel->name, rc); + } +#endif return rc; } @@ -805,6 +848,315 @@ int dsi_panel_sync_pen_fps(struct dsi_panel *panel, return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int dsi_panel_esd_irq_ctrl(struct dsi_panel *panel, + bool enable) +{ + struct drm_panel_esd_config *esd_config; + struct irq_desc *desc; + + if (!panel || !panel->panel_initialized) { + pr_err("[LCD] panel not ready!\n"); + return -EINVAL; + } + + mutex_lock(&panel->panel_lock); + + esd_config = &panel->esd_config; + if (gpio_is_valid(esd_config->esd_err_irq_gpio)) { + if (esd_config->esd_err_irq) { + if (enable) { + desc = irq_to_desc(esd_config->esd_err_irq); + if (!irq_settings_is_level(desc)) + desc->istate &= ~IRQS_PENDING; + enable_irq(esd_config->esd_err_irq); + pr_info("panel esd irq is enable\n"); + } else { + disable_irq_nosync(esd_config->esd_err_irq); + pr_info("panel esd irq is disable\n"); + } + } + } + + mutex_unlock(&panel->panel_lock); + return 0; +} + +static int dsi_panel_get_lockdown_from_cmdline(unsigned char *plockdowninfo) +{ + int ret = -1; + char lockdown_str[40] = {'\0'}; + char *match = (char *) strnstr(saved_command_line, + "msm_drm.panel_lockdown=", + strlen(saved_command_line)); + + if (match && plockdowninfo) { + memcpy(lockdown_str, (match + strlen("msm_drm.panel_lockdown=")), + sizeof(lockdown_str) - 1); + if (sscanf(lockdown_str, "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x", + &plockdowninfo[0], &plockdowninfo[1], &plockdowninfo[2], &plockdowninfo[3], + &plockdowninfo[4], &plockdowninfo[5], &plockdowninfo[6], &plockdowninfo[7]) + != 8) { + pr_err("failed to parse lockdown info from cmdline !\n"); + } else { + pr_info("lockdown info from cmdline = 0x%02x,0x%02x,0x%02x,0x%02x,0x%02x," + "0x%02x,0x%02x,0x%02x", + plockdowninfo[0], plockdowninfo[1], plockdowninfo[2], plockdowninfo[3], + plockdowninfo[4], plockdowninfo[5], plockdowninfo[6], plockdowninfo[7]); + ret = 0; + } + } + return ret; +} + +ssize_t dsi_panel_lockdown_info_read(unsigned char *plockdowninfo) +{ + int rc = 0; + int i = 0; + static int count = 0; + struct dsi_display *primary_display = get_main_display(); + + if (!dsi_panel_get_lockdown_from_cmdline(plockdowninfo)) + return 1; + if (!primary_display || !primary_display->panel || !plockdowninfo) { + pr_err("invalid params\n"); + return -EINVAL; + } + + while (!primary_display->panel->lockdowninfo_read.lockdowninfo_read_done && count < MAX_READ_LOCKDOWN_COUNT) { + pr_debug("[%s][%s] waitting for panel priv_info initialized!\n", __func__, primary_display->panel->name); + msleep_interruptible(1000); + count++; + } + for(i = 0; i < 8; i++) { + pr_info("0x%x", primary_display->panel->lockdowninfo_read.lockdowninfo[i]); + plockdowninfo[i] = primary_display->panel->lockdowninfo_read.lockdowninfo[i]; + } + rc = plockdowninfo[0]; + return rc; +} +EXPORT_SYMBOL(dsi_panel_lockdown_info_read); + +int dsi_panel_lockdowninfo_param_read(struct dsi_panel *panel) +{ + int rc = 0; + int i = 0; + struct dsi_panel_cmd_set *cmd_sets; + struct dsi_read_config ld_read_config; + struct dsi_panel_cmd_set read_cmd_set = {0}; + if (!panel || !panel->cur_mode || !panel->cur_mode->priv_info) { + pr_err("invalid params\n"); + return -EINVAL; + } + + if (!panel->panel_initialized) { + pr_err("panel not initialized\n"); + return -EINVAL; + } + + cmd_sets = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_MI_READ_LOCKDOWN_INFO]; + if (cmd_sets->cmds) { + read_cmd_set.cmds = cmd_sets->cmds; + read_cmd_set.count = 1; + read_cmd_set.state = cmd_sets->state; + rc = dsi_panel_write_cmd_set(panel, &read_cmd_set); + if (rc) { + pr_err("[%s] failed to send cmds, rc=%d\n",panel->name, rc); + rc = -EIO; + } + pr_info("[%s]", panel->name); + if (strcmp(panel->name,"xiaomi 42 02 0a video mode dual dsi cphy panel") && + strcmp(panel->name,"xiaomi 36 02 0b video mode dual dsi cphy panel")) { + ld_read_config.enabled= 1; + ld_read_config.cmds_rlen = 8; + ld_read_config.read_cmd = read_cmd_set; + ld_read_config.read_cmd.cmds = &read_cmd_set.cmds[1]; + rc = dsi_panel_read_cmd_set(panel, &ld_read_config); + if (rc <= 0) { + pr_err("[%s] failed to read cmds, rc=%d\n", panel->name, rc); + rc = -EIO; + } + for(i = 0; i < 8; i++) { + pr_info("0x%x", ld_read_config.rbuf[i]); + panel->lockdowninfo_read.lockdowninfo[i] = ld_read_config.rbuf[i]; + } + + if (!strcmp(panel->name,"xiaomi 37 02 0b video mode dsc dsi panel")) { + panel->lockdowninfo_read.lockdowninfo[7] = 0x01; + pr_info("plockdowninfo[7] = 0x%d \n", + panel->lockdowninfo_read.lockdowninfo[7]); + } + panel->lockdowninfo_read.lockdowninfo_read_done = 1; + } else { + for(i = 0; i < 8; i++) { + ld_read_config.enabled= 1; + ld_read_config.cmds_rlen = 1; + ld_read_config.read_cmd = read_cmd_set; + ld_read_config.read_cmd.cmds = &read_cmd_set.cmds[i+1]; + rc = dsi_panel_read_cmd_set(panel, &ld_read_config); + if (rc <= 0) { + pr_err("[%s] failed to read, rc=%d\n", panel->name, rc); + rc = -EIO; + } + + pr_info("0x%x", ld_read_config.rbuf[0]); + panel->lockdowninfo_read.lockdowninfo[i] = ld_read_config.rbuf[0]; + } + panel->lockdowninfo_read.lockdowninfo_read_done = 1; + } + } + + return rc; + +} + +int dsi_panel_write_cmd_set(struct dsi_panel *panel, + struct dsi_panel_cmd_set *cmd_sets) +{ + int rc = 0, i = 0; + ssize_t len; + struct dsi_cmd_desc *cmds; + u32 count; + enum dsi_cmd_set_state state; + struct dsi_display_mode *mode; + const struct mipi_dsi_host_ops *ops = panel->host->ops; + + if (!panel || !panel->cur_mode) + return -EINVAL; + + mode = panel->cur_mode; + + cmds = cmd_sets->cmds; + count = cmd_sets->count; + state = cmd_sets->state; + + if (count == 0) { + pr_debug("[%s] No commands to be sent for state\n", panel->name); + goto error; + } + + for (i = 0; i < count; i++) { + if (state == DSI_CMD_SET_STATE_LP) + cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM; + + if (cmds->last_command) + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + + len = ops->transfer(panel->host, &cmds->msg); + if (len < 0) { + rc = len; + pr_err("failed to set cmds, rc=%d\n", rc); + goto error; + } + if (cmds->post_wait_ms) + usleep_range(cmds->post_wait_ms*1000, + ((cmds->post_wait_ms*1000)+10)); + cmds++; + } +error: + return rc; +} + +int dsi_panel_read_cmd_set(struct dsi_panel *panel, + struct dsi_read_config *read_config) +{ + struct mipi_dsi_host *host; + struct dsi_display *display; + struct dsi_display_ctrl *ctrl; + struct dsi_cmd_desc *cmds; + enum dsi_cmd_set_state state; + int i, rc = 0, count = 0; + u32 flags = 0; + + if (panel == NULL || read_config == NULL) + return -EINVAL; + + host = panel->host; + if (host) { + display = container_of(host, struct dsi_display, host); + if (display == NULL) + return -EINVAL; + } else + return -EINVAL; + + if (!panel->panel_initialized) { + pr_info("Panel not initialized\n"); + return -EINVAL; + } + + if (!read_config->enabled) { + pr_info("read operation was not permitted\n"); + return -EPERM; + } + + dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + + ctrl = &display->ctrl[display->cmd_master_idx]; + + rc = dsi_display_cmd_engine_enable(display); + if (rc) { + pr_err("cmd engine enable failed\n"); + rc = -EPERM; + goto exit_ctrl; + } + + if (display->tx_cmd_buf == NULL) { + rc = dsi_host_alloc_cmd_tx_buffer(display); + if (rc) { + pr_err("failed to allocate cmd tx buffer memory\n"); + goto exit; + } + } + + count = read_config->read_cmd.count; + cmds = read_config->read_cmd.cmds; + state = read_config->read_cmd.state; + if (count == 0) { + pr_err("No commands to be sent\n"); + goto exit; + } + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + if (state == DSI_CMD_SET_STATE_LP) + cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM; + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ | + DSI_CTRL_CMD_CUSTOM_DMA_SCHED); + + memset(read_config->rbuf, 0x0, sizeof(read_config->rbuf)); + cmds->msg.rx_buf = read_config->rbuf; + cmds->msg.rx_len = read_config->cmds_rlen; + + rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &(cmds->msg), flags); + if (rc <= 0) { + pr_err("rx cmd transfer failed rc=%d\n", rc); + goto exit; + } + + for (i = 0; i < read_config->cmds_rlen; i++) //debug + pr_info("0x%x ", read_config->rbuf[i]); + pr_info("\n"); + +exit: + dsi_display_cmd_engine_disable(display); +exit_ctrl: + dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + + return rc; +} + +void dsi_panel_doubleclick_enable(bool on) +{ + struct dsi_display *primary_display = get_main_display(); + if (primary_display && primary_display->panel) + primary_display->panel->tddi_doubleclick_flag = on; +} +EXPORT_SYMBOL(dsi_panel_doubleclick_enable); +#endif + int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) { int rc = 0; @@ -1886,6 +2238,9 @@ const char *cmd_set_prop_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-sync-pen-30hz-command", "qcom,mdss-dsi-sync-pen-60hz-command", "qcom,mdss-dsi-sync-pen-120hz-command", +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + "mi,mdss-dsi-read-lockdown-info-command", +#endif }; const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { @@ -1918,6 +2273,9 @@ const char *cmd_set_state_map[DSI_CMD_SET_MAX] = { "qcom,mdss-dsi-sync-pen-30hz-command-state", "qcom,mdss-dsi-sync-pen-60hz-command-state", "qcom,mdss-dsi-sync-pen-120hz-command-state", +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + "mi,mdss-dsi-read-lockdown-info-command-state", +#endif }; static int dsi_panel_get_cmd_pkt_count(const char *data, u32 length, u32 *cnt) @@ -3415,6 +3773,27 @@ static int dsi_panel_parse_esd_config(struct dsi_panel *panel) esd_config = &panel->esd_config; esd_config->status_mode = ESD_MODE_MAX; + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* esd-err-flag method will be prefered */ + esd_config->esd_err_irq_gpio = of_get_named_gpio_flags( + panel->panel_of_node, + "qcom,esd-err-irq-gpio", + 0, + (enum of_gpio_flags *)&(esd_config->esd_err_irq_flags)); + if (gpio_is_valid(esd_config->esd_err_irq_gpio)) { + esd_config->esd_err_irq = gpio_to_irq(esd_config->esd_err_irq_gpio); + rc = gpio_request(esd_config->esd_err_irq_gpio, "esd_err_irq_gpio"); + if (rc) + pr_err("%s: Failed to get esd irq gpio %d (code: %d)", + __func__, esd_config->esd_err_irq_gpio, rc); + else + gpio_direction_input(esd_config->esd_err_irq_gpio); + + return 0; + } +#endif + esd_config->esd_enabled = utils->read_bool(utils->data, "qcom,esd-check-enabled"); @@ -3490,6 +3869,28 @@ static void dsi_panel_update_util(struct dsi_panel *panel, utils->node = panel->panel_of_node; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int dsi_panel_parse_mi_config(struct dsi_panel *panel, + struct device_node *of_node) +{ + int rc = 0; + struct dsi_parser_utils *utils; + + if (panel == NULL) + return -EINVAL; + + utils = &panel->utils; + + panel->is_tddi_flag = utils->read_bool(of_node, + "mi,is-tddi-flag"); + + panel->panel_dead_flag = false; + panel->tddi_doubleclick_flag = false; + + return rc; +} +#endif + static void dsi_panel_esd_enable_delayed_work(struct work_struct *work) { struct dsi_panel *panel = container_of(work, @@ -3617,6 +4018,12 @@ struct dsi_panel *dsi_panel_get(struct device *parent, if (rc) pr_debug("failed to parse esd config, rc=%d\n", rc); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = dsi_panel_parse_mi_config(panel, of_node); + if (rc) + pr_err("failed to parse mi config, rc=%d\n", rc); +#endif + INIT_DELAYED_WORK(&panel->esd_work, dsi_panel_esd_enable_delayed_work); panel->power_mode = SDE_MODE_DPMS_OFF; @@ -4587,6 +4994,9 @@ int dsi_panel_disable(struct dsi_panel *panel) /* Avoid sending panel off commands when ESD recovery is underway */ if (!atomic_read(&panel->esd_recovery_pending)) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + panel->panel_initialized = false; +#endif /* * Need to set IBB/AB regulator mode to STANDBY, * if panel is going off from AOD mode. diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index aa64c4e753b7..b8e0aa5b2b0e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -37,6 +37,11 @@ #define DSI_MODE_MAX 5 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define BUF_LEN_MAX 256 +#define MAX_READ_LOCKDOWN_COUNT 200 +#endif + enum dsi_panel_rotation { DSI_PANEL_ROTATE_NONE = 0, DSI_PANEL_ROTATE_HV_FLIP, @@ -167,6 +172,11 @@ struct drm_panel_esd_config { u8 *return_buf; u8 *status_buf; u32 groups; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int esd_err_irq_gpio; + int esd_err_irq; + int esd_err_irq_flags; +#endif }; #define BRIGHTNESS_ALPHA_PAIR_LEN 2 @@ -175,6 +185,21 @@ struct brightness_alpha_pair { u32 alpha; }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +struct lockdowninfo_cfg { + u8 lockdowninfo[16]; + bool lockdowninfo_read_done; +}; + +struct dsi_read_config { + bool enabled; + struct dsi_panel_cmd_set read_cmd; + u32 cmds_rlen; + u32 valid_bits; + u8 rbuf[BUF_LEN_MAX]; +}; +#endif + struct dsi_panel { const char *name; const char *type; @@ -233,6 +258,14 @@ struct dsi_panel { struct delayed_work esd_work; bool sync_pen_fps; + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool is_tddi_flag; + bool tddi_doubleclick_flag; + bool panel_dead_flag; + + struct lockdowninfo_cfg lockdowninfo_read; +#endif }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -362,4 +395,18 @@ int dsi_panel_set_esd_check(struct dsi_panel *panel); int dsi_panel_sync_pen_fps(struct dsi_panel *panel, struct dsi_display_mode *adj_mode); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int dsi_panel_esd_irq_ctrl(struct dsi_panel *panel, bool enable); + +ssize_t dsi_panel_lockdown_info_read(unsigned char *plockdowninfo); + +int dsi_panel_write_cmd_set(struct dsi_panel *panel, struct dsi_panel_cmd_set *cmd_sets); + +int dsi_panel_read_cmd_set(struct dsi_panel *panel, struct dsi_read_config *read_config); + +void dsi_panel_doubleclick_enable(bool on); + +int dsi_panel_lockdowninfo_param_read(struct dsi_panel *panel); +#endif + #endif /* _DSI_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c index e5339f9c1d0a..873bdea40de5 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c @@ -131,6 +131,9 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, * to the logical data lane 0 */ DSI_W32(phy, DSIPHY_LNX_LPRX_CTRL(i), 0); +#ifdef CONFIG_MACH_XIAOMI_NABU + DSI_W32(phy, DSIPHY_LNX_PIN_SWAP(i), 0x0); +#endif } dsi_phy_hw_v4_0_config_lpcdrx(phy, cfg, true); @@ -140,8 +143,10 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, DSI_W32(phy, DSIPHY_LNX_CFG1(i), cfg->lanecfg.lane[i][1]); DSI_W32(phy, DSIPHY_LNX_CFG2(i), cfg->lanecfg.lane[i][2]); DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(i), tx_dctrl[i]); +#ifndef CONFIG_MACH_XIAOMI_NABU DSI_W32(phy, DSIPHY_LNX_PIN_SWAP(i), (cfg->lane_pnswap >> i) & 0x1); +#endif } } diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index 30a9dbd1d18a..398fb943a8fc 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -21,6 +21,9 @@ #include #include "dsi_drm.h" #include "dsi_display.h" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#include "dsi_panel.h" +#endif #include "sde_crtc.h" #include "sde_rm.h" @@ -758,12 +761,19 @@ void sde_connector_helper_bridge_enable(struct drm_connector *connector) MSM_ENC_TX_COMPLETE); c_conn->allow_bl_update = true; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!display->is_first_boot && c_conn->bl_device) { +#else if (c_conn->bl_device) { +#endif c_conn->bl_device->props.power = FB_BLANK_UNBLANK; c_conn->bl_device->props.state &= ~BL_CORE_FBBLANK; backlight_update_status(c_conn->bl_device); } c_conn->panel_dead = false; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + display->is_first_boot = false; +#endif } int sde_connector_clk_ctrl(struct drm_connector *connector, bool enable) @@ -1879,10 +1889,65 @@ static int sde_connector_atomic_check(struct drm_connector *connector, return 0; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static irqreturn_t esd_err_irq_handle(int irq, void *data) +{ + struct sde_connector *c_conn = data; + struct drm_event event; + bool panel_on = false; + struct dsi_display *display; + + if (!c_conn && !c_conn->display) { + return IRQ_HANDLED; + } + + display = c_conn->display; + + if (!display || !display->panel) { + SDE_ERROR("invalid display/panel\n"); + return IRQ_HANDLED; + } + + if (gpio_get_value(display->panel->esd_config.esd_err_irq_gpio) && display->panel->cphy_esd_check) { + SDE_ERROR("trigger esd by mistake,return\n"); + return IRQ_HANDLED; + } + + if (c_conn->connector_type == DRM_MODE_CONNECTOR_DSI) { + struct dsi_display * dsi_display = (struct dsi_display *)(c_conn->display); + if (dsi_display && dsi_display->panel) { + panel_on = dsi_display->panel->panel_initialized; + } + + if (atomic_read(&(display->panel->esd_recovery_pending))) { + SDE_ERROR("ESD recovery already pending\n"); + return IRQ_HANDLED; + } + + if (panel_on && (c_conn->panel_dead == false)) { + atomic_set(&display->panel->esd_recovery_pending, 1); + } + } + + if (panel_on && (c_conn->panel_dead == false)) { + c_conn->panel_dead = true; + event.type = DRM_EVENT_PANEL_DEAD; + event.length = sizeof(bool); + msm_mode_object_event_notify(&c_conn->base.base, + c_conn->base.dev, &event, (u8 *)&c_conn->panel_dead); + sde_encoder_display_failure_notification(c_conn->encoder,false); + } + return IRQ_HANDLED; +} +#endif + static void _sde_connector_report_panel_dead(struct sde_connector *conn, bool skip_pre_kickoff) { struct drm_event event; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct dsi_display *display = (struct dsi_display *)(conn->display); +#endif if (!conn) return; @@ -1896,6 +1961,9 @@ static void _sde_connector_report_panel_dead(struct sde_connector *conn, return; conn->panel_dead = true; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + display->panel->panel_dead_flag = true; +#endif event.type = DRM_EVENT_PANEL_DEAD; event.length = sizeof(bool); msm_mode_object_event_notify(&conn->base.base, @@ -2315,6 +2383,21 @@ struct drm_connector *sde_connector_init(struct drm_device *dev, sizeof(dsi_display->panel->hdr_props), CONNECTOR_PROP_HDR_INFO); } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* register esd irq and enable it after panel enabled */ + if (dsi_display && dsi_display->panel && + dsi_display->panel->esd_config.esd_err_irq_gpio > 0) { + rc = request_threaded_irq(dsi_display->panel->esd_config.esd_err_irq, + NULL, esd_err_irq_handle, + dsi_display->panel->esd_config.esd_err_irq_flags, + "esd_err_irq", c_conn); + if (rc < 0) { + pr_err("%s: request irq %d failed\n", __func__, dsi_display->panel->esd_config.esd_err_irq); + dsi_display->panel->esd_config.esd_err_irq = 0; + } + } +#endif } rc = sde_connector_get_info(&c_conn->base, &display_info); From 98e5c79dc77054135f4b6f8a4ece0a72b90a4a8a Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 17:55:11 +0200 Subject: [PATCH 040/226] drivers: Import halls driver * From cepheus-q-oss * Run clang-format on source files Change-Id: I0bb9b2a35997c1ef6a078841b9586b9ee94db9a5 Signed-off-by: firebird11 --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/halls/Kconfig | 9 ++ drivers/halls/Makefile | 1 + drivers/halls/halls.c | 311 +++++++++++++++++++++++++++++++++++++++++ include/linux/halls.h | 7 + 6 files changed, 331 insertions(+) create mode 100644 drivers/halls/Kconfig create mode 100644 drivers/halls/Makefile create mode 100644 drivers/halls/halls.c create mode 100644 include/linux/halls.h diff --git a/drivers/Kconfig b/drivers/Kconfig index 43377a3acb97..cfd0d22ebcca 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -225,4 +225,6 @@ source "drivers/sensors/Kconfig" source "drivers/esoc/Kconfig" +source "drivers/halls/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 4a067525bbdc..2f8e36eb37d5 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -188,6 +188,7 @@ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_SENSORS_SSC) += sensors/ obj-$(CONFIG_ESOC) += esoc/ +obj-$(CONFIG_HALLS) += halls/ # GNSS driver obj-$(CONFIG_GNSS_SIRF) += gnsssirf/ obj-$(CONFIG_GNSS) += gnss/ diff --git a/drivers/halls/Kconfig b/drivers/halls/Kconfig new file mode 100644 index 000000000000..75543568a7b1 --- /dev/null +++ b/drivers/halls/Kconfig @@ -0,0 +1,9 @@ +menu "Halls" + +config HALLS + bool "Halls" + default n + ---help--- + it's to handle hall sensors for slide + +endmenu diff --git a/drivers/halls/Makefile b/drivers/halls/Makefile new file mode 100644 index 000000000000..7c7b3ec68643 --- /dev/null +++ b/drivers/halls/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_HALLS) += halls.o diff --git a/drivers/halls/halls.c b/drivers/halls/halls.c new file mode 100644 index 000000000000..b7060a2b9771 --- /dev/null +++ b/drivers/halls/halls.c @@ -0,0 +1,311 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define HALLS_LOG printk + +#define LOGTAG "halls " +#define DEF_HALLS_DEVICE_NAME "halls" + +#define DEF_HALLS_IOCTRL_READ_HALL_1 1000 +#define DEF_HALLS_IOCTRL_READ_HALL_2 2000 +#define DEF_HALLS_IOCTRL_FLUSH 3000 + +#define DEF_HALLS_IOCTRL_STEUP 4000 +#define DEF_HALLS_IOCTRL_RELEASE 5000 + +#define DEF_HALL_IRQ_1_FIRED "h-1" +#define DEF_HALL_IRQ_2_FIRED "h-2" +#define DEF_HALL_FLUSH "flu" + +#define DEF_HALL_GPIO_1 42 +#define DEF_HALL_GPIO_2 114 + +//extern int elliptic_set_hall_state(int state); + +static int g_gpio_1_irq; +static int g_gpio_2_irq; +static int g_in_firedirq; +static int g_in_end; +static int g_in_flush; + +static int g_in_opencounter; + +struct _hall_device { + struct miscdevice miscdev; + struct delayed_work notify_work; + struct wakeup_source *hall_wakelock; + int hall_status; +}; + +struct _hall_device *g_st_halls; +struct semaphore g_st_semhallirq; + +halls_status_notify halls_status_notify_cb = NULL; + +void halls_register_halls_status_notify(halls_status_notify halls_cb) +{ + halls_status_notify_cb = halls_cb; +} + +void halls_deregister_halls_status_notify(halls_status_notify halls_cb) +{ + halls_status_notify_cb = NULL; +} + +static void hall_notify_work_func(struct work_struct *work) +{ + int iRet1 = 0, iRet2 = 0; + iRet1 = gpio_get_value_cansleep(DEF_HALL_GPIO_1); + iRet2 = gpio_get_value_cansleep(DEF_HALL_GPIO_2); + HALLS_LOG(LOGTAG "g_in_firedirq %d, g_gpio_1_irq %d, g_gpio_2_irq %d", + g_in_firedirq, g_gpio_1_irq, g_gpio_2_irq); + HALLS_LOG(LOGTAG " iRet1 %d iRet2 %d", iRet1, iRet2); + if (iRet1 == 0 && iRet2 == 1) { + g_st_halls->hall_status = 1; + } else if (iRet1 == 1 && iRet2 == 0) { + g_st_halls->hall_status = 0; + } else { + g_st_halls->hall_status = 2; + } + + HALLS_LOG(LOGTAG "hall_notify_work_func notify audio hall_status: %d!", + g_st_halls->hall_status); + //elliptic_set_hall_state(g_st_halls->hall_status); + if (halls_status_notify_cb != NULL) { + halls_status_notify_cb(g_st_halls->hall_status); + } +} + +static irqreturn_t halls_irq_handler(int irqno, void *dev_id) +{ + HALLS_LOG(LOGTAG "Entered halls_irq_handler irqno %d\n", irqno); + __pm_wakeup_event(g_st_halls->hall_wakelock, 20); + g_in_firedirq = irqno; + up(&g_st_semhallirq); + schedule_delayed_work(&g_st_halls->notify_work, 0); + return 0; +} + +static int halls_configurate_input(int in_GPIO, const char *ch_mark) +{ + int iRet = 0; + + iRet = gpio_request(in_GPIO, ch_mark); + if (iRet) + pr_err("%d is being used!\n", in_GPIO); + + iRet = gpio_direction_input(in_GPIO); + if (iRet) + pr_err("Setting hall gpio direction failed! iRet %d\n", iRet); + + return iRet; +} + +static int halls_configurate_irq(int in_GPIO, const char *ch_mark, void *arg, + int *out_irq) +{ + int iRet = 0, in_IRQ = 0; + + in_IRQ = gpio_to_irq(in_GPIO); + *out_irq = in_IRQ; + HALLS_LOG(LOGTAG "in_GPIO %d, IRQ %d\n", in_GPIO, in_IRQ); + iRet = request_irq(in_IRQ, halls_irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, + ch_mark, arg); + if (iRet) + pr_err("request_irq failed! iRet %d\n", iRet); + irq_set_irq_wake(in_IRQ, 1); + + HALLS_LOG(LOGTAG "request_irq return %d\n", iRet); + return iRet; +} + +static ssize_t halls_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + int iRead = 0; + + HALLS_LOG(LOGTAG "Entereed halls_read count %d", (int)count); + if (down_interruptible(&g_st_semhallirq)) { + HALLS_LOG(LOGTAG "down_interruptible failed!"); + } + if (g_in_end == 1) { + HALLS_LOG(LOGTAG "Ending... "); + return -EPERM; + } + HALLS_LOG(LOGTAG "g_in_firedirq %d, g_gpio_1_irq %d, g_gpio_2_irq %d", + g_in_firedirq, g_gpio_1_irq, g_gpio_2_irq); + if (g_in_flush == 1) { + g_in_flush = 0; + iRead = copy_to_user(buf, DEF_HALL_FLUSH, + strlen(DEF_HALL_FLUSH)); + HALLS_LOG(LOGTAG "End of copy_to_user flash... "); + } else if (g_in_firedirq == g_gpio_1_irq) { + iRead = copy_to_user(buf, DEF_HALL_IRQ_1_FIRED, + strlen(DEF_HALL_IRQ_1_FIRED)); + HALLS_LOG(LOGTAG "End of copy_to_user 1... "); + } else if (g_in_firedirq == g_gpio_2_irq) { + iRead = copy_to_user(buf, DEF_HALL_IRQ_2_FIRED, + strlen(DEF_HALL_IRQ_2_FIRED)); + HALLS_LOG(LOGTAG "End of copy_to_user 2... "); + } + return iRead; +} + +long halls_in_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int iRet = 0; + void *p_ReadValue = (void *)arg; + char ch_data[10] = { 0 }; + + HALLS_LOG(LOGTAG "Enter halls_in_ioctl cmd %d", cmd); + switch (cmd) { + case DEF_HALLS_IOCTRL_READ_HALL_1: { + iRet = gpio_get_value_cansleep(DEF_HALL_GPIO_1); + HALLS_LOG(LOGTAG "Read HALL_1 %d", iRet); + snprintf(ch_data, sizeof(ch_data), "%d", iRet); + iRet = copy_to_user(p_ReadValue, ch_data, strlen(ch_data)); + break; + } + case DEF_HALLS_IOCTRL_READ_HALL_2: { + iRet = gpio_get_value_cansleep(DEF_HALL_GPIO_2); + HALLS_LOG(LOGTAG "Read HALL_2 %d", iRet); + snprintf(ch_data, sizeof(ch_data), "%d", iRet); + iRet = copy_to_user(p_ReadValue, ch_data, strlen(ch_data)); + break; + } + case DEF_HALLS_IOCTRL_FLUSH: { + g_in_flush = 1; + up(&g_st_semhallirq); + schedule_delayed_work(&g_st_halls->notify_work, 0); + break; + } + case DEF_HALLS_IOCTRL_STEUP: { + if (g_in_opencounter == 0) { + g_in_end = 0; + sema_init(&g_st_semhallirq, 0); + iRet = halls_configurate_irq(DEF_HALL_GPIO_1, "hall-1", + (void *)g_st_halls, + &g_gpio_1_irq); + if (iRet) + pr_err("halls_configurate_irq failed!%d, iRet %d\n", + DEF_HALL_GPIO_1, iRet); + g_in_firedirq = g_gpio_1_irq; + + iRet = halls_configurate_irq(DEF_HALL_GPIO_2, "hall-2", + (void *)g_st_halls, + &g_gpio_2_irq); + if (iRet) + pr_err("halls_configurate_irq failed! %d iRet %d\n", + DEF_HALL_GPIO_2, iRet); + + HALLS_LOG(LOGTAG "g_gpio_2_irq %d, g_gpio_2_irq %d\n", + g_gpio_1_irq, g_gpio_2_irq); + g_in_opencounter = 1; + } + break; + } + case DEF_HALLS_IOCTRL_RELEASE: { + g_in_end = 1; + up(&g_st_semhallirq); + if (g_gpio_1_irq > 0) + free_irq(g_gpio_1_irq, g_st_halls); + + if (g_gpio_2_irq > 0) + free_irq(g_gpio_2_irq, g_st_halls); + g_in_opencounter = 0; + break; + } + default: + iRet = -1; + } + HALLS_LOG(LOGTAG "read value cmd %d, iRet %d", cmd, iRet); + return iRet; +} + +int halls_flush(struct file *file, fl_owner_t id) +{ + HALLS_LOG(LOGTAG " Entered halls_flush \n"); + return 0; +} + +int halls_open(struct inode *node, struct file *file) +{ + int iRet = 0; + + return iRet; +} + +static const struct file_operations halls_fops = { + .owner = THIS_MODULE, + .read = halls_read, + .unlocked_ioctl = halls_in_ioctl, + .flush = halls_flush, + .open = halls_open, +}; + +static int __init halls_init(void) +{ + int ret; + g_st_halls = kzalloc(sizeof(struct _hall_device), GFP_KERNEL); + if (!g_st_halls) + return -ENOMEM; + g_st_halls->miscdev.fops = &halls_fops; + g_st_halls->miscdev.minor = MISC_DYNAMIC_MINOR; + g_st_halls->miscdev.name = DEF_HALLS_DEVICE_NAME; + ret = misc_register(&g_st_halls->miscdev); + if (ret < 0) { + kfree(g_st_halls); + return ret; + } + ret = halls_configurate_input(DEF_HALL_GPIO_1, "hall-1"); + if (ret) { + pr_err("halls_configurate_input failed!%d, ret %d\n", + DEF_HALL_GPIO_1, ret); + gpio_free(DEF_HALL_GPIO_1); + return ret; + } + ret = halls_configurate_input(DEF_HALL_GPIO_2, "hall-2"); + if (ret) { + pr_err("halls_configurate_input failed! %d ret %d\n", + DEF_HALL_GPIO_2, ret); + gpio_free(DEF_HALL_GPIO_2); + return ret; + } + + g_st_halls->hall_status = 0; + INIT_DELAYED_WORK(&g_st_halls->notify_work, hall_notify_work_func); + + g_st_halls->hall_wakelock = wakeup_source_register("dual_hall_ws"); + if (!g_st_halls->hall_wakelock) { + pr_err("g_st_halls wakeup_source_register failed!\n"); + return ret; + } + + return ret; +} + +device_initcall(halls_init); + +static void __exit halls_exit(void) +{ + gpio_free(DEF_HALL_GPIO_1); + gpio_free(DEF_HALL_GPIO_2); +} + +module_exit(halls_exit); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/halls.h b/include/linux/halls.h new file mode 100644 index 000000000000..f9cf7349bf94 --- /dev/null +++ b/include/linux/halls.h @@ -0,0 +1,7 @@ +#ifndef HALLS_H +#define HALLS_H + +typedef void (*halls_status_notify)(int halls_status); +extern void halls_register_halls_status_notify(halls_status_notify halls_cb); + +#endif /* HALLS_H */ From db9e9b0e4c3134c880667f30382e59558ae03969 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 16 Apr 2024 03:39:16 +0200 Subject: [PATCH 041/226] drivers: halls: Fix compilation Change-Id: I474a9b983659ec6df30acaafe78c3204d83cc1e3 Signed-off-by: firebird11 --- drivers/halls/halls.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/halls/halls.c b/drivers/halls/halls.c index b7060a2b9771..2169261feb06 100644 --- a/drivers/halls/halls.c +++ b/drivers/halls/halls.c @@ -290,7 +290,8 @@ static int __init halls_init(void) g_st_halls->hall_status = 0; INIT_DELAYED_WORK(&g_st_halls->notify_work, hall_notify_work_func); - g_st_halls->hall_wakelock = wakeup_source_register("dual_hall_ws"); + g_st_halls->hall_wakelock = wakeup_source_register( + g_st_halls->miscdev.this_device, "dual_hall_ws"); if (!g_st_halls->hall_wakelock) { pr_err("g_st_halls wakeup_source_register failed!\n"); return ret; From d1fe373220c285c6d85a5fbf1469fb0ca5957295 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 17:57:23 +0200 Subject: [PATCH 042/226] drivers: iio: adc: Import Xiaomi changes Change-Id: I0a5ef10d57b86f21b4acbf7255826bdbed629cc0 Signed-off-by: firebird11 --- drivers/iio/adc/qcom-spmi-adc5.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 4ba747ce108d..36861c2b17f3 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -763,10 +763,17 @@ static const struct adc_channels adc_chans_pmic5[ADC_MAX_CHANNEL] = { SCALE_HW_CALIB_PM5_SMB_TEMP) [ADC_AMUX_THM3] = ADC_CHAN_TEMP("amux_thm3", 1, SCALE_HW_CALIB_PM5_SMB_TEMP) +#ifdef CONFIG_MACH_XIAOMI_SM8150 + [ADC_GPIO1_PU2] = ADC_CHAN_VOLT("gpio1_pu2", 1, + SCALE_HW_CALIB_DEFAULT) + [ADC_GPIO2_PU2] = ADC_CHAN_VOLT("gpio2_pu2", 1, + SCALE_HW_CALIB_DEFAULT) +#else [ADC_GPIO1_PU2] = ADC_CHAN_TEMP("gpio1_pu2", 1, SCALE_HW_CALIB_THERM_100K_PULLUP) [ADC_GPIO2_PU2] = ADC_CHAN_TEMP("gpio2_pu2", 1, SCALE_HW_CALIB_THERM_100K_PULLUP) +#endif [ADC_GPIO3_PU2] = ADC_CHAN_TEMP("gpio3_pu2", 1, SCALE_HW_CALIB_THERM_100K_PULLUP) [ADC_GPIO4_PU2] = ADC_CHAN_TEMP("gpio4_pu2", 1, From 40d855a9c3b7db6f68f0e7637c95038cbb0af259 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 17:58:43 +0200 Subject: [PATCH 043/226] drivers: iio: proximity: Import MIUS driver * From nabu-r-oss * Run clang-format on source files Change-Id: Iefd42f02cac26acb71fe6bd7e1c78dea982b80ee Signed-off-by: firebird11 --- drivers/iio/proximity/Kconfig | 8 + drivers/iio/proximity/Makefile | 1 + drivers/iio/proximity/us_prox.c | 335 ++++++++++++++++++++++++++++++++ 3 files changed, 344 insertions(+) create mode 100644 drivers/iio/proximity/us_prox.c diff --git a/drivers/iio/proximity/Kconfig b/drivers/iio/proximity/Kconfig index c03de24d3c51..0a64be17930b 100644 --- a/drivers/iio/proximity/Kconfig +++ b/drivers/iio/proximity/Kconfig @@ -69,4 +69,12 @@ config SRF08 To compile this driver as a module, choose M here: the module will be called srf08. +config US_PROXIMITY + tristate "xiaomi ultrasound proximity sensor" + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + select IIO_BUFFER_CB + select IIO_KFIFO_BUF + select IIO_TRIGGER + endmenu diff --git a/drivers/iio/proximity/Makefile b/drivers/iio/proximity/Makefile index ad6686391f08..6420fb39d232 100644 --- a/drivers/iio/proximity/Makefile +++ b/drivers/iio/proximity/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_LIDAR_LITE_V2) += pulsedlight-lidar-lite-v2.o obj-$(CONFIG_SRF04) += srf04.o obj-$(CONFIG_SRF08) += srf08.o obj-$(CONFIG_SX9500) += sx9500.o +obj-$(CONFIG_US_PROXIMITY) += us_prox.o diff --git a/drivers/iio/proximity/us_prox.c b/drivers/iio/proximity/us_prox.c new file mode 100644 index 000000000000..c6874cb2ecba --- /dev/null +++ b/drivers/iio/proximity/us_prox.c @@ -0,0 +1,335 @@ +/* + * + * Copyright (C) 2018 XiaoMi, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define US_PROX_IIO_NAME "distance" + +static struct us_prox_data *g_us_prox; + +struct us_prox_data { + struct platform_device *pdev; + /* common state */ + struct mutex mutex; + /* for proximity sensor */ + struct iio_dev *prox_idev; + bool prox_enabled; + int raw_data; +}; + +struct us_prox_el_data { + uint16_t data1; + uint16_t data2; + int64_t timestamp; +}; + +#define US_SENSORS_CHANNELS(device_type, mask, index, mod, ch2, s, endian, \ + rbits, sbits, addr) \ + { \ + .type = device_type, .modified = mod, \ + .info_mask_separate = mask, .scan_index = index, \ + .channel2 = ch2, .address = addr, \ + .scan_type = { \ + .sign = s, \ + .realbits = rbits, \ + .shift = sbits - rbits, \ + .storagebits = sbits, \ + .endianness = endian, \ + }, \ + } + +static const struct iio_chan_spec us_proximity_channels[] = { + US_SENSORS_CHANNELS(IIO_PROXIMITY, + BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + 0, 0, IIO_NO_MOD, 'u', IIO_LE, 16, 16, 0), + IIO_CHAN_SOFT_TIMESTAMP(2) +}; + +static int us_buffer_postenable(struct iio_dev *indio_dev) +{ + int ret = 0; + return ret; +} + +static int us_buffer_predisable(struct iio_dev *indio_dev) +{ + int ret = 0; + return ret; +} + +static const struct iio_buffer_setup_ops us_buffer_setup_ops = { + .postenable = us_buffer_postenable, + .predisable = us_buffer_predisable, +}; + +static const struct iio_trigger_ops us_sensor_trigger_ops = { + .owner = THIS_MODULE, +}; + +int us_setup_trigger_sensor(struct iio_dev *indio_dev) +{ + struct iio_trigger *trigger; + int ret; + + trigger = iio_trigger_alloc("%s-dev%d", indio_dev->name, indio_dev->id); + if (!trigger) + return -ENOMEM; + + trigger->dev.parent = indio_dev->dev.parent; + trigger->ops = &us_sensor_trigger_ops; + ret = iio_trigger_register(trigger); + if (ret < 0) + goto exit_free_trigger; + + indio_dev->trig = trigger; + + return 0; + +exit_free_trigger: + iio_trigger_free(trigger); + return ret; +} + +int us_afe_callback(int data) +{ + int ret; + struct us_prox_el_data el_data; + struct timespec ts; + + get_monotonic_boottime(&ts); + el_data.timestamp = timespec_to_ns(&ts); + pr_info("%s: data = %d\n", __func__, data); + + if (!data) + el_data.data1 = 0; + else + el_data.data1 = 5; + + if (g_us_prox) { + ret = iio_push_to_buffers(g_us_prox->prox_idev, + (unsigned char *)&el_data); + if (ret < 0) + pr_err("%s: failed to push us prox data to buffer, err=%d\n", + __func__, ret); + } + + return 0; +} + +EXPORT_SYMBOL(us_afe_callback); + +static ssize_t us_show_dump_output(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct us_prox_data *data; + unsigned long value; + + data = *((struct us_prox_data **)iio_priv(dev_get_drvdata(dev))); + + mutex_lock(&data->mutex); + value = data->raw_data; + mutex_unlock(&data->mutex); + + return scnprintf(buf, PAGE_SIZE, "%lu\n", value); +} + +static ssize_t us_store_dump_output(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + return 0; +} + +static DEVICE_ATTR(dump_output, S_IWUSR | S_IRUGO, us_show_dump_output, + us_store_dump_output); + +static struct attribute *us_prox_attributes[] = { + &dev_attr_dump_output.attr, + NULL, +}; + +static struct attribute_group us_prox_attribute_group = { + .attrs = us_prox_attributes, +}; + +static const struct iio_info us_proximity_info = { + .driver_module = THIS_MODULE, + .attrs = &us_prox_attribute_group, +}; + +static int us_proximity_iio_setup(struct us_prox_data *data) +{ + struct iio_dev *idev; + struct us_prox_data **priv_data; + int ret = 0; + + idev = iio_device_alloc(sizeof(*priv_data)); + if (!idev) { + pr_err("us prox IIO memory alloc fail\n"); + return -ENOMEM; + } + + data->prox_idev = idev; + + idev->channels = us_proximity_channels; + idev->num_channels = ARRAY_SIZE(us_proximity_channels); + idev->dev.parent = &(data->pdev->dev); + idev->info = &us_proximity_info; + idev->name = US_PROX_IIO_NAME; + idev->modes = INDIO_DIRECT_MODE; + + priv_data = iio_priv(idev); + *priv_data = data; + + ret = iio_triggered_buffer_setup(idev, NULL, NULL, + &us_buffer_setup_ops); + if (ret < 0) + goto free_iio_p; + + ret = us_setup_trigger_sensor(idev); + if (ret < 0) + goto free_buffer_p; + + ret = iio_device_register(idev); + if (ret) { + pr_err("Proximity IIO register fail\n"); + goto free_trigger_p; + } + return ret; + +free_trigger_p: + iio_trigger_unregister(idev->trig); + iio_trigger_free(idev->trig); +free_buffer_p: + iio_triggered_buffer_cleanup(idev); +free_iio_p: + data->prox_idev = NULL; + iio_device_free(idev); + return ret; +} + +static int us_proximity_teardown(struct us_prox_data *data) +{ + iio_device_unregister(data->prox_idev); + iio_trigger_unregister(data->prox_idev->trig); + iio_trigger_free(data->prox_idev->trig); + iio_triggered_buffer_cleanup(data->prox_idev); + iio_device_free(data->prox_idev); + + return 0; +} + +static int us_prox_probe(struct platform_device *pdev) +{ + int ret = 0; + struct us_prox_data *us_prox; + + pr_info("%s: start\n", __func__); + + us_prox = kzalloc(sizeof(*us_prox), GFP_KERNEL); + if (!us_prox) + return -ENOMEM; + + us_prox->pdev = pdev; + dev_set_drvdata(&pdev->dev, us_prox); + + g_us_prox = us_prox; + + mutex_init(&us_prox->mutex); + ret = us_proximity_iio_setup(us_prox); + if (ret < 0) { + pr_err("%s: iio setup failed ret = %d\n", __func__, ret); + return ret; + } + + pr_info("%s: end\n", __func__); + return ret; +} + +static int us_prox_remove(struct platform_device *pdev) +{ + struct us_prox_data *us_prox; + + us_prox = dev_get_drvdata(&pdev->dev); + + dev_set_drvdata(&pdev->dev, NULL); + + if (us_prox) { + us_proximity_teardown(us_prox); + kfree(us_prox); + } + + return 0; +} + +static const struct of_device_id dt_match[] = { + { .compatible = "us_prox" }, + {}, +}; + +static struct platform_driver us_prox_driver = { + .probe = us_prox_probe, + .remove = us_prox_remove, + .driver = { + .name = "us_prox", + .of_match_table = dt_match, + }, +}; + +static struct platform_device us_prox_dev = { + .name = "us_prox", + .dev = { + .platform_data = NULL, + }, +}; + +static int __init us_prox_init(void) +{ + platform_device_register(&us_prox_dev); + return platform_driver_register(&us_prox_driver); +} +module_init(us_prox_init); + +static void __exit us_prox_exit(void) +{ + platform_driver_unregister(&us_prox_driver); + platform_device_unregister(&us_prox_dev); +} +module_exit(us_prox_exit); + +MODULE_AUTHOR("xiaomi"); +MODULE_DESCRIPTION("Ultrasound IIO driver"); +MODULE_LICENSE("GPL"); From 00a450be02d44013c453078ed351d9a2eeb599f8 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:00:41 +0200 Subject: [PATCH 044/226] drivers: input: fingerprint: Import Xiaomi fingerprint drivers * Run clang-format on source files Change-Id: I6bb929b295b0dd9394e0dc0af674cc0be00422ab Signed-off-by: firebird11 --- drivers/input/Kconfig | 2 + drivers/input/Makefile | 1 + drivers/input/fingerprint/Kconfig | 17 + drivers/input/fingerprint/Makefile | 8 + drivers/input/fingerprint/fpc_tee/Kconfig | 16 + drivers/input/fingerprint/fpc_tee/Makefile | 1 + .../input/fingerprint/fpc_tee/fpc1020_tee.c | 872 +++++++++++++ drivers/input/fingerprint/goodix_ta/Kconfig | 10 + drivers/input/fingerprint/goodix_ta/Makefile | 1 + drivers/input/fingerprint/goodix_ta/gf_spi.c | 1077 +++++++++++++++++ drivers/input/fingerprint/goodix_ta/gf_spi.h | 160 +++ drivers/input/fingerprint/goodix_ta/netlink.c | 97 ++ .../input/fingerprint/goodix_ta/platform.c | 150 +++ 13 files changed, 2412 insertions(+) create mode 100644 drivers/input/fingerprint/Kconfig create mode 100644 drivers/input/fingerprint/Makefile create mode 100644 drivers/input/fingerprint/fpc_tee/Kconfig create mode 100644 drivers/input/fingerprint/fpc_tee/Makefile create mode 100644 drivers/input/fingerprint/fpc_tee/fpc1020_tee.c create mode 100644 drivers/input/fingerprint/goodix_ta/Kconfig create mode 100644 drivers/input/fingerprint/goodix_ta/Makefile create mode 100644 drivers/input/fingerprint/goodix_ta/gf_spi.c create mode 100644 drivers/input/fingerprint/goodix_ta/gf_spi.h create mode 100644 drivers/input/fingerprint/goodix_ta/netlink.c create mode 100644 drivers/input/fingerprint/goodix_ta/platform.c diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 1b748ad70af3..285cae64411f 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -215,6 +215,8 @@ source "drivers/input/sensors/smi130/Kconfig" source "drivers/input/rmi4/Kconfig" +source "drivers/input/fingerprint/Kconfig" + endif menu "Hardware I/O ports" diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 7133c3bc1b04..6d0bf108d536 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_INPUT_JOYSTICK) += joystick/ obj-$(CONFIG_INPUT_TABLET) += tablet/ obj-$(CONFIG_INPUT_TOUCHSCREEN) += touchscreen/ obj-$(CONFIG_INPUT_MISC) += misc/ +obj-$(CONFIG_INPUT_FINGERPRINT) += fingerprint/ obj-$(CONFIG_INPUT_APMPOWER) += apm-power.o obj-$(CONFIG_INPUT_KEYRESET) += keyreset.o diff --git a/drivers/input/fingerprint/Kconfig b/drivers/input/fingerprint/Kconfig new file mode 100644 index 000000000000..785c6066ce6b --- /dev/null +++ b/drivers/input/fingerprint/Kconfig @@ -0,0 +1,17 @@ +# +# Fingerprint driver configuration +# +menuconfig INPUT_FINGERPRINT + bool "Fingerprints" + help + Say Y here, and a list of supported fingerprints will be displayed. + This option doesn't affect the kernel. + + If unsure, say Y. + +if INPUT_FINGERPRINT + +source "drivers/input/fingerprint/goodix_ta/Kconfig" +source "drivers/input/fingerprint/fpc_tee/Kconfig" + +endif diff --git a/drivers/input/fingerprint/Makefile b/drivers/input/fingerprint/Makefile new file mode 100644 index 000000000000..e128700726eb --- /dev/null +++ b/drivers/input/fingerprint/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the fingerprint drivers. +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_FINGERPRINT_GOODIX_TA) += goodix_ta/ +obj-$(CONFIG_FINGERPRINT_FPC_TEE) += fpc_tee/ diff --git a/drivers/input/fingerprint/fpc_tee/Kconfig b/drivers/input/fingerprint/fpc_tee/Kconfig new file mode 100644 index 000000000000..6cfc23fa0f37 --- /dev/null +++ b/drivers/input/fingerprint/fpc_tee/Kconfig @@ -0,0 +1,16 @@ +config FINGERPRINT_FPC_TEE + tristate "Finger print card fpc" + depends on INPUT_FINGERPRINT + help + Say Y here to enable support for retrieving self-test reports. + + If unsure, say N. + + To compile this driver as a module, choose M here. + +config FINGERPRINT_FPC_SCREEN_NOTIFY + bool "fingerprint get screen status and notify" + default n + depends on FINGERPRINT_FPC_TEE + ---help--- + Say Y here to enable notify screen on/off status. diff --git a/drivers/input/fingerprint/fpc_tee/Makefile b/drivers/input/fingerprint/fpc_tee/Makefile new file mode 100644 index 000000000000..ac8f1bdeb071 --- /dev/null +++ b/drivers/input/fingerprint/fpc_tee/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_FINGERPRINT_FPC_TEE) += fpc1020_tee.o diff --git a/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c new file mode 100644 index 000000000000..4c192c32d1d9 --- /dev/null +++ b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c @@ -0,0 +1,872 @@ +/* + * FPC1020 Fingerprint sensor device driver + * + * This driver will control the platform resources that the FPC fingerprint + * sensor needs to operate. The major things are probing the sensor to check + * that it is actually connected and let the Kernel know this and with that also + * enabling and disabling of regulators, controlling GPIOs such as sensor reset + * line, sensor IRQ line. + * + * The driver will expose most of its available functionality in sysfs which + * enables dynamic control of these features from eg. a user space process. + * + * The sensor's IRQ events will be pushed to Kernel's event handling system and + * are exposed in the drivers event node. + * + * This driver will NOT send any commands to the sensor it only controls the + * electrical parts. + * + * + * Copyright (c) 2015 Fingerprint Cards AB + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License Version 2 + * as published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FPC_SCREEN_HOLD_TIME 2000 +#define FPC_TTW_HOLD_TIME 2000 +#define FP_UNLOCK_REJECTION_TIMEOUT (FPC_TTW_HOLD_TIME - 500) + +#define RESET_LOW_SLEEP_MIN_US 5000 +#define RESET_LOW_SLEEP_MAX_US (RESET_LOW_SLEEP_MIN_US + 100) +#define RESET_HIGH_SLEEP1_MIN_US 100 +#define RESET_HIGH_SLEEP1_MAX_US (RESET_HIGH_SLEEP1_MIN_US + 100) +#define RESET_HIGH_SLEEP2_MIN_US 5000 +#define RESET_HIGH_SLEEP2_MAX_US (RESET_HIGH_SLEEP2_MIN_US + 100) +#define PWR_ON_SLEEP_MIN_US 100 +#define PWR_ON_SLEEP_MAX_US (PWR_ON_SLEEP_MIN_US + 900) + +#define NUM_PARAMS_REG_ENABLE_SET 2 + +static const char *const pctl_names[] = { + "fpc1020_reset_reset", + "fpc1020_reset_active", +}; + +struct vreg_config { + char *name; + unsigned long vmin; + unsigned long vmax; + int ua_load; +}; + +static const struct vreg_config const vreg_conf[] = { + { + "vdd_ana", + 1800000UL, + 1800000UL, + 6000, + }, + { + "fp_vdd_vreg", + 3000000UL, + 3000000UL, + 6000, + }, + /* + { + "vcc_spi", + 1800000UL, + 1800000UL, + 10, + }, + { + "vdd_io", + 1800000UL, + 1800000UL, + 6000, + }, + */ +}; + +struct fpc1020_data { + struct device *dev; + + struct pinctrl *fingerprint_pinctrl; + struct pinctrl_state *pinctrl_state[ARRAY_SIZE(pctl_names)]; + struct regulator *vreg[ARRAY_SIZE(vreg_conf)]; + + struct wakeup_source ttw_wl; + struct wakeup_source screen_wl; + int irq_gpio; + int rst_gpio; + struct mutex lock; /* To set/get exported values in sysfs */ + bool prepared; + atomic_t wakeup_enabled; /* Used both in ISR and non-ISR */ + int irqf; + struct notifier_block fb_notifier; + bool fb_black; + bool wait_finger_down; + struct work_struct work; +}; + +static irqreturn_t fpc1020_irq_handler(int irq, void *handle); +static int fpc1020_request_named_gpio(struct fpc1020_data *fpc1020, + const char *label, int *gpio); + +static int vreg_setup(struct fpc1020_data *fpc1020, const char *name, + bool enable) +{ + size_t i; + int rc; + struct regulator *vreg; + struct device *dev = fpc1020->dev; + + for (i = 0; i < ARRAY_SIZE(fpc1020->vreg); i++) { + const char *n = vreg_conf[i].name; + + if (!strncmp(n, name, strlen(n))) + goto found; + } + + dev_err(dev, "Regulator %s not found\n", name); + + return -EINVAL; + +found: + vreg = fpc1020->vreg[i]; + if (enable) { + if (!vreg) { + vreg = regulator_get(dev, name); + if (IS_ERR(vreg)) { + dev_err(dev, "Unable to get %s\n", name); + return PTR_ERR(vreg); + } + } +#if 0 + if (regulator_count_voltages(vreg) > 0) { + rc = regulator_set_voltage(vreg, vreg_conf[i].vmin, + vreg_conf[i].vmax); + if (rc) + dev_err(dev, + "Unable to set voltage on %s, %d\n", + name, rc); + } + + rc = regulator_set_optimum_mode(vreg, vreg_conf[i].ua_load); + if (rc < 0) + dev_err(dev, "Unable to set current on %s, %d\n", + name, rc); +#endif + rc = regulator_enable(vreg); + if (rc) { + dev_err(dev, "error enabling %s: %d\n", name, rc); + regulator_put(vreg); + vreg = NULL; + } + fpc1020->vreg[i] = vreg; + dev_err(dev, "fp_vdd_vreg is enabled!\n"); + } else { + if (vreg) { + if (regulator_is_enabled(vreg)) { + regulator_disable(vreg); + dev_err(dev, "disabled %s\n", name); + } + regulator_put(vreg); + fpc1020->vreg[i] = NULL; + } + rc = 0; + } + + return rc; +} + +/** + * sysfs node for controlling clocks. + * + * This is disabled in platform variant of this driver but kept for + * backwards compatibility. Only prints a debug print that it is + * disabled. + */ +static ssize_t clk_enable_set(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + dev_dbg(dev, "clk_enable sysfs node not enabled in platform driver\n"); + + return count; +} +static DEVICE_ATTR(clk_enable, S_IWUSR, NULL, clk_enable_set); + +/** + * Will try to select the set of pins (GPIOS) defined in a pin control node of + * the device tree named @p name. + * + * The node can contain several eg. GPIOs that is controlled when selecting it. + * The node may activate or deactivate the pins it contains, the action is + * defined in the device tree node itself and not here. The states used + * internally is fetched at probe time. + * + * @see pctl_names + * @see fpc1020_probe + */ +static int select_pin_ctl(struct fpc1020_data *fpc1020, const char *name) +{ + size_t i; + int rc; + struct device *dev = fpc1020->dev; + + for (i = 0; i < ARRAY_SIZE(fpc1020->pinctrl_state); i++) { + const char *n = pctl_names[i]; + + if (!strncmp(n, name, strlen(n))) { + rc = pinctrl_select_state(fpc1020->fingerprint_pinctrl, + fpc1020->pinctrl_state[i]); + if (rc) + dev_err(dev, "cannot select '%s'\n", name); + else + dev_dbg(dev, "Selected '%s'\n", name); + goto exit; + } + } + + rc = -EINVAL; + dev_err(dev, "%s:'%s' not found\n", __func__, name); + +exit: + return rc; +} + +static ssize_t pinctl_set(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + int rc; + + mutex_lock(&fpc1020->lock); + rc = select_pin_ctl(fpc1020, buf); + mutex_unlock(&fpc1020->lock); + + return rc ? rc : count; +} +static DEVICE_ATTR(pinctl_set, S_IWUSR, NULL, pinctl_set); + +static ssize_t regulator_enable_set(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + int rc = 0; + + if (!strncmp(buf, "e", strlen("e"))) { + mutex_lock(&fpc1020->lock); + rc = vreg_setup(fpc1020, "fp_vdd_vreg", true); + mutex_unlock(&fpc1020->lock); + dev_err(dev, "enable fp_vdd_vreg!, rc = %d\n", rc); + } else if (!strncmp(buf, "d", strlen("d"))) { + mutex_lock(&fpc1020->lock); + rc = vreg_setup(fpc1020, "fp_vdd_vreg", false); + mutex_unlock(&fpc1020->lock); + dev_err(dev, "disable fp_vdd_vreg!, rc = %d\n", rc); + } else { + dev_err(dev, "operation disable!\n"); + rc = 1; + } + + return rc ? rc : count; +} +static DEVICE_ATTR(regulator_enable, S_IWUSR, NULL, regulator_enable_set); + +static int hw_reset(struct fpc1020_data *fpc1020) +{ + int irq_gpio; + struct device *dev = fpc1020->dev; + int rc = select_pin_ctl(fpc1020, "fpc1020_reset_active"); + + if (rc) + goto exit; + usleep_range(RESET_HIGH_SLEEP1_MIN_US, RESET_HIGH_SLEEP1_MAX_US); + + rc = select_pin_ctl(fpc1020, "fpc1020_reset_reset"); + if (rc) + goto exit; + usleep_range(RESET_LOW_SLEEP_MIN_US, RESET_LOW_SLEEP_MAX_US); + + rc = select_pin_ctl(fpc1020, "fpc1020_reset_active"); + if (rc) + goto exit; + usleep_range(RESET_HIGH_SLEEP2_MIN_US, RESET_HIGH_SLEEP2_MAX_US); + + irq_gpio = gpio_get_value(fpc1020->irq_gpio); + dev_info(dev, "IRQ after reset %d\n", irq_gpio); + +exit: + return rc; +} + +static ssize_t hw_reset_set(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int rc; + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + + if (!strncmp(buf, "reset", strlen("reset"))) { + mutex_lock(&fpc1020->lock); + rc = hw_reset(fpc1020); + mutex_unlock(&fpc1020->lock); + } else { + return -EINVAL; + } + + return rc ? rc : count; +} +static DEVICE_ATTR(hw_reset, S_IWUSR, NULL, hw_reset_set); + +/** + * Will setup GPIOs, and regulators to correctly initialize the touch sensor to + * be ready for work. + * + * In the correct order according to the sensor spec this function will + * enable/disable regulators, and reset line, all to set the sensor in a + * correct power on or off state "electrical" wise. + * + * @see device_prepare_set + * @note This function will not send any commands to the sensor it will only + * control it "electrically". + */ +static int device_prepare(struct fpc1020_data *fpc1020, bool enable) +{ + int rc; + struct device *dev = fpc1020->dev; + + mutex_lock(&fpc1020->lock); + if (enable && !fpc1020->prepared) { + /* + rc = select_pin_ctl(fpc1020, "fpc1020_irq_active"); + if (rc) { + pr_err("irq gpio set active failed\n"); + goto exit; + } + */ + rc = fpc1020_request_named_gpio(fpc1020, "fpc,gpio_irq", + &fpc1020->irq_gpio); + if (rc) { + pr_err("irq gpio request failed\n"); + goto exit; + } + /* + rc = fpc1020_request_named_gpio(fpc1020, "fpc,gpio_rst", + &fpc1020->rst_gpio); + if (rc) { + pr_err("reset gpio request failed\n"); + goto irq_gpio_exit; + } + */ + rc = devm_request_threaded_irq(dev, + gpio_to_irq(fpc1020->irq_gpio), + NULL, fpc1020_irq_handler, + fpc1020->irqf, dev_name(dev), + fpc1020); + if (rc) { + pr_err("could not request irq %d\n", + gpio_to_irq(fpc1020->irq_gpio)); + goto rst_gpio_exit; + } + + dev_dbg(dev, "requested irq %d\n", + gpio_to_irq(fpc1020->irq_gpio)); + + /* Request that the interrupt should be wakeable */ + enable_irq_wake(gpio_to_irq(fpc1020->irq_gpio)); + select_pin_ctl(fpc1020, "fpc1020_reset_reset"); +#if 0 + rc = vreg_setup(fpc1020, "vcc_spi", true); + if (rc) + goto exit; + + rc = vreg_setup(fpc1020, "vdd_io", true); + if (rc) + goto exit_1; +#endif + rc = vreg_setup(fpc1020, "vdd_ana", true); + if (rc) + goto free_irq_exit; + +#ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL + dev_err(dev, "fp_vdd_reg enabling...\n"); + rc = vreg_setup(fpc1020, "fp_vdd_vreg", true); + if (rc) { + pr_err("fp_vdd_vreg config failed, rc = %d\n", rc); + goto free_irq_exit; + } + dev_err(dev, "fp_vdd_reg enabled success\n"); +#endif + + usleep_range(PWR_ON_SLEEP_MIN_US, PWR_ON_SLEEP_MAX_US); + + /* As we can't control chip select here the other part of the + * sensor driver eg. the TEE driver needs to do a _SOFT_ reset + * on the sensor after power up to be sure that the sensor is + * in a good state after power up. Okeyed by ASIC. */ + + (void)select_pin_ctl(fpc1020, "fpc1020_reset_active"); + hw_reset(fpc1020); + fpc1020->prepared = true; + } else if (!enable && fpc1020->prepared) { + rc = 0; + (void)select_pin_ctl(fpc1020, "fpc1020_reset_reset"); + + usleep_range(PWR_ON_SLEEP_MIN_US, PWR_ON_SLEEP_MAX_US); + + (void)vreg_setup(fpc1020, "vdd_ana", false); +#if 0 +exit_2: + (void)vreg_setup(fpc1020, "vdd_io", false); +exit_1: + (void)vreg_setup(fpc1020, "vcc_spi", false); +#endif +free_irq_exit: + disable_irq(gpio_to_irq(fpc1020->irq_gpio)); + devm_free_irq(dev, gpio_to_irq(fpc1020->irq_gpio), fpc1020); +rst_gpio_exit: + /* + devm_gpio_free(dev, fpc1020->rst_gpio); + */ + devm_gpio_free(dev, fpc1020->irq_gpio); +exit: + fpc1020->prepared = false; + } else { + rc = 0; + } + mutex_unlock(&fpc1020->lock); + + return rc; +} + +/** + * sysfs node to enable/disable (power up/power down) the touch sensor + * + * @see device_prepare + */ +static ssize_t device_prepare_set(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int rc; + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + + if (!strncmp(buf, "enable", strlen("enable"))) { + rc = device_prepare(fpc1020, true); + } else if (!strncmp(buf, "disable", strlen("disable"))) { + rc = device_prepare(fpc1020, false); + } else { + return -EINVAL; + } + + return rc ? rc : count; +} +static DEVICE_ATTR(device_prepare, S_IWUSR, NULL, device_prepare_set); + +/** + * sysfs node for controlling whether the driver is allowed + * to wake up the platform on interrupt. + */ +static ssize_t wakeup_enable_set(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + ssize_t ret = count; + + mutex_lock(&fpc1020->lock); + /* + if (!strncmp(buf, "enable", strlen("enable"))) + atomic_set(&fpc1020->wakeup_enabled, 1); + else if (!strncmp(buf, "disable", strlen("disable"))) + atomic_set(&fpc1020->wakeup_enabled, 0); + else + ret = -EINVAL; + */ + mutex_unlock(&fpc1020->lock); + + return ret; +} +static DEVICE_ATTR(wakeup_enable, S_IWUSR, NULL, wakeup_enable_set); + +/** + * sysf node to check the interrupt status of the sensor, the interrupt + * handler should perform sysf_notify to allow userland to poll the node. + */ +static ssize_t irq_get(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + int irq = gpio_get_value(fpc1020->irq_gpio); + + return scnprintf(buf, PAGE_SIZE, "%i\n", irq); +} + +/** + * writing to the irq node will just drop a printk message + * and return success, used for latency measurement. + */ +static ssize_t irq_ack(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + + dev_dbg(fpc1020->dev, "%s\n", __func__); + + return count; +} +static DEVICE_ATTR(irq, S_IRUSR | S_IWUSR, irq_get, irq_ack); + +static ssize_t fingerdown_wait_set(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + + dev_dbg(fpc1020->dev, "%s\n", __func__); + if (!strncmp(buf, "enable", strlen("enable")) && fpc1020->prepared) + fpc1020->wait_finger_down = true; + else if (!strncmp(buf, "disable", strlen("disable")) && + fpc1020->prepared) + fpc1020->wait_finger_down = false; + else + return -EINVAL; + + return count; +} +static DEVICE_ATTR(fingerdown_wait, S_IWUSR, NULL, fingerdown_wait_set); + +static ssize_t vendor_update(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int rc; + return rc ? rc : count; +} +static DEVICE_ATTR(vendor, S_IWUSR, NULL, vendor_update); + +static ssize_t irq_enable_set(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int rc = 0; + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + + if (!strncmp(buf, "1", strlen("1"))) { + mutex_lock(&fpc1020->lock); + enable_irq(gpio_to_irq(fpc1020->irq_gpio)); + mutex_unlock(&fpc1020->lock); + pr_debug("fpc enable irq\n"); + } else if (!strncmp(buf, "0", strlen("0"))) { + mutex_lock(&fpc1020->lock); + disable_irq(gpio_to_irq(fpc1020->irq_gpio)); + mutex_unlock(&fpc1020->lock); + pr_debug("fpc disable irq\n"); + } + + return rc ? rc : count; +} +static DEVICE_ATTR(irq_enable, S_IWUSR | S_IRUSR | S_IRGRP | S_IWGRP, NULL, + irq_enable_set); + +static ssize_t screen_status_get(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int retval = 0; + struct fpc1020_data *fpc1020 = dev_get_drvdata(dev); + + retval = (fpc1020->fb_black == true) ? 0 : 1; + + return scnprintf(buf, PAGE_SIZE, "%d\n", retval); +} +static DEVICE_ATTR(screen_status, S_IRUSR | S_IRGRP, screen_status_get, NULL); + +static ssize_t vreg_op_cnt_set(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + char value[64] = { 0 }; + + snprintf(value, sizeof(value), "%s", buf); + return count; +} +static DEVICE_ATTR(vreg_op_cnt, S_IWUSR, NULL, vreg_op_cnt_set); + +static struct attribute *attributes[] = { + &dev_attr_pinctl_set.attr, + &dev_attr_device_prepare.attr, + &dev_attr_regulator_enable.attr, + &dev_attr_hw_reset.attr, + &dev_attr_wakeup_enable.attr, + &dev_attr_clk_enable.attr, + &dev_attr_irq_enable.attr, + &dev_attr_irq.attr, + &dev_attr_screen_status.attr, + &dev_attr_fingerdown_wait.attr, + &dev_attr_vendor.attr, + &dev_attr_vreg_op_cnt.attr, + NULL, +}; + +static const struct attribute_group attribute_group = { + .attrs = attributes, +}; + +static void notification_work(struct work_struct *work) +{ + pr_debug("%s: unblank\n", __func__); + dsi_bridge_interface_enable(FP_UNLOCK_REJECTION_TIMEOUT); +} + +static irqreturn_t fpc1020_irq_handler(int irq, void *handle) +{ + struct fpc1020_data *fpc1020 = handle; + + dev_dbg(fpc1020->dev, "%s\n", __func__); + + if (atomic_read(&fpc1020->wakeup_enabled)) { + __pm_wakeup_event(&fpc1020->ttw_wl, FPC_TTW_HOLD_TIME); + } + + sysfs_notify(&fpc1020->dev->kobj, NULL, dev_attr_irq.attr.name); + if (fpc1020->wait_finger_down && fpc1020->fb_black && + fpc1020->prepared) { + pr_debug("%s enter\n", __func__); + fpc1020->wait_finger_down = false; + schedule_work(&fpc1020->work); + } + + return IRQ_HANDLED; +} + +static int fpc1020_request_named_gpio(struct fpc1020_data *fpc1020, + const char *label, int *gpio) +{ + struct device *dev = fpc1020->dev; + struct device_node *np = dev->of_node; + int rc = of_get_named_gpio(np, label, 0); + + if (rc < 0) { + dev_err(dev, "failed to get '%s'\n", label); + return rc; + } + *gpio = rc; + + rc = devm_gpio_request(dev, *gpio, label); + if (rc) { + dev_err(dev, "failed to request gpio %d\n", *gpio); + return rc; + } + dev_dbg(dev, "%s %d\n", label, *gpio); + + return 0; +} + +static int fpc_fb_notif_callback(struct notifier_block *nb, unsigned long val, + void *data) +{ + struct fpc1020_data *fpc1020 = + container_of(nb, struct fpc1020_data, fb_notifier); + struct fb_event *evdata = data; + unsigned int blank; + + if (!fpc1020) + return 0; + + if (val != DRM_EVENT_BLANK || fpc1020->prepared == false) + return 0; + + pr_debug("[info] %s value = %d\n", __func__, (int)val); + + if (evdata && evdata->data && val == DRM_EVENT_BLANK) { + blank = *(int *)(evdata->data); + switch (blank) { + case DRM_BLANK_POWERDOWN: + fpc1020->fb_black = true; +#ifdef CONFIG_FINGERPRINT_FPC_SCREEN_NOTIFY + __pm_wakeup_event(&fpc1020->screen_wl, + FPC_SCREEN_HOLD_TIME); + sysfs_notify(&fpc1020->dev->kobj, NULL, + dev_attr_screen_status.attr.name); +#endif + break; + case DRM_BLANK_UNBLANK: + fpc1020->fb_black = false; +#ifdef CONFIG_FINGERPRINT_FPC_SCREEN_NOTIFY + __pm_wakeup_event(&fpc1020->screen_wl, + FPC_SCREEN_HOLD_TIME); + sysfs_notify(&fpc1020->dev->kobj, NULL, + dev_attr_screen_status.attr.name); +#endif + break; + default: + pr_debug("%s defalut\n", __func__); + break; + } + } + return NOTIFY_OK; +} + +static struct notifier_block fpc_notif_block = { + .notifier_call = fpc_fb_notif_callback, +}; + +static int fpc1020_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int rc = 0; + size_t i; + + struct device_node *np = dev->of_node; + struct fpc1020_data *fpc1020 = + devm_kzalloc(dev, sizeof(*fpc1020), GFP_KERNEL); + + if (!fpc1020) { + dev_err(dev, + "failed to allocate memory for struct fpc1020_data\n"); + rc = -ENOMEM; + goto exit; + } + + fpc1020->dev = dev; + platform_set_drvdata(pdev, fpc1020); + + if (!np) { + dev_err(dev, "no of node found\n"); + rc = -EINVAL; + goto exit; + } + + fpc1020->fingerprint_pinctrl = devm_pinctrl_get(dev); + if (IS_ERR(fpc1020->fingerprint_pinctrl)) { + if (PTR_ERR(fpc1020->fingerprint_pinctrl) == -EPROBE_DEFER) { + dev_info(dev, "pinctrl not ready\n"); + rc = -EPROBE_DEFER; + goto exit; + } + dev_err(dev, "Target does not use pinctrl\n"); + fpc1020->fingerprint_pinctrl = NULL; + rc = -EINVAL; + goto exit; + } + + for (i = 0; i < ARRAY_SIZE(fpc1020->pinctrl_state); i++) { + const char *n = pctl_names[i]; + struct pinctrl_state *state = + pinctrl_lookup_state(fpc1020->fingerprint_pinctrl, n); + if (IS_ERR(state)) { + dev_err(dev, "cannot find '%s'\n", n); + rc = -EINVAL; + goto exit; + } + dev_info(dev, "found pin control %s\n", n); + fpc1020->pinctrl_state[i] = state; + } + + atomic_set(&fpc1020->wakeup_enabled, 1); + + fpc1020->irqf = IRQF_TRIGGER_RISING | IRQF_ONESHOT | IRQF_NO_SUSPEND; + /* + if (of_property_read_bool(dev->of_node, "fpc,enable-wakeup")) { + fpc1020->irqf |= IRQF_NO_SUSPEND; + device_init_wakeup(dev, 1); + } + */ + mutex_init(&fpc1020->lock); + + wakeup_source_init(&fpc1020->ttw_wl, "fpc_ttw_wl"); + wakeup_source_init(&fpc1020->screen_wl, "fpc_screen_wl"); + + rc = sysfs_create_group(&dev->kobj, &attribute_group); + if (rc) { + dev_err(dev, "could not create sysfs\n"); + goto exit; + } + + if (of_property_read_bool(dev->of_node, "fpc,enable-on-boot")) { + dev_info(dev, "Enabling hardware\n"); + (void)device_prepare(fpc1020, true); + } + + fpc1020->fb_black = false; + fpc1020->wait_finger_down = false; + INIT_WORK(&fpc1020->work, notification_work); + fpc1020->fb_notifier = fpc_notif_block; + drm_register_client(&fpc1020->fb_notifier); + + dev_info(dev, "%s: ok\n", __func__); + +exit: + return rc; +} + +static int fpc1020_remove(struct platform_device *pdev) +{ + struct fpc1020_data *fpc1020 = platform_get_drvdata(pdev); + + drm_unregister_client(&fpc1020->fb_notifier); + sysfs_remove_group(&pdev->dev.kobj, &attribute_group); + mutex_destroy(&fpc1020->lock); + wakeup_source_trash(&fpc1020->ttw_wl); + wakeup_source_trash(&fpc1020->screen_wl); + (void)vreg_setup(fpc1020, "vdd_ana", false); + /* + (void)vreg_setup(fpc1020, "vdd_io", false); + (void)vreg_setup(fpc1020, "vcc_spi", false); + */ + dev_info(&pdev->dev, "%s\n", __func__); + + return 0; +} + +static struct of_device_id fpc1020_of_match[] = { + { + .compatible = "fpc,fpc1020", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, fpc1020_of_match); + +static struct platform_driver fpc1020_driver = { + .driver = { + .name = "fpc1020", + .owner = THIS_MODULE, + .of_match_table = fpc1020_of_match, + }, + .probe = fpc1020_probe, + .remove = fpc1020_remove, +}; + +static int __init fpc1020_init(void) +{ + int rc = platform_driver_register(&fpc1020_driver); + + if (!rc) + pr_info("%s OK\n", __func__); + else + pr_err("%s %d\n", __func__, rc); + + return rc; +} + +static void __exit fpc1020_exit(void) +{ + pr_info("%s\n", __func__); + platform_driver_unregister(&fpc1020_driver); +} + +module_init(fpc1020_init); +module_exit(fpc1020_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Aleksej Makarov"); +MODULE_AUTHOR("Henrik Tillman "); +MODULE_DESCRIPTION("FPC1020 Fingerprint sensor device driver."); diff --git a/drivers/input/fingerprint/goodix_ta/Kconfig b/drivers/input/fingerprint/goodix_ta/Kconfig new file mode 100644 index 000000000000..34b155459ad3 --- /dev/null +++ b/drivers/input/fingerprint/goodix_ta/Kconfig @@ -0,0 +1,10 @@ +config FINGERPRINT_GOODIX_TA + tristate "Finger print card goodix" + depends on INPUT_FINGERPRINT + help + Say Y here to enable support for retrieving self-test reports. + + If unsure, say N. + + To compile this driver as a module, choose M here. + diff --git a/drivers/input/fingerprint/goodix_ta/Makefile b/drivers/input/fingerprint/goodix_ta/Makefile new file mode 100644 index 000000000000..43929c138f64 --- /dev/null +++ b/drivers/input/fingerprint/goodix_ta/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_FINGERPRINT_GOODIX_TA) += gf_spi.o platform.o netlink.o diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.c b/drivers/input/fingerprint/goodix_ta/gf_spi.c new file mode 100644 index 000000000000..1812a5ef5de6 --- /dev/null +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.c @@ -0,0 +1,1077 @@ +/* + * TEE driver for goodix fingerprint sensor + * Copyright (C) 2016 Goodix + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define DEBUG +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#define GOODIX_DRM_INTERFACE_WA + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifndef GOODIX_DRM_INTERFACE_WA +#include +#endif + +#include "gf_spi.h" + +#if defined(USE_SPI_BUS) +#include +#include +#elif defined(USE_PLATFORM_BUS) +#include +#endif + +#define VER_MAJOR 1 +#define VER_MINOR 2 +#define PATCH_LEVEL 1 + +#define WAKELOCK_HOLD_TIME 2000 /* in ms */ +#define FP_UNLOCK_REJECTION_TIMEOUT (WAKELOCK_HOLD_TIME - 500) + +#define GF_SPIDEV_NAME "goodix,fingerprint" +/*device name after register in charater*/ +#define GF_DEV_NAME "goodix_fp" +#define GF_INPUT_NAME "uinput-goodix" /*"goodix_fp" */ + +#define CHRD_DRIVER_NAME "goodix_fp_spi" +#define CLASS_NAME "goodix_fp" + +#define N_SPI_MINORS 32 /* ... up to 256 */ + +static int SPIDEV_MAJOR; + +static DECLARE_BITMAP(minors, N_SPI_MINORS); +static LIST_HEAD(device_list); +static DEFINE_MUTEX(device_list_lock); +static struct wakeup_source fp_wakelock; +static struct gf_dev gf; + +struct gf_key_map maps[] = { + { EV_KEY, GF_KEY_INPUT_HOME }, + { EV_KEY, GF_KEY_INPUT_MENU }, + { EV_KEY, GF_KEY_INPUT_BACK }, + { EV_KEY, GF_KEY_INPUT_POWER }, +#if defined(SUPPORT_NAV_EVENT) + { EV_KEY, GF_NAV_INPUT_UP }, + { EV_KEY, GF_NAV_INPUT_DOWN }, + { EV_KEY, GF_NAV_INPUT_RIGHT }, + { EV_KEY, GF_NAV_INPUT_LEFT }, + { EV_KEY, GF_KEY_INPUT_CAMERA }, + { EV_KEY, GF_NAV_INPUT_CLICK }, + { EV_KEY, GF_NAV_INPUT_DOUBLE_CLICK }, + { EV_KEY, GF_NAV_INPUT_LONG_PRESS }, + { EV_KEY, GF_NAV_INPUT_HEAVY }, +#endif +}; + +static void gf_enable_irq(struct gf_dev *gf_dev) +{ + if (gf_dev->irq_enabled) { + pr_warn("IRQ has been enabled.\n"); + } else { + enable_irq(gf_dev->irq); + gf_dev->irq_enabled = 1; + } +} + +static void gf_disable_irq(struct gf_dev *gf_dev) +{ + if (gf_dev->irq_enabled) { + gf_dev->irq_enabled = 0; + disable_irq(gf_dev->irq); + } else { + pr_warn("IRQ has been disabled.\n"); + } +} + +#ifdef AP_CONTROL_CLK +static long spi_clk_max_rate(struct clk *clk, unsigned long rate) +{ + long lowest_available, nearest_low, step_size, cur; + long step_direction = -1; + long guess = rate; + int max_steps = 10; + cur = clk_round_rate(clk, rate); + + if (cur == rate) { + return rate; + } + + /* if we got here then: cur > rate */ + lowest_available = clk_round_rate(clk, 0); + + if (lowest_available > rate) { + return -EINVAL; + } + + step_size = (rate - lowest_available) >> 1; + nearest_low = lowest_available; + + while (max_steps-- && step_size) { + guess += step_size * step_direction; + cur = clk_round_rate(clk, guess); + + if ((cur < rate) && (cur > nearest_low)) { + nearest_low = cur; + } + + /* + * if we stepped too far, then start stepping in the other + * direction with half the step size + */ + if (((cur > rate) && (step_direction > 0)) || + ((cur < rate) && (step_direction < 0))) { + step_direction = -step_direction; + step_size >>= 1; + } + } + + return nearest_low; +} + +static void spi_clock_set(struct gf_dev *gf_dev, int speed) +{ + long rate; + int rc; + rate = spi_clk_max_rate(gf_dev->core_clk, speed); + + if (rate < 0) { + pr_debug("%s: no match found for requested clock frequency:%d", + __func__, speed); + return; + } + + rc = clk_set_rate(gf_dev->core_clk, rate); +} + +static int gfspi_ioctl_clk_init(struct gf_dev *data) +{ + pr_debug("%s: enter\n", __func__); + data->clk_enabled = 0; + data->core_clk = clk_get(&data->spi->dev, "core_clk"); + + if (IS_ERR_OR_NULL(data->core_clk)) { + pr_err("%s: fail to get core_clk\n", __func__); + return -EPERM; + } + + data->iface_clk = clk_get(&data->spi->dev, "iface_clk"); + + if (IS_ERR_OR_NULL(data->iface_clk)) { + pr_err("%s: fail to get iface_clk\n", __func__); + clk_put(data->core_clk); + data->core_clk = NULL; + return -ENOENT; + } + + return 0; +} + +static int gfspi_ioctl_clk_enable(struct gf_dev *data) +{ + int err; + pr_debug("%s: enter\n", __func__); + + if (data->clk_enabled) { + return 0; + } + + err = clk_prepare_enable(data->core_clk); + + if (err) { + pr_err("%s: fail to enable core_clk\n", __func__); + return -EPERM; + } + + err = clk_prepare_enable(data->iface_clk); + + if (err) { + pr_err("%s: fail to enable iface_clk\n", __func__); + clk_disable_unprepare(data->core_clk); + return -ENOENT; + } + + data->clk_enabled = 1; + return 0; +} + +static int gfspi_ioctl_clk_disable(struct gf_dev *data) +{ + pr_debug("%s: enter\n", __func__); + + if (!data->clk_enabled) { + return 0; + } + + clk_disable_unprepare(data->core_clk); + clk_disable_unprepare(data->iface_clk); + data->clk_enabled = 0; + return 0; +} + +static int gfspi_ioctl_clk_uninit(struct gf_dev *data) +{ + pr_debug("%s: enter\n", __func__); + + if (data->clk_enabled) { + gfspi_ioctl_clk_disable(data); + } + + if (!IS_ERR_OR_NULL(data->core_clk)) { + clk_put(data->core_clk); + data->core_clk = NULL; + } + + if (!IS_ERR_OR_NULL(data->iface_clk)) { + clk_put(data->iface_clk); + data->iface_clk = NULL; + } + + return 0; +} +#endif + +static void nav_event_input(struct gf_dev *gf_dev, gf_nav_event_t nav_event) +{ + uint32_t nav_input = 0; + + switch (nav_event) { + case GF_NAV_FINGER_DOWN: + pr_debug("%s nav finger down\n", __func__); + break; + + case GF_NAV_FINGER_UP: + pr_debug("%s nav finger up\n", __func__); + break; + + case GF_NAV_DOWN: + nav_input = GF_NAV_INPUT_DOWN; + pr_debug("%s nav down\n", __func__); + break; + + case GF_NAV_UP: + nav_input = GF_NAV_INPUT_UP; + pr_debug("%s nav up\n", __func__); + break; + + case GF_NAV_LEFT: + nav_input = GF_NAV_INPUT_LEFT; + pr_debug("%s nav left\n", __func__); + break; + + case GF_NAV_RIGHT: + nav_input = GF_NAV_INPUT_RIGHT; + pr_debug("%s nav right\n", __func__); + break; + + case GF_NAV_CLICK: + nav_input = GF_NAV_INPUT_CLICK; + pr_debug("%s nav click\n", __func__); + break; + + case GF_NAV_HEAVY: + nav_input = GF_NAV_INPUT_HEAVY; + pr_debug("%s nav heavy\n", __func__); + break; + + case GF_NAV_LONG_PRESS: + nav_input = GF_NAV_INPUT_LONG_PRESS; + pr_debug("%s nav long press\n", __func__); + break; + + case GF_NAV_DOUBLE_CLICK: + nav_input = GF_NAV_INPUT_DOUBLE_CLICK; + pr_debug("%s nav double click\n", __func__); + break; + + default: + pr_warn("%s unknown nav event: %d\n", __func__, nav_event); + break; + } + + if ((nav_event != GF_NAV_FINGER_DOWN) && + (nav_event != GF_NAV_FINGER_UP)) { + input_report_key(gf_dev->input, nav_input, 1); + input_sync(gf_dev->input); + input_report_key(gf_dev->input, nav_input, 0); + input_sync(gf_dev->input); + } +} + +static void gf_kernel_key_input(struct gf_dev *gf_dev, struct gf_key *gf_key) +{ + uint32_t key_input = 0; + + if (GF_KEY_HOME == gf_key->key) { + key_input = GF_KEY_INPUT_HOME; + } else if (GF_KEY_POWER == gf_key->key) { + key_input = GF_KEY_INPUT_POWER; + } else if (GF_KEY_CAMERA == gf_key->key) { + key_input = GF_KEY_INPUT_CAMERA; + } else { + /* add special key define */ + key_input = gf_key->key; + } + + pr_debug("%s: received key event[%d], key=%d, value=%d\n", __func__, + key_input, gf_key->key, gf_key->value); + + if ((GF_KEY_POWER == gf_key->key || GF_KEY_CAMERA == gf_key->key) && + (gf_key->value == 1)) { + input_report_key(gf_dev->input, key_input, 1); + input_sync(gf_dev->input); + input_report_key(gf_dev->input, key_input, 0); + input_sync(gf_dev->input); + } + + if (GF_KEY_HOME == gf_key->key) { + input_report_key(gf_dev->input, key_input, gf_key->value); + input_sync(gf_dev->input); + } +} + +static long gf_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct gf_dev *gf_dev = &gf; + struct gf_key gf_key; +#if defined(SUPPORT_NAV_EVENT) + gf_nav_event_t nav_event = GF_NAV_NONE; +#endif + int retval = 0; + u8 netlink_route = NETLINK_TEST; + struct gf_ioc_chip_info info; + + if (_IOC_TYPE(cmd) != GF_IOC_MAGIC) { + return -ENODEV; + } + + if (_IOC_DIR(cmd) & _IOC_READ) { + retval = !access_ok(VERIFY_WRITE, (void __user *)arg, + _IOC_SIZE(cmd)); + } else if (_IOC_DIR(cmd) & _IOC_WRITE) { + retval = !access_ok(VERIFY_READ, (void __user *)arg, + _IOC_SIZE(cmd)); + } + + if (retval) { + return -EFAULT; + } + + if (gf_dev->device_available == 0) { + if ((cmd == GF_IOC_ENABLE_POWER) || + (cmd == GF_IOC_DISABLE_POWER)) { + pr_debug("power cmd\n"); + } else { + pr_debug( + "get cmd %d, but sensor is power off currently.\n", + _IOC_NR(cmd)); + return -ENODEV; + } + } + + switch (cmd) { + case GF_IOC_INIT: + pr_debug("%s GF_IOC_INIT\n", __func__); + + if (copy_to_user((void __user *)arg, (void *)&netlink_route, + sizeof(u8))) { + retval = -EFAULT; + break; + } + + break; + + case GF_IOC_EXIT: + pr_debug("%s GF_IOC_EXIT\n", __func__); + break; + + case GF_IOC_DISABLE_IRQ: + pr_debug("%s GF_IOC_DISABEL_IRQ\n", __func__); + gf_disable_irq(gf_dev); + break; + + case GF_IOC_ENABLE_IRQ: + pr_debug("%s GF_IOC_ENABLE_IRQ\n", __func__); + gf_enable_irq(gf_dev); + break; + + case GF_IOC_RESET: + pr_debug("%s GF_IOC_RESET.\n", __func__); + gf_hw_reset(gf_dev, 3); + break; + + case GF_IOC_INPUT_KEY_EVENT: + if (copy_from_user(&gf_key, (struct gf_key *)arg, + sizeof(struct gf_key))) { + pr_debug( + "Failed to copy input key event from user to kernel\n"); + retval = -EFAULT; + break; + } + + gf_kernel_key_input(gf_dev, &gf_key); + break; +#if defined(SUPPORT_NAV_EVENT) + + case GF_IOC_NAV_EVENT: + pr_debug("%s GF_IOC_NAV_EVENT\n", __func__); + + if (copy_from_user(&nav_event, (gf_nav_event_t *)arg, + sizeof(gf_nav_event_t))) { + pr_debug( + "Failed to copy nav event from user to kernel\n"); + retval = -EFAULT; + break; + } + + nav_event_input(gf_dev, nav_event); + break; +#endif + + case GF_IOC_ENABLE_SPI_CLK: +#ifdef AP_CONTROL_CLK + gfspi_ioctl_clk_enable(gf_dev); +#endif + break; + + case GF_IOC_DISABLE_SPI_CLK: +#ifdef AP_CONTROL_CLK + gfspi_ioctl_clk_disable(gf_dev); +#endif + break; + + case GF_IOC_ENABLE_POWER: + pr_debug("%s GF_IOC_ENABLE_POWER\n", __func__); + + if (gf_dev->device_available == 1) { + pr_debug("Sensor has already powered-on.\n"); + } else { + gf_power_on(gf_dev); + } + + gf_dev->device_available = 1; + break; + + case GF_IOC_DISABLE_POWER: + pr_debug("%s GF_IOC_DISABLE_POWER\n", __func__); + + if (gf_dev->device_available == 0) { + pr_debug("Sensor has already powered-off.\n"); + } else { + gf_power_off(gf_dev); + } + + gf_dev->device_available = 0; + break; + + case GF_IOC_ENTER_SLEEP_MODE: + pr_debug("%s GF_IOC_ENTER_SLEEP_MODE\n", __func__); + break; + + case GF_IOC_GET_FW_INFO: + pr_debug("%s GF_IOC_GET_FW_INFO\n", __func__); + break; + + case GF_IOC_REMOVE: + pr_debug("%s GF_IOC_REMOVE\n", __func__); + break; + + case GF_IOC_CHIP_INFO: + pr_debug("%s GF_IOC_CHIP_INFO\n", __func__); + + if (copy_from_user(&info, (struct gf_ioc_chip_info *)arg, + sizeof(struct gf_ioc_chip_info))) { + retval = -EFAULT; + break; + } + + pr_debug("vendor_id : 0x%x\n", info.vendor_id); + pr_debug("mode : 0x%x\n", info.mode); + pr_debug("operation: 0x%x\n", info.operation); + break; + + default: + pr_warn("unsupport cmd:0x%x\n", cmd); + break; + } + + return retval; +} + +#ifdef CONFIG_COMPAT +static long gf_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return gf_ioctl(filp, cmd, (unsigned long)compat_ptr(arg)); +} +#endif /*CONFIG_COMPAT*/ + +#ifndef GOODIX_DRM_INTERFACE_WA +static void notification_work(struct work_struct *work) +{ + pr_debug("%s unblank\n", __func__); + dsi_bridge_interface_enable(FP_UNLOCK_REJECTION_TIMEOUT); +} +#endif + +static irqreturn_t gf_irq(int irq, void *handle) +{ + struct gf_dev *gf_dev = &gf; +#if defined(GF_NETLINK_ENABLE) + char temp[4] = { 0x0 }; + uint32_t key_input = 0; + temp[0] = GF_NET_EVENT_IRQ; + pr_debug("%s enter\n", __func__); + __pm_wakeup_event(&fp_wakelock, WAKELOCK_HOLD_TIME); + sendnlmsg(temp); + + if ((gf_dev->wait_finger_down == true) && + (gf_dev->device_available == 1) && (gf_dev->fb_black == 1)) { + key_input = KEY_RIGHT; + input_report_key(gf_dev->input, key_input, 1); + input_sync(gf_dev->input); + input_report_key(gf_dev->input, key_input, 0); + input_sync(gf_dev->input); + gf_dev->wait_finger_down = false; + schedule_work(&gf_dev->work); + } + +#elif defined(GF_FASYNC) + struct gf_dev *gf_dev = &gf; + + if (gf_dev->async) { + kill_fasync(&gf_dev->async, SIGIO, POLL_IN); + } + +#endif + return IRQ_HANDLED; +} + +static int gf_open(struct inode *inode, struct file *filp) +{ + struct gf_dev *gf_dev; + int status = -ENXIO; + int rc = 0; + int err = 0; + mutex_lock(&device_list_lock); + list_for_each_entry(gf_dev, &device_list, device_entry) { + if (gf_dev->devt == inode->i_rdev) { + pr_debug("Found\n"); + status = 0; + break; + } + } +#ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL + pr_info("Try to enable fp_vdd_vreg\n"); + gf_dev->vreg = regulator_get(&gf_dev->spi->dev, "fp_vdd_vreg"); + + if (gf_dev->vreg == NULL) { + dev_err(&gf_dev->spi->dev, + "fp_vdd_vreg regulator get failed!\n"); + mutex_unlock(&device_list_lock); + return -EPERM; + } + + if (regulator_is_enabled(gf_dev->vreg)) { + pr_info("fp_vdd_vreg is already enabled!\n"); + } else { + rc = regulator_enable(gf_dev->vreg); + + if (rc) { + dev_err(&gf_dev->spi->dev, + "error enabling fp_vdd_vreg!\n"); + regulator_put(gf_dev->vreg); + gf_dev->vreg = NULL; + mutex_unlock(&device_list_lock); + return -EPERM; + } + } + + pr_info("fp_vdd_vreg is enabled!\n"); +#endif + + if (status == 0) { + rc = gpio_request(gf_dev->reset_gpio, "goodix_reset"); + + if (rc) { + dev_err(&gf_dev->spi->dev, + "Failed to request RESET GPIO. rc = %d\n", rc); + mutex_unlock(&device_list_lock); + err = -EPERM; + goto open_error1; + } + + gpio_direction_output(gf_dev->reset_gpio, 0); + rc = gpio_request(gf_dev->irq_gpio, "goodix_irq"); + + if (rc) { + dev_err(&gf_dev->spi->dev, + "Failed to request IRQ GPIO. rc = %d\n", rc); + mutex_unlock(&device_list_lock); + err = -EPERM; + goto open_error2; + } + + gpio_direction_input(gf_dev->irq_gpio); + rc = request_threaded_irq(gf_dev->irq, NULL, gf_irq, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "gf", gf_dev); + + if (!rc) { + enable_irq_wake(gf_dev->irq); + gf_dev->irq_enabled = 1; + gf_disable_irq(gf_dev); + } else { + err = -EPERM; + goto open_error3; + } + + gf_dev->users++; + filp->private_data = gf_dev; + nonseekable_open(inode, filp); + pr_debug("Succeed to open device. irq = %d\n", gf_dev->irq); + } else { + pr_debug("No device for minor %d\n", iminor(inode)); + } + + mutex_unlock(&device_list_lock); + return status; +open_error3: + gpio_free(gf_dev->irq_gpio); +open_error2: + gpio_free(gf_dev->reset_gpio); +open_error1: + return err; +} + +#ifdef GF_FASYNC +static int gf_fasync(int fd, struct file *filp, int mode) +{ + struct gf_dev *gf_dev = filp->private_data; + int ret; + ret = fasync_helper(fd, filp, mode, &gf_dev->async); + pr_debug("ret = %d\n", ret); + return ret; +} +#endif + +static int gf_release(struct inode *inode, struct file *filp) +{ + struct gf_dev *gf_dev; + int status = 0; + pr_debug("%s\n", __func__); + mutex_lock(&device_list_lock); + gf_dev = filp->private_data; + filp->private_data = NULL; + /* + *Disable fp_vdd_vreg regulator + */ +#ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL + pr_info("disable fp_vdd_vreg!\n"); + + if (regulator_is_enabled(gf_dev->vreg)) { + regulator_disable(gf_dev->vreg); + regulator_put(gf_dev->vreg); + gf_dev->vreg = NULL; + } + +#endif + gf_dev->users--; + + if (!gf_dev->users) { + pr_debug("disble_irq. irq = %d\n", gf_dev->irq); + gf_disable_irq(gf_dev); + /*power off the sensor*/ + gf_dev->device_available = 0; + free_irq(gf_dev->irq, gf_dev); + gpio_free(gf_dev->irq_gpio); + gpio_free(gf_dev->reset_gpio); + gf_power_off(gf_dev); + } + + mutex_unlock(&device_list_lock); + return status; +} + +static const struct file_operations gf_fops = { + .owner = THIS_MODULE, + /* REVISIT switch to aio primitives, so that userspace + * gets more complete API coverage. It'll simplify things + * too, except for the locking. + */ + .unlocked_ioctl = gf_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = gf_compat_ioctl, +#endif /*CONFIG_COMPAT*/ + .open = gf_open, + .release = gf_release, +#ifdef GF_FASYNC + .fasync = gf_fasync, +#endif +}; + +#ifndef GOODIX_DRM_INTERFACE_WA +static int goodix_fb_state_chg_callback(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct gf_dev *gf_dev; + struct fb_event *evdata = data; + unsigned int blank; + char temp[4] = { 0x0 }; + + if (val != DRM_EVENT_BLANK) { + return 0; + } + + pr_debug( + "[info] %s go to the goodix_fb_state_chg_callback value = %d\n", + __func__, (int)val); + gf_dev = container_of(nb, struct gf_dev, notifier); + + if (evdata && evdata->data && val == DRM_EVENT_BLANK && gf_dev) { + blank = *(int *)(evdata->data); + + switch (blank) { + case DRM_BLANK_POWERDOWN: + if (gf_dev->device_available == 1) { + gf_dev->fb_black = 1; + gf_dev->wait_finger_down = true; +#if defined(GF_NETLINK_ENABLE) + temp[0] = GF_NET_EVENT_FB_BLACK; + sendnlmsg(temp); +#elif defined(GF_FASYNC) + + if (gf_dev->async) { + kill_fasync(&gf_dev->async, SIGIO, + POLL_IN); + } + +#endif + } + + break; + + case DRM_BLANK_UNBLANK: + if (gf_dev->device_available == 1) { + gf_dev->fb_black = 0; +#if defined(GF_NETLINK_ENABLE) + temp[0] = GF_NET_EVENT_FB_UNBLACK; + sendnlmsg(temp); +#elif defined(GF_FASYNC) + + if (gf_dev->async) { + kill_fasync(&gf_dev->async, SIGIO, + POLL_IN); + } + +#endif + } + + break; + + default: + pr_debug("%s defalut\n", __func__); + break; + } + } + + return NOTIFY_OK; +} + +static struct notifier_block goodix_noti_block = { + .notifier_call = goodix_fb_state_chg_callback, +}; +#endif + +static struct class *gf_class; +#if defined(USE_SPI_BUS) +static int gf_probe(struct spi_device *spi) +#elif defined(USE_PLATFORM_BUS) +static int gf_probe(struct platform_device *pdev) +#endif +{ + struct gf_dev *gf_dev = &gf; + int status = -EINVAL; + unsigned long minor; + int i; + /* Initialize the driver data */ + INIT_LIST_HEAD(&gf_dev->device_entry); +#if defined(USE_SPI_BUS) + gf_dev->spi = spi; +#elif defined(USE_PLATFORM_BUS) + gf_dev->spi = pdev; +#endif + gf_dev->irq_gpio = -EINVAL; + gf_dev->reset_gpio = -EINVAL; + gf_dev->pwr_gpio = -EINVAL; + gf_dev->device_available = 0; + gf_dev->fb_black = 0; + gf_dev->wait_finger_down = false; +#ifndef GOODIX_DRM_INTERFACE_WA + INIT_WORK(&gf_dev->work, notification_work); +#endif + + if (gf_parse_dts(gf_dev)) { + goto error_hw; + } + + /* If we can allocate a minor number, hook up this device. + * Reusing minors is fine so long as udev or mdev is working. + */ + mutex_lock(&device_list_lock); + minor = find_first_zero_bit(minors, N_SPI_MINORS); + + if (minor < N_SPI_MINORS) { + struct device *dev; + gf_dev->devt = MKDEV(SPIDEV_MAJOR, minor); + dev = device_create(gf_class, &gf_dev->spi->dev, gf_dev->devt, + gf_dev, GF_DEV_NAME); + status = IS_ERR(dev) ? PTR_ERR(dev) : 0; + } else { + dev_dbg(&gf_dev->spi->dev, "no minor number available!\n"); + status = -ENODEV; + mutex_unlock(&device_list_lock); + goto error_hw; + } + + if (status == 0) { + set_bit(minor, minors); + list_add(&gf_dev->device_entry, &device_list); + } else { + gf_dev->devt = 0; + } + + mutex_unlock(&device_list_lock); + + if (status == 0) { + /*input device subsystem */ + gf_dev->input = input_allocate_device(); + + if (gf_dev->input == NULL) { + pr_err("%s, failed to allocate input device\n", + __func__); + status = -ENOMEM; + goto error_dev; + } + + for (i = 0; i < ARRAY_SIZE(maps); i++) { + input_set_capability(gf_dev->input, maps[i].type, + maps[i].code); + } + + gf_dev->input->name = GF_INPUT_NAME; + status = input_register_device(gf_dev->input); + + if (status) { + pr_err("failed to register input device\n"); + goto error_input; + } + } + +#ifdef AP_CONTROL_CLK + pr_debug("Get the clk resource.\n"); + + /* Enable spi clock */ + if (gfspi_ioctl_clk_init(gf_dev)) { + goto gfspi_probe_clk_init_failed; + } + + if (gfspi_ioctl_clk_enable(gf_dev)) { + goto gfspi_probe_clk_enable_failed; + } + + spi_clock_set(gf_dev, 1000000); +#endif +#ifndef GOODIX_DRM_INTERFACE_WA + gf_dev->notifier = goodix_noti_block; + drm_register_client(&gf_dev->notifier); +#endif + gf_dev->irq = gf_irq_num(gf_dev); + wakeup_source_init(&fp_wakelock, "fp_wakelock"); + pr_debug("version V%d.%d.%02d\n", VER_MAJOR, VER_MINOR, PATCH_LEVEL); + return status; +#ifdef AP_CONTROL_CLK +gfspi_probe_clk_enable_failed: + gfspi_ioctl_clk_uninit(gf_dev); +gfspi_probe_clk_init_failed: +#endif + input_unregister_device(gf_dev->input); +error_input: + + if (gf_dev->input != NULL) { + input_free_device(gf_dev->input); + } + +error_dev: + + if (gf_dev->devt != 0) { + pr_debug("Err: status = %d\n", status); + mutex_lock(&device_list_lock); + list_del(&gf_dev->device_entry); + device_destroy(gf_class, gf_dev->devt); + clear_bit(MINOR(gf_dev->devt), minors); + mutex_unlock(&device_list_lock); + } + +error_hw: + gf_cleanup(gf_dev); + gf_dev->device_available = 0; + return status; +} + +#if defined(USE_SPI_BUS) +static int gf_remove(struct spi_device *spi) +#elif defined(USE_PLATFORM_BUS) +static int gf_remove(struct platform_device *pdev) +#endif +{ + struct gf_dev *gf_dev = &gf; + wakeup_source_trash(&fp_wakelock); + + /* make sure ops on existing fds can abort cleanly */ + if (gf_dev->irq) { + free_irq(gf_dev->irq, gf_dev); + } + + if (gf_dev->input != NULL) { + input_unregister_device(gf_dev->input); + } + + input_free_device(gf_dev->input); + /* prevent new opens */ + mutex_lock(&device_list_lock); + list_del(&gf_dev->device_entry); + device_destroy(gf_class, gf_dev->devt); + clear_bit(MINOR(gf_dev->devt), minors); + + if (gf_dev->users == 0) { + gf_cleanup(gf_dev); + } + +#ifndef GOODIX_DRM_INTERFACE_WA + drm_unregister_client(&gf_dev->notifier); +#endif + mutex_unlock(&device_list_lock); + return 0; +} + +static struct of_device_id gx_match_table[] = { + { .compatible = GF_SPIDEV_NAME }, + {}, +}; + +#if defined(USE_SPI_BUS) +static struct spi_driver gf_driver = { +#elif defined(USE_PLATFORM_BUS) +static struct platform_driver gf_driver = { +#endif + .driver = { + .name = GF_DEV_NAME, + .owner = THIS_MODULE, + .of_match_table = gx_match_table, + }, + .probe = gf_probe, + .remove = gf_remove, +}; + +static int __init gf_init(void) +{ + int status; + /* Claim our 256 reserved device numbers. Then register a class + * that will key udev/mdev to add/remove /dev nodes. Last, register + * the driver which manages those device numbers. + */ + BUILD_BUG_ON(N_SPI_MINORS > 256); + status = register_chrdev(SPIDEV_MAJOR, CHRD_DRIVER_NAME, &gf_fops); + + if (status < 0) { + pr_warn("Failed to register char device!\n"); + return status; + } + + SPIDEV_MAJOR = status; + gf_class = class_create(THIS_MODULE, CLASS_NAME); + + if (IS_ERR(gf_class)) { + unregister_chrdev(SPIDEV_MAJOR, gf_driver.driver.name); + pr_warn("Failed to create class.\n"); + return PTR_ERR(gf_class); + } + +#if defined(USE_PLATFORM_BUS) + status = platform_driver_register(&gf_driver); +#elif defined(USE_SPI_BUS) + status = spi_register_driver(&gf_driver); +#endif + + if (status < 0) { + class_destroy(gf_class); + unregister_chrdev(SPIDEV_MAJOR, gf_driver.driver.name); + pr_warn("Failed to register SPI driver.\n"); + } + +#ifdef GF_NETLINK_ENABLE + netlink_init(); +#endif + pr_debug("status = 0x%x\n", status); + return 0; +} +module_init(gf_init); + +static void __exit gf_exit(void) +{ +#ifdef GF_NETLINK_ENABLE + netlink_exit(); +#endif +#if defined(USE_PLATFORM_BUS) + platform_driver_unregister(&gf_driver); +#elif defined(USE_SPI_BUS) + spi_unregister_driver(&gf_driver); +#endif + class_destroy(gf_class); + unregister_chrdev(SPIDEV_MAJOR, gf_driver.driver.name); +} +module_exit(gf_exit); + +MODULE_AUTHOR("Jiangtao Yi, "); +MODULE_AUTHOR("Jandy Gou, "); +MODULE_DESCRIPTION("goodix fingerprint sensor device driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.h b/drivers/input/fingerprint/goodix_ta/gf_spi.h new file mode 100644 index 000000000000..3ea8a55b40fc --- /dev/null +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.h @@ -0,0 +1,160 @@ +/* + * driver definition for sensor driver + * + * Coypright (c) 2017 Goodix + */ +#ifndef __GF_SPI_H +#define __GF_SPI_H + +#include +#include +/**********************************************************/ +enum FP_MODE { + GF_IMAGE_MODE = 0, + GF_KEY_MODE, + GF_SLEEP_MODE, + GF_FF_MODE, + GF_DEBUG_MODE = 0x56 +}; + +#define SUPPORT_NAV_EVENT + +#if defined(SUPPORT_NAV_EVENT) +#define GF_NAV_INPUT_UP KEY_UP +#define GF_NAV_INPUT_DOWN KEY_DOWN +#define GF_NAV_INPUT_LEFT KEY_LEFT +#define GF_NAV_INPUT_RIGHT KEY_RIGHT +#define GF_NAV_INPUT_CLICK KEY_VOLUMEDOWN +#define GF_NAV_INPUT_DOUBLE_CLICK KEY_VOLUMEUP +#define GF_NAV_INPUT_LONG_PRESS KEY_SEARCH +#define GF_NAV_INPUT_HEAVY KEY_CHAT +#endif + +#define GF_KEY_INPUT_HOME KEY_HOME +#define GF_KEY_INPUT_MENU KEY_MENU +#define GF_KEY_INPUT_BACK KEY_BACK +#define GF_KEY_INPUT_POWER KEY_POWER +#define GF_KEY_INPUT_CAMERA KEY_CAMERA + +#if defined(SUPPORT_NAV_EVENT) +typedef enum gf_nav_event { + GF_NAV_NONE = 0, + GF_NAV_FINGER_UP, + GF_NAV_FINGER_DOWN, + GF_NAV_UP, + GF_NAV_DOWN, + GF_NAV_LEFT, + GF_NAV_RIGHT, + GF_NAV_CLICK, + GF_NAV_HEAVY, + GF_NAV_LONG_PRESS, + GF_NAV_DOUBLE_CLICK, +} gf_nav_event_t; +#endif + +typedef enum gf_key_event { + GF_KEY_NONE = 0, + GF_KEY_HOME, + GF_KEY_POWER, + GF_KEY_MENU, + GF_KEY_BACK, + GF_KEY_CAMERA, +} gf_key_event_t; + +struct gf_key { + enum gf_key_event key; + uint32_t value; /* key down = 1, key up = 0 */ +}; + +struct gf_key_map { + unsigned int type; + unsigned int code; +}; + +struct gf_ioc_chip_info { + unsigned char vendor_id; + unsigned char mode; + unsigned char operation; + unsigned char reserved[5]; +}; + +#define GF_IOC_MAGIC 'g' /*define magic number*/ +#define GF_IOC_INIT _IOR(GF_IOC_MAGIC, 0, uint8_t) +#define GF_IOC_EXIT _IO(GF_IOC_MAGIC, 1) +#define GF_IOC_RESET _IO(GF_IOC_MAGIC, 2) +#define GF_IOC_ENABLE_IRQ _IO(GF_IOC_MAGIC, 3) +#define GF_IOC_DISABLE_IRQ _IO(GF_IOC_MAGIC, 4) +#define GF_IOC_ENABLE_SPI_CLK _IOW(GF_IOC_MAGIC, 5, uint32_t) +#define GF_IOC_DISABLE_SPI_CLK _IO(GF_IOC_MAGIC, 6) +#define GF_IOC_ENABLE_POWER _IO(GF_IOC_MAGIC, 7) +#define GF_IOC_DISABLE_POWER _IO(GF_IOC_MAGIC, 8) +#define GF_IOC_INPUT_KEY_EVENT _IOW(GF_IOC_MAGIC, 9, struct gf_key) +#define GF_IOC_ENTER_SLEEP_MODE _IO(GF_IOC_MAGIC, 10) +#define GF_IOC_GET_FW_INFO _IOR(GF_IOC_MAGIC, 11, uint8_t) +#define GF_IOC_REMOVE _IO(GF_IOC_MAGIC, 12) +#define GF_IOC_CHIP_INFO _IOW(GF_IOC_MAGIC, 13, struct gf_ioc_chip_info) + +#if defined(SUPPORT_NAV_EVENT) +#define GF_IOC_NAV_EVENT _IOW(GF_IOC_MAGIC, 14, gf_nav_event_t) +#define GF_IOC_MAXNR 15 /* THIS MACRO IS NOT USED NOW... */ +#else +#define GF_IOC_MAXNR 14 /* THIS MACRO IS NOT USED NOW... */ +#endif + +/*#define AP_CONTROL_CLK 1*/ +#define USE_PLATFORM_BUS 1 +/*#define USE_SPI_BUS 1*/ +/*#define GF_FASYNC 1*/ /*If support fasync mechanism.*/ +#define GF_PW_CTL 1 +#define GF_NETLINK_ENABLE 1 +#define GF_NET_EVENT_IRQ 1 +#define GF_NET_EVENT_FB_BLACK 2 +#define GF_NET_EVENT_FB_UNBLACK 3 +#define NETLINK_TEST 25 + +struct gf_dev { + dev_t devt; + struct list_head device_entry; +#if defined(USE_SPI_BUS) + struct spi_device *spi; +#elif defined(USE_PLATFORM_BUS) + struct platform_device *spi; +#endif + struct clk *core_clk; + struct clk *iface_clk; + + struct input_dev *input; + /* buffer is NULL unless this device is open (users > 0) */ + unsigned users; + signed irq_gpio; + signed reset_gpio; + signed pwr_gpio; + int irq; + int irq_enabled; + int clk_enabled; +#ifdef GF_FASYNC + struct fasync_struct *async; +#endif + struct notifier_block notifier; + char device_available; + char fb_black; + char wait_finger_down; + struct work_struct work; +#ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL + struct regulator *vreg; +#endif +}; + +int gf_parse_dts(struct gf_dev *gf_dev); +void gf_cleanup(struct gf_dev *gf_dev); + +int gf_power_on(struct gf_dev *gf_dev); +int gf_power_off(struct gf_dev *gf_dev); + +int gf_hw_reset(struct gf_dev *gf_dev, unsigned int delay_ms); +int gf_irq_num(struct gf_dev *gf_dev); + +void sendnlmsg(char *message); +int netlink_init(void); +void netlink_exit(void); +#endif /*__GF_SPI_H*/ diff --git a/drivers/input/fingerprint/goodix_ta/netlink.c b/drivers/input/fingerprint/goodix_ta/netlink.c new file mode 100644 index 000000000000..a38d66b73937 --- /dev/null +++ b/drivers/input/fingerprint/goodix_ta/netlink.c @@ -0,0 +1,97 @@ +/* + * netlink interface + * + * Copyright (c) 2017 Goodix + * Copyright (C) 2019 XiaoMi, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +#define NETLINK_TEST 25 +#define MAX_MSGSIZE 32 +int stringlength(char *s); +void sendnlmsg(char *message); +static int pid = -1; +struct sock *nl_sk = NULL; + +void sendnlmsg(char *message) +{ + struct sk_buff *skb_1; + struct nlmsghdr *nlh; + int len = NLMSG_SPACE(MAX_MSGSIZE); + int slen = 0; + int ret = 0; + + if (!message || !nl_sk || !pid) { + return; + } + + skb_1 = alloc_skb(len, GFP_KERNEL); + + if (!skb_1) { + pr_err("alloc_skb error\n"); + return; + } + + slen = strlen(message); + nlh = nlmsg_put(skb_1, 0, 0, 0, MAX_MSGSIZE, 0); + NETLINK_CB(skb_1).portid = 0; + NETLINK_CB(skb_1).dst_group = 0; + message[slen] = '\0'; + memcpy(NLMSG_DATA(nlh), message, slen + 1); + ret = netlink_unicast(nl_sk, skb_1, pid, MSG_DONTWAIT); + + if (!ret) { + /*kfree_skb(skb_1);*/ + pr_err("send msg from kernel to usespace failed ret 0x%x\n", + ret); + } +} + +void nl_data_ready(struct sk_buff *__skb) +{ + struct sk_buff *skb; + struct nlmsghdr *nlh; + char str[100]; + skb = skb_get(__skb); + + if (skb->len >= NLMSG_SPACE(0)) { + nlh = nlmsg_hdr(skb); + memcpy(str, NLMSG_DATA(nlh), sizeof(str)); + pid = nlh->nlmsg_pid; + kfree_skb(skb); + } +} + +int netlink_init(void) +{ + struct netlink_kernel_cfg netlink_cfg; + memset(&netlink_cfg, 0, sizeof(struct netlink_kernel_cfg)); + netlink_cfg.groups = 0; + netlink_cfg.flags = 0; + netlink_cfg.input = nl_data_ready; + netlink_cfg.cb_mutex = NULL; + nl_sk = netlink_kernel_create(&init_net, NETLINK_TEST, &netlink_cfg); + + if (!nl_sk) { + pr_err("create netlink socket error\n"); + return 1; + } + + return 0; +} + +void netlink_exit(void) +{ + if (nl_sk != NULL) { + netlink_kernel_release(nl_sk); + nl_sk = NULL; + } + + pr_info("self module exited\n"); +} diff --git a/drivers/input/fingerprint/goodix_ta/platform.c b/drivers/input/fingerprint/goodix_ta/platform.c new file mode 100644 index 000000000000..b3ae8a663596 --- /dev/null +++ b/drivers/input/fingerprint/goodix_ta/platform.c @@ -0,0 +1,150 @@ +/* + * platform indepent driver interface + * + * Coypritht (c) 2017 Goodix + */ +#define DEBUG +#define pr_fmt(fmt) "gf_platform: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "gf_spi.h" + +#if defined(USE_SPI_BUS) +#include +#include +#elif defined(USE_PLATFORM_BUS) +#include +#endif + +int gf_parse_dts(struct gf_dev *gf_dev) +{ +#ifdef GF_PW_CTL + int rc = 0; + /*get pwr resource*/ + gf_dev->pwr_gpio = + of_get_named_gpio(gf_dev->spi->dev.of_node, "fp-gpio-pwr", 0); + + if (!gpio_is_valid(gf_dev->pwr_gpio)) { + pr_info("PWR GPIO is invalid.\n"); + return -1; + } + + rc = gpio_request(gf_dev->pwr_gpio, "goodix_pwr"); + + if (rc) { + dev_err(&gf_dev->spi->dev, + "Failed to request PWR GPIO. rc = %d\n", rc); + return -1; + } + +#endif + /*get reset resource*/ + gf_dev->reset_gpio = of_get_named_gpio(gf_dev->spi->dev.of_node, + "goodix,gpio-reset", 0); + + if (!gpio_is_valid(gf_dev->reset_gpio)) { + pr_info("RESET GPIO is invalid.\n"); + return -EPERM; + } + + /*get irq resourece*/ + gf_dev->irq_gpio = of_get_named_gpio(gf_dev->spi->dev.of_node, + "goodix,gpio-irq", 0); + pr_info("gf::irq_gpio:%d\n", gf_dev->irq_gpio); + + if (!gpio_is_valid(gf_dev->irq_gpio)) { + pr_info("IRQ GPIO is invalid.\n"); + return -EPERM; + } + + return 0; +} + +void gf_cleanup(struct gf_dev *gf_dev) +{ + pr_info("[info] %s\n", __func__); + + if (gpio_is_valid(gf_dev->irq_gpio)) { + gpio_free(gf_dev->irq_gpio); + pr_info("remove irq_gpio success\n"); + } + + if (gpio_is_valid(gf_dev->reset_gpio)) { + gpio_free(gf_dev->reset_gpio); + pr_info("remove reset_gpio success\n"); + } + +#ifdef GF_PW_CTL + + if (gpio_is_valid(gf_dev->pwr_gpio)) { + gpio_free(gf_dev->pwr_gpio); + pr_info("remove pwr_gpio success\n"); + } + +#endif +} + +int gf_power_on(struct gf_dev *gf_dev) +{ + int rc = 0; +#ifdef GF_PW_CTL + + if (gpio_is_valid(gf_dev->pwr_gpio)) { + rc = gpio_direction_output(gf_dev->pwr_gpio, 1); + pr_info("---- power on result: %d----\n", rc); + } else { + pr_info("%s: gpio_is_invalid\n", __func__); + } + +#endif + msleep(10); + return rc; +} + +int gf_power_off(struct gf_dev *gf_dev) +{ + int rc = 0; +#ifdef GF_PW_CTL + + if (gpio_is_valid(gf_dev->pwr_gpio)) { + rc = gpio_direction_output(gf_dev->pwr_gpio, 0); + pr_info("---- power off result: %d----\n", rc); + } else { + pr_info("%s: gpio_is_invalid\n", __func__); + } + +#endif + return rc; +} + +int gf_hw_reset(struct gf_dev *gf_dev, unsigned int delay_ms) +{ + if (gf_dev == NULL) { + pr_info("Input buff is NULL.\n"); + return -EPERM; + } + + gpio_direction_output(gf_dev->reset_gpio, 0); + mdelay(3); + gpio_set_value(gf_dev->reset_gpio, 1); + mdelay(delay_ms); + pr_info("%s\n", __func__); + return 0; +} + +int gf_irq_num(struct gf_dev *gf_dev) +{ + if (gf_dev == NULL) { + pr_info("Input buff is NULL.\n"); + return -EPERM; + } else { + return gpio_to_irq(gf_dev->irq_gpio); + } +} From 4bbd1bfe78f2fe8b02dea08cc768245c6556b745 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 21:41:52 +0100 Subject: [PATCH 045/226] drivers: input: fingerprint: Use MSM DRM notifier Change-Id: I724f3d67254603fe201f63d524584243c4f04884 Signed-off-by: firebird11 --- drivers/input/fingerprint/fpc_tee/fpc1020_tee.c | 14 +++++++------- drivers/input/fingerprint/goodix_ta/gf_spi.c | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c index 4c192c32d1d9..af457221f47c 100644 --- a/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c +++ b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #define FPC_SCREEN_HOLD_TIME 2000 #define FPC_TTW_HOLD_TIME 2000 @@ -681,15 +681,15 @@ static int fpc_fb_notif_callback(struct notifier_block *nb, unsigned long val, if (!fpc1020) return 0; - if (val != DRM_EVENT_BLANK || fpc1020->prepared == false) + if (val != MSM_DRM_EVENT_BLANK || fpc1020->prepared == false) return 0; pr_debug("[info] %s value = %d\n", __func__, (int)val); - if (evdata && evdata->data && val == DRM_EVENT_BLANK) { + if (evdata && evdata->data && val == MSM_DRM_EVENT_BLANK) { blank = *(int *)(evdata->data); switch (blank) { - case DRM_BLANK_POWERDOWN: + case MSM_DRM_BLANK_POWERDOWN: fpc1020->fb_black = true; #ifdef CONFIG_FINGERPRINT_FPC_SCREEN_NOTIFY __pm_wakeup_event(&fpc1020->screen_wl, @@ -698,7 +698,7 @@ static int fpc_fb_notif_callback(struct notifier_block *nb, unsigned long val, dev_attr_screen_status.attr.name); #endif break; - case DRM_BLANK_UNBLANK: + case MSM_DRM_BLANK_UNBLANK: fpc1020->fb_black = false; #ifdef CONFIG_FINGERPRINT_FPC_SCREEN_NOTIFY __pm_wakeup_event(&fpc1020->screen_wl, @@ -800,7 +800,7 @@ static int fpc1020_probe(struct platform_device *pdev) fpc1020->wait_finger_down = false; INIT_WORK(&fpc1020->work, notification_work); fpc1020->fb_notifier = fpc_notif_block; - drm_register_client(&fpc1020->fb_notifier); + msm_drm_register_client(&fpc1020->fb_notifier); dev_info(dev, "%s: ok\n", __func__); @@ -812,7 +812,7 @@ static int fpc1020_remove(struct platform_device *pdev) { struct fpc1020_data *fpc1020 = platform_get_drvdata(pdev); - drm_unregister_client(&fpc1020->fb_notifier); + msm_drm_unregister_client(&fpc1020->fb_notifier); sysfs_remove_group(&pdev->dev.kobj, &attribute_group); mutex_destroy(&fpc1020->lock); wakeup_source_trash(&fpc1020->ttw_wl); diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.c b/drivers/input/fingerprint/goodix_ta/gf_spi.c index 1812a5ef5de6..63986a6f3b05 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.c +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.c @@ -47,7 +47,7 @@ #include #include #ifndef GOODIX_DRM_INTERFACE_WA -#include +#include #endif #include "gf_spi.h" @@ -757,7 +757,7 @@ static int goodix_fb_state_chg_callback(struct notifier_block *nb, unsigned int blank; char temp[4] = { 0x0 }; - if (val != DRM_EVENT_BLANK) { + if (val != MSM_DRM_EVENT_BLANK) { return 0; } @@ -766,11 +766,11 @@ static int goodix_fb_state_chg_callback(struct notifier_block *nb, __func__, (int)val); gf_dev = container_of(nb, struct gf_dev, notifier); - if (evdata && evdata->data && val == DRM_EVENT_BLANK && gf_dev) { + if (evdata && evdata->data && val == MSM_DRM_EVENT_BLANK && gf_dev) { blank = *(int *)(evdata->data); switch (blank) { - case DRM_BLANK_POWERDOWN: + case MSM_DRM_BLANK_POWERDOWN: if (gf_dev->device_available == 1) { gf_dev->fb_black = 1; gf_dev->wait_finger_down = true; @@ -789,7 +789,7 @@ static int goodix_fb_state_chg_callback(struct notifier_block *nb, break; - case DRM_BLANK_UNBLANK: + case MSM_DRM_BLANK_UNBLANK: if (gf_dev->device_available == 1) { gf_dev->fb_black = 0; #if defined(GF_NETLINK_ENABLE) @@ -922,7 +922,7 @@ static int gf_probe(struct platform_device *pdev) #endif #ifndef GOODIX_DRM_INTERFACE_WA gf_dev->notifier = goodix_noti_block; - drm_register_client(&gf_dev->notifier); + msm_drm_register_client(&gf_dev->notifier); #endif gf_dev->irq = gf_irq_num(gf_dev); wakeup_source_init(&fp_wakelock, "fp_wakelock"); @@ -987,7 +987,7 @@ static int gf_remove(struct platform_device *pdev) } #ifndef GOODIX_DRM_INTERFACE_WA - drm_unregister_client(&gf_dev->notifier); + msm_drm_unregister_client(&gf_dev->notifier); #endif mutex_unlock(&device_list_lock); return 0; From ae98455b55ad6e7fc48e37a76797d1aced629295 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 21:43:27 +0100 Subject: [PATCH 046/226] drivers: input: fingerprint: Drop calls to dsi_bridge_interface_enable Change-Id: I2cf43d7c7bcdabb08ee03f5e193fe23aac431750 Signed-off-by: firebird11 --- drivers/input/fingerprint/fpc_tee/fpc1020_tee.c | 9 --------- drivers/input/fingerprint/goodix_ta/gf_spi.c | 12 ------------ drivers/input/fingerprint/goodix_ta/gf_spi.h | 1 - 3 files changed, 22 deletions(-) diff --git a/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c index af457221f47c..79684b15d084 100644 --- a/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c +++ b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c @@ -114,7 +114,6 @@ struct fpc1020_data { struct notifier_block fb_notifier; bool fb_black; bool wait_finger_down; - struct work_struct work; }; static irqreturn_t fpc1020_irq_handler(int irq, void *handle); @@ -620,12 +619,6 @@ static const struct attribute_group attribute_group = { .attrs = attributes, }; -static void notification_work(struct work_struct *work) -{ - pr_debug("%s: unblank\n", __func__); - dsi_bridge_interface_enable(FP_UNLOCK_REJECTION_TIMEOUT); -} - static irqreturn_t fpc1020_irq_handler(int irq, void *handle) { struct fpc1020_data *fpc1020 = handle; @@ -641,7 +634,6 @@ static irqreturn_t fpc1020_irq_handler(int irq, void *handle) fpc1020->prepared) { pr_debug("%s enter\n", __func__); fpc1020->wait_finger_down = false; - schedule_work(&fpc1020->work); } return IRQ_HANDLED; @@ -798,7 +790,6 @@ static int fpc1020_probe(struct platform_device *pdev) fpc1020->fb_black = false; fpc1020->wait_finger_down = false; - INIT_WORK(&fpc1020->work, notification_work); fpc1020->fb_notifier = fpc_notif_block; msm_drm_register_client(&fpc1020->fb_notifier); diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.c b/drivers/input/fingerprint/goodix_ta/gf_spi.c index 63986a6f3b05..7e2a64b9fedf 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.c +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.c @@ -544,14 +544,6 @@ static long gf_compat_ioctl(struct file *filp, unsigned int cmd, } #endif /*CONFIG_COMPAT*/ -#ifndef GOODIX_DRM_INTERFACE_WA -static void notification_work(struct work_struct *work) -{ - pr_debug("%s unblank\n", __func__); - dsi_bridge_interface_enable(FP_UNLOCK_REJECTION_TIMEOUT); -} -#endif - static irqreturn_t gf_irq(int irq, void *handle) { struct gf_dev *gf_dev = &gf; @@ -571,7 +563,6 @@ static irqreturn_t gf_irq(int irq, void *handle) input_report_key(gf_dev->input, key_input, 0); input_sync(gf_dev->input); gf_dev->wait_finger_down = false; - schedule_work(&gf_dev->work); } #elif defined(GF_FASYNC) @@ -845,9 +836,6 @@ static int gf_probe(struct platform_device *pdev) gf_dev->device_available = 0; gf_dev->fb_black = 0; gf_dev->wait_finger_down = false; -#ifndef GOODIX_DRM_INTERFACE_WA - INIT_WORK(&gf_dev->work, notification_work); -#endif if (gf_parse_dts(gf_dev)) { goto error_hw; diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.h b/drivers/input/fingerprint/goodix_ta/gf_spi.h index 3ea8a55b40fc..dde103b345e6 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.h +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.h @@ -139,7 +139,6 @@ struct gf_dev { char device_available; char fb_black; char wait_finger_down; - struct work_struct work; #ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL struct regulator *vreg; #endif From 8d5049b5c248e1c7e83d42b0f13d618be3335ea0 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sat, 9 Jul 2022 15:35:51 +0200 Subject: [PATCH 047/226] drivers: input: fingerprint: goodix: Improve wakelock handling * From vayu-r-oss Change-Id: Ie207478a65d1fbcebc014d9b134d77e528d4dc88 Signed-off-by: firebird11 --- drivers/input/fingerprint/goodix_ta/gf_spi.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.c b/drivers/input/fingerprint/goodix_ta/gf_spi.c index 7e2a64b9fedf..7ade4a784936 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.c +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.c @@ -81,7 +81,7 @@ static int SPIDEV_MAJOR; static DECLARE_BITMAP(minors, N_SPI_MINORS); static LIST_HEAD(device_list); static DEFINE_MUTEX(device_list_lock); -static struct wakeup_source fp_wakelock; +static struct wakeup_source *fp_wakelock = NULL; static struct gf_dev gf; struct gf_key_map maps[] = { @@ -552,7 +552,8 @@ static irqreturn_t gf_irq(int irq, void *handle) uint32_t key_input = 0; temp[0] = GF_NET_EVENT_IRQ; pr_debug("%s enter\n", __func__); - __pm_wakeup_event(&fp_wakelock, WAKELOCK_HOLD_TIME); + if (fp_wakelock != NULL) + __pm_wakeup_event(fp_wakelock, WAKELOCK_HOLD_TIME); sendnlmsg(temp); if ((gf_dev->wait_finger_down == true) && @@ -913,9 +914,15 @@ static int gf_probe(struct platform_device *pdev) msm_drm_register_client(&gf_dev->notifier); #endif gf_dev->irq = gf_irq_num(gf_dev); - wakeup_source_init(&fp_wakelock, "fp_wakelock"); + fp_wakelock = wakeup_source_register(&gf_dev->spi->dev, "fp_wakelock"); + if (fp_wakelock == NULL) + goto error_wakelock; pr_debug("version V%d.%d.%02d\n", VER_MAJOR, VER_MINOR, PATCH_LEVEL); return status; + +error_wakelock: + pr_debug("create fp wakelock failed.\n"); + #ifdef AP_CONTROL_CLK gfspi_probe_clk_enable_failed: gfspi_ioctl_clk_uninit(gf_dev); @@ -952,7 +959,8 @@ static int gf_remove(struct platform_device *pdev) #endif { struct gf_dev *gf_dev = &gf; - wakeup_source_trash(&fp_wakelock); + wakeup_source_unregister(fp_wakelock); + fp_wakelock = NULL; /* make sure ops on existing fds can abort cleanly */ if (gf_dev->irq) { From 9882a18f08c236ff01addf5f718ab4545abdc348 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 19:38:05 +0100 Subject: [PATCH 048/226] drivers: input: fingerprint: goodix: Add vayu support * From vayu-r-oss Change-Id: I1507b413477a80c8ca36a702499c7aeb4b7d51c2 Signed-off-by: firebird11 --- drivers/input/fingerprint/goodix_ta/gf_spi.c | 44 ++++++++++++++------ drivers/input/fingerprint/goodix_ta/gf_spi.h | 4 +- 2 files changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.c b/drivers/input/fingerprint/goodix_ta/gf_spi.c index 7ade4a784936..0d457eb7ea59 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.c +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.c @@ -49,6 +49,7 @@ #ifndef GOODIX_DRM_INTERFACE_WA #include #endif +#include #include "gf_spi.h" @@ -591,9 +592,11 @@ static int gf_open(struct inode *inode, struct file *filp) break; } } -#ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL pr_info("Try to enable fp_vdd_vreg\n"); - gf_dev->vreg = regulator_get(&gf_dev->spi->dev, "fp_vdd_vreg"); + if (get_hw_version_platform() == HARDWARE_PLATFORM_VAYU) + gf_dev->vreg = regulator_get(NULL, "pm8150_l17"); + else + gf_dev->vreg = regulator_get(&gf_dev->spi->dev, "fp_vdd_vreg"); if (gf_dev->vreg == NULL) { dev_err(&gf_dev->spi->dev, @@ -605,6 +608,17 @@ static int gf_open(struct inode *inode, struct file *filp) if (regulator_is_enabled(gf_dev->vreg)) { pr_info("fp_vdd_vreg is already enabled!\n"); } else { + if (get_hw_version_platform() == HARDWARE_PLATFORM_VAYU) { + status = regulator_set_voltage(gf_dev->vreg, 3000000, + 3000000); + if (status < 0) { + pr_info("fp_vdd_vreg set voltage failed!\n"); + gf_dev->vreg = NULL; + mutex_unlock(&device_list_lock); + return -EPERM; + } + } + rc = regulator_enable(gf_dev->vreg); if (rc) { @@ -618,10 +632,12 @@ static int gf_open(struct inode *inode, struct file *filp) } pr_info("fp_vdd_vreg is enabled!\n"); -#endif if (status == 0) { - rc = gpio_request(gf_dev->reset_gpio, "goodix_reset"); + if (get_hw_version_platform() == HARDWARE_PLATFORM_VAYU) + rc = gpio_request(gf_dev->reset_gpio, "gpio-reset"); + else + rc = gpio_request(gf_dev->reset_gpio, "goodix_reset"); if (rc) { dev_err(&gf_dev->spi->dev, @@ -632,7 +648,10 @@ static int gf_open(struct inode *inode, struct file *filp) } gpio_direction_output(gf_dev->reset_gpio, 0); - rc = gpio_request(gf_dev->irq_gpio, "goodix_irq"); + if (get_hw_version_platform() == HARDWARE_PLATFORM_VAYU) + rc = gpio_request(gf_dev->irq_gpio, "gpio-irq"); + else + rc = gpio_request(gf_dev->irq_gpio, "goodix_irq"); if (rc) { dev_err(&gf_dev->spi->dev, @@ -696,16 +715,15 @@ static int gf_release(struct inode *inode, struct file *filp) /* *Disable fp_vdd_vreg regulator */ -#ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL - pr_info("disable fp_vdd_vreg!\n"); + if (get_hw_version_platform() == HARDWARE_PLATFORM_VAYU) { + pr_info("disable fp_vdd_vreg!\n"); - if (regulator_is_enabled(gf_dev->vreg)) { - regulator_disable(gf_dev->vreg); - regulator_put(gf_dev->vreg); - gf_dev->vreg = NULL; + if (regulator_is_enabled(gf_dev->vreg)) { + regulator_disable(gf_dev->vreg); + regulator_put(gf_dev->vreg); + gf_dev->vreg = NULL; + } } - -#endif gf_dev->users--; if (!gf_dev->users) { diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.h b/drivers/input/fingerprint/goodix_ta/gf_spi.h index dde103b345e6..e9b17f8b19eb 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.h +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.h @@ -105,7 +105,9 @@ struct gf_ioc_chip_info { #define USE_PLATFORM_BUS 1 /*#define USE_SPI_BUS 1*/ /*#define GF_FASYNC 1*/ /*If support fasync mechanism.*/ +#ifndef CONFIG_MACH_XIAOMI_VAYU #define GF_PW_CTL 1 +#endif #define GF_NETLINK_ENABLE 1 #define GF_NET_EVENT_IRQ 1 #define GF_NET_EVENT_FB_BLACK 2 @@ -139,9 +141,7 @@ struct gf_dev { char device_available; char fb_black; char wait_finger_down; -#ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL struct regulator *vreg; -#endif }; int gf_parse_dts(struct gf_dev *gf_dev); From 8240a39907c75db8e602897719de90bb89d4213e Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:02:03 +0200 Subject: [PATCH 049/226] drivers: input: keyboard: Import Xiaomi changes Change-Id: I7bb81d202ac600005bda4d801e62d2d2c5132f88 Signed-off-by: firebird11 --- drivers/input/keyboard/gpio_keys.c | 34 ++++++++++++++++++++++++++++++ include/linux/gpio_keys.h | 3 +++ 2 files changed, 37 insertions(+) diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c index e9f0ebf3267a..69e66e3604ae 100644 --- a/drivers/input/keyboard/gpio_keys.c +++ b/drivers/input/keyboard/gpio_keys.c @@ -385,6 +385,21 @@ static void gpio_keys_gpio_work_func(struct work_struct *work) struct gpio_button_data *bdata = container_of(work, struct gpio_button_data, work.work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (bdata->button->level_trigger) { + unsigned int trigger = + irq_get_trigger_type(bdata->irq) & ~IRQF_TRIGGER_MASK; + int state = gpiod_get_value_cansleep(bdata->gpiod); + if (state) + trigger |= IRQF_TRIGGER_HIGH; + else + trigger |= IRQF_TRIGGER_LOW; + + irq_set_irq_type(bdata->irq, trigger); + enable_irq(bdata->irq); + } +#endif + gpio_keys_gpio_report_event(bdata); if (bdata->button->wakeup) @@ -397,11 +412,19 @@ static irqreturn_t gpio_keys_gpio_isr(int irq, void *dev_id) BUG_ON(irq != bdata->irq); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (bdata->button->level_trigger) + disable_irq_nosync(bdata->irq); +#endif + if (bdata->button->wakeup) { const struct gpio_keys_button *button = bdata->button; pm_stay_awake(bdata->input->dev.parent); if (bdata->suspended && +#ifdef CONFIG_MACH_XIAOMI_SM8150 + (button->code != KEY_AI) && +#endif (button->type == 0 || button->type == EV_KEY)) { /* * Simulate wakeup key press in case the key has @@ -567,6 +590,12 @@ static int gpio_keys_setup_key(struct platform_device *pdev, isr = gpio_keys_gpio_isr; irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (bdata->button->level_trigger) { + irqflags = gpiod_is_active_low(bdata->gpiod) ? + IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH; + } +#endif } else { if (!button->irq) { @@ -722,6 +751,11 @@ gpio_keys_get_devtree_pdata(struct device *dev) button->can_disable = fwnode_property_read_bool(child, "linux,can-disable"); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + button->level_trigger = + fwnode_property_read_bool(child, "gpio-key,level-trigger"); +#endif + if (fwnode_property_read_u32(child, "debounce-interval", &button->debounce_interval)) button->debounce_interval = 5; diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h index d06bf77400f1..cf1bba4e7aae 100644 --- a/include/linux/gpio_keys.h +++ b/include/linux/gpio_keys.h @@ -28,6 +28,9 @@ struct gpio_keys_button { int wakeup; int debounce_interval; bool can_disable; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool level_trigger; +#endif int value; unsigned int irq; }; From c81a101f06711e516b02cc0256bf05bdaefef959 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:03:45 +0200 Subject: [PATCH 050/226] drivers: input: misc: Import Xiaomi changes Change-Id: I9335d252b98c4e552cc04118a2cf59ec64a9f922 Signed-off-by: firebird11 --- drivers/input/misc/qti-haptics.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/input/misc/qti-haptics.c b/drivers/input/misc/qti-haptics.c index fe2ed14461cb..1eec6ae72dc7 100644 --- a/drivers/input/misc/qti-haptics.c +++ b/drivers/input/misc/qti-haptics.c @@ -1176,7 +1176,11 @@ static int qti_haptics_hw_init(struct qti_hap_chip *chip) addr = REG_HAP_AUTO_RES_CFG; mask = HAP_AUTO_RES_MODE_BIT | HAP_CAL_EOP_EN_BIT | HAP_CAL_PERIOD_MASK; val = config->lra_auto_res_mode << HAP_AUTO_RES_MODE_SHIFT; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + val |= HAP_CAL_EOP_EN_BIT; +#else val |= HAP_CAL_EOP_EN_BIT | HAP_CAL_OPT3_EVERY_8_PERIOD; +#endif rc = qti_haptics_masked_write(chip, addr, mask, val); if (rc < 0) { dev_err(chip->dev, "set AUTO_RES_CFG failed, rc=%d\n", rc); From 061139883b8fa64f39ebec2b257e338a3b7f605b Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 11:02:15 +0100 Subject: [PATCH 051/226] drivers: input: misc: Import aw8697_haptic_xm driver * Run clang-format on source files Change-Id: If9062dbbc2513b29bb4476267c6c5de1c8cc2ad7 Signed-off-by: firebird11 --- drivers/input/misc/Kconfig | 2 + drivers/input/misc/Makefile | 1 + drivers/input/misc/aw8697_haptic_xm/Kconfig | 15 + drivers/input/misc/aw8697_haptic_xm/Makefile | 2 + drivers/input/misc/aw8697_haptic_xm/aw8697.c | 4929 +++++++++++++++++ drivers/input/misc/aw8697_haptic_xm/aw8697.h | 454 ++ .../misc/aw8697_haptic_xm/aw8697_config.h | 117 + .../input/misc/aw8697_haptic_xm/aw8697_reg.h | 539 ++ .../input/misc/aw8697_haptic_xm/ringbuffer.c | 228 + .../input/misc/aw8697_haptic_xm/ringbuffer.h | 36 + 10 files changed, 6323 insertions(+) create mode 100755 drivers/input/misc/aw8697_haptic_xm/Kconfig create mode 100755 drivers/input/misc/aw8697_haptic_xm/Makefile create mode 100644 drivers/input/misc/aw8697_haptic_xm/aw8697.c create mode 100644 drivers/input/misc/aw8697_haptic_xm/aw8697.h create mode 100644 drivers/input/misc/aw8697_haptic_xm/aw8697_config.h create mode 100644 drivers/input/misc/aw8697_haptic_xm/aw8697_reg.h create mode 100644 drivers/input/misc/aw8697_haptic_xm/ringbuffer.c create mode 100644 drivers/input/misc/aw8697_haptic_xm/ringbuffer.h diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index e0c7a6f358df..4ff5b3406b8e 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -889,4 +889,6 @@ config INPUT_HISI_POWERKEY To compile this driver as a module, choose M here: the module will be called hisi_powerkey. +source "drivers/input/misc/aw8697_haptic_xm/Kconfig" + endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 137da08f75a8..c790f73d3dd8 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -85,3 +85,4 @@ obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_INPUT_IDEAPAD_SLIDEBAR) += ideapad_slidebar.o +obj-$(CONFIG_INPUT_AW8697_XM_HAPTIC) += aw8697_haptic_xm/ diff --git a/drivers/input/misc/aw8697_haptic_xm/Kconfig b/drivers/input/misc/aw8697_haptic_xm/Kconfig new file mode 100755 index 000000000000..978e396dcc77 --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/Kconfig @@ -0,0 +1,15 @@ +# +# Mediatek AW9233 Driver +# + +config INPUT_AW8697_XM_HAPTIC + tristate "Freescale AW8697 Touchkey" + depends on I2C + help + Say Y here if you have Freescale AW8697 touchkey controller + chip in your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called mpr121_touchkey. diff --git a/drivers/input/misc/aw8697_haptic_xm/Makefile b/drivers/input/misc/aw8697_haptic_xm/Makefile new file mode 100755 index 000000000000..4029f8dc9ca1 --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_INPUT_AW8697_XM_HAPTIC) += aw8697.o +obj-$(CONFIG_INPUT_AW8697_XM_HAPTIC) += ringbuffer.o diff --git a/drivers/input/misc/aw8697_haptic_xm/aw8697.c b/drivers/input/misc/aw8697_haptic_xm/aw8697.c new file mode 100644 index 000000000000..63b27b37267c --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/aw8697.c @@ -0,0 +1,4929 @@ +/* + * aw8697.c aw8697 haptic module + * + * Version: v1.1.3 + * + * Copyright (c) 2019 AWINIC Technology CO., LTD + * + * Author: Nick Li + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "aw8697_config.h" +#include "aw8697_reg.h" +#include "aw8697.h" +#include "ringbuffer.h" + +/****************************************************** + * + * Marco + * + ******************************************************/ +#define AW8697_I2C_NAME "aw8697_haptic" +#define AW8697_HAPTIC_NAME "aw8697_haptic" + +#define AW8697_VERSION "v1.1.3" + +#define AWINIC_RAM_UPDATE_DELAY + +#define AW_I2C_RETRIES 2 +#define AW_I2C_RETRY_DELAY 2 +#define AW_READ_CHIPID_RETRIES 5 +#define AW_READ_CHIPID_RETRY_DELAY 2 + +#define AW8697_MAX_DSP_START_TRY_COUNT 10 + +#define AW8697_MAX_FIRMWARE_LOAD_CNT 20 + +#define AW8697_MAX_BST_VO 0x1f + +#define OSC_CALIBRATION_T_LENGTH 5100000 +#define PM_QOS_VALUE_VB 400 +struct pm_qos_request pm_qos_req_vb; +/****************************************************** + * + * variable + * + ******************************************************/ +#define AW8697_RTP_NAME_MAX 64 +static char *aw8697_ram_name = "aw8697_haptic.bin"; +#ifdef TEST_RTP +static char aw8697_rtp_name[][AW8697_RTP_NAME_MAX] = { + { "aw8697_rtp_1.bin" }, +}; +#else +static char aw8697_rtp_name[][AW8697_RTP_NAME_MAX] = { + { "aw8697_rtp_1.bin" }, //8 + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + //{"aw8697_rtp_1.bin"}, + //{"aw8697_rtp_1.bin"}, + { "AcousticGuitar_RTP.bin" }, //21 + { "Blues_RTP.bin" }, + { "Candy_RTP.bin" }, + { "Carousel_RTP.bin" }, + { "Celesta_RTP.bin" }, + { "Childhood_RTP.bin" }, + { "Country_RTP.bin" }, + { "Cowboy_RTP.bin" }, + { "Echo_RTP.bin" }, + { "Fairyland_RTP.bin" }, + { "Fantasy_RTP.bin" }, + { "Field_Trip_RTP.bin" }, + { "Glee_RTP.bin" }, + { "Glockenspiel_RTP.bin" }, + { "Ice_Latte_RTP.bin" }, + { "Kung_Fu_RTP.bin" }, + { "Leisure_RTP.bin" }, + { "Lollipop_RTP.bin" }, + { "MiMix2_RTP.bin" }, + { "Mi_RTP.bin" }, + { "MiHouse_RTP.bin" }, + { "MiJazz_RTP.bin" }, + { "MiRemix_RTP.bin" }, + { "Mountain_Spring_RTP.bin" }, + { "Orange_RTP.bin" }, + { "Raindrops_RTP.bin" }, + { "Space_Age_RTP.bin" }, + { "ToyRobot_RTP.bin" }, + { "Vigor_RTP.bin" }, + { "Bottle_RTP.bin" }, + { "Bubble_RTP.bin" }, + { "Bullfrog_RTP.bin" }, + { "Burst_RTP.bin" }, + { "Chirp_RTP.bin" }, + { "Clank_RTP.bin" }, + { "Crystal_RTP.bin" }, + { "FadeIn_RTP.bin" }, + { "FadeOut_RTP.bin" }, + { "Flute_RTP.bin" }, + { "Fresh_RTP.bin" }, + { "Frog_RTP.bin" }, + { "Guitar_RTP.bin" }, + { "Harp_RTP.bin" }, + { "IncomingMessage_RTP.bin" }, + { "MessageSent_RTP.bin" }, + { "Moment_RTP.bin" }, + { "NotificationXylophone_RTP.bin" }, + { "Potion_RTP.bin" }, + { "Radar_RTP.bin" }, + { "Spring_RTP.bin" }, + { "Swoosh_RTP.bin" }, //71 + { "Gesture_UpSlide_RTP.bin" }, + { "FOD_Motion_Planet_RTP.bin" }, + { "Charge_Wire_RTP.bin" }, + { "Charge_Wireless_RTP.bin" }, + { "Unlock_Failed_RTP.bin" }, + { "FOD_Motion1_RTP.bin" }, + { "FOD_Motion2_RTP.bin" }, + { "FOD_Motion3_RTP.bin" }, + { "FOD_Motion4_RTP.bin" }, + { "FOD_Motion_Aurora_RTP.bin" }, + { "FaceID_Wrong2_RTP.bin" }, //82 + { "uninstall_animation_rtp.bin" }, + { "uninstall_dialog_rtp.bin" }, + { "screenshot_rtp.bin" }, + { "lockscreen_camera_entry_rtp.bin" }, + { "launcher_edit_rtp.bin" }, + { "launcher_icon_selection_rtp.bin" }, + { "taskcard_remove_rtp.bin" }, + { "task_cleanall_rtp.bin" }, + { "new_iconfolder_rtp.bin" }, + { "notification_remove_rtp.bin" }, + { "notification_cleanall_rtp.bin" }, + { "notification_setting_rtp.bin" }, + { "game_turbo_rtp.bin" }, + { "NFC_card_rtp.bin" }, + { "wakeup_voice_assistant_rtp.bin" }, + { "NFC_card_slow_rtp.bin" }, + { "aw8697_rtp_1.bin" }, //99 + { "aw8697_rtp_1.bin" }, //100 + { "offline_countdown_RTP.bin" }, + { "scene_bomb_injury_RTP.bin" }, + { "scene_bomb_RTP.bin" }, //103 + { "door_open_RTP.bin" }, + { "aw8697_rtp_1.bin" }, + { "scene_step_RTP.bin" }, //106 + { "crawl_RTP.bin" }, + { "scope_on_RTP.bin" }, + { "scope_off_RTP.bin" }, + { "magazine_quick_RTP.bin" }, + { "grenade_RTP.bin" }, + { "scene_getshot_RTP.bin" }, //112 + { "grenade_explosion_RTP.bin" }, + { "punch_RTP.bin" }, + { "pan_RTP.bin" }, + { "bandage_RTP.bin" }, + { "aw8697_rtp_1.bin" }, + { "scene_jump_RTP.bin" }, + { "vehicle_plane_RTP.bin" }, //119 + { "scene_openparachute_RTP.bin" }, //120 + { "scene_closeparachute_RTP.bin" }, //121 + { "vehicle_collision_RTP.bin" }, + { "vehicle_buggy_RTP.bin" }, //123 + { "vehicle_dacia_RTP.bin" }, //124 + { "vehicle_moto_RTP.bin" }, //125 + { "firearms_akm_RTP.bin" }, //126 + { "firearms_m16a4_RTP.bin" }, //127 + { "aw8697_rtp_1.bin" }, + { "firearms_awm_RTP.bin" }, //129 + { "firearms_mini14_RTP.bin" }, //130 + { "firearms_vss_RTP.bin" }, //131 + { "firearms_qbz_RTP.bin" }, //132 + { "firearms_ump9_RTP.bin" }, //133 + { "firearms_dp28_RTP.bin" }, //134 + { "firearms_s1897_RTP.bin" }, //135 + { "aw8697_rtp_1.bin" }, + { "firearms_p18c_RTP.bin" }, //137 + { "aw8697_rtp_1.bin" }, + { "aw8697_rtp_1.bin" }, + { "CFM_KillOne_RTP.bin" }, + { "CFM_Headshot_RTP.bin" }, //141 + { "CFM_MultiKill_RTP.bin" }, + { "CFM_KillOne_Strong_RTP.bin" }, + { "CFM_Headshot_Strong_RTP.bin" }, + { "CFM_MultiKill_Strong_RTP.bin" }, + { "CFM_Weapon_Grenade_Explode_RTP.bin" }, + { "CFM_Weapon_Grenade_KillOne_RTP.bin" }, + { "CFM_ImpactFlesh_Normal_RTP.bin" }, + { "CFM_Weapon_C4_Installed_RTP.bin" }, + { "CFM_Hero_Appear_RTP.bin" }, + { "CFM_UI_Reward_OpenBox_RTP.bin" }, + { "CFM_UI_Reward_Task_RTP.bin" }, + { "CFM_Weapon_BLT_Shoot_RTP.bin" }, //153 + { "Atlantis_RTP.bin" }, + { "DigitalUniverse_RTP.bin" }, + { "Reveries_RTP.bin" }, + { "FOD_Motion_Triang_RTP.bin" }, + { "FOD_Motion_Flare_RTP.bin" }, + { "FOD_Motion_Ripple_RTP.bin" }, + { "FOD_Motion_Spiral_RTP.bin" }, + { "gamebox_launch_rtp.bin" }, // 161 + { "Gesture_Back_Pull_RTP.bin" }, // 162 + { "Gesture_Back_Release_RTP.bin" }, // 163 + { "alert_rtp.bin" }, // 164 + { "feedback_negative_light_rtp.bin" }, // 165 + { "feedback_neutral_rtp.bin" }, // 166 + { "feedback_positive_rtp.bin" }, // 167 + { "fingerprint_record_rtp.bin" }, // 168 + { "lockdown_rtp.bin" }, // 169 + { "sliding_damping_rtp.bin" }, // 170 + { "todo_alldone_rtp.bin" }, // 171 + { "uninstall_animation_icon_rtp.bin" }, // 172 + { "signal_button_highlight_rtp.bin" }, //173 + { "signal_button_negative_rtp.bin" }, + { "signal_button_rtp.bin" }, + { "signal_clock_high_rtp.bin" }, //176 + { "signal_clock_rtp.bin" }, + { "signal_clock_unit_rtp.bin" }, + { "signal_inputbox_rtp.bin" }, + { "signal_key_high_rtp.bin" }, + { "signal_key_unit_rtp.bin" }, //181 + { "signal_list_highlight_rtp.bin" }, + { "signal_list_rtp.bin" }, + { "signal_picker_rtp.bin" }, + { "signal_popup_rtp.bin" }, + { "signal_seekbar_rtp.bin" }, //186 + { "signal_switch_rtp.bin" }, + { "signal_tab_rtp.bin" }, + { "signal_text_rtp.bin" }, + { "signal_transition_light_rtp.bin" }, + { "signal_transition_rtp.bin" }, //191 + { "haptics_video_rtp.bin" }, //192 +}; +#endif +static int CUSTOME_WAVE_ID; +struct aw8697_container *aw8697_rtp; +struct aw8697 *g_aw8697; + +/****************************************************** + * + * functions + * + ******************************************************/ +static void aw8697_interrupt_clear(struct aw8697 *aw8697); +static int aw8697_haptic_trig_enable_config(struct aw8697 *aw8697); + +/****************************************************** + * + * aw8697 i2c write/read + * + ******************************************************/ +static int aw8697_i2c_write(struct aw8697 *aw8697, unsigned char reg_addr, + unsigned char reg_data) +{ + int ret = -1; + unsigned char cnt = 0; + + while (cnt < AW_I2C_RETRIES) { + ret = i2c_smbus_write_byte_data(aw8697->i2c, reg_addr, + reg_data); + if (ret < 0) { + pr_err("%s: i2c_write cnt=%d error=%d\n", __func__, cnt, + ret); + } else { + break; + } + cnt++; + msleep(AW_I2C_RETRY_DELAY); + } + + return ret; +} + +static int aw8697_i2c_read(struct aw8697 *aw8697, unsigned char reg_addr, + unsigned char *reg_data) +{ + int ret = -1; + unsigned char cnt = 0; + + while (cnt < AW_I2C_RETRIES) { + ret = i2c_smbus_read_byte_data(aw8697->i2c, reg_addr); + if (ret < 0) { + pr_err("%s: i2c_read cnt=%d error=%d\n", __func__, cnt, + ret); + } else { + *reg_data = ret; + break; + } + cnt++; + msleep(AW_I2C_RETRY_DELAY); + } + + return ret; +} + +static int aw8697_i2c_write_bits(struct aw8697 *aw8697, unsigned char reg_addr, + unsigned int mask, unsigned char reg_data) +{ + unsigned char reg_val = 0; + + aw8697_i2c_read(aw8697, reg_addr, ®_val); + reg_val &= mask; + reg_val |= reg_data; + aw8697_i2c_write(aw8697, reg_addr, reg_val); + + return 0; +} + +static int aw8697_i2c_writes(struct aw8697 *aw8697, unsigned char reg_addr, + unsigned char *buf, unsigned int len) +{ + int ret = -1; + unsigned char *data; + + data = kmalloc(len + 1, GFP_KERNEL); + if (data == NULL) { + pr_err("%s: can not allocate memory\n", __func__); + return -ENOMEM; + } + + data[0] = reg_addr; + memcpy(&data[1], buf, len); + + ret = i2c_master_send(aw8697->i2c, data, len + 1); + if (ret < 0) { + pr_err("%s: i2c master send error\n", __func__); + } + + kfree(data); + + return ret; +} + +/***************************************************** + * + * ram update + * + *****************************************************/ +static void aw8697_rtp_loaded(const struct firmware *cont, void *context) +{ + struct aw8697 *aw8697 = context; + pr_info("%s enter\n", __func__); + + if (!cont) { + pr_err("%s: failed to read %s\n", __func__, + aw8697_rtp_name[aw8697->rtp_file_num]); + release_firmware(cont); + return; + } + + pr_info("%s: loaded %s - size: %zu\n", __func__, + aw8697_rtp_name[aw8697->rtp_file_num], cont ? cont->size : 0); + + /* aw8697 rtp update */ + aw8697_rtp = vmalloc(cont->size + sizeof(int)); + if (!aw8697_rtp) { + release_firmware(cont); + pr_err("%s: Error allocating memory\n", __func__); + return; + } + aw8697_rtp->len = cont->size; + pr_info("%s: rtp size = %d\n", __func__, aw8697_rtp->len); + memcpy(aw8697_rtp->data, cont->data, cont->size); + release_firmware(cont); + + aw8697->rtp_init = 1; + pr_info("%s: rtp update complete\n", __func__); +} + +static int aw8697_rtp_update(struct aw8697 *aw8697) +{ + pr_info("%s enter\n", __func__); + + return request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, + aw8697_rtp_name[aw8697->rtp_file_num], + aw8697->dev, GFP_KERNEL, aw8697, + aw8697_rtp_loaded); +} + +static void aw8697_container_update(struct aw8697 *aw8697, + struct aw8697_container *aw8697_cont) +{ + int i = 0; + unsigned int shift = 0; + + pr_info("%s enter\n", __func__); + + mutex_lock(&aw8697->lock); + + aw8697->ram.baseaddr_shift = 2; + aw8697->ram.ram_shift = 4; + + /* RAMINIT Enable */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_EN); + + /* base addr */ + shift = aw8697->ram.baseaddr_shift; + aw8697->ram.base_addr = + (unsigned int)((aw8697_cont->data[0 + shift] << 8) | + (aw8697_cont->data[1 + shift])); + pr_info("%s: base_addr=0x%4x\n", __func__, aw8697->ram.base_addr); + + aw8697_i2c_write(aw8697, AW8697_REG_BASE_ADDRH, + aw8697_cont->data[0 + shift]); + aw8697_i2c_write(aw8697, AW8697_REG_BASE_ADDRL, + aw8697_cont->data[1 + shift]); + + aw8697_i2c_write(aw8697, AW8697_REG_FIFO_AEH, + (unsigned char)((aw8697->ram.base_addr >> 2) >> 8)); + aw8697_i2c_write(aw8697, AW8697_REG_FIFO_AEL, + (unsigned char)((aw8697->ram.base_addr >> 2) & + 0x00FF)); + aw8697_i2c_write(aw8697, AW8697_REG_FIFO_AFH, + (unsigned char)((aw8697->ram.base_addr - + (aw8697->ram.base_addr >> 2)) >> + 8)); + aw8697_i2c_write(aw8697, AW8697_REG_FIFO_AFL, + (unsigned char)((aw8697->ram.base_addr - + (aw8697->ram.base_addr >> 2)) & + 0x00FF)); + + /* ram */ + shift = aw8697->ram.baseaddr_shift; + aw8697_i2c_write(aw8697, AW8697_REG_RAMADDRH, + aw8697_cont->data[0 + shift]); + aw8697_i2c_write(aw8697, AW8697_REG_RAMADDRL, + aw8697_cont->data[1 + shift]); + shift = aw8697->ram.ram_shift; + for (i = shift; i < aw8697_cont->len; i++) { + aw8697_i2c_write(aw8697, AW8697_REG_RAMDATA, + aw8697_cont->data[i]); + } + + /* RAMINIT Disable */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_OFF); + + mutex_unlock(&aw8697->lock); + + pr_info("%s exit\n", __func__); +} + +static void aw8697_ram_loaded(const struct firmware *cont, void *context) +{ + struct aw8697 *aw8697 = context; + struct aw8697_container *aw8697_fw; + int i = 0; + unsigned short check_sum = 0; + + pr_info("%s enter\n", __func__); + + if (!cont) { + pr_err("%s: failed to read %s\n", __func__, aw8697_ram_name); + release_firmware(cont); + return; + } + + pr_info("%s: loaded %s - size: %zu\n", __func__, aw8697_ram_name, + cont ? cont->size : 0); + /* + for(i=0; isize; i++) { + pr_info("%s: addr:0x%04x, data:0x%02x\n", __func__, i, *(cont->data+i)); + } + */ + + /* check sum */ + for (i = 2; i < cont->size; i++) { + check_sum += cont->data[i]; + } + if (check_sum != + (unsigned short)((cont->data[0] << 8) | (cont->data[1]))) { + pr_err("%s: check sum err: check_sum=0x%04x\n", __func__, + check_sum); + return; + } else { + pr_info("%s: check sum pass : 0x%04x\n", __func__, check_sum); + aw8697->ram.check_sum = check_sum; + } + + /* aw8697 ram update */ + aw8697_fw = kzalloc(cont->size + sizeof(int), GFP_KERNEL); + if (!aw8697_fw) { + release_firmware(cont); + pr_err("%s: Error allocating memory\n", __func__); + return; + } + aw8697_fw->len = cont->size; + memcpy(aw8697_fw->data, cont->data, cont->size); + release_firmware(cont); + + aw8697_container_update(aw8697, aw8697_fw); + + aw8697->ram.len = aw8697_fw->len; + + kfree(aw8697_fw); + + aw8697->ram_init = 1; + pr_info("%s: fw update complete\n", __func__); + + aw8697_haptic_trig_enable_config(aw8697); + + aw8697_rtp_update(aw8697); +} + +static int aw8697_ram_update(struct aw8697 *aw8697) +{ + aw8697->ram_init = 0; + aw8697->rtp_init = 0; + return request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, + aw8697_ram_name, aw8697->dev, GFP_KERNEL, + aw8697, aw8697_ram_loaded); +} + +#ifdef AWINIC_RAM_UPDATE_DELAY +static void aw8697_ram_work_routine(struct work_struct *work) +{ + struct aw8697 *aw8697 = + container_of(work, struct aw8697, ram_work.work); + + pr_info("%s enter\n", __func__); + + aw8697_ram_update(aw8697); +} +#endif + +static int aw8697_ram_init(struct aw8697 *aw8697) +{ +#ifdef AWINIC_RAM_UPDATE_DELAY + int ram_timer_val = 5000; + INIT_DELAYED_WORK(&aw8697->ram_work, aw8697_ram_work_routine); + //schedule_delayed_work(&aw8697->ram_work, + //msecs_to_jiffies(ram_timer_val)); + queue_delayed_work(aw8697->work_queue, &aw8697->ram_work, + msecs_to_jiffies(ram_timer_val)); +#else + aw8697_ram_update(aw8697); +#endif + return 0; +} + +/***************************************************** + * + * haptic control + * + *****************************************************/ +static int aw8697_haptic_softreset(struct aw8697 *aw8697) +{ + pr_debug("%s enter\n", __func__); + + aw8697_i2c_write(aw8697, AW8697_REG_ID, 0xAA); + msleep(1); + return 0; +} + +static int aw8697_haptic_active(struct aw8697 *aw8697) +{ + pr_debug("%s enter\n", __func__); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_WORK_MODE_MASK, + AW8697_BIT_SYSCTRL_ACTIVE); + aw8697_interrupt_clear(aw8697); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_UVLO_MASK, + AW8697_BIT_SYSINTM_UVLO_EN); + return 0; +} + +static int aw8697_haptic_play_mode(struct aw8697 *aw8697, + unsigned char play_mode) +{ + pr_debug("%s enter\n", __func__); + + switch (play_mode) { + case AW8697_HAPTIC_STANDBY_MODE: + aw8697->play_mode = AW8697_HAPTIC_STANDBY_MODE; + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_UVLO_MASK, + AW8697_BIT_SYSINTM_UVLO_OFF); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_WORK_MODE_MASK, + AW8697_BIT_SYSCTRL_STANDBY); + break; + case AW8697_HAPTIC_RAM_MODE: + aw8697->play_mode = AW8697_HAPTIC_RAM_MODE; + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_PLAY_MODE_MASK, + AW8697_BIT_SYSCTRL_PLAY_MODE_RAM); + aw8697_haptic_active(aw8697); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_BST_MODE_MASK, + AW8697_BIT_SYSCTRL_BST_MODE_BOOST); + break; + case AW8697_HAPTIC_RAM_LOOP_MODE: + aw8697->play_mode = AW8697_HAPTIC_RAM_LOOP_MODE; + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_PLAY_MODE_MASK, + AW8697_BIT_SYSCTRL_PLAY_MODE_RAM); + aw8697_haptic_active(aw8697); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_BST_MODE_MASK, + AW8697_BIT_SYSCTRL_BST_MODE_BYPASS); + break; + case AW8697_HAPTIC_RTP_MODE: + aw8697->play_mode = AW8697_HAPTIC_RTP_MODE; + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_PLAY_MODE_MASK, + AW8697_BIT_SYSCTRL_PLAY_MODE_RTP); + aw8697_haptic_active(aw8697); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_BST_MODE_MASK, + AW8697_BIT_SYSCTRL_BST_MODE_BOOST); + break; + case AW8697_HAPTIC_TRIG_MODE: + aw8697->play_mode = AW8697_HAPTIC_TRIG_MODE; + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_PLAY_MODE_MASK, + AW8697_BIT_SYSCTRL_PLAY_MODE_RAM); + aw8697_haptic_active(aw8697); + break; + case AW8697_HAPTIC_CONT_MODE: + aw8697->play_mode = AW8697_HAPTIC_CONT_MODE; + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_PLAY_MODE_MASK, + AW8697_BIT_SYSCTRL_PLAY_MODE_CONT); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_BST_MODE_MASK, + AW8697_BIT_SYSCTRL_BST_MODE_BYPASS); + aw8697_haptic_active(aw8697); + break; + default: + dev_err(aw8697->dev, "%s: play mode %d err", __func__, + play_mode); + break; + } + return 0; +} + +static int aw8697_haptic_play_go(struct aw8697 *aw8697, bool flag) +{ + if (flag == true) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_GO, AW8697_BIT_GO_MASK, + AW8697_BIT_GO_ENABLE); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_GO, AW8697_BIT_GO_MASK, + AW8697_BIT_GO_DISABLE); + } + return 0; +} + +static int aw8697_haptic_stop_delay(struct aw8697 *aw8697) +{ + unsigned char reg_val = 0; + unsigned int cnt = 100; + + while (cnt--) { + aw8697_i2c_read(aw8697, AW8697_REG_GLB_STATE, ®_val); + if ((reg_val & 0x0f) == 0x00) { + return 0; + } + msleep(2); + pr_debug("%s wait for standby, reg glb_state=0x%02x\n", + __func__, reg_val); + } + pr_err("%s do not enter standby automatically\n", __func__); + + return 0; +} + +static int aw8697_haptic_stop(struct aw8697 *aw8697) +{ + pr_debug("%s enter\n", __func__); + + aw8697_haptic_play_go(aw8697, false); + aw8697_haptic_stop_delay(aw8697); + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_STANDBY_MODE); + + return 0; +} + +static int aw8697_haptic_start(struct aw8697 *aw8697) +{ + pr_debug("%s enter\n", __func__); + + aw8697_haptic_play_go(aw8697, true); + + return 0; +} + +static int aw8697_haptic_set_wav_seq(struct aw8697 *aw8697, unsigned char wav, + unsigned char seq) +{ + aw8697_i2c_write(aw8697, AW8697_REG_WAVSEQ1 + wav, seq); + return 0; +} + +static int aw8697_haptic_set_wav_loop(struct aw8697 *aw8697, unsigned char wav, + unsigned char loop) +{ + unsigned char tmp = 0; + + if (wav % 2) { + tmp = loop << 0; + aw8697_i2c_write_bits(aw8697, AW8697_REG_WAVLOOP1 + (wav / 2), + AW8697_BIT_WAVLOOP_SEQNP1_MASK, tmp); + } else { + tmp = loop << 4; + aw8697_i2c_write_bits(aw8697, AW8697_REG_WAVLOOP1 + (wav / 2), + AW8697_BIT_WAVLOOP_SEQN_MASK, tmp); + } + + return 0; +} + +static int aw8697_haptic_set_repeat_wav_seq(struct aw8697 *aw8697, + unsigned char seq) +{ + aw8697_haptic_set_wav_seq(aw8697, 0x00, seq); + aw8697_haptic_set_wav_loop(aw8697, 0x00, + AW8697_BIT_WAVLOOP_INIFINITELY); + + return 0; +} + +static int aw8697_haptic_set_bst_vol(struct aw8697 *aw8697, + unsigned char bst_vol) +{ + if (bst_vol & 0xe0) { + bst_vol = 0x1f; + } + //printk("%s %d --\n", __func__, __LINE__); + aw8697_i2c_write_bits(aw8697, AW8697_REG_BSTDBG4, + AW8697_BIT_BSTDBG4_BSTVOL_MASK, (bst_vol << 1)); + return 0; +} + +static int aw8697_haptic_set_bst_peak_cur(struct aw8697 *aw8697, + unsigned char peak_cur) +{ + peak_cur &= AW8697_BSTCFG_PEAKCUR_LIMIT; + pr_info("%s %d enter\n", __func__, __LINE__); + aw8697_i2c_write_bits(aw8697, AW8697_REG_BSTCFG, + AW8697_BIT_BSTCFG_PEAKCUR_MASK, peak_cur); + return 0; +} + +static int aw8697_haptic_set_gain(struct aw8697 *aw8697, unsigned char gain) +{ + aw8697_i2c_write(aw8697, AW8697_REG_DATDBG, gain); + return 0; +} + +static int aw8697_haptic_set_pwm(struct aw8697 *aw8697, unsigned char mode) +{ + switch (mode) { + case AW8697_PWM_48K: + aw8697_i2c_write_bits(aw8697, AW8697_REG_PWMDBG, + AW8697_BIT_PWMDBG_PWM_MODE_MASK, + AW8697_BIT_PWMDBG_PWM_48K); + break; + case AW8697_PWM_24K: + aw8697_i2c_write_bits(aw8697, AW8697_REG_PWMDBG, + AW8697_BIT_PWMDBG_PWM_MODE_MASK, + AW8697_BIT_PWMDBG_PWM_24K); + break; + case AW8697_PWM_12K: + aw8697_i2c_write_bits(aw8697, AW8697_REG_PWMDBG, + AW8697_BIT_PWMDBG_PWM_MODE_MASK, + AW8697_BIT_PWMDBG_PWM_12K); + break; + default: + break; + } + return 0; +} + +static int aw8697_haptic_play_repeat_seq(struct aw8697 *aw8697, + unsigned char flag) +{ + pr_debug("%s enter\n", __func__); + + if (flag) { + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_RAM_LOOP_MODE); + aw8697_haptic_start(aw8697); + } + + return 0; +} + +/***************************************************** + * + * motor protect + * + *****************************************************/ +static int aw8697_haptic_swicth_motorprotect_config(struct aw8697 *aw8697, + unsigned char addr, + unsigned char val) +{ + pr_info("%s enter\n", __func__); + + if (addr == 1) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_DETCTRL, + AW8697_BIT_DETCTRL_PROTECT_MASK, + AW8697_BIT_DETCTRL_PROTECT_SHUTDOWN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_PWMPRC, + AW8697_BIT_PWMPRC_PRC_MASK, + AW8697_BIT_PWMPRC_PRC_ENABLE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_PRLVL, + AW8697_BIT_PRLVL_PR_MASK, + AW8697_BIT_PRLVL_PR_ENABLE); + } else if (addr == 0) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_DETCTRL, + AW8697_BIT_DETCTRL_PROTECT_MASK, + AW8697_BIT_DETCTRL_PROTECT_NO_ACTION); + aw8697_i2c_write_bits(aw8697, AW8697_REG_PWMPRC, + AW8697_BIT_PWMPRC_PRC_MASK, + AW8697_BIT_PWMPRC_PRC_DISABLE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_PRLVL, + AW8697_BIT_PRLVL_PR_MASK, + AW8697_BIT_PRLVL_PR_DISABLE); + } else if (addr == 0x2d) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_PWMPRC, + AW8697_BIT_PWMPRC_PRCTIME_MASK, val); + } else if (addr == 0x3e) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_PRLVL, + AW8697_BIT_PRLVL_PRLVL_MASK, val); + } else if (addr == 0x3f) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_PRTIME, + AW8697_BIT_PRTIME_PRTIME_MASK, val); + } else { + /*nothing to do; */ + } + return 0; +} + +/***************************************************** + * + * offset calibration + * + *****************************************************/ +static int aw8697_haptic_offset_calibration(struct aw8697 *aw8697) +{ + unsigned int cont = 2000; + unsigned char reg_val = 0; + + pr_info("%s enter\n", __func__); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_DETCTRL, + AW8697_BIT_DETCTRL_DIAG_GO_MASK, + AW8697_BIT_DETCTRL_DIAG_GO_ENABLE); + while (1) { + aw8697_i2c_read(aw8697, AW8697_REG_DETCTRL, ®_val); + if ((reg_val & 0x01) == 0 || cont == 0) + break; + cont--; + } + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_OFF); + + return 0; +} + +/***************************************************** + * + * trig config + * + *****************************************************/ + +static int aw8697_haptic_trig_param_init(struct aw8697 *aw8697) +{ + pr_info("%s enter\n", __func__); + + aw8697->trig[0].enable = aw8697->info.trig_config[0][0]; + aw8697->trig[0].default_level = aw8697->info.trig_config[0][1]; + aw8697->trig[0].dual_edge = aw8697->info.trig_config[0][2]; + aw8697->trig[0].frist_seq = aw8697->info.trig_config[0][3]; + aw8697->trig[0].second_seq = aw8697->info.trig_config[0][4]; + + aw8697->trig[1].enable = aw8697->info.trig_config[1][0]; + ; + aw8697->trig[1].default_level = aw8697->info.trig_config[1][1]; + aw8697->trig[1].dual_edge = aw8697->info.trig_config[1][2]; + aw8697->trig[1].frist_seq = aw8697->info.trig_config[1][3]; + aw8697->trig[1].second_seq = aw8697->info.trig_config[1][4]; + + aw8697->trig[2].enable = aw8697->info.trig_config[2][0]; + ; + aw8697->trig[2].default_level = aw8697->info.trig_config[2][1]; + aw8697->trig[2].dual_edge = aw8697->info.trig_config[2][2]; + aw8697->trig[2].frist_seq = aw8697->info.trig_config[2][3]; + aw8697->trig[2].second_seq = aw8697->info.trig_config[2][4]; + + return 0; +} + +static int aw8697_haptic_trig_param_config(struct aw8697 *aw8697) +{ + pr_info("%s enter\n", __func__); + + if (aw8697->trig[0].default_level) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG1_POLAR_MASK, + AW8697_BIT_TRGCFG1_TRG1_POLAR_NEG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG1_POLAR_MASK, + AW8697_BIT_TRGCFG1_TRG1_POLAR_POS); + } + if (aw8697->trig[1].default_level) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG2_POLAR_MASK, + AW8697_BIT_TRGCFG1_TRG2_POLAR_NEG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG2_POLAR_MASK, + AW8697_BIT_TRGCFG1_TRG2_POLAR_POS); + } + if (aw8697->trig[2].default_level) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG3_POLAR_MASK, + AW8697_BIT_TRGCFG1_TRG3_POLAR_NEG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG3_POLAR_MASK, + AW8697_BIT_TRGCFG1_TRG3_POLAR_POS); + } + + if (aw8697->trig[0].dual_edge) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG1_EDGE_MASK, + AW8697_BIT_TRGCFG1_TRG1_EDGE_POS_NEG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG1_EDGE_MASK, + AW8697_BIT_TRGCFG1_TRG1_EDGE_POS); + } + if (aw8697->trig[1].dual_edge) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG2_EDGE_MASK, + AW8697_BIT_TRGCFG1_TRG2_EDGE_POS_NEG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG2_EDGE_MASK, + AW8697_BIT_TRGCFG1_TRG2_EDGE_POS); + } + if (aw8697->trig[2].dual_edge) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG3_EDGE_MASK, + AW8697_BIT_TRGCFG1_TRG3_EDGE_POS_NEG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG1, + AW8697_BIT_TRGCFG1_TRG3_EDGE_MASK, + AW8697_BIT_TRGCFG1_TRG3_EDGE_POS); + } + + if (aw8697->trig[0].frist_seq) { + aw8697_i2c_write(aw8697, AW8697_REG_TRG1_WAV_P, + aw8697->trig[0].frist_seq); + } + if (aw8697->trig[0].second_seq && aw8697->trig[0].dual_edge) { + aw8697_i2c_write(aw8697, AW8697_REG_TRG1_WAV_N, + aw8697->trig[0].second_seq); + } + if (aw8697->trig[1].frist_seq) { + aw8697_i2c_write(aw8697, AW8697_REG_TRG2_WAV_P, + aw8697->trig[1].frist_seq); + } + if (aw8697->trig[1].second_seq && aw8697->trig[1].dual_edge) { + aw8697_i2c_write(aw8697, AW8697_REG_TRG2_WAV_N, + aw8697->trig[1].second_seq); + } + if (aw8697->trig[2].frist_seq) { + aw8697_i2c_write(aw8697, AW8697_REG_TRG3_WAV_P, + aw8697->trig[1].frist_seq); + } + if (aw8697->trig[2].second_seq && aw8697->trig[2].dual_edge) { + aw8697_i2c_write(aw8697, AW8697_REG_TRG3_WAV_N, + aw8697->trig[1].second_seq); + } + + return 0; +} + +static int aw8697_haptic_trig_enable_config(struct aw8697 *aw8697) +{ + pr_info("%s enter\n", __func__); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG2, + AW8697_BIT_TRGCFG2_TRG1_ENABLE_MASK, + aw8697->trig[0].enable); + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG2, + AW8697_BIT_TRGCFG2_TRG2_ENABLE_MASK, + aw8697->trig[1].enable); + aw8697_i2c_write_bits(aw8697, AW8697_REG_TRG_CFG2, + AW8697_BIT_TRGCFG2_TRG3_ENABLE_MASK, + aw8697->trig[2].enable); + + return 0; +} + +static int aw8697_haptic_auto_boost_config(struct aw8697 *aw8697, + unsigned char flag) +{ + aw8697->auto_boost = flag; + if (flag) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_BST_AUTO, + AW8697_BIT_BST_AUTO_BST_AUTOSW_MASK, + AW8697_BIT_BST_AUTO_BST_AUTOMATIC_BOOST); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_BST_AUTO, + AW8697_BIT_BST_AUTO_BST_AUTOSW_MASK, + AW8697_BIT_BST_AUTO_BST_MANUAL_BOOST); + } + return 0; +} + +/***************************************************** + * + * vbat mode + * + *****************************************************/ +static int aw8697_haptic_cont_vbat_mode(struct aw8697 *aw8697, + unsigned char flag) +{ + if (flag == AW8697_HAPTIC_CONT_VBAT_HW_COMP_MODE) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_ADCTEST, + AW8697_BIT_ADCTEST_VBAT_MODE_MASK, + AW8697_BIT_ADCTEST_VBAT_HW_COMP); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_ADCTEST, + AW8697_BIT_ADCTEST_VBAT_MODE_MASK, + AW8697_BIT_ADCTEST_VBAT_SW_COMP); + } + return 0; +} + +static int aw8697_haptic_get_vbat(struct aw8697 *aw8697) +{ + unsigned char reg_val = 0; + unsigned int cont = 2000; + + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_DETCTRL, + AW8697_BIT_DETCTRL_VBAT_GO_MASK, + AW8697_BIT_DETCTRL_VABT_GO_ENABLE); + + while (1) { + aw8697_i2c_read(aw8697, AW8697_REG_DETCTRL, ®_val); + if ((reg_val & 0x02) == 0 || cont == 0) + break; + cont--; + } + + aw8697_i2c_read(aw8697, AW8697_REG_VBATDET, ®_val); + aw8697->vbat = 6100 * reg_val / 256; + if (aw8697->vbat > AW8697_VBAT_MAX) { + aw8697->vbat = AW8697_VBAT_MAX; + pr_debug("%s vbat max limit = %dmV\n", __func__, aw8697->vbat); + } + if (aw8697->vbat < AW8697_VBAT_MIN) { + aw8697->vbat = AW8697_VBAT_MIN; + pr_debug("%s vbat min limit = %dmV\n", __func__, aw8697->vbat); + } + + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_OFF); + + return 0; +} + +static int aw8697_haptic_ram_vbat_comp(struct aw8697 *aw8697, bool flag) +{ + int temp_gain = 0; + //pr_info("%s %d enter\n", __func__, __LINE__); + if (flag) { + if (aw8697->ram_vbat_comp == + AW8697_HAPTIC_RAM_VBAT_COMP_ENABLE) { + aw8697_haptic_get_vbat(aw8697); + temp_gain = + aw8697->gain * AW8697_VBAT_REFER / aw8697->vbat; + if (temp_gain > + (128 * AW8697_VBAT_REFER / AW8697_VBAT_MIN)) { + temp_gain = 128 * AW8697_VBAT_REFER / + AW8697_VBAT_MIN; + pr_debug("%s gain limit=%d\n", __func__, + temp_gain); + } + aw8697_haptic_set_gain(aw8697, temp_gain); + } else { + aw8697_haptic_set_gain(aw8697, aw8697->gain); + } + } else { + aw8697_haptic_set_gain(aw8697, aw8697->gain); + } + + return 0; +} + +/***************************************************** + * + * f0 + * + *****************************************************/ +static int aw8697_haptic_set_f0_preset(struct aw8697 *aw8697) +{ + unsigned int f0_reg = 0; + + pr_info("%s enter\n", __func__); + + f0_reg = 1000000000 / (aw8697->info.f0_pre * aw8697->info.f0_coeff); + aw8697_i2c_write(aw8697, AW8697_REG_F_PRE_H, + (unsigned char)((f0_reg >> 8) & 0xff)); + aw8697_i2c_write(aw8697, AW8697_REG_F_PRE_L, + (unsigned char)((f0_reg >> 0) & 0xff)); + + return 0; +} + +#ifndef USE_CONT_F0_CALI +static int aw8697_haptic_read_f0(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char reg_val = 0; + unsigned int f0_reg = 0; + unsigned long f0_tmp = 0; + + pr_info("%s enter\n", __func__); + + ret = aw8697_i2c_read(aw8697, AW8697_REG_F_LRA_F0_H, ®_val); + f0_reg = (reg_val << 8); + ret = aw8697_i2c_read(aw8697, AW8697_REG_F_LRA_F0_L, ®_val); + f0_reg |= (reg_val << 0); + if (!f0_reg) { + pr_info("%s: not get f0_reg value is 0!\n", __func__); + return 0; + } + f0_tmp = 1000000000 / (f0_reg * aw8697->info.f0_coeff); + aw8697->f0 = (unsigned int)f0_tmp; + pr_info("%s f0=%d\n", __func__, aw8697->f0); + + return 0; +} +#endif + +#ifndef USE_CONT_F0_CALI +static int aw8697_haptic_read_cont_f0(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char reg_val = 0; + unsigned int f0_reg = 0; + unsigned long f0_tmp = 0; + + pr_debug("%s enter\n", __func__); + + ret = aw8697_i2c_read(aw8697, AW8697_REG_F_LRA_CONT_H, ®_val); + f0_reg = (reg_val << 8); + ret = aw8697_i2c_read(aw8697, AW8697_REG_F_LRA_CONT_L, ®_val); + f0_reg |= (reg_val << 0); + if (!f0_reg) { + pr_info("%s: not get f0_reg value is 0!\n", __func__); + return 0; + } + f0_tmp = 1000000000 / (f0_reg * aw8697->info.f0_coeff); + aw8697->cont_f0 = (unsigned int)f0_tmp; + pr_info("%s f0=%d\n", __func__, aw8697->cont_f0); + + return 0; +} +#else +static int aw8697_haptic_read_cont_f0(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char reg_val = 0; + unsigned int f0_reg = 0; + unsigned long f0_tmp = 0; + + pr_debug("%s enter\n", __func__); + + ret = aw8697_i2c_read(aw8697, AW8697_REG_F_LRA_CONT_H, ®_val); + f0_reg = (reg_val << 8); + ret = aw8697_i2c_read(aw8697, AW8697_REG_F_LRA_CONT_L, ®_val); + f0_reg |= (reg_val << 0); + if (!f0_reg) { + pr_info("%s: not get f0_reg value is 0!\n", __func__); + return 0; + } + f0_tmp = 1000000000 / (f0_reg * aw8697->info.f0_coeff); + aw8697->cont_f0 = (unsigned int)f0_tmp; + aw8697->cont_f0 -= 12; + aw8697->f0 = aw8697->cont_f0; + pr_info("%s f0=%d\n", __func__, aw8697->cont_f0); + + return 0; +} +#endif + +#ifndef USE_CONT_F0_CALI +static int aw8697_haptic_read_beme(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char reg_val = 0; + pr_info("%s %d enter\n", __func__, __LINE__); + ret = aw8697_i2c_read(aw8697, AW8697_REG_WAIT_VOL_MP, ®_val); + aw8697->max_pos_beme = (reg_val << 0); + ret = aw8697_i2c_read(aw8697, AW8697_REG_WAIT_VOL_MN, ®_val); + aw8697->max_neg_beme = (reg_val << 0); + + pr_info("%s max_pos_beme=%d\n", __func__, aw8697->max_pos_beme); + pr_info("%s max_neg_beme=%d\n", __func__, aw8697->max_neg_beme); + + return 0; +} +#else +static int aw8697_haptic_read_cont_bemf(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char reg_val = 0; + unsigned int bemf = 0; + + ret = aw8697_i2c_read(aw8697, AW8697_REG_BEMF_VOL_H, ®_val); + bemf |= (reg_val << 8); + ret = aw8697_i2c_read(aw8697, AW8697_REG_BEMF_VOL_L, ®_val); + bemf |= (reg_val << 0); + + pr_info("%s bemf=%d\n", __func__, bemf); + + return 0; +} +#endif + +/***************************************************** + * + * rtp + * + *****************************************************/ +static void aw8697_haptic_set_rtp_aei(struct aw8697 *aw8697, bool flag) +{ + if (flag) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_FF_AE_MASK, + AW8697_BIT_SYSINTM_FF_AE_EN); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_FF_AE_MASK, + AW8697_BIT_SYSINTM_FF_AE_OFF); + } +} + +static unsigned char aw8697_haptic_rtp_get_fifo_afi(struct aw8697 *aw8697) +{ + unsigned char ret = 0; + unsigned char reg_val = 0; + + if (aw8697->osc_cali_flag == 1) { + aw8697_i2c_read(aw8697, AW8697_REG_SYSST, ®_val); + reg_val &= AW8697_BIT_SYSST_FF_AFS; + ret = reg_val >> 3; + } else { + aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + reg_val &= AW8697_BIT_SYSINT_FF_AFI; + ret = reg_val >> 3; + } + + return ret; +} + +/***************************************************** + * + * rtp + * + *****************************************************/ +static int aw8697_haptic_rtp_init(struct aw8697 *aw8697) +{ + unsigned int buf_len = 0; + unsigned int period_size = aw8697->ram.base_addr >> 2; + bool rtp_start = true; + pm_qos_add_request(&pm_qos_req_vb, PM_QOS_CPU_DMA_LATENCY, + PM_QOS_VALUE_VB); + aw8697->rtp_cnt = 0; + while ((!aw8697_haptic_rtp_get_fifo_afi(aw8697)) && + (aw8697->play_mode == AW8697_HAPTIC_RTP_MODE) && + !atomic_read(&aw8697->exit_in_rtp_loop)) { + if (aw8697->is_custom_wave == 0) { + if (rtp_start) { + if ((aw8697_rtp->len - aw8697->rtp_cnt) < + aw8697->ram.base_addr) + buf_len = aw8697_rtp->len - + aw8697->rtp_cnt; + else + buf_len = (aw8697->ram.base_addr); + aw8697_i2c_writes( + aw8697, AW8697_REG_RTP_DATA, + &aw8697_rtp->data[aw8697->rtp_cnt], + buf_len); + rtp_start = false; + } else { + if ((aw8697_rtp->len - aw8697->rtp_cnt) < + (aw8697->ram.base_addr >> 2)) { + buf_len = aw8697_rtp->len - + aw8697->rtp_cnt; + } else { + buf_len = (aw8697->ram.base_addr >> 2); + } + aw8697_i2c_writes( + aw8697, AW8697_REG_RTP_DATA, + &aw8697_rtp->data[aw8697->rtp_cnt], + buf_len); + } + aw8697->rtp_cnt += buf_len; + pr_info("%s update rtp_cnt = %d \n", __func__, + aw8697->rtp_cnt); + if (aw8697->rtp_cnt == aw8697_rtp->len) { + aw8697->rtp_cnt = 0; + aw8697_haptic_set_rtp_aei(aw8697, false); + pm_qos_remove_request(&pm_qos_req_vb); + return 0; + } + } else { + buf_len = read_rb(aw8697_rtp->data, period_size); + aw8697_i2c_writes(aw8697, AW8697_REG_RTP_DATA, + aw8697_rtp->data, buf_len); + if (buf_len < period_size) { + pr_info("%s: custom rtp update complete\n", + __func__); + aw8697->rtp_cnt = 0; + aw8697_haptic_set_rtp_aei(aw8697, false); + pm_qos_remove_request(&pm_qos_req_vb); + return 0; + } + } + } + if (aw8697->play_mode == AW8697_HAPTIC_RTP_MODE && + !atomic_read(&aw8697->exit_in_rtp_loop)) { + aw8697_haptic_set_rtp_aei(aw8697, true); + } + pr_info("%s: exit\n", __func__); + pm_qos_remove_request(&pm_qos_req_vb); + return 0; +} + +static int16_t aw8697_haptic_effect_strength(struct aw8697 *aw8697) +{ + pr_debug("%s enter\n", __func__); + pr_debug("%s: aw8697->play.vmax_mv =0x%x\n", __func__, + aw8697->play.vmax_mv); +#if 0 + switch (aw8697->play.vmax_mv) { + case AW8697_LIGHT_MAGNITUDE: + aw8697->level = 0x80; + break; + case AW8697_MEDIUM_MAGNITUDE: + aw8697->level = 0x50; + break; + case AW8697_STRONG_MAGNITUDE: + aw8697->level = 0x30; + break; + default: + break; + } +#else + if (aw8697->play.vmax_mv >= 0x7FFF) + aw8697->level = 0x80; /*128*/ + else if (aw8697->play.vmax_mv <= 0x3FFF) + aw8697->level = 0x1E; /*30*/ + else + aw8697->level = (aw8697->play.vmax_mv - 16383) / 128; + if (aw8697->level < 0x1E) + aw8697->level = 0x1E; /*30*/ +#endif + + pr_info("%s: aw8697->level =0x%x\n", __func__, aw8697->level); + return 0; +} + +static int aw8697_haptic_play_effect_seq(struct aw8697 *aw8697, + unsigned char flag) +{ + if (aw8697->effect_id > aw8697->info.effect_id_boundary) + return 0; + //printk("%s:aw8697->effect_id =%d\n", __func__, aw8697->effect_id); + //printk("%s:aw8697->activate_mode =%d\n", __func__, aw8697->activate_mode); + + if (flag) { + if (aw8697->activate_mode == AW8697_HAPTIC_ACTIVATE_RAM_MODE) { + aw8697_haptic_set_wav_seq(aw8697, 0x00, + (char)aw8697->effect_id + 1); + aw8697_haptic_set_wav_seq(aw8697, 0x01, 0x00); + aw8697_haptic_set_wav_loop(aw8697, 0x00, 0x00); + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_RAM_MODE); + if (aw8697->info.bst_vol_ram <= AW8697_MAX_BST_VO) + aw8697_haptic_set_bst_vol( + aw8697, aw8697->info.bst_vol_ram); + else + aw8697_haptic_set_bst_vol(aw8697, aw8697->vmax); + aw8697_haptic_effect_strength(aw8697); + aw8697_haptic_set_gain(aw8697, aw8697->level); + aw8697_haptic_start(aw8697); + } + if (aw8697->activate_mode == + AW8697_HAPTIC_ACTIVATE_RAM_LOOP_MODE) { + aw8697_haptic_set_repeat_wav_seq( + aw8697, (aw8697->info.effect_id_boundary + 1)); + aw8697_haptic_play_repeat_seq(aw8697, true); + } + } + + return 0; +} + +static void aw8697_haptic_upload_lra(struct aw8697 *aw8697, unsigned char flag) +{ + if (flag) { + //printk("%s f0_cali_lra=%d\n", __func__, aw8697->f0_calib_data); + aw8697_i2c_write(aw8697, AW8697_REG_TRIM_LRA, + (char)aw8697->f0_calib_data); + } else { + //printk("%s rtp_cali_lra=%d\n", __func__, aw8697->lra_calib_data); + aw8697_i2c_write(aw8697, AW8697_REG_TRIM_LRA, + (char)aw8697->lra_calib_data); + } +} + +static int aw8697_clock_OSC_trim_calibration(unsigned long int theory_time, + unsigned long int real_time) +{ + unsigned int real_code = 0; + unsigned int LRA_TRIM_CODE = 0; + unsigned int DFT_LRA_TRIM_CODE = 0; + unsigned int Not_need_cali_threshold = + 10; /*0.1 percent not need calibrate*/ + + if (theory_time == real_time) { + pr_info("aw_osctheory_time == real_time:%ld theory_time = %ld not need to cali\n", + real_time, theory_time); + return 0; + } else if (theory_time < real_time) { + if ((real_time - theory_time) > (theory_time / 50)) { + pr_info("aw_osc(real_time - theory_time) > (theory_time/50) not to cali\n"); + return DFT_LRA_TRIM_CODE; + } + + if ((real_time - theory_time) < + (Not_need_cali_threshold * theory_time / 10000)) { + pr_info("aw_oscmicrosecond:%ld theory_time = %ld not need to cali\n", + real_time, theory_time); + return DFT_LRA_TRIM_CODE; + } + + real_code = ((real_time - theory_time) * 4000) / theory_time; + real_code = ((real_code % 10 < 5) ? 0 : 1) + real_code / 10; + real_code = 32 + real_code; + } else if (theory_time > real_time) { + if ((theory_time - real_time) > (theory_time / 50)) { + pr_info("aw_osc((theory_time - real_time) > (theory_time / 50)) not to cali\n"); + return DFT_LRA_TRIM_CODE; + } + if ((theory_time - real_time) < + (Not_need_cali_threshold * theory_time / 10000)) { + pr_info("aw_oscmicrosecond:%ld theory_time = %ld not need to cali\n", + real_time, theory_time); + return DFT_LRA_TRIM_CODE; + } + real_code = ((theory_time - real_time) * 4000) / theory_time; + real_code = ((real_code % 10 < 5) ? 0 : 1) + real_code / 10; + real_code = 32 - real_code; + } + if (real_code > 31) + LRA_TRIM_CODE = real_code - 32; + else + LRA_TRIM_CODE = real_code + 32; + pr_info("aw_oscmicrosecond:%ld theory_time = %ld real_code =0X%02X LRA_TRIM_CODE 0X%02X\n", + real_time, theory_time, real_code, LRA_TRIM_CODE); + + return LRA_TRIM_CODE; +} + +static int aw8697_rtp_trim_lra_calibration(struct aw8697 *aw8697) +{ + unsigned char reg_val = 0; + unsigned int fre_val = 0; + unsigned int theory_time = 0; + unsigned int lra_rtim_code = 0; + + aw8697_i2c_read(aw8697, AW8697_REG_PWMDBG, ®_val); + fre_val = (reg_val & 0x006f) >> 5; + + if (fre_val == 3) + theory_time = (aw8697->rtp_len / 12000) * 1000000; /*12K */ + if (fre_val == 2) + theory_time = (aw8697->rtp_len / 24000) * 1000000; /*24K */ + if (fre_val == 1 || fre_val == 0) + theory_time = (aw8697->rtp_len / 48000) * 1000000; /*48K */ + + printk("microsecond:%ld theory_time = %d\n", aw8697->microsecond, + theory_time); + + lra_rtim_code = aw8697_clock_OSC_trim_calibration(theory_time, + aw8697->microsecond); + if (lra_rtim_code > 0) { + aw8697->lra_calib_data = lra_rtim_code; + aw8697_i2c_write(aw8697, AW8697_REG_TRIM_LRA, + (char)lra_rtim_code); + } + return 0; +} +static unsigned char aw8697_haptic_osc_read_int(struct aw8697 *aw8697) +{ + unsigned char reg_val = 0; + + aw8697_i2c_read(aw8697, AW8697_REG_DBGSTAT, ®_val); + return reg_val; +} + +static int aw8697_rtp_osc_calibration(struct aw8697 *aw8697) +{ + const struct firmware *rtp_file; + int ret = -1; + unsigned int buf_len = 0; + unsigned char osc_int_state = 0; + aw8697->rtp_cnt = 0; + aw8697->timeval_flags = 1; + aw8697->osc_cali_flag = 1; + + pr_info("%s enter\n", __func__); + /* fw loaded */ + ret = request_firmware(&rtp_file, + aw8697_rtp_name[/*aw8697->rtp_file_num*/ 0], + aw8697->dev); + if (ret < 0) { + pr_err("%s: failed to read %s\n", __func__, + aw8697_rtp_name[/*aw8697->rtp_file_num*/ 0]); + return ret; + } + /*awinic add stop,for irq interrupt during calibrate*/ + aw8697_haptic_stop(aw8697); + aw8697->rtp_init = 0; + mutex_lock(&aw8697->rtp_lock); + vfree(aw8697_rtp); + aw8697_rtp = vmalloc(rtp_file->size + sizeof(int)); + if (!aw8697_rtp) { + release_firmware(rtp_file); + mutex_unlock(&aw8697->rtp_lock); + pr_err("%s: error allocating memory\n", __func__); + return -ENOMEM; + } + aw8697_rtp->len = rtp_file->size; + aw8697->rtp_len = rtp_file->size; + pr_info("%s: rtp file [%s] size = %d\n", __func__, + aw8697_rtp_name[/*aw8697->rtp_file_num*/ 0], aw8697_rtp->len); + memcpy(aw8697_rtp->data, rtp_file->data, rtp_file->size); + release_firmware(rtp_file); + mutex_unlock(&aw8697->rtp_lock); + + /* gain */ + aw8697_haptic_ram_vbat_comp(aw8697, false); + + /* rtp mode config */ + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_RTP_MODE); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_DBGCTRL, + AW8697_BIT_DBGCTRL_INT_MODE_MASK, + AW8697_BIT_DBGCTRL_INT_MODE_EDGE); + disable_irq(gpio_to_irq(aw8697->irq_gpio)); + /* haptic start */ + aw8697_haptic_start(aw8697); + pm_qos_add_request(&pm_qos_req_vb, PM_QOS_CPU_DMA_LATENCY, + PM_QOS_VALUE_VB); + while (1) { + if (!aw8697_haptic_rtp_get_fifo_afi(aw8697)) { + mutex_lock(&aw8697->rtp_lock); + if ((aw8697_rtp->len - aw8697->rtp_cnt) < + (aw8697->ram.base_addr >> 2)) + buf_len = aw8697_rtp->len - aw8697->rtp_cnt; + else + buf_len = (aw8697->ram.base_addr >> 2); + if (aw8697->rtp_cnt != aw8697_rtp->len) { + if (aw8697->timeval_flags == 1) { + do_gettimeofday(&aw8697->start); + aw8697->timeval_flags = 0; + } + aw8697_i2c_writes( + aw8697, AW8697_REG_RTP_DATA, + &aw8697_rtp->data[aw8697->rtp_cnt], + buf_len); + aw8697->rtp_cnt += buf_len; + } + mutex_unlock(&aw8697->rtp_lock); + } + osc_int_state = aw8697_haptic_osc_read_int(aw8697); + if (osc_int_state & AW8697_BIT_SYSINT_DONEI) { + do_gettimeofday(&aw8697->end); + pr_info("%s vincent playback done aw8697->rtp_cnt= %d \n", + __func__, aw8697->rtp_cnt); + break; + } + + do_gettimeofday(&aw8697->end); + aw8697->microsecond = + (aw8697->end.tv_sec - aw8697->start.tv_sec) * 1000000 + + (aw8697->end.tv_usec - aw8697->start.tv_usec); + if (aw8697->microsecond > OSC_CALIBRATION_T_LENGTH) { + pr_info("%s vincent time out aw8697->rtp_cnt %d osc_int_state %02x\n", + __func__, aw8697->rtp_cnt, osc_int_state); + break; + } + } + pm_qos_remove_request(&pm_qos_req_vb); + enable_irq(gpio_to_irq(aw8697->irq_gpio)); + + aw8697->osc_cali_flag = 0; + aw8697->microsecond = + (aw8697->end.tv_sec - aw8697->start.tv_sec) * 1000000 + + (aw8697->end.tv_usec - aw8697->start.tv_usec); + /*calibration osc*/ + pr_info("%s 2018_microsecond:%ld \n", __func__, aw8697->microsecond); + pr_info("%s exit\n", __func__); + return 0; +} + +static void aw8697_rtp_work_routine(struct work_struct *work) +{ + const struct firmware *rtp_file; + int ret = -1; + struct aw8697 *aw8697 = container_of(work, struct aw8697, rtp_work); + + if ((aw8697->effect_id < aw8697->info.effect_id_boundary) && + (aw8697->effect_id > aw8697->info.effect_max)) + return; + + pr_info("%s: effect_id = %d state=%d activate_mode = %d\n", __func__, + aw8697->effect_id, aw8697->state, aw8697->activate_mode); + mutex_lock(&aw8697->lock); + aw8697_haptic_upload_lra(aw8697, false); + aw8697_haptic_set_rtp_aei(aw8697, false); + aw8697_interrupt_clear(aw8697); + //wait for irq to exit + atomic_set(&aw8697->exit_in_rtp_loop, 1); + while (atomic_read(&aw8697->is_in_rtp_loop)) { + pr_info("%s goint to waiting irq exit\n", __func__); + mutex_unlock(&aw8697->lock); + ret = wait_event_interruptible( + aw8697->wait_q, + atomic_read(&aw8697->is_in_rtp_loop) == 0); + pr_info("%s wakeup \n", __func__); + mutex_lock(&aw8697->lock); + if (ret == -ERESTARTSYS) { + atomic_set(&aw8697->exit_in_rtp_loop, 0); + wake_up_interruptible(&aw8697->stop_wait_q); + mutex_unlock(&aw8697->lock); + pr_err("%s wake up by signal return erro\n", __func__); + return; + } + } + atomic_set(&aw8697->exit_in_rtp_loop, 0); + wake_up_interruptible(&aw8697->stop_wait_q); + //how to force exit this call + if (aw8697->is_custom_wave == 1 && aw8697->state) { + pr_err("%s buffer size %d, availbe size %d \n", __func__, + aw8697->ram.base_addr >> 2, get_rb_avalible_size()); + while (get_rb_avalible_size() < aw8697->ram.base_addr && + !rb_shoule_exit()) { + mutex_unlock(&aw8697->lock); + ret = wait_event_interruptible( + aw8697->stop_wait_q, (get_rb_avalible_size() >= + aw8697->ram.base_addr) || + rb_shoule_exit()); + mutex_lock(&aw8697->lock); + pr_info("%s wakeup \n", __func__); + pr_err("%s after wakeup sbuffer size %d, availbe size %d \n", + __func__, aw8697->ram.base_addr >> 2, + get_rb_avalible_size()); + if (ret == -ERESTARTSYS) { + mutex_unlock(&aw8697->lock); + pr_err("%s wake up by signal return erro\n", + __func__); + return; + } + } + } + aw8697_haptic_stop(aw8697); + + if (aw8697->state) { + pm_stay_awake(aw8697->dev); + if (aw8697->info.bst_vol_ram <= AW8697_MAX_BST_VO) + aw8697_haptic_set_bst_vol(aw8697, + aw8697->info.bst_vol_ram); + else + aw8697_haptic_set_bst_vol(aw8697, aw8697->vmax); + aw8697_haptic_effect_strength(aw8697); + aw8697_haptic_set_gain(aw8697, aw8697->level); + aw8697->rtp_init = 0; + if (aw8697->is_custom_wave == 0) { + aw8697->rtp_file_num = aw8697->effect_id - + aw8697->info.effect_id_boundary; + printk("%s: aw8697->rtp_file_num =%d\n", __func__, + aw8697->rtp_file_num); + if (aw8697->rtp_file_num < 0) + aw8697->rtp_file_num = 0; + if (aw8697->rtp_file_num > + ((sizeof(aw8697_rtp_name) / AW8697_RTP_NAME_MAX) - + 1)) + aw8697->rtp_file_num = + (sizeof(aw8697_rtp_name) / + AW8697_RTP_NAME_MAX) - + 1; + + /* fw loaded */ + ret = request_firmware( + &rtp_file, + aw8697_rtp_name[aw8697->rtp_file_num], + aw8697->dev); + if (ret < 0) { + pr_err("%s: failed to read %s\n", __func__, + aw8697_rtp_name[aw8697->rtp_file_num]); + pm_relax(aw8697->dev); + mutex_unlock(&aw8697->lock); + return; + } + + vfree(aw8697_rtp); + aw8697_rtp = vmalloc(rtp_file->size + sizeof(int)); + if (!aw8697_rtp) { + release_firmware(rtp_file); + pr_err("%s: error allocating memory\n", + __func__); + pm_relax(aw8697->dev); + mutex_unlock(&aw8697->lock); + return; + } + aw8697_rtp->len = rtp_file->size; + pr_info("%s: rtp file [%s] size = %d\n", __func__, + aw8697_rtp_name[aw8697->rtp_file_num], + aw8697_rtp->len); + memcpy(aw8697_rtp->data, rtp_file->data, + rtp_file->size); + release_firmware(rtp_file); + } else { + vfree(aw8697_rtp); + aw8697_rtp = vmalloc(aw8697->ram.base_addr >> 2); + if (!aw8697_rtp) { + pr_err("%s: error allocating memory\n", + __func__); + pm_relax(aw8697->dev); + mutex_unlock(&aw8697->lock); + return; + } + } + aw8697->rtp_init = 1; + + /* rtp mode config */ + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_RTP_MODE); + + /* haptic start */ + aw8697_haptic_start(aw8697); + + aw8697_haptic_rtp_init(aw8697); + } else { + aw8697->rtp_cnt = 0; + aw8697->rtp_init = 0; + pm_relax(aw8697->dev); + } + mutex_unlock(&aw8697->lock); +} + +static enum hrtimer_restart +aw8697_haptic_audio_timer_func(struct hrtimer *timer) +{ + struct aw8697 *aw8697 = + container_of(timer, struct aw8697, haptic_audio.timer); + + pr_debug("%s enter\n", __func__); + //schedule_work(&aw8697->haptic_audio.work); + queue_work(aw8697->work_queue, &aw8697->haptic_audio.work); + + hrtimer_start( + &aw8697->haptic_audio.timer, + ktime_set(aw8697->haptic_audio.timer_val / 1000000, + (aw8697->haptic_audio.timer_val % 1000000) * 1000), + HRTIMER_MODE_REL); + return HRTIMER_NORESTART; +} + +static void aw8697_haptic_audio_work_routine(struct work_struct *work) +{ + struct aw8697 *aw8697 = + container_of(work, struct aw8697, haptic_audio.work); + + pr_info("%s enter\n", __func__); + + mutex_lock(&aw8697->haptic_audio.lock); + memcpy(&aw8697->haptic_audio.ctr, + &aw8697->haptic_audio.data[aw8697->haptic_audio.cnt], + sizeof(struct haptic_ctr)); + pr_debug("%s: cnt=%d, cmd=%d, play=%d, wavseq=%d, loop=%d, gain=%d\n", + __func__, aw8697->haptic_audio.cnt, + aw8697->haptic_audio.ctr.cmd, aw8697->haptic_audio.ctr.play, + aw8697->haptic_audio.ctr.wavseq, aw8697->haptic_audio.ctr.loop, + aw8697->haptic_audio.ctr.gain); + mutex_unlock(&aw8697->haptic_audio.lock); + if (AW8697_HAPTIC_CMD_ENABLE == aw8697->haptic_audio.ctr.cmd) { + if (AW8697_HAPTIC_PLAY_ENABLE == + aw8697->haptic_audio.ctr.play) { + pr_info("%s: haptic_audio_play_start\n", __func__); + mutex_lock(&aw8697->lock); + aw8697_haptic_stop(aw8697); + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_RAM_MODE); + + aw8697_haptic_set_wav_seq( + aw8697, 0x00, aw8697->haptic_audio.ctr.wavseq); + aw8697_haptic_set_wav_seq(aw8697, 0x01, 0x00); + + aw8697_haptic_set_wav_loop( + aw8697, 0x00, aw8697->haptic_audio.ctr.loop); + + aw8697_haptic_set_gain(aw8697, + aw8697->haptic_audio.ctr.gain); + + aw8697_haptic_start(aw8697); + mutex_unlock(&aw8697->lock); + } else if (AW8697_HAPTIC_PLAY_STOP == + aw8697->haptic_audio.ctr.play) { + mutex_lock(&aw8697->lock); + aw8697_haptic_stop(aw8697); + mutex_unlock(&aw8697->lock); + } else if (AW8697_HAPTIC_PLAY_GAIN == + aw8697->haptic_audio.ctr.play) { + mutex_lock(&aw8697->lock); + aw8697_haptic_set_gain(aw8697, + aw8697->haptic_audio.ctr.gain); + mutex_unlock(&aw8697->lock); + } + mutex_lock(&aw8697->haptic_audio.lock); + memset(&aw8697->haptic_audio.data[aw8697->haptic_audio.cnt], 0, + sizeof(struct haptic_ctr)); + mutex_unlock(&aw8697->haptic_audio.lock); + } + + mutex_lock(&aw8697->haptic_audio.lock); + aw8697->haptic_audio.cnt++; + if (aw8697->haptic_audio.data[aw8697->haptic_audio.cnt].cmd == 0) { + aw8697->haptic_audio.cnt = 0; + pr_debug("%s: haptic play buffer restart\n", __func__); + } + mutex_unlock(&aw8697->haptic_audio.lock); +} + +/***************************************************** + * + * haptic cont + * + *****************************************************/ +static int aw8697_haptic_cont(struct aw8697 *aw8697) +{ + pr_info("%s enter\n", __func__); + + /* work mode */ + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_CONT_MODE); + + /* preset f0 */ + aw8697_haptic_set_f0_preset(aw8697); + + /* lpf */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_DATCTRL, + AW8697_BIT_DATCTRL_FC_MASK, + AW8697_BIT_DATCTRL_FC_1000HZ); + aw8697_i2c_write_bits(aw8697, AW8697_REG_DATCTRL, + AW8697_BIT_DATCTRL_LPF_ENABLE_MASK, + AW8697_BIT_DATCTRL_LPF_ENABLE); + + /* cont config */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_ZC_DETEC_MASK, + AW8697_BIT_CONT_CTRL_ZC_DETEC_ENABLE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_WAIT_PERIOD_MASK, + AW8697_BIT_CONT_CTRL_WAIT_1PERIOD); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_MODE_MASK, + AW8697_BIT_CONT_CTRL_BY_GO_SIGNAL); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_EN_CLOSE_MASK, + AW8697_CONT_PLAYBACK_MODE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_F0_DETECT_MASK, + AW8697_BIT_CONT_CTRL_F0_DETECT_DISABLE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_O2C_MASK, + AW8697_BIT_CONT_CTRL_O2C_DISABLE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_AUTO_BRK_MASK, + AW8697_BIT_CONT_CTRL_AUTO_BRK_ENABLE); + + /* TD time */ + aw8697_i2c_write(aw8697, AW8697_REG_TD_H, + (unsigned char)(aw8697->info.cont_td >> 8)); + aw8697_i2c_write(aw8697, AW8697_REG_TD_L, + (unsigned char)(aw8697->info.cont_td >> 0)); + aw8697_i2c_write(aw8697, AW8697_REG_TSET, aw8697->info.tset); + + /* zero cross */ + aw8697_i2c_write(aw8697, AW8697_REG_ZC_THRSH_H, + (unsigned char)(aw8697->info.cont_zc_thr >> 8)); + aw8697_i2c_write(aw8697, AW8697_REG_ZC_THRSH_L, + (unsigned char)(aw8697->info.cont_zc_thr >> 0)); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_BEMF_NUM, + AW8697_BIT_BEMF_NUM_BRK_MASK, + aw8697->info.cont_num_brk); + aw8697_i2c_write(aw8697, AW8697_REG_TIME_NZC, 0x23); // 35*171us=5.985ms + + /* f0 driver level */ + aw8697_i2c_write(aw8697, AW8697_REG_DRV_LVL, aw8697->info.cont_drv_lvl); + aw8697_i2c_write(aw8697, AW8697_REG_DRV_LVL_OV, + aw8697->info.cont_drv_lvl_ov); + + /* cont play go */ + aw8697_haptic_play_go(aw8697, true); + + return 0; +} + +#ifndef USE_CONT_F0_CALI +/***************************************************** + * + * haptic f0 cali + * + *****************************************************/ +static int aw8697_haptic_get_f0(struct aw8697 *aw8697) +{ + int ret = 0; + /*unsigned char i = 0; */ + unsigned char reg_val = 0; + unsigned char f0_pre_num = 0; + unsigned char f0_wait_num = 0; + unsigned char f0_repeat_num = 0; + unsigned char f0_trace_num = 0; + unsigned int t_f0_ms = 0; + unsigned int t_f0_trace_ms = 0; + /*unsigned int f0_cali_cnt = 50; */ + + pr_info("%s enter\n", __func__); + + aw8697->f0 = aw8697->info.f0_pre; + + /* f0 calibrate work mode */ + aw8697_haptic_stop(aw8697); + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_CONT_MODE); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_EN_CLOSE_MASK, + AW8697_BIT_CONT_CTRL_OPEN_PLAYBACK); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_F0_DETECT_MASK, + AW8697_BIT_CONT_CTRL_F0_DETECT_ENABLE); + + /* LPF */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_DATCTRL, + AW8697_BIT_DATCTRL_FC_MASK, + AW8697_BIT_DATCTRL_FC_1000HZ); + aw8697_i2c_write_bits(aw8697, AW8697_REG_DATCTRL, + AW8697_BIT_DATCTRL_LPF_ENABLE_MASK, + AW8697_BIT_DATCTRL_LPF_ENABLE); + + /* LRA OSC Source */ + if (aw8697->f0_cali_flag == AW8697_HAPTIC_CALI_F0) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_ANACTRL, + AW8697_BIT_ANACTRL_LRA_SRC_MASK, + AW8697_BIT_ANACTRL_LRA_SRC_REG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_ANACTRL, + AW8697_BIT_ANACTRL_LRA_SRC_MASK, + AW8697_BIT_ANACTRL_LRA_SRC_EFUSE); + } + + /* preset f0 */ + aw8697_haptic_set_f0_preset(aw8697); + + /* f0 driver level */ + aw8697_i2c_write(aw8697, AW8697_REG_DRV_LVL, aw8697->info.cont_drv_lvl); + + /* f0 trace parameter */ + f0_pre_num = aw8697->info.f0_trace_parameter[0]; + f0_wait_num = aw8697->info.f0_trace_parameter[1]; + f0_repeat_num = aw8697->info.f0_trace_parameter[2]; + f0_trace_num = aw8697->info.f0_trace_parameter[3]; + aw8697_i2c_write(aw8697, AW8697_REG_NUM_F0_1, + (f0_pre_num << 4) | (f0_wait_num << 0)); + aw8697_i2c_write(aw8697, AW8697_REG_NUM_F0_2, (f0_repeat_num << 0)); + aw8697_i2c_write(aw8697, AW8697_REG_NUM_F0_3, (f0_trace_num << 0)); + + /* clear aw8697 interrupt */ + ret = aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + + /* play go and start f0 calibration */ + aw8697_haptic_play_go(aw8697, true); + + /* f0 trace time */ + t_f0_ms = 1000 * 10 / aw8697->info.f0_pre; + t_f0_trace_ms = + t_f0_ms * (f0_pre_num + f0_wait_num + + (f0_trace_num + f0_wait_num) * (f0_repeat_num - 1)) + + 50; + msleep(t_f0_trace_ms); + +#if 0 + for (i = 0; i < f0_cali_cnt; i++) { + mdelay(200); + ret = aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + /* f0 calibrate done */ + if (reg_val & 0x01) { + aw8697_haptic_read_f0(aw8697); + aw8697_haptic_read_beme(aw8697); + break; + } + msleep(200); + pr_info("%s f0 cali sleep 10ms\n", __func__); + } + + if (i == f0_cali_cnt) { + ret = -1; + } else { + ret = 0; + } +#endif + + aw8697_haptic_read_f0(aw8697); + aw8697_haptic_read_beme(aw8697); + /* restore default config */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_EN_CLOSE_MASK, + AW8697_CONT_PLAYBACK_MODE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_F0_DETECT_MASK, + AW8697_BIT_CONT_CTRL_F0_DETECT_DISABLE); + + return ret; +} +#else +/***************************************************** + * + * haptic cont mode f0 cali + * + *****************************************************/ +static int aw8697_haptic_get_f0(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char i = 0; + unsigned char reg_val = 0; + unsigned int t_f0_trace_ms = 0; + unsigned int f0_cali_cnt = 50; + + pr_info("%s enter\n", __func__); + + aw8697->f0 = aw8697->info.f0_pre; + + /* f0 calibrate work mode */ + aw8697_haptic_stop(aw8697); + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_CONT_MODE); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_MODE_MASK, + AW8697_BIT_CONT_CTRL_BY_DRV_TIME); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_EN_CLOSE_MASK, + AW8697_BIT_CONT_CTRL_OPEN_PLAYBACK); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_EN_CLOSE_MASK, + AW8697_BIT_CONT_CTRL_CLOSE_PLAYBACK); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_F0_DETECT_MASK, + AW8697_BIT_CONT_CTRL_F0_DETECT_DISABLE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_AUTO_BRK_MASK, + AW8697_BIT_CONT_CTRL_AUTO_BRK_DISABLE); + + /* LPF */ + //aw8697_i2c_write_bits(aw8697, AW8697_REG_DATCTRL, + // AW8697_BIT_DATCTRL_FC_MASK, AW8697_BIT_DATCTRL_FC_1000HZ); + //aw8697_i2c_write_bits(aw8697, AW8697_REG_DATCTRL, + // AW8697_BIT_DATCTRL_LPF_ENABLE_MASK, AW8697_BIT_DATCTRL_LPF_ENABLE); + + /* LRA OSC Source */ + if (aw8697->f0_cali_flag == AW8697_HAPTIC_CALI_F0) { + aw8697_i2c_write_bits(aw8697, AW8697_REG_ANACTRL, + AW8697_BIT_ANACTRL_LRA_SRC_MASK, + AW8697_BIT_ANACTRL_LRA_SRC_REG); + } else { + aw8697_i2c_write_bits(aw8697, AW8697_REG_ANACTRL, + AW8697_BIT_ANACTRL_LRA_SRC_MASK, + AW8697_BIT_ANACTRL_LRA_SRC_EFUSE); + } + + /* f0 driver level */ + aw8697_i2c_write(aw8697, AW8697_REG_DRV_LVL, aw8697->info.cont_drv_lvl); + aw8697_i2c_write(aw8697, AW8697_REG_DRV_LVL_OV, + aw8697->info.cont_drv_lvl_ov); + + /* TD time */ + aw8697_i2c_write(aw8697, AW8697_REG_TD_H, aw8697->info.cont_td >> 8); + aw8697_i2c_write(aw8697, AW8697_REG_TD_L, aw8697->info.cont_td); + aw8697_i2c_write(aw8697, AW8697_REG_TSET, aw8697->info.tset); + + /* drive time */ + aw8697_i2c_write(aw8697, AW8697_REG_DRV_TIME, 0x75); + + /* preset f0 */ + aw8697_haptic_set_f0_preset(aw8697); + + /* clear aw8697 interrupt */ + ret = aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + + /* play go and start f0 calibration */ + aw8697_haptic_play_go(aw8697, true); + + /* f0 trace time */ + t_f0_trace_ms = 0xfe * 684 / 1000; + msleep(t_f0_trace_ms); + + for (i = 0; i < f0_cali_cnt; i++) { + ret = aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + /* f0 calibrate done */ + if (reg_val & 0x01) { + aw8697_haptic_read_cont_f0(aw8697); + aw8697_haptic_read_cont_bemf(aw8697); + break; + } + msleep(10); + pr_info("%s f0 cali sleep 10ms\n", __func__); + } + + if (i == f0_cali_cnt) { + ret = -1; + } else { + ret = 0; + } + + /* restore default config */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_EN_CLOSE_MASK, + AW8697_CONT_PLAYBACK_MODE); + aw8697_i2c_write_bits(aw8697, AW8697_REG_CONT_CTRL, + AW8697_BIT_CONT_CTRL_F0_DETECT_MASK, + AW8697_BIT_CONT_CTRL_F0_DETECT_DISABLE); + + return ret; +} +#endif + +static int aw8697_haptic_f0_calibration(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char reg_val = 0; + unsigned int f0_limit = 0; + char f0_cali_lra = 0; + int f0_cali_step = 0; + + pr_info("%s enter\n", __func__); + + aw8697->f0_cali_flag = AW8697_HAPTIC_CALI_F0; + + aw8697_i2c_write(aw8697, AW8697_REG_TRIM_LRA, 0x00); + if (aw8697_haptic_get_f0(aw8697)) { + pr_err("%s get f0 error, user defafult f0\n", __func__); + } else { + /* max and min limit */ + f0_limit = aw8697->f0; + if (aw8697->f0 * 100 < + aw8697->info.f0_pre * (100 - aw8697->info.f0_cali_percen)) { + f0_limit = aw8697->info.f0_pre; + } + if (aw8697->f0 * 100 > + aw8697->info.f0_pre * (100 + aw8697->info.f0_cali_percen)) { + f0_limit = aw8697->info.f0_pre; + } + + /* calculate cali step */ + f0_cali_step = 100000 * + ((int)f0_limit - (int)aw8697->info.f0_pre) / + ((int)f0_limit * 25); + pr_info("%s line=%d f0_cali_step=%d\n", __func__, __LINE__, + f0_cali_step); + pr_info("%s line=%d f0_limit=%d\n", __func__, __LINE__, + (int)f0_limit); + pr_info("%s line=%d aw8697->info.f0_pre=%d\n", __func__, + __LINE__, (int)aw8697->info.f0_pre); + + if (f0_cali_step >= 0) { /*f0_cali_step >= 0 */ + if (f0_cali_step % 10 >= 5) { + f0_cali_step = f0_cali_step / 10 + 1 + 32; + } else { + f0_cali_step = f0_cali_step / 10 + 32; + } + } else { /*f0_cali_step < 0 */ + if (f0_cali_step % 10 <= -5) { + f0_cali_step = 32 + (f0_cali_step / 10 - 1); + } else { + f0_cali_step = 32 + f0_cali_step / 10; + } + } + + if (f0_cali_step > 31) { + f0_cali_lra = (char)f0_cali_step - 32; + } else { + f0_cali_lra = (char)f0_cali_step + 32; + } + aw8697->f0_calib_data = (int)f0_cali_lra; + printk("%s f0_cali_lra=%d\n", __func__, (int)f0_cali_lra); + + /* update cali step */ + aw8697_i2c_write(aw8697, AW8697_REG_TRIM_LRA, + (char)f0_cali_lra); + aw8697_i2c_read(aw8697, AW8697_REG_TRIM_LRA, ®_val); + pr_info("%s final trim_lra=0x%02x\n", __func__, reg_val); + } + + /* restore default work mode */ + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_STANDBY_MODE); + aw8697->play_mode = AW8697_HAPTIC_RAM_MODE; + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_PLAY_MODE_MASK, + AW8697_BIT_SYSCTRL_PLAY_MODE_RAM); + aw8697_haptic_stop(aw8697); + + return ret; +} + +/***************************************************** + * + * haptic fops + * + *****************************************************/ +static int aw8697_file_open(struct inode *inode, struct file *file) +{ + if (!try_module_get(THIS_MODULE)) + return -ENODEV; + pr_info("%s enter\n", __func__); + file->private_data = (void *)g_aw8697; + + return 0; +} + +static int aw8697_file_release(struct inode *inode, struct file *file) +{ + file->private_data = (void *)NULL; + pr_info("%s enter\n", __func__); + module_put(THIS_MODULE); + + return 0; +} + +static long aw8697_file_unlocked_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct aw8697 *aw8697 = (struct aw8697 *)file->private_data; + + int ret = 0; + pr_info("%s enter\n", __func__); + dev_info(aw8697->dev, "%s: cmd=0x%x, arg=0x%lx\n", __func__, cmd, arg); + + mutex_lock(&aw8697->lock); + + if (_IOC_TYPE(cmd) != AW8697_HAPTIC_IOCTL_MAGIC) { + dev_err(aw8697->dev, "%s: cmd magic err\n", __func__); + return -EINVAL; + } + + switch (cmd) { + default: + dev_err(aw8697->dev, "%s, unknown cmd\n", __func__); + break; + } + + mutex_unlock(&aw8697->lock); + + return ret; +} + +static ssize_t aw8697_file_read(struct file *filp, char *buff, size_t len, + loff_t *offset) +{ + struct aw8697 *aw8697 = (struct aw8697 *)filp->private_data; + int ret = 0; + int i = 0; + unsigned char reg_val = 0; + unsigned char *pbuff = NULL; + pr_info("%s enter\n", __func__); + mutex_lock(&aw8697->lock); + + dev_info(aw8697->dev, "%s: len=%zu\n", __func__, len); + + switch (aw8697->fileops.cmd) { + case AW8697_HAPTIC_CMD_READ_REG: + pbuff = (unsigned char *)kzalloc(len, GFP_KERNEL); + if (pbuff != NULL) { + for (i = 0; i < len; i++) { + aw8697_i2c_read(aw8697, aw8697->fileops.reg + i, + ®_val); + pbuff[i] = reg_val; + } + for (i = 0; i < len; i++) { + dev_info(aw8697->dev, "%s: pbuff[%d]=0x%02x\n", + __func__, i, pbuff[i]); + } + ret = copy_to_user(buff, pbuff, len); + if (ret) { + dev_err(aw8697->dev, "%s: copy to user fail\n", + __func__); + } + kfree(pbuff); + } else { + dev_err(aw8697->dev, "%s: alloc memory fail\n", + __func__); + } + break; + default: + dev_err(aw8697->dev, "%s, unknown cmd %d \n", __func__, + aw8697->fileops.cmd); + break; + } + + mutex_unlock(&aw8697->lock); + + return len; +} + +static ssize_t aw8697_file_write(struct file *filp, const char *buff, + size_t len, loff_t *off) +{ + struct aw8697 *aw8697 = (struct aw8697 *)filp->private_data; + int i = 0; + int ret = 0; + unsigned char *pbuff = NULL; + pr_info("%s enter\n", __func__); + pbuff = (unsigned char *)kzalloc(len, GFP_KERNEL); + if (pbuff == NULL) { + dev_err(aw8697->dev, "%s: alloc memory fail\n", __func__); + return len; + } + ret = copy_from_user(pbuff, buff, len); + if (ret) { + dev_err(aw8697->dev, "%s: copy from user fail\n", __func__); + return len; + } + + for (i = 0; i < len; i++) { + dev_info(aw8697->dev, "%s: pbuff[%d]=0x%02x\n", __func__, i, + pbuff[i]); + } + + mutex_lock(&aw8697->lock); + + aw8697->fileops.cmd = pbuff[0]; + + switch (aw8697->fileops.cmd) { + case AW8697_HAPTIC_CMD_READ_REG: + if (len == 2) { + aw8697->fileops.reg = pbuff[1]; + } else { + dev_err(aw8697->dev, "%s: read cmd len %zu err\n", + __func__, len); + } + break; + case AW8697_HAPTIC_CMD_WRITE_REG: + if (len > 2) { + for (i = 0; i < len - 2; i++) { + dev_info(aw8697->dev, + "%s: write reg0x%02x=0x%02x\n", + __func__, pbuff[1] + i, pbuff[i + 2]); + aw8697_i2c_write(aw8697, pbuff[1] + i, + pbuff[2 + i]); + } + } else { + dev_err(aw8697->dev, "%s: write cmd len %zu err\n", + __func__, len); + } + break; + default: + dev_err(aw8697->dev, "%s, unknown cmd %d \n", __func__, + aw8697->fileops.cmd); + break; + } + + mutex_unlock(&aw8697->lock); + + if (pbuff != NULL) { + kfree(pbuff); + } + return len; +} + +static struct file_operations fops = { + .owner = THIS_MODULE, + .read = aw8697_file_read, + .write = aw8697_file_write, + .unlocked_ioctl = aw8697_file_unlocked_ioctl, + .open = aw8697_file_open, + .release = aw8697_file_release, +}; + +static struct miscdevice aw8697_haptic_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = AW8697_HAPTIC_NAME, + .fops = &fops, +}; + +static int aw8697_haptic_init(struct aw8697 *aw8697) +{ + int ret = 0; + unsigned char i = 0; + unsigned char reg_val = 0; + unsigned char bemf_config = 0; + + pr_info("%s enter\n", __func__); + ret = misc_register(&aw8697_haptic_misc); + if (ret) { + dev_err(aw8697->dev, "%s: misc fail: %d\n", __func__, ret); + return ret; + } + + /* haptic audio */ + aw8697->haptic_audio.delay_val = 1; + aw8697->haptic_audio.timer_val = 21318; + + hrtimer_init(&aw8697->haptic_audio.timer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + aw8697->haptic_audio.timer.function = aw8697_haptic_audio_timer_func; + INIT_WORK(&aw8697->haptic_audio.work, aw8697_haptic_audio_work_routine); + + mutex_init(&aw8697->haptic_audio.lock); + + /* haptic init */ + mutex_lock(&aw8697->lock); + + aw8697->activate_mode = aw8697->info.mode; + aw8697->osc_cali_run = 0; + ret = aw8697_i2c_read(aw8697, AW8697_REG_WAVSEQ1, ®_val); + aw8697->index = reg_val & 0x7F; + ret = aw8697_i2c_read(aw8697, AW8697_REG_DATDBG, ®_val); + aw8697->gain = reg_val & 0xFF; + ret = aw8697_i2c_read(aw8697, AW8697_REG_BSTDBG4, ®_val); + aw8697->vmax = (reg_val >> 1) & 0x1F; + for (i = 0; i < AW8697_SEQUENCER_SIZE; i++) { + ret = aw8697_i2c_read(aw8697, AW8697_REG_WAVSEQ1 + i, ®_val); + aw8697->seq[i] = reg_val; + } + + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_STANDBY_MODE); + + aw8697_haptic_set_pwm(aw8697, AW8697_PWM_24K); + + aw8697_i2c_write(aw8697, AW8697_REG_BSTDBG1, aw8697->info.bstdbg[0]); + aw8697_i2c_write(aw8697, AW8697_REG_BSTDBG2, aw8697->info.bstdbg[1]); + aw8697_i2c_write(aw8697, AW8697_REG_BSTDBG3, aw8697->info.bstdbg[2]); + aw8697_i2c_write(aw8697, AW8697_REG_TSET, aw8697->info.tset); + aw8697_i2c_write(aw8697, AW8697_REG_R_SPARE, aw8697->info.r_spare); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_ANADBG, + AW8697_BIT_ANADBG_IOC_MASK, + AW8697_BIT_ANADBG_IOC_4P65A); + + aw8697_haptic_set_bst_peak_cur(aw8697, AW8697_DEFAULT_PEAKCUR); + + aw8697_haptic_swicth_motorprotect_config(aw8697, 0x00, 0x00); + + aw8697_haptic_auto_boost_config(aw8697, false); + + if ((aw8697->info.trig_config[0][0] == 1) || + (aw8697->info.trig_config[1][0] == 1) || + (aw8697->info.trig_config[2][0] == 1)) { + aw8697_haptic_trig_param_init(aw8697); + aw8697_haptic_trig_param_config(aw8697); + } + + aw8697_haptic_offset_calibration(aw8697); + + /* vbat compensation */ + aw8697_haptic_cont_vbat_mode(aw8697, + AW8697_HAPTIC_CONT_VBAT_HW_COMP_MODE); + aw8697->ram_vbat_comp = AW8697_HAPTIC_RAM_VBAT_COMP_ENABLE; + + mutex_unlock(&aw8697->lock); + + /* f0 calibration */ + mutex_lock(&aw8697->lock); +#ifndef USE_CONT_F0_CALI + aw8697_haptic_f0_calibration(aw8697); +#endif + mutex_unlock(&aw8697->lock); + /* beme config */ + bemf_config = aw8697->info.bemf_config[0]; + aw8697_i2c_write(aw8697, AW8697_REG_BEMF_VTHH_H, bemf_config); + bemf_config = aw8697->info.bemf_config[1]; + aw8697_i2c_write(aw8697, AW8697_REG_BEMF_VTHH_L, bemf_config); + bemf_config = aw8697->info.bemf_config[2]; + aw8697_i2c_write(aw8697, AW8697_REG_BEMF_VTHL_H, bemf_config); + bemf_config = aw8697->info.bemf_config[3]; + aw8697_i2c_write(aw8697, AW8697_REG_BEMF_VTHL_L, bemf_config); + return ret; +} + +/***************************************************** + * + * vibrator + * + *****************************************************/ +static enum hrtimer_restart qti_hap_stop_timer(struct hrtimer *timer) +{ + struct aw8697 *aw8697 = container_of(timer, struct aw8697, stop_timer); + int rc; + + pr_info("%s enter\n", __func__); + aw8697->play.length_us = 0; + rc = aw8697_haptic_play_go(aw8697, + false); // qti_haptics_play(aw8697, false); + if (rc < 0) + dev_err(aw8697->dev, "Stop playing failed, rc=%d\n", rc); + + return HRTIMER_NORESTART; +} + +static enum hrtimer_restart qti_hap_disable_timer(struct hrtimer *timer) +{ + struct aw8697 *aw8697 = + container_of(timer, struct aw8697, hap_disable_timer); + int rc; + + pr_info("%s enter\n", __func__); + rc = aw8697_haptic_play_go( + aw8697, false); //qti_haptics_module_en(aw8697, false); + if (rc < 0) + dev_err(aw8697->dev, "Disable haptics module failed, rc=%d\n", + rc); + + return HRTIMER_NORESTART; +} + +static enum hrtimer_restart aw8697_vibrator_timer_func(struct hrtimer *timer) +{ + struct aw8697 *aw8697 = container_of(timer, struct aw8697, timer); + + pr_info("%s enter\n", __func__); + + aw8697->state = 0; + //schedule_work(&aw8697->vibrator_work); + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + + return HRTIMER_NORESTART; +} + +static void aw8697_vibrator_work_routine(struct work_struct *work) +{ + struct aw8697 *aw8697 = + container_of(work, struct aw8697, vibrator_work); + + pr_debug("%s enter\n", __func__); + pr_info("%s: effect_id = %d state=%d activate_mode = %d duration = %d\n", + __func__, aw8697->effect_id, aw8697->state, + aw8697->activate_mode, aw8697->duration); + mutex_lock(&aw8697->lock); + aw8697_haptic_upload_lra(aw8697, true); + aw8697_haptic_stop(aw8697); + if (aw8697->state) { + if (aw8697->activate_mode == AW8697_HAPTIC_ACTIVATE_RAM_MODE) { + aw8697_haptic_ram_vbat_comp(aw8697, false); + aw8697_haptic_play_effect_seq(aw8697, true); + } else if (aw8697->activate_mode == + AW8697_HAPTIC_ACTIVATE_RAM_LOOP_MODE) { + aw8697_haptic_ram_vbat_comp(aw8697, true); + aw8697_haptic_play_effect_seq(aw8697, true); + hrtimer_start( + &aw8697->timer, + ktime_set(aw8697->duration / 1000, + (aw8697->duration % 1000) * 1000000), + HRTIMER_MODE_REL); + } else if (aw8697->activate_mode == + AW8697_HAPTIC_ACTIVATE_CONT_MODE) { + aw8697_haptic_cont(aw8697); + hrtimer_start( + &aw8697->timer, + ktime_set(aw8697->duration / 1000, + (aw8697->duration % 1000) * 1000000), + HRTIMER_MODE_REL); + } else { + /*other mode */ + } + } + mutex_unlock(&aw8697->lock); +} + +static int aw8697_vibrator_init(struct aw8697 *aw8697) +{ + pr_info("%s enter\n", __func__); + + hrtimer_init(&aw8697->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + aw8697->timer.function = aw8697_vibrator_timer_func; + INIT_WORK(&aw8697->vibrator_work, aw8697_vibrator_work_routine); + INIT_WORK(&aw8697->rtp_work, aw8697_rtp_work_routine); + + mutex_init(&aw8697->lock); + atomic_set(&aw8697->is_in_rtp_loop, 0); + atomic_set(&aw8697->exit_in_rtp_loop, 0); + atomic_set(&aw8697->is_in_write_loop, 0); + init_waitqueue_head(&aw8697->wait_q); + init_waitqueue_head(&aw8697->stop_wait_q); + + return 0; +} + +/****************************************************** + * + * irq + * + ******************************************************/ +static void aw8697_interrupt_clear(struct aw8697 *aw8697) +{ + unsigned char reg_val = 0; + aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); +} + +static void aw8697_interrupt_setup(struct aw8697 *aw8697) +{ + unsigned char reg_val = 0; + + aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + + /* edge int mode */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_DBGCTRL, + AW8697_BIT_DBGCTRL_INT_MODE_MASK, + AW8697_BIT_DBGCTRL_INT_MODE_EDGE); + + /* int enable */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_BSTERR_MASK, + AW8697_BIT_SYSINTM_BSTERR_OFF); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_OV_MASK, + AW8697_BIT_SYSINTM_OV_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_UVLO_MASK, + AW8697_BIT_SYSINTM_UVLO_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_OCD_MASK, + AW8697_BIT_SYSINTM_OCD_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSINTM, + AW8697_BIT_SYSINTM_OT_MASK, + AW8697_BIT_SYSINTM_OT_EN); +} + +static irqreturn_t aw8697_irq(int irq, void *data) +{ + struct aw8697 *aw8697 = data; + unsigned char reg_val = 0; + unsigned char dbg_val = 0; + unsigned int buf_len = 0; + unsigned period_size = aw8697->ram.base_addr >> 2; + + atomic_set(&aw8697->is_in_rtp_loop, 1); + aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + //pr_info("%s: reg SYSINT=0x%x\n", __func__, reg_val); + aw8697_i2c_read(aw8697, AW8697_REG_DBGSTAT, &dbg_val); + //pr_info("%s: reg DBGSTAT=0x%x\n", __func__, dbg_val); + + if (reg_val & AW8697_BIT_SYSINT_OVI) { + pr_err("%s chip ov int error\n", __func__); + } + if (reg_val & AW8697_BIT_SYSINT_UVLI) { + pr_err("%s chip uvlo int error\n", __func__); + } + if (reg_val & AW8697_BIT_SYSINT_OCDI) { + pr_err("%s chip over current int error\n", __func__); + } + if (reg_val & AW8697_BIT_SYSINT_OTI) { + pr_err("%s chip over temperature int error\n", __func__); + } + if (reg_val & AW8697_BIT_SYSINT_DONEI) { + pr_info("%s chip playback done\n", __func__); + } + + if (reg_val & AW8697_BIT_SYSINT_FF_AEI) { + pr_debug("%s: aw8697 rtp fifo almost empty int\n", __func__); + if (aw8697->rtp_init) { + while ((!aw8697_haptic_rtp_get_fifo_afi(aw8697)) && + (aw8697->play_mode == AW8697_HAPTIC_RTP_MODE) && + !atomic_read(&aw8697->exit_in_rtp_loop)) { + mutex_lock(&aw8697->rtp_lock); + if (!aw8697_rtp) { + pr_info("%s:aw8697_rtp is null break\n", + __func__); + mutex_unlock(&aw8697->rtp_lock); + break; + } + if (aw8697->is_custom_wave == 1) { + buf_len = read_rb(aw8697_rtp->data, + period_size); + aw8697_i2c_writes(aw8697, + AW8697_REG_RTP_DATA, + aw8697_rtp->data, + buf_len); + if (buf_len < period_size) { + pr_info("%s: rtp update complete\n", + __func__); + aw8697_haptic_set_rtp_aei( + aw8697, false); + aw8697->rtp_cnt = 0; + aw8697->rtp_init = 0; + mutex_unlock(&aw8697->rtp_lock); + break; + } + } else { + if ((aw8697_rtp->len - + aw8697->rtp_cnt) < + (aw8697->ram.base_addr >> 2)) { + buf_len = aw8697_rtp->len - + aw8697->rtp_cnt; + } else { + buf_len = + (aw8697->ram.base_addr >> + 2); + } + aw8697_i2c_writes( + aw8697, AW8697_REG_RTP_DATA, + &aw8697_rtp + ->data[aw8697->rtp_cnt], + buf_len); + aw8697->rtp_cnt += buf_len; + pr_debug("%s: rtp_cnt = %d \n", + __func__, aw8697->rtp_cnt); + if (aw8697->rtp_cnt == + aw8697_rtp->len) { + pr_info("%s: rtp update complete\n", + __func__); + aw8697_haptic_set_rtp_aei( + aw8697, false); + aw8697->rtp_cnt = 0; + aw8697->rtp_init = 0; + mutex_unlock(&aw8697->rtp_lock); + break; + } + } + mutex_unlock(&aw8697->rtp_lock); + } + } else { + pr_err("%s: aw8697 rtp init = %d, init error\n", + __func__, aw8697->rtp_init); + } + } + + if (reg_val & AW8697_BIT_SYSINT_FF_AFI) { + pr_debug("%s: aw8697 rtp mode fifo full empty\n", __func__); + } + + if (aw8697->play_mode != AW8697_HAPTIC_RTP_MODE || + atomic_read(&aw8697->exit_in_rtp_loop)) { + aw8697_haptic_set_rtp_aei(aw8697, false); + } + + aw8697_i2c_read(aw8697, AW8697_REG_SYSINT, ®_val); + pr_debug("%s: reg SYSINT=0x%x\n", __func__, reg_val); + aw8697_i2c_read(aw8697, AW8697_REG_SYSST, ®_val); + pr_debug("%s: reg SYSST=0x%x\n", __func__, reg_val); + atomic_set(&aw8697->is_in_rtp_loop, 0); + wake_up_interruptible(&aw8697->wait_q); + pr_debug("%s exit\n", __func__); + return IRQ_HANDLED; +} + +/***************************************************** + * + * device tree + * + *****************************************************/ +static int aw8697_parse_dt(struct device *dev, struct aw8697 *aw8697, + struct device_node *np) +{ + unsigned int val = 0; + unsigned int bstdbg[6]; + unsigned int f0_trace_parameter[4]; + unsigned int bemf_config[4]; + unsigned int rtp_time[175]; + unsigned int trig_config[15]; + struct qti_hap_config *config = &aw8697->config; + struct device_node *child_node; + struct qti_hap_effect *effect; + int rc = 0, tmp, i = 0, j, m; + + printk("%s %d enter\n", __func__, __LINE__); + aw8697->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); + if (aw8697->reset_gpio < 0) { + dev_err(dev, + "%s: no reset gpio provided, will not HW reset device\n", + __func__); + return -EINVAL; + } else { + dev_info(dev, "%s: reset gpio provided ok\n", __func__); + } + aw8697->irq_gpio = of_get_named_gpio(np, "irq-gpio", 0); + if (aw8697->irq_gpio < 0) { + dev_err(dev, "%s: no irq gpio provided.\n", __func__); + } else { + dev_info(dev, "%s: irq gpio provided ok.\n", __func__); + } + + val = of_property_read_u32(np, "vib_mode", &aw8697->info.mode); + if (val != 0) + printk("vib_mode not found\n"); + val = of_property_read_u32(np, "vib_f0_pre", &aw8697->info.f0_pre); + if (val != 0) + printk("vib_f0_pre not found\n"); + val = of_property_read_u32(np, "vib_f0_cali_percen", + &aw8697->info.f0_cali_percen); + if (val != 0) + printk("vib_f0_cali_percen not found\n"); + val = of_property_read_u32(np, "vib_cont_drv_lev", + &aw8697->info.cont_drv_lvl); + if (val != 0) + printk("vib_cont_drv_lev not found\n"); + val = of_property_read_u32(np, "vib_cont_drv_lvl_ov", + &aw8697->info.cont_drv_lvl_ov); + if (val != 0) + printk("vib_cont_drv_lvl_ov not found\n"); + val = of_property_read_u32(np, "vib_cont_td", &aw8697->info.cont_td); + if (val != 0) + printk("vib_cont_td not found\n"); + val = of_property_read_u32(np, "vib_cont_zc_thr", + &aw8697->info.cont_zc_thr); + if (val != 0) + printk("vib_cont_zc_thr not found\n"); + val = of_property_read_u32(np, "vib_cont_num_brk", + &aw8697->info.cont_num_brk); + if (val != 0) + printk("vib_cont_num_brk not found\n"); + val = of_property_read_u32(np, "vib_f0_coeff", &aw8697->info.f0_coeff); + if (val != 0) + printk("vib_f0_coeff not found\n"); + + val = of_property_read_u32(np, "vib_tset", &aw8697->info.tset); + if (val != 0) + printk("%s vib_tset not found\n", __func__); + val = of_property_read_u32(np, "vib_r_spare", &aw8697->info.r_spare); + if (val != 0) + printk("%s vib_r_spare not found\n", __func__); + val = of_property_read_u32_array(np, "vib_bstdbg", bstdbg, + ARRAY_SIZE(bstdbg)); + if (val != 0) + printk("%s vib_bstdbg not found\n", __func__); + memcpy(aw8697->info.bstdbg, bstdbg, sizeof(bstdbg)); + + val = of_property_read_u32_array(np, "vib_f0_trace_parameter", + f0_trace_parameter, + ARRAY_SIZE(f0_trace_parameter)); + if (val != 0) + printk("%s vib_f0_trace_parameter not found\n", __func__); + memcpy(aw8697->info.f0_trace_parameter, f0_trace_parameter, + sizeof(f0_trace_parameter)); + val = of_property_read_u32_array(np, "vib_bemf_config", bemf_config, + ARRAY_SIZE(bemf_config)); + if (val != 0) + printk("%s vib_bemf_config not found\n", __func__); + memcpy(aw8697->info.bemf_config, bemf_config, sizeof(bemf_config)); + + val = of_property_read_u32_array(np, "vib_trig_config", trig_config, + ARRAY_SIZE(trig_config)); + if (val != 0) + printk("%s vib_trig_config not found\n", __func__); + memcpy(aw8697->info.trig_config, trig_config, sizeof(trig_config)); + + val = of_property_read_u32_array(np, "vib_rtp_time", rtp_time, + ARRAY_SIZE(rtp_time)); + if (val != 0) + printk("%s vib_rtp_time not found\n", __func__); + memcpy(aw8697->info.rtp_time, rtp_time, sizeof(rtp_time)); + + val = of_property_read_u32(np, "vib_effect_id_boundary", + &aw8697->info.effect_id_boundary); + if (val != 0) + printk("%s vib_effect_id_boundary not found\n", __func__); + val = of_property_read_u32(np, "vib_effect_max", + &aw8697->info.effect_max); + if (val != 0) + printk("%s vib_effect_max not found\n", __func__); + val = of_property_read_u32(np, "vib_bst_vol_default", + &aw8697->info.bst_vol_default); + if (val != 0) + printk("%s vib_bst_vol_default not found\n", __func__); + val = of_property_read_u32(np, "vib_bst_vol_ram", + &aw8697->info.bst_vol_ram); + if (val != 0) + printk("%s vib_bst_vol_ram not found\n", __func__); + val = of_property_read_u32(np, "vib_bst_vol_rtp", + &aw8697->info.bst_vol_rtp); + if (val != 0) + printk("%s vib_bst_vol_rtp not found\n", __func__); + + config->play_rate_us = HAP_PLAY_RATE_US_DEFAULT; + rc = of_property_read_u32(np, "qcom,play-rate-us", &tmp); + if (!rc) + config->play_rate_us = (tmp >= HAP_PLAY_RATE_US_MAX) ? + HAP_PLAY_RATE_US_MAX : + tmp; + + aw8697->constant.pattern = devm_kcalloc( + aw8697->dev, HAP_WAVEFORM_BUFFER_MAX, sizeof(u8), GFP_KERNEL); + if (!aw8697->constant.pattern) + return -ENOMEM; + + tmp = of_get_available_child_count(np); + aw8697->predefined = devm_kcalloc( + aw8697->dev, tmp, sizeof(*aw8697->predefined), GFP_KERNEL); + if (!aw8697->predefined) + return -ENOMEM; + + aw8697->effects_count = tmp; + printk("%s ---%d aw8697->effects_count=%d\n", __func__, __LINE__, + aw8697->effects_count); + for_each_available_child_of_node(np, child_node) { + printk("%s %d i=%d\n", __func__, __LINE__, i); + effect = &aw8697->predefined[i++]; + printk("%s %d i=%d\n", __func__, __LINE__, i); + rc = of_property_read_u32(child_node, "qcom,effect-id", + &effect->id); + if (rc != 0) { + printk("%s Read qcom,effect-id failed\n", __func__); + } + printk(" 20190420_dt effect_id: %d\n", effect->id); + + printk("%s ---%d \n", __func__, __LINE__); + effect->vmax_mv = config->vmax_mv; + rc = of_property_read_u32(child_node, "qcom,wf-vmax-mv", &tmp); + if (rc != 0) + printk("%s Read qcom,wf-vmax-mv failed !\n", __func__); + else + effect->vmax_mv = tmp; + + printk("%s ---%d effect->vmax_mv =%d \n", __func__, __LINE__, + effect->vmax_mv); + rc = of_property_count_elems_of_size( + child_node, "qcom,wf-pattern", sizeof(u8)); + if (rc < 0) { + printk("%s Count qcom,wf-pattern property failed !\n", + __func__); + } else if (rc == 0) { + printk("%s qcom,wf-pattern has no data\n", __func__); + } + printk("%s ---%d \n", __func__, __LINE__); + + effect->pattern_length = rc; + effect->pattern = devm_kcalloc(aw8697->dev, + effect->pattern_length, + sizeof(u8), GFP_KERNEL); + + rc = of_property_read_u8_array(child_node, "qcom,wf-pattern", + effect->pattern, + effect->pattern_length); + if (rc < 0) { + printk("%s Read qcom,wf-pattern property failed !\n", + __func__); + } + printk("%s %d effect->pattern_length=%d effect->pattern=%d \n", + __func__, __LINE__, effect->pattern_length, + (int)effect->pattern); + + effect->play_rate_us = config->play_rate_us; + rc = of_property_read_u32(child_node, "qcom,wf-play-rate-us", + &tmp); + if (rc < 0) + printk("%s Read qcom,wf-play-rate-us failed !\n", + __func__); + else + effect->play_rate_us = tmp; + printk("%s ---%d effect->play_rate_us=%d \n", __func__, + __LINE__, effect->play_rate_us); + + rc = of_property_read_u32(child_node, "qcom,wf-repeat-count", + &tmp); + if (rc < 0) { + printk("%s Read qcom,wf-repeat-count failed !\n", + __func__); + } else { + for (j = 0; j < ARRAY_SIZE(wf_repeat); j++) + if (tmp <= wf_repeat[j]) + break; + + effect->wf_repeat_n = j; + } + + printk("%s ---%d \n", __func__, __LINE__); + + rc = of_property_read_u32(child_node, "qcom,wf-s-repeat-count", + &tmp); + if (rc < 0) { + printk("%s Read qcom,wf-s-repeat-count failed !\n", + __func__); + } else { + for (j = 0; j < ARRAY_SIZE(wf_s_repeat); j++) + if (tmp <= wf_s_repeat[j]) + break; + + effect->wf_s_repeat_n = j; + } + + printk("%s ---%d \n", __func__, __LINE__); + + effect->lra_auto_res_disable = of_property_read_bool( + child_node, "qcom,lra-auto-resonance-disable"); + + tmp = of_property_count_elems_of_size( + child_node, "qcom,wf-brake-pattern", sizeof(u8)); + if (tmp <= 0) + continue; + + if (tmp > HAP_BRAKE_PATTERN_MAX) { + printk("%s wf-brake-pattern shouldn't be more than %d bytes\n", + __func__, HAP_BRAKE_PATTERN_MAX); + } + + rc = of_property_read_u8_array(child_node, + "qcom,wf-brake-pattern", + effect->brake, tmp); + if (rc < 0) { + printk("%s Failed to get wf-brake-pattern !\n", + __func__); + } + + effect->brake_pattern_length = tmp; + } + + for (j = 0; j < i; j++) { + printk(" 20190420_dt effect_id: %d\n", + aw8697->predefined[j].id); + printk(" 20190420_dt vmax: %d mv\n", + aw8697->predefined[j].vmax_mv); + printk("20190420_dt play_rate: %d us\n", + aw8697->predefined[j].play_rate_us); + for (m = 0; m < aw8697->predefined[j].pattern_length; m++) + printk("20190420_dt pattern[%d]: 0x%x\n", m, + aw8697->predefined[j].pattern[m]); + for (m = 0; m < aw8697->predefined[j].brake_pattern_length; m++) + printk("20190420_dt brake_pattern[%d]: 0x%x\n", m, + aw8697->predefined[j].brake[m]); + printk("20190420_dt brake_en: %d\n", + aw8697->predefined[j].brake_en); + printk("20190420_dt wf_repeat_n: %d\n", + aw8697->predefined[j].wf_repeat_n); + printk("20190420_dt wf_s_repeat_n: %d\n", + aw8697->predefined[j].wf_s_repeat_n); + printk("20190420_dt lra_auto_res_disable: %d\n", + aw8697->predefined[j].lra_auto_res_disable); + } + printk(" 20190420_dt aw8697->effects_count: %d\n", + aw8697->effects_count); + printk(" 20190420_dt aw8697->effect_id_boundary: %d\n", + aw8697->info.effect_id_boundary); + printk(" 20190420_dt aw8697->effect_max: %d\n", + aw8697->info.effect_max); + printk(" 20190420_dt aw8697->info.cont_drv_lvl: %d\n", + aw8697->info.cont_drv_lvl); + printk(" 20190420_dt aw8697->info.cont_drv_lvl_ov: %d\n", + aw8697->info.cont_drv_lvl_ov); + for (i = 0; i < 3; i++) + for (j = 0; j < 5; j++) + printk(" 20190420_dt aw8697->info.trig_config[%d][%d]: %d\n", + i, j, aw8697->info.trig_config[i][j]); + for (i = 0; i < 175; i++) + printk(" 20190420_dt aw8697->info.rtp_time[%d]: %d\n", i, + aw8697->info.rtp_time[i]); + + printk(" 20190420_dt aw8697->info.bst_vol_default: 0x%x\n", + aw8697->info.bst_vol_default); + printk(" 20190420_dt aw8697->info.bst_vol_ram: 0x%x\n", + aw8697->info.bst_vol_ram); + printk(" 20190420_dt aw8697->info.bst_vol_rtp: 0x%x\n", + aw8697->info.bst_vol_rtp); + return 0; +} + +static inline void get_play_length(struct qti_hap_play_info *play, + int *length_us) +{ + struct qti_hap_effect *effect = play->effect; + int tmp; + //printk("%s %d enter\n", __func__, __LINE__); + + tmp = effect->pattern_length * effect->play_rate_us; + tmp *= wf_s_repeat[effect->wf_s_repeat_n]; + tmp *= wf_repeat[effect->wf_repeat_n]; + if (effect->brake_en) + tmp += effect->play_rate_us * effect->brake_pattern_length; + + *length_us = tmp; +} + +static int aw8697_haptics_upload_effect(struct input_dev *dev, + struct ff_effect *effect, + struct ff_effect *old) +{ + struct aw8697 *aw8697 = input_get_drvdata(dev); + struct qti_hap_play_info *play = &aw8697->play; + s16 data[CUSTOM_DATA_LEN]; + ktime_t rem; + s64 time_us; + int ret; + + /*for osc calibration*/ + if (aw8697->osc_cali_run != 0) + return 0; + + if (hrtimer_active(&aw8697->timer)) { + rem = hrtimer_get_remaining(&aw8697->timer); + time_us = ktime_to_us(rem); + printk("waiting for playing clear sequence: %lld us\n", + time_us); + usleep_range(time_us, time_us + 100); + } + pr_debug("%s: effect->type=0x%x,FF_CONSTANT=0x%x,FF_PERIODIC=0x%x\n", + __func__, effect->type, FF_CONSTANT, FF_PERIODIC); + aw8697->effect_type = effect->type; + mutex_lock(&aw8697->lock); + while (atomic_read(&aw8697->exit_in_rtp_loop)) { + pr_info("%s goint to waiting rtp exit\n", __func__); + mutex_unlock(&aw8697->lock); + ret = wait_event_interruptible( + aw8697->stop_wait_q, + atomic_read(&aw8697->exit_in_rtp_loop) == 0); + pr_info("%s wakeup \n", __func__); + if (ret == -ERESTARTSYS) { + mutex_unlock(&aw8697->lock); + pr_err("%s wake up by signal return erro\n", __func__); + return ret; + } + mutex_lock(&aw8697->lock); + } + if (aw8697->effect_type == FF_CONSTANT) { + pr_debug("%s: effect_type is FF_CONSTANT! \n", __func__); + /*cont mode set duration */ + aw8697->duration = effect->replay.length; + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_RAM_LOOP_MODE; + aw8697->effect_id = aw8697->info.effect_id_boundary; + + } else if (aw8697->effect_type == FF_PERIODIC) { + if (aw8697->effects_count == 0) { + mutex_unlock(&aw8697->lock); + return -EINVAL; + } + + pr_debug("%s: effect_type is FF_PERIODIC! \n", __func__); + if (copy_from_user(data, effect->u.periodic.custom_data, + sizeof(s16) * CUSTOM_DATA_LEN)) { + mutex_unlock(&aw8697->lock); + return -EFAULT; + } + + aw8697->effect_id = data[0]; + pr_debug("%s: aw8697->effect_id =%d \n", __func__, + aw8697->effect_id); + play->vmax_mv = effect->u.periodic.magnitude; /*vmax level*/ + + if (aw8697->effect_id < 0 || + aw8697->effect_id > aw8697->info.effect_max) { + mutex_unlock(&aw8697->lock); + return 0; + } + aw8697->is_custom_wave = 0; + if (aw8697->effect_id < aw8697->info.effect_id_boundary) { + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_RAM_MODE; + pr_debug( + "%s: aw8697->effect_id=%d , aw8697->activate_mode = %d\n", + __func__, aw8697->effect_id, + aw8697->activate_mode); + data[1] = aw8697->predefined[aw8697->effect_id] + .play_rate_us / + 1000000; /*second data*/ + data[2] = aw8697->predefined[aw8697->effect_id] + .play_rate_us / + 1000; /*millisecond data*/ + } + if (aw8697->effect_id >= aw8697->info.effect_id_boundary) { + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_RTP_MODE; + pr_debug( + "%s: aw8697->effect_id=%d , aw8697->activate_mode = %d\n", + __func__, aw8697->effect_id, + aw8697->activate_mode); + data[1] = aw8697->info.rtp_time[aw8697->effect_id] / + 1000; /*second data*/ + data[2] = + aw8697->info.rtp_time + [aw8697->effect_id]; /*millisecond data*/ + } + if (aw8697->effect_id == CUSTOME_WAVE_ID) { + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_RTP_MODE; + pr_debug( + "%s: aw8697->effect_id=%d , aw8697->activate_mode = %d\n", + __func__, aw8697->effect_id, + aw8697->activate_mode); + data[1] = aw8697->info.rtp_time[aw8697->effect_id] / + 1000; /*second data*/ + data[2] = + aw8697->info.rtp_time + [aw8697->effect_id]; /*millisecond data*/ + aw8697->is_custom_wave = 1; + rb_init(); + } + if (copy_to_user(effect->u.periodic.custom_data, data, + sizeof(s16) * CUSTOM_DATA_LEN)) { + mutex_unlock(&aw8697->lock); + return -EFAULT; + } + + } else { + pr_err("%s Unsupported effect type: %d\n", __func__, + effect->type); + } + mutex_unlock(&aw8697->lock); + return 0; +} + +static int aw8697_haptics_playback(struct input_dev *dev, int effect_id, + int val) +{ + struct aw8697 *aw8697 = input_get_drvdata(dev); + int rc = 0; + + //printk("%s effect_id=%d , val = %d\n", __func__, effect_id, val); + //printk("%s aw8697->effect_id=%d , aw8697->activate_mode = %d\n", + // __func__, aw8697->effect_id, aw8697->activate_mode); + + pr_debug("%s: effect_id=%d , activate_mode = %d val = %d\n", __func__, + aw8697->effect_id, aw8697->activate_mode, val); + /*for osc calibration*/ + if (aw8697->osc_cali_run != 0) + return 0; + + if (val > 0) + aw8697->state = 1; + if (val <= 0) + aw8697->state = 0; + hrtimer_cancel(&aw8697->timer); + + if (aw8697->effect_type == FF_CONSTANT && + aw8697->activate_mode == AW8697_HAPTIC_ACTIVATE_RAM_LOOP_MODE) { + pr_debug("%s: enter cont_mode \n", __func__); + //schedule_work(&aw8697->vibrator_work); + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + } else if (aw8697->effect_type == FF_PERIODIC && + aw8697->activate_mode == AW8697_HAPTIC_ACTIVATE_RAM_MODE) { + pr_debug("%s: enter ram_mode\n", __func__); + //schedule_work(&aw8697->vibrator_work) + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + ; + } else if ((aw8697->effect_type == FF_PERIODIC) && + aw8697->activate_mode == AW8697_HAPTIC_ACTIVATE_RTP_MODE) { + pr_debug("%s: enter rtp_mode\n", __func__); + //schedule_work(&aw8697->rtp_work); + queue_work(aw8697->work_queue, &aw8697->rtp_work); + //if we are in the play mode, force to exit + if (val == 0) { + atomic_set(&aw8697->exit_in_rtp_loop, 1); + rb_force_exit(); + wake_up_interruptible(&aw8697->stop_wait_q); + } + } else { + /*other mode */ + } + + return rc; +} + +static int aw8697_haptics_erase(struct input_dev *dev, int effect_id) +{ + struct aw8697 *aw8697 = input_get_drvdata(dev); + int rc = 0; + + /*for osc calibration*/ + if (aw8697->osc_cali_run != 0) + return 0; + + pr_debug("%s: enter\n", __func__); + aw8697->effect_type = 0; + aw8697->is_custom_wave = 0; + aw8697->duration = 0; + return rc; +} + +static void set_gain(struct work_struct *work) +{ + struct aw8697 *aw8697 = + container_of(work, struct aw8697, set_gain_work); + pr_debug("%s enter set_gain queue work\n", __func__); + + if (aw8697->new_gain >= 0x7FFF) + aw8697->level = 0x80; /*128*/ + else if (aw8697->new_gain <= 0x3FFF) + aw8697->level = 0x1E; /*30*/ + else + aw8697->level = (aw8697->new_gain - 16383) / 128; + + if (aw8697->level < 0x1E) + aw8697->level = 0x1E; /*30*/ + + aw8697_haptic_set_gain(aw8697, aw8697->level); +} + +static void aw8697_haptics_set_gain(struct input_dev *dev, u16 gain) +{ + struct aw8697 *aw8697 = input_get_drvdata(dev); + pr_debug("%s enter\n", __func__); + aw8697->new_gain = gain; + queue_work(aw8697->work_queue, &aw8697->set_gain_work); +} + +static ssize_t aw8697_activate_test_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + + /* For now nothing to show */ + return snprintf(buf, PAGE_SIZE, "%d\n", aw8697->test_val); +} + +static ssize_t aw8697_activate_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + ; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + aw8697->test_val = val; + pr_debug("%s: aw8697->test_val=%d\n", __FUNCTION__, aw8697->test_val); + + if (aw8697->test_val == 1) { + printk("%s %d \n", __func__, __LINE__); + aw8697->duration = 3000; + + aw8697->state = 1; + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_CONT_MODE; + hrtimer_cancel(&aw8697->timer); + //schedule_work(&aw8697->vibrator_work); + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + } + if (aw8697->test_val == 2) { + printk("%s %d \n", __func__, __LINE__); + mutex_lock(&aw8697->lock); + aw8697_haptic_set_wav_seq(aw8697, 0x00, 0x01); + aw8697_haptic_set_wav_seq(aw8697, 0x01, 0x01); + + /*step 1: choose loop */ + aw8697_haptic_set_wav_loop(aw8697, 0x01, 0x01); + mutex_unlock(&aw8697->lock); + + aw8697->state = 1; + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_RAM_MODE; + hrtimer_cancel(&aw8697->timer); + //schedule_work(&aw8697->vibrator_work); + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + } + + if (aw8697->test_val == 3) { /*Ram instead of Cont */ + aw8697->duration = 10000; + + aw8697->state = 1; + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_CONT_MODE; + hrtimer_cancel(&aw8697->timer); + //schedule_work(&aw8697->vibrator_work); + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + } + + if (aw8697->test_val == 4) { + mutex_lock(&aw8697->lock); + aw8697_haptic_stop(aw8697); + aw8697_haptic_play_mode(aw8697, AW8697_HAPTIC_RAM_MODE); + + aw8697_haptic_set_wav_seq(aw8697, 0x00, 0x01); + aw8697_haptic_set_wav_seq(aw8697, 0x01, 0x00); + + aw8697_haptic_set_wav_loop(aw8697, 0x01, 0x01); + + if (aw8697->info.bst_vol_ram <= AW8697_MAX_BST_VO) + aw8697_haptic_set_bst_vol(aw8697, + aw8697->info.bst_vol_ram); + else + aw8697_haptic_set_bst_vol(aw8697, aw8697->vmax); + + aw8697->activate_mode = AW8697_HAPTIC_ACTIVATE_RAM_MODE; + aw8697->state = 1; + mutex_unlock(&aw8697->lock); + hrtimer_cancel(&aw8697->timer); + //schedule_work(&aw8697->vibrator_work); + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + } + + return count; +} +#ifdef ENABLE_PIN_CONTROL +static int select_pin_ctl(struct aw8697 *aw8697, const char *name) +{ + size_t i; + int rc; + + for (i = 0; i < ARRAY_SIZE(aw8697->pinctrl_state); i++) { + const char *n = pctl_names[i]; + + if (!strncmp(n, name, strlen(n))) { + rc = pinctrl_select_state(aw8697->aw8697_pinctrl, + aw8697->pinctrl_state[i]); + if (rc) + printk("cannot select '%s'\n", name); + else + printk("Selected '%s'\n", name); + goto exit; + } + } + + rc = -EINVAL; + printk("%s:'%s' not found\n", __func__, name); + +exit: + return rc; +} +static int aw8697_set_interrupt(struct aw8697 *aw8697) +{ + int rc = select_pin_ctl(aw8697, "aw8697_interrupt_active"); + return rc; +} +#endif + +static int aw8697_hw_reset(struct aw8697 *aw8697) +{ +#ifdef ENABLE_PIN_CONTROL + int rc = select_pin_ctl(aw8697, "aw8697_reset_active"); + msleep(5); + rc = select_pin_ctl(aw8697, "aw8697_reset_reset"); + msleep(5); + rc = select_pin_ctl(aw8697, "aw8697_reset_active"); +#endif + if (!aw8697->enable_pin_control) { + if (aw8697 && gpio_is_valid(aw8697->reset_gpio)) { + gpio_set_value_cansleep(aw8697->reset_gpio, 0); + printk("%s pull down1\n", __func__); + msleep(5); + gpio_set_value_cansleep(aw8697->reset_gpio, 1); + printk("%s pull up1\n", __func__); + msleep(5); + } else { + dev_err(aw8697->dev, "%s: failed\n", __func__); + } + } + + return 0; +} + +/***************************************************** + * + * check chip id + * + *****************************************************/ +static int aw8697_read_chipid(struct aw8697 *aw8697) +{ + int ret = -1; + unsigned char cnt = 0; + unsigned char reg = 0; + + while (cnt < AW_READ_CHIPID_RETRIES) { + /* hardware reset */ + aw8697_hw_reset(aw8697); + + ret = aw8697_i2c_read(aw8697, AW8697_REG_ID, ®); + if (ret < 0) { + dev_err(aw8697->dev, + "%s: failed to read register AW8697_REG_ID: %d\n", + __func__, ret); + } + switch (reg) { + case AW8697_CHIPID: + pr_info("%s aw8697 detected\n", __func__); + aw8697->chipid = AW8697_CHIPID; + aw8697_haptic_softreset(aw8697); + return 0; + default: + pr_info("%s unsupported device revision (0x%x)\n", + __func__, reg); + break; + } + cnt++; + + msleep(AW_READ_CHIPID_RETRY_DELAY); + } + + return -EINVAL; +} + +/****************************************************** + * + * sys group attribute: reg + * + ******************************************************/ +static ssize_t aw8697_i2c_reg_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + + unsigned int databuf[2] = { 0, 0 }; + + if (2 == sscanf(buf, "%x %x", &databuf[0], &databuf[1])) { + aw8697_i2c_write(aw8697, (unsigned char)databuf[0], + (unsigned char)databuf[1]); + } + + return count; +} + +static ssize_t aw8697_i2c_reg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + unsigned char i = 0; + unsigned char reg_val = 0; + for (i = 0; i < AW8697_REG_MAX; i++) { + if (!(aw8697_reg_access[i] & REG_RD_ACCESS)) + continue; + aw8697_i2c_read(aw8697, i, ®_val); + len += snprintf(buf + len, PAGE_SIZE - len, + "reg:0x%02x=0x%02x \n", i, reg_val); + } + return len; +} + +static ssize_t aw8697_i2c_ram_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + + unsigned int databuf[1] = { 0 }; + + if (1 == sscanf(buf, "%x", &databuf[0])) { + if (1 == databuf[0]) { + aw8697_ram_update(aw8697); + } + } + + return count; +} + +static ssize_t aw8697_i2c_ram_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + unsigned int i = 0; + unsigned char reg_val = 0; + + aw8697_haptic_stop(aw8697); + /* RAMINIT Enable */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_EN); + + aw8697_i2c_write(aw8697, AW8697_REG_RAMADDRH, + (unsigned char)(aw8697->ram.base_addr >> 8)); + aw8697_i2c_write(aw8697, AW8697_REG_RAMADDRL, + (unsigned char)(aw8697->ram.base_addr & 0x00ff)); + len += snprintf(buf + len, PAGE_SIZE - len, "aw8697_haptic_ram:\n"); + for (i = 0; i < aw8697->ram.len; i++) { + aw8697_i2c_read(aw8697, AW8697_REG_RAMDATA, ®_val); + len += snprintf(buf + len, PAGE_SIZE - len, "0x%02x,", reg_val); + } + len += snprintf(buf + len, PAGE_SIZE - len, "\n"); + /* RAMINIT Disable */ + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_OFF); + + return len; +} + +static ssize_t aw8697_duration_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ktime_t time_rem; + s64 time_ms = 0; + + if (hrtimer_active(&aw8697->timer)) { + time_rem = hrtimer_get_remaining(&aw8697->timer); + time_ms = ktime_to_ms(time_rem); + } + + return snprintf(buf, PAGE_SIZE, "%lld\n", time_ms); +} + +static ssize_t aw8697_duration_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + /* setting 0 on duration is NOP for now */ + if (val <= 0) + return count; + + aw8697->duration = val; + + return count; +} + +static ssize_t aw8697_activate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + + /* For now nothing to show */ + return snprintf(buf, PAGE_SIZE, "%d\n", aw8697->state); +} + +static ssize_t aw8697_activate_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + ; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + if (val != 0 && val != 1) + return count; + + pr_debug("%s: value=%d\n", __FUNCTION__, val); + + mutex_lock(&aw8697->lock); + hrtimer_cancel(&aw8697->timer); + + aw8697->state = val; + + mutex_unlock(&aw8697->lock); + //schedule_work(&aw8697->vibrator_work); + queue_work(aw8697->work_queue, &aw8697->vibrator_work); + + return count; +} + +static ssize_t aw8697_activate_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "activate_mode=%d\n", + aw8697->activate_mode); +} + +static ssize_t aw8697_activate_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + mutex_lock(&aw8697->lock); + aw8697->activate_mode = val; + mutex_unlock(&aw8697->lock); + return count; +} + +static ssize_t aw8697_index_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned char reg_val = 0; + aw8697_i2c_read(aw8697, AW8697_REG_WAVSEQ1, ®_val); + aw8697->index = reg_val; + + return snprintf(buf, PAGE_SIZE, "%d\n", aw8697->index); +} + +static ssize_t aw8697_index_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + pr_debug("%s: value=%d\n", __FUNCTION__, val); + + mutex_lock(&aw8697->lock); + aw8697->index = val; + aw8697_haptic_set_repeat_wav_seq(aw8697, aw8697->index); + mutex_unlock(&aw8697->lock); + return count; +} + +static ssize_t aw8697_vmax_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "0x%02x\n", aw8697->vmax); +} + +static ssize_t aw8697_vmax_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + pr_debug("%s: value=%d\n", __FUNCTION__, val); + + mutex_lock(&aw8697->lock); + aw8697->vmax = val; + aw8697_haptic_set_bst_vol(aw8697, aw8697->vmax); + mutex_unlock(&aw8697->lock); + return count; +} + +static ssize_t aw8697_gain_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + return snprintf(buf, PAGE_SIZE, "0x%02x\n", aw8697->gain); +} + +static ssize_t aw8697_gain_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + pr_debug("%s: value=%d\n", __FUNCTION__, val); + + mutex_lock(&aw8697->lock); + aw8697->gain = val; + aw8697_haptic_set_gain(aw8697, aw8697->gain); + mutex_unlock(&aw8697->lock); + return count; +} + +static ssize_t aw8697_seq_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + size_t count = 0; + unsigned char i = 0; + unsigned char reg_val = 0; + + for (i = 0; i < AW8697_SEQUENCER_SIZE; i++) { + aw8697_i2c_read(aw8697, AW8697_REG_WAVSEQ1 + i, ®_val); + count += snprintf(buf + count, PAGE_SIZE - count, + "seq%d: 0x%02x\n", i + 1, reg_val); + aw8697->seq[i] |= reg_val; + } + return count; +} + +static ssize_t aw8697_seq_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[2] = { 0, 0 }; + + if (2 == sscanf(buf, "%x %x", &databuf[0], &databuf[1])) { + pr_debug("%s: seq%d=0x%x\n", __FUNCTION__, databuf[0], + databuf[1]); + mutex_lock(&aw8697->lock); + aw8697->seq[databuf[0]] = (unsigned char)databuf[1]; + aw8697_haptic_set_wav_seq(aw8697, (unsigned char)databuf[0], + aw8697->seq[databuf[0]]); + mutex_unlock(&aw8697->lock); + } + return count; +} + +static ssize_t aw8697_loop_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + size_t count = 0; + unsigned char i = 0; + unsigned char reg_val = 0; + + for (i = 0; i < AW8697_SEQUENCER_LOOP_SIZE; i++) { + aw8697_i2c_read(aw8697, AW8697_REG_WAVLOOP1 + i, ®_val); + aw8697->loop[i * 2 + 0] = (reg_val >> 4) & 0x0F; + aw8697->loop[i * 2 + 1] = (reg_val >> 0) & 0x0F; + + count += snprintf(buf + count, PAGE_SIZE - count, + "seq%d loop: 0x%02x\n", i * 2 + 1, + aw8697->loop[i * 2 + 0]); + count += snprintf(buf + count, PAGE_SIZE - count, + "seq%d loop: 0x%02x\n", i * 2 + 2, + aw8697->loop[i * 2 + 1]); + } + return count; +} + +static ssize_t aw8697_loop_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[2] = { 0, 0 }; + + if (2 == sscanf(buf, "%x %x", &databuf[0], &databuf[1])) { + pr_debug("%s: seq%d loop=0x%x\n", __FUNCTION__, databuf[0], + databuf[1]); + mutex_lock(&aw8697->lock); + aw8697->loop[databuf[0]] = (unsigned char)databuf[1]; + aw8697_haptic_set_wav_loop(aw8697, (unsigned char)databuf[0], + aw8697->loop[databuf[0]]); + mutex_unlock(&aw8697->lock); + } + + return count; +} + +static ssize_t aw8697_rtp_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + len += snprintf(buf + len, PAGE_SIZE - len, "rtp play: %d\n", + aw8697->rtp_cnt); + + return len; +} + +static ssize_t aw8697_rtp_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + aw8697_haptic_stop(aw8697); + aw8697_haptic_set_rtp_aei(aw8697, false); + aw8697_interrupt_clear(aw8697); + if (val < (sizeof(aw8697_rtp_name) / AW8697_RTP_NAME_MAX)) { + aw8697->rtp_file_num = val; + if (val) { + //schedule_work(&aw8697->rtp_work); + queue_work(aw8697->work_queue, &aw8697->rtp_work); + } + } else { + pr_err("%s: rtp_file_num 0x%02x over max value \n", __func__, + aw8697->rtp_file_num); + } + + return count; +} + +static ssize_t aw8697_ram_update_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + //struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + len += snprintf(buf + len, PAGE_SIZE - len, "sram update mode\n"); + return len; +} + +static ssize_t aw8697_ram_update_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + if (val) { + aw8697_ram_update(aw8697); + } + return count; +} + +static ssize_t aw8697_f0_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + + mutex_lock(&aw8697->lock); + aw8697->f0_cali_flag = AW8697_HAPTIC_LRA_F0; + aw8697_haptic_get_f0(aw8697); + mutex_unlock(&aw8697->lock); + len += + //snprintf(buf + len, PAGE_SIZE - len, "aw8697 lra f0 = %d\n", + snprintf(buf + len, PAGE_SIZE - len, "%d\n", aw8697->f0); + return len; +} + +static ssize_t aw8697_f0_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + return count; +} + +static ssize_t aw8697_cali_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + mutex_lock(&aw8697->lock); + aw8697->f0_cali_flag = AW8697_HAPTIC_CALI_F0; + aw8697_haptic_get_f0(aw8697); + mutex_unlock(&aw8697->lock); + len += snprintf(buf + len, PAGE_SIZE - len, "aw8697 cali f0 = %d\n", + aw8697->f0); + return len; +} + +static ssize_t aw8697_cali_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + if (val) { + mutex_lock(&aw8697->lock); + aw8697_haptic_f0_calibration(aw8697); + mutex_unlock(&aw8697->lock); + } + return count; +} + +static ssize_t aw8697_cont_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + aw8697_haptic_read_cont_f0(aw8697); + len += snprintf(buf + len, PAGE_SIZE - len, "aw8697 cont f0 = %d\n", + aw8697->cont_f0); + return len; +} + +static ssize_t aw8697_cont_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + aw8697_haptic_stop(aw8697); + if (val) { + aw8697_haptic_cont(aw8697); + } + return count; +} + +static ssize_t aw8697_cont_td_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + len += snprintf(buf + len, PAGE_SIZE - len, + "aw8697 cont delay time = 0x%04x\n", + aw8697->info.cont_td); + return len; +} + +static ssize_t aw8697_cont_td_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[1] = { 0 }; + if (1 == sscanf(buf, "%x", &databuf[0])) { + aw8697->info.cont_td = databuf[0]; + aw8697_i2c_write(aw8697, AW8697_REG_TD_H, + (unsigned char)(databuf[0] >> 8)); + aw8697_i2c_write(aw8697, AW8697_REG_TD_L, + (unsigned char)(databuf[0] >> 0)); + } + return count; +} + +static ssize_t aw8697_cont_drv_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + len += snprintf(buf + len, PAGE_SIZE - len, + "aw8697 cont drv level = %d\n", + aw8697->info.cont_drv_lvl); + len += snprintf(buf + len, PAGE_SIZE - len, + "aw8697 cont drv level overdrive= %d\n", + aw8697->info.cont_drv_lvl_ov); + return len; +} + +static ssize_t aw8697_cont_drv_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[2] = { 0, 0 }; + if (2 == sscanf(buf, "%d %d", &databuf[0], &databuf[1])) { + aw8697->info.cont_drv_lvl = databuf[0]; + aw8697_i2c_write(aw8697, AW8697_REG_DRV_LVL, + aw8697->info.cont_drv_lvl); + aw8697->info.cont_drv_lvl_ov = databuf[1]; + aw8697_i2c_write(aw8697, AW8697_REG_DRV_LVL_OV, + aw8697->info.cont_drv_lvl_ov); + } + return count; +} + +static ssize_t aw8697_cont_num_brk_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + len += snprintf(buf + len, PAGE_SIZE - len, + "aw8697 cont break num = %d\n", + aw8697->info.cont_num_brk); + return len; +} + +//return buffer size and availbe size +static ssize_t aw8697_custom_wave_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + len += snprintf(buf + len, PAGE_SIZE - len, "period_size=%d;", + aw8697->ram.base_addr >> 2); + len += snprintf(buf + len, PAGE_SIZE - len, "max_size=%d;free_size=%d;", + get_rb_max_size(), get_rb_free_size()); + len += snprintf(buf + len, PAGE_SIZE - len, "custom_wave_id=%d;", + CUSTOME_WAVE_ID); + return len; +} + +static ssize_t aw8697_custom_wave_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned long buf_len, period_size, offset; + int ret; + period_size = (aw8697->ram.base_addr >> 2); + offset = 0; + pr_debug(" write szie %d, period size %d", count, period_size); + if (count % period_size || count < period_size) + rb_end(); + atomic_set(&aw8697->is_in_write_loop, 1); + + while (count > 0) { + buf_len = min(count, period_size); + ret = write_rb(buf + offset, buf_len); + if (ret < 0) + goto exit; + count -= buf_len; + offset += buf_len; + } + ret = offset; +exit: + atomic_set(&aw8697->is_in_write_loop, 0); + wake_up_interruptible(&aw8697->stop_wait_q); + pr_debug(" return size %d", ret); + return ret; +} + +static ssize_t aw8697_cont_num_brk_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[1] = { 0 }; + if (1 == sscanf(buf, "%d", &databuf[0])) { + aw8697->info.cont_num_brk = databuf[0]; + if (aw8697->info.cont_num_brk > 7) { + aw8697->info.cont_num_brk = 7; + } + aw8697_i2c_write_bits(aw8697, AW8697_REG_BEMF_NUM, + AW8697_BIT_BEMF_NUM_BRK_MASK, + aw8697->info.cont_num_brk); + } + return count; +} + +static ssize_t aw8697_cont_zc_thr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + len += snprintf(buf + len, PAGE_SIZE - len, + "aw8697 cont zero cross thr = 0x%04x\n", + aw8697->info.cont_zc_thr); + return len; +} + +static ssize_t aw8697_cont_zc_thr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[1] = { 0 }; + if (1 == sscanf(buf, "%x", &databuf[0])) { + aw8697->info.cont_zc_thr = databuf[0]; + aw8697_i2c_write(aw8697, AW8697_REG_ZC_THRSH_H, + (unsigned char)(databuf[0] >> 8)); + aw8697_i2c_write(aw8697, AW8697_REG_ZC_THRSH_L, + (unsigned char)(databuf[0] >> 0)); + } + return count; +} + +static ssize_t aw8697_vbat_monitor_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + + mutex_lock(&aw8697->lock); + aw8697_haptic_stop(aw8697); + aw8697_haptic_get_vbat(aw8697); + len += snprintf(buf + len, PAGE_SIZE - len, "vbat=%dmV\n", + aw8697->vbat); + mutex_unlock(&aw8697->lock); + + return len; +} + +static ssize_t aw8697_vbat_monitor_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return count; +} + +static ssize_t aw8697_lra_resistance_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + unsigned char reg_val = 0; + + mutex_lock(&aw8697->lock); + aw8697_haptic_stop(aw8697); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_BST_MODE_MASK, + AW8697_BIT_SYSCTRL_BST_MODE_BYPASS); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_ANACTRL, + AW8697_BIT_ANACTRL_HD_PD_MASK, + AW8697_BIT_ANACTRL_HD_HZ_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_D2SCFG, + AW8697_BIT_D2SCFG_CLK_ADC_MASK, + AW8697_BIT_D2SCFG_CLK_ASC_1P5MHZ); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_DETCTRL, + AW8697_BIT_DETCTRL_RL_OS_MASK, + AW8697_BIT_DETCTRL_RL_DETECT); + aw8697_i2c_write_bits(aw8697, AW8697_REG_DETCTRL, + AW8697_BIT_DETCTRL_DIAG_GO_MASK, + AW8697_BIT_DETCTRL_DIAG_GO_ENABLE); + msleep(3); + aw8697_i2c_read(aw8697, AW8697_REG_RLDET, ®_val); + aw8697->lra = 298 * reg_val; + len += snprintf(buf + len, PAGE_SIZE - len, "%d\n", aw8697->lra); + //snprintf(buf + len, PAGE_SIZE - len, "r_lra=%dmohm\n", aw8697->lra); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_ANACTRL, + AW8697_BIT_ANACTRL_HD_PD_MASK, + AW8697_BIT_ANACTRL_HD_PD_EN); + aw8697_i2c_write_bits(aw8697, AW8697_REG_D2SCFG, + AW8697_BIT_D2SCFG_CLK_ADC_MASK, + AW8697_BIT_D2SCFG_CLK_ASC_6MHZ); + + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_RAMINIT_MASK, + AW8697_BIT_SYSCTRL_RAMINIT_OFF); + aw8697_i2c_write_bits(aw8697, AW8697_REG_SYSCTRL, + AW8697_BIT_SYSCTRL_BST_MODE_MASK, + AW8697_BIT_SYSCTRL_BST_MODE_BOOST); + mutex_unlock(&aw8697->lock); + + return len; +} + +static ssize_t aw8697_lra_resistance_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return count; +} + +static ssize_t aw8697_auto_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + + len += snprintf(buf + len, PAGE_SIZE - len, "auto_boost=%d\n", + aw8697->auto_boost); + + return len; +} + +static ssize_t aw8697_auto_boost_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + mutex_lock(&aw8697->lock); + aw8697_haptic_stop(aw8697); + aw8697_haptic_auto_boost_config(aw8697, val); + mutex_unlock(&aw8697->lock); + + return count; +} + +static ssize_t aw8697_prctmode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + unsigned char reg_val = 0; + + aw8697_i2c_read(aw8697, AW8697_REG_RLDET, ®_val); + + len += snprintf(buf + len, PAGE_SIZE - len, "prctmode=%d\n", + reg_val & 0x20); + return len; +} + +static ssize_t aw8697_prctmode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[2] = { 0, 0 }; + unsigned int addr = 0; + unsigned int val = 0; + if (2 == sscanf(buf, "%x %x", &databuf[0], &databuf[1])) { + addr = databuf[0]; + val = databuf[1]; + mutex_lock(&aw8697->lock); + aw8697_haptic_swicth_motorprotect_config(aw8697, addr, val); + mutex_unlock(&aw8697->lock); + } + return count; +} + +static ssize_t aw8697_trig_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + unsigned char i = 0; + for (i = 0; i < AW8697_TRIG_NUM; i++) { + len += snprintf( + buf + len, PAGE_SIZE - len, + "trig%d: enable=%d, default_level=%d, dual_edge=%d, frist_seq=%d, second_seq=%d\n", + i + 1, aw8697->trig[i].enable, + aw8697->trig[i].default_level, + aw8697->trig[i].dual_edge, aw8697->trig[i].frist_seq, + aw8697->trig[i].second_seq); + } + + return len; +} + +static ssize_t aw8697_trig_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int databuf[6] = { 0 }; + if (sscanf(buf, "%d %d %d %d %d %d", &databuf[0], &databuf[1], + &databuf[2], &databuf[3], &databuf[4], &databuf[5])) { + pr_debug("%s: %d, %d, %d, %d, %d, %d\n", __func__, databuf[0], + databuf[1], databuf[2], databuf[3], databuf[4], + databuf[5]); + if (databuf[0] > 3) { + databuf[0] = 3; + } + if (databuf[0] > 0) { + databuf[0] -= 1; + } + aw8697->trig[databuf[0]].enable = databuf[1]; + aw8697->trig[databuf[0]].default_level = databuf[2]; + aw8697->trig[databuf[0]].dual_edge = databuf[3]; + aw8697->trig[databuf[0]].frist_seq = databuf[4]; + aw8697->trig[databuf[0]].second_seq = databuf[5]; + mutex_lock(&aw8697->lock); + aw8697_haptic_trig_param_config(aw8697); + aw8697_haptic_trig_enable_config(aw8697); + mutex_unlock(&aw8697->lock); + } + return count; +} + +static ssize_t aw8697_ram_vbat_comp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + + len += snprintf(buf + len, PAGE_SIZE - len, "ram_vbat_comp=%d\n", + aw8697->ram_vbat_comp); + + return len; +} + +static ssize_t aw8697_ram_vbat_comp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + mutex_lock(&aw8697->lock); + if (val) { + aw8697->ram_vbat_comp = AW8697_HAPTIC_RAM_VBAT_COMP_ENABLE; + } else { + aw8697->ram_vbat_comp = AW8697_HAPTIC_RAM_VBAT_COMP_DISABLE; + } + mutex_unlock(&aw8697->lock); + + return count; +} + +static ssize_t aw8697_osc_cali_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + + len += snprintf(buf + len, PAGE_SIZE - len, "%d\n", + aw8697->lra_calib_data); + + return len; +} + +static ssize_t aw8697_osc_cali_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + + int rc = 0; + + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + + mutex_lock(&aw8697->lock); + /*osc calibration flag start,Other behaviors are forbidden*/ + aw8697->osc_cali_run = 1; + if (val == 3) { + aw8697_rtp_osc_calibration(aw8697); + aw8697_rtp_trim_lra_calibration(aw8697); + } + if (val == 1) + aw8697_rtp_osc_calibration(aw8697); + + aw8697->osc_cali_run = 0; + /*osc calibration flag end,Other behaviors are permitted*/ + mutex_unlock(&aw8697->lock); + + return count; +} + +static ssize_t aw8697_osc_save_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + pr_info("%s enter\n", __func__); + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + aw8697->lra_calib_data = val; + pr_info("%s load osa cal: %d\n", __func__, val); + + return count; +} + +static ssize_t aw8697_f0_save_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + ssize_t len = 0; + + len += snprintf(buf + len, PAGE_SIZE - len, "%d\n", + aw8697->f0_calib_data); + + return len; +} + +static ssize_t aw8697_f0_save_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + unsigned int val = 0; + int rc = 0; + + pr_info("%s enter\n", __func__); + rc = kstrtouint(buf, 0, &val); + if (rc < 0) + return rc; + aw8697->f0_calib_data = val; + pr_info("%s load f0 cal: %d\n", __func__, val); + + return count; +} + +static ssize_t aw8697_f0_value_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aw8697 *aw8697 = dev_get_drvdata(dev); + return snprintf(buf, PAGE_SIZE, "%d\n", aw8697->f0); +} + +static DEVICE_ATTR(activate_test, S_IWUSR | S_IRUGO, aw8697_activate_test_show, + aw8697_activate_test_store); + +static DEVICE_ATTR(reg, S_IWUSR | S_IRUGO, aw8697_i2c_reg_show, + aw8697_i2c_reg_store); +static DEVICE_ATTR(ram, S_IWUSR | S_IRUGO, aw8697_i2c_ram_show, + aw8697_i2c_ram_store); +static DEVICE_ATTR(duration, S_IWUSR | S_IRUGO, aw8697_duration_show, + aw8697_duration_store); +static DEVICE_ATTR(activate, S_IWUSR | S_IRUGO, aw8697_activate_show, + aw8697_activate_store); +static DEVICE_ATTR(activate_mode, S_IWUSR | S_IRUGO, aw8697_activate_mode_show, + aw8697_activate_mode_store); +static DEVICE_ATTR(index, S_IWUSR | S_IRUGO, aw8697_index_show, + aw8697_index_store); +static DEVICE_ATTR(vmax, S_IWUSR | S_IRUGO, aw8697_vmax_show, + aw8697_vmax_store); +static DEVICE_ATTR(gain, S_IWUSR | S_IRUGO, aw8697_gain_show, + aw8697_gain_store); +static DEVICE_ATTR(seq, S_IWUSR | S_IRUGO, aw8697_seq_show, aw8697_seq_store); +static DEVICE_ATTR(loop, S_IWUSR | S_IRUGO, aw8697_loop_show, + aw8697_loop_store); +static DEVICE_ATTR(rtp, S_IWUSR | S_IRUGO, aw8697_rtp_show, aw8697_rtp_store); +static DEVICE_ATTR(ram_update, S_IWUSR | S_IRUGO, aw8697_ram_update_show, + aw8697_ram_update_store); +static DEVICE_ATTR(f0, S_IWUSR | S_IRUGO, aw8697_f0_show, aw8697_f0_store); +static DEVICE_ATTR(cali, S_IWUSR | S_IRUGO, aw8697_cali_show, + aw8697_cali_store); +static DEVICE_ATTR(cont, S_IWUSR | S_IRUGO, aw8697_cont_show, + aw8697_cont_store); +static DEVICE_ATTR(cont_td, S_IWUSR | S_IRUGO, aw8697_cont_td_show, + aw8697_cont_td_store); +static DEVICE_ATTR(cont_drv, S_IWUSR | S_IRUGO, aw8697_cont_drv_show, + aw8697_cont_drv_store); +static DEVICE_ATTR(cont_num_brk, S_IWUSR | S_IRUGO, aw8697_cont_num_brk_show, + aw8697_cont_num_brk_store); +static DEVICE_ATTR(cont_zc_thr, S_IWUSR | S_IRUGO, aw8697_cont_zc_thr_show, + aw8697_cont_zc_thr_store); +static DEVICE_ATTR(vbat_monitor, S_IWUSR | S_IRUGO, aw8697_vbat_monitor_show, + aw8697_vbat_monitor_store); +static DEVICE_ATTR(lra_resistance, S_IWUSR | S_IRUGO, + aw8697_lra_resistance_show, aw8697_lra_resistance_store); +static DEVICE_ATTR(auto_boost, S_IWUSR | S_IRUGO, aw8697_auto_boost_show, + aw8697_auto_boost_store); +static DEVICE_ATTR(prctmode, S_IWUSR | S_IRUGO, aw8697_prctmode_show, + aw8697_prctmode_store); +static DEVICE_ATTR(trig, S_IWUSR | S_IRUGO, aw8697_trig_show, + aw8697_trig_store); +static DEVICE_ATTR(ram_vbat_comp, S_IWUSR | S_IRUGO, aw8697_ram_vbat_comp_show, + aw8697_ram_vbat_comp_store); +static DEVICE_ATTR(osc_cali, S_IWUSR | S_IRUGO, aw8697_osc_cali_show, + aw8697_osc_cali_store); +static DEVICE_ATTR(f0_save, S_IWUSR | S_IRUGO, aw8697_f0_save_show, + aw8697_f0_save_store); +static DEVICE_ATTR(osc_save, S_IWUSR | S_IRUGO, aw8697_osc_cali_show, + aw8697_osc_save_store); +static DEVICE_ATTR(f0_value, S_IRUGO, aw8697_f0_value_show, NULL); +static DEVICE_ATTR(custom_wave, S_IWUSR | S_IRUGO, aw8697_custom_wave_show, + aw8697_custom_wave_store); + +static struct attribute *aw8697_vibrator_attributes[] = { + &dev_attr_reg.attr, &dev_attr_ram.attr, + &dev_attr_activate_test.attr, &dev_attr_duration.attr, + &dev_attr_activate.attr, &dev_attr_activate_mode.attr, + &dev_attr_index.attr, &dev_attr_vmax.attr, + &dev_attr_gain.attr, &dev_attr_seq.attr, + &dev_attr_loop.attr, &dev_attr_rtp.attr, + &dev_attr_ram_update.attr, &dev_attr_f0.attr, + &dev_attr_cali.attr, &dev_attr_cont.attr, + &dev_attr_cont_td.attr, &dev_attr_cont_drv.attr, + &dev_attr_cont_num_brk.attr, &dev_attr_cont_zc_thr.attr, + &dev_attr_vbat_monitor.attr, &dev_attr_lra_resistance.attr, + &dev_attr_auto_boost.attr, &dev_attr_prctmode.attr, + &dev_attr_trig.attr, &dev_attr_ram_vbat_comp.attr, + &dev_attr_osc_cali.attr, &dev_attr_osc_save.attr, + &dev_attr_f0_save.attr, &dev_attr_f0_value.attr, + &dev_attr_custom_wave.attr, NULL +}; + +static struct attribute_group aw8697_vibrator_attribute_group = { + .attrs = aw8697_vibrator_attributes +}; + +/****************************************************** + * + * i2c driver + * + ******************************************************/ +static int aw8697_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct aw8697 *aw8697; + struct input_dev *input_dev; + int rc = 0, effect_count_max; + struct ff_device *ff; + struct device_node *np = i2c->dev.of_node; + int irq_flags = 0; + int ret = -1; +#ifdef ENABLE_PIN_CONTROL + int i; +#endif + + pr_info("%s enter\n", __func__); + if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) { + dev_err(&i2c->dev, "check_functionality failed\n"); + return -EIO; + } + + aw8697 = devm_kzalloc(&i2c->dev, sizeof(struct aw8697), GFP_KERNEL); + if (aw8697 == NULL) + return -ENOMEM; + + input_dev = devm_input_allocate_device(&i2c->dev); + if (!input_dev) + return -ENOMEM; + + aw8697->dev = &i2c->dev; + aw8697->i2c = i2c; + device_init_wakeup(aw8697->dev, true); + i2c_set_clientdata(i2c, aw8697); + + /* aw8697 rst & int */ + if (np) { + ret = aw8697_parse_dt(&i2c->dev, aw8697, np); + printk("%s ---%d \n", __func__, __LINE__); + if (ret) { + dev_err(&i2c->dev, + "%s: failed to parse device tree node\n", + __func__); + goto err_parse_dt; + } + } else { + aw8697->reset_gpio = -1; + aw8697->irq_gpio = -1; + } + aw8697->enable_pin_control = 0; +#ifdef ENABLE_PIN_CONTROL + aw8697->aw8697_pinctrl = devm_pinctrl_get(&i2c->dev); + if (IS_ERR(aw8697->aw8697_pinctrl)) { + if (PTR_ERR(aw8697->aw8697_pinctrl) == -EPROBE_DEFER) { + printk("pinctrl not ready\n"); + rc = -EPROBE_DEFER; + return rc; + } + printk("Target does not use pinctrl\n"); + aw8697->aw8697_pinctrl = NULL; + rc = -EINVAL; + return rc; + } + for (i = 0; i < ARRAY_SIZE(aw8697->pinctrl_state); i++) { + const char *n = pctl_names[i]; + struct pinctrl_state *state = + pinctrl_lookup_state(aw8697->aw8697_pinctrl, n); + if (IS_ERR(state)) { + printk("cannot find '%s'\n", n); + rc = -EINVAL; + //goto exit; + } + printk("found pin control %s\n", n); + aw8697->pinctrl_state[i] = state; + aw8697->enable_pin_control = 1; + aw8697_set_interrupt(aw8697); + } +#endif + printk("%s ---%d \n", __func__, __LINE__); + if (!aw8697->enable_pin_control) { + if (gpio_is_valid(aw8697->reset_gpio)) { + ret = devm_gpio_request_one(&i2c->dev, + aw8697->reset_gpio, + GPIOF_OUT_INIT_LOW, + "aw8697_rst"); + if (ret) { + dev_err(&i2c->dev, "%s: rst request failed\n", + __func__); + goto err_reset_gpio_request; + } + } + } + + if (gpio_is_valid(aw8697->irq_gpio)) { + ret = devm_gpio_request_one(&i2c->dev, aw8697->irq_gpio, + GPIOF_DIR_IN, "aw8697_int"); + if (ret) { + dev_err(&i2c->dev, "%s: int request failed\n", + __func__); + goto err_irq_gpio_request; + } + } + + ret = aw8697_read_chipid(aw8697); + if (ret < 0) { + dev_err(&i2c->dev, "%s: aw8697_read_chipid failed ret=%d\n", + __func__, ret); + goto err_id; + } + + if (gpio_is_valid(aw8697->irq_gpio) && + !(aw8697->flags & AW8697_FLAG_SKIP_INTERRUPTS)) { + /* register irq handler */ + aw8697_interrupt_setup(aw8697); + irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT; + ret = devm_request_threaded_irq(&i2c->dev, + gpio_to_irq(aw8697->irq_gpio), + NULL, aw8697_irq, irq_flags, + "aw8697", aw8697); + if (ret != 0) { + dev_err(&i2c->dev, "%s: failed to request IRQ %d: %d\n", + __func__, gpio_to_irq(aw8697->irq_gpio), ret); + goto err_irq; + } + } else { + dev_info(&i2c->dev, "%s skipping IRQ registration\n", __func__); + /* disable feature support if gpio was invalid */ + aw8697->flags |= AW8697_FLAG_SKIP_INTERRUPTS; + } + + hrtimer_init(&aw8697->stop_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + aw8697->stop_timer.function = qti_hap_stop_timer; + hrtimer_init(&aw8697->hap_disable_timer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + aw8697->hap_disable_timer.function = qti_hap_disable_timer; + + input_dev->name = "aw8697_haptic"; // "qti-haptics"; + input_set_drvdata(input_dev, aw8697); + aw8697->input_dev = input_dev; + input_set_capability(input_dev, EV_FF, FF_CONSTANT); + input_set_capability(input_dev, EV_FF, FF_GAIN); + if (aw8697->effects_count != 0) { + input_set_capability(input_dev, EV_FF, FF_PERIODIC); + input_set_capability(input_dev, EV_FF, FF_CUSTOM); + } + + if (aw8697->effects_count + 1 > FF_EFFECT_COUNT_MAX) + effect_count_max = aw8697->effects_count + 1; + else + effect_count_max = FF_EFFECT_COUNT_MAX; + rc = input_ff_create(input_dev, effect_count_max); + if (rc < 0) { + dev_err(aw8697->dev, "create FF input device failed, rc=%d\n", + rc); + return rc; + } + aw8697->work_queue = + create_singlethread_workqueue("aw8976_vibrator_work_queue"); + if (!aw8697->work_queue) { + dev_err(&i2c->dev, + "%s: Error creating aw8976_vibrator_work_queue\n", + __func__); + goto err_sysfs; + } + INIT_WORK(&aw8697->set_gain_work, set_gain); + aw8697_vibrator_init(aw8697); + aw8697_haptic_init(aw8697); + aw8697_ram_init(aw8697); + + ff = input_dev->ff; + ff->upload = aw8697_haptics_upload_effect; + ff->playback = aw8697_haptics_playback; + ff->erase = aw8697_haptics_erase; + ff->set_gain = aw8697_haptics_set_gain; + rc = input_register_device(input_dev); + if (rc < 0) { + dev_err(aw8697->dev, "register input device failed, rc=%d\n", + rc); + goto destroy_ff; + } + + dev_set_drvdata(&i2c->dev, aw8697); + ret = sysfs_create_group(&i2c->dev.kobj, + &aw8697_vibrator_attribute_group); + if (ret < 0) { + dev_info(&i2c->dev, "%s error creating sysfs attr files\n", + __func__); + goto err_sysfs; + } + + g_aw8697 = aw8697; + ret = create_rb(); + if (ret < 0) { + dev_info(&i2c->dev, "%s error creating ringbuffer\n", __func__); + goto err_rb; + } + + CUSTOME_WAVE_ID = aw8697->info.effect_max; + pr_info("%s probe completed successfully!\n", __func__); + + return 0; + +err_rb: + sysfs_remove_group(&i2c->dev.kobj, &aw8697_vibrator_attribute_group); +err_sysfs: + devm_free_irq(&i2c->dev, gpio_to_irq(aw8697->irq_gpio), aw8697); +destroy_ff: + input_ff_destroy(aw8697->input_dev); +err_irq: +err_id: + if (gpio_is_valid(aw8697->irq_gpio)) + devm_gpio_free(&i2c->dev, aw8697->irq_gpio); +err_irq_gpio_request: + if (gpio_is_valid(aw8697->reset_gpio)) + devm_gpio_free(&i2c->dev, aw8697->reset_gpio); +err_reset_gpio_request: +err_parse_dt: + device_init_wakeup(aw8697->dev, false); + devm_kfree(&i2c->dev, aw8697); + aw8697 = NULL; + return ret; +} + +static int aw8697_i2c_remove(struct i2c_client *i2c) +{ + struct aw8697 *aw8697 = i2c_get_clientdata(i2c); + + pr_info("%s enter\n", __func__); + + sysfs_remove_group(&i2c->dev.kobj, &aw8697_vibrator_attribute_group); + + devm_free_irq(&i2c->dev, gpio_to_irq(aw8697->irq_gpio), aw8697); + + if (gpio_is_valid(aw8697->irq_gpio)) + devm_gpio_free(&i2c->dev, aw8697->irq_gpio); + if (gpio_is_valid(aw8697->reset_gpio)) + devm_gpio_free(&i2c->dev, aw8697->reset_gpio); + if (aw8697 != NULL) { + flush_workqueue(aw8697->work_queue); + destroy_workqueue(aw8697->work_queue); + } + device_init_wakeup(aw8697->dev, false); + release_rb(); + devm_kfree(&i2c->dev, aw8697); + aw8697 = NULL; + + return 0; +} + +static const struct i2c_device_id aw8697_i2c_id[] = { { AW8697_I2C_NAME, 0 }, + {} }; + +MODULE_DEVICE_TABLE(i2c, aw8697_i2c_id); + +static struct of_device_id aw8697_dt_match[] = { + { .compatible = "awinic,aw8697_haptic" }, + {}, +}; + +static struct i2c_driver aw8697_i2c_driver = { + .driver = { + .name = AW8697_I2C_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(aw8697_dt_match), + }, + .probe = aw8697_i2c_probe, + .remove = aw8697_i2c_remove, + .id_table = aw8697_i2c_id, +}; + +static int __init aw8697_i2c_init(void) +{ + int ret = 0; + + pr_info("aw8697 driver version %s\n", AW8697_VERSION); + + ret = i2c_add_driver(&aw8697_i2c_driver); + if (ret) { + pr_err("fail to add aw8697 device into i2c\n"); + return ret; + } + + return 0; +} + +module_init(aw8697_i2c_init); + +static void __exit aw8697_i2c_exit(void) +{ + i2c_del_driver(&aw8697_i2c_driver); +} + +module_exit(aw8697_i2c_exit); + +MODULE_DESCRIPTION("AW8697 Haptic Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/misc/aw8697_haptic_xm/aw8697.h b/drivers/input/misc/aw8697_haptic_xm/aw8697.h new file mode 100644 index 000000000000..444023b954c4 --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/aw8697.h @@ -0,0 +1,454 @@ +#ifndef _AW8697_H_ +#define _AW8697_H_ + +/********************************************************* + * + * kernel version + * + ********************************************************/ +#define INPUT_DEV +//#define TEST_RTP +#define TEST_CONT_TO_RAM +/********************************************************* + * + * aw8697.h + * + ********************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +/********************************************************* + * + * marco + * + ********************************************************/ +#define AW8697_CHIPID 0x97 + +#define MAX_I2C_BUFFER_SIZE 65536 + +#define AW8697_SEQUENCER_SIZE 8 +#define AW8697_SEQUENCER_LOOP_SIZE 4 + +#define AW8697_RTP_I2C_SINGLE_MAX_NUM 512 + +#define HAPTIC_MAX_TIMEOUT 10000 + +#define AW8697_VBAT_REFER 4200 +#define AW8697_VBAT_MIN 3000 +#define AW8697_VBAT_MAX 4500 +#define ENABLE_PIN_CONTROL + +#ifdef INPUT_DEV +/* common definitions */ +#define HAP_BRAKE_PATTERN_MAX 4 +#define HAP_WAVEFORM_BUFFER_MAX 8 /*used */ +#define HAP_VMAX_MV_DEFAULT 1800 +#define HAP_VMAX_MV_MAX 3596 +#define HAP_PLAY_RATE_US_DEFAULT 5715 /*used */ +#define HAP_PLAY_RATE_US_MAX 20475 +#define HAP_PLAY_RATE_US_LSB 5 +#define VMAX_MIN_PLAY_TIME_US 20000 +#define HAP_SC_DET_MAX_COUNT 5 +#define HAP_SC_DET_TIME_US 1000000 +#define FF_EFFECT_COUNT_MAX 32 +#define HAP_DISABLE_DELAY_USEC 1000 +#endif +/* + * trig default high level + * ___________ _________________ + * | | + * | | + * |___________| + * first edge + * second edge + * + * + * trig default low level + * ___________ + * | | + * | | + * __________| |_________________ + * first edge + * second edge + */ +/* trig config */ +/*dts config +* default_level -> 1: high level; 0: low level +* dual_edge -> 1: dual edge; 0: first edge +*vib_trig_config = < +* 1 1 1 1 2 +* enable default_level dual_edge first_seq second_seq +* 1 1 2 1 2 +* enable default_level dual_edge first_seq second_seq +* 1 1 3 1 2 +* enable default_level dual_edge first_seq second_seq +*/ +#define AW8697_TRIG_NUM 3 + +enum aw8697_flags { + AW8697_FLAG_NONR = 0, + AW8697_FLAG_SKIP_INTERRUPTS = 1, +}; + +enum aw8697_haptic_read_write { + AW8697_HAPTIC_CMD_READ_REG = 0, + AW8697_HAPTIC_CMD_WRITE_REG = 1, +}; + +enum aw8697_haptic_work_mode { + AW8697_HAPTIC_STANDBY_MODE = 0, + AW8697_HAPTIC_RAM_MODE = 1, + AW8697_HAPTIC_RTP_MODE = 2, + AW8697_HAPTIC_TRIG_MODE = 3, + AW8697_HAPTIC_CONT_MODE = 4, + AW8697_HAPTIC_RAM_LOOP_MODE = 5, +}; + +enum aw8697_haptic_bst_mode { + AW8697_HAPTIC_BYPASS_MODE = 0, + AW8697_HAPTIC_BOOST_MODE = 1, +}; + +enum aw8697_haptic_activate_mode { + AW8697_HAPTIC_ACTIVATE_RAM_MODE = 0, + AW8697_HAPTIC_ACTIVATE_CONT_MODE = 1, + AW8697_HAPTIC_ACTIVATE_RTP_MODE = 2, + AW8697_HAPTIC_ACTIVATE_RAM_LOOP_MODE = 3, +}; + +enum aw8697_haptic_cont_vbat_comp_mode { + AW8697_HAPTIC_CONT_VBAT_SW_COMP_MODE = 0, + AW8697_HAPTIC_CONT_VBAT_HW_COMP_MODE = 1, +}; + +enum aw8697_haptic_ram_vbat_comp_mode { + AW8697_HAPTIC_RAM_VBAT_COMP_DISABLE = 0, + AW8697_HAPTIC_RAM_VBAT_COMP_ENABLE = 1, +}; + +enum aw8697_haptic_f0_flag { + AW8697_HAPTIC_LRA_F0 = 0, + AW8697_HAPTIC_CALI_F0 = 1, +}; + +enum aw8697_haptic_pwm_mode { + AW8697_PWM_48K = 0, + AW8697_PWM_24K = 1, + AW8697_PWM_12K = 2, +}; + +enum aw8697_haptic_play { + AW8697_HAPTIC_PLAY_NULL = 0, + AW8697_HAPTIC_PLAY_ENABLE = 1, + AW8697_HAPTIC_PLAY_STOP = 2, + AW8697_HAPTIC_PLAY_GAIN = 8, +}; + +enum aw8697_haptic_cmd { + AW8697_HAPTIC_CMD_NULL = 0, + AW8697_HAPTIC_CMD_ENABLE = 1, + AW8697_HAPTIC_CMD_STOP = 255, +}; + +enum haptics_custom_effect_param { + CUSTOM_DATA_EFFECT_IDX, + CUSTOM_DATA_TIMEOUT_SEC_IDX, + CUSTOM_DATA_TIMEOUT_MSEC_IDX, + CUSTOM_DATA_LEN, +}; +enum aw8697_haptic_strength { + AW8697_LIGHT_MAGNITUDE = 0x3fff, + AW8697_MEDIUM_MAGNITUDE = 0x5fff, + AW8697_STRONG_MAGNITUDE = 0x7fff, +}; +/********************************************************* + * + * struct + * + ********************************************************/ +struct fileops { + unsigned char cmd; + unsigned char reg; + unsigned char ram_addrh; + unsigned char ram_addrl; +}; + +struct ram { + unsigned int len; + unsigned int check_sum; + unsigned int base_addr; + unsigned char version; + unsigned char ram_shift; + unsigned char baseaddr_shift; +}; + +struct haptic_ctr { + unsigned char cmd; + unsigned char play; + unsigned char wavseq; + unsigned char loop; + unsigned char gain; +}; + +struct haptic_audio { + struct mutex lock; + struct hrtimer timer; + struct work_struct work; + int delay_val; + int timer_val; + unsigned char cnt; + struct haptic_ctr data[256]; + struct haptic_ctr ctr; + unsigned char ori_gain; +}; + +struct trig { + unsigned char enable; + unsigned char default_level; + unsigned char dual_edge; + unsigned char frist_seq; + unsigned char second_seq; +}; + +struct aw8697_dts_info { + unsigned int mode; + unsigned int f0_pre; + unsigned int f0_cali_percen; + unsigned int cont_drv_lvl; + unsigned int cont_drv_lvl_ov; + unsigned int cont_td; + unsigned int cont_zc_thr; + unsigned int cont_num_brk; + unsigned int f0_coeff; + unsigned int f0_trace_parameter[4]; + unsigned int bemf_config[4]; + unsigned int sw_brake; + unsigned int tset; + unsigned int r_spare; + unsigned int bstdbg[6]; + unsigned int parameter1; + unsigned int effect_id_boundary; + unsigned int effect_max; + unsigned int rtp_time[175]; + unsigned int trig_config[3][5]; + unsigned int bst_vol_default; + unsigned int bst_vol_ram; + unsigned int bst_vol_rtp; +}; + +#ifdef INPUT_DEV +enum actutor_type { + ACT_LRA, + ACT_ERM, +}; + +enum lra_res_sig_shape { + RES_SIG_SINE, + RES_SIG_SQUARE, +}; + +enum lra_auto_res_mode { + AUTO_RES_MODE_ZXD, + AUTO_RES_MODE_QWD, +}; + +enum wf_src { + INT_WF_VMAX, + INT_WF_BUFFER, + EXT_WF_AUDIO, + EXT_WF_PWM, +}; + +struct qti_hap_effect { + int id; + u8 *pattern; + int pattern_length; + u16 play_rate_us; + u16 vmax_mv; + u8 wf_repeat_n; + u8 wf_s_repeat_n; + u8 brake[HAP_BRAKE_PATTERN_MAX]; + int brake_pattern_length; + bool brake_en; + bool lra_auto_res_disable; +}; + +struct qti_hap_play_info { + struct qti_hap_effect *effect; + u16 vmax_mv; + int length_us; + int playing_pos; + bool playing_pattern; +}; + +struct qti_hap_config { + enum actutor_type act_type; + enum lra_res_sig_shape lra_shape; + enum lra_auto_res_mode lra_auto_res_mode; + enum wf_src ext_src; + u16 vmax_mv; + u16 play_rate_us; + bool lra_allow_variable_play_rate; + bool use_ext_wf_src; +}; +#endif + +#ifdef ENABLE_PIN_CONTROL +const char *const pctl_names[] = { + "aw8697_reset_reset", + "aw8697_reset_active", + "aw8697_interrupt_active", +}; +#endif +struct aw8697 { + struct i2c_client *i2c; + struct mutex lock; +#ifdef ENABLE_PIN_CONTROL + struct pinctrl *aw8697_pinctrl; + struct pinctrl_state *pinctrl_state[ARRAY_SIZE(pctl_names)]; +#endif + int enable_pin_control; + struct work_struct vibrator_work; + struct work_struct rtp_work; + struct work_struct set_gain_work; + struct delayed_work ram_work; + + struct fileops fileops; + struct ram ram; + + struct timeval start, end; + unsigned int timeval_flags; + unsigned int osc_cali_flag; + unsigned long int microsecond; + unsigned int sys_frequency; + unsigned int rtp_len; + unsigned int lra_calib_data; + unsigned int f0_calib_data; + + int reset_gpio; + int irq_gpio; + + unsigned char hwen_flag; + unsigned char flags; + unsigned char chipid; + + unsigned char play_mode; + + unsigned char activate_mode; + + unsigned char auto_boost; + + int state; + int duration; + int amplitude; + int index; + int vmax; + int gain; + u16 new_gain; + unsigned char level; + + unsigned char seq[AW8697_SEQUENCER_SIZE]; + unsigned char loop[AW8697_SEQUENCER_SIZE]; + + unsigned int rtp_cnt; + unsigned int rtp_file_num; + + unsigned char rtp_init; + unsigned char ram_init; + + unsigned int f0; + unsigned int cont_f0; + unsigned char max_pos_beme; + unsigned char max_neg_beme; + unsigned char f0_cali_flag; + unsigned int osc_cali_run; + + unsigned char ram_vbat_comp; + unsigned int vbat; + unsigned int lra; + + struct trig trig[AW8697_TRIG_NUM]; + + struct haptic_audio haptic_audio; + struct aw8697_dts_info info; + atomic_t is_in_rtp_loop; + atomic_t exit_in_rtp_loop; + atomic_t is_in_write_loop; + wait_queue_head_t wait_q; //wait queue for exit irq mode + wait_queue_head_t stop_wait_q; //wait queue for stop rtp mode + struct workqueue_struct *work_queue; + +#ifdef INPUT_DEV + struct platform_device *pdev; + struct device *dev; + struct regmap *regmap; + struct input_dev *input_dev; + struct pwm_device *pwm_dev; + struct qti_hap_config config; + struct qti_hap_play_info play; + struct qti_hap_effect *predefined; + struct qti_hap_effect constant; + struct regulator *vdd_supply; + struct hrtimer stop_timer; + struct hrtimer hap_disable_timer; + struct hrtimer timer; /*test used ,del */ + struct dentry *hap_debugfs; + struct mutex rtp_lock; + spinlock_t bus_lock; + ktime_t last_sc_time; + int play_irq; + int sc_irq; + int effects_count; + int sc_det_count; + u16 reg_base; + bool perm_disable; + bool play_irq_en; + bool vdd_enabled; + int effect_type; + int effect_id; + int test_val; + int is_custom_wave; +#endif +}; + +struct aw8697_container { + int len; + unsigned char data[]; +}; + +/********************************************************* + * + * ioctl + * + ********************************************************/ +struct aw8697_seq_loop { + unsigned char loop[AW8697_SEQUENCER_SIZE]; +}; + +struct aw8697_que_seq { + unsigned char index[AW8697_SEQUENCER_SIZE]; +}; + +#define AW8697_HAPTIC_IOCTL_MAGIC 'h' + +#define AW8697_HAPTIC_SET_QUE_SEQ \ + _IOWR(AW8697_HAPTIC_IOCTL_MAGIC, 1, struct aw8697_que_seq *) +#define AW8697_HAPTIC_SET_SEQ_LOOP \ + _IOWR(AW8697_HAPTIC_IOCTL_MAGIC, 2, struct aw8697_seq_loop *) +#define AW8697_HAPTIC_PLAY_QUE_SEQ \ + _IOWR(AW8697_HAPTIC_IOCTL_MAGIC, 3, unsigned int) +#define AW8697_HAPTIC_SET_BST_VOL \ + _IOWR(AW8697_HAPTIC_IOCTL_MAGIC, 4, unsigned int) +#define AW8697_HAPTIC_SET_BST_PEAK_CUR \ + _IOWR(AW8697_HAPTIC_IOCTL_MAGIC, 5, unsigned int) +#define AW8697_HAPTIC_SET_GAIN _IOWR(AW8697_HAPTIC_IOCTL_MAGIC, 6, unsigned int) +#define AW8697_HAPTIC_PLAY_REPEAT_SEQ \ + _IOWR(AW8697_HAPTIC_IOCTL_MAGIC, 7, unsigned int) + +#endif diff --git a/drivers/input/misc/aw8697_haptic_xm/aw8697_config.h b/drivers/input/misc/aw8697_haptic_xm/aw8697_config.h new file mode 100644 index 000000000000..ca3119c0d868 --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/aw8697_config.h @@ -0,0 +1,117 @@ +#ifndef __AW8697_CONFIG_H__ +#define __AW8697_CONFIG_H__ + +#define AW8697_BSTCFG_PEAKCUR_LIMIT 0x07 +#define AW8697_DEFAULT_PEAKCUR AW8697_BIT_BSTCFG_PEAKCUR_3P5A + +#define AW8697_CONT_PLAYBACK_MODE AW8697_BIT_CONT_CTRL_CLOSE_PLAYBACK + +/*#define CONFIG_DEBUG_FS*/ + +/*#ifdef INPUT_DEV*/ +#if 1 +/* haptics module register definitions */ +#define REG_HAP_STATUS1 0x0A +#define HAP_SC_DET_BIT BIT(3) +#define HAP_BUSY_BIT BIT(1) + +#define REG_HAP_EN_CTL1 0x46 +#define HAP_EN_BIT BIT(7) + +#define REG_HAP_EN_CTL2 0x48 +#define HAP_AUTO_STANDBY_EN_BIT BIT(1) +#define HAP_BRAKE_EN_BIT BIT(0) + +#define REG_HAP_EN_CTL3 0x4A +#define HAP_HBRIDGE_EN_BIT BIT(7) +#define HAP_PWM_SIGNAL_EN_BIT BIT(6) +#define HAP_ILIM_EN_BIT BIT(5) +#define HAP_ILIM_CC_EN_BIT BIT(4) +#define HAP_AUTO_RES_RBIAS_EN_BIT BIT(3) +#define HAP_DAC_EN_BIT BIT(2) +#define HAP_ZX_HYST_EN_BIT BIT(1) +#define HAP_PWM_CTL_EN_BIT BIT(0) + +#define REG_HAP_AUTO_RES_CTRL 0x4B +#define HAP_AUTO_RES_EN_BIT BIT(7) +#define HAP_SEL_AUTO_RES_PERIOD BIT(6) +#define HAP_AUTO_RES_CNT_ERR_DELTA_MASK GENMASK(5, 4) +#define HAP_AUTO_RES_CNT_ERR_DELTA_SHIFT 4 +#define HAP_AUTO_RES_ERR_RECOVERY_BIT BIT(3) +#define HAP_AUTO_RES_EN_DLY_MASK GENMASK(2, 0) +#define AUTO_RES_CNT_ERR_DELTA(x) (x << HAP_AUTO_RES_CNT_ERR_DELTA_SHIFT) +#define AUTO_RES_EN_DLY(x) x + +#define REG_HAP_CFG1 0x4C +#define REG_HAP_CFG2 0x4D +#define HAP_LRA_RES_TYPE_BIT BIT(0) + +#define REG_HAP_SEL 0x4E +#define HAP_WF_SOURCE_MASK GENMASK(5, 4) +#define HAP_WF_SOURCE_SHIFT 4 +#define HAP_WF_TRIGGER_BIT BIT(0) +#define HAP_WF_SOURCE_VMAX (0 << HAP_WF_SOURCE_SHIFT) +#define HAP_WF_SOURCE_BUFFER (1 << HAP_WF_SOURCE_SHIFT) +#define HAP_WF_SOURCE_AUDIO (2 << HAP_WF_SOURCE_SHIFT) +#define HAP_WF_SOURCE_PWM (3 << HAP_WF_SOURCE_SHIFT) + +#define REG_HAP_AUTO_RES_CFG 0x4F +#define HAP_AUTO_RES_MODE_BIT BIT(7) +#define HAP_AUTO_RES_MODE_SHIFT 7 +#define HAP_AUTO_RES_CAL_DURATON_MASK GENMASK(6, 5) +#define HAP_CAL_EOP_EN_BIT BIT(3) +#define HAP_CAL_PERIOD_MASK GENMASK(2, 0) +#define HAP_CAL_OPT3_EVERY_8_PERIOD 2 + +#define REG_HAP_SLEW_CFG 0x50 +#define REG_HAP_VMAX_CFG 0x51 +#define HAP_VMAX_SIGN_BIT BIT(7) +#define HAP_VMAX_OVD_BIT BIT(6) +#define HAP_VMAX_MV_MASK GENMASK(5, 1) +#define HAP_VMAX_MV_SHIFT 1 +#define HAP_VMAX_MV_LSB 116 + +#define REG_HAP_ILIM_CFG 0x52 +#define HAP_ILIM_SEL_1000MA BIT(1) +#define HAP_ILIM_DEFAULT_SEL HAP_ILIM_SEL_1000MA +#define REG_HAP_SC_DEB_CFG 0x53 +#define REG_HAP_RATE_CFG1 0x54 +#define REG_HAP_RATE_CFG2 0x55 +#define REG_HAP_INTERNAL_PWM 0x56 +#define REG_HAP_EXTERNAL_PWM 0x57 +#define REG_HAP_PWM 0x58 + +#define REG_HAP_SC_CLR 0x59 +#define HAP_SC_CLR_BIT BIT(0) + +#define REG_HAP_ZX_CFG 0x5A +#define HAP_ZX_DET_DEB_MASK GENMASK(2, 0) +#define ZX_DET_DEB_10US 0 +#define ZX_DET_DEB_20US 1 +#define ZX_DET_DEB_40US 2 +#define ZX_DET_DEB_80US 3 + +#define REG_HAP_BRAKE 0x5C +#define HAP_BRAKE_PATTERN_MASK 0x3 +#define HAP_BRAKE_PATTERN_SHIFT 2 + +#define REG_HAP_WF_REPEAT 0x5E +#define HAP_WF_REPEAT_MASK GENMASK(6, 4) +#define HAP_WF_REPEAT_SHIFT 4 +#define HAP_WF_S_REPEAT_MASK GENMASK(1, 0) + +#define REG_HAP_WF_S1 0x60 +#define HAP_WF_SIGN_BIT BIT(7) +#define HAP_WF_OVD_BIT BIT(6) +#define HAP_WF_AMP_BIT GENMASK(5, 1) +#define HAP_WF_AMP_SHIFT 1 + +#define REG_HAP_PLAY 0x70 +#define HAP_PLAY_BIT BIT(7) + +#define REG_HAP_SEC_ACCESS 0xD0 + +static int wf_repeat[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; +static int wf_s_repeat[4] = { 1, 2, 4, 8 }; +#endif +#endif diff --git a/drivers/input/misc/aw8697_haptic_xm/aw8697_reg.h b/drivers/input/misc/aw8697_haptic_xm/aw8697_reg.h new file mode 100644 index 000000000000..09e5424eda6f --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/aw8697_reg.h @@ -0,0 +1,539 @@ +#ifndef _AW8697_REG_H_ +#define _AW8697_REG_H_ + +/******************************************** + * Register List + *******************************************/ +#define AW8697_REG_ID 0x00 +#define AW8697_REG_SYSST 0x01 +#define AW8697_REG_SYSINT 0x02 +#define AW8697_REG_SYSINTM 0x03 +#define AW8697_REG_SYSCTRL 0x04 +#define AW8697_REG_GO 0x05 +#define AW8697_REG_RTP_DATA 0x06 +#define AW8697_REG_WAVSEQ1 0x07 +#define AW8697_REG_WAVSEQ2 0x08 +#define AW8697_REG_WAVSEQ3 0x09 +#define AW8697_REG_WAVSEQ4 0x0a +#define AW8697_REG_WAVSEQ5 0x0b +#define AW8697_REG_WAVSEQ6 0x0c +#define AW8697_REG_WAVSEQ7 0x0d +#define AW8697_REG_WAVSEQ8 0x0e +#define AW8697_REG_WAVLOOP1 0x0f +#define AW8697_REG_WAVLOOP2 0x10 +#define AW8697_REG_WAVLOOP3 0x11 +#define AW8697_REG_WAVLOOP4 0x12 +#define AW8697_REG_MAIN_LOOP 0x13 +#define AW8697_REG_TRG1_WAV_P 0x14 +#define AW8697_REG_TRG2_WAV_P 0x15 +#define AW8697_REG_TRG3_WAV_P 0x16 +#define AW8697_REG_TRG1_WAV_N 0x17 +#define AW8697_REG_TRG2_WAV_N 0x18 +#define AW8697_REG_TRG3_WAV_N 0x19 +#define AW8697_REG_TRG_PRIO 0x1a +#define AW8697_REG_TRG_CFG1 0x1b +#define AW8697_REG_TRG_CFG2 0x1c +#define AW8697_REG_DBGCTRL 0x20 +#define AW8697_REG_BASE_ADDRH 0x21 +#define AW8697_REG_BASE_ADDRL 0x22 +#define AW8697_REG_FIFO_AEH 0x23 +#define AW8697_REG_FIFO_AEL 0x24 +#define AW8697_REG_FIFO_AFH 0x25 +#define AW8697_REG_FIFO_AFL 0x26 +#define AW8697_REG_WAKE_DLY 0x27 +#define AW8697_REG_START_DLY 0x28 +#define AW8697_REG_END_DLY_H 0x29 +#define AW8697_REG_END_DLY_L 0x2a +#define AW8697_REG_DATCTRL 0x2b +#define AW8697_REG_PWMDEL 0x2c +#define AW8697_REG_PWMPRC 0x2d +#define AW8697_REG_PWMDBG 0x2e +#define AW8697_REG_LDOCTRL 0x2f +#define AW8697_REG_DBGSTAT 0x30 +#define AW8697_REG_BSTDBG1 0x31 +#define AW8697_REG_BSTDBG2 0x32 +#define AW8697_REG_BSTDBG3 0x33 +#define AW8697_REG_BSTCFG 0x34 +#define AW8697_REG_ANADBG 0x35 +#define AW8697_REG_ANACTRL 0x36 +#define AW8697_REG_CPDBG 0x37 +#define AW8697_REG_GLBDBG 0x38 +#define AW8697_REG_DATDBG 0x39 +#define AW8697_REG_BSTDBG4 0x3a +#define AW8697_REG_BSTDBG5 0x3b +#define AW8697_REG_BSTDBG6 0x3c +#define AW8697_REG_HDRVDBG 0x3d +#define AW8697_REG_PRLVL 0x3e +#define AW8697_REG_PRTIME 0x3f +#define AW8697_REG_RAMADDRH 0x40 +#define AW8697_REG_RAMADDRL 0x41 +#define AW8697_REG_RAMDATA 0x42 +#define AW8697_REG_GLB_STATE 0x46 +#define AW8697_REG_BST_AUTO 0x47 +#define AW8697_REG_CONT_CTRL 0x48 +#define AW8697_REG_F_PRE_H 0x49 +#define AW8697_REG_F_PRE_L 0x4a +#define AW8697_REG_TD_H 0x4b +#define AW8697_REG_TD_L 0x4c +#define AW8697_REG_TSET 0x4d +#define AW8697_REG_TRIM_LRA 0x5b +#define AW8697_REG_R_SPARE 0x5d +#define AW8697_REG_D2SCFG 0x5e +#define AW8697_REG_DETCTRL 0x5f +#define AW8697_REG_RLDET 0x60 +#define AW8697_REG_OSDET 0x61 +#define AW8697_REG_VBATDET 0x62 +#define AW8697_REG_TESTDET 0x63 +#define AW8697_REG_DETLO 0x64 +#define AW8697_REG_BEMFDBG 0x65 +#define AW8697_REG_ADCTEST 0x66 +#define AW8697_REG_BEMFTEST 0x67 +#define AW8697_REG_F_LRA_F0_H 0x68 +#define AW8697_REG_F_LRA_F0_L 0x69 +#define AW8697_REG_F_LRA_CONT_H 0x6a +#define AW8697_REG_F_LRA_CONT_L 0x6b +#define AW8697_REG_WAIT_VOL_MP 0x6d +#define AW8697_REG_WAIT_VOL_MN 0x6f +#define AW8697_REG_BEMF_VOL_H 0x70 +#define AW8697_REG_BEMF_VOL_L 0x71 +#define AW8697_REG_ZC_THRSH_H 0x72 +#define AW8697_REG_ZC_THRSH_L 0x73 +#define AW8697_REG_BEMF_VTHH_H 0x74 +#define AW8697_REG_BEMF_VTHH_L 0x75 +#define AW8697_REG_BEMF_VTHL_H 0x76 +#define AW8697_REG_BEMF_VTHL_L 0x77 +#define AW8697_REG_BEMF_NUM 0x78 +#define AW8697_REG_DRV_TIME 0x79 +#define AW8697_REG_TIME_NZC 0x7a +#define AW8697_REG_DRV_LVL 0x7b +#define AW8697_REG_DRV_LVL_OV 0x7c +#define AW8697_REG_NUM_F0_1 0x7d +#define AW8697_REG_NUM_F0_2 0x7e +#define AW8697_REG_NUM_F0_3 0x7f + +/******************************************** + * Register Access + *******************************************/ +#define REG_NONE_ACCESS 0 +#define REG_RD_ACCESS (1 << 0) +#define REG_WR_ACCESS (1 << 1) +#define AW8697_REG_MAX 0xff + +const unsigned char aw8697_reg_access[AW8697_REG_MAX] = { + [AW8697_REG_ID] = REG_RD_ACCESS, + [AW8697_REG_SYSST] = REG_RD_ACCESS, + [AW8697_REG_SYSINT] = REG_RD_ACCESS, + [AW8697_REG_SYSINTM] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_SYSCTRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_GO] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_RTP_DATA] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ1] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ2] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ3] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ4] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ5] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ6] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ7] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVSEQ8] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVLOOP1] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVLOOP2] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVLOOP3] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAVLOOP4] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_MAIN_LOOP] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG1_WAV_P] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG2_WAV_P] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG3_WAV_P] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG1_WAV_N] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG2_WAV_N] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG3_WAV_N] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG_PRIO] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG_CFG1] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRG_CFG2] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DBGCTRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BASE_ADDRH] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BASE_ADDRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_FIFO_AEH] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_FIFO_AEL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_FIFO_AFH] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_FIFO_AFL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAKE_DLY] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_START_DLY] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_END_DLY_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_END_DLY_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DATCTRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_PWMDEL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_PWMPRC] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_PWMDBG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_LDOCTRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DBGSTAT] = REG_RD_ACCESS, + [AW8697_REG_BSTDBG1] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BSTDBG2] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BSTDBG3] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BSTCFG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_ANADBG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_ANACTRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_CPDBG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_GLBDBG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DATDBG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BSTDBG4] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BSTDBG5] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BSTDBG6] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_HDRVDBG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_PRLVL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_PRTIME] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_RAMADDRH] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_RAMADDRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_RAMDATA] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_GLB_STATE] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BST_AUTO] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_CONT_CTRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_F_PRE_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_F_PRE_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TD_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TD_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TSET] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TRIM_LRA] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_R_SPARE] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_D2SCFG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DETCTRL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_RLDET] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_OSDET] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_VBATDET] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TESTDET] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DETLO] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMFDBG] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_ADCTEST] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMFTEST] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_F_LRA_F0_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_F_LRA_F0_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_F_LRA_CONT_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_F_LRA_CONT_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAIT_VOL_MP] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_WAIT_VOL_MN] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMF_VOL_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMF_VOL_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_ZC_THRSH_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_ZC_THRSH_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMF_VTHH_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMF_VTHH_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMF_VTHL_H] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMF_VTHL_L] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_BEMF_NUM] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DRV_TIME] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_TIME_NZC] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DRV_LVL] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_DRV_LVL_OV] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_NUM_F0_1] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_NUM_F0_2] = REG_RD_ACCESS | REG_WR_ACCESS, + [AW8697_REG_NUM_F0_3] = REG_RD_ACCESS | REG_WR_ACCESS, +}; + +/****************************************************** + * Register Detail + *****************************************************/ +/* SYSST: reg0x01 */ +#define AW8697_BIT_SYSST_BSTERRS (1 << 7) +#define AW8697_BIT_SYSST_OVS (1 << 6) +#define AW8697_BIT_SYSST_UVLS (1 << 5) +#define AW8697_BIT_SYSST_FF_AES (1 << 4) +#define AW8697_BIT_SYSST_FF_AFS (1 << 3) +#define AW8697_BIT_SYSST_OCDS (1 << 2) +#define AW8697_BIT_SYSST_OTS (1 << 1) +#define AW8697_BIT_SYSST_DONES (1 << 0) + +/* SYSINT: reg0x02 */ +#define AW8697_BIT_SYSINT_BSTERRI (1 << 7) +#define AW8697_BIT_SYSINT_OVI (1 << 6) +#define AW8697_BIT_SYSINT_UVLI (1 << 5) +#define AW8697_BIT_SYSINT_FF_AEI (1 << 4) +#define AW8697_BIT_SYSINT_FF_AFI (1 << 3) +#define AW8697_BIT_SYSINT_OCDI (1 << 2) +#define AW8697_BIT_SYSINT_OTI (1 << 1) +#define AW8697_BIT_SYSINT_DONEI (1 << 0) + +/* SYSINTM: reg0x03 */ +#define AW8697_BIT_SYSINTM_BSTERR_MASK (~(1 << 7)) +#define AW8697_BIT_SYSINTM_BSTERR_OFF (1 << 7) +#define AW8697_BIT_SYSINTM_BSTERR_EN (0 << 7) +#define AW8697_BIT_SYSINTM_OV_MASK (~(1 << 6)) +#define AW8697_BIT_SYSINTM_OV_OFF (1 << 6) +#define AW8697_BIT_SYSINTM_OV_EN (0 << 6) +#define AW8697_BIT_SYSINTM_UVLO_MASK (~(1 << 5)) +#define AW8697_BIT_SYSINTM_UVLO_OFF (1 << 5) +#define AW8697_BIT_SYSINTM_UVLO_EN (0 << 5) +#define AW8697_BIT_SYSINTM_FF_AE_MASK (~(1 << 4)) +#define AW8697_BIT_SYSINTM_FF_AE_OFF (1 << 4) +#define AW8697_BIT_SYSINTM_FF_AE_EN (0 << 4) +#define AW8697_BIT_SYSINTM_FF_AF_MASK (~(1 << 3)) +#define AW8697_BIT_SYSINTM_FF_AF_OFF (1 << 3) +#define AW8697_BIT_SYSINTM_FF_AF_EN (0 << 3) +#define AW8697_BIT_SYSINTM_OCD_MASK (~(1 << 2)) +#define AW8697_BIT_SYSINTM_OCD_OFF (1 << 2) +#define AW8697_BIT_SYSINTM_OCD_EN (0 << 2) +#define AW8697_BIT_SYSINTM_OT_MASK (~(1 << 1)) +#define AW8697_BIT_SYSINTM_OT_OFF (1 << 1) +#define AW8697_BIT_SYSINTM_OT_EN (0 << 1) +#define AW8697_BIT_SYSINTM_DONE_MASK (~(1 << 0)) +#define AW8697_BIT_SYSINTM_DONE_OFF (1 << 0) +#define AW8697_BIT_SYSINTM_DONE_EN (0 << 0) + +/* SYSCTRL: reg0x04 */ +#define AW8697_BIT_SYSCTRL_WAVDAT_MODE_MASK (~(3 << 6)) +#define AW8697_BIT_SYSCTRL_WAVDAT_MODE_4X (3 << 6) +#define AW8697_BIT_SYSCTRL_WAVDAT_MODE_2X (0 << 6) +#define AW8697_BIT_SYSCTRL_WAVDAT_MODE_1X (1 << 6) +#define AW8697_BIT_SYSCTRL_RAMINIT_MASK (~(1 << 5)) +#define AW8697_BIT_SYSCTRL_RAMINIT_EN (1 << 5) +#define AW8697_BIT_SYSCTRL_RAMINIT_OFF (0 << 5) +#define AW8697_BIT_SYSCTRL_PLAY_MODE_MASK (~(3 << 2)) +#define AW8697_BIT_SYSCTRL_PLAY_MODE_CONT (2 << 2) +#define AW8697_BIT_SYSCTRL_PLAY_MODE_RTP (1 << 2) +#define AW8697_BIT_SYSCTRL_PLAY_MODE_RAM (0 << 2) +#define AW8697_BIT_SYSCTRL_BST_MODE_MASK (~(1 << 1)) +#define AW8697_BIT_SYSCTRL_BST_MODE_BOOST (1 << 1) +#define AW8697_BIT_SYSCTRL_BST_MODE_BYPASS (0 << 1) +#define AW8697_BIT_SYSCTRL_WORK_MODE_MASK (~(1 << 0)) +#define AW8697_BIT_SYSCTRL_STANDBY (1 << 0) +#define AW8697_BIT_SYSCTRL_ACTIVE (0 << 0) + +/* GO: reg0x05 */ +#define AW8697_BIT_GO_MASK (~(1 << 0)) +#define AW8697_BIT_GO_ENABLE (1 << 0) +#define AW8697_BIT_GO_DISABLE (0 << 0) + +/* WAVSEQ1: reg0x07 */ +#define AW8697_BIT_WAVSEQ1_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ1_WAV_FRM_SEQ1_MASK (~(127 << 0)) + +/* WAVSEQ2: reg0x08 */ +#define AW8697_BIT_WAVSEQ2_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ2_WAV_FRM_SEQ2_MASK (~(127 << 0)) + +/* WAVSEQ3: reg0x09 */ +#define AW8697_BIT_WAVSEQ3_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ3_WAV_FRM_SEQ3_MASK (~(127 << 0)) + +/* WAVSEQ4: reg0x0a */ +#define AW8697_BIT_WAVSEQ4_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ4_WAV_FRM_SEQ4_MASK (~(127 << 0)) + +/* WAVSEQ5: reg0x0b */ +#define AW8697_BIT_WAVSEQ5_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ5_WAV_FRM_SEQ5_MASK (~(127 << 0)) + +/* WAVSEQ6: reg0x0c */ +#define AW8697_BIT_WAVSEQ6_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ6_WAV_FRM_SEQ6_MASK (~(127 << 0)) + +/* WAVSEQ7: reg0x0d */ +#define AW8697_BIT_WAVSEQ7_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ7_WAV_FRM_SEQ7_MASK (~(127 << 0)) + +/* WAVSEQ8: reg0x0e */ +#define AW8697_BIT_WAVSEQ8_WAIT (1 << 7) +#define AW8697_BIT_WAVSEQ8_WAV_FRM_SEQ8_MASK (~(127 << 0)) + +/* WAVLOOP: */ +#define AW8697_BIT_WAVLOOP_SEQN_MASK (~(15 << 4)) +#define AW8697_BIT_WAVLOOP_SEQNP1_MASK (~(15 << 0)) +#define AW8697_BIT_WAVLOOP_INIFINITELY (15 << 0) + +/* WAVLOOP1: reg0x0f */ +#define AW8697_BIT_WAVLOOP1_SEQ1_MASK (~(15 << 4)) +#define AW8697_BIT_WAVLOOP1_SEQ2_MASK (~(15 << 0)) + +/* WAVLOOP2: reg0x10 */ +#define AW8697_BIT_WAVLOOP2_SEQ3_MASK (~(15 << 4)) +#define AW8697_BIT_WAVLOOP2_SEQ4_MASK (~(15 << 0)) + +/* WAVLOOP3: reg0x11 */ +#define AW8697_BIT_WAVLOOP3_SEQ5_MASK (~(15 << 4)) +#define AW8697_BIT_WAVLOOP3_SEQ6_MASK (~(15 << 0)) + +/* WAVLOOP4: reg0x12 */ +#define AW8697_BIT_WAVLOOP4_SEQ7_MASK (~(15 << 4)) +#define AW8697_BIT_WAVLOOP4_SEQ8_MASK (~(15 << 0)) + +/* PLAYPRIO: reg0x1a */ +#define AW8697_BIT_PLAYPRIO_GO_MASK (~(3 << 6)) +#define AW8697_BIT_PLAYPRIO_TRIG3_MASK (~(3 << 4)) +#define AW8697_BIT_PLAYPRIO_TRIG2_MASK (~(3 << 2)) +#define AW8697_BIT_PLAYPRIO_TRIG1_MASK (~(3 << 0)) + +/* TRGCFG1: reg0x1b */ +#define AW8697_BIT_TRGCFG1_TRG3_POLAR_MASK (~(1 << 5)) +#define AW8697_BIT_TRGCFG1_TRG3_POLAR_NEG (1 << 5) +#define AW8697_BIT_TRGCFG1_TRG3_POLAR_POS (0 << 5) +#define AW8697_BIT_TRGCFG1_TRG3_EDGE_MASK (~(1 << 4)) +#define AW8697_BIT_TRGCFG1_TRG3_EDGE_POS (1 << 4) +#define AW8697_BIT_TRGCFG1_TRG3_EDGE_POS_NEG (0 << 4) +#define AW8697_BIT_TRGCFG1_TRG2_POLAR_MASK (~(1 << 3)) +#define AW8697_BIT_TRGCFG1_TRG2_POLAR_NEG (1 << 3) +#define AW8697_BIT_TRGCFG1_TRG2_POLAR_POS (0 << 3) +#define AW8697_BIT_TRGCFG1_TRG2_EDGE_MASK (~(1 << 2)) +#define AW8697_BIT_TRGCFG1_TRG2_EDGE_POS (1 << 2) +#define AW8697_BIT_TRGCFG1_TRG2_EDGE_POS_NEG (0 << 2) +#define AW8697_BIT_TRGCFG1_TRG1_POLAR_MASK (~(1 << 1)) +#define AW8697_BIT_TRGCFG1_TRG1_POLAR_NEG (1 << 1) +#define AW8697_BIT_TRGCFG1_TRG1_POLAR_POS (0 << 1) +#define AW8697_BIT_TRGCFG1_TRG1_EDGE_MASK (~(1 << 0)) +#define AW8697_BIT_TRGCFG1_TRG1_EDGE_POS (1 << 0) +#define AW8697_BIT_TRGCFG1_TRG1_EDGE_POS_NEG (0 << 0) + +/* TRGCFG2: reg0x1c */ +#define AW8697_BIT_TRGCFG2_TRG3_ENABLE_MASK (~(1 << 2)) +#define AW8697_BIT_TRGCFG2_TRG3_ENABLE (1 << 2) +#define AW8697_BIT_TRGCFG2_TRG3_DISABLE (0 << 2) +#define AW8697_BIT_TRGCFG2_TRG2_ENABLE_MASK (~(1 << 1)) +#define AW8697_BIT_TRGCFG2_TRG2_ENABLE (1 << 1) +#define AW8697_BIT_TRGCFG2_TRG2_DISABLE (0 << 1) +#define AW8697_BIT_TRGCFG2_TRG1_ENABLE_MASK (~(1 << 0)) +#define AW8697_BIT_TRGCFG2_TRG1_ENABLE (1 << 0) +#define AW8697_BIT_TRGCFG2_TRG1_DISABLE (0 << 0) + +/* DBGCTRL: reg0x20 */ +#define AW8697_BIT_DBGCTRL_INT_EDGE_MODE_MASK (~(1 << 3)) +#define AW8697_BIT_DBGCTRL_INT_EDGE_MODE_POS (1 << 3) +#define AW8697_BIT_DBGCTRL_INT_EDGE_MODE_BOTH (0 << 3) +#define AW8697_BIT_DBGCTRL_INT_MODE_MASK (~(1 << 2)) +#define AW8697_BIT_DBGCTRL_INT_MODE_EDGE (1 << 2) +#define AW8697_BIT_DBGCTRL_INT_MODE_LEVEL (0 << 2) + +/* DATCTRL: reg0x2b */ +#define AW8697_BIT_DATCTRL_FC_MASK (~(1 << 6)) +#define AW8697_BIT_DATCTRL_FC_1000HZ (3 << 6) +#define AW8697_BIT_DATCTRL_FC_800HZ (3 << 6) +#define AW8697_BIT_DATCTRL_FC_600HZ (1 << 6) +#define AW8697_BIT_DATCTRL_FC_400HZ (0 << 6) +#define AW8697_BIT_DATCTRL_LPF_ENABLE_MASK (~(1 << 5)) +#define AW8697_BIT_DATCTRL_LPF_ENABLE (1 << 5) +#define AW8697_BIT_DATCTRL_LPF_DISABLE (0 << 5) +#define AW8697_BIT_DATCTRL_WAKEMODE_ENABLE_MASK (~(1 << 0)) +#define AW8697_BIT_DATCTRL_WAKEMODE_ENABLE (1 << 0) +#define AW8697_BIT_DATCTRL_WAKEMODE_DISABLE (0 << 0) + +/* PWMPRC: reg0x2d */ +#define AW8697_BIT_PWMPRC_PRC_MASK (~(1 << 7)) +#define AW8697_BIT_PWMPRC_PRC_ENABLE (1 << 7) +#define AW8697_BIT_PWMPRC_PRC_DISABLE (0 << 7) +#define AW8697_BIT_PWMPRC_PRCTIME_MASK (~(0x7f << 0)) + +/* PWMDBG: reg0x2e */ +#define AW8697_BIT_PWMDBG_PWM_MODE_MASK (~(3 << 5)) +#define AW8697_BIT_PWMDBG_PWM_12K (3 << 5) +#define AW8697_BIT_PWMDBG_PWM_24K (2 << 5) +#define AW8697_BIT_PWMDBG_PWM_48K (0 << 5) + +/* DBGST: reg0x30 */ +#define AW8697_BIT_DBGSTAT_FF_EMPTY (1 << 0) +/* BSTCFG: reg0x34 */ +#define AW8697_BIT_BSTCFG_PEAKCUR_MASK (~(7 << 0)) +#define AW8697_BIT_BSTCFG_PEAKCUR_4A (7 << 0) +#define AW8697_BIT_BSTCFG_PEAKCUR_3P75A (6 << 0) +#define AW8697_BIT_BSTCFG_PEAKCUR_3P5A (5 << 0) +#define AW8697_BIT_BSTCFG_PEAKCUR_3P25A (4 << 0) +#define AW8697_BIT_BSTCFG_PEAKCUR_3A (3 << 0) +#define AW8697_BIT_BSTCFG_PEAKCUR_2P5A (2 << 0) +#define AW8697_BIT_BSTCFG_PEAKCUR_2A (1 << 0) +#define AW8697_BIT_BSTCFG_PEAKCUR_1P5A (0 << 0) + +/* ANADBG: reg0x35 */ +#define AW8697_BIT_ANADBG_IOC_MASK (~(3 << 2)) +#define AW8697_BIT_ANADBG_IOC_4P65A (3 << 2) +#define AW8697_BIT_ANADBG_IOC_4P15A (2 << 2) +#define AW8697_BIT_ANADBG_IOC_3P65A (1 << 2) +#define AW8697_BIT_ANADBG_IOC_3P15A (0 << 2) + +/* ANACTRL: reg0x36 */ +#define AW8697_BIT_ANACTRL_LRA_SRC_MASK (~(1 << 5)) +#define AW8697_BIT_ANACTRL_LRA_SRC_REG (1 << 5) +#define AW8697_BIT_ANACTRL_LRA_SRC_EFUSE (0 << 5) +#define AW8697_BIT_ANACTRL_HD_PD_MASK (~(1 << 3)) +#define AW8697_BIT_ANACTRL_HD_PD_EN (1 << 3) +#define AW8697_BIT_ANACTRL_HD_HZ_EN (0 << 3) + +/* BSTDBG4: reg0x3a */ +#define AW8697_BIT_BSTDBG4_BSTVOL_MASK (~(31 << 1)) + +/* PRLVL: reg0x3e */ +#define AW8697_BIT_PRLVL_PR_MASK (~(1 << 7)) +#define AW8697_BIT_PRLVL_PR_ENABLE (1 << 7) +#define AW8697_BIT_PRLVL_PR_DISABLE (0 << 7) +#define AW8697_BIT_PRLVL_PRLVL_MASK (~(0x7f << 0)) + +/*PRTIME: reg0x3f */ +#define AW8697_BIT_PRTIME_PRTIME_MASK (~(0xff << 0)) + +/* BST_AUTO: reg0x47 */ +#define AW8697_BIT_BST_AUTO_BST_AUTOSW_MASK (~(1 << 2)) +#define AW8697_BIT_BST_AUTO_BST_AUTOMATIC_BOOST (1 << 2) +#define AW8697_BIT_BST_AUTO_BST_MANUAL_BOOST (0 << 2) +#define AW8697_BIT_BST_AUTO_BST_RTP_MASK (~(1 << 1)) +#define AW8697_BIT_BST_AUTO_BST_RTP_ENABLE (1 << 1) +#define AW8697_BIT_BST_AUTO_BST_RTP_DISABLE (0 << 1) +#define AW8697_BIT_BST_AUTO_BST_RAM_MASK (~(1 << 0)) +#define AW8697_BIT_BST_AUTO_BST_RAM_ENABLE (1 << 0) +#define AW8697_BIT_BST_AUTO_BST_RAM_DISABLE (0 << 0) + +/* CONT_CTRL: reg0x48 */ +#define AW8697_BIT_CONT_CTRL_ZC_DETEC_MASK (~(1 << 7)) +#define AW8697_BIT_CONT_CTRL_ZC_DETEC_ENABLE (1 << 7) +#define AW8697_BIT_CONT_CTRL_ZC_DETEC_DISABLE (0 << 7) +#define AW8697_BIT_CONT_CTRL_WAIT_PERIOD_MASK (~(3 << 5)) +#define AW8697_BIT_CONT_CTRL_WAIT_8PERIOD (3 << 5) +#define AW8697_BIT_CONT_CTRL_WAIT_4PERIOD (2 << 5) +#define AW8697_BIT_CONT_CTRL_WAIT_2PERIOD (1 << 5) +#define AW8697_BIT_CONT_CTRL_WAIT_1PERIOD (0 << 5) +#define AW8697_BIT_CONT_CTRL_MODE_MASK (~(1 << 4)) +#define AW8697_BIT_CONT_CTRL_BY_DRV_TIME (1 << 4) +#define AW8697_BIT_CONT_CTRL_BY_GO_SIGNAL (0 << 4) +#define AW8697_BIT_CONT_CTRL_EN_CLOSE_MASK (~(1 << 3)) +#define AW8697_BIT_CONT_CTRL_CLOSE_PLAYBACK (1 << 3) +#define AW8697_BIT_CONT_CTRL_OPEN_PLAYBACK (0 << 3) +#define AW8697_BIT_CONT_CTRL_F0_DETECT_MASK (~(1 << 2)) +#define AW8697_BIT_CONT_CTRL_F0_DETECT_ENABLE (1 << 2) +#define AW8697_BIT_CONT_CTRL_F0_DETECT_DISABLE (0 << 2) +#define AW8697_BIT_CONT_CTRL_O2C_MASK (~(1 << 1)) +#define AW8697_BIT_CONT_CTRL_O2C_ENABLE (1 << 1) +#define AW8697_BIT_CONT_CTRL_O2C_DISABLE (0 << 1) +#define AW8697_BIT_CONT_CTRL_AUTO_BRK_MASK (~(1 << 0)) +#define AW8697_BIT_CONT_CTRL_AUTO_BRK_ENABLE (1 << 0) +#define AW8697_BIT_CONT_CTRL_AUTO_BRK_DISABLE (0 << 0) + +/* D2SCFG: reg0x5e */ +#define AW8697_BIT_D2SCFG_CLK_ADC_MASK (~(7 << 5)) +#define AW8697_BIT_D2SCFG_CLK_ASC_0P09375MHZ (7 << 5) +#define AW8697_BIT_D2SCFG_CLK_ASC_0P1875MHZ (6 << 5) +#define AW8697_BIT_D2SCFG_CLK_ASC_0P375MHZ (5 << 5) +#define AW8697_BIT_D2SCFG_CLK_ASC_0P75MHZ (4 << 5) +#define AW8697_BIT_D2SCFG_CLK_ASC_1P5MHZ (3 << 5) +#define AW8697_BIT_D2SCFG_CLK_ASC_3MHZ (2 << 5) +#define AW8697_BIT_D2SCFG_CLK_ASC_6MHZ (1 << 5) +#define AW8697_BIT_D2SCFG_CLK_ASC_12MHZ (0 << 5) + +/* DETCTRL: reg0x5f */ +#define AW8697_BIT_DETCTRL_RL_OS_MASK (~(1 << 6)) +#define AW8697_BIT_DETCTRL_RL_DETECT (1 << 6) +#define AW8697_BIT_DETCTRL_OS_DETECT (0 << 6) +#define AW8697_BIT_DETCTRL_PROTECT_MASK (~(1 << 5)) +#define AW8697_BIT_DETCTRL_PROTECT_NO_ACTION (1 << 5) +#define AW8697_BIT_DETCTRL_PROTECT_SHUTDOWN (0 << 5) +#define AW8697_BIT_DETCTRL_ADO_SLOT_MODE_MASK (~(1 << 4)) +#define AW8697_BIT_DETCTRL_ADO_SLOT_MODE_ENABLE (1 << 4) +#define AW8697_BIT_DETCTRL_ADO_SLOT_MODE_DISABLE (0 << 4) +#define AW8697_BIT_DETCTRL_VBAT_GO_MASK (~(1 << 1)) +#define AW8697_BIT_DETCTRL_VABT_GO_ENABLE (1 << 1) +#define AW8697_BIT_DETCTRL_VBAT_GO_DISBALE (0 << 1) +#define AW8697_BIT_DETCTRL_DIAG_GO_MASK (~(1 << 0)) +#define AW8697_BIT_DETCTRL_DIAG_GO_ENABLE (1 << 0) +#define AW8697_BIT_DETCTRL_DIAG_GO_DISABLE (0 << 0) + +/* ADCTEST: reg0x66 */ +#define AW8697_BIT_ADCTEST_VBAT_MODE_MASK (~(1 << 6)) +#define AW8697_BIT_ADCTEST_VBAT_HW_COMP (1 << 6) +#define AW8697_BIT_ADCTEST_VBAT_SW_COMP (0 << 6) + +/* BEMF_NUM: reg0x78 */ +#define AW8697_BIT_BEMF_NUM_BRK_MASK (~(15 << 0)) + +#endif diff --git a/drivers/input/misc/aw8697_haptic_xm/ringbuffer.c b/drivers/input/misc/aw8697_haptic_xm/ringbuffer.c new file mode 100644 index 000000000000..9b74ef480a5f --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/ringbuffer.c @@ -0,0 +1,228 @@ +/* +* reader shoule NEVER block !!!, if no data is avaliable, just return zero +* writer will block if there is no space, and wakend up by reader or force exit +* there is 1 writer and 1 reader for each buffer, so no lock is used +* writer shoule read rd_index to check if free size is enought, +* and then fill this buffer update wr_index +* reader shoule read wr_index to check if avaliable size is enought, +* and then read the buffer and update rd_index +* empty: wr_index==rd_index +* full: (wr_index +1) % BUFFER_SIZE == rd_index +* total avaliable size is BUFFER_SIZE -1 +*/ +#define DEBUG +#include +#include "ringbuffer.h" + +#define MIN(x, y) ((x) < (y) ? (x) : (y)) + +#define BUFFER_SIZE (1024 * 8 + 1) + +struct rb { + char *gbuffer; + atomic_t wr_index; + atomic_t rd_index; + atomic_t eof; + volatile int32_t aval_size; // avalibale to write size. + atomic_t buf_condition, exit; + wait_queue_head_t wait_q; +}; + +struct rb *grb; + +int32_t get_free_size(int32_t tail, int32_t head) +{ + if (head == tail) + return BUFFER_SIZE - 1; + else if (head < tail) + return (head + BUFFER_SIZE - 1 - tail); + else + return (head - tail - 1); +} + +int write_rb(const char *data, int32_t size) +{ + int32_t tail = atomic_read(&grb->wr_index); + int32_t head = atomic_read(&grb->rd_index); + int32_t part; + int32_t ret; + + grb->aval_size = get_free_size(tail, head); + + pr_debug("%s: write write index %d, read index %d, free size %d", + __func__, tail, head, grb->aval_size); + + while ((grb->aval_size < size) && (!atomic_read(&grb->exit))) { + pr_debug("%s: no space avaliable", __func__); + pr_info("%s: goint to waiting irq exit\n", __func__); + ret = wait_event_interruptible( + grb->wait_q, atomic_read(&grb->buf_condition) == 1); + if (ret == -ERESTARTSYS) { + pr_err("%s: wake up by signal return erro\n", __func__); + return ret; + } + + atomic_set(&grb->buf_condition, 0); + tail = atomic_read(&grb->wr_index); + head = atomic_read(&grb->rd_index); + grb->aval_size = get_free_size(tail, head); + } + if (atomic_read(&grb->exit) == 1) { + pr_debug("%s: exit write_rb", __func__); + return -EPERM; + } + + part = BUFFER_SIZE - tail; + if (part < size) { + memcpy(grb->gbuffer + tail, data, part); + memcpy(grb->gbuffer, data + part, size - part); + tail = size - part; + } else { + memcpy(grb->gbuffer + tail, data, size); + tail += size; + if (tail >= BUFFER_SIZE) + tail = tail % BUFFER_SIZE; + } + atomic_set(&grb->wr_index, tail); + grb->aval_size = get_free_size(tail, head); + pr_debug( + "%s: after write %d, write index %d, read index %d, aval_size %d", + __func__, size, tail, head, grb->aval_size); + return size; +} + +int read_rb(char *data, int32_t size) +{ + int32_t tail; + int32_t head; + int32_t filled_size; + void *buf; + int32_t read_bytes, part; + buf = data; + + pr_debug("%s: read_rb data:%p, size %d", __func__, data, (int)size); + + tail = atomic_read(&grb->wr_index); + head = atomic_read(&grb->rd_index); + grb->aval_size = get_free_size(tail, head); + filled_size = BUFFER_SIZE - 1 - grb->aval_size; // aready write size. + + pr_debug("%s: write index %d, read index %d, filled size %d", __func__, + tail, head, filled_size); + read_bytes = MIN(size, filled_size); + if (size > filled_size) + pr_debug("%s: buffer underrun , req size %d, filled size %d", + __func__, size, filled_size); + part = BUFFER_SIZE - head; + if (part < read_bytes) { + memcpy(buf, grb->gbuffer + head, part); + memcpy((char *)buf + part, grb->gbuffer, read_bytes - part); + head = read_bytes - part; + } else { + memcpy(buf, grb->gbuffer + head, read_bytes); + head += read_bytes; + if (head >= BUFFER_SIZE) + head = head % BUFFER_SIZE; + } + atomic_set(&grb->rd_index, head); + grb->aval_size = get_free_size(tail, head); + + //add wakeup here + atomic_set(&grb->buf_condition, 1); + wake_up_interruptible(&grb->wait_q); + pr_debug( + "%s: after read %d write index %d, read index %d, aval_size %d", + __func__, read_bytes, tail, head, grb->aval_size); + + return atomic_read(&grb->eof) ? read_bytes : size; +} + +int get_rb_free_size(void) +{ + int32_t tail = atomic_read(&grb->wr_index); + int32_t head = atomic_read(&grb->rd_index); + + grb->aval_size = get_free_size(tail, head); + return grb->aval_size; +} + +int get_rb_avalible_size(void) +{ + return BUFFER_SIZE - 1 - get_rb_free_size(); +} + +int get_rb_max_size(void) +{ + return BUFFER_SIZE - 1; +} + +void rb_force_exit(void) +{ + pr_debug("%s: rb force exit", __func__); + atomic_set(&grb->exit, 1); + atomic_set(&grb->buf_condition, 1); + wake_up_interruptible(&grb->wait_q); +} + +void rb_end(void) +{ + atomic_set(&grb->eof, 1); +} + +int rb_shoule_exit(void) +{ + return atomic_read(&grb->eof) || atomic_read(&grb->exit); +} + +int create_rb(void) +{ + int32_t tail; + int32_t head; + + grb = kzalloc(sizeof(struct rb), GFP_KERNEL); + if (grb == NULL) { + goto err; + } + grb->gbuffer = kzalloc(BUFFER_SIZE, GFP_KERNEL); + if (grb->gbuffer == NULL) { + goto err; + } + + rb_init(); + + init_waitqueue_head(&grb->wait_q); + tail = atomic_read(&grb->wr_index); + head = atomic_read(&grb->rd_index); + grb->aval_size = get_free_size(tail, head); + + return 0; +err: + if (grb) + kfree(grb); + if (grb->gbuffer) + kfree(grb->gbuffer); + return -EPERM; +} + +void rb_init(void) +{ + pr_debug("%s: rb init", __func__); + atomic_set(&grb->wr_index, 0); + atomic_set(&grb->rd_index, 0); + atomic_set(&grb->buf_condition, 0); + atomic_set(&grb->exit, 0); + atomic_set(&grb->eof, 0); +} + +int release_rb(void) +{ + if (grb != NULL) { + if (grb->gbuffer) { + kfree(grb->gbuffer); + grb->gbuffer = NULL; + } + kfree(grb); + grb = NULL; + } + return 0; +} diff --git a/drivers/input/misc/aw8697_haptic_xm/ringbuffer.h b/drivers/input/misc/aw8697_haptic_xm/ringbuffer.h new file mode 100644 index 000000000000..7c097386d935 --- /dev/null +++ b/drivers/input/misc/aw8697_haptic_xm/ringbuffer.h @@ -0,0 +1,36 @@ +/* +* reader shoule NEVER block !!!, if no data is avaliable, just return zero +* writer will block if there is no space, and wakend up by reader or force exit +* there is 1 writer and 1 reader for each buffer, so no lock is used +* writer shoule read rd_index to check if free size is enought, +* and then fill this buffer update wr_index +* reader shoule read wr_index to check if avaliable size is enought, +* and then read the buffer and update rd_index +* empty: wr_index==rd_index +* full: (wr_index +1) % BUFFER_SIZE == rd_index +* total avaliable size is BUFFER_SIZE -1 +*/ + +#ifndef _RINGBUFFER_H_ +#define _RINGBUFFER_H_ + +#include +#include +#include +#include +#include +#include +#include + +int write_rb(const char *data, int32_t size); +int read_rb(char *data, int32_t size); +int get_rb_free_size(void); +int get_rb_max_size(void); +void rb_force_exit(void); +void rb_end(void); +int rb_shoule_exit(void); +int create_rb(void); +void rb_init(void); +int release_rb(void); +int get_rb_avalible_size(void); +#endif From 8ece510d1f5630fe3464c6e34d64051cec08d2ed Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 28 Jan 2024 18:49:11 +0100 Subject: [PATCH 052/226] drivers: input: misc: Import Xiaomi keyboard driver * From nabu-r-oss * Run clang-format on source files Change-Id: I4dff75188b74114b9849506dc202cbaa61e75a27 Signed-off-by: firebird11 --- drivers/input/misc/Kconfig | 2 + drivers/input/misc/Makefile | 1 + drivers/input/misc/xiaomi_keyboard/Kconfig | 8 + drivers/input/misc/xiaomi_keyboard/Makefile | 1 + .../misc/xiaomi_keyboard/xiaomi_keyboard.c | 651 ++++++++++++++++++ .../misc/xiaomi_keyboard/xiaomi_keyboard.h | 47 ++ 6 files changed, 710 insertions(+) create mode 100644 drivers/input/misc/xiaomi_keyboard/Kconfig create mode 100644 drivers/input/misc/xiaomi_keyboard/Makefile create mode 100644 drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c create mode 100644 drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 4ff5b3406b8e..bd94be97e8ae 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -891,4 +891,6 @@ config INPUT_HISI_POWERKEY source "drivers/input/misc/aw8697_haptic_xm/Kconfig" +source "drivers/input/misc/xiaomi_keyboard/Kconfig" + endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index c790f73d3dd8..5659e0306f23 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -86,3 +86,4 @@ obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_INPUT_IDEAPAD_SLIDEBAR) += ideapad_slidebar.o obj-$(CONFIG_INPUT_AW8697_XM_HAPTIC) += aw8697_haptic_xm/ +obj-$(CONFIG_XIAOMI_KEYBOARD) += xiaomi_keyboard/ diff --git a/drivers/input/misc/xiaomi_keyboard/Kconfig b/drivers/input/misc/xiaomi_keyboard/Kconfig new file mode 100644 index 000000000000..bfc4b1d891e5 --- /dev/null +++ b/drivers/input/misc/xiaomi_keyboard/Kconfig @@ -0,0 +1,8 @@ +config XIAOMI_KEYBOARD + bool "xiaomi keyboard control-driver" + depends on INPUT + default n + help + Say Y here, compile xiaomi keyboard control driver. + + If unsure, say N. diff --git a/drivers/input/misc/xiaomi_keyboard/Makefile b/drivers/input/misc/xiaomi_keyboard/Makefile new file mode 100644 index 000000000000..0a00118c658e --- /dev/null +++ b/drivers/input/misc/xiaomi_keyboard/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_XIAOMI_KEYBOARD) += xiaomi_keyboard.o \ No newline at end of file diff --git a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c new file mode 100644 index 000000000000..962771069660 --- /dev/null +++ b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c @@ -0,0 +1,651 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "xiaomi_keyboard.h" +#include +#include + +static struct xiaomi_keyboard_data *mdata; + +static void set_keyboard_status(bool on); + +static void xiaomi_keyboard_reset(void) +{ + if (!mdata || !mdata->pdata) { + MI_KB_ERR("reset failed!Invalid Memory\n"); + return; + } + MI_KB_INFO("xiaomi keyboard IC Reset\n"); + gpio_direction_output(mdata->pdata->rst_gpio, 0); + msleep(2); + gpio_direction_output(mdata->pdata->rst_gpio, 1); +} + +static void xiaomi_keyboard_connected_notify(struct device *dev) +{ + sysfs_notify(&dev->kobj, NULL, "xiaomi_keyboard_conn_status"); + MI_KB_INFO("connected status notify\n"); +} + +static ssize_t xiaomi_keyboard_conn_status_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret = 0, value = 1; + MI_KB_INFO("%s enter\n", __func__); + if (!mdata) { + MI_KB_ERR("Invalid driver info\n"); + return ret; + } + + mutex_lock(&mdata->rw_mutex); + value = mdata->keyboard_conn_status; + mutex_unlock(&mdata->rw_mutex); + + return scnprintf(buf, PAGE_SIZE, "%d", value); +} + +static ssize_t xiaomi_keyboard_conn_status_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *cmd; + cmd = kzalloc(count + 1, GFP_KERNEL); + + if (!cmd) { + MI_KB_ERR("Allocate Meomory Failed\n"); + goto out; + } + memcpy(cmd, buf, count); + + if (!mdata) + goto out; + + if (!strncmp(cmd, "reset", 5)) { + xiaomi_keyboard_reset(); + } else if (!strncmp(cmd, "enable_keyboard", 15)) { + MI_KB_INFO("enable keyboard\n"); + set_keyboard_status(1); + } else if (!strncmp(cmd, "disable_keyboard", 16)) { + MI_KB_INFO("disable keyboard\n"); + set_keyboard_status(0); + } else + MI_KB_ERR("Undefined CMD: %s\n", cmd); +out: + if (cmd) + kfree(cmd); + return count; +} + +DEVICE_ATTR(xiaomi_keyboard_conn_status, (S_IRUGO | S_IWUSR | S_IWGRP), + xiaomi_keyboard_conn_status_show, + xiaomi_keyboard_conn_status_store); + +static irqreturn_t xiaomi_keyboard_irq_func(int irq, void *data) +{ + int value = 0; + MI_KB_INFO("keyboard event: wakeup system\n"); + pm_wakeup_event(&mdata->pdev->dev, 500); + value = gpio_get_value_cansleep(mdata->pdata->in_irq_gpio); + + mutex_lock(&mdata->rw_mutex); + mdata->keyboard_conn_status = !mdata->keyboard_conn_status; + mutex_unlock(&mdata->rw_mutex); + + xiaomi_keyboard_connected_notify(&mdata->pdev->dev); + MI_KB_INFO("keyboard connected status: %d", + mdata->keyboard_conn_status); + return IRQ_HANDLED; +} + +static int xiaomi_keyboard_gpio_config(struct xiaomi_keyboard_platdata *pdata) +{ + int ret = 0; + if (gpio_is_valid(pdata->rst_gpio)) { + ret = gpio_request_one(pdata->rst_gpio, GPIOF_OUT_INIT_LOW, + "kb_rst"); + if (ret) { + MI_KB_ERR( + "Failed to request xiaomi keyboard rst gpio\n"); + goto err_request_rst_gpio; + } + } + + if (gpio_is_valid(pdata->in_irq_gpio)) { + ret = gpio_request_one(pdata->in_irq_gpio, GPIOF_IN, + "kb_in_irq"); + if (ret) { + MI_KB_ERR( + "Failed to request xiaomi keyboard in-irq gpio\n"); + goto err_request_in_irq_gpio; + } + } + + return ret; +err_request_in_irq_gpio: + gpio_free(pdata->rst_gpio); +err_request_rst_gpio: + return ret; +} + +static void +xiaomi_keyboard_gpio_deconfig(struct xiaomi_keyboard_platdata *pdata) +{ + if (gpio_is_valid(pdata->rst_gpio)) + gpio_free(pdata->rst_gpio); + + if (gpio_is_valid(pdata->in_irq_gpio)) + gpio_free(pdata->in_irq_gpio); +} + +static int xiaomi_keyboard_setup_gpio(struct xiaomi_keyboard_platdata *pdata) +{ + int ret = 0; + if (!pdata) { + MI_KB_ERR("xiaomi keyboard platdata is NULL\n"); + return -EINVAL; + } + if (gpio_is_valid(pdata->rst_gpio)) + gpio_direction_output(pdata->rst_gpio, 1); + + mdata->irq = gpio_to_irq(pdata->in_irq_gpio); + if (mdata->irq) { + ret = request_threaded_irq(mdata->irq, NULL, + xiaomi_keyboard_irq_func, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "MiKB-IRQ", mdata); + if (ret != 0) { + MI_KB_ERR("request threaded irq failed\n"); + return ret; + } + } + + return ret; +} + +static int xiaomi_keyboard_resetup_gpio(struct xiaomi_keyboard_platdata *pdata) +{ + int ret = 0; + + if (!mdata || !pdata) { + MI_KB_ERR("mdata or pdata not ready, return!"); + return -EINVAL; + } + + if (gpio_is_valid(pdata->rst_gpio)) + gpio_direction_output(pdata->rst_gpio, 0); + + free_irq(mdata->irq, mdata); + + return ret; +} + +#ifdef CONFIG_OF +static int xiaomi_keyboard_parse_dt(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct xiaomi_keyboard_platdata *pdata; + int ret = 0; + + pdata = mdata->pdata; + + pdata->rst_gpio = of_get_named_gpio_flags( + np, "xiaomi-keyboard,rst-gpio", 0, &pdata->rst_flags); + MI_KB_INFO("xiaomi-kb,reset-gpio=%d\n", pdata->rst_gpio); + + pdata->in_irq_gpio = of_get_named_gpio_flags( + np, "xiaomi-keyboard,in-irq-gpio", 0, &pdata->in_irq_flags); + MI_KB_INFO("xiaomi-kb,in-irq-gpio=%d\n", pdata->in_irq_gpio); + + pdata->vdd_gpio = of_get_named_gpio(np, "xiaomi-keyboard,vdd-gpio", 0); + MI_KB_INFO("xiaomi-kb,vdd-gpio=%d\n", pdata->vdd_gpio); + + return ret; +} +#else +static int xiaomi_keyboard_parse_dt(struct device *dev) +{ + MI_KB_ERR("Xiaomi Keyboard dev is not defined\n"); + return -EINVAL; +} +#endif + +static int xiaomi_keyboard_pinctrl_init(struct device *dev) +{ + int ret = 0; + + mdata->pinctrl = devm_pinctrl_get(dev); + if (IS_ERR_OR_NULL(mdata->pinctrl)) { + MI_KB_ERR("Failed to get pinctrl, please check dts\n"); + ret = PTR_ERR(mdata->pinctrl); + goto err_pinctrl_get; + } + mdata->pins_active = + pinctrl_lookup_state(mdata->pinctrl, "pm_kb_active"); + if (IS_ERR_OR_NULL(mdata->pins_active)) { + MI_KB_ERR("Pin state [active] not found\n"); + ret = PTR_ERR(mdata->pins_active); + goto err_pinctrl_lookup; + } + + mdata->pins_suspend = + pinctrl_lookup_state(mdata->pinctrl, "pm_kb_suspend"); + if (IS_ERR_OR_NULL(mdata->pins_suspend)) { + MI_KB_ERR("Pin state [suspend] not found\n"); + ret = PTR_ERR(mdata->pins_suspend); + goto err_pinctrl_lookup; + } + + return 0; +err_pinctrl_lookup: + if (mdata->pinctrl) { + devm_pinctrl_put(mdata->pinctrl); + } +err_pinctrl_get: + return ret; +} + +static int xiaomi_keyboard_power_on(void) +{ + int ret = 0; + struct xiaomi_keyboard_platdata *pdata; + pdata = mdata->pdata; + MI_KB_INFO("Power On\n"); + if (gpio_is_valid(pdata->vdd_gpio)) { + ret = gpio_request_one(pdata->vdd_gpio, GPIOF_OUT_INIT_HIGH, + "kb_vdd_gpio"); + if (ret) { + MI_KB_ERR( + "Failed to request xiaomi-keyboard-out-irq gpio\n"); + goto err_request_vdd_gpio; + } + } + + gpio_direction_output(pdata->vdd_gpio, 1); +err_request_vdd_gpio: + return ret; +} + +static void xiaomi_keyboard_power_off(void) +{ + struct xiaomi_keyboard_platdata *pdata; + pdata = mdata->pdata; + MI_KB_INFO("Power Off\n"); + if (gpio_is_valid(pdata->vdd_gpio)) { + gpio_direction_output(pdata->vdd_gpio, 0); + gpio_free(pdata->vdd_gpio); + } + return; +} + +static int xiaomi_keyboard_suspend(struct device *dev) +{ + int ret = 0; + MI_KB_INFO("enter\n"); + if (mdata->pinctrl && mdata->pins_suspend) { + ret = (mdata->keyboard_is_enable && mdata->is_usb_exist) ? + 0 : + pinctrl_select_state(mdata->pinctrl, + mdata->pins_suspend); + if (ret < 0) { + MI_KB_ERR("Set suspend pin state error:%d\n", ret); + } + } + MI_KB_INFO("exit\n"); + return ret; +} + +static int xiaomi_keyboard_resume(struct device *dev) +{ + int ret = 0; + MI_KB_INFO("enter\n"); + if (!mdata->keyboard_is_enable) { + MI_KB_INFO("keyboard_is_enable is false, stop resume.\n"); + MI_KB_INFO("exit\n"); + return -1; + } + if (mdata->pinctrl && mdata->pins_active) { + ret = pinctrl_select_state(mdata->pinctrl, mdata->pins_active); + if (ret < 0) { + MI_KB_ERR("Set active pin state error:%d\n", ret); + } + } + MI_KB_INFO("exit\n"); + return ret; +} + +static int xiaomi_keyboard_pm_suspend(struct device *dev) +{ + int ret = 0; + MI_KB_INFO("enter\n"); + enable_irq_wake(mdata->irq); + mdata->dev_pm_suspend = true; + return ret; +} + +static int xiaomi_keyboard_pm_resume(struct device *dev) +{ + int ret = 0; + MI_KB_INFO("enter\n"); + disable_irq_wake(mdata->irq); + mdata->dev_pm_suspend = false; + return ret; +} + +static const struct dev_pm_ops xiaomi_keyboard_pm_ops = { + .suspend = xiaomi_keyboard_pm_suspend, + .resume = xiaomi_keyboard_pm_resume, +}; + +static int keyboard_drm_notifier_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct drm_notify_data *evdata = data; + int *blank; + struct xiaomi_keyboard_data *mdata = + container_of(self, struct xiaomi_keyboard_data, drm_notif); + + if (!evdata) + return 0; + + if (evdata->data && mdata) { + blank = evdata->data; + flush_workqueue(mdata->event_wq); + if (event == DRM_EARLY_EVENT_BLANK) { + if (*blank == DRM_BLANK_POWERDOWN) { + MI_KB_ERR("keyboard suspend"); + mdata->is_in_suspend = true; + queue_work(mdata->event_wq, + &mdata->suspend_work); + } + } else if (event == DRM_EVENT_BLANK) { + if (*blank == DRM_BLANK_UNBLANK) { + MI_KB_ERR("keyboard resume"); + mdata->is_in_suspend = false; + flush_workqueue(mdata->event_wq); + queue_work(mdata->event_wq, + &mdata->resume_work); + } + } + } + + return 0; +} + +static void keyboard_resume_work(struct work_struct *work) +{ + struct xiaomi_keyboard_data *mdata = + container_of(work, struct xiaomi_keyboard_data, resume_work); + xiaomi_keyboard_resume(&mdata->pdev->dev); +} + +static void keyboard_suspend_work(struct work_struct *work) +{ + struct xiaomi_keyboard_data *mdata = + container_of(work, struct xiaomi_keyboard_data, resume_work); + xiaomi_keyboard_suspend(&mdata->pdev->dev); +} + +static int kb_power_supply_event(struct notifier_block *nb, unsigned long event, + void *ptr) +{ + struct xiaomi_keyboard_data *mdata = container_of( + nb, struct xiaomi_keyboard_data, power_supply_notifier); + + if (mdata != NULL) + queue_work(mdata->event_wq, &mdata->power_supply_work); + + return 0; +} + +static void kb_power_supply_work(struct work_struct *work) +{ + struct xiaomi_keyboard_data *mdata = container_of( + work, struct xiaomi_keyboard_data, power_supply_work); + int is_usb_exist = 0; + + mutex_lock(&mdata->power_supply_lock); + is_usb_exist = !!power_supply_is_system_supplied(); + if (is_usb_exist != mdata->is_usb_exist) { + mdata->is_usb_exist = is_usb_exist; + MI_KB_INFO("power supply is: %d", mdata->is_usb_exist); + } + mutex_unlock(&mdata->power_supply_lock); +} + +static void set_keyboard_status(bool on) +{ + int ret = 0; + + if (!mdata || !(mdata->pdata)) { + MI_KB_ERR("mdata or pdata not ready, return!"); + return; + } + + if (on && !(mdata->keyboard_is_enable)) { + ret = xiaomi_keyboard_power_on(); + if (ret) { + MI_KB_ERR("Init 3.3V power failed\n"); + return; + } + msleep(1); + ret = xiaomi_keyboard_setup_gpio(mdata->pdata); + if (ret) { + MI_KB_ERR("setup gpio failed\n"); + return; + } + msleep(2); + + if (!mdata->is_in_suspend) { + ret = pinctrl_select_state(mdata->pinctrl, + mdata->pins_active); + if (ret < 0) { + MI_KB_ERR("Set active pin state error:%d\n", + ret); + } + } + mdata->keyboard_is_enable = true; + + } else if (!on && mdata->keyboard_is_enable) { + if (!mdata->is_in_suspend) { + ret = pinctrl_select_state(mdata->pinctrl, + mdata->pins_suspend); + if (ret < 0) { + MI_KB_ERR("Set suspend pin state error:%d\n", + ret); + } + } + + ret = xiaomi_keyboard_resetup_gpio(mdata->pdata); + if (ret < 0) { + MI_KB_ERR("resetup gpio failed\n"); + return; + } + xiaomi_keyboard_power_off(); + mdata->keyboard_is_enable = false; + } else { + MI_KB_INFO("keyboard status do not need change!"); + } +} + +/******************************************************* +Description: + xiami pad keyboard driver probe function. + +return: + Executive outcomes. 0---succeed. negative---failed +*******************************************************/ +static int xiaomi_keyboard_probe(struct platform_device *pdev) +{ + struct xiaomi_keyboard_platdata *pdata; + int ret = 0; + MI_KB_INFO("enter\n"); + mdata = kzalloc(sizeof(struct xiaomi_keyboard_data), GFP_KERNEL); + if (!mdata) { + MI_KB_ERR("Alloc Memory for xiaomi_keyboard_data failed\n"); + return -ENOMEM; + } + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct xiaomi_keyboard_platdata), + GFP_KERNEL); + if (!pdata) { + MI_KB_ERR("Alloc Memory for xiaomi_keyboard_platdata failed\n"); + return -ENOMEM; + } + + mdata->pdev = pdev; + mdata->pdata = pdata; + mutex_init(&mdata->rw_mutex); + mutex_init(&mdata->power_supply_lock); + mdata->is_usb_exist = 0; + + ret = xiaomi_keyboard_parse_dt(&pdev->dev); + if (ret) { + MI_KB_ERR("parse device tree failed\n"); + goto out; + } + + ret = xiaomi_keyboard_pinctrl_init(&pdev->dev); + if (ret) { + MI_KB_ERR("Pinctrl init failed\n"); + goto out; + } + + pdata = mdata->pdata; + ret = xiaomi_keyboard_gpio_config(pdata); + if (ret) { + MI_KB_ERR("set gpio config failed\n"); + goto out; + } + + mdata->dev_pm_suspend = false; + mdata->keyboard_is_enable = false; + mdata->is_in_suspend = false; + + ret = sysfs_create_file(&mdata->pdev->dev.kobj, + &dev_attr_xiaomi_keyboard_conn_status.attr); + if (ret < 0) { + MI_KB_ERR( + "Create sysfs attribute xiaomi_keyboard_conn_status Failed\n"); + goto err_pinctrl_select; + } + + mdata->event_wq = + alloc_workqueue("kb-event-queue", + WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!mdata->event_wq) { + MI_KB_ERR("Can not create work thread for suspend/resume!!"); + ret = -ENOMEM; + goto err_alloc_work_thread_failed; + } + INIT_WORK(&mdata->resume_work, keyboard_resume_work); + INIT_WORK(&mdata->suspend_work, keyboard_suspend_work); + INIT_WORK(&mdata->power_supply_work, kb_power_supply_work); + + mdata->drm_notif.notifier_call = keyboard_drm_notifier_callback; + ret = drm_register_client(&mdata->drm_notif); + if (ret) { + MI_KB_ERR("register drm_notifier failed. ret=%d\n", ret); + goto err_register_drm_notif_failed; + } + + mdata->power_supply_notifier.notifier_call = kb_power_supply_event; + ret = power_supply_reg_notifier(&mdata->power_supply_notifier); + if (ret) { + MI_KB_ERR("register power_supply_notifier failed. ret=%d\n", + ret); + goto err_register_power_supply_notif_failed; + } + + MI_KB_INFO("Success\n"); + return ret; + +err_register_power_supply_notif_failed: +err_register_drm_notif_failed: + if (drm_unregister_client(&mdata->drm_notif)) + MI_KB_ERR("Error occurred while unregistering drm_notifier\n"); + if (mdata->event_wq) { + destroy_workqueue(mdata->event_wq); + } +err_alloc_work_thread_failed: + sysfs_remove_file(&mdata->pdev->dev.kobj, + &dev_attr_xiaomi_keyboard_conn_status.attr); +err_pinctrl_select: + if (mdata->pinctrl) { + devm_pinctrl_put(mdata->pinctrl); + } + xiaomi_keyboard_gpio_deconfig(pdata); +out: + mutex_destroy(&mdata->rw_mutex); + mutex_destroy(&mdata->power_supply_lock); + if (mdata) { + kfree(mdata); + mdata = NULL; + } + MI_KB_ERR("Failed\n"); + return ret; +} + +static int xiaomi_keyboard_remove(struct platform_device *pdev) +{ + MI_KB_INFO("enter\n"); + drm_unregister_client(&mdata->drm_notif); + destroy_workqueue(mdata->event_wq); + xiaomi_keyboard_gpio_deconfig(mdata->pdata); + sysfs_remove_file(&mdata->pdev->dev.kobj, + &dev_attr_xiaomi_keyboard_conn_status.attr); + xiaomi_keyboard_power_off(); + devm_pinctrl_put(mdata->pinctrl); + xiaomi_keyboard_gpio_deconfig(mdata->pdata); + mutex_destroy(&mdata->rw_mutex); + mutex_destroy(&mdata->power_supply_lock); + if (mdata) { + kfree(mdata); + mdata = NULL; + } + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id xiaomi_keyboard_dt_match[] = { + { .compatible = "xiaomi,keyboard" }, + {}, +}; +MODULE_DEVICE_TABLE(of, xiaomi_keyboard_dt_match); +#endif + +static const struct platform_device_id xiaomi_keyboard_driver_ids[] = { + { + .name = "xiaomi-keyboard", + .driver_data = 0, + }, +}; +MODULE_DEVICE_TABLE(platform, xiaomi_keyboard_driver_ids); + +static struct platform_driver xiaomi_keyboard_driver = { + .probe = xiaomi_keyboard_probe, + .remove = xiaomi_keyboard_remove, + .driver = { + .name = "xiaomi-keyboard", + .of_match_table = of_match_ptr(xiaomi_keyboard_dt_match), + .pm = &xiaomi_keyboard_pm_ops, + }, + .id_table = xiaomi_keyboard_driver_ids, +}; + +module_platform_driver(xiaomi_keyboard_driver); + +MODULE_DESCRIPTION("Xiaomi Keyboard Control-driver"); +MODULE_AUTHOR("Tonghui Wang"); diff --git a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h new file mode 100644 index 000000000000..32bb8c0dcbd4 --- /dev/null +++ b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h @@ -0,0 +1,47 @@ +#ifndef __XIAOMI_KEYBOARD_H +#define __XIAOMI_KEYBOARD_H + +#include +#include +#include +#include +#include +#include + +#define XIAOMI_KB_TAG "xiaomi-keyboard" +#define MI_KB_INFO(fmt, args...) \ + pr_info("[%s] %s %d: " fmt, XIAOMI_KB_TAG, __func__, __LINE__, ##args) +#define MI_KB_ERR(fmt, args...) \ + pr_err("[%s] %s %d: " fmt, XIAOMI_KB_TAG, __func__, __LINE__, ##args) + +struct xiaomi_keyboard_platdata { + u32 rst_gpio; + u32 rst_flags; + u32 in_irq_gpio; + u32 in_irq_flags; + u32 vdd_gpio; +}; + +struct xiaomi_keyboard_data { + struct notifier_block drm_notif; + struct xiaomi_keyboard_platdata *pdata; + bool dev_pm_suspend; + int irq; + struct platform_device *pdev; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_active; + struct pinctrl_state *pins_suspend; + struct workqueue_struct *event_wq; + struct work_struct resume_work; + struct work_struct suspend_work; + int keyboard_conn_status; + struct mutex rw_mutex; + + struct mutex power_supply_lock; + struct work_struct power_supply_work; + struct notifier_block power_supply_notifier; + int is_usb_exist; + bool keyboard_is_enable; + bool is_in_suspend; +}; +#endif From 7f42117985aa0fa6359f2b397b6319b781cc5fbe Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 16 Apr 2024 02:49:02 +0200 Subject: [PATCH 053/226] drivers: input: misc: xiaomi_keyboard: Use MSM DRM notifier Change-Id: I783972b91a22247f4bfafd955fd42383003952f9 Signed-off-by: firebird11 --- .../misc/xiaomi_keyboard/xiaomi_keyboard.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c index 962771069660..98d41b8eaeb2 100644 --- a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c +++ b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c @@ -13,7 +13,7 @@ #include #include #include "xiaomi_keyboard.h" -#include +#include #include static struct xiaomi_keyboard_data *mdata; @@ -351,7 +351,7 @@ static const struct dev_pm_ops xiaomi_keyboard_pm_ops = { static int keyboard_drm_notifier_callback(struct notifier_block *self, unsigned long event, void *data) { - struct drm_notify_data *evdata = data; + struct msm_drm_notifier *evdata = data; int *blank; struct xiaomi_keyboard_data *mdata = container_of(self, struct xiaomi_keyboard_data, drm_notif); @@ -362,15 +362,15 @@ static int keyboard_drm_notifier_callback(struct notifier_block *self, if (evdata->data && mdata) { blank = evdata->data; flush_workqueue(mdata->event_wq); - if (event == DRM_EARLY_EVENT_BLANK) { - if (*blank == DRM_BLANK_POWERDOWN) { + if (event == MSM_DRM_EARLY_EVENT_BLANK) { + if (*blank == MSM_DRM_BLANK_POWERDOWN) { MI_KB_ERR("keyboard suspend"); mdata->is_in_suspend = true; queue_work(mdata->event_wq, &mdata->suspend_work); } - } else if (event == DRM_EVENT_BLANK) { - if (*blank == DRM_BLANK_UNBLANK) { + } else if (event == MSM_DRM_EVENT_BLANK) { + if (*blank == MSM_DRM_BLANK_UNBLANK) { MI_KB_ERR("keyboard resume"); mdata->is_in_suspend = false; flush_workqueue(mdata->event_wq); @@ -555,7 +555,7 @@ static int xiaomi_keyboard_probe(struct platform_device *pdev) INIT_WORK(&mdata->power_supply_work, kb_power_supply_work); mdata->drm_notif.notifier_call = keyboard_drm_notifier_callback; - ret = drm_register_client(&mdata->drm_notif); + ret = msm_drm_register_client(&mdata->drm_notif); if (ret) { MI_KB_ERR("register drm_notifier failed. ret=%d\n", ret); goto err_register_drm_notif_failed; @@ -574,7 +574,7 @@ static int xiaomi_keyboard_probe(struct platform_device *pdev) err_register_power_supply_notif_failed: err_register_drm_notif_failed: - if (drm_unregister_client(&mdata->drm_notif)) + if (msm_drm_unregister_client(&mdata->drm_notif)) MI_KB_ERR("Error occurred while unregistering drm_notifier\n"); if (mdata->event_wq) { destroy_workqueue(mdata->event_wq); @@ -601,7 +601,7 @@ static int xiaomi_keyboard_probe(struct platform_device *pdev) static int xiaomi_keyboard_remove(struct platform_device *pdev) { MI_KB_INFO("enter\n"); - drm_unregister_client(&mdata->drm_notif); + msm_drm_unregister_client(&mdata->drm_notif); destroy_workqueue(mdata->event_wq); xiaomi_keyboard_gpio_deconfig(mdata->pdata); sysfs_remove_file(&mdata->pdev->dev.kobj, From 36a73a61c9cd1ac5c2e32930d4d14aa5bb1d9981 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 11 Oct 2023 15:20:08 +0200 Subject: [PATCH 054/226] firmware: Add FIRMWARE_IN_KERNEL support Change-Id: Id78f5b6bbb4c42fab30abfef2c78354d7f50c46a Signed-off-by: firebird11 --- firmware/Makefile | 61 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 2 deletions(-) diff --git a/firmware/Makefile b/firmware/Makefile index 30e6b738839e..96b4a8b0a63b 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -10,6 +10,28 @@ fwabs := $(addprefix $(srctree)/,$(filter-out /%,$(fwdir)))$(filter /%,$(fwdir)) fw-external-y := $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE)) +# There are three cases to care about: +# 1. Building kernel with CONFIG_FIRMWARE_IN_KERNEL=y -- $(fw-shipped-y) should +# include the firmware files to include, according to .config +# 2. 'make modules_install', which will install firmware for modules, and +# _also_ for the in-kernel drivers when CONFIG_FIRMWARE_IN_KERNEL=n +# 3. 'make firmware_install', which installs all firmware, unconditionally. + +# For the former two cases we want $(fw-shipped-y) and $(fw-shipped-m) to be +# accurate. In the latter case it doesn't matter -- it'll use $(fw-shipped-all). +# But be aware that the config file might not be included at all. + +fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) + +quiet_cmd_ihex = IHEX $@ + cmd_ihex = $(OBJCOPY) -Iihex -Obinary $< $@ + +quiet_cmd_ihex2fw = IHEX2FW $@ + cmd_ihex2fw = $(objtree)/$(obj)/ihex2fw $< $@ + +quiet_cmd_h16tofw = H16TOFW $@ + cmd_h16tofw = $(objtree)/$(obj)/ihex2fw -w $< $@ + quiet_cmd_fwbin = MK_FW $@ cmd_fwbin = FWNAME="$(patsubst firmware/%.gen.S,%,$@)"; \ FWSTR="$(subst /,_,$(subst .,_,$(subst -,_,$(patsubst \ @@ -42,14 +64,46 @@ wordsize_deps := $(wildcard include/config/64bit.h include/config/32bit.h \ include/config/x86_32.h include/config/x86_64.h \ firmware/Makefile) +$(patsubst %,$(obj)/%.gen.S, $(fw-shipped-y)): %: $(wordsize_deps) + $(call cmd,fwbin,$(patsubst %.gen.S,%,$@)) $(patsubst %,$(obj)/%.gen.S, $(fw-external-y)): %: $(wordsize_deps) \ include/config/extra/firmware/dir.h $(call cmd,fwbin,$(fwabs)/$(patsubst $(obj)/%.gen.S,%,$@)) # The .o files depend on the binaries directly; the .S files don't. +$(patsubst %,$(obj)/%.gen.o, $(fw-shipped-y)): %.gen.o: % $(patsubst %,$(obj)/%.gen.o, $(fw-external-y)): $(obj)/%.gen.o: $(fwdir)/% +# .ihex is used just as a simple way to hold binary files in a source tree +# where binaries are frowned upon. They are directly converted with objcopy. +$(obj)/%: $(obj)/%.ihex + $(call cmd,ihex) + +# Don't depend on ihex2fw if we're installing and it already exists. +# Putting it after | in the dependencies doesn't seem sufficient when +# we're installing after a cross-compile, because ihex2fw has dependencies +# on stuff like /usr/lib/gcc/ppc64-redhat-linux/4.3.0/include/stddef.h and +# thus wants to be rebuilt. Which it can't be, if the prebuilt kernel tree +# is exported read-only for someone to run 'make install'. +ifeq ($(INSTALL):$(wildcard $(obj)/ihex2fw),install:$(obj)/ihex2fw) +ihex2fw_dep := +else +ihex2fw_dep := $(obj)/ihex2fw +endif + +# .HEX is also Intel HEX, but where the offset and length in each record +# is actually meaningful, because the firmware has to be loaded in a certain +# order rather than as a single binary blob. Thus, we convert them into our +# more compact binary representation of ihex records () +$(obj)/%.fw: $(obj)/%.HEX $(ihex2fw_dep) + $(call cmd,ihex2fw) + +# .H16 is our own modified form of Intel HEX, with 16-bit length for records. +$(obj)/%.fw: $(obj)/%.H16 $(ihex2fw_dep) + $(call cmd,h16tofw) + obj-y += $(patsubst %,%.gen.o, $(fw-external-y)) +obj-$(CONFIG_FIRMWARE_IN_KERNEL) += $(patsubst %,%.gen.o, $(fw-shipped-y)) ifeq ($(KBUILD_SRC),) # Makefile.build only creates subdirectories for O= builds, but external @@ -57,8 +111,11 @@ ifeq ($(KBUILD_SRC),) _dummy := $(foreach d,$(addprefix $(obj)/,$(dir $(fw-external-y))), $(shell [ -d $(d) ] || mkdir -p $(d))) endif -targets := $(patsubst $(obj)/%,%, \ - $(shell find $(obj) -name \*.gen.S 2>/dev/null)) +# Remove .S files and binaries created from ihex +# (during 'make clean' .config isn't included so they're all in $(fw-shipped-)) +targets := $(fw-shipped-) $(patsubst $(obj)/%,%, \ + $(shell find $(obj) -name \*.gen.S 2>/dev/null)) + # Without this, built-in.o won't be created when it's empty, and the # final vmlinux link will fail. obj- := dummy From 5fe7f8e8863777cad651c5f33e4a6de5f560b873 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 11:29:49 +0100 Subject: [PATCH 055/226] drivers: input: touchscreen: Import Xiaomi drivers * fts_521 (andromeda, cepheus, crux) - from cepheus-q-oss * goodix_driver_gt9886 (raphael) - from cepheus-q-oss * nt36523 (nabu): From nabu-r-oss * nt36672c (vayu): From vayu-r-oss * Run clang-format on source files Change-Id: Ie9a3a9c4058b9ccd5c1fa3edb66e0860658a35f0 Signed-off-by: firebird11 --- drivers/input/touchscreen/Kconfig | 2 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/xiaomi/Kconfig | 23 + drivers/input/touchscreen/xiaomi/Makefile | 6 + .../input/touchscreen/xiaomi/fts_521/Kconfig | 25 + .../input/touchscreen/xiaomi/fts_521/Makefile | 6 + .../input/touchscreen/xiaomi/fts_521/fts.c | 7514 ++++++++++ .../input/touchscreen/xiaomi/fts_521/fts.h | 397 + .../input/touchscreen/xiaomi/fts_521/fts_fw.h | 8387 +++++++++++ .../xiaomi/fts_521/fts_lib/Makefile | 7 + .../xiaomi/fts_521/fts_lib/ftsCompensation.c | 764 + .../xiaomi/fts_521/fts_lib/ftsCompensation.h | 110 + .../xiaomi/fts_521/fts_lib/ftsCore.c | 1377 ++ .../xiaomi/fts_521/fts_lib/ftsCore.h | 187 + .../xiaomi/fts_521/fts_lib/ftsError.c | 360 + .../xiaomi/fts_521/fts_lib/ftsError.h | 181 + .../xiaomi/fts_521/fts_lib/ftsFlash.c | 1058 ++ .../xiaomi/fts_521/fts_lib/ftsFlash.h | 106 + .../xiaomi/fts_521/fts_lib/ftsFrame.c | 395 + .../xiaomi/fts_521/fts_lib/ftsFrame.h | 92 + .../xiaomi/fts_521/fts_lib/ftsGesture.c | 363 + .../xiaomi/fts_521/fts_lib/ftsGesture.h | 38 + .../xiaomi/fts_521/fts_lib/ftsHardware.h | 217 + .../xiaomi/fts_521/fts_lib/ftsIO.c | 911 ++ .../xiaomi/fts_521/fts_lib/ftsIO.h | 61 + .../xiaomi/fts_521/fts_lib/ftsSoftware.h | 400 + .../xiaomi/fts_521/fts_lib/ftsTest.c | 6342 ++++++++ .../xiaomi/fts_521/fts_lib/ftsTest.h | 304 + .../xiaomi/fts_521/fts_lib/ftsTime.c | 78 + .../xiaomi/fts_521/fts_lib/ftsTime.h | 63 + .../xiaomi/fts_521/fts_lib/ftsTool.c | 639 + .../xiaomi/fts_521/fts_lib/ftsTool.h | 56 + .../touchscreen/xiaomi/fts_521/fts_limits.h | 1412 ++ .../touchscreen/xiaomi/fts_521/fts_proc.c | 2421 +++ .../xiaomi/goodix_driver_gt9886/Kconfig | 45 + .../xiaomi/goodix_driver_gt9886/Makefile | 7 + .../goodix_driver_gt9886/goodix_cfg_bin.c | 674 + .../goodix_driver_gt9886/goodix_cfg_bin.h | 108 + .../goodix_driver_gt9886/goodix_default_fw.h | 6 + .../goodix_driver_gt9886/goodix_gtx8_update.c | 1397 ++ .../goodix_driver_gt9886/goodix_ts_core.c | 2910 ++++ .../goodix_driver_gt9886/goodix_ts_core.h | 788 + .../goodix_driver_gt9886/goodix_ts_gesture.c | 756 + .../goodix_driver_gt9886/goodix_ts_i2c.c | 2230 +++ .../goodix_driver_gt9886/goodix_ts_tools.c | 722 + .../goodix_driver_gt9886/test_core/Makefile | 40 + .../test_core/board_opr_interface.h | 123 + .../test_core/board_opr_interface_kernel.c | 691 + .../goodix_driver_gt9886/test_core/chip_ini.h | 70 + .../goodix_driver_gt9886/test_core/config.h | 81 + .../test_core/crc_decrypt.c | 205 + .../test_core/crc_decrypt.h | 32 + .../test_core/custom_info_def.h | 30 + .../test_core/extra_tp_control.c | 108 + .../test_core/extra_tp_control.h | 26 + .../test_core/generic_func.c | 250 + .../test_core/generic_func.h | 65 + .../test_core/memory_override.c | 126 + .../test_core/mxml-attr.c | 251 + .../test_core/mxml-entity.c | 246 + .../test_core/mxml-file.c | 1626 ++ .../goodix_driver_gt9886/test_core/mxml-get.c | 287 + .../test_core/mxml-index.c | 358 + .../test_core/mxml-node.c | 551 + .../test_core/mxml-private.c | 267 + .../test_core/mxml-private.h | 41 + .../test_core/mxml-search.c | 196 + .../goodix_driver_gt9886/test_core/mxml-set.c | 238 + .../test_core/mxml-string.c | 393 + .../goodix_driver_gt9886/test_core/mxml.h | 317 + .../test_core/normandy_short_test.c | 900 ++ .../test_core/normandy_short_test.h | 56 + .../test_core/public_fun.c | 59 + .../test_core/public_fun.h | 28 + .../goodix_driver_gt9886/test_core/res_inc.h | 167 + .../test_core/save_test_data.c | 355 + .../test_core/save_test_data.h | 43 + .../test_core/simple_mem_manager.h | 33 + .../test_core/simple_mem_manager_mach.c | 105 + .../goodix_driver_gt9886/test_core/strtol.c | 58 + .../test_core/test_item_def.h | 180 + .../test_core/test_item_init.c | 705 + .../test_core/test_item_init.h | 63 + .../test_core/test_order.c | 2531 ++++ .../test_core/test_order.h | 142 + .../test_core/test_param_init.c | 624 + .../test_core/test_param_init.h | 43 + .../test_core/test_proc.c | 260 + .../test_core/test_proc.h | 41 + .../test_core/tp_additional_option.c | 392 + .../test_core/tp_additional_option.h | 186 + .../test_core/tp_additional_option_param.h | 86 + .../test_core/tp_board_flash_alloc.h | 32 + .../test_core/tp_dev_control.c | 568 + .../test_core/tp_dev_control.h | 86 + .../test_core/tp_dev_def.h | 176 + .../test_core/tp_item_permutation.c | 123 + .../test_core/tp_item_permutation.h | 27 + .../test_core/tp_micro_def.h | 64 + .../test_core/tp_normandy_control.c | 692 + .../test_core/tp_normandy_control.h | 52 + .../test_core/tp_open_test.c | 2196 +++ .../test_core/tp_open_test.h | 227 + .../test_core/tp_open_test_param.h | 132 + .../test_core/tp_product_id_def.h | 66 + .../test_core/tp_short_test.c | 460 + .../test_core/tp_short_test.h | 79 + .../test_core/tp_short_test_param.h | 56 + .../tp_test_general_error_code_def.h | 35 + .../test_core/tp_test_item_buf_mem.c | 216 + .../test_core/tp_test_item_buf_mem.h | 22 + .../test_core/tp_test_item_id.h | 86 + .../test_core/tp_test_item_mem.c | 932 ++ .../test_core/tp_test_item_mem.h | 42 + .../test_core/tp_version_test.c | 267 + .../test_core/tp_version_test.h | 57 + .../test_core/tp_version_test_param.h | 51 + .../test_core/user_test_type_def.h | 143 + drivers/input/touchscreen/xiaomi/ndt_core.c | 1380 ++ drivers/input/touchscreen/xiaomi/ndt_core.h | 3 + .../input/touchscreen/xiaomi/nt36523/Kconfig | 11 + .../input/touchscreen/xiaomi/nt36523/Makefile | 9 + .../touchscreen/xiaomi/nt36523/nt36xxx.c | 3992 +++++ .../touchscreen/xiaomi/nt36523/nt36xxx.h | 292 + .../xiaomi/nt36523/nt36xxx_ext_proc.c | 2639 ++++ .../xiaomi/nt36523/nt36xxx_fw_update.c | 1110 ++ .../xiaomi/nt36523/nt36xxx_mem_map.h | 442 + .../xiaomi/nt36523/nt36xxx_mp_ctrlram.c | 4254 ++++++ .../xiaomi/nt36523/nt36xxx_mp_ctrlram.h | 1678 +++ .../input/touchscreen/xiaomi/nt36672c/Kconfig | 15 + .../touchscreen/xiaomi/nt36672c/Makefile | 7 + .../touchscreen/xiaomi/nt36672c/nt36xxx.c | 3347 +++++ .../touchscreen/xiaomi/nt36672c/nt36xxx.h | 269 + .../xiaomi/nt36672c/nt36xxx_ext_proc.c | 737 + .../xiaomi/nt36672c/nt36xxx_fw_update.c | 1184 ++ .../xiaomi/nt36672c/nt36xxx_mem_map.h | 358 + .../xiaomi/nt36672c/nt36xxx_mp_ctrlram.c | 2610 ++++ .../xiaomi/nt36672c/nt36xxx_mp_ctrlram.h | 87 + .../xiaomi/nt36672c/nt36xxx_mp_ctrlram_data.c | 536 + .../input/touchscreen/xiaomi/spi-xiaomi-tp.c | 196 + .../input/touchscreen/xiaomi/spi-xiaomi-tp.h | 52 + firmware/Makefile | 12 + firmware/goodix_gt9886_cfg_f11.bin.ihex | 116 + firmware/goodix_gt9886_fw_f11.bin.ihex | 5522 +++++++ firmware/j20s_novatek_ts_fw01.bin.ihex | 8707 +++++++++++ firmware/j20s_novatek_ts_fw02.bin.ihex | 8707 +++++++++++ firmware/j20s_novatek_ts_mp01.bin.ihex | 8707 +++++++++++ firmware/j20s_novatek_ts_mp02.bin.ihex | 8707 +++++++++++ firmware/ndt_fw.bin.ihex | 1249 ++ firmware/novatek_nt36523_fw01.bin.ihex | 12291 ++++++++++++++++ firmware/novatek_nt36523_fw02.bin.ihex | 12291 ++++++++++++++++ firmware/novatek_nt36523_mp01.bin.ihex | 12291 ++++++++++++++++ firmware/novatek_nt36523_mp02.bin.ihex | 12291 ++++++++++++++++ firmware/novatek_nt36672_f10.fw.ihex | 7426 ++++++++++ firmware/novatek_ts_fw.bin.ihex | 12291 ++++++++++++++++ firmware/novatek_ts_mp.bin.ihex | 12291 ++++++++++++++++ firmware/st_fts.ftb.ihex | 6813 +++++++++ firmware/st_fts_e5.ftb.ihex | 6799 +++++++++ firmware/st_fts_f1.ftb.ihex | 6816 +++++++++ firmware/st_fts_f1x.ftb.ihex | 6360 ++++++++ firmware/st_fts_j2a.ftb.ihex | 7136 +++++++++ firmware/st_fts_j2a_csot.ftb.ihex | 6948 +++++++++ firmware/st_fts_j2a_sdc.ftb.ihex | 7136 +++++++++ include/uapi/linux/input-event-codes.h | 1 + 164 files changed, 260624 insertions(+) create mode 100644 drivers/input/touchscreen/xiaomi/Kconfig create mode 100644 drivers/input/touchscreen/xiaomi/Makefile create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/Kconfig create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/Makefile create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_fw.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/Makefile create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsHardware.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsSoftware.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.c create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_limits.h create mode 100644 drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Kconfig create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Makefile create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_default_fw.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_gtx8_update.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_gesture.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_i2c.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_tools.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/Makefile create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface_kernel.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/chip_ini.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/config.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/custom_info_def.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/memory_override.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-attr.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-entity.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-file.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-get.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-index.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-node.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-search.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-set.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-string.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/res_inc.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager_mach.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/strtol.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_def.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option_param.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_board_flash_alloc.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_def.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_micro_def.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test_param.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_product_id_def.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test_param.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_general_error_code_def.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_id.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.c create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test_param.h create mode 100644 drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/user_test_type_def.h create mode 100644 drivers/input/touchscreen/xiaomi/ndt_core.c create mode 100644 drivers/input/touchscreen/xiaomi/ndt_core.h create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/Kconfig create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/Makefile create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_ext_proc.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_fw_update.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mem_map.h create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.h create mode 100755 drivers/input/touchscreen/xiaomi/nt36672c/Kconfig create mode 100755 drivers/input/touchscreen/xiaomi/nt36672c/Makefile create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.h create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_ext_proc.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_fw_update.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mem_map.h create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.c create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.h create mode 100644 drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram_data.c create mode 100644 drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.c create mode 100644 drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.h create mode 100755 firmware/goodix_gt9886_cfg_f11.bin.ihex create mode 100755 firmware/goodix_gt9886_fw_f11.bin.ihex create mode 100644 firmware/j20s_novatek_ts_fw01.bin.ihex create mode 100644 firmware/j20s_novatek_ts_fw02.bin.ihex create mode 100644 firmware/j20s_novatek_ts_mp01.bin.ihex create mode 100644 firmware/j20s_novatek_ts_mp02.bin.ihex create mode 100644 firmware/ndt_fw.bin.ihex create mode 100644 firmware/novatek_nt36523_fw01.bin.ihex create mode 100644 firmware/novatek_nt36523_fw02.bin.ihex create mode 100644 firmware/novatek_nt36523_mp01.bin.ihex create mode 100644 firmware/novatek_nt36523_mp02.bin.ihex create mode 100755 firmware/novatek_nt36672_f10.fw.ihex create mode 100644 firmware/novatek_ts_fw.bin.ihex create mode 100644 firmware/novatek_ts_mp.bin.ihex create mode 100644 firmware/st_fts.ftb.ihex create mode 100644 firmware/st_fts_e5.ftb.ihex create mode 100644 firmware/st_fts_f1.ftb.ihex create mode 100644 firmware/st_fts_f1x.ftb.ihex create mode 100644 firmware/st_fts_j2a.ftb.ihex create mode 100644 firmware/st_fts_j2a_csot.ftb.ihex create mode 100644 firmware/st_fts_j2a_sdc.ftb.ihex diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 4397e53e3cb4..7f85cd5deb14 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -1298,4 +1298,6 @@ config TOUCHSCREEN_RAYDIUM_CHIPSET source "drivers/input/touchscreen/focaltech_touch/Kconfig" +source "drivers/input/touchscreen/xiaomi/Kconfig" + endif diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 49ade9793bbe..17aa95412a5e 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -112,3 +112,4 @@ obj-$(CONFIG_TOUCHSCREEN_RASPBERRYPI_FW) += raspberrypi-ts.o obj-$(CONFIG_TOUCHSCREEN_IQS5XX) += iqs5xx.o obj-$(CONFIG_TOUCHSCREEN_ST) += st/ obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_touch/ +obj-y += xiaomi/ diff --git a/drivers/input/touchscreen/xiaomi/Kconfig b/drivers/input/touchscreen/xiaomi/Kconfig new file mode 100644 index 000000000000..20680df186d4 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/Kconfig @@ -0,0 +1,23 @@ +source "drivers/input/touchscreen/xiaomi/fts_521/Kconfig" +source "drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Kconfig" +source "drivers/input/touchscreen/xiaomi/nt36523/Kconfig" +source "drivers/input/touchscreen/xiaomi/nt36672c/Kconfig" + +config I2C_BY_DMA + bool "I2C BY DMA" + +config SECURE_TOUCH + bool "Secure Touch" + +config INPUT_PRESS_NDT + bool "ndt" + depends on I2C + help + Say Y here if you have a press ic ndt. + +config SPI_XIAOMI_TP + bool + depends on SPI + default y if TOUCHSCREEN_NT36xxx_HOSTDL_SPI + help + Say Y if want use xiaomi touch panel. diff --git a/drivers/input/touchscreen/xiaomi/Makefile b/drivers/input/touchscreen/xiaomi/Makefile new file mode 100644 index 000000000000..1e07625331f5 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/Makefile @@ -0,0 +1,6 @@ +obj-$(CONFIG_TOUCHSCREEN_ST_FTS_V521) += fts_521/ +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8) += goodix_driver_gt9886/ +obj-$(CONFIG_TOUCHSCREEN_NT36523_HOSTDL_SPI) += nt36523/ +obj-$(CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI) += nt36672c/ +obj-$(CONFIG_INPUT_PRESS_NDT) += ndt_core.o +obj-$(CONFIG_SPI_XIAOMI_TP) += spi-xiaomi-tp.o diff --git a/drivers/input/touchscreen/xiaomi/fts_521/Kconfig b/drivers/input/touchscreen/xiaomi/fts_521/Kconfig new file mode 100644 index 000000000000..d074d4b66c4e --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/Kconfig @@ -0,0 +1,25 @@ +config TOUCHSCREEN_ST_FTS_V521 + tristate "ST FTS V521 I2C Touchscreen" + depends on I2C + help + Say Y here if you have ST FTS series I2C touchscreen. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + +config FTS_FOD_AREA_REPORT + tristate "FTS FOD area report" + depends on TOUCHSCREEN_ST_FTS_V521 + help + Say Y here to enable fod area report functionality. + + If unsure, say N. + +config TOUCHSCREEN_ST_DEBUG_FS + tristate "St core driver module" + depends on TOUCHSCREEN_ST_FTS_V521 + help + Say Y here to enable touch debugfs functionality. + + If unsure, say N. diff --git a/drivers/input/touchscreen/xiaomi/fts_521/Makefile b/drivers/input/touchscreen/xiaomi/fts_521/Makefile new file mode 100644 index 000000000000..cf21f2190fcc --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the touchscreen drivers. +# + +obj-$(CONFIG_TOUCHSCREEN_ST_FTS_V521) += fts.o fts_proc.o fts_lib/ + diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c new file mode 100644 index 000000000000..e03e326c2241 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -0,0 +1,7514 @@ +/* + * fts.c + * + * FTS Capacitive touch screen controller (FingerTipS) + * + * Copyright (C) 2016, STMicroelectronics Limited. + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: AMG(Analog Mems Group) + * + * marco.cali@st.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THE PRESENT SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES + * OR CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED, FOR THE SOLE + * PURPOSE TO SUPPORT YOUR APPLICATION DEVELOPMENT. + * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE + * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING + * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * THIS SOFTWARE IS SPECIFICALLY DESIGNED FOR EXCLUSIVE USE WITH ST PARTS. + */ + +/*! +* \file fts.c +* \brief It is the main file which contains all the most important functions generally used by a device driver the driver +*/ +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SECURE_TOUCH +#include +#include +#include +#endif + +#include +#include +#include + +#include +#ifdef CONFIG_DRM +#include +#endif +#include + +#include +#include +#include +#include + +#ifdef KERNEL_ABOVE_2_6_38 +#include +#endif +#include "../xiaomi/xiaomi_touch.h" +#include "fts.h" +#include "fts_lib/ftsCompensation.h" +#include "fts_lib/ftsCore.h" +#include "fts_lib/ftsIO.h" +#include "fts_lib/ftsError.h" +#include "fts_lib/ftsFlash.h" +#include "fts_lib/ftsFrame.h" +#include "fts_lib/ftsGesture.h" +#include "fts_lib/ftsTest.h" +#include "fts_lib/ftsTime.h" +#include "fts_lib/ftsTool.h" + +/** + * Event handler installer helpers + */ +#define event_id(_e) (EVT_ID_##_e >> 4) +#define handler_name(_h) fts_##_h##_event_handler + +#define install_handler(_i, _evt, _hnd) \ + do { \ + _i->event_dispatch_table[event_id(_evt)] = handler_name(_hnd); \ + } while (0) + +#ifdef KERNEL_ABOVE_2_6_38 +#define TYPE_B_PROTOCOL +#endif + +#define INPUT_EVENT_START 0 +#define INPUT_EVENT_SENSITIVE_MODE_OFF 0 +#define INPUT_EVENT_SENSITIVE_MODE_ON 1 +#define INPUT_EVENT_STYLUS_MODE_OFF 2 +#define INPUT_EVENT_STYLUS_MODE_ON 3 +#define INPUT_EVENT_WAKUP_MODE_OFF 4 +#define INPUT_EVENT_WAKUP_MODE_ON 5 +#define INPUT_EVENT_COVER_MODE_OFF 6 +#define INPUT_EVENT_COVER_MODE_ON 7 +#define INPUT_EVENT_SLIDE_FOR_VOLUME 8 +#define INPUT_EVENT_DOUBLE_TAP_FOR_VOLUME 9 +#define INPUT_EVENT_SINGLE_TAP_FOR_VOLUME 10 +#define INPUT_EVENT_LONG_SINGLE_TAP_FOR_VOLUME 11 +#define INPUT_EVENT_PALM_OFF 12 +#define INPUT_EVENT_PALM_ON 13 +#define INPUT_EVENT_END 13 + +extern SysInfo systemInfo; +extern TestToDo tests; +#ifdef GESTURE_MODE +extern struct mutex gestureMask_mutex; +#endif + +char tag[8] = "[ FTS ]\0"; +/* buffer which store the input device name assigned by the kernel */ +char fts_ts_phys[64]; +/* buffer used to store the command sent from the MP device file node */ +static u32 typeOfComand[CMD_STR_LEN] = { 0 }; + +/* number of parameter passed through the MP device file node */ +static int numberParameters; +#ifdef USE_ONE_FILE_NODE +static int feature_feasibility = ERROR_OP_NOT_ALLOW; +#endif +#ifdef GESTURE_MODE +static u8 mask[GESTURE_MASK_SIZE + 2]; +extern u16 gesture_coordinates_x[GESTURE_MAX_COORDS_PAIRS_REPORT]; +extern u16 gesture_coordinates_y[GESTURE_MAX_COORDS_PAIRS_REPORT]; +extern int gesture_coords_reported; +extern struct mutex gestureMask_mutex; +#endif +/* store the last update of the key mask published by the IC */ +#ifdef PHONE_KEY +static u8 key_mask; +#endif + +extern spinlock_t fts_int; +struct fts_ts_info *fts_info; + +static int fts_init_sensing(struct fts_ts_info *info); +static int fts_mode_handler(struct fts_ts_info *info, int force); +static int fts_chip_initialization(struct fts_ts_info *info, int init_type); +static const char *fts_get_limit(struct fts_ts_info *info); +static irqreturn_t fts_event_handler(int irq, void *ts_info); +extern void lpm_disable_for_input(bool on); +extern void touch_irq_boost(void); + +/** +* Release all the touches in the linux input subsystem +* @param info pointer to fts_ts_info which contains info about the device and its hw setup +*/ +void release_all_touches(struct fts_ts_info *info) +{ + unsigned int type = MT_TOOL_FINGER; + int i; + + for (i = 0; i < TOUCH_ID_MAX; i++) { +#ifdef STYLUS_MODE + if (test_bit(i, &info->stylus_id)) + type = MT_TOOL_PEN; + else + type = MT_TOOL_FINGER; +#endif + info->coor[i][0] = -1; + info->coor[i][1] = -1; + input_mt_slot(info->input_dev, i); + input_mt_report_slot_state(info->input_dev, type, 0); + input_report_abs(info->input_dev, ABS_MT_TRACKING_ID, -1); + } + input_sync(info->input_dev); + info->touch_id = 0; + info->touch_skip = 0; + info->fod_id = 0; +#ifdef STYLUS_MODE + info->stylus_id = 0; +#endif + lpm_disable_for_input(false); +} + +/** + * @defgroup file_nodes Driver File Nodes + * Driver publish a series of file nodes used to provide several utilities to the host and give him access to different API. + * @{ + */ + +/** + * @defgroup device_file_nodes Device File Nodes + * @ingroup file_nodes + * Device File Nodes \n + * There are several file nodes that are associated to the device and which are designed to be used by the host to enable/disable features or trigger some system specific actions \n + * Usually their final path depend on the definition of device tree node of the IC (e.g /sys/devices/soc.0/f9928000.i2c/i2c-6/6-0049) + * @{ + */ +/***************************************** FW UPGGRADE ***************************************************/ + +/** + * File node function to Update firmware from shell \n + * echo path_to_fw X Y > fwupdate perform a fw update \n + * where: \n + * path_to_fw = file name or path of the the FW to burn, if "NULL" the default approach selected in the driver will be used\n + * X = 0/1 to force the FW update whichever fw_version and config_id; 0=perform a fw update only if the fw in the file is newer than the fw in the chip \n + * Y = 0/1 keep the initialization data; 0 = will erase the initialization data from flash, 1 = will keep the initialization data + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent an error code (00000000 no error) \n + * } = end byte + */ +static ssize_t fts_fwupdate_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret, mode[2]; + char path[100]; + struct fts_ts_info *info = dev_get_drvdata(dev); + + /* by default(if not specified by the user) set the force = 0 and keep_cx to 1 */ + mode[0] = 0; + mode[1] = 1; + + /* reading out firmware upgrade parameters */ + sscanf(buf, "%100s %d %d", path, &mode[0], &mode[1]); + logError(1, "%s fts_fwupdate_store: mode = %s \n", tag, path); + + ret = flashProcedure(path, mode[0], mode[1]); + + info->fwupdate_stat = ret; + + if (ret < OK) + logError(1, "%s %s Unable to upgrade firmware! ERROR %08X\n", + tag, __func__, ret); + return count; +} + +static ssize_t fts_fwupdate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + + /*fwupdate_stat: ERROR code Returned by flashProcedure. */ + return snprintf(buf, PAGE_SIZE, "{ %08X }\n", info->fwupdate_stat); +} + +/***************************************** UTILITIES (current fw_ver/conf_id, active mode, file fw_ver/conf_id) ***************************************************/ +/** +* File node to show on terminal external release version in Little Endian (first the less significant byte) \n +* cat appid show on the terminal external release version of the FW running in the IC +*/ +static ssize_t fts_appid_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int error; + char temp[100] = { + 0x00, + }; + + error = snprintf(buf, PAGE_SIZE, "%s\n", + printHex("EXT Release = ", systemInfo.u8_releaseInfo, + EXTERNAL_RELEASE_INFO_SIZE, temp)); + + return error; +} + +/** + * File node to show on terminal the mode that is active on the IC \n + * cat mode_active to show the bitmask which indicate the modes/features which are running on the IC in a specific instant of time + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1 = 1 byte in HEX format which represent the actual running scan mode (@link scan_opt Scan Mode Options @endlink) \n + * X2 = 1 byte in HEX format which represent the bitmask on which is running the actual scan mode \n + * X3X4 = 2 bytes in HEX format which represent a bitmask of the features that are enabled at this moment (@link feat_opt Feature Selection Options @endlink) \n + * } = end byte + * @see fts_mode_handler() + */ +static ssize_t fts_mode_active_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(1, "%s Current mode active = %08X\n", tag, info->mode); + return snprintf(buf, PAGE_SIZE, "{ %08X }\n", info->mode); +} + +/** + * File node to show the fw_ver and config_id of the FW file + * cat fw_file_test show on the kernel log fw_version and config_id of the FW stored in the fw file/header file + */ +static ssize_t fts_fw_test_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + Firmware fw; + int ret; + char temp[100] = { + 0x00, + }; + struct fts_ts_info *info = dev_get_drvdata(dev); + + fw.data = NULL; + ret = readFwFile(info->board->default_fw_name, &fw, 0); + + if (ret < OK) { + logError(1, "%s Error during reading FW file! ERROR %08X\n", + tag, ret); + } else { + logError(1, "%s %s, size = %d bytes\n", tag, + printHex("EXT Release = ", systemInfo.u8_releaseInfo, + EXTERNAL_RELEASE_INFO_SIZE, temp), + fw.data_size); + } + + kfree(fw.data); + return 0; +} + +/***************************************** FEATURES ***************************************************/ + +/*TODO: edit this function according to the features policy to allow during the screen on/off, following is shown an example but check always with ST for more details*/ +/** + * Check if there is any conflict in enable/disable a particular feature considering the features already enabled and running + * @param info pointer to fts_ts_info which contains info about the device and its hw setup + * @param feature code of the feature that want to be tested + * @return OK if is possible to enable/disable feature, ERROR_OP_NOT_ALLOW in case of any other conflict + */ +int check_feature_feasibility(struct fts_ts_info *info, unsigned int feature) +{ + int res = OK; + + switch (feature) { + case FEAT_SEL_GESTURE: + if (info->cover_enabled == 1) { + res = ERROR_OP_NOT_ALLOW; + logError( + 1, + "%s %s: Feature not allowed when in Cover mode! ERROR %08X \n", + tag, __func__, res); + /*for example here can be placed a code for disabling the cover mode when gesture is activated */ + } + break; + + case FEAT_SEL_GLOVE: + if (info->gesture_enabled == 1) { + res = ERROR_OP_NOT_ALLOW; + logError( + 1, + "%s %s: Feature not allowed when Gestures enabled! ERROR %08X \n", + tag, __func__, res); + /*for example here can be placed a code for disabling the gesture mode when cover is activated (that means that cover mode has an higher priority on gesture mode) */ + } + break; + + default: + logError(1, "%s %s: Feature Allowed! \n", tag, __func__); + } + + return res; +} + +#ifdef USE_ONE_FILE_NODE +/** + * File node to enable some feature + * echo XX 00/01 > feature_enable to enable/disable XX (possible values @link feat_opt Feature Selection Options @endlink) feature \n + * cat feature_enable to show the result of enabling/disabling process \n + * echo 01/00 > feature_enable; cat feature_enable to perform both actions stated before in just one call \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent an error code (00000000 = no error) \n + * } = end byte + */ +static ssize_t fts_feature_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + char *p = (char *)buf; + unsigned int temp; + int res = OK; + + if ((count - 2 + 1) / 3 != 1) { + logError( + 1, + "%s fts_feature_enable: Number of parameter wrong! %d > %d \n", + tag, (count - 2 + 1) / 3, 1); + } else { + sscanf(p, "%02X ", &temp); + p += 9; + res = check_feature_feasibility(info, temp); + if (res >= OK) { + switch (temp) { +#ifdef GESTURE_MODE + case FEAT_SEL_GESTURE: + sscanf(p, "%02X ", &info->gesture_enabled); + logError( + 1, + "%s fts_feature_enable: Gesture Enabled = %d \n", + tag, info->gesture_enabled); + break; +#endif + +#ifdef GLOVE_MODE + case FEAT_SEL_GLOVE: + sscanf(p, "%02X ", &info->glove_enabled); + logError( + 1, + "%s fts_feature_enable: Glove Enabled = %d \n", + tag, info->glove_enabled); + + break; +#endif + +#ifdef STYLUS_MODE + case FEAT_SEL_STYLUS: + sscanf(p, "%02X ", &info->stylus_enabled); + logError( + 1, + "%s fts_feature_enable: Stylus Enabled = %d \n", + tag, info->stylus_enabled); + + break; +#endif + +#ifdef COVER_MODE + case FEAT_SEL_COVER: + sscanf(p, "%02X ", &info->cover_enabled); + logError( + 1, + "%s fts_feature_enable: Cover Enabled = %d \n", + tag, info->cover_enabled); + + break; +#endif + +#ifdef CHARGER_MODE + case FEAT_SEL_CHARGER: + sscanf(p, "%02X ", &info->charger_enabled); + logError( + 1, + "%s fts_feature_enable: Charger Enabled = %d \n", + tag, info->charger_enabled); + + break; +#endif + +#ifdef GRIP_MODE + case FEAT_SEL_GRIP: + sscanf(p, "%02X ", &info->grip_enabled); + logError( + 1, + "%s fts_feature_enable: Grip Enabled = %d \n", + tag, info->grip_enabled); + + break; +#endif + default: + logError( + 1, + "%s fts_feature_enable: Feature %08X not valid! ERROR %08X\n", + tag, temp, ERROR_OP_NOT_ALLOW); + res = ERROR_OP_NOT_ALLOW; + } + feature_feasibility = res; + } + if (feature_feasibility >= OK) + feature_feasibility = fts_mode_handler(info, 1); + else { + logError( + 1, + "%s %s: Call echo XX 00/01 > feature_enable with a correct feature value (XX)! ERROR %08X \n", + tag, __func__, res); + } + } + return count; +} + +static ssize_t fts_feature_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0; + + if (feature_feasibility < OK) { + logError( + 1, + "%s %s: Call before echo XX 00/01 > feature_enable with a correct feature value (XX)! ERROR %08X \n", + tag, __func__, feature_feasibility); + } + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", + feature_feasibility); + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError( + 1, + "%s fts_feature_enable_show: Unable to allocate all_strbuff! ERROR %08X\n", + tag, ERROR_ALLOC); + } + + feature_feasibility = ERROR_OP_NOT_ALLOW; + return count; +} +#else + +#ifdef GRIP_MODE +/** + * File node to set the grip mode + * echo 01/00 > grip_mode to enable/disable glove mode \n + * cat grip_mode to show the status of the grip_enabled switch \n + * echo 01/00 > grip_mode; cat grip_mode to enable/disable grip mode and see the switch status in just one call \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent the value info->grip_enabled (1 = enabled; 0= disabled) \n + * } = end byte + */ +static ssize_t fts_grip_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(0, "%s %s: grip_enabled = %d \n", tag, __func__, + info->grip_enabled); + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", + info->grip_enabled); + + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError(1, + "%s %s: Unable to allocate all_strbuff! ERROR %08X\n", + tag, __func__, ERROR_ALLOC); + } + + return count; +} + +static ssize_t fts_grip_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *p = (char *)buf; + unsigned int temp; + int res; + struct fts_ts_info *info = dev_get_drvdata(dev); + + /*in case of a different elaboration of the input, just modify this initial part of the code according to customer needs*/ + if ((count + 1) / 3 != 1) { + logError( + 1, + "%s %s: Number of bytes of parameter wrong! %d != %d byte\n", + tag, __func__, (count + 1) / 3, 1); + } else { + sscanf(p, "%02X ", &temp); + p += 3; + /* +*this is a standard code that should be always used when a feature is enabled! +*first step : check if the wanted feature can be enabled +*second step: call fts_mode_handler to actually enable it +*NOTE: Disabling a feature is always allowed by default +*/ + res = check_feature_feasibility(info, FEAT_SEL_GRIP); + if (res >= OK || temp == FEAT_DISABLE) { + info->grip_enabled = temp; + res = fts_mode_handler(info, 1); + if (res < OK) { + logError( + 1, + "%s %s: Error during fts_mode_handler! ERROR %08X\n", + tag, __func__, res); + } + } + } + return count; +} +#endif + +#ifdef CHARGER_MODE +/** + * File node to set the glove mode + * echo XX/00 > charger_mode to value >0 to enable (possible values: @link charger_opt Charger Options @endlink),00 to disable charger mode \n + * cat charger_mode to show the status of the charger_enabled switch \n + * echo 01/00 > charger_mode; cat charger_mode to enable/disable charger mode and see the switch status in just one call \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent the value info->charger_enabled (>0 = enabled; 0= disabled) \n + * } = end byte + */ +static ssize_t fts_charger_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(0, "%s %s: charger_enabled = %d \n", tag, __func__, + info->charger_enabled); + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", + info->charger_enabled); + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError(1, + "%s %s: Unable to allocate all_strbuff! ERROR %08X\n", + tag, __func__, ERROR_ALLOC); + } + + return count; +} + +static ssize_t fts_charger_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *p = (char *)buf; + unsigned int temp; + int res; + struct fts_ts_info *info = dev_get_drvdata(dev); + + /*in case of a different elaboration of the input, just modify this initial part of the code according to customer needs*/ + if ((count + 1) / 3 != 1) { + logError( + 1, + "%s %s: Number of bytes of parameter wrong! %d != %d byte\n", + tag, __func__, (count + 1) / 3, 1); + } else { + sscanf(p, "%02X ", &temp); + p += 3; + /* +*this is a standard code that should be always used when a feature is enabled! +*first step : check if the wanted feature can be enabled +*second step: call fts_mode_handler to actually enable it +*NOTE: Disabling a feature is always allowed by default +*/ + res = check_feature_feasibility(info, FEAT_SEL_CHARGER); + if (res >= OK || temp == FEAT_DISABLE) { + info->charger_enabled = temp; + res = fts_mode_handler(info, 1); + if (res < OK) { + logError( + 1, + "%s %s: Error during fts_mode_handler! ERROR %08X\n", + tag, __func__, res); + } + } + } + return count; +} +#endif + +#ifdef GLOVE_MODE +/** + * File node to set the glove mode + * echo 01/00 > glove_mode to enable/disable glove mode \n + * cat glove_mode to show the status of the glove_enabled switch \n + * echo 01/00 > glove_mode; cat glove_mode to enable/disable glove mode and see the switch status in just one call \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent the of value info->glove_enabled (1 = enabled; 0= disabled) \n + * } = end byte + */ +static ssize_t fts_glove_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(0, "%s %s: glove_enabled = %d \n", tag, __func__, + info->glove_enabled); + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", + info->glove_enabled); + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError(1, + "%s %s: Unable to allocate all_strbuff! ERROR %08X\n", + tag, __func__, ERROR_ALLOC); + } + + return count; +} + +static ssize_t fts_glove_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *p = (char *)buf; + unsigned int temp; + int res; + struct fts_ts_info *info = dev_get_drvdata(dev); + + /*in case of a different elaboration of the input, just modify this initial part of the code according to customer needs*/ + if ((count + 1) / 3 != 1) { + logError( + 1, + "%s %s: Number of bytes of parameter wrong! %d != %d byte\n", + tag, __func__, (count + 1) / 3, 1); + } else { + sscanf(p, "%02X ", &temp); + p += 3; + /* +*this is a standard code that should be always used when a feature is enabled! +*first step : check if the wanted feature can be enabled +*second step: call fts_mode_handler to actually enable it +*NOTE: Disabling a feature is always allowed by default +*/ + res = check_feature_feasibility(info, FEAT_SEL_GLOVE); + if (res >= OK || temp == FEAT_DISABLE) { + info->glove_enabled = temp; + res = fts_mode_handler(info, 1); + if (res < OK) { + logError( + 1, + "%s %s: Error during fts_mode_handler! ERROR %08X\n", + tag, __func__, res); + } + } + } + + return count; +} +#endif + +#ifdef COVER_MODE +/** + * File node to set the cover mode + * echo 01/00 > cover_mode to enable/disable cover mode \n + * cat cover_mode to show the status of the cover_enabled switch \n + * echo 01/00 > cover_mode; cat cover_mode to enable/disable cover mode and see the switch status in just one call \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which is the value of info->cover_enabled (1 = enabled; 0= disabled)\n + * } = end byte\n + * NOTE: \n + * the cover can be handled also using a notifier, in this case the body of these functions should be copied in the notifier callback + */ +static ssize_t fts_cover_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(0, "%s %s: cover_enabled = %d \n", tag, __func__, + info->cover_enabled); + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", + info->cover_enabled); + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError(1, + "%s %s: Unable to allocate all_strbuff! ERROR %08X\n", + tag, __func__, ERROR_ALLOC); + } + + return count; +} + +static ssize_t fts_cover_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *p = (char *)buf; + unsigned int temp; + int res; + struct fts_ts_info *info = dev_get_drvdata(dev); + + /*in case of a different elaboration of the input, just modify this initial part of the code according to customer needs*/ + if ((count + 1) / 3 != 1) { + logError( + 1, + "%s %s: Number of bytes of parameter wrong! %d != %d byte\n", + tag, __func__, (count + 1) / 3, 1); + } else { + sscanf(p, "%02X ", &temp); + p += 3; + /* +*this is a standard code that should be always used when a feature is enabled! +*first step : check if the wanted feature can be enabled +*second step: call fts_mode_handler to actually enable it +*NOTE: Disabling a feature is always allowed by default +*/ + res = check_feature_feasibility(info, FEAT_SEL_COVER); + if (res >= OK || temp == FEAT_DISABLE) { + info->cover_enabled = temp; + res = fts_mode_handler(info, 1); + if (res < OK) { + logError( + 1, + "%s %s: Error during fts_mode_handler! ERROR %08X\n", + tag, __func__, res); + } + } + } + + return count; +} +#endif + +#ifdef STYLUS_MODE +/** + * File node to enable the stylus report + * echo 01/00 > stylus_mode to enable/disable stylus mode\n + * cat stylus_mode to show the status of the stylus_enabled switch\n + * echo 01/00 > stylus_mode; cat stylus_mode to enable/disable stylus mode and see the switch status in just one call\n + * the string returned in the shell is made up as follow:\n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which is the value of info->stylus_enabled (1 = enabled; 0= disabled)\n + * } = end byte + */ +static ssize_t fts_stylus_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(0, "%s %s: stylus_enabled = %d \n", tag, __func__, + info->stylus_enabled); + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", + info->stylus_enabled); + + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError(1, + "%s %s: Unable to allocate all_strbuff! ERROR %08X\n", + tag, __func__, ERROR_ALLOC); + } + + return count; +} + +static ssize_t fts_stylus_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *p = (char *)buf; + unsigned int temp; + struct fts_ts_info *info = dev_get_drvdata(dev); + + /*in case of a different elaboration of the input, just modify this initial part of the code according to customer needs*/ + if ((count + 1) / 3 != 1) { + logError( + 1, + "%s %s: Number of bytes of parameter wrong! %d != %d byte\n", + tag, __func__, (count + 1) / 3, 1); + } else { + sscanf(p, "%02X ", &temp); + p += 3; + info->stylus_enabled = temp; + } + return count; +} +#endif + +#endif + +/***************************************** GESTURES ***************************************************/ +#ifdef GESTURE_MODE +#ifdef USE_GESTURE_MASK +/** + * File node used by the host to set the gesture mask to enable or disable + * echo EE X1 X2 ~~ > gesture_mask set the gesture to disable/enable; EE = 00(disable) or 01(enable)\n + * X1 ~~ = gesture mask (example 06 00 ~~ 00 this gesture mask represents the gestures with ID = 1 and 2) can be specified from 1 to GESTURE_MASK_SIZE bytes,\n + * if less than GESTURE_MASK_SIZE bytes are passed as arguments, the omit bytes of the mask maintain the previous settings\n + * if one or more gestures is enabled the driver will automatically enable the gesture mode, If all the gestures are disabled the driver automatically will disable the gesture mode\n + * cat gesture_mask set inside the specified mask and return an error code for the operation \n + * the string returned in the shell is made up as follow:\n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent an error code for enabling the mask (00000000 = no error)\n + * } = end byte \n\n + * if USE_GESTURE_MASK is not define the usage of the function become: \n\n + * echo EE X1 X2 ~~ > gesture_mask set the gesture to disable/enable; EE = 00(disable) or 01(enable)\n + * X1 ~~ = gesture IDs (example 01 02 05 represent the gestures with ID = 1, 2 and 5) there is no limit of the IDs passed as arguments, (@link gesture_opt Gesture IDs @endlink)\n + * if one or more gestures is enabled the driver will automatically enable the gesture mode. If all the gestures are disabled the driver automatically will disable the gesture mode.\n + * cat gesture_mask to show the status of the gesture enabled switch \n + * the string returned in the shell is made up as follow:\n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which is the value of info->gesture_enabled (1 = enabled; 0= disabled)\n + * } = end byte + */ +static ssize_t fts_gesture_mask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0, res, temp; + struct fts_ts_info *info = dev_get_drvdata(dev); + + if (mask[0] == 0) { + res = ERROR_OP_NOT_ALLOW; + logError( + 1, + "%s %s: Call before echo enable/disable xx xx .... > gesture_mask with a correct number of parameters! ERROR %08X \n", + tag, __func__, res); + } else { + if (mask[1] == FEAT_ENABLE || mask[1] == FEAT_DISABLE) + res = updateGestureMask(&mask[2], mask[0], mask[1]); + else + res = ERROR_OP_NOT_ALLOW; + + if (res < OK) { + logError(1, "%s fts_gesture_mask_store: ERROR %08X \n", + tag, res); + } + } + res |= check_feature_feasibility(info, FEAT_SEL_GESTURE); + temp = isAnyGestureActive(); + if (res >= OK || temp == FEAT_DISABLE) { + info->gesture_enabled = temp; + } + + logError(1, "%s fts_gesture_mask_store: Gesture Enabled = %d \n", tag, + info->gesture_enabled); + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", res); + + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError( + 1, + "%s fts_gesture_mask_show: Unable to allocate all_strbuff! ERROR %08X\n", + tag, ERROR_ALLOC); + } + + mask[0] = 0; + return count; +} + +static ssize_t fts_gesture_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *p = (char *)buf; + int n; + unsigned int temp; + + if ((count + 1) / 3 > GESTURE_MASK_SIZE + 1) { + logError( + 1, + "%s fts_gesture_mask_store: Number of bytes of parameter wrong! %d > (enable/disable + %d )\n", + tag, (count + 1) / 3, GESTURE_MASK_SIZE); + mask[0] = 0; + } else { + mask[0] = ((count + 1) / 3) - 1; + for (n = 1; n <= (count + 1) / 3; n++) { + sscanf(p, "%02X ", &temp); + p += 3; + mask[n] = (u8)temp; + logError(0, "%s mask[%d] = %02X \n", tag, n, mask[n]); + } + } + + return count; +} + +#else +/** + * File node used by the host to set the gesture mask to enable or disable + * echo EE X1 X2 ~~ > gesture_mask set the gesture to disable/enable; EE = 00(disable) or 01(enable)\n + * X1 ~ = gesture IDs (example 01 02 05 represent the gestures with ID = 1, 2 and 5) there is no limit of the IDs passed as arguments, (@link gesture_opt Gesture IDs @endlink) \n + * if one or more gestures is enabled the driver will automatically enable the gesture mode, If all the gestures are disabled the driver automatically will disable the gesture mode \n + * cat gesture_mask to show the status of the gesture enabled switch \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which is the value of info->gesture_enabled (1 = enabled; 0= disabled)\n + * } = end byte + */ +static ssize_t fts_gesture_mask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(0, "%s fts_gesture_mask_show: gesture_enabled = %d \n", tag, + info->gesture_enabled); + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + index += snprintf(&all_strbuff[index], 13, "{ %08X }", + info->gesture_enabled); + + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError( + 1, + "%s fts_gesture_mask_show: Unable to allocate all_strbuff! ERROR %08X\n", + tag, ERROR_ALLOC); + } + + return count; +} + +static ssize_t fts_gesture_mask_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + char *p = (char *)buf; + int n; + unsigned int temp; + int res; + struct fts_ts_info *info = dev_get_drvdata(dev); + + if ((count + 1) / 3 < 2 || (count + 1) / 3 > GESTURE_MASK_SIZE + 1) { + logError( + 1, + "%s fts_gesture_mask_store: Number of bytes of parameter wrong! %d < or > (enable/disable + at least one gestureID or max %d bytes)\n", + tag, (count + 1) / 3, GESTURE_MASK_SIZE); + mask[0] = 0; + } else { + memset(mask, 0, GESTURE_MASK_SIZE + 2); + mask[0] = ((count + 1) / 3) - 1; + sscanf(p, "%02X ", &temp); + p += 3; + mask[1] = (u8)temp; + for (n = 1; n < (count + 1) / 3; n++) { + sscanf(p, "%02X ", &temp); + p += 3; + fromIDtoMask((u8)temp, &mask[2], GESTURE_MASK_SIZE); + } + + for (n = 0; n < GESTURE_MASK_SIZE + 2; n++) { + logError(1, "%s mask[%d] = %02X \n", tag, n, mask[n]); + } + } + + if (mask[0] == 0) { + res = ERROR_OP_NOT_ALLOW; + logError( + 1, + "%s %s: Call before echo enable/disable xx xx .... > gesture_mask with a correct number of parameters! ERROR %08X \n", + tag, __func__, res); + } else { + if (mask[1] == FEAT_ENABLE || mask[1] == FEAT_DISABLE) + res = updateGestureMask(&mask[2], mask[0], mask[1]); + else + res = ERROR_OP_NOT_ALLOW; + + if (res < OK) { + logError(1, "%s fts_gesture_mask_store: ERROR %08X \n", + tag, res); + } + } + + res = check_feature_feasibility(info, FEAT_SEL_GESTURE); + temp = isAnyGestureActive(); + if (res >= OK || temp == FEAT_DISABLE) { + info->gesture_enabled = temp; + } + res = fts_mode_handler(info, 0); + + return count; +} + +#endif + +/** + * File node to read the coordinates of the last gesture drawn by the user \n + * cat gesture_coordinates to obtain the gesture coordinates \n + * the string returned in the shell follow this up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent an error code (00000000 no error) \n + * \n if error code = 00000000 \n + * CC = 1 byte in HEX format number of coords (pair of x,y) returned \n + * XXiYYi ... = XXi 2 bytes in HEX format for x[i] and YYi 2 bytes in HEX format for y[i] (big endian) \n + * \n + * } = end byte + */ +static ssize_t fts_gesture_coordinates_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int size = (6 * 2) + 1, index = 0; + u8 *all_strbuff = NULL; + int count = 0, res, i = 0; + + logError(0, "%s %s: Getting gestures coordinates... \n", tag, __func__); + + if (gesture_coords_reported < OK) { + logError(1, "%s %s: invalid coordinates! ERROR %08X \n", tag, + __func__, gesture_coords_reported); + res = gesture_coords_reported; + } else { + size += gesture_coords_reported * 2 * 4 + 2; + res = OK; + } + + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + if (all_strbuff != NULL) { + snprintf(&all_strbuff[index], 11, "{ %08X", res); + index += 10; + + if (res >= OK) { + snprintf(&all_strbuff[index], 3, "%02X", + gesture_coords_reported); + index += 2; + + for (i = 0; i < gesture_coords_reported; i++) { + snprintf(&all_strbuff[index], 5, "%04X", + gesture_coordinates_x[i]); + index += 4; + snprintf(&all_strbuff[index], 5, "%04X", + gesture_coordinates_y[i]); + index += 4; + } + } + + index += snprintf(&all_strbuff[index], 3, " }"); + + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + logError(0, "%s %s: Getting gestures coordinates FINISHED! \n", + tag, __func__); + + } else { + logError(1, + "%s %s: Unable to allocate all_strbuff! ERROR %08X\n", + tag, ERROR_ALLOC); + } + + return count; +} +#endif + +/***************************************** PRODUCTION TEST ***************************************************/ + +/** + * File node to execute the Mass Production Test or to get data from the IC (raw or ms/ss init data) + * echo cmd > stm_fts_cmd to execute a command \n + * cat stm_fts_cmd to show the result of the command \n + * echo cmd > stm_fts_cmd; cat stm_fts_cmd to execute and show the result in just one call \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * X1X2X3X4 = 4 bytes in HEX format which represent an error_code (00000000 = OK)\n + * (optional) data = data coming from the command executed represented as HEX string \n + * Not all the command return additional data \n + * } = end byte + * \n + * Possible commands (cmd): \n + * - 00 = MP Test -> return erro_code \n + * - 01 = ITO Test -> return error_code \n + * - 03 = MS Raw Test -> return error_code \n + * - 04 = MS Init Data Test -> return error_code \n + * - 05 = SS Raw Test -> return error_code \n + * - 06 = SS Init Data Test -> return error_code \n + * - 13 = Read 1 MS Raw Frame -> return additional data: MS frame row after row \n + * - 14 = Read MS Init Data -> return additional data: MS init data row after row \n + * - 15 = Read 1 SS Raw Frame -> return additional data: SS frame, force channels followed by sense channels \n + * - 16 = Read SS Init Data -> return additional data: SS Init data, first IX for force and sense channels and then CX for force and sense channels \n + * - F0 = Perform a system reset -> return error_code \n + * - F1 = Perform a system reset and reenable the sensing and the interrupt + */ +static ssize_t stm_fts_cmd_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int n; + char *p = (char *)buf; + + memset(typeOfComand, 0, CMD_STR_LEN * sizeof(u32)); + + logError(1, "%s \n", tag); + for (n = 0; n < (count + 1) / 3; n++) { + sscanf(p, "%02X ", &typeOfComand[n]); + p += 3; + logError(1, "%s typeOfComand[%d] = %02X \n", tag, n, + typeOfComand[n]); + } + + numberParameters = n; + logError(1, "%s Number of Parameters = %d \n", tag, numberParameters); + return count; +} + +static ssize_t stm_fts_cmd_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int res, j, doClean = 0, count = 0, index = 0; + char buff[CMD_STR_LEN] = { 0 }; + + int size = (6 * 2) + 1; + int init_type = SPECIAL_PANEL_INIT; + u8 *all_strbuff = NULL; + const char *limit_file_name = NULL; + struct fts_ts_info *info = dev_get_drvdata(dev); + + MutualSenseData compData; + SelfSenseData comData; + MutualSenseFrame frameMS; + SelfSenseFrame frameSS; + + if (numberParameters >= 1) { + res = fts_disableInterrupt(); + if (res < 0) { + logError(0, "%s fts_disableInterrupt: ERROR %08X \n", + tag, res); + res = (res | ERROR_DISABLE_INTER); + goto END; + } +#ifdef CONFIG_DRM + res = drm_unregister_client(&info->notifier); + if (res < 0) { + logError(1, "%s ERROR: unregister notifier failed!\n", + tag); + goto END; + } +#endif + switch (typeOfComand[0]) { + /*ITO TEST */ + case 0x01: + res = production_test_ito(LIMITS_FILE, &tests); + break; + /*PRODUCTION TEST */ + case 0x00: + + if (systemInfo.u8_cfgAfeVer != systemInfo.u8_cxAfeVer) { + res = ERROR_OP_NOT_ALLOW; + logError( + 0, + "%s Miss match in CX version! MP test not allowed with wrong CX memory! ERROR %08X \n", + tag, res); + break; + } + + limit_file_name = fts_get_limit(info); + res = production_test_main(LIMITS_FILE, 1, init_type, + &tests); + break; + /*read mutual raw */ + case 0x13: + logError(0, "%s Get 1 MS Frame \n", tag); + setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + flushFIFO(); + res = getMSFrame3(MS_RAW, &frameMS); + if (res < 0) { + logError( + 0, + "%s Error while taking the MS frame... ERROR %08X \n", + tag, res); + + } else { + logError(0, "%s The frame size is %d words\n", + tag, res); + size = (res * (sizeof(short) * 2 + 1)) + 10; + res = OK; + print_frame_short( + "MS frame =", + array1dTo2d_short( + frameMS.node_data, + frameMS.node_data_size, + frameMS.header.sense_node), + frameMS.header.force_node, + frameMS.header.sense_node); + } + break; + /*read self raw */ + case 0x15: + logError(0, "%s Get 1 SS Frame \n", tag); + setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + flushFIFO(); + res = getSSFrame3(SS_RAW, &frameSS); + + if (res < OK) { + logError( + 0, + "%s Error while taking the SS frame... ERROR %08X \n", + tag, res); + + } else { + logError(0, "%s The frame size is %d words\n", + tag, res); + size = (res * (sizeof(short) * 2 + 1)) + 10; + res = OK; + print_frame_short( + "SS force frame =", + array1dTo2d_short( + frameSS.force_data, + frameSS.header.force_node, 1), + frameSS.header.force_node, 1); + print_frame_short( + "SS sense frame =", + array1dTo2d_short( + frameSS.sense_data, + frameSS.header.sense_node, + frameSS.header.sense_node), + 1, frameSS.header.sense_node); + } + + break; + + case 0x14: + logError(0, "%s Get MS Compensation Data \n", tag); + res = readMutualSenseCompensationData(LOAD_CX_MS_TOUCH, + &compData); + + if (res < 0) { + logError( + 0, + "%s Error reading MS compensation data ERROR %08X \n", + tag, res); + } else { + logError( + 0, + "%s MS Compensation Data Reading Finished! \n", + tag); + size = (compData.node_data_size * sizeof(u8)) * + 3 + + 1; + print_frame_i8( + "MS Data (Cx2) =", + array1dTo2d_i8( + compData.node_data, + compData.node_data_size, + compData.header.sense_node), + compData.header.force_node, + compData.header.sense_node); + } + break; + + case 0x16: + logError(0, "%s Get SS Compensation Data... \n", tag); + res = readSelfSenseCompensationData(LOAD_CX_SS_TOUCH, + &comData); + if (res < 0) { + logError( + 0, + "%s Error reading SS compensation data ERROR %08X\n", + tag, res); + } else { + logError( + 0, + "%s SS Compensation Data Reading Finished! \n", + tag); + size = ((comData.header.force_node + + comData.header.sense_node) * + 2 + + 12) * sizeof(u8) * + 2 + + 1; + print_frame_u8( + "SS Data Ix2_fm = ", + array1dTo2d_u8( + comData.ix2_fm, + comData.header.force_node, 1), + comData.header.force_node, 1); + print_frame_i8( + "SS Data Cx2_fm = ", + array1dTo2d_i8( + comData.cx2_fm, + comData.header.force_node, 1), + comData.header.force_node, 1); + print_frame_u8( + "SS Data Ix2_sn = ", + array1dTo2d_u8( + comData.ix2_sn, + comData.header.sense_node, + comData.header.sense_node), + 1, comData.header.sense_node); + print_frame_i8( + "SS Data Cx2_sn = ", + array1dTo2d_i8( + comData.cx2_sn, + comData.header.sense_node, + comData.header.sense_node), + 1, comData.header.sense_node); + } + break; + + case 0x03: + res = fts_system_reset(); + if (res >= OK) + res = production_test_ms_raw(LIMITS_FILE, 1, + &tests); + break; + + case 0x04: + res = fts_system_reset(); + if (res >= OK) + res = production_test_ms_cx(LIMITS_FILE, 1, + &tests); + break; + + case 0x05: + res = fts_system_reset(); + if (res >= OK) + res = production_test_ss_raw(LIMITS_FILE, 1, + &tests); + break; + + case 0x06: + res = fts_system_reset(); + if (res >= OK) + res = production_test_ss_ix_cx(LIMITS_FILE, 1, + &tests); + break; + + case 0xF0: + case 0xF1: + doClean = (int)(typeOfComand[0] & 0x01); + res = cleanUp(doClean); + break; + + default: + logError( + 1, + "%s COMMAND NOT VALID!! Insert a proper value ...\n", + tag); + res = ERROR_OP_NOT_ALLOW; + break; + } + + doClean = fts_mode_handler(info, 1); + if (typeOfComand[0] != 0xF0) + doClean |= fts_enableInterrupt(); + if (doClean < 0) { + logError(0, "%s %s: ERROR %08X \n", tag, __func__, + (doClean | ERROR_ENABLE_INTER)); + } + } else { + logError( + 1, + "%s NO COMMAND SPECIFIED!!! do: 'echo [cmd_code] [args] > stm_fts_cmd' before looking for result!\n", + tag); + res = ERROR_OP_NOT_ALLOW; + } +#ifdef CONFIG_DRM + if (drm_register_client(&info->notifier) < 0) { + logError(1, "%s ERROR: register notifier failed!\n", tag); + } +#endif +END: + all_strbuff = (u8 *)kzalloc(size, GFP_KERNEL); + + if (res >= OK) { + /*all the other cases are already fine printing only the res. */ + switch (typeOfComand[0]) { + case 0x13: + snprintf(all_strbuff, size, "ms_frame\n"); + for (j = 0; j < frameMS.node_data_size; j++) { + if ((j + 1) % frameMS.header.sense_node) + snprintf(buff, sizeof(buff), "%04d ", + frameMS.node_data[j]); + else + snprintf(buff, sizeof(buff), "%04d\n", + frameMS.node_data[j]); + + strlcat(all_strbuff, buff, size); + } + + kfree(frameMS.node_data); + frameMS.node_data = NULL; + break; + + case 0x15: + snprintf(all_strbuff, size, "ss_frame\n"); + for (j = 0; j < frameSS.header.force_node - 1; j++) { + snprintf(buff, sizeof(buff), "%04d ", + frameSS.force_data[j]); + strlcat(all_strbuff, buff, size); + } + + if (j == frameSS.header.force_node - 1) { + snprintf(buff, sizeof(buff), "%04d\n", + frameSS.force_data[j]); + strlcat(all_strbuff, buff, size); + } + + for (j = 0; j < frameSS.header.sense_node - 1; j++) { + snprintf(buff, sizeof(buff), "%04d ", + frameSS.sense_data[j]); + strlcat(all_strbuff, buff, size); + } + + if (j == frameSS.header.sense_node - 1) { + snprintf(buff, sizeof(buff), "%04d\n", + frameSS.sense_data[j]); + strlcat(all_strbuff, buff, size); + } + + kfree(frameSS.force_data); + kfree(frameSS.sense_data); + + break; + + case 0x14: + snprintf(buff, sizeof(buff), "%02X", + (u8)compData.header.force_node); + strlcat(all_strbuff, buff, size); + snprintf(buff, sizeof(buff), "%02X", + (u8)compData.header.sense_node); + strlcat(all_strbuff, buff, size); + snprintf(buff, sizeof(buff), "%02X", compData.cx1); + strlcat(all_strbuff, buff, size); + + for (j = 0; j < compData.node_data_size; j++) { + snprintf(buff, sizeof(buff), "%02X", + *(compData.node_data + j)); + strlcat(all_strbuff, buff, size); + } + + kfree(compData.node_data); + compData.node_data = NULL; + + break; + + case 0x16: + snprintf(buff, sizeof(buff), "%02X", + comData.header.force_node); + strlcat(all_strbuff, buff, size); + snprintf(buff, sizeof(buff), "%02X", + comData.header.sense_node); + strlcat(all_strbuff, buff, size); + snprintf(buff, sizeof(buff), "%02X", comData.f_ix1); + strlcat(all_strbuff, buff, size); + snprintf(buff, sizeof(buff), "%02X", comData.s_ix1); + strlcat(all_strbuff, buff, size); + snprintf(buff, sizeof(buff), "%02X", comData.f_cx1); + strlcat(all_strbuff, buff, size); + snprintf(buff, sizeof(buff), "%02X", comData.s_cx1); + strlcat(all_strbuff, buff, size); + + for (j = 0; j < comData.header.force_node; j++) { + snprintf(buff, sizeof(buff), "%02X", + comData.ix2_fm[j]); + strlcat(all_strbuff, buff, size); + } + + for (j = 0; j < comData.header.sense_node; j++) { + snprintf(buff, sizeof(buff), "%02X", + comData.ix2_sn[j]); + strlcat(all_strbuff, buff, size); + } + + for (j = 0; j < comData.header.force_node; j++) { + snprintf(buff, sizeof(buff), "%02X", + comData.cx2_fm[j]); + strlcat(all_strbuff, buff, size); + } + + for (j = 0; j < comData.header.sense_node; j++) { + snprintf(buff, sizeof(buff), "%02X", + comData.cx2_sn[j]); + strlcat(all_strbuff, buff, size); + } + + kfree(comData.ix2_fm); + kfree(comData.ix2_sn); + kfree(comData.cx2_fm); + kfree(comData.cx2_sn); + + break; + + default: + snprintf(&all_strbuff[index], 11, "{ %08X", res); + index += 10; + snprintf(&all_strbuff[index], 3, " }"); + index += 2; + + break; + } + } else { + snprintf(&all_strbuff[index], 11, "{ %08X", res); + index += 10; + snprintf(&all_strbuff[index], 3, " }"); + index += 2; + } + + count = snprintf(buf, TSP_BUF_SIZE, "%s\n", all_strbuff); + numberParameters = 0; + kfree(all_strbuff); + + return count; +} + +static ssize_t fts_panel_color_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + return snprintf(buf, PAGE_SIZE, "%c\n", info->lockdown_info[2]); +} + +static ssize_t fts_panel_vendor_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + return snprintf(buf, PAGE_SIZE, "%c\n", info->lockdown_info[6]); +} + +static ssize_t fts_panel_display_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + return snprintf(buf, PAGE_SIZE, "%c\n", info->lockdown_info[1]); +} + +static ssize_t fts_lockdown_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + int ret; + ret = fts_get_lockdown_info(info->lockdown_info, info); + + if (ret != OK) { + logError(1, "%s get lockdown info error\n", tag); + return 0; + } + + return snprintf( + buf, PAGE_SIZE, + "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + info->lockdown_info[0], info->lockdown_info[1], + info->lockdown_info[2], info->lockdown_info[3], + info->lockdown_info[4], info->lockdown_info[5], + info->lockdown_info[6], info->lockdown_info[7]); +} + +static ssize_t fts_lockdown_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int n, i, ret; + char *p = (char *)buf; + u8 *typecomand = NULL; + + memset(typeOfComand, 0, CMD_STR_LEN * sizeof(u32)); + logError(1, "%s \n", tag); + for (n = 0; n < (count + 1) / 3; n++) { + sscanf(p, "%02X ", &typeOfComand[n]); + p += 3; + logError(1, "%s command_sequence[%d] = %02X\n", tag, n, + typeOfComand[n]); + } + numberParameters = n; + if (numberParameters < 3) + goto END; + logError(1, "%s %d = %d \n", tag, n, numberParameters); + + typecomand = + (u8 *)kmalloc((numberParameters - 2) * sizeof(u8), GFP_KERNEL); + if (typecomand != NULL) { + for (i = 0; i < numberParameters - 2; i++) { + typecomand[i] = (u8)typeOfComand[i + 2]; + logError(1, "%s typecomand[%d] = %X \n", tag, i, + typecomand[i]); + } + } else { + goto END; + } + + ret = writeLockDownInfo(typecomand, numberParameters - 2, + typeOfComand[0]); + if (ret < 0) { + logError(1, "%s fts_lockdown_store failed\n", tag); + } + kfree(typecomand); +END: + logError(1, "%s Number of Parameters = %d \n", tag, numberParameters); + + return count; +} + +static ssize_t fts_lockdown_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i, ret; + int size = 0, count = 0; + u8 type; + u8 *temp_buffer = NULL; + + temp_buffer = (u8 *)kmalloc(LOCKDOWN_LENGTH * sizeof(u8), GFP_KERNEL); + if (temp_buffer == NULL || numberParameters < 2) { + count += snprintf(&buf[count], PAGE_SIZE, + "prepare read lockdown failded\n"); + return count; + } + type = typeOfComand[0]; + size = (int)(typeOfComand[1]); + count += snprintf(&buf[count], PAGE_SIZE, "read lock down code:\n"); + ret = readLockDownInfo(temp_buffer, type, size); + if (ret < OK) { + count += snprintf(&buf[count], PAGE_SIZE, + "read lockdown failded\n"); + goto END; + } + for (i = 0; i < size; i++) { + count += snprintf(&buf[count], PAGE_SIZE, "%02X ", + temp_buffer[i]); + } + count += snprintf(&buf[count], PAGE_SIZE, "\n"); + +END: + numberParameters = 0; + kfree(temp_buffer); + return count; +} + +static ssize_t fts_selftest_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int res = 0, i = 0, count = 0, force_node = 0, sense_node = 0, pos = 0, + last_pos = 0; + MutualSenseFrame frameMS; + char buff[80]; + struct i2c_client *client = to_i2c_client(dev); + struct fts_ts_info *info = i2c_get_clientdata(client); + + res = fts_disableInterrupt(); + if (res < OK) + goto END; + + setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + flushFIFO(); + res = getMSFrame3(MS_RAW, &frameMS); + if (res < 0) { + logError(0, + "%s Error while taking the MS frame... ERROR %08X \n", + tag, res); + goto END; + } + fts_mode_handler(info, 1); + + sense_node = frameMS.header.sense_node; + force_node = frameMS.header.force_node; + + for (i = 0; i < RELEASE_INFO_SIZE; i++) { + if (i == 0) { + pos += snprintf(buff + last_pos, PAGE_SIZE, "0x%02x", + systemInfo.u8_releaseInfo[i]); + last_pos = pos; + } else { + pos += snprintf(buff + last_pos, PAGE_SIZE, "%02x", + systemInfo.u8_releaseInfo[i]); + last_pos = pos; + } + } + count = snprintf( + buf, PAGE_SIZE, + "Device address:,0x49\nChip Id:,0x%04x\nFw version:,0x%04x\nConfig version:,0x%04x\nChip serial number:,%s\nForce lines count:,%02d\nSense lines count:,%02d\n\n", + systemInfo.u16_chip0Id, systemInfo.u16_fwVer, + systemInfo.u16_cfgVer, buff, force_node, sense_node); +END: + fts_enableInterrupt(); + return count; +} + +static ssize_t fts_ms_raw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int res = 0, count = 0, j = 0, sense_node = 0, force_node = 0, pos = 0, + last_pos = 0; + char *all_strbuff = NULL; + struct i2c_client *client = to_i2c_client(dev); + struct fts_ts_info *info = i2c_get_clientdata(client); + MutualSenseFrame frameMS; + + res = fts_disableInterrupt(); + if (res < OK) + goto END; + all_strbuff = vmalloc(PAGE_SIZE); + if (!all_strbuff) { + logError(1, "%s %s alloc all_strbuff fail\n", tag, __func__); + goto END; + } else + memset(all_strbuff, 0, PAGE_SIZE); + + setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + flushFIFO(); + res = getMSFrame3(MS_RAW, &frameMS); + + fts_mode_handler(info, 1); + sense_node = frameMS.header.sense_node; + force_node = frameMS.header.force_node; + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "MsTouchRaw,%2d,%2d\n ,", force_node, sense_node); + last_pos = pos; + if (res >= OK) { + for (j = 0; j < sense_node; j++) + if ((j + 1) % sense_node) { + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, "C%02d,", j); + last_pos = pos; + } else { + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, "C%02d\nR00,", j); + last_pos = pos; + } + for (j = 0; j < sense_node * force_node; j++) { + if ((j + 1) % sense_node) { + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, "%4d,", + frameMS.node_data[j]); + last_pos = pos; + } else { + if ((j + 1) / sense_node != force_node) + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, + "%4d\nR%02d,", + frameMS.node_data[j], + (j + 1) / sense_node); + else + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, "%4d\n", + frameMS.node_data[j]); + last_pos = pos; + } + } + if (frameMS.node_data) { + kfree(frameMS.node_data); + frameMS.node_data = NULL; + } + } + + count = snprintf(buf, PAGE_SIZE, "%s\n", all_strbuff); + vfree(all_strbuff); +END: + fts_enableInterrupt(); + return count; +} + +static ssize_t fts_ms_cx_total_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int res = 0, pos = 0, last_pos = 0, count = 0, j = 0, sense_node = 0, + force_node = 0; + char *all_strbuff = NULL; + TotMutualSenseData totCompData; + + res = fts_disableInterrupt(); + if (res < OK) + goto END; + all_strbuff = vmalloc(PAGE_SIZE); + if (!all_strbuff) { + logError(1, "%s %s alloc all_strbuff fail\n", tag, __func__); + goto END; + } else + memset(all_strbuff, 0, PAGE_SIZE); + + res = readTotMutualSenseCompensationData(LOAD_PANEL_CX_TOT_MS_TOUCH, + &totCompData); + if (res >= OK) { + sense_node = totCompData.header.sense_node; + force_node = totCompData.header.force_node; + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "MsTouchTotalCx,%2d,%2d\n ,", force_node, + sense_node); + last_pos = pos; + for (j = 0; j < sense_node; j++) + if ((j + 1) % sense_node) { + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, "C%02d,", j); + last_pos = pos; + } else { + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, "C%02d\nR00,", j); + last_pos = pos; + } + for (j = 0; j < sense_node * force_node; j++) { + if ((j + 1) % sense_node) { + pos += snprintf(all_strbuff + last_pos, + PAGE_SIZE, "%4d,", + totCompData.node_data[j]); + last_pos = pos; + } else { + if ((j + 1) / sense_node != force_node) + pos += snprintf( + all_strbuff + last_pos, + PAGE_SIZE, "%4d\nR%02d,", + totCompData.node_data[j], + (j + 1) / sense_node); + else + pos += snprintf( + all_strbuff + last_pos, + PAGE_SIZE, "%4d\n", + totCompData.node_data[j]); + last_pos = pos; + } + } + if (totCompData.node_data) { + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } + } + + count = snprintf(buf, PAGE_SIZE, "%s\n", all_strbuff); + vfree(all_strbuff); +END: + fts_enableInterrupt(); + return count; +} + +static ssize_t fts_ss_ix_total_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0, pos = 0, last_pos = 0, count = 0, j = 0, sense_node = 0, + force_node = 0; + char *all_strbuff = NULL; + TotSelfSenseData totCompData; + + ret = fts_disableInterrupt(); + if (ret < OK) + goto END; + all_strbuff = vmalloc(PAGE_SIZE); + if (!all_strbuff) { + logError(1, "%s %s alloc all_strbuff fail\n", tag, __func__); + goto END; + } else { + memset(all_strbuff, 0, PAGE_SIZE); + } + ret = readTotSelfSenseCompensationData(LOAD_PANEL_CX_TOT_SS_TOUCH, + &totCompData); + if (ret < 0) { + logError( + 1, + "%s production_test_data: readTotSelfSenseCompensationData failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + goto END; + } + + sense_node = 1; + force_node = totCompData.header.force_node; + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SsTouchForceTotalIx,%2d,1\n ,C00\n", force_node); + last_pos = pos; + for (j = 0; j < force_node; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "R%02d,%4d\n", j, totCompData.ix_fm[j]); + last_pos = pos; + } + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SsTouchForceTotalCx,%2d,1\n ,C00\n", force_node); + last_pos = pos; + for (j = 0; j < force_node; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "R%02d,%4d\n", j, totCompData.cx_fm[j]); + last_pos = pos; + } + + sense_node = totCompData.header.sense_node; + force_node = 1; + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SsTouchsenseTotalIx,%2d,1\n ,C00\n", sense_node); + last_pos = pos; + for (j = 0; j < sense_node; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "R%02d,%4d\n", j, totCompData.ix_sn[j]); + last_pos = pos; + } + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SsTouchsenseTotalCx,%2d,1\n ,C00\n", sense_node); + last_pos = pos; + for (j = 0; j < sense_node; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "R%02d,%4d\n", j, totCompData.cx_sn[j]); + last_pos = pos; + } + + if (totCompData.ix_fm != NULL) { + kfree(totCompData.ix_fm); + totCompData.ix_fm = NULL; + } + + if (totCompData.cx_fm != NULL) { + kfree(totCompData.cx_fm); + totCompData.cx_fm = NULL; + } + + if (totCompData.ix_sn != NULL) { + kfree(totCompData.ix_sn); + totCompData.ix_sn = NULL; + } + + if (totCompData.cx_sn != NULL) { + kfree(totCompData.cx_sn); + totCompData.cx_sn = NULL; + } + + count = snprintf(buf, PAGE_SIZE, "%s\n", all_strbuff); + vfree(all_strbuff); +END: + fts_enableInterrupt(); + return count; +} + +static ssize_t fts_ss_raw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int res = 0, count = 0, j = 0, sense_node = 0, force_node = 0, pos = 0, + last_pos = 0; + char *all_strbuff = NULL; + struct i2c_client *client = to_i2c_client(dev); + struct fts_ts_info *info = i2c_get_clientdata(client); + SelfSenseFrame frameSS; + + res = fts_disableInterrupt(); + if (res < OK) + goto END; + all_strbuff = vmalloc(PAGE_SIZE * 4); + if (!all_strbuff) { + logError(1, "%s %s alloc all_strbuff fail\n", tag, __func__); + goto END; + } else + memset(all_strbuff, 0, PAGE_SIZE); + setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + flushFIFO(); + res = getSSFrame3(SS_RAW, &frameSS); + + fts_mode_handler(info, 1); + sense_node = frameSS.header.sense_node; + force_node = frameSS.header.force_node; + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SsTouchRaw,%2d,%2d\n", force_node, sense_node); + last_pos = pos; + if (res >= OK) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS force frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.force_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.force_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.force_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.force_data[j]); + last_pos = pos; + } + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS sense frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.sense_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.sense_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.sense_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.sense_data[j]); + last_pos = pos; + } + + if (frameSS.force_data) { + kfree(frameSS.force_data); + frameSS.force_data = NULL; + } + if (frameSS.sense_data) { + kfree(frameSS.sense_data); + frameSS.sense_data = NULL; + } + } + + count = snprintf(buf, PAGE_SIZE, "%s\n", all_strbuff); + vfree(all_strbuff); +END: + fts_enableInterrupt(); + return count; +} + +static ssize_t fts_strength_frame_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + MutualSenseFrame frame; + int res = 0, count = 0, j = 0, size = 0; + char *all_strbuff = NULL; + char buff[CMD_STR_LEN] = { 0 }; + struct i2c_client *client = to_i2c_client(dev); + struct fts_ts_info *info = i2c_get_clientdata(client); + frame.node_data = NULL; + + res = fts_disableInterrupt(); + if (res < OK) + goto END; + + res = getMSFrame3(MS_STRENGTH, &frame); + + if (res < OK) { + logError(1, "%s %s: could not get the frame! ERROR %08X \n", + tag, __func__, res); + goto END; + } + size = (res * 5) + 11; + + /* + flushFIFO(); + */ + fts_mode_handler(info, 1); + all_strbuff = (char *)kmalloc(PAGE_SIZE * sizeof(char), GFP_KERNEL); + + if (all_strbuff != NULL) { + memset(all_strbuff, 0, size); + snprintf(all_strbuff, size, "ms_differ\n"); + if (res >= OK) { + for (j = 0; j < frame.node_data_size; j++) { + if ((j + 1) % frame.header.sense_node) + snprintf(buff, sizeof(buff), "%4d,", + frame.node_data[j]); + else + snprintf(buff, sizeof(buff), "%4d\n", + frame.node_data[j]); + + strlcat(all_strbuff, buff, size); + } + + kfree(frame.node_data); + frame.node_data = NULL; + } + + count = snprintf(buf, PAGE_SIZE, "%s\n", all_strbuff); + kfree(all_strbuff); + } else { + logError(1, + "%s %s: Unable to allocate all_strbuff! ERROR %08X\n", + tag, __func__, ERROR_ALLOC); + } + +END: + fts_enableInterrupt(); + + return count; +} + +int fts_hover_auto_tune(struct fts_ts_info *info) +{ + int res = OK; + u8 sett[2]; + logError(0, "%s start...\n", tag, __func__); + + fts_disableInterrupt(); + + sett[0] = 0x02; + sett[1] = 0x00; + res = writeSysCmd(SYS_CMD_SPECIAL_TUNING, sett, 2); + if (res < OK) { + logError( + 1, + "%s fts_hover_autotune Ioffset tuning 02 00 failed ERROR %08X\n", + tag, (res | ERROR_PROD_TEST_INITIALIZATION)); + return res | ERROR_PROD_TEST_INITIALIZATION; + } + sett[0] = 0x00; + sett[1] = 0x01; + res = writeSysCmd(SYS_CMD_CX_TUNING, sett, 2); + if (res < OK) { + logError( + 1, + "%s fts_hover_autotune autotune hover 00 01 failed ERROR %08X\n", + tag, (res | ERROR_PROD_TEST_INITIALIZATION)); + return res | ERROR_PROD_TEST_INITIALIZATION; + } + sett[0] = 0x06; + res = writeSysCmd(SYS_CMD_SAVE_FLASH, sett, 1); + if (res < OK) { + logError( + 1, + "%s fts_hover_autotune save flash 06 failed ERROR %08X\n", + tag, (res | ERROR_PROD_TEST_INITIALIZATION)); + return res | ERROR_PROD_TEST_INITIALIZATION; + } + logError(0, "%s end...\n", tag, __func__); + + fts_enableInterrupt(); + + return res; +} + +static ssize_t fts_hover_autotune_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + int on; + int ret = 0; + + sscanf(buf, "%u", &on); + logError(1, " %s %s\n", tag, __func__); + if (on) + ret = fts_hover_auto_tune(info); + if (ret < OK) + return -1; + + return count; +} + +static ssize_t fts_hover_raw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int res = 0, count = 0, j = 0, sense_node = 0, force_node = 0, pos = 0, + last_pos = 0; + char *all_strbuff = NULL; + struct i2c_client *client = to_i2c_client(dev); + struct fts_ts_info *info = i2c_get_clientdata(client); + SelfSenseFrame frameSS; + TotSelfSenseData ssHoverCompData; + u8 hover_cnt[4] = { 0xa8, 0x0b, 0x01, 0x00 }; + + res = fts_disableInterrupt(); + if (res < OK) + goto END; + all_strbuff = vmalloc(PAGE_SIZE * 4); + if (!all_strbuff) { + logError(1, "%s %s alloc all_strbuff fail\n", tag, __func__); + goto END; + } else { + memset(all_strbuff, 0, PAGE_SIZE); + } + res = fts_write_dma_safe(hover_cnt, sizeof(hover_cnt)); + if (res != OK) { + logError(1, "%s hover clear count ERROR = %d\n", tag, res); + goto END; + } + + setScanMode(SCAN_MODE_ACTIVE, 0xFF); + + res = getSSFrame3(SS_HVR_RAW, &frameSS); + + sense_node = frameSS.header.sense_node; + force_node = frameSS.header.force_node; + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SsHoverTouchRaw,%2d,%2d\n", force_node, sense_node); + last_pos = pos; + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, "TxRaw\n"); + last_pos = pos; + + if (res >= OK) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover force frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.force_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.force_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.force_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.force_data[j]); + last_pos = pos; + } + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover sense frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.sense_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.sense_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.sense_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.sense_data[j]); + last_pos = pos; + } + + if (frameSS.force_data) { + kfree(frameSS.force_data); + frameSS.force_data = NULL; + } + if (frameSS.sense_data) { + kfree(frameSS.sense_data); + frameSS.sense_data = NULL; + } + } + + res = getSSFrame3(SS_HVR_FILTER, &frameSS); + + sense_node = frameSS.header.sense_node; + force_node = frameSS.header.force_node; + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, "TxFilter\n"); + last_pos = pos; + + if (res >= OK) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover force frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.force_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.force_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.force_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.force_data[j]); + last_pos = pos; + } + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover sense frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.sense_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.sense_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.sense_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.sense_data[j]); + last_pos = pos; + } + + if (frameSS.force_data) { + kfree(frameSS.force_data); + frameSS.force_data = NULL; + } + if (frameSS.sense_data) { + kfree(frameSS.sense_data); + frameSS.sense_data = NULL; + } + } + + res = getSSFrame3(SS_HVR_BASELINE, &frameSS); + + sense_node = frameSS.header.sense_node; + force_node = frameSS.header.force_node; + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, "TxBaseline\n"); + last_pos = pos; + + if (res >= OK) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover force frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.force_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.force_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.force_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.force_data[j]); + last_pos = pos; + } + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover sense frame\n ,"); + last_pos = pos; + + for (j = 0; j < frameSS.header.sense_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d,", frameSS.sense_data[j]); + last_pos = pos; + } + + if (j == frameSS.header.sense_node - 1) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "%04d\n", frameSS.sense_data[j]); + last_pos = pos; + } + + if (frameSS.force_data) { + kfree(frameSS.force_data); + frameSS.force_data = NULL; + } + + if (frameSS.sense_data) { + kfree(frameSS.sense_data); + frameSS.sense_data = NULL; + } + } + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover IX Data\n ,"); + last_pos = pos; + + res = readTotSelfSenseCompensationData( + STAPI_HOST_DATA_ID_PANEL_CX_SS_HVR, &ssHoverCompData); + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "SS Hover IX force frame\n ,"); + last_pos = pos; + for (j = 0; j < ssHoverCompData.header.force_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, "%04d,", + ssHoverCompData.ix_fm[j]); + last_pos = pos; + } + + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, + "\nSS Hover IX sense frame\n ,"); + last_pos = pos; + + for (j = 0; j < ssHoverCompData.header.sense_node - 1; j++) { + pos += snprintf(all_strbuff + last_pos, PAGE_SIZE, "%04d,", + ssHoverCompData.ix_sn[j]); + last_pos = pos; + } + + if (ssHoverCompData.ix_fm != NULL) + kfree(ssHoverCompData.ix_fm); + if (ssHoverCompData.ix_sn != NULL) + kfree(ssHoverCompData.ix_sn); + if (ssHoverCompData.cx_fm != NULL) + kfree(ssHoverCompData.cx_fm); + if (ssHoverCompData.cx_sn != NULL) + kfree(ssHoverCompData.cx_sn); + + count = snprintf(buf, PAGE_SIZE, "%s\n", all_strbuff); + vfree(all_strbuff); +END: + fts_mode_handler(info, 1); + fts_enableInterrupt(); + return count; +} + +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP +static ssize_t fts_touch_suspend_notify_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", fts_info->sensor_sleep); +} +#endif + +static ssize_t fts_doze_time_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + + return snprintf(buf, TSP_BUF_SIZE, "%u\n", info->doze_time); +} + +static ssize_t fts_doze_time_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 cmd[4] = { FTS_CMD_CUSTOM, 0x00, 0x00, 0x00 }; + int ret = 0; + u16 reg_val = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + pr_info("%s,buf:%s,count:%zu\n", __func__, buf, count); + sscanf(buf, "%u", &info->doze_time); + /*reg value * 10 represents of the num of frames ,one frame is about 8ms, the input value is ms*/ + reg_val = (info->doze_time / 8 - 1) / 10; + cmd[3] = reg_val; + ret = fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)); + if (ret < OK) { + logError(1, "%s %s: write failed...ERROR %08X !\n", tag, + __func__, ret); + return -EPERM; + } + return count; +} + +static ssize_t fts_grip_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + + return snprintf(buf, TSP_BUF_SIZE, "%d\n", info->grip_enabled); +} + +static ssize_t fts_grip_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 cmd[3] = { FTS_CMD_FEATURE, 0x04, 0x01 }; + int ret = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + pr_info("%s,buf:%s,count:%zu\n", __func__, buf, count); + sscanf(buf, "%u", &info->grip_enabled); + cmd[2] = info->grip_enabled; + ret = fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)); + if (ret < OK) { + logError(1, "%s %s: write failed...ERROR %08X !\n", tag, + __func__, ret); + return -EPERM; + } + return count; +} + +static ssize_t fts_grip_area_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + + return snprintf(buf, TSP_BUF_SIZE, "%d\n", info->grip_pixel); +} + +static ssize_t fts_grip_area_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 cmd[4] = { FTS_CMD_CUSTOM, 0x01, 0x01, 0x00 }; + int ret = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(1, " %s %s,buf:%s,count:%zu\n", tag, __func__, buf, count); + sscanf(buf, "%u", &info->grip_pixel); + cmd[3] = info->grip_pixel; + if (atomic_read(&info->system_is_resetting)) { + logError(1, "%s %s system is resetting ,wait reset done\n", tag, + __func__); + ret = wait_for_completion_timeout(&info->tp_reset_completion, + msecs_to_jiffies(40)); + if (!ret) { + logError( + 1, + "%s %s wait tp reset timeout, wrtie grip area error\n", + tag, __func__); + return count; + } + } + ret = fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)); + if (ret < OK) { + logError(1, "%s %s: write failed...ERROR %08X !\n", tag, + __func__, ret); + return -EPERM; + } + return count; +} +#ifdef CONFIG_FTS_FOD_AREA_REPORT +static ssize_t fts_fod_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + + return snprintf(buf, TSP_BUF_SIZE, "%d\n", info->fod_status); +} + +static ssize_t fts_fod_status_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + int res = 0; + u8 gesture_cmd[6] = { 0xA2, 0x03, 0x20, 0x00, 0x00, 0x01 }; + u8 single_only_cmd[4] = { 0xC0, 0x02, 0x00, 0x00 }; + u8 single_double_cmd[4] = { 0xC0, 0x02, 0x01, 0x1E }; + + logError(1, " %s %s buf:%c,count:%zu\n", tag, __func__, buf[0], count); + sscanf(buf, "%u", &info->fod_status); + + mutex_lock(&info->fod_mutex); + if (info->fod_status) { + if (info->fod_status_set) { + logError(1, " %s %s fod status has set\n", tag, + __func__); + } else { + res = fts_write_dma_safe(gesture_cmd, + ARRAY_SIZE(gesture_cmd)); + if (res < OK) + logError( + 1, + "%s %s: enter gesture and longpress failed! ERROR %08X recovery in senseOff...\n", + tag, __func__, res); + + if (info->sensor_sleep) { + logError( + 1, + " %s %s set fod cmd in sensor off status\n", + tag, __func__); + res = setScanMode(SCAN_MODE_LOW_POWER, 0); + if (info->gesture_enabled == 1) { + res = fts_write_dma_safe( + single_double_cmd, + ARRAY_SIZE(single_double_cmd)); + if (res < OK) + logError( + 1, + "%s %s: set single and double tap delay time failed! ERROR %08X\n", + tag, __func__, res); + } else { + res = fts_write_dma_safe( + single_only_cmd, + ARRAY_SIZE(single_only_cmd)); + if (res < OK) + logError( + 1, + "%s %s: set single only delay time failed! ERROR %08X\n", + tag, __func__, res); + } + } + fts_enableInterrupt(); + info->fod_status_set = true; + } + } + mutex_unlock(&info->fod_mutex); + logError(1, " %s %s end\n", tag, __func__); + + return count; +} + +static ssize_t fts_fod_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int value = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); + + logError(1, " %s %s,buf:%s,count:%zu\n", tag, __func__, buf, count); + sscanf(buf, "%u", &value); + if (value) { + input_report_key(info->input_dev, BTN_INFO, 1); + input_report_key(info->input_dev, KEY_INFO, 1); + info->fod_pressed = true; + input_sync(info->input_dev); + input_mt_slot(info->input_dev, 0); + input_mt_report_slot_state(info->input_dev, MT_TOOL_FINGER, 1); + input_report_key(info->input_dev, BTN_TOUCH, 1); + input_report_key(info->input_dev, BTN_TOOL_FINGER, 1); + input_report_abs(info->input_dev, ABS_MT_TRACKING_ID, 0); + input_report_abs(info->input_dev, ABS_MT_WIDTH_MINOR, 1); + input_report_abs(info->input_dev, ABS_MT_POSITION_X, CENTER_X); + input_report_abs(info->input_dev, ABS_MT_POSITION_Y, CENTER_Y); + input_sync(info->input_dev); + } else { + input_mt_slot(info->input_dev, 0); + input_report_abs(info->input_dev, ABS_MT_WIDTH_MINOR, 0); + input_mt_report_slot_state(info->input_dev, MT_TOOL_FINGER, 0); + input_report_abs(info->input_dev, ABS_MT_TRACKING_ID, -1); + input_report_key(info->input_dev, BTN_INFO, 0); + input_report_key(info->input_dev, KEY_INFO, 0); + input_sync(info->input_dev); + } + return count; +} +#endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +static ssize_t fts_touchgame_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 get_value[7] = { + 0x0, + }; + u8 get_cmd[2] = { 0xc1, 0x05 }; + u8 grip_rcmd[2] = { 0xc1, 0x08 }; + u8 grip_value[7] = { + 0x0, + }; + int ret; + + ret = fts_writeRead_dma_safe(get_cmd, sizeof(get_cmd) / sizeof(u8), + get_value, sizeof(get_value) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading touchmode data ERROR %08X\n", + tag, __func__, ret); + } + ret = fts_writeRead_dma_safe(grip_rcmd, sizeof(grip_rcmd) / sizeof(u8), + grip_value, + sizeof(grip_value) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading edge filter data ERROR %08X\n", + tag, __func__, ret); + } + + return snprintf(buf, PAGE_SIZE, + "game mode:%d,%d,%d,%d,%d,%d,%d\n" + "grip mode:0x%x, 0x%x, 0x%x, %d, %d, %d, %d\n", + get_value[0], get_value[1], get_value[2], get_value[3], + get_value[4], get_value[5], get_value[6], grip_value[0], + grip_value[1], grip_value[2], grip_value[3], + grip_value[4], grip_value[5], grip_value[6]); +} +#endif + +#ifdef CONFIG_SECURE_TOUCH +static void fts_secure_touch_notify(struct fts_ts_info *info) +{ + /*might sleep*/ + sysfs_notify(&info->dev->kobj, NULL, "secure_touch"); + logError(1, "%s %s SECURE_NOTIFY:notify secure_touch\n", tag, __func__); +} + +static int fts_secure_stop(struct fts_ts_info *info, bool block) +{ + struct fts_secure_info *scr_info = info->secure_info; + + logError(1, "%s %s SECURE_STOP: block = %d\n", tag, __func__, + (int)block); + if (atomic_read(&scr_info->st_enabled) == 0) { + logError(1, "%s %s secure touch is already disabled\n", tag, + __func__); + return OK; + } + + atomic_set(&scr_info->st_pending_irqs, -1); + fts_secure_touch_notify(info); + if (block) { + if (wait_for_completion_interruptible( + &scr_info->st_powerdown) == -ERESTARTSYS) { + logError( + 1, + "%s %s SECURE_STOP:st_powerdown be interrupted\n", + tag, __func__); + } else { + logError( + 1, + "%s %s SECURE_STOP:st_powerdown be completed\n", + tag, __func__); + } + } + return OK; +} + +static void fts_secure_work(struct fts_secure_info *scr_info) +{ + struct fts_ts_info *info = (struct fts_ts_info *)scr_info->fts_info; + + fts_secure_touch_notify(info); + atomic_set(&scr_info->st_1st_complete, 1); + if (wait_for_completion_interruptible(&scr_info->st_irq_processed) == + -ERESTARTSYS) { + logError( + 1, + "%s %s SECURE_FILTER:st_irq_processed be interrupted\n", + tag, __func__); + } else { + logError(1, + "%s %s SECURE_FILTER:st_irq_processed be completed\n", + tag, __func__); + } + + fts_enableInterrupt(); + logError(1, "%s %s SECURE_FILTER:enable irq\n", tag, __func__); +} + +static void fts_palm_store_delay(struct fts_secure_info *scr_info) +{ + int ret; + struct fts_ts_info *info = scr_info->fts_info; + + logError(1, "%s %s IN", tag, __func__); + ret = fts_palm_sensor_cmd(scr_info->scr_delay.palm_value); + if (!ret) + info->palm_sensor_changed = true; + logError(1, "%s %s OUT", tag, __func__); +} + +static void fts_flush_delay_task(struct fts_secure_info *scr_info) +{ + if (scr_info->scr_delay.palm_pending) { + fts_palm_store_delay(scr_info); + scr_info->scr_delay.palm_pending = false; + } +} + +static int fts_secure_filter_interrupt(struct fts_ts_info *info) +{ + struct fts_secure_info *scr_info = info->secure_info; + + /*inited and enable first*/ + if (!scr_info->secure_inited || + atomic_read(&scr_info->st_enabled) == 0) { + return -EPERM; + } + + fts_disableInterruptNoSync(); + logError(1, "%s %s SECURE_FILTER:disable irq\n", tag, __func__); + /*check and change irq pending state + *change irq pending here, secure_touch_show, secure_touch_enable_store + *completion st_irq_processed at secure_touch_show, secure_touch_enable_stroe + */ + logError(1, "%s %s SECURE_FILTER:st_pending_irqs = %d\n", tag, __func__, + atomic_read(&scr_info->st_pending_irqs)); + if (atomic_cmpxchg(&scr_info->st_pending_irqs, 0, 1) == 0) { + fts_secure_work(scr_info); + logError(1, "%s %s SECURE_FILTER:secure_work return\n", tag, + __func__); + } + + return 0; +} + +static ssize_t fts_secure_touch_enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + struct fts_secure_info *scr_info = info->secure_info; + + logError(1, "%s %s SECURE_TOUCH_ENABLE[R]:st_enabled = %d\n", tag, + __func__, atomic_read(&scr_info->st_enabled)); + return scnprintf(buf, PAGE_SIZE, "%d", + atomic_read(&scr_info->st_enabled)); +} + +/* echo 0 > secure_touch_enable to disable secure touch + * echo 1 > secure_touch_enable to enable secure touch + */ +static ssize_t fts_secure_touch_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned long value; + struct fts_ts_info *info = dev_get_drvdata(dev); + struct fts_secure_info *scr_info = info->secure_info; + + atomic_set(&scr_info->st_1st_complete, 0); + logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:st_1st_complete=0\n", tag, + __func__); + logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:parse parameter\n", tag, + __func__); + /*check and get cmd*/ + if (count > 2) + return -EINVAL; + ret = kstrtoul(buf, 10, &value); + if (ret != 0) + return ret; + + if (!scr_info->secure_inited) + return -EIO; + + ret = count; + + logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:st_enabled = %d\n", tag, + __func__, value); + switch (value) { + case 0: + if (atomic_read(&scr_info->st_enabled) == 0) { + logError(1, "%s %s secure touch is already disabled\n", + tag, __func__); + return ret; + } + mutex_lock(&scr_info->palm_lock); + atomic_set(&scr_info->st_enabled, 0); + fts_secure_touch_notify(info); + complete(&scr_info->st_irq_processed); + fts_event_handler(info->client->irq, info); + complete(&scr_info->st_powerdown); + fts_flush_delay_task(scr_info); + mutex_unlock(&scr_info->palm_lock); + logError( + 1, + "%s %s SECURE_TOUCH_ENABLE[W]:disable secure touch successful\n", + tag, __func__); + break; + case 1: + if (atomic_read(&scr_info->st_enabled) == 1) { + logError(1, "%s %s secure touch is already enabled\n", + tag, __func__); + return ret; + } + mutex_lock(&scr_info->palm_lock); + /*wait until finish process all normal irq*/ + synchronize_irq(info->client->irq); + + /*enable secure touch*/ + reinit_completion(&scr_info->st_powerdown); + reinit_completion(&scr_info->st_irq_processed); + atomic_set(&scr_info->st_pending_irqs, 0); + atomic_set(&scr_info->st_enabled, 1); + mutex_unlock(&scr_info->palm_lock); + logError( + 1, + "%s %s SECURE_TOUCH_ENABLE[W]:enable secure touch successful\n", + tag, __func__); + break; + default: + logError(1, "%s %s %d in secure_touch_enable is not support\n", + tag, __func__, value); + break; + } + return ret; +} + +static ssize_t fts_secure_touch_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + struct fts_secure_info *scr_info = info->secure_info; + int value = 0; + + logError(1, "%s %s SECURE_TOUCH[R]:st_1st_complete = %d\n", tag, + __func__, atomic_read(&scr_info->st_1st_complete)); + logError(1, "%s %s SECURE_TOUCH[R]:st_pending_irqs = %d\n", tag, + __func__, atomic_read(&scr_info->st_pending_irqs)); + + if (atomic_read(&scr_info->st_enabled) == 0) { + return -EBADF; + } + + if (atomic_cmpxchg(&scr_info->st_pending_irqs, -1, 0) == -1) + return -EINVAL; + + if (atomic_cmpxchg(&scr_info->st_pending_irqs, 1, 0) == 1) { + value = 1; + } else if (atomic_cmpxchg(&scr_info->st_1st_complete, 1, 0) == 1) { + complete(&scr_info->st_irq_processed); + logError(1, + "%s %s SECURE_TOUCH[R]:comlpetion st_irq_processed\n", + tag, __func__); + } + return scnprintf(buf, PAGE_SIZE, "%d", value); +} +#endif +static DEVICE_ATTR(fts_lockdown, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_lockdown_show, fts_lockdown_store); +static DEVICE_ATTR(fwupdate, (S_IRUGO | S_IWUSR | S_IWGRP), fts_fwupdate_show, + fts_fwupdate_store); +static DEVICE_ATTR(panel_vendor, (S_IRUGO), fts_panel_vendor_show, NULL); +static DEVICE_ATTR(panel_color, (S_IRUGO), fts_panel_color_show, NULL); +static DEVICE_ATTR(panel_display, (S_IRUGO), fts_panel_display_show, NULL); +static DEVICE_ATTR(ms_strength, (S_IRUGO), fts_strength_frame_show, NULL); +static DEVICE_ATTR(lockdown_info, (S_IRUGO), fts_lockdown_info_show, NULL); +static DEVICE_ATTR(appid, (S_IRUGO), fts_appid_show, NULL); +static DEVICE_ATTR(mode_active, (S_IRUGO), fts_mode_active_show, NULL); +static DEVICE_ATTR(fw_file_test, (S_IRUGO), fts_fw_test_show, NULL); +static DEVICE_ATTR(selftest_info, (S_IRUGO), fts_selftest_info_show, NULL); +static DEVICE_ATTR(ms_raw, (S_IRUGO), fts_ms_raw_show, NULL); +static DEVICE_ATTR(ss_raw, (S_IRUGO), fts_ss_raw_show, NULL); +static DEVICE_ATTR(ms_cx_total, (S_IRUGO), fts_ms_cx_total_show, NULL); +static DEVICE_ATTR(ss_ix_total, (S_IRUGO), fts_ss_ix_total_show, NULL); +static DEVICE_ATTR(ss_hover, (S_IRUGO), fts_hover_raw_show, NULL); +static DEVICE_ATTR(stm_fts_cmd, (S_IRUGO | S_IWUSR | S_IWGRP), stm_fts_cmd_show, + stm_fts_cmd_store); +#ifdef USE_ONE_FILE_NODE +static DEVICE_ATTR(feature_enable, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_feature_enable_show, fts_feature_enable_store); +#else + +#ifdef GRIP_MODE +static DEVICE_ATTR(grip_mode, (S_IRUGO | S_IWUSR | S_IWGRP), fts_grip_mode_show, + fts_grip_mode_store); +#endif + +#ifdef CHARGER_MODE +static DEVICE_ATTR(charger_mode, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_charger_mode_show, fts_charger_mode_store); +#endif + +#ifdef GLOVE_MODE +static DEVICE_ATTR(glove_mode, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_glove_mode_show, fts_glove_mode_store); +#endif + +#ifdef COVER_MODE +static DEVICE_ATTR(cover_mode, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_cover_mode_show, fts_cover_mode_store); +#endif + +#ifdef STYLUS_MODE +static DEVICE_ATTR(stylus_mode, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_stylus_mode_show, fts_stylus_mode_store); +#endif + +#endif + +#ifdef GESTURE_MODE +static DEVICE_ATTR(gesture_mask, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_gesture_mask_show, fts_gesture_mask_store); +static DEVICE_ATTR(gesture_coordinates, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_gesture_coordinates_show, NULL); +#endif +static DEVICE_ATTR(doze_time, (S_IRUGO | S_IWUSR | S_IWGRP), fts_doze_time_show, + fts_doze_time_store); +static DEVICE_ATTR(grip_enable, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_grip_enable_show, fts_grip_enable_store); +static DEVICE_ATTR(grip_area, (S_IRUGO | S_IWUSR | S_IWGRP), fts_grip_area_show, + fts_grip_area_store); + +static DEVICE_ATTR(hover_tune, (S_IRUGO | S_IWUSR | S_IWGRP), NULL, + fts_hover_autotune_store); + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +static DEVICE_ATTR(touchgame, (S_IRUGO | S_IWUSR | S_IWGRP), fts_touchgame_show, + NULL); +#endif +static struct attribute *fts_attr_group[] = { + &dev_attr_fwupdate.attr, + &dev_attr_appid.attr, + &dev_attr_mode_active.attr, + &dev_attr_fw_file_test.attr, + &dev_attr_stm_fts_cmd.attr, +#ifdef USE_ONE_FILE_NODE + &dev_attr_feature_enable.attr, +#else + +#ifdef GRIP_MODE + &dev_attr_grip_mode.attr, +#endif +#ifdef CHARGER_MODE + &dev_attr_charger_mode.attr, +#endif +#ifdef GLOVE_MODE + &dev_attr_glove_mode.attr, +#endif +#ifdef COVER_MODE + &dev_attr_cover_mode.attr, +#endif +#ifdef STYLUS_MODE + &dev_attr_stylus_mode.attr, +#endif +#endif + &dev_attr_fts_lockdown.attr, + &dev_attr_panel_vendor.attr, + &dev_attr_panel_color.attr, + &dev_attr_panel_display.attr, + &dev_attr_lockdown_info.attr, +#ifdef GESTURE_MODE + &dev_attr_gesture_mask.attr, + &dev_attr_gesture_coordinates.attr, +#endif + &dev_attr_selftest_info.attr, + &dev_attr_ms_raw.attr, + &dev_attr_ss_raw.attr, + &dev_attr_ms_cx_total.attr, + &dev_attr_ss_ix_total.attr, + &dev_attr_ms_strength.attr, + &dev_attr_ss_hover.attr, + &dev_attr_hover_tune.attr, + &dev_attr_doze_time.attr, + &dev_attr_grip_enable.attr, + &dev_attr_grip_area.attr, +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + &dev_attr_touchgame.attr, +#endif + NULL, +}; + +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP +static DEVICE_ATTR(touch_suspend_notify, (S_IRUGO | S_IRGRP), + fts_touch_suspend_notify_show, NULL); +#endif +#ifdef CONFIG_FTS_FOD_AREA_REPORT +static DEVICE_ATTR(fod_status, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_fod_status_show, fts_fod_status_store); + +static DEVICE_ATTR(fod_test, (S_IRUGO | S_IWUSR | S_IWGRP), NULL, + fts_fod_test_store); +#endif + +#ifdef CONFIG_SECURE_TOUCH +DEVICE_ATTR(secure_touch_enable, (S_IRUGO | S_IWUSR | S_IWGRP), + fts_secure_touch_enable_show, fts_secure_touch_enable_store); +DEVICE_ATTR(secure_touch, (S_IRUGO | S_IWUSR | S_IWGRP), fts_secure_touch_show, + NULL); +#endif +/**@}*/ +/**@}*/ + +/** + * @defgroup isr Interrupt Service Routine (Event Handler) + * The most important part of the driver is the ISR (Interrupt Service Routine) called also as Event Handler \n + * As soon as the interrupt pin goes low, fts_interrupt_handler() is called and the chain to read and parse the event read from the FIFO start.\n + * For any different kind of EVT_ID there is a specific event handler which will take the correct action to report the proper info to the host. \n + * The most important events are the one related to touch informations, status update or user report. + * @{ + */ + +/** + * Report to the linux input system the pressure and release of a button handling concurrency + * @param info pointer to fts_ts_info which contains info about the device and its hw setup + * @param key_code button value + */ +void fts_input_report_key(struct fts_ts_info *info, int key_code) +{ + mutex_lock(&info->input_report_mutex); + input_report_key(info->input_dev, key_code, 1); + input_sync(info->input_dev); + input_report_key(info->input_dev, key_code, 0); + input_sync(info->input_dev); + mutex_unlock(&info->input_report_mutex); +} + +/** +* Event Handler for no events (EVT_ID_NOEVENT) +*/ +static void fts_nop_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + logError( + 1, + "%s %s Doing nothing for event = %02X %02X %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[0], event[1], event[2], event[3], event[4], + event[5], event[6], event[7]); +} + +#ifdef CONFIG_FTS_FOD_AREA_REPORT +static bool fts_is_in_fodarea(int x, int y) +{ + if ((x > FOD_LX && x < FOD_LX + FOD_SIDE) && + (y > FOD_LY && y < FOD_LY + FOD_SIDE)) + return true; + else + return false; +} + +static bool finger_report_flag; + +#endif +/** +* Event handler for enter and motion events (EVT_ID_ENTER_POINT, EVT_ID_MOTION_POINT ) +* report to the linux input system touches with their coordinated and additional informations +*/ +static void fts_enter_pointer_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + unsigned char touchId; + unsigned int touch_condition = 1, tool = MT_TOOL_FINGER; + int x, y, z, distance; + u8 touchType; + int area_size; +#ifndef CONFIG_FTS_FOD_AREA_REPORT + if (!info->resume_bit) + goto no_report; +#endif + if (info->sensor_sleep) { + logError(1, "%s %s sensor sleep, skip touch down event\n", tag, + __func__); + return; + } + touchType = event[1] & 0x0F; + touchId = (event[1] & 0xF0) >> 4; + + x = (((int)event[3] & 0x0F) << 8) | (event[2]); + y = ((int)event[4] << 4) | ((event[3] & 0xF0) >> 4); + + z = 1; + distance = 0; + + if (event[0] == EVT_ID_MOTION_POINT) { + area_size = (event[5] << 8) | event[6]; + } else { + area_size = 1; + } + + if (x >= info->board->x_max) + x = info->board->x_max; + + if (y >= info->board->y_max) + y = info->board->y_max; +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + info->coor[touchId][0] = x; + info->coor[touchId][1] = y; +/* + if (fts_touchmode_edgefilter(touchId, x, y)) + return; +*/ +#endif + + input_mt_slot(info->input_dev, touchId); + switch (touchType) { +#ifdef STYLUS_MODE + case TOUCH_TYPE_STYLUS: + logError(0, "%s %s : It is a stylus!\n", tag, __func__); + if (info->stylus_enabled == 1) { + tool = MT_TOOL_PEN; + touch_condition = 1; + __set_bit(touchId, &info->stylus_id); + break; + } +#endif + case TOUCH_TYPE_FINGER: + /*logError(0, "%s %s : It is a finger!\n",tag,__func__); */ + case TOUCH_TYPE_GLOVE: + /*logError(0, "%s %s : It is a glove!\n",tag,__func__); */ + case TOUCH_TYPE_PALM: + /*logError(0, "%s %s : It is a palm!\n",tag,__func__); */ + tool = MT_TOOL_FINGER; + touch_condition = 1; + __set_bit(touchId, &info->touch_id); + break; + + case TOUCH_TYPE_HOVER: + tool = MT_TOOL_FINGER; + touch_condition = 0; + z = 0; + __set_bit(touchId, &info->touch_id); + distance = DISTANCE_MAX; + break; + + case TOUCH_TYPE_INVALID: + default: + logError(1, "%s %s : Invalid touch type = %d ! No Report...\n", + tag, __func__, touchType); +#ifndef CONFIG_FTS_FOD_AREA_REPORT + goto no_report; +#endif + } + + input_mt_report_slot_state(info->input_dev, tool, 1); + input_report_key(info->input_dev, BTN_TOUCH, touch_condition); + if (touch_condition) + input_report_key(info->input_dev, BTN_TOOL_FINGER, 1); + + /*input_report_abs(info->input_dev, ABS_MT_TRACKING_ID, touchId); */ + input_report_abs(info->input_dev, ABS_MT_POSITION_X, x); + input_report_abs(info->input_dev, ABS_MT_POSITION_Y, y); + input_report_abs(info->input_dev, ABS_MT_TOUCH_MINOR, z); + input_report_abs(info->input_dev, ABS_MT_DISTANCE, distance); + input_report_abs(info->input_dev, ABS_MT_TOUCH_MAJOR, area_size); +#ifdef CONFIG_FTS_FOD_AREA_REPORT + if (fts_is_in_fodarea(x, y) && !(info->fod_id & ~(1 << touchId))) { + __set_bit(touchId, &info->sleep_finger); + if (info->fod_status) { + info->fod_x = x; + info->fod_y = y; + info->fod_coordinate_update = true; + __set_bit(touchId, &info->fod_id); + input_report_abs(info->input_dev, ABS_MT_WIDTH_MINOR, + info->fod_overlap); + logError(1, "%s %s : FOD Press :%d, fod_id:%08x\n", + tag, __func__, touchId, info->fod_id); + } + } else if (__test_and_clear_bit(touchId, &info->fod_id)) { + input_report_abs(info->input_dev, ABS_MT_WIDTH_MINOR, 0); + input_report_key(info->input_dev, BTN_INFO, 0); + input_report_key(info->input_dev, KEY_INFO, 0); + info->fod_coordinate_update = false; + info->fod_overlap = 0; + logError(1, "%s %s : FOD Release :%d\n", tag, __func__, + touchId); + __clear_bit(touchId, &info->sleep_finger); + } +#endif + input_sync(info->input_dev); + dev_dbg(info->dev, + "%s %s : Event 0x%02x - ID[%d], (x, y, z) = (%3d, %3d, %3d) type = %d, size = %d, overlap:%d\n", + tag, __func__, *event, touchId, x, y, z, touchType, area_size, + info->fod_overlap); + if (event[0] == 0x13) + logError(1, "%s %s : Event 0x%02x - Press ID[%d] type = %d\n", + tag, __func__, event[0], touchId, touchType); + +#ifndef CONFIG_FTS_FOD_AREA_REPORT +no_report: + return; +#endif +} + +/** +* Event handler for leave event (EVT_ID_LEAVE_POINT ) +* Report to the linux input system that one touch left the display +*/ +static void fts_leave_pointer_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + unsigned char touchId = 0; + unsigned int tool = MT_TOOL_FINGER; + unsigned int touch_condition = 0; + u8 touchType; +#ifdef CONFIG_FTS_FOD_AREA_REPORT + int x, y; + bool fod_up = false; +#endif +#ifdef CONFIG_FTS_FOD_AREA_REPORT + if (event[1] == 0xb5) { + touchType = TOUCH_TYPE_FINGER; + info->sleep_finger = 0; + if (!info->fod_id) { + logError(1, "%s %s : FOD Release without FOD press\n", + tag, __func__); + goto exit; + } + if (info->touch_id) { + logError(1, "%s %s : FOD Release in active mode\n", + tag, __func__); + goto exit; + } + touchId = ffs(info->fod_id) - 1; + info->fod_overlap = 0; + + logError(1, "%s %s : FOD Release :%d, fod_id:%08x\n", tag, + __func__, touchId, info->fod_id); + + __clear_bit(touchId, &info->fod_id); + fod_up = true; + + } else { +#endif + touchType = event[1] & 0x0F; + touchId = (event[1] & 0xF0) >> 4; +#ifdef CONFIG_FTS_FOD_AREA_REPORT + } + x = (event[2] << 4) | (event[4] & 0xF0) >> 4; + y = (event[3] << 4) | (event[4] & 0x0F); +#endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + info->coor[touchId][0] = -1; + info->coor[touchId][1] = -1; +/* + if (test_bit(touchId, &info->touch_skip)) { + __clear_bit(touchId, &info->touch_skip); + return; + } +*/ +#endif + input_mt_slot(info->input_dev, touchId); + switch (touchType) { +#ifdef STYLUS_MODE + case TOUCH_TYPE_STYLUS: + logError(0, "%s %s : It is a stylus!\n", tag, __func__); + if (info->stylus_enabled == 1) { + tool = MT_TOOL_PEN; + __clear_bit(touchId, &info->stylus_id); + break; + } +#endif + + case TOUCH_TYPE_FINGER: + /*logError(0, "%s %s : It is a finger!\n",tag,__func__); */ + case TOUCH_TYPE_GLOVE: + /*logError(0, "%s %s : It is a glove!\n",tag,__func__); */ + case TOUCH_TYPE_PALM: + /*logError(0, "%s %s : It is a palm!\n",tag,__func__); */ + tool = MT_TOOL_FINGER; + touch_condition = 0; + __clear_bit(touchId, &info->touch_id); + break; + case TOUCH_TYPE_HOVER: + tool = MT_TOOL_FINGER; + touch_condition = 1; + __clear_bit(touchId, &info->touch_id); + break; + + case TOUCH_TYPE_INVALID: + default: + logError(1, "%s %s : Invalid touch type = %d ! No Report...\n", + tag, __func__, touchType); + return; + } +#ifdef CONFIG_FTS_FOD_AREA_REPORT + __clear_bit(touchId, &info->sleep_finger); + if (__test_and_clear_bit(touchId, &info->fod_id)) { + input_report_abs(info->input_dev, ABS_MT_WIDTH_MINOR, 0); + input_report_key(info->input_dev, BTN_INFO, 0); + input_report_key(info->input_dev, KEY_INFO, 0); + info->fod_coordinate_update = false; + } +#endif + input_mt_report_slot_state(info->input_dev, tool, 0); + if (info->touch_id == 0) { + input_report_key(info->input_dev, BTN_TOUCH, touch_condition); + lpm_disable_for_input(false); + if (!touch_condition) + input_report_key(info->input_dev, BTN_TOOL_FINGER, 0); +#ifdef CONFIG_FTS_FOD_AREA_REPORT + info->fod_pressed = false; + info->fod_overlap = 0; + input_report_key(info->input_dev, BTN_INFO, 0); + input_report_key(info->input_dev, KEY_INFO, 0); + finger_report_flag = false; +#endif + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + wake_up(&info->wait_queue); +#endif + info->touch_skip = 0; + info->sleep_finger = 0; + info->fod_id = 0; + } + input_report_abs(info->input_dev, ABS_MT_TRACKING_ID, -1); +#ifdef CONFIG_FTS_FOD_AREA_REPORT + if (fod_up) + logError(1, "%s %s : Event FOD - release ID[%d] type = %d\n", + tag, __func__, touchId, touchType); + else +#endif + logError(1, + "%s %s : Event 0x%02x - release ID[%d] type = %d\n", + tag, __func__, event[0], touchId, touchType); + + input_sync(info->input_dev); +#ifdef CONFIG_FTS_FOD_AREA_REPORT +exit: +#endif + return; +} + +/* EventId : EVT_ID_MOTION_POINT */ +#define fts_motion_pointer_event_handler fts_enter_pointer_event_handler + +/** +* Event handler for error events (EVT_ID_ERROR) +* Handle unexpected error events implementing recovery strategy and restoring the sensing status that the IC had before the error occured +*/ +static void fts_error_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + int error = 0; + logError( + 1, + "%s %s Received event %02X %02X %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[0], event[1], event[2], event[3], event[4], + event[5], event[6], event[7]); + + switch (event[1]) { + case EVT_TYPE_ERROR_ESD: { + release_all_touches(info); + + fts_chip_powercycle(info); + + error = fts_system_reset(); + error |= fts_mode_handler(info, 0); + error |= fts_enableInterrupt(); + if (error < OK) { + logError(1, + "%s %s Cannot restore the device ERROR %08X\n", + tag, __func__, error); + } + } break; + case EVT_TYPE_ERROR_WATCHDOG: { + dumpErrorInfo(NULL, 0); + release_all_touches(info); + error = fts_system_reset(); + error |= fts_mode_handler(info, 0); + error |= fts_enableInterrupt(); + if (error < OK) { + logError(1, + "%s %s Cannot reset the device ERROR %08X\n", + tag, __func__, error); + } + } break; + } +} + +/** +* Event handler for controller ready event (EVT_ID_CONTROLLER_READY) +* Handle controller events received after unexpected reset of the IC updating the resets flag and restoring the proper sensing status +*/ +static void fts_controller_ready_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + int error; + logError( + 1, + "%s %s Received event %02X %02X %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[0], event[1], event[2], event[3], event[4], + event[5], event[6], event[7]); + release_all_touches(info); + setSystemResetedUp(1); + setSystemResetedDown(1); + error = fts_mode_handler(info, 0); + if (error < OK) { + logError(1, + "%s %s Cannot restore the device status ERROR %08X\n", + tag, __func__, error); + } +} + +/** +* Event handler for status events (EVT_ID_STATUS_UPDATE) +* Handle status update events +*/ +static void fts_status_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + switch (event[1]) { + case EVT_TYPE_STATUS_ECHO: + logError( + 0, + "%s %s Echo event of command = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], event[5], + event[6], event[7]); + break; + + case EVT_TYPE_STATUS_FORCE_CAL: + switch (event[2]) { + case 0x00: + logError( + 1, + "%s %s Continuous frame drop Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x01: + logError( + 1, + "%s %s Mutual negative detect Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x02: + logError( + 1, + "%s %s Mutual calib deviation Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x11: + logError( + 1, + "%s %s SS negative detect Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x12: + logError( + 1, + "%s %s SS negative detect Force cal in Low Power mode = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x13: + logError( + 1, + "%s %s SS negative detect Force cal in Idle mode = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x20: + logError( + 1, + "%s %s SS invalid Mutual Strength soft Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x21: + logError( + 1, + "%s %s SS invalid Self Strength soft Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x22: + logError( + 1, + "%s %s SS invalid Self Island soft Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x30: + logError( + 1, + "%s %s MS invalid Mutual Strength soft Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x31: + logError( + 1, + "%s %s MS invalid Self Strength soft Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + default: + logError( + 1, + "%s %s Force cal = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + } + break; + + case EVT_TYPE_STATUS_FRAME_DROP: + switch (event[2]) { + case 0x01: + logError( + 1, + "%s %s Frame drop noisy frame = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x02: + logError( + 1, + "%s %s Frame drop bad R = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case 0x03: + logError( + 1, + "%s %s Frame drop invalid processing state = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + default: + logError( + 1, + "%s %s Frame drop = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + } + break; + + case EVT_TYPE_STATUS_SS_RAW_SAT: + if (event[2] == 1) + logError( + 1, + "%s %s SS Raw Saturated = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + else + logError( + 1, + "%s %s SS Raw No more Saturated = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; + + case EVT_TYPE_STATUS_WATER: + if (event[2] == 1) + logError( + 1, + "%s %s Enter Water mode = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + else + logError( + 1, + "%s %s Exit Water mode = %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[2], event[3], event[4], + event[5], event[6], event[7]); + break; +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + case EVT_TYPE_STATUS_POCKET: + if (event[0] == 0x43 && event[2] == 0x01) { + update_palm_sensor_value(1); + } else if (event[0] == 0x43 && event[2] == 0x00) { + update_palm_sensor_value(0); + } + break; +#endif + default: + logError( + 1, + "%s %s Received unhandled status event = %02X %02X %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[0], event[1], event[2], event[3], + event[4], event[5], event[6], event[7]); + break; + } +} + +#ifdef PHONE_KEY +/** + * Event handler for status events (EVT_TYPE_USER_KEY) + * Handle keys update events, the third byte of the event is a bitmask where if the bit set means that the corresponding key is pressed. + */ +static void fts_key_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + logError( + 0, + "%s %s Received event %02X %02X %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[0], event[1], event[2], event[3], event[4], + event[5], event[6], event[7]); + + if (event[0] == EVT_ID_USER_REPORT && event[1] == EVT_TYPE_USER_KEY) { + if ((event[2] & FTS_KEY_0) == 0 && (key_mask & FTS_KEY_0) > 0) { + logError(0, + "%s %s: Button HOME pressed and released! \n", + tag, __func__); + fts_input_report_key(info, KEY_HOMEPAGE); + } + + if ((event[2] & FTS_KEY_1) == 0 && (key_mask & FTS_KEY_1) > 0) { + logError(0, + "%s %s: Button Back pressed and released! \n", + tag, __func__); + fts_input_report_key(info, KEY_BACK); + } + + if ((event[2] & FTS_KEY_2) == 0 && (key_mask & FTS_KEY_2) > 0) { + logError(0, "%s %s: Button Menu pressed! \n", tag, + __func__); + fts_input_report_key(info, KEY_MENU); + } + + key_mask = event[2]; + } else { + logError(1, "%s %s: Invalid event passed as argument! \n", tag, + __func__); + } +} +#endif + +#ifdef GESTURE_MODE +/** + * Event handler for gesture events (EVT_TYPE_USER_GESTURE) + * Handle gesture events and simulate the click on a different button for any gesture detected (@link gesture_opt Gesture IDs @endlink) + */ +static void fts_gesture_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + int value; + int needCoords = 0; + char ch[64] = { + 0x0, + }; +#ifdef CONFIG_FTS_FOD_AREA_REPORT + int touch_area; + int fod_overlap; + int fod_id = 0; + int x = (event[4] << 8) | (event[3]); + int y = (event[6] << 8) | (event[5]); +#endif + + logError( + 1, + "%s gesture event data: %02X %02X %02X %02X %02X %02X %02X %02X\n", + tag, event[0], event[1], event[2], event[3], event[4], event[5], + event[6], event[7]); + if (event[0] == EVT_ID_USER_REPORT && + event[1] == EVT_TYPE_USER_GESTURE) { + needCoords = 1; +#ifdef CONFIG_FTS_FOD_AREA_REPORT + if (event[2] == GEST_ID_LONG_PRESS && info->fod_status) { + touch_area = (event[9] << 8) | (event[8]); + fod_overlap = (event[11] << 8) | (event[10]); + if ((!info->sensor_sleep && + info->fod_coordinate_update && info->fod_id && + fts_is_in_fodarea(info->fod_x, info->fod_y)) || + (info->sensor_sleep && fts_is_in_fodarea(x, y))) { + if (!finger_report_flag) { + logError( + 1, + "%s %s finger down in the fod area\n", + tag, __func__); + finger_report_flag = true; + } + info->fod_overlap = fod_overlap; + + if ((info->sensor_sleep && + !info->sleep_finger) || + !info->sensor_sleep) { + info->fod_pressed = true; + input_report_key(info->input_dev, + BTN_INFO, 1); + input_report_key(info->input_dev, + KEY_INFO, 1); + input_sync(info->input_dev); + if (info->fod_id) { + fod_id = ffs(info->fod_id) - 1; + if (info->fod_id & + ~(1 << fod_id)) + logError( + 1, + "%s %s multi fingers on fod area:%08x\n", + tag, __func__, + info->fod_id); + } else if (info->sensor_sleep) { + __set_bit(0, &info->fod_id); + } + + if (info->fod_coordinate_update || + info->sensor_sleep) { + input_mt_slot(info->input_dev, + fod_id); + input_mt_report_slot_state( + info->input_dev, + MT_TOOL_FINGER, 1); + input_report_key( + info->input_dev, + BTN_TOUCH, 1); + input_report_key( + info->input_dev, + BTN_TOOL_FINGER, 1); + if (info->sensor_sleep) { + input_report_abs( + info->input_dev, + ABS_MT_POSITION_X, + x); + input_report_abs( + info->input_dev, + ABS_MT_POSITION_Y, + y); + } else { + input_report_abs( + info->input_dev, + ABS_MT_POSITION_X, + info->fod_x); + input_report_abs( + info->input_dev, + ABS_MT_POSITION_Y, + info->fod_y); + info->fod_coordinate_update = + false; + } + input_report_abs( + info->input_dev, + ABS_MT_WIDTH_MAJOR, + touch_area); + input_report_abs( + info->input_dev, + ABS_MT_WIDTH_MINOR, + fod_overlap); + logError( + 1, + "%s %s id:%d, fod_id:%08x, touch_area:%d, overlap:%d,fod report\n", + tag, __func__, fod_id, + info->fod_id, + touch_area, + fod_overlap); + } + input_sync(info->input_dev); + } + } + goto gesture_done; + } else if (event[2] == GEST_ID_SINGTAP && info->fod_status) { + input_report_key(info->input_dev, KEY_GOTO, 1); + input_sync(info->input_dev); + input_report_key(info->input_dev, KEY_GOTO, 0); + input_sync(info->input_dev); + info->sleep_finger = 0; + info->fod_overlap = 0; + info->fod_pressed = false; + goto gesture_done; + } +#endif + switch (event[2]) { + case GEST_ID_DBLTAP: + if (!info->gesture_enabled) + goto gesture_done; + value = KEY_WAKEUP; + logError(0, "%s %s: double tap ! \n", tag, __func__); + info->dbclick_count++; + snprintf(ch, sizeof(ch), "%d", info->dbclick_count); + needCoords = 0; + break; + + case GEST_ID_AT: + value = KEY_WWW; + logError(0, "%s %s: @ ! \n", tag, __func__); + break; + + case GEST_ID_C: + value = KEY_C; + logError(0, "%s %s: C ! \n", tag, __func__); + break; + + case GEST_ID_E: + value = KEY_E; + logError(0, "%s %s: e ! \n", tag, __func__); + break; + + case GEST_ID_F: + value = KEY_F; + logError(0, "%s %s: F ! \n", tag, __func__); + break; + + case GEST_ID_L: + value = KEY_L; + logError(0, "%s %s: L ! \n", tag, __func__); + break; + + case GEST_ID_M: + value = KEY_M; + logError(0, "%s %s: M ! \n", tag, __func__); + break; + + case GEST_ID_O: + value = KEY_O; + logError(0, "%s %s: O ! \n", tag, __func__); + break; + + case GEST_ID_S: + value = KEY_S; + logError(0, "%s %s: S ! \n", tag, __func__); + break; + + case GEST_ID_V: + value = KEY_V; + logError(0, "%s %s: V ! \n", tag, __func__); + break; + + case GEST_ID_W: + value = KEY_W; + logError(0, "%s %s: W ! \n", tag, __func__); + break; + + case GEST_ID_Z: + value = KEY_Z; + logError(0, "%s %s: Z ! \n", tag, __func__); + break; + + case GEST_ID_RIGHT_1F: + value = KEY_RIGHT; + logError(0, "%s %s: -> ! \n", tag, __func__); + break; + + case GEST_ID_LEFT_1F: + value = KEY_LEFT; + logError(0, "%s %s: <- ! \n", tag, __func__); + break; + + case GEST_ID_UP_1F: + value = KEY_UP; + logError(0, "%s %s: UP ! \n", tag, __func__); + break; + + case GEST_ID_DOWN_1F: + value = KEY_DOWN; + logError(0, "%s %s: DOWN ! \n", tag, __func__); + break; + + case GEST_ID_CARET: + value = KEY_APOSTROPHE; + logError(0, "%s %s: ^ ! \n", tag, __func__); + break; + + case GEST_ID_LEFTBRACE: + value = KEY_LEFTBRACE; + logError(0, "%s %s: < ! \n", tag, __func__); + break; + + case GEST_ID_RIGHTBRACE: + value = KEY_RIGHTBRACE; + logError(0, "%s %s: > ! \n", tag, __func__); + break; + + default: + logError(0, "%s %s: No valid GestureID! \n", tag, + __func__); + goto gesture_done; + } + + if (needCoords == 1) + readGestureCoords(event); + + fts_input_report_key(info, value); + +gesture_done: + return; + } else { + logError(1, "%s %s: Invalid event passed as argument! \n", tag, + __func__); + } +} +#endif + +/** + * Event handler for user report events (EVT_ID_USER_REPORT) + * Handle user events reported by the FW due to some interaction triggered by an external user (press keys, perform gestures, etc.) + */ +static void fts_user_report_event_handler(struct fts_ts_info *info, + unsigned char *event) +{ + switch (event[1]) { +#ifdef PHONE_KEY + case EVT_TYPE_USER_KEY: + fts_key_event_handler(info, event); + break; +#endif + + case EVT_TYPE_USER_PROXIMITY: + if (event[2] == 0) { + logError(1, "%s %s No proximity!\n", tag, __func__); + } else { + logError(1, "%s %s Proximity Detected!\n", tag, + __func__); + } + break; + +#ifdef GESTURE_MODE + case EVT_TYPE_USER_GESTURE: + fts_gesture_event_handler(info, event); + break; +#endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + case EVT_TYPE_USER_EARDET: + if (event[2] == 0xAA) { + logError(1, "%s %s hover ear enter\n", tag, __func__); + update_p_sensor_value(1); + } else if (event[2] == 0xBB) { + logError(1, "%s %s hover leave\n", tag, __func__); + update_p_sensor_value(0); + } else if (event[2] == 0xCC) { + logError(1, "%s %s hover palm enter\n", tag, __func__); + update_p_sensor_value(2); + } + break; +#endif + default: + logError( + 1, + "%s %s Received unhandled user report event = %02X %02X %02X %02X %02X %02X %02X %02X\n", + tag, __func__, event[0], event[1], event[2], event[3], + event[4], event[5], event[6], event[7]); + break; + } +} + +/* +static void buffDump(unsigned char *buf, unsigned int buflength, char *tag) +{ + unsigned char *tmp, *back; + unsigned int i; + unsigned int to_read; + unsigned int remain = buflength; + unsigned int chunk = 10; + + logError(1, "%s BUFFDUMP IN:", tag); + + tmp = kmalloc(300, GFP_ATOMIC); + if (!tmp) { + logError(1, "alloc tmp=%04d byte failed", 300); + return; + } + back = tmp; + + memcpy(tmp, buf, buflength); + + while (remain > 0) { + if (remain > chunk) { + remain -= chunk; + to_read = chunk; + } else { + to_read = remain; + for (i = to_read; i < chunk; i++) { + tmp[i] = 0xED; + } + remain = 0; + } + + logError(1, "%s %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + tag, tmp[0], tmp[1], tmp[2], tmp[3], tmp[4], tmp[5], tmp[6], tmp[7], tmp[8], tmp[9]); + + tmp += to_read; + } + kfree(back); +} +*/ + +static void fts_ts_sleep_work(struct work_struct *work) +{ + struct fts_ts_info *info = + container_of(work, struct fts_ts_info, sleep_work); + int error = 0, count = 0; + unsigned char regAdd = FIFO_CMD_READALL; + unsigned char data[FIFO_EVENT_SIZE * FIFO_DEPTH] = { 0 }; + unsigned char eventId; + const unsigned char EVENTS_REMAINING_POS = 7; + const unsigned char EVENTS_REMAINING_MASK = 0x1F; + unsigned char events_remaining = 0; + unsigned char *evt_data; + static char pre_id[3]; + event_dispatch_handler_t event_handler; + int r; + fts_disableInterrupt(); + if (info->tp_pm_suspend) { + r = wait_for_completion_timeout(&info->pm_resume_completion, + msecs_to_jiffies(500)); + if (!r) { + logError( + 1, + "%s pm_resume_completion timeout, i2c is closed", + tag); + pm_relax(info->dev); + fts_enableInterrupt(); + lpm_disable_for_input(false); + return; + } else { + logError( + 1, + "%s pm_resume_completion be completed, handling irq", + tag); + } + } + + info->irq_status = true; + error = fts_writeReadU8UX(regAdd, 0, 0, data, FIFO_EVENT_SIZE, + DUMMY_FIFO); + events_remaining = data[EVENTS_REMAINING_POS] & EVENTS_REMAINING_MASK; + events_remaining = (events_remaining > FIFO_DEPTH - 1) ? + FIFO_DEPTH - 1 : + events_remaining; + + /*Drain the rest of the FIFO, up to 31 events*/ + if (error == OK && events_remaining > 0) { + error = fts_writeReadU8UX(regAdd, 0, 0, &data[FIFO_EVENT_SIZE], + FIFO_EVENT_SIZE * events_remaining, + DUMMY_FIFO); + } + if (error != OK) { + logError( + 1, + "Error (%d) while reading from FIFO in fts_event_handler", + error); + } else { + for (count = 0; count < events_remaining + 1; count++) { + evt_data = &data[count * FIFO_EVENT_SIZE]; + if (pre_id[0] == EVT_ID_USER_REPORT && + pre_id[1] == 0x02 && pre_id[2] == 0x18) { + pre_id[0] = 0; + pre_id[1] = 0; + pre_id[2] = 0; + continue; + } + if (evt_data[0] == EVT_ID_NOEVENT) + break; + eventId = evt_data[0] >> 4; + /*Ensure event ID is within bounds*/ + if (eventId < NUM_EVT_ID) { + event_handler = + info->event_dispatch_table[eventId]; + event_handler(info, (evt_data)); + pre_id[0] = evt_data[0]; + pre_id[1] = evt_data[1]; + pre_id[2] = evt_data[2]; + } + } + } + input_sync(info->input_dev); + info->irq_status = false; +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + wake_up(&info->wait_queue); +#endif + pm_relax(info->dev); + fts_enableInterrupt(); + lpm_disable_for_input(false); + return; +} + +/** + * Bottom Half Interrupt Handler function + * This handler is called each time there is at least one new event in the FIFO and the interrupt pin of the IC goes low. + * It will read all the events from the FIFO and dispatch them to the proper event handler according the event ID + */ +static irqreturn_t fts_event_handler(int irq, void *ts_info) +{ + struct fts_ts_info *info = ts_info; + int error = 0, count = 0; + unsigned char regAdd = FIFO_CMD_READALL; + unsigned char data[FIFO_EVENT_SIZE * FIFO_DEPTH] = { 0 }; + unsigned char eventId; + const unsigned char EVENTS_REMAINING_POS = 7; + const unsigned char EVENTS_REMAINING_MASK = 0x1F; + unsigned char events_remaining = 0; + unsigned char *evt_data; + static char pre_id[3]; + event_dispatch_handler_t event_handler; + + if (info->tp_pm_suspend) { + logError(1, "%s device in suspend, schedue to work", tag); + pm_wakeup_event(info->dev, 0); + if (!work_pending(&info->sleep_work)) { + pm_stay_awake(info->dev); + queue_work(info->irq_wq, &info->sleep_work); + } + return IRQ_HANDLED; + } + +#ifdef CONFIG_SECURE_TOUCH + if (!fts_secure_filter_interrupt(info)) { + return IRQ_HANDLED; + } +#endif + lpm_disable_for_input(true); + + info->irq_status = true; + error = fts_writeReadU8UX(regAdd, 0, 0, data, FIFO_EVENT_SIZE, + DUMMY_FIFO); + events_remaining = data[EVENTS_REMAINING_POS] & EVENTS_REMAINING_MASK; + events_remaining = (events_remaining > FIFO_DEPTH - 1) ? + FIFO_DEPTH - 1 : + events_remaining; + + /*Drain the rest of the FIFO, up to 31 events*/ + if (error == OK && events_remaining > 0) { + error = fts_writeReadU8UX(regAdd, 0, 0, &data[FIFO_EVENT_SIZE], + FIFO_EVENT_SIZE * events_remaining, + DUMMY_FIFO); + } + if (error != OK) { + logError( + 1, + "Error (%d) while reading from FIFO in fts_event_handler", + error); + } else { + for (count = 0; count < events_remaining + 1; count++) { + evt_data = &data[count * FIFO_EVENT_SIZE]; + if (pre_id[0] == EVT_ID_USER_REPORT && + pre_id[1] == 0x02 && pre_id[2] == 0x18) { + pre_id[0] = 0; + pre_id[1] = 0; + pre_id[2] = 0; + continue; + } + if (evt_data[0] == EVT_ID_NOEVENT) + break; + eventId = evt_data[0] >> 4; + /*Ensure event ID is within bounds*/ + if (eventId < NUM_EVT_ID) { + event_handler = + info->event_dispatch_table[eventId]; + event_handler(info, (evt_data)); + pre_id[0] = evt_data[0]; + pre_id[1] = evt_data[1]; + pre_id[2] = evt_data[2]; + } + } + } + input_sync(info->input_dev); + info->irq_status = false; + if (!info->touch_id) + lpm_disable_for_input(false); +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + wake_up(&info->wait_queue); +#endif + return IRQ_HANDLED; +} + +/**@}*/ + +static const char *fts_get_config(struct fts_ts_info *info) +{ + struct fts_hw_platform_data *pdata = info->board; + int i = 0, ret = 0; + + ret = fts_get_lockdown_info(info->lockdown_info, info); + + if (ret < OK) { + logError(1, "%s can't read lockdown info", tag); + return pdata->default_fw_name; + } + + ret |= fts_enableInterrupt(); + + for (i = 0; i < pdata->config_array_size; i++) { + if (info->lockdown_info[0] == pdata->config_array[i].tp_vendor) + break; + } + + if (i >= pdata->config_array_size) { + logError(1, "%s can't find right config", tag); + return pdata->default_fw_name; + } + + logError(1, "%s Choose config %d: %s", tag, i, + pdata->config_array[i].fts_cfg_name); + pdata->current_index = i; +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + if (pdata->dump_click_count) { + info->current_clicknum_file = + kzalloc(TOUCH_COUNT_FILE_MAXSIZE, GFP_KERNEL); + strlcpy(info->current_clicknum_file, + pdata->config_array[i].clicknum_file_name, + TOUCH_COUNT_FILE_MAXSIZE); + } +#endif + return pdata->config_array[i].fts_cfg_name; +} + +static const char *fts_get_limit(struct fts_ts_info *info) +{ + struct fts_hw_platform_data *pdata = info->board; + int i = 0, ret = 0; + + ret = fts_get_lockdown_info(info->lockdown_info, info); + + if (ret < OK) { + logError(1, "%s can't read lockdown info", tag); + return LIMITS_FILE; + } + + ret |= fts_enableInterrupt(); + + for (i = 0; i < pdata->config_array_size; i++) { + if (info->lockdown_info[0] == pdata->config_array[i].tp_vendor) + break; + } + + if (i >= pdata->config_array_size) { + logError(1, "%s can't find right limit", tag); + return LIMITS_FILE; + } + + logError(1, "%s Choose limit file %d: %s", tag, i, + pdata->config_array[i].fts_limit_name); + pdata->current_index = i; + return pdata->config_array[i].fts_limit_name; +} + +/** +* Implement the fw update and initialization flow of the IC that should be executed at every boot up. +* The function perform a fw update of the IC in case of crc error or a new fw version and then understand if the IC need to be re-initialized again. +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_fw_update(struct fts_ts_info *info, const char *fw_name, int force) +{ + u8 error_to_search[4] = { EVT_TYPE_ERROR_CRC_CX_HEAD, + EVT_TYPE_ERROR_CRC_CX, + EVT_TYPE_ERROR_CRC_CX_SUB_HEAD, + EVT_TYPE_ERROR_CRC_CX_SUB }; + int retval = 0; + int retval1 = 0; + int ret; + int crc_status = 0; + int error = 0; + int init_type = NO_INIT; +#ifdef PRE_SAVED_METHOD + int keep_cx = 1; +#else + int keep_cx = 0; +#endif + + logError(1, "%s Fw Auto Update is starting... \n", tag); + + ret = fts_crc_check(); + if (ret > OK) { + logError(1, "%s %s: CRC Error or NO FW!\n", tag, __func__); + crc_status = ret; + } else { + crc_status = 0; + logError( + 1, + "%s %s: NO CRC Error or Impossible to read CRC register! \n", + tag, __func__); + } + + if (fw_name == NULL) { + fw_name = fts_get_config(info); + if (fw_name == NULL) + logError(1, "%s not found mached config!", tag); + } + + if (fw_name) { + if (force) + retval = flashProcedure(fw_name, 1, keep_cx); + else + retval = flashProcedure(fw_name, crc_status, keep_cx); + + if ((retval & 0xFF000000) == ERROR_FLASH_PROCEDURE) { + logError( + 1, + "%s %s: firmware update failed and retry! ERROR %08X\n", + tag, __func__, retval); + fts_chip_powercycle(info); + retval1 = flashProcedure(info->board->default_fw_name, + crc_status, keep_cx); + if ((retval1 & 0xFF000000) == ERROR_FLASH_PROCEDURE) { + logError( + 1, + "%s %s: firmware update failed again! ERROR %08X\n", + tag, __func__, retval1); + logError(1, "%s Fw Auto Update Failed!\n", tag); + } + } + } + + logError(1, "%s %s: Verifying if CX CRC Error...\n", tag, __func__, + ret); + ret = fts_system_reset(); + if (ret >= OK) { + ret = pollForErrorType(error_to_search, 4); + if (ret < OK) { + logError(1, "%s %s: No Cx CRC Error Found! \n", tag, + __func__); + logError(1, "%s %s: Verifying if Panel CRC Error... \n", + tag, __func__); + error_to_search[0] = EVT_TYPE_ERROR_CRC_PANEL_HEAD; + error_to_search[1] = EVT_TYPE_ERROR_CRC_PANEL; + ret = pollForErrorType(error_to_search, 2); + if (ret < OK) { + logError(1, + "%s %s: No Panel CRC Error Found! \n", + tag, __func__); + init_type = NO_INIT; + } else { + logError( + 1, + "%s %s: Panel CRC Error FOUND! CRC ERROR = %02X\n", + tag, __func__, ret); + init_type = SPECIAL_PANEL_INIT; + } + } else { + logError( + 1, + "%s %s: Cx CRC Error FOUND! CRC ERROR = %02X\n", + tag, __func__, ret); + + logError( + 1, + "%s %s: Try to recovery with CX in fw file...\n", + tag, __func__, ret); + flashProcedure(info->board->default_fw_name, CRC_CX, 0); + logError(1, "%s %s: Refresh panel init data... \n", tag, + __func__, ret); + } + } else { + logError( + 1, + "%s %s: Error while executing system reset! ERROR %08X\n", + tag, __func__, ret); + } + + if (init_type == NO_INIT) { +#ifdef PRE_SAVED_METHOD + if (systemInfo.u8_cfgAfeVer != systemInfo.u8_cxAfeVer) { + init_type = SPECIAL_FULL_PANEL_INIT; + logError( + 0, + "%s %s: Different CX AFE Ver: %02X != %02X... Execute FULL Panel Init! \n", + tag, __func__, systemInfo.u8_cfgAfeVer, + systemInfo.u8_cxAfeVer); + } else +#endif + + if (systemInfo.u8_cfgAfeVer != + systemInfo.u8_panelCfgAfeVer) { + init_type = SPECIAL_PANEL_INIT; + logError( + 0, + "%s %s: Different Panel AFE Ver: %02X != %02X... Execute Panel Init! \n", + tag, __func__, systemInfo.u8_cfgAfeVer, + systemInfo.u8_panelCfgAfeVer); + } else { + init_type = NO_INIT; + } + } + + if (init_type != NO_INIT) { + error = fts_chip_initialization(info, init_type); + if (error < OK) { + logError( + 1, + "%s %s Cannot initialize the chip ERROR %08X\n", + tag, __func__, error); + } + } + + error = fts_init_sensing(info); + if (error < OK) { + logError( + 1, + "%s Cannot initialize the hardware device ERROR %08X\n", + tag, error); + } + + logError(1, "%s Fw Update Finished! error = %08X\n", tag, error); + return error; +} + +#ifndef FW_UPDATE_ON_PROBE + +/** +* Function called by the delayed workthread executed after the probe in order to perform the fw update flow +* @see fts_fw_update() +*/ +static void fts_fw_update_auto(struct work_struct *work) +{ + struct delayed_work *fwu_work = + container_of(work, struct delayed_work, work); + struct fts_ts_info *info = + container_of(fwu_work, struct fts_ts_info, fwu_work); + fts_fw_update(info, NULL, 0); +} +#endif + +/** +* Execute the initialization of the IC (supporting a retry mechanism), checking also the resulting data +* @see production_test_main() +*/ +static int fts_chip_initialization(struct fts_ts_info *info, int init_type) +{ + int ret2 = 0; + int retry; + int initretrycnt = 0; + + for (retry = 0; retry <= RETRY_INIT_BOOT; retry++) { + ret2 = production_test_initialization(init_type); + if (ret2 == OK) + break; + initretrycnt++; + logError(1, + "%s initialization cycle count = %04d - ERROR %08X \n", + tag, initretrycnt, ret2); + fts_chip_powercycle(info); + } + + if (ret2 < OK) { + logError(1, "%s fts initialization failed 3 times \n", tag); + } + + return ret2; +} + +/** + * @addtogroup isr + * @{ + */ +/** +* Top half Interrupt handler function +* Respond to the interrupt and schedule the bottom half interrupt handler in its work queue +* @see fts_event_handler() +*/ +/* +static irqreturn_t fts_interrupt_handler(int irq, void *handle) +{ + struct fts_ts_info *info = handle; +#ifdef CONFIG_SECURE_TOUCH + if (!fts_secure_filter_interrupt(info)) { + return IRQ_HANDLED; + } +#endif + disable_irq_nosync(info->client->irq); + queue_work(info->event_wq, &info->work); + + return IRQ_HANDLED; +} +*/ +/** +* Initialize the dispatch table with the event handlers for any possible event ID and the interrupt routine behavior (triggered when the IRQ pin is low and associating the top half interrupt handler function). +* @see fts_interrupt_handler() +*/ +static int fts_interrupt_install(struct fts_ts_info *info) +{ + int i, error = 0; + + info->event_dispatch_table = kzalloc( + sizeof(event_dispatch_handler_t) * NUM_EVT_ID, GFP_KERNEL); + + if (!info->event_dispatch_table) { + logError(1, "%s OOM allocating event dispatch table\n", tag); + return -ENOMEM; + } + + for (i = 0; i < NUM_EVT_ID; i++) + info->event_dispatch_table[i] = fts_nop_event_handler; + + install_handler(info, ENTER_POINT, enter_pointer); + install_handler(info, LEAVE_POINT, leave_pointer); + install_handler(info, MOTION_POINT, motion_pointer); + install_handler(info, ERROR, error); + install_handler(info, CONTROLLER_READY, controller_ready); + install_handler(info, STATUS_UPDATE, status); + install_handler(info, USER_REPORT, user_report); + + /* disable interrupts in any case */ + error = fts_disableInterrupt(); + logError(1, "%s Interrupt Mode\n", tag); + if (request_threaded_irq(info->client->irq, NULL, fts_event_handler, + info->board->irq_flags, FTS_TS_DRV_NAME, + info)) { + logError(1, "%s Request irq failed\n", tag); + kfree(info->event_dispatch_table); + error = -EBUSY; + } else { + disable_irq(info->client->irq); + } + + return error; +} + +/** +* Clean the dispatch table and the free the IRQ. +* This function is called when the driver need to be removed +*/ +static void fts_interrupt_uninstall(struct fts_ts_info *info) +{ + fts_disableInterrupt(); + + kfree(info->event_dispatch_table); + + free_irq(info->client->irq, info); +} + +/**@}*/ + +/** +* This function try to attempt to communicate with the IC for the first time during the boot up process in order to acquire the necessary info for the following stages. +* The function execute a system reset, read fundamental info (system info) from the IC and install the interrupt +* @return OK if success or an error code which specify the type of error encountered +*/ +static int fts_init(struct fts_ts_info *info) +{ + int error; + + error = fts_system_reset(); + if (error < OK && isI2cError(error)) { + logError(1, "%s Cannot reset the device! ERROR %08X\n", tag, + error); + return error; + } else { + if (error == (ERROR_TIMEOUT | ERROR_SYSTEM_RESET_FAIL)) { + logError(1, "%s Setting default Sys INFO! \n", tag); + error = defaultSysInfo(0); + } else { + error = readSysInfo(0); + if (error < OK) { + if (!isI2cError(error)) + error = OK; + logError( + 1, + "%s Cannot read Sys Info! ERROR %08X\n", + tag, error); + } + } + } + + return error; +} + +/** +* Execute a power cycle in the IC, toggling the power lines (AVDD and DVDD) +* @param info pointer to fts_ts_info struct which contain information of the regulators +* @return 0 if success or another value if fail +*/ +int fts_chip_powercycle(struct fts_ts_info *info) +{ + int error = 0; + + logError(1, "%s %s: Power Cycle Starting... \n", tag, __func__); + logError(1, "%s %s: Disabling IRQ... \n", tag, __func__); + + fts_disableInterruptNoSync(); + + if (info->vdd_reg) { + error = regulator_disable(info->vdd_reg); + if (error < 0) { + logError(1, "%s %s: Failed to disable DVDD regulator\n", + tag, __func__); + } + } + + if (info->avdd_reg) { + error = regulator_disable(info->avdd_reg); + if (error < 0) { + logError(1, "%s %s: Failed to disable AVDD regulator\n", + tag, __func__); + } + } + + if (info->board->reset_gpio != GPIO_NOT_DEFINED) + gpio_set_value(info->board->reset_gpio, 0); + else + mdelay(300); + + if (info->vdd_reg) { + error = regulator_enable(info->vdd_reg); + if (error < 0) { + logError(1, "%s %s: Failed to enable DVDD regulator\n", + tag, __func__); + } + } + + mdelay(1); + + if (info->avdd_reg) { + error = regulator_enable(info->avdd_reg); + if (error < 0) { + logError(1, "%s %s: Failed to enable AVDD regulator\n", + tag, __func__); + } + } + + mdelay(5); + + if (info->board->reset_gpio != GPIO_NOT_DEFINED) { + mdelay(10); + gpio_set_value(info->board->reset_gpio, 1); + } + + release_all_touches(info); + + logError(1, "%s %s: Power Cycle Finished! ERROR CODE = %08x\n", tag, + __func__, error); + setSystemResetedUp(1); + setSystemResetedDown(1); + return error; +} + +/** + * Complete the boot up process, initializing the sensing of the IC according to the current setting chosen by the host and register the notifier for the suspend/resume actions and the event handler + * @return OK if success or an error code which specify the type of error encountered + */ +static int fts_init_sensing(struct fts_ts_info *info) +{ + int error = 0; +#ifdef CONFIG_DRM + error |= drm_register_client(&info->notifier); +#endif + error |= fts_interrupt_install(info); + error |= fts_mode_handler(info, 0); +#ifdef CONFIG_FTS_FOD_AREA_REPORT + error |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + error |= setScanMode(SCAN_MODE_ACTIVE, 0x01); +#endif + error |= fts_enableInterrupt(); + + if (error < OK) + logError(1, "%s %s Init after Probe error (ERROR = %08X)\n", + tag, __func__, error); + + return error; +} + +/** + * @ingroup mode_section + * @{ + */ +/** + * The function handle the switching of the mode in the IC enabling/disabling the sensing and the features set from the host + * @param info pointer to fts_ts_info which contains info about the device and its hw setup + * @param force if 1, the enabling/disabling command will be send even if the feature was alredy enabled/disabled otherwise it will judge if the feature changed status or the IC had s system reset and therefore the features need to be restored + * @return OK if success or an error code which specify the type of error encountered + */ +static int fts_mode_handler(struct fts_ts_info *info, int force) +{ + int res = OK; + int ret = OK; + u8 settings[4] = { 0 }; +#ifdef CONFIG_FTS_FOD_AREA_REPORT + u8 gesture_cmd[6] = { 0xA2, 0x03, 0x20, 0x00, 0x00, 0x01 }; + u8 single_only_cmd[4] = { 0xC0, 0x02, 0x00, 0x00 }; + u8 single_double_cmd[4] = { 0xC0, 0x02, 0x01, 0x1E }; +#endif +#ifdef CONFIG_FTS_FOD_AREA_REPORT + mutex_lock(&info->fod_mutex); +#endif + info->mode = MODE_NOTHING; + logError(0, "%s %s: Mode Handler starting... \n", tag, __func__); + switch (info->resume_bit) { + case 0: + logError(0, "%s %s: Screen OFF... \n", tag, __func__); + +#ifdef CONFIG_FTS_FOD_AREA_REPORT + if (info->fod_status) { + logError(1, "%s %s: Sense OFF by FOD \n", tag, + __func__); + logError(1, "%s %s,send long press and gesture cmd\n", + tag, __func__); + res = fts_write_dma_safe(gesture_cmd, + ARRAY_SIZE(gesture_cmd)); + if (res < OK) + logError( + 1, + "%s %s: enter gesture and longpress failed! ERROR %08X recovery in senseOff...\n", + tag, __func__, res); + res = setScanMode(SCAN_MODE_LOW_POWER, 0); + res |= ret; + if (info->gesture_enabled == 1) { + res = fts_write_dma_safe( + single_double_cmd, + ARRAY_SIZE(single_double_cmd)); + if (res < OK) + logError( + 1, + "%s %s: set single and double tap delay time failed! ERROR %08X\n", + tag, __func__, res); + } else { + res = fts_write_dma_safe( + single_only_cmd, + ARRAY_SIZE(single_only_cmd)); + if (res < OK) + logError( + 1, + "%s %s: set single only delay time failed! ERROR %08X\n", + tag, __func__, res); + } + info->fod_status_set = true; + } else { +#endif + logError(1, "%s %s: Sense OFF! \n", tag, __func__); + ret = setScanMode(SCAN_MODE_ACTIVE, 0x00); + res |= ret; + + if (info->gesture_enabled == 1) { + logError(1, "%s %s: enter in gesture mode ! \n", + tag, __func__); + res = enterGestureMode(isSystemResettedDown()); + if (res >= OK) { + fromIDtoMask(FEAT_SEL_GESTURE, + (u8 *)&info->mode, + sizeof(info->mode)); + MODE_LOW_POWER(info->mode, 0); + } else { + logError( + 1, + "%s %s: enterGestureMode failed! ERROR %08X recovery in senseOff...\n", + tag, __func__, res); + } + } + info->fod_status_set = false; +#ifdef CONFIG_FTS_FOD_AREA_REPORT + } +#endif + setSystemResetedDown(0); + break; + + case 1: + logError(1, "%s %s: Screen ON... \n", tag, __func__); + +#ifdef GLOVE_MODE + if ((info->glove_enabled == FEAT_ENABLE && + isSystemResettedUp()) || + force == 1) { + logError(0, "%s %s: Glove Mode setting... \n", tag, + __func__); + settings[0] = info->glove_enabled; + ret = setFeatures(FEAT_SEL_GLOVE, settings, 1); + if (ret < OK) { + logError( + 1, + "%s %s: error during setting GLOVE_MODE! ERROR %08X\n", + tag, __func__, ret); + } + res |= ret; + + if (ret >= OK && info->glove_enabled == FEAT_ENABLE) { + fromIDtoMask(FEAT_SEL_GLOVE, (u8 *)&info->mode, + sizeof(info->mode)); + logError(1, "%s %s: GLOVE_MODE Enabled! \n", + tag, __func__); + } else { + logError(1, "%s %s: GLOVE_MODE Disabled! \n", + tag, __func__); + } + } +#endif + +#ifdef COVER_MODE + if ((info->cover_enabled == FEAT_ENABLE && + isSystemResettedUp()) || + force == 1) { + logError(0, "%s %s: Cover Mode setting... \n", tag, + __func__); + settings[0] = info->cover_enabled; + ret = setFeatures(FEAT_SEL_COVER, settings, 1); + if (ret < OK) { + logError( + 1, + "%s %s: error during setting COVER_MODE! ERROR %08X\n", + tag, __func__, ret); + } + res |= ret; + + if (ret >= OK && info->cover_enabled == FEAT_ENABLE) { + fromIDtoMask(FEAT_SEL_COVER, (u8 *)&info->mode, + sizeof(info->mode)); + logError(1, "%s %s: COVER_MODE Enabled! \n", + tag, __func__); + } else { + logError(1, "%s %s: COVER_MODE Disabled! \n", + tag, __func__); + } + } +#endif +#ifdef CHARGER_MODE + if ((info->charger_enabled > 0 && isSystemResettedUp()) || + force == 1) { + logError(0, "%s %s: Charger Mode setting... \n", tag, + __func__); + + settings[0] = info->charger_enabled; + ret = setFeatures(FEAT_SEL_CHARGER, settings, 1); + if (ret < OK) { + logError( + 1, + "%s %s: error during setting CHARGER_MODE! ERROR %08X\n", + tag, __func__, ret); + } + res |= ret; + + if (ret >= OK && info->charger_enabled == FEAT_ENABLE) { + fromIDtoMask(FEAT_SEL_CHARGER, + (u8 *)&info->mode, + sizeof(info->mode)); + logError(1, "%s %s: CHARGER_MODE Enabled! \n", + tag, __func__); + } else { + logError(1, "%s %s: CHARGER_MODE Disabled! \n", + tag, __func__); + } + } +#endif + +#ifdef GRIP_MODE + if ((info->grip_enabled == FEAT_ENABLE && + isSystemResettedUp()) || + force == 1) { + logError(0, "%s %s: Grip Mode setting... \n", tag, + __func__); + settings[0] = info->grip_enabled; + ret = setFeatures(FEAT_SEL_GRIP, settings, 1); + if (ret < OK) { + logError( + 1, + "%s %s: error during setting GRIP_MODE! ERROR %08X\n", + tag, __func__, ret); + } + res |= ret; + + if (ret >= OK && info->grip_enabled == FEAT_ENABLE) { + fromIDtoMask(FEAT_SEL_GRIP, (u8 *)&info->mode, + sizeof(info->mode)); + logError(1, "%s %s: GRIP_MODE Enabled! \n", tag, + __func__); + } else { + logError(1, "%s %s: GRIP_MODE Disabled! \n", + tag, __func__); + } + } +#endif +#ifdef CONFIG_FTS_FOD_AREA_REPORT + if (info->fod_pressed) { + logError(1, "%s %s: Sense OFF \n", tag, __func__); + res |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + logError(1, "%s %s: Sense ON without cal \n", tag, + __func__); + res |= setScanMode(SCAN_MODE_ACTIVE, 0x20); + } else { + logError(1, "%s %s: Sense ON\n", tag, __func__); + res |= setScanMode(SCAN_MODE_ACTIVE, 0x01); + } + info->sensor_scan = true; + if (info->fod_status) { + res = fts_write_dma_safe(gesture_cmd, + ARRAY_SIZE(gesture_cmd)); + if (res < OK) + logError( + 1, + "%s %s: enter gesture and longpress failed! ERROR %08X recovery in senseOff...\n", + tag, __func__, res); + info->fod_status_set = true; + } +#else + settings[0] = 0x01; + logError(1, "%s %s: Sense ON! \n", tag, __func__); + res |= setScanMode(SCAN_MODE_ACTIVE, settings[0]); + info->mode |= (SCAN_MODE_ACTIVE << 24); + MODE_ACTIVE(info->mode, settings[0]); +#endif + setSystemResetedUp(0); + break; + + default: + logError(1, + "%s %s: invalid resume_bit value = %d! ERROR %08X \n", + tag, __func__, info->resume_bit, ERROR_OP_NOT_ALLOW); + res = ERROR_OP_NOT_ALLOW; + } + + logError(0, "%s %s: Mode Handler finished! res = %08X mode = %08X \n", + tag, __func__, res, info->mode); +#ifdef CONFIG_FTS_FOD_AREA_REPORT + mutex_unlock(&info->fod_mutex); +#endif + return res; +} + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +static struct xiaomi_touch_interface xiaomi_touch_interfaces; + +bool inline fts_touchmode_edgefilter(unsigned int touch_id, int x, int y) +{ + int i; + bool top_half = false; + + const struct fts_hw_platform_data *bdata = fts_info->board; + int filter_size = 0; + + switch (xiaomi_touch_interfaces + .touch_mode[Touch_Edge_Filter][GET_CUR_VALUE]) { + case 0: + filter_size = 0; + break; + case 1: + filter_size = 100; + break; + case 2: + filter_size = 150; + break; + case 3: + filter_size = 250; + break; + default: + filter_size = 0; + logError(1, "%s %s: no support value %08d\n", tag, __func__, + filter_size); + break; + } + + if (!filter_size) + return false; + + if (test_bit(touch_id, &fts_info->touch_skip)) { + logError(1, "%s %s: skip mask finger:%d, %x\n", tag, __func__, + touch_id, fts_info->touch_skip); + return true; + } else if ((x >= 0 && x < filter_size) && + ((y >= 0 && y < filter_size) || + (y > bdata->y_max - filter_size && y < bdata->y_max))) { + if (y >= 0 && y < filter_size) { + top_half = true; + } else { + top_half = false; + } + + for (i = 0; i < TOUCH_ID_MAX; i++) { + if ((i == touch_id) || + (!test_bit(i, &fts_info->touch_id))) + continue; + if ((fts_info->coor[i][1] > (int)(bdata->y_max / 2) && + top_half) || + (fts_info->coor[i][1] < (int)(bdata->y_max / 2) && + fts_info->coor[i][1] >= 0 && !top_half)) { + return false; + } + } + + if (!test_bit(touch_id, &fts_info->touch_id) && + fts_info->touch_id != 0) { + __set_bit(touch_id, &fts_info->touch_skip); + logError( + 1, + "%s %s: skip mask first finger:%d, touch_id:%x, touch_skip:%0x\n", + tag, __func__, touch_id, fts_info->touch_id, + fts_info->touch_skip); + return true; + } + } + + return false; +} + +int fts_read_touchmode_data() +{ + int ret = 0; + u8 get_cmd[2] = { 0xc1, 0x05 }; + u8 get_value[Touch_Mode_NUM] = { + 0x0, + }; + u8 grip_cmd[2] = { 0xc1, 0x08 }; + u8 grip_value[Touch_Mode_NUM] = { + 0x0, + }; + int readBytes = 7; + int i; + ret = fts_writeRead_dma_safe(get_cmd, sizeof(get_cmd) / sizeof(u8), + get_value, readBytes); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading touchmode data ERROR %08X\n", + tag, __func__, ret); + return -1; + } + ret = fts_writeRead_dma_safe(grip_cmd, sizeof(grip_cmd) / sizeof(u8), + grip_value, readBytes); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading edge filter data ERROR %08X\n", + tag, __func__, ret); + return -1; + } + + for (i = 0; i < Touch_Mode_NUM; i++) { + if (i == Touch_Edge_Filter) + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] = + grip_value[0]; + else + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] = + get_value[i]; + } + + for (i = 0; i < 7; i++) { + xiaomi_touch_interfaces.touch_edge[i] = grip_value[i]; + } + + logError( + 1, + "%s %s: game_mode:%d, active_mode:%d, up_threshold:%d, landlock:%d, wgh:%d, %d, %d\n", + tag, __func__, get_value[0], get_value[1], get_value[2], + get_value[3], get_value[4], get_value[5], get_value[6]); + logError(1, "%s %s: grip:0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", + tag, __func__, grip_value[0], grip_value[1], grip_value[2], + grip_value[3], grip_value[4], grip_value[5], grip_value[6]); + + return ret; +} + +static void fts_init_touchmode_data() +{ + int i; + + /* default value should equl the first initial value */ + for (i = 0; i < Touch_Mode_NUM; i++) { + xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE] = + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE]; + xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE] = + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE]; + } + /* Touch Game Mode Switch */ + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MAX_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_DEF_VALUE] = 0; + + /* Acitve Mode */ + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MAX_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_DEF_VALUE] = + 0; + + /* finger hysteresis */ + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_DEF_VALUE] = + 80; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE] = + 80; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_CUR_VALUE] = + 80; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MAX_VALUE] = + 120; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MIN_VALUE] = + 40; + + /* Tolerance */ + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_DEF_VALUE] = 25; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MAX_VALUE] = 35; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MIN_VALUE] = 5; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][SET_CUR_VALUE] = 25; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_CUR_VALUE] = 25; + + /* Wgh Min */ + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_DEF_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_CUR_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][SET_CUR_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_MAX_VALUE] = 15; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_MIN_VALUE] = 0; + + /* Wgh Max */ + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_DEF_VALUE] = 5; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_CUR_VALUE] = 5; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][SET_CUR_VALUE] = 5; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_MAX_VALUE] = 15; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_MIN_VALUE] = 0; + + /* Wgh Step */ + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_DEF_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_CUR_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][SET_CUR_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_MAX_VALUE] = 2; + xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_MIN_VALUE] = 0; + + /* edge filter */ + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MAX_VALUE] = + 3; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_DEF_VALUE] = + 2; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE] = + 2; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = + 2; + + /* Orientation */ + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MAX_VALUE] = 3; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = 0; + + for (i = 0; i < Touch_Mode_NUM; i++) { + logError( + 1, + "%s %s: mode:%d, set cur:%d, get cur:%d, def:%d min:%d max:%d\n", + tag, __func__, i, + xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MIN_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MAX_VALUE]); + } + + return; +} +#define EDGE_OF_LEFTRIGHT 45 +#define EDGE_OF_TOPBOTTOM 0 +static void fts_edge_rejection(bool on, int value) +{ + /* the fixed edge_reject is 65 */ + int ret = 0; + u8 edge_of_leftright[4] = { 0xc0, 0x01, 0x00, 0x00 }; + u8 edge_of_topbottom[4] = { 0xc0, 0x01, 0x01, 0x00 }; + + if (on) { + edge_of_topbottom[3] = value; + edge_of_leftright[3] = 0; + } else { + edge_of_leftright[3] = EDGE_OF_LEFTRIGHT; + edge_of_topbottom[3] = EDGE_OF_TOPBOTTOM; + } + + ret = fts_write_dma_safe(edge_of_leftright, + sizeof(edge_of_leftright) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while writing edge left/right data ERROR %08X\n", + tag, __func__, ret); + return; + } + + ret = fts_write_dma_safe(edge_of_topbottom, + sizeof(edge_of_topbottom) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while writing edge top/bottom data ERROR %08X\n", + tag, __func__, ret); + return; + } + logError(1, "%s %s: on:%d, value:%d\n", tag, __func__, on, value); + + return; +} + +static void fts_update_grip_mode() +{ + int i, ret; + u8 grip_cmd[9] = { + 0xc0, + 0x08, + 0x00, + }; + u8 grip_rcmd[2] = { 0xc1, 0x08 }; + u8 grip_value[7] = { + 0x0, + }; + int temp_value = 0; + bool topbottom_edge_filter = false; + int direction = 0; + + logError(1, "%s %s: value:%d\n", tag, __func__, + xiaomi_touch_interfaces + .touch_mode[Touch_Edge_Filter][SET_CUR_VALUE]); + switch (xiaomi_touch_interfaces + .touch_mode[Touch_Edge_Filter][SET_CUR_VALUE]) { + case 0: + temp_value = 0; + break; + case 1: + temp_value = 100; + break; + case 2: + temp_value = 170; + break; + case 3: + temp_value = 250; + break; + default: + temp_value = 0; + logError(1, "%s %s: no support value %08d\n", tag, __func__, + temp_value); + break; + } + + direction = xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE]; + + switch (direction) { + case 0: + case 2: + /* 0 and 180, filter the leftright edge */ + topbottom_edge_filter = false; + xiaomi_touch_interfaces.touch_edge[0] = 0; + xiaomi_touch_interfaces.touch_edge[1] = 0x0f; + xiaomi_touch_interfaces.touch_edge[2] = 0x00; + xiaomi_touch_interfaces.touch_edge[3] = 0; + xiaomi_touch_interfaces.touch_edge[4] = 0; + xiaomi_touch_interfaces.touch_edge[5] = 0; + xiaomi_touch_interfaces.touch_edge[6] = 0; + break; + case 1: + topbottom_edge_filter = true; + xiaomi_touch_interfaces.touch_edge[0] = 1; + xiaomi_touch_interfaces.touch_edge[1] = 0x0f; + xiaomi_touch_interfaces.touch_edge[2] = 0x00; + xiaomi_touch_interfaces.touch_edge[3] = temp_value; + xiaomi_touch_interfaces.touch_edge[4] = temp_value; + xiaomi_touch_interfaces.touch_edge[5] = 0; + xiaomi_touch_interfaces.touch_edge[6] = 0; + break; + case 3: + topbottom_edge_filter = true; + xiaomi_touch_interfaces.touch_edge[0] = 1; + xiaomi_touch_interfaces.touch_edge[1] = 0x0f; + xiaomi_touch_interfaces.touch_edge[2] = 0x00; + xiaomi_touch_interfaces.touch_edge[3] = 0; + xiaomi_touch_interfaces.touch_edge[4] = 0; + xiaomi_touch_interfaces.touch_edge[5] = temp_value; + xiaomi_touch_interfaces.touch_edge[6] = temp_value; + break; + default: + /* Dont't support */ + break; + }; + + if (!xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_CUR_VALUE] || + !topbottom_edge_filter) { + logError(1, "%s %s: touch game mode off or portrait\n", tag, + __func__); + fts_edge_rejection(false, 0); + } else + fts_edge_rejection(true, 0); + + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[Touch_Edge_Filter][SET_CUR_VALUE]; + + for (i = 0; i < 7; i++) { + grip_cmd[2 + i] = (u8)(xiaomi_touch_interfaces.touch_edge[i]); + } + logError( + 1, + "%s %s: write grip:0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", + tag, __func__, grip_cmd[0], grip_cmd[1], grip_cmd[2], + grip_cmd[3], grip_cmd[4], grip_cmd[5], grip_cmd[6], grip_cmd[7], + grip_cmd[8]); + + ret = fts_write_dma_safe(grip_cmd, sizeof(grip_cmd) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while writing touchmode data ERROR %08X\n", + tag, __func__, ret); + return; + } + msleep(10); + ret = fts_writeRead_dma_safe(grip_rcmd, sizeof(grip_rcmd) / sizeof(u8), + grip_value, + sizeof(grip_value) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading edge filter data ERROR %08X\n", + tag, __func__, ret); + return; + } + logError(1, + "%s %s: read grip:0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", + tag, __func__, grip_value[0], grip_value[1], grip_value[2], + grip_value[3], grip_value[4], grip_value[5], grip_value[6]); + + logError(1, "%s %s: grip enable:%d, direction:%d\n", tag, __func__, + grip_value[0], direction); + + return; +} + +static void fts_update_touchmode_data() +{ + bool update = false; + int i, j, ret = 0; + u8 set_cmd[9] = { + 0xc0, + 0x05, + 0, + }; + u8 get_cmd[2] = { 0xc1, 0x05 }; + u8 get_value[7] = { + 0x0, + }; + int temp_value = 0; + + ret = wait_event_interruptible_timeout(fts_info->wait_queue, + !(fts_info->irq_status || + fts_info->touch_id), + msecs_to_jiffies(500)); + + if (ret <= 0) { + logError(1, "%s %s: wait touch finger up timeout\n", tag, + __func__); + return; + } + mutex_lock(&fts_info->cmd_update_mutex); + + for (i = 0; i < Touch_Mode_NUM; i++) { + if (xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] != + xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE]) { + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE]; + logError(1, "%s %s: mode:%d changed, value:%d\n", tag, + __func__, i, + xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE]); + update = true; + } + } + + if (update) { + for (j = 2; j < sizeof(set_cmd) / sizeof(u8); j++) { + if (j - 2 == Touch_UP_THRESHOLD || + j - 2 == Touch_Tolerance) + temp_value = + xiaomi_touch_interfaces + .touch_mode[j - 2] + [GET_MAX_VALUE] - + xiaomi_touch_interfaces + .touch_mode[j - 2] + [GET_CUR_VALUE] + + xiaomi_touch_interfaces + .touch_mode[j - 2] + [GET_MIN_VALUE]; + else + temp_value = + (xiaomi_touch_interfaces + .touch_mode[j - 2] + [GET_CUR_VALUE]); + + set_cmd[j] = (u8)temp_value; + } + logError( + 1, + "%s %s: write game:0x%x, 0x%x, %d, %d, %d, %d, %d, %d, %d\n", + tag, __func__, set_cmd[0], set_cmd[1], set_cmd[2], + set_cmd[3], set_cmd[4], set_cmd[5], set_cmd[6], + set_cmd[7], set_cmd[8]); + + ret = fts_write_dma_safe(set_cmd, sizeof(set_cmd) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while writing touchmode data ERROR %08X\n", + tag, __func__, ret); + goto end; + } + + ret = fts_writeRead_dma_safe(get_cmd, + sizeof(get_cmd) / sizeof(u8), + get_value, + sizeof(get_value) / sizeof(u8)); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading touchmode data ERROR %08X\n", + tag, __func__, ret); + goto end; + } + + logError( + 1, + "%s %s: read game:%d, active_mode:%d, up_threshold:%d, landlock:%d, wgh:%d, %d, %d\n", + tag, __func__, get_value[0], get_value[1], get_value[2], + get_value[3], get_value[4], get_value[5], get_value[6]); + fts_update_grip_mode(); + } else { + logError(1, "%s %s: no update\n", tag, __func__); + } + +end: + mutex_unlock(&fts_info->cmd_update_mutex); + return; +} + +static void fts_cmd_update_work(struct work_struct *work) +{ + fts_update_touchmode_data(); + + return; +} + +static int fts_set_cur_value(int mode, int value) +{ + if (mode < Touch_Mode_NUM && mode >= 0) { + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = value; + + if (xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] > + xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]) { + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[mode][GET_MAX_VALUE]; + + } else if (xiaomi_touch_interfaces + .touch_mode[mode][SET_CUR_VALUE] < + xiaomi_touch_interfaces + .touch_mode[mode][GET_MIN_VALUE]) { + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[mode][GET_MIN_VALUE]; + } + } else { + logError(1, "%s %s, don't support\n", tag, __func__); + } + logError(1, "%s %s, mode:%d, value:%d\n", tag, __func__, mode, value); + + queue_work(fts_info->touch_feature_wq, &fts_info->cmd_update_work); + + return 0; +} + +static int fts_get_mode_value(int mode, int value_type) +{ + int value = -1; + + if (mode < Touch_Mode_NUM && mode >= 0) + value = xiaomi_touch_interfaces.touch_mode[mode][value_type]; + else + logError(1, "%s, %s, don't support\n", tag, __func__); + + return value; +} + +static int fts_get_mode_all(int mode, int *value) +{ + if (mode < Touch_Mode_NUM && mode >= 0) { + value[0] = + xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE]; + value[1] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + value[2] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; + value[3] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; + } else { + logError(1, "%s %s, don't support\n", tag, __func__); + } + logError(1, "%s %s, mode:%d, value:%d:%d:%d:%d\n", tag, __func__, mode, + value[0], value[1], value[2], value[3]); + + return 0; +} + +static int fts_reset_mode(int mode) +{ + int i = 0; + + if (mode < Touch_Mode_NUM && mode > 0) { + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + } else if (mode == 0) { + for (i = 0; i < Touch_Mode_NUM; i++) { + xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[i][GET_DEF_VALUE]; + } + } else { + logError(1, "%s %s, don't support\n", tag, __func__); + } + + logError(1, "%s %s, mode:%d\n", tag, __func__, mode); + + queue_work(fts_info->event_wq, &fts_info->cmd_update_work); + + return 0; +} + +int fts_p_sensor_cmd(int input) +{ + int ret; + u8 cmd_on[] = { 0xa0, 0x00, 0x05 }; + u8 cmd_off[] = { 0xa0, 0x00, 0x01 }; + u8 hover_on[] = { 0xc0, 0x03, 0x01, 0x00 }; + u8 hover_off[] = { 0xc0, 0x03, 0x00, 0x00 }; + + if (input) { + ret = fts_write_dma_safe(cmd_on, sizeof(cmd_on)); + ret = fts_write_dma_safe(hover_on, sizeof(hover_on)); + } else { + ret = fts_write_dma_safe(cmd_off, sizeof(cmd_off)); + ret = fts_write_dma_safe(hover_off, sizeof(hover_off)); + } + if (ret < OK) { + logError(1, "%s %s: write palm sensor cmd on...ERROR %08X !\n", + tag, __func__, ret); + return -EINVAL; + } + + return 0; +} + +int fts_p_sensor_write(int value) +{ + int ret = 0; + + fts_info->p_sensor_switch = value; + + if (fts_info->sensor_sleep) { + fts_info->p_sensor_changed = false; + return 0; + } + ret = fts_p_sensor_cmd(value); + + if (!ret) + fts_info->p_sensor_changed = true; + + return ret; +} + +int fts_palm_sensor_cmd(int on) +{ + int ret; + u8 cmd_on[] = { 0xc0, 0x07, 0x01 }; + u8 cmd_off[] = { 0xc0, 0x07, 0x00 }; + + if (on) { + ret = fts_write_dma_safe(cmd_on, sizeof(cmd_on)); + } else { + ret = fts_write_dma_safe(cmd_off, sizeof(cmd_off)); + } + + if (ret < OK) { + logError(1, + "%s %s: write anti mis-touch cmd on...ERROR %08X !\n", + tag, __func__, ret); + return -EINVAL; + } + logError(1, "%s %s %d\n", tag, __func__, on); + + return 0; +} + +int fts_palm_sensor_write(int value) +{ + int ret = 0; + struct fts_secure_info *scr_info = fts_info->secure_info; + + fts_info->palm_sensor_switch = value; + + if (fts_info->sensor_sleep) { + fts_info->palm_sensor_changed = false; + return 0; + } + + mutex_lock(&scr_info->palm_lock); + if (atomic_read(&scr_info->st_enabled)) { + if (!scr_info->scr_delay.palm_pending) { + scr_info->scr_delay.palm_value = value; + scr_info->scr_delay.palm_pending = true; + } else { + logError(1, "%s already pending,skip", tag); + } + } else { + ret = fts_palm_sensor_cmd(value); + if (!ret) + fts_info->palm_sensor_changed = true; + } + mutex_unlock(&scr_info->palm_lock); + + return ret; +} +#endif +/** + * Resume work function which perform a system reset, clean all the touches from the linux input system and prepare the ground for enabling the sensing + */ +static void fts_resume_work(struct work_struct *work) +{ + struct fts_ts_info *info; + + info = container_of(work, struct fts_ts_info, resume_work); + fts_disableInterrupt(); +#ifdef CONFIG_SECURE_TOUCH + fts_secure_stop(info, true); +#endif + info->resume_bit = 1; +#ifdef CONFIG_FTS_FOD_AREA_REPORT + if (!info->fod_pressed) { +#endif + fts_system_reset(); + release_all_touches(info); +#ifdef CONFIG_FTS_FOD_AREA_REPORT + } +#endif + info->fod_status_set = false; + fts_mode_handler(info, 0); + info->sensor_sleep = false; + info->sleep_finger = 0; + + fts_enableInterrupt(); +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + if (info->palm_sensor_switch && !info->palm_sensor_changed) { + fts_palm_sensor_cmd(info->palm_sensor_switch); + info->palm_sensor_changed = true; + } +#endif +} + +/** + * Suspend work function which clean all the touches from Linux input system and prepare the ground to disabling the sensing or enter in gesture mode + */ +static void fts_suspend_work(struct work_struct *work) +{ + struct fts_ts_info *info; + + info = container_of(work, struct fts_ts_info, suspend_work); +#ifdef CONFIG_SECURE_TOUCH + fts_secure_stop(info, true); +#endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + if (info->palm_sensor_switch) { + logError(1, "%s %s: palm sensor on status, switch to off\n", + tag, __func__); + update_palm_sensor_value(0); + fts_palm_sensor_cmd(0); + info->palm_sensor_switch = false; + } +#endif + fts_disableInterrupt(); + info->resume_bit = 0; + fts_mode_handler(info, 0); + release_all_touches(info); + + info->sensor_sleep = true; + + if (info->gesture_enabled || info->fod_status) + fts_enableInterrupt(); +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + sysfs_notify(&fts_info->fts_touch_dev->kobj, NULL, + "touch_suspend_notify"); +#endif + lpm_disable_for_input(false); +} + +#ifdef CONFIG_DRM +/**@}*/ + +/** + * Callback function used to detect the suspend/resume events generated by clicking the power button. + * This function schedule a suspend or resume work according to the event received. + */ +static int fts_drm_state_chg_callback(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct fts_ts_info *info = + container_of(nb, struct fts_ts_info, notifier); + struct drm_notify_data *evdata = data; + unsigned int blank; + + logError(0, "%s %s: fts notifier begin!\n", tag, __func__); + + if (evdata && evdata->data && info) { + blank = *(int *)(evdata->data); + logError(1, "%s %s: val:%lu,blank:%u\n", tag, __func__, val, + blank); + + if (val == DRM_EARLY_EVENT_BLANK && + (blank == DRM_BLANK_POWERDOWN || blank == DRM_BLANK_LP1 || + blank == DRM_BLANK_LP2)) { + if (info->sensor_sleep) + return NOTIFY_OK; + + logError(1, "%s %s: FB_BLANK %s\n", tag, __func__, + blank == DRM_BLANK_POWERDOWN ? "POWER DOWN" : + "LP"); + + flush_workqueue(info->event_wq); + queue_work(info->event_wq, &info->suspend_work); + } else if (val == DRM_EVENT_BLANK && + blank == DRM_BLANK_UNBLANK) { + if (!info->sensor_sleep) + return NOTIFY_OK; + + logError(1, "%s %s: FB_BLANK_UNBLANK\n", tag, __func__); + + flush_workqueue(info->event_wq); + queue_work(info->event_wq, &info->resume_work); + } + } + return NOTIFY_OK; +} + +static struct notifier_block fts_noti_block = { + .notifier_call = fts_drm_state_chg_callback, +}; +#endif + +static int fts_bl_state_chg_callback(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct fts_ts_info *info = + container_of(nb, struct fts_ts_info, bl_notifier); + unsigned int blank; + int ret; + + if (val != BACKLIGHT_UPDATED) + return NOTIFY_OK; + if (data && info) { + blank = *(int *)(data); + logError(1, "%s %s: val:%lu,blank:%u\n", tag, __func__, val, + blank); + flush_workqueue(info->event_wq); + if (blank == BACKLIGHT_OFF && + (info->fod_status_set && !info->sensor_sleep && + !info->touch_id)) { +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + if (info->p_sensor_switch) { + logError(1, + "%s eardet enabled, skip disableirq\n", + tag, __func__); + return NOTIFY_OK; + } +#endif + if (info->sensor_sleep) + return NOTIFY_OK; + logError(1, "%s %s: BL_EVENT_BLANK\n", tag, __func__); + ret = fts_disableInterrupt(); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + info->sensor_scan = false; + flushFIFO(); + release_all_touches(info); + if (ret < OK) + logError(1, + "%s fts_disableInterrupt ERROR %08X\n", + tag, ret | ERROR_ENABLE_INTER); + } else if (blank == BACKLIGHT_ON) { + logError(1, "%s %s: BL_EVENT_UNBLANK\n", tag, __func__); + if (!info->sensor_sleep) { + ret = fts_enableInterrupt(); + if (ret < OK) + logError( + 1, + "%s fts_enableInterrupt ERROR %08X\n", + tag, ret | ERROR_ENABLE_INTER); + if (!info->sensor_scan) + setScanMode(SCAN_MODE_ACTIVE, 0x01); + } + } + } + return NOTIFY_OK; +} + +static struct notifier_block fts_bl_noti_block = { + .notifier_call = fts_bl_state_chg_callback, +}; + +/** + * From the name of the power regulator get/put the actual regulator structs (copying their references into fts_ts_info variable) + * @param info pointer to fts_ts_info which contains info about the device and its hw setup + * @param get if 1, the regulators are get otherwise they are put (released) back to the system + * @return OK if success or an error code which specify the type of error encountered + */ +static int fts_get_reg(struct fts_ts_info *info, bool get) +{ + int retval; + const struct fts_hw_platform_data *bdata = info->board; + + if (!get) { + retval = 0; + goto regulator_put; + } + + if ((bdata->vdd_reg_name != NULL) && (*bdata->vdd_reg_name != 0)) { + info->vdd_reg = regulator_get(info->dev, bdata->vdd_reg_name); + if (IS_ERR(info->vdd_reg)) { + logError(1, "%s %s: Failed to get power regulator\n", + tag, __func__); + retval = PTR_ERR(info->vdd_reg); + goto regulator_put; + } + } + + if ((bdata->avdd_reg_name != NULL) && (*bdata->avdd_reg_name != 0)) { + info->avdd_reg = regulator_get(info->dev, bdata->avdd_reg_name); + if (IS_ERR(info->avdd_reg)) { + logError(1, + "%s %s: Failed to get bus pullup regulator\n", + tag, __func__); + retval = PTR_ERR(info->avdd_reg); + goto regulator_put; + } + } + + return OK; + +regulator_put: + if (info->vdd_reg) { + regulator_put(info->vdd_reg); + info->vdd_reg = NULL; + } + + if (info->avdd_reg) { + regulator_put(info->avdd_reg); + info->avdd_reg = NULL; + } + + return retval; +} + +/** + * Enable or disable the power regulators + * @param info pointer to fts_ts_info which contains info about the device and its hw setup + * @param enable if 1, the power regulators are turned on otherwise they are turned off + * @return OK if success or an error code which specify the type of error encountered + */ +static int fts_enable_reg(struct fts_ts_info *info, bool enable) +{ + int retval; + + if (!enable) { + retval = 0; + goto disable_pwr_reg; + } + + if (info->vdd_reg) { + retval = regulator_enable(info->vdd_reg); + if (retval < 0) { + logError(1, "%s %s: Failed to enable bus regulator\n", + tag, __func__); + goto exit; + } + } + + if (info->avdd_reg) { + retval = regulator_enable(info->avdd_reg); + if (retval < 0) { + logError(1, "%s %s: Failed to enable power regulator\n", + tag, __func__); + goto disable_bus_reg; + } + } + + return OK; + +disable_pwr_reg: + if (info->avdd_reg) + regulator_disable(info->vdd_reg); + +disable_bus_reg: + if (info->vdd_reg) + regulator_disable(info->avdd_reg); + +exit: + return retval; +} + +/** + * Configure a GPIO according to the parameters + * @param gpio gpio number + * @param config if true, the gpio is set up otherwise it is free + * @param dir direction of the gpio, 0 = in, 1 = out + * @param state initial value (if the direction is in, this parameter is ignored) + * return error code + */ +static int fts_gpio_setup(int gpio, bool config, int dir, int state) +{ + int retval = 0; + unsigned char buf[16]; + + if (config) { + snprintf(buf, 16, "fts_gpio_%u\n", gpio); + + retval = gpio_request(gpio, buf); + if (retval) { + logError(1, "%s %s: Failed to get gpio %d (code: %d)", + tag, __func__, gpio, retval); + return retval; + } + + if (dir == 0) + retval = gpio_direction_input(gpio); + else + retval = gpio_direction_output(gpio, state); + if (retval) { + logError(1, "%s %s: Failed to set gpio %d direction", + tag, __func__, gpio); + return retval; + } + } else { + gpio_free(gpio); + } + + return retval; +} + +/** + * Setup the IRQ and RESET (if present) gpios. + * If the Reset Gpio is present it will perform a cycle HIGH-LOW-HIGH in order to assure that the IC has been reset properly + */ +static int fts_set_gpio(struct fts_ts_info *info) +{ + int retval; + struct fts_hw_platform_data *bdata = info->board; + + retval = fts_gpio_setup(bdata->irq_gpio, true, 0, 0); + if (retval < 0) { + logError(1, "%s %s: Failed to configure irq GPIO\n", tag, + __func__); + goto err_gpio_irq; + } + + if (bdata->reset_gpio >= 0) { + retval = fts_gpio_setup(bdata->reset_gpio, true, 1, 0); + if (retval < 0) { + logError(1, "%s %s: Failed to configure reset GPIO\n", + tag, __func__); + goto err_gpio_reset; + } + } + if (bdata->reset_gpio >= 0) { + gpio_set_value(bdata->reset_gpio, 0); + mdelay(10); + gpio_set_value(bdata->reset_gpio, 1); + } + + return OK; + +err_gpio_reset: + fts_gpio_setup(bdata->irq_gpio, false, 0, 0); + bdata->reset_gpio = GPIO_NOT_DEFINED; +err_gpio_irq: + return retval; +} + +static int fts_pinctrl_init(struct fts_ts_info *info) +{ + int retval = 0; + /* Get pinctrl if target uses pinctrl */ + info->ts_pinctrl = devm_pinctrl_get(info->dev); + + if (IS_ERR_OR_NULL(info->ts_pinctrl)) { + retval = PTR_ERR(info->ts_pinctrl); + dev_err(info->dev, "Target does not use pinctrl %d\n", retval); + goto err_pinctrl_get; + } + + info->pinctrl_state_active = + pinctrl_lookup_state(info->ts_pinctrl, PINCTRL_STATE_ACTIVE); + + if (IS_ERR_OR_NULL(info->pinctrl_state_active)) { + retval = PTR_ERR(info->pinctrl_state_active); + dev_err(info->dev, "Can not lookup %s pinstate %d\n", + PINCTRL_STATE_ACTIVE, retval); + goto err_pinctrl_lookup; + } + + info->pinctrl_state_suspend = + pinctrl_lookup_state(info->ts_pinctrl, PINCTRL_STATE_SUSPEND); + + if (IS_ERR_OR_NULL(info->pinctrl_state_suspend)) { + retval = PTR_ERR(info->pinctrl_state_suspend); + dev_dbg(info->dev, "Can not lookup %s pinstate %d\n", + PINCTRL_STATE_SUSPEND, retval); + goto err_pinctrl_lookup; + } + + return 0; +err_pinctrl_lookup: + devm_pinctrl_put(info->ts_pinctrl); +err_pinctrl_get: + info->ts_pinctrl = NULL; + return retval; +} + +/** + * Retrieve and parse the hw information from the device tree node defined in the system. + * the most important information to obtain are: IRQ and RESET gpio numbers, power regulator names + * In the device file node is possible to define additional optional information that can be parsed here. + */ +static int parse_dt(struct device *dev, struct fts_hw_platform_data *bdata) +{ + int retval; + const char *name; + struct device_node *temp, *np = dev->of_node; + struct fts_config_info *config_info; + u32 temp_val; + + bdata->irq_gpio = of_get_named_gpio_flags(np, "fts,irq-gpio", 0, NULL); + + logError(0, "%s irq_gpio = %d\n", tag, bdata->irq_gpio); + + retval = of_property_read_string(np, "fts,pwr-reg-name", &name); + if (retval == -EINVAL) + bdata->vdd_reg_name = NULL; + else if (retval < 0) + return retval; + else { + bdata->vdd_reg_name = name; + logError(0, "%s pwr_reg_name = %s\n", tag, name); + } + + retval = of_property_read_string(np, "fts,bus-reg-name", &name); + if (retval == -EINVAL) + bdata->avdd_reg_name = NULL; + else if (retval < 0) + return retval; + else { + bdata->avdd_reg_name = name; + logError(0, "%s bus_reg_name = %s\n", tag, name); + } + + if (of_property_read_bool(np, "fts,reset-gpio-enable")) { + bdata->reset_gpio = + of_get_named_gpio_flags(np, "fts,reset-gpio", 0, NULL); + logError(0, "%s reset_gpio =%d\n", tag, bdata->reset_gpio); + } else { + bdata->reset_gpio = GPIO_NOT_DEFINED; + } + + retval = of_property_read_u32(np, "fts,irq-flags", &temp_val); + if (retval < 0) + return retval; + else + bdata->irq_flags = temp_val; + retval = of_property_read_u32(np, "fts,x-max", &temp_val); + if (retval < 0) + bdata->x_max = X_AXIS_MAX; + else + bdata->x_max = temp_val; + + retval = of_property_read_u32(np, "fts,y-max", &temp_val); + if (retval < 0) + bdata->y_max = Y_AXIS_MAX; + else + bdata->y_max = temp_val; + retval = of_property_read_string(np, "fts,default-fw-name", + &bdata->default_fw_name); + +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + bdata->dump_click_count = + of_property_read_bool(np, "fts,dump-click-count"); +#endif + retval = of_property_read_u32(np, "fts,config-array-size", + (u32 *)&bdata->config_array_size); + + if (retval) { + logError(1, "%s Unable to get array size\n", tag); + return retval; + } + + bdata->config_array = devm_kzalloc( + dev, bdata->config_array_size * sizeof(struct fts_config_info), + GFP_KERNEL); + + if (!bdata->config_array) { + logError(1, "%s Unable to allocate memory\n", tag); + return -ENOMEM; + } + + config_info = bdata->config_array; + for_each_child_of_node(np, temp) { + retval = of_property_read_u32(temp, "fts,tp-vendor", &temp_val); + + if (retval) { + logError(1, "%s Unable to read tp vendor\n", tag); + } else { + config_info->tp_vendor = (u8)temp_val; + logError(1, "%s %s:tp vendor: %u", tag, __func__, + config_info->tp_vendor); + } + retval = of_property_read_u32(temp, "fts,tp-color", &temp_val); + if (retval) { + logError(1, "%s Unable to read tp color\n", tag); + } else { + config_info->tp_color = (u8)temp_val; + logError(1, "%s %s:tp color: %u", tag, __func__, + config_info->tp_color); + } + + retval = of_property_read_u32(temp, "fts,tp-hw-version", + &temp_val); + + if (retval) { + logError(1, "%s Unable to read tp hw version\n", tag); + } else { + config_info->tp_hw_version = (u8)temp_val; + logError(1, "%s %s:tp color: %u", tag, __func__, + config_info->tp_hw_version); + } + + retval = of_property_read_string(temp, "fts,fw-name", + &config_info->fts_cfg_name); + + if (retval && (retval != -EINVAL)) { + logError(1, "%s Unable to read cfg name\n", tag); + } else { + logError(1, "%s %s:fw_name: %s", tag, __func__, + config_info->fts_cfg_name); + } + retval = of_property_read_string(temp, "fts,limit-name", + &config_info->fts_limit_name); + + if (retval && (retval != -EINVAL)) { + logError(1, "%s Unable to read limit name\n", tag); + } else { + logError(1, "%s %s:limit_name: %s", tag, __func__, + config_info->fts_limit_name); + } +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + if (bdata->dump_click_count) { + retval = of_property_read_string( + temp, "fts,clicknum-file-name", + &config_info->clicknum_file_name); + if (retval && (retval != -EINVAL)) { + dev_err(dev, + "Unable to read click count file name\n"); + } else + dev_err(dev, "%s\n", + config_info->clicknum_file_name); + } +#endif + + config_info++; + } + return OK; +} + +static void fts_switch_mode_work(struct work_struct *work) +{ + struct fts_mode_switch *ms = + container_of(work, struct fts_mode_switch, switch_mode_work); + + struct fts_ts_info *info = ms->info; + unsigned char value = ms->mode; + static const char *fts_gesture_on = "01 20"; + char *gesture_result; + int size = 6 * 2 + 1; + char ch[16] = { + 0x0, + }; + + logError(1, "%s %s mode:%d\n", tag, __func__, value); + + if (value >= INPUT_EVENT_WAKUP_MODE_OFF && + value <= INPUT_EVENT_WAKUP_MODE_ON) { + info->gesture_enabled = value - INPUT_EVENT_WAKUP_MODE_OFF; + if (info->gesture_enabled) { + gesture_result = (u8 *)kzalloc(size, GFP_KERNEL); + if (gesture_result != NULL) { + fts_gesture_mask_store(info->dev, NULL, + fts_gesture_on, + strlen(fts_gesture_on)); + fts_gesture_mask_show(info->dev, NULL, + gesture_result); + if (strncmp("{ 00000000 }", gesture_result, + size - 1)) + logError( + 1, + "%s %s:store gesture mask error\n", + tag, __func__); + kfree(gesture_result); + gesture_result = NULL; + } + } + snprintf(ch, sizeof(ch), "%s", + (value - INPUT_EVENT_WAKUP_MODE_OFF) ? "enabled" : + "disabled"); + } else if (value >= INPUT_EVENT_COVER_MODE_OFF && + value <= INPUT_EVENT_COVER_MODE_ON) { + info->glove_enabled = value - INPUT_EVENT_COVER_MODE_OFF; + fts_mode_handler(info, 1); + } +#ifdef EDGEHOVER_FOR_VOLUME + if (value >= INPUT_EVENT_SLIDE_FOR_VOLUME && + value <= INPUT_EVENT_LONG_SINGLE_TAP_FOR_VOLUME) { + info->volume_type = value; + if (fts_info->volume_type == + INPUT_EVENT_SINGLE_TAP_FOR_VOLUME) { + fts_info->single_press_time_low = 30; + fts_info->single_press_time_hi = 800; + } else if (fts_info->volume_type == + INPUT_EVENT_LONG_SINGLE_TAP_FOR_VOLUME) { + fts_info->single_press_time_low = 300; + fts_info->single_press_time_hi = 800; + } + } +#endif +#ifdef PHONE_PALM + if (value >= INPUT_EVENT_PALM_OFF && value <= INPUT_EVENT_PALM_ON) + info->palm_enabled = value - INPUT_EVENT_PALM_OFF; +#endif + if (ms != NULL) { + kfree(ms); + ms = NULL; + } +} + +static int fts_input_event(struct input_dev *dev, unsigned int type, + unsigned int code, int value) +{ + struct fts_ts_info *info = input_get_drvdata(dev); + struct fts_mode_switch *ms; + + logError(1, "%s %s:set input event value = %d\n", tag, __func__, value); + + if (!info) { + printk("%s fts_ts_info is NULL\n", __func__); + return 0; + } + + if (type == EV_SYN && code == SYN_CONFIG) { + if (value >= INPUT_EVENT_START && value <= INPUT_EVENT_END) { + ms = (struct fts_mode_switch *)kmalloc( + sizeof(struct fts_mode_switch), GFP_ATOMIC); + + if (ms != NULL) { + ms->info = info; + ms->mode = (unsigned char)value; + INIT_WORK(&ms->switch_mode_work, + fts_switch_mode_work); + schedule_work(&ms->switch_mode_work); + } else { + logError( + 1, + "%s %s:failed in allocating memory for switching mode\n", + tag, __func__); + return -ENOMEM; + } + } else { + logError(1, "%s %s:Invalid event value\n", tag, + __func__); + return -EINVAL; + } + } + + return 0; +} + +static int fts_short_open_test(void) +{ + TestToDo selftests; + int res = -1; + int init_type = SPECIAL_PANEL_INIT; + + memset(&selftests, 0x00, sizeof(TestToDo)); + + /* Hover Test */ + selftests.SelfHoverForceRaw = 0; /* SS Hover Force Raw min/Max test */ + selftests.SelfHoverSenceRaw = 0; /* SS Hover Sence Raw min/Max test */ + selftests.SelfHoverForceIxTotal = + 0; /* SS Hover Total Force Ix min/Max (for each node)* test */ + selftests.SelfHoverSenceIxTotal = 0; + + selftests.MutualRawAdjITO = 0; + selftests.MutualRaw = 0; + selftests.MutualRawEachNode = 1; + selftests.MutualRawGap = 0; + selftests.MutualRawAdj = 0; + selftests.MutualRawLP = 0; + selftests.MutualRawGapLP = 0; + selftests.MutualRawAdjLP = 0; + selftests.MutualCx1 = 0; + selftests.MutualCx2 = 0; + selftests.MutualCx2Adj = 0; + selftests.MutualCxTotal = 0; + selftests.MutualCxTotalAdj = 0; + selftests.MutualCx1LP = 0; + selftests.MutualCx2LP = 0; + selftests.MutualCx2AdjLP = 0; + selftests.MutualCxTotalLP = 0; + selftests.MutualCxTotalAdjLP = 0; +#ifdef PHONE_KEY + selftests.MutualKeyRaw = 0; +#else + selftests.MutualKeyRaw = 0; +#endif + selftests.MutualKeyCx1 = 0; + selftests.MutualKeyCx2 = 0; +#ifdef PHONE_KEY + selftests.MutualKeyCxTotal = 0; +#else + selftests.MutualKeyCxTotal = 0; +#endif + selftests.SelfForceRaw = 1; + selftests.SelfForceRawGap = 0; + selftests.SelfForceRawLP = 0; + selftests.SelfForceRawGapLP = 0; + selftests.SelfForceIx1 = 0; + selftests.SelfForceIx2 = 0; + selftests.SelfForceIx2Adj = 0; + selftests.SelfForceIxTotal = 0; + selftests.SelfForceIxTotalAdj = 0; + selftests.SelfForceCx1 = 0; + selftests.SelfForceCx2 = 0; + selftests.SelfForceCx2Adj = 0; + selftests.SelfForceCxTotal = 0; + selftests.SelfForceCxTotalAdj = 0; + selftests.SelfSenseRaw = 1; + selftests.SelfSenseRawGap = 0; + selftests.SelfSenseRawLP = 0; + selftests.SelfSenseRawGapLP = 0; + selftests.SelfSenseIx1 = 0; + selftests.SelfSenseIx2 = 0; + selftests.SelfSenseIx2Adj = 0; + selftests.SelfSenseIxTotal = 0; + selftests.SelfSenseIxTotalAdj = 0; + selftests.SelfSenseCx1 = 0; + selftests.SelfSenseCx2 = 0; + selftests.SelfSenseCx2Adj = 0; + selftests.SelfSenseCxTotal = 0; + selftests.SelfSenseCxTotalAdj = 0; + + res = fts_disableInterrupt(); + if (res < 0) { + logError(0, "%s fts_disableInterrupt: ERROR %08X \n", tag, res); + res = (res | ERROR_DISABLE_INTER); + goto END; + } + res = production_test_main(LIMITS_FILE, 1, init_type, &selftests); +END: + fts_mode_handler(fts_info, 1); + fts_enableInterrupt(); + if (res == OK) + return FTS_RESULT_PASS; + else + return FTS_RESULT_FAIL; +} + +static int fts_i2c_test(void) +{ + int ret = 0; + u8 data[SYS_INFO_SIZE] = { 0 }; + + logError(0, "%s %s: Reading System Info...\n", tag, __func__); + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, + ADDR_FRAMEBUFFER, data, SYS_INFO_SIZE, + DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading the system data ERROR %08X\n", + tag, __func__, ret); + return FTS_RESULT_FAIL; + } + + return FTS_RESULT_PASS; +} + +static ssize_t fts_selftest_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + char tmp[5] = { 0 }; + int cnt; + + if (*pos != 0) + return 0; + cnt = snprintf(tmp, sizeof(fts_info->result_type), "%d\n", + fts_info->result_type); + if (copy_to_user(buf, tmp, strlen(tmp))) { + return -EFAULT; + } + *pos += cnt; + return cnt; +} + +static ssize_t fts_selftest_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + int retval = 0; + char tmp[6]; + + if (copy_from_user(tmp, buf, count)) { + retval = -EFAULT; + goto out; + } + + if (!strncmp("short", tmp, 5) || !strncmp("open", tmp, 4)) { + retval = fts_short_open_test(); + } else if (!strncmp("i2c", tmp, 3)) + retval = fts_i2c_test(); + + fts_info->result_type = retval; +out: + if (retval >= 0) + retval = count; + + return retval; +} + +static const struct file_operations fts_selftest_ops = { + .read = fts_selftest_read, + .write = fts_selftest_write, +}; + +static ssize_t fts_datadump_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + int ret = 0, cnt1 = 0, cnt2 = 0, cnt3 = 0; + char *tmp; + + if (*pos != 0) + return 0; + + tmp = vmalloc(PAGE_SIZE * 2); + if (tmp == NULL) + return 0; + else + memset(tmp, 0, PAGE_SIZE * 2); + + cnt1 = fts_strength_frame_show(fts_info->dev, NULL, tmp); + if (cnt1 == 0) { + ret = 0; + goto out; + } + + ret = stm_fts_cmd_store(fts_info->dev, NULL, "13", 2); + if (ret == 0) + goto out; + cnt2 = stm_fts_cmd_show(fts_info->dev, NULL, tmp + cnt1); + if (cnt2 == 0) { + ret = 0; + goto out; + } + + ret = stm_fts_cmd_store(fts_info->dev, NULL, "15", 2); + if (ret == 0) + goto out; + cnt3 = stm_fts_cmd_show(fts_info->dev, NULL, tmp + cnt1 + cnt2); + if (cnt3 == 0) { + ret = 0; + goto out; + } + + if (copy_to_user(buf, tmp, cnt1 + cnt2 + cnt3)) + ret = -EFAULT; + +out: + if (tmp) { + vfree(tmp); + tmp = NULL; + } + *pos += (cnt1 + cnt2 + cnt3); + if (ret <= 0) + return ret; + return cnt1 + cnt2 + cnt3; +} + +static const struct file_operations fts_datadump_ops = { + .read = fts_datadump_read, +}; + +#define TP_INFO_MAX_LENGTH 50 + +static ssize_t fts_fw_version_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + int cnt = 0, ret = 0; + char tmp[TP_INFO_MAX_LENGTH]; + + if (*pos != 0) + return 0; + + cnt = snprintf(tmp, TP_INFO_MAX_LENGTH, "%x.%x\n", systemInfo.u16_fwVer, + systemInfo.u16_cfgVer); + ret = copy_to_user(buf, tmp, cnt); + *pos += cnt; + if (ret != 0) + return 0; + else + return cnt; +} + +static const struct file_operations fts_fw_version_ops = { + .read = fts_fw_version_read, +}; + +static ssize_t fts_lockdown_info_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + int cnt = 0, ret = 0; + char tmp[TP_INFO_MAX_LENGTH]; + + if (*pos != 0) + return 0; + + ret = fts_get_lockdown_info(fts_info->lockdown_info, fts_info); + if (ret != OK) { + logError(1, "%s %s get lockdown info error\n", tag, __func__); + goto out; + } + + cnt = snprintf( + tmp, TP_INFO_MAX_LENGTH, + "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + fts_info->lockdown_info[0], fts_info->lockdown_info[1], + fts_info->lockdown_info[2], fts_info->lockdown_info[3], + fts_info->lockdown_info[4], fts_info->lockdown_info[5], + fts_info->lockdown_info[6], fts_info->lockdown_info[7]); + ret = copy_to_user(buf, tmp, cnt); +out: + *pos += cnt; + if (ret != 0) + return 0; + else + return cnt; +} + +static const struct file_operations fts_lockdown_info_ops = { + .read = fts_lockdown_info_read, +}; + +#ifdef CONFIG_PM +static int fts_pm_suspend(struct device *dev) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + +#ifndef CONFIG_FTS_FOD_AREA_REPORT + if (device_may_wakeup(dev) && info->gesture_enabled) { + logError(1, "%s enable touch irq wake\n", tag); + enable_irq_wake(info->client->irq); + } +#else + enable_irq_wake(info->client->irq); +#endif + info->tp_pm_suspend = true; + reinit_completion(&info->pm_resume_completion); + + return 0; +} + +static int fts_pm_resume(struct device *dev) +{ + struct fts_ts_info *info = dev_get_drvdata(dev); + +#ifndef CONFIG_FTS_FOD_AREA_REPORT + if (device_may_wakeup(dev) && info->gesture_enabled) { + logError(1, "%s disable touch irq wake\n", tag); + disable_irq_wake(info->client->irq); + } +#else + disable_irq_wake(info->client->irq); +#endif + info->tp_pm_suspend = false; + complete(&info->pm_resume_completion); + + return 0; +} + +static const struct dev_pm_ops fts_dev_pm_ops = { + .suspend = fts_pm_suspend, + .resume = fts_pm_resume, +}; +#endif + +#ifdef CONFIG_TOUCHSCREEN_ST_DEBUG_FS +static void tpdbg_shutdown(struct fts_ts_info *info, bool sleep) +{ + u8 settings[4] = { 0 }; + info->mode = MODE_NOTHING; + + if (sleep) { + logError(0, "%s %s: Sense OFF! \n", tag, __func__); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + } else { + settings[0] = 0x01; + logError(0, "%s %s: Sense ON! \n", tag, __func__); + setScanMode(SCAN_MODE_ACTIVE, settings[0]); + info->mode |= (SCAN_MODE_ACTIVE << 24); + MODE_ACTIVE(info->mode, settings[0]); + } +} + +static void tpdbg_suspend(struct fts_ts_info *info, bool enable) +{ + if (enable) + queue_work(info->event_wq, &info->suspend_work); + else + queue_work(info->event_wq, &info->resume_work); +} + +static int tpdbg_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + + return 0; +} + +static ssize_t tpdbg_read(struct file *file, char __user *buf, size_t size, + loff_t *ppos) +{ + const char *str = "cmd support as below:\n \ + \necho \"irq-disable\" or \"irq-enable\" to ctrl irq\n \ + \necho \"tp-sd-en\" of \"tp-sd-off\" to ctrl panel in or off sleep mode\n \ + \necho \"tp-suspend-en\" or \"tp-suspend-off\" to ctrl panel in or off suspend status\n"; + + loff_t pos = *ppos; + int len = strlen(str); + + if (pos < 0) + return -EINVAL; + if (pos >= len) + return 0; + + if (copy_to_user(buf, str, len)) + return -EFAULT; + + *ppos = pos + len; + + return len; +} + +static ssize_t tpdbg_write(struct file *file, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct fts_ts_info *info = file->private_data; + char *cmd = kzalloc(size + 1, GFP_KERNEL); + int ret = size; + + if (!cmd) + return -ENOMEM; + + if (copy_from_user(cmd, buf, size)) { + ret = -EFAULT; + goto out; + } + + cmd[size] = '\0'; + + if (!strncmp(cmd, "irq-disable", 11)) + disable_irq(info->client->irq); + else if (!strncmp(cmd, "irq-enable", 10)) + enable_irq(info->client->irq); + else if (!strncmp(cmd, "tp-sd-en", 8)) + tpdbg_shutdown(info, true); + else if (!strncmp(cmd, "tp-sd-off", 9)) + tpdbg_shutdown(info, false); + else if (!strncmp(cmd, "tp-suspend-en", 13)) + tpdbg_suspend(info, true); + else if (!strncmp(cmd, "tp-suspend-off", 14)) + tpdbg_suspend(info, false); +out: + kfree(cmd); + + return ret; +} + +static int tpdbg_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + + return 0; +} + +static const struct file_operations tpdbg_operations = { + .owner = THIS_MODULE, + .open = tpdbg_open, + .read = tpdbg_read, + .write = tpdbg_write, + .release = tpdbg_release, +}; +#endif + +#ifdef CONFIG_SECURE_TOUCH +int fts_secure_init(struct fts_ts_info *info) +{ + int ret; + struct fts_secure_info *scr_info = + kmalloc(sizeof(*scr_info), GFP_KERNEL); + if (!scr_info) { + logError(1, "%s %s alloc fts_secure_info failed\n", tag, + __func__); + return -ENOMEM; + } + + logError(1, "%s fts_secure_init\n", tag); + + mutex_init(&scr_info->palm_lock); + + init_completion(&scr_info->st_powerdown); + init_completion(&scr_info->st_irq_processed); + + atomic_set(&scr_info->st_enabled, 0); + atomic_set(&scr_info->st_pending_irqs, 0); + + info->secure_info = scr_info; + + ret = sysfs_create_file(&info->dev->kobj, + &dev_attr_secure_touch_enable.attr); + if (ret < 0) { + logError( + 1, + "%s %s create sysfs attribute secure_touch_enable failed\n", + tag, __func__); + goto err; + } + + ret = sysfs_create_file(&info->dev->kobj, &dev_attr_secure_touch.attr); + if (ret < 0) { + logError(1, + "%s %s create sysfs attribute secure_touch failed\n", + tag, __func__); + goto err; + } + + scr_info->fts_info = info; + scr_info->secure_inited = true; + + return 0; + +err: + kfree(scr_info); + info->secure_info = NULL; + return ret; +} + +void fts_secure_remove(struct fts_ts_info *info) +{ + struct fts_secure_info *scr_info = info->secure_info; + + sysfs_remove_file(&info->dev->kobj, &dev_attr_secure_touch_enable.attr); + sysfs_remove_file(&info->dev->kobj, &dev_attr_secure_touch.attr); + kfree(scr_info); +} + +#endif + +/** + * Probe function, called when the driver it is matched with a device with the same name compatible name + * This function allocate, initialize and define all the most important function and flow that are used by the driver to operate with the IC. + * It allocates device variables, initialize queues and schedule works, registers the IRQ handler, suspend/resume callbacks, registers the device to the linux input subsystem etc. + */ +#ifdef I2C_INTERFACE +static int fts_probe(struct i2c_client *client, const struct i2c_device_id *idp) +{ +#else +static int fts_probe(struct spi_device *client) +{ +#endif + + struct fts_ts_info *info = NULL; + int error = 0; + struct device_node *dp = client->dev.of_node; + int retval; + int skip_5_1 = 0; + u16 bus_type; + u8 *tp_maker; + + logError(1, "%s %s: driver ver: %s\n", tag, __func__, + FTS_TS_DRV_VERSION); + +#ifdef I2C_INTERFACE + logError(0, "%s I2C interface... \n", tag); + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + logError(1, "%s Unsupported I2C functionality\n", tag); + error = -EIO; + goto ProbeErrorExit_0; + } + + logError(0, "%s i2c address: %x \n", tag, client->addr); + bus_type = BUS_I2C; +#else + logError(0, "%s SPI interface... \n", tag); + client->mode = SPI_MODE_0; +#ifndef SPI4_WIRE + client->mode |= SPI_3WIRE; +#endif + client->max_speed_hz = SPI_CLOCK_FREQ; + client->bits_per_word = 8; + if (spi_setup(client) < 0) { + logError(1, "%s Unsupported SPI functionality\n", tag); + error = -EIO; + goto ProbeErrorExit_0; + } + bus_type = BUS_SPI; +#endif + + logError(0, "%s SET Device driver INFO: \n", tag); + + info = kzalloc(sizeof(struct fts_ts_info), GFP_KERNEL); + if (!info) { + logError( + 1, + "%s Out of memory... Impossible to allocate struct info!\n", + tag); + error = -ENOMEM; + goto ProbeErrorExit_0; + } + + fts_info = info; + info->client = client; + info->dev = &info->client->dev; + dev_set_drvdata(info->dev, info); + + if (dp) { + info->board = devm_kzalloc(&client->dev, + sizeof(struct fts_hw_platform_data), + GFP_KERNEL); + if (!info->board) { + logError(1, "%s ERROR:info.board kzalloc failed \n", + tag); + error = -ENOMEM; + goto ProbeErrorExit_1; + } + parse_dt(&client->dev, info->board); + } + + logError(0, "%s SET Regulators: \n", tag); + retval = fts_get_reg(info, true); + if (retval < 0) { + logError(1, "%s ERROR: %s: Failed to get regulators\n", tag, + __func__); + error = retval; + goto ProbeErrorExit_1; + } + + retval = fts_enable_reg(info, true); + if (retval < 0) { + logError(1, "%s %s: ERROR Failed to enable regulators\n", tag, + __func__); + error = retval; + goto ProbeErrorExit_2; + } + + logError(0, "%s SET GPIOS: \n", tag); + retval = fts_set_gpio(info); + if (retval < 0) { + logError(1, "%s %s: ERROR Failed to set up GPIO's\n", tag, + __func__); + error = retval; + goto ProbeErrorExit_2; + } + + error = fts_pinctrl_init(info); + + if (!error && info->ts_pinctrl) { + error = pinctrl_select_state(info->ts_pinctrl, + info->pinctrl_state_active); + + if (error < 0) { + dev_err(&client->dev, + "%s: Failed to select %s pinstate %d\n", + __func__, PINCTRL_STATE_ACTIVE, error); + } + } else { + dev_err(&client->dev, "%s: Failed to init pinctrl\n", __func__); + } + + info->client->irq = gpio_to_irq(info->board->irq_gpio); + + logError(0, "%s SET Event Handler: \n", tag); + + info->event_wq = + alloc_workqueue("fts-event-queue", + WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!info->event_wq) { + logError(1, "%s ERROR: Cannot create work thread\n", tag); + error = -ENOMEM; + goto ProbeErrorExit_4; + } + + info->irq_wq = alloc_workqueue( + "fts-irq-queue", WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!info->irq_wq) { + logError(1, "%s ERROR: Cannot create irq work thread\n", tag); + error = -ENOMEM; + goto ProbeErrorExit_4; + } + + INIT_WORK(&info->resume_work, fts_resume_work); + INIT_WORK(&info->suspend_work, fts_suspend_work); + INIT_WORK(&info->sleep_work, fts_ts_sleep_work); + init_completion(&info->tp_reset_completion); +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + init_waitqueue_head(&info->wait_queue); +#endif + logError(0, "%s SET Input Device Property: \n", tag); + info->dev = &info->client->dev; + info->input_dev = input_allocate_device(); + if (!info->input_dev) { + logError(1, "%s ERROR: No such input device defined! \n", tag); + error = -ENODEV; + goto ProbeErrorExit_5; + } + info->input_dev->dev.parent = &client->dev; + info->input_dev->name = FTS_TS_DRV_NAME; + snprintf(fts_ts_phys, sizeof(fts_ts_phys), "%s/input0", + info->input_dev->name); + info->input_dev->phys = fts_ts_phys; + info->input_dev->id.bustype = bus_type; + info->input_dev->id.vendor = 0x0001; + info->input_dev->id.product = 0x0002; + info->input_dev->id.version = 0x0100; + info->input_dev->event = fts_input_event; + input_set_drvdata(info->input_dev, info); + + __set_bit(EV_SYN, info->input_dev->evbit); + __set_bit(EV_KEY, info->input_dev->evbit); + __set_bit(EV_ABS, info->input_dev->evbit); + __set_bit(BTN_TOUCH, info->input_dev->keybit); + __set_bit(BTN_TOOL_FINGER, info->input_dev->keybit); + /*__set_bit(BTN_TOOL_PEN, info->input_dev->keybit);*/ + + input_mt_init_slots(info->input_dev, TOUCH_ID_MAX, INPUT_MT_DIRECT); + + /*input_mt_init_slots(info->input_dev, TOUCH_ID_MAX); */ + + input_set_abs_params(info->input_dev, ABS_MT_POSITION_X, X_AXIS_MIN, + info->board->x_max - 1, 0, 0); + input_set_abs_params(info->input_dev, ABS_MT_POSITION_Y, Y_AXIS_MIN, + info->board->y_max - 1, 0, 0); + input_set_abs_params(info->input_dev, ABS_MT_TOUCH_MAJOR, AREA_MIN, + AREA_MAX, 0, 0); + input_set_abs_params(info->input_dev, ABS_MT_TOUCH_MINOR, AREA_MIN, + AREA_MAX, 0, 0); + input_set_abs_params(info->input_dev, ABS_MT_WIDTH_MINOR, AREA_MIN, + AREA_MAX, 0, 0); + input_set_abs_params(info->input_dev, ABS_MT_WIDTH_MAJOR, AREA_MIN, + AREA_MAX, 0, 0); + +#ifdef CONFIG_FTS_FOD_AREA_REPORT + /*input_set_abs_params(info->input_dev, ABS_MT_PRESSURE, PRESSURE_MIN, PRESSURE_MAX, 0, 0);*/ +#endif + input_set_abs_params(info->input_dev, ABS_MT_DISTANCE, DISTANCE_MIN, + DISTANCE_MAX, 0, 0); + +#ifdef GESTURE_MODE + input_set_capability(info->input_dev, EV_KEY, KEY_WAKEUP); + + input_set_capability(info->input_dev, EV_KEY, KEY_M); + input_set_capability(info->input_dev, EV_KEY, KEY_O); + input_set_capability(info->input_dev, EV_KEY, KEY_E); + input_set_capability(info->input_dev, EV_KEY, KEY_W); + input_set_capability(info->input_dev, EV_KEY, KEY_C); + input_set_capability(info->input_dev, EV_KEY, KEY_L); + input_set_capability(info->input_dev, EV_KEY, KEY_F); + input_set_capability(info->input_dev, EV_KEY, KEY_V); + input_set_capability(info->input_dev, EV_KEY, KEY_S); + input_set_capability(info->input_dev, EV_KEY, KEY_Z); + input_set_capability(info->input_dev, EV_KEY, KEY_WWW); + + input_set_capability(info->input_dev, EV_KEY, KEY_LEFT); + input_set_capability(info->input_dev, EV_KEY, KEY_RIGHT); + input_set_capability(info->input_dev, EV_KEY, KEY_UP); + input_set_capability(info->input_dev, EV_KEY, KEY_DOWN); + + input_set_capability(info->input_dev, EV_KEY, KEY_F1); + input_set_capability(info->input_dev, EV_KEY, KEY_F2); + input_set_capability(info->input_dev, EV_KEY, KEY_F3); + input_set_capability(info->input_dev, EV_KEY, KEY_F4); + input_set_capability(info->input_dev, EV_KEY, KEY_F5); + + input_set_capability(info->input_dev, EV_KEY, KEY_LEFTBRACE); + input_set_capability(info->input_dev, EV_KEY, KEY_RIGHTBRACE); +#endif + +#ifdef PHONE_KEY + /*KEY associated to the touch screen buttons */ + input_set_capability(info->input_dev, EV_KEY, KEY_HOMEPAGE); + input_set_capability(info->input_dev, EV_KEY, KEY_BACK); + input_set_capability(info->input_dev, EV_KEY, KEY_MENU); +#endif +#ifdef CONFIG_FTS_FOD_AREA_REPORT + input_set_capability(info->input_dev, EV_KEY, BTN_INFO); + input_set_capability(info->input_dev, EV_KEY, KEY_INFO); + input_set_capability(info->input_dev, EV_KEY, KEY_GOTO); +#endif + mutex_init(&(info->input_report_mutex)); +#ifdef GESTURE_MODE + mutex_init(&gestureMask_mutex); +#endif + + spin_lock_init(&fts_int); + + /* register the multi-touch input device */ + error = input_register_device(info->input_dev); + if (error) { + logError(1, "%s ERROR: No such input device\n", tag); + error = -ENODEV; + goto ProbeErrorExit_5_1; + } + + skip_5_1 = 1; + /* track slots */ + info->touch_id = 0; +#ifdef STYLUS_MODE + info->stylus_id = 0; +#endif + + /* init feature switches (by default all the features are disable, if one feature want to be enabled from the start, set the corresponding value to 1) */ + info->gesture_enabled = 0; + info->glove_enabled = 0; + info->charger_enabled = 0; + info->cover_enabled = 0; + info->grip_enabled = 0; + info->grip_pixel_def = 30; + info->grip_pixel = info->grip_pixel_def; + + info->resume_bit = 1; + info->lockdown_is_ok = false; +#ifdef CONFIG_DRM + info->notifier = fts_noti_block; +#endif + info->bl_notifier = fts_bl_noti_block; + logError(0, "%s Init Core Lib: \n", tag); + initCore(info); + /* init hardware device */ + logError(0, "%s Device Initialization: \n", tag); + error = fts_init(info); + if (error < OK) { + logError(1, "%s Cannot initialize the device ERROR %08X\n", tag, + error); + error = -ENODEV; + goto ProbeErrorExit_6; + } + +#ifdef CONFIG_SECURE_TOUCH + logError(1, "%s %s create secure touch file...\n", tag, __func__); + error = fts_secure_init(info); + if (error < 0) { + logError(1, "%s %s init secure touch failed\n", tag, __func__); + goto ProbeErrorExit_7; + } + logError(1, "%s %s create secure touch file successful\n", tag, + __func__); + fts_secure_stop(info, 1); +#endif + +#ifdef CONFIG_I2C_BY_DMA + /*dma buf init*/ + info->dma_buf = (struct fts_dma_buf *)kzalloc(sizeof(*info->dma_buf), + GFP_KERNEL); + if (!info->dma_buf) { + logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); + goto ProbeErrorExit_7; + } + mutex_init(&info->dma_buf->dmaBufLock); + info->dma_buf->rdBuf = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (!info->dma_buf->rdBuf) { + logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); + goto ProbeErrorExit_7; + } + info->dma_buf->wrBuf = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (!info->dma_buf->wrBuf) { + logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); + goto ProbeErrorExit_7; + } +#endif + + error = fts_get_lockdown_info(info->lockdown_info, info); + + if (error < OK) + logError(1, "%s can't get lockdown info", tag); + else { + logError( + 1, + "%s Lockdown:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + tag, info->lockdown_info[0], info->lockdown_info[1], + info->lockdown_info[2], info->lockdown_info[3], + info->lockdown_info[4], info->lockdown_info[5], + info->lockdown_info[6], info->lockdown_info[7]); + info->lockdown_is_ok = true; + } + +#ifdef FW_UPDATE_ON_PROBE + logError(1, "%s FW Update and Sensing Initialization: \n", tag); + error = fts_fw_update(info, NULL, 0); + if (error < OK) { + logError(1, + "%s Cannot execute fw upgrade the device ERROR %08X\n", + tag, error); + error = -ENODEV; + goto ProbeErrorExit_7; + } +#else + logError(0, "%s SET Auto Fw Update: \n", tag); + info->fwu_workqueue = alloc_workqueue( + "fts-fwu-queue", WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!info->fwu_workqueue) { + logError(1, "%s ERROR: Cannot create fwu work thread\n", tag); + goto ProbeErrorExit_7; + } + INIT_DELAYED_WORK(&info->fwu_work, fts_fw_update_auto); +#endif + info->sensor_scan = true; + + logError(0, "%s SET Device File Nodes: \n", tag); + /* sysfs stuff */ + info->attrs.attrs = fts_attr_group; + error = sysfs_create_group(&client->dev.kobj, &info->attrs); + if (error) { + logError(1, "%s ERROR: Cannot create sysfs structure!\n", tag); + error = -ENODEV; + goto ProbeErrorExit_7; + } + + error = fts_proc_init(); + if (error < OK) + logError(1, "%s Error: can not create /proc file! \n", tag); + info->dbclick_count = 0; + + tp_maker = kzalloc(20, GFP_KERNEL); + if (tp_maker == NULL) + logError(1, "%s fail to alloc vendor name memory\n", tag); + else { + kfree(tp_maker); + tp_maker = NULL; + } + device_init_wakeup(&client->dev, 1); + init_completion(&info->pm_resume_completion); +/* + if (backlight_register_notifier(&info->bl_notifier) < 0) { + logError(1, "%s register bl_notifier failed!\n", tag); + } +*/ +#ifdef CONFIG_TOUCHSCREEN_ST_DEBUG_FS + info->debugfs = debugfs_create_dir("tp_debug", NULL); + if (info->debugfs) { + debugfs_create_file("switch_state", 0660, info->debugfs, info, + &tpdbg_operations); + } +#endif + + if (info->fts_tp_class == NULL) +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + info->fts_tp_class = get_xiaomi_touch_class(); +#else + info->fts_tp_class = class_create(THIS_MODULE, "touch"); +#endif + info->fts_touch_dev = + device_create(info->fts_tp_class, NULL, 0x49, info, "tp_dev"); + + if (IS_ERR(info->fts_touch_dev)) { + logError(1, + "%s ERROR: Failed to create device for the sysfs!\n", + tag); + goto ProbeErrorExit_8; + } + + dev_set_drvdata(info->fts_touch_dev, info); +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + error = sysfs_create_file(&info->fts_touch_dev->kobj, + &dev_attr_touch_suspend_notify.attr); + + if (error) { + logError(1, "%s ERROR: Failed to create sysfs group!\n", tag); + goto ProbeErrorExit_8; + } +#endif +#ifdef CONFIG_FTS_FOD_AREA_REPORT + mutex_init(&(info->fod_mutex)); + + error = sysfs_create_file(&info->fts_touch_dev->kobj, + &dev_attr_fod_status.attr); + if (error) { + logError(1, + "%s ERROR: Failed to create fod_status sysfs group!\n", + tag); + } + error = sysfs_create_file(&info->fts_touch_dev->kobj, + &dev_attr_fod_test.attr); + if (error) { + logError(1, + "%s ERROR: Failed to create fod_test sysfs group!\n", + tag); + } +#endif + info->tp_lockdown_info_proc = proc_create("tp_lockdown_info", 0444, + NULL, &fts_lockdown_info_ops); + info->tp_selftest_proc = + proc_create("tp_selftest", 0644, NULL, &fts_selftest_ops); + info->tp_data_dump_proc = + proc_create("tp_data_dump", 0444, NULL, &fts_datadump_ops); + info->tp_fw_version_proc = + proc_create("tp_fw_version", 0444, NULL, &fts_fw_version_ops); + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + info->touch_feature_wq = + alloc_workqueue("fts-touch-feature", + WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!info->touch_feature_wq) { + logError(1, + "%s ERROR: Cannot create touch feature work thread\n", + tag); + goto ProbeErrorExit_8; + } + INIT_WORK(&info->cmd_update_work, fts_cmd_update_work); + mutex_init(&info->cmd_update_mutex); + memset(&xiaomi_touch_interfaces, 0x00, + sizeof(struct xiaomi_touch_interface)); + xiaomi_touch_interfaces.getModeValue = fts_get_mode_value; + xiaomi_touch_interfaces.setModeValue = fts_set_cur_value; + xiaomi_touch_interfaces.resetMode = fts_reset_mode; + xiaomi_touch_interfaces.getModeAll = fts_get_mode_all; + xiaomi_touch_interfaces.p_sensor_write = fts_palm_sensor_write; + xiaomi_touch_interfaces.palm_sensor_write = fts_palm_sensor_write; + xiaomitouch_register_modedata(&xiaomi_touch_interfaces); + fts_read_touchmode_data(); + fts_init_touchmode_data(); +#endif +#ifndef FW_UPDATE_ON_PROBE + queue_delayed_work(info->fwu_workqueue, &info->fwu_work, + msecs_to_jiffies(EXP_FN_WORK_DELAY_MS)); +#endif + + logError(1, "%s Probe Finished! \n", tag); + return OK; +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP +ProbeErrorExit_8: + device_destroy(info->fts_tp_class, 0x49); + class_destroy(info->fts_tp_class); + info->fts_tp_class = NULL; +#endif +ProbeErrorExit_7: +#ifdef CONFIG_SECURE_TOUCH + fts_secure_remove(info); +#endif +#ifdef CONFIG_I2C_BY_DMA + if (info->dma_buf) + kfree(info->dma_buf); + if (info->dma_buf->rdBuf) + kfree(info->dma_buf->rdBuf); + if (info->dma_buf->wrBuf) + kfree(info->dma_buf->wrBuf); +#endif +#ifdef CONFIG_DRM + drm_unregister_client(&info->notifier); +#endif + +ProbeErrorExit_6: + input_unregister_device(info->input_dev); + +ProbeErrorExit_5_1: + if (skip_5_1 != 1) + input_free_device(info->input_dev); + +ProbeErrorExit_5: + destroy_workqueue(info->event_wq); + +ProbeErrorExit_4: + fts_enable_reg(info, false); + +ProbeErrorExit_2: + fts_get_reg(info, false); + +ProbeErrorExit_1: + kfree(info); + +ProbeErrorExit_0: + logError(1, "%s Probe Failed!\n", tag); + + return error; +} + +/** + * Clear and free all the resources associated to the driver. + * This function is called when the driver need to be removed. + */ +#ifdef I2C_INTERFACE +static int fts_remove(struct i2c_client *client) +{ +#else +static int fts_remove(struct spi_device *client) +{ +#endif + + struct fts_ts_info *info = dev_get_drvdata(&(client->dev)); + + fts_proc_remove(); + /* sysfs stuff */ + sysfs_remove_group(&client->dev.kobj, &info->attrs); + /* remove interrupt and event handlers */ + fts_interrupt_uninstall(info); + /*backlight_unregister_notifier(&info->bl_notifier);*/ +#ifdef CONFIG_DRM + drm_unregister_client(&info->notifier); +#endif + + /* unregister the device */ + input_unregister_device(info->input_dev); + + /* Remove the work thread */ + destroy_workqueue(info->event_wq); +#ifndef FW_UPDATE_ON_PROBE + destroy_workqueue(info->fwu_workqueue); +#endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + destroy_workqueue(info->touch_feature_wq); +#endif +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + if (info->board->dump_click_count && !info->current_clicknum_file) { + kfree(info->current_clicknum_file); + info->current_clicknum_file = NULL; + } + sysfs_remove_file(&info->fts_touch_dev->kobj, + &dev_attr_touch_suspend_notify.attr); + device_destroy(info->fts_tp_class, DCHIP_ID_0); + class_destroy(info->fts_tp_class); + info->fts_tp_class = NULL; +#endif + + fts_enable_reg(info, false); + fts_get_reg(info, false); + fts_info = NULL; +#ifdef CONFIG_SECURE_TOUCH + fts_secure_remove(info); +#endif + /* free all */ + kfree(info); + + return OK; +} + +/** +* Struct which contains the compatible names that need to match with the definition of the device in the device tree node +*/ +static struct of_device_id fts_of_match_table[] = { + { + .compatible = "st,fts", + }, + {}, +}; + +#ifdef I2C_INTERFACE +static const struct i2c_device_id fts_device_id[] = { { FTS_TS_DRV_NAME, 0 }, + {} }; + +static struct i2c_driver fts_i2c_driver = { + .driver = { + .name = FTS_TS_DRV_NAME, + .of_match_table = fts_of_match_table, +#ifdef CONFIG_PM + .pm = &fts_dev_pm_ops, +#endif + }, + .probe = fts_probe, + .remove = fts_remove, + .id_table = fts_device_id, +}; +#else +static struct spi_driver fts_spi_driver = { + .driver = { + .name = FTS_TS_DRV_NAME, + .of_match_table = fts_of_match_table, + .owner = THIS_MODULE, + }, + .probe = fts_probe, + .remove = fts_remove, +}; +#endif + +static int __init fts_driver_init(void) +{ +#ifdef I2C_INTERFACE + return i2c_add_driver(&fts_i2c_driver); +#else + return spi_register_driver(&fts_spi_driver); +#endif +} + +static void __exit fts_driver_exit(void) +{ +#ifdef I2C_INTERFACE + i2c_del_driver(&fts_i2c_driver); +#else + spi_unregister_driver(&fts_spi_driver); +#endif +} + +MODULE_DESCRIPTION("STMicroelectronics MultiTouch IC Driver"); +MODULE_AUTHOR("STMicroelectronics"); +MODULE_LICENSE("GPL"); + +late_initcall(fts_driver_init); +module_exit(fts_driver_exit); diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.h b/drivers/input/touchscreen/xiaomi/fts_521/fts.h new file mode 100644 index 000000000000..0e5522d2e7b8 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.h @@ -0,0 +1,397 @@ +/* + * fts.c + * + * FTS Capacitive touch screen controller (FingerTipS) + * + * Copyright (C) 2017, STMicroelectronics + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: AMG(Analog Mems Group) + * + * marco.cali@st.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THE PRESENT SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES + * OR CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED, FOR THE SOLE + * PURPOSE TO SUPPORT YOUR APPLICATION DEVELOPMENT. + * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE + * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING + * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + * THIS SOFTWARE IS SPECIFICALLY DESIGNED FOR EXCLUSIVE USE WITH ST PARTS. + */ + +/*! +* \file fts.h +* \brief Contains all the definitions and structs used generally by the driver +*/ + +#ifndef _LINUX_FTS_I2C_H_ +#define _LINUX_FTS_I2C_H_ + +#include +#include +#include +#include +#include "fts_lib/ftsSoftware.h" +#include "fts_lib/ftsHardware.h" +#include +/****************** CONFIGURATION SECTION ******************/ +/** @defgroup conf_section Driver Configuration Section +* Settings of the driver code in order to suit the HW set up and the application behavior +* @{ +*/ + +/**** CODE CONFIGURATION ****/ +#define FTS_TS_DRV_NAME "fts" /*driver name*/ +#define FTS_TS_DRV_VERSION "5.2.4" /*driver version string format*/ +#define FTS_TS_DRV_VER 0x05020400 /*driver version u32 format*/ + +#define PINCTRL_STATE_ACTIVE "pmx_ts_active" +#define PINCTRL_STATE_SUSPEND "pmx_ts_suspend" +#define PINCTRL_STATE_RELEASE "pmx_ts_release" + +#define DRIVER_TEST + +#define PRE_SAVED_METHOD + +/*#define FW_H_FILE*/ +#define FW_UPDATE_ON_PROBE +#ifdef FW_H_FILE +#define FW_SIZE_NAME myArray_size +#define FW_ARRAY_NAME myArray +#endif + +/*#define LIMITS_H_FILE*/ +#ifdef LIMITS_H_FILE +#define LIMITS_SIZE_NAME myArray2_size +#define LIMITS_ARRAY_NAME myArray2 +#endif + +/*#define USE_ONE_FILE_NODE*/ + +#ifndef FW_UPDATE_ON_PROBE +#define EXP_FN_WORK_DELAY_MS 1000 +#endif + +/**** END ****/ + +/**** FEATURES USED IN THE IC ****/ + +/*#define PHONE_KEY*/ + +#define GESTURE_MODE +#ifdef GESTURE_MODE +#define USE_GESTURE_MASK +#endif + +#define CHARGER_MODE + +#define GLOVE_MODE + +#define COVER_MODE + +#define STYLUS_MODE + +/**** END ****/ + +/**** PANEL SPECIFICATION ****/ +#define X_AXIS_MAX 1080 +#define X_AXIS_MIN 0 +#define Y_AXIS_MAX 2340 +#define Y_AXIS_MIN 0 + +#define PRESSURE_MIN 0 +#ifdef CONFIG_INPUT_PRESS_NDT +#define PRESSURE_MAX 2048 +#else +#define PRESSURE_MAX 127 +#endif + +#define DISTANCE_MIN 0 +#define DISTANCE_MAX 127 + +#define TOUCH_ID_MAX 10 + +#define AREA_MIN PRESSURE_MIN +#define AREA_MAX PRESSURE_MAX +/**** END ****/ +/**@}*/ +/*********************************************************/ + +/* + * Configuration mode + * + * bitmask which can assume the value defined as features in ftsSoftware.h or the following values + */ + +/** @defgroup mode_section IC Status Mode +* Bitmask which keeps track of the features and working mode enabled in the IC. +* The meaning of the the LSB of the bitmask must be interpreted considering that the value defined in @link feat_opt Feature Selection Option @endlink correspond to the position of the corresponding bit in the mask +* @{ +*/ +#define MODE_NOTHING 0x00000000 +#define MODE_ACTIVE(_mask, _sett) \ + do { \ + _mask |= (SCAN_MODE_ACTIVE << 24) | (_sett << 16); \ + } while (0) +#define MODE_LOW_POWER(_mask, _sett) \ + do { \ + _mask |= (SCAN_MODE_LOW_POWER << 24) | (_sett << 16); \ + } while (0) +/** @}*/ + +#define CMD_STR_LEN 32 + +#define TSP_BUF_SIZE PAGE_SIZE + +#define CONFIG_FTS_TOUCH_COUNT_DUMP + +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP +#define TOUCH_COUNT_FILE_MAXSIZE 50 +#endif + +/** + * Struct which contains information about the HW platform and set up + */ +#define FTS_LOCKDOWN_SIZE 8 +#define FTS_RESULT_INVALID 0 +#define FTS_RESULT_PASS 2 +#define FTS_RESULT_FAIL 1 + +struct fts_config_info { + u8 tp_vendor; + u8 tp_color; + u8 tp_hw_version; + const char *fts_cfg_name; + const char *fts_limit_name; +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + const char *clicknum_file_name; +#endif +}; + +struct fts_hw_platform_data { + int (*power)(bool on); + int irq_gpio; + int reset_gpio; + unsigned long irq_flags; + unsigned int x_max; + unsigned int y_max; + const char *vdd_reg_name; + const char *avdd_reg_name; + const char *default_fw_name; + size_t config_array_size; + struct fts_config_info *config_array; + int current_index; +#ifdef PHONE_KEY + size_t nbuttons; + int *key_code; +#endif +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + bool dump_click_count; +#endif + unsigned long keystates; +}; + +/* + * Forward declaration + */ +struct fts_ts_info; +extern char tag[8]; + +/* + * Dispatch event handler + */ +typedef void (*event_dispatch_handler_t)(struct fts_ts_info *info, + unsigned char *data); + +#ifdef CONFIG_SECURE_TOUCH +struct fts_secure_delay { + bool palm_pending; + int palm_value; +}; + +struct fts_secure_info { + bool secure_inited; + atomic_t st_1st_complete; + atomic_t st_enabled; + atomic_t st_pending_irqs; + struct completion st_irq_processed; + struct completion st_powerdown; + struct fts_secure_delay scr_delay; + struct mutex palm_lock; + void *fts_info; +}; +#endif + +#ifdef CONFIG_I2C_BY_DMA +struct fts_dma_buf { + struct mutex dmaBufLock; + u8 *rdBuf; + u8 *wrBuf; +}; +#endif + +/** + * FTS capacitive touch screen device information + * - dev Pointer to the structure device \n + * - client client structure \n + * - input_dev Input device structure \n + * - work Work thread \n + * - event_wq Event queue for work thread \n + * - event_dispatch_table Event dispatch table handlers \n + * - attrs SysFS attributes \n + * - mode Device operating mode (bitmask) \n + * - touch_id Bitmask for touch id (mapped to input slots) \n + * - stylus_id Bitmask for tracking the stylus touches (mapped using the touchId) \n + * - timer Timer when operating in polling mode \n + * - power Power on/off routine \n + * - board HW info retrieved from device tree \n + * - vdd_reg DVDD power regulator \n + * - avdd_reg AVDD power regulator \n + * - resume_bit Indicate if screen off/on \n + * - fwupdate_stat Store the result of a fw update triggered by the host \n + * - notifier Used for be notified from a suspend/resume event \n + * - sensor_sleep true suspend was called, false resume was called \n + * - wakelock Wake Lock struct \n + * - input_report_mutex mutex for handling the pressure of keys \n + * - series_of_switches to store the enabling status of a particular feature from the host \n + */ +struct fts_ts_info { + struct device *dev; +#ifdef I2C_INTERFACE + struct i2c_client *client; +#else + struct spi_device *client; +#endif + struct input_dev *input_dev; + + struct work_struct work; + struct work_struct suspend_work; + struct work_struct resume_work; + struct work_struct cmd_update_work; + struct work_struct sleep_work; + struct workqueue_struct *event_wq; + struct workqueue_struct *irq_wq; + struct workqueue_struct *touch_feature_wq; + +#ifndef FW_UPDATE_ON_PROBE + struct delayed_work fwu_work; + struct workqueue_struct *fwu_workqueue; +#endif + event_dispatch_handler_t *event_dispatch_table; + + struct attribute_group attrs; + + unsigned int mode; + unsigned long touch_id; + unsigned long sleep_finger; + unsigned long touch_skip; + int coor[TOUCH_ID_MAX][2]; +#ifdef STYLUS_MODE + unsigned long stylus_id; +#endif + struct fts_hw_platform_data *board; + struct regulator *vdd_reg; + struct regulator *avdd_reg; + + int resume_bit; + int fwupdate_stat; + + struct notifier_block notifier; + struct notifier_block bl_notifier; + bool sensor_sleep; + bool sensor_scan; + struct pinctrl *ts_pinctrl; + struct pinctrl_state *pinctrl_state_active; + struct pinctrl_state *pinctrl_state_suspend; + u8 lockdown_info[FTS_LOCKDOWN_SIZE]; + int result_type; + struct proc_dir_entry *tp_selftest_proc; + struct proc_dir_entry *tp_data_dump_proc; + struct proc_dir_entry *tp_fw_version_proc; + struct proc_dir_entry *tp_lockdown_info_proc; + + /* input lock */ + struct mutex input_report_mutex; + int gesture_enabled; + int glove_enabled; + int charger_enabled; + int stylus_enabled; + int cover_enabled; + unsigned int grip_enabled; + unsigned int grip_pixel; + unsigned int doze_time; + unsigned int grip_pixel_def; + unsigned int doze_time_def; +#ifdef CONFIG_TOUCHSCREEN_ST_DEBUG_FS + struct dentry *debugfs; +#endif + int dbclick_count; +#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP + struct class *fts_tp_class; + struct device *fts_touch_dev; + char *current_clicknum_file; +#endif +#ifdef CONFIG_SECURE_TOUCH + struct fts_secure_info *secure_info; +#endif +#ifdef CONFIG_I2C_BY_DMA + struct fts_dma_buf *dma_buf; +#endif + bool lockdown_is_ok; + bool irq_status; + wait_queue_head_t wait_queue; + struct completion tp_reset_completion; + atomic_t system_is_resetting; + unsigned int fod_status; + unsigned int fod_overlap; + unsigned long fod_id; + unsigned long fod_x; + unsigned long fod_y; + struct mutex fod_mutex; + struct mutex cmd_update_mutex; + bool fod_coordinate_update; + bool fod_status_set; + bool fod_pressed; + bool p_sensor_changed; + bool p_sensor_switch; + bool palm_sensor_changed; + bool palm_sensor_switch; + bool tp_pm_suspend; + struct completion pm_resume_completion; +}; + +struct fts_mode_switch { + struct fts_ts_info *info; + unsigned char mode; + struct work_struct switch_mode_work; +}; + +int fts_chip_powercycle(struct fts_ts_info *info); +extern int input_register_notifier_client(struct notifier_block *nb); +extern int input_unregister_notifier_client(struct notifier_block *nb); + +extern int fts_proc_init(void); +extern int fts_proc_remove(void); +#ifdef CONFIG_FTS_FOD_AREA_REPORT +#define CENTER_X 540 +#define CENTER_Y 2005 +#define CIRCLE_R 87 +#define FOD_LX 420 +#define FOD_LY 1885 +#define FOD_SIDE 242 +bool fts_is_infod(void); +void fts_get_pointer(int *touch_flag, int *x, int *y); +#endif +void fts_restore_regvalues(void); + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +int fts_palm_sensor_cmd(int input); +int fts_p_sensor_cmd(int input); +bool fts_touchmode_edgefilter(unsigned int touch_id, int x, int y); +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_fw.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_fw.h new file mode 100644 index 000000000000..01d095959445 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_fw.h @@ -0,0 +1,8387 @@ +/*! +* \file fts_fw.h +* \brief Contains the size and the byte array of the fw file to burn into the IC +*/ +#ifndef FTS_FW_H +#define FTS_FW_H +/*This is an auto generated header file*/ +/*--->Remember to change the name of the two variables!<---*/ +const uint32_t myArray_size = 100476; + +const uint8_t myArray[] = { + 0x55, 0xAA, 0x55, 0xAA, 0x01, 0x00, 0x00, 0x00, 0x36, 0x39, 0x00, 0x00, + 0x33, 0xA2, 0x00, 0x00, 0x33, 0xA2, 0x00, 0x00, 0xA1, 0x00, 0xA1, 0x00, + 0xA1, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE8, 0x7D, 0x01, 0x00, + 0x50, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xF3, 0xB0, 0x4F, 0xDA, 0x69, 0xDA, 0x63, 0x91, 0x79, 0x5F, 0x00, 0x00, + 0x96, 0x25, 0x9C, 0x6E, 0x86, 0xA0, 0xFF, 0xFF, 0x00, 0x04, 0x10, 0x00, + 0xB5, 0x02, 0x00, 0x00, 0x0D, 0x03, 0x00, 0x00, 0x27, 0x03, 0x00, 0x00, + 0x41, 0x03, 0x00, 0x00, 0x5B, 0x03, 0x00, 0x00, 0x75, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x85, 0x6E, 0x01, 0x00, 0x8D, 0x6E, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x8F, 0x03, 0x00, 0x00, 0x95, 0x6E, 0x01, 0x00, + 0x9D, 0x6E, 0x01, 0x00, 0xAB, 0x6E, 0x01, 0x00, 0xB9, 0x6E, 0x01, 0x00, + 0xC7, 0x6E, 0x01, 0x00, 0xD5, 0x6E, 0x01, 0x00, 0xE3, 0x6E, 0x01, 0x00, + 0xF1, 0x6E, 0x01, 0x00, 0xFF, 0x6E, 0x01, 0x00, 0x0D, 0x6F, 0x01, 0x00, + 0x9D, 0x03, 0x00, 0x00, 0x1B, 0x6F, 0x01, 0x00, 0x29, 0x6F, 0x01, 0x00, + 0x37, 0x6F, 0x01, 0x00, 0x3F, 0x6F, 0x01, 0x00, 0x47, 0x6F, 0x01, 0x00, + 0x4F, 0x6F, 0x01, 0x00, 0x5D, 0x6F, 0x01, 0x00, 0x65, 0x6F, 0x01, 0x00, + 0x6D, 0x6F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x6F, 0x01, 0x00, + 0x7D, 0x6F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x6F, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0xA2, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x02, 0xF8, 0x00, 0xF0, 0x68, 0xF8, + 0x0A, 0xA0, 0x90, 0xE8, 0x00, 0x0C, 0x82, 0x44, 0x83, 0x44, 0xAA, 0xF1, + 0x01, 0x07, 0xDA, 0x45, 0x01, 0xD1, 0x00, 0xF0, 0x5D, 0xF8, 0xAF, 0xF2, + 0x09, 0x0E, 0xBA, 0xE8, 0x0F, 0x00, 0x13, 0xF0, 0x01, 0x0F, 0x18, 0xBF, + 0xFB, 0x1A, 0x43, 0xF0, 0x01, 0x03, 0x18, 0x47, 0x1C, 0x7C, 0x01, 0x00, + 0x4C, 0x7C, 0x01, 0x00, 0x0A, 0x44, 0x4F, 0xF0, 0x00, 0x0C, 0x10, 0xF8, + 0x01, 0x3B, 0x13, 0xF0, 0x07, 0x04, 0x08, 0xBF, 0x10, 0xF8, 0x01, 0x4B, + 0x1D, 0x11, 0x08, 0xBF, 0x10, 0xF8, 0x01, 0x5B, 0x64, 0x1E, 0x05, 0xD0, + 0x10, 0xF8, 0x01, 0x6B, 0x64, 0x1E, 0x01, 0xF8, 0x01, 0x6B, 0xF9, 0xD1, + 0x13, 0xF0, 0x08, 0x0F, 0x1E, 0xBF, 0x10, 0xF8, 0x01, 0x4B, 0xAD, 0x1C, + 0x0C, 0x1B, 0x09, 0xD1, 0x6D, 0x1E, 0x58, 0xBF, 0x01, 0xF8, 0x01, 0xCB, + 0xFA, 0xD5, 0x05, 0xE0, 0x14, 0xF8, 0x01, 0x6B, 0x01, 0xF8, 0x01, 0x6B, + 0x6D, 0x1E, 0xF9, 0xD5, 0x91, 0x42, 0xD6, 0xD3, 0x70, 0x47, 0x00, 0x00, + 0x10, 0x3A, 0x24, 0xBF, 0x78, 0xC8, 0x78, 0xC1, 0xFA, 0xD8, 0x52, 0x07, + 0x24, 0xBF, 0x30, 0xC8, 0x30, 0xC1, 0x44, 0xBF, 0x04, 0x68, 0x0C, 0x60, + 0x70, 0x47, 0x00, 0x00, 0x00, 0x23, 0x00, 0x24, 0x00, 0x25, 0x00, 0x26, + 0x10, 0x3A, 0x28, 0xBF, 0x78, 0xC1, 0xFB, 0xD8, 0x52, 0x07, 0x28, 0xBF, + 0x30, 0xC1, 0x48, 0xBF, 0x0B, 0x60, 0x70, 0x47, 0x1F, 0xB5, 0x1F, 0xBD, + 0x10, 0xB5, 0x10, 0xBD, 0xDF, 0xF8, 0x0C, 0xD0, 0xFF, 0xF7, 0xF8, 0xFF, + 0x16, 0xF0, 0xE4, 0xFE, 0x17, 0xF0, 0x69, 0xF8, 0x00, 0x04, 0x10, 0x00, + 0x03, 0xB4, 0xFF, 0xF7, 0xF1, 0xFF, 0x03, 0xBC, 0x17, 0xF0, 0x68, 0xF8, + 0x0A, 0x48, 0x4F, 0xF0, 0xFF, 0x01, 0x01, 0x70, 0x4F, 0xF0, 0x00, 0x00, + 0x80, 0xF3, 0x11, 0x88, 0x4F, 0xF0, 0x00, 0x00, 0x80, 0xF3, 0x09, 0x88, + 0x05, 0x48, 0x4F, 0xF0, 0x02, 0x01, 0x01, 0x70, 0x62, 0xB6, 0x04, 0x48, + 0x4F, 0xF0, 0x80, 0x51, 0x01, 0x60, 0x70, 0x47, 0x22, 0xED, 0x00, 0xE0, + 0x00, 0x04, 0x10, 0x00, 0x04, 0xED, 0x00, 0xE0, 0x02, 0x48, 0x4F, 0xF0, + 0x80, 0x51, 0x01, 0x60, 0x70, 0x47, 0x00, 0x00, 0x04, 0xED, 0x00, 0xE0, + 0x4F, 0xF0, 0x20, 0x00, 0x80, 0xF3, 0x11, 0x88, 0xEF, 0xF3, 0x09, 0x80, + 0x98, 0xB1, 0x12, 0x48, 0x00, 0x68, 0x12, 0x49, 0x09, 0x68, 0x88, 0x42, + 0x17, 0xD0, 0xEF, 0xF3, 0x09, 0x80, 0x0E, 0x49, 0x09, 0x68, 0x20, 0xE9, + 0xF0, 0x0F, 0x88, 0x60, 0x00, 0xB5, 0x0B, 0x48, 0x00, 0x68, 0x00, 0xF0, + 0x2F, 0xF9, 0x5D, 0xF8, 0x04, 0xEB, 0x08, 0x48, 0x08, 0x49, 0x0A, 0x68, + 0x02, 0x60, 0x00, 0x68, 0x81, 0x68, 0xB1, 0xE8, 0xF0, 0x0F, 0x81, 0xF3, + 0x09, 0x88, 0x4E, 0xF0, 0x04, 0x0E, 0x4F, 0xF0, 0x00, 0x00, 0x80, 0xF3, + 0x11, 0x88, 0x70, 0x47, 0x04, 0x04, 0x10, 0x00, 0x08, 0x04, 0x10, 0x00, + 0xEF, 0xF3, 0x11, 0x80, 0x4F, 0xF0, 0x20, 0x01, 0x81, 0xF3, 0x11, 0x88, + 0x70, 0x47, 0x00, 0x00, 0x4F, 0xF0, 0x00, 0x00, 0x80, 0xF3, 0x11, 0x88, + 0x70, 0x47, 0x00, 0x00, 0x62, 0xB6, 0x70, 0x47, 0x72, 0xB6, 0x70, 0x47, + 0x40, 0x1E, 0xFD, 0xD1, 0x70, 0x47, 0x00, 0x00, 0x40, 0xBA, 0x70, 0x47, + 0xC0, 0xBA, 0x70, 0x47, 0x12, 0x48, 0x13, 0x49, 0xA1, 0xEB, 0x00, 0x01, + 0x4F, 0xF0, 0x20, 0x03, 0x91, 0xFB, 0xF3, 0xF2, 0x02, 0xFB, 0x13, 0x11, + 0x4F, 0xF0, 0xCC, 0x33, 0x4F, 0xF0, 0xCC, 0x34, 0x4F, 0xF0, 0xCC, 0x35, + 0x4F, 0xF0, 0xCC, 0x36, 0x4F, 0xF0, 0xCC, 0x37, 0x4F, 0xF0, 0xCC, 0x38, + 0x4F, 0xF0, 0xCC, 0x39, 0x4F, 0xF0, 0xCC, 0x3A, 0xA0, 0xE8, 0xF8, 0x07, + 0x01, 0x3A, 0xFB, 0xD1, 0x19, 0xB1, 0x40, 0xF8, 0x04, 0xAB, 0x04, 0x39, + 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0x00, 0x00, 0x66, 0x75, 0x6A, 0xB0, +}; + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/Makefile b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/Makefile new file mode 100644 index 000000000000..ca95cb0289ed --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the FTS touchscreen driver. +# + + +obj-$(CONFIG_TOUCHSCREEN_ST_FTS_V521) += ftsCompensation.o ftsCore.o ftsError.o ftsFrame.o ftsIO.o ftsTest.o ftsTime.o ftsTool.o ftsFlash.o ftsGesture.o + diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.c new file mode 100644 index 000000000000..a4622fc5907b --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.c @@ -0,0 +1,764 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS functions for getting Initialization Data * +* * +************************************************************************** +************************************************************************** + +*/ +/*! +* \file ftsCompensation.c +* \brief Contains all the function to work with Initialization Data +*/ + +#include "ftsCompensation.h" +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsFrame.h" +#include "ftsHardware.h" +#include "ftsIO.h" +#include "ftsSoftware.h" +#include "ftsTime.h" +#include "ftsTool.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** +* Request to the FW to load the specified Initialization Data +* @param type type of Initialization data to load @link load_opt Load Host Data Option @endlink +* @return OK if success or an error code which specify the type of error encountered +*/ +int requestCompensationData(u8 type) +{ + int ret = ERROR_OP_NOT_ALLOW; + int retry = 0; + + logError(0, "%s %s: Requesting compensation data... \n", tag, __func__, + retry + 1); + while (retry < RETRY_COMP_DATA_READ) { + ret = writeSysCmd(SYS_CMD_LOAD_DATA, &type, 1); + if (ret < OK) { + logError(1, "%s %s: failed at %d attemp! \n", tag, + __func__, retry + 1); + retry += 1; + } else { + logError( + 0, + "%s %s: Request Compensation data FINISHED! \n", + tag, __func__); + return OK; + } + } + + logError(1, "%s %s: Requesting compensation data... ERROR %08X \n", tag, + __func__, ret | ERROR_REQU_COMP_DATA); + return ret | ERROR_REQU_COMP_DATA; +} + +/** +* Read Initialization Data Header and check that the type loaded match with the one previously requested +* @param type type of Initialization data requested @link load_opt Load Host Data Option @endlink +* @param header pointer to DataHeader variable which will contain the header +* @param address pointer to a variable which will contain the updated address to the next data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readCompensationDataHeader(u8 type, DataHeader *header, u64 *address) +{ + u64 offset = ADDR_FRAMEBUFFER; + u8 data[COMP_DATA_HEADER]; + int ret; + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, offset, data, + COMP_DATA_HEADER, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, + "%s %s: error while reading data header ERROR %08X \n", + tag, __func__, ret); + return ret; + } + + logError(0, "%s Read Data Header done! \n", tag); + + if (data[0] != HEADER_SIGNATURE) { + logError( + 1, + "%s %s: The Header Signature was wrong! %02X != %02X ERROR %08X \n", + tag, __func__, data[0], HEADER_SIGNATURE, + ERROR_WRONG_DATA_SIGN); + return ERROR_WRONG_DATA_SIGN; + } + + if (data[1] != type) { + logError(1, "%s %s: Wrong type found! %02X!=%02X ERROR %08X\n", + tag, __func__, data[1], type, ERROR_DIFF_DATA_TYPE); + return ERROR_DIFF_DATA_TYPE; + } + + logError(0, "%s Type = %02X of Compensation data OK! \n", tag, type); + + header->type = type; + + *address = offset + COMP_DATA_HEADER; + + return OK; +} + +/** +* Read MS Global Initialization data from the buffer such as Cx1 +* @param address pointer to a variable which contain the address from where to read the data and will contain the updated address to the next data +* @param global pointer to MutualSenseData variable which will contain the MS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readMutualSenseGlobalData(u64 *address, MutualSenseData *global) +{ + u8 data[COMP_DATA_GLOBAL]; + int ret; + + logError(0, "%s Address for Global data= %04X \n", tag, *address); + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, *address, data, + COMP_DATA_GLOBAL, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, "%s %s: error while reading info data ERROR %08X\n", + tag, __func__, ret); + return ret; + } + logError(0, "%s Global data Read !\n", tag); + + global->header.force_node = data[0]; + global->header.sense_node = data[1]; + global->cx1 = data[2]; + + logError(0, "%s force_len = %d sense_len = %d CX1 = %d \n", tag, + global->header.force_node, global->header.sense_node, + global->cx1); + + *address += COMP_DATA_GLOBAL; + return OK; +} + +/** +* Read MS Initialization data for each node from the buffer +* @param address a variable which contain the address from where to read the data +* @param node pointer to MutualSenseData variable which will contain the MS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readMutualSenseNodeData(u64 address, MutualSenseData *node) +{ + int ret; + int size = node->header.force_node * node->header.sense_node; + + logError(0, "%s Address for Node data = %04X \n", tag, address); + + node->node_data = (i8 *)kmalloc(size * (sizeof(i8)), GFP_KERNEL); + + if (node->node_data == NULL) { + logError(1, "%s %s: can not allocate node_data... ERROR %08X", + tag, __func__, ERROR_ALLOC); + return ERROR_ALLOC; + } + + logError(0, "%s Node Data to read %d bytes \n", tag, size); + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, address, + node->node_data, size, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, + "%s %s: error while reading node data ERROR %08X \n", + tag, __func__, ret); + kfree(node->node_data); + node->node_data = NULL; + return ret; + } + node->node_data_size = size; + + logError(0, "%s Read node data OK! \n", tag); + + return size; +} + +/** +* Perform all the steps to read the necessary info for MS Initialization data from the buffer and store it in a MutualSenseData variable +* @param type type of MS Initialization data to read @link load_opt Load Host Data Option @endlink +* @param data pointer to MutualSenseData variable which will contain the MS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readMutualSenseCompensationData(u8 type, MutualSenseData *data) +{ + int ret; + u64 address; + data->node_data = NULL; + + if (!(type == LOAD_CX_MS_TOUCH || type == LOAD_CX_MS_LOW_POWER || + type == LOAD_CX_MS_KEY || type == LOAD_CX_MS_FORCE)) { + logError( + 1, + "%s %s: Choose a MS type of compensation data ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + ret = requestCompensationData(type); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_REQU_COMP_DATA); + return (ret | ERROR_REQU_COMP_DATA); + } + + ret = readCompensationDataHeader(type, &(data->header), &address); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_HEADER); + return (ret | ERROR_COMP_DATA_HEADER); + } + + ret = readMutualSenseGlobalData(&address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X \n", tag, __func__, + ERROR_COMP_DATA_GLOBAL); + return (ret | ERROR_COMP_DATA_GLOBAL); + } + + ret = readMutualSenseNodeData(address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_NODE); + return (ret | ERROR_COMP_DATA_NODE); + } + + return OK; +} + +/** +* Read SS Global Initialization data from the buffer such as Ix1/Cx1 for force and sense +* @param address pointer to a variable which contain the address from where to read the data and will contain the updated address to the next data +* @param global pointer to MutualSenseData variable which will contain the SS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readSelfSenseGlobalData(u64 *address, SelfSenseData *global) +{ + int ret; + u8 data[COMP_DATA_GLOBAL]; + + logError(0, "%s Address for Global data= %04X \n", tag, *address); + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, *address, data, + COMP_DATA_GLOBAL, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, + "%s %s: error while reading the data... ERROR %08X \n", + tag, __func__, ret); + return ret; + } + + logError(0, "%s Global data Read !\n", tag); + + global->header.force_node = data[0]; + global->header.sense_node = data[1]; + global->f_ix1 = data[2]; + global->s_ix1 = data[3]; + global->f_cx1 = (i8)data[4]; + global->s_cx1 = (i8)data[5]; + global->f_max_n = data[6]; + global->s_max_n = data[7]; + + logError( + 0, + "%s force_len = %d sense_len = %d f_ix1 = %d s_ix1 = %d f_cx1 = %d s_cx1 = %d \n", + tag, global->header.force_node, global->header.sense_node, + global->f_ix1, global->s_ix1, global->f_cx1, global->s_cx1); + logError(0, "%s max_n = %d s_max_n = %d \n", tag, global->f_max_n, + global->s_max_n); + + *address += COMP_DATA_GLOBAL; + + return OK; +} + +/** +* Read SS Initialization data for each node of force and sense channels from the buffer +* @param address a variable which contain the address from where to read the data +* @param node pointer to SelfSenseData variable which will contain the SS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readSelfSenseNodeData(u64 address, SelfSenseData *node) +{ + int size = node->header.force_node * 2 + node->header.sense_node * 2; + u8 data[size]; + int ret; + + node->ix2_fm = (u8 *)kmalloc(node->header.force_node * (sizeof(u8)), + GFP_KERNEL); + if (node->ix2_fm == NULL) { + logError( + 1, + "%s %s: can not allocate memory for ix2_fm... ERROR %08X", + tag, __func__, ERROR_ALLOC); + return ERROR_ALLOC; + } + + node->cx2_fm = (i8 *)kmalloc(node->header.force_node * (sizeof(i8)), + GFP_KERNEL); + if (node->cx2_fm == NULL) { + logError( + 1, + "%s %s: can not allocate memory for cx2_fm ... ERROR %08X", + tag, __func__, ERROR_ALLOC); + kfree(node->ix2_fm); + return ERROR_ALLOC; + } + node->ix2_sn = (u8 *)kmalloc(node->header.sense_node * (sizeof(u8)), + GFP_KERNEL); + if (node->ix2_sn == NULL) { + logError(1, + "%s %s: can not allocate memory for ix2_sn ERROR %08X", + tag, __func__, ERROR_ALLOC); + kfree(node->ix2_fm); + kfree(node->cx2_fm); + return ERROR_ALLOC; + } + node->cx2_sn = (i8 *)kmalloc(node->header.sense_node * (sizeof(i8)), + GFP_KERNEL); + if (node->cx2_sn == NULL) { + logError(1, + "%s %s: can not allocate memory for cx2_sn ERROR %08X", + tag, __func__, ERROR_ALLOC); + kfree(node->ix2_fm); + kfree(node->cx2_fm); + kfree(node->ix2_sn); + return ERROR_ALLOC; + } + + logError(0, "%s Address for Node data = %02X \n", tag, address); + + logError(0, "%s Node Data to read %d bytes \n", tag, size); + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, address, data, + size, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, "%s %s: error while reading data... ERROR %08X\n", + tag, ret); + kfree(node->ix2_fm); + kfree(node->cx2_fm); + kfree(node->ix2_sn); + kfree(node->cx2_sn); + return ret; + } + + logError(0, "%s Read node data ok! \n", tag); + + memcpy(node->ix2_fm, data, node->header.force_node); + memcpy(node->ix2_sn, &data[node->header.force_node], + node->header.sense_node); + memcpy(node->cx2_fm, + &data[node->header.force_node + node->header.sense_node], + node->header.force_node); + memcpy(node->cx2_sn, + &data[node->header.force_node * 2 + node->header.sense_node], + node->header.sense_node); + + return OK; +} + +/** +* Perform all the steps to read the necessary info for SS Initialization data from the buffer and store it in a SelfSenseData variable +* @param type type of SS Initialization data to read @link load_opt Load Host Data Option @endlink +* @param data pointer to SelfSenseData variable which will contain the SS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readSelfSenseCompensationData(u8 type, SelfSenseData *data) +{ + int ret; + u64 address; + + data->ix2_fm = NULL; + data->cx2_fm = NULL; + data->ix2_sn = NULL; + data->cx2_sn = NULL; + + if (!(type == LOAD_CX_SS_TOUCH || type == LOAD_CX_SS_TOUCH_IDLE || + type == LOAD_CX_SS_KEY || type == LOAD_CX_SS_FORCE)) { + logError( + 1, + "%s %s: Choose a SS type of compensation data ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + ret = requestCompensationData(type); + if (ret < 0) { + logError(1, + "%s %s: error while requesting data... ERROR %08X\n", + tag, __func__, ERROR_REQU_COMP_DATA); + return (ret | ERROR_REQU_COMP_DATA); + } + + ret = readCompensationDataHeader(type, &(data->header), &address); + if (ret < 0) { + logError( + 1, + "%s %s: error while reading data header... ERROR %08X\n", + tag, __func__, ERROR_COMP_DATA_HEADER); + return (ret | ERROR_COMP_DATA_HEADER); + } + + ret = readSelfSenseGlobalData(&address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_GLOBAL); + return (ret | ERROR_COMP_DATA_GLOBAL); + } + + ret = readSelfSenseNodeData(address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_NODE); + return (ret | ERROR_COMP_DATA_NODE); + } + + return OK; +} + +/** +* Read TOT MS Global Initialization data from the buffer such as number of force and sense channels +* @param address pointer to a variable which contain the address from where to read the data and will contain the updated address to the next data +* @param global pointer to a variable which will contain the TOT MS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readTotMutualSenseGlobalData(u64 *address, TotMutualSenseData *global) +{ + int ret; + u8 data[COMP_DATA_GLOBAL]; + + logError(0, "%s Address for Global data= %04X \n", tag, *address); + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, *address, data, + COMP_DATA_GLOBAL, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, "%s %s: error while reading info data ERROR %08X\n", + tag, __func__, ret); + return ret; + } + logError(0, "%s Global data Read !\n", tag); + + global->header.force_node = data[0]; + global->header.sense_node = data[1]; + + logError(0, "%s force_len = %d sense_len = %d \n", tag, + global->header.force_node, global->header.sense_node); + + *address += COMP_DATA_GLOBAL; + return OK; +} + +/** +* Read TOT MS Initialization data for each node from the buffer +* @param address a variable which contain the address from where to read the data +* @param node pointer to MutualSenseData variable which will contain the TOT MS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readTotMutualSenseNodeData(u64 address, TotMutualSenseData *node) +{ + int ret, i; + int size = node->header.force_node * node->header.sense_node; + int toRead = size * sizeof(u16); + u8 data[toRead]; + + logError(0, "%s Address for Node data = %04X \n", tag, address); + + node->node_data = (short *)kmalloc(size * (sizeof(short)), GFP_KERNEL); + + if (node->node_data == NULL) { + logError(1, "%s %s: can not allocate node_data... ERROR %08X", + tag, __func__, ERROR_ALLOC); + return ERROR_ALLOC; + } + + logError(0, "%s Node Data to read %d bytes \n", tag, size); + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, address, data, + toRead, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, + "%s %s: error while reading node data ERROR %08X \n", + tag, __func__, ret); + kfree(node->node_data); + node->node_data = NULL; + return ret; + } + node->node_data_size = size; + + for (i = 0; i < size; i++) { + node->node_data[i] = ((short)data[i * 2 + 1]) << 8 | + data[i * 2]; + } + + logError(0, "%s Read node data OK! \n", tag); + + return size; +} + +/** +* Perform all the steps to read the necessary info for TOT MS Initialization data from the buffer and store it in a TotMutualSenseData variable +* @param type type of TOT MS Initialization data to read @link load_opt Load Host Data Option @endlink +* @param data pointer to a variable which will contain the TOT MS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readTotMutualSenseCompensationData(u8 type, TotMutualSenseData *data) +{ + int ret; + u64 address; + data->node_data = NULL; + + if (!(type == LOAD_PANEL_CX_TOT_MS_TOUCH || + type == LOAD_PANEL_CX_TOT_MS_LOW_POWER || + type == LOAD_PANEL_CX_TOT_MS_KEY || + type == LOAD_PANEL_CX_TOT_MS_FORCE)) { + logError( + 1, + "%s %s: Choose a TOT MS type of compensation data ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + ret = requestCompensationData(type); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_REQU_COMP_DATA); + return (ret | ERROR_REQU_COMP_DATA); + } + + ret = readCompensationDataHeader(type, &(data->header), &address); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_HEADER); + return (ret | ERROR_COMP_DATA_HEADER); + } + + ret = readTotMutualSenseGlobalData(&address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X \n", tag, __func__, + ERROR_COMP_DATA_GLOBAL); + return (ret | ERROR_COMP_DATA_GLOBAL); + } + + ret = readTotMutualSenseNodeData(address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_NODE); + return (ret | ERROR_COMP_DATA_NODE); + } + + return OK; +} + +/** +* Read TOT SS Global Initialization data from the buffer such as number of force and sense channels +* @param address pointer to a variable which contain the address from where to read the data and will contain the updated address to the next data +* @param global pointer to a variable which will contain the TOT SS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readTotSelfSenseGlobalData(u64 *address, TotSelfSenseData *global) +{ + int ret; + u8 data[COMP_DATA_GLOBAL]; + + logError(0, "%s Address for Global data= %04X \n", tag, *address); + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, *address, data, + COMP_DATA_GLOBAL, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, + "%s %s: error while reading the data... ERROR %08X \n", + tag, __func__, ret); + return ret; + } + + logError(0, "%s Global data Read !\n", tag); + + global->header.force_node = data[0]; + global->header.sense_node = data[1]; + + logError(0, "%s force_len = %d sense_len = %d \n", tag, + global->header.force_node, global->header.sense_node); + + *address += COMP_DATA_GLOBAL; + + return OK; +} + +/** +* Read TOT SS Global Initialization data from the buffer such as number of force and sense channels +* @param address pointer to a variable which contain the address from where to read the data and will contain the updated address to the next data +* @param node pointer to a variable which will contain the TOT SS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readTotSelfSenseNodeData(u64 address, TotSelfSenseData *node) +{ + int size = node->header.force_node * 2 + node->header.sense_node * 2; + int toRead = size * 2; + u8 data[toRead]; + int ret, i, j = 0; + + node->ix_fm = (u16 *)kmalloc(node->header.force_node * (sizeof(u16)), + GFP_KERNEL); + if (node->ix_fm == NULL) { + logError( + 1, + "%s %s: can not allocate memory for ix2_fm... ERROR %08X", + tag, __func__, ERROR_ALLOC); + return ERROR_ALLOC; + } + + node->cx_fm = (short *)kmalloc( + node->header.force_node * (sizeof(short)), GFP_KERNEL); + if (node->cx_fm == NULL) { + logError( + 1, + "%s %s: can not allocate memory for cx2_fm ... ERROR %08X", + tag, __func__, ERROR_ALLOC); + kfree(node->ix_fm); + return ERROR_ALLOC; + } + node->ix_sn = (u16 *)kmalloc(node->header.sense_node * (sizeof(u16)), + GFP_KERNEL); + if (node->ix_sn == NULL) { + logError(1, + "%s %s: can not allocate memory for ix2_sn ERROR %08X", + tag, __func__, ERROR_ALLOC); + kfree(node->ix_fm); + kfree(node->cx_fm); + return ERROR_ALLOC; + } + node->cx_sn = (short *)kmalloc( + node->header.sense_node * (sizeof(short)), GFP_KERNEL); + if (node->cx_sn == NULL) { + logError(1, + "%s %s: can not allocate memory for cx2_sn ERROR %08X", + tag, __func__, ERROR_ALLOC); + kfree(node->ix_fm); + kfree(node->cx_fm); + kfree(node->ix_sn); + return ERROR_ALLOC; + } + + logError(0, "%s Address for Node data = %02X \n", tag, address); + + logError(0, "%s Node Data to read %d bytes \n", tag, size); + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, address, data, + toRead, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, "%s %s: error while reading data... ERROR %08X\n", + tag, ret); + kfree(node->ix_fm); + kfree(node->cx_fm); + kfree(node->ix_sn); + kfree(node->cx_sn); + return ret; + } + + logError(0, "%s Read node data ok! \n", tag); + + j = 0; + for (i = 0; i < node->header.force_node; i++) { + node->ix_fm[i] = ((u16)data[j + 1]) << 8 | data[j]; + j += 2; + } + + for (i = 0; i < node->header.sense_node; i++) { + node->ix_sn[i] = ((u16)data[j + 1]) << 8 | data[j]; + j += 2; + } + + for (i = 0; i < node->header.force_node; i++) { + node->cx_fm[i] = ((short)data[j + 1]) << 8 | data[j]; + j += 2; + } + + for (i = 0; i < node->header.sense_node; i++) { + node->cx_sn[i] = ((short)data[j + 1]) << 8 | data[j]; + j += 2; + } + + if (j != toRead) { + logError(1, "%s %s: parsed a wrong number of bytes %d!=%d \n", + tag, __func__, j, toRead); + } + + return OK; +} + +/** +* Perform all the steps to read the necessary info for TOT SS Initialization data from the buffer and store it in a TotSelfSenseData variable +* @param type type of TOT MS Initialization data to read @link load_opt Load Host Data Option @endlink +* @param data pointer to a variable which will contain the TOT MS initialization data +* @return OK if success or an error code which specify the type of error encountered +*/ +int readTotSelfSenseCompensationData(u8 type, TotSelfSenseData *data) +{ + int ret; + u64 address; + + data->ix_fm = NULL; + data->cx_fm = NULL; + data->ix_sn = NULL; + data->cx_sn = NULL; + + if (!(type == LOAD_PANEL_CX_TOT_SS_TOUCH || + type == LOAD_PANEL_CX_TOT_SS_TOUCH_IDLE || + type == LOAD_PANEL_CX_TOT_SS_KEY || + type == LOAD_PANEL_CX_TOT_SS_FORCE || + type == STAPI_HOST_DATA_ID_PANEL_CX_SS_HVR)) { + logError( + 1, + "%s %s: Choose a TOT SS type of compensation data ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + ret = requestCompensationData(type); + if (ret < 0) { + logError(1, + "%s %s: error while requesting data... ERROR %08X\n", + tag, __func__, ERROR_REQU_COMP_DATA); + return (ret | ERROR_REQU_COMP_DATA); + } + + ret = readCompensationDataHeader(type, &(data->header), &address); + if (ret < 0) { + logError( + 1, + "%s %s: error while reading data header... ERROR %08X\n", + tag, __func__, ERROR_COMP_DATA_HEADER); + return (ret | ERROR_COMP_DATA_HEADER); + } + + ret = readTotSelfSenseGlobalData(&address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_GLOBAL); + return (ret | ERROR_COMP_DATA_GLOBAL); + } + + ret = readTotSelfSenseNodeData(address, data); + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_COMP_DATA_NODE); + return (ret | ERROR_COMP_DATA_NODE); + } + + return OK; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.h new file mode 100644 index 000000000000..83276fbde63a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCompensation.h @@ -0,0 +1,110 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS functions for getting Initialization Data * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsCompensation.h +* \brief Contains all the definitions and structs to work with Initialization Data +*/ + +#ifndef FTS_COMPENSATION_H +#define FTS_COMPENSATION_H + +#include "ftsCore.h" +#include "ftsSoftware.h" + +#define RETRY_COMP_DATA_READ 2 + +/*Bytes dimension of Compensation Data Format*/ + +#define COMP_DATA_HEADER DATA_HEADER +#define COMP_DATA_GLOBAL (16 - COMP_DATA_HEADER) + +#define HEADER_SIGNATURE 0xA5 + +/** +* Struct which contains the general info about Frames and Initialization Data +*/ +typedef struct { + int force_node; /*Number of Force Channels in the frame/Initialization data*/ + int sense_node; /*Number of Sense Channels in the frame/Initialization data*/ + int type; /*Type of frame/Initialization data*/ +} DataHeader; + +/** +* Struct which contains the MS Initialization data +*/ +typedef struct { + DataHeader header; /*Header*/ + i8 cx1; /*Cx1 value (can be negative))*/ + i8 *node_data; /*Pointer to an array of bytes which contains the CX2 data (can be negative)*/ + int node_data_size; /*size of the data*/ +} MutualSenseData; + +/** +* Struct which contains the SS Initialization data +*/ +typedef struct { + DataHeader header; /*Header*/ + u8 f_ix1; /*IX1 Force*/ + u8 s_ix1; /*IX1 Sense*/ + i8 f_cx1; /*CX1 Force (can be negative)*/ + i8 s_cx1; /*< CX1 Sense (can be negative)*/ + u8 f_max_n; /*Force MaxN*/ + u8 s_max_n; /*Sense MaxN*/ + + u8 *ix2_fm; /*pointer to an array of bytes which contains Force Ix2 data node*/ + u8 *ix2_sn; /*pointer to an array of bytes which contains Sense Ix2 data node*/ + i8 *cx2_fm; /*pointer to an array of bytes which contains Force Cx2 data node (can be negative)*/ + i8 *cx2_sn; /*pointer to an array of bytes which contains Sense Cx2 data node (can be negative))*/ + +} SelfSenseData; + +/** +* Struct which contains the TOT MS Initialization data +*/ +typedef struct { + DataHeader header; /*Header*/ + short *node_data; /*pointer to an array of ushort which contains TOT MS Initialization data*/ + int node_data_size; /*size of data*/ +} TotMutualSenseData; + +/** +* Struct which contains the TOT SS Initialization data +*/ +typedef struct { + DataHeader header; /*Header*/ + + u16 *ix_fm; /*pointer to an array of ushort which contains TOT SS IX Force data*/ + u16 *ix_sn; /*pointer to an array of ushort which contains TOT SS IX Sense data*/ + short *cx_fm; /*pointer to an array of ushort which contains TOT SS CX Force data (can be negative)*/ + short *cx_sn; /*pointer to an array of ushort which contains TOT SS CX Sense data (can be negative)*/ + +} TotSelfSenseData; + +int requestCompensationData(u8 type); +int readCompensationDataHeader(u8 type, DataHeader *header, u64 *address); +int readMutualSenseGlobalData(u64 *address, MutualSenseData *global); +int readMutualSenseNodeData(u64 address, MutualSenseData *node); +int readMutualSenseCompensationData(u8 type, MutualSenseData *data); +int readSelfSenseGlobalData(u64 *address, SelfSenseData *global); +int readSelfSenseNodeData(u64 address, SelfSenseData *node); +int readSelfSenseCompensationData(u8 type, SelfSenseData *data); +int readToTMutualSenseGlobalData(u64 *address, TotMutualSenseData *global); +int readToTMutualSenseNodeData(u64 address, TotMutualSenseData *node); +int readTotMutualSenseCompensationData(u8 type, TotMutualSenseData *data); +int readTotSelfSenseGlobalData(u64 *address, TotSelfSenseData *global); +int readTotSelfSenseNodeData(u64 address, TotSelfSenseData *node); +int readTotSelfSenseCompensationData(u8 type, TotSelfSenseData *data); +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.c new file mode 100644 index 000000000000..c035aec07dc3 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.c @@ -0,0 +1,1377 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS Core functions * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsCore.c +* \brief Contains the implementation of the Core functions +*/ + +#include +#include +#include +#include +#include +#include "ftsCompensation.h" +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsIO.h" +#include "ftsTest.h" +#include "ftsTime.h" +#include "ftsTool.h" + +extern struct fts_ts_info *fts_info; +/** @addtogroup system_info +* @{ +*/ +SysInfo systemInfo; /*Global System Info variable, accessible in all the driver*/ +/** @}*/ + +static int reset_gpio = + GPIO_NOT_DEFINED; /*gpio number of the rest pin, the value is GPIO_NOT_DEFINED if the reset pin is not connected*/ +static int + system_reseted_up; /*flag checked during resume to understand if there was a system reset and restore the proper state*/ +static int + system_reseted_down; /*flag checked during suspend to understand if there was a system reset and restore the proper state*/ +static int + disable_irq_count; /*count the number of call to disable_irq, start with 1 because at the boot IRQ are already disabled*/ +spinlock_t fts_int; /*spinlock to controll the access to the disable_irq_counter*/ + +/** +* Initialize core variables of the library. Must be called during the probe before any other lib function +* @param info pointer to fts_ts_info which contains info about the device and its hw setup +* @return OK if success or an error code which specify the type of error encountered +*/ +int initCore(struct fts_ts_info *info) +{ + int ret = OK; + logError(0, "%s %s: Initialization of the Core... \n", tag, __func__); + ret |= openChannel(info->client); + ret |= resetErrorList(); + ret |= initTestToDo(); + setResetGpio(info->board->reset_gpio); + if (ret < OK) { + logError(0, "%s %s: Initialization Core ERROR %08X! \n", tag, + __func__, ret); + } else { + logError(0, "%s %s: Initialization Finished! \n", tag, + __func__); + } + return ret; +} + +/** +* Set the reset_gpio variable with the actual gpio number of the board link to the reset pin +* @param gpio gpio number link to the reset pin of the IC +*/ +void setResetGpio(int gpio) +{ + reset_gpio = gpio; + logError(0, "%s setResetGpio: reset_gpio = %d\n", tag, reset_gpio); +} + +/** +* Perform a system reset of the IC. +* If the reset pin is associated to a gpio, the function execute an hw reset (toggling of reset pin) otherwise send an hw command to the IC +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_system_reset(void) +{ + u8 readData[FIFO_EVENT_SIZE]; + int event_to_search; + int res = -1; + int i; + u8 data[1] = { SYSTEM_RESET_VALUE }; + event_to_search = (int)EVT_ID_CONTROLLER_READY; + + logError(1, "%s System resetting...\n", tag); + if (fts_info) { + reinit_completion(&fts_info->tp_reset_completion); + atomic_set(&fts_info->system_is_resetting, 1); + } + for (i = 0; i < RETRY_SYSTEM_RESET && res < 0; i++) { + resetErrorList(); + fts_disableInterruptNoSync(); + + if (reset_gpio == GPIO_NOT_DEFINED) { + res = fts_writeU8UX(FTS_CMD_HW_REG_W, ADDR_SIZE_HW_REG, + ADDR_SYSTEM_RESET, data, + ARRAY_SIZE(data)); + } else { + gpio_set_value(reset_gpio, 0); + mdelay(10); + gpio_set_value(reset_gpio, 1); + res = OK; + } + if (res < OK) { + logError(1, "%s fts_system_reset: ERROR %08X\n", tag, + ERROR_BUS_W); + } else { + res = pollForEvent(&event_to_search, 1, readData, + GENERAL_TIMEOUT); + if (res < OK) { + logError(1, "%s fts_system_reset: ERROR %08X\n", + tag, res); + } + } + } + if (fts_info) { + complete(&fts_info->tp_reset_completion); + atomic_set(&fts_info->system_is_resetting, 0); + } + if (res < OK) { + logError( + 1, + "%s fts_system_reset...failed after 3 attempts: ERROR %08X\n", + tag, (res | ERROR_SYSTEM_RESET_FAIL)); + return (res | ERROR_SYSTEM_RESET_FAIL); + } else { + logError(1, "%s System reset DONE!\n", tag); + system_reseted_down = 1; + system_reseted_up = 1; + return OK; + } +} + +/** +* Return the value of system_resetted_down. +* @return the flag value: 0 if not set, 1 if set +*/ +int isSystemResettedDown(void) +{ + return system_reseted_down; +} + +/** +* Return the value of system_resetted_up. +* @return the flag value: 0 if not set, 1 if set +*/ +int isSystemResettedUp(void) +{ + return system_reseted_up; +} + +/** +* Set the value of system_reseted_down flag +* @param val value to write in the flag +*/ +void setSystemResetedDown(int val) +{ + system_reseted_down = val; +} + +/** +* Set the value of system_reseted_up flag +* @param val value to write in the flag +*/ +void setSystemResetedUp(int val) +{ + system_reseted_up = val; +} + +/** @addtogroup events_group + * @{ + */ + +/** +* Poll the FIFO looking for a specified event within a timeout. Support a retry mechanism. +* @param event_to_search pointer to an array of int where each element correspond to a byte of the event to find. If the element of the array has value -1, the byte of the event, in the same position of the element is ignored. +* @param event_bytes size of event_to_search +* @param readData pointer to an array of byte which will contain the event found +* @param time_to_wait time to wait before going in timeout +* @return OK if success or an error code which specify the type of error encountered +*/ +int pollForEvent(int *event_to_search, int event_bytes, u8 *readData, + int time_to_wait) +{ + int i, find, retry, count_err; + int time_to_count; + int err_handling = OK; + StopWatch clock; + + u8 cmd[1] = { FIFO_CMD_READONE }; + char temp[128] = { 0 }; + + find = 0; + retry = 0; + count_err = 0; + time_to_count = time_to_wait / TIMEOUT_RESOLUTION; + + startStopWatch(&clock); + while (find != 1 && retry < time_to_count && + fts_writeReadU8UX(cmd[0], 0, 0, readData, FIFO_EVENT_SIZE, + DUMMY_FIFO) >= OK) { + if (readData[0] == EVT_ID_ERROR) { + logError(1, "%s %s\n", tag, + printHex("ERROR EVENT = ", readData, + FIFO_EVENT_SIZE, temp)); + memset(temp, 0, 128); + count_err++; + err_handling = errorHandler(readData, FIFO_EVENT_SIZE); + if ((err_handling & 0xF0FF0000) == + ERROR_HANDLER_STOP_PROC) { + logError( + 0, + "%s pollForEvent: forced to be stopped! ERROR %08X\n", + tag, err_handling); + return err_handling; + } + } else { + if (readData[0] != EVT_ID_NOEVENT) { + logError(0, "%s %s\n", tag, + printHex("READ EVENT = ", readData, + FIFO_EVENT_SIZE, temp)); + memset(temp, 0, 128); + } + if (readData[0] == EVT_ID_CONTROLLER_READY && + event_to_search[0] != EVT_ID_CONTROLLER_READY) { + logError( + 0, + "%s pollForEvent: Unmanned Controller Ready Event! Setting reset flags...\n", + tag); + setSystemResetedUp(1); + setSystemResetedDown(1); + } + } + + find = 1; + + for (i = 0; i < event_bytes; i++) { + if (event_to_search[i] != -1 && + (int)readData[i] != event_to_search[i]) { + find = 0; + break; + } + } + + retry++; + mdelay(TIMEOUT_RESOLUTION); + } + stopStopWatch(&clock); + if ((retry >= time_to_count) && find != 1) { + logError(1, "%s pollForEvent: ERROR %02X \n", tag, + ERROR_TIMEOUT); + return ERROR_TIMEOUT; + } else if (find == 1) { + logError(0, "%s %s\n", tag, + printHex("FOUND EVENT = ", readData, FIFO_EVENT_SIZE, + temp)); + memset(temp, 0, 128); + logError( + 0, + "%s Event found in %d ms (%d iterations)! Number of errors found = %d \n", + tag, elapsedMillisecond(&clock), retry, count_err); + return count_err; + } else { + logError(1, "%s pollForEvent: ERROR %08X \n", tag, ERROR_BUS_R); + return ERROR_BUS_R; + } +} + +/** @}*/ + +/** +* Check that the FW sent the echo even after a command was sent +* @param cmd pointer to an array of byte which contain the command previously sent +* @param size size of cmd +* @return OK if success or an error code which specify the type of error encountered +*/ +int checkEcho(u8 *cmd, int size) +{ + int ret, i; + int event_to_search[FIFO_EVENT_SIZE]; + u8 readData[FIFO_EVENT_SIZE]; + + if (size < 1) { + logError(1, "%s checkEcho: Error Size = %d not valid! \n", tag, + size, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } else { + if ((size + 3) > FIFO_EVENT_SIZE) + size = FIFO_EVENT_SIZE - 3; + + event_to_search[0] = EVT_ID_STATUS_UPDATE; + event_to_search[1] = EVT_TYPE_STATUS_ECHO; + for (i = 2; i < size + 2; i++) { + event_to_search[i] = cmd[i - 2]; + } + ret = pollForEvent(event_to_search, size + 2, readData, + TIMEOUT_ECHO); + if (ret < OK) { + logError( + 1, + "%s checkEcho: Echo Event not found! ERROR %08X\n", + tag, ret); + return (ret | ERROR_CHECK_ECHO_FAIL); + } else if (ret > OK) { + logError( + 1, + "%s checkEcho: Echo Event found but with some error events before! num_error = %d \n", + tag, ret); + return ERROR_CHECK_ECHO_FAIL; + } + + logError(0, "%s ECHO OK!\n", tag); + return ret; + } +} + +/** @addtogroup scan_mode +* @{ +*/ +/** +* Set a scan mode in the IC +* @param mode scan mode to set; possible values @link scan_opt Scan Mode Option @endlink +* @param settings option for the selected scan mode (for example @link active_bitmask Active Mode Bitmask @endlink) +* @return OK if success or an error code which specify the type of error encountered +*/ +int setScanMode(u8 mode, u8 settings) +{ + u8 cmd[3] = { FTS_CMD_SCAN_MODE, mode, settings }; + int ret, size = 3; + + logError(0, "%s %s: Setting scan mode: mode = %02X settings = %02X !\n", + tag, __func__, mode, settings); + if (mode == SCAN_MODE_LOW_POWER) + size = 2; + ret = fts_write_dma_safe(cmd, size); + if (ret < OK) { + logError(1, "%s %s: write failed...ERROR %08X !\n", tag, + __func__, ret); + return ret | ERROR_SET_SCAN_MODE_FAIL; + } + logError(0, "%s %s: Setting scan mode OK!\n", tag, __func__); + return OK; +} + +/** @}*/ + +/** @addtogroup feat_sel +* @{ +*/ +/** +* Set a feature and its option in the IC +* @param feat feature to set; possible values @link feat_opt Feature Selection Option @endlink +* @param settings pointer to an array of byte which store the options for the selected feature (for example the gesture mask to activate @link gesture_opt Gesture IDs @endlink) +* @param size in bytes of settings +* @return OK if success or an error code which specify the type of error encountered +*/ +int setFeatures(u8 feat, u8 *settings, int size) +{ + u8 cmd[2 + size]; + int i = 0; + int ret; + logError(0, "%s %s: Setting feature: feat = %02X !\n", tag, __func__, + feat); + cmd[0] = FTS_CMD_FEATURE; + cmd[1] = feat; + logError(0, "%s %s: Settings = ", tag, __func__); + for (i = 0; i < size; i++) { + cmd[2 + i] = settings[i]; + logError(0, "%02X ", settings[i]); + } + logError(0, "\n"); + ret = fts_write_dma_safe(cmd, 2 + size); + if (ret < OK) { + logError(1, "%s %s: write failed...ERROR %08X !\n", tag, + __func__, ret); + return ret | ERROR_SET_FEATURE_FAIL; + } + logError(0, "%s %s: Setting feature OK!\n", tag, __func__); + return OK; +} + +/** @}*/ + +/** @addtogroup sys_cmd +* @{ +*/ +/** +* Write a system command to the IC +* @param sys_cmd System Command to execute; possible values @link sys_opt System Command Option @endlink +* @param sett settings option for the selected system command (@link sys_special_opt Special Command Option @endlink, @link ito_opt ITO Test Option @endlink, @link load_opt Load Host Data Option @endlink) +* @param size in bytes of settings +* @return OK if success or an error code which specify the type of error encountered +*/ +int writeSysCmd(u8 sys_cmd, u8 *sett, int size) +{ + u8 *cmd = NULL; + int ret; + + cmd = (u8 *)kzalloc(sizeof(u8) * size + 2, GFP_KERNEL); + if (!cmd) { + ret = ERROR_ALLOC; + goto end; + } + + cmd[0] = FTS_CMD_SYSTEM; + cmd[1] = sys_cmd; + + logError(0, "%s %s: Command = %02X %02X ", tag, __func__, cmd[0], + cmd[1]); + for (ret = 0; ret < size; ret++) { + cmd[2 + ret] = sett[ret]; + logError(0, "%02X ", cmd[2 + ret]); + } + logError(0, "\n%s %s: Writing Sys command...\n", tag, __func__); + if (sys_cmd != SYS_CMD_LOAD_DATA) { + ret = fts_writeFwCmd(cmd, 2 + size); + } else { + if (size >= 1) { + ret = requestSyncFrame(sett[0]); + } else { + logError(1, "%s %s: No setting argument! ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + ret = ERROR_OP_NOT_ALLOW; + goto end; + } + } + if (ret < OK) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, ret); + } else + logError(0, "%s %s: FINISHED! \n", tag, __func__); + +end: + if (cmd) + kfree(cmd); + return ret; +} + +/** @}*/ + +/** @addtogroup system_info +* @{ +*/ +/** +* Initialize the System Info Struct with default values according to the error found during the reading +* @param i2cError 1 if there was an I2C error while reading the System Info data from memory, other value if another error occurred +* @return OK if success or an error code which specify the type of error encountered +*/ +int defaultSysInfo(int i2cError) +{ + int i; + logError(0, "%s Setting default System Info... \n", tag); + + if (i2cError == 1) { + systemInfo.u16_fwVer = 0xFFFF; + systemInfo.u16_cfgProgectId = 0xFFFF; + for (i = 0; i < RELEASE_INFO_SIZE; i++) { + systemInfo.u8_releaseInfo[i] = 0xFF; + } + systemInfo.u16_cxVer = 0xFFFF; + } else { + systemInfo.u16_fwVer = 0x0000; + systemInfo.u16_cfgProgectId = 0x0000; + for (i = 0; i < RELEASE_INFO_SIZE; i++) { + systemInfo.u8_releaseInfo[i] = 0x00; + } + systemInfo.u16_cxVer = 0x0000; + } + + systemInfo.u8_scrRxLen = 0; + systemInfo.u8_scrTxLen = 0; + + logError(0, "%s default System Info DONE! \n", tag); + return OK; +} + +/** +* Read the System Info data from memory. System Info is loaded automatically after every system reset. +* @param request if 1, will be asked to the FW to reload the data, otherwise attempt to read it directly from memory +* @return OK if success or an error code which specify the type of error encountered +*/ +int readSysInfo(int request) +{ + int ret, i, index = 0; + u8 sett = LOAD_SYS_INFO; + u8 data[SYS_INFO_SIZE] = { 0 }; + char temp[256] = { 0 }; + + if (request == 1) { + logError(0, "%s %s: Requesting System Info...\n", tag, + __func__); + + ret = writeSysCmd(SYS_CMD_LOAD_DATA, &sett, 1); + if (ret < OK) { + logError( + 1, + "%s %s: error while writing the sys cmd ERROR %08X\n", + tag, __func__, ret); + goto FAIL; + } + } + + logError(0, "%s %s: Reading System Info...\n", tag, __func__); + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, + ADDR_FRAMEBUFFER, data, SYS_INFO_SIZE, + DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading the system data ERROR %08X\n", + tag, __func__, ret); + goto FAIL; + } + + logError(0, "%s %s: Parsing System Info...\n", tag, __func__); + + if (data[0] != HEADER_SIGNATURE) { + logError( + 1, + "%s %s: The Header Signature is wrong! sign: %02X != %02X ERROR %08X\n", + tag, __func__, data[0], HEADER_SIGNATURE, + ERROR_WRONG_DATA_SIGN); + ret = ERROR_WRONG_DATA_SIGN; + goto FAIL; + } + + if (data[1] != LOAD_SYS_INFO) { + logError( + 1, + "%s %s: The Data ID is wrong! ids: %02X != %02X ERROR %08X \n", + tag, __func__, data[3], LOAD_SYS_INFO, + ERROR_DIFF_DATA_TYPE); + ret = ERROR_DIFF_DATA_TYPE; + goto FAIL; + } + + index += 4; + u8ToU16(&data[index], &systemInfo.u16_apiVer_rev); + index += 2; + systemInfo.u8_apiVer_minor = data[index++]; + systemInfo.u8_apiVer_major = data[index++]; + u8ToU16(&data[index], &systemInfo.u16_chip0Ver); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_chip0Id); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_chip1Ver); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_chip1Id); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_fwVer); + index += 2; + logError(1, "%s FW VER = %04X \n", tag, systemInfo.u16_fwVer); + + u8ToU16(&data[index], &systemInfo.u16_svnRev); + index += 2; + logError(1, "%s SVN REV = %04X \n", tag, systemInfo.u16_svnRev); + u8ToU16(&data[index], &systemInfo.u16_cfgVer); + index += 2; + logError(1, "%s CONFIG VER = %04X \n", tag, systemInfo.u16_cfgVer); + u8ToU16(&data[index], &systemInfo.u16_cfgProgectId); + index += 2; + logError(1, "%s CONFIG PROJECT ID = %04X \n", tag, + systemInfo.u16_cfgProgectId); + u8ToU16(&data[index], &systemInfo.u16_cxVer); + index += 2; + logError(1, "%s CX VER = %04X \n", tag, systemInfo.u16_cxVer); + u8ToU16(&data[index], &systemInfo.u16_cxProjectId); + index += 2; + logError(1, "%s CX PROJECT ID = %04X \n", tag, + systemInfo.u16_cxProjectId); + systemInfo.u8_cfgAfeVer = data[index++]; + systemInfo.u8_cxAfeVer = data[index++]; + systemInfo.u8_panelCfgAfeVer = data[index++]; + logError(1, "%s AFE VER: CFG = %02X - CX = %02X - PANEL = %02X \n", tag, + systemInfo.u8_cfgAfeVer, systemInfo.u8_cxAfeVer, + systemInfo.u8_panelCfgAfeVer); + systemInfo.u8_protocol = data[index++]; + logError(0, "%s Protocol = %02X \n", tag, systemInfo.u8_protocol); + + for (i = 0; i < DIE_INFO_SIZE; i++) { + systemInfo.u8_dieInfo[i] = data[index++]; + } + logError(0, "%s %s \n", tag, + printHex("Die Info = ", systemInfo.u8_dieInfo, DIE_INFO_SIZE, + temp)); + memset(temp, 0, 256); + + for (i = 0; i < RELEASE_INFO_SIZE; i++) { + systemInfo.u8_releaseInfo[i] = data[index++]; + } + + logError(1, "%s %s \n", tag, + printHex("Release Info = ", systemInfo.u8_releaseInfo, + RELEASE_INFO_SIZE, temp)); + memset(temp, 0, 256); + + u8ToU32(&data[index], &systemInfo.u32_fwCrc); + index += 4; + u8ToU32(&data[index], &systemInfo.u32_cfgCrc); + + index += 4; + + index += 8; + + u8ToU16(&data[index], &systemInfo.u16_scrResX); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_scrResY); + index += 2; + logError(0, "%s Screen Resolution = %d x %d \n", tag, + systemInfo.u16_scrResX, systemInfo.u16_scrResY); + systemInfo.u8_scrTxLen = data[index++]; + logError(0, "%s TX Len = %d \n", tag, systemInfo.u8_scrTxLen); + systemInfo.u8_scrRxLen = data[index++]; + logError(0, "%s RX Len = %d \n", tag, systemInfo.u8_scrRxLen); + systemInfo.u8_keyLen = data[index++]; + logError(0, "%s Key Len = %d \n", tag, systemInfo.u8_keyLen); + systemInfo.u8_forceLen = data[index++]; + logError(0, "%s Force Len = %d \n", tag, systemInfo.u8_forceLen); + + index += 40; + + u8ToU16(&data[index], &systemInfo.u16_dbgInfoAddr); + index += 2; + + index += 6; + + u8ToU16(&data[index], &systemInfo.u16_msTchRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_msTchFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_msTchStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_msTchBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_ssTchTxRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssTchTxFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssTchTxStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssTchTxBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_ssTchRxRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssTchRxFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssTchRxStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssTchRxBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_keyRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_keyFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_keyStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_keyBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_frcRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_frcFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_frcStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_frcBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_ssHvrTxRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssHvrTxFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssHvrTxStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssHvrTxBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_ssHvrRxRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssHvrRxFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssHvrRxStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssHvrRxBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_ssPrxTxRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssPrxTxFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssPrxTxStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssPrxTxBaselineAddr); + index += 2; + + u8ToU16(&data[index], &systemInfo.u16_ssPrxRxRawAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssPrxRxFilterAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssPrxRxStrenAddr); + index += 2; + u8ToU16(&data[index], &systemInfo.u16_ssPrxRxBaselineAddr); + index += 2; + + logError(0, "%s Parsed %d bytes! \n", tag, index); + + if (index != SYS_INFO_SIZE) { + logError(1, "%s %s: index = %d different from %d ERROR %08X\n", + tag, __func__, index, SYS_INFO_SIZE, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + logError(0, "%s System Info Read DONE!\n", tag); + return OK; + +FAIL: + defaultSysInfo(isI2cError(ret)); + return ret; +} + +/** @}*/ + +/** + * Read data from the Config Memory + * @param offset Starting address in the Config Memory of data to read + * @param outBuf pointer of a byte array which contain the bytes to read + * @param len number of bytes to read + * @return OK if success or an error code which specify the type of error encountered + */ +int readConfig(u16 offset, u8 *outBuf, int len) +{ + int ret; + u64 final_address = offset + ADDR_CONFIG_OFFSET; + + logError(0, "%s %s: Starting to read config memory at %08X ...", tag, + __func__, final_address); + ret = fts_writeReadU8UX(FTS_CMD_CONFIG_R, BITS_16, final_address, + outBuf, len, DUMMY_CONFIG); + if (ret < OK) { + logError( + 1, + "%s %s: Impossible to read Config Memory... ERROR %08X!", + tag, __func__, ret); + return ret; + } + + logError(0, "%s %s: Read config memory FINISHED!", tag, __func__); + return OK; +} + +/** + * Disable the interrupt so the ISR of the driver can not be called + * @return OK if success or an error code which specify the type of error encountered + */ +int fts_disableInterrupt(void) +{ + if (getClient() != NULL) { + logError(0, "%s Number of disable = %d \n", tag, + disable_irq_count); + if (disable_irq_count == 0) { + logError(0, "%s Excecuting Disable... \n", tag); + disable_irq(getClient()->irq); + disable_irq_count++; + logError(1, "%s Interrupt Disabled!\n", tag); + } + return OK; + } else { + logError(1, "%s %s: Impossible get client irq... ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +/** + * Disable the interrupt async so the ISR of the driver can not be called + * @return OK if success or an error code which specify the type of error encountered + */ +int fts_disableInterruptNoSync(void) +{ + if (getClient() != NULL) { + spin_lock_irq(&fts_int); + logError(0, "%s Number of disable = %d \n", tag, + disable_irq_count); + if (disable_irq_count == 0) { + logError(0, "%s Executing Disable... \n", tag); + disable_irq_nosync(getClient()->irq); + disable_irq_count++; + } + + spin_unlock_irq(&fts_int); + logError(0, "%s Interrupt No Sync Disabled!\n", tag); + return OK; + } else { + logError(1, "%s %s: Impossible get client irq... ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +/** + * Reset the disable_irq count + * @return OK + */ +int fts_resetDisableIrqCount(void) +{ + disable_irq_count = 0; + return OK; +} + +/** + * Enable the interrupt so the ISR of the driver can be called + * @return OK if success or an error code which specify the type of error encountered + */ +int fts_enableInterrupt(void) +{ + if (getClient() != NULL) { + logError(0, "%s Number of re-enable = %d \n", tag, + disable_irq_count); + while (disable_irq_count > 0) { + logError(0, "%s Excecuting Enable... \n", tag); + enable_irq(getClient()->irq); + disable_irq_count--; + logError(1, "%s Interrupt Enabled!\n", tag); + } + return OK; + } else { + logError(1, "%s %s: Impossible get client irq... ERROR %08X\n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +/** +* Check if there is a crc error in the IC which prevent the fw to run. +* @return OK if no CRC error, or a number >OK according the CRC error found +*/ +int fts_crc_check(void) +{ + u8 val; + u8 crc_status; + int res; + u8 error_to_search[6] = { + EVT_TYPE_ERROR_CRC_CFG_HEAD, EVT_TYPE_ERROR_CRC_CFG, + EVT_TYPE_ERROR_CRC_CX, EVT_TYPE_ERROR_CRC_CX_HEAD, + EVT_TYPE_ERROR_CRC_CX_SUB, EVT_TYPE_ERROR_CRC_CX_SUB_HEAD + }; + + res = fts_writeReadU8UX(FTS_CMD_HW_REG_R, ADDR_SIZE_HW_REG, ADDR_CRC, + &val, 1, DUMMY_HW_REG); + if (res < OK) { + logError(1, "%s %s Cannot read crc status ERROR %08X\n", tag, + __func__, res); + return res; + } + + crc_status = val & CRC_MASK; + if (crc_status != OK) { + logError(1, "%s %s CRC ERROR = %02X \n", tag, __func__, + crc_status); + return CRC_CODE; + } + + logError(1, "%s %s: Verifying if Config CRC Error...\n", tag, __func__); + res = fts_system_reset(); + if (res >= OK) { + res = pollForErrorType(error_to_search, 2); + if (res < OK) { + logError(1, "%s %s: No Config CRC Error Found! \n", tag, + __func__); + logError(1, "%s %s: Verifying if Cx CRC Error...\n", + tag, __func__); + res = pollForErrorType(&error_to_search[2], 4); + if (res < OK) { + logError(1, "%s %s: No Cx CRC Error Found! \n", + tag, __func__); + return OK; + } else { + logError( + 1, + "%s %s: Cx CRC Error found! CRC ERROR = %02X\n", + tag, __func__, res); + return CRC_CX; + } + } else { + logError( + 1, + "%s %s: Config CRC Error found! CRC ERROR = %02X\n", + tag, __func__, res); + return CRC_CONFIG; + } + } else { + logError( + 1, + "%s %s: Error while executing system reset! ERROR %08X\n", + tag, __func__, res); + return res; + } + + return OK; +} + +/** + * Request a host data and use the sync method to understand when the FW load it + * @param type the type ID of host data to load (@link load_opt Load Host Data Option @endlink) + * @return OK if success or an error code which specify the type of error encountered + */ +int requestSyncFrame(u8 type) +{ + u8 request[3] = { FTS_CMD_SYSTEM, SYS_CMD_LOAD_DATA, type }; + u8 readData[DATA_HEADER] = { 0 }; + int ret, retry = 0, retry2 = 0, time_to_count; + int count, new_count; + + logError(0, "%s %s: Starting to get a sync frame...\n", tag, __func__); + + while (retry2 < RETRY_MAX_REQU_DATA) { + logError(0, "%s %s: Reading count...\n", tag, __func__); + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, + ADDR_FRAMEBUFFER, readData, DATA_HEADER, + DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError( + 0, + "%s %s: Error while reading count! ERROR %08X \n", + tag, __func__, ret | ERROR_REQU_DATA); + ret |= ERROR_REQU_DATA; + retry2++; + continue; + } + + if (readData[0] != HEADER_SIGNATURE) { + logError( + 1, + "%s %s: Invalid Signature while reading count! ERROR %08X \n", + tag, __func__, ret | ERROR_REQU_DATA); + ret |= ERROR_REQU_DATA; + retry2++; + continue; + } + + count = (readData[3] << 8) | readData[2]; + new_count = count; + logError(0, "%s %s: Base count = %d\n", tag, __func__, count); + + logError(0, "%s %s: Requesting frame %02X attempt = %d \n", + tag, __func__, type, retry2 + 1); + ret = fts_write_dma_safe(request, ARRAY_SIZE(request)); + if (ret >= OK) { + logError(0, "%s %s: Polling for new count... \n", tag, + __func__); + time_to_count = TIMEOUT_REQU_DATA / TIMEOUT_RESOLUTION; + while (count == new_count && retry < time_to_count) { + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, + BITS_16, + ADDR_FRAMEBUFFER, + readData, DATA_HEADER, + DUMMY_FRAMEBUFFER); + if (ret >= OK && + readData[0] == HEADER_SIGNATURE) { + new_count = ((readData[3] << 8) | + readData[2]); + } else { + logError( + 0, + "%s %s: invalid Signature or can not read count... ERROR %08X \n", + tag, __func__, ret); + } + retry++; + mdelay(TIMEOUT_RESOLUTION); + } + + if (count == new_count) { + logError( + 1, + "%s %s: New count not received! ERROR %08X \n", + tag, __func__, + ERROR_TIMEOUT | ERROR_REQU_DATA); + ret = ERROR_TIMEOUT | ERROR_REQU_DATA; + } else { + logError( + 0, + "%s %s: New count found! count = %d! Frame ready! \n", + tag, __func__, new_count); + return OK; + } + } + retry2++; + } + logError(1, "%s %s: Request Data failed! ERROR %08X \n", tag, __func__, + ret); + return ret; +} + +int calculateCRC8(u8 *u8_srcBuff, int size, u8 *crc) +{ + u8 u8_remainder; + u8 bit; + int i = 0; + u8_remainder = 0x00; + + logError(0, "%s %s: Start CRC computing...\n", tag, __func__); + if (size != 0 && u8_srcBuff != NULL) { + for (i = 0; i < size; i++) { + u8_remainder ^= u8_srcBuff[i]; + for (bit = 8; bit > 0; --bit) { + if (u8_remainder & (0x1 << 7)) { + u8_remainder = (u8_remainder << 1) ^ + 0x9B; + } else { + u8_remainder = (u8_remainder << 1); + } + } + } + *crc = u8_remainder; + logError(0, "%s %s: CRC value = %02X\n", tag, __func__, *crc); + return OK; + } else { + logError( + 1, + "%s %s: Arguments passed not valid! Data pointer = NULL or size = 0 (%d) ERROR %08X\n", + tag, __func__, size, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +int writeLockDownInfo(u8 *data, int size, u8 lock_id) +{ + int ret, i; + u8 crc_data = 0; + u8 crc_head = 0; + u8 cmd_lockdown_prepare[8] = { + LOCKDOWN_SIGNATURE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + u8 cmd_lockdown_crc[4] = { 0x00 }; + u8 lockdown_save[3] = { 0xA4, 0x00, 0x04 }; + u8 *temp = NULL; + u8 error_to_search[4] = { EVT_TYPE_ERROR_LOCKDOWN_FLASH, + EVT_TYPE_ERROR_LOCKDOWN_CRC, + EVT_TYPE_ERROR_LOCKDOWN_NO_DATA, + EVT_TYPE_ERROR_LOCKDOWN_WRITE_FULL }; + + logError(0, "%s %s:enter", tag, __func__); + if (lock_id < 0x70 || lock_id > 0x77 || size <= 0 || + size > LOCKDOWN_LENGTH - 20) { + logError(1, + "%s %s the lock id type is:%02X size:%d not support\n", + tag, __func__, lock_id, size); + return ERROR_LOCKDOWN_CODE; + } + + temp = printHex_data("Lockdown Code = ", data, size); + if (temp != NULL) { + logError(1, "%s: %s", __func__, temp); + kfree(temp); + } + + logError(0, "%s: Writing Lockdown code into the IC ...\n", __func__); + fts_disableInterrupt(); + for (i = 0; i < 3; i++) { + cmd_lockdown_prepare[1] = lock_id; + ret = calculateCRC8(data, size, &crc_data); + if (ret < OK) { + logError( + 1, + "%s %s: Unable to compute data CRC.. ERROR %08X\n", + tag, __func__, ret); + ret = (ret | ERROR_LOCKDOWN_CODE); + continue; + } + logError(0, "%s %s: Get the data CRC value:%02X\n", tag, + __func__, crc_data); + ret = fts_writeU8UX(LOCKDOWN_WRITEREAD_CMD, BITS_16, + ADDR_LOCKDOWN, cmd_lockdown_prepare, + ARRAY_SIZE(cmd_lockdown_prepare)); + if (ret < OK) { + logError( + 1, + "%s %s: Unable to write Lockdown data prepare at %d iteration.. ERROR %08X\n", + tag, __func__, i, ret); + ret = (ret | ERROR_LOCKDOWN_CODE); + continue; + } + logError(0, "%s %s: Compute 8bit header CRC...\n", tag, + __func__); + + cmd_lockdown_crc[0] = (u8)size; + cmd_lockdown_crc[1] = crc_data; + cmd_lockdown_crc[2] = lock_id; + ret = calculateCRC8(cmd_lockdown_crc, 3, &crc_head); + if (ret < OK) { + logError( + 1, + "%s %s: Unable to compute head CRC.. ERROR %08X\n", + tag, __func__, ret); + ret = (ret | ERROR_LOCKDOWN_CODE); + continue; + } + cmd_lockdown_crc[3] = crc_head; + logError(0, "%s %s: Get the header CRC value:%02X\n", tag, + __func__, crc_head); + + ret = fts_writeU8UX(LOCKDOWN_WRITEREAD_CMD, BITS_16, + ADDR_LOCKDOWN + LOCKDOWN_DATA_OFFSET - + LOCKDOWN_HEAD_LENGTH, + cmd_lockdown_crc, + ARRAY_SIZE(cmd_lockdown_crc)); + if (ret < OK) { + logError( + 1, + "%s %s: Unable to write Lockdown head at %d iteration.. ERROR %08X\n", + tag, __func__, i, ret); + ret = (ret | ERROR_LOCKDOWN_CODE); + continue; + } + mdelay(10); + ret = fts_writeU8UX(LOCKDOWN_WRITEREAD_CMD, BITS_16, + ADDR_LOCKDOWN + LOCKDOWN_DATA_OFFSET, data, + size); + if (ret < OK) { + logError( + 1, + "%s %s: Unable to write Lockdown head at %d iteration.. ERROR %08X\n", + tag, __func__, i, ret); + ret = (ret | ERROR_LOCKDOWN_CODE); + continue; + } + mdelay(10); + ret = fts_write_dma_safe(lockdown_save, 3); + mdelay(5); + ret = checkEcho(lockdown_save, 3); + if (ret < OK) { + logError(1, "%s No Echo received.. ERROR %08X !\n", tag, + ret); + continue; + } else { + logError(1, "%s Echo FOUND... OK!\n", tag, ret); + ret = pollForErrorType(error_to_search, 4); + if (ret < OK) { + logError(1, "%s %s: No Error Found! \n", tag, + __func__); + ret = OK; + } else { + logError( + 1, + "%s %s: have error when write lockdown ERROR = %02X\n", + tag, __func__, ret); + ret = ERROR_LOCKDOWN_CODE; + } + break; + } + } + if (ret < OK) + logError(1, "%s %s end, write lockdown failed\n", tag, __func__, + ret); + else + logError(1, "%s %s end, write lockdown success\n", tag, + __func__, ret); + + fts_enableInterrupt(); + return ret; +} + +int readLockDownInfo(u8 *lockData, u8 lock_id, int size) +{ + int ret = 0, i; + int loaded_cnt = 0; + int loaded_cnt_after = 0; + u8 *temp = NULL; + char *datatemp = NULL; + u8 cmd_lockdown[3] = { 0xA4, 0x06, 0x00 }; + + logError(0, "%s %s:enter", tag, __func__); + if (lock_id < 0x70 || lock_id > 0x77 || size <= 0 || + size > LOCKDOWN_LENGTH - 20) { + logError(1, "%s the lock id type is:%02X not support\n", tag, + lock_id); + return ERROR_LOCKDOWN_CODE; + } + + temp = (u8 *)kmalloc(LOCKDOWN_LENGTH * sizeof(u8), GFP_KERNEL); + if (temp == NULL) { + logError(1, "FTS temp alloc memory failed \n"); + return -ENOMEM; + } + memset(temp, 0, LOCKDOWN_LENGTH * sizeof(u8)); + + fts_disableInterrupt(); + for (i = 0; i < 3; i++) { + ret = fts_writeReadU8UX(LOCKDOWN_WRITEREAD_CMD, BITS_16, + ADDR_LOCKDOWN, temp, + LOCKDOWN_HEAD_LENGTH, DUMMY_CONFIG); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading data ERROR %08X \n", + tag, __func__, ret); + goto END; + } + loaded_cnt = (int)((temp[3] & 0xFF) << 8) + (temp[2] & 0xFF); + cmd_lockdown[2] = lock_id; + fts_write_dma_safe(cmd_lockdown, 3); + mdelay(10); + ret = checkEcho(cmd_lockdown, 3); + if (ret < OK) { + logError(1, "%s No Echo received.. ERROR %08X !\n", tag, + ret); + continue; + } else { + logError(1, "%s Echo FOUND... OK!\n", tag, ret); + } + ret = fts_writeReadU8UX(LOCKDOWN_WRITEREAD_CMD, BITS_16, + ADDR_LOCKDOWN, temp, + size + LOCKDOWN_DATA_OFFSET, + DUMMY_CONFIG); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading data ERROR %08X \n", + tag, __func__, ret); + goto END; + } + + loaded_cnt_after = + (int)((temp[3] & 0xFF) << 8) + (temp[2] & 0xFF); + if (temp[4] == EVT_TYPE_ERROR_LOCKDOWN_FLASH || + temp[4] == EVT_TYPE_ERROR_LOCKDOWN_NO_DATA) { + logError( + 1, + "%s %s: can not read the lockdown code ERROR type:%02X\n", + tag, __func__, temp[4]); + ret = ERROR_LOCKDOWN_CODE; + goto END; + } + + logError( + 1, + "%s %s signature:%02X id:%02X %02X beforecnt:%d,aftercnt:%d\n", + tag, __func__, temp[0], temp[1], lock_id, loaded_cnt, + loaded_cnt_after); + if (loaded_cnt_after == loaded_cnt + 1) { + ret = OK; + memcpy(lockData, &temp[LOCKDOWN_DATA_OFFSET], size); + break; + } + } + + datatemp = printHex_data("Lockdown Code = ", lockData, size); + if (datatemp != NULL) { + logError(1, "%s %s", tag, datatemp); + kfree(datatemp); + } + +END: + fts_enableInterrupt(); + kfree(temp); + return ret; +} + +int fts_get_lockdown_info(u8 *lockData, struct fts_ts_info *info) +{ + int ret = 0, i; + int loaded_cnt = 0; + u8 lock_id = FTS_CMD_LOCKDOWN_ID; + int size = FTS_LOCKDOWN_SIZE; + int loaded_cnt_after = 0; + u8 *temp = NULL; + u8 cmd_lockdown[3] = { 0xA4, 0x06, 0x00 }; + char *datatemp = NULL; + + if (info == NULL) + return ERROR_LOCKDOWN_CODE; + if (info->lockdown_is_ok) { + logError(1, "%s %s aleady get,skip\n", tag, __func__); + return OK; + } + logError(0, "%s %s:enter", tag, __func__); + if (lock_id < 0x70 || lock_id > 0x77) { + logError(1, "%s the lock id type is not support\n", tag); + return ERROR_LOCKDOWN_CODE; + } + + temp = (u8 *)kmalloc(1024 * sizeof(u8), GFP_KERNEL); + if (temp == NULL) { + logError(1, "FTS temp alloc memory failed \n"); + return -ENOMEM; + } + memset(temp, 0, 1024 * sizeof(u8)); + + fts_disableInterrupt(); + + for (i = 0; i < LOCKDOWN_CODE_RETRY; i++) { + ret = fts_writeReadU8UX(LOCKDOWN_WRITEREAD_CMD, BITS_16, + ADDR_LOCKDOWN, temp, + LOCKDOWN_HEAD_LENGTH, DUMMY_CONFIG); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading data ERROR %08X \n", + tag, __func__, ret); + goto END; + } + loaded_cnt = (int)((temp[3] & 0xFF) << 8) + (temp[2] & 0xFF); + cmd_lockdown[2] = lock_id; + fts_write_dma_safe(cmd_lockdown, 3); + mdelay(10); + ret = checkEcho(cmd_lockdown, 3); + if (ret < OK) { + logError(1, "%s No Echo received.. ERROR %08X !\n", tag, + ret); + continue; + } else { + logError(1, "%s Echo FOUND... OK!\n", tag, ret); + } + ret = fts_writeReadU8UX(LOCKDOWN_WRITEREAD_CMD, BITS_16, + ADDR_LOCKDOWN, temp, + size + LOCKDOWN_DATA_OFFSET, + DUMMY_CONFIG); + if (ret < OK) { + logError( + 1, + "%s %s: error while reading data ERROR %08X \n", + tag, __func__, ret); + goto END; + } + + loaded_cnt_after = + (int)((temp[3] & 0xFF) << 8) + (temp[2] & 0xFF); + if (temp[4] == EVT_TYPE_ERROR_LOCKDOWN_FLASH || + temp[4] == EVT_TYPE_ERROR_LOCKDOWN_NO_DATA) { + logError( + 1, + "%s %s: can not read the lockdown code ERROR type:%02X\n", + tag, __func__, temp[4]); + ret = ERROR_LOCKDOWN_CODE; + goto END; + } + + logError( + 1, + "%s %s signature:%02X id:%02X %02X beforecnt:%d,aftercnt:%d\n", + tag, __func__, temp[0], temp[1], lock_id, loaded_cnt, + loaded_cnt_after); + if (loaded_cnt_after == loaded_cnt + 1) { + ret = OK; + memcpy(lockData, &temp[LOCKDOWN_DATA_OFFSET], size); + break; + } + } + + datatemp = printHex_data("Lockdown Code = ", lockData, size); + if (datatemp != NULL) { + logError(0, "%s %s", tag, datatemp); + kfree(datatemp); + } + +END: + fts_enableInterrupt(); + kfree(temp); + return ret; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.h new file mode 100644 index 000000000000..1e09174e4523 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsCore.h @@ -0,0 +1,187 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS Core definitions * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsCore.h +* \brief Contains all the definitions and structs of Core functionalities +*/ + +#ifndef FTS_CORE_H +#define FTS_CORE_H + +#include "ftsHardware.h" +#include "ftsSoftware.h" +#include "../fts.h" + +/*HW DATA*/ +#define GPIO_NOT_DEFINED \ + -1 /*value assumed by reset_gpio when the reset pin of the IC is not connected*/ + +#define ADDR_SIZE_HW_REG \ + BITS_32 /*value of AddrSize for Hw register in FTI @see AddrSize*/ + +#define DATA_HEADER \ + 4 /*size in byte of the header loaded with the data in the frambuffer*/ +#define LOCKDOWN_CODE_RETRY 2 +/** + * Type of CRC errors + */ +typedef enum { + CRC_CODE = 1, /*CRC in the code section*/ + CRC_CONFIG = 2, /*CRC in the config section*/ + CRC_CX = 3, /*CRC in the cx section*/ + CRC_PANEL = 4 /*CRC in the panel section*/ +} CRC_Error; + +/*CHIP INFO*/ +/** @defgroup system_info System Info +* System Info Data collect the most important informations about hw and fw +* @{ +*/ +#define SYS_INFO_SIZE 208 /*Size in bytes of System Info data*/ +#define DIE_INFO_SIZE 16 /*num bytes of die info*/ +#define EXTERNAL_RELEASE_INFO_SIZE 8 /*num bytes of external release in config*/ +#define RELEASE_INFO_SIZE \ + (EXTERNAL_RELEASE_INFO_SIZE + \ + 8) /*num bytes of release info in sys info (first bytes are external release)*/ +/** @}*/ + +/*RETRY MECHANISM*/ +#define RETRY_MAX_REQU_DATA \ + 2 /*Max number of attemps performed when requesting data*/ +#define RETRY_SYSTEM_RESET 3 /*Max number of attemps performed to reset the IC*/ + +/*LOCKDOWN INFO*/ +#define LOCKDOWN_LENGTH 384 +#define LOCKDOWN_HEAD_LENGTH 4 +#define LOCKDOWN_DATA_OFFSET 20 +#define LOCKDOWN_SIGNATURE 0x5A +#define ADDR_LOCKDOWN ((u64)0x0000000000000000) +#define LOCKDOWN_WRITEREAD_CMD 0xA6 + +/** @addtogroup system_info +* @{ +*/ + +/** + * Struct which contains fundamental informations about the chip and its configuration + */ +typedef struct { + u16 u16_apiVer_rev; /*API revision version*/ + u8 u8_apiVer_minor; /*API minor version*/ + u8 u8_apiVer_major; /*API major version*/ + u16 u16_chip0Ver; /*Dev0 version*/ + u16 u16_chip0Id; /*Dev0 ID*/ + u16 u16_chip1Ver; /*Dev1 version*/ + u16 u16_chip1Id; /*Dev1 ID*/ + u16 u16_fwVer; /*Fw version*/ + u16 u16_svnRev; /*SVN Revision*/ + u16 u16_cfgVer; /*Config Version*/ + u16 u16_cfgProgectId; /*Config Project ID*/ + u16 u16_cxVer; /*Cx Version*/ + u16 u16_cxProjectId; /*Cx Project ID*/ + u8 u8_cfgAfeVer; /*AFE version in Config*/ + u8 u8_cxAfeVer; /*AFE version in CX*/ + u8 u8_panelCfgAfeVer; /*AFE version in PanelMem*/ + u8 u8_protocol; /*Touch Report Protocol*/ + u8 u8_dieInfo[DIE_INFO_SIZE]; /*Die information*/ + u8 u8_releaseInfo[RELEASE_INFO_SIZE]; /*Release information*/ + u32 u32_fwCrc; /*Crc of FW*/ + u32 u32_cfgCrc; /*Crc of config*/ + + u16 u16_scrResX; /*X resolution on main screen*/ + u16 u16_scrResY; /*Y resolution on main screen*/ + u8 u8_scrTxLen; /*Tx length*/ + u8 u8_scrRxLen; /*Rx length*/ + u8 u8_keyLen; /*Key Len*/ + u8 u8_forceLen; /*Force Len*/ + + u16 u16_dbgInfoAddr; /*Offset of debug Info structure*/ + + u16 u16_msTchRawAddr; /*Offset of MS touch raw frame*/ + u16 u16_msTchFilterAddr; /*Offset of MS touch filter frame*/ + u16 u16_msTchStrenAddr; /*Offset of MS touch strength frame*/ + u16 u16_msTchBaselineAddr; /*Offset of MS touch baseline frame*/ + + u16 u16_ssTchTxRawAddr; /*Offset of SS touch force raw frame*/ + u16 u16_ssTchTxFilterAddr; /*Offset of SS touch force filter frame*/ + u16 u16_ssTchTxStrenAddr; /*Offset of SS touch force strength frame*/ + u16 u16_ssTchTxBaselineAddr; /*Offset of SS touch force baseline frame*/ + + u16 u16_ssTchRxRawAddr; /*Offset of SS touch sense raw frame*/ + u16 u16_ssTchRxFilterAddr; /*Offset of SS touch sense filter frame*/ + u16 u16_ssTchRxStrenAddr; /*Offset of SS touch sense strength frame*/ + u16 u16_ssTchRxBaselineAddr; /*Offset of SS touch sense baseline frame*/ + + u16 u16_keyRawAddr; /*Offset of key raw frame*/ + u16 u16_keyFilterAddr; /*Offset of key filter frame*/ + u16 u16_keyStrenAddr; /*Offset of key strength frame*/ + u16 u16_keyBaselineAddr; /*Offset of key baseline frame*/ + + u16 u16_frcRawAddr; /*Offset of force touch raw frame*/ + u16 u16_frcFilterAddr; /*Offset of force touch filter frame*/ + u16 u16_frcStrenAddr; /*Offset of force touch strength frame*/ + u16 u16_frcBaselineAddr; /*Offset of force touch baseline frame*/ + + u16 u16_ssHvrTxRawAddr; /*Offset of SS hover Force raw frame*/ + u16 u16_ssHvrTxFilterAddr; /*Offset of SS hover Force filter frame*/ + u16 u16_ssHvrTxStrenAddr; /*Offset of SS hover Force strength frame*/ + u16 u16_ssHvrTxBaselineAddr; /*Offset of SS hover Force baseline frame*/ + + u16 u16_ssHvrRxRawAddr; /*Offset of SS hover Sense raw frame*/ + u16 u16_ssHvrRxFilterAddr; /*Offset of SS hover Sense filter frame*/ + u16 u16_ssHvrRxStrenAddr; /*Offset of SS hover Sense strength frame*/ + u16 u16_ssHvrRxBaselineAddr; /*Offset of SS hover Sense baseline frame*/ + + u16 u16_ssPrxTxRawAddr; /*Offset of SS proximity force raw frame*/ + u16 u16_ssPrxTxFilterAddr; /*Offset of SS proximity force filter frame*/ + u16 u16_ssPrxTxStrenAddr; /*Offset of SS proximity force strength frame*/ + u16 u16_ssPrxTxBaselineAddr; /*Offset of SS proximity force baseline frame*/ + + u16 u16_ssPrxRxRawAddr; /*Offset of SS proximity sense raw frame*/ + u16 u16_ssPrxRxFilterAddr; /*Offset of SS proximity sense filter frame*/ + u16 u16_ssPrxRxStrenAddr; /*Offset of SS proximity sense strength frame*/ + u16 u16_ssPrxRxBaselineAddr; /*Offset of SS proximity sense baseline frame*/ +} SysInfo; + +/** @}*/ + +int initCore(struct fts_ts_info *info); +void setResetGpio(int gpio); +int fts_system_reset(void); +int isSystemResettedUp(void); +int isSystemResettedDown(void); +void setSystemResetedUp(int val); +void setSystemResetedDown(int val); +int pollForEvent(int *event_to_search, int event_bytes, u8 *readData, + int time_to_wait); +int checkEcho(u8 *cmd, int size); +int setScanMode(u8 mode, u8 settings); +int setFeatures(u8 feat, u8 *settings, int size); +int defaultSysInfo(int i2cError); +int writeSysCmd(u8 sys_cmd, u8 *sett, int size); +int readSysInfo(int request); +int readConfig(u16 offset, u8 *outBuf, int len); +int fts_disableInterrupt(void); +int fts_disableInterruptNoSync(void); +int fts_resetDisableIrqCount(void); +int fts_enableInterrupt(void); +int fts_crc_check(void); +int requestSyncFrame(u8 type); +int fts_get_lockdown_info(u8 *lockData, struct fts_ts_info *info); +int writeLockDownInfo(u8 *data, int size, u8 lock_id); +int readLockDownInfo(u8 *lockData, u8 lock_id, int size); + +#endif /* FTS_CORE_H */ diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.c new file mode 100644 index 000000000000..5bd34cc26fd5 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.c @@ -0,0 +1,360 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS error/info kernel log reporting * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsError.c +* \brief Contains all the function which handle with Error conditions +*/ + +#include +#include +#include +#include +#include + +#include "../fts.h" +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsIO.h" +#include "ftsTool.h" +#include "ftsCompensation.h" + +static ErrorList errors; + +/** +* Print messages in the kernel log +* @param force if 1, the log is printed always otherwise only if DEBUG is defined, the log will be printed +* @param msg string containing the message to print +* @param ... additional parameters that are used in msg according the format of printf +*/ +void logError(int force, const char *msg, ...) +{ + if (force == 1 +#ifdef DEBUG + || 1 +#endif + ) { + va_list args; + va_start(args, msg); + vprintk(msg, args); + va_end(args); + } +} + +/** +* Check if an error code is related to an I2C failure +* @param error error code to check +* @return 1 if the first level error code is I2C related otherwise 0 +*/ +int isI2cError(int error) +{ + if (((error & 0x000000FF) >= (ERROR_BUS_R & 0x000000FF)) && + ((error & 0x000000FF) <= (ERROR_BUS_O & 0x000000FF))) + return 1; + else + return 0; +} + +/** + * Dump in the kernel log some debug info in case of FW hang + * @param outBuf (optional)pointer to bytes array where to copy the debug info, if NULL the data will just printed on the kernel log + * @param size dimension in bytes of outBuf, if > ERROR_DUMP_ROW_SIZE*ERROR_DUMP_COL_SIZE, only the first ERROR_DUMP_ROW_SIZE*ERROR_DUMP_COL_SIZE bytes will be copied + * @return OK if success or an error code which specify the type of error encountered + */ +int dumpErrorInfo(u8 *outBuf, int size) +{ + int ret, i; + u8 data[ERROR_DUMP_ROW_SIZE * ERROR_DUMP_COL_SIZE] = { 0 }; + u32 sign = 0; + + logError(0, "%s %s: Starting dump of error info...\n", tag, __func__); + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, ADDR_ERROR_DUMP, + data, ERROR_DUMP_ROW_SIZE * ERROR_DUMP_COL_SIZE, + DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, "%s %s: reading data ERROR %08X\n", tag, __func__, + ret); + return ret; + } else { + if (outBuf != NULL) { + sign = size > ERROR_DUMP_ROW_SIZE * + ERROR_DUMP_COL_SIZE ? + ERROR_DUMP_ROW_SIZE * + ERROR_DUMP_COL_SIZE : + size; + memcpy(outBuf, data, sign); + logError(0, + "%s %s: error info copied in the buffer! \n", + tag, __func__); + } + logError(1, "%s %s: Error Info = \n", tag, __func__); + u8ToU32(data, &sign); + if (sign != ERROR_DUMP_SIGNATURE) + logError( + 1, + "%s %s: Wrong Error Signature! Data may be invalid! \n", + tag, __func__); + else + logError( + 1, + "%s %s: Error Signature OK! Data are valid! \n", + tag, __func__); + + for (i = 0; i < ERROR_DUMP_ROW_SIZE * ERROR_DUMP_COL_SIZE; + i++) { + if (i % ERROR_DUMP_COL_SIZE == 0) { + logError(1, KERN_ERR "\n%s %s: %d) ", tag, + __func__, i / ERROR_DUMP_COL_SIZE); + } + logError(1, "%02X ", data[i]); + } + logError(1, "\n"); + + logError(0, "%s %s: dump of error info FINISHED!\n", tag, + __func__); + return OK; + } +} + +/** +* Implement recovery strategies to be used when an error event is found while polling the FIFO +* @param event error event found during the polling +* @param size size of event +* @return OK if the error event doesn't require any action or the recovery strategy doesn't have any impact in the possible procedure that trigger the error, otherwise return an error code which specify the kind of error encountered. If ERROR_HANDLER_STOP_PROC the calling function must stop! +*/ +int errorHandler(u8 *event, int size) +{ + int res = OK; + struct fts_ts_info *info = NULL; + + if (getDev() != NULL) + info = dev_get_drvdata(getDev()); + + if (info != NULL && event != NULL && size > 1 && + event[0] == EVT_ID_ERROR) { + logError(0, "%s errorHandler: Starting handling...\n", tag); + addErrorIntoList(event, size); + switch (event[1]) { + case EVT_TYPE_ERROR_ESD: + res = fts_chip_powercycle(info); + if (res < OK) { + logError( + 1, + "%s errorHandler: Error performing powercycle ERROR %08X\n", + tag, res); + } + + res = fts_system_reset(); + if (res < OK) { + logError( + 1, + "%s errorHandler: Cannot reset the device ERROR %08X\n", + tag, res); + } + res = (ERROR_HANDLER_STOP_PROC | res); + break; + + case EVT_TYPE_ERROR_WATCHDOG: + dumpErrorInfo(NULL, 0); + res = fts_system_reset(); + if (res < OK) { + logError( + 1, + "%s errorHandler: Cannot reset the device ERROR %08X\n", + tag, res); + } + res = (ERROR_HANDLER_STOP_PROC | res); + break; + + case EVT_TYPE_ERROR_ITO_FORCETOGND: + logError(1, "%s errorHandler: Force Short to GND!\n", + tag); + break; + case EVT_TYPE_ERROR_ITO_SENSETOGND: + logError(1, "%s errorHandler: Sense short to GND! \n", + tag); + break; + case EVT_TYPE_ERROR_ITO_FORCETOVDD: + logError(1, "%s errorHandler: Force short to VDD!\n", + tag); + break; + case EVT_TYPE_ERROR_ITO_SENSETOVDD: + logError(1, "%s errorHandler: Sense short to VDD!\n", + tag); + break; + case EVT_TYPE_ERROR_ITO_FORCE_P2P: + logError(1, + "%s errorHandler: Force Pin to Pin Short!\n", + tag); + break; + case EVT_TYPE_ERROR_ITO_SENSE_P2P: + logError(1, + "%s errorHandler: Sense Pin to Pin Short!\n", + tag); + break; + case EVT_TYPE_ERROR_ITO_FORCEOPEN: + logError(1, "%s errorHandler: Force Open !\n", tag); + break; + case EVT_TYPE_ERROR_ITO_SENSEOPEN: + logError(1, "%s errorHandler: Sense Open !\n", tag); + break; + case EVT_TYPE_ERROR_ITO_KEYOPEN: + logError(1, "%s errorHandler: Key Open !\n", tag); + break; + + default: + logError(0, "%s errorHandler: No Action taken! \n", + tag); + break; + } + logError(0, "%s errorHandler: handling Finished! res = %08X\n", + tag, res); + return res; + } else { + logError( + 1, + "%s errorHandler: event Null or not correct size! ERROR %08X \n", + tag, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +/** +* Add an error event into the Error List +* @param event error event to add +* @param size size of event +* @return OK +*/ +int addErrorIntoList(u8 *event, int size) +{ + int i = 0; + + logError(0, "%s Adding error in to ErrorList... \n", tag); + + memcpy(&errors.list[errors.last_index * FIFO_EVENT_SIZE], event, size); + i = FIFO_EVENT_SIZE - size; + if (i > 0) { + logError(0, + "%s Filling last %d bytes of the event with zero...\n", + tag, i); + memset(&errors.list[errors.last_index * FIFO_EVENT_SIZE + size], + 0, i); + } + logError(0, "%s Adding error in to ErrorList... FINISHED!\n", tag); + + errors.count += 1; + if (errors.count > FIFO_DEPTH) + logError( + 1, + "%s ErrorList is going in overflow... the first %d event(s) were override!\n", + tag, errors.count - FIFO_DEPTH); + errors.last_index = (errors.last_index + 1) % FIFO_DEPTH; + + return OK; +} + +/** +* Reset the Error List setting the count and last_index to 0. +* @return OK +*/ +int resetErrorList(void) +{ + errors.count = 0; + errors.last_index = 0; + memset(errors.list, 0, FIFO_DEPTH * FIFO_EVENT_SIZE); + return OK; +} + +/** +* Get the number of error events copied into the Error List +* @return the number of error events into the Error List +*/ +int getErrorListCount(void) +{ + if (errors.count > FIFO_DEPTH) + return FIFO_DEPTH; + else + return errors.count; +} + +/** +* Scroll the Error List looking for the event specified +* @param event_to_search event_to_search pointer to an array of int where each element correspond to a byte of the event to find. If the element of the array has value -1, the byte of the event, in the same position of the element is ignored. +* @param event_bytes size of event_to_search +* @return a value >=0 if the event is found which represent the index of the Error List where the event is located otherwise an error code +*/ +int pollErrorList(int *event_to_search, int event_bytes) +{ + int i = 0, j = 0, find = 0; + int count = getErrorListCount(); + + logError(0, "%s Starting to poll ErrorList... \n", tag); + while (find != 1 && i < count) { + find = 1; + for (j = 0; j < event_bytes; j++) { + if (event_to_search[i] != -1 && + (int)errors.list[i * FIFO_EVENT_SIZE + j] != + event_to_search[i]) { + find = 0; + break; + } + } + i++; + } + if (find == 1) { + logError(1, "%s Error Found into ErrorList! \n", tag); + return i - 1; + } else { + logError(0, "%s Error Not Found into ErrorList! ERROR %08X \n", + tag, ERROR_TIMEOUT); + return ERROR_TIMEOUT; + } +} + +/** +* Poll the Error List looking for any error types passed in the arguments. Return at the first match! +* @param list pointer to a list of error types to look for +* @param size size of list +* @return error type found if success or ERROR_TIMEOUT +*/ +int pollForErrorType(u8 *list, int size) +{ + int i = 0, j = 0, find = 0; + int count = getErrorListCount(); + + logError(0, "%s %s: Starting to poll ErrorList... count = %d \n", tag, + __func__, count); + while (find != 1 && i < count) { + for (j = 0; j < size; j++) { + if (list[j] == errors.list[i * FIFO_EVENT_SIZE + 1]) { + find = 1; + break; + } + } + i++; + } + if (find == 1) { + logError(1, "%s %s: Error Type %02X into ErrorList! \n", tag, + __func__, list[j]); + return list[j]; + } else { + logError( + 0, + "%s %s: Error Type Not Found into ErrorList! ERROR %08X \n", + tag, __func__, ERROR_TIMEOUT); + return ERROR_TIMEOUT; + } +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.h new file mode 100644 index 000000000000..6f84dca97bad --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsError.h @@ -0,0 +1,181 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS error/info kernel log reporting * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsError.h +* \brief Contains all the definitions and structs which refer to Error conditions +*/ + +#ifndef FTS_ERROR_H +#define FTS_ERROR_H + +#include "ftsHardware.h" +#include "ftsSoftware.h" + +/** @defgroup error_codes Error Codes + * Error codes that can be reported by the driver functions. + * An error code is made up by 4 bytes, each byte indicate a logic error level.\n + * From the LSB to the MSB, the logic level increase going from a low level error (I2C,TIMEOUT) to an high level error (flashing procedure fail, production test fail etc) + * @{ + */ + +/*FIRST LEVEL ERROR CODE*/ +/** @defgroup first_level First Level Error Code +* @ingroup error_codes +* Errors related to low level operation which are not under control of driver, such as: communication protocol (I2C/SPI), timeout, file operations ... +* @{ +*/ +#define OK ((int)0x00000000) /*No ERROR*/ +#define ERROR_ALLOC ((int)0x80000001) /*allocation of memory failed*/ +#define ERROR_BUS_R ((int)0x80000002) /*i2c/spi read failed*/ +#define ERROR_BUS_W ((int)0x80000003) /*i2c/spi write failed*/ +#define ERROR_BUS_WR ((int)0x80000004) /*i2c/spi write/read failed*/ +#define ERROR_BUS_O ((int)0x80000005) /*error during opening an i2c device*/ +#define ERROR_OP_NOT_ALLOW ((int)0x80000006) /*operation not allowed*/ +#define ERROR_TIMEOUT \ + ((int)0x80000007) /*timeout expired! exceed the max number of retries or the max waiting time*/ +#define ERROR_FILE_NOT_FOUND \ + ((int)0x80000008) /*the file that i want to open is not found*/ +#define ERROR_FILE_PARSE ((int)0x80000009) /*error during parsing the file*/ +#define ERROR_FILE_READ ((int)0x8000000A) /*error during reading the file*/ +#define ERROR_LABEL_NOT_FOUND ((int)0x8000000B) /*label not found*/ +#define ERROR_FW_NO_UPDATE \ + ((int)0x8000000C) /*fw in the chip newer than the one in the memmh*/ +#define ERROR_FLASH_UNKNOWN ((int)0x8000000D) /*flash status busy or unknown*/ +/** @}*/ + +/*SECOND LEVEL ERROR CODE */ +/** @defgroup second_level Second Level Error Code +* @ingroup error_codes +* Errors related to simple logic operations in the IC which require one command or which are part of a more complex procedure +* @{ +*/ +#define ERROR_DISABLE_INTER \ + ((int)0x80000200) /*unable to disable the interrupt*/ +#define ERROR_ENABLE_INTER ((int)0x80000300) /*unable to activate the interrup*/ +#define ERROR_READ_CONFIG ((int)0x80000400) /*failed to read config memory*/ +#define ERROR_GET_OFFSET \ + ((int)0x80000500) /*unable to read an offset from memory*/ +#define ERROR_GET_FRAME_DATA \ + ((int)0x80000600) /*unable to retrieve the data of a required frame*/ +#define ERROR_DIFF_DATA_TYPE \ + ((int)0x80000700) /*FW answers with an event that has a different address respect the request done*/ +#define ERROR_WRONG_DATA_SIGN \ + ((int)0x80000800) /*the signature of the host data is not HEADER_SIGNATURE*/ +#define ERROR_SET_SCAN_MODE_FAIL \ + ((int)0x80000900) /*setting the scanning mode failed (sense on/off etc...)*/ +#define ERROR_SET_FEATURE_FAIL \ + ((int)0x80000A00) /*setting a specific feature failed*/ +#define ERROR_SYSTEM_RESET_FAIL \ + ((int)0x80000B00) /*the comand SYSTEM RESET failed*/ +#define ERROR_FLASH_NOT_READY \ + ((int)0x80000C00) /*flash status not ready within a timeout*/ +#define ERROR_FW_VER_READ \ + ((int)0x80000D00) /*unable to retrieve fw_vers or the config_id*/ +#define ERROR_GESTURE_ENABLE_FAIL \ + ((int)0x80000E00) /*unable to enable/disable the gesture*/ +#define ERROR_GESTURE_START_ADD \ + ((int)0x80000F00) /*unable to start to add custom gesture*/ +#define ERROR_GESTURE_FINISH_ADD \ + ((int)0x80001000) /*unable to finish to add custom gesture*/ +#define ERROR_GESTURE_DATA_ADD \ + ((int)0x80001100) /*unable to add custom gesture data*/ +#define ERROR_GESTURE_REMOVE \ + ((int)0x80001200) /*unable to remove custom gesture data*/ +#define ERROR_FEATURE_ENABLE_DISABLE \ + ((int)0x80001300) /*unable to enable/disable a feature mode in the IC*/ +#define ERROR_NOISE_PARAMETERS \ + ((int)0x80001400) /*unable to set/read noise parameter in the IC*/ +#define ERROR_CH_LEN \ + ((int)0x80001500) /*unable to retrieve the force and/or sense length*/ +/** @}*/ + +/*THIRD LEVEL ERROR CODE */ +/** @defgroup third_level Third Level Error Code +* @ingroup error_codes +* Errors related to logic operations in the IC which require more commands/steps or which are part of a more complex procedure +* @{ +*/ +#define ERROR_REQU_COMP_DATA \ + ((int)0x80010000) /*compensation data request failed*/ +#define ERROR_REQU_DATA ((int)0x80020000) /*data request failed*/ +#define ERROR_COMP_DATA_HEADER \ + ((int)0x80030000) /*unable to retrieve the compensation data header*/ +#define ERROR_COMP_DATA_GLOBAL \ + ((int)0x80040000) /*unable to retrieve the global compensation data*/ +#define ERROR_COMP_DATA_NODE \ + ((int)0x80050000) /*unable to retrieve the compensation data for each node*/ +#define ERROR_TEST_CHECK_FAIL \ + ((int)0x80060000) /*check of production limits or of fw answers failed*/ +#define ERROR_MEMH_READ ((int)0x80070000) /*memh reading failed*/ +#define ERROR_FLASH_BURN_FAILED ((int)0x80080000) /*flash burn failed*/ +#define ERROR_MS_TUNING ((int)0x80090000) /*ms tuning failed*/ +#define ERROR_SS_TUNING ((int)0x800A0000) /*ss tuning failed*/ +#define ERROR_LP_TIMER_TUNING ((int)0x800B0000) /*lp timer calibration failed*/ +#define ERROR_SAVE_CX_TUNING ((int)0x800C0000) /*save cx data to flash failed*/ +#define ERROR_HANDLER_STOP_PROC \ + ((int)0x800D0000) /*stop the poll of the FIFO if particular errors are found*/ +#define ERROR_CHECK_ECHO_FAIL \ + ((int)0x800E0000) /*unable to retrieve echo event*/ +#define ERROR_GET_FRAME ((int)0x800F0000) /*unable to get frame*/ +/** @}*/ + +/*FOURTH LEVEL ERROR CODE*/ +/** @defgroup fourth_level Fourth Level Error Code +* @ingroup error_codes +* Errors related to the highest logic operations in the IC which have an important impact on the driver flow or which require several commands and steps to be executed +* @{ +*/ +#define ERROR_PROD_TEST_DATA ((int)0x81000000) /*production data test failed*/ +#define ERROR_FLASH_PROCEDURE ((int)0x82000000) /*fw update procedure failed*/ +#define ERROR_PROD_TEST_ITO ((int)0x83000000) /*production ito test failed*/ +#define ERROR_PROD_TEST_INITIALIZATION \ + ((int)0x84000000) /*production initialization test failed*/ +#define ERROR_GET_INIT_STATUS \ + ((int)0x85000000) /*mismatch of the MS or SS tuning_version*/ +#define ERROR_LOCKDOWN_CODE \ + ((int)0x80001600) /*unable to write/rewrite/read lockdown code in the IC*/ + +#define EVT_TYPE_ERROR_LOCKDOWN_FLASH \ + 0x30 /*FW shall not proceed with any flash write/read*/ +#define EVT_TYPE_ERROR_LOCKDOWN_CRC \ + 0x31 /*FW shall discard the record and do not write to flash*/ +#define EVT_TYPE_ERROR_LOCKDOWN_NO_DATA \ + 0x32 /*No data of this type exisitng in flash*/ +#define EVT_TYPE_ERROR_LOCKDOWN_WRITE_FULL \ + 0x33 /*FW shall not write this new record to flash*/ +/** @}*/ + +/** +* Struct which store an ordered list of the errors events encountered during the polling of a FIFO. +* The max number of error events that can be stored is equal to FIFO_DEPTH +*/ +typedef struct { + u8 list[FIFO_DEPTH * + FIFO_EVENT_SIZE]; /*byte array which contains the series of error events encountered from the last reset of the list.*/ + int count; /*number of error events stored in the list*/ + int last_index; /*index of the list where will be stored the next error event. Subtract -1 to have the index of the last error event!*/ +} ErrorList; + +void logError(int force, const char *msg, ...); +int isI2cError(int error); +int dumpErrorInfo(u8 *outBuf, int size); +int errorHandler(u8 *event, int size); +int addErrorIntoList(u8 *event, int size); +int getErrorListCount(void); +int resetErrorList(void); +int pollErrorList(int *event_to_search, int event_bytes); +int pollForErrorType(u8 *list, int size); +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.c new file mode 100644 index 000000000000..05e2a22853ba --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.c @@ -0,0 +1,1058 @@ +/* + + ************************************************************************** + ** STMicroelectronics ** + ************************************************************************** + ** marco.cali@st.com ** + ************************************************************************** + * * + * FTS API for Flashing the IC * + * * + ************************************************************************** + ************************************************************************** + + */ + +/*! +* \file ftsFlash.c +* \brief Contains all the functions to handle the FW update process +*/ + +#include "ftsCore.h" +#include "ftsCompensation.h" +#include "ftsError.h" +#include "ftsFlash.h" +#include "ftsFrame.h" +#include "ftsIO.h" +#include "ftsSoftware.h" +#include "ftsTest.h" +#include "ftsTime.h" +#include "ftsTool.h" +#include "../fts.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef FW_H_FILE +#include "../fts_fw.h" +#endif + +extern SysInfo systemInfo; +extern struct fts_ts_info *fts_info; + +/** + * Read the fw version and config id from the chip + * @param fw_vers pointer to the variable which will contains the fw version + * @param config_id pointer to the variable which will contains the config id + * @return OK if success or an error code which specify the type of error encountered + */ +int getFirmwareVersion(u16 *fw_vers, u16 *config_id) +{ + u8 fwvers[DCHIP_FW_VER_BYTE]; + u8 confid[CONFIG_ID_BYTE]; + int res; + + res = fts_writeReadU8UX(FTS_CMD_HW_REG_R, ADDR_SIZE_HW_REG, + ADDR_DCHIP_FW_VER, fwvers, DCHIP_FW_VER_BYTE, + DUMMY_HW_REG); + if (res < OK) { + logError( + 1, + "%s getFirmwareVersion: unable to read fw_version ERROR %08X\n", + tag, ERROR_FW_VER_READ); + return (res | ERROR_FW_VER_READ); + } + + u8ToU16(fwvers, fw_vers); + if (*fw_vers != 0) { + res = readConfig(ADDR_CONFIG_ID, confid, CONFIG_ID_BYTE); + if (res < OK) { + logError( + 1, + "%s getFirmwareVersion: unable to read config_id ERROR %08X\n", + tag, ERROR_FW_VER_READ); + return (res | ERROR_FW_VER_READ); + } + u8ToU16(confid, config_id); + } else { + *config_id = 0x0000; + } + + logError(0, "%s FW VERS = %04X\n", tag, *fw_vers); + logError(0, "%s CONFIG ID = %04X\n", tag, *config_id); + return OK; +} + +/** +* Retrieve the actual FW data from the system (bin file or header file) +* @param pathToFile name of FW file to load or "NULL" if the FW data should be loaded by a .h file +* @param data pointer to the pointer which will contains the FW data +* @param size pointer to a variable which will contain the size of the loaded data +* @return OK if success or an error code which specify the type of error encountered +*/ +int getFWdata(const char *pathToFile, u8 **data, int *size) +{ + const struct firmware *fw = NULL; + struct device *dev = NULL; + int res, from = 0; + char *path = (char *)pathToFile; + + logError(1, "%s getFWdata starting ...\n", tag); + if (strncmp(pathToFile, "NULL", 4) == 0) { + from = 1; + path = (char *)fts_info->board->default_fw_name; + } + switch (from) { +#ifdef FW_H_FILE + case 1: + logError(1, "%s Read FW from .h file!\n", tag); + *size = FW_SIZE_NAME; + *data = (u8 *)kmalloc((*size) * sizeof(u8), GFP_KERNEL); + if (*data == NULL) { + logError( + 1, + "%s getFWdata: Impossible to allocate memory! ERROR %08X\n", + tag, ERROR_ALLOC); + return ERROR_ALLOC; + } + memcpy(*data, (u8 *)FW_ARRAY_NAME, (*size)); + + break; +#endif + default: + logError(1, "%s Read FW from BIN file %s !\n", tag, path); + dev = getDev(); + + if (dev != NULL) { + res = request_firmware(&fw, path, dev); + if (res == 0) { + *size = fw->size; + *data = (u8 *)kmalloc((*size) * sizeof(u8), + GFP_KERNEL); + if (*data == NULL) { + logError( + 1, + "%s getFWdata: Impossible to allocate memory! ERROR %08X\n", + tag, ERROR_ALLOC); + release_firmware(fw); + return ERROR_ALLOC; + } + memcpy(*data, (u8 *)fw->data, (*size)); + release_firmware(fw); + } else { + logError( + 1, + "%s getFWdata: No File found! ERROR %08X\n", + tag, ERROR_FILE_NOT_FOUND); + return ERROR_FILE_NOT_FOUND; + } + + } else { + logError(1, + "%s getFWdata: No device found! ERROR %08X\n", + tag, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + } + + logError(1, "%s getFWdata Finished!\n", tag); + return OK; +} + +/** +* Perform all the steps to read the FW that should be burnt in the IC from the system and parse it in order to fill a Firmware struct with the relevant info +* @param path name of FW file to load or "NULL" if the FW data should be loaded by a .h file +* @param fw pointer to a Firmware variable which will contains the FW data and info +* @param keep_cx if 1, the CX area will be loaded otherwise will be skipped +* @return OK if success or an error code which specify the type of error encountered +*/ +int readFwFile(const char *path, Firmware *fw, int keep_cx) +{ + int res; + int orig_size; + u8 *orig_data = NULL; + + res = getFWdata(path, &orig_data, &orig_size); + if (res < OK) { + logError( + 1, + "%s readFwFile: impossible retrieve FW... ERROR %08X\n", + tag, ERROR_MEMH_READ); + return (res | ERROR_MEMH_READ); + } + res = parseBinFile(orig_data, orig_size, fw, keep_cx); + if (res < OK) { + logError(1, "%s readFwFile: impossible parse ERROR %08X\n", tag, + ERROR_MEMH_READ); + return (res | ERROR_MEMH_READ); + } + + return OK; +} + +/** +* Perform all the steps necessary to burn the FW into the IC +* @param path name of FW file to load or "NULL" if the FW data should be loaded by a .h file +* @param force if 1, the flashing procedure will be forced and executed regardless the additional info, otherwise the FW in the file will be burnt only if it is newer than the one running in the IC +* @param keep_cx if 1, the CX area will be loaded and burnt otherwise will be skipped and the area will be untouched +* @return OK if success or an error code which specify the type of error encountered +*/ +int flashProcedure(const char *path, int force, int keep_cx) +{ + Firmware fw; + int res; + + fw.data = NULL; + logError(0, "%s Reading Fw file... \n", tag); + res = readFwFile(path, &fw, keep_cx); + if (res < OK) { + logError(1, "%s flashProcedure: ERROR %08X \n", tag, + (res | ERROR_FLASH_PROCEDURE)); + kfree(fw.data); + return (res | ERROR_FLASH_PROCEDURE); + } + logError(0, "%s Fw file read COMPLETED! \n", tag); + + logError(0, "%s Starting flashing procedure... \n", tag); + res = flash_burn(fw, force, keep_cx); + if (res < OK && res != (ERROR_FW_NO_UPDATE | ERROR_FLASH_BURN_FAILED)) { + logError(1, "%s flashProcedure: ERROR %08X \n", tag, + ERROR_FLASH_PROCEDURE); + kfree(fw.data); + return (res | ERROR_FLASH_PROCEDURE); + } + logError(0, "%s flashing procedure Finished!\n", tag); + kfree(fw.data); + + return res; +} + +/** +* Poll the Flash Status Registers after the execution of a command to check if the Flash becomes ready within a timeout +* @param type register to check according to the previous command sent +* @return OK if success or an error code which specify the type of error encountered +*/ +int wait_for_flash_ready(u8 type) +{ + u8 cmd[5] = { FTS_CMD_HW_REG_R, 0x20, 0x00, 0x00, type }; + + u8 readData[2] = { 0 }; + int i, res = -1; + + logError(0, "%s Waiting for flash ready ... \n", tag); + for (i = 0; i < FLASH_RETRY_COUNT && res != 0; i++) { + res = fts_writeRead_dma_safe(cmd, ARRAY_SIZE(cmd), readData, 2); + if (res < OK) { + logError(1, "%s wait_for_flash_ready: ERROR % 08X\n", + tag, ERROR_BUS_W); + } else { +#ifdef I2C_INTERFACE + res = readData[0] & 0x80; +#else + res = readData[1] & 0x80; +#endif + + logError(0, "%s flash status = %d \n", tag, res); + } + mdelay(FLASH_WAIT_BEFORE_RETRY); + } + + if (i == FLASH_RETRY_COUNT && res != 0) { + logError(1, "%s Wait for flash TIMEOUT! ERROR %08X \n", tag, + ERROR_TIMEOUT); + return ERROR_TIMEOUT; + } + + logError(0, "%s Flash READY! \n", tag); + return OK; +} + +/** + * Put the M3 in hold + * @return OK if success or an error code which specify the type of error encountered + */ +int hold_m3(void) +{ + int ret; + u8 cmd[1] = { 0x01 }; + + logError(0, "%s Command m3 hold... \n", tag); + ret = fts_writeU8UX(FTS_CMD_HW_REG_W, ADDR_SIZE_HW_REG, + ADDR_SYSTEM_RESET, cmd, 1); + if (ret < OK) { + logError(1, "%s hold_m3: ERROR %08X\n", tag, ret); + return ret; + } + logError(0, "%s Hold M3 DONE! \n", tag); + +#if !defined(I2C_INTERFACE) && defined(SPI4_WIRE) + logError(0, "%s Setting SPI4 mode... \n", tag); + cmd[0] = 0x10; + ret = fts_writeU8UX(FTS_CMD_HW_REG_W, ADDR_SIZE_HW_REG, + ADDR_GPIO_DIRECTION, cmd, 1); + if (ret < OK) { + logError(1, "%s hold_m3: can not set gpio dir ERROR %08X\n", + tag, ret); + return ret; + } + + cmd[0] = 0x02; + ret = fts_writeU8UX(FTS_CMD_HW_REG_W, ADDR_SIZE_HW_REG, + ADDR_GPIO_PULLUP, cmd, 1); + if (ret < OK) { + logError(1, "%s hold_m3: can not set gpio pull-up ERROR %08X\n", + tag, ret); + return ret; + } + + cmd[0] = 0x07; + ret = fts_writeU8UX(FTS_CMD_HW_REG_W, ADDR_SIZE_HW_REG, + ADDR_GPIO_CONFIG_REG2, cmd, 1); + if (ret < OK) { + logError(1, "%s hold_m3: can not set gpio config ERROR %08X\n", + tag, ret); + return ret; + } + + cmd[0] = 0x30; + ret = fts_writeU8UX(FTS_CMD_HW_REG_W, ADDR_SIZE_HW_REG, + ADDR_GPIO_CONFIG_REG0, cmd, 1); + if (ret < OK) { + logError(1, "%s hold_m3: can not set gpio config ERROR %08X\n", + tag, ret); + return ret; + } + + cmd[0] = SPI4_MASK; + ret = fts_writeU8UX(FTS_CMD_HW_REG_W, ADDR_SIZE_HW_REG, ADDR_ICR, cmd, + 1); + if (ret < OK) { + logError(1, "%s hold_m3: can not set spi4 mode ERROR %08X\n", + tag, ret); + return ret; + } + mdelay(1); +#endif + + return OK; +} + +/** +* Parse the raw data read from a FW file in order to fill properly the fields of a Firmware variable +* @param fw_data raw FW data loaded from system +* @param fw_size size of fw_data +* @param fwData pointer to a Firmware variable which will contain the processed data +* @param keep_cx if 1, the CX area will be loaded and burnt otherwise will be skipped and the area will be untouched +* @return OK if success or an error code which specify the type of error encountered +*/ +int parseBinFile(u8 *fw_data, int fw_size, Firmware *fwData, int keep_cx) +{ + int dimension, index = 0; + u32 temp; + int res, i; + + if (fw_size < FW_HEADER_SIZE + FW_BYTES_ALLIGN || fw_data == NULL) { + logError( + 1, + "%s parseBinFile: Read only %d instead of %d... ERROR %08X\n", + tag, fw_size, FW_HEADER_SIZE + FW_BYTES_ALLIGN, + ERROR_FILE_PARSE); + res = ERROR_FILE_PARSE; + goto END; + } else { + u8ToU32(&fw_data[index], &temp); + if (temp != FW_HEADER_SIGNATURE) { + logError( + 1, + "%s parseBinFile: Wrong Signature %08X ... ERROR %08X\n", + tag, temp, ERROR_FILE_PARSE); + res = ERROR_FILE_PARSE; + goto END; + } + logError(0, "%s parseBinFile: Fw Signature OK!\n", tag); + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + if (temp != FW_FTB_VER) { + logError( + 1, + "%s parseBinFile: Wrong ftb_version %08X ... ERROR %08X\n", + tag, temp, ERROR_FILE_PARSE); + res = ERROR_FILE_PARSE; + goto END; + } + logError(0, "%s parseBinFile: ftb_version OK!\n", tag); + index += FW_BYTES_ALLIGN; + if (fw_data[index] != DCHIP_ID_0 || + fw_data[index + 1] != DCHIP_ID_1) { + logError( + 1, + "%s parseBinFile: Wrong target %02X != %02X %02X != %02X ... ERROR %08X\n", + tag, fw_data[index], DCHIP_ID_0, + fw_data[index + 1], DCHIP_ID_1, + ERROR_FILE_PARSE); + res = ERROR_FILE_PARSE; + goto END; + } + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + logError(1, "%s parseBinFile: FILE SVN REV = %08X\n", tag, + temp); + + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + fwData->fw_ver = temp; + logError(1, "%s parseBinFile: FILE Fw Version = %04X\n", tag, + fwData->fw_ver); + + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + fwData->config_id = temp; + logError(1, "%s parseBinFile: FILE Config Project ID = %08X\n", + tag, temp); + + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + logError(1, "%s parseBinFile: FILE Config Version = %08X\n", + tag, temp); + + index += FW_BYTES_ALLIGN * 2; + + index += FW_BYTES_ALLIGN; + logError(1, "%s parseBinFile: File External Release = ", tag); + for (i = 0; i < EXTERNAL_RELEASE_INFO_SIZE; i++) { + fwData->externalRelease[i] = fw_data[index++]; + logError(1, "%02X ", fwData->externalRelease[i]); + } + logError(1, "\n"); + + u8ToU32(&fw_data[index], &temp); + fwData->sec0_size = temp; + logError(1, "%s parseBinFile: sec0_size = %08X (%d bytes)\n", + tag, fwData->sec0_size, fwData->sec0_size); + + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + fwData->sec1_size = temp; + logError(1, "%s parseBinFile: sec1_size = %08X (%d bytes)\n", + tag, fwData->sec1_size, fwData->sec1_size); + + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + fwData->sec2_size = temp; + logError(1, "%s parseBinFile: sec2_size = %08X (%d bytes) \n", + tag, fwData->sec2_size, fwData->sec2_size); + + index += FW_BYTES_ALLIGN; + u8ToU32(&fw_data[index], &temp); + fwData->sec3_size = temp; + logError(1, "%s parseBinFile: sec3_size = %08X (%d bytes) \n", + tag, fwData->sec3_size, fwData->sec3_size); + + index += FW_BYTES_ALLIGN; + + dimension = fwData->sec0_size + fwData->sec1_size + + fwData->sec2_size + fwData->sec3_size; + temp = fw_size; + + if (dimension + FW_HEADER_SIZE + FW_BYTES_ALLIGN != temp) { + logError( + 1, + "%s parseBinFile: Read only %d instead of %d... ERROR %08X\n", + tag, fw_size, + dimension + FW_HEADER_SIZE + FW_BYTES_ALLIGN, + ERROR_FILE_PARSE); + res = ERROR_FILE_PARSE; + goto END; + } + + fwData->data = + (u8 *)kmalloc(dimension * sizeof(u8), GFP_KERNEL); + if (fwData->data == NULL) { + logError(1, "%s parseBinFile: ERROR %08X\n", tag, + ERROR_ALLOC); + res = ERROR_ALLOC; + goto END; + } + + index += FW_BYTES_ALLIGN; + memcpy(fwData->data, &fw_data[index], dimension); + if (fwData->sec2_size != 0) { + u8ToU16(&fwData->data[fwData->sec0_size + + fwData->sec1_size + FW_CX_VERSION], + &fwData->cx_ver); + + } else { + logError( + 1, + "%s parseBinFile: Initialize cx_ver to default value! \n", + tag); + fwData->cx_ver = systemInfo.u16_cxVer; + } + + logError(1, "%s parseBinFile: CX Version = %04X \n", tag, + fwData->cx_ver); + + fwData->data_size = dimension; + + logError(0, "%s READ FW DONE %d bytes!\n", tag, + fwData->data_size); + res = OK; + goto END; + } + +END: + kfree(fw_data); + return res; +} + +/** + * Enable UVLO and Auto Power Down Mode + * @return OK if success or an error code which specify the type of error + */ +int flash_enable_uvlo_autopowerdown(void) +{ + u8 cmd[6] = { FTS_CMD_HW_REG_W, + 0x20, + 0x00, + 0x00, + FLASH_UVLO_ENABLE_CODE0, + FLASH_UVLO_ENABLE_CODE1 }; + u8 cmd1[6] = { FTS_CMD_HW_REG_W, + 0x20, + 0x00, + 0x00, + FLASH_AUTOPOWERDOWN_ENABLE_CODE0, + FLASH_AUTOPOWERDOWN_ENABLE_CODE1 }; + logError(0, "%s Command enable uvlo ...\n", tag); + if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + logError(1, "%s flash_enable_uvlo_autopowerdown: ERROR %08X\n", + tag, ERROR_BUS_W); + return ERROR_BUS_W; + } + if (fts_write_dma_safe(cmd1, ARRAY_SIZE(cmd1)) < OK) { + logError(1, "%s flash_enable_uvlo_autopowerdown: ERROR %08X\n", + tag, ERROR_BUS_W); + return ERROR_BUS_W; + } + logError(0, "%s Enable uvlo and flash auto power down DONE!\n", tag); + return OK; +} +/** + * Unlock the flash to be programmed + * @return OK if success or an error code which specify the type of error + */ +int flash_unlock(void) +{ + u8 cmd[6] = { FTS_CMD_HW_REG_W, 0x20, 0x00, 0x00, FLASH_UNLOCK_CODE0, + FLASH_UNLOCK_CODE1 }; + + u8 cmd1[6] = { FTS_CMD_HW_REG_W, 0x20, 0x00, 0x00, FLASH_UNLOCK_CODE2, + FLASH_UNLOCK_CODE3 }; + + logError(0, "%s Command unlock ...\n", tag); + if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + logError(1, "%s flash_unlock: ERROR %08X\n", tag, ERROR_BUS_W); + return ERROR_BUS_W; + } + + if (fts_write_dma_safe(cmd1, ARRAY_SIZE(cmd1)) < OK) { + logError(1, "%s Command unlock: ERROR %08X\n", tag, + ERROR_BUS_W); + return ERROR_BUS_W; + } + logError(0, "%s Unlock flash DONE!\n", tag); + + return OK; +} + +/** +* Unlock the flash to be erased +* @return OK if success or an error code which specify the type of error encountered +*/ +int flash_erase_unlock(void) +{ + u8 cmd[6] = { FTS_CMD_HW_REG_W, + 0x20, + 0x00, + 0x00, + FLASH_ERASE_UNLOCK_CODE0, + FLASH_ERASE_UNLOCK_CODE1 }; + + logError(0, "%s Try to erase unlock flash... \n", tag); + + logError(0, "%s Command erase unlock ... \n", tag); + if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < 0) { + logError(1, "%s flash_erase_unlock: ERROR %08X\n", tag, + ERROR_BUS_W); + return ERROR_BUS_W; + } + + logError(0, "%s Erase Unlock flash DONE! \n", tag); + + return OK; +} + +/** +* Erase the full flash +* @return OK if success or an error code which specify the type of error encountered +*/ +int flash_full_erase(void) +{ + int status; + + u8 cmd1[6] = { FTS_CMD_HW_REG_W, 0x20, 0x00, 0x00, + FLASH_ERASE_CODE0 + 1, 0x00 }; + u8 cmd[6] = { FTS_CMD_HW_REG_W, 0x20, 0x00, 0x00, FLASH_ERASE_CODE0, + FLASH_ERASE_CODE1 }; + + if (fts_write_dma_safe(cmd1, ARRAY_SIZE(cmd1)) < OK) { + logError(1, "%s flash_erase_page_by_page: ERROR %08X\n", tag, + ERROR_BUS_W); + return ERROR_BUS_W; + } + + logError(0, "%s Command full erase sent ... \n", tag); + if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + logError(1, "%s flash_full_erase: ERROR %08X\n", tag, + ERROR_BUS_W); + return ERROR_BUS_W; + } + + status = wait_for_flash_ready(FLASH_ERASE_CODE0); + + if (status != OK) { + logError(1, "%s flash_full_erase: ERROR %08X\n", tag, + ERROR_FLASH_NOT_READY); + return (status | ERROR_FLASH_NOT_READY); + } + + logError(0, "%s Full Erase flash DONE! \n", tag); + + return OK; +} + +/** +* Erase the flash page by page, giving the possibility to skip the CX area and maintain therefore its value +* @param keep_cx if SKIP_PANEL_INIT the Panel Init pages will be skipped, if > SKIP_PANEL_CX_INIT Cx and Panel Init pages otherwise all the pages will be deleted +* @return OK if success or an error code which specify the type of error encountered +*/ +int flash_erase_page_by_page(ErasePage keep_cx) +{ + u8 status, i = 0; + u8 cmd1[6] = { FTS_CMD_HW_REG_W, 0x20, 0x00, 0x00, + FLASH_ERASE_CODE0 + 1, 0x00 }; + u8 cmd[6] = { FTS_CMD_HW_REG_W, 0x20, 0x00, 0x00, + FLASH_ERASE_CODE0, 0xA0 }; + u8 cmd2[9] = { + FTS_CMD_HW_REG_W, 0x20, 0x00, 0x01, 0x28, 0xFF, 0xFF, 0xFF, 0xFF + }; + u8 mask[4] = { 0 }; + + for (i = FLASH_CX_PAGE_START; + i <= FLASH_CX_PAGE_END && keep_cx >= SKIP_PANEL_CX_INIT; i++) { + logError(0, "%s Skipping erase CX page %d! \n", tag, i); + fromIDtoMask(i, mask, 4); + } + + for (i = FLASH_PANEL_PAGE_START; + i <= FLASH_PANEL_PAGE_END && keep_cx >= SKIP_PANEL_INIT; i++) { + logError(0, "%s Skipping erase Panel Init page %d! \n", tag, i); + fromIDtoMask(i, mask, 4); + } + + logError(0, "%s Setting the page mask = ", tag, i); + for (i = 0; i < 4; i++) { + cmd2[5 + i] = cmd2[5 + i] & (~mask[i]); + logError(0, "%02X ", cmd2[5 + i]); + } + + logError(0, "\n%s Writing page mask... \n", tag); + if (fts_write_dma_safe(cmd2, ARRAY_SIZE(cmd2)) < OK) { + logError(1, + "%s flash_erase_page_by_page: Page mask ERROR %08X\n", + tag, ERROR_BUS_W); + return ERROR_BUS_W; + } + + if (fts_write_dma_safe(cmd1, ARRAY_SIZE(cmd1)) < OK) { + logError( + 1, + "%s flash_erase_page_by_page: Disable info ERROR %08X\n", + tag, ERROR_BUS_W); + return ERROR_BUS_W; + } + + logError(0, "%s Command erase pages sent ... \n", tag); + if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + logError(1, "%s flash_erase_page_by_page: Erase ERROR %08X\n", + tag, ERROR_BUS_W); + return ERROR_BUS_W; + } + + status = wait_for_flash_ready(FLASH_ERASE_CODE0); + + if (status != OK) { + logError(1, "%s flash_erase_page_by_page: ERROR % 08X\n", tag, + ERROR_FLASH_NOT_READY); + return (status | ERROR_FLASH_NOT_READY); + } + + logError(0, "%s Erase flash page by page DONE! \n", tag); + + return OK; +} + +/** +* Start the DMA procedure which actually transfer and burn the data loaded from memory into the Flash +* @return OK if success or an error code which specify the type of error encountered +*/ +int start_flash_dma(void) +{ + int status; + u8 cmd[12] = { FLASH_CMD_WRITE_REGISTER, + 0x20, + 0x00, + 0x00, + 0x6B, + 0x00, + 0x40, + 0x42, + 0x0F, + 0x00, + 0x00, + FLASH_DMA_CODE1 }; + + logError(0, "%s Command flash DMA ... \n", tag); + if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + logError(1, "%s start_flash_dma: ERROR %08X\n", tag, + ERROR_BUS_W); + return ERROR_BUS_W; + } + + status = wait_for_flash_ready(FLASH_DMA_CODE0); + + if (status != OK) { + logError(1, "%s start_flash_dma: ERROR %08X\n", tag, + ERROR_FLASH_NOT_READY); + return (status | ERROR_FLASH_NOT_READY); + } + + logError(0, "%s flash DMA DONE! \n", tag); + + return OK; +} + +/** +* Copy the FW data that should be burnt in the Flash into the memory and then the DMA will take care about burning it into the Flash +* @param address address in memory where to copy the data, possible values are FLASH_ADDR_CODE, FLASH_ADDR_CONFIG, FLASH_ADDR_CX +* @param data pointer to an array of byte which contain the data that should be copied into the memory +* @param size size of data +* @return OK if success or an error code which specify the type of error encountered +*/ +int fillFlash(u32 address, u8 *data, int size) +{ + int remaining = size, index = 0; + int toWrite = 0; + int byteBlock = 0; + int wheel = 0; + u32 addr = 0; + int res; + int delta; + u8 *buff = NULL; + u8 buff2[12] = { 0 }; + + buff = (u8 *)kmalloc((DMA_CHUNK + 5) * sizeof(u8), GFP_KERNEL); + if (buff == NULL) { + logError(1, "%s fillFlash: ERROR %08X\n", tag, ERROR_ALLOC); + return ERROR_ALLOC; + } + + while (remaining > 0) { + byteBlock = 0; + + addr = 0x00100000; + + while (byteBlock < FLASH_CHUNK && remaining > 0) { + index = 0; + if (remaining >= DMA_CHUNK) { + if ((byteBlock + DMA_CHUNK) <= FLASH_CHUNK) { + toWrite = DMA_CHUNK; + remaining -= DMA_CHUNK; + byteBlock += DMA_CHUNK; + } else { + delta = FLASH_CHUNK - byteBlock; + toWrite = delta; + remaining -= delta; + byteBlock += delta; + } + } else { + if ((byteBlock + remaining) <= FLASH_CHUNK) { + toWrite = remaining; + byteBlock += remaining; + remaining = 0; + + } else { + delta = FLASH_CHUNK - byteBlock; + toWrite = delta; + remaining -= delta; + byteBlock += delta; + } + } + + buff[index++] = FTS_CMD_HW_REG_W; + buff[index++] = (u8)((addr & 0xFF000000) >> 24); + buff[index++] = (u8)((addr & 0x00FF0000) >> 16); + buff[index++] = (u8)((addr & 0x0000FF00) >> 8); + buff[index++] = (u8)(addr & 0x000000FF); + + memcpy(&buff[index], data, toWrite); + if (fts_write_dma_safe(buff, index + toWrite) < OK) { + logError(1, "%s fillFlash: ERROR %08X\n", tag, + ERROR_BUS_W); + kfree(buff); + return ERROR_BUS_W; + } + addr += toWrite; + data += toWrite; + } + + byteBlock = byteBlock / 4 - 1; + index = 0; + + buff2[index++] = FLASH_CMD_WRITE_REGISTER; + buff2[index++] = 0x20; + buff2[index++] = 0x00; + buff2[index++] = 0x00; + buff2[index++] = FLASH_DMA_CONFIG; + buff2[index++] = 0x00; + buff2[index++] = 0x00; + + addr = address + ((wheel * FLASH_CHUNK) / 4); + buff2[index++] = (u8)((addr & 0x000000FF)); + buff2[index++] = (u8)((addr & 0x0000FF00) >> 8); + buff2[index++] = (u8)(byteBlock & 0x000000FF); + buff2[index++] = (u8)((byteBlock & 0x0000FF00) >> 8); + buff2[index++] = 0x00; + + logError( + 0, + "%s DMA Command = %02X , address = %02X %02X, words = %02X %02X \n", + tag, buff2[0], buff2[8], buff2[7], buff2[10], buff2[9]); + + if (fts_write_dma_safe(buff2, index) < OK) { + logError( + 1, + "%s Error during filling Flash! ERROR %08X \n", + tag, ERROR_BUS_W); + kfree(buff); + return ERROR_BUS_W; + } + + res = start_flash_dma(); + if (res < OK) { + logError( + 1, + "%s Error during flashing DMA! ERROR %08X \n", + tag, res); + kfree(buff); + return res; + } + wheel++; + } + kfree(buff); + return OK; +} + +/** +* Execute the procedure to burn a FW in FTM4/FTI IC +* @param fw structure which contain the FW to be burnt +* @param force_burn if >0, the flashing procedure will be forced and executed regardless the additional info, otherwise the FW in the file will be burnt only if it is newer than the one running in the IC +* @param keep_cx if 1, the function preserve the CX/Panel Init area otherwise will be cleared +* @return OK if success or an error code which specify the type of error encountered +*/ +int flash_burn(Firmware fw, int force_burn, int keep_cx) +{ + int res; + + if (!force_burn) { + if (systemInfo.u16_fwVer != fw.fw_ver) + goto start; + for (res = EXTERNAL_RELEASE_INFO_SIZE - 1; res >= 0; res--) { + if (fw.externalRelease[res] != + systemInfo.u8_releaseInfo[res]) + goto start; + } + logError( + 1, + "%s flash_burn: Firmware in the chip newer or equal to the one to burn! NO UPDATE ERROR %08X \n", + tag, ERROR_FW_NO_UPDATE); + return (ERROR_FW_NO_UPDATE | ERROR_FLASH_BURN_FAILED); + } else { + if (force_burn == CRC_CX && fw.sec2_size == 0) { + for (res = EXTERNAL_RELEASE_INFO_SIZE - 1; res >= 0; + res--) { + if (fw.externalRelease[res] > + systemInfo.u8_releaseInfo[res]) + force_burn = 0; + goto start; + } + logError( + 1, + "%s flash_burn: CRC in CX but fw does not contain CX data! NO UPDATE ERROR %08X \n", + tag, ERROR_FW_NO_UPDATE); + return (ERROR_FW_NO_UPDATE | ERROR_FLASH_BURN_FAILED); + } + } + +start: + logError(0, "%s Programming Procedure for flashing started: \n\n", tag); + + logError(0, "%s 1) SYSTEM RESET: \n", tag); + res = fts_system_reset(); + if (res < 0) { + logError(1, "%s system reset FAILED!\n", tag); + if (res != (ERROR_SYSTEM_RESET_FAIL | ERROR_TIMEOUT)) + return (res | ERROR_FLASH_BURN_FAILED); + } else + logError(0, "%s system reset COMPLETED!\n\n", tag); + msleep(30); /* required by hw during flash procedure */ + logError(0, "%s 2) HOLD M3 : \n", tag); + res = hold_m3(); + if (res < OK) { + logError(1, "%s hold_m3 FAILED!\n", tag); + return (res | ERROR_FLASH_BURN_FAILED); + } else + logError(0, "%s hold_m3 COMPLETED!\n\n", tag); + + logError(0, "%s 3) ENABLE UVLO AND AUTO POWER DOWN MODE :\n", tag); + res = flash_enable_uvlo_autopowerdown(); + if (res < OK) { + logError(1, "%s flash_enable_uvlo_autopowerdown FAILED!\n", + tag); + return res | ERROR_FLASH_BURN_FAILED; + } else + logError(0, + "%s flash_enable_uvlo_autopowerdown COMPLETED!\n\n", + tag); + logError(0, "%s 4) FLASH UNLOCK: \n", tag); + res = flash_unlock(); + if (res < OK) { + logError(1, "%s flash unlock FAILED! ERROR %08X\n", tag, + ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } else { + logError(0, "%s flash unlock COMPLETED!\n\n", tag); + } + + logError(0, "%s 5) FLASH ERASE UNLOCK: \n", tag); + res = flash_erase_unlock(); + if (res < 0) { + logError(1, "%s flash unlock FAILED! ERROR %08X\n", tag, + ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } else { + logError(0, "%s flash unlock COMPLETED!\n\n", tag); + } + + logError(0, "%s 6) FLASH ERASE: \n", tag); + if (keep_cx > 0) { + if (fw.sec2_size != 0 && force_burn == CRC_CX) + res = flash_erase_page_by_page(SKIP_PANEL_INIT); + else + res = flash_erase_page_by_page(SKIP_PANEL_CX_INIT); + } else { + res = flash_erase_page_by_page(SKIP_PANEL_INIT); + if (fw.sec2_size == 0) + logError( + 1, + "%s WARNING!!! Erasing CX memory but no CX in fw file! touch will not work right after fw update! \n", + tag); + } + + if (res < OK) { + logError(1, "%s flash erase FAILED! ERROR %08X\n", tag, + ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } else { + logError(0, "%s flash erase COMPLETED!\n\n", tag); + } + + logError(0, "%s 7) LOAD PROGRAM: \n", tag); + res = fillFlash(FLASH_ADDR_CODE, &fw.data[0], fw.sec0_size); + if (res < OK) { + logError(1, "%s load program ERROR %08X\n", tag, + ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } + logError(1, "%s load program DONE!\n", tag); + + logError(0, "%s 8) LOAD CONFIG: \n", tag); + res = fillFlash(FLASH_ADDR_CONFIG, &(fw.data[fw.sec0_size]), + fw.sec1_size); + if (res < OK) { + logError(1, "%s load config ERROR %08X\n", tag, + ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } + logError(1, "%s load config DONE!\n", tag); + + if (fw.sec2_size != 0) { + if ((force_burn == CRC_CX) || (keep_cx <= 0)) { + logError(0, "%s 8.1) LOAD CX: \n", tag); + res = fillFlash(FLASH_ADDR_CX, + &(fw.data[fw.sec0_size + fw.sec1_size]), + fw.sec2_size); + if (res < OK) { + logError(1, "%s load cx ERROR %08X\n", tag, + ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } + logError(1, "%s load cx DONE!\n", tag); + } + } + + logError(0, "%s Flash burn COMPLETED!\n\n", tag); + + logError(0, "%s 9) SYSTEM RESET: \n", tag); + res = fts_system_reset(); + if (res < 0) { + logError(1, "%s system reset FAILED! ERROR %08X\n", tag, + ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } + logError(0, "%s system reset COMPLETED!\n\n", tag); + + logError(0, "%s 10) FINAL CHECK: \n", tag); + res = readSysInfo(0); + if (res < 0) { + logError( + 1, + "%s flash_burn: Unable to retrieve Chip INFO! ERROR %08X\n", + tag, ERROR_FLASH_BURN_FAILED); + return (res | ERROR_FLASH_BURN_FAILED); + } + + for (res = 0; res < EXTERNAL_RELEASE_INFO_SIZE; res++) { + if (fw.externalRelease[res] != systemInfo.u8_releaseInfo[res]) { + logError( + 1, + "%s Firmware in the chip different from the one that was burn! \n", + tag); + return ERROR_FLASH_BURN_FAILED; + } + } + + logError(0, "%s Final check OK! \n", tag); + + return OK; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.h new file mode 100644 index 000000000000..30742af22080 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFlash.h @@ -0,0 +1,106 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS API for Flashing the IC * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsFlash.h +* \brief Contains all the definitions and structs to handle the FW update process +*/ + +#ifndef FTS_FLASH_H +#define FTS_FLASH_H + +#include "ftsSoftware.h" + +/*Flash possible status*/ +#define FLASH_READY 0 /*value to indicate that the flash is ready*/ +#define FLASH_BUSY 1 /*value to indicate that the flash is busy*/ +#define FLASH_UNKNOWN -1 /*value to indicate an unknown status of the flash*/ + +#define FLASH_STATUS_BYTES \ + 1 /*number of bytes to check for read the flash status*/ + +/*Flash timing parameters*/ +#define FLASH_RETRY_COUNT 200 /*number of attemps to read the flash status*/ +#define FLASH_WAIT_BEFORE_RETRY \ + 50 /*time to wait in ms between one status reading and another*/ + +#ifdef FW_H_FILE +#define PATH_FILE_FW "NULL" +#else +#define PATH_FILE_FW "st_fts.ftb" /*new FW bin file name*/ +#endif + +#define FLASH_CHUNK \ + (64 * \ + 1024) /*Max number of bytes that the DMA can burn on the flash in one shot in FTI*/ +#define DMA_CHUNK \ + 32 /*Max number of bytes that can be written in I2C to the DMA*/ + +/** + * Define which kind of erase page by page should be performed + */ +typedef enum { + ERASE_ALL = 0, /*erase all the pages*/ + SKIP_PANEL_INIT = 1, /*skip erase Panel Init Pages*/ + SKIP_PANEL_CX_INIT = 2 /*skip erase Panel Init and CX Pages*/ +} ErasePage; + +/** @addtogroup fw_file + * @{ + */ + +/** +* Struct which contains information and data of the FW that should be burnt into the IC +*/ +typedef struct { + u8 *data; /*pointer to an array of bytes which represent the FW data*/ + u16 fw_ver; /*FW version of the FW file*/ + u16 config_id; /*Config ID of the FW file*/ + u16 cx_ver; /*Cx version of the FW file*/ + u8 externalRelease + [EXTERNAL_RELEASE_INFO_SIZE]; /*External Release Info of the FW file*/ + int data_size; /*dimension of data (the actual data to be burnt)*/ + u32 sec0_size; /*dimension of section 0 (FW) in .ftb file*/ + u32 sec1_size; /*dimension of section 1 (Config) in .ftb file*/ + u32 sec2_size; /*dimension of section 2 (Cx) in .ftb file*/ + u32 sec3_size; /*dimension of section 3 (TBD) in .ftb file*/ + +} Firmware; + +/** @}*/ + +/** @addtogroup flash_command + * @{ + */ + +int wait_for_flash_ready(u8 type); +int hold_m3(void); +int flash_erase_unlock(void); +int flash_full_erase(void); +int flash_erase_page_by_page(ErasePage keep_cx); +int start_flash_dma(void); +int fillFlash(u32 address, u8 *data, int size); + +int flash_unlock(void); +int getFirmwareVersion(u16 *fw_vers, u16 *config_id); +int getFWdata(const char *pathToFile, u8 **data, int *size); +int parseBinFile(u8 *fw_data, int fw_size, Firmware *fw, int keep_cx); +int readFwFile(const char *path, Firmware *fw, int keep_cx); +int flash_burn(Firmware fw, int force_burn, int keep_cx); +int flashProcedure(const char *path, int force, int keep_cx); +int flash_enable_uvlo_autopowerdown(void); +#endif + +/** @}*/ diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.c new file mode 100644 index 000000000000..b9ec5a42b058 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.c @@ -0,0 +1,395 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS functions for getting frames * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsFrame.c +* \brief Contains all the functions to work with frames +*/ + +#include "ftsCompensation.h" +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsFrame.h" +#include "ftsHardware.h" +#include "ftsIO.h" +#include "ftsSoftware.h" +#include "ftsTool.h" +#include "ftsTime.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern SysInfo systemInfo; + +/** + * Read the channels lengths from the config memory + * @return OK if success or an error code which specify the type of error encountered + */ +int getChannelsLength(void) +{ + int ret; + u8 data[2]; + + if (data == NULL) { + logError(1, "%s getChannelsLength: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + ret = readConfig(ADDR_CONFIG_SENSE_LEN, data, 2); + if (ret < OK) { + logError(1, "%s getChannelsLength: ERROR %08X\n", tag, ret); + + return ret; + } + + systemInfo.u8_scrRxLen = (int)data[0]; + systemInfo.u8_scrTxLen = (int)data[1]; + + logError(0, "%s Force_len = %d Sense_Len = %d \n", tag, + systemInfo.u8_scrTxLen, systemInfo.u8_scrRxLen); + + return OK; +} + +/** +* Read and pack the frame data related to the nodes +* @param address address in memory when the frame data node start +* @param size amount of data to read +* @param frame pointer to an array of bytes which will contain the frame node data +* @return OK if success or an error code which specify the type of error encountered +*/ +int getFrameData(u16 address, int size, short *frame) +{ + int i, j, ret; + u8 *data = (u8 *)kmalloc(size * sizeof(u8), GFP_KERNEL); + if (data == NULL) { + logError(1, "%s getFrameData: ERROR %08X\n", tag, ERROR_ALLOC); + return ERROR_ALLOC; + } + + ret = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, address, data, + size, DUMMY_FRAMEBUFFER); + if (ret < OK) { + logError(1, "%s getFrameData: ERROR %08X\n", tag, ERROR_BUS_R); + kfree(data); + return ERROR_BUS_R; + } + j = 0; + for (i = 0; i < size; i += 2) { + frame[j] = (short)((data[i + 1] << 8) + data[i]); + j++; + } + kfree(data); + return OK; +} + +/** + * Return the number of Sense Channels (Rx) + * @return number of Rx channels + */ +int getSenseLen(void) +{ + if (systemInfo.u8_scrRxLen == 0) { + getChannelsLength(); + } + return systemInfo.u8_scrRxLen; +} + +/** + * Return the number of Force Channels (Tx) + * @return number of Tx channels + */ +int getForceLen(void) +{ + if (systemInfo.u8_scrTxLen == 0) { + getChannelsLength(); + } + return systemInfo.u8_scrTxLen; +} + +/******************** New API **************************/ + +/** +* Read a MS Frame from frame buffer memory +* @param type type of MS frame to read +* @param frame pointer to MutualSenseFrame variable which will contain the data +* @return OK if success or an error code which specify the type of error encountered +*/ +int getMSFrame3(MSFrameType type, MutualSenseFrame *frame) +{ + u16 offset; + int ret, force_len, sense_len; + + force_len = getForceLen(); + sense_len = getSenseLen(); + + frame->node_data = NULL; + + logError(0, "%s %s: Starting to get frame %02X \n", tag, __func__, + type); + switch (type) { + case MS_RAW: + offset = systemInfo.u16_msTchRawAddr; + goto LOAD_NORM; + case MS_FILTER: + offset = systemInfo.u16_msTchFilterAddr; + + goto LOAD_NORM; + case MS_STRENGTH: + offset = systemInfo.u16_msTchStrenAddr; + goto LOAD_NORM; + case MS_BASELINE: + offset = systemInfo.u16_msTchBaselineAddr; +LOAD_NORM: + if (force_len == 0 || sense_len == 0) { + logError( + 1, + "%s %s: number of channels not initialized ERROR %08X\n", + tag, __func__, ERROR_CH_LEN); + return (ERROR_CH_LEN | ERROR_GET_FRAME); + } + + break; + + case MS_KEY_RAW: + offset = systemInfo.u16_keyRawAddr; + goto LOAD_KEY; + case MS_KEY_FILTER: + offset = systemInfo.u16_keyFilterAddr; + goto LOAD_KEY; + case MS_KEY_STRENGTH: + offset = systemInfo.u16_keyStrenAddr; + goto LOAD_KEY; + case MS_KEY_BASELINE: + offset = systemInfo.u16_keyBaselineAddr; +LOAD_KEY: + if (systemInfo.u8_keyLen == 0) { + logError( + 1, + "%s %s: number of channels not initialized ERROR %08X\n", + tag, __func__, ERROR_CH_LEN); + return (ERROR_CH_LEN | ERROR_GET_FRAME); + } + force_len = 1; + sense_len = systemInfo.u8_keyLen; + break; + + case FRC_RAW: + offset = systemInfo.u16_frcRawAddr; + goto LOAD_FRC; + case FRC_FILTER: + offset = systemInfo.u16_frcFilterAddr; + goto LOAD_FRC; + case FRC_STRENGTH: + offset = systemInfo.u16_frcStrenAddr; + goto LOAD_FRC; + case FRC_BASELINE: + offset = systemInfo.u16_frcBaselineAddr; +LOAD_FRC: + if (force_len == 0) { + logError( + 1, + "%s %s: number of channels not initialized ERROR %08X\n", + tag, __func__, ERROR_CH_LEN); + return (ERROR_CH_LEN | ERROR_GET_FRAME); + } + sense_len = 1; + break; + default: + logError(1, "%s %s: Invalid type ERROR %08X\n", tag, __func__, + ERROR_OP_NOT_ALLOW | ERROR_GET_FRAME); + return ERROR_OP_NOT_ALLOW | ERROR_GET_FRAME; + } + + frame->node_data_size = ((force_len)*sense_len); + frame->header.force_node = force_len; + frame->header.sense_node = sense_len; + frame->header.type = type; + + logError(0, "%s %s: Force_len = %d Sense_len = %d Offset = %04X \n", + tag, __func__, force_len, sense_len, offset); + + frame->node_data = (short *)kmalloc( + frame->node_data_size * sizeof(short), GFP_KERNEL); + if (frame->node_data == NULL) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_ALLOC | ERROR_GET_FRAME); + return ERROR_ALLOC | ERROR_GET_FRAME; + } + + ret = getFrameData(offset, frame->node_data_size * BYTES_PER_NODE, + (frame->node_data)); + if (ret < OK) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, + ERROR_GET_FRAME_DATA); + kfree(frame->node_data); + frame->node_data = NULL; + return (ret | ERROR_GET_FRAME_DATA | ERROR_GET_FRAME); + } + logError(0, "%s Frame acquired! \n", tag); + return frame->node_data_size; +} + +/** +* Read a SS Frame from frame buffer +* @param type type of SS frame to read +* @param frame pointer to SelfSenseFrame variable which will contain the data +* @return OK if success or an error code which specify the type of error encountered +*/ +int getSSFrame3(SSFrameType type, SelfSenseFrame *frame) +{ + u16 offset_force, offset_sense; + int ret; + + frame->force_data = NULL; + frame->sense_data = NULL; + + frame->header.force_node = getForceLen(); + frame->header.sense_node = getSenseLen(); + + if (frame->header.force_node == 0 || frame->header.sense_node == 0) { + logError( + 1, + "%s %s: number of channels not initialized ERROR %08X\n", + tag, __func__, ERROR_CH_LEN); + return (ERROR_CH_LEN | ERROR_GET_FRAME); + } + + logError(0, "%s %s: Starting to get frame %02X \n", tag, __func__, + type); + switch (type) { + case SS_RAW: + offset_force = systemInfo.u16_ssTchTxRawAddr; + offset_sense = systemInfo.u16_ssTchRxRawAddr; + break; + case SS_FILTER: + offset_force = systemInfo.u16_ssTchTxFilterAddr; + offset_sense = systemInfo.u16_ssTchRxFilterAddr; + break; + case SS_STRENGTH: + offset_force = systemInfo.u16_ssTchTxStrenAddr; + offset_sense = systemInfo.u16_ssTchRxStrenAddr; + break; + case SS_BASELINE: + offset_force = systemInfo.u16_ssTchTxBaselineAddr; + offset_sense = systemInfo.u16_ssTchRxBaselineAddr; + break; + + case SS_HVR_RAW: + offset_force = systemInfo.u16_ssHvrTxRawAddr; + offset_sense = systemInfo.u16_ssHvrRxRawAddr; + break; + case SS_HVR_FILTER: + offset_force = systemInfo.u16_ssHvrTxFilterAddr; + offset_sense = systemInfo.u16_ssHvrRxFilterAddr; + break; + case SS_HVR_STRENGTH: + offset_force = systemInfo.u16_ssHvrTxStrenAddr; + offset_sense = systemInfo.u16_ssHvrRxStrenAddr; + break; + case SS_HVR_BASELINE: + offset_force = systemInfo.u16_ssHvrTxBaselineAddr; + offset_sense = systemInfo.u16_ssHvrRxBaselineAddr; + break; + + case SS_PRX_RAW: + offset_force = systemInfo.u16_ssPrxTxRawAddr; + offset_sense = systemInfo.u16_ssPrxRxRawAddr; + break; + case SS_PRX_FILTER: + offset_force = systemInfo.u16_ssPrxTxFilterAddr; + offset_sense = systemInfo.u16_ssPrxRxFilterAddr; + break; + case SS_PRX_STRENGTH: + offset_force = systemInfo.u16_ssPrxTxStrenAddr; + offset_sense = systemInfo.u16_ssPrxRxStrenAddr; + break; + case SS_PRX_BASELINE: + offset_force = systemInfo.u16_ssPrxTxBaselineAddr; + offset_sense = systemInfo.u16_ssPrxRxBaselineAddr; + break; + + default: + logError(1, "%s %s: Invalid type ERROR %08X\n", tag, __func__, + ERROR_OP_NOT_ALLOW | ERROR_GET_FRAME); + return ERROR_OP_NOT_ALLOW | ERROR_GET_FRAME; + } + + frame->header.type = type; + + logError( + 0, + "%s %s: Force_len = %d Sense_len = %d Offset_force = %04X Offset_sense = %04X \n", + tag, __func__, frame->header.force_node, + frame->header.sense_node, offset_force, offset_sense); + + frame->force_data = (short *)kmalloc( + frame->header.force_node * sizeof(short), GFP_KERNEL); + if (frame->force_data == NULL) { + logError(1, "%s %s: can not allocate force_data ERROR %08X\n", + tag, __func__, ERROR_ALLOC | ERROR_GET_FRAME); + return ERROR_ALLOC | ERROR_GET_FRAME; + } + + frame->sense_data = (short *)kmalloc( + frame->header.sense_node * sizeof(short), GFP_KERNEL); + if (frame->sense_data == NULL) { + kfree(frame->force_data); + frame->force_data = NULL; + logError(1, "%s %s: can not allocate sense_data ERROR %08X\n", + tag, __func__, ERROR_ALLOC | ERROR_GET_FRAME); + return ERROR_ALLOC | ERROR_GET_FRAME; + } + + ret = getFrameData(offset_force, + frame->header.force_node * BYTES_PER_NODE, + (frame->force_data)); + if (ret < OK) { + logError(1, + "%s %s: error while reading force data ERROR %08X\n", + tag, __func__, ERROR_GET_FRAME_DATA); + kfree(frame->force_data); + frame->force_data = NULL; + kfree(frame->sense_data); + frame->sense_data = NULL; + return (ret | ERROR_GET_FRAME_DATA | ERROR_GET_FRAME); + } + + ret = getFrameData(offset_sense, + frame->header.sense_node * BYTES_PER_NODE, + (frame->sense_data)); + if (ret < OK) { + logError(1, + "%s %s: error while reading sense data ERROR %08X\n", + tag, __func__, ERROR_GET_FRAME_DATA); + kfree(frame->force_data); + frame->force_data = NULL; + kfree(frame->sense_data); + frame->sense_data = NULL; + return (ret | ERROR_GET_FRAME_DATA | ERROR_GET_FRAME); + } + + logError(0, "%s Frame acquired! \n", tag); + return frame->header.force_node + frame->header.sense_node; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.h new file mode 100644 index 000000000000..bade71c39e67 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsFrame.h @@ -0,0 +1,92 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS functions for getting frames * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsFrame.h +* \brief Contains all the definitions and structs to work with frames +*/ + +#ifndef FTS_FRAME_H +#define FTS_FRAME_H + +#include "ftsSoftware.h" + +/*Number of data bytes for each node */ +#define BYTES_PER_NODE 2 /*number of data bytes for each node*/ + +#define RETRY_FRAME_DATA_READ 2 /*max number of attempts to read a frame*/ + +/** +* Possible types of MS frames +*/ +typedef enum { + MS_RAW = 0, /*Mutual Sense Raw Frame*/ + MS_FILTER = 1, /*Mutual Sense Filtered Frame*/ + MS_STRENGTH = 2, /*Mutual Sense Strength Frame (Baseline-Raw)*/ + MS_BASELINE = 3, /*Mutual Sense Baseline Frame*/ + MS_KEY_RAW = 4, /*Mutual Sense Key Raw Frame*/ + MS_KEY_FILTER = 5, /*Mutual Sense Key Filter Frame*/ + MS_KEY_STRENGTH = 6, /*Mutual Sense Key Strength Frame (Baseline-Raw)*/ + MS_KEY_BASELINE = 7, /*Mutual Sense Key Baseline Frame*/ + FRC_RAW = 8, /*Force Raw Frame*/ + FRC_FILTER = 9, /*Force Filtered Frame*/ + FRC_STRENGTH = 10, /*Force Strength Frame (Baseline-Raw)*/ + FRC_BASELINE = 11 /*Force Baseline Frame*/ +} MSFrameType; + +/** +* Possible types of SS frames +*/ +typedef enum { + SS_RAW = 0, /*Self Sense Raw Frame*/ + SS_FILTER = 1, /*Self Sense Filtered Frame*/ + SS_STRENGTH = 2, /*Self Sense Strength Frame (Baseline-Raw)*/ + SS_BASELINE = 3, /*Self Sense Baseline Frame*/ + SS_HVR_RAW = 4, /*Self Sense Hover Raw Frame*/ + SS_HVR_FILTER = 5, /*Self Sense Hover Filter Frame*/ + SS_HVR_STRENGTH = 6, /*Self Sense Hover Strength Frame (Baseline-Raw)*/ + SS_HVR_BASELINE = 7, /*Self Sense Hover Baseline Frame*/ + SS_PRX_RAW = 8, /*Self Sense Proximity Raw Frame*/ + SS_PRX_FILTER = 9, /*Self Sense Proximity Filtered Frame*/ + SS_PRX_STRENGTH = + 10, /*Self Sense Proximity Strength Frame (Baseline-Raw)*/ + SS_PRX_BASELINE = 11 /*Self Sense Proximity Baseline Frame*/ +} SSFrameType; + +/** +* Struct which contains the data of a MS Frame +*/ +typedef struct { + DataHeader header; /*Header which contain basic info of the frame*/ + short *node_data; /*Data of the frame*/ + int node_data_size; /*Dimension of the data of the frame*/ +} MutualSenseFrame; + +/** +* Struct which contains the data of a SS Frame +*/ +typedef struct { + DataHeader header; /*Header which contain basic info of the frame*/ + short *force_data; /*Force Channels Data*/ + short *sense_data; /*Sense Channels Data*/ +} SelfSenseFrame; + +int getChannelsLength(void); +int getFrameData(u16 address, int size, short *frame); +int getSenseLen(void); +int getForceLen(void); +int getMSFrame3(MSFrameType type, MutualSenseFrame *frame); +int getSSFrame3(SSFrameType type, SelfSenseFrame *frame); +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.c new file mode 100644 index 000000000000..32457f9a427a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.c @@ -0,0 +1,363 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS Gesture Utilities * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsGesture.c +* \brief Contains all the functions and variable to handle the Gesture Detection features +*/ + +#include "ftsSoftware.h" +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsGesture.h" +#include "ftsIO.h" +#include "ftsTime.h" +#include "ftsTool.h" + +static u8 gesture_mask[GESTURE_MASK_SIZE] = { 0 }; +u16 gesture_coordinates_x[GESTURE_MAX_COORDS_PAIRS_REPORT] = { 0 }; +u16 gesture_coordinates_y[GESTURE_MAX_COORDS_PAIRS_REPORT] = { 0 }; +int gesture_coords_reported = ERROR_OP_NOT_ALLOW; +static u8 refreshGestureMask; +struct mutex gestureMask_mutex; + +/** + * Update the gesture mask stored in the driver and have to be used in gesture mode + * @param mask pointer to a byte array which store the gesture mask update that want to be performed. + * @param size dimension in byte of mask. This size can be <= GESTURE_MASK_SIZE. If size < GESTURE_MASK_SIZE the bytes of mask are considering continuos and starting from the less significant byte. + * @param en 0 = enable the gestures set in mask, 1 = disable the gestures set in mask + * @return OK if success or an error code which specify the type of error encountered + */ +int updateGestureMask(u8 *mask, int size, int en) +{ + u8 temp; + int i; + + if (mask != NULL) { + if (size <= GESTURE_MASK_SIZE) { + if (en == FEAT_ENABLE) { + mutex_lock(&gestureMask_mutex); + logError( + 0, + "%s updateGestureMask: setting gesture mask to enable...\n", + tag); + if (mask != NULL) { + for (i = 0; i < size; i++) { + gesture_mask[i] = + gesture_mask[i] | + mask[i]; + } + } + refreshGestureMask = 1; + logError( + 0, + "%s updateGestureMask: gesture mask to enable SET! \n", + tag); + mutex_unlock(&gestureMask_mutex); + return OK; + } + + else if (en == FEAT_DISABLE) { + mutex_lock(&gestureMask_mutex); + logError( + 0, + "%s updateGestureMask: setting gesture mask to disable...\n", + tag); + for (i = 0; i < size; i++) { + temp = gesture_mask[i] ^ mask[i]; + gesture_mask[i] = temp & + gesture_mask[i]; + } + logError( + 0, + "%s updateGestureMask: gesture mask to disable SET! \n", + tag); + refreshGestureMask = 1; + mutex_unlock(&gestureMask_mutex); + return OK; + } else { + logError( + 1, + "updateGestureMask: Enable parameter Invalid! %d != %d or %d ERROR %08X", + tag, FEAT_DISABLE, FEAT_ENABLE, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + } else { + logError( + 1, + "%s updateGestureMask: Size not valid! %d > %d ERROR %08X \n", + tag, size, GESTURE_MASK_SIZE); + return ERROR_OP_NOT_ALLOW; + } + } else { + logError(1, "%s updateGestureMask: Mask NULL! ERROR %08X \n", + tag, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +/** + * Enable in the FW the gesture mask to be used in gesture mode + * @param mask pointer to a byte array which store the gesture mask update that want to be sent to the FW, if NULL, will be used gesture_mask set previously without any changes. + * @param size dimension in byte of mask. This size can be <= GESTURE_MASK_SIZE. If size < GESTURE_MASK_SIZE the bytes of mask are considering continuos and starting from the less significant byte. + * @return OK if success or an error code which specify the type of error encountered + */ +int enableGesture(u8 *mask, int size) +{ + int i, res; + + logError(0, "%s Trying to enable gesture... \n", tag); + + if (size <= GESTURE_MASK_SIZE) { + mutex_lock(&gestureMask_mutex); + if (mask != NULL) { + for (i = 0; i < size; i++) { + gesture_mask[i] = gesture_mask[i] | mask[i]; + } + } + + res = setFeatures(FEAT_SEL_GESTURE, gesture_mask, + GESTURE_MASK_SIZE); + if (res < OK) { + logError(1, "%s enableGesture: ERROR %08X \n", tag, + res); + goto END; + } + + logError(0, "%s enableGesture DONE! \n", tag); + res = OK; + +END: + mutex_unlock(&gestureMask_mutex); + return res; + } else { + logError( + 1, + "%s enableGesture: Size not valid! %d > %d ERROR %08X \n", + tag, size, GESTURE_MASK_SIZE); + return ERROR_OP_NOT_ALLOW; + } +} + +/** + * Disable in the FW the gesture mask to be used in gesture mode + * @param mask pointer to a byte array which store the gesture mask update that want to be sent to the FW, if NULL, all the gestures will be disabled. + * @param size dimension in byte of mask. This size can be <= GESTURE_MASK_SIZE. If size < GESTURE_MASK_SIZE the bytes of mask are considering continuos and starting from the less significant byte. + * @return OK if success or an error code which specify the type of error encountered + */ +int disableGesture(u8 *mask, int size) +{ + u8 temp; + int i, res; + u8 *pointer; + + logError(0, "%s Trying to disable gesture... \n", tag); + + if (size <= GESTURE_MASK_SIZE) { + mutex_lock(&gestureMask_mutex); + if (mask != NULL) { + for (i = 0; i < size; i++) { + temp = gesture_mask[i] ^ mask[i]; + gesture_mask[i] = temp & gesture_mask[i]; + } + + pointer = gesture_mask; + } else { + i = 0; + pointer = (u8 *)&i; + } + + res = setFeatures(FEAT_SEL_GESTURE, pointer, GESTURE_MASK_SIZE); + if (res < OK) { + logError(1, "%s disableGesture: ERROR %08X \n", tag, + res); + goto END; + } + + logError(0, "%s disableGesture DONE! \n", tag); + + res = OK; + +END: + mutex_unlock(&gestureMask_mutex); + return res; + } else { + logError( + 1, + "%s disableGesture: Size not valid! %d > %d ERROR %08X \n", + tag, size, GESTURE_MASK_SIZE); + return ERROR_OP_NOT_ALLOW; + } +} + +/** + * Perform all the steps required to put the chip in gesture mode + * @param reload if set to 1, before entering in gesture mode it will re-enable in the FW the last defined gesture mask + * @return OK if success or an error code which specify the type of error encountered + */ +int enterGestureMode(int reload) +{ + int res, ret; + + res = fts_disableInterruptNoSync(); + if (res < OK) { + logError(1, "%s enterGestureMode: ERROR %08X \n", tag, + res | ERROR_DISABLE_INTER); + return res | ERROR_DISABLE_INTER; + } + + if (reload == 1 || refreshGestureMask == 1) { + res = enableGesture(NULL, 0); + if (res < OK) { + logError( + 1, + "%s enterGestureMode: enableGesture ERROR %08X \n", + tag, res); + goto END; + } + + refreshGestureMask = 0; + } + + res = setScanMode(SCAN_MODE_LOW_POWER, 0); + if (res < OK) { + logError( + 1, + "%s enterGestureMode: enter gesture mode ERROR %08X \n", + tag, res); + goto END; + } + + res = OK; +END: + ret = fts_enableInterrupt(); + if (ret < OK) { + logError( + 1, + "%s enterGestureMode: fts_enableInterrupt ERROR %08X \n", + tag, res | ERROR_ENABLE_INTER); + res |= ret | ERROR_ENABLE_INTER; + } + + return res; +} + +/** + * Check if one or more Gesture IDs are currently enabled in gesture_mask + * @return FEAT_ENABLE if one or more gesture ids are enabled, FEAT_DISABLE if all the gesture ids are currently disabled + */ +int isAnyGestureActive(void) +{ + int res = 0; + + while (res < (GESTURE_MASK_SIZE - 1) && gesture_mask[res] == 0) { + res++; + } + + if (gesture_mask[res] != 0) { + logError( + 0, + "%s %s: Active Gestures Found! gesture_mask[%d] = %02X !\n", + tag, __func__, res, gesture_mask[res]); + return FEAT_ENABLE; + } else { + logError(0, "%s %s: All Gestures Disabled!\n", tag, __func__); + return FEAT_DISABLE; + } +} + +/** + * Read from the frame buffer the gesture coordinates pairs of the points draw by an user when a gesture is detected + * @param event pointer to a byte array which contains the gesture event reported by the fw when a gesture is detected + * @return OK if success or an error code which specify the type of error encountered + */ +int readGestureCoords(u8 *event) +{ + int i = 0; + u64 address = 0; + int res; + + u8 val[GESTURE_MAX_COORDS_PAIRS_REPORT * 4]; + + if (event[0] == EVT_ID_USER_REPORT && + event[1] == EVT_TYPE_USER_GESTURE) { + address = (event[4] << 8) | event[3]; + gesture_coords_reported = event[5]; + if (gesture_coords_reported > GESTURE_MAX_COORDS_PAIRS_REPORT) { + logError( + 1, + "%s %s: FW reported more than %d points for the gestures! Decreasing to %d \n", + tag, __func__, gesture_coords_reported, + GESTURE_MAX_COORDS_PAIRS_REPORT); + gesture_coords_reported = + GESTURE_MAX_COORDS_PAIRS_REPORT; + } + + logError(1, "%s %s: Offset: %08X , coords pairs = %d\n", tag, + __func__, address, gesture_coords_reported); + + res = fts_writeReadU8UX(FTS_CMD_FRAMEBUFFER_R, BITS_16, address, + val, (gesture_coords_reported * 2 * 2), + DUMMY_FRAMEBUFFER); + if (res < OK) { + logError( + 1, + "%s %s: Cannot read the coordinates! ERROR %08X \n", + tag, __func__, res); + gesture_coords_reported = ERROR_OP_NOT_ALLOW; + return res; + } + + for (i = 0; i < gesture_coords_reported; i++) { + gesture_coordinates_x[i] = + (((u16)val[i * 2 + 1]) & 0x0F) << 8 | + (((u16)val[i * 2]) & 0xFF); + gesture_coordinates_y[i] = + (((u16)val[gesture_coords_reported * 2 + i * 2 + + 1]) & + 0x0F) << 8 | + (((u16)val[gesture_coords_reported * 2 + i * 2]) & + 0xFF); + } + + logError(1, "%s %s: Reading Gesture Coordinates DONE! \n", tag, + __func__); + return OK; + + } else { + logError( + 1, + "%s %s: The event passsed as argument is invalid! ERROR %08X \n", + tag, __func__, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +/** + * Return the coordinates of the points stored during the last detected gesture + * @param x output parameter which will store the address of the array containing the x coordinates + * @param y output parameter which will store the address of the array containing the y coordinates + * @return the number of points (x,y) stored and therefore the size of the x and y array returned. + */ +int getGestureCoords(u16 **x, u16 **y) +{ + *x = gesture_coordinates_x; + *y = gesture_coordinates_y; + logError(1, + "%s %s: Number of gesture coordinates pairs returned = %d \n", + tag, __func__, gesture_coords_reported); + return gesture_coords_reported; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.h new file mode 100644 index 000000000000..99a914203ab8 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsGesture.h @@ -0,0 +1,38 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS Gesture Utilities * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsGesture.h +* \brief Contains all the macro and prototypes to handle the Gesture Detection features +*/ + +#ifndef FTS_GESTURE_H_ +#define FTS_GESTURE_H_ + +#include "ftsHardware.h" + +#define GESTURE_MASK_SIZE 4 + +#define GESTURE_MAX_COORDS_PAIRS_REPORT 100 + +int updateGestureMask(u8 *mask, int size, int en); +int disableGesture(u8 *mask, int size); +int enableGesture(u8 *mask, int size); +int enterGestureMode(int reload); +int isAnyGestureActive(void); +int readGestureCoords(u8 *event); +int getGestureCoords(u16 **x, u16 **y); + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsHardware.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsHardware.h new file mode 100644 index 000000000000..8e9e87eb0caa --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsHardware.h @@ -0,0 +1,217 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* HW related data * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsHardware.h +* \brief Contains all the definitions and information related to the IC from an hardware point of view +*/ + +#ifndef FTS_HARDWARE_H +#define FTS_HARDWARE_H + +/*DIGITAL CHIP INFO*/ +#define DCHIP_ID_0 0x36 /*LSB chip ID for FTM5*/ +#define DCHIP_ID_1 0x39 /*MSB chip ID for FTM5*/ + +#define DCHIP_FW_VER_BYTE 2 /*number of bytes of the fw versions*/ + +/*CHUNKS*/ +#define READ_CHUNK \ + 1024 /*chunk dimension of a single i2c read, max allowed value is 2kB*/ +#define WRITE_CHUNK \ + 1024 /*chunk dimension of a single i2c write, max allowed value is 2kB*/ +#define MEMORY_CHUNK \ + 1024 /*chunk dimenasion of a single i2c write on mem, max allowed value is 2kB*/ + +/*PROTOCOL INFO*/ +#define I2C_INTERFACE /*comment if the chip use SPI bus*/ +#ifdef I2C_INTERFACE +#define I2C_SAD 0x49 /*slave address of the IC*/ +#else +#define SPI4_WIRE /*comment if the master is SPI3 wires (MOSI and MISO share same line)*/ +#define SPI_DELAY_CS 10 /*time in usec to wait before rising the CS*/ +#define SPI_CLOCK_FREQ 7000000 /*clock frequency in Hz of the SPI bus*/ +#endif + +#define IER_ENABLE 0x41 /*value to write in IER_ADDR to enable the interrupts*/ +#define IER_DISABLE \ + 0x00 /*value to write in IER_ADDR to disable the interrupts*/ + +/*FLASH COMMAND*/ +/** @defgroup flash_command Flash Commands + * All the commands that works with the flash of the IC + * @{ + */ +#define FLASH_CMD_UNLOCK 0xF7 + +#define FLASH_CMD_READ_REGISTER 0xFA +#define FLASH_CMD_WRITE_REGISTER 0xFA + +/*FLASH UNLOCK PARAMETER*/ +#define FLASH_UNLOCK_CODE0 0x25 +#define FLASH_UNLOCK_CODE1 0x20 +#define FLASH_UNLOCK_CODE2 0x6B +#define FLASH_UNLOCK_CODE3 0x00 + +#define FLASH_UVLO_ENABLE_CODE0 0x1B +#define FLASH_UVLO_ENABLE_CODE1 0x66 +#define FLASH_AUTOPOWERDOWN_ENABLE_CODE0 0x68 +#define FLASH_AUTOPOWERDOWN_ENABLE_CODE1 0x13 +/*FLASH ERASE and DMA PARAMETER*/ +#define FLASH_ERASE_START 0x80 +#define FLASH_ERASE_CODE1 0xC0 +#define FLASH_DMA_CODE1 0xC0 +#define FLASH_ERASE_UNLOCK_CODE0 0xDE +#define FLASH_ERASE_UNLOCK_CODE1 0x03 +#define FLASH_ERASE_CODE0 0x6A +#define FLASH_DMA_CODE0 0x71 +#define FLASH_DMA_CONFIG 0x72 +#define FLASH_NUM_PAGE 32 /*number of pages in main flash*/ + +#define FLASH_CX_PAGE_START 28 /*starting page which contain Cx data*/ +#define FLASH_CX_PAGE_END 30 /*last page which contain Cx data*/ +#define FLASH_PANEL_PAGE_START \ + 26 /*starting page which contain Panel Init data*/ +#define FLASH_PANEL_PAGE_END 27 /*last page which contain Panel Init data*/ + +/** @} */ + +/*FLASH ADDRESS*/ + +#define FLASH_ADDR_CODE \ + 0x00000000 /*starting address (words) in the flash of the code in FTI*/ +#define FLASH_ADDR_CONFIG \ + 0x00007C00 /*starting address (words) in the flash of the config in FTI*/ +#define FLASH_ADDR_CX \ + 0x00007000 /*starting address (words) in the flash of the Init data in FTI*/ + +/*SIZES FW, CODE, CONFIG, MEMH*/ +/** @defgroup fw_file FW file info + * All the info related to the fw file + * @{ + */ + +#define FW_HEADER_SIZE 64 /*dimension of the header of the .fts file*/ +#define FW_HEADER_SIGNATURE 0xAA55AA55 /*header signature*/ +#define FW_FTB_VER 0x00000001 /*.ftb version*/ +#define FW_BYTES_ALLIGN 4 /*allignment of the info*/ +#define FW_BIN_VER_OFFSET 16 /*offset of the fw version in the .ftb file*/ +#define FW_BIN_CONFIG_ID_OFFSET 20 /*offset of the config id in the .ftb file*/ +#define FW_CX_VERSION (16 + 4) /*offset of CX version in the sec2 of FW file*/ + +/** @} */ + +/*FIFO*/ +#define FIFO_EVENT_SIZE 8 /*number of bytes of one event*/ +#define FIFO_DEPTH \ + 32 /*max number of events that the FIFO can collect before going in overflow in FTM5*/ + +#ifdef I2C_INTERFACE +#define FIFO_CMD_READALL 0x86 /*command to read all the events in the FIFO*/ +#else +#define FIFO_CMD_READALL 0x87 /*command to read all the events in the FIFO*/ +#endif +#define FIFO_CMD_READONE FIFO_CMD_READALL /*commad to read one event from FIFO*/ + +/*OP CODES FOR MEMORY (based on protocol)*/ +#ifdef I2C_INTERFACE +#define FTS_CMD_HW_REG_R 0xFA /*command to read an hw register if FTI*/ +#define FTS_CMD_HW_REG_W 0xFA /*command to write an hw register if FTI*/ +#define FTS_CMD_FRAMEBUFFER_R 0xA6 /*command to read the framebuffer if FTI*/ +#define FTS_CMD_CONFIG_R 0xA8 /*command to read the config memory if FTI*/ +#define FTS_CMD_CONFIG_W 0xA8 /*command to write the config memory if FTI*/ +#else +#define FTS_CMD_HW_REG_R 0xFB /*command to read an hw register if FTI*/ +#define FTS_CMD_HW_REG_W 0xFA /*command to write an hw register if FTI*/ +#define FTS_CMD_FRAMEBUFFER_R 0xA7 /*command to read the framebuffer if FTI*/ +#define FTS_CMD_CONFIG_R 0xA9 /*command to read the config memory if FTI*/ +#define FTS_CMD_CONFIG_W 0xA8 /*command to write the config memory if FTI*/ +#endif + +/*DUMMY BYTES DATA*/ + +#ifndef I2C_INTERFACE +#define DUMMY_HW_REG 1 /*1 if the first byte read from HW register is dummy*/ +#define DUMMY_FRAMEBUFFER \ + 1 /*1 if the first byte read from Frame buffer is dummy*/ +#define DUMMY_CONFIG 1 /*1 if the first byte read from Config Memory is dummy*/ +#define DUMMY_FIFO 1 /*1 if the first byte read from FIFO is dummy*/ +#else +#define DUMMY_HW_REG 0 /*1 if the first byte read from HW register is dummy*/ +#define DUMMY_FRAMEBUFFER \ + 0 /*1 if the first byte read from Frame buffer is dummy*/ +#define DUMMY_CONFIG 0 /*1 if the first byte read from Config Memory is dummy*/ +#define DUMMY_FIFO 0 /*1 if the first byte read from FIFO is dummy*/ +#endif + +/** @defgroup hw_adr HW Address + * @ingroup address + * Important addresses of hardware registers (and sometimes their important values) + * @{ + */ + +/*IMPORTANT HW ADDRESSES (u64)*/ +#define ADDR_FRAMEBUFFER \ + ((u64)0x0000000000000000) /*frame buffer address in memory*/ +#define ADDR_ERROR_DUMP \ + ((u64)0x000000000000EF80) /*start address dump error log*/ + +/*SYSTEM RESET INFO*/ +#define ADDR_SYSTEM_RESET \ + ((u64)0x0000000020000024) /*address of System control register in FTI*/ +#define SYSTEM_RESET_VALUE \ + 0x80 /*value to write in SYSTEM_RESET_ADDRESS to perform a system reset in FTM5*/ + +/*REMAP REGISTER*/ +#define ADDR_BOOT_OPTION \ + ((u64)0x0000000020000025) /*address of Boot option register in SONIA*/ + +/*INTERRUPT INFO*/ +#define ADDR_IER \ + ((u64)0x0000000020000029) /*address of the Interrupt enable register in FTMI*/ + +/*Chip ID/Fw Version*/ +#define ADDR_DCHIP_ID ((u64)0x0000000020000000) /*chip id address for FTI*/ +#define ADDR_DCHIP_FW_VER \ + ((u64)0x0000000020000004) /*fw version address for FTI*/ + +/*INTERFACE REGISTER*/ +#define ADDR_ICR \ + ((u64)0x000000002000002D) /*address of Device control register to set the comunication protocol (SPI/I2C)*/ +#define SPI4_MASK 0x02 /*bit to set spi4*/ + +/*CRC ADDR*/ +#define ADDR_CRC \ + ((u64)0x0000000020000078) /*address of the CRC control register in FTI*/ +#define CRC_MASK \ + 0x03 /*bitmask which reveal if there is a CRC error in the flash*/ + +#define ADDR_CONFIG_OFFSET \ + ((u64)0x0000000000000000) /*config address in memory if FTI*/ + +#define ADDR_GPIO_INPUT \ + ((u64)0x0000000020000030) /*address of GPIO input register*/ +#define ADDR_GPIO_DIRECTION \ + ((u64)0x0000000020000032) /*address of GPIO direction register*/ +#define ADDR_GPIO_PULLUP \ + ((u64)0x0000000020000034) /*address of GPIO pullup register*/ +#define ADDR_GPIO_CONFIG_REG0 \ + ((u64)0x000000002000003D) /*address of GPIO config register*/ +#define ADDR_GPIO_CONFIG_REG2 \ + ((u64)0x000000002000003F) /*address of GPIO config register*/ + +/**@}*/ + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c new file mode 100644 index 000000000000..9c24d52936e2 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c @@ -0,0 +1,911 @@ +/* + + ************************************************************************** + ** STMicroelectronics ** + ************************************************************************** + ** marco.cali@st.com ** + ************************************************************************** + * * + * I2C/SPI Communication * + * * + ************************************************************************** + ************************************************************************** + + */ + +/*! +* \file ftsIO.c +* \brief Contains all the functions which handle with the I2C/SPI communication +*/ + +#include "ftsSoftware.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef I2C_INTERFACE +#include +#include +static u16 I2CSAD; +#include +#endif + +static void *client; + +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsHardware.h" +#include "ftsIO.h" + +extern struct fts_ts_info *fts_info; +static struct mutex rw_lock; +static u8 *buf1; +static u8 *buf2; + +/** +* Initialize the static client variable of the fts_lib library in order to allow any i2c/spi transaction in the driver. (Must be called in the probe) +* @param clt pointer to i2c_client or spi_device struct which identify the bus slave device +* @return OK +*/ +int openChannel(void *clt) +{ + client = clt; +#ifdef I2C_INTERFACE + I2CSAD = ((struct i2c_client *)clt)->addr; + logError(0, "%s openChannel: SAD: %02X \n", tag, I2CSAD); +#else + logError(1, "%s %s: spi_master: flags = %04X !\n", tag, __func__, + ((struct spi_device *)client)->master->flags); + logError( + 1, + "%s %s: spi_device: max_speed = %d chip select = %02X bits_per_words = %d mode = %04X !\n", + tag, __func__, ((struct spi_device *)client)->max_speed_hz, + ((struct spi_device *)client)->chip_select, + ((struct spi_device *)client)->bits_per_word, + ((struct spi_device *)client)->mode); + logError(1, "%s openChannel: completed! \n", tag); +#endif + mutex_init(&rw_lock); + + if (!buf1) + buf1 = (u8 *)kzalloc(PAGE_SIZE, GFP_ATOMIC); + if (!buf2) + buf2 = (u8 *)kzalloc(PAGE_SIZE, GFP_ATOMIC); + if (!buf1 || !buf2) + return ERROR_ALLOC; + + return OK; +} + +#ifdef I2C_INTERFACE +/** +* Change the I2C slave address which will be used during the transaction (For Debug Only) +* @param sad new slave address id +* @return OK +*/ +int changeSAD(u8 sad) +{ + I2CSAD = sad; + return OK; +} +#endif + +/** +* Retrieve the pointer to the device struct of the IC +* @return a the device struct pointer if client was previously set or NULL in all the other cases +*/ +struct device *getDev() +{ + if (client != NULL) + return &(getClient()->dev); + else + return NULL; +} + +#ifdef I2C_INTERFACE +/** +* Retrieve the pointer of the i2c_client struct representing the IC as i2c slave +* @return client if it was previously set or NULL in all the other cases +*/ +struct i2c_client *getClient() +{ + if (client != NULL) + return (struct i2c_client *)client; + else + return NULL; +} +#else +/** +* Retrieve the pointer of the spi_device struct representing the IC as spi slave +* @return client if it was previously set or NULL in all the other cases +*/ +struct spi_device *getClient() +{ + if (client != NULL) + return (struct spi_device *)client; + else + return NULL; +} +#endif + +/****************** New I2C API *********************/ + +/** +* Perform a direct bus read +* @param outBuf pointer of a byte array which should contain the byte read from the IC +* @param byteToRead number of bytes to read +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_read(u8 *outBuf, int byteToRead) +{ + int ret = -1; + int retry = 0; + +#ifdef I2C_INTERFACE + struct i2c_msg I2CMsg[1]; + + I2CMsg[0].addr = (__u16)I2CSAD; + I2CMsg[0].flags = (__u16)I2C_M_RD; + I2CMsg[0].len = (__u16)byteToRead; + I2CMsg[0].buf = (__u8 *)outBuf; +#else + struct spi_message msg; + struct spi_transfer transfer[1] = { { 0 } }; + + spi_message_init(&msg); + + transfer[0].len = byteToRead; + transfer[0].delay_usecs = SPI_DELAY_CS; + transfer[0].tx_buf = NULL; + transfer[0].rx_buf = outBuf; + spi_message_add_tail(&transfer[0], &msg); +#endif + + if (client == NULL) + return ERROR_BUS_O; + while (retry < I2C_RETRY && ret < OK) { +#ifdef I2C_INTERFACE + ret = i2c_transfer(getClient()->adapter, I2CMsg, 1); +#else + ret = spi_sync(getClient(), &msg); +#endif + + retry++; + if (ret < OK) + mdelay(I2C_WAIT_BEFORE_RETRY); + } + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, ERROR_BUS_R); + return ERROR_BUS_R; + } + return OK; +} + +/** +* Perform a bus write followed by a bus read without a stop condition +* @param cmd byte array containing the command to write +* @param cmdLength size of cmd +* @param outBuf pointer of a byte array which should contain the bytes read from the IC +* @param byteToRead number of bytes to read +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_writeRead(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead) +{ + int ret = -1; + int retry = 0; + +#ifdef I2C_INTERFACE + struct i2c_msg I2CMsg[2]; + + I2CMsg[0].addr = (__u16)I2CSAD; + I2CMsg[0].flags = (__u16)0; + I2CMsg[0].len = (__u16)cmdLength; + I2CMsg[0].buf = (__u8 *)cmd; + + I2CMsg[1].addr = (__u16)I2CSAD; + I2CMsg[1].flags = I2C_M_RD; + I2CMsg[1].len = byteToRead; + I2CMsg[1].buf = (__u8 *)outBuf; + +#else + struct spi_message msg; + struct spi_transfer transfer[2] = { { 0 }, { 0 } }; + + spi_message_init(&msg); + + transfer[0].len = cmdLength; + transfer[0].tx_buf = cmd; + transfer[0].rx_buf = NULL; + spi_message_add_tail(&transfer[0], &msg); + + transfer[1].len = byteToRead; + transfer[1].delay_usecs = SPI_DELAY_CS; + transfer[1].tx_buf = NULL; + transfer[1].rx_buf = outBuf; + spi_message_add_tail(&transfer[1], &msg); + +#endif + + if (client == NULL) + return ERROR_BUS_O; + + while (retry < I2C_RETRY && ret < OK) { +#ifdef I2C_INTERFACE + ret = i2c_transfer(getClient()->adapter, I2CMsg, 2); +#else + ret = spi_sync(getClient(), &msg); +#endif + + retry++; + if (ret < OK) + mdelay(I2C_WAIT_BEFORE_RETRY); + } + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, ERROR_BUS_WR); + return ERROR_BUS_WR; + } + return OK; +} + +/** +* Perform a bus write +* @param cmd byte array containing the command to write +* @param cmdLength size of cmd +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_write(u8 *cmd, int cmdLength) +{ + int ret = -1; + int retry = 0; + +#ifdef I2C_INTERFACE + struct i2c_msg I2CMsg[1]; + + I2CMsg[0].addr = (__u16)I2CSAD; + I2CMsg[0].flags = (__u16)0; + I2CMsg[0].len = (__u16)cmdLength; + I2CMsg[0].buf = (__u8 *)cmd; +#else + struct spi_message msg; + struct spi_transfer transfer[1] = { { 0 } }; + + spi_message_init(&msg); + + transfer[0].len = cmdLength; + transfer[0].delay_usecs = SPI_DELAY_CS; + transfer[0].tx_buf = cmd; + transfer[0].rx_buf = NULL; + spi_message_add_tail(&transfer[0], &msg); +#endif + + if (client == NULL) + return ERROR_BUS_O; + while (retry < I2C_RETRY && ret < OK) { +#ifdef I2C_INTERFACE + ret = i2c_transfer(getClient()->adapter, I2CMsg, 1); +#else + ret = spi_sync(getClient(), &msg); +#endif + + retry++; + if (ret < OK) + mdelay(I2C_WAIT_BEFORE_RETRY); + } + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, ERROR_BUS_W); + return ERROR_BUS_W; + } + return OK; +} +#ifdef CONFIG_I2C_BY_DMA +/** + * same as above but can be used when enable DMA. + */ +int fts_read_dma_safe(u8 *outBuf, int byteToRead) +{ + int ret; + struct fts_dma_buf *dma = fts_info->dma_buf; + u8 *malcBuf = dma->rdBuf; + u8 *tmpBuf = NULL; + u8 *finalBuf; + + mutex_lock(&dma->dmaBufLock); + /*use malloc buf*/ + if (byteToRead > 1) { + /*extend malloc buf*/ + if (unlikely(byteToRead > PAGE_SIZE)) { + tmpBuf = kzalloc(byteToRead, GFP_KERNEL); + if (!tmpBuf) { + logError(1, "%s %s:ERROR alloc mem failed!", + tag, __func__); + mutex_unlock(&dma->dmaBufLock); + return ERROR_ALLOC; + } + finalBuf = tmpBuf; + } else { + finalBuf = malcBuf; + } + } else { + finalBuf = outBuf; + } + + ret = fts_read(finalBuf, byteToRead); + if ((ret == OK) && (byteToRead > 1)) { + memcpy(outBuf, finalBuf, byteToRead); + } + if (unlikely(tmpBuf)) + kfree(tmpBuf); + mutex_unlock(&dma->dmaBufLock); + + return ret; +} + +int fts_writeRead_dma_safe(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead) +{ + int ret; + struct fts_dma_buf *dma = fts_info->dma_buf; + u8 *malcRdBuf = dma->rdBuf; + u8 *malcWrBuf = dma->wrBuf; + u8 *rdBuf, *tmpRdBuf = NULL; + u8 *wrBuf, *tmpWrBuf = NULL; + + mutex_lock(&dma->dmaBufLock); + if (cmdLength > 1) { + if (unlikely(cmdLength > PAGE_SIZE)) { + tmpWrBuf = kzalloc(cmdLength, GFP_KERNEL); + if (!tmpWrBuf) { + logError(1, "%s %s:ERROR alloc mem failed!", + tag, __func__); + mutex_unlock(&dma->dmaBufLock); + return ERROR_ALLOC; + } + wrBuf = tmpWrBuf; + } else { + wrBuf = malcWrBuf; + } + memcpy(wrBuf, cmd, cmdLength); + } else { + wrBuf = cmd; + } + + if (byteToRead > 1) { + if (unlikely(byteToRead > PAGE_SIZE)) { + tmpRdBuf = kzalloc(byteToRead, GFP_KERNEL); + if (!tmpRdBuf) { + logError(1, "%s %s:ERROR alloc mem failed!", + tag, __func__); + if (tmpWrBuf) + kfree(tmpWrBuf); + mutex_unlock(&dma->dmaBufLock); + return ERROR_ALLOC; + } + rdBuf = tmpRdBuf; + } else { + rdBuf = malcRdBuf; + } + } else { + rdBuf = outBuf; + } + + ret = fts_writeRead(wrBuf, cmdLength, rdBuf, byteToRead); + if ((ret == OK) && (byteToRead > 1)) + memcpy(outBuf, rdBuf, byteToRead); + + if (unlikely(tmpRdBuf)) + kfree(tmpRdBuf); + if (unlikely(tmpWrBuf)) + kfree(tmpWrBuf); + mutex_unlock(&dma->dmaBufLock); + + return ret; +} + +int fts_write_dma_safe(u8 *cmd, int cmdLength) +{ + int ret; + struct fts_dma_buf *dma = fts_info->dma_buf; + u8 *malcBuf = dma->wrBuf; + u8 *tmpBuf = NULL; + u8 *finalBuf; + + mutex_lock(&dma->dmaBufLock); + /*use malloc buf*/ + if (cmdLength > 1) { + /*extend malloc buf*/ + if (unlikely(cmdLength > PAGE_SIZE)) { + tmpBuf = kzalloc(cmdLength, GFP_KERNEL); + if (!tmpBuf) { + logError(1, "%s %s:ERROR alloc mem failed!", + tag, __func__); + mutex_unlock(&dma->dmaBufLock); + return ERROR_ALLOC; + } + finalBuf = tmpBuf; + } else { + finalBuf = malcBuf; + } + memcpy(finalBuf, cmd, cmdLength); + } else { + finalBuf = cmd; + } + + ret = fts_write(finalBuf, cmdLength); + + if (unlikely(tmpBuf)) + kfree(tmpBuf); + mutex_unlock(&dma->dmaBufLock); + + return ret; +} +#else +int fts_read_dma_safe(u8 *outBuf, int byteToRead) +{ + return fts_read(outBuf, byteToRead); +} +int fts_writeRead_dma_safe(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead) +{ + return fts_writeRead(cmd, cmdLength, outBuf, byteToRead); +} +int fts_write_dma_safe(u8 *cmd, int cmdLength) +{ + return fts_write(cmd, cmdLength); +} +#endif + +/** +* Write a FW command to the IC and check automatically the echo event +* @param cmd byte array containing the command to send +* @param cmdLength size of cmd +* @return OK if success, or an error code which specify the type of error encountered +*/ +int fts_writeFwCmd(u8 *cmd, int cmdLength) +{ + int ret = -1; + int ret2 = -1; + int retry = 0; +#ifdef I2C_INTERFACE + struct i2c_msg I2CMsg[1]; + + I2CMsg[0].addr = (__u16)I2CSAD; + I2CMsg[0].flags = (__u16)0; + I2CMsg[0].len = (__u16)cmdLength; + I2CMsg[0].buf = (__u8 *)cmd; +#else + struct spi_message msg; + struct spi_transfer transfer[1] = { { 0 } }; + + spi_message_init(&msg); + + transfer[0].len = cmdLength; + transfer[0].delay_usecs = SPI_DELAY_CS; + transfer[0].tx_buf = cmd; + transfer[0].rx_buf = NULL; + spi_message_add_tail(&transfer[0], &msg); +#endif + + if (client == NULL) + return ERROR_BUS_O; + resetErrorList(); + while (retry < I2C_RETRY && (ret < OK || ret2 < OK)) { +#ifdef I2C_INTERFACE + ret = i2c_transfer(getClient()->adapter, I2CMsg, 1); +#else + ret = spi_sync(getClient(), &msg); +#endif + retry++; + if (ret >= 0) + ret2 = checkEcho(cmd, cmdLength); + if (ret < OK || ret2 < OK) + mdelay(I2C_WAIT_BEFORE_RETRY); + } + if (ret < 0) { + logError(1, "%s fts_writeFwCmd: ERROR %08X\n", tag, + ERROR_BUS_W); + return ERROR_BUS_W; + } + if (ret2 < OK) { + logError(1, "%s fts_writeFwCmd: check echo ERROR %08X\n", tag, + ret2); + return ret2; + } + return OK; +} + +/** +* Perform two bus write and one bus read without any stop condition +* In case of FTI this function is not supported and the same sequence can be achieved calling fts_write followed by an fts_writeRead. +* @param writeCmd1 byte array containing the first command to write +* @param writeCmdLength size of writeCmd1 +* @param readCmd1 byte array containing the second command to write +* @param readCmdLength size of readCmd1 +* @param outBuf pointer of a byte array which should contain the bytes read from the IC +* @param byteToRead number of bytes to read +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_writeThenWriteRead(u8 *writeCmd1, int writeCmdLength, u8 *readCmd1, + int readCmdLength, u8 *outBuf, int byteToRead) +{ + int ret = -1; + int retry = 0; + +#ifdef I2C_INTERFACE + struct i2c_msg I2CMsg[3]; + + I2CMsg[0].addr = (__u16)I2CSAD; + I2CMsg[0].flags = (__u16)0; + I2CMsg[0].len = (__u16)writeCmdLength; + I2CMsg[0].buf = (__u8 *)writeCmd1; + + I2CMsg[1].addr = (__u16)I2CSAD; + I2CMsg[1].flags = (__u16)0; + I2CMsg[1].len = (__u16)readCmdLength; + I2CMsg[1].buf = (__u8 *)readCmd1; + + I2CMsg[2].addr = (__u16)I2CSAD; + I2CMsg[2].flags = I2C_M_RD; + I2CMsg[2].len = byteToRead; + I2CMsg[2].buf = (__u8 *)outBuf; +#else + struct spi_message msg; + struct spi_transfer transfer[3] = { { 0 }, { 0 }, { 0 } }; + + spi_message_init(&msg); + + transfer[0].len = writeCmdLength; + transfer[0].tx_buf = writeCmd1; + transfer[0].rx_buf = NULL; + spi_message_add_tail(&transfer[0], &msg); + + transfer[1].len = readCmdLength; + transfer[1].tx_buf = readCmd1; + transfer[1].rx_buf = NULL; + spi_message_add_tail(&transfer[1], &msg); + + transfer[2].len = byteToRead; + transfer[2].delay_usecs = SPI_DELAY_CS; + transfer[2].tx_buf = NULL; + transfer[2].rx_buf = outBuf; + spi_message_add_tail(&transfer[2], &msg); +#endif + + if (client == NULL) + return ERROR_BUS_O; + while (retry < I2C_RETRY && ret < OK) { +#ifdef I2C_INTERFACE + ret = i2c_transfer(getClient()->adapter, I2CMsg, 3); +#else + ret = spi_sync(getClient(), &msg); +#endif + retry++; + if (ret < OK) + mdelay(I2C_WAIT_BEFORE_RETRY); + } + + if (ret < 0) { + logError(1, "%s %s: ERROR %08X\n", tag, __func__, ERROR_BUS_WR); + return ERROR_BUS_WR; + } + return OK; +} + +/** +* Perform a chunked write with one byte op code and 1 to 8 bytes address +* @param cmd byte containing the op code to write +* @param addrSize address size in byte +* @param address the starting address +* @param data pointer of a byte array which contain the bytes to write +* @param dataSize size of data +* @return OK if success or an error code which specify the type of error encountered +*/ +/* this function works only if the address is max 8 bytes */ +int fts_writeU8UX(u8 cmd, AddrSize addrSize, u64 address, u8 *data, + int dataSize) +{ + u8 *finalCmd = buf1; + int remaining = dataSize; + int toWrite = 0, i = 0; + + mutex_lock(&rw_lock); + if (addrSize <= sizeof(u64)) { + while (remaining > 0) { + if (remaining >= WRITE_CHUNK) { + toWrite = WRITE_CHUNK; + remaining -= WRITE_CHUNK; + } else { + toWrite = remaining; + remaining = 0; + } + + finalCmd[0] = cmd; + logError(0, "%s %s: addrSize = %d \n", tag, __func__, + addrSize); + for (i = 0; i < addrSize; i++) { + finalCmd[i + 1] = + (u8)((address >> + ((addrSize - 1 - i) * 8)) & + 0xFF); + logError(1, "%s %s: cmd[%d] = %02X \n", tag, + __func__, i + 1, finalCmd[i + 1]); + } + + memcpy(&finalCmd[addrSize + 1], data, toWrite); + + if (fts_write(finalCmd, 1 + addrSize + toWrite) < OK) { + logError(1, "%s %s: ERROR %08X \n", tag, + __func__, ERROR_BUS_W); + mutex_unlock(&rw_lock); + return ERROR_BUS_W; + } + + address += toWrite; + + data += toWrite; + } + } else { + logError( + 1, + "%s %s: address size bigger than max allowed %d... ERROR %08X \n", + tag, __func__, sizeof(u64), ERROR_OP_NOT_ALLOW); + } + mutex_unlock(&rw_lock); + + return OK; +} + +/** +* Perform a chunked write read with one byte op code and 1 to 8 bytes address and dummy byte support. +* @param cmd byte containing the op code to write +* @param addrSize address size in byte +* @param address the starting address +* @param outBuf pointer of a byte array which contain the bytes to read +* @param byteToRead number of bytes to read +* @param hasDummyByte if the first byte of each reading is dummy (must be skipped) set to 1, otherwise if it is valid set to 0 (or any other value) +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_writeReadU8UX(u8 cmd, AddrSize addrSize, u64 address, u8 *outBuf, + int byteToRead, int hasDummyByte) +{ + u8 *finalCmd = buf1; + u8 *buff = buf2; + int remaining = byteToRead; + int toRead = 0, i = 0; + + mutex_lock(&rw_lock); + while (remaining > 0) { + if (remaining >= READ_CHUNK) { + toRead = READ_CHUNK; + remaining -= READ_CHUNK; + } else { + toRead = remaining; + remaining = 0; + } + + finalCmd[0] = cmd; + for (i = 0; i < addrSize; i++) { + finalCmd[i + 1] = + (u8)((address >> ((addrSize - 1 - i) * 8)) & + 0xFF); + } + + if (hasDummyByte == 1) { + if (fts_writeRead(finalCmd, 1 + addrSize, buff, + toRead + 1) < OK) { + logError(1, + "%s %s: read error... ERROR %08X \n", + tag, __func__, ERROR_BUS_WR); + mutex_unlock(&rw_lock); + return ERROR_BUS_WR; + } + memcpy(outBuf, buff + 1, toRead); + } else { + if (fts_writeRead(finalCmd, 1 + addrSize, buff, + toRead) < OK) { + logError(1, + "%s %s: read error... ERROR %08X \n", + tag, __func__, ERROR_BUS_WR); + mutex_unlock(&rw_lock); + return ERROR_BUS_WR; + } + memcpy(outBuf, buff, toRead); + } + + address += toRead; + + outBuf += toRead; + } + + mutex_unlock(&rw_lock); + + return OK; +} + +/** +* Perform a chunked write followed by a second write with one byte op code for each write and 1 to 8 bytes address (the sum of the 2 address size of the two writes can not exceed 8 bytes) +* @param cmd1 byte containing the op code of first write +* @param addrSize1 address size in byte of first write +* @param cmd2 byte containing the op code of second write +* @param addrSize2 address size in byte of second write +* @param address the starting address +* @param data pointer of a byte array which contain the bytes to write +* @param dataSize size of data +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_writeU8UXthenWriteU8UX(u8 cmd1, AddrSize addrSize1, u8 cmd2, + AddrSize addrSize2, u64 address, u8 *data, + int dataSize) +{ + u8 *finalCmd1 = NULL; + u8 *finalCmd2 = buf1; + int remaining = dataSize; + int toWrite = 0, i = 0, ret = OK; + + mutex_lock(&rw_lock); + finalCmd1 = (u8 *)kzalloc(sizeof(u8) * 10, GFP_KERNEL); + if (!finalCmd1) { + ret = ERROR_ALLOC; + goto end; + } + + while (remaining > 0) { + if (remaining >= WRITE_CHUNK) { + toWrite = WRITE_CHUNK; + remaining -= WRITE_CHUNK; + } else { + toWrite = remaining; + remaining = 0; + } + + finalCmd1[0] = cmd1; + for (i = 0; i < addrSize1; i++) { + finalCmd1[i + 1] = + (u8)((address >> + ((addrSize1 + addrSize2 - 1 - i) * 8)) & + 0xFF); + } + + finalCmd2[0] = cmd2; + for (i = addrSize1; i < addrSize1 + addrSize2; i++) { + finalCmd2[i - addrSize1 + 1] = + (u8)((address >> + ((addrSize1 + addrSize2 - 1 - i) * 8)) & + 0xFF); + } + + memcpy(&finalCmd2[addrSize2 + 1], data, toWrite); + + if (fts_write(finalCmd1, 1 + addrSize1) < OK) { + logError(1, "%s %s: first write error... ERROR %08X \n", + tag, __func__, ERROR_BUS_W); + ret = ERROR_BUS_W; + goto end; + } + + if (fts_write(finalCmd2, 1 + addrSize2 + toWrite) < OK) { + logError(1, + "%s %s: second write error... ERROR %08X \n", + tag, __func__, ERROR_BUS_W); + ret = ERROR_BUS_W; + goto end; + } + + address += toWrite; + + data += toWrite; + } + +end: + if (finalCmd1) + kfree(finalCmd1); + mutex_unlock(&rw_lock); + + return ret; +} + +/** +* Perform a chunked write followed by a write read with one byte op code and 1 to 8 bytes address for each write and dummy byte support. +* @param cmd1 byte containing the op code of first write +* @param addrSize1 address size in byte of first write +* @param cmd2 byte containing the op code of second write read +* @param addrSize2 address size in byte of second write read +* @param address the starting address +* @param outBuf pointer of a byte array which contain the bytes to read +* @param byteToRead number of bytes to read +* @param hasDummyByte if the first byte of each reading is dummy (must be skipped) set to 1, otherwise if it is valid set to 0 (or any other value) +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_writeU8UXthenWriteReadU8UX(u8 cmd1, AddrSize addrSize1, u8 cmd2, + AddrSize addrSize2, u64 address, u8 *outBuf, + int byteToRead, int hasDummyByte) +{ + u8 *finalCmd1 = NULL; + u8 *finalCmd2 = NULL; + u8 *buff = buf1; + int remaining = byteToRead; + int toRead = 0, i = 0, ret = OK; + + mutex_lock(&rw_lock); + finalCmd1 = (u8 *)kzalloc(sizeof(u8) * 10, GFP_KERNEL); + if (!finalCmd1) { + ret = ERROR_ALLOC; + goto end; + } + finalCmd2 = (u8 *)kzalloc(sizeof(u8) * 10, GFP_KERNEL); + if (!finalCmd2) { + ret = ERROR_ALLOC; + goto end; + } + + while (remaining > 0) { + if (remaining >= READ_CHUNK) { + toRead = READ_CHUNK; + remaining -= READ_CHUNK; + } else { + toRead = remaining; + remaining = 0; + } + + finalCmd1[0] = cmd1; + for (i = 0; i < addrSize1; i++) { + finalCmd1[i + 1] = + (u8)((address >> + ((addrSize1 + addrSize2 - 1 - i) * 8)) & + 0xFF); + } + + finalCmd2[0] = cmd2; + for (i = addrSize1; i < addrSize1 + addrSize2; i++) { + finalCmd2[i - addrSize1 + 1] = + (u8)((address >> + ((addrSize1 + addrSize2 - 1 - i) * 8)) & + 0xFF); + } + + if (fts_write(finalCmd1, 1 + addrSize1) < OK) { + logError(1, "%s %s: first write error... ERROR %08X \n", + tag, __func__, ERROR_BUS_W); + ret = ERROR_BUS_W; + goto end; + } + + if (hasDummyByte == 1) { + if (fts_writeRead(finalCmd2, 1 + addrSize2, buff, + toRead + 1) < OK) { + logError(1, + "%s %s: read error... ERROR %08X \n", + tag, __func__, ERROR_BUS_WR); + ret = ERROR_BUS_WR; + goto end; + } + memcpy(outBuf, buff + 1, toRead); + } else { + if (fts_writeRead(finalCmd2, 1 + addrSize2, buff, + toRead) < OK) { + logError(1, + "%s %s: read error... ERROR %08X \n", + tag, __func__, ERROR_BUS_WR); + ret = ERROR_BUS_WR; + goto end; + } + memcpy(outBuf, buff, toRead); + } + + address += toRead; + + outBuf += toRead; + } + +end: + if (finalCmd1) + kfree(finalCmd1); + if (finalCmd2) + kfree(finalCmd2); + mutex_unlock(&rw_lock); + return ret; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.h new file mode 100644 index 000000000000..f225de35ec79 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.h @@ -0,0 +1,61 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* I2C/SPI Communication * +* * +************************************************************************** +************************************************************************** + +*/ +/*! +* \file ftsIO.h +* \brief Contains all the definitions and prototypes used and implemented in ftsIO.c +*/ + +#ifndef FTS_IO_H +#define FTS_IO_H + +#include "ftsSoftware.h" + +#define I2C_RETRY 3 +#define I2C_WAIT_BEFORE_RETRY 2 + +#ifdef I2C_INTERFACE +#include +#include +struct i2c_client *getClient(void); +#else +#include +struct spi_device *getClient(void); +#endif + +int openChannel(void *clt); +struct device *getDev(void); + +/*************** NEW I2C API ****************/ +int changeSAD(u8 sad); +int fts_read(u8 *outBuf, int byteToRead); +int fts_writeRead(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead); +int fts_write(u8 *cmd, int cmdLength); +int fts_read_dma_safe(u8 *outBuf, int byteToRead); +int fts_writeRead_dma_safe(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead); +int fts_write_dma_safe(u8 *cmd, int cmdLength); +int fts_writeFwCmd(u8 *cmd, int cmdLenght); +int fts_writeThenWriteRead(u8 *writeCmd1, int writeCmdLength, u8 *readCmd1, + int readCmdLength, u8 *outBuf, int byteToRead); +int fts_writeU8UX(u8 cmd, AddrSize addrSize, u64 address, u8 *data, + int dataSize); +int fts_writeReadU8UX(u8 cmd, AddrSize addrSize, u64 address, u8 *outBuf, + int byteToRead, int hasDummyByte); +int fts_writeU8UXthenWriteU8UX(u8 cmd1, AddrSize addrSize1, u8 cmd2, + AddrSize addrSize2, u64 address, u8 *data, + int dataSize); +int fts_writeU8UXthenWriteReadU8UX(u8 cmd1, AddrSize addrSize1, u8 cmd2, + AddrSize addrSize2, u64 address, u8 *outBuf, + int count, int hasDummyByte); +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsSoftware.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsSoftware.h new file mode 100644 index 000000000000..2d13cfe58910 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsSoftware.h @@ -0,0 +1,400 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FW related data * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsSoftware.h +* \brief Contains all the definitions and information related to the IC from a fw/driver point of view +*/ + +#ifndef FTS_SOFTWARE_H +#define FTS_SOFTWARE_H +#include +#include "ftsHardware.h" + +typedef signed char i8; /*basic type that represent one signed byte (or 8 bits)*/ + +/** + * Enumerator which contains all the possible address length expressed in bytes. + */ +typedef enum { + NO_ADDR = 0, + BITS_8 = 1, + BITS_16 = 2, + BITS_24 = 3, + BITS_32 = 4, + BITS_40 = 5, + BITS_48 = 6, + BITS_56 = 7, + BITS_64 = 8 +} AddrSize; + +/******************** NEW API *********************/ + +/** @defgroup host_command Fw Host op codes + * Valid op codes for fw commands + * @{ + */ + +/** @defgroup scan_mode Scan Mode +* @ingroup host_command +* Set the scanning mode required according to the parameters +* @{ +*/ +#define FTS_CMD_SCAN_MODE 0xA0 /*OP Code to set scan mode*/ +/** @} */ + +/** @defgroup feat_sel Feature Select +* @ingroup host_command +* Set the system defined features to enable/disable according the parameters +* @{ +*/ +#define FTS_CMD_FEATURE 0xA2 /*OP code to set features*/ +/** @} */ + +/** @defgroup sys_cmd System Command +* @ingroup host_command +* Execute a system command to perform core tasks +* @{ +*/ +#define FTS_CMD_SYSTEM 0xA4 /*OP code to write s system command*/ + +#define FTS_CMD_LOCKDOWN_ID 0x70 +#define FTS_CMD_CUSTOM 0xC0 +/** @} */ + +/** @} */ + +/*SCAN MODE OPTION (0xA0)*/ +/** @defgroup scan_opt Scan Mode Option +* @ingroup scan_mode +* Valid scanning modes and their options +* @{ +*/ +#define SCAN_MODE_ACTIVE 0x00 /*Select the Active scanning mode*/ +#define SCAN_MODE_LOW_POWER 0x01 /*Select the low power scanning mode*/ +#define SCAN_MODE_JIG_1 0x02 /*Select the Jig test 1*/ +#define SCAN_MODE_LOCKED 0x03 /*Select the Scan mode which will be locked*/ +/** @}*/ + +/** @defgroup active_bitmask Active Mode Bitmask +* @ingroup scan_opt +* Bitmask to use to enables the specific scanning with the SCAN_MODE_ACTIVE option +* @{ +*/ +#define ACTIVE_MULTI_TOUCH 0x01 /*Bit 0 MS/SS scan*/ +#define ACTIVE_KEY 0x02 /*Bit 1 Key scan*/ +#define ACTIVE_HOVER 0x04 /*Bit 2 Hover scan*/ +#define ACTIVE_PROXIMITY 0x08 /*Bit 3 Proximity scan*/ +#define ACTIVE_FORCE 0x10 /*Bit 4 Force scan*/ +/** @}*/ + +/** @defgroup locked_opt Locked Mode Option +* @ingroup scan_opt +* Options to enable and lock specific scanning with the SCAN_MODE_LOCKED option +* @{ +*/ +#define LOCKED_ACTIVE 0x00 /*Active Scan Mode*/ +#define LOCKED_HOVER 0x01 /*Hover Scan Mode*/ +#define LOCKED_IDLE 0x02 /*Idle Scan Mode*/ +#define LOCKED_LP_DETECT 0x10 /*Low Power SS*/ +#define LOCKED_LP_ACTIVE 0x11 /*Low Power MS*/ +/** @}*/ + +/** @defgroup feat_opt Feature Selection Option +* @ingroup feat_sel +* System defined features that can be enable/disable +* @{ +*/ +#define FEAT_SEL_GLOVE 0x00 /*Glove Mode*/ +#define FEAT_SEL_COVER 0x01 /*Cover Mode*/ +#define FEAT_SEL_CHARGER 0x02 /*Charger Mode*/ +#define FEAT_SEL_GESTURE 0x03 /*Gesture Mode*/ +#define FEAT_SEL_GRIP 0x04 /*Grip Detection*/ +#define FEAT_SEL_STYLUS \ + 0x07 /*Stylus Mode (this is a driver define, not available in FW)*/ +/** @}*/ + +#define FEAT_ENABLE 1 /*General value to enable a feature*/ +#define FEAT_DISABLE 0 /*General value to disable a feature*/ + +/** @defgroup charger_opt Charger Mode Option +* @ingroup feat_sel +* Option for Charger Mode, it is a bitmask where the each bit indicate a different kind of chager +* @{ +*/ +#define CHARGER_CABLE 0x01 /*normal usb charger*/ +#define CHARGER_WIRLESS 0x02 /*wireless charger*/ +/** @}*/ + +/** @defgroup gesture_opt Gesture Mode Option +* @ingroup feat_sel +* Gesture IDs of the predefined gesture recognized by the fw. +* The ID represent also the position of the corresponding bit in the gesture mask +* @{ +*/ +#define GEST_ID_UP_1F 0x01 /*Bottom to Top line*/ +#define GEST_ID_DOWN_1F 0x02 /*Top to bottom line*/ +#define GEST_ID_LEFT_1F 0x03 /*Right to left line*/ +#define GEST_ID_RIGHT_1F 0x04 /*Left to right line*/ +#define GEST_ID_DBLTAP 0x05 /*Double Tap*/ +#define GEST_ID_O 0x06 /*'O'*/ +#define GEST_ID_C 0x07 /*'C'*/ +#define GEST_ID_M 0x08 /*'M'*/ +#define GEST_ID_W 0x09 /*'W'*/ +#define GEST_ID_E 0x0A /*'e'*/ +#define GEST_ID_L 0x0B /*'L'*/ +#define GEST_ID_F 0x0C /*'F'*/ +#define GEST_ID_V 0x0D /*'V'*/ +#define GEST_ID_AT 0x0E /*'@'*/ +#define GEST_ID_S 0x0F /*'S'*/ +#define GEST_ID_Z 0x10 /*'Z'*/ +#define GEST_ID_LEFTBRACE 0x11 /*'<'*/ +#define GEST_ID_RIGHTBRACE 0x12 /*'>'*/ +#define GEST_ID_CARET 0x13 /*'^'*/ +#define GEST_ID_LONG_PRESS 0x18 /*'^'*/ +#define GEST_ID_SINGTAP 0x19 /*'^'*/ +/** @}*/ + +/** @defgroup sys_opt System Command Option +* @ingroup sys_cmd +* Valid System Command Parameters +* @{ +*/ +#define SYS_CMD_SPECIAL 0x00 /*Special Commands*/ +#define SYS_CMD_INT 0x01 /*FW Interrupt Control*/ +#define SYS_CMD_FORCE_CAL 0x02 /*Force Calibration*/ +#define SYS_CMD_CX_TUNING 0x03 /*CX initialization*/ +#define SYS_CMD_ITO 0x04 /*ITO test*/ +#define SYS_CMD_SAVE_FLASH 0x05 /*Saving to flash*/ +#define SYS_CMD_LOAD_DATA 0x06 /*Load Host data memory*/ +#define SYS_CMD_SPECIAL_TUNING 0x08 /*Perform some special tuning*/ +/** @} */ + +/** @defgroup sys_special_opt Special Command Option +* @ingroup sys_cmd +* Valid special command +* @{ +*/ +#define SPECIAL_SYS_RESET 0x00 /*System Reset triggered by the FW*/ +#define SPECIAL_FIFO_FLUSH 0x01 /*Flush of the FIFO*/ +#define SPECIAL_PANEL_INIT 0x02 /*Panel Initialization*/ +#define SPECIAL_FULL_PANEL_INIT 0x03 /*Full panel initialization*/ +/** @} */ + +#define CAL_MS_TOUCH 0x00 /*Mutual Sense Touch*/ +#define CAL_MS_LOW_POWER 0x01 /*Mutual Sense Touch in low power mode*/ +#define CAL_SS_TOUCH 0x02 /*Self Sense Touch*/ +#define CAL_SS_IDLE 0x03 /*Self Sense Touch in idle mode*/ +#define CAL_MS_KEY 0x04 /*Mutual Sense Key*/ +#define CAL_SS_KEY 0x05 /*Self Sense Key*/ +#define CAL_MS_FORCE 0x06 /*Mutual Sense Force*/ +#define CAL_SS_FORCE 0x07 /*Self Sense Force*/ + +/** @defgroup ito_opt ITO Test Option +* @ingroup sys_cmd +* Valid option for the ITO test +* @{ +*/ +#define ITO_FORCE_OPEN 0x00 /*Check if some force channels is open*/ +#define ITO_SENSE_OPEN 0x01 /*Check if some sense channels is open*/ +#define ITO_FORCE_GROUND \ + 0x02 /*Check if some force channels is short to ground*/ +#define ITO_SENSE_GROUND \ + 0x03 /*Check if some sense channels is short to ground*/ +#define ITO_FORCE_VDD 0x04 /*Check if some force channels is short to VDD*/ +#define ITO_SENSE_VDD 0x05 /*Check if some sense channels is short to VDD*/ +#define ITO_FORCE_FORCE 0x06 /*Check force to force channels*/ +#define ITO_FORCE_SENSE 0x07 /*Check force to sense channels*/ +#define ITO_SENSE_SENSE 0x08 /*Check sense to sense channels*/ +#define ITO_KEY_FORCE_OPEN \ + 0x09 /*Check if some force channels used for the key is open*/ +#define ITO_KEY_SENSE_OPEN \ + 0x0A /*Check if some sense channels used for the key is open*/ +/** @}*/ + +/** @defgroup save_opt Save to Flash Option +* @ingroup sys_cmd +* Valid option for saving data to the Flash +* @{ +*/ +#define SAVE_FW_CONF 0x01 /*Save the confing to the flash*/ +#define SAVE_CX 0x02 /*Save the CX to the flash*/ +#define SAVE_PANEL_CONF 0x04 /*Save the Panel configuration to the flash*/ +/** @}*/ + +/** @defgroup load_opt Load Host Data Option +* @ingroup sys_cmd +* Valid option to ask to the FW to load host data into the memory +* @{ +*/ +#define LOAD_SYS_INFO 0x01 /*Load System Info*/ +#define LOAD_CX_MS_TOUCH 0x10 /*Load MS Init Data for Active Mode*/ +#define LOAD_CX_MS_LOW_POWER 0x11 /*Load MS Init Data for Low Power Mode*/ +#define LOAD_CX_SS_TOUCH 0x12 /*Load SS Init Data for Active Mode*/ +#define LOAD_CX_SS_TOUCH_IDLE 0x13 /*Load SS Init Data for Low Power Mode*/ +#define LOAD_CX_MS_KEY 0x14 /*Load MS Init Data for Key*/ +#define LOAD_CX_SS_KEY 0x15 /*Load SS Init Data for Key*/ +#define LOAD_CX_MS_FORCE 0x16 /*Load MS Init Data for Force*/ +#define LOAD_CX_SS_FORCE 0x17 /*Load SS Init Data for Force*/ +#define LOAD_CX_SS_HOVER 0x18 /*Load SS Hover Init Data for* Force */ +#define LOAD_SYNC_FRAME_RAW 0x30 /*Load a Synchronized Raw Frame*/ +#define LOAD_SYNC_FRAME_FILTER 0x31 /*Load a Synchronized Filter Frame*/ +#define LOAD_SYNC_FRAME_STRENGTH 0x33 /*Load a Synchronized Strength Frame*/ +#define LOAD_SYNC_FRAME_BASELINE 0x32 /*Load a Synchronized Baseline Frame*/ +#define LOAD_PANEL_CX_TOT_MS_TOUCH \ + 0x50 /*Load TOT MS Init Data for Active Mode*/ +#define LOAD_PANEL_CX_TOT_MS_LOW_POWER \ + 0x51 /*Load TOT MS Init Data for Low Power Mode*/ +#define LOAD_PANEL_CX_TOT_SS_TOUCH \ + 0x52 /*Load TOT SS Init Data for Active Mode*/ +#define LOAD_PANEL_CX_TOT_SS_TOUCH_IDLE \ + 0x53 /*Load TOT SS Init Data for Low Power Mode*/ +#define LOAD_PANEL_CX_TOT_MS_KEY 0x54 /*Load TOT MS Init Data for Key*/ +#define LOAD_PANEL_CX_TOT_SS_KEY 0x55 /*Load TOT SS Init Data for Key*/ +#define LOAD_PANEL_CX_TOT_MS_FORCE 0x56 /*Load TOT MS Init Data for Force*/ +#define LOAD_PANEL_CX_TOT_SS_FORCE 0x57 /*Load TOT SS Init Data for Force*/ +#define STAPI_HOST_DATA_ID_PANEL_CX_SS_HVR \ + 0x58 /*Load HOVER TOT SS Init Data for Activity*/ + +/** @}*/ + +#define SPECIAL_TUNING_LP_TIMER 0x01 /*Perform LP Timer calibration*/ +#define SPECIAL_TUNING_IOFF 0x02 /*Perform Ioff calibration*/ + +/** @}*/ + +/** @defgroup events_group FW Event IDs and Types +* Event IDs and Types pushed by the FW into the FIFO +* @{ +*/ +#define EVT_ID_NOEVENT 0x00 /*No Events*/ +#define EVT_ID_CONTROLLER_READY \ + 0x03 /*Controller ready, issued after a system reset.*/ +#define EVT_ID_ENTER_POINT 0x13 /*Touch enter in the sensing area*/ +#define EVT_ID_MOTION_POINT \ + 0x23 /*Touch motion (a specific touch changed position)*/ +#define EVT_ID_LEAVE_POINT 0x33 /*Touch leave the sensing area*/ +#define EVT_ID_STATUS_UPDATE 0x43 /*FW report a system condition change*/ +#define EVT_ID_USER_REPORT \ + 0x53 /*User related events triggered (keys, gestures, proximity etc)*/ +#define EVT_ID_DEBUG 0xE3 /*Debug Info*/ +#define EVT_ID_ERROR 0xF3 /*Error Event*/ + +#define NUM_EVT_ID \ + (((EVT_ID_ERROR & 0xF0) >> 4) + \ + 1) /*Max number of unique event IDs supported*/ +/** @}*/ + +/** @defgroup status_type Status Event Types +* @ingroup events_group +* Types of EVT_ID_STATUS_UPDATE events +* @{ +*/ +#define EVT_TYPE_STATUS_ECHO \ + 0x01 /*Echo event, contain the first 5 bytes of the FW command sent*/ +#define EVT_TYPE_STATUS_FRAME_DROP \ + 0x03 /*Some frame was skipped during the elaboration*/ +#define EVT_TYPE_STATUS_FORCE_CAL 0x05 /*Force Calibration has triggered*/ +#define EVT_TYPE_STATUS_WATER 0x06 /*Water Mode*/ +#define EVT_TYPE_STATUS_SS_RAW_SAT 0x07 /*Self Sense data saturated*/ +#define EVT_TYPE_STATUS_POCKET 0x09 +/** @} */ + +/** @defgroup user_type User Event Types +* @ingroup events_group +* Types of EVT_ID_USER_REPORT events generated by thw FW +* @{ +*/ +#define EVT_TYPE_USER_KEY 0x00 /*Keys pressed/relesed event report*/ +#define EVT_TYPE_USER_PROXIMITY 0x01 /*Proximity detection event report*/ +#define EVT_TYPE_USER_GESTURE 0x02 /*Gesture detection event report*/ +#define EVT_TYPE_USER_EARDET 0x03 /*ear detection event report*/ + +/** @}*/ + +/** @defgroup error_type Error Event Types +* @ingroup events_group +* Types of EVT_ID_ERROR events reported by the FW +* @{ +*/ +#define EVT_TYPE_ERROR_WATCHDOG 0x06 /*Watchdog timer expired*/ + +#define EVT_TYPE_ERROR_CRC_CFG_HEAD 0x20 /*CRC error in the Config Area Header*/ +#define EVT_TYPE_ERROR_CRC_CFG 0x21 /*CRC error in the Config Area*/ +#define EVT_TYPE_ERROR_CRC_PANEL_HEAD \ + 0x22 /*CRC error in the Panel Area Header*/ +#define EVT_TYPE_ERROR_CRC_PANEL 0x23 /*CRC error in the Panel Area*/ + +#define EVT_TYPE_ERROR_ITO_FORCETOGND 0x60 /*Force channel/s short to ground*/ +#define EVT_TYPE_ERROR_ITO_SENSETOGND 0x61 /*Sense channel/s short to ground*/ +#define EVT_TYPE_ERROR_ITO_FORCETOVDD 0x62 /*Force channel/s short to VDD*/ +#define EVT_TYPE_ERROR_ITO_SENSETOVDD 0x63 /*Sense channel/s short to VDD*/ +#define EVT_TYPE_ERROR_ITO_FORCE_P2P 0x64 /*Pin to Pin short Force channel/s*/ +#define EVT_TYPE_ERROR_ITO_SENSE_P2P 0x65 /*Pin to Pin short Sense channel/s*/ +#define EVT_TYPE_ERROR_ITO_FORCEOPEN 0x66 /*Force Panel open*/ +#define EVT_TYPE_ERROR_ITO_SENSEOPEN 0x67 /*Sense Panel open*/ +#define EVT_TYPE_ERROR_ITO_KEYOPEN 0x68 /*Key open*/ + +#define EVT_TYPE_ERROR_CRC_CX_HEAD 0xA0 /*CRC error in the CX Area Header*/ +#define EVT_TYPE_ERROR_CRC_CX 0xA1 /*CRC error in the CX Area*/ +#define EVT_TYPE_ERROR_CRC_CX_SUB_HEAD \ + 0xA5 /*CRC error in the CX Subsection Area Header*/ +#define EVT_TYPE_ERROR_CRC_CX_SUB 0xA6 /*CRC error in the CX Subsection Area*/ + +#define EVT_TYPE_ERROR_ESD 0xF0 /*ESD error*/ +/** @}*/ + +/** @defgroup address Chip Address + * Collection of HW and SW Addresses useful to collect different kind of data + * @{ + */ + +/** @defgroup config_adr SW Address + * @ingroup address + * Important addresses of data stored into Config memory (and sometimes their dimensions) + * @{ + */ +#define ADDR_CONFIG_ID 0x0010 /*Starting Address of the config ID*/ +#define CONFIG_ID_BYTE 2 /*Number of bytes of config ID*/ +#define ADDR_CONFIG_SENSE_LEN \ + 0x0030 /*Address where is stored the number of sense channels*/ +#define ADDR_CONFIG_FORCE_LEN \ + 0x0031 /*Address where is stored the number of force channels*/ +/** @}*/ + +/** @}*/ + +#define ERROR_DUMP_ROW_SIZE 32 /*number of rows of the error memory*/ +#define ERROR_DUMP_COL_SIZE \ + 4 /*number of bytes for each row of the error memory*/ +#define ERROR_DUMP_SIGNATURE 0xFA5005AF /*first row signature of a proper dump*/ + +#define TOUCH_TYPE_INVALID 0x00 /*Invalid touch type*/ +#define TOUCH_TYPE_FINGER 0x01 /*Finger touch*/ +#define TOUCH_TYPE_GLOVE 0x02 /*Glove touch*/ +#define TOUCH_TYPE_STYLUS 0x03 /*Stylus touch*/ +#define TOUCH_TYPE_PALM 0x04 /*Palm touch*/ +#define TOUCH_TYPE_HOVER 0x05 /*Hovering touch*/ + +#define FTS_KEY_0 0x01 /*Key 0 bit*/ +#define FTS_KEY_1 0x02 /*Key 1 bit*/ +#define FTS_KEY_2 0x04 /*Key 2 bit*/ +#define FTS_KEY_3 0x08 /*Key 3 bit*/ +#define FTS_KEY_4 0x10 /*Key 4 bit*/ +#define FTS_KEY_5 0x20 /*Key 5 bit*/ +#define FTS_KEY_6 0x40 /*Key 6 bit*/ +#define FTS_KEY_7 0x80 /*Key 7 bit*/ + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.c new file mode 100644 index 000000000000..34278f45a3d1 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.c @@ -0,0 +1,6342 @@ +/* + + ************************************************************************** + ** STMicroelectronics ** + ************************************************************************** + ** marco.cali@st.com ** + ************************************************************************** + * * + * FTS API for MP test * + * * + ************************************************************************** + ************************************************************************** + + */ + +/*! + * \file ftsTest.c + * \brief Contains all the functions related to the Mass Production Test + */ + +#include "ftsCompensation.h" +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsFrame.h" +#include "ftsHardware.h" +#include "ftsIO.h" +#include "ftsSoftware.h" +#include "ftsTest.h" +#include "ftsTime.h" +#include "ftsTool.h" +#include "../fts.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef LIMITS_H_FILE +#include "../fts_limits.h" +#endif + +TestToDo tests; +static LimitFile limit_file; + +/** + * Initialize the testToDo variable with the default tests to perform during the Mass Production Test + * @return OK + */ +int initTestToDo(void) +{ + /*** Initialize Limit File ***/ + limit_file.size = 0; + limit_file.data = NULL; + strlcpy(limit_file.name, " ", MAX_LIMIT_FILE_NAME); + tests.SelfHoverForceRaw = 1; /* /< SS Hover Force Raw min/Max test */ + tests.SelfHoverSenceRaw = 1; /* /< SS Hover Sence Raw min/Max test */ + tests.SelfHoverForceIxTotal = + 1; /* /< SS Hover Total Force Ix min/Max (for each node)* test */ + tests.SelfHoverSenceIxTotal = 1; + tests.MutualRawAdjITO = 0; + tests.MutualRaw = 0; + tests.MutualRawEachNode = 1; + tests.MutualRawGap = 0; + tests.MutualRawAdj = 0; + tests.MutualRawLP = 0; + tests.MutualRawGapLP = 0; + tests.MutualRawAdjLP = 0; + tests.MutualCx1 = 0; + tests.MutualCx2 = 0; + tests.MutualCx2Adj = 0; + tests.MutualCxTotal = 0; + tests.MutualCxTotalAdj = 0; + + tests.MutualCx1LP = 0; + tests.MutualCx2LP = 1; + tests.MutualCx2AdjLP = 1; + tests.MutualCxTotalLP = 0; + tests.MutualCxTotalAdjLP = 0; +#ifdef PHONE_KEY + tests.MutualKeyRaw = 0; +#else + tests.MutualKeyRaw = 0; +#endif + tests.MutualKeyCx1 = 0; + tests.MutualKeyCx2 = 0; +#ifdef PHONE_KEY + tests.MutualKeyCxTotal = 0; +#else + tests.MutualKeyCxTotal = 0; +#endif + tests.SelfForceRaw = 1; + tests.SelfForceRawGap = 0; + tests.SelfForceRawLP = 0; + tests.SelfForceRawGapLP = 0; + tests.SelfForceIx1 = 0; + tests.SelfForceIx2 = 0; + tests.SelfForceIx2Adj = 0; + tests.SelfForceIxTotal = 1; + tests.SelfForceIxTotalAdj = 0; + tests.SelfForceCx1 = 0; + tests.SelfForceCx2 = 0; + tests.SelfForceCx2Adj = 0; + tests.SelfForceCxTotal = 0; + tests.SelfForceCxTotalAdj = 0; + tests.SelfSenseRaw = 1; + tests.SelfSenseRawGap = 0; + tests.SelfSenseRawLP = 0; + tests.SelfSenseRawGapLP = 0; + tests.SelfSenseIx1 = 0; + tests.SelfSenseIx2 = 0; + tests.SelfSenseIx2Adj = 0; + tests.SelfSenseIxTotal = 1; + tests.SelfSenseIxTotalAdj = 0; + tests.SelfSenseCx1 = 0; + tests.SelfSenseCx2 = 0; + tests.SelfSenseCx2Adj = 0; + tests.SelfSenseCxTotal = 0; + tests.SelfSenseCxTotalAdj = 0; + return OK; +} + +/** + * Compute the Horizontal adjacent matrix doing the abs of the difference between the column i with the i-1 one. \n + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of signed bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjHoriz(i8 *data, int row, int column, u8 **result) +{ + int i, j; + int size = row * (column - 1); + + if (column < 2) { + logError(1, "%s computeAdjHoriz: ERROR % 08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u8 *)kmalloc(size * sizeof(u8), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjHoriz: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 0; i < row; i++) { + for (j = 1; j < column; j++) { + *(*result + (i * (column - 1) + (j - 1))) = + abs(data[i * column + j] - + data[i * column + (j - 1)]); + } + } + + return OK; +} + +/** + * Compute the Horizontal adjacent matrix of short values doing the abs of the difference between the column i with the i-1 one. + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of signed bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjHorizTotal(short *data, int row, int column, u16 **result) +{ + int i, j; + int size = row * (column - 1); + + if (column < 2) { + logError(1, "%s computeAdjHorizTotal: ERROR % 08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u16 *)kmalloc(size * sizeof(u16), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjHorizTotal: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 0; i < row; i++) { + for (j = 1; j < column; j++) { + *(*result + (i * (column - 1) + (j - 1))) = + abs(data[i * column + j] - + data[i * column + (j - 1)]); + } + } + + return OK; +} + +/** + * Compute the Vertical adjacent matrix doing the abs of the difference between the row i with the i-1 one. + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other. \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of signed bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjVert(i8 *data, int row, int column, u8 **result) +{ + int i, j; + int size = (row - 1) * (column); + + if (row < 2) { + logError(1, "%s computeAdjVert: ERROR % 08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u8 *)kmalloc(size * sizeof(u8), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjVert: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 1; i < row; i++) { + for (j = 0; j < column; j++) { + *(*result + ((i - 1) * column + j)) = + abs(data[i * column + j] - + data[(i - 1) * column + j]); + } + } + + return OK; +} + +/** + * Compute the Vertical adjacent matrix of short values doing the abs of the difference between the row i with the i-1 one. + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other. \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of signed bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjVertTotal(short *data, int row, int column, u16 **result) +{ + int i, j; + int size = (row - 1) * (column); + + if (row < 2) { + logError(1, "%s computeAdjVertTotal: ERROR %08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u16 *)kmalloc(size * sizeof(u16), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjVertTotal: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 1; i < row; i++) { + for (j = 0; j < column; j++) { + *(*result + ((i - 1) * column + j)) = + abs(data[i * column + j] - + data[(i - 1) * column + j]); + } + } + + return OK; +} + +/** + * Compute the Horizontal adjacent matrix doing the abs of the difference between the column i with the i-1 one. \n + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of unsigned bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjHorizFromU(u8 *data, int row, int column, u8 **result) +{ + int i, j; + int size = row * (column - 1); + + if (column < 2) { + logError(1, "%s computeAdjHoriz: ERROR %08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u8 *)kmalloc(size * sizeof(u8), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjHoriz: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 0; i < row; i++) { + for (j = 1; j < column; j++) { + *(*result + (i * (column - 1) + (j - 1))) = + abs(data[i * column + j] - + data[i * column + (j - 1)]); + } + } + + return OK; +} + +/** + * Compute the Horizontal adjacent matrix of u16 values doing the abs of the difference between the column i with the i-1 one. + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of unsigned bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjHorizTotalFromU(u16 *data, int row, int column, u16 **result) +{ + int i, j; + int size = row * (column - 1); + + if (column < 2) { + logError(1, "%s computeAdjHorizTotal: ERROR %08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u16 *)kmalloc(size * sizeof(u16), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjHorizTotal: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 0; i < row; i++) { + for (j = 1; j < column; j++) { + *(*result + (i * (column - 1) + (j - 1))) = + abs(data[i * column + j] - + data[i * column + (j - 1)]); + } + } + + return OK; +} + +/** + * Compute the Vertical adjacent matrix doing the abs of the difference between the row i with the i-1 one. + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other. \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of unsigned bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjVertFromU(u8 *data, int row, int column, u8 **result) +{ + int i, j; + int size = (row - 1) * (column); + + if (row < 2) { + logError(1, "%s computeAdjVert: ERROR %08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u8 *)kmalloc(size * sizeof(u8), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjVert: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 1; i < row; i++) { + for (j = 0; j < column; j++) { + *(*result + ((i - 1) * column + j)) = + abs(data[i * column + j] - + data[(i - 1) * column + j]); + } + } + + return OK; +} + +/** + * Compute the Vertical adjacent matrix of u16 values doing the abs of the difference between the row i with the i-1 one. + * Both the original data matrix and the adj matrix are disposed as 1 dimension array one row after the other. \n + * The resulting matrix has one column less than the starting original one \n + * @param data pointer to the array of unsigned bytes containing the original data + * @param row number of rows of the original data + * @param column number of columns of the original data + * @param result pointer of a pointer to an array of unsigned bytes which will contain the adj matrix + * @return OK if success or an error code which specify the type of error encountered + */ +int computeAdjVertTotalFromU(u16 *data, int row, int column, u16 **result) +{ + int i, j; + int size = (row - 1) * (column); + + if (row < 2) { + logError(1, "%s computeAdjVertTotal: ERROR %08X\n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + *result = (u16 *)kmalloc(size * sizeof(u16), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeAdjVertTotal: ERROR %08X\n", tag, + ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 1; i < row; i++) { + for (j = 0; j < column; j++) { + *(*result + ((i - 1) * column + j)) = + abs(data[i * column + j] - + data[(i - 1) * column + j]); + } + } + + return OK; +} + +int computeTotal(u8 *data, u8 main, int row, int column, int m, int n, + u16 **result) +{ + int i, j; + int size = (row) * (column); + *result = (u16 *)kmalloc(size * sizeof(u16), GFP_KERNEL); + + if (*result == NULL) { + logError(1, "%s computeTotal : ERROR %02X\n", tag, ERROR_ALLOC); + return ERROR_ALLOC; + } + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + *(*result + (i * column + j)) = + m * main + n * data[i * column + j]; + } + } + + return OK; +} + +/** + * Check that each value of a matrix of short doesn't exceed a min and a Max value (these values are included in the interval). \n + * The matrix is stored as 1 dimension array one row after the other. \n + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param min minimum value allowed + * @param max Maximum value allowed + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int checkLimitsMinMax(short *data, int row, int column, int min, int max) +{ + int i, j; + int count = 0; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] < min || + data[i * column + j] > max) { + logError( + 1, + "%s checkLimitsMinMax: Node[%d,%d] = %d exceed limit [%d, %d] \n", + tag, i, j, data[i * column + j], min, + max); + count++; + } + } + } + + return count; +} + +/** + * Check that the difference between the max and min of a matrix of short is less or equal to a threshold.\n + * The matrix is stored as 1 dimension array one row after the other. + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param threshold threshold value allowed + * @return OK if the difference is <= to threshold otherwise ERROR_TEST_CHECK_FAIL + */ +int checkLimitsGap(short *data, int row, int column, int threshold) +{ + int i, j; + int min_node; + int max_node; + + if (row == 0 || column == 0) { + logError( + 1, + "%s checkLimitsGap: invalid number of rows = %d or columns = %d ERROR %08X\n", + tag, row, column, ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } + + min_node = data[0]; + max_node = data[0]; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] < min_node) { + min_node = data[i * column + j]; + } else { + if (data[i * column + j] > max_node) + max_node = data[i * column + j]; + } + } + } + + if (max_node - min_node > threshold) { + logError(1, "%s checkLimitsGap: GAP = %d exceed limit %d \n", + tag, max_node - min_node, threshold); + return ERROR_TEST_CHECK_FAIL; + } else + return OK; +} + +/** + * Check that each value of a matrix of i8 doesn't exceed a specific min and Max value set for each node (these values are included in the interval). \n + * The matrixes of data, min and max values are stored as 1 dimension arrays one row after the other. + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param min pointer to a matrix which specify the minimum value allowed for each node + * @param max pointer to a matrix which specify the Maximum value allowed for each node + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int checkLimitsMap(i8 *data, int row, int column, int *min, int *max) +{ + int i, j; + int count = 0; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] < min[i * column + j] || + data[i * column + j] > max[i * column + j]) { + logError( + 1, + "%s checkLimitsMap: Node[%d,%d] = %d exceed limit [%d, %d] \n", + tag, i, j, data[i * column + j], + min[i * column + j], + max[i * column + j]); + count++; + } + } + } + + return count; +} + +/** + * Check that each value of a matrix of short doesn't exceed a specific min and Max value set for each node (these values are included in the interval). + * The matrixes of data, min and max values are stored as 1 dimension arrays one row after the other. + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param min pointer to a matrix which specify the minimum value allowed for each node + * @param max pointer to a matrix which specify the Maximum value allowed for each node + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int checkLimitsMapTotal(short *data, int row, int column, int *min, int *max) +{ + int i, j; + int count = 0; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] < min[i * column + j] || + data[i * column + j] > max[i * column + j]) { + logError( + 1, + "%s checkLimitsMapTotal: Node[%d,%d] = %d exceed limit [%d, %d] \n", + tag, i, j, data[i * column + j], + min[i * column + j], + max[i * column + j]); + count++; + } + } + } + + return count; +} + +/** + * Check that each value of a matrix of u8 doesn't exceed a specific min and Max value set for each node (these values are included in the interval). \n + * The matrixes of data, min and max values are stored as 1 dimension arrays one row after the other. + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param min pointer to a matrix which specify the minimum value allowed for each node + * @param max pointer to a matrix which specify the Maximum value allowed for each node + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int checkLimitsMapFromU(u8 *data, int row, int column, int *min, int *max) +{ + int i, j; + int count = 0; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] < min[i * column + j] || + data[i * column + j] > max[i * column + j]) { + logError( + 1, + "%s checkLimitsMap: Node[%d,%d] = %d exceed limit [%d, %d] \n", + tag, i, j, data[i * column + j], + min[i * column + j], + max[i * column + j]); + count++; + } + } + } + + return count; +} + +/** + * Check that each value of a matrix of u16 doesn't exceed a specific min and Max value set for each node (these values are included in the interval). + * The matrixes of data, min and max values are stored as 1 dimension arrays one row after the other. + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param min pointer to a matrix which specify the minimum value allowed for each node + * @param max pointer to a matrix which specify the Maximum value allowed for each node + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int checkLimitsMapTotalFromU(u16 *data, int row, int column, int *min, int *max) +{ + int i, j; + int count = 0; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] < min[i * column + j] || + data[i * column + j] > max[i * column + j]) { + logError( + 1, + "%s checkLimitsMapTotal: Node[%d,%d] = %d exceed limit [%d, %d] \n", + tag, i, j, data[i * column + j], + min[i * column + j], + max[i * column + j]); + count++; + } + logError(1, + "%s checkLimitsMapTotal: Node[%d,%d] = %d\n", + tag, i, j, data[i * column + j], + min[i * column + j], max[i * column + j]); + } + } + + return count; +} + +/** + * Check that each value of a matrix of u8 doesn't exceed a specific Max value set for each node (max value is included in the interval). + * The matrixes of data and max values are stored as 1 dimension arrays one row after the other. + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param max pointer to a matrix which specify the Maximum value allowed for each node + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int checkLimitsMapAdj(u8 *data, int row, int column, int *max) +{ + int i, j; + int count = 0; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] > max[i * column + j]) { + logError( + 1, + "%s checkLimitsMapAdj: Node[%d,%d] = %d exceed limit > %d \n", + tag, i, j, data[i * column + j], + max[i * column + j]); + count++; + } + } + } + + return count; +} + +/** + * Check that each value of a matrix of u16 doesn't exceed a specific Max value set for each node (max value is included in the interval). + * The matrixes of data and max values are stored as 1 dimension arrays one row after the other. + * @param data pointer to the array of short containing the data to check + * @param row number of rows of data + * @param column number of columns of data + * @param max pointer to a matrix which specify the Maximum value allowed for each node + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int checkLimitsMapAdjTotal(u16 *data, int row, int column, int *max) +{ + int i, j; + int count = 0; + + for (i = 0; i < row; i++) { + for (j = 0; j < column; j++) { + if (data[i * column + j] > max[i * column + j]) { + logError( + 1, + "%s checkLimitsMapAdjTotal: Node[%d,%d] = %d exceed limit > %d \n", + tag, i, j, data[i * column + j], + max[i * column + j]); + count++; + } + } + } + + return count; +} + +/** + * Perform an ITO test setting all the possible options (see @link ito_opt ITO Options @endlink) + * @return the number of elements that overcome the specified interval (0 = OK) + */ +int production_test_ito(char *path_limits, TestToDo *todo) +{ + int res = OK; + u8 sett[2] = { 0x00, 0x00 }; + MutualSenseFrame msRawFrame; + int *thresholds = NULL; + u16 *adj = NULL; + int trows, tcolumns; + logError(1, "%s ITO Production test is starting...\n", tag); + memset(&msRawFrame, 0x00, sizeof(msRawFrame)); + res = fts_system_reset(); + + if (res < 0) { + logError(1, "%s %s: ERROR %08X \n", tag, __func__, + ERROR_PROD_TEST_ITO); + return (res | ERROR_PROD_TEST_ITO); + } + + sett[0] = SPECIAL_TUNING_IOFF; + logError(0, "%s Trimming Ioff... \n", tag); + res = writeSysCmd(SYS_CMD_SPECIAL_TUNING, sett, 2); + + if (res < OK) { + logError(1, "%s production_test_ito: Trimm Ioff ERROR %08X \n", + tag, (res | ERROR_PROD_TEST_ITO)); + return (res | ERROR_PROD_TEST_ITO); + } + + sett[0] = 0xFF; + sett[1] = 0xFF; + logError(0, "%s ITO Check command sent... \n", tag); + res = writeSysCmd(SYS_CMD_ITO, sett, 2); + + if (res < OK) { + logError(1, "%s production_test_ito: ERROR %08X \n", tag, + (res | ERROR_PROD_TEST_ITO)); + return (res | ERROR_PROD_TEST_ITO); + } + + logError(0, "%s ITO Command = OK! \n", tag); + + if (todo->MutualRawAdjITO == 1) { + logError(1, "%s MS RAW ITO ADJ TEST: \n", tag); + logError(0, "%s Collecting MS Raw data... \n", tag); + res |= getMSFrame3(MS_RAW, &msRawFrame); + + if (res < OK) { + logError(1, "%s %s: getMSFrame failed... ERROR %08X \n", + tag, __func__, ERROR_PROD_TEST_ITO); + goto ERROR; + } + + logError(0, "%s MS RAW ITO ADJ HORIZONTAL TEST: \n", tag); + res = computeAdjHorizTotal(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, &adj); + + if (res < OK) { + logError( + 1, + "%s %s: computeAdjHoriz failed... ERROR %08X \n", + tag, __func__, ERROR_PROD_TEST_ITO); + goto ERROR; + } + + res = parseProductionTestLimits(path_limits, &limit_file, + MS_RAW_ITO_ADJH, &thresholds, + &trows, &tcolumns); + + if (res < OK || + (trows != msRawFrame.header.force_node || + tcolumns != msRawFrame.header.sense_node - 1)) { + logError( + 1, + "%s %s: parseProductionTestLimits MS_RAW_ITO_ADJH failed... ERROR %08X \n", + tag, __func__, ERROR_PROD_TEST_DATA); + goto ERROR; + } + + res = checkLimitsMapAdjTotal(adj, msRawFrame.header.force_node, + msRawFrame.header.sense_node - 1, + thresholds); + + if (res != OK) { + logError( + 1, + "%s production_test_data: checkLimitsAdj MS RAW ITO ADJH failed... ERROR COUNT = %d \n", + tag, res); + logError( + 0, + "%s MS RAW ITO ADJ HORIZONTAL TEST:.................FAIL \n\n", + tag); + print_frame_short( + "MS Raw ITO frame =", + array1dTo2d_short(msRawFrame.node_data, + msRawFrame.node_data_size, + msRawFrame.header.sense_node), + msRawFrame.header.force_node, + msRawFrame.header.sense_node); + res = ERROR_PROD_TEST_ITO; + goto ERROR; + } else + logError( + 0, + "%s MS RAW ITO ADJ HORIZONTAL TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + kfree(adj); + adj = NULL; + logError(0, "%s MS RAW ITO ADJ VERTICAL TEST: \n", tag); + res = computeAdjVertTotal(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, &adj); + + if (res < OK) { + logError( + 1, + "%s %s: computeAdjVert failed... ERROR %08X \n", + tag, __func__, ERROR_PROD_TEST_ITO); + goto ERROR; + } + + res = parseProductionTestLimits(path_limits, &limit_file, + MS_RAW_ITO_ADJV, &thresholds, + &trows, &tcolumns); + + if (res < OK || (trows != msRawFrame.header.force_node - 1 || + tcolumns != msRawFrame.header.sense_node)) { + logError( + 1, + "%s %s: parseProductionTestLimits MS_RAW_ITO_ADJV failed... ERROR %08X \n", + tag, __func__, ERROR_PROD_TEST_ITO); + goto ERROR; + } + + res = checkLimitsMapAdjTotal(adj, + msRawFrame.header.force_node - 1, + msRawFrame.header.sense_node, + thresholds); + + if (res != OK) { + logError( + 1, + "%s %s: checkLimitsAdj MS RAW ITO ADJV failed... ERROR COUNT = %d \n", + tag, __func__, res); + logError( + 0, + "%s MS RAW ITO ADJ VERTICAL TEST:.................FAIL \n\n", + tag); + print_frame_short( + "MS Raw ITO frame =", + array1dTo2d_short(msRawFrame.node_data, + msRawFrame.node_data_size, + msRawFrame.header.sense_node), + msRawFrame.header.force_node, + msRawFrame.header.sense_node); + res = ERROR_PROD_TEST_ITO; + goto ERROR; + } else + logError( + 0, + "%s MS RAW ITO ADJ VERTICAL TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + kfree(adj); + adj = NULL; + } else + logError(0, + "%s MS RAW ITO ADJ TEST:.................SKIPPED \n", + tag); + +ERROR: + + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (adj != NULL) { + kfree(adj); + adj = NULL; + } + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + freeLimitsFile(&limit_file); + res |= fts_system_reset(); + + if (res < OK) { + logError(1, "%s production_test_ito: ERROR %08X \n", tag, + ERROR_PROD_TEST_ITO); + res = (res | ERROR_PROD_TEST_ITO); + } + + return res; +} + +/** + * Perform the Initialization of the IC + * @param type type of initialization to do (see @link sys_special_opt Initialization Options (Full or Panel) @endlink) + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_initialization(u8 type) +{ + int res; + logError(1, "%s INITIALIZATION Production test is starting,type:%d\n", + tag, type); + + if (type != SPECIAL_PANEL_INIT && type != SPECIAL_FULL_PANEL_INIT) { + logError( + 1, + "%s production_test_initialization: Type incompatible! Type = %02X ERROR %08X \n", + tag, type, + ERROR_OP_NOT_ALLOW | ERROR_PROD_TEST_INITIALIZATION); + return (ERROR_OP_NOT_ALLOW | ERROR_PROD_TEST_INITIALIZATION); + } + + res = fts_system_reset(); + + if (res < 0) { + logError(1, "%s production_test_initialization: ERROR %08X \n", + tag, ERROR_PROD_TEST_INITIALIZATION); + return (res | ERROR_PROD_TEST_INITIALIZATION); + } + + logError(0, "%s INITIALIZATION command sent... %02X \n", tag, type); + res = writeSysCmd(SYS_CMD_SPECIAL, &type, 1); + + if (res < OK) { + logError(1, "%s production_test_initialization: ERROR %08X \n", + tag, (res | ERROR_PROD_TEST_INITIALIZATION)); + return (res | ERROR_PROD_TEST_INITIALIZATION); + } + + logError(0, "%s Refresh Sys Info...\n", tag); + res |= readSysInfo(1); + + if (res < 0) { + logError( + 1, + "%s production_test_initialization: read sys info ERROR %08X\n", + tag, ERROR_PROD_TEST_INITIALIZATION); + res = (res | ERROR_PROD_TEST_INITIALIZATION); + } + + return res; +} + +/** + * Perform a FULL (ITO + INIT + DATA CHECK) Mass Production Test of the IC + * @param pathThresholds name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param saveInit if >0 (possible values: NO_INIT, SPECIAL_PANEL_INIT or SPECIAL_FULL_PANEL_INIT), the Initialization of the IC is executed otherwise it is skipped + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_main(char *pathThresholds, int stop_on_fail, int saveInit, + TestToDo *todo) +{ + int res, ret; + logError(0, "%s MAIN Production test is starting...\n", tag); + logError(0, "%s \n", tag); + logError(0, "%s ITO TEST: \n", tag); + res = production_test_ito(pathThresholds, todo); + + if (res < 0) { + logError(0, "%s Error during ITO TEST! ERROR %08X\n", tag, res); + goto END; + } else { + logError(0, "%s ITO TEST OK!\n", tag); + } + + logError(0, "%s \n", tag); + logError(0, "%s INITIALIZATION TEST : \n", tag); + + if (saveInit != NO_INIT) { + res = production_test_initialization((u8)saveInit); + + if (res < 0) { + logError( + 0, + "%s Error during INITIALIZATION TEST! ERROR %08X\n", + tag, res); + + if (stop_on_fail) + goto END; + } else { + logError(0, "%s INITIALIZATION TEST OK!\n", tag); + } + } else + logError( + 0, + "%s INITIALIZATION TEST :................. SKIPPED \n", + tag); + + logError(0, "%s \n", tag); + + if (saveInit == 1) { + logError(0, "%s Cleaning up...\n", tag); + ret = fts_system_reset(); + + if (ret < 0) { + logError( + 1, + "%s production_test_main: system reset ERROR %08X\n", + tag, ret); + res |= ret; + + if (stop_on_fail) + goto END; + } + + logError(0, "%s \n", tag); + } + + logError(1, "%s PRODUCTION DATA TEST: \n", tag); + ret = production_test_data(pathThresholds, stop_on_fail, todo); + + if (ret < 0) { + logError(0, + "%s Error during PRODUCTION DATA TEST! ERROR %08X\n", + tag, ret); + } else { + logError(0, "%s PRODUCTION DATA TEST OK!\n", tag); + } + + res |= ret; +END: + + if (res < 0) { + logError( + 0, + "%s MAIN Production test finished.................FAILED \n", + tag); + return res; + } else { + logError( + 0, + "%s MAIN Production test finished.................OK\n", + tag); + return OK; + } +} + +/** + * Perform all the test selected in a TestTodo variable related to MS raw data (touch, keys etc..) + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ms_raw(char *path_limits, int stop_on_fail, TestToDo *todo) +{ + int ret, count_fail = 0; + MutualSenseFrame msRawFrame; + int *thresholds = NULL; + int *thresholds_min = NULL; + int *thresholds_max = NULL; + int trows, tcolumns; + u16 *adj = NULL; + /******************************* Mutual Sense Test *******************************/ + logError(0, "%s \n", tag); + + if (todo->MutualRaw == 1 || todo->MutualRawGap == 1 || + todo->MutualRawAdj == 1 || todo->MutualRawEachNode == 1) { + ret = setScanMode(SCAN_MODE_LOCKED, LOCKED_ACTIVE); + mdelay(WAIT_FOR_FRESH_FRAMES); + ret |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + ret |= getMSFrame3(MS_RAW, &msRawFrame); + + if (ret < OK) { + logError( + 1, + "%s production_test_data: getMSFrame failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + if (todo->MutualRaw == 1) { + logError(1, "%s MS RAW MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < OK || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + thresholds[0], thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax MS RAW failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS RAW MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW MIN MAX TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s MS RAW MIN MAX TEST:.................SKIPPED \n", + tag); + if (todo->MutualRawEachNode == 1) { + logError(1, "%s MS RAW EACH NODE MIN MAX TEST:\n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_EACH_NODE_MIN, + &thresholds_min, &trows, &tcolumns); + if (ret < OK || + (trows != msRawFrame.header.force_node || + tcolumns != msRawFrame.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_EACH_NODE_MIN failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_EACH_NODE_MAX, + &thresholds_max, &trows, &tcolumns); + if (ret < OK || + (trows != msRawFrame.header.force_node || + tcolumns != msRawFrame.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_EACH_NODE_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + ret = checkLimitsMapTotal(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + thresholds_min, + thresholds_max); + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMaxEachNodeData failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s MS_RAW EACH NODE MIN MAX TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail == 1) + goto ERROR; + } else { + logError( + 0, + "%s MS_RAW_EACH_NODE_MAX TEST:.................OK\n", + tag); + } + if (thresholds_min != NULL) { + kfree(thresholds_min); + thresholds_min = NULL; + } + if (thresholds_max != NULL) { + kfree(thresholds_max); + thresholds_max = NULL; + } + } else { + logError( + 0, + "%s MS RAW EACH NODE MIN MAX TEST:.................SKIPPED\n", + tag); + } + + logError(0, "%s \n", tag); + + if (todo->MutualRawGap == 1) { + logError(1, "%s MS RAW GAP TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, + &limit_file, MS_RAW_GAP, + &thresholds, &trows, + &tcolumns); + + if (ret < OK || (trows != 1 || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_GAP failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsGap(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + thresholds[0]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsGap MS RAW failed... ERROR = %08X \n", + tag, ret); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW GAP TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s MS RAW GAP TEST:.................SKIPPED \n", + tag); + + logError(0, "%s \n", tag); + + if (todo->MutualRawAdj == 1) { + logError(1, "%s MS RAW ADJ HORIZONTAL TEST: \n", tag); + ret = computeAdjHorizTotal(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + &adj); + + if (ret < OK) { + logError( + 1, + "%s production_test_data: computeAdjHoriz failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_ADJH, + &thresholds, &trows, &tcolumns); + + if (ret < OK || + (trows != msRawFrame.header.force_node || + tcolumns != msRawFrame.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_ADJH failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + adj, msRawFrame.header.force_node, + msRawFrame.header.sense_node - 1, thresholds); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsAdj MS RAW ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS RAW ADJ HORIZONTAL TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW ADJ HORIZONTAL TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + kfree(adj); + adj = NULL; + logError(0, "%s MS RAW ADJ VERTICAL TEST: \n", tag); + ret = computeAdjVertTotal(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + &adj); + + if (ret < OK) { + logError( + 1, + "%s production_test_data: computeAdjVert failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_ADJV, + &thresholds, &trows, &tcolumns); + + if (ret < OK || + (trows != msRawFrame.header.force_node - 1 || + tcolumns != msRawFrame.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_ADJV failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + adj, msRawFrame.header.force_node - 1, + msRawFrame.header.sense_node, thresholds); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsAdj MS RAW ADJV failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS RAW ADJ VERTICAL TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW ADJ VERTICAL TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + kfree(adj); + adj = NULL; + } else + logError( + 0, + "%s MS RAW ADJ TEST:.................SKIPPED \n", + tag); + } else + logError(0, "%s MS RAW FRAME TEST:.................SKIPPED \n", + tag); + + logError(0, "%s \n", tag); + + if (todo->MutualKeyRaw == 1) { + logError(1, "%s MS KEY RAW TEST:\n", tag); + ret = production_test_ms_key_raw(path_limits); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: production_test_ms_key_raw failed... ERROR = %08X \n", + tag, ret); + count_fail += 1; + + if (count_fail == 1) { + logError( + 0, + "%s MS RAW DATA TEST:.................FAIL fails_count = %d\n\n", + tag, count_fail); + goto ERROR_LIMITS; + } + } + } else + logError(0, "%s MS KEY RAW TEST:.................SKIPPED \n", + tag); + + ret = production_test_ms_raw_lp(path_limits, stop_on_fail, todo); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: production_test_ms_raw_lp failed... ERROR = %08X \n", + tag, ret); + count_fail += 1; + + if (count_fail == 1) { + logError( + 0, + "%s MS RAW DATA TEST:.................FAIL fails_count = %d\n\n", + tag, count_fail); + goto ERROR_LIMITS; + } + } + +ERROR: + logError(0, "%s \n", tag); + + if (count_fail == 0) { + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + + logError(0, + "%s MS RAW DATA TEST finished!.................OK\n", + tag); + return OK; + } else { + print_frame_short( + "MS Raw frame =", + array1dTo2d_short(msRawFrame.node_data, + msRawFrame.node_data_size, + msRawFrame.header.sense_node), + msRawFrame.header.force_node, + msRawFrame.header.sense_node); + + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (adj != NULL) { + kfree(adj); + adj = NULL; + } + logError( + 0, + "%s MS RAW DATA TEST:.................FAIL fails_count = %d\n\n", + tag, count_fail); + return (ERROR_PROD_TEST_DATA | ERROR_TEST_CHECK_FAIL); + } + +ERROR_LIMITS: + + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + return ret; +} + +/** + * Perform all the test selected in a TestTodo variable related to MS low power raw data + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ms_raw_lp(char *path_limits, int stop_on_fail, + TestToDo *todo) +{ + int ret, count_fail = 0; + MutualSenseFrame msRawFrame; + int *thresholds = NULL; + int trows, tcolumns; + u16 *adj = NULL; + memset(&msRawFrame, 0x00, sizeof(msRawFrame)); + /******************************* Mutual Sense Test *******************************/ + logError(0, "%s \n", tag); + + if (todo->MutualRawLP == 1 || todo->MutualRawGapLP == 1 || + todo->MutualRawAdjLP == 1) { + ret = setScanMode(SCAN_MODE_LOCKED, LOCKED_LP_ACTIVE); + mdelay(WAIT_FOR_FRESH_FRAMES); + ret |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + ret |= getMSFrame3(MS_RAW, &msRawFrame); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: getMSFrame failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + if (todo->MutualRawLP == 1) { + logError(1, "%s MS RAW LP MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_LP_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_LP_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + thresholds[0], thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax MS RAW LP failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS RAW LP MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW LP MIN MAX TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s MS RAW LP MIN MAX TEST:.................SKIPPED \n", + tag); + + logError(0, "%s \n", tag); + + if (todo->MutualRawGapLP == 1) { + logError(1, "%s MS RAW LP GAP TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_LP_GAP, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_LP_GAP failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsGap(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + thresholds[0]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsGap MS RAW LP failed... ERROR = %08X \n", + tag, ret); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW LP GAP TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s MS RAW LP GAP TEST:.................SKIPPED \n", + tag); + + logError(0, "%s \n", tag); + + if (todo->MutualRawAdjLP == 1) { + logError(1, "%s MS RAW LP ADJ HORIZONTAL TEST: \n", + tag); + ret = computeAdjHorizTotal(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + &adj); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_LP_ADJH, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || + (trows != msRawFrame.header.force_node || + tcolumns != msRawFrame.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_LP_ADJH failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + adj, msRawFrame.header.force_node, + msRawFrame.header.sense_node - 1, thresholds); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsAdj MS RAW LP ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS RAW LP ADJ HORIZONTAL TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW LP ADJ HORIZONTAL TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + kfree(adj); + adj = NULL; + logError(0, "%s MS RAW LP ADJ VERTICAL TEST: \n", tag); + ret = computeAdjVertTotal(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, + &adj); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_RAW_LP_ADJV, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || + (trows != msRawFrame.header.force_node - 1 || + tcolumns != msRawFrame.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_RAW_ADJV failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + adj, msRawFrame.header.force_node - 1, + msRawFrame.header.sense_node, thresholds); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsAdj MS RAW ADJV failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS RAW LP ADJ VERTICAL TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail == 1) + goto ERROR; + } else + logError( + 0, + "%s MS RAW LP ADJ VERTICAL TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + kfree(adj); + adj = NULL; + } else + logError( + 0, + "%s MS RAW LP ADJ TEST:.................SKIPPED \n", + tag); + } else + logError(0, + "%s MS RAW LP FRAME TEST:.................SKIPPED \n", + tag); + +ERROR: + logError(0, "%s \n", tag); + + if (count_fail == 0) { + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + + logError(0, + "%s MS RAW DATA TEST finished!.................OK\n", + tag); + return OK; + } else { + if (msRawFrame.node_data != NULL) { + print_frame_short( + "MS Raw LP frame =", + array1dTo2d_short(msRawFrame.node_data, + msRawFrame.node_data_size, + msRawFrame.header.sense_node), + msRawFrame.header.force_node, + msRawFrame.header.sense_node); + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (adj != NULL) { + kfree(adj); + adj = NULL; + } + logError( + 0, + "%s MS RAW LP DATA TEST:.................FAIL fails_count = %d\n\n", + tag, count_fail); + return (ERROR_PROD_TEST_DATA | ERROR_TEST_CHECK_FAIL); + } + +ERROR_LIMITS: + + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + return ret; +} + +/** + * Perform MS raw test for keys data + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ms_key_raw(char *path_limits) +{ + int ret; + MutualSenseFrame msRawFrame; + int *thresholds = NULL; + int trows, tcolumns; + /******************************* Mutual Sense Test *******************************/ + logError(1, "%s MS KEY RAW DATA TEST is starting...\n", tag); + ret = setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + ret |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + ret |= getMSFrame3(MS_KEY_RAW, &msRawFrame); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: getMSKeyFrame failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_KEY_RAW_MIN_MAX, &thresholds, &trows, + &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_KEY_RAW_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(msRawFrame.node_data, + msRawFrame.header.force_node, + msRawFrame.header.sense_node, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax MS KEY RAW failed... ERROR COUNT = %d \n", + tag, ret); + goto ERROR; + } else + logError(0, "%s MS KEY RAW TEST:.................OK \n\n", tag); + + kfree(thresholds); + thresholds = NULL; + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + return OK; +ERROR: + print_frame_short("MS Key Raw frame =", + array1dTo2d_short(msRawFrame.node_data, + msRawFrame.node_data_size, + msRawFrame.header.sense_node), + msRawFrame.header.force_node, + msRawFrame.header.sense_node); + + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + logError(0, "%s MS KEY RAW TEST:.................FAIL \n\n", tag); + return (ERROR_PROD_TEST_DATA | ERROR_TEST_CHECK_FAIL); +ERROR_LIMITS: + + if (msRawFrame.node_data != NULL) { + kfree(msRawFrame.node_data); + msRawFrame.node_data = NULL; + } + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + return ret; +} + +/** + * Perform all the tests selected in a TestTodo variable related to MS Init data (touch, keys etc..) + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ms_cx(char *path_limits, int stop_on_fail, TestToDo *todo) +{ + int ret; + int count_fail = 0; + int *thresholds = NULL; + int *thresholds_min = NULL; + int *thresholds_max = NULL; + int trows, tcolumns; + MutualSenseData msCompData; + TotMutualSenseData totCompData; + u8 *adjhor = NULL; + u8 *adjvert = NULL; + u16 container; + u16 *total_adjhor = NULL; + u16 *total_adjvert = NULL; + logError(0, "%s \n", tag); + ret = readMutualSenseCompensationData(LOAD_CX_MS_TOUCH, &msCompData); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: readMutualSenseCompensationData failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + ret = readTotMutualSenseCompensationData(LOAD_PANEL_CX_TOT_MS_TOUCH, + &totCompData); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: readTotMutualSenseCompensationData failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + kfree(msCompData.node_data); + msCompData.node_data = NULL; + return (ret | ERROR_PROD_TEST_DATA); + } + + if (todo->MutualCx1 == 1) { + logError(1, "%s MS CX1 TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX1_MIN_MAX, &thresholds, + &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX1_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + container = (u16)msCompData.cx1; + ret = checkLimitsMinMax(&container, 1, 1, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax MS CX1 failed... ERROR COUNT = %d \n", + tag, ret); + logError(0, "%s MS CX1 TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError(0, "%s MS CX1 TEST:.................OK \n\n", + tag); + } else + logError(0, "%s MS CX1 TEST:.................SKIPPED \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + + if (todo->MutualCx2 == 1) { + logError(1, "%s MS CX2 MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_MAP_MIN, &thresholds_min, + &trows, &tcolumns); + + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMap(msCompData.node_data, + msCompData.header.force_node, + msCompData.header.sense_node, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap MS CX2 MIN MAX failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS CX2 MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS CX2 MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError(0, + "%s MS CX2 MIN MAX TEST:.................SKIPPED \n\n", + tag); + + if (todo->MutualCx2Adj == 1) { + logError(1, "%s MS CX2 ADJ TEST: \n", tag); + ret = computeAdjHoriz(msCompData.node_data, + msCompData.header.force_node, + msCompData.header.sense_node, &adjhor); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s MS CX2 ADJ HORIZ computed! \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_ADJH_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_ADJH_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjhor, msCompData.header.force_node, + msCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj CX2 ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS CX2 ADJ HORIZ TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS CX2 ADJ HORIZ TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjhor); + adjhor = NULL; + logError(0, "%s MS CX2 ADJ VERT TEST: \n", tag); + ret = computeAdjVert(msCompData.node_data, + msCompData.header.force_node, + msCompData.header.sense_node, &adjvert); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s MS CX2 ADJ VERT computed! \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_ADJV_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != msCompData.header.force_node - 1 || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_ADJV_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjvert, + msCompData.header.force_node - 1, + msCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj CX2 ADJV failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS CX2 ADJ HORIZ TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS CX2 ADJ VERT TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjvert); + adjvert = NULL; + } else + logError(0, "%s MS CX2 ADJ TEST:.................SKIPPED \n\n", + tag); + + if (todo->MutualCxTotal == 1 || todo->MutualCxTotalAdj == 1) { + if (todo->MutualCxTotal == 1) { + logError(1, "%s MS TOTAL CX MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_TOTAL_CX_MAP_MIN, + &thresholds_min, &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, MS_TOTAL_CX_MAP_MAX, + &thresholds_max, &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotal(totCompData.node_data, + totCompData.header.force_node, + totCompData.header.sense_node, + thresholds_min, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap MS TOTAL CX TEST failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS TOTAL CX MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS TOTAL CX MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s MS TOTAL CX MIN MAX TEST:.................SKIPPED \n\n", + tag); + + if (todo->MutualCxTotalAdj == 1) { + logError(1, "%s MS TOTAL CX ADJ HORIZ TEST: \n", tag); + ret = computeAdjHorizTotal( + totCompData.node_data, + totCompData.header.force_node, + totCompData.header.sense_node, &total_adjhor); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s MS TOTAL CX ADJ HORIZ computed! \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + MS_TOTAL_CX_ADJH_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_ADJH_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjhor, totCompData.header.force_node, + totCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj MS TOTAL CX ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS TOTAL CX ADJ HORIZ TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS TOTAL CX ADJ HORIZ TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjhor); + total_adjhor = NULL; + logError(0, "%s MS TOTAL CX ADJ VERT TEST: \n", tag); + ret = computeAdjVertTotal(totCompData.node_data, + totCompData.header.force_node, + totCompData.header.sense_node, + &total_adjvert); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s MS TOTAL CX ADJ VERT computed! \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + MS_TOTAL_CX_ADJV_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node - 1 || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_ADJV_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjvert, + totCompData.header.force_node - 1, + totCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj MS TOTAL CX ADJV failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS TOTAL CX ADJ HORIZ TEST:.................FAIL \n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS TOTAL CX ADJ VERT TEST:.................OK \n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjvert); + total_adjvert = NULL; + } else + logError( + 0, + "%s MS TOTAL CX ADJ TEST:.................SKIPPED \n", + tag); + + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } else + logError(0, "%s MS TOTAL CX TEST:.................SKIPPED \n", + tag); + + if ((todo->MutualCx1LP | todo->MutualCx2LP | todo->MutualCx2AdjLP | + todo->MutualCxTotalLP | todo->MutualCxTotalAdjLP) == 1) { + ret = production_test_ms_cx_lp(path_limits, stop_on_fail, todo); + if (ret < OK) { + count_fail += 1; + logError( + 1, + "%s production_test_data: production_test_cx_lp failed... ERROR = %08X\n", + tag, ret); + logError( + 0, + "%s MS CX testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + return ret; + } + } else + logError(0, "%s MS KEY CX TEST:.................SKIPPED\n", + tag); + + if ((todo->MutualKeyCx1 | todo->MutualKeyCx2 | + todo->MutualKeyCxTotal) == 1) { + ret = production_test_ms_key_cx(path_limits, stop_on_fail, + todo); + + if (ret < 0) { + count_fail += 1; + logError( + 1, + "%s production_test_data: production_test_ms_key_cx failed... ERROR = %08X \n", + tag, ret); + logError( + 0, + "%s MS CX testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + return ret; + } + } else + logError(0, "%s MS KEY CX TEST:.................SKIPPED \n", + tag); + +ERROR: + logError(0, "%s \n", tag); + + if (count_fail == 0) { + logError(0, "%s MS CX testes finished!.................OK\n", + tag); + kfree(msCompData.node_data); + msCompData.node_data = NULL; + return OK; + } else { + print_frame_i8("MS Init Data (Cx2) =", + array1dTo2d_i8(msCompData.node_data, + msCompData.node_data_size, + msCompData.header.sense_node), + msCompData.header.force_node, + msCompData.header.sense_node); + print_frame_short( + " TOT MS Init Data (Cx) =", + array1dTo2d_short(totCompData.node_data, + totCompData.node_data_size, + totCompData.header.sense_node), + totCompData.header.force_node, + totCompData.header.sense_node); + logError( + 0, + "%s MS CX testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (thresholds_min != NULL) { + kfree(thresholds_min); + thresholds_min = NULL; + } + if (thresholds_max != NULL) { + kfree(thresholds_max); + thresholds_max = NULL; + } + if (adjhor != NULL) { + kfree(adjhor); + adjhor = NULL; + } + if (adjvert != NULL) { + kfree(adjvert); + adjvert = NULL; + } + if (totCompData.node_data != NULL) { + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } + if (total_adjhor != NULL) { + kfree(total_adjhor); + total_adjhor = NULL; + } + if (total_adjvert != NULL) { + kfree(total_adjvert); + total_adjvert = NULL; + } + if (msCompData.node_data != NULL) { + kfree(msCompData.node_data); + msCompData.node_data = NULL; + } + return (ERROR_TEST_CHECK_FAIL | ERROR_PROD_TEST_DATA); + } + +ERROR_LIMITS: + + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (thresholds_min != NULL) { + kfree(thresholds_min); + thresholds_min = NULL; + } + if (thresholds_max != NULL) { + kfree(thresholds_max); + thresholds_max = NULL; + } + if (adjhor != NULL) { + kfree(adjhor); + adjhor = NULL; + } + if (adjvert != NULL) { + kfree(adjvert); + adjvert = NULL; + } + if (totCompData.node_data != NULL) { + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } + if (total_adjhor != NULL) { + kfree(total_adjhor); + total_adjhor = NULL; + } + if (total_adjvert != NULL) { + kfree(total_adjvert); + total_adjvert = NULL; + } + if (msCompData.node_data != NULL) { + kfree(msCompData.node_data); + msCompData.node_data = NULL; + } + return ret; +} + +/** + * Perform all the tests selected in a TestTodo variable related to MS Init data of the keys + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ms_key_cx(char *path_limits, int stop_on_fail, + TestToDo *todo) +{ + int ret; + int count_fail = 0; + int num_keys = 0; + int *thresholds = NULL; + int *thresholds_min = NULL; + int *thresholds_max = NULL; + int trows, tcolumns; + MutualSenseData msCompData; + TotMutualSenseData totCompData; + short container; + ret = readMutualSenseCompensationData(LOAD_CX_MS_KEY, &msCompData); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: readMutualSenseCompensationData failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + if (msCompData.header.force_node > msCompData.header.sense_node) + num_keys = msCompData.header.force_node; + else + num_keys = msCompData.header.sense_node; + + if (todo->MutualKeyCx1 == 1) { + logError(1, "%s MS KEY CX1 TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_KEY_CX1_MIN_MAX, &thresholds, + &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_KEY_CX1_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + container = (short)msCompData.cx1; + ret = checkLimitsMinMax(&container, 1, 1, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax MS CX1 failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS KEY CX1 TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError(0, + "%s MS KEY CX1 TEST:.................OK \n\n", + tag); + } else + logError(0, "%s MS KEY CX1 TEST:.................SKIPPED \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + + if (todo->MutualKeyCx2 == 1) { + logError(1, "%s MS KEY CX2 TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_KEY_CX2_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_KEY_CX2_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_KEY_CX2_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_KEY_CX2_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMap(msCompData.node_data, + msCompData.header.force_node, + msCompData.header.sense_node, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap MS KEY CX2 failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS KEY CX2 TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError(0, + "%s MS KEY CX2 TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError(0, "%s MS CX2 TEST:.................SKIPPED \n\n", + tag); + + if (todo->MutualKeyCxTotal == 1) { + logError(1, "%s MS KEY TOTAL CX TEST: \n", tag); + ret = readTotMutualSenseCompensationData( + LOAD_PANEL_CX_TOT_MS_KEY, &totCompData); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeTotalCx failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_KEY_TOTAL_CX_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + + if (ret < 0 || (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_KEY_TOTAL_CX_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_KEY_TOTAL_CX_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_KEY_TOTAL_CX_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotal(totCompData.node_data, + totCompData.header.force_node, + totCompData.header.sense_node, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap MS TOTAL KEY CX TEST failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s MS KEY TOTAL CX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS KEY TOTAL CX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } else + logError(0, + "%s MS KEY TOTAL CX TEST:.................SKIPPED \n", + tag); + +ERROR: + logError(0, "%s \n", tag); + + if (count_fail == 0) { + logError(0, + "%s MS KEY CX testes finished!.................OK\n", + tag); + kfree(msCompData.node_data); + msCompData.node_data = NULL; + return OK; + } else { + print_frame_i8("MS Key Init Data (Cx2) =", + array1dTo2d_i8(msCompData.node_data, + msCompData.node_data_size, + msCompData.header.sense_node), + msCompData.header.force_node, + msCompData.header.sense_node); + logError( + 0, + "%s MS Key CX testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (thresholds_min != NULL) { + kfree(thresholds_min); + thresholds_min = NULL; + } + if (thresholds_max != NULL) { + kfree(thresholds_max); + thresholds_max = NULL; + } + if (msCompData.node_data != NULL) { + kfree(msCompData.node_data); + msCompData.node_data = NULL; + } + if (totCompData.node_data != NULL) { + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } + return (ERROR_TEST_CHECK_FAIL | ERROR_PROD_TEST_DATA); + } + +ERROR_LIMITS: + + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (thresholds_min != NULL) { + kfree(thresholds_min); + thresholds_min = NULL; + } + if (thresholds_max != NULL) { + kfree(thresholds_max); + thresholds_max = NULL; + } + if (msCompData.node_data != NULL) { + kfree(msCompData.node_data); + msCompData.node_data = NULL; + } + if (totCompData.node_data != NULL) { + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } + return ret; +} + +/** + * Perform all the tests selected in a TestTodo variable related to MS LowPower + * Init data (touch, keys etc..) + * @param path_limits name of Production Limit file to load or + * "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check + * failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error + */ +int production_test_ms_cx_lp(char *path_limits, int stop_on_fail, + TestToDo *todo) +{ + int ret; + int count_fail = 0; + + int *thresholds = NULL; + int *thresholds_min = NULL; + int *thresholds_max = NULL; + int trows, tcolumns; + + MutualSenseData msCompData; + TotMutualSenseData totCompData; + + u8 *adjhor = NULL; + + u8 *adjvert = NULL; + + u16 container; + /* u16 *total_cx = NULL; */ + u16 *total_adjhor = NULL; + u16 *total_adjvert = NULL; + + /* MS CX TEST */ + logError(0, "%s\n", tag); + + ret = readMutualSenseCompensationData(LOAD_CX_MS_LOW_POWER, + &msCompData); + /* read MS compensation data */ + if (ret < 0) { + logError( + 1, + "%s production_test_data: readMutualSenseCompensationData failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + return ret | ERROR_PROD_TEST_DATA; + } + + ret = readTotMutualSenseCompensationData(LOAD_PANEL_CX_TOT_MS_LOW_POWER, + &totCompData); + /* read TOT MS compensation data */ + if (ret < 0) { + logError( + 1, + "%s production_test_data: readTotMutualSenseCompensationData failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + kfree(msCompData.node_data); + msCompData.node_data = NULL; + return ret | ERROR_PROD_TEST_DATA; + } + + if (todo->MutualCx1LP == 1) { + logError(1, "%s MS LP CX1 TEST:\n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX1_LP_MIN_MAX, &thresholds, + &trows, &tcolumns); + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX1_LP_MIN_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + container = (u16)msCompData.cx1; + ret = checkLimitsMinMax(&container, 1, 1, thresholds[0], + thresholds[1]); + /* check the limits */ + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax MS LP CX1 failed... ERROR COUNT = %d\n", + tag, ret); + logError(0, + "%s MS LP CX1 TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError(0, "%s MS LP CX1 TEST:.................OK\n\n", + tag); + } else + logError(0, "%s MS LP CX1 TEST:.................SKIPPED\n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + + if (todo->MutualCx2LP == 1) { + logError(1, "%s MS LP CX2 MIN MAX TEST:\n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_LP_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + /* load min thresholds */ + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_LP_MAP_MIN failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_LP_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + /* load max thresholds */ + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_LP_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMap(msCompData.node_data, + msCompData.header.force_node, + msCompData.header.sense_node, + thresholds_min, thresholds_max); + /* check the limits */ + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap MS LP CX2 MIN MAX failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s MS LP CX2 MIN MAX TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS LP CX2 MIN MAX TEST:.................OK\n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s MS LP CX2 MIN MAX TEST:.................SKIPPED\n\n", + tag); + + if (todo->MutualCx2AdjLP == 1) { + logError(1, "%s MS LP CX2 ADJ TEST:\n", tag); + /* MS CX2 ADJ HORIZ */ + logError(0, "%s MS LP CX2 ADJ HORIZ TEST:\n", tag); + + ret = computeAdjHoriz(msCompData.node_data, + msCompData.header.force_node, + msCompData.header.sense_node, &adjhor); + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + logError(0, "%s MS LP CX2 ADJ HORIZ computed!\n", tag); + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_ADJH_LP_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + if (ret < 0 || (trows != msCompData.header.force_node || + tcolumns != msCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_ADJH_LP_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjhor, msCompData.header.force_node, + msCompData.header.sense_node - 1, + thresholds_max); + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj CX2 ADJH LP failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s MS LP CX2 ADJ HORIZ TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS LP CX2 ADJ HORIZ TEST:.................OK\n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjhor); + adjhor = NULL; + + /* MS CX2 ADJ VERT */ + logError(0, "%s MS LP CX2 ADJ VERT TEST:\n", tag); + + ret = computeAdjVert(msCompData.node_data, + msCompData.header.force_node, + msCompData.header.sense_node, &adjvert); + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + logError(0, "%s MS LP CX2 ADJ VERT computed!\n", tag); + + ret = parseProductionTestLimits(path_limits, &limit_file, + MS_CX2_ADJV_LP_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + if (ret < 0 || (trows != msCompData.header.force_node - 1 || + tcolumns != msCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_CX2_ADJV_LP_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjvert, + msCompData.header.force_node - 1, + msCompData.header.sense_node - 1, + thresholds_max); + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj CX2 ADJV LP failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s MS LP CX2 ADJ HORIZ TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS LP CX2 ADJ VERT TEST:.................OK\n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjvert); + adjvert = NULL; + } else + logError(0, + "%s MS LP CX2 ADJ TEST:.................SKIPPED\n\n", + tag); + + /* START OF TOTAL CHECK */ + + if (todo->MutualCxTotalLP == 1 || todo->MutualCxTotalAdjLP == 1) { + if (todo->MutualCxTotalLP == 1) { + logError(1, "%s MS TOTAL LP CX MIN MAX TEST:\n", tag); + ret = parseProductionTestLimits(path_limits, + &limit_file, + MS_TOTAL_CX_LP_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + /* load min thresholds */ + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_LP_MAP_MIN failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, + &limit_file, + MS_TOTAL_CX_LP_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + /* load max thresholds */ + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_LP_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotal(totCompData.node_data, + totCompData.header.force_node, + totCompData.header.sense_node, + thresholds_min, + thresholds_max); + /* check the limits */ + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap MS TOTAL CX LP TEST failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s MS TOTAL CX LP MIN MAX TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS TOTAL CX LP MIN MAX TEST:.................OK\n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s MS TOTAL CX LP MIN MAX TEST:.................SKIPPED\n\n", + tag); + + if (todo->MutualCxTotalAdjLP == 1) { + /* MS TOTAL CX ADJ HORIZ */ + logError(1, "%s MS TOTAL CX ADJ HORIZ LP TEST:\n", tag); + + ret = computeAdjHorizTotal( + totCompData.node_data, + totCompData.header.force_node, + totCompData.header.sense_node, &total_adjhor); + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + logError(0, "%s MS TOTAL CX ADJ HORIZ LP computed!\n", + tag); + + ret = parseProductionTestLimits( + path_limits, &limit_file, + MS_TOTAL_CX_ADJH_LP_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != totCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_ADJH_LP_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjhor, totCompData.header.force_node, + totCompData.header.sense_node - 1, + thresholds_max); + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj MS TOTAL CX ADJH LP failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s MS TOTAL CX ADJ HORIZ LP TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS TOTAL CX ADJ HORIZ LP TEST:.................OK\n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjhor); + total_adjhor = NULL; + + /* MS TOTAL CX ADJ VERT */ + logError(0, "%s MS TOTAL CX ADJ VERT LP TEST:\n", tag); + + ret = computeAdjVertTotal(totCompData.node_data, + totCompData.header.force_node, + totCompData.header.sense_node, + &total_adjvert); + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + logError(0, "%s MS TOTAL CX ADJ VERT LP computed!\n", + tag); + + ret = parseProductionTestLimits( + path_limits, &limit_file, + MS_TOTAL_CX_ADJV_LP_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + if (ret < 0 || + (trows != totCompData.header.force_node - 1 || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits MS_TOTAL_CX_ADJV_LP_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjvert, + totCompData.header.force_node - 1, + totCompData.header.sense_node - 1, + thresholds_max); + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj MS TOTAL CX ADJV failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s MS TOTAL CX ADJ HORIZ LP TEST:.................FAIL\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s MS TOTAL CX ADJ VERT LP TEST:.................OK\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjvert); + total_adjvert = NULL; + } else + logError( + 0, + "%s MS TOTAL CX ADJ LP TEST:.................SKIPPED\n", + tag); + + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } else + logError(0, "%s MS TOTAL CX LP TEST:.................SKIPPED\n", + tag); + +ERROR: + logError(0, "%s\n", tag); + if (count_fail == 0) { + logError(0, "%s MS LP CX testes finished!.................OK\n", + tag); + kfree(msCompData.node_data); + msCompData.node_data = NULL; + return OK; + } else { + print_frame_i8("MS LP Init Data (Cx2) =", + array1dTo2d_i8(msCompData.node_data, + msCompData.node_data_size, + msCompData.header.sense_node), + msCompData.header.force_node, + msCompData.header.sense_node); + print_frame_short( + " TOT MS LP Init Data (Cx) =", + array1dTo2d_short(totCompData.node_data, + totCompData.node_data_size, + totCompData.header.sense_node), + totCompData.header.force_node, + totCompData.header.sense_node); + logError( + 0, + "%s MS LP CX testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (thresholds_min != NULL) { + kfree(thresholds_min); + thresholds_min = NULL; + } + if (thresholds_max != NULL) { + kfree(thresholds_max); + thresholds_max = NULL; + } + if (adjhor != NULL) { + kfree(adjhor); + adjhor = NULL; + } + if (adjvert != NULL) { + kfree(adjvert); + adjvert = NULL; + } + if (totCompData.node_data != NULL) { + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } + if (total_adjhor != NULL) { + kfree(total_adjhor); + total_adjhor = NULL; + } + if (total_adjvert != NULL) { + kfree(total_adjvert); + total_adjvert = NULL; + } + if (msCompData.node_data != NULL) { + kfree(msCompData.node_data); + msCompData.node_data = NULL; + } + return ERROR_TEST_CHECK_FAIL | ERROR_PROD_TEST_DATA; + } + +ERROR_LIMITS: + if (thresholds != NULL) { + kfree(thresholds); + thresholds = NULL; + } + if (thresholds_min != NULL) { + kfree(thresholds_min); + thresholds_min = NULL; + } + if (thresholds_max != NULL) { + kfree(thresholds_max); + thresholds_max = NULL; + } + if (adjhor != NULL) { + kfree(adjhor); + adjhor = NULL; + } + if (adjvert != NULL) { + kfree(adjvert); + adjvert = NULL; + } + if (totCompData.node_data != NULL) { + kfree(totCompData.node_data); + totCompData.node_data = NULL; + } + if (total_adjhor != NULL) { + kfree(total_adjhor); + total_adjhor = NULL; + } + if (total_adjvert != NULL) { + kfree(total_adjvert); + total_adjvert = NULL; + } + if (msCompData.node_data != NULL) { + kfree(msCompData.node_data); + msCompData.node_data = NULL; + } + return ret; +} + +int production_test_ss_hover_raw(char *path_limits, int stop_on_fail, + TestToDo *todo) +{ + int ret; + int rows, columns; + int *thresholds = NULL; + int trows, tcolumns; + u8 hover_cnt[4] = { 0xa8, 0x0b, 0x01, 0x00 }; + + SelfSenseFrame ssHoverRawFrame; + int count_fail = 0; + + ret = fts_write_dma_safe(hover_cnt, sizeof(hover_cnt)); + if (ret != OK) { + logError(1, "%s hover clear count ERROR = %d\n", tag, ret); + goto ERROR_LIMITS; + } + + logError(0, "%s Getting SS Hover Frame...\n", tag); + ret = setScanMode(SCAN_MODE_LOCKED, LOCKED_HOVER); + msleep(WAIT_FOR_FRESH_FRAMES); + ret |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + msleep(WAIT_AFTER_SENSEOFF); + ret |= getSSFrame3(SS_HVR_RAW, &ssHoverRawFrame); + /* SS Hover RAW FORCE TEST */ + logError(0, "%s SS Hover RAW FORCE TEST:\n", tag); + + logError(0, "%s SS RAW FORCE MIN MAX TEST:\n", tag); + if (todo->SelfHoverForceRaw == 1) { + columns = 1; + rows = ssHoverRawFrame.header.force_node; + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_HOVER_RAW_FORCE_MIN_MAX, + &thresholds, &trows, &tcolumns); + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_HOVER_RAW_FORCE_MIN_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(ssHoverRawFrame.force_data, rows, + columns, thresholds[0], thresholds[1]); + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS HOVER RAW FORCE failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s SS Hover RAW FORCE MIN MAX TEST:.................FAIL\n\n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw force frame =", + array1dTo2d_short(ssHoverRawFrame.force_data, + rows * columns, columns), + rows, columns); + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW FORCE MIN MAX TEST:.................OK\n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW FORCE MIN MAX TEST:.................SKIPPED\n\n", + tag); + logError(0, "%s\n", tag); + /* SS Hover RAW SENSE TEST */ + logError(0, "%s SS Hover RAW SENSE TEST:\n", tag); + + logError(0, "%s SS RAW SENSE MIN MAX TEST:\n", tag); + if (todo->SelfHoverSenceRaw == 1) { + columns = ssHoverRawFrame.header.sense_node; + rows = 1; + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_HOVER_RAW_SENSE_MIN_MAX, + &thresholds, &trows, &tcolumns); + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_SENSE_MIN_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(ssHoverRawFrame.sense_data, rows, + columns, thresholds[0], thresholds[1]); + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS Hover RAW SENSE failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s SS Hover RAW SENSE MIN MAX TEST:.................FAIL\n", + tag); + count_fail += 1; + print_frame_short( + "SS Hover Raw sense frame =", + array1dTo2d_short(ssHoverRawFrame.sense_data, + rows * columns, columns), + rows, columns); + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS Hover RAW SENSE MIN MAX TEST:.................OK\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } + +ERROR_LIMITS: + if (ssHoverRawFrame.force_data != NULL) + kfree(ssHoverRawFrame.force_data); + if (ssHoverRawFrame.sense_data != NULL) + kfree(ssHoverRawFrame.sense_data); + if (thresholds != NULL) + kfree(thresholds); + + return ret; +} + +/** + * Perform all the test selected in a TestTodo variable related to SS raw data (touch, keys etc..) + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ss_raw(char *path_limits, int stop_on_fail, TestToDo *todo) +{ + int ret; + int count_fail = 0; + int rows, columns; + SelfSenseFrame ssRawFrame; + int *thresholds = NULL; + int trows, tcolumns; + logError(0, "%s \n", tag); + /******************************* Self Sense Test *******************************/ + logError(0, "%s Getting SS Frame... \n", tag); + ret = setScanMode(SCAN_MODE_LOCKED, LOCKED_ACTIVE); + mdelay(WAIT_FOR_FRESH_FRAMES); + ret |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + ret |= getSSFrame3(SS_RAW, &ssRawFrame); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: getSSFrame failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + if (todo->SelfForceRaw == 1 || todo->SelfForceRawGap == 1) { + columns = 1; + rows = ssRawFrame.header.force_node; + logError(0, "%s SS RAW FORCE MIN MAX TEST: \n", tag); + + if (todo->SelfForceRaw == 1) { + logError(1, "%s SS RAW FORCE MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, SS_RAW_FORCE_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_FORCE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(ssRawFrame.force_data, rows, + columns, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS RAW FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS RAW (PROXIMITY) FORCE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw force frame =", + array1dTo2d_short(ssRawFrame.force_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW (PROXIMITY) FORCE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW (PROXIMITY) FORCE MIN MAX TEST:.................SKIPPED \n\n", + tag); + + logError(0, "%s \n", tag); + + if (todo->SelfForceRawGap == 1) { + logError(1, "%s SS RAW FORCE GAP TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, SS_RAW_FORCE_GAP, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_FORCE_GAP failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsGap(ssRawFrame.force_data, rows, + columns, thresholds[0]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsGap SS RAW FORCE GAP failed... ERROR = %08X \n", + tag, ret); + logError( + 0, + "%s SS RAW FORCE GAP TEST:.................FAIL \n\n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw force frame =", + array1dTo2d_short(ssRawFrame.force_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW (PROXIMITY) FORCE GAP TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW (PROXIMITY) FORCE GAP TEST:.................SKIPPED \n\n", + tag); + + kfree(ssRawFrame.force_data); + ssRawFrame.force_data = NULL; + } else + logError( + 0, + "%s SS RAW (PROXIMITY) FORCE TEST:.................SKIPPED \n\n", + tag); + + logError(0, "%s \n", tag); + + if (todo->SelfSenseRaw == 1 || todo->SelfSenseRawGap == 1) { + columns = ssRawFrame.header.sense_node; + rows = 1; + + if (todo->SelfSenseRaw == 1) { + logError(1, "%s SS RAW SENSE MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, SS_RAW_SENSE_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_SENSE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(ssRawFrame.sense_data, rows, + columns, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS RAW SENSE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS RAW SENSE MIN MAX TEST:.................FAIL \n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw sense frame =", + array1dTo2d_short(ssRawFrame.sense_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW (PROXIMITY) SENSE MIN MAX TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW (PROXIMITY) SENSE MIN MAX TEST:.................SKIPPED \n", + tag); + + logError(0, "%s \n", tag); + + if (todo->SelfSenseRawGap == 1) { + logError(1, "%s SS RAW SENSE GAP TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, SS_RAW_SENSE_GAP, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_SENSE_GAP failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsGap(ssRawFrame.sense_data, rows, + columns, thresholds[0]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsGap SS RAW SENSE GAP failed... ERROR = %08X \n", + tag, ret); + logError( + 0, + "%s SS RAW SENSE GAP TEST:.................FAIL \n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw sense frame =", + array1dTo2d_short(ssRawFrame.sense_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW (PROXIMITY) SENSE GAP TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW (PROXIMITY) SENSE GAP TEST:.................SKIPPED \n", + tag); + + kfree(ssRawFrame.sense_data); + ssRawFrame.sense_data = NULL; + } + + ret = production_test_ss_raw_lp(path_limits, stop_on_fail, todo); + + if (ret < OK) { + logError( + 1, + "%s production_test_data: production_test_ss_raw_lp failed... ERROR = %08X \n", + tag, ret); + count_fail += 1; + } + if (todo->SelfHoverForceRaw == 1 || todo->SelfHoverSenceRaw) { + ret = production_test_ss_hover_raw(path_limits, stop_on_fail, + todo); + if (ret < OK) { + logError( + 1, + "%s production_test_data: production_test_ss_hover_raw failed... ERROR = %08X\n", + tag, ret); + count_fail += 1; + } + } + + logError(0, "%s \n", tag); + + if (count_fail == 0) { + logError(0, "%s SS RAW testes finished!.................OK\n\n", + tag); + return OK; + } else { + logError( + 0, + "%s SS RAW testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + return (ERROR_TEST_CHECK_FAIL | ERROR_PROD_TEST_DATA); + } + +ERROR_LIMITS: + + if (ssRawFrame.force_data != NULL) + kfree(ssRawFrame.force_data); + + if (ssRawFrame.sense_data != NULL) + kfree(ssRawFrame.sense_data); + + if (thresholds != NULL) + kfree(thresholds); + + return ret; +} + +/** + * Perform all the test selected in a TestTodo variable related to SS raw data low power + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ss_raw_lp(char *path_limits, int stop_on_fail, + TestToDo *todo) +{ + int ret; + int count_fail = 0; + int rows, columns; + SelfSenseFrame ssRawFrame; + int *thresholds = NULL; + int trows, tcolumns; + logError(0, "%s \n", tag); + /******************************* Self Sense Test *******************************/ + ret = setScanMode(SCAN_MODE_LOCKED, LOCKED_LP_DETECT); + mdelay(WAIT_FOR_FRESH_FRAMES); + ret |= setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + ret |= getSSFrame3(SS_RAW, &ssRawFrame); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: getSSFrame failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + if (todo->SelfForceRawLP == 1 || todo->SelfForceRawGapLP == 1) { + columns = 1; + rows = ssRawFrame.header.force_node; + + if (todo->SelfForceRawLP == 1) { + logError(1, "%s SS RAW LP FORCE MIN MAX TEST: \n", + tag); + ret = parseProductionTestLimits(path_limits, + &limit_file, + SS_RAW_LP_FORCE_MIN_MAX, + &thresholds, &trows, + &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_FORCE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(ssRawFrame.force_data, rows, + columns, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS RAW FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS RAW LP FORCE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw LP force frame =", + array1dTo2d_short(ssRawFrame.force_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW LP FORCE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW LP FORCE MIN MAX TEST:.................SKIPPED \n\n", + tag); + + logError(0, "%s \n", tag); + + if (todo->SelfForceRawGapLP == 1) { + logError(1, "%s SS RAW LP FORCE GAP TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, SS_RAW_LP_FORCE_GAP, + &thresholds, &trows, &tcolumns); + + if (ret < OK || (trows != 1 || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_FORCE_GAP failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsGap(ssRawFrame.force_data, rows, + columns, thresholds[0]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsGap SS RAW FORCE GAP failed... ERROR = %08X \n", + tag, ret); + logError( + 0, + "%s SS RAW LP FORCE GAP TEST:.................FAIL \n\n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw LP force frame =", + array1dTo2d_short(ssRawFrame.force_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW LP FORCE GAP TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW LP FORCE GAP TEST:.................SKIPPED \n\n", + tag); + + kfree(ssRawFrame.force_data); + ssRawFrame.force_data = NULL; + } else + logError( + 0, + "%s SS RAW LP FORCE TEST:.................SKIPPED \n\n", + tag); + + logError(0, "%s \n", tag); + + if (todo->SelfSenseRawLP == 1 || todo->SelfSenseRawGapLP == 1) { + columns = ssRawFrame.header.sense_node; + rows = 1; + logError(0, "%s SS RAW LP SENSE MIN MAX TEST: \n", tag); + + if (todo->SelfSenseRawLP == 1) { + logError(1, "%s SS RAW LP SENSE MIN MAX TEST: \n", + tag); + ret = parseProductionTestLimits(path_limits, + &limit_file, + SS_RAW_LP_SENSE_MIN_MAX, + &thresholds, &trows, + &tcolumns); + + if (ret < OK || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_SENSE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMinMax(ssRawFrame.sense_data, rows, + columns, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS RAW SENSE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS RAW LP SENSE MIN MAX TEST:.................FAIL \n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw LP sense frame =", + array1dTo2d_short(ssRawFrame.sense_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW SENSE MIN MAX TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW LP SENSE MIN MAX TEST:.................SKIPPED \n", + tag); + + logError(0, "%s \n", tag); + + if (todo->SelfSenseRawGapLP == 1) { + logError(1, "%s SS RAW LP SENSE GAP TEST: \n", tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, SS_RAW_LP_SENSE_GAP, + &thresholds, &trows, &tcolumns); + + if (ret < OK || (trows != 1 || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_RAW_SENSE_GAP failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsGap(ssRawFrame.sense_data, rows, + columns, thresholds[0]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsGap SS RAW SENSE GAP failed... ERROR = %08X \n", + tag, ret); + logError( + 0, + "%s SS RAW LP SENSE GAP TEST:.................FAIL \n", + tag); + count_fail += 1; + print_frame_short( + "SS Raw LP sense frame =", + array1dTo2d_short(ssRawFrame.sense_data, + rows * columns, + columns), + rows, columns); + + if (stop_on_fail) { + ret = ERROR_PROD_TEST_DATA | + ERROR_TEST_CHECK_FAIL; + goto ERROR_LIMITS; + } + } else + logError( + 0, + "%s SS RAW LP SENSE GAP TEST:.................OK \n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError( + 0, + "%s SS RAW LP SENSE GAP TEST:.................SKIPPED \n", + tag); + + kfree(ssRawFrame.sense_data); + ssRawFrame.sense_data = NULL; + } + + logError(0, "%s \n", tag); + + if (count_fail == 0) { + logError(0, + "%s SS RAW LP testes finished!.................OK\n\n", + tag); + return OK; + } else { + logError( + 0, + "%s SS RAW LP testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + return (ERROR_TEST_CHECK_FAIL | ERROR_PROD_TEST_DATA); + } + +ERROR_LIMITS: + + if (ssRawFrame.force_data != NULL) + kfree(ssRawFrame.force_data); + + if (ssRawFrame.sense_data != NULL) + kfree(ssRawFrame.sense_data); + + if (thresholds != NULL) + kfree(thresholds); + + return ret; +} + +int production_test_ss_hover_ix(char *path_limits, int stop_on_fail, + TestToDo *todo) +{ + TotSelfSenseData ssHoverCompData; + int ret; + int trows, tcolumns; + int *thresholds_min = NULL; + int *thresholds_max = NULL; + int count_fail = 0; + + /* ret = readSelfSenseCompensationData(LOAD_CX_SS_HOVER, &ssHoverCompData); */ + ret = readTotSelfSenseCompensationData( + STAPI_HOST_DATA_ID_PANEL_CX_SS_HVR, &ssHoverCompData); + /* read the SS compensation data */ + if (ret < 0) { + logError( + 1, + "%s production_test_data: readSelfSenseCompensationData failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + return ret | ERROR_PROD_TEST_DATA; + } + + logError(0, "%s SS Hover TOTAL IX FORCE TEST:\n", tag); + logError(0, "%s SS Hover TOTAL IX FORCE MIN MAX TEST:\n", tag); + if (todo->SelfHoverForceIxTotal == 1) { + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_HOVER_TOTAL_IX_FORCE_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + /* load the min thresholds */ + if (ret < 0 || (trows != ssHoverCompData.header.force_node || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_FORCE_MAP_MIN failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_TOTAL_IX_FORCE_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + /* load the max thresholds */ + if (ret < 0 || (trows != ssHoverCompData.header.force_node || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_FORCE_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotalFromU( + ssHoverCompData.ix_fm, + ssHoverCompData.header.force_node, 1, thresholds_min, + thresholds_max); + /* check the values with thresholds */ + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL IX FORCE failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s SS TOTAL IX FORCE MIN MAX TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL IX FORCE MIN MAX TEST:.................OK\n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS Hover TOTAL IX FORCE MIN MAX TEST:.................SKIPPED\n", + tag); + + logError(0, "%s SS HOVER TOTAL IX SENSE MIN MAX TEST:\n", tag); + if (todo->SelfHoverSenceIxTotal == 1) { + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_TOTAL_IX_SENSE_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + /* load the min thresholds */ + if (ret < 0 || + (trows != 1 || + tcolumns != ssHoverCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_SENSE_MAP_MIN failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_TOTAL_IX_SENSE_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + /* load the max thresholds */ + if (ret < 0 || + (trows != 1 || + tcolumns != ssHoverCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_SENSE_MAP_MAX failed... ERROR %08X\n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotalFromU( + ssHoverCompData.ix_sn, 1, + ssHoverCompData.header.sense_node, thresholds_min, + thresholds_max); + /* check the values with thresholds */ + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL IX SENSE failed... ERROR COUNT = %d\n", + tag, ret); + logError( + 0, + "%s SS Hover TOTAL IX SENSE MIN MAX TEST:.................FAIL\n\n", + tag); + count_fail += 1; + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL IX SENSE MIN MAX TEST:.................OK\n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS Hover TOTAL IX SENSE MIN MAX TEST:.................SKIPPED\n", + tag); +ERROR: + logError(0, "%s\n", tag); + if (count_fail == 0) { + kfree(ssHoverCompData.ix_fm); + ssHoverCompData.ix_fm = NULL; + kfree(ssHoverCompData.ix_sn); + ssHoverCompData.ix_sn = NULL; + kfree(ssHoverCompData.cx_fm); + ssHoverCompData.cx_fm = NULL; + kfree(ssHoverCompData.cx_sn); + ssHoverCompData.cx_sn = NULL; + logError( + 0, + "%s SS Hover IX testes finished!.................OK\n\n", + tag); + return OK; + } else { + print_frame_u16( + "TOT SS hover Init Data Ix_fm = ", + array1dTo2d_u16(ssHoverCompData.ix_fm, + ssHoverCompData.header.force_node, 1), + ssHoverCompData.header.force_node, 1); + print_frame_short( + "TOT SS hover hover Init Data Cx_fm = ", + array1dTo2d_short(ssHoverCompData.cx_fm, + ssHoverCompData.header.force_node, 1), + ssHoverCompData.header.force_node, 1); + print_frame_u16( + "TOT SS hover Init Data Ix_sn = ", + array1dTo2d_u16(ssHoverCompData.ix_sn, + ssHoverCompData.header.sense_node, + ssHoverCompData.header.sense_node), + 1, ssHoverCompData.header.sense_node); + print_frame_short( + "TOT SS hover Init Data Cx_sn = ", + array1dTo2d_short(ssHoverCompData.cx_sn, + ssHoverCompData.header.sense_node, + ssHoverCompData.header.sense_node), + 1, ssHoverCompData.header.sense_node); + logError( + 0, + "%s SS hover IX CX testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + if (thresholds_min != NULL) + kfree(thresholds_min); + if (thresholds_max != NULL) + kfree(thresholds_max); + if (ssHoverCompData.ix_fm != NULL) + kfree(ssHoverCompData.ix_fm); + if (ssHoverCompData.ix_sn != NULL) + kfree(ssHoverCompData.ix_sn); + if (ssHoverCompData.cx_fm != NULL) + kfree(ssHoverCompData.cx_fm); + if (ssHoverCompData.cx_sn != NULL) + kfree(ssHoverCompData.cx_sn); + return ERROR_TEST_CHECK_FAIL | ERROR_PROD_TEST_DATA; + } +ERROR_LIMITS: + if (thresholds_min != NULL) + kfree(thresholds_min); + if (thresholds_max != NULL) + kfree(thresholds_max); + if (ssHoverCompData.ix_fm != NULL) + kfree(ssHoverCompData.ix_fm); + if (ssHoverCompData.ix_sn != NULL) + kfree(ssHoverCompData.ix_sn); + if (ssHoverCompData.cx_fm != NULL) + kfree(ssHoverCompData.cx_fm); + if (ssHoverCompData.cx_sn != NULL) + kfree(ssHoverCompData.cx_sn); + return ret; +} + +/** + * Perform all the tests selected in a TestTodo variable related to SS Init data (touch, keys etc..) + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_ss_ix_cx(char *path_limits, int stop_on_fail, + TestToDo *todo) +{ + int ret; + int count_fail = 0; + int *thresholds = NULL; + int trows, tcolumns; + int *thresholds_min = NULL; + int *thresholds_max = NULL; + SelfSenseData ssCompData; + TotSelfSenseData totCompData; + u8 *adjhor = NULL; + u8 *adjvert = NULL; + short container; + u16 *total_adjhor = NULL; + u16 *total_adjvert = NULL; + logError(0, "%s \n", tag); + ret = readSelfSenseCompensationData(LOAD_CX_SS_TOUCH, &ssCompData); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: readSelfSenseCompensationData failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + return (ret | ERROR_PROD_TEST_DATA); + } + + ret = readTotSelfSenseCompensationData(LOAD_PANEL_CX_TOT_SS_TOUCH, + &totCompData); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: readTotSelfSenseCompensationData failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + kfree(ssCompData.ix2_fm); + kfree(ssCompData.ix2_sn); + kfree(ssCompData.cx2_fm); + kfree(ssCompData.cx2_sn); + return (ret | ERROR_PROD_TEST_DATA); + } + + /********************************************************* SS FORCE IX ****************************************************************/ + + if (todo->SelfForceIx1 == 1) { + logError(1, "%s SS IX1 FORCE TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX1_FORCE_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX1_FORCE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + container = (short)ssCompData.f_ix1; + ret = checkLimitsMinMax(&container, 1, 1, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS IX1 FORCE TEST failed... ERROR COUNT = %d \n", + tag, ret); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS IX1 FORCE TEST:.................OK \n\n", + tag); + } else + logError(0, + "%s SS IX1 FORCE TEST:.................SKIPPED \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + + if (todo->SelfForceIx2 == 1) { + logError(1, "%s SS IX2 FORCE MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX2_FORCE_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + + if (ret < 0 || + (trows != ssCompData.header.force_node || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX2_FORCE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX2_FORCE_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || + (trows != ssCompData.header.force_node || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX2_FORCE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapFromU(ssCompData.ix2_fm, + ssCompData.header.force_node, 1, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS IX2 FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS IX2 FORCE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS IX2 FORCE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS IX2 FORCE MIN MAX TEST:.................SKIPPED \n\n", + tag); + + if (todo->SelfForceIx2Adj == 1) { + logError(1, "%s SS IX2 FORCE ADJ TEST: \n", tag); + ret = computeAdjVertFromU(ssCompData.ix2_fm, + ssCompData.header.force_node, 1, + &adjvert); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert SS IX2 FORCE ADJV failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s SS IX2 FORCE ADJV computed! \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX2_FORCE_ADJV_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != ssCompData.header.force_node - 1 || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX2_FORCE_ADJV_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjvert, + ssCompData.header.force_node - 1, 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS IX2 FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS IX2 FORCE ADJV TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS IX2 FORCE ADJV TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjvert); + adjvert = NULL; + } else + logError( + 0, + "%s SS IX2 FORCE ADJ TEST:.................SKIPPED \n\n", + tag); + + if (todo->SelfForceIxTotal == 1 || todo->SelfForceIxTotalAdj == 1) { + if (todo->SelfForceIxTotal == 1) { + logError(1, "%s SS TOTAL IX FORCE MIN MAX TEST: \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_IX_FORCE_MAP_MIN, &thresholds_min, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_FORCE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_IX_FORCE_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_FORCE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotalFromU( + totCompData.ix_fm, + totCompData.header.force_node, 1, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL IX FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL IX FORCE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL IX FORCE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS TOTAL IX FORCE MIN MAX TEST:.................SKIPPED \n", + tag); + + if (todo->SelfForceIxTotalAdj == 1) { + logError(1, "%s SS TOTAL IX FORCE ADJVERT TEST: \n", + tag); + ret = computeAdjVertTotalFromU( + totCompData.ix_fm, + totCompData.header.force_node, 1, + &total_adjvert); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert SS TOTAL IX FORCE ADJV failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s SS TOTAL IX FORCE ADJV computed! \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_IX_FORCE_ADJV_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node - 1 || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_FORCE_ADJV_MAP_MAX... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjvert, + totCompData.header.force_node - 1, 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL IX FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL IX FORCE ADJV TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL IX FORCE ADJV TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjvert); + total_adjvert = NULL; + } else + logError( + 0, + "%s SS TOTAL IX FORCE ADJ TEST:.................SKIPPED \n", + tag); + } else + logError( + 0, + "%s SS TOTAL IX FORCE TEST:.................SKIPPED \n\n", + tag); + + /********************************************************* SS SENSE IX ****************************************************************/ + + if (todo->SelfSenseIx1 == 1) { + logError(1, "%s SS IX1 SENSE TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX1_SENSE_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX1_SENSE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + container = (short)ssCompData.s_ix1; + ret = checkLimitsMinMax(&container, 1, 1, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS IX1 SENSE TEST failed... ERROR COUNT = %d \n", + tag, ret); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS IX1 SENSE TEST:.................OK \n\n", + tag); + } else + logError(0, + "%s SS IX1 SENSE TEST:.................SKIPPED \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + + if (todo->SelfSenseIx2 == 1) { + logError(1, "%s SS IX2 SENSE MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX2_SENSE_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + + if (ret < 0 || + (trows != 1 || tcolumns != ssCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX2_SENSE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX2_SENSE_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || + (trows != 1 || tcolumns != ssCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX2_SENSE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapFromU(ssCompData.ix2_sn, 1, + ssCompData.header.sense_node, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS IX2 SENSE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS IX2 SENSE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS IX2 SENSE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS IX2 SENSE MIN MAX TEST:.................SKIPPED \n\n", + tag); + + if (todo->SelfSenseIx2Adj == 1) { + logError(1, "%s SS IX2 SENSE ADJHORIZ TEST: \n", tag); + ret = computeAdjHorizFromU(ssCompData.ix2_sn, 1, + ssCompData.header.sense_node, + &adjhor); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz SS IX2 SENSE ADJH failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s SS IX2 SENSE ADJ HORIZ computed! \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_IX2_SENSE_ADJH_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != 1 || + tcolumns != ssCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX2_SENSE_ADJH_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjhor, 1, + ssCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj SS IX2 SENSE ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS IX2 SENSE ADJH TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS IX2 SENSE ADJH TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjhor); + adjhor = NULL; + } else + logError( + 0, + "%s SS IX2 SENSE ADJ TEST:.................SKIPPED \n", + tag); + + if (todo->SelfSenseIxTotal == 1 || todo->SelfSenseIxTotalAdj == 1) { + if (todo->SelfSenseIxTotal == 1) { + logError(1, "%s SS TOTAL IX SENSE MIN MAX TEST: \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_IX_SENSE_MAP_MIN, &thresholds_min, + &trows, &tcolumns); + + if (ret < 0 || + (trows != 1 || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_SENSE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_IX_SENSE_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != 1 || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_SENSE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotalFromU( + totCompData.ix_sn, 1, + totCompData.header.sense_node, thresholds_min, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL IX SENSE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL IX SENSE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL IX SENSE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS TOTAL IX SENSE MIN MAX TEST:.................SKIPPED \n", + tag); + + if (todo->SelfSenseIxTotalAdj == 1) { + logError(1, "%s SS TOTAL IX SENSE ADJHORIZ TEST: \n", + tag); + ret = computeAdjHorizTotalFromU( + totCompData.ix_sn, 1, + totCompData.header.sense_node, &total_adjhor); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz SS TOTAL IX SENSE ADJH failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, + "%s SS TOTAL IX SENSE ADJ HORIZ computed! \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_IX_SENSE_ADJH_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != 1 || + tcolumns != totCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_IX_SENSE_ADJH_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjhor, 1, + totCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj SS TOTAL IX SENSE ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL IX SENSE ADJH TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL IX SENSE ADJH TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjhor); + total_adjhor = NULL; + } else + logError( + 0, + "%s SS TOTAL IX SENSE ADJ TEST:.................SKIPPED \n", + tag); + } else + logError( + 0, + "%s SS TOTAL IX SENSE TEST:.................SKIPPED \n", + tag); + + /********************************************************* SS SENSE CX ****************************************************************/ + + if (todo->SelfForceCx1 == 1) { + logError(1, "%s SS CX1 FORCE TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX1_FORCE_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_CX1_FORCE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + container = (short)ssCompData.f_cx1; + ret = checkLimitsMinMax(&container, 1, 1, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS CX1 FORCE TEST failed... ERROR COUNT = %d \n", + tag, ret); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS CX1 FORCE TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError(0, + "%s SS CX1 FORCE TEST:.................SKIPPED \n\n", + tag); + + if (todo->SelfForceCx2 == 1) { + logError(1, "%s SS CX2 FORCE MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX2_FORCE_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + + if (ret < 0 || + (trows != ssCompData.header.force_node || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_CX2_FORCE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX2_FORCE_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || + (trows != ssCompData.header.force_node || tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_CX2_FORCE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMap(ssCompData.cx2_fm, + ssCompData.header.force_node, 1, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS CX2 FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS CX2 FORCE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS CX2 FORCE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS CX2 FORCE MIN MAX TEST:.................SKIPPED \n", + tag); + + if (todo->SelfForceCx2Adj == 1) { + logError(1, "%s SS CX2 FORCE ADJVERT TEST: \n", tag); + ret = computeAdjVert(ssCompData.cx2_fm, + ssCompData.header.force_node, 1, &adjvert); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert SS CX2 FORCE ADJV failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s SS CX2 FORCE ADJV computed! \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX2_FORCE_ADJV_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != ssCompData.header.force_node - 1 || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_CX2_FORCE_ADJV_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjvert, + ssCompData.header.force_node - 1, 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS IX2 FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS CX2 FORCE ADJV TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS CX2 FORCE ADJV TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjvert); + adjvert = NULL; + } else + logError( + 0, + "%s SS CX2 FORCE ADJ TEST:.................SKIPPED \n\n", + tag); + + if (todo->SelfForceCxTotal == 1 || todo->SelfForceCxTotalAdj == 1) { + if (todo->SelfForceCxTotal == 1) { + logError(1, "%s SS TOTAL CX FORCE MIN MAX TEST: \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_CX_FORCE_MAP_MIN, &thresholds_min, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_CX_FORCE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_CX_FORCE_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_CX_FORCE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotal(totCompData.cx_fm, + totCompData.header.force_node, + 1, thresholds_min, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL FORCE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL FORCE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS TOTAL CX FORCE MIN MAX TEST:.................SKIPPED \n", + tag); + + if (todo->SelfForceCxTotalAdj == 1) { + logError(1, "%s SS TOTAL CX FORCE ADJVERT TEST: \n", + tag); + ret = computeAdjVertTotal(totCompData.cx_fm, + totCompData.header.force_node, + 1, &total_adjvert); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjVert SS TOTAL CX FORCE ADJV failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s SS TOTAL CX FORCE ADJV computed! \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_CX_FORCE_ADJV_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != totCompData.header.force_node - 1 || + tcolumns != 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_CX_FORCE_ADJV_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjvert, + totCompData.header.force_node - 1, 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL CX FORCE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL CX FORCE ADJV TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL CX FORCE ADJV TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjvert); + total_adjvert = NULL; + } else + logError( + 0, + "%s SS TOTAL CX FORCE ADJ TEST:.................SKIPPED \n", + tag); + } else + logError( + 0, + "%s SS TOTAL CX FORCE TEST:.................SKIPPED \n\n", + tag); + + /********************************************************* SS SENSE CX ****************************************************************/ + + if (todo->SelfSenseCx1 == 1) { + logError(1, "%s SS CX1 SENSE TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX1_SENSE_MIN_MAX, + &thresholds, &trows, &tcolumns); + + if (ret < 0 || (trows != 1 || tcolumns != 2)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_CX1_SENSE_MIN_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + container = (short)ssCompData.s_cx1; + ret = checkLimitsMinMax(&container, 1, 1, thresholds[0], + thresholds[1]); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMinMax SS CX1 SENSE TEST failed... ERROR COUNT = %d \n", + tag, ret); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS CX1 SENSE TEST:.................OK \n\n", + tag); + + kfree(thresholds); + thresholds = NULL; + } else + logError(0, + "%s SS CX1 SENSE TEST:.................SKIPPED \n\n", + tag); + + if (todo->SelfSenseCx2 == 1) { + logError(1, "%s SS CX2 SENSE MIN MAX TEST: \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX2_SENSE_MAP_MIN, + &thresholds_min, &trows, + &tcolumns); + + if (ret < 0 || + (trows != 1 || tcolumns != ssCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_CX2_SENSE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX2_SENSE_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || + (trows != 1 || tcolumns != ssCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_CX2_SENSE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMap(ssCompData.cx2_sn, 1, + ssCompData.header.sense_node, + thresholds_min, thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS CX2 SENSE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS CX2 SENSE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS CX2 SENSE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS CX2 SENSE MIN MAX TEST:.................SKIPPED \n", + tag); + + if (todo->SelfSenseCx2Adj == 1) { + logError(1, "%s SS CX2 SENSE ADJHORIZ TEST: \n", tag); + ret = computeAdjHoriz(ssCompData.cx2_sn, 1, + ssCompData.header.sense_node, &adjhor); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz SS CX2 SENSE ADJH failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, "%s SS CX2 SENSE ADJH computed! \n", tag); + ret = parseProductionTestLimits(path_limits, &limit_file, + SS_CX2_SENSE_ADJH_MAP_MAX, + &thresholds_max, &trows, + &tcolumns); + + if (ret < 0 || (trows != 1 || + tcolumns != ssCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_IX2_SENSE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdj(adjhor, 1, + ssCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj SS CX2 SENSE ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS CX2 SENSE ADJH TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS CX2 SENSE ADJH TEST:.................OK \n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(adjhor); + adjhor = NULL; + } else + logError( + 0, + "%s SS CX2 SENSE ADJ TEST:.................SKIPPED \n\n", + tag); + + if (todo->SelfSenseCxTotal == 1 || todo->SelfSenseCxTotalAdj == 1) { + if (todo->SelfSenseCxTotal == 1) { + logError(1, "%s SS TOTAL CX SENSE MIN MAX TEST: \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_CX_SENSE_MAP_MIN, &thresholds_min, + &trows, &tcolumns); + + if (ret < 0 || + (trows != 1 || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_CX_SENSE_MAP_MIN failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_CX_SENSE_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != 1 || + tcolumns != totCompData.header.sense_node)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_CX_SENSE_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapTotal(totCompData.cx_sn, 1, + totCompData.header.sense_node, + thresholds_min, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMap SS TOTAL CX SENSE failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL CX SENSE MIN MAX TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL CX SENSE MIN MAX TEST:.................OK \n\n", + tag); + + kfree(thresholds_min); + thresholds_min = NULL; + kfree(thresholds_max); + thresholds_max = NULL; + } else + logError( + 0, + "%s SS TOTAL CX SENSE MIN MAX TEST:.................SKIPPED \n", + tag); + + if (todo->SelfSenseCxTotalAdj == 1) { + logError(1, "%s SS TOTAL CX SENSE ADJHORIZ TEST: \n", + tag); + ret = computeAdjHorizTotal( + totCompData.cx_sn, 1, + totCompData.header.sense_node, &total_adjhor); + + if (ret < 0) { + logError( + 1, + "%s production_test_data: computeAdjHoriz SS TOTAL CX SENSE ADJH failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + logError(0, + "%s SS TOTAL CX SENSE ADJ HORIZ computed! \n", + tag); + ret = parseProductionTestLimits( + path_limits, &limit_file, + SS_TOTAL_CX_SENSE_ADJH_MAP_MAX, &thresholds_max, + &trows, &tcolumns); + + if (ret < 0 || + (trows != 1 || + tcolumns != totCompData.header.sense_node - 1)) { + logError( + 1, + "%s production_test_data: parseProductionTestLimits SS_TOTAL_CX_SENSE_ADJH_MAP_MAX failed... ERROR %08X \n", + tag, ERROR_PROD_TEST_DATA); + ret |= ERROR_PROD_TEST_DATA; + goto ERROR_LIMITS; + } + + ret = checkLimitsMapAdjTotal( + total_adjhor, 1, + totCompData.header.sense_node - 1, + thresholds_max); + + if (ret != OK) { + logError( + 1, + "%s production_test_data: checkLimitsMapAdj SS TOTAL CX SENSE ADJH failed... ERROR COUNT = %d \n", + tag, ret); + logError( + 0, + "%s SS TOTAL CX SENSE ADJH TEST:.................FAIL \n\n", + tag); + count_fail += 1; + + if (stop_on_fail) + goto ERROR; + } else + logError( + 0, + "%s SS TOTAL CX SENSE ADJH TEST:.................OK \n\n", + tag); + + kfree(thresholds_max); + thresholds_max = NULL; + kfree(total_adjhor); + total_adjhor = NULL; + } else + logError( + 0, + "%s SS TOTAL CX SENSE ADJ TEST:.................SKIPPED \n", + tag); + } else + logError( + 0, + "%s SS TOTAL CX SENSE TEST:.................SKIPPED \n", + tag); + if (todo->SelfHoverForceIxTotal == 1 || + todo->SelfHoverSenceIxTotal == 1) { + ret = production_test_ss_hover_ix(path_limits, stop_on_fail, + todo); + if (ret < OK) { + logError( + 1, + "%s production_test_data: production_test_ss_hover_ix_cx failed... ERROR = %08X\n", + tag, ret); + count_fail += 1; + } + } + +ERROR: + logError(0, "%s \n", tag); + + if (count_fail == 0) { + kfree(ssCompData.ix2_fm); + ssCompData.ix2_fm = NULL; + kfree(ssCompData.ix2_sn); + ssCompData.ix2_sn = NULL; + kfree(ssCompData.cx2_fm); + ssCompData.cx2_fm = NULL; + kfree(ssCompData.cx2_sn); + ssCompData.cx2_sn = NULL; + kfree(totCompData.ix_fm); + totCompData.ix_fm = NULL; + kfree(totCompData.ix_sn); + totCompData.ix_sn = NULL; + kfree(totCompData.cx_fm); + totCompData.cx_fm = NULL; + kfree(totCompData.cx_sn); + totCompData.cx_sn = NULL; + logError(0, + "%s SS IX CX testes finished!.................OK\n\n", + tag); + return OK; + } else { + print_frame_u8("SS Init Data Ix2_fm = ", + array1dTo2d_u8(ssCompData.ix2_fm, + ssCompData.header.force_node, 1), + ssCompData.header.force_node, 1); + print_frame_i8("SS Init Data Cx2_fm = ", + array1dTo2d_i8(ssCompData.cx2_fm, + ssCompData.header.force_node, 1), + ssCompData.header.force_node, 1); + print_frame_u8("SS Init Data Ix2_sn = ", + array1dTo2d_u8(ssCompData.ix2_sn, + ssCompData.header.sense_node, + ssCompData.header.sense_node), + 1, ssCompData.header.sense_node); + print_frame_i8("SS Init Data Cx2_sn = ", + array1dTo2d_i8(ssCompData.cx2_sn, + ssCompData.header.sense_node, + ssCompData.header.sense_node), + 1, ssCompData.header.sense_node); + print_frame_u16("TOT SS Init Data Ix_fm = ", + array1dTo2d_u16(totCompData.ix_fm, + totCompData.header.force_node, + 1), + totCompData.header.force_node, 1); + print_frame_short( + "TOT SS Init Data Cx_fm = ", + array1dTo2d_short(totCompData.cx_fm, + totCompData.header.force_node, 1), + totCompData.header.force_node, 1); + print_frame_u16("TOT SS Init Data Ix_sn = ", + array1dTo2d_u16(totCompData.ix_sn, + totCompData.header.sense_node, + totCompData.header.sense_node), + 1, totCompData.header.sense_node); + print_frame_short( + "TOT SS Init Data Cx_sn = ", + array1dTo2d_short(totCompData.cx_sn, + totCompData.header.sense_node, + totCompData.header.sense_node), + 1, totCompData.header.sense_node); + logError( + 0, + "%s SS IX CX testes finished!.................FAILED fails_count = %d\n\n", + tag, count_fail); + + if (thresholds != NULL) + kfree(thresholds); + + if (thresholds_min != NULL) + kfree(thresholds_min); + + if (thresholds_max != NULL) + kfree(thresholds_max); + + if (adjhor != NULL) + kfree(adjhor); + + if (adjvert != NULL) + kfree(adjvert); + + if (total_adjhor != NULL) + kfree(total_adjhor); + + if (total_adjvert != NULL) + kfree(total_adjvert); + + if (ssCompData.ix2_fm != NULL) + kfree(ssCompData.ix2_fm); + + if (ssCompData.ix2_sn != NULL) + kfree(ssCompData.ix2_sn); + + if (ssCompData.cx2_fm != NULL) + kfree(ssCompData.cx2_fm); + + if (ssCompData.cx2_sn != NULL) + kfree(ssCompData.cx2_sn); + + if (totCompData.ix_fm != NULL) + kfree(totCompData.ix_fm); + + if (totCompData.ix_sn != NULL) + kfree(totCompData.ix_sn); + + if (totCompData.cx_fm != NULL) + kfree(totCompData.cx_fm); + + if (totCompData.cx_sn != NULL) + kfree(totCompData.cx_sn); + + return (ERROR_TEST_CHECK_FAIL | ERROR_PROD_TEST_DATA); + } + +ERROR_LIMITS: + + if (thresholds != NULL) + kfree(thresholds); + + if (thresholds_min != NULL) + kfree(thresholds_min); + + if (thresholds_max != NULL) + kfree(thresholds_max); + + if (adjhor != NULL) + kfree(adjhor); + + if (adjvert != NULL) + kfree(adjvert); + + if (total_adjhor != NULL) + kfree(total_adjhor); + + if (total_adjvert != NULL) + kfree(total_adjvert); + + if (ssCompData.ix2_fm != NULL) + kfree(ssCompData.ix2_fm); + + if (ssCompData.ix2_sn != NULL) + kfree(ssCompData.ix2_sn); + + if (ssCompData.cx2_fm != NULL) + kfree(ssCompData.cx2_fm); + + if (ssCompData.cx2_sn != NULL) + kfree(ssCompData.cx2_sn); + + if (totCompData.ix_fm != NULL) + kfree(totCompData.ix_fm); + + if (totCompData.ix_sn != NULL) + kfree(totCompData.ix_sn); + + if (totCompData.cx_fm != NULL) + kfree(totCompData.cx_fm); + + if (totCompData.cx_sn != NULL) + kfree(totCompData.cx_sn); + + return ret; +} + +/** + * Perform a complete Data Test check of the IC + * @param path_limits name of Production Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param stop_on_fail if 1, the test flow stops at the first data check failure otherwise it keeps going performing all the selected test + * @param todo pointer to a TestToDo variable which select the test to do + * @return OK if success or an error code which specify the type of error encountered + */ +int production_test_data(char *path_limits, int stop_on_fail, TestToDo *todo) +{ + int res = OK, ret; + + if (todo == NULL) { + logError( + 1, + "%s production_test_data: No TestToDo specified!! ERROR = %08X \n", + tag, (ERROR_OP_NOT_ALLOW | ERROR_PROD_TEST_DATA)); + return (ERROR_OP_NOT_ALLOW | ERROR_PROD_TEST_DATA); + } + + logError(1, "%s DATA Production test is starting...\n", tag); + ret = production_test_ms_raw(path_limits, stop_on_fail, todo); + res |= ret; + + if (ret < 0) { + logError( + 1, + "%s production_test_data: production_test_ms_raw failed... ERROR = %08X \n", + tag, ret); + + if (stop_on_fail == 1) + goto END; + } + + ret = production_test_ms_cx(path_limits, stop_on_fail, todo); + res |= ret; + + if (ret < 0) { + logError( + 1, + "%s production_test_data: production_test_ms_cx failed... ERROR = %08X \n", + tag, ret); + + if (stop_on_fail == 1) + goto END; + } + + ret = production_test_ss_raw(path_limits, stop_on_fail, todo); + res |= ret; + + if (ret < 0) { + logError( + 1, + "%s production_test_data: production_test_ss_raw failed... ERROR = %08X \n", + tag, ret); + + if (stop_on_fail == 1) + goto END; + } + + ret = production_test_ss_ix_cx(path_limits, stop_on_fail, todo); + res |= ret; + + if (ret < 0) { + logError( + 1, + "%s production_test_data: production_test_ss_ix_cx failed... ERROR = %08X \n", + tag, ret); + + if (stop_on_fail == 1) + goto END; + } + +END: + freeLimitsFile(&limit_file); + + if (res < OK) + logError(0, "%s DATA Production test failed!\n", tag); + else + logError(0, "%s DATA Production test finished!\n", tag); + + return res; +} + +/** + * Retrieve the actual Test Limit data from the system (bin file or header file) + * @param path name of Production Test Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param file pointer to the LimitFile struct which will contains the limits data + * @return OK if success or an error code which specify the type of error encountered + */ +int getLimitsFile(char *path, LimitFile *file) +{ + const struct firmware *fw = NULL; + struct device *dev = NULL; + int fd = -1; + logError(0, "%s Get Limits File starting... %s\n", tag, path); + + if (file->data != NULL) { + logError( + 0, + "%s Pointer to Limits Data already contains something... freeing its content!\n", + tag); + kfree(file->data); + file->data = NULL; + file->size = 0; + } + + strlcpy(file->name, path, MAX_LIMIT_FILE_NAME); + + if (strncmp(path, "NULL", 4) == 0) { +#ifdef LIMITS_H_FILE + logError(0, "%s Loading Limits File from .h!\n", tag); + file->size = LIMITS_SIZE_NAME; + file->data = (char *)kmalloc((file->size) * sizeof(char), + GFP_KERNEL); + + if (file->data != NULL) { + memcpy(file->data, (char *)(LIMITS_ARRAY_NAME), + file->size); + return OK; + } else { + logError( + 1, + "%s Error while allocating data... ERROR %08X \n", + tag, path, ERROR_ALLOC); + return ERROR_ALLOC; + } + +#else + logError(1, "%s limit file path NULL... ERROR %08X \n", tag, + ERROR_FILE_NOT_FOUND); + return ERROR_FILE_NOT_FOUND; +#endif + } else { + dev = getDev(); + + if (dev != NULL) { + logError(0, "%s Loading Limits File from .csv!\n", tag); + fd = request_firmware(&fw, path, dev); + + if (fd == 0) { + logError(0, "%s Start to copy %s...\n", tag, + path); + file->size = fw->size; + file->data = (char *)kmalloc( + (file->size) * sizeof(char), + GFP_KERNEL); + + if (file->data != NULL) { + memcpy(file->data, (char *)fw->data, + file->size); + logError(0, + "%s Limit file Size = %d \n", + tag, file->size); + release_firmware(fw); + return OK; + } else { + logError( + 1, + "%s Error while allocating data... ERROR %08X \n", + tag, path, ERROR_ALLOC); + release_firmware(fw); + return ERROR_ALLOC; + } + } else { + logError( + 1, + "%s Request the file %s failed... ERROR %08X \n", + tag, path, ERROR_FILE_NOT_FOUND); + return ERROR_FILE_NOT_FOUND; + } + } else { + logError( + 1, + "%s Error while getting the device ERROR %08X \n", + tag, ERROR_FILE_READ); + return ERROR_FILE_READ; + } + } +} + +/** + * Reset and release the memory which store a Production Limit File previously loaded + * @param file pointer to the LimitFile struct to free + * @return OK if success or an error code which specify the type of error encountered + */ + +int freeLimitsFile(LimitFile *file) +{ + logError(0, "%s Freeing Limit File ...\n", tag); + + if (file != NULL) { + if (file->data != NULL) { + kfree(file->data); + file->data = NULL; + } else + logError(0, "%s Limit File was already freed!\n", tag); + + file->size = 0; + strlcpy(file->name, " ", MAX_LIMIT_FILE_NAME); + return OK; + } else { + logError(1, "%s Passed a NULL argument! ERROR %08X \n", tag, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} + +/** + * Reset and release the memory which store the current Limit File previously loaded + * @return OK if success or an error code which specify the type of error encountered + */ + +int freeCurrentLimitsFile(void) +{ + return freeLimitsFile(&limit_file); +} + +/** + * Parse the raw data read from a Production test limit file in order to find the specified information + * If no limits file data are passed, the function loads and stores the limit file from the system + * @param path name of Production Test Limit file to load or "NULL" if the limits data should be loaded by a .h file + * @param file pointer to LimitFile struct that should be parsed or NULL if the limit file in the system should be loaded and then parsed + * @param label string which identify a particular set of data in the file that want to be loaded + * @param data pointer to the pointer which will contains the specified limits data as 1 dimension matrix with data arranged row after row + * @param row pointer to a int variable which will contain the number of row of data + * @param column pointer to a int variable which will contain the number of column of data + * @return OK if success or an error code which specify the type of error encountered + */ +int parseProductionTestLimits(char *path, LimitFile *file, char *label, + int **data, int *row, int *column) +{ + int find = 0; + char *token = NULL; + int i = 0; + int j = 0; + int z = 0; + char *line2 = NULL; + char line[800]; + char *buf = NULL; + int n, size, pointer = 0, ret = OK; + char *data_file = NULL; + + if (file == NULL || strcmp(path, file->name) != 0 || file->size == 0) { + logError( + 0, + "%s No limit File data passed... try to get them from the system!\n", + tag); + ret = getLimitsFile(LIMITS_FILE, &limit_file); + + if (ret < OK) { + logError(1, + "%s parseProductionTestLimits: ERROR %08X\n", + tag, ERROR_FILE_NOT_FOUND); + return ERROR_FILE_NOT_FOUND; + } + + size = limit_file.size; + data_file = limit_file.data; + } else { + logError(0, "%s Limit File data passed as arguments!\n", tag); + size = file->size; + data_file = file->data; + } + + logError(0, "%s The size of the limits file is %d bytes...\n", tag, + size); + + while (find == 0) { + if (readLine(&data_file[pointer], line, size - pointer, &n) < + 0) { + find = -1; + break; + } + + pointer += n; + + if (line[0] == '*') { + line2 = kstrdup(line, GFP_KERNEL); + + if (line2 == NULL) { + logError( + 1, + "%s parseProductionTestLimits: kstrdup ERROR %08X\n", + tag, ERROR_ALLOC); + ret = ERROR_ALLOC; + goto END; + } + + buf = line2; + line2 += 1; + token = strsep(&line2, ","); + + if (strcmp(token, label) == 0) { + find = 1; + token = strsep(&line2, ","); + + if (token != NULL) { + sscanf(token, "%d", row); + logError(0, "%s Row = %d\n", tag, *row); + } else { + logError( + 1, + "%s parseProductionTestLimits 1: ERROR %08X\n", + tag, ERROR_FILE_PARSE); + ret = ERROR_FILE_PARSE; + goto END; + } + + token = strsep(&line2, ","); + + if (token != NULL) { + sscanf(token, "%d", column); + logError(0, "%s Column = %d\n", tag, + *column); + } else { + logError( + 1, + "%s parseProductionTestLimits 2: ERROR %08X\n", + tag, ERROR_FILE_PARSE); + ret = ERROR_FILE_PARSE; + goto END; + } + + kfree(buf); + buf = NULL; + *data = (int *)kmalloc(((*row) * (*column)) * + sizeof(int), + GFP_KERNEL); + j = 0; + + if (*data == NULL) { + logError( + 1, + "%s parseProductionTestLimits: ERROR %08X\n", + tag, ERROR_ALLOC); + ret = ERROR_ALLOC; + goto END; + } + + for (i = 0; i < *row; i++) { + if (readLine(&data_file[pointer], line, + size - pointer, &n) < 0) { + logError( + 1, + "%s parseProductionTestLimits : ERROR %08X\n", + tag, ERROR_FILE_READ); + ret = ERROR_FILE_READ; + goto END; + } + + pointer += n; + line2 = kstrdup(line, GFP_KERNEL); + + if (line2 == NULL) { + logError( + 1, + "%s parseProductionTestLimits: kstrdup ERROR %08X\n", + tag, ERROR_ALLOC); + ret = ERROR_ALLOC; + goto END; + } + + buf = line2; + token = strsep(&line2, ","); + + for (z = 0; + (z < *column) && (token != NULL); + z++) { + sscanf(token, "%d", + ((*data) + j)); + j++; + token = strsep(&line2, ","); + } + + kfree(buf); + buf = NULL; + } + + if (j == ((*row) * (*column))) { + logError(0, "%s READ DONE!\n", tag); + ret = OK; + goto END; + } + + logError( + 1, + "%s parseProductionTestLimits 3: ERROR %08X\n", + tag, ERROR_FILE_PARSE); + ret = ERROR_FILE_PARSE; + goto END; + } + + kfree(buf); + buf = NULL; + } + } + + logError(1, "%s parseProductionTestLimits: ERROR %08X\n", tag, + ERROR_LABEL_NOT_FOUND); + ret = ERROR_LABEL_NOT_FOUND; +END: + + if (buf != NULL) + kfree(buf); + + return ret; +} + +/** + * Read one line of a text file passed as array of byte and terminate it with a termination character '\0' + * @param data text file as array of bytes + * @param line pointer to an array of char that will contain the line read + * @param size size of data + * @param n pointer to a int variable which will contain the number of characters of the line + * @return OK if success or an error code which specify the type of error encountered + */ +int readLine(char *data, char *line, int size, int *n) +{ + int i = 0; + + if (size < 1) + return -EINVAL; + + while (data[i] != '\n' && i < size) { + line[i] = data[i]; + i++; + } + + *n = i + 1; + line[i] = '\0'; + return OK; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.h new file mode 100644 index 000000000000..7e71bb6b4e42 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTest.h @@ -0,0 +1,304 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS API for MP test * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsTest.h +* \brief Contains all the definitions and structs related to the Mass Production Test +*/ + +#ifndef FTS_TEST_H +#define FTS_TEST_H + +#include "ftsSoftware.h" + +#ifndef LIMITS_H_FILE +#define LIMITS_FILE \ + "stm_fts_production_limits.csv" /*Name of the Production Test Limit File*/ +#else +#define LIMITS_FILE "NULL" +#endif + +#define WAIT_FOR_FRESH_FRAMES \ + 200 /*Time in ms to wait after start to sensing before reading a frame*/ +#define WAIT_AFTER_SENSEOFF \ + 50 /*Time in ms to wait after stop sensing and before reading a frame from memory*/ + +#define NO_INIT 0 /*No Initialization required during the MP*/ + +#define RETRY_INIT_BOOT \ + 3 /*number of retry of the initialization process at boot*/ + +/** @defgroup mp_test Mass Production Test + * Mass production test API. + * Mass Production Test (MP) should be executed at least one time in the life of every device \n + * It used to verify that tit is not present any hardware damage and initialize some value of the chip in order to guarantee the working performance \n + * The MP test is made up by 3 steps: + * - ITO test = production_test_ito() \n + * - Initialization = production_test_initialization() \n + * - Data Test = production_test_data(), it is possible to select which items test thanks to the TestToDo struct\n + * To execute the Data Test it is mandatory load some thresholds that are stored in the Limit File. + * @{ + */ + +/** @defgroup limit_file Limit File + * @ingroup mp_test + * Production Test Limit File is a csv which contains thresholds of the data to test. + * This file can be loaded from the file system or stored as a header file according to the LIMITS_H_FILE define \n + * For each selectable test item there can be one or more associated labels which store the corresponding thresholds \n + * @{ + */ + +/** @defgroup test_labels Test Items Labels + * @ingroup limit_file + * Labels present in the Limit File and associated to the test items of TestToDo + * @{ + */ +#define MS_RAW_MIN_MAX "MS_RAW_DATA_MIN_MAX" +#define MS_RAW_EACH_NODE_MIN "MS_RAW_DATA_EACH_MIN" +#define MS_RAW_EACH_NODE_MAX "MS_RAW_DATA_EACH_MAX" +#define MS_RAW_GAP "MS_RAW_DATA_GAP" +#define MS_RAW_ADJH "MS_RAW_DATA_ADJ_HORIZONTAL" +#define MS_RAW_ADJV "MS_RAW_DATA_ADJ_VERTICAL" +#define MS_RAW_ITO_ADJH "MS_RAW_ITO_DATA_ADJ_HORIZONTAL" +#define MS_RAW_ITO_ADJV "MS_RAW_ITO_DATA_ADJ_VERTICAL" +#define MS_RAW_LP_MIN_MAX "MS_RAW_LOWPOWER_DATA_MIN_MAX" +#define MS_RAW_LP_GAP "MS_RAW_LOWPOWER_DATA_GAP" +#define MS_RAW_LP_ADJH "MS_RAW_LOWPOWER_DATA_ADJ_HORIZONTAL" +#define MS_RAW_LP_ADJV "MS_RAW_LOWPOWER_DATA_ADJ_VERTICAL" +#define MS_CX1_MIN_MAX "MS_TOUCH_ACTIVE_CX1_MIN_MAX" +#define MS_CX2_MAP_MIN "MS_TOUCH_ACTIVE_CX2_MIN" +#define MS_CX2_MAP_MAX "MS_TOUCH_ACTIVE_CX2_MAX" +#define MS_CX2_ADJH_MAP_MAX "MS_TOUCH_ACTIVE_CX2_ADJ_HORIZONTAL" +#define MS_CX2_ADJV_MAP_MAX "MS_TOUCH_ACTIVE_CX2_ADJ_VERTICAL" +#define MS_TOTAL_CX_MAP_MIN "MS_TOUCH_ACTIVE_TOTAL_CX_MIN" +#define MS_TOTAL_CX_MAP_MAX "MS_TOUCH_ACTIVE_TOTAL_CX_MAX" +#define MS_TOTAL_CX_ADJH_MAP_MAX "MS_TOUCH_ACTIVE_TOTAL_CX_ADJ_HORIZONTAL" +#define MS_TOTAL_CX_ADJV_MAP_MAX "MS_TOUCH_ACTIVE_TOTAL_CX_ADJ_VERTICAL" +#define MS_CX1_LP_MIN_MAX "MS_TOUCH_LOWPOWER_CX1_MIN_MAX" +#define MS_CX2_LP_MAP_MIN "MS_TOUCH_LOWPOWER_CX2_MIN" +#define MS_CX2_LP_MAP_MAX "MS_TOUCH_LOWPOWER_CX2_MAX" +#define MS_CX2_ADJH_LP_MAP_MAX "MS_TOUCH_LOWPOWER_CX2_ADJ_HORIZONTAL" +#define MS_CX2_ADJV_LP_MAP_MAX "MS_TOUCH_LOWPOWER_CX2_ADJ_VERTICAL" +#define MS_TOTAL_CX_LP_MAP_MIN "MS_TOUCH_LOWPOWER_TOTAL_CX_MIN" +#define MS_TOTAL_CX_LP_MAP_MAX "MS_TOUCH_LOWPOWER_TOTAL_CX_MAX" +#define MS_TOTAL_CX_ADJH_LP_MAP_MAX "MS_TOUCH_LOWPOWER_TOTAL_CX_ADJ_HORIZONTAL" +#define MS_TOTAL_CX_ADJV_LP_MAP_MAX "MS_TOUCH_LOWPOWER_TOTAL_CX_ADJ_VERTICAL" +#define SS_RAW_FORCE_MIN_MAX "SS_RAW_DATA_FORCE_MIN_MAX" +#define SS_RAW_SENSE_MIN_MAX "SS_RAW_DATA_SENSE_MIN_MAX" +#define SS_RAW_FORCE_GAP "SS_RAW_DATA_FORCE_GAP" +#define SS_RAW_SENSE_GAP "SS_RAW_DATA_SENSE_GAP" +#define SS_RAW_LP_FORCE_MIN_MAX "SS_RAW_LOWPOWER_DATA_FORCE_MIN_MAX" +#define SS_RAW_LP_SENSE_MIN_MAX "SS_RAW_LOWPOWER_DATA_SENSE_MIN_MAX" +#define SS_RAW_LP_FORCE_GAP "SS_RAW_LOWPOWER_DATA_FORCE_GAP" +#define SS_RAW_LP_SENSE_GAP "SS_RAW_LOWPOWER_DATA_SENSE_GAP" +#define SS_IX1_FORCE_MIN_MAX "SS_TOUCH_ACTIVE_IX1_FORCE_MIN_MAX" +#define SS_IX1_SENSE_MIN_MAX "SS_TOUCH_ACTIVE_IX1_SENSE_MIN_MAX" +#define SS_CX1_FORCE_MIN_MAX "SS_TOUCH_ACTIVE_CX1_FORCE_MIN_MAX" +#define SS_CX1_SENSE_MIN_MAX "SS_TOUCH_ACTIVE_CX1_SENSE_MIN_MAX" +#define SS_IX2_FORCE_MAP_MIN "SS_TOUCH_ACTIVE_IX2_FORCE_MIN" +#define SS_IX2_FORCE_MAP_MAX "SS_TOUCH_ACTIVE_IX2_FORCE_MAX" +#define SS_IX2_SENSE_MAP_MIN "SS_TOUCH_ACTIVE_IX2_SENSE_MIN" +#define SS_IX2_SENSE_MAP_MAX "SS_TOUCH_ACTIVE_IX2_SENSE_MAX" +#define SS_IX2_FORCE_ADJV_MAP_MAX "SS_TOUCH_ACTIVE_IX2_ADJ_VERTICAL" +#define SS_IX2_SENSE_ADJH_MAP_MAX "SS_TOUCH_ACTIVE_IX2_ADJ_HORIZONTAL" +#define SS_CX2_FORCE_MAP_MIN "SS_TOUCH_ACTIVE_CX2_FORCE_MIN" +#define SS_CX2_FORCE_MAP_MAX "SS_TOUCH_ACTIVE_CX2_FORCE_MAX" +#define SS_CX2_SENSE_MAP_MIN "SS_TOUCH_ACTIVE_CX2_SENSE_MIN" +#define SS_CX2_SENSE_MAP_MAX "SS_TOUCH_ACTIVE_CX2_SENSE_MAX" +#define SS_CX2_FORCE_ADJV_MAP_MAX "SS_TOUCH_ACTIVE_CX2_ADJ_VERTICAL" +#define SS_CX2_SENSE_ADJH_MAP_MAX "SS_TOUCH_ACTIVE_CX2_ADJ_HORIZONTAL" + +#define SS_TOTAL_IX_FORCE_MAP_MIN "SS_TOUCH_ACTIVE_TOTAL_IX_FORCE_MIN" +#define SS_TOTAL_IX_FORCE_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_IX_FORCE_MAX" +#define SS_TOTAL_IX_SENSE_MAP_MIN "SS_TOUCH_ACTIVE_TOTAL_IX_SENSE_MIN" +#define SS_TOTAL_IX_SENSE_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_IX_SENSE_MAX" +#define SS_TOTAL_IX_FORCE_ADJV_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_IX_ADJ_VERTICAL" +#define SS_TOTAL_IX_SENSE_ADJH_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_IX_ADJ_HORIZONTAL" +#define SS_TOTAL_CX_FORCE_MAP_MIN "SS_TOUCH_ACTIVE_TOTAL_CX_FORCE_MIN" +#define SS_TOTAL_CX_FORCE_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_CX_FORCE_MAX" +#define SS_TOTAL_CX_SENSE_MAP_MIN "SS_TOUCH_ACTIVE_TOTAL_CX_SENSE_MIN" +#define SS_TOTAL_CX_SENSE_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_CX_SENSE_MAX" +#define SS_TOTAL_CX_FORCE_ADJV_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_CX_ADJ_VERTICAL" +#define SS_TOTAL_CX_SENSE_ADJH_MAP_MAX "SS_TOUCH_ACTIVE_TOTAL_CX_ADJ_HORIZONTAL" + +#define MS_KEY_RAW_MIN_MAX "MS_KEY_RAW_DATA_MIN_MAX" +#define MS_KEY_CX1_MIN_MAX "MS_KEY_CX1_MIN_MAX" +#define MS_KEY_CX2_MAP_MIN "MS_KEY_CX2_MIN" +#define MS_KEY_CX2_MAP_MAX "MS_KEY_CX2_MAX" +#define MS_KEY_TOTAL_CX_MAP_MIN "MS_KEY_TOTAL_CX_MIN" +#define MS_KEY_TOTAL_CX_MAP_MAX "MS_KEY_TOTAL_CX_MAX" + +#define SS_IX1_FORCE_W "IX1_FORCE_W" +#define SS_IX2_FORCE_W "IX2_FORCE_W" +#define SS_IX1_SENSE_W "IX1_SENSE_W" +#define SS_IX2_SENSE_W "IX2_SENSE_W" + +/* SS HOVER*/ +#define SS_HOVER_RAW_FORCE_MIN_MAX "SS_RAW_HOVER_DATA_FORCE_MIN_MAX" +#define SS_HOVER_TOTAL_IX_FORCE_MAP_MIN "SS_HOVER_TOTAL_IX_FORCE_MIN" +#define SS_HOVER_TOTAL_IX_FORCE_MAP_MAX "SS_HOVER_TOTAL_IX_FORCE_MAX" +#define SS_HOVER_RAW_SENSE_MIN_MAX "SS_RAW_HOVER_DATA_SENSE_MIN_MAX" +#define SS_HOVER_TOTAL_IX_SENSE_MAP_MIN "SS_HOVER_TOTAL_IX_SENSE_MIN" +#define SS_HOVER_TOTAL_IX_SENSE_MAP_MAX "SS_HOVER_TOTAL_IX_SENSE_MAX" + +/** @}*/ + +/** +* Struct used to specify which test perform during the Mass Production Test. +* For each test item selected in this structure, there should be one or more labels associated in the Limit file from where load the thresholds +*/ +typedef struct { + int MutualRaw; /*MS Raw min/Max test*/ + int MutualRawEachNode; + int MutualRawGap; /*MS Raw Gap(max-min) test*/ + int MutualRawAdj; /*MS Raw Adjacent test*/ + int MutualRawLP; /*MS Low Power Raw min/Max test*/ + int MutualRawGapLP; /*MS Low Power Raw Gap(max-min) test*/ + int MutualRawAdjLP; /*MS Low Power Raw Adjacent test*/ + int MutualRawAdjITO; /*MS Raw Adjacent test during ITO test*/ + + int MutualCx1; /*MS Cx1 min/Max test*/ + int MutualCx2; /*MS Cx2 min/Max (for each node) test*/ + int MutualCx2Adj; /*MS Vertical and Horizontal Adj Cx2 min/Max (for each node) test*/ + int MutualCxTotal; /*MS Total Cx min/Max (for each node) test*/ + int MutualCxTotalAdj; /*MS Total vertical and Horizontal Adj Cx2 min/Max (for each node) test*/ + int MutualCx1LP; /* /< MS LowPower Cx1 min/Max test */ + int MutualCx2LP; /* /< MS LowPower Cx2 min/Max (for each node) test */ + int MutualCx2AdjLP; /* /< MS LowPower Vertical and Horizontal Adj Cx2 min/Max + * (for each node) test */ + int MutualCxTotalLP; /* /< MS Total LowPower Cx min/Max (for each node) test + * */ + int MutualCxTotalAdjLP; /* /< MS Total LowPower vertical and Horizontal Adj Cx2 + * min/Max (for each node) test */ + + int MutualKeyRaw; /*MS Raw Key min/Max test*/ + int MutualKeyCx1; /*MS Cx1 Key min/Max test*/ + int MutualKeyCx2; /*MS Cx2 Key min/Max (for each node) test*/ + int MutualKeyCxTotal; /*MS Total Cx Key min/Max (for each node) test*/ + + int SelfHoverForceRaw; /* SS Hover Force Raw min/Max test */ + int SelfHoverSenceRaw; /*SS Hover Sence Raw min/Max test */ + int SelfHoverForceIxTotal; /*SS Hover Total Force Ix min/Max (for each node)* test */ + int SelfHoverSenceIxTotal; /*SS Hover Total Sence Ix min/Max (for each node)* test */ + + int SelfForceRaw; /*SS Force Raw min/Max test*/ + int SelfForceRawGap; /*SS Force Raw Gap(max-min) test*/ + int SelfForceRawLP; /*SS Low Power Force Raw min/Max test*/ + int SelfForceRawGapLP; /*SS Low Power Force Raw Gap(max-min) test*/ + + int SelfForceIx1; /*SS Force Ix1 min/Max test*/ + int SelfForceIx2; /*SS Force Ix2 min/Max (for each node) test*/ + int SelfForceIx2Adj; /*SS Vertical Adj Force Ix2 min/Max (for each node) test*/ + int SelfForceIxTotal; /*SS Total Force Ix min/Max (for each node) test*/ + int SelfForceIxTotalAdj; /*SS Total Vertical Adj Force Ix min/Max (for each node) test*/ + int SelfForceCx1; /*SS Force Cx1 min/Max test*/ + int SelfForceCx2; /*SS Force Cx2 min/Max (for each node) test*/ + int SelfForceCx2Adj; /*SS Vertical Adj Force Cx2 min/Max (for each node) test*/ + int SelfForceCxTotal; /*SS Total Force Cx min/Max (for each node) test*/ + int SelfForceCxTotalAdj; /*SS Total Vertical Adj Force Cx min/Max (for each node) test*/ + + int SelfSenseRaw; /*SS Sense Raw min/Max test*/ + int SelfSenseRawGap; /*SS Sense Raw Gap(max-min) test*/ + int SelfSenseRawLP; /*SS Low Power Sense Raw min/Max test*/ + int SelfSenseRawGapLP; /*SS Low Power Sense Raw Gap(max-min) test*/ + + int SelfSenseIx1; /*SS Sense Ix1 min/Max test*/ + int SelfSenseIx2; /*SS Sense Ix2 min/Max (for each node) test*/ + int SelfSenseIx2Adj; /*SS Horizontal Adj Sense Ix2 min/Max (for each node) test*/ + int SelfSenseIxTotal; /*SS Total Horizontal Sense Ix min/Max (for each node) test*/ + int SelfSenseIxTotalAdj; /*SS Total Horizontal Adj Sense Ix min/Max (for each node) test*/ + int SelfSenseCx1; /*SS Sense Cx1 min/Max test*/ + int SelfSenseCx2; /*SS Sense Cx2 min/Max (for each node) test*/ + int SelfSenseCx2Adj; /*SS Horizontal Adj Sense Cx2 min/Max (for each node) test*/ + int SelfSenseCxTotal; /*SS Total Sense Cx min/Max (for each node) test*/ + int SelfSenseCxTotalAdj; /*SS Total Horizontal Adj Sense Cx min/Max (for each node) test*/ + +} TestToDo; + +#define MAX_LIMIT_FILE_NAME 100 /*max number of chars of the limit file name*/ + +/** + * Struct which store the data coming from a Production Limit File + */ +typedef struct { + char *data; + int size; + char name[MAX_LIMIT_FILE_NAME]; +} LimitFile; + +int initTestToDo(void); +/**@}*/ + +/**@}*/ + +int computeAdjHoriz(i8 *data, int row, int column, u8 **result); +int computeAdjHorizTotal(short *data, int row, int column, u16 **result); +int computeAdjVert(i8 *data, int row, int column, u8 **result); +int computeAdjVertTotal(short *data, int row, int column, u16 **result); +int computeAdjHorizFromU(u8 *data, int row, int column, u8 **result); +int computeAdjHorizTotalFromU(u16 *data, int row, int column, u16 **result); +int computeAdjVertFromU(u8 *data, int row, int column, u8 **result); +int computeAdjVertTotalFromU(u16 *data, int row, int column, u16 **result); +int checkLimitsMinMax(short *data, int row, int column, int min, int max); +int checkLimitsMap(i8 *data, int row, int column, int *min, int *max); +int checkLimitsMapTotal(short *data, int row, int column, int *min, int *max); +int checkLimitsMapFromU(u8 *data, int row, int column, int *min, int *max); +int checkLimitsMapTotalFromU(u16 *data, int row, int column, int *min, + int *max); +int checkLimitsMapAdj(u8 *data, int row, int column, int *max); +int checkLimitsMapAdjTotal(u16 *data, int row, int column, int *max); + +/** @defgroup mp_api MP API + * @ingroup mp_test + * Functions to execute the MP test. + * The parameters of these functions allow to customize their behavior in order to satisfy different scenarios + * @{ + */ +int production_test_ito(char *path_limits, TestToDo *todo); +int production_test_initialization(u8 type); +int production_test_main(char *pathThresholds, int stop_on_fail, int saveInit, + TestToDo *todo); +int production_test_ms_raw(char *path_limits, int stop_on_fail, TestToDo *todo); +int production_test_ms_raw_lp(char *path_limits, int stop_on_fail, + TestToDo *todo); +int production_test_ms_cx(char *path_limits, int stop_on_fail, TestToDo *todo); +int production_test_ms_cx_lp(char *path_limits, int stop_on_fail, + TestToDo *todo); +int production_test_ss_raw(char *path_limits, int stop_on_fail, TestToDo *todo); +int production_test_ss_raw_lp(char *path_limits, int stop_on_fail, + TestToDo *todo); +int production_test_ss_ix_cx(char *path_limits, int stop_on_fail, + TestToDo *todo); +int production_test_data(char *path_limits, int stop_on_fail, TestToDo *todo); +int production_test_ms_key_cx(char *path_limits, int stop_on_fail, + TestToDo *todo); +int production_test_ms_key_raw(char *path_limits); +int computeTotal(u8 *data, u8 main, int row, int column, int m, int n, + u16 **result); +/** @}*/ + +/** + * @addtogroup limit_file + * @{ + */ +int parseProductionTestLimits(char *path, LimitFile *file, char *label, + int **data, int *row, int *column); +int readLine(char *data, char *line, int size, int *n); +int getLimitsFile(char *path, LimitFile *file); +int freeLimitsFile(LimitFile *file); +int freeCurrentLimitsFile(void); +/**@}*/ + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.c new file mode 100644 index 000000000000..29b0f99adb81 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.c @@ -0,0 +1,78 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS Utility for mesuring/handling the time * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsTime.c +* \brief Contains all functions to handle and measure the time in the driver +*/ + +#include "ftsTime.h" + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** +* Take the starting time and save it in a StopWatch variable +* @param w pointer of a StopWatch struct +*/ +void startStopWatch(StopWatch *w) +{ + w->start = current_kernel_time(); +} + +/** +* Take the stop time and save it in a StopWatch variable +* @param w pointer of a StopWatch struct +*/ +void stopStopWatch(StopWatch *w) +{ + w->end = current_kernel_time(); +} + +/** +* Compute the amount of time spent from when the startStopWatch and then the stopStopWatch were called on the StopWatch variable +* @param w pointer of a StopWatch struct +* @return amount of time in ms (the return value is meaningless if the startStopWatch and stopStopWatch were not called before) +*/ +int elapsedMillisecond(StopWatch *w) +{ + int result; + + result = ((w->end.tv_sec - w->start.tv_sec) * 1000) + + (w->end.tv_nsec - w->start.tv_nsec) / 1000000; + return result; +} + +/** +* Compute the amount of time spent from when the startStopWatch and then the stopStopWatch were called on the StopWatch variable +* @param w pointer of a StopWatch struct +* @return amount of time in ns (the return value is meaningless if the startStopWatch and stopStopWatch were not called before) +*/ +int elapsedNanosecond(StopWatch *w) +{ + int result; + + result = ((w->end.tv_sec - w->start.tv_sec) * 1000000000) + + (w->end.tv_nsec - w->start.tv_nsec); + return result; +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.h new file mode 100644 index 000000000000..d9241c110cf4 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTime.h @@ -0,0 +1,63 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS Utility for measuring/handling the time * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsTime.h +* \brief Contains all the definitions and structs to handle and measure the time in the driver +*/ + +#ifndef FTS_TIME_H +#define FTS_TIME_H + +#include + +/** @defgroup timeouts Timeouts +* Definitions of all the Timeout used in several operations +* @{ +*/ +#define TIMEOUT_RESOLUTION \ + 2 /*timeout resolution in ms (all timeout should be multiples of this unit)*/ +#define GENERAL_TIMEOUT (50 * TIMEOUT_RESOLUTION) /*general timeout in ms*/ +#define RELEASE_INFO_TIMEOUT \ + (15 * TIMEOUT_RESOLUTION) /* timeout to request release info in ms*/ + +#define TIMEOUT_REQU_COMP_DATA \ + (100 * \ + TIMEOUT_RESOLUTION) /*timeout to request compensation data in ms*/ +#define TIMEOUT_REQU_DATA \ + (100 * TIMEOUT_RESOLUTION) /*timeout to request data in ms*/ +#define TIMEOUT_ITO_TEST_RESULT \ + (100 * TIMEOUT_RESOLUTION) /*timeout to perform ito test in ms*/ +#define TIMEOUT_INITIALIZATION_TEST_RESULT \ + (5000 * \ + TIMEOUT_RESOLUTION) /*timeout to perform initialization test in ms*/ +#define TIMEOUT_ECHO \ + TIMEOUT_INITIALIZATION_TEST_RESULT /*timeout of the echo command, should be the max of all the possible commands (used in worst case)*/ +/** @}*/ + +/** +* Struct used to measure the time elapsed between a starting and ending point. +*/ +typedef struct { + struct timespec start; /*store the starting time*/ + struct timespec end; /*store the finishing time*/ +} StopWatch; + +void startStopWatch(StopWatch *w); +void stopStopWatch(StopWatch *w); +int elapsedMillisecond(StopWatch *w); +int elapsedNanosecond(StopWatch *w); + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.c new file mode 100644 index 000000000000..eb4bda79f117 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.c @@ -0,0 +1,639 @@ +/* + + ************************************************************************** + ** STMicroelectronics ** + ************************************************************************** + ** marco.cali@st.com ** + ************************************************************************** + * * + * FTS Utility Functions * + * * + ************************************************************************** + ************************************************************************** + + */ + +/*! +* \file ftsTool.c +* \brief Contains all the functions to support common operation inside the driver +*/ + +#include "ftsCompensation.h" +#include "ftsCore.h" +#include "ftsError.h" +#include "ftsHardware.h" +#include "ftsIO.h" +#include "ftsSoftware.h" +#include "ftsTime.h" +#include "ftsTool.h" +#include "../fts.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** +* Print an array of byte in a HEX string and attach at the beginning a label. The function allocate memory that should be free outside the function itself +* @param label string to attach at the beginning +* @param buff pointer to the byte array that should be printed as HEX string +* @param count size of buff +* @return pointer to the array of characters that compose the HEX string. This point should be free outside when the string is no more needed +*/ +char *printHex(char *label, u8 *buff, int count, u8 *result) +{ + int i, offset; + + offset = strlen(label); + + strlcpy(result, label, offset); + + for (i = 0; i < count; i++) { + snprintf(&result[offset], 4, "%02X ", buff[i]); + offset += 3; + } + + return result; +} + +char *printHex_data(char *label, u8 *buff, int count) +{ + int i, offset; + char *result = NULL; + + offset = strlen(label); + result = (char *)kmalloc(((offset + 4 * count) + 1) * sizeof(char), + GFP_KERNEL); + if (result != NULL) { + strlcpy(result, label, offset); + + for (i = 0; i < count; i++) { + snprintf(&result[offset], 4, "%02X ", buff[i]); + offset += 3; + } + + strlcat(result, "\n", + ((offset + 4 * count) + 1) * sizeof(char)); + } + return result; +} + +/** + * Clear the FIFO from any event + * @return OK if success or an error code which specify the type of error encountered + */ +int flushFIFO(void) +{ + int ret; + u8 sett = SPECIAL_FIFO_FLUSH; + ret = writeSysCmd(SYS_CMD_SPECIAL, &sett, 1); + if (ret < OK) { + logError(1, "%s flushFIFO: ERROR %08X \n", tag, ret); + return ret; + } + + logError(0, "%s FIFO flushed! \n", tag); + return OK; +} + +/** +* Convert an array of bytes to an array of u16 taking two bytes at time, src has LSB first. +* @param src pointer to the source byte array +* @param src_length size of src +* @param dst pointer to the destination array. +* @return the final size of dst (half of the source) or ERROR_OP_NOT_ALLOW if the size of src is not multiple of 2. +*/ +int u8ToU16n(u8 *src, int src_length, u16 *dst) +{ + int i, j; + + if (src_length % 2 != 0) { + return ERROR_OP_NOT_ALLOW; + } else { + j = 0; + dst = (u16 *)kmalloc((src_length / 2) * sizeof(u16), + GFP_KERNEL); + for (i = 0; i < src_length; i += 2) { + dst[j] = ((src[i + 1] & 0x00FF) << 8) + + (src[i] & 0x00FF); + j++; + } + } + + return (src_length / 2); +} + +/** +* Convert an array of 2 bytes to a u16, src has LSB first (little endian). +* @param src pointer to the source byte array +* @param dst pointer to the destination u16. +* @return OK +*/ +int u8ToU16(u8 *src, u16 *dst) +{ + *dst = (u16)(((src[1] & 0x00FF) << 8) + (src[0] & 0x00FF)); + return OK; +} + +/** +* Convert an array of 2 bytes to a u16, src has MSB first (big endian). +* @param src pointer to the source byte array +* @param dst pointer to the destination u16. +* @return OK +*/ +int u8ToU16_be(u8 *src, u16 *dst) +{ + *dst = (u16)(((src[0] & 0x00FF) << 8) + (src[1] & 0x00FF)); + return OK; +} + +/** +* Convert an array of u16 to an array of u8, dst has MSB first (big endian). +* @param src pointer to the source array of u16 +* @param src_length size of src +* @param dst pointer to the destination array of u8. This array should be free when no need anymore +* @return size of dst (src size multiply by 2) +*/ +int u16ToU8n_be(u16 *src, int src_length, u8 *dst) +{ + int i, j; + dst = (u8 *)kmalloc((2 * src_length) * sizeof(u8), GFP_KERNEL); + j = 0; + for (i = 0; i < src_length; i++) { + dst[j] = (u8)(src[i] & 0xFF00) >> 8; + dst[j + 1] = (u8)(src[i] & 0x00FF); + j += 2; + } + + return src_length * 2; +} + +/** +* Convert a u16 to an array of 2 u8, dst has MSB first (big endian). +* @param src u16 to convert +* @param dst pointer to the destination array of 2 u8. +* @return OK +*/ +int u16ToU8_be(u16 src, u8 *dst) +{ + dst[0] = (u8)((src & 0xFF00) >> 8); + dst[1] = (u8)(src & 0x00FF); + return OK; +} + +/** +* Convert a u16 to an array of 2 u8, dst has LSB first (little endian). +* @param src u16 to convert +* @param dst pointer to the destination array of 2 u8. +* @return OK +*/ +int u16ToU8(u16 src, u8 *dst) +{ + dst[1] = (u8)((src & 0xFF00) >> 8); + dst[0] = (u8)(src & 0x00FF); + return OK; +} + +/** +* Convert an array of bytes to a u32, src has LSB first (little endian). +* @param src array of bytes to convert +* @param dst pointer to the destination u32 variable. +* @return OK +*/ +int u8ToU32(u8 *src, u32 *dst) +{ + *dst = (u32)(((src[3] & 0xFF) << 24) + ((src[2] & 0xFF) << 16) + + ((src[1] & 0xFF) << 8) + (src[0] & 0xFF)); + return OK; +} + +/** +* Convert a u32 to an array of 4 bytes, dst has LSB first (little endian). +* @param src u32 value to convert +* @param dst pointer to the destination array of 4 bytes. +* @return OK +*/ +int u32ToU8(u32 src, u8 *dst) +{ + dst[3] = (u8)((src & 0xFF000000) >> 24); + dst[2] = (u8)((src & 0x00FF0000) >> 16); + dst[1] = (u8)((src & 0x0000FF00) >> 8); + dst[0] = (u8)(src & 0x000000FF); + return OK; +} + +/** +* Convert a u32 to an array of 4 bytes, dst has MSB first (big endian). +* @param src u32 value to convert +* @param dst pointer to the destination array of 4 bytes. +* @return OK +*/ +int u32ToU8_be(u32 src, u8 *dst) +{ + dst[0] = (u8)((src & 0xFF000000) >> 24); + dst[1] = (u8)((src & 0x00FF0000) >> 16); + dst[2] = (u8)((src & 0x0000FF00) >> 8); + dst[3] = (u8)(src & 0x000000FF); + return OK; +} + +/** +* Execute a function passed as argment and retry it defined number of times if not successfull +* @param code pointer to a function which return an int and doesn't have any parameters +* @param wait_before_retry interval of time in ms to wait between one trial and another one +* @param retry_count max number of retry to attemp +* @return last return value obtained from the last execution of the code function +*/ +int attempt_function(int (*code)(void), unsigned long wait_before_retry, + int retry_count) +{ + int result; + int count = 0; + + do { + result = code(); + count++; + mdelay(wait_before_retry); + } while (count < retry_count && result < 0); + + if (count == retry_count) + return (result | ERROR_TIMEOUT); + else + return result; +} + +/** + * Enable all the possible sensing mode supported by the FW + * @return OK if success or an error code which specify the type of error encountered + */ +int senseOn(void) +{ + int ret; + + ret = setScanMode(SCAN_MODE_ACTIVE, 0x01); + if (ret < OK) { + logError(1, "%s senseOn: ERROR %08X\n", tag, ret); + return ret; + } + + logError(0, "%s senseOn: SENSE ON\n", tag); + return OK; +} + +/** + * Disable all the sensing mode + * @return OK if success or an error code which specify the type of error encountered + */ +int senseOff(void) +{ + int ret; + + ret = setScanMode(SCAN_MODE_ACTIVE, 0x00); + ; + if (ret < OK) { + logError(1, "%s senseOff: ERROR %08X\n", tag, ret); + return ret; + } + + logError(0, "%s senseOff: SENSE OFF\n", tag); + return OK; +} + +/** + * Clean up the IC status executing a system reset and giving the possibility to re-enabling the sensing + * @param enableTouch if 1, re-enable the sensing and the interrupt of the IC + * @return OK if success or an error code which specify the type of error encountered + */ +int cleanUp(int enableTouch) +{ + int res; + + logError(0, "%s cleanUp: system reset...\n", tag); + res = fts_system_reset(); + if (res < OK) + return res; + if (enableTouch) { + logError(0, "%s cleanUp: enabling touches...\n", tag); + res = senseOn(); + if (res < OK) + return res; + logError(0, "%s cleanUp: enabling interrupts...\n", tag); + res = fts_enableInterrupt(); + if (res < OK) + return res; + } + return OK; +} + +/** +* Transform an array of short in a matrix of short with a defined number of columns and the resulting number of rows +* @param data array of bytes to convert +* @param size size of data +* @param columns number of columns that the resulting matrix should have. +* @return a reference to a matrix of short where for each row there are columns elements +*/ +short **array1dTo2d_short(short *data, int size, int columns) +{ + int i; + short **matrix = (short **)kmalloc( + ((int)(size / columns)) * sizeof(short *), GFP_KERNEL); + if (matrix != NULL) { + for (i = 0; i < (int)(size / columns); i++) { + matrix[i] = (short *)kmalloc(columns * sizeof(short), + GFP_KERNEL); + } + + for (i = 0; i < size; i++) { + matrix[i / columns][i % columns] = data[i]; + } + } + + return matrix; +} + +/** +* Transform an array of u16 in a matrix of u16 with a defined number of columns and the resulting number of rows +* @param data array of bytes to convert +* @param size size of data +* @param columns number of columns that the resulting matrix should have. +* @return a reference to a matrix of u16 where for each row there are columns elements +*/ +u16 **array1dTo2d_u16(u16 *data, int size, int columns) +{ + int i; + u16 **matrix = (u16 **)kmalloc(((int)(size / columns)) * sizeof(u16 *), + GFP_KERNEL); + if (matrix != NULL) { + for (i = 0; i < (int)(size / columns); i++) { + matrix[i] = (u16 *)kmalloc(columns * sizeof(u16), + GFP_KERNEL); + } + + for (i = 0; i < size; i++) { + matrix[i / columns][i % columns] = data[i]; + } + } + + return matrix; +} + +/** +* Transform an array of u8 in a matrix of u8 with a defined number of columns and the resulting number of rows +* @param data array of bytes to convert +* @param size size of data +* @param columns number of columns that the resulting matrix should have. +* @return a reference to a matrix of short where for each row there are columns elements +*/ +u8 **array1dTo2d_u8(u8 *data, int size, int columns) +{ + int i; + u8 **matrix = (u8 **)kmalloc(((int)(size / columns)) * sizeof(u8 *), + GFP_KERNEL); + if (matrix != NULL) { + for (i = 0; i < (int)(size / columns); i++) { + matrix[i] = + (u8 *)kmalloc(columns * sizeof(u8), GFP_KERNEL); + } + + for (i = 0; i < size; i++) { + matrix[i / columns][i % columns] = data[i]; + } + } + + return matrix; +} + +/** +* Transform an array of i8 in a matrix of i8 with a defined number of columns and the resulting number of rows +* @param data array of bytes to convert +* @param size size of data +* @param columns number of columns that the resulting matrix should have. +* @return a reference to a matrix of short where for each row there are columns elements +*/ +i8 **array1dTo2d_i8(i8 *data, int size, int columns) +{ + int i; + i8 **matrix = (i8 **)kmalloc(((int)(size / columns)) * sizeof(i8 *), + GFP_KERNEL); + if (matrix != NULL) { + for (i = 0; i < (int)(size / columns); i++) { + matrix[i] = + (i8 *)kmalloc(columns * sizeof(i8), GFP_KERNEL); + } + + for (i = 0; i < size; i++) { + matrix[i / columns][i % columns] = data[i]; + } + } + + return matrix; +} + +/** +* Print in the kernel log a label followed by a matrix of short row x columns and free its memory +* @param label pointer to the string to print before the actual matrix +* @param matrix reference to the matrix of short which contain the actual data +* @param row number of rows on which the matrix should be print +* @param column number of columns for each row +*/ +void print_frame_short(char *label, short **matrix, int row, int column) +{ + int i, j; + logError(1, "%s %s \n", tag, label); + for (i = 0; i < row; i++) { + logError(1, "%s ", tag); + for (j = 0; j < column; j++) { + printk("%d ", matrix[i][j]); + } + logError(1, "\n"); + kfree(matrix[i]); + } + kfree(matrix); +} + +/** +* Print in the kernel log a label followed by a matrix of u16 row x columns and free its memory +* @param label pointer to the string to print before the actual matrix +* @param matrix reference to the matrix of u16 which contain the actual data +* @param row number of rows on which the matrix should be print +* @param column number of columns for each row +*/ +void print_frame_u16(char *label, u16 **matrix, int row, int column) +{ + int i, j; + logError(1, "%s %s \n", tag, label); + for (i = 0; i < row; i++) { + logError(0, "%s ", tag); + for (j = 0; j < column; j++) { + printk("%d ", matrix[i][j]); + } + logError(0, "\n"); + kfree(matrix[i]); + } + kfree(matrix); +} + +/** +* Print in the kernel log a label followed by a matrix of u8 row x columns and free its memory +* @param label pointer to the string to print before the actual matrix +* @param matrix reference to the matrix of u8 which contain the actual data +* @param row number of rows on which the matrix should be print +* @param column number of columns for each row +*/ +void print_frame_u8(char *label, u8 **matrix, int row, int column) +{ + int i, j; + logError(1, "%s %s \n", tag, label); + for (i = 0; i < row; i++) { + logError(1, "%s ", tag); + for (j = 0; j < column; j++) { + printk("%d ", matrix[i][j]); + } + logError(1, "\n"); + kfree(matrix[i]); + } + kfree(matrix); +} + +/** +* Print in the kernel log a label followed by a matrix of i8 row x columns and free its memory +* @param label pointer to the string to print before the actual matrix +* @param matrix reference to the matrix of u8 which contain the actual data +* @param row number of rows on which the matrix should be print +* @param column number of columns for each row +*/ +void print_frame_i8(char *label, i8 **matrix, int row, int column) +{ + int i, j; + logError(1, "%s %s \n", tag, label); + for (i = 0; i < row; i++) { + logError(1, "%s ", tag); + for (j = 0; j < column; j++) { + printk("%d ", matrix[i][j]); + } + logError(1, "\n"); + kfree(matrix[i]); + } + kfree(matrix); +} + +/** +* Print in the kernel log a label followed by a matrix of u32 row x columns and free its memory +* @param label pointer to the string to print before the actual matrix +* @param matrix reference to the matrix of u32 which contain the actual data +* @param row number of rows on which the matrix should be print +* @param column number of columns for each row +*/ +void print_frame_u32(char *label, u32 **matrix, int row, int column) +{ + int i, j; + logError(1, "%s %s \n", tag, label); + for (i = 0; i < row; i++) { + logError(0, "%s ", tag); + for (j = 0; j < column; j++) { + printk("%d ", matrix[i][j]); + } + logError(0, "\n"); + kfree(matrix[i]); + } + kfree(matrix); +} + +/** +* Print in the kernel log a label followed by a matrix of int row x columns and free its memory +* @param label pointer to the string to print before the actual matrix +* @param matrix reference to the matrix of int which contain the actual data +* @param row number of rows on which the matrix should be print +* @param column number of columns for each row +*/ +void print_frame_int(char *label, int **matrix, int row, int column) +{ + int i, j; + logError(1, "%s %s \n", tag, label); + for (i = 0; i < row; i++) { + logError(0, "%s ", tag); + for (j = 0; j < column; j++) { + printk("%d ", matrix[i][j]); + } + logError(0, "\n"); + kfree(matrix[i]); + } + kfree(matrix); +} + +/** +* Convert an array of bytes to an u64, src has MSB first (big endian). +* @param src array of bytes +* @param dest pointer to the destination u64. +* @param size size of src (can be <= 8) +* @return OK if success or ERROR_OP_NOT_ALLOW if size exceed 8 +*/ +int u8ToU64_be(u8 *src, u64 *dest, int size) +{ + int i = 0; + + if (size > sizeof(u64)) { + return ERROR_OP_NOT_ALLOW; + } else { + *dest = 0; + + for (i = 0; i < size; i++) { + *dest |= (u64)(src[i]) << ((size - 1 - i) * 8); + } + + return OK; + } +} + +/** +* Convert an u64 to an array of bytes, dest has MSB first (big endian). +* @param src value of u64 +* @param dest pointer to the destination array of bytes. +* @param size size of src (can be <= 8) +* @return OK if success or ERROR_OP_NOT_ALLOW if size exceed 8 +*/ +int u64ToU8_be(u64 src, u8 *dest, int size) +{ + int i = 0; + if (size > sizeof(u64)) { + return ERROR_OP_NOT_ALLOW; + } else { + for (i = 0; i < size; i++) { + dest[i] = (u8)((src >> ((size - 1 - i) * 8)) & 0xFF); + } + } + + return OK; +} + +/*********** NEW API *************/ + +/** + * Convert a value of an id in a bitmask with a 1 in the position of the value of the id + * @param id Value of the ID to convert + * @param mask pointer to the bitmask that will be updated with the value of id + * @param size dimension in bytes of mask + * @return OK if success or ERROR_OP_NOT_ALLOW if size of mask is not enough to contain ID + */ +int fromIDtoMask(u8 id, u8 *mask, int size) +{ + if (((int)((id) / 8)) < size) { + logError(0, "%s %s: ID = %d Index = %d Position = %d !\n", tag, + __func__, id, ((int)((id) / 8)), (id % 8)); + mask[((int)((id) / 8))] |= 0x01 << (id % 8); + return OK; + } else { + logError( + 1, + "%s %s: Bitmask too small! Impossible contain ID = %d %d>=%d! ERROR %08X\n", + tag, __func__, id, ((int)((id) / 8)), size, + ERROR_OP_NOT_ALLOW); + return ERROR_OP_NOT_ALLOW; + } +} diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.h new file mode 100644 index 000000000000..565c57b8636c --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsTool.h @@ -0,0 +1,56 @@ +/* + +************************************************************************** +** STMicroelectronics ** +************************************************************************** +** marco.cali@st.com ** +************************************************************************** +* * +* FTS Utility Functions * +* * +************************************************************************** +************************************************************************** + +*/ + +/*! +* \file ftsTool.h +* \brief Contains all the definitions to support common operations inside the driver +*/ + +#ifndef FTS_TOOL_H +#define FTS_TOOL_H + +char *printHex(char *label, u8 *buff, int count, u8 *result); +char *printHex_data(char *label, u8 *buff, int count); +int u8ToU16(u8 *src, u16 *dst); +int u8ToU16_be(u8 *src, u16 *dst); +int u8ToU16n(u8 *src, int src_length, u16 *dst); +int u16ToU8(u16 src, u8 *dst); +int u16ToU8_be(u16 src, u8 *dst); +int u16ToU8n_be(u16 *src, int src_length, u8 *dst); +int u8ToU32(u8 *src, u32 *dst); +int u32ToU8(u32 src, u8 *dst); +int u32ToU8_be(u32 src, u8 *dst); +int u8ToU64_be(u8 *src, u64 *dest, int size); +int u64ToU8_be(u64 src, u8 *dest, int size); +int attempt_function(int (*code)(void), unsigned long wait_before_retry, + int retry_count); +int senseOn(void); +int senseOff(void); +void print_frame_short(char *label, short **matrix, int row, int column); +short **array1dTo2d_short(short *data, int size, int columns); +void print_frame_u16(char *label, u16 **matrix, int row, int column); +u16 **array1dTo2d_u16(u16 *data, int size, int columns); +u8 **array1dTo2d_u8(u8 *data, int size, int columns); +i8 **array1dTo2d_i8(i8 *data, int size, int columns); +void print_frame_u8(char *label, u8 **matrix, int row, int column); +void print_frame_i8(char *label, i8 **matrix, int row, int column); +void print_frame_u32(char *label, u32 **matrix, int row, int column); +void print_frame_int(char *label, int **matrix, int row, int column); +int cleanUp(int enableTouch); +int flushFIFO(void); + +int fromIDtoMask(u8 id, u8 *mask, int size); + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_limits.h b/drivers/input/touchscreen/xiaomi/fts_521/fts_limits.h new file mode 100644 index 000000000000..7d34aa93c02a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_limits.h @@ -0,0 +1,1412 @@ +/*! +* \file fts_limits.h +* \brief Contains the size and the byte array of the production test limit file which contains thresholds used to test data +*/ + +#ifndef FTS_LIMITS_H +#define FTS_LIMITS_H +/*This is an auto generated header file*/ +/*--->Remember to change the name of the two variables!<---*/ +const uint32_t myArray2_size = 16725; + +/** + * Array containing the production limit file + */ +const uint8_t myArray2[] = { + 0x2A, 0x53, 0x54, 0x4F, 0x50, 0x5F, 0x4F, 0x4E, 0x5F, 0x46, 0x41, 0x49, + 0x4C, 0x2C, 0x31, 0x2C, 0x31, 0x0A, 0x31, 0x0A, 0x2A, 0x53, 0x54, 0x4F, + 0x50, 0x5F, 0x4F, 0x4E, 0x5F, 0x45, 0x52, 0x52, 0x4F, 0x52, 0x2C, 0x31, + 0x2C, 0x31, 0x0A, 0x31, 0x0A, 0x2A, 0x46, 0x4F, 0x52, 0x43, 0x45, 0x5F, + 0x46, 0x57, 0x5F, 0x55, 0x50, 0x44, 0x41, 0x54, 0x45, 0x2C, 0x31, 0x2C, + 0x31, 0x0A, 0x30, 0x0A, 0x2A, 0x53, 0x53, 0x5F, 0x49, 0x58, 0x31, 0x5F, + 0x46, 0x4F, 0x52, 0x43, 0x45, 0x5F, 0x57, 0x2C, 0x31, 0x2C, 0x31, 0x0A, + 0x32, 0x0A, 0x2A, 0x53, 0x53, 0x5F, 0x49, 0x58, 0x32, 0x5F, 0x46, 0x4F, + 0x52, 0x43, 0x45, 0x5F, 0x57, 0x2C, 0x31, 0x2C, 0x31, 0x0A, 0x31, 0x0A, + 0x2A, 0x53, 0x53, 0x5F, 0x49, 0x58, 0x31, 0x5F, 0x53, 0x45, 0x4E, 0x53, + 0x45, 0x5F, 0x57, 0x2C, 0x31, 0x2C, 0x31, 0x0A, 0x32, 0x0A, 0x2A, 0x53, + 0x53, 0x5F, 0x49, 0x58, 0x32, 0x5F, 0x53, 0x45, 0x4E, 0x53, 0x45, 0x5F, + 0x57, 0x2C, 0x31, 0x2C, 0x31, 0x0A, 0x31, 0x0A, 0x2A, 0x4D, 0x53, 0x5F, + 0x52, 0x41, 0x57, 0x5F, 0x44, 0x41, 0x54, 0x41, 0x5F, 0x4D, 0x49, 0x4E, + 0x5F, 0x4D, 0x41, 0x58, 0x2C, 0x31, 0x2C, 0x32, 0x0A, 0x31, 0x30, 0x30, + 0x30, 0x2C, 0x31, 0x35, 0x30, 0x30, 0x30, 0x0A, 0x2A, 0x4D, 0x53, 0x5F, + 0x52, 0x41, 0x57, 0x5F, 0x44, 0x41, 0x54, 0x41, 0x5F, 0x47, 0x41, 0x50, + 0x2C, 0x31, 0x2C, 0x31, 0x0A, 0x33, 0x30, 0x30, 0x30, 0x0A, 0x2A, 0x4D, + 0x53, 0x5F, 0x54, 0x4F, 0x55, 0x43, 0x48, 0x5F, 0x41, 0x43, 0x54, 0x49, + 0x56, 0x45, 0x5F, 0x43, 0x58, 0x31, 0x5F, 0x4D, 0x49, 0x4E, 0x5F, 0x4D, + 0x41, 0x58, 0x2C, 0x31, 0x2C, 0x32, 0x0A, 0x30, 0x2C, 0x36, 0x33, 0x0A, + 0x2A, 0x4D, 0x53, 0x5F, 0x54, 0x4F, 0x55, 0x43, 0x48, 0x5F, 0x41, 0x43, + 0x54, 0x49, 0x56, 0x45, 0x5F, 0x43, 0x58, 0x32, 0x5F, 0x4D, 0x49, 0x4E, + 0x2C, 0x32, 0x32, 0x2C, 0x32, 0x37, 0x0A, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x0A, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x0A, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, + 0x0A, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 0x30, 0x2C, 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0x32, 0x35, 0x35, + 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, + 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, + 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, + 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, + 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, + 0x2C, 0x32, 0x35, 0x35, 0x2C, 0x32, 0x35, 0x35, 0x0A, +}; + +#endif diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c new file mode 100644 index 000000000000..2b1b5fa8dd0c --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c @@ -0,0 +1,2421 @@ +/* + + ************************************************************************** + ** STMicroelectronics ** + ************************************************************************** + ** marco.cali@st.com ** + ************************************************************************** + * * + * Utilities published in /proc/fts * + * * + ************************************************************************** + ************************************************************************** + + */ + +/*! +* \file fts_proc.c +* \brief contains the function and variables needed to publish a file node in the file system which allow to communicate with the IC from userspace +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fts.h" +#include "fts_lib/ftsCompensation.h" +#include "fts_lib/ftsCore.h" +#include "fts_lib/ftsIO.h" +#include "fts_lib/ftsError.h" +#include "fts_lib/ftsFrame.h" +#include "fts_lib/ftsFlash.h" +#include "fts_lib/ftsTest.h" +#include "fts_lib/ftsTime.h" +#include "fts_lib/ftsTool.h" + +#define DRIVER_TEST_FILE_NODE "driver_test" +#define CHUNK_PROC 1024 +#define DIAGNOSTIC_NUM_FRAME 10 + +/** @defgroup proc_file_code Proc File Node +* @ingroup file_nodes +* The /proc/fts/driver_test file node provide expose the most important API implemented into the driver to execute any possible operation into the IC \n +* Thanks to a series of Operation Codes, each of them, with a different set of parameter, it is possible to select a function to execute\n +* The result of the function is usually returned into the shell as an ASCII hex string where each byte is encoded in two chars.\n +* @{ +*/ + +/*Bus operations*/ +#define CMD_READ 0x00 +#define CMD_WRITE 0x01 +#define CMD_WRITEREAD 0x02 +#define CMD_WRITETHENWRITEREAD 0x03 +#define CMD_WRITEU8UX 0x04 +#define CMD_WRITEREADU8UX 0x05 +#define CMD_WRITEU8UXTHENWRITEU8UX 0x06 +#define CMD_WRITEU8UXTHENWRITEREADU8UX 0x07 +#define CMD_GETLIMITSFILE 0x08 +#define CMD_GETFWFILE 0x09 +#define CMD_VERSION 0x0A +#define CMD_READCONFIG 0x0B + +/*GUI utils byte ver*/ +#define CMD_READ_BYTE 0xF0 +#define CMD_WRITE_BYTE 0xF1 +#define CMD_WRITEREAD_BYTE 0xF2 +#define CMD_WRITETHENWRITEREAD_BYTE 0xF3 +#define CMD_WRITEU8UX_BYTE 0xF4 +#define CMD_WRITEREADU8UX_BYTE 0xF5 +#define CMD_WRITEU8UXTHENWRITEU8UX_BYTE 0xF6 +#define CMD_WRITEU8UXTHENWRITEREADU8UX_BYTE 0xF7 +#define CMD_GETLIMITSFILE_BYTE 0xF8 +#define CMD_GETFWFILE_BYTE 0xF9 +#define CMD_VERSION_BYTE 0xFA +#define CMD_CHANGE_OUTPUT_MODE 0xFF + +/*Core/Tools*/ +#define CMD_POLLFOREVENT 0x11 +#define CMD_SYSTEMRESET 0x12 +#define CMD_CLEANUP 0x13 +#define CMD_POWERCYCLE 0x14 +#define CMD_READSYSINFO 0x15 +#define CMD_FWWRITE 0x16 +#define CMD_INTERRUPT 0x17 + +/*Frame*/ +#define CMD_GETFORCELEN 0x20 +#define CMD_GETSENSELEN 0x21 +#define CMD_GETMSFRAME 0x23 +#define CMD_GETSSFRAME 0x24 + +/*Compensation*/ +#define CMD_REQCOMPDATA 0x30 +#define CMD_READCOMPDATAHEAD 0x31 +#define CMD_READMSCOMPDATA 0x32 +#define CMD_READSSCOMPDATA 0x33 +#define CMD_READTOTMSCOMPDATA 0x35 +#define CMD_READTOTSSCOMPDATA 0x36 + +/*FW Update*/ +#define CMD_GETFWVER 0x40 +#define CMD_FLASHUNLOCK 0x42 +#define CMD_READFWFILE 0x43 +#define CMD_FLASHPROCEDURE 0x44 +#define CMD_FLASHERASEUNLOCK 0x45 +#define CMD_FLASHERASEPAGE 0x46 + +/*MP test*/ +#define CMD_ITOTEST 0x50 +#define CMD_INITTEST 0x51 +#define CMD_MSRAWTEST 0x52 +#define CMD_MSINITDATATEST 0x53 +#define CMD_SSRAWTEST 0x54 +#define CMD_SSINITDATATEST 0x55 +#define CMD_MAINTEST 0x56 +#define CMD_FREELIMIT 0x57 + +/*Diagnostic*/ +#define CMD_DIAGNOSTIC 0x60 + +#define CMD_CHANGE_SAD 0x70 + +static u8 bin_output; +/** @}*/ + +/** @defgroup scriptless Scriptless Protocol + * @ingroup proc_file_code + * Scriptless Protocol allows ST Software (such as FingerTip Studio etc) to communicate with the IC from an user space. + * This mode gives access to common bus operations (write, read etc) and support additional functionalities. \n + * The protocol is based on exchange of binary messages included between a start and an end byte + * @{ + */ + +#define MESSAGE_START_BYTE 0x7B +#define MESSAGE_END_BYTE 0x7D +#define MESSAGE_MIN_HEADER_SIZE 8 + +/** + * Possible actions that can be requested by an host + */ +typedef enum { + ACTION_WRITE = (u16)0x0001, + ACTION_READ = (u16)0x0002, + ACTION_WRITE_READ = (u16)0x0003, + ACTION_GET_VERSION = (u16)0x0004, + ACTION_WRITEU8UX = (u16)0x0011, + ACTION_WRITEREADU8UX = (u16)0x0012, + ACTION_WRITETHENWRITEREAD = (u16)0x0013, + ACTION_WRITEU8XTHENWRITEREADU8UX = (u16)0x0014, + ACTION_WRITEU8UXTHENWRITEU8UX = (u16)0x0015, + ACTION_GET_FW = (u16)0x1000, + ACTION_GET_LIMIT = (u16)0x1001 +} Actions; + +/** + * Struct used to contain info of the message received by the host in Scriptless mode + */ +typedef struct { + u16 msg_size; + u16 counter; + Actions action; + u8 dummy; +} Message; + +/** @}*/ + +extern TestToDo tests; +extern SysInfo systemInfo; + +static int limit; +static int chunk; +static int printed; +static struct proc_dir_entry *fts_dir; +static u8 *driver_test_buff; +char buf_chunk[CHUNK_PROC]; +static Message mess; + +/************************ SEQUENTIAL FILE UTILITIES **************************/ +/** +* This function is called at the beginning of the stream to a sequential file or every time into the sequential were already written PAGE_SIZE bytes and the stream need to restart +* @param s pointer to the sequential file on which print the data +* @param pos pointer to the offset where write the data +* @return NULL if there is no data to print or the pointer to the beginning of the data that need to be printed +*/ +static void *fts_seq_start(struct seq_file *s, loff_t *pos) +{ + logError( + 0, + "%s %s: Entering start(), pos = %Ld limit = %d printed = %d \n", + tag, __func__, *pos, limit, printed); + + if (driver_test_buff == NULL && *pos == 0) { + logError(1, "%s %s: No data to print!\n", tag, __func__); + driver_test_buff = (u8 *)kmalloc(13 * sizeof(u8), GFP_KERNEL); + + snprintf(driver_test_buff, PAGE_SIZE, "{ %08X }\n", + ERROR_OP_NOT_ALLOW); + + limit = strlen(driver_test_buff); + } else { + if (*pos != 0) + *pos += chunk - 1; + + if (*pos >= limit) { + return NULL; + } + } + + chunk = CHUNK_PROC; + if (limit - *pos < CHUNK_PROC) + chunk = limit - *pos; + memset(buf_chunk, 0, CHUNK_PROC); + memcpy(buf_chunk, &driver_test_buff[(int)*pos], chunk); + + return buf_chunk; +} + +/** +* This function actually print a chunk amount of data in the sequential file +* @param s pointer to the sequential file where to print the data +* @param v pointer to the data to print +* @return 0 +*/ +static int fts_seq_show(struct seq_file *s, void *v) +{ + seq_write(s, (u8 *)v, chunk); + printed += chunk; + return 0; +} + +/** +* This function update the pointer and the counters to the next data to be printed +* @param s pointer to the sequential file where to print the data +* @param v pointer to the data to print +* @param pos pointer to the offset where write the next data +* @return NULL if there is no data to print or the pointer to the beginning of the next data that need to be printed +*/ +static void *fts_seq_next(struct seq_file *s, void *v, loff_t *pos) +{ + (*pos) += chunk; + chunk = CHUNK_PROC; + + if (*pos >= limit) + return NULL; + else { + if (limit - *pos < CHUNK_PROC) + chunk = limit - *pos; + } + + memset(buf_chunk, 0, CHUNK_PROC); + memcpy(buf_chunk, &driver_test_buff[(int)*pos], chunk); + return buf_chunk; +} + +/** +* This function is called when there are no more data to print the stream need to be terminated or when PAGE_SIZE data were already written into the sequential file +* @param s pointer to the sequential file where to print the data +* @param v pointer returned by fts_seq_next +*/ +static void fts_seq_stop(struct seq_file *s, void *v) +{ + if (v) { + /*logError(0, "%s %s: v is %X.\n", tag, __func__, v);*/ + } else { + limit = 0; + chunk = 0; + printed = 0; + if (driver_test_buff != NULL) { + kfree(driver_test_buff); + driver_test_buff = NULL; + + } else { + /*logError(0, "%s %s: driver_test_buff is already null.\n", tag, __func__);*/ + } + } +} + +/** +* Struct where define and specify the functions which implements the flow for writing on a sequential file +*/ +static struct seq_operations fts_seq_ops = { .start = fts_seq_start, + .next = fts_seq_next, + .stop = fts_seq_stop, + .show = fts_seq_show }; + +/** +* This function open a sequential file +* @param inode Inode in the file system that was called and triggered this function +* @param file file associated to the file node +* @return error code, 0 if success +*/ +static int fts_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &fts_seq_ops); +}; + +/*****************************************************************************/ + +/**************************** DRIVER TEST ************************************/ + +/** @addtogroup proc_file_code + * @{ + */ + +/** + * Receive the OP code and the inputs from shell when the file node is called, parse it and then execute the corresponding function + * echo cmd+parameters > /proc/fts/driver_test to execute the select command + * cat /proc/fts/driver_test to obtain the result into the shell \n + * the string returned in the shell is made up as follow: \n + * { = start byte \n + * the answer content and format strictly depend on the cmd executed. In general can be: an HEX string or a byte array (e.g in case of 0xF- commands) \n + * } = end byte \n + */ +static ssize_t fts_driver_test_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + int numberParam = 0; + struct fts_ts_info *info = dev_get_drvdata(getDev()); + char *p = NULL; + char pbuf[count]; + char path[100] = { 0 }; + int res = -1, j, index = 0; + int size = 6; + int temp, byte_call = 0; + u16 byteToRead = 0; + u32 fileSize = 0; + u8 *readData = NULL; + u8 *cmd = NULL; + u32 funcToTest[((count + 1) / 3)]; + u64 addr = 0; + MutualSenseFrame frameMS; + SelfSenseFrame frameSS; + + DataHeader dataHead; + MutualSenseData compData; + SelfSenseData comData; + TotMutualSenseData totCompData; + TotSelfSenseData totComData; + + u64 address; + u16 fw_version; + u16 config_id; + + Firmware fw; + LimitFile lim; + + mess.dummy = 0; + mess.action = 0; + mess.msg_size = 0; + + cmd = (u8 *)kzalloc(sizeof(u8) * count, GFP_KERNEL); + if (!cmd) { + res = ERROR_ALLOC; + goto END; + } + if (access_ok(VERIFY_READ, buf, count) < OK || + copy_from_user(pbuf, buf, count) != 0) { + res = ERROR_ALLOC; + goto END; + } + + p = pbuf; + if (count > MESSAGE_MIN_HEADER_SIZE - 1 && p[0] == MESSAGE_START_BYTE) { + logError(0, "%s Enter in Byte Mode! \n", tag); + byte_call = 1; + mess.msg_size = (p[1] << 8) | p[2]; + mess.counter = (p[3] << 8) | p[4]; + mess.action = (p[5] << 8) | p[6]; + logError( + 0, + "%s Message received: size = %d, counter_id = %d, action = %04X \n", + tag, mess.msg_size, mess.counter, mess.action); + size = MESSAGE_MIN_HEADER_SIZE + 2; + if (count < mess.msg_size || p[count - 2] != MESSAGE_END_BYTE) { + logError( + 1, + "%s number of byte received or end byte wrong! msg_size = %d != %d, last_byte = %02X != %02X ... ERROR %08X\n", + tag, mess.msg_size, count, p[count - 1], + MESSAGE_END_BYTE, ERROR_OP_NOT_ALLOW); + res = ERROR_OP_NOT_ALLOW; + goto END; + + } else { + numberParam = + mess.msg_size - MESSAGE_MIN_HEADER_SIZE + 1; + size = MESSAGE_MIN_HEADER_SIZE + 2; + switch (mess.action) { + case ACTION_READ: + cmd[0] = funcToTest[0] = CMD_READ_BYTE; + break; + + case ACTION_WRITE: + cmd[0] = funcToTest[0] = CMD_WRITE_BYTE; + break; + + case ACTION_WRITE_READ: + cmd[0] = funcToTest[0] = CMD_WRITEREAD_BYTE; + break; + + case ACTION_GET_VERSION: + cmd[0] = funcToTest[0] = CMD_VERSION_BYTE; + break; + + case ACTION_WRITETHENWRITEREAD: + cmd[0] = funcToTest[0] = + CMD_WRITETHENWRITEREAD_BYTE; + break; + + case ACTION_WRITEU8UX: + cmd[0] = funcToTest[0] = CMD_WRITEU8UX_BYTE; + break; + + case ACTION_WRITEREADU8UX: + cmd[0] = funcToTest[0] = CMD_WRITEREADU8UX_BYTE; + break; + + case ACTION_WRITEU8UXTHENWRITEU8UX: + cmd[0] = funcToTest[0] = + CMD_WRITEU8UXTHENWRITEU8UX_BYTE; + break; + + case ACTION_WRITEU8XTHENWRITEREADU8UX: + cmd[0] = funcToTest[0] = + CMD_WRITEU8UXTHENWRITEREADU8UX_BYTE; + break; + + case ACTION_GET_FW: + cmd[0] = funcToTest[0] = CMD_GETFWFILE_BYTE; + break; + + case ACTION_GET_LIMIT: + cmd[0] = funcToTest[0] = CMD_GETLIMITSFILE_BYTE; + break; + + default: + logError( + 1, + "%s Invalid Action = %d ... ERROR %08X\n", + tag, mess.action, ERROR_OP_NOT_ALLOW); + res = ERROR_OP_NOT_ALLOW; + goto END; + } + + if (numberParam - 1 != 0) + memcpy(&cmd[1], &p[7], numberParam - 1); + } + } else { + if (((count + 1) / 3) >= 1) { + sscanf(p, "%02X ", &funcToTest[0]); + p += 3; + cmd[0] = (u8)funcToTest[0]; + numberParam = 1; + } else { + res = ERROR_OP_NOT_ALLOW; + goto END; + } + + logError(1, "%s functionToTest[0] = %02X cmd[0]= %02X\n", tag, + funcToTest[0], cmd[0]); + switch (funcToTest[0]) { + case CMD_GETFWFILE: + case CMD_GETLIMITSFILE: + if (count - 2 - 1 > 1) { + numberParam = 2; + sscanf(p, "%100s", path); + } + break; + + default: + for (; numberParam < (count + 1) / 3; numberParam++) { + sscanf(p, "%02X ", &funcToTest[numberParam]); + p += 3; + cmd[numberParam] = (u8)funcToTest[numberParam]; + logError( + 1, + "%s functionToTest[%d] = %02X cmd[%d]= %02X\n", + tag, numberParam, + funcToTest[numberParam], numberParam, + cmd[numberParam]); + } + } + } + + fw.data = NULL; + lim.data = NULL; + + logError(1, "%s Number of Parameters = %d \n", tag, numberParam); + + if (numberParam >= 1) { + switch (funcToTest[0]) { + case CMD_VERSION_BYTE: + logError(0, "%s %s: Get Version Byte \n", tag, __func__, + res); + byteToRead = 2; + mess.dummy = 0; + readData = (u8 *)kmalloc(byteToRead * sizeof(u8), + GFP_KERNEL); + size += byteToRead; + if (readData != NULL) { + readData[0] = (u8)(FTS_TS_DRV_VER >> 24); + readData[1] = (u8)(FTS_TS_DRV_VER >> 16); + res = OK; + logError(0, "%s %s: Version = %02X%02X \n", tag, + __func__, readData[0], readData[1]); + } else { + res = ERROR_ALLOC; + logError( + 1, + "%s %s: Impossible allocate memory... ERROR %08X \n", + tag, __func__, res); + } + break; + + case CMD_VERSION: + byteToRead = 2 * sizeof(u32); + mess.dummy = 0; + readData = (u8 *)kmalloc(byteToRead * sizeof(u8), + GFP_KERNEL); + u32ToU8_be(FTS_TS_DRV_VER, readData); + fileSize = 0; +#ifdef FW_H_FILE + fileSize |= 0x00010000; +#endif + +#ifdef LIMITS_H_FILE + fileSize |= 0x00020000; +#endif + +#ifdef USE_ONE_FILE_NODE + fileSize |= 0x00040000; +#endif + +#ifdef FW_UPDATE_ON_PROBE + fileSize |= 0x00080000; +#endif + +#ifdef PRE_SAVED_METHOD + fileSize |= 0x00100000; +#endif + +#ifdef USE_GESTURE_MASK + fileSize |= 0x00100000; +#endif + +#ifdef I2C_INTERFACE + fileSize |= 0x00200000; +#endif + +#ifdef PHONE_KEY + fileSize |= 0x00000100; +#endif + +#ifdef GESTURE_MODE + fromIDtoMask(FEAT_SEL_GESTURE, (u8 *)&fileSize, 4); +#endif + +#ifdef GRIP_MODE + fromIDtoMask(FEAT_SEL_GRIP, (u8 *)&fileSize, 4); +#endif + +#ifdef CHARGER_MODE + fromIDtoMask(FEAT_SEL_CHARGER, (u8 *)&fileSize, 4); +#endif + +#ifdef GLOVE_MODE + fromIDtoMask(FEAT_SEL_GLOVE, (u8 *)&fileSize, 4); +#endif + +#ifdef COVER_MODE + fromIDtoMask(FEAT_SEL_COVER, (u8 *)&fileSize, 4); +#endif + +#ifdef STYLUS_MODE + fromIDtoMask(FEAT_SEL_STYLUS, (u8 *)&fileSize, 4); +#endif + + u32ToU8_be(fileSize, &readData[4]); + res = OK; + size += (byteToRead * sizeof(u8)); + break; + + case CMD_WRITEREAD: + case CMD_WRITEREAD_BYTE: + if (numberParam >= 5) { + temp = numberParam - 4; + if (cmd[numberParam - 1] == 0) { + mess.dummy = 0; + } else + mess.dummy = 1; + + u8ToU16_be(&cmd[numberParam - 3], &byteToRead); + logError(0, "%s bytesToRead = %d \n", tag, + byteToRead + mess.dummy); + + readData = (u8 *)kmalloc( + (byteToRead + mess.dummy) * sizeof(u8), + GFP_KERNEL); + res = fts_writeRead_dma_safe( + &cmd[1], temp, readData, + byteToRead + mess.dummy); + size += (byteToRead * sizeof(u8)); + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_WRITE: + case CMD_WRITE_BYTE: + if (numberParam >= 2) { + temp = numberParam - 1; + res = fts_write_dma_safe(&cmd[1], temp); + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_READ: + case CMD_READ_BYTE: + if (numberParam >= 3) { + if (numberParam == 3 || + (numberParam == 4 && + cmd[numberParam - 1] == 0)) { + mess.dummy = 0; + } else + mess.dummy = 1; + u8ToU16_be(&cmd[1], &byteToRead); + readData = (u8 *)kmalloc( + (byteToRead + mess.dummy) * sizeof(u8), + GFP_KERNEL); + res = fts_read_dma_safe( + readData, byteToRead + mess.dummy); + size += (byteToRead * sizeof(u8)); + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_WRITETHENWRITEREAD: + case CMD_WRITETHENWRITEREAD_BYTE: + if (numberParam >= 6) { + u8ToU16_be(&cmd[numberParam - 2], &byteToRead); + readData = (u8 *)kmalloc( + byteToRead * sizeof(u8), GFP_KERNEL); + res = fts_writeThenWriteRead( + &cmd[3], cmd[1], &cmd[3 + (int)cmd[1]], + cmd[2], readData, byteToRead); + size += (byteToRead * sizeof(u8)); + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_WRITEU8UX: + case CMD_WRITEU8UX_BYTE: + if (numberParam >= 4) { + if (cmd[2] <= sizeof(u64)) { + u8ToU64_be(&cmd[3], &addr, cmd[2]); + logError(0, "%s addr = %016X %ld \n", + tag, addr, addr); + res = fts_writeU8UX( + cmd[1], cmd[2], addr, + &cmd[3 + cmd[2]], + (numberParam - cmd[2] - 3)); + } else { + logError(1, "%s Wrong address size!\n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_WRITEREADU8UX: + case CMD_WRITEREADU8UX_BYTE: + if (numberParam >= 6) { + if (cmd[2] <= sizeof(u64)) { + u8ToU64_be(&cmd[3], &addr, cmd[2]); + u8ToU16_be(&cmd[numberParam - 3], + &byteToRead); + readData = (u8 *)kmalloc( + byteToRead * sizeof(u8), + GFP_KERNEL); + logError( + 0, + "%s addr = %016X byteToRead = %d \n", + tag, addr, byteToRead); + res = fts_writeReadU8UX( + cmd[1], cmd[2], addr, readData, + byteToRead, + cmd[numberParam - 1]); + size += (byteToRead * sizeof(u8)); + + } else { + logError(1, "%s Wrong address size!\n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_WRITEU8UXTHENWRITEU8UX: + case CMD_WRITEU8UXTHENWRITEU8UX_BYTE: + if (numberParam >= 6) { + if ((cmd[2] + cmd[4]) <= sizeof(u64)) { + u8ToU64_be(&cmd[5], &addr, + cmd[2] + cmd[4]); + logError(0, "%s addr = %016X %ld \n", + tag, addr, addr); + res = fts_writeU8UXthenWriteU8UX( + cmd[1], cmd[2], cmd[3], cmd[4], + addr, &cmd[5 + cmd[2] + cmd[4]], + (numberParam - cmd[2] - cmd[4] - + 5)); + } else { + logError(1, "%s Wrong address size! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_WRITEU8UXTHENWRITEREADU8UX: + case CMD_WRITEU8UXTHENWRITEREADU8UX_BYTE: + if (numberParam >= 8) { + if ((cmd[2] + cmd[4]) <= sizeof(u64)) { + u8ToU64_be(&cmd[5], &addr, + cmd[2] + cmd[4]); + logError( + 1, + "%s %s: cmd[5] = %02X, addr = %016X \n", + tag, __func__, cmd[5], addr); + u8ToU16_be(&cmd[numberParam - 3], + &byteToRead); + readData = (u8 *)kmalloc( + byteToRead * sizeof(u8), + GFP_KERNEL); + res = fts_writeU8UXthenWriteReadU8UX( + cmd[1], cmd[2], cmd[3], cmd[4], + addr, readData, byteToRead, + cmd[numberParam - 1]); + size += (byteToRead * sizeof(u8)); + } else { + logError( + 1, + "%s Wrong total address size! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + break; + + case CMD_CHANGE_OUTPUT_MODE: + if (numberParam >= 2) { + bin_output = cmd[1]; + logError( + 0, + "%s Setting Scriptless output mode: %d \n", + tag, bin_output); + res = OK; + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_FWWRITE: + if (numberParam >= 3) { + if (numberParam >= 2) { + temp = numberParam - 1; + res = fts_writeFwCmd(&cmd[1], temp); + } else { + logError(1, "%s Wrong parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_INTERRUPT: + if (numberParam >= 2) { + if (cmd[1] == 1) + res = fts_enableInterrupt(); + else + res = fts_disableInterrupt(); + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_READCONFIG: + if (numberParam == 5) { + byteToRead = + ((funcToTest[3] << 8) | funcToTest[4]); + readData = (u8 *)kmalloc( + byteToRead * sizeof(u8), GFP_KERNEL); + res = readConfig( + (u16)((((u8)funcToTest[1] & 0x00FF) + << 8) + + ((u8)funcToTest[2] & 0x00FF)), + readData, byteToRead); + size += (byteToRead * sizeof(u8)); + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_POLLFOREVENT: + if (numberParam >= 5) { + temp = (int)funcToTest[1]; + if (numberParam == 5 + (temp - 1) && + temp != 0) { + readData = (u8 *)kmalloc( + FIFO_EVENT_SIZE * sizeof(u8), + GFP_KERNEL); + res = pollForEvent( + (int *)&funcToTest[2], temp, + readData, + ((funcToTest[temp + 2] & 0x00FF) + << 8) + (funcToTest[temp + 3] & + 0x00FF)); + if (res >= OK) + res = OK; + size += (FIFO_EVENT_SIZE * sizeof(u8)); + byteToRead = FIFO_EVENT_SIZE; + } else { + logError(1, "%s Wrong parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_SYSTEMRESET: + res = fts_system_reset(); + + break; + + case CMD_READSYSINFO: + if (numberParam == 2) { + res = readSysInfo(funcToTest[1]); + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + break; + + case CMD_CLEANUP: + if (numberParam == 2) { + res = cleanUp(funcToTest[1]); + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + + break; + + case CMD_GETFORCELEN: + temp = getForceLen(); + if (temp < OK) + res = temp; + else { + size += (1 * sizeof(u8)); + res = OK; + } + break; + + case CMD_GETSENSELEN: + temp = getSenseLen(); + if (temp < OK) + res = temp; + else { + size += (1 * sizeof(u8)); + res = OK; + } + break; + + case CMD_GETMSFRAME: + if (numberParam == 2) { + logError(0, "%s Get 1 MS Frame \n", tag); + setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + flushFIFO(); + res = getMSFrame3((MSFrameType)cmd[1], + &frameMS); + if (res < 0) { + logError( + 0, + "%s Error while taking the MS frame... ERROR %08X \n", + tag, res); + + } else { + logError( + 0, + "%s The frame size is %d words\n", + tag, res); + size += (res * sizeof(short) + 2); + /* set res to OK because if getMSFrame is + successful res = number of words read + */ + res = OK; + print_frame_short( + "MS frame =", + array1dTo2d_short( + frameMS.node_data, + frameMS.node_data_size, + frameMS.header + .sense_node), + frameMS.header.force_node, + frameMS.header.sense_node); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + /*read self raw */ + case CMD_GETSSFRAME: + if (numberParam == 2) { + logError(0, "%s Get 1 SS Frame \n", tag); + flushFIFO(); + setScanMode(SCAN_MODE_ACTIVE, 0x01); + mdelay(WAIT_FOR_FRESH_FRAMES); + setScanMode(SCAN_MODE_ACTIVE, 0x00); + mdelay(WAIT_AFTER_SENSEOFF); + res = getSSFrame3((SSFrameType)cmd[1], + &frameSS); + + if (res < OK) { + logError( + 0, + "%s Error while taking the SS frame... ERROR %08X \n", + tag, res); + + } else { + logError( + 0, + "%s The frame size is %d words\n", + tag, res); + size += (res * sizeof(short) + 2); + /* set res to OK because if getMSFrame is + successful res = number of words read + */ + res = OK; + print_frame_short( + "SS force frame =", + array1dTo2d_short( + frameSS.force_data, + frameSS.header + .force_node, + 1), + frameSS.header.force_node, 1); + print_frame_short( + "SS sense frame =", + array1dTo2d_short( + frameSS.sense_data, + frameSS.header + .sense_node, + frameSS.header + .sense_node), + 1, frameSS.header.sense_node); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_REQCOMPDATA: + if (numberParam == 2) { + logError(0, + "%s Requesting Compensation Data \n", + tag); + res = requestCompensationData(cmd[1]); + + if (res < OK) { + logError( + 0, + "%s Error requesting compensation data ERROR %08X \n", + tag, res); + } else { + logError( + 0, + "%s Requesting Compensation Data Finished! \n", + tag); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_READCOMPDATAHEAD: + if (numberParam == 2) { + logError(0, + "%s Requesting Compensation Data \n", + tag); + res = requestCompensationData(cmd[1]); + if (res < OK) { + logError( + 0, + "%s Error requesting compensation data ERROR %08X \n", + tag, res); + } else { + logError( + 0, + "%s Requesting Compensation Data Finished! \n", + tag); + res = readCompensationDataHeader( + (u8)funcToTest[1], &dataHead, + &address); + if (res < OK) { + logError( + 0, + "%s Read Compensation Data Header ERROR %08X\n", + tag, res); + } else { + logError( + 0, + "%s Read Compensation Data Header OK!\n", + tag); + size += (1 * sizeof(u8)); + } + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_READMSCOMPDATA: + if (numberParam == 2) { + logError(0, "%s Get MS Compensation Data \n", + tag); + res = readMutualSenseCompensationData( + cmd[1], &compData); + + if (res < OK) { + logError( + 0, + "%s Error reading MS compensation data ERROR %08X \n", + tag, res); + } else { + logError( + 0, + "%s MS Compensation Data Reading Finished! \n", + tag); + size = ((compData.node_data_size + 10) * + sizeof(i8)); + print_frame_i8( + "MS Data (Cx2) =", + array1dTo2d_i8( + compData.node_data, + compData.node_data_size, + compData.header + .sense_node), + compData.header.force_node, + compData.header.sense_node); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_READSSCOMPDATA: + if (numberParam == 2) { + logError(0, "%s Get SS Compensation Data... \n", + tag); + res = readSelfSenseCompensationData(cmd[1], + &comData); + if (res < OK) { + logError( + 0, + "%s Error reading SS compensation data ERROR %08X\n", + tag, res); + } else { + logError( + 0, + "%s SS Compensation Data Reading Finished! \n", + tag); + size = ((comData.header.force_node + + comData.header.sense_node) * + 2 + + 13) * + sizeof(i8); + print_frame_i8( + "SS Data Ix2_fm = ", + array1dTo2d_i8( + comData.ix2_fm, + comData.header + .force_node, + comData.header + .force_node), + 1, comData.header.force_node); + print_frame_i8( + "SS Data Cx2_fm = ", + array1dTo2d_i8( + comData.cx2_fm, + comData.header + .force_node, + comData.header + .force_node), + 1, comData.header.force_node); + print_frame_i8( + "SS Data Ix2_sn = ", + array1dTo2d_i8( + comData.ix2_sn, + comData.header + .sense_node, + comData.header + .sense_node), + 1, comData.header.sense_node); + print_frame_i8( + "SS Data Cx2_sn = ", + array1dTo2d_i8( + comData.cx2_sn, + comData.header + .sense_node, + comData.header + .sense_node), + 1, comData.header.sense_node); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_READTOTMSCOMPDATA: + if (numberParam == 2) { + logError(0, + "%s Get TOT MS Compensation Data \n", + tag); + res = readTotMutualSenseCompensationData( + cmd[1], &totCompData); + + if (res < OK) { + logError( + 0, + "%s Error reading TOT MS compensation data ERROR %08X \n", + tag, res); + } else { + logError( + 0, + "%s TOT MS Compensation Data Reading Finished! \n", + tag); + size = (totCompData.node_data_size * + sizeof(short) + + 9); + print_frame_short( + "MS Data (TOT Cx) =", + array1dTo2d_short( + totCompData.node_data, + totCompData + .node_data_size, + totCompData.header + .sense_node), + totCompData.header.force_node, + totCompData.header.sense_node); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_READTOTSSCOMPDATA: + if (numberParam == 2) { + logError( + 0, + "%s Get TOT SS Compensation Data... \n", + tag); + res = readTotSelfSenseCompensationData( + cmd[1], &totComData); + if (res < OK) { + logError( + 0, + "%s Error reading TOT SS compensation data ERROR %08X\n", + tag, res); + } else { + logError( + 0, + "%s TOT SS Compensation Data Reading Finished! \n", + tag); + size = ((totComData.header.force_node + + totComData.header.sense_node) * + 2 * sizeof(short) + + 9); + print_frame_u16( + "SS Data TOT Ix_fm = ", + array1dTo2d_u16( + totComData.ix_fm, + totComData.header + .force_node, + totComData.header + .force_node), + 1, + totComData.header.force_node); + print_frame_short( + "SS Data TOT Cx_fm = ", + array1dTo2d_short( + totComData.cx_fm, + totComData.header + .force_node, + totComData.header + .force_node), + 1, + totComData.header.force_node); + print_frame_u16( + "SS Data TOT Ix_sn = ", + array1dTo2d_u16( + totComData.ix_sn, + totComData.header + .sense_node, + totComData.header + .sense_node), + 1, + totComData.header.sense_node); + print_frame_short( + "SS Data TOT Cx_sn = ", + array1dTo2d_short( + totComData.cx_sn, + totComData.header + .sense_node, + totComData.header + .sense_node), + 1, + totComData.header.sense_node); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_GETFWVER: + res = getFirmwareVersion(&fw_version, &config_id); + if (res < OK) { + logError( + 1, + "%s Error reading firmware version and config id ERROR %02X\n", + tag, res); + } else { + logError(0, + "%s getFirmwareVersion Finished! \n", + tag); + size += (4) * sizeof(u8); + } + break; + + case CMD_FLASHUNLOCK: + res = flash_unlock(); + if (res < OK) { + logError( + 1, + "%s Impossible Unlock Flash ERROR %08X\n", + tag, res); + } else { + logError(0, "%s Flash Unlock OK!\n", tag); + } + break; + + case CMD_READFWFILE: + if (numberParam == 2) { + logError(0, "%s Reading FW File... \n", tag); + res = readFwFile(PATH_FILE_FW, &fw, + funcToTest[1]); + if (res < OK) { + logError( + 0, + "%s Error reading FW File ERROR %08X\n", + tag, res); + } else { + logError(0, + "%s Read FW File Finished! \n", + tag); + } + kfree(fw.data); + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_FLASHPROCEDURE: + if (numberParam == 3) { + logError(0, + "%s Starting Flashing Procedure... \n", + tag); + res = flashProcedure(PATH_FILE_FW, cmd[1], + cmd[2]); + if (res < OK) { + logError( + 0, + "%s Error during flash procedure ERROR %08X\n", + tag, res); + } else { + logError( + 0, + "%s Flash Procedure Finished! \n", + tag); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_FLASHERASEUNLOCK: + res = flash_erase_unlock(); + if (res < OK) { + logError( + 0, + "%s Error during flash erase unlock... ERROR %08X\n", + tag, res); + } else { + logError(0, + "%s Flash Erase Unlock Finished! \n", + tag); + } + break; + + case CMD_FLASHERASEPAGE: + if (numberParam == 2) { + logError( + 0, + "%s Starting Flashing Page Erase... \n", + tag); + res = flash_erase_page_by_page(cmd[1]); + if (res < OK) { + logError( + 0, + "%s Error during flash page erase... ERROR %08X\n", + tag, res); + } else { + logError( + 0, + "%s Flash Page Erase Finished! \n", + tag); + } + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + /*ITO TEST */ + case CMD_ITOTEST: + res = production_test_ito(LIMITS_FILE, &tests); + break; + + /*Initialization */ + case CMD_INITTEST: + if (numberParam == 2) { + res = production_test_initialization(cmd[1]); + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_MSRAWTEST: + if (numberParam == 2) + res = production_test_ms_raw(LIMITS_FILE, + cmd[1], &tests); + else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_MSINITDATATEST: + if (numberParam == 2) + res = production_test_ms_cx(LIMITS_FILE, cmd[1], + &tests); + else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_SSRAWTEST: + if (numberParam == 2) + res = production_test_ss_raw(LIMITS_FILE, + cmd[1], &tests); + else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_SSINITDATATEST: + if (numberParam == 2) + res = production_test_ss_ix_cx(LIMITS_FILE, + cmd[1], &tests); + else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + /*PRODUCTION TEST */ + case CMD_MAINTEST: + if (numberParam == 3) + res = production_test_main(LIMITS_FILE, cmd[1], + cmd[2], &tests); + else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_FREELIMIT: + res = freeCurrentLimitsFile(); + break; + + case CMD_POWERCYCLE: + res = fts_chip_powercycle(info); + break; + + case CMD_GETLIMITSFILE: + if (numberParam >= 1) { + lim.data = NULL; + lim.size = 0; + if (numberParam == 1) + res = getLimitsFile(LIMITS_FILE, &lim); + else + res = getLimitsFile(path, &lim); + readData = lim.data; + fileSize = lim.size; + size += (fileSize * sizeof(u8)); + if (byte_call == 1) + size += sizeof(u32); + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_GETLIMITSFILE_BYTE: + if (numberParam >= 3) { + lim.data = NULL; + lim.size = 0; + + u8ToU16_be(&cmd[1], &byteToRead); + addr = ((u64)byteToRead) * 4; + + res = getLimitsFile(LIMITS_FILE, &lim); + + readData = lim.data; + fileSize = lim.size; + + if (fileSize > addr) { + logError( + 1, + "%s Limits dimension expected by Host is less than actual size: expected = %d, real = %d \n", + tag, byteToRead, fileSize); + res = ERROR_OP_NOT_ALLOW; + } + + size += (addr * sizeof(u8)); + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_GETFWFILE: + if (numberParam >= 1) { + if (numberParam == 1) + res = getFWdata(PATH_FILE_FW, &readData, + &fileSize); + else + res = getFWdata(path, &readData, + &fileSize); + + size += (fileSize * sizeof(u8)); + if (byte_call == 1) + size += sizeof(u32); + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + + case CMD_GETFWFILE_BYTE: + if (numberParam == 3) { + u8ToU16_be(&cmd[1], &byteToRead); + addr = ((u64)byteToRead) * 4; + + res = getFWdata(PATH_FILE_FW, &readData, + &fileSize); + if (fileSize > addr) { + logError( + 1, + "%s FW dimension expected by Host is less than actual size: expected = %d, real = %d \n", + tag, byteToRead, fileSize); + res = ERROR_OP_NOT_ALLOW; + } + + size += (addr * sizeof(u8)); + + } else { + logError(1, "%s Wrong number of parameters! \n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + break; + /* +* finish all the diagnostic command with a goto ERROR in order to skip the modification on driver_test_buff +* remember to set properly the limit and printed variables in order to make the seq_file logic to work +*/ + case CMD_DIAGNOSTIC: + index = 0; + size = 0; + fileSize = 256 * 1024 * sizeof(char); + driver_test_buff = (u8 *)kzalloc(fileSize, GFP_KERNEL); + readData = (u8 *)kmalloc( + (ERROR_DUMP_ROW_SIZE * ERROR_DUMP_COL_SIZE) * + sizeof(u8), + GFP_KERNEL); + if (driver_test_buff == NULL || readData == NULL) { + res = ERROR_ALLOC; + logError( + 1, + "%s Impossible allocate memory for buffers! ERROR %08X! \n", + tag, res); + goto END; + } + j = snprintf(&driver_test_buff[index], fileSize - index, + "DIAGNOSTIC TEST:\n1) I2C Test: "); + index += j; + + res = fts_writeReadU8UX(FTS_CMD_HW_REG_R, + ADDR_SIZE_HW_REG, ADDR_DCHIP_ID, + (u8 *)&temp, 2, DUMMY_HW_REG); + if (res < OK) { + logError( + 1, + "%s Error during I2C test: ERROR %08X! \n", + tag, res); + j = snprintf(&driver_test_buff[index], + fileSize - index, "ERROR %08X \n", + res); + index += j; + res = ERROR_OP_NOT_ALLOW; + goto END_DIAGNOSTIC; + } + + temp &= 0xFFFF; + logError(1, "%s Chip ID = %04X! \n", tag, temp); + j = snprintf(&driver_test_buff[index], fileSize - index, + "DATA = %04X, expected = %02X%02X \n", + temp, DCHIP_ID_1, DCHIP_ID_0); + index += j; + if (temp != ((DCHIP_ID_1 << 8) | DCHIP_ID_0)) { + logError( + 1, + "%s Wrong CHIP ID, Diagnostic failed! \n", + tag, res); + res = ERROR_OP_NOT_ALLOW; + goto END_DIAGNOSTIC; + } + + j = snprintf(&driver_test_buff[index], fileSize - index, + "Present Driver Mode: %08X \n", + info->mode); + index += j; + + j = snprintf(&driver_test_buff[index], fileSize - index, + "2) FW running: Sensing On..."); + index += j; + logError(1, "%s Sensing On! \n", tag, temp); + readData[0] = FTS_CMD_SCAN_MODE; + readData[1] = SCAN_MODE_ACTIVE; + readData[2] = 0x1; + fts_write(readData, 3); + res = checkEcho(readData, 3); + if (res < OK) { + logError(1, + "%s No Echo received.. ERROR %08X !\n", + tag, res); + j = snprintf(&driver_test_buff[index], + fileSize - index, + "No echo found... ERROR %08X!\n", + res); + index += j; + goto END_DIAGNOSTIC; + } else { + logError(1, "%s Echo FOUND... OK!\n", tag, res); + j = snprintf(&driver_test_buff[index], + fileSize - index, + "Echo FOUND... OK!\n"); + index += j; + } + + logError(1, "%s Reading Frames...! \n", tag, temp); + j = snprintf(&driver_test_buff[index], fileSize - index, + "3) Read Frames: \n"); + index += j; + for (temp = 0; temp < DIAGNOSTIC_NUM_FRAME; temp++) { + logError(1, "%s Iteration n. %d...\n", tag, + temp + 1); + j = snprintf(&driver_test_buff[index], + fileSize - index, + "Iteration n. %d...\n", temp + 1); + index += j; + for (addr = 0; addr < 3; addr++) { + switch (addr) { + case 0: + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "MS RAW FRAME ="); + index += j; + res |= getMSFrame3(MS_RAW, + &frameMS); + break; + case 2: + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "MS STRENGTH FRAME ="); + index += j; + res |= getMSFrame3(MS_STRENGTH, + &frameMS); + break; + case 1: + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "MS BASELINE FRAME ="); + index += j; + res |= getMSFrame3(MS_BASELINE, + &frameMS); + break; + } + if (res < OK) { + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "No data! ERROR %08X \n", + res); + index += j; + } else { + for (address = 0; + address < + frameMS.node_data_size; + address++) { + if (address % + frameMS.header + .sense_node == + 0) { + j = snprintf( + &driver_test_buff + [index], + fileSize - + index, + "\n"); + index += j; + } + j = snprintf( + &driver_test_buff + [index], + fileSize - + index, + "%5d, ", + frameMS.node_data + [address]); + index += j; + } + j = snprintf( + &driver_test_buff[index], + fileSize - index, "\n"); + index += j; + } + if (frameMS.node_data != NULL) + kfree(frameMS.node_data); + } + for (addr = 0; addr < 3; addr++) { + switch (addr) { + case 0: + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "SS RAW FRAME = \n"); + index += j; + res |= getSSFrame3(SS_RAW, + &frameSS); + break; + case 2: + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "SS STRENGTH FRAME = \n"); + index += j; + res |= getSSFrame3(SS_STRENGTH, + &frameSS); + break; + case 1: + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "SS BASELINE FRAME = \n"); + index += j; + res |= getSSFrame3(SS_BASELINE, + &frameSS); + break; + } + if (res < OK) { + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "No data! ERROR %08X \n", + res); + index += j; + } else { + for (address = 0; + address < + frameSS.header.force_node; + address++) { + j = snprintf( + &driver_test_buff + [index], + fileSize - + index, + "%d\n", + frameSS.force_data + [address]); + + index += j; + } + for (address = 0; + address < + frameSS.header.sense_node; + address++) { + j = snprintf( + &driver_test_buff + [index], + fileSize - + index, + "%d, ", + frameSS.sense_data + [address]); + + index += j; + } + j = snprintf( + &driver_test_buff[index], + fileSize - index, "\n"); + index += j; + } + if (frameSS.force_data != NULL) + kfree(frameSS.force_data); + if (frameSS.sense_data != NULL) + kfree(frameSS.sense_data); + } + } + + logError(1, "%s Reading error info... \n", tag, temp); + j = snprintf(&driver_test_buff[index], fileSize - index, + "4) FW INFO DUMP: "); + index += j; + temp = dumpErrorInfo(readData, + ERROR_DUMP_ROW_SIZE * + ERROR_DUMP_COL_SIZE); + if (temp < OK) { + logError(1, + "%s Error during dump: ERROR %08X! \n", + tag, res); + j = snprintf(&driver_test_buff[index], + fileSize - index, "ERROR %08X \n", + temp); + index += j; + } else { + logError(1, "%s DUMP OK! \n", tag, res); + for (temp = 0; + temp < + ERROR_DUMP_ROW_SIZE * ERROR_DUMP_COL_SIZE; + temp++) { + if (temp % ERROR_DUMP_COL_SIZE == 0) { + j = snprintf( + &driver_test_buff[index], + fileSize - index, + "\n%2d - ", + temp / ERROR_DUMP_COL_SIZE); + index += j; + } + j = snprintf(&driver_test_buff[index], + fileSize - index, "%02X ", + readData[temp]); + index += j; + } + } + res |= temp; + +END_DIAGNOSTIC: + if (res < OK) { + j = snprintf(&driver_test_buff[index], + fileSize - index, + "\nRESULT = FAIL \n"); + index += j; + } else { + j = snprintf(&driver_test_buff[index], + fileSize - index, + "\nRESULT = FINISHED \n"); + index += j; + } + limit = index; + printed = 0; + goto ERROR; + break; + case CMD_CHANGE_SAD: + res = changeSAD(cmd[1]); + break; + + default: + logError(1, "%s COMMAND ID NOT VALID!!! \n", tag); + res = ERROR_OP_NOT_ALLOW; + break; + } + + } else { + logError( + 1, + "%s NO COMMAND SPECIFIED!!! do: 'echo [cmd_code] [args] > stm_fts_cmd' before looking for result!\n", + tag); + res = ERROR_OP_NOT_ALLOW; + } + +END: + if (driver_test_buff != NULL) { + logError( + 1, + "%s Consecutive echo on the file node, free the buffer with the previous result\n", + tag); + kfree(driver_test_buff); + } + + if (byte_call == 0) { + size *= 2; + size += 2; + } else { + if (bin_output != 1) { + size *= 2; + size -= 1; + } else + size += 1; + } + + logError(0, "%s Size = %d\n", tag, size); + driver_test_buff = (u8 *)kzalloc(size, GFP_KERNEL); + logError(0, "%s Finish to allocate memory! \n", tag); + if (driver_test_buff == NULL) { + logError(0, + "%s Unable to allocate driver_test_buff! ERROR %08X\n", + tag, ERROR_ALLOC); + goto ERROR; + } + + if (byte_call == 0) { + index = 0; + snprintf(&driver_test_buff[index], 3, "{ "); + index += 2; + snprintf(&driver_test_buff[index], 9, "%08X", res); + + index += 8; + if (res >= OK) { + /*all the other cases are already fine printing only the res. */ + switch (funcToTest[0]) { + case CMD_VERSION: + case CMD_READ: + case CMD_WRITEREAD: + case CMD_WRITETHENWRITEREAD: + case CMD_WRITEREADU8UX: + case CMD_WRITEU8UXTHENWRITEREADU8UX: + case CMD_READCONFIG: + case CMD_POLLFOREVENT: + if (mess.dummy == 1) + j = 1; + else + j = 0; + for (; j < byteToRead + mess.dummy; j++) { + snprintf(&driver_test_buff[index], 3, + "%02X", readData[j]); + index += 2; + } + break; + case CMD_GETFWFILE: + case CMD_GETLIMITSFILE: + logError(0, "%s Start To parse! \n", tag); + for (j = 0; j < fileSize; j++) { + snprintf(&driver_test_buff[index], 3, + "%02X", readData[j]); + index += 2; + } + logError(0, "%s Finish to parse! \n", tag); + break; + case CMD_GETFORCELEN: + case CMD_GETSENSELEN: + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)temp); + index += 2; + + break; + + case CMD_GETMSFRAME: + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)frameMS.header.force_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)frameMS.header.sense_node); + index += 2; + + for (j = 0; j < frameMS.node_data_size; j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (frameMS.node_data[j] & + 0xFF00) >> + 8, + frameMS.node_data[j] & 0xFF); + index += 4; + } + + kfree(frameMS.node_data); + break; + + case CMD_GETSSFRAME: + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)frameSS.header.force_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)frameSS.header.sense_node); + index += 2; + for (j = 0; j < frameSS.header.force_node; + j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (frameSS.force_data[j] & + 0xFF00) >> + 8, + frameSS.force_data[j] & 0xFF); + index += 4; + } + + for (j = 0; j < frameSS.header.sense_node; + j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (frameSS.sense_data[j] & + 0xFF00) >> + 8, + frameSS.sense_data[j] & 0xFF); + index += 4; + } + + kfree(frameSS.force_data); + kfree(frameSS.sense_data); + break; + + case CMD_READMSCOMPDATA: + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)compData.header.type); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)compData.header.force_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)compData.header.sense_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + compData.cx1 & 0xFF); + index += 2; + + for (j = 0; j < compData.node_data_size; j++) { + snprintf(&driver_test_buff[index], 3, + "%02X", + compData.node_data[j] & 0xFF); + index += 2; + } + + kfree(compData.node_data); + break; + + case CMD_READSSCOMPDATA: + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)comData.header.type); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + comData.header.force_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + comData.header.sense_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + comData.f_ix1 & 0xFF); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + comData.s_ix1 & 0xFF); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + comData.f_cx1 & 0xFF); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + comData.s_cx1 & 0xFF); + index += 2; + + for (j = 0; j < comData.header.force_node; + j++) { + snprintf(&driver_test_buff[index], 3, + "%02X", + comData.ix2_fm[j] & 0xFF); + index += 2; + } + + for (j = 0; j < comData.header.sense_node; + j++) { + snprintf(&driver_test_buff[index], 3, + "%02X", + comData.ix2_sn[j] & 0xFF); + index += 2; + } + + for (j = 0; j < comData.header.force_node; + j++) { + snprintf(&driver_test_buff[index], 3, + "%02X", + comData.cx2_fm[j] & 0xFF); + + index += 2; + } + + for (j = 0; j < comData.header.sense_node; + j++) { + snprintf(&driver_test_buff[index], 3, + "%02X", + comData.cx2_sn[j] & 0xFF); + index += 2; + } + + kfree(comData.ix2_fm); + kfree(comData.ix2_sn); + kfree(comData.cx2_fm); + kfree(comData.cx2_sn); + break; + + case CMD_READTOTMSCOMPDATA: + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)totCompData.header.type); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)totCompData.header.force_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)totCompData.header.sense_node); + + index += 2; + + for (j = 0; j < totCompData.node_data_size; + j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (totCompData.node_data[j] & + 0xFF00) >> + 8, + totCompData.node_data[j] & + 0xFF); + index += 4; + } + + kfree(totCompData.node_data); + break; + + case CMD_READTOTSSCOMPDATA: + snprintf(&driver_test_buff[index], 3, "%02X", + (u8)totComData.header.type); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + totComData.header.force_node); + index += 2; + + snprintf(&driver_test_buff[index], 3, "%02X", + totComData.header.sense_node); + index += 2; + + for (j = 0; j < totComData.header.force_node; + j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (totComData.ix_fm[j] & + 0xFF00) >> + 8, + totComData.ix_fm[j] & 0xFF); + index += 4; + } + + for (j = 0; j < totComData.header.sense_node; + j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (totComData.ix_sn[j] & + 0xFF00) >> + 8, + totComData.ix_sn[j] & 0xFF); + index += 4; + } + + for (j = 0; j < totComData.header.force_node; + j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (totComData.cx_fm[j] & + 0xFF00) >> + 8, + totComData.cx_fm[j] & 0xFF); + + index += 4; + } + + for (j = 0; j < totComData.header.sense_node; + j++) { + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (totComData.cx_sn[j] & + 0xFF00) >> + 8, + totComData.cx_sn[j] & 0xFF); + index += 4; + } + + kfree(totComData.ix_fm); + kfree(totComData.ix_sn); + kfree(totComData.cx_fm); + kfree(totComData.cx_sn); + break; + + case CMD_GETFWVER: + snprintf(&driver_test_buff[index], 5, "%04X", + fw_version); + index += 4; + + snprintf(&driver_test_buff[index], 5, "%04X", + config_id); + index += 4; + break; + + case CMD_READCOMPDATAHEAD: + snprintf(&driver_test_buff[index], 3, "%02X", + dataHead.type); + index += 2; + break; + + default: + break; + } + } + + snprintf(&driver_test_buff[index], 4, " }\n"); + limit = size - 1; + printed = 0; + } else { + driver_test_buff[index++] = MESSAGE_START_BYTE; + if (bin_output == 1) { + driver_test_buff[index++] = (size & 0xFF00) >> 8; + driver_test_buff[index++] = (size & 0x00FF); + + driver_test_buff[index++] = (mess.counter & 0xFF00) >> + 8; + driver_test_buff[index++] = (mess.counter & 0x00FF); + + driver_test_buff[index++] = (mess.action & 0xFF00) >> 8; + driver_test_buff[index++] = (mess.action & 0x00FF); + + driver_test_buff[index++] = (res & 0xFF00) >> 8; + driver_test_buff[index++] = (res & 0x00FF); + + } else { + if (funcToTest[0] == CMD_GETLIMITSFILE_BYTE || + funcToTest[0] == CMD_GETFWFILE_BYTE) + snprintf(&driver_test_buff[index], 5, + "%02X%02X", + (((fileSize + 3) / 4) & 0xFF00) >> 8, + ((fileSize + 3) / 4) & 0x00FF); + else + snprintf(&driver_test_buff[index], 5, + "%02X%02X", (size & 0xFF00) >> 8, + size & 0xFF); + index += 4; + index += snprintf(&driver_test_buff[index], 5, "%04X", + (u16)mess.counter); + index += snprintf(&driver_test_buff[index], 5, "%04X", + (u16)mess.action); + index += snprintf(&driver_test_buff[index], 5, + "%02X%02X", (res & 0xFF00) >> 8, + res & 0xFF); + } + + switch (funcToTest[0]) { + case CMD_VERSION_BYTE: + case CMD_READ_BYTE: + case CMD_WRITEREAD_BYTE: + case CMD_WRITETHENWRITEREAD_BYTE: + case CMD_WRITEREADU8UX_BYTE: + case CMD_WRITEU8UXTHENWRITEREADU8UX_BYTE: + if (bin_output == 1) { + if (mess.dummy == 1) + memcpy(&driver_test_buff[index], + &readData[1], byteToRead); + else + memcpy(&driver_test_buff[index], + readData, byteToRead); + index += byteToRead; + } else { + j = mess.dummy; + for (; j < byteToRead + mess.dummy; j++) + index += snprintf( + &driver_test_buff[index], 3, + "%02X", (u8)readData[j]); + } + break; + + case CMD_GETLIMITSFILE_BYTE: + case CMD_GETFWFILE_BYTE: + if (bin_output == 1) { + driver_test_buff[1] = + (((fileSize + 3) / 4) & 0xFF00) >> 8; + driver_test_buff[2] = + (((fileSize + 3) / 4) & 0x00FF); + + if (readData != NULL) { + memcpy(&driver_test_buff[index], + readData, fileSize); + } else { + logError( + 0, + "%s readData = NULL... returning junk data!", + tag); + } + index += addr; + } else { + for (j = 0; j < fileSize; j++) { + index += snprintf( + &driver_test_buff[index], 3, + "%02X", (u8)readData[j]); + } + for (; j < addr; j++) + index += snprintf( + &driver_test_buff[index], 3, + "%02X", 0); + } + break; + default: + break; + } + + driver_test_buff[index++] = MESSAGE_END_BYTE; + driver_test_buff[index] = '\n'; + limit = size; + printed = 0; + } +ERROR: + numberParam = 0; + if (readData != NULL) + kfree(readData); + if (cmd) + kfree(cmd); + return count; +} + +/** @}*/ + +/** + * file_operations struct which define the functions for the canonical operation on a device file node (open. read, write etc.) + */ +static struct file_operations fts_driver_test_ops = { + .open = fts_open, + .read = seq_read, + .write = fts_driver_test_write, + .llseek = seq_lseek, + .release = seq_release +}; + +/*****************************************************************************/ + +/** +* This function is called in the probe to initialize and create the directory /proc/fts and the driver test file node DRIVER_TEST_FILE_NODE into the /proc file system +* @return OK if success or an error code which specify the type of error encountered +*/ +int fts_proc_init(void) +{ + struct proc_dir_entry *entry; + + int retval = 0; + + fts_dir = proc_mkdir_data("fts", 0777, NULL, NULL); + if (fts_dir == NULL) { + retval = -ENOMEM; + goto out; + } + + entry = proc_create(DRIVER_TEST_FILE_NODE, 0644, fts_dir, + &fts_driver_test_ops); + + if (entry) { + logError(1, "%s %s: proc entry CREATED! \n", tag, __func__); + } else { + logError(1, "%s %s: error creating proc entry! \n", tag, + __func__); + retval = -ENOMEM; + goto badfile; + } + return OK; +badfile: + remove_proc_entry("fts", NULL); +out: + return retval; +} + +/** +* Delete and Clean from the file system, all the references to the driver test file node +* @return OK +*/ +int fts_proc_remove(void) +{ + remove_proc_entry(DRIVER_TEST_FILE_NODE, fts_dir); + remove_proc_entry("fts", NULL); + return OK; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Kconfig b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Kconfig new file mode 100644 index 000000000000..e894eb406199 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Kconfig @@ -0,0 +1,45 @@ +# +# Goodix touchscreen driver configuration +# +menuconfig TOUCHSCREEN_GOODIX_GTX8 + bool "Goodix GTx8 touchscreen" + depends on I2C + help + Say Y here if you have a Goodix GTx5xx touchscreen connected + to your system. + + If unsure, say N. + +if TOUCHSCREEN_GOODIX_GTX8 + +config TOUCHSCREEN_GOODIX_GTX8_UPDATE + tristate "Goodix GTx8 firmware update module" + default y + help + Say Y here to enable support for doing firmware update. + + If unsure, say N. + + To compile this driver as a module, choose M here. + +config TOUCHSCREEN_GOODIX_GTX8_GESTURE + tristate "Goodix GTx8 gesture wakeup feature" + default y + help + Say Y here to enable support for gesture wakeup feature.. + + If unsure, say N. + + To compile this driver as a module, choose M here. + +config TOUCHSCREEN_GOODIX_GTX8_TOOLS + tristate "Goodix touch tools support" + default y + help + Say Y here to enable debug tools. + + If unsure, say N. + + To compile this driver as a module, choose M here. + +endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Makefile b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Makefile new file mode 100644 index 000000000000..ed921866fb75 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/Makefile @@ -0,0 +1,7 @@ +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8) += goodix_ts_i2c.o +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8) += goodix_ts_core.o +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8) += goodix_cfg_bin.o +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8_UPDATE) += goodix_gtx8_update.o +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8_GESTURE) += goodix_ts_gesture.o +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8_TOOLS) += goodix_ts_tools.o +obj-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8) += test_core/ diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c new file mode 100644 index 000000000000..d1025106a6a5 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c @@ -0,0 +1,674 @@ +#include "goodix_cfg_bin.h" +#include + +extern int goodix_i2c_write(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len); +extern int goodix_i2c_read(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len); +extern int goodix_hw_reset(struct goodix_ts_device *dev); +extern struct goodix_module goodix_modules; + +int goodix_start_cfg_bin(struct goodix_ts_core *ts_core) +{ + struct task_struct *cfg_bin_thrd; + /* create and run update thread */ + ts_err("enter::%s\n", __func__); + cfg_bin_thrd = kthread_run(goodix_cfg_bin_proc, ts_core, + "goodix-parse_cfg_bin"); + if (IS_ERR_OR_NULL(cfg_bin_thrd)) { + ts_err("Failed to create update thread:%ld", + PTR_ERR(cfg_bin_thrd)); + return -EFAULT; + } + return 0; +} + +int goodix_get_lockdowninfo(struct goodix_ts_core *ts_core) +{ + int ret = 0; + struct goodix_ts_device *ts_dev = ts_core->ts_dev; + + ret = ts_dev->hw_ops->read(ts_dev, TS_LOCKDOWN_REG, + ts_core->lockdown_info, + GOODIX_LOCKDOWN_SIZE); + if (ret) { + ts_err("can't get lockdown"); + return -EINVAL; + } + ts_info("lockdown is:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x", + ts_core->lockdown_info[0], ts_core->lockdown_info[1], + ts_core->lockdown_info[2], ts_core->lockdown_info[3], + ts_core->lockdown_info[4], ts_core->lockdown_info[5], + ts_core->lockdown_info[6], ts_core->lockdown_info[7]); + return 0; +} + +int goodix_parse_cfg_bin(struct goodix_cfg_bin *cfg_bin) +{ + u8 checksum; + int i, r; + u16 offset1, offset2; + if (!cfg_bin->bin_data || cfg_bin->bin_data_len == 0) { + ts_err("NO cfg_bin data, cfg_bin data length:%d", + cfg_bin->bin_data_len); + r = -EINVAL; + goto exit; + } + + /* copy cfg_bin head info */ + if (cfg_bin->bin_data_len < sizeof(struct goodix_cfg_bin_head)) { + ts_err("Invalid cfg_bin size:%d", cfg_bin->bin_data_len); + r = -EINVAL; + goto exit; + } + memcpy(&cfg_bin->head, cfg_bin->bin_data, + sizeof(struct goodix_cfg_bin_head)); + cfg_bin->head.bin_len = le32_to_cpu(cfg_bin->head.bin_len); + + /*check length*/ + if (cfg_bin->bin_data_len != cfg_bin->head.bin_len) { + ts_err("cfg_bin length error,len in cfg_bin:%d, len of firmware:%d", + cfg_bin->head.bin_len, cfg_bin->bin_data_len); + r = -EINVAL; + goto exit; + } + + /*check cfg_bin valid*/ + checksum = 0; + for (i = TS_BIN_VERSION_START_INDEX; i < cfg_bin->bin_data_len; i++) { + checksum += cfg_bin->bin_data[i]; + } + if (checksum != cfg_bin->head.checksum) { + ts_err("cfg_bin checksum ERROR, checksum in cfg_bin:0x%02x, checksum caculate:0x%02x", + cfg_bin->head.checksum, checksum); + r = -EINVAL; + goto exit; + } + + /*allocate memory for cfg packages*/ + cfg_bin->cfg_pkgs = kzalloc(sizeof(struct goodix_cfg_package) * + cfg_bin->head.pkg_num, + GFP_KERNEL); + if (!cfg_bin->cfg_pkgs) { + ts_err("cfg_pkgs, allocate memory ERROR"); + r = -ENOMEM; + goto exit; + } + /*get cfg_pkg's info*/ + for (i = 0; i < cfg_bin->head.pkg_num; i++) { + /*get cfg pkg length*/ + if (i == cfg_bin->head.pkg_num - 1) { + offset1 = cfg_bin->bin_data[TS_CFG_BIN_HEAD_LEN + + i * TS_CFG_OFFSET_LEN] + + (cfg_bin->bin_data[TS_CFG_BIN_HEAD_LEN + + i * TS_CFG_OFFSET_LEN + 1] + << 8); + cfg_bin->cfg_pkgs[i].pkg_len = + cfg_bin->bin_data_len - offset1; + } else { + offset1 = cfg_bin->bin_data[TS_CFG_BIN_HEAD_LEN + + i * TS_CFG_OFFSET_LEN] + + (cfg_bin->bin_data[TS_CFG_BIN_HEAD_LEN + + i * TS_CFG_OFFSET_LEN + 1] + << 8); + offset2 = cfg_bin->bin_data[TS_CFG_BIN_HEAD_LEN + + i * TS_CFG_OFFSET_LEN + 2] + + (cfg_bin->bin_data[TS_CFG_BIN_HEAD_LEN + + i * TS_CFG_OFFSET_LEN + 3] + << 8); + if (offset2 <= offset1) { + ts_err("offset error,pkg:%d, offset1:%d, offset2:%d", + i, offset1, offset2); + r = -EINVAL; + goto exit; + } + cfg_bin->cfg_pkgs[i].pkg_len = offset2 - offset1; + } + /*get cfg pkg head*/ + memcpy(&cfg_bin->cfg_pkgs[i].cnst_info, + &cfg_bin->bin_data[offset1], TS_PKG_CONST_INFO_LEN); + memcpy(&cfg_bin->cfg_pkgs[i].reg_info, + &cfg_bin->bin_data[offset1 + TS_PKG_CONST_INFO_LEN], + TS_PKG_REG_INFO_LEN); + /*compatible little edition and big edition*/ + goodix_cfg_pkg_leToCpu(&cfg_bin->cfg_pkgs[i]); + + /*get configuration data*/ + cfg_bin->cfg_pkgs[i].cfg = + &cfg_bin->bin_data[offset1 + TS_PKG_HEAD_LEN]; + } + + /*debug, print pkg information*/ + for (i = 0; i < cfg_bin->head.pkg_num; i++) { + ts_info("---------------------------------------------"); + ts_info("------package:%d------", i + 1); + ts_info("package len:%04x", + cfg_bin->cfg_pkgs[i].cnst_info.pkg_len); + ts_info("package ic_type:%s", + cfg_bin->cfg_pkgs[i].cnst_info.ic_type); + ts_info("package cfg_type:%01x", + cfg_bin->cfg_pkgs[i].cnst_info.cfg_type); + ts_info("package sensor_id:%01x", + cfg_bin->cfg_pkgs[i].cnst_info.sensor_id); + ts_info("package hw_pid:%s", + cfg_bin->cfg_pkgs[i].cnst_info.hw_pid); + ts_info("package hw_vid:%s", + cfg_bin->cfg_pkgs[i].cnst_info.hw_vid); + ts_info("package fw_mask_version:%s", + cfg_bin->cfg_pkgs[i].cnst_info.fw_mask); + ts_info("package fw_patch_version:%s", + cfg_bin->cfg_pkgs[i].cnst_info.fw_patch); + ts_info("package x_res_offset:%02x", + cfg_bin->cfg_pkgs[i].cnst_info.x_res_offset); + ts_info("package y_res_offset:%02x", + cfg_bin->cfg_pkgs[i].cnst_info.y_res_offset); + ts_info("package trigger_offset:%02x", + cfg_bin->cfg_pkgs[i].cnst_info.trigger_offset); + + ts_info(""); + ts_info("send_cfg_flag reg:%02x", + cfg_bin->cfg_pkgs[i].reg_info.cfg_send_flag.addr); + ts_info("version base reg:%02x, len:%d", + cfg_bin->cfg_pkgs[i].reg_info.version_base.addr, + cfg_bin->cfg_pkgs[i].reg_info.version_base.reserved1); + ts_info("pid reg:%02x", cfg_bin->cfg_pkgs[i].reg_info.pid.addr); + ts_info("vid reg:%02x", cfg_bin->cfg_pkgs[i].reg_info.vid.addr); + ts_info("sensor_id reg:%02x", + cfg_bin->cfg_pkgs[i].reg_info.sensor_id.addr); + ts_info("fw_status reg:%02x", + cfg_bin->cfg_pkgs[i].reg_info.fw_status.addr); + ts_info("cfg_addr reg:%02x", + cfg_bin->cfg_pkgs[i].reg_info.cfg_addr.addr); + ts_info("esd reg:%02x", cfg_bin->cfg_pkgs[i].reg_info.esd.addr); + ts_info("command reg:%02x", + cfg_bin->cfg_pkgs[i].reg_info.command.addr); + ts_info("coor:%02x", cfg_bin->cfg_pkgs[i].reg_info.coor.addr); + ts_info("gesture:%02x", + cfg_bin->cfg_pkgs[i].reg_info.gesture.addr); + ts_info("fw_request:%02x", + cfg_bin->cfg_pkgs[i].reg_info.fw_request.addr); + ts_info("proximity:%02x", + cfg_bin->cfg_pkgs[i].reg_info.proximity.addr); + ts_info("--------------------------------------------"); + } + r = 0; +exit: + return r; +} + +int goodix_cfg_bin_proc(void *data) +{ + struct goodix_ts_core *core_data = data; + struct goodix_ts_device *ts_dev = core_data->ts_dev; + + struct device *dev = ts_dev->dev; + int r; + +#ifdef CONFIG_GOODIX_HWINFO + u8 *tp_maker; +#endif + struct goodix_cfg_bin *cfg_bin = + kzalloc(sizeof(struct goodix_cfg_bin), GFP_KERNEL); + if (!cfg_bin) { + ts_err("Failed to alloc memory for cfg_bin"); + r = -ENOMEM; + goto exit; + } + /*get cfg_bin from file system*/ + r = goodix_read_cfg_bin(dev, cfg_bin); + if (r < 0) { + ts_err("read cfg_bin from /etc/firmware FAILED"); + goto exit; + } + /*parse cfg bin*/ + r = goodix_parse_cfg_bin(cfg_bin); + if (!r) { + ts_info("parse cfg bin SUCCESS"); + } else { + ts_err("parse cfg bin FAILED"); + goto exit; + } + /*init i2c_set_doze_mode para*/ + ts_dev->doze_mode_set_count = 0; + mutex_init(&ts_dev->doze_mode_lock); + /*get register address and configuration from cfg bin*/ + r = goodix_get_reg_and_cfg(ts_dev, cfg_bin); + if (!r) { + ts_info("get reg and cfg from cfg_bin SUCCESS"); + } else { + if (r != -EBUS) { + ts_err("get reg and cfg from cfg_bin FAILED, update fw then retry"); + goodix_modules.core_data = core_data; + goodix_modules.core_exit = false; + complete_all(&goodix_modules.core_comp); + goto exit; + } else { + ts_err("get reg and cfg from cfg_bin FAILED, I2C com ERROR"); + goto exit; + } + } + /*init i2c_set_doze_mode para*/ + ts_dev->doze_mode_set_count = 0; + mutex_init(&ts_dev->doze_mode_lock); + + ts_info("cfg_send_flag:0x%04x", ts_dev->reg.cfg_send_flag); + ts_info("pid:0x%04x", ts_dev->reg.pid); + ts_info("vid:0x%04x", ts_dev->reg.vid); + ts_info("sensor_id:0x%04x", ts_dev->reg.sensor_id); + ts_info("fw_mask:0x%04x", ts_dev->reg.fw_mask); + ts_info("fw_status:0x%04x", ts_dev->reg.fw_status); + ts_info("cfg_addr:0x%04x", ts_dev->reg.cfg_addr); + ts_info("esd:0x%04x", ts_dev->reg.esd); + ts_info("command:0x%04x", ts_dev->reg.command); + ts_info("coor:0x%04x", ts_dev->reg.coor); + ts_info("gesture:0x%04x", ts_dev->reg.gesture); + ts_info("fw_request:0x%04x", ts_dev->reg.fw_request); + ts_info("proximity:0x%04x", ts_dev->reg.proximity); + + /* initialize firmware */ + r = ts_dev->hw_ops->init(ts_dev); + if (-EBUS == r) + goto exit; + + /* alloc/config/register input device */ + r = goodix_ts_input_dev_config(core_data); + if (r < 0) + goto exit; + + /* request irq line */ + r = goodix_ts_irq_setup(core_data); + if (r < 0) + goto exit; + + /*set flag, prevent fwupdate module parse cfg_group again*/ + core_data->cfg_group_parsed = true; + + /* inform the external module manager that + * touch core layer is ready now */ + goodix_modules.core_data = core_data; + goodix_modules.core_exit = false; + /*complete_all(&goodix_modules.core_comp);*/ + +#ifdef CONFIG_DRM + core_data->fb_notifier.notifier_call = goodix_ts_fb_notifier_callback; + if (drm_register_client(&core_data->fb_notifier)) + ts_err("Failed to register fb notifier client:%d", r); +#elif defined(CONFIG_HAS_EARLYSUSPEND) + core_data->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1; + core_data->early_suspend.resume = goodix_ts_lateresume; + core_data->early_suspend.suspend = goodix_ts_earlysuspend; + register_early_suspend(&core_data->early_suspend); +#endif + goodix_get_lockdowninfo(core_data); + + /* esd protector */ + goodix_ts_esd_init(core_data); + + /* generic notifier callback */ + core_data->ts_notifier.notifier_call = goodix_generic_noti_callback; + goodix_ts_register_notifier(&core_data->ts_notifier); + +#ifdef CONFIG_GOODIX_HWINFO + tp_maker = kzalloc(20, GFP_KERNEL); + if (tp_maker == NULL) + ts_err("fail to alloc vendor name memory\n"); + else { + kfree(tp_maker); + tp_maker = NULL; + } +#endif + +exit: + complete_all(&goodix_modules.core_comp); + if (cfg_bin->cfg_pkgs) { + kfree(cfg_bin->cfg_pkgs); + cfg_bin->cfg_pkgs = NULL; + } + if (cfg_bin->bin_data) { + kfree(cfg_bin->bin_data); + cfg_bin->bin_data = NULL; + } + return r; +} + +int goodix_get_reg_and_cfg(struct goodix_ts_device *ts_dev, + struct goodix_cfg_bin *cfg_bin) +{ + int i; + u16 addr; + u8 read_len; + struct goodix_cfg_package *normal_pkg, *high_sense_pkg; + char temp_sensor_id = -1; + u8 temp_fw_mask[TS_CFG_BLOCK_FW_MASK_LEN] = { 0x00 }; + u8 temp_pid[TS_CFG_BLOCK_PID_LEN] = { 0x00 }; + int r = -EINVAL; + normal_pkg = NULL; + high_sense_pkg = NULL; + + if (!cfg_bin->head.pkg_num || !cfg_bin->cfg_pkgs) { + ts_err("there is none cfg package, pkg_num:%d", + cfg_bin->head.pkg_num); + r = -EINVAL; + goto exit; + } + + /*select suitable cfg packages*/ + for (i = 0; i < cfg_bin->head.pkg_num; i++) { + /*get ic type*/ + if (!strncmp(cfg_bin->cfg_pkgs[i].cnst_info.ic_type, "nanjing", + sizeof(cfg_bin->cfg_pkgs[i].cnst_info.ic_type))) + ts_dev->ic_type = IC_TYPE_NANJING; + else if (!strncmp( + cfg_bin->cfg_pkgs[i].cnst_info.ic_type, + "normandy", + sizeof(cfg_bin->cfg_pkgs[i].cnst_info.ic_type))) + ts_dev->ic_type = IC_TYPE_NORMANDY; + else + ts_err("get ic type FAILED, unknow ic type from cfg_bin:%s", + cfg_bin->cfg_pkgs[i].cnst_info.ic_type); + + ts_info("ic_type:%d", ts_dev->ic_type); + /*contrast sensor id*/ + addr = cfg_bin->cfg_pkgs[i].reg_info.sensor_id.addr; + if (!addr) { + ts_info("pkg:%d, sensor_id reg is NULL", i); + continue; + } + r = goodix_i2c_read(ts_dev, addr, &temp_sensor_id, 1); + if (r < 0) { + ts_err("read sensor id FAILED,I2C ERROR, pkg:%d, sensor_id reg:0x%02x", + i, addr); + goto exit; + } else { + /*sensor.reserved1 is a mask, if it's not ZERO, use it*/ + if (cfg_bin->cfg_pkgs[i].reg_info.sensor_id.reserved1 != + 0) + temp_sensor_id &= + cfg_bin->cfg_pkgs[i] + .reg_info.sensor_id.reserved1; + if (temp_sensor_id != + cfg_bin->cfg_pkgs[i].cnst_info.sensor_id) { + ts_err("pkg:%d, sensor id contrast FAILED, reg:0x%02x", + i, addr); + ts_err("sensor_id from i2c:%d, sensor_id of cfg bin:%d", + temp_sensor_id, + cfg_bin->cfg_pkgs[i].cnst_info.sensor_id); + continue; + } + } + + /*contrast fw_mask, if this reg is null, skip this step*/ + addr = cfg_bin->cfg_pkgs[i].reg_info.fw_mask.addr; + if (!addr || !cfg_bin->cfg_pkgs[i].cnst_info.fw_mask[0]) { + ts_err("pkg:%d, fw_mask of cfg bin is NULL, Skip!!", i); + } else { + r = goodix_i2c_read(ts_dev, addr, temp_fw_mask, + sizeof(temp_fw_mask)); + if (r < 0) { + ts_err("read fw_mask FAILED, I2C ERROR, pkg: %d, fw_mask reg:0x%02x", + i, addr); + goto exit; + } else if (strncmp(temp_fw_mask, + cfg_bin->cfg_pkgs[i] + .cnst_info.fw_mask, + sizeof(temp_fw_mask))) { + ts_err("pkg:%d, fw_mask contrast FAILED, reg:0x%02x,", + i, addr); + ts_err("mask from i2c:%s, mask of cfg bin:%s", + temp_fw_mask, + cfg_bin->cfg_pkgs[i].cnst_info.fw_mask); + continue; + } + } + + /*contrast pid*/ + addr = cfg_bin->cfg_pkgs[i].reg_info.pid.addr; + read_len = cfg_bin->cfg_pkgs[i].reg_info.pid.reserved1; + if (!addr) { + ts_err("pkg:%d, pid reg is NULL", i); + continue; + } + if (read_len <= 0 || read_len > TS_CFG_BLOCK_PID_LEN) { + ts_err("pkg:%d, hw_pid length ERROR, len:%d", i, + read_len); + continue; + } + r = goodix_i2c_read(ts_dev, addr, temp_pid, read_len); + if (r < 0) { + ts_err("read pid FAILED, I2C ERROR, pkg: %d, pid reg:0x%02x", + i, addr); + goto exit; + } else if (strncmp(temp_pid, + cfg_bin->cfg_pkgs[i].cnst_info.hw_pid, + read_len)) { + ts_err("pkg:%d, pid contrast FAILED, reg:0x%02x", i, + addr); + ts_err("pid from i2c:%s, pid of cfg bin:%s", temp_pid, + cfg_bin->cfg_pkgs[i].cnst_info.hw_pid); + continue; + } + + /*contrast success, cfg_type*/ + if (cfg_bin->cfg_pkgs[i].cnst_info.cfg_type == TS_NORMAL_CFG) { + ts_info("find normal cfg_pkg SUCCESS"); + r = 0; + normal_pkg = &cfg_bin->cfg_pkgs[i]; + } + if (cfg_bin->cfg_pkgs[i].cnst_info.cfg_type == + TS_HIGH_SENSE_CFG) { + ts_info("find high sense cfg_pkg SUCCESS"); + high_sense_pkg = &cfg_bin->cfg_pkgs[i]; + } + } + + /*get register address from normal_pkg*/ + if (!normal_pkg) { + ts_err("ERROR, none suitable normal_pkg exist in cfg_bin"); + /*ts_dev->ic_type = IC_TYPE_NONE;*/ + r = -EINVAL; + goto exit; + } else { + /*get ic type*/ + if (!strncmp(normal_pkg->cnst_info.ic_type, "nanjing", + sizeof(normal_pkg->cnst_info.ic_type))) + ts_dev->ic_type = IC_TYPE_NANJING; + else if (!strncmp(normal_pkg->cnst_info.ic_type, "normandy", + sizeof(normal_pkg->cnst_info.ic_type))) + ts_dev->ic_type = IC_TYPE_NORMANDY; + else + ts_err("get ic type FAILED, unknow ic type from cfg_bin:%s", + normal_pkg->cnst_info.ic_type); + + /*get register info*/ + ts_dev->reg.cfg_send_flag = + normal_pkg->reg_info.cfg_send_flag.addr; + ts_dev->reg.version_base = + normal_pkg->reg_info.version_base.addr; + ts_dev->reg.version_len = + normal_pkg->reg_info.version_base.reserved1; + ts_dev->reg.pid = normal_pkg->reg_info.pid.addr; + ts_dev->reg.pid_len = normal_pkg->reg_info.pid.reserved1; + ts_dev->reg.vid = normal_pkg->reg_info.vid.addr; + ts_dev->reg.vid_len = normal_pkg->reg_info.vid.reserved1; + ts_dev->reg.sensor_id = normal_pkg->reg_info.sensor_id.addr; + ts_dev->reg.sensor_id_mask = + normal_pkg->reg_info.sensor_id.reserved1; + ts_dev->reg.fw_mask = normal_pkg->reg_info.fw_mask.addr; + ts_dev->reg.fw_status = normal_pkg->reg_info.fw_status.addr; + ts_dev->reg.cfg_addr = normal_pkg->reg_info.cfg_addr.addr; + ts_dev->reg.esd = normal_pkg->reg_info.esd.addr; + ts_dev->reg.command = normal_pkg->reg_info.command.addr; + ts_dev->reg.coor = normal_pkg->reg_info.coor.addr; + ts_dev->reg.gesture = normal_pkg->reg_info.gesture.addr; + ts_dev->reg.fw_request = normal_pkg->reg_info.fw_request.addr; + ts_dev->reg.proximity = normal_pkg->reg_info.proximity.addr; + } + + /*get configuration from pkgs*/ + if (normal_pkg) { + ts_info("normal cfg is found!"); + if (!ts_dev->normal_cfg) { + ts_dev->normal_cfg = devm_kzalloc( + ts_dev->dev, sizeof(*ts_dev->normal_cfg), + GFP_KERNEL); + if (!ts_dev->normal_cfg) { + ts_err("Failed to alloc memory for normal cfg"); + return -ENOMEM; + } + mutex_init(&ts_dev->normal_cfg->lock); + } + + ts_dev->normal_cfg->length = normal_pkg->pkg_len - + TS_PKG_CONST_INFO_LEN - + TS_PKG_REG_INFO_LEN; + memcpy(ts_dev->normal_cfg->data, normal_pkg->cfg, + ts_dev->normal_cfg->length); + } + + if (high_sense_pkg) { + ts_info("high sense cfg is found!"); + if (!ts_dev->highsense_cfg) { + ts_dev->highsense_cfg = devm_kzalloc( + ts_dev->dev, sizeof(*ts_dev->highsense_cfg), + GFP_KERNEL); + if (!ts_dev->highsense_cfg) { + ts_err("Failed to alloc memory for high sense cfg"); + return -ENOMEM; + } + mutex_init(&ts_dev->highsense_cfg->lock); + } + + ts_dev->highsense_cfg->length = high_sense_pkg->pkg_len - + TS_PKG_CONST_INFO_LEN - + TS_PKG_REG_INFO_LEN; + memcpy(ts_dev->highsense_cfg->data, high_sense_pkg->cfg, + ts_dev->highsense_cfg->length); + } + +exit: + return r; +} + +int goodix_read_cfg_bin(struct device *dev, struct goodix_cfg_bin *cfg_bin) +{ + int r; + const struct firmware *firmware; + char cfg_bin_name[32] = { 0x00 }; + int i = 0; + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + struct goodix_ts_board_data *ts_bdata = ts_dev->board_data; + + if (ts_dev == NULL) { + ts_err("can't get ts_dev"); + return -EINVAL; + } + ts_bdata = ts_dev->board_data; + if (ts_bdata == NULL) { + ts_err("can't get ts_bdata"); + return -EINVAL; + } + /*get cfg_bin_name*/ + if (ts_bdata->cfg_bin_name) + strlcpy(cfg_bin_name, ts_bdata->cfg_bin_name, + sizeof(cfg_bin_name)); + else + strlcpy(cfg_bin_name, TS_DEFAULT_CFG_BIN, sizeof(cfg_bin_name)); + ts_info("ts_bdata->cfg_bin_name:%s", ts_bdata->cfg_bin_name); + ts_info("cfg_bin_name:%s", cfg_bin_name); + for (i = 0; i < TS_RQST_FW_RETRY_TIMES; i++) { + r = request_firmware(&firmware, cfg_bin_name, dev); + if (r < 0) { + ts_err("Cfg_bin image [%s] not available,error:%d, try_times:%d", + cfg_bin_name, r, i + 1); + msleep(1000); + } else { + ts_info("Cfg_bin image [%s] is ready, try_times:%d", + cfg_bin_name, i + 1); + break; + } + } + if (i >= TS_RQST_FW_RETRY_TIMES) { + ts_err("get cfg_bin FAILED"); + goto exit; + } + + if (firmware->size <= 0) { + ts_err("request_firmware, cfg_bin length ERROR,len:%zu", + firmware->size); + r = -EINVAL; + goto exit; + } + + cfg_bin->bin_data_len = firmware->size; + /*allocate memory for cfg_bin->bin_data*/ + cfg_bin->bin_data = kzalloc(cfg_bin->bin_data_len, GFP_KERNEL); + if (!cfg_bin->bin_data) { + ts_err("Allocate memory for cfg_bin->bin_data FAILED"); + r = -ENOMEM; + } + memcpy(cfg_bin->bin_data, firmware->data, cfg_bin->bin_data_len); + r = 0; +exit: + if (firmware) { + release_firmware(firmware); + firmware = NULL; + } + return r; +} + +int goodix_read_cfg_bin_from_dts(struct device_node *node, + struct goodix_cfg_bin *cfg_bin) +{ + unsigned int len = 0; + struct property *prop = NULL; + + prop = of_find_property(node, "goodix_cfg_bin", &len); + if (!prop || !prop->value || len == 0) { + ts_err("Invalid cfg type, size:%u", len); + return -EINVAL; + } + + cfg_bin->bin_data_len = len; + /*allocate memory for cfg_bin->bin_data*/ + cfg_bin->bin_data = kzalloc(cfg_bin->bin_data_len, GFP_KERNEL); + if (!cfg_bin->bin_data) { + ts_err("Allocate memory for cfg_bin->bin_data FAILED"); + return -ENOMEM; + } + memcpy(cfg_bin->bin_data, prop->value, cfg_bin->bin_data_len); + return 0; +} + +void goodix_cfg_pkg_leToCpu(struct goodix_cfg_package *pkg) +{ + if (!pkg) { + ts_err("cfg package is NULL"); + return; + } + /*package const_info*/ + pkg->cnst_info.pkg_len = le32_to_cpu(pkg->cnst_info.pkg_len); + pkg->cnst_info.x_res_offset = le16_to_cpu(pkg->cnst_info.x_res_offset); + pkg->cnst_info.y_res_offset = le16_to_cpu(pkg->cnst_info.y_res_offset); + pkg->cnst_info.trigger_offset = + le16_to_cpu(pkg->cnst_info.trigger_offset); + + /*package reg_info*/ + pkg->reg_info.cfg_send_flag.addr = + le16_to_cpu(pkg->reg_info.cfg_send_flag.addr); + pkg->reg_info.pid.addr = le16_to_cpu(pkg->reg_info.pid.addr); + pkg->reg_info.vid.addr = le16_to_cpu(pkg->reg_info.vid.addr); + pkg->reg_info.sensor_id.addr = + le16_to_cpu(pkg->reg_info.sensor_id.addr); + pkg->reg_info.fw_status.addr = + le16_to_cpu(pkg->reg_info.fw_status.addr); + pkg->reg_info.cfg_addr.addr = le16_to_cpu(pkg->reg_info.cfg_addr.addr); + pkg->reg_info.esd.addr = le16_to_cpu(pkg->reg_info.esd.addr); + pkg->reg_info.command.addr = le16_to_cpu(pkg->reg_info.command.addr); + pkg->reg_info.coor.addr = le16_to_cpu(pkg->reg_info.coor.addr); + pkg->reg_info.gesture.addr = le16_to_cpu(pkg->reg_info.gesture.addr); + pkg->reg_info.fw_request.addr = + le16_to_cpu(pkg->reg_info.fw_request.addr); + pkg->reg_info.proximity.addr = + le16_to_cpu(pkg->reg_info.proximity.addr); +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.h new file mode 100644 index 000000000000..5828c59d65be --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.h @@ -0,0 +1,108 @@ +#ifndef _GOODIX_CFG_BIN_H_ +#define _GOODIX_CFG_BIN_H_ + +#include "goodix_ts_core.h" + +#define TS_DEFAULT_CFG_BIN "goodix_gt9886_cfg_f11.bin" +#define TS_BIN_VERSION_START_INDEX 5 +#define TS_BIN_VERSION_LEN 4 +#define TS_CFG_BIN_HEAD_RESERVED_LEN 6 +#define TS_CFG_OFFSET_LEN 2 +#define TS_IC_TYPE_NAME_MAX_LEN 15 +#define TS_CFG_BIN_HEAD_LEN \ + (sizeof(struct goodix_cfg_bin_head) + TS_CFG_BIN_HEAD_RESERVED_LEN) +#define TS_PKG_CONST_INFO_LEN (sizeof(struct goodix_cfg_pkg_const_info)) +#define TS_PKG_REG_INFO_LEN (sizeof(struct goodix_cfg_pkg_reg_info)) +#define TS_PKG_HEAD_LEN (TS_PKG_CONST_INFO_LEN + TS_PKG_REG_INFO_LEN) + +/*cfg block definitin*/ +#define TS_CFG_BLOCK_PID_LEN 8 +#define TS_CFG_BLOCK_VID_LEN 8 +#define TS_CFG_BLOCK_FW_MASK_LEN 9 +#define TS_CFG_BLOCK_FW_PATCH_LEN 4 +#define TS_CFG_BLOCK_RESERVED_LEN 9 + +#define TS_NORMAL_CFG 0x01 +#define TS_HIGH_SENSE_CFG 0x03 +#define TS_RQST_FW_RETRY_TIMES 2 +#define TS_LOCKDOWN_REG 0xBDB4 + +#pragma pack(1) +struct goodix_cfg_pkg_reg { + u16 addr; + u8 reserved1; + u8 reserved2; +}; + +struct goodix_cfg_pkg_const_info { + u32 pkg_len; + u8 ic_type[TS_IC_TYPE_NAME_MAX_LEN]; + u8 cfg_type; + u8 sensor_id; + u8 hw_pid[TS_CFG_BLOCK_PID_LEN]; + u8 hw_vid[TS_CFG_BLOCK_VID_LEN]; + u8 fw_mask[TS_CFG_BLOCK_FW_MASK_LEN]; + u8 fw_patch[TS_CFG_BLOCK_FW_PATCH_LEN]; + u16 x_res_offset; + u16 y_res_offset; + u16 trigger_offset; +}; + +struct goodix_cfg_pkg_reg_info { + struct goodix_cfg_pkg_reg cfg_send_flag; + struct goodix_cfg_pkg_reg version_base; + struct goodix_cfg_pkg_reg pid; + struct goodix_cfg_pkg_reg vid; + struct goodix_cfg_pkg_reg sensor_id; + struct goodix_cfg_pkg_reg fw_mask; + struct goodix_cfg_pkg_reg fw_status; + struct goodix_cfg_pkg_reg cfg_addr; + struct goodix_cfg_pkg_reg esd; + struct goodix_cfg_pkg_reg command; + struct goodix_cfg_pkg_reg coor; + struct goodix_cfg_pkg_reg gesture; + struct goodix_cfg_pkg_reg fw_request; + struct goodix_cfg_pkg_reg proximity; + u8 reserved[TS_CFG_BLOCK_RESERVED_LEN]; +}; + +struct goodix_cfg_bin_head { + u32 bin_len; + u8 checksum; + u8 bin_version[TS_BIN_VERSION_LEN]; + u8 pkg_num; +}; + +#pragma pack() + +struct goodix_cfg_package { + struct goodix_cfg_pkg_const_info cnst_info; + struct goodix_cfg_pkg_reg_info reg_info; + const u8 *cfg; + u32 pkg_len; +}; + +struct goodix_cfg_bin { + unsigned char *bin_data; + unsigned int bin_data_len; + struct goodix_cfg_bin_head head; + struct goodix_cfg_package *cfg_pkgs; +}; + +int goodix_cfg_bin_proc(void *data); + +int goodix_parse_cfg_bin(struct goodix_cfg_bin *cfg_bin); + +int goodix_get_reg_and_cfg(struct goodix_ts_device *ts_dev, + struct goodix_cfg_bin *cfg_bin); + +int goodix_read_cfg_bin(struct device *dev, struct goodix_cfg_bin *cfg_bin); + +int goodix_read_cfg_bin_from_dts(struct device_node *node, + struct goodix_cfg_bin *cfg_bin); + +void goodix_cfg_pkg_leToCpu(struct goodix_cfg_package *pkg); + +int goodix_start_cfg_bin(struct goodix_ts_core *ts_core); + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_default_fw.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_default_fw.h new file mode 100644 index 000000000000..00fd39d4b840 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_default_fw.h @@ -0,0 +1,6 @@ +#ifndef _GOODIX_FIRMWARE_FW_H_ +#define _GOODIX_FIRMWARE_FW_H_ + +u8 goodix_default_fw[] = { 0x00 }; + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_gtx8_update.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_gtx8_update.c new file mode 100644 index 000000000000..8e97ed43e820 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_gtx8_update.c @@ -0,0 +1,1397 @@ +/* + * Goodix GTX5 Firmware Update Driver. + * + * Copyright (C) 2015 - 2016 Goodix, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: Yulong Cai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be a reference + * to you, when you are integrating the GOODiX's CTP IC into your system, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ +#include "goodix_ts_core.h" +#include "goodix_cfg_bin.h" +#include "goodix_default_fw.h" +/* COMMON PART - START */ +#define TS_DEFAULT_FIRMWARE "goodix_gt9886_fw_f11.bin" + +#define FW_HEADER_SIZE 256 +#define FW_SUBSYS_INFO_SIZE 8 +#define FW_SUBSYS_INFO_OFFSET 32 +#define FW_SUBSYS_MAX_NUM 28 +#define FW_UPDATE_RETRY 2 + +#define ISP_MAX_BUFFERSIZE (1024 * 4) + +#define HW_REG_CPU_CTRL 0x2180 +#define HW_REG_DSP_MCU_POWER 0x2010 +#define HW_REG_RESET 0x2184 +#define HW_REG_SCRAMBLE 0x2218 +#define HW_REG_BANK_SELECT 0x2048 +#define HW_REG_ACCESS_PATCH0 0x204D +#define HW_REG_EC_SRM_START 0x204F +#define HW_REG_CPU_RUN_FROM 0x4506 /* for nor_L is 0x4006 */ +#define HW_REG_ISP_RUN_FLAG 0x6006 +#define HW_REG_ISP_ADDR 0xC000 +#define HW_REG_ISP_BUFFER 0x6100 +#define HW_REG_SUBSYS_TYPE 0x6020 +#define HW_REG_FLASH_FLAG 0x6022 +#define HW_REG_CACHE 0x204B +#define HW_REG_ESD_KEY 0x2318 +#define HW_REG_WTD_TIMER 0x20B0 + +#define CPU_CTRL_PENDING 0x00 +#define CPU_CTRL_RUNNING 0x01 + +#define ISP_STAT_IDLE 0xFF +#define ISP_STAT_READY 0xAA +#define ISP_STAT_WRITING 0xAA +#define ISP_FLASH_SUCCESS 0xBB +#define ISP_FLASH_ERROR 0xCC +#define ISP_FLASH_CHECK_ERROR 0xDD +#define ISP_CMD_PREPARE 0x55 +#define ISP_CMD_FLASH 0xAA + +#define TS_CHECK_ISP_STATE_RETRY_TIMES 200 +#define TS_READ_FLASH_STATE_RETRY_TIMES 200 + +/*0: Header update + *1: request firmware update*/ +atomic_t fw_update_mode = ATOMIC_INIT(1); + +/** + * fw_subsys_info - subsytem firmware infomation + * @type: sybsystem type + * @size: firmware size + * @flash_addr: flash address + * @data: firmware data + */ +struct fw_subsys_info { + u8 type; + u32 size; + u16 flash_addr; + const u8 *data; +}; + +#pragma pack(1) +/** + * firmware_info + * @size: fw total length + * @checksum: checksum of fw + * @hw_pid: mask pid string + * @hw_pid: mask vid code + * @fw_pid: fw pid string + * @fw_vid: fw vid code + * @subsys_num: number of fw subsystem + * @chip_type: chip type + * @protocol_ver: firmware packing + * protocol version + * @subsys: sybsystem info + */ +struct firmware_info { + u32 size; + u16 checksum; + u8 hw_pid[6]; + u8 hw_vid[3]; + u8 fw_pid[8]; + u8 fw_vid[4]; + u8 subsys_num; + u8 chip_type; + u8 protocol_ver; + u8 reserved[2]; + struct fw_subsys_info subsys[FW_SUBSYS_MAX_NUM]; +}; + +#pragma pack() + +/** + * firmware_data - firmware data structure + * @fw_info: firmware infomation + * @firmware: firmware data structure + */ +struct firmware_data { + struct firmware_info fw_info; + const struct firmware *firmware; +}; + +enum update_status { + UPSTA_NOTWORK = 0, + UPSTA_PREPARING, + UPSTA_UPDATING, + UPSTA_ABORT, + UPSTA_SUCCESS, + UPSTA_FAILED +}; + +/** + * fw_update_ctrl - sturcture used to control the + * firmware update process + * @status: update status + * @progress: indicate the progress of update + * @allow_reset: control the reset callback + * @allow_irq: control the irq callback + * @allow_suspend: control the suspend callback + * @allow_resume: allow resume callback + * @fw_data: firmware data + * @ts_dev: touch device + * @fw_name: firmware name + * @attr_fwimage: sysfs bin attrs, for storing fw image + * @fw_from_sysfs: whether the firmware image is loadind + * from sysfs + */ +struct fw_update_ctrl { + enum update_status status; + unsigned int progress; + bool force_update; + bool allow_reset; + bool allow_irq; + bool allow_suspend; + bool allow_resume; + struct firmware_data fw_data; + struct goodix_ts_device *ts_dev; + struct goodix_ts_core *core_data; + char fw_name[32]; + struct bin_attribute attr_fwimage; + bool fw_from_sysfs; +}; + +/** + * goodix_parse_firmware - parse firmware header infomation + * and subsystem infomation from firmware data buffer + * + * @fw_data: firmware struct, contains firmware header info + * and firmware data. + * return: 0 - OK, < 0 - error + */ +static int goodix_parse_firmware(struct firmware_data *fw_data) +{ + const struct firmware *firmware; + struct firmware_info *fw_info; + unsigned int i, fw_offset, info_offset; + u16 checksum; + int r = 0; + + if (!fw_data || !fw_data->firmware) { + ts_err("Invalid goodix firmware data"); + return -EINVAL; + } + fw_info = &fw_data->fw_info; + + /* copy firmware head info */ + firmware = fw_data->firmware; + if (firmware->size < FW_SUBSYS_INFO_OFFSET) { + ts_err("Invalid goodix firmware size:%zu", firmware->size); + r = -EINVAL; + goto err_size; + } + memcpy(fw_info, firmware->data, FW_SUBSYS_INFO_OFFSET); + + /* check firmware size */ + fw_info->size = be32_to_cpu(fw_info->size); + if (firmware->size != fw_info->size + 6) { + ts_err("Bad goodix firmware, size not match"); + r = -EINVAL; + goto err_size; + } + + /* calculate checksum, note: sum of bytes, but check + * by u16 checksum */ + for (i = 6, checksum = 0; i < firmware->size; i++) + checksum += firmware->data[i]; + + /* byte order change, and check */ + fw_info->checksum = be16_to_cpu(fw_info->checksum); + if (checksum != fw_info->checksum) { + ts_err("Bad goodix firmware, cheksum error"); + r = -EINVAL; + goto err_size; + } + + if (fw_info->subsys_num > FW_SUBSYS_MAX_NUM) { + ts_err("Bad goodix firmware, invalid subsys num: %d", + fw_info->subsys_num); + r = -EINVAL; + goto err_size; + } + + /* parse subsystem info */ + fw_offset = FW_HEADER_SIZE; + for (i = 0; i < fw_info->subsys_num; i++) { + info_offset = FW_SUBSYS_INFO_OFFSET + i * FW_SUBSYS_INFO_SIZE; + fw_info->subsys[i].type = firmware->data[info_offset]; + fw_info->subsys[i].size = be32_to_cpup( + (__be32 *)&firmware->data[info_offset + 1]); + fw_info->subsys[i].flash_addr = be16_to_cpup( + (__be16 *)&firmware->data[info_offset + 5]); + if (fw_offset > firmware->size) { + ts_err("Sybsys offset exceed Firmware size"); + goto err_size; + } + fw_info->subsys[i].data = firmware->data + fw_offset; + fw_offset += fw_info->subsys[i].size; + } + + ts_info("Firmware package protocol: V%u", fw_info->protocol_ver); + ts_info("Fimware PID:GT%s", fw_info->fw_pid); + ts_info("Fimware VID:0x%02X %02X %02X %02x", fw_info->fw_vid[0], + fw_info->fw_vid[1], fw_info->fw_vid[2], fw_info->fw_vid[3]); + ts_info("Firmware chip type:0x%02X", fw_info->chip_type); + ts_info("Firmware size:%u", fw_info->size); + ts_info("Firmware subsystem num:%u", fw_info->subsys_num); +#ifdef CONFIG_GOODIX_DEBUG + for (i = 0; i < fw_info->subsys_num; i++) { + ts_debug("------------------------------------------"); + ts_debug("Index:%d", i); + ts_debug("Subsystem type:0x%02X", fw_info->subsys[i].type); + ts_debug("Subsystem size:%u", fw_info->subsys[i].size); + ts_debug("Subsystem flash_addr:0x%08X", + fw_info->subsys[i].flash_addr); + ts_debug("Subsystem Ptr:%p", fw_info->subsys[i].data); + } + ts_debug("------------------------------------------"); +#endif + +err_size: + return r; +} + +/** + * goodix_check_update - compare the version of firmware running in + * touch device with the version getting from the firmware file. + * @fw_info: firmware infomation to be compared + * return: 0 firmware in the touch device needs to be updated + * < 0 no need to update firmware + */ +static int goodix_check_update(struct goodix_ts_device *dev, + const struct firmware_info *fw_info) +{ + struct goodix_ts_version fw_ver; + /*u8 fwimg_cid;*/ + int r = 0; + int res = 0; + + /* read version from chip, if we got invalid + * firmware version, maybe fimware in flash is + * incorrect, so we need to update firmware */ + r = dev->hw_ops->read_version(dev, &fw_ver); + if (r == -EBUS) + return r; + + if (fw_ver.valid) { + ts_info("pid_len=%d\n", dev->reg.pid_len); + ts_info("tp.pid=%s fw.pid=%s\n", fw_ver.pid, fw_info->fw_pid); + if (memcmp(fw_ver.pid, fw_info->fw_pid, dev->reg.pid_len)) { + ts_err("tp.pid=0x%x fw.pid=0x%x\n", fw_ver.pid, + fw_info->fw_pid); + ts_err("Product ID is not match"); + return -EPERM; + } + + ts_info("vid_len=%d\n", dev->reg.vid_len); + ts_info("Touchpanel VID:0x%02x 0x%02x 0x%02x 0x%02x", + fw_ver.vid[0], fw_ver.vid[1], fw_ver.vid[2], + fw_ver.vid[3]); + ts_info("Fimware VID:0x%02X 0x%02x 0x%02x 0x%02x", + fw_info->fw_vid[0], fw_info->fw_vid[1], + fw_info->fw_vid[2], fw_info->fw_vid[3]); + res = memcmp(fw_ver.vid, fw_info->fw_vid, dev->reg.vid_len); + if (res == 0) { + ts_err("FW version is equal to the IC's"); + return -EPERM; + } else { + ts_info("tp version not equal firmware version\n"); + } + } /* else invalid firmware, update firmware */ + + ts_info("Firmware needs to be updated"); + return 0; +} + +/** + * goodix_reg_write_confirm - write register and confirm the value + * in the register. + * @dev: pointer to touch device + * @addr: register address + * @data: pointer to data buffer + * @len: data length + * return: 0 write success and confirm ok + * < 0 failed + */ +static int goodix_reg_write_confirm(struct goodix_ts_device *dev, + unsigned int addr, unsigned char *data, + unsigned int len) +{ + u8 *cfm, cfm_buf[32]; + int r, i; + + if (len > sizeof(cfm_buf)) { + cfm = kzalloc(len, GFP_KERNEL); + if (!cfm) { + ts_err("Mem alloc failed"); + return -ENOMEM; + } + } else { + cfm = &cfm_buf[0]; + } + + for (i = 0; i < GOODIX_BUS_RETRY_TIMES; i++) { + r = dev->hw_ops->write_trans(dev, addr, data, len); + if (r < 0) + goto exit; + + r = dev->hw_ops->read_trans(dev, addr, cfm, len); + if (r < 0) + goto exit; + + if (memcmp(data, cfm, len)) { + r = -EMEMCMP; + continue; + } else { + r = 0; + break; + } + } + +exit: + if (cfm != &cfm_buf[0]) + kfree(cfm); + return r; +} + +static inline int goodix_reg_write(struct goodix_ts_device *dev, + unsigned int addr, unsigned char *data, + unsigned int len) +{ + return dev->hw_ops->write_trans(dev, addr, data, len); +} + +static inline int goodix_reg_read(struct goodix_ts_device *dev, + unsigned int addr, unsigned char *data, + unsigned int len) +{ + return dev->hw_ops->read_trans(dev, addr, data, len); +} +/** + * goodix_load_isp - load ISP program to deivce ram + * @dev: pointer to touch device + * @fw_data: firmware data + * return 0 ok, <0 error + */ +static int goodix_load_isp(struct goodix_ts_device *ts_dev, + struct firmware_data *fw_data) +{ + struct fw_subsys_info *fw_isp; + u8 reg_val[8] = { 0x00 }; + int r; + int i; + + fw_isp = &fw_data->fw_info.subsys[0]; + ts_info("Loading ISP start"); + /* select bank0 */ + reg_val[0] = 0x00; + r = goodix_reg_write(ts_dev, HW_REG_BANK_SELECT, reg_val, 1); + if (r < 0) { + ts_err("Failed to select bank0"); + return r; + } + ts_debug("Success select bank0, Set 0x%x -->0x00", HW_REG_BANK_SELECT); + + /* enable bank0 access */ + reg_val[0] = 0x01; + r = goodix_reg_write(ts_dev, HW_REG_ACCESS_PATCH0, reg_val, 1); + if (r < 0) { + ts_err("Failed to enable patch0 access"); + return r; + } + ts_debug("Success select bank0, Set 0x%x -->0x01", + HW_REG_ACCESS_PATCH0); + r = goodix_reg_write_confirm(ts_dev, HW_REG_ISP_ADDR, + (u8 *)fw_isp->data, fw_isp->size); + if (r < 0) { + ts_err("Loading ISP error"); + return r; + } + ts_debug("Success send ISP data to IC"); + + /* forbid patch access */ + reg_val[0] = 0x00; + r = goodix_reg_write_confirm(ts_dev, HW_REG_ACCESS_PATCH0, reg_val, 1); + if (r < 0) { + ts_err("Failed to disable patch0 access"); + return r; + } + ts_debug("Success forbit bank0 accedd, set 0x%x -->0x00", + HW_REG_ACCESS_PATCH0); + + /*clear 0x6006*/ + reg_val[0] = 0x00; + reg_val[1] = 0x00; + r = goodix_reg_write(ts_dev, HW_REG_ISP_RUN_FLAG, reg_val, 2); + if (r < 0) { + ts_err("Failed to clear 0x%x", HW_REG_ISP_RUN_FLAG); + return r; + } + ts_debug("Success clear 0x%x", HW_REG_ISP_RUN_FLAG); + + /* TODO: change address 0xBDE6 set backdoor flag HW_REG_CPU_RUN_FROM */ + memset(reg_val, 0x55, 8); + r = goodix_reg_write(ts_dev, HW_REG_CPU_RUN_FROM, reg_val, 8); + if (r < 0) { + ts_err("Failed set backdoor flag"); + return r; + } + ts_debug("Success write [8]0x55 to 0x%x", HW_REG_CPU_RUN_FROM); + /* TODO: change reg_val 0x08---> 0x00 release ss51 */ + reg_val[0] = 0x00; + r = goodix_reg_write(ts_dev, HW_REG_CPU_CTRL, reg_val, 1); + if (r < 0) { + ts_err("Failed to run isp"); + return r; + } + ts_debug("Success run isp, set 0x%x-->0x00", HW_REG_CPU_CTRL); + + /* check isp work state */ + for (i = 0; i < TS_CHECK_ISP_STATE_RETRY_TIMES; i++) { + r = goodix_reg_read(ts_dev, HW_REG_ISP_RUN_FLAG, reg_val, 2); + if (r < 0 || (reg_val[0] == 0xAA && reg_val[1] == 0xBB)) + break; + usleep_range(5000, 5100); + } + if (reg_val[0] == 0xAA && reg_val[1] == 0xBB) { + ts_info("ISP working OK"); + return 0; + } else { + ts_err("ISP not work,0x%x=0x%x, 0x%x=0x%x", HW_REG_ISP_RUN_FLAG, + reg_val[0], HW_REG_ISP_RUN_FLAG + 1, reg_val[1]); + return -EFAULT; + } +} + +/** + * goodix_update_prepare - update prepare, loading ISP program + * and make sure the ISP is running. + * @fwu_ctrl: pointer to fimrware control structure + * return: 0 ok, <0 error + */ +static int goodix_update_prepare(struct fw_update_ctrl *fwu_ctrl) +{ + struct goodix_ts_device *ts_dev = fwu_ctrl->ts_dev; + u8 reg_val[4] = { 0x00 }; + u8 temp_buf[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + int retry = 20; + int r; + + ts_dev->hw_ops->write(ts_dev, HW_REG_CPU_RUN_FROM, temp_buf, 8); + + /*reset IC*/ + fwu_ctrl->allow_reset = true; + ts_info("normandy firmware update, reset"); + gpio_direction_output(ts_dev->board_data->reset_gpio, 0); + udelay(2000); + gpio_direction_output(ts_dev->board_data->reset_gpio, 1); + usleep_range(10000, 11000); + fwu_ctrl->allow_reset = false; + + retry = 20; + do { + /*r = goodix_reg_read(ts_dev, addr + index, temp_buf, rlen); + if (r < 0) { + ts_err("Failed read back addr 0x%x", addr + index); + goto err_out; + }*/ + reg_val[0] = 0x24; + r = goodix_reg_write_confirm(ts_dev, HW_REG_CPU_CTRL, reg_val, + 1); + if (r < 0) { + ts_info("Failed to hold ss51, retry"); + msleep(20); + } else { + break; + } + } while (--retry); + if (!retry) { + ts_err("Failed hold ss51,return =%d", r); + return -EINVAL; + } + ts_debug("Success hold ss51"); + + /* enable DSP & MCU power */ + reg_val[0] = 0x00; + r = goodix_reg_write_confirm(ts_dev, HW_REG_DSP_MCU_POWER, reg_val, 1); + if (r < 0) { + ts_err("Failed enable DSP&MCU power"); + return r; + } + ts_debug("Success enabled DSP&MCU power,set 0x%x-->0x00", + HW_REG_DSP_MCU_POWER); + + /* disable watchdog timer */ + reg_val[0] = 0x00; + r = goodix_reg_write(ts_dev, HW_REG_CACHE, reg_val, 1); + if (r < 0) { + ts_err("Failed to clear cache"); + return r; + } + ts_debug("Success clear cache"); + + reg_val[0] = 0x95; + r = goodix_reg_write(ts_dev, HW_REG_ESD_KEY, reg_val, 1); + reg_val[0] = 0x00; + r |= goodix_reg_write(ts_dev, HW_REG_WTD_TIMER, reg_val, 1); + + reg_val[0] = 0x27; + r |= goodix_reg_write(ts_dev, HW_REG_ESD_KEY, reg_val, 1); + if (r < 0) { + ts_err("Failed to disable watchdog"); + return r; + } + ts_debug("Success disable watchdog"); + + /* set scramble */ + reg_val[0] = 0x00; + r = goodix_reg_write(ts_dev, HW_REG_SCRAMBLE, reg_val, 1); + if (r < 0) { + ts_err("Failed to set scramble"); + return r; + } + ts_debug("Succcess set scramble"); + /* load ISP code and run form isp */ + r = goodix_load_isp(ts_dev, &fwu_ctrl->fw_data); + if (r < 0) + ts_err("Failed lode and run isp"); + return r; +} + +/** + * goodix_format_fw_packet - formate one flash packet + * @pkt: target firmware packet + * @flash_addr: flash address + * @size: packet size + * @data: packet data + */ +static int goodix_format_fw_packet(u8 *pkt, u32 flash_addr, u16 len, + const u8 *data) +{ + u16 checksum; + if (!pkt || !data) + return -EINVAL; + + /* + * checksum rule:sum of data in one format is equal to zero + * data format: byte/le16/be16/le32/be32/le64/be64 + */ + pkt[0] = (len >> 8) & 0xff; + pkt[1] = len & 0xff; + pkt[2] = (flash_addr >> 16) & + 0xff; /* u16 >> 16bit seems nosense but really important */ + pkt[3] = (flash_addr >> 8) & 0xff; + memcpy(&pkt[4], data, len); + checksum = checksum_be16(pkt, len + 4); + checksum = 0 - checksum; + pkt[len + 4] = (checksum >> 8) & 0xff; + pkt[len + 5] = checksum & 0xff; + return 0; +} +/** + * goodix_send_fw_packet - send one firmware packet to ISP + * @dev: target touch device + * @pkt: firmware packet + * return：0 ok, <0 error + */ +static int goodix_send_fw_packet(struct goodix_ts_device *dev, u8 type, u8 *pkt, + u32 len) +{ + u8 reg_val[4]; + int r, i; + + if (!pkt) + return -EINVAL; + + r = goodix_reg_write_confirm(dev, HW_REG_ISP_BUFFER, pkt, len); + if (r < 0) { + ts_err("Failed to write firmware packet"); + return r; + } + + reg_val[0] = 0; + reg_val[1] = 0; + /* clear flash flag 0X6022 */ + r = goodix_reg_write_confirm(dev, HW_REG_FLASH_FLAG, reg_val, 2); + if (r < 0) { + ts_err("Faile to clear flash flag"); + return r; + } + + /* write subsystem type 0X8020*/ + reg_val[0] = type; + reg_val[1] = type; + r = goodix_reg_write_confirm(dev, HW_REG_SUBSYS_TYPE, reg_val, 2); + if (r < 0) { + ts_err("Failed write subsystem type to IC"); + return r; + } + + for (i = 0; i < TS_READ_FLASH_STATE_RETRY_TIMES; i++) { + r = goodix_reg_read(dev, HW_REG_FLASH_FLAG, reg_val, 2); + if (r < 0) { + ts_err("Failed read flash state"); + return r; + } + + /* flash haven't end */ + if (reg_val[0] == ISP_STAT_WRITING && + reg_val[1] == ISP_STAT_WRITING) { + ts_debug("Flash not ending..."); + usleep_range(55000, 56000); + continue; + } + if (reg_val[0] == ISP_FLASH_SUCCESS && + reg_val[1] == ISP_FLASH_SUCCESS) { + /* read twice to confirm the result */ + r = goodix_reg_read(dev, HW_REG_FLASH_FLAG, reg_val, 2); + if (!r && reg_val[0] == ISP_FLASH_SUCCESS && + reg_val[1] == ISP_FLASH_SUCCESS) { + /*r = goodix_read_back_check(dev, 0x8104, len - 6, (char*)pkt + 4); + if (r) { + ts_err("Read back compare failed"); + } else { + ts_info("Read back compare OK"); + }*/ + ts_info("Flash subsystem ok"); + return 0; + } + } + if (reg_val[0] == ISP_FLASH_ERROR && + reg_val[1] == ISP_FLASH_ERROR) { + ts_err(" Flash subsystem failed"); + return -EAGAIN; + } + if (reg_val[0] == ISP_FLASH_CHECK_ERROR) { + ts_err("Subsystem checksum err"); + return -EAGAIN; + } + usleep_range(250, 260); + } + + ts_err("Wait for flash end timeout, 0x6022= %x %x", reg_val[0], + reg_val[1]); + return -EAGAIN; +} + +/** + * goodix_flash_subsystem - flash subsystem firmware, + * Main flow of flashing firmware. + * Each firmware subsystem is divided into several + * packets, the max size of packet is limited to + * @{ISP_MAX_BUFFERSIZE} + * @dev: pointer to touch device + * @subsys: subsystem infomation + * return: 0 ok, < 0 error + */ +static int goodix_flash_subsystem(struct goodix_ts_device *dev, + struct fw_subsys_info *subsys) +{ + u16 data_size, offset; + u32 total_size; + u32 subsys_base_addr = subsys->flash_addr << 8; + u8 *fw_packet; + int r = 0, i; + + /* + * if bus(i2c/spi) error occued, then exit, we will do + * hardware reset and re-prepare ISP and then retry + * flashing + */ + total_size = subsys->size; + fw_packet = kzalloc(ISP_MAX_BUFFERSIZE + 6, GFP_KERNEL); + if (!fw_packet) { + ts_err("Failed alloc memory"); + return -EINVAL; + } + + offset = 0; + while (total_size > 0) { + data_size = total_size > ISP_MAX_BUFFERSIZE ? + ISP_MAX_BUFFERSIZE : + total_size; + ts_info("Flash firmware to %08x,size:%u bytes", + subsys_base_addr + offset, data_size); + + /* format one firmware packet */ + r = goodix_format_fw_packet(fw_packet, + subsys_base_addr + offset, + data_size, &subsys->data[offset]); + if (r < 0) { + ts_err("Invalid packet params"); + goto exit; + } + + /* send one firmware packet, retry 3 time if send failed */ + for (i = 0; i < 3; i++) { + r = goodix_send_fw_packet(dev, subsys->type, fw_packet, + data_size + 6); + if (!r) + break; + } + if (r) { + ts_err("Failed flash subsystem"); + goto exit; + } + offset += data_size; + total_size -= data_size; + } /* end while */ + +exit: + kfree(fw_packet); + return r; +} + +/** + * goodix_flash_firmware - flash firmware + * @dev: pointer to touch device + * @fw_data: firmware data + * return: 0 ok, < 0 error + */ +static int goodix_flash_firmware(struct goodix_ts_device *dev, + struct firmware_data *fw_data) +{ + struct fw_update_ctrl *fw_ctrl; + struct firmware_info *fw_info; + struct fw_subsys_info *fw_x; + int retry = GOODIX_BUS_RETRY_TIMES; + int i, r = 0, fw_num, prog_step; + + /* start from subsystem 1, + * subsystem 0 is the ISP program */ + fw_ctrl = container_of(fw_data, struct fw_update_ctrl, fw_data); + fw_info = &fw_data->fw_info; + fw_num = fw_info->subsys_num; + + /* we have 80% work here */ + prog_step = 80 / (fw_num - 1); + + for (i = 1; i < fw_num && retry;) { + ts_info("--- Start to flash subsystem[%d] ---", i); + fw_x = &fw_info->subsys[i]; + r = goodix_flash_subsystem(dev, fw_x); + if (r == 0) { + ts_info("--- End flash subsystem[%d]: OK ---", i); + fw_ctrl->progress += prog_step; + i++; + } else if (r == -EAGAIN) { + retry--; + ts_err("--- End flash subsystem%d: Fail, errno:%d, retry:%d ---", + i, r, GOODIX_BUS_RETRY_TIMES - retry); + } else if (r < 0) { /* bus error */ + ts_err("--- End flash subsystem%d: Fatal error:%d exit ---", + i, r); + goto exit_flash; + } + } + +exit_flash: + return r; +} + +/** + * goodix_update_finish - update finished, free resource + * and reset flags--- + * @fwu_ctrl: pointer to fw_update_ctrl structrue + * return: 0 ok, < 0 error + */ +static int goodix_update_finish(struct goodix_ts_device *ts_dev, + struct fw_update_ctrl *fwu_ctrl) +{ + u8 reg_val[8] = { 0 }; + int r = 0; + + /* hold ss51 */ + reg_val[0] = 0x24; + r = goodix_reg_write(ts_dev, HW_REG_CPU_CTRL, reg_val, 1); + if (r < 0) + ts_err("Failed to hold ss51"); + + /* clear back door flag */ + memset(reg_val, 0, sizeof(reg_val)); + r = goodix_reg_write(ts_dev, HW_REG_CPU_RUN_FROM, reg_val, 8); + if (r) { + ts_err("Failed set CPU run from normal firmware"); + return r; + } + + /* release ss51 */ + reg_val[0] = 0x00; + r = goodix_reg_write(ts_dev, HW_REG_CPU_CTRL, reg_val, 1); + if (r < 0) + ts_err("Failed to run ss51"); + + /*reset*/ + r = ts_dev->hw_ops->reset(ts_dev); + + return r; +} + +/** + * goodix_fw_update_proc - firmware update process, the entry of + * firmware update flow + * @fwu_ctrl: firmware control + * return: 0 ok, < 0 error + */ +int goodix_fw_update_proc(struct fw_update_ctrl *fwu_ctrl) +{ + int retry0 = FW_UPDATE_RETRY; + int retry1 = FW_UPDATE_RETRY; + int r = 0; + + if (fwu_ctrl->status == UPSTA_PREPARING || + fwu_ctrl->status == UPSTA_UPDATING) { + ts_err("Firmware update already in progress"); + return 0; + } + + fwu_ctrl->progress = 0; + fwu_ctrl->status = UPSTA_PREPARING; + + r = goodix_parse_firmware(&fwu_ctrl->fw_data); + if (r < 0) { + fwu_ctrl->status = UPSTA_ABORT; + goto err_parse_fw; + } + + /* TODO: set force update flag*/ + /*fwu_ctrl->force_update = true;*/ + fwu_ctrl->progress = 10; + if (fwu_ctrl->force_update == false) { + r = goodix_check_update(fwu_ctrl->ts_dev, + &fwu_ctrl->fw_data.fw_info); + if (r < 0) { + fwu_ctrl->status = UPSTA_ABORT; + goto err_check_update; + } + } + +start_update: + fwu_ctrl->progress = 20; + fwu_ctrl->status = UPSTA_UPDATING; /* show upgrading status */ + r = goodix_update_prepare(fwu_ctrl); + if ((r == -EBUS || r == -EAGAIN) && --retry0 > 0) { + ts_err("Bus error, retry prepare ISP:%d", + FW_UPDATE_RETRY - retry0); + goto start_update; + } else if (r < 0) { + ts_err("Failed to prepare ISP, exit update:%d", r); + fwu_ctrl->status = UPSTA_FAILED; + goto err_fw_prepare; + } + + /* progress: 20%~100% */ + r = goodix_flash_firmware(fwu_ctrl->ts_dev, &fwu_ctrl->fw_data); + if ((r == -EBUS || r == -ETIMEOUT) && --retry1 > 0) { + /* we will retry[twice] if returns bus error[i2c/spi] + * we will do hardware reset and re-prepare ISP and then retry + * flashing + */ + ts_err("Bus error, retry firmware update:%d", + FW_UPDATE_RETRY - retry1); + goto start_update; + } else if (r < 0) { + ts_err("Fatal error, exit update:%d", r); + fwu_ctrl->status = UPSTA_FAILED; + goto err_fw_flash; + } + fwu_ctrl->status = UPSTA_SUCCESS; + +err_fw_flash: +err_fw_prepare: + goodix_update_finish(fwu_ctrl->ts_dev, fwu_ctrl); +err_check_update: +err_parse_fw: + if (fwu_ctrl->status == UPSTA_SUCCESS) + ts_info("Firmware update successfully"); + else if (fwu_ctrl->status == UPSTA_FAILED) + ts_err("Firmware update failed"); + fwu_ctrl->progress = 100; /* 100% */ + return r; +} +/* COMMON PART - END */ + +static struct goodix_ext_module goodix_fwu_module; + +/** + * goodix_request_firmware - request firmware data from user space + * + * @fw_data: firmware struct, contains firmware header info + * and firmware data pointer. + * return: 0 - OK, < 0 - error + */ +static int goodix_request_firmware(struct firmware_data *fw_data, + const char *name) +{ + struct fw_update_ctrl *fw_ctrl = + container_of(fw_data, struct fw_update_ctrl, fw_data); + struct device *dev = fw_ctrl->ts_dev->dev; + int r; + + ts_info("Request firmware image [%s]", name); + r = request_firmware(&fw_data->firmware, name, dev); + ts_info("Request firmware r = %d\n", r); + if (r < 0) + ts_err("Firmware image [%s] not available,errno:%d", name, r); + else + ts_info("Firmware image [%s] is ready", name); + return r; +} + +/** + * relase firmware resources + * + */ +static inline void goodix_release_firmware(struct firmware_data *fw_data) +{ + if (fw_data->firmware) { + release_firmware(fw_data->firmware); + fw_data->firmware = NULL; + } +} + +static int goodix_fw_update_thread(void *data) +{ + struct fw_update_ctrl *fwu_ctrl = data; + struct firmware *temp_firmware = NULL; + static DEFINE_MUTEX(fwu_lock); + int r; + + ts_err("%s:start\n", __func__); + if (!fwu_ctrl) { + ts_err("Invaid thread params"); + goodix_unregister_ext_module(&goodix_fwu_module); + return 0; + } + + mutex_lock(&fwu_lock); + if (!fwu_ctrl->fw_from_sysfs) { + if (atomic_read(&fw_update_mode) == 0) { + ts_info("goodix Firmware header update starts"); + temp_firmware = + kzalloc(sizeof(struct firmware), GFP_KERNEL); + if (!temp_firmware) { + ts_err("Failed to allocate memory for firmware"); + goto out; + } + temp_firmware->size = sizeof(goodix_default_fw); + temp_firmware->data = goodix_default_fw; + fwu_ctrl->fw_data.firmware = temp_firmware; + } else if (atomic_read(&fw_update_mode) == 1) { + ts_info("goodix Firmware request update starts"); + r = goodix_request_firmware(&fwu_ctrl->fw_data, + fwu_ctrl->fw_name); + if (r < 0) { + fwu_ctrl->status = UPSTA_ABORT; + fwu_ctrl->progress = 100; + goto out; + } + } + } else { + if (!fwu_ctrl->fw_data.firmware) { + ts_err("Invalid goodix firmware from sysfs"); + fwu_ctrl->status = UPSTA_ABORT; + fwu_ctrl->progress = 100; + goto out; + } + } + + /* DONT allow reset/irq/suspend/resume during update */ + fwu_ctrl->allow_irq = false; + fwu_ctrl->allow_suspend = false; + fwu_ctrl->allow_resume = false; + fwu_ctrl->allow_reset = false; + goodix_ts_blocking_notify(NOTIFY_FWUPDATE_START, NULL); + + /* ready to update */ + goodix_fw_update_proc(fwu_ctrl); + + goodix_ts_blocking_notify(NOTIFY_FWUPDATE_END, NULL); + fwu_ctrl->allow_reset = true; + fwu_ctrl->allow_irq = true; + fwu_ctrl->allow_suspend = true; + fwu_ctrl->allow_resume = true; + + /* clean */ + if (!fwu_ctrl->fw_from_sysfs) { + if (atomic_read(&fw_update_mode) == 0) { + kfree(fwu_ctrl->fw_data.firmware); + fwu_ctrl->fw_data.firmware = NULL; + temp_firmware = NULL; + } else if (atomic_read(&fw_update_mode) == 1) { + goodix_release_firmware(&fwu_ctrl->fw_data); + } + } else { + fwu_ctrl->fw_from_sysfs = false; + vfree(fwu_ctrl->fw_data.firmware); + fwu_ctrl->fw_data.firmware = NULL; + if (atomic_read(&fw_update_mode) == 0) + temp_firmware = NULL; + } + + /*parse cfg_group.bin*/ + if (!fwu_ctrl->core_data->cfg_group_parsed) + goodix_cfg_bin_proc(fwu_ctrl->core_data); + +out: + goodix_unregister_ext_module(&goodix_fwu_module); + mutex_unlock(&fwu_lock); + atomic_set(&fw_update_mode, 0); + return 0; +} +/* sysfs attributes */ +static ssize_t goodix_sysfs_update_en_store(struct goodix_ext_module *module, + const char *buf, size_t count) +{ + int val = 0, r; + r = sscanf(buf, "%d", &val); + if (r < 0) + return r; + if (r) { + atomic_set(&fw_update_mode, 1); + if (goodix_register_ext_module(&goodix_fwu_module)) + return -EIO; + } + return count; +} + +static ssize_t +goodix_sysfs_update_progress_show(struct goodix_ext_module *module, char *buf) +{ + struct fw_update_ctrl *fw_ctrl = module->priv_data; + return scnprintf(buf, PAGE_SIZE, "%d\n", fw_ctrl->progress); +} + +static ssize_t goodix_sysfs_update_result_show(struct goodix_ext_module *module, + char *buf) +{ + char *result = NULL; + struct fw_update_ctrl *fw_ctrl = module->priv_data; + + ts_info("result show"); + switch (fw_ctrl->status) { + case UPSTA_NOTWORK: + result = "notwork"; + break; + case UPSTA_PREPARING: + result = "preparing"; + break; + case UPSTA_UPDATING: + result = "upgrading"; + break; + case UPSTA_ABORT: + result = "abort"; + break; + case UPSTA_SUCCESS: + result = "success"; + break; + case UPSTA_FAILED: + result = "failed"; + break; + default: + break; + } + + return scnprintf(buf, PAGE_SIZE, "%s\n", result); +} + +static ssize_t +goodix_sysfs_update_fwversion_show(struct goodix_ext_module *module, char *buf) +{ + struct goodix_ts_version fw_ver; + struct fw_update_ctrl *fw_ctrl = module->priv_data; + int r = 0; + char str[5]; + + /* read version from chip */ + r = fw_ctrl->ts_dev->hw_ops->read_version(fw_ctrl->ts_dev, &fw_ver); + if (!r) { + memcpy(str, fw_ver.pid, 4); + str[4] = '\0'; + return scnprintf( + buf, PAGE_SIZE, + "PID:%s VID:%02x %02x %02x %02x SENSOR_ID:%d\n", str, + fw_ver.vid[0], fw_ver.vid[1], fw_ver.vid[2], + fw_ver.vid[3], fw_ver.sensor_id); + } + return 0; +} + +static ssize_t goodix_sysfs_fwsize_show(struct goodix_ext_module *module, + char *buf) +{ + struct fw_update_ctrl *fw_ctrl = module->priv_data; + int r = -EINVAL; + + if (fw_ctrl && fw_ctrl->fw_data.firmware) + r = snprintf(buf, PAGE_SIZE, "%zu\n", + fw_ctrl->fw_data.firmware->size); + return r; +} + +static ssize_t goodix_sysfs_fwsize_store(struct goodix_ext_module *module, + const char *buf, size_t count) +{ + struct fw_update_ctrl *fw_ctrl = module->priv_data; + struct firmware *fw; + u8 **data; + size_t size = 0; + + if (!fw_ctrl) + return -EINVAL; + + if (sscanf(buf, "%zu", &size) < 0 || !size) { + ts_err("Failed to get fwsize"); + return -EFAULT; + } + + fw = vmalloc(sizeof(*fw) + size); + if (fw == NULL) { + ts_err("Failed to alloc memory,size:%zu", size + sizeof(*fw)); + return -ENOMEM; + } + + memset(fw, 0x00, sizeof(*fw) + size); + data = (u8 **)&fw->data; + *data = (u8 *)fw + sizeof(struct firmware); + fw->size = size; + fw_ctrl->fw_data.firmware = fw; + fw_ctrl->fw_from_sysfs = true; + return count; +} + +static ssize_t goodix_sysfs_fwimage_store(struct file *file, + struct kobject *kobj, + struct bin_attribute *attr, char *buf, + loff_t pos, size_t count) +{ + struct fw_update_ctrl *fw_ctrl; + struct firmware_data *fw_data; + + fw_ctrl = container_of(attr, struct fw_update_ctrl, attr_fwimage); + fw_data = &fw_ctrl->fw_data; + + if (!fw_data->firmware) { + ts_err("Need set fw image size first"); + return -ENOMEM; + } + + if (fw_data->firmware->size == 0) { + ts_err("Invalid firmware size"); + return -EINVAL; + } + + if (pos + count > fw_data->firmware->size) + return -EFAULT; + memcpy((u8 *)&fw_data->firmware->data[pos], buf, count); + fw_ctrl->force_update = true; + return count; +} + +static ssize_t goodix_sysfs_force_update_store(struct goodix_ext_module *module, + const char *buf, size_t count) +{ + struct fw_update_ctrl *fw_ctrl = module->priv_data; + int val = 0, r; + + r = sscanf(buf, "%d", &val); + if (r < 0) + return r; + if (r) + fw_ctrl->force_update = true; + else + fw_ctrl->force_update = false; + return count; +} + +static struct goodix_ext_attribute goodix_fwu_attrs[] = { + __EXTMOD_ATTR(update_en, S_IWUGO, NULL, goodix_sysfs_update_en_store), + __EXTMOD_ATTR(progress, S_IRUGO, goodix_sysfs_update_progress_show, + NULL), + __EXTMOD_ATTR(result, S_IRUGO, goodix_sysfs_update_result_show, NULL), + __EXTMOD_ATTR(fwversion, S_IRUGO, goodix_sysfs_update_fwversion_show, + NULL), + __EXTMOD_ATTR(fwsize, S_IRUGO | S_IWUGO, goodix_sysfs_fwsize_show, + goodix_sysfs_fwsize_store), + __EXTMOD_ATTR(force_update, S_IWUGO, NULL, + goodix_sysfs_force_update_store), +}; + +static int goodix_syfs_init(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct fw_update_ctrl *fw_ctrl = module->priv_data; + struct kobj_type *ktype; + int ret = 0, i; + + ktype = goodix_get_default_ktype(); + ret = kobject_init_and_add(&module->kobj, ktype, + &core_data->pdev->dev.kobj, "fwupdate"); + if (ret) { + ts_err("Create fwupdate sysfs node error!"); + goto exit_sysfs_init; + } + + for (i = 0; i < ARRAY_SIZE(goodix_fwu_attrs); i++) { + if (sysfs_create_file(&module->kobj, + &goodix_fwu_attrs[i].attr)) { + ts_err("Create sysfs attr file error"); + kobject_put(&module->kobj); + ret = -EINVAL; + goto exit_sysfs_init; + } + } + + fw_ctrl->attr_fwimage.attr.name = "fwimage"; + fw_ctrl->attr_fwimage.attr.mode = S_IRUGO | S_IWUGO; + fw_ctrl->attr_fwimage.size = 0; + fw_ctrl->attr_fwimage.write = goodix_sysfs_fwimage_store; + ret = sysfs_create_bin_file(&module->kobj, &fw_ctrl->attr_fwimage); + +exit_sysfs_init: + return ret; +} + +static int goodix_fw_update_init(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct goodix_ts_board_data *ts_bdata = board_data(core_data); + struct task_struct *fwu_thrd; + struct fw_update_ctrl *fwu_ctrl; + static bool init_sysfs = true; + + if (!core_data->ts_dev) + return -ENODEV; + + if (!module->priv_data) { + module->priv_data = + kzalloc(sizeof(struct fw_update_ctrl), GFP_KERNEL); + if (!module->priv_data) { + ts_err("Failed to alloc memory for fwu_ctrl"); + return -ENOMEM; + } + } + fwu_ctrl = module->priv_data; + fwu_ctrl->ts_dev = core_data->ts_dev; + fwu_ctrl->allow_reset = true; + fwu_ctrl->allow_irq = true; + fwu_ctrl->allow_suspend = true; + fwu_ctrl->allow_resume = true; + fwu_ctrl->core_data = core_data; + + /* find a valid firmware image name */ + if (ts_bdata && ts_bdata->fw_name) { + strlcpy(fwu_ctrl->fw_name, ts_bdata->fw_name, + sizeof(fwu_ctrl->fw_name)); + ts_info("find goodix firmware:%s\n", ts_bdata->fw_name); + } else { + strlcpy(fwu_ctrl->fw_name, TS_DEFAULT_FIRMWARE, + sizeof(fwu_ctrl->fw_name)); + ts_info("can't find goodix firmware,use default name\n"); + } + + /* create sysfs interface */ + if (init_sysfs) { + if (!goodix_syfs_init(core_data, module)) + init_sysfs = false; + } + + /* create and run update thread */ + fwu_thrd = kthread_run(goodix_fw_update_thread, module->priv_data, + "goodix-fwu"); + if (IS_ERR_OR_NULL(fwu_thrd)) { + ts_err("goodix:Failed to create update thread:%ld", + PTR_ERR(fwu_thrd)); + return -EFAULT; + } + + return 0; +} + +static int goodix_fw_update_exit(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + return 0; +} + +static int goodix_fw_before_suspend(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct fw_update_ctrl *fwu_ctrl = module->priv_data; + + return fwu_ctrl->allow_suspend ? EVT_HANDLED : EVT_CANCEL_SUSPEND; +} + +static int goodix_fw_before_resume(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct fw_update_ctrl *fwu_ctrl = module->priv_data; + return fwu_ctrl->allow_resume ? EVT_HANDLED : EVT_CANCEL_RESUME; +} + +static int goodix_fw_after_resume(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + return 0; +} + +static int goodix_fw_irq_event(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct fw_update_ctrl *fwu_ctrl = module->priv_data; + return fwu_ctrl->allow_irq ? EVT_HANDLED : EVT_CANCEL_IRQEVT; +} + +static int goodix_fw_before_reset(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct fw_update_ctrl *fwu_ctrl = module->priv_data; + return fwu_ctrl->allow_reset ? EVT_HANDLED : EVT_CANCEL_RESET; +} + +static const struct goodix_ext_module_funcs goodix_ext_funcs = { + .init = goodix_fw_update_init, + .exit = goodix_fw_update_exit, + .before_reset = goodix_fw_before_reset, + .after_reset = NULL, + .before_suspend = goodix_fw_before_suspend, + .after_suspend = NULL, + .before_resume = goodix_fw_before_resume, + .after_resume = goodix_fw_after_resume, + .irq_event = goodix_fw_irq_event, +}; + +static struct goodix_ext_module goodix_fwu_module = { + .name = "goodix-fwu", + .funcs = &goodix_ext_funcs, + .priority = EXTMOD_PRIO_FWUPDATE, +}; + +static int __init goodix_fwu_module_init(void) +{ + pr_err("goodix firmware update module init start\n"); + return goodix_register_ext_module(&goodix_fwu_module); +} + +static void __exit goodix_fwu_module_exit(void) +{ + return; +} + +module_init(goodix_fwu_module_init); +module_exit(goodix_fwu_module_exit); + +MODULE_DESCRIPTION("Goodix FWU Module"); +MODULE_AUTHOR("Goodix, Inc."); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c new file mode 100644 index 000000000000..37eadcd09e81 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c @@ -0,0 +1,2910 @@ +/* + * Goodix Touchscreen Driver + * Core layer of touchdriver architecture. + * + * Copyright (C) 2015 - 2016 Goodix, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: Yulong Cai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be a reference + * to you, when you are integrating the GOODiX's CTP IC into your system, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_DRM +#include +#include +#include +#endif +#include +#include +//#include +#include "goodix_ts_core.h" + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 38) +#include +#define INPUT_TYPE_B_PROTOCOL +#endif +#include +#include "../xiaomi/xiaomi_touch.h" +#include "test_core/test_param_init.h" + +#define INPUT_EVENT_START 0 +#define INPUT_EVENT_SENSITIVE_MODE_OFF 0 +#define INPUT_EVENT_SENSITIVE_MODE_ON 1 +#define INPUT_EVENT_STYLUS_MODE_OFF 2 +#define INPUT_EVENT_STYLUS_MODE_ON 3 +#define INPUT_EVENT_WAKUP_MODE_OFF 4 +#define INPUT_EVENT_WAKUP_MODE_ON 5 +#define INPUT_EVENT_COVER_MODE_OFF 6 +#define INPUT_EVENT_COVER_MODE_ON 7 +#define INPUT_EVENT_SLIDE_FOR_VOLUME 8 +#define INPUT_EVENT_DOUBLE_TAP_FOR_VOLUME 9 +#define INPUT_EVENT_SINGLE_TAP_FOR_VOLUME 10 +#define INPUT_EVENT_LONG_SINGLE_TAP_FOR_VOLUME 11 +#define INPUT_EVENT_PALM_OFF 12 +#define INPUT_EVENT_PALM_ON 13 +#define INPUT_EVENT_END 13 +#define IS_USB_EXIST 0x06 +#define IS_USB_NOT_EXIST 0x07 + +#define GOOIDX_INPUT_PHYS "goodix_ts/input0" +#define PINCTRL_STATE_ACTIVE "pmx_ts_active" +#define PINCTRL_STATE_SUSPEND "pmx_ts_suspend" +extern int goodix_start_cfg_bin(struct goodix_ts_core *ts_core); +extern int goodix_i2c_write(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len); + +struct goodix_module goodix_modules; +struct goodix_ts_core *goodix_core_data; +/** + * __do_register_ext_module - register external module + * to register into touch core modules structure + */ +static void __do_register_ext_module(struct work_struct *work) +{ + struct goodix_ext_module *module = + container_of(work, struct goodix_ext_module, work); + struct goodix_ext_module *ext_module; + struct list_head *insert_point = &goodix_modules.head; + + ts_info("__do_register_ext_module IN, goodix_modules.core_exit:%d", + goodix_modules.core_exit); + + /* waitting for core layer */ + if (!wait_for_completion_timeout(&goodix_modules.core_comp, 25 * HZ)) { + ts_err("Module [%s] timeout", module->name); + return; + } + + /* driver probe failed */ + if (goodix_modules.core_exit) { + ts_err("Can't register ext_module, core exit"); + return; + } + ts_info("start register ext_module"); + /* prority level *must* be set */ + if (module->priority == EXTMOD_PRIO_RESERVED) { + ts_err("Priority of module [%s] needs to be set", module->name); + return; + } + + mutex_lock(&goodix_modules.mutex); + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (ext_module == module) { + ts_info("Module [%s] already exists", + module->name); + mutex_unlock(&goodix_modules.mutex); + return; + } + } + + list_for_each_entry(ext_module, &goodix_modules.head, list) { + /* small value of priority have + * higher priority level*/ + if (ext_module->priority >= module->priority) { + insert_point = &ext_module->list; + break; + } + } /* else module will be inserted + to goodix_modules->head */ + } + + if (module->funcs && module->funcs->init) { + if (module->funcs->init(goodix_modules.core_data, module) < 0) { + ts_err("Module [%s] init error", + module->name ? module->name : " "); + mutex_unlock(&goodix_modules.mutex); + return; + } + } + list_add(&module->list, insert_point->prev); + goodix_modules.count++; + mutex_unlock(&goodix_modules.mutex); + ts_info("Module [%s] registered,priority:%u", module->name, + module->priority); + return; +} + +/** + * goodix_register_ext_module - interface for external module + * to register into touch core modules structure + * + * @module: pointer to external module to be register + * return: 0 ok, <0 failed + */ +int goodix_register_ext_module(struct goodix_ext_module *module) +{ + if (!module) + return -EINVAL; + + if (!goodix_modules.initilized) { + goodix_modules.initilized = true; + goodix_modules.core_exit = true; + INIT_LIST_HEAD(&goodix_modules.head); + mutex_init(&goodix_modules.mutex); + init_completion(&goodix_modules.core_comp); + } + + /*if (goodix_modules.core_exit) { + ts_err("Can't register ext_module, core exit"); + return -EFAULT; + } +*/ + ts_info("goodix_register_ext_module IN"); + INIT_WORK(&module->work, __do_register_ext_module); + schedule_work(&module->work); + ts_info("goodix_register_ext_module OUT"); + return 0; +} +EXPORT_SYMBOL_GPL(goodix_register_ext_module); + +/** + * goodix_unregister_ext_module - interface for external module + * to unregister external modules + * + * @module: pointer to external module + * return: 0 ok, <0 failed + */ +int goodix_unregister_ext_module(struct goodix_ext_module *module) +{ + struct goodix_ext_module *ext_module; + bool found = false; + if (!module) + return -EINVAL; + if (!goodix_modules.initilized) + return -EINVAL; + if (!goodix_modules.core_data) + return -ENODEV; + mutex_lock(&goodix_modules.mutex); + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (ext_module == module) { + found = true; + break; + } + } + } else { + mutex_unlock(&goodix_modules.mutex); + return -EFAULT; + } + + if (!found) { + ts_err("Module [%s] never registed", module->name); + mutex_unlock(&goodix_modules.mutex); + return -EFAULT; + } + + list_del(&module->list); + mutex_unlock(&goodix_modules.mutex); + if (module->funcs && module->funcs->exit) + module->funcs->exit(goodix_modules.core_data, module); + goodix_modules.count--; + ts_info("Moudle [%s] unregistered", module->name ? module->name : " "); + return 0; +} +EXPORT_SYMBOL_GPL(goodix_unregister_ext_module); + +static void goodix_ext_sysfs_release(struct kobject *kobj) +{ + ts_info("Kobject released!"); +} + +#define to_ext_module(kobj) container_of(kobj, struct goodix_ext_module, kobj) +#define to_ext_attr(attr) container_of(attr, struct goodix_ext_attribute, attr) + +static ssize_t goodix_ext_sysfs_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct goodix_ext_module *module = to_ext_module(kobj); + struct goodix_ext_attribute *ext_attr = to_ext_attr(attr); + + if (ext_attr->show) + return ext_attr->show(module, buf); + return -EIO; +} + +static ssize_t goodix_ext_sysfs_store(struct kobject *kobj, + struct attribute *attr, const char *buf, + size_t count) +{ + struct goodix_ext_module *module = to_ext_module(kobj); + struct goodix_ext_attribute *ext_attr = to_ext_attr(attr); + + if (ext_attr->store) + return ext_attr->store(module, buf, count); + return -EIO; +} + +static const struct sysfs_ops goodix_ext_ops = { + .show = goodix_ext_sysfs_show, + .store = goodix_ext_sysfs_store +}; + +static struct kobj_type goodix_ext_ktype = { + .release = goodix_ext_sysfs_release, + .sysfs_ops = &goodix_ext_ops, +}; + +struct kobj_type *goodix_get_default_ktype(void) +{ + return &goodix_ext_ktype; +} +EXPORT_SYMBOL_GPL(goodix_get_default_ktype); + +struct kobject *goodix_get_default_kobj(void) +{ + struct kobject *kobj = NULL; + + if (goodix_modules.core_data && goodix_modules.core_data->pdev) + kobj = &goodix_modules.core_data->pdev->dev.kobj; + return kobj; +} +EXPORT_SYMBOL_GPL(goodix_get_default_kobj); + +/* debug fs */ +struct debugfs_buf { + struct debugfs_blob_wrapper buf; + int pos; + struct dentry *dentry; +} goodix_dbg; + +void goodix_msg_printf(const char *fmt, ...) +{ + va_list args; + int r; + + if (goodix_dbg.pos < goodix_dbg.buf.size) { + va_start(args, fmt); + r = vscnprintf(goodix_dbg.buf.data + goodix_dbg.pos, + goodix_dbg.buf.size - 1, fmt, args); + goodix_dbg.pos += r; + va_end(args); + } +} +EXPORT_SYMBOL_GPL(goodix_msg_printf); + +static int goodix_debugfs_init(void) +{ + struct dentry *r_b; + goodix_dbg.buf.size = PAGE_SIZE; + goodix_dbg.pos = 0; + goodix_dbg.buf.data = kzalloc(goodix_dbg.buf.size, GFP_KERNEL); + if (goodix_dbg.buf.data == NULL) { + pr_err("Debugfs init failed\n"); + goto exit; + } + r_b = debugfs_create_blob("goodix_ts", 0644, NULL, &goodix_dbg.buf); + if (!r_b) { + pr_err("Debugfs create failed\n"); + return -ENOENT; + } + goodix_dbg.dentry = r_b; + +exit: + return 0; +} + +static void goodix_debugfs_exit(void) +{ + debugfs_remove(goodix_dbg.dentry); + goodix_dbg.dentry = NULL; + pr_info("Debugfs module exit\n"); +} + +/* show external module infomation */ +static ssize_t goodix_ts_extmod_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct goodix_ext_module *module; + size_t offset = 0; + int r; + + mutex_lock(&goodix_modules.mutex); + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(module, &goodix_modules.head, list) { + r = snprintf(&buf[offset], PAGE_SIZE, + "priority:%u module:%s\n", + module->priority, module->name); + if (r < 0) { + mutex_unlock(&goodix_modules.mutex); + return -EINVAL; + } + offset += r; + } + } + + mutex_unlock(&goodix_modules.mutex); + return offset; +} + +/* show driver infomation */ +static ssize_t goodix_ts_driver_info_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "DriverVersion:%s\n", + GOODIX_DRIVER_VERSION); +} + +/* show chip infoamtion */ +static ssize_t goodix_ts_chip_info_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + struct goodix_ts_version chip_ver; + int r, cnt = 0; + + cnt += snprintf(buf, PAGE_SIZE, "TouchDeviceName:%s\n", ts_dev->name); + if (ts_dev->hw_ops->read_version) { + r = ts_dev->hw_ops->read_version(ts_dev, &chip_ver); + if (!r && chip_ver.valid) { + cnt += snprintf( + &buf[cnt], PAGE_SIZE, + "PID:%s\nVID:%02x %02x %02x %02x\nSensorID:%02x\n", + chip_ver.pid, chip_ver.vid[0], chip_ver.vid[1], + chip_ver.vid[2], chip_ver.vid[3], + chip_ver.sensor_id); + } + } + return cnt; +} + +/* show chip configuration data */ +static ssize_t goodix_ts_config_data_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + struct goodix_ts_config *ncfg = ts_dev->normal_cfg; + u8 *data; + int i, r, offset = 0; + + if (ncfg && ncfg->initialized && ncfg->length < PAGE_SIZE) { + data = kmalloc(ncfg->length, GFP_KERNEL); + if (!data) + return -ENOMEM; + + r = ts_dev->hw_ops->read(ts_dev, ncfg->reg_base, &data[0], + ncfg->length); + if (r < 0) { + kfree(data); + return -EINVAL; + } + + for (i = 0; i < ncfg->length; i++) { + if (i != 0 && i % 20 == 0) + buf[offset++] = '\n'; + offset += snprintf(&buf[offset], PAGE_SIZE - offset, + "%02x ", data[i]); + } + buf[offset++] = '\n'; + buf[offset++] = '\0'; + kfree(data); + return offset; + } + return -EINVAL; +} + +/* reset chip */ +static ssize_t goodix_ts_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + int en; + + if (sscanf(buf, "%d", &en) != 1) + return -EINVAL; + if (en != 1) + return -EINVAL; + if (ts_dev->hw_ops->reset) + ts_dev->hw_ops->reset(ts_dev); + return count; +} + +static ssize_t goodix_ts_read_cfg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + int ret, i, offset; + char *cfg_buf; + + cfg_buf = kzalloc(4096, GFP_KERNEL); + disable_irq(core_data->irq); + if (ts_dev->hw_ops->read_config) + ret = ts_dev->hw_ops->read_config(ts_dev, cfg_buf, 0); + else + ret = -EINVAL; + enable_irq(core_data->irq); + + offset = 0; + if (ret > 0) { + for (i = 0; i < ret; i++) { + if (i != 0 && i % 20 == 0) + buf[offset++] = '\n'; + offset += snprintf(&buf[offset], 4096 - offset, "%02x ", + cfg_buf[i]); + } + } + kfree(cfg_buf); + return ret; +} + +static int goodix_ts_convert_0x_data(const u8 *buf, int buf_size, + unsigned char *out_buf, int *out_buf_len) +{ + int i, m_size = 0; + int temp_index = 0; + + for (i = 0; i < buf_size; i++) { + if (buf[i] == 'x' || buf[i] == 'X') + m_size++; + } + ts_info("***m_size:%d", m_size); + if (m_size <= 1) { + ts_err("cfg file ERROR, valid data count:%d\n", m_size); + return -EINVAL; + } + *out_buf_len = m_size; + for (i = 0; i < buf_size; i++) { + if (buf[i] == 'x' || buf[i] == 'X') { + if (temp_index >= m_size) { + ts_err("exchange cfg data error, overflow, temp_index:%d,m_size:%d\n", + temp_index, m_size); + return -EINVAL; + } + if (buf[i + 1] >= '0' && buf[i + 1] <= '9') + out_buf[temp_index] = (buf[i + 1] - '0') << 4; + else if (buf[i + 1] >= 'a' && buf[i + 1] <= 'f') + out_buf[temp_index] = (buf[i + 1] - 'a' + 10) + << 4; + else if (buf[i + 1] >= 'A' && buf[i + 1] <= 'F') + out_buf[temp_index] = (buf[i + 1] - 'A' + 10) + << 4; + if (buf[i + 2] >= '0' && buf[i + 2] <= '9') + out_buf[temp_index] += (buf[i + 2] - '0'); + else if (buf[i + 2] >= 'a' && buf[i + 2] <= 'f') + out_buf[temp_index] += (buf[i + 2] - 'a' + 10); + else if (buf[i + 2] >= 'A' && buf[i + 2] <= 'F') + out_buf[temp_index] += (buf[i + 2] - 'A' + 10); + temp_index++; + } + } + return 0; +} + +static ssize_t goodix_ts_send_cfg_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + int en, r; + const struct firmware *cfg_img; + struct goodix_ts_config *config = NULL; + + ts_err("%s::enter\n", __func__); + if (sscanf(buf, "%d", &en) != 1) + return -EINVAL; + + if (en != 1) + return -EINVAL; + + ts_err("en:%d", en); + disable_irq(core_data->irq); + + /*request configuration*/ + r = request_firmware(&cfg_img, GOODIX_DEFAULT_CFG_NAME, dev); + if (r < 0) { + ts_err("cfg file [%s] not available,errno:%d", + GOODIX_DEFAULT_CFG_NAME, r); + goto exit; + } else + ts_info("cfg file [%s] is ready", GOODIX_DEFAULT_CFG_NAME); + + config = kzalloc(sizeof(struct goodix_ts_config), GFP_KERNEL); + if (config == NULL) { + ts_err("Memory allco err"); + goto exit; + } + + /*parse cfg data*/ + if (goodix_ts_convert_0x_data(cfg_img->data, cfg_img->size, + config->data, &config->length)) { + ts_err("convert config data FAILED"); + goto exit; + } + + config->reg_base = ts_dev->reg.cfg_addr; + mutex_init(&config->lock); + config->initialized = true; + if (ts_dev->hw_ops->send_config) + ts_dev->hw_ops->send_config(ts_dev, config); + +exit: + enable_irq(core_data->irq); + if (config) { + kfree(config); + config = NULL; + } + if (cfg_img) { + release_firmware(cfg_img); + cfg_img = NULL; + } + ts_info("******OUT"); + return count; +} + +/* show irq infomation */ +static ssize_t goodix_ts_irq_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + struct irq_desc *desc; + size_t offset = 0; + int r; + + r = snprintf(&buf[offset], PAGE_SIZE, "irq:%u\n", core_data->irq); + if (r < 0) + return -EINVAL; + + offset += r; + r = snprintf(&buf[offset], PAGE_SIZE - offset, "state:%s\n", + atomic_read(&core_data->irq_enabled) ? "enabled" : + "disabled"); + if (r < 0) + return -EINVAL; + + desc = irq_to_desc(core_data->irq); + offset += r; + r = snprintf(&buf[offset], PAGE_SIZE - offset, "disable-depth:%d\n", + desc->depth); + if (r < 0) + return -EINVAL; + + offset += r; + r = snprintf(&buf[offset], PAGE_SIZE - offset, "trigger-count:%zu\n", + core_data->irq_trig_cnt); + if (r < 0) + return -EINVAL; + + offset += r; + r = snprintf(&buf[offset], PAGE_SIZE - offset, + "echo 0/1 > irq_info to disable/enable irq"); + if (r < 0) + return -EINVAL; + offset += r; + return offset; +} + +/* enable/disable irq */ +static ssize_t goodix_ts_irq_info_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + int en; + + if (sscanf(buf, "%d", &en) != 1) + return -EINVAL; + goodix_ts_irq_enable(core_data, en); + return count; +} + +/* open short test */ +static ssize_t goodix_ts_tp_test_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + int r = 0; + ret = goodix_tools_register(); + + if (ret) { + ret = 0; + ts_err("tp_test prepare goodix_tools_register failed"); + r = snprintf(buf, sizeof(ret), "%d", ret); + if (r < 0) + return -EINVAL; + return sizeof(ret); + } + ts_info("test start!"); + ret = test_process(dev); + + if (ret == 0) { + ret = 1; + ts_err("test PASS!"); + } else { + ts_err("test FAILED. result:%x", ret); + ret = 0; + } + goodix_tools_unregister(); + r = snprintf(buf, sizeof(ret), "%d\n", ret); + if (r < 0) + return -EINVAL; + + ts_info("test finish!"); + return sizeof(ret); +} + +/* tp get rawdata */ +static ssize_t goodix_ts_tp_rawdata_show(struct device *dev, + struct device_attribute *attr, + char *buf) + +{ + int ret = 0; + int r = 0; + int buf_size = 0; + ret = goodix_tools_register(); + + if (ret) { + ret = 0; + ts_err("tp_rawdata prepare goodix_tools_register failed"); + r = snprintf(buf, 6, "-EIO\t\n"); + if (r < 0) + return -EINVAL; + return 4; /*sizeof("-EIO")*/ + } + ts_info("start get rawdata!"); + ret = get_tp_rawdata(dev, buf, &buf_size); + goodix_tools_unregister(); + ts_info("test finish!"); + return ret; +} + +static ssize_t goodix_ts_power_reset_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + const struct goodix_ts_hw_ops *hw_ops = ts_hw_ops(core_data); + + int ret = 0; + ts_info("ts power reset test!"); + + goodix_ts_power_off(core_data); + goodix_ts_power_on(core_data); + if (hw_ops->reset) + hw_ops->reset(core_data->ts_dev); + + return ret; +} + +/* tp get test config */ +static ssize_t goodix_ts_tp_get_testcfg_show(struct device *dev, + struct device_attribute *attr, + char *buf) + +{ + int ret = 0; + int r = 0; + int buf_size = 0; + ret = goodix_tools_register(); + + if (ret) { + ret = 0; + ts_err("tp_rawdata prepare goodix_tools_register failed"); + r = snprintf(buf, 6, "-EIO\t\n"); + if (r < 0) + return -EINVAL; + return 4; /*sizeof("-EIO")*/ + } + + ts_info("start get rawdata!"); + ret = get_tp_testcfg(dev, buf, &buf_size); + goodix_tools_unregister(); + ts_info("test finish!"); + return ret; +} +static DEVICE_ATTR(extmod_info, S_IRUGO, goodix_ts_extmod_show, NULL); +static DEVICE_ATTR(driver_info, S_IRUGO, goodix_ts_driver_info_show, NULL); +static DEVICE_ATTR(chip_info, S_IRUGO, goodix_ts_chip_info_show, NULL); +static DEVICE_ATTR(config_data, S_IRUGO, goodix_ts_config_data_show, NULL); +static DEVICE_ATTR(reset, S_IWUSR | S_IWGRP, NULL, goodix_ts_reset_store); +static DEVICE_ATTR(send_cfg, S_IWUSR | S_IWGRP, NULL, goodix_ts_send_cfg_store); +static DEVICE_ATTR(read_cfg, S_IRUGO, goodix_ts_read_cfg_show, NULL); +static DEVICE_ATTR(irq_info, S_IRUGO | S_IWUSR | S_IWGRP, + goodix_ts_irq_info_show, goodix_ts_irq_info_store); +static DEVICE_ATTR(tp_test, S_IRUGO, goodix_ts_tp_test_show, NULL); +static DEVICE_ATTR(tp_rawdata, S_IRUGO, goodix_ts_tp_rawdata_show, NULL); +static DEVICE_ATTR(tp_get_testcfg, S_IRUGO, goodix_ts_tp_get_testcfg_show, + NULL); +static DEVICE_ATTR(tp_power_reset, S_IRUGO, goodix_ts_power_reset_show, NULL); + +static struct attribute *sysfs_attrs[] = { + &dev_attr_extmod_info.attr, + &dev_attr_driver_info.attr, + &dev_attr_chip_info.attr, + &dev_attr_config_data.attr, + &dev_attr_reset.attr, + &dev_attr_send_cfg.attr, + &dev_attr_read_cfg.attr, + &dev_attr_irq_info.attr, + &dev_attr_tp_test.attr, + &dev_attr_tp_rawdata.attr, + &dev_attr_tp_get_testcfg.attr, + &dev_attr_tp_power_reset.attr, + NULL, +}; + +static const struct attribute_group sysfs_group = { + .attrs = sysfs_attrs, +}; + +int goodix_ts_sysfs_init(struct goodix_ts_core *core_data) +{ + return sysfs_create_group(&core_data->pdev->dev.kobj, &sysfs_group); +} + +static void goodix_ts_sysfs_exit(struct goodix_ts_core *core_data) +{ + sysfs_remove_group(&core_data->pdev->dev.kobj, &sysfs_group); +} + +/* event notifier */ +static BLOCKING_NOTIFIER_HEAD(ts_notifier_list); +/** + * goodix_ts_register_client - register a client notifier + * @nb: notifier block to callback on events + * see enum ts_notify_event in goodix_ts_core.h + */ +int goodix_ts_register_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&ts_notifier_list, nb); +} +EXPORT_SYMBOL(goodix_ts_register_notifier); + +/** + * goodix_ts_unregister_client - unregister a client notifier + * @nb: notifier block to callback on events + * see enum ts_notify_event in goodix_ts_core.h + */ +int goodix_ts_unregister_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&ts_notifier_list, nb); +} +EXPORT_SYMBOL(goodix_ts_unregister_notifier); + +/** + * fb_notifier_call_chain - notify clients of fb_events + * see enum ts_notify_event in goodix_ts_core.h + */ +int goodix_ts_blocking_notify(enum ts_notify_event evt, void *v) +{ + return blocking_notifier_call_chain(&ts_notifier_list, + (unsigned long)evt, v); +} +EXPORT_SYMBOL_GPL(goodix_ts_blocking_notify); + +static void release_all_touches(struct goodix_ts_core *core_data) +{ + unsigned int type = MT_TOOL_FINGER; + struct goodix_ts_device *ts_dev = core_data->ts_dev; + int i; + mutex_lock(&ts_dev->report_mutex); + + for (i = 0; i < GOODIX_MAX_TOUCH; i++) { + input_mt_slot(core_data->input_dev, i); + input_mt_report_slot_state(core_data->input_dev, type, 0); + } + ts_err("enter:%s core_data->touch_id=%d\n", __func__, + core_data->touch_id); + core_data->sleep_finger = core_data->touch_id; + core_data->touch_id = 0; + input_sync(core_data->input_dev); + mutex_unlock(&ts_dev->report_mutex); +} + +/** + * goodix_ts_input_report - report touch event to input subsystem + * + * @dev: input device pointer + * @touch_data: touch data pointer + * return: 0 ok, <0 failed + */ +static int goodix_ts_input_report(struct input_dev *dev, + struct goodix_touch_data *touch_data) +{ + struct goodix_ts_coords *coords = &touch_data->coords[0]; + struct goodix_ts_core *core_data = input_get_drvdata(dev); + struct goodix_ts_board_data *ts_bdata = board_data(core_data); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + unsigned int touch_num = touch_data->touch_num; + int i, id; + + if (core_data->fod_status) { + if ((core_data->event_status & 0x20) == 0x20) { + ts_info("%s:the data sended was error,return\n", + __func__); + return 0; + } + } + + mutex_lock(&ts_dev->report_mutex); + id = coords->id; + for (i = 0; i < ts_bdata->panel_max_id * 2; i++) { + if (touch_num && + i == id) { /* this is a valid touch down event */ + input_mt_slot(dev, id); + input_mt_report_slot_state(dev, MT_TOOL_FINGER, true); + + /*first touch down event*/ + input_report_key(dev, BTN_TOUCH, !!touch_num); + /*point position*/ + input_report_abs(dev, ABS_MT_POSITION_X, coords->x); + input_report_abs(dev, ABS_MT_POSITION_Y, coords->y); + /* + input_report_abs(dev, ABS_MT_TOUCH_MAJOR, coords->w); + input_report_abs(dev, ABS_MT_PRESSURE, coords->p); + input_report_abs(dev, ABS_MT_TOUCH_MINOR, coords->area); + */ + + if ((core_data->event_status & 0x88) != 0x88 || + !core_data->fod_status) + coords->overlapping_area = 0; + input_report_abs(dev, ABS_MT_WIDTH_MINOR, + coords->overlapping_area); + input_report_abs(dev, ABS_MT_WIDTH_MAJOR, + coords->overlapping_area); + if (!__test_and_set_bit(i, &core_data->touch_id)) { + ts_info("[GTP] %s report press:%d", __func__, + i); + } + dev_dbg(core_data->ts_dev->dev, + "[GTP] %s report:[%d](%d, %d, %d, %d)", + __func__, id, touch_data->coords[0].x, + touch_data->coords[0].y, + touch_data->coords[0].area, + touch_data->coords[0].overlapping_area); + id = (++coords)->id; + } else { + if (__test_and_clear_bit(i, &core_data->touch_id)) { + input_mt_slot(dev, i); + input_mt_report_slot_state(dev, MT_TOOL_FINGER, + false); + if (!touch_num) { + input_report_key(dev, BTN_TOUCH, + !!touch_num); + input_report_key(dev, BTN_TOOL_FINGER, + 0); + core_data->sleep_finger = 0; + } + ts_info("[GTP] %s report leave:%d", __func__, + i); + } + } + } + + /*report finger*/ + /*ts_info("get_event_now :0x%02x, pre_event : %d", get_event_now, pre_event);*/ + if ((core_data->event_status & 0x88) == 0x88 && core_data->fod_status) { + input_report_key(core_data->input_dev, BTN_INFO, 1); + /*input_report_key(core_data->input_dev, KEY_INFO, 1);*/ + core_data->fod_pressed = true; + ts_info("BTN_INFO press"); + } else if (core_data->fod_pressed && + (core_data->event_status & 0x88) != 0x88) { + if (unlikely(!core_data->fod_test)) { + input_report_key(core_data->input_dev, BTN_INFO, 0); + /*input_report_key(core_data->input_dev, KEY_INFO, 0);*/ + ts_info("BTN_INFO release"); + core_data->fod_pressed = false; + } + } + mutex_unlock(&ts_dev->report_mutex); + input_sync(dev); + /* check the ghost touch issue */ + if (!touch_num && core_data->touch_id) { + ts_err("touch fw miss the up event"); + release_all_touches(core_data); + } + + return 0; +} + +static void goodix_ts_sleep_work(struct work_struct *work) +{ + struct goodix_ts_core *core_data = + container_of(work, struct goodix_ts_core, sleep_work); + struct goodix_ts_device *ts_dev = core_data->ts_dev; + struct goodix_ext_module *ext_module; + struct goodix_ts_event *ts_event = &core_data->ts_event; + int r; + + ts_info("enter"); + + if (core_data->tp_already_suspend) { + r = wait_for_completion_timeout( + &core_data->pm_resume_completion, + msecs_to_jiffies(500)); + if (!r) { + ts_info("pm_resume_completion timeout, i2c is closed"); + return; + } else { + ts_info("pm_resume_completion be completed, handling irq"); + } + } + + mutex_lock(&goodix_modules.mutex); + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (!ext_module->funcs->irq_event) + continue; + r = ext_module->funcs->irq_event(core_data, ext_module); + if (r == EVT_CANCEL_IRQEVT) { + ts_info("irq exit"); + mutex_unlock(&goodix_modules.mutex); + return; + } + } + mutex_unlock(&goodix_modules.mutex); + + /* read touch data from touch device */ + r = ts_dev->hw_ops->event_handler(ts_dev, ts_event); + if (likely(r >= 0)) { + if (ts_event->event_type == EVENT_TOUCH) { + /* report touch */ + goodix_ts_input_report( + core_data->input_dev, + &ts_event->event_data.touch_data); + } + } + ts_info("exit"); +} + +/** + * goodix_ts_threadirq_func - Bottom half of interrupt + * This functions is excuted in thread context, + * sleep in this function is permit. + * + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +static irqreturn_t goodix_ts_threadirq_func(int irq, void *data) +{ + u8 irq_flag = 0; + struct goodix_ts_core *core_data = data; + struct goodix_ts_device *ts_dev = core_data->ts_dev; + struct goodix_ext_module *ext_module; + struct goodix_ts_event *ts_event = &core_data->ts_event; + int r; + struct i2c_client *client = NULL; + + client = to_i2c_client(ts_dev->dev); + i2c_set_clientdata(client, core_data); + + core_data->irq_trig_cnt++; + /* inform external module */ + /* ts_err("enter %s\n", __func__);*/ + if (core_data->tp_already_suspend) { + ts_info("device in suspend noirq, schedue to work"); + pm_wakeup_event(&client->dev, msecs_to_jiffies(500)); + queue_work(core_data->event_wq, &core_data->sleep_work); + return IRQ_HANDLED; + } + + mutex_lock(&goodix_modules.mutex); + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (!ext_module->funcs->irq_event) + continue; + r = ext_module->funcs->irq_event(core_data, ext_module); + /*ts_err("enter %s r=%d\n", __func__, r);*/ + if (r == EVT_CANCEL_IRQEVT) { + ts_err("enter %s EVT_CANCEL_IRQEVT \n", __func__); + mutex_unlock(&goodix_modules.mutex); + return IRQ_HANDLED; + } + } + mutex_unlock(&goodix_modules.mutex); + + /* read touch data from touch device */ + r = ts_dev->hw_ops->event_handler(ts_dev, ts_event); + if (likely(r >= 0)) { + if (ts_event->event_type == EVENT_TOUCH) { + /* report touch */ + goodix_ts_input_report( + core_data->input_dev, + &ts_event->event_data.touch_data); + } + } + /* clean irq flag */ + ts_dev->hw_ops->write_trans(ts_dev, ts_dev->reg.coor, &irq_flag, + 1); /*TS_REG_COORDS_BASE*/ + return IRQ_HANDLED; +} + +/** + * goodix_ts_init_irq - Requset interrput line from system + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +int goodix_ts_irq_setup(struct goodix_ts_core *core_data) +{ + const struct goodix_ts_board_data *ts_bdata = board_data(core_data); + int r; + + /* if ts_bdata-> irq is invalid */ + if (ts_bdata->irq <= 0) { + core_data->irq = gpio_to_irq(ts_bdata->irq_gpio); + } else { + core_data->irq = ts_bdata->irq; + } + + ts_info("IRQ:%u,flags:%d", core_data->irq, (int)ts_bdata->irq_flags); + r = devm_request_threaded_irq(&core_data->pdev->dev, core_data->irq, + NULL, goodix_ts_threadirq_func, + ts_bdata->irq_flags | IRQF_ONESHOT, + GOODIX_CORE_DRIVER_NAME, core_data); + if (r < 0) + ts_err("Failed to requeset threaded irq:%d", r); + else + atomic_set(&core_data->irq_enabled, 1); + return r; +} + +/** + * goodix_ts_irq_enable - Enable/Disable a irq + * @core_data: pointer to touch core data + * enable: enable or disable irq + * return: 0 ok, <0 failed + */ +int goodix_ts_irq_enable(struct goodix_ts_core *core_data, bool enable) +{ + if (enable) { + if (!atomic_cmpxchg(&core_data->irq_enabled, 0, 1)) { + enable_irq(core_data->irq); + ts_debug("Irq enabled"); + } + } else { + if (atomic_cmpxchg(&core_data->irq_enabled, 1, 0)) { + disable_irq(core_data->irq); + ts_debug("Irq disabled"); + } + } + return 0; +} +EXPORT_SYMBOL(goodix_ts_irq_enable); +/** + * goodix_ts_power_init - Get regulator for touch device + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +static int goodix_ts_power_init(struct goodix_ts_core *core_data) +{ + struct goodix_ts_board_data *ts_bdata; + ts_bdata = board_data(core_data); + + gpio_direction_output(ts_bdata->reset_gpio, 0); + gpio_direction_output(ts_bdata->irq_gpio, 1); + + return 0; +} + +/** + * goodix_ts_power_on - Turn on power to the touch device + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +int goodix_ts_power_on(struct goodix_ts_core *core_data) +{ + struct goodix_ts_board_data *ts_bdata = board_data(core_data); + int r = 0; + + ts_err("enter::%s\n", __func__); + if (core_data->power_on) + return 0; + gpio_direction_output(ts_bdata->vdd_gpio, 1); + gpio_direction_output(ts_bdata->avdd_gpio, 1); + core_data->power_on = 1; + return r; +} + +/** + * goodix_ts_power_off - Turn off power to the touch device + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +int goodix_ts_power_off(struct goodix_ts_core *core_data) +{ + struct goodix_ts_board_data *ts_bdata = board_data(core_data); + int r = 0; + + ts_info("Device power off"); + if (!core_data->power_on) + return 0; + gpio_direction_output(ts_bdata->vdd_gpio, 0); + gpio_direction_output(ts_bdata->avdd_gpio, 0); + core_data->power_on = 0; + return r; +} + +#ifdef CONFIG_PINCTRL +/** + * goodix_ts_pinctrl_init - Get pinctrl handler and pinctrl_state + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +static int goodix_ts_pinctrl_init(struct goodix_ts_core *core_data) +{ + int r = 0; + + /* get pinctrl handler from of node */ + core_data->pinctrl = devm_pinctrl_get(core_data->ts_dev->dev); + if (IS_ERR_OR_NULL(core_data->pinctrl)) { + ts_err("Failed to get pinctrl handler"); + return PTR_ERR(core_data->pinctrl); + } + + /* active state */ + core_data->pin_sta_active = + pinctrl_lookup_state(core_data->pinctrl, PINCTRL_STATE_ACTIVE); + if (IS_ERR_OR_NULL(core_data->pin_sta_active)) { + r = PTR_ERR(core_data->pin_sta_active); + ts_err("Failed to get pinctrl state:%s, r:%d", + PINCTRL_STATE_ACTIVE, r); + goto exit_pinctrl_put; + } + + /* suspend state */ + core_data->pin_sta_suspend = + pinctrl_lookup_state(core_data->pinctrl, PINCTRL_STATE_SUSPEND); + if (IS_ERR_OR_NULL(core_data->pin_sta_suspend)) { + r = PTR_ERR(core_data->pin_sta_suspend); + ts_err("Failed to get pinctrl state:%s, r:%d", + PINCTRL_STATE_SUSPEND, r); + goto exit_pinctrl_put; + } + + return 0; +exit_pinctrl_put: + devm_pinctrl_put(core_data->pinctrl); + core_data->pinctrl = NULL; + return r; +} +#endif + +/** + * goodix_ts_gpio_setup - Request gpio resources from GPIO subsysten + * reset_gpio and irq_gpio number are obtained from goodix_ts_device + * which created in hardware layer driver. e.g.goodix_xx_i2c.c + * A goodix_ts_device should set those two fileds to right value + * before registed to touch core driver. + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +static int goodix_ts_gpio_setup(struct goodix_ts_core *core_data) +{ + struct goodix_ts_board_data *ts_bdata = board_data(core_data); + int r = 0; + + ts_info("GPIO setup,reset-gpio:%d, irq-gpio:%d", ts_bdata->reset_gpio, + ts_bdata->irq_gpio); + /* + * after kenerl3.13, gpio_ api is deprecated, new + * driver should use gpiod_ api. + */ + r = devm_gpio_request_one(&core_data->pdev->dev, ts_bdata->reset_gpio, + GPIOF_OUT_INIT_HIGH, "ts_reset_gpio"); + if (r < 0) { + ts_err("Failed to request reset gpio, r:%d", r); + return r; + } + + r = devm_gpio_request_one(&core_data->pdev->dev, ts_bdata->irq_gpio, + GPIOF_IN, "ts_irq_gpio"); + if (r < 0) { + ts_err("Failed to request irq gpio, r:%d", r); + return r; + } + return 0; +} + +static ssize_t gtp_touch_suspend_notify_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", + !!atomic_read(&goodix_core_data->suspend_stat)); +} + +static ssize_t gtp_fod_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int value = 0; + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + + ts_info("buf:%c,count:%zu\n", buf[0], count); + sscanf(buf, "%u", &value); + if (value) { + input_report_key(core_data->input_dev, BTN_INFO, 1); + /*input_report_key(core_data->input_dev, KEY_INFO, 1);*/ + input_sync(core_data->input_dev); + input_mt_slot(core_data->input_dev, 0); + input_mt_report_slot_state(core_data->input_dev, MT_TOOL_FINGER, + 1); + input_report_key(core_data->input_dev, BTN_TOUCH, 1); + input_report_key(core_data->input_dev, BTN_TOOL_FINGER, 1); + input_report_abs(core_data->input_dev, ABS_MT_TRACKING_ID, 0); + input_report_abs(core_data->input_dev, ABS_MT_POSITION_X, + CENTER_X); + input_report_abs(core_data->input_dev, ABS_MT_POSITION_Y, + CENTER_Y); + input_report_abs(core_data->input_dev, ABS_MT_WIDTH_MINOR, 8); + input_report_abs(core_data->input_dev, ABS_MT_WIDTH_MAJOR, 8); + input_sync(core_data->input_dev); + } else { + input_mt_slot(core_data->input_dev, 0); + input_mt_report_slot_state(core_data->input_dev, MT_TOOL_FINGER, + 0); + input_report_abs(core_data->input_dev, ABS_MT_TRACKING_ID, -1); + input_report_key(core_data->input_dev, BTN_INFO, 0); + /*input_report_key(core_data->input_dev, KEY_INFO, 0);*/ + input_sync(core_data->input_dev); + } + return count; +} + +static ssize_t gtp_fod_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + + return snprintf(buf, 10, "%d\n", core_data->fod_status); +} + +static ssize_t gtp_fod_status_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + //struct goodix_ts_event *ts_event = &core_data->ts_event; + ts_info("buf:%s, count:%zu\n", buf, count); + sscanf(buf, "%u", &core_data->fod_status); + + //goodix_ts_input_report(core_data->input_dev,&ts_event->event_data.touch_data); + core_data->gesture_enabled = core_data->double_wakeup | + core_data->fod_status; + goodix_check_gesture_stat(!!core_data->fod_status); + + return count; +} +static DEVICE_ATTR(fod_status, (S_IRUGO | S_IWUSR | S_IWGRP), + gtp_fod_status_show, gtp_fod_status_store); + +static DEVICE_ATTR(fod_test, (S_IRUGO | S_IWUSR | S_IWGRP), NULL, + gtp_fod_test_store); + +static DEVICE_ATTR(touch_suspend_notify, (S_IRUGO | S_IRGRP), + gtp_touch_suspend_notify_show, NULL); + +static void goodix_switch_mode_work(struct work_struct *work) +{ + struct goodix_mode_switch *ms = + container_of(work, struct goodix_mode_switch, switch_mode_work); + + struct goodix_ts_core *info = ms->info; + unsigned char value = ms->mode; + +#ifdef CONFIG_GOODIX_HWINFO + char ch[16] = { + 0x0, + }; +#endif + if (value >= INPUT_EVENT_WAKUP_MODE_OFF && + value <= INPUT_EVENT_WAKUP_MODE_ON) { + info->double_wakeup = value - INPUT_EVENT_WAKUP_MODE_OFF; + info->gesture_enabled = info->double_wakeup | info->fod_status; + /*goodix_gesture_enable(!!info->gesture_enabled);*/ +#ifdef CONFIG_GOODIX_HWINFO + snprintf(ch, sizeof(ch), "%s", + info->gesture_enabled ? "enabled" : "disabled"); +#endif + } +} + +static int goodix_input_event(struct input_dev *dev, unsigned int type, + unsigned int code, int value) +{ + struct goodix_ts_core *core_data = input_get_drvdata(dev); + struct goodix_mode_switch *ms; + + if (!core_data) { + ts_err("core_data is NULL"); + return 0; + } + + if (type == EV_SYN && code == SYN_CONFIG) { + if (value >= INPUT_EVENT_START && value <= INPUT_EVENT_END) { + ms = (struct goodix_mode_switch *)kmalloc( + sizeof(struct goodix_mode_switch), GFP_ATOMIC); + if (ms != NULL) { + ms->info = core_data; + ms->mode = (unsigned char)value; + INIT_WORK(&ms->switch_mode_work, + goodix_switch_mode_work); + schedule_work(&ms->switch_mode_work); + } else { + ts_err("failed in allocating memory for switching mode"); + return -ENOMEM; + } + } else { + ts_err("Invalid event value"); + return -EINVAL; + } + } + return 0; +} + +/** + * goodix_input_set_params - set input parameters + */ +static void goodix_ts_set_input_params(struct input_dev *input_dev, + struct goodix_ts_board_data *ts_bdata) +{ + int i; + + if (ts_bdata->swap_axis) + swap(ts_bdata->panel_max_x, ts_bdata->panel_max_y); + input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, + ts_bdata->panel_max_x, 0, 0); + input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0, + ts_bdata->panel_max_y, 0, 0); + /*input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, + 0, ts_bdata->panel_max_w, 0, 0);*/ + /*input_set_abs_params(input_dev, ABS_MT_PRESSURE, + 0, ts_bdata->panel_max_p, 0, 0);*/ + /*input_set_abs_params(input_dev, ABS_MT_TOUCH_MINOR, + 0, ts_bdata->panel_max_w, 0, 0);*/ + input_set_abs_params(input_dev, ABS_MT_WIDTH_MINOR, 0, + ts_bdata->panel_max_overlapping_area, 0, 0); + input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, + ts_bdata->panel_max_overlapping_area, 0, 0); + if (ts_bdata->panel_max_key) { + for (i = 0; i < ts_bdata->panel_max_key; i++) + input_set_capability(input_dev, EV_KEY, + ts_bdata->panel_key_map[i]); + } +} + +/** + * goodix_ts_input_dev_config - Requset and config a input device + * then register it to input sybsystem. + * NOTE that some hardware layer may provide a input device + * (ts_dev->input_dev not NULL). + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +int goodix_ts_input_dev_config(struct goodix_ts_core *core_data) +{ + struct goodix_ts_board_data *ts_bdata = board_data(core_data); + struct input_dev *input_dev = NULL; + int r; + + input_dev = devm_input_allocate_device(&core_data->pdev->dev); + if (!input_dev) { + ts_err("Failed to allocated input device"); + return -ENOMEM; + } + + core_data->input_dev = input_dev; + input_set_drvdata(input_dev, core_data); + + input_dev->name = GOODIX_CORE_DRIVER_NAME; + input_dev->phys = GOOIDX_INPUT_PHYS; + input_dev->id.product = 0xDEAD; + input_dev->id.vendor = 0xBEEF; + input_dev->id.version = 10427; + input_dev->event = goodix_input_event; + + __set_bit(EV_SYN, input_dev->evbit); + __set_bit(EV_KEY, input_dev->evbit); + __set_bit(EV_ABS, input_dev->evbit); + __set_bit(BTN_TOUCH, input_dev->keybit); + __set_bit(BTN_TOOL_FINGER, input_dev->keybit); + +#ifdef INPUT_PROP_DIRECT + __set_bit(INPUT_PROP_DIRECT, input_dev->propbit); +#endif + + /* set input parameters */ + goodix_ts_set_input_params(input_dev, ts_bdata); + +#ifdef INPUT_TYPE_B_PROTOCOL +#if LINUX_VERSION_CODE > KERNEL_VERSION(3, 7, 0) + input_mt_init_slots(input_dev, ts_bdata->panel_max_id * 2 + 1, + INPUT_MT_DIRECT); +#else + input_mt_init_slots(input_dev, ts_bdata->panel_max_id * 2 + 1); +#endif +#endif + + input_set_capability(input_dev, EV_KEY, KEY_WAKEUP); + input_set_capability(input_dev, EV_KEY, BTN_INFO); + input_set_capability(input_dev, EV_KEY, KEY_GOTO); + /*input_set_capability(input_dev, EV_KEY, KEY_INFO);*/ + + r = input_register_device(input_dev); + if (r < 0) { + ts_err("Unable to register input device"); + return r; + } + return 0; +} + +/** + * goodix_ts_hw_init - Hardware initilize + * poweron - hardware reset - sendconfig + * @core_data: pointer to touch core data + * return: 0 intilize ok, <0 failed + */ +int goodix_ts_hw_init(struct goodix_ts_core *core_data) +{ + const struct goodix_ts_hw_ops *hw_ops = ts_hw_ops(core_data); + int r; + + /* reset touch device */ + if (hw_ops->reset) { + r = hw_ops->reset(core_data->ts_dev); + if (r < 0) + goto exit; + } + + /* init */ + if (hw_ops->init) { + r = hw_ops->init(core_data->ts_dev); + if (r < 0) + goto exit; + } + +exit: + /* if bus communication error occured then + * exit driver binding, other errors will + * be ignored */ + if (r != -EBUS) + r = 0; + return r; +} + +/** + * goodix_ts_esd_work - check hardware status and recovery + * the hardware if needed. + */ +static void goodix_ts_esd_work(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct goodix_ts_esd *ts_esd = + container_of(dwork, struct goodix_ts_esd, esd_work); + struct goodix_ts_core *core = + container_of(ts_esd, struct goodix_ts_core, ts_esd); + const struct goodix_ts_hw_ops *hw_ops = ts_hw_ops(core); + int r = 0; + u8 data = GOODIX_ESD_TICK_WRITE_DATA; + + if (ts_esd->esd_on == false) + return; + + if (hw_ops->check_hw) + r = hw_ops->check_hw(core->ts_dev); + if (r < 0) { + goodix_ts_power_off(core); + goodix_ts_power_on(core); + if (hw_ops->reset) + hw_ops->reset(core->ts_dev); + + /*init static esd*/ + if (core->ts_dev->ic_type == IC_TYPE_NANJING) { + r = hw_ops->write(core->ts_dev, 0x8043, &data, 1); + if (r < 0) + ts_err("nanjing esd reset, init static esd FAILED, i2c wirte ERROR"); + } + + /*init dynamic esd*/ + r = hw_ops->write_trans(core->ts_dev, core->ts_dev->reg.esd, + &data, 1); + if (r < 0) + ts_err("esd reset, init dynamic esd FAILED, i2c write ERROR"); + } else { + /*init dynamic esd*/ + r = hw_ops->write_trans(core->ts_dev, core->ts_dev->reg.esd, + &data, 1); + if (r < 0) + ts_err("esd init watch dog FAILED, i2c write ERROR"); + } + mutex_lock(&ts_esd->esd_mutex); + if (ts_esd->esd_on) + schedule_delayed_work(&ts_esd->esd_work, + GOODIX_ESD_CHECK_INTERVAL * HZ); + mutex_unlock(&ts_esd->esd_mutex); +} + +/** + * goodix_ts_esd_on - turn on esd protection + */ +static void goodix_ts_esd_on(struct goodix_ts_core *core) +{ + struct goodix_ts_esd *ts_esd = &core->ts_esd; + + if (core->ts_dev->reg.esd == 0) + return; + + mutex_lock(&ts_esd->esd_mutex); + if (ts_esd->esd_on == false) { + ts_esd->esd_on = true; + schedule_delayed_work(&ts_esd->esd_work, + GOODIX_ESD_CHECK_INTERVAL * HZ); + mutex_unlock(&ts_esd->esd_mutex); + ts_info("Esd on"); + return; + } + mutex_unlock(&ts_esd->esd_mutex); +} + +/** + * goodix_ts_esd_off - turn off esd protection + */ +static void goodix_ts_esd_off(struct goodix_ts_core *core) +{ + struct goodix_ts_esd *ts_esd = &core->ts_esd; + + mutex_lock(&ts_esd->esd_mutex); + if (ts_esd->esd_on == true) { + ts_esd->esd_on = false; + cancel_delayed_work(&ts_esd->esd_work); + mutex_unlock(&ts_esd->esd_mutex); + ts_info("Esd off"); + return; + } + mutex_unlock(&ts_esd->esd_mutex); +} + +/** + * goodix_esd_notifier_callback - notification callback + * under certain condition, we need to turn off/on the esd + * protector, we use kernel notify call chain to achieve this. + * + * for example: before firmware update we need to turn off the + * esd protector and after firmware update finished, we should + * turn on the esd protector. + */ +static int goodix_esd_notifier_callback(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct goodix_ts_esd *ts_esd = + container_of(nb, struct goodix_ts_esd, esd_notifier); + + switch (action) { + case NOTIFY_FWUPDATE_START: + case NOTIFY_SUSPEND: + case NOTIFY_ESD_OFF: + goodix_ts_esd_off(ts_esd->ts_core); + break; + case NOTIFY_FWUPDATE_END: + case NOTIFY_RESUME: + case NOTIFY_ESD_ON: + goodix_ts_esd_on(ts_esd->ts_core); + break; + } + return 0; +} + +/** + * goodix_ts_esd_init - initialize esd protection + */ +int goodix_ts_esd_init(struct goodix_ts_core *core) +{ + struct goodix_ts_esd *ts_esd = &core->ts_esd; + struct goodix_ts_device *dev = core->ts_dev; + u8 data = GOODIX_ESD_TICK_WRITE_DATA; + int r; + + INIT_DELAYED_WORK(&ts_esd->esd_work, goodix_ts_esd_work); + mutex_init(&ts_esd->esd_mutex); + ts_esd->ts_core = core; + ts_esd->esd_on = false; + ts_esd->esd_notifier.notifier_call = goodix_esd_notifier_callback; + goodix_ts_register_notifier(&ts_esd->esd_notifier); + + if (dev->hw_ops->check_hw && dev->reg.esd != 0) { + /*init static esd*/ + if (dev->ic_type == IC_TYPE_NANJING) { + r = dev->hw_ops->write_trans(core->ts_dev, 0x8043, + &data, 1); + if (r < 0) + ts_err("static ESD init ERROR, i2c write failed"); + } + + /*init dynamic esd*/ + r = dev->hw_ops->write_trans(core->ts_dev, + core->ts_dev->reg.esd, &data, 1); + if (r < 0) + ts_err("dynamic ESD init ERROR, i2c write failed"); + goodix_ts_esd_on(core); + } + return 0; +} + +/** + * goodix_ts_suspend - Touchscreen suspend function + * Called by PM/FB/EARLYSUSPEN module to put the device to sleep + */ +int goodix_ts_suspend(struct goodix_ts_core *core_data) +{ + struct goodix_ext_module *ext_module; + struct goodix_ts_device *ts_dev = core_data->ts_dev; + int r = 0; + + ts_info("Suspend start"); + + mutex_lock(&core_data->work_stat); + if (atomic_read(&core_data->suspend_stat)) { + ts_info("suspended, skip"); + goto out; + } + + /* + * notify suspend event, inform the esd protector + * and charger detector to turn off the work + */ + goodix_ts_blocking_notify(NOTIFY_SUSPEND, NULL); + + /* inform external module */ + mutex_lock(&goodix_modules.mutex); + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (!ext_module->funcs->before_suspend) + continue; + + r = ext_module->funcs->before_suspend(core_data, + ext_module); + if (r == EVT_CANCEL_SUSPEND) { + if (core_data->double_wakeup && + core_data->fod_status) { + atomic_set(&core_data->suspend_stat, + TP_GESTURE_DBCLK_FOD); + } else if (core_data->double_wakeup) { + atomic_set(&core_data->suspend_stat, + TP_GESTURE_DBCLK); + } else if (core_data->fod_status) { + atomic_set(&core_data->suspend_stat, + TP_GESTURE_FOD); + } + mutex_unlock(&goodix_modules.mutex); + ts_info("suspend_stat[%d]", + atomic_read(&core_data->suspend_stat)); + ts_info("Canceled by module:%s", + ext_module->name); + if (!atomic_read(&core_data->suspend_stat)) + ts_info("go suspend remaind work\n"); + else + goto out; + } + } + } + mutex_unlock(&goodix_modules.mutex); + + /* disable irq */ + goodix_ts_irq_enable(core_data, false); + + /* let touch ic work in sleep mode */ + if (ts_dev && ts_dev->hw_ops->suspend) + ts_dev->hw_ops->suspend(ts_dev); + atomic_set(&core_data->suspended, 1); + atomic_set(&core_data->suspend_stat, TP_SLEEP); + +#ifdef CONFIG_PINCTRL + if (core_data->pinctrl) { + r = pinctrl_select_state(core_data->pinctrl, + core_data->pin_sta_suspend); + if (r < 0) + ts_err("Failed to select active pinstate, r:%d", r); + } +#endif + + /* inform exteranl modules */ + mutex_lock(&goodix_modules.mutex); + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (!ext_module->funcs->after_suspend) + continue; + + r = ext_module->funcs->after_suspend(core_data, + ext_module); + if (r == EVT_CANCEL_SUSPEND) { + mutex_unlock(&goodix_modules.mutex); + ts_info("Canceled by module:%s", + ext_module->name); + goto out; + } + } + } + mutex_unlock(&goodix_modules.mutex); + +out: + /* release all the touch IDs */ + release_all_touches(core_data); + core_data->ts_event.event_data.touch_data.touch_num = 0; + + sysfs_notify(&core_data->gtp_touch_dev->kobj, NULL, + "touch_suspend_notify"); + + mutex_unlock(&core_data->work_stat); + + ts_info("Suspend end"); + return 0; +} + +/** + * goodix_ts_resume - Touchscreen resume function + * Called by PM/FB/EARLYSUSPEN module to wakeup device + */ +int goodix_ts_resume(struct goodix_ts_core *core_data) +{ + struct goodix_ext_module *ext_module; + struct goodix_ts_device *ts_dev = core_data->ts_dev; + int r = 0; + + ts_info("Resume start"); + /*goodix_ts_irq_enable(core_data, false);*/ + mutex_lock(&core_data->work_stat); + if (!atomic_read(&core_data->suspend_stat)) { + ts_info("resumed, skip"); + /*goodix_ts_irq_enable(core_data, true);*/ + goto out; + } + + mutex_lock(&goodix_modules.mutex); + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (!ext_module->funcs->before_resume) + continue; + + r = ext_module->funcs->before_resume(core_data, + ext_module); + if (r == EVT_CANCEL_RESUME) { + mutex_unlock(&goodix_modules.mutex); + ts_info("Canceled by module:%s", + ext_module->name); + goto out; + } + } + } + mutex_unlock(&goodix_modules.mutex); + +#ifdef CONFIG_PINCTRL + if (core_data->pinctrl) { + r = pinctrl_select_state(core_data->pinctrl, + core_data->pin_sta_active); + if (r < 0) + ts_err("Failed to select active pinstate, r:%d", r); + } +#endif + + atomic_set(&core_data->suspended, 0); + /* resume device */ + if (ts_dev && ts_dev->hw_ops->resume) + ts_dev->hw_ops->resume(ts_dev); + + atomic_set(&core_data->suspend_stat, TP_NO_SUSPEND); + + mutex_lock(&goodix_modules.mutex); + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (!ext_module->funcs->after_resume) + continue; + + r = ext_module->funcs->after_resume(core_data, + ext_module); + if (r == EVT_CANCEL_RESUME) { + mutex_unlock(&goodix_modules.mutex); + ts_info("Canceled by module:%s", + ext_module->name); + goto out; + } + } + } + mutex_unlock(&goodix_modules.mutex); + goodix_ts_irq_enable(core_data, true); +out: + /* + * notify resume event, inform the esd protector + * and charger detector to turn on the work + */ + goodix_ts_blocking_notify(NOTIFY_RESUME, NULL); + + ts_err("core_data->fod_pressed = %d\n", core_data->fod_pressed); + + if (!core_data->fod_pressed) { + ts_err("resume release all touch"); + release_all_touches(core_data); + } + core_data->sleep_finger = 0; + + sysfs_notify(&core_data->gtp_touch_dev->kobj, NULL, + "touch_suspend_notify"); + + mutex_unlock(&core_data->work_stat); + + ts_info("Resume end"); + return 0; +} + +static int goodix_bl_state_chg_callback(struct notifier_block *nb, + unsigned long val, void *data) +{ + struct goodix_ts_core *core_data = + container_of(nb, struct goodix_ts_core, bl_notifier); + unsigned int blank; + if (val != BACKLIGHT_UPDATED) + return NOTIFY_OK; + if (data && core_data) { + blank = *(int *)(data); + ts_info("%s val:%lu, blank:%u\n", __func__, val, blank); + if (blank == BACKLIGHT_OFF && + (atomic_read(&core_data->suspend_stat) && + core_data->fod_status)) { + ts_info("%s BACKLIGHT OFF, disable irq\n", __func__); + goodix_ts_irq_enable(core_data, false); + } else + goodix_ts_irq_enable(core_data, true); + } + return NOTIFY_OK; +} + +#ifdef CONFIG_DRM +/** + * goodix_ts_fb_notifier_callback - Framebuffer notifier callback + * Called by kernel during framebuffer blanck/unblank phrase + */ +int goodix_ts_fb_notifier_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct goodix_ts_core *core_data = + container_of(self, struct goodix_ts_core, fb_notifier); + struct drm_notify_data *fb_event = data; + int blank; + + if (fb_event && fb_event->data && core_data) { + blank = *(int *)(fb_event->data); + flush_workqueue(core_data->event_wq); + if (event == DRM_EVENT_BLANK && + (blank == DRM_BLANK_POWERDOWN || blank == DRM_BLANK_LP1 || + blank == DRM_BLANK_LP2)) { + ts_info("touchpanel suspend .....blank=%d\n", blank); + ts_info("touchpanel suspend .....suspend_stat=%d\n", + atomic_read(&core_data->suspend_stat)); + if (atomic_read(&core_data->suspend_stat)) + return 0; + ts_info("touchpanel suspend by %s", + blank == DRM_BLANK_POWERDOWN ? "blank" : + "doze"); + queue_work(core_data->event_wq, + &core_data->suspend_work); + } else if (event == DRM_EVENT_BLANK && + blank == DRM_BLANK_UNBLANK) { + //if (!atomic_read(&core_data->suspend_stat)) + ts_info("core_data->suspend_stat = %d\n", + atomic_read(&core_data->suspend_stat)); + ts_info("touchpanel resume"); + queue_work(core_data->event_wq, + &core_data->resume_work); + } + } + + return 0; +} +#endif + +#ifdef CONFIG_HAS_EARLYSUSPEND +/** + * goodix_ts_earlysuspend - Early suspend function + * Called by kernel during system suspend phrase + */ +static void goodix_ts_earlysuspend(struct early_suspend *h) +{ + struct goodix_ts_core *core_data = + container_of(h, struct goodix_ts_core, early_suspend); + + goodix_ts_suspend(core_data); +} +/** + * goodix_ts_lateresume - Late resume function + * Called by kernel during system wakeup + */ +static void goodix_ts_lateresume(struct early_suspend *h) +{ + struct goodix_ts_core *core_data = + container_of(h, struct goodix_ts_core, early_suspend); + goodix_ts_resume(core_data); +} +#endif + +#ifdef CONFIG_PM +#ifdef CONFIG_DRM +static void goodix_ts_resume_work(struct work_struct *work) +{ + struct goodix_ts_core *core_data = + container_of(work, struct goodix_ts_core, resume_work); + goodix_ts_resume(core_data); +} +static void goodix_ts_suspend_work(struct work_struct *work) +{ + struct goodix_ts_core *core_data = + container_of(work, struct goodix_ts_core, suspend_work); + goodix_ts_suspend(core_data); +} + +/** + * goodix_ts_pm_suspend - PM suspend function + * Called by kernel during system suspend phrase + */ +static int goodix_ts_pm_suspend(struct device *dev) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + if (device_may_wakeup(dev) && core_data->gesture_enabled) { + enable_irq_wake(core_data->irq); + } + + core_data->tp_already_suspend = true; + reinit_completion(&core_data->pm_resume_completion); + + return 0; +} +/** + * goodix_ts_pm_resume - PM resume function + * Called by kernel during system wakeup + */ +static int goodix_ts_pm_resume(struct device *dev) +{ + struct goodix_ts_core *core_data = dev_get_drvdata(dev); + if (device_may_wakeup(dev) && core_data->gesture_enabled) { + disable_irq_wake(core_data->irq); + } + + core_data->tp_already_suspend = false; + complete(&core_data->pm_resume_completion); + + return 0; +} + +#endif +#endif + +#ifdef CONFIG_TOUCHSCREEN_GOODIX_DEBUG_FS +/* +static void tpdbg_shutdown(struct goodix_ts_core *core_data, bool sleep) +{ + +} +*/ + +static void tpdbg_suspend(struct goodix_ts_core *core_data, bool enable) +{ + if (enable) + queue_work(core_data->event_wq, &core_data->suspend_work); + else + queue_work(core_data->event_wq, &core_data->resume_work); +} + +static int tpdbg_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + + return 0; +} + +static ssize_t tpdbg_read(struct file *file, char __user *buf, size_t size, + loff_t *ppos) +{ + const char *str = "cmd support as below:\n \ + echo \"irq-disable\" or \"irq-enable\" to ctrl irq\n \ + echo \"tp-suspend-en\" or \"tp-suspend-off\" to ctrl panel in or off suspend status\n"; + + loff_t pos = *ppos; + int len = strlen(str); + + if (pos < 0) + return -EINVAL; + if (pos >= len) + return 0; + + if (copy_to_user(buf, str, len)) + return -EFAULT; + + *ppos = pos + len; + + return len; +} + +static ssize_t tpdbg_write(struct file *file, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct goodix_ts_core *core_data = file->private_data; + char *cmd = kzalloc(size + 1, GFP_KERNEL); + int ret = size; + + if (!cmd) + return -ENOMEM; + + if (copy_from_user(cmd, buf, size)) { + ret = -EFAULT; + goto out; + } + + cmd[size] = '\0'; + + if (!strncmp(cmd, "irq-disable", 11)) + goodix_ts_irq_enable(core_data, false); + else if (!strncmp(cmd, "irq-enable", 10)) + goodix_ts_irq_enable(core_data, true); + /* + else if (!strncmp(cmd, "tp-sd-en", 8)) + tpdbg_shutdown(core_data, true); + else if (!strncmp(cmd, "tp-sd-off", 9)) + tpdbg_shutdown(core_data, false); +*/ + else if (!strncmp(cmd, "tp-suspend-en", 13)) + tpdbg_suspend(core_data, true); + else if (!strncmp(cmd, "tp-suspend-off", 14)) + tpdbg_suspend(core_data, false); +out: + kfree(cmd); + + return ret; +} + +static int tpdbg_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + + return 0; +} + +static const struct file_operations tpdbg_operations = { + .owner = THIS_MODULE, + .open = tpdbg_open, + .read = tpdbg_read, + .write = tpdbg_write, + .release = tpdbg_release, +}; +#endif + +/** + * goodix_generic_noti_callback - generic notifier callback + * for goodix touch notification event. + */ +int goodix_generic_noti_callback(struct notifier_block *self, + unsigned long action, void *data) +{ + struct goodix_ts_core *ts_core = + container_of(self, struct goodix_ts_core, ts_notifier); + const struct goodix_ts_hw_ops *hw_ops = ts_hw_ops(ts_core); + int r; + + switch (action) { + case NOTIFY_FWUPDATE_END: + if (hw_ops->init) { + /* Firmware has been updated, we need to reinit + * the chip, read the sensor ID and send the + * correct config data based on sensor ID. + * The input parameters also needs to be updated.*/ + r = hw_ops->init(ts_core->ts_dev); + if (r < 0) + goto exit; + goodix_ts_set_input_params(ts_core->input_dev, + ts_core->ts_dev->board_data); + } + break; + } +exit: + return 0; +} + +static ssize_t goodix_lockdown_info_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + int cnt = 0, ret = 0; +#define TP_INFO_MAX_LENGTH 50 + char tmp[TP_INFO_MAX_LENGTH]; + + if (*pos != 0 || !goodix_core_data) + return 0; + + cnt = snprintf( + tmp, TP_INFO_MAX_LENGTH, + "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + goodix_core_data->lockdown_info[0], + goodix_core_data->lockdown_info[1], + goodix_core_data->lockdown_info[2], + goodix_core_data->lockdown_info[3], + goodix_core_data->lockdown_info[4], + goodix_core_data->lockdown_info[5], + goodix_core_data->lockdown_info[6], + goodix_core_data->lockdown_info[7]); + ret = copy_to_user(buf, tmp, cnt); + *pos += cnt; + if (ret != 0) + return 0; + else + return cnt; +} + +static const struct file_operations goodix_lockdown_info_ops = { + .read = goodix_lockdown_info_read, +}; + +static ssize_t goodix_panel_color_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (!goodix_core_data) + return 0; + + return snprintf(buf, PAGE_SIZE, "%c\n", + goodix_core_data->lockdown_info[2]); +} + +static ssize_t goodix_panel_vendor_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + if (!goodix_core_data) + return 0; + + return snprintf(buf, PAGE_SIZE, "%c\n", + goodix_core_data->lockdown_info[6]); +} + +static ssize_t goodix_panel_display_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + if (!goodix_core_data) + return 0; + + return snprintf(buf, PAGE_SIZE, "%c\n", + goodix_core_data->lockdown_info[1]); +} + +static ssize_t goodix_lockdown_info_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + if (!goodix_core_data) + return 0; + + return snprintf( + buf, PAGE_SIZE, + "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + goodix_core_data->lockdown_info[0], + goodix_core_data->lockdown_info[1], + goodix_core_data->lockdown_info[2], + goodix_core_data->lockdown_info[3], + goodix_core_data->lockdown_info[4], + goodix_core_data->lockdown_info[5], + goodix_core_data->lockdown_info[6], + goodix_core_data->lockdown_info[7]); +} + +static DEVICE_ATTR(lockdown_info, (S_IRUGO), goodix_lockdown_info_show, NULL); +static DEVICE_ATTR(panel_vendor, (S_IRUGO), goodix_panel_vendor_show, NULL); +static DEVICE_ATTR(panel_color, (S_IRUGO), goodix_panel_color_show, NULL); +static DEVICE_ATTR(panel_display, (S_IRUGO), goodix_panel_display_show, NULL); + +static struct attribute *goodix_attr_group[] = { + &dev_attr_panel_vendor.attr, + &dev_attr_panel_color.attr, + &dev_attr_panel_display.attr, + &dev_attr_lockdown_info.attr, + NULL, +}; + +static int gtp_i2c_test(void) +{ + int ret = 0; + u8 read_val = 0; + struct goodix_ts_device *ts_device; + ts_device = goodix_core_data->ts_dev; + + ret = ts_device->hw_ops->read_trans(ts_device, 0x3100, &read_val, 1); + if (!ret) { + ts_info("i2c test SUCCESS"); + } else { + ts_err("i2c test FAILED"); + return GTP_RESULT_FAIL; + } + + return GTP_RESULT_PASS; +} + +static ssize_t gtp_selftest_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + char tmp[5] = { 0 }; + int cnt; + + if (*pos != 0 || !goodix_core_data) + return 0; + cnt = snprintf(tmp, sizeof(goodix_core_data->result_type), "%d\n", + goodix_core_data->result_type); + if (copy_to_user(buf, tmp, strlen(tmp))) { + return -EFAULT; + } + *pos += cnt; + return cnt; +} + +static int gtp_short_open_test(void) +{ + int ret = 0; + + ret = goodix_tools_register(); + + if (ret) { + ts_err("tp_test prepare goodix_tools_register failed"); + return GTP_RESULT_INVALID; + } + ts_info("test start!"); + ret = test_process((void *)(&goodix_core_data->pdev->dev)); + + if (ret == 0) { + ts_err("test PASS!"); + return GTP_RESULT_PASS; + } else { + ts_err("test FAILED. result:%x", ret); + return GTP_RESULT_FAIL; + } + goodix_tools_unregister(); + + ts_info("test finish!"); + return GTP_RESULT_FAIL; +} +static ssize_t gtp_selftest_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + int retval = 0; + char tmp[6]; + + if (copy_from_user(tmp, buf, count)) { + retval = -EFAULT; + goto out; + } + if (!goodix_core_data) + return GTP_RESULT_INVALID; + + if (!strncmp("short", tmp, 5) || !strncmp("open", tmp, 4)) { + retval = gtp_short_open_test(); + } else if (!strncmp("i2c", tmp, 3)) + retval = gtp_i2c_test(); + + goodix_core_data->result_type = retval; +out: + if (retval >= 0) + retval = count; + + return retval; +} + +static const struct file_operations gtp_selftest_ops = { + .read = gtp_selftest_read, + .write = gtp_selftest_write, +}; + +static void gtp_power_supply_work(struct work_struct *work) +{ + struct goodix_ts_core *core_data = + container_of(work, struct goodix_ts_core, power_supply_work); + struct goodix_ts_device *dev = core_data->ts_dev; + u8 state_data[3]; + int is_usb_exist = 0; + + if (!atomic_read(&core_data->suspend_stat) && + !goodix_modules.core_exit) { + is_usb_exist = !!power_supply_is_system_supplied(); + if (is_usb_exist != core_data->is_usb_exist || + core_data->is_usb_exist < 0) { + core_data->is_usb_exist = is_usb_exist; + ts_info("Power_supply_event:%d", is_usb_exist); + if (is_usb_exist) { + state_data[0] = IS_USB_EXIST; + state_data[1] = 0x00; + state_data[2] = 0xFA; + goodix_i2c_write(dev, 0x6F68, state_data, 3); + ts_info("USB is exist"); + } else { + state_data[0] = IS_USB_NOT_EXIST; + state_data[1] = 0x00; + state_data[2] = 0xF9; + goodix_i2c_write(dev, 0x6F68, state_data, 3); + ts_info("USB is not exist"); + } + } + } +} +static int gtp_power_supply_event(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct goodix_ts_core *ts_core = + container_of(nb, struct goodix_ts_core, power_supply_notifier); + + queue_work(ts_core->event_wq, &ts_core->power_supply_work); + + return 0; +} + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +static struct xiaomi_touch_interface xiaomi_touch_interfaces; + +static int gtp_set_cur_value(int gtp_mode, int gtp_value) +{ + u8 state_data[3] = { 0 }; + u8 goodix_game_value = 0; + u8 temp_value = 0; + int ret = 0; + int i = 0; + + struct goodix_ts_device *dev = goodix_core_data->ts_dev; + /* + if (gtp_mode == Touch_Fod_Enable && goodix_core_data && gtp_value >= 0) { + ts_info("set fod status"); + goodix_core_data->fod_status = gtp_value; + goodix_core_data->gesture_enabled = goodix_core_data->double_wakeup | + goodix_core_data->fod_status | goodix_core_data->aod_status; + goodix_check_gesture_stat(!!goodix_core_data->fod_status); + return 0; + } + if (gtp_mode == Touch_Aod_Enable && goodix_core_data && gtp_value >= 0) { + ts_info("set aod status"); + goodix_core_data->aod_status = gtp_value; + goodix_core_data->gesture_enabled = goodix_core_data->double_wakeup | + goodix_core_data->fod_status | goodix_core_data->aod_status; + goodix_check_gesture_stat(!!goodix_core_data->aod_status); + return 0; + } +*/ + if (gtp_mode >= Touch_Mode_NUM && gtp_mode < 0) { + ts_err("gtp mode is error:%d", gtp_mode); + return -EINVAL; + } else if (xiaomi_touch_interfaces.touch_mode[gtp_mode][SET_CUR_VALUE] > + xiaomi_touch_interfaces.touch_mode[gtp_mode][GET_MAX_VALUE]) { + xiaomi_touch_interfaces.touch_mode[gtp_mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[gtp_mode][GET_MAX_VALUE]; + + } else if (xiaomi_touch_interfaces.touch_mode[gtp_mode][SET_CUR_VALUE] < + xiaomi_touch_interfaces.touch_mode[gtp_mode][GET_MIN_VALUE]) { + xiaomi_touch_interfaces.touch_mode[gtp_mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[gtp_mode][GET_MIN_VALUE]; + } + + xiaomi_touch_interfaces.touch_mode[gtp_mode][SET_CUR_VALUE] = gtp_value; + + if (gtp_mode == Touch_Game_Mode && gtp_value == 0) { + ts_info("exit touch game mode"); + state_data[0] = GTP_EXIT_GAME_CMD; + state_data[1] = 0x00; + state_data[2] = 0xF1; + ret = goodix_i2c_write(dev, GTP_GAME_CMD_ADD, state_data, 3); + if (ret < 0) { + ts_err("exit game mode fail"); + } + goodix_game_value = 0; + return ret; + } + + for (i = 0; i < Touch_Mode_NUM; i++) { + switch (i) { + case Touch_Game_Mode: + break; + case Touch_Active_MODE: + break; + case Touch_UP_THRESHOLD: + temp_value = xiaomi_touch_interfaces + .touch_mode[Touch_UP_THRESHOLD] + [SET_CUR_VALUE]; + goodix_game_value &= 0xFC; + goodix_game_value |= temp_value; + break; + case Touch_Tolerance: + temp_value = xiaomi_touch_interfaces + .touch_mode[Touch_Tolerance] + [SET_CUR_VALUE]; + temp_value = 3 - temp_value; + goodix_game_value &= 0xF3; + goodix_game_value |= (temp_value << 2); + break; + case Touch_Edge_Filter: + temp_value = xiaomi_touch_interfaces + .touch_mode[Touch_Edge_Filter] + [SET_CUR_VALUE]; + goodix_game_value &= 0xCF; + goodix_game_value |= (temp_value << 4); + break; + case Touch_Panel_Orientation: + /* 0,1,2,3 = 0, 90, 180,270 */ + temp_value = + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation] + [SET_CUR_VALUE]; + if (temp_value == 3) + temp_value = 2; + else if (temp_value == 2) + temp_value = 3; + goodix_game_value &= 0x3F; + goodix_game_value |= (temp_value << 6); + break; + default: + /* Don't support */ + break; + }; + } + ts_info("mode:%d, value:%d, write value:0x%x", gtp_mode, gtp_value, + goodix_game_value); + + xiaomi_touch_interfaces.touch_mode[gtp_mode][GET_CUR_VALUE] = + xiaomi_touch_interfaces.touch_mode[gtp_mode][SET_CUR_VALUE]; + + if (xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][SET_CUR_VALUE]) { + state_data[0] = GTP_GAME_CMD; + state_data[1] = goodix_game_value; + state_data[2] = 0xFF & (0 - state_data[0] - state_data[1]); + + ret = goodix_i2c_write(dev, GTP_GAME_CMD_ADD, state_data, 3); + + if (ret < 0) { + ts_err("change game mode fail"); + } + } + return ret; +} + +static int gtp_get_mode_value(int mode, int value_type) +{ + int value = -1; + + if (mode < Touch_Mode_NUM && mode >= 0) + value = xiaomi_touch_interfaces.touch_mode[mode][value_type]; + else + ts_err("don't support"); + + return value; +} + +static int gtp_get_mode_all(int mode, int *value) +{ + if (mode < Touch_Mode_NUM && mode >= 0) { + value[0] = + xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE]; + value[1] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + value[2] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; + value[3] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; + } else { + ts_err("don't support"); + } + ts_info("mode:%d, value:%d:%d:%d:%d", mode, value[0], value[1], + value[2], value[3]); + + return 0; +} + +static int gtp_reset_mode(int mode) +{ + int i = 0; + + if (mode < Touch_Mode_NUM && mode > 0) { + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + gtp_set_cur_value( + mode, + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE]); + } else if (mode == 0) { + for (i = 0; i < Touch_Mode_NUM; i++) { + xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[i][GET_DEF_VALUE]; + gtp_set_cur_value( + mode, xiaomi_touch_interfaces + .touch_mode[mode][SET_CUR_VALUE]); + } + } else { + ts_err("don't support"); + } + + ts_info("mode:%d", mode); + + return 0; +} + +static void gtp_init_touchmode_data(void) +{ + int i; + + /* Touch Game Mode Switch */ + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MAX_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_CUR_VALUE] = 0; + + /* Acitve Mode */ + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MAX_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_DEF_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_CUR_VALUE] = + 0; + + /* finger hysteresis */ + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MAX_VALUE] = + 3; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_DEF_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_CUR_VALUE] = + 0; + + /* Tolerance */ + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MAX_VALUE] = 3; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_CUR_VALUE] = 0; + + /* edge filter */ + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MAX_VALUE] = + 3; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MIN_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_DEF_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = + 1; + + /* Orientation */ + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MAX_VALUE] = 3; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = 0; + + for (i = 0; i < Touch_Mode_NUM; i++) { + ts_info("mode:%d, set cur:%d, get cur:%d, def:%d min:%d max:%d\n", + i, xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MIN_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MAX_VALUE]); + } + + return; +} +#endif + +/** + * goodix_ts_probe - called by kernel when a Goodix touch + * platform driver is added. + */ +static int goodix_ts_probe(struct platform_device *pdev) +{ + struct goodix_ts_core *core_data = NULL; + struct goodix_ts_device *ts_device; + struct i2c_client *client = NULL; + int r; + u8 read_val = 0; + + ts_err("enter::%s\n", __func__); + ts_device = pdev->dev.platform_data; + if (!ts_device || !ts_device->hw_ops || !ts_device->board_data) { + ts_err("Invalid touch device"); + return -ENODEV; + } + + core_data = devm_kzalloc(&pdev->dev, sizeof(struct goodix_ts_core), + GFP_KERNEL); + if (!core_data) { + ts_err("Failed to allocate memory for core data"); + return -ENOMEM; + } + goodix_core_data = core_data; + + /* touch core layer is a platform driver */ + core_data->pdev = pdev; + core_data->ts_dev = ts_device; + platform_set_drvdata(pdev, core_data); + + client = to_i2c_client(ts_device->dev); + i2c_set_clientdata(client, core_data); + core_data->cfg_group_parsed = false; + + r = goodix_ts_power_init(core_data); + if (r < 0) { + pr_err("goodix_ts_power_init fail \n"); + goto out; + } + + r = goodix_ts_power_on(core_data); + if (r < 0) { + pr_err("goodix_ts_power_on fail \n"); + goto out; + } + +#ifdef CONFIG_PINCTRL + /* Pinctrl handle is optional. */ + r = goodix_ts_pinctrl_init(core_data); + if (!r && core_data->pinctrl) { + r = pinctrl_select_state(core_data->pinctrl, + core_data->pin_sta_active); + if (r < 0) + ts_err("Failed to select active pinstate, r:%d", r); + } +#endif + + /* get GPIO resource */ + r = goodix_ts_gpio_setup(core_data); + if (r < 0) { + pr_err("goodix_ts_gpio_setup fail \n"); + goto out; + } + /*init lock to protect suspend_stat*/ + mutex_init(&core_data->work_stat); + mutex_init(&ts_device->report_mutex); + /*init complete and pm status*/ + core_data->tp_already_suspend = false; + init_completion(&core_data->pm_resume_completion); + + /*create sysfs files*/ + goodix_ts_sysfs_init(core_data); + + r = ts_device->hw_ops->reset(ts_device); + if (r < 0) { + pr_err("goodix_hw_ops->reset fail \n"); + goto out; + } + + core_data->event_wq = + alloc_workqueue("gdt-event-queue", + WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!core_data->event_wq) { + ts_err("goodix cannot create work thread"); + r = -ENOMEM; + goto out; + } + + INIT_WORK(&core_data->resume_work, goodix_ts_resume_work); + INIT_WORK(&core_data->suspend_work, goodix_ts_suspend_work); + INIT_WORK(&core_data->sleep_work, goodix_ts_sleep_work); + device_init_wakeup(&pdev->dev, 1); + + core_data->is_usb_exist = -1; + /*i2c test*/ + r = ts_device->hw_ops->read_trans(ts_device, 0x3100, &read_val, 1); + if (!r) + ts_info("i2c test SUCCESS"); + else { + ts_err("i2c test FAILED"); + goto out; + } + + core_data->tp_lockdown_info_proc = proc_create( + "tp_lockdown_info", 0664, NULL, &goodix_lockdown_info_ops); + + /*unified protocl + * start a thread to parse cfg_bin and init IC*/ + r = goodix_start_cfg_bin(core_data); + if (!r) { + ts_info("***start cfg_bin_proc SUCCESS"); + } else { + ts_err("***start cfg_bin_proc FAILED"); + goto out; + } + + core_data->power_supply_notifier.notifier_call = gtp_power_supply_event; + power_supply_reg_notifier(&core_data->power_supply_notifier); + INIT_WORK(&core_data->power_supply_work, gtp_power_supply_work); + + core_data->bl_notifier.notifier_call = goodix_bl_state_chg_callback; + if (backlight_register_notifier(&core_data->bl_notifier) < 0) { + ts_err("ERROR:register bl_notifier failed\n"); + goto out; + } + core_data->attrs.attrs = goodix_attr_group; + r = sysfs_create_group(&client->dev.kobj, &core_data->attrs); + if (r) { + ts_err("ERROR: Cannot create sysfs structure!\n"); + r = -ENODEV; + goto out; + } + + if (core_data->gtp_tp_class == NULL) +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + core_data->gtp_tp_class = get_xiaomi_touch_class(); + if (core_data->gtp_tp_class == NULL) + ts_err("ERROR: gtp_tp_class is NULL!\n"); +#else + core_data->gtp_tp_class = class_create(THIS_MODULE, "touch"); +#endif + core_data->gtp_touch_dev = device_create(core_data->gtp_tp_class, NULL, + 0x5d, core_data, "tp_dev"); + if (IS_ERR(core_data->gtp_touch_dev)) { + ts_err("ERROR: Cannot create device for the sysfs!\n"); + goto out; + } + dev_set_drvdata(core_data->gtp_touch_dev, core_data); + + if (sysfs_create_file(&core_data->gtp_touch_dev->kobj, + &dev_attr_touch_suspend_notify.attr)) { + ts_err("Failed to create sysfs group!\n"); + goto out; + } + + if (sysfs_create_file(&core_data->gtp_touch_dev->kobj, + &dev_attr_fod_status.attr)) { + ts_err("Failed to create fod_status sysfs group!\n"); + goto out; + } + + if (sysfs_create_file(&core_data->gtp_touch_dev->kobj, + &dev_attr_fod_test.attr)) { + ts_err("Failed to create fod_test sysfs group!"); + goto out; + } + + core_data->tp_selftest_proc = + proc_create("tp_selftest", 0644, NULL, >p_selftest_ops); + +#ifdef CONFIG_GOODIX_HWINFO + core_data->dbclick_count = 0; +#endif + + /*core_data->fod_status = -1;*/ + //wake_lock_init(&core_data->tp_wakelock, WAKE_LOCK_SUSPEND, "touch_locker"); +#ifdef CONFIG_TOUCHSCREEN_GOODIX_DEBUG_FS + core_data->debugfs = debugfs_create_dir("tp_debug", NULL); + if (core_data->debugfs) { + debugfs_create_file("switch_state", 0660, core_data->debugfs, + core_data, &tpdbg_operations); + } +#endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + memset(&xiaomi_touch_interfaces, 0x00, + sizeof(struct xiaomi_touch_interface)); + xiaomi_touch_interfaces.getModeValue = gtp_get_mode_value; + xiaomi_touch_interfaces.setModeValue = gtp_set_cur_value; + xiaomi_touch_interfaces.resetMode = gtp_reset_mode; + xiaomi_touch_interfaces.getModeAll = gtp_get_mode_all; + xiaomitouch_register_modedata(&xiaomi_touch_interfaces); + gtp_init_touchmode_data(); +#endif + +out: + backlight_unregister_notifier(&core_data->bl_notifier); + ts_info("goodix_ts_probe OUT, r:%d", r); + return r; +} + +static int goodix_ts_remove(struct platform_device *pdev) +{ + struct goodix_ts_core *core_data = platform_get_drvdata(pdev); +#ifdef CONFIG_DRM + drm_unregister_client(&core_data->fb_notifier); +#endif + //wake_lock_destroy(&core_data->tp_wakelock); + power_supply_unreg_notifier(&core_data->power_supply_notifier); + goodix_ts_power_off(core_data); + goodix_debugfs_exit(); + goodix_ts_sysfs_exit(core_data); + return 0; +} + +#ifdef CONFIG_PM +static const struct dev_pm_ops dev_pm_ops = { + .suspend = goodix_ts_pm_suspend, + .resume = goodix_ts_pm_resume, +}; +#endif + +static const struct platform_device_id ts_core_ids[] = { + { .name = GOODIX_CORE_DRIVER_NAME }, + {} +}; +MODULE_DEVICE_TABLE(platform, ts_core_ids); + +static struct platform_driver goodix_ts_driver = { + .driver = { + .name = GOODIX_CORE_DRIVER_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &dev_pm_ops, +#endif + }, + .probe = goodix_ts_probe, + .remove = goodix_ts_remove, + .id_table = ts_core_ids, +}; + +static int __init goodix_ts_core_init(void) +{ + ts_info("goodix9886 Core layer init"); + if (!goodix_modules.initilized) { + goodix_modules.initilized = true; + goodix_modules.core_exit = true; + INIT_LIST_HEAD(&goodix_modules.head); + mutex_init(&goodix_modules.mutex); + init_completion(&goodix_modules.core_comp); + } + goodix_debugfs_init(); + return platform_driver_register(&goodix_ts_driver); +} + +static void __exit goodix_ts_core_exit(void) +{ + ts_info("Core layer exit"); + platform_driver_unregister(&goodix_ts_driver); + return; +} + +module_init(goodix_ts_core_init); +module_exit(goodix_ts_core_exit); + +MODULE_DESCRIPTION("Goodix Touchscreen Core Module"); +MODULE_AUTHOR("Goodix, Inc."); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h new file mode 100644 index 000000000000..c6033562578a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h @@ -0,0 +1,788 @@ +/* + * Goodix Touchscreen Driver + * Core layer of touchdriver architecture. + * + * Copyright (C) 2015 - 2016 Goodix, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: Yulong Cai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be a reference + * to you, when you are integrating the GOODiX's CTP IC into your system, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ +#ifndef _GOODIX_TS_CORE_H_ +#define _GOODIX_TS_CORE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_OF +#include +#include +#endif +#include +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif +#ifdef CONFIG_DRM +#include +#include +#include +#endif + +/* macros definition */ +#define GOODIX_CORE_DRIVER_NAME "goodix_ts" +#define GOODIX_DRIVER_VERSION "v1.2.0.1" +#define GOODIX_BUS_RETRY_TIMES 3 +#define GOODIX_MAX_TOUCH 10 +#define GOODIX_MAX_PEN 1 +#define GOODIX_MAX_KEY 3 +#define GOODIX_PEN_MAX_KEY 2 +#define GOODIX_CFG_MAX_SIZE 1024 +#define GOODIX_ESD_TICK_WRITE_DATA 0xAA +#define GOODIX_PID_MAX_LEN 8 +#define GOODIX_VID_MAX_LEN 8 +#define GOODIX_ESD_CHECK_INTERVAL 5 + +#define GOODIX_DEFAULT_CFG_NAME "goodix_config.cfg" + +#define IC_TYPE_NONE 0 +#define IC_TYPE_NORMANDY 1 +#define IC_TYPE_NANJING 2 + +#define GOODIX_TOUCH_EVENT 0x80 +#define GOODIX_REQUEST_EVENT 0x40 +#define GOODIX_GESTURE_EVENT 0x20 +#define GOODIX_HOTKNOT_EVENT 0x10 +#define GOODIX_LOCKDOWN_SIZE 8 + +#define CENTER_X 540 +#define CENTER_Y 2030 + +#define KEY_GOTO 0x162 +#define BTN_INFO 0x152 + +#define GTP_RESULT_INVALID 0 +#define GTP_RESULT_PASS 2 +#define GTP_RESULT_FAIL 1 + +#define GTP_GAME_CMD_ADD 0x6F68 +#define GTP_GAME_CMD 0x0E +#define GTP_EXIT_GAME_CMD 0x0F + +#define CONFIG_TOUCHSCREEN_GOODIX_DEBUG_FS + +#define CONFIG_GOODIX_HWINFO + +/* + * struct goodix_module - external modules container + * @head: external modules list + * @initilized: whether this struct is initilized + * @mutex: mutex lock + * @count: current number of registered external module + * @wq: workqueue to do register work + * @core_exit: if goodix touch core exit, then no + * registration is allowed. + * @core_data: core_data pointer + */ +struct goodix_module { + struct list_head head; + bool initilized; + struct mutex mutex; + unsigned int count; + struct workqueue_struct *wq; + bool core_exit; + struct completion core_comp; + struct goodix_ts_core *core_data; +}; + +/* + * struct goodix_ts_board_data - board data + * @avdd_name: name of analoy regulator + * @reset_gpio: reset gpio number + * @irq_gpio: interrupt gpio number + * @irq_flag: irq trigger type + * @power_on_delay_us: power on delay time (us) + * @power_off_delay_us: power off delay time (us) + * @swap_axis: whether swaw x y axis + * @panel_max_id: max supported fingers + * @panel_max_x/y/w/p: resolution and size + * @panel_max_key: max supported keys + * @pannel_key_map: key map + * @fw_name: name of the firmware image + */ +struct goodix_ts_board_data { + const char *avdd_name; + const char *vddio_name; + unsigned int avdd_load; + unsigned int reset_gpio; + unsigned int irq_gpio; + unsigned int vdd_gpio; + unsigned int avdd_gpio; + int irq; + unsigned int irq_flags; + + unsigned int power_on_delay_us; + unsigned int power_off_delay_us; + + unsigned int swap_axis; + unsigned int panel_max_id; /*max touch id*/ + unsigned int panel_max_x; + unsigned int panel_max_y; + unsigned int panel_max_w; /*major and minor*/ + unsigned int panel_max_p; /*pressure*/ + unsigned int panel_max_area; /*pressure*/ + unsigned int panel_max_overlapping_area; /*pressure*/ + unsigned int panel_max_key; + unsigned int panel_key_map[GOODIX_MAX_KEY + GOODIX_PEN_MAX_KEY]; + /*add by lishuai*/ + unsigned int x2x; + unsigned int y2y; + bool pen_enable; + unsigned int tp_key_num; + /*add end*/ + + const char *fw_name; + const char *limit_name; + const char *cfg_bin_name; + bool esd_default_on; +}; + +/* + * struct goodix_ts_config - chip config data + * @initialized: whether intialized + * @name: name of this config + * @lock: mutex + * @reg_base: register base of config data + * @length: bytes of the config + * @delay: delay time after sending config + * @data: config data buffer + */ +struct goodix_ts_config { + bool initialized; + char name[24]; + struct mutex lock; + unsigned int reg_base; + unsigned int length; + unsigned int delay; /*ms*/ + unsigned char data[GOODIX_CFG_MAX_SIZE]; +}; + +/* + * struct goodix_ts_cmd - command package + * @initialized: whether initialized + * @cmd_reg: command register + * @length: command length in bytes + * @cmds: command data + */ +#pragma pack(4) +struct goodix_ts_cmd { + u32 initialized; + u32 cmd_reg; + u32 length; + u8 cmds[3]; +}; +#pragma pack() + +/* interrupt event type */ +enum ts_event_type { + EVENT_INVALID, + EVENT_TOUCH, + EVENT_REQUEST, +}; + +/* requset event type */ +enum ts_request_type { + REQUEST_INVALID, + REQUEST_CONFIG, + REQUEST_BAKREF, + REQUEST_RESET, + REQUEST_MAINCLK, +}; + +/* notifier event */ + +enum ts_notify_event { + NOTIFY_FWUPDATE_START, + NOTIFY_FWUPDATE_END, + NOTIFY_SUSPEND, + NOTIFY_RESUME, + NOTIFY_ESD_OFF, + NOTIFY_ESD_ON, +}; + +/* suspend status*/ +enum tp_suspend_stat { + TP_NO_SUSPEND, + TP_GESTURE_DBCLK, + TP_GESTURE_FOD, + TP_GESTURE_DBCLK_FOD, + TP_SLEEP, +}; + +/* coordinate package */ +struct goodix_ts_coords { + int id; + unsigned int x, y, w, p, area, overlapping_area; +}; + +/* touch event data */ +struct goodix_touch_data { + /* finger */ + int touch_num; + struct goodix_ts_coords coords[GOODIX_MAX_TOUCH]; + /* key */ + u8 key_value; + bool have_key; + /*pen*/ + struct goodix_ts_coords pen_coords[GOODIX_MAX_PEN]; + bool pen_down; +}; + +/* request event data */ +struct goodix_request_data { + enum ts_request_type request_type; +}; + +/* + * struct goodix_ts_event - touch event struct + * @event_type: touch event type, touch data or + * request event + * @event_data: event data + */ +struct goodix_ts_event { + enum ts_event_type event_type; + union { + struct goodix_touch_data touch_data; + struct goodix_request_data request_data; + } event_data; +}; + +/* + * struct goodix_ts_version - firmware version + * @valid: whether these infomation is valid + * @pid: product id string + * @vid: firmware version code + * @cid: customer id code + * @sensor_id: sendor id + */ +struct goodix_ts_version { + bool valid; + char pid[GOODIX_PID_MAX_LEN]; + char vid[GOODIX_VID_MAX_LEN]; + u8 cid; + u8 sensor_id; +}; + +struct goodix_ts_regs { + u16 cfg_send_flag; + u16 version_base; + u8 version_len; + u16 pid; + u8 pid_len; + u16 vid; + u8 vid_len; + u16 sensor_id; + u8 sensor_id_mask; + u16 fw_mask; + u16 fw_status; + u16 cfg_addr; + u16 esd; + u16 command; + u16 coor; + u16 gesture; + u16 fw_request; + u16 proximity; +}; + +/* + * struct goodix_ts_device - ts device data + * @name: device name + * @version: reserved + * @bus_type: i2c or spi + * @board_data: board data obtained from dts + * @normal_cfg: normal config data + * @highsense_cfg: high sense config data + * @hw_ops: hardware operations + * @chip_version: firmware version infomation + * @sleep_cmd: sleep commang + * @gesture_cmd: gesture command + * @dev: device pointer,may be a i2c or spi device + * @of_node: device node + */ +struct goodix_ts_device { + char *name; + int version; + int bus_type; + u8 ic_type; + struct goodix_ts_regs reg; + int doze_mode_set_count; + struct mutex doze_mode_lock; + struct mutex report_mutex; + struct goodix_ts_board_data *board_data; + struct goodix_ts_config *normal_cfg; + struct goodix_ts_config *highsense_cfg; + const struct goodix_ts_hw_ops *hw_ops; + struct goodix_ts_version chip_version; + struct device *dev; +}; + +/* + * struct goodix_ts_hw_ops - hardware opeartions + * @init: hardware initialization + * @reset: hardware reset + * @read: read data from touch device + * @write: write data to touch device + * @send_cmd: send command to touch device + * @send_config: send configuration data + * @read_version: read firmware version + * @event_handler: touch event handler + * @suspend: put touch device into low power mode + * @resume: put touch device into working mode + */ +struct goodix_ts_hw_ops { + int (*init)(struct goodix_ts_device *dev); + int (*reset)(struct goodix_ts_device *dev); + int (*read)(struct goodix_ts_device *dev, unsigned int addr, + unsigned char *data, unsigned int len); + int (*write)(struct goodix_ts_device *dev, unsigned int addr, + unsigned char *data, unsigned int len); + int (*read_trans)(struct goodix_ts_device *dev, unsigned int addr, + unsigned char *data, unsigned int len); + int (*write_trans)(struct goodix_ts_device *dev, unsigned int addr, + unsigned char *data, unsigned int len); + int (*send_cmd)(struct goodix_ts_device *dev, + struct goodix_ts_cmd *cmd); + int (*send_config)(struct goodix_ts_device *dev, + struct goodix_ts_config *config); + int (*read_config)(struct goodix_ts_device *dev, u8 *config_data, + u32 config_len); + int (*read_version)(struct goodix_ts_device *dev, + struct goodix_ts_version *version); + int (*event_handler)(struct goodix_ts_device *dev, + struct goodix_ts_event *ts_event); + int (*check_hw)(struct goodix_ts_device *dev); + int (*suspend)(struct goodix_ts_device *dev); + int (*resume)(struct goodix_ts_device *dev); +}; + +/* + * struct goodix_ts_esd - esd protector structure + * @esd_work: esd delayed work + * @esd_on: true - turn on esd protection, false - turn + * off esd protection + * @esd_mutex: protect @esd_on flag + */ +struct goodix_ts_esd { + struct delayed_work esd_work; + struct mutex esd_mutex; + struct notifier_block esd_notifier; + struct goodix_ts_core *ts_core; + bool esd_on; +}; + +/* + * struct godix_ts_core - core layer data struct + * @pdev: core layer platform device + * @ts_dev: hardware layer touch device + * @input_dev: input device + * @avdd: analog regulator + * @pinctrl: pinctrl handler + * @pin_sta_active: active/normal pin state + * @pin_sta_suspend: suspend/sleep pin state + * @ts_event: touch event data struct + * @power_on: power on/off flag + * @irq: irq number + * @irq_enabled: irq enabled/disabled flag + * @suspended: suspend/resume flag + * @hw_err: indicate that hw_ops->init() failed + * @ts_notifier: generic notifier + * @ts_esd: esd protector structure + * @fb_notifier: framebuffer notifier + * @early_suspend: early suspend + */ +struct goodix_ts_core { + struct platform_device *pdev; + struct goodix_ts_device *ts_dev; + struct input_dev *input_dev; + + struct regulator *avdd; + struct regulator *vddio; +#ifdef CONFIG_PINCTRL + struct pinctrl *pinctrl; + struct pinctrl_state *pin_sta_active; + struct pinctrl_state *pin_sta_suspend; +#endif + struct goodix_ts_event ts_event; + unsigned long touch_id; + unsigned long sleep_finger; + unsigned long event_status; + unsigned int avdd_load; + unsigned char lockdown_info[GOODIX_LOCKDOWN_SIZE]; + + int power_on; + int irq; + size_t irq_trig_cnt; + + atomic_t irq_enabled; + atomic_t suspended; + + bool cfg_group_parsed; + struct attribute_group attrs; + + struct notifier_block ts_notifier; + struct goodix_ts_esd ts_esd; + + struct proc_dir_entry *tp_selftest_proc; + struct proc_dir_entry *tp_data_dump_proc; + struct proc_dir_entry *tp_fw_version_proc; + struct proc_dir_entry *tp_lockdown_info_proc; +#ifdef CONFIG_DRM + struct notifier_block fb_notifier; +#elif defined(CONFIG_HAS_EARLYSUSPEND) + struct early_suspend early_suspend; +#endif + struct notifier_block power_supply_notifier; + struct notifier_block bl_notifier; + struct workqueue_struct *event_wq; + struct work_struct suspend_work; + struct work_struct resume_work; + struct work_struct power_supply_work; + atomic_t suspend_stat; + int is_usb_exist; + int gesture_enabled; + int fod_status; + int aod_status; + int fod_pressed; + int fod_test; + int double_wakeup; + int result_type; + struct class *gtp_tp_class; + struct device *gtp_touch_dev; + char *current_clicknum_file; + struct mutex work_stat; + struct work_struct sleep_work; + bool tp_already_suspend; + bool palm_sensor_switch; + struct completion pm_resume_completion; +#ifdef CONFIG_TOUCHSCREEN_GOODIX_DEBUG_FS + struct dentry *debugfs; +#endif +#ifdef CONFIG_GOODIX_HWINFO + int dbclick_count; +#endif +}; + +struct goodix_mode_switch { + struct goodix_ts_core *info; + unsigned char mode; + struct work_struct switch_mode_work; +}; + +/* external module structures */ +enum goodix_ext_priority { + EXTMOD_PRIO_RESERVED = 0, + EXTMOD_PRIO_FWUPDATE, + EXTMOD_PRIO_GESTURE, + EXTMOD_PRIO_HOTKNOT, + EXTMOD_PRIO_DBGTOOL, + EXTMOD_PRIO_DEFAULT, +}; + +struct goodix_ext_module; +/* external module's operations callback */ +struct goodix_ext_module_funcs { + int (*init)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + int (*exit)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + + int (*before_reset)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + int (*after_reset)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + + int (*before_suspend)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + int (*after_suspend)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + + int (*before_resume)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + int (*after_resume)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); + + int (*irq_event)(struct goodix_ts_core *core_data, + struct goodix_ext_module *module); +}; + +/* + * struct goodix_ext_module - external module struct + * @list: list used to link into modules manager + * @name: name of external module + * @priority: module priority vlaue, zero is invalid + * @funcs: operations callback + * @priv_data: private data region + * @kobj: kobject + * @work: used to queue one work to do registration + */ +struct goodix_ext_module { + struct list_head list; + char *name; + enum goodix_ext_priority priority; + const struct goodix_ext_module_funcs *funcs; + void *priv_data; + struct kobject kobj; + struct work_struct work; +}; + +/* + * struct goodix_ext_attribute - exteranl attribute struct + * @attr: attribute + * @show: show interface of external attribute + * @store: store interface of external attribute + */ +struct goodix_ext_attribute { + struct attribute attr; + ssize_t (*show)(struct goodix_ext_module *, char *); + ssize_t (*store)(struct goodix_ext_module *, const char *, size_t); +}; + +/* external attrs helper macro */ +#define __EXTMOD_ATTR(_name, _mode, _show, _store) \ + { \ + .attr = { .name = __stringify(_name), .mode = _mode }, \ + .show = _show, \ + .store = _store, \ + } + +/* external attrs helper macro, used to define external attrs */ +#define DEFINE_EXTMOD_ATTR(_name, _mode, _show, _store) \ + static struct goodix_ext_attribute ext_attr_##_name = \ + __EXTMOD_ATTR(_name, _mode, _show, _store); + +/* + * get board data pointer + */ +static inline struct goodix_ts_board_data * +board_data(struct goodix_ts_core *core) +{ + return core->ts_dev->board_data; +} + +/* + * get touch device pointer + */ +static inline struct goodix_ts_device *ts_device(struct goodix_ts_core *core) +{ + return core->ts_dev; +} + +/* + * get touch hardware operations pointer + */ +static inline const struct goodix_ts_hw_ops * +ts_hw_ops(struct goodix_ts_core *core) +{ + return core->ts_dev->hw_ops; +} + +/* + * checksum helper functions + * checksum can be u8/le16/be16/le32/be32 format + * NOTE: the caller shoule be responsible for the + * legality of @data and @size parameters, so be + * careful when call these functions. + */ +static inline u8 checksum_u8(u8 *data, u32 size) +{ + u8 checksum = 0; + u32 i; + for (i = 0; i < size; i++) + checksum += data[i]; + return checksum; +} + +static inline u16 checksum_le16(u8 *data, u32 size) +{ + u16 checksum = 0; + u32 i; + + for (i = 0; i < size; i += 2) + checksum += le16_to_cpup((__le16 *)(data + i)); + return checksum; +} + +static inline u16 checksum_be16(u8 *data, u32 size) +{ + u16 checksum = 0; + u32 i; + for (i = 0; i < size; i += 2) + checksum += be16_to_cpup((__be16 *)(data + i)); + return checksum; +} + +static inline u32 checksum_le32(u8 *data, u32 size) +{ + u32 checksum = 0; + u32 i; + for (i = 0; i < size; i += 4) + checksum += le32_to_cpup((__le32 *)(data + i)); + return checksum; +} + +static inline u32 checksum_be32(u8 *data, u32 size) +{ + u32 checksum = 0; + u32 i; + for (i = 0; i < size; i += 4) + checksum += be32_to_cpup((__be32 *)(data + i)); + return checksum; +} + +/* + * define event action + * EVT_xxx macros are used in opeartions callback + * defined in @goodix_ext_module_funcs to control + * the behaviors of event such as suspend/resume/irq_event. + * generally there are two types of behaviors: + * 1. you want the flow of this event be canceled, + * in this condition, you should return EVT_CANCEL_XXX in + * the operations callback. + * e.g. the firmware update module is updating + * the firmware, you want to cancel suspend flow, + * so you need to return EVT_CANCEL_SUSPEND in + * suspend callback function. + * 2. you want the flow of this event continue, in + * this condition, you should return EVT_HANDLED in + * the callback function. + * */ +#define EVT_HANDLED 0 +#define EVT_CONTINUE 0 +#define EVT_CANCEL 1 +#define EVT_CANCEL_IRQEVT 1 +#define EVT_CANCEL_SUSPEND 1 +#define EVT_CANCEL_RESUME 1 +#define EVT_CANCEL_RESET 1 + +/* + * errno define + * Note: + * 1. bus read/write functions defined in hardware + * layer code(e.g. goodix_xxx_i2c.c) *must* return + * -EBUS if failed to transfer data on bus. + */ +#define EBUS 1000 +#define ETIMEOUT 1001 +#define ECHKSUM 1002 +#define EMEMCMP 1003 + +#define CONFIG_GOODIX_DEBUG +/* log macro */ +#define ts_info(fmt, arg...) \ + pr_info("[GTP9886-INF][%s:%d] " fmt "\n", __func__, __LINE__, ##arg) +#define ts_err(fmt, arg...) \ + pr_err("[GTP9886-ERR][%s:%d] " fmt "\n", __func__, __LINE__, ##arg) +#define boot_log(fmt, arg...) g_info(fmt, ##arg) +#ifdef CONFIG_GOODIX_DEBUG +#define ts_debug(fmt, arg...) \ + pr_info("[GTP9886-DBG][%s:%d] " fmt "\n", __func__, __LINE__, ##arg) +#else +#define ts_debug(fmt, arg...) \ + do { \ + } while (0) +#endif + +/** + * goodix_register_ext_module - interface for external module + * to register into touch core modules structure + * + * @module: pointer to external module to be register + * return: 0 ok, <0 failed + */ +int goodix_register_ext_module(struct goodix_ext_module *module); + +/** + * goodix_unregister_ext_module - interface for external module + * to unregister external modules + * + * @module: pointer to external module + * return: 0 ok, <0 failed + */ +int goodix_unregister_ext_module(struct goodix_ext_module *module); + +/** + * goodix_ts_irq_enable - Enable/Disable a irq + + * @core_data: pointer to touch core data + * enable: enable or disable irq + * return: 0 ok, <0 failed + */ +int goodix_ts_irq_enable(struct goodix_ts_core *core_data, bool enable); + +struct kobj_type *goodix_get_default_ktype(void); + +/** + * fb_notifier_call_chain - notify clients of fb_events + * see enum ts_notify_event in goodix_ts_core.h + */ +int goodix_ts_blocking_notify(enum ts_notify_event evt, void *v); + +/** + * * goodix_ts_power_on - Turn on power to the touch device + * * @core_data: pointer to touch core data + * * return: 0 ok, <0 failed + * */ +int goodix_ts_power_on(struct goodix_ts_core *core_data); + +/** + * goodix_ts_power_off - Turn off power to the touch device + * @core_data: pointer to touch core data + * return: 0 ok, <0 failed + */ +int goodix_ts_power_off(struct goodix_ts_core *core_data); +int goodix_ts_hw_init(struct goodix_ts_core *core_data); +int goodix_ts_input_dev_config(struct goodix_ts_core *core_data); +int goodix_ts_irq_setup(struct goodix_ts_core *core_data); +int goodix_ts_sysfs_init(struct goodix_ts_core *core_data); +int goodix_ts_esd_init(struct goodix_ts_core *core); +int goodix_ts_register_notifier(struct notifier_block *nb); +int goodix_generic_noti_callback(struct notifier_block *self, + unsigned long action, void *data); +int goodix_ts_fb_notifier_callback(struct notifier_block *self, + unsigned long event, void *data); +extern void goodix_msg_printf(const char *fmt, ...); +int goodix_gesture_enable(bool enable); + +int goodix_check_gesture_stat(bool enable); + +int goodix_get_lockdowninfo(struct goodix_ts_core *ts_core); +extern int sync_read_rawdata(unsigned int reg, unsigned char *data, + unsigned int len); +extern int goodix_tools_register(void); +extern int goodix_tools_unregister(void); +extern struct goodix_ts_core *goodix_core_data; +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_gesture.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_gesture.c new file mode 100644 index 000000000000..5cfebdea0eb3 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_gesture.c @@ -0,0 +1,756 @@ +/* + * Goodix GTX5 Gesture Dirver + * + * Copyright (C) 2015 - 2016 Goodix, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: Wang Yafei + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be a reference + * to you, when you are integrating the GOODiX's CTP IC into your system, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "goodix_ts_core.h" + +#define GSX_REG_GESTURE_DATA 0x4100 +#define GSX_REG_GESTURE 0x6F68 + +#define GSX_GESTURE_CMD 0x08 + +#define QUERYBIT(longlong, bit) (!!(longlong[bit / 8] & (1 << bit % 8))) + +extern int goodix_i2c_write(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len); +extern int goodix_i2c_read(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len); +static int goodix_set_suspend_func(struct goodix_ts_core *core_data); +static int goodix_wakeup_and_set_suspend_func(struct goodix_ts_core *core_data); + +#define GSX_KEY_DATA_LEN 37 +#define GSX_GESTURE_TYPE_LEN 32 +static int FP_Event_Gesture; + +/* + * struct gesture_module - gesture module data + * @registered: module register state + * @sysfs_node_created: sysfs node state + * @gesture_type: store valied gesture type,each bit stand for a gesture + * @gesture_data: gesture data + * @gesture_ts_cmd: gesture command data +*/ +struct gesture_module { + atomic_t registered; + unsigned int kobj_initialized; + rwlock_t rwlock; + unsigned char gesture_type[GSX_GESTURE_TYPE_LEN]; + unsigned char gesture_data[GSX_KEY_DATA_LEN]; + struct goodix_ext_module module; + struct goodix_ts_cmd cmd; +}; + +extern struct goodix_module goodix_modules; /*declaration at goodix_ts_core.c*/ + +static struct gesture_module *gsx_gesture; /*allocated in gesture init module*/ + +/** + * gsx_gesture_type_show - show valid gesture type + * + * @module: pointer to goodix_ext_module struct + * @buf: pointer to output buffer + * Returns >=0 - succeed,< 0 - failed + */ +static ssize_t gsx_gesture_type_show(struct goodix_ext_module *module, + char *buf) +{ + int count = 0, i, ret = 0; + unsigned char *type; + + if (atomic_read(&gsx_gesture->registered) != 1) { + ts_info("Gesture module not register!"); + return -EPERM; + } + type = kzalloc(256, GFP_KERNEL); + if (!type) + return -ENOMEM; + read_lock(&gsx_gesture->rwlock); + for (i = 0; i < 256; i++) { + if (QUERYBIT(gsx_gesture->gesture_type, i)) { + type[count] = i; + count++; + } + } + type[count] = '\0'; + if (count > 0) { + /* TODO 这里使用scnprintf需è¦ç¡®è®¤ä¸€ä¸‹æ˜¯å¦æœ‰æ•ˆ */ + ret = scnprintf(buf, PAGE_SIZE, "%s", type); + } + read_unlock(&gsx_gesture->rwlock); + + kfree(type); + return ret; +} + +/** + * gsx_gesture_type_store - set vailed gesture + * + * @module: pointer to goodix_ext_module struct + * @buf: pointer to valid gesture type + * @count: length of buf + * Returns >0 - valid gestures, < 0 - failed + */ +static ssize_t gsx_gesture_type_store(struct goodix_ext_module *module, + const char *buf, size_t count) +{ + int i; + + if (count <= 0 || count > 256 || buf == NULL) { + ts_err("Parameter error"); + return -EINVAL; + } + + write_lock(&gsx_gesture->rwlock); + memset(gsx_gesture->gesture_type, 0, GSX_GESTURE_TYPE_LEN); + for (i = 0; i < count; i++) + gsx_gesture->gesture_type[buf[i] / 8] |= (0x1 << buf[i] % 8); + write_unlock(&gsx_gesture->rwlock); + + return count; +} + +static ssize_t gsx_gesture_enable_show(struct goodix_ext_module *module, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%d\n", + atomic_read(&gsx_gesture->registered)); +} + +static ssize_t gsx_gesture_enable_store(struct goodix_ext_module *module, + const char *buf, size_t count) +{ + unsigned int tmp; + int ret; + + if (sscanf(buf, "%u", &tmp) != 1) { + ts_info("Parameter illegal"); + return -EINVAL; + } + ts_debug("Tmp value =%d", tmp); + + if (tmp == 1) { + if (atomic_read(&gsx_gesture->registered)) { + ts_debug("Gesture module has aready registered"); + return count; + } + ret = goodix_register_ext_module(&gsx_gesture->module); + if (!ret) { + ts_info("Gesture module registered!"); + atomic_set(&gsx_gesture->registered, 1); + } else { + atomic_set(&gsx_gesture->registered, 0); + ts_err("Gesture module register failed"); + } + } else if (tmp == 0) { + if (!atomic_read(&gsx_gesture->registered)) { + ts_debug("Gesture module has aready unregistered"); + return count; + } + ts_debug("Start unregistered gesture module"); + ret = goodix_unregister_ext_module(&gsx_gesture->module); + if (!ret) { + atomic_set(&gsx_gesture->registered, 0); + ts_info("Gesture module unregistered success"); + } else { + atomic_set(&gsx_gesture->registered, 1); + ts_info("Gesture module unregistered failed"); + } + } else { + ts_err("Parameter error!"); + return -EINVAL; + } + return count; +} + +int goodix_gesture_enable(bool enable) +{ + int ret = 0; + + if (enable == true) { + if (atomic_read(&gsx_gesture->registered)) { + ts_debug("Gesture module has aready registered"); + return 0; + } + ret = goodix_register_ext_module(&gsx_gesture->module); + if (!ret) { + ts_info("Gesture module registered!"); + atomic_set(&gsx_gesture->registered, 1); + } else { + atomic_set(&gsx_gesture->registered, 0); + ts_err("Gesture module register failed"); + } + } else { + if (!atomic_read(&gsx_gesture->registered)) { + ts_debug("Gesture module has aready unregistered"); + return 0; + } + ts_debug("Start unregistered gesture module"); + ret = goodix_unregister_ext_module(&gsx_gesture->module); + if (!ret) { + atomic_set(&gsx_gesture->registered, 0); + ts_info("Gesture module unregistered success"); + } else { + atomic_set(&gsx_gesture->registered, 1); + ts_info("Gesture module unregistered failed"); + } + } + + return 0; +} + +int goodix_sync_ic_stat(struct goodix_ts_core *core_data) +{ + int tp_stat; + int ret = 0; + + if (!core_data) { + ts_err("parameter illegal"); + } + + mutex_lock(&core_data->work_stat); + tp_stat = atomic_read(&core_data->suspend_stat); + if (tp_stat == TP_GESTURE_DBCLK) { + ts_info("sync IC suspend stat from DBCLK to DBCLK_FOD"); + + /*TODO:maybe add retry here*/ + ret = goodix_set_suspend_func(core_data); + if (ret < 0) + ts_err("set suspend function failed!!"); + } else if (tp_stat == TP_SLEEP) { + ts_info("sync IC suspend stat from SLEEP to FOD"); + + ret = goodix_wakeup_and_set_suspend_func(core_data); + if (ret < 0) + ts_err("set suspend function failed!!"); + } + mutex_unlock(&core_data->work_stat); + + return ret; +} + +int goodix_check_gesture_stat(bool enable) +{ + if (enable) { + goodix_sync_ic_stat(goodix_core_data); + } + return 0; +} +/** + * gsx_gesture_data_show - show gesture data read frome IC + * + * @module: pointer to goodix_ext_module struct + * @buf: pointer to output buffer + * Returns >0 - gesture data length,< 0 - failed + */ +/*static ssize_t gsx_gesture_data_show(struct goodix_ext_module *module, + char *buf) +{ + int count = GSX_KEY_DATA_LEN; + + if (atomic_read(&gsx_gesture->registered) != 1) { + ts_info("Gesture module not register!"); + return -EPERM; + } + if (!buf || !gsx_gesture->gesture_data) { + ts_info("Parameter error!"); + return -EPERM; + } + read_lock(&gsx_gesture->rwlock); + memcpy(buf, gsx_gesture->gesture_data, count); + read_unlock(&gsx_gesture->rwlock); + + return count; +}*/ + +static ssize_t gsx_gesture_data_show(struct goodix_ext_module *module, + char *buf) +{ + int count = GSX_KEY_DATA_LEN; + + if (atomic_read(&gsx_gesture->registered) != 1) { + ts_info("Gesture module not register!"); + return -EPERM; + } + if (!buf || !*(gsx_gesture->gesture_data)) { + ts_info("Parameter error!"); + return -EPERM; + } + read_lock(&gsx_gesture->rwlock); + + count = scnprintf(buf, PAGE_SIZE, "Previous gesture type:0x%x\n", + gsx_gesture->gesture_data[2]); + read_unlock(&gsx_gesture->rwlock); + + return count; +} + +const struct goodix_ext_attribute gesture_attrs[] = { + __EXTMOD_ATTR(type, 0666, gsx_gesture_type_show, + gsx_gesture_type_store), + __EXTMOD_ATTR(enable, 0666, gsx_gesture_enable_show, + gsx_gesture_enable_store), + __EXTMOD_ATTR(data, 0444, gsx_gesture_data_show, NULL) +}; + +static int gsx_gesture_init(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + int i, ret; + struct goodix_ts_device *ts_dev = core_data->ts_dev; + + if (!core_data || !ts_dev->hw_ops->write || !ts_dev->hw_ops->read) { + ts_err("Register gesture module failed, ts_core unsupported"); + goto exit_gesture_init; + } + + gsx_gesture->cmd.cmd_reg = GSX_REG_GESTURE; + gsx_gesture->cmd.length = 3; + gsx_gesture->cmd.cmds[0] = GSX_GESTURE_CMD; + gsx_gesture->cmd.cmds[1] = 0x0; + gsx_gesture->cmd.cmds[2] = 0 - GSX_GESTURE_CMD; + gsx_gesture->cmd.initialized = 1; + + memset(gsx_gesture->gesture_type, 0, GSX_GESTURE_TYPE_LEN); + memset(gsx_gesture->gesture_data, 0xff, GSX_KEY_DATA_LEN); + + ts_debug("Set gesture type manually"); + memset(gsx_gesture->gesture_type, 0xff, GSX_GESTURE_TYPE_LEN); + /*gsx_gesture->gesture_type[34/8] |= (0x1 << 34%8);*/ /* 0x22 double click */ + /*gsx_gesture->gesture_type[170/8] |= (0x1 << 170%8);*/ /* 0xaa up swip */ + /*gsx_gesture->gesture_type[187/8] |= (0x1 << 187%8);*/ /* 0xbb right swip */ + /*gsx_gesture->gesture_type[171/8] |= (0x1 << 171%8);*/ /* 0xab down swip */ + /*gsx_gesture->gesture_type[186/8] |= (0x1 << 186%8);*/ /* 0xba left swip */ + + if (gsx_gesture->kobj_initialized) + goto exit_gesture_init; + + ret = kobject_init_and_add(&module->kobj, goodix_get_default_ktype(), + &core_data->pdev->dev.kobj, "gesture"); + + if (ret) { + ts_err("Create gesture sysfs node error!"); + goto exit_gesture_init; + } + + for (i = 0; i < sizeof(gesture_attrs) / sizeof(gesture_attrs[0]); i++) { + if (sysfs_create_file(&module->kobj, &gesture_attrs[i].attr)) { + ts_err("Create sysfs attr file error"); + kobject_put(&module->kobj); + goto exit_gesture_init; + } + } + gsx_gesture->kobj_initialized = 1; + +exit_gesture_init: + return 0; +} +static int gsx_gesture_exit(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + /*if (gsx_gesture->kobj_initialized) + kobject_put(&module->kobj); + gsx_gesture->kobj_initialized = 0;*/ + atomic_set(&gsx_gesture->registered, 0); + return 0; +} + +/** + * gsx_gesture_ist - Gesture Irq handle + * This functions is excuted when interrupt happended and + * ic in doze mode. + * + * @core_data: pointer to touch core data + * @module: pointer to goodix_ext_module struct + * return: 0 goon execute, EVT_CANCEL_IRQEVT stop execute + */ +static int gsx_gesture_ist(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + int ret; + int x, y, area, overlapping_area; + unsigned char clear_reg = 0; + unsigned char checksum = 0, temp_data[GSX_KEY_DATA_LEN]; + struct goodix_ts_device *ts_dev = core_data->ts_dev; +#ifdef CONFIG_GOODIX_HWINFO + char ch[64] = { + 0x0, + }; +#endif + + /*ts_debug("gsx_gesture_ist, core_data-suspend=%d", + atomic_read(&core_data->suspended));*/ + /*ts_err("enter %s core_data->suspended=%d\n", __func__, atomic_read(&core_data->suspended));*/ + if (atomic_read(&core_data->suspended) == 0) + return EVT_CONTINUE; + + mutex_lock(&ts_dev->report_mutex); + /* get ic gesture state*/ + ret = ts_dev->hw_ops->read_trans(core_data->ts_dev, + GSX_REG_GESTURE_DATA, temp_data, + sizeof(temp_data)); + /*ts_err("enter %s temp_data[0]=0x%x ret=%d\n", __func__, temp_data[0], ret);*/ + if (ret < 0 || ((temp_data[0] & GOODIX_GESTURE_EVENT) == 0)) { + ts_err("Read gesture data faild, ret=%d, temp_data[0]=0x%x", + ret, temp_data[0]); + goto re_send_ges_cmd; + } + + if ((temp_data[0] & 0x08) != 0) { + FP_Event_Gesture = 1; + /*ts_debug("FP_Event_Gesture = %d", FP_Event_Gesture);*/ + } + + checksum = checksum_u8(temp_data, sizeof(temp_data)); + if (checksum != 0) { + ts_err("Gesture data checksum error:0x%x", checksum); + ts_info("Gesture data %*ph", (int)sizeof(temp_data), temp_data); + goto re_send_ges_cmd; + } + + /*ts_debug("temp_data： %*ph", (int)sizeof(temp_data), temp_data); + ts_debug("FP_Event_Gesture： %d", FP_Event_Gesture); + ts_debug("fod_status= %d aod_status=%d", core_data->fod_status, core_data->aod_status); + ts_debug("sleep_finger： %d", !core_data->sleep_finger);*/ + + if (core_data->fod_status || core_data->aod_status) { + if ((FP_Event_Gesture == 1) && (temp_data[2] == 0x46)) { + x = temp_data[4] | (temp_data[5] << 8); + y = temp_data[6] | (temp_data[7] << 8); + overlapping_area = temp_data[8]; + area = temp_data[9]; + + input_mt_slot(core_data->input_dev, 0); + input_mt_report_slot_state(core_data->input_dev, + MT_TOOL_FINGER, true); + input_report_key(core_data->input_dev, BTN_INFO, 1); + /*input_report_key(core_data->input_dev, KEY_INFO, 1);*/ + input_report_key(core_data->input_dev, BTN_TOUCH, 1); + input_report_key(core_data->input_dev, BTN_TOOL_FINGER, + 1); + input_report_abs(core_data->input_dev, ABS_MT_TOOL_TYPE, + MT_TOOL_FINGER); + input_report_abs(core_data->input_dev, + ABS_MT_POSITION_X, x); + input_report_abs(core_data->input_dev, + ABS_MT_POSITION_Y, y); + input_report_abs(core_data->input_dev, + ABS_MT_WIDTH_MINOR, overlapping_area); + /*input_report_abs(core_data->input_dev, ABS_MT_TOUCH_MINOR, area);*/ + + core_data->fod_pressed = true; + __set_bit(0, &core_data->touch_id); + + ts_debug( + "Gesture report, x=%d, y=%d, overlapping_area=%d, area=%d", + x, y, overlapping_area, area); + + /*wait for report key event*/ + FP_Event_Gesture = 0; + input_sync(core_data->input_dev); + } + + if ((FP_Event_Gesture == 1) && (temp_data[2] == 0x4c)) { + /*wait for report key event*/ + FP_Event_Gesture = 0; + input_report_key(core_data->input_dev, KEY_GOTO, 1); + input_sync(core_data->input_dev); + input_report_key(core_data->input_dev, KEY_GOTO, 0); + input_sync(core_data->input_dev); + core_data->sleep_finger = 0; + ts_debug("Gesture report L"); + } + + if ((FP_Event_Gesture == 1) && (temp_data[2] == 0xff)) { + if (core_data->fod_pressed) { + ts_debug("Gesture report up"); + input_mt_slot(core_data->input_dev, 0); + input_mt_report_slot_state(core_data->input_dev, + MT_TOOL_FINGER, + false); + input_report_abs(core_data->input_dev, + ABS_MT_WIDTH_MINOR, 0); + input_report_key(core_data->input_dev, BTN_INFO, + 0); + /*input_report_key(core_data->input_dev, KEY_INFO, 0);*/ + input_report_key(core_data->input_dev, + BTN_TOUCH, 0); + input_report_key(core_data->input_dev, + BTN_TOOL_FINGER, 0); + input_sync(core_data->input_dev); + __clear_bit(0, &core_data->touch_id); + core_data->fod_pressed = false; + } + core_data->sleep_finger = 0; + } + + write_lock(&gsx_gesture->rwlock); + memcpy(gsx_gesture->gesture_data, temp_data, sizeof(temp_data)); + write_unlock(&gsx_gesture->rwlock); + } + + if (temp_data[2] == 0xcc && core_data->double_wakeup) { + /*ts_info("Gesture match success, resume IC");*/ +#ifdef CONFIG_GOODIX_HWINFO + if (core_data) { + core_data->dbclick_count++; + snprintf(ch, sizeof(ch), "%d", + core_data->dbclick_count); + } +#endif + input_report_key(core_data->input_dev, KEY_WAKEUP, 1); + input_sync(core_data->input_dev); + input_report_key(core_data->input_dev, KEY_WAKEUP, 0); + input_sync(core_data->input_dev); + goto gesture_ist_exit; + } + if (QUERYBIT(gsx_gesture->gesture_type, temp_data[2])) { + /* do resume routine */ + /*ts_info("Gesture match success, resume IC");*/ + + goto gesture_ist_exit; + } else { + ts_info("Unsupported gesture:%x", temp_data[2]); + } + +re_send_ges_cmd: + /*if (ts_dev->hw_ops->send_cmd(core_data->ts_dev, gesture_cmd)) + ts_info("warning: failed re_send gesture cmd\n");*/ + if (goodix_set_suspend_func(core_data) < 0) + ts_err("set suspend function failed!!"); +gesture_ist_exit: + ts_dev->hw_ops->write_trans(core_data->ts_dev, GSX_REG_GESTURE_DATA, + &clear_reg, 1); + mutex_unlock(&ts_dev->report_mutex); + return EVT_CANCEL_IRQEVT; +} + +/** + *goodix_set_suspend_func - send cmd choose func when at suspend stat + *When cmd send successful,IC in doze mode + * + * @core_data: pointer to touch core data + * return: 0 send cmd successful, other send cmd failed. + */ +static int goodix_set_suspend_func(struct goodix_ts_core *core_data) +{ + struct goodix_ts_device *dev = core_data->ts_dev; + u8 state_data[3] = { 0 }; + int ret; + + if (core_data->double_wakeup && core_data->fod_status) { + state_data[0] = GSX_GESTURE_CMD; + state_data[1] = 0x01; + state_data[2] = 0xF7; + ret = goodix_i2c_write(dev, GSX_REG_GESTURE, state_data, 3); + ts_info("Set IC double wakeup mode on,FOD mode on;"); + } else if (core_data->double_wakeup && (!core_data->fod_status)) { + state_data[0] = GSX_GESTURE_CMD; + state_data[1] = 0x03; + state_data[2] = 0xF5; + ret = goodix_i2c_write(dev, GSX_REG_GESTURE, state_data, 3); + ts_info("Set IC double wakeup mode on,FOD mode off;"); + } else if (!core_data->double_wakeup && core_data->fod_status) { + state_data[0] = GSX_GESTURE_CMD; + state_data[1] = 0x00; + state_data[2] = 0xF8; + ret = goodix_i2c_write(dev, GSX_REG_GESTURE, state_data, 3); + ts_info("Set IC double wakeup mode off,FOD mode on;"); + } else if (!core_data->double_wakeup && (!core_data->fod_status)) { + state_data[0] = GSX_GESTURE_CMD; + state_data[1] = 0x02; + state_data[2] = 0xF6; + ret = goodix_i2c_write(dev, GSX_REG_GESTURE, state_data, 3); + ts_info("Set IC double wakeup mode off,FOD mode off;"); + } else { + ret = -1; + ts_info("Get IC mode falied,core_data->double_wakeup=%d,core_data->fod_status=%d;", + core_data->double_wakeup, core_data->fod_status); + } + + return ret; +} + +/** + *goodix_wakeup_and_set_suspend_func --- wake up ic from sleep mode and set suspend func + *invoke this func when ic in sleep mode + * + * @core_data: pointer to touch core data + * return: 0 reset ic stat successful, other failed. + */ +static int goodix_wakeup_and_set_suspend_func(struct goodix_ts_core *core_data) +{ + int r = 0; + int retry = 0; + struct goodix_ext_module *ext_module; + struct goodix_ts_device *ts_dev = core_data->ts_dev; + + /*start resume*/ + if (!list_empty(&goodix_modules.head)) { + list_for_each_entry(ext_module, &goodix_modules.head, list) { + if (!ext_module->funcs->before_resume) + continue; + + do { + r = ext_module->funcs->before_resume( + core_data, ext_module); + if (r == EVT_CANCEL_RESUME) { + ts_info("wait for fwupdate findish"); + mdelay(5); + } + } while (r == EVT_CANCEL_RESUME && ++retry < 3); + } + } + + if (ts_dev && ts_dev->hw_ops->resume) + ts_dev->hw_ops->resume(ts_dev); + goodix_ts_irq_enable(core_data, true); + /*finish resume*/ + + /*start suspend*/ + do { + r = goodix_set_suspend_func(core_data); + if (r < 0) { + ts_info("Send doze command failed, retry"); + } + } while (r < 0 && ++retry < 3); + + if (core_data->double_wakeup && core_data->fod_status) { + atomic_set(&core_data->suspend_stat, TP_GESTURE_DBCLK_FOD); + } else if (core_data->double_wakeup) { + atomic_set(&core_data->suspend_stat, TP_GESTURE_DBCLK); + } else if (core_data->fod_status) { + atomic_set(&core_data->suspend_stat, TP_GESTURE_FOD); + } + ts_info("suspend_stat[%d]", atomic_read(&core_data->suspend_stat)); + + /*finish suspend*/ + + return r; +} + +/** + * gsx_gesture_before_suspend - execute gesture suspend routine + * This functions is excuted to set ic into doze mode + * + * @core_data: pointer to touch core data + * @module: pointer to goodix_ext_module struct + * return: 0 goon execute, EVT_IRQCANCLED stop execute + */ +static int gsx_gesture_before_suspend(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + int ret; + const struct goodix_ts_hw_ops *hw_ops = core_data->ts_dev->hw_ops; + struct goodix_ts_cmd *gesture_cmd = &gsx_gesture->cmd; + + if (!gesture_cmd->initialized || hw_ops == NULL) { + ts_err("Uninitialized doze command or hw_ops"); + return 0; + } + + if (!core_data->gesture_enabled) { + ts_err("enter %s\n", __func__); + atomic_set(&core_data->suspended, 1); + return EVT_CONTINUE; + } + + ret = goodix_set_suspend_func(core_data); + if (ret != 0) { + ts_err("Send doze command error"); + return 0; + } else { + ts_info("Set IC in doze mode"); + atomic_set(&core_data->suspended, 1); + return EVT_CANCEL_SUSPEND; + } +} + +/** + * gsx_gesture_before_resume - execute gesture resume routine + * This functions is excuted to make ic out doze mode + * + * @core_data: pointer to touch core data + * @module: pointer to goodix_ext_module struct + * return: 0 goon execute, EVT_CANCLED stop execute + * +static int gsx_gesture_before_resume(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct goodix_ts_device *ts_dev = core_data->ts_dev; + + ts_dev->hw_ops->reset(ts_dev); + return 0; +} +*/ + +static struct goodix_ext_module_funcs gsx_gesture_funcs = { + .irq_event = gsx_gesture_ist, + .init = gsx_gesture_init, + .exit = gsx_gesture_exit, + .before_suspend = gsx_gesture_before_suspend +}; + +static int __init goodix_gsx_gesture_init(void) +{ + /* initialize core_data->ts_dev->gesture_cmd*/ + int result; + ts_info("gesture module init"); + gsx_gesture = kzalloc(sizeof(struct gesture_module), GFP_KERNEL); + if (!gsx_gesture) + result = -ENOMEM; + gsx_gesture->module.funcs = &gsx_gesture_funcs; + gsx_gesture->module.priority = EXTMOD_PRIO_GESTURE; + gsx_gesture->module.name = "Goodix_gsx_gesture"; + gsx_gesture->module.priv_data = gsx_gesture; + gsx_gesture->kobj_initialized = 0; + atomic_set(&gsx_gesture->registered, 0); + rwlock_init(&gsx_gesture->rwlock); + + result = goodix_register_ext_module(&(gsx_gesture->module)); + if (result == 0) + atomic_set(&gsx_gesture->registered, 1); + + return result; +} + +static void __exit goodix_gsx_gesture_exit(void) +{ + ts_info("gesture module exit"); + if (gsx_gesture->kobj_initialized) + kobject_put(&gsx_gesture->module.kobj); + kfree(gsx_gesture); + return; +} + +module_init(goodix_gsx_gesture_init); +module_exit(goodix_gsx_gesture_exit); + +MODULE_DESCRIPTION("Goodix gsx Touchscreen Gesture Module"); +MODULE_AUTHOR("Goodix, Inc."); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_i2c.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_i2c.c new file mode 100644 index 000000000000..e9aa14f30a20 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_i2c.c @@ -0,0 +1,2230 @@ +/* + * Goodix GTx5 I2C Dirver + * Hardware interface layer of touchdriver architecture. + * + * Copyright (C) 2015 - 2016 Goodix, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: Yulong Cai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be a reference + * to you, when you are integrating the GOODiX's CTP IC into your system, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include "goodix_ts_core.h" +#include "goodix_cfg_bin.h" +#include +#include + +#define TS_DT_COMPATIBLE "goodix,gt9889" +#define TS_DRIVER_NAME "goodix_i2c" +#define I2C_MAX_TRANSFER_SIZE 256 +#define TS_ADDR_LENGTH 2 +#define TS_DOZE_ENABLE_RETRY_TIMES 10 +#define TS_DOZE_DISABLE_RETRY_TIMES 10 +#define TS_WAIT_CFG_READY_RETRY_TIMES 30 +#define TS_WAIT_CMD_FREE_RETRY_TIMES 10 + +#define TS_REG_COORDS_BASE 0x824E +#define TS_REG_CMD 0x8040 +#define TS_REG_REQUEST 0x8044 +#define TS_REG_VERSION 0x8240 +#define TS_REG_CFG_BASE 0x8050 +#define TS_REG_DOZE_CTRL 0x30F0 +#define TS_REG_DOZE_STAT 0x3100 +#define TS_REG_ESD_TICK_R 0x3103 + +#define CFG_XMAX_OFFSET (0x8052 - 0x8050) +#define CFG_YMAX_OFFSET (0x8054 - 0x8050) + +#define REQUEST_HANDLED 0x00 +#define REQUEST_CONFIG 0x01 +#define REQUEST_BAKREF 0x02 +#define REQUEST_RESET 0x03 +#define REQUEST_MAINCLK 0x04 +#define REQUEST_IDLE 0x05 + +#define COMMAND_SLEEP 0x05 +#define COMMAND_CLOSE_HID 0xaa +#define COMMAND_START_SEND_CFG 0x80 +#define COMMAND_END_SEND_CFG 0x83 +#define COMMAND_SEND_SMALL_CFG 0x81 +#define COMMAND_SEND_CFG_PREPARE_OK 0x82 +#define COMMAND_START_READ_CFG 0x86 +#define COMMAND_READ_CFG_PREPARE_OK 0x85 + +#define BYTES_PER_COORD 8 +#define TS_MAX_SENSORID 5 +#define TS_CFG_MAX_LEN 1024 +#define TS_CFG_HEAD_LEN 4 +#define TS_CFG_BAG_NUM_INDEX 2 +#define TS_CFG_BAG_START_INDEX 4 +#if TS_CFG_MAX_LEN > GOODIX_CFG_MAX_SIZE +#error GOODIX_CFG_MAX_SIZE too small, please fix. +#endif + +#define TS_DOZE_DISABLE_DATA 0xAA +#define TS_DOZE_CLOSE_OK_DATA 0xBB +#define TS_DOZE_ENABLE_DATA 0xCC +#define TS_CMD_REG_READY 0xFF + +#ifdef CONFIG_OF +int pre_event; + +/** + * goodix_parse_dt_resolution - parse resolution from dt + * @node: devicetree node + * @board_data: pointer to board data structure + * return: 0 - no error, <0 error +*/ +static int goodix_parse_dt_resolution(struct device_node *node, + struct goodix_ts_board_data *board_data) +{ + int r, err; + + r = of_property_read_u32(node, "goodix,panel-max-id", + &board_data->panel_max_id); + if (r) { + err = -ENOENT; + } else { + if (board_data->panel_max_id > GOODIX_MAX_TOUCH) + board_data->panel_max_id = GOODIX_MAX_TOUCH; + } + + r = of_property_read_u32(node, "goodix,panel-max-x", + &board_data->panel_max_x); + if (r) + err = -ENOENT; + + r = of_property_read_u32(node, "goodix,panel-max-y", + &board_data->panel_max_y); + if (r) + err = -ENOENT; + + r = of_property_read_u32(node, "goodix,panel-max-w", + &board_data->panel_max_w); + if (r) + err = -ENOENT; + + r = of_property_read_u32(node, "goodix,panel-max-p", + &board_data->panel_max_p); + if (r) + err = -ENOENT; + + r = of_property_read_u32(node, "goodix,panel-max-fod", + &board_data->panel_max_overlapping_area); + if (r) + err = -ENOENT; + + board_data->swap_axis = of_property_read_bool(node, "goodix,swap-axis"); + + board_data->x2x = of_property_read_bool(node, "goodix,x2x"); + + board_data->y2y = of_property_read_bool(node, "goodix,y2y"); + + return 0; +} + +/** + * goodix_parse_dt - parse board data from dt + * @dev: pointer to device + * @board_data: pointer to board data structure + * return: 0 - no error, <0 error +*/ +static int goodix_parse_dt(struct device_node *node, + struct goodix_ts_board_data *board_data) +{ + struct property *prop; + int r; + + ts_err("enter::%s\n", __func__); + if (!board_data) { + ts_err("Invalid board data"); + return -EINVAL; + } + + r = of_get_named_gpio(node, "goodix,reset-gpio", 0); + if (r < 0) { + ts_err("Invalid reset-gpio in dt: %d", r); + return -EINVAL; + } else { + ts_info("Parse reset-gpio[%d] from dt", r); + board_data->reset_gpio = r; + } + + r = of_get_named_gpio(node, "goodix,vdd-gpio", 0); + if (r < 0) { + ts_err("Invalid vdd-gpio in dt: %d", r); + return -EINVAL; + } else { + ts_info("Parse vdd-gpio[%d] from dt", r); + board_data->vdd_gpio = r; + } + + r = of_get_named_gpio(node, "goodix,avdd-gpio", 0); + if (r < 0) { + ts_err("Invalid avdd-gpio in dt: %d", r); + return -EINVAL; + } else { + ts_info("Parse avdd-gpio[%d] from dt", r); + board_data->avdd_gpio = r; + } + + r = of_get_named_gpio(node, "goodix,irq-gpio", 0); + if (r < 0) { + ts_err("Invalid irq-gpio in dt: %d", r); + return -EINVAL; + } else { + ts_info("Parse irq-gpio[%d] from dt", r); + board_data->irq_gpio = r; + } + + r = of_property_read_u32(node, "goodix,irq-flags", + &board_data->irq_flags); + if (r) { + ts_err("Invalid irq-flags"); + return -EINVAL; + } + + board_data->avdd_name = "vtouch"; + board_data->vddio_name = "iotouch"; + r = of_property_read_u32(node, "vtouch-load", &board_data->avdd_load); + if (r) { + ts_err("can't get vtouch-load"); + board_data->avdd_load = 0; + } + + r = of_property_read_string(node, "goodix,cfg-name", + &board_data->cfg_bin_name); + if (r) { + ts_err("can't get cfg name"); + board_data->cfg_bin_name = NULL; + } + + r = of_property_read_u32(node, "goodix,power-on-delay-us", + &board_data->power_on_delay_us); + if (!r) { + /* 1000ms is too large, maybe you have pass + * a wrong value */ + if (board_data->power_on_delay_us > 1000 * 1000) { + ts_err("Power on delay time exceed 1s, please check"); + board_data->power_on_delay_us = 0; + } + } + + r = of_property_read_u32(node, "goodix,power-off-delay-us", + &board_data->power_off_delay_us); + if (!r) { + /* 1000ms is too large, maybe you have pass + * a wrong value */ + if (board_data->power_off_delay_us > 1000 * 1000) { + ts_err("Power off delay time exceed 1s, please check"); + board_data->power_off_delay_us = 0; + } + } + + /* get xyz resolutions */ + r = goodix_parse_dt_resolution(node, board_data); + if (r < 0) { + ts_err("Failed to parse resolutions:%d", r); + return r; + } + + /* key map */ + prop = of_find_property(node, "goodix,panel-key-map", NULL); + if (prop && prop->length) { + if (prop->length / sizeof(u32) > GOODIX_MAX_KEY) { + ts_err("Size of panel-key-map is invalid"); + return r; + } + + board_data->panel_max_key = prop->length / sizeof(u32); + board_data->tp_key_num = prop->length / sizeof(u32); + r = of_property_read_u32_array(node, "goodix,panel-key-map", + &board_data->panel_key_map[0], + board_data->panel_max_key); + if (r) + return r; + } + + /*get pen-enable switch and pen keys, must after "key map"*/ + board_data->pen_enable = + of_property_read_bool(node, "goodix,pen-enable"); + if (board_data->pen_enable) { + prop = of_find_property(node, "goodix,key-of-pen", NULL); + if (prop && prop->length) { + if (prop->length / sizeof(u32) > GOODIX_PEN_MAX_KEY) { + ts_err("Size of key-of-pen is invalid"); + return r; + } + r = of_property_read_u32_array( + node, "goodix,key-of-pen", + &board_data->panel_key_map + [board_data->panel_max_key], + prop->length / sizeof(u32)); + if (r) + return r; + board_data->panel_max_key += + (prop->length / sizeof(u32)); + } + } + ts_info("***key:%d, %d, %d, %d, %d", board_data->panel_key_map[0], + board_data->panel_key_map[1], board_data->panel_key_map[2], + board_data->panel_key_map[3], board_data->panel_key_map[4]); + /*add end*/ + + ts_debug("[DT]id:%d, x:%d, y:%d, w:%d, p:%d", board_data->panel_max_id, + board_data->panel_max_x, board_data->panel_max_y, + board_data->panel_max_w, board_data->panel_max_p); + return 0; +} + +/** + * goodix_parse_customize_params - parse sensor independent params + * @dev: pointer to device data + * @board_data: board data + * @sensor_id: sensor ID + * return: 0 - read ok, < 0 - i2c transter error +*/ +static int +goodix_parse_customize_params(struct goodix_ts_device *dev, + struct goodix_ts_board_data *board_data, + unsigned int sensor_id) +{ + struct device_node *node = dev->dev->of_node; + char of_node_name[24]; + int r; + + if (sensor_id > TS_MAX_SENSORID || node == NULL) { + ts_err("Invalid sensor id"); + return -EINVAL; + } + + /* parse sensor independent parameters */ + snprintf(of_node_name, sizeof(of_node_name), "sensor%u", sensor_id); + node = of_find_node_by_name(dev->dev->of_node, of_node_name); + if (!node) { + ts_err("Child property[%s] not found", of_node_name); + return -EINVAL; + } + + r = of_property_read_string(node, "goodix,fw-name", + &board_data->fw_name); + if (r) { + ts_err("can't get firmware name"); + board_data->fw_name = NULL; + } + + r = of_property_read_string(node, "goodix,limit-name", + &board_data->limit_name); + if (r) { + ts_err("can't get limit name"); + board_data->limit_name = NULL; + } + + /* sensor independent resolutions */ + r = goodix_parse_dt_resolution(node, board_data); + return r; +} +#endif + +#ifdef CONFIG_ACPI +static int goodix_parse_acpi(struct acpi_device *dev, + struct goodix_ts_board_data *bdata) +{ + return 0; +} + +static int goodix_parse_acpi_cfg(struct acpi_device *dev, char *cfg_type, + struct goodix_ts_config *config, + unsigned int sensor_id) +{ + return 0; +} +#endif + +/** + * goodix_i2c_read_trans - read device register through i2c bus + * @dev: pointer to device data + * @addr: register address + * @data: read buffer + * @len: bytes to read + * return: 0 - read ok, < 0 - i2c transter error +*/ +int goodix_i2c_read_trans(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len) +{ + struct i2c_client *client = to_i2c_client(dev->dev); + unsigned int transfer_length = 0; + unsigned int pos = 0, address = reg; + unsigned char get_buf[32], addr_buf[2]; + int retry, r = 0; + struct i2c_msg msgs[] = { { + .addr = client->addr, + .flags = !I2C_M_RD, + .buf = &addr_buf[0], + .len = TS_ADDR_LENGTH, + }, + { + .addr = client->addr, + .flags = I2C_M_RD, + } }; + + if (likely(len < sizeof(get_buf))) { + /* code optimize, use stack memory */ + msgs[1].buf = &get_buf[0]; + } else { + msgs[1].buf = kzalloc(I2C_MAX_TRANSFER_SIZE < len ? + I2C_MAX_TRANSFER_SIZE : + len, + GFP_KERNEL); + if (msgs[1].buf == NULL) { + ts_err("Malloc failed"); + return -ENOMEM; + } + } + + while (pos != len) { + if (unlikely(len - pos > I2C_MAX_TRANSFER_SIZE)) + transfer_length = I2C_MAX_TRANSFER_SIZE; + else + transfer_length = len - pos; + + msgs[0].buf[0] = (address >> 8) & 0xFF; + msgs[0].buf[1] = address & 0xFF; + msgs[1].len = transfer_length; + + for (retry = 0; retry < GOODIX_BUS_RETRY_TIMES; retry++) { + if (likely(i2c_transfer(client->adapter, msgs, 2) == + 2)) { + memcpy(&data[pos], msgs[1].buf, + transfer_length); + pos += transfer_length; + address += transfer_length; + break; + } + ts_info("I2c read retry[%d]:0x%x", retry + 1, reg); + msleep(20); + } + if (unlikely(retry == GOODIX_BUS_RETRY_TIMES)) { + ts_err("I2c read failed,dev:%02x,reg:%04x,size:%u", + client->addr, reg, len); + r = -EBUS; + goto read_exit; + } + } + +read_exit: + if (unlikely(len >= sizeof(get_buf))) + kfree(msgs[1].buf); + return r; +} + +/** + * goodix_i2c_write_trans - write device register through i2c bus + * @dev: pointer to device data + * @addr: register address + * @data: write buffer + * @len: bytes to write + * return: 0 - write ok; < 0 - i2c transter error. +*/ +int goodix_i2c_write_trans(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len) +{ + struct i2c_client *client = to_i2c_client(dev->dev); + unsigned int pos = 0, transfer_length = 0; + unsigned int address = reg; + unsigned char put_buf[64]; + int retry, r = 0; + struct i2c_msg msg = { + .addr = client->addr, + .flags = !I2C_M_RD, + }; + + if (likely(len + TS_ADDR_LENGTH < sizeof(put_buf))) { + /* code optimize,use stack memory*/ + msg.buf = &put_buf[0]; + } else { + msg.buf = kmalloc(I2C_MAX_TRANSFER_SIZE < len + TS_ADDR_LENGTH ? + I2C_MAX_TRANSFER_SIZE : + len + TS_ADDR_LENGTH, + GFP_KERNEL); + if (msg.buf == NULL) { + ts_err("Malloc failed"); + return -ENOMEM; + } + } + + while (pos != len) { + if (unlikely(len - pos > + I2C_MAX_TRANSFER_SIZE - TS_ADDR_LENGTH)) + transfer_length = + I2C_MAX_TRANSFER_SIZE - TS_ADDR_LENGTH; + else + transfer_length = len - pos; + + msg.buf[0] = (unsigned char)((address >> 8) & 0xFF); + msg.buf[1] = (unsigned char)(address & 0xFF); + msg.len = transfer_length + 2; + memcpy(&msg.buf[2], &data[pos], transfer_length); + + for (retry = 0; retry < GOODIX_BUS_RETRY_TIMES; retry++) { + if (likely(i2c_transfer(client->adapter, &msg, 1) == + 1)) { + pos += transfer_length; + address += transfer_length; + break; + } + ts_info("I2c write retry[%d]", retry + 1); + msleep(20); + } + if (unlikely(retry == GOODIX_BUS_RETRY_TIMES)) { + ts_err("I2c write failed,dev:%02x,reg:%04x,size:%u", + client->addr, reg, len); + r = -EBUS; + goto write_exit; + } + } + +write_exit: + if (likely(len + TS_ADDR_LENGTH >= sizeof(put_buf))) + kfree(msg.buf); + return r; +} + +/** + * goodix_set_i2c_doze_mode - disable or enable doze mode + * @dev: pointer to device data + * @enable: true/flase + * return: 0 - ok; < 0 - error. + * This func must be used in pairs, when you disable doze + * mode, then you must enable it again. + * Between set_doze_false and set_doze_true, do not reset + * IC! +*/ +int goodix_set_i2c_doze_mode(struct goodix_ts_device *dev, int enable) +{ + int result = -EINVAL; + int i; + u8 w_data, r_data; + + if (dev->ic_type != IC_TYPE_NORMANDY) + return 0; + mutex_lock(&dev->doze_mode_lock); + if (enable) { + if (dev->doze_mode_set_count != 0) + dev->doze_mode_set_count--; + /*when count equal 0, allow ic enter doze mode*/ + if (dev->doze_mode_set_count == 0) { + w_data = TS_DOZE_ENABLE_DATA; + for (i = 0; i < TS_DOZE_ENABLE_RETRY_TIMES; i++) { + result = goodix_i2c_write_trans( + dev, TS_REG_DOZE_CTRL, &w_data, 1); + if (!result) { + result = 0; + goto exit; + } + usleep_range(1000, 1100); + } + if (i >= TS_DOZE_ENABLE_RETRY_TIMES) + ts_err("i2c doze mode enable failed, i2c write fail"); + } else { + /*ts_info("doze count not euqal 0, so skip doze mode enable");*/ + result = 0; + goto exit; + } + } else { + dev->doze_mode_set_count++; + if (dev->doze_mode_set_count == 1) { + w_data = TS_DOZE_DISABLE_DATA; + goodix_i2c_write_trans(dev, TS_REG_DOZE_CTRL, &w_data, + 1); + usleep_range(1000, 1100); + for (i = 0; i < TS_DOZE_DISABLE_RETRY_TIMES; i++) { + goodix_i2c_read_trans(dev, TS_REG_DOZE_STAT, + &r_data, 1); + if (TS_DOZE_CLOSE_OK_DATA == r_data) { + result = 0; + goto exit; + } else if (0xAA != r_data) { + w_data = TS_DOZE_DISABLE_DATA; + goodix_i2c_write_trans(dev, + TS_REG_DOZE_CTRL, + &w_data, 1); + } + usleep_range(10000, 10100); + } + ts_err("doze mode disable FAILED"); + } else { + result = 0; + goto exit; + } + } + +exit: + mutex_unlock(&dev->doze_mode_lock); + return result; +} + +/** + * goodix_i2c_write - write device register through i2c bus + * @dev: pointer to device data + * @addr: register address + * @data: write buffer + * @len: bytes to write + * return: 0 - write ok; < 0 - i2c transter error. +*/ +int goodix_i2c_write(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len) +{ + int r; + + if (dev->ic_type == IC_TYPE_NORMANDY) { + if (goodix_set_i2c_doze_mode(dev, false) != 0) + ts_err("gtx8 i2c write:0x%04x ERROR, disable doze mode FAILED", + reg); + } + + r = goodix_i2c_write_trans(dev, reg, data, len); + + if (dev->ic_type == IC_TYPE_NORMANDY) { + if (goodix_set_i2c_doze_mode(dev, true) != 0) + ts_err("gtx8 i2c write:0x%04x ERROR, enable doze mode FAILED", + reg); + } + return r; +} + +/** + * goodix_i2c_read - read device register through i2c bus + * @dev: pointer to device data + * @addr: register address + * @data: read buffer + * @len: bytes to read + * return: 0 - read ok, < 0 - i2c transter error +*/ +int goodix_i2c_read(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len) +{ + int r; + + if (dev->ic_type == IC_TYPE_NORMANDY) { + if (goodix_set_i2c_doze_mode(dev, false) != 0) + ts_err("gtx8 i2c read:0x%04x ERROR, disable doze mode FAILED", + reg); + } + r = goodix_i2c_read_trans(dev, reg, data, len); + if (dev->ic_type == IC_TYPE_NORMANDY) { + if (goodix_set_i2c_doze_mode(dev, true) != 0) + ts_err("gtx8 i2c read:0x%04x ERROR, enable doze mode FAILED", + reg); + } + return r; +} + +/** + * goodix_i2c_write_trans_once - + * write device register through i2c bus, no retry + * @dev: pointer to device data + * @addr: register address + * @data: write buffer + * @len: bytes to write + * return: 0 - write ok; < 0 - i2c transter error. +*/ +int goodix_i2c_write_trans_once(struct goodix_ts_device *dev, unsigned int reg, + unsigned char *data, unsigned int len) +{ + struct i2c_client *client = to_i2c_client(dev->dev); + unsigned int pos = 0, transfer_length = 0; + unsigned int address = reg; + unsigned char put_buf[64]; + struct i2c_msg msg = { + .addr = client->addr, + .flags = !I2C_M_RD, + }; + + if (likely(len + TS_ADDR_LENGTH < sizeof(put_buf))) { + /* code optimize,use stack memory*/ + msg.buf = &put_buf[0]; + } else { + msg.buf = kmalloc(I2C_MAX_TRANSFER_SIZE < len + TS_ADDR_LENGTH ? + I2C_MAX_TRANSFER_SIZE : + len + TS_ADDR_LENGTH, + GFP_KERNEL); + if (msg.buf == NULL) { + ts_err("Malloc failed"); + return -ENOMEM; + } + } + + while (pos != len) { + if (unlikely(len - pos > + I2C_MAX_TRANSFER_SIZE - TS_ADDR_LENGTH)) + transfer_length = + I2C_MAX_TRANSFER_SIZE - TS_ADDR_LENGTH; + else + transfer_length = len - pos; + + msg.buf[0] = (unsigned char)((address >> 8) & 0xFF); + msg.buf[1] = (unsigned char)(address & 0xFF); + msg.len = transfer_length + 2; + memcpy(&msg.buf[2], &data[pos], transfer_length); + + i2c_transfer(client->adapter, &msg, 1); + pos += transfer_length; + address += transfer_length; + } + + if (likely(len + TS_ADDR_LENGTH >= sizeof(put_buf))) + kfree(msg.buf); + return 0; +} + +static void goodix_cmds_init(struct goodix_ts_cmd *ts_cmd, u8 cmds, u8 cmd_data, + u32 reg_addr) +{ + if (reg_addr) { + ts_cmd->cmd_reg = reg_addr; + ts_cmd->length = 3; + ts_cmd->cmds[0] = cmds; + ts_cmd->cmds[1] = cmd_data; + ts_cmd->cmds[2] = 0 - cmds - cmd_data; + ts_cmd->initialized = true; + } else { + ts_cmd->initialized = false; + } +} + +/** + * goodix_send_command - seng cmd to firmware + * + * @dev: pointer to device + * @cmd: pointer to command struct which cotain command data + * Returns 0 - succeed,<0 - failed + */ +int goodix_send_command(struct goodix_ts_device *dev, struct goodix_ts_cmd *cmd) +{ + int ret; + + if (!cmd || !cmd->initialized) + return -EINVAL; + + ret = goodix_i2c_write(dev, cmd->cmd_reg, cmd->cmds, cmd->length); + + return ret; +} + +static int goodix_read_version(struct goodix_ts_device *dev, + struct goodix_ts_version *version) +{ + u8 buffer[12]; + u8 temp_buf[256], checksum; + int r; + u8 pid_read_len = dev->reg.pid_len; + u8 vid_read_len = dev->reg.vid_len; + u8 sensor_id_mask = dev->reg.sensor_id_mask; +#define IS_CHAR(c) \ + (((c) >= 'A' && (c) <= 'Z') || ((c) >= 'a' && (c) <= 'z') || \ + ((c) >= '0' && (c) <= '9')) + + if (!version) { + ts_err("pointer of version is NULL"); + return -EINVAL; + } + version->valid = false; + + /*check reg info valid*/ + if (!dev->reg.pid || !dev->reg.sensor_id || !dev->reg.vid) { + ts_err("reg is NULL, pid:0x%04x, vid:0x%04x, sensor_id:0x%04x", + dev->reg.pid, dev->reg.vid, dev->reg.sensor_id); + return -EINVAL; + } + if (!pid_read_len || pid_read_len > GOODIX_PID_MAX_LEN || + !vid_read_len || vid_read_len > GOODIX_VID_MAX_LEN) { + ts_err("pid vid read len ERROR, pid_read_len:%d, vid_read_len:%d", + pid_read_len, vid_read_len); + return -EINVAL; + } + + /*disable doze mode, just valid for normandy + * this func must be used in pairs*/ + goodix_set_i2c_doze_mode(dev, false); + + /*check checksum*/ + if (dev->reg.version_base && dev->reg.version_len < 256) { + r = goodix_i2c_read(dev, dev->reg.version_base, temp_buf, + dev->reg.version_len); + + if (r < 0) { + ts_err("Read version base failed, reg:0x%02x, len:%d", + dev->reg.version_base, dev->reg.version_len); + if (version) + version->valid = false; + goto exit; + } + + checksum = checksum_u8(temp_buf, dev->reg.version_len); + if (checksum) { + ts_err("checksum error:0x%02x, base:0x%02x, len:%d", + checksum, dev->reg.version_base, + dev->reg.version_len); + ts_err("%*ph", (int)(dev->reg.version_len / 2), + temp_buf); + ts_err("%*ph", + (int)(dev->reg.version_len - + dev->reg.version_len / 2), + &temp_buf[dev->reg.version_len / 2]); + + if (version) + version->valid = false; + r = -EINVAL; + goto exit; + } + } + + /*read pid*/ + memset(buffer, 0, sizeof(buffer)); + memset(version->pid, 0, sizeof(version->pid)); + r = goodix_i2c_read(dev, dev->reg.pid, buffer, pid_read_len); + if (r < 0) { + ts_err("Read pid failed"); + if (version) + version->valid = false; + goto exit; + } + memcpy(version->pid, buffer, pid_read_len); + + /*read vid*/ + memset(buffer, 0, sizeof(buffer)); + memset(version->vid, 0, sizeof(version->vid)); + r = goodix_i2c_read(dev, dev->reg.vid, buffer, vid_read_len); + if (r < 0) { + ts_err("Read vid failed"); + if (version) + version->valid = false; + goto exit; + } + memcpy(version->vid, buffer, vid_read_len); + ts_info("PID:%s, VID:0x%02x 0x%02x 0x%02x 0x%02x", version->pid, + version->vid[0], version->vid[1], version->vid[2], + version->vid[3]); + /*read sensor_id*/ + memset(buffer, 0, sizeof(buffer)); + r = goodix_i2c_read(dev, dev->reg.sensor_id, buffer, 1); + if (r < 0) { + ts_err("Read sensor_id failed"); + if (version) + version->valid = false; + goto exit; + } + if (sensor_id_mask != 0) { + version->sensor_id = buffer[0] & sensor_id_mask; + ts_info("sensor_id_mask:0x%02x, sensor_id:0x%02x", + sensor_id_mask, version->sensor_id); + } else { + version->sensor_id = buffer[0]; + } + + version->valid = true; + + r = goodix_i2c_read(dev, dev->reg.vid, buffer, vid_read_len); + memcpy(version->vid, buffer, vid_read_len); + ts_info("PID:%s,SensorID:%d, VID:%*ph", version->pid, + version->sensor_id, (int)sizeof(version->vid), version->vid); + +exit: + /*enable doze mode, just valid for normandy + * this func must be used in pairs*/ + goodix_set_i2c_doze_mode(dev, true); + + return r; +} + +static int goodix_wait_cfg_cmd_ready(struct goodix_ts_device *dev, u8 right_cmd, + u8 send_cmd) +{ + int try_times = 0; + u8 cmd_flag = 0; + u8 cmd_buf[3] = { 0 }; + u16 command_reg = dev->reg.command; + struct goodix_ts_cmd ts_cmd; + + goodix_cmds_init(&ts_cmd, send_cmd, 0, command_reg); + + for (try_times = 0; try_times < TS_WAIT_CFG_READY_RETRY_TIMES; + try_times++) { + if (goodix_i2c_read(dev, command_reg, cmd_buf, 3)) { + ts_err("Read cmd_reg error"); + return -EINVAL; + } + cmd_flag = cmd_buf[0]; + if (cmd_flag == right_cmd) { + return 0; + } else if (cmd_flag != send_cmd) { + ts_err("Read cmd_reg data abnormal,return:0x%02X, 0x%02X, 0x%02X, send again", + cmd_buf[0], cmd_buf[1], cmd_buf[2]); + if (goodix_send_command(dev, &ts_cmd)) { + ts_err("Resend cmd 0x%02X FAILED", send_cmd); + return -EINVAL; + } + } + usleep_range(10000, 11000); + } + + return -EINVAL; +} + +static int goodix_send_small_config(struct goodix_ts_device *dev, + struct goodix_ts_config *config) +{ + int r = 0; + int try_times = 0; + u8 buf = 0; + u16 command_reg = dev->reg.command; + u16 cfg_reg = dev->reg.cfg_addr; + struct goodix_ts_cmd ts_cmd; + + /*1. Inquire command_reg until it's free*/ + for (try_times = 0; try_times < TS_WAIT_CMD_FREE_RETRY_TIMES; + try_times++) { + if (!goodix_i2c_read(dev, command_reg, &buf, 1) && + buf == TS_CMD_REG_READY) + break; + usleep_range(10000, 11000); + } + if (try_times >= TS_WAIT_CMD_FREE_RETRY_TIMES) { + ts_err("Send small cfg FAILED, before send, reg:0x%04x is not 0xff", + command_reg); + r = -EINVAL; + goto exit; + } + + /*2. write cfg data*/ + if (goodix_i2c_write(dev, cfg_reg, config->data, config->length)) { + ts_err("Send small cfg FAILED, write cfg to fw ERROR"); + r = -EINVAL; + goto exit; + } + + /*3. send 0x81 command*/ + goodix_cmds_init(&ts_cmd, COMMAND_SEND_SMALL_CFG, 0, dev->reg.command); + if (goodix_send_command(dev, &ts_cmd)) { + ts_err("Send large cfg FAILED, send COMMAND_SEND_SMALL_CFG ERROR"); + r = -EINVAL; + goto exit; + } + + r = 0; + ts_info("send small cfg SUCCESS"); + +exit: + return r; +} + +static int goodix_send_large_config(struct goodix_ts_device *dev, + struct goodix_ts_config *config) +{ + int r = 0; + int try_times = 0; + u8 buf = 0; + u16 command_reg = dev->reg.command; + u16 cfg_reg = dev->reg.cfg_addr; + struct goodix_ts_cmd ts_cmd; + + /*1. Inquire command_reg until it's free*/ + for (try_times = 0; try_times < TS_WAIT_CMD_FREE_RETRY_TIMES; + try_times++) { + if (!goodix_i2c_read(dev, command_reg, &buf, 1) && + buf == TS_CMD_REG_READY) + break; + usleep_range(10000, 11000); + } + if (try_times >= TS_WAIT_CMD_FREE_RETRY_TIMES) { + ts_err("Send large cfg FAILED, before send, reg:0x%04x is not 0xff", + command_reg); + r = -EINVAL; + goto exit; + } + + /*2. send "start write cfg" command*/ + goodix_cmds_init(&ts_cmd, COMMAND_START_SEND_CFG, 0, dev->reg.command); + if (goodix_send_command(dev, &ts_cmd)) { + ts_err("Send large cfg FAILED, send COMMAND_START_SEND_CFG ERROR"); + r = -EINVAL; + goto exit; + } + + /*3. wait ic set command_reg to 0x82*/ + if (goodix_wait_cfg_cmd_ready(dev, COMMAND_SEND_CFG_PREPARE_OK, + COMMAND_START_SEND_CFG)) { + ts_err("Send large cfg FAILED, reg:0x%04x is not 0x82", + command_reg); + r = -EINVAL; + goto exit; + } + + /*4. write cfg*/ + if (goodix_i2c_write(dev, cfg_reg, config->data, config->length)) { + ts_err("Send large cfg FAILED, write cfg to fw ERROR"); + r = -EINVAL; + goto exit; + } + + /*5. send "end send cfg" command*/ + goodix_cmds_init(&ts_cmd, COMMAND_END_SEND_CFG, 0, dev->reg.command); + if (goodix_send_command(dev, &ts_cmd)) { + ts_err("Send large cfg FAILED, send COMMAND_END_SEND_CFG ERROR"); + r = -EINVAL; + goto exit; + } + + /*6. wait ic set command_reg to 0xff*/ + for (try_times = 0; try_times < TS_WAIT_CMD_FREE_RETRY_TIMES; + try_times++) { + if (!goodix_i2c_read(dev, command_reg, &buf, 1) && + buf == TS_CMD_REG_READY) + break; + usleep_range(10000, 11000); + } + if (try_times >= TS_WAIT_CMD_FREE_RETRY_TIMES) { + ts_err("Send large cfg FAILED, after send, reg:0x%04x is not 0xff", + command_reg); + r = -EINVAL; + goto exit; + } + + ts_info("Send large cfg SUCCESS"); + r = 0; + +exit: + return r; +} + +static int goodix_check_cfg_valid(struct goodix_ts_device *dev, u8 *cfg, + u32 length) +{ + int ret; + u8 bag_num; + u8 checksum; + int i, j; + int bag_start = 0; + int bag_end = 0; + if (!cfg || length < TS_CFG_HEAD_LEN) { + ts_err("cfg is INVALID, len:%d", length); + ret = -EINVAL; + goto exit; + } + + if (dev->ic_type == IC_TYPE_NANJING) { + /*check configuration head checksum*/ + checksum = 0; + for (i = 0; i < 3; i++) + checksum += cfg[i]; + + if (checksum != 0) { + ts_err("cfg head checksum ERROR, ic type:nanjing, checksum:0x%02x", + checksum); + ret = -EINVAL; + goto exit; + } + bag_num = cfg[1]; + bag_start = 3; + } else if (dev->ic_type == IC_TYPE_NORMANDY) { + checksum = 0; + for (i = 0; i < TS_CFG_HEAD_LEN; i++) + checksum += cfg[i]; + if (checksum != 0) { + ts_err("cfg head checksum ERROR, ic type:normandy, checksum:0x%02x", + checksum); + ret = -EINVAL; + goto exit; + } + bag_num = cfg[TS_CFG_BAG_NUM_INDEX]; + bag_start = TS_CFG_BAG_START_INDEX; + } else { + ts_err("cfg check FAILED, unkonw ic_type"); + ret = -EINVAL; + goto exit; + } + + ts_info("cfg bag_num:%d, cfg length:%d", bag_num, length); + + /*check each bag's checksum*/ + for (j = 0; j < bag_num; j++) { + if (bag_start >= length - 1) { + ts_err("ERROR, overflow!!bag_start:%d, cfg_len:%d", + bag_start, length); + ret = -EINVAL; + goto exit; + } + + bag_end = bag_start + cfg[bag_start + 1] + 3; + if ((j == 0) && (dev->ic_type == IC_TYPE_NANJING)) + /*the first bag of nanjing cfg is different!*/ + bag_end = 336; + + checksum = 0; + if (bag_end > length) { + ts_err("ERROR, overflow!!bag:%d, bag_start:%d, bag_end:%d, cfg length:%d", + j, bag_start, bag_end, length); + ret = -EINVAL; + goto exit; + } + for (i = bag_start; i < bag_end; i++) + checksum += cfg[i]; + if (checksum != 0) { + ts_err("cfg INVALID, bag:%d checksum ERROR:0x%02x", j, + checksum); + ret = -EINVAL; + goto exit; + } + bag_start = bag_end; + } + + ret = 0; + ts_info("configuration check SUCCESS"); + +exit: + return ret; +} + +static int goodix_send_config(struct goodix_ts_device *dev, + struct goodix_ts_config *config) +{ + int r = 0; + + /*check reg valid*/ + /* if (!dev->reg.cfg_addr) { + ts_err("cfg register is NULL"); + return -EINVAL; + }*/ + if (!config || !*(config->data)) { + ts_err("Null config data"); + return -EINVAL; + } + + /*check configuration valid*/ + r = goodix_check_cfg_valid(dev, config->data, config->length); + if (r != 0) { + ts_err("cfg check FAILED"); + return -EINVAL; + } + + ts_info("ver:%02xh,size:%d", config->data[0], config->length); + + mutex_lock(&config->lock); + + if (dev->ic_type == IC_TYPE_NANJING) + r = goodix_send_large_config(dev, config); + else if (dev->ic_type == IC_TYPE_NORMANDY) { + /*disable doze mode*/ + goodix_set_i2c_doze_mode(dev, false); + + if (config->length > 32) + r = goodix_send_large_config(dev, config); + else + r = goodix_send_small_config(dev, config); + + /*enable doze mode*/ + goodix_set_i2c_doze_mode(dev, true); + } + + if (r != 0) + ts_err("send_cfg FAILED, ic_type:%d, cfg_len:%d", dev->ic_type, + config->length); + + mutex_unlock(&config->lock); + return r; +} + +#if 0 +/** + * goodix_send_config - send config data to device. + * @dev: pointer to device + * @config: pointer to config data struct to be send + * @return: 0 - succeed, < 0 - failed + */ +static int goodix_send_config(struct goodix_ts_device *dev, + struct goodix_ts_config *config) +{ + int r = 0; + + if (!config || !config->data) { + ts_err("Null config data"); + return -EINVAL; + } + + ts_info("Send %s,ver:%02xh,size:%d", + config->name, config->data[0], + config->length); + + mutex_lock(&config->lock); + r = goodix_i2c_write(dev, config->reg_base, + config->data, config->length); + if (r) + goto exit; + + /* make sure the firmware accept the config data*/ + if (config->delay) + msleep(config->delay); +exit: + mutex_unlock(&config->lock); + return r; +} +#endif + +/** + * goodix_close_hidi2c_mode + * Called by touch core module when bootup + * @ts_dev: pointer to touch device + * return: 0 - no error, <0 error +*/ +static int goodix_close_hidi2c_mode(struct goodix_ts_device *ts_dev) +{ + int r = 0; + int try_times; + int j; + unsigned char buffer[1]; + unsigned char reg_sta; + struct goodix_ts_cmd ts_cmd; + + for (try_times = 0; try_times < 10; try_times++) { + if (goodix_i2c_read(ts_dev, 0x8040, ®_sta, 1) != 0) + continue; + else if (reg_sta == 0xff) + break; + usleep_range(10000, 11000); + } + if (try_times >= 10) { + ts_info("goodix_close_hidi2c_mode FAILED, 0x8040 is not equal to 0xff"); + return -EINVAL; + } + + goodix_cmds_init(&ts_cmd, COMMAND_CLOSE_HID, 0, 0x8040); + for (try_times = 0; try_times < 3; try_times++) { + if (ts_cmd.initialized) { + r = goodix_send_command(ts_dev, &ts_cmd); + if (r) + continue; + + usleep_range(100000, 110000); + + /*read 0x8040, if it's not 0xFF,continue*/ + for (j = 0; j < 3; j++) { + if (goodix_i2c_read(ts_dev, 0x8040, buffer, + 1) != 0) + continue; + else { + if (buffer[0] != 0xFF) { + ts_info("try_times:%d:%d, read 0x8040:0x%02x", + try_times, j, + buffer[0]); + usleep_range(10000, 11000); + continue; + } else + goto exit; + } + } + } + } + +exit: + if (try_times >= 3) { + ts_info("close hid_i2c mode FAILED"); + r = -EINVAL; + } else { + ts_info("close hid_i2c mode SUCCESS"); + r = 0; + } + return r; +} + +/* success return config length else return -1 */ +static int _goodix_do_read_config(struct goodix_ts_device *dev, u32 base_addr, + u8 *buf) +{ + int sub_bags = 0; + int offset = 0; + int subbag_len; + u8 checksum; + int i; + int ret; + + /*disable doze mode*/ + if (dev->ic_type == IC_TYPE_NORMANDY) + goodix_set_i2c_doze_mode(dev, false); + + ret = goodix_i2c_read(dev, base_addr, buf, TS_CFG_HEAD_LEN); + if (ret) + goto err_out; + + if (dev->ic_type == IC_TYPE_NANJING) { + offset = 3; + sub_bags = buf[1]; + checksum = checksum_u8(buf, 3); + } else { + offset = TS_CFG_BAG_START_INDEX; + sub_bags = buf[TS_CFG_BAG_NUM_INDEX]; + checksum = checksum_u8(buf, TS_CFG_HEAD_LEN); + } + if (checksum) { + ts_err("Config head checksum err:0x%x,data:%*ph", checksum, + TS_CFG_HEAD_LEN, buf); + ret = -EINVAL; + goto err_out; + } + + ts_info("config_version:%u, vub_bags:%u", buf[0], sub_bags); + for (i = 0; i < sub_bags; i++) { + /* read sub head [0]: sub bag num, [1]: sub bag length */ + ret = goodix_i2c_read(dev, base_addr + offset, buf + offset, 2); + if (ret) + goto err_out; + + /* read sub bag data */ + if (dev->ic_type == IC_TYPE_NANJING && i == 0) + subbag_len = buf[offset + 1] + 256; + else + subbag_len = buf[offset + 1]; + + ts_info("sub bag num:%u,sub bag length:%u", buf[offset], + subbag_len); + ret = goodix_i2c_read(dev, base_addr + offset + 2, + buf + offset + 2, subbag_len + 1); + if (ret) + goto err_out; + checksum = checksum_u8(buf + offset, subbag_len + 3); + if (checksum) { + ts_err("sub bag checksum err:0x%x", checksum); + ret = -EINVAL; + goto err_out; + } + offset += subbag_len + 3; + ts_debug("sub bag %d, data:%*ph", buf[offset], + buf[offset + 1] + 3, buf + offset); + } + ret = offset; + +err_out: + /*enable doze mode*/ + if (dev->ic_type == IC_TYPE_NORMANDY) + goodix_set_i2c_doze_mode(dev, true); + + return ret; +} + +/* success return config_len, <= 0 failed */ +static int goodix_read_config(struct goodix_ts_device *dev, u8 *config_data, + u32 config_len) +{ + struct goodix_ts_cmd ts_cmd; + u8 cmd_flag; + u32 cmd_reg = dev->reg.command; + int r = 0; + int i; + + if (!config_data || config_len > TS_CFG_MAX_LEN) { + ts_err("Illegal params"); + return -EINVAL; + } + if (!dev->reg.command) { + ts_err("command register ERROR:0x%04x", dev->reg.command); + return -EINVAL; + } + + /*disable doze mode*/ + if (dev->ic_type == IC_TYPE_NORMANDY) + goodix_set_i2c_doze_mode(dev, false); + + /* wait for IC in IDLE state */ + for (i = 0; i < TS_WAIT_CMD_FREE_RETRY_TIMES; i++) { + cmd_flag = 0; + r = goodix_i2c_read(dev, cmd_reg, &cmd_flag, 1); + if (r < 0 || cmd_flag == TS_CMD_REG_READY) + break; + usleep_range(10000, 11000); + } + if (cmd_flag != TS_CMD_REG_READY) { + ts_err("Wait for IC ready IDEL state timeout:addr 0x%x\n", + cmd_reg); + r = -EAGAIN; + goto exit; + } + /* 0x86 read config command */ + goodix_cmds_init(&ts_cmd, COMMAND_START_READ_CFG, 0, cmd_reg); + r = goodix_send_command(dev, &ts_cmd); + if (r) { + ts_err("Failed send read config command"); + goto exit; + } + /* wait for config data ready */ + if (goodix_wait_cfg_cmd_ready(dev, COMMAND_READ_CFG_PREPARE_OK, + COMMAND_START_READ_CFG)) { + ts_err("Wait for config data ready timeout"); + r = -EAGAIN; + goto exit; + } + if (config_len) { + r = goodix_i2c_read(dev, cmd_reg + 16, config_data, config_len); + if (r) + ts_err("Failed read config data"); + else + r = config_len; + } else { + r = _goodix_do_read_config(dev, cmd_reg + 16, config_data); + if (r < 0) + ts_err("Failed read config data"); + } + if (r > 0) + ts_info("success read config, len:%d", r); + /* clear command */ + goodix_cmds_init(&ts_cmd, TS_CMD_REG_READY, 0, cmd_reg); + goodix_send_command(dev, &ts_cmd); + + /*enable doze mode*/ + if (dev->ic_type == IC_TYPE_NORMANDY) + goodix_set_i2c_doze_mode(dev, true); + +exit: + return r; +} + +/** + * goodix_hw_init - hardware initialize + * Called by touch core module when bootup + * @ts_dev: pointer to touch device + * return: 0 - no error, <0 error +*/ +static int goodix_hw_init(struct goodix_ts_device *ts_dev) +{ + int r; + + BUG_ON(!ts_dev); + ts_info("goodix_hw_init"); + /* goodix_hw_init may be called many times */ + if (!ts_dev->normal_cfg) { + ts_dev->normal_cfg = devm_kzalloc( + ts_dev->dev, sizeof(*ts_dev->normal_cfg), GFP_KERNEL); + if (!ts_dev->normal_cfg) { + ts_err("Failed to alloc memory for normal cfg"); + return -ENOMEM; + } + mutex_init(&ts_dev->normal_cfg->lock); + } + if (!ts_dev->highsense_cfg) { + ts_dev->highsense_cfg = devm_kzalloc( + ts_dev->dev, sizeof(*ts_dev->highsense_cfg), + GFP_KERNEL); + if (!ts_dev->highsense_cfg) { + ts_err("Failed to alloc memory for high sense cfg"); + return -ENOMEM; + } + mutex_init(&ts_dev->highsense_cfg->lock); + } + + /*for Nanjing IC, close HID_I2C mode when driver is probed*/ + if (ts_dev->ic_type == IC_TYPE_NANJING) { + r = goodix_close_hidi2c_mode(ts_dev); + if (r < 0) + ts_info("close hid i2c mode FAILED"); + } + + /* read chip version: PID/VID/sensor ID,etc.*/ + r = goodix_read_version(ts_dev, &ts_dev->chip_version); + if (r < 0) + return r; + + /* devicetree property like resolution(panel_max_xxx) + * may be different between sensors, here we try to parse + * parameters form sensor child node */ + r = goodix_parse_customize_params(ts_dev, ts_dev->board_data, + ts_dev->chip_version.sensor_id); + if (r < 0) + ts_info("Cann't find customized parameters"); + + ts_dev->normal_cfg->delay = 500; + /* send normal-cfg to firmware */ + r = goodix_send_config(ts_dev, ts_dev->normal_cfg); + + return r; +} + +/** + * goodix_hw_reset - reset device + * + * @dev: pointer to touch device + * Returns 0 - succeed,<0 - failed + */ +int goodix_hw_reset(struct goodix_ts_device *dev) +{ + u8 data[2] = { 0x00 }; + int r = 0; + + ts_info("HW reset"); + ts_info("ic_type = %d\n", dev->ic_type); + dev->ic_type = IC_TYPE_NORMANDY; + if (dev->ic_type == IC_TYPE_NORMANDY) { + ts_info("touchpanel normandy reset"); + //gpio_direction_output(dev->board_data->reset_gpio, 1); + //msleep(10); + gpio_direction_output(dev->board_data->reset_gpio, 0); + udelay(2000); + gpio_direction_output(dev->board_data->reset_gpio, 1); + msleep(100); + } else if (dev->ic_type == IC_TYPE_NANJING) { + ts_info("nanjing reset"); + + /*close watch dog*/ + data[0] = 0; + goodix_i2c_write(dev, 0x40b0, data, 1); + msleep(10); + + /*soft reset*/ + data[0] = 1; + goodix_i2c_write_trans_once(dev, 0x4180, data, 1); + msleep(250); + goodix_close_hidi2c_mode(dev); + + /*clear coor_reg*/ + data[0] = 0; + data[1] = 0; + goodix_i2c_write(dev, 0x824d, data, 2); + } + + /*init static esd*/ + data[0] = GOODIX_ESD_TICK_WRITE_DATA; + if (dev->ic_type == IC_TYPE_NANJING) { + r = goodix_i2c_write(dev, 0x8043, data, 1); + if (r < 0) + ts_err("nanjing reset, init static esd FAILED, i2c wirte ERROR"); + } + + /*init dynamic esd*/ + if (dev->reg.esd) { + r = goodix_i2c_write_trans(dev, dev->reg.esd, data, 1); + if (r < 0) + ts_err("IC reset, init dynamic esd FAILED, i2c write ERROR"); + } else + ts_info("reg.esd is NULL, skip dynamic esd init"); + + return 0; +} + +/** + * goodix_request_handler - handle firmware request + * + * @dev: pointer to touch device + * @request_data: requset information + * Returns 0 - succeed,<0 - failed + */ +static int goodix_request_handler(struct goodix_ts_device *dev, + struct goodix_request_data *request_data) +{ + unsigned char buffer[1]; + int r; + + if (dev->reg.fw_request != 0x6F6D) { + ts_info("firmware reg is wrong!\n"); + dev->reg.fw_request = 0x6F6D; + } + r = goodix_i2c_read_trans(dev, dev->reg.fw_request, buffer, + 1); /*TS_REG_REQUEST*/ + if (r < 0) + return r; + + switch (buffer[0]) { + case REQUEST_CONFIG: + ts_info("HW request config"); + goodix_send_config(dev, dev->normal_cfg); + goto clear_requ; + break; + case REQUEST_BAKREF: + ts_info("HW request bakref"); + goto clear_requ; + break; + case REQUEST_RESET: + ts_info("HW requset reset"); + goto clear_requ; + break; + case REQUEST_MAINCLK: + ts_info("HW request mainclk"); + goto clear_requ; + break; + default: + ts_info("Unknown hw request:%d", buffer[0]); + return 0; + } + +clear_requ: + buffer[0] = 0x00; + r = goodix_i2c_write_trans(dev, dev->reg.fw_request, buffer, + 1); /*TS_REG_REQUEST*/ + return r; +} + +/*goodix_swap_coords - swap coord + */ + +static void goodix_swap_coords(struct goodix_ts_device *dev, + struct goodix_ts_coords *coords, int touch_num) +{ + int i, temp; + struct goodix_ts_board_data *bdata = dev->board_data; + for (i = 0; i < touch_num; i++) { + if (bdata->swap_axis) { + temp = coords->x; + coords->x = coords->y; + coords->y = temp; + } + if (bdata->x2x) + coords->x = bdata->panel_max_x - coords->x; + if (bdata->y2y) + coords->y = bdata->panel_max_y - coords->y; + coords++; + } +} + +static int goodix_remap_trace_id(struct goodix_ts_device *dev, u8 *coor_buf, + u32 coor_buf_len, int touch_num) +{ + static u8 remap_array[20] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + int i, j; + int offset = 0; + bool need_leave = false; + bool need_add = false; + u8 temp_buf[BYTES_PER_COORD] = { 0x00 }; + u8 *small; + bool need_swap = false; + int max_touch_num = dev->board_data->panel_max_id; + + if (touch_num > dev->board_data->panel_max_id) { + ts_err("touch num error, trace id no remap:%d", touch_num); + return 0; + } + + if (!coor_buf || coor_buf_len > (2 + BYTES_PER_COORD * max_touch_num)) { + ts_err("touch data buff error, !coor_buf:%d, len:%d", !coor_buf, + coor_buf_len); + return 0; + } + + /*clear and reset remap_array*/ + if (touch_num == 0) { + for (i = 0; i < sizeof(remap_array); i++) + remap_array[i] = 0xff; + return 0; + } + + /*find and add new point*/ + offset = 0; + for (i = 0; i < touch_num; i++) { + need_add = true; + for (j = 0; j < sizeof(remap_array); j++) { + if (coor_buf[offset] == remap_array[j]) { + need_add = false; + break; + } + } + if (need_add == true) { + for (j = 0; j < sizeof(remap_array); j++) { + if (remap_array[j] == 0xff) { + remap_array[j] = coor_buf[offset]; + break; + } + } + } + offset += BYTES_PER_COORD; + } + + /*scan remap_array, find and remove leave point*/ + for (i = 0; i < sizeof(remap_array); i++) { + if (remap_array[i] == 0xff) + continue; + else { + need_leave = true; + offset = 0; + for (j = 0; j < touch_num; j++) { + if (remap_array[i] == coor_buf[offset]) { + need_leave = false; + break; + } + offset += BYTES_PER_COORD; + } + if (need_leave == true) { + /*ts_info("---leave, trace id:%d:%d", remap_array[i], i);*/ + remap_array[i] = 0xff; + } + } + } + + /*remap trace id*/ + offset = 0; + for (i = 0; i < touch_num; i++) { + /*do not remap pen's trace ID*/ + if (coor_buf[offset] >= 0x80) { + offset += BYTES_PER_COORD; + continue; + } else { + for (j = 0; j < sizeof(remap_array); j++) { + if (remap_array[j] == coor_buf[offset]) { + /*ts_info("***remap, %d--->%d", coor_buf[offset], j);*/ + coor_buf[offset] = j; + break; + } + } + if (j >= sizeof(remap_array)) { + ts_err("remap ERROR!!trace id:%d", + coor_buf[offset]); + ts_err("remap_array:%*ph", + (int)sizeof(remap_array), remap_array); + } + offset += BYTES_PER_COORD; + } + } + + /*for (i = 0; i < touch_num; i++) { + ts_info("remap data%d:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x", + i, coor_buf[i * 8], coor_buf[i * 8 + 1], + coor_buf[i * 8 + 2], coor_buf[i * 8 + 3], + coor_buf[i * 8 + 4], coor_buf[i * 8 + 5], + coor_buf[i * 8 + 6], coor_buf[i * 8 + 7]); + }*/ + + /*realign coor data by new trace ID*/ + for (i = 0; i < touch_num - 1; i++) { + small = &coor_buf[BYTES_PER_COORD * i]; + need_swap = false; + for (j = i + 1; j < touch_num; j++) { + if (coor_buf[BYTES_PER_COORD * j] < *small) { + need_swap = true; + small = &coor_buf[BYTES_PER_COORD * j]; + } + } + /*swap*/ + if (need_swap) { + memcpy(temp_buf, small, BYTES_PER_COORD); + memcpy(small, &coor_buf[BYTES_PER_COORD * i], + BYTES_PER_COORD); + memcpy(&coor_buf[BYTES_PER_COORD * i], temp_buf, + BYTES_PER_COORD); + } + } + + /*for (i = 0; i < touch_num; i++) { + ts_info("final data%d:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x", + i, coor_buf[i * 8], coor_buf[i * 8 + 1], + coor_buf[i * 8 + 2], coor_buf[i * 8 + 3], + coor_buf[i * 8 + 4], coor_buf[i * 8 + 5], + coor_buf[i * 8 + 6], coor_buf[i * 8 + 7]); + }*/ + + return 0; +} + +/** + * goodix_event_handler - handle firmware event + * + * @dev: pointer to touch device + * @ts_event: pointer to touch event structure + * Returns 0 - succeed,<0 - failed + */ + +static int goodix_touch_handler(struct goodix_ts_device *dev, + struct goodix_ts_event *ts_event, u8 *pre_buf, + u32 pre_buf_len) +{ + struct goodix_touch_data *touch_data = &ts_event->event_data.touch_data; + struct goodix_ts_coords *coords = &(touch_data->coords[0]); + int max_touch_num = dev->board_data->panel_max_id; + unsigned char buffer[4 + BYTES_PER_COORD * max_touch_num]; + unsigned char coord_sta; + int touch_num = 0, i, r; + unsigned char chksum = 0; + + if (!pre_buf || pre_buf_len != (4 + BYTES_PER_COORD)) { + r = -EINVAL; + return r; + } + + /*copy data to buffer*/ + memcpy(buffer, pre_buf, pre_buf_len); + + /* buffer[1]: touch state */ + coord_sta = buffer[1]; + + touch_num = coord_sta & 0x0F; + + if (unlikely(touch_num > max_touch_num)) { + touch_num = -EINVAL; + goto exit_clean_sta; + } else if (unlikely(touch_num > 1)) { + r = goodix_i2c_read_trans( + dev, + dev->reg.coor + 4 + + BYTES_PER_COORD, /*TS_REG_COORDS_BASE*/ + &buffer[4 + BYTES_PER_COORD], + (touch_num - 1) * BYTES_PER_COORD); + if (unlikely(r < 0)) + goto exit_clean_sta; + } + + /* touch_num * BYTES_PER_COORD + 1(touch event state) + * + 1(checksum) + 1(key value) */ + if (dev->ic_type == IC_TYPE_NANJING) { + chksum = checksum_u8(&buffer[1], + touch_num * BYTES_PER_COORD + 3); + } else { + chksum = checksum_u8(&buffer[0], + touch_num * BYTES_PER_COORD + 4); + } + if (unlikely(chksum != 0)) { + ts_err("Checksum error:%X, ic_type:%d", chksum, dev->ic_type); + r = -EINVAL; + goto exit_clean_sta; + } + + touch_data->have_key = false; /*clear variable*/ + touch_data->key_value = 0; /*clear variable*/ + touch_data->have_key = (coord_sta >> 4) & 0x01; + if (unlikely(touch_data->have_key)) { + touch_data->key_value = buffer[touch_num * BYTES_PER_COORD + 2]; + if (dev->board_data->pen_enable) + touch_data->key_value = + (touch_data->key_value & 0x0f) | + ((touch_data->key_value & 0xf0) >> + (4 - dev->board_data->tp_key_num)); + } + /*ts_info("$$$$$$coord_sta:0x%02x, have_key:%d, key_value:0x%02x", + coord_sta, touch_data->have_key, touch_data->key_value);*/ + + /*for (i = 0; i < touch_num; i++) { + ts_info("raw coor data%d:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x", + i, buffer[i * 8 + 2], buffer[i * 8 + 3], + buffer[i * 8 + 4], buffer[i * 8 + 5], + buffer[i * 8 + 6], buffer[i * 8 + 7], + buffer[i * 8 + 8], buffer[i * 8 + 9]); + }*/ + + /*add end*/ + + /*remap trace id*/ + if (dev->ic_type == IC_TYPE_NANJING) + goodix_remap_trace_id(dev, &buffer[2], + 2 + BYTES_PER_COORD * max_touch_num, + touch_num); + + /*clear buffer*/ + memset(touch_data->coords, 0x00, sizeof(touch_data->coords)); + memset(touch_data->pen_coords, 0x00, sizeof(touch_data->pen_coords)); + + if (likely(touch_num >= 1)) { + /*"0 ~ touch_num - 2" is finger, "touch_num - 1" may be a finger or a pen*/ + /*process "0 ~ touch_num -2"*/ + for (i = 0; i < touch_num - 1; i++) { + coords->id = buffer[i * BYTES_PER_COORD + 2] & 0x0f; + coords->x = buffer[i * BYTES_PER_COORD + 3] | + (buffer[i * BYTES_PER_COORD + 4] << 8); + coords->y = buffer[i * BYTES_PER_COORD + 5] | + (buffer[i * BYTES_PER_COORD + 6] << 8); + coords->w = buffer[i * BYTES_PER_COORD + 7]; + coords->p = coords->w; + coords->overlapping_area = buffer[8]; + coords->area = buffer[i * BYTES_PER_COORD + 9]; + coords++; + } + + /*process "touch_num - 1", it may be a finger or a pen*/ + /*it's a pen*/ + i = touch_num - 1; + //ts_err("%s:i=%d touch_num=%d\n",__func__,i,touch_num); + if (unlikely(touch_num >= 1 && + buffer[i * BYTES_PER_COORD + 2] >= 0x80)) { + if (dev->board_data->pen_enable) { /*pen_enable*/ + touch_data->pen_down = true; + /*change pen's trace ID, let it equal to "panel_max_id - 1"*/ + /*touch_data->pen_coords[0].id = dev->board_data->panel_max_id - 1;*/ + touch_data->pen_coords[0].id = + dev->board_data->panel_max_id * 2; + touch_data->pen_coords[0].x = + buffer[i * BYTES_PER_COORD + 3] | + (buffer[i * BYTES_PER_COORD + 4] << 8); + touch_data->pen_coords[0].y = + buffer[i * BYTES_PER_COORD + 5] | + (buffer[i * BYTES_PER_COORD + 6] << 8); + touch_data->pen_coords[0].w = + buffer[i * BYTES_PER_COORD + 7]; + touch_data->pen_coords[0].p = + touch_data->pen_coords[0].w; + } + } else { /*it's a finger*/ + coords->id = buffer[i * BYTES_PER_COORD + 2] & 0x0f; + coords->x = buffer[i * BYTES_PER_COORD + 3] | + (buffer[i * BYTES_PER_COORD + 4] << 8); + coords->y = buffer[i * BYTES_PER_COORD + 5] | + (buffer[i * BYTES_PER_COORD + 6] << 8); + coords->w = buffer[i * BYTES_PER_COORD + 7]; + coords->p = coords->w; + coords->overlapping_area = buffer[8]; + coords->area = buffer[i * BYTES_PER_COORD + 9]; + /*ts_debug("EF:[%d](%d, %d)", coords->id, coords->x, coords->y);*/ + if (touch_data->pen_down == true) { + touch_data->pen_down = false; + /*ts_info("***pen leave");*/ + } + } + } + + /*swap coord*/ + goodix_swap_coords(dev, &touch_data->coords[0], touch_num); + goodix_swap_coords(dev, &touch_data->pen_coords[0], 1); + + touch_data->touch_num = touch_num; + /* mark this event as touch event */ + ts_event->event_type = EVENT_TOUCH; + r = 0; + +exit_clean_sta: + /* handshake */ + /*buffer[0] = 0x00;*/ + /*goodix_i2c_write_trans(dev, dev->reg.coor, buffer, 1);*/ + return r; +} + +static int goodix_event_handler(struct goodix_ts_device *dev, + struct goodix_ts_event *ts_event) +{ + unsigned char pre_buf[4 + BYTES_PER_COORD]; + unsigned char event_sta; + struct i2c_client *client = to_i2c_client(dev->dev); + struct goodix_ts_core *core_data = i2c_get_clientdata(client); + int r; + + /*memset(pre_buf, 0, sizeof(pre_buf));*/ + + r = goodix_i2c_read_trans(dev, dev->reg.coor, pre_buf, + 4 + BYTES_PER_COORD); + if (unlikely(r < 0)) + return r; + + /* buffer[0]: event state */ + core_data->event_status = pre_buf[0]; + event_sta = pre_buf[0]; + + if (likely((event_sta & GOODIX_TOUCH_EVENT) == GOODIX_TOUCH_EVENT)) { + /*handle touch event*/ + goodix_touch_handler(dev, ts_event, pre_buf, + 4 + BYTES_PER_COORD); + } else if (unlikely((event_sta & GOODIX_REQUEST_EVENT) == + GOODIX_REQUEST_EVENT)) { + /* handle request event */ + ts_event->event_type = EVENT_REQUEST; + goodix_request_handler(dev, &ts_event->event_data.request_data); + } else if ((event_sta & GOODIX_GESTURE_EVENT) == GOODIX_GESTURE_EVENT) { + /* handle gesture event */ + ts_info("Gesture event"); + } else if ((event_sta & GOODIX_HOTKNOT_EVENT) == GOODIX_HOTKNOT_EVENT) { + /* handle hotknot event */ + ts_info("Hotknot event"); + } else { + ts_info("unknow event type:%02x", event_sta); + r = -EINVAL; + } + + return r; +} + +/** + * goodix_hw_suspend - Let touch deivce stay in lowpower mode. + * @dev: pointer to goodix touch device + * @return: 0 - succeed, < 0 - failed + */ +static int goodix_hw_suspend(struct goodix_ts_device *dev) +{ + struct goodix_ts_cmd sleep_cmd; + int r = 0; + + goodix_cmds_init(&sleep_cmd, COMMAND_SLEEP, 0, dev->reg.command); + if (sleep_cmd.initialized) { + r = goodix_send_command(dev, &sleep_cmd); + if (!r) + ts_info("Chip in sleep mode"); + } else + ts_err("Uninitialized sleep command"); + + return r; +} + +/** + * goodix_hw_resume - Let touch deivce stay in active mode. + * @dev: pointer to goodix touch device + * @return: 0 - succeed, < 0 - failed + */ +static int goodix_hw_resume(struct goodix_ts_device *dev) +{ + int r = 0, i, retry = GOODIX_BUS_RETRY_TIMES; + u8 temp_buf[256], checksum; + u8 data[2] = { 0x00 }; + + for (; retry > 0; retry--) { + /*resume IC*/ + if (dev->ic_type == IC_TYPE_NORMANDY) + goodix_hw_reset(dev); + else if (dev->ic_type == IC_TYPE_NANJING) { + /*1. read 0x8000 to resume nanjing*/ + goodix_i2c_read(dev, 0x8000, data, 1); + msleep(150); + /*2. check resume success or not*/ + for (i = 0; i < 10; i++) { + r = goodix_i2c_read(dev, dev->reg.command, data, + 1); + if (!r && data[0] == 0xff) + break; + msleep(20); + } + + if (i >= 10) { + ts_err("resume nanjing failed, after read 0x8000, 0x8040 not equal 0xff"); + continue; + } + /*3. close hid i2c*/ + goodix_close_hidi2c_mode(dev); + + /*4. clear coor*/ + data[0] = 0; + data[1] = 0; + goodix_i2c_write(dev, 0x824d, data, 2); + } + + /*read version and check checksum*/ + if (dev->reg.version_base && dev->reg.version_len < 256) { + r = goodix_i2c_read(dev, dev->reg.version_base, + temp_buf, dev->reg.version_len); + if (r < 0) + continue; + + checksum = checksum_u8(temp_buf, dev->reg.version_len); + if (!checksum) { + ts_info("read version SUCCESS"); + break; + } + } + } + return r; +} + +static int goodix_esd_check(struct goodix_ts_device *dev) +{ + int r; + u8 data = 0; + + if (dev->reg.esd == 0) { + ts_err("esd reg is NULL"); + return 0; + } + + /*check dynamic esd*/ + if (dev->ic_type == IC_TYPE_NORMANDY) + r = dev->hw_ops->read_trans(dev, TS_REG_ESD_TICK_R, &data, 1); + else + r = dev->hw_ops->read_trans(dev, dev->reg.esd, &data, 1); + + if (r < 0 || (data == GOODIX_ESD_TICK_WRITE_DATA)) { + ts_info("dynamic esd occur, r:%d, data:0x%02x", r, data); + r = -EINVAL; + goto exit; + } + + /*check static esd*/ + if (dev->ic_type == IC_TYPE_NANJING) { + r = dev->hw_ops->read_trans(dev, 0x8043, &data, 1); + + if (r < 0 || (data != 0xaa)) { + ts_info("static esd occur, r:%d, data:0x%02x", r, data); + r = -EINVAL; + goto exit; + } + } + +exit: + return r; +} + +/* hardware opeation funstions */ +static const struct goodix_ts_hw_ops hw_i2c_ops = { + .init = goodix_hw_init, + .read = goodix_i2c_read, + .write = goodix_i2c_write, + .read_trans = goodix_i2c_read_trans, + .write_trans = goodix_i2c_write_trans, + .reset = goodix_hw_reset, + .event_handler = goodix_event_handler, + .send_config = goodix_send_config, + .read_config = goodix_read_config, + .send_cmd = goodix_send_command, + .read_version = goodix_read_version, + .suspend = goodix_hw_suspend, + .resume = goodix_hw_resume, + .check_hw = goodix_esd_check, +}; + +static struct platform_device *goodix_pdev; + +static void goodix_pdev_release(struct device *dev) +{ + kfree(goodix_pdev); + return; +} + +static int goodix_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *dev_id) +{ + struct goodix_ts_device *ts_device = NULL; + struct goodix_ts_board_data *ts_bdata = NULL; + int r = 0; + + ts_err("enter::%s\n", __func__); + + r = i2c_check_functionality(client->adapter, I2C_FUNC_I2C); + if (!r) + return -EIO; + + /* board data */ + ts_bdata = devm_kzalloc( + &client->dev, sizeof(struct goodix_ts_board_data), GFP_KERNEL); + if (!ts_bdata) + return -ENOMEM; + + if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { + /* parse devicetree property */ + r = goodix_parse_dt(client->dev.of_node, ts_bdata); + if (r < 0) + return r; + } +#ifdef CONFIG_ACPI + else if (ACPI_COMPANION(&client->dev)) { + r = goodix_parse_acpi(&client->dev, ts_bdata); + if (r < 0) + return r; + } +#endif + else { + /* use platform data */ + devm_kfree(&client->dev, ts_bdata); + ts_bdata = client->dev.platform_data; + } + + if (!ts_bdata) + return -ENODEV; + + ts_device = devm_kzalloc(&client->dev, sizeof(struct goodix_ts_device), + GFP_KERNEL); + if (!ts_device) + return -ENOMEM; + + ts_device->name = "GTx5 TouchDevcie"; + ts_device->dev = &client->dev; + ts_device->board_data = ts_bdata; + ts_device->hw_ops = &hw_i2c_ops; + + /* ts core device */ + goodix_pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL); + if (!goodix_pdev) + return -ENOMEM; + + goodix_pdev->name = GOODIX_CORE_DRIVER_NAME; + goodix_pdev->id = 0; + goodix_pdev->num_resources = 0; + /* + * you could find this platform dev in + * /sys/devices/platfrom/goodix_ts.0 + * goodix_pdev->dev.parent = &client->dev; + */ + goodix_pdev->dev.platform_data = ts_device; + goodix_pdev->dev.release = goodix_pdev_release; + + /* register platform device, then the goodix_ts_core + * module will probe the touch deivce. */ + r = platform_device_register(goodix_pdev); + + ts_info("goodix9886_i2c_probe OUT"); + + return r; +} + +static int goodix_i2c_remove(struct i2c_client *client) +{ + platform_device_unregister(goodix_pdev); + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id i2c_matchs[] = { + { + .compatible = TS_DT_COMPATIBLE, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, i2c_matchs); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id acpi_matchs[] = { + { .id = "PNPxxx" }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, acpi_matchs); +#endif + +static const struct i2c_device_id i2c_id_table[] = { + { TS_DRIVER_NAME, 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, i2c_id_table); + +static struct i2c_driver goodix_i2c_driver = { + .driver = { + .name = TS_DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(i2c_matchs), +#ifdef CONFIG_ACPI + .acpi_match_table = acpi_matchs, +#endif + }, + .probe = goodix_i2c_probe, + .remove = goodix_i2c_remove, + .id_table = i2c_id_table, +}; + +static int __init goodix_i2c_init(void) +{ + ts_info("GTx5xx HW layer init"); + return i2c_add_driver(&goodix_i2c_driver); +} + +static void __exit goodix_i2c_exit(void) +{ + i2c_del_driver(&goodix_i2c_driver); + return; +} + +module_init(goodix_i2c_init); +module_exit(goodix_i2c_exit); + +MODULE_DESCRIPTION("Goodix GTx5 Touchscreen Hardware Module"); +MODULE_AUTHOR("Goodix, Inc."); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_tools.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_tools.c new file mode 100644 index 000000000000..cd6387d57709 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_tools.c @@ -0,0 +1,722 @@ +/* + * Goodix GTX5 tools Dirver + * + * Copyright (C) 2015 - 2016 Goodix, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * Authors: Wang Yafei + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be a reference + * to you, when you are integrating the GOODiX's CTP IC into your system, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "goodix_ts_core.h" + +#define GOODIX_TOOLS_NAME "gtp_tools" +#define GOODIX_TS_IOC_MAGIC 'G' +#define NEGLECT_SIZE_MASK (~(_IOC_SIZEMASK << _IOC_SIZESHIFT)) + +#define GTP_IRQ_ENABLE _IO(GOODIX_TS_IOC_MAGIC, 0) +#define GTP_DEV_RESET _IO(GOODIX_TS_IOC_MAGIC, 1) +#define GTP_SEND_COMMAND (_IOW(GOODIX_TS_IOC_MAGIC, 2, u8) & NEGLECT_SIZE_MASK) +#define GTP_SEND_CONFIG (_IOW(GOODIX_TS_IOC_MAGIC, 3, u8) & NEGLECT_SIZE_MASK) +#define GTP_ASYNC_READ (_IOR(GOODIX_TS_IOC_MAGIC, 4, u8) & NEGLECT_SIZE_MASK) +#define GTP_SYNC_READ (_IOR(GOODIX_TS_IOC_MAGIC, 5, u8) & NEGLECT_SIZE_MASK) +#define GTP_ASYNC_WRITE (_IOW(GOODIX_TS_IOC_MAGIC, 6, u8) & NEGLECT_SIZE_MASK) +#define GTP_READ_CONFIG (_IOW(GOODIX_TS_IOC_MAGIC, 7, u8) & NEGLECT_SIZE_MASK) +#define GTP_ESD_ENABLE _IO(GOODIX_TS_IOC_MAGIC, 8) +#define GTP_DRV_VERSION (_IOR(GOODIX_TS_IOC_MAGIC, 9, u8) & NEGLECT_SIZE_MASK) + +#define GOODIX_TS_IOC_MAXNR 10 + +#define IRQ_FALG (0x01 << 2) + +#define I2C_MSG_HEAD_LEN 20 +#define TS_REG_COORDS_BASE 0x4100 + +/* + * struct goodix_tools_data - goodix tools data message used in sync read + * @data: The buffer into which data is written + * @reg_addr: Slave device register start address to start read data + * @length: Number of data bytes in @data being read from slave device + * @filled: When buffer @data be filled will set this flag with 1, outhrwise 0 + * @list_head:Eonnet every goodix_tools_data struct into a list +*/ + +struct goodix_tools_data { + u32 reg_addr; + u32 length; + u8 *data; + bool filled; + struct list_head list; +}; + +/* + * struct goodix_tools_dev - goodix tools device struct + * @ts_core: The core data struct of ts driver + * @ops_mode: represent device work mode + * @rawdiffcmd: Set slave device into rawdata mode + * @normalcmd: Set slave device into normal mode + * @wq: Wait queue struct use in synchronous data read + * @mutex: Protect goodix_tools_dev +*/ +struct goodix_tools_dev { + struct goodix_ts_core *ts_core; + struct list_head head; + unsigned int ops_mode; + struct goodix_ts_cmd rawdiffcmd, normalcmd; + wait_queue_head_t wq; + struct mutex mutex; + atomic_t t_count; + struct goodix_ext_module module; +} *goodix_tools_dev; + +/* read data from i2c asynchronous, +** success return bytes read, else return <= 0 +*/ +static int async_read(struct goodix_tools_dev *dev, void __user *arg) +{ + u8 *databuf = NULL; + int ret = 0; + u32 reg_addr, length; + u8 i2c_msg_head[I2C_MSG_HEAD_LEN]; + struct goodix_ts_device *ts_dev = dev->ts_core->ts_dev; + const struct goodix_ts_hw_ops *hw_ops = ts_dev->hw_ops; + + ret = copy_from_user(&i2c_msg_head, arg, I2C_MSG_HEAD_LEN); + if (ret) { + ret = -EFAULT; + goto err_out; + } + reg_addr = i2c_msg_head[0] + (i2c_msg_head[1] << 8) + + (i2c_msg_head[2] << 16) + (i2c_msg_head[3] << 24); + length = i2c_msg_head[4] + (i2c_msg_head[5] << 8) + + (i2c_msg_head[6] << 16) + (i2c_msg_head[7] << 24); + + databuf = kzalloc(length, GFP_KERNEL); + if (!databuf) { + ts_err("Alloc memory failed"); + return -ENOMEM; + } + + if (!hw_ops->read_trans(ts_dev, reg_addr, databuf, length)) { + if (copy_to_user((u8 *)arg + I2C_MSG_HEAD_LEN, databuf, + length)) { + ret = -EFAULT; + ts_err("Copy_to_user failed"); + } else { + ret = length; + } + } else { + ret = -EBUSY; + ts_err("Read i2c failed"); + } +err_out: + kfree(databuf); + return ret; +} + +/* if success return config data length */ +static int read_config_data(struct goodix_ts_device *ts_dev, void __user *arg) +{ + int ret = 0; + u32 reg_addr, length; + u8 i2c_msg_head[I2C_MSG_HEAD_LEN]; + u8 *tmp_buf; + + ret = copy_from_user(&i2c_msg_head, arg, I2C_MSG_HEAD_LEN); + if (ret) { + ts_err("Copy data from user failed"); + return -EFAULT; + } + reg_addr = i2c_msg_head[0] + (i2c_msg_head[1] << 8) + + (i2c_msg_head[2] << 16) + (i2c_msg_head[3] << 24); + length = i2c_msg_head[4] + (i2c_msg_head[5] << 8) + + (i2c_msg_head[6] << 16) + (i2c_msg_head[7] << 24); + ts_info("read config,reg_addr=0x%x, length=%d", reg_addr, length); + tmp_buf = kzalloc(length, GFP_KERNEL); + if (!tmp_buf) { + ts_err("failed alloc memory"); + return -ENOMEM; + } + /* if reg_addr == 0, read config data with specific flow */ + if (!reg_addr) { + if (ts_dev->hw_ops->read_config) + ret = ts_dev->hw_ops->read_config(ts_dev, tmp_buf, 0); + else + ret = -EINVAL; + } else { + ret = ts_dev->hw_ops->read_trans(ts_dev, reg_addr, tmp_buf, + length); + if (!ret) + ret = length; + } + if (ret <= 0) + goto err_out; + + if (copy_to_user((u8 *)arg + I2C_MSG_HEAD_LEN, tmp_buf, ret)) { + ret = -EFAULT; + ts_err("Copy_to_user failed"); + } + +err_out: + kfree(tmp_buf); + return ret; +} + +/* read data from i2c synchronous, +** success return bytes read, else return <= 0 +*/ +static int sync_read(struct goodix_tools_dev *dev, void __user *arg) +{ + int ret = 0; + u8 i2c_msg_head[I2C_MSG_HEAD_LEN]; + struct goodix_tools_data tools_data; + + ret = copy_from_user(&i2c_msg_head, arg, I2C_MSG_HEAD_LEN); + if (ret) { + ts_err("Copy data from user failed"); + return -EFAULT; + } + tools_data.reg_addr = i2c_msg_head[0] + (i2c_msg_head[1] << 8) + + (i2c_msg_head[2] << 16) + (i2c_msg_head[3] << 24); + tools_data.length = i2c_msg_head[4] + (i2c_msg_head[5] << 8) + + (i2c_msg_head[6] << 16) + (i2c_msg_head[7] << 24); + tools_data.filled = 0; + + tools_data.data = kzalloc(tools_data.length, GFP_KERNEL); + if (!tools_data.data) { + ts_err("Alloc memory failed"); + return -ENOMEM; + } + + mutex_lock(&dev->mutex); + list_add_tail(&tools_data.list, &dev->head); + mutex_unlock(&dev->mutex); + /* wait queue will timeout after 1 seconds */ + wait_event_interruptible_timeout(dev->wq, tools_data.filled == 1, + HZ * 3); + + mutex_lock(&dev->mutex); + list_del(&tools_data.list); + mutex_unlock(&dev->mutex); + if (tools_data.filled == 1) { + if (copy_to_user((u8 *)arg + I2C_MSG_HEAD_LEN, tools_data.data, + tools_data.length)) { + ret = -EFAULT; + ts_err("Copy_to_user failed"); + } else { + ret = tools_data.length; + } + } else { + ret = -EAGAIN; + ts_err("Wait queue timeout"); + } + + kfree(tools_data.data); + return ret; +} + +/* write data to i2c asynchronous, +** success return bytes write, else return <= 0 +*/ +static int async_write(struct goodix_tools_dev *dev, void __user *arg) +{ + u8 *databuf; + int ret = 0; + u32 reg_addr, length; + u8 i2c_msg_head[I2C_MSG_HEAD_LEN]; + struct goodix_ts_device *ts_dev = dev->ts_core->ts_dev; + const struct goodix_ts_hw_ops *hw_ops = ts_dev->hw_ops; + + ret = copy_from_user(&i2c_msg_head, arg, I2C_MSG_HEAD_LEN); + if (ret) { + ts_err("Copy data from user failed"); + return -EFAULT; + } + reg_addr = i2c_msg_head[0] + (i2c_msg_head[1] << 8) + + (i2c_msg_head[2] << 16) + (i2c_msg_head[3] << 24); + length = i2c_msg_head[4] + (i2c_msg_head[5] << 8) + + (i2c_msg_head[6] << 16) + (i2c_msg_head[7] << 24); + + databuf = kzalloc(length, GFP_KERNEL); + if (!databuf) { + ts_err("Alloc memory failed"); + return -ENOMEM; + } + ret = copy_from_user(databuf, (u8 *)arg + I2C_MSG_HEAD_LEN, length); + if (ret) { + ret = -EFAULT; + ts_err("Copy data from user failed"); + goto err_out; + } + + if (hw_ops->write_trans(ts_dev, reg_addr, databuf, length)) { + ret = -EBUSY; + ts_err("Write data to device failed"); + } else { + ret = length; + } + +err_out: + kfree(databuf); + return ret; +} + +/** + + * sync_read_rawdata - read device register through i2c bus + + * @dev: pointer to device data + + * @addr: register address + + * @data: read buffer + + * @len: bytes to read + + * return: 0 - read ok, < 0 - i2c transter error + +*/ + +int sync_read_rawdata(unsigned int reg, unsigned char *data, unsigned int len) + +{ + int ret = 0; + + struct goodix_tools_dev *dev = goodix_tools_dev; + + struct goodix_tools_data tools_data; + + tools_data.reg_addr = reg; + + tools_data.length = len; + + tools_data.filled = 0; + + tools_data.data = kzalloc(tools_data.length, GFP_KERNEL); + + if (!tools_data.data) { + ts_err("Alloc memory failed"); + + return -ENOMEM; + } + + mutex_lock(&dev->mutex); + + list_add_tail(&tools_data.list, &dev->head); + + ts_info("add sync_read to list"); + + mutex_unlock(&dev->mutex); + + /* wait queue will timeout after 1 seconds */ + + wait_event_interruptible_timeout(dev->wq, tools_data.filled == 1, + HZ * 3); + + mutex_lock(&dev->mutex); + + list_del(&tools_data.list); + + mutex_unlock(&dev->mutex); + + if (tools_data.filled == 1) { + memcpy(data, tools_data.data, tools_data.length); + + } else { + ret = -EAGAIN; + + ts_err("Wait queue timeout"); + } + + kfree(tools_data.data); + + return ret; +} + +int goodix_tools_register(void) + +{ + int ret = 0; + + ts_info("register tools module"); + + /* Only the first time open device need to register module */ + + ret = goodix_register_ext_module(&goodix_tools_dev->module); + + if (ret) { + ts_info("failed register to core module"); + } + + return ret; +} + +int goodix_tools_unregister(void) + +{ + int ret = 0; + + /* when the last close this dev node unregister the module */ + + ret = goodix_unregister_ext_module(&goodix_tools_dev->module); + + return ret; +} + +static int init_cfg_data(struct goodix_ts_config *cfg, void __user *arg) +{ + int ret = 0; + u32 reg_addr, length; + u8 i2c_msg_head[I2C_MSG_HEAD_LEN]; + + cfg->initialized = 0; + mutex_init(&cfg->lock); + ret = copy_from_user(&i2c_msg_head, arg, I2C_MSG_HEAD_LEN); + if (ret) { + ts_err("Copy data from user failed"); + return -EFAULT; + } + + reg_addr = i2c_msg_head[0] + (i2c_msg_head[1] << 8) + + (i2c_msg_head[2] << 16) + (i2c_msg_head[3] << 24); + length = i2c_msg_head[4] + (i2c_msg_head[5] << 8) + + (i2c_msg_head[6] << 16) + (i2c_msg_head[7] << 24); + + ret = copy_from_user(cfg->data, (u8 *)arg + I2C_MSG_HEAD_LEN, length); + if (ret) { + ret = -EFAULT; + ts_err("Copy data from user failed"); + goto err_out; + } + cfg->reg_base = reg_addr; + cfg->length = length; + strlcpy(cfg->name, "tools-send-cfg", sizeof(cfg->name)); + cfg->delay = 50; + cfg->initialized = true; + return 0; + +err_out: + return ret; +} +/** + * goodix_tools_ioctl - ioctl implementation + * + * @filp: Pointer to file opened + * @cmd: Ioctl opertion command + * @arg: Command data + * Returns >=0 - succeed, else failed + */ +static long goodix_tools_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int ret = 0; + struct goodix_tools_dev *dev = filp->private_data; + struct goodix_ts_device *ts_dev; + const struct goodix_ts_hw_ops *hw_ops; + struct goodix_ts_cmd temp_cmd; + struct goodix_ts_config *temp_cfg = NULL; + + if (dev->ts_core == NULL) { + ts_err("Tools module not register"); + return -EINVAL; + } + ts_dev = dev->ts_core->ts_dev; + hw_ops = ts_dev->hw_ops; + + if (_IOC_TYPE(cmd) != GOODIX_TS_IOC_MAGIC) { + ts_err("Bad magic num:%c", _IOC_TYPE(cmd)); + return -ENOTTY; + } + if (_IOC_NR(cmd) > GOODIX_TS_IOC_MAXNR) { + ts_err("Bad cmd num:%d > %d", _IOC_NR(cmd), + GOODIX_TS_IOC_MAXNR); + return -ENOTTY; + } + + switch (cmd & NEGLECT_SIZE_MASK) { + case GTP_IRQ_ENABLE: + if (arg == 1) { + goodix_ts_irq_enable(dev->ts_core, true); + mutex_lock(&dev->mutex); + dev->ops_mode |= IRQ_FALG; + mutex_unlock(&dev->mutex); + ts_info("IRQ enabled"); + } else if (arg == 0) { + goodix_ts_irq_enable(dev->ts_core, false); + mutex_lock(&dev->mutex); + dev->ops_mode &= ~IRQ_FALG; + mutex_unlock(&dev->mutex); + ts_info("IRQ disabled"); + } else { + ts_info("Irq aready set with, arg = %ld", arg); + } + ret = 0; + break; + case GTP_ESD_ENABLE: + if (arg == 0) + goodix_ts_blocking_notify(NOTIFY_ESD_OFF, NULL); + else + goodix_ts_blocking_notify(NOTIFY_ESD_ON, NULL); + break; + case GTP_DEV_RESET: + hw_ops->reset(ts_dev); + break; + case GTP_SEND_COMMAND: + ret = copy_from_user(&temp_cmd, (void __user *)arg, + sizeof(struct goodix_ts_cmd)); + if (ret) { + ret = -EINVAL; + goto err_out; + } + + ret = hw_ops->send_cmd(ts_dev, &temp_cmd); + if (ret) { + ts_err("Send command failed"); + ret = -EAGAIN; + } + break; + case GTP_SEND_CONFIG: + temp_cfg = kzalloc(sizeof(struct goodix_ts_config), GFP_KERNEL); + if (temp_cfg == NULL) { + ts_err("Memory allco err"); + ret = -ENOMEM; + goto err_out; + } + + ret = init_cfg_data(temp_cfg, (void __user *)arg); + + if (!ret && hw_ops->send_config) { + ret = hw_ops->send_config(ts_dev, temp_cfg); + if (ret) { + ts_err("Failed send config"); + ret = -EAGAIN; + } else { + ts_info("Send config success"); + ret = 0; + } + } + break; + case GTP_READ_CONFIG: + ret = read_config_data(ts_dev, (void __user *)arg); + if (ret > 0) + ts_info("success read config:len=%d", ret); + else + ts_err("failed read config:ret=0x%x", ret); + break; + case GTP_ASYNC_READ: + ret = async_read(dev, (void __user *)arg); + if (ret < 0) + ts_err("Async data read failed"); + break; + case GTP_SYNC_READ: + if (filp->f_flags & O_NONBLOCK) { + ts_err("Goodix tools now worked in sync_bus mode"); + ret = -EAGAIN; + goto err_out; + } + ret = sync_read(dev, (void __user *)arg); + if (ret < 0) + ts_err("Sync data read failed"); + break; + case GTP_ASYNC_WRITE: + ret = async_write(dev, (void __user *)arg); + if (ret < 0) + ts_err("Async data write failed"); + break; + case GTP_DRV_VERSION: + ret = copy_to_user((u8 *)arg, GOODIX_DRIVER_VERSION, + sizeof(GOODIX_DRIVER_VERSION)); + if (ret) + ts_err("failed copy driver version info to user"); + break; + default: + ts_info("Invalid cmd"); + ret = -ENOTTY; + break; + } + +err_out: + if (!temp_cfg) { + kfree(temp_cfg); + temp_cfg = NULL; + } + return ret; +} + +#ifdef CONFIG_COMPAT +static long goodix_tools_compat_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + void __user *arg32 = compat_ptr(arg); + + if (!file->f_op || !file->f_op->unlocked_ioctl) + return -ENOTTY; + return file->f_op->unlocked_ioctl(file, cmd, (unsigned long)arg32); +} +#endif + +static int goodix_tools_open(struct inode *inode, struct file *filp) +{ + int ret = 0; + filp->private_data = goodix_tools_dev; + ts_info("tools open"); + /* Only the first time open device need to register module */ + ret = goodix_register_ext_module(&goodix_tools_dev->module); + if (ret) { + ts_info("failed register to core module"); + } + + return ret; +} + +static int goodix_tools_release(struct inode *inode, struct file *filp) +{ + int ret = 0; + /* when the last close this dev node unregister the module */ + ret = goodix_unregister_ext_module(&goodix_tools_dev->module); + return ret; +} + +/** + * goodix_tools_module_irq - goodix tools Irq handle + * This functions is excuted when interrupt happended + * + * @core_data: pointer to touch core data + * @module: pointer to goodix_ext_module struct + * return: EVT_CONTINUE let other module handle this irq + */ +static int goodix_tools_module_irq(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct goodix_tools_dev *dev = module->priv_data; + struct goodix_ts_device *ts_dev = dev->ts_core->ts_dev; + const struct goodix_ts_hw_ops *hw_ops = ts_dev->hw_ops; + struct goodix_tools_data *tools_data; + int r = 0; + u8 evt_sta = 0; + + mutex_lock(&dev->mutex); + if (!list_empty(&dev->head)) { + r = hw_ops->read_trans(ts_dev, + ts_dev->reg.coor /* TS_REG_COORDS_BASE*/, + &evt_sta, 1); + if (r < 0 || ((evt_sta & GOODIX_TOUCH_EVENT) == 0)) { + ts_err("data not ready:0x%x, read ret =%d", evt_sta, r); + mutex_unlock(&dev->mutex); + return EVT_CONTINUE; + } + + list_for_each_entry(tools_data, &dev->head, list) { + if (!hw_ops->read_trans(ts_dev, tools_data->reg_addr, + tools_data->data, + tools_data->length)) { + tools_data->filled = 1; + } + } + wake_up(&dev->wq); + } + mutex_unlock(&dev->mutex); + return EVT_CONTINUE; +} + +static int goodix_tools_module_init(struct goodix_ts_core *core_data, + struct goodix_ext_module *module) +{ + struct goodix_tools_dev *tools_dev = module->priv_data; + + if (core_data) + tools_dev->ts_core = core_data; + else + return -ENODEV; + + return 0; +} + +static const struct file_operations goodix_tools_fops = { + .owner = THIS_MODULE, + .open = goodix_tools_open, + .release = goodix_tools_release, + .unlocked_ioctl = goodix_tools_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = goodix_tools_compat_ioctl, +#endif +}; + +static struct miscdevice goodix_tools_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = GOODIX_TOOLS_NAME, + .fops = &goodix_tools_fops, +}; + +static struct goodix_ext_module_funcs goodix_tools_module_funcs = { + .irq_event = goodix_tools_module_irq, + .init = goodix_tools_module_init, +}; + +/** + * goodix_tools_init - init goodix tools device and register a miscdevice + * + * return: 0 success, else failed + */ +static int __init goodix_tools_init(void) +{ + int ret; + + goodix_tools_dev = kzalloc(sizeof(struct goodix_tools_dev), GFP_KERNEL); + if (goodix_tools_dev == NULL) { + ts_err("Memory allco err"); + return -ENOMEM; + } + + INIT_LIST_HEAD(&goodix_tools_dev->head); + goodix_tools_dev->ops_mode = 0; + goodix_tools_dev->ops_mode |= IRQ_FALG; + init_waitqueue_head(&goodix_tools_dev->wq); + mutex_init(&goodix_tools_dev->mutex); + atomic_set(&goodix_tools_dev->t_count, 0); + + goodix_tools_dev->module.funcs = &goodix_tools_module_funcs; + goodix_tools_dev->module.name = GOODIX_TOOLS_NAME; + goodix_tools_dev->module.priv_data = goodix_tools_dev; + goodix_tools_dev->module.priority = EXTMOD_PRIO_DBGTOOL; + + ret = misc_register(&goodix_tools_miscdev); + if (ret) + ts_err("Debug tools miscdev register failed"); + + return ret; +} + +static void __exit goodix_tools_exit(void) +{ + misc_deregister(&goodix_tools_miscdev); + kfree(goodix_tools_dev); + ts_info("Goodix tools miscdev exit"); +} + +module_init(goodix_tools_init); +module_exit(goodix_tools_exit); + +MODULE_DESCRIPTION("Goodix tools Module"); +MODULE_AUTHOR("Goodix, Inc."); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/Makefile b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/Makefile new file mode 100644 index 000000000000..b82ae26d8dc2 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/Makefile @@ -0,0 +1,40 @@ +# test core code +# +ccflags-y += -I$(srctree)/drivers/input/touchscreen/normandy_unified_protocol + +obj-y += board_opr_interface_kernel.o +obj-y += public_fun.o +obj-y += simple_mem_manager_mach.o +obj-y += test_proc.o +obj-y += tp_additional_option.o +obj-y += tp_dev_control.o +obj-y += tp_item_permutation.o +obj-y += tp_normandy_control.o +obj-y += tp_open_test.o +obj-y += normandy_short_test.o +obj-y += tp_short_test.o +obj-y += tp_test_item_buf_mem.o +obj-y += tp_test_item_mem.o +obj-y += tp_version_test.o +obj-y += memory_override.o + +#comm +obj-y += crc_decrypt.o +obj-y += extra_tp_control.o +obj-y += generic_func.o +obj-y += save_test_data.o +obj-y += test_item_init.o +obj-y += test_order.o +obj-y += test_param_init.o + +# xml lib +obj-y += mxml-attr.o +obj-y += mxml-entity.o +obj-y += mxml-file.o +obj-y += mxml-get.o +obj-y += mxml-index.o +obj-y += mxml-node.o +obj-y += mxml-private.o +obj-y += mxml-search.o +obj-y += mxml-set.o +obj-y += mxml-string.o diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface.h new file mode 100644 index 000000000000..acbf89d8f57c --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface.h @@ -0,0 +1,123 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : board_opr_interface.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 08/23/2017 +* Description : board operation interface +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef BOARD_OPR_INTERFACE_H +#define BOARD_OPR_INTERFACE_H + +#include "user_test_type_def.h" +#include "tp_dev_def.h" +#include "res_inc.h" + +#include +#include "../goodix_ts_core.h" +#include +#include +#include +#include +/*#include */ +/*#include */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define L_MAX 2147483647 /*0x7FFFFFFF */ +#define L_MIN (-2147483647 - 1) /*-0x80000000*/ + +#define CONFIG_GOODIX_DEBUG +#ifdef CONFIG_GOODIX_DEBUG +#define board_print_debug(fmt, arg...) \ + pr_info("[GTP-DBG][%s:%d]" fmt "\n", __func__, __LINE__, ##arg) +#else +#define board_print_debug(fmt, arg...) \ + do { \ + } while (0) +#endif +#define board_print_error(fmt, arg...) \ + pr_err("[GTP-ERR][%s:%d]" fmt "\n", __func__, __LINE__, ##arg) +#define board_print_warning(fmt, arg...) \ + pr_info("[GTP-WARN][%s:%d]" fmt "\n", __func__, __LINE__, ##arg) +#define board_print_info(fmt, arg...) \ + pr_info("[GTP-INF][%s:%d]" fmt "\n", __func__, __LINE__, ##arg) +#define printf(fmt, arg...) \ + pr_info("[GTP-INF][%s:%d]" fmt "\n", __func__, __LINE__, ##arg) + +#define usleep(ms) msleep(ms / 1000) +#define EOF -1 +/*********************************str opr**********************************/ +extern char *strdup(const char *s); +extern int strtol(const char *nptr, char **endptr, int base); + +/*********************************mem opr**********************************/ +extern void *malloc(size_t size); +extern void free(void *ptr); +extern void *realloc(void *ptr, size_t size); +extern void *calloc(size_t n, size_t size); + +/*********************************adc opr**********************************/ +/*such 2 functions only used in arm test board*/ +extern u16 board_get_volt_value(PST_TP_DEV p_dev, u8 adc_id, u16 aver_len); +extern u32 board_get_avg_current(PST_TP_DEV p_dev, u32 cnt); + +/*********************************dac opr**********************************/ +/*such 2 functions only used in arm test board*/ +extern s32 board_set_power_volt(PST_TP_DEV p_dev, u16 volt, u16 aver_len, + u8 cnt); +extern s32 board_set_comm_volt(PST_TP_DEV p_dev, u16 volt, u16 aver_len, + u8 cnt); + +/*********************************gpio opr**********************************/ +/*such 2 functions only used in arm test board*/ +extern void board_gpio_mode_set(PST_TP_DEV p_dev, u8 gpio_type, u16 gpio_pin, + u8 gpio_mode); +extern void board_gpio_reset_bits(PST_TP_DEV p_dev, u8 gpio_type, u16 gpio_pin); +extern void board_gpio_set_bits(PST_TP_DEV p_dev, u8 gpio_type, u16 gpio_pin); + +/*********************************delay opr**********************************/ +extern void board_delay_ms(u16 ms); +extern void board_delay_s(u16 s); +extern void board_delay_us(u16 us); +extern void board_get_now_time(u8 *p_tim_buf, u8 *p_len); + +/*********************************communicate opr**********************************/ +extern s32 board_read_chip_reg(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len); +extern s32 board_write_chip_reg(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len); + +/*********************************platform debug**********************************/ + +/*********************************work mode**********************************/ +extern s32 board_enter_rawdata_mode(PST_TP_DEV p_dev); +extern s32 board_enter_coord_mode(PST_TP_DEV p_dev); +extern s32 board_enter_sleep_mode(PST_TP_DEV p_dev); +extern s32 board_enter_diffdata_mode(PST_TP_DEV p_dev); + +extern s32 board_get_rawdata(PST_TP_DEV p_dev, u16 time_out_ms, + u8 b_filter_data, ptr32 p_cur_data); +extern s32 board_get_diffdata(PST_TP_DEV p_dev, u16 time_out_ms, + u8 b_filter_data, ptr32 p_cur_data); + +/*********************************chip opr**********************************/ +extern s32 board_hard_reset_chip(PST_TP_DEV p_dev); +extern s32 board_chip_hid_opr(PST_TP_DEV p_dev, + s32 b_ena); /*use for hid protocol*/ +extern s32 board_disable_dev_status(PST_TP_DEV p_dev); +extern s32 board_recovery_dev_status(PST_TP_DEV p_dev); +extern s32 board_seek_dev_addr(PST_TP_DEV p_dev); +extern s32 board_max_trans_len(PST_TP_DEV p_dev); +extern s32 board_update_chip_fw(PST_TP_DEV p_dev, ptr32 p_cur_data); +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface_kernel.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface_kernel.c new file mode 100644 index 000000000000..30d3763d457a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/board_opr_interface_kernel.c @@ -0,0 +1,691 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : board_opr_interface.cpp +* Author : +* Version : V1.0.0 +* Date : 08/23/2017 +* Description : board operation interface,you may change this file if you + use a new test platform +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE +#include "board_opr_interface.h" +#include "tp_dev_control.h" +#include "tp_open_test.h" +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* Function Name : board_delay_ms +* Description : delay milliseconds +* Input : u16 ms +* Output : none +* Return : void +*******************************************************************************/ +extern void board_delay_ms(u16 ms) +{ +#if WCE_CODE == 1 + +#else + usleep(ms * 1000); +#endif +} +/******************************************************************************* +* Function Name : board_delay_us +* Description : delay microseconds +* Input : u16 us +* Output : none +* Return : void +*******************************************************************************/ +extern void board_delay_us(u16 us) +{ +#if QNX_CODE == 1 + /*usleep(us);*/ +#elif ANDROID_CODE == 1 + +#endif +} + +/******************************************************************************* +* Function Name : board_delay_s +* Description : delay seconds +* Input : u16 s +* Output : none +* Return : void +*******************************************************************************/ +extern void board_delay_s(u16 s) +{ +#if ANDROID_CODE == 1 + +#elif QNX_CODE == 1 + +#endif +} + +/******************************************************************************* +* Function Name : seg_read_chip_reg +* Description : read chip reg segmentally +* Input : PST_TP_DEV p_dev + : u16 addr(address) + : u8* p_buf(data buffer) + : u16 buf_len(buffer length) +* Output : u8* p_buf +* Return : u8(0:have not handled 1:handled) +*******************************************************************************/ +static s32 seg_read_chip_reg(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, u16 buf_len) +{ + struct device *dev; + struct goodix_ts_core *core_data; + struct goodix_ts_device *ts_dev; + const struct goodix_ts_hw_ops *hw_ops; + s32 ret = 1; + + u16 i = 0; + u16 pack_size = 255; + u16 code_len = buf_len; + u16 packages; + u32 send_len; + u16 start_addr, tmp_addr; + start_addr = addr; + tmp_addr = addr; + send_len = pack_size; + packages = code_len / pack_size + 1; + for (i = 0; i < packages; i++) { + if (send_len > code_len) { + send_len = code_len; + } + /*read code*/ + dev = (struct device *)p_dev->p_logic_dev; + core_data = dev_get_drvdata(dev); + ts_dev = core_data->ts_dev; + hw_ops = ts_dev->hw_ops; + ret = hw_ops->read_trans(ts_dev, tmp_addr, + (u8 *)&p_buf[tmp_addr - start_addr], + send_len); + if (ret < 0) + ret = 0; + else + ret = 1; + + if (ret == 0) + return 0; + tmp_addr += send_len; + code_len -= send_len; + if (code_len <= 0) { + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : seg_write_chip_reg +* Description : write chip reg segmentally +* Input : PST_TP_DEV p_dev + : u16 addr(address) + : u8* p_buf(data buffer) + : u16 buf_len(buffer length) +* Output : u8* p_buf +* Return : u8(0:have not handled 1:handled) +*******************************************************************************/ +static s32 seg_write_chip_reg(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len) +{ + struct device *dev; + struct goodix_ts_core *core_data; + struct goodix_ts_device *ts_dev; + const struct goodix_ts_hw_ops *hw_ops; + s32 ret = 1; + + u16 i = 0; + u16 pack_size = 255; + u16 code_len = buf_len; + u16 packages; + u32 write_len; + u16 start_addr, tmp_addr; + start_addr = addr; + tmp_addr = addr; + write_len = pack_size; + packages = code_len / pack_size + 1; + for (i = 0; i < packages; i++) { + if (write_len > code_len) { + write_len = code_len; + } + /*send code*/ + dev = (struct device *)p_dev->p_logic_dev; + core_data = dev_get_drvdata(dev); + ts_dev = core_data->ts_dev; + hw_ops = ts_dev->hw_ops; + ret = hw_ops->write_trans(ts_dev, tmp_addr, + (u8 *)&p_buf[tmp_addr - start_addr], + write_len); + if (ret < 0) { + ret = 0; + } else { + ret = 1; + } + + if (ret == 0) { + /*board_print_error("segment write code error!\n");*/ + return 0; + } + + tmp_addr += write_len; + code_len -= write_len; + if (code_len <= 0) { + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : board_read_chip_reg +* Description : read data from module +* Input : PST_TP_DEV p_dev + : u16 addr(address) + : u8* p_buf(data buffer) + : u16 buf_len(buffer length) +* Output : u8* p_buf +* Return : u8(0:have not handled 1:handled) +*******************************************************************************/ +extern s32 board_read_chip_reg(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len) +{ + return seg_read_chip_reg(p_dev, addr, p_buf, buf_len); +} +/******************************************************************************* +* Function Name : board_write_chip_reg +* Description : write data to module +* Input : PST_TP_DEV p_dev + : u16 addr(address) + : u8* p_buf(data buffer) + : u16 buf_len(buffer length) +* Output : none +* Return : u8(0:have not handled 1:handled) +*******************************************************************************/ +extern s32 board_write_chip_reg(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len) +{ + return seg_write_chip_reg(p_dev, addr, p_buf, buf_len); +} + +/******************************************************************************* +* Function Name : board_hard_reset_chip +* Description : hard reset chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_hard_reset_chip(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + struct device *dev; + struct goodix_ts_core *core_data; + struct goodix_ts_device *ts_dev; + const struct goodix_ts_hw_ops *hw_ops; + dev = (struct device *)p_dev->p_logic_dev; + core_data = dev_get_drvdata(dev); + ts_dev = core_data->ts_dev; + hw_ops = ts_dev->hw_ops; + ret = hw_ops->reset(ts_dev); + if (ret < 0) { + ret = 0; + } else { + ret = 1; + } + return ret; +} + +/******************************************************************************* +* Function Name : board_disable_dev_status +* Description : disable esd ird ... +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_disable_dev_status(PST_TP_DEV p_dev) +{ + s32 ret = 1; + struct device *dev; + struct goodix_ts_core *core_data; + dev = (struct device *)p_dev->p_logic_dev; + core_data = dev_get_drvdata(dev); + /*disable esd*/ + goodix_ts_blocking_notify(NOTIFY_ESD_OFF, NULL); + /*disable irq*/ + goodix_ts_irq_enable(core_data, false); + return ret; +} + +/******************************************************************************* +* Function Name : board_recovery_dev_status +* Description : recovey dev status(esd,irq) +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_recovery_dev_status(PST_TP_DEV p_dev) +{ + s32 ret = 1; + struct device *dev; + struct goodix_ts_core *core_data; + dev = (struct device *)p_dev->p_logic_dev; + core_data = dev_get_drvdata(dev); + + /*disable esd*/ + goodix_ts_blocking_notify(NOTIFY_ESD_ON, NULL); + /*disable irq*/ + goodix_ts_irq_enable(core_data, true); + return ret; +} + +/******************************************************************************* +* Function Name : board_enter_rawdata_mode +* Description : chip enter rawdata mode +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_enter_rawdata_mode(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + u8 i = 0; + u8 retry_cnt = 5; + board_delay_ms(5); + + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_write(p_dev, p_dev->cmd_set.rawdata_cmd.addr, + p_dev->cmd_set.rawdata_cmd.cmd_buf, + p_dev->cmd_set.rawdata_cmd.cmd_len); + if (1 == ret) { + break; + } + } + + board_delay_ms(18); + ret = clr_data_flag(p_dev); + return ret; +} + +/******************************************************************************* +* Function Name : board_enter_coord_mode +* Description : set chip enter coordinate mode +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_enter_coord_mode(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + u8 i = 0; + u8 retry_cnt = 5; + + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_write(p_dev, p_dev->cmd_set.coorddata_cmd.addr, + p_dev->cmd_set.coorddata_cmd.cmd_buf, + p_dev->cmd_set.coorddata_cmd.cmd_len); + if (1 == ret) { + break; + } + } + + board_delay_ms(18); + ret = clr_data_flag(p_dev); + return ret; +} + +/******************************************************************************* +* Function Name : board_enter_sleep_mode +* Description : set chip entering sleep mode +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_enter_sleep_mode(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + u8 retry_cnt = 3; + u8 i = 0; + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_write(p_dev, p_dev->cmd_set.sleep_cmd.addr, + p_dev->cmd_set.sleep_cmd.cmd_buf, + p_dev->cmd_set.sleep_cmd.cmd_len); + if (1 == ret) { + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : board_enter_diffdata_mode +* Description : set chip entering diffdata mode +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_enter_diffdata_mode(IN PST_TP_DEV p_dev) +{ + return board_enter_rawdata_mode(p_dev); +} + +/******************************************************************************* +* Function Name : board_get_rawdata +* Description : board_get_rawdata +* Input : PST_TP_DEV p_dev(touch panel device) +* Input : u16 time_out_ms +* Output : ptr32 p_cur_data +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_get_rawdata(PST_TP_DEV p_dev, u16 time_out_ms, + u8 b_filter_data, ptr32 p_cur_data) +{ + s32 ret = 0; + u8 i = 0; + u8 retry_cnt = 3; + u8 data_size = 1; + PST_CUR_RAWDATA p_rawdata = (PST_CUR_RAWDATA)p_cur_data; + + if ((p_dev->chip_type == TP_NORMANDY) || + (p_dev->chip_type == TP_OSLO)) { + if (b_filter_data == 1) { + return 1; + } + + data_size = get_data_size(p_dev->rawdata_option); + for (i = 0; i < retry_cnt; i++) { + ret = sync_read_rawdata(p_dev->rawdata_addr, + p_rawdata->p_data_buf, + p_dev->rawdata_len * data_size); + if (ret >= 0) { + ret = 1; + break; + } + } + board_print_debug("rawdata buf len :%d!\n", + p_rawdata->data_len); + if (ret == 1) { + if ((p_dev->rawdata_option & _DATA_LARGE_ENDIAN) || + (p_dev->rawdata_option & _DATA_DRV_SEN_INVERT)) { + reshape_data(p_dev->rawdata_option, p_dev, + p_rawdata); + } + } + return ret; + } else { + return get_rawdata(p_dev, time_out_ms, b_filter_data, + p_rawdata); + } +} + +/******************************************************************************* +* Function Name : board_get_diffdata +* Description : board_get_diffdata +* Input : PST_TP_DEV p_dev(touch panel device) +* Input : u16 time_out_ms +* Output : ptr32 p_cur_data +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_get_diffdata(PST_TP_DEV p_dev, u16 time_out_ms, + u8 b_filter_data, ptr32 p_cur_data) +{ + s32 ret = 0; + u8 i = 0; + u8 retry_cnt = 3; + u8 data_size = 1; + PST_CUR_DIFFDATA p_diffdata = (PST_CUR_DIFFDATA)p_cur_data; + + if ((p_dev->chip_type == TP_NORMANDY) || + (p_dev->chip_type == TP_OSLO)) { + if (b_filter_data == 1) { + return 1; + } + + data_size = get_data_size(p_dev->diffdata_option); + for (i = 0; i < retry_cnt; i++) { + ret = sync_read_rawdata( + p_dev->diffdata_addr, p_diffdata->p_data_buf, + p_dev->diffdata_len * data_size); + if (ret > 0) { + ret = 1; + break; + } + } + if (ret == 1) { + if ((p_dev->diffdata_option & _DATA_LARGE_ENDIAN) || + (p_dev->diffdata_option & _DATA_DRV_SEN_INVERT)) { + reshape_data(p_dev->diffdata_option, p_dev, + p_diffdata); + } + } + return ret; + } else { + return get_diffdata(p_dev, time_out_ms, b_filter_data, + p_diffdata); + } +} + +/******************************************************************************* +* Function Name : board_hard_reset_chip +* Description : (use for hid protocol) +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : s32 b_ena(1:enable hid 0:disable hid) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 board_chip_hid_opr(PST_TP_DEV p_dev, s32 b_ena) +{ + s32 ret = 1; + s32 i = 0; + s32 retry_cnt = 3; + + if ((1 == b_ena && 0 == p_dev->hid_state) || + (0 == b_ena && 1 == p_dev->hid_state)) { + p_dev->hid_state = (p_dev->hid_state == 0) ? (1) : (0); + } else { + return 1; + } + + if (1 == b_ena) { + for (i = 0; i < retry_cnt; i++) { + ret = board_write_chip_reg( + p_dev, p_dev->cmd_set.hid_ena_cmd.addr, + p_dev->cmd_set.hid_ena_cmd.cmd_buf, + p_dev->cmd_set.hid_ena_cmd.cmd_len); + /* + cmd_buf[0] = 0xbb; + cmd_buf[1] = 0x00; + cmd_buf[2] = 0x45; + ret = board_write_chip_reg(p_dev, 0x8040,cmd_buf, 3); + */ + if (1 == ret) { + break; + } + } + } else if (0 == b_ena) { + for (i = 0; i < retry_cnt; i++) { + ret = board_write_chip_reg( + p_dev, p_dev->cmd_set.hid_dis_cmd.addr, + p_dev->cmd_set.hid_dis_cmd.cmd_buf, + p_dev->cmd_set.hid_dis_cmd.cmd_len); + /* + cmd_buf[0] = 0xaa; + cmd_buf[1] = 0x00; + cmd_buf[2] = 0x56; + ret = board_write_chip_reg(p_dev, 0x8040,cmd_buf, 3); + */ + if (1 == ret) { + break; + } + } + } + + if (0 == ret) { + board_print_error("%s\n", "send hid opr cmd fail!"); + } + return ret; +} +extern char *strdup(const char *s) +{ + size_t len = strlen(s) + 1; + void *new = malloc(len); + if (new == NULL) { + return NULL; + } + return (char *)memcpy(new, s, len); +} + +extern int strtol(const char *nptr, char **endptr, int base) +{ + const char *p = nptr; + int ret; + int ch; + int Overflow; + int sign = 0, flag, LimitRemainder; + /*delete space*/ + do { + ch = *p++; + } while (ch == ' '); + + if (ch == '-') { + sign = 1; + ch = *p++; + } else if (ch == '+') + ch = *p++; + if ((base == 0 || base == 16) && ch == '0' && + (*p == 'x' || *p == 'X')) { + ch = p[1]; + p += 2; + base = 16; + } + if (base == 0) + base = ch == '0' ? 8 : 10; + Overflow = sign ? -(u32)L_MIN : L_MAX; + LimitRemainder = Overflow % (u32)base; + Overflow /= (u32)base; + for (ret = 0, flag = 0;; ch = *p++) { + /*get target value*/ + if (ch >= '0' && ch <= '9') + ch -= '0'; + else if (ch >= 'A' && ch <= 'Z') + ch -= 'A' - 10; + else if (ch >= 'a' && ch <= 'z') + ch -= 'a' - 10; + else + break; + if (ch >= base) + break; + /*overflow*/ + if (flag < 0 || ret > Overflow || + (ret == Overflow && ch > LimitRemainder)) + flag = -1; + else { + flag = 1; + ret *= base; + ret += ch; + } + } + if (flag < 0) + ret = sign ? L_MIN : L_MAX; + else if (sign) + ret = -ret; + if (endptr != 0) + *endptr = (char *)(flag ? (p - 1) : nptr); + return ret; +} +/* +extern void* realloc(void* ptr, size_t size){ + void *new = NULL; + if (ptr == NULL) + return NULL; + if (size != 0){ + if (!(new == kmalloc(size, GFP_KERNEL))) + return NULL; + memcpy(new,ptr,strlen((const char*)ptr)); + kfree(ptr); + return new; + }else + return NULL; + +}*/ + +extern void *calloc(size_t n, size_t size) +{ + void *buf = NULL; + buf = malloc(n * size); + if (buf != NULL) + memset(buf, 0, n * size); + return buf; +} +/****************************************arm interface**************************************************/ +extern s32 board_get_exti_flag(PST_TP_DEV p_dev, u8 exti_id) +{ + return 1; +} +extern s32 board_clear_exti_flag(PST_TP_DEV p_dev, u8 exti_id) +{ + return 1; +} + +extern u16 board_get_volt_value(PST_TP_DEV p_dev, u8 adc_id, u16 aver_len) +{ + return 1; +} + +extern s32 board_set_power_volt(PST_TP_DEV p_dev, u16 volt, u16 aver_len, + u8 cnt) +{ + return 1; +} +extern s32 board_set_comm_volt(PST_TP_DEV p_dev, u16 volt, u16 aver_len, u8 cnt) +{ + return 1; +} + +extern void board_gpio_mode_set(PST_TP_DEV p_dev, u8 gpio_type, u16 gpio_pin, + u8 gpio_mode) +{ + ; +} +extern void board_gpio_reset_bits(PST_TP_DEV p_dev, u8 gpio_type, u16 gpio_pin) +{ + ; +} +extern void board_gpio_set_bits(PST_TP_DEV p_dev, u8 gpio_type, u16 gpio_pin) +{ + ; +} +extern s32 board_set_exti_on(PST_TP_DEV p_dev, u8 exti_id, u16 modle) +{ + return 1; +} +extern void board_get_now_time(u8 *p_tim_buf, u8 *p_len) +{ + ; +} +extern u32 board_get_avg_current(PST_TP_DEV p_dev, u32 cnt) +{ + return 1; +} + +extern s32 board_max_trans_len(PST_TP_DEV p_dev) +{ + return 1024; +} + +extern s32 board_seek_dev_addr(PST_TP_DEV p_dev) +{ + return 1; +} + +extern s32 board_update_chip_fw(PST_TP_DEV p_dev, ptr32 p_cur_data) +{ + return 0; +} +/****************************************arm interface end**************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/chip_ini.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/chip_ini.h new file mode 100644 index 000000000000..1c3dfadd72cb --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/chip_ini.h @@ -0,0 +1,70 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : chip_ini.h +* Author : zhitao yang +* Version : V1.0.0 +* Date : 14/11/2018 +* Description : chip info +*******************************************************************************/ +#ifndef CHIP_INI_H +#define CHIP_INI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "tp_product_id_def.h" +#include "user_test_type_def.h" + +/*cfg*/ +#define CFG_START_ADDR 0x6F78 +#define CFG_LEN 690 + +#define SEN_MAX_NUM_IN_DIE 36 +#define DRV_MAX_NUM_IN_DIE 40 +#define MAX_SEN_NUM 36 +#define MAX_DRV_NUM 40 +#define MAX_KEY_NUM 4 + +/*cmd*/ +#define CMD_ADDR 0x6F68 + +/*rawdata*/ +#define DATA_ENDIAN 1 +#define DATA_INVERT 1 +#define RAWDATA_ADDR 0x8FA0 +#define RAW_UNIT_OF_BYTE 2 +#define RAW_SIGNED 1 +#define SYN_ADDR 0x4100 +#define SYN_MASK 0x80 + +#define MAP_DISABLE 0 + +u8 IC_NAME[] = "GT9886"; +u8 SEN_NUM_ADDR[] = "T1,10,0,7"; +u8 DRV_NUM_ADDR[] = "T1,14,0,7,T1,15,0,7"; + +u8 SEN_START_ADDR[] = "T2,2,0,7"; +u8 DRV_START_ADDR[] = "T2,38,0,7"; + +u8 KEY_START_ADDR[] = "T16,12,0,15"; +u8 SEN_AS_KEY_ADDR[] = "T16,2,3,3"; +u8 KEY_PORT_NUM[] = ""; +u8 KEY_EN[] = "T16,2,0,0"; +u8 HOPPING_EN[] = "T10,2,0,0"; + +/*channel map*/ +u8 DRV_MAP[] = { 46, 48, 49, 47, 45, 50, 56, 52, 51, 53, + 55, 54, 59, 64, 57, 60, 62, 58, 65, 63, + 61, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255 }; +u8 SEN_MAP[] = { 32, 34, 35, 30, 31, 33, 27, 28, 29, 10, 25, 26, + 23, 13, 24, 12, 9, 11, 8, 7, 5, 6, 4, 3, + 2, 1, 0, 73, 75, 74, 39, 72, 40, 36, 37, 38 }; +/*cmd buf*/ +u8 RAW_CMD_BUF[] = { 0x01, 0x00, 0xff }; +u8 COOR_CMD_BUF[] = { 0x00, 0x00, 0x00 }; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/config.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/config.h new file mode 100644 index 000000000000..1e321045d260 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/config.h @@ -0,0 +1,81 @@ +/* + * Configuration file for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Beginning with VC2005, Microsoft breaks ISO C and POSIX conformance + * by deprecating a number of functions in the name of security, even + * when many of the affected functions are otherwise completely secure. + * The _CRT_SECURE_NO_DEPRECATE definition ensures that we won't get + * warnings from their use... + * + * Then Microsoft decided that they should ignore this in VC2008 and use + * yet another define (_CRT_SECURE_NO_WARNINGS) instead. Bastards. + */ + +#define _CRT_SECURE_NO_DEPRECATE +#define _CRT_SECURE_NO_WARNINGS + +/* + * Include necessary headers... + */ + +#include +#include +#include +/*#include */ +#include "board_opr_interface.h" + +/* + * Microsoft also renames the POSIX functions to _name, and introduces + * a broken compatibility layer using the original names. As a result, + * random crashes can occur when, for example, strdup() allocates memory + * from a different heap than used by malloc() and free(). + * + * To avoid moronic problems like this, we #define the POSIX function + * names to the corresponding non-standard Microsoft names. + */ + +/* + * Version number... + */ + +#define MXML_VERSION "Mini-XML v2.11" +#define HAVE_LONG_LONG 1 +#define HAVE_SNPRINTF 1 +#define HAVE_VSNPRINTF 1 +#define HAVE_STRDUP 1 + +#ifndef HAVE_STRDUP +extern char *_mxml_strdup(const char *); +#define strdup _mxml_strdup +#endif /* !HAVE_STRDUP */ + +#ifndef HAVE_STRLCPY +extern size_t _mxml_strlcpy(char *, const char *, size_t); +#define strlcpy _mxml_strlcpy +#endif /* !HAVE_STRLCPY */ + +extern char *_mxml_strdupf(const char *, ...); +extern char *_mxml_vstrdupf(const char *, va_list); + +#ifndef HAVE_SNPRINTF +extern int _mxml_snprintf(char *, size_t, const char *, ...); +#define snprintf _mxml_snprintf +#endif /* !HAVE_SNPRINTF */ + +#ifndef HAVE_VSNPRINTF +extern int _mxml_vsnprintf(char *, size_t, const char *, va_list); +#define vsnprintf _mxml_vsnprintf +#endif /* !HAVE_VSNPRINTF */ diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.c new file mode 100644 index 000000000000..96dc961501aa --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.c @@ -0,0 +1,205 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : crc_decrypt.cpp +* Author : +* Version : V1.0.0 +* Date : 26/03/2018 +* Description : decrypt file +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "crc_decrypt.h" +#include "generic_func.h" +#include "board_opr_interface.h" +#include "simple_mem_manager.h" +#include +#include +#include "../goodix_ts_core.h" +const char default_order_name[] = "goodix_gt9886_limit_f11.tporder"; + +/******************************************************************************* +* Function Name : decrypt_reflect +* Description : +* Input : u32 ref + : s8 ch +* Output : +* Return : s32(0:Fail 1:ok) +*******************************************************************************/ +extern u32 decrypt_reflect(u32 ref, s8 ch) +{ + u32 value = 0; + s32 i; + for (i = 1; i < (ch + 1); i++) { + if (ref & 1) + value |= 1 << (ch - i); + ref >>= 1; + } + return value; +} + +/******************************************************************************* +* Function Name : decrypt_init_crc32_table +* Description : init crc32 table +* Input : u32 crc32_table[] +* Output : +* Return : s32(0:Fail 1:ok) +*******************************************************************************/ +extern s32 decrypt_init_crc32_table(u32 *crc32_table) +{ + u32 crc, temp; + u32 t1, t2; + u32 flag; + u32 ulPolynomial = 0x04c11db7; + s32 i, j; + for (i = 0; i <= 0xFF; i++) { + temp = decrypt_reflect(i, 8); + crc32_table[i] = temp << 24; + for (j = 0; j < 8; j++) { + flag = crc32_table[i] & 0x80000000; + t1 = (crc32_table[i] << 1); + if (flag == 0) + t2 = 0; + else + t2 = ulPolynomial; + crc32_table[i] = t1 ^ t2; + } + crc = crc32_table[i]; + crc32_table[i] = decrypt_reflect(crc32_table[i], 32); + } + return 1; +} + +/******************************************************************************* +* Function Name : decrypt_generate_crc32 +* Description : generate crc32 code +* Input : u32 crc32_table[] + : u8* buf + : u32 len +* Output : +* Return : u32() +*******************************************************************************/ +extern u32 decrypt_generate_crc32(u32 *crc32_table, u8 *buf, u32 len) +{ + u32 old_crc32 = 0xFFFFFFFF; + u32 i = 0; + for (i = 0; i < len; ++i) { + u32 t = (old_crc32 ^ buf[i]) & 0xFF; + old_crc32 = ((old_crc32 >> 8) & 0xFFFFFF) ^ crc32_table[t]; + } + /*old_crc32 = ~old_crc32;*/ + return (~old_crc32) & 0xffffffff; +} + +/******************************************************************************* +* Function Name : read_file_decoder +* Description : read file and decode file content +* Input : PST_TP_DEV p_tp_dev + : s8* ver_date + : s8* file_content +* Output : +* Return : s32(0:Fail 1:ok) +*******************************************************************************/ +extern s32 read_file_decoder(PST_TP_DEV p_tp_dev, s8 **ver_date, + s8 **file_content) +{ + s32 ret = 0; + s32 i = 0; + u32 file_len = 0; + u32 index_ver = 0; + u32 index_cont = 0; + s8 *cont_buf = NULL; + u32 crc_calc = 0; + u32 crc_origin = 0; + u32 crc32_table[256]; + char order_name[64]; + const struct firmware *firmware; + struct device *dev; + struct goodix_ts_board_data *ts_bdata = board_data(goodix_core_data); + + dev = (struct device *)p_tp_dev->p_logic_dev; + + if (ts_bdata && ts_bdata->limit_name) + strlcpy(order_name, ts_bdata->limit_name, sizeof(order_name)); + else + strlcpy(order_name, default_order_name, sizeof(order_name)); + /*read content*/ + for (i = 0; i < 2; i++) { + ret = request_firmware(&firmware, order_name, dev); + if (ret < 0) { + board_delay_ms(1); + } else { + ret = 1; + break; + } + } + if (i >= 2) { + board_print_error("request firmware error:%s\n", order_name); + ret = 0; + goto DECODE_EXIT; + } + + file_len = firmware->size; + board_print_debug("read file len:%d\n", file_len); + board_print_debug("malloc memory [crc]1!"); + /*malloc memory*/ + ret = alloc_mem_in_heap((void **)&cont_buf, file_len + 1); + if (cont_buf == NULL) { + board_print_error("malloc buf error!"); + } + ret = alloc_mem_in_heap((void **)ver_date, VECTOR_BYTE_LEN + 1); + ret = alloc_mem_in_heap((void **)file_content, file_len + 1); + if ((cont_buf == NULL) || (*ver_date == NULL) || + (*file_content == NULL)) { + board_print_error("cont buf malloc error!\n"); + release_firmware(firmware); + firmware = NULL; + return 0; + } + /*init*/ + cont_buf[file_len] = '\0'; + (*ver_date)[VECTOR_BYTE_LEN] = '\0'; + (*file_content)[file_len] = '\0'; + memcpy(cont_buf, firmware->data, file_len); + release_firmware(firmware); + firmware = NULL; + decrypt_init_crc32_table(crc32_table); + for (i = 0; i < 256; i++) { + crc32_table[i] &= 0xffffffff; + } + + crc_calc = decrypt_generate_crc32(crc32_table, (u8 *)cont_buf, + file_len - CRC_BYTE_LEN); + crc_origin += (u8)cont_buf[file_len - 1]; + crc_origin <<= 8; + crc_origin += (u8)cont_buf[file_len - 2]; + crc_origin <<= 8; + crc_origin += (u8)cont_buf[file_len - 3]; + crc_origin <<= 8; + crc_origin += (u8)cont_buf[file_len - 4]; + crc_origin = crc_origin & 0xffffffff; + if (crc_calc != crc_origin) { + board_print_error("crc check error!crc_calc=%d,crc_origin=%d\n", + crc_calc, crc_origin); + ret = 0; + goto DECODE_EXIT; + } + board_print_debug("crc check pass!crc_calc=%d,crc_origin=%d\n", + crc_calc, crc_origin); + for (i = 0; i < file_len - CRC_BYTE_LEN; i++) { + if (i < VECTOR_BYTE_LEN) { + (*ver_date)[index_ver++] = ((cont_buf[i] >> 4) & 0xFF); + (*ver_date)[index_ver++] = (cont_buf[i] & 0xFF); + } else { + (*file_content)[index_cont++] = (u8)(cont_buf[i] - 1); + } + } + ret = 1; +DECODE_EXIT: + free_mem_in_heap(cont_buf); + return ret; +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.h new file mode 100644 index 000000000000..2dd27f4c673f --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/crc_decrypt.h @@ -0,0 +1,32 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : crc_decrypt.h +* Author : +* Version : V1.0.0 +* Date : 26/03/2018 +* Description : decrypt file +*******************************************************************************/ +#ifndef CRC_DECRYPT_H +#define CRC_DECRYPT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "board_opr_interface.h" + +#define CRC_BYTE_LEN 4 +#define VECTOR_BYTE_LEN 5 + +/*************************************Public methods start********************************************/ +extern u32 decrypt_reflect(u32 ref, s8 ch); +extern s32 decrypt_init_crc32_table(u32 *crc32_table); +extern u32 decrypt_generate_crc32(u32 *crc32_table, u8 *buf, u32 len); +extern s32 read_file_decoder(PST_TP_DEV p_tp_dev, s8 **ver_date, + s8 **file_content); +/*************************************Public methods end********************************************/ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/custom_info_def.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/custom_info_def.h new file mode 100644 index 000000000000..596cfa49bab1 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/custom_info_def.h @@ -0,0 +1,30 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : custom_info_def.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : define custom info struct +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef CUSTOM_INFO_DEF_H +#define CUSTOM_INFO_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" + +#define CUSTOM_INFO_DESC_MAX_LEN 20 +typedef struct CUSTOM_INFO_BYTE { + u8 index; + u8 value; + u8 desc[CUSTOM_INFO_DESC_MAX_LEN]; +} ST_CUSTOM_INFO_BYTE, *PST_CUSTOM_INFO_BYTE; + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.c new file mode 100644 index 000000000000..dff5b8ccc977 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.c @@ -0,0 +1,108 @@ + +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : extra_tp_control.cpp +* Author : yangzhitao +* Version : V1.0.0 +* Date : 30/03/2018 +* Description : tp control func +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "extra_tp_control.h" +#include "tp_dev_control.h" +#include "tp_normandy_control.h" +#include "generic_func.h" +#include + +/******************************************************************************* +* Function Name : read_sensor_id +* Description : read sensor id +* Input : PST_TP_DEV p_tp_dev + : u8* sensor_id +* Output : u8* sensor_id +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 read_sensor_id(PST_TP_DEV p_tp_dev, u8 *sensor_id) +{ + s32 ret = 0; + u8 tmp_id[1]; + u16 sen_id_addr; + + switch (p_tp_dev->chip_type) { + case TP_NORMANDY: { + sen_id_addr = 0x4541; + break; + } + default: { + sen_id_addr = 0x814A; + break; + } + } + board_print_debug("sensor id addr:0x%04x!\n", sen_id_addr); + ret = chip_reg_read(p_tp_dev, sen_id_addr, sensor_id, 1); + ret = chip_reg_read(p_tp_dev, sen_id_addr, tmp_id, 1); + if (sensor_id[0] != tmp_id[0]) { + ret = chip_reg_read(p_tp_dev, sen_id_addr, sensor_id, 1); + ret = chip_reg_read(p_tp_dev, sen_id_addr, tmp_id, 1); + if (sensor_id[0] != tmp_id[0]) { + board_print_error("sensor id is not equal!\n"); + return 0; + } + } + sensor_id[0] &= 0x0F; + return ret; +} + +/******************************************************************************* +* Function Name : read_chip_original_cfg +* Description : read chip original config +* Input : PST_TP_DEV p_tp_dev +* Output : none +* Return : s32(0:Fail >0:read config len) +*******************************************************************************/ +extern s32 read_chip_original_cfg(PST_TP_DEV p_tp_dev) +{ + s32 ret = 0; + switch (p_tp_dev->chip_type) { + case TP_NORMANDY: { + ret = read_cfg_arr(p_tp_dev, p_tp_dev->cfg, 0); + p_tp_dev->cfg_len = ret; + /*updata status flag*/ + p_tp_dev->cfg[1] |= 0x01; + break; + } + default: { + ret = read_cfg_arr(p_tp_dev, p_tp_dev->cfg, p_tp_dev->cfg_len); + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : update_cfg_checksum +* Description : update test config checksum +* Input : PST_TP_DEV p_tp_dev + : u8* test_cfg +* Output : +* Return : void +*******************************************************************************/ +extern void update_cfg_checksum(PST_TP_DEV p_tp_dev, u8 *test_cfg, u16 len) +{ + switch (p_tp_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + normandy_cfg_update_chksum(test_cfg, len); + break; + } + default: { + break; + } + } +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.h new file mode 100644 index 000000000000..d9bc87efc4f5 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/extra_tp_control.h @@ -0,0 +1,26 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : extra_tp_control.h +* Author : +* Version : V1.0.0 +* Date : 30/03/2018 +* Description : tp control func +*******************************************************************************/ +#ifndef EXTRA_TP_CONTROL_H +#define EXTRA_TP_CONTROL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "tp_dev_def.h" + +/*************************************Public methods start********************************************/ +extern s32 read_sensor_id(PST_TP_DEV p_tp_dev, u8 *sensor_id); +extern s32 read_chip_original_cfg(PST_TP_DEV p_tp_dev); +extern void update_cfg_checksum(PST_TP_DEV p_tp_dev, u8 *test_cfg, u16 len); +/*************************************Public methods end********************************************/ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.c new file mode 100644 index 000000000000..a43064ffd622 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.c @@ -0,0 +1,250 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : generic_func.cpp +* Author : +* Version : V1.0.0 +* Date : 07/03/2017 +* Description : init test param interface +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic_func.h" +#include "board_opr_interface.h" +#include "simple_mem_manager.h" +#include + +static s32 test_res_all; +static u8 show_detail_info; + +/******************************************************************************* +* Function Name : set_detail_info_flag +* Description : set detail test info flag +* Input : u8 flag +* Output : none +* Return : none +*******************************************************************************/ +extern void set_detail_info_flag(u8 flag) +{ + show_detail_info = flag; +} +/******************************************************************************* +* Function Name : get_detail_info_flag +* Description : get detail test info flag +* Input : none +* Output : none +* Return : u8(1:save reult in csv file 0:no need save) +*******************************************************************************/ +extern u8 get_detail_info_flag(void) +{ + return show_detail_info; +} + +/******************************************************************************* +* Function Name : getrid_space +* Description : get rid of space +* Input : s8* data + : s32 len +* Output : none +* Return : s32 (length of data) +*******************************************************************************/ +extern s32 getrid_space(s8 *data, s32 len) +{ + u8 *buf = NULL; + s32 i; + u32 count = 0; + + if (alloc_mem_in_heap((void **)&buf, len + 5) == 0) + return (s32)(-1); + for (i = 0; i < len; i++) { + if (data[i] == ' ' || data[i] == '\r' || data[i] == '\n') { + continue; + } + buf[count++] = data[i]; + } + buf[count++] = '\0'; + memcpy(data, buf, count); + free_mem_in_heap(buf); + return count; +} + +extern int atoi(const char *str) +{ + int value = 0; + int sign = 1; + if (str == NULL) + return 0; + while (*str == ' ') { + str++; + } + if (*str == '-') { + sign = -1; + } + + if (*str == '-' || *str == '+') { + str++; + } + /*str to int*/ + while (*str >= '0' && *str <= '9') { + value = value * 10 + *str - '0'; + str++; + } + value = value * sign; + return value; +} +/******************************************************************************* +* Function Name : atohex +* Description : alpha to hex +* Input : s8* buf + : u16 len +* Output : +* Return : u16(0:Fail others:value) +*******************************************************************************/ +extern u16 atohex(u8 *buf, u16 len) +{ + u16 value = 0; + u8 data[10]; + u8 data_len = 0; + u8 i = 0; + if (len == 1) { + data[0] = '0'; + data[1] = buf[0]; + data_len = 2; + } + + if (len >= 2) { + if (buf[0] == '0' && (buf[1] == 'x' || buf[1] == 'X')) { + for (i = 2; i < len; i++) { + data[data_len] = buf[i]; + data_len++; + } + } else { + for (i = 0; i < len; i++) { + data[data_len] = buf[i]; + data_len++; + } + } + } + + for (i = 0; i < data_len; i++) { + if (HEX(data[i])) { + value = value << 4; + if (data[i] >= '0' && data[i] <= '9') { + value |= (data[i] - '0'); + } else if (data[i] >= 'A' && data[i] <= 'F') { + value |= (data[i] - 'A' + 10); + } else if (data[i] >= 'a' && data[i] <= 'f') { + value |= (data[i] - 'a' + 10); + } + } else { + return 0; + board_print_error("HEX string is illegal!\n"); + } + } + return value; +} + +/******************************************************************************* +* Function Name : decstr_to_array +* Description : dec string to integer array(Only use for one byte) +* Input : u8* tmp_value +* Input : u8* txt +* Input : s32 len(max array_value length) +* Output : +* Return : s32(array len) +*******************************************************************************/ +extern s32 decstr_to_array(u8 *tmp_value, u8 *text, s32 len) +{ + s32 i = 0; + u8 *field = NULL; + + field = (u8 *)strsep((char **)&tmp_value, ","); + while (field != NULL) { + text[i] = atoi((const char *)field); + i++; + field = (u8 *)strsep((char **)&tmp_value, ","); + if (i >= len) { + break; + } + } + return i; +} + +/******************************************************************************* +* Function Name : hexstr_to_array +* Description : hex string to integer array +* Input : u8* array_value + : s8* str_param + : s32 len +* Output : +* Return : s32(array len) +*******************************************************************************/ +extern s32 hexstr_to_array(u8 *array_value, s8 *str_param, s32 len) +{ + s32 i = 0; + s32 data_len = 0; + data_len = getrid_space(str_param, strlen((cstr)str_param)); + for (i = 0; i < (data_len + 1) / 5; i++) { + if (i >= len) { + break; + } + array_value[i] = (u8)atohex((u8 *)&str_param[i * 5], 4); + } + return i; +} + +/******************************************************************************* +* Function Name : str_to_int +* Description : string to integer +* Input : s8* data +* Output : +* Return : s32(value) +*******************************************************************************/ +extern s32 str_to_int(s8 *data) +{ + s32 i = 0; + s32 data_len = 0; + data_len = getrid_space(data, strlen((cstr)data)); + i = atoi((cstr)data); + return i; +} + +/******************************************************************************* +* Function Name : init_test_res +* Description : init test result +* Input : none +* Output : none +* Return : s32(test result) +*******************************************************************************/ +extern void init_test_res(void) +{ + test_res_all = 0; +} + +/******************************************************************************* +* Function Name : get_test_res +* Description : get test result +* Input : none +* Output : none +* Return : s32(test result) +*******************************************************************************/ +extern s32 get_test_res(void) +{ + return test_res_all; +} + +/******************************************************************************* +* Function Name : modify_test_result +* Description : modify test result +* Input : none +* Output : none +* Return : s32(test result) +*******************************************************************************/ +extern void modify_test_result(s32 test_res) +{ + test_res_all |= test_res; +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.h new file mode 100644 index 000000000000..f271f6d0f021 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/generic_func.h @@ -0,0 +1,65 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : generic_func +* Author : +* Version : V1.0.0 +* Date : 07/03/2017 +* Description : init test param interface +*******************************************************************************/ +#ifndef GENERIC_FUNC_H +#define GENERIC_FUNC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" + +#include +#include +#include + +#define LIB_VERSION \ + "Goodix Touch Panel Mutiple Production Test Core Version 1.0.2" +#define RESULT_LOG_VERSION "GTLib01.00.0000.01" +#define MAX_BUFFER_SIZE 15000 +#define PATH_LEN 250 +#define HEX(a) \ + ((a >= '0' && a <= '9') || (a >= 'A' && a <= 'F') || \ + (a >= 'a' && a <= 'f')) + +/*---------------------------------LOG DEFINE---------------------------------------*/ +#define BOARD_PRINT(fmt, arg...) \ + do { \ + if (get_detail_info_flag()) { \ + board_print_info(fmt, ##arg); \ + } else { \ + board_print_debug(fmt, ##arg); \ + } \ + } while (0) + +/**********************************operator file*************************************/ + +/*************************************Public methods start********************************************/ +extern u16 atohex(u8 *buf, u16 len); +extern s32 getrid_space(s8 *data, s32 len); +extern s32 hexstr_to_array(u8 *array_value, s8 *str_param, s32 len); +extern s32 str_to_int(s8 *dat); +extern int atoi(const char *str); +extern s32 decstr_to_array(u8 *tmp_value, u8 *text, s32 len); + +/*get test result value*/ +extern s32 get_test_res(void); +/*add the result of test item*/ +extern void modify_test_result(s32 test_res); +extern void init_test_res(void); + +/*set/get detail info flag*/ +extern void set_detail_info_flag(u8 flag); +extern u8 get_detail_info_flag(void); + +/*************************************Public methods start********************************************/ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/memory_override.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/memory_override.c new file mode 100644 index 000000000000..e45d34e88d38 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/memory_override.c @@ -0,0 +1,126 @@ +#include +#include +#include /* for list_head */ +#include +#include +#include "board_opr_interface.h" + +typedef struct memblock_s { + struct list_head list; + void *ptr; + size_t size; +} memblock_t; + +/* +* The list of memory blocks (one simple list) +*/ +static LIST_HEAD(memblock_list); +/*static rwlock_t memblock_lock = RW_LOCK_UNLOCKED;*/ +static DEFINE_RWLOCK(memblock_lock); + +static int memblock_add(void *ptr, size_t size) +{ + memblock_t *m; + m = kmalloc(sizeof(memblock_t), GFP_KERNEL); + if (!m) + return -ENOMEM; + m->ptr = ptr; + m->size = size; + + write_lock(&memblock_lock); + list_add(&m->list, &memblock_list); + write_unlock(&memblock_lock); + return 0; +} + +static void memblock_del(memblock_t *m) +{ + write_lock(&memblock_lock); + list_del(&m->list); + write_unlock(&memblock_lock); + kfree(m); +} + +static memblock_t *memblock_get(void *ptr) +{ + struct list_head *l; + memblock_t *m; + + read_lock(&memblock_lock); + list_for_each(l, &memblock_list) { + m = list_entry(l, memblock_t, list); + if (m->ptr == ptr) { + /* HIT */ + read_unlock(&memblock_lock); + return m; + } + } + read_unlock(&memblock_lock); + return NULL; +} + +void *malloc(size_t size) +{ + void *ptr; + ptr = kmalloc(size, GFP_KERNEL); + if (!ptr) + return NULL; + if (memblock_add(ptr, size)) { + kfree(ptr); + return NULL; + } + return ptr; +} + +void free(void *ptr) +{ + memblock_t *m; + if (!ptr) + return; + m = memblock_get(ptr); + if (!m) { + printk(KERN_ERR "bug: free non-exist memory\n"); + return; + } + memblock_del(m); + kfree(ptr); +} + +void *realloc(void *ptr, size_t size) +{ + memblock_t *m; + void *new = NULL; + + if (ptr) { + m = memblock_get(ptr); + if (!m) { + printk(KERN_ERR "bug: realloc non-exist memory\n"); + return NULL; + } + if (size == m->size) + return ptr; + if (size != 0) { + new = kmalloc(size, GFP_KERNEL); + if (!new) + return NULL; + memmove(new, ptr, m->size); + if (memblock_add(new, size)) { + kfree(new); + return NULL; + } + } + memblock_del(m); + kfree(ptr); + } else { + if (size != 0) { + new = kmalloc(size, GFP_KERNEL); + if (!new) + return NULL; + if (memblock_add(new, size)) { + kfree(new); + return NULL; + } + } + } + return new; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-attr.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-attr.c new file mode 100644 index 000000000000..396be9765217 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-attr.c @@ -0,0 +1,251 @@ +/* + * Attribute support code for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" +#include "mxml.h" + +/* + * Local functions... + */ + +static int mxml_set_attr(mxml_node_t *node, const char *name, char *value); + +/* + * 'mxmlElementDeleteAttr()' - Delete an attribute. + * + * @since Mini-XML 2.4@ + */ + +void mxmlElementDeleteAttr(mxml_node_t *node, /* I - Element */ + const char *name) +{ /* I - Attribute name */ + int i; /* Looping var */ + mxml_attr_t *attr; /* Cirrent attribute */ + + /* Range check input */ + if (!node || node->type != MXML_ELEMENT || !name) + return; + + /* Look for the attribute */ + for (i = node->value.element.num_attrs, + attr = node->value.element.attrs; + i > 0; i--, attr++) { + if (!strcmp(attr->name, name)) { + /* Delete this attribute...*/ + free(attr->name); + free(attr->value); + i--; + if (i > 0) + memmove(attr, attr + 1, + i * sizeof(mxml_attr_t)); + node->value.element.num_attrs--; + if (node->value.element.num_attrs == 0) + free(node->value.element.attrs); + return; + } + } +} + +/* + * 'mxmlElementGetAttr()' - Get an attribute. + * + * This function returns @code NULL@ if the node is not an element or the + * named attribute does not exist. + */ + +const char * /* O - Attribute value or @code NULL@ */ +mxmlElementGetAttr(mxml_node_t *node, /* I - Element node */ + const char *name) +{ /* I - Name of attribute */ + int i; /* Looping var */ + mxml_attr_t *attr; /* Cirrent attribute */ + + /* Range check input... */ + + if (!node || node->type != MXML_ELEMENT || !name) + return NULL; + /* Look for the attribute...*/ + + for (i = node->value.element.num_attrs, + attr = node->value.element.attrs; + i > 0; i--, attr++) { + if (!strcmp(attr->name, name)) { + return attr->value; + } + } + + /* Didn't find attribute, so return NULL... */ + return NULL; +} + +/* + * 'mxmlElementGetAttrByIndex()' - Get an element attribute by index. + * + * The index ("idx") is 0-based. @code NULL@ is returned if the specified index + * is out of range. + * + * @since Mini-XML 2.11@ + */ + +const char * /* O - Attribute value */ +mxmlElementGetAttrByIndex(mxml_node_t *node, /* I - Node */ + int idx, /* I - Attribute index, starting at 0 */ + const char **name) +{ /* O - Attribute name */ + if (!node || node->type != MXML_ELEMENT || idx < 0 || + idx >= node->value.element.num_attrs) + return NULL; + + if (name) + *name = node->value.element.attrs[idx].name; + return node->value.element.attrs[idx].value; +} + +/* + * 'mxmlElementGetAttrCount()' - Get the number of element attributes. + * + * @since Mini-XML 2.11@ + */ + +int mxmlElementGetAttrCount(/* O - Number of attributes */ + mxml_node_t *node) +{ /* I - Node */ + if (node && node->type == MXML_ELEMENT) + return node->value.element.num_attrs; + else + return 0; +} + +/* + * 'mxmlElementSetAttr()' - Set an attribute. + * + * If the named attribute already exists, the value of the attribute + * is replaced by the new string value. The string value is copied + * into the element node. This function does nothing if the node is + * not an element. + */ + +void mxmlElementSetAttr(mxml_node_t *node, /* I - Element node */ + const char *name, /* I - Name of attribute */ + const char *value) +{ /* I - Attribute value */ + char *valuec; /* Copy of value */ + + /* Range check input... */ + + if (!node || node->type != MXML_ELEMENT || !name) + return; + if (value) + valuec = strdup(value); + else + valuec = NULL; + if (mxml_set_attr(node, name, valuec)) + free(valuec); +} + +/* + * 'mxmlElementSetAttrf()' - Set an attribute with a formatted value. + * + * If the named attribute already exists, the value of the attribute + * is replaced by the new formatted string. The formatted string value is + * copied into the element node. This function does nothing if the node + * is not an element. + * + * @since Mini-XML 2.3@ + */ + +void mxmlElementSetAttrf( + mxml_node_t *node, /* I - Element node */ + const char *name, /* I - Name of attribute */ + const char *format, /* I - Printf-style attribute value */ + ...) +{ /* I - Additional arguments as needed */ + va_list ap; /* Argument pointer */ + char *value; /* Value */ + + /* Range check input... */ + if (!node || node->type != MXML_ELEMENT || !name || !format) + return; + + /* Format the value... */ + + va_start(ap, format); + value = _mxml_vstrdupf(format, ap); + va_end(ap); + + if (!value) + mxml_error( + "Unable to allocate memory for attribute '%s' in element %s!", + name, node->value.element.name); + else if (mxml_set_attr(node, name, value)) + free(value); +} + +/* + * 'mxml_set_attr()' - Set or add an attribute name/value pair. + */ +/* O - 0 on success, -1 on failure */ +static int mxml_set_attr(mxml_node_t *node, /* I - Element node */ + const char *name, /* I - Attribute name */ + char *value) +{ /* I - Attribute value */ + int i; /* Looping var */ + mxml_attr_t *attr; /* New attribute */ + + /* Look for the attribute... */ + + for (i = node->value.element.num_attrs, + attr = node->value.element.attrs; + i > 0; i--, attr++) + if (!strcmp(attr->name, name)) { + /* Free the old value as needed... */ + if (attr->value) + free(attr->value); + attr->value = value; + return 0; + } + /* Add a new attribute... */ + + if (node->value.element.num_attrs == 0) + attr = malloc(sizeof(mxml_attr_t)); + else + attr = realloc(node->value.element.attrs, + (node->value.element.num_attrs + 1) * + sizeof(mxml_attr_t)); + + if (!attr) { + mxml_error( + "Unable to allocate memory for attribute '%s' in element %s!", + name, node->value.element.name); + return (-1); + } + + node->value.element.attrs = attr; + attr += node->value.element.num_attrs; + attr->name = strdup(name); + if (attr->name == NULL) { + mxml_error( + "Unable to allocate memory for attribute '%s' in element %s!", + name, node->value.element.name); + return (-1); + } + attr->value = value; + node->value.element.num_attrs++; + return 0; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-entity.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-entity.c new file mode 100644 index 000000000000..1c1e6e07e929 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-entity.c @@ -0,0 +1,246 @@ +/* + * Character entity support code for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "mxml-private.h" + +/* + * 'mxmlEntityAddCallback()' - Add a callback to convert entities to Unicode. + */ +/* O - 0 on success, -1 on failure */ +int mxmlEntityAddCallback(mxml_entity_cb_t cb) +{ /* I - Callback function to add */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + + if (global->num_entity_cbs < + (int)(sizeof(global->entity_cbs) / sizeof(global->entity_cbs[0]))) { + global->entity_cbs[global->num_entity_cbs] = cb; + global->num_entity_cbs++; + + return 0; + } else { + mxml_error("Unable to add entity callback!"); + return (-1); + } +} + +/* + * 'mxmlEntityGetName()' - Get the name that corresponds to the character value. + * + * If val does not need to be represented by a named entity, @code NULL@ is returned. + */ + +const char * /* O - Entity name or @code NULL@ */ +mxmlEntityGetName(int val) +{ /* I - Character value */ + switch (val) { + case '&': + return "amp"; + + case '<': + return "lt"; + + case '>': + return "gt"; + + case '\"': + return "quot"; + + default: + return NULL; + } +} + +/* + * 'mxmlEntityGetValue()' - Get the character corresponding to a named entity. + * + * The entity name can also be a numeric constant. -1 is returned if the + * name is not known. + */ +/* O - Character value or -1 on error */ +int mxmlEntityGetValue(const char *name) +{ /* I - Entity name */ + int i; /* Looping var */ + int ch; /* Character value */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + + for (i = 0; i < global->num_entity_cbs; i++) { + ch = (global->entity_cbs[i])(name); + if (ch >= 0) + return ch; + } + return (int)(-1); +} + +/* + * 'mxmlEntityRemoveCallback()' - Remove a callback. + */ + +void mxmlEntityRemoveCallback(mxml_entity_cb_t cb) +{ /* I - Callback function to remove */ + int i; /* Looping var */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + + for (i = 0; i < global->num_entity_cbs; i++) + if (cb == global->entity_cbs[i]) { + /* Remove the callback... */ + global->num_entity_cbs--; + if (i < global->num_entity_cbs) + memmove(global->entity_cbs + i, + global->entity_cbs + i + 1, + (global->num_entity_cbs - i) * + sizeof(global->entity_cbs[0])); + return; + } +} + +/* + * '_mxml_entity_cb()' - Lookup standard (X)HTML entities. + */ + +int _mxml_entity_cb(const char *name) /* O - Unicode value or -1 */ +{ /* I - Entity name */ + int diff; /* Difference between names */ + int curent; /* Current entity in search */ + int first; /* First entity in search */ + int last; /* Last entity in search */ + static const struct { + const char *name; /* Entity name */ + int val; /* Character value */ + } entities[] = { + { "AElig", 198 }, { "Aacute", 193 }, { "Acirc", 194 }, + { "Agrave", 192 }, { "Alpha", 913 }, { "Aring", 197 }, + { "Atilde", 195 }, { "Auml", 196 }, { "Beta", 914 }, + { "Ccedil", 199 }, { "Chi", 935 }, { "Dagger", 8225 }, + { "Delta", 916 }, { "Dstrok", 208 }, { "ETH", 208 }, + { "Eacute", 201 }, { "Ecirc", 202 }, { "Egrave", 200 }, + { "Epsilon", 917 }, { "Eta", 919 }, { "Euml", 203 }, + { "Gamma", 915 }, { "Iacute", 205 }, { "Icirc", 206 }, + { "Igrave", 204 }, { "Iota", 921 }, { "Iuml", 207 }, + { "Kappa", 922 }, { "Lambda", 923 }, { "Mu", 924 }, + { "Ntilde", 209 }, { "Nu", 925 }, { "OElig", 338 }, + { "Oacute", 211 }, { "Ocirc", 212 }, { "Ograve", 210 }, + { "Omega", 937 }, { "Omicron", 927 }, { "Oslash", 216 }, + { "Otilde", 213 }, { "Ouml", 214 }, { "Phi", 934 }, + { "Pi", 928 }, { "Prime", 8243 }, { "Psi", 936 }, + { "Rho", 929 }, { "Scaron", 352 }, { "Sigma", 931 }, + { "THORN", 222 }, { "Tau", 932 }, { "Theta", 920 }, + { "Uacute", 218 }, { "Ucirc", 219 }, { "Ugrave", 217 }, + { "Upsilon", 933 }, { "Uuml", 220 }, { "Xi", 926 }, + { "Yacute", 221 }, { "Yuml", 376 }, { "Zeta", 918 }, + { "aacute", 225 }, { "acirc", 226 }, { "acute", 180 }, + { "aelig", 230 }, { "agrave", 224 }, { "alefsym", 8501 }, + { "alpha", 945 }, { "amp", '&' }, { "and", 8743 }, + { "ang", 8736 }, { "apos", '\'' }, { "aring", 229 }, + { "asymp", 8776 }, { "atilde", 227 }, { "auml", 228 }, + { "bdquo", 8222 }, { "beta", 946 }, { "brkbar", 166 }, + { "brvbar", 166 }, { "bull", 8226 }, { "cap", 8745 }, + { "ccedil", 231 }, { "cedil", 184 }, { "cent", 162 }, + { "chi", 967 }, { "circ", 710 }, { "clubs", 9827 }, + { "cong", 8773 }, { "copy", 169 }, { "crarr", 8629 }, + { "cup", 8746 }, { "curren", 164 }, { "dArr", 8659 }, + { "dagger", 8224 }, { "darr", 8595 }, { "deg", 176 }, + { "delta", 948 }, { "diams", 9830 }, { "die", 168 }, + { "divide", 247 }, { "eacute", 233 }, { "ecirc", 234 }, + { "egrave", 232 }, { "empty", 8709 }, { "emsp", 8195 }, + { "ensp", 8194 }, { "epsilon", 949 }, { "equiv", 8801 }, + { "eta", 951 }, { "eth", 240 }, { "euml", 235 }, + { "euro", 8364 }, { "exist", 8707 }, { "fnof", 402 }, + { "forall", 8704 }, { "frac12", 189 }, { "frac14", 188 }, + { "frac34", 190 }, { "frasl", 8260 }, { "gamma", 947 }, + { "ge", 8805 }, { "gt", '>' }, { "hArr", 8660 }, + { "harr", 8596 }, { "hearts", 9829 }, { "hellip", 8230 }, + { "hibar", 175 }, { "iacute", 237 }, { "icirc", 238 }, + { "iexcl", 161 }, { "igrave", 236 }, { "image", 8465 }, + { "infin", 8734 }, { "int", 8747 }, { "iota", 953 }, + { "iquest", 191 }, { "isin", 8712 }, { "iuml", 239 }, + { "kappa", 954 }, { "lArr", 8656 }, { "lambda", 955 }, + { "lang", 9001 }, { "laquo", 171 }, { "larr", 8592 }, + { "lceil", 8968 }, { "ldquo", 8220 }, { "le", 8804 }, + { "lfloor", 8970 }, { "lowast", 8727 }, { "loz", 9674 }, + { "lrm", 8206 }, { "lsaquo", 8249 }, { "lsquo", 8216 }, + { "lt", '<' }, { "macr", 175 }, { "mdash", 8212 }, + { "micro", 181 }, { "middot", 183 }, { "minus", 8722 }, + { "mu", 956 }, { "nabla", 8711 }, { "nbsp", 160 }, + { "ndash", 8211 }, { "ne", 8800 }, { "ni", 8715 }, + { "not", 172 }, { "notin", 8713 }, { "nsub", 8836 }, + { "ntilde", 241 }, { "nu", 957 }, { "oacute", 243 }, + { "ocirc", 244 }, { "oelig", 339 }, { "ograve", 242 }, + { "oline", 8254 }, { "omega", 969 }, { "omicron", 959 }, + { "oplus", 8853 }, { "or", 8744 }, { "ordf", 170 }, + { "ordm", 186 }, { "oslash", 248 }, { "otilde", 245 }, + { "otimes", 8855 }, { "ouml", 246 }, { "para", 182 }, + { "part", 8706 }, { "permil", 8240 }, { "perp", 8869 }, + { "phi", 966 }, { "pi", 960 }, { "piv", 982 }, + { "plusmn", 177 }, { "pound", 163 }, { "prime", 8242 }, + { "prod", 8719 }, { "prop", 8733 }, { "psi", 968 }, + { "quot", '\"' }, { "rArr", 8658 }, { "radic", 8730 }, + { "rang", 9002 }, { "raquo", 187 }, { "rarr", 8594 }, + { "rceil", 8969 }, { "rdquo", 8221 }, { "real", 8476 }, + { "reg", 174 }, { "rfloor", 8971 }, { "rho", 961 }, + { "rlm", 8207 }, { "rsaquo", 8250 }, { "rsquo", 8217 }, + { "sbquo", 8218 }, { "scaron", 353 }, { "sdot", 8901 }, + { "sect", 167 }, { "shy", 173 }, { "sigma", 963 }, + { "sigmaf", 962 }, { "sim", 8764 }, { "spades", 9824 }, + { "sub", 8834 }, { "sube", 8838 }, { "sum", 8721 }, + { "sup", 8835 }, { "sup1", 185 }, { "sup2", 178 }, + { "sup3", 179 }, { "supe", 8839 }, { "szlig", 223 }, + { "tau", 964 }, { "there4", 8756 }, { "theta", 952 }, + { "thetasym", 977 }, { "thinsp", 8201 }, { "thorn", 254 }, + { "tilde", 732 }, { "times", 215 }, { "trade", 8482 }, + { "uArr", 8657 }, { "uacute", 250 }, { "uarr", 8593 }, + { "ucirc", 251 }, { "ugrave", 249 }, { "uml", 168 }, + { "upsih", 978 }, { "upsilon", 965 }, { "uuml", 252 }, + { "weierp", 8472 }, { "xi", 958 }, { "yacute", 253 }, + { "yen", 165 }, { "yuml", 255 }, { "zeta", 950 }, + { "zwj", 8205 }, { "zwnj", 8204 } + }; + + /* + * Do a binary search for the named entity... + */ + + first = 0; + last = (int)(sizeof(entities) / sizeof(entities[0]) - 1); + + while ((last - first) > 1) { + curent = (first + last) / 2; + diff = strcmp(name, entities[curent].name); + if (diff == 0) + return entities[curent].val; + else if (diff < 0) + last = curent; + else + first = curent; + } + + /* + * If we get here, there is a small chance that there is still + * a match; check first and last... + */ + + if (!strcmp(name, entities[first].name)) + return entities[first].val; + else if (!strcmp(name, entities[last].name)) + return entities[last].val; + else + return (-1); +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-file.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-file.c new file mode 100644 index 000000000000..54881fff5d72 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-file.c @@ -0,0 +1,1626 @@ +/* + * File loading code for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#ifndef WIN32 +#endif /* !WIN32 */ +#include "mxml-private.h" +#include + +/* + * Character encoding... + */ + +#define ENCODE_UTF8 0 /* UTF-8 */ +#define ENCODE_UTF16BE 1 /* UTF-16 Big-Endian */ +#define ENCODE_UTF16LE 2 /* UTF-16 Little-Endian */ + +/* + * Macro to test for a bad XML character... + */ + +#define mxml_bad_char(ch) \ + ((ch) < ' ' && (ch) != '\n' && (ch) != '\r' && (ch) != '\t') + +/* + * Types and structures... + */ + +typedef int (*_mxml_getc_cb_t)(void *, int *); +typedef int (*_mxml_putc_cb_t)(int, void *); + +typedef struct _mxml_fdbuf_s { + /**** File descriptor buffer ****/ + int fd; /* File descriptor */ + unsigned char *curr, /* Current position in buffer */ + *end, /* End of buffer */ + buffer[8192]; /* Character buffer */ +} _mxml_fdbuf_t; + +/* + * Local functions... + */ + +static int mxml_add_char(int ch, char **ptr, char **buffer, int *bufsize); + +static int mxml_get_entity(mxml_node_t *parent, void *p, int *encoding, + _mxml_getc_cb_t getc_cb); +static inline int mxml_isspace(int ch) +{ + return (ch == ' ' || ch == '\t' || ch == '\r' || ch == '\n'); +} + +static mxml_node_t *mxml_load_data(mxml_node_t *top, void *p, mxml_load_cb_t cb, + _mxml_getc_cb_t getc_cb, + mxml_sax_cb_t sax_cb, void *sax_data); +static int mxml_parse_element(mxml_node_t *node, void *p, int *encoding, + _mxml_getc_cb_t getc_cb); +static int mxml_string_getc(void *p, int *encoding); +static int mxml_string_putc(int ch, void *p); +static int mxml_write_name(const char *s, void *p, _mxml_putc_cb_t putc_cb); +static int mxml_write_node(mxml_node_t *node, void *p, mxml_save_cb_t cb, + int col, _mxml_putc_cb_t putc_cb, + _mxml_global_t *global); +static int mxml_write_string(const char *s, void *p, _mxml_putc_cb_t putc_cb); +static int mxml_write_ws(mxml_node_t *node, void *p, mxml_save_cb_t cb, int ws, + int col, _mxml_putc_cb_t putc_cb); + +/* + * 'mxmlLoadString()' - Load a string into an XML node tree. + * + * The nodes in the specified string are added to the specified top node. + * If no top node is provided, the XML string MUST be well-formed with a + * single parent node like for the entire string. The callback + * function returns the value type that should be used for child nodes. + * The constants @code MXML_INTEGER_CALLBACK@, @code MXML_OPAQUE_CALLBACK@, + * @code MXML_REAL_CALLBACK@, and @code MXML_TEXT_CALLBACK@ are defined for + * loading child (data) nodes of the specified type. + */ + +mxml_node_t * /* O - First node or @code NULL@ if the string has errors. */ +mxmlLoadString(mxml_node_t *top, /* I - Top node */ + const char *s, /* I - String to load */ + mxml_load_cb_t cb) +{ /* I - Callback function or constant */ + /* + * Read the XML data... + */ + + return (mxml_load_data(top, (void *)&s, cb, mxml_string_getc, + MXML_NO_CALLBACK, NULL)); +} + +/* + * 'mxmlSaveAllocString()' - Save an XML tree to an allocated string. + * + * This function returns a pointer to a string containing the textual + * representation of the XML node tree. The string should be freed + * using the free() function when you are done with it. @code NULL@ is returned + * if the node would produce an empty string or if the string cannot be + * allocated. + * + * The callback argument specifies a function that returns a whitespace + * string or NULL before and after each element. If @code MXML_NO_CALLBACK@ + * is specified, whitespace will only be added before @code MXML_TEXT@ nodes + * with leading whitespace and before attribute names inside opening + * element tags. + */ + +char * /* O - Allocated string or @code NULL@ */ +mxmlSaveAllocString(mxml_node_t *node, /* I - Node to write */ + mxml_save_cb_t cb) +{ /* I - Whitespace callback or @code MXML_NO_CALLBACK@ */ + int bytes; /* Required bytes */ + //char buffer[2000]; /* Temporary buffer */ + char buffer[512]; /* Temporary buffer */ + char *s; /* Allocated string */ + + /* + * Write the node to the temporary buffer... + */ + + bytes = mxmlSaveString(node, buffer, sizeof(buffer), cb); + + if (bytes <= 0) + return NULL; + if (bytes < (int)(sizeof(buffer) - 1)) { + /* + * Node fit inside the buffer, so just duplicate that string and + * return... + */ + return strdup(buffer); + } + /* + * Allocate a buffer of the required size and save the node to the + * new buffer... + */ + s = malloc(bytes + 1); + if (s == NULL) + return NULL; + + mxmlSaveString(node, s, bytes + 1, cb); + /* Return the allocated string... */ + return s; +} + +/* + * 'mxmlSaveString()' - Save an XML node tree to a string. + * + * This function returns the total number of bytes that would be + * required for the string but only copies (bufsize - 1) characters + * into the specified buffer. + * + * The callback argument specifies a function that returns a whitespace + * string or NULL before and after each element. If @code MXML_NO_CALLBACK@ + * is specified, whitespace will only be added before @code MXML_TEXT@ nodes + * with leading whitespace and before attribute names inside opening + * element tags. + */ +/* O - Size of string */ +int mxmlSaveString(mxml_node_t *node, /* I - Node to write */ + char *buffer, /* I - String buffer */ + int bufsize, /* I - Size of string buffer */ + mxml_save_cb_t cb) +{ /* I - Whitespace callback or @code MXML_NO_CALLBACK@ */ + int col; /* Final column */ + char *ptr[2]; /* Pointers for putc_cb */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + /* Write the node... */ + ptr[0] = buffer; + ptr[1] = buffer + bufsize; + col = mxml_write_node(node, ptr, cb, 0, mxml_string_putc, global); + if (col < 0) + return (-1); + + if (col > 0) + mxml_string_putc('\n', ptr); + + /* Nul-terminate the buffer... */ + + if (ptr[0] >= ptr[1]) + buffer[bufsize - 1] = '\0'; + else + ptr[0][0] = '\0'; + /* Return the number of characters... */ + return ((int)(ptr[0] - buffer)); +} + +/* + * 'mxmlSAXLoadString()' - Load a string into an XML node tree + * using a SAX callback. + * + * The nodes in the specified string are added to the specified top node. + * If no top node is provided, the XML string MUST be well-formed with a + * single parent node like for the entire string. The callback + * function returns the value type that should be used for child nodes. + * The constants @code MXML_INTEGER_CALLBACK@, @code MXML_OPAQUE_CALLBACK@, + * @code MXML_REAL_CALLBACK@, and @code MXML_TEXT_CALLBACK@ are defined for + * loading child nodes of the specified type. + * + * The SAX callback must call @link mxmlRetain@ for any nodes that need to + * be kept for later use. Otherwise, nodes are deleted when the parent + * node is closed or after each data, comment, CDATA, or directive node. + * + * @since Mini-XML 2.3@ + */ + +mxml_node_t * /* O - First node or @code NULL@ if the string has errors. */ +mxmlSAXLoadString( + mxml_node_t *top, /* I - Top node */ + const char *s, /* I - String to load */ + mxml_load_cb_t cb, /* I - Callback function or constant */ + mxml_sax_cb_t sax_cb, /* I - SAX callback or @code MXML_NO_CALLBACK@ */ + void *sax_data) +{ /* I - SAX user data */ + /* Read the XML data... */ + return (mxml_load_data(top, (void *)&s, cb, mxml_string_getc, sax_cb, + sax_data)); +} + +/* + * 'mxmlSetCustomHandlers()' - Set the handling functions for custom data. + * + * The load function accepts a node pointer and a data string and must + * return 0 on success and non-zero on error. + * + * The save function accepts a node pointer and must return a malloc'd + * string on success and @code NULL@ on error. + * + */ + +void mxmlSetCustomHandlers(mxml_custom_load_cb_t load, /* I - Load function */ + mxml_custom_save_cb_t save) +{ /* I - Save function */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + global->custom_load_cb = load; + global->custom_save_cb = save; +} + +/* + * 'mxmlSetErrorCallback()' - Set the error message callback. + */ + +void mxmlSetErrorCallback(mxml_error_cb_t cb) +{ /* I - Error callback function */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + global->error_cb = cb; +} + +/* + * 'mxmlSetWrapMargin()' - Set the wrap margin when saving XML data. + * + * Wrapping is disabled when "column" is 0. + * + * @since Mini-XML 2.3@ + */ + +void mxmlSetWrapMargin(int column) +{ /* I - Column for wrapping, 0 to disable wrapping */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + global->wrap = column; +} + +/* + * 'mxml_add_char()' - Add a character to a buffer, expanding as needed. + */ + +static int /* O - 0 on success, -1 on error */ +mxml_add_char(int ch, /* I - Character to add */ + char **bufptr, /* IO - Current position in buffer */ + char **buffer, /* IO - Current buffer */ + int *bufsize) +{ /* IO - Current buffer size */ + char *newbuffer; /* New buffer value */ + if (*bufptr >= (*buffer + *bufsize - 4)) { + /* Increase the size of the buffer... */ + if (*bufsize < 1024) + (*bufsize) *= 2; + else + (*bufsize) += 1024; + newbuffer = realloc(*buffer, *bufsize); + if (newbuffer == NULL) { + free(*buffer); + mxml_error( + "Unable to expand string buffer to %d bytes!", + *bufsize); + return (-1); + } + *bufptr = newbuffer + (*bufptr - *buffer); + *buffer = newbuffer; + } + + if (ch < 0x80) { + /* Single byte ASCII... */ + *(*bufptr)++ = ch; + } else if (ch < 0x800) { + /* Two-byte UTF-8... */ + *(*bufptr)++ = 0xc0 | (ch >> 6); + *(*bufptr)++ = 0x80 | (ch & 0x3f); + } else if (ch < 0x10000) { + /* Three-byte UTF-8... */ + *(*bufptr)++ = 0xe0 | (ch >> 12); + *(*bufptr)++ = 0x80 | ((ch >> 6) & 0x3f); + *(*bufptr)++ = 0x80 | (ch & 0x3f); + } else { + /* Four-byte UTF-8... */ + *(*bufptr)++ = 0xf0 | (ch >> 18); + *(*bufptr)++ = 0x80 | ((ch >> 12) & 0x3f); + *(*bufptr)++ = 0x80 | ((ch >> 6) & 0x3f); + *(*bufptr)++ = 0x80 | (ch & 0x3f); + } + return 0; +} + +/* + * 'mxml_get_entity()' - Get the character corresponding to an entity... + */ + +static int mxml_get_entity(mxml_node_t *parent, void *p, int *encoding, + int (*getc_cb)(void *, int *)) +{ + int ch; /* Current character */ + char entity[64], /* Entity string */ + *entptr; /* Pointer into entity */ + + entptr = entity; + while ((ch = (*getc_cb)(p, encoding)) != EOF) + if (ch > 126 || (!isalnum(ch) && ch != '#')) + break; + else if (entptr < (entity + sizeof(entity) - 1)) + *entptr++ = ch; + else { + mxml_error("Entity name too long under parent <%s>!", + parent ? parent->value.element.name : + "null"); + break; + } + + *entptr = '\0'; + if (ch != ';') { + mxml_error( + "Character entity \"%s\" not terminated under parent <%s>!", + entity, parent ? parent->value.element.name : "null"); + return EOF; + } + + if (entity[0] == '#') { + if (entity[1] == 'x') + ch = (int)strtol(entity + 2, NULL, 16); + else + ch = (int)strtol(entity + 1, NULL, 10); + } else { + ch = mxmlEntityGetValue(entity); + if (ch < 0) + mxml_error( + "Entity name \"%s;\" not supported under parent <%s>!", + entity, + parent ? parent->value.element.name : "null"); + } + if (mxml_bad_char(ch)) { + mxml_error( + "Bad control character 0x%02x under parent <%s> not allowed by XML standard!", + ch, parent ? parent->value.element.name : "null"); + return EOF; + } + return ch; +} + +/* + * 'mxml_load_data()' - Load data into an XML node tree. + */ + +static mxml_node_t * /* O - First node or NULL if the file could not be read. */ +mxml_load_data(mxml_node_t *top, /* I - Top node */ + void *p, /* I - Pointer to data */ + mxml_load_cb_t cb, /* I - Callback function or MXML_NO_CALLBACK */ + _mxml_getc_cb_t getc_cb, /* I - Read function */ + mxml_sax_cb_t sax_cb, /* I - SAX callback or MXML_NO_CALLBACK */ + void *sax_data) +{ /* I - SAX user data */ + mxml_node_t *node = NULL, /* Current node */ + *first = NULL, /* First node added */ + *parent = NULL; /* Current parent node */ + int ch, /* Character from file */ + whitespace; /* Non-zero if whitespace seen */ + char *buffer = NULL, /* String buffer */ + *bufptr = NULL; /* Pointer into buffer */ + int bufsize; /* Size of buffer */ + mxml_type_t type; /* Current node type */ + int encoding; /* Character encoding */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + static const char *const types[] = /* Type strings... */ + { + "MXML_ELEMENT", /* XML element with attributes */ + "MXML_INTEGER", /* Integer value */ + "MXML_OPAQUE", /* Opaque string */ + "MXML_REAL", /* Real value */ + "MXML_TEXT", /* Text fragment */ + "MXML_CUSTOM" /* Custom data */ + }; + + /* + * Read elements and other nodes from the file... + */ + buffer = malloc(64); + if (buffer == NULL) { + mxml_error("Unable to allocate string buffer!"); + return NULL; + } + + bufsize = 64; + bufptr = buffer; + parent = top; + first = NULL; + whitespace = 0; + encoding = ENCODE_UTF8; + + if (cb && parent) + type = (*cb)(parent); + else if (parent) + type = MXML_TEXT; + else + type = MXML_IGNORE; + + while ((ch = (*getc_cb)(p, &encoding)) != EOF) { + if ((ch == '<' || (mxml_isspace(ch) && type != MXML_OPAQUE && + type != MXML_CUSTOM)) && + bufptr > buffer) { + /* Add a new value node... */ + + *bufptr = '\0'; + switch (type) { + case MXML_INTEGER: + node = mxmlNewInteger(parent, + (int)strtol(buffer, + &bufptr, 0)); + break; + + case MXML_OPAQUE: + node = mxmlNewOpaque(parent, buffer); + break; + + case MXML_REAL: + break; + + case MXML_TEXT: + node = mxmlNewText(parent, whitespace, buffer); + break; + + case MXML_CUSTOM: + if (global->custom_load_cb) { + /* * Use the callback to fill in the custom data... */ + node = mxmlNewCustom(parent, NULL, + NULL); + if ((*global->custom_load_cb)(node, + buffer)) { + mxml_error( + "Bad custom value '%s' in parent <%s>!", + buffer, + parent ? + parent->value + .element + .name : + "null"); + mxmlDelete(node); + node = NULL; + } + break; + } + + default: /* Ignore... */ + node = NULL; + break; + } + + if (*bufptr) { + /* Bad integer/real number value... */ + + mxml_error("Bad %s value '%s' in parent <%s>!", + type == MXML_INTEGER ? "integer" : + "real", + buffer, + parent ? parent->value.element.name : + "null"); + break; + } + + bufptr = buffer; + whitespace = mxml_isspace(ch) && type == MXML_TEXT; + + if (!node && type != MXML_IGNORE) { + /* Print error and return... */ + mxml_error( + "Unable to add value node of type %s to parent <%s>!", + types[type], + parent ? parent->value.element.name : + "null"); + goto error; + } + + if (sax_cb) { + (*sax_cb)(node, MXML_SAX_DATA, sax_data); + + if (!mxmlRelease(node)) + node = NULL; + } + + if (!first && node) + first = node; + } else if (mxml_isspace(ch) && type == MXML_TEXT) + whitespace = 1; + + /* + * Add lone whitespace node if we have an element and existing + * whitespace... + */ + + if (ch == '<' && whitespace && type == MXML_TEXT) { + if (parent) { + node = mxmlNewText(parent, whitespace, ""); + if (sax_cb) { + (*sax_cb)(node, MXML_SAX_DATA, + sax_data); + if (!mxmlRelease(node)) + node = NULL; + } + if (!first && node) + first = node; + } + whitespace = 0; + } + + if (ch == '<') { + /* Start of open/close tag... */ + bufptr = buffer; + while ((ch = (*getc_cb)(p, &encoding)) != EOF) + if (mxml_isspace(ch) || ch == '>' || + (ch == '/' && bufptr > buffer)) + break; + else if (ch == '<') { + mxml_error("Bare < in element!"); + goto error; + } else if (ch == '&') { + ch = mxml_get_entity( + parent, p, &encoding, getc_cb); + if (ch == EOF) + goto error; + if (mxml_add_char(ch, &bufptr, &buffer, + &bufsize)) + goto error; + } else if (ch < '0' && ch != '!' && ch != '-' && + ch != '.' && ch != '/') + goto error; + else if (mxml_add_char(ch, &bufptr, &buffer, + &bufsize)) + goto error; + else if (((bufptr - buffer) == 1 && + buffer[0] == '?') || + ((bufptr - buffer) == 3 && + !strncmp(buffer, "!--", 3)) || + ((bufptr - buffer) == 8 && + !strncmp(buffer, "![CDATA[", 8))) + break; + + *bufptr = '\0'; + if (!strcmp(buffer, "!--")) { + /* Gather rest of comment... */ + while ((ch = (*getc_cb)(p, &encoding)) != EOF) { + if (ch == '>' && + bufptr > (buffer + 4) && + bufptr[-3] != '-' && + bufptr[-2] == '-' && + bufptr[-1] == '-') + break; + else if (mxml_add_char(ch, &bufptr, + &buffer, + &bufsize)) + goto error; + } + + /* Error out if we didn't get the whole comment... */ + if (ch != '>') { + /* Print error and return... */ + + mxml_error( + "Early EOF in comment node!"); + goto error; + } + /* Otherwise add this as an element under the curr parent... */ + *bufptr = '\0'; + if (!parent && first) { + /* There can only be one root element! */ + mxml_error( + "<%s> cannot be a second root node after <%s>", + buffer, + first->value.element.name); + goto error; + } + node = mxmlNewElement(parent, buffer); + if (node == NULL) { + /* Just print error for now... */ + mxml_error( + "Unable to add comment node to parent <%s>!", + parent ? parent->value.element + .name : + "null"); + break; + } + + if (sax_cb) { + (*sax_cb)(node, MXML_SAX_COMMENT, + sax_data); + if (!mxmlRelease(node)) + node = NULL; + } + if (node && !first) + first = node; + } else if (!strcmp(buffer, "![CDATA[")) { + /* Gather CDATA section... */ + while ((ch = (*getc_cb)(p, &encoding)) != EOF) { + if (ch == '>' && + !strncmp(bufptr - 2, "]]", 2)) { + /* Drop terminator from CDATA string... */ + bufptr[-2] = '\0'; + break; + } else if (mxml_add_char(ch, &bufptr, + &buffer, + &bufsize)) + goto error; + } + /* Error out if we didn't get the whole comment... */ + if (ch != '>') { + /* Print error and return... */ + mxml_error("Early EOF in CDATA node!"); + goto error; + } + /* Otherwise add this as an element under the curr parent... */ + + *bufptr = '\0'; + + if (!parent && first) { + /* There can only be one root element! */ + mxml_error( + "<%s> cannot be a second root node after <%s>", + buffer, + first->value.element.name); + goto error; + } + node = mxmlNewElement(parent, buffer); + if (node == NULL) { + /* Print error and return... */ + mxml_error( + "Unable to add CDATA node to parent <%s>!", + parent ? parent->value.element + .name : + "null"); + goto error; + } + + if (sax_cb) { + (*sax_cb)(node, MXML_SAX_CDATA, + sax_data); + if (!mxmlRelease(node)) + node = NULL; + } + if (node && !first) + first = node; + } else if (buffer[0] == '?') { + /* Gather rest of processing instruction... */ + while ((ch = (*getc_cb)(p, &encoding)) != EOF) { + if (ch == '>' && bufptr > buffer && + bufptr[-1] == '?') + break; + else if (mxml_add_char(ch, &bufptr, + &buffer, + &bufsize)) + goto error; + } + + /* Error out if we didn't get the whole processing instruction... */ + if (ch != '>') { + /* Print error and return... */ + mxml_error( + "Early EOF in processing instruction node!"); + goto error; + } + /* Otherwise add this as an element under the current parent... */ + *bufptr = '\0'; + if (!parent && first) { + /* * There can only be one root element! */ + mxml_error( + "<%s> cannot be a second root node after <%s>", + buffer, + first->value.element.name); + goto error; + } + node = mxmlNewElement(parent, buffer); + if (node == NULL) { + /* Print error and return... */ + mxml_error( + "Unable to add processing instruction node to parent <%s>!", + parent ? parent->value.element + .name : + "null"); + goto error; + } + + if (sax_cb) { + (*sax_cb)(node, MXML_SAX_DIRECTIVE, + sax_data); + if (!mxmlRelease(node)) + node = NULL; + } + + if (node) { + if (!first) + first = node; + if (!parent) { + parent = node; + if (cb) + type = (*cb)(parent); + else + type = MXML_TEXT; + } + } + } else if (buffer[0] == '!') { + /* Gather rest of declaration... */ + do { + if (ch == '>') + break; + else { + if (ch == '&') { + ch = mxml_get_entity( + parent, p, + &encoding, + getc_cb); + if (ch == EOF) + goto error; + } + if (mxml_add_char(ch, &bufptr, + &buffer, + &bufsize)) + goto error; + } + } while ((ch = (*getc_cb)(p, &encoding)) != + EOF); + /* Error out if we didn't get the whole declaration... */ + if (ch != '>') { + /* Print error and return... */ + mxml_error( + "Early EOF in declaration node!"); + goto error; + } + /* Otherwise add this as an element under the current parent... */ + *bufptr = '\0'; + if (!parent && first) { + /* * There can only be one root element! */ + mxml_error( + "<%s> cannot be a second root node after <%s>", + buffer, + first->value.element.name); + goto error; + } + node = mxmlNewElement(parent, buffer); + if (node == NULL) { + /* * Print error and return... */ + mxml_error( + "Unable to add declaration node to parent <%s>!", + parent ? parent->value.element + .name : + "null"); + goto error; + } + + if (sax_cb) { + (*sax_cb)(node, MXML_SAX_DIRECTIVE, + sax_data); + if (!mxmlRelease(node)) + node = NULL; + } + + if (node) { + if (!first) + first = node; + if (!parent) { + parent = node; + if (cb) + type = (*cb)(parent); + else + type = MXML_TEXT; + } + } + } else if (buffer[0] == '/') { + /* Handle close tag... */ + if (!parent || + strcmp(buffer + 1, + parent->value.element.name)) { + /* * Close tag doesn't match tree; print an error for now... */ + mxml_error( + "Mismatched close tag <%s> under parent <%s>!", + buffer, + parent ? parent->value.element + .name : + "(null)"); + goto error; + } + + /* * Keep reading until we see >... */ + while (ch != '>' && ch != EOF) + ch = (*getc_cb)(p, &encoding); + node = parent; + parent = parent->parent; + if (sax_cb) { + (*sax_cb)(node, MXML_SAX_ELEMENT_CLOSE, + sax_data); + if (!mxmlRelease(node) && first == node) + first = NULL; + } + /* * Ascend into the parent and set the value type as needed... */ + if (cb && parent) + type = (*cb)(parent); + } else { + /* * Handle open tag... */ + if (!parent && first) { + /* * There can only be one root element! */ + mxml_error( + "<%s> cannot be a second root node after <%s>", + buffer, + first->value.element.name); + goto error; + } + node = mxmlNewElement(parent, buffer); + if (node == NULL) { + /* * Just print error for now... */ + mxml_error( + "Unable to add element node to parent <%s>!", + parent ? parent->value.element + .name : + "null"); + goto error; + } + + if (mxml_isspace(ch)) { + ch = mxml_parse_element( + node, p, &encoding, getc_cb); + if (ch == EOF) + goto error; + } else if (ch == '/') { + ch = (*getc_cb)(p, &encoding); + if (ch != '>') { + mxml_error( + "Expected > but got '%c' instead for element <%s/>!", + ch, buffer); + mxmlDelete(node); + goto error; + } + ch = '/'; + } + if (sax_cb) + (*sax_cb)(node, MXML_SAX_ELEMENT_OPEN, + sax_data); + if (!first) + first = node; + if (ch == EOF) + break; + if (ch != '/') { + /* * Descend into this node, setting the value type as needed... */ + parent = node; + if (cb && parent) + type = (*cb)(parent); + else + type = MXML_TEXT; + } else if (sax_cb) { + (*sax_cb)(node, MXML_SAX_ELEMENT_CLOSE, + sax_data); + if (!mxmlRelease(node) && first == node) + first = NULL; + } + } + bufptr = buffer; + } else if (ch == '&') { + /* * Add character entity to current buffer... */ + ch = mxml_get_entity(parent, p, &encoding, getc_cb); + if (ch == EOF) + goto error; + if (mxml_add_char(ch, &bufptr, &buffer, &bufsize)) + goto error; + } else if (type == MXML_OPAQUE || type == MXML_CUSTOM || + !mxml_isspace(ch)) { + /* * Add character to current buffer... */ + if (mxml_add_char(ch, &bufptr, &buffer, &bufsize)) + goto error; + } + } + /* * Free the string buffer - we don't need it anymore... */ + free(buffer); + /* * Find the top element and return it... */ + if (parent) { + node = parent; + while (parent != top && parent->parent) + parent = parent->parent; + if (node != parent) { + mxml_error("Missing close tag under parent <%s>!", + node->value.element.name, + node->parent ? + node->parent->value.element.name : + "(null)"); + mxmlDelete(first); + return NULL; + } + } + if (parent) + return parent; + else + return first; + /* * Common error return... */ + +error: + mxmlDelete(first); + free(buffer); + return NULL; +} + +/* + * 'mxml_parse_element()' - Parse an element for any attributes... + */ + +static int /* O - Terminating character */ +mxml_parse_element(mxml_node_t *node, /* I - Element node */ + void *p, /* I - Data to read from */ + int *encoding, /* IO - Encoding */ + _mxml_getc_cb_t getc_cb) +{ /* I - Data callback */ + int ch, /* Current character in file */ + quote; /* Quoting character */ + char *name, /* Attribute name */ + *value, /* Attribute value */ + *ptr; /* Pointer into name/value */ + int namesize, /* Size of name string */ + valsize; /* Size of value string */ + + /* Initialize the name and value buffers... */ + name = malloc(64); + if (name == NULL) { + mxml_error("Unable to allocate memory for name!"); + return EOF; + } + + namesize = 64; + value = malloc(64); + if (value == NULL) { + free(name); + mxml_error("Unable to allocate memory for value!"); + return EOF; + } + valsize = 64; + /* * Loop until we hit a >, /, ?, or EOF... */ + + while ((ch = (*getc_cb)(p, encoding)) != EOF) { + /* * Skip leading whitespace... */ + if (mxml_isspace(ch)) + continue; + /* * Stop at /, ?, or >... */ + if (ch == '/' || ch == '?') { + /* * Grab the > character and print an error if it isn't there... */ + quote = (*getc_cb)(p, encoding); + if (quote != '>') { + mxml_error( + "Expected '>' after '%c' for element %s, but got '%c'!", + ch, node->value.element.name, quote); + goto error; + } + break; + } else if (ch == '<') { + mxml_error("Bare < in element %s!", + node->value.element.name); + goto error; + } else if (ch == '>') + break; + /* * Read the attribute name... */ + name[0] = ch; + ptr = name + 1; + if (ch == '\"' || ch == '\'') { + /* * Name is in quotes, so get a quoted string... */ + quote = ch; + while ((ch = (*getc_cb)(p, encoding)) != EOF) { + if (ch == '&') { + ch = mxml_get_entity(node, p, encoding, + getc_cb); + if (ch == EOF) + goto error; + } + if (mxml_add_char(ch, &ptr, &name, &namesize)) + goto error; + if (ch == quote) + break; + } + } else { + /* * Grab an normal, non-quoted name... */ + while ((ch = (*getc_cb)(p, encoding)) != EOF) + if (mxml_isspace(ch) || ch == '=' || + ch == '/' || ch == '>' || ch == '?') + break; + else { + if (ch == '&') { + ch = mxml_get_entity(node, p, + encoding, + getc_cb); + if (ch == EOF) + goto error; + } + if (mxml_add_char(ch, &ptr, &name, + &namesize)) + goto error; + } + } + *ptr = '\0'; + if (mxmlElementGetAttr(node, name)) + goto error; + while (ch != EOF && mxml_isspace(ch)) + ch = (*getc_cb)(p, encoding); + if (ch == '=') { + /* * Read the attribute value... */ + do { + ch = (*getc_cb)(p, encoding); + } while (ch != EOF && mxml_isspace(ch)); + + if (ch == EOF) { + mxml_error( + "Missing value for attribute '%s' in element %s!", + name, node->value.element.name); + goto error; + } + if (ch == '\'' || ch == '\"') { + /* * Read quoted value... */ + quote = ch; + ptr = value; + while ((ch = (*getc_cb)(p, encoding)) != EOF) + if (ch == quote) + break; + else { + if (ch == '&') { + ch = mxml_get_entity( + node, p, + encoding, + getc_cb); + if (ch == EOF) + goto error; + } + if (mxml_add_char(ch, &ptr, + &value, + &valsize)) + goto error; + } + *ptr = '\0'; + } else { + /* * Read unquoted value... */ + value[0] = ch; + ptr = value + 1; + while ((ch = (*getc_cb)(p, encoding)) != EOF) + if (mxml_isspace(ch) || ch == '=' || + ch == '/' || ch == '>') + break; + else { + if (ch == '&') { + ch = mxml_get_entity( + node, p, + encoding, + getc_cb); + if (ch == EOF) + goto error; + } + if (mxml_add_char(ch, &ptr, + &value, + &valsize)) + goto error; + } + *ptr = '\0'; + } + /* * Set the attribute with the given string value... */ + mxmlElementSetAttr(node, name, value); + } else { + mxml_error( + "Missing value for attribute '%s' in element %s!", + name, node->value.element.name); + goto error; + } + + /* * Check the end character... */ + if (ch == '/' || ch == '?') { + /* * Grab the > character and print an error if it isn't there... */ + quote = (*getc_cb)(p, encoding); + if (quote != '>') { + mxml_error( + "Expected '>' after '%c' for element %s, but got '%c'!", + ch, node->value.element.name, quote); + ch = EOF; + } + break; + } else if (ch == '>') + break; + } + /* * Free the name and value buffers and return... */ + free(name); + free(value); + return ch; + /* * Common error return point... */ +error: + free(name); + free(value); + return EOF; +} + +/* + * 'mxml_string_getc()' - Get a character from a string. + */ + +static int /* O - Character or EOF */ +mxml_string_getc(void *p, /* I - Pointer to file */ + int *encoding) +{ /* IO - Encoding */ + int ch; /* Character */ + const char **s; /* Pointer to string pointer */ + + s = (const char **)p; + ch = (*s)[0] & 255; + if (ch != 0 || *encoding == ENCODE_UTF16LE) { + /* * Got character; convert UTF-8 to integer and return... */ + + (*s)++; + switch (*encoding) { + case ENCODE_UTF8: + if (!(ch & 0x80)) { + if (mxml_bad_char(ch)) { + mxml_error( + "Bad control character 0x%02x not allowed by XML standard!", + ch); + return EOF; + } + return ch; + } else if (ch == 0xfe) { + /* * UTF-16 big-endian BOM? */ + if (((*s)[0] & 255) != 0xff) + return EOF; + *encoding = ENCODE_UTF16BE; + (*s)++; + return mxml_string_getc(p, encoding); + } else if (ch == 0xff) { + /* * UTF-16 little-endian BOM? */ + if (((*s)[0] & 255) != 0xfe) + return EOF; + *encoding = ENCODE_UTF16LE; + (*s)++; + return mxml_string_getc(p, encoding); + } else if ((ch & 0xe0) == 0xc0) { + if (((*s)[0] & 0xc0) != 0x80) + return EOF; + ch = ((ch & 0x1f) << 6) | ((*s)[0] & 0x3f); + (*s)++; + if (ch < 0x80) { + mxml_error( + "Invalid UTF-8 sequence for character 0x%04x!", + ch); + return EOF; + } + return ch; + } else if ((ch & 0xf0) == 0xe0) { + if (((*s)[0] & 0xc0) != 0x80 || + ((*s)[1] & 0xc0) != 0x80) + return EOF; + ch = ((((ch & 0x0f) << 6) | ((*s)[0] & 0x3f)) + << 6) | + ((*s)[1] & 0x3f); + (*s) += 2; + if (ch < 0x800) { + mxml_error( + "Invalid UTF-8 sequence for character 0x%04x!", + ch); + return EOF; + } + if (ch == 0xfeff) + return mxml_string_getc(p, encoding); + return ch; + } else if ((ch & 0xf8) == 0xf0) { + if (((*s)[0] & 0xc0) != 0x80 || + ((*s)[1] & 0xc0) != 0x80 || + ((*s)[2] & 0xc0) != 0x80) + return EOF; + ch = ((((((ch & 0x07) << 6) | ((*s)[0] & 0x3f)) + << 6) | + ((*s)[1] & 0x3f)) + << 6) | + ((*s)[2] & 0x3f); + (*s) += 3; + if (ch < 0x10000) { + mxml_error( + "Invalid UTF-8 sequence for character 0x%04x!", + ch); + return EOF; + } + return ch; + } else + return EOF; + + case ENCODE_UTF16BE: + ch = (ch << 8) | ((*s)[0] & 255); + (*s)++; + if (mxml_bad_char(ch)) { + mxml_error( + "Bad control character 0x%02x not allowed by XML standard!", + ch); + return EOF; + } else if (ch >= 0xd800 && ch <= 0xdbff) { + int lch; /* Lower word */ + if (!(*s)[0]) + return EOF; + lch = (((*s)[0] & 255) << 8) | ((*s)[1] & 255); + (*s) += 2; + if (lch < 0xdc00 || lch >= 0xdfff) + return EOF; + ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + + 0x10000; + } + return ch; + + case ENCODE_UTF16LE: + ch = ch | (((*s)[0] & 255) << 8); + if (!ch) { + (*s)--; + return EOF; + } + (*s)++; + if (mxml_bad_char(ch)) { + mxml_error( + "Bad control character 0x%02x not allowed by XML standard!", + ch); + return EOF; + } else if (ch >= 0xd800 && ch <= 0xdbff) { + int lch; /* Lower word */ + if (!(*s)[1]) + return EOF; + lch = (((*s)[1] & 255) << 8) | ((*s)[0] & 255); + (*s) += 2; + if (lch < 0xdc00 || lch >= 0xdfff) + return EOF; + ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + + 0x10000; + } + return ch; + } + } + return EOF; +} + +/* + * 'mxml_string_putc()' - Write a character to a string. + */ + +static int /* O - 0 on success, -1 on failure */ +mxml_string_putc(int ch, /* I - Character to write */ + void *p) +{ /* I - Pointer to string pointers */ + char **pp; /* Pointer to string pointers */ + pp = (char **)p; + if (pp[0] < pp[1]) + pp[0][0] = ch; + pp[0]++; + return 0; +} + +/* + * 'mxml_write_name()' - Write a name string. + */ + +static int /* O - 0 on success, -1 on failure */ +mxml_write_name(const char *s, /* I - Name to write */ + void *p, /* I - Write pointer */ + int (*putc_cb)(int, void *)) +/* I - Write callback */ +{ + char quote; /* Quote character */ + const char *name; /* Entity name */ + + if (*s == '\"' || *s == '\'') { + if ((*putc_cb)(*s, p) < 0) + return (-1); + quote = *s++; + while (*s && *s != quote) { + name = mxmlEntityGetName(*s); + if (name != NULL) { + if ((*putc_cb)('&', p) < 0) + return (-1); + while (*name) { + if ((*putc_cb)(*name, p) < 0) + return (-1); + name++; + } + if ((*putc_cb)(';', p) < 0) + return (-1); + } else if ((*putc_cb)(*s, p) < 0) + return (-1); + s++; + } + if ((*putc_cb)(quote, p) < 0) + return (-1); + } else { + while (*s) { + if ((*putc_cb)(*s, p) < 0) + return (-1); + s++; + } + } + return 0; +} + +/* + * 'mxml_write_node()' - Save an XML node to a file. + */ + +static int /* O - Column or -1 on error */ +mxml_write_node(mxml_node_t *node, /* I - Node to write */ + void *p, /* I - File to write to */ + mxml_save_cb_t cb, /* I - Whitespace callback */ + int col, /* I - Current column */ + _mxml_putc_cb_t putc_cb, /* I - Output callback */ + _mxml_global_t *global) +{ /* I - Global data */ + mxml_node_t *curr, /* Current node */ + *next; /* Next node */ + int i, /* Looping var */ + width; /* Width of attr + value */ + mxml_attr_t *attr; /* Current attribute */ + char s[255]; /* Temporary string */ + + /* * Loop through this node and all of its children... */ + for (curr = node; curr; curr = next) { + switch (curr->type) { + case MXML_ELEMENT: + col = mxml_write_ws(curr, p, cb, MXML_WS_BEFORE_OPEN, + col, putc_cb); + if ((*putc_cb)('<', p) < 0) + return (-1); + if (curr->value.element.name[0] == '?' || + !strncmp(curr->value.element.name, "!--", 3)) { + /* + * Comments and processing instructions do not use character + * entities. + */ + const char *ptr; /* Pointer into name */ + for (ptr = curr->value.element.name; *ptr; + ptr++) + if ((*putc_cb)(*ptr, p) < 0) + return (-1); + } else if (!strncmp(curr->value.element.name, + "![CDATA[", 8)) { + /* + * CDATA elements do not use character entities, but also need the + * "]]" terminator added at the end. + */ + const char *ptr; /* Pointer into name */ + for (ptr = curr->value.element.name; *ptr; + ptr++) + if ((*putc_cb)(*ptr, p) < 0) + return (-1); + if ((*putc_cb)(']', p) < 0) + return (-1); + if ((*putc_cb)(']', p) < 0) + return (-1); + } else if (mxml_write_name(curr->value.element.name, p, + putc_cb) < 0) + return (-1); + col += strlen(curr->value.element.name) + 1; + for (i = curr->value.element.num_attrs, + attr = curr->value.element.attrs; + i > 0; i--, attr++) { + width = (int)strlen(attr->name); + if (attr->value) + width += strlen(attr->value) + 3; + { + if ((*putc_cb)(' ', p) < 0) + return (-1); + col++; + } + if (mxml_write_name(attr->name, p, putc_cb) < 0) + return (-1); + if (attr->value) { + if ((*putc_cb)('=', p) < 0) + return (-1); + if ((*putc_cb)('\"', p) < 0) + return (-1); + if (mxml_write_string(attr->value, p, + putc_cb) < 0) + return (-1); + if ((*putc_cb)('\"', p) < 0) + return (-1); + } + col += width; + } + if (curr->child) { + if ((*putc_cb)('>', p) < 0) + return (-1); + else + col++; + col = mxml_write_ws(curr, p, cb, + MXML_WS_AFTER_OPEN, col, + putc_cb); + } else if (curr->value.element.name[0] == '!' || + curr->value.element.name[0] == '?') { + if ((*putc_cb)('>', p) < 0) + return (-1); + else + col++; + col = mxml_write_ws(curr, p, cb, + MXML_WS_AFTER_OPEN, col, + putc_cb); + } else { + if ((*putc_cb)(' ', p) < 0) + return (-1); + if ((*putc_cb)('/', p) < 0) + return (-1); + if ((*putc_cb)('>', p) < 0) + return (-1); + col += 3; + col = mxml_write_ws(curr, p, cb, + MXML_WS_AFTER_OPEN, col, + putc_cb); + } + break; + case MXML_INTEGER: + if (curr->prev) { + if (global->wrap > 0 && col > global->wrap) { + if ((*putc_cb)('\n', p) < 0) + return (-1); + col = 0; + } else if ((*putc_cb)(' ', p) < 0) + return (-1); + else + col++; + } + snprintf(s, sizeof(s), "%d", curr->value.integer); + if (mxml_write_string(s, p, putc_cb) < 0) + return (-1); + col += strlen(s); + break; + case MXML_OPAQUE: + if (mxml_write_string(curr->value.opaque, p, putc_cb) < + 0) + return (-1); + col += strlen(curr->value.opaque); + break; + + case MXML_REAL: + if (curr->prev) { + if (global->wrap > 0 && col > global->wrap) { + if ((*putc_cb)('\n', p) < 0) + return (-1); + col = 0; + } else if ((*putc_cb)(' ', p) < 0) + return (-1); + else + col++; + } + /*sprintf(s, "%f", curr->value.real);*/ + if (mxml_write_string(s, p, putc_cb) < 0) + return (-1); + + col += strlen(s); + break; + + case MXML_TEXT: + if (curr->value.text.whitespace && col > 0) { + if (global->wrap > 0 && col > global->wrap) { + if ((*putc_cb)('\n', p) < 0) + return (-1); + + col = 0; + } else if ((*putc_cb)(' ', p) < 0) + return (-1); + else + col++; + } + + if (mxml_write_string(curr->value.text.string, p, + putc_cb) < 0) + return (-1); + + col += strlen(curr->value.text.string); + break; + + case MXML_CUSTOM: + if (global->custom_save_cb) { + char *data; /* Custom data string */ + const char *newline; /* Last newline in string */ + data = (*global->custom_save_cb)(curr); + if (data == NULL) + return (-1); + if (mxml_write_string(data, p, putc_cb) < 0) + return (-1); + newline = strrchr(data, '\n'); + if (newline == NULL) + col += strlen(data); + else + col = (int)strlen(newline); + + free(data); + break; + } + + default: /* Should never happen */ + return (-1); + } + + next = curr->child; + if (next == NULL) { + while ((next = curr->next) == NULL) { + if (curr == node) + break; + + curr = curr->parent; + if (curr->value.element.name[0] != '!' && + curr->value.element.name[0] != '?') { + col = mxml_write_ws( + curr, p, cb, + MXML_WS_BEFORE_CLOSE, col, + putc_cb); + if ((*putc_cb)('<', p) < 0) + return (-1); + if ((*putc_cb)('/', p) < 0) + return (-1); + if (mxml_write_string( + curr->value.element.name, p, + putc_cb) < 0) + return (-1); + if ((*putc_cb)('>', p) < 0) + return (-1); + col += strlen(curr->value.element.name) + + 3; + col = mxml_write_ws(curr, p, cb, + MXML_WS_AFTER_CLOSE, + col, putc_cb); + } + } + } + } + return col; +} + +/* + * 'mxml_write_string()' - Write a string, escaping & and < as needed. + */ + +static int /* O - 0 on success, -1 on failure */ +mxml_write_string(const char *s, /* I - String to write */ + void *p, /* I - Write pointer */ + _mxml_putc_cb_t putc_cb) +{ /* I - Write callback */ + const char *name; /* Entity name, if any */ + + while (*s) { + name = mxmlEntityGetName(*s); + if (name != NULL) { + if ((*putc_cb)('&', p) < 0) + return (-1); + while (*name) { + if ((*putc_cb)(*name, p) < 0) + return (-1); + name++; + } + if ((*putc_cb)(';', p) < 0) + return (-1); + } else if ((*putc_cb)(*s, p) < 0) + return (-1); + s++; + } + return 0; +} + +/* + * 'mxml_write_ws()' - Do whitespace callback... + */ + +static int /* O - New column */ +mxml_write_ws(mxml_node_t *node, /* I - Current node */ + void *p, /* I - Write pointer */ + mxml_save_cb_t cb, /* I - Callback function */ + int ws, /* I - Where value */ + int col, /* I - Current column */ + _mxml_putc_cb_t putc_cb) +{ /* I - Write callback */ + const char *s; /* Whitespace string */ + s = (*cb)(node, ws); + if (cb && s != NULL) { + while (*s) { + if ((*putc_cb)(*s, p) < 0) + return (-1); + else if (*s == '\n') + col = 0; + else if (*s == '\t') { + col += MXML_TAB; + col = col - (col % MXML_TAB); + } else + col++; + s++; + } + } + return col; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-get.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-get.c new file mode 100644 index 000000000000..4e9c97f116f1 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-get.c @@ -0,0 +1,287 @@ +/* + * Node get functions for Mini-XML, a small XML file parsing library. + * + * Copyright 2014-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" +#include "mxml.h" + +/* + * 'mxmlGetCDATA()' - Get the value for a CDATA node. + * + * @code NULL@ is returned if the node is not a CDATA element. + * + * @since Mini-XML 2.7@ + */ + +const char * /* O - CDATA value or @code NULL@ */ +mxmlGetCDATA(mxml_node_t *node) +{ /* I - Node to get */ + + if (!node || node->type != MXML_ELEMENT || + strncmp(node->value.element.name, "![CDATA[", 8)) + return NULL; + /* Return the text following the CDATA declaration... */ + return (node->value.element.name + 8); +} + +/* + * 'mxmlGetCustom()' - Get the value for a custom node. + * + * @code NULL@ is returned if the node (or its first child) is not a custom + * value node. + * + * @since Mini-XML 2.7@ + */ + +const void * /* O - Custom value or @code NULL@ */ +mxmlGetCustom(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return NULL; + + /* * Return the integer value... */ + + if (node->type == MXML_CUSTOM) + return node->value.custom.data; + else if (node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_CUSTOM) + return node->child->value.custom.data; + else + return NULL; +} + +/* + * 'mxmlGetElement()' - Get the name for an element node. + * + * @code NULL@ is returned if the node is not an element node. + * + * @since Mini-XML 2.7@ + */ + +const char * /* O - Element name or @code NULL@ */ +mxmlGetElement(mxml_node_t *node) +{ /* I - Node to get */ + if (!node || node->type != MXML_ELEMENT) + return NULL; + /* * Return the element name... */ + return node->value.element.name; +} + +/* + * 'mxmlGetFirstChild()' - Get the first child of an element node. + * + * @code NULL@ is returned if the node is not an element node or if the node + * has no children. + * + * @since Mini-XML 2.7@ + */ + +mxml_node_t * /* O - First child or @code NULL@ */ +mxmlGetFirstChild(mxml_node_t *node) +{ /* I - Node to get */ + if (!node || node->type != MXML_ELEMENT) + return NULL; + /* * Return the first child node... */ + return node->child; +} + +/* + * 'mxmlGetInteger()' - Get the integer value from the specified node or its + * first child. + * + * 0 is returned if the node (or its first child) is not an integer value node. + * + * @since Mini-XML 2.7@ + */ + +int /* O - Integer value or 0 */ mxmlGetInteger(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return 0; + + /* * Return the integer value... */ + + if (node->type == MXML_INTEGER) + return node->value.integer; + else if (node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_INTEGER) + return node->child->value.integer; + else + return 0; +} + +/* + * 'mxmlGetLastChild()' - Get the last child of an element node. + * + * @code NULL@ is returned if the node is not an element node or if the node + * has no children. + * + * @since Mini-XML 2.7@ + */ + +mxml_node_t * /* O - Last child or @code NULL@ */ +mxmlGetLastChild(mxml_node_t *node) +{ /* I - Node to get */ + if (!node || node->type != MXML_ELEMENT) + return NULL; + /* * Return the node type... */ + return node->last_child; +} + +/* + * 'mxmlGetNextSibling()' - Get the next node for the current parent. + * + * @code NULL@ is returned if this is the last child for the current parent. + * + * @since Mini-XML 2.7@ + */ + +mxml_node_t *mxmlGetNextSibling(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return NULL; + /* * Return the node type... */ + return node->next; +} + +/* + * 'mxmlGetOpaque()' - Get an opaque string value for a node or its first child. + * + * @code NULL@ is returned if the node (or its first child) is not an opaque + * value node. + * + * @since Mini-XML 2.7@ + */ + +const char * /* O - Opaque string or @code NULL@ */ +mxmlGetOpaque(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return NULL; + /* * Return the integer value... */ + if (node->type == MXML_OPAQUE) + return node->value.opaque; + else if (node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_OPAQUE) + return node->child->value.opaque; + else + return NULL; +} + +/* + * 'mxmlGetParent()' - Get the parent node. + * + * @code NULL@ is returned for a root node. + * + * @since Mini-XML 2.7@ + */ + +mxml_node_t * /* O - Parent node or @code NULL@ */ +mxmlGetParent(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return NULL; + /* * Return the node type... */ + return node->parent; +} + +/* + * 'mxmlGetPrevSibling()' - Get the previous node for the current parent. + * + * @code NULL@ is returned if this is the first child for the current parent. + * + * @since Mini-XML 2.7@ + */ + +mxml_node_t * /* O - Previous node or @code NULL@ */ +mxmlGetPrevSibling(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return NULL; + /* * Return the node type... */ + return node->prev; +} + +/* + * 'mxmlGetText()' - Get the text value for a node or its first child. + * + * @code NULL@ is returned if the node (or its first child) is not a text node. + * The "whitespace" argument can be @code NULL@. + * + * @since Mini-XML 2.7@ + */ + +const char * /* O - Text string or @code NULL@ */ +mxmlGetText(mxml_node_t *node, /* I - Node to get */ + int *whitespace) +{ /* O - 1 if string is preceded by whitespace, 0 otherwise */ + if (!node) { + if (whitespace) + *whitespace = 0; + return NULL; + } + if (node->type == MXML_TEXT) { + if (whitespace) + *whitespace = node->value.text.whitespace; + + return node->value.text.string; + } else if (node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_TEXT) { + if (whitespace) + *whitespace = node->child->value.text.whitespace; + return node->child->value.text.string; + } else { + if (whitespace) + *whitespace = 0; + return NULL; + } +} + +/* + * 'mxmlGetType()' - Get the node type. + * + * @code MXML_IGNORE@ is returned if "node" is @code NULL@. + * + * @since Mini-XML 2.7@ + */ + +mxml_type_t /* O - Type of node */ +mxmlGetType(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return MXML_IGNORE; + /* * Return the node type... */ + return node->type; +} + +/* + * 'mxmlGetUserData()' - Get the user data pointer for a node. + * + * @since Mini-XML 2.7@ + */ + +void * /* O - User data pointer */ +mxmlGetUserData(mxml_node_t *node) +{ /* I - Node to get */ + if (!node) + return NULL; + /* + * Return the user data pointer... + */ + return node->user_data; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-index.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-index.c new file mode 100644 index 000000000000..b55ab95c4a83 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-index.c @@ -0,0 +1,358 @@ +/* + * Index support code for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" +#include "mxml.h" + +/* + * Sort functions... + */ + +static int index_compare(mxml_index_t *ind, mxml_node_t *first, + mxml_node_t *second); +static int index_find(mxml_index_t *ind, const char *element, const char *value, + mxml_node_t *node); +static void index_sort(mxml_index_t *ind, int left, int right); + +/* + * 'mxmlIndexDelete()' - Delete an index. + */ + +void mxmlIndexDelete(mxml_index_t *ind) +{ /* I - Index to delete */ + if (!ind) + return; + if (ind->attr) + free(ind->attr); + if (ind->alloc_nodes) + free(ind->nodes); + free(ind); +} + +/* + * 'mxmlIndexEnum()' - Return the next node in the index. + * + * You should call @link mxmlIndexReset@ prior to using this function to get + * the first node in the index. Nodes are returned in the sorted order of the + * index. + */ + +mxml_node_t * /* O - Next node or @code NULL@ if there is none */ +mxmlIndexEnum(mxml_index_t *ind) +{ /* I - Index to enumerate */ + if (!ind) + return NULL; + if (ind->cur_node < ind->num_nodes) + return ind->nodes[ind->cur_node++]; + else + return NULL; +} + +/* + * 'mxmlIndexFind()' - Find the next matching node. + * + * You should call @link mxmlIndexReset@ prior to using this function for + * the first time with a particular set of "element" and "value" + * strings. Passing @code NULL@ for both "element" and "value" is equivalent + * to calling @link mxmlIndexEnum@. + */ + +mxml_node_t * /* O - Node or @code NULL@ if none found */ +mxmlIndexFind(mxml_index_t *ind, /* I - Index to search */ + const char *element, /* I - Element name to find, if any */ + const char *value) +{ /* I - Attribute value, if any */ + int diff, /* Difference between names */ + curr, /* Current entity in search */ + first, /* First entity in search */ + last; /* Last entity in search */ + + if (!ind || (!ind->attr && value)) { + return NULL; + } + + /* + * If both element and value are NULL, just enumerate the nodes in the + * index... + */ + + if (!element && !value) + return mxmlIndexEnum(ind); + + /* * If there are no nodes in the index, return NULL... */ + + if (!ind->num_nodes) { + return NULL; + } + + /* * If cur_node == 0, then find the first matching node... */ + if (ind->cur_node == 0) { + /* * Find the first node using a modified binary search algorithm... */ + first = 0; + last = ind->num_nodes - 1; + while ((last - first) > 1) { + curr = (first + last) / 2; + diff = index_find(ind, element, value, + ind->nodes[curr]); + if (diff == 0) { + /* * Found a match, move back to find the first... */ + while (curr > 0 && + !index_find(ind, element, value, + ind->nodes[curr - 1])) + curr--; + /* * Return the first match and save the index to the next... */ + ind->cur_node = curr + 1; + return ind->nodes[curr]; + } else if (diff < 0) + last = curr; + else + first = curr; + } + /* * If we get this far, then we found exactly 0 or 1 matches... */ + for (curr = first; curr <= last; curr++) + if (!index_find(ind, element, value, + ind->nodes[curr])) { + /* * Found exactly one (or possibly two) match... */ + ind->cur_node = curr + 1; + return ind->nodes[curr]; + } + ind->cur_node = ind->num_nodes; + return NULL; + } else if (ind->cur_node < ind->num_nodes && + !index_find(ind, element, value, + ind->nodes[ind->cur_node])) { + /* * Return the next matching node... */ + return ind->nodes[ind->cur_node++]; + } + /* * If we get this far, then we have no matches... */ + ind->cur_node = ind->num_nodes; + return NULL; +} + +/* + * 'mxmlIndexGetCount()' - Get the number of nodes in an index. + * + * @since Mini-XML 2.7@ + */ + +int /* I - Number of nodes in index */ mxmlIndexGetCount(mxml_index_t *ind) +{ /* I - Index of nodes */ + if (!ind) + return 0; + /* + * Return the number of nodes in the index... + */ + return ind->num_nodes; +} + +/* + * 'mxmlIndexNew()' - Create a new index. + * + * The index will contain all nodes that contain the named element and/or + * attribute. If both "element" and "attr" are @code NULL@, then the index will + * contain a sorted list of the elements in the node tree. Nodes are + * sorted by element name and optionally by attribute value if the "attr" + * argument is not NULL. + */ + +mxml_index_t * /* O - New index */ +mxmlIndexNew( + mxml_node_t *node, /* I - XML node tree */ + const char *element, /* I - Element to index or @code NULL@ for all */ + const char *attr) +{ /* I - Attribute to index or @code NULL@ for none */ + mxml_index_t *ind; /* New index */ + mxml_node_t *curr, /* Current node in index */ + **temp; /* Temporary node pointer array */ + + if (!node) + return NULL; + + ind = calloc(1, sizeof(mxml_index_t)); + if (ind == NULL) { + mxml_error("Unable to allocate %d bytes for index - %s", + sizeof(mxml_index_t), NULL); + return NULL; + } + + if (attr) + ind->attr = strdup(attr); + + if (!element && !attr) + curr = node; + else + curr = mxmlFindElement(node, node, element, attr, NULL, + MXML_DESCEND); + + while (curr) { + if (ind->num_nodes >= ind->alloc_nodes) { + if (!ind->alloc_nodes) + temp = malloc(64 * sizeof(mxml_node_t *)); + else + temp = realloc(ind->nodes, + (ind->alloc_nodes + 64) * + sizeof(mxml_node_t *)); + if (!temp) { + /* * Unable to allocate memory for the index, so abort... */ + mxml_error( + "Unable to allocate %d bytes for index: %s", + (ind->alloc_nodes + 64) * + sizeof(mxml_node_t *), + NULL); + mxmlIndexDelete(ind); + return NULL; + } + ind->nodes = temp; + ind->alloc_nodes += 64; + } + ind->nodes[ind->num_nodes++] = curr; + curr = mxmlFindElement(curr, node, element, attr, NULL, + MXML_DESCEND); + } + + /* + * Sort nodes based upon the search criteria... + */ + + if (ind->num_nodes > 1) + index_sort(ind, 0, ind->num_nodes - 1); + return ind; +} + +/* + * 'mxmlIndexReset()' - Reset the enumeration/find pointer in the index and + * return the first node in the index. + * + * This function should be called prior to using @link mxmlIndexEnum@ or + * @link mxmlIndexFind@ for the first time. + */ + +mxml_node_t * /* O - First node or @code NULL@ if there is none */ +mxmlIndexReset(mxml_index_t *ind) +{ /* I - Index to reset */ + if (!ind) + return NULL; + + /* * Set the index to the first element... */ + ind->cur_node = 0; + if (ind->num_nodes) + return ind->nodes[0]; + else + return NULL; +} + +/* + * 'index_compare()' - Compare two nodes. + */ + +static int /* O - Result of comparison */ +index_compare(mxml_index_t *ind, /* I - Index */ + mxml_node_t *first, /* I - First node */ + mxml_node_t *second) +{ /* I - Second node */ + int diff; /* Difference */ + diff = strcmp(first->value.element.name, second->value.element.name); + if (diff != 0) + return diff; + if (ind->attr) { + diff = strcmp(mxmlElementGetAttr(first, ind->attr), + mxmlElementGetAttr(second, ind->attr)); + if (diff != 0) + return diff; + } + return 0; +} + +/* + * 'index_find()' - Compare a node with index values. + */ + +static int /* O - Result of comparison */ +index_find(mxml_index_t *ind, /* I - Index */ + const char *element, /* I - Element name or @code NULL@ */ + const char *value, /* I - Attribute value or @code NULL@ */ + mxml_node_t *node) +{ /* I - Node */ + int diff; /* Difference */ + if (element) { + diff = strcmp(element, node->value.element.name); + if (diff != 0) + return diff; + } + if (value) { + diff = strcmp(value, mxmlElementGetAttr(node, ind->attr)); + if (diff != 0) + return diff; + } + return 0; +} + +/* + * 'index_sort()' - Sort the nodes in the index... + * + * This function implements the classic quicksort algorithm... + */ + +static void index_sort(mxml_index_t *ind, /* I - Index to sort */ + int left, /* I - Left node in partition */ + int right) +{ /* I - Right node in partition */ + mxml_node_t *pivot, /* Pivot node */ + *temp; /* Swap node */ + int templ, /* Temporary left node */ + tempr; /* Temporary right node */ + + /* * Loop until we have sorted all the way to the right... */ + + do { + /* * Sort the pivot in the curr partition... */ + pivot = ind->nodes[left]; + for (templ = left, tempr = right; templ < tempr;) { + /* * Move left while left node <= pivot node... */ + while ((templ < right) && + index_compare(ind, ind->nodes[templ], pivot) <= + 0) + templ++; + /* * Move right while right node > pivot node... */ + while ((tempr > left) && + index_compare(ind, ind->nodes[tempr], pivot) > 0) + tempr--; + /* * Swap nodes if needed... */ + if (templ < tempr) { + temp = ind->nodes[templ]; + ind->nodes[templ] = ind->nodes[tempr]; + ind->nodes[tempr] = temp; + } + } + + /* + * When we get here, the right (tempr) node is the new position for the + * pivot node... + */ + + if (index_compare(ind, pivot, ind->nodes[tempr]) > 0) { + ind->nodes[left] = ind->nodes[tempr]; + ind->nodes[tempr] = pivot; + } + + /* * Recursively sort the left partition as needed... */ + if (left < (tempr - 1)) + index_sort(ind, left, tempr - 1); + } while (right > (left = tempr + 1)); +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-node.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-node.c new file mode 100644 index 000000000000..c8a3fcbd67db --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-node.c @@ -0,0 +1,551 @@ +/* + * Node support code for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" +#include "mxml.h" + +/* + * Local functions... + */ + +static void mxml_free(mxml_node_t *node); +static mxml_node_t *mxml_new(mxml_node_t *parent, mxml_type_t type); + +/* + * 'mxmlAdd()' - Add a node to a tree. + * + * Adds the specified node to the parent. If the child argument is not + * @code NULL@, puts the new node before or after the specified child depending + * on the value of the where argument. If the child argument is @code NULL@, + * puts the new node at the beginning of the child list (@code MXML_ADD_BEFORE@) + * or at the end of the child list (@code MXML_ADD_AFTER@). The constant + * @code MXML_ADD_TO_PARENT@ can be used to specify a @code NULL@ child pointer. + */ + +void mxmlAdd( + mxml_node_t *parent, /* I - Parent node */ + int where, /* I - Where to add, @code MXML_ADD_BEFORE@ or @code MXML_ADD_AFTER@ */ + mxml_node_t * + child, /* I - Child node for where or @code MXML_ADD_TO_PARENT@ */ + mxml_node_t *node) +{ /* I - Node to add */ + + /* Range check input... */ + + if (!parent || !node) + return; + + /* Remove the node from any existing parent... */ + if (node->parent) + mxmlRemove(node); + + /* Reset pointers... */ + + node->parent = parent; + switch (where) { + case MXML_ADD_BEFORE: + if (!child || child == parent->child || + child->parent != parent) { + /* Insert as first node under parent... */ + node->next = parent->child; + if (parent->child) + parent->child->prev = node; + else + parent->last_child = node; + parent->child = node; + } else { + /* Insert node before this child... */ + node->next = child; + node->prev = child->prev; + if (child->prev) + child->prev->next = node; + else + parent->child = node; + child->prev = node; + } + break; + + case MXML_ADD_AFTER: + if (!child || child == parent->last_child || + child->parent != parent) { + /* Insert as last node under parent... */ + node->parent = parent; + node->prev = parent->last_child; + if (parent->last_child) + parent->last_child->next = node; + else + parent->child = node; + parent->last_child = node; + } else { + /* Insert node after this child... */ + node->prev = child; + node->next = child->next; + if (child->next) + child->next->prev = node; + else + parent->last_child = node; + child->next = node; + } + break; + } +} + +/* + * 'mxmlDelete()' - Delete a node and all of its children. + * + * If the specified node has a parent, this function first removes the + * node from its parent using the @link mxmlRemove@ function. + */ + +void mxmlDelete(mxml_node_t *node) +{ /* I - Node to delete */ + mxml_node_t *curr, /* Current node */ + *next; /* Next node */ + + /* Range check input... */ + + if (!node) + return; + /* Remove the node from its parent, if any... */ + mxmlRemove(node); + /* Delete children... */ + for (curr = node->child; curr; curr = next) { + /* Get the next node... */ + next = curr->child; + if (next != NULL) { + /* Free parent nodes after child nodes have been freed... */ + curr->child = NULL; + continue; + } + next = curr->next; + if (next == NULL) { + /* Next node is the parent, which we'll free as needed... */ + next = curr->parent; + if (next == node) + next = NULL; + } + /* Free child... */ + mxml_free(curr); + } + /* Then free the memory used by the parent node... */ + mxml_free(node); +} + +/* + * 'mxmlGetRefCount()' - Get the current reference (use) count for a node. + * + * The initial reference count of new nodes is 1. Use the @link mxmlRetain@ + * and @link mxmlRelease@ functions to increment and decrement a node's + * reference count. + * + * @since Mini-XML 2.7@. + */ + +int /* O - Reference count */ mxmlGetRefCount(mxml_node_t *node) +{ /* I - Node */ + /* Range check input... */ + + if (!node) + return 0; + /* Return the reference count... */ + return node->ref_count; +} + +/* + * 'mxmlNewCDATA()' - Create a new CDATA node. + * + * The new CDATA node is added to the end of the specified parent's child + * list. The constant @code MXML_NO_PARENT@ can be used to specify that the new + * CDATA node has no parent. The data string must be nul-terminated and + * is copied into the new node. CDATA nodes currently use the + * @code MXML_ELEMENT@ type. + * + * @since Mini-XML 2.3@ + */ + +mxml_node_t * /* O - New node */ +mxmlNewCDATA(mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + const char *data) +{ /* I - Data string */ + mxml_node_t *node; /* New node */ + + /* Range check input... */ + + if (!data) + return NULL; + + /* Create the node and set the name value... */ + node = mxml_new(parent, MXML_ELEMENT); + if (node != NULL) + node->value.element.name = _mxml_strdupf("![CDATA[%s]]", data); + return node; +} + +/* + * 'mxmlNewCustom()' - Create a new custom data node. + * + * The new custom node is added to the end of the specified parent's child + * list. The constant @code MXML_NO_PARENT@ can be used to specify that the new + * element node has no parent. @code NULL@ can be passed when the data in the + * node is not dynamically allocated or is separately managed. + * + * @since Mini-XML 2.1@ + */ + +mxml_node_t * /* O - New node */ +mxmlNewCustom(mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + void *data, /* I - Pointer to data */ + mxml_custom_destroy_cb_t destroy) +{ /* I - Function to destroy data */ + mxml_node_t *node; /* New node */ + + /* Create the node and set the value... */ + node = mxml_new(parent, MXML_CUSTOM); + if (node != NULL) { + node->value.custom.data = data; + node->value.custom.destroy = destroy; + } + return node; +} + +/* + * 'mxmlNewElement()' - Create a new element node. + * + * The new element node is added to the end of the specified parent's child + * list. The constant @code MXML_NO_PARENT@ can be used to specify that the new + * element node has no parent. + */ + +mxml_node_t * /* O - New node */ +mxmlNewElement( + mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + const char *name) +{ /* I - Name of element */ + mxml_node_t *node; /* New node */ + + /* Range check input... */ + + if (!name) + return NULL; + + /* Create the node and set the element name... */ + node = mxml_new(parent, MXML_ELEMENT); + if (node != NULL) + node->value.element.name = strdup(name); + return node; +} + +/* + * 'mxmlNewInteger()' - Create a new integer node. + * + * The new integer node is added to the end of the specified parent's child + * list. The constant @code MXML_NO_PARENT@ can be used to specify that the new + * integer node has no parent. + */ + +mxml_node_t * /* O - New node */ +mxmlNewInteger( + mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + int integer) +{ /* I - Integer value */ + mxml_node_t *node; /* New node */ + + /* Create the node and set the element name... */ + node = mxml_new(parent, MXML_INTEGER); + if (node != NULL) + node->value.integer = integer; + return node; +} + +/* + * 'mxmlNewOpaque()' - Create a new opaque string. + * + * The new opaque string node is added to the end of the specified parent's + * child list. The constant @code MXML_NO_PARENT@ can be used to specify that + * the new opaque string node has no parent. The opaque string must be nul- + * terminated and is copied into the new node. + */ + +mxml_node_t * /* O - New node */ +mxmlNewOpaque(mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + const char *opaque) +{ /* I - Opaque string */ + mxml_node_t *node; /* New node */ + + /* * Range check input... */ + if (!opaque) + return NULL; + /* Create the node and set the element name... */ + node = mxml_new(parent, MXML_OPAQUE); + if (node != NULL) + node->value.opaque = strdup(opaque); + return node; +} + +/* + * 'mxmlNewOpaquef()' - Create a new formatted opaque string node. + * + * The new opaque string node is added to the end of the specified parent's + * child list. The constant @code MXML_NO_PARENT@ can be used to specify that + * the new opaque string node has no parent. The format string must be + * nul-terminated and is formatted into the new node. + */ + +mxml_node_t * /* O - New node */ +mxmlNewOpaquef( + mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + const char *format, /* I - Printf-style format string */ + ...) +{ /* I - Additional args as needed */ + mxml_node_t *node; /* New node */ + va_list ap; /* Pointer to arguments */ + + /* Range check input... */ + if (!format) + return NULL; + /* Create the node and set the text value... */ + node = mxml_new(parent, MXML_OPAQUE); + if (node != NULL) { + va_start(ap, format); + node->value.opaque = _mxml_vstrdupf(format, ap); + va_end(ap); + } + return node; +} + +/* + * 'mxmlNewText()' - Create a new text fragment node. + * + * The new text node is added to the end of the specified parent's child + * list. The constant @code MXML_NO_PARENT@ can be used to specify that the new + * text node has no parent. The whitespace parameter is used to specify + * whether leading whitespace is present before the node. The text + * string must be nul-terminated and is copied into the new node. + */ + +mxml_node_t * /* O - New node */ +mxmlNewText(mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */ + const char *string) +{ /* I - String */ + mxml_node_t *node; /* New node */ + + /* Range check input... */ + + if (!string) + return NULL; + /* Create the node and set the text value... */ + node = mxml_new(parent, MXML_TEXT); + if (node != NULL) { + node->value.text.whitespace = whitespace; + node->value.text.string = strdup(string); + } + return node; +} + +/* + * 'mxmlNewTextf()' - Create a new formatted text fragment node. + * + * The new text node is added to the end of the specified parent's child + * list. The constant @code MXML_NO_PARENT@ can be used to specify that the new + * text node has no parent. The whitespace parameter is used to specify + * whether leading whitespace is present before the node. The format + * string must be nul-terminated and is formatted into the new node. + */ + +mxml_node_t * /* O - New node */ +mxmlNewTextf(mxml_node_t *parent, /* I - Parent node or @code MXML_NO_PARENT@ */ + int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */ + const char *format, /* I - Printf-style format string */ + ...) +{ /* I - Additional args as needed */ + mxml_node_t *node; /* New node */ + va_list ap; /* Pointer to arguments */ + + /* Range check input... */ + if (!format) + return NULL; + + /* Create the node and set the text value... */ + node = mxml_new(parent, MXML_TEXT); + if (node != NULL) { + va_start(ap, format); + node->value.text.whitespace = whitespace; + node->value.text.string = _mxml_vstrdupf(format, ap); + va_end(ap); + } + return node; +} + +/* + * 'mxmlRemove()' - Remove a node from its parent. + * + * This function does not free memory used by the node - use @link mxmlDelete@ + * for that. This function does nothing if the node has no parent. + */ + +void mxmlRemove(mxml_node_t *node) +{ /* I - Node to remove */ + + /* Range check input... */ + if (!node || !node->parent) + return; + + /* Remove from parent... */ + if (node->prev) + node->prev->next = node->next; + else + node->parent->child = node->next; + if (node->next) + node->next->prev = node->prev; + else + node->parent->last_child = node->prev; + node->parent = NULL; + node->prev = NULL; + node->next = NULL; +} + +/* + * 'mxmlNewXML()' - Create a new XML document tree. + * + * The "version" argument specifies the version number to put in the + * ?xml element node. If @code NULL@, version "1.0" is assumed. + * + * @since Mini-XML 2.3@ + */ + +mxml_node_t * /* O - New ?xml node */ +mxmlNewXML(const char *version) +{ /* I - Version number to use */ + char element[1024]; /* Element text */ + snprintf(element, sizeof(element), + "?xml version=\"%s\" encoding=\"utf-8\"?", + version ? version : "1.0"); + return mxmlNewElement(NULL, element); +} + +/* + * 'mxmlRelease()' - Release a node. + * + * When the reference count reaches zero, the node (and any children) + * is deleted via @link mxmlDelete@. + * + * @since Mini-XML 2.3@ + */ + +int /* O - New reference count */ mxmlRelease(mxml_node_t *node) +{ /* I - Node */ + if (node) { + if ((--node->ref_count) <= 0) { + mxmlDelete(node); + return 0; + } else + return node->ref_count; + } else + return (-1); +} + +/* + * 'mxmlRetain()' - Retain a node. + * + * @since Mini-XML 2.3@ + */ + +int /* O - New reference count */ mxmlRetain(mxml_node_t *node) +{ /* I - Node */ + if (node) + return (++node->ref_count); + else + return (-1); +} + +/* + * 'mxml_free()' - Free the memory used by a node. + * + * Note: Does not free child nodes, does not remove from parent. + */ + +static void mxml_free(mxml_node_t *node) +{ /* I - Node */ + int i; /* Looping var */ + + switch (node->type) { + case MXML_ELEMENT: + if (node->value.element.name) + free(node->value.element.name); + + if (node->value.element.num_attrs) { + for (i = 0; i < node->value.element.num_attrs; i++) { + if (node->value.element.attrs[i].name) + free(node->value.element.attrs[i].name); + if (node->value.element.attrs[i].value) + free(node->value.element.attrs[i].value); + } + free(node->value.element.attrs); + } + break; + case MXML_INTEGER: + /* Nothing to do */ + break; + case MXML_OPAQUE: + if (node->value.opaque) + free(node->value.opaque); + break; + case MXML_REAL: + /* Nothing to do */ + break; + case MXML_TEXT: + if (node->value.text.string) + free(node->value.text.string); + break; + case MXML_CUSTOM: + if (node->value.custom.data && node->value.custom.destroy) + (*(node->value.custom.destroy))( + node->value.custom.data); + break; + default: + break; + } + free(node); +} + +/* + * 'mxml_new()' - Create a new node. + */ + +static mxml_node_t * /* O - New node */ +mxml_new(mxml_node_t *parent, /* I - Parent node */ + mxml_type_t type) +{ /* I - Node type */ + mxml_node_t *node; /* New node */ + + /* Allocate memory for the node... */ + node = calloc(1, sizeof(mxml_node_t)); + if (node == NULL) { + return NULL; + } + /* Set the node type... */ + node->type = type; + node->ref_count = 1; + /* Add to the parent if present... */ + if (parent) + mxmlAdd(parent, MXML_ADD_AFTER, MXML_ADD_TO_PARENT, node); + /* Return the new node... */ + return node; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.c new file mode 100644 index 000000000000..b8553299b956 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.c @@ -0,0 +1,267 @@ +/* + * Private functions for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "mxml-private.h" + +/* + * Some crazy people think that unloading a shared object is a good or safe + * thing to do. Unfortunately, most objects are simply *not* safe to unload + * and bad things *will* happen. + * + * The following mess of conditional code allows us to provide a destructor + * function in Mini-XML for our thread-global storage so that it can possibly + * be unloaded safely, although since there is no standard way to do so I + * can't even provide any guarantees that you can do it safely on all platforms. + * + * This code currently supports AIX, HP-UX, Linux, Mac OS X, Solaris, and + * Windows. It might work on the BSDs and IRIX, but I haven't tested that. + */ + +#if defined(__sun) || defined(_AIX) +#pragma fini(_mxml_fini) +#define _MXML_FINI _mxml_fini +#elif defined(__hpux) +#pragma FINI _mxml_fini +#define _MXML_FINI _mxml_fini +#elif defined(__GNUC__) /* Linux and Mac OS X */ +#define _MXML_FINI (__attribute((destructor)) _mxml_fini) +#else +#define _MXML_FINI _fini +#endif /* __sun */ + +/* + * 'mxml_error()' - Display an error message. + */ + +void mxml_error(const char *format, /* I - Printf-style format string */ + ...) +{ /* I - Additional arguments as needed */ + va_list ap; /* Pointer to arguments */ + char s[1024]; /* Message string */ + _mxml_global_t *global = _mxml_global(); + /* Global data */ + + /* Range check input... */ + + if (!format) + return; + + /* Format the error message string... */ + + va_start(ap, format); + vsnprintf(s, sizeof(s), format, ap); + va_end(ap); + /* * And then display the error message... */ + if (global->error_cb) + (*global->error_cb)(s); +} + +/* + * 'mxml_ignore_cb()' - Default callback for ignored values. + */ + +mxml_type_t /* O - Node type */ +mxml_ignore_cb(mxml_node_t *node) +{ /* I - Current node */ + (void)node; + return MXML_IGNORE; +} + +/* + * 'mxml_integer_cb()' - Default callback for integer values. + */ + +mxml_type_t /* O - Node type */ +mxml_integer_cb(mxml_node_t *node) +{ /* I - Current node */ + (void)node; + return MXML_INTEGER; +} + +/* + * 'mxml_opaque_cb()' - Default callback for opaque values. + */ + +mxml_type_t /* O - Node type */ +mxml_opaque_cb(mxml_node_t *node) +{ /* I - Current node */ + (void)node; + return MXML_OPAQUE; +} + +/* + * 'mxml_real_cb()' - Default callback for real number values. + */ + +mxml_type_t /* O - Node type */ +mxml_real_cb(mxml_node_t *node) +{ /* I - Current node */ + (void)node; + return MXML_REAL; +} + +#ifdef HAVE_PTHREAD_H /**** POSIX threading ****/ +#include + +static pthread_key_t _mxml_key = -1; /* Thread local storage key */ +static pthread_once_t _mxml_key_once = PTHREAD_ONCE_INIT; +/* One-time initialization object */ +static void _mxml_init(void); +static void _mxml_destructor(void *g); + +/* + * '_mxml_destructor()' - Free memory used for globals... + */ + +static void _mxml_destructor(void *g) +{ /* I - Global data */ + free(g); +} + +/* + * '_mxml_fini()' - Clean up when unloaded. + */ + +static void _MXML_FINI(void) +{ + _mxml_global_t *global; /* Global data */ + if (_mxml_key != -1) { + global = (_mxml_global_t *)pthread_getspecific(_mxml_key); + if (global != NULL) + _mxml_destructor(global); + pthread_key_delete(_mxml_key); + _mxml_key = -1; + } +} + +/* + * '_mxml_global()' - Get global data. + */ + +_mxml_global_t * /* O - Global data */ +_mxml_global(void) +{ + _mxml_global_t *global; /* Global data */ + pthread_once(&_mxml_key_once, _mxml_init); + global = (_mxml_global_t *)pthread_getspecific(_mxml_key); + if (global == NULL) { + global = (_mxml_global_t *)calloc(1, sizeof(_mxml_global_t)); + pthread_setspecific(_mxml_key, global); + global->num_entity_cbs = 1; + global->entity_cbs[0] = _mxml_entity_cb; + global->wrap = 72; + } + return global; +} + +/* + * '_mxml_init()' - Initialize global data... + */ + +static void _mxml_init(void) +{ + pthread_key_create(&_mxml_key, _mxml_destructor); +} + +#elif defined(WIN32) && defined(MXML1_EXPORTS) /**** WIN32 threading ****/ +#include + +static DWORD _mxml_tls_index; /* Index for global storage */ + +/* + * 'DllMain()' - Main entry for library. + */ + +BOOL WINAPI /* O - Success/failure */ +DllMain(HINSTANCE hinst, /* I - DLL module handle */ + DWORD reason, /* I - Reason */ + LPVOID reserved) +{ /* I - Unused */ + _mxml_global_t *global; /* Global data */ + (void)hinst; + (void)reserved; + + switch (reason) { + case DLL_PROCESS_ATTACH: /* Called on library initialization */ + _mxml_tls_index = TlsAlloc(); + if (_mxml_tls_index == TLS_OUT_OF_INDEXES) + return FALSE; + break; + + case DLL_THREAD_DETACH: /* Called when a thread terminates */ + global = (_mxml_global_t *)TlsGetValue(_mxml_tls_index); + if (global != NULL) + free(global); + break; + + case DLL_PROCESS_DETACH: /* Called when library is unloaded */ + global = (_mxml_global_t *)TlsGetValue(_mxml_tls_index); + if (global != NULL) + free(global); + + TlsFree(_mxml_tls_index); + break; + + default: + break; + } + + return TRUE; +} + +/* + * '_mxml_global()' - Get global data. + */ + +_mxml_global_t * /* O - Global data */ +_mxml_global(void) +{ + _mxml_global_t *global; /* Global data */ + global = (_mxml_global_t *)TlsGetValue(_mxml_tls_index); + if (global == NULL) { + global = (_mxml_global_t *)calloc(1, sizeof(_mxml_global_t)); + global->num_entity_cbs = 1; + global->entity_cbs[0] = _mxml_entity_cb; + global->wrap = 72; + TlsSetValue(_mxml_tls_index, (LPVOID)global); + } + return global; +} + +#else /**** No threading ****/ +/* + * '_mxml_global()' - Get global data. + */ + +_mxml_global_t * /* O - Global data */ +_mxml_global(void) +{ + static _mxml_global_t global = /* Global data */ + { + NULL, /* error_cb */ + 1, /* num_entity_cbs */ + { _mxml_entity_cb }, /* entity_cbs */ + 72, /* wrap */ + NULL, /* custom_load_cb */ + NULL /* custom_save_cb */ + }; + + return &global; +} +#endif /* HAVE_PTHREAD_H */ diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.h new file mode 100644 index 000000000000..51b1c41a8848 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-private.h @@ -0,0 +1,41 @@ +/* + * Private definitions for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" +#include "mxml.h" + +/* + * Global, per-thread data... + */ + +typedef struct _mxml_global_s { + void (*error_cb)(const char *); + int num_entity_cbs; + int (*entity_cbs[100])(const char *name); + int wrap; + mxml_custom_load_cb_t custom_load_cb; + mxml_custom_save_cb_t custom_save_cb; +} _mxml_global_t; + +/* + * Functions... + */ + +extern _mxml_global_t *_mxml_global(void); +extern int _mxml_entity_cb(const char *name); diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-search.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-search.c new file mode 100644 index 000000000000..0291641c180d --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-search.c @@ -0,0 +1,196 @@ +/* + * Search/navigation functions for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" +#include "mxml.h" + +/* + * 'mxmlFindElement()' - Find the named element. + * + * The search is constrained by the name, attribute name, and value; any + * @code NULL@ names or values are treated as wildcards, so different kinds of + * searches can be implemented by looking for all elements of a given name + * or all elements with a specific attribute. The descend argument determines + * whether the search descends into child nodes; normally you will use + * @code MXML_DESCEND_FIRST@ for the initial search and @code MXML_NO_DESCEND@ + * to find additional direct descendents of the node. The top node argument + * constrains the search to a particular node's children. + */ + +mxml_node_t * /* O - Element node or @code NULL@ */ +mxmlFindElement( + mxml_node_t *node, /* I - Current node */ + mxml_node_t *top, /* I - Top node */ + const char *element, /* I - Element name or @code NULL@ for any */ + const char *attr, /* I - Attribute name, or @code NULL@ for none */ + const char *value, /* I - Attribute value, or @code NULL@ for any */ + int descend) +{ /* I - Descend into tree - @code MXML_DESCEND@, @code MXML_NO_DESCEND@, or @code MXML_DESCEND_FIRST@ */ + const char *temp; /* Current attribute value */ + if (!node || !top || (!attr && value)) + return NULL; + /* * Start with the next node... */ + node = mxmlWalkNext(node, top, descend); + /* * Loop until we find a matching element... */ + while (node != NULL) { + /* * See if this node matches... */ + if (node->type == MXML_ELEMENT && node->value.element.name && + (!element || !strcmp(node->value.element.name, element))) { + /* * See if we need to check for an attribute... */ + if (!attr) + return node; + /* * Check for the attribute... */ + temp = mxmlElementGetAttr(node, attr); + if (temp != NULL) { + /* * OK, we have the attribute, does it match? */ + if (!value || !strcmp(value, temp)) + return node; /* Yes, return it... */ + } + } + /* * No match, move on to the next node... */ + if (descend == MXML_DESCEND) + node = mxmlWalkNext(node, top, MXML_DESCEND); + else + node = node->next; + } + return NULL; +} + +/* + * 'mxmlFindPath()' - Find a node with the given path. + * + * The "path" is a slash-separated list of element names. The name "*" is + * considered a wildcard for one or more levels of elements. For example, + * "foo/one/two", "bar/two/one", "*\/one", and so forth. + * + * The first child node of the found node is returned if the given node has + * children and the first child is a value node. + * + * @since Mini-XML 2.7@ + */ + +mxml_node_t * /* O - Found node or @code NULL@ */ +mxmlFindPath(mxml_node_t *top, /* I - Top node */ + const char *path) +{ /* I - Path to element */ + mxml_node_t *node; /* Current node */ + char element[256]; /* Current element name */ + const char *pathsep; /* Separator in path */ + int descend; /* mxmlFindElement option */ + + if (!top || !path || !*path) + return NULL; + /* * Search each element in the path... */ + + node = top; + while (*path) { + /* * Handle wildcards... */ + if (!strncmp(path, "*/", 2)) { + path += 2; + descend = MXML_DESCEND; + } else + descend = MXML_DESCEND_FIRST; + /* * Get the next element in the path... */ + pathsep = strnchr(path, '/', strlen(path)); + if (pathsep == NULL) + pathsep = path + strlen(path); + if (pathsep == path || (pathsep - path) >= sizeof(element)) + return NULL; + memcpy(element, path, pathsep - path); + element[pathsep - path] = '\0'; + if (*pathsep) + path = pathsep + 1; + else + path = pathsep; + /* * Search for the element... */ + node = mxmlFindElement(node, node, element, NULL, NULL, + descend); + if (node == NULL) + return NULL; + } + + /* * If we get this far, return the node or its first child... */ + if (node->child && node->child->type != MXML_ELEMENT) + return node->child; + else + return node; +} + +/* + * 'mxmlWalkNext()' - Walk to the next logical node in the tree. + * + * The descend argument controls whether the first child is considered + * to be the next node. The top node argument constrains the walk to + * the node's children. + */ + +mxml_node_t * /* O - Next node or @code NULL@ */ +mxmlWalkNext(mxml_node_t *node, /* I - Current node */ + mxml_node_t *top, /* I - Top node */ + int descend) +{ /* I - Descend into tree - @code MXML_DESCEND@, @code MXML_NO_DESCEND@, or @code MXML_DESCEND_FIRST@ */ + if (!node) + return NULL; + else if (node->child && descend) + return node->child; + else if (node == top) + return NULL; + else if (node->next) + return node->next; + else if (node->parent && node->parent != top) { + node = node->parent; + while (!node->next) + if (node->parent == top || !node->parent) + return NULL; + else + node = node->parent; + return node->next; + } else + return NULL; +} + +/* + * 'mxmlWalkPrev()' - Walk to the previous logical node in the tree. + * + * The descend argument controls whether the previous node's last child + * is considered to be the previous node. The top node argument constrains + * the walk to the node's children. + */ + +mxml_node_t * /* O - Previous node or @code NULL@ */ +mxmlWalkPrev(mxml_node_t *node, /* I - Current node */ + mxml_node_t *top, /* I - Top node */ + int descend) +{ /* I - Descend into tree - @code MXML_DESCEND@, @code MXML_NO_DESCEND@, or @code MXML_DESCEND_FIRST@ */ + if (!node || node == top) + return NULL; + else if (node->prev) { + if (node->prev->last_child && descend) { + /* * Find the last child under the previous node... */ + node = node->prev->last_child; + while (node->last_child) + node = node->last_child; + return node; + } else + return node->prev; + } else if (node->parent != top) + return node->parent; + else + return NULL; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-set.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-set.c new file mode 100644 index 000000000000..2206ecbaa2fe --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-set.c @@ -0,0 +1,238 @@ +/* + * Node set functions for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" +#include "mxml.h" + +/* + * 'mxmlSetCDATA()' - Set the element name of a CDATA node. + * + * The node is not changed if it (or its first child) is not a CDATA element node. + * + * @since Mini-XML 2.3@ + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetCDATA(mxml_node_t *node, /* I - Node to set */ + const char *data) +{ /* I - New data string */ + if (node && node->type == MXML_ELEMENT && + strncmp(node->value.element.name, "![CDATA[", 8) && node->child && + node->child->type == MXML_ELEMENT && + !strncmp(node->child->value.element.name, "![CDATA[", 8)) + node = node->child; + + if (!node || node->type != MXML_ELEMENT || !data || + strncmp(node->value.element.name, "![CDATA[", 8)) + return (-1); + /* * Free any old element value and set the new value... */ + if (node->value.element.name) + free(node->value.element.name); + node->value.element.name = _mxml_strdupf("![CDATA[%s]]", data); + return 0; +} + +/* + * 'mxmlSetCustom()' - Set the data and destructor of a custom data node. + * + * The node is not changed if it (or its first child) is not a custom node. + * + * @since Mini-XML 2.1@ + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetCustom(mxml_node_t *node, /* I - Node to set */ + void *data, /* I - New data pointer */ + mxml_custom_destroy_cb_t destroy) +{ /* I - New destructor function */ + if (node && node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_CUSTOM) + node = node->child; + + if (!node || node->type != MXML_CUSTOM) + return (-1); + /* * Free any old element value and set the new value... */ + + if (node->value.custom.data && node->value.custom.destroy) + (*(node->value.custom.destroy))(node->value.custom.data); + node->value.custom.data = data; + node->value.custom.destroy = destroy; + return 0; +} + +/* + * 'mxmlSetElement()' - Set the name of an element node. + * + * The node is not changed if it is not an element node. + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetElement(mxml_node_t *node, /* I - Node to set */ + const char *name) +{ /* I - New name string */ + if (!node || node->type != MXML_ELEMENT || !name) + return (-1); + + /* * Free any old element value and set the new value... */ + + if (node->value.element.name) + free(node->value.element.name); + node->value.element.name = strdup(name); + return 0; +} + +/* + * 'mxmlSetInteger()' - Set the value of an integer node. + * + * The node is not changed if it (or its first child) is not an integer node. + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetInteger(mxml_node_t *node, /* I - Node to set */ + int integer) +{ /* I - Integer value */ + if (node && node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_INTEGER) + node = node->child; + + if (!node || node->type != MXML_INTEGER) + return (-1); + node->value.integer = integer; + return 0; +} + +/* + * 'mxmlSetOpaque()' - Set the value of an opaque node. + * + * The node is not changed if it (or its first child) is not an opaque node. + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetOpaque(mxml_node_t *node, /* I - Node to set */ + const char *opaque) +{ /* I - Opaque string */ + if (node && node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_OPAQUE) + node = node->child; + if (!node || node->type != MXML_OPAQUE || !opaque) + return (-1); + /* * Free any old opaque value and set the new value... */ + if (node->value.opaque) + free(node->value.opaque); + node->value.opaque = strdup(opaque); + return 0; +} + +/* + * 'mxmlSetOpaquef()' - Set the value of an opaque string node to a formatted string. + * + * The node is not changed if it (or its first child) is not an opaque node. + * + * @since Mini-XML 2.11@ + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetOpaquef(mxml_node_t *node, /* I - Node to set */ + const char *format, /* I - Printf-style format string */ + ...) +{ /* I - Additional arguments as needed */ + va_list ap; /* Pointer to arguments */ + if (node && node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_OPAQUE) + node = node->child; + if (!node || node->type != MXML_OPAQUE || !format) + return (int)(-1); + /* * Free any old string value and set the new value... */ + if (node->value.opaque) + free(node->value.opaque); + va_start(ap, format); + node->value.opaque = _mxml_strdupf(format, ap); + va_end(ap); + return 0; +} + +/* + * 'mxmlSetText()' - Set the value of a text node. + * + * The node is not changed if it (or its first child) is not a text node. + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetText(mxml_node_t *node, /* I - Node to set */ + int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */ + const char *string) +{ /* I - String */ + if (node && node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_TEXT) + node = node->child; + + if (!node || node->type != MXML_TEXT || !string) + return (int)(-1); + /* * Free any old string value and set the new value... */ + if (node->value.text.string) + free(node->value.text.string); + node->value.text.whitespace = whitespace; + node->value.text.string = strdup(string); + return 0; +} + +/* + * 'mxmlSetTextf()' - Set the value of a text node to a formatted string. + * + * The node is not changed if it (or its first child) is not a text node. + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetTextf(mxml_node_t *node, /* I - Node to set */ + int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */ + const char *format, /* I - Printf-style format string */ + ...) +{ /* I - Additional arguments as needed */ + va_list ap; /* Pointer to arguments */ + if (node && node->type == MXML_ELEMENT && node->child && + node->child->type == MXML_TEXT) + node = node->child; + if (!node || node->type != MXML_TEXT || !format) + return (-1); + /* * Free any old string value and set the new value... */ + if (node->value.text.string) + free(node->value.text.string); + va_start(ap, format); + node->value.text.whitespace = whitespace; + node->value.text.string = _mxml_strdupf(format, ap); + va_end(ap); + return 0; +} + +/* + * 'mxmlSetUserData()' - Set the user data pointer for a node. + * + * @since Mini-XML 2.7@ + */ + +int /* O - 0 on success, -1 on failure */ +mxmlSetUserData(mxml_node_t *node, /* I - Node to set */ + void *data) +{ /* I - User data pointer */ + if (!node) + return (int)(-1); + /* * Set the user data pointer and return... */ + node->user_data = data; + return 0; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-string.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-string.c new file mode 100644 index 000000000000..96aa5fcb6510 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml-string.c @@ -0,0 +1,393 @@ +/* + * String functions for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Include necessary headers... + */ + +#include "config.h" + +/* + * The va_copy macro is part of C99, but many compilers don't implement it. + * Provide a "direct assignment" implmentation when va_copy isn't defined... + */ + +#ifndef va_copy +#ifdef __va_copy +#define va_copy(dst, src) __va_copy(dst, src) +#else +#define va_copy(dst, src) memcpy(&dst, src, sizeof(va_list)) +#endif /* __va_copy */ +#endif /* va_copy */ + +#ifndef HAVE_SNPRINTF +/* + * '_mxml_snprintf()' - Format a string. + */ + +int /* O - Number of bytes formatted */ +_mxml_snprintf(char *buffer, /* I - Output buffer */ + size_t bufsize, /* I - Size of output buffer */ + const char *format, /* I - Printf-style format string */ + ...) +{ /* I - Additional arguments as needed */ + va_list ap; /* Argument list */ + int bytes; /* Number of bytes formatted */ + va_start(ap, format); + bytes = vsnprintf(buffer, bufsize, format, ap); + va_end(ap); + return bytes; +} +#endif /* !HAVE_SNPRINTF */ + +/* + * '_mxml_strdup()' - Duplicate a string. + */ + +#ifndef HAVE_STRDUP +char * /* O - New string pointer */ +_mxml_strdup(const char *s) +{ /* I - String to duplicate */ + char *t; /* New string pointer */ + if (s == NULL) + return NULL; + t = malloc(strlen(s) + 1); + if (r == NULL) + return NULL; + return strlcpy(t, s, strlen(s) + 1); +} +#endif /* !HAVE_STRDUP */ + +/* + * '_mxml_strdupf()' - Format and duplicate a string. + */ + +char * /* O - New string pointer */ +_mxml_strdupf(const char *format, /* I - Printf-style format string */ + ...) +{ /* I - Additional arguments as needed */ + va_list ap; /* Pointer to additional arguments */ + char *s; /* Pointer to formatted string */ + + /* + * Get a pointer to the additional arguments, format the string, + * and return it... + */ + + va_start(ap, format); +#ifdef HAVE_VASPRINTF + if (vasprintf(&s, format, ap) < 0) + s = NULL; +#else + s = _mxml_vstrdupf(format, ap); +#endif /* HAVE_VASPRINTF */ + va_end(ap); + return s; +} + +#ifndef HAVE_STRLCAT +size_t /* O - Number of bytes copied */ +_mxml_strlcat(char *dst, /* I - Destination buffer */ + const char *src, /* I - Source string */ + size_t dstsize) +{ /* I - Size of destinatipon buffer */ + size_t srclen; /* Length of source string */ + size_t dstlen; /* Length of destination string */ + dstlen = strlen(dst); + if (dstsize <= (dstlen + 1)) + return dstlen; /* No room, return immediately... */ + dstsize -= dstlen + 1; + srclen = strlen(src); + if (srclen > dstsize) + srclen = dstsize; + memmove(dst + dstlen, src, srclen); + dst[dstlen + srclen] = '\0'; + return (dstlen + srclen); +} +#endif /* !HAVE_STRLCAT */ + +#ifndef HAVE_STRLCPY +size_t /* O - Number of bytes copied */ +_mxml_strlcpy(char *dst, /* I - Destination buffer */ + const char *src, /* I - Source string */ + size_t dstsize) +{ /* I - Size of destinatipon buffer */ + size_t srclen; /* Length of source string */ + dstsize--; + srclen = strlen(src); + if (srclen > dstsize) + srclen = dstsize; + memmove(dst, src, srclen); + dst[srclen] = '\0'; + return srclen; +} +#endif /* !HAVE_STRLCPY */ + +#ifndef HAVE_VSNPRINTF +int /* O - Number of bytes formatted */ +_mxml_vsnprintf(char *buffer, /* O - Output buffer */ + size_t bufsize, /* O - Size of output buffer */ + const char *format, /* I - Printf-style format string */ + va_list ap) +{ /* I - Pointer to additional arguments */ + char *bufptr, /* Pointer to position in buffer */ + *bufend, /* Pointer to end of buffer */ + sign, /* Sign of format width */ + size, /* Size character (h, l, L) */ + type; /* Format type character */ + int width, /* Width of field */ + prec; /* Number of characters of precision */ + char tformat[100], /* Temporary format string for sprintf() */ + *tptr, /* Pointer into temporary format */ + temp[1024]; /* Buffer for formatted numbers */ + char *s; /* Pointer to string */ + int slen; /* Length of string */ + int bytes; /* Total number of bytes needed */ + + bufptr = buffer; + bufend = buffer + bufsize - 1; + bytes = 0; + + while (*format) { + if (*format == '%') { + tptr = tformat; + *tptr++ = *format++; + if (*format == '%') { + if (bufptr && bufptr < bufend) + *bufptr++ = *format; + bytes++; + format++; + continue; + } else if (strnchr(" -+#\'", *format, + strlen(" -+#\'"))) { + *tptr++ = *format; + sign = *format++; + } else + sign = 0; + if (*format == '*') { + format++; + width = va_arg(ap, int); + snprintf(tptr, + sizeof(tformat) - (tptr - tformat), + "%d", width); + tptr += strlen(tptr); + } else { + width = 0; + while (isdigit(*format & 255)) { + if (tptr < + (tformat + sizeof(tformat) - 1)) + *tptr++ = *format; + width = width * 10 + *format++ - '0'; + } + } + if (*format == '.') { + if (tptr < (tformat + sizeof(tformat) - 1)) + *tptr++ = *format; + format++; + if (*format == '*') { + format++; + prec = va_arg(ap, int); + snprintf(tptr, + sizeof(tformat) - + (tptr - tformat), + "%d", prec); + tptr += strlen(tptr); + } else { + prec = 0; + while (isdigit(*format & 255)) { + if (tptr < + (tformat + sizeof(tformat) - + 1)) + *tptr++ = *format; + prec = prec * 10 + *format++ - + '0'; + } + } + } else + prec = -1; + if (*format == 'l' && format[1] == 'l') { + size = 'L'; + if (tptr < (tformat + sizeof(tformat) - 2)) { + *tptr++ = 'l'; + *tptr++ = 'l'; + } + format += 2; + } else if (*format == 'h' || *format == 'l' || + *format == 'L') { + if (tptr < (tformat + sizeof(tformat) - 1)) + *tptr++ = *format; + size = *format++; + } + if (!*format) + break; + if (tptr < (tformat + sizeof(tformat) - 1)) + *tptr++ = *format; + type = *format++; + *tptr = '\0'; + switch (type) { + case 'E': /* Floating point formats */ + case 'G': + case 'e': + case 'f': + case 'g': + break; + case 'B': /* Integer formats */ + case 'X': + case 'b': + case 'd': + case 'i': + case 'o': + case 'u': + case 'x': + if ((width + 2) > sizeof(temp)) + break; +#ifdef HAVE_LONG_LONG + if (size == 'L') + snprintf(temp, sizeof(temp), tformat, + va_arg(ap, long long)); + else +#endif /* HAVE_LONG_LONG */ + snprintf(temp, sizeof(temp), tformat, + va_arg(ap, int)); + bytes += strlen(temp); + if (bufptr) { + if ((bufptr + strlen(temp)) > bufend) { + strlcpy(bufptr, temp, + (size_t)(bufend - + bufptr + 1)); + bufptr = bufend; + } else { + strlcpy(bufptr, temp, + bytes + 1); + bufptr += strlen(temp); + } + } + break; + + case 'p': /* Pointer value */ + if ((width + 2) > sizeof(temp)) + break; + snprintf(temp, sizeof(temp), tformat, + va_arg(ap, void *)); + bytes += strlen(temp); + if (bufptr) { + if ((bufptr + strlen(temp)) > bufend) { + strlcpy(bufptr, temp, + (size_t)(bufend - + bufptr + 1)); + bufptr = bufend; + } else { + strlcpy(bufptr, temp, + bytes + 1); + bufptr += strlen(temp); + } + } + break; + + case 'c': /* Character or character array */ + bytes += width; + + if (bufptr) { + if (width <= 1) + *bufptr++ = va_arg(ap, int); + else { + if ((bufptr + width) > bufend) + width = bufend - bufptr; + + memcpy(bufptr, + va_arg(ap, char *), + (size_t)width); + bufptr += width; + } + } + break; + + case 's': /* String */ + s = va_arg(ap, char *); + if (s == NULL) + s = "(null)"; + slen = strlen(s); + if (slen > width && prec != width) + width = slen; + bytes += width; + if (bufptr) { + if ((bufptr + width) > bufend) + width = bufend - bufptr; + if (slen > width) + slen = width; + if (sign == '-') { + strlcpy(bufptr, s, + (size_t)(slen + 1)); + memset(bufptr + slen, ' ', + (size_t)(width - slen)); + } else { + memset(bufptr, ' ', + (size_t)(width - slen)); + strlcpy(bufptr + width - slen, + s, (size_t)(slen + 1)); + } + bufptr += width; + } + break; + + case 'n': /* Output number of chars so far */ + *(va_arg(ap, int *)) = bytes; + break; + } + } else { + bytes++; + if (bufptr && bufptr < bufend) + *bufptr++ = *format; + format++; + } + } + *bufptr = '\0'; + return bytes; +} +#endif /* !HAVE_VSNPRINTF */ + +char * /* O - New string pointer */ +_mxml_vstrdupf(const char *format, /* I - Printf-style format string */ + va_list ap) +{ /* I - Pointer to additional arguments */ +#ifdef HAVE_VASPRINTF + char *s; /* String */ + if (vasprintf(&s, format, ap) < 0) + s = NULL; + return s; + +#else + int bytes; /* Number of bytes required */ + char *buffer, /* String buffer */ + temp[256]; /* Small buffer for first vsnprintf */ + +#ifdef WIN32 + bytes = _vscprintf(format, ap); +#else + va_list apcopy; /* Copy of argument list */ + va_copy(apcopy, ap); + bytes = vsnprintf(temp, sizeof(temp), format, apcopy); +#endif /* WIN32 */ + + if (bytes < sizeof(temp)) { + return strdup(temp); + } + + buffer = calloc(1, bytes + 1); + if (buffer != NULL) + vsnprintf(buffer, bytes + 1, format, ap); + return buffer; +#endif /* HAVE_VASPRINTF */ +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml.h new file mode 100644 index 000000000000..657e0587b496 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/mxml.h @@ -0,0 +1,317 @@ +/* + * Header file for Mini-XML, a small XML file parsing library. + * + * Copyright 2003-2017 by Michael R Sweet. + * Copyright (C) 2019 XiaoMi, Inc. + * + * These coded instructions, statements, and computer programs are the + * property of Michael R Sweet and are protected by Federal copyright + * law. Distribution and use rights are outlined in the file "COPYING" + * which should have been included with this file. If this file is + * missing or damaged, see the license at: + * + * https://michaelrsweet.github.io/mxml + */ + +/* + * Prevent multiple inclusion... + */ + +#ifndef _mxml_h_ +#define _mxml_h_ + +/* + * Include necessary headers... + */ + +#include +#include +#include + +#include "board_opr_interface.h" + +#define DEBUG 0 +/* + * Constants... + */ + +#define MXML_MAJOR_VERSION 2 /* Major version number */ +#define MXML_MINOR_VERSION 11 /* Minor version number */ + +#define MXML_TAB 8 /* Tabs every N columns */ + +#define MXML_NO_CALLBACK 0 /* Don't use a type callback */ +#define MXML_INTEGER_CALLBACK mxml_integer_cb +/* Treat all data as integers */ +#define MXML_OPAQUE_CALLBACK mxml_opaque_cb +/* Treat all data as opaque */ +#define MXML_REAL_CALLBACK mxml_real_cb +/* Treat all data as real numbers */ +#define MXML_TEXT_CALLBACK 0 /* Treat all data as text */ +#define MXML_IGNORE_CALLBACK mxml_ignore_cb +/* Ignore all non-element content */ + +#define MXML_NO_PARENT 0 /* No parent for the node */ + +#define MXML_DESCEND 1 /* Descend when finding/walking */ +#define MXML_NO_DESCEND 0 /* Don't descend when finding/walking */ +#define MXML_DESCEND_FIRST -1 /* Descend for first find */ + +#define MXML_WS_BEFORE_OPEN 0 /* Callback for before open tag */ +#define MXML_WS_AFTER_OPEN 1 /* Callback for after open tag */ +#define MXML_WS_BEFORE_CLOSE 2 /* Callback for before close tag */ +#define MXML_WS_AFTER_CLOSE 3 /* Callback for after close tag */ + +#define MXML_ADD_BEFORE 0 /* Add node before specified node */ +#define MXML_ADD_AFTER 1 /* Add node after specified node */ +#define MXML_ADD_TO_PARENT NULL /* Add node relative to parent */ + +/* + * Data types... + */ + +typedef enum mxml_sax_event_e { + /**** SAX event type. ****/ + MXML_SAX_CDATA, /* CDATA node */ + MXML_SAX_COMMENT, /* Comment node */ + MXML_SAX_DATA, /* Data node */ + MXML_SAX_DIRECTIVE, /* Processing directive node */ + MXML_SAX_ELEMENT_CLOSE, /* Element closed */ + MXML_SAX_ELEMENT_OPEN /* Element opened */ +} mxml_sax_event_t; + +typedef enum mxml_type_e { + /**** The XML node type. ****/ + MXML_IGNORE = -1, /* Ignore/throw away node @since Mini-XML 2.3@ */ + MXML_ELEMENT, /* XML element with attributes */ + MXML_INTEGER, /* Integer value */ + MXML_OPAQUE, /* Opaque string */ + MXML_REAL, /* Real value */ + MXML_TEXT, /* Text fragment */ + MXML_CUSTOM /* Custom data @since Mini-XML 2.1@ */ +} mxml_type_t; + +/**** Custom data destructor ****/ +typedef void (*mxml_custom_destroy_cb_t)(void *); + +/**** Error callback function ****/ +typedef void (*mxml_error_cb_t)(const char *); + +typedef struct mxml_attr_s { + /**** An XML element attribute value. @private@ ****/ + char *name; /* Attribute name */ + char *value; /* Attribute value */ +} mxml_attr_t; + +typedef struct mxml_element_s { + /**** An XML element value. @private@ ****/ + char *name; /* Name of element */ + int num_attrs; /* Number of attributes */ + mxml_attr_t *attrs; /* Attributes */ +} mxml_element_t; + +typedef struct mxml_text_s { + /**** An XML text value. @private@ ****/ + int whitespace; /* Leading whitespace? */ + char *string; /* Fragment string */ +} mxml_text_t; + +typedef struct mxml_custom_s { + /**** An XML custom value. @private@ ****/ + void *data; /* Pointer to (allocated) custom data */ + mxml_custom_destroy_cb_t destroy; /* Pointer to destructor function */ +} mxml_custom_t; + +typedef union mxml_value_u { + /**** An XML node value. @private@ ****/ + mxml_element_t element; /* Element */ + int integer; /* Integer number */ + char *opaque; /* Opaque string */ + mxml_text_t text; /* Text fragment */ + mxml_custom_t custom; /* Custom data @since Mini-XML 2.1@ */ +} mxml_value_t; + +struct mxml_node_s { + /**** An XML node. @private@ ****/ + mxml_type_t type; /* Node type */ + struct mxml_node_s *next; /* Next node under same parent */ + struct mxml_node_s *prev; /* Previous node under same parent */ + struct mxml_node_s *parent; /* Parent node */ + struct mxml_node_s *child; /* First child node */ + struct mxml_node_s *last_child; /* Last child node */ + mxml_value_t value; /* Node value */ + int ref_count; /* Use count */ + void *user_data; /* User data */ +}; + +typedef struct mxml_node_s mxml_node_t; /**** An XML node. ****/ + +struct mxml_index_s { + /**** An XML node index. @private@ ****/ + char *attr; /* Attribute used for indexing or NULL */ + int num_nodes; /* Number of nodes in index */ + int alloc_nodes; /* Allocated nodes in index */ + int cur_node; /* Current node */ + mxml_node_t **nodes; /* Node array */ +}; + +/**** An XML node index. ****/ +typedef struct mxml_index_s mxml_index_t; + +/**** Custom data load callback function ****/ +typedef int (*mxml_custom_load_cb_t)(mxml_node_t *, const char *); + +/**** Custom data save callback function ****/ +typedef char *(*mxml_custom_save_cb_t)(mxml_node_t *); + +/**** Entity callback function */ +typedef int (*mxml_entity_cb_t)(const char *); + +/**** Load callback function ****/ +typedef mxml_type_t (*mxml_load_cb_t)(mxml_node_t *); + +/**** Save callback function ****/ +typedef const char *(*mxml_save_cb_t)(mxml_node_t *, int); + +/**** SAX callback function ****/ +typedef void (*mxml_sax_cb_t)(mxml_node_t *, mxml_sax_event_t, void *); + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Prototypes... + */ + +extern void mxmlAdd(mxml_node_t *parent, int where, mxml_node_t *child, + mxml_node_t *node); +extern void mxmlDelete(mxml_node_t *node); +extern void mxmlElementDeleteAttr(mxml_node_t *node, const char *name); +extern const char *mxmlElementGetAttr(mxml_node_t *node, const char *name); +extern const char *mxmlElementGetAttrByIndex(mxml_node_t *node, int idx, + const char **name); +extern int mxmlElementGetAttrCount(mxml_node_t *node); +extern void mxmlElementSetAttr(mxml_node_t *node, const char *name, + const char *value); +extern void mxmlElementSetAttrf(mxml_node_t *node, const char *name, + const char *format, ...) +#ifdef __GNUC__ + __attribute__((__format__(__printf__, 3, 4))) +#endif /* __GNUC__ */ + ; +extern int mxmlEntityAddCallback(mxml_entity_cb_t cb); +extern const char *mxmlEntityGetName(int val); +extern int mxmlEntityGetValue(const char *name); +extern void mxmlEntityRemoveCallback(mxml_entity_cb_t cb); +extern mxml_node_t *mxmlFindElement(mxml_node_t *node, mxml_node_t *top, + const char *element, const char *attr, + const char *value, int descend); +extern mxml_node_t *mxmlFindPath(mxml_node_t *node, const char *path); +extern const char *mxmlGetCDATA(mxml_node_t *node); +extern const void *mxmlGetCustom(mxml_node_t *node); +extern const char *mxmlGetElement(mxml_node_t *node); +extern mxml_node_t *mxmlGetFirstChild(mxml_node_t *node); +extern int mxmlGetInteger(mxml_node_t *node); +extern mxml_node_t *mxmlGetLastChild(mxml_node_t *node); +extern mxml_node_t *mxmlGetNextSibling(mxml_node_t *node); +extern const char *mxmlGetOpaque(mxml_node_t *node); +extern mxml_node_t *mxmlGetParent(mxml_node_t *node); +extern mxml_node_t *mxmlGetPrevSibling(mxml_node_t *node); +extern int mxmlGetRefCount(mxml_node_t *node); +extern const char *mxmlGetText(mxml_node_t *node, int *whitespace); +extern mxml_type_t mxmlGetType(mxml_node_t *node); +extern void *mxmlGetUserData(mxml_node_t *node); +extern void mxmlIndexDelete(mxml_index_t *ind); +extern mxml_node_t *mxmlIndexEnum(mxml_index_t *ind); +extern mxml_node_t *mxmlIndexFind(mxml_index_t *ind, const char *element, + const char *value); +extern int mxmlIndexGetCount(mxml_index_t *ind); +extern mxml_index_t *mxmlIndexNew(mxml_node_t *node, const char *element, + const char *attr); +extern mxml_node_t *mxmlIndexReset(mxml_index_t *ind); +extern mxml_node_t *mxmlLoadFd(mxml_node_t *top, int fd, + mxml_type_t (*cb)(mxml_node_t *)); +extern mxml_node_t *mxmlLoadString(mxml_node_t *top, const char *s, + mxml_type_t (*cb)(mxml_node_t *)); +extern mxml_node_t *mxmlNewCDATA(mxml_node_t *parent, const char *string); +extern mxml_node_t *mxmlNewCustom(mxml_node_t *parent, void *data, + mxml_custom_destroy_cb_t destroy); +extern mxml_node_t *mxmlNewElement(mxml_node_t *parent, const char *name); +extern mxml_node_t *mxmlNewInteger(mxml_node_t *parent, int integer); +extern mxml_node_t *mxmlNewOpaque(mxml_node_t *parent, const char *opaque); +extern mxml_node_t *mxmlNewOpaquef(mxml_node_t *parent, const char *format, ...) +#ifdef __GNUC__ + __attribute__((__format__(__printf__, 2, 3))) +#endif /* __GNUC__ */ + ; + +extern mxml_node_t *mxmlNewText(mxml_node_t *parent, int whitespace, + const char *string); +extern mxml_node_t *mxmlNewTextf(mxml_node_t *parent, int whitespace, + const char *format, ...) +#ifdef __GNUC__ + __attribute__((__format__(__printf__, 3, 4))) +#endif /* __GNUC__ */ + ; +extern mxml_node_t *mxmlNewXML(const char *version); +extern int mxmlRelease(mxml_node_t *node); +extern void mxmlRemove(mxml_node_t *node); +extern int mxmlRetain(mxml_node_t *node); +extern char *mxmlSaveAllocString(mxml_node_t *node, mxml_save_cb_t cb); +extern int mxmlSaveFd(mxml_node_t *node, int fd, mxml_save_cb_t cb); +extern int mxmlSaveString(mxml_node_t *node, char *buffer, int bufsize, + mxml_save_cb_t cb); +extern mxml_node_t *mxmlSAXLoadFd(mxml_node_t *top, int fd, + mxml_type_t (*cb)(mxml_node_t *), + mxml_sax_cb_t sax, void *sax_data); +extern mxml_node_t *mxmlSAXLoadString(mxml_node_t *top, const char *s, + mxml_type_t (*cb)(mxml_node_t *), + mxml_sax_cb_t sax, void *sax_data); +extern int mxmlSetCDATA(mxml_node_t *node, const char *data); +extern int mxmlSetCustom(mxml_node_t *node, void *data, + mxml_custom_destroy_cb_t destroy); +extern void mxmlSetCustomHandlers(mxml_custom_load_cb_t load, + mxml_custom_save_cb_t save); +extern int mxmlSetElement(mxml_node_t *node, const char *name); +extern void mxmlSetErrorCallback(mxml_error_cb_t cb); +extern int mxmlSetInteger(mxml_node_t *node, int integer); +extern int mxmlSetOpaque(mxml_node_t *node, const char *opaque); +extern int mxmlSetOpaquef(mxml_node_t *node, const char *format, ...) +#ifdef __GNUC__ + __attribute__((__format__(__printf__, 2, 3))) +#endif /* __GNUC__ */ + ; + +extern int mxmlSetText(mxml_node_t *node, int whitespace, const char *string); +extern int mxmlSetTextf(mxml_node_t *node, int whitespace, const char *format, + ...) +#ifdef __GNUC__ + __attribute__((__format__(__printf__, 3, 4))) +#endif /* __GNUC__ */ + ; +extern int mxmlSetUserData(mxml_node_t *node, void *data); +extern void mxmlSetWrapMargin(int column); +extern mxml_node_t *mxmlWalkNext(mxml_node_t *node, mxml_node_t *top, + int descend); +extern mxml_node_t *mxmlWalkPrev(mxml_node_t *node, mxml_node_t *top, + int descend); + +/* + * Semi-private functions... + */ + +extern void mxml_error(const char *format, ...); +extern mxml_type_t mxml_ignore_cb(mxml_node_t *node); +extern mxml_type_t mxml_integer_cb(mxml_node_t *node); +extern mxml_type_t mxml_opaque_cb(mxml_node_t *node); +extern mxml_type_t mxml_real_cb(mxml_node_t *node); + +/* + * C++ support... + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* !_mxml_h_ */ diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.c new file mode 100644 index 000000000000..24204808a2d9 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.c @@ -0,0 +1,900 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : normandy_short_test.c +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : normandy short test +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "normandy_short_test.h" +#include "tp_short_test.h" +#include "simple_mem_manager.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*************************************Private methods start********************************************/ +static s32 have_short_code_in_fw(PST_TP_DEV p_dev); +static s32 download_short_code(ptr32 p_data); +static s32 run_short_code(ptr32 p_data); +static s32 send_cmd(PST_TP_DEV p_dev, u8 cmd, u8 param); +static s32 wait_status(PST_TP_DEV p_dev, u16 sta_addr, u8 right_sta, + u16 time_out); +static s32 send_short_param(ptr32 p_data); +static s32 wait_short_end(PST_TP_DEV p_dev); +static u16 calc_short_gnd_vdd(u16 diff_code, s32 avdd, u8 *p_short_opt); +static u16 calc_short_chn(PST_TP_DEV p_dev, IN u8 chn1, IN u8 chn2, + IN u16 self_code, IN u16 short_code); +static s32 analyse_short_res(ptr32 p_data); +static u8 short_id_to_selfdata_id(PST_TP_DEV p_dev, u8 short_id); +/*************************************Private methods end********************************************/ +/******************************************************************************* +* Function Name : normandy_short_test +* Description : normandy short test +* Input : ptr32 p_data(You must cast it to type 'PST_TEST_ITEM' ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 normandy_short_test(IN_OUT ptr32 p_data) +{ + s32 ret = 0; + PST_SHORT_PARAM p_param = NULL; + PST_SHORT_TEST_RES p_test_res = NULL; + PST_TEST_ITEM p_item = NULL; + PST_TP_DEV p_dev = NULL; + p_item = (PST_TEST_ITEM)p_data; + if (NULL == p_item) { + board_print_error("%s\n", + "in short test, p_item parameter is NULL"); + goto NORMANDY_SHORT_TEST_END; + } + p_dev = p_item->p_tp_dev; + p_param = (PST_SHORT_PARAM)p_item->param.ptr_param; + if (NULL == p_param) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SHORT_TEST_PARAMETER_ERROR; + p_test_res->item_res_header.test_status = TEST_ABORTED; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error("%s\n", "in short test, parameter is NULL"); + goto NORMANDY_SHORT_TEST_END; + } + + p_test_res = (PST_SHORT_TEST_RES)p_item->test_res.ptr_res; + /*clear short mess*/ + clear_short_mess_in_res(p_item); + /*********test program*************/ + ret = have_short_code_in_fw(p_dev); + if (1 != ret) { + /*download short code in ram,and run this code*/ + ret = download_short_code(p_data); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = + SHORT_TEST_DOWNLOAD_FW_FAIL; + p_test_res->item_res_header.test_status = TEST_ABORTED; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error( + "%s\n", + "in short test, download short fw fail"); + goto NORMANDY_SHORT_TEST_END; + } + } + /* (2)run short code*/ + ret = run_short_code(p_data); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SHORT_TEST_RUN_FW_FAIL; + p_test_res->item_res_header.test_status = TEST_ABORTED; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error("%s\n", "in short test, run short fw error"); + goto NORMANDY_SHORT_TEST_END; + } + /*(3)send short param*/ + ret = send_short_param(p_data); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SHORT_TEST_SEND_PARAMETER_FAIL; + p_test_res->item_res_header.test_status = TEST_ABORTED; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error("%s\n", + "in short test, send short parameter fail"); + goto NORMANDY_SHORT_TEST_END; + } + /* (4)wait test end*/ + ret = wait_short_end(p_dev); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SHORT_TEST_END_FAIL; + p_test_res->item_res_header.test_status = TEST_ABORTED; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error("%s\n", "in short test, wait test end fail"); + goto NORMANDY_SHORT_TEST_END; + } + /* (5)annlyze short result*/ + ret = analyse_short_res(p_data); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SHORT_TEST_ANALYSIS_RESULT_FAIL; + p_test_res->item_res_header.test_status = TEST_ABORTED; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error( + "%s\n", + "in short test, annlyze short test result fail"); + goto NORMANDY_SHORT_TEST_END; + } + + short_test_channel_map(p_item, TX_RX_SHARED); + p_test_res->item_res_header.test_status = TEST_FINISH; +NORMANDY_SHORT_TEST_END: + return ret; +} + +#ifdef __cplusplus +} +#endif + +/******************************************************************************* +* Function Name : have_short_code_in_fw +* Description : Judge that is there short code in firmware +* Input : PST_TP_DEV p_dev +* Output : none +* Return : s32(0:not exist short code in fw 1:exist short code in fw) +*******************************************************************************/ +static s32 have_short_code_in_fw(IN PST_TP_DEV p_dev) +{ + return 1; +} + +/******************************************************************************* +* Function Name : download_short_code +* Description : download short code +* Input : ptr32 p_data(You must cast it to type 'PST_TEST_ITEM' ) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 download_short_code(IN ptr32 p_data) +{ + return 0; +} + +/******************************************************************************* +* Function Name : run_short_code +* Description : run short code +* Input : ptr32 p_data(You must cast it to type 'PST_TEST_ITEM' ) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 run_short_code(IN ptr32 p_data) +{ + s32 ret = 0; + u8 i = 0, retry_cnt = 3; + PST_TEST_ITEM p_item = NULL; + PST_TP_DEV p_dev = NULL; + p_item = (PST_TEST_ITEM)p_data; + p_dev = p_item->p_tp_dev; + + for (i = 0; i < retry_cnt; i++) { + /*switch to short firmware*/ + ret = send_cmd(p_dev, 0x0B, 0x00); + if (0 == ret) { + continue; + } + /*delay 130ms -> 50ms*/ + board_delay_ms(50); + + /*wait short ready*/ + ret = wait_status(p_dev, NORM_SHORT_STA_ADDR, + NORM_SHORT_STA_READY, 200); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error("%s\n", "switch to short firmware fail"); + } + return ret; +} + +/******************************************************************************* +* Function Name : send_cmd +* Description : send_cmd +* Input : PST_TP_DEV p_dev +* Input : u8 cmd +* Input : u8 param +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 send_cmd(IN PST_TP_DEV p_dev, IN u8 cmd, IN u8 param) +{ + s32 ret = 0; + u8 buf_arr[3]; + buf_arr[0] = cmd; + buf_arr[1] = param; + buf_arr[2] = (u8)(0 - (cmd + param)); + ret = chip_reg_write(p_dev, p_dev->real_cmd_addr, buf_arr, 3); + return ret; +} + +/******************************************************************************* +* Function Name : wait_status +* Description : wait_status +* Input : PST_TP_DEV p_dev +* Input : u16 sta_addr +* Input : u8 right_sta +* Input : u16 time_out +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 wait_status(IN PST_TP_DEV p_dev, IN u16 sta_addr, IN u8 right_sta, + IN u16 time_out) +{ + s32 ret = 0; + u16 i = 0; + u16 cnt = (time_out + 9) / 10; + /*make sure unequal for initialization*/ + u8 data_tmp = right_sta - 1; + + for (i = 0; i < cnt; i++) { + ret = chip_reg_read(p_dev, sta_addr, &data_tmp, 1); + if ((ret == 1) && (data_tmp == right_sta)) { + break; + } + board_delay_ms(10); + } + if (i >= cnt) { + ret = 0; + board_print_debug("short test status:0x%02x!\n", data_tmp); + } + return ret; +} + +/******************************************************************************* +* Function Name : send_short_param +* Description : send_short_param +* Input : ptr32 p_data(You must cast it to type 'PST_TEST_ITEM' ) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 send_short_param(IN ptr32 p_data) +{ + s32 ret = 0; + u8 buf_tmp[10]; + + PST_TEST_ITEM p_item = NULL; + PST_TP_DEV p_dev = NULL; + PST_SHORT_PARAM p_short_param = NULL; + p_item = (PST_TEST_ITEM)p_data; + p_dev = p_item->p_tp_dev; + p_short_param = (PST_SHORT_PARAM)p_item->param.ptr_param; + + /*data store in normandy ram wit big-endian + //Tx&Tx Rx&Rx Tx&Rx short adc threshold + */ + buf_tmp[0] = ((p_short_param->short_threshold.gt_short_threshold >> 8) & + 0xFF); + buf_tmp[1] = + ((p_short_param->short_threshold.gt_short_threshold) & 0xFF); + /*diffcode threshold*/ + buf_tmp[2] = + ((p_short_param->short_threshold.diffcode_short_threshold >> + 8) & + 0xFF); + buf_tmp[3] = + ((p_short_param->short_threshold.diffcode_short_threshold) & + 0xFF); + /*adc read delay*/ + buf_tmp[4] = + ((p_short_param->short_threshold.adc_read_delay >> 8) & 0xFF); + buf_tmp[5] = ((p_short_param->short_threshold.adc_read_delay) & 0xFF); + ret = chip_reg_write(p_dev, NORM_SHORT_TXRX_ADC_THD_ADDR, buf_tmp, 6); + if (0 == ret) { + board_print_error( + "%s\n", + "send tx&rx or gnd&vdd adc threshold or adc delay fail"); + goto SEND_END; + } + /*Intialize cfg ,and start test*/ + buf_tmp[0] = 0x01; + ret = chip_reg_write(p_dev, 0x5095, buf_tmp, 1); + if (0 == ret) { + board_print_error("%s\n", "write 0x01 to 0x5095 fail"); + goto SEND_END; + } +SEND_END: + return ret; +} + +/******************************************************************************* +* Function Name : wait_short_end +* Description : wait shott end +* Input : PST_TP_DEV p_dev +* Output : none +* Return : u8(0:fail 1:short test end) +*******************************************************************************/ +static s32 wait_short_end(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + u8 tmp_data = 0; + + /*send start short test cmd*/ + tmp_data = 0x01; + ret = chip_reg_write(p_dev, NORM_SHORT_STA_ADDR, &tmp_data, 1); + if (0 == ret) { + board_print_error("%s\n", "send start short test cmd fail!"); + goto WAIT_END; + } + /*delay 1800ms*/ + board_delay_ms(1800); + /*wait test end*/ + ret = wait_status(p_dev, NORM_SHORT_TESTEND_ADDR, + NORM_SHORT_ALL_TEST_END, 1200); + if (0 == ret) { + board_print_error("%s\n", "wait test end fail!"); + goto WAIT_END; + } +WAIT_END: + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_group +* Description : get the group of channel +* Input : u8 chn +* Output : none +* Return : u8(group num the channel in) +*******************************************************************************/ +static u8 get_chn_group(IN u8 chn) +{ + u8 group = 0; + + if ((chn >= 0) && (chn < 9)) { /*pad s0~s8*/ + group = 5; + } else if ((chn >= 9) && (chn < 14)) { /*pad s9~s13*/ + group = 4; + } else if ((chn >= 14) && (chn < 18)) { /*pad s14~s17*/ + group = 3; + } else if ((chn >= 18) && (chn < 27)) { /* pad s18~s26*/ + group = 2; + } else if ((chn >= 27) && (chn < 32)) { /* pad s27~s31*/ + group = 1; + } else if ((chn >= 32) && (chn < 36)) { /* pad s32~s35*/ + group = 0; + } else if ((chn >= 36) && (chn < 45)) { /* pad d0~d8*/ + group = 5; + } else if ((chn >= 45) && (chn < 54)) { /* pad d9~d17*/ + group = 2; + } else if ((chn >= 54) && (chn < 59)) { /* pad d18~d22*/ + group = 1; + } else if ((chn >= 59) && (chn < 63)) { /* pad d23~d26*/ + group = 0; + } else if ((chn >= 63) && (chn < 67)) { /* pad d27~d30*/ + group = 3; + } else if ((chn >= 67) && (chn < 72)) { /* pad d31~d35*/ + group = 4; + } else if ((chn >= 72) && (chn < 76)) { /* pad d36~d39 */ + group = 0; + } + return group; +} + +/******************************************************************************* +* Function Name : calc_short_gnd_vdd +* Description : calculate short between channel with gnd or vdd(similar to gt9p) +* Input : u16 diff_code +* Input : s32 avdd +* Output : u8* p_short_opt(0:gnd short 1:vdd short) +* Return : u16((resistor(0.1kom))) +*******************************************************************************/ +static u16 calc_short_gnd_vdd(IN u16 diff_code, IN s32 avdd, + OUT u8 *p_short_opt) +{ + s32 r = 0; + if ((diff_code & 0x7fff) == 0) { + diff_code += 1; + } + /*bit15==1 means vdd,bit15==0 means gnd*/ + if ((diff_code & (0x8000)) == 0) { /*short to GND*/ + /*52662.85/diff_code-40*/ + r = (526628 / (diff_code & (~0x8000)) - 40 * 10); + *p_short_opt = 0; + } else { /*short to VDD*/ + diff_code &= (~0x8000); + r = 9 * 1024 * (avdd - 9) * 40 / diff_code / 7 - 40 * 10; + *p_short_opt = 1; + } + /*r *= 2;*/ + if (r < 65530) { + ; + } else { + r = 65535; + } + board_print_info("GND/VDD r:%d", r); + return (u16)(r >= 0 ? r : 0); +} + +/******************************************************************************* +* Function Name : calc_short_chn +* Description : calculate short between chn1 with chn2 +* Input : PST_TP_DEV p_dev + : u8 chn1 +* Input : u8 chn2 +* Input : u16 self_code +* Input : u16 short_code +* Output : none +* Return : u16(resistor(0.1kom)) +*******************************************************************************/ +static u16 calc_short_chn(PST_TP_DEV p_dev, IN u8 chn1, IN u8 chn2, + IN u16 self_code, IN u16 short_code) +{ + s32 r = 0; + s32 b_in_same_grp = 0; + u8 group1 = 0; + u8 group2 = 0; + u8 die_num1 = 0; + u8 die_num2 = 0; + u8 chn_flag = 0; + if (((chn1 & CHANNEL_TX_FLAG) == CHANNEL_TX_FLAG) && + ((chn2 & CHANNEL_TX_FLAG) == CHANNEL_TX_FLAG)) { + chn1 &= ~CHANNEL_TX_FLAG; + chn2 &= ~CHANNEL_TX_FLAG; + group1 = get_chn_group(chn1); + group2 = get_chn_group(chn2); + chn_flag = 1; + if (group1 == group2) { + b_in_same_grp = 1; + die_num1 += chn1; + die_num2 += chn2; + } + } else if (((chn1 & CHANNEL_TX_FLAG) == 0) && + ((chn2 & CHANNEL_TX_FLAG) == 0)) { + group1 = get_chn_group(chn1); + group2 = get_chn_group(chn2); + chn_flag = 1; + if (group1 == group2) { + b_in_same_grp = 1; + } + } + + if (!b_in_same_grp) { + r = (10 * self_code * 81 / short_code - 81 * 10); + } else { + die_num1 = (die_num1 >= die_num2) ? (die_num1 - die_num2) : + (die_num2 - die_num1); + if ((die_num1 > 3) && (group1 == 0)) { /*different setting*/ + r = (10 * self_code * 81 / short_code - 81 * 10); + } else { + r = (10 * self_code * 64 / short_code - 64 * 10); + } + } + if (r < 65535) { + ; + } else { + r = 65535; + } + return (u16)(r >= 0 ? r : 0); +} + +/******************************************************************************* +* Function Name : analyse_short_res +* Description : analyse short result +* Input : ptr32 p_data(You must cast it to type 'PST_TEST_ITEM' ) +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +static s32 analyse_short_res(IN_OUT ptr32 p_data) +{ + s32 ret = 0; + u8 *p_tmp_data_arr = NULL; + u16 i = 0, j = 0; + u16 retry_cnt = 3; + PST_TEST_ITEM p_test_item = NULL; + PST_TP_DEV p_dev = NULL; + PST_SHORT_PARAM p_short_param = NULL; + PST_SHORT_TEST_RES p_short_res = NULL; + + u16 short_code_tmp = 0; + u16 data_len_tmp = 0; + u16 tmp_data16 = 0; + u8 chn_id_tmp1 = 0; + u8 chn_id_tmp2 = 0; + u8 id_tmp = 0; + u8 short_flag = 0; + u8 chn_short_cnt[3]; + u16 diff_code_tmp = 0; + u16 short_r = 0; + u16 *p_self_code_arr = NULL; + u16 chn_short_mess_addr = 0; + u8 max_sen_num_in_die = 0; + u8 max_drv_num_in_die = 0; + + p_test_item = (PST_TEST_ITEM)p_data; + p_dev = p_test_item->p_tp_dev; + p_short_param = (PST_SHORT_PARAM)p_test_item->param.ptr_param; + p_short_res = (PST_SHORT_TEST_RES)p_test_item->test_res.ptr_res; + max_sen_num_in_die = p_dev->max_sen_num_in_die; + max_drv_num_in_die = p_dev->max_drv_num_in_die; + + data_len_tmp = (max_drv_num_in_die + max_sen_num_in_die) * 2; + ret = alloc_mem_block((void **)&p_tmp_data_arr, data_len_tmp); + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse short test result, malloc memory for p_tmp_data_arr fail"); + goto ANALYSE_SHORT_RES_END; + } + + data_len_tmp = (max_drv_num_in_die + max_sen_num_in_die) * 2; + ret = alloc_mem_block((void **)&p_self_code_arr, data_len_tmp); + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse short test result, malloc memory for self_code_arr fail"); + goto ANALYSE_SHORT_RES_END; + } + /*judge short flag*/ + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_dev, NORM_SHORT_TEST_RESULT_ADDR, + &short_flag, 1); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse short test result, read short flag fail"); + goto ANALYSE_SHORT_RES_END; + } + + /*short_flag: + bit0: Tx & Tx + bit1: Rx & Rx + bit2: Tx & Rx + bit3: Tx/Rx & GND/VDD + */ + + if (0 == (short_flag & 0x0F)) { + /*board_print_error("%s\n", "in analyse short test result, read short flag fail");*/ + goto ANALYSE_SHORT_RES_END; + } + /*bit3: Tx/Rx & GND/VDD */ + data_len_tmp = (max_drv_num_in_die + max_sen_num_in_die) * 2; + if (0x08 == (short_flag & 0x08)) { + /*get diffcode*/ + for (i = 0; i < retry_cnt; i++) { + /*NORM_SHORT_DIFFCODE_ADDR is the start address of diffcode*/ + ret = chip_reg_read(p_dev, NORM_SHORT_DIFFCODE_ADDR, + p_tmp_data_arr, data_len_tmp); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse Tx/Rx & GND/VDD, read diffcode fail"); + goto ANALYSE_SHORT_RES_END; + } + for (i = 0; i < data_len_tmp; i += 2) { + diff_code_tmp = (p_tmp_data_arr[i] << 8) + + p_tmp_data_arr[i + 1]; + /*calculate short_r*/ + short_r = calc_short_gnd_vdd( + diff_code_tmp, (10 * p_dev->power_volt / 1000), + &chn_id_tmp2); + chn_id_tmp1 = i >> 1; + + /*must convert it + //|max_drv_num_in_die|max_sen_num_in_die| + */ + if (chn_id_tmp1 < max_drv_num_in_die) { + chn_id_tmp1 += max_sen_num_in_die; + chn_id_tmp1 |= CHANNEL_TX_FLAG; + tmp_data16 = + p_short_param->short_threshold + .drv_gnd_vdd_resistor_threshold * + 10; + } else { + chn_id_tmp1 -= max_drv_num_in_die; + tmp_data16 = + p_short_param->short_threshold + .sen_gnd_vdd_resistor_threshold * + 10; + } + if (1 == chn_id_tmp2) { + chn_id_tmp2 = CHANNEL_VDD; + } else if (0 == chn_id_tmp2) { + chn_id_tmp2 = CHANNEL_GND; + } + /*store this data in result*/ + if (short_r < tmp_data16) { + store_short_mess_in_res(chn_id_tmp1, + chn_id_tmp2, short_r, + p_short_res); + } + } + } + + /*get self code*/ + data_len_tmp = (max_drv_num_in_die + max_sen_num_in_die) * 2; + for (i = 0; i < retry_cnt; i++) { + /*NORM_SHORT_DRVSELFCODE_ADDR is the start address of self code*/ + ret = chip_reg_read(p_dev, NORM_SHORT_DRVSELFCODE_ADDR, + p_tmp_data_arr, data_len_tmp); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error("%s\n", + "in analyse Tx/Rx, read selfcode fail"); + goto ANALYSE_SHORT_RES_END; + } + for (i = 0; i < data_len_tmp / 2; i++) { + p_self_code_arr[i] = ((p_tmp_data_arr[2 * i] << 8) + + p_tmp_data_arr[2 * i + 1]) & + 0x7FFF; + } + + /*get channel short cnt*/ + for (i = 0; i < retry_cnt; i++) { + /*0x8042 Tx&Tx short cnt + //0x8043 Rx&Rx short cnt + //0x8044 Tx&Rx short cnt + */ + ret = chip_reg_read(p_dev, NORM_SHORT_NUMBER_ADDR, + chn_short_cnt, 3); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse Tx/Rx, read channel short cnt fail"); + goto ANALYSE_SHORT_RES_END; + } + /*Tx & Tx*/ + if (0x01 == (short_flag & 0x01)) { + chn_short_mess_addr = NORM_SHORT_TxTx_PIN_NUM_ADDR; + /*2 bytes short pin num + //2 bytes reserved + //2*max_drv_num_in_die bytes TX buffer + //2 bytes check sum + */ + data_len_tmp = 2 + 2 + 2 * max_drv_num_in_die + 2; + for (i = 0; i < chn_short_cnt[0]; i++) { + /*get short code*/ + for (j = 0; j < retry_cnt; j++) { + ret = chip_reg_read(p_dev, chn_short_mess_addr, + p_tmp_data_arr, + data_len_tmp); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse Tx & Tx, read short code fail"); + goto ANALYSE_SHORT_RES_END; + } + /*calc resistor + Normandy Sens Pad and Drv Pads is Unified Numbering + 0~35 is s0~s35(RX) And 36~76 is d0 ~d40(TX) + */ + chn_id_tmp1 = + (p_tmp_data_arr[0] << 8) + p_tmp_data_arr[1]; + { + /*Tx*/ + for (j = 0; j < max_drv_num_in_die; j++) { + short_code_tmp = + (p_tmp_data_arr[NORM_SHORT_HEAD + + j * 2] + << 8) + + p_tmp_data_arr[NORM_SHORT_HEAD + + j * 2 + 1]; + chn_id_tmp1 |= CHANNEL_TX_FLAG; + chn_id_tmp2 = (j + max_sen_num_in_die) | + CHANNEL_TX_FLAG; + if (short_code_tmp >= + p_short_param->short_threshold + .gt_short_threshold) { + id_tmp = short_id_to_selfdata_id( + p_dev, chn_id_tmp1); + short_r = calc_short_chn( + p_dev, chn_id_tmp1, + chn_id_tmp2, + p_self_code_arr[id_tmp], + short_code_tmp); + if (short_r < + p_short_param->short_threshold + .drv_drv_resistor_threshold * + 10) { + store_short_mess_in_res( + chn_id_tmp1, + chn_id_tmp2, + short_r, + p_short_res); + } + } + } + } + /*update address*/ + chn_short_mess_addr += data_len_tmp; + } + } + /*Rx & Rx*/ + if (0x02 == (short_flag & 0x02)) { + chn_short_mess_addr = NORM_SHORT_RxRx_PIN_NUM_ADDR; + /*2 bytes short pin num + //2 bytes reserved + //2*max_sen_num_in_die bytes RX buffer + //2 bytes check sum + */ + data_len_tmp = 2 + 2 + 2 * max_sen_num_in_die + 2; + for (i = 0; i < chn_short_cnt[1]; i++) { + /*get short code*/ + for (j = 0; j < retry_cnt; j++) { + ret = chip_reg_read(p_dev, chn_short_mess_addr, + p_tmp_data_arr, + data_len_tmp); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse Rx & Rx, read short code fail"); + goto ANALYSE_SHORT_RES_END; + } + /*calc resistor*/ + chn_id_tmp1 = (p_tmp_data_arr[0] << 8) + + p_tmp_data_arr[1]; /*Rx*/ + { + /*Rx*/ + for (j = 0; j < max_sen_num_in_die; j++) { + /*filter this case*/ + if (j == chn_id_tmp1 || + (j < chn_id_tmp1 && + ((j & 0x01) == 0))) { + continue; + } + + short_code_tmp = + (p_tmp_data_arr[NORM_SHORT_HEAD + + j * 2] + << 8) + + p_tmp_data_arr[NORM_SHORT_HEAD + + j * 2 + 1]; + chn_id_tmp2 = (u8)j; + if (short_code_tmp >= + p_short_param->short_threshold + .gt_short_threshold) { + id_tmp = short_id_to_selfdata_id( + p_dev, chn_id_tmp1); + short_r = calc_short_chn( + p_dev, chn_id_tmp1, + chn_id_tmp2, + p_self_code_arr[id_tmp], + short_code_tmp); + if (short_r < + p_short_param->short_threshold + .sen_sen_resistor_threshold * + 10) { + store_short_mess_in_res( + chn_id_tmp1, + chn_id_tmp2, + short_r, + p_short_res); + } + } + } + } + /*update address*/ + chn_short_mess_addr += data_len_tmp; + } + } + /*Tx & Rx*/ + if (0x04 == (short_flag & 0x04)) { + chn_short_mess_addr = NORM_SHORT_TxRx_PIN_NUM_ADDR; + /*2 bytes short pin num + //2 bytes reserved + //2*max_drv_num_in_die bytes RX buffer + //2 bytes check sum + */ + data_len_tmp = 2 + 2 + 2 * max_drv_num_in_die + 2; + for (i = 0; i < chn_short_cnt[2]; i++) { + /*get short code*/ + for (j = 0; j < retry_cnt; j++) { + ret = chip_reg_read(p_dev, chn_short_mess_addr, + p_tmp_data_arr, + data_len_tmp); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "%s\n", + "in analyse Tx & Rx, read short code fail"); + goto ANALYSE_SHORT_RES_END; + } + /*calc resistor*/ + chn_id_tmp1 = (p_tmp_data_arr[0] << 8) + + p_tmp_data_arr[1]; /*Rx*/ + { + /*Tx*/ + for (j = 0; j < max_drv_num_in_die; j++) { + short_code_tmp = + (p_tmp_data_arr[NORM_SHORT_HEAD + + j * 2] + << 8) + + p_tmp_data_arr[NORM_SHORT_HEAD + + j * 2 + 1]; + chn_id_tmp2 = (j + max_sen_num_in_die) | + CHANNEL_TX_FLAG; + if (short_code_tmp >= + p_short_param->short_threshold + .gt_short_threshold) { + id_tmp = short_id_to_selfdata_id( + p_dev, chn_id_tmp1); + short_r = calc_short_chn( + p_dev, chn_id_tmp1, + chn_id_tmp2, + p_self_code_arr[id_tmp], + short_code_tmp); + if (short_r < + p_short_param->short_threshold + .drv_sen_resistor_threshold * + 10) { + store_short_mess_in_res( + chn_id_tmp1, + chn_id_tmp2, + short_r, + p_short_res); + } + } + } + } + /*update address*/ + chn_short_mess_addr += data_len_tmp; + } + } + if (p_short_res->short_num > 0) { + p_short_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SHORT_TEST_EXIST_SHORT; + p_short_res->item_res_header.test_status = TEST_ABORTED; + p_short_res->item_res_header.test_result = TEST_NG; + } + +ANALYSE_SHORT_RES_END: + free_mem_block(p_tmp_data_arr); + free_mem_block(p_self_code_arr); + return ret; +} + +/******************************************************************************* +* Function Name : short_id_to_selfdata_id +* Description : short_id_to_selfdata_id +* Input : PST_TP_DEV p_dev +* Input : u8 short_id +* Output : none +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +static u8 short_id_to_selfdata_id(IN PST_TP_DEV p_dev, IN u8 short_id) +{ + u8 ret = 0; + /*drv*/ + if ((short_id & CHANNEL_TX_FLAG) == CHANNEL_TX_FLAG) { + ret = (short_id & ~CHANNEL_TX_FLAG) - p_dev->max_sen_num_in_die; + } else { + ret = short_id + p_dev->max_drv_num_in_die; + } + return ret; +} + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.h new file mode 100644 index 000000000000..328110725ac2 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/normandy_short_test.h @@ -0,0 +1,56 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : normandy_short_test.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 10/26/2017 +* Description : normandy short test +*******************************************************************************/ +#ifndef NORMANDY_SHORT_TEST_H +#define NORMANDY_SHORT_TEST_H + +#include "user_test_type_def.h" + +#include "test_item_def.h" +#include "tp_dev_control.h" +#include "public_fun.h" + +/*------------------------------------define-----------------------------------*/ +/*Address*/ +#define NORM_SHORT_STA_ADDR 0x5095 +#define NORM_ESD_KEY_ADDR 0x20B0 +#define NORM_SHORT_TXRX_ADC_THD_ADDR 0x8408 +#define NORM_SHORT_DIFF_THD_ADDR 0x840A +#define NORM_ADC_READ_DELAY_ADDR 0x840C + +#define NORM_SEN_CONFIG_ADDR 0x8436 +#define NORM_DRV_CONFIG_ADDR 0x840E +#define NORM_SHORT_CHECKSUM_ADDR 0x845A + +#define NORM_SHORT_TESTEND_ADDR 0x8400 +#define NORM_SHORT_TEST_RESULT_ADDR 0x8401 +#define NORM_SHORT_NUMBER_ADDR 0x8402 +#define NORM_SHORT_DRVSELFCODE_ADDR 0xA8E0 +#define NORM_SHORT_DIFFCODE_ADDR 0xA97A +#define NORM_SHORT_TxTx_PIN_NUM_ADDR 0x8460 +#define NORM_SHORT_RxRx_PIN_NUM_ADDR 0x91D0 +#define NORM_SHORT_TxRx_PIN_NUM_ADDR 0x9CC8 + +/*Status*/ +#define NORM_SHORT_STA_READY 0xAA +#define NORM_SHORT_START_TEST 0x00 +#define NORM_SHORT_TX_TEST_END 0x08 +#define NORM_SHORT_RX_TEST_END 0x80 +#define NORM_SHORT_ALL_TEST_END 0x88 + +#define NORM_SHORT_HEAD 4 +/*------------------------------------define-----------------------------------*/ +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 normandy_short_test(ptr32 p_data); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.c new file mode 100644 index 000000000000..2d46c4c56d45 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.c @@ -0,0 +1,59 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : public_func.cpp +* Author : Bob Huang +* Version : V1.0.0 +* Date : 10/23/2017 +* Description : this file contain some public functions that do not depend + on platform such as Windows,Arm or Android +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifdef __cplusplus +extern "C" { +#endif + +#include "public_fun.h" + +/******************************************************************************* +* Function Name : compare_buffer +* Description : compare_buffer +* Input : u8* src_buf + : u8* dest_buf + : u8 size +* Output : none +* Return : src_buf == dest_buf 1 else return 0 +*******************************************************************************/ +extern s32 compare_buffer(IN u8 *src_buf, IN u8 *dest_buf, IN u8 size) +{ + u8 index; + for (index = 0; index < size; size++) { + if (src_buf[index] != dest_buf[index]) { + return 0; + } + } + return 1; +} + +/******************************************************************************* +* Function Name : current_test_status +* Description : compare_buffer +* Input : IN u8 res +* Output : IN_OUT P_TEST_ITEM_RES p_res +* Return : 1,0 +*******************************************************************************/ +extern s32 current_test_status(IN u8 res, IN_OUT P_TEST_ITEM_RES p_res) +{ + if (res == 1) + return 1; + else { + p_res->test_status = TEST_ABORTED; + p_res->test_result = TEST_WARNING; + } + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.h new file mode 100644 index 000000000000..92f47b8b493a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/public_fun.h @@ -0,0 +1,28 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : public_func.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 10/23/2017 +* Description : this file contain some public functions that do not depend + on platform such as Windows,Arm or Android +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef PUBLIC_FUN_H +#define PUBLIC_FUN_H + +#include "user_test_type_def.h" +#include "test_item_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 compare_buffer(u8 *src_buf, u8 *dest_buf, u8 size); +extern s32 current_test_status(u8 res, P_TEST_ITEM_RES p_res); + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/res_inc.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/res_inc.h new file mode 100644 index 000000000000..0c67c5360790 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/res_inc.h @@ -0,0 +1,167 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : res_inc.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 01/22/2018 +* Description : resource include +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef RES_INC_H +#define RES_INC_H + +/*#ifdef __cplusplus +extern "C" { +#endif*/ + +#include "user_test_type_def.h" +#include "tp_dev_def.h" +#if ARM_CODE == 1 +#ifdef STM32F4XX +#include "stm32f4xx.h" +#endif +#ifdef STM32F1XX +/*STM32F10x Library Definitions*/ +#include "Gpio_define.h" +#endif +#elif PC_CODE == 1 +#include "TestInclude.h" + +#ifdef _DEBUG +#include "MemoryLeakDetected.h" +#define new DEBUG_NEW +#endif + +#elif QNX_CODE == 1 + +#endif +/****************************test board resouce define***************************/ +#if ARM_CODE != 1 + +#define GPIO_Pin_0 ((u16)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((u16)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((u16)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((u16)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((u16)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((u16)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((u16)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((u16)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((u16)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((u16)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((u16)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((u16)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((u16)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((u16)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((u16)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((u16)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((u16)0xFFFF) /* All pins selected */ + +typedef enum { + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +/*Test board Rst pin*/ +#define MODULE_SHDN GPIO_Pin_12 +#define MODULE_SHDN_PORT TPYE_GPIO_C + +#define nV_LEVEL_EN_PORT TPYE_GPIO_B +#define nV_LEVEL_EN_PIN GPIO_Pin_4 + +#define G_IC_INT_PORT TPYE_GPIO_B +#define G_IC_INT_PIN GPIO_Pin_2 + +#define G_SPI_NSS_PORT TPYE_GPIO_B +#define G_SPI_NSS_PIN GPIO_Pin_12 /*SPI_CS*/ + +#define ADC_GF_INT_PORT TPYE_GPIO_B +#define ADC_GF_INT_PIN GPIO_Pin_1 + +#define GF_RST_PORT TPYE_GPIO_B +#define GF_RST_PIN GPIO_Pin_0 + +#define G_IC_SHDN_PORT TPYE_GPIO_B +#define G_IC_SHDN_PIN GPIO_Pin_11 + +#define DAC_PROPER_RANGE (u16)15 /*if (1-x)% ~ (1+x)% dac output ok*/ +#define DVE_TYPE_IIC 0x00; +#define DVE_TYPE_SPI 0x01; +#else +#include "stm32f10x_gpio.h" +#endif + +enum { + TPYE_GPIO_A, + TPYE_GPIO_B, + TPYE_GPIO_C, + TPYE_GPIO_D, + TPYE_GPIO_E, + TPYE_GPIO_F, + TPYE_GPIO_G, + TPYE_GPIO_H, +}; + +/*io mode type*/ +typedef enum { GIO_LOW = 0x00, GIO_HIGH = 0x01 } GIOBit_Def; + +typedef enum { + Mode_AIN = 0x00, + Mode_IPD = 0x28, + Mode_IPU = 0x48, + Mode_Out_OD = 0x14, + Mode_Out_PP = 0x10, + Mode_AF_OD = 0x1C, + Mode_AF_PP = 0x18, + + MODE_PD = 0x02, /*pull down*/ + MODE_PU = 0x03, /*pull up*/ + Mode_IN_FLOATING = 0x04, /*floating*/ + MODE_OUTPUT = 0x05 /*output*/ +} GIOMode_Def; +/*define INT id*/ +#define MODULE_INT_ID 5 +/* +// in test board we use pin12 as shdn to reset chip +// how to know group of pin +// in doc we can see PA PB PC PD,for example, +// look for GUITAR TEST TOOL SCH V4.1_20150624.pdf +// we know line 53-PC12/USART5_TX is MODULE_SHDN ,so we can use GPIOC*/ +#define MODULE_IC GPIO_Pin_2 +#define MODULE_EN GPIO_Pin_4 +/* PB5 GPIOB*/ +#define MODULE_INT GPIO_Pin_5 +#define MODULE_SCL GPIO_Pin_8 +#define MODULE_SDA GPIO_Pin_9 + +#define ADC_I_AVDD GPIO_Pin_6 +#define ADC_Is_AVDD GPIO_Pin_7 + +/*ADC define*/ +#define ADC_V_AVDD_VALUE ((u8)0x01) +#define ADC_V_VDDIO_VALUE ((u8)0x02) +#define ADC_VREF_PIN_VALUE ((u8)0x03) +#define ADC_I_AVDD_VALUE ((u8)0x04) +#define ADC_Is_AVDD_VALUE ((u8)0x05) +#define ADC_I_VDDIO_VALUE ((u8)0x0C) +#define ADC_Is_VDDIO_VALUE ((u8)0x0D) +#define ADC_M_SHDN_VALUE ((u8)0x08) +#define ADC_M_INT_VALUE ((u8)0x09) +#define ADC_M_SCL_VALUE ((u8)0x0A) +#define ADC_M_SDA_VALUE ((u8)0x0B) +#define ADC_GF_RST_VALUE ((u8)0x06) +#define ADC_GF_INT_VALUE ((u8)0x07) + +/*ADS1015 define*/ +#define ADS_FLAG 0x80 +#define ADS_SPI_CS_VALUE ((u8)(0x4 | ADS_FLAG)) +#define ADS_SPI_SCK_VALUE ((u8)(0x5 | ADS_FLAG)) +#define ADS_SPI_MOSI_VALUE ((u8)(0x6 | ADS_FLAG)) +#define ADS_SPI_MISO_VALUE ((u8)(0x7 | ADS_FLAG)) + +/*#ifdef __cplusplus +} +#endif*/ + +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.c new file mode 100644 index 000000000000..0360b883e515 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.c @@ -0,0 +1,355 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : save_test_data.cpp +* Author : +* Version : V1.0.0 +* Date : 27/03/2018 +* Description : save test data +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "save_test_data.h" + +#include "tp_dev_control.h" +#include "tp_open_test.h" +#include "tp_short_test.h" +#include "tp_version_test.h" +#include "tp_additional_option.h" +#include "simple_mem_manager.h" +#include "test_order.h" +#include "generic_func.h" +#include "board_opr_interface.h" +/******************************************************************************* +* Function Name : print_rawdata_test_res +* Description : print rawdata test reult +* Input : ptr32 p_data (You must cast it to type PST_TEST_ORDER ) +* Output : ptr32 p_data +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 print_rawdata_test_res(ptr32 p_data) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_ITEM p_test_item = NULL; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + s32 open_test_res = 0; + PST_TP_DEV p_tp_dev = NULL; + u16 node_num = 0; + u8 key_num = 0; + PST_SUB_TEST_ITEM_ID_SET p_sub_id_set = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + open_test_res = p_raw_test_res->open_test_result; + p_tp_dev = p_test_item->p_tp_dev; + node_num = p_tp_dev->sc_sen_num * p_tp_dev->sc_drv_num; + key_num = p_tp_dev->key_num; + p_sub_id_set = p_raw_test_res->item_res_header.p_sub_id_set; + + modify_test_result(open_test_res); + board_print_info("\n---Show open test result!---\n"); + if ((p_raw_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] != RAWDATA_TEST_FAIL) && + (p_raw_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] != RAWDATA_TEST_SUCCESSFULLY)) { + board_print_info("OPEN TEST ABORTED: OPEN TEST ERROR!\n"); + return 1; + } + if (p_sub_id_set->len == 0) { + board_print_info("RAWDATA TEST PASS!\n"); + } + + for (i = 0; i < p_sub_id_set->len; i++) { + switch (p_sub_id_set->p_id_set[i]) { + case TP_RAWDATA_MAX_TEST_ITEM_ID: { + if ((open_test_res & BEYOND_RAWDATA_UPPER_LIMIT) != 0) { + board_print_info( + "BEYOND RAWDATA UPPER LIMIT!\n"); + /*print_beyond_limit_node(p_raw_test_res->p_beyond_rawdata_upper_limit_cnt,node_num);*/ + } else { + board_print_info( + "RAWDATA UPPER LIMIT TEST PASS!\n"); + } + break; + } + case TP_RAWDATA_MIN_TEST_ITEM_ID: { + if ((open_test_res & BEYOND_RAWDATA_LOWER_LIMIT) != 0) { + board_print_info( + "BEYOND RAWDATA LOWER LIMIT!\n"); + /*print_beyond_limit_node(p_raw_test_res->p_beyond_rawdata_lower_limit_cnt,node_num);*/ + } else { + board_print_info( + "RAWDATA LOWER LIMIT TEST PASS!\n"); + } + break; + } + case TP_KEYDATA_MAX_TEST_ITEM_ID: { + if ((open_test_res & KEY_BEYOND_UPPER_LIMIT) != 0) { + board_print_info("KEY BEYOND UPPER LIMIT!\n"); + /*print_beyond_limit_node(p_raw_test_res->p_beyond_key_upper_limit_cnt,key_num);*/ + } else { + board_print_info( + "KEYDATA UPPER LIMIT TEST PASS!\n"); + } + break; + } + case TP_KEYDATA_MIN_TEST_ITEM_ID: { + if ((open_test_res & KEY_BEYOND_LOWER_LIMIT) != 0) { + board_print_info("KEY BEYOND LOWER LIMIT!\n"); + /*print_beyond_limit_node(p_raw_test_res->p_beyond_key_lower_limit_cnt,key_num);*/ + } else { + board_print_info( + "KEYDATA LOWER LIMIT TEST PASS!\n"); + } + break; + } + case TP_OFFSET_TEST_ITEM_ID: { + if ((open_test_res & BEYOND_OFFSET_LIMIT) != 0) { + board_print_info("BEYOND OFFSET LIMIT!\n"); + /*print_beyond_limit_node(p_raw_test_res->p_beyond_offset_limit_cnt,node_num);*/ + } else { + board_print_info("OFFSET TEST PASS!\n"); + } + break; + } + case TP_RAWDATA_JITTER_TEST_ITEM_ID: { + if ((open_test_res & BEYOND_JITTER_LIMIT) != 0) { + board_print_info("BEYOND JITTER LIMIT!\n"); + /*rint_beyond_limit_node(p_raw_test_res->p_beyond_jitter_limit_cnt,node_num);*/ + } else { + board_print_info("JITTER TEST PASS!\n"); + } + break; + } + case TP_ACCORD_TEST_ITEM_ID: { + if ((open_test_res & BEYOND_ACCORD_LIMIT) != 0) { + board_print_info("BEYOND ACCORD LIMIT!\n"); + /*print_beyond_limit_node(p_raw_test_res->p_beyond_accord_limit_cnt,node_num);*/ + } else { + board_print_info("ACCORD TEST PASS!\n"); + } + break; + } + case TP_UNIFORMITY_TEST_ITEM_ID: { + if ((open_test_res & BEYOND_UNIFORMITY_LIMIT) != 0) { + board_print_info("BEYOND UNIFORMITY LIMIT!\n"); + /*print_beyond_limit_node(p_raw_test_res->p_beyond_jitter_limit_cnt,node_num);*/ + } else { + board_print_info("UNIFORMITY TEST PASS!\n"); + } + break; + } + default: + break; + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : print_short_test_res +* Description : print short test result +* Input : ptr32 p_data(You must cast it to type PST_TEST_ORDER ) +* Output : +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 print_short_test_res(ptr32 p_data) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_ITEM p_test_item = NULL; + PST_SHORT_TEST_RES p_short_res = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_short_res = (PST_SHORT_TEST_RES)p_test_item->test_res.ptr_res; + board_print_info("\n---show short test result!---\n"); + modify_test_result(p_short_res->item_res_header.test_item_err_code + .ptr_err_code_set[0]); + if ((p_short_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] != SHORT_TEST_NONE_ERROR) && + (p_short_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] != SHORT_TEST_EXIST_SHORT)) { + board_print_info("SHORT TEST ABORTED:SHORT TEST ERROR!\n"); + return 1; + } + + if (p_short_res->short_num > 0) { + board_print_info("SHORT TEST FAILD!\n"); + for (i = 0; i < p_short_res->short_num; i++) { + if (p_short_res->short_mess_arr[4 * i + 0] == + CHANNEL_GND) { + board_print_info("GND and "); + } else if (p_short_res->short_mess_arr[4 * i + 0] == + CHANNEL_VDD) { + board_print_info("VDD and "); + } else { + if (p_short_res->short_mess_arr[4 * i + 0] & + 0x80) { + board_print_info( + "drv-%d and ", + p_short_res->short_mess_arr + [4 * i + 0] & + 0x7f); + } else { + board_print_info( + "sen-%d and ", + p_short_res->short_mess_arr + [4 * i + 0] & + 0x7f); + } + } + + if (p_short_res->short_mess_arr[4 * i + 1] == + CHANNEL_GND) { + board_print_info("GND short,"); + } else if (p_short_res->short_mess_arr[4 * i + 1] == + CHANNEL_VDD) { + board_print_info("VDD short,"); + } else { + if (p_short_res->short_mess_arr[4 * i + 1] & + 0x80) { + board_print_info( + "drv-%d short,", + p_short_res->short_mess_arr + [4 * i + 1] & + 0x7f); + } else { + board_print_info( + "sen-%d short,", + p_short_res->short_mess_arr + [4 * i + 1] & + 0x7f); + } + } + board_print_info( + "short r=%d Kohm\n", + (((p_short_res->short_mess_arr[4 * i + 2] << 8) + + p_short_res->short_mess_arr[4 * i + 3])) / + 10); + } + } else { + board_print_info("SHORT TEST PASS!\n"); + } + return ret; +} + +/******************************************************************************* +* Function Name : print_version_test_res +* Description : print version test result +* Input : ptr32 p_data(You must cast it to type PST_TEST_ORDER ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 print_version_test_res(ptr32 p_data) +{ + s32 ret = 1; + + PST_TEST_ITEM p_test_item = NULL; + PST_VERSION_TEST_RES p_ver_test_res = NULL; + PST_VERSION_PARAM p_ver_param = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_ver_test_res = (PST_VERSION_TEST_RES)p_test_item->test_res.ptr_res; + p_ver_param = (PST_VERSION_PARAM)p_test_item->param.ptr_param; + board_print_info("\n---Show fw version test result!---\n"); + + modify_test_result(p_ver_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0]); + if (p_ver_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] == VERSION_TEST_NONE_ERROR) { + board_print_info("FW VERSION TEST PASS!\n"); + } else { + board_print_info("VERSION TEST FAILD!\n"); + } + return ret; +} + +/******************************************************************************* +* Function Name : print_flash_test_res +* Description : print flash test result +* Input : ptr32 p_data(You must cast it to type PST_TEST_ORDER ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 print_flash_test_res(ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = NULL; + PST_FLASH_TEST_RES p_flash_test_res = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_flash_test_res = (PST_FLASH_TEST_RES)p_test_item->test_res.ptr_res; + board_print_info("\n---Show flash test result!---\n"); + + modify_test_result(p_flash_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0]); + if (p_flash_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] == FLASH_TEST_ERROR_CODE_NONE) { + board_print_info("FLASH TEST PASS!\n"); + } else { + board_print_info("FLASH TEST FAILD!\n"); + } + return ret; +} + +/******************************************************************************* +* Function Name : print_send_cfg_test_res +* Description : print send config test result +* Input : ptr32 p_data(You must cast it to type PST_TEST_ORDER ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 print_send_cfg_test_res(ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = NULL; + PST_CHIP_CONFIG_PROC_RES p_send_cfg_test_res = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_send_cfg_test_res = + (PST_CHIP_CONFIG_PROC_RES)p_test_item->test_res.ptr_res; + board_print_info("\n---Show send config test result!---\n"); + modify_test_result(p_send_cfg_test_res->item_res_header + .test_item_err_code.ptr_err_code_set[0]); + if (p_send_cfg_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] == CFG_CHECK_TEST_NONE_ERROR) { + board_print_info("SEND CONFIG TEST PASS!\n"); + } else { + board_print_info("SEND CONFIG FAILD!\n"); + } + return ret; +} + +/******************************************************************************* +* Function Name : print_cfg_recover_test_res +* Description : print config recover test result +* Input : ptr32 p_data(You must cast it to type PST_TEST_ORDER ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 print_cfg_recover_test_res(ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = NULL; + PST_RECOVER_CHIP_CFG_RES p_cfg_recover_test_res = NULL; + p_test_item = (PST_TEST_ITEM)p_data; + p_cfg_recover_test_res = + (PST_RECOVER_CHIP_CFG_RES)p_test_item->test_res.ptr_res; + board_print_info("\n---Show cfg recover test result!---\n"); + + modify_test_result(p_cfg_recover_test_res->item_res_header + .test_item_err_code.ptr_err_code_set[0]); + if (p_cfg_recover_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] == RECOVER_CFG_ERROR_CODE_NONE) { + board_print_info("CONFIG RECOVER TEST PASS!\n"); + } else { + board_print_info("CONFIG RECOVER FAILD!\n"); + } + return ret; +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.h new file mode 100644 index 000000000000..add6f3571ff6 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/save_test_data.h @@ -0,0 +1,43 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : save_test_data.h +* Author : +* Version : V1.0.0 +* Date : 28/03/2018 +* Description : save test data +*******************************************************************************/ +#ifndef SAVE_TEST_DATA_H +#define SAVE_TEST_DATA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "mxml.h" +#include "config.h" + +#define GT_SHORT 0x00400000 +#define VERSION_ERR 0x10000 +#define BEYOND_FLASH_LAYER_LIMIT 0x01000000 +#define SEND_CONFIG_ERR 0x00100000 +#define RECOVER_CONFIG_ERR 0x00200000 +#define TEST_ABORT 0x00000100 + +/***********************************print test data**************************************/ +extern s32 print_rawdata_test_res(ptr32 p_data); +/*print short test result*/ +extern s32 print_short_test_res(ptr32 p_data); +/*print version test result*/ +extern s32 print_version_test_res(ptr32 p_data); +/*print flash test result*/ +extern s32 print_flash_test_res(ptr32 p_data); +/*print send config test result*/ +extern s32 print_send_cfg_test_res(ptr32 p_data); +/*print cfg recover test result*/ +extern s32 print_cfg_recover_test_res(ptr32 p_data); +/**********************************print test data end**********************************/ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager.h new file mode 100644 index 000000000000..c85f3b40b4fa --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager.h @@ -0,0 +1,33 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : simple_mem_manager.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 08/23/2017 +* Description : we use this module manger memory pool +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef SIMPLE_MEM_MANAGER_H +#define SIMPLE_MEM_MANAGER_H + +#include "user_test_type_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**********************memory manger in stack*******************************/ +extern s32 alloc_mem_block(void **pp_buf, u16 buf_size); +extern s32 free_mem_block(void *p_buf); + +/**********************memory manger in heap*******************************/ +extern s32 alloc_mem_in_heap(void **pp_param, u32 data_size); +extern s32 free_mem_in_heap(void *p_param); + +extern s32 free_mem_in_heap_p(void **pp_param); + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager_mach.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager_mach.c new file mode 100644 index 000000000000..5300b07c57f6 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/simple_mem_manager_mach.c @@ -0,0 +1,105 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : simple_mem_manager_mach.cpp +* Author : +* Version : V1.0.0 +* Date : 05/14/2018 +* Description : we use this module manager memory,or support dynamic memory +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "simple_mem_manager.h" +#include "board_opr_interface.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* Function Name : alloc_mem_block +* Description : allocate memory block +* Input : void** pp_buf(pointer to buffer pointer) + : u16 buf_size (no more than 8K) +* Output : void** pp_buf +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 alloc_mem_block(IN_OUT void **pp_buf, IN u16 buf_size) +{ + s32 ret = 0; + (*pp_buf) = (void *)malloc(buf_size * sizeof(u8)); + if (NULL != (*pp_buf)) { + ret = 1; + } + return ret; +} + +/******************************************************************************* +* Function Name : free_mem_block +* Description : free memory block +* Input : void* p_buf +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 free_mem_block(IN void *p_buf) +{ + s32 ret = 0; + if (p_buf != NULL) { + ret = free_mem_in_heap(p_buf); + } + return ret; +} + +/******************************************************************************* +* Function Name : alloc_mem_in_heap +* Description : alloc memory in heap +* Input : void** pp_param(pointer to buffer pointer) + : u32 data_size +* Output : void** pp_param +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 alloc_mem_in_heap(IN_OUT void **pp_param, IN u32 data_size) +{ + s32 ret = 0; + (*pp_param) = (void *)malloc(data_size * sizeof(u8)); + if (NULL != (*pp_param)) { + ret = 1; + } + + return ret; +} + +/******************************************************************************* +* Function Name : free_mem_in_heap +* Description : free memory in heap +* Input : void* p_param(buffer pointer) +* Output : void* p_param +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 free_mem_in_heap(IN void *p_param) +{ + if (p_param != NULL) { + free(p_param); + p_param = NULL; + } + return 1; +} +/******************************************************************************* +* Function Name : free_mem_in_heap_p +* Description : free memory in heap +* Input : void** pp_param(pointer to buffer pointer) +* Output : void** pp_param +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 free_mem_in_heap_p(IN_OUT void **pp_param) +{ + if (*pp_param != NULL) { + free(*pp_param); + *pp_param = NULL; + } + return 1; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/strtol.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/strtol.c new file mode 100644 index 000000000000..3a97167cfbe2 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/strtol.c @@ -0,0 +1,58 @@ +#define LONG_MAX 2147483647L /*0x7FFFFFFF */ +#define LONG_MIN (-2147483647L - 1L) /*-0x80000000*/ + +int strtol(const char *nptr, char **endptr, int base) +{ + const char *p = nptr; + unsigned long ret; + int ch; + unsigned long Overflow; + int sign = 0, flag, LimitRemainder; + /*delete space*/ + do { + ch = *p++; + } while (isspace(ch)); + if (ch == '-') { + sign = 1; + ch = *p++; + } else if (ch == '+') + ch = *p++; + if ((base == 0 || base == 16) && ch == '0' && + (*p == 'x' || *p == 'X')) { + ch = p[1]; + p += 2; + base = 16; + } + if (base == 0) + base = ch == '0' ? 8 : 10; + Overflow = sign ? -(unsigned long)LONG_MIN : LONG_MAX; + LimitRemainder = Overflow % (unsigned long)base; + Overflow /= (unsigned long)base; + for (ret = 0, flag = 0;; ch = *p++) { + /*get target value*/ + if (isdigit(ch)) + ch -= '0'; + else if (isalpha(ch)) + ch -= isupper(ch) ? 'A' - 10 : 'a' - 10; + else + break; + if (ch >= base) + break; + /*overflow*/ + if (flag < 0 || ret > Overflow || + (ret == Overflow && ch > LimitRemainder)) + flag = -1; + else { + flag = 1; + ret *= base; + ret += ch; + } + } + if (flag < 0) + ret = sign ? LONG_MIN : LONG_MAX; + else if (sign) + ret = -ret; + if (endptr != 0) + *endptr = (char *)(flag ? (p - 1) : nptr); + return ret; +} diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_def.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_def.h new file mode 100644 index 000000000000..43cbccac9ffc --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_def.h @@ -0,0 +1,180 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : test_item_def.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : define test item id or test item error code or struct +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TEST_ITEM_DEF_H +#define TEST_ITEM_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "tp_test_item_id.h" +#include "tp_dev_def.h" + +/*test item callback function pointer define*/ +typedef s32 (*TEST_CALLBACK_PTR)(ptr32); + +/*test item callback function pointer define*/ +typedef TEST_CALLBACK_PTR TEST_ITEM_FUNC_PTR; + +/*sub test item id set*/ +typedef struct SUB_TEST_ITEM_ID_SET { + u8 len; + u8 *p_id_set; +} ST_SUB_TEST_ITEM_ID_SET, *PST_SUB_TEST_ITEM_ID_SET; + +/*test item define*/ +typedef struct TEST_ITEM { + /*test item id*/ + u16 test_item_id; + + /*sub test item id set*/ + PST_SUB_TEST_ITEM_ID_SET p_sub_id_set; + + /*touch panel device*/ + PST_TP_DEV p_tp_dev; + + /*we use this variable optimal + //(1)In arm test board platform,this variable store starting address of test item parameter in flash + //(2)In other platform ,this variable store pointer of test item parameter,now it is not used + */ + union { + u32 item_addr_u32; + ptr32 item_addr_ptr; + } item_addr_start; + + /*current data*/ + union { + u32 n_cur_data; /*interger data*/ + ptr32 ptr_cur_data; /*pointer data*/ + } cur_data; + + /*you can use this for parameter limit or other infomation*/ + union { + u32 n_param; /*interger data*/ + ptr32 ptr_param; /*pointer data*/ + } param; + + /*test callback function*/ + TEST_ITEM_FUNC_PTR ptr_general_func; + ptr32 ptr_general_func_param; + + /*this function may use p_tp_dev to decide some branch + //the return value 1 means ok,0 means fail + //the parameter of function is 'TEST_ITEM' + */ + TEST_ITEM_FUNC_PTR ptr_test_func; + + /*this function is used to do some word for preparing testing,such as + //(1)set some hardware + //(2)get test parameter pointer + //(3)notify test starting + //the return value 1 means ok,0 means fail + */ + TEST_ITEM_FUNC_PTR ptr_test_item_before_func; + ptr32 ptr_test_item_before_func_param; + + /*this function is used to do some word for finish testing,such as + //(1)recover some hardware + //(2)notify function + //(3)save test result + //(4)notify test finished + //the return value 1 means ok,0 means fail + */ + TEST_ITEM_FUNC_PTR ptr_test_item_finished_func; + ptr32 ptr_test_item_finished_func_param; + + /*test result*/ + union { + u32 n_res; /*integer data*/ + ptr32 ptr_res; /*pointer data*/ + } test_res; + + /*shared data,you can use this data to communicate with other module*/ + ptr32 ptr_share_data; + + /*this pointer to ST_TEST_PROC_DATA*/ + ptr32 ptr_test_proc_data; + + /*this pointer point special struct which contains special callback function + //you must cast this pointer to you declared struct + */ + ptr32 ptr_special_callback_data; + +} ST_TEST_ITEM, *PST_TEST_ITEM; + +/*test result enum define */ +typedef enum TEST_RESULT { + TEST_OK = 0x00, + TEST_NG = 0x01, + TEST_WARNING = 0x02 +} ENUM_TEST_RESULT; + +/*test status define*/ +typedef enum TEST_STATUS { + TEST_NOT_START = 0x00, + TEST_START = 0x01, + TEST_DOING = 0x02, + TEST_FINISH = 0x03, + TEST_ABORTED = 0x04, + TEST_START_PRE = 0x05, +} ENUM_TEST_STATUS; + +/*test item error code set*/ +typedef struct TEST_ITEM_ERR_CODE_SET { + u8 item_num; + u16 *p_item_arr; +} ST_TEST_ITEM_ERR_CODE_SET, *PST_TEST_ITEM_ERR_CODE_SET; + +typedef struct ITEM_ERR_CODE { + u16 len; + u16 *ptr_err_code_set; +} ST_ITEM_ERR_CODE, *PST_ST_ITEM_ERR_CODE; + +/*test item result define*/ +typedef struct TEST_ITEM_RES { + /*test ietm id */ + u16 test_id; + + /*test progress*/ + u16 test_progress; + + /*sub test item id set*/ + PST_SUB_TEST_ITEM_ID_SET p_sub_id_set; + + ENUM_TEST_RESULT test_result; + ENUM_TEST_STATUS test_status; + + ST_ITEM_ERR_CODE test_item_err_code; + +} ST_TEST_ITEM_RES, *P_TEST_ITEM_RES; + +/*test process data*/ +typedef struct TEST_PROC_DATA { + u16 test_item_num; + ENUM_TEST_STATUS test_proc_status; + u8 test_break_flag; + + PST_TP_DEV p_dev; /*touc pannel device pointer*/ + + PST_TEST_ITEM *pp_test_item_arr; + + TEST_CALLBACK_PTR p_test_items_before_func_ptr; + ptr32 p_test_items_before_func_ptr_param; + TEST_CALLBACK_PTR p_test_items_finished_func_ptr; + ptr32 p_test_items_finished_func_ptr_param; +} ST_TEST_PROC_DATA, *PST_TEST_PROC_DATA; +typedef const ST_TEST_PROC_DATA CST_TEST_PROC_DATA; +typedef const PST_TEST_PROC_DATA CPST_TEST_PROC_DATA; + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.c new file mode 100644 index 000000000000..6f3907634031 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.c @@ -0,0 +1,705 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : test_item_init.h +* Author : Zhitao Yang +* Version : V1.0.0 +* Date : 28/03/2018 +* Description : initial test item +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "test_item_init.h" + +#include "tp_dev_control.h" +#include "tp_open_test.h" +#include "tp_short_test.h" +#include "tp_version_test.h" +#include "tp_additional_option.h" +#include "tp_test_item_mem.h" +#include "simple_mem_manager.h" +#include "save_test_data.h" + +/******************************************************************************* +* Function Name : free_item_param +* Description : +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : void +*******************************************************************************/ +extern void free_item_param(PST_TEST_ITEM p_test_item) +{ + if (p_test_item->p_sub_id_set != NULL) { + p_test_item->p_sub_id_set->p_id_set = NULL; + } + p_test_item->p_sub_id_set = NULL; + p_test_item->p_tp_dev = NULL; + p_test_item->item_addr_start.item_addr_ptr = NULL; + p_test_item->ptr_general_func = NULL; + p_test_item->ptr_general_func_param = NULL; + p_test_item->ptr_test_func = NULL; + p_test_item->ptr_test_item_before_func = NULL; + p_test_item->ptr_test_item_before_func_param = NULL; + p_test_item->ptr_test_item_finished_func = NULL; + p_test_item->ptr_test_item_finished_func_param = NULL; + p_test_item->ptr_share_data = NULL; + p_test_item->ptr_test_proc_data = NULL; + if (p_test_item->ptr_special_callback_data != NULL) { + free_mem_in_heap(p_test_item->ptr_special_callback_data); + p_test_item->ptr_special_callback_data = NULL; + } +} + +/*-------------------------------init open test item---------------------------------------*/ + +/******************************************************************************* +* Function Name : rawdata_test_before_func +* Description : set some hardware and init rawdata test param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 rawdata_test_before_func(ptr32 p_data, ptr32 p_param) +{ + s32 ret = 0; + PST_TEST_ITEM p_test_item = NULL; + PST_CUR_RAWDATA p_cur_data = NULL; + PST_TEST_PARAM p_test_param = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_test_item->test_res.ptr_res = NULL; + p_test_param = (PST_TEST_PARAM)p_param; + /*init raw param*/ + p_test_item->param.ptr_param = p_test_param->p_raw_test_param; + + /* get rawdata test result buf*/ + ret = alloc_rawdata_test_item_res(p_test_item); + if (ret == 0) { + board_print_error("get raw test result error!\n"); + return 0; + } + p_cur_data = (PST_CUR_RAWDATA)p_test_item->cur_data.ptr_cur_data; + board_print_debug("rawdata buf len :%d!\n", p_cur_data->data_len); + return ret; +} + +/******************************************************************************* +* Function Name : release_rawdata_test_item +* Description : release test param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 release_rawdata_test_item(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_test_item->param.ptr_param = NULL; + /*release rawdata test res*/ + ret = free_rawdata_test_item_res(p_test_item); + free_item_param(p_test_item); + return ret; +} + +/*-------------------------------init short test item---------------------------------------*/ + +/******************************************************************************* +* Function Name : get_gt900_short_param +* Description : gt900 short test res mem malloc +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) + : PST_TEST_PARAM p_test_param +* Output : none +* Return : s32(0:have not handled 1:handled) +*******************************************************************************/ +static s32 get_gt900_short_param(IN_OUT PST_TEST_ITEM p_test_item, + PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + p_test_item->param.ptr_param = p_test_param->p_short_param; + return ret; +} + +/******************************************************************************* +* Function Name : get_phoenix_test_param +* Description : phoenix short test res mem malloc +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:have not handled 1:handled) +*******************************************************************************/ +static s32 get_phoenix_test_param(IN_OUT PST_TEST_ITEM p_test_item, + PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + u16 i = 0; + u16 j = 0; + u16 chk_sum = 0; + PST_SHORT_PARAM p_short_param = NULL; + PST_TP_DEV p_tp_dev = NULL; + u16 param_addr = 0x8118; + u16 len = 0x81FE - 0x8118; + u8 *opt_param = NULL; + + p_short_param = p_test_param->p_short_param; + p_tp_dev = p_test_item->p_tp_dev; + p_short_param->short_opt.len = len + 5; + if (alloc_mem_in_heap((void **)&p_short_param->short_opt.opt.opt_ptr, + p_short_param->short_opt.len) == 0) { + board_print_error("short testopt param malloc momory error!\n"); + return 0; + } + memset(p_short_param->short_opt.opt.opt_ptr, 0, len + 3); + opt_param = p_short_param->short_opt.opt.opt_ptr; + /*param len*/ + opt_param[i++] = len + 2; + /*param addr*/ + opt_param[i++] = (param_addr & 0xff); + opt_param[i++] = (param_addr >> 8) & 0xff; + /*sen/drv line*/ + for (j = 0; j < p_tp_dev->max_sen_num_in_die; j++) { + if (j > p_tp_dev->max_sen_num) { + opt_param[i++] = 0xFF; + } else { + opt_param[i++] = p_tp_dev->sen_map[j]; + } + } + for (j = 0; j < p_tp_dev->max_drv_num_in_die; j++) { + if (j > p_tp_dev->max_drv_num) { + opt_param[i++] = 0xFF; + } else { + opt_param[i++] = p_tp_dev->drv_map[j]; + } + } + /* 4 bytes reseverd -> 2 bytes reseved add 2 bytes for driver,so driver max number is 46*/ + opt_param[i++] = 0x00; + opt_param[i++] = 0x00; + + /*Short Check Max num ≤100*/ + opt_param[i++] = 100; + /* + ShortCheck + Mode Sensor Line + Rx的线åºé€‰æ‹©ï¼š0~3å…±4ç§æ¨¡å¼ï¼› + PINè„šå·ï¼šS0~121ï¼› + 0：S0~75ï¼›1：S46~121ï¼›2：S22~97ï¼› + 3：S0~37&S84~121。 + æ ¹æ®äº§å“é…置自动获å–，并上传到此寄存器。 + */ + /*p_test_param->mode_sen_line = (p_test_param->test_cfg[0x80AC-p_tp_dev->cfg_start_addr]>>5) & 0x03;*/ + opt_param[i++] = p_test_param->mode_sen_line; + + /*Tx&Tx short resistor threshold*/ + opt_param[i++] = + ((p_short_param->short_threshold.drv_drv_resistor_threshold) & + 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.drv_drv_resistor_threshold >> + 8) & + 0xFF); + /*Tx&Rx short resistor threshold*/ + opt_param[i++] = + ((p_short_param->short_threshold.drv_sen_resistor_threshold) & + 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.drv_sen_resistor_threshold >> + 8) & + 0xFF); + /*Rx&Rx short resistor threshold*/ + opt_param[i++] = + ((p_short_param->short_threshold.sen_sen_resistor_threshold) & + 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.sen_sen_resistor_threshold >> + 8) & + 0xFF); + /*adc read delay*/ + opt_param[i++] = + ((p_short_param->short_threshold.adc_read_delay) & 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.adc_read_delay >> 8) & 0xFF); + /*Tx&GND short resistor threshold*/ + opt_param[i++] = ((p_short_param->short_threshold + .drv_gnd_vdd_resistor_threshold) & + 0xFF); + opt_param[i++] = ((p_short_param->short_threshold + .drv_gnd_vdd_resistor_threshold >> + 8) & + 0xFF); + /*Tx&VDD short resistor threshold*/ + opt_param[i++] = ((p_short_param->short_threshold + .drv_gnd_vdd_resistor_threshold) & + 0xFF); + opt_param[i++] = ((p_short_param->short_threshold + .drv_gnd_vdd_resistor_threshold >> + 8) & + 0xFF); + /*Rx&GND short resistor threshold*/ + opt_param[i++] = ((p_short_param->short_threshold + .sen_gnd_vdd_resistor_threshold) & + 0xFF); + opt_param[i++] = ((p_short_param->short_threshold + .sen_gnd_vdd_resistor_threshold >> + 8) & + 0xFF); + /*Rx&VDD short resistor threshold*/ + opt_param[i++] = ((p_short_param->short_threshold + .sen_gnd_vdd_resistor_threshold) & + 0xFF); + opt_param[i++] = ((p_short_param->short_threshold + .sen_gnd_vdd_resistor_threshold >> + 8) & + 0xFF); + /*第一段ADCæ•°æ®åŒºé—´èµ·å§‹æ—¶é—´ï¼Œå•ä½ï¼š0.5us；建议>=200。(暂未使用)*/ + opt_param[i++] = 0x00; + opt_param[i++] = 0x00; + /*第二段ADCæ•°æ®åŒºé—´èµ·å§‹æ—¶é—´ï¼Œå•ä½ï¼š0.5us；建议>=1000。(暂未使用)*/ + opt_param[i++] = 0x00; + opt_param[i++] = 0x00; + /*ADC Samping Time，å•ä½ï¼šHz，建议：<=1700Hz（采样时间约588us），ä¸èƒ½ä½ŽäºŽç¬¬äºŒæ®µADC区间起始时间。(暂未使用)*/ + opt_param[i++] = 0x00; + opt_param[i++] = 0x00; + /*Tx&Tx Rx&Rx Tx&Rx short adc threshold*/ + opt_param[i++] = + ((p_short_param->short_threshold.gt_short_threshold) & 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.gt_short_threshold >> 8) & + 0xFF); + /*diffcode threshold*/ + opt_param[i++] = + ((p_short_param->short_threshold.diffcode_short_threshold) & + 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.diffcode_short_threshold >> + 8) & + 0xFF); + /*Tx与Tx短路æ¢ç®—系数，范围40~500*/ + opt_param[i++] = ((p_short_param->short_threshold.tx_tx_factor) & 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.tx_tx_factor >> 8) & 0xFF); + /*Tx与Rx短路æ¢ç®—系数，范围40~500*/ + opt_param[i++] = ((p_short_param->short_threshold.tx_rx_factor) & 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.tx_rx_factor >> 8) & 0xFF); + /*Rx与Rx短路æ¢ç®—系数，范围40~500*/ + opt_param[i++] = ((p_short_param->short_threshold.rx_rx_factor) & 0xFF); + opt_param[i++] = + ((p_short_param->short_threshold.rx_rx_factor >> 8) & 0xFF); + /*reserved*/ + opt_param[i++] = 0x00; + opt_param[i++] = 0x00; + + for (j = 3; j < len + 3; j += 2) { + chk_sum += ((u16)(opt_param[j + 1] << 8) + opt_param[j]); + } + chk_sum = 0 - chk_sum; + opt_param[len + 3] = ((chk_sum) & 0xFF); + opt_param[len + 4] = ((chk_sum >> 8) & 0xFF); + opt_param[0] = len + 2; + p_short_param->short_opt.len = len + 5; + board_print_debug("short test opt param len:%d\n", len + 2); + + p_test_item->param.ptr_param = p_short_param; + + return ret; +} + +/******************************************************************************* +* Function Name : get_short_param +* Description : get short param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 get_short_param(IN_OUT PST_TEST_ITEM p_test_item, + PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + switch (p_test_item->p_tp_dev->chip_type) { + case TP_NANJING: + case TP_PHOENIX: { + ret = get_phoenix_test_param(p_test_item, p_test_param); + } break; + default: { + ret = get_gt900_short_param(p_test_item, p_test_param); + } break; + } + return ret; +} + +/******************************************************************************* +* Function Name : short_test_before_func +* Description : set some hardware and init short param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 short_test_before_func(ptr32 p_data, ptr32 p_param) +{ + s32 ret = 0; + PST_TEST_ITEM p_test_item = NULL; + PST_TEST_PARAM p_test_param = NULL; + p_test_item = (PST_TEST_ITEM)p_data; + p_test_item->test_res.ptr_res = NULL; + p_test_param = (PST_TEST_PARAM)p_param; + + /*init short param*/ + ret = get_short_param(p_test_item, p_test_param); + if (ret == 0) { + board_print_error("get short param error!\n"); + return ret; + } + + ret = alloc_short_test_item_res(p_test_item); + if (ret == 0) { + board_print_error("get short res buf error!\n"); + return ret; + } + return ret; +} + +/******************************************************************************* +* Function Name : release_short_test_item +* Description : release memory function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:have not handled 1:handled) +*******************************************************************************/ +extern s32 release_short_test_item(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = NULL; + PST_SHORT_PARAM p_short_param = NULL; + p_test_item = (PST_TEST_ITEM)p_data; + p_short_param = (PST_SHORT_PARAM)p_test_item->param.ptr_param; + + if (p_short_param != NULL) { + p_short_param->short_bin.update_bin_addr.bin_ptr = NULL; + if (p_short_param->short_opt.opt.opt_ptr != NULL) { + free_mem_in_heap(p_short_param->short_opt.opt.opt_ptr); + p_short_param->short_opt.opt.opt_ptr = NULL; + } + p_short_param = NULL; + } + /*release short test result*/ + ret = free_short_test_item_res(p_test_item); + free_item_param(p_test_item); + return ret; +} + +/*-------------------------------init version test item---------------------------------------*/ + +/******************************************************************************* +* Function Name : version_test_before_func +* Description : set some hardware and init version test param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) + : ptr32 p_param +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 version_test_before_func(ptr32 p_data, ptr32 p_param) +{ + s32 ret = 0; + PST_TEST_ITEM p_test_item = NULL; + PST_TEST_PARAM p_test_param = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_test_param = (PST_TEST_PARAM)p_param; + p_test_item->test_res.ptr_res = NULL; + /*init version param*/ + p_test_item->param.ptr_param = p_test_param->p_version_test_param; + /* get version test result buf*/ + ret = alloc_version_test_item_res(p_test_item); + if (ret == 0) { + board_print_error("get version test result error!\n"); + return 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : version_test_finished_func +* Description : release test param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 version_test_finished_func(ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = NULL; + p_test_item = (PST_TEST_ITEM)p_data; + p_test_item->param.ptr_param = NULL; + /*release version test res*/ + ret = free_version_test_item_res(p_test_item); + free_item_param(p_test_item); + return ret; +} + +/*-------------------------------init flash test item---------------------------------------*/ + +/******************************************************************************* +* Function Name : flash_test_before_func +* Description : set some hardware and init flash param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) + : ptr32 p_param +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 flash_test_before_func(ptr32 p_data, ptr32 p_param) +{ + s32 ret = 0; + PST_TEST_ITEM p_test_item = NULL; + PST_TEST_PARAM p_test_param = NULL; + PST_FLASH_TEST_PARAM p_flash_param = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_test_param = (PST_TEST_PARAM)p_param; + p_test_item->test_res.ptr_res = NULL; + + /*init falsh param*/ + p_flash_param = p_test_param->p_flash_test_param; + p_flash_param->config_arr = p_test_param->test_cfg; + p_flash_param->cfg_len = p_test_param->cfg_len; + p_test_item->param.ptr_param = p_flash_param; + + /* get flash test result buf*/ + ret = alloc_flash_test_item_res(p_test_item); + if (ret == 0) { + board_print_error("get flash test result error!\n"); + return 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : release_flash_test_item +* Description : release test param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 release_flash_test_item(ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = NULL; + PST_FLASH_TEST_PARAM p_flash_param = NULL; + p_test_item = (PST_TEST_ITEM)p_data; + p_flash_param = (PST_FLASH_TEST_PARAM)p_test_item->param.ptr_param; + if (p_test_item->param.ptr_param != NULL) { + p_flash_param->config_arr = NULL; + p_test_item->param.ptr_param = NULL; + } + /*release flash test res*/ + ret = free_flash_test_item_res(p_test_item); + free_item_param(p_test_item); + return ret; +} + +/*-------------------------------init send config test item---------------------------------------*/ + +/******************************************************************************* +* Function Name : send_cfg_test_before_func +* Description : set some hardware and init send config param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) + : ptr32 p_param +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 send_cfg_test_before_func(ptr32 p_data, ptr32 p_param) +{ + s32 ret = 0; + PST_TEST_ITEM p_test_item = NULL; + PST_TEST_PARAM p_test_param = NULL; + p_test_item = (PST_TEST_ITEM)p_data; + p_test_item->test_res.ptr_res = NULL; + + p_test_param = (PST_TEST_PARAM)p_param; + p_test_item->test_res.ptr_res = NULL; + + ret = get_send_cfg_param_mess(p_test_item, p_test_param); + if (ret == 0) { + board_print_error("get send config param error!\n"); + return 0; + } + + /*get send config test result buf*/ + ret = alloc_chip_cfg_proc_item_res(p_test_item); + if (ret == 0) { + board_print_error("get send config test result error!\n"); + return 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : get_send_cfg_param_mess +* Description : get send cfg param +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 get_send_cfg_param_mess(PST_TEST_ITEM p_test_item, + PST_TEST_PARAM p_test_param) +{ + s32 ret = 0; + PST_CHIP_CONFIG_PROC_PARAM p_send_cfg_param = NULL; + + ret = alloc_mem_in_heap((void **)&p_send_cfg_param, + sizeof(ST_CHIP_CONFIG_PROC_PARAM)); + if (ret == 0) { + board_print_error("send config param alloc memory error!\n"); + return 0; + } + + p_send_cfg_param->config = p_test_param->test_cfg; + p_send_cfg_param->cfg_len = p_test_param->cfg_len; + p_send_cfg_param->option = p_test_param->send_cfg_option; + p_test_item->param.ptr_param = p_send_cfg_param; + return ret; +} + +/******************************************************************************* +* Function Name : release_cfg_test_item +* Description : release test param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 release_cfg_test_item(ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + + /*release send config test param*/ + ret = release_send_cfg_param(p_test_item); + /*release send config test res*/ + ret = free_chip_cfg_proc_item_res(p_test_item); + free_item_param(p_test_item); + return ret; +} + +/******************************************************************************* +* Function Name : release_send_cfg_param +* Description : release send config param +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_send_cfg_param(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_CHIP_CONFIG_PROC_PARAM p_send_cfg_param = NULL; + p_send_cfg_param = + (PST_CHIP_CONFIG_PROC_PARAM)p_test_item->param.ptr_param; + if (p_send_cfg_param != NULL) { + p_send_cfg_param->config = NULL; + ret = free_mem_in_heap_p( + (void **)&p_test_item->param.ptr_param); + p_test_item->param.ptr_param = NULL; + } + return ret; +} + +/*-------------------------------init config recover test item---------------------------------------*/ + +/******************************************************************************* +* Function Name : cfg_recover_test_before_func +* Description : set some hardware and init recover config param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 cfg_recover_test_before_func(ptr32 p_data) +{ + s32 ret = 0; + PST_RECOVER_CHIP_CFG_RES p_res = NULL; + PST_TEST_ITEM p_test_item = NULL; + + p_test_item = (PST_TEST_ITEM)p_data; + p_test_item->test_res.ptr_res = NULL; + + ret = get_recover_cfg_param_mess(p_test_item); + if (ret == 0) { + board_print_error("get recover config param error!\n"); + return 0; + } + /* get cfg recover test result buf*/ + ret = alloc_recover_cfg_item_res(p_test_item); + if (ret == 0) { + board_print_error("get cfg recover test result error!\n"); + return 0; + } + p_res = (PST_RECOVER_CHIP_CFG_RES)p_test_item->test_res.ptr_res; + return ret; +} + +/******************************************************************************* +* Function Name : get_recover_cfg_param_mess +* Description : get recover cfg param +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : u8(0:fail 1:ok) +*******************************************************************************/ +extern s32 get_recover_cfg_param_mess(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_RECOVER_CHIP_CFG_PARAM p_recover_cfg_param = NULL; + PST_TP_DEV p_tp_dev = p_test_item->p_tp_dev; + + ret = alloc_mem_in_heap((void **)&p_recover_cfg_param, + sizeof(ST_RECOVER_CHIP_CFG_PARAM)); + if (ret == 0) { + board_print_error( + "recovery config param alloc memory error!\n"); + return 0; + } + + p_recover_cfg_param->config_arr = p_tp_dev->cfg; + p_recover_cfg_param->cfg_len = p_tp_dev->cfg_len; + p_test_item->param.ptr_param = p_recover_cfg_param; + return ret; +} +/******************************************************************************* +* Function Name : release_cfg_recover_test_item +* Description : release test param +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 release_cfg_recover_test_item(ptr32 p_data) +{ + s32 ret = 1; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + + /*release config recover test param*/ + ret = release_cfg_recover_param(p_test_item); + /*release config recover test res*/ + ret = free_recover_cfg_item_res(p_test_item); + free_item_param(p_test_item); + return ret; +} + +/******************************************************************************* +* Function Name : release_cfg_recover_param +* Description : release config recover param +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_cfg_recover_param(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_RECOVER_CHIP_CFG_PARAM p_recover_cfg_param = NULL; + p_recover_cfg_param = + (PST_RECOVER_CHIP_CFG_PARAM)p_test_item->param.ptr_param; + if (p_recover_cfg_param != NULL) { + p_recover_cfg_param->config_arr = NULL; + ret = free_mem_in_heap_p( + (void **)&p_test_item->param.ptr_param); + p_test_item->param.ptr_param = NULL; + } + return ret; +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.h new file mode 100644 index 000000000000..b769021423fe --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_item_init.h @@ -0,0 +1,63 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : test_item_init.h +* Author : Zhitao Yang +* Version : V1.0.0 +* Date : 28/03/2018 +* Description : initial test item +*******************************************************************************/ +#ifndef TEST_ITEM_INIT_H +#define TEST_ITEM_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "test_item_def.h" +#include "test_order.h" + +/*************************************init open test item********************************************/ +extern s32 rawdata_test_before_func(ptr32 p_data, ptr32 p_param); +extern s32 release_rawdata_test_item(ptr32 p_data); +/*************************************init open test item end*****************************************/ + +/*************************************init short test item********************************************/ +/*init short test param*/ +extern s32 short_test_before_func(ptr32 p_data, ptr32 p_param); +extern s32 get_short_param(IN_OUT PST_TEST_ITEM p_test_item, + PST_TEST_PARAM p_test_param); +extern s32 release_short_test_item(IN_OUT ptr32 p_data); + +/*************************************init short test item end*****************************************/ + +/*************************************init version test item********************************************/ +extern s32 version_test_before_func(ptr32 p_data, ptr32 p_param); +extern s32 version_test_finished_func(ptr32 p_data); +/*************************************init version test item end*****************************************/ + +/*************************************init flash test item********************************************/ +extern s32 flash_test_before_func(ptr32 p_data, ptr32 p_param); +extern s32 release_flash_test_item(ptr32 p_data); + +/*************************************init flash test item end*****************************************/ + +/*************************************init send config test item********************************************/ +extern s32 send_cfg_test_before_func(ptr32 p_data, ptr32 p_param); +/*init send config test param*/ +extern s32 get_send_cfg_param_mess(PST_TEST_ITEM p_test_item, + PST_TEST_PARAM p_test_param); +extern s32 release_cfg_test_item(ptr32 p_data); +extern s32 release_send_cfg_param(PST_TEST_ITEM p_test_item); +/*************************************init send config test item end*****************************************/ + +/*************************************init recover config test item********************************************/ +extern s32 cfg_recover_test_before_func(ptr32 p_data); +/*init cfg recover test param*/ +extern s32 get_recover_cfg_param_mess(PST_TEST_ITEM p_test_item); +extern s32 release_cfg_recover_test_item(ptr32 p_data); +extern s32 release_cfg_recover_param(PST_TEST_ITEM p_test_item); +/*************************************init recover config test item end*****************************************/ +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.c new file mode 100644 index 000000000000..a278a7533719 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.c @@ -0,0 +1,2531 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : test_order.h +* Author : +* Version : V1.0.0 +* Date : 03/05/2018 +* Description : parse XML order +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "chip_ini.h" +#include "test_order.h" +#include "crc_decrypt.h" +#include "simple_mem_manager.h" +#include "tp_dev_control.h" +#include "generic_func.h" + +#include "generic_func.h" +#include "extra_tp_control.h" +#include "tp_dev_control.h" + +#include "config.h" +#include "mxml.h" + +static mxml_node_t *top; + +/******************************************************************************* +* Function Name : get_rawdata_len +* Description : get rawdata len +* Input : PST_TP_DEV p_tp_dev +* Output : PST_TP_DEV p_tp_dev +* Return : none +*******************************************************************************/ +static void get_rawdata_len(PST_TP_DEV p_tp_dev) +{ + p_tp_dev->rawdata_len = + p_tp_dev->total_drv_num * p_tp_dev->total_sen_num; + p_tp_dev->key_rawdata_num = + p_tp_dev->total_drv_num * p_tp_dev->total_sen_num - + p_tp_dev->sc_sen_num * p_tp_dev->sc_drv_num; +} +/******************************************************************************* +* Function Name : get_key_pos_map +* Description : get key position +* Input : PST_TP_DEV p_tp_dev + : u8* key_pos + : u8 key_num_in_port + : u8 drv_flag +* Output : PST_TP_DEV p_tp_dev +* Return : none +*******************************************************************************/ +static void get_key_pos_map(PST_TP_DEV p_tp_dev, u8 *key_pos, + u8 key_num_in_port, u8 drv_flag) +{ + u8 i = 0; + u8 area_key = 0; + u8 tmp_pos = 0; + u8 key_num = 0; + u8 depend_key_rat = 8; + if (p_tp_dev->chip_type == TP_ALTO) { + depend_key_rat = 6; + } + for (i = 0; i < strlen((const char *)key_pos); i++) { + if (key_pos[i] % depend_key_rat != 0) { + area_key = 1; + break; + } + } + if (area_key == 1) { + p_tp_dev->key_num = + p_tp_dev->total_drv_num * p_tp_dev->total_sen_num - + p_tp_dev->sc_sen_num * p_tp_dev->sc_drv_num; + for (i = 0; i < p_tp_dev->key_num; i++) { + p_tp_dev->key_pos_arr[i] = i; + } + } else { + key_num = 0; + for (i = 0; i < strlen((const char *)key_pos); i++) { + if (key_pos[i] != 0) { + if (drv_flag) { + tmp_pos = + key_pos[i] / depend_key_rat + + p_tp_dev->sc_sen_num * + (i / key_num_in_port) - + 1; + } else { + tmp_pos = + key_pos[i] / depend_key_rat + + p_tp_dev->sc_drv_num * + (i / key_num_in_port) - + 1; + } + p_tp_dev->key_pos_arr[key_num] = tmp_pos; + key_num++; + } + } + p_tp_dev->key_num = key_num; + } +} + +/******************************************************************************* +* Function Name : get_sc_drv_sen_key_num +* Description : get sc_drv_num sc_sen_num key_num +* Input : PST_TP_DEV p_tp_dev +* Input : u8 key_start_addr + : u8 key_en + ：u8 sen_as_key + ：u8 key_com_port_num + ：u8 max_key_num +* Output : PST_TP_DEV p_tp_dev +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 get_sc_drv_sen_key_num(PST_TP_DEV p_tp_dev, u8 key_start_addr, + u8 key_en, u8 sen_as_key, u8 key_com_port_num, + u8 max_key_num) +{ + s32 ret = 1; + u8 key_pos[TP_MAX_KEY_NUM]; + u8 max_key_num_in_com_port = 0; + u8 drv_flag = 0; + + p_tp_dev->sc_drv_num = p_tp_dev->total_drv_num; + p_tp_dev->sc_sen_num = p_tp_dev->total_sen_num; + /* screen sensor and driver num */ + if (sen_as_key == 0) { + drv_flag = 1; + + if (key_com_port_num == 1) { + max_key_num_in_com_port = max_key_num / 2; + p_tp_dev->sc_drv_num = + p_tp_dev->total_drv_num - key_en * 2; + } else { + max_key_num_in_com_port = max_key_num; + p_tp_dev->sc_drv_num = p_tp_dev->total_drv_num - key_en; + } + } else { + if (key_com_port_num == 1) { + max_key_num_in_com_port = max_key_num / 2; + p_tp_dev->sc_sen_num = + p_tp_dev->total_sen_num - key_en * 2; + } else { + max_key_num_in_com_port = max_key_num; + p_tp_dev->sc_sen_num = p_tp_dev->total_sen_num - key_en; + } + } + board_print_debug("sc drv num is:%d\n", p_tp_dev->sc_drv_num); + board_print_debug("sc sen num is:%d\n", p_tp_dev->sc_sen_num); + get_rawdata_len(p_tp_dev); + if (p_tp_dev->key_rawdata_num == 0) { + p_tp_dev->key_num = 0; + } else { + /*read key_pos*/ + ret = chip_reg_read(p_tp_dev, key_start_addr, key_pos, + sizeof(key_pos)); + if (ret == 0) { + board_print_error("read key_pos faild!\n"); + return 0; + } + get_key_pos_map(p_tp_dev, key_pos, max_key_num_in_com_port, + drv_flag); + } + board_print_debug("key_num:%d\n", p_tp_dev->key_num); + return ret; +} + +/******************************************************************************* +* Function Name : get_data_step +* Description : get data step +* Input : u8 *data_str +* Output : +* Return : s32(data step) +*******************************************************************************/ +static s32 get_data_step(cu8 *data_str) +{ + s32 step = 0; + if (data_str[0] == 'T') { + step = 4; + } else { + step = 3; + } + return step; +} + +/******************************************************************************* +* Function Name : get_step4_abs_addr +* Description : get_step4_abs_addr +* Input : PST_TP_DEV p_dev +* Output : PST_ADDR_POS_INFO p_addr_info +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 get_step4_abs_addr(PST_TP_DEV p_dev, PST_ADDR_POS_INFO p_addr_info, + cu8 *config) +{ + s32 ret = 1; + cu8 *sub_bag_ptr = NULL; + u8 i; + + sub_bag_ptr = &config[4]; + for (i = 0; i < config[2]; i++) { + if (sub_bag_ptr[0] == p_addr_info->package_id) + break; + sub_bag_ptr += sub_bag_ptr[1] + 3; + } + + if (i >= config[2]) { + board_print_error("Cann't find the specifiled bag num %d\n", + p_addr_info->package_id); + return 0; + } + + if (sub_bag_ptr[1] + 3 < p_addr_info->offset + 1) { + board_print_debug( + "Sub bag len less then you want to read: %d < %d,pacakge id:%d,offset:%d,lsb:%d,hsb:%d\n", + sub_bag_ptr[1] + 3, p_addr_info->offset + 1, + p_addr_info->package_id, p_addr_info->offset, + p_addr_info->lsb, p_addr_info->hsb); + return 0; + } + + p_addr_info->addr = p_dev->cfg_start_addr + + (sub_bag_ptr + p_addr_info->offset - config); + return ret; +} + +/******************************************************************************* +* Function Name : parse_step3_addr_data +* Description : parse_step3_addr_data +* Input : cu8* string_info +* Input : PST_ADDR_POS_INFO p_addr1_info +* Input : PST_ADDR_POS_INFO p_addr2_info +* Output : PST_ADDR_POS_INFO p_addr1_info +* Output : PST_ADDR_POS_INFO p_addr2_info +* Return : s32(0:fail 1,2:ok,1:p_addr1_info 2:p_addr1_info,p_addr2_info) +*******************************************************************************/ +static s32 parse_step3_addr_data(PST_TP_DEV p_dev, cu8 *string_info, + PST_ADDR_POS_INFO p_addr1_info, + PST_ADDR_POS_INFO p_addr2_info) +{ + s32 ret = 0; + u8 str_tmp[128]; + u8 string_info_len = strlen((const s8 *)string_info); + u8 *field = NULL; + if (NULL == string_info || string_info_len == 0) { + board_print_error("parse str is null!\n"); + return ret; + } + if (string_info_len > sizeof(str_tmp)) { + board_print_error("ini addr str is error:%s!\n", string_info); + return ret; + } + memcpy(str_tmp, string_info, string_info_len); + str_tmp[string_info_len] = '0'; + + if ((strlen((const char *)str_tmp) == 0)) { + return ret; + } + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + board_print_error("get addr1 null!\n"); + return ret; + } + p_addr1_info->addr = atohex(field, strlen((const char *)field)); + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + return ret; + } + p_addr1_info->lsb = atoi((char const *)field); + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + return ret; + } + p_addr1_info->hsb = atoi((char const *)field); + ret++; + + if (p_addr2_info != NULL) { + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + board_print_debug("get addr2 null, parse str:%s!\n", + string_info); + return ret; + } + p_addr2_info->addr = atohex(field, strlen((const char *)field)); + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + return ret; + } + p_addr2_info->lsb = atoi((char const *)field); + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + return ret; + } + p_addr2_info->hsb = atoi((char const *)field); + ret++; + } + return ret; +} + +/******************************************************************************* +* Function Name : parse_step4_addr_data +* Description : get data with package id and offset +* Input : cu8* string_info +* Output : PST_ADDR_POS_INFO p_addr1_info +* Output : PST_ADDR_POS_INFO p_addr2_info +* Return : s32(0:fail 1,2:ok,1:p_addr1_info 2:p_addr1_info,p_addr2_info) +*******************************************************************************/ +static s32 parse_step4_addr_data(PST_TP_DEV p_dev, cu8 *string_info, + PST_ADDR_POS_INFO p_addr1_info, + PST_ADDR_POS_INFO p_addr2_info) +{ + s32 ret = 0; + s32 free_mem = 0; + u8 *field = NULL; + u8 *str_tmp = NULL; + u8 string_info_len = 0; + + string_info_len = strlen((const s8 *)string_info); + if (string_info_len == 0) { + board_print_error("string_info len is invalid!\n"); + return ret; + } + /*board_print_debug("string_info len is: %d!\n",string_info_len);*/ + ret = alloc_mem_in_heap((void **)&str_tmp, string_info_len + 1); + if (0 == ret) { + board_print_error("string_info malloc error!\n"); + free_mem_in_heap((void *)str_tmp); + return ret; + } + memcpy(str_tmp, string_info, string_info_len); + str_tmp[string_info_len] = '\0'; + + /*sub package id*/ + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + board_print_error("get addr1 null!\n"); + goto mallc_exit; + } + p_addr1_info->package_id = atoi((const char *)&field[1]); + + /*offset*/ + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + goto mallc_exit; + } + p_addr1_info->offset = atoi((char const *)field); + + /*low bit*/ + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + goto mallc_exit; + } + p_addr1_info->lsb = atoi((char const *)field); + + /*high bit*/ + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + goto mallc_exit; + } + p_addr1_info->hsb = atoi((char const *)field); + ret++; + + field = (u8 *)strsep((char **)&str_tmp, ","); + if ((p_addr2_info != NULL) && (field != NULL)) { + if (field == NULL) { + board_print_debug("get addr2 null!,parse str:%s\n", + string_info); + goto mallc_exit; + } + p_addr2_info->package_id = atoi((const char *)&field[1]); + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + goto mallc_exit; + } + p_addr2_info->offset = atoi((char const *)field); + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + goto mallc_exit; + } + p_addr2_info->lsb = atoi((char const *)field); + + field = (u8 *)strsep((char **)&str_tmp, ","); + if (field == NULL) { + goto mallc_exit; + } + p_addr2_info->hsb = atoi((char const *)field); + ret++; + } + +mallc_exit: + free_mem = free_mem_in_heap((void *)str_tmp); + board_print_debug("free_mem_in_heap return %d \n", free_mem); + str_tmp = NULL; + return ret; +} + +/******************************************************************************* +* Function Name : parse_addr_data +* Description : parse_addr_data +* Input : u8* string_info +* Input : PST_ADDR_POS_INFO p_addr1_info +* Input : PST_ADDR_POS_INFO p_addr2_info +* Input : u8 data_step +* Output : PST_ADDR_POS_INFO p_addr1_info +* Output : PST_ADDR_POS_INFO p_addr2_info +* Return : s32(0:fail 1,2:ok,1:p_addr1_info 2:p_addr1_info,p_addr2_info) +*******************************************************************************/ +static s32 parse_addr_data(PST_TP_DEV p_dev, u8 *string_info, + PST_ADDR_POS_INFO p_addr1_info, + PST_ADDR_POS_INFO p_addr2_info, u8 data_step) +{ + getrid_space((s8 *)string_info, strlen((const char *)string_info)); + if (data_step == 3) { + return parse_step3_addr_data(p_dev, string_info, p_addr1_info, + p_addr2_info); + } + if (data_step == 4) { + return parse_step4_addr_data(p_dev, string_info, p_addr1_info, + p_addr2_info); + } + return 0; +} + +/******************************************************************************* +* Function Name : get_step3_cfg_data +* Description : get_step3_cfg_data +* Input : PST_TP_DEV p_tp_dev +* Input : PST_ADDR_POS_INFO p_addr_info +* Input : cu8* config +* Output : none +* Return : u8(data in cfg) +*******************************************************************************/ +static u8 get_step3_cfg_data(PST_TP_DEV p_tp_dev, PST_ADDR_POS_INFO p_addr_info, + cu8 *config) +{ + u8 value = 0; + u8 tmp = 0; + tmp = (1 << (p_addr_info->hsb - p_addr_info->lsb + 1)) - 1; + tmp &= 0xff; + value = (config[p_addr_info->addr - p_tp_dev->cfg_start_addr] >> + p_addr_info->lsb) & + tmp; + return value; +} + +/******************************************************************************* +* Function Name : get_step4_cfg_data +* Description : get_step4_cfg_data +* Input : PST_TP_DEV p_tp_dev +* Input : PST_ADDR_POS_INFO p_addr_info +* Input : cu8* config +* Output : none +* Return : u8(data in cfg) +*******************************************************************************/ +static u8 get_step4_cfg_data(PST_TP_DEV p_tp_dev, PST_ADDR_POS_INFO p_addr_info, + cu8 *config) +{ + s32 ret = 0; + u8 value = 0; + u32 tmp = 0; + + ret = get_step4_abs_addr(p_tp_dev, p_addr_info, config); + if (ret == 0) { + return 0; + } + + tmp = (1 << (p_addr_info->hsb - p_addr_info->lsb + 1)) - 1; + tmp &= 0xff; + value = ((config[p_addr_info->addr - p_tp_dev->cfg_start_addr] >> + p_addr_info->lsb) & + tmp); + return value; +} + +/******************************************************************************* +* Function Name : get_reg_data +* Description : get reg data +* Input : PST_TP_DEV p_tp_dev +* Input : PST_ADDR_POS_INFO p_addr_info +* Input : cu8* config +* Input : u8 data_step +* Output : none +* Return : u8(data in reg) +*******************************************************************************/ +static u8 get_cfg_data(PST_TP_DEV p_tp_dev, PST_ADDR_POS_INFO p_addr_info, + cu8 *config, u8 data_step) +{ + if (data_step == 3) { + return get_step3_cfg_data(p_tp_dev, p_addr_info, config); + } + if (data_step == 4) { + return get_step4_cfg_data(p_tp_dev, p_addr_info, config); + } + return 0; +} + +/******************************************************************************* +* Function Name : parse_cfg_value +* Description : parse_cfg_value +* Input : PST_TP_DEV p_dev +* Input : u8* string_info +* Input : u8* p_config +* Output : PST_TP_DEV p_tp_dev +* Return : u32 (data in cfg parsed) +*******************************************************************************/ +extern u32 parse_cfg_value(PST_TP_DEV p_dev, u8 *string_info, u8 *p_config) +{ + u32 ret = 0; + s32 step = 0; + u8 value1 = 0; + u8 value2 = 0; + s32 val_num = 0; + ST_ADDR_POS_INFO addr_info1, addr_info2; + step = get_data_step(string_info); + val_num = parse_addr_data(p_dev, string_info, &addr_info1, &addr_info2, + step); + if (val_num == 0) { + return 0; + } + value1 = get_cfg_data(p_dev, &addr_info1, p_config, step); + if (val_num >= 2) { + value2 = get_cfg_data(p_dev, &addr_info2, p_config, step); + } + ret = value1 + value2; + return ret; +} + +/******************************************************************************* +* Function Name : parse_addr_from_str +* Description : parse_addr_from_str +* Input : PST_TP_DEV p_dev +* Input : u8* string_info +* Input : cu8* config +* Output : none +* Return : u32 (address) +*******************************************************************************/ +extern u32 parse_addr_from_str(PST_TP_DEV p_dev, u8 *string_info, cu8 *config) +{ + s32 ret = 0; + s32 step = 0; + s32 val_num = 0; + ST_ADDR_POS_INFO addr_info1, addr_info2; + step = get_data_step(string_info); + val_num = parse_addr_data(p_dev, string_info, &addr_info1, &addr_info2, + step); + if (val_num == 0) { + return 0; + } + if (step == 4) { + ret = get_step4_abs_addr(p_dev, &addr_info1, config); + if (ret == 0) { + return 0; + } + } + return addr_info1.addr; +} + +/******************************************************************************* +* Function Name : disable_hopping +* Description : disable hopping +* Input : PST_TP_DEV p_tp_dev +* Input : u8*str_info + : u8*cfg +* Output : PST_TP_DEV p_tp_dev +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 disable_hopping(PST_TP_DEV p_tp_dev, u8 *str_info, u8 *cfg, + u16 cfg_len) +{ + s32 ret = 1; + u8 num = 0; + s32 step = 0; + u32 hopping_en = 0; + u8 tmp = 1; + ST_ADDR_POS_INFO addr_info1; + + step = get_data_step(str_info); + num = parse_addr_data(p_tp_dev, str_info, &addr_info1, NULL, step); + if (num == 0) { + return 0; + } + hopping_en = get_cfg_data(p_tp_dev, &addr_info1, cfg, step); + if (hopping_en == 1) { + tmp = (1 << (addr_info1.hsb - addr_info1.lsb + 1)) - 1; + tmp = tmp << addr_info1.lsb; + tmp = (~tmp) & 0xff; + if (step == 4) { + get_step4_abs_addr(p_tp_dev, &addr_info1, cfg); + } + + cfg[addr_info1.addr - p_tp_dev->cfg_start_addr] &= tmp; + } + update_cfg_checksum(p_tp_dev, cfg, cfg_len); + return ret; +} + +/******************************************************************************* +* Function Name : init_dev_const_param +* Description : init dev const param +* Input : PST_TP_DEV p_tp_dev +* Output : PST_TP_DEV p_tp_dev +* Return : void +*******************************************************************************/ +extern void init_dev_const_param(PST_TP_DEV p_tp_dev) +{ + p_tp_dev->chip_type = TP_NORMANDY; /* chip type*/ + p_tp_dev->chip_sub_type = TP_GT9886; /* chip sub type*/ + + /*voltage setting*/ + p_tp_dev->doze_ref_cnt = 1; /*1:doze mode 0:exit doze*/ + + /*cfg*/ + p_tp_dev->cfg_start_addr = 0x6F78; + p_tp_dev->ext_cfg_addr = 0; + p_tp_dev->ext_cfg_len = 0; + p_tp_dev->cfg_len = + 690; /*if ext_cfg_len != 0 then cfg_len = base_cfg_len + ext_cfg_len*/ + + p_tp_dev->use_soft_reset = 0; /* 1 use soft reset first */ + p_tp_dev->no_rst_pin = 0; /* 1 no rst pin 0 has rst pin default 0*/ + + /* max sensor and driver num for die*/ + p_tp_dev->max_sen_num_in_die = 36; + p_tp_dev->max_drv_num_in_die = 40; + + /* max sensor and driver num for this chip*/ + p_tp_dev->max_sen_num = 36; + p_tp_dev->max_drv_num = 40; + /*p_tp_dev->max_key_num = 4;*/ + + /*drv channel map*/ + p_tp_dev->map_disable = 0; + memcpy(p_tp_dev->drv_map, DRV_MAP, sizeof(DRV_MAP)); + memcpy(p_tp_dev->sen_map, SEN_MAP, sizeof(SEN_MAP)); + + /*real_cmd_addr*/ + p_tp_dev->real_cmd_addr = + 0x6F68; /*this field may be same as fields in cmd_set*/ + + /*rawdata_cmd*/ + p_tp_dev->cmd_set.coorddata_cmd.addr = 0x6F68; + p_tp_dev->cmd_set.coorddata_cmd.cmd_buf[0] = 0x00; + p_tp_dev->cmd_set.coorddata_cmd.cmd_buf[1] = 0x00; + p_tp_dev->cmd_set.coorddata_cmd.cmd_buf[2] = 0x00; + p_tp_dev->cmd_set.coorddata_cmd.cmd_len = 3; + + p_tp_dev->cmd_set.rawdata_cmd.addr = 0x6F68; + p_tp_dev->cmd_set.rawdata_cmd.cmd_buf[0] = 0x01; + p_tp_dev->cmd_set.rawdata_cmd.cmd_buf[1] = 0x00; + p_tp_dev->cmd_set.rawdata_cmd.cmd_buf[2] = 0xff; + p_tp_dev->cmd_set.rawdata_cmd.cmd_len = 3; + + p_tp_dev->rawdata_addr = 0x8FA0; + p_tp_dev->rawdata_len = 0; + p_tp_dev->rawdata_option = _DATA_BIT_16 | _DATA_LARGE_ENDIAN | + _DATA_SIGNED | _DATA_DRV_SEN_INVERT; + + p_tp_dev->syncflag_addr = 0x4100; + p_tp_dev->syncflag_mask = 0x80; +} + +/******************************************************************************* +* Function Name : parse_key_data +* Description : parse key infor +* Input : PST_TP_DEV p_tp_dev +* Input : dictionary* p_dict_ini +* Output : PST_TP_DEV p_tp_dev +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_key_data(PST_TP_DEV p_tp_dev, u8 *cfg) +{ + s32 ret = 1; + u16 key_start_addr; + u8 sen_as_key = 0; /*0:use sen chn as key, 1: use drv chn as key*/ + u8 key_com_port_num = 0; + u8 key_en = 0; + u8 max_key_num = 4; + + key_start_addr = parse_addr_from_str(p_tp_dev, KEY_START_ADDR, cfg); + sen_as_key = parse_cfg_value(p_tp_dev, SEN_AS_KEY_ADDR, cfg); + key_en = parse_cfg_value(p_tp_dev, KEY_EN, cfg); + + ret = get_sc_drv_sen_key_num(p_tp_dev, key_start_addr, key_en, + sen_as_key, key_com_port_num, max_key_num); + return ret; +} + +/******************************************************************************* +* Function Name : parse_cfg +* Description : prse config +* Input : PST_TP_DEV p_tp_dev + : u8*cfg + : u16 cfg_len +* Output : PST_TP_DEV p_tp_dev +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_cfg(PST_TP_DEV p_tp_dev, u8 *cfg) +{ + s32 ret = 0; + p_tp_dev->total_sen_num = parse_cfg_value(p_tp_dev, SEN_NUM_ADDR, cfg); + p_tp_dev->sc_sen_num = p_tp_dev->total_sen_num; + board_print_debug("total sen num:%d\n", p_tp_dev->total_sen_num); + p_tp_dev->total_drv_num = parse_cfg_value(p_tp_dev, DRV_NUM_ADDR, cfg); + p_tp_dev->sc_drv_num = p_tp_dev->total_drv_num; + board_print_debug("total drv num:%d\n", p_tp_dev->total_drv_num); + + p_tp_dev->sen_start_addr = + parse_addr_from_str(p_tp_dev, SEN_START_ADDR, cfg); + p_tp_dev->drv_start_addr = + parse_addr_from_str(p_tp_dev, DRV_START_ADDR, cfg); + ret = parse_key_data(p_tp_dev, cfg); + return ret; +} + +/******************************************************************************* +* Function Name : init_test_config +* Description : init test config +* Input : PST_TP_DEV p_tp_dev + : u8*cfg + ：u16 p_cfg_len +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 init_test_config(PST_TP_DEV p_tp_dev, u8 *test_cfg, u16 *p_cfg_len) +{ + s32 ret = 1; + if (*p_cfg_len == 0) { + BOARD_PRINT("switch to original config!\n"); + memcpy(test_cfg, p_tp_dev->cfg, p_tp_dev->cfg_len); + *p_cfg_len = p_tp_dev->cfg_len; + } else { + BOARD_PRINT("switch to test config in order!\n"); + test_cfg[0] = p_tp_dev->cfg[0]; + if (p_tp_dev->chip_type == TP_NORMANDY) { + test_cfg[1] |= 0x01; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : header_file_init_dev +* Description : init dev info with chip_ini.h +* Input : PST_TP_DEV p_tp_dev +* Output : PST_TP_DEV p_tp_dev +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 header_file_init_dev(PST_TP_DEV p_tp_dev, u8 *cfg, u16 *p_cfg_len) +{ + s32 ret = 1; + /*init const param*/ + init_dev_const_param(p_tp_dev); + + /*read cfg*/ + ret = read_chip_original_cfg(p_tp_dev); + if (ret == 0) { + board_print_error("read chip config faild!\n"); + return 0; + } + /*init test config*/ + ret = init_test_config(p_tp_dev, cfg, p_cfg_len); + if (ret == 0) { + board_print_error("init test config faild!\n"); + return 0; + } + /*parse config*/ + ret = parse_cfg(p_tp_dev, cfg); + if (ret == 0) { + board_print_error("parse config faild!\n"); + return 0; + } + /*disable hopping*/ + ret = disable_hopping(p_tp_dev, HOPPING_EN, cfg, *p_cfg_len); + return ret; +} + +/******************************************************************************* +* Function Name : parse_init_dev_info +* Description : parse device info from order +* Input : PST_TP_DEV p_tp_dev + : PST_TEST_PARAM p_test_parm +* Output : PST_TP_DEV p_tp_dev +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_init_dev_info(PST_TP_DEV p_tp_dev, PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + mxml_node_t *obj_set = NULL; + mxml_node_t *chip_ini = NULL; + mxml_node_t *parent_xnode = NULL; + u16 chip_type = 0; + u16 chip_sub_type = 0; + + /* get chip ini content from xml order*/ + obj_set = mxmlFindElement(top, top, "OBJ_SETTING", NULL, NULL, + MXML_DESCEND); + + if ((obj_set == NULL) || (obj_set->child == NULL)) { + board_print_error("can not find OBJ_SETTING in order!\n"); + return 0; + } + + parent_xnode = mxmlFindElement(obj_set, obj_set, "powerVolt", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + p_tp_dev->power_volt = 2800; + } else { + p_tp_dev->power_volt = + str_to_int(parent_xnode->child->value.opaque); + } + board_print_debug("power volt:%d!\n", p_tp_dev->power_volt); + /*find chip type*/ + parent_xnode = mxmlFindElement(obj_set, obj_set, "tpMainType", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find tpMainType in order!\n"); + return 0; + } + chip_type = str_to_int(parent_xnode->child->value.opaque); + if (chip_type != p_tp_dev->chip_type) { + board_print_error("chip type set in order is error!\n"); + return 0; + } + + parent_xnode = mxmlFindElement(parent_xnode, obj_set, "tpSubType", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find tpSubType in order!\n"); + return 0; + } + chip_sub_type = str_to_int(parent_xnode->child->value.opaque); + chip_ini = + mxmlFindElement(top, top, "chipIni", NULL, NULL, MXML_DESCEND); + if ((chip_ini == NULL) || (chip_ini->child == NULL)) { + board_print_error( + "order error,test station should be set as ANDR-MAC!\n"); + return 0; + } + + memset(p_tp_dev->drv_map, 255, TP_MAX_CHN_NUM); + memset(p_tp_dev->sen_map, 255, TP_MAX_CHN_NUM); + memset(p_tp_dev->pack_drv_2_adc_map, 255, TP_MAX_CHN_NUM); + memset(p_tp_dev->pack_sen_2_adc_map, 255, TP_MAX_CHN_NUM); + + /*init tp device with header file*/ + ret = header_file_init_dev(p_tp_dev, p_test_param->test_cfg, + &p_test_param->cfg_len); + return ret; +} + +/******************************************************************************* +* Function Name : parse_order_config +* Description : parse order config +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_order_config(PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + p_test_param->cfg_len = 0; + + board_print_debug("parse order config!\n"); + ret = alloc_mem_in_heap((void **)&p_test_param->test_cfg, + TP_MAX_CFG_LEN); + if (ret == 0) { + board_print_error("test config malloc memory error!\n"); + return 0; + } + p_test_param->test_cfg[0] = '\0'; + + /*find config from top node*/ + parent_xnode = mxmlFindElement(top, top, "chipConfigProc", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find chipConfigProc param in order!\n"); + return 0; + } + /*init test config */ + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "config", + NULL, NULL, MXML_DESCEND); + if ((child_xnode != NULL) && (child_xnode->child != NULL)) { + ret = hexstr_to_array(p_test_param->test_cfg, + child_xnode->child->value.opaque, + TP_MAX_CFG_LEN); + if (ret > 0) { + board_print_debug("test cfg len=%d\n", ret); + p_test_param->cfg_len = ret; + } + } + + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "option", + NULL, NULL, MXML_DESCEND); + if ((child_xnode != NULL) && (child_xnode->child != NULL)) { + p_test_param->send_cfg_option = + str_to_int(child_xnode->child->value.opaque); + } + return ret; +} + +/******************************************************************************* +* Function Name : is_mach_test_item +* Description : test item +* Input : u16 test_id +* Output : +* Return : s32(0:no 1:yes) +*******************************************************************************/ +static s32 is_mach_test_item(u16 test_id) +{ + if (test_id == TP_RAWDATA_TEST_ITEMS_SET_ID) { + return 1; + } else if (test_id == TP_SHORT_TEST_ITEM_ID) { + return 1; + } else if (test_id == TP_VERSION_TEST_ITEM_ID) { + return 1; + } else if (test_id == TP_FLASH_TEST_ITEM_ID) { + return 1; + } else if (test_id == TP_CHIP_CFG_PROC_ITEM_ID) { + return 1; + } else if (test_id == TP_RECOVER_CFG_ITEM_ID) { + return 1; + } else { + return 0; + } +} + +/******************************************************************************* +* Function Name : parse_test_item_id +* Description : parse test item id +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_test_item_id(PST_TEST_PARAM p_test_param) +{ + s32 ret = 0; + u16 i = 0; + u16 itest_id = 0xffff; + u16 test_num = 0; + u16 sub_id_num = 0; + mxml_node_t *test_item = NULL; + mxml_node_t *test_id = NULL; + mxml_node_t *is_select = NULL; + mxml_node_t *sub_item = NULL; + mxml_node_t *parent_xnode = NULL; + PST_TEST_ITEM_ID_SET p_test_id_set = NULL; + p_test_param->test_item_num = 0; + /*定义空节点*/ + + /*find testItemSet from top node */ + parent_xnode = mxmlFindElement(top, top, "testItemSet", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_debug("no testItenSet in order file!\n"); + return 0; + } + /*malloc memory for test id*/ + ret = alloc_mem_in_heap((void **)&p_test_param->p_test_item_id_set, + MAX_TEST_NUM * sizeof(ST_TEST_ITEM_ID_SET)); + if (ret == 0) { + board_print_error("test item id set malloc memory error!\n"); + return 0; + } + p_test_id_set = p_test_param->p_test_item_id_set; + for (i = 0; i < MAX_TEST_NUM; i++) { + p_test_id_set[i].p_sub_id_set = NULL; + } + + /*find test item*/ + test_item = mxmlFindElement(parent_xnode, parent_xnode, "testItem", + NULL, NULL, MXML_DESCEND); + while ((test_item != NULL) && (test_item->child != NULL)) { + /*test item is select or not*/ + is_select = mxmlFindElement(test_item, test_item, "bSelected", + NULL, NULL, MXML_DESCEND); + if ((is_select != NULL) && (is_select->child != NULL) && + (str_to_int(is_select->child->value.opaque) == 1)) { + /*find test id*/ + test_id = mxmlFindElement(test_item, test_item, + "itemId", NULL, NULL, + MXML_DESCEND); + if ((test_id != NULL) && (test_id->child != NULL)) { + itest_id = str_to_int( + test_id->child->value.opaque); + if (is_mach_test_item(itest_id) != 1) { + test_item = mxmlFindElement( + test_item, parent_xnode, + "testItem", NULL, NULL, + MXML_NO_DESCEND); + continue; + } + board_print_debug("test id :%d\n", itest_id); + p_test_id_set[test_num].test_id = str_to_int( + test_id->child->value.opaque); + /*find sub test id*/ + sub_item = mxmlFindElement(test_item, test_item, + "subTestItem", NULL, + NULL, MXML_DESCEND); + if ((sub_item != NULL) && + (sub_item->child != NULL)) { + sub_id_num = 0; + ret = alloc_mem_in_heap( + (void **)&p_test_id_set[test_num] + .p_sub_id_set, + sizeof(ST_TEST_ITEM_ID_SET)); + if (ret == 0) { + board_print_error( + "test item id malloc memory error!i=%d\n", + i); + return 0; + } + p_test_id_set[test_num] + .p_sub_id_set->len = 0; + ret = alloc_mem_in_heap( + (void **)&p_test_id_set[test_num] + .p_sub_id_set->p_id_set, + MAX_SUBTEST_NUM); + if (ret == 0) { + board_print_error( + "sub id malloc memory error!test_id=%d\n", + p_test_id_set[test_num] + .test_id); + return 0; + } + } + while ((sub_item != NULL) && + (sub_item->child != NULL)) { + is_select = mxmlFindElement( + sub_item, sub_item, "bSelected", + NULL, NULL, MXML_DESCEND); + board_print_debug( + "sub id is select:%d\n", + str_to_int( + is_select->child->value + .opaque)); + if ((is_select != NULL) && + (is_select->child != NULL) && + (str_to_int(is_select->child->value + .opaque) == + 1)) { + /*find sub item id */ + test_id = mxmlFindElement( + sub_item, sub_item, + "itemId", NULL, NULL, + MXML_DESCEND); + if ((test_id != NULL) && + (test_id->child != NULL)) { + p_test_id_set[test_num] + .p_sub_id_set + ->p_id_set + [sub_id_num] = str_to_int( + test_id->child + ->value + .opaque); + sub_id_num++; + } + } + /*find next sub test item*/ + sub_item = mxmlFindElement( + sub_item, test_item, + "subTestItem", NULL, NULL, + MXML_DESCEND); + } + if (p_test_id_set[test_num].p_sub_id_set != + NULL) { + p_test_id_set[test_num] + .p_sub_id_set->len = sub_id_num; + board_print_debug("sub test num:%d\n", + sub_id_num); + } + test_num++; + } + } + /*find next test item*/ + test_item = mxmlFindElement(test_item, parent_xnode, "testItem", + NULL, NULL, MXML_NO_DESCEND); + } + p_test_param->test_item_num = test_num; + board_print_debug("test num:%d\n", test_num); + return ret; +} + +/******************************************************************************* +* Function Name : parse_need_check_node +* Description : parse need check node +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : u16(node num) +*******************************************************************************/ +extern u16 parse_need_check_node(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 0; + char *tmp_value = NULL; + u16 data_len = 0; + mxml_node_t *parent_xnode = NULL; + + parent_xnode = mxmlFindElement(top, top, "needCheckNodeParam", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("please set need check node!\n"); + return 0; + } + + if (parent_xnode->child == NULL) { + board_print_error("no need check node!\n"); + return 0; + } + tmp_value = parent_xnode->child->value.opaque; + data_len = (strlen(tmp_value) + 1) / 5 + 1; + + ret = alloc_mem_in_heap((void **)&p_raw_test_param->p_need_check_node, + sizeof(ST_NEED_CHECK_NODE)); + if (ret == 0) { + board_print_error("need check node malloc memory error!\n"); + return 0; + } + ret = alloc_mem_in_heap( + (void **)&p_raw_test_param->p_need_check_node->p_data_buf, + data_len); + if (ret == 0) { + board_print_error("need check node malloc memory error!\n"); + return 0; + } + /*init need check node*/ + p_raw_test_param->p_need_check_node->data_len = 0; + memset(p_raw_test_param->p_need_check_node->p_data_buf, 0, data_len); + p_raw_test_param->p_need_check_node->data_len = + hexstr_to_array(p_raw_test_param->p_need_check_node->p_data_buf, + tmp_value, data_len); + return data_len; +} + +/******************************************************************************* +* Function Name : parse_need_check_key +* Description : parse need check key +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param + : u16 data_len +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_need_check_key(PST_RAWDATA_TEST_PARAM p_raw_test_param, + u16 data_len) +{ + s32 ret = 0; + char *tmp_value = NULL; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + PST_NEED_CHECK_KEY p_need_check_key = NULL; + /*judge if need check key*/ + if (p_raw_test_param->p_raw_key_limit == NULL) { + return 1; + } + + ret = alloc_mem_in_heap( + (void **)&p_raw_test_param->p_raw_key_limit->p_need_check_key, + sizeof(ST_NEED_CHECK_KEY)); + if (ret == 0) { + board_print_error("need check key malloc memory error!\n"); + return 0; + } + p_need_check_key = p_raw_test_param->p_raw_key_limit->p_need_check_key; + /*init need check key*/ + ret = alloc_mem_in_heap((void **)&p_need_check_key->p_data_buf, + data_len); + if (ret == 0) { + board_print_error("need check key buf malloc memory error!\n"); + return 0; + } + p_need_check_key->len = 0; + memset(p_need_check_key->p_data_buf, 0, data_len); + + child_xnode = mxmlFindElement(parent_xnode, top, "needCheckKey", NULL, + NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_debug( + "no need check key, please set need check key!\n"); + return 1; + } + tmp_value = child_xnode->child->value.opaque; + p_need_check_key->len = hexstr_to_array(p_need_check_key->p_data_buf, + tmp_value, data_len); + return ret; +} + +/******************************************************************************* +* Function Name : parse_special_node +* Description : parse special node +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param + : u16 data_len +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_special_node(PST_RAWDATA_TEST_PARAM p_raw_test_param, + u16 data_len) +{ + s32 ret = 0; + u16 i = 0; + + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + mxml_node_t *special_xnode = NULL; + + ret = alloc_mem_in_heap((void **)&p_raw_test_param->p_special_node, + sizeof(ST_RAWDATA_SPECIAL_NODE_PARAM)); + if (ret == 0) { + board_print_error("need check node malloc memory error!\n"); + return 0; + } + + ret = alloc_mem_in_heap( + (void **)&p_raw_test_param->p_special_node->p_data_buf, + data_len * sizeof(ST_SPECIAL_NODE_DEF)); + if (ret == 0) { + board_print_error("need check node malloc memory error!\n"); + return 0; + } + /*init sepcial node*/ + p_raw_test_param->p_special_node->data_len = 0; + special_xnode = mxmlFindElement(top, top, "rawdataSpecialNodeParam", + NULL, NULL, MXML_DESCEND); + if ((special_xnode == NULL) || (special_xnode->child == NULL)) { + return 1; + } + + i = 0; + parent_xnode = mxmlFindElement(special_xnode, special_xnode, "node", + NULL, NULL, MXML_DESCEND); + while ((special_xnode != NULL) && (special_xnode->child != NULL)) { + /*node id */ + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "nodeId", NULL, NULL, + MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + break; + } + p_raw_test_param->p_special_node->p_data_buf[i].node_id = + str_to_int(child_xnode->child->value.opaque); + + /*high raw limit*/ + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "highRawLimit", NULL, NULL, + MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + break; + } + p_raw_test_param->p_special_node->p_data_buf[i].high_raw_limit = + str_to_int(child_xnode->child->value.opaque); + + /*low raw limit*/ + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "lowRawLimit", NULL, NULL, + MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + break; + } + p_raw_test_param->p_special_node->p_data_buf[i].low_raw_limit = + str_to_int(child_xnode->child->value.opaque); + + /*accord limit*/ + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "accordLimit", NULL, NULL, + MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + break; + } + p_raw_test_param->p_special_node->p_data_buf[i].accord_limit = + str_to_int(child_xnode->child->value.opaque); + + /*offset limit*/ + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "offsetLimit", NULL, NULL, + MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + break; + } + p_raw_test_param->p_special_node->p_data_buf[i].offset_limit = + str_to_int(child_xnode->child->value.opaque); + + /*accord option*/ + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "accordOption", NULL, NULL, + MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + break; + } + p_raw_test_param->p_special_node->p_data_buf[i].accord_option = + str_to_int(child_xnode->child->value.opaque); + i++; + parent_xnode = mxmlFindElement(parent_xnode, special_xnode, + "node", NULL, NULL, + MXML_DESCEND); + } + p_raw_test_param->p_special_node->data_len = i; + return ret; +} + +/******************************************************************************* +* Function Name : parse_raw_max_limit +* Description : parse raw upper limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_raw_max_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 0; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + board_print_debug("parse raw max limit!\n"); + parent_xnode = mxmlFindElement(top, top, "rawdataLimitParam", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find rawdataLimitParam,please set in order!\n"); + return 0; + } + + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "upperLimit", + NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error( + "can not find raw upperLimit,please set in order!\n"); + return 0; + } + + if (p_raw_test_param->p_rawdata_limit == NULL) { + ret = alloc_mem_in_heap( + (void **)&p_raw_test_param->p_rawdata_limit, + sizeof(ST_RAWDATA_LIMIT_PARAM)); + if (ret == 0) { + board_print_error( + "rawdata limit malloc memory error!\n"); + return 0; + } + } + p_raw_test_param->p_rawdata_limit->upper_limit = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("rawdata upper limit:%d!\n", + p_raw_test_param->p_rawdata_limit->upper_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_raw_min_limit +* Description : parse raw lower limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_raw_min_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 1; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + board_print_debug("parse raw lower limit!\n"); + parent_xnode = mxmlFindElement(top, top, "rawdataLimitParam", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find rawdataLimitParam in order!\n"); + return 0; + } + + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "lowerLimit", + NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error( + "can not find raw lowerLimit,please set raw low limit!\n"); + return 0; + } + + if (p_raw_test_param->p_rawdata_limit == NULL) { + ret = alloc_mem_in_heap( + (void **)&p_raw_test_param->p_rawdata_limit, + sizeof(ST_RAWDATA_LIMIT_PARAM)); + if (ret == 0) { + board_print_error( + "rawdata limit malloc memory error!\n"); + return 0; + } + } + p_raw_test_param->p_rawdata_limit->lower_limit = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("rawdata lower limit:%d!\n", + p_raw_test_param->p_rawdata_limit->lower_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_accord_limit +* Description : parse accord limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_accord_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 0; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + + parent_xnode = mxmlFindElement(top, top, "accordLimitParam", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find accordLimitParam in order!\n"); + return 0; + } + ret = alloc_mem_in_heap((void **)&p_raw_test_param->p_raw_accord_limit, + sizeof(ST_RAW_ACCORD_LIMIT_PARAM)); + if (ret == 0) { + board_print_error("accord limit malloc memory error!\n"); + return 0; + } + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "accordLimit", + NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error("can not find accordLimit in order!\n"); + return 0; + } + p_raw_test_param->p_raw_accord_limit->accord_limit = + str_to_int(child_xnode->child->value.opaque); + + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "accordOption", NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error("can not find accordOption in order!\n"); + return 0; + } + p_raw_test_param->p_raw_accord_limit->accord_option = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("accord limit:%d!\n", + p_raw_test_param->p_raw_accord_limit->accord_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_offset_limit +* Description : parse offset limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_offset_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 0; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + + parent_xnode = mxmlFindElement(top, top, "offsetLimitParam", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find offsetLimitParam in order!\n"); + return 0; + } + ret = alloc_mem_in_heap((void **)&p_raw_test_param->p_raw_offset_limit, + sizeof(ST_RAW_OFFSET_LIMIT_PARAM)); + if (ret == 0) { + board_print_error("offset limit malloc memory error!\n"); + return 0; + } + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "offsetLimit", + NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error("can not find offsetLimit in order!\n"); + return 0; + } + p_raw_test_param->p_raw_offset_limit->offset_limit = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("offset limit:%d!\n", + p_raw_test_param->p_raw_offset_limit->offset_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_uniform_limit +* Description : parse uniform limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_uniform_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 0; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + + parent_xnode = mxmlFindElement(top, top, "uniformLimitParam", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find uniformLimitParam in order!\n"); + return 0; + } + ret = alloc_mem_in_heap((void **)&p_raw_test_param->p_raw_uniform_limit, + sizeof(ST_RAW_UNIFORM_LIMIT_PARAM)); + if (ret == 0) { + board_print_error("uniform limit malloc memory error!\n"); + return 0; + } + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, + "uniformLimit", NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error( + "can not find uniformLimit, please set uniform limit!\n"); + return 0; + } + p_raw_test_param->p_raw_uniform_limit->uniform_limit = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("uniform limit:%d!\n", + p_raw_test_param->p_raw_uniform_limit->uniform_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_jitter_limit +* Description : parse jitter limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_jitter_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 0; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + + parent_xnode = mxmlFindElement(top, top, "jitterLimitParam", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find jitterLimitParam in order!\n"); + return 0; + } + ret = alloc_mem_in_heap((void **)&p_raw_test_param->p_raw_jitter_limit, + sizeof(ST_RAW_JITTER_LIMIT_PARAM)); + if (ret == 0) { + board_print_error("jitter limit malloc memory error!\n"); + return 0; + } + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "jitterLimit", + NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error( + "can not find jitterLimit, please set jitter limit!\n"); + return 0; + } + p_raw_test_param->p_raw_jitter_limit->jitter_limit = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("jitter limit:%d!\n", + p_raw_test_param->p_raw_jitter_limit->jitter_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_key_max_limit +* Description : parse key upper limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_key_max_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 0; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + + parent_xnode = mxmlFindElement(top, top, "keydataLimitParam", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find keydataLimitParam in order!\n"); + return 0; + } + if (p_raw_test_param->p_raw_key_limit == NULL) { + ret = alloc_mem_in_heap( + (void **)&p_raw_test_param->p_raw_key_limit, + sizeof(ST_RAW_KEY_LIMIT_PARAM)); + if (ret == 0) { + board_print_error( + "key data limit malloc memory error!\n"); + return 0; + } + } + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "upperLimit", + NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error("can not find key upperLimit in order!\n"); + return 0; + } + p_raw_test_param->p_raw_key_limit->upper_limit = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("key upper limit:%d!\n", + p_raw_test_param->p_raw_key_limit->upper_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_key_min_limit +* Description : parse key lower limit +* Input : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Output : PST_RAWDATA_TEST_PARAM p_raw_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_key_min_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param) +{ + s32 ret = 1; + mxml_node_t *parent_xnode = NULL; + mxml_node_t *child_xnode = NULL; + + parent_xnode = mxmlFindElement(top, top, "keydataLimitParam", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find keydataLimitParam in order!\n"); + return 0; + } + if (p_raw_test_param->p_raw_key_limit == NULL) { + ret = alloc_mem_in_heap( + (void **)&p_raw_test_param->p_raw_key_limit, + sizeof(ST_RAW_KEY_LIMIT_PARAM)); + if (ret == 0) { + board_print_error( + "key data limit malloc memory error!\n"); + return 0; + } + } + child_xnode = mxmlFindElement(parent_xnode, parent_xnode, "lowerLimit", + NULL, NULL, MXML_DESCEND); + if ((child_xnode == NULL) || (child_xnode->child == NULL)) { + board_print_error("can not find key lowerLimit in order!\n"); + return 0; + } + p_raw_test_param->p_raw_key_limit->lower_limit = + str_to_int(child_xnode->child->value.opaque); + board_print_debug("key lower limit:%d!\n", + p_raw_test_param->p_raw_key_limit->lower_limit); + return ret; +} + +/******************************************************************************* +* Function Name : parse_raw_test_param +* Description : parse rawdata test param +* Input : PST_TEST_PARAM p_test_param + : PST_SUB_TEST_ITEM_ID_SET p_sub_id_set +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_raw_test_param(PST_TEST_PARAM p_test_param, + PST_SUB_TEST_ITEM_ID_SET p_sub_id_set) +{ + s32 ret = 0; + u16 i = 0; + u16 data_len = 0; + PST_RAWDATA_TEST_PARAM p_raw_test_param = NULL; + mxml_node_t *test_item = NULL; + + /*no sub id */ + if (p_sub_id_set == NULL) { + return 1; + } + /*find rawdat test param*/ + test_item = mxmlFindElement(top, top, "rawdataTestParam", NULL, NULL, + MXML_DESCEND); + if ((test_item == NULL) || (test_item->child == NULL)) { + board_print_error("can not find rawdataTestParam in order!\n"); + return 0; + } + + ret = alloc_mem_in_heap((void **)&p_test_param->p_raw_test_param, + sizeof(ST_RAWDATA_TEST_PARAM)); + if (ret == 0) { + board_print_error("raw test param malloc memory error!\n"); + return ret; + } + p_raw_test_param = + (PST_RAWDATA_TEST_PARAM)p_test_param->p_raw_test_param; + + p_raw_test_param->p_need_check_node = NULL; + p_raw_test_param->p_special_node = NULL; + p_raw_test_param->p_rawdata_limit = NULL; + p_raw_test_param->p_raw_accord_limit = NULL; + p_raw_test_param->p_raw_offset_limit = NULL; + p_raw_test_param->p_raw_jitter_limit = NULL; + p_raw_test_param->p_raw_uniform_limit = NULL; + p_raw_test_param->p_raw_key_limit = NULL; + + for (i = 0; i < p_sub_id_set->len; i++) { + switch (p_sub_id_set->p_id_set[i]) { + case TP_RAWDATA_MAX_TEST_ITEM_ID: { + /*rawdata limit*/ + ret = parse_raw_max_limit(p_raw_test_param); + break; + } + case TP_RAWDATA_MIN_TEST_ITEM_ID: { + ret = parse_raw_min_limit(p_raw_test_param); + break; + } + case TP_ACCORD_TEST_ITEM_ID: { + /*accord limit*/ + ret = parse_accord_limit(p_raw_test_param); + break; + } + case TP_OFFSET_TEST_ITEM_ID: { + /*offset limit*/ + ret = parse_offset_limit(p_raw_test_param); + break; + } + case TP_UNIFORMITY_TEST_ITEM_ID: { + /*uniform limit*/ + ret = parse_uniform_limit(p_raw_test_param); + break; + } + case TP_RAWDATA_JITTER_TEST_ITEM_ID: { + /*jitter limit*/ + ret = parse_jitter_limit(p_raw_test_param); + break; + } + case TP_KEYDATA_MAX_TEST_ITEM_ID: { + /*key data upper limit*/ + ret = parse_key_max_limit(p_raw_test_param); + break; + } + case TP_KEYDATA_MIN_TEST_ITEM_ID: { + /*key data min limit*/ + ret = parse_key_min_limit(p_raw_test_param); + break; + } + default: { + break; + } + } + + if (ret == 0) { + return ret; + board_print_error("parse rawdata item error!\n"); + } + } + /*need check node*/ + data_len = parse_need_check_node(p_raw_test_param); + if (data_len == 0) { + board_print_error("parse need check node error!\n"); + return 0; + } + /*special test node*/ + ret = parse_special_node(p_raw_test_param, data_len + TP_MAX_KEY_NUM); + if (ret == 0) { + board_print_error("parse special node error!\n"); + return 0; + } + board_print_debug("special node len:%d!\n", + p_raw_test_param->p_special_node->data_len); + + /*need check key*/ + ret = parse_need_check_key(p_raw_test_param, TP_MAX_KEY_NUM); + if (ret == 0) { + board_print_error("parse need check key error!\n"); + return 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : parse_short_test_param +* Description : parse short test param +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_short_test_param(PST_TEST_PARAM p_test_param) +{ + s32 ret = 0; + mxml_node_t *test_item = NULL; + mxml_node_t *parent_xnode = NULL; + PST_SHORT_PARAM p_short_param = NULL; + + /*find short test param*/ + test_item = mxmlFindElement(top, top, "shortThresholdParam", NULL, NULL, + MXML_DESCEND); + if ((test_item == NULL) || (test_item->child == NULL)) { + board_print_error( + "can not find shortThresholdParam,plesse set short param in order!\n"); + return 0; + } + + ret = alloc_mem_in_heap((void **)&p_test_param->p_short_param, + sizeof(ST_SHORT_PARAM)); + if (ret == 0) { + board_print_error("short test param malloc memory error!\n"); + return 0; + } + p_short_param = (PST_SHORT_PARAM)p_test_param->p_short_param; + p_short_param->short_bin.update_bin_addr.bin_ptr = NULL; + p_short_param->short_bin.update_bin_len = 0; + p_short_param->short_opt.opt.opt_ptr = NULL; + + /*short test thrd node*/ + parent_xnode = mxmlFindElement(test_item, test_item, + "drvGndVddResistorThreshold", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find drvGndVddResistorThreshold,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.drv_gnd_vdd_resistor_threshold = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug( + "drv_gnd_vdd_resistor_threshold is :%d\n", + p_short_param->short_threshold.drv_gnd_vdd_resistor_threshold); + + parent_xnode = mxmlFindElement(test_item, test_item, + "senGndVddResistorThreshold", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find senGndVddResistorThreshold,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.sen_gnd_vdd_resistor_threshold = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug( + "sen_gnd_vdd_resistor_threshold is :%d\n", + p_short_param->short_threshold.sen_gnd_vdd_resistor_threshold); + + parent_xnode = mxmlFindElement(test_item, test_item, + "senSenResistorThreshold", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find senSenResistorThreshold,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.sen_sen_resistor_threshold = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug( + "sen_sen_resistor_threshold is :%d\n", + p_short_param->short_threshold.sen_sen_resistor_threshold); + + parent_xnode = mxmlFindElement(test_item, test_item, + "drvDrvResistorThreshold", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find drvDrvResistorThreshold,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.drv_drv_resistor_threshold = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug( + "drv_drv_resistor_threshold is :%d\n", + p_short_param->short_threshold.drv_drv_resistor_threshold); + + parent_xnode = mxmlFindElement(test_item, test_item, + "drvSenResistorThreshold", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find drvSenResistorThreshold,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.drv_sen_resistor_threshold = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug( + "drv_sen_resistor_threshold is :%d\n", + p_short_param->short_threshold.drv_sen_resistor_threshold); + + parent_xnode = mxmlFindElement(test_item, test_item, "gtShortThreshold", + NULL, NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find gtShortThreshold,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.gt_short_threshold = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug("gt_short_threshold is :%d\n", + p_short_param->short_threshold.gt_short_threshold); + + parent_xnode = mxmlFindElement(test_item, test_item, "adcReadDelay", + NULL, NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find adcReadDelay,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.adc_read_delay = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug("adc_read_delay is :%d\n", + p_short_param->short_threshold.adc_read_delay); + + parent_xnode = mxmlFindElement(test_item, test_item, + "diffcodeShortThreshold", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find diffcodeShortThreshold,plesse set in order!\n"); + return 0; + } + p_short_param->short_threshold.diffcode_short_threshold = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug( + "diffcode_short_threshold is :%d\n", + p_short_param->short_threshold.diffcode_short_threshold); + + p_short_param->short_threshold.tx_tx_factor = 68; + parent_xnode = mxmlFindElement(test_item, test_item, "txTxFactor", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode != NULL) && (parent_xnode->child != NULL)) { + p_short_param->short_threshold.tx_tx_factor = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug("tx_tx_factor is :%d\n", + p_short_param->short_threshold.tx_tx_factor); + } + + p_short_param->short_threshold.tx_rx_factor = 89; + parent_xnode = mxmlFindElement(test_item, test_item, "txRxFactor", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode != NULL) && (parent_xnode->child != NULL)) { + p_short_param->short_threshold.tx_rx_factor = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug("tx_rx_factor is :%d\n", + p_short_param->short_threshold.tx_rx_factor); + } + + p_short_param->short_threshold.rx_rx_factor = 75; + parent_xnode = mxmlFindElement(test_item, test_item, "rxRxFactor", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode != NULL) && (parent_xnode->child != NULL)) { + p_short_param->short_threshold.rx_rx_factor = + str_to_int(parent_xnode->child->value.opaque); + board_print_debug("rx_rx_factor is :%d\n", + p_short_param->short_threshold.rx_rx_factor); + } + return ret; +} + +/******************************************************************************* +* Function Name : parse_version_test_param +* Description : parse version test param +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_version_test_param(PST_TEST_PARAM p_test_param) +{ + s32 ret = 0; + mxml_node_t *test_item = NULL; + mxml_node_t *parent_xnode = NULL; + PST_VERSION_PARAM p_ver_param = NULL; + + /*malloc memory*/ + if (p_test_param->p_version_test_param == NULL) { + ret = alloc_mem_in_heap( + (void **)&p_test_param->p_version_test_param, + sizeof(ST_VERSION_PARAM)); + if (ret == 0) { + board_print_error( + "version test param malloc memory error!\n"); + return 0; + } + } else { + board_print_error("version test param memory error!\n"); + } + p_ver_param = (PST_VERSION_PARAM)p_test_param->p_version_test_param; + p_ver_param->p_update_bin_param = NULL; + + /*find version test param*/ + test_item = mxmlFindElement(top, top, "versionTestParam", NULL, NULL, + MXML_DESCEND); + if ((test_item == NULL) || (test_item->child == NULL)) { + board_print_error( + "can not find varsion test param,plesse set version param in order!\n"); + return 0; + } + + parent_xnode = mxmlFindElement(test_item, test_item, "icVerAddr", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find icVerAddr,plesse set icVerAddr in order!\n"); + return 0; + } + p_ver_param->ic_ver_addr = + atohex((unsigned char *)parent_xnode->child->value.opaque, + strlen((const char *)parent_xnode->child->value.opaque)); + board_print_debug("ic version addr:0x%04x!\n", + p_ver_param->ic_ver_addr); + p_ver_param->b_auto_update = 0; + + parent_xnode = mxmlFindElement(test_item, test_item, "versionStr", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error( + "can not find varsion info,plesse set fw version in order!\n"); + return 0; + } + p_ver_param->ver_param_len = hexstr_to_array( + p_ver_param->ver_param_str, parent_xnode->child->value.opaque, + MAX_VERSION_LEN); + board_print_debug("ver_param_len:%d!\n", p_ver_param->ver_param_len); + return ret; +} + +/******************************************************************************* +* Function Name : parse_flash_test_param +* Description : parse flash test param +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_flash_test_param(PST_TEST_PARAM p_test_param) +{ + s32 ret = 0; + mxml_node_t *test_item = NULL; + mxml_node_t *parent_xnode = NULL; + PST_FLASH_TEST_PARAM p_flash_param = NULL; + + /*find version test param*/ + ret = alloc_mem_in_heap((void **)&p_test_param->p_flash_test_param, + sizeof(ST_FLASH_TEST_PARAM)); + if (ret == 0) { + board_print_error("flash test param malloc memory error!\n"); + return 0; + } + p_flash_param = (PST_FLASH_TEST_PARAM)p_test_param->p_flash_test_param; + p_flash_param->config_arr = NULL; + p_flash_param->delay_time = 0; + + test_item = mxmlFindElement(top, top, "flashTestParam", NULL, NULL, + MXML_DESCEND); + if ((test_item == NULL) || (test_item->child == NULL)) { + board_print_error( + "can not find flash test param,plesse set flash param in order!\n"); + return 0; + } + + parent_xnode = mxmlFindElement(test_item, test_item, "option", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find flash option,order error!\n"); + return 0; + } + p_flash_param->option = str_to_int(parent_xnode->child->value.opaque); + board_print_debug("flash test option:0x%04x!\n", p_flash_param->option); + + parent_xnode = mxmlFindElement(test_item, test_item, "delayTime", NULL, + NULL, MXML_DESCEND); + if ((parent_xnode != NULL) && (parent_xnode->child != NULL)) { + p_flash_param->delay_time = + str_to_int(parent_xnode->child->value.opaque); + } + board_print_debug("delay_time in xml:%d!\n", p_flash_param->delay_time); + + return ret; +} + +/******************************************************************************* +* Function Name : parse_ic_name +* Description : parse_ic_name from order +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 parse_ic_name(PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + mxml_node_t *obj_set = NULL; + mxml_node_t *parent_xnode = NULL; + + obj_set = mxmlFindElement(top, top, "OBJ_SETTING", NULL, NULL, + MXML_DESCEND); + + if ((obj_set == NULL) || (obj_set->child == NULL)) { + board_print_error("can not find OBJ_SETTING in order!\n"); + return 0; + } + + parent_xnode = mxmlFindElement(obj_set, obj_set, "chipName", NULL, NULL, + MXML_DESCEND); + if ((parent_xnode == NULL) || (parent_xnode->child == NULL)) { + board_print_error("can not find chipName in order!\n"); + return 0; + } + memcpy(p_test_param->ic_name, parent_xnode->child->value.opaque, + strlen((const char *)parent_xnode->child->value.opaque) + 1); + board_print_debug("ic name in order :%s\n", p_test_param->ic_name); + + return ret; +} + +/******************************************************************************* +* Function Name : parse_test_param +* Description : parse test param +* Input : PST_TEST_PARAM *pp_test_param +* Output : PST_TEST_PARAM *pp_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 parse_test_param(PST_TEST_PARAM *pp_test_param) +{ + PST_TEST_PARAM p_test_param; + u16 i = 0; + s32 ret = 0; + u8 need_send_cfg = 0; + u8 cfg_flag = 0; + + /*(1)malloc memory for test param*/ + if (alloc_mem_in_heap((void **)pp_test_param, sizeof(ST_TEST_PARAM)) == + 0) { + board_print_error("test param malloc memory error!"); + return 0; + } + p_test_param = (PST_TEST_PARAM)(*pp_test_param); + p_test_param->test_cfg = NULL; + p_test_param->cfg_len = 0; + p_test_param->mode_sen_line = 0; + p_test_param->p_test_item_id_set = NULL; + p_test_param->p_raw_test_param = NULL; + p_test_param->p_diff_test_param = NULL; + p_test_param->p_short_param = NULL; + p_test_param->p_version_test_param = NULL; + p_test_param->p_flash_test_param = NULL; + + ret = parse_ic_name(p_test_param); + if (ret == 0) { + return 0; + } + + ret = parse_test_item_id(p_test_param); + if (ret == 0) { + board_print_error("parse test item id error!\n"); + return 0; + } + + if (p_test_param->test_item_num == 0) { + board_print_error("no need test item!\n"); + return 0; + } + + ret = parse_order_config(p_test_param); + if (ret == 0) { + board_print_error("parse_order_config error!\n"); + return 0; + } + + for (i = 0; i < p_test_param->test_item_num; i++) { + switch (p_test_param->p_test_item_id_set[i].test_id) { + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + p_test_param->close_hop = 1; + need_send_cfg++; + ret = parse_raw_test_param( + p_test_param, + p_test_param->p_test_item_id_set[i] + .p_sub_id_set); + break; + } + case TP_SHORT_TEST_ITEM_ID: { + need_send_cfg++; + ret = parse_short_test_param(p_test_param); + break; + } + case TP_VERSION_TEST_ITEM_ID: { + ret = parse_version_test_param(p_test_param); + break; + } + case TP_FLASH_TEST_ITEM_ID: { + ret = parse_flash_test_param(p_test_param); + break; + } + case TP_CHIP_CFG_PROC_ITEM_ID: { + cfg_flag |= 0x01; + /*ret = parse_order_config(p_test_param);*/ + break; + } + case TP_RECOVER_CFG_ITEM_ID: { + cfg_flag |= 0x02; + break; + } + default: { + break; + } + } + if (ret == 0) { + board_print_error("parse test param error!\n"); + break; + } + } + + if (need_send_cfg > 0) { + if ((cfg_flag & 0x01) == 0) { + p_test_param + ->p_test_item_id_set[p_test_param->test_item_num] + .test_id = TP_CHIP_CFG_PROC_ITEM_ID; + p_test_param->test_item_num++; + } + if ((cfg_flag & 0x02) == 0) { + p_test_param + ->p_test_item_id_set[p_test_param->test_item_num] + .test_id = TP_RECOVER_CFG_ITEM_ID; + p_test_param->test_item_num++; + } + } else { + if (((cfg_flag & 0x01) == 1) && ((cfg_flag & 0x02) == 0)) { + p_test_param + ->p_test_item_id_set[p_test_param->test_item_num] + .test_id = TP_RECOVER_CFG_ITEM_ID; + p_test_param->test_item_num++; + } + } + if ((cfg_flag & 0x01) == 0) { + p_test_param->test_cfg[0] = '\0'; + p_test_param->cfg_len = 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : release_order_config +* Description : release order config +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_order_config(PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + if (p_test_param->test_cfg != NULL) { + ret = free_mem_in_heap_p((void **)&p_test_param->test_cfg); + } + + return ret; +} + +/******************************************************************************* +* Function Name : release_test_item_id +* Description : release test item id +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_test_item_id(PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + u16 i = 0; + if (p_test_param->p_test_item_id_set != NULL) { + if (p_test_param->p_test_item_id_set[i].p_sub_id_set != NULL) { + if (p_test_param->p_test_item_id_set[i] + .p_sub_id_set->p_id_set != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_test_param + ->p_test_item_id_set[i] + .p_sub_id_set->p_id_set); + } + ret = free_mem_in_heap_p( + (void **)&p_test_param->p_test_item_id_set[i] + .p_sub_id_set); + } + ret = free_mem_in_heap_p( + (void **)&p_test_param->p_test_item_id_set); + } + + return ret; +} + +/******************************************************************************* +* Function Name : release_raw_test_param +* Description : release rawdata test param +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_raw_test_param(PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + PST_RAWDATA_TEST_PARAM p_raw_test_param = + p_test_param->p_raw_test_param; + if (p_raw_test_param != NULL) { + /*free need check node buffer*/ + if (p_raw_test_param->p_need_check_node != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_need_check_node + ->p_data_buf); + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_need_check_node); + } + /*free special node buffer*/ + if (p_raw_test_param->p_special_node != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_special_node + ->p_data_buf); + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_special_node); + } + /*free raw limit parameter buffer*/ + if (p_raw_test_param->p_rawdata_limit != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_rawdata_limit); + } + /*free rawdata acoord limit parameter buffe*/ + if (p_raw_test_param->p_raw_accord_limit != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_raw_accord_limit); + } + /*free raw offset limit parameter buffer*/ + if (p_raw_test_param->p_raw_offset_limit != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_raw_offset_limit); + } + /*free raw jitter limit parameter buffer*/ + if (p_raw_test_param->p_raw_jitter_limit != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_raw_jitter_limit); + } + /*free raw uniform limit parameter buffer*/ + if (p_raw_test_param->p_raw_uniform_limit != NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_raw_uniform_limit); + } + /*free keydata limit parameter buffer*/ + if (p_raw_test_param->p_raw_key_limit != NULL) { + if (p_raw_test_param->p_raw_key_limit + ->p_need_check_key != NULL) { + if (p_raw_test_param->p_raw_key_limit + ->p_need_check_key->p_data_buf != + NULL) { + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param + ->p_raw_key_limit + ->p_need_check_key + ->p_data_buf); + } + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param + ->p_raw_key_limit + ->p_need_check_key); + } + ret = free_mem_in_heap_p( + (void **)&p_raw_test_param->p_raw_key_limit); + } + /*free raw test parameter*/ + ret = free_mem_in_heap_p((void **)&p_raw_test_param); + p_test_param->p_raw_test_param = NULL; + } + + return ret; +} + +/******************************************************************************* +* Function Name : release_short_test_param +* Description : release short test param +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_short_test_param(PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + PST_SHORT_PARAM p_short_param = p_test_param->p_short_param; + if (p_short_param != NULL) { + ret = free_mem_in_heap_p((void **)&p_short_param); + } + return ret; +} + +/******************************************************************************* +* Function Name : release_version_test_param +* Description : release version test param +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_version_test_param(PST_TEST_PARAM p_test_param) +{ + s32 ret = 0; + PST_VERSION_PARAM p_ver_param = NULL; + p_ver_param = p_test_param->p_version_test_param; + if (p_ver_param == NULL) { + return 1; + } + p_ver_param->p_update_bin_param = NULL; + ret = free_mem_in_heap((void *)p_ver_param); + p_test_param->p_version_test_param = NULL; + return ret; +} + +/******************************************************************************* +* Function Name : release_flash_test_param +* Description : release flash test param +* Input : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PARAM p_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_flash_test_param(PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + PST_FLASH_TEST_PARAM p_flash_param = NULL; + p_flash_param = p_test_param->p_flash_test_param; + if (p_flash_param != NULL) { + if (p_flash_param->config_arr != NULL) { + ret = free_mem_in_heap( + (void *)p_flash_param->config_arr); + } + ret = free_mem_in_heap((void *)p_flash_param); + } + return ret; +} + +/******************************************************************************* +* Function Name : release_test_param +* Description : release test param +* Input : PST_TEST_PARAM* pp_test_param +* Output : PST_TEST_PARAM* pp_test_param +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_test_param(PST_TEST_PARAM *pp_test_param) +{ + s32 ret = 1; + PST_TEST_PARAM p_test_param = NULL; + if ((pp_test_param == NULL) || ((*pp_test_param) == NULL)) { + return 1; + } + p_test_param = (*pp_test_param); + ret = release_order_config(p_test_param); + ret = release_test_item_id(p_test_param); + ret = release_raw_test_param(p_test_param); + ret = release_short_test_param(p_test_param); + ret = release_version_test_param(p_test_param); + ret = release_flash_test_param(p_test_param); + ret = free_mem_in_heap(p_test_param); + p_test_param = NULL; + return ret; +} + +/******************************************************************************* +* Function Name : decrypt_tp_order +* Description : decrypt_tp_order +* Input : s8** pp_buf(buf content)you need free memory by yourself +* Input : s2* p_len(len) +* Output : none +* Return : s32(0:ok other:error code) +*******************************************************************************/ +static s32 decrypt_tp_order(PST_TP_DEV p_tp_dev, s8 **pp_buf, u32 *p_len) +{ + s32 ret = 0; + s8 *ver = NULL; + + /*read decode order*/ + ret = read_file_decoder(p_tp_dev, &ver, pp_buf); + if (ret == 0) { + board_print_error("read file decoder error!\n"); + free_mem_in_heap(ver); + return 0; + } + /*get length of xml*/ + *p_len = strlen((cstr)*pp_buf); + + free_mem_in_heap(ver); + return ret; +} + +/******************************************************************************* +* Function Name : parse_init_param_dev +* Description : parse_init_param_dev +* Input : PST_TEST_PROC_DATA p_test_proc_data +* Output : PST_TEST_PROC_DATA p_test_proc_data +* Return : s32(0:faild 1:ok) +*******************************************************************************/ +extern int parse_test_order(PST_TEST_PARAM *pp_test_param, PST_TP_DEV p_tp_dev) +{ + s32 ret = 1; + s8 *file_content = NULL; + u32 xml_buf_len = 0; + PST_TEST_PARAM p_test_param = NULL; + + /*(1)decrypt order*/ + board_print_debug("decypt order!"); + ret = decrypt_tp_order(p_tp_dev, &file_content, &xml_buf_len); + if (ret == 0) { + free_mem_in_heap(file_content); + return 0; + } + /*(2)load xml file*/ + board_print_debug("load xml file!"); + top = mxmlLoadString(NULL, file_content, MXML_OPAQUE_CALLBACK); + if (top == NULL) { + ret = 0; + board_print_error("load xml fail!\n"); + free_mem_in_heap(file_content); + return 0; + } + /*(3)init test param struct*/ + board_print_debug("parse test param!\n"); + ret = parse_test_param(pp_test_param); + p_test_param = (PST_TEST_PARAM)(*pp_test_param); + if (ret == 0) { + goto PARSE_END; + } + /*(2)init tp ev struct*/ + ret = parse_init_dev_info(p_tp_dev, p_test_param); + if (ret == 0) { + goto PARSE_END; + } + /*judge need check node*/ + if (p_test_param->p_raw_test_param != NULL && + p_test_param->p_raw_test_param->p_need_check_node != NULL) { + if (p_test_param->p_raw_test_param->p_need_check_node->data_len < + p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num) { + board_print_error( + "need check node param error, node len in xml:%d, sc_drv_num:%d, sc_sen_num:%d\n", + p_test_param->p_raw_test_param + ->p_need_check_node->data_len, + p_tp_dev->sc_drv_num, p_tp_dev->sc_sen_num); + ret = 0; + goto PARSE_END; + } + } + +PARSE_END: + /*release xml file */ + /*mxmlDelete(top);*/ + free_mem_in_heap(file_content); + + return ret; +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.h new file mode 100644 index 000000000000..cf440a8e2b09 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_order.h @@ -0,0 +1,142 @@ +/******************** (C) COPYRIGHT 2018 Goodix ******************** +* File Name : test_order.h +* Author : +* Version : V1.0.0 +* Date : 03/05/2018 +* Description : test order info +*******************************************************************************/ +#ifndef TEST_ORDER_H +#define TEST_ORDER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "test_item_def.h" +#include "tp_open_test_param.h" +#include "tp_short_test_param.h" +#include "tp_version_test_param.h" +#include "tp_additional_option_param.h" +#include "tp_dev_def.h" +#include "mxml.h" +#include "config.h" + +/***********************************dev info**********************************/ + +#define IC_NAME_LEN 15 +#define MAX_PARAM_LEN 200 + +/***********************************test param**********************************/ + +typedef struct TEST_ITEM_ID_SET { + u16 test_id; + PST_SUB_TEST_ITEM_ID_SET p_sub_id_set; +} ST_TEST_ITEM_ID_SET, *PST_TEST_ITEM_ID_SET; + +#define MAX_TEST_NUM 20 +#define MAX_SUBTEST_NUM 10 + +typedef struct TEST_PARAM { + u8 ic_name[15]; + u16 cfg_len; + u8 *test_cfg; + u16 send_cfg_option; + u16 close_hop; /*1:need close hopping 0:do nothing*/ + u8 mode_sen_line; + /*test items*/ + u16 test_item_num; + PST_TEST_ITEM_ID_SET p_test_item_id_set; + /*rawdata test*/ + PST_RAWDATA_TEST_PARAM p_raw_test_param; + /*diffdata test*/ + PST_DIFFDATA_TEST_PARAM p_diff_test_param; + /*short test*/ + PST_SHORT_PARAM p_short_param; + /*version test*/ + PST_VERSION_PARAM p_version_test_param; + /*flash test*/ + PST_FLASH_TEST_PARAM p_flash_test_param; +} ST_TEST_PARAM, *PST_TEST_PARAM; + +typedef struct ADDR_POS_INFO { + u16 addr; + u16 package_id; /*package_id(Tx),*/ + u16 offset; /*normandy*/ + u8 lsb; /*least significant bit*/ + u8 hsb; /*high significant bit*/ +} ST_ADDR_POS_INFO, *PST_ADDR_POS_INFO; + +/*************************************Public methods start********************************************/ + +/*malloc memory for test order param*/ +extern int parse_test_order(PST_TEST_PARAM *pp_test_param, PST_TP_DEV p_tp_dev); +extern s32 release_test_order(PST_TEST_PARAM *pp_test_param); + +/*parse dev info*/ +extern s32 parse_init_dev_info(PST_TP_DEV p_tp_dev, + PST_TEST_PARAM p_test_param); + +/*init dev*/ +extern s32 header_file_init_dev(PST_TP_DEV p_tp_dev, u8 *cfg, u16 *p_cfg_len); +extern void init_dev_const_param(PST_TP_DEV p_tp_dev); +extern s32 parse_key_data(PST_TP_DEV p_tp_dev, u8 *cfg); +extern s32 parse_cfg(PST_TP_DEV p_tp_dev, u8 *cfg); +extern u32 parse_addr_from_str(PST_TP_DEV p_dev, u8 *string_info, cu8 *config); +extern u32 parse_cfg_value(PST_TP_DEV p_dev, u8 *string_info, u8 *p_config); +extern s32 get_sc_drv_sen_key_num(PST_TP_DEV p_tp_dev, u8 key_start_addr, + u8 key_en, u8 sen_as_key, u8 key_com_port_num, + u8 max_key_num); +extern s32 disable_hopping(PST_TP_DEV p_tp_dev, u8 *str_info, u8 *cfg, + u16 cfg_len); + +/*parse test param*/ +extern s32 parse_test_param(PST_TEST_PARAM *pp_test_param); +extern s32 release_test_param(PST_TEST_PARAM *pp_test_param); + +/*parse test config*/ +extern s32 parse_order_config(PST_TEST_PARAM p_test_param); +extern s32 release_order_config(PST_TEST_PARAM p_test_param); + +/*parse test item id*/ +extern s32 parse_test_item_id(PST_TEST_PARAM p_test_param); +extern s32 release_test_item_id(PST_TEST_PARAM p_test_param); + +/*parse rawdata test param*/ +extern s32 parse_raw_test_param(PST_TEST_PARAM p_test_param, + PST_SUB_TEST_ITEM_ID_SET p_sub_id_set); +extern u16 parse_need_check_node(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_need_check_key(PST_RAWDATA_TEST_PARAM p_raw_test_param, + u16 data_len); +extern s32 parse_special_node(PST_RAWDATA_TEST_PARAM p_raw_test_param, + u16 data_len); +extern s32 parse_raw_max_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_raw_min_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_accord_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_offset_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_uniform_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_jitter_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_key_max_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 parse_key_min_limit(PST_RAWDATA_TEST_PARAM p_raw_test_param); +extern s32 release_raw_test_param(PST_TEST_PARAM p_test_param); + +/*parse diffdata test param*/ +extern s32 parse_diff_test_param(PST_TEST_PARAM p_test_param); +extern s32 release_diff_test_param(PST_TEST_PARAM p_test_param); + +/*parse short test param*/ +extern s32 parse_short_test_param(PST_TEST_PARAM p_test_param); +extern s32 release_short_test_param(PST_TEST_PARAM p_test_param); + +/*parse version test param*/ +extern s32 parse_version_test_param(PST_TEST_PARAM p_test_param); +extern s32 release_version_test_param(PST_TEST_PARAM p_test_param); + +/*parse flash test param*/ +extern s32 parse_flash_test_param(PST_TEST_PARAM p_test_param); +extern s32 release_flash_test_param(PST_TEST_PARAM p_test_param); +/*************************************Public methods end********************************************/ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.c new file mode 100644 index 000000000000..b2d713de3631 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.c @@ -0,0 +1,624 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : test_param_init.h +* Author : Zhitao Yang +* Version : V1.0.0 +* Date : 12/29/2017 +* Description : initial test param +*******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +#include "test_param_init.h" +#include "test_proc.h" +#include "simple_mem_manager.h" + +#include "tp_dev_control.h" +#include "tp_open_test.h" +#include "tp_short_test.h" +#include "tp_version_test.h" +#include "tp_additional_option.h" + +#include "test_item_init.h" +#include "save_test_data.h" +#include "generic_func.h" +#include "extra_tp_control.h" +#include "tp_item_permutation.h" +#include "board_opr_interface.h" +#include + +#include "tp_normandy_control.h" + +/*static s8 s_ic_name[10] = "";*/ + +/******************************************************************************* +* Function Name : init_test_item +* Description : initial test item +* Input : PST_TEST_PROC_DATA p_test_proc_data + : PST_TEST_PARAM p_test_param +* Output : PST_TEST_PROC_DATA p_test_proc_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 init_test_item(PST_TEST_PROC_DATA p_test_proc_data, + PST_TEST_PARAM p_test_param) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_ITEM *pp_test_item_arr = NULL; + u16 item_num = 0; + + pp_test_item_arr = p_test_proc_data->pp_test_item_arr; + item_num = p_test_proc_data->test_item_num; + + for (i = 0; i < item_num; i++) { + switch (pp_test_item_arr[i]->test_item_id) { + /*----------------------tp open test-----------------------*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + ret = rawdata_test_before_func( + (p_test_proc_data->pp_test_item_arr)[i], + p_test_param); + } break; + + /*----------------------hardware test-----------------------*/ + case TP_SHORT_TEST_ITEM_ID: { + ret = short_test_before_func( + (p_test_proc_data->pp_test_item_arr)[i], + p_test_param); + } break; + + case TP_VERSION_TEST_ITEM_ID: { + ret = version_test_before_func( + (p_test_proc_data->pp_test_item_arr)[i], + p_test_param); + } break; + + /*----------------------other test-----------------------*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + ret = send_cfg_test_before_func( + (p_test_proc_data->pp_test_item_arr)[i], + p_test_param); + } break; + + case TP_RECOVER_CFG_ITEM_ID: { + ret = cfg_recover_test_before_func( + (p_test_proc_data->pp_test_item_arr)[i]); + } break; + + case TP_FLASH_TEST_ITEM_ID: { + ret = flash_test_before_func( + (p_test_proc_data->pp_test_item_arr)[i], + p_test_param); + } break; + + default: { + ; + } break; + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : register_test_item_finished_func +* Description : print test result +* Input : PST_TEST_PROC_DATA* pp_test_proc_data +* Output : PST_TEST_PROC_DATA* pp_test_proc_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 register_test_item_finished_func(PST_TEST_PROC_DATA p_test_proc_data) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_ITEM *pp_test_item_arr = NULL; + u16 item_num = 0; + pp_test_item_arr = p_test_proc_data->pp_test_item_arr; + item_num = p_test_proc_data->test_item_num; + if (pp_test_item_arr == NULL) { + return ret; + } + + for (i = 0; i < item_num; i++) { + if ((p_test_proc_data->pp_test_item_arr)[i] != NULL) { + switch (pp_test_item_arr[i]->test_item_id) { + /*----------------------tp open test-----------------------*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + pp_test_item_arr[i] + ->ptr_test_item_finished_func = + print_rawdata_test_res; + pp_test_item_arr[i] + ->ptr_test_item_finished_func_param = + (p_test_proc_data->pp_test_item_arr)[i]; + } break; + + /*----------------------hardware test-----------------------*/ + case TP_SHORT_TEST_ITEM_ID: { + pp_test_item_arr[i] + ->ptr_test_item_finished_func = + print_short_test_res; + pp_test_item_arr[i] + ->ptr_test_item_finished_func_param = + (p_test_proc_data->pp_test_item_arr)[i]; + } break; + + case TP_VERSION_TEST_ITEM_ID: { + pp_test_item_arr[i] + ->ptr_test_item_finished_func = + print_version_test_res; + pp_test_item_arr[i] + ->ptr_test_item_finished_func_param = + (p_test_proc_data->pp_test_item_arr)[i]; + } break; + + /*----------------------other test-----------------------*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + pp_test_item_arr[i] + ->ptr_test_item_finished_func = + print_send_cfg_test_res; + pp_test_item_arr[i] + ->ptr_test_item_finished_func_param = + (p_test_proc_data->pp_test_item_arr)[i]; + } break; + + case TP_RECOVER_CFG_ITEM_ID: { + pp_test_item_arr[i] + ->ptr_test_item_finished_func = + print_cfg_recover_test_res; + pp_test_item_arr[i] + ->ptr_test_item_finished_func_param = + (p_test_proc_data->pp_test_item_arr)[i]; + } break; + + case TP_FLASH_TEST_ITEM_ID: { + pp_test_item_arr[i] + ->ptr_test_item_finished_func = + print_flash_test_res; + pp_test_item_arr[i] + ->ptr_test_item_finished_func_param = + (p_test_proc_data->pp_test_item_arr)[i]; + } break; + + default: { + ; + } break; + } + } + } + return ret; +} + +/******************************************************************************* +* Function Name : release_test_item +* Description : release test item +* Input : PST_TEST_PROC_DATA* pp_test_proc_data +* Output : PST_TEST_PROC_DATA* pp_test_proc_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_test_item(PST_TEST_PROC_DATA p_test_proc_data) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_ITEM *pp_test_item_arr = NULL; + u16 item_num = 0; + pp_test_item_arr = p_test_proc_data->pp_test_item_arr; + item_num = p_test_proc_data->test_item_num; + if (pp_test_item_arr == NULL) { + return ret; + } + + for (i = 0; i < item_num; i++) { + if ((p_test_proc_data->pp_test_item_arr)[i] != NULL) { + switch (pp_test_item_arr[i]->test_item_id) { + /*----------------------tp open test-----------------------*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + ret = release_rawdata_test_item(( + p_test_proc_data->pp_test_item_arr)[i]); + } break; + + /*----------------------hardware test-----------------------*/ + case TP_SHORT_TEST_ITEM_ID: { + ret = release_short_test_item(( + p_test_proc_data->pp_test_item_arr)[i]); + } break; + + case TP_VERSION_TEST_ITEM_ID: { + ret = version_test_finished_func(( + p_test_proc_data->pp_test_item_arr)[i]); + } break; + + /*----------------------other test-----------------------*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + ret = release_cfg_test_item(( + p_test_proc_data->pp_test_item_arr)[i]); + } break; + + case TP_RECOVER_CFG_ITEM_ID: { + ret = release_cfg_recover_test_item(( + p_test_proc_data->pp_test_item_arr)[i]); + } break; + + case TP_FLASH_TEST_ITEM_ID: { + ret = release_flash_test_item(( + p_test_proc_data->pp_test_item_arr)[i]); + } break; + default: { + ; + } break; + } + } + } + return ret; +} + +/******************************************************************************* +* Function Name : init_test_proc_data +* Description : initial test proc data +* Input : PST_TEST_PROC_DATA p_test_proc_data + : PST_TEST_PARAM* pp_test_param +* Output : PST_TEST_PROC_DATA p_test_proc_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 init_test_proc_data(PST_TEST_PROC_DATA *pp_test_proc_data, + PST_TEST_PARAM *pp_test_param, void *p_drv_dev) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_PARAM p_test_param = NULL; + PST_TEST_PROC_DATA p_test_proc_data = NULL; + + /*(1)malloc memory for test proc data*/ + if (alloc_mem_in_heap((void **)pp_test_proc_data, + sizeof(ST_TEST_PROC_DATA)) == 0) { + board_print_error("test proc data malloc memory error!"); + return 0; + } + p_test_proc_data = (PST_TEST_PROC_DATA)(*pp_test_proc_data); + p_test_proc_data->p_dev = NULL; + p_test_proc_data->test_item_num = 0; + p_test_proc_data->test_break_flag = 0; + p_test_proc_data->pp_test_item_arr = NULL; + p_test_proc_data->p_test_items_before_func_ptr = NULL; + p_test_proc_data->p_test_items_finished_func_ptr = NULL; + + /*malloc memory for tp device */ + ret = alloc_mem_in_heap((void **)&p_test_proc_data->p_dev, + sizeof(ST_TP_DEV)); + if (0 == ret) { + board_print_error("tp device malloc memory error!"); + return 0; + } + p_test_proc_data->p_dev->doze_ref_cnt = 1; + p_test_proc_data->p_dev->hid_state = 1; + p_test_proc_data->p_dev->chip_type = TP_NORMANDY; + p_test_proc_data->p_dev->p_logic_dev = p_drv_dev; + + /*(4)parse test param*/ + ret = parse_test_order(pp_test_param, p_test_proc_data->p_dev); + if (ret == 0) { + board_print_error("parse test order error!\n"); + return 0; + } + p_test_param = (PST_TEST_PARAM)(*pp_test_param); + + /*(7)init test param*/ + p_test_proc_data->test_item_num = p_test_param->test_item_num; + ret = alloc_mem_in_heap((void **)&(p_test_proc_data->pp_test_item_arr), + p_test_proc_data->test_item_num * + sizeof(PST_TEST_ITEM)); + if (0 == ret) { + board_print_error("pp_test_item_arr malloc error!\n"); + return ret; + } + /*alloc memory for each varibale*/ + for (i = 0; i < p_test_proc_data->test_item_num; i++) { + ret = alloc_mem_in_heap( + (void **)(&(p_test_proc_data->pp_test_item_arr[i])), + sizeof(ST_TEST_ITEM)); + if (0 == ret) { + return ret; + } + /*init pointer in test item struct*/ + (p_test_proc_data->pp_test_item_arr)[i]->test_item_id = + p_test_param->p_test_item_id_set[i].test_id; + (p_test_proc_data->pp_test_item_arr)[i]->p_sub_id_set = + p_test_param->p_test_item_id_set[i].p_sub_id_set; + (p_test_proc_data->pp_test_item_arr)[i]->p_tp_dev = + p_test_proc_data->p_dev; + (p_test_proc_data->pp_test_item_arr)[i]->cur_data.ptr_cur_data = + NULL; + (p_test_proc_data->pp_test_item_arr)[i]->param.ptr_param = NULL; + (p_test_proc_data->pp_test_item_arr)[i]->test_res.ptr_res = + NULL; + (p_test_proc_data->pp_test_item_arr)[i]->ptr_general_func = + NULL; + (p_test_proc_data->pp_test_item_arr)[i] + ->ptr_test_item_before_func = NULL; + (p_test_proc_data->pp_test_item_arr)[i] + ->ptr_test_item_before_func_param = NULL; + (p_test_proc_data->pp_test_item_arr)[i]->ptr_test_func = NULL; + (p_test_proc_data->pp_test_item_arr)[i] + ->ptr_test_item_finished_func = NULL; + (p_test_proc_data->pp_test_item_arr)[i] + ->ptr_test_item_finished_func_param = NULL; + (p_test_proc_data->pp_test_item_arr)[i]->ptr_test_proc_data = + p_test_proc_data; + (p_test_proc_data->pp_test_item_arr)[i] + ->ptr_special_callback_data = NULL; + } + + /*register test item function*/ + ret = register_test_item_func(p_test_proc_data); + + /*register test item finish func(print test result)*/ + ret = register_test_item_finished_func(p_test_proc_data); + + /*init test item*/ + ret = init_test_item(p_test_proc_data, p_test_param); + if (ret == 0) { + board_print_error("init test item error!\n"); + return ret; + } + /*sort test item*/ + ret = sort_item_permutation(p_test_proc_data); + for (i = 0; i < p_test_proc_data->test_item_num; i++) { + board_print_debug( + "test seq:%d\n", + (p_test_proc_data->pp_test_item_arr)[i]->test_item_id); + } + + return ret; +} + +/******************************************************************************* +* Function Name : release_test_proc_data +* Description : release test proc data ,this function will be called + after changing test parameter +* Input : PST_TEST_PROC_DATA* pp_test_proc_data +* Output : PST_TEST_PROC_DATA* pp_test_proc_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 release_test_proc_data(PST_TEST_PROC_DATA *pp_test_proc_data) +{ + s32 ret = 1; + u16 i = 0; + + PST_TEST_PROC_DATA p_test_proc_data = NULL; + if ((pp_test_proc_data == NULL) || ((*pp_test_proc_data) == NULL)) { + return 1; + } + + p_test_proc_data = (*pp_test_proc_data); + ret = release_test_item(p_test_proc_data); + if (NULL != p_test_proc_data->p_dev) { + if (p_test_proc_data->p_dev->chip_type != 0xffff) { + if (p_test_proc_data->p_dev->chip_type == TP_PHOENIX) { + ret = chip_reg_write( + p_test_proc_data->p_dev, + p_test_proc_data->p_dev->cmd_set + .hid_ena_cmd.addr, + p_test_proc_data->p_dev->cmd_set + .hid_ena_cmd.cmd_buf, + p_test_proc_data->p_dev->cmd_set + .hid_ena_cmd.cmd_len); + } + } + p_test_proc_data->p_dev->p_logic_dev = NULL; + ret = free_mem_in_heap(p_test_proc_data->p_dev); + p_test_proc_data->p_dev = NULL; + } + + if (NULL != p_test_proc_data->pp_test_item_arr) { + for (i = 0; i < p_test_proc_data->test_item_num; i++) { + ret = free_mem_in_heap( + p_test_proc_data->pp_test_item_arr[i]); + p_test_proc_data->pp_test_item_arr[i] = NULL; + } + ret = free_mem_in_heap(p_test_proc_data->pp_test_item_arr); + p_test_proc_data->pp_test_item_arr = NULL; + } + ret = free_mem_in_heap(p_test_proc_data); + p_test_proc_data = NULL; + + return ret; +} + +/* test */ +/******************************************************************************* +* Function Name : test_process +* Description : test process +* Input : void* p_drv_dev +* Output : none +* Return : s32(-1:fail other:test finish) +*******************************************************************************/ +extern s32 test_process(void *p_drv_dev) +{ + s32 ret = 0; + PST_TEST_PARAM p_test_param = NULL; + PST_TEST_PROC_DATA p_test_proc_data = NULL; + + init_test_res(); /* init result as 0 before start test*/ + + /*(1)parse test order and init test proc data*/ + board_print_debug("init test proc data!\n"); + ret = init_test_proc_data(&p_test_proc_data, &p_test_param, p_drv_dev); + if (ret == 0) { + goto TEST_EXIT; + } + /*(2)start test*/ + board_print_debug("start test!\n"); + start_test_interface(p_test_proc_data); + /*(4)set test status*/ + board_print_debug("release test proc data!\n"); + ret &= stop_test_interface(p_test_proc_data); + if (get_detail_info_flag() == 0) { + } + +TEST_EXIT: + /*(5)release test proc data*/ + ret &= release_test_proc_data(&p_test_proc_data); + /*(6)release test param*/ + ret &= release_test_param(&p_test_param); + + /*(7)modify return value*/ + if (ret == 0) { + return (s32)(-1); + } + ret = get_test_res(); + board_print_debug("test_result is:%d\n", ret); + if (ret & TEST_ABORT) { + return (s32)(-1); + } + return ret; +} + +/* test*/ +/******************************************************************************* +* Function Name : get_tp_rawdata +* Description : get_tp_rawdata +* Input : void* p_drv_dev +* Output : none +* Return : s32(-1:fail other:test finish) +*******************************************************************************/ +extern int get_tp_rawdata(void *p_drv_dev, char *buf, int *buf_size) +{ + s32 ret = 0; + int offset = 0; + int r = 0, i = 0; + s32 data_tmp = 0; + u16 node_num = 0; + u8 data_size = 0; + u8 rawdata_test_id = 0; + PST_TEST_PARAM p_test_param = NULL; + PST_TEST_PROC_DATA p_test_proc_data = NULL; + PST_CUR_RAWDATA p_cur_data = NULL; + /*(1)parse test order and init test proc data*/ + board_print_debug("init get rawdata proc!\n"); + ret = init_test_proc_data(&p_test_proc_data, &p_test_param, p_drv_dev); + if (ret == 0) { + goto TEST_EXIT; + } + /*find the rawdata_test_item id for get_rawdata */ + for (i = 0; i < p_test_proc_data->test_item_num; i++) { + if (p_test_proc_data->pp_test_item_arr[i]->test_item_id == + TP_RAWDATA_TEST_ITEMS_SET_ID) { + rawdata_test_id = i; + break; + } + } + if (i == p_test_proc_data->test_item_num) { + goto TEST_EXIT; + } + node_num = p_test_proc_data->p_dev->sc_sen_num * + p_test_proc_data->p_dev->sc_drv_num; + data_size = get_data_size(p_test_proc_data->p_dev->rawdata_option); + board_print_debug("[%s]node_num = %d,data_size = %d\n", __func__, + node_num, data_size); + + if (!alloc_mem_block((void **)&(p_cur_data), sizeof(p_cur_data))) { + goto TEST_EXIT; + } + if (alloc_mem_block((void **)&(p_cur_data->p_data_buf), + node_num * data_size)) { + /*init_for_buffer*/ + for (i = 0; i < node_num * data_size; i++) { + p_cur_data->p_data_buf[i] = 0; + } + } + ret = chip_mode_select( + (p_test_proc_data->pp_test_item_arr)[rawdata_test_id]->p_tp_dev, + CHIP_RAW_DATA_MODE); + board_get_rawdata( + (p_test_proc_data->pp_test_item_arr)[rawdata_test_id]->p_tp_dev, + 3000, 0, p_cur_data); + + r = snprintf(&buf[offset], 20, "Tx:%d Rx:%d\n", + p_test_proc_data->p_dev->sc_drv_num, + p_test_proc_data->p_dev->sc_sen_num); + offset += r; + r = snprintf(&buf[offset], 2, "\n"); + offset += r; + /*end print test cfg */ + r = snprintf(&buf[offset], 20, "Rawdata:\n"); + offset += r; + board_print_debug("[%s]r = %d\n", __func__, r); + for (i = 0; i < node_num; i++) { + data_tmp = (s16)((p_cur_data->p_data_buf[i * 2]) + + (p_cur_data->p_data_buf[i * 2 + 1] << 8)); + r = snprintf(&buf[offset], 10, "%4d,", data_tmp); + offset += r; + if (((i + 1) % (p_test_proc_data->p_dev->sc_drv_num)) == 0) { + r = snprintf(&buf[offset], 2, "\n"); + offset += r; + } + } + *buf_size = offset; + ret = chip_mode_select( + (p_test_proc_data->pp_test_item_arr)[rawdata_test_id]->p_tp_dev, + CHIP_COORD_MODE); + /*get diff data end*/ + + ret &= free_mem_block((void *)p_cur_data->p_data_buf); + p_cur_data->p_data_buf = NULL; +TEST_EXIT: + ret &= free_mem_block((void *)p_cur_data); + p_cur_data = NULL; + /*(5)release test proc data*/ + ret &= release_test_proc_data(&p_test_proc_data); + /*(6)release test order*/ + ret &= release_test_param(&p_test_param); + /*(7)modify return value*/ + return offset; +} + +/* test*/ +/******************************************************************************* +* Function Name : get_tp_rawdata +* Description : get_tp_rawdata +* Input : void* p_drv_dev +* Output : none +* Return : s32(-1:fail other:test finish) +*******************************************************************************/ +extern int get_tp_testcfg(void *p_drv_dev, char *buf, int *buf_size) +{ + s32 ret = 0; + int offset = 0; + int r = 0, i = 0; + PST_TEST_PARAM p_test_param = NULL; + PST_TEST_PROC_DATA p_test_proc_data = NULL; + + /*(1)parse test order and init test proc data*/ + board_print_debug("init get rawdata proc!\n"); + ret = init_test_proc_data(&p_test_proc_data, &p_test_param, p_drv_dev); + if (ret == 0) { + goto TEST_EXIT; + } + + offset += r; + /*print test cfg */ + r = snprintf(&buf[offset], 20, "Test-config:\n"); + offset += r; + for (i = 0; i < p_test_param->cfg_len; i++) { + r = snprintf(&buf[offset], 10, "0x%2x,", + p_test_param->test_cfg[i]); + offset += r; + if ((i + 1) % 30 == 0) { + r = snprintf(&buf[offset], 2, "\n"); + offset += r; + } + } + r = snprintf(&buf[offset], 2, "\n"); + offset += r; + /*end print test cfg */ +TEST_EXIT: + /*(5)release test proc data*/ + ret &= release_test_proc_data(&p_test_proc_data); + /*(6)release test order*/ + ret &= release_test_param(&p_test_param); + /*(7)modify return value*/ + + return offset; +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.h new file mode 100644 index 000000000000..8e479c41272e --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_param_init.h @@ -0,0 +1,43 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : test_param_init.h +* Author : Zhitao Yang +* Version : V1.0.0 +* Date : 12/29/2017 +* Description : initial test data +*******************************************************************************/ + +#ifndef TEST_PARAM_INIT_H +#define TEST_PARAM_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "tp_dev_def.h" +#include "test_item_def.h" +#include "test_order.h" + +/*************************************Public methods start********************************************/ +/*init test item*/ +extern s32 init_test_item(PST_TEST_PROC_DATA p_test_proc_data, + PST_TEST_PARAM p_test_param); +extern s32 release_test_item(PST_TEST_PROC_DATA p_test_proc_data); + +/*register callback function*/ +extern s32 +register_test_item_finished_func(PST_TEST_PROC_DATA p_test_proc_data); + +/*init proc data*/ +extern s32 init_test_proc_data(PST_TEST_PROC_DATA *pp_test_proc_data, + PST_TEST_PARAM *pp_test_param, void *p_drv_dev); +extern s32 release_test_proc_data(PST_TEST_PROC_DATA *pp_test_proc_data); + +/*test process*/ +extern s32 test_process(void *p_drv_dev); +extern int get_tp_rawdata(void *p_drv_dev, char *buf, int *buf_size); +extern int get_tp_testcfg(void *p_drv_dev, char *buf, int *buf_size); +/*************************************Public methods end********************************************/ +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.c new file mode 100644 index 000000000000..2cfb700a3897 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.c @@ -0,0 +1,260 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : test_proc.c +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : structs in this file also exist in pc,it is an interface + of test item +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "test_proc.h" + +#include "tp_open_test.h" +#include "tp_short_test.h" +#include "tp_version_test.h" +#include "tp_additional_option.h" +#include "simple_mem_manager.h" +#include "tp_test_general_error_code_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* Function Name : get_arr_id_from_sub_item +* Description : get array index from sub test item array +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32(array id) +*******************************************************************************/ +extern s32 get_arr_id_from_sub_item(IN PST_TEST_ITEM p_test_item, + IN u8 sub_item_id) +{ + s32 ret = 0xFF; + u8 i = 0; + PST_SUB_TEST_ITEM_ID_SET p_sub_id_set = NULL; + p_sub_id_set = p_test_item->p_sub_id_set; + for (i = 0; i < p_sub_id_set->len; i++) { + if (p_sub_id_set->p_id_set[i] == sub_item_id) { + ret = i; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : test_proc_func +* Description : test process functiton +* Input : PST_TEST_PROC_DATA p_test_proc_data +* Output : PST_TEST_PROC_DATA p_test_proc_data +* Return : s32(0:fail 1:ok) If all functions in test_proc_func excuting ok + then the return value is 1 +*******************************************************************************/ +extern s32 test_proc_func(IN_OUT PST_TEST_PROC_DATA p_test_proc_data) +{ + u16 i = 0; + s32 res = 1; + /*off line run*/ + p_test_proc_data->test_proc_status = TEST_START; + if (NULL != p_test_proc_data->p_test_items_before_func_ptr) { + res &= p_test_proc_data->p_test_items_before_func_ptr( + p_test_proc_data->p_test_items_before_func_ptr_param); + } + /*(2)run all test items*/ + p_test_proc_data->test_proc_status = TEST_DOING; + for (i = 0; i < p_test_proc_data->test_item_num; i++) { + if (1 == p_test_proc_data->test_break_flag) { + p_test_proc_data->test_proc_status = TEST_ABORTED; + break; + } + if (NULL != p_test_proc_data->pp_test_item_arr[i] && + NULL != p_test_proc_data->pp_test_item_arr[i] + ->ptr_test_func) { + res &= p_test_proc_data->pp_test_item_arr[i] + ->ptr_test_func( + p_test_proc_data + ->pp_test_item_arr[i]); + } + } + if (1 == p_test_proc_data->test_break_flag) { + p_test_proc_data->test_proc_status = TEST_ABORTED; + } + + if (NULL != p_test_proc_data->p_test_items_finished_func_ptr) { + res &= p_test_proc_data->p_test_items_finished_func_ptr( + p_test_proc_data->p_test_items_finished_func_ptr_param); + } + p_test_proc_data->test_proc_status = TEST_FINISH; + return res; +} + +/******************************************************************************* +* Function Name : register_test_item_func +* Description : register test function.you must modify this function,while you + add some tes functions. +* Input : PST_TEST_PROC_DATA p_test_proc_data +* Output : PST_TEST_PROC_DATA p_test_proc_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 register_test_item_func(IN_OUT PST_TEST_PROC_DATA p_test_proc_data) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_ITEM *pp_test_item_arr = p_test_proc_data->pp_test_item_arr; + u16 item_num = p_test_proc_data->test_item_num; + + for (i = 0; i < item_num; i++) { + switch (pp_test_item_arr[i]->test_item_id) { + /*----------------------tp open test-----------------------*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + pp_test_item_arr[i]->ptr_test_func = + rawdata_test_sets_func; + } break; + + /*----------------------hardware test-----------------------*/ + case TP_SHORT_TEST_ITEM_ID: { + pp_test_item_arr[i]->ptr_test_func = short_test_func; + } break; + + /*----------------------firmware test-----------------------*/ + case TP_VERSION_TEST_ITEM_ID: { + pp_test_item_arr[i]->ptr_test_func = fw_version_test; + } break; + + /*----------------------other test-----------------------*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + pp_test_item_arr[i]->ptr_test_func = tp_chip_cfg_proc; + } break; + case TP_FLASH_TEST_ITEM_ID: { + pp_test_item_arr[i]->ptr_test_func = tp_flash_test; + } break; + + case TP_RECOVER_CFG_ITEM_ID: { + pp_test_item_arr[i]->ptr_test_func = + tp_recover_cfg_to_chip; + } break; + + default: { + pp_test_item_arr[i]->ptr_test_func = NULL; + } break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_test_item_from_proc_data +* Description : get test item from test proce data +* Input : PST_TEST_PROC_DATA p_test_proc_data +* Input : u16 test_item_id +* Output : PST_TEST_ITEM* pp_test_item +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 get_test_item_from_proc_data(IN PST_TEST_PROC_DATA p_test_proc_data, + IN u16 test_item_id, + OUT PST_TEST_ITEM *pp_test_item) +{ + u16 i = 0; + s32 ret = 0; + PST_TEST_ITEM *pp_test_item_arr = p_test_proc_data->pp_test_item_arr; + u16 item_num = p_test_proc_data->test_item_num; + + for (i = 0; i < item_num; i++) { + if (pp_test_item_arr[i]->test_item_id == test_item_id) { + *pp_test_item = pp_test_item_arr[i]; + ret = 1; + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : test_before_func_fail_proc +* Description : test_before_func_fail_proc +* Input : P_TEST_ITEM_RES p_test_res_head +* Output : P_TEST_ITEM_RES p_test_res_head +* Return : none +*******************************************************************************/ +extern void test_before_func_fail_proc(IN_OUT P_TEST_ITEM_RES p_test_res_head) +{ + if (p_test_res_head->test_item_err_code.len >= 1) { + p_test_res_head->test_item_err_code.ptr_err_code_set[0] = + TEST_BEFORE_FUNC_FAIL; + } + p_test_res_head->test_status = TEST_ABORTED; + p_test_res_head->test_result = TEST_NG; + board_print_error("p_test_item->ptr_test_item_before_func fail\n"); +} + +/******************************************************************************* +* Function Name : 0 == judge_test_item_legal +* Description : 0 == judge_test_item_legal +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : 1:OK 0:Fail +*******************************************************************************/ +extern s32 judge_test_item_legal(PST_TEST_ITEM p_test_item) +{ + s32 ret = 1; + + /*-----------------Judge parameter----------------*/ + if (NULL == p_test_item || NULL == p_test_item->param.ptr_param || + NULL == p_test_item->test_res.ptr_res || + NULL == p_test_item->p_tp_dev || + NULL == p_test_item->ptr_test_proc_data) { + ret = 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : start_test_interface +* Description : start test interface +* Input : ptr32 p_data(must cast to 'PST_TEST_PROC_DATA') +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 start_test_interface(IN_OUT ptr32 ptr) +{ + s32 ret = 1; + ret = test_proc_func((PST_TEST_PROC_DATA)ptr); + return ret; +} + +/******************************************************************************* +* Function Name : stop_test_interface +* Description : stop test interface +* Input : ptr32 p_data(must cast to 'PST_TEST_PROC_DATA') +* Output : ptr32 p_data +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 stop_test_interface(IN_OUT ptr32 ptr) +{ + s32 ret = 1; + u16 i = 0; + PST_TEST_PROC_DATA p_test_proc_data = (PST_TEST_PROC_DATA)ptr; + P_TEST_ITEM_RES p_test_res_header = NULL; + p_test_proc_data->test_proc_status = TEST_ABORTED; + + /*set all test item */ + for (i = 0; i < p_test_proc_data->test_item_num; i++) { + if ((NULL != p_test_proc_data->pp_test_item_arr[i]) && + (NULL != (p_test_proc_data->pp_test_item_arr[i]) + ->test_res.ptr_res)) { + p_test_res_header = + (P_TEST_ITEM_RES)(p_test_proc_data + ->pp_test_item_arr[i]) + ->test_res.ptr_res; + p_test_res_header->test_status = TEST_ABORTED; + } + } + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.h new file mode 100644 index 000000000000..fd50d756f7e7 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/test_proc.h @@ -0,0 +1,41 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : test_proc.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : structs in this file also exist in pc,it is an interface + of test item +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TEST_PROC_H +#define TEST_PROC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "test_item_def.h" +/*get array index from sub test item array*/ +extern s32 get_arr_id_from_sub_item(PST_TEST_ITEM p_test_item, u8 sub_item_id); +/*test proc func*/ +extern s32 test_proc_func(PST_TEST_PROC_DATA p_test_proc_data); +extern s32 get_test_item_by_another_item(u16 item_id, + PST_TEST_ITEM p_src_test_item, + PST_TEST_ITEM *pp_des_test_item); +extern s32 register_test_item_func(PST_TEST_PROC_DATA p_test_proc_data); +extern s32 get_test_item_from_proc_data(PST_TEST_PROC_DATA p_test_proc_data, + u16 test_item_id, + PST_TEST_ITEM *pp_test_item); + +extern void test_before_func_fail_proc(P_TEST_ITEM_RES p_test_res_head); +extern s32 judge_test_item_legal(PST_TEST_ITEM p_test_item); +/*start test interface*/ +extern s32 start_test_interface(ptr32 ptr); +/*stop test interface*/ +extern s32 stop_test_interface(ptr32 ptr); +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.c new file mode 100644 index 000000000000..806191b9da84 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.c @@ -0,0 +1,392 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_additional_option.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 10/26/2017 +* Description : this file offer some functions which are called close to test end +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "tp_additional_option.h" +#include "tp_dev_control.h" +#include "simple_mem_manager.h" +#include "tp_version_test.h" +#include "test_proc.h" +#include "tp_test_general_error_code_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* Function Name : tp_send_cfg_to_chip +* Description : tp_send_cfg_to_chip +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 tp_chip_cfg_proc(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + u16 i = 0; + PST_CHIP_CONFIG_PROC_PARAM p_param = NULL; + PST_CHIP_CONFIG_PROC_RES p_test_res = NULL; + PST_TP_DEV p_dev = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + + /*-----------------Judge parameter----------------*/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto SEN_CFG_END; + } + + p_param = (PST_CHIP_CONFIG_PROC_PARAM)p_test_item->param.ptr_param; + p_test_res = (PST_CHIP_CONFIG_PROC_RES)p_test_item->test_res.ptr_res; + p_dev = p_test_item->p_tp_dev; + + if (NULL != p_test_item->ptr_test_item_before_func) { + ret &= p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (0 == ret) { + test_before_func_fail_proc( + &p_test_res->item_res_header); + goto SEN_CFG_END; + } + } + + p_test_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = + CFG_CHECK_TEST_NONE_ERROR; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_OK; + /*clear config in res*/ + for (i = 0; i < p_test_res->cfg_len; i++) { + p_test_res->p_read_cfg[i] = 0x00; + } + + if (p_param->option == CHIP_CFG_SEND) { + /*write cfg*/ + ret &= force_update_cfg(p_dev, p_param->config, + p_param->cfg_len); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = + CFG_CHECK_TEST_UPDATE_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error( + "[send config test]update config error!\n"); + goto SEN_CFG_END; + } + } + /*read cfg*/ + if (read_cfg_arr(p_dev, p_test_res->p_read_cfg, p_test_res->cfg_len) == + 0) { + ret = 0; + } else { + ret &= 1; + } + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = CFG_CHECK_TEST_READ_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + board_print_error("[send config test]read config error!\n"); + goto SEN_CFG_END; + } + p_test_res->item_res_header.test_status = TEST_FINISH; +SEN_CFG_END: + if (p_test_item->ptr_test_item_finished_func) { + ret &= p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param); + } + return ret; +} + +/******************************************************************************* +* Function Name : tp_send_spec_cfg_to_chip +* Description : tp send spec cfg to chip +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:error 1:Ok) +*******************************************************************************/ +extern s32 tp_send_spec_cfg_to_chip(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + u16 i = 0; + PST_SPEC_CONFIG_PARAM p_param = NULL; + PST_SEND_SPEC_CONFIG_RES p_test_res = NULL; + PST_TP_DEV p_dev = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + + /*-----------------Judge parameter----------------*/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto SEN_SPC_CFG_END; + } + + p_param = (PST_SPEC_CONFIG_PARAM)p_test_item->param.ptr_param; + p_test_res = (PST_SEND_SPEC_CONFIG_RES)p_test_item->test_res.ptr_res; + p_dev = p_test_item->p_tp_dev; + + if (NULL != p_test_item->ptr_test_item_before_func) { + ret &= p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (0 == ret) { + test_before_func_fail_proc( + &p_test_res->item_res_header); + goto SEN_SPC_CFG_END; + } + } + + p_test_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = + SPEC_CONFIG_ERROR_CODE_NONE; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_OK; + /*clear config in res*/ + for (i = 0; i < p_test_res->read_cfg_len; i++) { + p_test_res->read_config[i] = 0x00; + } + + if (1 > p_test_res->read_cfg_len) { + ret = 0; + goto SEN_SPC_CFG_END; + } + /*write config to chip*/ + ret &= force_update_cfg(p_dev, p_param->config, p_param->cfg_len); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SPEC_CONFIG_UPDATE_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + board_print_error( + "[send special config]update config error!\n"); + goto SEN_SPC_CFG_END; + } + /*read config from chip*/ + if (read_cfg_arr(p_dev, p_test_res->read_config, + p_test_res->read_cfg_len) == 0) { + ret = 0; + } else { + ret &= 1; + } + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SPEC_CONFIG_READ_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + board_print_error("[send special config]read config error!\n"); + goto SEN_SPC_CFG_END; + } + /*check cfg*/ + ret &= cmp_cfg(p_dev, p_test_res->read_config, p_param->config, + p_param->cfg_len); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SPEC_CONFIG_CHECK_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + ret = 1; + board_print_info( + "[send special config]cfg is not equal with chip config!\n"); + } + p_test_res->item_res_header.test_status = TEST_FINISH; + +SEN_SPC_CFG_END: + if (p_test_item->ptr_test_item_finished_func) { + ret &= p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param); + } + return ret; +} + +/******************************************************************************* +* Function Name : tp_flash_test +* Description : tp_flash_test +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:error 1:Ok) +*******************************************************************************/ +extern s32 tp_flash_test(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + u16 i = 0; + PST_FLASH_TEST_PARAM p_param = NULL; + PST_FLASH_TEST_RES p_test_res = NULL; + PST_TP_DEV p_dev = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + + /*-----------------Judge parameter----------------*/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto FLASH_TEST_END; + } + + p_param = (PST_FLASH_TEST_PARAM)p_test_item->param.ptr_param; + p_test_res = (PST_FLASH_TEST_RES)p_test_item->test_res.ptr_res; + p_dev = p_test_item->p_tp_dev; + + if (NULL != p_test_item->ptr_test_item_before_func) { + ret &= p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (0 == ret) { + test_before_func_fail_proc( + &p_test_res->item_res_header); + goto FLASH_TEST_END; + } + } + + p_test_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = + FLASH_TEST_ERROR_CODE_NONE; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_OK; + /*clear config in res*/ + for (i = 0; i < p_test_res->cfg_len; i++) { + p_test_res->config_arr[i] = 0x00; + } + + /*Write cfg to ram*/ + if ((p_param->option & FLASH_TEST_SEND_CFG_OPT) == + FLASH_TEST_SEND_CFG_OPT) { + /*write cfg*/ + ret &= force_update_cfg(p_dev, p_param->config_arr, + p_param->cfg_len); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = + FLASH_TEST_CFG_WRITE_ERROR; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error("[flash test]update config error!\n"); + goto FLASH_TEST_END; + } + } + /*wait firmware transfer config to flash from ram*/ + if ((p_param->option & FLASH_TEST_DEFAULT_DELAY) == + FLASH_TEST_DEFAULT_DELAY) { + cfg_to_flash_delay(p_dev); + } else { + board_delay_ms(p_param->delay_time); + } + + /*Reset chip and wait firmware initialization*/ + ret &= reset_chip_proc(p_dev, RESET_TO_AP); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = FLASH_TEST_RST_FAIL_ERROR; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + goto FLASH_TEST_END; + } + /*read cfg*/ + if (read_cfg_arr(p_dev, p_test_res->config_arr, p_test_res->cfg_len) == + 0) { + ret = 0; + } else { + ret &= 1; + } + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = FLASH_TEST_CFG_READ_ERROR; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + board_print_error("[flash test]read config error!\n"); + goto FLASH_TEST_END; + } + p_test_res->item_res_header.test_status = TEST_FINISH; + +FLASH_TEST_END: + if (p_test_item->ptr_test_item_finished_func) { + ret &= p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param); + } + return ret; +} + +/******************************************************************************* +* Function Name : tp_recover_cfg_to_chip +* Description : tp_recover_cfg_to_chip +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:error 1:Ok) +*******************************************************************************/ +extern s32 tp_recover_cfg_to_chip(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + PST_RECOVER_CHIP_CFG_PARAM p_param = NULL; + PST_RECOVER_CHIP_CFG_RES p_test_res = NULL; + PST_TP_DEV p_dev = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + + /*-----------------Judge parameter----------------*/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto RECOVER_CFG_END; + } + + p_param = (PST_RECOVER_CHIP_CFG_PARAM)p_test_item->param.ptr_param; + p_test_res = (PST_RECOVER_CHIP_CFG_RES)p_test_item->test_res.ptr_res; + p_dev = p_test_item->p_tp_dev; + + if (NULL != p_test_item->ptr_test_item_before_func) { + ret &= p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (0 == ret) { + test_before_func_fail_proc( + &p_test_res->item_res_header); + goto RECOVER_CFG_END; + } + } + + p_test_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = + RECOVER_CFG_ERROR_CODE_NONE; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_OK; + + /*Write cfg to ram*/ + ret &= force_update_cfg(p_dev, p_param->config_arr, p_param->cfg_len); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = RECOVER_CFG_CFG_WRITE_ERROR; + p_test_res->item_res_header.test_result = TEST_NG; + board_print_error( + "[recover config test]update config error!\n"); + goto RECOVER_CFG_END; + } + /*read cfg*/ + if (read_cfg_arr(p_dev, p_test_res->config_arr, p_test_res->cfg_len) == + 0) { + ret = 0; + } else { + ret &= 1; + } + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = RECOVER_CFG_CFG_READ_ERROR; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + board_print_error("[recover config test]read config error!\n"); + goto RECOVER_CFG_END; + } + /*check cfg*/ + ret &= cmp_cfg(p_dev, p_test_res->config_arr, p_param->config_arr, + p_param->cfg_len); + if (0 == ret) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = RECOVER_CFG_CMP_ERROR; + p_test_res->item_res_header.test_result = TEST_NG; + ret = 1; + board_print_info( + "[recover config test]cfg is not equal with chip config!\n"); + } + p_test_res->item_res_header.test_status = TEST_FINISH; + +RECOVER_CFG_END: + if (p_test_item->ptr_test_item_finished_func) { + ret &= p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param); + } + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.h new file mode 100644 index 000000000000..11fbe427c111 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option.h @@ -0,0 +1,186 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_additional_option.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 10/26/2017 +* Description : this file offer some functions which are called close to test end +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_ADDITIONAL_OPTION_H +#define TP_ADDITIONAL_OPTION_H + +#include "board_opr_interface.h" +#include "tp_additional_option_param.h" + +#ifdef __cplusplus +extern "C" { +#endif +/******************************chip config proc*********************************/ + +#define CFG_CHECK_TEST_NONE_ERROR 0x00 +#define CFG_CHECK_TEST_UPDATE_FAIL 0x01 +#define CFG_CHECK_TEST_READ_FAIL 0x02 +#define CFG_CHECK_TEST_CHECK_FAIL 0x03 +#define CFG_SET_CHIP_COORD_MODE_FAIL 0x04 + +/*send config result*/ +typedef struct CHIP_CONFIG_PROC_RES { + ST_TEST_ITEM_RES item_res_header; + u16 cfg_len; + u8 *p_read_cfg; +} ST_CHIP_CONFIG_PROC_RES, *PST_CHIP_CONFIG_PROC_RES; + +extern s32 tp_chip_cfg_proc(ptr32 p_data); + +/*************send spec config test error code**************/ +#define SPEC_CONFIG_ERROR_CODE_NONE 0x00 +#define SPEC_CONFIG_UPDATE_FAIL 0x01 +#define SPEC_CONFIG_READ_FAIL 0x02 +#define SPEC_CONFIG_CHECK_FAIL 0x03 +/*send special config result*/ +typedef struct SEND_SPEC_CONFIG_RES { + ST_TEST_ITEM_RES item_res_header; + u16 read_cfg_len; + u8 *read_config; +} ST_SEND_SPEC_CONFIG_RES, *PST_SEND_SPEC_CONFIG_RES; + +/*************send spec config test error code**************/ + +extern s32 tp_send_spec_cfg_to_chip(ptr32 p_data); + +/**********************************flash test***********************************/ +/*flash test (TP_FLASH_TEST_ITEM_ID)*/ + +/*------------Error Code-------------*/ +#define FLASH_TEST_ERROR_CODE_NONE 0 /*test ok*/ +#define FLASH_TEST_CFG_WRITE_ERROR 1 +#define FLASH_TEST_CFG_READ_ERROR 2 +#define FLASH_TEST_RST_FAIL_ERROR 3 +#define FLASH_TEST_CMP_ERROR 4 + +/*flash test result*/ +typedef struct FLASH_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + u16 cfg_len; + u8 *config_arr; +} ST_FLASH_TEST_RES, *PST_FLASH_TEST_RES; + +extern s32 tp_flash_test(ptr32 p_data); + +/**********************************update special firmware***********************************/ +/*//update special firmware(TP_UPDATE_SPEC_FW_ITEM_ID) +//------------------Error Code--------------------//*/ +#define UPDATE_SPEC_FW_ERROR_NONE 0x00 +#define UPDATE_SPEC_FW_FAIL 0x01 + +/*flash test result*/ +typedef struct UPDATE_SPEC_FW_RES { + ST_TEST_ITEM_RES item_res_header; +} ST_UPDATE_SPEC_FW_RES, *PST_UPDATE_SPEC_FW_RES; + +extern s32 tp_update_spec_fw(ptr32 p_data); + +/**********************************custom information************************************/ +/*custom information(TP_CUSTOM_INFO_TEST_ITEM_ID)*/ + +/*--------------------Error Code----------------------*/ +#define CUSTOM_INFO_NONE_ERROR 0x00 +#define CUSTOM_INFO_WRITE_ERROR 0x01 +#define CUSTOM_INFO_READ_ERROR 0x02 +#define CUSTOM_INFO_CMP_ERROR 0x03 +#define CUSTOM_INFO_RESET_ERROR 0x04 + +/*write custom information test result*/ +typedef struct CUSTOM_INFO_RES { + ST_TEST_ITEM_RES item_res_header; + u8 info_len; + PST_CUSTOM_INFO_BYTE p_info; +} ST_CUSTOM_INFO_RES, *PST_CUSTOM_INFO_RES; + +extern s32 tp_custom_info_proc(ptr32 p_data); + +/**********************************Check Chip Test Result************************************/ +/*//TP_CHK_CHIP_TEST_RESULT_ITEM_ID +//------------------Error Code--------------------//*/ +#define CHECK_CHIP_TEST_ERROR_NONE 0x00 + +/*test result*/ +typedef struct CHECK_CHIP_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + u16 chip_test_res_info_len; + u8 *chip_test_res_info; +} ST_CHECK_CHIP_TEST_RES, *PST_CHECK_CHIP_TEST_RES; +extern s32 tp_check_chip_test_result(ptr32 p_data); + +/**********************************Check Module Test Result************************************/ +/*TP_CHK_MODULE_TEST_RESULT_ITEM_ID*/ +#define MAX_TEST_RES_LEN 8 +/*--------------------Error Code---------------------*/ +#define CHECK_MODULE_TEST_ERROR_NONE 0x00 +#define CHECK_MODULE_TEST_READ_FAIL 0x01 +#define CHECK_MODULE_TEST_RES_NG 0x02 +#define CHECK_MODULE_TEST_CHKSUM_ERROR 0x03 + +/*test result*/ +typedef struct CHECK_MODULE_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + u8 test_res_buf[MAX_TEST_RES_LEN]; + u8 test_res_buf_len; +} ST_CHECK_MODULE_TEST_RES, *PST_CHECK_MODULE_TEST_RES; +extern s32 tp_check_module_test_result(ptr32 p_data); + +/**********************************Recover Config To Chip************************************/ +/*TP_RECOVER_CFG_ITEM_ID*/ +#define RECOVER_CFG_ERROR_CODE_NONE 0 /*test ok*/ +#define RECOVER_CFG_CFG_WRITE_ERROR 1 +#define RECOVER_CFG_CFG_READ_ERROR 2 +#define RECOVER_CFG_CMP_ERROR 3 + +/*test result*/ +typedef struct RECOVER_CHIP_CFG_RES { + ST_TEST_ITEM_RES item_res_header; + u16 cfg_len; + u8 *config_arr; +} ST_RECOVER_CHIP_CFG_RES, *PST_RECOVER_CHIP_CFG_RES; +extern s32 tp_recover_cfg_to_chip(ptr32 p_data); + +/**********************************Save Result To Chip Storage************************************/ +/*//TP_SAVE_RES_TO_IC_STORAGE_ITEM_ID +//--------------------Error Code---------------------//*/ +#define SAVE_RES_TO_CHIP_ERROR_NONE 0 +#define SAVE_RES_GET_TOTAL_RES_FAIL 1 +#define SAVE_RES_WRITE_TO_CHIP_FAIL 2 + +/*test result*/ +typedef struct SAVE_RES_TO_CHIP_RES { + ST_TEST_ITEM_RES item_res_header; + u8 test_res_buf[MAX_TEST_RES_LEN]; + u8 test_res_buf_len; +} ST_SAVE_RES_TO_CHIP_RES, *PST_SAVE_RES_TO_CHIP_RES; +extern s32 tp_save_res_to_chip(ptr32 p_data); + +/**********************************Chip Uid Process************************************/ +/*//TP_CHIP_UID_PROCESS_ITEM_ID +//--------------------Error Code---------------------//*/ +#define CHIP_UID_PROC_ERROR_NONE 0 +#define CHIP_UID_PROC_READ_ERROR 1 +#define CHIP_UID_PROC_WRITE_ERROR 2 + +/*test result*/ +#define MAX_CHIP_UID_LEN 32 +typedef struct CHIP_UID_PROCESS_RES { + ST_TEST_ITEM_RES item_res_header; + u8 uid_len; + u8 uid_arr[MAX_CHIP_UID_LEN]; +} ST_CHIP_UID_PROCESS_RES, *PST_CHIP_UID_PROCESS_RES; +extern s32 tp_chip_uid_proc(ptr32 p_data); + +/*************************************Private methods start********************************************/ + +/*************************************Private methods end********************************************/ +#ifdef __cplusplus +} +#endif +#endif +#endif \ No newline at end of file diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option_param.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option_param.h new file mode 100644 index 000000000000..e7e993d0829c --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_additional_option_param.h @@ -0,0 +1,86 @@ +#ifndef TP_ADDITIONAL_OPTION_PARAM_H +#define TP_ADDITIONAL_OPTION_PARAM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "test_item_def.h" +#include "custom_info_def.h" + +/*chip config proc param*/ +#define CHIP_CFG_SEND 0x0000 +#define CHIP_CFG_CHECKED 0x0001 +typedef struct CHIP_CONFIG_PROC_PARAM { + u16 option; + u16 cfg_len; + u8 *config; +} ST_CHIP_CONFIG_PROC_PARAM, *PST_CHIP_CONFIG_PROC_PARAM; + +/****************************send special config*******************************/ +/*special config param(TP_SEND_SPEC_CFG_ITEM_ID)*/ +typedef struct SPEC_CONFIG_PARAM { + u16 cfg_len; + u8 *config; +} ST_SPEC_CONFIG_PARAM, *PST_SPEC_CONFIG_PARAM; + +/*check config param(TP_CFG_CHECK_TEST_ITEM_ID)*/ +typedef ST_CHIP_CONFIG_PROC_PARAM ST_CHECK_CONFIG_PARAM; +typedef PST_CHIP_CONFIG_PROC_PARAM PST_CHECK_CONFIG_PARAM; + +/*---------------option----------------*/ +#define FLASH_TEST_SEND_CFG_OPT 0x0001 +#define FLASH_TEST_DEFAULT_DELAY 0x0002 +typedef struct FLASH_TEST_PARAM { + u16 delay_time; + u16 option; + u16 cfg_len; + u8 *config_arr; +} ST_FLASH_TEST_PARAM, *PST_FLASH_TEST_PARAM; + +typedef struct UPDATE_SPEC_FW_PARAM { + u8 *fw_buf; + u32 fw_len; +} ST_UPDATE_SPEC_FW_PARAM, *PST_UPDATE_SPEC_FW_PARAM; + +/*--------------------Option------------------------*/ +#define CUSTOM_INFO_WRITE_OPTION 0x00 +#define CUSTOM_INFO_READ_OPTION 0x01 +#define CUSTOM_INFO_SMART_OPTION 0x02 + +typedef struct CUSTOM_INFO_PARAM { + u8 option; + u8 info_len; + PST_CUSTOM_INFO_BYTE p_info; +} ST_CUSTOM_INFO_PARAM, *PST_CUSTOM_INFO_PARAM; + +typedef struct CHECK_CHIP_TEST_PARAM { + u8 reserved1; +} ST_CHECK_CHIP_TEST_PARAM, *PST_CHECK_CHIP_TEST_PARAM; + +typedef struct CHECK_MODULE_TEST_PARAM { + u8 reserved1; +} ST_CHECK_MODULE_TEST_PARAM, *PST_CHECK_MODULE_TEST_PARAM; + +typedef struct RECOVER_CHIP_CFG_PARAM { + u16 cfg_len; + u8 *config_arr; +} ST_RECOVER_CHIP_CFG_PARAM, *PST_RECOVER_CHIP_CFG_PARAM; + +typedef struct SAVE_RES_TO_CHIP_PARAM { + u8 reserved1; +} ST_SAVE_RES_TO_CHIP_PARAM, *PST_SAVE_RES_TO_CHIP_PARAM; + +/*--------------------Option---------------------*/ +#define CHIP_UID_PROC_READ_OPT 0x00 +#define CHIP_UID_PROC_WRITE_OPT 0x01 +#define CHIP_UID_PROC_SMART_OPT 0x02 +typedef struct CHIP_UID_PROCESS_PARAM { + u8 option; +} ST_CHIP_UID_PROCESS_PARAM, *PST_CHIP_UID_PROCESS_PARAM; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_board_flash_alloc.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_board_flash_alloc.h new file mode 100644 index 000000000000..de0cdd420dfa --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_board_flash_alloc.h @@ -0,0 +1,32 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_board_flash_alloc.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : test parameter store in flash must obey this file's rules +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_BOARD_FLASH_ALLOC_H +#define TP_BOARD_FLASH_ALLOC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" + +#if ARM_CODE == 1 +#include "flash_mem_alloc_def.h" +#include "user_test_type_def.h" + +#define USER_TEST_FLASH_MEM_START_ADDR (_STORAGE_MEM_ADDR) +#define USER_TEST_FLASH_MEM_LEN (256 * 1024) + +#endif + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.c new file mode 100644 index 000000000000..5b1faed4c14a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.c @@ -0,0 +1,568 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_dev_contol.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : device control interface +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "simple_mem_manager.h" +#include "tp_dev_control.h" +#include "tp_dev_def.h" +#include "public_fun.h" +#include "tp_normandy_control.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static s32 soft_reset_chip(PST_TP_DEV p_dev); + +static s32 reset_hold_chip(PST_TP_DEV p_dev); + +static s32 chip_int_sync(PST_TP_DEV p_dev); + +/******************************************************************************* +* Function Name : chip_reg_write +* Description : write chip register +* Input : PST_TP_DEV p_dev(pointer to a touch panel deice, which should be inited before) +* Input : u16 addr(address) +* Input : s32* p_buf(data buffer) +* Input : u16 buf_len(buffer length) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 chip_reg_write(IN PST_TP_DEV p_dev, IN u16 addr, IN u8 *p_buf, + IN u16 buf_len) +{ + s32 ret = 0; + u8 retry_cnt = 3; + u8 i = 0; + + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_reg_write(p_dev, addr, p_buf, buf_len); + } break; + default: { + for (i = 0; i < retry_cnt; i++) { + ret = board_write_chip_reg(p_dev, addr, p_buf, buf_len); + if (1 == ret) { + break; + } + } + } break; + } + + return ret; +} + +/******************************************************************************* +* Function Name : chip_reg_read +* Description : read chip register +* Input : PST_TP_DEV p_dev(pointer to a touch panel deice, which should be inited before) +* Input : u16 addr(address) +* Input : s32* p_buf(data buffer) +* Input : u16 buf_len(buffer length) +* Output : s32* p_buf +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 chip_reg_read(IN PST_TP_DEV p_dev, IN u16 addr, OUT u8 *p_buf, + IN u16 buf_len) +{ + s32 ret = 0; + u8 retry_cnt = 3; + u8 i = 0; + + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_reg_read(p_dev, addr, p_buf, buf_len); + } break; + default: { + for (i = 0; i < retry_cnt; i++) { + ret = board_read_chip_reg(p_dev, addr, p_buf, buf_len); + if (1 == ret) { + break; + } + } + } break; + } + return ret; +} + +/******************************************************************************* +* Function Name : chip_reg_write_chk +* Description : write chip register and check whether writing successfully +* Input : PST_TP_DEV p_dev(pointer to a touch panel deice, which should be inited before) +* Input : u16 addr(address) +* Input : s32* p_buf(data buffer) +* Input : u16 buf_len(buffer length) +* Output : s32* p_buf +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 chip_reg_write_chk(IN PST_TP_DEV p_dev, IN u16 addr, IN u8 *p_buf, + IN u16 buf_len) +{ + s32 ret = 0; + u16 i = 0; + u8 *p_buf_read_tmp = NULL; + ret = chip_reg_write(p_dev, addr, p_buf, buf_len); + if (1 == ret) { + ret = alloc_mem_in_heap((void **)&p_buf_read_tmp, buf_len); + if (0 == ret) { + return ret; + } + ret = chip_reg_read(p_dev, addr, p_buf_read_tmp, buf_len); + if (1 == ret) { + for (i = 0; i < buf_len; i++) { + if (p_buf[i] != p_buf_read_tmp[i]) { + ret = 0; + break; + } + } + } + free_mem_in_heap(p_buf_read_tmp); + } + return ret; +} + +/******************************************************************************* +* Function Name : reset_chip +* Description : reset chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : RST_OPTION rst_opt(reset option,you can refer RST_OPTION) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 reset_chip_proc(IN PST_TP_DEV p_dev, IN RST_OPTION rst_opt) +{ + s32 ret = 0; + if (p_dev == NULL) { + return ret; + } + /* reset ap flow + // 1. reset chip 2.chip init sync 3.seek dev addr + // (1)reset chip + */ + switch (rst_opt) { + case RESET_TO_AP: { + ret = reset_chip(p_dev); + /*(2)sync int pin*/ + if (ret) { + ret = chip_int_sync(p_dev); + } + } break; + case RESET_TP_DSP: { + ret = reset_hold_chip(p_dev); + } break; + default: + break; + } + + return ret; +} + +/******************************************************************************* +* Function Name : chip_mode_select +* Description : set chip to a pointed work mode +* Input : PST_TP_DEV p_dev(pointer to a touch panel deice, which should be inited before) +* Input : s32 work_mode +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 chip_mode_select(IN PST_TP_DEV p_dev, IN u8 work_mode) +{ + s32 ret = 0; + switch (work_mode) { + case CHIP_RAW_DATA_MODE: + ret = board_enter_rawdata_mode(p_dev); + break; + case CHIP_COORD_MODE: + ret = board_enter_coord_mode(p_dev); + break; + case CHIP_SLEEP_MODE: + ret = board_enter_sleep_mode(p_dev); + break; + case CHIP_DIFF_DATA_MODE: + ret = board_enter_diffdata_mode(p_dev); + break; + default: + break; + } + return ret; +} + +/******************************************************************************* +* Function Name : reset_chip +* Description : reset chip,hardware reset or softreset +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 reset_chip(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + if (p_dev->no_rst_pin) { + ret = soft_reset_chip(p_dev); + } else { + /*(1)Judge whether use soft reset*/ + if (p_dev->use_soft_reset) { + ret = soft_reset_chip(p_dev); + } + /*(2)If soft reset fail or no use soft reset*/ + if (0 == ret) { + ret = board_hard_reset_chip(p_dev); + } + } + /*clear doze_ref_cnt,module power on initialized with doze*/ + p_dev->doze_ref_cnt = 1; + /*p_dev->hid_state = 1;*/ + + return ret; +} +/******************************************************************************* +* Function Name : wakeup_chip +* Description : wakeup chip,reset or read +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +s32 wakeup_chip(PST_TP_DEV p_dev) +{ + s32 ret = 1; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_wakeup_chip(p_dev); + } break; + default: { + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + ret = 0; + } break; + } + return ret; +} + +/******************************************************************************* +* Function Name : get_data_flag +* Description : get data flag +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:no flag 1:flag) +*******************************************************************************/ +extern s32 get_data_flag(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + u16 i = 0, retry_cnt = 15; + u8 data_temp; + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_dev, p_dev->syncflag_addr, &data_temp, 1); + if ((1 == ret) && (0 != (p_dev->syncflag_mask & data_temp))) { + ret = 1; + break; + } else { + ret = 0; + } + board_delay_ms(2); + } + return ret; +} + +/******************************************************************************* +* Function Name : clr_data_flag +* Description : clr data flag +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 clr_data_flag(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + u8 i = 0, retry_cnt = 3; + u8 buf_tmp = 0x00; + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_write(p_dev, p_dev->syncflag_addr, &buf_tmp, 1); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_warning("clr_data_flag fail"); + } + return ret; +} + +/******************************************************************************* +* Function Name : write_cfg +* Description : write config to tp chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : u8* config(the buffer store cfg) +* Input : u16 cfg_len(cfg len) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 force_update_cfg(IN PST_TP_DEV p_dev, IN u8 *config, IN u16 cfg_len) +{ + s32 ret = 0; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_force_update_cfg(p_dev, config, cfg_len); + } break; + default: { + ret = 0; + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : write_cfg +* Description : write config to tp chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : s32* cfg1 +* Input : s32* cfg2 +* Input : u16 cfg_len +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 cmp_cfg(IN PST_TP_DEV p_dev, IN u8 *cfg1, IN u8 *cfg2, + IN u16 cfg_len) +{ + s32 ret = 0; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_cmp_cfg(p_dev, cfg1, cfg2, cfg_len); + } break; + default: { + ret = 0; + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : write_cmd +* Description : write_cmd +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : u16 cmd_addr +* Input : s32 cmd_byte +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 write_cmd(IN PST_TP_DEV p_dev, IN u16 cmd_addr, IN u8 cmd_byte) +{ + s32 ret = 0; + switch (p_dev->chip_type) { + case TP_GT900: + case TP_ALTO: { + ret = chip_reg_write(p_dev, cmd_addr, &cmd_byte, 1); + } break; + + default: { + u8 buf_tmp[3]; + buf_tmp[0] = cmd_byte; + buf_tmp[1] = 0; + buf_tmp[2] = 0x100 - buf_tmp[0] - buf_tmp[1]; + ret = chip_reg_write(p_dev, cmd_addr, buf_tmp, 3); + } break; + } + return ret; +} + +/******************************************************************************* +* Function Name : write_cfg +* Description : write config to tp chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 write_cfg(IN PST_TP_DEV p_dev) +{ + return write_cfg_arr(p_dev, p_dev->cfg, p_dev->cfg_len); +} + +/******************************************************************************* +* Function Name : read_cfg +* Description : read config from tp chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : PST_TP_DEV p_dev(touch panel deice) +* Return : s32(0:fail >0:read config len) +*******************************************************************************/ +extern s32 read_cfg(IN_OUT PST_TP_DEV p_dev) +{ + return read_cfg_arr(p_dev, p_dev->cfg, p_dev->cfg_len); +} + +/******************************************************************************* +* Function Name : write_cfg_arr +* Description : write config to tp chip +* Input : PST_TP_DEV p_dev (touch panel deice) +* Input : s32* config (the buffer store cfg) +* Input : u16 cfg_len (cfg len) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 write_cfg_arr(IN PST_TP_DEV p_dev, IN u8 *config, IN u16 cfg_len) +{ + s32 ret = 0; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_write_cfg(p_dev); + } break; + default: { + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + ret = 0; + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : read_cfg +* Description : read config from tp chip +* Input : PST_TP_DEV p_dev (touch panel deice) +* Input : s32* config (the buffer store cfg) +* Input : u16 cfg_len (cfg len) +* Output : s32* config +* Return : s32(0:fail >0:read config len) +*******************************************************************************/ +extern s32 read_cfg_arr(IN PST_TP_DEV p_dev, IN_OUT u8 *config, IN u16 cfg_len) +{ + s32 ret = 0; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_read_cfg_arr(p_dev, config, cfg_len); + } break; + default: { + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + ret = 0; + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : cfg_to_flash_delay +* Description : wait cfg save to flash from ram +* Input : PST_TP_DEV p_dev(pointer to a touch panel deice, which should be inited before) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 cfg_to_flash_delay(IN PST_TP_DEV p_dev) +{ + s32 ret = 1; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + board_delay_ms(600); + } break; + default: { + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + ret = 0; + } break; + } + return ret; +} + +#ifdef __cplusplus +} +#endif + +/*************************************Private methods start********************************************/ + +/******************************************************************************* +* Function Name : soft_reset_chip +* Description : soft reset chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +s32 soft_reset_chip(IN PST_TP_DEV p_dev) +{ + s32 ret = 1; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_soft_reset_chip(p_dev); + } break; + default: { + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + ret = 0; + } break; + } + return ret; +} + +/******************************************************************************* +* Function Name : reset_hold_chip +* Description : reset hold chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 reset_hold_chip(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + switch (p_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_reset_hold_chip(p_dev); + } break; + default: { + board_print_warning( + "chip type (%d) is not exist, please check it", + p_dev->chip_type); + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : chip_int_sync +* Description : chip int pin sync +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +static s32 chip_int_sync(IN PST_TP_DEV p_dev) +{ + s32 ret = 1; + /*set gpio mode GPIO_Mode_Out_PP( if you wanna input high)*/ + board_gpio_mode_set(p_dev, TPYE_GPIO_B, MODULE_INT, Mode_Out_PP); + board_gpio_reset_bits(p_dev, TPYE_GPIO_B, MODULE_INT); + board_delay_ms(50); + board_gpio_set_bits(p_dev, TPYE_GPIO_B, MODULE_INT); + board_gpio_mode_set(p_dev, TPYE_GPIO_B, MODULE_INT, Mode_IN_FLOATING); + return ret; +} + +/*************************************Private methods end********************************************/ + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.h new file mode 100644 index 000000000000..b8f76617309a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_control.h @@ -0,0 +1,86 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_dev_contol.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : device control interface +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_DEV_CONTROL_H +#define TP_DEV_CONTROL_H + +#include "tp_dev_def.h" +#include "board_opr_interface.h" +#include "custom_info_def.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*************************************Public methods start********************************************/ +extern s32 chip_reg_write(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, u16 buf_len); +extern s32 chip_reg_read(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, u16 buf_len); +extern s32 chip_reg_write_chk(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len); + +extern s32 ctrl_chip_io(PST_TP_DEV p_dev, u16 io_id, GIOMode_Def modeType); + +/*set tp chip io state*/ +extern s32 setbit_chip_io(PST_TP_DEV p_dev, u16 io_id, GIOBit_Def bit_state); +/*get tp chip io state*/ +extern GIOBit_Def getbit_chip_io(PST_TP_DEV p_dev, u16 io_id); + +/*rst pin operation*/ +typedef enum { RESET_TO_AP = 0x00, RESET_TP_DSP = 0x01 } RST_OPTION; +extern s32 reset_chip_proc(PST_TP_DEV p_dev, RST_OPTION rst_opt); +extern s32 reset_chip(PST_TP_DEV p_dev); + +extern s32 wakeup_chip(PST_TP_DEV p_dev); + +/*int pin operation*/ +extern s32 set_chip_int_floating(PST_TP_DEV p_dev); + +enum { + CHIP_RAW_DATA_MODE, + CHIP_COORD_MODE, /*coordinate mode */ + CHIP_SLEEP_MODE, + CHIP_DIFF_DATA_MODE, +}; +extern s32 chip_mode_select(PST_TP_DEV p_dev, u8 work_mode); + +extern s32 enter_gest_doze(PST_TP_DEV p_dev); +extern s32 exit_gest_doze(PST_TP_DEV p_dev); + +/*data flag indicate there is coord data(rawdata) or not*/ +extern s32 get_data_flag(PST_TP_DEV p_dev); +extern s32 clr_data_flag(PST_TP_DEV p_dev); + +/*cfg process*/ +extern s32 write_cfg_arr(PST_TP_DEV p_dev, u8 *config, u16 cfg_len); +extern s32 read_cfg_arr(PST_TP_DEV p_dev, u8 *config, u16 cfg_len); +extern s32 write_cfg(PST_TP_DEV p_dev); +extern s32 read_cfg(PST_TP_DEV p_dev); +extern s32 force_update_cfg(PST_TP_DEV p_dev, u8 *config, u16 cfg_len); + +extern s32 cfg_to_flash_delay(PST_TP_DEV p_dev); + +extern s32 cmp_cfg(PST_TP_DEV p_dev, u8 *cfg1, u8 *cfg2, u16 cfg_len); + +/*cmd*/ +extern s32 write_cmd(PST_TP_DEV p_dev, u16 cmd_addr, u8 cmd_byte); + +#define CHECK_CHIP_TEST_RES_OK 0 +#define CHECK_CHIP_TEST_COMM_ERR 1 +#define CHECK_CHIP_TEST_CHK_SUM_ERR 2 +#define CHECK_CHIP_TEST_RES_NG 3 +#define CHECK_CHIP_TEST_QUALITY_NG 4 +extern s32 check_chip_test_res_info(PST_TP_DEV p_dev, u8 *test_res_info, + u32 len); +/*************************************Public methods end**********************************************/ + +#ifdef __cplusplus +} +#endif +/*************************************Private methods start********************************************/ /*************************************Private methods end********************************************/ +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_def.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_def.h new file mode 100644 index 000000000000..e9177180ec32 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_dev_def.h @@ -0,0 +1,176 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_dev_def.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 12/31/2017 +* Description : touch panel device define +*******************************************************************************/ +#ifndef TP_DEF_DEF_H +#define TP_DEF_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "tp_product_id_def.h" +#include "tp_micro_def.h" + +/* communication info*/ +typedef struct TP_COMM { + u8 comm_type; /* the type of communication -default i2c*/ + u8 i2c_address_num; + u8 i2c_address[TP_MAX_I2C_ADDRESS_NUM]; /*127*/ + u8 dev_address; /* seek i2c address*/ + u8 dev_fix_address; /* fixed address*/ +} ST_TP_COMM, *PST_TP_COMM; + +/*device command define*/ +typedef struct TP_DEV_CMD { + u16 addr; + u8 cmd_len; + u8 cmd_buf[TP_DEV_CMD_LEN]; +} ST_TP_DEV_CMD, *PST_TP_DEV_CMD; +/*cmd set*/ +typedef struct TP_DEV_CMD_SET { + ST_TP_DEV_CMD rawdata_cmd; + ST_TP_DEV_CMD diffdata_cmd; + ST_TP_DEV_CMD coorddata_cmd; + ST_TP_DEV_CMD sleep_cmd; + ST_TP_DEV_CMD hid_ena_cmd; + ST_TP_DEV_CMD hid_dis_cmd; + ST_TP_DEV_CMD enter_gest_cmd; + +} ST_TP_DEV_CMD_SET, *PST_TP_DEV_CMD_SET; + +/*data option*/ +#define _DATA_BIT_8 0x01 +#define _DATA_BIT_16 0x02 +#define _DATA_BIT_32 0x04 +#define _DATA_BIT_64 0x08 +#define _DATA_DRV_SEN_INVERT 0x10 +#define _DATA_SIGNED 0x40 +#define _DATA_LARGE_ENDIAN 0x80 + +/*touch panel device define*/ +typedef struct TP_DEV { + /* COMM*/ + PST_TP_COMM p_tp_comm; + ptr32 p_logic_dev; /*use in pc code,arm code equeal null*/ + + u16 chip_type; /* chip type*/ + u16 chip_sub_type; /* chip sub type*/ + + /*voltage setting*/ + u16 power_volt; /* mV*/ + u16 comm_volt; /* mV */ + + /*cfg*/ + u16 cfg_start_addr; + u16 ext_cfg_addr; + u16 ext_cfg_len; + u16 cfg_len; /*if ext_cfg_len != 0 then cfg_len = base_cfg_len + ext_cfg_len*/ + u8 cfg[TP_MAX_CFG_LEN]; + + u8 use_soft_reset; /* 1 use soft reset first */ + u8 no_rst_pin; /* 1 no rst pin 0 has rst pin default 0*/ + + /* max sensor and driver num for die*/ + u8 max_sen_num_in_die; + u8 max_drv_num_in_die; + + /* max sensor and driver num for this chip*/ + u8 max_sen_num; + u8 max_drv_num; + + /* current sensor num and driver(include key channel)*/ + u8 total_sen_num; + u8 total_drv_num; + + /*screen sensor num and driver(exclude key channel)*/ + u8 sc_sen_num; + u8 sc_drv_num; + u16 sen_start_addr; + u16 drv_start_addr; + u16 sen1_start_addr; /*have two G1 use,eg Phoenix*/ + u16 drv1_start_addr; /*have two G1 use,eg Phoenix*/ + /*channel map*/ + u8 map_disable; + u8 drv_map[TP_MAX_CHN_NUM]; + u8 sen_map[TP_MAX_CHN_NUM]; + u8 pack_drv_2_adc_map[TP_MAX_CHN_NUM]; + u8 pack_sen_2_adc_map[TP_MAX_CHN_NUM]; + u8 chn_map[TP_MAX_CHN_NUM]; + + /* key*/ + u8 key_num; + u8 key_rawdata_num; + u8 key_pos_arr[TP_MAX_KEY_NUM]; + + /* cmd */ + u16 seek_reg_addr; + + u16 real_cmd_addr; /*this field may be same as fields in cmd_set*/ + ST_TP_DEV_CMD_SET cmd_set; + + u16 rawdata_addr; + u16 rawdata_len; + u8 rawdata_option; + + u16 diffdata_addr; + u16 diffdata_len; + u8 diffdata_option; + + u16 basedata_addr; + u16 basedata_len; + u8 basedata_option; + + u16 syncflag_addr; + u16 syncflag_mask; + u16 coordchk_sum; + + /*in GT900/GT9P/GT9L this address is u16,in Phoenix/Normandy this address is u32*/ + u32 custom_info_addr; + u8 custom_info_len; + + u32 module_test_res_addr; + u8 module_test_res_len; + + u32 uid_addr; + u8 uid_len; + + u32 chip_test_res_addr; + u16 chip_test_res_len; + + /* general flash protocol*/ + u32 flash_rw_cmd_addr; + u8 flash_read_cmd_byte; + u8 flash_write_cmd_byte; + u8 flash_send_cmd_end_byte; + + u32 flash_rw_sta_addr; + u8 flash_rw_ok_sta_byte; + u8 flash_rw_fail_sta_byte; + u8 flash_enter_rw_sta_byte; + u8 flash_chk_sum_err_sta_byte; + u8 flash_erase_fail_sta_byte; + u8 flash_write_fail_sta_byte; + u8 flash_read_fail_sta_byte; + u8 flash_access_fail_sta_byte; + u8 flash_clr_sta_byte; + u8 flash_rw_available; + u8 b_flash_big_endian; + + u32 flash_rw_switch_buf_addr; + u32 flash_max_data_size; + u32 flash_page_size; + + u8 doze_ref_cnt; /*1:doze mode 0:exit doze*/ + u8 hid_state; /*1:state of enable hid 0:state of disable hid*/ + +} ST_TP_DEV, *PST_TP_DEV; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.c new file mode 100644 index 000000000000..06458b79dc96 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.c @@ -0,0 +1,123 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : test_proc.c +* Author : Bob Huang +* Version : V1.0.0 +* Date : 02/06/2018 +* Description : Sort item +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "tp_item_permutation.h" +#include "board_opr_interface.h" + +/*-----------------------------static variable-------------------------------*/ +const static u16 cs_item_permutation[] = { + TP_CHK_CHIP_TEST_RESULT_ITEM_ID, + TP_CHK_MODULE_TEST_RESULT_ITEM_ID, + TP_I2C_VOLT_TEST_ITEM_ID, + TP_INT_VOLT_TEST_ITEM_ID, + TP_INT_CAP_TEST_ITEM_ID, + TP_RST_VOLT_TEST_ITEM_ID, + TP_PIN1_TEST_ITEM_ID, + TP_PIN2_TEST_ITEM_ID, + TP_CHIP_UID_PROCESS_ITEM_ID, + TP_VERSION_TEST_ITEM_ID, + TP_CHK_FW_RUN_STATE_ITEM_ID, + TP_CUSTOM_INFO_TEST_ITEM_ID, + TP_MODULE_TYPE_TEST_ITEM_ID, + TP_CHIP_CFG_PROC_ITEM_ID, + TP_GESTURE_TEST_ITEM_ID, + TP_SLEEP_CURRENT_TEST_ITEM_ID, + TP_FLASH_TEST_ITEM_ID, + TP_SHORT_TEST_ITEM_ID, + TP_ACTIVE_CURRENT_TEST_ITEM_ID, + TP_RAWDATA_TEST_ITEMS_SET_ID, + TP_DIFFDATA_TEST_ITEMS_SET_ID, + TP_LINE_TEST_ITEM_ID, + TP_KEY_TOUCH_TEST_ITEM_ID, + TP_RECOVER_CFG_ITEM_ID, + TP_UPDATE_SPEC_FW_ITEM_ID, + TP_SEND_SPEC_CFG_ITEM_ID, + TP_SAVE_RES_TO_IC_STORAGE_ITEM_ID, + TP_TEST_ITEM_END_ID, +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* Function Name : get_index_from_permutaion_arr +* Description : sort item get_index_from_permutaion_arr +* Input : u16 item_id +* Output : none +* Return : s32(index) +*******************************************************************************/ +extern s32 get_index_from_permutaion_arr(IN u16 item_id) +{ + s32 index_ret = -1; + s32 arr_size = sizeof(cs_item_permutation); + s32 i = 0; + for (i = 0; + i < arr_size && cs_item_permutation[i] != TP_TEST_ITEM_END_ID; + i++) { + if (cs_item_permutation[i] == item_id) { + index_ret = i; + break; + } + } + return index_ret; +} + +/******************************************************************************* +* Function Name : sort_item_permutation +* Description : sort item permutation +* Input : PST_TEST_PROC_DATA p_test_proc_data +* Output : PST_TEST_PROC_DATA p_test_proc_data +* Return : s32(1:ok 0:fail) +*******************************************************************************/ +extern s32 sort_item_permutation(IN_OUT PST_TEST_PROC_DATA p_test_proc_data) +{ + s32 ret = 1; + s32 i = 0, j = 0; + s32 item_cnt = 0; + s32 index1 = -1, index2 = -1; + PST_TEST_ITEM p_item_tmp = NULL; + if (NULL != p_test_proc_data) { + item_cnt = p_test_proc_data->test_item_num; + for (i = 0; i < item_cnt; i++) { + for (j = i + 1; j < item_cnt; j++) { + index1 = get_index_from_permutaion_arr( + p_test_proc_data->pp_test_item_arr[i] + ->test_item_id); + index2 = get_index_from_permutaion_arr( + p_test_proc_data->pp_test_item_arr[j] + ->test_item_id); + if (-1 == index1 || -1 == index2) { + board_print_error( + "%s\n", + "can not find test item!"); + } + if (index1 != -1 && index2 != -1 && + index1 > index2) { + p_item_tmp = + p_test_proc_data + ->pp_test_item_arr[i]; + p_test_proc_data->pp_test_item_arr[i] = + p_test_proc_data + ->pp_test_item_arr[j]; + p_test_proc_data->pp_test_item_arr[j] = + p_item_tmp; + } + } + } + ret = 1; + } + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.h new file mode 100644 index 000000000000..ac6544bbf266 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_item_permutation.h @@ -0,0 +1,27 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : test_proc.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : structs in this file also exist in pc,it is an interface + of test item +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_ITEM_PERMUTATION_H +#define TP_ITEM_PERMUTATION_H + +#include "test_item_def.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*sort item permutation */ +extern s32 sort_item_permutation(PST_TEST_PROC_DATA p_test_proc_data); +extern s32 get_index_from_permutaion_arr(u16 item_id); + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_micro_def.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_micro_def.h new file mode 100644 index 000000000000..b4f7cffadd3c --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_micro_def.h @@ -0,0 +1,64 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_micro_def.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 12/31/2017 +* Description : touch panel device define +*******************************************************************************/ +#ifndef TP_MICRO_DEF_H +#define TP_MICRO_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "tp_product_id_def.h" + +#define TP_MAX_KEY_NUM (15) +#define TP_MAX_SEN_NUM (152) +#define TP_MAX_DRV_NUM (152) +#define TP_MAX_CHN_NUM (TP_MAX_SEN_NUM + TP_MAX_DRV_NUM) +#define TP_MAX_NODE_NUM (TP_MAX_SEN_NUM * TP_MAX_DRV_NUM) + +#define TP_MAX_BIN_SIZE (256 * 1024) +#define TP_MAX_SHORT_BIN_SIZE (128 * 1024) +#define TP_MAX_SHORT_OPT_PARAM_SIZE (256) +#define TP_MAX_OPT_MESS_SIZE (2 * 1024) + +#define TP_MAX_CUSTOM_INFO_SIZE (64) + +#define TP_MAX_NC_LEN (TP_MAX_SEN_NUM * TP_MAX_DRV_NUM) +#define TP_MAX_KEY_NC_LEN (TP_MAX_KEY_NUM * TP_MAX_CHN_NUM) + +#define TP_FLAG_NEED_CHECK (0x01) +#define TP_FLAG_NOT_NEED_CHECK (!TP_FLAG_NEED_CHECK) +#define TP_FLAG_KEY_NEED_CHECK (0x01) +#define TP_FLAG_KEY_NOT_NEED_CHECK (!TP_FLAG_KEY_NEED_CHECK) + +/*need move to other place*/ +#define TP_INVALID_SNODE (0xFFFF) + +/*cfg pack num*/ +#define TP_MAX_CFG_PACK_NUM (100) + +/* cfg length*/ +#define TP_MAX_CFG_LEN (2048) +#define TP_MAX_I2C_ADDRESS_NUM (127) +#define TP_MAX_CMD_LEN (10) +#define TP_DEV_CMD_LEN (3) + +#define TP_MAX_TOUCH_NUM (10) +#define TP_MAX_INT_MODE_NUM (4) + +/*channel define */ +#define GT_9P_DRV_NUM_MAX (32) +#define GT_9P_SEN_NUM_MAX (32) + +#define GT_9PT_DRV_NUM_MAX GT_9P_DRV_NUM_MAX +#define GT_9PT_SEN_NUM_MAX GT_9P_SEN_NUM_MAX + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.c new file mode 100644 index 000000000000..49576593d2af --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.c @@ -0,0 +1,692 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_normandy_control.cpp +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : normandy device control interface +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "tp_normandy_control.h" +#include "board_opr_interface.h" +#include "tp_dev_control.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*************************************Private methods start********************************************/ +static s32 normandy_hold_dsp(PST_TP_DEV p_dev); +/*************************************Private methods End********************************************/ + +/******************************************************************************* +* Function Name : normandy_reg_write +* Description : write chip register +* Input : PST_TP_DEV p_dev(pointer to a touch panel deice, which should be initialized before) +* Input : u16 addr(address) +* Input : u32* p_buf(data buffer) +* Input : u16 buf_len(buffer length) +* Output : none +* Return : u32(1:ok 0:fail) +*******************************************************************************/ +extern s32 normandy_reg_write(IN PST_TP_DEV p_dev, IN u16 addr, IN u8 *p_buf, + IN u16 buf_len) +{ + s32 ret = 0; + u8 retry_cnt = 3; + u8 i = 0; + ret = normandy_doze_mode(p_dev, 0, 0); + if (0 == ret) { + board_print_error( + "[normandy_reg_write]normandy_doze_mode(p_dev,0,0) fail!\n"); + return ret; + } + + for (i = 0; i < retry_cnt; i++) { + ret = board_write_chip_reg(p_dev, addr, p_buf, buf_len); + if (1 == ret) { + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : normandy_reg_read +* Description : read chip register +* Input : PST_TP_DEV p_dev(pointer to a touch panel deice, which should be inited before) +* Input : u16 addr(address) +* Input : u32* p_buf(data buffer) +* Input : u16 buf_len(buffer length) +* Output : none +* Return : u32(1:ok 0:fail) +*******************************************************************************/ +extern s32 normandy_reg_read(IN PST_TP_DEV p_dev, IN u16 addr, IN_OUT u8 *p_buf, + IN u16 buf_len) +{ + s32 ret = 0; + u8 retry_cnt = 3; + u8 i = 0; + ret = normandy_doze_mode(p_dev, 0, 0); + if (0 == ret) { + board_print_error( + "[normandy_reg_read]normandy_doze_mode(p_dev,0,0) fail!\n"); + return ret; + } + for (i = 0; i < retry_cnt; i++) { + ret = board_read_chip_reg(p_dev, addr, p_buf, buf_len); + if (1 == ret) { + break; + } + } + return ret; +} +/******************************************************************************* +* Function Name : normandy_wakeup_chip +* Description : normandy wakeup chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_wakeup_chip(PST_TP_DEV p_dev) +{ + return reset_chip_proc(p_dev, RESET_TO_AP); +} +/******************************************************************************* +* Function Name : normandy_soft_reset_chip +* Description : normandy soft reset chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_soft_reset_chip(IN PST_TP_DEV p_dev) +{ + s32 ret = 1; + u8 i = 0, retry_cnt = 3; + u8 hold_reg_val = 0x01; + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_write(p_dev, 0x4180, &hold_reg_val, 1); + if (1 == ret) { + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : normandy_reset_hold_chip +* Description : normandy reset hold chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_reset_hold_chip(IN PST_TP_DEV p_dev) +{ + s32 ret = 0; + /* (3) reset ic*/ + ret = board_hard_reset_chip(p_dev); + if (1 == ret) { + ret = normandy_hold_dsp(p_dev); + } + return ret; +} + +/******************************************************************************* +* Function Name : normandy_force_update_cfg +* Description : force update cfg (version) +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : u16 cfg_len +* Output : OUT u8* config +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_force_update_cfg(IN PST_TP_DEV p_dev, IN u8 *config, + IN u16 cfg_len) +{ + s32 ret = 0; + u8 ver_tmp = 0; + u8 i = 0; + u8 retry_cnt = 3; + + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_dev, p_dev->cfg_start_addr, &ver_tmp, 1); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "%s\n", + "[normandy_force_update_cfg],read cfg version fail"); + goto UPDATE_CFG_END; + } + if (config[0] < ver_tmp && config[0] != 0) { + config[0] = 0xFF; + } + + for (i = 0; i < retry_cnt; i++) { + normandy_cfg_update_chksum(config, cfg_len); + ret = normandy_write_cfg_arr(p_dev, config, cfg_len); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error("%s\n", + "[normandy_force_update_cfg],write cfg fail"); + goto UPDATE_CFG_END; + } + +UPDATE_CFG_END: + return ret; +} + +/******************************************************************************* +* Function Name : normandy_write_cfg +* Description : normandy write config to tp chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_write_cfg(IN_OUT PST_TP_DEV p_dev) +{ + return normandy_write_cfg_arr(p_dev, p_dev->cfg, p_dev->cfg_len); +} + +/******************************************************************************* +* Function Name : normandy_read_cfg +* Description : read config from tp normandy chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : PST_TP_DEV p_dev(touch panel deice) +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_read_cfg(IN_OUT PST_TP_DEV p_dev) +{ + return normandy_read_cfg_arr(p_dev, p_dev->cfg, p_dev->cfg_len); +} + +/******************************************************************************* +* Function Name : normandy_write_cfg_arr +* Description : write config from tp normandy chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : u32* config +* Input : u16 cfg_len +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_write_cfg_arr(IN PST_TP_DEV p_dev, IN u8 *config, + IN u16 cfg_len) +{ + s32 ret = 1; + u8 buf_arr[10]; + u8 retry_cnt = 10; + u8 retry_cnt1 = 10; + u8 i = 0; + u8 j = 0; + u8 tmp_write_cmd = 0; + u8 write_wait_cmd = 0; + + /*----------------------------------------enter idle ------------------------------------------*/ + buf_arr[0] = 0xFF; + buf_arr[1] = 0x00; + buf_arr[2] = 0x100 - buf_arr[0] - buf_arr[1]; + ret = chip_reg_write(p_dev, p_dev->real_cmd_addr, buf_arr, 3); + if (0 == ret) { + board_print_error("%s\n", "write 0xFF to real_cmd_addr fail!"); + goto READ_END; + } + /*----------------------------------------scan idle status------------------------------------------*/ + for (i = 0; i < retry_cnt; i++) { + buf_arr[0] = 0x00; + ret = chip_reg_read(p_dev, p_dev->real_cmd_addr, buf_arr, 1); + if (1 == ret && 0xFF == buf_arr[0]) { + break; + } else { + ret = 0; + } + board_delay_ms(10); + } + if (0 == ret) { + board_print_error("%s\n", "fail to wait idle status!"); + goto READ_END; + } + + /*-------------------------------------send write cfg cmd--------------------------------------*/ + if (cfg_len > 32) { + tmp_write_cmd = 0x80; + write_wait_cmd = 0x82; + } else { + tmp_write_cmd = 0x81; + write_wait_cmd = 0x81; + } + retry_cnt = 3; + for (i = 0; i < retry_cnt; i++) { + /*send write cfg cmd*/ + buf_arr[0] = tmp_write_cmd; + buf_arr[1] = 0x00; + buf_arr[2] = 0x100 - buf_arr[0] - buf_arr[1]; + ret = chip_reg_write(p_dev, p_dev->real_cmd_addr, buf_arr, 3); + if (1 == ret) { + board_delay_ms(50); + /*wait ready status*/ + retry_cnt1 = 50; + for (j = 0; j < retry_cnt1; j++) { + buf_arr[0] = 0x00; + ret = chip_reg_read(p_dev, p_dev->real_cmd_addr, + buf_arr, 1); + if (1 == ret && write_wait_cmd == buf_arr[0]) { + break; + } else { + ret = 0; + } + board_delay_ms(10); + } + if (ret == 1) { + break; + } + } else if (i == retry_cnt - 1) { + board_print_error("fail to send write cfg cmd!"); + return 0; + } + } + if ((0 == ret) && (j >= retry_cnt1)) { + board_print_error("%s\n", "fail to wait ready status!"); + goto READ_END; + } + + /*-------------------------------------- write cfg ------------------------------------------*/ + retry_cnt = 3; + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_write(p_dev, p_dev->cfg_start_addr, config, + cfg_len); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error("%s\n", "fail to write cfg!"); + goto READ_END; + } + /*---------------------------------notify write completion------------------------------------*/ + buf_arr[0] = 0x83; + buf_arr[1] = 0x00; + buf_arr[2] = 0x100 - buf_arr[0] - buf_arr[1]; + ret = chip_reg_write(p_dev, p_dev->real_cmd_addr, buf_arr, 3); + if (0 == ret) { + board_print_error("%s\n", + "fail to notify write cfg completion!"); + goto READ_END; + } + /*---------------------------------wait idle------------------------------------*/ + board_delay_ms(50); + retry_cnt = 3; + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_dev, p_dev->real_cmd_addr, buf_arr, 1); + if (1 == ret && 0xFF == buf_arr[0]) { + break; + } else { + ret = 0; + } + board_delay_ms(1); + } + if (0 == ret) { + board_print_error("%s\n", "fail to wait idle status!"); + goto READ_END; + } + p_dev->doze_ref_cnt = 1; + /*for fw store config to fresh*/ + board_delay_ms(50); +READ_END: + return ret; +} + +/******************************************************************************* +* Function Name : normandy_read_cfg_arr +* Description : read config from tp normandy chip +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : u16 cfg_len +* Output : u8* config +* Return : s32(0:fail >0:read cfg len) +*******************************************************************************/ +extern s32 normandy_read_cfg_arr(IN PST_TP_DEV p_dev, IN_OUT u8 *config, + IN u16 cfg_len) +{ + s32 ret = 1; + u8 buf_arr[10]; + u8 retry_cnt = 10; + u8 retry_cnt1 = 0; + u8 i = 0; + u8 j = 0; + u8 sub_bags = 0; + u16 offset = 0; + /*enter idle */ + buf_arr[0] = 0xFF; + buf_arr[1] = 0x00; + buf_arr[2] = 0x100 - buf_arr[0] - buf_arr[1]; + board_print_debug("start read cfg!"); + ret = chip_reg_write(p_dev, p_dev->real_cmd_addr, buf_arr, 3); + if (0 == ret) { + board_print_error("%s\n", "write 0xFF to real_cmd_addr fail!"); + return 0; + } + /*scan idle status*/ + for (i = 0; i < retry_cnt; i++) { + buf_arr[0] = 0x00; + ret = chip_reg_read(p_dev, p_dev->real_cmd_addr, buf_arr, 1); + if (1 == ret && 0xFF == buf_arr[0]) { + break; + } else { + ret = 0; + } + board_delay_ms(10); + } + if (0 == ret) { + board_print_error("%s\n", "fail to wait idle status!"); + return 0; + } + + retry_cnt = 5; + for (i = 0; i < retry_cnt; i++) { + /*send read cfg cmd*/ + buf_arr[0] = 0x86; + buf_arr[1] = 0x00; + buf_arr[2] = 0x100 - buf_arr[0] - buf_arr[1]; + ret = chip_reg_write(p_dev, p_dev->real_cmd_addr, buf_arr, 3); + if (ret == 1) { + ret = 0; + /*wait for firmware ready for reading cfg*/ + retry_cnt1 = 50; + for (j = 0; j < retry_cnt1; j++) { + buf_arr[0] = 0x00; + ret = chip_reg_read(p_dev, p_dev->real_cmd_addr, + buf_arr, 1); + if (1 == ret && 0x85 == buf_arr[0]) { + break; + } else { + ret = 0; + } + board_delay_ms(10); + } + if (ret == 1) { + break; + } + } else if (i == retry_cnt - 1) { + board_print_error("fail to send read cfg end!"); + return 0; + } + } + if ((0 == ret) && (j >= retry_cnt1)) { + board_print_error( + "%s\n", + "fail to wait for firmware ready for reading cfg!"); + return 0; + } + + /*read cfg*/ + retry_cnt = 3; + if (cfg_len == 0) { /*config len is not known*/ + /*read config head*/ + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_dev, p_dev->cfg_start_addr, + config, 4); + if (ret == 1) { + break; + } + } + if (0 == ret) { + board_print_error("%s\n", "fail to read cfg head!"); + return 0; + } + /*read sub bugs*/ + sub_bags = config[2]; + offset = 4; + for (j = 0; j < sub_bags; j++) { + /*read sub bags head*/ + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read( + p_dev, p_dev->cfg_start_addr + offset, + config + offset, 2); + if (ret == 1) { + break; + } + } + if (0 == ret) { + board_print_error( + "fail to read cfg sub bug %d head!\n", + j); + return 0; + } + /*read sub bugs*/ + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_dev, + p_dev->cfg_start_addr + + offset + 2, + config + offset + 2, + config[offset + 1] + 1); + if (ret == 1) { + break; + } + } + if (0 == ret) { + board_print_error( + "fail to read cfg sub bug %d!\n", j); + return 0; + } + board_print_debug("read sub bug %d offset is %d\n", j, + offset); + offset += config[offset + 1] + 3; + } + cfg_len = offset; + board_print_debug("chip cfg len: %d\n", cfg_len); + + } else { + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_dev, p_dev->cfg_start_addr, + config, cfg_len); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error("%s\n", "fail to read cfg!"); + return 0; + } + } + + /*write idle cmd*/ + buf_arr[0] = 0xFF; + buf_arr[1] = 0x00; + buf_arr[2] = 0x100 - buf_arr[0] - buf_arr[1]; + ret = chip_reg_write(p_dev, p_dev->real_cmd_addr, buf_arr, 3); + if (0 == ret) { + board_print_error("%s\n", "fail to write idle cmd!"); + return 0; + } + + return cfg_len; +} + +/******************************************************************************* +* Function Name : normandy_cfg_update_chksum +* Description : update check sum +* Input : u32* config +* Input : u16 cfg_len +* Output : u8* config +* Return : none +*******************************************************************************/ +extern void normandy_cfg_update_chksum(IN_OUT u8 *config, IN u16 cfg_len) +{ + u16 pack_map_len_arr[100]; + u16 packNum = 0; + u16 pack_len_tmp = 0; + u16 pack_id_tmp = 0; + u16 i = 0, j = 0; + u16 cur_pos = 0; + u8 check_sum = 0; + + if (cfg_len < 4) + return; + + pack_map_len_arr[pack_id_tmp] = 4; + packNum = config[2]; + for (i = 4; i < cfg_len;) { + pack_id_tmp++; + pack_len_tmp = config[i + 1] + 3; + pack_map_len_arr[pack_id_tmp] = pack_len_tmp; + i += pack_len_tmp; + } + + cur_pos = 0; + for (i = 0; i <= pack_id_tmp; i++) { + check_sum = 0; + for (j = cur_pos; j < cur_pos + pack_map_len_arr[i] - 1; j++) { + check_sum += config[j]; + } + config[cur_pos + pack_map_len_arr[i] - 1] = (u8)(0 - check_sum); + cur_pos += pack_map_len_arr[i]; + } +} + +/******************************************************************************* +* Function Name : normandy_cmp_cfg +* Description : normandy_cmp_cfg +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : u32* cfg1 +* Input : u32* cfg2 +* Input : u16 cfg_len +* Output : OUT u8* config +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_cmp_cfg(IN PST_TP_DEV p_dev, IN u8 *cfg1, IN u8 *cfg2, + IN u16 cfg_len) +{ + s32 ret = 1; + u16 i = 0; + for (i = 0; i < cfg_len; i++) { + if (0 == i || 1 == i || 3 == i) /*|| + //cfg_len - 1 == i)*/ + { + continue; + } + if (cfg1[i] != cfg2[i]) { + ret = 0; + break; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : normandy_doze_mode +* Description : normandy_doze_mode +* Input : PST_TP_DEV p_dev(touch panel deice) +* Input : u32 b_ena +* Input : u32 b_force +* Output : none +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +extern s32 normandy_doze_mode(IN PST_TP_DEV p_dev, IN u8 b_ena, IN u8 b_force) +{ + s32 ret = 1; + u8 temp_data = 0; + u8 temp_read = 0; + u8 i = 0; + u8 j = 0; + u8 retry_cnt = 20; + if (b_ena) { /*enter doze*/ + + if (p_dev->doze_ref_cnt == 0 || b_force) { + temp_data = 0xCC; + for (i = 0; i < retry_cnt; i++) { + ret = board_write_chip_reg(p_dev, 0x30f0, + &temp_data, 1); + if (1 == ret) { + break; + } + board_delay_ms(1); + } + if (1 == ret && 0 == p_dev->doze_ref_cnt) { + p_dev->doze_ref_cnt++; + } + if (0 == ret) { + board_print_error( + "%s\n", + "[normandy_doze_mode]board_write_chip_reg 0xCC in 0x30f0 fail!"); + } + } + } else { /*exit doze*/ + + if (p_dev->doze_ref_cnt == 1 || b_force) { + for (i = 0; i < retry_cnt; i++) { + if (0xAA != + temp_read) { /*only 0x3100 is not 0xAA and need write 0x30f0 0xAA */ + temp_data = 0xAA; + ret = board_write_chip_reg( + p_dev, 0x30f0, &temp_data, 1); + if (ret == 0) { + continue; + } + board_delay_ms(1); + } + + for (j = 0; j < retry_cnt; j++) { + ret = board_read_chip_reg( + p_dev, 0x3100, &temp_read, 1); + if ((1 == ret && 0xBB == temp_read)) { + break; + } + if ((1 == ret && 0xAA != temp_read)) { + ret = 0; + break; /*if 0x3100 is not 0xAA or 0xBB,rewrite 0x30F0 0xAA*/ + } + ret = 0; + board_delay_ms(5); + } + if ((1 == ret && 0xBB == temp_read)) { + break; + } + } + if (1 == ret && 1 == p_dev->doze_ref_cnt) { + p_dev->doze_ref_cnt--; + } + if (0 == ret) { + board_print_error( + "%s\n", + "[normandy_doze_mode]board_write_chip_reg 0xAA in 0x30f0 fail!"); + } + } + } + return ret; +} + +#ifdef __cplusplus +} +#endif + +/******************************************************************************* +* Function Name : normandy_hold_dsp +* Description : normandy hold dsp +* Input : PST_TP_DEV p_dev(touch panel deice) +* Output : none +* Return : u32(0:fail 1:ok) +*******************************************************************************/ +static s32 normandy_hold_dsp(IN PST_TP_DEV p_dev) +{ + /* if failed,retry, for max times 10*/ + s32 ret = 0; + u8 index = 0; + u8 write_value = 0x24; + u8 buf_tmp[2]; + buf_tmp[0] = write_value; + for (index = 0; index < 10; index++) { + ret = chip_reg_write(p_dev, 0x2180, buf_tmp, 1); + if (1 == ret) { + ret = chip_reg_read(p_dev, 0x2180, &(write_value), 1); + if (1 == ret && write_value == buf_tmp[0]) { + ret = 1; + break; + } + } + } + return ret; +} + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.h new file mode 100644 index 000000000000..7e3976c66ce3 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_normandy_control.h @@ -0,0 +1,52 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_normandy_control.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : normandy device control interface +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_NORMANDY_CONTROL_H +#define TP_NORMANDY_CONTROL_H + +#include "tp_dev_def.h" +#include "board_opr_interface.h" +#include "custom_info_def.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*************************************Public methods start********************************************/ +extern s32 normandy_reg_write(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len); +extern s32 normandy_reg_read(PST_TP_DEV p_dev, u16 addr, u8 *p_buf, + u16 buf_len); +extern s32 normandy_soft_reset_chip(PST_TP_DEV p_dev); +extern s32 normandy_reset_hold_chip(PST_TP_DEV p_dev); +extern s32 normandy_wakeup_chip(PST_TP_DEV p_dev); +extern s32 normandy_ctrl_chip_io(PST_TP_DEV p_dev, u16 io_id, + GIOMode_Def modeType); +extern s32 normandy_setbit_chip_io(PST_TP_DEV p_dev, u16 io_id, + GIOBit_Def bit_state); +extern GIOBit_Def normandy_getbit_chip_io(PST_TP_DEV p_dev, u16 io_id); +extern s32 normandy_force_update_cfg(PST_TP_DEV p_dev, u8 *config, u16 cfg_len); +extern s32 normandy_write_cfg(PST_TP_DEV p_dev); +extern s32 normandy_read_cfg(PST_TP_DEV p_dev); +extern s32 normandy_write_cfg_arr(PST_TP_DEV p_dev, u8 *config, u16 cfg_len); +extern s32 normandy_read_cfg_arr(PST_TP_DEV p_dev, u8 *config, u16 cfg_len); +extern void normandy_cfg_update_chksum(u8 *config, u16 cfg_len); +extern s32 normandy_cmp_cfg(PST_TP_DEV p_dev, u8 *cfg1, u8 *cfg2, u16 cfg_len); +extern s32 normandy_write_custom_info(PST_TP_DEV p_dev, + PST_CUSTOM_INFO_BYTE custom_info, u8 len); +extern s32 normandy_read_custom_info(PST_TP_DEV p_dev, + PST_CUSTOM_INFO_BYTE custom_info, u8 len); +extern s32 normandy_doze_mode(PST_TP_DEV p_dev, u8 b_ena, u8 b_force); +extern s32 normandy_check_chip_test_res_info(IN PST_TP_DEV p_dev, + IN u8 *test_res_info, IN u32 len); +/*************************************Public methods End********************************************/ +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.c new file mode 100644 index 000000000000..6033b02a1242 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.c @@ -0,0 +1,2196 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_open_test.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : touch panel circuit open test +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include +#include "tp_open_test.h" +#include "tp_dev_control.h" +#include "test_proc.h" +#include "simple_mem_manager.h" +#include "tp_additional_option.h" +#include "tp_test_general_error_code_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static s32 clear_rawtest_res_buf(PST_TEST_ITEM p_test_item); + +/*analyze rawdata test result*/ +static s32 analyze_rawtest_res(u8 offse_and_accord_flag, + PST_TEST_ITEM p_test_item); + +/*---------------rawdata limit test------------*/ +/*modify max and min avg */ +static s32 modify_statistic_data(PST_TEST_ITEM p_test_item); +/*-----------------------------rawdata as data source end-------------------------------*/ + +/*-----------------------------diffdata as data source start-------------------------------*/ + +static s32 clear_difftest_res_buf(PST_TEST_ITEM p_test_item); + +/*analyze diffdata test result*/ +static s32 analyze_difftest_res(u8 cur_frame_id, PST_TEST_ITEM p_test_item); + +/*modify statistic data of diffdata*/ +static s32 modify_diff_statistic_data(PST_TEST_ITEM p_test_item); + +/*-----------------------------diffdata as data source end-------------------------------*/ + +/******************************************************************************* +* Function Name : rawdata_test_sets_func +* Description : rawdata test func +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : u8(0:test error 1:ok) +*******************************************************************************/ +extern s32 rawdata_test_sets_func(IN_OUT ptr32 p_data) +{ + //You can leran more details from code gtp + s32 ret = 0; + u8 i = 0; + u8 offse_and_accord_flag = 0; + u16 err_code = RAWDATA_TEST_SUCCESSFULLY; + u16 get_rawdata_timeout = 3000; + u8 max_frame_total_num = TOTAL_FRAME_NUM_MAX; + u8 cur_frame_total_num = 16; + u8 add_frame_num = 16; + u8 filter_frame_cnt = 0; + u8 filter_frame_num = 1; + u8 b_filter_data = 0; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + PST_RAWDATA_TEST_RES p_test_res = NULL; + PST_RAWDATA_TEST_CALLBACK_SET p_spec_callback_set = NULL; + PST_CUR_RAWDATA p_cur_data = NULL; + PST_TEST_PROC_DATA p_test_proc_data = NULL; + + /*-----------------Judge parameter----------------**/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto EXIT_RAWDATA_TEST; + } + /*(1)callback function test before*/ + if (NULL != p_test_item->ptr_test_item_before_func) { + ret = p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (ret == 0) { + board_print_error( + "[open test]callback function test before error!\n"); + err_code = TEST_BEFORE_FUNC_FAIL; + goto EXIT_RAWDATA_TEST; + } + } + p_test_proc_data = (PST_TEST_PROC_DATA)p_test_item->ptr_test_proc_data; + p_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + /*p_test_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = RAWDATA_TEST_SUCCESSFULLY; + //p_test_res->item_res_header.test_result = TEST_NG; + //p_test_res->item_res_header.test_status = TEST_START;*/ + + /*(2)clear rawdate result buf*/ + clear_rawtest_res_buf(p_test_item); + + /*(3)sending command and then get raw data.*/ + ret = chip_mode_select(p_test_item->p_tp_dev, CHIP_RAW_DATA_MODE); + if (0 == ret) { + board_print_error("enter raw data mode error!\n"); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = RAWDATA_TEST_ENTER_MODE_FAIL; + p_test_res->item_res_header.test_status = TEST_ABORTED; + err_code = RAWDATA_TEST_ENTER_MODE_FAIL; + goto RAWDATA_TEST_SETS_FUNC_END; + } + p_cur_data = (PST_CUR_RAWDATA)p_test_item->cur_data.ptr_cur_data; + p_cur_data->cur_frame_id = 0; + while (1) { + if (p_test_proc_data->test_break_flag) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = RAWDATA_TEST_BREAK_OUT; + p_test_res->item_res_header.test_status = TEST_ABORTED; + err_code = RAWDATA_TEST_BREAK_OUT; + board_print_error("rawdata test break out!\n"); + goto RAWDATA_TEST_SETS_FUNC_END; + } + /*get rawdata*/ + b_filter_data = 0; + if (filter_frame_cnt < filter_frame_num) { + b_filter_data = 1; + } + ret = board_get_rawdata(p_test_item->p_tp_dev, + get_rawdata_timeout, b_filter_data, + p_cur_data); + if (0 == ret) { + board_print_error("get rawdata error!\n"); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = + RAWDATA_TEST_GET_DATA_TIME_OUT; + p_test_res->item_res_header.test_status = TEST_ABORTED; + err_code = RAWDATA_TEST_GET_DATA_TIME_OUT; + goto RAWDATA_TEST_SETS_FUNC_END; + } + if (filter_frame_cnt < filter_frame_num) { + filter_frame_cnt++; + continue; + } + /*modify max & min & avg data*/ + modify_statistic_data(p_test_item); + + /*sub test items*/ + for (i = 0; i < p_test_item->p_sub_id_set->len; i++) { + switch (p_test_item->p_sub_id_set->p_id_set[i]) { + case TP_RAWDATA_MAX_TEST_ITEM_ID: + rawdata_max_test_func(p_data); + break; + case TP_RAWDATA_MIN_TEST_ITEM_ID: + rawdata_min_test_func(p_data); + break; + case TP_KEYDATA_MAX_TEST_ITEM_ID: + keydata_max_test_func(p_data); + break; + case TP_KEYDATA_MIN_TEST_ITEM_ID: + keydata_min_test_func(p_data); + break; + case TP_ACCORD_TEST_ITEM_ID: + rawdata_accord_test_func(p_data); + offse_and_accord_flag |= 0x01; + break; + case TP_OFFSET_TEST_ITEM_ID: + rawdata_offset_test_func(p_data); + offse_and_accord_flag |= 0x02; + break; + case TP_UNIFORMITY_TEST_ITEM_ID: + rawdata_uniform_test_func(p_data); + break; + case TP_RAWDATA_JITTER_TEST_ITEM_ID: + rawdata_jitter_test_func(p_data); + break; + default: + break; + } + } + + p_spec_callback_set = + (PST_RAWDATA_TEST_CALLBACK_SET) + p_test_item->ptr_special_callback_data; + if (NULL != p_spec_callback_set) { + /*save current data*/ + ret = p_spec_callback_set->ptr_save_cur_data_func( + p_spec_callback_set + ->ptr_save_cur_data_func_param); + if (ret == 0) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = + SAVE_CUR_DATA_ERR; + err_code = SAVE_CUR_DATA_ERR; + board_print_error( + "save current rawdata error!\n"); + } + } + /*count frame id*/ + p_cur_data->cur_frame_id++; + + p_test_res->total_frame_cnt = p_cur_data->cur_frame_id; + + /*(4)analysis result*/ + if ((cur_frame_total_num <= max_frame_total_num) && + (0 == p_cur_data->cur_frame_id % add_frame_num)) { + ret = analyze_rawtest_res(offse_and_accord_flag, + p_test_item); + if (ret == 0 || ret == 1) { + break; + } else if (ret == 2) { + cur_frame_total_num += add_frame_num; + p_test_res->open_test_result |= FIRST_TEST_FLAG; + } + } + if (p_cur_data->cur_frame_id >= max_frame_total_num) { + break; + } + } + + /*(5)clear flag*/ + p_test_res->open_test_result &= (~FIRST_TEST_FLAG); + + /*(6)modify test status*/ + p_test_res->item_res_header.test_status = TEST_FINISH; + if (p_test_res->open_test_result == 0) { + p_test_res->item_res_header.test_result = TEST_OK; + } else { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = RAWDATA_TEST_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + } +RAWDATA_TEST_SETS_FUNC_END: + + /*(7)enter coord mode*/ + ret = chip_mode_select(p_test_item->p_tp_dev, CHIP_COORD_MODE); + if (ret == 0) { + board_print_error("enter coordinate mode error!\n"); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = ENTER_COORD_MODE_ERR; + err_code = ENTER_COORD_MODE_ERR; + } +EXIT_RAWDATA_TEST: + /*(8)callback function after test finished*/ + if (NULL != p_test_item->ptr_test_item_finished_func) { + ret = p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param); + if (ret == 0) { + board_print_error( + "[open test]callback function after test error!\n"); + err_code = TEST_FINISH_FUNC_FAIL; + } + } + + if (err_code == RAWDATA_TEST_SUCCESSFULLY) { + ret = 1; + } else { + ret = 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : rawdata_max_test_func +* Description : rawdata max limit test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 rawdata_max_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + + /*judge test item result*/ + if (((p_raw_test_res->open_test_result & FIRST_TEST_FLAG) != 0) && + ((p_raw_test_res->open_test_result & BEYOND_RAWDATA_UPPER_LIMIT) == + 0)) { + return ret; + } + + index = get_arr_id_from_sub_item(p_test_item, + TP_RAWDATA_MAX_TEST_ITEM_ID); + if (0xFF != index) { + u16 id = 0; + u16 node_num = 0; + s32 data_tmp = 0; + s32 para_tmp = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + node_num = p_dev->sc_sen_num * p_dev->sc_drv_num; + + /*upper limit*/ + for (id = 0; id < node_num; id++) { + if (get_chn_need_check(p_test_item, id)) { + data_tmp = get_chn_rawdata(p_test_item, id); + para_tmp = get_chn_upper_limit(p_test_item, id); + if (data_tmp > para_tmp) { + /*mark this channel beyond upper limit count*/ + p_raw_test_res + ->p_beyond_rawdata_upper_limit_cnt + [id]++; + p_raw_test_res->open_test_result |= + BEYOND_RAWDATA_UPPER_LIMIT; + p_raw_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[index + 1] = + RAWDATA_TEST_BEYOND_MAX_LIMIT; + ret = 0; + } + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : rawdata_min_test_func +* Description : rawdata min limit test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 rawdata_min_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + + /*judge test item result*/ + if (((p_raw_test_res->open_test_result & FIRST_TEST_FLAG) != 0) && + ((p_raw_test_res->open_test_result & BEYOND_RAWDATA_LOWER_LIMIT) == + 0)) { + return ret; + } + + index = get_arr_id_from_sub_item(p_test_item, + TP_RAWDATA_MIN_TEST_ITEM_ID); + if (0xFF != index) { + u16 id = 0; + u16 node_num = 0; + s32 data_tmp = 0; + s32 para_tmp = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + node_num = p_dev->sc_sen_num * p_dev->sc_drv_num; + + /*lower limit*/ + for (id = 0; id < node_num; id++) { + if (get_chn_need_check(p_test_item, id)) { + data_tmp = get_chn_rawdata(p_test_item, id); + para_tmp = get_chn_lower_limit(p_test_item, id); + if (data_tmp < para_tmp) { + /*mark this channel beyond lower limit count*/ + p_raw_test_res + ->p_beyond_rawdata_lower_limit_cnt + [id]++; + p_raw_test_res->open_test_result |= + BEYOND_RAWDATA_LOWER_LIMIT; + p_raw_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[index + 1] = + BEYOND_RAWDATA_LOWER_LIMIT; + ret = 0; + } + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : rawdata_accord_test_func +* Description : accord test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 rawdata_accord_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + if ((p_raw_test_res->open_test_result & FIRST_TEST_FLAG) != 0 && + (p_raw_test_res->open_test_result & BEYOND_ACCORD_LIMIT) == 0) { + return ret; + } + + index = get_arr_id_from_sub_item(p_test_item, TP_ACCORD_TEST_ITEM_ID); + if (0xFF != index) { + u16 id = 0; + u16 node_num = 0; + s32 data_tmp = 0; + s32 para_tmp = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + node_num = p_dev->sc_sen_num * p_dev->sc_drv_num; + + for (id = 0; id < node_num; id++) { + if (get_chn_need_check(p_test_item, id)) { + data_tmp = get_chn_accord(p_test_item, id); + /*/upper limit*/ + para_tmp = + get_chn_accord_limit(p_test_item, id); + if (data_tmp > para_tmp) { + /*mark this channel beyond accord limit count*/ + p_raw_test_res + ->p_beyond_accord_limit_cnt[id]++; + p_raw_test_res->open_test_result |= + BEYOND_ACCORD_LIMIT; + p_raw_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[index + 1] = + RAWDATA_TEST_BEYOND_ACCORD_LIMIT; + ret = 0; + } + } + } + } + return ret; +} + +/******************************************************************************* +* Function Name : keydata_max_test_func +* Description : keydata max limit test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 keydata_max_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + + /*judge test item result*/ + if (((p_raw_test_res->open_test_result & FIRST_TEST_FLAG) != 0) && + ((p_raw_test_res->open_test_result & KEY_BEYOND_UPPER_LIMIT) == + 0)) { + return ret; + } + + index = get_arr_id_from_sub_item(p_test_item, + TP_KEYDATA_MAX_TEST_ITEM_ID); + if (0xFF != index) { + u8 id = 0; + u8 key_num = 0; + s32 data_tmp = 0; + s32 para_tmp = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + key_num = p_dev->key_num; + + /*upper limit*/ + for (id = 0; id < key_num; id++) { + if (get_key_need_check(p_test_item, id)) { + data_tmp = get_keydata(p_test_item, id); + para_tmp = get_key_upper_limit(p_test_item, id); + if (data_tmp > para_tmp) { + /*mark this channel beyond upper limit count*/ + p_raw_test_res + ->p_beyond_key_upper_limit_cnt + [id]++; + p_raw_test_res->open_test_result |= + KEY_BEYOND_UPPER_LIMIT; + p_raw_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[index + 1] = + RAWDATA_TEST_BEYOND_KEY_MAX_LIMIT; + ret = 0; + } + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : keydata_min_test_func +* Description : keydata min limit test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 keydata_min_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + + /*judge test item result*/ + if (((p_raw_test_res->open_test_result & FIRST_TEST_FLAG) != 0) && + ((p_raw_test_res->open_test_result & KEY_BEYOND_LOWER_LIMIT) == + 0)) { + return ret; + } + + index = get_arr_id_from_sub_item(p_test_item, + TP_KEYDATA_MIN_TEST_ITEM_ID); + if (0xFF != index) { + u8 id = 0; + u8 key_num = 0; + s32 data_tmp = 0; + s32 para_tmp = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + key_num = p_dev->key_num; + /*PST_SUB_TEST_ITEM_ID_SET p_sub_item_id_set = NULL; + //p_sub_item_id_set = (PST_SUB_TEST_ITEM_ID_SET)p_test_item->p_sub_id_set;*/ + + /*lower limit*/ + for (id = 0; id < key_num; id++) { + if (get_key_need_check(p_test_item, id)) { + data_tmp = get_keydata(p_test_item, id); + para_tmp = get_key_lower_limit(p_test_item, id); + if (data_tmp < para_tmp) { + /*mark this channel beyond lower limit count*/ + p_raw_test_res + ->p_beyond_key_lower_limit_cnt + [id]++; + p_raw_test_res->open_test_result |= + KEY_BEYOND_LOWER_LIMIT; + p_raw_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[index + 1] = + RAWDATA_TEST_BEYOND_KEY_MIN_LIMIT; + ret = 0; + } + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : rawdata_jitter_test_func +* Description : rawdata jitter test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* : u8 cur_frame_id +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 rawdata_jitter_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + PST_CUR_RAWDATA p_cur_data = + (PST_CUR_RAWDATA)p_test_item->cur_data.ptr_cur_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + if ((p_cur_data->cur_frame_id + 1) != 16) { + return 1; + } + + index = get_arr_id_from_sub_item(p_test_item, + TP_RAWDATA_JITTER_TEST_ITEM_ID); + if (0xFF != index) { + u16 id = 0; + s32 data_tmp = 0; + s32 para_tmp = 0; + u16 node_num = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + node_num = p_dev->sc_sen_num * p_dev->sc_drv_num; + para_tmp = get_rawdata_jitter_limit(p_test_item); + for (id = 0; id < node_num; id++) { + if (get_chn_need_check(p_test_item, id)) { + data_tmp = p_raw_test_res->p_max_raw_tmp_data + ->p_data_buf[id] - + p_raw_test_res->p_min_raw_tmp_data + ->p_data_buf[id]; + if (data_tmp > para_tmp) { + /*mark this beyond jitter limit count*/ + p_raw_test_res + ->p_beyond_jitter_limit_cnt[id] |= + 0x80; + p_raw_test_res->open_test_result |= + BEYOND_JITTER_LIMIT; + p_raw_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[index + 1] = + RAWDATA_TEST_BEYOND_JITTER_LIMIT; + ret = 0; + } + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : rawdata_uniform_test_func +* Description : rawdata uniform test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 rawdata_uniform_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + if ((p_raw_test_res->open_test_result & FIRST_TEST_FLAG) != 0 && + (p_raw_test_res->open_test_result & BEYOND_UNIFORMITY_LIMIT) == 0) { + return ret; + } + + index = get_arr_id_from_sub_item(p_test_item, + TP_UNIFORMITY_TEST_ITEM_ID); + if (0xFF != index) { + s32 data_tmp = 0; + s32 para_tmp = 0; + data_tmp = get_uniform_value(p_test_item); + para_tmp = get_uniform_limit(p_test_item); + + if (data_tmp < para_tmp) { + /*mark this channel beyond lower limit*/ + p_raw_test_res->beyond_uniform_limit_cnt++; + p_raw_test_res->open_test_result |= + BEYOND_UNIFORMITY_LIMIT; + p_raw_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[index + 1] = + RAWDATA_TEST_BEYOND_UNIFORM_LIMIT; + ret = 0; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : rawdata_offset_test_func +* Description : rawdata offset test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test ng 1:test ok) +*******************************************************************************/ +extern s32 rawdata_offset_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 1; + s32 index = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + if ((p_raw_test_res->open_test_result & FIRST_TEST_FLAG) != 0 && + (p_raw_test_res->open_test_result & BEYOND_OFFSET_LIMIT) == 0) { + return ret; + } + + index = get_arr_id_from_sub_item(p_test_item, TP_OFFSET_TEST_ITEM_ID); + if (0xFF != index) { + u16 id = 0; + u16 node_num = 0; + s32 data_tmp = 0; + s32 para_tmp = 0; + /*PST_SUB_TEST_ITEM_ID_SET p_sub_item_id_set = NULL;*/ + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + /*p_sub_item_id_set = (PST_SUB_TEST_ITEM_ID_SET)p_test_item->p_sub_id_set;*/ + node_num = p_dev->sc_sen_num * p_dev->sc_drv_num; + + /*(1)sending command and then get rawdata.*/ + for (id = 0; id < node_num; id++) { + data_tmp = get_chn_offset(p_test_item, id); + if (get_chn_need_check(p_test_item, id)) { + /*upper limit*/ + para_tmp = + get_chn_offset_limit(p_test_item, id); + if (data_tmp > para_tmp) { + /*//mark this channel beyond offset limit count*/ + p_raw_test_res + ->p_beyond_offset_limit_cnt[id]++; + p_raw_test_res->open_test_result |= + BEYOND_OFFSET_LIMIT; + p_raw_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[index + 1] = + RAWDATA_TEST_BEYOND_OFFSET_LIMIT; + ret = 0; + } + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : diffdata_test_sets_func +* Description : diffdata test sets function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 diffdata_test_sets_func(IN_OUT ptr32 p_data) +{ + /*//You can leran more details from code gtp*/ + s32 ret = 1; + u8 i = 0; + u16 get_diffdata_timeout = 3000; + u8 max_frame_total_num = 64; + u8 cur_frame_total_num = 16; + u8 add_frame_num = 16; + u8 filter_frame_cnt = 0; + u8 filter_frame_num = 1; + u8 b_filter_data = 0; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + PST_DIFFDATA_TEST_RES p_test_res = NULL; + PST_DIFFDATA_TEST_CALLBACK_SET p_spec_callback_set = NULL; + PST_CUR_DIFFDATA p_cur_data = NULL; + PST_TEST_PROC_DATA p_test_proc_data = NULL; + + /*//-----------------Judge parameter----------------*/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto DIFFDATA_TEST_SETS_FUNC_END; + } + + p_test_proc_data = (PST_TEST_PROC_DATA)p_test_item->ptr_test_proc_data; + p_test_res = (PST_DIFFDATA_TEST_RES)p_test_item->test_res.ptr_res; + p_cur_data = (PST_CUR_DIFFDATA)p_test_item->cur_data.ptr_cur_data; + + /*//(1)callback function test before*/ + if (NULL != p_test_item->ptr_test_item_before_func) { + ret &= p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (ret == 0) { + test_before_func_fail_proc( + &p_test_res->item_res_header); + goto DIFFDATA_TEST_SETS_FUNC_END; + } + } + /*//clear result buffer*/ + clear_difftest_res_buf(p_test_item); + + /*//sending command and then get diff data.*/ + ret = chip_mode_select(p_test_item->p_tp_dev, CHIP_DIFF_DATA_MODE); + if (0 == ret) { + board_print_error("enter diff data mode error!\n"); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = DIFFDATA_TEST_ENTER_MODE_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + goto DIFFDATA_TEST_SETS_FUNC_END; + } + + p_cur_data->cur_frame_id = 0; + while (1) { + if (p_test_proc_data->test_break_flag) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = DIFFDATA_TEST_BREAK_OUT; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + goto DIFFDATA_TEST_SETS_FUNC_END; + } + /*//get diffdata*/ + b_filter_data = 0; + if (filter_frame_cnt < filter_frame_num) { + b_filter_data = 1; + } + ret = board_get_diffdata(p_test_item->p_tp_dev, + get_diffdata_timeout, b_filter_data, + p_cur_data); + if (0 == ret) { + board_print_error("get diffdata error!\n"); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = + DIFFDATA_TEST_GET_DATA_TIME_OUT; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + goto DIFFDATA_TEST_SETS_FUNC_END; + } + + if (filter_frame_cnt < filter_frame_num) { + filter_frame_cnt++; + continue; + } + + /*//statistic data modify*/ + ret = modify_diff_statistic_data(p_test_item); + /*//sub test items*/ + for (i = 0; i < p_test_item->p_sub_id_set->len; i++) { + switch (p_test_item->p_sub_id_set->p_id_set[i]) { + case TP_DIFFDATA_JITTER_TEST_ITEM_ID: + diffdata_jitter_test_func(p_data); + break; + default: + break; + } + } + + p_spec_callback_set = + (PST_DIFFDATA_TEST_CALLBACK_SET) + p_test_item->ptr_special_callback_data; + if (NULL != p_spec_callback_set) { + /*//save current data*/ + p_spec_callback_set->ptr_save_cur_data_func( + p_spec_callback_set + ->ptr_save_cur_data_func_param); + } + /*//count frame id*/ + p_cur_data->cur_frame_id++; + p_test_res->total_frame_cnt = p_cur_data->cur_frame_id; + /*//analysis result*/ + if ((cur_frame_total_num <= max_frame_total_num) && + (0 == p_cur_data->cur_frame_id % add_frame_num)) { + ret = analyze_difftest_res(p_cur_data->cur_frame_id, + p_test_item); + if (ret == 0) { + break; + } else if (ret == 1) { + p_test_res->item_res_header.test_result = + TEST_NG; + p_test_res->item_res_header.test_status = + TEST_ABORTED; + break; + } else if (ret == 2) { + cur_frame_total_num += add_frame_num; + } + } + if (p_cur_data->cur_frame_id >= max_frame_total_num) { + break; + } + } + +DIFFDATA_TEST_SETS_FUNC_END: + + /*//enter coord mode*/ + ret = chip_mode_select(p_test_item->p_tp_dev, CHIP_COORD_MODE); + if (ret == 0) { + board_print_error("enter coordinate mode error!\n"); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = ENTER_COORD_MODE_ERR; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + } + + if (NULL != p_test_item->ptr_test_item_finished_func) { + if (0 == + p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param)) { + board_print_error( + "[diffdata_test_sets_func]callback function after test error!\n"); + ret = 0; + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : diffdata_jitter_test_func +* Description : diffdata jitter test function +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 diffdata_jitter_test_func(IN_OUT ptr32 p_data) +{ + /*//PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data;*/ + return 1; +} + +/******************************************************************************* +* Function Name : get rawdata +* Description : get rawdata +* Input : PST_TP_DEV p_dev(device ) +* Input : u16 time_out_ms +* Input : u8 b_filter_data +* Output : OUT PST_CUR_RAWDATA p_cur_data +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 get_rawdata(IN PST_TP_DEV p_dev, IN u16 time_out_ms, + IN u8 b_filter_data, OUT PST_CUR_RAWDATA p_cur_data) +{ + s32 ret = 0; + u16 i = 0; + u8 retry_cnt = 3; + u8 data_size = 1; + u16 wait_time = 0; + s32 data_flag = 0; + if (p_dev->rawdata_option & _DATA_BIT_8) { + data_size = 1; + } else if (p_dev->rawdata_option & _DATA_BIT_16) { + data_size = 2; + } else if (p_dev->rawdata_option & _DATA_BIT_32) { + data_size = 4; + } else if (p_dev->rawdata_option & _DATA_BIT_64) { + data_size = 8; + } + + while (wait_time < time_out_ms) { + /*//Is there data ?*/ + data_flag = get_data_flag(p_dev); + board_print_debug("get rawdata flag!"); + if (data_flag) { + if (0 == b_filter_data) { + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read( + p_dev, p_dev->rawdata_addr, + p_cur_data->p_data_buf, + p_dev->rawdata_len * data_size); + if (1 == ret) { + break; + } + } + if (0 == ret) { + board_print_error( + "read rawdata error!\n"); + goto GET_RAWDATA_END; + } + + if ((p_dev->rawdata_option & + _DATA_LARGE_ENDIAN) || + (p_dev->rawdata_option & + _DATA_DRV_SEN_INVERT)) { + reshape_data(p_dev->rawdata_option, + p_dev, p_cur_data); + } + } + /*//clear data flag*/ + ret = clr_data_flag(p_dev); + if (0 == ret) { + board_print_error("clear dataflag error!\n"); + goto GET_RAWDATA_END; + } + goto GET_RAWDATA_END; + } + board_delay_ms(5); + wait_time += 5; + } + if (data_flag == 0) { + board_print_error("get_data_flag failed\n"); + return 0; + } +GET_RAWDATA_END: + + return ret; +} + +/******************************************************************************* +* Function Name : get_diffdata +* Description : get diffdata +* Input : PST_TP_DEV p_tp_dev(device ) +* Input : u16 time_out_ms +* Input : u8 b_filter_data +* Output : PST_CUR_DIFFDATA p_cur_data +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +extern s32 get_diffdata(IN PST_TP_DEV p_dev, IN u16 time_out_ms, + IN u8 b_filter_data, IN_OUT PST_CUR_DIFFDATA p_cur_data) +{ + s32 ret = 0; + u8 i = 0; + u8 retry_cnt = 3; + u8 data_size = 0; + u16 wait_time = 0; + if (p_dev->diffdata_option & _DATA_BIT_8) { + data_size = 1; + } else if (p_dev->diffdata_option & _DATA_BIT_16) { + data_size = 2; + } else if (p_dev->diffdata_option & _DATA_BIT_32) { + data_size = 4; + } else if (p_dev->diffdata_option & _DATA_BIT_64) { + data_size = 8; + } + + while (wait_time < time_out_ms) { + /*//Is there data ?*/ + if (get_data_flag(p_dev)) { + if (0 == b_filter_data) { + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read( + p_dev, p_dev->diffdata_addr, + (u8 *)p_cur_data->p_data_buf, + p_dev->diffdata_len * + data_size); + if (1 == ret) { + break; + } + } + + if (0 == ret) { + board_print_error( + "read diffdata error!\n"); + goto GET_DIFFDATA_END; + } + if ((p_dev->diffdata_option & + _DATA_LARGE_ENDIAN) || + (p_dev->diffdata_option & + _DATA_DRV_SEN_INVERT)) { + reshape_data(p_dev->diffdata_option, + p_dev, p_cur_data); + } + } + /*//clear data flag*/ + ret = clr_data_flag(p_dev); + if (0 == ret) { + board_print_error("clear dataflag error!\n"); + goto GET_DIFFDATA_END; + } + goto GET_DIFFDATA_END; + } + board_delay_ms(5); + wait_time += 5; + } +GET_DIFFDATA_END: + + return ret; +} + +/******************************************************************************* +* Function Name : get_data_size +* Description : get byte count of data +* Input : u8 data_option +* Output : +* Return : u8(byte cnt of data) +*******************************************************************************/ +extern u8 get_data_size(u8 data_option) +{ + u8 data_size = 2; + if (data_option & _DATA_BIT_8) { + data_size = 1; + } else if (data_option & _DATA_BIT_16) { + data_size = 2; + } else if (data_option & _DATA_BIT_32) { + data_size = 4; + } else if (data_option & _DATA_BIT_64) { + data_size = 8; + } + return data_size; +} + +/******************************************************************************* +* Function Name : reshape_data +* Description : +* Input : u8 data_option +: PST_CUR_RAWDATA p_cur_data +: PST_TP_DEV p_dev +* Output : PST_CUR_RAWDATA p_cur_data +* Return : none +*******************************************************************************/ +extern void reshape_data(IN u8 data_option, IN PST_TP_DEV p_dev, + IN_OUT PST_CUR_RAWDATA p_cur_data) +{ + u8 data_size = 2; + u8 data_tmp = 0; + u16 i = 0; + u8 j = 0; + u8 *p_buf_tmp = NULL; + u8 drv_id = 0; + u8 sen_id = 0; + u16 tmp_id = 0; + u8 *p_buf_bak = NULL; + + if (data_option & _DATA_BIT_8) { + data_size = 1; + } else if (data_option & _DATA_BIT_16) { + data_size = 2; + } else if (data_option & _DATA_BIT_32) { + data_size = 4; + } else if (data_option & _DATA_BIT_64) { + data_size = 8; + } + + p_buf_tmp = p_cur_data->p_data_buf; + /*//in arm or pc,data is little-endian in ram so we need change "large-endian" to "little-endian"*/ + if ((data_option & _DATA_LARGE_ENDIAN) && (data_size > 1)) { + for (i = 0; i < p_dev->rawdata_len * data_size; + i += data_size) { + for (j = 0; j < data_size - j; j++) { + data_tmp = p_buf_tmp[i + j]; + p_buf_tmp[i + j] = + p_buf_tmp[i + data_size - j - 1]; + p_buf_tmp[i + data_size - j - 1] = data_tmp; + } + } + } + /*//storage data in driver direction must change in sensor direction in single-chip*/ + /*//drv sen invert*/ + if ((data_option & _DATA_DRV_SEN_INVERT)) { + if (alloc_mem_block((void **)&p_buf_bak, + p_dev->rawdata_len * data_size)) { + memcpy(p_buf_bak, p_buf_tmp, + p_dev->rawdata_len * data_size); + for (i = 0; i < p_dev->sc_drv_num * p_dev->sc_sen_num; + i++) { + drv_id = i / p_dev->sc_sen_num; + sen_id = i % p_dev->sc_sen_num; + tmp_id = sen_id * p_dev->sc_drv_num + drv_id; + for (j = 0; j < data_size; j++) { + p_buf_tmp[tmp_id * data_size + j] = + p_buf_bak[i * data_size + j]; + } + } + free_mem_block(p_buf_bak); + } + } +} + +/******************************************************************************* +* Function Name : get_chn_rawdata +* Description : get specialized channel rawdata +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_rawdata(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + PST_CUR_RAWDATA p_cur_rawdata = + (PST_CUR_RAWDATA)(p_test_item->cur_data.ptr_cur_data); + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + u16 len = p_dev->sc_sen_num * p_dev->sc_drv_num; + + /*//data is little-endian after reshaping*/ + if (len > chn_id) { + if (p_dev->rawdata_option & _DATA_BIT_8) { + ret = p_cur_rawdata->p_data_buf[chn_id]; + } else if (p_dev->rawdata_option & _DATA_BIT_16) { + ret = (s16)((p_cur_rawdata->p_data_buf[chn_id * 2]) + + (p_cur_rawdata->p_data_buf[chn_id * 2 + 1] + << 8)); + } else if (p_dev->rawdata_option & _DATA_BIT_32) { + ret = (p_cur_rawdata->p_data_buf[chn_id * 4]) + + (p_cur_rawdata->p_data_buf[chn_id * 4 + 1] << 8) + + (p_cur_rawdata->p_data_buf[chn_id * 4 + 2] + << 16) + + (p_cur_rawdata->p_data_buf[chn_id * 4 + 3] << 24); + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_need_check +* Description : judge specialized channel whether need check or not.we use bit +to save memory. +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : s32(0:not need check 1:need check) +*******************************************************************************/ +extern s32 get_chn_need_check(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + PST_TP_DEV p_dev = NULL; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = NULL; + if (NULL == p_test_item) { + return 1; + } + p_dev = p_test_item->p_tp_dev; + p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + if (chn_id < p_dev->sc_sen_num * p_dev->sc_drv_num) { + if (p_rawdata_test_param->p_need_check_node + ->p_data_buf[chn_id] == TP_FLAG_NEED_CHECK) { + ret = 1; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_upper_limit +* Description : get node upper limit +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_upper_limit(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + u16 i = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + PST_RAWDATA_SPECIAL_NODE_PARAM p_spec_node = + p_rawdata_test_param->p_special_node; + + ret = p_rawdata_test_param->p_rawdata_limit->upper_limit; + for (i = 0; i < p_spec_node->data_len; i++) { + if (chn_id == p_spec_node->p_data_buf[i].node_id) { + ret = p_spec_node->p_data_buf[i].high_raw_limit; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_lower_limit +* Description : get node lower limit +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_lower_limit(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + u16 i = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + PST_RAWDATA_SPECIAL_NODE_PARAM p_spec_node = + p_rawdata_test_param->p_special_node; + ret = p_rawdata_test_param->p_rawdata_limit->lower_limit; + for (i = 0; i < p_spec_node->data_len; i++) { + if (chn_id == p_spec_node->p_data_buf[i].node_id) { + ret = p_spec_node->p_data_buf[i].low_raw_limit; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_accord +* Description : get chn accord(*1000) +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_accord(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + u16 accord_opt = DEF_ACCORD_CALC; + s32 tmp_data = 0x7FFFFFFF; + s32 cur_data = 0; + u8 i = 0; + s16 pos_arr[4] = { -1, -1, -1, -1 }; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + + tmp_data = get_adjacent_node(chn_id, p_dev, pos_arr); + accord_opt = get_chn_accord_option(p_test_item, chn_id); + for (i = 0; i < 4; i++) { + /*//upon,down,left,right*/ + if (0 == (accord_opt & (1 << i))) { + pos_arr[i] = -1; + } + } + cur_data = get_chn_rawdata(p_test_item, chn_id); + for (i = 0; i < 4; i++) { + if (-1 == pos_arr[i]) { + continue; + } + tmp_data = get_chn_rawdata(p_test_item, (u16)pos_arr[i]); + tmp_data = (tmp_data - cur_data) > 0 ? (tmp_data - cur_data) : + (cur_data - tmp_data); + tmp_data = (s32)(1000 * tmp_data / cur_data); + if (tmp_data > ret) { + ret = tmp_data; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_accord_limit +* Description : get chn accord limit(*1000) +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_accord_limit(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + u16 i = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + PST_RAWDATA_SPECIAL_NODE_PARAM p_spec_node = + p_rawdata_test_param->p_special_node; + ret = p_rawdata_test_param->p_raw_accord_limit->accord_limit; + for (i = 0; i < p_spec_node->data_len; i++) { + if (chn_id == p_spec_node->p_data_buf[i].node_id) { + ret = p_spec_node->p_data_buf[i].accord_limit; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_accord_option +* Description : get_chn_accord_option +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : u16 +*******************************************************************************/ +extern u16 get_chn_accord_option(PST_TEST_ITEM p_test_item, u16 chn_id) +{ + u16 ret = DEF_ACCORD_CALC; + u16 i = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + PST_RAWDATA_SPECIAL_NODE_PARAM p_spec_node = + p_rawdata_test_param->p_special_node; + + ret = p_rawdata_test_param->p_raw_accord_limit->accord_option; + for (i = 0; i < p_spec_node->data_len; i++) { + if (chn_id == p_spec_node->p_data_buf[i].node_id) { + ret = p_spec_node->p_data_buf[i].accord_option; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_adjacent_node +* Description : get adjacent node +* Input : u16 node_id +: PST_TP_DEV p_dev +* Output : s16* p_arr +* Return : s32(adjacent node num) +*******************************************************************************/ +extern u8 get_adjacent_node(IN u16 node_id, IN PST_TP_DEV p_dev, OUT s16 *p_arr) +{ + u8 ret = 4; + u16 drv_id = 0; /*//col_id*/ + u16 sen_id = 0; /*//row_id*/ + + drv_id = node_id % p_dev->sc_drv_num; + sen_id = node_id / p_dev->sc_drv_num; + + p_arr[ADJ_POS_UP] = (sen_id - 1) * (p_dev->sc_drv_num) + drv_id; + p_arr[ADJ_POS_DOWN] = (sen_id + 1) * (p_dev->sc_drv_num) + drv_id; + p_arr[ADJ_POS_LEFT] = (sen_id) * (p_dev->sc_drv_num) + drv_id - 1; + p_arr[ADJ_POS_RIGHT] = (sen_id) * (p_dev->sc_drv_num) + drv_id + 1; + + if (sen_id == 0) { + p_arr[ADJ_POS_UP] = -1; + ret--; + } else if (sen_id == p_dev->sc_sen_num - 1) { + p_arr[ADJ_POS_DOWN] = -1; + ret--; + } + + if (drv_id == 0) { + p_arr[ADJ_POS_LEFT] = -1; + ret--; + } else if (drv_id == p_dev->sc_drv_num - 1) { + p_arr[ADJ_POS_RIGHT] = -1; + ret--; + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_offset +* Description : get chn offset(*1000) +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_offset(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = + (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + u16 len = p_dev->sc_sen_num * p_dev->sc_drv_num; + u32 tmp_data = 0; + u32 tmp_raw = 0; + u32 avg = 0; + if (len > chn_id) { + tmp_raw = get_chn_rawdata(p_test_item, chn_id); + avg = p_raw_test_res->raw_avg; + tmp_data = (tmp_raw - avg) > 0 ? (tmp_raw - avg) : + (avg - tmp_raw); + ret = (s32)(1000 * tmp_data / p_raw_test_res->raw_avg); + } + return ret; +} + +/******************************************************************************* +* Function Name : get_chn_offset_limit +* Description : get channel offset limit(*1000) +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_offset_limit(IN PST_TEST_ITEM p_test_item, IN u16 chn_id) +{ + s32 ret = 0; + u16 i = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + PST_RAWDATA_SPECIAL_NODE_PARAM p_spec_node = + p_rawdata_test_param->p_special_node; + ret = p_rawdata_test_param->p_raw_offset_limit->offset_limit; + for (i = 0; i < p_spec_node->data_len; i++) { + if (chn_id == p_spec_node->p_data_buf[i].node_id) { + ret = p_spec_node->p_data_buf[i].offset_limit; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_keydata +* Description : get keydata +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u8 key_id(key id) +* Return : s32 +*******************************************************************************/ +extern s32 get_keydata(IN PST_TEST_ITEM p_test_item, IN u8 key_id) +{ + s32 ret = 0; + u16 tmp_id = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + PST_CUR_RAWDATA p_cur_rawdata = + (PST_CUR_RAWDATA)p_test_item->cur_data.ptr_cur_data; + + if (key_id < p_dev->key_num) { + tmp_id = p_dev->sc_sen_num * p_dev->sc_drv_num + + p_dev->key_pos_arr[key_id] - 1; + + if (p_dev->rawdata_option & _DATA_BIT_8) { + ret = p_cur_rawdata->p_data_buf[tmp_id]; + } else if (p_dev->rawdata_option & _DATA_BIT_16) { + ret = (s16)((p_cur_rawdata->p_data_buf[tmp_id * 2]) + + (p_cur_rawdata->p_data_buf[tmp_id * 2 + 1] + << 8)); + } else if (p_dev->rawdata_option & _DATA_BIT_32) { + ret = (p_cur_rawdata->p_data_buf[tmp_id * 4]) + + (p_cur_rawdata->p_data_buf[tmp_id * 4 + 1] << 8) + + (p_cur_rawdata->p_data_buf[tmp_id * 4 + 2] + << 16) + + (p_cur_rawdata->p_data_buf[tmp_id * 4 + 3] << 24); + } + } + return ret; +} +/******************************************************************************* +* Function Name : get_key_need_check +* Description : judge specialized key whether need check or not +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 key_id(key id) +* Return : s32(0:not need check 1:need check) +*******************************************************************************/ +extern s32 get_key_need_check(IN PST_TEST_ITEM p_test_item, IN u16 key_id) +{ + s32 ret = 0; + u16 key_pos = 0; + + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + + if (key_id < p_dev->key_num) { + key_pos = p_dev->key_pos_arr[key_id] - 1; + if (p_rawdata_test_param->p_raw_key_limit->p_need_check_key + ->p_data_buf[key_pos] == TP_FLAG_KEY_NEED_CHECK) { + ret = 1; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_key_upper_limit +* Description : get key upper limit +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u8 key_id(key id) +* Return : s32 +*******************************************************************************/ +extern s32 get_key_upper_limit(IN PST_TEST_ITEM p_test_item, IN u8 key_id) +{ + s32 ret = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + u16 i = 0; + u16 node_id; + PST_TP_DEV p_tp_dev = p_test_item->p_tp_dev; + PST_RAWDATA_SPECIAL_NODE_PARAM p_spec_node = + p_rawdata_test_param->p_special_node; + ret = p_rawdata_test_param->p_raw_key_limit->upper_limit; + for (i = 0; i < p_spec_node->data_len; i++) { + node_id = p_spec_node->p_data_buf[i].node_id; + if ((node_id >= p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num) && + node_id - p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num == + key_id) { + ret = p_spec_node->p_data_buf[i].high_raw_limit; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_key_lower_limit +* Description : get key lower limit +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u8 key_id(key id) +* Return : s32 +*******************************************************************************/ +extern s32 get_key_lower_limit(IN PST_TEST_ITEM p_test_item, IN u8 key_id) +{ + s16 ret = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + u16 i = 0; + u16 node_id; + PST_TP_DEV p_tp_dev = p_test_item->p_tp_dev; + PST_RAWDATA_SPECIAL_NODE_PARAM p_spec_node = + p_rawdata_test_param->p_special_node; + ret = p_rawdata_test_param->p_raw_key_limit->lower_limit; + for (i = 0; i < p_spec_node->data_len; i++) { + node_id = p_spec_node->p_data_buf[i].node_id; + if ((node_id >= p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num) && + (node_id - p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num == + key_id)) { + ret = p_spec_node->p_data_buf[i].low_raw_limit; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_uniform_value +* Description : get uniform value(amplify 1000) +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_uniform_value(IN PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + s32 max_data_tmp = 0; + s32 min_data_tmp = 0; + s32 data_tmp = 0; + u16 i = 0; + u8 flag = 0; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + for (i = 0; i < p_dev->sc_drv_num * p_dev->sc_sen_num; i++) { + if (get_chn_need_check(p_test_item, i)) { + data_tmp = get_chn_rawdata(p_test_item, i); + /*//Initialize max_data_tmp and min_data_tmp*/ + if (flag == 0) { + max_data_tmp = data_tmp; + min_data_tmp = max_data_tmp; + flag = 1; + } else { + /*//Update max_data_tmp*/ + if (data_tmp > max_data_tmp) { + max_data_tmp = data_tmp; + } + /*//Update min_data_tmp*/ + if (data_tmp < min_data_tmp) { + min_data_tmp = data_tmp; + } + } + } + } + + /*//avoid 0*/ + if (0 == max_data_tmp) { + max_data_tmp++; + } + if (0 == min_data_tmp) { + min_data_tmp++; + } + ret = (s32)(1000 * min_data_tmp / max_data_tmp); + return ret; +} + +/******************************************************************************* +* Function Name : get_uniform_limit +* Description : get uniform limit +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_uniform_limit(IN PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + ret = p_rawdata_test_param->p_raw_uniform_limit->uniform_limit; + return ret; +} + +/******************************************************************************* +* Function Name : get_rawdata_jitter_value +* Description : get rawdata jitter value limit +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_rawdata_jitter_value(IN PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + s32 tmp_data = 0; + u16 i = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = + (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + for (i = 0; i < p_raw_test_res->p_max_raw_tmp_data->len; i++) { + tmp_data = p_raw_test_res->p_max_raw_tmp_data->p_data_buf[i] - + p_raw_test_res->p_min_raw_tmp_data->p_data_buf[i]; + if (ret < tmp_data) { + ret = tmp_data; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : get_rawdata_jitter_limit +* Description : get rawdata jitter limit +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_rawdata_jitter_limit(IN PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_RAWDATA_TEST_PARAM p_rawdata_test_param = + (PST_RAWDATA_TEST_PARAM)(p_test_item->param.ptr_param); + ret = p_rawdata_test_param->p_raw_jitter_limit->jitter_limit; + return ret; +} + +//-----------------------------diffdata as data source start-------------------------------// +// +/******************************************************************************* +* Function Name : get_chn_diffdata +* Description : get specialized channel diffdata +* Input : PST_TEST_ITEM p_test_item(item pointer) +: u16 chn_id(channel index) +* Output : none +* Return : s32 +*******************************************************************************/ +extern s32 get_chn_diffdata(PST_TEST_ITEM p_test_item, u16 chn_id) +{ + s32 ret = 0; + PST_CUR_DIFFDATA p_cur_diffdata = + (PST_CUR_DIFFDATA)(p_test_item->cur_data.ptr_cur_data); + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + u16 len = p_dev->sc_sen_num * p_dev->sc_drv_num; + + /*//data is little-endian after reshaping*/ + if (len > chn_id) { + if (p_dev->diffdata_option & _DATA_BIT_8) { + ret = p_cur_diffdata->p_data_buf[chn_id]; + } else if (p_dev->diffdata_option & _DATA_BIT_16) { + ret = (s16)((p_cur_diffdata->p_data_buf[chn_id * 2]) + + (p_cur_diffdata->p_data_buf[chn_id * 2 + 1] + << 8)); + } else if (p_dev->diffdata_option & _DATA_BIT_32) { + ret = (p_cur_diffdata->p_data_buf[chn_id * 4]) + + (p_cur_diffdata->p_data_buf[chn_id * 4 + 1] + << 8) + + (p_cur_diffdata->p_data_buf[chn_id * 4 + 2] + << 16) + + (p_cur_diffdata->p_data_buf[chn_id * 4 + 3] + << 24); + } + } + return ret; +} + +#ifdef __cplusplus +} +#endif + +/******************************************************************************* +* Function Name : init_for_buffer +* Description : initialize temp buffer with 0 +* Input : u8* p_buf +: u16 buf_size +* Output : u8* p_buf +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +static s32 init_for_buffer(u8 *p_buf, u16 buf_size) +{ + s32 ret = 1; + u16 i = 0; + for (i = 0; i < buf_size; i++) { + p_buf[i] = 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : get_need_check +* Description : judge channel or key whether need check or not +* Input : PST_TEST_ITEM p_test_item +: u16 node_num +: s32 beyond_limit_status +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:not need check 1:need check) +*******************************************************************************/ +static s32 get_need_check(IN_OUT PST_TEST_ITEM p_test_item, IN u16 id, + IN s32 beyond_limit_status) +{ + if ((beyond_limit_status == KEY_BEYOND_UPPER_LIMIT) || + (beyond_limit_status == KEY_BEYOND_LOWER_LIMIT)) { + return get_key_need_check(p_test_item, id); + } else { + return get_chn_need_check(p_test_item, id); + } +} + +/******************************************************************************* +* Function Name : analyze_test_item_res +* Description : analyze rawdata subitem test result +* Input : PST_TEST_ITEM p_test_item +: s32 beyond_limit_status +: u8* p_beyond_limit_num +: u16 node_num +* Output : PST_TEST_ITEM p_test_item +* Return : s32(beyond_limit_satus:test result is unstable 0:others) +*******************************************************************************/ +static s32 analyze_test_item_res(IN_OUT PST_TEST_ITEM p_test_item, + IN s32 beyond_limit_status, + IN u8 *p_beyond_limit_cnt, IN u16 node_num) +{ + s32 ret = beyond_limit_status; + u16 id = 0; + s32 low_ratio = 10 * 0.1; + s32 high_ratio = 10 * 0.9; + PST_RAWDATA_TEST_RES p_raw_test_res = NULL; + u16 cur_frame_id = 0; + s32 tmp_open_test_result = 0; + p_raw_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + cur_frame_id = p_raw_test_res->total_frame_cnt; + tmp_open_test_result = p_raw_test_res->open_test_result; + tmp_open_test_result &= ~beyond_limit_status; + for (id = 0; id < node_num; id++) { + if (get_need_check(p_test_item, id, beyond_limit_status)) { + if (p_beyond_limit_cnt[id] * 10 >= + high_ratio * cur_frame_id) { + p_beyond_limit_cnt[id] |= 0x80; + tmp_open_test_result |= beyond_limit_status; + ret = 0; + } else if (p_beyond_limit_cnt[id] * 10 > + low_ratio * cur_frame_id) { + p_beyond_limit_cnt[id] |= 0x80; + tmp_open_test_result |= beyond_limit_status; + if (cur_frame_id >= TOTAL_FRAME_NUM_MAX) { + ret = 0; + } + } else { + ret = 0; + } + } + } + p_raw_test_res->open_test_result = tmp_open_test_result; + return ret; +} + +/******************************************************************************* +* Function Name : clear_rawtest_res_buf +* Description : clear_rawtest_res_buf +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(1:ok 0:fail) +*******************************************************************************/ +static s32 clear_rawtest_res_buf(IN_OUT PST_TEST_ITEM p_test_item) +{ + PST_RAWDATA_TEST_RES p_test_res = + (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + PST_TP_DEV p_dev = (PST_TP_DEV)p_test_item->p_tp_dev; + u16 buf_size = p_dev->sc_drv_num * p_dev->sc_sen_num; + u16 i = 0; + u8 key_buf_size = p_dev->key_num; + PST_CUR_RAWDATA p_cur_data = + (PST_CUR_RAWDATA)p_test_item->cur_data.ptr_cur_data; + + p_cur_data->cur_frame_id = 0; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_NG; + for (i = 0; i < p_test_res->item_res_header.test_item_err_code.len; + i++) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[i] = RAWDATA_TEST_SUCCESSFULLY; + } + p_test_res->open_test_result = OPEN_TEST_PASS; + p_test_res->total_frame_cnt = 0; + + /*//max data record*/ + for (i = 0; i < buf_size; i++) { + p_test_res->p_max_raw_tmp_data->p_data_buf[i] = 0; + } + + /*/min data record*/ + for (i = 0; i < buf_size; i++) { + p_test_res->p_min_raw_tmp_data->p_data_buf[i] = 0x7FFFFFFF; + } + + init_for_buffer(p_test_res->p_beyond_rawdata_upper_limit_cnt, buf_size); + init_for_buffer(p_test_res->p_beyond_rawdata_lower_limit_cnt, buf_size); + init_for_buffer(p_test_res->p_beyond_jitter_limit_cnt, buf_size); + init_for_buffer(p_test_res->p_beyond_accord_limit_cnt, buf_size); + init_for_buffer(p_test_res->p_beyond_offset_limit_cnt, buf_size); + init_for_buffer(p_test_res->p_beyond_key_upper_limit_cnt, key_buf_size); + init_for_buffer(p_test_res->p_beyond_key_lower_limit_cnt, key_buf_size); + p_test_res->beyond_uniform_limit_cnt = 0; + return 1; +} + +/******************************************************************************* +* Function Name : analyze_rawtest_res +* Description : analyze rawdata test result +* Input : u8 offse_and_accord_flag +* : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:test result is pass 1:test result is fail 2:test result is unstable) +*******************************************************************************/ +static s32 analyze_rawtest_res(IN u8 offse_and_accord_flag, + IN_OUT PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + u16 i = 0; + s32 test_res_unstb = 0; + s32 test_end = 0; + u16 node_num = 0; + u8 key_num = 0; + s32 low_ratio = 10 * 0.1; + s32 high_ratio = 10 * 0.9; + u8 id_tmp = 0; + + PST_RAWDATA_TEST_RES p_test_res = NULL; + + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + node_num = p_dev->sc_sen_num * p_dev->sc_drv_num; + p_test_res = (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + key_num = p_dev->key_num; + + /*//cover error code*/ + for (i = 0; i < p_test_res->item_res_header.test_item_err_code.len; + i++) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[i] = RAWDATA_TEST_SUCCESSFULLY; + } + + /*//analyze rawdata upper limit*/ + if ((p_test_res->open_test_result & BEYOND_RAWDATA_UPPER_LIMIT) != 0) { + test_res_unstb |= analyze_test_item_res( + p_test_item, BEYOND_RAWDATA_UPPER_LIMIT, + p_test_res->p_beyond_rawdata_upper_limit_cnt, node_num); + + if (0 == (test_res_unstb & BEYOND_RAWDATA_UPPER_LIMIT) && + (p_test_res->open_test_result & + BEYOND_RAWDATA_UPPER_LIMIT) != 0) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_RAWDATA_MAX_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_MAX_LIMIT; + } + } + /*//analyze rawdata lower limit*/ + if ((p_test_res->open_test_result & BEYOND_RAWDATA_LOWER_LIMIT) != 0) { + test_res_unstb |= analyze_test_item_res( + p_test_item, BEYOND_RAWDATA_LOWER_LIMIT, + p_test_res->p_beyond_rawdata_lower_limit_cnt, node_num); + + if (0 == (test_res_unstb & BEYOND_RAWDATA_LOWER_LIMIT) && + (p_test_res->open_test_result & + BEYOND_RAWDATA_LOWER_LIMIT) != 0) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_RAWDATA_MIN_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_MIN_LIMIT; + } + } + /*//analyze key upper limit*/ + if ((p_test_res->open_test_result & KEY_BEYOND_UPPER_LIMIT) != 0) { + test_res_unstb |= analyze_test_item_res( + p_test_item, KEY_BEYOND_UPPER_LIMIT, + p_test_res->p_beyond_key_upper_limit_cnt, key_num); + + if (0 == (test_res_unstb & KEY_BEYOND_UPPER_LIMIT) && + (p_test_res->open_test_result & KEY_BEYOND_UPPER_LIMIT) != + 0) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_KEYDATA_MAX_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_KEY_MAX_LIMIT; + } + } + /*//analyze key lower limit*/ + if ((p_test_res->open_test_result & KEY_BEYOND_LOWER_LIMIT) != 0) { + test_res_unstb |= analyze_test_item_res( + p_test_item, KEY_BEYOND_LOWER_LIMIT, + p_test_res->p_beyond_key_lower_limit_cnt, key_num); + + if (0 == (test_res_unstb & KEY_BEYOND_LOWER_LIMIT) && + (p_test_res->open_test_result & KEY_BEYOND_LOWER_LIMIT) != + 0) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_KEYDATA_MIN_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_KEY_MIN_LIMIT; + } + } + /*//analyze offset limit*/ + if ((p_test_res->open_test_result & BEYOND_OFFSET_LIMIT) != 0) { + test_res_unstb |= analyze_test_item_res( + p_test_item, BEYOND_OFFSET_LIMIT, + p_test_res->p_beyond_offset_limit_cnt, node_num); + + if (0 == (test_res_unstb & BEYOND_OFFSET_LIMIT) && + (p_test_res->open_test_result & BEYOND_OFFSET_LIMIT) != 0) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_OFFSET_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_OFFSET_LIMIT; + } + } + + /*//analyze uniform limit*/ + if ((p_test_res->open_test_result & BEYOND_UNIFORMITY_LIMIT) != 0) { + p_test_res->open_test_result &= ~BEYOND_UNIFORMITY_LIMIT; + if (p_test_res->beyond_uniform_limit_cnt * 10 >= + high_ratio * p_test_res->total_frame_cnt) { + p_test_res->open_test_result |= BEYOND_UNIFORMITY_LIMIT; + } else if (p_test_res->beyond_uniform_limit_cnt * 10 > + low_ratio * p_test_res->total_frame_cnt) { + p_test_res->open_test_result |= BEYOND_UNIFORMITY_LIMIT; + test_res_unstb |= BEYOND_UNIFORMITY_LIMIT; + } + + if (0 == (test_res_unstb & BEYOND_UNIFORMITY_LIMIT) && + (p_test_res->open_test_result & BEYOND_UNIFORMITY_LIMIT) != + 0) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_UNIFORMITY_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_UNIFORM_LIMIT; + } + } + + /*//analyze accord limit*/ + if ((p_test_res->open_test_result & BEYOND_ACCORD_LIMIT) != 0) { + test_res_unstb |= analyze_test_item_res( + p_test_item, BEYOND_ACCORD_LIMIT, + p_test_res->p_beyond_accord_limit_cnt, node_num); + + if (0 == (test_res_unstb & BEYOND_ACCORD_LIMIT) && + (p_test_res->open_test_result & BEYOND_ACCORD_LIMIT) != 0) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_ACCORD_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_ACCORD_LIMIT; + } + } + + /*// analyze accord and offset limit*/ + if (offse_and_accord_flag == 0x03) { + u32 tmp_accord_res = 0; + for (i = 0; i < node_num; i++) { + if (get_chn_need_check(p_test_item, i)) { + if ((p_test_res->p_beyond_accord_limit_cnt[i] & + 0x80) != 0) { + if ((p_test_res->p_beyond_offset_limit_cnt + [i] & + 0x80) != 0) { + tmp_accord_res |= + BEYOND_ACCORD_LIMIT; + } else { + p_test_res + ->p_beyond_accord_limit_cnt + [i] &= 0x7f; + } + } + } + } + if (tmp_accord_res == 0) { + test_res_unstb &= ~BEYOND_ACCORD_LIMIT; + p_test_res->open_test_result &= ~BEYOND_ACCORD_LIMIT; + + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_ACCORD_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_SUCCESSFULLY; + } + } + + if (p_test_res->open_test_result & BEYOND_JITTER_LIMIT) { + id_tmp = get_arr_id_from_sub_item( + p_test_item, TP_RAWDATA_JITTER_TEST_ITEM_ID); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + RAWDATA_TEST_BEYOND_JITTER_LIMIT; + return 1; + } + test_end = p_test_res->open_test_result; + test_end &= (~FIRST_TEST_FLAG); + if (test_end == OPEN_TEST_PASS) { + ret = 0; + } else if (test_end == test_res_unstb) { + ret = 2; + } else { + ret = 1; + } + return ret; +} + +/******************************************************************************* +* Function Name : modify_statistic_data +* Description : modify max and min avg data +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +static s32 modify_statistic_data(IN_OUT PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + u16 i = 0; + s32 curval; + u16 cnt = 0; + PST_RAWDATA_TEST_RES p_raw_test_res = + (PST_RAWDATA_TEST_RES)p_test_item->test_res.ptr_res; + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + + p_raw_test_res->raw_avg = 0; + for (i = 0; i < p_dev->rawdata_len; i++) { + if (get_chn_need_check(p_test_item, i)) { + curval = get_chn_rawdata(p_test_item, i); + p_raw_test_res->raw_avg += curval; + cnt++; + if (curval > + p_raw_test_res->p_max_raw_tmp_data->p_data_buf[i]) { + p_raw_test_res->p_max_raw_tmp_data + ->p_data_buf[i] = curval; + } + + if (curval < + p_raw_test_res->p_min_raw_tmp_data->p_data_buf[i]) { + p_raw_test_res->p_min_raw_tmp_data + ->p_data_buf[i] = curval; + } + } + } + if (0 != cnt) { + p_raw_test_res->raw_avg /= cnt; + } else { + p_raw_test_res->raw_avg = 0; + } + ret = 1; + return ret; +} + +/******************************************************************************* +* Function Name : clear_difftest_res_buf +* Description : clear_difftest_res_buf +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(1:ok 0:fail) +*******************************************************************************/ +static s32 clear_difftest_res_buf(IN_OUT PST_TEST_ITEM p_test_item) +{ + PST_DIFFDATA_TEST_RES p_test_res = + (PST_DIFFDATA_TEST_RES)p_test_item->test_res.ptr_res; + PST_TP_DEV p_dev = (PST_TP_DEV)p_test_item->p_tp_dev; + u16 buf_size = p_dev->sc_drv_num * p_dev->sc_sen_num; + u16 i = 0; + + PST_CUR_DIFFDATA p_cur_data = + (PST_CUR_DIFFDATA)p_test_item->cur_data.ptr_cur_data; + + p_cur_data->cur_frame_id = 0; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_OK; + for (i = 0; i < p_test_res->item_res_header.test_item_err_code.len; + i++) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[i] = DIFFDATA_TEST_SUCCESSFULLY; + } + p_test_res->total_frame_cnt = 0; + + /*//max data record*/ + for (i = 0; i < buf_size && i < p_test_res->p_max_diff_tmp_data->len; + i++) { + p_test_res->p_max_diff_tmp_data->p_data_buf[i] = 0; + } + return 1; +} + +/******************************************************************************* +* Function Name : analyze_difftest_res +* Description : analyze diffdata test result +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:test result is pass 1:test result is fail 2:test result is unstable) +*******************************************************************************/ +static s32 analyze_difftest_res(u8 cur_frame_id, PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + u16 i = 0; + u16 node_num = 0; + u8 id_tmp = 0; + + PST_DIFFDATA_TEST_RES p_test_res = NULL; + PST_DIFFDATA_TEST_PARAM p_param = NULL; + PST_TEST_ITEM p_raw_data_test_item = NULL; + PST_TP_DEV p_dev = NULL; + get_test_item_from_proc_data( + (PST_TEST_PROC_DATA)p_test_item->ptr_test_proc_data, + TP_RAWDATA_TEST_ITEMS_SET_ID, &p_raw_data_test_item); + + p_param = (PST_DIFFDATA_TEST_PARAM)p_test_item->param.ptr_param; + p_test_res = (PST_DIFFDATA_TEST_RES)p_test_item->test_res.ptr_res; + p_dev = p_test_item->p_tp_dev; + node_num = p_dev->sc_sen_num * p_dev->sc_drv_num; + + /*//cover error code*/ + for (i = 0; i < p_test_res->item_res_header.test_item_err_code.len; + i++) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[i] = DIFFDATA_TEST_SUCCESSFULLY; + } + + /*//diff jitter test */ + id_tmp = get_arr_id_from_sub_item(p_test_item, + TP_DIFFDATA_JITTER_TEST_ITEM_ID); + for (i = 0; i < node_num; i++) { + /*//share need_check_node with item 'TP_RAWDATA_TEST_ITEMS_SET_ID'*/ + if (get_chn_need_check(p_raw_data_test_item, i)) { + if (p_test_res->p_max_diff_tmp_data->p_data_buf[i] > + p_param->p_diff_jitter_limit->diff_jitter_limit) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[id_tmp + 1] = + DIFFTEST_JITTER_BEYOND_LIMIT; + ret = 1; + break; + } + } + } + return ret; +} + +/******************************************************************************* +* Function Name : modify_diff_statistic_data +* Description : modify statistic data of diffdata +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +static s32 modify_diff_statistic_data(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + u16 i = 0; + s32 curval; + PST_DIFFDATA_TEST_RES p_test_res = + (PST_DIFFDATA_TEST_RES)p_test_item->test_res.ptr_res; + + PST_TP_DEV p_dev = p_test_item->p_tp_dev; + PST_TEST_ITEM p_raw_data_test_item = NULL; + get_test_item_from_proc_data( + (PST_TEST_PROC_DATA)p_test_item->ptr_test_proc_data, + TP_RAWDATA_TEST_ITEMS_SET_ID, &p_raw_data_test_item); + + if (NULL == p_test_res->p_max_diff_tmp_data) { + goto MODIFY_END; + } + + for (i = 0; i < p_dev->diffdata_len; i++) { + /*//share need_check_node with item 'TP_RAWDATA_TEST_ITEMS_SET_ID'*/ + if (get_chn_need_check(p_raw_data_test_item, i)) { + curval = get_chn_diffdata(p_test_item, i); + if (curval > + p_test_res->p_max_diff_tmp_data->p_data_buf[i]) { + p_test_res->p_max_diff_tmp_data->p_data_buf[i] = + curval; + } + } + } + ret = 1; + +MODIFY_END: + return ret; +} + +/*//-----------------------------diffdata as data source end-------------------------------*/ + +#endif \ No newline at end of file diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.h new file mode 100644 index 000000000000..d146f7b589b2 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test.h @@ -0,0 +1,227 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_open_test.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : touch panel circuit open test +data 1-dimension means drv data +data 2-dimension means sen data + +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_OPEN_TEST_H +#define TP_OPEN_TEST_H + +#include "tp_open_test_param.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*//rawdata test sets error code define*/ +#define RAWDATA_TEST_SUCCESSFULLY 0 + +#define RAWDATA_TEST_BREAK_OUT 1 +#define GET_RAW_PARAM_ERR 2 +#define SEND_TEST_CONFIG_ERR 3 +#define RAWDATA_TEST_ENTER_MODE_FAIL 4 +#define RAWDATA_TEST_SUB_ITEM_ERR 5 +#define RAWDATA_TEST_GET_BUF_FAIL 6 +#define RAWDATA_TEST_GET_DATA_TIME_OUT 7 +#define RAWDATA_TEST_GET_RES_BUF_FAIL 8 +#define OPEN_HOPPING_ERR 9 +#define ENTER_COORD_MODE_ERR 10 +#define SAVE_CUR_DATA_ERR 11 + +#define RAWDATA_TEST_BEYOND_MAX_LIMIT 12 +#define RAWDATA_TEST_BEYOND_MIN_LIMIT 13 +#define RAWDATA_TEST_BEYOND_PARAM_LIMIT 14 + +#define RAWDATA_TEST_BEYOND_KEY_MAX_LIMIT 15 +#define RAWDATA_TEST_BEYOND_KEY_MIN_LIMIT 16 +#define RAWDATA_TEST_BEYOND_KEY_PARAM_LIMIT 17 + +#define RAWDATA_TEST_BEYOND_ACCORD_LIMIT 18 +#define RAWDATA_TEST_BEYOND_OFFSET_LIMIT 19 +#define RAWDATA_TEST_BEYOND_UNIFORM_LIMIT 20 +#define RAWDATA_TEST_BEYOND_JITTER_LIMIT 21 +#define RAWDATA_TEST_FAIL 22 + +/*//diffdata error code*/ +#define DIFFDATA_TEST_SUCCESSFULLY 0 +#define DIFFDATA_TEST_BREAK_OUT 1 +#define GET_DIFF_PARAM_ERR 2 +#define DIFFDATA_TEST_ENTER_MODE_FAIL 3 +#define DIFFDATA_TEST_BEFORE_FUNC_FAIL 4 +#define DIFFDATA_TEST_GET_DATA_TIME_OUT 5 +#define DIFFTEST_JITTER_BEYOND_LIMIT 6 + +/*//Max Frame NUm*/ +#define TOTAL_FRAME_NUM_MAX 64 + +/*//current rawdata define*/ +typedef struct CUR_RAWDATA { + u8 cur_frame_id; + u16 data_len; /*//rawdata len*/ + u8 *p_data_buf; /*//storage rawdata by byte*/ +} ST_CUR_RAWDATA, *PST_CUR_RAWDATA; + +/*//-------------------------------------RAWDATA TEST RESULT SATRT-------------------------------------*/ +/*//rawdata test tmp data*/ +typedef struct RAW_TMP_DATA { + u16 len; + s32 *p_data_buf; +} ST_RAW_TMP_DATA, *PST_RAW_TMP_DATA; + +#define OPEN_TEST_PASS 0x0000 +#define BEYOND_RAWDATA_UPPER_LIMIT 0x0001 +#define BEYOND_RAWDATA_LOWER_LIMIT 0x0002 +#define KEY_BEYOND_UPPER_LIMIT 0x1000 +#define KEY_BEYOND_LOWER_LIMIT 0x2000 +#define BEYOND_ACCORD_LIMIT 0x0004 +#define BEYOND_OFFSET_LIMIT 0x0008 +#define BEYOND_JITTER_LIMIT 0x0010 +#define BEYOND_UNIFORMITY_LIMIT 0x00800000 +#define FIRST_TEST_FLAG 0x80000000 +/*//rawdata test result*/ +typedef struct RAWDATA_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + s32 raw_avg; + u8 total_frame_cnt; + + PST_RAW_TMP_DATA p_max_raw_tmp_data; + PST_RAW_TMP_DATA p_min_raw_tmp_data; + /*//test item test fail count*/ + u8 *p_beyond_rawdata_upper_limit_cnt; + u8 *p_beyond_rawdata_lower_limit_cnt; + u8 *p_beyond_jitter_limit_cnt; + u8 *p_beyond_accord_limit_cnt; + u8 *p_beyond_offset_limit_cnt; + u8 *p_beyond_key_upper_limit_cnt; + u8 *p_beyond_key_lower_limit_cnt; + u8 beyond_uniform_limit_cnt; + /*//the highest bit set if need another test*/ + s32 open_test_result; + +} ST_RAWDATA_TEST_RES, *PST_RAWDATA_TEST_RES; + +/*//rawdata test special callback set*/ +typedef struct RAWDATA_TEST_CALLBACK_SET { + TEST_CALLBACK_PTR ptr_save_cur_data_func; + ptr32 ptr_save_cur_data_func_param; +} ST_RAWDATA_TEST_CALLBACK_SET, *PST_RAWDATA_TEST_CALLBACK_SET; +/*//-------------------------------------RAWDATA TEST RESULT END-------------------------------------*/ + +typedef ST_CUR_RAWDATA ST_CUR_DIFFDATA; +typedef PST_CUR_RAWDATA PST_CUR_DIFFDATA; + +typedef ST_RAWDATA_TEST_CALLBACK_SET ST_DIFFDATA_TEST_CALLBACK_SET; +typedef PST_RAWDATA_TEST_CALLBACK_SET PST_DIFFDATA_TEST_CALLBACK_SET; + +typedef ST_RAW_TMP_DATA ST_DIFF_TMP_DATA; +typedef PST_RAW_TMP_DATA PST_DIFF_TMP_DATA; + +/*//-------------------------------------DIFFDATA TEST RESULT SATRT-------------------------------------*/ +/*//diffdata test result*/ +typedef struct DIFFDATA_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + u8 total_frame_cnt; + + PST_DIFF_TMP_DATA p_max_diff_tmp_data; +} ST_DIFFDATA_TEST_RES, *PST_DIFFDATA_TEST_RES; +/*//-------------------------------------DIFFDATA TEST RESULT END-------------------------------------*/ + +/*************************************Public methods start********************************************/ + +/*//-----------------------------rawdata as data source---------------------------*/ + +/*//rawdata test */ +extern s32 rawdata_test_sets_func(ptr32 p_data); + +/*//sub test items*/ +/*//rawdata test function*/ +extern s32 rawdata_max_test_func(ptr32 p_data); +extern s32 rawdata_min_test_func(ptr32 p_data); +/*//accord test function*/ +extern s32 rawdata_accord_test_func(ptr32 p_data); +/*//keydata test function*/ +extern s32 keydata_max_test_func(ptr32 p_data); +extern s32 keydata_min_test_func(ptr32 p_data); +/*//rawdata jitter test function*/ +extern s32 rawdata_jitter_test_func(ptr32 p_data); +/*//rawdata uniform test function*/ +extern s32 rawdata_uniform_test_func(ptr32 p_data); +/*//rawdata offset test function*/ +extern s32 rawdata_offset_test_func(ptr32 p_data); + +/*//get rawdata*/ +extern s32 get_rawdata(PST_TP_DEV p_tp_dev, u16 time_out_ms, u8 b_filter_data, + PST_CUR_RAWDATA p_cur_data); + +/*//-----------------------------diffdata as data source---------------------------*/ +extern s32 diffdata_test_sets_func(ptr32 p_data); +extern s32 diffdata_jitter_test_func(ptr32 p_data); + +/*//get diffdata */ +extern s32 get_diffdata(PST_TP_DEV p_dev, u16 time_out_ms, u8 b_filter_data, + PST_CUR_DIFFDATA p_cur_data); + +/*//judge specialized channel whether need check or not*/ +extern s32 get_chn_need_check(PST_TEST_ITEM p_test_item, u16 chn_id); + +/*//get specialized channel rawdata*/ +extern s32 get_chn_rawdata(PST_TEST_ITEM p_test_item, u16 chn_id); +/*//rawdata_limit_test_func parameter*/ +extern s32 get_chn_upper_limit(PST_TEST_ITEM p_test_item, u16 chn_id); +extern s32 get_chn_lower_limit(PST_TEST_ITEM p_test_item, u16 chn_id); + +extern u8 get_adjacent_node(u16 node_id, PST_TP_DEV p_dev, s16 *p_arr); +/*//---------------accord test------------*/ +/*//get chn accord(*1000)*/ +extern s32 get_chn_accord(PST_TEST_ITEM p_test_item, u16 chn_id); +/*//1000*/ +extern s32 get_chn_accord_limit(PST_TEST_ITEM p_test_item, u16 chn_id); +extern u16 get_chn_accord_option(PST_TEST_ITEM p_test_item, u16 chn_id); + +/*//-----------------keydata test--------------------*/ +/*//get keydata*/ +extern s32 get_keydata(IN PST_TEST_ITEM p_test_item, IN u8 key_id); +/*//judge specialized key whether need check or not*/ +extern s32 get_key_need_check(PST_TEST_ITEM p_test_item, u16 key_id); +/*//key parameter limit*/ +extern s32 get_key_upper_limit(PST_TEST_ITEM p_test_item, u8 key_id); +extern s32 get_key_lower_limit(PST_TEST_ITEM p_test_item, u8 key_id); + +/*//-----------------uniform test-------------------*/ +extern s32 get_uniform_value(PST_TEST_ITEM p_test_item); +extern s32 get_uniform_limit(PST_TEST_ITEM p_test_item); + +/*//---------------rawdata jitter test---------------*/ +extern s32 get_rawdata_jitter_value(PST_TEST_ITEM p_test_item); +extern s32 get_rawdata_jitter_limit(PST_TEST_ITEM p_test_item); +extern s32 get_chn_offset(IN PST_TEST_ITEM p_test_item, IN u16 chn_id); +extern s32 get_chn_offset_limit(IN PST_TEST_ITEM p_test_item, IN u16 chn_id); + +/*//reshape data*/ +extern void reshape_data(u8 data_option, PST_TP_DEV p_tp_dev, + PST_CUR_RAWDATA p_cur_data); +extern u8 get_data_size(u8 data_option); + +/*//get specialized channel diffdata*/ +extern s32 get_chn_diffdata(PST_TEST_ITEM p_test_item, u16 chn_id); + +/*************************************Public methods end********************************************/ +#ifdef __cplusplus +} +#endif +/*************************************private methods start********************************************/ +/*//-----------------------------rawdata as data source start---------------------------------*/ +/*//get adjacent node*/ +#define ADJ_POS_UP 0 +#define ADJ_POS_DOWN 1 +#define ADJ_POS_LEFT 2 +#define ADJ_POS_RIGHT 3 +/*************************************private methods end********************************************/ +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test_param.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test_param.h new file mode 100644 index 000000000000..ce8d6bb10bc9 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_open_test_param.h @@ -0,0 +1,132 @@ +#ifndef TP_OPEN_TEST_PARAM_H +#define TP_OPEN_TEST_PARAM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "test_item_def.h" + +/*//need check node define*/ +typedef struct NEED_CHECK_NODE { + u16 data_len; + u8 *p_data_buf; +} ST_NEED_CHECK_NODE, *PST_NEED_CHECK_NODE; + +/*//----------accord_option----------*/ +#define ACCORD_CALC_UPON 0x0001 +#define ACCORD_CALC_DOWN 0x0002 +#define ACCORD_CALC_LEFT 0x0004 +#define ACCORD_CALC_RIGHT 0x0008 + +#define DEF_ACCORD_CALC \ + (ACCORD_CALC_UPON | ACCORD_CALC_DOWN | ACCORD_CALC_LEFT | \ + ACCORD_CALC_RIGHT) + +/*//special node define*/ +typedef struct SPECIAL_NODE_DEF { + u16 node_id; + s32 high_raw_limit; + s32 low_raw_limit; + s32 accord_limit; + s32 offset_limit; + u16 accord_option; +} ST_SPECIAL_NODE_DEF, *PST_SPECIAL_NODE_DEF; + +/*//rawdata special node parameter define*/ +typedef struct RAWDATA_SPECIAL_NODE_PARAM { + u16 data_len; + PST_SPECIAL_NODE_DEF p_data_buf; +} ST_RAWDATA_SPECIAL_NODE_PARAM, *PST_RAWDATA_SPECIAL_NODE_PARAM; + +/*//rawdata limit test parameter*/ +typedef struct RAWDATA_LIMIT_PARAM { + s32 upper_limit; + s32 lower_limit; +} ST_RAWDATA_LIMIT_PARAM, *PST_RAWDATA_LIMIT_PARAM; + +/*//rawdata accord limit test parameter*/ +typedef struct RAW_ACCORD_LIMIT_PARAM { + s32 accord_limit; + u16 accord_option; +} ST_RAW_ACCORD_LIMIT_PARAM, *PST_RAW_ACCORD_LIMIT_PARAM; + +/*//rawdata offset limit test parameter*/ +typedef struct RAW_OFFSET_LIMIT_PARAM { + s32 offset_limit; +} ST_RAW_OFFSET_LIMIT_PARAM, *PST_RAW_OFFSET_LIMIT_PARAM; + +/*//rawdata jitter limit test parameter*/ +typedef struct RAW_JITTER_LIMIT_PARAM { + s32 jitter_limit; +} ST_RAW_JITTER_LIMIT_PARAM, *PST_RAW_JITTER_LIMIT_PARAM; + +/*//rawdata uniform limit test parameter*/ +typedef struct RAW_UNIFORM_LIMIT_PARAM { + s32 uniform_limit; +} ST_RAW_UNIFORM_LIMIT_PARAM, *PST_RAW_UNIFORM_LIMIT_PARAM; + +/*//rawdata key limit test parameter*/ +typedef struct NEED_CHECK_KEY { + u16 len; + u8 *p_data_buf; +} ST_NEED_CHECK_KEY, *PST_NEED_CHECK_KEY; +typedef struct RAW_KEY_LIMIT_PARAM { + s32 upper_limit; + s32 lower_limit; + PST_NEED_CHECK_KEY p_need_check_key; +} ST_RAW_KEY_LIMIT_PARAM, *PST_RAW_KEY_LIMIT_PARAM; + +/*//this struct is used for +(1)rawdata limit test +(2)accord limit test +(3)offset limit test +(4)rawdata jitter test +(5)uniform test +(6)key test +rawdata limit paramter define*/ +typedef struct RAWDATA_TEST_PARAM { + /*//In arm,the pointers follows below equal flash address + //In Pc,the pointers point special struct*/ + + /*//need check node*/ + PST_NEED_CHECK_NODE p_need_check_node; + + /*//special node*/ + PST_RAWDATA_SPECIAL_NODE_PARAM p_special_node; + + /*//rawdata limit parameter*/ + PST_RAWDATA_LIMIT_PARAM p_rawdata_limit; + + /*//rawdata acoord limit parameter*/ + PST_RAW_ACCORD_LIMIT_PARAM p_raw_accord_limit; + + /*//raw offset limit parameter*/ + PST_RAW_OFFSET_LIMIT_PARAM p_raw_offset_limit; + + /*//raw jitter limit parameter*/ + PST_RAW_JITTER_LIMIT_PARAM p_raw_jitter_limit; + + /*//raw uniform limit parameter*/ + PST_RAW_UNIFORM_LIMIT_PARAM p_raw_uniform_limit; + + /*//keydata limit parameter*/ + PST_RAW_KEY_LIMIT_PARAM p_raw_key_limit; + +} ST_RAWDATA_TEST_PARAM, *PST_RAWDATA_TEST_PARAM; + +/*//diff jitter limit parameter*/ +typedef struct DIFF_JITTER_LIMIT_PARAM { + s32 diff_jitter_limit; +} ST_DIFF_JITTER_LIMIT_PARAM, *PST_DIFF_JITTER_LIMIT_PARAM; + +/*//diffdata test parameter*/ +typedef struct DIFFDATA_TEST_PARAM { + PST_DIFF_JITTER_LIMIT_PARAM p_diff_jitter_limit; +} ST_DIFFDATA_TEST_PARAM, *PST_DIFFDATA_TEST_PARAM; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_product_id_def.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_product_id_def.h new file mode 100644 index 000000000000..1bc85b42283c --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_product_id_def.h @@ -0,0 +1,66 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_product_id_def.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 12/31/2017 +* Description : touch panel product id define +*******************************************************************************/ +#ifndef TP_PRODUCT_ID_DEF_H +#define TP_PRODUCT_ID_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*//this file must be used in arm code +//define chip main type +//we plan use 2 bytes store it,so we can distinguish 65536 chip main types.*/ +#define TP_GT900 0x0000 +#define TP_GT9P 0x0001 +#define TP_GT9L 0x0002 +#define TP_GT9PT 0x0003 +#define TP_BOSTON 0x0004 +#define TP_NANJING 0x0005 +#define TP_NORMANDY 0x0006 +#define TP_ALTO 0x0007 +#define TP_PHOENIX 0x0008 +#define TP_OSLO 0x0009 +#define TP_NORMANDY_L 0x000A + +/*//we plan use two bytes store it,so we can distinguish 65536 chip sub types.*/ +/*//TP_GT900 sub type*/ +#define TP_GT915 0x0000 +#define TP_GT9157 0x0001 + +/*//TP_GT9P sub type*/ +#define TP_GT1151 0x0000 +#define TP_GT9286 0x0001 + +/*//TP_GT9L sub type*/ +#define TP_GT5668 0x0000 +#define TP_GT5663 0x0001 +#define TP_GT5688 0x0002 + +/*//TP_GT9PT sub type*/ +#define TP_GT1158 0x0000 +#define TP_GT7288 0x0001 + +/*//TP_NORMANDY sub type*/ +#define TP_GT9886 0x0001 /*//normal iic*/ +#define TP_GT9886S 0x0002 /*//GT9886S spi*/ + +/*//TP_PHOENIX sub type*/ +#define TP_GT7387P 0x0001 +#define TP_GT7385P 0x0002 +#define TP_GT7389 0x0003 +#define TP_GT7387 0x0004 +#define TP_GT7385 0x0005 + +/*//TP_OSLO sub type*/ +#define TP_GT6861 0x0001 +#define TP_GT6861P 0x0002 + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.c new file mode 100644 index 000000000000..55b5af0d9058 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.c @@ -0,0 +1,460 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : short_test_func.c +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : We use this file unify a interface for short test +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "simple_mem_manager.h" +#include "tp_short_test.h" + +#include "normandy_short_test.h" +#include "tp_test_general_error_code_def.h" +#include "test_proc.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* Function Name : short_test_func +* Description : short test +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : s32(0:test error 1:ok) +*******************************************************************************/ +extern s32 short_test_func(IN_OUT ptr32 p_data) +{ + s32 ret = 0; + u16 err_code = SHORT_TEST_NONE_ERROR; + PST_TEST_ITEM p_test_item = (PST_TEST_ITEM)p_data; + PST_SHORT_TEST_RES p_test_res = NULL; + + /*//-----------------Judge parameter----------------*/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto SHORTTEST_END; + } + /*//prepared for test*/ + if (NULL != p_test_item->ptr_test_item_before_func) { + ret = p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (0 == ret) { + board_print_error( + "[short test]callback function test before error!\n"); + err_code = TEST_BEFORE_FUNC_FAIL; + goto SHORTTEST_END; + } + } + + p_test_res = (PST_SHORT_TEST_RES)p_test_item->test_res.ptr_res; + p_test_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = + SHORT_TEST_NONE_ERROR; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_NG; + + ret = board_disable_dev_status(p_test_item->p_tp_dev); + if (0 == ret) { + board_print_error("[short test]disable device status faild!\n"); + err_code = DISABLE_DEV_STATUS_FAIL; + goto SHORTTEST_END; + } + /*//selecting different branch according to chip id*/ + switch (p_test_item->p_tp_dev->chip_type) { + case TP_NORMANDY: + case TP_OSLO: { + ret = normandy_short_test(p_data); + } break; + default: + board_print_warning( + "chip type (%d) is not exist, please check it", + p_test_item->p_tp_dev->chip_type); + err_code = CHIP_TYPE_NOT_EXIST; + break; + } + err_code = p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0]; + +SHORTTEST_END: + + /*// recovery chip on normal mode*/ + ret = short_test_end(p_test_item); + if (ret == 0) { + board_print_warning("[short test]recovry chip status error!\n"); + err_code = SHORT_TEST_END_FAIL; + } + /*//notify test result*/ + if (p_test_item->ptr_test_item_finished_func) { + ret = p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param); + if (ret == 0) { + board_print_error( + "[short test]callback function after test error!\n"); + err_code = TEST_FINISH_FUNC_FAIL; + } + } + if ((err_code == SHORT_TEST_NONE_ERROR) || + (err_code == SHORT_TEST_EXIST_SHORT)) { + ret = 1; + } else { + ret = 0; + } + + return ret; +} + +/******************************************************************************* +* Function Name : clear_short_mess_in_res +* Description : clear_short_mess_in_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 clear_short_mess_in_res(IN_OUT PST_TEST_ITEM p_test_item) +{ + PST_SHORT_TEST_RES p_short_res = + (PST_SHORT_TEST_RES)p_test_item->test_res.ptr_res; + p_short_res->short_num = 0; + p_short_res->item_res_header.test_id = p_test_item->test_item_id; + p_short_res->item_res_header.test_status = TEST_START; + p_short_res->item_res_header.test_result = TEST_OK; + p_short_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = + SHORT_TEST_NONE_ERROR; + return 1; +} + +/******************************************************************************* +* Function Name : store_short_mess_in_res +* Description : store short message in result +* Input : s32 chn1 +* Input : s32 chn2 +* Input : u16 r +* Output : PST_SHORT_TEST_RES p_short_res +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 store_short_mess_in_res(IN u8 chn1, IN u8 chn2, IN u16 r, + OUT PST_SHORT_TEST_RES p_short_res) +{ + s32 ret = 0; + u8 i = 0; + u8 repeat_cnt = 0; + u8 repeat = 0; + if (chn1 == chn2 || p_short_res->short_num >= MAX_SHORT_NUM) { + goto STORE_END; + } + /*//filter repeating data*/ + for (i = 0; i < p_short_res->short_num; i++) { + repeat_cnt = 0; + if (p_short_res->short_mess_arr[4 * i + 0] == chn1) { + repeat_cnt++; + } + + if (p_short_res->short_mess_arr[4 * i + 0] == chn2) { + repeat_cnt++; + } + + if (p_short_res->short_mess_arr[4 * i + 1] == chn1) { + repeat_cnt++; + } + + if (p_short_res->short_mess_arr[4 * i + 1] == chn2) { + repeat_cnt++; + } + if (repeat_cnt >= 2) { + repeat = 1; + } + } + if (repeat == 0) { + p_short_res->short_mess_arr[4 * p_short_res->short_num + 0] = + chn1; + p_short_res->short_mess_arr[4 * p_short_res->short_num + 1] = + chn2; + p_short_res->short_mess_arr[4 * p_short_res->short_num + 2] = + (r >> 8) & 0xFF; + p_short_res->short_mess_arr[4 * p_short_res->short_num + 3] = + r & 0xFF; + if (p_short_res->short_num < MAX_SHORT_NUM) { + p_short_res->short_num++; + } + ret = 1; + } + +STORE_END: + return ret; +} + +/******************************************************************************* +* Function Name : short_test_channel_map +* Description : +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Input : ENUM_CHN_MAP_MODE chn_enum +* Output : none +* Return : void +*******************************************************************************/ +extern void short_test_channel_map(IN ptr32 p_data, + IN ENUM_CHN_MAP_MODE chn_enum) +{ + u8 i = 0; + u8 j = 0; + u8 k = 0; + u8 ch_cnt = 0; + PST_TEST_ITEM p_item = NULL; + PST_SHORT_TEST_RES p_short_res = NULL; + PST_TP_DEV p_dev = NULL; + u8 b_find = 0; + u8 ic_chn_num; + u8 valid_chn_mark[4 * MAX_SHORT_NUM]; + u8 *p_short_mess_tmp = NULL; + + p_item = (PST_TEST_ITEM)p_data; + p_short_res = (PST_SHORT_TEST_RES)p_item->test_res.ptr_res; + p_dev = p_item->p_tp_dev; + + if (p_dev->map_disable == 1) { + return; + } + + memset(valid_chn_mark, 0x00, 4 * p_short_res->short_num); + + for (i = 0; i < p_short_res->short_num * 4; i++) { + if (i % 4 == 2 || i % 4 == 3) { + continue; + } + + switch (chn_enum) { + case TX_RX_SHARED: { + b_find = 0; + j = p_short_res->short_mess_arr[i] & (~CHANNEL_TX_FLAG); + + if (0 == b_find) { + for (ch_cnt = 0; ch_cnt < p_dev->max_drv_num; + ch_cnt++) { + if (p_dev->drv_map[ch_cnt] == j) { + p_short_res->short_mess_arr[i] = + CHANNEL_TX_FLAG | + ch_cnt; + valid_chn_mark[i] = 1; + b_find = 1; + break; + } + } + } + + if (0 == b_find) { + for (ch_cnt = 0; ch_cnt < p_dev->max_sen_num; + ch_cnt++) { + if (p_dev->sen_map[ch_cnt] == j) { + p_short_res->short_mess_arr[i] = + ch_cnt; + valid_chn_mark[i] = 1; + b_find = 1; + break; + } + } + } + } break; + case TX_RX_PACK_ADC: { + j = p_short_res->short_mess_arr[i]; + if ((j & CHANNEL_TX_FLAG) == + CHANNEL_TX_FLAG) { /*//Drv Chancel*/ + + j = j & (~CHANNEL_TX_FLAG); + for (ch_cnt = 0; ch_cnt < p_dev->max_drv_num; + ch_cnt++) { + if (p_dev->drv_map[ch_cnt] == j) { + ic_chn_num = + p_dev->pack_drv_2_adc_map + [ch_cnt]; + if (ch_cnt < + (p_dev->max_drv_num / + 2)) { /*//the first G1 chancel*/ + + for (k = 0; + k < + (p_dev->max_drv_num / + 2); + k++) { + if (p_dev->cfg + [p_dev->drv_start_addr - + p_dev->cfg_start_addr + + k] == + ic_chn_num) { + p_short_res + ->short_mess_arr + [i] = + CHANNEL_TX_FLAG | + j; + valid_chn_mark + [i] = 1; + break; + } + } + } else { /*//the second G1 chancel*/ + for (k = 0; + k < + p_dev->max_drv_num / + 2; + k++) { + if (p_dev->cfg + [p_dev->drv1_start_addr - + p_dev->cfg_start_addr + + k] == + ic_chn_num) { + p_short_res + ->short_mess_arr + [i] = + CHANNEL_TX_FLAG | + j; //((p_dev->max_drv_num / 2) + k); + valid_chn_mark + [i] = 1; + break; + } + } + } + break; + } + } /*//end for (ch_cnt = 0; ch_cnt < p_dev->max_drv_num; ch_cnt++)*/ + } else { /*// Sen Chancel*/ + + for (ch_cnt = 0; ch_cnt < p_dev->max_sen_num; + ch_cnt++) { + if (p_dev->sen_map[ch_cnt] == j) { + ic_chn_num = + p_dev->pack_sen_2_adc_map + [ch_cnt]; + if (ch_cnt < + (p_dev->max_sen_num / + 2)) { /*//the first G1 chancel*/ + for (k = 0; + k < + (p_dev->max_sen_num / + 2); + k++) { + if (p_dev->cfg + [p_dev->sen_start_addr - + p_dev->cfg_start_addr + + k] == + ic_chn_num) { + p_short_res + ->short_mess_arr + [i] = + j; + valid_chn_mark + [i] = 1; + break; + } + } + } else { /*//the second G1 chancel*/ + for (k = 0; + k < + p_dev->max_sen_num / + 2; + k++) { + if (p_dev->cfg + [p_dev->sen1_start_addr - + p_dev->cfg_start_addr + + k] == + ic_chn_num) { + p_short_res + ->short_mess_arr + [i] = + j; /*//(p_dev->max_sen_num / 2) + k;*/ + valid_chn_mark + [i] = 1; + break; + } + } + } + break; + } + } /*//end for (ch_cnt = 0; ch_cnt < p_dev->max_sen_num; ch_cnt++)*/ + } + } break; + case TX_RX_SEPERATION: + default: { + if ((p_short_res->short_mess_arr[i] & + CHANNEL_TX_FLAG) == CHANNEL_TX_FLAG) { + j = p_short_res->short_mess_arr[i] & + (~CHANNEL_TX_FLAG); + for (ch_cnt = 0; ch_cnt < p_dev->max_drv_num; + ch_cnt++) { + if (p_dev->drv_map[ch_cnt] == j) { + p_short_res->short_mess_arr[i] = + CHANNEL_TX_FLAG | + ch_cnt; + valid_chn_mark[i] = 1; + break; + } + } + } else { + j = p_short_res->short_mess_arr[i]; + for (ch_cnt = 0; ch_cnt < p_dev->max_sen_num; + ch_cnt++) { + if (p_dev->sen_map[ch_cnt] == j) { + p_short_res->short_mess_arr[i] = + ch_cnt; + valid_chn_mark[i] = 1; + break; + } + } + } + } break; + } /*// end switch (chn_enum)*/ + } /*//end for(i = 0; ishort_num*4; i++)*/ + + /*//check the short valid or not*/ + ic_chn_num = 0; + p_short_mess_tmp = &p_short_res->short_mess_arr[0]; + for (i = 0; i < p_short_res->short_num * 4; i += 4) { + if ((valid_chn_mark[i] != 1 && + p_short_mess_tmp[0] != CHANNEL_GND && + p_short_mess_tmp[0] != CHANNEL_VDD) || + (valid_chn_mark[i + 1] != 1 && + p_short_mess_tmp[1] != CHANNEL_GND && + p_short_mess_tmp[1] != CHANNEL_VDD)) { + if (p_short_res->short_num * 4 - i - 4 >= 4) { + memcpy(p_short_mess_tmp, p_short_mess_tmp + 4, + p_short_res->short_num * 4 - (i + 4)); + } + } else { + ic_chn_num++; + p_short_mess_tmp += 4; + } + } + p_short_res->short_num = ic_chn_num; + if (p_short_res->short_num == 0) { + p_short_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = SHORT_TEST_NONE_ERROR; + p_short_res->item_res_header.test_result = TEST_OK; + } +} + +/******************************************************************************* +* Function Name : short_test_end +* Description : (1)open esd and irq (2)reset chip +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32(0:have not handled 1:handled) +*******************************************************************************/ +extern s32 short_test_end(PST_TEST_ITEM p_test_item) +{ + s32 ret = 1; + if (board_recovery_dev_status(p_test_item->p_tp_dev) == 0) { + ret = 0; + } + + if (reset_chip_proc(p_test_item->p_tp_dev, RESET_TO_AP) == 0) { + board_print_error("reset tp error!\n"); + ret = 0; + } + return ret; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.h new file mode 100644 index 000000000000..f03e07e500c5 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test.h @@ -0,0 +1,79 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : short_test_func.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : We use this file unify a interface for short test +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_SHORT_TEST_H +#define TP_SHORT_TEST_H + +#include "tp_dev_def.h" +#include "tp_short_test_param.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SHORT_TEST_NONE_ERROR 0x00 +#define SHORT_TEST_PARAMETER_ERROR 0x01 +#define SHORT_TEST_DOWNLOAD_FW_FAIL 0x02 +#define SHORT_TEST_RUN_FW_FAIL 0x03 +#define SHORT_TEST_SEND_PARAMETER_FAIL 0x04 +#define SHORT_TEST_END_FAIL 0x05 +#define SHORT_TEST_EXIST_SHORT 0x06 +#define SHORT_TEST_ANALYSIS_RESULT_FAIL 0x07 +#define SHORT_TEST_WRITE_LINE_SEQ_FAIL 0x08 +#define WAIT_SHORT_CODE_RUN_FINISHED_ERROR 0x09 +#define SHORT_TEST_RECOVERY_CHIP_ERROR 0x09 +#define DISABLE_DEV_STATUS_FAIL 0x0A + +/*//short res*/ +/*//bit7=1 means Tx,bit7==0 means Rx*/ +#define CHANNEL_TX_FLAG 0x80 + +/*//exclude 0x7f and 0xff from 0~0xff,so we can use 254 ids stand for channel*/ +#define CHANNEL_GND 0x7f +#define CHANNEL_VDD 0xff + +#define MAX_SHORT_NUM 15 +typedef struct SHORT_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + u8 short_num; + /*//byte1:chn1 + //byte2:chn2 + //byte3~4:resistence,unit 0.1Kom*/ + u8 short_mess_arr[4 * MAX_SHORT_NUM]; +} ST_SHORT_TEST_RES, *PST_SHORT_TEST_RES; +typedef const ST_SHORT_TEST_RES CST_SHORT_TEST_RES; +typedef const PST_SHORT_TEST_RES CPST_SHORT_TEST_RES; + +/*************************************Public methods start********************************************/ +/*//short test*/ +extern s32 short_test_func(ptr32 p_data); + +extern s32 clear_short_mess_in_res(PST_TEST_ITEM p_test_item); +/*//store short message in result*/ +extern s32 store_short_mess_in_res(u8 chn1, u8 chn2, u16 r, + PST_SHORT_TEST_RES p_short_res); + +typedef enum SHORT_CHN_MAP_ENUM { + TX_RX_SEPERATION = 0x00, + TX_RX_SHARED = 0x01, + TX_RX_PACK_ADC = 0x02 +} ENUM_CHN_MAP_MODE; +extern void short_test_channel_map(ptr32 p_data, ENUM_CHN_MAP_MODE chn_enum); +extern s32 short_test_end(PST_TEST_ITEM p_test_item); + +/*************************************Public methods end********************************************/ + +/*************************************Private methods start********************************************/ + +/*************************************Private methods end********************************************/ +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test_param.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test_param.h new file mode 100644 index 000000000000..5b3e88281e99 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_short_test_param.h @@ -0,0 +1,56 @@ +#ifndef TP_SHORT_TEST_PARAM_H +#define TP_SHORT_TEST_PARAM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "user_test_type_def.h" +#include "test_item_def.h" + +/*//short test threshold parameter*/ +typedef struct SHORT_THRESHOLD_PARAM { + u16 drv_gnd_vdd_resistor_threshold; + u16 sen_gnd_vdd_resistor_threshold; + u16 sen_sen_resistor_threshold; + u16 drv_drv_resistor_threshold; + u16 drv_sen_resistor_threshold; + + u16 gt_short_threshold; + u16 adc_read_delay; + u16 diffcode_short_threshold; + u16 tx_tx_factor; + u16 tx_rx_factor; + u16 rx_rx_factor; + +} ST_SHORT_THRESHOLD_PARAM, *PST_SHORT_THRESHOLD_PARAM; + +/*//short bin*/ +typedef struct SHORT_BIN_PARAM { + u32 update_bin_len; + union { + u32 bin_addr; + u8 *bin_ptr; + } update_bin_addr; + +} ST_SHORT_BIN_PARAM, *PST_SHORT_BIN_PARAM; + +/*//short option*/ +typedef struct SHORT_OPTION { + u16 len; + union { + u32 opt_u32; + u8 *opt_ptr; + } opt; +} ST_SHORT_OPTION, *PST_SHORT_OPTION; + +typedef struct SHORT_PARAM { + ST_SHORT_THRESHOLD_PARAM short_threshold; + ST_SHORT_BIN_PARAM short_bin; + ST_SHORT_OPTION short_opt; +} ST_SHORT_PARAM, *PST_SHORT_PARAM; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_general_error_code_def.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_general_error_code_def.h new file mode 100644 index 000000000000..a01893889608 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_general_error_code_def.h @@ -0,0 +1,35 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_test_general_error_code_def.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 03/30/2018 +* Description : general error code start with 0x8000 +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_TEST_GENERAL_ERROR_CODE_DEF_H +#define TP_TEST_GENERAL_ERROR_CODE_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*//--------------------------------------------test item error code define start------------------------------------------------//*/ +#define ERROR_CODE_NONE 0 /*//ok*/ +#define PROCESS_BREAK_OUT 0x8001 /*//process break out*/ +#define PARAMETER_ERRROR 0x8002 /*//parameter error*/ +#define COMMUNICATION_ERROR 0x8003 /*//communication error*/ +#define MEMORY_ACCESS_ERROR 0x8004 /*//memory access error*/ +#define POINTER_ERROR 0x8005 /*//pointer error*/ +#define TEST_BEFORE_FUNC_FAIL 0x8006 /*//test before function fail*/ +#define TEST_FINISH_FUNC_FAIL 0x8007 /*//test finshed function fail*/ +#define TEST_RST_OPR_FAIL 0x8008 /*//test rst operation fail*/ +#define CHIP_TYPE_NOT_EXIST 0x8009 /*//chip type is not exist*/ + +/*//--------------------------------------------test item error code define start------------------------------------------------//*/ + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.c new file mode 100644 index 000000000000..64ffdbae3b00 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.c @@ -0,0 +1,216 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : TpTestItemResultMemProc.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 01/11/2018 +* Description : Tp Test Item Result Memory Process +*******************************************************************************/ + +#include "tp_test_item_mem.h" +#include "test_proc.h" +#include "simple_mem_manager.h" +#include "tp_open_test.h" +#include "tp_short_test.h" +#include "tp_version_test.h" + +#ifdef __cplusplus +extern "C" { +#endif +/******************************************************************************* +* Function Name : alloc_test_item_cur_buf +* Description : alloc_test_item_cur_buf +* Input : none +* Output : none +* Return : s32(1:ok false:fail) +*******************************************************************************/ +extern s32 alloc_test_item_cur_buf(PST_TEST_ITEM *pp_test_item, u16 item_num) +{ + s32 bRet = 0; + u32 i = 0; + for (i = 0; i < item_num; i++) { + PST_TEST_ITEM pTestItem = pp_test_item[i]; + switch (pTestItem->test_item_id) { + /*//----------------------tp open test-----------------------//*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + } break; + + case TP_DIFFDATA_TEST_ITEMS_SET_ID: { + } break; + + /*//----------------------hardware test-----------------------//*/ + case TP_SHORT_TEST_ITEM_ID: { + } break; + + case TP_RST_VOLT_TEST_ITEM_ID: { + } break; + + case TP_I2C_VOLT_TEST_ITEM_ID: { + } break; + + case TP_INT_VOLT_TEST_ITEM_ID: { + } break; + case TP_ACTIVE_CURRENT_TEST_ITEM_ID: { + } break; + + case TP_SLEEP_CURRENT_TEST_ITEM_ID: { + } break; + + case TP_INT_CAP_TEST_ITEM_ID: { + } break; + + case TP_MODULE_TYPE_TEST_ITEM_ID: { + } break; + + case TP_PIN1_TEST_ITEM_ID: { + } break; + + case TP_PIN2_TEST_ITEM_ID: { + } break; + + /*//----------------------firmware test-----------------------//*/ + case TP_VERSION_TEST_ITEM_ID: { + } break; + case TP_CHK_FW_RUN_STATE_ITEM_ID: { + } break; + + /*//----------------line test or key touch test---------------//*/ + case TP_KEY_TOUCH_TEST_ITEM_ID: { + } break; + + case TP_LINE_TEST_ITEM_ID: { + } break; + + /*//----------------------other test-----------------------//*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + } break; + + case TP_FLASH_TEST_ITEM_ID: { + } break; + + case TP_SEND_SPEC_CFG_ITEM_ID: { + } break; + + case TP_UPDATE_SPEC_FW_ITEM_ID: { + } break; + + case TP_CUSTOM_INFO_TEST_ITEM_ID: { + } break; + + case TP_CHK_CHIP_TEST_RESULT_ITEM_ID: { + } break; + case TP_CHK_MODULE_TEST_RESULT_ITEM_ID: { + } break; + case TP_RECOVER_CFG_ITEM_ID: { + } break; + case TP_SAVE_RES_TO_IC_STORAGE_ITEM_ID: { + } break; + + default: + break; + } + } + bRet = 1; + + return bRet; +} + +/******************************************************************************* +* Function Name : free_test_item_cur_buf +* Description : free_test_item_cur_buf +* Input : PST_TEST_ITEM* pp_test_item +* Output : u16 item_num +* Return : s32(1:ok false:fail) +*******************************************************************************/ +extern s32 free_test_item_cur_buf(PST_TEST_ITEM *pp_test_item, u16 item_num) +{ + s32 bRet = 0; + u32 i = 0; + for (i = 0; i < item_num; i++) { + PST_TEST_ITEM pTestItem = pp_test_item[i]; + switch (pTestItem->test_item_id) { + /*//----------------------tp open test-----------------------//*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + } break; + + case TP_DIFFDATA_TEST_ITEMS_SET_ID: { + } break; + + /*//----------------------hardware test-----------------------//*/ + case TP_SHORT_TEST_ITEM_ID: { + } break; + + case TP_RST_VOLT_TEST_ITEM_ID: { + } break; + + case TP_I2C_VOLT_TEST_ITEM_ID: { + } break; + + case TP_INT_VOLT_TEST_ITEM_ID: { + } break; + case TP_ACTIVE_CURRENT_TEST_ITEM_ID: { + } break; + + case TP_SLEEP_CURRENT_TEST_ITEM_ID: { + } break; + + case TP_INT_CAP_TEST_ITEM_ID: { + } break; + + case TP_MODULE_TYPE_TEST_ITEM_ID: { + } break; + + case TP_PIN1_TEST_ITEM_ID: { + } break; + + case TP_PIN2_TEST_ITEM_ID: { + } break; + + /*//----------------------firmware test-----------------------//*/ + case TP_VERSION_TEST_ITEM_ID: { + } break; + case TP_CHK_FW_RUN_STATE_ITEM_ID: { + } break; + + /*//----------------line test or key touch test---------------//*/ + case TP_KEY_TOUCH_TEST_ITEM_ID: { + } break; + + case TP_LINE_TEST_ITEM_ID: { + } break; + + /*//----------------------other test-----------------------//*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + } break; + + case TP_FLASH_TEST_ITEM_ID: { + } break; + + case TP_SEND_SPEC_CFG_ITEM_ID: { + } break; + + case TP_UPDATE_SPEC_FW_ITEM_ID: { + } break; + case TP_CUSTOM_INFO_TEST_ITEM_ID: { + } break; + + case TP_CHK_CHIP_TEST_RESULT_ITEM_ID: { + } break; + case TP_CHK_MODULE_TEST_RESULT_ITEM_ID: { + } break; + case TP_RECOVER_CFG_ITEM_ID: { + } break; + case TP_SAVE_RES_TO_IC_STORAGE_ITEM_ID: { + } break; + + default: + break; + } + } + bRet = 1; + + return bRet; +} + +#ifdef __cplusplus +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.h new file mode 100644 index 000000000000..c93edae94472 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_buf_mem.h @@ -0,0 +1,22 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : tp_test_item_buf_mem.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 01/11/2018 +* Description : Tp Test Item Current Buffer Memory Process +*******************************************************************************/ +#ifndef TP_TEST_ITEM_BUF_MEM_H +#define TP_TEST_ITEM_BUF_MEM_H + +#include "test_item_def.h" + +#ifdef __cplusplus +extern "C" { +#endif +s32 alloc_test_item_cur_buf(PST_TEST_ITEM *pp_test_item, u16 item_num); +s32 free_test_item_cur_buf(PST_TEST_ITEM *pp_test_item, u16 item_num); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_id.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_id.h new file mode 100644 index 000000000000..c1f27aaff78d --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_id.h @@ -0,0 +1,86 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : tp_test_item_id.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 12/31/2017 +* Description : touch panel test item id + //-----------------Very Important--------------------// + You can not modify each micro define,because this define + will be recorded in doc and send to custom. +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef TP_TEST_ITEM_ID_H +#define TP_TEST_ITEM_ID_H + +#ifdef __cplusplus +extern "C" { +#endif +/*//touch panel project start with TP*/ + +/*//device information ID may occupy 0~4 reserved ID*/ +#define TP_DEV_INFO_ID 0 + +/*//--------------------------------------------test item Id define start------------------------------------------------//*/ +/*//test item ID define 0~4 reserved*/ +#define TP_TEST_ITEM_START_ID 5 +/*//data test*/ +#define TP_RAWDATA_TEST_ITEMS_SET_ID 5 +#define TP_RAWDATA_MAX_TEST_ITEM_ID 0 +#define TP_RAWDATA_MIN_TEST_ITEM_ID 1 +#define TP_KEYDATA_MAX_TEST_ITEM_ID 2 +#define TP_KEYDATA_MIN_TEST_ITEM_ID 3 +#define TP_ACCORD_TEST_ITEM_ID 4 +#define TP_OFFSET_TEST_ITEM_ID 5 +#define TP_UNIFORMITY_TEST_ITEM_ID 6 +#define TP_RAWDATA_JITTER_TEST_ITEM_ID 7 + +#define TP_DIFFDATA_TEST_ITEMS_SET_ID 6 +#define TP_DIFFDATA_JITTER_TEST_ITEM_ID 0 + +/*//hardware test*/ +#define TP_SHORT_TEST_ITEM_ID 200 +#define TP_RST_VOLT_TEST_ITEM_ID 201 +#define TP_I2C_VOLT_TEST_ITEM_ID 202 +#define TP_INT_VOLT_TEST_ITEM_ID 203 +#define TP_PIN1_TEST_ITEM_ID 204 +#define TP_PIN2_TEST_ITEM_ID 205 + +#define TP_ACTIVE_CURRENT_TEST_ITEM_ID 206 +#define TP_SLEEP_CURRENT_TEST_ITEM_ID 207 +#define TP_INT_CAP_TEST_ITEM_ID 208 +#define TP_MODULE_TYPE_TEST_ITEM_ID 209 +#define TP_GESTURE_TEST_ITEM_ID 210 +#define TP_SPI_VOLT_TEST_ITEM_ID 211 + +/*//firmware test*/ +#define TP_VERSION_TEST_ITEM_ID 600 +#define TP_CHK_FW_RUN_STATE_ITEM_ID 601 + +/*//line test or key touch test*/ +#define TP_KEY_TOUCH_TEST_ITEM_ID 800 +#define TP_LINE_TEST_ITEM_ID 801 + +/*//other test*/ +#define TP_CHIP_CFG_PROC_ITEM_ID \ + 1200 /*/cfg check,check cfg in chip whether ok or not,or send config*/ +#define TP_FLASH_TEST_ITEM_ID \ + 1201 /*//flash test using send cfg ,reset chip,then read and compare cfg*/ +#define TP_SEND_SPEC_CFG_ITEM_ID 1202 /*//after test send special config*/ +#define TP_UPDATE_SPEC_FW_ITEM_ID 1203 /*//after test update special firmware*/ +#define TP_CUSTOM_INFO_TEST_ITEM_ID \ + 1204 /*//custom information:including write information or check information*/ +#define TP_CHK_CHIP_TEST_RESULT_ITEM_ID 1205 /*//check chip test result*/ +#define TP_CHK_MODULE_TEST_RESULT_ITEM_ID 1206 /*//check module test result*/ +#define TP_RECOVER_CFG_ITEM_ID 1207 /*//recovery config to chip*/ +#define TP_SAVE_RES_TO_IC_STORAGE_ITEM_ID 1208 /*//save result to ic storage*/ +#define TP_CHIP_UID_PROCESS_ITEM_ID 1209 /*//tp chip uid process*/ + +#define TP_TEST_SUB_ITEM_END_ID 0xFF +#define TP_TEST_ITEM_END_ID 0xFFFF +/*//--------------------------------------------test item Id define end------------------------------------------------//*/ +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.c new file mode 100644 index 000000000000..19215c0b0159 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.c @@ -0,0 +1,932 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : tp_test_item_mem.cpp +* Author : Bob Huang +* Version : V1.0.0 +* Date : 01/11/2018 +* Description : Tp Test Item Result Memory Process +*******************************************************************************/ + +#include "tp_test_item_mem.h" +#include "test_proc.h" +#include "simple_mem_manager.h" +#include "tp_open_test.h" +#include "tp_short_test.h" +#include "tp_version_test.h" +#include "tp_additional_option.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static s32 init_for_buffer(u8 *p_buf, u16 buf_size); + +/******************************************************************************* +* Function Name : alloc_test_item_res +* Description : alloc test item res +* Input : none +* Output : none +* Return : s32(1:ok 0:fail) +*******************************************************************************/ +s32 alloc_test_item_res(PST_TEST_ITEM *pp_test_item, u16 item_num) +{ + s32 ret = 0; + u16 i = 0; + for (i = 0; i < item_num; i++) { + PST_TEST_ITEM p_test_item = pp_test_item[i]; + switch (p_test_item->test_item_id) { + /*//----------------------tp open test-----------------------//*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + if (1 == alloc_rawdata_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + case TP_DIFFDATA_TEST_ITEMS_SET_ID: { + if (1 == alloc_diffdata_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + /*//----------------------hardware test-----------------------//*/ + case TP_SHORT_TEST_ITEM_ID: { + if (1 == alloc_short_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + /*//----------------------firmware test-----------------------//*/ + case TP_VERSION_TEST_ITEM_ID: { + if (1 == alloc_version_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + /*//----------------------other test-----------------------//*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + if (1 == alloc_chip_cfg_proc_item_res(p_test_item)) { + ret = 1; + } + } break; + + case TP_FLASH_TEST_ITEM_ID: { + if (1 == alloc_flash_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + case TP_RECOVER_CFG_ITEM_ID: { + if (1 == alloc_recover_cfg_item_res(p_test_item)) { + ret = 1; + } + } break; + default: + break; + } + } + ret = 1; + return ret; +} + +/******************************************************************************* +* Function Name : free_test_item_res +* Description : free test item res +* Input : none +* Output : none +* Return : s32(1:ok 0:fail) +*******************************************************************************/ +s32 free_test_item_res(PST_TEST_ITEM *pp_test_item, u16 item_num) +{ + s32 ret = 0; + u16 i = 0; + for (i = 0; i < item_num; i++) { + PST_TEST_ITEM p_test_item = pp_test_item[i]; + switch (p_test_item->test_item_id) { + /*//----------------------tp open test-----------------------//*/ + case TP_RAWDATA_TEST_ITEMS_SET_ID: { + if (1 == free_rawdata_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + case TP_DIFFDATA_TEST_ITEMS_SET_ID: { + if (1 == free_diffdata_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + /*//----------------------hardware test-----------------------//*/ + case TP_SHORT_TEST_ITEM_ID: { + if (1 == free_short_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + /*//----------------------firmware test-----------------------//*/ + case TP_VERSION_TEST_ITEM_ID: { + if (1 == free_version_test_item_res(p_test_item)) { + ret = 1; + } + } break; + /*//----------------------other test-----------------------//*/ + case TP_CHIP_CFG_PROC_ITEM_ID: { + if (1 == free_chip_cfg_proc_item_res(p_test_item)) { + ret = 1; + } + } break; + + case TP_FLASH_TEST_ITEM_ID: { + if (1 == free_flash_test_item_res(p_test_item)) { + ret = 1; + } + } break; + + case TP_RECOVER_CFG_ITEM_ID: { + if (1 == free_recover_cfg_item_res(p_test_item)) { + ret = 1; + } + } break; + default: + break; + } + } + ret = 1; + return ret; +} + +/******************************************************************************* +* Function Name : alloc_item_res_header +* Description : alloc_item_res_header +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 alloc_item_res_header(IN_OUT PST_TEST_ITEM p_test_item) +{ + P_TEST_ITEM_RES p_item_res_header = NULL; + p_item_res_header = (P_TEST_ITEM_RES)p_test_item->test_res.ptr_res; + + /*//default initialization*/ + p_item_res_header->test_id = p_test_item->test_item_id; + p_item_res_header->test_status = TEST_START; + p_item_res_header->test_result = TEST_OK; + + /*//item_res_header.p_sub_id_set*/ + if (NULL != p_test_item->p_sub_id_set) { + if (alloc_mem_in_heap( + (void **)&(p_item_res_header->p_sub_id_set), + sizeof(ST_SUB_TEST_ITEM_ID_SET))) { + p_item_res_header->p_sub_id_set->len = + p_test_item->p_sub_id_set->len; + if (alloc_mem_in_heap( + (void **)&(p_item_res_header->p_sub_id_set + ->p_id_set), + p_item_res_header->p_sub_id_set->len * + sizeof(u8))) { + memcpy(p_item_res_header->p_sub_id_set->p_id_set, + p_test_item->p_sub_id_set->p_id_set, + p_test_item->p_sub_id_set->len); + } + } + /*//item_res_header.test_item_err_code.ptr_err_code_set*/ + p_item_res_header->test_item_err_code.len = + p_test_item->p_sub_id_set->len + + 1; /*//each sub test for 1byte,maybe modify in future*/ + alloc_mem_in_heap( + (void **)&(p_item_res_header->test_item_err_code + .ptr_err_code_set), + p_item_res_header->test_item_err_code.len * + sizeof(u16)); + memset(p_item_res_header->test_item_err_code.ptr_err_code_set, + 0, p_item_res_header->test_item_err_code.len); + } else { + p_item_res_header->p_sub_id_set = NULL; + p_item_res_header->test_item_err_code.len = + 1; /*//main test for 1byte,maybe modify in future*/ + alloc_mem_in_heap( + (void **)&(p_item_res_header->test_item_err_code + .ptr_err_code_set), + p_item_res_header->test_item_err_code.len * + sizeof(u16)); + memset(p_item_res_header->test_item_err_code.ptr_err_code_set, + 0, + p_item_res_header->test_item_err_code.len * sizeof(u16)); + } + + return 1; +} + +/******************************************************************************* +* Function Name : free_item_res_header +* Description : free_item_res_header +* Input : PST_TEST_ITEM p_test_item +: u16 buf_size +* Output : +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 free_item_res_header(IN_OUT PST_TEST_ITEM p_test_item) +{ + P_TEST_ITEM_RES p_item_res_header = NULL; + p_item_res_header = (P_TEST_ITEM_RES)p_test_item->test_res.ptr_res; + + if (NULL != p_item_res_header->test_item_err_code.ptr_err_code_set) { + free_mem_in_heap((void *)p_item_res_header->test_item_err_code + .ptr_err_code_set); + p_item_res_header->test_item_err_code.ptr_err_code_set = NULL; + } + + if (NULL != p_item_res_header->p_sub_id_set) { + if (NULL != p_item_res_header->p_sub_id_set->p_id_set) { + free_mem_in_heap((void *)p_item_res_header->p_sub_id_set + ->p_id_set); + p_item_res_header->p_sub_id_set->p_id_set = NULL; + } + free_mem_in_heap((void *)p_item_res_header->p_sub_id_set); + p_item_res_header->p_sub_id_set = NULL; + } + return 1; +} + +/******************************************************************************* +* Function Name : alloc_rawdata_test_item_res +* Description : alloc_rawdata_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 alloc_rawdata_test_item_res(IN_OUT PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + u16 i = 0; + + PST_TP_DEV p_tp_dev = p_test_item->p_tp_dev; + u16 buf_size = p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num; + u8 key_buf_size = p_tp_dev->key_num; + u8 data_byte = 0; + PST_RAWDATA_TEST_RES *pp_rawdata_res = + (PST_RAWDATA_TEST_RES *)(&p_test_item->test_res.ptr_res); + PST_CUR_RAWDATA p_cur_rawdata = NULL; + if (p_tp_dev->rawdata_option & _DATA_BIT_8) { + data_byte = 1; + } else if (p_tp_dev->rawdata_option & _DATA_BIT_16) { + data_byte = 2; + } else if (p_tp_dev->rawdata_option & _DATA_BIT_32) { + data_byte = 4; + } + + if (NULL != p_test_item->test_res.ptr_res) { + return 1; + } + if (alloc_mem_in_heap((void **)pp_rawdata_res, + sizeof(ST_RAWDATA_TEST_RES))) { + ret = alloc_item_res_header(p_test_item); + if (0 == ret) { + return ret; + } + + (*pp_rawdata_res)->p_max_raw_tmp_data = NULL; + (*pp_rawdata_res)->p_min_raw_tmp_data = NULL; + (*pp_rawdata_res)->p_beyond_rawdata_upper_limit_cnt = NULL; + (*pp_rawdata_res)->p_beyond_rawdata_lower_limit_cnt = NULL; + (*pp_rawdata_res)->p_beyond_jitter_limit_cnt = NULL; + (*pp_rawdata_res)->p_beyond_accord_limit_cnt = NULL; + (*pp_rawdata_res)->p_beyond_offset_limit_cnt = NULL; + (*pp_rawdata_res)->p_beyond_key_upper_limit_cnt = NULL; + (*pp_rawdata_res)->p_beyond_key_lower_limit_cnt = NULL; + (*pp_rawdata_res)->beyond_uniform_limit_cnt = 0; + (*pp_rawdata_res)->total_frame_cnt = 0; + (*pp_rawdata_res)->open_test_result = OPEN_TEST_PASS; + + /*//max data tmp buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_rawdata_res)->p_max_raw_tmp_data), + sizeof(ST_RAW_TMP_DATA))) { + (*pp_rawdata_res)->p_max_raw_tmp_data->len = 0; + if (1 == alloc_mem_block( + (void **)&((*pp_rawdata_res) + ->p_max_raw_tmp_data + ->p_data_buf), + buf_size * sizeof(s32))) { + for (i = 0; i < buf_size; i++) { + (*pp_rawdata_res) + ->p_max_raw_tmp_data + ->p_data_buf[i] = 0; + } + (*pp_rawdata_res)->p_max_raw_tmp_data->len = + p_tp_dev->sc_sen_num * + p_tp_dev->sc_drv_num; + } + } + + /*//min data tmp buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_rawdata_res)->p_min_raw_tmp_data), + sizeof(ST_RAW_TMP_DATA))) { + (*pp_rawdata_res)->p_min_raw_tmp_data->len = 0; + if (alloc_mem_block( + (void **)&((*pp_rawdata_res) + ->p_min_raw_tmp_data + ->p_data_buf), + buf_size * sizeof(s32))) { + for (i = 0; i < buf_size; i++) { + (*pp_rawdata_res) + ->p_min_raw_tmp_data + ->p_data_buf[i] = 0x7FFFFFFF; + } + (*pp_rawdata_res)->p_min_raw_tmp_data->len = + p_tp_dev->sc_sen_num * + p_tp_dev->sc_drv_num; + } + } + /*//beyond rawdata upper limit buffer*/ + if (alloc_mem_in_heap( + (void **)&( + (*pp_rawdata_res) + ->p_beyond_rawdata_upper_limit_cnt), + buf_size)) { + init_for_buffer( + (u8 *)(*pp_rawdata_res) + ->p_beyond_rawdata_upper_limit_cnt, + buf_size); + } + /*//beyond rawdata lower limit buffer*/ + if (alloc_mem_in_heap( + (void **)&( + (*pp_rawdata_res) + ->p_beyond_rawdata_lower_limit_cnt), + buf_size)) { + init_for_buffer( + (*pp_rawdata_res) + ->p_beyond_rawdata_lower_limit_cnt, + buf_size); + } + /*//beyond jitter limit buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_rawdata_res) + ->p_beyond_jitter_limit_cnt), + buf_size)) { + init_for_buffer( + (*pp_rawdata_res)->p_beyond_jitter_limit_cnt, + buf_size); + } + /*//beyond accord limit buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_rawdata_res) + ->p_beyond_accord_limit_cnt), + buf_size)) { + init_for_buffer( + (*pp_rawdata_res)->p_beyond_accord_limit_cnt, + buf_size); + } + /*//beyond offset limit buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_rawdata_res) + ->p_beyond_offset_limit_cnt), + buf_size)) { + init_for_buffer( + (*pp_rawdata_res)->p_beyond_offset_limit_cnt, + buf_size); + } + /*//beyond key upper limit buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_rawdata_res) + ->p_beyond_key_upper_limit_cnt), + key_buf_size)) { + init_for_buffer( + (*pp_rawdata_res)->p_beyond_key_upper_limit_cnt, + key_buf_size); + } + /*//beyond key lower limit buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_rawdata_res) + ->p_beyond_key_lower_limit_cnt), + key_buf_size)) { + init_for_buffer( + (*pp_rawdata_res)->p_beyond_key_lower_limit_cnt, + key_buf_size); + } + + if (alloc_mem_in_heap( + (void **)&(p_test_item->cur_data.ptr_cur_data), + sizeof(ST_CUR_RAWDATA))) { + buf_size = p_tp_dev->rawdata_len; + p_cur_rawdata = + (PST_CUR_RAWDATA) + p_test_item->cur_data.ptr_cur_data; + p_cur_rawdata->cur_frame_id = 0; + p_cur_rawdata->data_len = buf_size; + if (alloc_mem_block( + (void **)&(p_cur_rawdata->p_data_buf), + buf_size * data_byte)) { + init_for_buffer( + (u8 *)(p_cur_rawdata->p_data_buf), + buf_size * data_byte); + } + } + + if (NULL != (*pp_rawdata_res)->p_max_raw_tmp_data->p_data_buf && + NULL != (*pp_rawdata_res)->p_min_raw_tmp_data->p_data_buf && + NULL != (*pp_rawdata_res)->p_beyond_rawdata_upper_limit_cnt && + NULL != (*pp_rawdata_res)->p_beyond_rawdata_lower_limit_cnt && + NULL != (*pp_rawdata_res)->p_beyond_jitter_limit_cnt && + NULL != (*pp_rawdata_res)->p_beyond_accord_limit_cnt && + NULL != (*pp_rawdata_res)->p_beyond_offset_limit_cnt && + NULL != (*pp_rawdata_res)->p_beyond_key_upper_limit_cnt && + NULL != (*pp_rawdata_res)->p_beyond_key_lower_limit_cnt && + NULL != (*pp_rawdata_res) + ->item_res_header.test_item_err_code + .ptr_err_code_set && + NULL != p_test_item->cur_data.ptr_cur_data && + NULL != ((PST_CUR_RAWDATA)p_test_item->cur_data.ptr_cur_data) + ->p_data_buf) { + ret = 1; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : free_rawdata_test_item_res +* Description : free_rawdata_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 free_rawdata_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 1; + PST_RAWDATA_TEST_RES *pp_rawdata_res = NULL; + PST_CUR_RAWDATA p_curdata = NULL; + if (NULL == p_test_item->test_res.ptr_res) { + return 1; + } + pp_rawdata_res = + (PST_RAWDATA_TEST_RES *)(&p_test_item->test_res.ptr_res); + + /*//free test item res header*/ + ret &= free_item_res_header(p_test_item); + + /*//free beyond rawdata upper limit buffer*/ + ret &= free_mem_in_heap( + (void *)(*pp_rawdata_res)->p_beyond_rawdata_upper_limit_cnt); + (*pp_rawdata_res)->p_beyond_rawdata_upper_limit_cnt = NULL; + + /*//free beyond rawdata lower limit buffer*/ + ret &= free_mem_in_heap( + (void *)(*pp_rawdata_res)->p_beyond_rawdata_lower_limit_cnt); + (*pp_rawdata_res)->p_beyond_rawdata_lower_limit_cnt = NULL; + + /*//free beyond jitter limit buffer*/ + ret &= free_mem_in_heap( + (void *)(*pp_rawdata_res)->p_beyond_jitter_limit_cnt); + (*pp_rawdata_res)->p_beyond_jitter_limit_cnt = NULL; + + /*//free beyond accord limit buffer*/ + ret &= free_mem_in_heap( + (void *)(*pp_rawdata_res)->p_beyond_accord_limit_cnt); + (*pp_rawdata_res)->p_beyond_accord_limit_cnt = NULL; + + /*//free beyond offset limit buffer*/ + ret &= free_mem_in_heap( + (void *)(*pp_rawdata_res)->p_beyond_offset_limit_cnt); + (*pp_rawdata_res)->p_beyond_offset_limit_cnt = NULL; + + /*//free beyond key upper limit buffer*/ + ret &= free_mem_in_heap( + (void *)(*pp_rawdata_res)->p_beyond_key_upper_limit_cnt); + (*pp_rawdata_res)->p_beyond_key_upper_limit_cnt = NULL; + + /*//free beyond key lower limit buffer*/ + ret &= free_mem_in_heap( + (void *)(*pp_rawdata_res)->p_beyond_key_lower_limit_cnt); + (*pp_rawdata_res)->p_beyond_key_lower_limit_cnt = NULL; + + /*//free max tmp data buffer*/ + ret &= free_mem_block( + (void *)(*pp_rawdata_res)->p_max_raw_tmp_data->p_data_buf); + (*pp_rawdata_res)->p_max_raw_tmp_data->p_data_buf = NULL; + ret &= free_mem_in_heap((*pp_rawdata_res)->p_max_raw_tmp_data); + (*pp_rawdata_res)->p_max_raw_tmp_data = NULL; + + /*//free min tmp data buffer*/ + ret &= free_mem_block( + (void *)(*pp_rawdata_res)->p_min_raw_tmp_data->p_data_buf); + (*pp_rawdata_res)->p_min_raw_tmp_data->p_data_buf = NULL; + ret &= free_mem_in_heap((*pp_rawdata_res)->p_min_raw_tmp_data); + (*pp_rawdata_res)->p_min_raw_tmp_data = NULL; + + /*//free struct */ + ret &= free_mem_in_heap_p((void **)(pp_rawdata_res)); + + /*//free current data*/ + p_curdata = (PST_CUR_RAWDATA)p_test_item->cur_data.ptr_cur_data; + ret &= free_mem_block((void *)(p_curdata->p_data_buf)); + ret &= free_mem_in_heap_p( + (void **)&(p_test_item->cur_data.ptr_cur_data)); + + return ret; +} + +/******************************************************************************* +* Function Name : alloc_diffdata_test_item_res +* Description : alloc_diffdata_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 alloc_diffdata_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 i = 0; + s32 ret = 0; + PST_TP_DEV p_tp_dev = p_test_item->p_tp_dev; + u16 buf_size = p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num; + u8 data_byte = 0; + PST_DIFFDATA_TEST_RES *pp_diffdata_res = NULL; + PST_CUR_DIFFDATA p_cur_diffdata = NULL; + if (p_tp_dev->diffdata_option & _DATA_BIT_8) { + data_byte = 1; + } else if (p_tp_dev->diffdata_option & _DATA_BIT_16) { + data_byte = 2; + } else if (p_tp_dev->diffdata_option & _DATA_BIT_32) { + data_byte = 4; + } + + if (NULL != p_test_item->test_res.ptr_res) { + return 1; + } + pp_diffdata_res = + (PST_DIFFDATA_TEST_RES *)(&p_test_item->test_res.ptr_res); + if (alloc_mem_in_heap((void **)pp_diffdata_res, + sizeof(ST_DIFFDATA_TEST_RES))) { + ret = alloc_item_res_header(p_test_item); + if (0 == ret) { + return ret; + } + /*//max data tmp buffer*/ + if (alloc_mem_in_heap( + (void **)&((*pp_diffdata_res)->p_max_diff_tmp_data), + sizeof(ST_DIFF_TMP_DATA))) { + buf_size = p_tp_dev->sc_drv_num * p_tp_dev->sc_sen_num; + (*pp_diffdata_res)->p_max_diff_tmp_data->len = 0; + if (1 == + alloc_mem_block( + (void **)&((*pp_diffdata_res) + ->p_max_diff_tmp_data + ->p_data_buf), + buf_size * sizeof(s32))) { + for (i = 0; i < buf_size; i++) { + (*pp_diffdata_res) + ->p_max_diff_tmp_data + ->p_data_buf[i] = 0; + } + (*pp_diffdata_res)->p_max_diff_tmp_data->len = + buf_size; + } + } + + if (alloc_mem_in_heap( + (void **)&(p_test_item->cur_data.ptr_cur_data), + sizeof(ST_CUR_DIFFDATA))) { + buf_size = p_tp_dev->diffdata_len; + p_cur_diffdata = + (PST_CUR_DIFFDATA) + p_test_item->cur_data.ptr_cur_data; + p_cur_diffdata->cur_frame_id = 0; + p_cur_diffdata->data_len = buf_size; + if (alloc_mem_block( + (void **)&(p_cur_diffdata->p_data_buf), + buf_size * data_byte)) { + init_for_buffer( + (u8 *)(p_cur_diffdata->p_data_buf), + buf_size * data_byte); + } + } + } + + return ret; +} + +/******************************************************************************* +* Function Name : free_diffdata_test_item_res +* Description : free_diffdata_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 free_diffdata_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 1; + PST_DIFFDATA_TEST_RES *pp_diffdata_res = NULL; + PST_CUR_DIFFDATA p_curdata = NULL; + if (NULL == p_test_item->test_res.ptr_res) { + return 1; + } + /*//free struct */ + pp_diffdata_res = + (PST_DIFFDATA_TEST_RES *)(&p_test_item->test_res.ptr_res); + + ret &= free_item_res_header(p_test_item); + /*//free max tmp data buffer*/ + ret &= free_mem_block( + (void *)(*pp_diffdata_res)->p_max_diff_tmp_data->p_data_buf); + (*pp_diffdata_res)->p_max_diff_tmp_data->p_data_buf = NULL; + ret &= free_mem_in_heap((*pp_diffdata_res)->p_max_diff_tmp_data); + (*pp_diffdata_res)->p_max_diff_tmp_data = NULL; + + ret = free_mem_in_heap_p((void **)(pp_diffdata_res)); + + /*//free current data*/ + p_curdata = (PST_CUR_DIFFDATA)p_test_item->cur_data.ptr_cur_data; + ret &= free_mem_block((void *)(p_curdata->p_data_buf)); + ret &= free_mem_in_heap_p( + (void **)&(p_test_item->cur_data.ptr_cur_data)); + + return ret; +} + +/******************************************************************************* +* Function Name : alloc_short_test_item_res +* Description : alloc_short_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 alloc_short_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_SHORT_TEST_RES *pp_test_res = NULL; + if (NULL != p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = (PST_SHORT_TEST_RES *)(&p_test_item->test_res.ptr_res); + if (alloc_mem_in_heap((void **)pp_test_res, + sizeof(ST_SHORT_TEST_RES))) { + ret = alloc_item_res_header(p_test_item); + (*pp_test_res)->short_num = 0; + } + + return ret; +} + +/******************************************************************************* +* Function Name : free_short_test_item_res +* Description : free_short_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 free_short_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_SHORT_TEST_RES *pp_test_res = NULL; + if (NULL == p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = (PST_SHORT_TEST_RES *)(&p_test_item->test_res.ptr_res); + ret = free_item_res_header(p_test_item); + ret = free_mem_in_heap_p((void **)pp_test_res); + return ret; +} + +/******************************************************************************* +* Function Name : alloc_version_test_item_res +* Description : alloc_version_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 alloc_version_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_VERSION_TEST_RES *pp_test_res = NULL; + if (NULL != p_test_item->test_res.ptr_res) { + return 1; + } + + pp_test_res = (PST_VERSION_TEST_RES *)(&p_test_item->test_res.ptr_res); + if (alloc_mem_in_heap((void **)pp_test_res, + sizeof(ST_VERSION_TEST_RES))) { + ret = alloc_item_res_header(p_test_item); + (*pp_test_res)->cur_ver_data_len = 0; + } + + return ret; +} + +/******************************************************************************* +* Function Name : free_version_test_item_res +* Description : free_version_test_item_res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +s32 free_version_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_VERSION_TEST_RES *pp_test_res = NULL; + if (NULL == p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = (PST_VERSION_TEST_RES *)(&p_test_item->test_res.ptr_res); + ret = free_item_res_header(p_test_item); + ret = free_mem_in_heap_p((void **)(pp_test_res)); + return ret; +} +/******************************************************************************* +* Function Name : free_sleep_current_test_item_res +* Description : free sleep current test item res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(1:ok 0:fail) +*******************************************************************************/ +s32 alloc_chip_cfg_proc_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_CHIP_CONFIG_PROC_RES *pp_test_res = NULL; + PST_CHIP_CONFIG_PROC_PARAM p_param = NULL; + if (NULL != p_test_item->test_res.ptr_res) { + return 1; + } + + pp_test_res = + (PST_CHIP_CONFIG_PROC_RES *)(&p_test_item->test_res.ptr_res); + if (alloc_mem_in_heap((void **)pp_test_res, + sizeof(ST_CHIP_CONFIG_PROC_RES))) { + ret = alloc_item_res_header(p_test_item); + p_param = (PST_CHIP_CONFIG_PROC_PARAM) + p_test_item->param.ptr_param; + if (NULL != p_param && 0 < p_param->cfg_len) { + (*pp_test_res)->cfg_len = p_param->cfg_len; + ret = alloc_mem_in_heap( + (void **)(&(*pp_test_res)->p_read_cfg), + (*pp_test_res)->cfg_len * sizeof(u8)); + } else { + (*pp_test_res)->cfg_len = 0; + (*pp_test_res)->p_read_cfg = NULL; + } + } + return ret; +} + +/******************************************************************************* +* Function Name : free_cfg_check_test_item_res +* Description : free sleep free_cfg_check_test_item_res test item res +* Input : PST_TEST_ITEM p_test_item +* Output : PST_TEST_ITEM p_test_item +* Return : s32(1:ok 0:fail) +*******************************************************************************/ +s32 free_chip_cfg_proc_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_CHIP_CONFIG_PROC_RES *pp_test_res = NULL; + if (NULL == p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = + (PST_CHIP_CONFIG_PROC_RES *)(&p_test_item->test_res.ptr_res); + ret = free_item_res_header(p_test_item); + if (NULL != (*pp_test_res)->p_read_cfg) { + ret = free_mem_in_heap_p((void **)&(*pp_test_res)->p_read_cfg); + } + ret = free_mem_in_heap_p((void **)(pp_test_res)); + return ret; +} + +/***************************************************************** +* Function Name : alloc_flash_test_item_res +* Description : alloc_flash_test_item_res +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 alloc_flash_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_FLASH_TEST_RES *pp_test_res = NULL; + PST_FLASH_TEST_PARAM p_param = NULL; + if (NULL != p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = (PST_FLASH_TEST_RES *)(&p_test_item->test_res.ptr_res); + if (alloc_mem_in_heap((void **)pp_test_res, + sizeof(ST_FLASH_TEST_RES))) { + ret = alloc_item_res_header(p_test_item); + + p_param = (PST_FLASH_TEST_PARAM)p_test_item->param.ptr_param; + if (NULL != p_param && 0 < p_param->cfg_len) { + (*pp_test_res)->cfg_len = p_param->cfg_len; + ret = alloc_mem_in_heap( + (void **)(&(*pp_test_res)->config_arr), + (*pp_test_res)->cfg_len * sizeof(u8)); + } else { + (*pp_test_res)->cfg_len = 0; + (*pp_test_res)->config_arr = NULL; + } + } + return ret; +} + +/***************************************************************** +* Function Name : free_flash_test_item_res +* Description : free_flash_test_item_res +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 free_flash_test_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_FLASH_TEST_RES *pp_test_res = NULL; + if (NULL == p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = (PST_FLASH_TEST_RES *)(&p_test_item->test_res.ptr_res); + ret = free_item_res_header(p_test_item); + if (NULL != (*pp_test_res)->config_arr) { + ret = free_mem_in_heap_p((void **)&(*pp_test_res)->config_arr); + } + + ret = free_mem_in_heap_p((void **)(pp_test_res)); + return ret; +} + +/***************************************************************** +* Function Name : alloc_recover_cfg_item_res +* Description : alloc_recover_cfg_item_res +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 alloc_recover_cfg_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_RECOVER_CHIP_CFG_RES *pp_test_res = NULL; + PST_RECOVER_CHIP_CFG_PARAM p_param = + (PST_RECOVER_CHIP_CFG_PARAM)p_test_item->param.ptr_param; + if (NULL != p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = + (PST_RECOVER_CHIP_CFG_RES *)(&p_test_item->test_res.ptr_res); + if (alloc_mem_in_heap((void **)pp_test_res, + sizeof(ST_RECOVER_CHIP_CFG_RES))) { + ret = alloc_item_res_header(p_test_item); + if (NULL != p_param) { + (*pp_test_res)->cfg_len = p_param->cfg_len; + ret = alloc_mem_in_heap( + (void **)&(*pp_test_res)->config_arr, + (*pp_test_res)->cfg_len * sizeof(u8)); + } else { + (*pp_test_res)->cfg_len = 0; + (*pp_test_res)->config_arr = NULL; + } + } + return ret; +} + +/***************************************************************** +* Function Name : free_revover_cfg_item_res +* Description : free_revover_cfg_item_res +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Return : s32(0:fail 1:ok) +*******************************************************************************/ +extern s32 free_recover_cfg_item_res(PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + PST_RECOVER_CHIP_CFG_RES *pp_test_res = NULL; + if (NULL == p_test_item->test_res.ptr_res) { + return 1; + } + pp_test_res = + (PST_RECOVER_CHIP_CFG_RES *)(&p_test_item->test_res.ptr_res); + + ret = free_item_res_header(p_test_item); + if (NULL != (*pp_test_res)->config_arr) { + ret = free_mem_in_heap_p((void **)&(*pp_test_res)->config_arr); + } + ret = free_mem_in_heap_p((void **)(pp_test_res)); + return ret; +} + +#ifdef __cplusplus +} +#endif + +/******************************************************************************* +* Function Name : init_for_buffer +* Description : initialize temp buffer with 0 +* Input : u8* p_buf +: u16 buf_size +* Output : u8* p_buf +* Return : s32(0:Fail 1:Ok) +*******************************************************************************/ +static s32 init_for_buffer(u8 *p_buf, u16 buf_size) +{ + s32 ret = 1; + u16 i = 0; + for (i = 0; i < buf_size; i++) { + p_buf[i] = 0; + } + return ret; +} \ No newline at end of file diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.h new file mode 100644 index 000000000000..9012bdbd1332 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_test_item_mem.h @@ -0,0 +1,42 @@ +/******************** (C) COPYRIGHT 2017 Goodix ******************** +* File Name : tp_test_item_mem.cpp.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 01/11/2018 +* Description : Tp Test Item Result Memory Process +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE +#ifndef TP_TEST_ITEM_MEM_H +#define TP_TEST_ITEM_MEM_H + +#include "test_item_def.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 alloc_test_item_res(PST_TEST_ITEM *pp_test_item, u16 item_num); +extern s32 free_test_item_res(PST_TEST_ITEM *pp_test_item, u16 item_num); + +extern s32 alloc_item_res_header(PST_TEST_ITEM p_test_item); +extern s32 free_item_res_header(PST_TEST_ITEM p_test_item); +extern s32 alloc_rawdata_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 free_rawdata_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 alloc_diffdata_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 free_diffdata_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 alloc_short_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 free_short_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 alloc_version_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 free_version_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 alloc_chip_cfg_proc_item_res(PST_TEST_ITEM p_test_item); +extern s32 free_chip_cfg_proc_item_res(PST_TEST_ITEM p_test_item); +extern s32 alloc_flash_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 free_flash_test_item_res(PST_TEST_ITEM p_test_item); +extern s32 alloc_recover_cfg_item_res(PST_TEST_ITEM p_test_item); +extern s32 free_recover_cfg_item_res(PST_TEST_ITEM p_test_item); + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.c new file mode 100644 index 000000000000..dfb894933d15 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.c @@ -0,0 +1,267 @@ +/******************** (C) COPYRIGHT 2016 Goodix **************************** +* File Name : version_test.c +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : test touch panel version or update firmware +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#include "test_item_def.h" +#include "tp_version_test.h" +#include "tp_dev_control.h" +#include "board_opr_interface.h" +#include "tp_test_general_error_code_def.h" +#include "test_proc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static s32 compare_version_equal(PST_TEST_ITEM p_test_item); +static s32 compare_version_equal_greater(PST_TEST_ITEM p_test_item); +static s32 compare_version(PST_TEST_ITEM p_test_item); + +/******************************************************************************* +* Function Name : fw_version_test +* Description : firmware version test +* Input : ptr32 p_data(You must cast it to type PST_TEST_ITEM ) +* Output : none +* Return : u8(0:test error 1:ok) +*******************************************************************************/ +extern s32 fw_version_test(IN_OUT ptr32 p_data) +{ + PST_TEST_ITEM p_test_item = NULL; + PST_VERSION_PARAM p_ver_param = NULL; + PST_VERSION_TEST_RES p_test_res = NULL; + u16 err_code = VERSION_TEST_NONE_ERROR; + u8 i = 0; + s32 ret = 0; + + p_test_item = (PST_TEST_ITEM)p_data; + /*-----------------Judge parameter----------------*/ + if (0 == judge_test_item_legal((PST_TEST_ITEM)p_data)) { + ret = 0; + goto TEST_ITEM_END; + } + + p_ver_param = (PST_VERSION_PARAM)p_test_item->param.ptr_param; + p_test_res = (PST_VERSION_TEST_RES)p_test_item->test_res.ptr_res; + + /*callback function test before*/ + if (NULL != p_test_item->ptr_test_item_before_func) { + ret = p_test_item->ptr_test_item_before_func( + p_test_item->ptr_test_item_before_func_param); + if (0 == ret) { + board_print_error( + "[version test]callback function test before error!\n"); + err_code = TEST_BEFORE_FUNC_FAIL; + goto TEST_ITEM_END; + } + } + + p_test_res->cur_ver_data_len = p_ver_param->ver_param_len; + p_test_res->item_res_header.test_status = TEST_START; + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_item_err_code.ptr_err_code_set[0] = + VERSION_TEST_NONE_ERROR; + for (i = 0; i < p_ver_param->ver_param_len; i++) { /*//clear res*/ + p_test_res->cur_ver_data[i] = 0x00; + } + + /*//force update*/ + if (1 == p_ver_param->b_force_update) { + /*//update fw*/ + } + /*//compare version*/ + ret = compare_version(p_test_item); + if (ret == 0) { + if (1 == p_ver_param->b_force_update) { + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = + VERSION_TEST_VERSIONMATCH_FAIL_AFTER; + } + p_test_res->item_res_header.test_result = TEST_NG; + p_test_res->item_res_header.test_status = TEST_ABORTED; + board_print_debug("compare fw version error!\n"); + err_code = p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0]; + /*//goto TEST_ITEM_END;*/ + } + + if (p_test_res->item_res_header.test_result == TEST_OK) { + p_test_res->item_res_header.test_status = TEST_FINISH; + goto TEST_ITEM_END; + } else { + if (0 == p_ver_param->b_auto_update) { + p_test_res->item_res_header.test_status = TEST_FINISH; + goto TEST_ITEM_END; + } else if (0 == p_ver_param->b_force_update) { + /*//compare version again*/ + ret = compare_version(p_test_item); + if (0 == ret) { + if (1 == p_ver_param->b_force_update) { + p_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[0] = + VERSION_TEST_VERSIONMATCH_FAIL_AFTER; + } + p_test_res->item_res_header.test_result = + TEST_NG; + p_test_res->item_res_header.test_status = + TEST_ABORTED; + board_print_error( + "auto update:compare fw version error!\n"); + err_code = p_test_res->item_res_header + .test_item_err_code + .ptr_err_code_set[0]; + goto TEST_ITEM_END; + } + } + } + + p_test_res->item_res_header.test_status = TEST_FINISH; +TEST_ITEM_END: + if (NULL != p_test_item->ptr_test_item_finished_func) { + ret = p_test_item->ptr_test_item_finished_func( + p_test_item->ptr_test_item_finished_func_param); + if (ret == 0) { + board_print_error( + "[version test]callback function after test error!\n"); + err_code = TEST_FINISH_FUNC_FAIL; + } + } + + if (err_code == VERSION_TEST_NONE_ERROR) { + ret = 1; + } else { + ret = 0; + } + return ret; +} + +/******************************************************************************* +* Function Name : compare_version +* Description : compare version +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32(0:error 1:handled) +*******************************************************************************/ +static s32 compare_version(PST_TEST_ITEM p_test_item) +{ + u8 i = 0, retry_cnt = 3; + s32 ret = 0; + s32 cmp_ret = 0; + PST_VERSION_PARAM p_ver_param = + (PST_VERSION_PARAM)p_test_item->param.ptr_param; + PST_VERSION_TEST_RES p_test_res = + (PST_VERSION_TEST_RES)p_test_item->test_res.ptr_res; + /*//read ic version */ + for (i = 0; i < retry_cnt; i++) { + ret = chip_reg_read(p_test_item->p_tp_dev, + p_ver_param->ic_ver_addr, + p_test_res->cur_ver_data, + p_ver_param->ver_param_len); + if (1 == ret) { + break; + } + } + if (i >= retry_cnt) { + board_print_error("%s\n", + "in compare version, read version fail"); + goto COMPARE_END; + } + + if (p_ver_param->ver_cmp_opt == VERSION_CMP_EQUAL) { + cmp_ret = compare_version_equal(p_test_item); + } else if (p_ver_param->ver_cmp_opt == VERSION_CMP_GREATOR_EQUAL) { + cmp_ret = compare_version_equal_greater(p_test_item); + } + + if (0 == cmp_ret) { + board_print_debug("%s\n", + "in compare version, version match fail"); + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = VERSION_TEST_VERSION_MATCH_FAIL; + p_test_res->item_res_header.test_result = TEST_NG; + ret = 0; + goto COMPARE_END; + } else { + p_test_res->item_res_header.test_result = TEST_OK; + p_test_res->item_res_header.test_item_err_code + .ptr_err_code_set[0] = VERSION_TEST_NONE_ERROR; + ret = 1; + } +COMPARE_END: + return ret; +} + +/******************************************************************************* +* Function Name : compare_version_equal +* Description : compare_version_equal +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32(0:error 1:cmp ok) +*******************************************************************************/ +static s32 compare_version_equal(IN PST_TEST_ITEM p_test_item) +{ + u8 i = 0; + s32 ret = 0; + PST_VERSION_PARAM p_ver_param = + (PST_VERSION_PARAM)p_test_item->param.ptr_param; + PST_VERSION_TEST_RES p_test_res = + (PST_VERSION_TEST_RES)p_test_item->test_res.ptr_res; + + /*//compare version*/ + for (i = 0; i < p_ver_param->ver_param_len; i++) { + if (p_test_res->cur_ver_data[i] != + p_ver_param->ver_param_str[i]) { + break; + } + } + + if (i == p_ver_param->ver_param_len) { + ret = 1; + } + return ret; +} + +/******************************************************************************* +* Function Name : compare_version_equal_greater +* Description : compare_version_equal_greater +* Input : PST_TEST_ITEM p_test_item +* Output : none +* Return : s32(0:error 1:cmp ok) +*******************************************************************************/ +static s32 compare_version_equal_greater(IN PST_TEST_ITEM p_test_item) +{ + s32 ret = 0; + u8 i = 0; + PST_VERSION_PARAM p_ver_param = + (PST_VERSION_PARAM)p_test_item->param.ptr_param; + PST_VERSION_TEST_RES p_test_res = + (PST_VERSION_TEST_RES)p_test_item->test_res.ptr_res; + ret = compare_version_equal(p_test_item); + if (1 == ret) { + return ret; + } + /*//compare version + //do not care about public version and special version updating*/ + for (i = 0; i < p_ver_param->ver_param_len; i++) { + if (p_test_res->cur_ver_data[i] < + p_ver_param->ver_param_str[i]) { + return 0; + } + if (p_test_res->cur_ver_data[i] > + p_ver_param->ver_param_str[i]) { + return 1; + } + } + + return 1; +} +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.h new file mode 100644 index 000000000000..5d51596978cf --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test.h @@ -0,0 +1,57 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : version_test.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : test touch panel version or update firmware +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef VERSION_TEST_H +#define VERSION_TEST_H + +#include "tp_version_test_param.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define VERSION_TEST_NONE_ERROR 0x00 +#define VERSION_TEST_VERSION_MATCH_FAIL 0x01 +#define VERSION_TEST_FW_UPDATE_FAIL 0x02 +#define VERSION_TEST_VERSIONMATCH_FAIL_AFTER 0x03 + +/*//---------------------Version Test----------------------//*/ + +/*//test result*/ +typedef struct VERSION_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + u8 cur_ver_data_len; + u8 cur_ver_data[MAX_VERSION_LEN]; +} ST_VERSION_TEST_RES, *PST_VERSION_TEST_RES; + +extern s32 fw_version_test(ptr32 p_data); +extern s32 fw_update(ptr32 p_data, PST_UPDATA_BIN_PARAM p_update_bin); + +typedef struct CHK_FW_RUN_STATE_RES { + ST_TEST_ITEM_RES item_res_header; +} ST_CHK_FW_RUN_STATE_RES, *PST_CHK_FW_RUN_STATE_RES; +extern s32 check_fw_run_state(ptr32 p_data); + +/*//--------------------Error code---------------------//*/ +#define GEST_TEST_ERROR_NONE 0x00 +#define GEST_TEST_ENTER_DOZE_FAIL 0x01 +#define GEST_TEST_EXIT_DOZE_FAIL 0x02 +#define GEST_TEST_VER_CMP_ERROR 0x03 +typedef struct GESTURE_TEST_RES { + ST_TEST_ITEM_RES item_res_header; + u8 ver_buf[MAX_GESTURE_VER_BUF_SIZE]; + u8 ver_buf_len; +} ST_GESTURE_TEST_RES, *PST_GESTURE_TEST_RES; +extern s32 tp_gesture_test(ptr32 p_data); + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test_param.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test_param.h new file mode 100644 index 000000000000..79d5944f258a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/tp_version_test_param.h @@ -0,0 +1,51 @@ +#ifndef VERSION_TEST_PARAM_H +#define VERSION_TEST_PARAM_H + +#include "user_test_type_def.h" +#include "test_item_def.h" + +#ifdef __cplusplus +extern "C" { +#endif +typedef struct UPDATA_BIN_PARAM { + u32 update_bin_len; + union { + u32 bin_addr; + u8 *bin_ptr; + } update_bin_addr; + +} ST_UPDATA_BIN_PARAM, *PST_UPDATA_BIN_PARAM; + +/*//ver_cmp_opt */ +#define VERSION_CMP_EQUAL 0 +#define VERSION_CMP_GREATOR_EQUAL 1 +/*test param */ +#define MAX_VERSION_LEN 30 +typedef struct VERSION_PARAM { + u8 ver_param_len; + u8 ver_cmp_opt; + u8 b_auto_update; + u8 b_force_update; + u16 ic_ver_addr; + u8 ver_param_str[MAX_VERSION_LEN]; + PST_UPDATA_BIN_PARAM p_update_bin_param; +} ST_VERSION_PARAM, *PST_VERSION_PARAM; + +/*//---------------------Fw state check----------------------//*/ +typedef struct CHK_FW_RUN_STATE_PARAM { + u8 option; +} ST_CHK_FW_RUN_STATE_PARAM, *PST_CHK_FW_RUN_STATE_PARAM; + +/*//---------------------Gesture test----------------------//*/ +#define MAX_GESTURE_VER_BUF_SIZE 10 +typedef struct GESTURE_TEST_PARAM { + u16 ver_addr; + u8 ver_len; + u8 option; + u8 ver_buf[MAX_GESTURE_VER_BUF_SIZE]; +} ST_GESTURE_TEST_PARAM, *PST_GESTURE_TEST_PARAM; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/user_test_type_def.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/user_test_type_def.h new file mode 100644 index 000000000000..4918ef0a3b2a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/test_core/user_test_type_def.h @@ -0,0 +1,143 @@ +/******************** (C) COPYRIGHT 2016 Goodix ******************** +* File Name : user_test_type_def.h +* Author : Bob Huang +* Version : V1.0.0 +* Date : 07/26/2017 +* Description : The basic type in user test module +*******************************************************************************/ +#ifndef TP_TEST_MODULE_DISABLE + +#ifndef USER_TEST_TYPE_DEF_H +#define USER_TEST_TYPE_DEF_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define KERNEL_CODE_OPEN +/*//--------------------Platform Micro--------------------//*/ +#if defined(PC_CODE_OPEN) +#define PC_CODE 1 +#else +#define PC_CODE 0 +#endif + +#if defined(ARM_CODE_OPEN) +#define ARM_CODE 1 +#else +#define ARM_CODE 0 +#endif + +#if defined(ANDROID_CODE_OPEN) +#define ANDROID_CODE 1 +#else +#define ANDROID_CODE 0 +#endif + +#if defined(QNX_CODE_OPEN) +#define QNX_CODE 1 +#else +#define QNX_CODE 0 +#endif + +#if defined(WCE_CODE_OPEN) +#define WCE_CODE 1 +#else +#define WCE_CODE 0 +#endif + +#if defined(KERNEL_CODE_OPEN) +#define LINUX_KERNEL 1 +#else +#define LINUX_KERNEL 0 +#endif + +/*//----------------------------------------//*/ +#define IN +#define OUT +#define IN_OUT + +#if WCE_CODE == 1 +typedef unsigned char u8; +typedef const unsigned char cu8; +typedef unsigned short u16; +typedef const unsigned short cu16; +typedef unsigned int u32; +typedef const unsigned int cu32; +typedef int s32; +typedef const int cs32; +typedef signed short s16; +typedef const signed short cs16; +typedef void *ptr32; +typedef void const *cptr32; +typedef unsigned long vu32; +typedef const unsigned long cvu32; +#define NULL 0 +typedef const char *cstr; + +#elif PC_CODE == 1 +typedef char s8; +typedef unsigned char u8; +typedef const unsigned char cu8; +typedef unsigned short u16; +typedef const unsigned short cu16; +typedef unsigned int u32; +typedef const unsigned int cu32; +typedef int s32; +typedef const int cs32; +typedef signed short s16; +typedef const signed short cs16; +typedef void *ptr32; +typedef void const *cptr32; +typedef unsigned long vu32; +typedef const unsigned long cvu32; + +#define NULL 0 + +typedef const char *cstr; +#elif ARM_CODE == 1 +#include "type.h" +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef int s32; + +typedef const unsigned short cu16; +typedef const signed short cs16; +typedef signed short s16; +typedef void *ptr32; +typedef void const *cptr32; + +#ifdef STM32F1XX +typedef unsigned int uint32_t; +typedef int int32_t; +typedef const char *cstr; +#endif + +#elif ANDROID_CODE == 1 || QNX_CODE || LINUX_KERNEL == 1 +//typedef unsigned char u8; +//typedef signed char s8; +typedef const unsigned char cu8; +//typedef unsigned short u16; +typedef const unsigned short cu16; +//typedef unsigned int u32; +typedef const unsigned int cu32; +//typedef int s32; +typedef const int cs32; +//typedef signed short s16; +typedef const signed short cs16; +typedef void *ptr32; +typedef void const *cptr32; +typedef unsigned long vu32; +typedef const unsigned long cvu32; +typedef const char *cstr; + +#endif + +#ifdef __cplusplus +} +#endif +#endif +#endif diff --git a/drivers/input/touchscreen/xiaomi/ndt_core.c b/drivers/input/touchscreen/xiaomi/ndt_core.c new file mode 100644 index 000000000000..1f3851b32a2a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/ndt_core.c @@ -0,0 +1,1380 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ndt_core.h" +#ifdef CONFIG_TOUCHSCREEN_ST_CORE +#include "./fts/fts.h" +#endif +#ifdef CONFIG_TOUCHSCREEN_ST_FTS_V521 +#include "./fts_521/fts.h" +#endif +#define IIC_EEPROM 0 +#define IIC_DEV_ID 0x02 +#define IIC_MANU_ID 0x03 +#define IIC_MODULE_ID 0x04 +#define IIC_FW_VER 0x05 +#define IIC_WAKE_UP 0x06 +#define IIC_SLEEP 0x07 +#define IIC_DEBUG_MODE 0x60 +#define IIC_DATA_READY 0x61 +#define IIC_DEBUG_DATA1 0x62 +#define IIC_DEBUG_DATA2 0x63 +#define IIC_DEBUG_DATA3 0x64 +#define IIC_DEBUG_DATA4 0x65 +#define IIC_KEY_SEN 0xD0 +#define CONFIG_INPUT_NDT_FWUPDATE + +#ifdef CONFIG_INPUT_NDT_INTERRUPT +#define RELEASE_THRE 70 +#endif +static struct i2c_client *g_ndt_client; +struct input_dev *ndt_input_dev; +static int ndt_read_register(unsigned char reg, unsigned char *datbuf, + int byteno); +static int ndt_write_register(unsigned char reg, unsigned char *datbuf, + int byteno); +#ifdef CONFIG_INPUT_NDT_FWUPDATE +static int ndt_read_eeprom(unsigned short reg, unsigned char *datbuf, + int byteno); +static int ndt_write_eeprom(unsigned short reg, unsigned char *datbuf, + int byteno); +static void ndt_reset(void); +#endif +#ifdef CONFIG_INPUT_NDT_FWUPDATE +static int ndt_burn_fw(unsigned char *buf, unsigned int len); +static int ndt_eeprom_erase(void); +static int ndt_eeprom_skip(void); +static ssize_t pressure_update_fw_show(struct device *dev, + struct device_attribute *attr, + char *buf); +static ssize_t pressure_update_fw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); +static ssize_t pressure_erase_fw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); +static ssize_t pressure_force_update_fw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); +#endif +static ssize_t pressure_fw_info_show(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t pressure_pressure_show(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t ndt_threshold_show(struct device *dev, + struct device_attribute *attr, char *buf); +static ssize_t ndt_reset_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count); +static ssize_t ndt_irq_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); +static ssize_t ndt_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); +static ssize_t ndt_reset_and_read_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); +static DEVICE_ATTR(fw_info, 0444, pressure_fw_info_show, NULL); +static DEVICE_ATTR(pressure, 0444, pressure_pressure_show, NULL); +static DEVICE_ATTR(reset, 0200, NULL, ndt_reset_store); +static DEVICE_ATTR(irq_enable, 0200, NULL, ndt_irq_enable_store); +static DEVICE_ATTR(reset_and_read, 0200, NULL, ndt_reset_and_read_store); +static DEVICE_ATTR(threshold, 0644, ndt_threshold_show, ndt_threshold_store); +#ifdef CONFIG_INPUT_NDT_FWUPDATE +static DEVICE_ATTR(fw_update, (S_IRUGO | S_IWUSR | S_IWGRP), + pressure_update_fw_show, pressure_update_fw_store); +static DEVICE_ATTR(fw_erase, (S_IRUGO | S_IWUSR | S_IWGRP), + pressure_update_fw_show, pressure_erase_fw_store); +static DEVICE_ATTR(fw_update_force, (S_IRUGO | S_IWUSR | S_IWGRP), + pressure_update_fw_show, pressure_force_update_fw_store); +#endif + +static struct attribute *ndt_attr[] = { &dev_attr_fw_info.attr, + &dev_attr_pressure.attr, + &dev_attr_reset.attr, + &dev_attr_irq_enable.attr, + &dev_attr_reset_and_read.attr, + &dev_attr_threshold.attr, +#ifdef CONFIG_INPUT_NDT_FWUPDATE + &dev_attr_fw_update.attr, + &dev_attr_fw_update_force.attr, + &dev_attr_fw_erase.attr, +#endif + NULL }; + +static const struct attribute_group ndt_attr_group = { + .attrs = ndt_attr, +}; + +struct ndt_force_data { + struct i2c_client *client; + struct input_dev *input_dev; + struct hrtimer release_timer; + int released; + struct work_struct release_work; + struct workqueue_struct *event_wq; + int report_status; + struct ndt_platform_data *pdata; + int suspend_flag; + struct regulator *ndt_vdd; + struct regulator *ndt_vddio; + bool fw_updated; +}; + +struct ndt_platform_data { + int irq_gpio; +}; + +static int ndt_read_register(unsigned char reg, unsigned char *datbuf, + int byteno) +{ + struct i2c_msg msg[2]; + int ret = 0, retry = 0; + msg[0].addr = g_ndt_client->addr; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = ® + msg[1].addr = g_ndt_client->addr; + msg[1].flags = I2C_M_RD; + msg[1].len = byteno; + msg[1].buf = datbuf; + + if (!datbuf) + return -EINVAL; + do { + ret = i2c_transfer(g_ndt_client->adapter, msg, 2); + if (ret >= 0) + break; + if (ret < 0) + pr_err("ndt:i2c_transfer Error ! err_code:%d, retry:%d\n", + ret, retry); + } while (retry++ < 5); + return ret; +} + +static int ndt_write_register(unsigned char reg, unsigned char *datbuf, + int byteno) +{ + unsigned char *buf; + struct i2c_msg msg; + int ret = 0, retry = 0; + + if (!datbuf) + return -EINVAL; + + buf = (unsigned char *)kmalloc(byteno + 1, GFP_KERNEL); + + if (!buf) + return -EINVAL; + + memset(buf, 0, byteno + 1); + buf[0] = reg; + + if (byteno > 0) { + memcpy(buf + 1, datbuf, byteno); + } + msg.addr = g_ndt_client->addr; + msg.flags = 0; + msg.len = byteno + 1; + msg.buf = buf; + do { + ret = i2c_transfer(g_ndt_client->adapter, &msg, 1); + if (ret >= 0) + break; + if (ret < 0) { + pr_err("ndt:i2c_transfer Error ! err_code:%d, retry:%d\n", + ret, retry); + } + } while (retry++ < 5); + + kfree(buf); + return ret; +} + +static unsigned int g_last_x; +static unsigned int g_last_y; +static unsigned char g_touch_flag; + +int ndt_get_pressure(int touch_flag, int x, int y) +{ + int i; + int pressure; + unsigned char buf[10]; + int count = 0; + int ndt_press_num = 0; + + if (g_ndt_client == NULL) + return 1; + + pr_debug("%s,touch_flag:%d,g_touch_flag:%d,x:%d,y:%d\n", __func__, + touch_flag, g_touch_flag, x, y); + if (touch_flag == 0 && g_touch_flag == 0) { + return 1; + } + + if (touch_flag == 0 && x == 0 && y == 0) { + x = g_last_x; + y = g_last_y; + } + buf[0] = x & 0xff; + buf[1] = x >> 8; + buf[2] = y & 0xff; + buf[3] = y >> 8; + buf[4] = touch_flag; + if (x != g_last_x || y != g_last_y) { + ndt_write_register(0x11, buf, 5); + } + g_last_x = x; + g_last_y = y; + if (touch_flag == 1 && g_touch_flag == 0) { + buf[0] = 1; + ndt_write_register(0x1f, buf, 1); + ndt_write_register(0x10, buf, 1); + g_touch_flag = 1; + } else if (touch_flag == 0 && g_touch_flag == 1) { + buf[0] = 0; + ndt_write_register(0x10, buf, 1); + g_touch_flag = 0; + return 1; + } + buf[0] = 0; + do { + ndt_read_register(0x20, buf, 1); + + if (buf[0] != 0) + break; + msleep(2); + } while (count++ < 10); + + ndt_press_num = buf[0]; + + if (ndt_press_num != 1) + ndt_press_num = 1; + + memset(buf, 0, sizeof(buf)); + + for (i = 0; i < ndt_press_num; i++) { + ndt_read_register(0x21, buf, 2); + } + + pressure = buf[1] << 8 | buf[0]; + pr_debug("ndt:pressure:pressure = %d\n", pressure); + + if (pressure == 0) { + pressure = 1; + } + return pressure; +} + +#ifdef CONFIG_INPUT_NDT_FWUPDATE +static void ndt_reset(void) +{ + int error = 0; + struct ndt_force_data *data = i2c_get_clientdata(g_ndt_client); + + error = regulator_disable(data->ndt_vdd); + msleep(2000); + error = regulator_enable(data->ndt_vdd); + msleep(20); +} + +static int ndt_burn_fw(unsigned char *buf, unsigned int len) +{ + unsigned short reg; + int byteno = 0; + int pos = 0; + unsigned char *read_buf; + int ret = 1; + int i = 0; + int number = 0; + bool i2c_ok_flag = true; + + if (len % 128 != 0) { + pr_err("ndt:burn len is not 128 *\n"); + return 0; + } + /*reset*/ + ndt_reset(); + /*erase flash*/ + read_buf = (unsigned char *)kmalloc(len, GFP_KERNEL); + + do { + pr_info("ndt:burn eeprom number: %d\n", number + 1); + ret = 1; + byteno = 0; + + if (ndt_eeprom_erase() == 0) { + i2c_ok_flag = false; + } + /*write eeprom*/ + pos = 0; + reg = IIC_EEPROM; + byteno = 128; + while (i2c_ok_flag && pos < len) { + if (ndt_write_eeprom(reg, buf + pos, byteno) > 0) { + pr_debug("reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_info("failed!\n"); + i2c_ok_flag = false; + } + + pos += byteno; + reg += byteno; + msleep(15); + } + + /*read eeprom and check*/ + pos = 0; + reg = IIC_EEPROM; + byteno = 256; + + while (i2c_ok_flag && pos < len) { + if (ndt_read_eeprom(reg, read_buf + pos, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, + byteno); + } else { + pr_info("ndt:failed!\n"); + i2c_ok_flag = false; + } + + pos += byteno; + reg += byteno; + msleep(15); + } + + /*check */ + for (i = 0; i < len; i++) { + if (i2c_ok_flag && buf[i] != read_buf[i]) { + pr_info("ndt:burn check error!%d,%d\n", buf[i], + read_buf[i]); + ret = 0; + break; + } + } + + number++; + } while (i2c_ok_flag && number < 3 && ret == 0); + + if (i2c_ok_flag == false || ret == 0) { + pr_err("ndt:burn eeprom fail!\n"); + ret = 0; + } else { + pr_info("ndt:burn eeprom succeed!\n"); + } + + /*exit burn */ + ndt_eeprom_skip(); + kfree(read_buf); + return ret; +} + +static ssize_t pressure_update_fw_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t ret; + int fw_size; + unsigned char ic_fw_ver[2]; + unsigned char reg; + int byteno; + unsigned char file_fw_ver[2]; + const struct firmware *fw_entry = NULL; + char *data; + + ret = request_firmware(&fw_entry, "ndt_fw.bin", &(g_ndt_client->dev)); + if (ret != 0) { + pr_err("%s request firmware failed\n", __func__); + return -EINVAL; + } + + fw_size = fw_entry->size; + data = (char *)kzalloc(fw_size * sizeof(char), GFP_KERNEL); + if (data == NULL) { + pr_err("%s kzalloc memory fail\n", __func__); + release_firmware(fw_entry); + return -EINVAL; + } + memcpy(data, fw_entry->data, fw_size); + + reg = IIC_FW_VER; + byteno = 2; + if (ndt_read_register(reg, ic_fw_ver, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_err("ndt:failed!\n"); + } + memcpy(file_fw_ver, data + 8, sizeof(file_fw_ver)); + pr_info("ndt:read file_fw_ver: %02x%02x\n", file_fw_ver[0], + file_fw_ver[1]); + ret = snprintf(buf, PAGE_SIZE, + "ic_fw_ver:%02x%02x,file_fw_ver:%02x%02x\n", + ic_fw_ver[0], ic_fw_ver[1], file_fw_ver[1], + file_fw_ver[0]); + release_firmware(fw_entry); + kfree(data); + data = NULL; + return ret; +} + +static ssize_t ndt_reset_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int yes_no; + + yes_no = simple_strtoul(buf, NULL, 10); + + if (yes_no == 1) + ndt_reset(); + return count; +} + +static ssize_t ndt_irq_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int yes_no; + + yes_no = simple_strtoul(buf, NULL, 10); + + if (yes_no == 1) + enable_irq(g_ndt_client->irq); + else + disable_irq(g_ndt_client->irq); + return count; +} + +#define MIN_LIMIT 50 +#define MAX_LIMIT 10000 +static ssize_t ndt_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + int value; + unsigned char buffer[10]; + + ret = sscanf(buf, "%d", &value); + if (ret != 1 || value < MIN_LIMIT || value > MAX_LIMIT) { + pr_err("failed to set trigger value -- invalid argumet\n"); + return -EINVAL; + } + + buffer[0] = 0x32; + ndt_write_register(0x80, buffer, 1); + msleep(20); + + buffer[0] = 0x00; + buffer[1] = 0x00; + buffer[2] = value & 0xFF; + buffer[3] = (value >> 8) & 0xFF; + buffer[4] = (value >> 16) & 0xFF; + buffer[5] = (value >> 24) & 0xFF; + ndt_write_register(0x82, buffer, 6); + msleep(20); + + buffer[0] = 0x06; + ndt_write_register(0x81, buffer, 1); + msleep(100); + + buffer[0] = 0x00; + ndt_write_register(0x80, buffer, 1); + pr_info("%s,threshold:%d\n", __func__, value); + + return count; +} + +static ssize_t ndt_reset_and_read_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int yes_no; + int error = 0; + struct ndt_force_data *data = i2c_get_clientdata(g_ndt_client); + static unsigned char g_ver[2] = { 0 }; + + yes_no = simple_strtoul(buf, NULL, 10); + + if (yes_no == 1) { + error = regulator_disable(data->ndt_vdd); + msleep(20); + error = regulator_enable(data->ndt_vdd); + msleep(10); + } + /*i2c test */ + error = ndt_read_register(0x05, g_ver, 2); + if (error < 0) { + pr_err("ndt:i2c test error\n"); + } else + pr_info("ndt:i2c test ok,g_ver:0x%x:0x%x\n", g_ver[0], + g_ver[1]); + return count; +} + +static ssize_t pressure_erase_fw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ndt_force_data *data = i2c_get_clientdata(g_ndt_client); + int yes_no = simple_strtoul(buf, NULL, 10); + + if (yes_no != 1) { + pr_info("ndt:no need update fw\n"); + return count; + } + disable_irq(data->client->irq); + ndt_reset(); + ndt_eeprom_erase(); + enable_irq(data->client->irq); + return count; +} + +static ssize_t pressure_update_fw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int len = 0; + char *fw_name; + + len = strnlen(buf, count); + fw_name = kzalloc(len + 1, GFP_KERNEL); + if (fw_name == NULL) + return -ENOMEM; + if (count > 0) { + strlcpy(fw_name, buf, len); + if (fw_name[len - 1] == '\n') + fw_name[len - 1] = 0; + else + fw_name[len] = 0; + } + pr_info("ndt:fw_name%s\n", fw_name); + ndt_update_fw(false, fw_name); + return count; +} + +static int ndt_eeprom_erase(void) +{ + unsigned char erase_cmd[10]; + unsigned short reg; + int byteno = 0; + + if (g_ndt_client == NULL) + return 0; + + /*erase flash*/ + reg = IIC_EEPROM; + erase_cmd[byteno++] = 0xaa; + erase_cmd[byteno++] = 0x55; + erase_cmd[byteno++] = 0xa5; + erase_cmd[byteno++] = 0x5a; + + if (ndt_write_eeprom(reg, erase_cmd, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_err("ndt:failed!\n"); + return 0; + } + + msleep(2000); + return 1; +} + +static int ndt_eeprom_skip(void) +{ + unsigned char erase_cmd[10]; + unsigned short reg; + int byteno = 0; + + ndt_reset(); + msleep(100); + + if (g_ndt_client == NULL) + return 0; + + reg = IIC_EEPROM; + byteno = 0; + erase_cmd[byteno++] = 0x7e; + erase_cmd[byteno++] = 0xe7; + erase_cmd[byteno++] = 0xee; + erase_cmd[byteno++] = 0x77; + + if (ndt_write_eeprom(reg, erase_cmd, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_err("ndt:failed!\n"); + return 0; + } + + return 1; +} + +int ndt_update_fw(bool force, char *fw_name) +{ + loff_t pos = 0; + char fw_data_len[4]; + int len = 0; + char *fw_data = NULL; + char *data = NULL; + char tmpbuf[10]; + unsigned char ic_fw_ver[2]; + unsigned char reg = 0; + int byteno = 0; + unsigned char file_fw_ver[2]; + int ret = 1; + int fw_size = 0; + const struct firmware *fw_entry = NULL; + struct ndt_force_data *ndt_data = NULL; + i2c_get_clientdata(g_ndt_client); + + if (g_ndt_client == NULL) + return -EINVAL; + ndt_data = i2c_get_clientdata(g_ndt_client); + if (!force && ndt_data->fw_updated) { + pr_info("ndt fw aleady updated or fw is updating,no need to update fw\n"); + return ret; + } + disable_irq(g_ndt_client->irq); + ret = request_firmware(&fw_entry, fw_name, &(g_ndt_client->dev)); + if (ret != 0) { + pr_err("%s request firmware failed\n", __func__); + enable_irq(g_ndt_client->irq); + ndt_threshold_store(&g_ndt_client->dev, NULL, "70", 2); + return -EINVAL; + } + + fw_size = fw_entry->size; + data = (char *)kzalloc(fw_size * sizeof(char), GFP_KERNEL); + if (data == NULL) { + pr_err("%s kzalloc memory fail\n", __func__); + ret = -EINVAL; + goto FAIL; + } + memcpy(data, fw_entry->data, fw_size); + memcpy(tmpbuf, data, sizeof(tmpbuf)); + pr_debug("ndt:file header: 0x%02x%02x\n", tmpbuf[0], tmpbuf[1]); + pos = 8; + data += pos; + reg = IIC_FW_VER; + byteno = 2; + ic_fw_ver[0] = 0; + ic_fw_ver[1] = 0; + if (ndt_read_register(reg, ic_fw_ver, byteno) > 0) { + pr_info("ndt:ic_fw_ver: %02x%02x\n", ic_fw_ver[0], + ic_fw_ver[1]); + } else + pr_err("ndt:failed!\n"); + memcpy(file_fw_ver, data, sizeof(file_fw_ver)); + pr_info("ndt:read file_fw_ver: %02x%02x\n", file_fw_ver[0], + file_fw_ver[1]); + if ((ic_fw_ver[0] | (ic_fw_ver[1] << 8)) == + (file_fw_ver[1] | (file_fw_ver[0] << 8))) { + if (!force) { + pr_info("ndt:fw version is equal,no need update!\n"); + ret = -EINVAL; + goto FAIL; + } + } + pos = 12 - 8; + data += pos; + memcpy(fw_data_len, data, sizeof(fw_data_len)); + pr_debug("ndt:read fw_data_len: 0x%02x%02x%02x%02x\n", fw_data_len[0], + fw_data_len[1], fw_data_len[2], fw_data_len[3]); + len = (int)((unsigned int)fw_data_len[3] << 0) | + ((unsigned int)fw_data_len[2] << 8) | + ((unsigned int)fw_data_len[1] << 16) | (fw_data_len[0] << 24); + fw_data = (char *)kzalloc(len, GFP_KERNEL); + if (fw_data == NULL) { + pr_err("%s malloc fw_data error", __func__); + ret = -EINVAL; + goto FAIL; + } + pos = 0x100 - 0x0c; + data += pos; + memcpy(fw_data, data, len); + + if (ndt_burn_fw(fw_data, len) == 0) { + pr_err("ndt:Burn FW failed!\n"); + ret = -EINVAL; + } +FAIL: + if (data) { + kfree(data); + data = NULL; + } + if (fw_data) { + kfree(fw_data); + fw_data = NULL; + } + release_firmware(fw_entry); + enable_irq(g_ndt_client->irq); + ndt_threshold_store(&g_ndt_client->dev, NULL, "70", 2); + return ret; +} + +static ssize_t pressure_force_update_fw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int len = 0; + char *fw_name; + + len = strnlen(buf, count); + fw_name = kzalloc(len + 1, GFP_KERNEL); + if (fw_name == NULL) + return -ENOMEM; + if (count > 0) { + strlcpy(fw_name, buf, len); + if (fw_name[len - 1] == '\n') + fw_name[len - 1] = 0; + else + fw_name[len] = 0; + } + pr_info("ndt:fw_name%s\n", fw_name); + ndt_update_fw(true, fw_name); + return count; +} + +#endif + +bool ndt_is_pressed(void) +{ + struct ndt_force_data *data = NULL; + + if (g_ndt_client == NULL) + return false; + else { + data = i2c_get_clientdata(g_ndt_client); + return data->released; + } +} + +static ssize_t pressure_pressure_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int pressure, count; + int touch_down, x, y; + + fts_get_pointer(&touch_down, &x, &y); + pressure = ndt_get_pressure(touch_down, x, y); + + count = snprintf(buf, PAGE_SIZE, "Pressure:%d\n", pressure); + return count; +} + +static ssize_t pressure_fw_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i = 0; + char s_dev_id[30]; + ssize_t ret; + unsigned char dev_id[10]; + unsigned char manu_id[2]; + unsigned char module_id[2]; + unsigned char fw_ver[2]; + unsigned char reg; + int byteno = 0; + + memset(dev_id, 0, sizeof(dev_id)); + memset(manu_id, 0, sizeof(manu_id)); + memset(module_id, 0, sizeof(module_id)); + memset(fw_ver, 0, sizeof(fw_ver)); + reg = IIC_DEV_ID; + byteno = 10; + + if (ndt_read_register(reg, dev_id, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_err("ndt:failed!\n"); + } + + reg = IIC_MANU_ID; + byteno = 2; + + if (ndt_read_register(reg, manu_id, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_err("ndt:failed!\n"); + } + + reg = IIC_MODULE_ID; + byteno = 2; + + if (ndt_read_register(reg, module_id, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_err("ndt:failed!\n"); + } + + reg = IIC_FW_VER; + byteno = 2; + + if (ndt_read_register(reg, fw_ver, byteno) > 0) { + pr_debug("ndt:reg=0x%02x,byteno=%d\n", reg, byteno); + } else { + pr_err("ndt:failed!\n"); + } + + memset(s_dev_id, 0, 30); + + for (i = 0; i < 10; i++) { + snprintf(s_dev_id + 2 * i, PAGE_SIZE, "%02x", dev_id[i]); + } + + ret = snprintf( + buf, PAGE_SIZE, + "device id:%s,manu id:%02x%02x,module id:%02x%02x,fw version:%02x%02x\n", + s_dev_id, manu_id[0], manu_id[1], module_id[0], module_id[1], + fw_ver[0], fw_ver[1]); + return ret + 1; +} + +static ssize_t ndt_threshold_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + int value; + int retry = 0; + unsigned char buffer[10]; + + buffer[0] = 0x33; + ndt_write_register(0x80, buffer, 1); + msleep(20); + buffer[0] = 0x00; + buffer[1] = 0x00; + ndt_write_register(0x82, buffer, 2); + msleep(20); + buffer[0] = 0x02; + ndt_write_register(0x81, buffer, 1); + msleep(20); + /* check if ready*/ + do { + ndt_read_register(0x81, buffer, 1); + if (buffer[0] == 1 || buffer[0] == 4) + break; + msleep(20); + } while (retry++ < 5); + if (buffer[0] != 4) { + ret = snprintf(buf, PAGE_SIZE, "failed to read back threshold"); + goto exit_error; + } + ndt_read_register(0x82, buffer, 4); + value = buffer[3] << 24 | buffer[2] << 16 | buffer[1] << 8 | buffer[0]; + ret = snprintf(buf, PAGE_SIZE, "threshold: %d\n", value); +exit_error: + buffer[0] = 0x00; + ndt_write_register(0x80, buffer, 1); + return ret; +} + +#ifdef CONFIG_INPUT_NDT_FWUPDATE +static int ndt_read_eeprom(unsigned short reg, unsigned char *datbuf, + int byteno) +{ + struct i2c_msg msg[2]; + int ret; + unsigned char reg16[2]; + int count = 0; + + if (!datbuf) + return -EINVAL; + + reg16[0] = (reg >> 8) & 0xff; + reg16[1] = reg & 0xff; + msg[0].addr = g_ndt_client->addr; + msg[0].flags = 0; + msg[0].len = 2; + msg[0].buf = reg16; + msg[1].addr = g_ndt_client->addr; + msg[1].flags = I2C_M_RD; + msg[1].len = byteno; + msg[1].buf = datbuf; + do { + ret = i2c_transfer(g_ndt_client->adapter, msg, 2); + if (ret >= 0) + break; + msleep(1); + } while (count++ < 5); + + if (ret < 0) { + pr_err("ndt:i2c_transfer Error ! err_code:%d\n", ret); + } else { + pr_debug("ndt:i2c_transfer OK !\n"); + } + + return ret; +} + +static int ndt_write_eeprom(unsigned short reg, unsigned char *datbuf, + int byteno) +{ + unsigned char *buf; + struct i2c_msg msg; + int ret; + int count = 0; + + if (!datbuf) + return -EINVAL; + + buf = (unsigned char *)kmalloc(byteno + 2, GFP_KERNEL); + + if (!buf) + return -EINVAL; + + memset(buf, 0, byteno + 2); + buf[0] = (reg >> 8) & 0xff; + buf[1] = reg & 0xff; + memcpy(buf + 2, datbuf, byteno); + msg.addr = g_ndt_client->addr; + msg.flags = 0; + msg.len = byteno + 2; + msg.buf = buf; + do { + ret = i2c_transfer(g_ndt_client->adapter, &msg, 1); + if (ret >= 0) + break; + msleep(1); + } while (count++ < 5); + + if (ret < 0) { + pr_err("ndt:i2c_master_send Error ! err_code:%d\n", ret); + } else { + pr_debug("ndt:i2c_master_send OK !\n"); + } + + kfree(buf); + return ret; +} +#endif + +#ifdef CONFIG_INPUT_NDT_INTERRUPT +static void ndt_abs_input_report(struct ndt_force_data *data, int pressure) +{ + if (fts_is_infod()) { + input_report_abs(data->input_dev, ABS_MT_PRESSURE, pressure); + input_sync(data->input_dev); + } +} + +bool ndt_down_flag; + +static void ndt_release_work(struct work_struct *work) +{ + struct ndt_force_data *data = + container_of(work, struct ndt_force_data, release_work); + int pressure = 0; + int touch_down, x, y; + + fts_get_pointer(&touch_down, &x, &y); + pressure = ndt_get_pressure(touch_down, x, y); + pr_info("%s,pressure:%d\n", __func__, pressure); + if (pressure < RELEASE_THRE) { + input_report_abs(data->input_dev, ABS_MT_PRESSURE, 0); + input_sync(data->input_dev); + } + ndt_down_flag = false; + /* +#ifdef CONFIG_TOUCHSCREEN_ST_CORE + fts_senseoff_without_cal(); +#endif +*/ +} + +static enum hrtimer_restart ndt_timer_func(struct hrtimer *timer) +{ + struct ndt_force_data *data = + container_of(timer, struct ndt_force_data, release_timer); + + data->released = 1; + queue_work(data->event_wq, &data->release_work); + return HRTIMER_NORESTART; +} + +static irqreturn_t ndt_force_interrupt(int irq, void *dev_id) +{ + struct ndt_force_data *data = (struct ndt_force_data *)dev_id; + int pressure; + int touch_down, x, y; + + pr_debug("%s\n", __func__); + fts_get_pointer(&touch_down, &x, &y); + pressure = ndt_get_pressure(touch_down, x, y); + if (!ndt_down_flag) { + pr_info("ndt down in the fod area,pressure:%d\n", pressure); + ndt_down_flag = true; + } + /* +#ifdef CONFIG_TOUCHSCREEN_ST_CORE + fts_senseon_without_cal(); +#endif +*/ + ndt_abs_input_report(data, pressure); + if (data->released == 1) + hrtimer_start(&data->release_timer, + ktime_set(0, 15 * 1000 * 1000), HRTIMER_MODE_REL); + if (!data->released) { + hrtimer_start_range_ns(&data->release_timer, + ns_to_ktime(15 * 1000 * 1000), 0, + HRTIMER_MODE_REL); + } + data->released = 0; + return IRQ_HANDLED; +} +#endif + +static int ndt_open(struct inode *inode, struct file *file) +{ + if (g_ndt_client == NULL) { + return -EINVAL; + } else { + return 0; + } +} + +static int ndt_close(struct inode *inode, struct file *file) +{ + return 0; +} + +static ssize_t ndt_read(struct file *file, char __user *buf, size_t count, + loff_t *offset) +{ + char *kbuf = NULL; + int err = 0; + char reg = 0; + + kbuf = kzalloc(count, GFP_KERNEL); + if (!kbuf) { + err = -ENOMEM; + goto exit; + } + /*get reg addr buf[0]*/ + if (copy_from_user(®, buf, 1)) { + err = -EFAULT; + goto exit_kfree; + } + + ndt_read_register(reg, kbuf, count); + + if (copy_to_user(buf + 1, kbuf, count)) + err = -EFAULT; +exit_kfree: + kfree(kbuf); + +exit: + return err; +} + +static ssize_t ndt_write(struct file *file, const char __user *buf, + size_t count, loff_t *offset) +{ + char *kbuf = NULL; + int err = 0; + char reg = 0; + + kbuf = kzalloc(count, GFP_KERNEL); + if (!kbuf) { + err = -ENOMEM; + goto exit; + } + + if (copy_from_user(®, buf, 1) || + copy_from_user(kbuf, buf + 1, count)) { + err = -EFAULT; + goto exit_kfree; + } + + ndt_write_register(reg, kbuf, count); +exit_kfree: + kfree(kbuf); + +exit: + return err; +} + +static const struct file_operations ndt_fops = { + .owner = THIS_MODULE, + .read = ndt_read, + .write = ndt_write, + .open = ndt_open, + .release = ndt_close, +}; + +static struct miscdevice ndt_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = "ndt_i2c_node", + .fops = &ndt_fops, +}; + +static int ndt_parse_dt(struct device *dev, struct ndt_platform_data *pdata) +{ + struct device_node *np = dev->of_node; + + if (!np) + return -EINVAL; + /* irq gpio */ + pdata->irq_gpio = of_get_named_gpio(np, "ndt,irq-gpio", 0); + return 0; +} + +#ifdef CONFIG_PM +static int ndt_pm_suspend(struct device *dev) +{ + struct ndt_force_data *data = dev_get_drvdata(dev); + pr_info("%s enable ndt irq wake\n", __func__); + enable_irq_wake(data->client->irq); +#ifdef CONFIG_INPUT_NDT_INTERRUPT + hrtimer_cancel(&data->release_timer); + cancel_work(&data->release_work); +#endif + data->suspend_flag = 1; + return 0; +} + +static int ndt_pm_resume(struct device *dev) +{ + struct ndt_force_data *data = dev_get_drvdata(dev); + pr_info("%s disable ndt irq wake\n", __func__); + disable_irq_wake(data->client->irq); + data->suspend_flag = 0; + return 0; +} + +static const struct dev_pm_ops ndt_dev_pm_ops = { + .suspend = ndt_pm_suspend, + .resume = ndt_pm_resume, +}; +#endif + +static int ndt_force_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ndt_force_data *data; + int error = -EINVAL; + static unsigned char g_ver[2] = { 0 }; + + data = kzalloc(sizeof(struct ndt_force_data), GFP_KERNEL); + if (!data) { + dev_err(&client->dev, "Failed to allocate memory for data!\n"); + return -ENOMEM; + } + + data->pdata = kzalloc(sizeof(struct ndt_platform_data), GFP_KERNEL); + if (!data->pdata) { + dev_err(&client->dev, "Failed to allocate memory for data!\n"); + goto ndt_free_data; + } + + error = ndt_parse_dt(&client->dev, data->pdata); + if (error < 0) { + dev_err(&client->dev, "Failed to get pdata!\n"); + goto ndt_free_pdata; + } + + error = i2c_check_functionality(client->adapter, I2C_FUNC_I2C); + if (!error) { + dev_err(&client->dev, "I2C check functionality failed\n"); + goto ndt_free_pdata; + } + /* enable power */ + data->ndt_vdd = regulator_get(&client->dev, "ndt,vdd"); + if (IS_ERR(data->ndt_vdd)) { + dev_err(&client->dev, "failed to get ndt vdd"); + goto ndt_free_pdata; + } + error = regulator_enable(data->ndt_vdd); + if (error < 0) { + dev_err(&client->dev, "Failed to enable power regulator\n"); + goto ndt_free_pdata; + } + + data->ndt_vddio = regulator_get(&client->dev, "ndt,vddio"); + if (IS_ERR(data->ndt_vddio)) { + dev_err(&client->dev, "failed to get ndt vdd"); + goto ndt_free_pdata; + } + error = regulator_enable(data->ndt_vddio); + if (error < 0) { + dev_err(&client->dev, "Failed to enable power regulator\n"); + goto ndt_free_pdata; + } + + if (data->pdata->irq_gpio) { + error = gpio_request(data->pdata->irq_gpio, + "ndt_force_irq_gpio"); + if (error) { + dev_err(&client->dev, "Unable to request gpio [%d]\n", + data->pdata->irq_gpio); + goto ndt_vddio_disable; + } + error = gpio_direction_input(data->pdata->irq_gpio); + if (error) { + dev_err(&client->dev, + "unable to set direction for gpio [%d]\n", + data->pdata->irq_gpio); + goto ndt_free_irq_gpio; + } + client->irq = gpio_to_irq(data->pdata->irq_gpio); + } + data->client = client; + i2c_set_clientdata(data->client, data); + g_ndt_client = client; + data->fw_updated = false; + + /* Initialize input device */ + data->input_dev = input_allocate_device(); + + if (!data->input_dev) { + dev_err(&client->dev, "Failed to allocate input device\n"); + goto ndt_free_irq_gpio; + } + data->input_dev->name = "ndt_force"; + data->input_dev->id.bustype = BUS_I2C; + data->input_dev->dev.parent = &data->client->dev; + input_set_capability(data->input_dev, EV_KEY, KEY_POWER); + input_set_abs_params(data->input_dev, ABS_MT_PRESSURE, 0, 2048, 0, 0); + input_set_drvdata(data->input_dev, data); + dev_set_drvdata(&data->client->dev, data); + __set_bit(EV_SYN, data->input_dev->evbit); + __set_bit(EV_KEY, data->input_dev->evbit); + error = input_register_device(data->input_dev); + + if (error) { + dev_err(&client->dev, + "Unable to register input device, error: %d\n", error); + goto ndt_free_irq_gpio; + } + + msleep(10); + /*i2c test *, if i2c error ,maybe fw is wrong ,so goon*/ + error = ndt_read_register(0x05, g_ver, 2); + if (error < 0) { + pr_err("ndt:i2c test error, maybe fw fail, force update fw\n"); + error = ndt_update_fw(1, "ndt_fw.bin"); + if (error == -EINVAL) { + pr_err("ndt:i2c error after fw update, unregister device\n"); + goto ndt_free_input_dev; + } else { + pr_err("i2c is ok after fw update\n"); + data->fw_updated = true; + } + } else + pr_info("ndt:i2c test ok,g_ver:0x%x:0x%x\n", g_ver[0], + g_ver[1]); + error = sysfs_create_group(&client->dev.kobj, &ndt_attr_group); + + if (error) + dev_err(&client->dev, "Failure %d creating sysfs group\n", + error); + + data->event_wq = create_singlethread_workqueue("ndt-event-queue"); +#ifdef CONFIG_INPUT_NDT_INTERRUPT + INIT_WORK(&data->release_work, ndt_release_work); + hrtimer_init(&data->release_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + data->release_timer.function = ndt_timer_func; + data->released = 1; + error = request_threaded_irq(client->irq, NULL, ndt_force_interrupt, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + client->dev.driver->name, data); + + if (error) { + dev_err(&client->dev, "Error %d registering irq\n", error); + goto ndt_free_input_dev; + } +#endif + misc_register(&ndt_misc); + ndt_input_dev = data->input_dev; + pr_info("%s,probe ok\n", __func__); + return 0; +ndt_free_input_dev: + input_unregister_device(data->input_dev); + g_ndt_client = NULL; +ndt_free_irq_gpio: + gpio_free(data->pdata->irq_gpio); +ndt_vddio_disable: + regulator_disable(data->ndt_vddio); +ndt_free_pdata: + kfree(data->pdata); + data->pdata = NULL; +ndt_free_data: + kfree(data); + data = NULL; + return error; +} + +static const struct i2c_device_id cyt_id[] = { + { "ndt_press", 0 }, + {}, +}; + +static struct of_device_id ndt_match_table[] = { + { + .compatible = "ndt,press", + }, + {}, +}; + +static int ndt_force_remove(struct i2c_client *client) +{ + struct ndt_force_data *data = i2c_get_clientdata(client); + struct ndt_platform_data *pdata = data->pdata; + + misc_deregister(&ndt_misc); + free_irq(client->irq, data); + if (data->input_dev != NULL) + input_unregister_device(data->input_dev); + + gpio_free(pdata->irq_gpio); + if (pdata != NULL) { + kfree(pdata); + pdata = NULL; + } + if (data != NULL) { + kfree(data); + data = NULL; + } + return 0; +} + +static struct i2c_driver ndt_force_driver = { + .driver = { + .name = "ndt_press", + .owner = THIS_MODULE, + .of_match_table = ndt_match_table, +#ifdef CONFIG_PM + .pm = &ndt_dev_pm_ops, +#endif + }, + .probe = ndt_force_probe, + .remove = ndt_force_remove, + .id_table = cyt_id, +}; + +static int __init ndt_force_init(void) +{ + return i2c_add_driver(&ndt_force_driver); +} + +static void __exit ndt_force_exit(void) +{ + i2c_del_driver(&ndt_force_driver); +} + +module_init(ndt_force_init); +module_exit(ndt_force_exit); + +MODULE_AUTHOR("Liuyinghong "); +MODULE_DESCRIPTION("Ndt Press Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/xiaomi/ndt_core.h b/drivers/input/touchscreen/xiaomi/ndt_core.h new file mode 100644 index 000000000000..78650cac565a --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/ndt_core.h @@ -0,0 +1,3 @@ +int ndt_update_fw(bool force, char *fw_name); +bool ndt_is_pressed(void); +int ndt_get_pressure(int touch_flag, int x, int y); diff --git a/drivers/input/touchscreen/xiaomi/nt36523/Kconfig b/drivers/input/touchscreen/xiaomi/nt36523/Kconfig new file mode 100644 index 000000000000..c67b1b795d4e --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/Kconfig @@ -0,0 +1,11 @@ +# +# Novatek NT36523 touchscreen driver configuration +# +config TOUCHSCREEN_NT36523_HOSTDL_SPI + tristate "Novatek NT36523 host download SPI driver" + default n + help + Say Y here if you have a Novatek NT36523 no flash touchscreen connected + to your system by SPI bus. + + If unsure, say N. diff --git a/drivers/input/touchscreen/xiaomi/nt36523/Makefile b/drivers/input/touchscreen/xiaomi/nt36523/Makefile new file mode 100644 index 000000000000..4f0bf8732633 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the Novatek NT36523 touchscreen driver. +# + +obj-$(CONFIG_TOUCHSCREEN_NT36523_HOSTDL_SPI) += nt36523_touch.o +nt36523_touch-y := nt36xxx.o \ + nt36xxx_fw_update.o \ + nt36xxx_ext_proc.o \ + nt36xxx_mp_ctrlram.o diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c new file mode 100644 index 000000000000..1851c7c5b5e6 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -0,0 +1,3992 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * $Revision: 73033 $ + * $Date: 2020-11-26 10:09:14 +0800 (週四, 26 å一月 2020) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM +#include +#endif +#include +#include +#elif defined(CONFIG_HAS_EARLYSUSPEND) +#include +#endif + +#include "nt36xxx.h" +#ifndef NVT_SAVE_TESTDATA_IN_FILE +#include "nt36xxx_mp_ctrlram.h" +#endif +#if NVT_TOUCH_ESD_PROTECT +#include +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +#include "../xiaomi/xiaomi_touch.h" +#endif + +#if NVT_TOUCH_ESD_PROTECT +static struct delayed_work nvt_esd_check_work; +static struct workqueue_struct *nvt_esd_check_wq; +static unsigned long irq_timer = 0; +uint8_t esd_check = false; +uint8_t esd_retry = 0; +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#if NVT_TOUCH_EXT_PROC +extern int32_t nvt_extra_proc_init(void); +extern void nvt_extra_proc_deinit(void); +#endif + +#if NVT_TOUCH_MP +extern int32_t nvt_mp_proc_init(void); +extern void nvt_mp_proc_deinit(void); +#endif + +struct nvt_ts_data *ts; + +#if BOOT_UPDATE_FIRMWARE +static struct workqueue_struct *nvt_fwu_wq; +static struct workqueue_struct *nvt_lockdown_wq; +extern void Boot_Update_Firmware(struct work_struct *work); +#endif + +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM +static int nvt_drm_notifier_callback(struct notifier_block *self, + unsigned long event, void *data); +#else +static int nvt_fb_notifier_callback(struct notifier_block *self, + unsigned long event, void *data); +#endif +#elif defined(CONFIG_HAS_EARLYSUSPEND) +static void nvt_ts_early_suspend(struct early_suspend *h); +static void nvt_ts_late_resume(struct early_suspend *h); +#endif + +static int32_t nvt_ts_suspend(struct device *dev); +static int32_t nvt_ts_resume(struct device *dev); +extern int dsi_panel_lockdown_info_read(unsigned char *plockdowninfo); +extern void dsi_panel_doubleclick_enable(bool on); +extern void touch_irq_boost(void); +extern void lpm_disable_for_input(bool on); +extern int pen_charge_state_notifier_register_client(struct notifier_block *nb); +extern int +pen_charge_state_notifier_unregister_client(struct notifier_block *nb); + +uint32_t ENG_RST_ADDR = 0x7FFF80; +uint32_t SWRST_N8_ADDR = 0; //read from dtsi +uint32_t SPI_RD_FAST_ADDR = 0; //read from dtsi + +#if TOUCH_KEY_NUM > 0 +const uint16_t touch_key_array[TOUCH_KEY_NUM] = { KEY_BACK, KEY_HOME, + KEY_MENU }; +#endif + +#if WAKEUP_GESTURE +const uint16_t gesture_key_array[] = { + KEY_POWER, //GESTURE_WORD_C + KEY_POWER, //GESTURE_WORD_W + KEY_POWER, //GESTURE_WORD_V + KEY_WAKEUP, //GESTURE_DOUBLE_CLICK + KEY_POWER, //GESTURE_WORD_Z + KEY_POWER, //GESTURE_WORD_M + KEY_POWER, //GESTURE_WORD_O + KEY_POWER, //GESTURE_WORD_e + KEY_POWER, //GESTURE_WORD_S + KEY_POWER, //GESTURE_SLIDE_UP + KEY_POWER, //GESTURE_SLIDE_DOWN + KEY_POWER, //GESTURE_SLIDE_LEFT + KEY_POWER, //GESTURE_SLIDE_RIGHT + KEY_WAKEUP, //GESTURE_PEN_ONE_CLICK +}; +#endif + +#ifdef CONFIG_MTK_SPI +const struct mt_chip_conf spi_ctrdata = { + .setuptime = 25, + .holdtime = 25, + .high_time = 5, /* 10MHz (SPI_SPEED=100M / (high_time+low_time(10ns)))*/ + .low_time = 5, + .cs_idletime = 2, + .ulthgh_thrsh = 0, + .cpol = 0, + .cpha = 0, + .rx_mlsb = 1, + .tx_mlsb = 1, + .tx_endian = 0, + .rx_endian = 0, + .com_mod = DMA_TRANSFER, + .pause = 0, + .finish_intr = 1, + .deassert = 0, + .ulthigh = 0, + .tckdly = 0, +}; +#endif + +#ifdef CONFIG_SPI_MT65XX +const struct mtk_chip_config spi_ctrdata = { + .rx_mlsb = 1, + .tx_mlsb = 1, + .cs_pol = 0, +}; +#endif + +static ssize_t nvt_panel_color_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[2]); +} + +static ssize_t nvt_panel_vendor_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[6]); +} + +static ssize_t nvt_panel_display_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[1]); +} + +static DEVICE_ATTR(panel_color, (S_IRUGO), nvt_panel_color_show, NULL); +static DEVICE_ATTR(panel_vendor, (S_IRUGO), nvt_panel_vendor_show, NULL); +static DEVICE_ATTR(panel_display, (S_IRUGO), nvt_panel_display_show, NULL); + +struct attribute *nvt_panel_attr[] = { + &dev_attr_panel_color.attr, + &dev_attr_panel_vendor.attr, + &dev_attr_panel_display.attr, + NULL, +}; + +static uint8_t bTouchIsAwake = 0; + +/******************************************************* +Description: + Novatek touchscreen irq enable/disable function. + +return: + n.a. +*******************************************************/ +static void nvt_irq_enable(bool enable) +{ + struct irq_desc *desc; + + if (enable) { + if (!ts->irq_enabled) { + enable_irq(ts->client->irq); + ts->irq_enabled = true; + } + } else { + if (ts->irq_enabled) { + disable_irq(ts->client->irq); + ts->irq_enabled = false; + } + } + + desc = irq_to_desc(ts->client->irq); + NVT_LOG("enable=%d, desc->depth=%d\n", enable, desc->depth); +} + +/******************************************************* +Description: + Novatek touchscreen spi read/write core function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static inline int32_t spi_read_write(struct spi_device *client, uint8_t *buf, + size_t len, NVT_SPI_RW rw) +{ + struct spi_message m; + struct spi_transfer t = { + .len = len, + }; + + memset(ts->xbuf, 0, len + DUMMY_BYTES); + memcpy(ts->xbuf, buf, len); + + switch (rw) { + case NVTREAD: + t.tx_buf = ts->xbuf; + t.rx_buf = ts->rbuf; + t.len = (len + DUMMY_BYTES); + break; + + case NVTWRITE: + t.tx_buf = ts->xbuf; + break; + } + + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return spi_sync(client, &m); +} + +/******************************************************* +Description: + Novatek touchscreen spi read function. + +return: + Executive outcomes. 2---succeed. -5---I/O error +*******************************************************/ +int32_t CTP_SPI_READ(struct spi_device *client, uint8_t *buf, uint16_t len) +{ + int32_t ret = -1; + int32_t retries = 0; + + mutex_lock(&ts->xbuf_lock); + + buf[0] = SPI_READ_MASK(buf[0]); + + while (retries < 5) { + ret = spi_read_write(client, buf, len, NVTREAD); + if (ret == 0) + break; + retries++; + } + + if (unlikely(retries == 5)) { + NVT_ERR("read error, ret=%d\n", ret); + ret = -EIO; + } else { + memcpy((buf + 1), (ts->rbuf + 2), (len - 1)); + } + + mutex_unlock(&ts->xbuf_lock); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen spi write function. + +return: + Executive outcomes. 1---succeed. -5---I/O error +*******************************************************/ +int32_t CTP_SPI_WRITE(struct spi_device *client, uint8_t *buf, uint16_t len) +{ + int32_t ret = -1; + int32_t retries = 0; + + mutex_lock(&ts->xbuf_lock); + + buf[0] = SPI_WRITE_MASK(buf[0]); + + while (retries < 5) { + ret = spi_read_write(client, buf, len, NVTWRITE); + if (ret == 0) + break; + retries++; + } + + if (unlikely(retries == 5)) { + NVT_ERR("error, ret=%d\n", ret); + ret = -EIO; + } + + mutex_unlock(&ts->xbuf_lock); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen set index/page/addr address. + +return: + Executive outcomes. 0---succeed. -5---access fail. +*******************************************************/ +int32_t nvt_set_page(uint32_t addr) +{ + uint8_t buf[4] = { 0 }; + + buf[0] = 0xFF; //set index/page/addr command + buf[1] = (addr >> 15) & 0xFF; + buf[2] = (addr >> 7) & 0xFF; + + return CTP_SPI_WRITE(ts->client, buf, 3); +} + +/******************************************************* +Description: + Novatek touchscreen write data to specify address. + +return: + Executive outcomes. 0---succeed. -5---access fail. +*******************************************************/ +int32_t nvt_write_addr(uint32_t addr, uint8_t data) +{ + int32_t ret = 0; + uint8_t buf[4] = { 0 }; + + //---set xdata index--- + buf[0] = 0xFF; //set index/page/addr command + buf[1] = (addr >> 15) & 0xFF; + buf[2] = (addr >> 7) & 0xFF; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret) { + NVT_ERR("set page 0x%06X failed, ret = %d\n", addr, ret); + return ret; + } + + //---write data to index--- + buf[0] = addr & (0x7F); + buf[1] = data; + ret = CTP_SPI_WRITE(ts->client, buf, 2); + if (ret) { + NVT_ERR("write data to 0x%06X failed, ret = %d\n", addr, ret); + return ret; + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen enable hw bld crc function. + +return: + N/A. +*******************************************************/ +void nvt_bld_crc_enable(void) +{ + uint8_t buf[4] = { 0 }; + + //---set xdata index to BLD_CRC_EN_ADDR--- + nvt_set_page(ts->mmap->BLD_CRC_EN_ADDR); + + //---read data from index--- + buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + //---write data to index--- + buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); + buf[1] = buf[1] | (0x01 << 7); + CTP_SPI_WRITE(ts->client, buf, 2); +} + +/******************************************************* +Description: + Novatek touchscreen clear status & enable fw crc function. + +return: + N/A. +*******************************************************/ +void nvt_fw_crc_enable(void) +{ + uint8_t buf[4] = { 0 }; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); + + //---clear fw reset status--- + buf[0] = EVENT_MAP_RESET_COMPLETE & (0x7F); + buf[1] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 2); + + //---enable fw crc--- + buf[0] = EVENT_MAP_HOST_CMD & (0x7F); + buf[1] = 0xAE; //enable fw crc command + CTP_SPI_WRITE(ts->client, buf, 2); +} + +/******************************************************* +Description: + Novatek touchscreen set boot ready function. + +return: + N/A. +*******************************************************/ +void nvt_boot_ready(void) +{ + //---write BOOT_RDY status cmds--- + nvt_write_addr(ts->mmap->BOOT_RDY_ADDR, 1); + + mdelay(5); + + if (!ts->hw_crc) { + //---write BOOT_RDY status cmds--- + nvt_write_addr(ts->mmap->BOOT_RDY_ADDR, 0); + + //---write POR_CD cmds--- + nvt_write_addr(ts->mmap->POR_CD_ADDR, 0xA0); + } +} + +/******************************************************* +Description: + Novatek touchscreen enable auto copy mode function. + +return: + N/A. +*******************************************************/ +void nvt_tx_auto_copy_mode(void) +{ + //---write TX_AUTO_COPY_EN cmds--- + nvt_write_addr(ts->mmap->TX_AUTO_COPY_EN, 0x69); + + NVT_ERR("tx auto copy mode enable\n"); +} + +/******************************************************* +Description: + Novatek touchscreen check spi dma tx info function. + +return: + N/A. +*******************************************************/ +int32_t nvt_check_spi_dma_tx_info(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 200; + + for (i = 0; i < retry; i++) { + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->SPI_DMA_TX_INFO); + + //---read fw status--- + buf[0] = ts->mmap->SPI_DMA_TX_INFO & 0x7F; + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + if (buf[1] == 0x00) + break; + + usleep_range(1000, 1000); + } + + if (i >= retry) { + NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); + return -1; + } else { + return 0; + } +} + +/******************************************************* +Description: + Novatek touchscreen eng reset cmd + function. + +return: + n.a. +*******************************************************/ +void nvt_eng_reset(void) +{ + //---eng reset cmds to ENG_RST_ADDR--- + nvt_write_addr(ENG_RST_ADDR, 0x5A); + + mdelay(1); //wait tMCU_Idle2TP_REX_Hi after TP_RST +} + +/******************************************************* +Description: + Novatek touchscreen reset MCU + function. + +return: + n.a. +*******************************************************/ +void nvt_sw_reset(void) +{ + //---software reset cmds to SWRST_N8_ADDR--- + nvt_write_addr(SWRST_N8_ADDR, 0x55); + + msleep(10); +} + +/******************************************************* +Description: + Novatek touchscreen reset MCU then into idle mode + function. + +return: + n.a. +*******************************************************/ +void nvt_sw_reset_idle(void) +{ + //---MCU idle cmds to SWRST_N8_ADDR--- + nvt_write_addr(SWRST_N8_ADDR, 0xAA); + + msleep(15); +} + +/******************************************************* +Description: + Novatek touchscreen reset MCU (boot) function. + +return: + n.a. +*******************************************************/ +void nvt_bootloader_reset(void) +{ + //---reset cmds to SWRST_N8_ADDR--- + nvt_write_addr(SWRST_N8_ADDR, 0x69); + + mdelay(5); //wait tBRST2FR after Bootload RST + + if (SPI_RD_FAST_ADDR) { + /* disable SPI_RD_FAST */ + nvt_write_addr(SPI_RD_FAST_ADDR, 0x00); + } +} + +/******************************************************* +Description: + Novatek touchscreen clear FW status function. + +return: + Executive outcomes. 0---succeed. -1---fail. +*******************************************************/ +int32_t nvt_clear_fw_status(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 20; + + for (i = 0; i < retry; i++) { + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + //---clear fw status--- + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 2); + + //---read fw status--- + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + if (buf[1] == 0x00) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); + return -1; + } else { + return 0; + } +} + +/******************************************************* +Description: + Novatek touchscreen check FW status function. + +return: + Executive outcomes. 0---succeed. -1---failed. +*******************************************************/ +int32_t nvt_check_fw_status(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 50; + + for (i = 0; i < retry; i++) { + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + //---read fw status--- + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + + if ((buf[1] & 0xF0) == 0xA0) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); + return -1; + } else { + return 0; + } +} + +/******************************************************* +Description: + Novatek touchscreen check FW reset state function. + +return: + Executive outcomes. 0---succeed. -1---failed. +*******************************************************/ +int32_t nvt_check_fw_reset_state(RST_COMPLETE_STATE check_reset_state) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + int32_t retry = 0; + int32_t retry_max = (check_reset_state == RESET_STATE_INIT) ? 10 : 50; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_RESET_COMPLETE); + + while (1) { + //---read reset state--- + buf[0] = EVENT_MAP_RESET_COMPLETE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 6); + + if ((buf[1] >= check_reset_state) && + (buf[1] <= RESET_STATE_MAX)) { + ret = 0; + break; + } + + retry++; + if (unlikely(retry > retry_max)) { + NVT_ERR("error, retry=%d, buf[1]=0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X\n", + retry, buf[1], buf[2], buf[3], buf[4], buf[5]); + ret = -1; + break; + } + + usleep_range(10000, 10000); + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen get novatek project id information + function. + +return: + Executive outcomes. 0---success. -1---fail. +*******************************************************/ +int32_t nvt_read_pid(void) +{ + uint8_t buf[4] = { 0 }; + int32_t ret = 0; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_PROJECTID); + + //---read project id--- + buf[0] = EVENT_MAP_PROJECTID; + buf[1] = 0x00; + buf[2] = 0x00; + CTP_SPI_READ(ts->client, buf, 3); + + ts->nvt_pid = (buf[2] << 8) + buf[1]; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); + + NVT_LOG("PID=%04X\n", ts->nvt_pid); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen get firmware related information + function. + +return: + Executive outcomes. 0---success. -1---fail. +*******************************************************/ +int32_t nvt_get_fw_info(void) +{ + uint8_t buf[64] = { 0 }; + uint32_t retry_count = 0; + int32_t ret = 0; + +info_retry: + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_FWINFO); + + //---read fw info--- + buf[0] = EVENT_MAP_FWINFO; + CTP_SPI_READ(ts->client, buf, 39); + ts->fw_ver = buf[1]; + ts->x_num = buf[3]; + ts->y_num = buf[4]; + ts->abs_x_max = (uint16_t)((buf[5] << 8) | buf[6]); + ts->abs_y_max = (uint16_t)((buf[7] << 8) | buf[8]); + ts->max_button_num = buf[11]; + ts->cascade = buf[34] & 0x01; + if (ts->pen_support) { + ts->x_gang_num = buf[37]; + ts->y_gang_num = buf[38]; + } + + //---clear x_num, y_num if fw info is broken--- + if ((buf[1] + buf[2]) != 0xFF) { + NVT_ERR("FW info is broken! fw_ver=0x%02X, ~fw_ver=0x%02X\n", + buf[1], buf[2]); + ts->fw_ver = 0; + ts->x_num = 18; + ts->y_num = 32; + ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; + ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + ts->max_button_num = TOUCH_KEY_NUM; + + if (retry_count < 3) { + retry_count++; + NVT_ERR("retry_count=%d\n", retry_count); + goto info_retry; + } else { + NVT_ERR("Set default fw_ver=%d, x_num=%d, y_num=%d, " + "abs_x_max=%d, abs_y_max=%d, max_button_num=%d!\n", + ts->fw_ver, ts->x_num, ts->y_num, ts->abs_x_max, + ts->abs_y_max, ts->max_button_num); + ret = -1; + } + } else { + ret = 0; + } + + NVT_LOG("fw_ver = 0x%02X, fw_type = 0x%02X, x_num=%d, y_num=%d\n", + ts->fw_ver, buf[14], ts->x_num, ts->y_num); + + //---Get Novatek PID--- + nvt_read_pid(); + + return ret; +} + +/******************************************************* + Create Device Node (Proc Entry) +*******************************************************/ +#if NVT_TOUCH_PROC +static struct proc_dir_entry *NVT_proc_entry; +#define DEVICE_NAME "NVTSPI" + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI read function. + +return: + Executive outcomes. 2---succeed. -5,-14---failed. +*******************************************************/ +static ssize_t nvt_flash_read(struct file *file, char __user *buff, + size_t count, loff_t *offp) +{ + uint8_t *str = NULL; + int32_t ret = 0; + int32_t retries = 0; + int8_t spi_wr = 0; + uint8_t *buf; + + if ((count > NVT_TRANSFER_LEN + 3) || (count < 3)) { + NVT_ERR("invalid transfer len!\n"); + return -EFAULT; + } + + /* allocate buffer for spi transfer */ + str = (uint8_t *)kzalloc((count), GFP_KERNEL); + if (str == NULL) { + NVT_ERR("kzalloc for buf failed!\n"); + ret = -ENOMEM; + goto kzalloc_failed; + } + + buf = (uint8_t *)kzalloc((count), GFP_KERNEL | GFP_DMA); + if (buf == NULL) { + NVT_ERR("kzalloc for buf failed!\n"); + ret = -ENOMEM; + kfree(str); + str = NULL; + goto kzalloc_failed; + } + + if (copy_from_user(str, buff, count)) { + NVT_ERR("copy from user error\n"); + ret = -EFAULT; + goto out; + } + +#if NVT_TOUCH_ESD_PROTECT + /* + * stop esd check work to avoid case that 0x77 report righ after here to enable esd check again + * finally lead to trigger esd recovery bootloader reset + */ + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + spi_wr = str[0] >> 7; + memcpy(buf, str + 2, ((str[0] & 0x7F) << 8) | str[1]); + + if (spi_wr == NVTWRITE) { //SPI write + while (retries < 20) { + ret = CTP_SPI_WRITE(ts->client, buf, + ((str[0] & 0x7F) << 8) | str[1]); + if (!ret) + break; + else + NVT_ERR("error, retries=%d, ret=%d\n", retries, + ret); + + retries++; + } + + if (unlikely(retries == 20)) { + NVT_ERR("error, ret = %d\n", ret); + ret = -EIO; + goto out; + } + } else if (spi_wr == NVTREAD) { //SPI read + while (retries < 20) { + ret = CTP_SPI_READ(ts->client, buf, + ((str[0] & 0x7F) << 8) | str[1]); + if (!ret) + break; + else + NVT_ERR("error, retries=%d, ret=%d\n", retries, + ret); + + retries++; + } + + memcpy(str + 2, buf, ((str[0] & 0x7F) << 8) | str[1]); + // copy buff to user if spi transfer + if (retries < 20) { + if (copy_to_user(buff, str, count)) { + ret = -EFAULT; + goto out; + } + } + + if (unlikely(retries == 20)) { + NVT_ERR("error, ret = %d\n", ret); + ret = -EIO; + goto out; + } + } else { + NVT_ERR("Call error, str[0]=%d\n", str[0]); + ret = -EFAULT; + goto out; + } + +out: + kfree(str); + kfree(buf); +kzalloc_failed: + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI open function. + +return: + Executive outcomes. 0---succeed. -12---failed. +*******************************************************/ +static int32_t nvt_flash_open(struct inode *inode, struct file *file) +{ + struct nvt_flash_data *dev; + + dev = kmalloc(sizeof(struct nvt_flash_data), GFP_KERNEL); + if (dev == NULL) { + NVT_ERR("Failed to allocate memory for nvt flash data\n"); + return -ENOMEM; + } + + rwlock_init(&dev->lock); + file->private_data = dev; + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI close function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_flash_close(struct inode *inode, struct file *file) +{ + struct nvt_flash_data *dev = file->private_data; + + if (dev) + kfree(dev); + + return 0; +} + +static const struct file_operations nvt_flash_fops = { + .owner = THIS_MODULE, + .open = nvt_flash_open, + .release = nvt_flash_close, + .read = nvt_flash_read, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI initial function. + +return: + Executive outcomes. 0---succeed. -12---failed. +*******************************************************/ +static int32_t nvt_flash_proc_init(void) +{ + NVT_proc_entry = proc_create(DEVICE_NAME, 0444, NULL, &nvt_flash_fops); + if (NVT_proc_entry == NULL) { + NVT_ERR("Failed!\n"); + return -ENOMEM; + } else { + NVT_LOG("Succeeded!\n"); + } + + NVT_LOG("============================================================\n"); + NVT_LOG("Create /proc/%s\n", DEVICE_NAME); + NVT_LOG("============================================================\n"); + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI deinitial function. + +return: + n.a. +*******************************************************/ +static void nvt_flash_proc_deinit(void) +{ + if (NVT_proc_entry != NULL) { + remove_proc_entry(DEVICE_NAME, NULL); + NVT_proc_entry = NULL; + NVT_LOG("Removed /proc/%s\n", DEVICE_NAME); + } +} +#endif + +#if WAKEUP_GESTURE +#define GESTURE_WORD_C 12 +#define GESTURE_WORD_W 13 +#define GESTURE_WORD_V 14 +#define GESTURE_DOUBLE_CLICK 15 +#define GESTURE_WORD_Z 16 +#define GESTURE_WORD_M 17 +#define GESTURE_WORD_O 18 +#define GESTURE_WORD_e 19 +#define GESTURE_WORD_S 20 +#define GESTURE_SLIDE_UP 21 +#define GESTURE_SLIDE_DOWN 22 +#define GESTURE_SLIDE_LEFT 23 +#define GESTURE_SLIDE_RIGHT 24 +#define GESTURE_PEN_ONE_CLICK 25 +/* customized gesture id */ +#define DATA_PROTOCOL 30 + +/* function page definition */ +#define FUNCPAGE_GESTURE 1 + +/******************************************************* +Description: + Novatek touchscreen wake up gesture key report function. + +return: + n.a. +*******************************************************/ +void nvt_ts_wakeup_gesture_report(uint8_t gesture_id, uint8_t *data) +{ + uint32_t keycode = 0; + uint8_t func_type = data[2]; + uint8_t func_id = data[3]; + + /* support fw specifal data protocol */ + if ((gesture_id == DATA_PROTOCOL) && (func_type == FUNCPAGE_GESTURE)) { + gesture_id = func_id; + } else if (gesture_id > DATA_PROTOCOL) { + NVT_ERR("gesture_id %d is invalid, func_type=%d, func_id=%d\n", + gesture_id, func_type, func_id); + return; + } + + NVT_LOG("gesture_id = %d\n", gesture_id); + + switch (gesture_id) { + case GESTURE_WORD_C: + NVT_LOG("Gesture : Word-C.\n"); + keycode = gesture_key_array[0]; + break; + case GESTURE_WORD_W: + NVT_LOG("Gesture : Word-W.\n"); + keycode = gesture_key_array[1]; + break; + case GESTURE_WORD_V: + NVT_LOG("Gesture : Word-V.\n"); + keycode = gesture_key_array[2]; + break; + case GESTURE_DOUBLE_CLICK: + NVT_LOG("Gesture : Double Click.\n"); + if (ts->db_wakeup & 0x01) { + keycode = gesture_key_array[3]; + } else { + NVT_LOG("Gesture : Double Click Not Enable.\n"); + keycode = 0; + } + break; + case GESTURE_WORD_Z: + NVT_LOG("Gesture : Word-Z.\n"); + keycode = gesture_key_array[4]; + break; + case GESTURE_WORD_M: + NVT_LOG("Gesture : Word-M.\n"); + keycode = gesture_key_array[5]; + break; + case GESTURE_WORD_O: + NVT_LOG("Gesture : Word-O.\n"); + keycode = gesture_key_array[6]; + break; + case GESTURE_WORD_e: + NVT_LOG("Gesture : Word-e.\n"); + keycode = gesture_key_array[7]; + break; + case GESTURE_WORD_S: + NVT_LOG("Gesture : Word-S.\n"); + keycode = gesture_key_array[8]; + break; + case GESTURE_SLIDE_UP: + NVT_LOG("Gesture : Slide UP.\n"); + keycode = gesture_key_array[9]; + break; + case GESTURE_SLIDE_DOWN: + NVT_LOG("Gesture : Slide DOWN.\n"); + keycode = gesture_key_array[10]; + break; + case GESTURE_SLIDE_LEFT: + NVT_LOG("Gesture : Slide LEFT.\n"); + keycode = gesture_key_array[11]; + break; + case GESTURE_SLIDE_RIGHT: + NVT_LOG("Gesture : Slide RIGHT.\n"); + keycode = gesture_key_array[12]; + break; + case GESTURE_PEN_ONE_CLICK: + NVT_LOG("Gesture : Pen Click.\n"); + if (ts->db_wakeup & 0x02) { + keycode = gesture_key_array[13]; + } else { + NVT_LOG("Gesture : Pen Click Not Enable.\n"); + keycode = 0; + } + break; + default: + break; + } + + if (keycode > 0) { + input_report_key(ts->input_dev, keycode, 1); + input_sync(ts->input_dev); + input_report_key(ts->input_dev, keycode, 0); + input_sync(ts->input_dev); + } +} +#endif + +static void release_pen_event() +{ + if (ts && ts->pen_input_dev) { + input_report_abs(ts->pen_input_dev, ABS_X, 0); + input_report_abs(ts->pen_input_dev, ABS_Y, 0); + input_report_abs(ts->pen_input_dev, ABS_PRESSURE, 0); + input_report_abs(ts->pen_input_dev, ABS_TILT_X, 0); + input_report_abs(ts->pen_input_dev, ABS_TILT_Y, 0); + input_report_abs(ts->pen_input_dev, ABS_DISTANCE, 0); + input_report_key(ts->pen_input_dev, BTN_TOUCH, 0); + input_report_key(ts->pen_input_dev, BTN_TOOL_PEN, 0); + input_report_key(ts->pen_input_dev, BTN_STYLUS, 0); + input_report_key(ts->pen_input_dev, BTN_STYLUS2, 0); + input_sync(ts->pen_input_dev); + } +} + +/******************************************************* +Description: + Novatek touchscreen parse device tree function. + +return: + n.a. +*******************************************************/ +#ifdef CONFIG_OF +static int32_t nvt_parse_dt(struct device *dev) +{ + struct nvt_config_info *config_info; + struct device_node *temp, *np = dev->of_node; + int32_t ret = 0; + uint32_t temp_val; + +#if NVT_TOUCH_SUPPORT_HW_RST + ts->reset_gpio = of_get_named_gpio_flags(np, "novatek,reset-gpio", 0, + &ts->reset_flags); + NVT_LOG("novatek,reset-gpio=%d\n", ts->reset_gpio); +#endif + ts->irq_gpio = of_get_named_gpio_flags(np, "novatek,irq-gpio", 0, + &ts->irq_flags); + NVT_LOG("novatek,irq-gpio=%d\n", ts->irq_gpio); + + ts->pen_support = of_property_read_bool(np, "novatek,pen-support"); + NVT_LOG("novatek,pen-support=%d\n", ts->pen_support); + + ts->wgp_stylus = of_property_read_bool(np, "novatek,wgp-stylus"); + NVT_LOG("novatek,wgp-stylus=%d\n", ts->wgp_stylus); + + ret = of_property_read_u32(np, "novatek,swrst-n8-addr", &SWRST_N8_ADDR); + if (ret) { + NVT_ERR("error reading novatek,swrst-n8-addr. ret=%d\n", ret); + return ret; + } else { + NVT_LOG("SWRST_N8_ADDR=0x%06X\n", SWRST_N8_ADDR); + } + + ret = of_property_read_u32(np, "novatek,spi-rd-fast-addr", + &SPI_RD_FAST_ADDR); + if (ret) { + NVT_LOG("not support novatek,spi-rd-fast-addr\n"); + SPI_RD_FAST_ADDR = 0; + ret = 0; + } else { + NVT_LOG("SPI_RD_FAST_ADDR=0x%06X\n", SPI_RD_FAST_ADDR); + } + + ret = of_property_read_u32(np, "novatek,config-array-size", + &ts->config_array_size); + if (ret) { + NVT_LOG("Unable to get array size\n"); + return ret; + } else { + NVT_LOG("config-array-size: %u\n", ts->config_array_size); + } + + ret = of_property_read_u32(np, "spi-max-frequency", &ts->spi_max_freq); + if (ret) { + NVT_LOG("Unable to get spi freq\n"); + return ret; + } else { + NVT_LOG("spi-max-frequency: %u\n", ts->spi_max_freq); + } + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + ret = of_property_read_u32_array(np, "novatek,touch-game-param-config1", + ts->gamemode_config[0], 5); + if (ret) { + NVT_LOG("Failed to get touch-game-param-config1\n"); + SPI_RD_FAST_ADDR = 0; + ret = 0; + } else { + NVT_LOG("read touch gamemode parameter config1:[%d, %d, %d, %d, %d]", + ts->gamemode_config[0][0], ts->gamemode_config[0][1], + ts->gamemode_config[0][2], ts->gamemode_config[0][3], + ts->gamemode_config[0][4]); + } + + ret = of_property_read_u32_array(np, "novatek,touch-game-param-config2", + ts->gamemode_config[1], 5); + if (ret) { + NVT_LOG("Failed to get touch-game-param-config2\n"); + SPI_RD_FAST_ADDR = 0; + ret = 0; + } else { + NVT_LOG("read touch gamemode parameter config2:[%d, %d, %d, %d, %d]", + ts->gamemode_config[1][0], ts->gamemode_config[1][1], + ts->gamemode_config[1][2], ts->gamemode_config[1][3], + ts->gamemode_config[1][4]); + } + + ret = of_property_read_u32_array(np, "novatek,touch-game-param-config3", + ts->gamemode_config[2], 5); + if (ret) { + NVT_LOG("Failed to get touch-game-param-config3\n"); + SPI_RD_FAST_ADDR = 0; + ret = 0; + } else { + NVT_LOG("read touch gamemode parameter config3:[%d, %d, %d, %d, %d]", + ts->gamemode_config[2][0], ts->gamemode_config[2][1], + ts->gamemode_config[2][2], ts->gamemode_config[2][3], + ts->gamemode_config[2][4]); + } +#endif /* #if CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE */ + ts->config_array = devm_kzalloc( + dev, ts->config_array_size * sizeof(struct nvt_config_info), + GFP_KERNEL); + if (!ts->config_array) { + NVT_LOG("Unable to allocate memory\n"); + return -ENOMEM; + } + + config_info = ts->config_array; + for_each_child_of_node(np, temp) { + if (config_info - ts->config_array >= ts->config_array_size) { + NVT_ERR("parse %ld config down\n", + config_info - ts->config_array); + break; + } + + ret = of_property_read_u32(temp, "novatek,display-maker", + &temp_val); + if (ret) { + NVT_LOG("Unable to read tp hw version\n"); + } else { + config_info->display_maker = (u8)temp_val; + NVT_LOG("tp hw version: %u", + config_info->display_maker); + } + + ret = of_property_read_string(temp, "novatek,fw-name", + &config_info->nvt_fw_name); + if (ret && (ret != -EINVAL)) { + NVT_LOG("Unable to read fw name\n"); + } else { + NVT_LOG("fw_name: %s", config_info->nvt_fw_name); + } + + ret = of_property_read_string(temp, "novatek,mp-name", + &config_info->nvt_mp_name); + if (ret && (ret != -EINVAL)) { + NVT_LOG("Unable to read mp name\n"); + } else { + NVT_LOG("mp_name: %s", config_info->nvt_mp_name); + } + + config_info++; + } + + return ret; +} +#else +static int32_t nvt_parse_dt(struct device *dev) +{ +#if NVT_TOUCH_SUPPORT_HW_RST + ts->reset_gpio = NVTTOUCH_RST_PIN; +#endif + ts->irq_gpio = NVTTOUCH_INT_PIN; + return 0; +} +#endif + +static int nvt_get_panel_type(struct nvt_ts_data *ts_data) +{ + int i; + int j; + u8 *lockdown = ts_data->lockdown_info; + struct nvt_config_info *panel_list = ts->config_array; + + for (j = 0; j < 60; j++) { + if (lockdown[1] == 0x42) { + i = 0; + NVT_ERR("This is CSOT Display Panel!"); + break; + } + if (lockdown[1] == 0x36) { + i = 1; + NVT_ERR("This is TM Display Panel!"); + break; + } + + mdelay(1000); + } + if (i != 0 && i != 1) { + i = 1; + } + + ts->panel_index = i; + + if (i >= ts->config_array_size) { + NVT_ERR("mismatch panel type, use default fw"); + ts->panel_index = -EINVAL; + return ts->panel_index; + } + + NVT_LOG("match panle type, fw is [%s], mp is [%s]", + panel_list[i].nvt_fw_name, panel_list[i].nvt_mp_name); + + return ts->panel_index; +} + +bool is_lockdown_empty(u8 *lockdown) +{ + bool ret = true; + int i; + + for (i = 0; i < NVT_LOCKDOWN_SIZE; i++) { + if (lockdown[i] != 0) { + ret = false; + break; + } + } + return ret; +} + +void nvt_match_fw(void) +{ + NVT_LOG("start match fw name"); + if (is_lockdown_empty(ts->lockdown_info)) + flush_delayed_work(&ts->nvt_lockdown_work); + if (nvt_get_panel_type(ts) < 0) { + ts->fw_name = DEFAULT_BOOT_UPDATE_FIRMWARE_NAME; + ts->mp_name = DEFAULT_MP_UPDATE_FIRMWARE_NAME; + } else { + ts->fw_name = ts->config_array[ts->panel_index].nvt_fw_name; + ts->mp_name = ts->config_array[ts->panel_index].nvt_mp_name; + } +} + +/******************************************************* +Description: + Novatek touchscreen config and request gpio + +return: + Executive outcomes. 0---succeed. not 0---failed. +*******************************************************/ +static int nvt_gpio_config(struct nvt_ts_data *ts) +{ + int32_t ret = 0; + +#if NVT_TOUCH_SUPPORT_HW_RST + /* request RST-pin (Output/High) */ + if (gpio_is_valid(ts->reset_gpio)) { + ret = gpio_request_one(ts->reset_gpio, GPIOF_OUT_INIT_LOW, + "NVT-tp-rst"); + if (ret) { + NVT_ERR("Failed to request NVT-tp-rst GPIO\n"); + goto err_request_reset_gpio; + } + } +#endif + + /* request INT-pin (Input) */ + if (gpio_is_valid(ts->irq_gpio)) { + ret = gpio_request_one(ts->irq_gpio, GPIOF_IN, "NVT-int"); + if (ret) { + NVT_ERR("Failed to request NVT-int GPIO\n"); + goto err_request_irq_gpio; + } + } + + return ret; + +err_request_irq_gpio: +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_free(ts->reset_gpio); +err_request_reset_gpio: +#endif + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen deconfig gpio + +return: + n.a. +*******************************************************/ +static void nvt_gpio_deconfig(struct nvt_ts_data *ts) +{ + if (gpio_is_valid(ts->irq_gpio)) + gpio_free(ts->irq_gpio); +#if NVT_TOUCH_SUPPORT_HW_RST + if (gpio_is_valid(ts->reset_gpio)) + gpio_free(ts->reset_gpio); +#endif +} + +static uint8_t nvt_fw_recovery(uint8_t *point_data) +{ + uint8_t i = 0; + uint8_t detected = true; + + /* check pattern */ + for (i = 1; i < 7; i++) { + if (point_data[i] != 0x77) { + detected = false; + break; + } + } + + return detected; +} + +void nvt_set_dbgfw_status(bool enable) +{ + ts->fw_debug = enable; +} + +bool nvt_get_dbgfw_status(void) +{ + return ts->fw_debug; +} + +#if NVT_TOUCH_ESD_PROTECT +void nvt_esd_check_enable(uint8_t enable) +{ + /* update interrupt timer */ + irq_timer = jiffies; + /* clear esd_retry counter, if protect function is enabled */ + esd_retry = enable ? 0 : esd_retry; + /* enable/disable esd check flag */ + esd_check = enable; +} + +static void nvt_esd_check_func(struct work_struct *work) +{ + unsigned int timer = jiffies_to_msecs(jiffies - irq_timer); + + //NVT_LOG("esd_check = %d (retry %d)\n", esd_check, esd_retry); //DEBUG + + if ((timer > NVT_TOUCH_ESD_CHECK_PERIOD) && esd_check) { + mutex_lock(&ts->lock); + NVT_ERR("do ESD recovery, timer = %d, retry = %d\n", timer, + esd_retry); + /* do esd recovery, reload fw */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + mutex_unlock(&ts->lock); + /* update interrupt timer */ + irq_timer = jiffies; + /* update esd_retry counter */ + esd_retry++; + } + + queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, + msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); +} +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#if NVT_TOUCH_WDT_RECOVERY +static uint8_t recovery_cnt = 0; +static uint8_t nvt_wdt_fw_recovery(uint8_t *point_data) +{ + uint32_t recovery_cnt_max = 10; + uint8_t recovery_enable = false; + uint8_t i = 0; + + recovery_cnt++; + + /* check pattern */ + for (i = 1; i < 7; i++) { + if ((point_data[i] != 0xFD) && (point_data[i] != 0xFE)) { + recovery_cnt = 0; + break; + } + } + + if (recovery_cnt > recovery_cnt_max) { + recovery_enable = true; + recovery_cnt = 0; + } + + return recovery_enable; +} +#endif /* #if NVT_TOUCH_WDT_RECOVERY */ + +#define PEN_DATA_LEN 14 +#if CHECK_PEN_DATA_CHECKSUM +static int32_t nvt_ts_pen_data_checksum(uint8_t *buf, uint8_t length) +{ + uint8_t checksum = 0; + int32_t i = 0; + + // Calculate checksum + for (i = 0; i < length - 1; i++) { + checksum += buf[i]; + } + checksum = (~checksum + 1); + + // Compare ckecksum and dump fail data + if (checksum != buf[length - 1]) { + NVT_ERR("pen packet checksum not match. (buf[%d]=0x%02X, checksum=0x%02X)\n", + length - 1, buf[length - 1], checksum); + //--- dump pen buf --- + for (i = 0; i < length; i++) { + printk("%02X ", buf[i]); + } + printk("\n"); + + return -1; + } + + return 0; +} +#endif // #if CHECK_PEN_DATA_CHECKSUM + +#define FW_HISTORY_SIZE 128 +static uint32_t nvt_dump_fw_history(void) +{ + int32_t ret = 0; + uint8_t buf[FW_HISTORY_SIZE + 1 + DUMMY_BYTES] = { 0 }; + int32_t i = 0; + char *tmp_dump = NULL; + int32_t line_cnt = 0; + + if (ts->mmap->FW_HISTORY_ADDR == 0) { + NVT_ERR("FW_HISTORY_ADDR not available!\n"); + ret = -1; + goto exit_nvt_dump_fw_history; + } + nvt_set_page(ts->mmap->FW_HISTORY_ADDR); + buf[0] = ts->mmap->FW_HISTORY_ADDR & 0xFF; + CTP_SPI_READ(ts->client, buf, FW_HISTORY_SIZE + 1); + if (ret) { + NVT_ERR("CTP_SPI_READ failed.(%d)\n", ret); + ret = -1; + goto exit_nvt_dump_fw_history; + } + + tmp_dump = (char *)kzalloc(FW_HISTORY_SIZE * 4, GFP_KERNEL); + for (i = 0; i < FW_HISTORY_SIZE; i++) { + sprintf(tmp_dump + i * 3 + line_cnt, "%02X ", buf[1 + i]); + if ((i + 1) % 16 == 0) { + sprintf(tmp_dump + i * 3 + line_cnt + 3, "%c", '\n'); + line_cnt++; + } + } + NVT_LOG("%s", tmp_dump); + +exit_nvt_dump_fw_history: + if (tmp_dump) { + kfree(tmp_dump); + tmp_dump = NULL; + } + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); + + return ret; +} + +#if POINT_DATA_CHECKSUM +static int32_t nvt_ts_point_data_checksum(uint8_t *buf, uint8_t length) +{ + uint8_t checksum = 0; + int32_t i = 0; + + // Generate checksum + for (i = 0; i < length - 1; i++) { + checksum += buf[i + 1]; + } + checksum = (~checksum + 1); + + // Compare ckecksum and dump fail data + if (checksum != buf[length]) { + NVT_ERR("i2c/spi packet checksum not match. (point_data[%d]=0x%02X, checksum=0x%02X)\n", + length, buf[length], checksum); + + for (i = 0; i < 10; i++) { + NVT_LOG("%02X %02X %02X %02X %02X %02X\n", + buf[1 + i * 6], buf[2 + i * 6], buf[3 + i * 6], + buf[4 + i * 6], buf[5 + i * 6], buf[6 + i * 6]); + } + + NVT_LOG("%02X %02X %02X %02X %02X\n", buf[61], buf[62], buf[63], + buf[64], buf[65]); + + return -1; + } + + return 0; +} +#endif /* POINT_DATA_CHECKSUM */ + +#define POINT_DATA_LEN 65 +/******************************************************* +Description: + Novatek touchscreen work function. + +return: + n.a. +*******************************************************/ +static irqreturn_t nvt_ts_work_func(int irq, void *data) +{ + int32_t ret = -1; + uint8_t point_data[POINT_DATA_LEN + PEN_DATA_LEN + 1 + DUMMY_BYTES] = { + 0 + }; + uint32_t position = 0; + uint32_t input_x = 0; + uint32_t input_y = 0; + uint32_t input_w = 0; + uint32_t input_p = 0; + uint8_t input_id = 0; +#if MT_PROTOCOL_B + uint8_t press_id[TOUCH_MAX_FINGER_NUM] = { 0 }; +#endif /* MT_PROTOCOL_B */ + int32_t i = 0; + int32_t finger_cnt = 0; + uint8_t pen_format_id = 0; + uint32_t pen_x = 0; + uint32_t pen_y = 0; + uint32_t pen_pressure = 0; + uint32_t pen_distance = 0; + int8_t pen_tilt_x = 0; + int8_t pen_tilt_y = 0; + uint32_t pen_btn1 = 0; + uint32_t pen_btn2 = 0; + uint32_t pen_battery = 0; + +#if WAKEUP_GESTURE + if (bTouchIsAwake == 0) { + pm_wakeup_event(&ts->input_dev->dev, 5000); + } +#endif + + touch_irq_boost(); + lpm_disable_for_input(true); + + mutex_lock(&ts->lock); + + if (ts->dev_pm_suspend) { + ret = wait_for_completion_timeout( + &ts->dev_pm_suspend_completion, msecs_to_jiffies(500)); + if (!ret) { + NVT_ERR("system(spi) can't finished resuming procedure, skip it\n"); + lpm_disable_for_input(false); + goto XFER_ERROR; + } + } + + if (ts->pen_support) + ret = CTP_SPI_READ(ts->client, point_data, + POINT_DATA_LEN + PEN_DATA_LEN + 1); + else + ret = CTP_SPI_READ(ts->client, point_data, POINT_DATA_LEN + 1); + if (ret < 0) { + NVT_ERR("CTP_SPI_READ failed.(%d)\n", ret); + goto XFER_ERROR; + } + + /*--- dump SPI buf --- + for (i = 0; i < 10; i++) { + NVT_LOG("%02X %02X %02X %02X %02X %02X \n", + point_data[1+i*6], point_data[2+i*6], point_data[3+i*6], point_data[4+i*6], point_data[5+i*6], point_data[6+i*6]); + } + */ + +#if NVT_TOUCH_WDT_RECOVERY + /* ESD protect by WDT */ + if (nvt_wdt_fw_recovery(point_data)) { + NVT_ERR("Recover for fw reset, %02X\n", point_data[1]); + if (point_data[1] == 0xFD) { + NVT_ERR("Dump FW history:\n"); + nvt_dump_fw_history(); + } + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + goto XFER_ERROR; + } +#endif /* #if NVT_TOUCH_WDT_RECOVERY */ + + /* ESD protect by FW handshake */ + if (nvt_fw_recovery(point_data)) { +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(true); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + goto XFER_ERROR; + } + +#if POINT_DATA_CHECKSUM + if (POINT_DATA_LEN >= POINT_DATA_CHECKSUM_LEN) { + ret = nvt_ts_point_data_checksum(point_data, + POINT_DATA_CHECKSUM_LEN); + if (ret) { + goto XFER_ERROR; + } + } +#endif /* POINT_DATA_CHECKSUM */ + +#if WAKEUP_GESTURE + if (bTouchIsAwake == 0) { + NVT_LOG("Enter WAKEUP_GESTURE\n"); + input_id = (uint8_t)(point_data[1] >> 3); + nvt_ts_wakeup_gesture_report(input_id, point_data); + mutex_unlock(&ts->lock); + lpm_disable_for_input(false); + return IRQ_HANDLED; + } +#endif + + finger_cnt = 0; + + for (i = 0; i < ts->max_touch_num; i++) { + position = 1 + 6 * i; + input_id = (uint8_t)(point_data[position + 0] >> 3); + if ((input_id == 0) || (input_id > ts->max_touch_num)) + continue; + + if (((point_data[position] & 0x07) == 0x01) || + ((point_data[position] & 0x07) == + 0x02)) { //finger down (enter & moving) +#if NVT_TOUCH_ESD_PROTECT + /* update interrupt timer */ + irq_timer = jiffies; +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + input_x = (uint32_t)(point_data[position + 1] << 4) + + (uint32_t)(point_data[position + 3] >> 4); + input_y = (uint32_t)(point_data[position + 2] << 4) + + (uint32_t)(point_data[position + 3] & 0x0F); + if ((input_x < 0) || (input_y < 0)) + continue; + if ((input_x > ts->abs_x_max) || + (input_y > ts->abs_y_max)) + continue; + input_w = (uint32_t)(point_data[position + 4]); + if (input_w == 0) + input_w = 1; + if (i < 2) { + input_p = (uint32_t)(point_data[position + 5]) + + (uint32_t)(point_data[i + 63] << 8); + if (input_p > TOUCH_FORCE_NUM) + input_p = TOUCH_FORCE_NUM; + } else { + input_p = (uint32_t)(point_data[position + 5]); + } + if (input_p == 0) + input_p = 1; + +#if MT_PROTOCOL_B + press_id[input_id - 1] = 1; + input_mt_slot(ts->input_dev, input_id - 1); + input_mt_report_slot_state(ts->input_dev, + MT_TOOL_FINGER, true); +#else /* MT_PROTOCOL_B */ + input_report_abs(ts->input_dev, ABS_MT_TRACKING_ID, + input_id - 1); + input_report_key(ts->input_dev, BTN_TOUCH, 1); +#endif /* MT_PROTOCOL_B */ + + input_report_abs(ts->input_dev, ABS_MT_POSITION_X, + input_x); + input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, + input_y); + input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, + input_w); + input_report_abs(ts->input_dev, ABS_MT_PRESSURE, + input_p); + +#if MT_PROTOCOL_B +#else /* MT_PROTOCOL_B */ + input_mt_sync(ts->input_dev); +#endif /* MT_PROTOCOL_B */ + + finger_cnt++; + } + } + +#if MT_PROTOCOL_B + for (i = 0; i < ts->max_touch_num; i++) { + if (press_id[i] != 1) { + input_mt_slot(ts->input_dev, i); + input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0); + input_report_abs(ts->input_dev, ABS_MT_PRESSURE, 0); + input_mt_report_slot_state(ts->input_dev, + MT_TOOL_FINGER, false); + } + } + input_report_key(ts->input_dev, BTN_TOUCH, (finger_cnt > 0)); +#else /* MT_PROTOCOL_B */ + if (finger_cnt == 0) { + input_report_key(ts->input_dev, BTN_TOUCH, 0); + input_mt_sync(ts->input_dev); + } +#endif /* MT_PROTOCOL_B */ + +#if TOUCH_KEY_NUM > 0 + if (point_data[61] == 0xF8) { +#if NVT_TOUCH_ESD_PROTECT + /* update interrupt timer */ + irq_timer = jiffies; +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + for (i = 0; i < ts->max_button_num; i++) { + input_report_key(ts->input_dev, touch_key_array[i], + ((point_data[62] >> i) & 0x01)); + } + } else { + for (i = 0; i < ts->max_button_num; i++) { + input_report_key(ts->input_dev, touch_key_array[i], 0); + } + } +#endif + + input_sync(ts->input_dev); + + if (ts->pen_support && ts->pen_input_dev_enable && + !(ts->pen_is_charge)) { +/* + //--- dump pen buf --- + printk("%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", + point_data[66], point_data[67], point_data[68], point_data[69], point_data[70], + point_data[71], point_data[72], point_data[73], point_data[74], point_data[75], + point_data[76], point_data[77], point_data[78], point_data[79]); +*/ +#if CHECK_PEN_DATA_CHECKSUM + if (nvt_ts_pen_data_checksum(&point_data[66], PEN_DATA_LEN)) { + // pen data packet checksum not match, skip it + goto XFER_ERROR; + } +#endif // #if CHECK_PEN_DATA_CHECKSUM + + // parse and handle pen report + pen_format_id = point_data[66]; + if (pen_format_id != 0xFF) { + if (pen_format_id == 0x01) { + // report pen data + pen_x = (uint32_t)(point_data[67] << 8) + + (uint32_t)(point_data[68]); + pen_y = (uint32_t)(point_data[69] << 8) + + (uint32_t)(point_data[70]); + if (pen_x >= ts->abs_x_max * 2 - 1) { + pen_x -= 1; + } + if (pen_y >= ts->abs_y_max * 2 - 1) { + pen_y -= 1; + } + pen_pressure = (uint32_t)(point_data[71] << 8) + + (uint32_t)(point_data[72]); + pen_tilt_x = (int32_t)point_data[73]; + pen_tilt_y = (int32_t)point_data[74]; + pen_distance = (uint32_t)(point_data[75] << 8) + + (uint32_t)(point_data[76]); + pen_btn1 = (uint32_t)(point_data[77] & 0x01); + pen_btn2 = (uint32_t)((point_data[77] >> 1) & + 0x01); + pen_battery = (uint32_t)point_data[78]; + // printk("x=%d,y=%d,p=%d,tx=%d,ty=%d,d=%d,b1=%d,b2=%d,bat=%d\n", pen_x, pen_y, pen_pressure, + // pen_tilt_x, pen_tilt_y, pen_distance, pen_btn1, pen_btn2, pen_battery); + + input_report_abs(ts->pen_input_dev, ABS_X, + pen_x); + input_report_abs(ts->pen_input_dev, ABS_Y, + pen_y); + input_report_abs(ts->pen_input_dev, + ABS_PRESSURE, pen_pressure); + input_report_key(ts->pen_input_dev, BTN_TOUCH, + !!pen_pressure); + input_report_abs(ts->pen_input_dev, ABS_TILT_X, + pen_tilt_x); + input_report_abs(ts->pen_input_dev, ABS_TILT_Y, + pen_tilt_y); + input_report_abs(ts->pen_input_dev, + ABS_DISTANCE, pen_distance); + input_report_key( + ts->pen_input_dev, BTN_TOOL_PEN, + !!pen_distance || !!pen_pressure); + input_report_key(ts->pen_input_dev, BTN_STYLUS, + pen_btn1); + input_report_key(ts->pen_input_dev, BTN_STYLUS2, + pen_btn2); + input_sync(ts->pen_input_dev); + // TBD: pen battery event report + // NVT_LOG("pen_battery=%d\n", pen_battery); + } else if (pen_format_id == 0xF0) { + // report Pen ID + } else { + NVT_ERR("Unknown pen format id!\n"); + goto XFER_ERROR; + } + } else { // pen_format_id = 0xFF, i.e. no pen present + release_pen_event(); + } + } /* if (ts->pen_support) */ + +XFER_ERROR: + + mutex_unlock(&ts->lock); + lpm_disable_for_input(false); + return IRQ_HANDLED; +} + +/******************************************************* +Description: + Novatek touchscreen check chip version trim function. + +return: + Executive outcomes. 0---NVT IC. -1---not NVT IC. +*******************************************************/ +static int8_t nvt_ts_check_chip_ver_trim(uint32_t chip_ver_trim_addr) +{ + uint8_t buf[8] = { 0 }; + int32_t retry = 0; + int32_t list = 0; + int32_t i = 0; + int32_t found_nvt_chip = 0; + int32_t ret = -1; + + //---Check for 5 times--- + for (retry = 5; retry > 0; retry--) { + nvt_bootloader_reset(); + + nvt_set_page(chip_ver_trim_addr); + + buf[0] = chip_ver_trim_addr & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + buf[5] = 0x00; + buf[6] = 0x00; + CTP_SPI_READ(ts->client, buf, 7); + NVT_LOG("buf[1]=0x%02X, buf[2]=0x%02X, buf[3]=0x%02X, buf[4]=0x%02X, buf[5]=0x%02X, buf[6]=0x%02X\n", + buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); + + // compare read chip id on supported list + for (list = 0; list < (sizeof(trim_id_table) / + sizeof(struct nvt_ts_trim_id_table)); + list++) { + found_nvt_chip = 0; + + // compare each byte + for (i = 0; i < NVT_ID_BYTE_MAX; i++) { + if (trim_id_table[list].mask[i]) { + if (buf[i + 1] != + trim_id_table[list].id[i]) + break; + } + } + + if (i == NVT_ID_BYTE_MAX) { + found_nvt_chip = 1; + } + + if (found_nvt_chip) { + NVT_LOG("This is NVT touch IC\n"); + ts->mmap = trim_id_table[list].mmap; + ts->carrier_system = + trim_id_table[list] + .hwinfo->carrier_system; + ts->hw_crc = trim_id_table[list].hwinfo->hw_crc; + ret = 0; + goto out; + } else { + ts->mmap = NULL; + ret = -1; + } + } + + msleep(10); + } + +out: + return ret; +} + +static void nvt_switch_mode_work(struct work_struct *work) +{ + NVT_LOG("%s double click wakeup", ts->db_wakeup ? "ENABLE" : "DISABLE"); + if (ts->ic_state <= NVT_IC_SUSPEND_OUT && ts->ic_state != NVT_IC_INIT) { + ts->gesture_command_delayed = ts->db_wakeup; + NVT_ERR("Panel off, don't set dbclick gesture flag util panel on"); + ts->db_wakeup = 0; + } else if (ts->ic_state >= NVT_IC_RESUME_IN) { + dsi_panel_doubleclick_enable(!!ts->db_wakeup); + } +} + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +static struct xiaomi_touch_interface xiaomi_touch_interfaces; + +int32_t nvt_check_palm(uint8_t input_id, uint8_t *data) +{ + int32_t ret = 0; + uint8_t func_type = data[2]; + uint8_t palm_state = data[3]; + + if ((input_id == DATA_PROTOCOL) && (func_type == FUNCPAGE_PALM)) { + ret = palm_state; + if (palm_state == PACKET_PALM_ON) { + NVT_LOG("get packet palm on event.\n"); + update_palm_sensor_value(1); + } else if (palm_state == PACKET_PALM_OFF) { + NVT_LOG("get packet palm off event.\n"); + update_palm_sensor_value(0); + } else { + NVT_ERR("invalid palm state %d!\n", palm_state); + ret = -1; + } + } else { + ret = 0; + } + + return ret; +} + +static int nvt_palm_sensor_write(int value) +{ + int ret = 0; + NVT_LOG("enter %d %d\n", value, ts->palm_sensor_switch); + ts->palm_sensor_switch = value; + + if (ts->dev_pm_suspend) { + NVT_LOG("tp has dev_pm_suspend status\n"); + return 0; + } + + if (bTouchIsAwake) + ret = nvt_set_pocket_palm_switch(value); + return ret; +} + +static void nvt_init_touchmode_data(void) +{ + int i; + + NVT_LOG("%s,ENTER\n", __func__); + /* Touch Game Mode Switch */ + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MAX_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_CUR_VALUE] = 0; + + /* Acitve Mode */ + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MAX_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_DEF_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_CUR_VALUE] = + 0; + + /* Tap Sensivity */ + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MAX_VALUE] = + 4; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_DEF_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_CUR_VALUE] = + 0; + + /* Touch Tolerance */ + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MAX_VALUE] = 4; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_CUR_VALUE] = 0; + + /* Touch Aim Sensitivity */ + xiaomi_touch_interfaces + .touch_mode[Touch_Aim_Sensitivity][GET_MAX_VALUE] = 4; + xiaomi_touch_interfaces + .touch_mode[Touch_Aim_Sensitivity][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Aim_Sensitivity][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Aim_Sensitivity][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Aim_Sensitivity][GET_CUR_VALUE] = 0; + + /* [Touch Tap Stability */ + xiaomi_touch_interfaces.touch_mode[Touch_Tap_Stability][GET_MAX_VALUE] = + 4; + xiaomi_touch_interfaces.touch_mode[Touch_Tap_Stability][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tap_Stability][GET_DEF_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tap_Stability][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tap_Stability][GET_CUR_VALUE] = + 0; + + xiaomi_touch_interfaces.touch_mode[Touch_Expert_Mode][GET_MAX_VALUE] = + 3; + xiaomi_touch_interfaces.touch_mode[Touch_Expert_Mode][GET_MIN_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Expert_Mode][GET_DEF_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Expert_Mode][SET_CUR_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Expert_Mode][GET_CUR_VALUE] = + 1; + + /* Panel orientation*/ + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MAX_VALUE] = 3; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = 0; + + /* Edge filter area*/ + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MAX_VALUE] = + 3; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_DEF_VALUE] = + 2; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = + 0; + + /* Resist RF interference*/ + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_MAX_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_CUR_VALUE] = 0; + + for (i = 0; i < Touch_Mode_NUM; i++) { + NVT_LOG("mode:%d, set cur:%d, get cur:%d, def:%d min:%d max:%d\n", + i, xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MIN_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MAX_VALUE]); + } + + return; +} + +static int nvt_touchfeature_cmd_xsfer(uint8_t *touchfeature) +{ + int ret; + uint8_t buf[8] = { 0 }; + + NVT_LOG("++\n"); + NVT_LOG("cmd xsfer:%02x, %02x", touchfeature[0], touchfeature[1]); + /* ---set xdata index to EVENT BUF ADDR--- */ + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_touchfeature_cmd_xsfer_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = touchfeature[0]; + buf[2] = touchfeature[1]; + + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write sensitivity switch command fail!\n"); + goto nvt_touchfeature_cmd_xsfer_out; + } + +nvt_touchfeature_cmd_xsfer_out: + NVT_LOG("--\n"); + return ret; +} + +static int nvt_touchfeature_set(uint8_t *touchfeature) +{ + int ret; + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + ret = nvt_touchfeature_cmd_xsfer(touchfeature); + if (ret < 0) + NVT_ERR("send cmd via SPI failed, errno:%d", ret); + + mutex_unlock(&ts->lock); + msleep(35); + return ret; +} + +#define PANEL_ORIENTATION_DEGREE_0 0 /* normal portrait orientation */ +#define PANEL_ORIENTATION_DEGREE_90 1 /* anticlockwise 90 degrees */ +#define PANEL_ORIENTATION_DEGREE_180 2 /* anticlockwise 180 degrees */ +#define PANEL_ORIENTATION_DEGREE_270 3 /* anticlockwise 270 degrees */ + +static void update_touchfeature_value_work(struct work_struct *work) +{ + uint8_t ret = 0; + uint8_t i = 0; + uint8_t nvt_game_value[2] = { 0 }; + int size = 6; + enum MODE_TYPE mode_type[6] = { + Touch_Game_Mode, Touch_UP_THRESHOLD, Touch_Tolerance, + Touch_Tap_Stability, Touch_Aim_Sensitivity, Touch_Edge_Filter + }; + uint8_t touchfeature_addr[6] = { 0x7A, 0x71, 0x78, 0x70, 0x79, 0x72 }; + uint8_t temp_set_value; + uint8_t temp_get_value; + + NVT_LOG("enter"); + for (i = 0; i < size; i++) { + temp_get_value = + xiaomi_touch_interfaces + .touch_mode[mode_type[i]][GET_CUR_VALUE]; + temp_set_value = + xiaomi_touch_interfaces + .touch_mode[mode_type[i]][SET_CUR_VALUE]; + if (temp_get_value == temp_set_value) + continue; + nvt_game_value[0] = touchfeature_addr[i]; + nvt_game_value[1] = temp_set_value; + ret = nvt_touchfeature_set(nvt_game_value); + msleep(40); + if (ret < 0) { + NVT_ERR("change game mode fail, mode is %d", + mode_type[i]); + return; + } + xiaomi_touch_interfaces.touch_mode[mode_type[i]][GET_CUR_VALUE] = + temp_set_value; + NVT_LOG("set mode:%d = %d", mode_type[i], temp_set_value); + } + /* orientation set */ + temp_get_value = + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE]; + temp_set_value = + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE]; + if (temp_get_value != temp_set_value) { + if (temp_set_value == PANEL_ORIENTATION_DEGREE_0 || + temp_set_value == PANEL_ORIENTATION_DEGREE_180) { + nvt_game_value[0] = 0xBA; + } else if (temp_set_value == PANEL_ORIENTATION_DEGREE_90) { + nvt_game_value[0] = 0xBC; + } else if (temp_set_value == PANEL_ORIENTATION_DEGREE_270) { + nvt_game_value[0] = 0xBB; + } + nvt_game_value[1] = 0; + ret = nvt_touchfeature_set(nvt_game_value); + if (ret < 0) { + NVT_ERR("change panel orientation mode fail"); + return; + } + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = + temp_set_value; + NVT_LOG("set mode:%d = %d", Touch_Panel_Orientation, + temp_set_value); + } + + /* RF set */ + temp_get_value = xiaomi_touch_interfaces + .touch_mode[Touch_Resist_RF][GET_CUR_VALUE]; + temp_set_value = xiaomi_touch_interfaces + .touch_mode[Touch_Resist_RF][SET_CUR_VALUE]; + if (temp_get_value != temp_set_value) { + if (temp_set_value == 0) { + nvt_game_value[0] = 0x76; + } else if (temp_set_value == 1) { + nvt_game_value[0] = 0x75; + } + nvt_game_value[1] = 0; + ret = nvt_touchfeature_set(nvt_game_value); + if (ret < 0) { + NVT_ERR("change panel RF mode fail"); + return; + } + xiaomi_touch_interfaces + .touch_mode[Touch_Resist_RF][GET_CUR_VALUE] = + temp_set_value; + NVT_LOG("set mode:%d = %d", Touch_Resist_RF, temp_set_value); + } + NVT_LOG("exit"); +} + +static int disable_pen_input_device(bool disable) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + if (!bTouchIsAwake || !ts) { + NVT_LOG("touch suspend, stop set pen state %s", + disable ? "DISABLE" : "ENABLE"); + goto nvt_set_pen_enable_out; + } + + msleep(35); + disable = (!(ts->pen_input_dev_enable) || ts->pen_is_charge) ? true : + disable; + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_pen_enable_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x7B; + buf[2] = !!disable; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("set pen %s failed!\n", disable ? "DISABLE" : "ENABLE"); + goto nvt_set_pen_enable_out; + } + NVT_LOG("pen charge state is %s, %s pen input device\n", + ts->pen_is_charge ? "ENABLE" : "DISABLE", + disable ? "DISABLE" : "ENABLE"); + +nvt_set_pen_enable_out: + NVT_LOG("--\n"); + return ret; +} + +static int nvt_pen_charge_state_notifier_callback(struct notifier_block *self, + unsigned long event, + void *data) +{ + ts->pen_is_charge = !!event; + release_pen_event(); + schedule_work(&ts->pen_charge_state_change_work); + return 0; +} + +static void nvt_pen_charge_state_change_work(struct work_struct *work) +{ + NVT_LOG("pen charge is %s", ts->pen_is_charge ? "ENABLE" : "DISABLE"); + disable_pen_input_device(ts->pen_is_charge); +} + +static int nvt_set_cur_value(int nvt_mode, int nvt_value) +{ + if (nvt_mode >= Touch_Mode_NUM && nvt_mode < 0) { + NVT_ERR("%s, nvt mode is error:%d", __func__, nvt_mode); + return -EINVAL; + } + + NVT_LOG("mode:%d, value:%d", nvt_mode, nvt_value); + if (nvt_mode == Touch_Doubletap_Mode && ts && nvt_value >= 0) { + ts->db_wakeup = nvt_value ? (ts->db_wakeup | 0x01) : + (ts->db_wakeup & 0xFE); + ts->db_wakeup = nvt_value ? (ts->db_wakeup | 0x02) : + (ts->db_wakeup & + 0xFD); /* enable pen wake up */ + schedule_work(&ts->switch_mode_work); + return 0; + } else if (nvt_mode == Touch_Pen_ENABLE && ts && nvt_value >= 0) { + ts->pen_input_dev_enable = !!nvt_value; + NVT_LOG("%s pen input dev", + ts->pen_input_dev_enable ? "ENABLE" : "DISABLE"); + disable_pen_input_device(!ts->pen_input_dev_enable); + release_pen_event(); + return 0; + } + + if (nvt_value > + xiaomi_touch_interfaces.touch_mode[nvt_mode][GET_MAX_VALUE]) { + nvt_value = xiaomi_touch_interfaces + .touch_mode[nvt_mode][GET_MAX_VALUE]; + } else if (nvt_value < + xiaomi_touch_interfaces.touch_mode[nvt_mode][GET_MIN_VALUE]) { + nvt_value = xiaomi_touch_interfaces + .touch_mode[nvt_mode][GET_MIN_VALUE]; + } + xiaomi_touch_interfaces.touch_mode[nvt_mode][SET_CUR_VALUE] = nvt_value; + + if (nvt_mode == Touch_Expert_Mode) { + NVT_LOG("This is Expert Mode, mode is %d", nvt_value); + xiaomi_touch_interfaces + .touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE] = + ts->gamemode_config[nvt_value - 1][0]; + xiaomi_touch_interfaces + .touch_mode[Touch_Tolerance][SET_CUR_VALUE] = + ts->gamemode_config[nvt_value - 1][1]; + xiaomi_touch_interfaces + .touch_mode[Touch_Aim_Sensitivity][SET_CUR_VALUE] = + ts->gamemode_config[nvt_value - 1][2]; + xiaomi_touch_interfaces + .touch_mode[Touch_Tap_Stability][SET_CUR_VALUE] = + ts->gamemode_config[nvt_value - 1][3]; + xiaomi_touch_interfaces + .touch_mode[Touch_Edge_Filter][SET_CUR_VALUE] = + ts->gamemode_config[nvt_value - 1][4]; + } + + if (bTouchIsAwake) { + queue_work(ts->set_touchfeature_wq, &ts->set_touchfeature_work); + } + + return 0; +} + +static char nvt_touch_vendor_read(void) +{ + char value = '4'; + NVT_LOG("%s Get touch vendor: %c\n", __func__, value); + return value; +} + +static u8 nvt_panel_vendor_read(void) +{ + char value = '0'; + int ret = 0; + if (!ts) + return value; + ret = dsi_panel_lockdown_info_read(ts->lockdown_info); + if (ret <= 0) { + NVT_ERR("can't get lockdown info"); + return value; + } + if (!ts->lockdown_info[6]) { + NVT_ERR("%s lockdown info is NULL\n", __func__); + return value; + } else { + value = ts->lockdown_info[1]; + NVT_LOG("%s Get touch vendor: %d\n", __func__, value); + } + return value; +} + +static u8 nvt_panel_color_read(void) +{ + char value = '2'; + + return value; +} + +static u8 nvt_panel_display_read(void) +{ + char value = '0'; + int ret = 0; + if (!ts) + return value; + ret = dsi_panel_lockdown_info_read(ts->lockdown_info); + if (ret <= 0) { + NVT_ERR("can't get lockdown info"); + return value; + } + if (!ts->lockdown_info[1]) { + NVT_ERR("%s lockdown info is NULL\n", __func__); + return value; + } else { + value = ts->lockdown_info[1]; + NVT_LOG("%s Get touch vendor: %d\n", __func__, value); + } + return value; +} + +static int nvt_get_mode_value(int mode, int value_type) +{ + int value = -1; + + if (mode < Touch_Mode_NUM && mode >= 0) + value = xiaomi_touch_interfaces.touch_mode[mode][value_type]; + else + NVT_ERR("%s, don't support\n", __func__); + + return value; +} + +static int nvt_get_mode_all(int mode, int *value) +{ + if (mode < Touch_Mode_NUM && mode >= 0) { + value[0] = + xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE]; + value[1] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + value[2] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; + value[3] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; + } else { + NVT_ERR("%s, don't support\n", __func__); + } + NVT_LOG("%s, mode:%d, value:%d:%d:%d:%d\n", __func__, mode, value[0], + value[1], value[2], value[3]); + + return 0; +} + +static void nvt_game_mode_recovery(void) +{ + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE]; + + queue_work(ts->set_touchfeature_wq, &ts->set_touchfeature_work); +} + +static int nvt_reset_mode(int mode) +{ + int i = 0; + + NVT_LOG("nvt_reset_mode enter\n"); + + if (mode < Touch_Report_Rate && mode > 0) { + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + nvt_set_cur_value( + mode, + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE]); + } else if (mode == 0) { + for (i = 0; i <= Touch_Report_Rate; i++) { + if (i == Touch_Panel_Orientation) { + xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[i][GET_CUR_VALUE]; + } else { + xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[i][GET_DEF_VALUE]; + } + if (i == Touch_Expert_Mode) { + continue; + } + nvt_set_cur_value( + i, xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE]); + } + } else { + NVT_ERR("%s, don't support\n", __func__); + } + + NVT_LOG("%s, mode:%d\n", __func__, mode); + + return 0; +} +#endif + +#ifdef CONFIG_TOUCHSCREEN_NVT_DEBUG_FS +static void tpdbg_suspend(struct nvt_ts_data *ts_core, bool enable) +{ + if (enable) + nvt_ts_suspend(&ts_core->client->dev); + else + nvt_ts_resume(&ts_core->client->dev); +} + +static int tpdbg_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + + return 0; +} + +static ssize_t tpdbg_read(struct file *file, char __user *buf, size_t size, + loff_t *ppos) +{ + const char *str = "cmd support as below:\n \ + echo \"irq-disable\" or \"irq-enable\" to ctrl irq\n \ + echo \"tp-sd-en\" or \"tp-sd-off\" to ctrl panel on or off sensor\n \ + echo \"tp-suspend-en\" or \"tp-suspend-off\" to ctrl panel in or off suspend status\n \ + echo \"fw-debug-on\" or \"fw-debug-off\" to on or off fw debug function\n"; + + loff_t pos = *ppos; + int len = strlen(str); + + if (pos < 0) + return -EINVAL; + if (pos >= len) + return 0; + + if (copy_to_user(buf, str, len)) + return -EFAULT; + + *ppos = pos + len; + + return len; +} + +static ssize_t tpdbg_write(struct file *file, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct nvt_ts_data *ts_core = file->private_data; + char *cmd = kzalloc(size + 1, GFP_KERNEL); + int ret = size; + + if (!cmd) + return -ENOMEM; + + if (copy_from_user(cmd, buf, size)) { + ret = -EFAULT; + goto out; + } + +#if NVT_TOUCH_ESD_PROTECT + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + cmd[size] = '\0'; + + if (!strncmp(cmd, "irq-disable", 11)) + nvt_irq_enable(false); + else if (!strncmp(cmd, "irq-enable", 10)) + nvt_irq_enable(true); + else if (!strncmp(cmd, "tp-sd-en", 8)) + tpdbg_suspend(ts_core, true); + else if (!strncmp(cmd, "tp-sd-off", 9)) + tpdbg_suspend(ts_core, false); + else if (!strncmp(cmd, "tp-suspend-en", 13)) + tpdbg_suspend(ts_core, true); + else if (!strncmp(cmd, "tp-suspend-off", 14)) + tpdbg_suspend(ts_core, false); + else if (!strncmp(cmd, "fw-debug-on", 11)) + nvt_set_dbgfw_status(true); + else if (!strncmp(cmd, "fw-debug-off", 12)) + nvt_set_dbgfw_status(false); +out: + kfree(cmd); + + return ret; +} + +static int tpdbg_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + + return 0; +} + +static ssize_t nvt_touch_test_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + int retval = -1; + uint8_t cmd[8]; + if (copy_from_user(cmd, buf, count)) { + retval = -EFAULT; + goto out; + } + switch (cmd[0]) { + case '0': + ts->debug_flag = 0; + break; + case '1': + ts->debug_flag = 1; + break; + case '2': + ts->debug_flag = 2; + break; + default: + NVT_LOG("%s invalid input cmd, set default value\n", __func__); + ts->debug_flag = 2; + } + NVT_LOG("%s set touch boost debug flag to %d\n", __func__, + ts->debug_flag); + retval = count; +out: + return retval; +} + +static const struct file_operations nvt_touch_test_fops = { + .owner = THIS_MODULE, + .write = nvt_touch_test_write, +}; + +static const struct file_operations tpdbg_ops = { + .owner = THIS_MODULE, + .open = tpdbg_open, + .read = tpdbg_read, + .write = tpdbg_write, + .release = tpdbg_release, +}; +#endif + +static void nvt_suspend_work(struct work_struct *work) +{ + struct nvt_ts_data *ts_core = + container_of(work, struct nvt_ts_data, suspend_work); + nvt_ts_suspend(&ts_core->client->dev); +} + +static void nvt_resume_work(struct work_struct *work) +{ + struct nvt_ts_data *ts_core = + container_of(work, struct nvt_ts_data, resume_work); + nvt_ts_resume(&ts_core->client->dev); +} + +static int nvt_pinctrl_init(struct nvt_ts_data *nvt_data) +{ + int retval = 0; + /* Get pinctrl if target uses pinctrl */ + nvt_data->ts_pinctrl = devm_pinctrl_get(&nvt_data->client->dev); + NVT_LOG("%s Enter\n", __func__); + if (IS_ERR_OR_NULL(nvt_data->ts_pinctrl)) { + retval = PTR_ERR(nvt_data->ts_pinctrl); + NVT_ERR("Target does not use pinctrl %d\n", retval); + goto err_pinctrl_get; + } + + nvt_data->pinctrl_state_active = pinctrl_lookup_state( + nvt_data->ts_pinctrl, PINCTRL_STATE_ACTIVE); + + if (IS_ERR_OR_NULL(nvt_data->pinctrl_state_active)) { + retval = PTR_ERR(nvt_data->pinctrl_state_active); + NVT_ERR("Can not lookup %s pinstate %d\n", PINCTRL_STATE_ACTIVE, + retval); + goto err_pinctrl_lookup; + } + + nvt_data->pinctrl_state_suspend = pinctrl_lookup_state( + nvt_data->ts_pinctrl, PINCTRL_STATE_SUSPEND); + + if (IS_ERR_OR_NULL(nvt_data->pinctrl_state_suspend)) { + retval = PTR_ERR(nvt_data->pinctrl_state_suspend); + NVT_ERR("Can not lookup %s pinstate %d\n", + PINCTRL_STATE_SUSPEND, retval); + goto err_pinctrl_lookup; + } + + return 0; +err_pinctrl_lookup: + devm_pinctrl_put(nvt_data->ts_pinctrl); +err_pinctrl_get: + nvt_data->ts_pinctrl = NULL; + return retval; +} + +static void get_lockdown_info(struct work_struct *work) +{ + int ret = 0; + + NVT_LOG("lkdown_readed = %d", ts->lkdown_readed); + + if (!ts->lkdown_readed) { + ret = dsi_panel_lockdown_info_read(ts->lockdown_info); + if (ret < 0) { + NVT_ERR("can't get lockdown info"); + } else { + NVT_LOG("Lockdown:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + ts->lockdown_info[0], ts->lockdown_info[1], + ts->lockdown_info[2], ts->lockdown_info[3], + ts->lockdown_info[4], ts->lockdown_info[5], + ts->lockdown_info[6], ts->lockdown_info[7]); + } + ts->lkdown_readed = true; + NVT_LOG("READ LOCKDOWN!!!"); + } else { + NVT_LOG("use lockdown info that readed before"); + NVT_LOG("Lockdown:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + ts->lockdown_info[0], ts->lockdown_info[1], + ts->lockdown_info[2], ts->lockdown_info[3], + ts->lockdown_info[4], ts->lockdown_info[5], + ts->lockdown_info[6], ts->lockdown_info[7]); + } +} + +/******************************************************* +Description: + Novatek touchscreen write doubleclick wakeup cmd. + +return: + n.a. +*******************************************************/ +void nvt_enable_doubleclick(void) +{ + int ret = 0; + uint8_t buf[4] = { 0 }; + if (ts->db_wakeup) { + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x13; + ret = CTP_SPI_WRITE(ts->client, buf, 2); + if (ret) { + NVT_ERR("Failed\n"); + return; + } + NVT_LOG("Success\n"); + msleep(20); + } else { + NVT_LOG("skip\n"); + } +} + +/******************************************************* +Description: + Novatek touchscreen driver probe function. + +return: + Executive outcomes. 0---succeed. negative---failed +*******************************************************/ +static int32_t nvt_ts_probe(struct spi_device *client) +{ + int32_t ret = 0; +#if ((TOUCH_KEY_NUM > 0) || WAKEUP_GESTURE) + int32_t retry = 0; +#endif + struct attribute_group *attrs_p = NULL; + + NVT_LOG("probe start\n"); + + ts = kzalloc(sizeof(struct nvt_ts_data), GFP_KERNEL); + if (ts == NULL) { + NVT_ERR("failed to allocated memory for nvt ts data\n"); + return -ENOMEM; + } + + ts->xbuf = (uint8_t *)kzalloc((NVT_TRANSFER_LEN + 1 + DUMMY_BYTES), + GFP_KERNEL); + if (ts->xbuf == NULL) { + NVT_ERR("kzalloc for xbuf failed!\n"); + ret = -ENOMEM; + goto err_malloc_xbuf; + } + + ts->rbuf = (uint8_t *)kzalloc(NVT_READ_LEN, GFP_KERNEL); + if (ts->rbuf == NULL) { + NVT_ERR("kzalloc for rbuf failed!\n"); + ret = -ENOMEM; + goto err_malloc_rbuf; + } + + ts->client = client; + spi_set_drvdata(client, ts); + + //---prepare for spi parameter--- + if (ts->client->master->flags & SPI_MASTER_HALF_DUPLEX) { + NVT_ERR("Full duplex not supported by master\n"); + ret = -EIO; + goto err_ckeck_full_duplex; + } + ts->client->bits_per_word = 8; + ts->client->mode = SPI_MODE_0; + + ret = spi_setup(ts->client); + if (ret < 0) { + NVT_ERR("Failed to perform SPI setup\n"); + goto err_spi_setup; + } + +#ifdef CONFIG_MTK_SPI + /* old usage of MTK spi API */ + memcpy(&ts->spi_ctrl, &spi_ctrdata, sizeof(struct mt_chip_conf)); + ts->client->controller_data = (void *)&ts->spi_ctrl; +#endif + +#ifdef CONFIG_SPI_MT65XX + /* new usage of MTK spi API */ + memcpy(&ts->spi_ctrl, &spi_ctrdata, sizeof(struct mtk_chip_config)); + ts->client->controller_data = (void *)&ts->spi_ctrl; +#endif + + NVT_LOG("mode=%d, max_speed_hz=%d\n", ts->client->mode, + ts->client->max_speed_hz); + + //---parse dts--- + ret = nvt_parse_dt(&client->dev); + if (ret) { + NVT_ERR("parse dt error\n"); + goto err_spi_setup; + } + + ret = nvt_pinctrl_init(ts); + if (!ret && ts->ts_pinctrl) { + ret = pinctrl_select_state(ts->ts_pinctrl, + ts->pinctrl_state_active); + if (ret < 0) { + NVT_ERR("Failed to select %s pinstate %d\n", + PINCTRL_STATE_ACTIVE, ret); + } + } else { + NVT_ERR("Failed to init pinctrl\n"); + } + + //---request and config GPIOs--- + ret = nvt_gpio_config(ts); + if (ret) { + NVT_ERR("gpio config error!\n"); + goto err_gpio_config_failed; + } + + mutex_init(&ts->lock); + mutex_init(&ts->xbuf_lock); + + //---eng reset before TP_RESX high + nvt_eng_reset(); + +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 1); +#endif + + // need 10ms delay after POR(power on reset) + msleep(10); + + //---check chip version trim--- + ret = nvt_ts_check_chip_ver_trim(CHIP_VER_TRIM_ADDR); + if (ret) { + NVT_LOG("try to check from old chip ver trim address\n"); + ret = nvt_ts_check_chip_ver_trim(CHIP_VER_TRIM_OLD_ADDR); + if (ret) { + NVT_ERR("chip is not identified\n"); + ret = -EINVAL; + goto err_chipvertrim_failed; + } + } + + ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; + ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + + //---allocate input device--- + ts->input_dev = input_allocate_device(); + if (ts->input_dev == NULL) { + NVT_ERR("allocate input device failed\n"); + ret = -ENOMEM; + goto err_input_dev_alloc_failed; + } + + ts->max_touch_num = TOUCH_MAX_FINGER_NUM; + +#if TOUCH_KEY_NUM > 0 + ts->max_button_num = TOUCH_KEY_NUM; +#endif + + ts->int_trigger_type = INT_TRIGGER_TYPE; + + //---set input device info.--- + ts->input_dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | + BIT_MASK(EV_ABS); + ts->input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); + ts->input_dev->propbit[0] = BIT(INPUT_PROP_DIRECT); + + ts->db_wakeup = 0; + ts->fw_ver = 0; + ts->x_num = 32; + ts->y_num = 50; + ts->x_gang_num = 4; + ts->y_gang_num = 6; + ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; + ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + ts->max_button_num = TOUCH_KEY_NUM; + NVT_LOG("Set default fw_ver=%d, x_num=%d, y_num=%d, " + "abs_x_max=%d, abs_y_max=%d, max_button_num=%d!\n", + ts->fw_ver, ts->x_num, ts->y_num, ts->abs_x_max, ts->abs_y_max, + ts->max_button_num); + +#if MT_PROTOCOL_B + input_mt_init_slots(ts->input_dev, ts->max_touch_num, 0); +#endif + + input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, TOUCH_FORCE_NUM, + 0, 0); //pressure = TOUCH_FORCE_NUM + +#if TOUCH_MAX_FINGER_NUM > 1 + input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, + 0); //area = 255 + + input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, 0, + ts->abs_x_max - 1, 0, 0); + input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, 0, + ts->abs_y_max - 1, 0, 0); +#if MT_PROTOCOL_B + // no need to set ABS_MT_TRACKING_ID, input_mt_init_slots() already set it +#else + input_set_abs_params(ts->input_dev, ABS_MT_TRACKING_ID, 0, + ts->max_touch_num, 0, 0); +#endif //MT_PROTOCOL_B +#endif //TOUCH_MAX_FINGER_NUM > 1 + +#if TOUCH_KEY_NUM > 0 + for (retry = 0; retry < ts->max_button_num; retry++) { + input_set_capability(ts->input_dev, EV_KEY, + touch_key_array[retry]); + } +#endif + +#if WAKEUP_GESTURE + for (retry = 0; + retry < (sizeof(gesture_key_array) / sizeof(gesture_key_array[0])); + retry++) { + input_set_capability(ts->input_dev, EV_KEY, + gesture_key_array[retry]); + } +#endif + + sprintf(ts->phys, "input/ts"); + ts->input_dev->name = NVT_TS_NAME; + ts->input_dev->phys = ts->phys; + ts->input_dev->id.bustype = BUS_SPI; + + //---register input device--- + ret = input_register_device(ts->input_dev); + if (ret) { + NVT_ERR("register input device (%s) failed. ret=%d\n", + ts->input_dev->name, ret); + goto err_input_register_device_failed; + } + + if (ts->pen_support) { + //---allocate pen input device--- + ts->pen_input_dev = input_allocate_device(); + if (ts->pen_input_dev == NULL) { + NVT_ERR("allocate pen input device failed\n"); + ret = -ENOMEM; + goto err_pen_input_dev_alloc_failed; + } + + //---set pen input device info.--- + ts->pen_input_dev->evbit[0] = + BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + ts->pen_input_dev->keybit[BIT_WORD(BTN_TOUCH)] = + BIT_MASK(BTN_TOUCH); + ts->pen_input_dev->keybit[BIT_WORD(BTN_TOOL_PEN)] |= + BIT_MASK(BTN_TOOL_PEN); + //ts->pen_input_dev->keybit[BIT_WORD(BTN_TOOL_RUBBER)] |= BIT_MASK(BTN_TOOL_RUBBER); + ts->pen_input_dev->keybit[BIT_WORD(BTN_STYLUS)] |= + BIT_MASK(BTN_STYLUS); + ts->pen_input_dev->keybit[BIT_WORD(BTN_STYLUS2)] |= + BIT_MASK(BTN_STYLUS2); + ts->pen_input_dev->propbit[0] = BIT(INPUT_PROP_DIRECT); + + if (ts->wgp_stylus) { + input_set_abs_params(ts->pen_input_dev, ABS_X, 0, + ts->abs_x_max * 2 - 1, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, + ts->abs_y_max * 2 - 1, 0, 0); + } else { + input_set_abs_params(ts->pen_input_dev, ABS_X, 0, + ts->abs_x_max - 1, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_Y, 0, + ts->abs_y_max - 1, 0, 0); + } + + input_set_abs_params(ts->pen_input_dev, ABS_PRESSURE, 0, + PEN_PRESSURE_MAX, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_DISTANCE, 0, + PEN_DISTANCE_MAX, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_TILT_X, + PEN_TILT_MIN, PEN_TILT_MAX, 0, 0); + input_set_abs_params(ts->pen_input_dev, ABS_TILT_Y, + PEN_TILT_MIN, PEN_TILT_MAX, 0, 0); + + sprintf(ts->pen_phys, "input/pen"); + ts->pen_input_dev->name = NVT_PEN_NAME; + ts->pen_input_dev->phys = ts->pen_phys; + ts->pen_input_dev->id.bustype = BUS_SPI; + + //---register pen input device--- + ret = input_register_device(ts->pen_input_dev); + if (ret) { + NVT_ERR("register pen input device (%s) failed. ret=%d\n", + ts->pen_input_dev->name, ret); + goto err_pen_input_register_device_failed; + } + } /* if (ts->pen_support) */ + + //---set int-pin & request irq--- + client->irq = gpio_to_irq(ts->irq_gpio); + if (client->irq) { + NVT_LOG("int_trigger_type=%d\n", ts->int_trigger_type); + ts->irq_enabled = true; + ret = request_threaded_irq(client->irq, NULL, nvt_ts_work_func, + ts->int_trigger_type | IRQF_ONESHOT, + NVT_SPI_NAME, ts); + if (ret != 0) { + NVT_ERR("request irq failed. ret=%d\n", ret); + goto err_int_request_failed; + } else { + nvt_irq_enable(false); + NVT_LOG("request irq %d succeed\n", client->irq); + } + } + + INIT_WORK(&ts->switch_mode_work, nvt_switch_mode_work); + INIT_WORK(&ts->pen_charge_state_change_work, + nvt_pen_charge_state_change_work); + ts->pen_is_charge = false; + + ts->lkdown_readed = false; + pm_stay_awake(&client->dev); + nvt_lockdown_wq = alloc_workqueue("nvt_lockdown_wq", + WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + if (!nvt_lockdown_wq) { + NVT_ERR("nvt_lockdown_wq create workqueue failed\n"); + ret = -ENOMEM; + goto err_create_nvt_lockdown_wq_failed; + } + INIT_DELAYED_WORK(&ts->nvt_lockdown_work, get_lockdown_info); + /* please make sure boot update start after display reset(RESX) sequence*/ + queue_delayed_work(nvt_lockdown_wq, &ts->nvt_lockdown_work, + msecs_to_jiffies(4000)); + +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 1); +#endif + + ts->ic_state = NVT_IC_INIT; + ts->dev_pm_suspend = false; + ts->gesture_command_delayed = -1; + init_completion(&ts->dev_pm_suspend_completion); + ts->fw_debug = false; + +#ifdef CONFIG_FACTORY_BUILD + ts->pen_input_dev_enable = 1; +#else + ts->pen_input_dev_enable = 0; +#endif + +#if BOOT_UPDATE_FIRMWARE + nvt_fwu_wq = + alloc_workqueue("nvt_fwu_wq", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + if (!nvt_fwu_wq) { + NVT_ERR("nvt_fwu_wq create workqueue failed\n"); + ret = -ENOMEM; + goto err_create_nvt_fwu_wq_failed; + } + INIT_DELAYED_WORK(&ts->nvt_fwu_work, Boot_Update_Firmware); + // please make sure boot update start after display reset(RESX) sequence + queue_delayed_work(nvt_fwu_wq, &ts->nvt_fwu_work, + msecs_to_jiffies(14000)); +#endif + + NVT_LOG("NVT_TOUCH_ESD_PROTECT is %d\n", NVT_TOUCH_ESD_PROTECT); +#if NVT_TOUCH_ESD_PROTECT + INIT_DELAYED_WORK(&nvt_esd_check_work, nvt_esd_check_func); + nvt_esd_check_wq = + alloc_workqueue("nvt_esd_check_wq", WQ_MEM_RECLAIM, 1); + if (!nvt_esd_check_wq) { + NVT_ERR("nvt_esd_check_wq create workqueue failed\n"); + ret = -ENOMEM; + goto err_create_nvt_esd_check_wq_failed; + } + queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, + msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + //---set device node--- +#if NVT_TOUCH_PROC + ret = nvt_flash_proc_init(); + if (ret != 0) { + NVT_ERR("nvt flash proc init failed. ret=%d\n", ret); + goto err_flash_proc_init_failed; + } +#endif + +#if NVT_TOUCH_EXT_PROC + ret = nvt_extra_proc_init(); + if (ret != 0) { + NVT_ERR("nvt extra proc init failed. ret=%d\n", ret); + goto err_extra_proc_init_failed; + } +#endif + +#if NVT_TOUCH_MP + ret = nvt_mp_proc_init(); + if (ret != 0) { + NVT_ERR("nvt mp proc init failed. ret=%d\n", ret); + goto err_mp_proc_init_failed; + } +#endif + +#ifndef NVT_SAVE_TESTDATA_IN_FILE + ret = nvt_test_data_proc_init(ts->client); + if (ret < 0) { + NVT_ERR("nvt test data interface init failed. ret=%d\n", ret); + goto err_mp_proc_init_failed; + } +#endif + + attrs_p = (struct attribute_group *)devm_kzalloc( + &client->dev, sizeof(*attrs_p), GFP_KERNEL); + if (!attrs_p) { + NVT_ERR("no mem to alloc"); + goto err_mp_proc_init_failed; + } + ts->attrs = attrs_p; + attrs_p->name = "panel_info"; + attrs_p->attrs = nvt_panel_attr; + ret = sysfs_create_group(&client->dev.kobj, ts->attrs); + + ts->event_wq = + alloc_workqueue("nvt-event-queue", + WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!ts->event_wq) { + NVT_ERR("Can not create work thread for suspend/resume!!"); + ret = -ENOMEM; + goto err_alloc_work_thread_failed; + } + INIT_WORK(&ts->resume_work, nvt_resume_work); + INIT_WORK(&ts->suspend_work, nvt_suspend_work); + ts->set_touchfeature_wq = + create_singlethread_workqueue("nvt-set-touchfeature-queue"); + if (!ts->set_touchfeature_wq) { + NVT_ERR("create set touch feature workqueue fail"); + ret = -ENOMEM; + goto err_create_set_touchfeature_work_queue; + } + INIT_WORK(&ts->set_touchfeature_work, update_touchfeature_value_work); + + ts->pen_charge_state_notifier.notifier_call = + nvt_pen_charge_state_notifier_callback; + ret = pen_charge_state_notifier_register_client( + &ts->pen_charge_state_notifier); + if (ret) { + NVT_ERR("register pen charge state change notifier failed. ret=%d\n", + ret); + goto err_register_pen_charge_state_failed; + } +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM + ts->drm_notif.notifier_call = nvt_drm_notifier_callback; + ret = drm_register_client(&ts->drm_notif); + if (ret) { + NVT_ERR("register drm_notifier failed. ret=%d\n", ret); + goto err_register_drm_notif_failed; + } +#else + ts->fb_notif.notifier_call = nvt_fb_notifier_callback; + ret = fb_register_client(&ts->fb_notif); + if (ret) { + NVT_ERR("register fb_notifier failed. ret=%d\n", ret); + goto err_register_fb_notif_failed; + } +#endif +#elif defined(CONFIG_HAS_EARLYSUSPEND) + ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1; + ts->early_suspend.suspend = nvt_ts_early_suspend; + ts->early_suspend.resume = nvt_ts_late_resume; + ret = register_early_suspend(&ts->early_suspend); + if (ret) { + NVT_ERR("register early suspend failed. ret=%d\n", ret); + goto err_register_early_suspend_failed; + } +#endif + +#ifdef CONFIG_TOUCHSCREEN_NVT_DEBUG_FS + ts->debugfs = debugfs_create_dir("tp_debug", NULL); + if (ts->debugfs) { + debugfs_create_file("switch_state", 0660, ts->debugfs, ts, + &tpdbg_ops); + debugfs_create_file("touch_boost", 0660, ts->debugfs, ts, + &nvt_touch_test_fops); + } +#endif + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + xiaomi_touch_interfaces.touch_vendor_read = nvt_touch_vendor_read; + xiaomi_touch_interfaces.panel_display_read = nvt_panel_display_read; + xiaomi_touch_interfaces.panel_vendor_read = nvt_panel_vendor_read; + xiaomi_touch_interfaces.panel_color_read = nvt_panel_color_read; + xiaomi_touch_interfaces.getModeValue = nvt_get_mode_value; + xiaomi_touch_interfaces.setModeValue = nvt_set_cur_value; + xiaomi_touch_interfaces.resetMode = nvt_reset_mode; + xiaomi_touch_interfaces.getModeAll = nvt_get_mode_all; + xiaomi_touch_interfaces.palm_sensor_write = nvt_palm_sensor_write; + nvt_init_touchmode_data(); + xiaomitouch_register_modedata(&xiaomi_touch_interfaces); +#endif + + bTouchIsAwake = 1; + NVT_LOG("end\n"); + + nvt_irq_enable(true); + + return 0; + +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM + if (drm_unregister_client(&ts->drm_notif)) + NVT_ERR("Error occurred while unregistering drm_notifier.\n"); +err_register_drm_notif_failed: +#else + if (fb_unregister_client(&ts->fb_notif)) + NVT_ERR("Error occurred while unregistering fb_notifier.\n"); +err_register_fb_notif_failed: +#endif +#elif defined(CONFIG_HAS_EARLYSUSPEND) + unregister_early_suspend(&ts->early_suspend); +err_register_early_suspend_failed: +#endif + if (pen_charge_state_notifier_unregister_client( + &ts->pen_charge_state_notifier)) + NVT_ERR("Error occurred while unregistering pen charge state notifier.\n"); +err_register_pen_charge_state_failed: + destroy_workqueue(ts->set_touchfeature_wq); +err_create_set_touchfeature_work_queue: + destroy_workqueue(ts->event_wq); +err_alloc_work_thread_failed: +#ifndef NVT_SAVE_TESTDATA_IN_FILE + nvt_test_data_proc_deinit(); +#endif +#if NVT_TOUCH_MP + nvt_mp_proc_deinit(); +err_mp_proc_init_failed: +#endif +#if NVT_TOUCH_EXT_PROC + nvt_extra_proc_deinit(); +err_extra_proc_init_failed: +#endif +#if NVT_TOUCH_PROC + nvt_flash_proc_deinit(); +err_flash_proc_init_failed: +#endif +#if NVT_TOUCH_ESD_PROTECT + if (nvt_esd_check_wq) { + cancel_delayed_work_sync(&nvt_esd_check_work); + destroy_workqueue(nvt_esd_check_wq); + nvt_esd_check_wq = NULL; + } +err_create_nvt_esd_check_wq_failed: +#endif +#if BOOT_UPDATE_FIRMWARE + if (nvt_fwu_wq) { + cancel_delayed_work_sync(&ts->nvt_fwu_work); + destroy_workqueue(nvt_fwu_wq); + nvt_fwu_wq = NULL; + } +err_create_nvt_fwu_wq_failed: + if (nvt_lockdown_wq) { + cancel_delayed_work_sync(&ts->nvt_lockdown_work); + destroy_workqueue(nvt_lockdown_wq); + nvt_lockdown_wq = NULL; + } +#endif +err_create_nvt_lockdown_wq_failed: +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 0); +#endif + free_irq(client->irq, ts); +err_int_request_failed: + if (ts->pen_support) { + input_unregister_device(ts->pen_input_dev); + ts->pen_input_dev = NULL; + } +err_pen_input_register_device_failed: + if (ts->pen_support) { + if (ts->pen_input_dev) { + input_free_device(ts->pen_input_dev); + ts->pen_input_dev = NULL; + } + } +err_pen_input_dev_alloc_failed: + input_unregister_device(ts->input_dev); + ts->input_dev = NULL; +err_input_register_device_failed: + if (ts->input_dev) { + input_free_device(ts->input_dev); + ts->input_dev = NULL; + } +err_input_dev_alloc_failed: +err_chipvertrim_failed: + mutex_destroy(&ts->xbuf_lock); + mutex_destroy(&ts->lock); + nvt_gpio_deconfig(ts); +err_gpio_config_failed: +err_spi_setup: +err_ckeck_full_duplex: + spi_set_drvdata(client, NULL); + if (ts->rbuf) { + kfree(ts->rbuf); + ts->rbuf = NULL; + } +err_malloc_rbuf: + if (ts->xbuf) { + kfree(ts->xbuf); + ts->xbuf = NULL; + } +err_malloc_xbuf: + if (ts) { + kfree(ts); + ts = NULL; + } + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen driver release function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_ts_remove(struct spi_device *client) +{ + NVT_LOG("Removing driver...\n"); + +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM + if (drm_unregister_client(&ts->drm_notif)) + NVT_ERR("Error occurred while unregistering drm_notifier.\n"); +#else + if (fb_unregister_client(&ts->fb_notif)) + NVT_ERR("Error occurred while unregistering fb_notifier.\n"); +#endif +#elif defined(CONFIG_HAS_EARLYSUSPEND) + unregister_early_suspend(&ts->early_suspend); +#endif + + if (pen_charge_state_notifier_unregister_client( + &ts->pen_charge_state_notifier)) + NVT_ERR("Error occurred while unregistering pen charge state notifier.\n"); + +#if NVT_TOUCH_MP + nvt_mp_proc_deinit(); +#endif +#if NVT_TOUCH_EXT_PROC + nvt_extra_proc_deinit(); +#endif +#if NVT_TOUCH_PROC + nvt_flash_proc_deinit(); +#endif + +#if NVT_TOUCH_ESD_PROTECT + if (nvt_esd_check_wq) { + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); + destroy_workqueue(nvt_esd_check_wq); + nvt_esd_check_wq = NULL; + } +#endif + +#if BOOT_UPDATE_FIRMWARE + if (nvt_fwu_wq) { + cancel_delayed_work_sync(&ts->nvt_fwu_work); + destroy_workqueue(nvt_fwu_wq); + nvt_fwu_wq = NULL; + } +#endif + +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 0); +#endif + + nvt_irq_enable(false); + free_irq(client->irq, ts); + + mutex_destroy(&ts->xbuf_lock); + mutex_destroy(&ts->lock); + + nvt_gpio_deconfig(ts); + + if (ts->pen_support) { + if (ts->pen_input_dev) { + input_unregister_device(ts->pen_input_dev); + ts->pen_input_dev = NULL; + } + } + + if (ts->input_dev) { + input_unregister_device(ts->input_dev); + ts->input_dev = NULL; + } + + spi_set_drvdata(client, NULL); + + if (ts->set_touchfeature_wq) + destroy_workqueue(ts->set_touchfeature_wq); + + if (ts) { + kfree(ts); + ts = NULL; + } + + return 0; +} + +static void nvt_ts_shutdown(struct spi_device *client) +{ + NVT_LOG("Shutdown driver...\n"); + + nvt_irq_enable(false); + +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM + if (drm_unregister_client(&ts->drm_notif)) + NVT_ERR("Error occurred while unregistering drm_notifier.\n"); +#else + if (fb_unregister_client(&ts->fb_notif)) + NVT_ERR("Error occurred while unregistering fb_notifier.\n"); +#endif +#elif defined(CONFIG_HAS_EARLYSUSPEND) + unregister_early_suspend(&ts->early_suspend); +#endif + + destroy_workqueue(ts->event_wq); + if (pen_charge_state_notifier_unregister_client( + &ts->pen_charge_state_notifier)) + NVT_ERR("Error occurred while unregistering pen charge state notifier.\n"); + +#if NVT_TOUCH_MP + nvt_mp_proc_deinit(); +#endif +#if NVT_TOUCH_EXT_PROC + nvt_extra_proc_deinit(); +#endif +#if NVT_TOUCH_PROC + nvt_flash_proc_deinit(); +#endif + +#if NVT_TOUCH_ESD_PROTECT + if (nvt_esd_check_wq) { + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); + destroy_workqueue(nvt_esd_check_wq); + nvt_esd_check_wq = NULL; + } +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#if BOOT_UPDATE_FIRMWARE + if (nvt_fwu_wq) { + cancel_delayed_work_sync(&ts->nvt_fwu_work); + destroy_workqueue(nvt_fwu_wq); + nvt_fwu_wq = NULL; + } +#endif + +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 0); +#endif +} + +/******************************************************* +Description: + Novatek touchscreen driver suspend function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_ts_suspend(struct device *dev) +{ + uint8_t buf[4] = { 0 }; + int ret; +#if MT_PROTOCOL_B + uint32_t i = 0; +#endif + + if (!bTouchIsAwake) { + NVT_LOG("Touch is already suspend\n"); + return 0; + } + + pm_stay_awake(dev); + ts->ic_state = NVT_IC_SUSPEND_IN; + + if (!ts->db_wakeup) { + if (!ts->irq_enabled) + NVT_LOG("IRQ already disabled\n"); + else + nvt_irq_enable(false); + } + +#if NVT_TOUCH_ESD_PROTECT + NVT_LOG("cancel delayed work sync\n"); + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + mutex_lock(&ts->lock); + + NVT_LOG("suspend start\n"); + + bTouchIsAwake = 0; + + if (ts->pen_input_dev_enable) { + NVT_LOG("if enable pen,will close it"); + disable_pen_input_device(true); + } + + if (ts->db_wakeup) { + /*---write command to enter "wakeup gesture mode"---*/ + /*DoubleClick wakeup CMD was sent by display to meet timing*/ + /* + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x13; + CTP_SPI_WRITE(ts->client, buf, 2); + */ + enable_irq_wake(ts->client->irq); + + NVT_LOG("Enabled touch wakeup gesture\n"); + } else { + /*---write command to enter "deep sleep mode"---*/ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x11; + CTP_SPI_WRITE(ts->client, buf, 2); + if (ts->ts_pinctrl) { + ret = pinctrl_select_state(ts->ts_pinctrl, + ts->pinctrl_state_suspend); + if (ret < 0) { + NVT_ERR("Failed to select %s pinstate %d\n", + PINCTRL_STATE_SUSPEND, ret); + } + } else { + NVT_ERR("Failed to init pinctrl\n"); + } + } + + mutex_unlock(&ts->lock); + + /* release all touches */ +#if MT_PROTOCOL_B + for (i = 0; i < ts->max_touch_num; i++) { + input_mt_slot(ts->input_dev, i); + input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0); + input_report_abs(ts->input_dev, ABS_MT_PRESSURE, 0); + input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0); + } +#endif + input_report_key(ts->input_dev, BTN_TOUCH, 0); +#if !MT_PROTOCOL_B + input_mt_sync(ts->input_dev); +#endif + input_sync(ts->input_dev); + + msleep(50); + /* release pen event */ + release_pen_event(); + if (likely(ts->ic_state == NVT_IC_SUSPEND_IN)) + ts->ic_state = NVT_IC_SUSPEND_OUT; + else + NVT_ERR("IC state may error,caused by suspend/resume flow, please CHECK!!"); + pm_relax(dev); + NVT_LOG("end\n"); + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen driver resume function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_ts_resume(struct device *dev) +{ + int ret = 0; + if (bTouchIsAwake) { + NVT_LOG("Touch is already resume\n"); + return 0; + } + + if (ts->dev_pm_suspend) + pm_stay_awake(dev); + + mutex_lock(&ts->lock); + + NVT_LOG("resume start\n"); + ts->ic_state = NVT_IC_RESUME_IN; + if (!ts->db_wakeup) { + if (ts->ts_pinctrl) { + ret = pinctrl_select_state(ts->ts_pinctrl, + ts->pinctrl_state_active); + if (ret < 0) { + NVT_ERR("Failed to select %s pinstate %d\n", + PINCTRL_STATE_ACTIVE, ret); + } + } else { + NVT_ERR("Failed to init pinctrl\n"); + } + } + + // please make sure display reset(RESX) sequence and mipi dsi cmds sent before this +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 1); +#endif + if (nvt_get_dbgfw_status()) { + ret = nvt_update_firmware(DEFAULT_DEBUG_FW_NAME); + if (ret < 0) { + NVT_ERR("use built-in fw"); + ret = nvt_update_firmware(ts->fw_name); + } + } else { + ret = nvt_update_firmware(ts->fw_name); + } + if (ret) + NVT_ERR("download firmware failed\n"); + + nvt_check_fw_reset_state(RESET_STATE_REK); + + if (!ts->db_wakeup && !ts->irq_enabled) { + nvt_irq_enable(true); + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); + queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, + msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + bTouchIsAwake = 1; + + mutex_unlock(&ts->lock); + + disable_pen_input_device(false); + dsi_panel_doubleclick_enable( + !!ts->db_wakeup); /*if true, dbclick work until next suspend*/ + if (likely(ts->ic_state == NVT_IC_RESUME_IN)) { + ts->ic_state = NVT_IC_RESUME_OUT; + } else { + NVT_ERR("IC state may error,caused by suspend/resume flow, please CHECK!!"); + } + if (ts->gesture_command_delayed >= 0) { + ts->db_wakeup = ts->gesture_command_delayed; + ts->gesture_command_delayed = -1; + NVT_LOG("execute delayed command, set double click wakeup %d\n", + ts->db_wakeup); + dsi_panel_doubleclick_enable(!!ts->db_wakeup); + } + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + NVT_LOG("reload the game mode cmd"); + nvt_game_mode_recovery(); +#endif + + if (ts->dev_pm_suspend) + pm_relax(dev); + NVT_LOG("end\n"); + + return 0; +} + +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM +static int nvt_drm_notifier_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct drm_notify_data *evdata = data; + int *blank; + struct nvt_ts_data *ts_data = + container_of(self, struct nvt_ts_data, drm_notif); + + if (!evdata) + return 0; + + if (evdata && ts_data) { + blank = evdata->data; + if (event == DRM_EARLY_EVENT_BLANK) { + if (*blank == DRM_BLANK_POWERDOWN) { + NVT_LOG("event=%lu, *blank=%d\n", event, + *blank); + flush_workqueue(ts_data->event_wq); + queue_work(ts_data->event_wq, + &ts_data->suspend_work); + } + } else if (event == DRM_R_EARLY_EVENT_BLANK) { + if (*blank == DRM_BLANK_POWERDOWN) { + NVT_LOG("event=%lu, *blank=%d\n", event, + *blank); + nvt_enable_doubleclick(); + } + } else if (event == DRM_EVENT_BLANK) { + if (*blank == DRM_BLANK_UNBLANK) { + NVT_LOG("event=%lu, *blank=%d\n", event, + *blank); + flush_workqueue(ts_data->event_wq); + queue_work(ts_data->event_wq, + &ts_data->resume_work); + } + } + } + + return 0; +} +#else +static int nvt_fb_notifier_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct fb_event *evdata = data; + int *blank; + struct nvt_ts_data *ts = + container_of(self, struct nvt_ts_data, fb_notif); + + if (evdata && evdata->data && event == FB_EARLY_EVENT_BLANK) { + blank = evdata->data; + if (*blank == FB_BLANK_POWERDOWN) { + NVT_LOG("event=%lu, *blank=%d\n", event, *blank); + nvt_ts_suspend(&ts->client->dev); + } + } else if (evdata && evdata->data && event == FB_EVENT_BLANK) { + blank = evdata->data; + if (*blank == FB_BLANK_UNBLANK) { + NVT_LOG("event=%lu, *blank=%d\n", event, *blank); + nvt_ts_resume(&ts->client->dev); + } + } + + return 0; +} +#endif + +static int nvt_pm_suspend(struct device *dev) +{ + if (device_may_wakeup(dev) && ts->db_wakeup) { + NVT_LOG("enable touch irq wake\n"); + enable_irq_wake(ts->client->irq); + } + ts->dev_pm_suspend = true; + reinit_completion(&ts->dev_pm_suspend_completion); + + return 0; +} + +static int nvt_pm_resume(struct device *dev) +{ + if (device_may_wakeup(dev) && ts->db_wakeup) { + NVT_LOG("disable touch irq wake\n"); + disable_irq_wake(ts->client->irq); + } + ts->dev_pm_suspend = false; + complete(&ts->dev_pm_suspend_completion); + + return 0; +} + +static const struct dev_pm_ops nvt_dev_pm_ops = { + .suspend = nvt_pm_suspend, + .resume = nvt_pm_resume, +}; + +#elif defined(CONFIG_HAS_EARLYSUSPEND) +/******************************************************* +Description: + Novatek touchscreen driver early suspend function. + +return: + n.a. +*******************************************************/ +static void nvt_ts_early_suspend(struct early_suspend *h) +{ + nvt_ts_suspend(ts->client, PMSG_SUSPEND); +} + +/******************************************************* +Description: + Novatek touchscreen driver late resume function. + +return: + n.a. +*******************************************************/ +static void nvt_ts_late_resume(struct early_suspend *h) +{ + nvt_ts_resume(ts->client); +} +#endif + +static const struct spi_device_id nvt_ts_id[] = { { NVT_SPI_NAME, 0 }, {} }; + +#ifdef CONFIG_OF +static struct of_device_id nvt_match_table[] = { + { + .compatible = "novatek,NVT-ts-spi", + }, + {}, +}; +#endif + +static struct spi_driver nvt_spi_driver = { + .probe = nvt_ts_probe, + .remove = nvt_ts_remove, + .shutdown = nvt_ts_shutdown, + .id_table = nvt_ts_id, + .driver = { + .name = NVT_SPI_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &nvt_dev_pm_ops, +#endif +#ifdef CONFIG_OF + .of_match_table = nvt_match_table, +#endif + }, +}; + +static bool nvt_off_charger_mode(void) +{ + bool charger_mode = false; + char charger_node[8] = { '\0' }; + char *chose = (char *)strnstr(saved_command_line, "androidboot.mode=", + strlen(saved_command_line)); + if (chose) { + memcpy(charger_node, (chose + strlen("androidboot.mode=")), + sizeof(charger_node) - 1); + NVT_LOG("%s: charger_node is %s\n", __func__, charger_node); + if (!strncmp(charger_node, "charger", strlen("charger"))) { + charger_mode = true; + } + } + return charger_mode; +} + +/******************************************************* +Description: + Driver Install function. + +return: + Executive Outcomes. 0---succeed. not 0---failed. +********************************************************/ +static int32_t __init nvt_driver_init(void) +{ + int32_t ret = 0; + + NVT_LOG("driver init start\n"); + if (nvt_off_charger_mode()) { + NVT_LOG("off_charger states, %s exit", __func__); + return 0; + } + + //---add spi driver--- + ret = spi_register_driver(&nvt_spi_driver); + if (ret) { + NVT_ERR("failed to add spi driver"); + goto err_driver; + } + + NVT_LOG("finished\n"); + +err_driver: + return ret; +} + +/******************************************************* +Description: + Driver uninstall function. + +return: + n.a. +********************************************************/ +static void __exit nvt_driver_exit(void) +{ + spi_unregister_driver(&nvt_spi_driver); +} + +late_initcall(nvt_driver_init); +//module_init(nvt_driver_init); +module_exit(nvt_driver_exit); + +MODULE_DESCRIPTION("Novatek Touchscreen Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h new file mode 100644 index 000000000000..fcc59ba5cf78 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * $Revision: 69262 $ + * $Date: 2020-09-23 15:07:14 +0800 (週三, 23 ä¹æœˆ 2020) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#ifndef _LINUX_NVT_TOUCH_H +#define _LINUX_NVT_TOUCH_H + +#include +#include +#include +#include +#include + +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif +#include "nt36xxx_mem_map.h" + +#ifdef CONFIG_MTK_SPI +/* Please copy mt_spi.h file under mtk spi driver folder */ +#include "mt_spi.h" +#endif + +#ifdef CONFIG_SPI_MT65XX +#include +#endif + +#define NVT_DEBUG 1 + +//---GPIO number--- +#define NVTTOUCH_RST_PIN 980 +#define NVTTOUCH_INT_PIN 943 + +#define NVT_LOCKDOWN_SIZE 8 +#define PINCTRL_STATE_ACTIVE "pmx_ts_active" +#define PINCTRL_STATE_SUSPEND "pmx_ts_suspend" + +//---INT trigger mode--- +//#define IRQ_TYPE_EDGE_RISING 1 +//#define IRQ_TYPE_EDGE_FALLING 2 +#define INT_TRIGGER_TYPE IRQ_TYPE_EDGE_RISING + +//---SPI driver info.--- +#define NVT_SPI_NAME "NVT-ts" + +#if NVT_DEBUG +#define NVT_LOG(fmt, args...) \ + pr_err("[%s] %s %d: " fmt, NVT_SPI_NAME, __func__, __LINE__, ##args) +#else +#define NVT_LOG(fmt, args...) \ + pr_info("[%s] %s %d: " fmt, NVT_SPI_NAME, __func__, __LINE__, ##args) +#endif +#define NVT_ERR(fmt, args...) \ + pr_err("[%s] %s %d: " fmt, NVT_SPI_NAME, __func__, __LINE__, ##args) + +//---Input device info.--- +#define NVT_TS_NAME "NVTCapacitiveTouchScreen" +#define NVT_PEN_NAME "NVTCapacitivePen" + +//---Touch info.--- +#define TOUCH_DEFAULT_MAX_WIDTH 1600 +#define TOUCH_DEFAULT_MAX_HEIGHT 2560 +#define TOUCH_MAX_FINGER_NUM 10 +#define TOUCH_KEY_NUM 0 +#if TOUCH_KEY_NUM > 0 +extern const uint16_t touch_key_array[TOUCH_KEY_NUM]; +#endif +#define TOUCH_FORCE_NUM 1000 +//---for Pen--- +#define PEN_PRESSURE_MAX (4095) +#define PEN_DISTANCE_MAX (1) +#define PEN_TILT_MIN (-60) +#define PEN_TILT_MAX (60) + +/* Enable only when module have tp reset pin and connected to host */ +#define NVT_TOUCH_SUPPORT_HW_RST 0 + +//---Customerized func.--- +#define NVT_TOUCH_PROC 1 +#define NVT_TOUCH_EXT_PROC 1 +#define NVT_TOUCH_MP 1 +#define NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV 1 +#define MT_PROTOCOL_B 1 +#define WAKEUP_GESTURE 1 +#define FUNCPAGE_PALM 4 +#define PACKET_PALM_ON 3 +#define PACKET_PALM_OFF 4 + +#if WAKEUP_GESTURE +extern const uint16_t gesture_key_array[]; +#endif +#define BOOT_UPDATE_FIRMWARE 1 +#define DEFAULT_BOOT_UPDATE_FIRMWARE_NAME "novatek_ts_fw.bin" +#define DEFAULT_MP_UPDATE_FIRMWARE_NAME "novatek_ts_mp.bin" +#define DEFAULT_DEBUG_FW_NAME "novatek_debug_fw.bin" +#define DEFAULT_DEBUG_MP_NAME "novatek_debug_mp.bin" +#define POINT_DATA_CHECKSUM 1 +#define POINT_DATA_CHECKSUM_LEN 65 +#define CHECK_PEN_DATA_CHECKSUM 0 + +//---ESD Protect.--- +#define NVT_TOUCH_ESD_PROTECT 1 +#define NVT_TOUCH_ESD_CHECK_PERIOD 1500 /* ms */ +#define NVT_TOUCH_WDT_RECOVERY 1 + +enum nvt_ic_state { + NVT_IC_SUSPEND_IN, + NVT_IC_SUSPEND_OUT, + NVT_IC_RESUME_IN, + NVT_IC_RESUME_OUT, + NVT_IC_INIT, +}; + +struct nvt_config_info { + u8 tp_vendor; + u8 tp_color; + u8 display_maker; + u8 glass_vendor; + const char *nvt_fw_name; + const char *nvt_mp_name; + const char *nvt_limit_name; +}; + +struct nvt_ts_data { + struct spi_device *client; + struct input_dev *input_dev; + struct delayed_work nvt_fwu_work; + struct delayed_work nvt_lockdown_work; + struct work_struct switch_mode_work; + struct work_struct pen_charge_state_change_work; + bool pen_is_charge; + struct notifier_block pen_charge_state_notifier; + uint16_t addr; + int8_t phys[32]; +#if defined(CONFIG_FB) +#ifdef CONFIG_DRM + struct notifier_block drm_notif; +#else + struct notifier_block fb_notif; +#endif +#elif defined(CONFIG_HAS_EARLYSUSPEND) + struct early_suspend early_suspend; +#endif + uint32_t config_array_size; + struct nvt_config_info *config_array; + const u8 *fw_name; + const u8 *mp_name; + bool lkdown_readed; + u8 lockdown_info[NVT_LOCKDOWN_SIZE]; + uint8_t fw_ver; + uint8_t x_num; + uint8_t y_num; + int ic_state; + uint16_t abs_x_max; + uint16_t abs_y_max; + uint8_t max_touch_num; + uint8_t max_button_num; + uint32_t int_trigger_type; +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + u32 gamemode_config[3][5]; + struct workqueue_struct *set_touchfeature_wq; + struct work_struct set_touchfeature_work; +#endif + int32_t irq_gpio; + uint32_t irq_flags; + int32_t reset_gpio; + uint32_t reset_flags; + struct mutex lock; + const struct nvt_ts_mem_map *mmap; + uint8_t carrier_system; + uint8_t hw_crc; + uint16_t nvt_pid; + uint8_t *rbuf; + uint8_t *xbuf; + struct mutex xbuf_lock; + bool irq_enabled; + uint8_t cascade; + bool pen_support; + bool wgp_stylus; + uint8_t x_gang_num; + uint8_t y_gang_num; + struct input_dev *pen_input_dev; + bool pen_input_dev_enable; + int8_t pen_phys[32]; + struct workqueue_struct *event_wq; + struct work_struct suspend_work; + struct work_struct resume_work; + struct attribute_group *attrs; + int result_type; + int panel_index; + uint32_t spi_max_freq; + int db_wakeup; +#ifdef CONFIG_MTK_SPI + struct mt_chip_conf spi_ctrl; +#endif +#ifdef CONFIG_SPI_MT65XX + struct mtk_chip_config spi_ctrl; +#endif +#ifdef CONFIG_TOUCHSCREEN_NVT_DEBUG_FS + struct dentry *debugfs; +#endif + uint8_t debug_flag; + bool fw_debug; + bool dev_pm_suspend; + struct completion dev_pm_suspend_completion; + bool palm_sensor_switch; + int gesture_command_delayed; + struct pinctrl *ts_pinctrl; + struct pinctrl_state *pinctrl_state_active; + struct pinctrl_state *pinctrl_state_suspend; +#ifndef NVT_SAVE_TESTDATA_IN_FILE + void *testdata; +#endif +}; + +#if NVT_TOUCH_PROC +struct nvt_flash_data { + rwlock_t lock; +}; +#endif + +typedef enum { + RESET_STATE_INIT = 0xA0, // IC reset + RESET_STATE_REK, // ReK baseline + RESET_STATE_REK_FINISH, // baseline is ready + RESET_STATE_NORMAL_RUN, // normal run + RESET_STATE_MAX = 0xAF +} RST_COMPLETE_STATE; + +typedef enum { + EVENT_MAP_HOST_CMD = 0x50, + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE = 0x51, + EVENT_MAP_RESET_COMPLETE = 0x60, + EVENT_MAP_FWINFO = 0x78, + EVENT_MAP_PROJECTID = 0x9A, +} SPI_EVENT_MAP; + +//---SPI READ/WRITE--- +#define SPI_WRITE_MASK(a) (a | 0x80) +#define SPI_READ_MASK(a) (a & 0x7F) + +#define DUMMY_BYTES (1) +#define NVT_TRANSFER_LEN (63 * 1024) +#define NVT_READ_LEN (2 * 1024) + +typedef enum { NVTWRITE = 0, NVTREAD = 1 } NVT_SPI_RW; + +//---extern structures--- +extern struct nvt_ts_data *ts; + +//---extern functions--- +int32_t CTP_SPI_READ(struct spi_device *client, uint8_t *buf, uint16_t len); +int32_t CTP_SPI_WRITE(struct spi_device *client, uint8_t *buf, uint16_t len); +void nvt_bootloader_reset(void); +void nvt_eng_reset(void); +void nvt_sw_reset(void); +void nvt_sw_reset_idle(void); +void nvt_boot_ready(void); +void nvt_bld_crc_enable(void); +void nvt_fw_crc_enable(void); +void nvt_tx_auto_copy_mode(void); +void nvt_set_dbgfw_status(bool enable); +void nvt_match_fw(void); +int32_t nvt_update_firmware(const char *firmware_name); +int32_t nvt_check_fw_reset_state(RST_COMPLETE_STATE check_reset_state); +int32_t nvt_get_fw_info(void); +int32_t nvt_clear_fw_status(void); +int32_t nvt_check_fw_status(void); +int32_t nvt_check_spi_dma_tx_info(void); +int32_t nvt_set_page(uint32_t addr); +int32_t nvt_write_addr(uint32_t addr, uint8_t data); +bool nvt_get_dbgfw_status(void); +int32_t nvt_set_pocket_palm_switch(uint8_t pocket_palm_switch); +#if NVT_TOUCH_ESD_PROTECT +extern void nvt_esd_check_enable(uint8_t enable); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#endif /* _LINUX_NVT_TOUCH_H */ diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_ext_proc.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_ext_proc.c new file mode 100644 index 000000000000..5fe90c63a0dd --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_ext_proc.c @@ -0,0 +1,2639 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * $Revision: 57674 $ + * $Date: 2020-03-02 11:16:20 +0800 (週一, 02 三月 2020) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include + +#include "nt36xxx.h" + +#if NVT_TOUCH_EXT_PROC +#define NVT_FW_VERSION "nvt_fw_version" +#define NVT_BASELINE "nvt_baseline" +#define NVT_RAW "nvt_raw" +#define NVT_DIFF "nvt_diff" +#define NVT_PEN_DIFF "nvt_pen_diff" +#define NVT_PF_SWITCH "nvt_pf_switch" +#define NVT_SENSITIVITY_SWITCH "nvt_sensitivity_switch" +#define NVT_ER_RANGE_SWITCH "nvt_er_range_switch" +#define NVT_EDGE_REJECT_SWITCH "nvt_edge_reject_switch" +#define NVT_HAND_ONLY_SWITCH "nvt_hand_only_switch" +#define NVT_DRAG_LATENCY_SWITCH "nvt_drag_latency_switch" +#define NVT_SMALL_JITTER_SWITCH "nvt_small_jitter_switch" +#define NVT_GAME_MODE_SWITCH "nvt_game_mode_switch" +#define NVT_XIAOMI_LOCKDOWN_INFO "tp_lockdown_info" + +#define BUS_TRANSFER_LENGTH 256 + +#define NORMAL_MODE 0x00 +#define TEST_MODE_1 0x21 +#define TEST_MODE_2 0x22 +#define HANDSHAKING_HOST_READY 0xBB + +#define XDATA_SECTOR_SIZE 256 + +static uint8_t xdata_tmp[5000] = { 0 }; +static int32_t xdata[2500] = { 0 }; +static int32_t xdata_pen_tip_x[256] = { 0 }; +static int32_t xdata_pen_tip_y[256] = { 0 }; +static int32_t xdata_pen_ring_x[256] = { 0 }; +static int32_t xdata_pen_ring_y[256] = { 0 }; + +static struct proc_dir_entry *NVT_proc_fw_version_entry; +static struct proc_dir_entry *NVT_proc_baseline_entry; +static struct proc_dir_entry *NVT_proc_raw_entry; +static struct proc_dir_entry *NVT_proc_diff_entry; +static struct proc_dir_entry *NVT_proc_pen_diff_entry; +static struct proc_dir_entry *NVT_proc_pf_switch_entry; +static struct proc_dir_entry *NVT_proc_sensitivity_switch_entry; +static struct proc_dir_entry *NVT_proc_er_range_switch_entry; +static struct proc_dir_entry *NVT_proc_edge_reject_switch_entry; +static struct proc_dir_entry *NVT_proc_hand_only_switch_entry; +static struct proc_dir_entry *NVT_proc_drag_latency_switch_entry; +static struct proc_dir_entry *NVT_proc_small_jitter_switch_entry; +static struct proc_dir_entry *NVT_proc_xiaomi_lockdown_info_entry; +static struct proc_dir_entry *NVT_proc_game_mode_switch_entry; + +/******************************************************* +Description: + Novatek touchscreen change mode function. + +return: + n.a. +*******************************************************/ +void nvt_change_mode(uint8_t mode) +{ + uint8_t buf[8] = { 0 }; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + //---set mode--- + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = mode; + CTP_SPI_WRITE(ts->client, buf, 2); + + if (mode == NORMAL_MODE) { + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = HANDSHAKING_HOST_READY; + CTP_SPI_WRITE(ts->client, buf, 2); + msleep(20); + } +} + +int32_t nvt_set_pen_inband_mode_1(uint8_t freq_idx, uint8_t x_term) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 5; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + //---set mode--- + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0xC1; + buf[2] = 0x02; + buf[3] = freq_idx; + buf[4] = x_term; + CTP_SPI_WRITE(ts->client, buf, 5); + + for (i = 0; i < retry; i++) { + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + if (buf[1] == 0x00) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); + return -1; + } else { + return 0; + } +} + +int32_t nvt_set_pen_normal_mode(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 5; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + //---set mode--- + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0xC1; + buf[2] = 0x04; + CTP_SPI_WRITE(ts->client, buf, 3); + + for (i = 0; i < retry; i++) { + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + if (buf[1] == 0x00) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); + return -1; + } else { + return 0; + } +} + +/******************************************************* +Description: + Novatek touchscreen get firmware pipe function. + +return: + Executive outcomes. 0---pipe 0. 1---pipe 1. +*******************************************************/ +uint8_t nvt_get_fw_pipe(void) +{ + uint8_t buf[8] = { 0 }; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + //---read fw status--- + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + + //NVT_LOG("FW pipe=%d, buf[1]=0x%02X\n", (buf[1]&0x01), buf[1]); + + return (buf[1] & 0x01); +} + +/******************************************************* +Description: + Novatek touchscreen read meta data function. + +return: + n.a. +*******************************************************/ +void nvt_read_mdata(uint32_t xdata_addr, uint32_t xdata_btn_addr) +{ + int32_t i = 0; + int32_t j = 0; + int32_t k = 0; + uint8_t buf[BUS_TRANSFER_LENGTH + 2] = { 0 }; + uint32_t head_addr = 0; + int32_t dummy_len = 0; + int32_t data_len = 0; + int32_t residual_len = 0; + + //---set xdata sector address & length--- + head_addr = xdata_addr - (xdata_addr % XDATA_SECTOR_SIZE); + dummy_len = xdata_addr - head_addr; + data_len = ts->x_num * ts->y_num * 2; + residual_len = (head_addr + dummy_len + data_len) % XDATA_SECTOR_SIZE; + + //printk("head_addr=0x%05X, dummy_len=0x%05X, data_len=0x%05X, residual_len=0x%05X\n", head_addr, dummy_len, data_len, residual_len); + + //read xdata : step 1 + for (i = 0; i < ((dummy_len + data_len) / XDATA_SECTOR_SIZE); i++) { + //---change xdata index--- + nvt_set_page(head_addr + XDATA_SECTOR_SIZE * i); + + //---read xdata by BUS_TRANSFER_LENGTH + for (j = 0; j < (XDATA_SECTOR_SIZE / BUS_TRANSFER_LENGTH); + j++) { + //---read data--- + buf[0] = BUS_TRANSFER_LENGTH * j; + CTP_SPI_READ(ts->client, buf, BUS_TRANSFER_LENGTH + 1); + + //---copy buf to xdata_tmp--- + for (k = 0; k < BUS_TRANSFER_LENGTH; k++) { + xdata_tmp[XDATA_SECTOR_SIZE * i + + BUS_TRANSFER_LENGTH * j + k] = + buf[k + 1]; + //printk("0x%02X, 0x%04X\n", buf[k+1], (XDATA_SECTOR_SIZE*i + BUS_TRANSFER_LENGTH*j + k)); + } + } + //printk("addr=0x%05X\n", (head_addr+XDATA_SECTOR_SIZE*i)); + } + + //read xdata : step2 + if (residual_len != 0) { + //---change xdata index--- + nvt_set_page(xdata_addr + data_len - residual_len); + + //---read xdata by BUS_TRANSFER_LENGTH + for (j = 0; j < (residual_len / BUS_TRANSFER_LENGTH + 1); j++) { + //---read data--- + buf[0] = BUS_TRANSFER_LENGTH * j; + CTP_SPI_READ(ts->client, buf, BUS_TRANSFER_LENGTH + 1); + + //---copy buf to xdata_tmp--- + for (k = 0; k < BUS_TRANSFER_LENGTH; k++) { + xdata_tmp[(dummy_len + data_len - residual_len) + + BUS_TRANSFER_LENGTH * j + k] = + buf[k + 1]; + //printk("0x%02X, 0x%04x\n", buf[k+1], ((dummy_len+data_len-residual_len) + BUS_TRANSFER_LENGTH*j + k)); + } + } + //printk("addr=0x%05X\n", (xdata_addr+data_len-residual_len)); + } + + //---remove dummy data and 2bytes-to-1data--- + for (i = 0; i < (data_len / 2); i++) { + xdata[i] = (int16_t)(xdata_tmp[dummy_len + i * 2] + + 256 * xdata_tmp[dummy_len + i * 2 + 1]); + } + +#if TOUCH_KEY_NUM > 0 + //read button xdata : step3 + //---change xdata index--- + nvt_set_page(xdata_btn_addr); + + //---read data--- + buf[0] = (xdata_btn_addr & 0xFF); + CTP_SPI_READ(ts->client, buf, (TOUCH_KEY_NUM * 2 + 1)); + + //---2bytes-to-1data--- + for (i = 0; i < TOUCH_KEY_NUM; i++) { + xdata[ts->x_num * ts->y_num + i] = + (int16_t)(buf[1 + i * 2] + 256 * buf[1 + i * 2 + 1]); + } +#endif + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); +} + +/******************************************************* +Description: + Novatek touchscreen get meta data function. + +return: + n.a. +*******************************************************/ +void nvt_get_mdata(int32_t *buf, uint8_t *m_x_num, uint8_t *m_y_num) +{ + *m_x_num = ts->x_num; + *m_y_num = ts->y_num; + memcpy(buf, xdata, + ((ts->x_num * ts->y_num + TOUCH_KEY_NUM) * sizeof(int32_t))); +} + +/******************************************************* +Description: + Novatek touchscreen read and get number of meta data function. + +return: + n.a. +*******************************************************/ +void nvt_read_get_num_mdata(uint32_t xdata_addr, int32_t *buffer, uint32_t num) +{ + int32_t i = 0; + int32_t j = 0; + int32_t k = 0; + uint8_t buf[BUS_TRANSFER_LENGTH + 2] = { 0 }; + uint32_t head_addr = 0; + int32_t dummy_len = 0; + int32_t data_len = 0; + int32_t residual_len = 0; + + //---set xdata sector address & length--- + head_addr = xdata_addr - (xdata_addr % XDATA_SECTOR_SIZE); + dummy_len = xdata_addr - head_addr; + data_len = num * 2; + residual_len = (head_addr + dummy_len + data_len) % XDATA_SECTOR_SIZE; + + //printk("head_addr=0x%05X, dummy_len=0x%05X, data_len=0x%05X, residual_len=0x%05X\n", head_addr, dummy_len, data_len, residual_len); + + //read xdata : step 1 + for (i = 0; i < ((dummy_len + data_len) / XDATA_SECTOR_SIZE); i++) { + //---change xdata index--- + nvt_set_page(head_addr + XDATA_SECTOR_SIZE * i); + + //---read xdata by BUS_TRANSFER_LENGTH + for (j = 0; j < (XDATA_SECTOR_SIZE / BUS_TRANSFER_LENGTH); + j++) { + //---read data--- + buf[0] = BUS_TRANSFER_LENGTH * j; + CTP_SPI_READ(ts->client, buf, BUS_TRANSFER_LENGTH + 1); + + //---copy buf to xdata_tmp--- + for (k = 0; k < BUS_TRANSFER_LENGTH; k++) { + xdata_tmp[XDATA_SECTOR_SIZE * i + + BUS_TRANSFER_LENGTH * j + k] = + buf[k + 1]; + //printk("0x%02X, 0x%04X\n", buf[k+1], (XDATA_SECTOR_SIZE*i + BUS_TRANSFER_LENGTH*j + k)); + } + } + //printk("addr=0x%05X\n", (head_addr+XDATA_SECTOR_SIZE*i)); + } + + //read xdata : step2 + if (residual_len != 0) { + //---change xdata index--- + nvt_set_page(xdata_addr + data_len - residual_len); + + //---read xdata by BUS_TRANSFER_LENGTH + for (j = 0; j < (residual_len / BUS_TRANSFER_LENGTH + 1); j++) { + //---read data--- + buf[0] = BUS_TRANSFER_LENGTH * j; + CTP_SPI_READ(ts->client, buf, BUS_TRANSFER_LENGTH + 1); + + //---copy buf to xdata_tmp--- + for (k = 0; k < BUS_TRANSFER_LENGTH; k++) { + xdata_tmp[(dummy_len + data_len - residual_len) + + BUS_TRANSFER_LENGTH * j + k] = + buf[k + 1]; + //printk("0x%02X, 0x%04x\n", buf[k+1], ((dummy_len+data_len-residual_len) + BUS_TRANSFER_LENGTH*j + k)); + } + } + //printk("addr=0x%05X\n", (xdata_addr+data_len-residual_len)); + } + + //---remove dummy data and 2bytes-to-1data--- + for (i = 0; i < (data_len / 2); i++) { + buffer[i] = (int16_t)(xdata_tmp[dummy_len + i * 2] + + 256 * xdata_tmp[dummy_len + i * 2 + 1]); + } + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); +} + +/******************************************************* +Description: + Novatek touchscreen firmware version show function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t c_fw_version_show(struct seq_file *m, void *v) +{ + seq_printf(m, "fw_ver=%d, x_num=%d, y_num=%d, button_num=%d\n", + ts->fw_ver, ts->x_num, ts->y_num, ts->max_button_num); + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print show + function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t c_show(struct seq_file *m, void *v) +{ + int32_t i = 0; + int32_t j = 0; + + for (i = 0; i < ts->y_num; i++) { + for (j = 0; j < ts->x_num; j++) { + seq_printf(m, "%5d, ", xdata[i * ts->x_num + j]); + } + seq_puts(m, "\n"); + } + +#if TOUCH_KEY_NUM > 0 + for (i = 0; i < TOUCH_KEY_NUM; i++) { + seq_printf(m, "%5d, ", xdata[ts->x_num * ts->y_num + i]); + } + seq_puts(m, "\n"); +#endif + + seq_printf(m, "\n\n"); + return 0; +} + +/******************************************************* +Description: + Novatek pen 1D diff xdata sequence print show + function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t c_pen_1d_diff_show(struct seq_file *m, void *v) +{ + int32_t i = 0; + + seq_printf(m, "Tip X:\n"); + for (i = 0; i < ts->x_num; i++) { + seq_printf(m, "%5d, ", xdata_pen_tip_x[i]); + } + seq_puts(m, "\n"); + seq_printf(m, "Tip Y:\n"); + for (i = 0; i < ts->y_num; i++) { + seq_printf(m, "%5d, ", xdata_pen_tip_y[i]); + } + seq_puts(m, "\n"); + seq_printf(m, "Ring X:\n"); + for (i = 0; i < ts->x_num; i++) { + seq_printf(m, "%5d, ", xdata_pen_ring_x[i]); + } + seq_puts(m, "\n"); + seq_printf(m, "Ring Y:\n"); + for (i = 0; i < ts->y_num; i++) { + seq_printf(m, "%5d, ", xdata_pen_ring_y[i]); + } + seq_puts(m, "\n"); + + seq_printf(m, "\n\n"); + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print start + function. + +return: + Executive outcomes. 1---call next function. + NULL---not call next function and sequence loop + stop. +*******************************************************/ +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print next + function. + +return: + Executive outcomes. NULL---no next and call sequence + stop function. +*******************************************************/ +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print stop + function. + +return: + n.a. +*******************************************************/ +static void c_stop(struct seq_file *m, void *v) +{ + return; +} + +const struct seq_operations nvt_fw_version_seq_ops = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_fw_version_show +}; + +const struct seq_operations nvt_seq_ops = { .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_show }; + +const struct seq_operations nvt_pen_diff_seq_ops = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_pen_1d_diff_show +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_fw_version open + function. + +return: + n.a. +*******************************************************/ +static int32_t nvt_fw_version_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("++\n"); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + return seq_open(file, &nvt_fw_version_seq_ops); +} + +static const struct file_operations nvt_fw_version_fops = { + .owner = THIS_MODULE, + .open = nvt_fw_version_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_baseline open function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_baseline_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("++\n"); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_change_mode(TEST_MODE_2); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_read_mdata(ts->mmap->BASELINE_ADDR, ts->mmap->BASELINE_BTN_ADDR); + + nvt_change_mode(NORMAL_MODE); + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + return seq_open(file, &nvt_seq_ops); +} + +static const struct file_operations nvt_baseline_fops = { + .owner = THIS_MODULE, + .open = nvt_baseline_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_raw open function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_raw_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("++\n"); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_change_mode(TEST_MODE_2); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->RAW_PIPE0_ADDR, + ts->mmap->RAW_BTN_PIPE0_ADDR); + else + nvt_read_mdata(ts->mmap->RAW_PIPE1_ADDR, + ts->mmap->RAW_BTN_PIPE1_ADDR); + + nvt_change_mode(NORMAL_MODE); + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + return seq_open(file, &nvt_seq_ops); +} + +static const struct file_operations nvt_raw_fops = { + .owner = THIS_MODULE, + .open = nvt_raw_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_diff open function. + +return: + Executive outcomes. 0---succeed. negative---failed. +*******************************************************/ +static int32_t nvt_diff_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("++\n"); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_change_mode(TEST_MODE_2); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->DIFF_PIPE0_ADDR, + ts->mmap->DIFF_BTN_PIPE0_ADDR); + else + nvt_read_mdata(ts->mmap->DIFF_PIPE1_ADDR, + ts->mmap->DIFF_BTN_PIPE1_ADDR); + + nvt_change_mode(NORMAL_MODE); + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + return seq_open(file, &nvt_seq_ops); +} + +static const struct file_operations nvt_diff_fops = { + .owner = THIS_MODULE, + .open = nvt_diff_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_pen_diff open function. + +return: + Executive outcomes. 0---succeed. negative---failed. +*******************************************************/ +static int32_t nvt_pen_diff_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("++\n"); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_set_pen_inband_mode_1(0xFF, 0x00)) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN)) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_change_mode(TEST_MODE_2); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_read_get_num_mdata(ts->mmap->PEN_1D_DIFF_TIP_X_ADDR, + xdata_pen_tip_x, ts->x_num); + nvt_read_get_num_mdata(ts->mmap->PEN_1D_DIFF_TIP_Y_ADDR, + xdata_pen_tip_y, ts->y_num); + nvt_read_get_num_mdata(ts->mmap->PEN_1D_DIFF_RING_X_ADDR, + xdata_pen_ring_x, ts->x_num); + nvt_read_get_num_mdata(ts->mmap->PEN_1D_DIFF_RING_Y_ADDR, + xdata_pen_ring_y, ts->y_num); + + nvt_change_mode(NORMAL_MODE); + + nvt_set_pen_normal_mode(); + + nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN); + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + return seq_open(file, &nvt_pen_diff_seq_ops); +} + +static const struct file_operations nvt_pen_diff_fops = { + .owner = THIS_MODULE, + .open = nvt_pen_diff_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int nvt_xiaomi_lockdown_info_show(struct seq_file *m, void *v) +{ + u8 *lk = ts->lockdown_info; + + seq_printf(m, + "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + lk[0], lk[1], lk[2], lk[3], lk[4], lk[5], lk[6], lk[7]); + return 0; +} + +static int32_t nvt_xiaomi_lockdown_info_open(struct inode *inode, + struct file *file) +{ + return single_open(file, nvt_xiaomi_lockdown_info_show, NULL); +} + +static const struct file_operations nvt_xiaomi_lockdown_info_fops = { + .owner = THIS_MODULE, + .open = nvt_xiaomi_lockdown_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +int32_t nvt_set_pocket_palm_switch(uint8_t pocket_palm_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("set pocket palm switch: %d\n", pocket_palm_switch); + + msleep(35); + + /* ---set xdata index to EVENT BUF ADDR--- */ + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_pocket_palm_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + if (pocket_palm_switch == 0) { + /* pocket palm disable */ + buf[1] = 0x74; + } else if (pocket_palm_switch == 1) { + /* pocket palm enable */ + buf[1] = 0x73; + } else { + NVT_ERR("Invalid value! pocket_palm_switch = %d\n", + pocket_palm_switch); + ret = -EINVAL; + goto nvt_set_pocket_palm_switch_out; + } + ret = CTP_SPI_WRITE(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Write pocket palm switch command fail!\n"); + goto nvt_set_pocket_palm_switch_out; + } + +nvt_set_pocket_palm_switch_out: + NVT_LOG("%s --\n", __func__); + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_pf_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_pf_switch(uint8_t pf_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set pf switch: %d\n", pf_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_pf_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x70; + buf[2] = pf_switch; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write pf switch command fail!\n"); + goto nvt_set_pf_switch_out; + } + +nvt_set_pf_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_pf_switch(uint8_t *pf_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5D); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_pf_switch_out; + } + + buf[0] = 0x5D; + buf[1] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Read pf switch status fail!\n"); + goto nvt_get_pf_switch_out; + } + + *pf_switch = (buf[1] & 0x07); + NVT_LOG("pf_switch = %d\n", *pf_switch); + +nvt_get_pf_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_pf_switch_proc_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t pf_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_pf_switch(&pf_switch); + + mutex_unlock(&ts->lock); + + //cnt = snprintf(buf, PAGE_SIZE - len, "pf_switch: %d\n", pf_switch); + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "pf_switch: %d\n", pf_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_pf_switch_proc_write(struct file *filp, + const char __user *buf, size_t count, + loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t pf_switch; + char *tmp_buf; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value! count = %zu\n", count); + ret = -EINVAL; + goto out; + } + + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value! ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + if (tmp < 0 || tmp > 4) { + NVT_ERR("Invalid value! tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + pf_switch = (uint8_t)tmp; + NVT_LOG("pf_switch = %d\n", pf_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_pf_switch(pf_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_pf_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_pf_switch_proc_read, + .write = nvt_pf_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_sensitivity_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_sensitivity_switch(uint8_t sensitivity_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set sensitivity switch: %d\n", sensitivity_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_sensitivity_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x71; + buf[2] = sensitivity_switch; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write sensitivity switch command fail!\n"); + goto nvt_set_sensitivity_switch_out; + } + +nvt_set_sensitivity_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_sensitivity_switch(uint8_t *sensitivity_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5D); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_sensitivity_switch_out; + } + + buf[0] = 0x5D; + buf[1] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Read sensitivity switch status fail!\n"); + goto nvt_get_sensitivity_switch_out; + } + + *sensitivity_switch = ((buf[1] >> 3) & 0x07); + NVT_LOG("sensitivity_switch = %d\n", *sensitivity_switch); + +nvt_get_sensitivity_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_sensitivity_switch_proc_read(struct file *filp, + char __user *buf, size_t count, + loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t sensitivity_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_sensitivity_switch(&sensitivity_switch); + + mutex_unlock(&ts->lock); + + //cnt = snprintf(buf, PAGE_SIZE - len, "sensitivity_switch: %d\n", sensitivity_switch); + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "sensitivity_switch: %d\n", + sensitivity_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_sensitivity_switch_proc_write(struct file *filp, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t sensitivity_switch; + char *tmp_buf; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value! count = %zu\n", count); + ret = -EINVAL; + goto out; + } + + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value! ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + if (tmp < 0 || tmp > 4) { + NVT_ERR("Invalid value! tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + sensitivity_switch = (uint8_t)tmp; + NVT_LOG("sensitivity_switch = %d\n", sensitivity_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_sensitivity_switch(sensitivity_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_sensitivity_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_sensitivity_switch_proc_read, + .write = nvt_sensitivity_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_er_range_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_er_range_switch(uint8_t er_range_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set er range switch: %d\n", er_range_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_er_range_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x72; + buf[2] = er_range_switch; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write er range switch command fail!\n"); + goto nvt_set_er_range_switch_out; + } + +nvt_set_er_range_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_er_range_switch(uint8_t *er_range_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5D); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_er_range_switch_out; + } + + buf[0] = 0x5D; + buf[1] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Read er range switch status fail!\n"); + goto nvt_get_er_range_switch_out; + } + + *er_range_switch = ((buf[1] >> 6) & 0x03); + NVT_LOG("er_range_switch = %d\n", *er_range_switch); + +nvt_get_er_range_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_er_range_switch_proc_read(struct file *filp, + char __user *buf, size_t count, + loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t er_range_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_er_range_switch(&er_range_switch); + + mutex_unlock(&ts->lock); + + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "er_range_switch: %d\n", + er_range_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_er_range_switch_proc_write(struct file *filp, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t er_range_switch; + char *tmp_buf = 0; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value! count = %zu\n", count); + ret = -EINVAL; + goto out; + } + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value! ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + + if (tmp < 0 || tmp > 3) { + NVT_ERR("Invalid value! tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + er_range_switch = (uint8_t)tmp; + NVT_LOG("er_range_switch = %d\n", er_range_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_er_range_switch(er_range_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_er_range_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_er_range_switch_proc_read, + .write = nvt_er_range_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_edge_reject_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_edge_reject_switch(uint8_t edge_reject_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set edge reject switch: %d\n", edge_reject_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_edge_reject_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + if (edge_reject_switch == 1) { + // vertical + buf[1] = 0xBA; + } else if (edge_reject_switch == 2) { + // left up + buf[1] = 0xBB; + } else if (edge_reject_switch == 3) { + // righ up + buf[1] = 0xBC; + } else { + NVT_ERR("Invalid value! edge_reject_switch = %d\n", + edge_reject_switch); + ret = -EINVAL; + goto nvt_set_edge_reject_switch_out; + } + ret = CTP_SPI_WRITE(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Write edge reject switch command fail!\n"); + goto nvt_set_edge_reject_switch_out; + } + +nvt_set_edge_reject_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_edge_reject_switch(uint8_t *edge_reject_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5C); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_edge_reject_switch_out; + } + + buf[0] = 0x5C; + buf[1] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Read edge reject switch status fail!\n"); + goto nvt_get_edge_reject_switch_out; + } + + *edge_reject_switch = ((buf[1] >> 5) & 0x03); + NVT_LOG("edge_reject_switch = %d\n", *edge_reject_switch); + +nvt_get_edge_reject_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_edge_reject_switch_proc_read(struct file *filp, + char __user *buf, size_t count, + loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t edge_reject_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_edge_reject_switch(&edge_reject_switch); + + mutex_unlock(&ts->lock); + + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "edge_reject_switch: %d\n", + edge_reject_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_edge_reject_switch_proc_write(struct file *filp, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t edge_reject_switch; + char *tmp_buf = 0; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value! count = %zu\n", count); + ret = -EINVAL; + goto out; + } + + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value! ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + + if (tmp < 1 || tmp > 3) { + NVT_ERR("Invalid value! tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + edge_reject_switch = (uint8_t)tmp; + NVT_LOG("edge_reject_switch = %d\n", edge_reject_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_edge_reject_switch(edge_reject_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_edge_reject_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_edge_reject_switch_proc_read, + .write = nvt_edge_reject_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_hand_only_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_hand_only_switch(uint8_t hand_only_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set hand only switch: %d\n", hand_only_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_hand_only_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x77; + buf[2] = hand_only_switch; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write hand only switch command fail!\n"); + goto nvt_set_hand_only_switch_out; + } + +nvt_set_hand_only_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_hand_only_switch(uint8_t *hand_only_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5E); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_hand_only_switch_out; + } + + buf[0] = 0x5E; + buf[1] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Read hand only switch status fail!\n"); + goto nvt_get_hand_only_switch_out; + } + + *hand_only_switch = ((buf[1] >> 2) & 0x01); + NVT_LOG("hand_only_switch = %d\n", *hand_only_switch); + +nvt_get_hand_only_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_hand_only_switch_proc_read(struct file *filp, + char __user *buf, size_t count, + loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t hand_only_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_hand_only_switch(&hand_only_switch); + + mutex_unlock(&ts->lock); + + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "hand_only_switch: %d\n", + hand_only_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_hand_only_switch_proc_write(struct file *filp, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t hand_only_switch; + char *tmp_buf; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value!, count = %zu\n", count); + ret = -EINVAL; + goto out; + } + + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value!, ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + if ((tmp < 0) || (tmp > 1)) { + NVT_ERR("Invalid value!, tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + hand_only_switch = (uint8_t)tmp; + NVT_LOG("hand_only_switch = %d\n", hand_only_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_hand_only_switch(hand_only_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_hand_only_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_hand_only_switch_proc_read, + .write = nvt_hand_only_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_drag_latency_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_drag_latency_switch(uint8_t drag_latency_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set drag latency switch: %d\n", drag_latency_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_drag_latency_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x78; + buf[2] = drag_latency_switch; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write drag_latency switch command fail!\n"); + goto nvt_set_drag_latency_switch_out; + } + +nvt_set_drag_latency_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_drag_latency_switch(uint8_t *drag_latency_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5E); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_drag_latency_switch_out; + } + + buf[0] = 0x5E; + buf[1] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Read drag_latency switch status fail!\n"); + goto nvt_get_drag_latency_switch_out; + } + + *drag_latency_switch = ((buf[1] >> 3) & 0x07); + NVT_LOG("drag_latency_switch = %d\n", *drag_latency_switch); + +nvt_get_drag_latency_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_drag_latency_switch_proc_read(struct file *filp, + char __user *buf, size_t count, + loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t drag_latency_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_drag_latency_switch(&drag_latency_switch); + + mutex_unlock(&ts->lock); + + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "drag_latency_switch: %d\n", + drag_latency_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_drag_latency_switch_proc_write(struct file *filp, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t drag_latency_switch; + char *tmp_buf; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value! count = %zu\n", count); + ret = -EINVAL; + goto out; + } + + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value! ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + if (tmp < 0 || tmp > 4) { + NVT_ERR("Invalid value! tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + drag_latency_switch = (uint8_t)tmp; + NVT_LOG("drag_latency_switch = %d\n", drag_latency_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_drag_latency_switch(drag_latency_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_drag_latency_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_drag_latency_switch_proc_read, + .write = nvt_drag_latency_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_small_jitter_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_small_jitter_switch(uint8_t small_jitter_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set small jitter switch: %d\n", small_jitter_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_small_jitter_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x79; + buf[2] = small_jitter_switch; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write small jitter switch command fail!\n"); + goto nvt_set_small_jitter_switch_out; + } + +nvt_set_small_jitter_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_small_jitter_switch(uint8_t *small_jitter_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5E); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_small_jitter_switch_out; + } + + buf[0] = 0x5E; + buf[1] = 0x00; + buf[2] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Read small jitter switch status fail!\n"); + goto nvt_get_small_jitter_switch_out; + } + + *small_jitter_switch = + (((buf[2] & 0x01) << 2) | ((buf[1] >> 6) & 0x03)); + NVT_LOG("small_jitter_switch = %d\n", *small_jitter_switch); + +nvt_get_small_jitter_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_small_jitter_switch_proc_read(struct file *filp, + char __user *buf, size_t count, + loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t small_jitter_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_small_jitter_switch(&small_jitter_switch); + + mutex_unlock(&ts->lock); + + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "small_jitter_switch: %d\n", + small_jitter_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_small_jitter_switch_proc_write(struct file *filp, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t small_jitter_switch; + char *tmp_buf; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value! count = %zu\n", count); + ret = -EINVAL; + goto out; + } + + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value! ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + if (tmp < 0 || tmp > 4) { + NVT_ERR("Invalid value! tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + small_jitter_switch = (uint8_t)tmp; + NVT_LOG("small_jitter_switch = %d\n", small_jitter_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_small_jitter_switch(small_jitter_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_small_jitter_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_small_jitter_switch_proc_read, + .write = nvt_small_jitter_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_game_mode_switch function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +int32_t nvt_set_game_mode_switch(uint8_t game_mode_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + NVT_LOG("set game mode switch: %d\n", game_mode_switch); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_game_mode_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x7A; + buf[2] = game_mode_switch; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write game mode switch command fail!\n"); + goto nvt_set_game_mode_switch_out; + } + +nvt_set_game_mode_switch_out: + NVT_LOG("--\n"); + return ret; +} + +int32_t nvt_get_game_mode_switch(uint8_t *game_mode_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + + msleep(35); + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x5F); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_get_game_mode_switch_out; + } + + buf[0] = 0x5F; + buf[1] = 0x00; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Read game mode switch status fail!\n"); + goto nvt_get_game_mode_switch_out; + } + + *game_mode_switch = ((buf[1] >> 1) & 0x01); + NVT_LOG("game_mode_switch = %d\n", *game_mode_switch); + +nvt_get_game_mode_switch_out: + NVT_LOG("--\n"); + return ret; +} + +static ssize_t nvt_game_mode_switch_proc_read(struct file *filp, + char __user *buf, size_t count, + loff_t *f_pos) +{ + static int finished; + int32_t cnt = 0; + int32_t len = 0; + uint8_t game_mode_switch; + char tmp_buf[64]; + + NVT_LOG("++\n"); + + /* + * We return 0 to indicate end of file, that we have + * no more information. Otherwise, processes will + * continue to read from us in an endless loop. + */ + if (finished) { + NVT_LOG("read END\n"); + finished = 0; + return 0; + } + finished = 1; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_get_game_mode_switch(&game_mode_switch); + + mutex_unlock(&ts->lock); + + cnt = snprintf(tmp_buf, sizeof(tmp_buf), "game_mode_switch: %d\n", + game_mode_switch); + if (copy_to_user(buf, tmp_buf, sizeof(tmp_buf))) { + NVT_ERR("copy_to_user() error!\n"); + return -EFAULT; + } + buf += cnt; + len += cnt; + + NVT_LOG("--\n"); + return len; +} + +static ssize_t nvt_game_mode_switch_proc_write(struct file *filp, + const char __user *buf, + size_t count, loff_t *f_pos) +{ + int32_t ret; + int32_t tmp; + uint8_t game_mode_switch; + char *tmp_buf; + + NVT_LOG("++\n"); + + if (count == 0 || count > 2) { + NVT_ERR("Invalid value!, count = %zu\n", count); + ret = -EINVAL; + goto out; + } + + tmp_buf = kzalloc((count + 1), GFP_KERNEL); + if (!tmp_buf) { + NVT_ERR("Allocate tmp_buf fail!\n"); + ret = -ENOMEM; + goto out; + } + if (copy_from_user(tmp_buf, buf, count)) { + NVT_ERR("copy_from_user() error!\n"); + ret = -EFAULT; + goto out; + } + ret = sscanf(tmp_buf, "%d", &tmp); + if (ret != 1) { + NVT_ERR("Invalid value!, ret = %d\n", ret); + ret = -EINVAL; + goto out; + } + if ((tmp < 0) || (tmp > 1)) { + NVT_ERR("Invalid value!, tmp = %d\n", tmp); + ret = -EINVAL; + goto out; + } + game_mode_switch = (uint8_t)tmp; + NVT_LOG("game_mode_switch = %d\n", game_mode_switch); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + nvt_set_game_mode_switch(game_mode_switch); + + mutex_unlock(&ts->lock); + + ret = count; +out: + if (tmp_buf) + kfree(tmp_buf); + NVT_LOG("--\n"); + return ret; +} + +static const struct file_operations nvt_game_mode_switch_fops = { + .owner = THIS_MODULE, + .read = nvt_game_mode_switch_proc_read, + .write = nvt_game_mode_switch_proc_write, +}; + +/******************************************************* +Description: + Novatek touchscreen extra function proc. file node + initial function. + +return: + Executive outcomes. 0---succeed. -12---failed. +*******************************************************/ +int32_t nvt_extra_proc_init(void) +{ + NVT_proc_fw_version_entry = + proc_create(NVT_FW_VERSION, 0444, NULL, &nvt_fw_version_fops); + if (NVT_proc_fw_version_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_FW_VERSION); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_FW_VERSION); + } + + NVT_proc_baseline_entry = + proc_create(NVT_BASELINE, 0444, NULL, &nvt_baseline_fops); + if (NVT_proc_baseline_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_BASELINE); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_BASELINE); + } + + NVT_proc_raw_entry = proc_create(NVT_RAW, 0444, NULL, &nvt_raw_fops); + if (NVT_proc_raw_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_RAW); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_RAW); + } + + NVT_proc_diff_entry = proc_create(NVT_DIFF, 0444, NULL, &nvt_diff_fops); + if (NVT_proc_diff_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_DIFF); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_DIFF); + } + + if (ts->pen_support) { + NVT_proc_pen_diff_entry = proc_create(NVT_PEN_DIFF, 0444, NULL, + &nvt_pen_diff_fops); + if (NVT_proc_pen_diff_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_PEN_DIFF); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_PEN_DIFF); + } + } + + NVT_proc_pf_switch_entry = + proc_create(NVT_PF_SWITCH, 0666, NULL, &nvt_pf_switch_fops); + if (NVT_proc_pf_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_PF_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_PF_SWITCH); + } + + NVT_proc_sensitivity_switch_entry = + proc_create(NVT_SENSITIVITY_SWITCH, 0666, NULL, + &nvt_sensitivity_switch_fops); + if (NVT_proc_sensitivity_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_SENSITIVITY_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_SENSITIVITY_SWITCH); + } + + NVT_proc_er_range_switch_entry = proc_create( + NVT_ER_RANGE_SWITCH, 0666, NULL, &nvt_er_range_switch_fops); + if (NVT_proc_er_range_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_ER_RANGE_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_ER_RANGE_SWITCH); + } + + NVT_proc_edge_reject_switch_entry = + proc_create(NVT_EDGE_REJECT_SWITCH, 0666, NULL, + &nvt_edge_reject_switch_fops); + if (NVT_proc_edge_reject_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_EDGE_REJECT_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_EDGE_REJECT_SWITCH); + } + + NVT_proc_hand_only_switch_entry = proc_create( + NVT_HAND_ONLY_SWITCH, 0666, NULL, &nvt_hand_only_switch_fops); + if (NVT_proc_hand_only_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_HAND_ONLY_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_HAND_ONLY_SWITCH); + } + + NVT_proc_drag_latency_switch_entry = + proc_create(NVT_DRAG_LATENCY_SWITCH, 0666, NULL, + &nvt_drag_latency_switch_fops); + if (NVT_proc_drag_latency_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_DRAG_LATENCY_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_DRAG_LATENCY_SWITCH); + } + + NVT_proc_small_jitter_switch_entry = + proc_create(NVT_SMALL_JITTER_SWITCH, 0666, NULL, + &nvt_small_jitter_switch_fops); + if (NVT_proc_small_jitter_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_SMALL_JITTER_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_SMALL_JITTER_SWITCH); + } + + NVT_proc_game_mode_switch_entry = proc_create( + NVT_GAME_MODE_SWITCH, 0666, NULL, &nvt_game_mode_switch_fops); + if (NVT_proc_game_mode_switch_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_GAME_MODE_SWITCH); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_GAME_MODE_SWITCH); + } + + NVT_proc_xiaomi_lockdown_info_entry = + proc_create(NVT_XIAOMI_LOCKDOWN_INFO, 0444, NULL, + &nvt_xiaomi_lockdown_info_fops); + if (NVT_proc_xiaomi_lockdown_info_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_XIAOMI_LOCKDOWN_INFO); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", + NVT_XIAOMI_LOCKDOWN_INFO); + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen extra function proc. file node + deinitial function. + +return: + n.a. +*******************************************************/ +void nvt_extra_proc_deinit(void) +{ + if (NVT_proc_fw_version_entry != NULL) { + remove_proc_entry(NVT_FW_VERSION, NULL); + NVT_proc_fw_version_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_FW_VERSION); + } + + if (NVT_proc_baseline_entry != NULL) { + remove_proc_entry(NVT_BASELINE, NULL); + NVT_proc_baseline_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_BASELINE); + } + + if (NVT_proc_raw_entry != NULL) { + remove_proc_entry(NVT_RAW, NULL); + NVT_proc_raw_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_RAW); + } + + if (NVT_proc_diff_entry != NULL) { + remove_proc_entry(NVT_DIFF, NULL); + NVT_proc_diff_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_DIFF); + } + + if (ts->pen_support) { + if (NVT_proc_pen_diff_entry != NULL) { + remove_proc_entry(NVT_PEN_DIFF, NULL); + NVT_proc_pen_diff_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_PEN_DIFF); + } + } + + if (NVT_proc_pf_switch_entry != NULL) { + remove_proc_entry(NVT_PF_SWITCH, NULL); + NVT_proc_pf_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_PF_SWITCH); + } + + if (NVT_proc_sensitivity_switch_entry != NULL) { + remove_proc_entry(NVT_SENSITIVITY_SWITCH, NULL); + NVT_proc_sensitivity_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_SENSITIVITY_SWITCH); + } + + if (NVT_proc_er_range_switch_entry != NULL) { + remove_proc_entry(NVT_ER_RANGE_SWITCH, NULL); + NVT_proc_er_range_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_ER_RANGE_SWITCH); + } + + if (NVT_proc_edge_reject_switch_entry != NULL) { + remove_proc_entry(NVT_EDGE_REJECT_SWITCH, NULL); + NVT_proc_edge_reject_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_EDGE_REJECT_SWITCH); + } + + if (NVT_proc_hand_only_switch_entry != NULL) { + remove_proc_entry(NVT_HAND_ONLY_SWITCH, NULL); + NVT_proc_hand_only_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_HAND_ONLY_SWITCH); + } + + if (NVT_proc_drag_latency_switch_entry != NULL) { + remove_proc_entry(NVT_DRAG_LATENCY_SWITCH, NULL); + NVT_proc_drag_latency_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_DRAG_LATENCY_SWITCH); + } + + if (NVT_proc_small_jitter_switch_entry != NULL) { + remove_proc_entry(NVT_SMALL_JITTER_SWITCH, NULL); + NVT_proc_small_jitter_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_SMALL_JITTER_SWITCH); + } + + if (NVT_proc_game_mode_switch_entry != NULL) { + remove_proc_entry(NVT_GAME_MODE_SWITCH, NULL); + NVT_proc_game_mode_switch_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_GAME_MODE_SWITCH); + } +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_fw_update.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_fw_update.c new file mode 100644 index 000000000000..a721ec364c13 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_fw_update.c @@ -0,0 +1,1110 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * $Revision: 68983 $ + * $Date: 2020-09-17 09:43:23 +0800 (週四, 17 ä¹æœˆ 2020) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include + +#include "nt36xxx.h" + +#if BOOT_UPDATE_FIRMWARE + +#define SIZE_4KB 4096 +#define FLASH_SECTOR_SIZE SIZE_4KB +#define FW_BIN_VER_OFFSET (fw_need_write_size - SIZE_4KB) +#define FW_BIN_VER_BAR_OFFSET (FW_BIN_VER_OFFSET + 1) +#define NVT_FLASH_END_FLAG_LEN 3 +#define NVT_FLASH_END_FLAG_ADDR (fw_need_write_size - NVT_FLASH_END_FLAG_LEN) + +#define NVT_DUMP_PARTITION (0) +#define NVT_DUMP_PARTITION_LEN (1024) +#define NVT_DUMP_PARTITION_PATH "/data/local/tmp" + +static ktime_t start, end; +const struct firmware *fw_entry = NULL; +static size_t fw_need_write_size = 0; +static uint8_t *fwbuf = NULL; + +struct nvt_ts_bin_map { + char name[12]; + uint32_t BIN_addr; + uint32_t SRAM_addr; + uint32_t size; + uint32_t crc; +}; + +static struct nvt_ts_bin_map *bin_map; + +static int32_t nvt_get_fw_need_write_size(const struct firmware *fw_entry) +{ + int32_t i = 0; + int32_t total_sectors_to_check = 0; + + total_sectors_to_check = fw_entry->size / FLASH_SECTOR_SIZE; + /* printk("total_sectors_to_check = %d\n", total_sectors_to_check); */ + + for (i = total_sectors_to_check; i > 0; i--) { + /* printk("current end flag address checked = 0x%X\n", i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN); */ + /* check if there is end flag "NVT" at the end of this sector */ + if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - + NVT_FLASH_END_FLAG_LEN], + "NVT", NVT_FLASH_END_FLAG_LEN) == 0) { + fw_need_write_size = i * FLASH_SECTOR_SIZE; + NVT_LOG("fw_need_write_size = %zu(0x%zx), NVT end flag\n", + fw_need_write_size, fw_need_write_size); + return 0; + } + + /* check if there is end flag "MOD" at the end of this sector */ + if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - + NVT_FLASH_END_FLAG_LEN], + "MOD", NVT_FLASH_END_FLAG_LEN) == 0) { + fw_need_write_size = i * FLASH_SECTOR_SIZE; + NVT_LOG("fw_need_write_size = %zu(0x%zx), MOD end flag\n", + fw_need_write_size, fw_need_write_size); + return 0; + } + } + + NVT_ERR("end flag \"NVT\" \"MOD\" not found!\n"); + return -1; +} + +/******************************************************* +Description: + Novatek touchscreen init variable and allocate buffer +for download firmware function. + +return: + n.a. +*******************************************************/ +static int32_t nvt_download_init(void) +{ + /* allocate buffer for transfer firmware */ + //NVT_LOG("NVT_TRANSFER_LEN = 0x%06X\n", NVT_TRANSFER_LEN); + + if (fwbuf == NULL) { + fwbuf = (uint8_t *)kzalloc((NVT_TRANSFER_LEN + 1 + DUMMY_BYTES), + GFP_KERNEL); + if (fwbuf == NULL) { + NVT_ERR("kzalloc for fwbuf failed!\n"); + return -ENOMEM; + } + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen checksum function. Calculate bin +file checksum for comparison. + +return: + n.a. +*******************************************************/ +static uint32_t CheckSum(const u8 *data, size_t len) +{ + uint32_t i = 0; + uint32_t checksum = 0; + + for (i = 0; i < len + 1; i++) + checksum += data[i]; + + checksum += len; + checksum = ~checksum + 1; + + return checksum; +} + +static uint32_t byte_to_word(const uint8_t *data) +{ + return data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24); +} + +/******************************************************* +Description: + Novatek touchscreen parsing bin header function. + +return: + n.a. +*******************************************************/ +static uint32_t partition = 0; +static uint8_t ilm_dlm_num = 2; +static uint8_t cascade_2nd_header_info = 0; +static int32_t nvt_bin_header_parser(const u8 *fwdata, size_t fwsize) +{ + uint32_t list = 0; + uint32_t pos = 0x00; + uint32_t end = 0x00; + uint8_t info_sec_num = 0; + uint8_t ovly_sec_num = 0; + uint8_t ovly_info = 0; + uint8_t find_bin_header = 0; + + /* Find the header size */ + end = fwdata[0] + (fwdata[1] << 8) + (fwdata[2] << 16) + + (fwdata[3] << 24); + + /* check cascade next header */ + cascade_2nd_header_info = (fwdata[0x20] & 0x02) >> 1; + NVT_LOG("cascade_2nd_header_info = %d\n", cascade_2nd_header_info); + + if (cascade_2nd_header_info) { + pos = 0x30; // info section start at 0x30 offset + while (pos < (end / 2)) { + info_sec_num++; + pos += 0x10; /* each header info is 16 bytes */ + } + + info_sec_num = info_sec_num + 1; //next header section + } else { + pos = 0x30; // info section start at 0x30 offset + while (pos < end) { + info_sec_num++; + pos += 0x10; /* each header info is 16 bytes */ + } + } + + /* + * Find the DLM OVLY section + * [0:3] Overlay Section Number + * [4] Overlay Info + */ + ovly_info = (fwdata[0x28] & 0x10) >> 4; + ovly_sec_num = (ovly_info) ? (fwdata[0x28] & 0x0F) : 0; + + /* + * calculate all partition number + * ilm_dlm_num (ILM & DLM) + ovly_sec_num + info_sec_num + */ + partition = ilm_dlm_num + ovly_sec_num + info_sec_num; + NVT_LOG("ovly_info = %d, ilm_dlm_num = %d, ovly_sec_num = %d, info_sec_num = %d, partition = %d\n", + ovly_info, ilm_dlm_num, ovly_sec_num, info_sec_num, partition); + + /* allocated memory for header info */ + bin_map = (struct nvt_ts_bin_map *)kzalloc( + (partition + 1) * sizeof(struct nvt_ts_bin_map), GFP_KERNEL); + if (bin_map == NULL) { + NVT_ERR("kzalloc for bin_map failed!\n"); + return -ENOMEM; + } + + for (list = 0; list < partition; list++) { + /* + * [1] parsing ILM & DLM header info + * BIN_addr : SRAM_addr : size (12-bytes) + * crc located at 0x18 & 0x1C + */ + if (list < ilm_dlm_num) { + bin_map[list].BIN_addr = + byte_to_word(&fwdata[0 + list * 12]); + bin_map[list].SRAM_addr = + byte_to_word(&fwdata[4 + list * 12]); + bin_map[list].size = + byte_to_word(&fwdata[8 + list * 12]); + if (ts->hw_crc) + bin_map[list].crc = + byte_to_word(&fwdata[0x18 + list * 4]); + else { //ts->hw_crc + if ((bin_map[list].BIN_addr + + bin_map[list].size) < fwsize) + bin_map[list].crc = CheckSum( + &fwdata[bin_map[list].BIN_addr], + bin_map[list].size); + else { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + + bin_map[list].size); + return -EINVAL; + } + } //ts->hw_crc + if (list == 0) + sprintf(bin_map[list].name, "ILM"); + else if (list == 1) + sprintf(bin_map[list].name, "DLM"); + } + + /* + * [2] parsing others header info + * SRAM_addr : size : BIN_addr : crc (16-bytes) + */ + if ((list >= ilm_dlm_num) && + (list < (ilm_dlm_num + info_sec_num))) { + if (find_bin_header == 0) { + /* others partition located at 0x30 offset */ + pos = 0x30 + (0x10 * (list - ilm_dlm_num)); + } else if (find_bin_header && cascade_2nd_header_info) { + /* cascade 2nd header info */ + pos = end - 0x10; + } + + bin_map[list].SRAM_addr = byte_to_word(&fwdata[pos]); + bin_map[list].size = byte_to_word(&fwdata[pos + 4]); + bin_map[list].BIN_addr = byte_to_word(&fwdata[pos + 8]); + if (ts->hw_crc) + bin_map[list].crc = + byte_to_word(&fwdata[pos + 12]); + else { //ts->hw_crc + if ((bin_map[list].BIN_addr + + bin_map[list].size) < fwsize) + bin_map[list].crc = CheckSum( + &fwdata[bin_map[list].BIN_addr], + bin_map[list].size); + else { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + + bin_map[list].size); + return -EINVAL; + } + } //ts->hw_crc + /* detect header end to protect parser function */ + if ((bin_map[list].BIN_addr < end) && + (bin_map[list].size != 0)) { + sprintf(bin_map[list].name, "Header"); + find_bin_header = 1; + } else { + sprintf(bin_map[list].name, "Info-%d", + (list - ilm_dlm_num)); + } + } + + /* + * [3] parsing overlay section header info + * SRAM_addr : size : BIN_addr : crc (16-bytes) + */ + if (list >= (ilm_dlm_num + info_sec_num)) { + /* overlay info located at DLM (list = 1) start addr */ + pos = bin_map[1].BIN_addr + + (0x10 * (list - ilm_dlm_num - info_sec_num)); + + bin_map[list].SRAM_addr = byte_to_word(&fwdata[pos]); + bin_map[list].size = byte_to_word(&fwdata[pos + 4]); + bin_map[list].BIN_addr = byte_to_word(&fwdata[pos + 8]); + if (ts->hw_crc) + bin_map[list].crc = + byte_to_word(&fwdata[pos + 12]); + else { //ts->hw_crc + if ((bin_map[list].BIN_addr + + bin_map[list].size) < fwsize) + bin_map[list].crc = CheckSum( + &fwdata[bin_map[list].BIN_addr], + bin_map[list].size); + else { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + + bin_map[list].size); + return -EINVAL; + } + } //ts->hw_crc + sprintf(bin_map[list].name, "Overlay-%d", + (list - ilm_dlm_num - info_sec_num)); + } + + /* BIN size error detect */ + if ((bin_map[list].BIN_addr + bin_map[list].size) > fwsize) { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + bin_map[list].size); + return -EINVAL; + } + + // NVT_LOG("[%d][%s] SRAM (0x%08X), SIZE (0x%08X), BIN (0x%08X), CRC (0x%08X)\n", + // list, bin_map[list].name, + // bin_map[list].SRAM_addr, bin_map[list].size, bin_map[list].BIN_addr, bin_map[list].crc); + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen release update firmware function. + +return: + n.a. +*******************************************************/ +static void update_firmware_release(void) +{ + if (fw_entry) { + release_firmware(fw_entry); + } + + fw_entry = NULL; +} + +/******************************************************* +Description: + Novatek touchscreen request update firmware function. + +return: + Executive outcomes. 0---succeed. -1,-22---failed. +*******************************************************/ +static int32_t update_firmware_request(const char *filename) +{ + uint8_t retry = 0; + int32_t ret = 0; + + if (NULL == filename) { + return -ENOENT; + } + + while (1) { + NVT_LOG("filename is %s\n", filename); + + ret = request_firmware(&fw_entry, filename, &ts->client->dev); + if (ret) { + NVT_ERR("firmware load failed, ret=%d\n", ret); + goto request_fail; + } + + // check FW need to write size + if (nvt_get_fw_need_write_size(fw_entry)) { + NVT_ERR("get fw need to write size fail!\n"); + ret = -EINVAL; + goto invalid; + } + + // check if FW version add FW version bar equals 0xFF + if (*(fw_entry->data + FW_BIN_VER_OFFSET) + + *(fw_entry->data + FW_BIN_VER_BAR_OFFSET) != + 0xFF) { + NVT_ERR("bin file FW_VER + FW_VER_BAR should be 0xFF!\n"); + NVT_ERR("FW_VER=0x%02X, FW_VER_BAR=0x%02X\n", + *(fw_entry->data + FW_BIN_VER_OFFSET), + *(fw_entry->data + FW_BIN_VER_BAR_OFFSET)); + ret = -ENOEXEC; + goto invalid; + } + + /* BIN Header Parser */ + ret = nvt_bin_header_parser(fw_entry->data, fw_entry->size); + if (ret) { + NVT_ERR("bin header parser failed\n"); + goto invalid; + } else { + break; + } + +invalid: + update_firmware_release(); + if (!IS_ERR_OR_NULL(bin_map)) { + kfree(bin_map); + bin_map = NULL; + } + +request_fail: + retry++; + if (unlikely(retry > 2)) { + NVT_ERR("error, retry=%d\n", retry); + break; + } + } + + return ret; +} + +#if NVT_DUMP_PARTITION +/******************************************************* +Description: + Novatek touchscreen dump flash partition function. + +return: + n.a. +*******************************************************/ +loff_t file_offset = 0; +static int32_t nvt_read_ram_and_save_file(uint32_t addr, uint16_t len, + char *name) +{ + char file[256] = ""; + uint8_t *fbufp = NULL; + int32_t ret = 0; + struct file *fp = NULL; + mm_segment_t org_fs; + + sprintf(file, "%s/dump_%s.bin", NVT_DUMP_PARTITION_PATH, name); + NVT_LOG("Dump [%s] from 0x%08X to 0x%08X\n", file, addr, addr + len); + + fbufp = (uint8_t *)kzalloc(len + 1, GFP_KERNEL); + if (fbufp == NULL) { + NVT_ERR("kzalloc for fbufp failed!\n"); + ret = -ENOMEM; + goto alloc_buf_fail; + } + + org_fs = get_fs(); + set_fs(KERNEL_DS); + fp = filp_open(file, O_RDWR | O_CREAT, 0644); + if (fp == NULL || IS_ERR(fp)) { + ret = -ENOMEM; + NVT_ERR("open file failed\n"); + goto open_file_fail; + } + + /* SPI read */ + //---set xdata index to addr--- + nvt_set_page(addr); + + fbufp[0] = addr & 0x7F; //offset + CTP_SPI_READ(ts->client, fbufp, len + 1); + + /* Write to file */ + ret = vfs_write(fp, (char __user *)fbufp + 1, len, &file_offset); + if (ret != len) { + NVT_ERR("write file failed\n"); + goto open_file_fail; + } else { + ret = 0; + } + +open_file_fail: + set_fs(org_fs); + if (!IS_ERR_OR_NULL(fp)) { + filp_close(fp, NULL); + fp = NULL; + } + + if (!IS_ERR_OR_NULL(fbufp)) { + kfree(fbufp); + fbufp = NULL; + } +alloc_buf_fail: + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen nvt_dump_partition function to dump + each partition for debug. + +return: + n.a. +*******************************************************/ +static int32_t nvt_dump_partition(void) +{ + uint32_t list = 0; + char *name; + uint32_t SRAM_addr, size; + uint32_t i = 0; + uint16_t len = 0; + int32_t count = 0; + int32_t ret = 0; + + if (NVT_DUMP_PARTITION_LEN >= sizeof(ts->rbuf)) { + NVT_ERR("dump len %d is larger than buffer size %ld\n", + NVT_DUMP_PARTITION_LEN, sizeof(ts->rbuf)); + return -EINVAL; + } else if (NVT_DUMP_PARTITION_LEN >= NVT_TRANSFER_LEN) { + NVT_ERR("dump len %d is larger than NVT_TRANSFER_LEN\n", + NVT_DUMP_PARTITION_LEN); + return -EINVAL; + } + + if (bin_map == NULL) { + NVT_ERR("bin_map is NULL\n"); + return -ENOMEM; + } + + memset(fwbuf, 0, (NVT_DUMP_PARTITION_LEN + 1)); + + for (list = 0; list < partition; list++) { + /* initialize variable */ + SRAM_addr = bin_map[list].SRAM_addr; + size = bin_map[list].size; + name = bin_map[list].name; + + /* ignore reserved partition (Reserved Partition size is zero) */ + if (!size) + continue; + else + size = size + 1; + + /* write data to SRAM */ + if (size % NVT_DUMP_PARTITION_LEN) + count = (size / NVT_DUMP_PARTITION_LEN) + 1; + else + count = (size / NVT_DUMP_PARTITION_LEN); + + for (i = 0; i < count; i++) { + len = (size < NVT_DUMP_PARTITION_LEN) ? + size : + NVT_DUMP_PARTITION_LEN; + + /* dump for debug download firmware */ + ret = nvt_read_ram_and_save_file(SRAM_addr, len, name); + if (ret < 0) { + NVT_ERR("nvt_read_ram_and_save_file failed, ret = %d\n", + ret); + goto out; + } + + SRAM_addr += NVT_DUMP_PARTITION_LEN; + size -= NVT_DUMP_PARTITION_LEN; + } + + file_offset = 0; + } + +out: + return ret; +} +#endif /* NVT_DUMP_PARTITION */ + +/******************************************************* +Description: + Novatek touchscreen write data to sram function. + +- fwdata : The buffer is written +- SRAM_addr: The sram destination address +- size : Number of data bytes in @fwdata being written +- BIN_addr : The transferred data offset of @fwdata + +return: + Executive outcomes. 0---succeed. else---fail. +*******************************************************/ +static int32_t nvt_write_sram(const u8 *fwdata, uint32_t SRAM_addr, + uint32_t size, uint32_t BIN_addr) +{ + int32_t ret = 0; + uint32_t i = 0; + uint16_t len = 0; + int32_t count = 0; + + if (size % NVT_TRANSFER_LEN) + count = (size / NVT_TRANSFER_LEN) + 1; + else + count = (size / NVT_TRANSFER_LEN); + + for (i = 0; i < count; i++) { + len = (size < NVT_TRANSFER_LEN) ? size : NVT_TRANSFER_LEN; + + //---set xdata index to start address of SRAM--- + ret = nvt_set_page(SRAM_addr); + if (ret) { + NVT_ERR("set page failed, ret = %d\n", ret); + return ret; + } + + //---write data into SRAM--- + fwbuf[0] = SRAM_addr & 0x7F; //offset + memcpy(fwbuf + 1, &fwdata[BIN_addr], len); //payload + ret = CTP_SPI_WRITE(ts->client, fwbuf, len + 1); + if (ret) { + NVT_ERR("write to sram failed, ret = %d\n", ret); + return ret; + } + + SRAM_addr += NVT_TRANSFER_LEN; + BIN_addr += NVT_TRANSFER_LEN; + size -= NVT_TRANSFER_LEN; + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen nvt_write_firmware function to write +firmware into each partition. + +return: + n.a. +*******************************************************/ +static int32_t nvt_write_firmware(const u8 *fwdata, size_t fwsize) +{ + uint32_t list = 0; + char *name; + uint32_t BIN_addr, SRAM_addr, size; + int32_t ret = 0; + + memset(fwbuf, 0, (NVT_TRANSFER_LEN + 1)); + + for (list = 0; list < partition; list++) { + /* initialize variable */ + SRAM_addr = bin_map[list].SRAM_addr; + size = bin_map[list].size; + BIN_addr = bin_map[list].BIN_addr; + name = bin_map[list].name; + + // NVT_LOG("[%d][%s] SRAM (0x%08X), SIZE (0x%08X), BIN (0x%08X)\n", + // list, name, SRAM_addr, size, BIN_addr); + + /* Check data size */ + if ((BIN_addr + size) > fwsize) { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + BIN_addr, BIN_addr + size); + ret = -EINVAL; + goto out; + } + + /* ignore reserved partition (Reserved Partition size is zero) */ + if (!size) + continue; + else + size = size + 1; + + /* write data to SRAM */ + ret = nvt_write_sram(fwdata, SRAM_addr, size, BIN_addr); + if (ret) { + NVT_ERR("sram program failed, ret = %d\n", ret); + goto out; + } + } + +out: + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen check checksum function. +This function will compare file checksum and fw checksum. + +return: + n.a. +*******************************************************/ +static int32_t nvt_check_fw_checksum(void) +{ + uint32_t fw_checksum = 0; + uint32_t len = partition * 4; + uint32_t list = 0; + int32_t ret = 0; + + memset(fwbuf, 0, (len + 1)); + + //---set xdata index to checksum--- + nvt_set_page(ts->mmap->R_ILM_CHECKSUM_ADDR); + + /* read checksum */ + fwbuf[0] = (ts->mmap->R_ILM_CHECKSUM_ADDR) & 0x7F; + ret = CTP_SPI_READ(ts->client, fwbuf, len + 1); + if (ret) { + NVT_ERR("Read fw checksum failed\n"); + return ret; + } + + /* + * Compare each checksum from fw + * ILM + DLM + Overlay + Info + * ilm_dlm_num (ILM & DLM) + ovly_sec_num + info_sec_num + */ + for (list = 0; list < partition; list++) { + fw_checksum = byte_to_word(&fwbuf[1 + list * 4]); + + /* ignore reserved partition (Reserved Partition size is zero) */ + if (!bin_map[list].size) + continue; + + if (bin_map[list].crc != fw_checksum) { + NVT_ERR("[%d] BIN_checksum=0x%08X, FW_checksum=0x%08X\n", + list, bin_map[list].crc, fw_checksum); + ret = -EIO; + } + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen set bootload crc reg bank function. +This function will set hw crc reg before enable crc function. + +return: + n.a. +*******************************************************/ +static void nvt_set_bld_crc_bank(uint32_t DES_ADDR, uint32_t SRAM_ADDR, + uint32_t LENGTH_ADDR, uint32_t size, + uint32_t G_CHECKSUM_ADDR, uint32_t crc) +{ + /* write destination address */ + nvt_set_page(DES_ADDR); + fwbuf[0] = DES_ADDR & 0x7F; + fwbuf[1] = (SRAM_ADDR) & 0xFF; + fwbuf[2] = (SRAM_ADDR >> 8) & 0xFF; + fwbuf[3] = (SRAM_ADDR >> 16) & 0xFF; + CTP_SPI_WRITE(ts->client, fwbuf, 4); + + /* write length */ + //nvt_set_page(LENGTH_ADDR); + fwbuf[0] = LENGTH_ADDR & 0x7F; + fwbuf[1] = (size) & 0xFF; + fwbuf[2] = (size >> 8) & 0xFF; + fwbuf[3] = (size >> 16) & 0x01; + if (ts->hw_crc == 1) { + CTP_SPI_WRITE(ts->client, fwbuf, 3); + } else if (ts->hw_crc > 1) { + CTP_SPI_WRITE(ts->client, fwbuf, 4); + } + + /* write golden dlm checksum */ + //nvt_set_page(G_CHECKSUM_ADDR); + fwbuf[0] = G_CHECKSUM_ADDR & 0x7F; + fwbuf[1] = (crc) & 0xFF; + fwbuf[2] = (crc >> 8) & 0xFF; + fwbuf[3] = (crc >> 16) & 0xFF; + fwbuf[4] = (crc >> 24) & 0xFF; + CTP_SPI_WRITE(ts->client, fwbuf, 5); + + return; +} + +/******************************************************* +Description: + Novatek touchscreen set BLD hw crc function. +This function will set ILM and DLM crc information to register. + +return: + n.a. +*******************************************************/ +static void nvt_set_bld_hw_crc(void) +{ + /* [0] ILM */ + /* write register bank */ + nvt_set_bld_crc_bank(ts->mmap->ILM_DES_ADDR, bin_map[0].SRAM_addr, + ts->mmap->ILM_LENGTH_ADDR, bin_map[0].size, + ts->mmap->G_ILM_CHECKSUM_ADDR, bin_map[0].crc); + + /* [1] DLM */ + /* write register bank */ + nvt_set_bld_crc_bank(ts->mmap->DLM_DES_ADDR, bin_map[1].SRAM_addr, + ts->mmap->DLM_LENGTH_ADDR, bin_map[1].size, + ts->mmap->G_DLM_CHECKSUM_ADDR, bin_map[1].crc); +} + +/******************************************************* +Description: + Novatek touchscreen read BLD hw crc info function. +This function will check crc results from register. + +return: + n.a. +*******************************************************/ +static void nvt_read_bld_hw_crc(void) +{ + uint8_t buf[8] = { 0 }; + uint32_t g_crc = 0, r_crc = 0; + + /* CRC Flag */ + nvt_set_page(ts->mmap->BLD_ILM_DLM_CRC_ADDR); + buf[0] = ts->mmap->BLD_ILM_DLM_CRC_ADDR & 0x7F; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + NVT_ERR("crc_done = %d, ilm_crc_flag = %d, dlm_crc_flag = %d\n", + (buf[1] >> 2) & 0x01, (buf[1] >> 0) & 0x01, + (buf[1] >> 1) & 0x01); + + /* ILM CRC */ + nvt_set_page(ts->mmap->G_ILM_CHECKSUM_ADDR); + buf[0] = ts->mmap->G_ILM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + g_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + nvt_set_page(ts->mmap->R_ILM_CHECKSUM_ADDR); + buf[0] = ts->mmap->R_ILM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + r_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + NVT_ERR("ilm: bin crc = 0x%08X, golden = 0x%08X, result = 0x%08X\n", + bin_map[0].crc, g_crc, r_crc); + + /* DLM CRC */ + nvt_set_page(ts->mmap->G_DLM_CHECKSUM_ADDR); + buf[0] = ts->mmap->G_DLM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + g_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + nvt_set_page(ts->mmap->R_DLM_CHECKSUM_ADDR); + buf[0] = ts->mmap->R_DLM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + r_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + NVT_ERR("dlm: bin crc = 0x%08X, golden = 0x%08X, result = 0x%08X\n", + bin_map[1].crc, g_crc, r_crc); + + return; +} + +/******************************************************* +Description: + Novatek touchscreen Download_Firmware with HW CRC +function. It's complete download firmware flow. + +return: + Executive outcomes. 0---succeed. else---fail. +*******************************************************/ +static int32_t nvt_download_firmware_hw_crc(void) +{ + uint8_t retry = 0; + int32_t ret = 0; + + start = ktime_get(); + + while (1) { + /* bootloader reset to reset MCU */ + nvt_bootloader_reset(); + + /* set ilm & dlm reg bank */ + nvt_set_bld_hw_crc(); + + /* Start to write firmware process */ + if (cascade_2nd_header_info) { + /* for cascade */ + nvt_tx_auto_copy_mode(); + + ret = nvt_write_firmware(fw_entry->data, + fw_entry->size); + if (ret) { + NVT_ERR("Write_Firmware failed. (%d)\n", ret); + goto fail; + } + + ret = nvt_check_spi_dma_tx_info(); + if (ret) { + NVT_ERR("spi dma tx info failed. (%d)\n", ret); + goto fail; + } + } else { + ret = nvt_write_firmware(fw_entry->data, + fw_entry->size); + if (ret) { + NVT_ERR("Write_Firmware failed. (%d)\n", ret); + goto fail; + } + } + +#if NVT_DUMP_PARTITION + ret = nvt_dump_partition(); + if (ret) { + NVT_ERR("nvt_dump_partition failed, ret = %d\n", ret); + } +#endif + + /* enable hw bld crc function */ + nvt_bld_crc_enable(); + + /* clear fw reset status & enable fw crc check */ + nvt_fw_crc_enable(); + + /* Set Boot Ready Bit */ + nvt_boot_ready(); + + ret = nvt_check_fw_reset_state(RESET_STATE_INIT); + if (ret) { + NVT_ERR("nvt_check_fw_reset_state failed. (%d)\n", ret); + goto fail; + } else { + break; + } + +fail: + retry++; + if (unlikely(retry > 2)) { + NVT_ERR("error, retry=%d\n", retry); + nvt_read_bld_hw_crc(); + break; + } + } + + end = ktime_get(); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen Download_Firmware function. It's +complete download firmware flow. + +return: + n.a. +*******************************************************/ +static int32_t nvt_download_firmware(void) +{ + uint8_t retry = 0; + int32_t ret = 0; + + start = ktime_get(); + + while (1) { + /* + * Send eng reset cmd before download FW + * Keep TP_RESX low when send eng reset cmd + */ +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 0); + mdelay(1); //wait 1ms +#endif + nvt_eng_reset(); +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 1); + mdelay(10); //wait tRT2BRST after TP_RST +#endif + nvt_bootloader_reset(); + + /* clear fw reset status */ + nvt_write_addr(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_RESET_COMPLETE, + 0x00); + + /* Start to write firmware process */ + ret = nvt_write_firmware(fw_entry->data, fw_entry->size); + if (ret) { + NVT_ERR("Write_Firmware failed. (%d)\n", ret); + goto fail; + } + +#if NVT_DUMP_PARTITION + ret = nvt_dump_partition(); + if (ret) { + NVT_ERR("nvt_dump_partition failed, ret = %d\n", ret); + } +#endif + + /* Set Boot Ready Bit */ + nvt_boot_ready(); + + ret = nvt_check_fw_reset_state(RESET_STATE_INIT); + if (ret) { + NVT_ERR("nvt_check_fw_reset_state failed. (%d)\n", ret); + goto fail; + } + + /* check fw checksum result */ + ret = nvt_check_fw_checksum(); + if (ret) { + NVT_ERR("firmware checksum not match, retry=%d\n", + retry); + goto fail; + } else { + break; + } + +fail: + retry++; + if (unlikely(retry > 2)) { + NVT_ERR("error, retry=%d\n", retry); + break; + } + } + + end = ktime_get(); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen update firmware main function. + +return: + n.a. +*******************************************************/ +int32_t nvt_update_firmware(const char *firmware_name) +{ + int32_t ret = 0; + + // request bin file in "/etc/firmware" + ret = update_firmware_request(firmware_name); + if (ret) { + NVT_ERR("update_firmware_request failed. (%d)\n", ret); + goto request_firmware_fail; + } + + /* initial buffer and variable */ + ret = nvt_download_init(); + if (ret) { + NVT_ERR("Download Init failed. (%d)\n", ret); + goto download_fail; + } + + /* download firmware process */ + if (ts->hw_crc) + ret = nvt_download_firmware_hw_crc(); + else + ret = nvt_download_firmware(); + if (ret) { + NVT_ERR("Download Firmware failed. (%d)\n", ret); + goto download_fail; + } + + NVT_LOG("Update firmware success! <%ld us>\n", + (long)ktime_us_delta(end, start)); + + /* Get FW Info */ + ret = nvt_get_fw_info(); + if (ret) { + NVT_ERR("nvt_get_fw_info failed. (%d)\n", ret); + } + +download_fail: + if (!IS_ERR_OR_NULL(bin_map)) { + kfree(bin_map); + bin_map = NULL; + } + + update_firmware_release(); +request_firmware_fail: + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen update firmware when booting + function. + +return: + n.a. +*******************************************************/ +void Boot_Update_Firmware(struct work_struct *work) +{ + nvt_match_fw(); + mutex_lock(&ts->lock); + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + nvt_get_fw_info(); + mutex_unlock(&ts->lock); +} +#endif /* BOOT_UPDATE_FIRMWARE */ diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mem_map.h b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mem_map.h new file mode 100644 index 000000000000..cc92256f9efe --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mem_map.h @@ -0,0 +1,442 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * $Revision: 57674 $ + * $Date: 2020-03-02 11:16:20 +0800 (週一, 02 三月 2020) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#define CHIP_VER_TRIM_ADDR 0x3F004 +#define CHIP_VER_TRIM_OLD_ADDR 0x1F64E + +struct nvt_ts_mem_map { + uint32_t EVENT_BUF_ADDR; + uint32_t RAW_PIPE0_ADDR; + uint32_t RAW_PIPE1_ADDR; + uint32_t BASELINE_ADDR; + uint32_t BASELINE_BTN_ADDR; + uint32_t DIFF_PIPE0_ADDR; + uint32_t DIFF_PIPE1_ADDR; + uint32_t RAW_BTN_PIPE0_ADDR; + uint32_t RAW_BTN_PIPE1_ADDR; + uint32_t DIFF_BTN_PIPE0_ADDR; + uint32_t DIFF_BTN_PIPE1_ADDR; + uint32_t PEN_2D_BL_TIP_X_ADDR; + uint32_t PEN_2D_BL_TIP_Y_ADDR; + uint32_t PEN_2D_BL_RING_X_ADDR; + uint32_t PEN_2D_BL_RING_Y_ADDR; + uint32_t PEN_2D_DIFF_TIP_X_ADDR; + uint32_t PEN_2D_DIFF_TIP_Y_ADDR; + uint32_t PEN_2D_DIFF_RING_X_ADDR; + uint32_t PEN_2D_DIFF_RING_Y_ADDR; + uint32_t PEN_2D_RAW_TIP_X_ADDR; + uint32_t PEN_2D_RAW_TIP_Y_ADDR; + uint32_t PEN_2D_RAW_RING_X_ADDR; + uint32_t PEN_2D_RAW_RING_Y_ADDR; + uint32_t PEN_1D_DIFF_TIP_X_ADDR; + uint32_t PEN_1D_DIFF_TIP_Y_ADDR; + uint32_t PEN_1D_DIFF_RING_X_ADDR; + uint32_t PEN_1D_DIFF_RING_Y_ADDR; + uint32_t READ_FLASH_CHECKSUM_ADDR; + uint32_t RW_FLASH_DATA_ADDR; + /* Phase 2 Host Download */ + uint32_t BOOT_RDY_ADDR; + uint32_t POR_CD_ADDR; + uint32_t TX_AUTO_COPY_EN; + uint32_t SPI_DMA_TX_INFO; + /* BLD CRC */ + uint32_t BLD_LENGTH_ADDR; + uint32_t ILM_LENGTH_ADDR; + uint32_t DLM_LENGTH_ADDR; + uint32_t BLD_DES_ADDR; + uint32_t ILM_DES_ADDR; + uint32_t DLM_DES_ADDR; + uint32_t G_ILM_CHECKSUM_ADDR; + uint32_t G_DLM_CHECKSUM_ADDR; + uint32_t R_ILM_CHECKSUM_ADDR; + uint32_t R_DLM_CHECKSUM_ADDR; + uint32_t BLD_CRC_EN_ADDR; + uint32_t DMA_CRC_EN_ADDR; + uint32_t BLD_ILM_DLM_CRC_ADDR; + uint32_t DMA_CRC_FLAG_ADDR; + uint32_t FW_HISTORY_ADDR; +}; + +struct nvt_ts_hw_info { + uint8_t carrier_system; + uint8_t hw_crc; +}; + +static const struct nvt_ts_mem_map NT36523_memory_map = { + .EVENT_BUF_ADDR = 0x2FE00, + .RAW_PIPE0_ADDR = 0x30FA0, + .RAW_PIPE1_ADDR = 0x30FA0, + .BASELINE_ADDR = 0x36510, + .BASELINE_BTN_ADDR = 0, + .DIFF_PIPE0_ADDR = 0x373E8, + .DIFF_PIPE1_ADDR = 0x38068, + .RAW_BTN_PIPE0_ADDR = 0, + .RAW_BTN_PIPE1_ADDR = 0, + .DIFF_BTN_PIPE0_ADDR = 0, + .DIFF_BTN_PIPE1_ADDR = 0, + .PEN_2D_BL_TIP_X_ADDR = 0x2988A, + .PEN_2D_BL_TIP_Y_ADDR = 0x29A1A, + .PEN_2D_BL_RING_X_ADDR = 0x29BAA, + .PEN_2D_BL_RING_Y_ADDR = 0x29D3A, + .PEN_2D_DIFF_TIP_X_ADDR = 0x29ECA, + .PEN_2D_DIFF_TIP_Y_ADDR = 0x2A05A, + .PEN_2D_DIFF_RING_X_ADDR = 0x2A1EA, + .PEN_2D_DIFF_RING_Y_ADDR = 0x2A37A, + .PEN_2D_RAW_TIP_X_ADDR = 0x2A50A, + .PEN_2D_RAW_TIP_Y_ADDR = 0x2A69A, + .PEN_2D_RAW_RING_X_ADDR = 0x2A82A, + .PEN_2D_RAW_RING_Y_ADDR = 0x2A9BA, + .PEN_1D_DIFF_TIP_X_ADDR = 0x2AB4A, + .PEN_1D_DIFF_TIP_Y_ADDR = 0x2ABAE, + .PEN_1D_DIFF_RING_X_ADDR = 0x2AC12, + .PEN_1D_DIFF_RING_Y_ADDR = 0x2AC76, + .READ_FLASH_CHECKSUM_ADDR = 0x24000, + .RW_FLASH_DATA_ADDR = 0x24002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + .TX_AUTO_COPY_EN = 0x3F7E8, + .SPI_DMA_TX_INFO = 0x3F7F1, + /* BLD CRC */ + .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) + .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) + .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) + .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) + .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) + .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) + .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) + .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F136, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, + .FW_HISTORY_ADDR = 0x38D54, +}; + +static const struct nvt_ts_mem_map NT36526_memory_map = { + .EVENT_BUF_ADDR = 0x22D00, + .RAW_PIPE0_ADDR = 0x24000, + .RAW_PIPE1_ADDR = 0x24000, + .BASELINE_ADDR = 0x21758, + .BASELINE_BTN_ADDR = 0, + .DIFF_PIPE0_ADDR = 0x20AB0, + .DIFF_PIPE1_ADDR = 0x24AB0, + .RAW_BTN_PIPE0_ADDR = 0, + .RAW_BTN_PIPE1_ADDR = 0, + .DIFF_BTN_PIPE0_ADDR = 0, + .DIFF_BTN_PIPE1_ADDR = 0, + .READ_FLASH_CHECKSUM_ADDR = 0x24000, + .RW_FLASH_DATA_ADDR = 0x24002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ + .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) + .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) + .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) + .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) + .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) + .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) + .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) + .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F136, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, +}; + +static const struct nvt_ts_mem_map NT36675_memory_map = { + .EVENT_BUF_ADDR = 0x22D00, + .RAW_PIPE0_ADDR = 0x24000, + .RAW_PIPE1_ADDR = 0x24000, + .BASELINE_ADDR = 0x21B90, + .BASELINE_BTN_ADDR = 0, + .DIFF_PIPE0_ADDR = 0x20C60, + .DIFF_PIPE1_ADDR = 0x24C60, + .RAW_BTN_PIPE0_ADDR = 0, + .RAW_BTN_PIPE1_ADDR = 0, + .DIFF_BTN_PIPE0_ADDR = 0, + .DIFF_BTN_PIPE1_ADDR = 0, + .READ_FLASH_CHECKSUM_ADDR = 0x24000, + .RW_FLASH_DATA_ADDR = 0x24002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ + .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) + .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) + .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) + .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) + .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) + .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) + .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) + .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F136, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, +}; + +static const struct nvt_ts_mem_map NT36672A_memory_map = { + .EVENT_BUF_ADDR = 0x21C00, + .RAW_PIPE0_ADDR = 0x20000, + .RAW_PIPE1_ADDR = 0x23000, + .BASELINE_ADDR = 0x20BFC, + .BASELINE_BTN_ADDR = 0x23BFC, + .DIFF_PIPE0_ADDR = 0x206DC, + .DIFF_PIPE1_ADDR = 0x236DC, + .RAW_BTN_PIPE0_ADDR = 0x20510, + .RAW_BTN_PIPE1_ADDR = 0x23510, + .DIFF_BTN_PIPE0_ADDR = 0x20BF0, + .DIFF_BTN_PIPE1_ADDR = 0x23BF0, + .READ_FLASH_CHECKSUM_ADDR = 0x24000, + .RW_FLASH_DATA_ADDR = 0x24002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ + .BLD_LENGTH_ADDR = 0x3F10E, //0x3F10E ~ 0x3F10F (2 bytes) + .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F119 (2 bytes) + .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F131 (2 bytes) + .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) + .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) + .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) + .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) + .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F132, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, +}; + +static const struct nvt_ts_mem_map NT36772_memory_map = { + .EVENT_BUF_ADDR = 0x11E00, + .RAW_PIPE0_ADDR = 0x10000, + .RAW_PIPE1_ADDR = 0x12000, + .BASELINE_ADDR = 0x10E70, + .BASELINE_BTN_ADDR = 0x12E70, + .DIFF_PIPE0_ADDR = 0x10830, + .DIFF_PIPE1_ADDR = 0x12830, + .RAW_BTN_PIPE0_ADDR = 0x10E60, + .RAW_BTN_PIPE1_ADDR = 0x12E60, + .DIFF_BTN_PIPE0_ADDR = 0x10E68, + .DIFF_BTN_PIPE1_ADDR = 0x12E68, + .READ_FLASH_CHECKSUM_ADDR = 0x14000, + .RW_FLASH_DATA_ADDR = 0x14002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x1F141, + .POR_CD_ADDR = 0x1F61C, + /* BLD CRC */ + .R_ILM_CHECKSUM_ADDR = 0x1BF00, +}; + +static const struct nvt_ts_mem_map NT36525_memory_map = { + .EVENT_BUF_ADDR = 0x11A00, + .RAW_PIPE0_ADDR = 0x10000, + .RAW_PIPE1_ADDR = 0x12000, + .BASELINE_ADDR = 0x10B08, + .BASELINE_BTN_ADDR = 0x12B08, + .DIFF_PIPE0_ADDR = 0x1064C, + .DIFF_PIPE1_ADDR = 0x1264C, + .RAW_BTN_PIPE0_ADDR = 0x10634, + .RAW_BTN_PIPE1_ADDR = 0x12634, + .DIFF_BTN_PIPE0_ADDR = 0x10AFC, + .DIFF_BTN_PIPE1_ADDR = 0x12AFC, + .READ_FLASH_CHECKSUM_ADDR = 0x14000, + .RW_FLASH_DATA_ADDR = 0x14002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x1F141, + .POR_CD_ADDR = 0x1F61C, + /* BLD CRC */ + .R_ILM_CHECKSUM_ADDR = 0x1BF00, +}; + +static const struct nvt_ts_mem_map NT36676F_memory_map = { + .EVENT_BUF_ADDR = 0x11A00, + .RAW_PIPE0_ADDR = 0x10000, + .RAW_PIPE1_ADDR = 0x12000, + .BASELINE_ADDR = 0x10B08, + .BASELINE_BTN_ADDR = 0x12B08, + .DIFF_PIPE0_ADDR = 0x1064C, + .DIFF_PIPE1_ADDR = 0x1264C, + .RAW_BTN_PIPE0_ADDR = 0x10634, + .RAW_BTN_PIPE1_ADDR = 0x12634, + .DIFF_BTN_PIPE0_ADDR = 0x10AFC, + .DIFF_BTN_PIPE1_ADDR = 0x12AFC, + .READ_FLASH_CHECKSUM_ADDR = 0x14000, + .RW_FLASH_DATA_ADDR = 0x14002, +}; + +static struct nvt_ts_hw_info NT36523_hw_info = { + .carrier_system = 2, + .hw_crc = 2, +}; + +static struct nvt_ts_hw_info NT36526_hw_info = { + .carrier_system = 2, + .hw_crc = 2, +}; + +static struct nvt_ts_hw_info NT36675_hw_info = { + .carrier_system = 2, + .hw_crc = 2, +}; + +static struct nvt_ts_hw_info NT36672A_hw_info = { + .carrier_system = 0, + .hw_crc = 1, +}; + +static struct nvt_ts_hw_info NT36772_hw_info = { + .carrier_system = 0, + .hw_crc = 0, +}; + +static struct nvt_ts_hw_info NT36525_hw_info = { + .carrier_system = 0, + .hw_crc = 0, +}; + +static struct nvt_ts_hw_info NT36676F_hw_info = { + .carrier_system = 0, + .hw_crc = 0, +}; + +#define NVT_ID_BYTE_MAX 6 +struct nvt_ts_trim_id_table { + uint8_t id[NVT_ID_BYTE_MAX]; + uint8_t mask[NVT_ID_BYTE_MAX]; + const struct nvt_ts_mem_map *mmap; + const struct nvt_ts_hw_info *hwinfo; +}; + +static const struct nvt_ts_trim_id_table trim_id_table[] = { + { .id = { 0x20, 0xFF, 0xFF, 0x23, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36523_memory_map, + .hwinfo = &NT36523_hw_info }, + { .id = { 0x0C, 0xFF, 0xFF, 0x23, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36523_memory_map, + .hwinfo = &NT36523_hw_info }, + { .id = { 0x0B, 0xFF, 0xFF, 0x23, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36523_memory_map, + .hwinfo = &NT36523_hw_info }, + { .id = { 0x0A, 0xFF, 0xFF, 0x23, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36523_memory_map, + .hwinfo = &NT36523_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x23, 0x65, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36523_memory_map, + .hwinfo = &NT36523_hw_info }, + { .id = { 0x0C, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36675_memory_map, + .hwinfo = &NT36675_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x26, 0x65, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36526_memory_map, + .hwinfo = &NT36526_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x75, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36675_memory_map, + .hwinfo = &NT36675_hw_info }, + { .id = { 0x0B, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0B, 0xFF, 0xFF, 0x82, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0B, 0xFF, 0xFF, 0x25, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0A, 0xFF, 0xFF, 0x72, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0A, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0A, 0xFF, 0xFF, 0x82, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0A, 0xFF, 0xFF, 0x70, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0B, 0xFF, 0xFF, 0x70, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x0A, 0xFF, 0xFF, 0x72, 0x67, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info }, + { .id = { 0x55, 0x00, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0x55, 0x72, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0xAA, 0x00, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0xAA, 0x72, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x72, 0x67, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x70, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x70, 0x67, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x25, 0x65, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36525_memory_map, + .hwinfo = &NT36525_hw_info }, + { .id = { 0xFF, 0xFF, 0xFF, 0x76, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36676F_memory_map, + .hwinfo = &NT36676F_hw_info } +}; diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.c new file mode 100644 index 000000000000..91bf34c77526 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.c @@ -0,0 +1,4254 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * $Revision: 60182 $ + * $Date: 2020-04-13 10:07:31 +0800 (週一, 13 四月 2020) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include + +#include "nt36xxx.h" +#include "nt36xxx_mp_ctrlram.h" + +#if NVT_TOUCH_MP + +#define NORMAL_MODE 0x00 +#define TEST_MODE_1 0x21 +#define TEST_MODE_2 0x22 +#define MP_MODE_CC 0x41 +#define FREQ_HOP_DISABLE 0x66 +#define FREQ_HOP_ENABLE 0x65 + +#define NVT_RESULT_INVALID 0 +#define NVT_RESULT_PASS 2 +#define NVT_RESULT_FAIL 1 + +#define SHORT_TEST_CSV_FILE "/data/misc/tp_selftest_data/ShortTest.csv" +#define OPEN_TEST_CSV_FILE "/data/misc/tp_selftest_data/OpenTest.csv" +#define FW_RAWDATA_CSV_FILE "/data/misc/tp_selftest_data/FWMutualTest.csv" +#define FW_CC_CSV_FILE "/data/misc/tp_selftest_data/FWCCTest.csv" +#define NOISE_TEST_CSV_FILE "/data/misc/tp_selftest_data/NoiseTest.csv" +#define PEN_FW_RAW_TEST_CSV_FILE "/data/misc/tp_selftest_data/PenFWRawTest.csv" +#define PEN_NOISE_TEST_CSV_FILE "/data/misc/tp_selftest_data/PenNoiseTest.csv" + +#define nvt_mp_seq_printf(m, fmt, args...) \ + do { \ + seq_printf(m, fmt, ##args); \ + if (!nvt_mp_test_result_printed) \ + printk(fmt, ##args); \ + } while (0) + +static uint8_t *RecordResult_Short = NULL; +static uint8_t *RecordResult_Open = NULL; +static uint8_t *RecordResult_FWMutual = NULL; +static uint8_t *RecordResult_FW_CC = NULL; +static uint8_t *RecordResult_FW_DiffMax = NULL; +static uint8_t *RecordResult_FW_DiffMin = NULL; +static uint8_t *RecordResult_PenTipX_Raw = NULL; +static uint8_t *RecordResult_PenTipY_Raw = NULL; +static uint8_t *RecordResult_PenRingX_Raw = NULL; +static uint8_t *RecordResult_PenRingY_Raw = NULL; +static uint8_t *RecordResult_PenTipX_DiffMax = NULL; +static uint8_t *RecordResult_PenTipX_DiffMin = NULL; +static uint8_t *RecordResult_PenTipY_DiffMax = NULL; +static uint8_t *RecordResult_PenTipY_DiffMin = NULL; +static uint8_t *RecordResult_PenRingX_DiffMax = NULL; +static uint8_t *RecordResult_PenRingX_DiffMin = NULL; +static uint8_t *RecordResult_PenRingY_DiffMax = NULL; +static uint8_t *RecordResult_PenRingY_DiffMin = NULL; + +static int32_t TestResult_Short = 0; +static int32_t TestResult_Open = 0; +static int32_t TestResult_FW_Rawdata = 0; +static int32_t TestResult_FWMutual = 0; +static int32_t TestResult_FW_CC = 0; +static int32_t TestResult_Noise = 0; +static int32_t TestResult_FW_DiffMax = 0; +static int32_t TestResult_FW_DiffMin = 0; +static int32_t TestResult_Pen_FW_Raw = 0; +static int32_t TestResult_PenTipX_Raw = 0; +static int32_t TestResult_PenTipY_Raw = 0; +static int32_t TestResult_PenRingX_Raw = 0; +static int32_t TestResult_PenRingY_Raw = 0; +static int32_t TestResult_Pen_Noise = 0; +static int32_t TestResult_PenTipX_DiffMax = 0; +static int32_t TestResult_PenTipX_DiffMin = 0; +static int32_t TestResult_PenTipY_DiffMax = 0; +static int32_t TestResult_PenTipY_DiffMin = 0; +static int32_t TestResult_PenRingX_DiffMax = 0; +static int32_t TestResult_PenRingX_DiffMin = 0; +static int32_t TestResult_PenRingY_DiffMax = 0; +static int32_t TestResult_PenRingY_DiffMin = 0; + +static int32_t *RawData_Short = NULL; +static int32_t *RawData_Open = NULL; +static int32_t *RawData_Diff = NULL; +static int32_t *RawData_Diff_Min = NULL; +static int32_t *RawData_Diff_Max = NULL; +static int32_t *RawData_FWMutual = NULL; +static int32_t *RawData_FW_CC = NULL; +static int32_t *RawData_PenTipX_Raw = NULL; +static int32_t *RawData_PenTipY_Raw = NULL; +static int32_t *RawData_PenRingX_Raw = NULL; +static int32_t *RawData_PenRingY_Raw = NULL; +static int32_t *RawData_PenTipX_DiffMin = NULL; +static int32_t *RawData_PenTipX_DiffMax = NULL; +static int32_t *RawData_PenTipY_DiffMin = NULL; +static int32_t *RawData_PenTipY_DiffMax = NULL; +static int32_t *RawData_PenRingX_DiffMin = NULL; +static int32_t *RawData_PenRingX_DiffMax = NULL; +static int32_t *RawData_PenRingY_DiffMin = NULL; +static int32_t *RawData_PenRingY_DiffMax = NULL; + +static struct proc_dir_entry *NVT_proc_selftest_entry = NULL; +static struct proc_dir_entry *NVT_proc_aftersales_test_entry; +#ifndef NVT_SAVE_TESTDATA_IN_FILE +static struct proc_dir_entry *NVT_proc_test_data_entry = NULL; +#endif + +static int8_t nvt_mp_test_result_printed = 0; +static uint8_t fw_ver = 0; + +extern void nvt_change_mode(uint8_t mode); +extern uint8_t nvt_get_fw_pipe(void); +extern void nvt_read_mdata(uint32_t xdata_addr, uint32_t xdata_btn_addr); +extern void nvt_get_mdata(int32_t *buf, uint8_t *m_x_num, uint8_t *m_y_num); +extern void nvt_read_get_num_mdata(uint32_t xdata_addr, int32_t *buffer, + uint32_t num); +int32_t nvt_mp_parse_dt(struct device_node *root, const char *node_compatible); + +/******************************************************* +Description: + Novatek touchscreen allocate buffer for mp selftest. + +return: + Executive outcomes. 0---succeed. -12---Out of memory +*******************************************************/ +static int nvt_mp_buffer_init(void) +{ + size_t RecordResult_BufSize = + IC_X_CFG_SIZE * IC_Y_CFG_SIZE + IC_KEY_CFG_SIZE; + size_t RawData_BufSize = + (IC_X_CFG_SIZE * IC_Y_CFG_SIZE + IC_KEY_CFG_SIZE) * + sizeof(int32_t); + size_t Pen_RecordResult_BufSize = + max(ts->x_num * ts->y_gang_num, ts->x_gang_num * ts->y_num); + size_t Pen_RawData_BufSize = + max(ts->x_num * ts->y_gang_num, ts->x_gang_num * ts->y_num) * + sizeof(int32_t); + + RecordResult_Short = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_Short) { + NVT_ERR("kzalloc for RecordResult_Short failed!\n"); + return -ENOMEM; + } + + RecordResult_Open = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_Open) { + NVT_ERR("kzalloc for RecordResult_Open failed!\n"); + return -ENOMEM; + } + + RecordResult_FWMutual = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FWMutual) { + NVT_ERR("kzalloc for RecordResult_FWMutual failed!\n"); + return -ENOMEM; + } + + RecordResult_FW_CC = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FW_CC) { + NVT_ERR("kzalloc for RecordResult_FW_CC failed!\n"); + return -ENOMEM; + } + + RecordResult_FW_DiffMax = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FW_DiffMax) { + NVT_ERR("kzalloc for RecordResult_FW_DiffMax failed!\n"); + return -ENOMEM; + } + + RecordResult_FW_DiffMin = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FW_DiffMin) { + NVT_ERR("kzalloc for RecordResult_FW_DiffMin failed!\n"); + return -ENOMEM; + } + + if (ts->pen_support) { + RecordResult_PenTipX_Raw = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenTipX_Raw) { + NVT_ERR("kzalloc for RecordResult_PenTipX_Raw failed!\n"); + return -ENOMEM; + } + + RecordResult_PenTipY_Raw = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenTipY_Raw) { + NVT_ERR("kzalloc for RecordResult_PenTipY_Raw failed!\n"); + return -ENOMEM; + } + + RecordResult_PenRingX_Raw = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenRingX_Raw) { + NVT_ERR("kzalloc for RecordResult_PenRingX_Raw failed!\n"); + return -ENOMEM; + } + + RecordResult_PenRingY_Raw = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenRingY_Raw) { + NVT_ERR("kzalloc for RecordResult_PenRingY_Raw failed!\n"); + return -ENOMEM; + } + + RecordResult_PenTipX_DiffMax = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenTipX_DiffMax) { + NVT_ERR("kzalloc for RecordResult_PenTipX_DiffMax failed!\n"); + return -ENOMEM; + } + + RecordResult_PenTipX_DiffMin = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenTipX_DiffMin) { + NVT_ERR("kzalloc for RecordResult_PenTipX_DiffMin failed!\n"); + return -ENOMEM; + } + + RecordResult_PenTipY_DiffMax = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenTipY_DiffMax) { + NVT_ERR("kzalloc for RecordResult_PenTipY_DiffMax failed!\n"); + return -ENOMEM; + } + + RecordResult_PenTipY_DiffMin = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenTipY_DiffMin) { + NVT_ERR("kzalloc for RecordResult_PenTipY_DiffMin failed!\n"); + return -ENOMEM; + } + + RecordResult_PenRingX_DiffMax = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenRingX_DiffMax) { + NVT_ERR("kzalloc for RecordResult_PenRingX_DiffMax failed!\n"); + return -ENOMEM; + } + + RecordResult_PenRingX_DiffMin = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenRingX_DiffMin) { + NVT_ERR("kzalloc for RecordResult_PenRingX_DiffMin failed!\n"); + return -ENOMEM; + } + + RecordResult_PenRingY_DiffMax = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenRingY_DiffMax) { + NVT_ERR("kzalloc for RecordResult_PenRingY_DiffMax failed!\n"); + return -ENOMEM; + } + + RecordResult_PenRingY_DiffMin = (uint8_t *)kzalloc( + Pen_RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_PenRingY_DiffMin) { + NVT_ERR("kzalloc for RecordResult_PenRingY_DiffMin failed!\n"); + return -ENOMEM; + } + } /* if (ts->pen_support) */ + + RawData_Short = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Short) { + NVT_ERR("kzalloc for RawData_Short failed!\n"); + return -ENOMEM; + } + + RawData_Open = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Open) { + NVT_ERR("kzalloc for RawData_Open failed!\n"); + return -ENOMEM; + } + + RawData_Diff = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Diff) { + NVT_ERR("kzalloc for RawData_Diff failed!\n"); + return -ENOMEM; + } + + RawData_Diff_Min = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Diff_Min) { + NVT_ERR("kzalloc for RawData_Diff_Min failed!\n"); + return -ENOMEM; + } + + RawData_Diff_Max = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Diff_Max) { + NVT_ERR("kzalloc for RawData_Diff_Max failed!\n"); + return -ENOMEM; + } + + RawData_FWMutual = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_FWMutual) { + NVT_ERR("kzalloc for RawData_FWMutual failed!\n"); + return -ENOMEM; + } + + RawData_FW_CC = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_FW_CC) { + NVT_ERR("kzalloc for RawData_FW_CC failed!\n"); + return -ENOMEM; + } + + if (ts->pen_support) { + RawData_PenTipX_Raw = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenTipX_Raw) { + NVT_ERR("kzalloc for RawData_PenTipX_Raw failed!\n"); + return -ENOMEM; + } + + RawData_PenTipY_Raw = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenTipY_Raw) { + NVT_ERR("kzalloc for RawData_PenTipY_Raw failed!\n"); + return -ENOMEM; + } + + RawData_PenRingX_Raw = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenRingX_Raw) { + NVT_ERR("kzalloc for RawData_PenRingX_Raw failed!\n"); + return -ENOMEM; + } + + RawData_PenRingY_Raw = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenRingY_Raw) { + NVT_ERR("kzalloc for RawData_PenRingY_Raw failed!\n"); + return -ENOMEM; + } + + RawData_PenTipX_DiffMax = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenTipX_DiffMax) { + NVT_ERR("kzalloc for RawData_PenTipX_DiffMax failed!\n"); + return -ENOMEM; + } + + RawData_PenTipX_DiffMin = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenTipX_DiffMin) { + NVT_ERR("kzalloc for RawData_PenTipX_DiffMin failed!\n"); + return -ENOMEM; + } + + RawData_PenTipY_DiffMax = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenTipY_DiffMax) { + NVT_ERR("kzalloc for RawData_PenTipY_DiffMax failed!\n"); + return -ENOMEM; + } + + RawData_PenTipY_DiffMin = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenTipY_DiffMin) { + NVT_ERR("kzalloc for RawData_PenTipY_DiffMin failed!\n"); + return -ENOMEM; + } + + RawData_PenRingX_DiffMax = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenRingX_DiffMax) { + NVT_ERR("kzalloc for RawData_PenRingX_DiffMax failed!\n"); + return -ENOMEM; + } + + RawData_PenRingX_DiffMin = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenRingX_DiffMin) { + NVT_ERR("kzalloc for RawData_PenRingX_DiffMin failed!\n"); + return -ENOMEM; + } + + RawData_PenRingY_DiffMax = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenRingY_DiffMax) { + NVT_ERR("kzalloc for RawData_PenRingY_DiffMax failed!\n"); + return -ENOMEM; + } + + RawData_PenRingY_DiffMin = + (int32_t *)kzalloc(Pen_RawData_BufSize, GFP_KERNEL); + if (!RawData_PenRingY_DiffMin) { + NVT_ERR("kzalloc for RawData_PenRingY_DiffMin failed!\n"); + return -ENOMEM; + } + } /* if (ts->pen_support) */ + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen free buffer for mp selftest. + +return: + n.a. +*******************************************************/ +static void nvt_mp_buffer_deinit(void) +{ + if (RecordResult_Short) { + kfree(RecordResult_Short); + RecordResult_Short = NULL; + } + + if (RecordResult_Open) { + kfree(RecordResult_Open); + RecordResult_Open = NULL; + } + + if (RecordResult_FWMutual) { + kfree(RecordResult_FWMutual); + RecordResult_FWMutual = NULL; + } + + if (RecordResult_FW_CC) { + kfree(RecordResult_FW_CC); + RecordResult_FW_CC = NULL; + } + + if (RecordResult_FW_DiffMax) { + kfree(RecordResult_FW_DiffMax); + RecordResult_FW_DiffMax = NULL; + } + + if (RecordResult_FW_DiffMin) { + kfree(RecordResult_FW_DiffMin); + RecordResult_FW_DiffMin = NULL; + } + + if (ts->pen_support) { + if (RecordResult_PenTipX_Raw) { + kfree(RecordResult_PenTipX_Raw); + RecordResult_PenTipX_Raw = NULL; + } + + if (RecordResult_PenTipY_Raw) { + kfree(RecordResult_PenTipY_Raw); + RecordResult_PenTipY_Raw = NULL; + } + + if (RecordResult_PenRingX_Raw) { + kfree(RecordResult_PenRingX_Raw); + RecordResult_PenRingX_Raw = NULL; + } + + if (RecordResult_PenRingY_Raw) { + kfree(RecordResult_PenRingY_Raw); + RecordResult_PenRingY_Raw = NULL; + } + + if (RecordResult_PenTipX_DiffMax) { + kfree(RecordResult_PenTipX_DiffMax); + RecordResult_PenTipX_DiffMax = NULL; + } + + if (RecordResult_PenTipX_DiffMin) { + kfree(RecordResult_PenTipX_DiffMin); + RecordResult_PenTipX_DiffMin = NULL; + } + + if (RecordResult_PenTipY_DiffMax) { + kfree(RecordResult_PenTipY_DiffMax); + RecordResult_PenTipY_DiffMax = NULL; + } + + if (RecordResult_PenTipY_DiffMin) { + kfree(RecordResult_PenTipY_DiffMin); + RecordResult_PenTipY_DiffMin = NULL; + } + + if (RecordResult_PenRingX_DiffMax) { + kfree(RecordResult_PenRingX_DiffMax); + RecordResult_PenRingX_DiffMax = NULL; + } + + if (RecordResult_PenRingX_DiffMin) { + kfree(RecordResult_PenRingX_DiffMin); + RecordResult_PenRingX_DiffMin = NULL; + } + + if (RecordResult_PenRingY_DiffMax) { + kfree(RecordResult_PenRingY_DiffMax); + RecordResult_PenRingY_DiffMax = NULL; + } + + if (RecordResult_PenRingY_DiffMin) { + kfree(RecordResult_PenRingY_DiffMin); + RecordResult_PenRingY_DiffMin = NULL; + } + } /* if (ts->pen_support) */ + + if (RawData_Short) { + kfree(RawData_Short); + RawData_Short = NULL; + } + + if (RawData_Open) { + kfree(RawData_Open); + RawData_Open = NULL; + } + + if (RawData_Diff) { + kfree(RawData_Diff); + RawData_Diff = NULL; + } + + if (RawData_Diff_Min) { + kfree(RawData_Diff_Min); + RawData_Diff_Min = NULL; + } + + if (RawData_Diff_Max) { + kfree(RawData_Diff_Max); + RawData_Diff_Max = NULL; + } + + if (RawData_FWMutual) { + kfree(RawData_FWMutual); + RawData_FWMutual = NULL; + } + + if (RawData_FW_CC) { + kfree(RawData_FW_CC); + RawData_FW_CC = NULL; + } + + if (ts->pen_support) { + if (RawData_PenTipX_Raw) { + kfree(RawData_PenTipX_Raw); + RawData_PenTipX_Raw = NULL; + } + + if (RawData_PenTipY_Raw) { + kfree(RawData_PenTipY_Raw); + RawData_PenTipY_Raw = NULL; + } + + if (RawData_PenRingX_Raw) { + kfree(RawData_PenRingX_Raw); + RawData_PenRingX_Raw = NULL; + } + + if (RawData_PenRingY_Raw) { + kfree(RawData_PenRingY_Raw); + RawData_PenRingY_Raw = NULL; + } + + if (RawData_PenTipX_DiffMax) { + kfree(RawData_PenTipX_DiffMax); + RawData_PenTipX_DiffMax = NULL; + } + + if (RawData_PenTipX_DiffMin) { + kfree(RawData_PenTipX_DiffMin); + RawData_PenTipX_DiffMin = NULL; + } + + if (RawData_PenTipY_DiffMax) { + kfree(RawData_PenTipY_DiffMax); + RawData_PenTipY_DiffMax = NULL; + } + + if (RawData_PenTipY_DiffMin) { + kfree(RawData_PenTipY_DiffMin); + RawData_PenTipY_DiffMin = NULL; + } + + if (RawData_PenRingX_DiffMax) { + kfree(RawData_PenRingX_DiffMax); + RawData_PenRingX_DiffMax = NULL; + } + + if (RawData_PenRingX_DiffMin) { + kfree(RawData_PenRingX_DiffMin); + RawData_PenRingX_DiffMin = NULL; + } + + if (RawData_PenRingY_DiffMax) { + kfree(RawData_PenRingY_DiffMax); + RawData_PenRingY_DiffMax = NULL; + } + + if (RawData_PenRingY_DiffMin) { + kfree(RawData_PenRingY_DiffMin); + RawData_PenRingY_DiffMin = NULL; + } + } /* if (ts->pen_support) */ +} + +static void nvt_print_data_log_in_one_line(int32_t *data, int32_t data_num) +{ + char *tmp_log = NULL; + int32_t i = 0; + + tmp_log = (char *)kzalloc(data_num * 7 + 1, GFP_KERNEL); + if (!tmp_log) { + NVT_ERR("kzalloc for tmp_log failed!\n "); + return; + } + + for (i = 0; i < data_num; i++) { + sprintf(tmp_log + i * 7, "%5d, ", data[i]); + } + tmp_log[data_num * 7] = '\0'; + printk("%s", tmp_log); + if (tmp_log) { + kfree(tmp_log); + tmp_log = NULL; + } + + return; +} + +static void nvt_print_result_log_in_one_line(uint8_t *result, + int32_t result_num) +{ + char *tmp_log = NULL; + int32_t i = 0; + + tmp_log = (char *)kzalloc(result_num * 6 + 1, GFP_KERNEL); + if (!tmp_log) { + NVT_ERR("kzalloc for tmp_log failed!\n "); + return; + } + + for (i = 0; i < result_num; i++) { + sprintf(tmp_log + i * 6, "0x%02X, ", result[i]); + } + tmp_log[result_num * 6] = '\0'; + printk("%s", tmp_log); + if (tmp_log) { + kfree(tmp_log); + tmp_log = NULL; + } + + return; +} + +/******************************************************* +Description: + Novatek touchscreen self-test criteria print function. + +return: + n.a. +*******************************************************/ +static void nvt_print_lmt_array(int32_t *array, int32_t x_ch, int32_t y_ch) +{ + int32_t j = 0; + + for (j = 0; j < y_ch; j++) { + nvt_print_data_log_in_one_line(array + j * x_ch, x_ch); + printk("\n"); + } +#if TOUCH_KEY_NUM > 0 + nvt_print_data_log_in_one_line(array + y_ch * x_ch, Key_Channel); + printk("\n"); +#endif /* #if TOUCH_KEY_NUM > 0 */ +} + +static void nvt_print_criteria(void) +{ + NVT_LOG("++\n"); + + //---PS_Config_Lmt_Short_Rawdata--- + printk("PS_Config_Lmt_Short_Rawdata_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Short_Rawdata_P, X_Channel, + Y_Channel); + printk("PS_Config_Lmt_Short_Rawdata_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Short_Rawdata_N, X_Channel, + Y_Channel); + + //---PS_Config_Lmt_Open_Rawdata--- + printk("PS_Config_Lmt_Open_Rawdata_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Open_Rawdata_P, X_Channel, Y_Channel); + printk("PS_Config_Lmt_Open_Rawdata_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Open_Rawdata_N, X_Channel, Y_Channel); + + //---PS_Config_Lmt_FW_Rawdata--- + printk("PS_Config_Lmt_FW_Rawdata_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Rawdata_P, X_Channel, Y_Channel); + printk("PS_Config_Lmt_FW_Rawdata_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Rawdata_N, X_Channel, Y_Channel); + + //---PS_Config_Lmt_FW_CC--- + printk("PS_Config_Lmt_FW_CC_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_CC_P, X_Channel, Y_Channel); + printk("PS_Config_Lmt_FW_CC_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_CC_N, X_Channel, Y_Channel); + + //---PS_Config_Lmt_FW_Diff--- + printk("PS_Config_Lmt_FW_Diff_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Diff_P, X_Channel, Y_Channel); + printk("PS_Config_Lmt_FW_Diff_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Diff_N, X_Channel, Y_Channel); + + if (ts->pen_support) { + //---PS_Config_Lmt_PenTipX_FW_Raw--- + printk("PS_Config_Lmt_PenTipX_FW_Raw_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipX_FW_Raw_P, ts->x_num, + ts->y_gang_num); + printk("PS_Config_Lmt_PenTipX_FW_Raw_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipX_FW_Raw_N, ts->x_num, + ts->y_gang_num); + + //---PS_Config_Lmt_PenTipY_FW_Raw--- + printk("PS_Config_Lmt_PenTipY_FW_Raw_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipY_FW_Raw_P, + ts->x_gang_num, ts->y_num); + printk("PS_Config_Lmt_PenTipY_FW_Raw_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipY_FW_Raw_N, + ts->x_gang_num, ts->y_num); + + //---PS_Config_Lmt_PenRingX_FW_Raw--- + printk("PS_Config_Lmt_PenRingX_FW_Raw_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingX_FW_Raw_P, ts->x_num, + ts->y_gang_num); + printk("PS_Config_Lmt_PenRingX_FW_Raw_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingX_FW_Raw_N, ts->x_num, + ts->y_gang_num); + + //---PS_Config_Lmt_PenRingY_FW_Raw--- + printk("PS_Config_Lmt_PenRingY_FW_Raw_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingY_FW_Raw_P, + ts->x_gang_num, ts->y_num); + printk("PS_Config_Lmt_PenRingY_FW_Raw_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingY_FW_Raw_N, + ts->x_gang_num, ts->y_num); + + //---PS_Config_Lmt_PenTipX_FW_Diff--- + printk("PS_Config_Lmt_PenTipX_FW_Diff_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipX_FW_Diff_P, ts->x_num, + ts->y_gang_num); + printk("PS_Config_Lmt_PenTipX_FW_Diff_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipX_FW_Diff_N, ts->x_num, + ts->y_gang_num); + + //---PS_Config_Lmt_PenTipY_FW_Diff--- + printk("PS_Config_Lmt_PenTipY_FW_Diff_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipY_FW_Diff_P, + ts->x_gang_num, ts->y_num); + printk("PS_Config_Lmt_PenTipY_FW_Diff_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenTipY_FW_Diff_N, + ts->x_gang_num, ts->y_num); + + //---PS_Config_Lmt_PenRingX_FW_Diff--- + printk("PS_Config_Lmt_PenRingX_FW_Diff_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingX_FW_Diff_P, ts->x_num, + ts->y_gang_num); + printk("PS_Config_Lmt_PenRingX_FW_Diff_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingX_FW_Diff_N, ts->x_num, + ts->y_gang_num); + + //---PS_Config_Lmt_PenRingY_FW_Diff--- + printk("PS_Config_Lmt_PenRingY_FW_Diff_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingY_FW_Diff_P, + ts->x_gang_num, ts->y_num); + printk("PS_Config_Lmt_PenRingY_FW_Diff_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_PenRingY_FW_Diff_N, + ts->x_gang_num, ts->y_num); + } /* if (ts->pen_support) */ + + NVT_LOG("--\n"); +} + +#ifndef NVT_SAVE_TESTDATA_IN_FILE +void dump_buff(int32_t *rawdata, uint8_t x_ch, uint8_t y_ch) +{ + int32_t y = 0; + + for (y = 0; y < y_ch; y++) { + nvt_print_data_log_in_one_line(rawdata + y * x_ch, x_ch); + printk("\n"); + } +} +#endif + +static int32_t nvt_save_rawdata_to_csv(int32_t *rawdata, uint8_t x_ch, + uint8_t y_ch, const char *file_path, + uint32_t offset, enum test_type type) +{ +#ifdef NVT_SAVE_TESTDATA_IN_FILE + int32_t x = 0; + int32_t y = 0; + int32_t iArrayIndex = 0; + struct file *fp = NULL; + char *fbufp = NULL; + mm_segment_t org_fs; + int32_t write_ret = 0; + uint32_t output_len = 0; + loff_t pos = 0; +#if TOUCH_KEY_NUM > 0 + int32_t k = 0; + int32_t keydata_output_offset = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ +#else /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + struct test_buf *tbuf = ts->testdata; +#endif /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + + printk("%s:++\n", __func__); +#ifdef NVT_SAVE_TESTDATA_IN_FILE + fbufp = (char *)kzalloc(16384, GFP_KERNEL); + if (!fbufp) { + NVT_ERR("kzalloc for fbufp failed!\n"); + return -ENOMEM; + } + + for (y = 0; y < y_ch; y++) { + for (x = 0; x < x_ch; x++) { + iArrayIndex = y * x_ch + x; + sprintf(fbufp + iArrayIndex * 7 + y * 2, "%5d, ", + rawdata[iArrayIndex]); + } + nvt_print_data_log_in_one_line(rawdata + y * x_ch, x_ch); + printk("\n"); + sprintf(fbufp + (iArrayIndex + 1) * 7 + y * 2, "\r\n"); + } +#if TOUCH_KEY_NUM > 0 + keydata_output_offset = y_ch * x_ch * 7 + y_ch * 2; + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = y_ch * x_ch + k; + sprintf(fbufp + keydata_output_offset + k * 7, "%5d, ", + rawdata[iArrayIndex]); + } + nvt_print_data_log_in_one_line(rawdata + y_ch * x_ch, Key_Channel); + printk("\n"); + sprintf(fbufp + y_ch * x_ch * 7 + y_ch * 2 + Key_Channel * 7, "\r\n"); +#endif /* #if TOUCH_KEY_NUM > 0 */ + + org_fs = get_fs(); + set_fs(KERNEL_DS); + fp = filp_open(file_path, O_RDWR | O_CREAT, 0644); + if (fp == NULL || IS_ERR(fp)) { + NVT_ERR("open %s failed\n", file_path); + set_fs(org_fs); + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } + return -1; + } + +#if TOUCH_KEY_NUM > 0 + output_len = y_ch * x_ch * 7 + y_ch * 2 + Key_Channel * 7 + 2; +#else + output_len = y_ch * x_ch * 7 + y_ch * 2; +#endif /* #if TOUCH_KEY_NUM > 0 */ + pos = offset; + write_ret = vfs_write(fp, (char __user *)fbufp, output_len, &pos); + if (write_ret <= 0) { + NVT_ERR("write %s failed\n", file_path); + set_fs(org_fs); + if (fp) { + filp_close(fp, NULL); + fp = NULL; + } + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } + return -1; + } + + set_fs(org_fs); + if (fp) { + filp_close(fp, NULL); + fp = NULL; + } + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } +#else /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + switch (type) { + case SHORT_TEST: + NVT_LOG("SHORT_TEST start copy TEST_BUF_LEN = %d", + TEST_BUF_LEN); + memset(tbuf->shorttest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->shorttest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->shorttest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST(%p):=============\n", + tbuf->shorttest.buf); + dump_buff((int32_t *)tbuf->shorttest.buf, x_ch, y_ch); + NVT_LOG("SHORT_TEST copy complete"); + break; + case OPEN_TEST: + NVT_LOG("OPEN_TEST start copy"); + memset(tbuf->opentest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->opentest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->opentest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST(%p):=============\n", + tbuf->opentest.buf); + dump_buff((int32_t *)tbuf->opentest.buf, x_ch, y_ch); + NVT_LOG("OPEN_TEST copy complete"); + break; + case FWMUTUAL_TEST: + NVT_LOG("FWMUTUAL_TEST start copy"); + memset(tbuf->fwmutualtest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->fwmutualtest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->fwmutualtest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->fwmutualtest.buf, x_ch, y_ch); + NVT_LOG("FWMUTUAL_TEST copy complete"); + break; + case FWCC_TEST: + NVT_LOG("FWCC_TEST start copy"); + memset(tbuf->fwcctest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->fwcctest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->fwcctest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->fwcctest.buf, x_ch, y_ch); + NVT_LOG("FWCC_TEST copy complete"); + break; + case NOISE_MAX_TEST: + NVT_LOG("NOISE_MAX_TEST start copy"); + memset(tbuf->noisetest_max.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->noisetest_max.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->noisetest_max.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->noisetest_max.buf, x_ch, y_ch); + NVT_LOG("NOISE_MAX_TEST copy complete"); + break; + case NOISE_MIN_TEST: + NVT_LOG("NOISE_MIN_TEST start copy"); + memset(tbuf->noisetest_min.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->noisetest_min.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->noisetest_min.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->noisetest_min.buf, x_ch, y_ch); + NVT_LOG("NOISE_MIN_TEST copy complete"); + break; + case PEN_TIPX_RAW: + NVT_LOG("PEN_TIPX_RAW start copy"); + memset(tbuf->pen_tipx_raw.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_tipx_raw.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_tipx_raw.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_tipx_raw.buf, x_ch, y_ch); + NVT_LOG("PEN_TIPX_RAW copy complete"); + break; + case PEN_TIPY_RAW: + NVT_LOG("PEN_TIPY_RAW start copy"); + memset(tbuf->pen_tipy_raw.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_tipy_raw.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_tipy_raw.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_tipy_raw.buf, x_ch, y_ch); + NVT_LOG("PEN_TIPY_RAW copy complete"); + break; + case PEN_RINGX_RAW: + NVT_LOG("PEN_RINGX_RAW start copy"); + memset(tbuf->pen_ringx_raw.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_ringx_raw.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_ringx_raw.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_ringx_raw.buf, x_ch, y_ch); + NVT_LOG("PEN_RINGX_RAW copy complete"); + break; + case PEN_RINGY_RAW: + NVT_LOG("PEN_RINGY_RAW start copy"); + memset(tbuf->pen_ringy_raw.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_ringy_raw.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_ringy_raw.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_ringy_raw.buf, x_ch, y_ch); + NVT_LOG("PEN_RINGY_RAW copy complete"); + break; + case PEN_TIPX_DIFFMAX: + NVT_LOG("PEN_TIPX_DIFFMAX start copy"); + memset(tbuf->pen_tipx_diffmax.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_tipx_diffmax.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_tipx_diffmax.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_tipx_diffmax.buf, x_ch, y_ch); + NVT_LOG("PEN_TIPX_DIFFMAX copy complete"); + break; + case PEN_TIPX_DIFFMIN: + NVT_LOG("PEN_TIPX_DIFFMIN start copy"); + memset(tbuf->pen_tipx_diffmin.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_tipx_diffmin.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_tipx_diffmin.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_tipx_diffmin.buf, x_ch, y_ch); + NVT_LOG("PEN_TIPX_DIFFMIN copy complete"); + break; + case PEN_TIPY_DIFFMAX: + NVT_LOG("PEN_TIPY_DIFFMAX start copy"); + memset(tbuf->pen_tipy_diffmax.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_tipy_diffmax.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_tipy_diffmax.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_tipy_diffmax.buf, x_ch, y_ch); + NVT_LOG("PEN_TIPY_DIFFMAX copy complete"); + break; + case PEN_TIPY_DIFFMIN: + NVT_LOG("PEN_TIPY_DIFFMIN start copy"); + memset(tbuf->pen_tipy_diffmin.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_tipy_diffmin.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_tipy_diffmin.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_tipy_diffmin.buf, x_ch, y_ch); + NVT_LOG("PEN_TIPY_DIFFMIN copy complete"); + break; + case PEN_RINGX_DIFFMAX: + NVT_LOG("PEN_RINGX_DIFFMAX start copy"); + memset(tbuf->pen_ringx_diffmax.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_ringx_diffmax.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_ringx_diffmax.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_ringx_diffmax.buf, x_ch, y_ch); + NVT_LOG("PEN_RINGX_DIFFMAX copy complete"); + break; + case PEN_RINGX_DIFFMIN: + NVT_LOG("PEN_RINGX_DIFFMIN start copy"); + memset(tbuf->pen_ringx_diffmin.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_ringx_diffmin.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_ringx_diffmin.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_ringx_diffmin.buf, x_ch, y_ch); + NVT_LOG("PEN_RINGX_DIFFMIN copy complete"); + break; + case PEN_RINGY_DIFFMAX: + NVT_LOG("PEN_RINGY_DIFFMAX start copy"); + memset(tbuf->pen_ringy_diffmax.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_ringy_diffmax.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_ringy_diffmax.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_ringy_diffmax.buf, x_ch, y_ch); + NVT_LOG("PEN_RINGY_DIFFMAX copy complete"); + break; + case PEN_RINGY_DIFFMIN: + NVT_LOG("PEN_RINGY_DIFFMIN start copy"); + memset(tbuf->pen_ringy_diffmin.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->pen_ringy_diffmin.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->pen_ringy_diffmin.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->pen_ringy_diffmin.buf, x_ch, y_ch); + NVT_LOG("PEN_RINGY_DIFFMIN copy complete"); + break; + default: + NVT_ERR("test type is illegal"); + break; + } +#endif /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + printk("%s:--\n", __func__); + + return 0; +} + +static int32_t nvt_polling_hand_shake_status(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 250; + + for (i = 0; i < retry; i++) { + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + //---read fw status--- + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + + if ((buf[1] == 0xA0) || (buf[1] == 0xA1)) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("polling hand shake status failed, buf[1]=0x%02X\n", + buf[1]); + + // Read back 5 bytes from offset EVENT_MAP_HOST_CMD for debug check + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + buf[5] = 0x00; + CTP_SPI_READ(ts->client, buf, 6); + NVT_ERR("Read back 5 bytes from offset EVENT_MAP_HOST_CMD: 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X\n", + buf[1], buf[2], buf[3], buf[4], buf[5]); + + return -1; + } else { + return 0; + } +} + +static int8_t nvt_switch_FreqHopEnDis(uint8_t FreqHopEnDis) +{ + uint8_t buf[8] = { 0 }; + uint8_t retry = 0; + int8_t ret = 0; + + NVT_LOG("++\n"); + + for (retry = 0; retry < 20; retry++) { + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + //---switch FreqHopEnDis--- + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = FreqHopEnDis; + CTP_SPI_WRITE(ts->client, buf, 2); + + msleep(35); + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + if (buf[1] == 0x00) + break; + } + + if (unlikely(retry == 20)) { + NVT_ERR("switch FreqHopEnDis 0x%02X failed, buf[1]=0x%02X\n", + FreqHopEnDis, buf[1]); + ret = -1; + } + + NVT_LOG("--\n"); + + return ret; +} + +static int32_t nvt_read_baseline(int32_t *xdata) +{ + uint8_t x_num = 0; + uint8_t y_num = 0; + uint32_t x = 0; + uint32_t y = 0; + int32_t iArrayIndex = 0; +#if TOUCH_KEY_NUM > 0 + int32_t k = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ + + NVT_LOG("++\n"); + + nvt_read_mdata(ts->mmap->BASELINE_ADDR, ts->mmap->BASELINE_BTN_ADDR); + + nvt_get_mdata(xdata, &x_num, &y_num); + + for (y = 0; y < y_num; y++) { + for (x = 0; x < x_num; x++) { + iArrayIndex = y * x_num + x; + xdata[iArrayIndex] = (int16_t)xdata[iArrayIndex]; + } + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = Y_Channel * X_Channel + k; + xdata[iArrayIndex] = (int16_t)xdata[iArrayIndex]; + } +#endif /* #if TOUCH_KEY_NUM > 0 */ + + printk("%s:\n", __func__); + // Save Rawdata to CSV file + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, + FW_RAWDATA_CSV_FILE, 0, + FWMUTUAL_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("--\n"); + + return 0; +} + +static int32_t nvt_read_CC(int32_t *xdata) +{ + uint8_t x_num = 0; + uint8_t y_num = 0; + uint32_t x = 0; + uint32_t y = 0; + int32_t iArrayIndex = 0; +#if TOUCH_KEY_NUM > 0 + int32_t k = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ + + NVT_LOG("++\n"); + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->DIFF_PIPE1_ADDR, + ts->mmap->DIFF_BTN_PIPE1_ADDR); + else + nvt_read_mdata(ts->mmap->DIFF_PIPE0_ADDR, + ts->mmap->DIFF_BTN_PIPE0_ADDR); + + nvt_get_mdata(xdata, &x_num, &y_num); + + for (y = 0; y < y_num; y++) { + for (x = 0; x < x_num; x++) { + iArrayIndex = y * x_num + x; + xdata[iArrayIndex] = (int16_t)xdata[iArrayIndex]; + } + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = Y_Channel * X_Channel + k; + xdata[iArrayIndex] = (int16_t)xdata[iArrayIndex]; + } +#endif /* #if TOUCH_KEY_NUM > 0 */ + + printk("%s:\n", __func__); + // Save Rawdata to CSV file + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, FW_CC_CSV_FILE, + 0, FWCC_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("--\n"); + + return 0; +} + +static int32_t nvt_read_pen_baseline(void) +{ + uint32_t csv_output_offset = 0; + + NVT_LOG("++\n"); + + nvt_read_get_num_mdata(ts->mmap->PEN_2D_BL_TIP_X_ADDR, + RawData_PenTipX_Raw, ts->x_num * ts->y_gang_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_BL_TIP_Y_ADDR, + RawData_PenTipY_Raw, ts->x_gang_num * ts->y_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_BL_RING_X_ADDR, + RawData_PenRingX_Raw, + ts->x_num * ts->y_gang_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_BL_RING_Y_ADDR, + RawData_PenRingY_Raw, + ts->x_gang_num * ts->y_num); + + // Save Rawdata to CSV file + printk("%s:RawData_PenTipX_Raw\n", __func__); + if (nvt_save_rawdata_to_csv(RawData_PenTipX_Raw, ts->x_num, + ts->y_gang_num, PEN_FW_RAW_TEST_CSV_FILE, + csv_output_offset, PEN_TIPX_RAW) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_output_offset += + ts->y_gang_num * ts->x_num * 7 + ts->y_gang_num * 2; + printk("%s:RawData_PenTipY_Raw\n", __func__); + if (nvt_save_rawdata_to_csv(RawData_PenTipY_Raw, ts->x_gang_num, + ts->y_num, PEN_FW_RAW_TEST_CSV_FILE, + csv_output_offset, PEN_TIPY_RAW) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_output_offset += ts->y_num * ts->x_gang_num * 7 + ts->y_num * 2; + printk("%s:RawData_PenRingX_Raw\n", __func__); + if (nvt_save_rawdata_to_csv(RawData_PenRingX_Raw, ts->x_num, + ts->y_gang_num, PEN_FW_RAW_TEST_CSV_FILE, + csv_output_offset, PEN_RINGX_RAW) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_output_offset += + ts->y_gang_num * ts->x_num * 7 + ts->y_gang_num * 2; + printk("%s:RawData_PenRingY_Raw\n", __func__); + if (nvt_save_rawdata_to_csv(RawData_PenRingY_Raw, ts->x_gang_num, + ts->y_num, PEN_FW_RAW_TEST_CSV_FILE, + csv_output_offset, PEN_RINGY_RAW) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("--\n"); + + return 0; +} + +static void nvt_enable_noise_collect(int32_t frame_num) +{ + uint8_t buf[8] = { 0 }; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + //---enable noise collect--- + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x47; + buf[2] = 0xAA; + buf[3] = frame_num; + buf[4] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 5); +} + +static int32_t nvt_read_fw_noise(int32_t *xdata) +{ + uint8_t x_num = 0; + uint8_t y_num = 0; + uint32_t x = 0; + uint32_t y = 0; + int32_t iArrayIndex = 0; + int32_t frame_num = 0; + uint32_t rawdata_diff_min_offset = 0; +#if TOUCH_KEY_NUM > 0 + int32_t k = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ + uint32_t csv_pen_noise_offset = 0; + + NVT_LOG("++\n"); + + //---Enter Test Mode--- + if (nvt_clear_fw_status()) { + return -EAGAIN; + } + + frame_num = PS_Config_Diff_Test_Frame / 10; + if (frame_num <= 0) + frame_num = 1; + printk("%s: frame_num=%d\n", __func__, frame_num); + nvt_enable_noise_collect(frame_num); + // need wait PS_Config_Diff_Test_Frame * 8.3ms + msleep(frame_num * 83); + + if (nvt_polling_hand_shake_status()) { + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + return -EAGAIN; + } + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->DIFF_PIPE0_ADDR, + ts->mmap->DIFF_BTN_PIPE0_ADDR); + else + nvt_read_mdata(ts->mmap->DIFF_PIPE1_ADDR, + ts->mmap->DIFF_BTN_PIPE1_ADDR); + + nvt_get_mdata(xdata, &x_num, &y_num); + + for (y = 0; y < y_num; y++) { + for (x = 0; x < x_num; x++) { + iArrayIndex = y * x_num + x; + RawData_Diff_Max[iArrayIndex] = + (int8_t)((xdata[iArrayIndex] >> 8) & 0xFF); + RawData_Diff_Min[iArrayIndex] = + (int8_t)(xdata[iArrayIndex] & 0xFF); + } + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = Y_Channel * X_Channel + k; + RawData_Diff_Max[iArrayIndex] = + (int8_t)((xdata[iArrayIndex] >> 8) & 0xFF); + RawData_Diff_Min[iArrayIndex] = + (int8_t)(xdata[iArrayIndex] & 0xFF); + } +#endif /* #if TOUCH_KEY_NUM > 0 */ + + if (ts->pen_support) { + // get pen noise data + nvt_read_get_num_mdata(ts->mmap->PEN_2D_DIFF_TIP_X_ADDR, + RawData_PenTipX_DiffMax, + ts->x_num * ts->y_gang_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_RAW_TIP_X_ADDR, + RawData_PenTipX_DiffMin, + ts->x_num * ts->y_gang_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_DIFF_TIP_Y_ADDR, + RawData_PenTipY_DiffMax, + ts->x_gang_num * ts->y_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_RAW_TIP_Y_ADDR, + RawData_PenTipY_DiffMin, + ts->x_gang_num * ts->y_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_DIFF_RING_X_ADDR, + RawData_PenRingX_DiffMax, + ts->x_num * ts->y_gang_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_RAW_RING_X_ADDR, + RawData_PenRingX_DiffMin, + ts->x_num * ts->y_gang_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_DIFF_RING_Y_ADDR, + RawData_PenRingY_DiffMax, + ts->x_gang_num * ts->y_num); + nvt_read_get_num_mdata(ts->mmap->PEN_2D_RAW_RING_Y_ADDR, + RawData_PenRingY_DiffMin, + ts->x_gang_num * ts->y_num); + } /* if (ts->pen_support) */ + + //---Leave Test Mode--- + nvt_change_mode(NORMAL_MODE); + + printk("%s:RawData_Diff_Max:\n", __func__); + // Save Rawdata to CSV file + if (nvt_save_rawdata_to_csv(RawData_Diff_Max, X_Channel, Y_Channel, + NOISE_TEST_CSV_FILE, 0, + NOISE_MAX_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + +#if TOUCH_KEY_NUM > 0 + rawdata_diff_min_offset = + Y_Channel * X_Channel * 7 + Y_Channel * 2 + Key_Channel * 7 + 2; +#else + rawdata_diff_min_offset = Y_Channel * X_Channel * 7 + Y_Channel * 2; +#endif /* #if TOUCH_KEY_NUM > 0 */ + printk("%s:RawData_Diff_Min:\n", __func__); + // Save Rawdata to CSV file + if (nvt_save_rawdata_to_csv( + RawData_Diff_Min, X_Channel, Y_Channel, NOISE_TEST_CSV_FILE, + rawdata_diff_min_offset, NOISE_MIN_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + if (ts->pen_support) { + // save pen noise to csv + printk("%s:RawData_PenTipX_DiffMax:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenTipX_DiffMax, ts->x_num, ts->y_gang_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_TIPX_DIFFMAX) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_pen_noise_offset += + ts->y_gang_num * ts->x_num * 7 + ts->y_gang_num * 2; + printk("%s:RawData_PenTipX_DiffMin:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenTipX_DiffMin, ts->x_num, ts->y_gang_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_TIPX_DIFFMIN) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_pen_noise_offset += + ts->y_gang_num * ts->x_num * 7 + ts->y_gang_num * 2; + printk("%s:RawData_PenTipY_DiffMax:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenTipY_DiffMax, ts->x_gang_num, ts->y_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_TIPY_DIFFMAX) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_pen_noise_offset += + ts->y_num * ts->x_gang_num * 7 + ts->y_num * 2; + printk("%s:RawData_PenTipY_DiffMin:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenTipY_DiffMin, ts->x_gang_num, ts->y_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_TIPY_DIFFMIN) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_pen_noise_offset += + ts->y_num * ts->x_gang_num * 7 + ts->y_num * 2; + printk("%s:RawData_PenRingX_DiffMax:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenRingX_DiffMax, ts->x_num, ts->y_gang_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_RINGX_DIFFMAX) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_pen_noise_offset += + ts->y_gang_num * ts->x_num * 7 + ts->y_gang_num * 2; + printk("%s:RawData_PenRingX_DiffMin:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenRingX_DiffMin, ts->x_num, ts->y_gang_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_RINGX_DIFFMIN) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_pen_noise_offset += + ts->y_gang_num * ts->x_num * 7 + ts->y_gang_num * 2; + printk("%s:RawData_PenRingY_DiffMax:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenRingY_DiffMax, ts->x_gang_num, ts->y_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_RINGY_DIFFMAX) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + csv_pen_noise_offset += + ts->y_num * ts->x_gang_num * 7 + ts->y_num * 2; + printk("%s:RawData_PenRingY_DiffMin:\n", __func__); + if (nvt_save_rawdata_to_csv( + RawData_PenRingY_DiffMin, ts->x_gang_num, ts->y_num, + PEN_NOISE_TEST_CSV_FILE, csv_pen_noise_offset, + PEN_RINGY_DIFFMIN) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + } /* if (ts->pen_support) */ + + NVT_LOG("--\n"); + + return 0; +} + +static void nvt_enable_open_test(void) +{ + uint8_t buf[8] = { 0 }; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + //---enable open test--- + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x45; + buf[2] = 0xAA; + buf[3] = 0x02; + buf[4] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 5); +} + +static void nvt_enable_short_test(void) +{ + uint8_t buf[8] = { 0 }; + + //---set xdata index to EVENT BUF ADDR--- + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + //---enable short test--- + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x43; + buf[2] = 0xAA; + buf[3] = 0x02; + buf[4] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 5); +} + +static int32_t nvt_read_fw_open(int32_t *xdata) +{ + uint32_t raw_pipe_addr = 0; + uint8_t *rawdata_buf = NULL; + uint32_t x = 0; + uint32_t y = 0; + uint8_t buf[128] = { 0 }; +#if TOUCH_KEY_NUM > 0 + uint32_t raw_btn_pipe_addr = 0; + int32_t k = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ + + NVT_LOG("++\n"); + + //---Enter Test Mode--- + if (nvt_clear_fw_status()) { + return -EAGAIN; + } + + nvt_enable_open_test(); + + if (nvt_polling_hand_shake_status()) { + return -EAGAIN; + } + +#if TOUCH_KEY_NUM > 0 + rawdata_buf = (uint8_t *)kzalloc( + (IC_X_CFG_SIZE * IC_Y_CFG_SIZE + IC_KEY_CFG_SIZE) * 2, + GFP_KERNEL); +#else + rawdata_buf = (uint8_t *)kzalloc(IC_X_CFG_SIZE * IC_Y_CFG_SIZE * 2, + GFP_KERNEL); +#endif /* #if TOUCH_KEY_NUM > 0 */ + if (!rawdata_buf) { + NVT_ERR("kzalloc for rawdata_buf failed!\n"); + return -ENOMEM; + } + + if (nvt_get_fw_pipe() == 0) + raw_pipe_addr = ts->mmap->RAW_PIPE0_ADDR; + else + raw_pipe_addr = ts->mmap->RAW_PIPE1_ADDR; + + for (y = 0; y < IC_Y_CFG_SIZE; y++) { + //---change xdata index--- + nvt_set_page(raw_pipe_addr + y * IC_X_CFG_SIZE * 2); + buf[0] = (uint8_t)((raw_pipe_addr + y * IC_X_CFG_SIZE * 2) & + 0xFF); + CTP_SPI_READ(ts->client, buf, IC_X_CFG_SIZE * 2 + 1); + memcpy(rawdata_buf + y * IC_X_CFG_SIZE * 2, buf + 1, + IC_X_CFG_SIZE * 2); + } +#if TOUCH_KEY_NUM > 0 + if (nvt_get_fw_pipe() == 0) + raw_btn_pipe_addr = ts->mmap->RAW_BTN_PIPE0_ADDR; + else + raw_btn_pipe_addr = ts->mmap->RAW_BTN_PIPE1_ADDR; + + //---change xdata index--- + nvt_set_page(raw_btn_pipe_addr); + buf[0] = (uint8_t)(raw_btn_pipe_addr & 0xFF); + CTP_SPI_READ(ts->client, buf, IC_KEY_CFG_SIZE * 2 + 1); + memcpy(rawdata_buf + IC_Y_CFG_SIZE * IC_X_CFG_SIZE * 2, buf + 1, + IC_KEY_CFG_SIZE * 2); +#endif /* #if TOUCH_KEY_NUM > 0 */ + + for (y = 0; y < IC_Y_CFG_SIZE; y++) { + for (x = 0; x < IC_X_CFG_SIZE; x++) { + if ((AIN_Y[y] != 0xFF) && (AIN_X[x] != 0xFF)) { + xdata[AIN_Y[y] * X_Channel + AIN_X[x]] = (int16_t)(( + rawdata_buf[(y * IC_X_CFG_SIZE + x) * 2] + + 256 * rawdata_buf[(y * IC_X_CFG_SIZE + + x) * 2 + + 1])); + } + } + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < IC_KEY_CFG_SIZE; k++) { + if (AIN_KEY[k] != 0xFF) + xdata[Y_Channel * X_Channel + AIN_KEY[k]] = + (int16_t)(rawdata_buf[(IC_Y_CFG_SIZE * + IC_X_CFG_SIZE + + k) * + 2] + + 256 * rawdata_buf[(IC_Y_CFG_SIZE * + IC_X_CFG_SIZE + + k) * 2 + + 1]); + } +#endif /* #if TOUCH_KEY_NUM > 0 */ + + if (rawdata_buf) { + kfree(rawdata_buf); + rawdata_buf = NULL; + } + + //---Leave Test Mode--- + nvt_change_mode(NORMAL_MODE); + + printk("%s:RawData_Open\n", __func__); + // Save RawData to CSV file + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, + OPEN_TEST_CSV_FILE, 0, OPEN_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("--\n"); + + return 0; +} + +static int32_t nvt_read_fw_short(int32_t *xdata) +{ + uint32_t raw_pipe_addr = 0; + uint8_t *rawdata_buf = NULL; + uint32_t x = 0; + uint32_t y = 0; + uint8_t buf[128] = { 0 }; + int32_t iArrayIndex = 0; +#if TOUCH_KEY_NUM > 0 + uint32_t raw_btn_pipe_addr = 0; + int32_t k = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ + + NVT_LOG("++\n"); + + //---Enter Test Mode--- + if (nvt_clear_fw_status()) { + return -EAGAIN; + } + + nvt_enable_short_test(); + + if (nvt_polling_hand_shake_status()) { + return -EAGAIN; + } + +#if TOUCH_KEY_NUM > 0 + rawdata_buf = (uint8_t *)kzalloc( + (X_Channel * Y_Channel + Key_Channel) * 2, GFP_KERNEL); +#else + rawdata_buf = (uint8_t *)kzalloc(X_Channel * Y_Channel * 2, GFP_KERNEL); +#endif /* #if TOUCH_KEY_NUM > 0 */ + if (!rawdata_buf) { + NVT_ERR("kzalloc for rawdata_buf failed!\n"); + return -ENOMEM; + } + + if (nvt_get_fw_pipe() == 0) + raw_pipe_addr = ts->mmap->RAW_PIPE0_ADDR; + else + raw_pipe_addr = ts->mmap->RAW_PIPE1_ADDR; + + for (y = 0; y < Y_Channel; y++) { + //---change xdata index--- + nvt_set_page(raw_pipe_addr + y * X_Channel * 2); + buf[0] = (uint8_t)((raw_pipe_addr + y * X_Channel * 2) & 0xFF); + CTP_SPI_READ(ts->client, buf, X_Channel * 2 + 1); + memcpy(rawdata_buf + y * X_Channel * 2, buf + 1, X_Channel * 2); + } +#if TOUCH_KEY_NUM > 0 + if (nvt_get_fw_pipe() == 0) + raw_btn_pipe_addr = ts->mmap->RAW_BTN_PIPE0_ADDR; + else + raw_btn_pipe_addr = ts->mmap->RAW_BTN_PIPE1_ADDR; + + //---change xdata index--- + nvt_set_page(raw_btn_pipe_addr); + buf[0] = (uint8_t)(raw_btn_pipe_addr & 0xFF); + CTP_SPI_READ(ts->client, buf, Key_Channel * 2 + 1); + memcpy(rawdata_buf + Y_Channel * X_Channel * 2, buf + 1, + Key_Channel * 2); +#endif /* #if TOUCH_KEY_NUM > 0 */ + + for (y = 0; y < Y_Channel; y++) { + for (x = 0; x < X_Channel; x++) { + iArrayIndex = y * X_Channel + x; + xdata[iArrayIndex] = + (int16_t)(rawdata_buf[iArrayIndex * 2] + + 256 * rawdata_buf[iArrayIndex * 2 + + 1]); + } + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = Y_Channel * X_Channel + k; + xdata[iArrayIndex] = + (int16_t)(rawdata_buf[iArrayIndex * 2] + + 256 * rawdata_buf[iArrayIndex * 2 + 1]); + } +#endif /* #if TOUCH_KEY_NUM > 0 */ + + if (rawdata_buf) { + kfree(rawdata_buf); + rawdata_buf = NULL; + } + + //---Leave Test Mode--- + nvt_change_mode(NORMAL_MODE); + + printk("%s:RawData_Short\n", __func__); + // Save Rawdata to CSV file + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, + SHORT_TEST_CSV_FILE, 0, SHORT_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("--\n"); + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen raw data test for each single point function. + +return: + Executive outcomes. 0---passed. negative---failed. +*******************************************************/ +static int32_t RawDataTest_SinglePoint_Sub(int32_t rawdata[], + uint8_t RecordResult[], uint8_t x_ch, + uint8_t y_ch, + int32_t Rawdata_Limit_Postive[], + int32_t Rawdata_Limit_Negative[]) +{ + int32_t i = 0; + int32_t j = 0; +#if TOUCH_KEY_NUM > 0 + int32_t k = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ + int32_t iArrayIndex = 0; + bool isPass = true; + + for (j = 0; j < y_ch; j++) { + for (i = 0; i < x_ch; i++) { + iArrayIndex = j * x_ch + i; + + RecordResult[iArrayIndex] = + 0x00; // default value for PASS + + if (rawdata[iArrayIndex] > + Rawdata_Limit_Postive[iArrayIndex]) + RecordResult[iArrayIndex] |= 0x01; + + if (rawdata[iArrayIndex] < + Rawdata_Limit_Negative[iArrayIndex]) + RecordResult[iArrayIndex] |= 0x02; + } + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = y_ch * x_ch + k; + + RecordResult[iArrayIndex] = 0x00; // default value for PASS + + if (rawdata[iArrayIndex] > Rawdata_Limit_Postive[iArrayIndex]) + RecordResult[iArrayIndex] |= 0x01; + + if (rawdata[iArrayIndex] < Rawdata_Limit_Negative[iArrayIndex]) + RecordResult[iArrayIndex] |= 0x02; + } +#endif /* #if TOUCH_KEY_NUM > 0 */ + + //---Check RecordResult--- + for (j = 0; j < y_ch; j++) { + for (i = 0; i < x_ch; i++) { + if (RecordResult[j * x_ch + i] != 0) { + isPass = false; + break; + } + } + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = y_ch * x_ch + k; + if (RecordResult[iArrayIndex] != 0) { + isPass = false; + break; + } + } +#endif /* #if TOUCH_KEY_NUM > 0 */ + + if (isPass == false) { + return -1; // FAIL + } else { + return 0; // PASS + } +} + +/******************************************************* +Description: + Novatek touchscreen print self-test result function. + +return: + n.a. +*******************************************************/ +void print_selftest_result(struct seq_file *m, int32_t TestResult, + uint8_t RecordResult[], int32_t rawdata[], + uint8_t x_len, uint8_t y_len) +{ + int32_t i = 0; + int32_t j = 0; + int32_t iArrayIndex = 0; +#if TOUCH_KEY_NUM > 0 + int32_t k = 0; +#endif /* #if TOUCH_KEY_NUM > 0 */ + + switch (TestResult) { + case 0: + nvt_mp_seq_printf(m, " PASS!\n"); + break; + + case 1: + nvt_mp_seq_printf(m, " ERROR! Read Data FAIL!\n"); + break; + + case -1: + nvt_mp_seq_printf(m, " FAIL!\n"); + nvt_mp_seq_printf(m, "RecordResult:\n"); + for (i = 0; i < y_len; i++) { + for (j = 0; j < x_len; j++) { + iArrayIndex = i * x_len + j; + seq_printf(m, "0x%02X, ", + RecordResult[iArrayIndex]); + } + if (!nvt_mp_test_result_printed) + nvt_print_result_log_in_one_line( + RecordResult + i * x_len, x_len); + nvt_mp_seq_printf(m, "\n"); + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = y_len * x_len + k; + seq_printf(m, "0x%02X, ", RecordResult[iArrayIndex]); + } + if (!nvt_mp_test_result_printed) + nvt_print_result_log_in_one_line( + RecordResult + y_len * x_len, Key_Channel); + nvt_mp_seq_printf(m, "\n"); +#endif /* #if TOUCH_KEY_NUM > 0 */ + nvt_mp_seq_printf(m, "ReadData:\n"); + for (i = 0; i < y_len; i++) { + for (j = 0; j < x_len; j++) { + iArrayIndex = i * x_len + j; + seq_printf(m, "%5d, ", rawdata[iArrayIndex]); + } + if (!nvt_mp_test_result_printed) + nvt_print_data_log_in_one_line( + rawdata + i * x_len, x_len); + nvt_mp_seq_printf(m, "\n"); + } +#if TOUCH_KEY_NUM > 0 + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = y_len * x_len + k; + seq_printf(m, "%5d, ", rawdata[iArrayIndex]); + } + if (!nvt_mp_test_result_printed) + nvt_print_data_log_in_one_line(rawdata + y_len * x_len, + Key_Channel); + nvt_mp_seq_printf(m, "\n"); +#endif /* #if TOUCH_KEY_NUM > 0 */ + break; + } + nvt_mp_seq_printf(m, "\n"); +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print show + function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t c_show_selftest(struct seq_file *m, void *v) +{ + NVT_LOG("++\n"); + + nvt_mp_seq_printf(m, "FW Version: %d\n\n", fw_ver); + + nvt_mp_seq_printf(m, "Short Test"); + print_selftest_result(m, TestResult_Short, RecordResult_Short, + RawData_Short, X_Channel, Y_Channel); + + nvt_mp_seq_printf(m, "Open Test"); + print_selftest_result(m, TestResult_Open, RecordResult_Open, + RawData_Open, X_Channel, Y_Channel); + + nvt_mp_seq_printf(m, "FW Rawdata Test"); + if ((TestResult_FW_Rawdata == 0) || (TestResult_FW_Rawdata == 1)) { + print_selftest_result(m, TestResult_FWMutual, + RecordResult_FWMutual, RawData_FWMutual, + X_Channel, Y_Channel); + } else { // TestResult_FW_Rawdata is -1 + nvt_mp_seq_printf(m, " FAIL!\n"); + if (TestResult_FWMutual == -1) { + nvt_mp_seq_printf(m, "FW Mutual"); + print_selftest_result(m, TestResult_FWMutual, + RecordResult_FWMutual, + RawData_FWMutual, X_Channel, + Y_Channel); + } + if (TestResult_FW_CC == -1) { + nvt_mp_seq_printf(m, "FW CC"); + print_selftest_result(m, TestResult_FW_CC, + RecordResult_FW_CC, RawData_FW_CC, + X_Channel, Y_Channel); + } + } + + nvt_mp_seq_printf(m, "Noise Test"); + if ((TestResult_Noise == 0) || (TestResult_Noise == 1)) { + print_selftest_result(m, TestResult_FW_DiffMax, + RecordResult_FW_DiffMax, RawData_Diff_Max, + X_Channel, Y_Channel); + } else { // TestResult_Noise is -1 + nvt_mp_seq_printf(m, " FAIL!\n"); + if (TestResult_FW_DiffMax == -1) { + nvt_mp_seq_printf(m, "FW Diff Max"); + print_selftest_result(m, TestResult_FW_DiffMax, + RecordResult_FW_DiffMax, + RawData_Diff_Max, X_Channel, + Y_Channel); + } + if (TestResult_FW_DiffMin == -1) { + nvt_mp_seq_printf(m, "FW Diff Min"); + print_selftest_result(m, TestResult_FW_DiffMin, + RecordResult_FW_DiffMin, + RawData_Diff_Min, X_Channel, + Y_Channel); + } + } + + if (ts->pen_support) { + nvt_mp_seq_printf(m, "Pen FW Rawdata Test"); + if ((TestResult_Pen_FW_Raw == 0) || + (TestResult_Pen_FW_Raw == 1)) { + print_selftest_result(m, TestResult_Pen_FW_Raw, + RecordResult_PenTipX_Raw, + RawData_PenTipX_Raw, ts->x_num, + ts->y_gang_num); + } else { // TestResult_Pen_FW_Raw is -1 + nvt_mp_seq_printf(m, " FAIL!\n"); + if (TestResult_PenTipX_Raw == -1) { + nvt_mp_seq_printf(m, "Pen Tip X Raw"); + print_selftest_result(m, TestResult_PenTipX_Raw, + RecordResult_PenTipX_Raw, + RawData_PenTipX_Raw, + ts->x_num, + ts->y_gang_num); + } + if (TestResult_PenTipY_Raw == -1) { + nvt_mp_seq_printf(m, "Pen Tip Y Raw"); + print_selftest_result(m, TestResult_PenTipY_Raw, + RecordResult_PenTipY_Raw, + RawData_PenTipY_Raw, + ts->x_gang_num, + ts->y_num); + } + if (TestResult_PenRingX_Raw == -1) { + nvt_mp_seq_printf(m, "Pen Ring X Raw"); + print_selftest_result(m, + TestResult_PenRingX_Raw, + RecordResult_PenRingX_Raw, + RawData_PenRingX_Raw, + ts->x_num, + ts->y_gang_num); + } + if (TestResult_PenRingY_Raw == -1) { + nvt_mp_seq_printf(m, "Pen Ring Y Raw"); + print_selftest_result(m, + TestResult_PenRingY_Raw, + RecordResult_PenRingY_Raw, + RawData_PenRingY_Raw, + ts->x_gang_num, + ts->y_num); + } + } + + nvt_mp_seq_printf(m, "Pen Noise Test"); + if ((TestResult_Pen_Noise == 0) || + (TestResult_Pen_Noise == 1)) { + print_selftest_result(m, TestResult_Pen_Noise, + RecordResult_PenTipX_DiffMax, + RawData_PenTipX_DiffMax, + ts->x_num, ts->y_gang_num); + } else { // TestResult_Pen_Noise is -1 + nvt_mp_seq_printf(m, " FAIL!\n"); + if (TestResult_PenTipX_DiffMax == -1) { + nvt_mp_seq_printf(m, "Pen Tip X Diff Max"); + print_selftest_result( + m, TestResult_PenTipX_DiffMax, + RecordResult_PenTipX_DiffMax, + RawData_PenTipX_DiffMax, ts->x_num, + ts->y_gang_num); + } + if (TestResult_PenTipX_DiffMin == -1) { + nvt_mp_seq_printf(m, "Pen Tip X Diff Min"); + print_selftest_result( + m, TestResult_PenTipX_DiffMin, + RecordResult_PenTipX_DiffMin, + RawData_PenTipX_DiffMin, ts->x_num, + ts->y_gang_num); + } + if (TestResult_PenTipY_DiffMax == -1) { + nvt_mp_seq_printf(m, "Pen Tip Y Diff Max"); + print_selftest_result( + m, TestResult_PenTipY_DiffMax, + RecordResult_PenTipY_DiffMax, + RawData_PenTipY_DiffMax, ts->x_gang_num, + ts->y_num); + } + if (TestResult_PenTipY_DiffMin == -1) { + nvt_mp_seq_printf(m, "Pen Tip Y Diff Min"); + print_selftest_result( + m, TestResult_PenTipY_DiffMin, + RecordResult_PenTipY_DiffMin, + RawData_PenTipY_DiffMin, ts->x_gang_num, + ts->y_num); + } + if (TestResult_PenRingX_DiffMax == -1) { + nvt_mp_seq_printf(m, "Pen Ring X Diff Max"); + print_selftest_result( + m, TestResult_PenRingX_DiffMax, + RecordResult_PenRingX_DiffMax, + RawData_PenRingX_DiffMax, ts->x_num, + ts->y_gang_num); + } + if (TestResult_PenRingX_DiffMin == -1) { + nvt_mp_seq_printf(m, "Pen Ring X Diff Min"); + print_selftest_result( + m, TestResult_PenRingX_DiffMin, + RecordResult_PenRingX_DiffMin, + RawData_PenRingX_DiffMin, ts->x_num, + ts->y_gang_num); + } + if (TestResult_PenRingY_DiffMax == -1) { + nvt_mp_seq_printf(m, "Pen Ring Y Diff Max"); + print_selftest_result( + m, TestResult_PenRingY_DiffMax, + RecordResult_PenRingY_DiffMax, + RawData_PenRingY_DiffMax, + ts->x_gang_num, ts->y_num); + } + if (TestResult_PenRingY_DiffMin == -1) { + nvt_mp_seq_printf(m, "Pen Ring Y Diff Min"); + print_selftest_result( + m, TestResult_PenRingY_DiffMin, + RecordResult_PenRingY_DiffMin, + RawData_PenRingY_DiffMin, + ts->x_gang_num, ts->y_num); + } + } + } /* if (ts->pen_support) */ + + nvt_mp_test_result_printed = 1; + NVT_LOG("--\n"); + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print start + function. + +return: + Executive outcomes. 1---call next function. + NULL---not call next function and sequence loop + stop. +*******************************************************/ +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print next + function. + +return: + Executive outcomes. NULL---no next and call sequence + stop function. +*******************************************************/ +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print stop + function. + +return: + n.a. +*******************************************************/ +static void c_stop(struct seq_file *m, void *v) +{ + return; +} + +const struct seq_operations nvt_selftest_seq_ops = { .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_show_selftest }; + +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV +static void goto_next_line(char **ptr) +{ + do { + *ptr = *ptr + 1; + } while (**ptr != '\n'); + *ptr = *ptr + 1; +} + +static void copy_this_line(char *dest, char *src) +{ + char *copy_from; + char *copy_to; + + copy_from = src; + copy_to = dest; + do { + *copy_to = *copy_from; + copy_from++; + copy_to++; + } while ((*copy_from != '\n') && (*copy_from != '\r')); + *copy_to = '\0'; +} + +int32_t parse_mp_setting_criteria_item(char **ptr, const char *item_string, + int32_t *item_value) +{ + char *tmp = NULL; + + NVT_LOG("%s ++\n", __func__); + tmp = strstr(*ptr, item_string); + if (tmp == NULL) { + NVT_ERR("%s not found\n", item_string); + return -1; + } + *ptr = tmp; + goto_next_line(ptr); + sscanf(*ptr, "%d,", item_value); + NVT_LOG("%s %d\n", item_string, *item_value); + + NVT_LOG("%s --\n", __func__); + return 0; +} + +int32_t parse_mp_setting_ain_array(char **ptr, const char *item_string, + uint8_t *ain_array, uint32_t IC_CFG_SIZE) +{ + char *tmp = NULL; + int32_t i = 0; + char *token = NULL; + char *tok_ptr = NULL; + size_t offset = 0; + char tmp_buf[512] = { 0 }; + + NVT_LOG("%s ++\n", __func__); + tmp = strstr(*ptr, item_string); + if (tmp == NULL) { + NVT_ERR("%s not found!\n", item_string); + return -1; + } + *ptr = tmp; + + NVT_LOG("%s\n", item_string); + /* walk thru this line */ + goto_next_line(ptr); + + /* copy this line to tmp_buf */ + memset(tmp_buf, 0, sizeof(tmp_buf)); + copy_this_line(tmp_buf, *ptr); + offset = strlen(tmp_buf); + tok_ptr = tmp_buf; + i = 0; + while ((token = strsep(&tok_ptr, ", \t\r\0"))) { + if (strlen(token) == 0) + continue; + if (!strcmp(token, "0xFF") || !strcmp(token, "0xff")) + ain_array[i] = 255; + else + ain_array[i] = (uint8_t)simple_strtol(token, NULL, 10); + NVT_LOG("%d, ", ain_array[i]); + + i++; + } + NVT_LOG("\n"); + /* check if number equals to IC_CFG_SIZE */ + if (i != IC_CFG_SIZE) { + NVT_ERR("load AIN config failed!, i=%d, IC_CFG_SIZE=%d\n", i, + IC_CFG_SIZE); + return -1; + } + /* go forward */ + *ptr = *ptr + offset; + + NVT_LOG("%s --\n", __func__); + return 0; +} + +int32_t parse_mp_criteria_item_array(char **ptr, const char *item_string, + int32_t *item_array, uint32_t x_num, + uint32_t y_num) +{ + char *tmp = NULL; + int32_t i = 0; + int32_t j = 0; + char *token = NULL; + char *tok_ptr = NULL; + size_t offset = 0; + char tmp_buf[512] = { 0 }; + + NVT_LOG("%s ++\n", __func__); + tmp = strstr(*ptr, item_string); + if (tmp == NULL) { + NVT_ERR("%s not found\n", item_string); + return -1; + } + *ptr = tmp; + + NVT_LOG("%s\n", item_string); + for (i = 0; i < y_num; i++) { + /* walk thru this line */ + goto_next_line(ptr); + memset(tmp_buf, 0, sizeof(tmp_buf)); + copy_this_line(tmp_buf, *ptr); + offset = strlen(tmp_buf); + tok_ptr = tmp_buf; + j = 0; + while ((token = strsep(&tok_ptr, ", \t\r\0"))) { + if (strlen(token) == 0) + continue; + item_array[i * x_num + j] = + (int32_t)simple_strtol(token, NULL, 10); + //NVT_LOG("%5d, ", item_array[i * x_num + j]); + printk("%5d, ", item_array[i * x_num + j]); + j++; + } + //NVT_LOG("\n"); + printk("\n"); + /* check if j equals to x_num */ + if (j != x_num) { + NVT_ERR("%s :j not equal x_num!, j=%d, x_num=%d\n", + item_string, j, x_num); + return -1; + } + /* go forward */ + *ptr = *ptr + offset; + } + + NVT_LOG("%s --\n", __func__); + return 0; +} + +static int32_t nvt_load_mp_setting_criteria_from_csv(const char *filename) +{ + int32_t retval = 0; + const struct firmware *fw_entry = NULL; + char *fbufp = NULL; + char *ptr = NULL; + + NVT_LOG("%s ++\n", __func__); + + if (NULL == filename) { + NVT_ERR("filename is null\n"); + retval = -1; + goto exit_free; + } + + retval = request_firmware(&fw_entry, filename, &ts->client->dev); + if (retval) { + NVT_ERR("%s load failed, retval=%d\n", filename, retval); + retval = -1; + goto exit_free; + } + + fbufp = (char *)kzalloc(fw_entry->size + 2, GFP_KERNEL); + if (!fbufp) { + NVT_ERR("kzalloc %zu bytes failed!\n", fw_entry->size); + retval = -1; + goto exit_free; + } + + memcpy(fbufp, fw_entry->data, fw_entry->size); + + /* NVT_LOG("File Size: %zu\n", fw_entry->size); + NVT_LOG("---------------------------------------------------\n"); + printk("fbufp:\n"); + for(i = 0; i < fw_entry->size; i++) { + printk("%c", fbufp[i]); + } + NVT_LOG("---------------------------------------------------\n"); */ + + fbufp[fw_entry->size] = '\0'; + fbufp[fw_entry->size + 1] = '\n'; + + ptr = fbufp; + if (parse_mp_setting_criteria_item( + &ptr, "IC_X_CFG_SIZE:", &IC_X_CFG_SIZE) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_criteria_item( + &ptr, "IC_Y_CFG_SIZE:", &IC_Y_CFG_SIZE) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_criteria_item(&ptr, "X_Channel:", &X_Channel) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_criteria_item(&ptr, "Y_Channel:", &Y_Channel) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_ain_array(&ptr, "AIN_X:", AIN_X, IC_X_CFG_SIZE) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_ain_array(&ptr, "AIN_Y:", AIN_Y, IC_Y_CFG_SIZE) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Short_Rawdata_P:", + PS_Config_Lmt_Short_Rawdata_P, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Short_Rawdata_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Short_Rawdata_N:", + PS_Config_Lmt_Short_Rawdata_N, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Short_Rawdata_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Open_Rawdata_P:", + PS_Config_Lmt_Open_Rawdata_P, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Open_Rawdata_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Open_Rawdata_N:", + PS_Config_Lmt_Open_Rawdata_N, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Open_Rawdata_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_Rawdata_P:", + PS_Config_Lmt_FW_Rawdata_P, X_Channel, + Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Rawdata_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_Rawdata_N:", + PS_Config_Lmt_FW_Rawdata_N, X_Channel, + Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Rawdata_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_FW_CC_P:", PS_Config_Lmt_FW_CC_P, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_CC_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_FW_CC_N:", PS_Config_Lmt_FW_CC_N, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_CC_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_FW_Diff_P:", PS_Config_Lmt_FW_Diff_P, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Diff_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_FW_Diff_N:", PS_Config_Lmt_FW_Diff_N, + X_Channel, Y_Channel) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Diff_N array value!\n"); + retval = -1; + goto exit_free; + } + + if (ts->pen_support) { + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipX_FW_Raw_P:", + PS_Config_Lmt_PenTipX_FW_Raw_P, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipX_FW_Raw_N:", + PS_Config_Lmt_PenTipX_FW_Raw_N, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipY_FW_Raw_P:", + PS_Config_Lmt_PenTipY_FW_Raw_P, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipY_FW_Raw_N:", + PS_Config_Lmt_PenTipY_FW_Raw_N, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingX_FW_Raw_P:", + PS_Config_Lmt_PenRingX_FW_Raw_P, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingX_FW_Raw_N:", + PS_Config_Lmt_PenRingX_FW_Raw_N, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingY_FW_Raw_P:", + PS_Config_Lmt_PenRingY_FW_Raw_P, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingY_FW_Raw_N:", + PS_Config_Lmt_PenRingY_FW_Raw_N, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipX_FW_Diff_P:", + PS_Config_Lmt_PenTipX_FW_Diff_P, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipX_FW_Diff_N:", + PS_Config_Lmt_PenTipX_FW_Diff_N, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipY_FW_Diff_P:", + PS_Config_Lmt_PenTipY_FW_Diff_P, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenTipY_FW_Diff_N:", + PS_Config_Lmt_PenTipY_FW_Diff_N, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingX_FW_Diff_P:", + PS_Config_Lmt_PenRingX_FW_Diff_P, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingX_FW_Diff_N:", + PS_Config_Lmt_PenRingX_FW_Diff_N, ts->x_num, + ts->y_gang_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingY_FW_Diff_P:", + PS_Config_Lmt_PenRingY_FW_Diff_P, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array( + &ptr, "PS_Config_Lmt_PenRingY_FW_Diff_N:", + PS_Config_Lmt_PenRingY_FW_Diff_N, ts->x_gang_num, + ts->y_num) < 0) { + retval = -1; + goto exit_free; + } + } /* if (ts->pen_support) */ + + ptr = fbufp; + if (parse_mp_setting_criteria_item(&ptr, "PS_Config_Diff_Test_Frame:", + &PS_Config_Diff_Test_Frame) < 0) { + retval = -1; + goto exit_free; + } + + NVT_LOG("Load MP setting and criteria from CSV file finished.\n"); + retval = 0; + +exit_free: + if (fw_entry) { + release_firmware(fw_entry); + fw_entry = NULL; + } + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } + + NVT_LOG("--, retval=%d\n", retval); + return retval; +} +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_selftest open function. + +return: + Executive outcomes. 0---succeed. negative---failed. +*******************************************************/ +static int32_t nvt_selftest_open(struct inode *inode, struct file *file) +{ + struct device_node *np = ts->client->dev.of_node; + unsigned char mpcriteria[32] = { 0 }; //novatek-mp-criteria-default +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + char mp_setting_criteria_csv_filename[64] = { 0 }; +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + TestResult_Short = 0; + TestResult_Open = 0; + TestResult_FW_Rawdata = 0; + TestResult_FWMutual = 0; + TestResult_FW_CC = 0; + TestResult_Noise = 0; + TestResult_FW_DiffMax = 0; + TestResult_FW_DiffMin = 0; + if (ts->pen_support) { + TestResult_Pen_FW_Raw = 0; + TestResult_PenTipX_Raw = 0; + TestResult_PenTipY_Raw = 0; + TestResult_PenRingX_Raw = 0; + TestResult_PenRingY_Raw = 0; + TestResult_Pen_Noise = 0; + TestResult_PenTipX_DiffMax = 0; + TestResult_PenTipX_DiffMin = 0; + TestResult_PenTipY_DiffMax = 0; + TestResult_PenTipY_DiffMin = 0; + TestResult_PenRingX_DiffMax = 0; + TestResult_PenRingX_DiffMin = 0; + TestResult_PenRingY_DiffMax = 0; + TestResult_PenRingY_DiffMin = 0; + } /* if (ts->pen_support) */ + + NVT_LOG("++\n"); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + //---Download MP FW--- + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_MP_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->mp_name); + } + } else { + nvt_update_firmware(ts->mp_name); + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + NVT_ERR("get fw info failed!\n"); + return -EAGAIN; + } + + nvt_mp_buffer_deinit(); + if (nvt_mp_buffer_init()) { + NVT_ERR("Allocate mp memory failed\n"); + return -ENOMEM; + } + + fw_ver = ts->fw_ver; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + /* ---Check if MP Setting Criteria CSV file exist and load--- */ + snprintf(mp_setting_criteria_csv_filename, + sizeof(mp_setting_criteria_csv_filename), + "NT36xxx_MP_Setting_Criteria_%04X.csv", ts->nvt_pid); + NVT_LOG("MP setting criteria csv filename: %s\n", + mp_setting_criteria_csv_filename); + if (nvt_load_mp_setting_criteria_from_csv( + mp_setting_criteria_csv_filename) < 0) { + NVT_ERR("SelfTest MP setting criteria CSV file not exist or load failed\n"); +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + /* Parsing criteria from dts */ + if (of_property_read_bool(np, "novatek,mp-support-dt")) { + /* + * Parsing Criteria by Novatek PID + * The string rule is "novatek-mp-criteria-" + * nvt_pid is 2 bytes (show hex). + * + * Ex. nvt_pid = 500A + * mpcriteria = "novatek-mp-criteria-500A" + */ + snprintf(mpcriteria, sizeof(mpcriteria), + "novatek-mp-criteria-%04X", ts->nvt_pid); + + if (nvt_mp_parse_dt(np, mpcriteria)) { + //---Download Normal FW--- + nvt_update_firmware(ts->fw_name); + mutex_unlock(&ts->lock); + NVT_ERR("mp parse device tree failed!\n"); + return -EINVAL; + } + } else { + NVT_LOG("Not found novatek,mp-support-dt, use default setting\n"); + //---Print Test Criteria--- + nvt_print_criteria(); + } +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + } else { + NVT_LOG("SelfTest MP setting criteria loaded from CSV file\n"); + } +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + if (nvt_switch_FreqHopEnDis(FREQ_HOP_DISABLE)) { + mutex_unlock(&ts->lock); + NVT_ERR("switch frequency hopping disable failed!\n"); + return -EAGAIN; + } + + if (nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN)) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw reset state failed!\n"); + return -EAGAIN; + } + + msleep(100); + + //---Enter Test Mode--- + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + NVT_ERR("clear fw status failed!\n"); + return -EAGAIN; + } + + nvt_change_mode(MP_MODE_CC); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw status failed!\n"); + return -EAGAIN; + } + + //---FW Rawdata Test--- + if (nvt_read_baseline(RawData_FWMutual) != 0) { + TestResult_FWMutual = 1; + } else { + TestResult_FWMutual = RawDataTest_SinglePoint_Sub( + RawData_FWMutual, RecordResult_FWMutual, X_Channel, + Y_Channel, PS_Config_Lmt_FW_Rawdata_P, + PS_Config_Lmt_FW_Rawdata_N); + } + if (nvt_read_CC(RawData_FW_CC) != 0) { + TestResult_FW_CC = 1; + } else { + TestResult_FW_CC = RawDataTest_SinglePoint_Sub( + RawData_FW_CC, RecordResult_FW_CC, X_Channel, Y_Channel, + PS_Config_Lmt_FW_CC_P, PS_Config_Lmt_FW_CC_N); + } + + if ((TestResult_FWMutual == 1) || (TestResult_FW_CC == 1)) { + TestResult_FW_Rawdata = 1; + } else { + if ((TestResult_FWMutual == -1) || (TestResult_FW_CC == -1)) + TestResult_FW_Rawdata = -1; + else + TestResult_FW_Rawdata = 0; + } + + if (ts->pen_support) { + //---Pen FW Rawdata Test--- + if (nvt_read_pen_baseline() != 0) { + TestResult_Pen_FW_Raw = 1; + } else { + TestResult_PenTipX_Raw = RawDataTest_SinglePoint_Sub( + RawData_PenTipX_Raw, RecordResult_PenTipX_Raw, + ts->x_num, ts->y_gang_num, + PS_Config_Lmt_PenTipX_FW_Raw_P, + PS_Config_Lmt_PenTipX_FW_Raw_N); + TestResult_PenTipY_Raw = RawDataTest_SinglePoint_Sub( + RawData_PenTipY_Raw, RecordResult_PenTipY_Raw, + ts->x_gang_num, ts->y_num, + PS_Config_Lmt_PenTipY_FW_Raw_P, + PS_Config_Lmt_PenTipY_FW_Raw_N); + TestResult_PenRingX_Raw = RawDataTest_SinglePoint_Sub( + RawData_PenRingX_Raw, RecordResult_PenRingX_Raw, + ts->x_num, ts->y_gang_num, + PS_Config_Lmt_PenRingX_FW_Raw_P, + PS_Config_Lmt_PenRingX_FW_Raw_N); + TestResult_PenRingY_Raw = RawDataTest_SinglePoint_Sub( + RawData_PenRingY_Raw, RecordResult_PenRingY_Raw, + ts->x_gang_num, ts->y_num, + PS_Config_Lmt_PenRingY_FW_Raw_P, + PS_Config_Lmt_PenRingY_FW_Raw_N); + + if ((TestResult_PenTipX_Raw == -1) || + (TestResult_PenTipY_Raw == -1) || + (TestResult_PenRingX_Raw == -1) || + (TestResult_PenRingY_Raw == -1)) + TestResult_Pen_FW_Raw = -1; + else + TestResult_Pen_FW_Raw = 0; + } + } /* if (ts->pen_support) */ + + //---Leave Test Mode--- + nvt_change_mode(NORMAL_MODE); + + //---Noise Test--- + if (nvt_read_fw_noise(RawData_Diff) != 0) { + TestResult_Noise = 1; // 1: ERROR + TestResult_FW_DiffMax = 1; + TestResult_FW_DiffMin = 1; + if (ts->pen_support) { + TestResult_Pen_Noise = 1; + TestResult_PenTipX_DiffMax = 1; + TestResult_PenTipX_DiffMin = 1; + TestResult_PenTipY_DiffMax = 1; + TestResult_PenTipY_DiffMin = 1; + TestResult_PenRingX_DiffMax = 1; + TestResult_PenRingX_DiffMin = 1; + TestResult_PenRingY_DiffMax = 1; + TestResult_PenRingY_DiffMin = 1; + } /* if (ts->pen_support) */ + } else { + TestResult_FW_DiffMax = RawDataTest_SinglePoint_Sub( + RawData_Diff_Max, RecordResult_FW_DiffMax, X_Channel, + Y_Channel, PS_Config_Lmt_FW_Diff_P, + PS_Config_Lmt_FW_Diff_N); + + TestResult_FW_DiffMin = RawDataTest_SinglePoint_Sub( + RawData_Diff_Min, RecordResult_FW_DiffMin, X_Channel, + Y_Channel, PS_Config_Lmt_FW_Diff_P, + PS_Config_Lmt_FW_Diff_N); + + if ((TestResult_FW_DiffMax == -1) || + (TestResult_FW_DiffMin == -1)) + TestResult_Noise = -1; + else + TestResult_Noise = 0; + + if (ts->pen_support) { + TestResult_PenTipX_DiffMax = + RawDataTest_SinglePoint_Sub( + RawData_PenTipX_DiffMax, + RecordResult_PenTipX_DiffMax, ts->x_num, + ts->y_gang_num, + PS_Config_Lmt_PenTipX_FW_Diff_P, + PS_Config_Lmt_PenTipX_FW_Diff_N); + + TestResult_PenTipX_DiffMin = + RawDataTest_SinglePoint_Sub( + RawData_PenTipX_DiffMin, + RecordResult_PenTipX_DiffMin, ts->x_num, + ts->y_gang_num, + PS_Config_Lmt_PenTipX_FW_Diff_P, + PS_Config_Lmt_PenTipX_FW_Diff_N); + + TestResult_PenTipY_DiffMax = + RawDataTest_SinglePoint_Sub( + RawData_PenTipY_DiffMax, + RecordResult_PenTipY_DiffMax, + ts->x_gang_num, ts->y_num, + PS_Config_Lmt_PenTipY_FW_Diff_P, + PS_Config_Lmt_PenTipY_FW_Diff_N); + + TestResult_PenTipY_DiffMin = + RawDataTest_SinglePoint_Sub( + RawData_PenTipY_DiffMin, + RecordResult_PenTipY_DiffMin, + ts->x_gang_num, ts->y_num, + PS_Config_Lmt_PenTipY_FW_Diff_P, + PS_Config_Lmt_PenTipY_FW_Diff_N); + + TestResult_PenRingX_DiffMax = + RawDataTest_SinglePoint_Sub( + RawData_PenRingX_DiffMax, + RecordResult_PenRingX_DiffMax, + ts->x_num, ts->y_gang_num, + PS_Config_Lmt_PenRingX_FW_Diff_P, + PS_Config_Lmt_PenRingX_FW_Diff_N); + + TestResult_PenRingX_DiffMin = + RawDataTest_SinglePoint_Sub( + RawData_PenRingX_DiffMin, + RecordResult_PenRingX_DiffMin, + ts->x_num, ts->y_gang_num, + PS_Config_Lmt_PenRingX_FW_Diff_P, + PS_Config_Lmt_PenRingX_FW_Diff_N); + + TestResult_PenRingY_DiffMax = + RawDataTest_SinglePoint_Sub( + RawData_PenRingY_DiffMax, + RecordResult_PenRingY_DiffMax, + ts->x_gang_num, ts->y_num, + PS_Config_Lmt_PenRingY_FW_Diff_P, + PS_Config_Lmt_PenRingY_FW_Diff_N); + + TestResult_PenRingY_DiffMin = + RawDataTest_SinglePoint_Sub( + RawData_PenRingY_DiffMin, + RecordResult_PenRingY_DiffMin, + ts->x_gang_num, ts->y_num, + PS_Config_Lmt_PenRingY_FW_Diff_P, + PS_Config_Lmt_PenRingY_FW_Diff_N); + + if ((TestResult_PenTipX_DiffMax == -1) || + (TestResult_PenTipX_DiffMin == -1) || + (TestResult_PenTipY_DiffMax == -1) || + (TestResult_PenTipY_DiffMin == -1) || + (TestResult_PenRingX_DiffMax == -1) || + (TestResult_PenRingX_DiffMin == -1) || + (TestResult_PenRingY_DiffMax == -1) || + (TestResult_PenRingY_DiffMin == -1)) + TestResult_Pen_Noise = -1; + else + TestResult_Pen_Noise = 0; + } /* if (ts->pen_support) */ + } + + //--Short Test--- + if (nvt_read_fw_short(RawData_Short) != 0) { + TestResult_Short = 1; // 1:ERROR + } else { + //---Self Test Check --- // 0:PASS, -1:FAIL + TestResult_Short = RawDataTest_SinglePoint_Sub( + RawData_Short, RecordResult_Short, X_Channel, Y_Channel, + PS_Config_Lmt_Short_Rawdata_P, + PS_Config_Lmt_Short_Rawdata_N); + } + + //---Open Test--- + if (nvt_read_fw_open(RawData_Open) != 0) { + TestResult_Open = 1; // 1:ERROR + } else { + //---Self Test Check --- // 0:PASS, -1:FAIL + TestResult_Open = RawDataTest_SinglePoint_Sub( + RawData_Open, RecordResult_Open, X_Channel, Y_Channel, + PS_Config_Lmt_Open_Rawdata_P, + PS_Config_Lmt_Open_Rawdata_N); + } + + //---Download Normal FW--- + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + nvt_mp_test_result_printed = 0; + + return seq_open(file, &nvt_selftest_seq_ops); +} + +static const struct file_operations nvt_selftest_fops = { + .owner = THIS_MODULE, + .open = nvt_selftest_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +#ifdef CONFIG_OF +/******************************************************* +Description: + Novatek touchscreen parse AIN setting for array type. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_ain(struct device_node *np, const char *name, + uint8_t *array, int32_t size) +{ + struct property *data; + int32_t len, ret; + int32_t tmp[50]; + int32_t i; + + data = of_find_property(np, name, &len); + len /= sizeof(u32); + if ((!data) || (!len) || (len != size)) { + NVT_ERR("error find %s. len=%d\n", name, len); + return -1; + } else { + NVT_LOG("%s. len=%d\n", name, len); + ret = of_property_read_u32_array(np, name, tmp, len); + if (ret) { + NVT_ERR("error reading %s. ret=%d\n", name, ret); + return -1; + } + + for (i = 0; i < len; i++) + array[i] = tmp[i]; + +#if NVT_DEBUG + printk("[NVT-ts] %s = ", name); + nvt_print_result_log_in_one_line(array, len); + printk("\n"); +#endif + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen parse criterion for u32 type. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_u32(struct device_node *np, const char *name, + int32_t *para) +{ + int32_t ret; + + ret = of_property_read_u32(np, name, para); + if (ret) { + NVT_ERR("error reading %s. ret=%d\n", name, ret); + return -1; + } else { +#if NVT_DEBUG + NVT_LOG("%s=%d\n", name, *para); +#endif + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen parse criterion for array type. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_array(struct device_node *np, const char *name, + int32_t *array, int32_t size) +{ + struct property *data; + int32_t len, ret; +#if NVT_DEBUG + int32_t j = 0; +#endif + + data = of_find_property(np, name, &len); + len /= sizeof(u32); + if ((!data) || (!len) || (len < size)) { + NVT_ERR("error find %s. len=%d\n", name, len); + return -1; + } else { + NVT_LOG("%s. len=%d\n", name, len); + ret = of_property_read_u32_array(np, name, array, len); + if (ret) { + NVT_ERR("error reading %s. ret=%d\n", name, ret); + return -1; + } + +#if NVT_DEBUG + NVT_LOG("%s =\n", name); + for (j = 0; j < Y_Channel; j++) { + nvt_print_data_log_in_one_line(array + j * X_Channel, + X_Channel); + printk("\n"); + } +#if TOUCH_KEY_NUM > 0 + nvt_print_data_log_in_one_line(array + Y_Channel * X_Channel, + Key_Channel); + printk("\n"); +#endif +#endif + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen parse criterion for pen array type. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_pen_array(struct device_node *np, const char *name, + int32_t *array, uint32_t x_num, uint32_t y_num) +{ + struct property *data; + int32_t len, ret; +#if NVT_DEBUG + int32_t j = 0; +#endif + uint32_t size; + + size = x_num * y_num; + data = of_find_property(np, name, &len); + len /= sizeof(u32); + if ((!data) || (!len) || (len < size)) { + NVT_ERR("error find %s. len=%d\n", name, len); + return -1; + } else { + NVT_LOG("%s. len=%d\n", name, len); + ret = of_property_read_u32_array(np, name, array, len); + if (ret) { + NVT_ERR("error reading %s. ret=%d\n", name, ret); + return -1; + } + +#if NVT_DEBUG + NVT_LOG("%s =\n", name); + for (j = 0; j < y_num; j++) { + nvt_print_data_log_in_one_line(array + j * x_num, + x_num); + printk("\n"); + } +#endif + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen parse device tree mp function. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_dt(struct device_node *root, const char *node_compatible) +{ + struct device_node *np = root; + struct device_node *child = NULL; + + NVT_LOG("Parse mp criteria for node %s\n", node_compatible); + + /* find each MP sub-nodes */ + for_each_child_of_node(root, child) { + /* find the specified node */ + if (of_device_is_compatible(child, node_compatible)) { + NVT_LOG("found child node %s\n", node_compatible); + np = child; + break; + } + } + if (child == NULL) { + NVT_ERR("Not found compatible node %s!\n", node_compatible); + return -1; + } + + /* MP Config*/ + if (nvt_mp_parse_u32(np, "IC_X_CFG_SIZE", &IC_X_CFG_SIZE)) + return -1; + + if (nvt_mp_parse_u32(np, "IC_Y_CFG_SIZE", &IC_Y_CFG_SIZE)) + return -1; + +#if TOUCH_KEY_NUM > 0 + if (nvt_mp_parse_u32(np, "IC_KEY_CFG_SIZE", &IC_KEY_CFG_SIZE)) + return -1; +#endif + + if (nvt_mp_parse_u32(np, "X_Channel", &X_Channel)) + return -1; + + if (nvt_mp_parse_u32(np, "Y_Channel", &Y_Channel)) + return -1; + + if (nvt_mp_parse_ain(np, "AIN_X", AIN_X, IC_X_CFG_SIZE)) + return -1; + + if (nvt_mp_parse_ain(np, "AIN_Y", AIN_Y, IC_Y_CFG_SIZE)) + return -1; + +#if TOUCH_KEY_NUM > 0 + if (nvt_mp_parse_ain(np, "AIN_KEY", AIN_KEY, IC_KEY_CFG_SIZE)) + return -1; +#endif + + /* MP Criteria */ + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Short_Rawdata_P", + PS_Config_Lmt_Short_Rawdata_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Short_Rawdata_N", + PS_Config_Lmt_Short_Rawdata_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Open_Rawdata_P", + PS_Config_Lmt_Open_Rawdata_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Open_Rawdata_N", + PS_Config_Lmt_Open_Rawdata_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Rawdata_P", + PS_Config_Lmt_FW_Rawdata_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Rawdata_N", + PS_Config_Lmt_FW_Rawdata_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_CC_P", + PS_Config_Lmt_FW_CC_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_CC_N", + PS_Config_Lmt_FW_CC_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Diff_P", + PS_Config_Lmt_FW_Diff_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Diff_N", + PS_Config_Lmt_FW_Diff_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (ts->pen_support) { + if (nvt_mp_parse_pen_array(np, "PS_Config_Lmt_PenTipX_FW_Raw_P", + PS_Config_Lmt_PenTipX_FW_Raw_P, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, "PS_Config_Lmt_PenTipX_FW_Raw_N", + PS_Config_Lmt_PenTipX_FW_Raw_N, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, "PS_Config_Lmt_PenTipY_FW_Raw_P", + PS_Config_Lmt_PenTipY_FW_Raw_P, + ts->x_gang_num, ts->y_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, "PS_Config_Lmt_PenTipY_FW_Raw_N", + PS_Config_Lmt_PenTipY_FW_Raw_N, + ts->x_gang_num, ts->y_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingX_FW_Raw_P", + PS_Config_Lmt_PenRingX_FW_Raw_P, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingX_FW_Raw_N", + PS_Config_Lmt_PenRingX_FW_Raw_N, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingY_FW_Raw_P", + PS_Config_Lmt_PenRingY_FW_Raw_P, + ts->x_gang_num, ts->y_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingY_FW_Raw_N", + PS_Config_Lmt_PenRingY_FW_Raw_N, + ts->x_gang_num, ts->y_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenTipX_FW_Diff_P", + PS_Config_Lmt_PenTipX_FW_Diff_P, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenTipX_FW_Diff_N", + PS_Config_Lmt_PenTipX_FW_Diff_N, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenTipY_FW_Diff_P", + PS_Config_Lmt_PenTipY_FW_Diff_P, + ts->x_gang_num, ts->y_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenTipY_FW_Diff_N", + PS_Config_Lmt_PenTipY_FW_Diff_N, + ts->x_gang_num, ts->y_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingX_FW_Diff_P", + PS_Config_Lmt_PenRingX_FW_Diff_P, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingX_FW_Diff_N", + PS_Config_Lmt_PenRingX_FW_Diff_N, + ts->x_num, ts->y_gang_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingY_FW_Diff_P", + PS_Config_Lmt_PenRingY_FW_Diff_P, + ts->x_gang_num, ts->y_num)) + return -1; + + if (nvt_mp_parse_pen_array(np, + "PS_Config_Lmt_PenRingY_FW_Diff_N", + PS_Config_Lmt_PenRingY_FW_Diff_N, + ts->x_gang_num, ts->y_num)) + return -1; + } /* if (ts->pen_support) */ + + if (nvt_mp_parse_u32(np, "PS_Config_Diff_Test_Frame", + &PS_Config_Diff_Test_Frame)) + return -1; + + NVT_LOG("Parse mp criteria done!\n"); + + return 0; +} +#endif /* #ifdef CONFIG_OF */ + +static int nvt_short_test(void) +{ + struct device_node *np = ts->client->dev.of_node; + unsigned char mpcriteria[32] = { 0 }; /*novatek-mp-criteria-default*/ +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + char mp_setting_criteria_csv_filename[64] = { 0 }; +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + TestResult_Short = 0; + + NVT_LOG("++\n"); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + /*---Download MP FW---*/ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_MP_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->mp_name); + } + } else { + nvt_update_firmware(ts->mp_name); + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + NVT_ERR("get fw info failed!\n"); + return -EAGAIN; + } + fw_ver = ts->fw_ver; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + /*---Check if MP Setting Criteria CSV file exist and load---*/ + snprintf(mp_setting_criteria_csv_filename, + sizeof(mp_setting_criteria_csv_filename), + "NT36xxx_MP_Setting_Criteria_%04X.csv", ts->nvt_pid); + NVT_LOG("MP setting criteria csv filename: %s\n", + mp_setting_criteria_csv_filename); + if (nvt_load_mp_setting_criteria_from_csv( + mp_setting_criteria_csv_filename) < 0) { + NVT_ERR("SelfTest MP setting criteria CSV file not exist or load failed\n"); +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + /* Parsing criteria from dts */ + if (of_property_read_bool(np, "novatek,mp-support-dt")) { + /* + * Parsing Criteria by Novatek PID + * The string rule is "novatek-mp-criteria-" + * nvt_pid is 2 bytes (show hex). + * + * Ex. nvt_pid = 500A + * mpcriteria = "novatek-mp-criteria-500A" + */ + snprintf(mpcriteria, sizeof(mpcriteria), + "novatek-mp-criteria-%04X", ts->nvt_pid); + + if (nvt_mp_parse_dt(np, mpcriteria)) { + /*---Download Normal FW---*/ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware( + DEFAULT_DEBUG_FW_NAME) < + 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware( + ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + mutex_unlock(&ts->lock); + NVT_ERR("mp parse device tree failed!\n"); + return -EINVAL; + } + } else { + NVT_LOG("Not found novatek,mp-support-dt, use default setting\n"); + /*---Print Test Criteria---*/ + nvt_print_criteria(); + } +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + } else { + NVT_LOG("SelfTest MP setting criteria loaded from CSV file\n"); + } +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + if (nvt_switch_FreqHopEnDis(FREQ_HOP_DISABLE)) { + mutex_unlock(&ts->lock); + NVT_ERR("switch frequency hopping disable failed!\n"); + return -EAGAIN; + } + + if (nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN)) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw reset state failed!\n"); + return -EAGAIN; + } + + msleep(100); + + /*--Short Test---*/ + if (nvt_read_fw_short(RawData_Short) != 0) { + TestResult_Short = 1; /* 1:ERROR*/ + } else { + /*---Self Test Check ---*/ /* 0:PASS, -1:FAIL*/ + TestResult_Short = RawDataTest_SinglePoint_Sub( + RawData_Short, RecordResult_Short, X_Channel, Y_Channel, + PS_Config_Lmt_Short_Rawdata_P, + PS_Config_Lmt_Short_Rawdata_N); + } + + /*---Download Normal FW---*/ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + nvt_mp_test_result_printed = 0; + return TestResult_Short; +} + +static int nvt_open_test(void) +{ + struct device_node *np = ts->client->dev.of_node; + unsigned char mpcriteria[32] = { 0 }; /*novatek-mp-criteria-default*/ +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + char mp_setting_criteria_csv_filename[64] = { 0 }; +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + TestResult_Open = 0; + + NVT_LOG("++\n"); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + /*---Download MP FW---*/ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_MP_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->mp_name); + } + } else { + nvt_update_firmware(ts->mp_name); + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + NVT_ERR("get fw info failed!\n"); + return -EAGAIN; + } + fw_ver = ts->fw_ver; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + /*---Check if MP Setting Criteria CSV file exist and load---*/ + snprintf(mp_setting_criteria_csv_filename, + sizeof(mp_setting_criteria_csv_filename), + "NT36xxx_MP_Setting_Criteria_%04X.csv", ts->nvt_pid); + NVT_LOG("MP setting criteria csv filename: %s\n", + mp_setting_criteria_csv_filename); + if (nvt_load_mp_setting_criteria_from_csv( + mp_setting_criteria_csv_filename) < 0) { + NVT_ERR("SelfTest MP setting criteria CSV file not exist or load failed\n"); +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + /* Parsing criteria from dts */ + if (of_property_read_bool(np, "novatek,mp-support-dt")) { + /* + * Parsing Criteria by Novatek PID + * The string rule is "novatek-mp-criteria-" + * nvt_pid is 2 bytes (show hex). + * + * Ex. nvt_pid = 500A + * mpcriteria = "novatek-mp-criteria-500A" + */ + snprintf(mpcriteria, sizeof(mpcriteria), + "novatek-mp-criteria-%04X", ts->nvt_pid); + + if (nvt_mp_parse_dt(np, mpcriteria)) { + /*---Download Normal FW---*/ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware( + DEFAULT_DEBUG_FW_NAME) < + 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware( + ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + mutex_unlock(&ts->lock); + NVT_ERR("mp parse device tree failed!\n"); + return -EINVAL; + } + } else { + NVT_LOG("Not found novatek,mp-support-dt, use default setting\n"); + /*---Print Test Criteria---*/ + nvt_print_criteria(); + } +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + } else { + NVT_LOG("SelfTest MP setting criteria loaded from CSV file\n"); + } +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + if (nvt_switch_FreqHopEnDis(FREQ_HOP_DISABLE)) { + mutex_unlock(&ts->lock); + NVT_ERR("switch frequency hopping disable failed!\n"); + return -EAGAIN; + } + + if (nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN)) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw reset state failed!\n"); + return -EAGAIN; + } + + msleep(100); + + /*---Open Test---*/ + if (nvt_read_fw_open(RawData_Open) != 0) { + TestResult_Open = 1; /* 1:ERROR*/ + } else { + /*---Self Test Check ---*/ /* 0:PASS, -1:FAIL*/ + TestResult_Open = RawDataTest_SinglePoint_Sub( + RawData_Open, RecordResult_Open, X_Channel, Y_Channel, + PS_Config_Lmt_Open_Rawdata_P, + PS_Config_Lmt_Open_Rawdata_N); + } + + /*---Download Normal FW---*/ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + + mutex_unlock(&ts->lock); + + NVT_LOG("--\n"); + + nvt_mp_test_result_printed = 0; + + return TestResult_Open; +} + +static ssize_t nvt_selftest_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + char tmp[5] = { 0 }; + int cnt; + + if (*pos != 0) + return 0; + cnt = snprintf(tmp, sizeof(tmp), "%d\n", ts->result_type); + if (copy_to_user(buf, tmp, strlen(tmp))) { + return -EFAULT; + } + + *pos += cnt; + return cnt; +} + +static ssize_t nvt_selftest_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + int retval = 0; + char tmp[6]; + + if (copy_from_user(tmp, buf, count)) { + retval = -EFAULT; + goto out; + } + + if (!strncmp("short", tmp, 5)) { + retval = nvt_short_test(); + } else if (!strncmp("open", tmp, 4)) { + retval = nvt_open_test(); + } else if (!strncmp("i2c", tmp, 3)) { + retval = nvt_get_fw_info(); + } else { + NVT_ERR("[%s] cmd not support", tmp); + retval = -EINVAL; + } + + switch (retval) { + case 0: + ts->result_type = NVT_RESULT_PASS; + break; + case -EINVAL: + ts->result_type = NVT_RESULT_INVALID; + break; + default: + ts->result_type = NVT_RESULT_FAIL; + break; + } + +out: + if (retval >= 0) + retval = count; + + return retval; +} + +static const struct file_operations nvt_aftersales_test_ops = { + .read = nvt_selftest_read, + .write = nvt_selftest_write, +}; + +/******************************************************* +Description: + Novatek touchscreen MP function proc. file node + initial function. + +return: + Executive outcomes. 0---succeed. -1---failed. +*******************************************************/ +int32_t nvt_mp_proc_init(void) +{ + NVT_proc_selftest_entry = + proc_create("nvt_selftest", 0444, NULL, &nvt_selftest_fops); + if (NVT_proc_selftest_entry == NULL) { + NVT_ERR("create /proc/nvt_selftest Failed!\n"); + return -1; + } else { + if (nvt_mp_buffer_init()) { + NVT_ERR("Allocate mp memory failed\n"); + return -1; + } else { + NVT_LOG("create /proc/nvt_selftest Succeeded!\n"); + } + } + + NVT_proc_aftersales_test_entry = proc_create("tp_selftest", 0644, NULL, + &nvt_aftersales_test_ops); + if (NVT_proc_aftersales_test_entry == NULL) { + NVT_ERR("create /proc/tp_selftest Failed!\n"); + return -1; + } else { + NVT_LOG("create /proc/tp_selftest Succeeded!\n"); + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen MP function proc. file node + deinitial function. + +return: + n.a. +*******************************************************/ +void nvt_mp_proc_deinit(void) +{ + nvt_mp_buffer_deinit(); + if (NVT_proc_selftest_entry != NULL) { + remove_proc_entry("nvt_selftest", NULL); + NVT_proc_selftest_entry = NULL; + NVT_LOG("Removed /proc/%s\n", "nvt_selftest"); + } +} + +#ifndef NVT_SAVE_TESTDATA_IN_FILE +static void test_buff_free(struct test_buf *buf) +{ + if (buf) { + if (buf->shorttest.buf) + kfree(buf->shorttest.buf); + if (buf->opentest.buf) + kfree(buf->opentest.buf); + if (buf->fwmutualtest.buf) + kfree(buf->fwmutualtest.buf); + if (buf->fwcctest.buf) + kfree(buf->fwcctest.buf); + if (buf->noisetest_max.buf) + kfree(buf->noisetest_max.buf); + if (buf->noisetest_min.buf) + kfree(buf->noisetest_min.buf); + if (buf->pen_tipx_raw.buf) + kfree(buf->pen_tipx_raw.buf); + if (buf->pen_tipy_raw.buf) + kfree(buf->pen_tipy_raw.buf); + if (buf->pen_ringx_raw.buf) + kfree(buf->pen_ringx_raw.buf); + if (buf->pen_ringy_raw.buf) + kfree(buf->pen_ringy_raw.buf); + if (buf->pen_tipx_diffmax.buf) + kfree(buf->pen_tipx_diffmax.buf); + if (buf->pen_tipx_diffmin.buf) + kfree(buf->pen_tipx_diffmin.buf); + if (buf->pen_tipy_diffmax.buf) + kfree(buf->pen_tipy_diffmax.buf); + if (buf->pen_tipy_diffmin.buf) + kfree(buf->pen_tipy_diffmin.buf); + if (buf->pen_ringx_diffmax.buf) + kfree(buf->pen_ringx_diffmax.buf); + if (buf->pen_ringx_diffmin.buf) + kfree(buf->pen_ringx_diffmin.buf); + if (buf->pen_ringy_diffmax.buf) + kfree(buf->pen_ringy_diffmax.buf); + if (buf->pen_ringy_diffmin.buf) + kfree(buf->pen_ringy_diffmin.buf); + + kfree(buf); + } + return; +} + +static int32_t test_buff_init(struct test_buf **tbuf) +{ + struct test_buf *buf; + int32_t ret; + + buf = (struct test_buf *)kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf); + goto alloc_fail; + } + + buf->shorttest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->shorttest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->shorttest.buf); + goto alloc_fail; + } + + buf->opentest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->opentest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->opentest.buf); + goto alloc_fail; + } + + buf->fwmutualtest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->fwmutualtest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->fwmutualtest.buf); + goto alloc_fail; + } + + buf->fwcctest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->fwcctest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->fwcctest.buf); + goto alloc_fail; + } + + buf->noisetest_max.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->noisetest_max.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->noisetest_max.buf); + goto alloc_fail; + } + + buf->noisetest_min.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->noisetest_min.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->noisetest_min.buf); + goto alloc_fail; + } + + buf->pen_tipx_raw.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_tipx_raw.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_tipx_raw.buf); + goto alloc_fail; + } + + buf->pen_tipy_raw.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_tipy_raw.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_tipy_raw.buf); + goto alloc_fail; + } + + buf->pen_ringx_raw.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_ringx_raw.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_ringx_raw.buf); + goto alloc_fail; + } + + buf->pen_ringy_raw.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_ringy_raw.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_ringy_raw.buf); + goto alloc_fail; + } + + buf->pen_tipx_diffmax.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_tipx_diffmax.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_tipx_diffmax.buf); + goto alloc_fail; + } + + buf->pen_tipx_diffmin.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_tipx_diffmin.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_tipx_diffmin.buf); + goto alloc_fail; + } + + buf->pen_tipy_diffmax.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_tipy_diffmax.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_tipy_diffmax.buf); + goto alloc_fail; + } + + buf->pen_tipy_diffmin.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_tipy_diffmin.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_tipy_diffmin.buf); + goto alloc_fail; + } + + buf->pen_ringx_diffmax.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_ringx_diffmax.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_ringx_diffmax.buf); + goto alloc_fail; + } + + buf->pen_ringx_diffmin.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_ringx_diffmin.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_ringx_diffmin.buf); + goto alloc_fail; + } + + buf->pen_ringy_diffmax.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_ringy_diffmax.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_ringy_diffmax.buf); + goto alloc_fail; + } + + buf->pen_ringy_diffmin.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->pen_ringy_diffmin.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->pen_ringy_diffmin.buf); + goto alloc_fail; + } + + buf->shorttest.type = SHORT_TEST; + buf->opentest.type = OPEN_TEST; + buf->fwmutualtest.type = FWMUTUAL_TEST; + buf->fwcctest.type = FWCC_TEST; + buf->noisetest_max.type = NOISE_MAX_TEST; + buf->noisetest_min.type = NOISE_MIN_TEST; + buf->pen_tipx_raw.type = PEN_TIPX_RAW; + buf->pen_tipy_raw.type = PEN_TIPY_RAW; + buf->pen_ringx_raw.type = PEN_RINGX_RAW; + buf->pen_ringy_raw.type = PEN_RINGY_RAW; + buf->pen_tipx_diffmax.type = PEN_TIPX_DIFFMAX; + buf->pen_tipx_diffmin.type = PEN_TIPX_DIFFMIN; + buf->pen_tipy_diffmax.type = PEN_TIPY_DIFFMAX; + buf->pen_tipy_diffmin.type = PEN_TIPY_DIFFMIN; + buf->pen_ringx_diffmax.type = PEN_RINGX_DIFFMAX; + buf->pen_ringx_diffmin.type = PEN_RINGX_DIFFMIN; + buf->pen_ringy_diffmax.type = PEN_RINGY_DIFFMAX; + buf->pen_ringy_diffmin.type = PEN_RINGY_DIFFMIN; + + *tbuf = buf; + return ret; + +alloc_fail: + *tbuf = NULL; + test_buff_free(buf); + return ret; +} + +struct item_buf *item_arr[MAX_TEST_TYPE]; + +static void *t_start(struct seq_file *m, loff_t *pos) +{ + struct test_buf *tbuf = ts->testdata; + + item_arr[SHORT_TEST] = &tbuf->shorttest; + item_arr[OPEN_TEST] = &tbuf->opentest; + item_arr[FWMUTUAL_TEST] = &tbuf->fwmutualtest; + item_arr[FWCC_TEST] = &tbuf->fwcctest; + item_arr[NOISE_MAX_TEST] = &tbuf->noisetest_max; + item_arr[NOISE_MIN_TEST] = &tbuf->noisetest_min; + item_arr[PEN_TIPX_RAW] = &tbuf->pen_tipx_raw; + item_arr[PEN_TIPY_RAW] = &tbuf->pen_tipy_raw; + item_arr[PEN_RINGX_RAW] = &tbuf->pen_ringx_raw; + item_arr[PEN_RINGY_RAW] = &tbuf->pen_ringy_raw; + item_arr[PEN_TIPX_DIFFMAX] = &tbuf->pen_tipx_diffmax; + item_arr[PEN_TIPX_DIFFMIN] = &tbuf->pen_tipx_diffmin; + item_arr[PEN_TIPY_DIFFMAX] = &tbuf->pen_tipy_diffmax; + item_arr[PEN_TIPY_DIFFMIN] = &tbuf->pen_tipy_diffmin; + item_arr[PEN_RINGX_DIFFMAX] = &tbuf->pen_ringx_diffmax; + item_arr[PEN_RINGX_DIFFMIN] = &tbuf->pen_ringx_diffmin; + item_arr[PEN_RINGY_DIFFMAX] = &tbuf->pen_ringy_diffmax; + item_arr[PEN_RINGY_DIFFMIN] = &tbuf->pen_ringy_diffmin; + + if (*pos >= MAX_TEST_TYPE) { + /* *pos = 0; */ + return NULL; + } + + NVT_LOG("In start\n"); + NVT_LOG("=short= item ptr (%p), type (%d), buf ptr(%p)\n", + &tbuf->shorttest, tbuf->shorttest.type, tbuf->shorttest.buf); + NVT_LOG("=open= item ptr (%p), type (%d), buf ptr(%p)\n", + &tbuf->opentest, tbuf->opentest.type, tbuf->opentest.buf); + NVT_LOG("pos (%lld), first item ptr(%p)", *pos, item_arr[*pos]); + return item_arr[*pos]; +} + +static void *t_next(struct seq_file *m, void *v, loff_t *pos) +{ + NVT_LOG("In next\n"); + NVT_LOG("ptr v (%p), pos (%lld), item ptr (%p)\n", v, *pos, + &item_arr[*pos]); + + ++*pos; + if (*pos >= MAX_TEST_TYPE) { + /* *pos = 0; */ + return NULL; + } + + NVT_LOG("ptr v (%p), pos (%lld), item ptr (%p)\n", v, *pos, + &item_arr[*pos]); + return item_arr[*pos]; +} + +static int32_t t_show(struct seq_file *m, void *v) +{ + int i, j; + struct item_buf *item = v; + int32_t *data = (int32_t *)item->buf; + + NVT_LOG("In show\n"); + NVT_LOG("item ptr (%p), type (%d), buf ptr(%p)\n", item, item->type, + item->buf); + + switch (item->type) { + case SHORT_TEST: + seq_printf(m, "========SHORT_TEST========\n"); + break; + case OPEN_TEST: + seq_printf(m, "========OPEN_TEST========\n"); + break; + case FWMUTUAL_TEST: + seq_printf(m, "========FWMUTUAL_TEST========\n"); + break; + case FWCC_TEST: + seq_printf(m, "========FWCC_TEST========\n"); + break; + case NOISE_MAX_TEST: + seq_printf(m, "========NOISE_MAX_TEST========\n"); + break; + case NOISE_MIN_TEST: + seq_printf(m, "========NOISE_MIN_TEST========\n"); + break; + case PEN_TIPX_RAW: + seq_printf(m, "========PEN_TIPX_RAW========\n"); + break; + case PEN_TIPY_RAW: + seq_printf(m, "========PEN_TIPY_RAW========\n"); + break; + case PEN_RINGX_RAW: + seq_printf(m, "========PEN_RINGX_RAW========\n"); + break; + case PEN_RINGY_RAW: + seq_printf(m, "========PEN_RINGY_RAW========\n"); + break; + case PEN_TIPX_DIFFMAX: + seq_printf(m, "========PEN_TIPX_DIFFMAX========\n"); + break; + case PEN_TIPX_DIFFMIN: + seq_printf(m, "========PEN_TIPX_DIFFMIN========\n"); + break; + case PEN_TIPY_DIFFMAX: + seq_printf(m, "========PEN_TIPY_DIFFMAX========\n"); + break; + case PEN_TIPY_DIFFMIN: + seq_printf(m, "========PEN_TIPY_DIFFMIN========\n"); + break; + case PEN_RINGX_DIFFMAX: + seq_printf(m, "========PEN_RINGX_DIFFMAX========\n"); + break; + case PEN_RINGX_DIFFMIN: + seq_printf(m, "========PEN_RINGX_DIFFMIN========\n"); + break; + case PEN_RINGY_DIFFMAX: + seq_printf(m, "========PEN_RINGY_DIFFMAX========\n"); + break; + case PEN_RINGY_DIFFMIN: + seq_printf(m, "========PEN_RINGY_DIFFMIN========\n"); + break; + default: + NVT_LOG("test type illegal (%d)\n", item->type); + return -EINVAL; + } + + for (i = 0; i < Y_Channel; i++) { + for (j = 0; j < X_Channel; j++) { + seq_printf(m, "%5d, ", data[i * X_Channel + j]); + } + seq_puts(m, "\n"); + } + seq_puts(m, "\n\n"); + + return 0; +} + +static void t_stop(struct seq_file *m, void *v) +{ + NVT_LOG("In stop\n"); + return; +} + +const struct seq_operations t_fops = { .start = t_start, + .next = t_next, + .stop = t_stop, + .show = t_show }; + +static int32_t nvt_test_data_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &t_fops); +} + +static const struct file_operations nvt_test_data_fops = { + .owner = THIS_MODULE, + .open = nvt_test_data_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +int32_t nvt_test_data_proc_init(struct spi_device *client) +{ + int ret; + struct test_buf *tbuf; + struct nvt_ts_data *ts = spi_get_drvdata(client); + + NVT_proc_test_data_entry = + proc_create("nvt_test_data", 0, NULL, &nvt_test_data_fops); + if (NVT_proc_test_data_entry == NULL) { + NVT_ERR("create proc/nvt_test_data Failed!"); + return -ENOMEM; + } else { + NVT_LOG("create proc/nvt_test_data Succeeded!"); + } + + ret = test_buff_init(&tbuf); + if (!tbuf) { + NVT_ERR("test buff init failed"); + remove_proc_entry("nvt_test_data", NULL); + return ret; + } + + ts->testdata = tbuf; + + return 0; +} + +void nvt_test_data_proc_deinit(void) +{ + test_buff_free(ts->testdata); + ts->testdata = NULL; + + if (NVT_proc_test_data_entry != NULL) { + remove_proc_entry("nvt_test_data", NULL); + NVT_proc_test_data_entry = NULL; + NVT_LOG("Removed /proc/nvt_test_data"); + } +} +#endif /*ifndef NVT_SAVE_TESTDATA_IN_FILE*/ +#endif /* #if NVT_TOUCH_MP */ diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.h b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.h new file mode 100644 index 000000000000..4745e7f0ac53 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx_mp_ctrlram.h @@ -0,0 +1,1678 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * $Revision: 71886 $ + * $Date: 2020-11-10 15:36:01 +0800 (週二, 10 å一月 2020) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#if NVT_TOUCH_MP + +static uint32_t IC_X_CFG_SIZE = 32; +static uint32_t IC_Y_CFG_SIZE = 50; +static uint32_t IC_KEY_CFG_SIZE = 4; +static uint32_t X_Channel = 32; +static uint32_t Y_Channel = 50; +static uint32_t Key_Channel = TOUCH_KEY_NUM; +static uint8_t AIN_X[50] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }; +static uint8_t AIN_Y[50] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 }; +#if TOUCH_KEY_NUM > 0 +static uint8_t AIN_KEY[8] = { 0, 1, 2, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; +#endif /* #if TOUCH_KEY_NUM > 0 */ + +static int32_t PS_Config_Lmt_Short_Rawdata_P[50 * 50] = { + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 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5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, + 5120, 5120, 5120, 5120, +#if TOUCH_KEY_NUM > 0 + 5120, 5120, 5120, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_Open_Rawdata_N[50 * 50] = { + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, -511, 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-511, + -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, -511, + -511, -511, -511, -511, +#if TOUCH_KEY_NUM > 0 + -511, -511, -511, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_FW_Rawdata_P[50 * 50] = { + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 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3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, 3840, + 3840, 3840, 3840, 3840, +#if TOUCH_KEY_NUM > 0 + 3840, 3840, 3840, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_FW_Rawdata_N[50 * 50] = { + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 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240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, +#if TOUCH_KEY_NUM > 0 + 240, 240, 240, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_FW_CC_P[50 * 50] = { + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 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314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, +#if TOUCH_KEY_NUM > 0 + 314, 314, 314, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_FW_CC_N[50 * 50] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +#if TOUCH_KEY_NUM > 0 + 0, 0, 0, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_FW_Diff_P[50 * 50] = { + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 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75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, +#if TOUCH_KEY_NUM > 0 + 75, 75, 75, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_FW_Diff_N[50 * 50] = { + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, 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-75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, 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-75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, +#if TOUCH_KEY_NUM > 0 + -75, -75, -75, +#endif /* #if TOUCH_KEY_NUM > 0 */ +}; + +static int32_t PS_Config_Lmt_PenTipX_FW_Raw_P[200] = { + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, +}; + +static int32_t PS_Config_Lmt_PenTipX_FW_Raw_N[200] = { + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, +}; + +static int32_t PS_Config_Lmt_PenTipY_FW_Raw_P[200] = { + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, +}; + +static int32_t PS_Config_Lmt_PenTipY_FW_Raw_N[200] = { + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, +}; + +static int32_t PS_Config_Lmt_PenRingX_FW_Raw_P[200] = { + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, +}; + +static int32_t PS_Config_Lmt_PenRingX_FW_Raw_N[200] = { + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, +}; + +static int32_t PS_Config_Lmt_PenRingY_FW_Raw_P[200] = { + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, 570, + 570, 570, 570, 570, +}; + +static int32_t PS_Config_Lmt_PenRingY_FW_Raw_N[200] = { + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, -570, + -570, -570, -570, -570, -570, -570, -570, -570, +}; + +static int32_t PS_Config_Lmt_PenTipX_FW_Diff_P[200] = { + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, +}; + +static int32_t PS_Config_Lmt_PenTipX_FW_Diff_N[200] = { + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, +}; + +static int32_t PS_Config_Lmt_PenTipY_FW_Diff_P[200] = { + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, +}; + +static int32_t PS_Config_Lmt_PenTipY_FW_Diff_N[200] = { + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, +}; + +static int32_t PS_Config_Lmt_PenRingX_FW_Diff_P[200] = { + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, +}; + +static int32_t PS_Config_Lmt_PenRingX_FW_Diff_N[200] = { + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, +}; + +static int32_t PS_Config_Lmt_PenRingY_FW_Diff_P[200] = { + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, 870, + 870, 870, 870, 870, +}; + +static int32_t PS_Config_Lmt_PenRingY_FW_Diff_N[200] = { + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, -870, + -870, -870, -870, -870, -870, -870, -870, -870, +}; + +static int32_t PS_Config_Diff_Test_Frame = 50; + +#ifndef NVT_SAVE_TESTDATA_IN_FILE +#define TEST_BUF_LEN 5000 + +enum test_type { + SHORT_TEST = 0, + OPEN_TEST, + FWMUTUAL_TEST, + FWCC_TEST, + NOISE_MAX_TEST, + NOISE_MIN_TEST, + PEN_TIPX_RAW, + PEN_TIPY_RAW, + PEN_RINGX_RAW, + PEN_RINGY_RAW, + PEN_TIPX_DIFFMAX, + PEN_TIPX_DIFFMIN, + PEN_TIPY_DIFFMAX, + PEN_TIPY_DIFFMIN, + PEN_RINGX_DIFFMAX, + PEN_RINGX_DIFFMIN, + PEN_RINGY_DIFFMAX, + PEN_RINGY_DIFFMIN, + MAX_TEST_TYPE = 18, +}; + +struct item_buf { + uint8_t *buf; + uint32_t len; + enum test_type type; +}; + +struct test_buf { + // spinlock_t tbuf_lock; + // bool update; + struct item_buf shorttest; + struct item_buf opentest; + struct item_buf fwmutualtest; + struct item_buf fwcctest; + struct item_buf noisetest_max; + struct item_buf noisetest_min; + struct item_buf pen_tipx_raw; + struct item_buf pen_tipy_raw; + struct item_buf pen_ringx_raw; + struct item_buf pen_ringy_raw; + struct item_buf pen_tipx_diffmax; + struct item_buf pen_tipx_diffmin; + struct item_buf pen_tipy_diffmax; + struct item_buf pen_tipy_diffmin; + struct item_buf pen_ringx_diffmax; + struct item_buf pen_ringx_diffmin; + struct item_buf pen_ringy_diffmax; + struct item_buf pen_ringy_diffmin; +}; + +int32_t nvt_test_data_proc_init(struct spi_device *client); +void nvt_test_data_proc_deinit(void); + +#endif /*#ifndef NVT_SAVE_TESTDATA_IN_FILE*/ +#endif /* #if NVT_TOUCH_MP */ diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/Kconfig b/drivers/input/touchscreen/xiaomi/nt36672c/Kconfig new file mode 100755 index 000000000000..28271c8535ed --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/Kconfig @@ -0,0 +1,15 @@ +# +# Novatek NT36xxx touchscreen driver configuration +# +config TOUCHSCREEN_NT36xxx_HOSTDL_SPI + bool "Novatek NT36xxx host download SPI driver" + help + Say Y here if you have a Novatek NT36xxx no flash touchscreen connected + to your system by SPI bus. + + If unsure, say N. + +config TOUCHSCREEN_NVT_DEBUG_FS + bool "Touch debug interface" + help + Control IRQ,suspend,sensor,debug firmware,etc. diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/Makefile b/drivers/input/touchscreen/xiaomi/nt36672c/Makefile new file mode 100755 index 000000000000..93505a4512d9 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the Novatek NT36xxx touchscreen driver. +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI) += nt36xxx.o nt36xxx_fw_update.o nt36xxx_ext_proc.o nt36xxx_mp_ctrlram_data.o nt36xxx_mp_ctrlram.o diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c new file mode 100644 index 000000000000..cb4c52513ded --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c @@ -0,0 +1,3347 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * + * $Revision: 32206 $ + * $Date: 2018-08-10 19:23:04 +0800 (週五, 10 八月 2018) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../spi-xiaomi-tp.h" +#include + +#include +#ifdef CONFIG_DRM +#include +#endif + +#include +#if defined(CONFIG_HAS_EARLYSUSPEND) +#include +#endif + +#include "nt36xxx.h" +#ifndef NVT_SAVE_TESTDATA_IN_FILE +#include "nt36xxx_mp_ctrlram.h" +#endif +#if NVT_TOUCH_ESD_PROTECT +#include +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +#include "../xiaomi/xiaomi_touch.h" +#endif + +#if NVT_TOUCH_ESD_PROTECT +static struct delayed_work nvt_esd_check_work; +static struct workqueue_struct *nvt_esd_check_wq; +static unsigned long irq_timer = 0; +uint8_t esd_check = false; +uint8_t esd_retry = 0; +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#if NVT_TOUCH_EXT_PROC +extern int32_t nvt_extra_proc_init(void); +extern void nvt_extra_proc_deinit(void); +#endif + +#if NVT_TOUCH_MP +extern int32_t nvt_mp_proc_init(void); +extern void nvt_mp_proc_deinit(void); +#endif + +struct nvt_ts_data *ts; + +#if BOOT_UPDATE_FIRMWARE +static struct workqueue_struct *nvt_fwu_wq; +static struct workqueue_struct *nvt_lockdown_wq; +extern void Boot_Update_Firmware(struct work_struct *work); +#endif + +#ifdef CONFIG_DRM +static int nvt_drm_notifier_callback(struct notifier_block *self, + unsigned long event, void *data); +#else +static int nvt_fb_notifier_callback(struct notifier_block *self, + unsigned long event, void *data); +#endif +#if defined(CONFIG_HAS_EARLYSUSPEND) +static void nvt_ts_early_suspend(struct early_suspend *h); +static void nvt_ts_late_resume(struct early_suspend *h); +#endif +static int32_t nvt_ts_suspend(struct device *dev); +static int32_t nvt_ts_resume(struct device *dev); +extern int dsi_panel_lockdown_info_read(unsigned char *plockdowninfo); +extern void dsi_panel_doubleclick_enable(bool on); +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE +static int32_t nvt_check_palm(uint8_t input_id, uint8_t *data); +#endif +extern void touch_irq_boost(void); +extern void lpm_disable_for_input(bool on); +uint32_t ENG_RST_ADDR = 0x7FFF80; +uint32_t SWRST_N8_ADDR = 0; /* read from dtsi */ +uint32_t SPI_RD_FAST_ADDR = 0; /* read from dtsi */ + +#ifdef CONFIG_MTK_SPI +const struct mt_chip_conf spi_ctrdata = { + .setuptime = 25, + .holdtime = 25, + .high_time = 5, /* 10MHz (SPI_SPEED=100M / (high_time+low_time(10ns)))*/ + .low_time = 5, + .cs_idletime = 2, + .ulthgh_thrsh = 0, + .cpol = 0, + .cpha = 0, + .rx_mlsb = 1, + .tx_mlsb = 1, + .tx_endian = 0, + .rx_endian = 0, + .com_mod = DMA_TRANSFER, + .pause = 0, + .finish_intr = 1, + .deassert = 0, + .ulthigh = 0, + .tckdly = 0, +}; +#endif /*endif CONFIG_MTK_SPI*/ + +#ifdef CONFIG_SPI_MT65XX +const struct mtk_chip_config spi_ctrdata = { + .rx_mlsb = 1, + .tx_mlsb = 1, + .cs_pol = 0, +}; +#endif /*endif CONFIG_SPI_MT65XX*/ + +static ssize_t nvt_cg_color_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[2]); +} + +static ssize_t nvt_cg_maker_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[6]); +} + +static ssize_t nvt_display_maker_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[1]); +} + +static DEVICE_ATTR(cg_color, (S_IRUGO), nvt_cg_color_show, NULL); +static DEVICE_ATTR(cg_maker, (S_IRUGO), nvt_cg_maker_show, NULL); +static DEVICE_ATTR(display_maker, (S_IRUGO), nvt_display_maker_show, NULL); + +struct attribute *nvt_panel_attr[] = { + &dev_attr_cg_color.attr, + &dev_attr_cg_maker.attr, + &dev_attr_display_maker.attr, + NULL, +}; + +static uint8_t bTouchIsAwake = 0; +/******************************************************* +Description: + Novatek touchscreen irq enable/disable function. + +return: + n.a. +*******************************************************/ +static void nvt_irq_enable(bool enable) +{ + struct irq_desc *desc; + + if (enable) { + if (!ts->irq_enabled) { + enable_irq(ts->client->irq); + ts->irq_enabled = true; + } + } else { + if (ts->irq_enabled) { + disable_irq(ts->client->irq); + ts->irq_enabled = false; + } + } + + desc = irq_to_desc(ts->client->irq); + NVT_LOG("enable=%d, desc->depth=%d\n", enable, desc->depth); +} + +/******************************************************* +Description: + Novatek touchscreen spi read/write core function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static inline int32_t spi_read_write(struct spi_device *client, uint8_t *buf, + size_t len, NVT_SPI_RW rw) +{ + struct spi_message m; + struct spi_transfer t = { + .len = len, + }; + + memcpy(ts->xbuf, buf, len); + + switch (rw) { + case NVTREAD: + t.tx_buf = ts->xbuf; + t.rx_buf = ts->rbuf; + t.len = (len + DUMMY_BYTES); + break; + + case NVTWRITE: + t.tx_buf = ts->xbuf; + break; + } + spi_message_init(&m); + spi_message_add_tail(&t, &m); + return spi_sync(client, &m); +} + +/******************************************************* +Description: + Novatek touchscreen spi read function. + +return: + Executive outcomes. 2---succeed. -5---I/O error +*******************************************************/ +int32_t CTP_SPI_READ(struct spi_device *client, uint8_t *buf, uint16_t len) +{ + int32_t ret = -1; + int32_t retries = 0; + + mutex_lock(&ts->xbuf_lock); + + buf[0] = SPI_READ_MASK(buf[0]); + + while (retries < 5) { + ret = spi_read_write(client, buf, len, NVTREAD); + if (ret == 0) + break; + retries++; + } + + if (unlikely(retries == 5)) { + NVT_ERR("read error, ret=%d\n", ret); + ret = -EIO; + } else { + memcpy((buf + 1), (ts->rbuf + 2), (len - 1)); + } + + mutex_unlock(&ts->xbuf_lock); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen spi write function. + +return: + Executive outcomes. 1---succeed. -5---I/O error +*******************************************************/ +int32_t CTP_SPI_WRITE(struct spi_device *client, uint8_t *buf, uint16_t len) +{ + int32_t ret = -1; + int32_t retries = 0; + mutex_lock(&ts->xbuf_lock); + buf[0] = SPI_WRITE_MASK(buf[0]); + while (retries < 5) { + ret = spi_read_write(client, buf, len, NVTWRITE); + if (ret == 0) + break; + retries++; + } + + if (unlikely(retries == 5)) { + NVT_ERR("error, ret=%d\n", ret); + ret = -EIO; + } + mutex_unlock(&ts->xbuf_lock); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen set index/page/addr address. + +return: + Executive outcomes. 0---succeed. -5---access fail. +*******************************************************/ +int32_t nvt_set_page(uint32_t addr) +{ + uint8_t buf[4] = { 0 }; + + buf[0] = 0xFF; /* set index/page/addr command */ + buf[1] = (addr >> 15) & 0xFF; + buf[2] = (addr >> 7) & 0xFF; + + return CTP_SPI_WRITE(ts->client, buf, 3); +} + +/******************************************************* +Description: + Novatek touchscreen write data to specify address. + +return: + Executive outcomes. 0---succeed. -5---access fail. +*******************************************************/ +int32_t nvt_write_addr(uint32_t addr, uint8_t data) +{ + int32_t ret = 0; + uint8_t buf[4] = { 0 }; + NVT_LOG("nvt_write_addr enter\n"); + /* ---set xdata index--- */ + buf[0] = 0xFF; /* set index/page/addr command */ + buf[1] = (addr >> 15) & 0xFF; + buf[2] = (addr >> 7) & 0xFF; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret) { + NVT_ERR("set page 0x%06X failed, ret = %d\n", addr, ret); + return ret; + } + + /* ---write data to index--- */ + buf[0] = addr & (0x7F); + buf[1] = data; + ret = CTP_SPI_WRITE(ts->client, buf, 2); + if (ret) { + NVT_ERR("write data to 0x%06X failed, ret = %d\n", addr, ret); + return ret; + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen enable hw bld crc function. + +return: + N/A. +*******************************************************/ +void nvt_bld_crc_enable(void) +{ + uint8_t buf[2] = { 0 }; + + /* ---set xdata index to BLD_CRC_EN_ADDR--- */ + nvt_set_page(ts->mmap->BLD_CRC_EN_ADDR); + + /* ---read data from index--- */ + buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + /* ---write data to index--- */ + buf[0] = ts->mmap->BLD_CRC_EN_ADDR & (0x7F); + buf[1] = buf[1] | (0x01 << 7); + CTP_SPI_WRITE(ts->client, buf, 2); +} + +/******************************************************* +Description: + Novatek touchscreen clear status & enable fw crc function. + +return: + N/A. +*******************************************************/ +void nvt_fw_crc_enable(void) +{ + uint8_t buf[2] = { 0 }; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); + + /* ---clear fw reset status--- */ + buf[0] = EVENT_MAP_RESET_COMPLETE & (0x7F); + buf[1] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 2); + + /* ---enable fw crc--- */ + buf[0] = EVENT_MAP_HOST_CMD & (0x7F); + buf[1] = 0xAE; /* enable fw crc command */ + CTP_SPI_WRITE(ts->client, buf, 2); +} + +/******************************************************* +Description: + Novatek touchscreen set boot ready function. + +return: + N/A. +*******************************************************/ +void nvt_boot_ready(void) +{ + /* ---write BOOT_RDY status cmds--- */ + nvt_write_addr(ts->mmap->BOOT_RDY_ADDR, 1); + + mdelay(5); + + if (!ts->hw_crc) { + /* ---write BOOT_RDY status cmds--- */ + nvt_write_addr(ts->mmap->BOOT_RDY_ADDR, 0); + + /* ---write POR_CD cmds--- */ + nvt_write_addr(ts->mmap->POR_CD_ADDR, 0xA0); + } +} + +/******************************************************* +Description: + Novatek touchscreen eng reset cmd + function. + +return: + n.a. +*******************************************************/ +void nvt_eng_reset(void) +{ + /* ---eng reset cmds to ENG_RST_ADDR--- */ + NVT_LOG("%s \n", __func__); + nvt_write_addr(ENG_RST_ADDR, 0x5A); + NVT_LOG("%s leave\n", __func__); + mdelay(1); /* wait tMCU_Idle2TP_REX_Hi after TP_RST */ +} + +/******************************************************* +Description: + Novatek touchscreen reset MCU + function. + +return: + n.a. +*******************************************************/ +void nvt_sw_reset(void) +{ + /* ---software reset cmds to SWRST_N8_ADDR--- */ + nvt_write_addr(SWRST_N8_ADDR, 0x55); + + msleep(10); +} + +/******************************************************* +Description: + Novatek touchscreen reset MCU then into idle mode + function. + +return: + n.a. +*******************************************************/ +void nvt_sw_reset_idle(void) +{ + /* ---MCU idle cmds to SWRST_N8_ADDR--- */ + nvt_write_addr(SWRST_N8_ADDR, 0xAA); + + msleep(15); +} + +/******************************************************* +Description: + Novatek touchscreen reset MCU (boot) function. + +return: + n.a. +*******************************************************/ +void nvt_bootloader_reset(void) +{ + /* ---reset cmds to SWRST_N8_ADDR--- */ + nvt_write_addr(SWRST_N8_ADDR, 0x69); + + mdelay(5); /* wait tBRST2FR after Bootload RST */ + + if (SPI_RD_FAST_ADDR) { + /* disable SPI_RD_FAST */ + nvt_write_addr(SPI_RD_FAST_ADDR, 0x00); + } +} + +/******************************************************* +Description: + Novatek touchscreen clear FW status function. + +return: + Executive outcomes. 0---succeed. -1---fail. +*******************************************************/ +int32_t nvt_clear_fw_status(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 20; + + for (i = 0; i < retry; i++) { + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + /* ---clear fw status--- */ + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 2); + + /* ---read fw status--- */ + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + if (buf[1] == 0x00) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); + return -1; + } else { + return 0; + } +} + +/******************************************************* +Description: + Novatek touchscreen check FW status function. + +return: + Executive outcomes. 0---succeed. -1---failed. +*******************************************************/ +int32_t nvt_check_fw_status(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 50; + + for (i = 0; i < retry; i++) { + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + /* ---read fw status--- */ + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + + if ((buf[1] & 0xF0) == 0xA0) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); + return -1; + } else { + return 0; + } +} + +/******************************************************* +Description: + Novatek touchscreen check FW reset state function. + +return: + Executive outcomes. 0---succeed. -1---failed. +*******************************************************/ +int32_t nvt_check_fw_reset_state(RST_COMPLETE_STATE check_reset_state) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + int32_t retry = 0; + int32_t retry_max = (check_reset_state == RESET_STATE_INIT) ? 10 : 50; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_RESET_COMPLETE); + + while (1) { + /* ---read reset state--- */ + buf[0] = EVENT_MAP_RESET_COMPLETE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 6); + + if ((buf[1] >= check_reset_state) && + (buf[1] <= RESET_STATE_MAX)) { + ret = 0; + break; + } + + retry++; + if (unlikely(retry > retry_max)) { + NVT_ERR("error, retry=%d, buf[1]=0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X\n", + retry, buf[1], buf[2], buf[3], buf[4], buf[5]); + ret = -1; + break; + } + + usleep_range(10000, 10000); + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen get novatek project id information + function. + +return: + Executive outcomes. 0---success. -1---fail. +*******************************************************/ +int32_t nvt_read_pid(void) +{ + uint8_t buf[3] = { 0 }; + int32_t ret = 0; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_PROJECTID); + + /* ---read project id--- */ + buf[0] = EVENT_MAP_PROJECTID; + buf[1] = 0x00; + buf[2] = 0x00; + CTP_SPI_READ(ts->client, buf, 3); + + ts->nvt_pid = (buf[2] << 8) + buf[1]; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); + + NVT_LOG("PID=%04X\n", ts->nvt_pid); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen get firmware related information + function. + +return: + Executive outcomes. 0---success. -1---fail. +*******************************************************/ +int32_t nvt_get_fw_info(void) +{ + uint8_t buf[64] = { 0 }; + uint32_t retry_count = 0; + int32_t ret = 0; + +#if 0 + /* READ CHIP ID */ + /* ---set xdata index to 0x1F600-- */ + nvt_set_page(0x1F600); + buf[0] = 0x4E; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + buf[5] = 0x00; + buf[6] = 0x00; + CTP_SPI_READ(ts->client, buf, 7); + NVT_LOG("buf[1]=0x%02X, buf[2]=0x%02X, buf[3]=0x%02X, buf[4]=0x%02X, buf[5]=0x%02X, buf[6]=0x%02X\n", + buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); + memset(buf, 0, 64); +#endif +info_retry: + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_FWINFO); + + /* ---read fw info--- */ + buf[0] = EVENT_MAP_FWINFO; + CTP_SPI_READ(ts->client, buf, 17); + ts->fw_ver = buf[1]; + ts->x_num = buf[3]; + ts->y_num = buf[4]; + ts->abs_x_max = (uint16_t)((buf[5] << 8) | buf[6]); + ts->abs_y_max = (uint16_t)((buf[7] << 8) | buf[8]); + ts->max_button_num = buf[11]; + + /* ---clear x_num, y_num if fw info is broken--- */ + if ((buf[1] + buf[2]) != 0xFF) { + NVT_ERR("FW info is broken! fw_ver=0x%02X, ~fw_ver=0x%02X\n", + buf[1], buf[2]); + ts->fw_ver = 0; + ts->x_num = 18; + ts->y_num = 32; + ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; + ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + ts->max_button_num = TOUCH_KEY_NUM; + + if (retry_count < 3) { + retry_count++; + NVT_ERR("retry_count=%d\n", retry_count); + goto info_retry; + } else { + NVT_ERR("Set default fw_ver=%d, x_num=%d, y_num=%d, " + "abs_x_max=%d, abs_y_max=%d, max_button_num=%d!\n", + ts->fw_ver, ts->x_num, ts->y_num, ts->abs_x_max, + ts->abs_y_max, ts->max_button_num); + ret = -1; + } + } else { + ret = 0; + } + + NVT_LOG("FW type is 0x%02X, fw_ver=%d\n", buf[14], ts->fw_ver); + + /* ---Get Novatek PID--- */ + nvt_read_pid(); + return ret; +} + +/******************************************************* + Create Device Node (Proc Entry) +*******************************************************/ +#if NVT_TOUCH_PROC +static struct proc_dir_entry *NVT_proc_entry; +#define DEVICE_NAME "NVTSPI" + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI read function. + +return: + Executive outcomes. 2---succeed. -5,-14---failed. +*******************************************************/ +static ssize_t nvt_flash_read(struct file *file, char __user *buff, + size_t count, loff_t *offp) +{ + uint8_t *str = NULL; + int32_t ret = 0; + int32_t retries = 0; + int8_t spi_wr = 0; + uint8_t *buf; + + if (count > NVT_TRANSFER_LEN) { + NVT_ERR("invalid transfer len!\n"); + return -EFAULT; + } + + /* allocate buffer for spi transfer */ + str = (uint8_t *)kzalloc((count), GFP_KERNEL); + if (str == NULL) { + NVT_ERR("kzalloc for buf failed!\n"); + ret = -ENOMEM; + goto kzalloc_failed; + } + + buf = (uint8_t *)kzalloc((count), GFP_KERNEL | GFP_DMA); + if (buf == NULL) { + NVT_ERR("kzalloc for buf failed!\n"); + ret = -ENOMEM; + kfree(str); + str = NULL; + goto kzalloc_failed; + } + + if (copy_from_user(str, buff, count)) { + NVT_ERR("copy from user error\n"); + ret = -EFAULT; + goto out; + } + +#if NVT_TOUCH_ESD_PROTECT + /* + * stop esd check work to avoid case that 0x77 report righ after here to enable esd check again + * finally lead to trigger esd recovery bootloader reset + */ + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + spi_wr = str[0] >> 7; + memcpy(buf, str + 2, ((str[0] & 0x7F) << 8) | str[1]); + + if (spi_wr == NVTWRITE) { /* SPI write */ + while (retries < 20) { + ret = CTP_SPI_WRITE(ts->client, buf, + ((str[0] & 0x7F) << 8) | str[1]); + if (!ret) + break; + else + NVT_ERR("error, retries=%d, ret=%d\n", retries, + ret); + + retries++; + } + + if (unlikely(retries == 20)) { + NVT_ERR("error, ret = %d\n", ret); + ret = -EIO; + goto out; + } + } else if (spi_wr == NVTREAD) { /* SPI read */ + while (retries < 20) { + ret = CTP_SPI_READ(ts->client, buf, + ((str[0] & 0x7F) << 8) | str[1]); + if (!ret) + break; + else + NVT_ERR("error, retries=%d, ret=%d\n", retries, + ret); + + retries++; + } + + memcpy(str + 2, buf, ((str[0] & 0x7F) << 8) | str[1]); + /* copy buff to user if spi transfer */ + if (retries < 20) { + if (copy_to_user(buff, str, count)) { + ret = -EFAULT; + goto out; + } + } + + if (unlikely(retries == 20)) { + NVT_ERR("error, ret = %d\n", ret); + ret = -EIO; + goto out; + } + } else { + NVT_ERR("Call error, str[0]=%d\n", str[0]); + ret = -EFAULT; + goto out; + } + +out: + kfree(str); + kfree(buf); +kzalloc_failed: + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI open function. + +return: + Executive outcomes. 0---succeed. -12---failed. +*******************************************************/ +static int32_t nvt_flash_open(struct inode *inode, struct file *file) +{ + struct nvt_flash_data *dev; + + dev = kmalloc(sizeof(struct nvt_flash_data), GFP_KERNEL); + if (dev == NULL) { + NVT_ERR("Failed to allocate memory for nvt flash data\n"); + return -ENOMEM; + } + + rwlock_init(&dev->lock); + file->private_data = dev; + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI close function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_flash_close(struct inode *inode, struct file *file) +{ + struct nvt_flash_data *dev = file->private_data; + + if (dev) + kfree(dev); + + return 0; +} + +static const struct file_operations nvt_flash_fops = { + .owner = THIS_MODULE, + .open = nvt_flash_open, + .release = nvt_flash_close, + .read = nvt_flash_read, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI initial function. + +return: + Executive outcomes. 0---succeed. -12---failed. +*******************************************************/ +static int32_t nvt_flash_proc_init(void) +{ + NVT_proc_entry = proc_create(DEVICE_NAME, 0444, NULL, &nvt_flash_fops); + if (NVT_proc_entry == NULL) { + NVT_ERR("Failed!\n"); + return -ENOMEM; + } else { + NVT_LOG("Succeeded!\n"); + } + + NVT_LOG("============================================================\n"); + NVT_LOG("Create /proc/%s\n", DEVICE_NAME); + NVT_LOG("============================================================\n"); + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen /proc/NVTSPI deinitial function. + +return: + n.a. +*******************************************************/ +static void nvt_flash_proc_deinit(void) +{ + if (NVT_proc_entry != NULL) { + remove_proc_entry(DEVICE_NAME, NULL); + NVT_proc_entry = NULL; + NVT_LOG("Removed /proc/%s\n", DEVICE_NAME); + } +} +#endif + +#if WAKEUP_GESTURE +#define GESTURE_WORD_C 12 +#define GESTURE_WORD_W 13 +#define GESTURE_WORD_V 14 +#define GESTURE_DOUBLE_CLICK 15 +#define GESTURE_WORD_Z 16 +#define GESTURE_WORD_M 17 +#define GESTURE_WORD_O 18 +#define GESTURE_WORD_e 19 +#define GESTURE_WORD_S 20 +#define GESTURE_SLIDE_UP 21 +#define GESTURE_SLIDE_DOWN 22 +#define GESTURE_SLIDE_LEFT 23 +#define GESTURE_SLIDE_RIGHT 24 +/* customized gesture id */ +#define DATA_PROTOCOL 30 + +/* function page definition */ +#define FUNCPAGE_GESTURE 1 + +/******************************************************* +Description: + Novatek touchscreen wake up gesture key report function. + +return: + n.a. +*******************************************************/ +void nvt_ts_wakeup_gesture_report(uint8_t gesture_id, uint8_t *data) +{ + uint8_t func_type = data[2]; + uint8_t func_id = data[3]; + + /* support fw specifal data protocol */ + if ((gesture_id == DATA_PROTOCOL) && (func_type == FUNCPAGE_GESTURE)) { + gesture_id = func_id; + } else if (gesture_id > DATA_PROTOCOL) { + NVT_ERR("gesture_id %d is invalid, func_type=%d, func_id=%d\n", + gesture_id, func_type, func_id); + return; + } + + NVT_LOG("gesture_id = %d\n", gesture_id); + + switch (gesture_id) { + case GESTURE_DOUBLE_CLICK: + NVT_LOG("Gesture : Double Click.\n"); + input_report_key(ts->input_dev, KEY_WAKEUP, 1); + input_sync(ts->input_dev); + input_report_key(ts->input_dev, KEY_WAKEUP, 0); + input_sync(ts->input_dev); + break; + default: + break; + } +} +#endif + +/******************************************************* +Description: + Novatek touchscreen parse device tree function. + +return: + n.a. +*******************************************************/ +#ifdef CONFIG_OF +static int32_t nvt_parse_dt(struct device *dev) +{ + struct nvt_config_info *config_info; + struct device_node *temp, *np = dev->of_node; + int32_t ret = 0; + uint32_t temp_val; + +#if NVT_TOUCH_SUPPORT_HW_RST + ts->reset_gpio = of_get_named_gpio_flags(np, "novatek,reset-gpio", 0, + &ts->reset_flags); + NVT_LOG("novatek,reset-gpio=%d\n", ts->reset_gpio); +#endif + ts->irq_gpio = of_get_named_gpio_flags(np, "novatek,irq-gpio", 0, + &ts->irq_flags); + NVT_LOG("novatek,irq-gpio=%d\n", ts->irq_gpio); + + ret = of_property_read_u32(np, "novatek,swrst-n8-addr", &SWRST_N8_ADDR); + if (ret) { + NVT_ERR("error reading novatek,swrst-n8-addr. ret=%d\n", ret); + return ret; + } else { + NVT_LOG("SWRST_N8_ADDR=0x%06X\n", SWRST_N8_ADDR); + } + + ret = of_property_read_u32(np, "novatek,spi-rd-fast-addr", + &SPI_RD_FAST_ADDR); + if (ret) { + NVT_ERR("not support novatek,spi-rd-fast-addr\n"); + SPI_RD_FAST_ADDR = 0; + ret = 0; + } else { + NVT_LOG("SPI_RD_FAST_ADDR=0x%06X\n", SPI_RD_FAST_ADDR); + } + + ret = of_property_read_u32(np, "novatek,config-array-size", + &ts->config_array_size); + if (ret) { + NVT_ERR("Unable to get array size\n"); + return ret; + } else { + NVT_LOG("config-array-size: %u\n", ts->config_array_size); + } + + ret = of_property_read_u32(np, "spi-max-frequency", &ts->spi_max_freq); + if (ret) { + NVT_ERR("Unable to get spi freq\n"); + return ret; + } else { + NVT_LOG("spi-max-frequency: %u\n", ts->spi_max_freq); + } + + ts->config_array = devm_kzalloc( + dev, ts->config_array_size * sizeof(struct nvt_config_info), + GFP_KERNEL); + if (!ts->config_array) { + NVT_ERR("Unable to allocate memory\n"); + return -ENOMEM; + } + + config_info = ts->config_array; + for_each_child_of_node(np, temp) { + if (config_info - ts->config_array >= ts->config_array_size) { + NVT_LOG("parse %ld config down\n", + config_info - ts->config_array); + break; + } + + ret = of_property_read_u32(temp, "novatek,tp-vendor", + &temp_val); + if (ret) { + NVT_ERR("Unable to read tp vendor\n"); + } else { + config_info->tp_vendor = (u8)temp_val; + NVT_LOG("tp vendor: %u", config_info->tp_vendor); + } + + ret = of_property_read_u32(temp, "novatek,display-maker", + &temp_val); + if (ret) { + NVT_ERR("Unable to read tp hw version\n"); + } else { + config_info->display_maker = (u8)temp_val; + NVT_LOG("tp hw version: %u", + config_info->display_maker); + } + + /* + ret = of_property_read_u32(temp, "novatek,glass-vendor", &temp_val); + if (ret) { + NVT_ERR("Unable to read tp hw version\n"); + } else { + config_info->glass_vendor = (u8) temp_val; + NVT_LOG("tp hw version: %u", config_info->glass_vendor); + }*/ + + ret = of_property_read_string(temp, "novatek,fw-name", + &config_info->nvt_fw_name); + if (ret && (ret != -EINVAL)) { + NVT_ERR("Unable to read fw name\n"); + } else { + NVT_LOG("fw_name: %s", config_info->nvt_fw_name); + } + + ret = of_property_read_string(temp, "novatek,mp-name", + &config_info->nvt_mp_name); + if (ret && (ret != -EINVAL)) { + NVT_ERR("Unable to read mp name\n"); + } else { + NVT_LOG("mp_name: %s", config_info->nvt_mp_name); + } + + /* + ret = of_property_read_string(temp, "novatek,limit-name", + &config_info->nvt_limit_name); + if (ret && (ret != -EINVAL)) { + NVT_LOG("Unable to read limit name\n"); + } else { + NVT_LOG("limit_name: %s", config_info->nvt_limit_name); + }*/ + config_info++; + } + return ret; +} +#endif + +static bool nvt_cmds_panel_info(void) +{ + bool panel_id = false; + char display_node[37] = { '\0' }; + char *match = (char *)strnstr( + saved_command_line, + "msm_drm.dsi_display0=", strlen(saved_command_line)); + if (match) { + memcpy(display_node, (match + strlen("msm_drm.dsi_display0=")), + sizeof(display_node) - 1); + NVT_LOG("%s: display_node is %s\n", __func__, display_node); + if (!strncmp(display_node, "dsi_j20s_36_02_0a_video_display", + strlen("dsi_j20s_36_02_0a_video_display"))) { + panel_id = true; + } + } + return panel_id; +} + +static int nvt_get_panel_type(struct nvt_ts_data *ts_data) +{ + int i; + u8 *lockdown = ts_data->lockdown_info; + struct nvt_config_info *panel_list = ts->config_array; + + for (i = 0; i < ts->config_array_size; i++) { + if (lockdown[0] == panel_list[i].tp_vendor) { + if (lockdown[0] == 0x46) { + break; + } + if (lockdown[7] == panel_list[i].glass_vendor) { + break; + } + } + } + + ts->panel_index = i; + + if (i >= ts->config_array_size) { + NVT_ERR("mismatch panel type, use default fw"); + ts->panel_index = -EINVAL; + return ts->panel_index; + } + + NVT_LOG("match panle type, fw is [%s], mp is [%s]", + panel_list[i].nvt_fw_name, panel_list[i].nvt_mp_name); + return ts->panel_index; +} + +bool is_lockdown_empty(u8 *lockdown) +{ + bool ret = true; + int i; + for (i = 0; i < NVT_LOCKDOWN_SIZE; i++) { + if (lockdown[i] != 0) { + ret = false; + break; + } + } + + return ret; +} + +void nvt_match_fw(void) +{ + NVT_LOG("start match fw name"); + if (is_lockdown_empty(ts->lockdown_info)) + flush_delayed_work(&ts->nvt_lockdown_work); + if (nvt_get_panel_type(ts) < 0) { + if (nvt_cmds_panel_info()) { + NVT_LOG("%s: panel is first\n", __func__); + ts->fw_name = DEFAULT_BOOT_UPDATE_FIRMWARE_FIRST; + ts->mp_name = DEFAULT_MP_UPDATE_FIRMWARE_FIRST; + } else { + NVT_LOG("%s: panel is second\n", __func__); + ts->fw_name = DEFAULT_BOOT_UPDATE_FIRMWARE_SECOND; + ts->mp_name = DEFAULT_MP_UPDATE_FIRMWARE_SECOND; + } + } else { + ts->fw_name = ts->config_array[ts->panel_index].nvt_fw_name; + ts->mp_name = ts->config_array[ts->panel_index].nvt_mp_name; + } +} + +/******************************************************* +Description: + Novatek touchscreen config and request gpio + +return: + Executive outcomes. 0---succeed. not 0---failed. +*******************************************************/ +static int nvt_gpio_config(struct nvt_ts_data *ts) +{ + int32_t ret = 0; + +#if NVT_TOUCH_SUPPORT_HW_RST + /* request RST-pin (Output/High) */ + if (gpio_is_valid(ts->reset_gpio)) { + ret = gpio_request_one(ts->reset_gpio, GPIOF_OUT_INIT_LOW, + "NVT-tp-rst"); + if (ret) { + NVT_ERR("Failed to request NVT-tp-rst GPIO\n"); + goto err_request_reset_gpio; + } + } +#endif + + /* request INT-pin (Input) */ + if (gpio_is_valid(ts->irq_gpio)) { + ret = gpio_request_one(ts->irq_gpio, GPIOF_IN, "NVT-int"); + if (ret) { + NVT_ERR("Failed to request NVT-int GPIO\n"); + goto err_request_irq_gpio; + } + } + NVT_LOG("%s Exit\n", __func__); + return ret; + +err_request_irq_gpio: +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_free(ts->reset_gpio); +err_request_reset_gpio: +#endif + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen deconfig gpio + +return: + n.a. +*******************************************************/ +static void nvt_gpio_deconfig(struct nvt_ts_data *ts) +{ + if (gpio_is_valid(ts->irq_gpio)) + gpio_free(ts->irq_gpio); +#if NVT_TOUCH_SUPPORT_HW_RST + if (gpio_is_valid(ts->reset_gpio)) + gpio_free(ts->reset_gpio); +#endif +} + +void nvt_set_dbgfw_status(bool enable) +{ + ts->fw_debug = enable; +} + +bool nvt_get_dbgfw_status(void) +{ + return ts->fw_debug; +} + +#if NVT_TOUCH_ESD_PROTECT +void nvt_esd_check_enable(uint8_t enable) +{ + /* update interrupt timer */ + irq_timer = jiffies; + /* clear esd_retry counter, if protect function is enabled */ + esd_retry = enable ? 0 : esd_retry; + /* enable/disable esd check flag */ + esd_check = enable; +} + +static uint8_t nvt_fw_recovery(uint8_t *point_data) +{ + uint8_t i = 0; + uint8_t detected = true; + + /* check pattern */ + for (i = 1; i < 7; i++) { + if (point_data[i] != 0x77) { + detected = false; + break; + } + } + + return detected; +} + +static void nvt_esd_check_func(struct work_struct *work) +{ + unsigned int timer = jiffies_to_msecs(jiffies - irq_timer); + + if ((timer > NVT_TOUCH_ESD_CHECK_PERIOD) && esd_check) { + mutex_lock(&ts->lock); + NVT_LOG("do ESD recovery, timer = %d, retry = %d\n", timer, + esd_retry); + /* do esd recovery, reload fw */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + mutex_unlock(&ts->lock); + /* update interrupt timer */ + irq_timer = jiffies; + /* update esd_retry counter */ + esd_retry++; + } + + queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, + msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); +} +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#if NVT_TOUCH_WDT_RECOVERY +static uint8_t recovery_cnt = 0; +static uint8_t nvt_wdt_fw_recovery(uint8_t *point_data) +{ + uint32_t recovery_cnt_max = 10; + uint8_t recovery_enable = false; + uint8_t i = 0; + + recovery_cnt++; + + /* check pattern */ + for (i = 1; i < 7; i++) { + if ((point_data[i] != 0xFD) && (point_data[i] != 0xFE)) { + recovery_cnt = 0; + break; + } + } + + if (recovery_cnt > recovery_cnt_max) { + recovery_enable = true; + recovery_cnt = 0; + } + + return recovery_enable; +} +#endif /* #if NVT_TOUCH_WDT_RECOVERY */ + +static uint32_t nvt_dump_fw_history(void) +{ + int32_t ret = 0; + uint8_t buf[FW_HISTORY_SIZE + 1 + DUMMY_BYTES] = { 0 }; + int32_t i = 0; + char *tmp_dump = NULL; + int32_t line_cnt = 0; + + if (ts->mmap->FW_HISTORY_ADDR == 0) { + NVT_ERR("FW_HISTORY_ADDR not available!\n"); + ret = -1; + goto exit_nvt_dump_fw_history; + } + nvt_set_page(ts->mmap->FW_HISTORY_ADDR); + buf[0] = ts->mmap->FW_HISTORY_ADDR & 0xFF; + CTP_SPI_READ(ts->client, buf, FW_HISTORY_SIZE + 1); + if (ret) { + NVT_ERR("CTP_SPI_READ failed.(%d)\n", ret); + ret = -1; + goto exit_nvt_dump_fw_history; + } + + tmp_dump = (char *)kzalloc(FW_HISTORY_SIZE * 4, GFP_KERNEL); + for (i = 0; i < FW_HISTORY_SIZE; i++) { + sprintf(tmp_dump + i * 3 + line_cnt, "%02X ", buf[1 + i]); + if ((i + 1) % 16 == 0) { + sprintf(tmp_dump + i * 3 + line_cnt + 3, "%c", '\n'); + line_cnt++; + } + } + NVT_LOG("%s", tmp_dump); + +exit_nvt_dump_fw_history: + if (tmp_dump) { + kfree(tmp_dump); + tmp_dump = NULL; + } + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); + + return ret; +} + +#define POINT_DATA_LEN 65 +/******************************************************* +Description: + Novatek touchscreen work function. + +return: + n.a. +*******************************************************/ +static irqreturn_t nvt_ts_work_func(int irq, void *data) +{ + int32_t ret = -1; + uint8_t point_data[POINT_DATA_LEN + 1 + DUMMY_BYTES] = { 0 }; + uint32_t position = 0; + uint32_t input_x = 0; + uint32_t input_y = 0; + uint32_t input_w = 0; + uint32_t input_p = 0; + uint8_t input_id = 0; +#if MT_PROTOCOL_B + uint8_t press_id[TOUCH_MAX_FINGER_NUM] = { 0 }; +#endif /* MT_PROTOCOL_B */ + int32_t i = 0; + int32_t finger_cnt = 0; + +#if WAKEUP_GESTURE + if (bTouchIsAwake == 0) { + pm_wakeup_event(&ts->input_dev->dev, 5000); + } +#endif + if (ts->debug_flag == TOUCH_IRQ_BOOST) + touch_irq_boost(); + mutex_lock(&ts->lock); + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(true); + if (ts->dev_pm_suspend) { + ret = wait_for_completion_timeout( + &ts->dev_pm_suspend_completion, msecs_to_jiffies(500)); + if (!ret) { + NVT_ERR("system(spi) can't finished resuming procedure, skip it\n"); + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(false); + goto XFER_ERROR; + } + } + + ret = CTP_SPI_READ(ts->client, point_data, POINT_DATA_LEN + 1); + if (ret < 0) { + NVT_ERR("CTP_SPI_READ failed.(%d)\n", ret); + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(false); + goto XFER_ERROR; + } + /* + //--- dump SPI buf --- + for (i = 0; i < 10; i++) { + printk("%02X %02X %02X %02X %02X %02X ", + point_data[1+i*6], point_data[2+i*6], point_data[3+i*6], point_data[4+i*6], point_data[5+i*6], point_data[6+i*6]); + } + printk("\n");*/ + +#if NVT_TOUCH_WDT_RECOVERY + /* ESD protect by WDT */ + if (nvt_wdt_fw_recovery(point_data)) { + NVT_ERR("Recover for fw reset, %02X\n", point_data[1]); + if (point_data[1] == 0xFD) { + NVT_ERR("Dump FW history:\n"); + nvt_dump_fw_history(); + } + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(false); + goto XFER_ERROR; + } +#endif /* #if NVT_TOUCH_WDT_RECOVERY */ + +#if NVT_TOUCH_ESD_PROTECT + /* ESD protect by FW handshake */ + if (nvt_fw_recovery(point_data)) { + nvt_esd_check_enable(true); + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(false); + goto XFER_ERROR; + } +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + input_id = (uint8_t)(point_data[1] >> 3); + if (nvt_check_palm(input_id, point_data)) { + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(false); + goto XFER_ERROR; /* to skip point data parsing */ + } +#endif + +#if WAKEUP_GESTURE + if (bTouchIsAwake == 0) { + input_id = (uint8_t)(point_data[1] >> 3); + nvt_ts_wakeup_gesture_report(input_id, point_data); + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(false); + mutex_unlock(&ts->lock); + return IRQ_HANDLED; + } +#endif + + finger_cnt = 0; + + for (i = 0; i < ts->max_touch_num; i++) { + position = 1 + 6 * i; + input_id = (uint8_t)(point_data[position + 0] >> 3); + if ((input_id == 0) || (input_id > ts->max_touch_num)) + continue; + + if (((point_data[position] & 0x07) == 0x01) || + ((point_data[position] & 0x07) == + 0x02)) { //finger down (enter & moving) +#if NVT_TOUCH_ESD_PROTECT + /* update interrupt timer */ + irq_timer = jiffies; +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + input_x = (uint32_t)(point_data[position + 1] << 4) + + (uint32_t)(point_data[position + 3] >> 4); + input_y = (uint32_t)(point_data[position + 2] << 4) + + (uint32_t)(point_data[position + 3] & 0x0F); + if ((input_x < 0) || (input_y < 0)) + continue; + if ((input_x > ts->abs_x_max) || + (input_y > ts->abs_y_max)) + continue; + input_w = (uint32_t)(point_data[position + 4]); + if (input_w == 0) + input_w = 1; + if (i < 2) { + input_p = (uint32_t)(point_data[position + 5]) + + (uint32_t)(point_data[i + 63] << 8); + if (input_p > TOUCH_FORCE_NUM) + input_p = TOUCH_FORCE_NUM; + } else { + input_p = (uint32_t)(point_data[position + 5]); + } + if (input_p == 0) + input_p = 1; + +#if MT_PROTOCOL_B + press_id[input_id - 1] = 1; + input_mt_slot(ts->input_dev, input_id - 1); + input_mt_report_slot_state(ts->input_dev, + MT_TOOL_FINGER, true); + input_report_key(ts->input_dev, BTN_TOUCH, 1); + input_report_key(ts->input_dev, BTN_TOOL_FINGER, 1); +#else /* MT_PROTOCOL_B */ + input_report_abs(ts->input_dev, ABS_MT_TRACKING_ID, + input_id - 1); + input_report_key(ts->input_dev, BTN_TOUCH, 1); +#endif /* MT_PROTOCOL_B */ + + input_report_abs(ts->input_dev, ABS_MT_POSITION_X, + input_x); + input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, + input_y); + /*input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, input_w);*/ + /*input_report_abs(ts->input_dev, ABS_MT_PRESSURE, input_p);*/ + +#if MT_PROTOCOL_B +#else /* MT_PROTOCOL_B */ + input_mt_sync(ts->input_dev); +#endif /* MT_PROTOCOL_B */ + + set_bit(input_id - 1, ts->slot_map); + finger_cnt++; + } + } + +#if MT_PROTOCOL_B + for (i = 0; i < ts->max_touch_num; i++) { + if (press_id[i] != 1) { + input_mt_slot(ts->input_dev, i); + /*input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0);*/ + input_mt_report_slot_state(ts->input_dev, + MT_TOOL_FINGER, false); + /*input_report_abs(ts->input_dev, ABS_MT_PRESSURE, 0); */ + if (finger_cnt == 0 && test_bit(i, ts->slot_map)) { + input_report_key(ts->input_dev, BTN_TOUCH, 0); + input_report_key(ts->input_dev, BTN_TOOL_FINGER, + 0); + if (ts->debug_flag >= TOUCH_DISABLE_LPM) + lpm_disable_for_input(false); + } + clear_bit(i, ts->slot_map); + } + } + /* input_report_key(ts->input_dev, BTN_TOUCH, (finger_cnt > 0)); */ +#else /* MT_PROTOCOL_B */ + if (finger_cnt == 0) { + input_report_key(ts->input_dev, BTN_TOUCH, 0); + input_mt_sync(ts->input_dev); + } +#endif /* MT_PROTOCOL_B */ + + input_sync(ts->input_dev); + +XFER_ERROR: + mutex_unlock(&ts->lock); + return IRQ_HANDLED; +} + +/******************************************************* +Description: + Novatek touchscreen check chip version trim function. + +return: + Executive outcomes. 0---NVT IC. -1---not NVT IC. +*******************************************************/ +static int8_t nvt_ts_check_chip_ver_trim(void) +{ + uint8_t buf[8] = { 0 }; + int32_t retry = 0; + int32_t list = 0; + int32_t i = 0; + int32_t found_nvt_chip = 0; + int32_t ret = -1; + + /* ---Check for 5 times--- */ + for (retry = 5; retry > 0; retry--) { + nvt_bootloader_reset(); + + /* ---set xdata index to 0x1F600--- */ + nvt_set_page(0x1F600); + + buf[0] = 0x4E; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + buf[5] = 0x00; + buf[6] = 0x00; + CTP_SPI_READ(ts->client, buf, 7); + NVT_LOG("buf[1]=0x%02X, buf[2]=0x%02X, buf[3]=0x%02X, buf[4]=0x%02X, buf[5]=0x%02X, buf[6]=0x%02X\n", + buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); + + /* compare read chip id on supported list */ + for (list = 0; list < (sizeof(trim_id_table) / + sizeof(struct nvt_ts_trim_id_table)); + list++) { + found_nvt_chip = 0; + /* compare each byte */ + for (i = 0; i < NVT_ID_BYTE_MAX; i++) { + if (trim_id_table[list].mask[i]) { + if (buf[i + 1] != + trim_id_table[list].id[i]) + break; + } + } + + if (i == NVT_ID_BYTE_MAX) { + found_nvt_chip = 1; + } + + if (found_nvt_chip) { + NVT_LOG("This is NVT touch IC\n"); + ts->mmap = trim_id_table[list].mmap; + ts->carrier_system = + trim_id_table[list] + .hwinfo->carrier_system; + ts->hw_crc = trim_id_table[list].hwinfo->hw_crc; + ret = 0; + goto out; + } else { + ts->mmap = NULL; + ret = -1; + } + } + + msleep(10); + } + +out: + return ret; +} + +static int nvt_pinctrl_init(struct nvt_ts_data *nvt_data) +{ + int retval = 0; + /* Get pinctrl if target uses pinctrl */ + nvt_data->ts_pinctrl = devm_pinctrl_get(&nvt_data->pdev->dev); + NVT_LOG("%s Enter\n", __func__); + if (IS_ERR_OR_NULL(nvt_data->ts_pinctrl)) { + retval = PTR_ERR(nvt_data->ts_pinctrl); + NVT_ERR("Target does not use pinctrl %d\n", retval); + goto err_pinctrl_get; + } + + nvt_data->pinctrl_state_active = pinctrl_lookup_state( + nvt_data->ts_pinctrl, PINCTRL_STATE_ACTIVE); + + if (IS_ERR_OR_NULL(nvt_data->pinctrl_state_active)) { + retval = PTR_ERR(nvt_data->pinctrl_state_active); + NVT_ERR("Can not lookup %s pinstate %d\n", PINCTRL_STATE_ACTIVE, + retval); + goto err_pinctrl_lookup; + } + + nvt_data->pinctrl_state_suspend = pinctrl_lookup_state( + nvt_data->ts_pinctrl, PINCTRL_STATE_SUSPEND); + + if (IS_ERR_OR_NULL(nvt_data->pinctrl_state_suspend)) { + retval = PTR_ERR(nvt_data->pinctrl_state_suspend); + NVT_ERR("Can not lookup %s pinstate %d\n", + PINCTRL_STATE_SUSPEND, retval); + goto err_pinctrl_lookup; + } + + return 0; +err_pinctrl_lookup: + devm_pinctrl_put(nvt_data->ts_pinctrl); +err_pinctrl_get: + nvt_data->ts_pinctrl = NULL; + return retval; +} + +static void nvt_switch_mode_work(struct work_struct *work) +{ + NVT_LOG("%s double click wakeup", ts->db_wakeup ? "ENABLE" : "DISABLE"); + if (ts->ic_state <= NVT_IC_SUSPEND_OUT && ts->ic_state != NVT_IC_INIT) { + ts->gesture_command_delayed = ts->db_wakeup; + NVT_ERR("Panel off, don't set dbclick gesture flag util panel on"); + ts->db_wakeup = 0; + } else if (ts->ic_state >= NVT_IC_RESUME_IN) { + dsi_panel_doubleclick_enable(!!ts->db_wakeup); + } +} + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + +static struct xiaomi_touch_interface xiaomi_touch_interfaces; + +int32_t nvt_check_palm(uint8_t input_id, uint8_t *data) +{ + int32_t ret = 0; + uint8_t func_type = data[2]; + uint8_t palm_state = data[3]; + + if ((input_id == DATA_PROTOCOL) && (func_type == FUNCPAGE_PALM)) { + ret = palm_state; + if (palm_state == PACKET_PALM_ON) { + NVT_LOG("get packet palm on event.\n"); + update_palm_sensor_value(1); + } else if (palm_state == PACKET_PALM_OFF) { + NVT_LOG("get packet palm off event.\n"); + update_palm_sensor_value(0); + } else { + NVT_ERR("invalid palm state %d!\n", palm_state); + ret = -1; + } + } else { + ret = 0; + } + + return ret; +} + +static int nvt_palm_sensor_write(int value) +{ + int ret = 0; + NVT_LOG("enter %d %d\n", value, ts->palm_sensor_switch); + ts->palm_sensor_switch = value; + + if (ts->dev_pm_suspend) { + NVT_LOG("tp has dev_pm_suspend status\n"); + return 0; + } + + if (bTouchIsAwake) + ret = nvt_set_pocket_palm_switch(value); + return ret; +} + +static struct xiaomi_touch_interface xiaomi_touch_interfaces; +static void nvt_init_touchmode_data(void) +{ + int i; + + NVT_LOG("%s,ENTER\n", __func__); + /* Touch Game Mode Switch */ + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MAX_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_CUR_VALUE] = 0; + + /* Acitve Mode */ + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MAX_VALUE] = + 1; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_DEF_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_CUR_VALUE] = + 0; + + /* Sensivity */ + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MAX_VALUE] = + 2; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_DEF_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_CUR_VALUE] = + 0; + + /* Tolerance */ + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MAX_VALUE] = 2; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_CUR_VALUE] = 0; + + /* Panel orientation*/ + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MAX_VALUE] = 3; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = 0; + + /* Edge filter area*/ + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MAX_VALUE] = + 3; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MIN_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_DEF_VALUE] = + 2; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE] = + 0; + xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = + 0; + + /* Resist RF interference*/ + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_MAX_VALUE] = 1; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_MIN_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_DEF_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][SET_CUR_VALUE] = 0; + xiaomi_touch_interfaces.touch_mode[Touch_Resist_RF][GET_CUR_VALUE] = 0; + + for (i = 0; i < Touch_Mode_NUM; i++) { + NVT_LOG("mode:%d, set cur:%d, get cur:%d, def:%d min:%d max:%d\n", + i, xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MIN_VALUE], + xiaomi_touch_interfaces.touch_mode[i][GET_MAX_VALUE]); + } + + return; +} + +static int nvt_touchfeature_cmd_xsfer(uint8_t *touchfeature) +{ + int ret; + uint8_t buf[8] = { 0 }; + + NVT_LOG("++\n"); + NVT_LOG("cmd xsfer:%02x, %02x", touchfeature[0], touchfeature[1]); + /* ---set xdata index to EVENT BUF ADDR--- */ + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_touchfeature_cmd_xsfer_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = touchfeature[0]; + buf[2] = touchfeature[1]; + + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("Write sensitivity switch command fail!\n"); + goto nvt_touchfeature_cmd_xsfer_out; + } + +nvt_touchfeature_cmd_xsfer_out: + NVT_LOG("--\n"); + return ret; +} + +static int nvt_touchfeature_set(uint8_t *touchfeature) +{ + int ret; + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + ret = nvt_touchfeature_cmd_xsfer(touchfeature); + if (ret < 0) + NVT_ERR("send cmd via SPI failed, errno:%d", ret); + + mutex_unlock(&ts->lock); + msleep(35); + return ret; +} + +static int nvt_set_cur_value(int nvt_mode, int nvt_value) +{ + bool skip = false; + uint8_t nvt_game_value[2] = { 0 }; + uint8_t temp_value = 0; + uint8_t ret = 0; + + if (nvt_mode >= Touch_Mode_NUM && nvt_mode < 0) { + NVT_ERR("%s, nvt mode is error:%d", __func__, nvt_mode); + return -EINVAL; + } + + if (nvt_mode == Touch_Doubletap_Mode && ts && nvt_value >= 0) { + ts->db_wakeup = nvt_value; + schedule_work(&ts->switch_mode_work); + } + + xiaomi_touch_interfaces.touch_mode[nvt_mode][SET_CUR_VALUE] = nvt_value; + + if (xiaomi_touch_interfaces.touch_mode[nvt_mode][SET_CUR_VALUE] > + xiaomi_touch_interfaces.touch_mode[nvt_mode][GET_MAX_VALUE]) { + xiaomi_touch_interfaces.touch_mode[nvt_mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[nvt_mode][GET_MAX_VALUE]; + + } else if (xiaomi_touch_interfaces.touch_mode[nvt_mode][SET_CUR_VALUE] < + xiaomi_touch_interfaces.touch_mode[nvt_mode][GET_MIN_VALUE]) { + xiaomi_touch_interfaces.touch_mode[nvt_mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[nvt_mode][GET_MIN_VALUE]; + } + + switch (nvt_mode) { + case Touch_Game_Mode: + break; + case Touch_Active_MODE: + break; + case Touch_UP_THRESHOLD: + temp_value = + xiaomi_touch_interfaces + .touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE]; + nvt_game_value[0] = 0x71; + nvt_game_value[1] = temp_value; + break; + case Touch_Tolerance: + temp_value = + xiaomi_touch_interfaces + .touch_mode[Touch_Tolerance][SET_CUR_VALUE]; + nvt_game_value[0] = 0x70; + nvt_game_value[1] = temp_value; + break; + case Touch_Edge_Filter: + /* filter 0,1,2,3 = default,1,2,3 level*/ + temp_value = + xiaomi_touch_interfaces + .touch_mode[Touch_Edge_Filter][SET_CUR_VALUE]; + nvt_game_value[0] = 0x72; + nvt_game_value[1] = temp_value; + break; + case Touch_Panel_Orientation: + /* 0,1,2,3 = 0, 90, 180,270 Counter-clockwise*/ + temp_value = xiaomi_touch_interfaces + .touch_mode[Touch_Panel_Orientation] + [SET_CUR_VALUE]; + if (temp_value == 0 || temp_value == 2) { + nvt_game_value[0] = 0xBA; + } else if (temp_value == 1) { + nvt_game_value[0] = 0xBC; + } else if (temp_value == 3) { + nvt_game_value[0] = 0xBB; + } + nvt_game_value[1] = 0; + break; + case Touch_Resist_RF: + temp_value = + xiaomi_touch_interfaces + .touch_mode[Touch_Resist_RF][SET_CUR_VALUE]; + if (temp_value == 0) { + nvt_game_value[0] = 0x76; + } else if (temp_value == 1) { + nvt_game_value[0] = 0x75; + } + nvt_game_value[1] = 0; + break; + default: + /* Don't support */ + skip = true; + break; + }; + + NVT_LOG("mode:%d, value:%d,temp_value:%d,game value:0x%x,0x%x", + nvt_mode, nvt_value, temp_value, nvt_game_value[0], + nvt_game_value[1]); + + if (!skip) { + xiaomi_touch_interfaces.touch_mode[nvt_mode][GET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[nvt_mode][SET_CUR_VALUE]; + + ret = nvt_touchfeature_set(nvt_game_value); + if (ret < 0) { + NVT_ERR("change game mode fail"); + } + } else { + NVT_LOG("Cmd is not support,skip!"); + } + + return 0; +} + +static char nvt_touch_vendor_read(void) +{ + char value = '4'; + NVT_LOG("%s Get touch vendor: %c\n", __func__, value); + return value; +} + +static u8 nvt_panel_vendor_read(void) +{ + char value = '0'; + int ret = 0; + if (!ts) + return value; + ret = dsi_panel_lockdown_info_read(ts->lockdown_info); + if (ret <= 0) { + NVT_ERR("can't get lockdown info"); + return value; + } + if (!ts->lockdown_info[6]) { + NVT_ERR("%s lockdown info is NULL\n", __func__); + return value; + } else { + value = ts->lockdown_info[1]; + NVT_LOG("%s Get touch vendor: %d\n", __func__, value); + } + return value; +} + +static u8 nvt_panel_color_read(void) +{ + char value = '0'; + int ret = 0; + if (!ts) + return value; + ret = dsi_panel_lockdown_info_read(ts->lockdown_info); + if (ret <= 0) { + NVT_ERR("can't get lockdown info"); + return value; + } + if (!ts->lockdown_info[2]) { + NVT_ERR("%s lockdown info is NULL\n", __func__); + return value; + } else { + value = ts->lockdown_info[2]; + NVT_LOG("%s Get touch vendor: %d\n", __func__, value); + } + return value; +} + +static u8 nvt_panel_display_read(void) +{ + char value = '0'; + int ret = 0; + if (!ts) + return value; + ret = dsi_panel_lockdown_info_read(ts->lockdown_info); + if (ret <= 0) { + NVT_ERR("can't get lockdown info"); + return value; + } + if (!ts->lockdown_info[1]) { + NVT_ERR("%s lockdown info is NULL\n", __func__); + return value; + } else { + value = ts->lockdown_info[1]; + NVT_LOG("%s Get touch vendor: %d\n", __func__, value); + } + return value; +} + +static int nvt_get_mode_value(int mode, int value_type) +{ + int value = -1; + + if (mode < Touch_Mode_NUM && mode >= 0) + value = xiaomi_touch_interfaces.touch_mode[mode][value_type]; + else + NVT_ERR("%s, don't support\n", __func__); + + return value; +} + +static int nvt_get_mode_all(int mode, int *value) +{ + if (mode < Touch_Mode_NUM && mode >= 0) { + value[0] = + xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE]; + value[1] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + value[2] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; + value[3] = + xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; + } else { + NVT_ERR("%s, don't support\n", __func__); + } + NVT_LOG("%s, mode:%d, value:%d:%d:%d:%d\n", __func__, mode, value[0], + value[1], value[2], value[3]); + + return 0; +} + +static int nvt_reset_mode(int mode) +{ + int i = 0; + + NVT_LOG("nvt_reset_mode enter\n"); + + if (mode < Touch_Report_Rate && mode > 0) { + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = + xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; + nvt_set_cur_value( + mode, + xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE]); + } else if (mode == 0) { + for (i = 0; i <= Touch_Report_Rate; i++) { + if (i == Touch_Panel_Orientation) { + xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[i][GET_CUR_VALUE]; + } else { + xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE] = + xiaomi_touch_interfaces + .touch_mode[i][GET_DEF_VALUE]; + } + nvt_set_cur_value( + i, xiaomi_touch_interfaces + .touch_mode[i][SET_CUR_VALUE]); + } + } else { + NVT_ERR("%s, don't support\n", __func__); + } + + NVT_LOG("%s, mode:%d\n", __func__, mode); + + return 0; +} +#endif + +#ifdef CONFIG_TOUCHSCREEN_NVT_DEBUG_FS + +/*static void tpdbg_shutdown(struct nvt_ts_data *ts_core, bool enable) +{ + mutex_lock(&ts->lock); + if (enable) { + if (nvt_write_addr(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD, 0x1A) < 0) { + NVT_ERR("disable tp sensor failed!"); + } + } else { + if (nvt_write_addr(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD, 0x15) < 0) { + NVT_ERR("enable tp sensor failed!"); + } + } + mutex_unlock(&ts->lock); +}*/ + +static void tpdbg_suspend(struct nvt_ts_data *ts_core, bool enable) +{ + if (enable) + nvt_ts_suspend(&ts_core->client->dev); + else + nvt_ts_resume(&ts_core->client->dev); +} + +static int tpdbg_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + + return 0; +} + +static ssize_t tpdbg_read(struct file *file, char __user *buf, size_t size, + loff_t *ppos) +{ + const char *str = "cmd support as below:\n \ + echo \"irq-disable\" or \"irq-enable\" to ctrl irq\n \ + echo \"tp-sd-en\" or \"tp-sd-off\" to ctrl panel on or off sensor\n \ + echo \"tp-suspend-en\" or \"tp-suspend-off\" to ctrl panel in or off suspend status\n \ + echo \"fw-debug-on\" or \"fw-debug-off\" to on or off fw debug function\n"; + + loff_t pos = *ppos; + int len = strlen(str); + + if (pos < 0) + return -EINVAL; + if (pos >= len) + return 0; + + if (copy_to_user(buf, str, len)) + return -EFAULT; + + *ppos = pos + len; + + return len; +} + +static ssize_t tpdbg_write(struct file *file, const char __user *buf, + size_t size, loff_t *ppos) +{ + struct nvt_ts_data *ts_core = file->private_data; + char *cmd = kzalloc(size + 1, GFP_KERNEL); + int ret = size; + + if (!cmd) + return -ENOMEM; + + if (copy_from_user(cmd, buf, size)) { + ret = -EFAULT; + goto out; + } + +#if NVT_TOUCH_ESD_PROTECT + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + cmd[size] = '\0'; + + if (!strncmp(cmd, "irq-disable", 11)) + nvt_irq_enable(false); + else if (!strncmp(cmd, "irq-enable", 10)) + nvt_irq_enable(true); + else if (!strncmp(cmd, "tp-sd-en", 8)) + tpdbg_suspend(ts_core, true); + else if (!strncmp(cmd, "tp-sd-off", 9)) + tpdbg_suspend(ts_core, false); + else if (!strncmp(cmd, "tp-suspend-en", 13)) + tpdbg_suspend(ts_core, true); + else if (!strncmp(cmd, "tp-suspend-off", 14)) + tpdbg_suspend(ts_core, false); + else if (!strncmp(cmd, "fw-debug-on", 11)) + nvt_set_dbgfw_status(true); + else if (!strncmp(cmd, "fw-debug-off", 12)) + nvt_set_dbgfw_status(false); +out: + kfree(cmd); + + return ret; +} + +static int tpdbg_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + + return 0; +} + +static ssize_t nvt_touch_test_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + int retval = -1; + uint8_t cmd[8]; + if (copy_from_user(cmd, buf, count)) { + retval = -EFAULT; + goto out; + } + switch (cmd[0]) { + case '0': + ts->debug_flag = 0; + break; + case '1': + ts->debug_flag = 1; + break; + case '2': + ts->debug_flag = 2; + break; + default: + NVT_LOG("%s invalid input cmd, set default value\n", __func__); + ts->debug_flag = 2; + } + NVT_LOG("%s set touch boost debug flag to %d\n", __func__, + ts->debug_flag); + retval = count; +out: + return retval; +} + +static const struct file_operations nvt_touch_test_fops = { + .owner = THIS_MODULE, + .write = nvt_touch_test_write, +}; + +static const struct file_operations tpdbg_ops = { + .owner = THIS_MODULE, + .open = tpdbg_open, + .read = tpdbg_read, + .write = tpdbg_write, + .release = tpdbg_release, +}; +#endif + +/* +static void nvt_suspend_work(struct work_struct *work) +{ + struct nvt_ts_data *ts_core = container_of(work, struct nvt_ts_data, suspend_work); + nvt_ts_suspend(&ts_core->client->dev); +} +*/ + +static void nvt_resume_work(struct work_struct *work) +{ + struct nvt_ts_data *ts_core = + container_of(work, struct nvt_ts_data, resume_work); + nvt_ts_resume(&ts_core->client->dev); +} + +static void get_lockdown_info(struct work_struct *work) +{ + int ret = 0; + + NVT_LOG("lkdown_readed = %d", ts->lkdown_readed); + + if (!ts->lkdown_readed) { + ret = dsi_panel_lockdown_info_read(ts->lockdown_info); + if (ret < 0) { + NVT_ERR("can't get lockdown info"); + } else { + NVT_LOG("Lockdown:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + ts->lockdown_info[0], ts->lockdown_info[1], + ts->lockdown_info[2], ts->lockdown_info[3], + ts->lockdown_info[4], ts->lockdown_info[5], + ts->lockdown_info[6], ts->lockdown_info[7]); + } + ts->lkdown_readed = true; + NVT_LOG("READ LOCKDOWN!!!"); + } else { + NVT_LOG("use lockdown info that readed before"); + NVT_LOG("Lockdown:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + ts->lockdown_info[0], ts->lockdown_info[1], + ts->lockdown_info[2], ts->lockdown_info[3], + ts->lockdown_info[4], ts->lockdown_info[5], + ts->lockdown_info[6], ts->lockdown_info[7]); + } +} + +/******************************************************* +Description: + Novatek touchscreen driver probe function. + +return: + Executive outcomes. 0---succeed. negative---failed +*******************************************************/ +static int32_t nvt_ts_probe(struct platform_device *pdev) +{ + struct spi_device *ts_xsfer; + int32_t ret = 0; + int32_t retry = 0; + struct attribute_group *attrs_p = NULL; + + NVT_LOG("start\n"); + + ts = kzalloc(sizeof(struct nvt_ts_data), GFP_KERNEL); + if (ts == NULL) { + NVT_ERR("failed to allocated memory for nvt ts data\n"); + return -ENOMEM; + } + ts->xbuf = (uint8_t *)kzalloc((NVT_TRANSFER_LEN + 1), GFP_KERNEL); + if (ts->xbuf == NULL) { + NVT_ERR("kzalloc for xbuf failed!\n"); + if (ts) { + kfree(ts); + ts = NULL; + } + return -ENOMEM; + } + + ts->pdev = pdev; + for (retry = 1; retry <= 3; ++retry) { + ret = tmp_hold_ts_xsfer(&ts_xsfer); + if (ret < 0) { + if (ret == -EBUSY) { + NVT_ERR("tmp hold ts_xsfer failed, retry:%d\n", + retry); + mdelay(100); + continue; + } else if (ret == -EPERM) { + NVT_ERR("ts_xsfer has been used, exit nvt probe\n"); + goto err_get_spi; + } else if (ret == -EINVAL) { + NVT_ERR("ts_xsfer not exist, exit nvt probe\n"); + goto err_get_spi; + } + } else { + break; + } + } + if (ret == -EBUSY) { + NVT_ERR("ts_xsfer always busy, exit nvt probe\n"); + goto err_get_spi; + } + + /* ---parse dts--- */ + ret = nvt_parse_dt(&pdev->dev); + if (ret) { + NVT_ERR("parse dt error\n"); + goto err_spi_setup; + } + + ts->client = ts_xsfer; + spi_set_drvdata(ts->client, ts); + + /* ---prepare for spi parameter--- */ + if (ts->client->master->flags & SPI_MASTER_HALF_DUPLEX) { + NVT_ERR("Full duplex not supported by master\n"); + ret = -EIO; + goto err_ckeck_full_duplex; + } + ts->client->bits_per_word = 8; + ts->client->mode = SPI_MODE_0; + ts->client->max_speed_hz = ts->spi_max_freq; + ts->debug_flag = 2; + + ret = spi_setup(ts->client); + if (ret < 0) { + NVT_ERR("Failed to perform SPI setup\n"); + goto err_spi_setup; + } + +#ifdef CONFIG_MTK_SPI + /* old usage of MTK spi API */ + memcpy(&ts->spi_ctrl, &spi_ctrdata, sizeof(struct mt_chip_conf)); + ts->client->controller_data = (void *)&ts->spi_ctrl; +#endif + +#ifdef CONFIG_SPI_MT65XX + /* new usage of MTK spi API */ + memcpy(&ts->spi_ctrl, &spi_ctrdata, sizeof(struct mtk_chip_config)); + ts->client->controller_data = (void *)&ts->spi_ctrl; +#endif + + NVT_LOG("mode=%d, max_speed_hz=%d\n", ts->client->mode, + ts->client->max_speed_hz); + + ret = nvt_pinctrl_init(ts); + if (!ret && ts->ts_pinctrl) { + ret = pinctrl_select_state(ts->ts_pinctrl, + ts->pinctrl_state_active); + + if (ret < 0) { + NVT_ERR("Failed to select %s pinstate %d\n", + PINCTRL_STATE_ACTIVE, ret); + } + } else { + NVT_ERR("Failed to init pinctrl\n"); + } + + NVT_LOG("Request GPIO\n"); + /* ---request and config GPIOs--- */ + ret = nvt_gpio_config(ts); + if (ret) { + NVT_ERR("gpio config error!\n"); + goto err_gpio_config_failed; + } + + mutex_init(&ts->lock); + mutex_init(&ts->xbuf_lock); + + /* ---eng reset before TP_RESX high */ + + nvt_eng_reset(); +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 1); +#endif + NVT_LOG("gpio set complete\n"); + /* need 10ms delay after POR(power on reset) */ + msleep(10); + + /* ---check chip version trim--- */ + NVT_LOG("start check chip\n"); + ret = nvt_ts_check_chip_ver_trim(); + if (ret) { + NVT_ERR("chip is not identified\n"); + ret = -EINVAL; + goto err_chipvertrim_failed; + } + NVT_LOG("finish check chip\n"); + + get_ts_xsfer(NVT_SPI_NAME); + tmp_drop_ts_xsfer(); + ts->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; + ts->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + ts->input_dev = input_allocate_device(); + if (ts->input_dev == NULL) { + NVT_ERR("allocate input device failed\n"); + ret = -ENOMEM; + goto err_input_dev_alloc_failed; + } + + ts->max_touch_num = TOUCH_MAX_FINGER_NUM; + + ts->int_trigger_type = INT_TRIGGER_TYPE; + + ts->input_dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | + BIT_MASK(EV_ABS); + __set_bit(BTN_TOUCH, ts->input_dev->keybit); + __set_bit(BTN_TOOL_FINGER, ts->input_dev->keybit); + ts->input_dev->propbit[0] = BIT(INPUT_PROP_DIRECT); + +#if MT_PROTOCOL_B + input_mt_init_slots(ts->input_dev, ts->max_touch_num, 0); +#endif + +#if TOUCH_MAX_FINGER_NUM > 1 + /*input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);*/ + + input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, 0, + ts->abs_x_max - 1, 0, 0); + input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, 0, + ts->abs_y_max - 1, 0, 0); +#if MT_PROTOCOL_B + /* no need to set ABS_MT_TRACKING_ID, input_mt_init_slots() already set it */ +#else + input_set_abs_params(ts->input_dev, ABS_MT_TRACKING_ID, 0, + ts->max_touch_num, 0, 0); +#endif +#endif + +#if WAKEUP_GESTURE + input_set_capability(ts->input_dev, EV_KEY, KEY_WAKEUP); +#endif + + sprintf(ts->phys, "input/ts"); + ts->input_dev->name = NVT_TS_NAME; + ts->input_dev->phys = ts->phys; + ts->input_dev->id.bustype = BUS_SPI; + + input_set_drvdata(ts->input_dev, ts); + ret = input_register_device(ts->input_dev); + if (ret) { + NVT_ERR("register input device (%s) failed. ret=%d\n", + ts->input_dev->name, ret); + goto err_input_register_device_failed; + } + + ts->client->irq = gpio_to_irq(ts->irq_gpio); + if (ts->client->irq) { + NVT_LOG("int_trigger_type=%d\n", ts->int_trigger_type); + ts->irq_enabled = true; + ret = request_threaded_irq(ts->client->irq, NULL, + nvt_ts_work_func, + ts->int_trigger_type | IRQF_ONESHOT, + NVT_SPI_NAME, ts); + if (ret != 0) { + NVT_ERR("request irq failed. ret=%d\n", ret); + goto err_int_request_failed; + } else { + nvt_irq_enable(false); + NVT_LOG("request irq %d succeed\n", ts->client->irq); + } + } + + INIT_WORK(&ts->switch_mode_work, nvt_switch_mode_work); + + pm_stay_awake(&ts->pdev->dev); + nvt_lockdown_wq = alloc_workqueue("nvt_lockdown_wq", + WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + if (!nvt_lockdown_wq) { + NVT_ERR("nvt_fwu_wq create workqueue failed\n"); + ret = -ENOMEM; + goto err_create_nvt_lockdown_wq_failed; + } + INIT_DELAYED_WORK(&ts->nvt_lockdown_work, get_lockdown_info); + /* please make sure boot update start after display reset(RESX) sequence*/ + queue_delayed_work(nvt_lockdown_wq, &ts->nvt_lockdown_work, + msecs_to_jiffies(1000)); + +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 1); +#endif + ts->ic_state = NVT_IC_INIT; + ts->dev_pm_suspend = false; + ts->gesture_command_delayed = -1; + init_completion(&ts->dev_pm_suspend_completion); + +#if BOOT_UPDATE_FIRMWARE + nvt_fwu_wq = + alloc_workqueue("nvt_fwu_wq", WQ_UNBOUND | WQ_MEM_RECLAIM, 1); + if (!nvt_fwu_wq) { + NVT_ERR("nvt_fwu_wq create workqueue failed\n"); + ret = -ENOMEM; + goto err_create_nvt_fwu_wq_failed; + } + INIT_DELAYED_WORK(&ts->nvt_fwu_work, Boot_Update_Firmware); + /* please make sure boot update start after display reset(RESX) sequence */ + queue_delayed_work(nvt_fwu_wq, &ts->nvt_fwu_work, + msecs_to_jiffies(10000)); +#endif + + NVT_LOG("NVT_TOUCH_ESD_PROTECT is %d\n", NVT_TOUCH_ESD_PROTECT); +#if NVT_TOUCH_ESD_PROTECT + INIT_DELAYED_WORK(&nvt_esd_check_work, nvt_esd_check_func); + nvt_esd_check_wq = + alloc_workqueue("nvt_esd_check_wq", WQ_MEM_RECLAIM, 1); + if (!nvt_esd_check_wq) { + NVT_ERR("nvt_esd_check_wq create workqueue failed\n"); + ret = -ENOMEM; + goto err_create_nvt_esd_check_wq_failed; + } + queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, + msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#if NVT_TOUCH_PROC + ret = nvt_flash_proc_init(); + if (ret != 0) { + NVT_ERR("nvt flash proc init failed. ret=%d\n", ret); + goto err_flash_proc_init_failed; + } +#endif + +#if NVT_TOUCH_EXT_PROC + ret = nvt_extra_proc_init(); + if (ret != 0) { + NVT_ERR("nvt extra proc init failed. ret=%d\n", ret); + goto err_extra_proc_init_failed; + } +#endif + +#if NVT_TOUCH_MP + ret = nvt_mp_proc_init(); + if (ret != 0) { + NVT_ERR("nvt mp proc init failed. ret=%d\n", ret); + goto err_mp_proc_init_failed; + } + +#ifndef NVT_SAVE_TESTDATA_IN_FILE + ret = nvt_test_data_proc_init(ts->client); + if (ret < 0) { + NVT_ERR("nvt test data interface init failed. ret=%d\n", ret); + goto err_mp_proc_init_failed; + } +#endif + +#endif + attrs_p = (struct attribute_group *)devm_kzalloc( + &pdev->dev, sizeof(*attrs_p), GFP_KERNEL); + if (!attrs_p) { + NVT_ERR("no mem to alloc"); + goto err_mp_proc_init_failed; + } + ts->attrs = attrs_p; + attrs_p->name = "panel_info"; + attrs_p->attrs = nvt_panel_attr; + ret = sysfs_create_group(&pdev->dev.kobj, ts->attrs); + + ts->event_wq = + alloc_workqueue("nvt-event-queue", + WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); + if (!ts->event_wq) { + NVT_ERR("Can not create work thread for suspend/resume!!"); + ret = -ENOMEM; + goto err_alloc_work_thread_failed; + } + INIT_WORK(&ts->resume_work, nvt_resume_work); + /*INIT_WORK(&ts->suspend_work, nvt_suspend_work);*/ + +#ifdef CONFIG_DRM + ts->drm_notif.notifier_call = nvt_drm_notifier_callback; + ret = drm_register_client(&ts->drm_notif); + if (ret) { + NVT_ERR("register drm_notifier failed. ret=%d\n", ret); + goto err_register_drm_notif_failed; + } +#else + ts->fb_notif.notifier_call = nvt_fb_notifier_callback; + ret = fb_register_client(&ts->fb_notif); + if (ret) { + NVT_ERR("register fb_notifier failed. ret=%d\n", ret); + goto err_register_fb_notif_failed; + } +#endif +#if defined(CONFIG_HAS_EARLYSUSPEND) + ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1; + ts->early_suspend.suspend = nvt_ts_early_suspend; + ts->early_suspend.resume = nvt_ts_late_resume; + ret = register_early_suspend(&ts->early_suspend); + if (ret) { + NVT_ERR("register early suspend failed. ret=%d\n", ret); + goto err_register_early_suspend_failed; + } +#endif + +#ifdef CONFIG_TOUCHSCREEN_NVT_DEBUG_FS + ts->debugfs = debugfs_create_dir("tp_debug", NULL); + if (ts->debugfs) { + debugfs_create_file("switch_state", 0660, ts->debugfs, ts, + &tpdbg_ops); + debugfs_create_file("touch_boost", 0660, ts->debugfs, ts, + &nvt_touch_test_fops); + } +#endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + xiaomi_touch_interfaces.touch_vendor_read = nvt_touch_vendor_read; + xiaomi_touch_interfaces.panel_display_read = nvt_panel_display_read; + xiaomi_touch_interfaces.panel_vendor_read = nvt_panel_vendor_read; + xiaomi_touch_interfaces.panel_color_read = nvt_panel_color_read; + xiaomi_touch_interfaces.getModeValue = nvt_get_mode_value; + xiaomi_touch_interfaces.setModeValue = nvt_set_cur_value; + xiaomi_touch_interfaces.resetMode = nvt_reset_mode; + xiaomi_touch_interfaces.getModeAll = nvt_get_mode_all; + xiaomi_touch_interfaces.palm_sensor_write = nvt_palm_sensor_write; + nvt_init_touchmode_data(); + xiaomitouch_register_modedata(&xiaomi_touch_interfaces); +#endif + + bTouchIsAwake = 1; + NVT_LOG("end\n"); + + nvt_irq_enable(true); + + return 0; + +#ifdef CONFIG_DRM + if (drm_unregister_client(&ts->drm_notif)) + NVT_ERR("Error occurred while unregistering drm_notifier.\n"); +err_register_drm_notif_failed: +#else + if (fb_unregister_client(&ts->fb_notif)) + NVT_ERR("Error occurred while unregistering fb_notifier.\n"); +err_register_fb_notif_failed: +#endif +#if defined(CONFIG_HAS_EARLYSUSPEND) + unregister_early_suspend(&ts->early_suspend); +err_register_early_suspend_failed: +#endif + destroy_workqueue(ts->event_wq); +err_alloc_work_thread_failed: +#if NVT_TOUCH_MP + nvt_mp_proc_deinit(); +err_mp_proc_init_failed: +#endif +#if NVT_TOUCH_EXT_PROC + nvt_extra_proc_deinit(); +err_extra_proc_init_failed: +#endif +#if NVT_TOUCH_PROC + nvt_flash_proc_deinit(); +err_flash_proc_init_failed: +#endif +#if NVT_TOUCH_ESD_PROTECT + if (nvt_esd_check_wq) { + cancel_delayed_work_sync(&nvt_esd_check_work); + destroy_workqueue(nvt_esd_check_wq); + nvt_esd_check_wq = NULL; + } +err_create_nvt_esd_check_wq_failed: +#endif +#if BOOT_UPDATE_FIRMWARE + if (nvt_fwu_wq) { + cancel_delayed_work_sync(&ts->nvt_fwu_work); + destroy_workqueue(nvt_fwu_wq); + nvt_fwu_wq = NULL; + } +err_create_nvt_fwu_wq_failed: + if (nvt_lockdown_wq) { + cancel_delayed_work_sync(&ts->nvt_lockdown_work); + destroy_workqueue(nvt_lockdown_wq); + nvt_lockdown_wq = NULL; + } +#endif +err_create_nvt_lockdown_wq_failed: + pm_relax(&ts->pdev->dev); +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 0); +#endif + free_irq(ts->client->irq, ts); +err_int_request_failed: + input_unregister_device(ts->input_dev); + ts->input_dev = NULL; +err_input_register_device_failed: + if (ts->input_dev) { + input_free_device(ts->input_dev); + ts->input_dev = NULL; + } +err_input_dev_alloc_failed: +err_chipvertrim_failed: + mutex_destroy(&ts->xbuf_lock); + mutex_destroy(&ts->lock); + nvt_gpio_deconfig(ts); +err_gpio_config_failed: +err_spi_setup: +err_ckeck_full_duplex: + spi_set_drvdata(ts->client, NULL); +err_get_spi: + tmp_drop_ts_xsfer(); + if (ts->xbuf) { + kfree(ts->xbuf); + ts->xbuf = NULL; + } + if (ts) { + kfree(ts); + ts = NULL; + } + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen driver release function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_ts_remove(struct platform_device *pdev) +{ + NVT_LOG("Removing driver...\n"); + +#ifdef CONFIG_DRM + if (drm_unregister_client(&ts->drm_notif)) + NVT_ERR("Error occurred while unregistering drm_notifier.\n"); +#else + if (fb_unregister_client(&ts->fb_notif)) + NVT_ERR("Error occurred while unregistering fb_notifier.\n"); +#endif +#if defined(CONFIG_HAS_EARLYSUSPEND) + unregister_early_suspend(&ts->early_suspend); +#endif +#ifndef NVT_SAVE_TESTDATA_IN_FILE + nvt_test_data_proc_deinit(); +#endif +#if NVT_TOUCH_MP + nvt_mp_proc_deinit(); +#endif +#if NVT_TOUCH_EXT_PROC + nvt_extra_proc_deinit(); +#endif +#if NVT_TOUCH_PROC + nvt_flash_proc_deinit(); +#endif + +#if NVT_TOUCH_ESD_PROTECT + if (nvt_esd_check_wq) { + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); + destroy_workqueue(nvt_esd_check_wq); + nvt_esd_check_wq = NULL; + } +#endif + +#if BOOT_UPDATE_FIRMWARE + if (nvt_fwu_wq) { + cancel_delayed_work_sync(&ts->nvt_fwu_work); + destroy_workqueue(nvt_fwu_wq); + nvt_fwu_wq = NULL; + } +#endif + +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 0); +#endif + + nvt_irq_enable(false); + free_irq(ts->client->irq, ts); + + mutex_destroy(&ts->xbuf_lock); + mutex_destroy(&ts->lock); + + nvt_gpio_deconfig(ts); + + if (ts->input_dev) { + input_unregister_device(ts->input_dev); + ts->input_dev = NULL; + } + + spi_set_drvdata(ts->client, NULL); + + put_ts_xsfer(NVT_SPI_NAME); + if (ts) { + kfree(ts); + ts = NULL; + } + + return 0; +} + +static void nvt_ts_shutdown(struct platform_device *pdev) +{ + NVT_LOG("Shutdown driver...\n"); + + nvt_irq_enable(false); + +#ifdef CONFIG_DRM + if (drm_unregister_client(&ts->drm_notif)) + NVT_ERR("Error occurred while unregistering drm_notifier.\n"); +#else + if (fb_unregister_client(&ts->fb_notif)) + NVT_ERR("Error occurred while unregistering fb_notifier.\n"); +#endif +#if defined(CONFIG_HAS_EARLYSUSPEND) + unregister_early_suspend(&ts->early_suspend); +#endif +#if NVT_TOUCH_MP + nvt_mp_proc_deinit(); +#endif +#if NVT_TOUCH_EXT_PROC + nvt_extra_proc_deinit(); +#endif +#if NVT_TOUCH_PROC + nvt_flash_proc_deinit(); +#endif + +#if NVT_TOUCH_ESD_PROTECT + if (nvt_esd_check_wq) { + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); + destroy_workqueue(nvt_esd_check_wq); + nvt_esd_check_wq = NULL; + } +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + +#if WAKEUP_GESTURE + device_init_wakeup(&ts->input_dev->dev, 0); +#endif +} + +/******************************************************* +Description: + Novatek touchscreen driver suspend function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_ts_suspend(struct device *dev) +{ + uint8_t buf[4] = { 0 }; +#if MT_PROTOCOL_B + uint32_t i = 0; +#endif + int ret = 0; + if (!bTouchIsAwake) { + NVT_LOG("Touch is already suspend\n"); + return 0; + } + pm_stay_awake(dev); + ts->ic_state = NVT_IC_SUSPEND_IN; + +#if NVT_TOUCH_ESD_PROTECT + NVT_LOG("cancel delayed work sync\n"); + cancel_delayed_work_sync(&nvt_esd_check_work); + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + NVT_LOG("start\n"); + + if (!ts->db_wakeup) + nvt_irq_enable(false); /*must before hold lock*/ + + mutex_lock(&ts->lock); + bTouchIsAwake = 0; + +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + if (ts->palm_sensor_switch) { + NVT_LOG("palm sensor on status, switch to off\n"); + update_palm_sensor_value(0); + nvt_set_pocket_palm_switch(false); + } +#endif + mdelay(10); + if (ts->db_wakeup) { + /* ---write command to enter "wakeup gesture mode"--- */ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x13; + CTP_SPI_WRITE(ts->client, buf, 2); + + enable_irq_wake(ts->client->irq); + + NVT_LOG("Enabled touch wakeup gesture\n"); + + } else { + /* ---write command to enter "deep sleep mode"--- */ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x11; + CTP_SPI_WRITE(ts->client, buf, 2); + if (ts->ts_pinctrl) { + ret = pinctrl_select_state(ts->ts_pinctrl, + ts->pinctrl_state_suspend); + + if (ret < 0) { + NVT_ERR("Failed to select %s pinstate %d\n", + PINCTRL_STATE_SUSPEND, ret); + } + } else { + NVT_ERR("Failed to init pinctrl\n"); + } + } + mdelay(10); + mutex_unlock(&ts->lock); + /* release all touches */ +#if MT_PROTOCOL_B + for (i = 0; i < ts->max_touch_num; i++) { + input_mt_slot(ts->input_dev, i); + /*input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0);*/ + input_report_abs(ts->input_dev, ABS_MT_PRESSURE, 0); + input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0); + } +#endif + input_report_key(ts->input_dev, BTN_TOOL_FINGER, 0); + input_report_key(ts->input_dev, BTN_TOUCH, 0); +#if !MT_PROTOCOL_B + input_mt_sync(ts->input_dev); +#endif + input_sync(ts->input_dev); + + msleep(50); + if (likely(ts->ic_state == NVT_IC_SUSPEND_IN)) + ts->ic_state = NVT_IC_SUSPEND_OUT; + else + NVT_ERR("IC state may error,caused by suspend/resume flow, please CHECK!!"); + NVT_LOG("end\n"); + pm_relax(dev); + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen driver resume function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_ts_resume(struct device *dev) +{ + int ret; + if (ts->dev_pm_suspend) + pm_stay_awake(dev); + if (!ts->db_wakeup) { + if (ts->ts_pinctrl) { + ret = pinctrl_select_state(ts->ts_pinctrl, + ts->pinctrl_state_active); + + if (ret < 0) { + NVT_ERR("Failed to select %s pinstate %d\n", + PINCTRL_STATE_ACTIVE, ret); + } + } else { + NVT_ERR("Failed to init pinctrl\n"); + } + } + if (bTouchIsAwake) { + NVT_LOG("Touch is already resume\n"); +#if NVT_TOUCH_WDT_RECOVERY + mutex_lock(&ts->lock); + if (nvt_get_dbgfw_status()) { + ret = nvt_update_firmware(DEFAULT_DEBUG_FW_NAME); + } else { + ret = nvt_update_firmware(ts->fw_name); + } + mutex_unlock(&ts->lock); +#endif /* #if NVT_TOUCH_WDT_RECOVERY */ + goto Exit; + } + + ts->ic_state = NVT_IC_RESUME_IN; + + mutex_lock(&ts->lock); + NVT_LOG("start\n"); + + /* please make sure display reset(RESX) sequence and mipi dsi cmds sent before this */ +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 1); +#endif + if (nvt_get_dbgfw_status()) { + ret = nvt_update_firmware(DEFAULT_DEBUG_FW_NAME); + if (ret < 0) { + NVT_ERR("use built-in fw"); + ret = nvt_update_firmware(ts->fw_name); + } + } else { + ret = nvt_update_firmware(ts->fw_name); + } + if (ret) + NVT_ERR("download firmware failed\n"); + nvt_check_fw_reset_state(RESET_STATE_REK); + + nvt_irq_enable(true); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); + queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, + msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + bTouchIsAwake = 1; +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE + NVT_LOG("palm_sensor_switch=%d", ts->palm_sensor_switch); + if (ts->palm_sensor_switch) { + NVT_LOG("palm sensor on status, switch to on\n"); + nvt_set_pocket_palm_switch(true); + } +#endif + mutex_unlock(&ts->lock); + dsi_panel_doubleclick_enable( + !!ts->db_wakeup); /*if true, dbclick work until next suspend*/ + if (likely(ts->ic_state == NVT_IC_RESUME_IN)) + ts->ic_state = NVT_IC_RESUME_OUT; + else + NVT_ERR("IC state may error,caused by suspend/resume flow, please CHECK!!"); + + if (ts->gesture_command_delayed >= 0) { + ts->db_wakeup = ts->gesture_command_delayed; + ts->gesture_command_delayed = -1; + NVT_LOG("execute delayed command, set double click wakeup %d\n", + ts->db_wakeup); + dsi_panel_doubleclick_enable(!!ts->db_wakeup); + } +Exit: + if (ts->dev_pm_suspend) + pm_relax(dev); + NVT_LOG("end\n"); + + return 0; +} + +#ifdef CONFIG_DRM +static int nvt_drm_notifier_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct drm_notify_data *evdata = data; + int *blank; + struct nvt_ts_data *ts_data = + container_of(self, struct nvt_ts_data, drm_notif); + + if (evdata && ts_data) { + blank = evdata->data; + NVT_LOG("%s: event:%lu,blank:%u\n", event, blank); + + if (event == DRM_EARLY_EVENT_BLANK) { + if (*blank == DRM_BLANK_POWERDOWN) { + NVT_LOG("event=%lu, *blank=%d\n", event, + *blank); + flush_workqueue(ts_data->event_wq); + nvt_ts_suspend(&ts_data->client->dev); + } + } else if (event == DRM_EVENT_BLANK) { + if (*blank == DRM_BLANK_UNBLANK) { + NVT_LOG("event=%lu, *blank=%d\n", event, + *blank); + flush_workqueue(ts_data->event_wq); + queue_work(ts_data->event_wq, + &ts_data->resume_work); + } + } + } + return NOTIFY_OK; +} + +#else +static int nvt_fb_notifier_callback(struct notifier_block *self, + unsigned long event, void *data) +{ + struct fb_event *evdata = data; + int *blank; + struct nvt_ts_data *ts = + container_of(self, struct nvt_ts_data, fb_notif); + + if (evdata && evdata->data && event == FB_EARLY_EVENT_BLANK) { + blank = evdata->data; + if (*blank == FB_BLANK_POWERDOWN) { + NVT_LOG("event=%lu, *blank=%d\n", event, *blank); + flush_workqueue(ts->event_wq); + nvt_ts_suspend(&ts->client->dev); + } + } else if (evdata && evdata->data && event == FB_EVENT_BLANK) { + blank = evdata->data; + if (*blank == FB_BLANK_UNBLANK) { + NVT_LOG("event=%lu, *blank=%d\n", event, *blank); + flush_workqueue(ts->event_wq); + queue_work(ts->event_wq, &ts->resume_work); + } + } + + return 0; +} +#endif + +static int nvt_pm_suspend(struct device *dev) +{ + if (device_may_wakeup(dev) && ts->db_wakeup) { + NVT_LOG("enable touch irq wake\n"); + enable_irq_wake(ts->client->irq); + } + ts->dev_pm_suspend = true; + reinit_completion(&ts->dev_pm_suspend_completion); + + return 0; +} + +static int nvt_pm_resume(struct device *dev) +{ + if (device_may_wakeup(dev) && ts->db_wakeup) { + NVT_LOG("disable touch irq wake\n"); + disable_irq_wake(ts->client->irq); + } + ts->dev_pm_suspend = false; + complete(&ts->dev_pm_suspend_completion); + + return 0; +} + +static const struct dev_pm_ops nvt_dev_pm_ops = { + .suspend = nvt_pm_suspend, + .resume = nvt_pm_resume, +}; + +#if defined(CONFIG_HAS_EARLYSUSPEND) +/******************************************************* +Description: + Novatek touchscreen driver early suspend function. + +return: + n.a. +*******************************************************/ +static void nvt_ts_early_suspend(struct early_suspend *h) +{ + nvt_ts_suspend(ts->client, PMSG_SUSPEND); +} + +/******************************************************* +Description: + Novatek touchscreen driver late resume function. + +return: + n.a. +*******************************************************/ +static void nvt_ts_late_resume(struct early_suspend *h) +{ + nvt_ts_resume(ts->client); +} +#endif + +static const struct platform_device_id nvt_ts_id[] = { + { NVT_SPI_NAME, 0 }, + {}, +}; + +#ifdef CONFIG_OF +static struct of_device_id nvt_match_table[] = { + { + .compatible = "novatek,NVT-ts-spi", + }, + {}, +}; +#endif + +static struct platform_driver nvt_driver = { + .probe = nvt_ts_probe, + .remove = nvt_ts_remove, + .shutdown = nvt_ts_shutdown, + .id_table = nvt_ts_id, + .driver = { + .name = NVT_SPI_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_PM + .pm = &nvt_dev_pm_ops, +#endif +#ifdef CONFIG_OF + .of_match_table = nvt_match_table, +#endif + }, +}; + +static bool nvt_off_charger_mode(void) +{ + bool charger_mode = false; + char charger_node[8] = { '\0' }; + char *chose = (char *)strnstr(saved_command_line, "androidboot.mode=", + strlen(saved_command_line)); + if (chose) { + memcpy(charger_node, (chose + strlen("androidboot.mode=")), + sizeof(charger_node) - 1); + NVT_LOG("%s: charger_node is %s\n", __func__, charger_node); + if (!strncmp(charger_node, "charger", strlen("charger"))) { + charger_mode = true; + } + } + return charger_mode; +} + +/******************************************************* +Description: + Driver Install function. + +return: + Executive Outcomes. 0---succeed. not 0---failed. +********************************************************/ +static int32_t __init nvt_driver_init(void) +{ + int32_t ret = 0; + + NVT_LOG("start\n"); + if (nvt_off_charger_mode()) { + NVT_LOG("off_charger states, %s exit", __func__); + return 0; + } + + /* ---add platform driver--- */ + ret = platform_driver_register(&nvt_driver); + if (ret) { + NVT_ERR("failed to add nvt touch driver"); + goto err_driver; + } + + NVT_LOG("finished\n"); + +err_driver: + return ret; +} + +/******************************************************* +Description: + Driver uninstall function. + +return: + n.a. +********************************************************/ +static void __exit nvt_driver_exit(void) +{ + platform_driver_unregister(&nvt_driver); +} +late_initcall(nvt_driver_init); + +MODULE_DESCRIPTION("Novatek Touchscreen Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.h b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.h new file mode 100644 index 000000000000..130c28373106 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.h @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * + * $Revision: 32206 $ + * $Date: 2018-08-10 19:23:04 +0800 (週五, 10 八月 2018) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#ifndef _LINUX_NVT_TOUCH_H +#define _LINUX_NVT_TOUCH_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif + +#include "nt36xxx_mem_map.h" + +#ifdef CONFIG_MTK_SPI +#include "mtk_spi.h" +#endif + +#ifdef CONFIG_SPI_MT65XX +#include +#endif + +#define FW_HISTORY_SIZE 128 +/*Lock down info size*/ +#define NVT_LOCKDOWN_SIZE 8 + +#define PINCTRL_STATE_ACTIVE "pmx_ts_active" +#define PINCTRL_STATE_SUSPEND "pmx_ts_suspend" +#define PINCTRL_STATE_RELEASE "pmx_ts_release" + +#define TOUCH_DISABLE_LPM 1 +#define TOUCH_IRQ_BOOST 2 + +/* ---GPIO number--- */ +#define NVTTOUCH_RST_PIN 980 +#define NVTTOUCH_INT_PIN 943 + +/* ---INT trigger mode--- */ +/* #define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 */ +#define INT_TRIGGER_TYPE IRQ_TYPE_EDGE_RISING + +/* ---SPI driver info.--- */ +#define NVT_SPI_NAME "NVT-ts-spi" +#define NVT_LOG(fmt, args...) \ + pr_info("[%s] %s %d: " fmt, NVT_SPI_NAME, __func__, __LINE__, ##args) +#define NVT_ERR(fmt, args...) \ + pr_err("[%s] %s %d: " fmt, NVT_SPI_NAME, __func__, __LINE__, ##args) + +/* ---Input device info.--- */ +#define NVT_TS_NAME "NVTCapacitiveTouchScreen" + +/* ---Touch info.--- */ +#define TOUCH_DEFAULT_MAX_WIDTH 1080 +#define TOUCH_DEFAULT_MAX_HEIGHT 2400 +#define TOUCH_MAX_FINGER_NUM 10 +#define TOUCH_KEY_NUM 0 +#define TOUCH_FORCE_NUM 1000 + +/* Enable only when module have tp reset pin and connected to host */ +#define NVT_TOUCH_SUPPORT_HW_RST 1 + +/* ---Customerized func.--- */ +#define NVT_TOUCH_PROC 1 +#define NVT_TOUCH_EXT_PROC 1 +#define NVT_TOUCH_MP 1 +#define NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV 1 +#define MT_PROTOCOL_B 1 +#define WAKEUP_GESTURE 1 +#define FUNCPAGE_PALM 4 +#define PACKET_PALM_ON 3 +#define PACKET_PALM_OFF 4 + +#define BOOT_UPDATE_FIRMWARE 1 +#define DEFAULT_BOOT_UPDATE_FIRMWARE_FIRST "j20s_novatek_ts_fw01.bin" +#define DEFAULT_MP_UPDATE_FIRMWARE_FIRST "j20s_novatek_ts_mp01.bin" +#define DEFAULT_BOOT_UPDATE_FIRMWARE_SECOND "j20s_novatek_ts_fw02.bin" +#define DEFAULT_MP_UPDATE_FIRMWARE_SECOND "j20s_novatek_ts_mp02.bin" +#define DEFAULT_DEBUG_FW_NAME "novatek_debug_fw.bin" +#define DEFAULT_DEBUG_MP_NAME "novatek_debug_mp.bin" + +/* ---ESD Protect.--- */ +#define NVT_TOUCH_ESD_PROTECT 1 +#define NVT_TOUCH_ESD_CHECK_PERIOD 1500 /* ms */ +#define NVT_TOUCH_WDT_RECOVERY 1 +#define NVT_TOUCH_ESD_DISP_RECOVERY 1 + +struct nvt_config_info { + u8 tp_vendor; + u8 tp_color; + u8 display_maker; + u8 glass_vendor; + const char *nvt_fw_name; + const char *nvt_mp_name; + const char *nvt_limit_name; +}; + +enum nvt_ic_state { + NVT_IC_SUSPEND_IN, + NVT_IC_SUSPEND_OUT, + NVT_IC_RESUME_IN, + NVT_IC_RESUME_OUT, + NVT_IC_INIT, +}; + +struct nvt_ts_data { + struct spi_device *client; + struct platform_device *pdev; + struct input_dev *input_dev; + struct delayed_work nvt_fwu_work; + struct delayed_work nvt_lockdown_work; + struct work_struct switch_mode_work; + uint16_t addr; + int8_t phys[32]; + +#ifdef CONFIG_DRM + struct notifier_block drm_notif; +#else + struct notifier_block fb_notif; +#endif +#if defined(CONFIG_HAS_EARLYSUSPEND) + struct early_suspend early_suspend; +#endif + + uint8_t fw_ver; + uint8_t x_num; + uint8_t y_num; + uint16_t abs_x_max; + uint16_t abs_y_max; + uint8_t max_touch_num; + uint8_t max_button_num; + uint32_t int_trigger_type; + int32_t irq_gpio; + uint32_t irq_flags; + int32_t reset_gpio; + uint32_t reset_flags; + struct mutex lock; + const struct nvt_ts_mem_map *mmap; + uint8_t carrier_system; + uint8_t hw_crc; + uint16_t nvt_pid; + uint8_t rbuf[1025]; + uint8_t *xbuf; + struct mutex xbuf_lock; + bool irq_enabled; +#ifdef CONFIG_MTK_SPI + struct mt_chip_conf spi_ctrl; +#endif +#ifdef CONFIG_SPI_MT65XX + struct mtk_chip_config spi_ctrl; +#endif + struct pinctrl *ts_pinctrl; + struct pinctrl_state *pinctrl_state_active; + struct pinctrl_state *pinctrl_state_suspend; +#ifndef NVT_SAVE_TESTDATA_IN_FILE + void *testdata; +#endif + int db_wakeup; + bool lkdown_readed; + u8 lockdown_info[NVT_LOCKDOWN_SIZE]; + uint32_t config_array_size; + struct nvt_config_info *config_array; + int panel_index; + const u8 *fw_name; + const u8 *mp_name; + uint32_t spi_max_freq; + struct attribute_group *attrs; + /*bit map indicate which slot(0~9) has been used*/ + unsigned long slot_map[BITS_TO_LONGS(10)]; + bool fw_debug; +#ifdef CONFIG_TOUCHSCREEN_NVT_DEBUG_FS + struct dentry *debugfs; +#endif + struct workqueue_struct *event_wq; + struct work_struct suspend_work; + struct work_struct resume_work; + int result_type; + int ic_state; + int gesture_command_delayed; + bool dev_pm_suspend; + struct completion dev_pm_suspend_completion; + bool palm_sensor_switch; + uint8_t debug_flag; +}; + +#if NVT_TOUCH_PROC +struct nvt_flash_data { + rwlock_t lock; +}; +#endif + +typedef enum { + RESET_STATE_INIT = 0xA0, /* IC reset */ + RESET_STATE_REK, /* ReK baseline */ + RESET_STATE_REK_FINISH, /* baseline is ready */ + RESET_STATE_NORMAL_RUN, /* normal run */ + RESET_STATE_MAX = 0xAF +} RST_COMPLETE_STATE; + +typedef enum { + EVENT_MAP_HOST_CMD = 0x50, + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE = 0x51, + EVENT_MAP_RESET_COMPLETE = 0x60, + EVENT_MAP_FWINFO = 0x78, + EVENT_MAP_PROJECTID = 0x9A, +} SPI_EVENT_MAP; + +//---SPI READ/WRITE--- +#define SPI_WRITE_MASK(a) (a | 0x80) +#define SPI_READ_MASK(a) (a & 0x7F) + +#define DUMMY_BYTES (1) +#define NVT_TRANSFER_LEN (63 * 1024) + +typedef enum { + NVTWRITE = 0, + NVTREAD = 1, +} NVT_SPI_RW; + +//---extern structures--- +extern struct nvt_ts_data *ts; + +//---extern functions--- + +int32_t CTP_SPI_READ(struct spi_device *client, uint8_t *buf, uint16_t len); +int32_t CTP_SPI_WRITE(struct spi_device *client, uint8_t *buf, uint16_t len); +void nvt_bootloader_reset(void); +void nvt_eng_reset(void); +void nvt_sw_reset(void); +void nvt_sw_reset_idle(void); +void nvt_boot_ready(void); +void nvt_bld_crc_enable(void); +void nvt_fw_crc_enable(void); +int32_t nvt_update_firmware(const char *firmware_name); +int32_t nvt_check_fw_reset_state(RST_COMPLETE_STATE check_reset_state); +int32_t nvt_get_fw_info(void); +int32_t nvt_clear_fw_status(void); +int32_t nvt_check_fw_status(void); +int32_t nvt_set_page(uint32_t addr); +int32_t nvt_write_addr(uint32_t addr, uint8_t data); +void nvt_set_dbgfw_status(bool enable); +bool nvt_get_dbgfw_status(void); +void nvt_match_fw(void); +int32_t nvt_set_pocket_palm_switch(uint8_t pocket_palm_switch); +#if NVT_TOUCH_ESD_PROTECT +extern void nvt_esd_check_enable(uint8_t enable); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ +#endif /* _LINUX_NVT_TOUCH_H */ diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_ext_proc.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_ext_proc.c new file mode 100644 index 000000000000..ece36127360d --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_ext_proc.c @@ -0,0 +1,737 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * + * $Revision: 32206 $ + * $Date: 2018-08-10 19:23:04 +0800 (週五, 10 八月 2018) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include + +#include "nt36xxx.h" + +#if NVT_TOUCH_EXT_PROC +#define NVT_FW_VERSION "nvt_fw_version" +#define NVT_BASELINE "nvt_baseline" +#define NVT_RAW "nvt_raw" +#define NVT_DIFF "nvt_diff" +#define NVT_XIAOMI_CONFIG_INFO "nvt_xiaomi_config_info" +#define NVT_XIAOMI_LOCKDOWN_INFO "tp_lockdown_info" + +#define SPI_TANSFER_LENGTH 256 + +#define NORMAL_MODE 0x00 +#define TEST_MODE_1 0x21 +#define TEST_MODE_2 0x22 +#define HANDSHAKING_HOST_READY 0xBB + +#define XDATA_SECTOR_SIZE 256 + +static uint8_t xdata_tmp[2048] = { 0 }; +static int32_t xdata[2048] = { 0 }; + +static struct proc_dir_entry *NVT_proc_fw_version_entry; +static struct proc_dir_entry *NVT_proc_baseline_entry; +static struct proc_dir_entry *NVT_proc_raw_entry; +static struct proc_dir_entry *NVT_proc_diff_entry; +static struct proc_dir_entry *NVT_proc_xiaomi_config_info_entry; +static struct proc_dir_entry *NVT_proc_xiaomi_lockdown_info_entry; + +// Xiaomi Config Info. +static uint8_t nvt_xiaomi_conf_info_fw_ver = 0; +static uint8_t nvt_xiaomi_conf_info_fae_id = 0; +static uint64_t nvt_xiaomi_conf_info_reservation = 0; + +/******************************************************* +Description: + Novatek touchscreen change mode function. + +return: + n.a. +*******************************************************/ +void nvt_change_mode(uint8_t mode) +{ + uint8_t buf[8] = { 0 }; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + /* ---set mode--- */ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = mode; + CTP_SPI_WRITE(ts->client, buf, 2); + + if (mode == NORMAL_MODE) { + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = HANDSHAKING_HOST_READY; + CTP_SPI_WRITE(ts->client, buf, 2); + msleep(20); + } +} + +/******************************************************* +Description: + Novatek touchscreen get firmware pipe function. + +return: + Executive outcomes. 0---pipe 0. 1---pipe 1. +*******************************************************/ +uint8_t nvt_get_fw_pipe(void) +{ + uint8_t buf[8] = { 0 }; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + /* ---read fw status--- */ + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + return (buf[1] & 0x01); +} + +/******************************************************* +Description: + Novatek touchscreen read meta data function. + +return: + n.a. +*******************************************************/ +void nvt_read_mdata(uint32_t xdata_addr, uint32_t xdata_btn_addr) +{ + int32_t i = 0; + int32_t j = 0; + int32_t k = 0; + uint8_t buf[SPI_TANSFER_LENGTH + 1] = { 0 }; + uint32_t head_addr = 0; + int32_t dummy_len = 0; + int32_t data_len = 0; + int32_t residual_len = 0; + + /* ---set xdata sector address & length--- */ + head_addr = xdata_addr - (xdata_addr % XDATA_SECTOR_SIZE); + dummy_len = xdata_addr - head_addr; + data_len = ts->x_num * ts->y_num * 2; + residual_len = (head_addr + dummy_len + data_len) % XDATA_SECTOR_SIZE; + + //printk("head_addr=0x%05X, dummy_len=0x%05X, data_len=0x%05X, residual_len=0x%05X\n", head_addr, dummy_len, data_len, residual_len); + + /* read xdata : step 1 */ + for (i = 0; i < ((dummy_len + data_len) / XDATA_SECTOR_SIZE); i++) { + /* ---read xdata by SPI_TANSFER_LENGTH */ + for (j = 0; j < (XDATA_SECTOR_SIZE / SPI_TANSFER_LENGTH); j++) { + /* ---change xdata index--- */ + nvt_set_page(head_addr + (XDATA_SECTOR_SIZE * i) + + (SPI_TANSFER_LENGTH * j)); + + /* ---read data--- */ + buf[0] = SPI_TANSFER_LENGTH * j; + CTP_SPI_READ(ts->client, buf, SPI_TANSFER_LENGTH + 1); + + /* ---copy buf to xdata_tmp--- */ + for (k = 0; k < SPI_TANSFER_LENGTH; k++) { + xdata_tmp[XDATA_SECTOR_SIZE * i + + SPI_TANSFER_LENGTH * j + k] = + buf[k + 1]; + /* printk("0x%02X, 0x%04X\n", buf[k+1], (XDATA_SECTOR_SIZE*i + SPI_TANSFER_LENGTH*j + k)); */ + } + } + /* printk("addr=0x%05X\n", (head_addr+XDATA_SECTOR_SIZE*i)); */ + } + + /* read xdata : step2 */ + if (residual_len != 0) { + /* ---read xdata by SPI_TANSFER_LENGTH */ + for (j = 0; j < (residual_len / SPI_TANSFER_LENGTH + 1); j++) { + /* ---change xdata index--- */ + nvt_set_page(xdata_addr + data_len - residual_len + + (SPI_TANSFER_LENGTH * j)); + + /* ---read data--- */ + buf[0] = SPI_TANSFER_LENGTH * j; + CTP_SPI_READ(ts->client, buf, SPI_TANSFER_LENGTH + 1); + + /* ---copy buf to xdata_tmp--- */ + for (k = 0; k < SPI_TANSFER_LENGTH; k++) { + xdata_tmp[(dummy_len + data_len - residual_len) + + SPI_TANSFER_LENGTH * j + k] = + buf[k + 1]; + /* printk("0x%02X, 0x%04x\n", buf[k+1], ((dummy_len+data_len-residual_len) + SPI_TANSFER_LENGTH*j + k)); */ + } + } + /* printk("addr=0x%05X\n", (xdata_addr+data_len-residual_len)); */ + } + + /* ---remove dummy data and 2bytes-to-1data--- */ + for (i = 0; i < (data_len / 2); i++) { + xdata[i] = (int16_t)(xdata_tmp[dummy_len + i * 2] + + 256 * xdata_tmp[dummy_len + i * 2 + 1]); + } + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR); +} + +/******************************************************* +Description: + Novatek touchscreen get meta data function. + +return: + n.a. +*******************************************************/ +void nvt_get_mdata(int32_t *buf, uint8_t *m_x_num, uint8_t *m_y_num) +{ + *m_x_num = ts->x_num; + *m_y_num = ts->y_num; + memcpy(buf, xdata, + ((ts->x_num * ts->y_num + TOUCH_KEY_NUM) * sizeof(int32_t))); +} + +/******************************************************* +Description: + Novatek touchscreen firmware version show function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t c_fw_version_show(struct seq_file *m, void *v) +{ + seq_printf(m, "fw_ver=%d, x_num=%d, y_num=%d, button_num=%d\n", + ts->fw_ver, ts->x_num, ts->y_num, ts->max_button_num); + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print show + function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t c_show(struct seq_file *m, void *v) +{ + int32_t i = 0; + int32_t j = 0; + for (i = 0; i < ts->y_num; i++) { + for (j = 0; j < ts->x_num; j++) { + seq_printf(m, "%5d, ", xdata[i * ts->x_num + j]); + } + seq_puts(m, "\n"); + } + + seq_printf(m, "\n\n"); + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print start + function. + +return: + Executive outcomes. 1---call next function. + NULL---not call next function and sequence loop + stop. +*******************************************************/ +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print next + function. + +return: + Executive outcomes. NULL---no next and call sequence + stop function. +*******************************************************/ +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +/******************************************************* +Description: + Novatek touchscreen xdata sequence print stop + function. + +return: + n.a. +*******************************************************/ +static void c_stop(struct seq_file *m, void *v) +{ + return; +} + +const struct seq_operations nvt_fw_version_seq_ops = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_fw_version_show +}; + +const struct seq_operations nvt_seq_ops = { .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_show }; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_fw_version open + function. + +return: + n.a. +*******************************************************/ +static int32_t nvt_fw_version_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("%s ++\n", __func__); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + return seq_open(file, &nvt_fw_version_seq_ops); +} + +static const struct file_operations nvt_fw_version_fops = { + .owner = THIS_MODULE, + .open = nvt_fw_version_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_baseline open function. + +return: +Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_baseline_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("%s ++\n", __func__); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_change_mode(TEST_MODE_2); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_read_mdata(ts->mmap->BASELINE_ADDR, ts->mmap->BASELINE_BTN_ADDR); + + nvt_change_mode(NORMAL_MODE); + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + return seq_open(file, &nvt_seq_ops); +} + +static const struct file_operations nvt_baseline_fops = { + .owner = THIS_MODULE, + .open = nvt_baseline_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_raw open function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t nvt_raw_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("%s ++\n", __func__); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_change_mode(TEST_MODE_2); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->RAW_PIPE0_ADDR, + ts->mmap->RAW_BTN_PIPE0_ADDR); + else + nvt_read_mdata(ts->mmap->RAW_PIPE1_ADDR, + ts->mmap->RAW_BTN_PIPE1_ADDR); + + nvt_change_mode(NORMAL_MODE); + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + return seq_open(file, &nvt_seq_ops); +} + +static const struct file_operations nvt_raw_fops = { + .owner = THIS_MODULE, + .open = nvt_raw_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_diff open function. + +return: + Executive outcomes. 0---succeed. negative---failed. +*******************************************************/ +static int32_t nvt_diff_open(struct inode *inode, struct file *file) +{ + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("%s ++\n", __func__); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + nvt_change_mode(TEST_MODE_2); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + return -EAGAIN; + } + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->DIFF_PIPE0_ADDR, + ts->mmap->DIFF_BTN_PIPE0_ADDR); + else + nvt_read_mdata(ts->mmap->DIFF_PIPE1_ADDR, + ts->mmap->DIFF_BTN_PIPE1_ADDR); + + nvt_change_mode(NORMAL_MODE); + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + return seq_open(file, &nvt_seq_ops); +} + +static const struct file_operations nvt_diff_fops = { + .owner = THIS_MODULE, + .open = nvt_diff_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static int nvt_xiaomi_config_info_show(struct seq_file *m, void *v) +{ + seq_printf(m, "FW version/Config version, Debug version: 0x%02X\n", + nvt_xiaomi_conf_info_fw_ver); + seq_printf(m, "FAE ID: 0x%02X\n", nvt_xiaomi_conf_info_fae_id); + seq_printf(m, "Reservation byte: 0x%012llX\n", + nvt_xiaomi_conf_info_reservation); + + return 0; +} + +static int32_t nvt_xiaomi_config_info_open(struct inode *inode, + struct file *file) +{ + uint8_t buf[16] = { 0 }; + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + + NVT_LOG("%s ++\n", __func__); + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | 0x9C); + + buf[0] = 0x9C; + CTP_SPI_READ(ts->client, buf, 9); + + nvt_xiaomi_conf_info_fw_ver = buf[1]; + nvt_xiaomi_conf_info_fae_id = buf[2]; + nvt_xiaomi_conf_info_reservation = + (((uint64_t)buf[3] << 40) | ((uint64_t)buf[4] << 32) | + ((uint64_t)buf[5] << 24) | ((uint64_t)buf[6] << 16) | + ((uint64_t)buf[7] << 8) | (uint64_t)buf[8]); + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + return single_open(file, nvt_xiaomi_config_info_show, NULL); +} + +static const struct file_operations nvt_xiaomi_config_info_fops = { + .owner = THIS_MODULE, + .open = nvt_xiaomi_config_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int nvt_xiaomi_lockdown_info_show(struct seq_file *m, void *v) +{ + u8 *lk = ts->lockdown_info; + + seq_printf(m, + "0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", + lk[0], lk[1], lk[2], lk[3], lk[4], lk[5], lk[6], lk[7]); + return 0; +} + +static int32_t nvt_xiaomi_lockdown_info_open(struct inode *inode, + struct file *file) +{ + return single_open(file, nvt_xiaomi_lockdown_info_show, NULL); +} + +static const struct file_operations nvt_xiaomi_lockdown_info_fops = { + .owner = THIS_MODULE, + .open = nvt_xiaomi_lockdown_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +int32_t nvt_set_pocket_palm_switch(uint8_t pocket_palm_switch) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("set pocket palm switch: %d\n", pocket_palm_switch); + + msleep(35); + + /* ---set xdata index to EVENT BUF ADDR--- */ + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_pocket_palm_switch_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + if (pocket_palm_switch == 0) { + /* pocket palm disable */ + buf[1] = 0x74; + } else if (pocket_palm_switch == 1) { + /* pocket palm enable */ + buf[1] = 0x73; + } else { + NVT_ERR("Invalid value! pocket_palm_switch = %d\n", + pocket_palm_switch); + ret = -EINVAL; + goto nvt_set_pocket_palm_switch_out; + } + ret = CTP_SPI_WRITE(ts->client, buf, 2); + if (ret < 0) { + NVT_ERR("Write pocket palm switch command fail!\n"); + goto nvt_set_pocket_palm_switch_out; + } + +nvt_set_pocket_palm_switch_out: + NVT_LOG("%s --\n", __func__); + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen extra function proc. file node + initial function. + +return: + Executive outcomes. 0---succeed. -12---failed. +*******************************************************/ +int32_t nvt_extra_proc_init(void) +{ + NVT_proc_fw_version_entry = + proc_create(NVT_FW_VERSION, 0444, NULL, &nvt_fw_version_fops); + if (NVT_proc_fw_version_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_FW_VERSION); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_FW_VERSION); + } + + NVT_proc_baseline_entry = + proc_create(NVT_BASELINE, 0444, NULL, &nvt_baseline_fops); + if (NVT_proc_baseline_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_BASELINE); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_BASELINE); + } + + NVT_proc_raw_entry = proc_create(NVT_RAW, 0444, NULL, &nvt_raw_fops); + if (NVT_proc_raw_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_RAW); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_RAW); + } + + NVT_proc_diff_entry = proc_create(NVT_DIFF, 0444, NULL, &nvt_diff_fops); + if (NVT_proc_diff_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_DIFF); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_DIFF); + } + + NVT_proc_xiaomi_config_info_entry = + proc_create(NVT_XIAOMI_CONFIG_INFO, 0444, NULL, + &nvt_xiaomi_config_info_fops); + if (NVT_proc_xiaomi_config_info_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_XIAOMI_CONFIG_INFO); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", NVT_XIAOMI_CONFIG_INFO); + } + + NVT_proc_xiaomi_lockdown_info_entry = + proc_create(NVT_XIAOMI_LOCKDOWN_INFO, 0444, NULL, + &nvt_xiaomi_lockdown_info_fops); + if (NVT_proc_xiaomi_lockdown_info_entry == NULL) { + NVT_ERR("create proc/%s Failed!\n", NVT_XIAOMI_LOCKDOWN_INFO); + return -ENOMEM; + } else { + NVT_LOG("create proc/%s Succeeded!\n", + NVT_XIAOMI_LOCKDOWN_INFO); + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen extra function proc. file node + deinitial function. + +return: + n.a. +*******************************************************/ +void nvt_extra_proc_deinit(void) +{ + if (NVT_proc_fw_version_entry != NULL) { + remove_proc_entry(NVT_FW_VERSION, NULL); + NVT_proc_fw_version_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_FW_VERSION); + } + + if (NVT_proc_baseline_entry != NULL) { + remove_proc_entry(NVT_BASELINE, NULL); + NVT_proc_baseline_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_BASELINE); + } + + if (NVT_proc_raw_entry != NULL) { + remove_proc_entry(NVT_RAW, NULL); + NVT_proc_raw_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_RAW); + } + + if (NVT_proc_diff_entry != NULL) { + remove_proc_entry(NVT_DIFF, NULL); + NVT_proc_diff_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_DIFF); + } + + if (NVT_proc_xiaomi_config_info_entry != NULL) { + remove_proc_entry(NVT_XIAOMI_CONFIG_INFO, NULL); + NVT_proc_xiaomi_config_info_entry = NULL; + NVT_LOG("Removed /proc/%s\n", NVT_XIAOMI_CONFIG_INFO); + } +} +#endif diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_fw_update.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_fw_update.c new file mode 100644 index 000000000000..d405269671e7 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_fw_update.c @@ -0,0 +1,1184 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * + * $Revision: 32206 $ + * $Date: 2018-08-10 19:23:04 +0800 (週五, 10 八月 2018) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "nt36xxx.h" + +#if BOOT_UPDATE_FIRMWARE + +#define SIZE_4KB 4096 +#define FLASH_SECTOR_SIZE SIZE_4KB +#define FW_BIN_VER_OFFSET (fw_need_write_size - SIZE_4KB) +#define FW_BIN_VER_BAR_OFFSET (FW_BIN_VER_OFFSET + 1) +#define NVT_FLASH_END_FLAG_LEN 3 +#define NVT_FLASH_END_FLAG_ADDR (fw_need_write_size - NVT_FLASH_END_FLAG_LEN) + +#define NVT_DUMP_PARTITION (0) +#define NVT_DUMP_PARTITION_LEN (1024) +#define NVT_DUMP_PARTITION_PATH "/data/local/tmp" + +struct timeval start, end; +const struct firmware *fw_entry = NULL; +static size_t fw_need_write_size = 0; +static uint8_t *fwbuf = NULL; + +struct nvt_ts_bin_map { + char name[12]; + uint32_t BIN_addr; + uint32_t SRAM_addr; + uint32_t size; + uint32_t crc; +}; + +static struct nvt_ts_bin_map *bin_map; + +static int32_t nvt_get_fw_need_write_size(const struct firmware *fw_entry) +{ + int32_t i = 0; + int32_t total_sectors_to_check = 0; + + total_sectors_to_check = fw_entry->size / FLASH_SECTOR_SIZE; + /* printk("total_sectors_to_check = %d\n", total_sectors_to_check); */ + + for (i = total_sectors_to_check; i > 0; i--) { + /* printk("current end flag address checked = 0x%X\n", i * FLASH_SECTOR_SIZE - NVT_FLASH_END_FLAG_LEN); */ + /* check if there is end flag "NVT" at the end of this sector */ + if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - + NVT_FLASH_END_FLAG_LEN], + "NVT", NVT_FLASH_END_FLAG_LEN) == 0) { + fw_need_write_size = i * FLASH_SECTOR_SIZE; + NVT_LOG("fw_need_write_size = %zu(0x%zx), NVT end flag\n", + fw_need_write_size, fw_need_write_size); + return 0; + } + + /* check if there is end flag "MOD" at the end of this sector */ + if (strncmp(&fw_entry->data[i * FLASH_SECTOR_SIZE - + NVT_FLASH_END_FLAG_LEN], + "MOD", NVT_FLASH_END_FLAG_LEN) == 0) { + fw_need_write_size = i * FLASH_SECTOR_SIZE; + NVT_LOG("fw_need_write_size = %zu(0x%zx), MOD end flag\n", + fw_need_write_size, fw_need_write_size); + return 0; + } + } + + NVT_ERR("end flag \"NVT\" \"MOD\" not found!\n"); + return -1; +} + +/******************************************************* +Description: + Novatek touchscreen init variable and allocate buffer +for download firmware function. + +return: + n.a. +*******************************************************/ +static int32_t nvt_download_init(void) +{ + /* allocate buffer for transfer firmware */ + /* NVT_LOG("NVT_TRANSFER_LEN = 0x%06X\n", NVT_TRANSFER_LEN); */ + + if (fwbuf == NULL) { + fwbuf = (uint8_t *)kzalloc((NVT_TRANSFER_LEN + 1), GFP_KERNEL); + if (fwbuf == NULL) { + NVT_ERR("kzalloc for fwbuf failed!\n"); + return -ENOMEM; + } + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen checksum function. Calculate bin +file checksum for comparison. + +return: + n.a. +*******************************************************/ +static uint32_t CheckSum(const u8 *data, size_t len) +{ + uint32_t i = 0; + uint32_t checksum = 0; + + for (i = 0; i < len + 1; i++) + checksum += data[i]; + + checksum += len; + checksum = ~checksum + 1; + + return checksum; +} + +static uint32_t byte_to_word(const uint8_t *data) +{ + return data[0] + (data[1] << 8) + (data[2] << 16) + (data[3] << 24); +} + +/******************************************************* +Description: + Novatek touchscreen parsing bin header function. + +return: + n.a. +*******************************************************/ +static uint32_t partition = 0; +static uint8_t ilm_dlm_num = 2; +static int32_t nvt_bin_header_parser(const u8 *fwdata, size_t fwsize) +{ + uint32_t list = 0; + uint32_t pos = 0x00; + uint32_t end = 0x00; + uint8_t info_sec_num = 0; + uint8_t ovly_sec_num = 0; + uint8_t ovly_info = 0; + + /* Find the header size */ + end = fwdata[0] + (fwdata[1] << 8) + (fwdata[2] << 16) + + (fwdata[3] << 24); + pos = 0x30; /* info section start at 0x30 offset */ + while (pos < end) { + info_sec_num++; + pos += 0x10; /* each header info is 16 bytes */ + } + + /* + * Find the DLM OVLY section + * [0:3] Overlay Section Number + * [4] Overlay Info + */ + ovly_info = (fwdata[0x28] & 0x10) >> 4; + ovly_sec_num = (ovly_info) ? (fwdata[0x28] & 0x0F) : 0; + + /* + * calculate all partition number + * ilm_dlm_num (ILM & DLM) + ovly_sec_num + info_sec_num + */ + partition = ilm_dlm_num + ovly_sec_num + info_sec_num; + NVT_LOG("ovly_info = %d, ilm_dlm_num = %d, ovly_sec_num = %d, info_sec_num = %d, partition = %d\n", + ovly_info, ilm_dlm_num, ovly_sec_num, info_sec_num, partition); + + /* allocated memory for header info */ + bin_map = (struct nvt_ts_bin_map *)kzalloc( + (partition + 1) * sizeof(struct nvt_ts_bin_map), GFP_KERNEL); + if (bin_map == NULL) { + NVT_ERR("kzalloc for bin_map failed!\n"); + return -ENOMEM; + } + + for (list = 0; list < partition; list++) { + /* + * [1] parsing ILM & DLM header info + * BIN_addr : SRAM_addr : size (12-bytes) + * crc located at 0x18 & 0x1C + */ + if (list < ilm_dlm_num) { + bin_map[list].BIN_addr = + byte_to_word(&fwdata[0 + list * 12]); + bin_map[list].SRAM_addr = + byte_to_word(&fwdata[4 + list * 12]); + bin_map[list].size = + byte_to_word(&fwdata[8 + list * 12]); + if (ts->hw_crc) + bin_map[list].crc = + byte_to_word(&fwdata[0x18 + list * 4]); + else { //ts->hw_crc + if ((bin_map[list].BIN_addr + + bin_map[list].size) < fwsize) + bin_map[list].crc = CheckSum( + &fwdata[bin_map[list].BIN_addr], + bin_map[list].size); + else { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + + bin_map[list].size); + return -EINVAL; + } + } + if (list == 0) + sprintf(bin_map[list].name, "ILM"); + else if (list == 1) + sprintf(bin_map[list].name, "DLM"); + } + + /* + * [2] parsing others header info + * SRAM_addr : size : BIN_addr : crc (16-bytes) + */ + if ((list >= ilm_dlm_num) && + (list < (ilm_dlm_num + info_sec_num))) { + /* others partition located at 0x30 offset */ + pos = 0x30 + (0x10 * (list - ilm_dlm_num)); + + bin_map[list].SRAM_addr = byte_to_word(&fwdata[pos]); + bin_map[list].size = byte_to_word(&fwdata[pos + 4]); + bin_map[list].BIN_addr = byte_to_word(&fwdata[pos + 8]); + if (ts->hw_crc) + bin_map[list].crc = + byte_to_word(&fwdata[pos + 12]); + else { + if ((bin_map[list].BIN_addr + + bin_map[list].size) < fwsize) + bin_map[list].crc = CheckSum( + &fwdata[bin_map[list].BIN_addr], + bin_map[list].size); + else { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + + bin_map[list].size); + return -EINVAL; + } + } + /* detect header end to protect parser function */ + if ((bin_map[list].BIN_addr == 0) && + (bin_map[list].size != 0)) { + sprintf(bin_map[list].name, "Header"); + } else { + sprintf(bin_map[list].name, "Info-%d", + (list - ilm_dlm_num)); + } + } + + /* + * [3] parsing overlay section header info + * SRAM_addr : size : BIN_addr : crc (16-bytes) + */ + if (list >= (ilm_dlm_num + info_sec_num)) { + /* overlay info located at DLM (list = 1) start addr */ + pos = bin_map[1].BIN_addr + + (0x10 * (list - ilm_dlm_num - info_sec_num)); + + bin_map[list].SRAM_addr = byte_to_word(&fwdata[pos]); + bin_map[list].size = byte_to_word(&fwdata[pos + 4]); + bin_map[list].BIN_addr = byte_to_word(&fwdata[pos + 8]); + if (ts->hw_crc) + bin_map[list].crc = + byte_to_word(&fwdata[pos + 12]); + else { + if ((bin_map[list].BIN_addr + + bin_map[list].size) < fwsize) + bin_map[list].crc = CheckSum( + &fwdata[bin_map[list].BIN_addr], + bin_map[list].size); + else { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + + bin_map[list].size); + return -EINVAL; + } + } + sprintf(bin_map[list].name, "Overlay-%d", + (list - ilm_dlm_num - info_sec_num)); + } + + /* BIN size error detect */ + if ((bin_map[list].BIN_addr + bin_map[list].size) > fwsize) { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + bin_map[list].BIN_addr, + bin_map[list].BIN_addr + bin_map[list].size); + return -EINVAL; + } + + /* NVT_LOG("[%d][%s] SRAM (0x%08X), SIZE (0x%08X), BIN (0x%08X), CRC (0x%08X)\n", + list, bin_map[list].name, + bin_map[list].SRAM_addr, bin_map[list].size, bin_map[list].BIN_addr, bin_map[list].crc); */ + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen release update firmware function. + +return: + n.a. +*******************************************************/ +static void update_firmware_release(void) +{ + if (fw_entry) { + release_firmware(fw_entry); + } + + fw_entry = NULL; +} + +/******************************************************* +Description: + Novatek touchscreen request update firmware function. + +return: + Executive outcomes. 0---succeed. -1,-22---failed. +*******************************************************/ +static int32_t update_firmware_request(const char *filename) +{ + uint8_t retry = 0; + int32_t ret = 0; + + if (NULL == filename) { + return -ENOENT; + } + + while (1) { + NVT_LOG("filename is %s\n", filename); + + ret = request_firmware(&fw_entry, filename, &ts->client->dev); + if (ret) { + NVT_ERR("firmware load failed, ret=%d\n", ret); + goto request_fail; + } + + /* check FW need to write size */ + if (nvt_get_fw_need_write_size(fw_entry)) { + NVT_ERR("get fw need to write size fail!\n"); + ret = -EINVAL; + goto invalid; + } + + /* check if FW version add FW version bar equals 0xFF */ + if (*(fw_entry->data + FW_BIN_VER_OFFSET) + + *(fw_entry->data + FW_BIN_VER_BAR_OFFSET) != + 0xFF) { + NVT_ERR("bin file FW_VER + FW_VER_BAR should be 0xFF!\n"); + NVT_ERR("FW_VER=0x%02X, FW_VER_BAR=0x%02X\n", + *(fw_entry->data + FW_BIN_VER_OFFSET), + *(fw_entry->data + FW_BIN_VER_BAR_OFFSET)); + ret = -ENOEXEC; + goto invalid; + } + + /* BIN Header Parser */ + ret = nvt_bin_header_parser(fw_entry->data, fw_entry->size); + if (ret) { + NVT_ERR("bin header parser failed\n"); + goto invalid; + } else { + break; + } + +invalid: + update_firmware_release(); + if (!IS_ERR_OR_NULL(bin_map)) { + kfree(bin_map); + bin_map = NULL; + } + +request_fail: + retry++; + if (unlikely(retry > 2)) { + NVT_ERR("error, retry=%d\n", retry); + break; + } + } + + return ret; +} + +#if NVT_DUMP_PARTITION +/******************************************************* +Description: + Novatek touchscreen dump flash partition function. + +return: + n.a. +*******************************************************/ +loff_t file_offset = 0; +static int32_t nvt_read_ram_and_save_file(uint32_t addr, uint16_t len, + char *name) +{ + char file[256] = ""; + uint8_t *fbufp = NULL; + int32_t ret = 0; + struct file *fp = NULL; + mm_segment_t org_fs; + + sprintf(file, "%s/dump_%s.bin", NVT_DUMP_PARTITION_PATH, name); + NVT_LOG("Dump [%s] from 0x%08X to 0x%08X\n", file, addr, addr + len); + + fbufp = (uint8_t *)kzalloc(len + 1, GFP_KERNEL); + if (fbufp == NULL) { + NVT_ERR("kzalloc for fbufp failed!\n"); + ret = -ENOMEM; + goto alloc_buf_fail; + } + + org_fs = get_fs(); + set_fs(KERNEL_DS); + fp = filp_open(file, O_RDWR | O_CREAT, 0644); + if (fp == NULL || IS_ERR(fp)) { + ret = -ENOMEM; + NVT_ERR("open file failed\n"); + goto open_file_fail; + } + + /* SPI read */ + /* ---set xdata index to addr--- */ + nvt_set_page(addr); + + fbufp[0] = addr & 0x7F; + CTP_SPI_READ(ts->client, fbufp, len + 1); + + /* Write to file */ + ret = vfs_write(fp, (char __user *)fbufp + 1, len, &file_offset); + if (ret != len) { + NVT_ERR("write file failed\n"); + goto open_file_fail; + } else { + ret = 0; + } + +open_file_fail: + set_fs(org_fs); + if (!IS_ERR_OR_NULL(fp)) { + filp_close(fp, NULL); + fp = NULL; + } + + if (!IS_ERR_OR_NULL(fbufp)) { + kfree(fbufp); + fbufp = NULL; + } +alloc_buf_fail: + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen nvt_dump_partition function to dump + each partition for debug. + +return: + n.a. +*******************************************************/ +static int32_t nvt_dump_partition(void) +{ + uint32_t list = 0; + char *name; + uint32_t SRAM_addr, size; + uint32_t i = 0; + uint16_t len = 0; + int32_t count = 0; + int32_t ret = 0; + + if (NVT_DUMP_PARTITION_LEN >= sizeof(ts->rbuf)) { + NVT_ERR("dump len %d is larger than buffer size %ld\n", + NVT_DUMP_PARTITION_LEN, sizeof(ts->rbuf)); + return -EINVAL; + } else if (NVT_DUMP_PARTITION_LEN >= NVT_TRANSFER_LEN) { + NVT_ERR("dump len %d is larger than NVT_TRANSFER_LEN\n", + NVT_DUMP_PARTITION_LEN); + return -EINVAL; + } + + if (bin_map == NULL) { + NVT_ERR("bin_map is NULL\n"); + return -ENOMEM; + } + + memset(fwbuf, 0, (NVT_DUMP_PARTITION_LEN + 1)); + + for (list = 0; list < partition; list++) { + /* initialize variable */ + SRAM_addr = bin_map[list].SRAM_addr; + size = bin_map[list].size; + name = bin_map[list].name; + + /* ignore reserved partition (Reserved Partition size is zero) */ + if (!size) + continue; + else + size = size + 1; + + /* write data to SRAM */ + if (size % NVT_DUMP_PARTITION_LEN) + count = (size / NVT_DUMP_PARTITION_LEN) + 1; + else + count = (size / NVT_DUMP_PARTITION_LEN); + + for (i = 0; i < count; i++) { + len = (size < NVT_DUMP_PARTITION_LEN) ? + size : + NVT_DUMP_PARTITION_LEN; + + /* dump for debug download firmware */ + ret = nvt_read_ram_and_save_file(SRAM_addr, len, name); + if (ret < 0) { + NVT_ERR("nvt_read_ram_and_save_file failed, ret = %d\n", + ret); + goto out; + } + + SRAM_addr += NVT_DUMP_PARTITION_LEN; + size -= NVT_DUMP_PARTITION_LEN; + } + + file_offset = 0; + } + +out: + return ret; +} +#endif /* NVT_DUMP_PARTITION */ + +/******************************************************* +Description: + Novatek touchscreen write data to sram function. + +- fwdata : The buffer is written +- SRAM_addr: The sram destination address +- size : Number of data bytes in @fwdata being written +- BIN_addr : The transferred data offset of @fwdata + +return: + Executive outcomes. 0---succeed. else---fail. +*******************************************************/ +static int32_t nvt_write_sram(const u8 *fwdata, uint32_t SRAM_addr, + uint32_t size, uint32_t BIN_addr) +{ + int32_t ret = 0; + uint32_t i = 0; + uint16_t len = 0; + int32_t count = 0; + + if (size % NVT_TRANSFER_LEN) + count = (size / NVT_TRANSFER_LEN) + 1; + else + count = (size / NVT_TRANSFER_LEN); + + for (i = 0; i < count; i++) { + len = (size < NVT_TRANSFER_LEN) ? size : NVT_TRANSFER_LEN; + + /* ---set xdata index to start address of SRAM--- */ + ret = nvt_set_page(SRAM_addr); + if (ret) { + NVT_ERR("set page failed, ret = %d\n", ret); + return ret; + } + + /* ---write data into SRAM--- */ + fwbuf[0] = SRAM_addr & 0x7F; + memcpy(fwbuf + 1, &fwdata[BIN_addr], len); + ret = CTP_SPI_WRITE(ts->client, fwbuf, len + 1); + if (ret) { + NVT_ERR("write to sram failed, ret = %d\n", ret); + return ret; + } + + SRAM_addr += NVT_TRANSFER_LEN; + BIN_addr += NVT_TRANSFER_LEN; + size -= NVT_TRANSFER_LEN; + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen nvt_write_firmware function to write +firmware into each partition. + +return: + n.a. +*******************************************************/ +static int32_t nvt_write_firmware(const u8 *fwdata, size_t fwsize) +{ + uint32_t list = 0; + char *name; + uint32_t BIN_addr, SRAM_addr, size; + int32_t ret = 0; + + memset(fwbuf, 0, (NVT_TRANSFER_LEN + 1)); + + for (list = 0; list < partition; list++) { + /* initialize variable */ + SRAM_addr = bin_map[list].SRAM_addr; + size = bin_map[list].size; + BIN_addr = bin_map[list].BIN_addr; + name = bin_map[list].name; + + /* NVT_LOG("[%d][%s] SRAM (0x%08X), SIZE (0x%08X), BIN (0x%08X)\n", + list, name, SRAM_addr, size, BIN_addr); */ + + /* Check data size */ + if ((BIN_addr + size) > fwsize) { + NVT_ERR("access range (0x%08X to 0x%08X) is larger than bin size!\n", + BIN_addr, BIN_addr + size); + ret = -EINVAL; + goto out; + } + + /* ignore reserved partition (Reserved Partition size is zero) */ + if (!size) + continue; + else + size = size + 1; + + /* write data to SRAM */ + ret = nvt_write_sram(fwdata, SRAM_addr, size, BIN_addr); + if (ret) { + NVT_ERR("sram program failed, ret = %d\n", ret); + goto out; + } + } + +out: + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen check checksum function. +This function will compare file checksum and fw checksum. + +return: + n.a. +*******************************************************/ +static int32_t nvt_check_fw_checksum(void) +{ + uint32_t fw_checksum = 0; + uint32_t len = partition * 4; + uint32_t list = 0; + int32_t ret = 0; + + memset(fwbuf, 0, (len + 1)); + + /* ---set xdata index to checksum--- */ + nvt_set_page(ts->mmap->R_ILM_CHECKSUM_ADDR); + + /* read checksum */ + fwbuf[0] = (ts->mmap->R_ILM_CHECKSUM_ADDR) & 0x7F; + ret = CTP_SPI_READ(ts->client, fwbuf, len + 1); + if (ret) { + NVT_ERR("Read fw checksum failed\n"); + return ret; + } + + /* + * Compare each checksum from fw + * ILM + DLM + Overlay + Info + * ilm_dlm_num (ILM & DLM) + ovly_sec_num + info_sec_num + */ + for (list = 0; list < partition; list++) { + fw_checksum = byte_to_word(&fwbuf[1 + list * 4]); + + /* ignore reserved partition (Reserved Partition size is zero) */ + if (!bin_map[list].size) + continue; + + if (bin_map[list].crc != fw_checksum) { + NVT_ERR("[%d] BIN_checksum=0x%08X, FW_checksum=0x%08X\n", + list, bin_map[list].crc, fw_checksum); + ret = -EIO; + } + } + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen set bootload crc reg bank function. +This function will set hw crc reg before enable crc function. + +return: + n.a. +*******************************************************/ +static void nvt_set_bld_crc_bank(uint32_t DES_ADDR, uint32_t SRAM_ADDR, + uint32_t LENGTH_ADDR, uint32_t size, + uint32_t G_CHECKSUM_ADDR, uint32_t crc) +{ + /* write destination address */ + nvt_set_page(DES_ADDR); + fwbuf[0] = DES_ADDR & 0x7F; + fwbuf[1] = (SRAM_ADDR) & 0xFF; + fwbuf[2] = (SRAM_ADDR >> 8) & 0xFF; + fwbuf[3] = (SRAM_ADDR >> 16) & 0xFF; + CTP_SPI_WRITE(ts->client, fwbuf, 4); + + /* write length */ + /* nvt_set_page(LENGTH_ADDR); */ + fwbuf[0] = LENGTH_ADDR & 0x7F; + fwbuf[1] = (size) & 0xFF; + fwbuf[2] = (size >> 8) & 0xFF; + fwbuf[3] = (size >> 16) & 0x01; + if (ts->hw_crc == 1) { + CTP_SPI_WRITE(ts->client, fwbuf, 3); + } else if (ts->hw_crc > 1) { + CTP_SPI_WRITE(ts->client, fwbuf, 4); + } + + /* write golden dlm checksum */ + /* nvt_set_page(G_CHECKSUM_ADDR); */ + fwbuf[0] = G_CHECKSUM_ADDR & 0x7F; + fwbuf[1] = (crc) & 0xFF; + fwbuf[2] = (crc >> 8) & 0xFF; + fwbuf[3] = (crc >> 16) & 0xFF; + fwbuf[4] = (crc >> 24) & 0xFF; + CTP_SPI_WRITE(ts->client, fwbuf, 5); + + return; +} + +/******************************************************* +Description: + Novatek touchscreen set BLD hw crc function. +This function will set ILM and DLM crc information to register. + +return: + n.a. +*******************************************************/ +static void nvt_set_bld_hw_crc(void) +{ + /* [0] ILM */ + /* write register bank */ + nvt_set_bld_crc_bank(ts->mmap->ILM_DES_ADDR, bin_map[0].SRAM_addr, + ts->mmap->ILM_LENGTH_ADDR, bin_map[0].size, + ts->mmap->G_ILM_CHECKSUM_ADDR, bin_map[0].crc); + + /* [1] DLM */ + /* write register bank */ + nvt_set_bld_crc_bank(ts->mmap->DLM_DES_ADDR, bin_map[1].SRAM_addr, + ts->mmap->DLM_LENGTH_ADDR, bin_map[1].size, + ts->mmap->G_DLM_CHECKSUM_ADDR, bin_map[1].crc); +} + +/******************************************************* +Description: + Novatek touchscreen read BLD hw crc info function. +This function will check crc results from register. + +return: + n.a. +*******************************************************/ +static void nvt_read_bld_hw_crc(void) +{ + uint8_t buf[8] = { 0 }; + uint32_t g_crc = 0, r_crc = 0; + + /* CRC Flag */ + nvt_set_page(ts->mmap->BLD_ILM_DLM_CRC_ADDR); + buf[0] = ts->mmap->BLD_ILM_DLM_CRC_ADDR & 0x7F; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + NVT_ERR("crc_done = %d, ilm_crc_flag = %d, dlm_crc_flag = %d\n", + (buf[1] >> 2) & 0x01, (buf[1] >> 0) & 0x01, + (buf[1] >> 1) & 0x01); + + /* ILM CRC */ + nvt_set_page(ts->mmap->G_ILM_CHECKSUM_ADDR); + buf[0] = ts->mmap->G_ILM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + g_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + nvt_set_page(ts->mmap->R_ILM_CHECKSUM_ADDR); + buf[0] = ts->mmap->R_ILM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + r_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + NVT_ERR("ilm: bin crc = 0x%08X, golden = 0x%08X, result = 0x%08X\n", + bin_map[0].crc, g_crc, r_crc); + + /* DLM CRC */ + nvt_set_page(ts->mmap->G_DLM_CHECKSUM_ADDR); + buf[0] = ts->mmap->G_DLM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + g_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + nvt_set_page(ts->mmap->R_DLM_CHECKSUM_ADDR); + buf[0] = ts->mmap->R_DLM_CHECKSUM_ADDR & 0x7F; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + CTP_SPI_READ(ts->client, buf, 5); + r_crc = buf[1] | (buf[2] << 8) | (buf[3] << 16) | (buf[4] << 24); + + NVT_ERR("dlm: bin crc = 0x%08X, golden = 0x%08X, result = 0x%08X\n", + bin_map[1].crc, g_crc, r_crc); + + return; +} + +#if NVT_TOUCH_ESD_DISP_RECOVERY +#define ILM_CRC_FLAG 0x01 +#define CRC_DONE 0x04 +static int32_t nvt_check_crc_done_ilm_err(void) +{ + uint8_t buf[8] = { 0 }; + + nvt_set_page(ts->mmap->BLD_ILM_DLM_CRC_ADDR); + buf[0] = ts->mmap->BLD_ILM_DLM_CRC_ADDR & 0x7F; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + + NVT_LOG("CRC DONE, ILM DLM FLAG = 0x%02X\n", buf[1]); + if (((buf[1] & ILM_CRC_FLAG) && (buf[1] & CRC_DONE)) || + (buf[1] == 0xFE) || ((buf[1] & CRC_DONE) == 0x00)) + return 1; + else + return 0; +} + +#define DISP_OFF_ADDR 0x2800 +static int nvt_f2c_disp_off(void) +{ + uint8_t buf[8] = { 0 }; + int ret = 0; + uint8_t tmp_val = 0; + int32_t write_disp_off_retry = 0; + int32_t retry = 0; + + NVT_LOG("%s ++\n", __func__); + + /* SW Reset & Idle */ + nvt_sw_reset_idle(); + + /* Setp1: Set REG CPU_IF_ADDR[15:0] */ + nvt_write_addr(ts->mmap->CPU_IF_ADDR_LOW, DISP_OFF_ADDR & 0xFF); + nvt_write_addr(ts->mmap->CPU_IF_ADDR_HIGH, (DISP_OFF_ADDR >> 8) & 0xFF); + + /* Step2: Set REG FFM_ADDR[15:0] */ + /* set FFM_ADDR to 0x20000 */ + nvt_write_addr(ts->mmap->FFM_ADDR_LOW, 0x00); + nvt_write_addr(ts->mmap->FFM_ADDR_MID, 0x00); + if (ts->hw_crc > 1) + nvt_write_addr(ts->mmap->FFM_ADDR_HIGH, 0x00); + + /* Step3: Set REG F2C_LENGT[H7:0] */ + nvt_write_addr(ts->mmap->F2C_LENGTH, 1); + +nvt_write_disp_off_retry: + /* Step4: Set REG CPU_Polling_En=1, F2C_RW=1, CPU_IF_ADDR_INC=1, F2C_EN=1 */ + nvt_set_page(ts->mmap->FFM2CPU_CTL); + buf[0] = ts->mmap->FFM2CPU_CTL & 0x7F; + buf[1] = 0xFF; + ret = CTP_SPI_READ(ts->client, buf, 2); + if (ret) { + NVT_ERR("Read FFM2CPU control failed!\n"); + return ret; + } + tmp_val = buf[1] | 0x27; + nvt_write_addr(ts->mmap->FFM2CPU_CTL, tmp_val); + + /* Step5: wait F2C_EN = 0 */ + retry = 0; + while (1) { + nvt_set_page(ts->mmap->FFM2CPU_CTL); + buf[0] = ts->mmap->FFM2CPU_CTL & 0x7F; + buf[1] = 0xFF; + buf[2] = 0xFF; + ret = CTP_SPI_READ(ts->client, buf, 3); + if (ret) { + NVT_ERR("Read FFM2CPU control failed!\n"); + return ret; + } + + if ((buf[1] & 0x01) == 0x00) + break; + + usleep_range(1000, 1000); + retry++; + + if (unlikely(retry > 1)) { + NVT_ERR("Wait F2C_EN = 0 failed!\n"); + return -EIO; + } + } + + /* Step6: Check REG TH_CPU_CHK status (1: Success, 0: Fail), if 0, can Retry Step4. */ + if (((buf[2] & 0x04) >> 2) != 0x01) { + write_disp_off_retry++; + if (write_disp_off_retry <= 3) { + goto nvt_write_disp_off_retry; + } else { + NVT_ERR("Write display off failed!, buf[1]=0x%02X, buf[2]=0x%02X\n", + buf[1], buf[2]); + return -EIO; + } + } + NVT_LOG("%s --\n", __func__); + + return ret; +} +#endif /* #if NVT_TOUCH_ESD_DISP_RECOVERY */ + +/******************************************************* +Description: + Novatek touchscreen Download_Firmware with HW CRC +function. It's complete download firmware flow. + +return: + Executive outcomes. 0---succeed. else---fail. +*******************************************************/ +static int32_t nvt_download_firmware_hw_crc(void) +{ + uint8_t retry = 0; + int32_t ret = 0; + + do_gettimeofday(&start); + + while (1) { + /* bootloader reset to reset MCU */ + nvt_bootloader_reset(); + + /* Start to write firmware process */ + ret = nvt_write_firmware(fw_entry->data, fw_entry->size); + if (ret) { + NVT_ERR("Write_Firmware failed. (%d)\n", ret); + goto fail; + } + +#if NVT_DUMP_PARTITION + ret = nvt_dump_partition(); + if (ret) { + NVT_ERR("nvt_dump_partition failed, ret = %d\n", ret); + } +#endif + + /* set ilm & dlm reg bank */ + nvt_set_bld_hw_crc(); + + /* enable hw bld crc function */ + nvt_bld_crc_enable(); + + /* clear fw reset status & enable fw crc check */ + nvt_fw_crc_enable(); + + /* Set Boot Ready Bit */ + nvt_boot_ready(); + + ret = nvt_check_fw_reset_state(RESET_STATE_INIT); + if (ret) { + NVT_ERR("nvt_check_fw_reset_state failed. (%d)\n", ret); + goto fail; + } else { + break; + } + +fail: + retry++; + if (unlikely(retry > 2)) { + NVT_ERR("error, retry=%d\n", retry); + nvt_read_bld_hw_crc(); +#if NVT_TOUCH_ESD_DISP_RECOVERY + if (nvt_check_crc_done_ilm_err()) { + NVT_ERR("set display off to trigger display esd recovery.\n"); + nvt_f2c_disp_off(); + } +#endif /* #if NVT_TOUCH_ESD_DISP_RECOVERY */ + break; + } + } + + do_gettimeofday(&end); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen Download_Firmware function. It's +complete download firmware flow. + +return: + n.a. +*******************************************************/ +static int32_t nvt_download_firmware(void) +{ + uint8_t retry = 0; + int32_t ret = 0; + + do_gettimeofday(&start); + + while (1) { + /* + * Send eng reset cmd before download FW + * Keep TP_RESX low when send eng reset cmd + */ +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 0); + mdelay(1); +#endif + nvt_eng_reset(); +#if NVT_TOUCH_SUPPORT_HW_RST + gpio_set_value(ts->reset_gpio, 1); + mdelay(10); +#endif + nvt_bootloader_reset(); + + /* clear fw reset status */ + nvt_write_addr(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_RESET_COMPLETE, + 0x00); + + /* Start to write firmware process */ + ret = nvt_write_firmware(fw_entry->data, fw_entry->size); + if (ret) { + NVT_ERR("Write_Firmware failed. (%d)\n", ret); + goto fail; + } + +#if NVT_DUMP_PARTITION + ret = nvt_dump_partition(); + if (ret) { + NVT_ERR("nvt_dump_partition failed, ret = %d\n", ret); + } +#endif + + /* Set Boot Ready Bit */ + nvt_boot_ready(); + + ret = nvt_check_fw_reset_state(RESET_STATE_INIT); + if (ret) { + NVT_ERR("nvt_check_fw_reset_state failed. (%d)\n", ret); + goto fail; + } + + /* check fw checksum result */ + ret = nvt_check_fw_checksum(); + if (ret) { + NVT_ERR("firmware checksum not match, retry=%d\n", + retry); + goto fail; + } else { + break; + } + +fail: + retry++; + if (unlikely(retry > 2)) { + NVT_ERR("error, retry=%d\n", retry); + break; + } + } + + do_gettimeofday(&end); + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen update firmware main function. + +return: + n.a. +*******************************************************/ +int32_t nvt_update_firmware(const char *firmware_name) +{ + int32_t ret = 0; + + /* request bin file in "/etc/firmware" */ + ret = update_firmware_request(firmware_name); + if (ret) { + NVT_ERR("update_firmware_request failed. (%d)\n", ret); + goto request_firmware_fail; + } + + /* initial buffer and variable */ + ret = nvt_download_init(); + if (ret) { + NVT_ERR("Download Init failed. (%d)\n", ret); + goto download_fail; + } + + /* download firmware process */ + if (ts->hw_crc) + ret = nvt_download_firmware_hw_crc(); + else + ret = nvt_download_firmware(); + if (ret) { + NVT_ERR("Download Firmware failed. (%d)\n", ret); + goto download_fail; + } + + NVT_LOG("Update firmware success! <%ld us>\n", + (end.tv_sec - start.tv_sec) * 1000000L + + (end.tv_usec - start.tv_usec)); + + /* Get FW Info */ + ret = nvt_get_fw_info(); + if (ret) { + NVT_ERR("nvt_get_fw_info failed. (%d)\n", ret); + } + +download_fail: + if (!IS_ERR_OR_NULL(bin_map)) { + kfree(bin_map); + bin_map = NULL; + } + + update_firmware_release(); +request_firmware_fail: + + return ret; +} + +/******************************************************* +Description: + Novatek touchscreen update firmware when booting + function. + +return: + n.a. +*******************************************************/ +void Boot_Update_Firmware(struct work_struct *work) +{ + nvt_match_fw(); + mutex_lock(&ts->lock); + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + nvt_get_fw_info(); + mutex_unlock(&ts->lock); + pm_relax(&ts->pdev->dev); +} +#endif /* BOOT_UPDATE_FIRMWARE */ diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mem_map.h b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mem_map.h new file mode 100644 index 000000000000..57643b2f89a3 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mem_map.h @@ -0,0 +1,358 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * + * $Revision: 32206 $ + * $Date: 2018-08-10 19:23:04 +0800 (週五, 10 八月 2018) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +struct nvt_ts_mem_map { + uint32_t EVENT_BUF_ADDR; + uint32_t RAW_PIPE0_ADDR; + uint32_t RAW_PIPE1_ADDR; + uint32_t BASELINE_ADDR; + uint32_t BASELINE_BTN_ADDR; + uint32_t DIFF_PIPE0_ADDR; + uint32_t DIFF_PIPE1_ADDR; + uint32_t RAW_BTN_PIPE0_ADDR; + uint32_t RAW_BTN_PIPE1_ADDR; + uint32_t DIFF_BTN_PIPE0_ADDR; + uint32_t DIFF_BTN_PIPE1_ADDR; + uint32_t READ_FLASH_CHECKSUM_ADDR; + uint32_t RW_FLASH_DATA_ADDR; + /* Phase 2 Host Download */ + uint32_t BOOT_RDY_ADDR; + uint32_t POR_CD_ADDR; + /* BLD CRC */ + uint32_t BLD_LENGTH_ADDR; + uint32_t ILM_LENGTH_ADDR; + uint32_t DLM_LENGTH_ADDR; + uint32_t BLD_DES_ADDR; + uint32_t ILM_DES_ADDR; + uint32_t DLM_DES_ADDR; + uint32_t G_ILM_CHECKSUM_ADDR; + uint32_t G_DLM_CHECKSUM_ADDR; + uint32_t R_ILM_CHECKSUM_ADDR; + uint32_t R_DLM_CHECKSUM_ADDR; + uint32_t BLD_CRC_EN_ADDR; + uint32_t DMA_CRC_EN_ADDR; + uint32_t BLD_ILM_DLM_CRC_ADDR; + uint32_t DMA_CRC_FLAG_ADDR; + uint32_t FFM2CPU_CTL; + uint32_t F2C_LENGTH; + uint32_t CPU_IF_ADDR_LOW; + uint32_t CPU_IF_ADDR_HIGH; + uint32_t FFM_ADDR_LOW; + uint32_t FFM_ADDR_MID; + uint32_t FFM_ADDR_HIGH; + uint32_t FW_HISTORY_ADDR; +}; + +struct nvt_ts_hw_info { + uint8_t carrier_system; + uint8_t hw_crc; +}; + +static const struct nvt_ts_mem_map NT36675_memory_map = { + .EVENT_BUF_ADDR = 0x22D00, + .RAW_PIPE0_ADDR = 0x24000, + .RAW_PIPE1_ADDR = 0x24000, + .BASELINE_ADDR = 0x21B90, + .BASELINE_BTN_ADDR = 0, + .DIFF_PIPE0_ADDR = 0x20C60, + .DIFF_PIPE1_ADDR = 0x24C60, + .RAW_BTN_PIPE0_ADDR = 0, + .RAW_BTN_PIPE1_ADDR = 0, + .DIFF_BTN_PIPE0_ADDR = 0, + .DIFF_BTN_PIPE1_ADDR = 0, + .READ_FLASH_CHECKSUM_ADDR = 0x24000, + .RW_FLASH_DATA_ADDR = 0x24002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ + .BLD_LENGTH_ADDR = 0x3F138, //0x3F138 ~ 0x3F13A (3 bytes) + .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F11A (3 bytes) + .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F132 (3 bytes) + .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) + .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) + .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) + .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) + .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F136, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, + .FFM2CPU_CTL = 0x3F280, + .F2C_LENGTH = 0x3F283, + .CPU_IF_ADDR_LOW = 0x3F284, + .CPU_IF_ADDR_HIGH = 0x3F285, + .FFM_ADDR_LOW = 0x3F286, + .FFM_ADDR_MID = 0x3F287, + .FFM_ADDR_HIGH = 0x3F288, + .FW_HISTORY_ADDR = 0x23D10, +}; + +static const struct nvt_ts_mem_map NT36672A_memory_map = { + .EVENT_BUF_ADDR = 0x21C00, + .RAW_PIPE0_ADDR = 0x20000, + .RAW_PIPE1_ADDR = 0x23000, + .BASELINE_ADDR = 0x20BFC, + .BASELINE_BTN_ADDR = 0x23BFC, + .DIFF_PIPE0_ADDR = 0x206DC, + .DIFF_PIPE1_ADDR = 0x236DC, + .RAW_BTN_PIPE0_ADDR = 0x20510, + .RAW_BTN_PIPE1_ADDR = 0x23510, + .DIFF_BTN_PIPE0_ADDR = 0x20BF0, + .DIFF_BTN_PIPE1_ADDR = 0x23BF0, + .READ_FLASH_CHECKSUM_ADDR = 0x24000, + .RW_FLASH_DATA_ADDR = 0x24002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x3F10D, + /* BLD CRC */ + .BLD_LENGTH_ADDR = 0x3F10E, //0x3F10E ~ 0x3F10F (2 bytes) + .ILM_LENGTH_ADDR = 0x3F118, //0x3F118 ~ 0x3F119 (2 bytes) + .DLM_LENGTH_ADDR = 0x3F130, //0x3F130 ~ 0x3F131 (2 bytes) + .BLD_DES_ADDR = 0x3F114, //0x3F114 ~ 0x3F116 (3 bytes) + .ILM_DES_ADDR = 0x3F128, //0x3F128 ~ 0x3F12A (3 bytes) + .DLM_DES_ADDR = 0x3F12C, //0x3F12C ~ 0x3F12E (3 bytes) + .G_ILM_CHECKSUM_ADDR = 0x3F100, //0x3F100 ~ 0x3F103 (4 bytes) + .G_DLM_CHECKSUM_ADDR = 0x3F104, //0x3F104 ~ 0x3F107 (4 bytes) + .R_ILM_CHECKSUM_ADDR = 0x3F120, //0x3F120 ~ 0x3F123 (4 bytes) + .R_DLM_CHECKSUM_ADDR = 0x3F124, //0x3F124 ~ 0x3F127 (4 bytes) + .BLD_CRC_EN_ADDR = 0x3F30E, + .DMA_CRC_EN_ADDR = 0x3F132, + .BLD_ILM_DLM_CRC_ADDR = 0x3F133, + .DMA_CRC_FLAG_ADDR = 0x3F134, +}; + +static const struct nvt_ts_mem_map NT36772_memory_map = { + .EVENT_BUF_ADDR = 0x11E00, + .RAW_PIPE0_ADDR = 0x10000, + .RAW_PIPE1_ADDR = 0x12000, + .BASELINE_ADDR = 0x10E70, + .BASELINE_BTN_ADDR = 0x12E70, + .DIFF_PIPE0_ADDR = 0x10830, + .DIFF_PIPE1_ADDR = 0x12830, + .RAW_BTN_PIPE0_ADDR = 0x10E60, + .RAW_BTN_PIPE1_ADDR = 0x12E60, + .DIFF_BTN_PIPE0_ADDR = 0x10E68, + .DIFF_BTN_PIPE1_ADDR = 0x12E68, + .READ_FLASH_CHECKSUM_ADDR = 0x14000, + .RW_FLASH_DATA_ADDR = 0x14002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x1F141, + .POR_CD_ADDR = 0x1F61C, + /* BLD CRC */ + .R_ILM_CHECKSUM_ADDR = 0x1BF00, +}; + +static const struct nvt_ts_mem_map NT36525_memory_map = { + .EVENT_BUF_ADDR = 0x11A00, + .RAW_PIPE0_ADDR = 0x10000, + .RAW_PIPE1_ADDR = 0x12000, + .BASELINE_ADDR = 0x10B08, + .BASELINE_BTN_ADDR = 0x12B08, + .DIFF_PIPE0_ADDR = 0x1064C, + .DIFF_PIPE1_ADDR = 0x1264C, + .RAW_BTN_PIPE0_ADDR = 0x10634, + .RAW_BTN_PIPE1_ADDR = 0x12634, + .DIFF_BTN_PIPE0_ADDR = 0x10AFC, + .DIFF_BTN_PIPE1_ADDR = 0x12AFC, + .READ_FLASH_CHECKSUM_ADDR = 0x14000, + .RW_FLASH_DATA_ADDR = 0x14002, + /* Phase 2 Host Download */ + .BOOT_RDY_ADDR = 0x1F141, + .POR_CD_ADDR = 0x1F61C, + /* BLD CRC */ + .R_ILM_CHECKSUM_ADDR = 0x1BF00, +}; + +static const struct nvt_ts_mem_map NT36676F_memory_map = { + .EVENT_BUF_ADDR = 0x11A00, + .RAW_PIPE0_ADDR = 0x10000, + .RAW_PIPE1_ADDR = 0x12000, + .BASELINE_ADDR = 0x10B08, + .BASELINE_BTN_ADDR = 0x12B08, + .DIFF_PIPE0_ADDR = 0x1064C, + .DIFF_PIPE1_ADDR = 0x1264C, + .RAW_BTN_PIPE0_ADDR = 0x10634, + .RAW_BTN_PIPE1_ADDR = 0x12634, + .DIFF_BTN_PIPE0_ADDR = 0x10AFC, + .DIFF_BTN_PIPE1_ADDR = 0x12AFC, + .READ_FLASH_CHECKSUM_ADDR = 0x14000, + .RW_FLASH_DATA_ADDR = 0x14002, +}; + +static struct nvt_ts_hw_info NT36675_hw_info = { + .carrier_system = 2, + .hw_crc = 2, +}; + +static struct nvt_ts_hw_info NT36672A_hw_info = { + .carrier_system = 0, + .hw_crc = 1, +}; + +static struct nvt_ts_hw_info NT36772_hw_info = { + .carrier_system = 0, + .hw_crc = 0, +}; + +static struct nvt_ts_hw_info NT36525_hw_info = { + .carrier_system = 0, + .hw_crc = 0, +}; + +static struct nvt_ts_hw_info NT36676F_hw_info = { + .carrier_system = 0, + .hw_crc = 0, +}; + +#define NVT_ID_BYTE_MAX 6 +struct nvt_ts_trim_id_table { + uint8_t id[NVT_ID_BYTE_MAX]; + uint8_t mask[NVT_ID_BYTE_MAX]; + const struct nvt_ts_mem_map *mmap; + const struct nvt_ts_hw_info *hwinfo; +}; + +static const struct nvt_ts_trim_id_table trim_id_table[] = { + { + .id = { 0x0C, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36675_memory_map, + .hwinfo = &NT36675_hw_info, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x75, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36675_memory_map, + .hwinfo = &NT36675_hw_info, + }, + { + .id = { 0x0B, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0B, 0xFF, 0xFF, 0x82, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0B, 0xFF, 0xFF, 0x25, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0A, 0xFF, 0xFF, 0x72, 0x65, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0A, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0A, 0xFF, 0xFF, 0x82, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0A, 0xFF, 0xFF, 0x70, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0B, 0xFF, 0xFF, 0x70, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x0A, 0xFF, 0xFF, 0x72, 0x67, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mmap = &NT36672A_memory_map, + .hwinfo = &NT36672A_hw_info, + }, + { + .id = { 0x55, 0x00, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0x55, 0x72, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0xAA, 0x00, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0xAA, 0x72, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x72, 0x67, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x70, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x70, 0x67, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36772_memory_map, + .hwinfo = &NT36772_hw_info, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x25, 0x65, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36525_memory_map, + .hwinfo = &NT36525_hw_info, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x76, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mmap = &NT36676F_memory_map, + .hwinfo = &NT36676F_hw_info, + }, +}; diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.c new file mode 100644 index 000000000000..62e2bf33e9d4 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.c @@ -0,0 +1,2610 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * + * $Revision: 32206 $ + * $Date: 2018-08-10 19:23:04 +0800 (週五, 10 八月 2018) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "nt36xxx.h" +#include "nt36xxx_mp_ctrlram.h" + +#if NVT_TOUCH_MP + +#define NORMAL_MODE 0x00 +#define TEST_MODE_1 0x21 +#define TEST_MODE_2 0x22 +#define MP_MODE_CC 0x41 +#define FREQ_HOP_DISABLE 0x66 +#define FREQ_HOP_ENABLE 0x65 + +#define SHORT_TEST_CSV_FILE "/data/misc/tp_selftest_data/ShortTest.csv" +#define OPEN_TEST_CSV_FILE "/data/misc/tp_selftest_data/OpenTest.csv" +#define FW_RAWDATA_CSV_FILE "/data/misc/tp_selftest_data/FWMutualTest.csv" +#define FW_CC_CSV_FILE "/data/misc/tp_selftest_data/FWCCTest.csv" +#define NOISE_TEST_CSV_FILE "/data/misc/tp_selftest_data/NoiseTest.csv" + +#define nvt_mp_seq_printf(m, fmt, args...) \ + do { \ + seq_printf(m, fmt, ##args); \ + if (!nvt_mp_test_result_printed) \ + printk(fmt, ##args); \ + } while (0) + +#define NVT_RESULT_INVALID 0 +#define NVT_RESULT_PASS 2 +#define NVT_RESULT_FAIL 1 + +static uint8_t *RecordResult_Short = NULL; +static uint8_t *RecordResult_Open = NULL; +static uint8_t *RecordResult_FWMutual = NULL; +static uint8_t *RecordResult_FW_CC = NULL; +static uint8_t *RecordResult_FW_DiffMax = NULL; +static uint8_t *RecordResult_FW_DiffMin = NULL; + +static int32_t TestResult_Short = 0; +static int32_t TestResult_Open = 0; +static int32_t TestResult_FW_Rawdata = 0; +static int32_t TestResult_FWMutual = 0; +static int32_t TestResult_FW_CC = 0; +static int32_t TestResult_Noise = 0; +static int32_t TestResult_FW_DiffMax = 0; +static int32_t TestResult_FW_DiffMin = 0; + +static int32_t *RawData_Short = NULL; +static int32_t *RawData_Open = NULL; +static int32_t *RawData_Diff = NULL; +static int32_t *RawData_Diff_Min = NULL; +static int32_t *RawData_Diff_Max = NULL; +static int32_t *RawData_FWMutual = NULL; +static int32_t *RawData_FW_CC = NULL; + +static struct proc_dir_entry *NVT_proc_selftest_entry = NULL; +static struct proc_dir_entry *NVT_proc_aftersales_test_entry; + +#ifndef NVT_SAVE_TESTDATA_IN_FILE +static struct proc_dir_entry *NVT_proc_test_data_entry = NULL; +#endif + +static int8_t nvt_mp_test_result_printed = 0; +static uint8_t fw_ver = 0; + +extern void nvt_change_mode(uint8_t mode); +extern uint8_t nvt_get_fw_pipe(void); +extern void nvt_read_mdata(uint32_t xdata_addr, uint32_t xdata_btn_addr); +extern void nvt_get_mdata(int32_t *buf, uint8_t *m_x_num, uint8_t *m_y_num); +int32_t nvt_mp_parse_dt(struct device_node *root, const char *node_compatible); + +/******************************************************* +Description: + Novatek touchscreen allocate buffer for mp selftest. + +return: + Executive outcomes. 0---succeed. -12---Out of memory +*******************************************************/ +static int nvt_mp_buffer_init(void) +{ + size_t RecordResult_BufSize = + IC_X_CFG_SIZE * IC_Y_CFG_SIZE + IC_KEY_CFG_SIZE; + size_t RawData_BufSize = + (IC_X_CFG_SIZE * IC_Y_CFG_SIZE + IC_KEY_CFG_SIZE) * + sizeof(int32_t); + + RecordResult_Short = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_Short) { + NVT_ERR("kzalloc for RecordResult_Short failed!\n"); + return -ENOMEM; + } + + RecordResult_Open = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_Open) { + NVT_ERR("kzalloc for RecordResult_Open failed!\n"); + return -ENOMEM; + } + + RecordResult_FWMutual = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FWMutual) { + NVT_ERR("kzalloc for RecordResult_FWMutual failed!\n"); + return -ENOMEM; + } + + RecordResult_FW_CC = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FW_CC) { + NVT_ERR("kzalloc for RecordResult_FW_CC failed!\n"); + return -ENOMEM; + } + + RecordResult_FW_DiffMax = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FW_DiffMax) { + NVT_ERR("kzalloc for RecordResult_FW_DiffMax failed!\n"); + return -ENOMEM; + } + + RecordResult_FW_DiffMin = + (uint8_t *)kzalloc(RecordResult_BufSize, GFP_KERNEL); + if (!RecordResult_FW_DiffMin) { + NVT_ERR("kzalloc for RecordResult_FW_DiffMin failed!\n"); + return -ENOMEM; + } + + RawData_Short = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Short) { + NVT_ERR("kzalloc for RawData_Short failed!\n"); + return -ENOMEM; + } + + RawData_Open = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Open) { + NVT_ERR("kzalloc for RawData_Open failed!\n"); + return -ENOMEM; + } + + RawData_Diff = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Diff) { + NVT_ERR("kzalloc for RawData_Diff failed!\n"); + return -ENOMEM; + } + + RawData_Diff_Min = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Diff_Min) { + NVT_ERR("kzalloc for RawData_Diff_Min failed!\n"); + return -ENOMEM; + } + + RawData_Diff_Max = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_Diff_Max) { + NVT_ERR("kzalloc for RawData_Diff_Max failed!\n"); + return -ENOMEM; + } + + RawData_FWMutual = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_FWMutual) { + NVT_ERR("kzalloc for RawData_FWMutual failed!\n"); + return -ENOMEM; + } + + RawData_FW_CC = (int32_t *)kzalloc(RawData_BufSize, GFP_KERNEL); + if (!RawData_FW_CC) { + NVT_ERR("kzalloc for RawData_FW_CC failed!\n"); + return -ENOMEM; + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen free buffer for mp selftest. + +return: + n.a. +*******************************************************/ +static void nvt_mp_buffer_deinit(void) +{ + if (RecordResult_Short) { + kfree(RecordResult_Short); + RecordResult_Short = NULL; + } + + if (RecordResult_Open) { + kfree(RecordResult_Open); + RecordResult_Open = NULL; + } + + if (RecordResult_FWMutual) { + kfree(RecordResult_FWMutual); + RecordResult_FWMutual = NULL; + } + + if (RecordResult_FW_CC) { + kfree(RecordResult_FW_CC); + RecordResult_FW_CC = NULL; + } + + if (RecordResult_FW_DiffMax) { + kfree(RecordResult_FW_DiffMax); + RecordResult_FW_DiffMax = NULL; + } + + if (RecordResult_FW_DiffMin) { + kfree(RecordResult_FW_DiffMin); + RecordResult_FW_DiffMin = NULL; + } + + if (RawData_Short) { + kfree(RawData_Short); + RawData_Short = NULL; + } + + if (RawData_Open) { + kfree(RawData_Open); + RawData_Open = NULL; + } + + if (RawData_Diff) { + kfree(RawData_Diff); + RawData_Diff = NULL; + } + + if (RawData_Diff_Min) { + kfree(RawData_Diff_Min); + RawData_Diff_Min = NULL; + } + + if (RawData_Diff_Max) { + kfree(RawData_Diff_Max); + RawData_Diff_Max = NULL; + } + + if (RawData_FWMutual) { + kfree(RawData_FWMutual); + RawData_FWMutual = NULL; + } + + if (RawData_FW_CC) { + kfree(RawData_FW_CC); + RawData_FW_CC = NULL; + } +} + +static void nvt_print_data_log_in_one_line(int32_t *data, int32_t data_num) +{ + char *tmp_log = NULL; + int32_t i = 0; + + tmp_log = (char *)kzalloc(data_num * 7 + 1, GFP_KERNEL); + if (!tmp_log) { + NVT_ERR("kzalloc for tmp_log failed!\n "); + return; + } + + for (i = 0; i < data_num; i++) { + sprintf(tmp_log + i * 7, "%5d, ", data[i]); + } + tmp_log[data_num * 7] = '\0'; + NVT_LOG("%s", tmp_log); + if (tmp_log) { + kfree(tmp_log); + tmp_log = NULL; + } + + return; +} + +static void nvt_print_result_log_in_one_line(uint8_t *result, + int32_t result_num) +{ + char *tmp_log = NULL; + int32_t i = 0; + + tmp_log = (char *)kzalloc(result_num * 6 + 1, GFP_KERNEL); + if (!tmp_log) { + NVT_ERR("kzalloc for tmp_log failed!\n "); + return; + } + + for (i = 0; i < result_num; i++) { + sprintf(tmp_log + i * 6, "0x%02X, ", result[i]); + } + tmp_log[result_num * 6] = '\0'; + printk("%s", tmp_log); + if (tmp_log) { + kfree(tmp_log); + tmp_log = NULL; + } + + return; +} + +/******************************************************* +Description: + Novatek touchscreen self-test criteria print function. + +return: + n.a. +*******************************************************/ +static void nvt_print_lmt_array(int32_t *array, int32_t x_ch, int32_t y_ch) +{ + int32_t j = 0; + + for (j = 0; j < y_ch; j++) { + nvt_print_data_log_in_one_line(array + j * x_ch, x_ch); + printk("\n"); + } +} + +static void nvt_print_criteria(void) +{ + NVT_LOG("%s ++\n", __func__); + + /* ---PS_Config_Lmt_Short_Rawdata--- */ + NVT_LOG("PS_Config_Lmt_Short_Rawdata_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Short_Rawdata_P, X_Channel, + Y_Channel); + NVT_LOG("PS_Config_Lmt_Short_Rawdata_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Short_Rawdata_N, X_Channel, + Y_Channel); + + /* ---PS_Config_Lmt_Open_Rawdata--- */ + NVT_LOG("PS_Config_Lmt_Open_Rawdata_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Open_Rawdata_P, X_Channel, Y_Channel); + NVT_LOG("PS_Config_Lmt_Open_Rawdata_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_Open_Rawdata_N, X_Channel, Y_Channel); + + /* ---PS_Config_Lmt_FW_Rawdata--- */ + NVT_LOG("PS_Config_Lmt_FW_Rawdata_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Rawdata_P, X_Channel, Y_Channel); + NVT_LOG("PS_Config_Lmt_FW_Rawdata_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Rawdata_N, X_Channel, Y_Channel); + + /* ---PS_Config_Lmt_FW_CC--- */ + NVT_LOG("PS_Config_Lmt_FW_CC_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_CC_P, X_Channel, Y_Channel); + NVT_LOG("PS_Config_Lmt_FW_CC_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_CC_N, X_Channel, Y_Channel); + + /* ---PS_Config_Lmt_FW_Diff--- */ + NVT_LOG("PS_Config_Lmt_FW_Diff_P:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Diff_P, X_Channel, Y_Channel); + NVT_LOG("PS_Config_Lmt_FW_Diff_N:\n"); + nvt_print_lmt_array(PS_Config_Lmt_FW_Diff_N, X_Channel, Y_Channel); + + NVT_LOG("%s --\n", __func__); +} + +#ifndef NVT_SAVE_TESTDATA_IN_FILE +void dump_buff(int32_t *rawdata, uint8_t x_ch, uint8_t y_ch) +{ + int32_t y = 0; + + for (y = 0; y < y_ch; y++) { + nvt_print_data_log_in_one_line(rawdata + y * x_ch, x_ch); + NVT_LOG("%s:++\n", __func__); + } +} +#endif +static int32_t nvt_save_rawdata_to_csv(int32_t *rawdata, uint8_t x_ch, + uint8_t y_ch, const char *file_path, + uint32_t offset, enum test_type type) +{ +#ifdef NVT_SAVE_TESTDATA_IN_FILE + int32_t x = 0; + int32_t y = 0; + int32_t iArrayIndex = 0; + struct file *fp = NULL; + char *fbufp = NULL; + mm_segment_t org_fs; + int32_t write_ret = 0; + uint32_t output_len = 0; + loff_t pos = 0; +#else /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + struct test_buf *tbuf = ts->testdata; +#endif /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + + NVT_LOG("%s:++\n", __func__); + +#ifdef NVT_SAVE_TESTDATA_IN_FILE + fbufp = (char *)kzalloc(8192, GFP_KERNEL); + if (!fbufp) { + NVT_ERR("kzalloc for fbufp failed!\n"); + return -ENOMEM; + } + + for (y = 0; y < y_ch; y++) { + for (x = 0; x < x_ch; x++) { + iArrayIndex = y * x_ch + x; + sprintf(fbufp + iArrayIndex * 7 + y * 2, "%5d, ", + rawdata[iArrayIndex]); + } + nvt_print_data_log_in_one_line(rawdata + y * x_ch, x_ch); + NVT_LOG("\n"); + sprintf(fbufp + (iArrayIndex + 1) * 7 + y * 2, "\r\n"); + } + + org_fs = get_fs(); + set_fs(KERNEL_DS); + fp = filp_open(file_path, O_RDWR | O_CREAT, 0644); + if (fp == NULL || IS_ERR(fp)) { + NVT_ERR("open %s failed\n", file_path); + set_fs(org_fs); + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } + return -1; + } + + output_len = y_ch * x_ch * 7 + y_ch * 2; + pos = offset; + write_ret = vfs_write(fp, (char __user *)fbufp, output_len, &pos); + if (write_ret <= 0) { + NVT_ERR("write %s failed\n", file_path); + set_fs(org_fs); + if (fp) { + filp_close(fp, NULL); + fp = NULL; + } + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } + return -1; + } + + set_fs(org_fs); + if (fp) { + filp_close(fp, NULL); + fp = NULL; + } + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } +#else /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + switch (type) { + case SHORT_TEST: + NVT_LOG("SHORT_TEST start copy TEST_BUF_LEN = %d", + TEST_BUF_LEN); + memset(tbuf->shorttest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->shorttest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->shorttest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST(%p):=============\n", + tbuf->shorttest.buf); + dump_buff((int32_t *)tbuf->shorttest.buf, x_ch, y_ch); + NVT_LOG("SHORT_TEST copy complete"); + break; + case OPEN_TEST: + NVT_LOG("OPEN_TEST start copy"); + memset(tbuf->opentest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->opentest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->opentest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST(%p):=============\n", + tbuf->opentest.buf); + dump_buff((int32_t *)tbuf->opentest.buf, x_ch, y_ch); + NVT_LOG("OPEN_TEST copy complete"); + break; + case FWMUTUAL_TEST: + NVT_LOG("FWMUTUAL_TEST start copy"); + memset(tbuf->fwmutualtest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->fwmutualtest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->fwmutualtest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->fwmutualtest.buf, x_ch, y_ch); + NVT_LOG("FWMUTUAL_TEST copy complete"); + break; + case FWCC_TEST: + NVT_LOG("FWCC_TEST start copy"); + memset(tbuf->fwcctest.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->fwcctest.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->fwcctest.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->fwcctest.buf, x_ch, y_ch); + NVT_LOG("FWCC_TEST copy complete"); + break; + case NOISE_MAX_TEST: + NVT_LOG("NOISE_MAX_TEST start copy"); + memset(tbuf->noisetest_max.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->noisetest_max.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->noisetest_max.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->noisetest_max.buf, x_ch, y_ch); + NVT_LOG("NOISE_MAX_TEST copy complete"); + break; + case NOISE_MIN_TEST: + NVT_LOG("NOISE_MIN_TEST start copy"); + memset(tbuf->noisetest_min.buf, 0, TEST_BUF_LEN); + memcpy(tbuf->noisetest_min.buf, (uint8_t *)rawdata, + x_ch * y_ch * sizeof(int32_t)); + tbuf->noisetest_min.len = x_ch * y_ch * sizeof(int32_t); + NVT_LOG("===========SRC:=============\n"); + dump_buff(rawdata, x_ch, y_ch); + NVT_LOG("===========DST:=============\n"); + dump_buff((int32_t *)tbuf->noisetest_min.buf, x_ch, y_ch); + NVT_LOG("NOISE_MIN_TEST copy complete"); + break; + default: + NVT_ERR("test type is illegal"); + break; + } +#endif /*#ifdef NVT_SAVE_TESTDATA_IN_FILE*/ + NVT_LOG("%s:--\n", __func__); + + return 0; +} + +static int32_t nvt_polling_hand_shake_status(void) +{ + uint8_t buf[8] = { 0 }; + int32_t i = 0; + const int32_t retry = 250; + + for (i = 0; i < retry; i++) { + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE); + + /* ---read fw status--- */ + buf[0] = EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE; + buf[1] = 0x00; + CTP_SPI_READ(ts->client, buf, 2); + + if ((buf[1] == 0xA0) || (buf[1] == 0xA1)) + break; + + usleep_range(10000, 10000); + } + + if (i >= retry) { + NVT_ERR("polling hand shake status failed, buf[1]=0x%02X\n", + buf[1]); + + /* Read back 5 bytes from offset EVENT_MAP_HOST_CMD for debug check */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + buf[4] = 0x00; + buf[5] = 0x00; + CTP_SPI_READ(ts->client, buf, 6); + NVT_ERR("Read back 5 bytes from offset EVENT_MAP_HOST_CMD: 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X\n", + buf[1], buf[2], buf[3], buf[4], buf[5]); + + return -1; + } else { + return 0; + } +} + +static int8_t nvt_switch_FreqHopEnDis(uint8_t FreqHopEnDis) +{ + uint8_t buf[8] = { 0 }; + uint8_t retry = 0; + int8_t ret = 0; + + NVT_LOG("%s ++\n", __func__); + + for (retry = 0; retry < 20; retry++) { + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + /* ---switch FreqHopEnDis--- */ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = FreqHopEnDis; + CTP_SPI_WRITE(ts->client, buf, 2); + + msleep(35); + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0xFF; + CTP_SPI_READ(ts->client, buf, 2); + + if (buf[1] == 0x00) + break; + } + + if (unlikely(retry == 20)) { + NVT_ERR("switch FreqHopEnDis 0x%02X failed, buf[1]=0x%02X\n", + FreqHopEnDis, buf[1]); + ret = -1; + } + + NVT_LOG("%s --\n", __func__); + + return ret; +} + +static int32_t nvt_read_baseline(int32_t *xdata) +{ + uint8_t x_num = 0; + uint8_t y_num = 0; + uint32_t x = 0; + uint32_t y = 0; + int32_t iArrayIndex = 0; + + NVT_LOG("%s ++\n", __func__); + + nvt_read_mdata(ts->mmap->BASELINE_ADDR, ts->mmap->BASELINE_BTN_ADDR); + + nvt_get_mdata(xdata, &x_num, &y_num); + + for (y = 0; y < y_num; y++) { + for (x = 0; x < x_num; x++) { + iArrayIndex = y * x_num + x; + xdata[iArrayIndex] = (int16_t)xdata[iArrayIndex]; + } + } + + NVT_LOG("%s:\n", __func__); + // Save Rawdata to CSV file + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, + FW_RAWDATA_CSV_FILE, 0, + FWMUTUAL_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("%s --\n", __func__); + + return 0; +} + +static int32_t nvt_read_CC(int32_t *xdata) +{ + uint8_t x_num = 0; + uint8_t y_num = 0; + uint32_t x = 0; + uint32_t y = 0; + int32_t iArrayIndex = 0; + + NVT_LOG("%s ++\n", __func__); + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->DIFF_PIPE1_ADDR, + ts->mmap->DIFF_BTN_PIPE1_ADDR); + else + nvt_read_mdata(ts->mmap->DIFF_PIPE0_ADDR, + ts->mmap->DIFF_BTN_PIPE0_ADDR); + + nvt_get_mdata(xdata, &x_num, &y_num); + + for (y = 0; y < y_num; y++) { + for (x = 0; x < x_num; x++) { + iArrayIndex = y * x_num + x; + xdata[iArrayIndex] = (int16_t)xdata[iArrayIndex]; + } + } + + NVT_LOG("%s:\n", __func__); + /* Save Rawdata to CSV file */ + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, FW_CC_CSV_FILE, + 0, FWCC_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("%s --\n", __func__); + + return 0; +} + +static void nvt_enable_noise_collect(int32_t frame_num) +{ + uint8_t buf[8] = { 0 }; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + /* ---enable noise collect--- */ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x47; + buf[2] = 0xAA; + buf[3] = frame_num; + buf[4] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 5); +} + +static int32_t nvt_read_fw_noise(int32_t *xdata) +{ + uint8_t x_num = 0; + uint8_t y_num = 0; + uint32_t x = 0; + uint32_t y = 0; + int32_t iArrayIndex = 0; + int32_t frame_num = 0; + uint32_t rawdata_diff_min_offset = 0; + + NVT_LOG("%s ++\n", __func__); + + /* --Enter Test Mode--- */ + if (nvt_clear_fw_status()) { + return -EAGAIN; + } + + frame_num = PS_Config_Diff_Test_Frame / 10; + if (frame_num <= 0) + frame_num = 1; + NVT_LOG("%s: frame_num=%d\n", __func__, frame_num); + nvt_enable_noise_collect(frame_num); + /* need wait PS_Config_Diff_Test_Frame * 8.3ms */ + msleep(frame_num * 83); + + if (nvt_polling_hand_shake_status()) { + return -EAGAIN; + } + + if (nvt_get_fw_info()) { + return -EAGAIN; + } + + if (nvt_get_fw_pipe() == 0) + nvt_read_mdata(ts->mmap->DIFF_PIPE0_ADDR, + ts->mmap->DIFF_BTN_PIPE0_ADDR); + else + nvt_read_mdata(ts->mmap->DIFF_PIPE1_ADDR, + ts->mmap->DIFF_BTN_PIPE1_ADDR); + + nvt_get_mdata(xdata, &x_num, &y_num); + + for (y = 0; y < y_num; y++) { + for (x = 0; x < x_num; x++) { + iArrayIndex = y * x_num + x; + RawData_Diff_Max[iArrayIndex] = + (int8_t)((xdata[iArrayIndex] >> 8) & 0xFF); + RawData_Diff_Min[iArrayIndex] = + (int8_t)(xdata[iArrayIndex] & 0xFF); + } + } + + /*---Leave Test Mode--- */ + nvt_change_mode(NORMAL_MODE); + + NVT_LOG("%s:RawData_Diff_Max:\n", __func__); + /* Save Rawdata to CSV file */ + if (nvt_save_rawdata_to_csv(RawData_Diff_Max, X_Channel, Y_Channel, + NOISE_TEST_CSV_FILE, 0, + NOISE_MAX_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + rawdata_diff_min_offset = Y_Channel * X_Channel * 7 + Y_Channel * 2; + NVT_LOG("%s:RawData_Diff_Min:\n", __func__); + /* Save Rawdata to CSV file */ + if (nvt_save_rawdata_to_csv( + RawData_Diff_Min, X_Channel, Y_Channel, NOISE_TEST_CSV_FILE, + rawdata_diff_min_offset, NOISE_MIN_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("%s --\n", __func__); + + return 0; +} + +static void nvt_enable_open_test(void) +{ + uint8_t buf[8] = { 0 }; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + /* ---enable open test--- */ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x45; + buf[2] = 0xAA; + buf[3] = 0x02; + buf[4] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 5); +} + +static void nvt_enable_short_test(void) +{ + uint8_t buf[8] = { 0 }; + + /* ---set xdata index to EVENT BUF ADDR--- */ + nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + + /* ---enable short test--- */ + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x43; + buf[2] = 0xAA; + buf[3] = 0x02; + buf[4] = 0x00; + CTP_SPI_WRITE(ts->client, buf, 5); +} + +static int32_t nvt_read_fw_open(int32_t *xdata) +{ + uint32_t raw_pipe_addr = 0; + uint8_t *rawdata_buf = NULL; + uint32_t x = 0; + uint32_t y = 0; + uint8_t buf[128] = { 0 }; + + NVT_LOG("%s ++\n", __func__); + + /*---Enter Test Mode--- */ + if (nvt_clear_fw_status()) { + return -EAGAIN; + } + + nvt_enable_open_test(); + + if (nvt_polling_hand_shake_status()) { + return -EAGAIN; + } + + rawdata_buf = (uint8_t *)kzalloc(IC_X_CFG_SIZE * IC_Y_CFG_SIZE * 2, + GFP_KERNEL); + + if (!rawdata_buf) { + NVT_ERR("kzalloc for rawdata_buf failed!\n"); + return -ENOMEM; + } + + if (nvt_get_fw_pipe() == 0) + raw_pipe_addr = ts->mmap->RAW_PIPE0_ADDR; + else + raw_pipe_addr = ts->mmap->RAW_PIPE1_ADDR; + + for (y = 0; y < IC_Y_CFG_SIZE; y++) { + /* ---change xdata index--- */ + nvt_set_page(raw_pipe_addr + y * IC_X_CFG_SIZE * 2); + + buf[0] = (uint8_t)((raw_pipe_addr + y * IC_X_CFG_SIZE * 2) & + 0xFF); + CTP_SPI_READ(ts->client, buf, IC_X_CFG_SIZE * 2 + 1); + memcpy(rawdata_buf + y * IC_X_CFG_SIZE * 2, buf + 1, + IC_X_CFG_SIZE * 2); + } + + for (y = 0; y < IC_Y_CFG_SIZE; y++) { + for (x = 0; x < IC_X_CFG_SIZE; x++) { + if ((AIN_Y[y] != 0xFF) && (AIN_X[x] != 0xFF)) { + xdata[AIN_Y[y] * X_Channel + AIN_X[x]] = (int16_t)(( + rawdata_buf[(y * IC_X_CFG_SIZE + x) * 2] + + 256 * rawdata_buf[(y * IC_X_CFG_SIZE + + x) * 2 + + 1])); + } + } + } + + if (rawdata_buf) { + kfree(rawdata_buf); + rawdata_buf = NULL; + } + + /* ---Leave Test Mode--- */ + nvt_change_mode(NORMAL_MODE); + + NVT_LOG("%s:RawData_Open\n", __func__); + /* Save RawData to CSV file */ + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, + OPEN_TEST_CSV_FILE, 0, OPEN_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("%s --\n", __func__); + + return 0; +} + +static int32_t nvt_read_fw_short(int32_t *xdata) +{ + uint32_t raw_pipe_addr = 0; + uint8_t *rawdata_buf = NULL; + uint32_t x = 0; + uint32_t y = 0; + uint8_t buf[128] = { 0 }; + int32_t iArrayIndex = 0; + + NVT_LOG("%s ++\n", __func__); + + /* ---Enter Test Mode--- */ + if (nvt_clear_fw_status()) { + return -EAGAIN; + } + + nvt_enable_short_test(); + + if (nvt_polling_hand_shake_status()) { + return -EAGAIN; + } + + rawdata_buf = (uint8_t *)kzalloc(X_Channel * Y_Channel * 2, GFP_KERNEL); + + if (!rawdata_buf) { + NVT_ERR("kzalloc for rawdata_buf failed!\n"); + return -ENOMEM; + } + + if (nvt_get_fw_pipe() == 0) + raw_pipe_addr = ts->mmap->RAW_PIPE0_ADDR; + else + raw_pipe_addr = ts->mmap->RAW_PIPE1_ADDR; + + for (y = 0; y < Y_Channel; y++) { + /* ---change xdata index--- */ + nvt_set_page(raw_pipe_addr + y * X_Channel * 2); + + buf[0] = (uint8_t)((raw_pipe_addr + y * X_Channel * 2) & 0xFF); + CTP_SPI_READ(ts->client, buf, X_Channel * 2 + 1); + memcpy(rawdata_buf + y * X_Channel * 2, buf + 1, X_Channel * 2); + } + + for (y = 0; y < Y_Channel; y++) { + for (x = 0; x < X_Channel; x++) { + iArrayIndex = y * X_Channel + x; + xdata[iArrayIndex] = + (int16_t)(rawdata_buf[iArrayIndex * 2] + + 256 * rawdata_buf[iArrayIndex * 2 + + 1]); + } + } + + if (rawdata_buf) { + kfree(rawdata_buf); + rawdata_buf = NULL; + } + + /* ---Leave Test Mode--- */ + nvt_change_mode(NORMAL_MODE); + + NVT_LOG("%s:RawData_Short\n", __func__); + /* Save Rawdata to CSV file */ + if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, + SHORT_TEST_CSV_FILE, 0, SHORT_TEST) < 0) { + NVT_ERR("save rawdata to CSV file failed\n"); + return -EAGAIN; + } + + NVT_LOG("%s --\n", __func__); + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen raw data test for each single point function. + +return: + Executive outcomes. 0---passed. negative---failed. +*******************************************************/ +static int32_t RawDataTest_SinglePoint_Sub(int32_t rawdata[], + uint8_t RecordResult[], uint8_t x_ch, + uint8_t y_ch, + int32_t Rawdata_Limit_Postive[], + int32_t Rawdata_Limit_Negative[]) +{ + int32_t i = 0; + int32_t j = 0; + int32_t iArrayIndex = 0; + bool isPass = true; + + for (j = 0; j < y_ch; j++) { + for (i = 0; i < x_ch; i++) { + iArrayIndex = j * x_ch + i; + + RecordResult[iArrayIndex] = + 0x00; /* default value for PASS */ + + if (rawdata[iArrayIndex] > + Rawdata_Limit_Postive[iArrayIndex]) + RecordResult[iArrayIndex] |= 0x01; + + if (rawdata[iArrayIndex] < + Rawdata_Limit_Negative[iArrayIndex]) + RecordResult[iArrayIndex] |= 0x02; + } + } + + /* ---Check RecordResult--- */ + for (j = 0; j < y_ch; j++) { + for (i = 0; i < x_ch; i++) { + if (RecordResult[j * x_ch + i] != 0) { + isPass = false; + break; + } + } + } + + if (isPass == false) { + return -1; + } else { + return 0; + } +} + +/******************************************************* +Description: + Novatek touchscreen print self-test result function. + +return: + n.a. +*******************************************************/ +void print_selftest_result(struct seq_file *m, int32_t TestResult, + uint8_t RecordResult[], int32_t rawdata[], + uint8_t x_len, uint8_t y_len) +{ + int32_t i = 0; + int32_t j = 0; + int32_t iArrayIndex = 0; + + switch (TestResult) { + case 0: + nvt_mp_seq_printf(m, " PASS!\n"); + break; + + case 1: + nvt_mp_seq_printf(m, " ERROR! Read Data FAIL!\n"); + break; + + case -1: + nvt_mp_seq_printf(m, " FAIL!\n"); + nvt_mp_seq_printf(m, "RecordResult:\n"); + for (i = 0; i < y_len; i++) { + for (j = 0; j < x_len; j++) { + iArrayIndex = i * x_len + j; + seq_printf(m, "0x%02X, ", + RecordResult[iArrayIndex]); + } + if (!nvt_mp_test_result_printed) + nvt_print_result_log_in_one_line( + RecordResult + i * x_len, x_len); + nvt_mp_seq_printf(m, "\n"); + } + nvt_mp_seq_printf(m, "ReadData:\n"); + for (i = 0; i < y_len; i++) { + for (j = 0; j < x_len; j++) { + iArrayIndex = i * x_len + j; + seq_printf(m, "%5d, ", rawdata[iArrayIndex]); + } + if (!nvt_mp_test_result_printed) + nvt_print_data_log_in_one_line( + rawdata + i * x_len, x_len); + nvt_mp_seq_printf(m, "\n"); + } + break; + } + nvt_mp_seq_printf(m, "\n"); +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print show + function. + +return: + Executive outcomes. 0---succeed. +*******************************************************/ +static int32_t c_show_selftest(struct seq_file *m, void *v) +{ + NVT_LOG("%s ++\n", __func__); + + nvt_mp_seq_printf(m, "FW Version: %d\n\n", fw_ver); + + nvt_mp_seq_printf(m, "Short Test"); + if ((TestResult_Short == 0) || (TestResult_Short == 1)) { + print_selftest_result(m, TestResult_Short, RecordResult_Short, + RawData_Short, X_Channel, Y_Channel); + } else { /* TestResult_Short is -1 */ + print_selftest_result(m, TestResult_Short, RecordResult_Short, + RawData_Short, X_Channel, Y_Channel); + } + + nvt_mp_seq_printf(m, "Open Test"); + print_selftest_result(m, TestResult_Open, RecordResult_Open, + RawData_Open, X_Channel, Y_Channel); + + nvt_mp_seq_printf(m, "FW Rawdata Test"); + if ((TestResult_FW_Rawdata == 0) || (TestResult_FW_Rawdata == 1)) { + print_selftest_result(m, TestResult_FWMutual, + RecordResult_FWMutual, RawData_FWMutual, + X_Channel, Y_Channel); + } else { /* TestResult_FW_Rawdata is -1 */ + nvt_mp_seq_printf(m, " FAIL!\n"); + if (TestResult_FWMutual == -1) { + nvt_mp_seq_printf(m, "FW Mutual"); + print_selftest_result(m, TestResult_FWMutual, + RecordResult_FWMutual, + RawData_FWMutual, X_Channel, + Y_Channel); + } + if (TestResult_FW_CC == -1) { + nvt_mp_seq_printf(m, "FW CC"); + print_selftest_result(m, TestResult_FW_CC, + RecordResult_FW_CC, RawData_FW_CC, + X_Channel, Y_Channel); + } + } + + nvt_mp_seq_printf(m, "Noise Test"); + if ((TestResult_Noise == 0) || (TestResult_Noise == 1)) { + print_selftest_result(m, TestResult_FW_DiffMax, + RecordResult_FW_DiffMax, RawData_Diff_Max, + X_Channel, Y_Channel); + } else { /* TestResult_Noise is -1 */ + nvt_mp_seq_printf(m, " FAIL!\n"); + + if (TestResult_FW_DiffMax == -1) { + nvt_mp_seq_printf(m, "FW Diff Max"); + print_selftest_result(m, TestResult_FW_DiffMax, + RecordResult_FW_DiffMax, + RawData_Diff_Max, X_Channel, + Y_Channel); + } + if (TestResult_FW_DiffMin == -1) { + nvt_mp_seq_printf(m, "FW Diff Min"); + print_selftest_result(m, TestResult_FW_DiffMin, + RecordResult_FW_DiffMin, + RawData_Diff_Min, X_Channel, + Y_Channel); + } + } + + nvt_mp_test_result_printed = 1; + + NVT_LOG("%s --\n", __func__); + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print start + function. + +return: + Executive outcomes. 1---call next function. + NULL---not call next function and sequence loop + stop. +*******************************************************/ +static void *c_start(struct seq_file *m, loff_t *pos) +{ + return *pos < 1 ? (void *)1 : NULL; +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print next + function. + +return: + Executive outcomes. NULL---no next and call sequence + stop function. +*******************************************************/ +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return NULL; +} + +/******************************************************* +Description: + Novatek touchscreen self-test sequence print stop + function. + +return: + n.a. +*******************************************************/ +static void c_stop(struct seq_file *m, void *v) +{ + return; +} + +const struct seq_operations nvt_selftest_seq_ops = { .start = c_start, + .next = c_next, + .stop = c_stop, + .show = c_show_selftest }; + +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV +static void goto_next_line(char **ptr) +{ + do { + *ptr = *ptr + 1; + } while (**ptr != '\n'); + *ptr = *ptr + 1; +} + +static void copy_this_line(char *dest, char *src) +{ + char *copy_from; + char *copy_to; + + copy_from = src; + copy_to = dest; + do { + *copy_to = *copy_from; + copy_from++; + copy_to++; + } while ((*copy_from != '\n') && (*copy_from != '\r')); + *copy_to = '\0'; +} + +int32_t parse_mp_setting_criteria_item(char **ptr, const char *item_string, + int32_t *item_value) +{ + char *tmp = NULL; + + NVT_LOG("%s ++\n", __func__); + tmp = strstr(*ptr, item_string); + if (tmp == NULL) { + NVT_ERR("%s not found\n", item_string); + return -1; + } + *ptr = tmp; + goto_next_line(ptr); + sscanf(*ptr, "%d,", item_value); + NVT_LOG("%s %d\n", item_string, *item_value); + + NVT_LOG("%s --\n", __func__); + return 0; +} + +int32_t parse_mp_setting_ain_array(char **ptr, const char *item_string, + uint8_t *ain_array, uint32_t IC_CFG_SIZE) +{ + char *tmp = NULL; + int32_t i = 0; + char *token = NULL; + char *tok_ptr = NULL; + size_t offset = 0; + char tmp_buf[512] = { 0 }; + + NVT_LOG("%s ++\n", __func__); + tmp = strstr(*ptr, item_string); + if (tmp == NULL) { + NVT_ERR("%s not found!\n", item_string); + return -1; + } + *ptr = tmp; + + NVT_LOG("%s\n", item_string); + /* walk thru this line */ + goto_next_line(ptr); + + /* copy this line to tmp_buf */ + memset(tmp_buf, 0, sizeof(tmp_buf)); + copy_this_line(tmp_buf, *ptr); + offset = strlen(tmp_buf); + tok_ptr = tmp_buf; + i = 0; + while ((token = strsep(&tok_ptr, ", \t\r\0"))) { + if (strlen(token) == 0) + continue; + if (!strcmp(token, "0xFF") || !strcmp(token, "0xff")) + ain_array[i] = 255; + else + ain_array[i] = (uint8_t)simple_strtol(token, NULL, 10); + NVT_LOG("%d, ", ain_array[i]); + + i++; + } + NVT_LOG("\n"); + /* check if number equals to IC_CFG_SIZE */ + if (i != IC_CFG_SIZE) { + NVT_ERR("load AIN config failed!, i=%d, IC_CFG_SIZE=%d\n", i, + IC_CFG_SIZE); + return -1; + } + /* go forward */ + *ptr = *ptr + offset; + + NVT_LOG("%s --\n", __func__); + return 0; +} + +int32_t parse_mp_criteria_item_array(char **ptr, const char *item_string, + int32_t *item_array) +{ + char *tmp = NULL; + int32_t i = 0; + int32_t j = 0; + char *token = NULL; + char *tok_ptr = NULL; + size_t offset = 0; + char tmp_buf[512] = { 0 }; + + NVT_LOG("%s ++\n", __func__); + tmp = strstr(*ptr, item_string); + if (tmp == NULL) { + NVT_ERR("%s not found\n", item_string); + return -1; + } + *ptr = tmp; + + NVT_LOG("%s\n", item_string); + for (i = 0; i < Y_Channel; i++) { + /* walk thru this line */ + goto_next_line(ptr); + memset(tmp_buf, 0, sizeof(tmp_buf)); + copy_this_line(tmp_buf, *ptr); + offset = strlen(tmp_buf); + tok_ptr = tmp_buf; + j = 0; + while ((token = strsep(&tok_ptr, ", \t\r\0"))) { + if (strlen(token) == 0) + continue; + item_array[i * X_Channel + j] = + (int32_t)simple_strtol(token, NULL, 10); + NVT_LOG("%5d, ", item_array[i * X_Channel + j]); + j++; + } + NVT_LOG("\n"); + /* check if j equals to X_Channel */ + if (j != X_Channel) { + NVT_ERR("%s :j not equal X_Channel!, j=%d, X_Channel=%d\n", + item_string, j, X_Channel); + return -1; + } + /* go forward */ + *ptr = *ptr + offset; + } + + NVT_LOG("%s --\n", __func__); + return 0; +} + +static int32_t nvt_load_mp_setting_criteria_from_csv(const char *filename) +{ + int32_t retval = 0; + const struct firmware *fw_entry = NULL; + char *fbufp = NULL; + char *ptr = NULL; + + NVT_LOG("%s ++\n", __func__); + + if (NULL == filename) { + NVT_ERR("filename is null\n"); + retval = -1; + goto exit_free; + } + + retval = request_firmware(&fw_entry, filename, &ts->client->dev); + if (retval) { + NVT_ERR("%s load failed, retval=%d\n", filename, retval); + retval = -1; + goto exit_free; + } + + fbufp = (char *)kzalloc(fw_entry->size + 2, GFP_KERNEL); + if (!fbufp) { + NVT_ERR("kzalloc %zu bytes failed!\n", fw_entry->size); + retval = -1; + goto exit_free; + } + + memcpy(fbufp, fw_entry->data, fw_entry->size); + + /* NVT_LOG("File Size: %zu\n", fw_entry->size); + NVT_LOG("---------------------------------------------------\n"); + printk("fbufp:\n"); + for(i = 0; i < fw_entry->size; i++) { + printk("%c", fbufp[i]); + } + NVT_LOG("---------------------------------------------------\n"); */ + + fbufp[fw_entry->size] = '\0'; + fbufp[fw_entry->size + 1] = '\n'; + + ptr = fbufp; + if (parse_mp_setting_criteria_item( + &ptr, "IC_X_CFG_SIZE:", &IC_X_CFG_SIZE) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_criteria_item( + &ptr, "IC_Y_CFG_SIZE:", &IC_Y_CFG_SIZE) < 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_criteria_item(&ptr, "X_Channel:", &X_Channel) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_criteria_item(&ptr, "Y_Channel:", &Y_Channel) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_ain_array(&ptr, "AIN_X:", AIN_X, IC_X_CFG_SIZE) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_ain_array(&ptr, "AIN_Y:", AIN_Y, IC_Y_CFG_SIZE) < + 0) { + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Short_Rawdata_P:", + PS_Config_Lmt_Short_Rawdata_P) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Short_Rawdata_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Short_Rawdata_N:", + PS_Config_Lmt_Short_Rawdata_N) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Short_Rawdata_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Open_Rawdata_P:", + PS_Config_Lmt_Open_Rawdata_P) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Open_Rawdata_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_Open_Rawdata_N:", + PS_Config_Lmt_Open_Rawdata_N) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_Open_Rawdata_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_Rawdata_P:", + PS_Config_Lmt_FW_Rawdata_P) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Rawdata_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_Rawdata_N:", + PS_Config_Lmt_FW_Rawdata_N) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Rawdata_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_CC_P:", + PS_Config_Lmt_FW_CC_P) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_CC_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_CC_N:", + PS_Config_Lmt_FW_CC_N) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_CC_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_Diff_P:", + PS_Config_Lmt_FW_Diff_P) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Diff_P array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_criteria_item_array(&ptr, "PS_Config_Lmt_FW_Diff_N:", + PS_Config_Lmt_FW_Diff_N) < 0) { + NVT_ERR("Cannot get PS_Config_Lmt_FW_Diff_N array value!\n"); + retval = -1; + goto exit_free; + } + + ptr = fbufp; + if (parse_mp_setting_criteria_item(&ptr, "PS_Config_Diff_Test_Frame:", + &PS_Config_Diff_Test_Frame) < 0) { + retval = -1; + goto exit_free; + } + + NVT_LOG("Load MP setting and criteria from CSV file finished.\n"); + retval = 0; + +exit_free: + if (fw_entry) { + release_firmware(fw_entry); + fw_entry = NULL; + } + if (fbufp) { + kfree(fbufp); + fbufp = NULL; + } + + NVT_LOG("--, retval=%d\n", retval); + return retval; +} +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + +/******************************************************* +Description: + Novatek touchscreen /proc/nvt_selftest open function. + +return: + Executive outcomes. 0---succeed. negative---failed. +*******************************************************/ +static int32_t nvt_selftest_open(struct inode *inode, struct file *file) +{ + struct device_node *np = ts->pdev->dev.of_node; + unsigned char mpcriteria[32] = { 0 }; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + char mp_setting_criteria_csv_filename[64] = { 0 }; +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + TestResult_Short = 0; + TestResult_Open = 0; + TestResult_FW_Rawdata = 0; + TestResult_FWMutual = 0; + TestResult_FW_CC = 0; + TestResult_Noise = 0; + TestResult_FW_DiffMax = 0; + TestResult_FW_DiffMin = 0; + + NVT_LOG("%s ++\n", __func__); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_MP_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->mp_name); + } + } else { + nvt_update_firmware(ts->mp_name); + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + NVT_ERR("get fw info failed!\n"); + return -EAGAIN; + } + fw_ver = ts->fw_ver; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + /* ---Check if MP Setting Criteria CSV file exist and load--- */ + snprintf(mp_setting_criteria_csv_filename, PAGE_SIZE, + "NT36xxx_MP_Setting_Criteria_%04X.csv", ts->nvt_pid); + NVT_LOG("MP setting criteria csv filename: %s\n", + mp_setting_criteria_csv_filename); + if (nvt_load_mp_setting_criteria_from_csv( + mp_setting_criteria_csv_filename) < 0) { + NVT_ERR("SelfTest MP setting criteria CSV file not exist or load failed\n"); +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + /* Parsing criteria from dts */ + if (of_property_read_bool(np, "novatek,mp-support-dt")) { + /* + * Parsing Criteria by Novatek PID + * The string rule is "novatek-mp-criteria-" + * nvt_pid is 2 bytes (show hex). + * + * Ex. nvt_pid = 500A + * mpcriteria = "novatek-mp-criteria-500A" + */ + snprintf(mpcriteria, PAGE_SIZE, + "novatek-mp-criteria-%04X", ts->nvt_pid); + + if (nvt_mp_parse_dt(np, mpcriteria)) { + /* ---Download Normal FW--- */ + nvt_update_firmware(ts->fw_name); + mutex_unlock(&ts->lock); + NVT_ERR("mp parse device tree failed!\n"); + return -EINVAL; + } + } else { + NVT_LOG("Not found novatek,mp-support-dt, use default setting\n"); + /* ---Print Test Criteria--- */ + nvt_print_criteria(); + } +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + } else { + NVT_LOG("SelfTest MP setting criteria loaded from CSV file\n"); + } +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + if (nvt_switch_FreqHopEnDis(FREQ_HOP_DISABLE)) { + mutex_unlock(&ts->lock); + NVT_ERR("switch frequency hopping disable failed!\n"); + return -EAGAIN; + } + + if (nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN)) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw reset state failed!\n"); + return -EAGAIN; + } + + msleep(100); + + /* ---Enter Test Mode--- */ + if (nvt_clear_fw_status()) { + mutex_unlock(&ts->lock); + NVT_ERR("clear fw status failed!\n"); + return -EAGAIN; + } + + nvt_change_mode(MP_MODE_CC); + + if (nvt_check_fw_status()) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw status failed!\n"); + return -EAGAIN; + } + + /* ---FW Rawdata Test--- */ + if (nvt_read_baseline(RawData_FWMutual) != 0) { + TestResult_FWMutual = 1; + } else { + TestResult_FWMutual = RawDataTest_SinglePoint_Sub( + RawData_FWMutual, RecordResult_FWMutual, X_Channel, + Y_Channel, PS_Config_Lmt_FW_Rawdata_P, + PS_Config_Lmt_FW_Rawdata_N); + } + if (nvt_read_CC(RawData_FW_CC) != 0) { + TestResult_FW_CC = 1; + } else { + TestResult_FW_CC = RawDataTest_SinglePoint_Sub( + RawData_FW_CC, RecordResult_FW_CC, X_Channel, Y_Channel, + PS_Config_Lmt_FW_CC_P, PS_Config_Lmt_FW_CC_N); + } + + if ((TestResult_FWMutual == 1) || (TestResult_FW_CC == 1)) { + TestResult_FW_Rawdata = 1; + } else { + if ((TestResult_FWMutual == -1) || (TestResult_FW_CC == -1)) + TestResult_FW_Rawdata = -1; + else + TestResult_FW_Rawdata = 0; + } + + /*---Leave Test Mode--- */ + nvt_change_mode(NORMAL_MODE); + + /*---Noise Test--- */ + if (nvt_read_fw_noise(RawData_Diff) != 0) { + TestResult_Noise = 1; /* 1: ERROR */ + TestResult_FW_DiffMax = 1; + TestResult_FW_DiffMin = 1; + } else { + TestResult_FW_DiffMax = RawDataTest_SinglePoint_Sub( + RawData_Diff_Max, RecordResult_FW_DiffMax, X_Channel, + Y_Channel, PS_Config_Lmt_FW_Diff_P, + PS_Config_Lmt_FW_Diff_N); + + TestResult_FW_DiffMin = RawDataTest_SinglePoint_Sub( + RawData_Diff_Min, RecordResult_FW_DiffMin, X_Channel, + Y_Channel, PS_Config_Lmt_FW_Diff_P, + PS_Config_Lmt_FW_Diff_N); + + if ((TestResult_FW_DiffMax == -1) || + (TestResult_FW_DiffMin == -1)) + TestResult_Noise = -1; + else + TestResult_Noise = 0; + } + + /* --Short Test--- */ + if (nvt_read_fw_short(RawData_Short) != 0) { + TestResult_Short = 1; // 1:ERROR */ + } else { + /* ---Self Test Check --- 0:PASS, -1:FAIL */ + TestResult_Short = RawDataTest_SinglePoint_Sub( + RawData_Short, RecordResult_Short, X_Channel, Y_Channel, + PS_Config_Lmt_Short_Rawdata_P, + PS_Config_Lmt_Short_Rawdata_N); + } + + /*---Open Test--- */ + if (nvt_read_fw_open(RawData_Open) != 0) { + TestResult_Open = 1; /* 1:ERROR */ + } else { + /*---Self Test Check --- 0:PASS, -1:FAIL */ + TestResult_Open = RawDataTest_SinglePoint_Sub( + RawData_Open, RecordResult_Open, X_Channel, Y_Channel, + PS_Config_Lmt_Open_Rawdata_P, + PS_Config_Lmt_Open_Rawdata_N); + } + + /* ---Download Normal FW--- */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + nvt_mp_test_result_printed = 0; + + return seq_open(file, &nvt_selftest_seq_ops); +} + +static const struct file_operations nvt_selftest_fops = { + .owner = THIS_MODULE, + .open = nvt_selftest_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +#ifdef CONFIG_OF +/******************************************************* +Description: + Novatek touchscreen parse AIN setting for array type. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_ain(struct device_node *np, const char *name, + uint8_t *array, int32_t size) +{ + struct property *data; + int32_t len, ret; + int32_t tmp[40]; + int32_t i; + + data = of_find_property(np, name, &len); + len /= sizeof(u32); + if ((!data) || (!len) || (len != size)) { + NVT_ERR("error find %s. len=%d\n", name, len); + return -1; + } else { + NVT_LOG("%s. len=%d\n", name, len); + ret = of_property_read_u32_array(np, name, tmp, len); + if (ret) { + NVT_ERR("error reading %s. ret=%d\n", name, ret); + return -1; + } + + for (i = 0; i < len; i++) + array[i] = tmp[i]; + + NVT_LOG("[NVT-ts] %s = ", name); + nvt_print_result_log_in_one_line(array, len); + NVT_LOG("\n"); + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen parse criterion for u32 type. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_u32(struct device_node *np, const char *name, + int32_t *para) +{ + int32_t ret; + + ret = of_property_read_u32(np, name, para); + if (ret) { + NVT_ERR("error reading %s. ret=%d\n", name, ret); + return -1; + } else { + NVT_LOG("%s=%d\n", name, *para); + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen parse criterion for array type. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_array(struct device_node *np, const char *name, + int32_t *array, int32_t size) +{ + struct property *data; + int32_t len, ret; + int32_t j = 0; + + data = of_find_property(np, name, &len); + len /= sizeof(u32); + if ((!data) || (!len) || (len < size)) { + NVT_ERR("error find %s. len=%d\n", name, len); + return -1; + } else { + NVT_LOG("%s. len=%d\n", name, len); + ret = of_property_read_u32_array(np, name, array, len); + if (ret) { + NVT_ERR("error reading %s. ret=%d\n", name, ret); + return -1; + } + + NVT_LOG("%s =\n", name); + for (j = 0; j < Y_Channel; j++) { + nvt_print_data_log_in_one_line(array + j * X_Channel, + X_Channel); + NVT_LOG("\n"); + } + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen parse device tree mp function. + +return: + n.a. +*******************************************************/ +int32_t nvt_mp_parse_dt(struct device_node *root, const char *node_compatible) +{ + struct device_node *np = root; + struct device_node *child = NULL; + + NVT_LOG("Parse mp criteria for node %s\n", node_compatible); + + /* find each MP sub-nodes */ + for_each_child_of_node(root, child) { + /* find the specified node */ + if (of_device_is_compatible(child, node_compatible)) { + NVT_LOG("found child node %s\n", node_compatible); + np = child; + break; + } + } + if (child == NULL) { + NVT_ERR("Not found compatible node %s!\n", node_compatible); + return -1; + } + + /* MP Config*/ + if (nvt_mp_parse_u32(np, "IC_X_CFG_SIZE", &IC_X_CFG_SIZE)) + return -1; + + if (nvt_mp_parse_u32(np, "IC_Y_CFG_SIZE", &IC_Y_CFG_SIZE)) + return -1; + + if (nvt_mp_parse_u32(np, "X_Channel", &X_Channel)) + return -1; + + if (nvt_mp_parse_u32(np, "Y_Channel", &Y_Channel)) + return -1; + + if (nvt_mp_parse_ain(np, "AIN_X", AIN_X, IC_X_CFG_SIZE)) + return -1; + + if (nvt_mp_parse_ain(np, "AIN_Y", AIN_Y, IC_Y_CFG_SIZE)) + return -1; + + /* MP Criteria */ + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Short_Rawdata_P", + PS_Config_Lmt_Short_Rawdata_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Short_Rawdata_N", + PS_Config_Lmt_Short_Rawdata_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Open_Rawdata_P", + PS_Config_Lmt_Open_Rawdata_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_Open_Rawdata_N", + PS_Config_Lmt_Open_Rawdata_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Rawdata_P", + PS_Config_Lmt_FW_Rawdata_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Rawdata_N", + PS_Config_Lmt_FW_Rawdata_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_CC_P", + PS_Config_Lmt_FW_CC_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_CC_N", + PS_Config_Lmt_FW_CC_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Diff_P", + PS_Config_Lmt_FW_Diff_P, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_array(np, "PS_Config_Lmt_FW_Diff_N", + PS_Config_Lmt_FW_Diff_N, + X_Channel * Y_Channel + Key_Channel)) + return -1; + + if (nvt_mp_parse_u32(np, "PS_Config_Diff_Test_Frame", + &PS_Config_Diff_Test_Frame)) + return -1; + + NVT_LOG("Parse mp criteria done!\n"); + + return 0; +} +#endif /* #ifdef CONFIG_OF */ + +static int nvt_short_test(void) +{ + struct device_node *np = ts->client->dev.of_node; + unsigned char mpcriteria[32] = { 0 }; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + char mp_setting_criteria_csv_filename[64] = { 0 }; +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + TestResult_Short = 0; + + NVT_LOG("%s ++\n", __func__); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_MP_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->mp_name); + } + } else { + nvt_update_firmware(ts->mp_name); + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + NVT_ERR("get fw info failed!\n"); + return -EAGAIN; + } + fw_ver = ts->fw_ver; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + /* ---Check if MP Setting Criteria CSV file exist and load--- */ + snprintf(mp_setting_criteria_csv_filename, PAGE_SIZE, + "NT36xxx_MP_Setting_Criteria_%04X.csv", ts->nvt_pid); + NVT_LOG("MP setting criteria csv filename: %s\n", + mp_setting_criteria_csv_filename); + if (nvt_load_mp_setting_criteria_from_csv( + mp_setting_criteria_csv_filename) < 0) { + NVT_ERR("SelfTest MP setting criteria CSV file not exist or load failed\n"); +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + /* Parsing criteria from dts */ + if (of_property_read_bool(np, "novatek,mp-support-dt")) { + /* + * Parsing Criteria by Novatek PID + * The string rule is "novatek-mp-criteria-" + * nvt_pid is 2 bytes (show hex). + * + * Ex. nvt_pid = 500A + * mpcriteria = "novatek-mp-criteria-500A" + */ + snprintf(mpcriteria, PAGE_SIZE, + "novatek-mp-criteria-%04X", ts->nvt_pid); + + if (nvt_mp_parse_dt(np, mpcriteria)) { + /* ---Download Normal FW--- */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware( + DEFAULT_DEBUG_FW_NAME) < + 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware( + ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + mutex_unlock(&ts->lock); + NVT_ERR("mp parse device tree failed!\n"); + return -EINVAL; + } + } else { + NVT_LOG("Not found novatek,mp-support-dt, use default setting\n"); + /* ---Print Test Criteria--- */ + nvt_print_criteria(); + } +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + } else { + NVT_LOG("SelfTest MP setting criteria loaded from CSV file\n"); + } +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + if (nvt_switch_FreqHopEnDis(FREQ_HOP_DISABLE)) { + mutex_unlock(&ts->lock); + NVT_ERR("switch frequency hopping disable failed!\n"); + return -EAGAIN; + } + + if (nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN)) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw reset state failed!\n"); + return -EAGAIN; + } + + msleep(100); + + /* --Short Test--- */ + if (nvt_read_fw_short(RawData_Short) != 0) { + TestResult_Short = 1; /* 1:ERROR */ + } else { + /* ---Self Test Check --- 0:PASS, -1:FAIL */ + TestResult_Short = RawDataTest_SinglePoint_Sub( + RawData_Short, RecordResult_Short, X_Channel, Y_Channel, + PS_Config_Lmt_Short_Rawdata_P, + PS_Config_Lmt_Short_Rawdata_N); + } + + /* ---Download Normal FW--- */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + nvt_mp_test_result_printed = 0; + return TestResult_Short; +} + +static int nvt_open_test(void) +{ + struct device_node *np = ts->client->dev.of_node; + unsigned char mpcriteria[32] = { 0 }; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + char mp_setting_criteria_csv_filename[64] = { 0 }; +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + TestResult_Open = 0; + + NVT_LOG("%s ++\n", __func__); + + if (mutex_lock_interruptible(&ts->lock)) { + return -ERESTARTSYS; + } + +#if NVT_TOUCH_ESD_PROTECT + nvt_esd_check_enable(false); +#endif /* #if NVT_TOUCH_ESD_PROTECT */ + + /* ---Download MP FW--- */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_MP_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->mp_name); + } + } else { + nvt_update_firmware(ts->mp_name); + } + + if (nvt_get_fw_info()) { + mutex_unlock(&ts->lock); + NVT_ERR("get fw info failed!\n"); + return -EAGAIN; + } + fw_ver = ts->fw_ver; +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + /* ---Check if MP Setting Criteria CSV file exist and load--- */ + snprintf(mp_setting_criteria_csv_filename, PAGE_SIZE, + "NT36xxx_MP_Setting_Criteria_%04X.csv", ts->nvt_pid); + NVT_LOG("MP setting criteria csv filename: %s\n", + mp_setting_criteria_csv_filename); + if (nvt_load_mp_setting_criteria_from_csv( + mp_setting_criteria_csv_filename) < 0) { + NVT_ERR("SelfTest MP setting criteria CSV file not exist or load failed\n"); +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + /* Parsing criteria from dts */ + if (of_property_read_bool(np, "novatek,mp-support-dt")) { + /* + * Parsing Criteria by Novatek PID + * The string rule is "novatek-mp-criteria-" + * nvt_pid is 2 bytes (show hex). + * + * Ex. nvt_pid = 500A + * mpcriteria = "novatek-mp-criteria-500A" + */ + snprintf(mpcriteria, PAGE_SIZE, + "novatek-mp-criteria-%04X", ts->nvt_pid); + + if (nvt_mp_parse_dt(np, mpcriteria)) { + /* ---Download Normal FW--- */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware( + DEFAULT_DEBUG_FW_NAME) < + 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware( + ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + mutex_unlock(&ts->lock); + NVT_ERR("mp parse device tree failed!\n"); + return -EINVAL; + } + } else { + NVT_LOG("Not found novatek,mp-support-dt, use default setting\n"); + /* ---Print Test Criteria--- */ + nvt_print_criteria(); + } +#if NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV + } else { + NVT_LOG("SelfTest MP setting criteria loaded from CSV file\n"); + } +#endif /* NVT_TOUCH_MP_SETTING_CRITERIA_FROM_CSV */ + + if (nvt_switch_FreqHopEnDis(FREQ_HOP_DISABLE)) { + mutex_unlock(&ts->lock); + NVT_ERR("switch frequency hopping disable failed!\n"); + return -EAGAIN; + } + + if (nvt_check_fw_reset_state(RESET_STATE_NORMAL_RUN)) { + mutex_unlock(&ts->lock); + NVT_ERR("check fw reset state failed!\n"); + return -EAGAIN; + } + + msleep(100); + + /*---Open Test--- */ + if (nvt_read_fw_open(RawData_Open) != 0) { + TestResult_Open = 1; /* 1:ERROR */ + } else { + /* ---Self Test Check --- 0:PASS, -1:FAIL */ + TestResult_Open = RawDataTest_SinglePoint_Sub( + RawData_Open, RecordResult_Open, X_Channel, Y_Channel, + PS_Config_Lmt_Open_Rawdata_P, + PS_Config_Lmt_Open_Rawdata_N); + } + + /* ---Download Normal FW--- */ + if (nvt_get_dbgfw_status()) { + if (nvt_update_firmware(DEFAULT_DEBUG_FW_NAME) < 0) { + NVT_ERR("use built-in fw"); + nvt_update_firmware(ts->fw_name); + } + } else { + nvt_update_firmware(ts->fw_name); + } + + mutex_unlock(&ts->lock); + + NVT_LOG("%s --\n", __func__); + + nvt_mp_test_result_printed = 0; + + return TestResult_Open; +} + +static ssize_t nvt_selftest_read(struct file *file, char __user *buf, + size_t count, loff_t *pos) +{ + char tmp[5] = { 0 }; + int cnt; + + if (*pos != 0) + return 0; + cnt = snprintf(tmp, sizeof(ts->result_type), "%d\n", ts->result_type); + if (copy_to_user(buf, tmp, strlen(tmp))) { + return -EFAULT; + } + + *pos += cnt; + return cnt; +} + +static ssize_t nvt_selftest_write(struct file *file, const char __user *buf, + size_t count, loff_t *pos) +{ + int retval = 0; + char tmp[6]; + + if (copy_from_user(tmp, buf, count)) { + retval = -EFAULT; + goto out; + } + + if (!strncmp("short", tmp, 5)) { + retval = nvt_short_test(); + } else if (!strncmp("open", tmp, 4)) { + retval = nvt_open_test(); + } else if (!strncmp("i2c", tmp, 3)) { + retval = nvt_get_fw_info(); + } else { + NVT_ERR("[%s] cmd not support", tmp); + retval = -EINVAL; + } + + switch (retval) { + case 0: + ts->result_type = NVT_RESULT_PASS; + break; + case -EINVAL: + ts->result_type = NVT_RESULT_INVALID; + break; + default: + ts->result_type = NVT_RESULT_FAIL; + break; + } + +out: + if (retval >= 0) + retval = count; + + return retval; +} + +static const struct file_operations nvt_aftersales_test_ops = { + .read = nvt_selftest_read, + .write = nvt_selftest_write, +}; + +/******************************************************* +Description: + Novatek touchscreen MP function proc. file node + initial function. + +return: + Executive outcomes. 0---succeed. -1---failed. +*******************************************************/ +int32_t nvt_mp_proc_init(void) +{ + NVT_proc_selftest_entry = + proc_create("nvt_selftest", 0444, NULL, &nvt_selftest_fops); + if (NVT_proc_selftest_entry == NULL) { + NVT_ERR("create /proc/nvt_selftest Failed!\n"); + return -1; + } else { + if (nvt_mp_buffer_init()) { + NVT_ERR("Allocate mp memory failed\n"); + return -1; + } else { + NVT_LOG("create /proc/nvt_selftest Succeeded!\n"); + } + } + + NVT_proc_aftersales_test_entry = proc_create("tp_selftest", 0644, NULL, + &nvt_aftersales_test_ops); + if (NVT_proc_aftersales_test_entry == NULL) { + NVT_ERR("create /proc/tp_selftest Failed!\n"); + return -1; + } else { + NVT_LOG("create /proc/tp_selftest Succeeded!\n"); + } + + return 0; +} + +/******************************************************* +Description: + Novatek touchscreen MP function proc. file node + deinitial function. + +return: + n.a. +*******************************************************/ +void nvt_mp_proc_deinit(void) +{ + nvt_mp_buffer_deinit(); + + if (NVT_proc_selftest_entry != NULL) { + remove_proc_entry("nvt_selftest", NULL); + NVT_proc_selftest_entry = NULL; + NVT_LOG("Removed /proc/%s\n", "nvt_selftest"); + } +} + +#ifndef NVT_SAVE_TESTDATA_IN_FILE +static void test_buff_free(struct test_buf *buf) +{ + if (buf) { + if (buf->shorttest.buf) + kfree(buf->shorttest.buf); + if (buf->opentest.buf) + kfree(buf->opentest.buf); + if (buf->fwmutualtest.buf) + kfree(buf->fwmutualtest.buf); + if (buf->fwcctest.buf) + kfree(buf->fwcctest.buf); + if (buf->noisetest_max.buf) + kfree(buf->noisetest_max.buf); + if (buf->noisetest_min.buf) + kfree(buf->noisetest_min.buf); + kfree(buf); + } + return; +} + +static int32_t test_buff_init(struct test_buf **tbuf) +{ + struct test_buf *buf; + int32_t ret; + + buf = (struct test_buf *)kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf); + goto alloc_fail; + } + + buf->shorttest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->shorttest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->shorttest.buf); + goto alloc_fail; + } + + buf->opentest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->opentest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->opentest.buf); + goto alloc_fail; + } + + buf->fwmutualtest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->fwmutualtest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->fwmutualtest.buf); + goto alloc_fail; + } + + buf->fwcctest.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->fwcctest.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->fwcctest.buf); + goto alloc_fail; + } + + buf->noisetest_max.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->noisetest_max.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->noisetest_max.buf); + goto alloc_fail; + } + + buf->noisetest_min.buf = kzalloc(TEST_BUF_LEN, GFP_KERNEL); + if (!buf->noisetest_min.buf) { + NVT_ERR("alloc memory failed"); + ret = PTR_ERR(buf->noisetest_min.buf); + goto alloc_fail; + } + + buf->shorttest.type = SHORT_TEST; + buf->opentest.type = OPEN_TEST; + buf->fwmutualtest.type = FWMUTUAL_TEST; + buf->fwcctest.type = FWCC_TEST; + buf->noisetest_max.type = NOISE_MAX_TEST; + buf->noisetest_min.type = NOISE_MIN_TEST; + + *tbuf = buf; + return ret; + +alloc_fail: + *tbuf = NULL; + test_buff_free(buf); + return ret; +} + +struct item_buf *item_arr[MAX_TEST_TYPE]; + +static void *t_start(struct seq_file *m, loff_t *pos) +{ + struct test_buf *tbuf = ts->testdata; + + item_arr[SHORT_TEST] = &tbuf->shorttest; + item_arr[OPEN_TEST] = &tbuf->opentest; + item_arr[FWMUTUAL_TEST] = &tbuf->fwmutualtest; + item_arr[FWCC_TEST] = &tbuf->fwcctest; + item_arr[NOISE_MAX_TEST] = &tbuf->noisetest_max; + item_arr[NOISE_MIN_TEST] = &tbuf->noisetest_min; + + if (*pos >= MAX_TEST_TYPE) { + /* *pos = 0; */ + return NULL; + } + + NVT_LOG("In start\n"); + NVT_LOG("=short= item ptr (%p), type (%d), buf ptr(%p)\n", + &tbuf->shorttest, tbuf->shorttest.type, tbuf->shorttest.buf); + NVT_LOG("=open= item ptr (%p), type (%d), buf ptr(%p)\n", + &tbuf->opentest, tbuf->opentest.type, tbuf->opentest.buf); + NVT_LOG("pos (%lld), first item ptr(%p)", *pos, item_arr[*pos]); + return item_arr[*pos]; +} + +static void *t_next(struct seq_file *m, void *v, loff_t *pos) +{ + NVT_LOG("In next\n"); + NVT_LOG("ptr v (%p), pos (%lld), item ptr (%p)\n", v, *pos, + &item_arr[*pos]); + + ++*pos; + if (*pos >= MAX_TEST_TYPE) { + /* *pos = 0; */ + return NULL; + } + + NVT_LOG("ptr v (%p), pos (%lld), item ptr (%p)\n", v, *pos, + &item_arr[*pos]); + return item_arr[*pos]; +} + +static int32_t t_show(struct seq_file *m, void *v) +{ + int i, j; + struct item_buf *item = v; + int32_t *data = (int32_t *)item->buf; + + NVT_LOG("In show\n"); + NVT_LOG("item ptr (%p), type (%d), buf ptr(%p)\n", item, item->type, + item->buf); + + switch (item->type) { + case SHORT_TEST: + seq_printf(m, "========SHORT_TEST========\n"); + break; + case OPEN_TEST: + seq_printf(m, "========OPEN_TEST========\n"); + break; + case FWMUTUAL_TEST: + seq_printf(m, "========FWMUTUAL_TEST========\n"); + break; + case FWCC_TEST: + seq_printf(m, "========FWCC_TEST========\n"); + break; + case NOISE_MAX_TEST: + seq_printf(m, "========NOISE_MAX_TEST========\n"); + break; + case NOISE_MIN_TEST: + seq_printf(m, "========NOISE_MIN_TEST========\n"); + break; + default: + NVT_LOG("test type illegal (%d)\n", item->type); + return -EINVAL; + } + + for (i = 0; i < Y_Channel; i++) { + for (j = 0; j < X_Channel; j++) { + seq_printf(m, "%5d, ", data[i * X_Channel + j]); + } + seq_puts(m, "\n"); + } + seq_puts(m, "\n\n"); + + return 0; +} + +static void t_stop(struct seq_file *m, void *v) +{ + NVT_LOG("In stop\n"); + return; +} + +const struct seq_operations t_fops = { + .start = t_start, + .next = t_next, + .stop = t_stop, + .show = t_show, +}; + +static int32_t nvt_test_data_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &t_fops); +} + +static const struct file_operations nvt_test_data_fops = { + .owner = THIS_MODULE, + .open = nvt_test_data_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +int32_t nvt_test_data_proc_init(struct spi_device *client) +{ + int ret; + struct test_buf *tbuf; + struct nvt_ts_data *ts = spi_get_drvdata(client); + + NVT_proc_test_data_entry = + proc_create("nvt_test_data", 0, NULL, &nvt_test_data_fops); + if (NVT_proc_test_data_entry == NULL) { + NVT_ERR("create proc/nvt_test_data Failed!"); + return -ENOMEM; + } else { + NVT_LOG("create proc/nvt_test_data Succeeded!"); + } + + ret = test_buff_init(&tbuf); + if (!tbuf) { + NVT_ERR("test buff init failed"); + remove_proc_entry("nvt_test_data", NULL); + return ret; + } + + ts->testdata = tbuf; + + return 0; +} + +void nvt_test_data_proc_deinit(void) +{ + test_buff_free(ts->testdata); + ts->testdata = NULL; + + if (NVT_proc_test_data_entry != NULL) { + remove_proc_entry("nvt_test_data", NULL); + NVT_proc_test_data_entry = NULL; + NVT_LOG("Removed /proc/nvt_test_data"); + } +} +#endif /*ifndef NVT_SAVE_TESTDATA_IN_FILE*/ +#endif /* #if NVT_TOUCH_MP */ diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.h b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.h new file mode 100644 index 000000000000..f42c64546aa2 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2010 - 2018 Novatek, Inc. + * + * $Revision: 32206 $ + * $Date: 2018-08-10 19:23:04 +0800 (週五, 10 八月 2018) $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#if NVT_TOUCH_MP + +extern uint32_t IC_X_CFG_SIZE; +extern uint32_t IC_Y_CFG_SIZE; +extern uint32_t IC_KEY_CFG_SIZE; +extern uint32_t X_Channel; +extern uint32_t Y_Channel; +extern uint32_t Key_Channel; +extern uint8_t AIN_X[40]; +extern uint8_t AIN_Y[40]; + +extern int32_t PS_Config_Lmt_Short_Rawdata_P[40 * 40]; + +extern int32_t PS_Config_Lmt_Short_Rawdata_N[40 * 40]; + +extern int32_t PS_Config_Lmt_Open_Rawdata_P[40 * 40]; + +extern int32_t PS_Config_Lmt_Open_Rawdata_N[40 * 40]; + +extern int32_t PS_Config_Lmt_FW_Rawdata_P[40 * 40]; + +extern int32_t PS_Config_Lmt_FW_Rawdata_N[40 * 40]; + +extern int32_t PS_Config_Lmt_FW_CC_P[40 * 40]; + +extern int32_t PS_Config_Lmt_FW_CC_N[40 * 40]; + +extern int32_t PS_Config_Lmt_FW_Diff_P[40 * 40]; + +extern int32_t PS_Config_Lmt_FW_Diff_N[40 * 40]; + +extern int32_t PS_Config_Diff_Test_Frame; + +#ifndef NVT_SAVE_TESTDATA_IN_FILE +#define TEST_BUF_LEN 5000 + +enum test_type { + SHORT_TEST = 0, + OPEN_TEST, + FWMUTUAL_TEST, + FWCC_TEST, + NOISE_MAX_TEST, + NOISE_MIN_TEST, + MAX_TEST_TYPE = 6, +}; + +struct item_buf { + uint8_t *buf; + uint32_t len; + enum test_type type; +}; + +struct test_buf { + // spinlock_t tbuf_lock; + // bool update; + struct item_buf shorttest; + struct item_buf opentest; + struct item_buf fwmutualtest; + struct item_buf fwcctest; + struct item_buf noisetest_max; + struct item_buf noisetest_min; +}; + +int32_t nvt_test_data_proc_init(struct spi_device *client); +void nvt_test_data_proc_deinit(void); + +#endif /*#ifndef NVT_SAVE_TESTDATA_IN_FILE*/ + +#endif /* #if NVT_TOUCH_MP */ diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram_data.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram_data.c new file mode 100644 index 000000000000..ce96954ba111 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx_mp_ctrlram_data.c @@ -0,0 +1,536 @@ +#include "nt36xxx.h" + +#if NVT_TOUCH_MP + +uint32_t IC_X_CFG_SIZE = 18; +uint32_t IC_Y_CFG_SIZE = 36; +uint32_t IC_KEY_CFG_SIZE = 4; +uint32_t X_Channel = 18; +uint32_t Y_Channel = 36; +uint32_t Key_Channel = TOUCH_KEY_NUM; +uint8_t AIN_X[40] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15, 16, 17 }; +uint8_t AIN_Y[40] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 }; + +int32_t PS_Config_Lmt_Short_Rawdata_P[40 * 40] = { + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, + 14008, 14008, 14008, 14008, 14008, 14008, 14008, 14008, +}; + +int32_t PS_Config_Lmt_Short_Rawdata_N[40 * 40] = { + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, + 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, +}; + +int32_t PS_Config_Lmt_Open_Rawdata_P[40 * 40] = { + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, + 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 4096, +}; + +int32_t PS_Config_Lmt_Open_Rawdata_N[40 * 40] = { + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, +}; + +int32_t PS_Config_Lmt_FW_Rawdata_P[40 * 40] = { + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, + 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, 1920, +}; + +int32_t PS_Config_Lmt_FW_Rawdata_N[40 * 40] = { + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, +}; + +int32_t PS_Config_Lmt_FW_CC_P[40 * 40] = { + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, 314, + 314, 314, 314, 314, +}; + +int32_t PS_Config_Lmt_FW_CC_N[40 * 40] = { + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, +}; + +int32_t PS_Config_Lmt_FW_Diff_P[40 * 40] = { + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, + 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, +}; + +int32_t PS_Config_Lmt_FW_Diff_N[40 * 40] = { + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, -75, + -75, -75, -75, -75, + +}; + +int32_t PS_Config_Diff_Test_Frame = 50; +#endif /*NVT_TOUCH_MP*/ diff --git a/drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.c b/drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.c new file mode 100644 index 000000000000..3301a6c252b2 --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.c @@ -0,0 +1,196 @@ +#include + +#define DEBUG + +static struct ts_spi_info owner; + +static ssize_t ts_xsfer_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t ret; + mutex_lock(&owner.lock); + ret = snprintf(buf, PAGE_SIZE, "[%s] used:%d, tmp:%d\n", owner.name, + owner.used, owner.tmp); + mutex_unlock(&owner.lock); + return ret; +} + +static DEVICE_ATTR(ts_xsfer_state, S_IRUGO, ts_xsfer_state_show, NULL); + +/*tmporary get spi device's ownership until invoke tmp_drop_ts_xsfer() + * + *return -EBUSY others is using, -EPERM if spi device already belong to others. + */ +int32_t tmp_hold_ts_xsfer(struct spi_device **client) +{ + if (!owner.init) { + PDEBUG("ts_xsfer does not exist"); + return -EINVAL; + } + mutex_lock(&owner.lock); + if (owner.used) { + PDEBUG("ts_xsfer belong to %s, can't tmporary use it\n", + owner.name); + mutex_unlock(&owner.lock); + return -EPERM; + } + + if (owner.tmp) { + PDEBUG("ts_xsfer is in using, others can't use it now\n"); + mutex_unlock(&owner.lock); + return -EBUSY; + } + + owner.tmp = true; + *client = owner.client; + mutex_unlock(&owner.lock); + return 0; +} + +EXPORT_SYMBOL_GPL(tmp_hold_ts_xsfer); + +/*must balance with tmp_hold_ts_xsfer*/ +void tmp_drop_ts_xsfer(void) +{ + if (owner.init) { + mutex_lock(&owner.lock); + owner.tmp = false; + mutex_unlock(&owner.lock); + } +} + +EXPORT_SYMBOL_GPL(tmp_drop_ts_xsfer); + +/*make spi device belong to module which invoke this function + *-EPERM if spi device already belong to others. + */ +int32_t get_ts_xsfer(const char *name) +{ + if (!name) { + PDEBUG("name can't be empty\n"); + return -EINVAL; + } + mutex_lock(&owner.lock); + if (owner.used) { + PDEBUG("ts_xsfer belong to %s, others can't get it\n", + owner.name); + mutex_unlock(&owner.lock); + return -EPERM; + } + owner.used = true; + strlcpy(owner.name, name, NAME_MAX_LENS); + mutex_unlock(&owner.lock); + return 0; +} + +EXPORT_SYMBOL_GPL(get_ts_xsfer); + +void put_ts_xsfer(const char *name) +{ + if (name && !strncmp(name, owner.name, NAME_MAX_LENS)) { + mutex_lock(&owner.lock); + owner.used = false; + owner.name[0] = '\0'; + mutex_unlock(&owner.lock); + } else { + PDEBUG("must released by owner\n"); + } +} + +EXPORT_SYMBOL_GPL(put_ts_xsfer); + +const char *get_owner_name(void) +{ + if (owner.name[0] == '\0') + return NULL; + return owner.name; +} + +EXPORT_SYMBOL_GPL(get_owner_name); + +/*test weather spi device belong someone, if not get the device's ownership. + *name@:name of owner + *return NULL if device already been used. + */ +struct spi_device *test_then_get_spi(const char *name) +{ + struct spi_device *ret; + + mutex_lock(&owner.lock); + if (owner.used) { + ret = NULL; + } else { + owner.used = true; + ret = owner.client; + if (name) + strlcpy(owner.name, name, NAME_MAX_LENS); + } + mutex_unlock(&owner.lock); + + return ret; +} + +EXPORT_SYMBOL_GPL(test_then_get_spi); + +static int32_t ts_spi_probe(struct spi_device *client) +{ + int32_t ret; + PDEBUG("Start probe\n"); + mutex_init(&owner.lock); + owner.name[0] = '\0'; + owner.used = false; + owner.tmp = false; + owner.client = client; + + ret = sysfs_create_file(&client->dev.kobj, + &dev_attr_ts_xsfer_state.attr); + if (ret < 0) { + PDEBUG("create sysfs failed\n"); + } + + owner.init = true; + PDEBUG("init ts_xsfer device successful\n"); + + return 0; +} + +static int32_t ts_spi_remove(struct spi_device *client) +{ + PDEBUG("touch_xsfer will be remove, touch must stop spi xsfer\n"); + sysfs_remove_file(&client->dev.kobj, &dev_attr_ts_xsfer_state.attr); + return 0; +} + +static struct of_device_id ts_match_tbl[] = { + { + .compatible = "xiaomi,spi-for-tp", + }, + {}, +}; + +static struct spi_driver touch_spi_drv = { + .probe = ts_spi_probe, + .remove = ts_spi_remove, + .driver = { + .name = "touch_xsfer", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(ts_match_tbl), + }, +}; + +static int32_t __init touch_spi_init(void) +{ + PDEBUG("Start register spi for tp\n"); + return spi_register_driver(&touch_spi_drv); +} + +static void __exit touch_spi_exit(void) +{ + spi_unregister_driver(&touch_spi_drv); +} + +module_init(touch_spi_init); +module_exit(touch_spi_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("XIAOMI,JIANGHAO"); diff --git a/drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.h b/drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.h new file mode 100644 index 000000000000..1de8d7b4f52b --- /dev/null +++ b/drivers/input/touchscreen/xiaomi/spi-xiaomi-tp.h @@ -0,0 +1,52 @@ +#ifndef _SPI_XIAOMI_TP_H +#define _SPI_XIAOMI_TP_H + +#include +#include +#include +#include +#include + +#define TP_SPI_DEBUG + +#define TP_TAG "[TP_SPI]: " + +#undef PDEBUG +#ifdef TP_SPI_DEBUG +#ifdef __KERNEL__ +#define PDEBUG(fmt, args...) printk(KERN_ERR TP_TAG fmt, ##args) +#else /*NO __KERNEL__*/ +#define PDEBUG(fmt, args...) fprintf(stderr, TP_TAG fmt, ##args) +#endif /*END __KERNEL__*/ +#else /*NO TP_SPI_DEBUG*/ +#define PDEBUG(fmt, args...) +#endif /*END TP_SPI_DEBUG*/ + +#undef PDEBUGG +#define PDEBUGG(fmt, args...) +#define NAME_MAX_LENS 32 + +/*lock@:protect this struct + *name@:indicate who own this device + *used@:indicate this device has it owner + *tmp@:device in using but don't has it owner + *init&:indicate ts_xsfer already init. + *client@:pointer to spi device + */ +struct ts_spi_info { + struct mutex lock; + char name[NAME_MAX_LENS]; + bool used; + bool tmp; + bool init; + struct spi_device *client; +}; + +extern int32_t tmp_hold_ts_xsfer(struct spi_device **client); +extern void tmp_drop_ts_xsfer(void); +extern int32_t get_ts_xsfer(const char *name); +extern void put_ts_xsfer(const char *name); +extern const char *get_owner_name(void); +extern struct spi_device *test_then_get_spi(const char *name); + +#endif /*_SPI_XIAOMI_TP_H*/ diff --git a/firmware/Makefile b/firmware/Makefile index 96b4a8b0a63b..dc3996547019 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -20,6 +20,18 @@ fw-external-y := $(subst $(quote),,$(CONFIG_EXTRA_FIRMWARE)) # For the former two cases we want $(fw-shipped-y) and $(fw-shipped-m) to be # accurate. In the latter case it doesn't matter -- it'll use $(fw-shipped-all). # But be aware that the config file might not be included at all. +fw-shipped-$(CONFIG_TOUCHSCREEN_GOODIX_GTX8) += goodix_gt9886_cfg_f11.bin goodix_gt9886_fw_f11.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_ST_FTS_V521) += st_fts_f1.ftb st_fts.ftb st_fts_e5.ftb st_fts_f1x.ftb +fw-shipped-$(CONFIG_TOUCHSCREEN_ST_FTS_V59y) += st_fts_j2a.ftb st_fts_j2a_sdc.ftb st_fts_j2a_csot.ftb +fw-shipped-$(CONFIG_INPUT_PRESS_NDT) += ndt_fw.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36XX) += novatek_nt36672_f10.fw +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI) += j20s_novatek_ts_fw01.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI) += j20s_novatek_ts_mp01.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI) += j20s_novatek_ts_fw02.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI) += j20s_novatek_ts_mp02.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36523_HOSTDL_SPI) += novatek_ts_fw.bin novatek_ts_mp.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36523_HOSTDL_SPI) += novatek_nt36523_fw01.bin novatek_nt36523_mp01.bin +fw-shipped-$(CONFIG_TOUCHSCREEN_NT36523_HOSTDL_SPI) += novatek_nt36523_fw02.bin novatek_nt36523_mp02.bin fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) diff --git a/firmware/goodix_gt9886_cfg_f11.bin.ihex b/firmware/goodix_gt9886_cfg_f11.bin.ihex new file mode 100755 index 000000000000..d15385aa4983 --- /dev/null +++ b/firmware/goodix_gt9886_cfg_f11.bin.ihex @@ -0,0 +1,116 @@ +:10000000260700005D000000000200000000000064 +:1000100014009D03890300006E6F726D616E647938 +:1000200000000000000000010139383836000000EF +:1000300000000000000000000000000000000000C0 +:100040000000000000000000000000004245040025 +:100050002C454800354504003D45040041450F004E +:100060000000000000000000786F0000F330000086 +:10007000686F000000410000000000000000000068 +:10008000000000000000000000000000001E012C25 +:10009000B5011F34F188821E200401210117DE08FA +:1000A000070400000F210000320000222112003F4F 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+:10BDA000640010000000000000000000000000001F +:10BDB0000000000000000000000000000000000083 +:10BDC0000000000000000000000000000000000073 +:0CBDD000000000000000000043C6B0E2CC +:00000001FF diff --git a/include/uapi/linux/input-event-codes.h b/include/uapi/linux/input-event-codes.h index dae4dde06926..7048ef8ca1a9 100644 --- a/include/uapi/linux/input-event-codes.h +++ b/include/uapi/linux/input-event-codes.h @@ -418,6 +418,7 @@ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 +#define BTN_INFO 0x152 #define KEY_OK 0x160 #define KEY_SELECT 0x161 From a645ae3e579da35a9b802b90c9fe780fc77e1ab8 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 11:50:55 +0100 Subject: [PATCH 056/226] drivers: input: touchscreen: xiaomi: Use MSM DRM notifier Change-Id: I7ceaeb165b790ba69621074a7470569acf1f07aa Signed-off-by: firebird11 --- .../input/touchscreen/xiaomi/fts_521/fts.c | 30 +++--- .../goodix_driver_gt9886/goodix_cfg_bin.c | 4 +- .../goodix_driver_gt9886/goodix_ts_core.c | 21 ++-- .../goodix_driver_gt9886/goodix_ts_core.h | 2 +- .../touchscreen/xiaomi/nt36523/nt36xxx.c | 100 ++++++++---------- .../touchscreen/xiaomi/nt36523/nt36xxx.h | 4 +- .../touchscreen/xiaomi/nt36672c/nt36xxx.c | 20 ++-- 7 files changed, 85 insertions(+), 96 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c index e03e326c2241..f00d2eb9cce4 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -56,7 +56,7 @@ #include #ifdef CONFIG_DRM -#include +#include #endif #include @@ -1235,7 +1235,7 @@ static ssize_t stm_fts_cmd_show(struct device *dev, goto END; } #ifdef CONFIG_DRM - res = drm_unregister_client(&info->notifier); + res = msm_drm_unregister_client(&info->notifier); if (res < 0) { logError(1, "%s ERROR: unregister notifier failed!\n", tag); @@ -1467,7 +1467,7 @@ static ssize_t stm_fts_cmd_show(struct device *dev, res = ERROR_OP_NOT_ALLOW; } #ifdef CONFIG_DRM - if (drm_register_client(&info->notifier) < 0) { + if (msm_drm_register_client(&info->notifier) < 0) { logError(1, "%s ERROR: register notifier failed!\n", tag); } #endif @@ -4738,7 +4738,7 @@ static int fts_init_sensing(struct fts_ts_info *info) { int error = 0; #ifdef CONFIG_DRM - error |= drm_register_client(&info->notifier); + error |= msm_drm_register_client(&info->notifier); #endif error |= fts_interrupt_install(info); error |= fts_mode_handler(info, 0); @@ -5794,7 +5794,7 @@ static int fts_drm_state_chg_callback(struct notifier_block *nb, { struct fts_ts_info *info = container_of(nb, struct fts_ts_info, notifier); - struct drm_notify_data *evdata = data; + struct msm_drm_notifier *evdata = data; unsigned int blank; logError(0, "%s %s: fts notifier begin!\n", tag, __func__); @@ -5804,20 +5804,22 @@ static int fts_drm_state_chg_callback(struct notifier_block *nb, logError(1, "%s %s: val:%lu,blank:%u\n", tag, __func__, val, blank); - if (val == DRM_EARLY_EVENT_BLANK && - (blank == DRM_BLANK_POWERDOWN || blank == DRM_BLANK_LP1 || - blank == DRM_BLANK_LP2)) { + if (val == MSM_DRM_EARLY_EVENT_BLANK && + (blank == MSM_DRM_BLANK_POWERDOWN || + blank == MSM_DRM_BLANK_LP1 || + blank == MSM_DRM_BLANK_LP2)) { if (info->sensor_sleep) return NOTIFY_OK; logError(1, "%s %s: FB_BLANK %s\n", tag, __func__, - blank == DRM_BLANK_POWERDOWN ? "POWER DOWN" : - "LP"); + blank == MSM_DRM_BLANK_POWERDOWN ? + "POWER DOWN" : + "LP"); flush_workqueue(info->event_wq); queue_work(info->event_wq, &info->suspend_work); - } else if (val == DRM_EVENT_BLANK && - blank == DRM_BLANK_UNBLANK) { + } else if (val == MSM_DRM_EVENT_BLANK && + blank == MSM_DRM_BLANK_UNBLANK) { if (!info->sensor_sleep) return NOTIFY_OK; @@ -7363,7 +7365,7 @@ static int fts_probe(struct spi_device *client) kfree(info->dma_buf->wrBuf); #endif #ifdef CONFIG_DRM - drm_unregister_client(&info->notifier); + msm_drm_unregister_client(&info->notifier); #endif ProbeErrorExit_6: @@ -7412,7 +7414,7 @@ static int fts_remove(struct spi_device *client) fts_interrupt_uninstall(info); /*backlight_unregister_notifier(&info->bl_notifier);*/ #ifdef CONFIG_DRM - drm_unregister_client(&info->notifier); + msm_drm_unregister_client(&info->notifier); #endif /* unregister the device */ diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c index d1025106a6a5..ee539cdcf643 100644 --- a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_cfg_bin.c @@ -1,5 +1,5 @@ #include "goodix_cfg_bin.h" -#include +#include extern int goodix_i2c_write(struct goodix_ts_device *dev, unsigned int reg, unsigned char *data, unsigned int len); @@ -291,7 +291,7 @@ int goodix_cfg_bin_proc(void *data) #ifdef CONFIG_DRM core_data->fb_notifier.notifier_call = goodix_ts_fb_notifier_callback; - if (drm_register_client(&core_data->fb_notifier)) + if (msm_drm_register_client(&core_data->fb_notifier)) ts_err("Failed to register fb notifier client:%d", r); #elif defined(CONFIG_HAS_EARLYSUSPEND) core_data->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1; diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c index 37eadcd09e81..3ba99ad25043 100644 --- a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c @@ -28,7 +28,7 @@ #include #include #ifdef CONFIG_DRM -#include +#include #include #include #endif @@ -1903,27 +1903,28 @@ int goodix_ts_fb_notifier_callback(struct notifier_block *self, { struct goodix_ts_core *core_data = container_of(self, struct goodix_ts_core, fb_notifier); - struct drm_notify_data *fb_event = data; + struct msm_drm_notifier *fb_event = data; int blank; if (fb_event && fb_event->data && core_data) { blank = *(int *)(fb_event->data); flush_workqueue(core_data->event_wq); - if (event == DRM_EVENT_BLANK && - (blank == DRM_BLANK_POWERDOWN || blank == DRM_BLANK_LP1 || - blank == DRM_BLANK_LP2)) { + if (event == MSM_DRM_EVENT_BLANK && + (blank == MSM_DRM_BLANK_POWERDOWN || + blank == MSM_DRM_BLANK_LP1 || + blank == MSM_DRM_BLANK_LP2)) { ts_info("touchpanel suspend .....blank=%d\n", blank); ts_info("touchpanel suspend .....suspend_stat=%d\n", atomic_read(&core_data->suspend_stat)); if (atomic_read(&core_data->suspend_stat)) return 0; ts_info("touchpanel suspend by %s", - blank == DRM_BLANK_POWERDOWN ? "blank" : - "doze"); + blank == MSM_DRM_BLANK_POWERDOWN ? "blank" : + "doze"); queue_work(core_data->event_wq, &core_data->suspend_work); - } else if (event == DRM_EVENT_BLANK && - blank == DRM_BLANK_UNBLANK) { + } else if (event == MSM_DRM_EVENT_BLANK && + blank == MSM_DRM_BLANK_UNBLANK) { //if (!atomic_read(&core_data->suspend_stat)) ts_info("core_data->suspend_stat = %d\n", atomic_read(&core_data->suspend_stat)); @@ -2845,7 +2846,7 @@ static int goodix_ts_remove(struct platform_device *pdev) { struct goodix_ts_core *core_data = platform_get_drvdata(pdev); #ifdef CONFIG_DRM - drm_unregister_client(&core_data->fb_notifier); + msm_drm_unregister_client(&core_data->fb_notifier); #endif //wake_lock_destroy(&core_data->tp_wakelock); power_supply_unreg_notifier(&core_data->power_supply_notifier); diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h index c6033562578a..ac6600cf8b36 100644 --- a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.h @@ -48,7 +48,7 @@ #include #endif #ifdef CONFIG_DRM -#include +#include #include #include #endif diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c index 1851c7c5b5e6..39f9746cda1f 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -27,10 +27,9 @@ #include #include -#if defined(CONFIG_FB) #ifdef CONFIG_DRM -#include -#endif +#include +#elif defined(CONFIG_FB) #include #include #elif defined(CONFIG_HAS_EARLYSUSPEND) @@ -75,14 +74,12 @@ static struct workqueue_struct *nvt_lockdown_wq; extern void Boot_Update_Firmware(struct work_struct *work); #endif -#if defined(CONFIG_FB) #ifdef CONFIG_DRM static int nvt_drm_notifier_callback(struct notifier_block *self, unsigned long event, void *data); -#else +#elif defined(CONFIG_FB) static int nvt_fb_notifier_callback(struct notifier_block *self, unsigned long event, void *data); -#endif #elif defined(CONFIG_HAS_EARLYSUSPEND) static void nvt_ts_early_suspend(struct early_suspend *h); static void nvt_ts_late_resume(struct early_suspend *h); @@ -3260,22 +3257,20 @@ static int32_t nvt_ts_probe(struct spi_device *client) ret); goto err_register_pen_charge_state_failed; } -#if defined(CONFIG_FB) #ifdef CONFIG_DRM ts->drm_notif.notifier_call = nvt_drm_notifier_callback; - ret = drm_register_client(&ts->drm_notif); + ret = msm_drm_register_client(&ts->drm_notif); if (ret) { NVT_ERR("register drm_notifier failed. ret=%d\n", ret); goto err_register_drm_notif_failed; } -#else +#elif defined(CONFIG_FB) ts->fb_notif.notifier_call = nvt_fb_notifier_callback; ret = fb_register_client(&ts->fb_notif); if (ret) { NVT_ERR("register fb_notifier failed. ret=%d\n", ret); goto err_register_fb_notif_failed; } -#endif #elif defined(CONFIG_HAS_EARLYSUSPEND) ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1; ts->early_suspend.suspend = nvt_ts_early_suspend; @@ -3318,16 +3313,14 @@ static int32_t nvt_ts_probe(struct spi_device *client) return 0; -#if defined(CONFIG_FB) #ifdef CONFIG_DRM - if (drm_unregister_client(&ts->drm_notif)) + if (msm_drm_unregister_client(&ts->drm_notif)) NVT_ERR("Error occurred while unregistering drm_notifier.\n"); err_register_drm_notif_failed: -#else +#elif defined(CONFIG_FB) if (fb_unregister_client(&ts->fb_notif)) NVT_ERR("Error occurred while unregistering fb_notifier.\n"); err_register_fb_notif_failed: -#endif #elif defined(CONFIG_HAS_EARLYSUSPEND) unregister_early_suspend(&ts->early_suspend); err_register_early_suspend_failed: @@ -3438,14 +3431,12 @@ static int32_t nvt_ts_remove(struct spi_device *client) { NVT_LOG("Removing driver...\n"); -#if defined(CONFIG_FB) #ifdef CONFIG_DRM - if (drm_unregister_client(&ts->drm_notif)) + if (msm_drm_unregister_client(&ts->drm_notif)) NVT_ERR("Error occurred while unregistering drm_notifier.\n"); -#else +#elif defined(CONFIG_FB) if (fb_unregister_client(&ts->fb_notif)) NVT_ERR("Error occurred while unregistering fb_notifier.\n"); -#endif #elif defined(CONFIG_HAS_EARLYSUSPEND) unregister_early_suspend(&ts->early_suspend); #endif @@ -3524,14 +3515,12 @@ static void nvt_ts_shutdown(struct spi_device *client) nvt_irq_enable(false); -#if defined(CONFIG_FB) #ifdef CONFIG_DRM - if (drm_unregister_client(&ts->drm_notif)) + if (msm_drm_unregister_client(&ts->drm_notif)) NVT_ERR("Error occurred while unregistering drm_notifier.\n"); -#else +#elif defined(CONFIG_FB) if (fb_unregister_client(&ts->fb_notif)) NVT_ERR("Error occurred while unregistering fb_notifier.\n"); -#endif #elif defined(CONFIG_HAS_EARLYSUSPEND) unregister_early_suspend(&ts->early_suspend); #endif @@ -3773,12 +3762,11 @@ static int32_t nvt_ts_resume(struct device *dev) return 0; } -#if defined(CONFIG_FB) #ifdef CONFIG_DRM static int nvt_drm_notifier_callback(struct notifier_block *self, unsigned long event, void *data) { - struct drm_notify_data *evdata = data; + struct msm_drm_notifier *evdata = data; int *blank; struct nvt_ts_data *ts_data = container_of(self, struct nvt_ts_data, drm_notif); @@ -3788,22 +3776,22 @@ static int nvt_drm_notifier_callback(struct notifier_block *self, if (evdata && ts_data) { blank = evdata->data; - if (event == DRM_EARLY_EVENT_BLANK) { - if (*blank == DRM_BLANK_POWERDOWN) { + if (event == MSM_DRM_EARLY_EVENT_BLANK) { + if (*blank == MSM_DRM_BLANK_POWERDOWN) { NVT_LOG("event=%lu, *blank=%d\n", event, *blank); flush_workqueue(ts_data->event_wq); queue_work(ts_data->event_wq, &ts_data->suspend_work); } - } else if (event == DRM_R_EARLY_EVENT_BLANK) { - if (*blank == DRM_BLANK_POWERDOWN) { + } else if (event == MSM_DRM_R_EARLY_EVENT_BLANK) { + if (*blank == MSM_DRM_BLANK_POWERDOWN) { NVT_LOG("event=%lu, *blank=%d\n", event, *blank); nvt_enable_doubleclick(); } - } else if (event == DRM_EVENT_BLANK) { - if (*blank == DRM_BLANK_UNBLANK) { + } else if (event == MSM_DRM_EVENT_BLANK) { + if (*blank == MSM_DRM_BLANK_UNBLANK) { NVT_LOG("event=%lu, *blank=%d\n", event, *blank); flush_workqueue(ts_data->event_wq); @@ -3815,7 +3803,7 @@ static int nvt_drm_notifier_callback(struct notifier_block *self, return 0; } -#else +#elif defined(CONFIG_FB) static int nvt_fb_notifier_callback(struct notifier_block *self, unsigned long event, void *data) { @@ -3840,8 +3828,33 @@ static int nvt_fb_notifier_callback(struct notifier_block *self, return 0; } +#elif defined(CONFIG_HAS_EARLYSUSPEND) +/******************************************************* +Description: + Novatek touchscreen driver early suspend function. + +return: + n.a. +*******************************************************/ +static void nvt_ts_early_suspend(struct early_suspend *h) +{ + nvt_ts_suspend(ts->client, PMSG_SUSPEND); +} + +/******************************************************* +Description: + Novatek touchscreen driver late resume function. + +return: + n.a. +*******************************************************/ +static void nvt_ts_late_resume(struct early_suspend *h) +{ + nvt_ts_resume(ts->client); +} #endif +#ifdef CONFIG_PM static int nvt_pm_suspend(struct device *dev) { if (device_may_wakeup(dev) && ts->db_wakeup) { @@ -3870,31 +3883,6 @@ static const struct dev_pm_ops nvt_dev_pm_ops = { .suspend = nvt_pm_suspend, .resume = nvt_pm_resume, }; - -#elif defined(CONFIG_HAS_EARLYSUSPEND) -/******************************************************* -Description: - Novatek touchscreen driver early suspend function. - -return: - n.a. -*******************************************************/ -static void nvt_ts_early_suspend(struct early_suspend *h) -{ - nvt_ts_suspend(ts->client, PMSG_SUSPEND); -} - -/******************************************************* -Description: - Novatek touchscreen driver late resume function. - -return: - n.a. -*******************************************************/ -static void nvt_ts_late_resume(struct early_suspend *h) -{ - nvt_ts_resume(ts->client); -} #endif static const struct spi_device_id nvt_ts_id[] = { { NVT_SPI_NAME, 0 }, {} }; diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h index fcc59ba5cf78..2f79af798a64 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.h @@ -146,12 +146,10 @@ struct nvt_ts_data { struct notifier_block pen_charge_state_notifier; uint16_t addr; int8_t phys[32]; -#if defined(CONFIG_FB) #ifdef CONFIG_DRM struct notifier_block drm_notif; -#else +#elif defined(CONFIG_FB) struct notifier_block fb_notif; -#endif #elif defined(CONFIG_HAS_EARLYSUSPEND) struct early_suspend early_suspend; #endif diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c index cb4c52513ded..bb18ef46c2e1 100644 --- a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c @@ -33,7 +33,7 @@ #include #ifdef CONFIG_DRM -#include +#include #endif #include @@ -2680,7 +2680,7 @@ static int32_t nvt_ts_probe(struct platform_device *pdev) #ifdef CONFIG_DRM ts->drm_notif.notifier_call = nvt_drm_notifier_callback; - ret = drm_register_client(&ts->drm_notif); + ret = msm_drm_register_client(&ts->drm_notif); if (ret) { NVT_ERR("register drm_notifier failed. ret=%d\n", ret); goto err_register_drm_notif_failed; @@ -2735,7 +2735,7 @@ static int32_t nvt_ts_probe(struct platform_device *pdev) return 0; #ifdef CONFIG_DRM - if (drm_unregister_client(&ts->drm_notif)) + if (msm_drm_unregister_client(&ts->drm_notif)) NVT_ERR("Error occurred while unregistering drm_notifier.\n"); err_register_drm_notif_failed: #else @@ -2830,7 +2830,7 @@ static int32_t nvt_ts_remove(struct platform_device *pdev) NVT_LOG("Removing driver...\n"); #ifdef CONFIG_DRM - if (drm_unregister_client(&ts->drm_notif)) + if (msm_drm_unregister_client(&ts->drm_notif)) NVT_ERR("Error occurred while unregistering drm_notifier.\n"); #else if (fb_unregister_client(&ts->fb_notif)) @@ -2904,7 +2904,7 @@ static void nvt_ts_shutdown(struct platform_device *pdev) nvt_irq_enable(false); #ifdef CONFIG_DRM - if (drm_unregister_client(&ts->drm_notif)) + if (msm_drm_unregister_client(&ts->drm_notif)) NVT_ERR("Error occurred while unregistering drm_notifier.\n"); #else if (fb_unregister_client(&ts->fb_notif)) @@ -3139,7 +3139,7 @@ static int32_t nvt_ts_resume(struct device *dev) static int nvt_drm_notifier_callback(struct notifier_block *self, unsigned long event, void *data) { - struct drm_notify_data *evdata = data; + struct msm_drm_notifier *evdata = data; int *blank; struct nvt_ts_data *ts_data = container_of(self, struct nvt_ts_data, drm_notif); @@ -3148,15 +3148,15 @@ static int nvt_drm_notifier_callback(struct notifier_block *self, blank = evdata->data; NVT_LOG("%s: event:%lu,blank:%u\n", event, blank); - if (event == DRM_EARLY_EVENT_BLANK) { - if (*blank == DRM_BLANK_POWERDOWN) { + if (event == MSM_DRM_EARLY_EVENT_BLANK) { + if (*blank == MSM_DRM_BLANK_POWERDOWN) { NVT_LOG("event=%lu, *blank=%d\n", event, *blank); flush_workqueue(ts_data->event_wq); nvt_ts_suspend(&ts_data->client->dev); } - } else if (event == DRM_EVENT_BLANK) { - if (*blank == DRM_BLANK_UNBLANK) { + } else if (event == MSM_DRM_EVENT_BLANK) { + if (*blank == MSM_DRM_BLANK_UNBLANK) { NVT_LOG("event=%lu, *blank=%d\n", event, *blank); flush_workqueue(ts_data->event_wq); From 341dbd00ef558b196062d09ef1361de0f246d66b Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 11 Oct 2023 15:37:05 +0200 Subject: [PATCH 057/226] drivers: input: touchscreen: xiaomi: Drop touch_irq_boost Change-Id: I0f82537d75f453fc88e389d494117b34cd7cdc4f Signed-off-by: firebird11 --- drivers/input/touchscreen/xiaomi/fts_521/fts.c | 1 - drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c | 2 -- drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c | 3 --- 3 files changed, 6 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c index f00d2eb9cce4..965d0214e0f7 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -151,7 +151,6 @@ static int fts_chip_initialization(struct fts_ts_info *info, int init_type); static const char *fts_get_limit(struct fts_ts_info *info); static irqreturn_t fts_event_handler(int irq, void *ts_info); extern void lpm_disable_for_input(bool on); -extern void touch_irq_boost(void); /** * Release all the touches in the linux input subsystem diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c index 39f9746cda1f..4e1bdb5f4795 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -89,7 +89,6 @@ static int32_t nvt_ts_suspend(struct device *dev); static int32_t nvt_ts_resume(struct device *dev); extern int dsi_panel_lockdown_info_read(unsigned char *plockdowninfo); extern void dsi_panel_doubleclick_enable(bool on); -extern void touch_irq_boost(void); extern void lpm_disable_for_input(bool on); extern int pen_charge_state_notifier_register_client(struct notifier_block *nb); extern int @@ -1664,7 +1663,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) } #endif - touch_irq_boost(); lpm_disable_for_input(true); mutex_lock(&ts->lock); diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c index bb18ef46c2e1..93ba8565e00a 100644 --- a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c @@ -97,7 +97,6 @@ extern void dsi_panel_doubleclick_enable(bool on); #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE static int32_t nvt_check_palm(uint8_t input_id, uint8_t *data); #endif -extern void touch_irq_boost(void); extern void lpm_disable_for_input(bool on); uint32_t ENG_RST_ADDR = 0x7FFF80; uint32_t SWRST_N8_ADDR = 0; /* read from dtsi */ @@ -1419,8 +1418,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) pm_wakeup_event(&ts->input_dev->dev, 5000); } #endif - if (ts->debug_flag == TOUCH_IRQ_BOOST) - touch_irq_boost(); mutex_lock(&ts->lock); if (ts->debug_flag >= TOUCH_DISABLE_LPM) lpm_disable_for_input(true); From 0bc9a89b48f929fccbcc1d1850ec57332370411a Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 28 Jan 2024 03:09:02 +0100 Subject: [PATCH 058/226] drivers: input: touchscreen: xiaomi: Drop lpm_disable_for_input Change-Id: I3b8c72c63dc3e20c00e54ef28925126345075a38 Signed-off-by: firebird11 --- drivers/input/touchscreen/xiaomi/fts_521/fts.c | 10 ---------- .../input/touchscreen/xiaomi/nt36523/nt36xxx.c | 6 ------ .../input/touchscreen/xiaomi/nt36672c/nt36xxx.c | 17 ----------------- 3 files changed, 33 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c index 965d0214e0f7..d5fa0b5ec0a2 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -150,7 +150,6 @@ static int fts_mode_handler(struct fts_ts_info *info, int force); static int fts_chip_initialization(struct fts_ts_info *info, int init_type); static const char *fts_get_limit(struct fts_ts_info *info); static irqreturn_t fts_event_handler(int irq, void *ts_info); -extern void lpm_disable_for_input(bool on); /** * Release all the touches in the linux input subsystem @@ -181,7 +180,6 @@ void release_all_touches(struct fts_ts_info *info) #ifdef STYLUS_MODE info->stylus_id = 0; #endif - lpm_disable_for_input(false); } /** @@ -3395,7 +3393,6 @@ static void fts_leave_pointer_event_handler(struct fts_ts_info *info, input_mt_report_slot_state(info->input_dev, tool, 0); if (info->touch_id == 0) { input_report_key(info->input_dev, BTN_TOUCH, touch_condition); - lpm_disable_for_input(false); if (!touch_condition) input_report_key(info->input_dev, BTN_TOOL_FINGER, 0); #ifdef CONFIG_FTS_FOD_AREA_REPORT @@ -4116,7 +4113,6 @@ static void fts_ts_sleep_work(struct work_struct *work) tag); pm_relax(info->dev); fts_enableInterrupt(); - lpm_disable_for_input(false); return; } else { logError( @@ -4176,7 +4172,6 @@ static void fts_ts_sleep_work(struct work_struct *work) #endif pm_relax(info->dev); fts_enableInterrupt(); - lpm_disable_for_input(false); return; } @@ -4214,8 +4209,6 @@ static irqreturn_t fts_event_handler(int irq, void *ts_info) return IRQ_HANDLED; } #endif - lpm_disable_for_input(true); - info->irq_status = true; error = fts_writeReadU8UX(regAdd, 0, 0, data, FIFO_EVENT_SIZE, DUMMY_FIFO); @@ -4261,8 +4254,6 @@ static irqreturn_t fts_event_handler(int irq, void *ts_info) } input_sync(info->input_dev); info->irq_status = false; - if (!info->touch_id) - lpm_disable_for_input(false); #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE wake_up(&info->wait_queue); #endif @@ -5778,7 +5769,6 @@ static void fts_suspend_work(struct work_struct *work) sysfs_notify(&fts_info->fts_touch_dev->kobj, NULL, "touch_suspend_notify"); #endif - lpm_disable_for_input(false); } #ifdef CONFIG_DRM diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c index 4e1bdb5f4795..914e1598dfd6 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -89,7 +89,6 @@ static int32_t nvt_ts_suspend(struct device *dev); static int32_t nvt_ts_resume(struct device *dev); extern int dsi_panel_lockdown_info_read(unsigned char *plockdowninfo); extern void dsi_panel_doubleclick_enable(bool on); -extern void lpm_disable_for_input(bool on); extern int pen_charge_state_notifier_register_client(struct notifier_block *nb); extern int pen_charge_state_notifier_unregister_client(struct notifier_block *nb); @@ -1663,8 +1662,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) } #endif - lpm_disable_for_input(true); - mutex_lock(&ts->lock); if (ts->dev_pm_suspend) { @@ -1672,7 +1669,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) &ts->dev_pm_suspend_completion, msecs_to_jiffies(500)); if (!ret) { NVT_ERR("system(spi) can't finished resuming procedure, skip it\n"); - lpm_disable_for_input(false); goto XFER_ERROR; } } @@ -1738,7 +1734,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) input_id = (uint8_t)(point_data[1] >> 3); nvt_ts_wakeup_gesture_report(input_id, point_data); mutex_unlock(&ts->lock); - lpm_disable_for_input(false); return IRQ_HANDLED; } #endif @@ -1929,7 +1924,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) XFER_ERROR: mutex_unlock(&ts->lock); - lpm_disable_for_input(false); return IRQ_HANDLED; } diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c index 93ba8565e00a..17eb850be3cb 100644 --- a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c @@ -97,7 +97,6 @@ extern void dsi_panel_doubleclick_enable(bool on); #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE static int32_t nvt_check_palm(uint8_t input_id, uint8_t *data); #endif -extern void lpm_disable_for_input(bool on); uint32_t ENG_RST_ADDR = 0x7FFF80; uint32_t SWRST_N8_ADDR = 0; /* read from dtsi */ uint32_t SPI_RD_FAST_ADDR = 0; /* read from dtsi */ @@ -1419,15 +1418,11 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) } #endif mutex_lock(&ts->lock); - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(true); if (ts->dev_pm_suspend) { ret = wait_for_completion_timeout( &ts->dev_pm_suspend_completion, msecs_to_jiffies(500)); if (!ret) { NVT_ERR("system(spi) can't finished resuming procedure, skip it\n"); - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(false); goto XFER_ERROR; } } @@ -1435,8 +1430,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) ret = CTP_SPI_READ(ts->client, point_data, POINT_DATA_LEN + 1); if (ret < 0) { NVT_ERR("CTP_SPI_READ failed.(%d)\n", ret); - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(false); goto XFER_ERROR; } /* @@ -1463,8 +1456,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) } else { nvt_update_firmware(ts->fw_name); } - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(false); goto XFER_ERROR; } #endif /* #if NVT_TOUCH_WDT_RECOVERY */ @@ -1473,8 +1464,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) /* ESD protect by FW handshake */ if (nvt_fw_recovery(point_data)) { nvt_esd_check_enable(true); - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(false); goto XFER_ERROR; } #endif /* #if NVT_TOUCH_ESD_PROTECT */ @@ -1482,8 +1471,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE input_id = (uint8_t)(point_data[1] >> 3); if (nvt_check_palm(input_id, point_data)) { - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(false); goto XFER_ERROR; /* to skip point data parsing */ } #endif @@ -1492,8 +1479,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) if (bTouchIsAwake == 0) { input_id = (uint8_t)(point_data[1] >> 3); nvt_ts_wakeup_gesture_report(input_id, point_data); - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(false); mutex_unlock(&ts->lock); return IRQ_HANDLED; } @@ -1579,8 +1564,6 @@ static irqreturn_t nvt_ts_work_func(int irq, void *data) input_report_key(ts->input_dev, BTN_TOUCH, 0); input_report_key(ts->input_dev, BTN_TOOL_FINGER, 0); - if (ts->debug_flag >= TOUCH_DISABLE_LPM) - lpm_disable_for_input(false); } clear_bit(i, ts->slot_map); } From 54d30d5e09a96f043a90373b541c1969b70b995d Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 11 Oct 2023 15:30:25 +0200 Subject: [PATCH 059/226] drivers: input: touchscreen: xiaomi: Make it compile without xiaomi_touch Change-Id: I05c378d3bf348bfcc96e44fbca96e14cd7f3b677 Signed-off-by: firebird11 --- .../input/touchscreen/xiaomi/fts_521/fts.c | 48 +++---- .../input/touchscreen/xiaomi/fts_521/fts.h | 2 +- .../goodix_driver_gt9886/goodix_ts_core.c | 2 + .../touchscreen/xiaomi/nt36523/nt36xxx.c | 118 +++++++++--------- 4 files changed, 90 insertions(+), 80 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c index d5fa0b5ec0a2..c1d3da688342 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -68,7 +68,9 @@ #ifdef KERNEL_ABOVE_2_6_38 #include #endif +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE #include "../xiaomi/xiaomi_touch.h" +#endif #include "fts.h" #include "fts_lib/ftsCompensation.h" #include "fts_lib/ftsCore.h" @@ -5000,6 +5002,29 @@ static int fts_mode_handler(struct fts_ts_info *info, int force) return res; } +int fts_palm_sensor_cmd(int on) +{ + int ret; + u8 cmd_on[] = { 0xc0, 0x07, 0x01 }; + u8 cmd_off[] = { 0xc0, 0x07, 0x00 }; + + if (on) { + ret = fts_write_dma_safe(cmd_on, sizeof(cmd_on)); + } else { + ret = fts_write_dma_safe(cmd_off, sizeof(cmd_off)); + } + + if (ret < OK) { + logError(1, + "%s %s: write anti mis-touch cmd on...ERROR %08X !\n", + tag, __func__, ret); + return -EINVAL; + } + logError(1, "%s %s %d\n", tag, __func__, on); + + return 0; +} + #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE static struct xiaomi_touch_interface xiaomi_touch_interfaces; @@ -5648,29 +5673,6 @@ int fts_p_sensor_write(int value) return ret; } -int fts_palm_sensor_cmd(int on) -{ - int ret; - u8 cmd_on[] = { 0xc0, 0x07, 0x01 }; - u8 cmd_off[] = { 0xc0, 0x07, 0x00 }; - - if (on) { - ret = fts_write_dma_safe(cmd_on, sizeof(cmd_on)); - } else { - ret = fts_write_dma_safe(cmd_off, sizeof(cmd_off)); - } - - if (ret < OK) { - logError(1, - "%s %s: write anti mis-touch cmd on...ERROR %08X !\n", - tag, __func__, ret); - return -EINVAL; - } - logError(1, "%s %s %d\n", tag, __func__, on); - - return 0; -} - int fts_palm_sensor_write(int value) { int ret = 0; diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.h b/drivers/input/touchscreen/xiaomi/fts_521/fts.h index 0e5522d2e7b8..118d750d37ea 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.h +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.h @@ -388,9 +388,9 @@ bool fts_is_infod(void); void fts_get_pointer(int *touch_flag, int *x, int *y); #endif void fts_restore_regvalues(void); +int fts_palm_sensor_cmd(int input); #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -int fts_palm_sensor_cmd(int input); int fts_p_sensor_cmd(int input); bool fts_touchmode_edgefilter(unsigned int touch_id, int x, int y); #endif diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c index 3ba99ad25043..fa59135c89c3 100644 --- a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c @@ -42,7 +42,9 @@ #define INPUT_TYPE_B_PROTOCOL #endif #include +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE #include "../xiaomi/xiaomi_touch.h" +#endif #include "test_core/test_param_init.h" #define INPUT_EVENT_START 0 diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c index 914e1598dfd6..707cacb27fca 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -2013,6 +2013,62 @@ static void nvt_switch_mode_work(struct work_struct *work) } } +static int disable_pen_input_device(bool disable) +{ + uint8_t buf[8] = { 0 }; + int32_t ret = 0; + + NVT_LOG("++\n"); + if (!bTouchIsAwake || !ts) { + NVT_LOG("touch suspend, stop set pen state %s", + disable ? "DISABLE" : "ENABLE"); + goto nvt_set_pen_enable_out; + } + + msleep(35); + disable = (!(ts->pen_input_dev_enable) || ts->pen_is_charge) ? true : + disable; + + //---set xdata index to EVENT BUF ADDR--- + ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); + if (ret < 0) { + NVT_ERR("Set event buffer index fail!\n"); + goto nvt_set_pen_enable_out; + } + + buf[0] = EVENT_MAP_HOST_CMD; + buf[1] = 0x7B; + buf[2] = !!disable; + ret = CTP_SPI_WRITE(ts->client, buf, 3); + if (ret < 0) { + NVT_ERR("set pen %s failed!\n", disable ? "DISABLE" : "ENABLE"); + goto nvt_set_pen_enable_out; + } + NVT_LOG("pen charge state is %s, %s pen input device\n", + ts->pen_is_charge ? "ENABLE" : "DISABLE", + disable ? "DISABLE" : "ENABLE"); + +nvt_set_pen_enable_out: + NVT_LOG("--\n"); + return ret; +} + +static int nvt_pen_charge_state_notifier_callback(struct notifier_block *self, + unsigned long event, + void *data) +{ + ts->pen_is_charge = !!event; + release_pen_event(); + schedule_work(&ts->pen_charge_state_change_work); + return 0; +} + +static void nvt_pen_charge_state_change_work(struct work_struct *work) +{ + NVT_LOG("pen charge is %s", ts->pen_is_charge ? "ENABLE" : "DISABLE"); + disable_pen_input_device(ts->pen_is_charge); +} + #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE static struct xiaomi_touch_interface xiaomi_touch_interfaces; @@ -2323,62 +2379,6 @@ static void update_touchfeature_value_work(struct work_struct *work) NVT_LOG("exit"); } -static int disable_pen_input_device(bool disable) -{ - uint8_t buf[8] = { 0 }; - int32_t ret = 0; - - NVT_LOG("++\n"); - if (!bTouchIsAwake || !ts) { - NVT_LOG("touch suspend, stop set pen state %s", - disable ? "DISABLE" : "ENABLE"); - goto nvt_set_pen_enable_out; - } - - msleep(35); - disable = (!(ts->pen_input_dev_enable) || ts->pen_is_charge) ? true : - disable; - - //---set xdata index to EVENT BUF ADDR--- - ret = nvt_set_page(ts->mmap->EVENT_BUF_ADDR | EVENT_MAP_HOST_CMD); - if (ret < 0) { - NVT_ERR("Set event buffer index fail!\n"); - goto nvt_set_pen_enable_out; - } - - buf[0] = EVENT_MAP_HOST_CMD; - buf[1] = 0x7B; - buf[2] = !!disable; - ret = CTP_SPI_WRITE(ts->client, buf, 3); - if (ret < 0) { - NVT_ERR("set pen %s failed!\n", disable ? "DISABLE" : "ENABLE"); - goto nvt_set_pen_enable_out; - } - NVT_LOG("pen charge state is %s, %s pen input device\n", - ts->pen_is_charge ? "ENABLE" : "DISABLE", - disable ? "DISABLE" : "ENABLE"); - -nvt_set_pen_enable_out: - NVT_LOG("--\n"); - return ret; -} - -static int nvt_pen_charge_state_notifier_callback(struct notifier_block *self, - unsigned long event, - void *data) -{ - ts->pen_is_charge = !!event; - release_pen_event(); - schedule_work(&ts->pen_charge_state_change_work); - return 0; -} - -static void nvt_pen_charge_state_change_work(struct work_struct *work) -{ - NVT_LOG("pen charge is %s", ts->pen_is_charge ? "ENABLE" : "DISABLE"); - disable_pen_input_device(ts->pen_is_charge); -} - static int nvt_set_cur_value(int nvt_mode, int nvt_value) { if (nvt_mode >= Touch_Mode_NUM && nvt_mode < 0) { @@ -3231,6 +3231,7 @@ static int32_t nvt_ts_probe(struct spi_device *client) } INIT_WORK(&ts->resume_work, nvt_resume_work); INIT_WORK(&ts->suspend_work, nvt_suspend_work); +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE ts->set_touchfeature_wq = create_singlethread_workqueue("nvt-set-touchfeature-queue"); if (!ts->set_touchfeature_wq) { @@ -3239,6 +3240,7 @@ static int32_t nvt_ts_probe(struct spi_device *client) goto err_create_set_touchfeature_work_queue; } INIT_WORK(&ts->set_touchfeature_work, update_touchfeature_value_work); +#endif ts->pen_charge_state_notifier.notifier_call = nvt_pen_charge_state_notifier_callback; @@ -3321,8 +3323,10 @@ static int32_t nvt_ts_probe(struct spi_device *client) &ts->pen_charge_state_notifier)) NVT_ERR("Error occurred while unregistering pen charge state notifier.\n"); err_register_pen_charge_state_failed: +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE destroy_workqueue(ts->set_touchfeature_wq); err_create_set_touchfeature_work_queue: +#endif destroy_workqueue(ts->event_wq); err_alloc_work_thread_failed: #ifndef NVT_SAVE_TESTDATA_IN_FILE @@ -3490,8 +3494,10 @@ static int32_t nvt_ts_remove(struct spi_device *client) spi_set_drvdata(client, NULL); +#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE if (ts->set_touchfeature_wq) destroy_workqueue(ts->set_touchfeature_wq); +#endif if (ts) { kfree(ts); From d585a109032b760409f819f7fc16d3231a9e0aee Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 16 Apr 2024 03:39:57 +0200 Subject: [PATCH 060/226] drivers: input: touchscreen: xiaomi: nt36523: Fix function declaration args Change-Id: Ieea79fa899abf340d1ea5827e0b660e42559d2ad Signed-off-by: firebird11 --- drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c index 707cacb27fca..d9dc28329656 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -1113,7 +1113,7 @@ void nvt_ts_wakeup_gesture_report(uint8_t gesture_id, uint8_t *data) } #endif -static void release_pen_event() +static void release_pen_event(void) { if (ts && ts->pen_input_dev) { input_report_abs(ts->pen_input_dev, ABS_X, 0); From d0f8caf706b6f16c43e529a3d2619b67083fc243 Mon Sep 17 00:00:00 2001 From: Yumi Yukimura Date: Wed, 7 Feb 2024 23:57:30 +0800 Subject: [PATCH 061/226] drivers: input: touchscreen: xiaomi: fts_521: Fix strict-prototypes error Change-Id: Iddba34c831a691f4b6f5e3bb8a2ddf178f89f965 Signed-off-by: firebird11 --- drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c index 9c24d52936e2..4e328b91483e 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_lib/ftsIO.c @@ -101,7 +101,7 @@ int changeSAD(u8 sad) * Retrieve the pointer to the device struct of the IC * @return a the device struct pointer if client was previously set or NULL in all the other cases */ -struct device *getDev() +struct device *getDev(void) { if (client != NULL) return &(getClient()->dev); @@ -114,7 +114,7 @@ struct device *getDev() * Retrieve the pointer of the i2c_client struct representing the IC as i2c slave * @return client if it was previously set or NULL in all the other cases */ -struct i2c_client *getClient() +struct i2c_client *getClient(void) { if (client != NULL) return (struct i2c_client *)client; @@ -126,7 +126,7 @@ struct i2c_client *getClient() * Retrieve the pointer of the spi_device struct representing the IC as spi slave * @return client if it was previously set or NULL in all the other cases */ -struct spi_device *getClient() +struct spi_device *getClient(void) { if (client != NULL) return (struct spi_device *)client; From 8dc4138b3649baee213f3db0b14ad0be789c627d Mon Sep 17 00:00:00 2001 From: Yumi Yukimura Date: Thu, 8 Feb 2024 15:22:30 +0800 Subject: [PATCH 062/226] drivers: input: touchscreen: xiaomi: fts_521: Fix sscanf() buffer overflow Change-Id: I20dcdc3e0242ae61b0bce256575c3c9bc315f810 Signed-off-by: firebird11 --- drivers/input/touchscreen/xiaomi/fts_521/fts.c | 2 +- drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c index c1d3da688342..421d31f599e3 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -225,7 +225,7 @@ static ssize_t fts_fwupdate_store(struct device *dev, mode[1] = 1; /* reading out firmware upgrade parameters */ - sscanf(buf, "%100s %d %d", path, &mode[0], &mode[1]); + sscanf(buf, "%99s %d %d", path, &mode[0], &mode[1]); logError(1, "%s fts_fwupdate_store: mode = %s \n", tag, path); ret = flashProcedure(path, mode[0], mode[1]); diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c b/drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c index 2b1b5fa8dd0c..5ce24e9f52fe 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts_proc.c @@ -466,7 +466,7 @@ static ssize_t fts_driver_test_write(struct file *file, const char __user *buf, case CMD_GETLIMITSFILE: if (count - 2 - 1 > 1) { numberParam = 2; - sscanf(p, "%100s", path); + sscanf(p, "%99s", path); } break; From c685e85d7fc0bf2d591820f2f8cb104cb43e38d7 Mon Sep 17 00:00:00 2001 From: dianlujitao Date: Wed, 19 Feb 2020 16:48:25 +0800 Subject: [PATCH 063/226] drivers: input: touchscreen: Add an interface to expose TP features to userspace * Needs to implement and register ops from TP driver * Access them via /sys/touchpanel/* Change-Id: I2baa61c6055ca6f6207ac0d6f627fe03048ccfb6 Signed-off-by: firebird11 --- drivers/input/touchscreen/Kconfig | 9 +++++++++ drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/tp_common.c | 26 ++++++++++++++++++++++++++ include/linux/input/tp_common.h | 13 +++++++++++++ 4 files changed, 49 insertions(+) create mode 100644 drivers/input/touchscreen/tp_common.c create mode 100644 include/linux/input/tp_common.h diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 7f85cd5deb14..580d995e3a19 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -1300,4 +1300,13 @@ source "drivers/input/touchscreen/focaltech_touch/Kconfig" source "drivers/input/touchscreen/xiaomi/Kconfig" +config TOUCHSCREEN_COMMON + bool "Common touchscreen interface to interact with userspace" + default y + help + Say Y here if you want to control touchpanel features via + /sys/touchpanel. + + If unsure, say N. + endif diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 17aa95412a5e..86bc6541e70a 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -113,3 +113,4 @@ obj-$(CONFIG_TOUCHSCREEN_IQS5XX) += iqs5xx.o obj-$(CONFIG_TOUCHSCREEN_ST) += st/ obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_touch/ obj-y += xiaomi/ +obj-$(CONFIG_TOUCHSCREEN_COMMON) += tp_common.o diff --git a/drivers/input/touchscreen/tp_common.c b/drivers/input/touchscreen/tp_common.c new file mode 100644 index 000000000000..d3a5498457b7 --- /dev/null +++ b/drivers/input/touchscreen/tp_common.c @@ -0,0 +1,26 @@ +#include + +struct kobject *touchpanel_kobj; + +#define TS_ENABLE_FOPS(type) \ + int tp_common_set_##type##_ops(struct tp_common_ops *ops) \ + { \ + static struct kobj_attribute kattr = \ + __ATTR(type, (S_IWUSR | S_IRUGO), NULL, NULL); \ + kattr.show = ops->show; \ + kattr.store = ops->store; \ + return sysfs_create_file(touchpanel_kobj, &kattr.attr); \ + } + +TS_ENABLE_FOPS(double_tap) +TS_ENABLE_FOPS(fod_status) + +static int __init tp_common_init(void) +{ + touchpanel_kobj = kobject_create_and_add("touchpanel", NULL); + if (!touchpanel_kobj) + return -ENOMEM; + + return 0; +} +core_initcall(tp_common_init); diff --git a/include/linux/input/tp_common.h b/include/linux/input/tp_common.h new file mode 100644 index 000000000000..0428a046f9fd --- /dev/null +++ b/include/linux/input/tp_common.h @@ -0,0 +1,13 @@ +#include + +extern struct kobject *touchpanel_kobj; + +struct tp_common_ops { + ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr, + char *buf); + ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count); +}; + +int tp_common_set_double_tap_ops(struct tp_common_ops *ops); +int tp_common_set_fod_status_ops(struct tp_common_ops *ops); From 53316130ab4227e1b68b8105149f450c42bdda50 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 11 Jun 2024 22:37:40 +0200 Subject: [PATCH 064/226] drivers: input: touchscreen: tp_common: Add pen node Change-Id: I5d4046dba7a13d58cd78d2fafdc89e57e4747873 Signed-off-by: firebird11 --- drivers/input/touchscreen/tp_common.c | 1 + include/linux/input/tp_common.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/input/touchscreen/tp_common.c b/drivers/input/touchscreen/tp_common.c index d3a5498457b7..404994c4c865 100644 --- a/drivers/input/touchscreen/tp_common.c +++ b/drivers/input/touchscreen/tp_common.c @@ -14,6 +14,7 @@ struct kobject *touchpanel_kobj; TS_ENABLE_FOPS(double_tap) TS_ENABLE_FOPS(fod_status) +TS_ENABLE_FOPS(pen) static int __init tp_common_init(void) { diff --git a/include/linux/input/tp_common.h b/include/linux/input/tp_common.h index 0428a046f9fd..9cb74e80c9ed 100644 --- a/include/linux/input/tp_common.h +++ b/include/linux/input/tp_common.h @@ -11,3 +11,4 @@ struct tp_common_ops { int tp_common_set_double_tap_ops(struct tp_common_ops *ops); int tp_common_set_fod_status_ops(struct tp_common_ops *ops); +int tp_common_set_pen_ops(struct tp_common_ops *ops); From c8b9396535a04b0ca39f6eff36e9ea9de46fcdd1 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 11 Oct 2023 15:40:02 +0200 Subject: [PATCH 065/226] drivers: input: touchscreen: xiaomi: fts_521: Implement double_tap node Change-Id: I219ef6b0305649690594e5e053a0c4ce4b719ef6 Signed-off-by: firebird11 --- .../input/touchscreen/xiaomi/fts_521/fts.c | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c index 421d31f599e3..9854ee503248 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -83,6 +83,10 @@ #include "fts_lib/ftsTime.h" #include "fts_lib/ftsTool.h" +#ifdef CONFIG_TOUCHSCREEN_COMMON +#include +#endif + /** * Event handler installer helpers */ @@ -2726,6 +2730,34 @@ static ssize_t fts_touchgame_show(struct device *dev, } #endif +#if defined(CONFIG_TOUCHSCREEN_COMMON) && defined(GESTURE_MODE) +static ssize_t double_tap_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", fts_info->gesture_enabled); +} + +static ssize_t double_tap_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, + size_t count) +{ + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + fts_info->gesture_enabled = !!val; + + return count; +} + +static struct tp_common_ops double_tap_ops = { + .show = double_tap_show, + .store = double_tap_store, +}; +#endif + #ifdef CONFIG_SECURE_TOUCH static void fts_secure_touch_notify(struct fts_ts_info *info) { @@ -7335,6 +7367,16 @@ static int fts_probe(struct spi_device *client) msecs_to_jiffies(EXP_FN_WORK_DELAY_MS)); #endif +#ifdef CONFIG_TOUCHSCREEN_COMMON +#ifdef GESTURE_MODE + retval = tp_common_set_double_tap_ops(&double_tap_ops); + if (retval < 0) { + logError(1, "%s %s: Failed to create double_tap node err=%d\n", + tag, __func__, retval); + } +#endif +#endif + logError(1, "%s Probe Finished! \n", tag); return OK; #ifdef CONFIG_FTS_TOUCH_COUNT_DUMP From 822bd48c4a85c3b6f95318772bd7fa03684a33c5 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 11 Oct 2023 15:47:49 +0200 Subject: [PATCH 066/226] drivers: input: touchscreen: xiaomI: fts_521: Give fod_status ops to tp_common Change-Id: Ic55e03042f934989df4a484969ff174db2a06df5 Signed-off-by: firebird11 --- .../input/touchscreen/xiaomi/fts_521/fts.c | 56 ++++++++++--------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/fts_521/fts.c b/drivers/input/touchscreen/xiaomi/fts_521/fts.c index 9854ee503248..753c063bac34 100644 --- a/drivers/input/touchscreen/xiaomi/fts_521/fts.c +++ b/drivers/input/touchscreen/xiaomi/fts_521/fts.c @@ -2581,31 +2581,28 @@ static ssize_t fts_grip_area_store(struct device *dev, } return count; } -#ifdef CONFIG_FTS_FOD_AREA_REPORT -static ssize_t fts_fod_status_show(struct device *dev, - struct device_attribute *attr, char *buf) +#if defined(CONFIG_TOUCHSCREEN_COMMON) && defined(CONFIG_FTS_FOD_AREA_REPORT) +static ssize_t fts_fod_status_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) { - struct fts_ts_info *info = dev_get_drvdata(dev); - - return snprintf(buf, TSP_BUF_SIZE, "%d\n", info->fod_status); + return snprintf(buf, TSP_BUF_SIZE, "%d\n", fts_info->fod_status); } -static ssize_t fts_fod_status_store(struct device *dev, - struct device_attribute *attr, +static ssize_t fts_fod_status_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) { - struct fts_ts_info *info = dev_get_drvdata(dev); int res = 0; u8 gesture_cmd[6] = { 0xA2, 0x03, 0x20, 0x00, 0x00, 0x01 }; u8 single_only_cmd[4] = { 0xC0, 0x02, 0x00, 0x00 }; u8 single_double_cmd[4] = { 0xC0, 0x02, 0x01, 0x1E }; logError(1, " %s %s buf:%c,count:%zu\n", tag, __func__, buf[0], count); - sscanf(buf, "%u", &info->fod_status); + sscanf(buf, "%u", &fts_info->fod_status); - mutex_lock(&info->fod_mutex); - if (info->fod_status) { - if (info->fod_status_set) { + mutex_lock(&fts_info->fod_mutex); + if (fts_info->fod_status) { + if (fts_info->fod_status_set) { logError(1, " %s %s fod status has set\n", tag, __func__); } else { @@ -2617,13 +2614,13 @@ static ssize_t fts_fod_status_store(struct device *dev, "%s %s: enter gesture and longpress failed! ERROR %08X recovery in senseOff...\n", tag, __func__, res); - if (info->sensor_sleep) { + if (fts_info->sensor_sleep) { logError( 1, " %s %s set fod cmd in sensor off status\n", tag, __func__); res = setScanMode(SCAN_MODE_LOW_POWER, 0); - if (info->gesture_enabled == 1) { + if (fts_info->gesture_enabled == 1) { res = fts_write_dma_safe( single_double_cmd, ARRAY_SIZE(single_double_cmd)); @@ -2644,15 +2641,22 @@ static ssize_t fts_fod_status_store(struct device *dev, } } fts_enableInterrupt(); - info->fod_status_set = true; + fts_info->fod_status_set = true; } } - mutex_unlock(&info->fod_mutex); + mutex_unlock(&fts_info->fod_mutex); logError(1, " %s %s end\n", tag, __func__); return count; } +static struct tp_common_ops fod_status_ops = { + .show = fts_fod_status_show, + .store = fts_fod_status_store, +}; +#endif + +#ifdef CONFIG_FTS_FOD_AREA_REPORT static ssize_t fts_fod_test_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) @@ -3118,9 +3122,6 @@ static DEVICE_ATTR(touch_suspend_notify, (S_IRUGO | S_IRGRP), fts_touch_suspend_notify_show, NULL); #endif #ifdef CONFIG_FTS_FOD_AREA_REPORT -static DEVICE_ATTR(fod_status, (S_IRUGO | S_IWUSR | S_IWGRP), - fts_fod_status_show, fts_fod_status_store); - static DEVICE_ATTR(fod_test, (S_IRUGO | S_IWUSR | S_IWGRP), NULL, fts_fod_test_store); #endif @@ -7314,13 +7315,6 @@ static int fts_probe(struct spi_device *client) #ifdef CONFIG_FTS_FOD_AREA_REPORT mutex_init(&(info->fod_mutex)); - error = sysfs_create_file(&info->fts_touch_dev->kobj, - &dev_attr_fod_status.attr); - if (error) { - logError(1, - "%s ERROR: Failed to create fod_status sysfs group!\n", - tag); - } error = sysfs_create_file(&info->fts_touch_dev->kobj, &dev_attr_fod_test.attr); if (error) { @@ -7377,6 +7371,14 @@ static int fts_probe(struct spi_device *client) #endif #endif +#if defined(CONFIG_TOUCHSCREEN_COMMON) && defined(CONFIG_FTS_FOD_AREA_REPORT) + retval = tp_common_set_fod_status_ops(&fod_status_ops); + if (retval < 0) { + logError(1, "%s %s: Failed to create fod_status node err=%d\n", + tag, __func__, retval); + } +#endif + logError(1, "%s Probe Finished! \n", tag); return OK; #ifdef CONFIG_FTS_TOUCH_COUNT_DUMP From c75b2ce8ea44fe385e3396a9b995a0f944c7cff2 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 11 Oct 2023 15:50:51 +0200 Subject: [PATCH 067/226] drivers: input: touchscreen: xiaomi: goodix_driver_gt9886: Implement double_tap node Change-Id: I128b90427ae7399a6d4b98b9f89b10a5c74deece Signed-off-by: firebird11 --- .../goodix_driver_gt9886/goodix_ts_core.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c index fa59135c89c3..6e5a5ec29db7 100644 --- a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c @@ -47,6 +47,10 @@ #endif #include "test_core/test_param_init.h" +#ifdef CONFIG_TOUCHSCREEN_COMMON +#include +#endif + #define INPUT_EVENT_START 0 #define INPUT_EVENT_SENSITIVE_MODE_OFF 0 #define INPUT_EVENT_SENSITIVE_MODE_ON 1 @@ -741,6 +745,45 @@ static ssize_t goodix_ts_tp_get_testcfg_show(struct device *dev, ts_info("test finish!"); return ret; } + +#ifdef CONFIG_TOUCHSCREEN_COMMON +static ssize_t double_tap_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", goodix_core_data->double_wakeup); +} + +static ssize_t double_tap_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, + size_t count) +{ + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + goodix_core_data->double_wakeup = !!val; + if (goodix_core_data->fod_status == -1 || + goodix_core_data->fod_status == 100) + goodix_core_data->gesture_enabled = + goodix_core_data->double_wakeup | + goodix_core_data->aod_status; + else + goodix_core_data->gesture_enabled = + goodix_core_data->double_wakeup | + goodix_core_data->fod_status | + goodix_core_data->aod_status; + + return count; +} + +static struct tp_common_ops double_tap_ops = { + .show = double_tap_show, + .store = double_tap_store, +}; +#endif + static DEVICE_ATTR(extmod_info, S_IRUGO, goodix_ts_extmod_show, NULL); static DEVICE_ATTR(driver_info, S_IRUGO, goodix_ts_driver_info_show, NULL); static DEVICE_ATTR(chip_info, S_IRUGO, goodix_ts_chip_info_show, NULL); @@ -2717,6 +2760,13 @@ static int goodix_ts_probe(struct platform_device *pdev) /*create sysfs files*/ goodix_ts_sysfs_init(core_data); +#ifdef CONFIG_TOUCHSCREEN_COMMON + r = tp_common_set_double_tap_ops(&double_tap_ops); + if (r < 0) { + ts_err("Failed to create double_tap node err=%d\n", r); + } +#endif + r = ts_device->hw_ops->reset(ts_device); if (r < 0) { pr_err("goodix_hw_ops->reset fail \n"); From 46e368082c55ba163e00f97cfbfbf9fdc8e357d4 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 11 Oct 2023 15:53:20 +0200 Subject: [PATCH 068/226] drivers: input: touchscreen: xiaomi: goodix_driver_gt9886: Give fod_status ops to tp_common Change-Id: I785bfd8cb1c89742c55bdb1f82933289545214ed Signed-off-by: firebird11 --- .../goodix_driver_gt9886/goodix_ts_core.c | 44 +++++++++---------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c index 6e5a5ec29db7..b8c7ddb5ce41 100644 --- a/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c +++ b/drivers/input/touchscreen/xiaomi/goodix_driver_gt9886/goodix_ts_core.c @@ -1332,32 +1332,31 @@ static ssize_t gtp_fod_test_store(struct device *dev, return count; } -static ssize_t gtp_fod_status_show(struct device *dev, - struct device_attribute *attr, char *buf) +#ifdef CONFIG_TOUCHSCREEN_COMMON +static ssize_t gtp_fod_status_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) { - struct goodix_ts_core *core_data = dev_get_drvdata(dev); - - return snprintf(buf, 10, "%d\n", core_data->fod_status); + return snprintf(buf, 10, "%d\n", goodix_core_data->fod_status); } -static ssize_t gtp_fod_status_store(struct device *dev, - struct device_attribute *attr, +static ssize_t gtp_fod_status_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) { - struct goodix_ts_core *core_data = dev_get_drvdata(dev); - //struct goodix_ts_event *ts_event = &core_data->ts_event; - ts_info("buf:%s, count:%zu\n", buf, count); - sscanf(buf, "%u", &core_data->fod_status); + sscanf(buf, "%u", &goodix_core_data->fod_status); - //goodix_ts_input_report(core_data->input_dev,&ts_event->event_data.touch_data); - core_data->gesture_enabled = core_data->double_wakeup | - core_data->fod_status; - goodix_check_gesture_stat(!!core_data->fod_status); + goodix_core_data->gesture_enabled = goodix_core_data->double_wakeup | + goodix_core_data->fod_status; + goodix_check_gesture_stat(!!goodix_core_data->fod_status); return count; } -static DEVICE_ATTR(fod_status, (S_IRUGO | S_IWUSR | S_IWGRP), - gtp_fod_status_show, gtp_fod_status_store); + +static struct tp_common_ops fod_status_ops = { + .show = gtp_fod_status_show, + .store = gtp_fod_status_store, +}; +#endif static DEVICE_ATTR(fod_test, (S_IRUGO | S_IWUSR | S_IWGRP), NULL, gtp_fod_test_store); @@ -2765,6 +2764,11 @@ static int goodix_ts_probe(struct platform_device *pdev) if (r < 0) { ts_err("Failed to create double_tap node err=%d\n", r); } + + r = tp_common_set_fod_status_ops(&fod_status_ops); + if (r < 0) { + ts_err("Failed to create fod_status node err=%d\n", r); + } #endif r = ts_device->hw_ops->reset(ts_device); @@ -2849,12 +2853,6 @@ static int goodix_ts_probe(struct platform_device *pdev) goto out; } - if (sysfs_create_file(&core_data->gtp_touch_dev->kobj, - &dev_attr_fod_status.attr)) { - ts_err("Failed to create fod_status sysfs group!\n"); - goto out; - } - if (sysfs_create_file(&core_data->gtp_touch_dev->kobj, &dev_attr_fod_test.attr)) { ts_err("Failed to create fod_test sysfs group!"); From 4b5f7487fc2d15261a76109d6b20b90c93102f27 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 28 Jan 2024 16:22:06 +0100 Subject: [PATCH 069/226] drivers: input: touchscreen: xiaomi: nt36523: Implement double_tap node Change-Id: Icaa46478fac2293a9c89a464f9975c679d7b3f4f Signed-off-by: firebird11 --- .../touchscreen/xiaomi/nt36523/nt36xxx.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c index d9dc28329656..592164fd6146 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -48,6 +48,10 @@ #include "../xiaomi/xiaomi_touch.h" #endif +#if WAKEUP_GESTURE && defined(CONFIG_TOUCHSCREEN_COMMON) +#include +#endif + #if NVT_TOUCH_ESD_PROTECT static struct delayed_work nvt_esd_check_work; static struct workqueue_struct *nvt_esd_check_wq; @@ -119,6 +123,33 @@ const uint16_t gesture_key_array[] = { KEY_POWER, //GESTURE_SLIDE_RIGHT KEY_WAKEUP, //GESTURE_PEN_ONE_CLICK }; + +#ifdef CONFIG_TOUCHSCREEN_COMMON +static ssize_t double_tap_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", ts->db_wakeup); +} + +static ssize_t double_tap_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, + size_t count) +{ + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + ts->db_wakeup = !!val; + return count; +} + +static struct tp_common_ops double_tap_ops = { + .show = double_tap_show, + .store = double_tap_store, +}; +#endif #endif #ifdef CONFIG_MTK_SPI @@ -3024,6 +3055,14 @@ static int32_t nvt_ts_probe(struct spi_device *client) input_set_capability(ts->input_dev, EV_KEY, gesture_key_array[retry]); } + +#ifdef CONFIG_TOUCHSCREEN_COMMON + ret = tp_common_set_double_tap_ops(&double_tap_ops); + if (ret < 0) { + NVT_ERR("%s: Failed to create double_tap node err=%d\n", + __func__, ret); + } +#endif #endif sprintf(ts->phys, "input/ts"); From 4f0ba8e3b88639d5c64eab33ed8d7ef14823d9fe Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 11 Jun 2024 23:25:40 +0200 Subject: [PATCH 070/226] drivers: input: touchscreen: xiaomi: nt36523: Implement pen node Change-Id: I7dd9174f7e2d9bfd5e1f3d2a43ed4df23f92fa00 Signed-off-by: firebird11 --- .../touchscreen/xiaomi/nt36523/nt36xxx.c | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c index 592164fd6146..a8b45aae3e6b 100644 --- a/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36523/nt36xxx.c @@ -2100,6 +2100,35 @@ static void nvt_pen_charge_state_change_work(struct work_struct *work) disable_pen_input_device(ts->pen_is_charge); } +#ifdef CONFIG_TOUCHSCREEN_COMMON +static ssize_t pen_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + return sprintf(buf, "%d\n", ts->pen_input_dev_enable); +} + +static ssize_t pen_store(struct kobject *kobj, struct kobj_attribute *attr, + const char *buf, size_t count) +{ + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + ts->pen_input_dev_enable = !!val; + disable_pen_input_device(!ts->pen_input_dev_enable); + release_pen_event(); + + return count; +} + +static struct tp_common_ops pen_ops = { + .show = pen_show, + .store = pen_store, +}; +#endif + #ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE static struct xiaomi_touch_interface xiaomi_touch_interfaces; @@ -3134,6 +3163,14 @@ static int32_t nvt_ts_probe(struct spi_device *client) ts->pen_input_dev->name, ret); goto err_pen_input_register_device_failed; } + +#ifdef CONFIG_TOUCHSCREEN_COMMON + ret = tp_common_set_pen_ops(&pen_ops); + if (ret < 0) { + NVT_ERR("%s: Failed to create pen node err=%d\n", + __func__, ret); + } +#endif } /* if (ts->pen_support) */ //---set int-pin & request irq--- From e1a481afdfc44e39ba32ce8d737adb36d2ed2d67 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 22:36:30 +0100 Subject: [PATCH 071/226] drivers: input: touchscreen: xiaomi: nt36672c: Implement double_tap node Change-Id: I1ff68f35ed5b0c21f993ef339ffc3df111c60e74 Signed-off-by: firebird11 --- .../touchscreen/xiaomi/nt36672c/nt36xxx.c | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c index 17eb850be3cb..197812c16fe1 100644 --- a/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c +++ b/drivers/input/touchscreen/xiaomi/nt36672c/nt36xxx.c @@ -53,6 +53,10 @@ #include "../xiaomi/xiaomi_touch.h" #endif +#if WAKEUP_GESTURE && defined(CONFIG_TOUCHSCREEN_COMMON) +#include +#endif + #if NVT_TOUCH_ESD_PROTECT static struct delayed_work nvt_esd_check_work; static struct workqueue_struct *nvt_esd_check_wq; @@ -975,6 +979,31 @@ void nvt_ts_wakeup_gesture_report(uint8_t gesture_id, uint8_t *data) break; } } + +#ifdef CONFIG_TOUCHSCREEN_COMMON +static ssize_t double_tap_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", ts->db_wakeup); +} + +static ssize_t double_tap_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, + size_t count) +{ + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + ts->db_wakeup = !!val; + return count; +} + +static struct tp_common_ops double_tap_ops = { .show = double_tap_show, + .store = double_tap_store }; +#endif #endif /******************************************************* @@ -2521,6 +2550,14 @@ static int32_t nvt_ts_probe(struct platform_device *pdev) #if WAKEUP_GESTURE input_set_capability(ts->input_dev, EV_KEY, KEY_WAKEUP); + +#ifdef CONFIG_TOUCHSCREEN_COMMON + ret = tp_common_set_double_tap_ops(&double_tap_ops); + if (ret < 0) { + NVT_ERR("%s: Failed to create double_tap node err=%d\n", + __func__, ret); + } +#endif #endif sprintf(ts->phys, "input/ts"); From 3744ffaec16be583bbd8f49d37f5e06f739ea842 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:18:37 +0200 Subject: [PATCH 072/226] drivers: leds: Import Xiaomi changes Change-Id: I12973f2400bd2abbd9e3b9333d4a7be1ec0b7a4b Signed-off-by: firebird11 --- drivers/leds/leds-qpnp-flash-v2.c | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/leds/leds-qpnp-flash-v2.c b/drivers/leds/leds-qpnp-flash-v2.c index 719b5fe07bd1..6191e148c152 100644 --- a/drivers/leds/leds-qpnp-flash-v2.c +++ b/drivers/leds/leds-qpnp-flash-v2.c @@ -354,6 +354,13 @@ static int max_ires_curr_ma_table[MAX_IRES_LEVELS] = { FLASH_LED_IRES7P5_MAX_CURR_MA, FLASH_LED_IRES5P0_MAX_CURR_MA }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +struct flash_node_data *g_torch_0 = NULL; +struct flash_node_data *g_torch_1 = NULL; +struct flash_switch_data *g_switch_0 = NULL; +struct flash_switch_data *g_switch_1 = NULL; +#endif + static inline int get_current_reg_code(int target_curr_ma, int ires_ua) { if (!ires_ua || !target_curr_ma || (target_curr_ma < (ires_ua / 1000))) @@ -1751,6 +1758,11 @@ static void qpnp_flash_led_brightness_set(struct led_classdev *led_cdev, strlen("led:torch"))) { fnode = container_of(led_cdev, struct flash_node_data, cdev); led = dev_get_drvdata(&fnode->pdev->dev); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } else if (!strncmp(led_cdev->name, "flashlight", strlen("flashlight"))) { + fnode = container_of(led_cdev, struct flash_node_data, cdev); + led = dev_get_drvdata(&fnode->pdev->dev); +#endif } if (!led) { @@ -1764,7 +1776,20 @@ static void qpnp_flash_led_brightness_set(struct led_classdev *led_cdev, if (rc < 0) pr_err("Failed to set flash LED switch rc=%d\n", rc); } else if (fnode) { +#ifndef CONFIG_MACH_XIAOMI_SM8150 qpnp_flash_led_node_set(fnode, value); +#else + if (!strncmp(led_cdev->name, "flashlight", strlen("flashlight"))) { + if (g_torch_0 && g_torch_1 && g_switch_0 && g_switch_1) { + qpnp_flash_led_node_set(g_torch_0, value); + qpnp_flash_led_node_set(g_torch_1, value); + qpnp_flash_led_switch_set(g_switch_0, value > 0); + qpnp_flash_led_switch_set(g_switch_1, value > 0); + } + } else { + qpnp_flash_led_node_set(fnode, value); + } +#endif } spin_unlock(&led->lock); @@ -2667,6 +2692,10 @@ static int qpnp_flash_led_probe(struct platform_device *pdev) const char *temp_string; unsigned int base; int rc, i = 0, j = 0; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct flash_node_data *fnode; + struct flash_switch_data *snode; +#endif node = pdev->dev.of_node; if (!node) { @@ -2759,12 +2788,28 @@ static int qpnp_flash_led_probe(struct platform_device *pdev) i, rc); goto error_led_register; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + fnode = &led->fnode[i]; + if (!strcmp("led:torch_0", fnode->cdev.name)) { + g_torch_0 = fnode; + } else if (!strcmp("led:torch_1", fnode->cdev.name)){ + g_torch_1 = fnode; + } +#endif i++; } if (!strcmp("switch", temp_string)) { rc = qpnp_flash_led_parse_and_register_switch(led, &led->snode[j], temp); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + snode = &led->snode[j]; + if (!strcmp("led:switch_0", snode->cdev.name)) { + g_switch_0 = snode; + } else if (!strcmp("led:switch_1", snode->cdev.name)) { + g_switch_1 = snode; + } +#endif if (rc < 0) { pr_err("Unable to parse and register switch node, rc=%d\n", rc); From 608b56e2d7dee5e5f36eb62077d80dba50acf01b Mon Sep 17 00:00:00 2001 From: UtsavBalar1231 Date: Thu, 3 Dec 2020 21:33:14 +0530 Subject: [PATCH 073/226] drivers: media: platform: msm: camera: Import Xiaomi changes Co-authored-by: Sebastiano Barezzi Change-Id: I20a82c9e77f92405d77a0d16621ce12209dfd194 Signed-off-by: firebird11 --- drivers/media/platform/msm/Kconfig | 8 + .../camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 19 + .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 25 + .../msm/camera/cam_isp/cam_isp_context.c | 40 ++ .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 60 ++ .../isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c | 4 + .../cam_actuator/cam_actuator_core.c | 207 +++++++ .../cam_sensor_module/cam_cci/cam_cci_core.c | 6 +- .../cam_csiphy/cam_csiphy_soc.c | 9 + .../cam_csiphy/include/cam_csiphy_1_1_hwreg.h | 345 +++++++---- .../include/cam_csiphy_1_1_hwreg_vayu.h | 585 ++++++++++++++++++ .../cam_eeprom/cam_eeprom_core.c | 8 + .../cam_sensor_module/cam_ois/cam_ois_core.c | 87 +++ .../cam_sensor/cam_sensor_core.c | 112 ++++ .../msm/camera/cam_sync/cam_sync_private.h | 4 + .../msm/camera/cam_sync/cam_sync_util.c | 10 + .../msm/camera/cam_utils/cam_soc_util.h | 4 + include/uapi/media/cam_defs.h | 5 + include/uapi/media/cam_req_mgr.h | 4 + include/uapi/media/cam_sensor.h | 3 + 20 files changed, 1431 insertions(+), 114 deletions(-) create mode 100644 drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg_vayu.h diff --git a/drivers/media/platform/msm/Kconfig b/drivers/media/platform/msm/Kconfig index aba3e316e8b6..6a704e37ae9b 100644 --- a/drivers/media/platform/msm/Kconfig +++ b/drivers/media/platform/msm/Kconfig @@ -57,6 +57,14 @@ if MSMB_CAMERA source "drivers/media/platform/msm/camera_v2/Kconfig" endif # MSMB_CAMERA +config USE_ROHM_BU64753 + bool "use ROHM BU64753 acculator" + default n + +config VCM_AK7374 + bool "use ak7374 vcm" + default n + source "drivers/media/platform/msm/vidc_3x/Kconfig" source "drivers/media/platform/msm/vidc/Kconfig" source "drivers/media/platform/msm/sde/Kconfig" diff --git a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index 2caf6d0a844d..60e1c9793f94 100644 --- a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -880,7 +880,9 @@ static int cam_fd_mgr_util_submit_frame(void *priv, void *data) trace_cam_submit_to_hw("FD", frame_req->request_id); list_del_init(&frame_req->list); +#ifndef CONFIG_MACH_XIAOMI_NABU mutex_unlock(&hw_mgr->frame_req_mutex); +#endif if (hw_device->hw_intf->hw_ops.start) { start_args.hw_ctx = hw_ctx; @@ -896,20 +898,30 @@ static int cam_fd_mgr_util_submit_frame(void *priv, void *data) if (rc) { CAM_ERR(CAM_FD, "Failed in HW Start %d", rc); mutex_unlock(&hw_device->lock); +#ifdef CONFIG_MACH_XIAOMI_NABU + mutex_unlock(&hw_mgr->frame_req_mutex); +#endif goto put_req_into_free_list; } } else { CAM_ERR(CAM_FD, "Invalid hw_ops.start"); mutex_unlock(&hw_device->lock); rc = -EPERM; +#ifdef CONFIG_MACH_XIAOMI_NABU + mutex_unlock(&hw_mgr->frame_req_mutex); +#endif goto put_req_into_free_list; } hw_device->ready_to_process = false; hw_device->cur_hw_ctx = hw_ctx; hw_device->req_id = frame_req->request_id; +#ifdef CONFIG_MACH_XIAOMI_NABU + list_add_tail(&frame_req->list, &hw_mgr->frame_processing_list); +#endif mutex_unlock(&hw_device->lock); +#ifndef CONFIG_MACH_XIAOMI_NABU cam_common_util_get_curr_timestamp(&frame_req->submit_timestamp); rc = cam_fd_mgr_util_put_frame_req( &hw_mgr->frame_processing_list, &frame_req); @@ -918,9 +930,15 @@ static int cam_fd_mgr_util_submit_frame(void *priv, void *data) "Failed in putting frame req in processing list"); goto stop_unlock; } +#endif + +#ifdef CONFIG_MACH_XIAOMI_NABU + mutex_unlock(&hw_mgr->frame_req_mutex); +#endif return rc; +#ifndef CONFIG_MACH_XIAOMI_NABU stop_unlock: if (hw_device->hw_intf->hw_ops.stop) { struct cam_fd_hw_stop_args stop_args; @@ -933,6 +951,7 @@ static int cam_fd_mgr_util_submit_frame(void *priv, void *data) sizeof(stop_args))) CAM_ERR(CAM_FD, "Failed in HW Stop %d", rc); } +#endif put_req_into_free_list: cam_fd_mgr_util_put_frame_req(&hw_mgr->frame_free_list, &frame_req); diff --git a/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 4bc666984083..8af7a17a73e8 100644 --- a/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -51,6 +51,9 @@ #include "cam_trace.h" #include "cam_cpas_api.h" #include "cam_common_util.h" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include "../cam_sync/cam_sync_private.h" +#endif #define ICP_WORKQ_TASK_CMD_TYPE 1 #define ICP_WORKQ_TASK_MSG_TYPE 2 @@ -58,7 +61,11 @@ #define ICP_DEV_TYPE_TO_CLK_TYPE(dev_type) \ ((dev_type == CAM_ICP_RES_TYPE_BPS) ? ICP_CLK_HW_BPS : ICP_CLK_HW_IPE) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define ICP_DEVICE_IDLE_TIMEOUT 3000 +#else #define ICP_DEVICE_IDLE_TIMEOUT 400 +#endif static struct cam_icp_hw_mgr icp_hw_mgr; @@ -3571,6 +3578,24 @@ static bool cam_icp_mgr_is_valid_inconfig(struct cam_packet *packet) packet->num_io_configs, IPE_IO_IMAGES_MAX, num_in_map_entries, CAM_MAX_IN_RES); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* + * From the input parameter side, we add the + * protection to avoid the kernel mem bort which + * introduced from userspace, since we have the + * limit on CAM_SYNC_MAX_OBJS for icp sync_obj num. + */ + for (i = 0 ; i < packet->num_io_configs; i++) { + if ((io_cfg_ptr[i].direction == CAM_BUF_INPUT) && + (io_cfg_ptr[i].fence >= CAM_SYNC_MAX_OBJS)) { + in_config_valid = false; + CAM_ERR(CAM_ICP, + "In config fence/sync_obj(%u) more than allowed(%u)", + io_cfg_ptr[i].fence, (CAM_SYNC_MAX_OBJS - 1)); + } + } +#endif + return in_config_valid; } diff --git a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c index adf01832aea9..8cb5b4ff240c 100644 --- a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c +++ b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c @@ -596,6 +596,10 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( struct cam_isp_ctx_req *req_isp; struct cam_context *ctx = ctx_isp->base; uint64_t buf_done_req_id; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct cam_ctx_request *next_req; + struct cam_isp_ctx_req *next_req_isp; +#endif if (list_empty(&ctx->active_req_list)) { CAM_INFO(CAM_ISP, "Buf done with no active request!"); @@ -772,6 +776,33 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( ctx_isp->active_req_cnt--; } ctx_isp->irq_delay_detect = false; + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (ctx_isp->active_req_cnt > 0) { + if (list_empty(&ctx->active_req_list)) { + CAM_DBG(CAM_ISP, "Buf done with no active request!"); + goto end; + } + next_req = list_first_entry(&ctx->active_req_list, struct cam_ctx_request, list); + CAM_DBG(CAM_REQ, "next_req:%p, active_reqcnt:%d", next_req, ctx_isp->active_req_cnt); + + next_req_isp = (struct cam_isp_ctx_req *) next_req->req_priv; + + CAM_DBG(CAM_REQ, "next_req_isp:bubble_detected:%d,bubble_report:%d", + next_req_isp->bubble_detected, next_req_isp->bubble_report); + if (next_req_isp->bubble_detected && next_req_isp->bubble_report) { + next_req_isp->num_acked = 0; + next_req_isp->bubble_detected = false; + list_del_init(&next_req->list); + list_add(&next_req->list, &ctx->pending_req_list); + atomic_set(&ctx_isp->process_bubble, 0); + ctx_isp->active_req_cnt--; + CAM_DBG(CAM_REQ, + "Move active request %lld to pending list(cnt = %d) [bubble recovery], ctx %u", + next_req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); + } + } +#endif end: return rc; } @@ -782,6 +813,11 @@ static void __cam_isp_ctx_send_sof_boot_timestamp( { struct cam_req_mgr_message req_msg; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (0 == request_id) + return; +#endif + req_msg.session_hdl = ctx_isp->base->session_hdl; req_msg.u.frame_msg.frame_id = ctx_isp->frame_id; req_msg.u.frame_msg.request_id = request_id; @@ -3496,6 +3532,10 @@ static int __cam_isp_ctx_config_dev_in_top_state( list_add_tail(&req->list, &ctx->free_req_list); spin_unlock_bh(&ctx->lock); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + atomic_set(&ctx_isp->process_bubble, 0); +#endif + return rc; } diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 27311e862b60..22b104d90c8e 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -368,6 +368,9 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) int rc = 0; uint32_t val = 0, i; uint32_t status; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + unsigned long flags; +#endif soc_info = &csid_hw->hw_info->soc_info; csid_reg = csid_hw->csid_info->csid_reg; @@ -382,6 +385,10 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) CAM_DBG(CAM_ISP, "CSID:%d Csid reset", csid_hw->hw_intf->hw_idx); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); +#endif + /* Mask all interrupts */ cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); @@ -424,6 +431,10 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); +#endif + cam_io_w_mb(0x80, soc_info->reg_map[0].mem_base + csid_hw->csid_info->csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); @@ -1045,6 +1056,9 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) const struct cam_ife_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; uint32_t i, val, clk_lvl; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + unsigned long flags; +#endif csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; @@ -1083,6 +1097,10 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) goto disable_soc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); +#endif + /* clear all interrupts */ cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); @@ -1109,6 +1127,10 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); +#endif + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_hw_version_addr); CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x", @@ -2682,6 +2704,10 @@ static int cam_ife_csid_reset(void *hw_priv, csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; reset = (struct cam_csid_reset_cfg_args *)reset_args; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + mutex_lock(&csid_hw->hw_info->hw_mutex); +#endif + switch (reset->reset_type) { case CAM_IFE_CSID_RESET_GLOBAL: rc = cam_ife_csid_global_reset(csid_hw); @@ -2696,6 +2722,10 @@ static int cam_ife_csid_reset(void *hw_priv, break; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + mutex_unlock(&csid_hw->hw_info->hw_mutex); +#endif + return rc; } @@ -2838,8 +2868,16 @@ static int cam_ife_csid_reset_retain_sw_reg( const struct cam_ife_csid_reg_offset *csid_reg = csid_hw->csid_info->csid_reg; struct cam_hw_soc_info *soc_info; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + unsigned long flags; +#endif soc_info = &csid_hw->hw_info->soc_info; + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); +#endif + /* clear the top interrupt first */ cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); @@ -2852,6 +2890,11 @@ static int cam_ife_csid_reset_retain_sw_reg( cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_rst_strobes_addr); + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); +#endif + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_status_addr, status, (status & 0x1) == 0x1, @@ -2865,11 +2908,20 @@ static int cam_ife_csid_reset_retain_sw_reg( csid_hw->hw_intf->hw_idx, rc); rc = 0; } + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); +#endif + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); +#endif + return rc; } @@ -3577,6 +3629,10 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); +#endif + /* clear */ cam_io_w_mb(irq_status[CSID_IRQ_STATUS_RX], soc_info->reg_map[0].mem_base + @@ -3599,6 +3655,10 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); +#endif + if (irq_status[CSID_IRQ_STATUS_RX] & BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "csi rx reset complete"); diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c index 19c73f06c49f..7f7560bf7bb7 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -436,7 +436,11 @@ void cam_isp_hw_get_timestamp(struct cam_isp_timestamp *time_stamp) { struct timespec ts; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + ktime_get_ts(&ts); +#else get_monotonic_boottime(&ts); +#endif time_stamp->mono_time.tv_sec = ts.tv_sec; time_stamp->mono_time.tv_usec = ts.tv_nsec/1000; time_stamp->time_usecs = ts.tv_sec * 1000000 + diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c index 25e1644933f2..acce1128d723 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -408,6 +408,209 @@ int32_t cam_actuator_publish_dev_info(struct cam_req_mgr_device_info *info) return 0; } +#ifdef CONFIG_VCM_AK7374 +/* ---------------------------------------------------- +* Anti-Actuator-Noise logic start, +* Re-config actuator eeprom values +------------------------------------------------------*/ +#define AAN_AK7374_MASK 0xE8 +#define AAN_AK7374_WRITE_NUM 25 +#define AAN_AK7374_READ_NUM 22 + +unsigned int aan_already_write; + +unsigned int aan_ak7374_setting[AAN_AK7374_WRITE_NUM][2] = { + {0xAE, 0x3B}, {0x10, 0x36}, {0x11, 0x23}, {0x12, 0xDC}, + {0x13, 0x78}, {0x14, 0x14}, {0x15, 0x1E}, {0x16, 0x1A}, + {0x17, 0x5E}, {0x18, 0xDB}, {0x19, 0xC8}, {0x1A, 0x28}, + {0x1C, 0x00}, {0x1D, 0x00}, {0x1E, 0x00}, {0x20, 0x6E}, + {0x21, 0x01}, {0x22, 0x00}, {0x23, 0x1A}, {0x24, 0x00}, + {0x25, 0x00}, {0x03, 0x01}, {0x03, 0x02}, {0x03, 0x04}, + {0x03, 0x08} +}; + + /* +read-check: 0xE9,0x4B, 0x0 +write:0xE8,0xAE, 0x0 +power off +power on +wait 10ms + */ +unsigned int aan_ak7374_verify[AAN_AK7374_READ_NUM][2] = { + {0x0A, 0x89}, {0x0B, 0x84}, {0x10, 0x36}, {0x11, 0x23}, + {0x12, 0xDC}, {0x13, 0x78}, {0x14, 0x14}, {0x15, 0x1E}, + {0x16, 0x1A}, {0x17, 0x5E}, {0x18, 0xDB}, {0x19, 0xC8}, + {0x1A, 0x28}, {0x1C, 0x00}, {0x1D, 0x00}, {0x1E, 0x00}, + {0x20, 0x6E}, {0x21, 0x01}, {0x22, 0x00}, {0x23, 0x1A}, + {0x24, 0x00}, {0x25, 0x00} +}; + +static void aan_i2c_read(struct camera_io_master *io_master_info, struct i2c_settings_list *i2c_list, unsigned short addr, unsigned short *data) +{ + int rc = 0; + + i2c_list->i2c_settings.addr_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + i2c_list->i2c_settings.data_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + + rc = camera_io_dev_read( + io_master_info, + addr, + (uint32_t *)(data), + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type); + + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "aan, aan_i2c_read failed: %d", rc); + } else { + CAM_DBG(CAM_ACTUATOR, "aan, aan_i2c_read, addr=0x%x, data=0x%x, data_addr=0x%x, sid=0x%x", + addr, *data, data, io_master_info->cci_client->sid); + } +} + +static void aan_i2c_write(struct camera_io_master *io_master_info, struct i2c_settings_list *i2c_list, unsigned short addr, unsigned short data) +{ + int32_t rc = 0; + + i2c_list->i2c_settings.reg_setting[0].reg_addr = addr; + i2c_list->i2c_settings.reg_setting[0].reg_data = data; + i2c_list->i2c_settings.data_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + i2c_list->i2c_settings.addr_type = CAMERA_SENSOR_I2C_TYPE_BYTE; + i2c_list->op_code == CAM_SENSOR_I2C_WRITE_RANDOM; + i2c_list->i2c_settings.size = 1; + + rc = camera_io_dev_write(io_master_info, &(i2c_list->i2c_settings)); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "aan, aan_i2c_write failed: %d", rc); + } else { + CAM_DBG(CAM_ACTUATOR, "aan, aan_i2c_write, addr=0x%x, data=0x%x, sid=%d", addr, data, io_master_info->cci_client->sid); + } +} + +static int32_t cam_actuator_anti_noise(struct cam_actuator_ctrl_t *a_ctrl, struct i2c_settings_array *i2c_set) +{ + unsigned int i = 0; + unsigned short dat = 0; + struct i2c_settings_list *i2c_list; + unsigned int ret = 0; + unsigned int sid_backup; + + if (aan_already_write == 1) { + CAM_DBG(CAM_ACTUATOR, "aan, eeprom already set"); + return 0; + } else { + CAM_DBG(CAM_ACTUATOR, "aan, in"); + } + + if (a_ctrl != NULL && a_ctrl->io_master_info.cci_client != NULL) { + sid_backup = a_ctrl->io_master_info.cci_client->sid; + } else { + CAM_ERR(CAM_ACTUATOR, "aan, invalid param, a_ctrl or cci_client is NULL, a_ctrl=0x%p", a_ctrl); + return 0; + } + CAM_DBG(CAM_ACTUATOR, "aan, orig a_ctrl->io_master_info.cci_client->sid=%d", sid_backup); + + if ((AAN_AK7374_MASK >> 1) != a_ctrl->io_master_info.cci_client->sid) { + CAM_ERR(CAM_ACTUATOR, "aan, not 2nd provider module, no need update."); + return 0; + } + + if (a_ctrl == NULL || i2c_set == NULL) { + CAM_ERR(CAM_ACTUATOR, "aan, cam_actuator_anti_noise, Invalid Args"); + ret = -EINVAL; + goto aan_out; + } + + if (i2c_set->is_settings_valid != 1) { + CAM_ERR(CAM_ACTUATOR, "aan, cam_actuator_anti_noise, Invalid Args"); + ret = -EINVAL; + goto aan_out; + } + + list_for_each_entry(i2c_list, &(i2c_set->list_head), list) { + CAM_DBG(CAM_ACTUATOR, "aan, cam_actuator_anti_noise start. sid=%d, master_type=%d, i2c_set->request_id=%d", + a_ctrl->io_master_info.cci_client->sid, a_ctrl->io_master_info.master_type, i2c_set->request_id); + + // for 2nd provider AK7374 + a_ctrl->io_master_info.cci_client->sid = AAN_AK7374_MASK>>1; //AK7374 EEPROM mask + aan_i2c_read(&(a_ctrl->io_master_info), i2c_list, 0x03, &dat); + if (dat == 0x0E) { + //Step 1: Check whethre need to update the eeprom. + for (i = 0; i < AAN_AK7374_READ_NUM; i++) { + aan_i2c_read(&(a_ctrl->io_master_info), i2c_list, aan_ak7374_verify[i][0], &dat); + if (dat != aan_ak7374_verify[i][1]) { + CAM_ERR(CAM_ACTUATOR, "aan, eeprom data not match, i=%d, addr=0x%x, expect=0x%x, real=0x%x", + i, aan_ak7374_verify[i][0], aan_ak7374_verify[i][1], dat); + break; + } + } + if (i == AAN_AK7374_READ_NUM) { + CAM_ERR(CAM_ACTUATOR, "aan, do not need update"); + aan_already_write = 1; + goto aan_out; + } + + //Step 2: Update the eeprom PID. + for (i = 0; i < AAN_AK7374_WRITE_NUM; i++) { + aan_i2c_write(&(a_ctrl->io_master_info), i2c_list, aan_ak7374_setting[i][0], aan_ak7374_setting[i][1]); + if (0x03 == aan_ak7374_setting[i][0]) { + msleep(100); + } + } + + //Step 3: Check registers flag1 + aan_i2c_read(&(a_ctrl->io_master_info), i2c_list, 0x4B, &dat); + if (dat != 0) { + for (i = AAN_AK7374_WRITE_NUM-4; i < AAN_AK7374_WRITE_NUM; i++) { + aan_i2c_write(&(a_ctrl->io_master_info), i2c_list, aan_ak7374_setting[i][0], aan_ak7374_setting[i][1]); + } + aan_i2c_read(&(a_ctrl->io_master_info), i2c_list, 0x4B, &dat); + if (dat != 0) { + CAM_ERR(CAM_ACTUATOR, "aan, ak7374_write failed, 0x4B=0x%x", dat); + goto aan_out; + } + } + + //Step 4: Check register flag2 + aan_i2c_write(&(a_ctrl->io_master_info), i2c_list, 0x03, 0x10); + msleep(100); + aan_i2c_write(&(a_ctrl->io_master_info), i2c_list, 0xAE, 0x0); + msleep(100); + aan_i2c_read(&(a_ctrl->io_master_info), i2c_list, 0x0A, &dat); + if (dat != 0x89) { + CAM_ERR(CAM_ACTUATOR, "aan, ak7374 flag2 failed, 0x0A, expect=0x89, real=0x%x", dat); + } + CAM_DBG(CAM_ACTUATOR, "aan, ak7374_write done"); + + //Step 5: Verify PID data + for (i = 0; i < AAN_AK7374_READ_NUM; i++) { + aan_i2c_read(&(a_ctrl->io_master_info), i2c_list, aan_ak7374_verify[i][0], &dat); + if (dat != aan_ak7374_verify[i][1]) { + CAM_ERR(CAM_ACTUATOR, "aan, ak7374_write failed, i=%d, addr=0x%x,, expect=0x%x, real=0x%x", + i, aan_ak7374_verify[i][0], aan_ak7374_verify[i][1], dat); + break; + } + } + if (i == AAN_AK7374_READ_NUM) { + CAM_DBG(CAM_ACTUATOR, "aan, ak7374_write success."); + } else { + CAM_ERR(CAM_ACTUATOR, "aan, ak7374_write failed."); + } + goto aan_out; + } else { + CAM_ERR(CAM_ACTUATOR, "aan, not ak7374, 0x03=0x%x", dat); + } + } +aan_out: + a_ctrl->io_master_info.cci_client->sid = sid_backup; + aan_already_write = 1; + CAM_DBG(CAM_ACTUATOR, "aan, cam_actuator_anti_noise done"); + return 0; +} +/* ---------------------------------------------------- +* Anti-Actuator-Noise logic end +------------------------------------------------------*/ +#endif + int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, void *arg) { @@ -596,6 +799,10 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, goto rel_pkt_buf; } +#ifdef CONFIG_VCM_AK7374 + cam_actuator_anti_noise(a_ctrl, &a_ctrl->i2c_data.init_settings); +#endif + /* Delete the request even if the apply is failed */ rc = delete_request(&a_ctrl->i2c_data.init_settings); if (rc < 0) { diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_cci/cam_cci_core.c index a06a4c6c6339..9ab01270750d 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_cci/cam_cci_core.c @@ -471,6 +471,8 @@ static int32_t cam_cci_calc_cmd_len(struct cci_device *cci_dev, for (i = 0; i < pack_max_len;) { if (cmd->delay || ((cmd - i2c_cmd) >= (cmd_size - 1))) break; + /* delete for E5G ois setting write */ +#ifndef CONFIG_USE_ROHM_BU64753 if (cmd->reg_addr + 1 == (cmd+1)->reg_addr) { len += data_len; @@ -479,7 +481,9 @@ static int32_t cam_cci_calc_cmd_len(struct cci_device *cci_dev, break; } (*pack)++; - } else { + } +#endif + else { break; } i += data_len; diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index 1c6037370a2b..d8d197364d2f 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -12,7 +12,11 @@ #include "cam_csiphy_soc.h" #include "cam_csiphy_core.h" +#ifdef CONFIG_MACH_XIAOMI_VAYU +#include "include/cam_csiphy_1_1_hwreg_vayu.h" +#else #include "include/cam_csiphy_1_1_hwreg.h" +#endif #include "include/cam_csiphy_1_0_hwreg.h" #include "include/cam_csiphy_1_2_hwreg.h" #include "include/cam_csiphy_1_2_2_hwreg.h" @@ -254,7 +258,12 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->hw_version = CSIPHY_VERSION_V11; csiphy_dev->clk_lane = 0; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_1_1; +#else csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; +#endif } else if (of_device_is_compatible(soc_info->dev->of_node, "qcom,csiphy-v1.2")) { csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg; diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h index 9c31dd458cf5..4fd632314c46 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h @@ -19,10 +19,10 @@ struct csiphy_reg_parms_t csiphy_v1_1 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, - .csiphy_common_array_size = 5, + .csiphy_common_array_size = 6, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 16, - .csiphy_3ph_config_array_size = 28, + .csiphy_3ph_config_array_size = 43, .csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_combo_ck_ln = 0x10, }; @@ -31,6 +31,7 @@ struct csiphy_reg_t csiphy_common_reg_1_1[] = { {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x72, 0x00, CSIPHY_3PH_REGS}, {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }; @@ -60,27 +61,25 @@ struct csiphy_reg_t csiphy_irq_reg_1_1[] = { struct csiphy_reg_t csiphy_2ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { - {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0028, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -89,169 +88,179 @@ csiphy_reg_t csiphy_2ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070C, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0428, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, }; struct csiphy_reg_t csiphy_2ph_v1_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { - {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0060, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070C, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0760, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - + {0x0260, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0418, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x041C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0460, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x060C, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, }, }; struct csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { - {0x015C, 0xC8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x016C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, @@ -266,22 +275,37 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x09B0, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0980, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0984, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0988, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { - {0x035C, 0xC8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x036C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, @@ -296,22 +320,37 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0AB0, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { - {0x055C, 0xC8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x056C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, @@ -326,16 +365,22 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0BB0, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; @@ -343,9 +388,18 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { struct csiphy_reg_t csiphy_3ph_v1_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { - {0x015C, 0xC8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x016C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, @@ -360,22 +414,37 @@ struct csiphy_reg_t {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x09B0, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0980, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0984, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0988, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x035C, 0xC8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x036C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, @@ -390,22 +459,37 @@ struct csiphy_reg_t {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0AB0, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS}, }, { - {0x055C, 0xC8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x056C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, @@ -420,18 +504,53 @@ struct csiphy_reg_t {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0BB0, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; + +struct data_rate_settings_t data_rate_delta_table_1_1 = { + .num_data_rate_settings = 2, + .data_rate_settings = { + { + // data rate <= 2.3 Gsps + // max bandwidth = 2.3 * 2.28 * (10**3) Mbps + .bandwidth = 5243000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x09B0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS} + } + }, + { + // 2.3 Gsps <= data rate <= 2.5 Gsps + // max bandwidth = 2.5 * 2.28 * (10**3) Mbps + .bandwidth = 5700000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x09B0, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS} + } + } + } +}; + #endif /* _CAM_CSIPHY_1_1_HWREG_H_ */ diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg_vayu.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg_vayu.h new file mode 100644 index 000000000000..bbaad56a41be --- /dev/null +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg_vayu.h @@ -0,0 +1,585 @@ +/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CAM_CSIPHY_1_1_HWREG_H_ +#define _CAM_CSIPHY_1_1_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_parms_t csiphy_v1_1 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_common_array_size = 5, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 18, + .csiphy_3ph_config_array_size = 43, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_1_1[] = { + {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_reset_reg_1_1[] = { + {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, + {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct csiphy_reg_t csiphy_irq_reg_1_1[] = { + {0x082c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0xFB, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083c, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0840, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0844, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0848, 0xEF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x084c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0850, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0854, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + +struct +csiphy_reg_t csiphy_2ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_2ph_v1_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0418, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, +}; + +struct +csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0144, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + +struct csiphy_reg_t + csiphy_3ph_v1_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0144, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09B0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B90, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B94, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B98, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0x5F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x59, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058C, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + + +struct data_rate_settings_t data_rate_delta_table_1_1 = { + .num_data_rate_settings = 2, + .data_rate_settings = { + { + // data rate <= 2.3 Gsps + // max bandwidth = 2.3 * 2.28 * (10**3) Mbps + .bandwidth = 5243000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x09B0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x23, 0x00, CSIPHY_DEFAULT_PARAMS} + } + }, + { + // 2.3 Gsps <= data rate <= 2.5 Gsps + // max bandwidth = 2.5 * 2.28 * (10**3) Mbps + .bandwidth = 5700000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x09B0, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AB0, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BB0, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS} + } + } + } +}; + +#endif /* _CAM_CSIPHY_1_1_HWREG_H_ */ diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index 6f1f32e80e03..07e1f0ec6c60 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -905,6 +905,14 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) if (rc) { CAM_ERR(CAM_EEPROM, "read_eeprom_memory failed"); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cam_destroy_device_hdl(e_ctrl->bridge_intf.device_hdl); + CAM_ERR(CAM_EEPROM, "destroying the device hdl"); + + e_ctrl->bridge_intf.device_hdl = -1; + e_ctrl->bridge_intf.link_hdl = -1; + e_ctrl->bridge_intf.session_hdl = -1; +#endif goto power_down; } diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c index 0123cb3a83d5..b3cdd9898af2 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c @@ -64,6 +64,11 @@ int32_t cam_ois_construct_default_power_setting( } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CUSTOM_INIT_DL +#define OIS_TRANS_SIZE 64 +#endif + /** * cam_ois_get_dev_handle - get device handle * @o_ctrl: ctrl structure @@ -300,6 +305,40 @@ static int cam_ois_slaveInfo_pkt_parser(struct cam_ois_ctrl_t *o_ctrl, return rc; } +#ifdef CUSTOM_INIT_DL +struct cam_sensor_i2c_reg_array ois_init0_array[]= { + {0x8262, 0xFF02, 0x0, 0x0}, + {0x8263, 0x9F05, 0x0, 0x0}, + {0x8264, 0x6040, 0x0, 0x0}, + {0x8260, 0x1130, 0x0, 0x0}, + {0x8265, 0x8000, 0x0, 0x0}, + {0x8261, 0x0280, 0x0, 0x0}, + {0x8261, 0x0380, 0x0, 0x0}, + {0x8261, 0x0988, 0x0, 0x0}, +}; + +static int cam_ois_fw_init0(struct cam_ois_ctrl_t *o_ctrl) +{ + int32_t rc = 0; + struct cam_sensor_i2c_reg_setting write_setting; + write_setting.size= sizeof(ois_init0_array)/sizeof(struct cam_sensor_i2c_reg_array); + write_setting.addr_type =CAMERA_SENSOR_I2C_TYPE_WORD; + write_setting.data_type= CAMERA_SENSOR_I2C_TYPE_WORD; + write_setting.delay=0; + write_setting.reg_setting= ois_init0_array; + + rc = camera_io_dev_write(&(o_ctrl->io_master_info), + &write_setting); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "{debug-ois}Failed in Applying i2c wrt settings"); + return rc; + } + + return rc; +} +#endif + static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) { uint16_t total_bytes = 0; @@ -314,6 +353,9 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) struct device *dev = &(o_ctrl->pdev->dev); struct cam_sensor_i2c_reg_setting i2c_reg_setting; struct page *page = NULL; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int32_t i; +#endif if (!o_ctrl) { CAM_ERR(CAM_OIS, "Invalid Args"); @@ -328,6 +370,10 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) fw_name_prog = name_prog; fw_name_coeff = name_coeff; +#ifdef CUSTOM_INIT_DL + cam_ois_fw_init0(o_ctrl); +#endif + /* Load FW */ rc = request_firmware(&fw, fw_name_prog, dev); if (rc) { @@ -353,6 +399,26 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) i2c_reg_setting.reg_setting = (struct cam_sensor_i2c_reg_array *) ( page_address(page)); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + for (i = 0, ptr = (uint8_t *)fw->data; i < total_bytes;) { + for (cnt = 0; cnt < OIS_TRANS_SIZE && i < total_bytes; + cnt++, ptr++, i++) { + i2c_reg_setting.reg_setting[cnt].reg_addr = + o_ctrl->opcode.prog; + i2c_reg_setting.reg_setting[cnt].reg_data = *ptr; + i2c_reg_setting.reg_setting[cnt].delay = 0; + i2c_reg_setting.reg_setting[cnt].data_mask = 0; + } + i2c_reg_setting.size = cnt; + + rc = camera_io_dev_write_continuous(&(o_ctrl->io_master_info), + &i2c_reg_setting, 1); + if (rc < 0) { + CAM_ERR(CAM_OIS, "OIS FW download failed %d", rc); + goto release_firmware; + } + } +#else for (cnt = 0, ptr = (uint8_t *)fw->data; cnt < total_bytes; cnt++, ptr++) { i2c_reg_setting.reg_setting[cnt].reg_addr = @@ -368,6 +434,7 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) CAM_ERR(CAM_OIS, "OIS FW download failed %d", rc); goto release_firmware; } +#endif cma_release(dev_get_cma_area((o_ctrl->soc_info.dev)), page, fw_size); page = NULL; @@ -398,6 +465,25 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) i2c_reg_setting.reg_setting = (struct cam_sensor_i2c_reg_array *) ( page_address(page)); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + for (i = 0, ptr = (uint8_t *)fw->data; i < total_bytes;) { + for (cnt = 0; cnt < OIS_TRANS_SIZE && i < total_bytes; + cnt++, ptr++, i++) { + i2c_reg_setting.reg_setting[cnt].reg_addr = + o_ctrl->opcode.coeff; + i2c_reg_setting.reg_setting[cnt].reg_data = *ptr; + i2c_reg_setting.reg_setting[cnt].delay = 0; + i2c_reg_setting.reg_setting[cnt].data_mask = 0; + } + + i2c_reg_setting.size = cnt; + + rc = camera_io_dev_write_continuous(&(o_ctrl->io_master_info), + &i2c_reg_setting, 1); + if (rc < 0) + CAM_ERR(CAM_OIS, "OIS FW download failed %d", rc); + } +#else for (cnt = 0, ptr = (uint8_t *)fw->data; cnt < total_bytes; cnt++, ptr++) { i2c_reg_setting.reg_setting[cnt].reg_addr = @@ -411,6 +497,7 @@ static int cam_ois_fw_download(struct cam_ois_ctrl_t *o_ctrl) &i2c_reg_setting, 1); if (rc < 0) CAM_ERR(CAM_OIS, "OIS FW download failed %d", rc); +#endif release_firmware: cma_release(dev_get_cma_area((o_ctrl->soc_info.dev)), diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c index a20ac4962345..655187b65686 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -647,6 +647,9 @@ int cam_sensor_match_id(struct cam_sensor_ctrl_t *s_ctrl) return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +uint32_t operation_mode = 0; +#endif int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, void *arg) { @@ -775,6 +778,10 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, goto release_mutex; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + operation_mode = sensor_acq_dev.operation_mode; +#endif + bridge_params.session_hdl = sensor_acq_dev.session_handle; bridge_params.ops = &s_ctrl->bridge_intf.ops; bridge_params.v4l2_sub_dev_flag = 0; @@ -997,6 +1004,100 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, } } break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case CAM_UPDATE_REG: { + struct cam_sensor_i2c_reg_setting user_reg_setting; + struct cam_sensor_i2c_reg_array *i2c_reg_setting = NULL; + int i; + + rc = copy_from_user(&user_reg_setting, (void __user *)cmd->handle, sizeof(user_reg_setting)); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Copy data from user space failed\n"); + goto release_mutex; + } + + CAM_DBG(CAM_SENSOR, "CAM_UPDATE_REG reg setting size = %d", user_reg_setting.size); + i2c_reg_setting = kzalloc(sizeof(struct cam_sensor_i2c_reg_array) * + user_reg_setting.size, GFP_KERNEL); + if (!i2c_reg_setting) { + rc = -ENOMEM; + CAM_ERR(CAM_SENSOR, "kzalloc memory failed\n"); + goto release_mutex; + } + + rc = copy_from_user(i2c_reg_setting, (void __user *)user_reg_setting.reg_setting, + sizeof(struct cam_sensor_i2c_reg_array) * user_reg_setting.size); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Copy i2c setting from user space failed\n"); + kfree(i2c_reg_setting); + goto release_mutex; + } + user_reg_setting.reg_setting = i2c_reg_setting; + + for (i = 0; i < user_reg_setting.size; i++) { + CAM_DBG(CAM_SENSOR, "CAM_UPDATE_REG reg_addr=0x%x, reg_value=0x%x", + i2c_reg_setting[i].reg_addr, i2c_reg_setting[i].reg_data); + } + + rc = camera_io_dev_write(&s_ctrl->io_master_info, &user_reg_setting); + if (rc < 0) + CAM_ERR(CAM_SENSOR, "Write setting failed, rc = %d\n", rc); + + kfree(i2c_reg_setting); + } + break; + case CAM_READ_REG: { + struct cam_sensor_i2c_reg_setting user_reg_setting; + struct cam_sensor_i2c_reg_array *i2c_reg_setting; + int ret = 0; + int i; + + rc = copy_from_user(&user_reg_setting, (void __user *)cmd->handle, sizeof(user_reg_setting)); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Copy data from user space failed"); + goto release_mutex; + } + + CAM_DBG(CAM_SENSOR, "CAM_READ_REG reg setting size = %d", user_reg_setting.size); + i2c_reg_setting = kzalloc(sizeof(struct cam_sensor_i2c_reg_array) * + user_reg_setting.size, GFP_KERNEL); + if (!i2c_reg_setting) { + rc = -ENOMEM; + CAM_ERR(CAM_SENSOR, "kzalloc memory failed\n"); + goto release_mutex; + } + + rc = copy_from_user(i2c_reg_setting, (void __user *)user_reg_setting.reg_setting, + sizeof(struct cam_sensor_i2c_reg_array) * user_reg_setting.size); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "Copy i2c setting from user space failed"); + kfree(i2c_reg_setting); + goto release_mutex; + } + + for (i = 0; i < user_reg_setting.size; i++) { + ret += camera_io_dev_read( + &(s_ctrl->io_master_info), + i2c_reg_setting[i].reg_addr, + &i2c_reg_setting[i].reg_data, CAMERA_SENSOR_I2C_TYPE_WORD, + CAMERA_SENSOR_I2C_TYPE_BYTE); + CAM_DBG(CAM_SENSOR, "CAM_READ_REG reg_addr=0x%x, reg_value=0x%x, sid = 0x%x", + i2c_reg_setting[i].reg_addr, i2c_reg_setting[i].reg_data, s_ctrl->io_master_info.cci_client->sid); + } + + if (copy_to_user((void __user *)user_reg_setting.reg_setting, i2c_reg_setting, + sizeof(struct cam_sensor_i2c_reg_array) * user_reg_setting.size) || ret != 0) { + CAM_ERR(CAM_SENSOR, "Copy data to user space failed"); + rc = -EFAULT; + } + if (copy_to_user((void __user *)cmd->handle, &user_reg_setting, sizeof(user_reg_setting)) || ret != 0) { + CAM_ERR(CAM_SENSOR, "Copy data to user space failed"); + rc = -EFAULT; + } + kfree(i2c_reg_setting); + } + break; +#endif default: CAM_ERR(CAM_SENSOR, "Invalid Opcode: %d", cmd->op_code); rc = -EINVAL; @@ -1036,12 +1137,23 @@ int cam_sensor_publish_dev_info(struct cam_req_mgr_device_info *info) info->dev_id = CAM_REQ_MGR_DEVICE_SENSOR; strlcpy(info->name, CAM_SENSOR_NAME, sizeof(info->name)); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (s_ctrl->pipeline_delay >= 0 && s_ctrl->pipeline_delay <= 3) +#else if (s_ctrl->pipeline_delay >= 1 && s_ctrl->pipeline_delay <= 3) +#endif info->p_delay = s_ctrl->pipeline_delay; else info->p_delay = 2; info->trigger = CAM_TRIGGER_POINT_SOF; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (operation_mode == 0x8006) + info->p_delay = 0; + if (operation_mode == 0x8002) + info->p_delay = 1; +#endif + return rc; } diff --git a/drivers/media/platform/msm/camera/cam_sync/cam_sync_private.h b/drivers/media/platform/msm/camera/cam_sync/cam_sync_private.h index c3cb345a13fa..a4d6fb5d6a92 100644 --- a/drivers/media/platform/msm/camera/cam_sync/cam_sync_private.h +++ b/drivers/media/platform/msm/camera/cam_sync/cam_sync_private.h @@ -31,7 +31,11 @@ #endif #define CAM_SYNC_OBJ_NAME_LEN 64 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CAM_SYNC_MAX_OBJS 1280 +#else #define CAM_SYNC_MAX_OBJS 1024 +#endif #define CAM_SYNC_MAX_V4L2_EVENTS 50 #define CAM_SYNC_DEBUG_FILENAME "cam_debug" #define CAM_SYNC_DEBUG_BASEDIR "cam" diff --git a/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c b/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c index 7935ada7bd53..29babcc37c7e 100644 --- a/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c +++ b/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c @@ -80,6 +80,16 @@ int cam_sync_init_group_object(struct sync_table_row *table, */ for (i = 0; i < num_objs; i++) { child_row = table + sync_objs[i]; + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (idx == sync_objs[i] || (sync_objs[i] >= CAM_SYNC_MAX_OBJS)) { + CAM_ERR(CAM_SYNC, "invalid fence:%d should be released", + sync_objs[i]); + rc = -EINVAL; + goto clean_children_info; + } +#endif + spin_lock_bh(&sync_dev->row_spinlocks[sync_objs[i]]); /* validate child */ diff --git a/drivers/media/platform/msm/camera/cam_utils/cam_soc_util.h b/drivers/media/platform/msm/camera/cam_utils/cam_soc_util.h index d0bab027790e..9e6e14024893 100644 --- a/drivers/media/platform/msm/camera/cam_utils/cam_soc_util.h +++ b/drivers/media/platform/msm/camera/cam_utils/cam_soc_util.h @@ -36,7 +36,11 @@ #define CAM_SOC_MAX_BASE CAM_SOC_MAX_BLOCK /* maximum number of device regulator */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CAM_SOC_MAX_REGULATOR 6 +#else #define CAM_SOC_MAX_REGULATOR 5 +#endif /* maximum number of device clock */ #define CAM_SOC_MAX_CLK 32 diff --git a/include/uapi/media/cam_defs.h b/include/uapi/media/cam_defs.h index 0fa3777ee7a5..abdda6339daa 100644 --- a/include/uapi/media/cam_defs.h +++ b/include/uapi/media/cam_defs.h @@ -26,6 +26,11 @@ #define CAM_EXT_OPCODE_BASE 0x200 #define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CAM_UPDATE_REG (CAM_EXT_OPCODE_BASE + 0x2) +#define CAM_READ_REG (CAM_EXT_OPCODE_BASE + 0x3) +#endif + /* camera handle type */ #define CAM_HANDLE_USER_POINTER 1 #define CAM_HANDLE_MEM_HANDLE 2 diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 50b81276d0e1..c1b8abd29c40 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -35,7 +35,11 @@ * Max handles supported by cam_req_mgr * It includes both session and device handles */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CAM_REQ_MGR_MAX_HANDLES 128 +#else #define CAM_REQ_MGR_MAX_HANDLES 64 +#endif #define CAM_REQ_MGR_MAX_HANDLES_V2 128 #define MAX_LINKS_PER_SESSION 2 diff --git a/include/uapi/media/cam_sensor.h b/include/uapi/media/cam_sensor.h index 8fc180b7b632..72b6ee4053c9 100644 --- a/include/uapi/media/cam_sensor.h +++ b/include/uapi/media/cam_sensor.h @@ -370,6 +370,9 @@ struct cam_sensor_acquire_dev { uint32_t handle_type; uint32_t reserved; uint64_t info_handle; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + uint32_t operation_mode; +#endif } __attribute__((packed)); /** From 10fecf7a22762dc338c3549713b9c288406558f0 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 28 Aug 2024 17:02:20 +0200 Subject: [PATCH 074/226] arch: arm64: boot: dts: qcom: xiaomi: Commonize IR binding Change-Id: I377682516716686626b94c220f27f93207b46553 Signed-off-by: firebird11 --- .../qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi | 10 +--------- arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi | 9 +++++++++ .../boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi | 10 +--------- .../boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi | 10 +--------- .../boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi | 10 +--------- 5 files changed, 13 insertions(+), 36 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi index 5a3a024b5cff..d9789a1dba6f 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/cepheus/cepheus-sm8150.dtsi @@ -315,15 +315,7 @@ And public attribution of xiaomi platforms(like F1 and so and) }; -&qupv3_se1_spi { - status = "ok"; - irled@0 { - compatible = "ir-spi"; - reg = <0x0>; - status = "ok"; - spi-max-frequency = <19200000>; - }; -}; +#include "../common/ir.dtsi" &pm8150l_lpg { qcom,lut-patterns = <0 1 2 3 4 5 7 9 11 13 15 diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi new file mode 100644 index 000000000000..e7c91aa569e2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi @@ -0,0 +1,9 @@ +&qupv3_se1_spi { + status = "ok"; + irled@0 { + compatible = "ir-spi"; + reg = <0x0>; + status = "ok"; + spi-max-frequency = <19200000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi index 13907b71874d..63bf537c35e6 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/crux/crux-sm8150.dtsi @@ -789,15 +789,7 @@ And public attribution of xiaomi platforms(like F1X and so and) // qcom,esd-err-irq-gpio = <&tlmm 101 0x2002>; //}; -&qupv3_se1_spi { - status = "ok"; - irled@0 { - compatible = "ir-spi"; - reg = <0x0>; - status = "ok"; - spi-max-frequency = <19200000>; - }; -}; +#include "../common/ir.dtsi" &qupv3_se7_i2c { status = "ok"; diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi index f31136085341..2a542400b64e 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/nabu/nabu-sm8150.dtsi @@ -780,15 +780,7 @@ And public attribution of xiaomi platforms(like J20S and so and) }; }; -&qupv3_se1_spi { - status = "ok"; - irled@0 { - compatible = "ir-spi"; - reg = <0x0>; - status = "ok"; - spi-max-frequency = <19200000>; - }; -}; +#include "../common/ir.dtsi" &pm8150l_lpg { qcom,lut-patterns = <0 1 2 3 4 5 7 9 11 13 15 diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi index b65899889e98..2e2470c20d76 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/vayu/vayu-sm8150.dtsi @@ -1539,15 +1539,7 @@ And public attribution of xiaomi platforms(like J20S and so and) }; }; -&qupv3_se1_spi { - status = "ok"; - irled@0 { - compatible = "ir-spi"; - reg = <0x0>; - status = "ok"; - spi-max-frequency = <19200000>; - }; -}; +#include "../common/ir.dtsi" &pm8150l_lpg { qcom,lut-patterns = <0 1 2 3 4 5 7 9 11 13 15 From 15d74a88d23cb8d972afc6bfc515e70569004315 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 28 Aug 2024 17:04:14 +0200 Subject: [PATCH 075/226] arch: arm64: boot: dts: qcom: xiaomi: Adapt IR SPI binding for upstream driver Change-Id: I9002f2e8d3a214195fe6131cc38d2a09e4c4c6f2 Signed-off-by: firebird11 --- arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi index e7c91aa569e2..538d11a8b054 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/overlay/common/ir.dtsi @@ -1,8 +1,16 @@ +&soc { + irda_regulator: irda-regulator { + compatible = "regulator-dummy"; + regulator-name = "irda_regulator"; + }; +}; + &qupv3_se1_spi { status = "ok"; irled@0 { - compatible = "ir-spi"; + compatible = "ir-spi-led"; reg = <0x0>; + power-supply = <&irda_regulator>; status = "ok"; spi-max-frequency = <19200000>; }; From 2e17daa96f7472116129edf826949352a98c3ef3 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:26:43 +0200 Subject: [PATCH 076/226] drivers: mfd: Import Xiaomi speaker ID driver * Run clang-format on source files Change-Id: Ibc8087ded16d22bb368ce8c3f10f9e1d79ae03fa Signed-off-by: firebird11 --- drivers/mfd/Kconfig | 5 + drivers/mfd/Makefile | 2 + drivers/mfd/spk-id.c | 235 +++++++++++++++++++++++++++++++++++++ include/linux/mfd/spk-id.h | 34 ++++++ 4 files changed, 276 insertions(+) create mode 100644 drivers/mfd/spk-id.c create mode 100644 include/linux/mfd/spk-id.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 99776c7768fd..aae080c9e012 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1829,5 +1829,10 @@ config MFD_VEXPRESS_SYSREG System Registers are the platform configuration block on the ARM Ltd. Versatile Express board. +config MFD_SPK_ID + bool "Versatile Express System Registers" + help + Xiaomi speaker ID driver. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index aef0d81d77c6..df705872a47a 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -228,3 +228,5 @@ obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o + +obj-$(CONFIG_MFD_SPK_ID) += spk-id.o diff --git a/drivers/mfd/spk-id.c b/drivers/mfd/spk-id.c new file mode 100644 index 000000000000..6860fed7fb5f --- /dev/null +++ b/drivers/mfd/spk-id.c @@ -0,0 +1,235 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct spk_id_info { + struct pinctrl *pinctrl; + struct pinctrl_state *pull_down; + struct pinctrl_state *pull_up; + struct pinctrl_state *no_pull; + int gpio; + int state; +}; + +static struct spk_id_info *spk_id_get_info(struct device_node *np) +{ + struct platform_device *pdev; + struct spk_id_info *info; + + if (!np) { + pr_err("%s: device node is null\n", __func__); + return NULL; + } + + pdev = of_find_device_by_node(np); + if (!pdev) { + pr_err("%s: platform device not found!\n", __func__); + return NULL; + } + + info = dev_get_drvdata(&pdev->dev); + if (!info) + dev_err(&pdev->dev, "%s: cannot find spk id info\n", __func__); + + return info; +} + +int spk_id_get_pin_3state(struct device_node *np) +{ + struct spk_id_info *info; + int pu = 0; + int pd = 0; + + info = spk_id_get_info(np); + if (!info) + return -EINVAL; + + if (IS_ERR_OR_NULL(info->pinctrl)) { + pr_err("%s: pin ctrl is invalid:%ld\n", __func__, + PTR_ERR(info->pinctrl)); + return -EINVAL; + } + + if (!gpio_is_valid(info->gpio)) { + pr_err("%s: gpio is invalid:%d\n", __func__, info->gpio); + return -EINVAL; + } + + pinctrl_select_state(info->pinctrl, info->pull_down); + msleep(3); + pd = gpio_get_value(info->gpio); + + pinctrl_select_state(info->pinctrl, info->pull_up); + msleep(3); + pu = gpio_get_value(info->gpio); + + if ((pd == pu) && (pd == 0)) { + pr_info("%s: id pin%d = %d\n", __func__, info->gpio, pd); + pinctrl_select_state(info->pinctrl, info->pull_down); + info->state = PIN_PULL_DOWN; + } else if ((pd == pu) && (pd == 1)) { + pr_info("%s: id pin%d = %d\n", __func__, info->gpio, pd); + pinctrl_select_state(info->pinctrl, info->pull_up); + info->state = PIN_PULL_UP; + } else { + pr_info("%s: id pin%d = 2\n", __func__, info->gpio); + pinctrl_select_state(info->pinctrl, info->no_pull); + info->state = PIN_FLOAT; + } + + return info->state; +} +EXPORT_SYMBOL(spk_id_get_pin_3state); + +int spk_id_get(struct device_node *np) +{ + int id; + int state; + + state = spk_id_get_pin_3state(np); + if (state < 0) { + pr_err("%s: Can not get id pin state, %d\n", __func__, state); + return VENDOR_ID_NONE; + } + + switch (state) { + case PIN_PULL_DOWN: + id = VENDOR_ID_AAC; + break; + case PIN_PULL_UP: + id = VENDOR_ID_UNKNOWN; + break; + case PIN_FLOAT: + id = VENDOR_ID_GOER; + break; + default: + id = VENDOR_ID_UNKNOWN; + break; + } + return id; +} +EXPORT_SYMBOL(spk_id_get); + +static int spk_id_probe(struct platform_device *pdev) +{ + int ret = 0; + struct spk_id_info *info; + + info = devm_kzalloc(&pdev->dev, sizeof(struct spk_id_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + dev_dbg(&pdev->dev, "%s: device %s\n", __func__, pdev->name); + info->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR_OR_NULL(info->pinctrl)) { + dev_err(&pdev->dev, + "%s: Cannot get speaker id gpio pinctrl:%ld\n", + __func__, PTR_ERR(info->pinctrl)); + ret = PTR_ERR(info->pinctrl); + goto err_pctrl_get; + } + + info->pull_down = pinctrl_lookup_state(info->pinctrl, "pull_down"); + if (IS_ERR_OR_NULL(info->pull_down)) { + dev_err(&pdev->dev, + "%s: Cannot get pull_down pinctrl state:%ld\n", + __func__, PTR_ERR(info->pull_down)); + ret = PTR_ERR(info->pull_down); + goto err_lookup_state; + } + + info->pull_up = pinctrl_lookup_state(info->pinctrl, "pull_up"); + if (IS_ERR_OR_NULL(info->pull_up)) { + dev_err(&pdev->dev, + "%s: Cannot get pull_up pinctrl state:%ld\n", __func__, + PTR_ERR(info->pull_up)); + ret = PTR_ERR(info->pull_up); + goto err_lookup_state; + } + + info->no_pull = pinctrl_lookup_state(info->pinctrl, "no_pull"); + if (IS_ERR_OR_NULL(info->no_pull)) { + dev_err(&pdev->dev, + "%s: Cannot get no_pull pinctrl state:%ld\n", __func__, + PTR_ERR(info->no_pull)); + ret = PTR_ERR(info->no_pull); + goto err_lookup_state; + } + + info->gpio = of_get_named_gpio(pdev->dev.of_node, + "audio,speaker-id-gpio", 0); + if (gpio_is_valid(info->gpio)) { + ret = gpio_request(info->gpio, "speaker-id"); + if (ret) { + dev_err(&pdev->dev, "%s: Failed to request gpio %d\n", + __func__, info->gpio); + goto err_lookup_state; + } + } + + dev_set_drvdata(&pdev->dev, info); + return 0; + +err_lookup_state: + devm_pinctrl_put(info->pinctrl); +err_pctrl_get: + devm_kfree(&pdev->dev, info); + return ret; +} + +static int spk_id_remove(struct platform_device *pdev) +{ + struct spk_id_info *info; + + info = dev_get_drvdata(&pdev->dev); + + if (info) { + if (info->pinctrl) + devm_pinctrl_put(info->pinctrl); + if (gpio_is_valid(info->gpio)) + gpio_free(info->gpio); + } + + devm_kfree(&pdev->dev, info); + return 0; +} + +static const struct of_device_id spk_id_match[] = { + { .compatible = "audio,speaker-id" }, + {} +}; + +static struct platform_driver spk_id_driver = { + .driver = { + .name = "spk-id", + .owner = THIS_MODULE, + .of_match_table = spk_id_match, + }, + .probe = spk_id_probe, + .remove = spk_id_remove, +}; +module_platform_driver(spk_id_driver); + +MODULE_DESCRIPTION("Speaker ID platform driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/mfd/spk-id.h b/include/linux/mfd/spk-id.h new file mode 100644 index 000000000000..1ca22e186ccd --- /dev/null +++ b/include/linux/mfd/spk-id.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPK_ID_H_ +#define __SPK_ID_H_ + +#include +#include + +#define PIN_PULL_DOWN 0 +#define PIN_PULL_UP 1 +#define PIN_FLOAT 2 + +#define VENDOR_ID_NONE 0 +#define VENDOR_ID_AAC 1 +#define VENDOR_ID_SSI 2 +#define VENDOR_ID_GOER 3 + +#define VENDOR_ID_UNKNOWN 4 + +int spk_id_get_pin_3state(struct device_node *np); +int spk_id_get(struct device_node *np); + +#endif From 69d662e8253416e991b7c082cbc7bbfddaa0a6e4 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:29:11 +0200 Subject: [PATCH 077/226] drivers: misc: Import AKM09970 driver * Run clang-format on source files Change-Id: I7b65cf4c0807c09d6d2a9f06e83ccdfe34afe43f Signed-off-by: firebird11 --- drivers/misc/Kconfig | 10 + drivers/misc/Makefile | 1 + drivers/misc/akm09970.c | 863 ++++++++++++++++++++++++++++++++++ include/uapi/linux/akm09970.h | 98 ++++ 4 files changed, 972 insertions(+) create mode 100644 drivers/misc/akm09970.c create mode 100644 include/uapi/linux/akm09970.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 2d4c9718efc8..d840c5508e77 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -595,6 +595,16 @@ config TEST_IRQ_REQUESTER If in doubt, say N. +config AKM09970 + tristate "INPUT_AK09970 digital hall sensor support" + depends on I2C + help + Say Y here if you have AKM Sensortec's AK09970 magnet + sensor hooked to an I2C bus. + + To compile this driver as a module, choose M here: the + module will be called akm09970. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 89fb698afadf..b8d2536975d7 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_FPR_FPC) += fpr_FingerprintCard/ obj-$(CONFIG_UID_SYS_STATS) += uid_sys_stats.o obj-$(CONFIG_MEMORY_STATE_TIME) += memory_state_time.o obj-$(CONFIG_QPNP_MISC) += qpnp-misc.o +obj-$(CONFIG_AKM09970) += akm09970.o obj-$(CONFIG_OKL4_USER_VIRQ) += okl4-virq.o obj-$(CONFIG_OKL4_RINGBUF) += okl4-ringbuf.o diff --git a/drivers/misc/akm09970.c b/drivers/misc/akm09970.c new file mode 100644 index 000000000000..0ca357f936bb --- /dev/null +++ b/drivers/misc/akm09970.c @@ -0,0 +1,863 @@ +/* drivers/intput/misc/akm09970.c - akm09970 compass driver + * + * Copyright (c) 2018-2019, Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +//#define DEBUG +#define pr_fmt(fmt) "akm09970: %s: %d " fmt, __func__, __LINE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "uapi/linux/akm09970.h" + +#define CLEAR_IRQ_TIME 20 + +static DECLARE_WAIT_QUEUE_HEAD(poll_wait_queue); + +struct akm09970_soc_ctrl { + uint8_t chip_info[AKM_SENSOR_INFO_SIZE]; + uint8_t chip_data[AKM_SENSOR_DATA_SIZE]; + uint8_t measure_range; + uint32_t measure_freq_hz; + bool read_flag; + + atomic_t power_enabled; + atomic_t data_ready; + + int gpio_reset; + int gpio_irq; + int irq; + + struct akm09970_platform_data pdata; + + dev_t dev_num; + struct device *dev; + struct cdev cdev; + struct class *chr_class; + struct device *chr_dev; + + struct device_node *of_node; + + struct i2c_client *client; + + struct pinctrl *pinctrl; + struct pinctrl_state *gpio_state_active; + struct pinctrl_state *gpio_state_suspend; + + struct regulator *vdd; + + struct hrtimer timer; + + struct work_struct report_work; + struct workqueue_struct *work_queue; +}; + +static int akm09970_write_byte(struct i2c_client *client, u8 reg, u8 val) +{ + int rc; + + if (client->irq) + disable_irq_nosync(client->irq); + + rc = i2c_smbus_write_byte_data(client, reg, val); + + if (client->irq) + enable_irq(client->irq); + + return rc; +} + +static int akm09970_set_reg_bits(struct i2c_client *client, int val, int shift, + u8 mask, u8 reg) +{ + int data; + + data = i2c_smbus_read_byte_data(client, reg); + if (data < 0) + return data; + + data = (data & ~mask) | ((val << shift) & mask); + pr_info("reg: 0x%x, data: 0x%x", reg, data); + return akm09970_write_byte(client, reg, data); +} + +static int akm09970_set_mode(struct akm09970_soc_ctrl *c_ctrl, uint8_t mode) +{ + int rc; + + rc = akm09970_set_reg_bits(c_ctrl->client, mode, AK09970_MODE_POS, + AK09970_MODE_MSK, AK09970_MODE_REG); + + return rc; +} + +static enum hrtimer_restart hrtimer_handler(struct hrtimer *timer_t) +{ + struct akm09970_soc_ctrl *c_ctrl = + container_of(timer_t, struct akm09970_soc_ctrl, timer); + + if (!c_ctrl->read_flag) + queue_work(c_ctrl->work_queue, &c_ctrl->report_work); + + return HRTIMER_NORESTART; +} + +static void akm09970_reset(struct akm09970_soc_ctrl *c_ctrl) +{ + gpio_set_value(c_ctrl->gpio_reset, 0); + udelay(50); + gpio_set_value(c_ctrl->gpio_reset, 1); + udelay(100); + + return; +} + +static int akm09970_power_down(struct akm09970_soc_ctrl *c_ctrl) +{ + int rc = 0; + + if (atomic_read(&c_ctrl->power_enabled)) { + gpio_set_value(c_ctrl->gpio_reset, 0); + + rc = regulator_disable(c_ctrl->vdd); + if (rc) { + pr_err("Regulator vdd disable failed rc=%d\n", rc); + } + atomic_set(&c_ctrl->power_enabled, 0); + pr_debug("Power down successfully"); + } + + return rc; +} + +static int akm09970_power_up(struct akm09970_soc_ctrl *c_ctrl) +{ + int rc = 0; + + if (!atomic_read(&c_ctrl->power_enabled)) { + rc = regulator_enable(c_ctrl->vdd); + if (rc) { + pr_err("Regulator vdd enable failed rc=%d\n", rc); + return rc; + } + udelay(20); + akm09970_reset(c_ctrl); + atomic_set(&c_ctrl->power_enabled, 1); + pr_debug("Power down successfully"); + } + + return rc; +} + +static int akm09970_active(struct akm09970_soc_ctrl *c_ctrl, bool on) +{ + int rc = 0; + uint8_t mode = 0x00; + + pr_info("akm sensor %s\n", on ? "on" : "off"); + + if (!atomic_read(&c_ctrl->power_enabled) && on) { + rc = akm09970_power_up(c_ctrl); + if (rc) { + pr_err("Sensor power up fail!\n"); + return rc; + } + + if (c_ctrl->measure_freq_hz >= 100) + mode = AK09970_MODE_CONTINUOUS_100HZ; + else if (c_ctrl->measure_freq_hz >= 50 && + c_ctrl->measure_freq_hz < 100) + mode = AK09970_MODE_CONTINUOUS_50HZ; + else if (c_ctrl->measure_freq_hz >= 20 && + c_ctrl->measure_freq_hz < 50) + mode = AK09970_MODE_CONTINUOUS_20HZ; + else + mode = AK09970_MODE_CONTINUOUS_10HZ; + + c_ctrl->measure_range = 0; + + rc = akm09970_write_byte(c_ctrl->client, AK09970_MODE_REG, + (mode | c_ctrl->measure_range)); + if (rc < 0) { + pr_err("Failed to set mode and smr."); + akm09970_power_down(c_ctrl); + return rc; + } + pr_info("reg: 0x%x, data: 0x%x", AK09970_MODE_REG, + (mode | c_ctrl->measure_range)); + + enable_irq(c_ctrl->irq); + hrtimer_start(&c_ctrl->timer, + ktime_set(CLEAR_IRQ_TIME / MSEC_PER_SEC, + (CLEAR_IRQ_TIME % MSEC_PER_SEC) * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + c_ctrl->read_flag = false; + pr_debug("Enable irq successfully"); + } else if (atomic_read(&c_ctrl->power_enabled) && !on) { + disable_irq_nosync(c_ctrl->irq); + cancel_work_sync(&c_ctrl->report_work); + c_ctrl->read_flag = false; + pr_err("Disable irq successfully"); + + rc = akm09970_set_mode(c_ctrl, AK09970_MODE_POWERDOWN); + if (rc) + pr_warn("Failed to set to POWERDOWN mode.\n"); + + akm09970_power_down(c_ctrl); + } else { + pr_info("The same power state, do nothing!"); + } + + return 0; +} + +static int akm09970_read_data(struct akm09970_soc_ctrl *c_ctrl) +{ + int rc = 0; + + rc = i2c_smbus_read_i2c_block_data(c_ctrl->client, AK09970_REG_ST_XYZ, + AKM_SENSOR_DATA_SIZE, + c_ctrl->chip_data); + if (rc < 0) { + pr_err("read data failed!"); + return rc; + } + + if (AKM_ERRADC_IS_HIGH(c_ctrl->chip_data[0])) { + pr_err("ADC over run!\n"); + rc = -EIO; + } + + if (AKM_ERRXY_IS_HIGH(c_ctrl->chip_data[1])) { + pr_err("Errxy over run!\n"); + rc = -EIO; + } + + return 0; +} + +static void akm09970_dev_work_queue(struct work_struct *work) +{ + int rc = 0; + struct akm09970_soc_ctrl *c_ctrl = + container_of(work, struct akm09970_soc_ctrl, report_work); + + rc = akm09970_read_data(c_ctrl); + if (rc < 0) { + atomic_set(&c_ctrl->data_ready, 0); + pr_warn("Failed to read data"); + } else { + atomic_set(&c_ctrl->data_ready, 1); + wake_up(&poll_wait_queue); + c_ctrl->read_flag = true; + } +} + +static irqreturn_t akm09970_irq_handler(int irq, void *dev_id) +{ + struct akm09970_soc_ctrl *c_ctrl = dev_id; + + queue_work(c_ctrl->work_queue, &c_ctrl->report_work); + + return IRQ_HANDLED; +} + +static int akm09970_release(struct inode *inp, struct file *filp) +{ + int rc = 0; + + return rc; +} + +static int akm09970_open(struct inode *inp, struct file *filp) +{ + int rc = 0; + struct akm09970_soc_ctrl *c_ctrl = + container_of(inp->i_cdev, struct akm09970_soc_ctrl, cdev); + + filp->private_data = c_ctrl; + + pr_debug("open enter, irq = %d\n", c_ctrl->irq); + + return rc; +} + +static ssize_t akm09970_write(struct file *filp, const char *buf, size_t len, + loff_t *fseek) +{ + int rc = 0; + + return rc; +} + +static ssize_t akm09970_read(struct file *filp, char *buf, size_t len, + loff_t *fseek) +{ + int rc = 0; + + return rc; +} + +static unsigned int akm09970_poll(struct file *filp, poll_table *wait) +{ + unsigned int mask = 0; + struct akm09970_soc_ctrl *c_ctrl = filp->private_data; + + pr_debug("Poll enter\n"); + + poll_wait(filp, &poll_wait_queue, wait); + if (atomic_read(&c_ctrl->data_ready)) { + atomic_set(&c_ctrl->data_ready, 0); + mask = POLLIN | POLLRDNORM; + } + + return mask; +} + +static long akm09970_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int rc = 0; + int i = 0; + struct akm09970_soc_ctrl *c_ctrl = filp->private_data; + + if (NULL == c_ctrl) { + pr_err("NULL"); + return -EFAULT; + } + + if (_IOC_TYPE(cmd) != AKM_IOC_MAGIC) { + pr_err("magic number worng"); + return -ENODEV; + } + + if (_IOC_DIR(cmd) & _IOC_READ) + rc = !access_ok(VERIFY_WRITE, (void __user *)arg, + _IOC_SIZE(cmd)); + else if (_IOC_DIR(cmd) & _IOC_WRITE) + rc = !access_ok(VERIFY_READ, (void __user *)arg, + _IOC_SIZE(cmd)); + if (rc) { + pr_err("access failed"); + return -EFAULT; + } + + if (_IOC_DIR(cmd) & _IOC_WRITE) { + if (copy_from_user(&c_ctrl->pdata, (void __user *)arg, + sizeof(struct akm09970_platform_data))) { + pr_err("Copy data from user space failed"); + return -EFAULT; + } + } + + switch (cmd) { + case AKM_IOC_SET_ACTIVE: + pr_err("AKM_IOC_SET_ACTIVE, c_ctrl->pdata.sensor_state = %d\n", + c_ctrl->pdata.sensor_state); + rc = akm09970_active(c_ctrl, c_ctrl->pdata.sensor_state); + break; + case AKM_IOC_SET_MODE: + pr_err("AKM_IOC_SET_MODE, c_ctrl->pdata.sensor_mode = %d\n", + c_ctrl->pdata.sensor_mode); + c_ctrl->measure_freq_hz = c_ctrl->pdata.sensor_mode; + //rc = akm09970_set_mode(pctrl, mode); + break; + case AKM_IOC_GET_SENSSMR: + pr_err("AKM_IOC_GET_SENSSMR, c_ctrl->measure_range = %d", + c_ctrl->measure_range); + c_ctrl->pdata.sensor_smr = c_ctrl->measure_range; + break; + case AKM_IOC_GET_SENSEDATA: + pr_debug("AKM_IOC_GET_SENSEDATA"); + for (i = 0; i < AKM_SENSOR_DATA_SIZE; i++) { + c_ctrl->pdata.data[i] = c_ctrl->chip_data[i]; + pr_debug("data%d = %d\n", i, c_ctrl->chip_data[i]); + } + break; + default: + pr_warn("unsupport cmd:0x%x\n", cmd); + break; + } + + if (_IOC_DIR(cmd) & _IOC_READ) { + if (copy_to_user((void __user *)arg, &c_ctrl->pdata, + sizeof(struct akm09970_platform_data))) { + pr_err("Copy data from user space failed"); + return -EFAULT; + } + } + + return rc; +} + +#ifdef CONFIG_COMPAT +static long akm09970_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return akm09970_ioctl(filp, cmd, (unsigned long)compat_ptr(arg)); +} +#endif + +static const struct file_operations akm09970_fops = { + .owner = THIS_MODULE, + .open = akm09970_open, + .release = akm09970_release, + .read = akm09970_read, + .write = akm09970_write, + .unlocked_ioctl = akm09970_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = akm09970_compat_ioctl, +#endif + .poll = akm09970_poll, +}; + +static int akm09970_check_device_id(struct akm09970_soc_ctrl *c_ctrl) +{ + int rc = 0; + + rc = akm09970_power_up(c_ctrl); + if (rc < 0) + return rc; + + rc = i2c_smbus_read_i2c_block_data(c_ctrl->client, AK09970_REG_WIA, + AKM_SENSOR_INFO_SIZE, + c_ctrl->chip_info); + if (rc < 0) + goto exit; + + if ((c_ctrl->chip_info[0] != AK09970_WIA1_VALUE) || + (c_ctrl->chip_info[1] != AK09970_WIA2_VALUE)) { + pr_err("The device is not AKM Hall sensor\n"); + rc = -ENXIO; + } + +exit: + akm09970_power_down(c_ctrl); + + return rc; +} + +static ssize_t akm09970_chip_rev_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct akm09970_soc_ctrl *c_ctrl = dev_get_drvdata(dev); + + return sprintf(buf, "%x,%x\n", (char)c_ctrl->chip_info[0], + (char)c_ctrl->chip_info[1]); +} +static DEVICE_ATTR(chip_rev, S_IRUGO, akm09970_chip_rev_show, NULL); + +static struct device_attribute *akm_attrs[] = { + &dev_attr_chip_rev, +}; + +static int akm09970_regulator_init(struct akm09970_soc_ctrl *c_ctrl, bool on) +{ + int rc; + + if (on) { + c_ctrl->vdd = regulator_get(&c_ctrl->client->dev, "vdd"); + if (IS_ERR(c_ctrl->vdd)) { + rc = PTR_ERR(c_ctrl->vdd); + pr_err("Regulator get failed vdd rc=%d", rc); + return rc; + } + + if (regulator_count_voltages(c_ctrl->vdd) > 0) { + rc = regulator_set_voltage(c_ctrl->vdd, + AKM09970_VDD_MIN_UV, + AKM09970_VDD_MAX_UV); + if (rc) { + pr_err("Regulator set failed vdd rc=%d", rc); + regulator_put(c_ctrl->vdd); + return rc; + } + } + } else { + if (regulator_count_voltages(c_ctrl->vdd) > 0) + regulator_set_voltage(c_ctrl->vdd, 0, + AKM09970_VDD_MAX_UV); + + regulator_put(c_ctrl->vdd); + } + + return 0; +} + +static int akm09970_gpio_config(struct akm09970_soc_ctrl *c_ctrl) +{ + int32_t rc = 0; + + rc = gpio_request_one(c_ctrl->gpio_reset, GPIOF_OUT_INIT_LOW, + "akm09970-reset"); + if (rc < 0) { + pr_err("Failed to request power enable GPIO %d", + c_ctrl->gpio_reset); + goto reset_gpio_req_err; + } + gpio_direction_output(c_ctrl->gpio_reset, 0); + + rc = gpio_request_one(c_ctrl->gpio_irq, GPIOF_IN, "akm09970-irq"); + if (rc < 0) { + pr_err("Failed to request power enable GPIO %d", + c_ctrl->gpio_irq); + goto irq_gpio_req_err; + } else { + gpio_direction_input(c_ctrl->gpio_irq); + c_ctrl->irq = gpio_to_irq(c_ctrl->gpio_irq); + rc = request_threaded_irq(c_ctrl->irq, akm09970_irq_handler, + NULL, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "akm09970_irq", c_ctrl); + if (rc < 0) { + pr_err("Unable to request irq\n"); + goto irq_req_err; + } + disable_irq_nosync(c_ctrl->irq); + } + + return 0; + +irq_req_err: + if (gpio_is_valid(c_ctrl->gpio_irq)) { + if (c_ctrl->irq) + free_irq(c_ctrl->irq, c_ctrl); + gpio_free(c_ctrl->gpio_irq); + } + +irq_gpio_req_err: + if (gpio_is_valid(c_ctrl->gpio_reset)) + gpio_free(c_ctrl->gpio_reset); + +reset_gpio_req_err: + return rc; +} + +static int akm09970_pinctrl_select(struct akm09970_soc_ctrl *c_ctrl, bool state) +{ + int rc = 0; + struct pinctrl_state *pins_state = state ? (c_ctrl->gpio_state_active) : + (c_ctrl->gpio_state_suspend); + + rc = pinctrl_select_state(c_ctrl->pinctrl, pins_state); + if (rc < 0) + pr_err("Failed to select pins state %s\n", + state ? "active" : "suspend"); + + return rc; +} + +static int akm09970_pinctrl_init(struct akm09970_soc_ctrl *c_ctrl) +{ + int rc = 0; + struct device *dev = c_ctrl->dev; + + c_ctrl->pinctrl = devm_pinctrl_get(dev); + if (IS_ERR_OR_NULL(c_ctrl->pinctrl)) { + rc = PTR_ERR(c_ctrl->pinctrl); + pr_err("Unable to acquire pinctrl %d", rc); + goto err_pinctrl_get; + } + + c_ctrl->gpio_state_active = + pinctrl_lookup_state(c_ctrl->pinctrl, "akm09970_gpio_active"); + if (IS_ERR_OR_NULL(c_ctrl->gpio_state_active)) { + pr_err("Cannot lookup active pinctrl state\n"); + rc = PTR_ERR(c_ctrl->gpio_state_active); + goto err_pinctrl_lookup; + } + + c_ctrl->gpio_state_suspend = + pinctrl_lookup_state(c_ctrl->pinctrl, "akm09970_gpio_suspend"); + if (IS_ERR_OR_NULL(c_ctrl->gpio_state_suspend)) { + pr_err("Cannot lookup suspend pinctrl state\n"); + rc = PTR_ERR(c_ctrl->gpio_state_suspend); + goto err_pinctrl_lookup; + } + + return 0; + +err_pinctrl_lookup: + devm_pinctrl_put(c_ctrl->pinctrl); +err_pinctrl_get: + c_ctrl->pinctrl = NULL; + + return rc; +} + +static int akm09970_parse_dt(struct device *dev, + struct akm09970_soc_ctrl *c_ctrl) +{ + int rc = 0; + + c_ctrl->gpio_reset = of_get_named_gpio_flags(dev->of_node, + "akm,gpio-reset", 0, NULL); + if (!gpio_is_valid(c_ctrl->gpio_reset)) { + pr_err("Gpio reset pin %d is invalid.", c_ctrl->gpio_reset); + return -EINVAL; + } + + c_ctrl->gpio_irq = + of_get_named_gpio_flags(dev->of_node, "akm,gpio-irq", 0, NULL); + if (!gpio_is_valid(c_ctrl->gpio_irq)) { + pr_err("gpio irq pin %d is invalid.", c_ctrl->gpio_irq); + return -EINVAL; + } + + return rc; +} + +static int akm09970_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int rc = 0; + struct akm09970_soc_ctrl *c_ctrl = NULL; + + pr_debug("Probe enter"); + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + pr_err("check_functionality failed."); + return -ENODEV; + } + + /* Allocate memory for driver data */ + c_ctrl = devm_kzalloc(&client->dev, sizeof(struct akm09970_soc_ctrl), + GFP_KERNEL); + if (!c_ctrl) { + pr_err("Alloc memory failed."); + return -ENOMEM; + } + + pr_debug("Start parse device tree"); + if (client->dev.of_node) { + rc = akm09970_parse_dt(&client->dev, c_ctrl); + if (rc < 0) { + pr_err("Unable to parse platfrom data rc=%d\n", rc); + goto exit; + } + } + + c_ctrl->dev = &client->dev; + c_ctrl->client = client; + i2c_set_clientdata(client, c_ctrl); + + rc = akm09970_pinctrl_init(c_ctrl); + if (rc) { + pr_err("Failed to initialize pinctrl\n"); + goto exit; + } else { + if (c_ctrl->pinctrl) { + rc = akm09970_pinctrl_select(c_ctrl, true); + if (rc < 0) { + pr_err("Failed to select default pinstate %d\n", + rc); + goto err_select_pinctrl; + } + } + } + + rc = akm09970_gpio_config(c_ctrl); + if (rc < 0) { + pr_err("Failed to config gpio\n"); + goto err_select_pinctrl; + } + + rc = akm09970_regulator_init(c_ctrl, true); + if (rc < 0) + goto err_regulator_init; + + rc = akm09970_check_device_id(c_ctrl); + if (rc < 0) + goto err_check_device; + + atomic_set(&c_ctrl->power_enabled, 0); + + pr_err("IRQ is #%d.", c_ctrl->irq); + + hrtimer_init(&c_ctrl->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + c_ctrl->timer.function = hrtimer_handler; + c_ctrl->work_queue = + alloc_workqueue("akm09970_poll_work_queue", + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI, 1); + INIT_WORK(&c_ctrl->report_work, akm09970_dev_work_queue); + + c_ctrl->chr_class = class_create(THIS_MODULE, AKM09970_CLASS_NAME); + if (c_ctrl->chr_class == NULL) { + pr_err("Failed to create class.\n"); + rc = -ENODEV; + goto err_check_device; + } + + rc = alloc_chrdev_region(&c_ctrl->dev_num, 0, 1, AKM09970_DRV_NAME); + if (rc < 0) { + pr_err("Failed to allocate chrdev region\n"); + goto err_destroy_class; + } + + c_ctrl->chr_dev = device_create(c_ctrl->chr_class, NULL, + c_ctrl->dev_num, c_ctrl, + AKM09970_DRV_NAME); + if (IS_ERR(c_ctrl->chr_dev)) { + pr_err("Failed to create char device\n"); + rc = PTR_ERR(c_ctrl->chr_dev); + goto err_unregister_chrdev; + } + + cdev_init(&(c_ctrl->cdev), &akm09970_fops); + c_ctrl->cdev.owner = THIS_MODULE; + + rc = cdev_add(&(c_ctrl->cdev), c_ctrl->dev_num, 1); + if (rc < 0) { + pr_err("Failed to add cdev\n"); + goto err_destroy_device; + } + + rc = device_create_file(c_ctrl->chr_dev, akm_attrs[0]); + if (rc < 0) + pr_err("Failed to create debug file: %d\n", rc); + + pr_err("Probe exit"); + + return 0; + +err_destroy_device: + if (c_ctrl->chr_dev) + device_destroy(c_ctrl->chr_class, c_ctrl->dev_num); + +err_unregister_chrdev: + unregister_chrdev_region(c_ctrl->dev_num, 1); +err_destroy_class: + if (c_ctrl->chr_class) + class_destroy(c_ctrl->chr_class); + +err_check_device: + akm09970_regulator_init(c_ctrl, false); + +err_regulator_init: + if (gpio_is_valid(c_ctrl->gpio_irq)) { + if (c_ctrl->irq) + free_irq(c_ctrl->irq, c_ctrl); + gpio_free(c_ctrl->gpio_irq); + } + + if (gpio_is_valid(c_ctrl->gpio_reset)) + gpio_free(c_ctrl->gpio_reset); + +err_select_pinctrl: + if (c_ctrl->pinctrl) { + devm_pinctrl_put(c_ctrl->pinctrl); + c_ctrl->pinctrl = NULL; + } + +exit: + return rc; +} + +static int akm09970_remove(struct i2c_client *client) +{ + struct akm09970_soc_ctrl *c_ctrl = i2c_get_clientdata(client); + + cancel_work_sync(&c_ctrl->report_work); + destroy_workqueue(c_ctrl->work_queue); + + if (&(c_ctrl->cdev)) + cdev_del(&(c_ctrl->cdev)); + + if (c_ctrl->chr_dev) + device_destroy(c_ctrl->chr_class, c_ctrl->dev_num); + + unregister_chrdev_region(c_ctrl->dev_num, 1); + if (c_ctrl->chr_class) + class_destroy(c_ctrl->chr_class); + + akm09970_power_down(c_ctrl); + + akm09970_regulator_init(c_ctrl, false); + + if (gpio_is_valid(c_ctrl->gpio_irq)) { + if (c_ctrl->irq) + free_irq(c_ctrl->irq, c_ctrl); + gpio_free(c_ctrl->gpio_irq); + } + + if (gpio_is_valid(c_ctrl->gpio_reset)) + gpio_free(c_ctrl->gpio_reset); + + if (c_ctrl->pinctrl) { + devm_pinctrl_put(c_ctrl->pinctrl); + c_ctrl->pinctrl = NULL; + } + + pr_debug("Removed exit"); + + return 0; +} + +static const struct i2c_device_id akm09970_id[] = { + { AKM09970_DRV_NAME, 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, akm09970_id); + +static struct of_device_id akm09970_match_table[] = { + { + .compatible = "akm,akm09970", + }, + {}, +}; + +static struct i2c_driver akm09970_driver = { + .driver = { + .name = AKM09970_DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = akm09970_match_table, + }, + .probe = akm09970_probe, + .remove = akm09970_remove, + .id_table = akm09970_id, +}; + +module_i2c_driver(akm09970_driver); + +MODULE_AUTHOR("zhunengjin "); +MODULE_DESCRIPTION("AKM compass driver"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("2.0"); diff --git a/include/uapi/linux/akm09970.h b/include/uapi/linux/akm09970.h new file mode 100644 index 000000000000..c6f8cc4874d4 --- /dev/null +++ b/include/uapi/linux/akm09970.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* + * Copyright (c) 2018-2019, Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef __AKM09970_H__ +#define __AKM09970_H__ + +#include +#include + +//#define pr_fmt(fmt) "akm09970: %s: %d " fmt, __func__, __LINE__ + +#define AKM09970_DRV_NAME "akm09970" +#define AKM09970_CLASS_NAME "akm" + +/* AKM09970 Driver Magic Number */ +#define AKM_IOC_MAGIC 'M' + +#define AKM_PRIVATE 109 + +/* Device specific constant values */ +#define AK09970_REG_WIA 0x00 +#define AK09970_REG_ST_XYZ 0x17 +#define AK09970_REG_CNTL1 0x20 +#define AK09970_REG_CNTL2 0x21 +#define AK09970_REG_RESET 0x30 + +#define AK09970_RESET_DATA 0x01 + +#define AK09970_WIA1_VALUE 0x48 +#define AK09970_WIA2_VALUE 0xC0 + +#define AK09970_MODE_POWERDOWN 0x00 +#define AK09970_MODE_CONTINUOUS_10HZ 0x08 /* 10Hz */ +#define AK09970_MODE_CONTINUOUS_20HZ 0x0A /* 20Hz */ +#define AK09970_MODE_CONTINUOUS_50HZ 0x0C /* 50Hz */ +#define AK09970_MODE_CONTINUOUS_100HZ 0x0E /* 100Hz */ + +#define AKM_SENSOR_INFO_SIZE 2 +#define AKM_SENSOR_CONF_SIZE 3 +#define AKM_SENSOR_DATA_SIZE 8 + +#define AK09970_MODE_POS 0 +#define AK09970_MODE_MSK 0x0F +#define AK09970_MODE_REG AK09970_REG_CNTL2 + +#define AK09970_SDR_MODE_POS 4 +#define AK09970_SDR_MODE_MSK 0x10 +#define AK09970_SDR_MODE_REG AK09970_REG_CNTL2 + +#define AK09970_SMR_MODE_POS 5 +#define AK09970_SMR_MODE_MSK 0x20 +#define AK09970_SMR_MODE_REG AK09970_REG_CNTL2 + +#define AKM_DRDY_IS_HIGH(x) ((x) & 0x01) +#define AKM_DOR_IS_HIGH(x) ((x) & 0x02) +#define AKM_ERRADC_IS_HIGH(x) ((x) & 0x01) +#define AKM_ERRXY_IS_HIGH(x) ((x) & 0x80) + +#define AK09970_SENS_Q16 ((int32_t)(72090)) /* 1.1uT in Q16 format */ + +#define AKM_DRDY_TIMEOUT_MS 100 +#define AKM_DEFAULT_MEASURE_HZ 10 + +/* POWER SUPPLY VOLTAGE RANGE */ +#define AKM09970_VDD_MIN_UV 1800000 +#define AKM09970_VDD_MAX_UV 1800000 + +#define PWM_PERIOD_DEFAULT_NS 1000000 + +struct akm09970_platform_data { + uint8_t sensor_smr; + uint8_t sensor_mode; + uint8_t sensor_state; + uint8_t data[AKM_SENSOR_DATA_SIZE]; +}; + +/* IOC CMD */ +#define AKM_IOC_SET_ACTIVE \ + _IOW(AKM_IOC_MAGIC, AKM_PRIVATE + 1, struct akm09970_platform_data) + +#define AKM_IOC_SET_MODE \ + _IOW(AKM_IOC_MAGIC, AKM_PRIVATE + 2, struct akm09970_platform_data) + +#define AKM_IOC_GET_SENSEDATA \ + _IOR(AKM_IOC_MAGIC, AKM_PRIVATE + 4, struct akm09970_platform_data) + +#define AKM_IOC_GET_SENSSMR \ + _IOR(AKM_IOC_MAGIC, AKM_PRIVATE + 5, struct akm09970_platform_data) + +#endif /* __AKM09970_H__ */ From 8944550297fcb8a5971f3b80199f10a6afe926f0 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:29:53 +0200 Subject: [PATCH 078/226] drivers: misc: Import DRV8846 driver * Run clang-format on source files Change-Id: I41c3c9ba9400cdfefe1c0d523a7cefcce86ee5f7 Signed-off-by: firebird11 --- drivers/misc/Kconfig | 8 + drivers/misc/Makefile | 1 + drivers/misc/drv8846.c | 741 ++++++++++++++++++++++++++++++++++++ include/uapi/misc/drv8846.h | 48 +++ 4 files changed, 798 insertions(+) create mode 100644 drivers/misc/drv8846.c create mode 100644 include/uapi/misc/drv8846.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d840c5508e77..f3c1f626d72e 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -605,6 +605,14 @@ config AKM09970 To compile this driver as a module, choose M here: the module will be called akm09970. +config TI_DRV8846 + tristate "TI step motor driver IC" + depends on PWM + help + Say 'y' here to include support for the H-Bridge Stepper + Motor Driver. The MISC peripheral holds the pwm and the + driver provides an API to drive stepper motor. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b8d2536975d7..c7d61c0d1ac7 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_UID_SYS_STATS) += uid_sys_stats.o obj-$(CONFIG_MEMORY_STATE_TIME) += memory_state_time.o obj-$(CONFIG_QPNP_MISC) += qpnp-misc.o obj-$(CONFIG_AKM09970) += akm09970.o +obj-$(CONFIG_TI_DRV8846) += drv8846.o obj-$(CONFIG_OKL4_USER_VIRQ) += okl4-virq.o obj-$(CONFIG_OKL4_RINGBUF) += okl4-ringbuf.o diff --git a/drivers/misc/drv8846.c b/drivers/misc/drv8846.c new file mode 100644 index 000000000000..6b46408f0c41 --- /dev/null +++ b/drivers/misc/drv8846.c @@ -0,0 +1,741 @@ +/* drivers/misc/drv8846.c - drv8846 step motor soc driver + * + * Copyright (c) 2014-2015, Linux Foundation. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define DEBUG +#define pr_fmt(fmt) "drv8846: %s: %d " fmt, __func__, __LINE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV8846_DEV_NAME "ti,drv8846" + +#define PWM_PERIOD_DEFAULT_NS 1000000 +#define RAMP_PERIOD_DEFAULT_NS 625000 +#define RAMP_DURATION_DEFAULT_MS 50 +#define HIGH_PERIOD_DEFAULT_NS 52083 +#define HIGH_DURATION_DEFAULT_MS 700 +#define DEFAULT_STEP_MODE 2 + +static DECLARE_WAIT_QUEUE_HEAD(poll_wait_queue); + +struct pwm_setting { + u64 pre_period_ns; + u64 period_ns; + u64 duty_ns; +}; + +struct drv8846_soc_ctrl { + struct platform_device *pdev; + struct miscdevice miscdev; + struct dentry *debugfs; + struct device_node *of_node; + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_default; + + struct pwm_device *pwm_dev; + struct pwm_setting pwm_setting; + struct hrtimer pwm_timer; + struct work_struct pwm_apply_work; + + atomic_t move_done; + + struct mutex motor_mutex; + struct fasync_struct *async; + + uint32_t rampup_period_ns; + uint32_t high_period_ns; + uint32_t rampdown_period_ns; + uint32_t high_duration_ms; + uint32_t rampup_duration_ms; + uint32_t rampdown_duration_ms; + uint32_t step_mode; + uint32_t direction; + + int gpio_mode0; + int gpio_mode1; + int gpio_dir; + int gpio_sleep; + int gpio_pwren; + + enum running_state state; +}; + +static int __drv8846_config_pwm(struct drv8846_soc_ctrl *mctrl, + struct pwm_setting *pwm) +{ + int rc; + struct pwm_state pstate; + + pwm_get_state(mctrl->pwm_dev, &pstate); + pstate.enabled = !!(pwm->duty_ns != 0); + pstate.period = pwm->period_ns; + pstate.duty_cycle = pwm->duty_ns; + pstate.output_type = PWM_OUTPUT_FIXED; + pstate.output_pattern = NULL; + pr_debug("enable %d\n", pstate.enabled); + rc = pwm_apply_state(mctrl->pwm_dev, &pstate); + if (rc < 0) + pr_err("Apply PWM state failed, rc=%d\n", rc); + + if (pstate.enabled == false) { + gpio_direction_output(mctrl->gpio_sleep, 0); + kill_fasync(&mctrl->async, SIGIO, POLL_IN); + atomic_set(&mctrl->move_done, 1); + wake_up(&poll_wait_queue); + } else { + gpio_direction_output(mctrl->gpio_sleep, 1); + } + return rc; +} + +static void pwm_config_work(struct work_struct *work) +{ + struct drv8846_soc_ctrl *mctrl = + container_of(work, struct drv8846_soc_ctrl, pwm_apply_work); + struct pwm_setting setting; + + setting = mctrl->pwm_setting; + + __drv8846_config_pwm(mctrl, &setting); +} + +static enum hrtimer_restart pwm_hrtimer_handler(struct hrtimer *timer) +{ + uint32_t duration_ms = 0; + struct drv8846_soc_ctrl *mctrl = + container_of(timer, struct drv8846_soc_ctrl, pwm_timer); + + switch (mctrl->state) { + case SPEEDUP: + mctrl->state = FULLSTEAM; + duration_ms = mctrl->high_duration_ms; + /* reconfig the pwm and timer to fast running mode. */ + mctrl->pwm_setting.period_ns = mctrl->high_period_ns; + mctrl->pwm_setting.pre_period_ns = mctrl->high_period_ns; + mctrl->pwm_setting.duty_ns = mctrl->high_period_ns >> 1; + if (mctrl->direction == DOWN) + duration_ms += DELTAMS; + hrtimer_forward_now(&mctrl->pwm_timer, + ktime_set(duration_ms / MSEC_PER_SEC, + (duration_ms % MSEC_PER_SEC) * + NSEC_PER_MSEC)); + break; + case FULLSTEAM: + mctrl->state = SLOWDOWN; + duration_ms = mctrl->rampdown_duration_ms; + /* reconfig the pwm and timer to slow mode(brake down) */ + mctrl->pwm_setting.period_ns = mctrl->rampdown_period_ns; + mctrl->pwm_setting.pre_period_ns = mctrl->rampdown_period_ns; + mctrl->pwm_setting.duty_ns = mctrl->rampdown_period_ns >> 1; + hrtimer_forward_now(&mctrl->pwm_timer, + ktime_set(duration_ms / MSEC_PER_SEC, + (duration_ms % MSEC_PER_SEC) * + NSEC_PER_MSEC)); + break; + case SLOWDOWN: + case UNIFORMSPEED: + mctrl->state = STILL; + /* should stop timer and pwm. */ + mctrl->pwm_setting.duty_ns = 0; + break; + default: + mctrl->pwm_setting.duty_ns = 0; + pr_info("default state."); + } + schedule_work(&mctrl->pwm_apply_work); + + if (mctrl->state == STILL) + return HRTIMER_NORESTART; + else + return HRTIMER_RESTART; +} + +void drv8846_move(struct drv8846_soc_ctrl *mctrl, uint8_t dir) +{ + pr_debug("move %s\n", dir ? "up" : "down"); + + hrtimer_start(&mctrl->pwm_timer, + ktime_set(mctrl->rampup_duration_ms / MSEC_PER_SEC, + (mctrl->rampup_duration_ms % MSEC_PER_SEC) * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + mctrl->state = SPEEDUP; + mctrl->direction = dir; + + gpio_direction_output(mctrl->gpio_dir, (dir == UP) ? 0 : 1); + gpio_direction_output(mctrl->gpio_sleep, 1); + + mctrl->pwm_setting.period_ns = mctrl->rampup_period_ns; + mctrl->pwm_setting.pre_period_ns = mctrl->rampup_period_ns; + mctrl->pwm_setting.duty_ns = mctrl->rampup_period_ns >> 1; + schedule_work(&mctrl->pwm_apply_work); +} + +static int drv8846_fasync(int fd, struct file *filp, int mode) +{ + struct drv8846_soc_ctrl *mctrl = filp->private_data; + + pr_debug("mctrl %p, application fasync!", mctrl); + return fasync_helper(fd, filp, mode, &mctrl->async); +} + +static unsigned int drv8846_poll(struct file *filp, poll_table *wait) +{ + unsigned int mask = 0; + struct drv8846_soc_ctrl *mctrl = filp->private_data; + + pr_debug("Poll enter\n"); + + poll_wait(filp, &poll_wait_queue, wait); + if (atomic_read(&mctrl->move_done)) { + atomic_set(&mctrl->move_done, 0); + mask = POLLIN | POLLRDNORM; + } + + return mask; +} + +static long drv8846_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int rc = 0; + uint8_t direction = 0; + ktime_t time_rem; + long time_ms = 0; + struct op_parameter parameters; + struct drv8846_soc_ctrl *mctrl = filp->private_data; + + pr_debug("enter, mctrl %p", mctrl); + + if (mctrl == NULL) + return -EFAULT; + + switch (cmd) { + case MOTOR_IOC_SET_AUTORUN: + pr_debug("MOTOR_IOCAUTORUN."); + if (copy_from_user(&direction, (uint8_t *)arg, + sizeof(uint8_t))) { + pr_err("Failed to copy direction from user to kernel\n"); + rc = -EFAULT; + break; + } + drv8846_move(mctrl, direction); + break; + case MOTOR_IOC_SET_MANUALRUN: + pr_debug("MOTOR_IOCMANUAL\n"); + if (copy_from_user(¶meters, (struct op_parameter *)arg, + sizeof(struct op_parameter))) { + pr_err("Failed to copy target position from user to kernel\n"); + rc = -EFAULT; + break; + } + pr_debug("dir %d, duration %dms, period %dns.", parameters.dir, + parameters.duration_ms, parameters.period_ns); + + /* configure pwm */ + gpio_direction_output(mctrl->gpio_dir, + (parameters.dir == UP) ? 0 : 1); + gpio_direction_output(mctrl->gpio_sleep, 1); + + mctrl->pwm_setting.period_ns = parameters.period_ns; + mctrl->pwm_setting.pre_period_ns = parameters.period_ns; + mctrl->pwm_setting.duty_ns = parameters.period_ns >> 1; + schedule_work(&mctrl->pwm_apply_work); + /* start hrtimer */ + hrtimer_start( + &mctrl->pwm_timer, + ktime_set(parameters.duration_ms / MSEC_PER_SEC, + (parameters.duration_ms % MSEC_PER_SEC) * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + mctrl->state = UNIFORMSPEED; + break; + case MOTOR_IOC_GET_REMAIN_TIME: + if (hrtimer_active(&mctrl->pwm_timer)) { + time_rem = hrtimer_get_remaining(&mctrl->pwm_timer); + time_ms = (long)ktime_to_ms(time_rem); + } + if (copy_to_user((void __user *)arg, &time_ms, sizeof(long))) { + pr_err("copy_to_user failed."); + return -EFAULT; + } + break; + case MOTOR_IOC_GET_STATE: + if (copy_to_user((void __user *)arg, &mctrl->state, + sizeof(enum running_state))) { + pr_err("copy_to_user failed."); + return -EFAULT; + } + break; + default: + pr_warn("unsupport cmd:0x%x\n", cmd); + break; + } + + return rc; +} + +#ifdef CONFIG_COMPAT +static long drv8846_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return drv8846_ioctl(filp, cmd, (unsigned long)compat_ptr(arg)); +} +#endif + +static int drv8846_open(struct inode *inode, struct file *filp) +{ + struct drv8846_soc_ctrl *mctrl = NULL; + + pr_debug("enter\n"); + + mctrl = container_of(filp->private_data, struct drv8846_soc_ctrl, + miscdev); + filp->private_data = mctrl; + + atomic_set(&mctrl->move_done, 0); + + pr_debug("mctrl: %p\n", mctrl); + + return 0; +} + +static int drv8846_release(struct inode *inode, struct file *file) +{ + struct drv8846_soc_ctrl *mctrl = file->private_data; + + atomic_set(&mctrl->move_done, 0); + + pr_debug("mctrl %p.", mctrl); + + return 0; +} + +static const struct file_operations drv8846_fops = { + .owner = THIS_MODULE, + .open = drv8846_open, + .release = drv8846_release, + .unlocked_ioctl = drv8846_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = drv8846_compat_ioctl, +#endif + .fasync = drv8846_fasync, + .poll = drv8846_poll, +}; + +static int drv8846_pinctrl_init(struct drv8846_soc_ctrl *mctrl) +{ + int rc = 0; + /* Get pinctrl if target uses pinctrl */ + mctrl->pinctrl = devm_pinctrl_get(&mctrl->pdev->dev); + + if (IS_ERR_OR_NULL(mctrl->pinctrl)) { + rc = PTR_ERR(mctrl->pinctrl); + pr_err("Target does not use pinctrl %d\n", rc); + goto err_pinctrl_get; + } + + mctrl->pinctrl_default = + pinctrl_lookup_state(mctrl->pinctrl, "default"); + + if (IS_ERR_OR_NULL(mctrl->pinctrl_default)) { + rc = PTR_ERR(mctrl->pinctrl_default); + pr_err("Can not lookup default pinstate %d\n", rc); + goto err_pinctrl_lookup; + } + + return 0; + +err_pinctrl_lookup: + devm_pinctrl_put(mctrl->pinctrl); +err_pinctrl_get: + mctrl->pinctrl = NULL; + + return rc; +} + +static int drv8846_gpio_config(struct drv8846_soc_ctrl *mctrl) +{ + int32_t rc = 0; + + rc = gpio_request_one(mctrl->gpio_mode0, GPIOF_OUT_INIT_HIGH, + "motor-mode0"); + if (rc < 0) { + pr_err("Failed to request mode0 GPIO %d", mctrl->gpio_mode0); + goto fail0; + } + gpio_direction_output(mctrl->gpio_mode0, (mctrl->step_mode & 0x01)); + + rc = gpio_request_one(mctrl->gpio_mode1, GPIOF_OUT_INIT_HIGH, + "motor-mode1"); + if (rc < 0) { + pr_err("Failed to request mode1 GPIO %d", mctrl->gpio_mode1); + goto fail1; + } + gpio_direction_output(mctrl->gpio_mode1, (mctrl->step_mode & 0x02)); + + rc = gpio_request_one(mctrl->gpio_dir, GPIOF_OUT_INIT_HIGH, + "motor-dir"); + if (rc < 0) { + pr_err("Failed to request dir GPIO %d\n", mctrl->gpio_dir); + goto fail2; + } + gpio_direction_output(mctrl->gpio_dir, 0); + + rc = gpio_request_one(mctrl->gpio_sleep, GPIOF_OUT_INIT_HIGH, + "motor-sleep"); + if (rc < 0) { + pr_err("Failed to request sleep GPIO %d", mctrl->gpio_sleep); + goto fail3; + } + gpio_direction_output(mctrl->gpio_sleep, 0); + + rc = gpio_request_one(mctrl->gpio_pwren, GPIOF_OUT_INIT_HIGH, + "motor-pwr"); + if (rc < 0) { + pr_err("Failed to request power enable GPIO %d", + mctrl->gpio_pwren); + goto fail4; + } + gpio_direction_output(mctrl->gpio_pwren, 1); + + return 0; + +fail4: + if (gpio_is_valid(mctrl->gpio_sleep)) + gpio_free(mctrl->gpio_sleep); +fail3: + if (gpio_is_valid(mctrl->gpio_dir)) + gpio_free(mctrl->gpio_dir); +fail2: + if (gpio_is_valid(mctrl->gpio_mode1)) + gpio_free(mctrl->gpio_mode1); +fail1: + if (gpio_is_valid(mctrl->gpio_mode0)) + gpio_free(mctrl->gpio_mode0); +fail0: + return rc; +} + +int drv8846_parse_dt(struct drv8846_soc_ctrl *mctrl) +{ + int rc = 0; + struct device_node *of_node = NULL; + + of_node = mctrl->pdev->dev.of_node; + + mctrl->pwm_dev = devm_of_pwm_get(&mctrl->pdev->dev, of_node, NULL); + if (IS_ERR(mctrl->pwm_dev)) { + rc = PTR_ERR(mctrl->pwm_dev); + if (rc != -EPROBE_DEFER) + pr_err("Get pwm device for motor failed, rc=%d\n", rc); + return rc; + } + + mctrl->pwm_setting.duty_ns = 0; + mctrl->pwm_setting.period_ns = PWM_PERIOD_DEFAULT_NS; + + mctrl->gpio_mode0 = + of_get_named_gpio_flags(of_node, "motor,gpio-mode0", 0, NULL); + if (!gpio_is_valid(mctrl->gpio_mode0)) { + pr_info("mctrl->motor_data.gpio_mode0 is invalid."); + return -EINVAL; + } + + mctrl->gpio_mode1 = + of_get_named_gpio_flags(of_node, "motor,gpio-mode1", 0, NULL); + if (!gpio_is_valid(mctrl->gpio_mode1)) { + pr_info("motor,mode1-gpio is invalid."); + return -EINVAL; + } + + mctrl->gpio_sleep = + of_get_named_gpio_flags(of_node, "motor,gpio-sleep", 0, NULL); + if (!gpio_is_valid(mctrl->gpio_sleep)) { + pr_info("motor,sleep-gpio is invalid."); + return -EINVAL; + } + + mctrl->gpio_dir = + of_get_named_gpio_flags(of_node, "motor,gpio-dir", 0, NULL); + if (!gpio_is_valid(mctrl->gpio_dir)) { + pr_info("motor,dir-gpio is invalid."); + return -EINVAL; + } + + mctrl->gpio_pwren = + of_get_named_gpio_flags(of_node, "motor,gpio-pwren", 0, NULL); + if (!gpio_is_valid(mctrl->gpio_pwren)) { + pr_info("power,en-gpio is invalid."); + return -EINVAL; + } + + rc = of_property_read_u32(of_node, "motor,rampup-pwm-period-ns", + &mctrl->rampup_period_ns); + if (rc < 0) { + pr_info("motor,rampup-pwm-period-ns not set, use default."); + mctrl->rampup_period_ns = RAMP_PERIOD_DEFAULT_NS; + } + + rc = of_property_read_u32(of_node, "motor,high-pwm-period-ns", + &mctrl->high_period_ns); + if (rc < 0) { + pr_info("motor,high-pwm-period-ns not set, use default."); + mctrl->high_period_ns = HIGH_PERIOD_DEFAULT_NS; + } + + rc = of_property_read_u32(of_node, "motor,rampdown-pwm-period-ns", + &mctrl->rampdown_period_ns); + if (rc < 0) { + pr_info("motor,rampdown-pwm-period-ns not set, use default."); + mctrl->rampdown_period_ns = RAMP_PERIOD_DEFAULT_NS; + } + + rc = of_property_read_u32(of_node, "motor,rampup-duration-ms", + &mctrl->rampup_duration_ms); + if (rc < 0) { + pr_info("motor,rampup-duration-ms not set, use default."); + mctrl->rampup_duration_ms = RAMP_DURATION_DEFAULT_MS; + } + + rc = of_property_read_u32(of_node, "motor,high-duration-ms", + &mctrl->high_duration_ms); + if (rc < 0) { + pr_info("motor,high-duration-ms not set, use default."); + mctrl->high_duration_ms = HIGH_DURATION_DEFAULT_MS; + } + + rc = of_property_read_u32(of_node, "motor,rampdown-duration-ms", + &mctrl->rampdown_duration_ms); + if (rc < 0) { + pr_info("motor,rampdown-duration-ms not set, use default."); + mctrl->rampdown_duration_ms = RAMP_DURATION_DEFAULT_MS; + } + + rc = of_property_read_u32(of_node, "motor,step-mode", + &mctrl->step_mode); + if (rc < 0) { + pr_info("motor,step-mode not set, use default."); + mctrl->step_mode = DEFAULT_STEP_MODE; + } + + return 0; +} + +static int step_mode_dbgfs_read(void *data, u64 *val) +{ + struct drv8846_soc_ctrl *mctrl = (struct drv8846_soc_ctrl *)data; + + *val = mctrl->step_mode; + + return 0; +} + +static int step_mode_dbgfs_write(void *data, u64 val) +{ + struct drv8846_soc_ctrl *mctrl = (struct drv8846_soc_ctrl *)data; + + mctrl->step_mode = val & 0x03; + gpio_direction_output(mctrl->gpio_mode0, (val & 0x01)); + gpio_direction_output(mctrl->gpio_mode1, (val & 0x02)); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(step_mode_debugfs_ops, step_mode_dbgfs_read, + step_mode_dbgfs_write, "%llu\n"); + +static int drv8846_probe(struct platform_device *pdev) +{ + int32_t rc = 0; + struct drv8846_soc_ctrl *mctrl = NULL; + + pr_debug("Enter"); + if (!pdev->dev.of_node) { + pr_err("of_node NULL"); + return -EINVAL; + } + + mctrl = kzalloc(sizeof(struct drv8846_soc_ctrl), GFP_KERNEL); + if (!mctrl) + return -ENOMEM; + + pr_debug("mctrl: %p\n", mctrl); + mctrl->pdev = pdev; + platform_set_drvdata(pdev, mctrl); + + mutex_init(&mctrl->motor_mutex); + + rc = drv8846_parse_dt(mctrl); + if (rc < 0) { + pr_err("parse dt failed"); + goto fail; + } + + rc = drv8846_pinctrl_init(mctrl); + if (!rc && mctrl->pinctrl) { + rc = pinctrl_select_state(mctrl->pinctrl, + mctrl->pinctrl_default); + if (rc < 0) { + pr_err("Failed to select default pinstate %d\n", rc); + } + } else { + pr_err("Failed to init pinctrl\n"); + } + + rc = drv8846_gpio_config(mctrl); + if (rc < 0) { + pr_err("Failed to config gpio\n"); + goto fail; + } + + INIT_WORK(&mctrl->pwm_apply_work, pwm_config_work); + + hrtimer_init(&mctrl->pwm_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + mctrl->pwm_timer.function = pwm_hrtimer_handler; + + mctrl->miscdev.minor = MISC_DYNAMIC_MINOR; + mctrl->miscdev.name = DRV8846_MISC_NAME; + mctrl->miscdev.fops = &drv8846_fops; + mctrl->miscdev.parent = &pdev->dev; + + rc = misc_register(&mctrl->miscdev); + if (rc < 0) { + pr_err("register misc device fail"); + goto register_fail; + } + + mctrl->debugfs = debugfs_create_dir("pwm_motor", NULL); + if (mctrl->debugfs) { + debugfs_create_u32("rampup_period_ns", 0666, mctrl->debugfs, + &mctrl->rampup_period_ns); + debugfs_create_u32("high_period_ns", 0666, mctrl->debugfs, + &mctrl->high_period_ns); + debugfs_create_u32("rampdown_period_ns", 0666, mctrl->debugfs, + &mctrl->rampdown_period_ns); + debugfs_create_u32("rampup_duration_ms", 0666, mctrl->debugfs, + &mctrl->rampup_duration_ms); + debugfs_create_u32("high_duration_ms", 0666, mctrl->debugfs, + &mctrl->high_duration_ms); + debugfs_create_u32("rampdown_duration_ms", 0666, mctrl->debugfs, + &mctrl->rampdown_duration_ms); + debugfs_create_file("step_mode", 0666, mctrl->debugfs, mctrl, + &step_mode_debugfs_ops); + } + + pr_debug("successfully probed."); + return 0; + +register_fail: + cancel_work_sync(&mctrl->pwm_apply_work); + hrtimer_cancel(&mctrl->pwm_timer); +fail: + mutex_destroy(&mctrl->motor_mutex); + kfree(mctrl); + platform_set_drvdata(pdev, NULL); + return rc; +} + +static int drv8846_remove(struct platform_device *pdev) +{ + struct drv8846_soc_ctrl *mctrl = platform_get_drvdata(pdev); + + cancel_work_sync(&mctrl->pwm_apply_work); + hrtimer_cancel(&mctrl->pwm_timer); + mutex_destroy(&mctrl->motor_mutex); + misc_deregister(&mctrl->miscdev); + platform_set_drvdata(pdev, NULL); + kfree(mctrl); + + return 0; +} + +static int drv8846_suspend(struct device *dev) +{ + struct drv8846_soc_ctrl *mctrl = dev_get_drvdata(dev); + + return gpio_direction_output(mctrl->gpio_pwren, 0); +} + +static int drv8846_resume(struct device *dev) +{ + struct drv8846_soc_ctrl *mctrl = dev_get_drvdata(dev); + + return gpio_direction_output(mctrl->gpio_pwren, 1); +} + +static const struct dev_pm_ops drv8846_pm_ops = { + .suspend = drv8846_suspend, + .resume = drv8846_resume, +}; + +static const struct of_device_id drv8846_match_table[] = { + { .compatible = DRV8846_DEV_NAME }, + {} +}; + +static struct platform_driver drv8846_driver = { + .driver = { + .name = DRV8846_DEV_NAME, + .owner = THIS_MODULE, + .of_match_table = drv8846_match_table, + .pm = &drv8846_pm_ops, + }, + .probe = drv8846_probe, + .remove = drv8846_remove, +}; + +static int __init drv8846_init(void) +{ + return platform_driver_register(&drv8846_driver); +} + +static void __exit drv8846_exit(void) +{ + return platform_driver_unregister(&drv8846_driver); +} + +module_init(drv8846_init); +module_exit(drv8846_exit); + +MODULE_AUTHOR("ran fei "); +MODULE_DESCRIPTION("TI Dual H-Bridge Stepper Motor Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/misc/drv8846.h b/include/uapi/misc/drv8846.h new file mode 100644 index 000000000000..ed764dfa8084 --- /dev/null +++ b/include/uapi/misc/drv8846.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* + * Copyright (c) 2014-2015, Linux Foundation. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef _UAPI_MISC_DRV8846_H +#define _UAPI_MISC_DRV8846_H + +#include +#include + +#define DRV8846_MISC_NAME "drv8846_dev" + +#define UP 1 +#define DOWN 0 + +/* Move back add delta ms to guarantee go home success */ +#define DELTAMS 5 + +enum running_state { + STILL = 0, + SPEEDUP, + FULLSTEAM, + SLOWDOWN, + UNIFORMSPEED, +}; + +struct op_parameter { + uint32_t dir; + uint32_t duration_ms; + uint32_t period_ns; +}; + +/* ioctl numbers */ +#define MOTOR_MAGIC 0xD3 +/* AFU devices */ +#define MOTOR_IOC_SET_AUTORUN _IOW(MOTOR_MAGIC, 0x01, uint8_t) +#define MOTOR_IOC_SET_MANUALRUN _IOW(MOTOR_MAGIC, 0x02, struct op_parameter) +#define MOTOR_IOC_GET_REMAIN_TIME _IOR(MOTOR_MAGIC, 0x10, long) +#define MOTOR_IOC_GET_STATE _IOR(MOTOR_MAGIC, 0x11, enum running_state) + +#endif /* _UAPI_MISC_DRV8846_H */ From 80913ec3c4812b401ebe6a13d98865235fe6caa6 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 18:58:49 +0200 Subject: [PATCH 079/226] drivers: misc: Import Xiaomi SIM tray status driver * Run clang-format on source files Change-Id: Ie173550660a4dbaca7700c29d680fc7563fe2877 Signed-off-by: firebird11 --- drivers/misc/Kconfig | 6 +++ drivers/misc/Makefile | 1 + drivers/misc/simtray.c | 87 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100644 drivers/misc/simtray.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f3c1f626d72e..d54829fc5b72 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -613,6 +613,12 @@ config TI_DRV8846 Motor Driver. The MISC peripheral holds the pwm and the driver provides an API to drive stepper motor. +config SIMTRAY_STATUS + tristate "Xiaomi SIM tray status" + default n + help + Say 'y' here to support SIM tray GPIO detection + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index c7d61c0d1ac7..ab94fd1adb17 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_MEMORY_STATE_TIME) += memory_state_time.o obj-$(CONFIG_QPNP_MISC) += qpnp-misc.o obj-$(CONFIG_AKM09970) += akm09970.o obj-$(CONFIG_TI_DRV8846) += drv8846.o +obj-$(CONFIG_SIMTRAY_STATUS) += simtray.o obj-$(CONFIG_OKL4_USER_VIRQ) += okl4-virq.o obj-$(CONFIG_OKL4_RINGBUF) += okl4-ringbuf.o diff --git a/drivers/misc/simtray.c b/drivers/misc/simtray.c new file mode 100644 index 000000000000..dc941ab6921d --- /dev/null +++ b/drivers/misc/simtray.c @@ -0,0 +1,87 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct simtray_data { + struct device *dev; + int status_gpio; +}; + +static ssize_t simtray_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct simtray_data *data = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, "%d\n", + gpio_get_value(data->status_gpio)); +} +static DEVICE_ATTR(status, 0444, simtray_status_show, NULL); + +static int simtray_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct simtray_data *data; + + pr_info("%s enter\n", __func__); + + data = devm_kzalloc(dev, sizeof(struct simtray_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->status_gpio = of_get_named_gpio(np, "status-gpio", 0); + if (data->status_gpio < 0) + return -EINVAL; + + ret = sysfs_create_file(&dev->kobj, &dev_attr_status.attr); + if (ret < 0) { + dev_err(dev, "Failed to create sysfs node.\n"); + return -EINVAL; + } + + data->dev = dev; + platform_set_drvdata(pdev, data); + + return ret; +} + +static int simtray_remove(struct platform_device *pdev) +{ + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_status.attr); + return 0; +} + +static const struct of_device_id simtray_of_match[] = { + { + .compatible = "xiaomi,simtray-status", + }, + {}, +}; + +static struct platform_driver simtray_status_driver = { + .driver = { + .name = "simtray-status", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(simtray_of_match), + }, + .probe = simtray_probe, + .remove = simtray_remove, +}; + +module_platform_driver(simtray_status_driver); +MODULE_AUTHOR("Tao Jun"); +MODULE_DESCRIPTION("Xiaomi SIM tray status"); +MODULE_LICENSE("GPL"); From 494fbada3d079015821fa8cd91cc1f327ad305bf Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:00:39 +0200 Subject: [PATCH 080/226] drivers: nfc: Import Xiaomi changes Change-Id: I09de882a627ebec1821f4cfc21312f956a8da653 Signed-off-by: firebird11 --- drivers/nfc/nq-nci.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/nfc/nq-nci.c b/drivers/nfc/nq-nci.c index 5f8cc5f061aa..c6c8b7c0adaf 100644 --- a/drivers/nfc/nq-nci.c +++ b/drivers/nfc/nq-nci.c @@ -153,6 +153,7 @@ static irqreturn_t nqx_dev_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } +#ifndef CONFIG_MACH_XIAOMI_SM8150 static int is_data_available_for_read(struct nqx_dev *nqx_dev) { int ret; @@ -162,6 +163,7 @@ static int is_data_available_for_read(struct nqx_dev *nqx_dev) !nqx_dev->irq_enabled, msecs_to_jiffies(MAX_IRQ_WAIT_TIME)); return ret; } +#endif static ssize_t nfc_read(struct file *filp, char __user *buf, size_t count, loff_t *offset) @@ -348,9 +350,13 @@ static int sn100_ese_pwr(struct nqx_dev *nqx_dev, unsigned long int arg) * VEN state will remain HIGH if NFC is enabled otherwise * it will be set as LOW */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!gpio_get_value(nqx_dev->en_gpio)) { +#else nqx_dev->nfc_ven_enabled = gpio_get_value(nqx_dev->en_gpio); if (!nqx_dev->nfc_ven_enabled) { +#endif dev_dbg(&nqx_dev->client->dev, "eSE HAL service setting en_gpio HIGH\n"); gpio_set_value(nqx_dev->en_gpio, 1); /* hardware dependent delay */ @@ -792,6 +798,7 @@ static const struct file_operations nfc_dev_fops = { #endif }; +#ifndef CONFIG_MACH_XIAOMI_SM8150 /* * function: get_nfcc_hw_info() * @@ -1112,6 +1119,7 @@ static int nfcc_hw_check(struct i2c_client *client, struct nqx_dev *nqx_dev) return ret; } +#endif /* * Routine to enable clock. @@ -1430,8 +1438,13 @@ static int nqx_probe(struct i2c_client *client, /* NFC_INT IRQ */ nqx_dev->irq_enabled = true; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + r = request_irq(client->irq, nqx_dev_irq_handler, + IRQF_TRIGGER_RISING, client->name, nqx_dev); +#else r = request_irq(client->irq, nqx_dev_irq_handler, IRQF_TRIGGER_HIGH, client->name, nqx_dev); +#endif if (r) { dev_err(&client->dev, "%s: request_irq failed\n", __func__); goto err_request_irq_failed; @@ -1443,6 +1456,7 @@ static int nqx_probe(struct i2c_client *client, * present before attempting further hardware initialisation. * */ +#ifndef CONFIG_MACH_XIAOMI_SM8150 r = nfcc_hw_check(client, nqx_dev); if (r) { /* make sure NFCC is not enabled */ @@ -1450,6 +1464,7 @@ static int nqx_probe(struct i2c_client *client, /* We don't think there is hardware switch NFC OFF */ goto err_request_hw_check_failed; } +#endif /* Register reboot notifier here */ r = register_reboot_notifier(&nfcc_notifier); @@ -1465,12 +1480,23 @@ static int nqx_probe(struct i2c_client *client, } #ifdef NFC_KERNEL_BU +#ifndef CONFIG_MACH_XIAOMI_SM8150 r = nqx_clock_select(nqx_dev); if (r < 0) { dev_err(&client->dev, "%s: nqx_clock_select failed\n", __func__); goto err_clock_en_failed; } +#else + if (nqx_dev->pdata->clk_pin_voting) { + r = nqx_clock_select(nqx_dev); + if (r < 0) { + dev_err(&client->dev, + "%s: nqx_clock_select failed\n", __func__); + goto err_clock_en_failed; + } + } +#endif gpio_set_value(platform_data->en_gpio, 1); #endif device_init_wakeup(&client->dev, true); From 5a6c2852f2990ca9babd6bca275a5b798db07539 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:01:55 +0200 Subject: [PATCH 081/226] drivers: of: Import Xiaomi changes Change-Id: I816c5168b4e419ca32a0b8a0d22f6738676eb86f Signed-off-by: firebird11 --- drivers/of/of_batterydata.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/of/of_batterydata.c b/drivers/of/of_batterydata.c index b275a8c0aad0..0aff4632beb9 100644 --- a/drivers/of/of_batterydata.c +++ b/drivers/of/of_batterydata.c @@ -321,6 +321,9 @@ struct device_node *of_batterydata_get_best_profile( { struct batt_ids batt_ids; struct device_node *node, *best_node = NULL; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct device_node *generic_node = NULL; +#endif const char *battery_type = NULL; int delta = 0, best_delta = 0, best_id_kohm = 0, id_range_pct, i = 0, rc = 0, limit = 0; @@ -374,9 +377,19 @@ struct device_node *of_batterydata_get_best_profile( } } } + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = of_property_read_string(node, "qcom,battery-type", + &battery_type); + if (!rc && strcmp(battery_type, "itech_3000mah") == 0) + generic_node = node; +#endif } if (best_node == NULL) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + best_node = generic_node; +#endif pr_err("No battery data found\n"); return best_node; } From 46028cccd72f45683659cb77273e4a3d9fc6fee3 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:06:57 +0200 Subject: [PATCH 082/226] drivers: pinctrl: qcom: Import Xiaomi changes Change-Id: I8dbbab6cf0a7c55e7fc4d26a51e2a64c3ddcee81 Signed-off-by: firebird11 --- drivers/pinctrl/qcom/pinctrl-msm.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 6c63b2ff3fae..9f90b60e5877 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -40,6 +40,9 @@ #include "../pinconf.h" #include "pinctrl-msm.h" #include "../pinctrl-utils.h" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include +#endif #include #ifdef CONFIG_HIBERNATION #include @@ -382,6 +385,12 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, u32 val; int i; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* gpio 0~3 is NFC spi, gpio 126~129 is FP spi */ + if (group < 4 || (group > 125 && group < 130)) + return 0; +#endif + g = &pctrl->soc->groups[group]; base = reassign_pctrl_reg(pctrl->soc, group); @@ -623,6 +632,19 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned i; for (i = 0; i < chip->ngpio; i++, gpio++) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* gpio 0~3 is NFC spi, gpio 126~129 is FP spi */ + if (i < 4 || (i > 125 && i < 130)) + continue; + + /*only for E5G*/ + if (HARDWARE_PLATFORM_ANDROMEDA == get_hw_version_platform()){ + /*skip 5G related gpio: 5G IPC HS-UART, 5G RF HS-UART*/ + if ((i >= 4 && i <= 7) || (i >= 83 && i <= 86)) + continue; + } +#endif + msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); seq_puts(s, "\n"); } From eed2c3c6cea72e5731bc86bf6fc18827fda9f6b5 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 5 Jul 2021 22:47:50 +0200 Subject: [PATCH 083/226] drivers: power: supply: Import Xiaomi drivers * From nabu-r-oss * idtp9220 driver from cepheus-q-oss * rx1619 driver from cmi-r-oss * Run clang-format on source files Change-Id: I615c5b86bb9a4143304a436667a6e0d523c60494 Signed-off-by: firebird11 --- drivers/power/supply/Kconfig | 8 + drivers/power/supply/Makefile | 8 + drivers/power/supply/halo/Kconfig | 14 + drivers/power/supply/halo/Makefile | 1 + drivers/power/supply/halo/halo_7221_cp.c | 737 ++ drivers/power/supply/lionsemi/Kconfig | 14 + drivers/power/supply/lionsemi/Makefile | 1 + drivers/power/supply/lionsemi/ln8282.c | 1088 +++ drivers/power/supply/maxim/Kconfig | 27 + drivers/power/supply/maxim/Makefile | 4 + drivers/power/supply/maxim/ds28e16.c | 1904 ++++++ drivers/power/supply/maxim/ds28e16.h | 133 + drivers/power/supply/maxim/ds28e16_common.h | 84 + drivers/power/supply/maxim/ds28e16_master.c | 1915 ++++++ drivers/power/supply/maxim/ds28e16_master.h | 55 + drivers/power/supply/maxim/ds28e16_slave.c | 1959 ++++++ drivers/power/supply/maxim/ds28e16_slave.h | 58 + drivers/power/supply/maxim/onewire_gpio.c | 613 ++ drivers/power/supply/maxim/onewire_gpio.h | 10 + .../power/supply/maxim/onewire_gpio_master.c | 604 ++ .../power/supply/maxim/onewire_gpio_master.h | 10 + .../power/supply/maxim/onewire_gpio_slave.c | 611 ++ .../power/supply/maxim/onewire_gpio_slave.h | 10 + drivers/power/supply/maxim/sha384_software.c | 109 + drivers/power/supply/maxim/sha384_software.h | 30 + drivers/power/supply/maxim/ucl_hash.h | 53 + drivers/power/supply/maxim/ucl_retdefs.h | 237 + drivers/power/supply/maxim/ucl_sha3.c | 429 ++ drivers/power/supply/maxim/ucl_sha3.h | 269 + drivers/power/supply/nuvolta/Kconfig | 30 + drivers/power/supply/nuvolta/Makefile | 3 + drivers/power/supply/nuvolta/rx1618.c | 1635 +++++ drivers/power/supply/nuvolta/rx1618.h | 1263 ++++ drivers/power/supply/nuvolta/rx1619.c | 4695 +++++++++++++ drivers/power/supply/nuvolta/rx1619.h | 2741 ++++++++ drivers/power/supply/nuvolta/rx1619_trim.c | 170 + drivers/power/supply/renesas/Kconfig | 25 + drivers/power/supply/renesas/Makefile | 2 + drivers/power/supply/renesas/idtp9220.c | 2223 ++++++ drivers/power/supply/renesas/idtp9220.h | 2263 +++++++ drivers/power/supply/renesas/idtp9418.c | 5971 +++++++++++++++++ drivers/power/supply/renesas/idtp9418.h | 507 ++ drivers/power/supply/renesas/idtp9418_fw.h | 3083 +++++++++ drivers/power/supply/ti/Kconfig | 24 + drivers/power/supply/ti/Makefile | 3 + drivers/power/supply/ti/bq25970_reg.h | 791 +++ drivers/power/supply/ti/bq2597x_charger.c | 2462 +++++++ drivers/power/supply/ti/bq27z561_fg.c | 2134 ++++++ drivers/power/supply/ti/cp_qc30.c | 1527 +++++ drivers/power/supply/ti/cp_qc30.h | 251 + drivers/power/supply/ti/ln8000_charger.c | 1826 +++++ drivers/power/supply/ti/ln8000_charger.h | 344 + drivers/power/supply/ti/pd_policy_manager.c | 1589 +++++ drivers/power/supply/ti/pd_policy_manager.h | 237 + include/linux/power/ln8282.h | 40 + 55 files changed, 46834 insertions(+) create mode 100644 drivers/power/supply/halo/Kconfig create mode 100644 drivers/power/supply/halo/Makefile create mode 100644 drivers/power/supply/halo/halo_7221_cp.c create mode 100644 drivers/power/supply/lionsemi/Kconfig create mode 100644 drivers/power/supply/lionsemi/Makefile create mode 100644 drivers/power/supply/lionsemi/ln8282.c create mode 100644 drivers/power/supply/maxim/Kconfig create mode 100644 drivers/power/supply/maxim/Makefile create mode 100644 drivers/power/supply/maxim/ds28e16.c create mode 100644 drivers/power/supply/maxim/ds28e16.h create mode 100644 drivers/power/supply/maxim/ds28e16_common.h create mode 100644 drivers/power/supply/maxim/ds28e16_master.c create mode 100644 drivers/power/supply/maxim/ds28e16_master.h create mode 100644 drivers/power/supply/maxim/ds28e16_slave.c create mode 100644 drivers/power/supply/maxim/ds28e16_slave.h create mode 100644 drivers/power/supply/maxim/onewire_gpio.c create mode 100644 drivers/power/supply/maxim/onewire_gpio.h create mode 100644 drivers/power/supply/maxim/onewire_gpio_master.c create mode 100644 drivers/power/supply/maxim/onewire_gpio_master.h create mode 100644 drivers/power/supply/maxim/onewire_gpio_slave.c create mode 100644 drivers/power/supply/maxim/onewire_gpio_slave.h create mode 100644 drivers/power/supply/maxim/sha384_software.c create mode 100644 drivers/power/supply/maxim/sha384_software.h create mode 100644 drivers/power/supply/maxim/ucl_hash.h create mode 100644 drivers/power/supply/maxim/ucl_retdefs.h create mode 100644 drivers/power/supply/maxim/ucl_sha3.c create mode 100644 drivers/power/supply/maxim/ucl_sha3.h create mode 100644 drivers/power/supply/nuvolta/Kconfig create mode 100644 drivers/power/supply/nuvolta/Makefile create mode 100644 drivers/power/supply/nuvolta/rx1618.c create mode 100644 drivers/power/supply/nuvolta/rx1618.h create mode 100644 drivers/power/supply/nuvolta/rx1619.c create mode 100644 drivers/power/supply/nuvolta/rx1619.h create mode 100644 drivers/power/supply/nuvolta/rx1619_trim.c create mode 100644 drivers/power/supply/renesas/Kconfig create mode 100644 drivers/power/supply/renesas/Makefile create mode 100644 drivers/power/supply/renesas/idtp9220.c create mode 100644 drivers/power/supply/renesas/idtp9220.h create mode 100644 drivers/power/supply/renesas/idtp9418.c create mode 100644 drivers/power/supply/renesas/idtp9418.h create mode 100644 drivers/power/supply/renesas/idtp9418_fw.h create mode 100644 drivers/power/supply/ti/Kconfig create mode 100644 drivers/power/supply/ti/Makefile create mode 100644 drivers/power/supply/ti/bq25970_reg.h create mode 100644 drivers/power/supply/ti/bq2597x_charger.c create mode 100644 drivers/power/supply/ti/bq27z561_fg.c create mode 100644 drivers/power/supply/ti/cp_qc30.c create mode 100644 drivers/power/supply/ti/cp_qc30.h create mode 100644 drivers/power/supply/ti/ln8000_charger.c create mode 100644 drivers/power/supply/ti/ln8000_charger.h create mode 100644 drivers/power/supply/ti/pd_policy_manager.c create mode 100644 drivers/power/supply/ti/pd_policy_manager.h create mode 100644 include/linux/power/ln8282.h diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 7c217d5a673a..75105e6769c3 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -613,4 +613,12 @@ config CHARGER_RT9455 source "drivers/power/supply/qcom/Kconfig" +# Xiaomi +source "drivers/power/supply/halo/Kconfig" +source "drivers/power/supply/lionsemi/Kconfig" +source "drivers/power/supply/maxim/Kconfig" +source "drivers/power/supply/nuvolta/Kconfig" +source "drivers/power/supply/renesas/Kconfig" +source "drivers/power/supply/ti/Kconfig" + endif # POWER_SUPPLY diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile index 4187af3ff90f..403137176c47 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -83,3 +83,11 @@ obj-$(CONFIG_CHARGER_TPS65217) += tps65217_charger.o obj-$(CONFIG_AXP288_FUEL_GAUGE) += axp288_fuel_gauge.o obj-$(CONFIG_AXP288_CHARGER) += axp288_charger.o obj-$(CONFIG_ARCH_QCOM) += qcom/ + +# xiaomi +obj-y += halo/ +obj-y += lionsemi/ +obj-y += maxim/ +obj-y += nuvolta/ +obj-y += renesas/ +obj-y += ti/ diff --git a/drivers/power/supply/halo/Kconfig b/drivers/power/supply/halo/Kconfig new file mode 100644 index 000000000000..d9bb3583a802 --- /dev/null +++ b/drivers/power/supply/halo/Kconfig @@ -0,0 +1,14 @@ +menu "HALO Electronics, Inc. Charger support" + +config HALO_7221 + tristate "HALO7221 Charge Pump" + depends on I2C + help + Say Y to include support for HALO 7221 charger pump. + HALO 7221 is a charger pump chip. + The driver supports charger enable/disable. + The driver reports the charger status via the power supply framework. + The driver controls 7221 via I2C and + supports device-tree interface. + +endmenu diff --git a/drivers/power/supply/halo/Makefile b/drivers/power/supply/halo/Makefile new file mode 100644 index 000000000000..11b23af0a422 --- /dev/null +++ b/drivers/power/supply/halo/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_HALO_7221) += halo_7221_cp.o diff --git a/drivers/power/supply/halo/halo_7221_cp.c b/drivers/power/supply/halo/halo_7221_cp.c new file mode 100644 index 000000000000..be7df83a213d --- /dev/null +++ b/drivers/power/supply/halo/halo_7221_cp.c @@ -0,0 +1,737 @@ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEVICE_NAME "HALO7221_cp" + +struct halo7221_dev; + +struct halo7221_dt_props { + unsigned int enable_gpio; +}; + +struct halo7221_func { + int (*read)(struct halo7221_dev *di, u16 reg, u8 *val); + int (*write)(struct halo7221_dev *di, u16 reg, u8 val); + int (*read_buf)(struct halo7221_dev *di, u16 reg, u8 *buf, u32 size); + int (*write_buf)(struct halo7221_dev *di, u16 reg, u8 *buf, u32 size); + int (*write_masked)(struct halo7221_dev *di, u16 reg, u8 mask, u8 val); +}; + +struct halo7221_dev { + char *name; + struct i2c_client *client; + struct device *dev; + struct regmap *regmap; + struct halo7221_func bus; + struct halo7221_dt_props dt_props; + + struct pinctrl *halo_pinctrl; + struct pinctrl_state *halo_gpio_active; + struct pinctrl_state *halo_gpio_suspend; + struct power_supply *halo_psy; +}; + +/* +typedef union{ + u16 value; + u8 ptr[2]; +}vuc; +*/ + +extern char *saved_command_line; +static int get_board_version(void) +{ + char boot[5] = { '\0' }; + char *match = (char *)strnstr( + saved_command_line, + "androidboot.hwlevel=", strlen(saved_command_line)); + if (match) { + memcpy(boot, (match + strlen("androidboot.hwlevel=")), + sizeof(boot) - 1); + printk("%s: hwlevel is %s\n", __func__, boot); + if (!strncmp(boot, "P1.3", strlen("P1.3"))) + return 1; + } + return 0; +} + +int halo7221_read(struct halo7221_dev *chip, u16 reg, u8 *val) +{ + unsigned int temp; + int rc; + + rc = regmap_read(chip->regmap, reg, &temp); + if (rc >= 0) + *val = (u8)temp; + + return rc; +} + +int halo7221_write(struct halo7221_dev *chip, u16 reg, u8 val) +{ + int rc = 0; + + rc = regmap_write(chip->regmap, reg, val); + if (rc < 0) + dev_err(chip->dev, "%s: write error: %d\n", __func__, rc); + + return rc; +} + +int halo7221_read_buffer(struct halo7221_dev *chip, u16 reg, u8 *buf, u32 size) +{ + return regmap_bulk_read(chip->regmap, reg, buf, size); +} + +int halo7221_write_buffer(struct halo7221_dev *chip, u16 reg, u8 *buf, u32 size) +{ + int rc = 0; + + while (size--) { + rc = chip->bus.write(chip, reg++, *buf++); + if (rc < 0) { + dev_err(chip->dev, "write error: %d\n", rc); + return rc; + } + } + + return rc; +} + +int halo7221_write_masked(struct halo7221_dev *chip, u16 reg, u8 mask, u8 val) +{ + return regmap_update_bits(chip->regmap, reg, mask, val); +} +#define REG_NONE_ACCESS 0 +#define REG_RD_ACCESS (1 << 0) +#define REG_WR_ACCESS (1 << 1) +#define REG_BIT_ACCESS (1 << 2) + +#define REG_MAX 0x0F + +static int halo7221_set_enable(struct halo7221_dev *chip, int enable) +{ + int ret = 0; + + if (gpio_is_valid(chip->dt_props.enable_gpio)) { + ret = gpio_request(chip->dt_props.enable_gpio, + "halo-enable-gpio"); + if (ret) { + dev_err(chip->dev, + "%s: unable to request halo enable gpio [%d]\n", + __func__, chip->dt_props.enable_gpio); + } + ret = gpio_direction_output(chip->dt_props.enable_gpio, enable); + if (ret) { + dev_err(chip->dev, + "%s: cannot set direction for halo enable gpio [%d]\n", + __func__, chip->dt_props.enable_gpio); + } + gpio_free(chip->dt_props.enable_gpio); + } + return ret; +} + +static int halo7221_hw_init(struct halo7221_dev *chip) +{ + int rc = 0; + + rc = chip->bus.write(chip, 0x61, 0x80); + msleep(200); + rc = chip->bus.write(chip, 0x61, 0x00); + msleep(200); + rc = chip->bus.write_masked(chip, 0x03, GENMASK(1, 0), + 0x01); // set 11v to enable cp mode + msleep(50); + rc = chip->bus.write_masked(chip, 0x01, GENMASK(7, 3), + 0x1A); // Iin_Limit 1500mA + + return rc; +} + +/* chip enable attrs */ +static ssize_t chip_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct halo7221_dev *chip = i2c_get_clientdata(client); + + if (gpio_is_valid(chip->dt_props.enable_gpio)) + ret = gpio_get_value(chip->dt_props.enable_gpio); + else { + dev_err(chip->dev, "%s: enable gpio not provided\n", __func__); + ret = -1; + } + + dev_info(chip->dev, "chip enable gpio: %d\n", ret); + + return snprintf(buf, sizeof(buf), "Chip enable: %d\n", ret); +} + +static ssize_t chip_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int ret, enable; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct halo7221_dev *chip = i2c_get_clientdata(client); + + ret = (int)simple_strtoul(buf, NULL, 10); + enable = !!ret; + + halo7221_set_enable(chip, enable); + + return count; +} + +static ssize_t chip_init_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int ret = 0; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct halo7221_dev *chip = i2c_get_clientdata(client); + + ret = halo7221_hw_init(chip); + if (ret < 0) { + dev_err(chip->dev, "%s: chip hw init error [%d]\n", __func__, + ret); + } + return snprintf(buf, sizeof(buf), "Chip init: %d\n", ret); +} + +/* +enum REG_INDEX +{ + CHIPID = 0, + VOUT, + INT_FLAG, + INTCTLR, + VOUTSET, + VFC, + CMD, + INDEX_MAX, +}; + +const u16 reg_access[INDEX_MAX][2] = { + [CHIPID] = {REG_CHIPID, REG_RD_ACCESS}, + [VOUT] = {REG_VOUT, REG_RD_ACCESS}, + [INT_FLAG] = {REG_INTFLAG,REG_RD_ACCESS}, + [INTCTLR] = {REG_INTCLR,REG_WR_ACCESS}, + [VOUTSET] = {REG_VOUTSET, REG_RD_ACCESS|REG_WR_ACCESS}, + [VFC] = {REG_VFC, REG_RD_ACCESS|REG_WR_ACCESS}, + [CMD] = {REG_CMD, REG_RD_ACCESS|REG_WR_ACCESS|REG_BIT_ACCESS}, +}; + + +static ssize_t get_reg(struct device* cd,struct device_attribute *attr, char* buf) +{ + u8 val[2]; + ssize_t len = 0; + int i = 0; + + for(i = 0; i< INDEX_MAX ;i++) { + if(reg_access[i][1] & REG_RD_ACCESS) { + halo7221_read_buffer(mte,reg_access[i][0],val,2); + len += snprintf(buf+len, PAGE_SIZE-len, "reg:0x%02x=0x%02x%02x\n", reg_access[i][0],val[0],val[1]); + } + } + + return len; +} + +static ssize_t set_reg(struct device* cd, struct device_attribute *attr, const char* buf, size_t len) +{ + unsigned int databuf[2]; + vuc val; + u8 tmp[2]; + u16 regdata; + int i = 0; + int ret = 0; + + ret = sscanf(buf,"%x %x",&databuf[0], &databuf[1]); + printk("%s : %d 0x%x 0x%x\n", __func__, ret, databuf[0],databuf[1]); + if(2 == ret) { + for(i = 0; i< INDEX_MAX ;i++) { + if(databuf[0] == reg_access[i][0]) { + if (reg_access[i][1] & REG_WR_ACCESS) { + val.ptr[1] = databuf[1]& 0x00ff; //big endian + val.ptr[0] = (databuf[1]& 0xff00) >> 8; + if (reg_access[i][1] & REG_BIT_ACCESS) { + halo7221_read_buffer(mte,databuf[0],tmp,2); + regdata = tmp[0]<<8|tmp[1]; + val.value |= regdata; + printk("get reg: 0x%04x set reg: 0x%04x \n", regdata,val.value); + halo7221_write_buffer(mte,databuf[0],val.ptr,2); + } + else { + printk("Set reg : [0x%04x] 0x%x 0x%x \n",databuf[1], val.ptr[0], val.ptr[1]); + halo7221_write_buffer(mte,databuf[0],val.ptr,2); + } + } + break; + } + } + } + return len; +} + +static ssize_t chip_version_show(struct device* dev, struct device_attribute* attr, char* buf) +{ + u8 fwver[2]; + ssize_t len = 0; // must to set 0 + pr_debug("chip_version_show\n"); + halo7221_read_buffer(mte,REG_FW_VER,fwver,2); + pr_debug("chip_version : 0x%02x,0x%02x\n",fwver[0],fwver[1]); + len += snprintf(buf+len, PAGE_SIZE-len, "chip_version : %02x,%02x\n", fwver[0],fwver[1]); + return len; +} +*/ + +/* voltage limit attrs */ +/* +static ssize_t chip_vout_show(struct device* dev, struct device_attribute* attr, char* buf) +{ + unsigned char fwver[2]; + unsigned short vout_value; + ssize_t len = 0; + pr_debug("chip_vout_show\n"); + // data_list = self.read(REG_VOUT, 2) + // val = data_list[1]|(data_list[0]<<8) + // self.insertPlainText('Vout: %0.3fV\n'%(val/1000.0)) + halo7221_read_buffer(mte,REG_VOUT,fwver,2); + vout_value = fwver[0] << 8 | fwver[1]; + pr_debug("chip Vout : %d\n",vout_value); + len += snprintf(buf+len, PAGE_SIZE-len, "chip Vout : %d mV\n",vout_value); + return len; +} + +static ssize_t chip_vout_store(struct device* dev, struct device_attribute* attr, const char* buf, size_t count) +{ + vuc val; + int error; + unsigned int temp; + u8 vptemp; + error = kstrtouint(buf, 10, &temp); + if (error) + return error; + if( (temp < 0) ||( temp > 20000)){ + pr_debug(" Parameter error\n"); + return count; + } + val.value = temp; + vptemp = val.ptr[0]; + val.ptr[0] = val.ptr[1]; + val.ptr[1] = vptemp; + halo7221_write_buffer(mte,REG_VOUTSET,val.ptr,2); + pr_debug("Set Vout : %d \n", val.value); + // mv=int(self.dsbVout.value()*1000) + // self.write(REG_VOUTSET, [(mv>>8)&0xff, mv&0xff]) + // self.insertPlainText('Set Vout: %0.3fV\n'%(mv/1000.0)) + + return count; +} + +static ssize_t fast_charging_store(struct device* dev, struct device_attribute* attr, const char* buf, size_t count) +{ + vuc val; + int error; + unsigned int temp; + u8 fcflag; + error = kstrtouint(buf, 10, &temp); + if (error) + return error; + if( (temp < 0) ||( temp > 20000)){ + pr_debug(" Parameter error\n"); + return count; + } + val.value = temp; + fcflag = val.ptr[0]; + val.ptr[0] = val.ptr[1]; + val.ptr[1] = fcflag; + halo7221_write_buffer(mte,REG_VFC,val.ptr,2); + pr_debug("FC send data : 0x%02x,0x%02x \n", val.ptr[0],val.ptr[1]); + val.value = FASTCHARGE; + halo7221_write_buffer(mte,REG_CMD,val.ptr,2); + return count; +} +static ssize_t fast_charging_show(struct device* dev, struct device_attribute* attr, char* buf) +{ + unsigned char fwver[2]; + unsigned short fc_value; + ssize_t len = 0; + pr_debug("fast_charging_show\n"); + // data_list = self.read(REG_VOUT, 2) + // val = data_list[1]|(data_list[0]<<8) + // self.insertPlainText('Vout: %0.3fV\n'%(val/1000.0)) + halo7221_read_buffer(mte,REG_VFC,fwver,2); + fc_value = fwver[0] << 8 | fwver[1]; + pr_debug("FC read data : %d\n",fc_value); + len += snprintf(buf+len, PAGE_SIZE-len, "FC read data : %d mV\n",fc_value); + return len; +} +*/ + +/* +static DEVICE_ATTR(chip_version, S_IRUGO | S_IWUSR, chip_version_show, NULL); +static DEVICE_ATTR(chip_vout, S_IRUGO | S_IWUSR, chip_vout_show, chip_vout_store); +static DEVICE_ATTR(fast_charging,S_IRUGO | S_IWUSR, fast_charging_show, fast_charging_store); +static DEVICE_ATTR(reg,S_IRUGO | S_IWUSR, get_reg, set_reg); +*/ +static DEVICE_ATTR(chip_enable, S_IWUSR | S_IRUGO, chip_enable_show, + chip_enable_store); +static DEVICE_ATTR(chip_init, S_IWUSR | S_IRUGO, chip_init_show, NULL); + +static struct attribute *halo7221_sysfs_attrs[] = { + /* + &dev_attr_chip_version.attr, + &dev_attr_chip_vout.attr, + &dev_attr_fast_charging.attr, + &dev_attr_reg.attr, +*/ + &dev_attr_chip_enable.attr, + &dev_attr_chip_init.attr, + NULL, +}; + +static const struct attribute_group halo7221_sysfs_group = { + .name = "halo7221group", + .attrs = halo7221_sysfs_attrs, +}; + +static const struct of_device_id match_table[] = { + { + .compatible = "halo7221,halo7221_cp", + }, + {}, +}; + +static const struct regmap_config halo7221_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xFFFF, +}; + +static int halo7221_parse_dt(struct halo7221_dev *chip) +{ + struct device_node *node = chip->dev->of_node; + if (!node) { + dev_err(chip->dev, "device tree node missing\n"); + return -EINVAL; + } + + chip->dt_props.enable_gpio = of_get_named_gpio(node, "halo,enable", 0); + if ((!gpio_is_valid(chip->dt_props.enable_gpio))) + return -EINVAL; + + return 0; +} + +static int halo7221_gpio_init(struct halo7221_dev *chip) +{ + int ret = 0; + + chip->halo_pinctrl = devm_pinctrl_get(chip->dev); + if (IS_ERR_OR_NULL(chip->halo_pinctrl)) { + dev_err(chip->dev, "No pinctrl config specified\n"); + ret = PTR_ERR(chip->dev); + return ret; + } + chip->halo_gpio_active = + pinctrl_lookup_state(chip->halo_pinctrl, "halo7221_active"); + if (IS_ERR_OR_NULL(chip->halo_gpio_active)) { + dev_err(chip->dev, "No active config specified\n"); + ret = PTR_ERR(chip->halo_gpio_active); + return ret; + } + chip->halo_gpio_suspend = + pinctrl_lookup_state(chip->halo_pinctrl, "halo7221_suspend"); + if (IS_ERR_OR_NULL(chip->halo_gpio_suspend)) { + dev_err(chip->dev, "No suspend config specified\n"); + ret = PTR_ERR(chip->halo_gpio_suspend); + return ret; + } + + ret = pinctrl_select_state(chip->halo_pinctrl, chip->halo_gpio_active); + if (ret < 0) { + dev_err(chip->dev, "fail to select pinctrl active rc=%d\n", + ret); + return ret; + } + + return ret; +} + +static int halo_get_mode(struct halo7221_dev *chip) +{ + int rc, ret; + u8 val; + + rc = chip->bus.read(chip, 0x08, &val); + dev_info(chip->dev, "get status is: 0x%x\n", val); + if (rc < 0) + ret = -1; + else { + ret = val & BIT(5); + } + if (ret == 0) + ret = 2; // return switching mode + + dev_info(chip->dev, "get opmode is: %d\n", ret); + + return ret; +} + +#define FORWARD_BYPASS 1 +#define FORWARD_SWITCH 2 +#define REVERSE_SWITCH 3 +static int halo_set_mode(struct halo7221_dev *chip, int mode) +{ + int rc = 0; + switch (mode) { + case FORWARD_BYPASS: + rc = chip->bus.write(chip, 0x00, 0xff); + rc = chip->bus.write(chip, 0x07, 0x78); + rc = chip->bus.write(chip, 0xA7, 0xf9); + rc = chip->bus.write(chip, 0x0A, 0x10); + rc = chip->bus.write(chip, 0x02, 0xa8); //set ilim to 1500mA + rc = chip->bus.write(chip, 0x05, 0x61); + rc = chip->bus.write(chip, 0x03, 0x53); + break; + case FORWARD_SWITCH: + rc = chip->bus.write(chip, 0x00, 0xff); + rc = chip->bus.write(chip, 0x07, 0x78); + rc = chip->bus.write(chip, 0xA7, 0xf9); + rc = chip->bus.write(chip, 0x0A, 0x10); + rc = chip->bus.write(chip, 0x02, 0xa9); //set ilim to 1500mA + rc = chip->bus.write(chip, 0x05, 0x61); + rc = chip->bus.write(chip, 0x03, 0x53); + break; + case REVERSE_SWITCH: + rc = chip->bus.write(chip, 0x00, 0xff); + rc = chip->bus.write(chip, 0x07, 0x78); + rc = chip->bus.write(chip, 0xA7, 0xf9); + rc = chip->bus.write(chip, 0x0A, 0x10); + rc = chip->bus.write(chip, 0x0B, 0x01); + break; + default: + dev_err(chip->dev, "%s: invalid settings\n", __func__); + } + + return rc; +} + +static enum power_supply_property halo_props[] = { + POWER_SUPPLY_PROP_DIV_2_MODE, +}; + +static int halo_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct halo7221_dev *chip = power_supply_get_drvdata(psy); + + switch (psp) { + case POWER_SUPPLY_PROP_DIV_2_MODE: + val->intval = halo_get_mode(chip); + break; + default: + return -EINVAL; + } + return 0; +} + +static int halo_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct halo7221_dev *chip = power_supply_get_drvdata(psy); + int rc = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_DIV_2_MODE: + rc = halo_set_mode(chip, val->intval); + break; + default: + return -EINVAL; + } + + return rc; +} + +static int halo_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + int rc; + + switch (psp) { + case POWER_SUPPLY_PROP_DIV_2_MODE: + return 1; + default: + rc = 0; + break; + } + + return rc; +} + +static const struct power_supply_desc halo_psy_desc = { + .name = "halo", + .type = POWER_SUPPLY_TYPE_WIRELESS, + .properties = halo_props, + .num_properties = ARRAY_SIZE(halo_props), + .get_property = halo_get_prop, + .set_property = halo_set_prop, + .property_is_writeable = halo_prop_is_writeable, +}; + +static int halo7221_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct halo7221_dev *chip; + int rc = 0, ret = 0; + struct power_supply_config halo_cfg = {}; + //vuc chipid; + + dev_info(&client->dev, "halo7221 probe!\n"); + + chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) { + dev_err(&client->dev, + "i2c allocated device info data failed!\n"); + return -ENOMEM; + } + + chip->regmap = regmap_init_i2c(client, &halo7221_regmap_config); + if (!chip->regmap) { + pr_err("parent regmap is missing\n"); + return -EINVAL; + } + chip->name = DEVICE_NAME; + chip->client = client; + chip->dev = &client->dev; + + chip->bus.read = halo7221_read; + chip->bus.write = halo7221_write; + chip->bus.read_buf = halo7221_read_buffer; + chip->bus.write_buf = halo7221_write_buffer; + chip->bus.write_masked = halo7221_write_masked; + + device_init_wakeup(chip->dev, true); + i2c_set_clientdata(client, chip); + + ret = halo7221_parse_dt(chip); + if (ret < 0) { + dev_err(chip->dev, "%s: parse dt error [%d]\n", __func__, ret); + goto cleanup; + } + + ret = halo7221_gpio_init(chip); + if (ret < 0) { + dev_err(chip->dev, "%s: gpio init error [%d]\n", __func__, ret); + goto cleanup; + } + /* + ret = halo7221_hw_init(chip); + if (ret < 0) { + dev_err(chip->dev, "%s: chip hw init error [%d]\n", + __func__, ret); + goto cleanup; + } +*/ + + sysfs_create_group(&client->dev.kobj, &halo7221_sysfs_group); + + halo_cfg.drv_data = chip; + chip->halo_psy = + power_supply_register(chip->dev, &halo_psy_desc, &halo_cfg); + + dev_info(chip->dev, "Success probe halo7221 driver\n"); + + return 0; +cleanup: + i2c_set_clientdata(client, NULL); + + return rc; +} + +static int halo7221_remove(struct i2c_client *client) +{ + sysfs_remove_group(&client->dev.kobj, &halo7221_sysfs_group); + + return 0; +} + +static const struct i2c_device_id halo7221_dev_id[] = { + { DEVICE_NAME, 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, halo7221_dev_id); + +static struct i2c_driver halo7221_driver = { + .driver = { + .name = DEVICE_NAME, + .owner = THIS_MODULE, + .of_match_table = match_table, + }, + .probe = halo7221_probe, + .remove = halo7221_remove, + .id_table = halo7221_dev_id, +}; + +static int __init halo7221_init(void) +{ + int ret; + int drv_load = 0; + + drv_load = get_board_version(); + if (!drv_load) + return 0; + + ret = i2c_add_driver(&halo7221_driver); + if (ret) + printk(KERN_ERR "halo7221 i2c driver init failed!\n"); + + return ret; +} + +static void __exit halo7221_exit(void) +{ + i2c_del_driver(&halo7221_driver); +} + +module_init(halo7221_init); +module_exit(halo7221_exit); + +MODULE_AUTHOR("Yangwl@maxictech.com"); +MODULE_DESCRIPTION("halo7221 Wireless Power Receiver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/power/supply/lionsemi/Kconfig b/drivers/power/supply/lionsemi/Kconfig new file mode 100644 index 000000000000..4c4c97abd925 --- /dev/null +++ b/drivers/power/supply/lionsemi/Kconfig @@ -0,0 +1,14 @@ +menu "Lion Semiconductor Inc. Charger Support" + +config LN8282 + tristate "LN8282 Charge Pump" + depends on I2C + help + Say Y to include support for LN8282 charger pump. + LN8282 is a charger pump chip. + The driver supports charger enable/disable. + The driver reports the charger status via the power supply framework. + The driver controls 8282 via I2C and + supports device-tree interface. + +endmenu diff --git a/drivers/power/supply/lionsemi/Makefile b/drivers/power/supply/lionsemi/Makefile new file mode 100644 index 000000000000..a3ad4b3b5aba --- /dev/null +++ b/drivers/power/supply/lionsemi/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_LN8282) += ln8282.o diff --git a/drivers/power/supply/lionsemi/ln8282.c b/drivers/power/supply/lionsemi/ln8282.c new file mode 100644 index 000000000000..29a9f372a6b0 --- /dev/null +++ b/drivers/power/supply/lionsemi/ln8282.c @@ -0,0 +1,1088 @@ +/* + * Driver (skeleton code) for LIONSEMI LN8282 SC Voltage Regulator + * + * Copyright (C) 2019 Lion Semiconductor Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: Jae Lee + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LN8282_DRIVER_NAME "ln8282" +#define LN8282_HW_REV_Bx + +#define LN8282_DEBUG_OTP_CTRL + +/********************************************************************************* + * DESIGN GUIDE: + *********************************************************************************/ + +/********************************************************************************* + * register map + *********************************************************************************/ + +#define LN8282_MASK_SC_OPERATION_MODE 0x03 +#define LN8282_MASK_POWERON_IRQ_EN 0x04 +#define LN8282_MASK_SWAP_EN 0x80 + +#ifdef LN8282_HW_REV_Bx +#define LN8282_MASK_BC_SYS 0x1F +#else +#define LN8282_MASK_BC_SYS 0x0F +#endif + +#define LN8282_INT_BYTES 3 + +#define LN8282_REG_DEVICE_ID 0x00 +#define LN8282_REG_INT_DEVICE_0 0x01 +#define LN8282_REG_INT_DEVICE_1 0x02 +#define LN8282_REG_INT_HV_SC_0 0x03 +#define LN8282_REG_INT_HV_SC_1 0x04 +#define LN8282_REG_INT_DEVICE_0_MSK 0x05 +#define LN8282_REG_INT_DEVICE_1_MSK 0x06 +#define LN8282_REG_INT_HV_SC_0_MSK 0x07 +#define LN8282_REG_INT_HV_SC_1_MSK 0x08 +#define LN8282_REG_INT_DEVICE_0_STS 0x09 +#define LN8282_REG_INT_DEVICE_1_STS 0x0A +#define LN8282_REG_INT_HV_SC_0_STS 0x0B +#define LN8282_REG_INT_HV_SC_1_STS 0x0C +#define LN8282_REG_DEVICE_CTRL_0 0x0D +#define LN8282_REG_DEVICE_CTRL_1 0x0E +#define LN8282_REG_HV_SC_CTRL_0 0x0F +#define LN8282_REG_HV_SC_CTRL_1 0x10 +#define LN8282_REG_HV_SC_CTRL_2 0x11 +#define LN8282_REG_SC_DITHER_CTRL 0x12 +#define LN8282_REG_GLITCH_CTRL 0x13 +#define LN8282_REG_FAULT_CTRL 0x14 +#define LN8282_REG_TRACK_CTRL 0x15 +#define LN8282_REG_LION_CTRL 0x20 + +#define LN8282_REG_TRIM_4 0x25 +#define LN8282_REG_TRIM_7 0x28 + +#ifdef LN8282_HW_REV_Bx +#define LN8282_REG_BC_OP_SUPPORT_CTRL 0x2E +#define LN8282_REG_NVM_DIN 0x38 +#define LN8282_REG_NVM_CTRL 0x39 +#define LN8282_REG_NVM_DOUT 0x3A +#define LN8282_REG_STS_F 0x42 +#define LN8282_REG_STS_G 0x43 +#define LN8282_REG_INTERNAL_RSVD 0x4D +#define LN8282_MAX_REGISTER LN8282_REG_INTERNAL_RSVD +#else +#define LN8282_REG_BC_OP_SUPPORT_CTRL 0x2D +#define LN8282_REG_NVM_DIN 0x32 +#define LN8282_REG_NVM_CTRL 0x33 +#define LN8282_REG_NVM_DOUT 0x34 +#define LN8282_REG_STS_D 0x3A +#define LN8282_REG_DEVICE_MARKER 0x46 +#define LN8282_MAX_REGISTER LN8282_REG_DEVICE_MARKER +#endif + +#define LN8282_REG_PRINT(regmap, reg_addr, val) \ + do { \ + regmap_read(regmap, reg_addr, &val); \ + pr_info("ln8282_reg: --> [%-30s] 0x%02X : 0x%02X\n", \ + #reg_addr, reg_addr, val & 0xFF); \ + } while (0) + +/********************************************************************************* + * data structures / platform data + *********************************************************************************/ + +enum { + LN8282_STATE_UNKNOWN = -1, + LN8282_STATE_IDLE = 2, + LN8282_STATE_SW_ACTIVE = 7, + LN8282_STATE_BYPASS_ACTIVE = 12, +}; + +#define LN8282_TIMER_INIT 3 + +/** + * struct ln8282_info - ln8282 regulator instance + * @monitor_wake_lock: lock to enter the suspend mode + * @lock: protects concurrent access to online variables + * @client: pointer to client + * @regmap: pointer to driver regmap + * @op_mode : chip operation mode (STANDBY, BYPASS, SWITCHING) + * @reverse_power : enable reverse power path + * @pdata: pointer to platform data + */ + +struct ln8282_dt_props { + unsigned int enable_gpio; +}; + +struct ln8282_info { + char *name; + struct device *dev; + struct i2c_client *client; + struct mutex lock; + struct regmap *regmap; + + int op_mode; + bool reverse_power; + bool auto_recovery; + + struct ln8282_dt_props dt_props; + struct pinctrl *ln_pinctrl; + struct pinctrl_state *ln_gpio_active; + struct pinctrl_state *ln_gpio_suspend; + + struct power_supply *ln_psy; +}; + +static struct ln8282_info *g_info; + +static const struct regmap_config ln8282_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = LN8282_MAX_REGISTER, +}; + +/********************************************************************************* + * supported CORE functionality + *********************************************************************************/ + +void ln8282_use_ext_5V(struct ln8282_info *info, unsigned int enable) +{ + regmap_update_bits(info->regmap, LN8282_REG_DEVICE_CTRL_1, 0x01, + (enable & 0x01)); +} +EXPORT_SYMBOL(ln8282_use_ext_5V); + +void ln8282_set_infet(struct ln8282_info *info, unsigned int enable) +{ + regmap_update_bits(info->regmap, LN8282_REG_DEVICE_CTRL_0, 0x01, + (enable & 0x01)); +} +EXPORT_SYMBOL(ln8282_set_infet); + +void ln8282_set_powerpath(struct ln8282_info *info, bool forward_path) +{ + info->reverse_power = (!forward_path); +} +EXPORT_SYMBOL(ln8282_set_powerpath); + +/* add for other module run */ +/* +void ln8282_set_powerpath_ext(bool forward_path) +{ + g_info->reverse_power = (!forward_path); + printk("%s:reverse_power:%d\n", __func__, g_info->reverse_power); +} +*/ + +static inline int ln8282_get_opmode(struct ln8282_info *info) +{ + int val; + if (regmap_read(info->regmap, LN8282_REG_HV_SC_CTRL_0, &val) < 0) + val = LN8282_OPMODE_UNKNOWN; + return (val & LN8282_MASK_SC_OPERATION_MODE); +} + +/* add for wireless driver get opmode */ +/* +unsigned int ln8282_get_opmode_ext(void) +{ + int val; + if (regmap_read(g_info->regmap, LN8282_REG_HV_SC_CTRL_0, &val) < 0) + val = LN8282_OPMODE_UNKNOWN; + return (val & LN8282_MASK_SC_OPERATION_MODE); +} +*/ +static inline void ln8282_auto_recovery(struct ln8282_info *info, + unsigned int enable) +{ + regmap_update_bits(info->regmap, LN8282_REG_DEVICE_CTRL_1, 0x40, + (enable << 6)); +} + +/* configure minimum set of control registers */ +static inline void ln8282_set_base_opt_Bx(struct ln8282_info *info, + unsigned int sc_out_precharge_cfg, + unsigned int vbus_in_max_ov_cfg, + unsigned int track_cfg) +{ + regmap_update_bits(info->regmap, LN8282_REG_HV_SC_CTRL_1, 0x60, + (vbus_in_max_ov_cfg << 6) | + (sc_out_precharge_cfg << 5)); + regmap_update_bits(info->regmap, LN8282_REG_TRACK_CTRL, 0x10, + (track_cfg << 4)); + + ln8282_auto_recovery(info, 1); +} + +static inline void ln8282_set_vbus_uv_track(struct ln8282_info *info, + unsigned int disable) +{ + regmap_update_bits(info->regmap, LN8282_REG_TRACK_CTRL, 0x04, + (disable << 2)); +} + +static inline void ln8282_set_switch_seq(struct ln8282_info *info, + unsigned int alt_en) +{ + regmap_write(info->regmap, LN8282_REG_LION_CTRL, 0x5B); + regmap_update_bits(info->regmap, LN8282_REG_TRIM_4, 0x04, + (alt_en << 2)); + regmap_write(info->regmap, LN8282_REG_LION_CTRL, 0x00); +} + +static void ln8282_enter_standby(struct ln8282_info *info) +{ + regmap_update_bits(info->regmap, LN8282_REG_HV_SC_CTRL_0, + LN8282_MASK_SC_OPERATION_MODE, + LN8282_OPMODE_STANDBY); + ln8282_set_base_opt_Bx(info, 1, 0, 1); + regmap_write(info->regmap, LN8282_REG_FAULT_CTRL, 0x04); +} + +static void ln8282_enter_bypass(struct ln8282_info *info) +{ + ln8282_set_base_opt_Bx(info, 1, 0, 1); + + if (info->reverse_power) + regmap_write(info->regmap, LN8282_REG_FAULT_CTRL, 0x0B); + else + regmap_write(info->regmap, LN8282_REG_FAULT_CTRL, 0x0C); + + regmap_update_bits(info->regmap, LN8282_REG_HV_SC_CTRL_0, + LN8282_MASK_SC_OPERATION_MODE, LN8282_OPMODE_BYPASS); +} + +static bool ln8282_vin_switch_ok(struct ln8282_info *info) +{ + int val; + if (regmap_read(info->regmap, LN8282_REG_INT_DEVICE_0_STS, &val) < 0) { + pr_warn("%s: Unable to read INT_DEVICE_0_STS\n", __func__); + return false; + } + + if ((val & 0x08) <= 0) { + pr_warn("%s: INVALID VIN range for switching operation.\n", + __func__); + return false; + } + + return true; +} + +static void ln8282_enter_switching(struct ln8282_info *info) +{ + if (info->reverse_power) { + pr_info("%s:set switch in reverse mode\n"); + ln8282_set_switch_seq(info, 0); + ln8282_set_base_opt_Bx(info, 0, 1, 0); + ln8282_set_vbus_uv_track(info, 1); + regmap_write(info->regmap, LN8282_REG_FAULT_CTRL, 0x09); + } else { + if (!ln8282_vin_switch_ok(info)) { + pr_warn("%s: Failed to transition to forward SWITCHING mode.\n", + __func__); + return; + } + pr_info("%s:set switch in forward mode\n"); + ln8282_set_switch_seq(info, 1); + ln8282_set_base_opt_Bx(info, 0, 1, 0); + regmap_write(info->regmap, LN8282_REG_FAULT_CTRL, 0x04); + } + + regmap_update_bits(info->regmap, LN8282_REG_HV_SC_CTRL_0, + LN8282_MASK_SC_OPERATION_MODE, + LN8282_OPMODE_SWITCHING); + + if (info->reverse_power) { + msleep(50); + ln8282_set_vbus_uv_track(info, 0); + } else { + msleep(100); + regmap_write(info->regmap, LN8282_REG_FAULT_CTRL, 0x0C); + } +} +/* main function for setting/changing operation mode */ +bool ln8282_change_opmode(struct ln8282_info *info, unsigned int target_mode) +{ + bool ret; + + info->op_mode = ln8282_get_opmode(info); + if (target_mode < 0 || target_mode > LN8282_OPMODE_SWITCHING_ALT) { + pr_err("%s: target operation mode (0x%02X) is invalid\n", + __func__, target_mode); + return false; + } + /* NOTE: + * CUSTOMER should know/indicate if power path is forward/reverse mode + * based on power connections before attempting to change operation mode + */ + + dev_info(info->dev, "opmode from %d change to %d\n", info->op_mode, + target_mode); + ret = true; + switch (target_mode) { + case LN8282_OPMODE_STANDBY: + ln8282_enter_standby(info); + break; + case LN8282_OPMODE_BYPASS: + ln8282_enter_bypass(info); + break; + case LN8282_OPMODE_SWITCHING: + case LN8282_OPMODE_SWITCHING_ALT: + ln8282_enter_switching(info); + break; + default: + ret = false; + } + return ret; +} +EXPORT_SYMBOL(ln8282_change_opmode); + +/* +bool ln8282_change_opmode_ext(unsigned int target_mode) +{ + g_info->op_mode = ln8282_get_opmode(g_info); + + if (target_mode < 0 || target_mode > LN8282_OPMODE_SWITCHING_ALT) { + pr_err("%s: target operation mode (0x%02X) is invalid\n", + __func__, target_mode); + return false; + } + printk("opmode from %d change to %d\n", g_info->op_mode, target_mode); + switch (target_mode) { + case LN8282_OPMODE_STANDBY: + ln8282_enter_standby(g_info); + break; + case LN8282_OPMODE_BYPASS: + ln8282_enter_bypass(g_info); + break; + case LN8282_OPMODE_SWITCHING: + case LN8282_OPMODE_SWITCHING_ALT: + ln8282_enter_switching(g_info); + break; + default: + return false; + } + return true; +} +*/ + +int ln8282_hw_init(struct ln8282_info *info) +{ + /* NOTES: + * When power source is removed, LN8282 is powered off and all register settings are lost + * So, LN8282 should be re-initialized every time it is powered on + * This routine should be called when the RX IC or PMIC detects a new power source + */ + + /* CUSTOMER should add basic initialization tasks + * -- unmasking interrupts + * -- overriding OTP settings, etc + */ + pr_info("%s: HW initialization\n", __func__); + +#ifdef LN8282_HW_REV_A1 + regmap_update_bits(info->regmap, LN8282_REG_HV_SC_CTRL_1, 0x10, + (1 << 4)); + regmap_update_bits(info->regmap, LN8282_REG_TRACK_CTRL, 0x04, (1 << 2)); +#endif + +#ifdef LN8282_HW_REV_Bx + regmap_write(info->regmap, LN8282_REG_LION_CTRL, 0x5B); + + regmap_update_bits(info->regmap, LN8282_REG_TRIM_7, LN8282_MASK_SWAP_EN, + 0 /*<<7*/); + regmap_write(info->regmap, LN8282_REG_LION_CTRL, 0x00); +#endif + + info->reverse_power = false; + + return 1; +} +EXPORT_SYMBOL(ln8282_hw_init); + +/********************************************************************************* + * (experimental) OTP support : NEVER use this in production releases + *********************************************************************************/ + +#ifdef LN8282_DEBUG_OTP_CTRL +#define LN8282_OTP_MASK_WRITE_EN 0x10 +#define LN8282_OTP_MASK_CS 0x80 +#define LN8282_OTP_MASK_ADDR 0x0F +#define LN8282_OTP_MASK_PROG 0x20 +static void ln8282_otp_power(struct ln8282_info *info, const bool enable) +{ + if (enable) { + msleep(2); + regmap_update_bits(info->regmap, LN8282_REG_BC_OP_SUPPORT_CTRL, + 0x02, (1 << 1)); //VPP_to_HV=1 + msleep(1); + } else { + //power down (lower VPP) + msleep(2); + regmap_update_bits(info->regmap, LN8282_REG_BC_OP_SUPPORT_CTRL, + 0x02, (0 << 1)); //VPP_to_HV=0 + msleep(1); + } +} + +static void ln8282_otp_write(struct ln8282_info *info, unsigned int otp_addr, + unsigned int otp_data) +{ + unsigned int nvm_ctrl; //NVM_CTRL value + + regmap_write(info->regmap, LN8282_REG_LION_CTRL, 0x5B); + ln8282_otp_power(info, true /*power-up*/); + + regmap_write(info->regmap, LN8282_REG_NVM_DIN, 0xFF); + nvm_ctrl = 0xFF & LN8282_OTP_MASK_WRITE_EN; + regmap_write(info->regmap, LN8282_REG_NVM_CTRL, nvm_ctrl); + + msleep(1); + + nvm_ctrl |= (0xFF & LN8282_OTP_MASK_CS); //CS = 1 + regmap_write(info->regmap, LN8282_REG_NVM_CTRL, nvm_ctrl); + + regmap_write(info->regmap, LN8282_REG_NVM_DIN, otp_data); + + nvm_ctrl |= (LN8282_OTP_MASK_ADDR & otp_addr); + regmap_write(info->regmap, LN8282_REG_NVM_CTRL, nvm_ctrl); + udelay(6); + + nvm_ctrl |= (0xFF & LN8282_OTP_MASK_PROG); + regmap_write(info->regmap, LN8282_REG_NVM_CTRL, nvm_ctrl); + + udelay(220); + + nvm_ctrl &= (0xFF & ~LN8282_OTP_MASK_PROG); + regmap_write(info->regmap, LN8282_REG_NVM_CTRL, nvm_ctrl); + + udelay(6 * 2); + + regmap_write(info->regmap, LN8282_REG_NVM_DIN, 0xFF); + + nvm_ctrl &= (0xFF & ~LN8282_OTP_MASK_CS); + regmap_write(info->regmap, LN8282_REG_NVM_CTRL, nvm_ctrl); + + udelay(6); + + nvm_ctrl &= (0xFF & ~LN8282_OTP_MASK_WRITE_EN); + regmap_write(info->regmap, LN8282_REG_NVM_CTRL, nvm_ctrl); + + ln8282_otp_power(info, false /*power-down*/); + regmap_write(info->regmap, LN8282_REG_LION_CTRL, 0x00); +} + +#endif + +/********************************************************************************* + * LION-DEBUG: user-space interaction through sysfs (for testing only) + *********************************************************************************/ + +static unsigned int ln8282_regcmd_addr; +static unsigned int ln8282_regcmd_data; +static bool ln8282_regcmd_valid; + +static ssize_t ln8282_sysfs_show_regcmd(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + if (ln8282_regcmd_valid) { + pr_info("%s: /sysfs/ return stored data value (0x%02X)\n", + __func__, ln8282_regcmd_data & 0xFF); + return scnprintf(buf, PAGE_SIZE, "0x%02x\n", + ln8282_regcmd_data & 0xFF); + } else { + pr_warn("%s: /sysfs/ regcmd is invalid or was not issued\n", + __func__); + return scnprintf(buf, PAGE_SIZE, "NA\n"); + } +} + +static ssize_t ln8282_sysfs_store_regcmd(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + bool write_cmd; + int ret; + /* command format: + * >>read,0x01 : read from 0x01 + * >>write,0x01,0xAA : write to 0x01 + */ + + ln8282_regcmd_valid = false; + if (strncmp("read,", buf, 5) == 0) + write_cmd = false; + else if (strncmp("write,", buf, 6) == 0) + write_cmd = true; + else { + pr_warn("%s: /sysfs/ invalid command: %s\n", __func__, buf); + goto parse_error; + } + + if (write_cmd) { + if (sscanf(buf, "write,%x,%x", &ln8282_regcmd_addr, + &ln8282_regcmd_data) != 2) + goto parse_error; + if (ln8282_regcmd_addr > LN8282_MAX_REGISTER || + ln8282_regcmd_data > 0xFF) { + pr_warn("%s: /sysfs/ write command addr/data out of bounds\n", + __func__); + goto parse_error; + } + + pr_info("%s: /sysfs/ writing to addr 0x%02X (data=0x%02X)\n", + __func__, ln8282_regcmd_addr, ln8282_regcmd_data); + ret = regmap_write(info->regmap, ln8282_regcmd_addr, + ln8282_regcmd_data); + } else { + if (sscanf(buf, "read,%x", &ln8282_regcmd_addr) != 1) + goto parse_error; + if (ln8282_regcmd_addr > LN8282_MAX_REGISTER) { + pr_warn("%s: /sysfs/ read command addr out of bounds\n", + __func__); + goto parse_error; + } + + pr_info("%s: /sysfs/ reading from addr 0x%02X\n", __func__, + ln8282_regcmd_addr); + ret = regmap_read(info->regmap, ln8282_regcmd_addr, + &ln8282_regcmd_data); + } + if (ret < 0) + return ret; + + ln8282_regcmd_valid = true; + return count; + +parse_error: + pr_warn("%s: /sysfs/ unable to parse command (%s)\n", __func__, buf); + return count; +} + +static ssize_t ln8282_sysfs_show_opmode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + int ret; + + pr_info("%s: /sysfs/ retrieve op_mode\n", __func__); + + info->op_mode = ln8282_get_opmode(info); + switch (info->op_mode) { + case LN8282_OPMODE_STANDBY: + ret = scnprintf(buf, PAGE_SIZE, "standby\n"); + break; + case LN8282_OPMODE_BYPASS: + ret = scnprintf(buf, PAGE_SIZE, "bypass\n"); + break; + case LN8282_OPMODE_SWITCHING: + case LN8282_OPMODE_SWITCHING_ALT: + ret = scnprintf(buf, PAGE_SIZE, "switching\n"); + break; + case LN8282_OPMODE_UNKNOWN: + default: + ret = scnprintf(buf, PAGE_SIZE, "unknown\n"); + } + return ret; +} + +static ssize_t ln8282_sysfs_show_dump(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + int val; + + pr_info("----------------------/dump/---------------------\n"); + pr_info("ln8282_reg: [ %-19s] /addr/ : /value/\n", + "Register Name"); + LN8282_REG_PRINT(info->regmap, LN8282_REG_DEVICE_CTRL_0, val); + LN8282_REG_PRINT(info->regmap, LN8282_REG_HV_SC_CTRL_0, val); + LN8282_REG_PRINT(info->regmap, LN8282_REG_HV_SC_CTRL_1, val); + LN8282_REG_PRINT(info->regmap, LN8282_REG_FAULT_CTRL, val); + LN8282_REG_PRINT(info->regmap, LN8282_REG_TRACK_CTRL, val); + +#ifdef LN8282_HW_REV_Bx + LN8282_REG_PRINT(info->regmap, LN8282_REG_STS_F, val); + LN8282_REG_PRINT(info->regmap, LN8282_REG_STS_G, val); +#else + LN8282_REG_PRINT(info->regmap, LN8282_REG_STS_D, val); +#endif + + pr_info("----------------------/dump/---------------------\n"); + return scnprintf(buf, PAGE_SIZE, "done\n"); +} + +static ssize_t ln8282_sysfs_store_opmode(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + int opmode; + + if (strncmp("standby", buf, 7) == 0) + opmode = LN8282_OPMODE_STANDBY; + else if (strncmp("bypass", buf, 6) == 0) + opmode = LN8282_OPMODE_BYPASS; + else if (strncmp("switching", buf, 9) == 0) + opmode = LN8282_OPMODE_SWITCHING; + else + opmode = LN8282_OPMODE_UNKNOWN; + pr_info("%s: /sysfs/ set op_mode to 0x%02X==%s", __func__, opmode, buf); + + if (!ln8282_change_opmode(info, opmode)) + pr_warn("%s: /sysfs/ unable to enter %s\n", __func__, buf); + return count; +} + +static ssize_t ln8282_sysfs_store_infet(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + unsigned int enable; + if (strncmp("1", buf, 1) == 0) + enable = 1; + else + enable = 0; + ln8282_set_infet(info, enable); + return count; +} + +static ssize_t ln8282_sysfs_store_ext_5v(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + unsigned int enable; + if (strncmp("1", buf, 1) == 0) + enable = 1; + else + enable = 0; + ln8282_use_ext_5V(info, enable); + return count; +} + +static ssize_t ln8282_sysfs_store_powerpath(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + bool forward; + if (strncmp("forward", buf, 1) == 0) + forward = true; + else + forward = false; + ln8282_set_powerpath(info, forward); + return count; +} + +static ssize_t ln8282_sysfs_hw_init(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + + ln8282_hw_init(info); + return scnprintf(buf, PAGE_SIZE, "done\n"); +} + +#ifdef LN8282_DEBUG_OTP_CTRL +static ssize_t ln8282_sysfs_otp_overwrite(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ln8282_info *info = dev_get_drvdata(dev); + +#ifdef LN8282_HW_REV_Bx + pr_info("%s: ********************** WARNING **********************\n", + __func__); + pr_info("%s: --> this is an experimental feature (temporary fix)\n", + __func__); + pr_info("%s: NEVER use this in production release\n", __func__); + pr_info("%s: --> begin to overwrite OTP cell [0xF] to 0xF8\n", + __func__); + + ln8282_otp_write(info, 0x0F /*OTP cell addr*/, 0xF8 /*new OTP value*/); + + pr_info("%s: --> finished overwriting OTP cell\n", __func__); + pr_info("%s: --> now, unplug/re-plugin VIN to power-up chip\n", + __func__); + pr_info("%s: *****************************************************\n", + __func__); +#endif + + return scnprintf(buf, PAGE_SIZE, + "unplug VIN to power-up LN8282 again\n"); +} +static DEVICE_ATTR(otp_overwrite, 0444, ln8282_sysfs_otp_overwrite, NULL); +#endif + +static DEVICE_ATTR(dump, 0444, ln8282_sysfs_show_dump, NULL); +static DEVICE_ATTR(hw_init, 0444, ln8282_sysfs_hw_init, NULL); +static DEVICE_ATTR(infet, 0200, NULL, ln8282_sysfs_store_infet); +static DEVICE_ATTR(ext_5v, 0200, NULL, ln8282_sysfs_store_ext_5v); +static DEVICE_ATTR(powerpath, 0200, NULL, ln8282_sysfs_store_powerpath); +static DEVICE_ATTR(opmode, 0644, ln8282_sysfs_show_opmode, + ln8282_sysfs_store_opmode); +static DEVICE_ATTR(regcmd, 0644, ln8282_sysfs_show_regcmd, + ln8282_sysfs_store_regcmd); +static struct attribute *ln8282_info_attr[] = { + &dev_attr_dump.attr, &dev_attr_hw_init.attr, +#ifdef LN8282_DEBUG_OTP_CTRL + &dev_attr_otp_overwrite.attr, +#endif + &dev_attr_regcmd.attr, &dev_attr_opmode.attr, + &dev_attr_infet.attr, &dev_attr_ext_5v.attr, + &dev_attr_powerpath.attr, NULL, +}; + +static const struct attribute_group ln8282_attr_group = { + .attrs = ln8282_info_attr, +}; + +/********************************************************************************* + * device layer + *********************************************************************************/ + +static int ln8282_parse_dt(struct ln8282_info *info) +{ + struct device_node *node = info->dev->of_node; + if (!node) { + dev_err(info->dev, "device tree node missing\n"); + return -EINVAL; + } + + info->dt_props.enable_gpio = of_get_named_gpio(node, "ln,enable", 0); + if ((!gpio_is_valid(info->dt_props.enable_gpio))) + return -EINVAL; + + return 0; +} + +static int ln8282_gpio_init(struct ln8282_info *info) +{ + int ret = 0; + + info->ln_pinctrl = devm_pinctrl_get(info->dev); + if (IS_ERR_OR_NULL(info->ln_pinctrl)) { + dev_err(info->dev, "No pinctrl config specified\n"); + ret = PTR_ERR(info->dev); + return ret; + } + info->ln_gpio_active = + pinctrl_lookup_state(info->ln_pinctrl, "ln8282_active"); + if (IS_ERR_OR_NULL(info->ln_gpio_active)) { + dev_err(info->dev, "No active config specified\n"); + ret = PTR_ERR(info->ln_gpio_active); + return ret; + } + info->ln_gpio_suspend = + pinctrl_lookup_state(info->ln_pinctrl, "ln8282_suspend"); + if (IS_ERR_OR_NULL(info->ln_gpio_suspend)) { + dev_err(info->dev, "No suspend config specified\n"); + ret = PTR_ERR(info->ln_gpio_suspend); + return ret; + } + + ret = pinctrl_select_state(info->ln_pinctrl, info->ln_gpio_active); + if (ret < 0) { + dev_err(info->dev, "fail to select pinctrl active rc=%d\n", + ret); + return ret; + } + + return ret; +} + +extern char *saved_command_line; + +static int get_board_version(void) +{ + char boot[5] = { '\0' }; + char *match = (char *)strnstr( + saved_command_line, + "androidboot.hwlevel=", strlen(saved_command_line)); + if (match) { + memcpy(boot, (match + strlen("androidboot.hwlevel=")), + sizeof(boot) - 1); + printk("%s: hwlevel is %s\n", __func__, boot); + if (!strncmp(boot, "P1.3", strlen("P1.3"))) + return 0; + } + return 1; +} + +#define FORWARD_BYPASS 1 +#define FORWARD_SWITCH 2 +#define REVERSE_SWITCH 3 +#define REVERSE_BYPASS 4 +static int ln8282_set_mode(struct ln8282_info *info, int mode) +{ + int ret = 0; + switch (mode) { + case FORWARD_BYPASS: + ln8282_set_powerpath(info, true); + ln8282_change_opmode(info, LN8282_OPMODE_BYPASS); + break; + case FORWARD_SWITCH: + ln8282_set_powerpath(info, true); + ln8282_change_opmode(info, LN8282_OPMODE_SWITCHING); + break; + case REVERSE_SWITCH: + ln8282_set_powerpath(info, false); + ln8282_change_opmode(info, LN8282_OPMODE_SWITCHING); + break; + case REVERSE_BYPASS: + ln8282_set_powerpath(info, false); + ln8282_change_opmode(info, LN8282_OPMODE_BYPASS); + default: + dev_err(info->dev, "%s: invalid settings\n", __func__); + } + + info->op_mode = ln8282_get_opmode(info); + + return ret; +} + +static enum power_supply_property ln8282_props[] = { + POWER_SUPPLY_PROP_DIV_2_MODE, + POWER_SUPPLY_PROP_RESET_DIV_2_MODE, +}; + +static int ln8282_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct ln8282_info *info = power_supply_get_drvdata(psy); + + switch (psp) { + case POWER_SUPPLY_PROP_DIV_2_MODE: + val->intval = info->op_mode; + break; + default: + return -EINVAL; + } + return 0; +} + +static int ln8282_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct ln8282_info *info = power_supply_get_drvdata(psy); + int rc = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_DIV_2_MODE: + rc = ln8282_set_mode(info, val->intval); + break; + case POWER_SUPPLY_PROP_RESET_DIV_2_MODE: + info->op_mode = 0; + break; + default: + return -EINVAL; + } + + return rc; +} + +static int ln8282_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + int rc; + + switch (psp) { + case POWER_SUPPLY_PROP_DIV_2_MODE: + case POWER_SUPPLY_PROP_RESET_DIV_2_MODE: + return 1; + default: + rc = 0; + break; + } + + return rc; +} + +static const struct power_supply_desc ln_psy_desc = { + .name = "lionsemi", + .type = POWER_SUPPLY_TYPE_WIRELESS, + .properties = ln8282_props, + .num_properties = ARRAY_SIZE(ln8282_props), + .get_property = ln8282_get_prop, + .set_property = ln8282_set_prop, + .property_is_writeable = ln8282_prop_is_writeable, +}; + +static int ln8282_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ln8282_info *info; + struct power_supply_config ln_cfg = {}; + int ret = 0; + pr_info("%s: =/START-PROBE/=\n", __func__); + + /* allocate memory for our device state and initialize it */ + info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); + if (info == NULL) + return -ENOMEM; + + mutex_init(&info->lock); + info->name = LN8282_DRIVER_NAME; + info->client = client; + info->dev = &client->dev; + i2c_set_clientdata(client, info); + + info->regmap = devm_regmap_init_i2c(client, &ln8282_regmap_config); + if (IS_ERR(info->regmap)) { + pr_err("%s: failed to initialize regmap\n", __func__); + return PTR_ERR(info->regmap); + } + + ret = ln8282_parse_dt(info); + if (ret < 0) { + dev_err(info->dev, "%s: parse dt error [%d]\n", __func__, ret); + goto cleanup; + } + + ret = ln8282_gpio_init(info); + if (ret < 0) { + dev_err(info->dev, "%s: gpio init error [%d]\n", __func__, ret); + goto cleanup; + } + + /* LION-DEBUG: test user-app through sysfs */ + if (sysfs_create_group(&info->client->dev.kobj, &ln8282_attr_group) < + 0) { + pr_err("%s: unable to create sysfs entries\n", __func__); + return -EINVAL; + } + + g_info = info; + + ln_cfg.drv_data = info; + info->ln_psy = power_supply_register(info->dev, &ln_psy_desc, &ln_cfg); + + pr_info("[ln8282]%s: success probe!\n", __func__); + return 0; + +cleanup: + i2c_set_clientdata(client, NULL); + return 0; +} + +static int ln8282_remove(struct i2c_client *client) +{ + struct ln8282_info *info = i2c_get_clientdata(client); + + dev_err(info->dev, "%s: driver remove\n", __func__); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int ln8282_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ln8282_info *info = i2c_get_clientdata(client); + + /* don't set bypass when suspend for reverse charge + ln8282_change_opmode(info, LN8282_OPMODE_BYPASS); + */ + dev_info(info->dev, "%s: suspend\n", __func__); + + return 0; +} + +static int ln8282_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ln8282_info *info = i2c_get_clientdata(client); + + pr_info("%s: update/resume\n", __func__); + dev_err(info->dev, "%s: resume\n", __func__); + return 0; +} +#endif +static SIMPLE_DEV_PM_OPS(ln8282_pm_ops, ln8282_suspend, ln8282_resume); + +#ifdef CONFIG_OF +static const struct of_device_id ln8282_dt_match[] = { + { .compatible = "lionsemi,ln8282" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ln8282_dt_match); +#endif + +static const struct i2c_device_id ln8282_id[] = { { "ln8282", 0 }, {} }; +MODULE_DEVICE_TABLE(i2c, ln8282_id); + +static struct i2c_driver ln8282_driver = { + .driver = { + .name = LN8282_DRIVER_NAME, + .of_match_table = of_match_ptr(ln8282_dt_match), + .pm = &ln8282_pm_ops, + }, + .probe = ln8282_probe, + .remove = ln8282_remove, + .id_table = ln8282_id, +}; + +static int __init ln8282_init(void) +{ + int ret; + int drv_load = 0; + + drv_load = get_board_version(); + if (!drv_load) + return 0; + + ret = i2c_add_driver(&ln8282_driver); + if (ret) + printk(KERN_ERR "ln8282 i2c driver init failed!\n"); + + return ret; +} + +static void __exit ln8282_exit(void) +{ + i2c_del_driver(&ln8282_driver); +} + +module_init(ln8282_init); +module_exit(ln8282_exit); + +MODULE_AUTHOR("Jae Lee"); +MODULE_DESCRIPTION("LN8282 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("0.3.0"); diff --git a/drivers/power/supply/maxim/Kconfig b/drivers/power/supply/maxim/Kconfig new file mode 100644 index 000000000000..8a7e1448e4c8 --- /dev/null +++ b/drivers/power/supply/maxim/Kconfig @@ -0,0 +1,27 @@ +menu "Maxim Integrated Products, Inc. Charger support" + +config BATT_VERIFY_BY_DS28E16 + tristate + prompt "Support ds28e16 as encryption IC." + help + It needs a onewire physical controller to work. + +config ONEWIRE_GPIO + tristate + prompt "Support Onewire Driver." + help + It's an onewire driver. + +config BATT_VERIFY_BY_DS28E16_NABU + tristate + prompt "Support ds28e16 as encryption IC." + help + It needs a onewire physical controller to work. + +config ONEWIRE_GPIO_NABU + tristate + prompt "Support Onewire Driver." + help + It's an onewire driver. + +endmenu diff --git a/drivers/power/supply/maxim/Makefile b/drivers/power/supply/maxim/Makefile new file mode 100644 index 000000000000..2e1cbc021058 --- /dev/null +++ b/drivers/power/supply/maxim/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ONEWIRE_GPIO) += onewire_gpio.o +obj-$(CONFIG_BATT_VERIFY_BY_DS28E16) += onewire_gpio.o ucl_sha3.o sha384_software.o ds28e16.o +obj-$(CONFIG_ONEWIRE_GPIO_NABU) += onewire_gpio_master.o onewire_gpio_slave.o +obj-$(CONFIG_BATT_VERIFY_BY_DS28E16_NABU) += onewire_gpio_master.o onewire_gpio_slave.o ucl_sha3.o sha384_software.o ds28e16_master.o ds28e16_slave.o diff --git a/drivers/power/supply/maxim/ds28e16.c b/drivers/power/supply/maxim/ds28e16.c new file mode 100644 index 000000000000..2947b5b361c8 --- /dev/null +++ b/drivers/power/supply/maxim/ds28e16.c @@ -0,0 +1,1904 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + ******************************************************************************* + * + * DS28E16.c - DS28E16 device module. Requires low level 1-Wire connection. + */ +#define pr_fmt(fmt) "[ds28e16] %s: " fmt, __func__ + +#include /* kfree() */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sha384_software.h" +#include "ds28e16.h" +#include "onewire_gpio.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ds_info pr_err +#define ds_dbg pr_err +#define ds_err pr_err +#define ds_log pr_err + +struct ds28e16_data { + struct platform_device *pdev; + struct device *dev; + + int version; + + struct power_supply *verify_psy; + struct power_supply_desc verify_psy_d; + + struct delayed_work authentic_work; +}; + +unsigned int attr_trytimes = 1; + +unsigned char session_seed[32] = { 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA }; +unsigned char S_secret[32] = { 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA }; +unsigned char challenge[32] = { 0x00 }; +int auth_ANON = 1; +int auth_BDCONST = 1; +int pagenumber = 1; + +// maxim define +int tm = 1; +unsigned short CRC16; +const short oddparity[16] = { 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 }; +unsigned char last_result_byte = RESULT_SUCCESS; + +unsigned char MANID[2] = { 0x00 }; + +// mi add +unsigned char flag_mi_romid = 0; +unsigned char flag_mi_status = 0; +unsigned char flag_mi_page0_data = 0; +unsigned char flag_mi_page1_data = 0; +unsigned char flag_mi_counter = 0; +unsigned char flag_mi_auth_result = 0; +unsigned char mi_romid[8] = { 0x00 }; +unsigned char mi_status[8] = { 0x00 }; +unsigned char mi_page0_data[16] = { 0x00 }; +unsigned char mi_page1_data[16] = { 0x00 }; +unsigned char mi_counter[16] = { 0x00 }; +int mi_auth_result = 0x00; + +unsigned char crc_low_first(unsigned char *ptr, unsigned char len) +{ + unsigned char i; + unsigned char crc = 0x00; + + while (len--) { + crc ^= *ptr++; + for (i = 0; i < 8; ++i) { + if (crc & 0x01) + crc = (crc >> 1) ^ 0x8c; + else + crc = (crc >> 1); + } + } + + return (crc); +} + +short Read_RomID(unsigned char *RomID) +{ + unsigned char i; + unsigned char crc = 0x00; + + if (flag_mi_romid == 2) { + memcpy(RomID, mi_romid, 8); + ds_log("lvchen---Read_RomID00\n"); + return DS_TRUE; + } + + if ((ow_reset()) != 0) { + ds_err("Read_RomID: Failed to reset ds28e16!\n"); + ow_reset(); + return ERROR_NO_DEVICE; + } + + ds_dbg("Ready to write 0x33 to maxim IC!\n"); + write_byte(CMD_READ_ROM); + Delay_us(10); + for (i = 0; i < 8; i++) + RomID[i] = read_byte(); + + ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", RomID[0], + RomID[1], RomID[2], RomID[3], RomID[4], RomID[5], RomID[6], + RomID[7]); + + crc = crc_low_first(RomID, 7); + ds_dbg("crc_low_first = %02x\n", crc); + + if (crc == RomID[7]) { + memcpy(mi_romid, RomID, 8); + if (mi_romid[0] == FAMILY_CODE && + mi_romid[6] == CUSTOM_ID_MSB && + (mi_romid[5] & 0xF0) == CUSTOM_ID_LSB) + flag_mi_romid = 2; + return DS_TRUE; + } else { + ow_reset(); + ds_log("lvchen---Read_RomID33\n"); + return DS_FALSE; + } +} + +unsigned short docrc16(unsigned short data) +{ + data = (data ^ (CRC16 & 0xff)) & 0xff; + CRC16 >>= 8; + + if (oddparity[data & 0xf] ^ oddparity[data >> 4]) + CRC16 ^= 0xc001; + + data <<= 6; + CRC16 ^= data; + data <<= 1; + CRC16 ^= data; + + return CRC16; +} + +int DS28E16_standard_cmd_flow(unsigned char *write_buf, int delay_ms, + unsigned char *read_buf, int *read_len, + int write_len) +{ + unsigned char buf[128]; + int i; + int buf_len = 0; + int expected_read_len = *read_len; + + //NEW FLOW + /*'1 Wire + ''''''''''''''''''''''' + ? + ? + ?TX: Start Command + ?TX: Length Byte + ?TX: Memory Command + ?TX: Parameter, TX: Data + ?RX: CRC16 + ?TX: Release Byte + ? + ?RX: Dummy Byte + ?RX: Length Byte + ?RX: Result byte + ?RX: CRC16 + ?< wait for reset> + '''''''''''''''''''''''*/ + ds_dbg("DS28E16_standard_cmd_flow start\n"); + + if ((ow_reset()) != 0) { + ds_err("Failed to reset ds28e16!\n"); + ow_reset(); + return ERROR_NO_DEVICE; + } + + write_byte(CMD_SKIP_ROM); + + buf[buf_len++] = CMD_START; + memcpy(&buf[buf_len], write_buf, write_len); + buf_len += write_len; + for (i = 0; i < buf_len; i++) + write_byte(buf[i]); + + buf[buf_len++] = read_byte(); + buf[buf_len++] = read_byte(); + + CRC16 = 0; + for (i = 0; i < buf_len; i++) + docrc16(buf[i]); + + if (CRC16 != 0xB001) { + ow_reset(); + ds_dbg("DS28E16_standard_cmd_flow: crc error!\n"); + return DS_FALSE; + } + + // check for strong pull-up + if (delay_ms > 0) { + write_byte(CMD_RELEASE_BYTE); + Delay_us(1000 * delay_ms); + } + + read_byte(); + *read_len = read_byte(); + + if (expected_read_len != *read_len) { + ow_reset(); + ds_dbg("DS28E16_standard_cmd_flow: len error!\n"); + return DS_FALSE; + } + + buf_len = *read_len + 2; + for (i = 0; i < buf_len; i++) + buf[i] = read_byte(); + + CRC16 = 0; + docrc16(*read_len); + for (i = 0; i < buf_len; i++) + docrc16(buf[i]); + + if (CRC16 != 0xB001) { + ow_reset(); + ds_dbg("DS28E16_standard_cmd_flow: crc2 error!\n"); + return DS_FALSE; + } + + memcpy(read_buf, buf, *read_len); + ds_dbg("DS28E16_standard_cmd_flow success!\n"); + return DS_TRUE; +} + +//-------------------------------------------------------------------------- +/// 'Read Status' command +/// +/// @param[out] data +/// pointer to unsigned char (buffer of length 1) for page protection data +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_readStatus(unsigned char *data) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int len_byte = 1; + int read_len = 7; + + ds_dbg("lvchen--data = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + data[0], data[1], data[2], data[3], data[4], data[5], data[6], + data[7]); + ds_dbg("lvchen--mi_status = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + mi_status[0], mi_status[1], mi_status[2], mi_status[3], + mi_status[4], mi_status[5], mi_status[6], mi_status[7]); + if (flag_mi_status) { + memcpy(data, mi_status, 8); + ds_log("lvchen---DS28E16_cmd_readStatus00\n"); + return DS_TRUE; + } + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Read Page Protection command + ?TX: Length (SMBus) [always 1] + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Protection Data + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_READ_STATUS; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_READ * tm, + read_buf, &read_len, write_len)) { + if (read_buf[0] == RESULT_SUCCESS) { + last_result_byte = read_buf[0]; + memcpy(data, &read_buf[1], 8); + flag_mi_status = 1; + memcpy(mi_status, data, 8); + MANID[0] = data[4]; + ds_dbg("lvchen--data = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + data[0], data[1], data[2], data[3], data[4], + data[5], data[6], data[7]); + ds_dbg("lvchen--mi_status = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + mi_status[0], mi_status[1], mi_status[2], + mi_status[3], mi_status[4], mi_status[5], + mi_status[6], mi_status[7]); + ds_log("lvchen---DS28E16_cmd_readStatus11\n"); + return DS_TRUE; + } + } + + ow_reset(); + ds_log("lvchen---DS28E16_cmd_readStatus22\n"); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Read Memory' command +/// +/// @param[in] pg +/// page number to read +/// @param[out] data +/// buffer length must be at least 32 bytes to hold memory read +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_readMemory(int pg, unsigned char *data) +{ + unsigned char write_buf[3]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 33; + int length_byte = 2; + unsigned char pagenum = (unsigned char)pg & 0x03; + + switch (pagenum) { + case 0x00: + if (flag_mi_page0_data) { + memcpy(data, mi_page0_data, 16); + return DS_TRUE; + } + break; + case 0x01: + if (flag_mi_page1_data) { + memcpy(data, mi_page1_data, 16); + return DS_TRUE; + } + break; + case 0x02: + if (flag_mi_counter) { + memcpy(data, mi_counter, 16); + return DS_TRUE; + } + break; + default: + return DS_FALSE; + } + + last_result_byte = RESULT_FAIL_NONE; + + /* + ? + ?TX: Read Memory Command + ?TX: Length (SMBus) + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) + ?RX: Result byte + ?RX: Data + ? + */ + + write_buf[write_len++] = length_byte; + write_buf[write_len++] = CMD_READ_MEM; + write_buf[write_len++] = pagenum; + + ds_dbg("DS28E16_cmd_readMemory write_buf:\n"); + ds_dbg("%02x %02x %02x", write_buf[0], write_buf[1], write_buf[2]); + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_READ * tm, + read_buf, &read_len, write_len)) { + if (read_len == 33) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + memcpy(data, &read_buf[1], 16); + if (pagenum == 0x00) { + flag_mi_page0_data = 1; + memcpy(mi_page0_data, data, 16); + } + if (pagenum == 0x01) { + flag_mi_page1_data = 1; + memcpy(mi_page1_data, data, 16); + } + return DS_TRUE; + } else { + if (read_buf[0] == 0x55 && pagenum == 2) { + memcpy(data, &read_buf[1], 16); + flag_mi_counter = 1; + memcpy(mi_counter, data, 16); + return DS_TRUE; + } + } + } + } + + ow_reset(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Write Memory' command +/// +/// @param[in] pg +/// page number to write +/// @param[in] data +/// buffer must be at least 32 bytes +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_writeMemory(int pg, unsigned char *data) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + int len_byte = 18; + unsigned char pagenum = (unsigned char)pg & 0x03; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Write Memory Command + ?TX: Length (SMBus) [always 33] + ?TX: Parameter + ?TX: Data + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_WRITE_MEM; + write_buf[write_len++] = pagenum; + memcpy(&write_buf[write_len], data, 16); + write_len += 16; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE * tm, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + if (pagenum == 0x00) { + flag_mi_page0_data = 0; + memset(mi_page0_data, 0x00, 16); + } + if (pagenum == 0x01) { + flag_mi_page1_data = 0; + memset(mi_page0_data, 0x00, 16); + } + if (pagenum == 0x02) { + flag_mi_counter = 0; + memset(mi_counter, 0x00, 16); + } + return DS_TRUE; + } + } + } + + ow_reset(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Decrement Counter' command +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_decrementCounter(void) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Decrement Counter Command + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = 1; + write_buf[write_len++] = CMD_DECREMENT_CNT; + + if (DS28E16_standard_cmd_flow(write_buf, 50, read_buf, &read_len, + write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Set Page Protection' command +/// +/// @param[in] pg +/// block to set protection +/// @param[in] prot +/// protection value to set +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_setPageProtection(int page, unsigned char prot) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + int len_byte = 3; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Set Page Protection Command + ?TX: Length (SMBus) [always 2] + ?TX: Parameter + ?TX: Protection Data + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_SET_PAGE_PROT; + write_buf[write_len++] = page & 0x03; + write_buf[write_len++] = prot & 0x03; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE * tm, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +int DS28E16_cmd_device_disable(int op, unsigned char *password) +{ + unsigned char write_buf[64]; + unsigned char read_buf[64]; + int write_len = 0; + int read_len = 1; + int length_byte = 10; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Length + ?TX: Device Disable Command + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) + ?RX: Result byte + ?RX: Data + ? + */ + + write_buf[write_len++] = length_byte; + write_buf[write_len++] = CMD_DISABLE_DEVICE; + write_buf[write_len++] = op & 0x0F; + memcpy(&write_buf[write_len], password, 8); + write_len += 8; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +// -------------------------------------------------------------------------- +/// 'Compute and Read Page Authentication' command +/// +/// @param[in] anon - boolean parameter +/// @param[in] pg - Page number 2,计数å™? 0,page0; 1,page1; +/// @param[in] challenge +/// @param[out] hmac 返回的计算结æž?2个字èŠ?/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_computeReadPageAuthentication(int anon, int pg, + unsigned char *challenge, + unsigned char *hmac) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 33; + int len_byte = 35; + + last_result_byte = RESULT_FAIL_NONE; + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_COMP_READ_AUTH; + write_buf[write_len] = pg & 0x03; + if (anon) + write_buf[write_len] = (write_buf[write_len] | 0xE0); + + write_len++; + write_buf[write_len++] = 0x02; // Fixed Parameter + memcpy(&write_buf[write_len], challenge, 32); // Challenge + write_len += 32; + + ds_dbg("computeReadPageAuthen:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + write_buf[0], write_buf[1], write_buf[2], write_buf[3], + write_buf[4], write_buf[5], write_buf[6], write_buf[7], + write_buf[8], write_buf[9], write_buf[10], write_buf[11], + write_buf[12], write_buf[13], write_buf[14], write_buf[15], + write_buf[16], write_buf[17], write_buf[18], write_buf[19], + write_buf[20], write_buf[21], write_buf[22], write_buf[23], + write_buf[24], write_buf[25], write_buf[26], write_buf[27], + write_buf[28], write_buf[29], write_buf[30], write_buf[31], + write_buf[32], write_buf[33], write_buf[34]); + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + ds_dbg("hmac read_buf:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + read_buf[0], read_buf[1], read_buf[2], + read_buf[3], read_buf[4], read_buf[5], + read_buf[6], read_buf[7], read_buf[8], + read_buf[9], read_buf[10], read_buf[11], + read_buf[12], read_buf[13], read_buf[14], + read_buf[15], read_buf[16], read_buf[17], + read_buf[18], read_buf[19], read_buf[20], + read_buf[21], read_buf[22], read_buf[23], + read_buf[24], read_buf[25], read_buf[26], + read_buf[27], read_buf[28], read_buf[29], + read_buf[30], read_buf[31], read_buf[32]); + memcpy(hmac, &read_buf[1], 32); + ds_dbg("hmac:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + hmac[0], hmac[1], hmac[2], hmac[3], hmac[4], + hmac[5], hmac[6], hmac[7], hmac[8], hmac[9], + hmac[10], hmac[11], hmac[12], hmac[13], hmac[14], + hmac[15], hmac[16], hmac[17], hmac[18], hmac[19], + hmac[20], hmac[21], hmac[22], hmac[23], hmac[24], + hmac[25], hmac[26], hmac[27], hmac[28], hmac[29], + hmac[30], hmac[31]); + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +// -------------------------------------------------------------------------- +/// 'Compute Secret S' command +/// +/// @param[in] anon - boolean parameter +/// @param[in] bdconst - boolean parameter +/// @param[in] pg - Page number é¡µé¢ +/// @param[in] partial secret 32个字节的ç§å­ +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_computeS_Secret(int anon, int bdconst, int pg, + unsigned char *partial) +{ + unsigned char write_buf[40]; + unsigned char read_buf[40]; + int write_len = 0; + int read_len = 1; + int len_byte = 35; + int param = pg & 0x03; + + last_result_byte = RESULT_FAIL_NONE; + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_COMP_S_SECRET; + + if (bdconst) + param = param | 0x04; + if (anon) + param = param | 0xE0; + + write_buf[write_len] = param; + write_len++; + write_buf[write_len++] = 0x08; // Fixed Parameter + memcpy(&write_buf[write_len], partial, 32); // Partial Secret + write_len += 32; + + ds_dbg("computeS_Secret:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + write_buf[0], write_buf[1], write_buf[2], write_buf[3], + write_buf[4], write_buf[5], write_buf[6], write_buf[7], + write_buf[8], write_buf[9], write_buf[10], write_buf[11], + write_buf[12], write_buf[13], write_buf[14], write_buf[15], + write_buf[16], write_buf[17], write_buf[18], write_buf[19], + write_buf[20], write_buf[21], write_buf[22], write_buf[23], + write_buf[24], write_buf[25], write_buf[26], write_buf[27], + write_buf[28], write_buf[29], write_buf[30], write_buf[31], + write_buf[32], write_buf[33], write_buf[34]); + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + + ow_reset(); + return DS_FALSE; +} + +int AuthenticateDS28E16(int anon, int bdconst, int S_Secret_PageNum, + int PageNum, unsigned char *Challenge, + unsigned char *Secret_Seeds, unsigned char *S_Secret) +{ + unsigned char PageData[32], MAC_Read_Value[32], CAL_MAC[32]; + unsigned char status_chip[16]; + unsigned char MAC_Computer_Datainput[128]; + int i = 0; + int msg_len = 0; + unsigned char flag = DS_FALSE; + + //if (flag_mi_auth_result) + if (mi_auth_result == DS_TRUE) + return mi_auth_result; + + if (anon != ANONYMOUS) { + if (ds28el16_get_page_status_retry(status_chip) == DS_TRUE) { + MANID[0] = status_chip[4]; + } else { + ow_reset(); + return ERROR_R_STATUS; + } + + if (ds28el16_Read_RomID_retry(mi_romid) != DS_TRUE) { + ow_reset(); + return ERROR_R_ROMID; + } + } + + // DS28E16 calculate its session secret + flag = DS28E16_cmd_computeS_Secret_retry( + anon, bdconst, S_Secret_PageNum, Secret_Seeds); + if (flag == DS_FALSE) { + ds_err("DS28E16_cmd_computeS_Secret error"); + ow_reset(); + return ERROR_S_SECRET; + } + + // DS28E16 compute its MAC based on above sessio secret + flag = DS28E16_cmd_computeReadPageAuthentication_retry( + anon, PageNum, Challenge, MAC_Read_Value); + if (flag == DS_FALSE) { + ds_err("DS28E16_cmd_computeReadPageAuthentication error"); + ow_reset(); + return ERROR_COMPUTE_MAC; + } + + ds_dbg("%02x %02x %02x %02x", anon, bdconst, S_Secret_PageNum, PageNum); + + ds_dbg("Seeds:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + Secret_Seeds[0], Secret_Seeds[1], Secret_Seeds[2], + Secret_Seeds[3], Secret_Seeds[4], Secret_Seeds[5], + Secret_Seeds[6], Secret_Seeds[7], Secret_Seeds[8], + Secret_Seeds[9], Secret_Seeds[10], Secret_Seeds[11], + Secret_Seeds[12], Secret_Seeds[13], Secret_Seeds[14], + Secret_Seeds[15], Secret_Seeds[16], Secret_Seeds[17], + Secret_Seeds[18], Secret_Seeds[19], Secret_Seeds[20], + Secret_Seeds[21], Secret_Seeds[22], Secret_Seeds[23], + Secret_Seeds[24], Secret_Seeds[25], Secret_Seeds[26], + Secret_Seeds[27], Secret_Seeds[28], Secret_Seeds[29], + Secret_Seeds[30], Secret_Seeds[31]); + + ds_dbg("S_Secret:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + S_Secret[0], S_Secret[1], S_Secret[2], S_Secret[3], S_Secret[4], + S_Secret[5], S_Secret[6], S_Secret[7], S_Secret[8], S_Secret[9], + S_Secret[10], S_Secret[11], S_Secret[12], S_Secret[13], + S_Secret[14], S_Secret[15], S_Secret[16], S_Secret[17], + S_Secret[18], S_Secret[19], S_Secret[20], S_Secret[21], + S_Secret[22], S_Secret[23], S_Secret[24], S_Secret[25], + S_Secret[26], S_Secret[27], S_Secret[28], S_Secret[29], + S_Secret[30], S_Secret[31]); + + ds_dbg("Challenge:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + Challenge[0], Challenge[1], Challenge[2], Challenge[3], + Challenge[4], Challenge[5], Challenge[6], Challenge[7], + Challenge[8], Challenge[9], Challenge[10], Challenge[11], + Challenge[12], Challenge[13], Challenge[14], Challenge[15], + Challenge[16], Challenge[17], Challenge[18], Challenge[19], + Challenge[20], Challenge[21], Challenge[22], Challenge[23], + Challenge[24], Challenge[25], Challenge[26], Challenge[27], + Challenge[28], Challenge[29], Challenge[30], Challenge[31]); + + ds_dbg("MAC_Read_Value:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + MAC_Read_Value[0], MAC_Read_Value[1], MAC_Read_Value[2], + MAC_Read_Value[3], MAC_Read_Value[4], MAC_Read_Value[5], + MAC_Read_Value[6], MAC_Read_Value[7], MAC_Read_Value[8], + MAC_Read_Value[9], MAC_Read_Value[10], MAC_Read_Value[11], + MAC_Read_Value[12], MAC_Read_Value[13], MAC_Read_Value[14], + MAC_Read_Value[15], MAC_Read_Value[16], MAC_Read_Value[17], + MAC_Read_Value[18], MAC_Read_Value[19], MAC_Read_Value[20], + MAC_Read_Value[21], MAC_Read_Value[22], MAC_Read_Value[23], + MAC_Read_Value[24], MAC_Read_Value[25], MAC_Read_Value[26], + MAC_Read_Value[27], MAC_Read_Value[28], MAC_Read_Value[29], + MAC_Read_Value[30], MAC_Read_Value[31]); + + // read the page data + flag = ds28el16_get_page_data_retry(PageNum, PageData); + if (flag != DS_TRUE) { + ds_err("DS28E16_cmd_readMemory error"); + ow_reset(); + return ERROR_R_PAGEDATA; + } + + // insert mi_romid + if (anon != ANONYMOUS) + memcpy(MAC_Computer_Datainput, mi_romid, 8); + else + memset(MAC_Computer_Datainput, 0xff, 8); + msg_len += 8; + + // insert Page Data + memcpy(&MAC_Computer_Datainput[msg_len], PageData, 16); + msg_len += 16; + memset(&MAC_Computer_Datainput[msg_len], 0x00, 16); + msg_len += 16; + + // insert Challenge + memcpy(&MAC_Computer_Datainput[msg_len], Challenge, 32); + msg_len += 32; + + // insert Bind Data Page number + MAC_Computer_Datainput[msg_len] = PageNum & 0x03; + MAC_Computer_Datainput[msg_len] = MAC_Computer_Datainput[msg_len] & + 0x03; + msg_len += 1; + + // insert MANID + memcpy(&MAC_Computer_Datainput[msg_len], MANID, 2); + msg_len += 2; + + // calculate the MAC + sha3_256_hmac(S_Secret, 32, MAC_Computer_Datainput, msg_len, CAL_MAC); + + ds_dbg("host data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + MAC_Computer_Datainput[0], MAC_Computer_Datainput[1], + MAC_Computer_Datainput[2], MAC_Computer_Datainput[3], + MAC_Computer_Datainput[4], MAC_Computer_Datainput[5], + MAC_Computer_Datainput[6], MAC_Computer_Datainput[7], + MAC_Computer_Datainput[8], MAC_Computer_Datainput[9], + MAC_Computer_Datainput[10], MAC_Computer_Datainput[11], + MAC_Computer_Datainput[12], MAC_Computer_Datainput[13], + MAC_Computer_Datainput[14], MAC_Computer_Datainput[15], + MAC_Computer_Datainput[16], MAC_Computer_Datainput[17], + MAC_Computer_Datainput[18], MAC_Computer_Datainput[19], + MAC_Computer_Datainput[20], MAC_Computer_Datainput[21], + MAC_Computer_Datainput[22], MAC_Computer_Datainput[23], + MAC_Computer_Datainput[24], MAC_Computer_Datainput[25], + MAC_Computer_Datainput[26], MAC_Computer_Datainput[27], + MAC_Computer_Datainput[28], MAC_Computer_Datainput[29], + MAC_Computer_Datainput[30], MAC_Computer_Datainput[31], + MAC_Computer_Datainput[32], MAC_Computer_Datainput[33], + MAC_Computer_Datainput[34], MAC_Computer_Datainput[35], + MAC_Computer_Datainput[36], MAC_Computer_Datainput[37], + MAC_Computer_Datainput[38], MAC_Computer_Datainput[39], + MAC_Computer_Datainput[40], MAC_Computer_Datainput[41], + MAC_Computer_Datainput[42], MAC_Computer_Datainput[43], + MAC_Computer_Datainput[44], MAC_Computer_Datainput[45], + MAC_Computer_Datainput[46], MAC_Computer_Datainput[47], + MAC_Computer_Datainput[48], MAC_Computer_Datainput[49], + MAC_Computer_Datainput[50], MAC_Computer_Datainput[51], + MAC_Computer_Datainput[52], MAC_Computer_Datainput[53], + MAC_Computer_Datainput[54], MAC_Computer_Datainput[55], + MAC_Computer_Datainput[56], MAC_Computer_Datainput[57], + MAC_Computer_Datainput[58], MAC_Computer_Datainput[59], + MAC_Computer_Datainput[60], MAC_Computer_Datainput[61], + MAC_Computer_Datainput[62], MAC_Computer_Datainput[63], + MAC_Computer_Datainput[64], MAC_Computer_Datainput[65], + MAC_Computer_Datainput[66], MAC_Computer_Datainput[67], + MAC_Computer_Datainput[68], MAC_Computer_Datainput[69], + MAC_Computer_Datainput[70], MAC_Computer_Datainput[71], + MAC_Computer_Datainput[72], MAC_Computer_Datainput[73], + MAC_Computer_Datainput[74], MAC_Computer_Datainput[75], + MAC_Computer_Datainput[76], MAC_Computer_Datainput[77], + MAC_Computer_Datainput[78], MAC_Computer_Datainput[79]); + + ds_dbg("host mac:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + CAL_MAC[0], CAL_MAC[1], CAL_MAC[2], CAL_MAC[3], CAL_MAC[4], + CAL_MAC[5], CAL_MAC[6], CAL_MAC[7], CAL_MAC[8], CAL_MAC[9], + CAL_MAC[10], CAL_MAC[11], CAL_MAC[12], CAL_MAC[13], CAL_MAC[14], + CAL_MAC[15], CAL_MAC[16], CAL_MAC[17], CAL_MAC[18], CAL_MAC[19], + CAL_MAC[20], CAL_MAC[21], CAL_MAC[22], CAL_MAC[23], CAL_MAC[24], + CAL_MAC[25], CAL_MAC[26], CAL_MAC[27], CAL_MAC[28], CAL_MAC[29], + CAL_MAC[30], CAL_MAC[31]); + + for (i = 0; i < 32; i++) { + if (CAL_MAC[i] != MAC_Read_Value[i]) + break; + } + + if (i != 32) { + flag_mi_auth_result = 1; + mi_auth_result = ERROR_UNMATCH_MAC; + // for debug + ds_dbg("hmac is not match. result=ERROR_UNMATCH_MAC\n"); + flag_mi_page1_data = 0; + return ERROR_UNMATCH_MAC; + } else { + flag_mi_auth_result = 1; + ds_dbg("hmac is match. result=DS_TRUE\n"); + mi_auth_result = DS_TRUE; + return DS_TRUE; + } +} + +// retry interface start // +static int ds28el16_Read_RomID_retry(unsigned char *RomID) +{ + int i; + unsigned char data[50]; + + for (i = 0; i < GET_ROM_ID_RETRY; i++) { + ds_info("read rom id communication start %d...\n", i); + if (DS28E16_cmd_readStatus(data) == DS_TRUE) { + if (Read_RomID(RomID) == DS_TRUE) + return DS_TRUE; + } + } + ds_log("ds28el16_Read_RomID_retry fail\n"); + return DS_FALSE; +} + +static int ds28el16_get_page_status_retry(unsigned char *data) +{ + int i; + + for (i = 0; i < GET_BLOCK_STATUS_RETRY; i++) { + ds_info("read page status communication start... %d\n", i); + + if (DS28E16_cmd_readStatus(data) == DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +/* +static int ds28el16_set_page_status_retry(unsigned char page, unsigned char status) +{ + int i; + + for (i = 0; i < SET_BLOCK_STATUS_RETRY; i++) { + ds_info("set page status communication start... %d\n", i); + + if (DS28E16_cmd_setPageProtection(page, status) == TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} +*/ + +static int ds28el16_get_page_data_retry(int page, unsigned char *data) +{ + int i; + + if (page >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_USER_MEMORY_RETRY; i++) { + ds_dbg("read page data communication start... %d\n", i); + + if (DS28E16_cmd_readMemory(page, data) == DS_TRUE) { + ds_dbg("page number is %d\n", page); + ds_dbg("page data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + data[0], data[1], data[2], data[3], data[4], + data[5], data[6], data[7], data[8], data[9], + data[10], data[11], data[12], data[13], data[14], + data[15]); + ds_dbg("flag_mi_page0_data is %d\n", + flag_mi_page0_data); + ds_dbg("mi_page0_data data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + mi_page0_data[0], mi_page0_data[1], + mi_page0_data[2], mi_page0_data[3], + mi_page0_data[4], mi_page0_data[5], + mi_page0_data[6], mi_page0_data[7], + mi_page0_data[8], mi_page0_data[9], + mi_page0_data[10], mi_page0_data[11], + mi_page0_data[12], mi_page0_data[13], + mi_page0_data[14], mi_page0_data[15]); + ds_dbg("flag_mi_page1_data is %d\n", + flag_mi_page1_data); + ds_dbg("mi_page1_data data:\n"); + ds_dbg("%%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + mi_page1_data[0], mi_page1_data[1], + mi_page1_data[2], mi_page1_data[3], + mi_page1_data[4], mi_page1_data[5], + mi_page1_data[6], mi_page1_data[7], + mi_page1_data[8], mi_page1_data[9], + mi_page1_data[10], mi_page1_data[11], + mi_page1_data[12], mi_page1_data[13], + mi_page1_data[14], mi_page1_data[15]); + ds_dbg("flag_mi_counter is %d\n", flag_mi_counter); + return DS_TRUE; + } + } + + return DS_FALSE; +} + +static int DS28E16_cmd_computeS_Secret_retry(int anon, int bdconst, int pg, + unsigned char *partial) +{ + int i; + + if (pg >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_S_SECRET_RETRY; i++) { + if (DS28E16_cmd_computeS_Secret(anon, bdconst, pg, partial) == + DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +static int DS28E16_cmd_computeReadPageAuthentication_retry( + int anon, int pg, unsigned char *challenge, unsigned char *hmac) +{ + int i; + + if (pg >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_MAC_RETRY; i++) { + if (DS28E16_cmd_computeReadPageAuthentication( + anon, pg, challenge, hmac) == DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +// retry interface end // + +/* All power supply functions here */ + +static enum power_supply_property verify_props[] = { + POWER_SUPPLY_PROP_ROMID, + POWER_SUPPLY_PROP_DS_STATUS, + POWER_SUPPLY_PROP_PAGENUMBER, + POWER_SUPPLY_PROP_PAGEDATA, + POWER_SUPPLY_PROP_AUTHEN_RESULT, + POWER_SUPPLY_PROP_SESSION_SEED, + POWER_SUPPLY_PROP_S_SECRET, + POWER_SUPPLY_PROP_CHALLENGE, + POWER_SUPPLY_PROP_AUTH_ANON, + POWER_SUPPLY_PROP_AUTH_BDCONST, + POWER_SUPPLY_PROP_PAGE0_DATA, + POWER_SUPPLY_PROP_PAGE1_DATA, + POWER_SUPPLY_PROP_VERIFY_MODEL_NAME, + POWER_SUPPLY_PROP_CHIP_OK, +}; + +static int verify_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + int ret; + unsigned char buf[50]; + + switch (psp) { + case POWER_SUPPLY_PROP_VERIFY_MODEL_NAME: + ret = ds28el16_Read_RomID_retry(mi_romid); + if (ret == DS_TRUE) + val->strval = "ds28e16"; + else + val->strval = "unknown"; + break; + case POWER_SUPPLY_PROP_AUTHEN_RESULT: + ret = AuthenticateDS28E16(auth_ANON, auth_BDCONST, 0, + pagenumber, challenge, session_seed, + S_secret); + if (ret == DS_TRUE) + val->intval = true; + else + val->intval = false; + break; + case POWER_SUPPLY_PROP_PAGENUMBER: + val->intval = pagenumber; + break; + case POWER_SUPPLY_PROP_ROMID: + ret = ds28el16_Read_RomID_retry(mi_romid); + memcpy(val->arrayval, mi_romid, 8); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_CHIP_OK: + ds_log("lvchen---POWER_SUPPLY_PROP_CHIP_OK\n"); + ret = ds28el16_Read_RomID_retry(mi_romid); + if ((mi_romid[0] == FAMILY_CODE) && + (mi_romid[6] == CUSTOM_ID_MSB) && + ((mi_romid[5] & 0xf0) == CUSTOM_ID_LSB)) + val->intval = true; + else + val->intval = false; + ds_log("lvchen---flag_mi_romid: %d, flag_mi_status: %d\n", + flag_mi_romid, flag_mi_status); + break; + case POWER_SUPPLY_PROP_DS_STATUS: + ret = ds28el16_get_page_status_retry(buf); + memcpy(val->arrayval, buf, 8); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGEDATA: + ret = ds28el16_get_page_data_retry(pagenumber, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGE0_DATA: + ret = ds28el16_get_page_data_retry(0, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGE1_DATA: + ret = ds28el16_get_page_data_retry(1, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + default: + ds_err("unsupported property %d\n", psp); + return -ENODATA; + } + + return 0; +} + +static int verify_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + //int ret; + //unsigned char buf[50]; + + switch (prop) { + case POWER_SUPPLY_PROP_PAGENUMBER: + pagenumber = val->intval; + break; + /* + case POWER_SUPPLY_PROP_PAGEDATA: + memcpy(buf, val->arrayval, 16); + ret = DS28E16_cmd_writeMemory(pagenumber, buf); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_SESSION_SEED: + memcpy(session_seed, val->arrayval, 32); + break; + case POWER_SUPPLY_PROP_S_SECRET: + memcpy(S_secret, val->arrayval, 32); + break; + case POWER_SUPPLY_PROP_CHALLENGE: + memcpy(challenge, val->arrayval, 32); + break; +*/ + case POWER_SUPPLY_PROP_AUTH_ANON: + auth_ANON = val->intval; + break; + case POWER_SUPPLY_PROP_AUTH_BDCONST: + auth_BDCONST = val->intval; + break; + default: + ds_err("unsupported property %d\n", prop); + return -ENODATA; + } + + return 0; +} + +static int verify_prop_is_writeable(struct power_supply *psy, + enum power_supply_property prop) +{ + int ret; + + switch (prop) { + case POWER_SUPPLY_PROP_PAGENUMBER: + case POWER_SUPPLY_PROP_PAGEDATA: + case POWER_SUPPLY_PROP_SESSION_SEED: + case POWER_SUPPLY_PROP_S_SECRET: + case POWER_SUPPLY_PROP_CHALLENGE: + case POWER_SUPPLY_PROP_AUTH_ANON: + case POWER_SUPPLY_PROP_AUTH_BDCONST: + ret = 1; + break; + default: + ret = 0; + break; + } + return ret; +} + +static int verify_psy_register(struct ds28e16_data *ds) +{ + struct power_supply_config verify_psy_cfg = {}; + + ds->verify_psy_d.name = "batt_verify"; + ds->verify_psy_d.type = POWER_SUPPLY_TYPE_BATT_VERIFY; + ds->verify_psy_d.properties = verify_props; + ds->verify_psy_d.num_properties = ARRAY_SIZE(verify_props); + ds->verify_psy_d.get_property = verify_get_property; + ds->verify_psy_d.set_property = verify_set_property; + ds->verify_psy_d.property_is_writeable = verify_prop_is_writeable; + + verify_psy_cfg.drv_data = ds; + verify_psy_cfg.of_node = ds->dev->of_node; + verify_psy_cfg.num_supplicants = 0; + ds->verify_psy = devm_power_supply_register(ds->dev, &ds->verify_psy_d, + &verify_psy_cfg); + if (IS_ERR(ds->verify_psy)) { + ds_err("Failed to register verify_psy"); + return PTR_ERR(ds->verify_psy); + } + + ds_log("%s power supply register successfully\n", + ds->verify_psy_d.name); + return 0; +} + +static void verify_psy_unregister(struct ds28e16_data *ds) +{ + power_supply_unregister(ds->verify_psy); +} + +// parse dts +static int ds28e16_parse_dt(struct device *dev, struct ds28e16_data *pdata) +{ + int error, val; + struct device_node *np = dev->of_node; + + // parse version + pdata->version = 0; + error = of_property_read_u32(np, "maxim,version", &val); + if (error && (error != -EINVAL)) + ds_err("Unable to read bootloader address\n"); + else if (error != -EINVAL) + pdata->version = val; + + return 0; +} + +// read data from file +static ssize_t ds28e16_ds_Auth_Result_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + + result = AuthenticateDS28E16(auth_ANON, auth_BDCONST, 0, pagenumber, + challenge, session_seed, S_secret); + if (result == ERROR_R_STATUS) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_R_STATUS!\n"); + else if (result == ERROR_UNMATCH_MAC) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : MAC is not match!\n"); + else if (result == ERROR_R_ROMID) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_R_ROMID!\n"); + else if (result == ERROR_COMPUTE_MAC) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_COMPUTE_MAC!\n"); + else if (result == ERROR_S_SECRET) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_S_SECRET!\n"); + else if (result == DS_TRUE) + return scnprintf(buf, PAGE_SIZE, "Authenticate success!!!\n"); + else + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : other reason.\n"); +} + +static ssize_t ds28e16_ds_romid_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + short status; + unsigned char RomID[10] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes; i++) { + status = ds28el16_Read_RomID_retry(RomID); + + if (status == DS_TRUE) { + count++; + ds_log("Read_RomID success!\n"); + } else { + ds_log("Read_RomID fail!\n"); + } + ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + RomID[0], RomID[1], RomID[2], RomID[3], RomID[4], + RomID[5], RomID[6], RomID[7]); + Delay_us(1000); + } + + /*ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + RomID[0], RomID[1], RomID[2], RomID[3], + RomID[4], RomID[5], RomID[6], RomID[7]); + */ + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\nRomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, RomID[0], RomID[1], RomID[2], RomID[3], RomID[4], + RomID[5], RomID[6], RomID[7]); +} + +static ssize_t ds28e16_ds_pagenumber_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", pagenumber); +} + +static ssize_t ds28e16_ds_pagenumber_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int buf_int; + + if (sscanf(buf, "%d", &buf_int) != 1) + return -EINVAL; + + ds_dbg("new pagenumber = %d\n", buf_int); + + if ((buf_int >= 0) && (buf_int <= 3)) + pagenumber = buf_int; + + return count; +} + +static ssize_t ds28e16_ds_pagedata_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + unsigned char pagedata[16] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes; i++) { + result = ds28el16_get_page_data_retry(pagenumber, pagedata); + + if (result == DS_TRUE) { + count++; + ds_log("DS28E16_cmd_readMemory success!\n"); + } else { + ds_log("DS28E16_cmd_readMemory fail!\n"); + } + ds_dbg("pagedata = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + pagedata[0], pagedata[1], pagedata[2], pagedata[3], + pagedata[4], pagedata[5], pagedata[6], pagedata[7], + pagedata[8], pagedata[9], pagedata[10], pagedata[11], + pagedata[12], pagedata[13], pagedata[14], pagedata[15]); + Delay_us(1000); + } + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\npagedata = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, pagedata[0], pagedata[1], pagedata[2], pagedata[3], + pagedata[4], pagedata[5], pagedata[6], pagedata[7], pagedata[8], + pagedata[9], pagedata[10], pagedata[11], pagedata[12], + pagedata[13], pagedata[14], pagedata[15]); +} + +static ssize_t ds28e16_ds_pagedata_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int result; + unsigned char pagedata[16] = { 0x00 }; + + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &pagedata[0], &pagedata[1], &pagedata[2], &pagedata[3], + &pagedata[4], &pagedata[5], &pagedata[6], &pagedata[7], + &pagedata[8], &pagedata[9], &pagedata[10], &pagedata[11], + &pagedata[12], &pagedata[13], &pagedata[14], + &pagedata[15]) != 16) + return -EINVAL; + + ds_dbg("new data = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + pagedata[0], pagedata[1], pagedata[2], pagedata[3], pagedata[4], + pagedata[5], pagedata[6], pagedata[7], pagedata[8], pagedata[9], + pagedata[10], pagedata[11], pagedata[12], pagedata[13], + pagedata[14], pagedata[15]); + + result = DS28E16_cmd_writeMemory(pagenumber, pagedata); + if (result == DS_TRUE) + ds_log("DS28E16_cmd_writeMemory success!\n"); + else + ds_log("DS28E16_cmd_writeMemory fail!\n"); + + return count; +} + +static ssize_t ds28e16_ds_time_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%d\n", attr_trytimes); +} + +static ssize_t ds28e16_ds_time_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int buf_int; + + if (sscanf(buf, "%d", &buf_int) != 1) + return -EINVAL; + + ds_log("new trytimes = %d\n", buf_int); + + if (buf_int > 0) + attr_trytimes = buf_int; + + return count; +} + +static ssize_t +ds28e16_ds_session_seed_status_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + session_seed[0], session_seed[1], session_seed[2], + session_seed[3], session_seed[4], session_seed[5], + session_seed[6], session_seed[7], session_seed[8], + session_seed[9], session_seed[10], session_seed[11], + session_seed[12], session_seed[13], session_seed[14], + session_seed[15], session_seed[16], session_seed[17], + session_seed[18], session_seed[19], session_seed[20], + session_seed[21], session_seed[22], session_seed[23], + session_seed[24], session_seed[25], session_seed[26], + session_seed[27], session_seed[28], session_seed[29], + session_seed[30], session_seed[31]); +} + +static ssize_t ds28e16_ds_session_seed_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &session_seed[0], &session_seed[1], &session_seed[2], + &session_seed[3], &session_seed[4], &session_seed[5], + &session_seed[6], &session_seed[7], &session_seed[8], + &session_seed[9], &session_seed[10], &session_seed[11], + &session_seed[12], &session_seed[13], &session_seed[14], + &session_seed[15], &session_seed[16], &session_seed[17], + &session_seed[18], &session_seed[19], &session_seed[20], + &session_seed[21], &session_seed[22], &session_seed[23], + &session_seed[24], &session_seed[25], &session_seed[26], + &session_seed[27], &session_seed[28], &session_seed[29], + &session_seed[30], &session_seed[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_challenge_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + challenge[0], challenge[1], challenge[2], challenge[3], + challenge[4], challenge[5], challenge[6], challenge[7], + challenge[8], challenge[9], challenge[10], challenge[11], + challenge[12], challenge[13], challenge[14], challenge[15], + challenge[16], challenge[17], challenge[18], challenge[19], + challenge[20], challenge[21], challenge[22], challenge[23], + challenge[24], challenge[25], challenge[26], challenge[27], + challenge[28], challenge[29], challenge[30], challenge[31]); +} + +static ssize_t ds28e16_ds_challenge_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &challenge[0], &challenge[1], &challenge[2], &challenge[3], + &challenge[4], &challenge[5], &challenge[6], &challenge[7], + &challenge[8], &challenge[9], &challenge[10], &challenge[11], + &challenge[12], &challenge[13], &challenge[14], + &challenge[15], &challenge[16], &challenge[17], + &challenge[18], &challenge[19], &challenge[20], + &challenge[21], &challenge[22], &challenge[23], + &challenge[24], &challenge[25], &challenge[26], + &challenge[27], &challenge[28], &challenge[29], + &challenge[30], &challenge[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_S_secret_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + S_secret[0], S_secret[1], S_secret[2], S_secret[3], S_secret[4], + S_secret[5], S_secret[6], S_secret[7], S_secret[8], S_secret[9], + S_secret[10], S_secret[11], S_secret[12], S_secret[13], + S_secret[14], S_secret[15], S_secret[16], S_secret[17], + S_secret[18], S_secret[19], S_secret[20], S_secret[21], + S_secret[22], S_secret[23], S_secret[24], S_secret[25], + S_secret[26], S_secret[27], S_secret[28], S_secret[29], + S_secret[30], S_secret[31]); +} + +static ssize_t ds28e16_ds_S_secret_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &S_secret[0], &S_secret[1], &S_secret[2], &S_secret[3], + &S_secret[4], &S_secret[5], &S_secret[6], &S_secret[7], + &S_secret[8], &S_secret[9], &S_secret[10], &S_secret[11], + &S_secret[12], &S_secret[13], &S_secret[14], &S_secret[15], + &S_secret[16], &S_secret[17], &S_secret[18], &S_secret[19], + &S_secret[20], &S_secret[21], &S_secret[22], &S_secret[23], + &S_secret[24], &S_secret[25], &S_secret[26], &S_secret[27], + &S_secret[28], &S_secret[29], &S_secret[30], + &S_secret[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_auth_ANON_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", auth_ANON); +} + +static ssize_t ds28e16_ds_auth_ANON_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, "%d", &auth_ANON) != 1) + return -EINVAL; + + return count; +} + +static ssize_t +ds28e16_ds_auth_BDCONST_status_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", auth_BDCONST); +} + +static ssize_t ds28e16_ds_auth_BDCONST_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, "%d", &auth_BDCONST) != 1) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_readstatus_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + unsigned char status[16] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes; i++) { + result = ds28el16_get_page_status_retry(status); + + if (result == DS_TRUE) { + count++; + ds_log("DS28E16_cmd_readStatus success!\n"); + } else { + ds_log("DS28E16_cmd_readStatus fail!\n"); + } + ds_dbg("Status = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + status[0], status[1], status[2], status[3], status[4], + status[5], status[6], status[7], status[8], status[9], + status[10], status[11], status[12], status[13], + status[14], status[15]); + Delay_us(1000); + } + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\nStatus = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, status[0], status[1], status[2], status[3], status[4], + status[5], status[6], status[7], status[8], status[9], + status[10], status[11], status[12], status[13], status[14], + status[15]); +} + +static DEVICE_ATTR(ds_readstatus, S_IRUGO, ds28e16_ds_readstatus_status_read, + NULL); +static DEVICE_ATTR(ds_romid, S_IRUGO, ds28e16_ds_romid_status_read, NULL); +static DEVICE_ATTR(ds_pagenumber, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_pagenumber_status_read, + ds28e16_ds_pagenumber_store); +static DEVICE_ATTR(ds_pagedata, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_pagedata_status_read, ds28e16_ds_pagedata_store); +static DEVICE_ATTR(ds_time, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_time_status_read, ds28e16_ds_time_store); +static DEVICE_ATTR(ds_session_seed, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_session_seed_status_read, + ds28e16_ds_session_seed_store); +static DEVICE_ATTR(ds_challenge, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_challenge_status_read, + ds28e16_ds_challenge_store); +static DEVICE_ATTR(ds_S_secret, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_S_secret_status_read, ds28e16_ds_S_secret_store); +static DEVICE_ATTR(ds_auth_ANON, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_auth_ANON_status_read, + ds28e16_ds_auth_ANON_store); +static DEVICE_ATTR(ds_auth_BDCONST, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_auth_BDCONST_status_read, + ds28e16_ds_auth_BDCONST_store); +static DEVICE_ATTR(ds_Auth_Result, S_IRUGO, ds28e16_ds_Auth_Result_status_read, + NULL); + +static struct attribute *ds_attributes[] = { + &dev_attr_ds_readstatus.attr, &dev_attr_ds_romid.attr, + &dev_attr_ds_pagenumber.attr, &dev_attr_ds_pagedata.attr, + &dev_attr_ds_time.attr, &dev_attr_ds_session_seed.attr, + &dev_attr_ds_challenge.attr, &dev_attr_ds_S_secret.attr, + &dev_attr_ds_auth_ANON.attr, &dev_attr_ds_auth_BDCONST.attr, + &dev_attr_ds_Auth_Result.attr, NULL, +}; + +static const struct attribute_group ds_attr_group = { + .attrs = ds_attributes, +}; + +static int authentic_period_ms = 5000; +#define AUTHENTIC_COUNT_MAX 5 +int retry_authentic; +static void authentic_work(struct work_struct *work) +{ + int rc; + union power_supply_propval pval = { + 0, + }; + + struct ds28e16_data *ds28e16_data = + container_of(work, struct ds28e16_data, authentic_work.work); + + rc = power_supply_get_property(ds28e16_data->verify_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, &pval); + if (pval.intval != true) { + retry_authentic++; + if (retry_authentic < AUTHENTIC_COUNT_MAX) { + ds_log("battery authentic work begin to restart, retry = %d\n", + retry_authentic); + schedule_delayed_work( + &ds28e16_data->authentic_work, + msecs_to_jiffies(authentic_period_ms)); + } + + if (retry_authentic == AUTHENTIC_COUNT_MAX) { + ds_log("authentic result is %d\n", pval.intval); + } + } else { + ds_log("authentic result is %d\n", pval.intval); + } +} + +static int ds28e16_probe(struct platform_device *pdev) +{ + int retval = 0; + struct ds28e16_data *ds28e16_data; + union power_supply_propval b_val = { + 0, + }; + + ds_log("%s entry.", __func__); + ds_dbg("platform_device is %s", pdev->name); + if (strcmp(pdev->name, "soc:maxim_ds28e16") != 0) + return -ENODEV; + + if (!pdev->dev.of_node || !of_device_is_available(pdev->dev.of_node)) + return -ENODEV; + + if (pdev->dev.of_node) { + ds28e16_data = devm_kzalloc( + &pdev->dev, sizeof(struct ds28e16_data), GFP_KERNEL); + if (!ds28e16_data) { + ds_err("Failed to allocate memory\n"); + return -ENOMEM; + } + + retval = ds28e16_parse_dt(&pdev->dev, ds28e16_data); + if (retval) { + retval = -EINVAL; + goto ds28e16_parse_dt_err; + } + } else { + ds28e16_data = pdev->dev.platform_data; + } + + if (!ds28e16_data) { + ds_err("No platform data found\n"); + return -EINVAL; + } + + ds28e16_data->dev = &pdev->dev; + ds28e16_data->pdev = pdev; + platform_set_drvdata(pdev, ds28e16_data); + INIT_DELAYED_WORK(&ds28e16_data->authentic_work, authentic_work); + + retval = verify_psy_register(ds28e16_data); + if (retval) { + ds_err("Failed to verify_psy_register, err:%d\n", retval); + goto ds28e16_psy_register_err; + } + + retval = sysfs_create_group(&ds28e16_data->dev->kobj, &ds_attr_group); + if (retval) { + ds_err("Failed to register sysfs, err:%d\n", retval); + goto ds28e16_create_group_err; + } + + retval = power_supply_get_property(ds28e16_data->verify_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, + &b_val); + if (b_val.intval != true) { + schedule_delayed_work(&ds28e16_data->authentic_work, + msecs_to_jiffies(0)); + } + return 0; + +ds28e16_create_group_err: +//sysfs_remove_groups(&ds28e16_data->dev->kobj, &(&ds_attr_group)); +ds28e16_psy_register_err: + dev_set_drvdata(ds28e16_data->dev, NULL); +ds28e16_parse_dt_err: + kfree(ds28e16_data); + return retval; +} + +static int ds28e16_remove(struct platform_device *pdev) +{ + struct ds28e16_data *ds28e16_data = platform_get_drvdata(pdev); + + verify_psy_unregister(ds28e16_data); + kfree(ds28e16_data); + return 0; +} + +static long ds28e16_dev_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + ds_log("%d, cmd: 0x%x\n", __LINE__, cmd); + return 0; +} +static int ds28e16_dev_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int ds28e16_dev_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations ds28e16_dev_fops = { + .owner = THIS_MODULE, + .open = ds28e16_dev_open, + .unlocked_ioctl = ds28e16_dev_ioctl, + .release = ds28e16_dev_release, +}; + +static const struct of_device_id ds28e16_dt_match[] = { + { .compatible = "maxim,ds28e16" }, + {}, +}; + +static struct platform_driver ds28e16_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "maxim_ds28e16", + .of_match_table = ds28e16_dt_match, + }, + .probe = ds28e16_probe, + .remove = ds28e16_remove, +}; + +static int __init ds28e16_init(void) +{ + ds_log("%s entry.", __func__); + + return platform_driver_register(&ds28e16_driver); +} + +static void __exit ds28e16_exit(void) +{ + ds_log("%s entry.", __func__); + platform_driver_unregister(&ds28e16_driver); +} + +module_init(ds28e16_init); +module_exit(ds28e16_exit); + +MODULE_AUTHOR("xiaomi Inc."); +MODULE_DESCRIPTION("ds28e16 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/maxim/ds28e16.h b/drivers/power/supply/maxim/ds28e16.h new file mode 100644 index 000000000000..a812b4675969 --- /dev/null +++ b/drivers/power/supply/maxim/ds28e16.h @@ -0,0 +1,133 @@ +// DS28E16.h - Include file for DS28E16/DS28E50? +// +#ifndef __DS28E16_H__ +#define __DS28E16_H__ + +#define ERROR_NO_DEVICE -1 +#define ERROR_R_STATUS -2 +#define ERROR_R_ROMID -3 +#define ERROR_R_PAGEDATA -4 +#define ERROR_COMPUTE_MAC -5 +#define ERROR_S_SECRET -6 +#define ERROR_UNMATCH_MAC -7 +#define DS_TRUE 1 +#define DS_FALSE 0 + +#define CMD_RELEASE_BYTE 0xAA +// 1-wire ROM commands +#define CMD_SEARCH_ROM 0xF0 +#define CMD_READ_ROM 0x33 +#define CMD_MATCH_ROM 0x55 +#define CMD_SKIP_ROM 0xCC +#define CMD_RESUME_ROM 0xA5 + +// DS28E16 commands +#define CMD_START 0x66 +#define CMD_WRITE_MEM 0x96 +#define CMD_READ_MEM 0x44 +#define CMD_READ_STATUS 0xAA +#define CMD_SET_PAGE_PROT 0xC3 +#define CMD_COMP_READ_AUTH 0xA5 +#define CMD_COMP_S_SECRET 0x3C +#define CMD_DECREMENT_CNT 0xC9 +#define CMD_DISABLE_DEVICE 0x33 + +#define CMD_READ_RNG 0xD2 + +// Result bytes +#define RESULT_SUCCESS 0xAA +#define RESULT_FAIL_PROTECTION 0x55 +#define RESULT_FAIL_PARAMETETER 0x77 +#define RESULT_FAIL_DEVICEDISABLED 0x88 +#define RESULT_FAIL_COUNTERINVALID 0x22 +#define RESULT_FAIL_COUNTERNOSET 0x33 +#define RESULT_FAIL_SEQUENCEWRONG 0x00 +#define RESULT_FAIL_NONE 0xFF + +// Delays +#define DELAY_DS28E16_EE_WRITE 100 +#define DELAY_DS28E16_EE_READ 50 +#define DELAY_DS28E16_RNG_READ 40 +#define DELAY_DS28E16_ENC_READ 40 + +// DS28E16 +#define PROT_RP 0x01 +#define PROT_WP 0x02 +#define PROT_WP_RP 0x03 +#define PROT_DC 0x08 + +// page number +#define PAGE0 0x00 +#define PAGE1 0x01 +#define DC_PAGE 0x02 +#define SECRET_PAGE 0x03 +#define MAX_PAGENUM 0x04 + +#define ANONYMOUS 1 + +//retry times config +#define SET_SRAM_RETRY 4 +#define GET_USER_MEMORY_RETRY 8 +#define GET_PERSONALITY_RETRY 8 +#define GET_ROM_ID_RETRY 8 +#define GET_BLOCK_STATUS_RETRY 8 +#define SET_BLOCK_STATUS_RETRY 8 +#define GET_MAC_RETRY 8 +#define GET_VERIFY_RETRY 8 +#define GET_S_SECRET_RETRY 4 + +// xiaomi's battery identity +#define FAMILY_CODE 0x9f +#define CUSTOM_ID_MSB 0x04 +#define CUSTOM_ID_LSB 0xF0 + +extern unsigned char last_result_byte; + +// Command functions +// 1-Wire ROMID commands +unsigned char crc_low_first(unsigned char *ptr, unsigned char len); +short Read_RomID(unsigned char *RomID); + +// Common Functions +unsigned short docrc16(unsigned short data); +int DS28E16_standard_cmd_flow(unsigned char *write_buf, int delay_ms, + unsigned char *read_buf, int *read_len, + int write_len); + +// Command Functions (no high level verification) +int DS28E16_cmd_readStatus( + unsigned char * + data); // 读入芯片的页é¢ä¿æŠ¤å±žæ€§ã€ä¸€ä¸ªMAN_ID字节和一个芯片版本字节，åˆè®¡6个字节 +int DS28E16_cmd_readMemory( + int pg, + unsigned char * + data); // pg=0,1,2页é¢ï¼Œä¸€æ¬¡è¯»å…¥32个字节，å‰16个字节为有效数æ®ï¼ŒåŽç»­16个字节固定为0x00或0xFF +int DS28E16_cmd_writeMemory( + int pg, unsigned char *data); // pg=0,1,2页é¢ï¼Œä¸€æ¬¡å¿…须完整写入16个字节 +int DS28E16_cmd_decrementCounter(void); // 执行此函数，完æˆ17ä½è®¡æ•°å™¨å‡1æ“作 +int DS28E16_cmd_setPageProtection(int pg, + unsigned char prot); // 设置芯片的页é¢å±žæ€§ +int DS28E16_cmd_device_disable(int op, + unsigned char *password); // 芯片自æ¯ï¼Œä¸èƒ½æ¢å¤ +int DS28E16_cmd_computeReadPageAuthentication( + int anon, int pg, unsigned char *challenge, + unsigned char * + hmac); // 器件基于会è¯å¯†ç ã€éšæœºæ•°ã€é¡µé¢æ•°æ®å’ŒROMID，返回器件的算法结果 +int DS28E16_cmd_computeS_Secret( + int anon, int bdconst, int pg, + unsigned char + *partial); // 基于主机å‘é€çš„密钥ç§å­ï¼Œå™¨ä»¶åœ¨å†…部计算出会è¯å¯†ç  + +// host functions +int AuthenticateDS28E16(int anon, int bdconst, int S_Secret_PageNum, + int PageNum, unsigned char *Challenge, + unsigned char *Secret_Seeds, unsigned char *S_Secret); + +static int ds28el16_Read_RomID_retry(unsigned char *RomID); +static int ds28el16_get_page_status_retry(unsigned char *data); +static int DS28E16_cmd_computeS_Secret_retry(int anon, int bdconst, int pg, + unsigned char *session_seed); +static int DS28E16_cmd_computeReadPageAuthentication_retry( + int anon, int pg, unsigned char *challenge, unsigned char *hmac); +static int ds28el16_get_page_data_retry(int page, unsigned char *data); +#endif diff --git a/drivers/power/supply/maxim/ds28e16_common.h b/drivers/power/supply/maxim/ds28e16_common.h new file mode 100644 index 000000000000..564f05bd0434 --- /dev/null +++ b/drivers/power/supply/maxim/ds28e16_common.h @@ -0,0 +1,84 @@ +// DS28E16.h - Include file for DS28E16/DS28E50? +// +#ifndef __DS28E16_COMMON_H__ +#define __DS28E16_COMMON_H__ + +#define ERROR_NO_DEVICE -1 +#define ERROR_R_STATUS -2 +#define ERROR_R_ROMID -3 +#define ERROR_R_PAGEDATA -4 +#define ERROR_COMPUTE_MAC -5 +#define ERROR_S_SECRET -6 +#define ERROR_UNMATCH_MAC -7 +#define DS_TRUE 1 +#define DS_FALSE 0 + +#define CMD_RELEASE_BYTE 0xAA +// 1-wire ROM commands +#define CMD_SEARCH_ROM 0xF0 +#define CMD_READ_ROM 0x33 +#define CMD_MATCH_ROM 0x55 +#define CMD_SKIP_ROM 0xCC +#define CMD_RESUME_ROM 0xA5 + +// DS28E16 commands +#define CMD_START 0x66 +#define CMD_WRITE_MEM 0x96 +#define CMD_READ_MEM 0x44 +#define CMD_READ_STATUS 0xAA +#define CMD_SET_PAGE_PROT 0xC3 +#define CMD_COMP_READ_AUTH 0xA5 +#define CMD_COMP_S_SECRET 0x3C +#define CMD_DECREMENT_CNT 0xC9 +#define CMD_DISABLE_DEVICE 0x33 + +#define CMD_READ_RNG 0xD2 + +// Result bytes +#define RESULT_SUCCESS 0xAA +#define RESULT_FAIL_PROTECTION 0x55 +#define RESULT_FAIL_PARAMETETER 0x77 +#define RESULT_FAIL_DEVICEDISABLED 0x88 +#define RESULT_FAIL_COUNTERINVALID 0x22 +#define RESULT_FAIL_COUNTERNOSET 0x33 +#define RESULT_FAIL_SEQUENCEWRONG 0x00 +#define RESULT_FAIL_NONE 0xFF + +// Delays +#define DELAY_DS28E16_EE_WRITE 100 +#define DELAY_DS28E16_EE_READ 50 +#define DELAY_DS28E16_RNG_READ 40 +#define DELAY_DS28E16_ENC_READ 40 + +// DS28E16 +#define PROT_RP 0x01 +#define PROT_WP 0x02 +#define PROT_WP_RP 0x03 +#define PROT_DC 0x08 + +// page number +#define PAGE0 0x00 +#define PAGE1 0x01 +#define DC_PAGE 0x02 +#define SECRET_PAGE 0x03 +#define MAX_PAGENUM 0x04 + +#define ANONYMOUS 1 + +//retry times config +#define SET_SRAM_RETRY 4 +#define GET_USER_MEMORY_RETRY 8 +#define GET_PERSONALITY_RETRY 8 +#define GET_ROM_ID_RETRY 8 +#define GET_BLOCK_STATUS_RETRY 8 +#define SET_BLOCK_STATUS_RETRY 8 +#define GET_MAC_RETRY 8 +#define GET_VERIFY_RETRY 8 +#define GET_S_SECRET_RETRY 4 + +// xiaomi's battery identity +#define FAMILY_CODE 0x9f +#define CUSTOM_ID_MSB 0x04 +#define CUSTOM_ID_LSB 0xF0 + +#endif diff --git a/drivers/power/supply/maxim/ds28e16_master.c b/drivers/power/supply/maxim/ds28e16_master.c new file mode 100644 index 000000000000..b5a526eaa166 --- /dev/null +++ b/drivers/power/supply/maxim/ds28e16_master.c @@ -0,0 +1,1915 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + ******************************************************************************* + * + * DS28E16.c - DS28E16 device module. Requires low level 1-Wire connection. + */ +#define pr_fmt(fmt) "[ds28e16] %s: " fmt, __func__ + +#include /* kfree() */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sha384_software.h" +#include "ds28e16_master.h" +#include "onewire_gpio_master.h" +#include "ds28e16_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ds_info pr_err +#define ds_dbg pr_err +#define ds_err pr_err +#define ds_log pr_err + +struct ds28e16_data { + struct platform_device *pdev; + struct device *dev; + + int version; + + struct power_supply *verify_psy; + struct power_supply_desc verify_psy_d; + + struct delayed_work authentic_work; +}; + +unsigned int attr_trytimes = 1; + +unsigned char session_seed[32] = { 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA }; +unsigned char S_secret[32] = { 0x0C, 0x99, 0x2B, 0xD3, 0x95, 0xDB, 0xA0, 0xB4, + 0xEF, 0x07, 0xB3, 0xD8, 0x75, 0xF3, 0xC7, 0xAE, + 0xDA, 0xC4, 0x41, 0x2F, 0x48, 0x93, 0xB5, 0xD9, + 0xE1, 0xE5, 0x4B, 0x20, 0x9B, 0xF3, 0x77, 0x39 }; +unsigned char challenge[32] = { 0x00 }; +int auth_ANON = 1; +int auth_BDCONST = 1; +int pagenumber = 1; + +// maxim define +int tm = 1; +unsigned short CRC16; +const short oddparity[16] = { 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 }; +unsigned char last_result_byte = RESULT_SUCCESS; + +unsigned char MANID[2] = { 0x00 }; + +// mi add +unsigned char flag_mi_romid = 0; +unsigned char flag_mi_status = 0; +unsigned char flag_mi_page0_data = 0; +unsigned char flag_mi_page1_data = 0; +unsigned char flag_mi_counter = 0; +unsigned char flag_mi_auth_result = 0; +unsigned char mi_romid[8] = { 0x00 }; +unsigned char mi_status[8] = { 0x00 }; +unsigned char mi_page0_data[16] = { 0x00 }; +unsigned char mi_page1_data[16] = { 0x00 }; +unsigned char mi_counter[16] = { 0x00 }; +int mi_auth_result = 0x00; +static bool batt_verified_result_from_uefi; +static bool batt_chip_ok_result_from_uefi; + +unsigned char crc_low_first(unsigned char *ptr, unsigned char len) +{ + unsigned char i; + unsigned char crc = 0x00; + + while (len--) { + crc ^= *ptr++; + for (i = 0; i < 8; ++i) { + if (crc & 0x01) + crc = (crc >> 1) ^ 0x8c; + else + crc = (crc >> 1); + } + } + + return (crc); +} + +short Read_RomID(unsigned char *RomID) +{ + unsigned char i; + unsigned char crc = 0x00; + + if (flag_mi_romid == 2) { + memcpy(RomID, mi_romid, 8); + return DS_TRUE; + } + + if ((ow_reset()) != 0) { + ds_err("Read_RomID: Failed to reset ds28e16!\n"); + ow_reset(); + return ERROR_NO_DEVICE; + } + + ds_dbg("Ready to write 0x33 to maxim IC!\n"); + write_byte(CMD_READ_ROM); + Delay_us(10); + for (i = 0; i < 8; i++) + RomID[i] = read_byte(); + + ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", RomID[0], + RomID[1], RomID[2], RomID[3], RomID[4], RomID[5], RomID[6], + RomID[7]); + + crc = crc_low_first(RomID, 7); + ds_dbg("crc_low_first = %02x\n", crc); + + if (crc == RomID[7]) { + memcpy(mi_romid, RomID, 8); + if (mi_romid[0] == FAMILY_CODE && + mi_romid[6] == CUSTOM_ID_MSB && + (mi_romid[5] & 0xF0) == CUSTOM_ID_LSB) + flag_mi_romid = 2; + return DS_TRUE; + } else { + ow_reset(); + return DS_FALSE; + } +} + +unsigned short docrc16(unsigned short data) +{ + data = (data ^ (CRC16 & 0xff)) & 0xff; + CRC16 >>= 8; + + if (oddparity[data & 0xf] ^ oddparity[data >> 4]) + CRC16 ^= 0xc001; + + data <<= 6; + CRC16 ^= data; + data <<= 1; + CRC16 ^= data; + + return CRC16; +} + +int DS28E16_standard_cmd_flow(unsigned char *write_buf, int delay_ms, + unsigned char *read_buf, int *read_len, + int write_len) +{ + unsigned char buf[128]; + int i; + int buf_len = 0; + int expected_read_len = *read_len; + + //NEW FLOW + /*'1 Wire + ''''''''''''''''''''''' + ? + ? + ?TX: Start Command + ?TX: Length Byte + ?TX: Memory Command + ?TX: Parameter, TX: Data + ?RX: CRC16 + ?TX: Release Byte + ? + ?RX: Dummy Byte + ?RX: Length Byte + ?RX: Result byte + ?RX: CRC16 + ?< wait for reset> + '''''''''''''''''''''''*/ + ds_dbg("DS28E16_standard_cmd_flow start\n"); + + if ((ow_reset()) != 0) { + ds_err("Failed to reset ds28e16!\n"); + ow_reset(); + return ERROR_NO_DEVICE; + } + + write_byte(CMD_SKIP_ROM); + + buf[buf_len++] = CMD_START; + memcpy(&buf[buf_len], write_buf, write_len); + buf_len += write_len; + for (i = 0; i < buf_len; i++) + write_byte(buf[i]); + + buf[buf_len++] = read_byte(); + buf[buf_len++] = read_byte(); + + CRC16 = 0; + for (i = 0; i < buf_len; i++) + docrc16(buf[i]); + + if (CRC16 != 0xB001) { + ow_reset(); + ds_dbg("DS28E16_standard_cmd_flow: crc error!\n"); + return DS_FALSE; + } + + // check for strong pull-up + if (delay_ms > 0) { + write_byte(CMD_RELEASE_BYTE); + Delay_us(1000 * delay_ms); + } + + read_byte(); + *read_len = read_byte(); + + if (expected_read_len != *read_len) { + ow_reset(); + ds_dbg("DS28E16_standard_cmd_flow: len error!\n"); + return DS_FALSE; + } + + buf_len = *read_len + 2; + for (i = 0; i < buf_len; i++) + buf[i] = read_byte(); + + CRC16 = 0; + docrc16(*read_len); + for (i = 0; i < buf_len; i++) + docrc16(buf[i]); + + if (CRC16 != 0xB001) { + ow_reset(); + ds_dbg("DS28E16_standard_cmd_flow: crc2 error!\n"); + return DS_FALSE; + } + + memcpy(read_buf, buf, *read_len); + ds_dbg("DS28E16_standard_cmd_flow success!\n"); + return DS_TRUE; +} + +//-------------------------------------------------------------------------- +/// 'Read Status' command +/// +/// @param[out] data +/// pointer to unsigned char (buffer of length 1) for page protection data +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_readStatus(unsigned char *data) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int len_byte = 1; + int read_len = 7; + + if (flag_mi_status) { + memcpy(data, mi_status, 8); + return DS_TRUE; + } + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Read Page Protection command + ?TX: Length (SMBus) [always 1] + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Protection Data + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_READ_STATUS; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_READ * tm, + read_buf, &read_len, write_len)) { + if (read_buf[0] == RESULT_SUCCESS) { + last_result_byte = read_buf[0]; + memcpy(data, &read_buf[1], 8); + flag_mi_status = 1; + memcpy(mi_status, data, 8); + MANID[0] = data[4]; + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Read Memory' command +/// +/// @param[in] pg +/// page number to read +/// @param[out] data +/// buffer length must be at least 32 bytes to hold memory read +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_readMemory(int pg, unsigned char *data) +{ + unsigned char write_buf[3]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 33; + int length_byte = 2; + unsigned char pagenum = (unsigned char)pg & 0x03; + + switch (pagenum) { + case 0x00: + if (flag_mi_page0_data) { + memcpy(data, mi_page0_data, 16); + return DS_TRUE; + } + break; + case 0x01: + if (flag_mi_page1_data) { + memcpy(data, mi_page1_data, 16); + return DS_TRUE; + } + break; + case 0x02: + if (flag_mi_counter) { + memcpy(data, mi_counter, 16); + return DS_TRUE; + } + break; + default: + return DS_FALSE; + } + + last_result_byte = RESULT_FAIL_NONE; + + /* + ? + ?TX: Read Memory Command + ?TX: Length (SMBus) + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) + ?RX: Result byte + ?RX: Data + ? + */ + + write_buf[write_len++] = length_byte; + write_buf[write_len++] = CMD_READ_MEM; + write_buf[write_len++] = pagenum; + + ds_dbg("DS28E16_cmd_readMemory write_buf:\n"); + ds_dbg("%02x %02x %02x", write_buf[0], write_buf[1], write_buf[2]); + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_READ * tm, + read_buf, &read_len, write_len)) { + if (read_len == 33) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + memcpy(data, &read_buf[1], 16); + if (pagenum == 0x00) { + flag_mi_page0_data = 1; + memcpy(mi_page0_data, data, 16); + } + if (pagenum == 0x01) { + flag_mi_page1_data = 1; + memcpy(mi_page1_data, data, 16); + } + return DS_TRUE; + } else { + if (read_buf[0] == 0x55 && pagenum == 2) { + memcpy(data, &read_buf[1], 16); + flag_mi_counter = 1; + memcpy(mi_counter, data, 16); + return DS_TRUE; + } + } + } + } + + ow_reset(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Write Memory' command +/// +/// @param[in] pg +/// page number to write +/// @param[in] data +/// buffer must be at least 32 bytes +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_writeMemory(int pg, unsigned char *data) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + int len_byte = 18; + unsigned char pagenum = (unsigned char)pg & 0x03; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Write Memory Command + ?TX: Length (SMBus) [always 33] + ?TX: Parameter + ?TX: Data + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_WRITE_MEM; + write_buf[write_len++] = pagenum; + memcpy(&write_buf[write_len], data, 16); + write_len += 16; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE * tm, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + if (pagenum == 0x00) { + flag_mi_page0_data = 0; + memset(mi_page0_data, 0x00, 16); + } + if (pagenum == 0x01) { + flag_mi_page1_data = 0; + memset(mi_page0_data, 0x00, 16); + } + if (pagenum == 0x02) { + flag_mi_counter = 0; + memset(mi_counter, 0x00, 16); + } + return DS_TRUE; + } + } + } + + ow_reset(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Decrement Counter' command +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_decrementCounter(void) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Decrement Counter Command + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = 1; + write_buf[write_len++] = CMD_DECREMENT_CNT; + + if (DS28E16_standard_cmd_flow(write_buf, 50, read_buf, &read_len, + write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Set Page Protection' command +/// +/// @param[in] pg +/// block to set protection +/// @param[in] prot +/// protection value to set +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_setPageProtection(int page, unsigned char prot) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + int len_byte = 3; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Set Page Protection Command + ?TX: Length (SMBus) [always 2] + ?TX: Parameter + ?TX: Protection Data + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_SET_PAGE_PROT; + write_buf[write_len++] = page & 0x03; + write_buf[write_len++] = prot & 0x03; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE * tm, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +int DS28E16_cmd_device_disable(int op, unsigned char *password) +{ + unsigned char write_buf[64]; + unsigned char read_buf[64]; + int write_len = 0; + int read_len = 1; + int length_byte = 10; + + last_result_byte = RESULT_FAIL_NONE; + /* + ? + ?TX: Length + ?TX: Device Disable Command + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) + ?RX: Result byte + ?RX: Data + ? + */ + + write_buf[write_len++] = length_byte; + write_buf[write_len++] = CMD_DISABLE_DEVICE; + write_buf[write_len++] = op & 0x0F; + memcpy(&write_buf[write_len], password, 8); + write_len += 8; + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +// -------------------------------------------------------------------------- +/// 'Compute and Read Page Authentication' command +/// +/// @param[in] anon - boolean parameter +/// @param[in] pg - Page number 2,计数å™? 0,page0; 1,page1; +/// @param[in] challenge +/// @param[out] hmac 返回的计算结æž?2个字èŠ?/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_computeReadPageAuthentication(int anon, int pg, + unsigned char *challenge, + unsigned char *hmac) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 33; + int len_byte = 35; + + last_result_byte = RESULT_FAIL_NONE; + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_COMP_READ_AUTH; + write_buf[write_len] = pg & 0x03; + if (anon) + write_buf[write_len] = (write_buf[write_len] | 0xE0); + + write_len++; + write_buf[write_len++] = 0x02; // Fixed Parameter + memcpy(&write_buf[write_len], challenge, 32); // Challenge + write_len += 32; + + ds_dbg("computeReadPageAuthen:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + write_buf[0], write_buf[1], write_buf[2], write_buf[3], + write_buf[4], write_buf[5], write_buf[6], write_buf[7], + write_buf[8], write_buf[9], write_buf[10], write_buf[11], + write_buf[12], write_buf[13], write_buf[14], write_buf[15], + write_buf[16], write_buf[17], write_buf[18], write_buf[19], + write_buf[20], write_buf[21], write_buf[22], write_buf[23], + write_buf[24], write_buf[25], write_buf[26], write_buf[27], + write_buf[28], write_buf[29], write_buf[30], write_buf[31], + write_buf[32], write_buf[33], write_buf[34]); + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + ds_dbg("hmac read_buf:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + read_buf[0], read_buf[1], read_buf[2], + read_buf[3], read_buf[4], read_buf[5], + read_buf[6], read_buf[7], read_buf[8], + read_buf[9], read_buf[10], read_buf[11], + read_buf[12], read_buf[13], read_buf[14], + read_buf[15], read_buf[16], read_buf[17], + read_buf[18], read_buf[19], read_buf[20], + read_buf[21], read_buf[22], read_buf[23], + read_buf[24], read_buf[25], read_buf[26], + read_buf[27], read_buf[28], read_buf[29], + read_buf[30], read_buf[31], read_buf[32]); + memcpy(hmac, &read_buf[1], 32); + ds_dbg("hmac:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + hmac[0], hmac[1], hmac[2], hmac[3], hmac[4], + hmac[5], hmac[6], hmac[7], hmac[8], hmac[9], + hmac[10], hmac[11], hmac[12], hmac[13], hmac[14], + hmac[15], hmac[16], hmac[17], hmac[18], hmac[19], + hmac[20], hmac[21], hmac[22], hmac[23], hmac[24], + hmac[25], hmac[26], hmac[27], hmac[28], hmac[29], + hmac[30], hmac[31]); + return DS_TRUE; + } + } + + ow_reset(); + return DS_FALSE; +} + +// -------------------------------------------------------------------------- +/// 'Compute Secret S' command +/// +/// @param[in] anon - boolean parameter +/// @param[in] bdconst - boolean parameter +/// @param[in] pg - Page number é¡µé¢ +/// @param[in] partial secret 32个字节的ç§å­ +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_computeS_Secret(int anon, int bdconst, int pg, + unsigned char *partial) +{ + unsigned char write_buf[40]; + unsigned char read_buf[40]; + int write_len = 0; + int read_len = 1; + int len_byte = 35; + int param = pg & 0x03; + + last_result_byte = RESULT_FAIL_NONE; + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_COMP_S_SECRET; + + if (bdconst) + param = param | 0x04; + if (anon) + param = param | 0xE0; + + write_buf[write_len] = param; + write_len++; + write_buf[write_len++] = 0x08; // Fixed Parameter + memcpy(&write_buf[write_len], partial, 32); // Partial Secret + write_len += 32; + + ds_dbg("computeS_Secret:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + write_buf[0], write_buf[1], write_buf[2], write_buf[3], + write_buf[4], write_buf[5], write_buf[6], write_buf[7], + write_buf[8], write_buf[9], write_buf[10], write_buf[11], + write_buf[12], write_buf[13], write_buf[14], write_buf[15], + write_buf[16], write_buf[17], write_buf[18], write_buf[19], + write_buf[20], write_buf[21], write_buf[22], write_buf[23], + write_buf[24], write_buf[25], write_buf[26], write_buf[27], + write_buf[28], write_buf[29], write_buf[30], write_buf[31], + write_buf[32], write_buf[33], write_buf[34]); + + if (DS28E16_standard_cmd_flow(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + last_result_byte = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + + ow_reset(); + return DS_FALSE; +} + +int AuthenticateDS28E16(int anon, int bdconst, int S_Secret_PageNum, + int PageNum, unsigned char *Challenge, + unsigned char *Secret_Seeds, unsigned char *S_Secret) +{ + unsigned char PageData[32], MAC_Read_Value[32], CAL_MAC[32]; + unsigned char status_chip[16]; + unsigned char MAC_Computer_Datainput[128]; + int i = 0; + int msg_len = 0; + unsigned char flag = DS_FALSE; + + //if (flag_mi_auth_result) + if (mi_auth_result == DS_TRUE) + return mi_auth_result; + + if (anon != ANONYMOUS) { + if (ds28el16_get_page_status_retry(status_chip) == DS_TRUE) { + MANID[0] = status_chip[4]; + } else { + ow_reset(); + return ERROR_R_STATUS; + } + + if (ds28el16_Read_RomID_retry(mi_romid) != DS_TRUE) { + ow_reset(); + return ERROR_R_ROMID; + } + } + + // DS28E16 calculate its session secret + flag = DS28E16_cmd_computeS_Secret_retry( + anon, bdconst, S_Secret_PageNum, Secret_Seeds); + if (flag == DS_FALSE) { + ds_err("DS28E16_cmd_computeS_Secret error"); + ow_reset(); + return ERROR_S_SECRET; + } + + // DS28E16 compute its MAC based on above sessio secret + flag = DS28E16_cmd_computeReadPageAuthentication_retry( + anon, PageNum, Challenge, MAC_Read_Value); + if (flag == DS_FALSE) { + ds_err("DS28E16_cmd_computeReadPageAuthentication error"); + ow_reset(); + return ERROR_COMPUTE_MAC; + } + + ds_dbg("%02x %02x %02x %02x", anon, bdconst, S_Secret_PageNum, PageNum); + + ds_dbg("Seeds:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + Secret_Seeds[0], Secret_Seeds[1], Secret_Seeds[2], + Secret_Seeds[3], Secret_Seeds[4], Secret_Seeds[5], + Secret_Seeds[6], Secret_Seeds[7], Secret_Seeds[8], + Secret_Seeds[9], Secret_Seeds[10], Secret_Seeds[11], + Secret_Seeds[12], Secret_Seeds[13], Secret_Seeds[14], + Secret_Seeds[15], Secret_Seeds[16], Secret_Seeds[17], + Secret_Seeds[18], Secret_Seeds[19], Secret_Seeds[20], + Secret_Seeds[21], Secret_Seeds[22], Secret_Seeds[23], + Secret_Seeds[24], Secret_Seeds[25], Secret_Seeds[26], + Secret_Seeds[27], Secret_Seeds[28], Secret_Seeds[29], + Secret_Seeds[30], Secret_Seeds[31]); + + ds_dbg("S_Secret:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + S_Secret[0], S_Secret[1], S_Secret[2], S_Secret[3], S_Secret[4], + S_Secret[5], S_Secret[6], S_Secret[7], S_Secret[8], S_Secret[9], + S_Secret[10], S_Secret[11], S_Secret[12], S_Secret[13], + S_Secret[14], S_Secret[15], S_Secret[16], S_Secret[17], + S_Secret[18], S_Secret[19], S_Secret[20], S_Secret[21], + S_Secret[22], S_Secret[23], S_Secret[24], S_Secret[25], + S_Secret[26], S_Secret[27], S_Secret[28], S_Secret[29], + S_Secret[30], S_Secret[31]); + + ds_dbg("Challenge:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + Challenge[0], Challenge[1], Challenge[2], Challenge[3], + Challenge[4], Challenge[5], Challenge[6], Challenge[7], + Challenge[8], Challenge[9], Challenge[10], Challenge[11], + Challenge[12], Challenge[13], Challenge[14], Challenge[15], + Challenge[16], Challenge[17], Challenge[18], Challenge[19], + Challenge[20], Challenge[21], Challenge[22], Challenge[23], + Challenge[24], Challenge[25], Challenge[26], Challenge[27], + Challenge[28], Challenge[29], Challenge[30], Challenge[31]); + + ds_dbg("MAC_Read_Value:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + MAC_Read_Value[0], MAC_Read_Value[1], MAC_Read_Value[2], + MAC_Read_Value[3], MAC_Read_Value[4], MAC_Read_Value[5], + MAC_Read_Value[6], MAC_Read_Value[7], MAC_Read_Value[8], + MAC_Read_Value[9], MAC_Read_Value[10], MAC_Read_Value[11], + MAC_Read_Value[12], MAC_Read_Value[13], MAC_Read_Value[14], + MAC_Read_Value[15], MAC_Read_Value[16], MAC_Read_Value[17], + MAC_Read_Value[18], MAC_Read_Value[19], MAC_Read_Value[20], + MAC_Read_Value[21], MAC_Read_Value[22], MAC_Read_Value[23], + MAC_Read_Value[24], MAC_Read_Value[25], MAC_Read_Value[26], + MAC_Read_Value[27], MAC_Read_Value[28], MAC_Read_Value[29], + MAC_Read_Value[30], MAC_Read_Value[31]); + + // read the page data + flag = ds28el16_get_page_data_retry(PageNum, PageData); + if (flag != DS_TRUE) { + ds_err("DS28E16_cmd_readMemory error"); + ow_reset(); + return ERROR_R_PAGEDATA; + } + + // insert mi_romid + if (anon != ANONYMOUS) + memcpy(MAC_Computer_Datainput, mi_romid, 8); + else + memset(MAC_Computer_Datainput, 0xff, 8); + msg_len += 8; + + // insert Page Data + memcpy(&MAC_Computer_Datainput[msg_len], PageData, 16); + msg_len += 16; + memset(&MAC_Computer_Datainput[msg_len], 0x00, 16); + msg_len += 16; + + // insert Challenge + memcpy(&MAC_Computer_Datainput[msg_len], Challenge, 32); + msg_len += 32; + + // insert Bind Data Page number + MAC_Computer_Datainput[msg_len] = PageNum & 0x03; + MAC_Computer_Datainput[msg_len] = MAC_Computer_Datainput[msg_len] & + 0x03; + msg_len += 1; + + // insert MANID + memcpy(&MAC_Computer_Datainput[msg_len], MANID, 2); + msg_len += 2; + + // calculate the MAC + sha3_256_hmac(S_Secret, 32, MAC_Computer_Datainput, msg_len, CAL_MAC); + + ds_dbg("host data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + MAC_Computer_Datainput[0], MAC_Computer_Datainput[1], + MAC_Computer_Datainput[2], MAC_Computer_Datainput[3], + MAC_Computer_Datainput[4], MAC_Computer_Datainput[5], + MAC_Computer_Datainput[6], MAC_Computer_Datainput[7], + MAC_Computer_Datainput[8], MAC_Computer_Datainput[9], + MAC_Computer_Datainput[10], MAC_Computer_Datainput[11], + MAC_Computer_Datainput[12], MAC_Computer_Datainput[13], + MAC_Computer_Datainput[14], MAC_Computer_Datainput[15], + MAC_Computer_Datainput[16], MAC_Computer_Datainput[17], + MAC_Computer_Datainput[18], MAC_Computer_Datainput[19], + MAC_Computer_Datainput[20], MAC_Computer_Datainput[21], + MAC_Computer_Datainput[22], MAC_Computer_Datainput[23], + MAC_Computer_Datainput[24], MAC_Computer_Datainput[25], + MAC_Computer_Datainput[26], MAC_Computer_Datainput[27], + MAC_Computer_Datainput[28], MAC_Computer_Datainput[29], + MAC_Computer_Datainput[30], MAC_Computer_Datainput[31], + MAC_Computer_Datainput[32], MAC_Computer_Datainput[33], + MAC_Computer_Datainput[34], MAC_Computer_Datainput[35], + MAC_Computer_Datainput[36], MAC_Computer_Datainput[37], + MAC_Computer_Datainput[38], MAC_Computer_Datainput[39], + MAC_Computer_Datainput[40], MAC_Computer_Datainput[41], + MAC_Computer_Datainput[42], MAC_Computer_Datainput[43], + MAC_Computer_Datainput[44], MAC_Computer_Datainput[45], + MAC_Computer_Datainput[46], MAC_Computer_Datainput[47], + MAC_Computer_Datainput[48], MAC_Computer_Datainput[49], + MAC_Computer_Datainput[50], MAC_Computer_Datainput[51], + MAC_Computer_Datainput[52], MAC_Computer_Datainput[53], + MAC_Computer_Datainput[54], MAC_Computer_Datainput[55], + MAC_Computer_Datainput[56], MAC_Computer_Datainput[57], + MAC_Computer_Datainput[58], MAC_Computer_Datainput[59], + MAC_Computer_Datainput[60], MAC_Computer_Datainput[61], + MAC_Computer_Datainput[62], MAC_Computer_Datainput[63], + MAC_Computer_Datainput[64], MAC_Computer_Datainput[65], + MAC_Computer_Datainput[66], MAC_Computer_Datainput[67], + MAC_Computer_Datainput[68], MAC_Computer_Datainput[69], + MAC_Computer_Datainput[70], MAC_Computer_Datainput[71], + MAC_Computer_Datainput[72], MAC_Computer_Datainput[73], + MAC_Computer_Datainput[74], MAC_Computer_Datainput[75], + MAC_Computer_Datainput[76], MAC_Computer_Datainput[77], + MAC_Computer_Datainput[78], MAC_Computer_Datainput[79]); + + ds_dbg("host mac:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + CAL_MAC[0], CAL_MAC[1], CAL_MAC[2], CAL_MAC[3], CAL_MAC[4], + CAL_MAC[5], CAL_MAC[6], CAL_MAC[7], CAL_MAC[8], CAL_MAC[9], + CAL_MAC[10], CAL_MAC[11], CAL_MAC[12], CAL_MAC[13], CAL_MAC[14], + CAL_MAC[15], CAL_MAC[16], CAL_MAC[17], CAL_MAC[18], CAL_MAC[19], + CAL_MAC[20], CAL_MAC[21], CAL_MAC[22], CAL_MAC[23], CAL_MAC[24], + CAL_MAC[25], CAL_MAC[26], CAL_MAC[27], CAL_MAC[28], CAL_MAC[29], + CAL_MAC[30], CAL_MAC[31]); + + for (i = 0; i < 32; i++) { + if (CAL_MAC[i] != MAC_Read_Value[i]) + break; + } + + if (i != 32) { + flag_mi_auth_result = 1; + mi_auth_result = ERROR_UNMATCH_MAC; + // for debug + ds_dbg("hmac is not match. result=ERROR_UNMATCH_MAC\n"); + flag_mi_page1_data = 0; + return ERROR_UNMATCH_MAC; + } else { + flag_mi_auth_result = 1; + ds_dbg("hmac is match. result=DS_TRUE\n"); + mi_auth_result = DS_TRUE; + return DS_TRUE; + } +} + +// retry interface start // +static int ds28el16_Read_RomID_retry(unsigned char *RomID) +{ + int i; + unsigned char data[50]; + + for (i = 0; i < GET_ROM_ID_RETRY; i++) { + ds_info("read rom id communication start %d...\n", i); + if (DS28E16_cmd_readStatus(data) == DS_TRUE) { + if (Read_RomID(RomID) == DS_TRUE) + return DS_TRUE; + } + } + ds_log("ds28el16_Read_RomID_retry fail\n"); + return DS_FALSE; +} + +static int ds28el16_get_page_status_retry(unsigned char *data) +{ + int i; + + for (i = 0; i < GET_BLOCK_STATUS_RETRY; i++) { + ds_info("read page status communication start... %d\n", i); + + if (DS28E16_cmd_readStatus(data) == DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +/* +static int ds28el16_set_page_status_retry(unsigned char page, unsigned char status) +{ + int i; + + for (i = 0; i < SET_BLOCK_STATUS_RETRY; i++) { + ds_info("set page status communication start... %d\n", i); + + if (DS28E16_cmd_setPageProtection(page, status) == TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} +*/ + +static int ds28el16_get_page_data_retry(int page, unsigned char *data) +{ + int i; + + if (page >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_USER_MEMORY_RETRY; i++) { + ds_dbg("read page data communication start... %d\n", i); + + if (DS28E16_cmd_readMemory(page, data) == DS_TRUE) { + ds_dbg("page number is %d\n", page); + ds_dbg("page data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + data[0], data[1], data[2], data[3], data[4], + data[5], data[6], data[7], data[8], data[9], + data[10], data[11], data[12], data[13], data[14], + data[15]); + ds_dbg("flag_mi_page0_data is %d\n", + flag_mi_page0_data); + ds_dbg("mi_page0_data data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + mi_page0_data[0], mi_page0_data[1], + mi_page0_data[2], mi_page0_data[3], + mi_page0_data[4], mi_page0_data[5], + mi_page0_data[6], mi_page0_data[7], + mi_page0_data[8], mi_page0_data[9], + mi_page0_data[10], mi_page0_data[11], + mi_page0_data[12], mi_page0_data[13], + mi_page0_data[14], mi_page0_data[15]); + ds_dbg("flag_mi_page1_data is %d\n", + flag_mi_page1_data); + ds_dbg("mi_page1_data data:\n"); + ds_dbg("%%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + mi_page1_data[0], mi_page1_data[1], + mi_page1_data[2], mi_page1_data[3], + mi_page1_data[4], mi_page1_data[5], + mi_page1_data[6], mi_page1_data[7], + mi_page1_data[8], mi_page1_data[9], + mi_page1_data[10], mi_page1_data[11], + mi_page1_data[12], mi_page1_data[13], + mi_page1_data[14], mi_page1_data[15]); + ds_dbg("flag_mi_counter is %d\n", flag_mi_counter); + return DS_TRUE; + } + } + + return DS_FALSE; +} + +static int DS28E16_cmd_computeS_Secret_retry(int anon, int bdconst, int pg, + unsigned char *partial) +{ + int i; + + if (pg >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_S_SECRET_RETRY; i++) { + if (DS28E16_cmd_computeS_Secret(anon, bdconst, pg, partial) == + DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +static int DS28E16_cmd_computeReadPageAuthentication_retry( + int anon, int pg, unsigned char *challenge, unsigned char *hmac) +{ + int i; + + if (pg >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_MAC_RETRY; i++) { + if (DS28E16_cmd_computeReadPageAuthentication( + anon, pg, challenge, hmac) == DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +// retry interface end // + +/* All power supply functions here */ + +static enum power_supply_property verify_props[] = { + POWER_SUPPLY_PROP_ROMID, + POWER_SUPPLY_PROP_DS_STATUS, + POWER_SUPPLY_PROP_PAGENUMBER, + POWER_SUPPLY_PROP_PAGEDATA, + POWER_SUPPLY_PROP_AUTHEN_RESULT, + POWER_SUPPLY_PROP_SESSION_SEED, + POWER_SUPPLY_PROP_S_SECRET, + POWER_SUPPLY_PROP_CHALLENGE, + POWER_SUPPLY_PROP_AUTH_ANON, + POWER_SUPPLY_PROP_AUTH_BDCONST, + POWER_SUPPLY_PROP_PAGE0_DATA, + POWER_SUPPLY_PROP_PAGE1_DATA, + POWER_SUPPLY_PROP_VERIFY_MODEL_NAME, + POWER_SUPPLY_PROP_CHIP_OK, +}; + +static int verify_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + int ret; + unsigned char buf[50]; + + switch (psp) { + case POWER_SUPPLY_PROP_VERIFY_MODEL_NAME: + ret = ds28el16_Read_RomID_retry(mi_romid); + if (ret == DS_TRUE) + val->strval = "ds28e16"; + else + val->strval = "unknown"; + break; + case POWER_SUPPLY_PROP_AUTHEN_RESULT: + if (batt_verified_result_from_uefi) { + val->intval = true; + ds_info("batt_verified_result_from_uefi is true\n"); + break; + } + ret = AuthenticateDS28E16(auth_ANON, auth_BDCONST, 0, + pagenumber, challenge, session_seed, + S_secret); + if (ret == DS_TRUE) + val->intval = true; + else + val->intval = false; + break; + case POWER_SUPPLY_PROP_PAGENUMBER: + val->intval = pagenumber; + break; + case POWER_SUPPLY_PROP_ROMID: + ret = ds28el16_Read_RomID_retry(mi_romid); + memcpy(val->arrayval, mi_romid, 8); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_CHIP_OK: + if (batt_chip_ok_result_from_uefi) { + val->intval = true; + ds_log("batt_chip_ok_result_from_uefi is true already\n"); + break; + } + ret = ds28el16_Read_RomID_retry(mi_romid); + if ((mi_romid[0] == FAMILY_CODE) && + (mi_romid[6] == CUSTOM_ID_MSB) && + ((mi_romid[5] & 0xf0) == CUSTOM_ID_LSB)) + val->intval = true; + else + val->intval = false; + break; + case POWER_SUPPLY_PROP_DS_STATUS: + ret = ds28el16_get_page_status_retry(buf); + memcpy(val->arrayval, buf, 8); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGEDATA: + ret = ds28el16_get_page_data_retry(pagenumber, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGE0_DATA: + ret = ds28el16_get_page_data_retry(0, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGE1_DATA: + ret = ds28el16_get_page_data_retry(1, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + default: + ds_err("unsupported property %d\n", psp); + return -ENODATA; + } + + return 0; +} + +static int verify_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + //int ret; + //unsigned char buf[50]; + + switch (prop) { + case POWER_SUPPLY_PROP_PAGENUMBER: + pagenumber = val->intval; + break; + /* + case POWER_SUPPLY_PROP_PAGEDATA: + memcpy(buf, val->arrayval, 16); + ret = DS28E16_cmd_writeMemory(pagenumber, buf); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_SESSION_SEED: + memcpy(session_seed, val->arrayval, 32); + break; + case POWER_SUPPLY_PROP_S_SECRET: + memcpy(S_secret, val->arrayval, 32); + break; + case POWER_SUPPLY_PROP_CHALLENGE: + memcpy(challenge, val->arrayval, 32); + break; +*/ + case POWER_SUPPLY_PROP_AUTH_ANON: + auth_ANON = val->intval; + break; + case POWER_SUPPLY_PROP_AUTH_BDCONST: + auth_BDCONST = val->intval; + break; + default: + ds_err("unsupported property %d\n", prop); + return -ENODATA; + } + + return 0; +} + +static int verify_prop_is_writeable(struct power_supply *psy, + enum power_supply_property prop) +{ + int ret; + + switch (prop) { + case POWER_SUPPLY_PROP_PAGENUMBER: + case POWER_SUPPLY_PROP_PAGEDATA: + case POWER_SUPPLY_PROP_SESSION_SEED: + case POWER_SUPPLY_PROP_S_SECRET: + case POWER_SUPPLY_PROP_CHALLENGE: + case POWER_SUPPLY_PROP_AUTH_ANON: + case POWER_SUPPLY_PROP_AUTH_BDCONST: + ret = 1; + break; + default: + ret = 0; + break; + } + return ret; +} + +static int verify_psy_register(struct ds28e16_data *ds) +{ + struct power_supply_config verify_psy_cfg = {}; + + ds->verify_psy_d.name = "batt_verify"; + ds->verify_psy_d.type = POWER_SUPPLY_TYPE_BATT_VERIFY; + ds->verify_psy_d.properties = verify_props; + ds->verify_psy_d.num_properties = ARRAY_SIZE(verify_props); + ds->verify_psy_d.get_property = verify_get_property; + ds->verify_psy_d.set_property = verify_set_property; + ds->verify_psy_d.property_is_writeable = verify_prop_is_writeable; + + verify_psy_cfg.drv_data = ds; + verify_psy_cfg.of_node = ds->dev->of_node; + verify_psy_cfg.num_supplicants = 0; + ds->verify_psy = devm_power_supply_register(ds->dev, &ds->verify_psy_d, + &verify_psy_cfg); + if (IS_ERR(ds->verify_psy)) { + ds_err("Failed to register verify_psy"); + return PTR_ERR(ds->verify_psy); + } + + ds_log("%s power supply register successfully\n", + ds->verify_psy_d.name); + return 0; +} + +static void verify_psy_unregister(struct ds28e16_data *ds) +{ + power_supply_unregister(ds->verify_psy); +} + +// parse dts +static int ds28e16_parse_dt(struct device *dev, struct ds28e16_data *pdata) +{ + int error, val; + struct device_node *np = dev->of_node; + + // parse version + pdata->version = 0; + error = of_property_read_u32(np, "maxim,version", &val); + if (error && (error != -EINVAL)) + ds_err("Unable to read bootloader address\n"); + else if (error != -EINVAL) + pdata->version = val; + + return 0; +} + +// read data from file +static ssize_t ds28e16_ds_Auth_Result_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + + result = AuthenticateDS28E16(auth_ANON, auth_BDCONST, 0, pagenumber, + challenge, session_seed, S_secret); + if (result == ERROR_R_STATUS) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_R_STATUS!\n"); + else if (result == ERROR_UNMATCH_MAC) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : MAC is not match!\n"); + else if (result == ERROR_R_ROMID) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_R_ROMID!\n"); + else if (result == ERROR_COMPUTE_MAC) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_COMPUTE_MAC!\n"); + else if (result == ERROR_S_SECRET) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_S_SECRET!\n"); + else if (result == DS_TRUE) + return scnprintf(buf, PAGE_SIZE, "Authenticate success!!!\n"); + else + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : other reason.\n"); +} + +static ssize_t ds28e16_ds_romid_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + short status; + unsigned char RomID[10] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes; i++) { + status = ds28el16_Read_RomID_retry(RomID); + + if (status == DS_TRUE) { + count++; + ds_log("Read_RomID success!\n"); + } else { + ds_log("Read_RomID fail!\n"); + } + ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + RomID[0], RomID[1], RomID[2], RomID[3], RomID[4], + RomID[5], RomID[6], RomID[7]); + Delay_us(1000); + } + + /*ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + RomID[0], RomID[1], RomID[2], RomID[3], + RomID[4], RomID[5], RomID[6], RomID[7]); + */ + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\nRomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, RomID[0], RomID[1], RomID[2], RomID[3], RomID[4], + RomID[5], RomID[6], RomID[7]); +} + +static ssize_t ds28e16_ds_pagenumber_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", pagenumber); +} + +static ssize_t ds28e16_ds_pagenumber_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int buf_int; + + if (sscanf(buf, "%d", &buf_int) != 1) + return -EINVAL; + + ds_dbg("new pagenumber = %d\n", buf_int); + + if ((buf_int >= 0) && (buf_int <= 3)) + pagenumber = buf_int; + + return count; +} + +static ssize_t ds28e16_ds_pagedata_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + unsigned char pagedata[16] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes; i++) { + result = ds28el16_get_page_data_retry(pagenumber, pagedata); + + if (result == DS_TRUE) { + count++; + ds_log("DS28E16_cmd_readMemory success!\n"); + } else { + ds_log("DS28E16_cmd_readMemory fail!\n"); + } + ds_dbg("pagedata = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + pagedata[0], pagedata[1], pagedata[2], pagedata[3], + pagedata[4], pagedata[5], pagedata[6], pagedata[7], + pagedata[8], pagedata[9], pagedata[10], pagedata[11], + pagedata[12], pagedata[13], pagedata[14], pagedata[15]); + Delay_us(1000); + } + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\npagedata = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, pagedata[0], pagedata[1], pagedata[2], pagedata[3], + pagedata[4], pagedata[5], pagedata[6], pagedata[7], pagedata[8], + pagedata[9], pagedata[10], pagedata[11], pagedata[12], + pagedata[13], pagedata[14], pagedata[15]); +} + +static ssize_t ds28e16_ds_pagedata_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int result; + unsigned char pagedata[16] = { 0x00 }; + + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &pagedata[0], &pagedata[1], &pagedata[2], &pagedata[3], + &pagedata[4], &pagedata[5], &pagedata[6], &pagedata[7], + &pagedata[8], &pagedata[9], &pagedata[10], &pagedata[11], + &pagedata[12], &pagedata[13], &pagedata[14], + &pagedata[15]) != 16) + return -EINVAL; + + ds_dbg("new data = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + pagedata[0], pagedata[1], pagedata[2], pagedata[3], pagedata[4], + pagedata[5], pagedata[6], pagedata[7], pagedata[8], pagedata[9], + pagedata[10], pagedata[11], pagedata[12], pagedata[13], + pagedata[14], pagedata[15]); + + result = DS28E16_cmd_writeMemory(pagenumber, pagedata); + if (result == DS_TRUE) + ds_log("DS28E16_cmd_writeMemory success!\n"); + else + ds_log("DS28E16_cmd_writeMemory fail!\n"); + + return count; +} + +static ssize_t ds28e16_ds_time_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%d\n", attr_trytimes); +} + +static ssize_t ds28e16_ds_time_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int buf_int; + + if (sscanf(buf, "%d", &buf_int) != 1) + return -EINVAL; + + ds_log("new trytimes = %d\n", buf_int); + + if (buf_int > 0) + attr_trytimes = buf_int; + + return count; +} + +static ssize_t +ds28e16_ds_session_seed_status_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + session_seed[0], session_seed[1], session_seed[2], + session_seed[3], session_seed[4], session_seed[5], + session_seed[6], session_seed[7], session_seed[8], + session_seed[9], session_seed[10], session_seed[11], + session_seed[12], session_seed[13], session_seed[14], + session_seed[15], session_seed[16], session_seed[17], + session_seed[18], session_seed[19], session_seed[20], + session_seed[21], session_seed[22], session_seed[23], + session_seed[24], session_seed[25], session_seed[26], + session_seed[27], session_seed[28], session_seed[29], + session_seed[30], session_seed[31]); +} + +static ssize_t ds28e16_ds_session_seed_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &session_seed[0], &session_seed[1], &session_seed[2], + &session_seed[3], &session_seed[4], &session_seed[5], + &session_seed[6], &session_seed[7], &session_seed[8], + &session_seed[9], &session_seed[10], &session_seed[11], + &session_seed[12], &session_seed[13], &session_seed[14], + &session_seed[15], &session_seed[16], &session_seed[17], + &session_seed[18], &session_seed[19], &session_seed[20], + &session_seed[21], &session_seed[22], &session_seed[23], + &session_seed[24], &session_seed[25], &session_seed[26], + &session_seed[27], &session_seed[28], &session_seed[29], + &session_seed[30], &session_seed[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_challenge_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + challenge[0], challenge[1], challenge[2], challenge[3], + challenge[4], challenge[5], challenge[6], challenge[7], + challenge[8], challenge[9], challenge[10], challenge[11], + challenge[12], challenge[13], challenge[14], challenge[15], + challenge[16], challenge[17], challenge[18], challenge[19], + challenge[20], challenge[21], challenge[22], challenge[23], + challenge[24], challenge[25], challenge[26], challenge[27], + challenge[28], challenge[29], challenge[30], challenge[31]); +} + +static ssize_t ds28e16_ds_challenge_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &challenge[0], &challenge[1], &challenge[2], &challenge[3], + &challenge[4], &challenge[5], &challenge[6], &challenge[7], + &challenge[8], &challenge[9], &challenge[10], &challenge[11], + &challenge[12], &challenge[13], &challenge[14], + &challenge[15], &challenge[16], &challenge[17], + &challenge[18], &challenge[19], &challenge[20], + &challenge[21], &challenge[22], &challenge[23], + &challenge[24], &challenge[25], &challenge[26], + &challenge[27], &challenge[28], &challenge[29], + &challenge[30], &challenge[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_S_secret_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + S_secret[0], S_secret[1], S_secret[2], S_secret[3], S_secret[4], + S_secret[5], S_secret[6], S_secret[7], S_secret[8], S_secret[9], + S_secret[10], S_secret[11], S_secret[12], S_secret[13], + S_secret[14], S_secret[15], S_secret[16], S_secret[17], + S_secret[18], S_secret[19], S_secret[20], S_secret[21], + S_secret[22], S_secret[23], S_secret[24], S_secret[25], + S_secret[26], S_secret[27], S_secret[28], S_secret[29], + S_secret[30], S_secret[31]); +} + +static ssize_t ds28e16_ds_S_secret_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &S_secret[0], &S_secret[1], &S_secret[2], &S_secret[3], + &S_secret[4], &S_secret[5], &S_secret[6], &S_secret[7], + &S_secret[8], &S_secret[9], &S_secret[10], &S_secret[11], + &S_secret[12], &S_secret[13], &S_secret[14], &S_secret[15], + &S_secret[16], &S_secret[17], &S_secret[18], &S_secret[19], + &S_secret[20], &S_secret[21], &S_secret[22], &S_secret[23], + &S_secret[24], &S_secret[25], &S_secret[26], &S_secret[27], + &S_secret[28], &S_secret[29], &S_secret[30], + &S_secret[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_auth_ANON_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", auth_ANON); +} + +static ssize_t ds28e16_ds_auth_ANON_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, "%d", &auth_ANON) != 1) + return -EINVAL; + + return count; +} + +static ssize_t +ds28e16_ds_auth_BDCONST_status_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", auth_BDCONST); +} + +static ssize_t ds28e16_ds_auth_BDCONST_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, "%d", &auth_BDCONST) != 1) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_readstatus_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + unsigned char status[16] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes; i++) { + result = ds28el16_get_page_status_retry(status); + + if (result == DS_TRUE) { + count++; + ds_log("DS28E16_cmd_readStatus success!\n"); + } else { + ds_log("DS28E16_cmd_readStatus fail!\n"); + } + ds_dbg("Status = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + status[0], status[1], status[2], status[3], status[4], + status[5], status[6], status[7], status[8], status[9], + status[10], status[11], status[12], status[13], + status[14], status[15]); + Delay_us(1000); + } + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\nStatus = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, status[0], status[1], status[2], status[3], status[4], + status[5], status[6], status[7], status[8], status[9], + status[10], status[11], status[12], status[13], status[14], + status[15]); +} + +static DEVICE_ATTR(ds_readstatus, S_IRUGO, ds28e16_ds_readstatus_status_read, + NULL); +static DEVICE_ATTR(ds_romid, S_IRUGO, ds28e16_ds_romid_status_read, NULL); +static DEVICE_ATTR(ds_pagenumber, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_pagenumber_status_read, + ds28e16_ds_pagenumber_store); +static DEVICE_ATTR(ds_pagedata, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_pagedata_status_read, ds28e16_ds_pagedata_store); +static DEVICE_ATTR(ds_time, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_time_status_read, ds28e16_ds_time_store); +static DEVICE_ATTR(ds_session_seed, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_session_seed_status_read, + ds28e16_ds_session_seed_store); +static DEVICE_ATTR(ds_challenge, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_challenge_status_read, + ds28e16_ds_challenge_store); +static DEVICE_ATTR(ds_S_secret, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_S_secret_status_read, ds28e16_ds_S_secret_store); +static DEVICE_ATTR(ds_auth_ANON, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_auth_ANON_status_read, + ds28e16_ds_auth_ANON_store); +static DEVICE_ATTR(ds_auth_BDCONST, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_auth_BDCONST_status_read, + ds28e16_ds_auth_BDCONST_store); +static DEVICE_ATTR(ds_Auth_Result, S_IRUGO, ds28e16_ds_Auth_Result_status_read, + NULL); + +static struct attribute *ds_attributes[] = { + &dev_attr_ds_readstatus.attr, &dev_attr_ds_romid.attr, + &dev_attr_ds_pagenumber.attr, &dev_attr_ds_pagedata.attr, + &dev_attr_ds_time.attr, &dev_attr_ds_session_seed.attr, + &dev_attr_ds_challenge.attr, &dev_attr_ds_S_secret.attr, + &dev_attr_ds_auth_ANON.attr, &dev_attr_ds_auth_BDCONST.attr, + &dev_attr_ds_Auth_Result.attr, NULL, +}; + +static const struct attribute_group ds_attr_group = { + .attrs = ds_attributes, +}; + +static int authentic_period_ms = 5000; +#define AUTHENTIC_COUNT_MAX 5 +int retry_authentic; +static void authentic_work(struct work_struct *work) +{ + int rc; + union power_supply_propval pval = { + 0, + }; + + struct ds28e16_data *ds28e16_data = + container_of(work, struct ds28e16_data, authentic_work.work); + + rc = power_supply_get_property(ds28e16_data->verify_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, &pval); + if (pval.intval != true) { + retry_authentic++; + if (retry_authentic < AUTHENTIC_COUNT_MAX) { + ds_log("battery authentic work begin to restart, retry = %d\n", + retry_authentic); + schedule_delayed_work( + &ds28e16_data->authentic_work, + msecs_to_jiffies(authentic_period_ms)); + } + + if (retry_authentic == AUTHENTIC_COUNT_MAX) { + ds_log("authentic result is %d\n", pval.intval); + } + } else { + ds_log("authentic result is %d\n", pval.intval); + } +} + +static int ds28e16_probe(struct platform_device *pdev) +{ + int retval = 0; + struct ds28e16_data *ds28e16_data; + union power_supply_propval b_val = { + 0, + }; + + ds_log("%s entry.", __func__); + ds_dbg("platform_device is %s", pdev->name); + if (strcmp(pdev->name, "soc:maxim_ds28e16") != 0) + return -ENODEV; + + if (!pdev->dev.of_node || !of_device_is_available(pdev->dev.of_node)) + return -ENODEV; + + if (pdev->dev.of_node) { + ds28e16_data = devm_kzalloc( + &pdev->dev, sizeof(struct ds28e16_data), GFP_KERNEL); + if (!ds28e16_data) { + ds_err("Failed to allocate memory\n"); + return -ENOMEM; + } + + retval = ds28e16_parse_dt(&pdev->dev, ds28e16_data); + if (retval) { + retval = -EINVAL; + goto ds28e16_parse_dt_err; + } + } else { + ds28e16_data = pdev->dev.platform_data; + } + + if (!ds28e16_data) { + ds_err("No platform data found\n"); + return -EINVAL; + } + + ds28e16_data->dev = &pdev->dev; + ds28e16_data->pdev = pdev; + platform_set_drvdata(pdev, ds28e16_data); + INIT_DELAYED_WORK(&ds28e16_data->authentic_work, authentic_work); + + retval = verify_psy_register(ds28e16_data); + if (retval) { + ds_err("Failed to verify_psy_register, err:%d\n", retval); + goto ds28e16_psy_register_err; + } + + retval = sysfs_create_group(&ds28e16_data->dev->kobj, &ds_attr_group); + if (retval) { + ds_err("Failed to register sysfs, err:%d\n", retval); + goto ds28e16_create_group_err; + } + + retval = power_supply_get_property(ds28e16_data->verify_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, + &b_val); + if (b_val.intval != true) { + schedule_delayed_work(&ds28e16_data->authentic_work, + msecs_to_jiffies(0)); + } + return 0; + +ds28e16_create_group_err: +//sysfs_remove_groups(&ds28e16_data->dev->kobj, &(&ds_attr_group)); +ds28e16_psy_register_err: + dev_set_drvdata(ds28e16_data->dev, NULL); +ds28e16_parse_dt_err: + kfree(ds28e16_data); + return retval; +} + +static int ds28e16_remove(struct platform_device *pdev) +{ + struct ds28e16_data *ds28e16_data = platform_get_drvdata(pdev); + + verify_psy_unregister(ds28e16_data); + kfree(ds28e16_data); + return 0; +} + +static long ds28e16_dev_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + ds_log("%d, cmd: 0x%x\n", __LINE__, cmd); + return 0; +} +static int ds28e16_dev_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int ds28e16_dev_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations ds28e16_dev_fops = { + .owner = THIS_MODULE, + .open = ds28e16_dev_open, + .unlocked_ioctl = ds28e16_dev_ioctl, + .release = ds28e16_dev_release, +}; + +static const struct of_device_id ds28e16_dt_match[] = { + { .compatible = "maxim,ds28e16" }, + {}, +}; + +static struct platform_driver ds28e16_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "maxim_ds28e16", + .of_match_table = ds28e16_dt_match, + }, + .probe = ds28e16_probe, + .remove = ds28e16_remove, +}; + +static int __init ds28e16_init(void) +{ + ds_log("%s entry.", __func__); + + return platform_driver_register(&ds28e16_driver); +} + +static void __exit ds28e16_exit(void) +{ + ds_log("%s entry.", __func__); + platform_driver_unregister(&ds28e16_driver); +} + +static int __init early_parse_batt_verified_result(char *p) +{ + if (*p == '1') { + batt_verified_result_from_uefi = true; + } else { + batt_verified_result_from_uefi = false; + } + if (*(p + 1) == '1') { + batt_chip_ok_result_from_uefi = true; + } else { + batt_chip_ok_result_from_uefi = false; + } + + return 0; +} +early_param("androidboot.batt_verified_result", + early_parse_batt_verified_result); + +module_init(ds28e16_init); +module_exit(ds28e16_exit); + +MODULE_AUTHOR("xiaomi Inc."); +MODULE_DESCRIPTION("ds28e16 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/maxim/ds28e16_master.h b/drivers/power/supply/maxim/ds28e16_master.h new file mode 100644 index 000000000000..1429752b0226 --- /dev/null +++ b/drivers/power/supply/maxim/ds28e16_master.h @@ -0,0 +1,55 @@ +// DS28E16.h - Include file for DS28E16/DS28E50? +// +#ifndef __DS28E16_MASTER_H__ +#define __DS28E16_MASTER_H__ + +extern unsigned char last_result_byte; + +// Command functions +// 1-Wire ROMID commands +unsigned char crc_low_first(unsigned char *ptr, unsigned char len); +short Read_RomID(unsigned char *RomID); + +// Common Functions +unsigned short docrc16(unsigned short data); +int DS28E16_standard_cmd_flow(unsigned char *write_buf, int delay_ms, + unsigned char *read_buf, int *read_len, + int write_len); + +// Command Functions (no high level verification) +int DS28E16_cmd_readStatus( + unsigned char * + data); // 读入芯片的页é¢ä¿æŠ¤å±žæ€§ã€ä¸€ä¸ªMAN_ID字节和一个芯片版本字节，åˆè®¡6个字节 +int DS28E16_cmd_readMemory( + int pg, + unsigned char * + data); // pg=0,1,2页é¢ï¼Œä¸€æ¬¡è¯»å…¥32个字节，å‰16个字节为有效数æ®ï¼ŒåŽç»­16个字节固定为0x00或0xFF +int DS28E16_cmd_writeMemory( + int pg, unsigned char *data); // pg=0,1,2页é¢ï¼Œä¸€æ¬¡å¿…须完整写入16个字节 +int DS28E16_cmd_decrementCounter(void); // 执行此函数，完æˆ17ä½è®¡æ•°å™¨å‡1æ“作 +int DS28E16_cmd_setPageProtection(int pg, + unsigned char prot); // 设置芯片的页é¢å±žæ€§ +int DS28E16_cmd_device_disable(int op, + unsigned char *password); // 芯片自æ¯ï¼Œä¸èƒ½æ¢å¤ +int DS28E16_cmd_computeReadPageAuthentication( + int anon, int pg, unsigned char *challenge, + unsigned char * + hmac); // 器件基于会è¯å¯†ç ã€éšæœºæ•°ã€é¡µé¢æ•°æ®å’ŒROMID，返回器件的算法结果 +int DS28E16_cmd_computeS_Secret( + int anon, int bdconst, int pg, + unsigned char + *partial); // 基于主机å‘é€çš„密钥ç§å­ï¼Œå™¨ä»¶åœ¨å†…部计算出会è¯å¯†ç  + +// host functions +int AuthenticateDS28E16(int anon, int bdconst, int S_Secret_PageNum, + int PageNum, unsigned char *Challenge, + unsigned char *Secret_Seeds, unsigned char *S_Secret); + +static int ds28el16_Read_RomID_retry(unsigned char *RomID); +static int ds28el16_get_page_status_retry(unsigned char *data); +static int DS28E16_cmd_computeS_Secret_retry(int anon, int bdconst, int pg, + unsigned char *session_seed); +static int DS28E16_cmd_computeReadPageAuthentication_retry( + int anon, int pg, unsigned char *challenge, unsigned char *hmac); +static int ds28el16_get_page_data_retry(int page, unsigned char *data); +#endif diff --git a/drivers/power/supply/maxim/ds28e16_slave.c b/drivers/power/supply/maxim/ds28e16_slave.c new file mode 100644 index 000000000000..7e030c486f77 --- /dev/null +++ b/drivers/power/supply/maxim/ds28e16_slave.c @@ -0,0 +1,1959 @@ +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + ******************************************************************************* + * + * DS28E16.c - DS28E16 device module. Requires low level 1-Wire connection. + */ +#define pr_fmt(fmt) "[ds28e16] %s: " fmt, __func__ + +#include /* kfree() */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sha384_software.h" +#include "ds28e16_slave.h" +#include "onewire_gpio_slave.h" +#include "ds28e16_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ds_info pr_err +#define ds_dbg pr_err +#define ds_err pr_err +#define ds_log pr_err + +struct ds28e16_data { + struct platform_device *pdev; + struct device *dev; + + int version; + + struct power_supply *verify_psy; + struct power_supply_desc verify_psy_d; + + struct delayed_work authentic_work; +}; + +unsigned int attr_trytimes_slave = 1; + +unsigned char session_seed_slave[32] = { + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA +}; +unsigned char S_secret_slave[32] = { 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, + 0xAA, 0xAA, 0xAA, 0xAA }; +unsigned char challenge_slave[32] = { 0x00 }; +int auth_ANON_slave = 1; +int auth_BDCONST_slave = 1; +int pagenumber_slave = 1; + +// maxim define +int tm_slave = 1; +unsigned short CRC16_slave; +const short oddparity_slave[16] = { 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0 }; +unsigned char last_result_byte_slave = RESULT_SUCCESS; + +unsigned char MANID_slave[2] = { 0x00 }; + +// mi add +unsigned char flag_mi_romid_slave = 0; +unsigned char flag_mi_status_slave = 0; +unsigned char flag_mi_page0_data_slave = 0; +unsigned char flag_mi_page1_data_slave = 0; +unsigned char flag_mi_counter_slave = 0; +unsigned char flag_mi_auth_result_slave = 0; +unsigned char mi_romid_slave[8] = { 0x00 }; +unsigned char mi_status_slave[8] = { 0x00 }; +unsigned char mi_page0_data_slave[16] = { 0x00 }; +unsigned char mi_page1_data_slave[16] = { 0x00 }; +unsigned char mi_counter_slave[16] = { 0x00 }; +int mi_auth_result_slave = 0x00; + +static bool batt_verified_result_from_uefi; +static bool batt_chip_ok_result_from_uefi; + +unsigned char crc_low_first_slave(unsigned char *ptr, unsigned char len) +{ + unsigned char i; + unsigned char crc = 0x00; + + while (len--) { + crc ^= *ptr++; + for (i = 0; i < 8; ++i) { + if (crc & 0x01) + crc = (crc >> 1) ^ 0x8c; + else + crc = (crc >> 1); + } + } + + return (crc); +} + +short Read_RomID_slave(unsigned char *RomID) +{ + unsigned char i; + unsigned char crc = 0x00; + + if (flag_mi_romid_slave == 2) { + memcpy(RomID, mi_romid_slave, 8); + return DS_TRUE; + } + + if ((ow_reset_slave()) != 0) { + ds_err("Read_RomID_slave: Failed to reset ds28e16!\n"); + ow_reset_slave(); + return ERROR_NO_DEVICE; + } + + ds_dbg("Ready to write 0x33 to maxim IC!\n"); + write_byte_slave(CMD_READ_ROM); + Delay_us_slave(10); + for (i = 0; i < 8; i++) + RomID[i] = read_byte_slave(); + + ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", RomID[0], + RomID[1], RomID[2], RomID[3], RomID[4], RomID[5], RomID[6], + RomID[7]); + + crc = crc_low_first_slave(RomID, 7); + ds_dbg("crc_low_first_slave = %02x\n", crc); + + if (crc == RomID[7]) { + memcpy(mi_romid_slave, RomID, 8); + if (mi_romid_slave[0] == FAMILY_CODE && + mi_romid_slave[6] == CUSTOM_ID_MSB && + (mi_romid_slave[5] & 0xF0) == CUSTOM_ID_LSB) + flag_mi_romid_slave = 2; + return DS_TRUE; + } else { + ow_reset_slave(); + return DS_FALSE; + } +} + +unsigned short docrc16_slave(unsigned short data) +{ + data = (data ^ (CRC16_slave & 0xff)) & 0xff; + CRC16_slave >>= 8; + + if (oddparity_slave[data & 0xf] ^ oddparity_slave[data >> 4]) + CRC16_slave ^= 0xc001; + + data <<= 6; + CRC16_slave ^= data; + data <<= 1; + CRC16_slave ^= data; + + return CRC16_slave; +} + +int DS28E16_standard_cmd_flow_slave(unsigned char *write_buf, int delay_ms, + unsigned char *read_buf, int *read_len, + int write_len) +{ + unsigned char buf[128]; + int i; + int buf_len = 0; + int expected_read_len = *read_len; + + //NEW FLOW + /*'1 Wire + ''''''''''''''''''''''' + ? + ? + ?TX: Start Command + ?TX: Length Byte + ?TX: Memory Command + ?TX: Parameter, TX: Data + ?RX: CRC16_slave + ?TX: Release Byte + ? + ?RX: Dummy Byte + ?RX: Length Byte + ?RX: Result byte + ?RX: CRC16_slave + ?< wait for reset> + '''''''''''''''''''''''*/ + ds_dbg("DS28E16_standard_cmd_flow_slave start\n"); + + if ((ow_reset_slave()) != 0) { + ds_err("Failed to reset ds28e16!\n"); + ow_reset_slave(); + return ERROR_NO_DEVICE; + } + + write_byte_slave(CMD_SKIP_ROM); + + buf[buf_len++] = CMD_START; + memcpy(&buf[buf_len], write_buf, write_len); + buf_len += write_len; + for (i = 0; i < buf_len; i++) + write_byte_slave(buf[i]); + + buf[buf_len++] = read_byte_slave(); + buf[buf_len++] = read_byte_slave(); + + CRC16_slave = 0; + for (i = 0; i < buf_len; i++) + docrc16_slave(buf[i]); + + if (CRC16_slave != 0xB001) { + ow_reset_slave(); + ds_dbg("DS28E16_standard_cmd_flow_slave: crc error!\n"); + return DS_FALSE; + } + + // check for strong pull-up + if (delay_ms > 0) { + write_byte_slave(CMD_RELEASE_BYTE); + Delay_us_slave(1000 * delay_ms); + } + + read_byte_slave(); + *read_len = read_byte_slave(); + + if (expected_read_len != *read_len) { + ow_reset_slave(); + ds_dbg("DS28E16_standard_cmd_flow_slave: len error!\n"); + return DS_FALSE; + } + + buf_len = *read_len + 2; + for (i = 0; i < buf_len; i++) + buf[i] = read_byte_slave(); + + CRC16_slave = 0; + docrc16_slave(*read_len); + for (i = 0; i < buf_len; i++) + docrc16_slave(buf[i]); + + if (CRC16_slave != 0xB001) { + ow_reset_slave(); + ds_dbg("DS28E16_standard_cmd_flow_slave: crc2 error!\n"); + return DS_FALSE; + } + + memcpy(read_buf, buf, *read_len); + ds_dbg("DS28E16_standard_cmd_flow_slave success!\n"); + return DS_TRUE; +} + +//-------------------------------------------------------------------------- +/// 'Read Status' command +/// +/// @param[out] data +/// pointer to unsigned char (buffer of length 1) for page protection data +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_readStatus_slave(unsigned char *data) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int len_byte = 1; + int read_len = 7; + + if (flag_mi_status_slave) { + memcpy(data, mi_status_slave, 8); + return DS_TRUE; + } + + last_result_byte_slave = RESULT_FAIL_NONE; + /* + ? + ?TX: Read Page Protection command + ?TX: Length (SMBus) [always 1] + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Protection Data + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_READ_STATUS; + + if (DS28E16_standard_cmd_flow_slave(write_buf, + DELAY_DS28E16_EE_READ * tm_slave, + read_buf, &read_len, write_len)) { + if (read_buf[0] == RESULT_SUCCESS) { + last_result_byte_slave = read_buf[0]; + memcpy(data, &read_buf[1], 8); + flag_mi_status_slave = 1; + memcpy(mi_status_slave, data, 8); + MANID_slave[0] = data[4]; + return DS_TRUE; + } + } + + ow_reset_slave(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Read Memory' command +/// +/// @param[in] pg +/// page number to read +/// @param[out] data +/// buffer length must be at least 32 bytes to hold memory read +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_readMemory_slave(int pg, unsigned char *data) +{ + unsigned char write_buf[3]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 33; + int length_byte = 2; + unsigned char pagenum = (unsigned char)pg & 0x03; + + switch (pagenum) { + case 0x00: + if (flag_mi_page0_data_slave) { + memcpy(data, mi_page0_data_slave, 16); + return DS_TRUE; + } + break; + case 0x01: + if (flag_mi_page1_data_slave) { + memcpy(data, mi_page1_data_slave, 16); + return DS_TRUE; + } + break; + case 0x02: + if (flag_mi_counter_slave) { + memcpy(data, mi_counter_slave, 16); + return DS_TRUE; + } + break; + default: + return DS_FALSE; + } + + last_result_byte_slave = RESULT_FAIL_NONE; + + /* + ? + ?TX: Read Memory Command + ?TX: Length (SMBus) + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) + ?RX: Result byte + ?RX: Data + ? + */ + + write_buf[write_len++] = length_byte; + write_buf[write_len++] = CMD_READ_MEM; + write_buf[write_len++] = pagenum; + + ds_dbg("DS28E16_cmd_readMemory_slave write_buf:\n"); + ds_dbg("%02x %02x %02x", write_buf[0], write_buf[1], write_buf[2]); + + if (DS28E16_standard_cmd_flow_slave(write_buf, + DELAY_DS28E16_EE_READ * tm_slave, + read_buf, &read_len, write_len)) { + if (read_len == 33) { + last_result_byte_slave = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + memcpy(data, &read_buf[1], 16); + if (pagenum == 0x00) { + flag_mi_page0_data_slave = 1; + memcpy(mi_page0_data_slave, data, 16); + } + if (pagenum == 0x01) { + flag_mi_page1_data_slave = 1; + memcpy(mi_page1_data_slave, data, 16); + } + return DS_TRUE; + } else { + if (read_buf[0] == 0x55 && pagenum == 2) { + memcpy(data, &read_buf[1], 16); + flag_mi_counter_slave = 1; + memcpy(mi_counter_slave, data, 16); + return DS_TRUE; + } + } + } + } + + ow_reset_slave(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Write Memory' command +/// +/// @param[in] pg +/// page number to write +/// @param[in] data +/// buffer must be at least 32 bytes +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_writeMemory_slave(int pg, unsigned char *data) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + int len_byte = 18; + unsigned char pagenum = (unsigned char)pg & 0x03; + + last_result_byte_slave = RESULT_FAIL_NONE; + /* + ? + ?TX: Write Memory Command + ?TX: Length (SMBus) [always 33] + ?TX: Parameter + ?TX: Data + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_WRITE_MEM; + write_buf[write_len++] = pagenum; + memcpy(&write_buf[write_len], data, 16); + write_len += 16; + + if (DS28E16_standard_cmd_flow_slave(write_buf, + DELAY_DS28E16_EE_WRITE * tm_slave, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte_slave = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + if (pagenum == 0x00) { + flag_mi_page0_data_slave = 0; + memset(mi_page0_data_slave, 0x00, 16); + } + if (pagenum == 0x01) { + flag_mi_page1_data_slave = 0; + memset(mi_page0_data_slave, 0x00, 16); + } + if (pagenum == 0x02) { + flag_mi_counter_slave = 0; + memset(mi_counter_slave, 0x00, 16); + } + return DS_TRUE; + } + } + } + + ow_reset_slave(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Decrement Counter' command +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_decrementCounter_slave(void) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + + last_result_byte_slave = RESULT_FAIL_NONE; + /* + ? + ?TX: Decrement Counter Command + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = 1; + write_buf[write_len++] = CMD_DECREMENT_CNT; + + if (DS28E16_standard_cmd_flow_slave(write_buf, 50, read_buf, &read_len, + write_len)) { + if (read_len == 1) { + last_result_byte_slave = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset_slave(); + return DS_FALSE; +} + +//-------------------------------------------------------------------------- +/// 'Set Page Protection' command +/// +/// @param[in] pg +/// block to set protection +/// @param[in] prot +/// protection value to set +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_setPageProtection_slave(int page, unsigned char prot) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 1; + int len_byte = 3; + + last_result_byte_slave = RESULT_FAIL_NONE; + /* + ? + ?TX: Set Page Protection Command + ?TX: Length (SMBus) [always 2] + ?TX: Parameter + ?TX: Protection Data + ? + ? + ? + ?RX: Length (SMBus) [always 1] + ?RX: Result byte + ? + */ + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_SET_PAGE_PROT; + write_buf[write_len++] = page & 0x03; + write_buf[write_len++] = prot & 0x03; + + if (DS28E16_standard_cmd_flow_slave(write_buf, + DELAY_DS28E16_EE_WRITE * tm_slave, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte_slave = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset_slave(); + return DS_FALSE; +} + +int DS28E16_cmd_device_disable_slave(int op, unsigned char *password) +{ + unsigned char write_buf[64]; + unsigned char read_buf[64]; + int write_len = 0; + int read_len = 1; + int length_byte = 10; + + last_result_byte_slave = RESULT_FAIL_NONE; + /* + ? + ?TX: Length + ?TX: Device Disable Command + ?TX: Parameter + ? + ? + ? + ?RX: Length (SMBus) + ?RX: Result byte + ?RX: Data + ? + */ + + write_buf[write_len++] = length_byte; + write_buf[write_len++] = CMD_DISABLE_DEVICE; + write_buf[write_len++] = op & 0x0F; + memcpy(&write_buf[write_len], password, 8); + write_len += 8; + + if (DS28E16_standard_cmd_flow_slave(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + if (read_len == 1) { + last_result_byte_slave = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + } + + ow_reset_slave(); + return DS_FALSE; +} + +// -------------------------------------------------------------------------- +/// 'Compute and Read Page Authentication' command +/// +/// @param[in] anon - boolean parameter +/// @param[in] pg - Page number 2,¿¿¿? 0,page0; 1,page1; +/// @param[in] challenge_slave +/// @param[out] hmac ¿¿¿¿¿¿¿?2¿¿¿?/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_computeReadPageAuthentication_slave( + int anon, int pg, unsigned char *challenge_slave, unsigned char *hmac) +{ + unsigned char write_buf[255]; + unsigned char read_buf[255]; + int write_len = 0; + int read_len = 33; + int len_byte = 35; + + last_result_byte_slave = RESULT_FAIL_NONE; + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_COMP_READ_AUTH; + write_buf[write_len] = pg & 0x03; + if (anon) + write_buf[write_len] = (write_buf[write_len] | 0xE0); + + write_len++; + write_buf[write_len++] = 0x02; // Fixed Parameter + memcpy(&write_buf[write_len], challenge_slave, 32); // Challenge + write_len += 32; + + ds_dbg("computeReadPageAuthen:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + write_buf[0], write_buf[1], write_buf[2], write_buf[3], + write_buf[4], write_buf[5], write_buf[6], write_buf[7], + write_buf[8], write_buf[9], write_buf[10], write_buf[11], + write_buf[12], write_buf[13], write_buf[14], write_buf[15], + write_buf[16], write_buf[17], write_buf[18], write_buf[19], + write_buf[20], write_buf[21], write_buf[22], write_buf[23], + write_buf[24], write_buf[25], write_buf[26], write_buf[27], + write_buf[28], write_buf[29], write_buf[30], write_buf[31], + write_buf[32], write_buf[33], write_buf[34]); + + if (DS28E16_standard_cmd_flow_slave(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + last_result_byte_slave = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) { + ds_dbg("hmac read_buf:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + read_buf[0], read_buf[1], read_buf[2], + read_buf[3], read_buf[4], read_buf[5], + read_buf[6], read_buf[7], read_buf[8], + read_buf[9], read_buf[10], read_buf[11], + read_buf[12], read_buf[13], read_buf[14], + read_buf[15], read_buf[16], read_buf[17], + read_buf[18], read_buf[19], read_buf[20], + read_buf[21], read_buf[22], read_buf[23], + read_buf[24], read_buf[25], read_buf[26], + read_buf[27], read_buf[28], read_buf[29], + read_buf[30], read_buf[31], read_buf[32]); + memcpy(hmac, &read_buf[1], 32); + ds_dbg("hmac:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + hmac[0], hmac[1], hmac[2], hmac[3], hmac[4], + hmac[5], hmac[6], hmac[7], hmac[8], hmac[9], + hmac[10], hmac[11], hmac[12], hmac[13], hmac[14], + hmac[15], hmac[16], hmac[17], hmac[18], hmac[19], + hmac[20], hmac[21], hmac[22], hmac[23], hmac[24], + hmac[25], hmac[26], hmac[27], hmac[28], hmac[29], + hmac[30], hmac[31]); + return DS_TRUE; + } + } + + ow_reset_slave(); + return DS_FALSE; +} + +// -------------------------------------------------------------------------- +/// 'Compute Secret S' command +/// +/// @param[in] anon - boolean parameter +/// @param[in] bdconst - boolean parameter +/// @param[in] pg - Page number ¿¿ +/// @param[in] partial secret 32¿¿¿¿¿¿ +/// +/// @return +/// DS_TRUE - command successful @n +/// DS_FALSE - command failed +/// +int DS28E16_cmd_computeS_Secret_slave(int anon, int bdconst, int pg, + unsigned char *partial) +{ + unsigned char write_buf[40]; + unsigned char read_buf[40]; + int write_len = 0; + int read_len = 1; + int len_byte = 35; + int param = pg & 0x03; + + last_result_byte_slave = RESULT_FAIL_NONE; + + write_buf[write_len++] = len_byte; + write_buf[write_len++] = CMD_COMP_S_SECRET; + + if (bdconst) + param = param | 0x04; + if (anon) + param = param | 0xE0; + + write_buf[write_len] = param; + write_len++; + write_buf[write_len++] = 0x08; // Fixed Parameter + memcpy(&write_buf[write_len], partial, 32); // Partial Secret + write_len += 32; + + ds_dbg("computeS_Secret:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + write_buf[0], write_buf[1], write_buf[2], write_buf[3], + write_buf[4], write_buf[5], write_buf[6], write_buf[7], + write_buf[8], write_buf[9], write_buf[10], write_buf[11], + write_buf[12], write_buf[13], write_buf[14], write_buf[15], + write_buf[16], write_buf[17], write_buf[18], write_buf[19], + write_buf[20], write_buf[21], write_buf[22], write_buf[23], + write_buf[24], write_buf[25], write_buf[26], write_buf[27], + write_buf[28], write_buf[29], write_buf[30], write_buf[31], + write_buf[32], write_buf[33], write_buf[34]); + + if (DS28E16_standard_cmd_flow_slave(write_buf, DELAY_DS28E16_EE_WRITE, + read_buf, &read_len, write_len)) { + last_result_byte_slave = read_buf[0]; + if (read_buf[0] == RESULT_SUCCESS) + return DS_TRUE; + } + + ow_reset_slave(); + return DS_FALSE; +} + +int AuthenticateDS28E16_slave(int anon, int bdconst, int S_Secret_PageNum, + int PageNum, unsigned char *Challenge, + unsigned char *Secret_Seeds, + unsigned char *S_Secret) +{ + unsigned char PageData[32], MAC_Read_Value[32], CAL_MAC[32]; + unsigned char status_chip[16]; + unsigned char MAC_Computer_Datainput[128]; + int i = 0; + int msg_len = 0; + unsigned char flag = DS_FALSE; + + //if (flag_mi_auth_result_slave) + if (mi_auth_result_slave == DS_TRUE) + return mi_auth_result_slave; + + if (anon != ANONYMOUS) { + if (ds28el16_get_page_status_retry_slave(status_chip) == + DS_TRUE) { + MANID_slave[0] = status_chip[4]; + } else { + ow_reset_slave(); + return ERROR_R_STATUS; + } + + if (ds28el16_Read_RomID_retry_slave(mi_romid_slave) != + DS_TRUE) { + ow_reset_slave(); + return ERROR_R_ROMID; + } + } + + // DS28E16 calculate its session secret + flag = DS28E16_cmd_computeS_Secret_retry_slave( + anon, bdconst, S_Secret_PageNum, Secret_Seeds); + if (flag == DS_FALSE) { + ds_err("DS28E16_cmd_computeS_Secret_slave error"); + ow_reset_slave(); + return ERROR_S_SECRET; + } + + // DS28E16 compute its MAC based on above sessio secret + flag = DS28E16_cmd_computeReadPageAuthentication_retry_slave( + anon, PageNum, Challenge, MAC_Read_Value); + if (flag == DS_FALSE) { + ds_err("DS28E16_cmd_computeReadPageAuthentication_slave error"); + ow_reset_slave(); + return ERROR_COMPUTE_MAC; + } + + ds_dbg("%02x %02x %02x %02x", anon, bdconst, S_Secret_PageNum, PageNum); + + ds_dbg("Seeds:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + Secret_Seeds[0], Secret_Seeds[1], Secret_Seeds[2], + Secret_Seeds[3], Secret_Seeds[4], Secret_Seeds[5], + Secret_Seeds[6], Secret_Seeds[7], Secret_Seeds[8], + Secret_Seeds[9], Secret_Seeds[10], Secret_Seeds[11], + Secret_Seeds[12], Secret_Seeds[13], Secret_Seeds[14], + Secret_Seeds[15], Secret_Seeds[16], Secret_Seeds[17], + Secret_Seeds[18], Secret_Seeds[19], Secret_Seeds[20], + Secret_Seeds[21], Secret_Seeds[22], Secret_Seeds[23], + Secret_Seeds[24], Secret_Seeds[25], Secret_Seeds[26], + Secret_Seeds[27], Secret_Seeds[28], Secret_Seeds[29], + Secret_Seeds[30], Secret_Seeds[31]); + + ds_dbg("S_Secret:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + S_Secret[0], S_Secret[1], S_Secret[2], S_Secret[3], S_Secret[4], + S_Secret[5], S_Secret[6], S_Secret[7], S_Secret[8], S_Secret[9], + S_Secret[10], S_Secret[11], S_Secret[12], S_Secret[13], + S_Secret[14], S_Secret[15], S_Secret[16], S_Secret[17], + S_Secret[18], S_Secret[19], S_Secret[20], S_Secret[21], + S_Secret[22], S_Secret[23], S_Secret[24], S_Secret[25], + S_Secret[26], S_Secret[27], S_Secret[28], S_Secret[29], + S_Secret[30], S_Secret[31]); + + ds_dbg("Challenge:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + Challenge[0], Challenge[1], Challenge[2], Challenge[3], + Challenge[4], Challenge[5], Challenge[6], Challenge[7], + Challenge[8], Challenge[9], Challenge[10], Challenge[11], + Challenge[12], Challenge[13], Challenge[14], Challenge[15], + Challenge[16], Challenge[17], Challenge[18], Challenge[19], + Challenge[20], Challenge[21], Challenge[22], Challenge[23], + Challenge[24], Challenge[25], Challenge[26], Challenge[27], + Challenge[28], Challenge[29], Challenge[30], Challenge[31]); + + ds_dbg("MAC_Read_Value:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + MAC_Read_Value[0], MAC_Read_Value[1], MAC_Read_Value[2], + MAC_Read_Value[3], MAC_Read_Value[4], MAC_Read_Value[5], + MAC_Read_Value[6], MAC_Read_Value[7], MAC_Read_Value[8], + MAC_Read_Value[9], MAC_Read_Value[10], MAC_Read_Value[11], + MAC_Read_Value[12], MAC_Read_Value[13], MAC_Read_Value[14], + MAC_Read_Value[15], MAC_Read_Value[16], MAC_Read_Value[17], + MAC_Read_Value[18], MAC_Read_Value[19], MAC_Read_Value[20], + MAC_Read_Value[21], MAC_Read_Value[22], MAC_Read_Value[23], + MAC_Read_Value[24], MAC_Read_Value[25], MAC_Read_Value[26], + MAC_Read_Value[27], MAC_Read_Value[28], MAC_Read_Value[29], + MAC_Read_Value[30], MAC_Read_Value[31]); + + // read the page data + flag = ds28el16_get_page_data_retry_slave(PageNum, PageData); + if (flag != DS_TRUE) { + ds_err("DS28E16_cmd_readMemory_slave error"); + ow_reset_slave(); + return ERROR_R_PAGEDATA; + } + + // insert mi_romid_slave + if (anon != ANONYMOUS) + memcpy(MAC_Computer_Datainput, mi_romid_slave, 8); + else + memset(MAC_Computer_Datainput, 0xff, 8); + msg_len += 8; + + // insert Page Data + memcpy(&MAC_Computer_Datainput[msg_len], PageData, 16); + msg_len += 16; + memset(&MAC_Computer_Datainput[msg_len], 0x00, 16); + msg_len += 16; + + // insert Challenge + memcpy(&MAC_Computer_Datainput[msg_len], Challenge, 32); + msg_len += 32; + + // insert Bind Data Page number + MAC_Computer_Datainput[msg_len] = PageNum & 0x03; + MAC_Computer_Datainput[msg_len] = MAC_Computer_Datainput[msg_len] & + 0x03; + msg_len += 1; + + // insert MANID_slave + memcpy(&MAC_Computer_Datainput[msg_len], MANID_slave, 2); + msg_len += 2; + + // calculate the MAC + sha3_256_hmac(S_Secret, 32, MAC_Computer_Datainput, msg_len, CAL_MAC); + + ds_dbg("host data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + MAC_Computer_Datainput[0], MAC_Computer_Datainput[1], + MAC_Computer_Datainput[2], MAC_Computer_Datainput[3], + MAC_Computer_Datainput[4], MAC_Computer_Datainput[5], + MAC_Computer_Datainput[6], MAC_Computer_Datainput[7], + MAC_Computer_Datainput[8], MAC_Computer_Datainput[9], + MAC_Computer_Datainput[10], MAC_Computer_Datainput[11], + MAC_Computer_Datainput[12], MAC_Computer_Datainput[13], + MAC_Computer_Datainput[14], MAC_Computer_Datainput[15], + MAC_Computer_Datainput[16], MAC_Computer_Datainput[17], + MAC_Computer_Datainput[18], MAC_Computer_Datainput[19], + MAC_Computer_Datainput[20], MAC_Computer_Datainput[21], + MAC_Computer_Datainput[22], MAC_Computer_Datainput[23], + MAC_Computer_Datainput[24], MAC_Computer_Datainput[25], + MAC_Computer_Datainput[26], MAC_Computer_Datainput[27], + MAC_Computer_Datainput[28], MAC_Computer_Datainput[29], + MAC_Computer_Datainput[30], MAC_Computer_Datainput[31], + MAC_Computer_Datainput[32], MAC_Computer_Datainput[33], + MAC_Computer_Datainput[34], MAC_Computer_Datainput[35], + MAC_Computer_Datainput[36], MAC_Computer_Datainput[37], + MAC_Computer_Datainput[38], MAC_Computer_Datainput[39], + MAC_Computer_Datainput[40], MAC_Computer_Datainput[41], + MAC_Computer_Datainput[42], MAC_Computer_Datainput[43], + MAC_Computer_Datainput[44], MAC_Computer_Datainput[45], + MAC_Computer_Datainput[46], MAC_Computer_Datainput[47], + MAC_Computer_Datainput[48], MAC_Computer_Datainput[49], + MAC_Computer_Datainput[50], MAC_Computer_Datainput[51], + MAC_Computer_Datainput[52], MAC_Computer_Datainput[53], + MAC_Computer_Datainput[54], MAC_Computer_Datainput[55], + MAC_Computer_Datainput[56], MAC_Computer_Datainput[57], + MAC_Computer_Datainput[58], MAC_Computer_Datainput[59], + MAC_Computer_Datainput[60], MAC_Computer_Datainput[61], + MAC_Computer_Datainput[62], MAC_Computer_Datainput[63], + MAC_Computer_Datainput[64], MAC_Computer_Datainput[65], + MAC_Computer_Datainput[66], MAC_Computer_Datainput[67], + MAC_Computer_Datainput[68], MAC_Computer_Datainput[69], + MAC_Computer_Datainput[70], MAC_Computer_Datainput[71], + MAC_Computer_Datainput[72], MAC_Computer_Datainput[73], + MAC_Computer_Datainput[74], MAC_Computer_Datainput[75], + MAC_Computer_Datainput[76], MAC_Computer_Datainput[77], + MAC_Computer_Datainput[78], MAC_Computer_Datainput[79]); + + ds_dbg("host mac:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + CAL_MAC[0], CAL_MAC[1], CAL_MAC[2], CAL_MAC[3], CAL_MAC[4], + CAL_MAC[5], CAL_MAC[6], CAL_MAC[7], CAL_MAC[8], CAL_MAC[9], + CAL_MAC[10], CAL_MAC[11], CAL_MAC[12], CAL_MAC[13], CAL_MAC[14], + CAL_MAC[15], CAL_MAC[16], CAL_MAC[17], CAL_MAC[18], CAL_MAC[19], + CAL_MAC[20], CAL_MAC[21], CAL_MAC[22], CAL_MAC[23], CAL_MAC[24], + CAL_MAC[25], CAL_MAC[26], CAL_MAC[27], CAL_MAC[28], CAL_MAC[29], + CAL_MAC[30], CAL_MAC[31]); + + for (i = 0; i < 32; i++) { + if (CAL_MAC[i] != MAC_Read_Value[i]) + break; + } + + if (i != 32) { + flag_mi_auth_result_slave = 1; + mi_auth_result_slave = ERROR_UNMATCH_MAC; + // for debug + ds_dbg("hmac is not match. result=ERROR_UNMATCH_MAC\n"); + flag_mi_page1_data_slave = 0; + return ERROR_UNMATCH_MAC; + } else { + flag_mi_auth_result_slave = 1; + ds_dbg("hmac is match. result=DS_TRUE\n"); + mi_auth_result_slave = DS_TRUE; + return DS_TRUE; + } +} + +// retry interface start // +static int ds28el16_Read_RomID_retry_slave(unsigned char *RomID) +{ + int i; + unsigned char data[50]; + + for (i = 0; i < GET_ROM_ID_RETRY; i++) { + ds_info("read rom id communication start %d...\n", i); + if (DS28E16_cmd_readStatus_slave(data) == DS_TRUE) { + if (Read_RomID_slave(RomID) == DS_TRUE) + return DS_TRUE; + } + } + ds_log("ds28el16_Read_RomID_retry_slave fail\n"); + return DS_FALSE; +} + +static int ds28el16_get_page_status_retry_slave(unsigned char *data) +{ + int i; + + for (i = 0; i < GET_BLOCK_STATUS_RETRY; i++) { + ds_info("read page status communication start... %d\n", i); + + if (DS28E16_cmd_readStatus_slave(data) == DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +/* +static int ds28el16_set_page_status_retry(unsigned char page, unsigned char status) +{ + int i; + + for (i = 0; i < SET_BLOCK_STATUS_RETRY; i++) { + ds_info("set page status communication start... %d\n", i); + + if (DS28E16_cmd_setPageProtection_slave(page, status) == TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} +*/ + +static int ds28el16_get_page_data_retry_slave(int page, unsigned char *data) +{ + int i; + + if (page >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_USER_MEMORY_RETRY; i++) { + ds_dbg("read page data communication start... %d\n", i); + + if (DS28E16_cmd_readMemory_slave(page, data) == DS_TRUE) { + ds_dbg("page number is %d\n", page); + ds_dbg("page data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + data[0], data[1], data[2], data[3], data[4], + data[5], data[6], data[7], data[8], data[9], + data[10], data[11], data[12], data[13], data[14], + data[15]); + ds_dbg("flag_mi_page0_data_slave is %d\n", + flag_mi_page0_data_slave); + ds_dbg("mi_page0_data_slave data:\n"); + ds_dbg("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + mi_page0_data_slave[0], mi_page0_data_slave[1], + mi_page0_data_slave[2], mi_page0_data_slave[3], + mi_page0_data_slave[4], mi_page0_data_slave[5], + mi_page0_data_slave[6], mi_page0_data_slave[7], + mi_page0_data_slave[8], mi_page0_data_slave[9], + mi_page0_data_slave[10], mi_page0_data_slave[11], + mi_page0_data_slave[12], mi_page0_data_slave[13], + mi_page0_data_slave[14], + mi_page0_data_slave[15]); + ds_dbg("flag_mi_page1_data_slave is %d\n", + flag_mi_page1_data_slave); + ds_dbg("mi_page1_data_slave data:\n"); + ds_dbg("%%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + mi_page1_data_slave[0], mi_page1_data_slave[1], + mi_page1_data_slave[2], mi_page1_data_slave[3], + mi_page1_data_slave[4], mi_page1_data_slave[5], + mi_page1_data_slave[6], mi_page1_data_slave[7], + mi_page1_data_slave[8], mi_page1_data_slave[9], + mi_page1_data_slave[10], mi_page1_data_slave[11], + mi_page1_data_slave[12], mi_page1_data_slave[13], + mi_page1_data_slave[14], + mi_page1_data_slave[15]); + ds_dbg("flag_mi_counter_slave is %d\n", + flag_mi_counter_slave); + return DS_TRUE; + } + } + + return DS_FALSE; +} + +static int DS28E16_cmd_computeS_Secret_retry_slave(int anon, int bdconst, + int pg, + unsigned char *partial) +{ + int i; + + if (pg >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_S_SECRET_RETRY; i++) { + if (DS28E16_cmd_computeS_Secret_slave(anon, bdconst, pg, + partial) == DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +static int DS28E16_cmd_computeReadPageAuthentication_retry_slave( + int anon, int pg, unsigned char *challenge_slave, unsigned char *hmac) +{ + int i; + + if (pg >= MAX_PAGENUM) + return DS_FALSE; + + for (i = 0; i < GET_MAC_RETRY; i++) { + if (DS28E16_cmd_computeReadPageAuthentication_slave( + anon, pg, challenge_slave, hmac) == DS_TRUE) + return DS_TRUE; + } + + return DS_FALSE; +} + +// retry interface end // + +/* All power supply functions here */ + +static enum power_supply_property verify_props[] = { + POWER_SUPPLY_PROP_ROMID, + POWER_SUPPLY_PROP_DS_STATUS, + POWER_SUPPLY_PROP_PAGENUMBER, + POWER_SUPPLY_PROP_PAGEDATA, + POWER_SUPPLY_PROP_AUTHEN_RESULT, + POWER_SUPPLY_PROP_SESSION_SEED, + POWER_SUPPLY_PROP_S_SECRET, + POWER_SUPPLY_PROP_CHALLENGE, + POWER_SUPPLY_PROP_AUTH_ANON, + POWER_SUPPLY_PROP_AUTH_BDCONST, + POWER_SUPPLY_PROP_PAGE0_DATA, + POWER_SUPPLY_PROP_PAGE1_DATA, + POWER_SUPPLY_PROP_VERIFY_MODEL_NAME, + POWER_SUPPLY_PROP_CHIP_OK, +}; + +static int verify_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + int ret; + unsigned char buf[50]; + + switch (psp) { + case POWER_SUPPLY_PROP_VERIFY_MODEL_NAME: + ret = ds28el16_Read_RomID_retry_slave(mi_romid_slave); + if (ret == DS_TRUE) + val->strval = "ds28e16"; + else + val->strval = "unknown"; + break; + case POWER_SUPPLY_PROP_AUTHEN_RESULT: + if (batt_verified_result_from_uefi) { + val->intval = true; + ds_info("batt_verified_result_from_uefi is true\n"); + break; + } + ret = AuthenticateDS28E16_slave( + auth_ANON_slave, auth_BDCONST_slave, 0, + pagenumber_slave, challenge_slave, session_seed_slave, + S_secret_slave); + if (ret == DS_TRUE) + val->intval = true; + else + val->intval = false; + break; + case POWER_SUPPLY_PROP_PAGENUMBER: + val->intval = pagenumber_slave; + break; + case POWER_SUPPLY_PROP_ROMID: + ret = ds28el16_Read_RomID_retry_slave(mi_romid_slave); + memcpy(val->arrayval, mi_romid_slave, 8); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_CHIP_OK: + if (batt_chip_ok_result_from_uefi) { + val->intval = true; + ds_info("batt_chip_ok_result_from_uefi is true already\n"); + break; + } + ret = ds28el16_Read_RomID_retry_slave(mi_romid_slave); + if ((mi_romid_slave[0] == FAMILY_CODE) && + (mi_romid_slave[6] == CUSTOM_ID_MSB) && + ((mi_romid_slave[5] & 0xf0) == CUSTOM_ID_LSB)) + val->intval = true; + else + val->intval = false; + break; + case POWER_SUPPLY_PROP_DS_STATUS: + ret = ds28el16_get_page_status_retry_slave(buf); + memcpy(val->arrayval, buf, 8); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGEDATA: + ret = ds28el16_get_page_data_retry_slave(pagenumber_slave, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGE0_DATA: + ret = ds28el16_get_page_data_retry_slave(0, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_PAGE1_DATA: + ret = ds28el16_get_page_data_retry_slave(1, buf); + memcpy(val->arrayval, buf, 16); + if (ret != DS_TRUE) + return -EAGAIN; + break; + default: + ds_err("unsupported property %d\n", psp); + return -ENODATA; + } + + return 0; +} + +static int verify_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + //int ret; + //unsigned char buf[50]; + + switch (prop) { + case POWER_SUPPLY_PROP_PAGENUMBER: + pagenumber_slave = val->intval; + break; + /* + case POWER_SUPPLY_PROP_PAGEDATA: + memcpy(buf, val->arrayval, 16); + ret = DS28E16_cmd_writeMemory_slave(pagenumber_slave, buf); + if (ret != DS_TRUE) + return -EAGAIN; + break; + case POWER_SUPPLY_PROP_SESSION_SEED: + memcpy(session_seed_slave, val->arrayval, 32); + break; + case POWER_SUPPLY_PROP_S_SECRET: + memcpy(S_secret_slave, val->arrayval, 32); + break; + case POWER_SUPPLY_PROP_CHALLENGE: + memcpy(challenge_slave, val->arrayval, 32); + break; +*/ + case POWER_SUPPLY_PROP_AUTH_ANON: + auth_ANON_slave = val->intval; + break; + case POWER_SUPPLY_PROP_AUTH_BDCONST: + auth_BDCONST_slave = val->intval; + break; + default: + ds_err("unsupported property %d\n", prop); + return -ENODATA; + } + + return 0; +} + +static int verify_prop_is_writeable(struct power_supply *psy, + enum power_supply_property prop) +{ + int ret; + + switch (prop) { + case POWER_SUPPLY_PROP_PAGENUMBER: + case POWER_SUPPLY_PROP_PAGEDATA: + case POWER_SUPPLY_PROP_SESSION_SEED: + case POWER_SUPPLY_PROP_S_SECRET: + case POWER_SUPPLY_PROP_CHALLENGE: + case POWER_SUPPLY_PROP_AUTH_ANON: + case POWER_SUPPLY_PROP_AUTH_BDCONST: + ret = 1; + break; + default: + ret = 0; + break; + } + return ret; +} + +static int verify_psy_register(struct ds28e16_data *ds) +{ + struct power_supply_config verify_psy_cfg = {}; + + ds->verify_psy_d.name = "batt_verify_slave"; + ds->verify_psy_d.type = POWER_SUPPLY_TYPE_BATT_VERIFY; + ds->verify_psy_d.properties = verify_props; + ds->verify_psy_d.num_properties = ARRAY_SIZE(verify_props); + ds->verify_psy_d.get_property = verify_get_property; + ds->verify_psy_d.set_property = verify_set_property; + ds->verify_psy_d.property_is_writeable = verify_prop_is_writeable; + + verify_psy_cfg.drv_data = ds; + verify_psy_cfg.of_node = ds->dev->of_node; + verify_psy_cfg.num_supplicants = 0; + ds->verify_psy = devm_power_supply_register(ds->dev, &ds->verify_psy_d, + &verify_psy_cfg); + if (IS_ERR(ds->verify_psy)) { + ds_err("Failed to register verify_psy slave"); + return PTR_ERR(ds->verify_psy); + } + + ds_log("%s power supply register successfully\n", + ds->verify_psy_d.name); + return 0; +} + +static void verify_psy_unregister(struct ds28e16_data *ds) +{ + power_supply_unregister(ds->verify_psy); +} + +// parse dts +static int ds28e16_parse_dt(struct device *dev, struct ds28e16_data *pdata) +{ + int error, val; + struct device_node *np = dev->of_node; + + // parse version + pdata->version = 0; + error = of_property_read_u32(np, "maxim,version", &val); + if (error && (error != -EINVAL)) + ds_err("Unable to read bootloader address\n"); + else if (error != -EINVAL) + pdata->version = val; + + return 0; +} + +// read data from file +static ssize_t ds28e16_ds_Auth_Result_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + + result = AuthenticateDS28E16_slave(auth_ANON_slave, auth_BDCONST_slave, + 0, pagenumber_slave, challenge_slave, + session_seed_slave, S_secret_slave); + if (result == ERROR_R_STATUS) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_R_STATUS!\n"); + else if (result == ERROR_UNMATCH_MAC) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : MAC is not match!\n"); + else if (result == ERROR_R_ROMID) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_R_ROMID!\n"); + else if (result == ERROR_COMPUTE_MAC) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_COMPUTE_MAC!\n"); + else if (result == ERROR_S_SECRET) + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : ERROR_S_SECRET!\n"); + else if (result == DS_TRUE) + return scnprintf(buf, PAGE_SIZE, "Authenticate success!!!\n"); + else + return scnprintf(buf, PAGE_SIZE, + "Authenticate failed : other reason.\n"); +} + +static ssize_t ds28e16_ds_romid_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + short status; + unsigned char RomID[10] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes_slave; i++) { + status = ds28el16_Read_RomID_retry_slave(RomID); + + if (status == DS_TRUE) { + count++; + ds_log("Read_RomID_slave success!\n"); + } else { + ds_log("Read_RomID_slave fail!\n"); + } + ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + RomID[0], RomID[1], RomID[2], RomID[3], RomID[4], + RomID[5], RomID[6], RomID[7]); + Delay_us_slave(1000); + } + + /*ds_dbg("RomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + RomID[0], RomID[1], RomID[2], RomID[3], + RomID[4], RomID[5], RomID[6], RomID[7]); + */ + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\nRomID = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, RomID[0], RomID[1], RomID[2], RomID[3], RomID[4], + RomID[5], RomID[6], RomID[7]); +} + +static ssize_t ds28e16_ds_pagenumber_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", pagenumber_slave); +} + +static ssize_t ds28e16_ds_pagenumber_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int buf_int; + + if (sscanf(buf, "%d", &buf_int) != 1) + return -EINVAL; + + ds_dbg("new pagenumber_slave = %d\n", buf_int); + + if ((buf_int >= 0) && (buf_int <= 3)) + pagenumber_slave = buf_int; + + return count; +} + +static ssize_t ds28e16_ds_pagedata_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + unsigned char pagedata[16] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes_slave; i++) { + result = ds28el16_get_page_data_retry_slave(pagenumber_slave, + pagedata); + + if (result == DS_TRUE) { + count++; + ds_log("DS28E16_cmd_readMemory_slave success!\n"); + } else { + ds_log("DS28E16_cmd_readMemory_slave fail!\n"); + } + ds_dbg("pagedata = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + pagedata[0], pagedata[1], pagedata[2], pagedata[3], + pagedata[4], pagedata[5], pagedata[6], pagedata[7], + pagedata[8], pagedata[9], pagedata[10], pagedata[11], + pagedata[12], pagedata[13], pagedata[14], pagedata[15]); + Delay_us_slave(1000); + } + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\npagedata = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, pagedata[0], pagedata[1], pagedata[2], pagedata[3], + pagedata[4], pagedata[5], pagedata[6], pagedata[7], pagedata[8], + pagedata[9], pagedata[10], pagedata[11], pagedata[12], + pagedata[13], pagedata[14], pagedata[15]); +} + +static ssize_t ds28e16_ds_pagedata_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int result; + unsigned char pagedata[16] = { 0x00 }; + + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &pagedata[0], &pagedata[1], &pagedata[2], &pagedata[3], + &pagedata[4], &pagedata[5], &pagedata[6], &pagedata[7], + &pagedata[8], &pagedata[9], &pagedata[10], &pagedata[11], + &pagedata[12], &pagedata[13], &pagedata[14], + &pagedata[15]) != 16) + return -EINVAL; + + ds_dbg("new data = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + pagedata[0], pagedata[1], pagedata[2], pagedata[3], pagedata[4], + pagedata[5], pagedata[6], pagedata[7], pagedata[8], pagedata[9], + pagedata[10], pagedata[11], pagedata[12], pagedata[13], + pagedata[14], pagedata[15]); + + result = DS28E16_cmd_writeMemory_slave(pagenumber_slave, pagedata); + if (result == DS_TRUE) + ds_log("DS28E16_cmd_writeMemory_slave success!\n"); + else + ds_log("DS28E16_cmd_writeMemory_slave fail!\n"); + + return count; +} + +static ssize_t ds28e16_ds_time_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%d\n", attr_trytimes_slave); +} + +static ssize_t ds28e16_ds_time_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int buf_int; + + if (sscanf(buf, "%d", &buf_int) != 1) + return -EINVAL; + + ds_log("new trytimes = %d\n", buf_int); + + if (buf_int > 0) + attr_trytimes_slave = buf_int; + + return count; +} + +static ssize_t +ds28e16_ds_session_seed_status_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + session_seed_slave[0], session_seed_slave[1], + session_seed_slave[2], session_seed_slave[3], + session_seed_slave[4], session_seed_slave[5], + session_seed_slave[6], session_seed_slave[7], + session_seed_slave[8], session_seed_slave[9], + session_seed_slave[10], session_seed_slave[11], + session_seed_slave[12], session_seed_slave[13], + session_seed_slave[14], session_seed_slave[15], + session_seed_slave[16], session_seed_slave[17], + session_seed_slave[18], session_seed_slave[19], + session_seed_slave[20], session_seed_slave[21], + session_seed_slave[22], session_seed_slave[23], + session_seed_slave[24], session_seed_slave[25], + session_seed_slave[26], session_seed_slave[27], + session_seed_slave[28], session_seed_slave[29], + session_seed_slave[30], session_seed_slave[31]); +} + +static ssize_t ds28e16_ds_session_seed_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &session_seed_slave[0], &session_seed_slave[1], + &session_seed_slave[2], &session_seed_slave[3], + &session_seed_slave[4], &session_seed_slave[5], + &session_seed_slave[6], &session_seed_slave[7], + &session_seed_slave[8], &session_seed_slave[9], + &session_seed_slave[10], &session_seed_slave[11], + &session_seed_slave[12], &session_seed_slave[13], + &session_seed_slave[14], &session_seed_slave[15], + &session_seed_slave[16], &session_seed_slave[17], + &session_seed_slave[18], &session_seed_slave[19], + &session_seed_slave[20], &session_seed_slave[21], + &session_seed_slave[22], &session_seed_slave[23], + &session_seed_slave[24], &session_seed_slave[25], + &session_seed_slave[26], &session_seed_slave[27], + &session_seed_slave[28], &session_seed_slave[29], + &session_seed_slave[30], &session_seed_slave[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_challenge_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + challenge_slave[0], challenge_slave[1], challenge_slave[2], + challenge_slave[3], challenge_slave[4], challenge_slave[5], + challenge_slave[6], challenge_slave[7], challenge_slave[8], + challenge_slave[9], challenge_slave[10], challenge_slave[11], + challenge_slave[12], challenge_slave[13], challenge_slave[14], + challenge_slave[15], challenge_slave[16], challenge_slave[17], + challenge_slave[18], challenge_slave[19], challenge_slave[20], + challenge_slave[21], challenge_slave[22], challenge_slave[23], + challenge_slave[24], challenge_slave[25], challenge_slave[26], + challenge_slave[27], challenge_slave[28], challenge_slave[29], + challenge_slave[30], challenge_slave[31]); +} + +static ssize_t ds28e16_ds_challenge_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &challenge_slave[0], &challenge_slave[1], + &challenge_slave[2], &challenge_slave[3], + &challenge_slave[4], &challenge_slave[5], + &challenge_slave[6], &challenge_slave[7], + &challenge_slave[8], &challenge_slave[9], + &challenge_slave[10], &challenge_slave[11], + &challenge_slave[12], &challenge_slave[13], + &challenge_slave[14], &challenge_slave[15], + &challenge_slave[16], &challenge_slave[17], + &challenge_slave[18], &challenge_slave[19], + &challenge_slave[20], &challenge_slave[21], + &challenge_slave[22], &challenge_slave[23], + &challenge_slave[24], &challenge_slave[25], + &challenge_slave[26], &challenge_slave[27], + &challenge_slave[28], &challenge_slave[29], + &challenge_slave[30], &challenge_slave[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_S_secret_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf( + buf, PAGE_SIZE, + "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,\n", + S_secret_slave[0], S_secret_slave[1], S_secret_slave[2], + S_secret_slave[3], S_secret_slave[4], S_secret_slave[5], + S_secret_slave[6], S_secret_slave[7], S_secret_slave[8], + S_secret_slave[9], S_secret_slave[10], S_secret_slave[11], + S_secret_slave[12], S_secret_slave[13], S_secret_slave[14], + S_secret_slave[15], S_secret_slave[16], S_secret_slave[17], + S_secret_slave[18], S_secret_slave[19], S_secret_slave[20], + S_secret_slave[21], S_secret_slave[22], S_secret_slave[23], + S_secret_slave[24], S_secret_slave[25], S_secret_slave[26], + S_secret_slave[27], S_secret_slave[28], S_secret_slave[29], + S_secret_slave[30], S_secret_slave[31]); +} + +static ssize_t ds28e16_ds_S_secret_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, + "%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx,%2hhx", + &S_secret_slave[0], &S_secret_slave[1], &S_secret_slave[2], + &S_secret_slave[3], &S_secret_slave[4], &S_secret_slave[5], + &S_secret_slave[6], &S_secret_slave[7], &S_secret_slave[8], + &S_secret_slave[9], &S_secret_slave[10], &S_secret_slave[11], + &S_secret_slave[12], &S_secret_slave[13], + &S_secret_slave[14], &S_secret_slave[15], + &S_secret_slave[16], &S_secret_slave[17], + &S_secret_slave[18], &S_secret_slave[19], + &S_secret_slave[20], &S_secret_slave[21], + &S_secret_slave[22], &S_secret_slave[23], + &S_secret_slave[24], &S_secret_slave[25], + &S_secret_slave[26], &S_secret_slave[27], + &S_secret_slave[28], &S_secret_slave[29], + &S_secret_slave[30], &S_secret_slave[31]) != 32) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_auth_ANON_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", auth_ANON_slave); +} + +static ssize_t ds28e16_ds_auth_ANON_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, "%d", &auth_ANON_slave) != 1) + return -EINVAL; + + return count; +} + +static ssize_t +ds28e16_ds_auth_BDCONST_status_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%02x\n", auth_BDCONST_slave); +} + +static ssize_t ds28e16_ds_auth_BDCONST_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + if (sscanf(buf, "%d", &auth_BDCONST_slave) != 1) + return -EINVAL; + + return count; +} + +static ssize_t ds28e16_ds_readstatus_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int result; + unsigned char status[16] = { 0x00 }; + int i = 0; + int count = 0; + + for (i = 0; i < attr_trytimes_slave; i++) { + result = ds28el16_get_page_status_retry_slave(status); + + if (result == DS_TRUE) { + count++; + ds_log("DS28E16_cmd_readStatus_slave success!\n"); + } else { + ds_log("DS28E16_cmd_readStatus_slave fail!\n"); + } + ds_dbg("Status = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + status[0], status[1], status[2], status[3], status[4], + status[5], status[6], status[7], status[8], status[9], + status[10], status[11], status[12], status[13], + status[14], status[15]); + Delay_us_slave(1000); + } + ds_log("test done\nsuccess time : %d\n", count); + return scnprintf( + buf, PAGE_SIZE, + "Success = %d\nStatus = %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + count, status[0], status[1], status[2], status[3], status[4], + status[5], status[6], status[7], status[8], status[9], + status[10], status[11], status[12], status[13], status[14], + status[15]); +} + +static DEVICE_ATTR(ds_readstatus, S_IRUGO, ds28e16_ds_readstatus_status_read, + NULL); +static DEVICE_ATTR(ds_romid, S_IRUGO, ds28e16_ds_romid_status_read, NULL); +static DEVICE_ATTR(ds_pagenumber, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_pagenumber_status_read, + ds28e16_ds_pagenumber_store); +static DEVICE_ATTR(ds_pagedata, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_pagedata_status_read, ds28e16_ds_pagedata_store); +static DEVICE_ATTR(ds_time, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_time_status_read, ds28e16_ds_time_store); +static DEVICE_ATTR(ds_session_seed, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_session_seed_status_read, + ds28e16_ds_session_seed_store); +static DEVICE_ATTR(ds_challenge, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_challenge_status_read, + ds28e16_ds_challenge_store); +static DEVICE_ATTR(ds_S_secret, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_S_secret_status_read, ds28e16_ds_S_secret_store); +static DEVICE_ATTR(ds_auth_ANON, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_auth_ANON_status_read, + ds28e16_ds_auth_ANON_store); +static DEVICE_ATTR(ds_auth_BDCONST, S_IRUGO | S_IWUSR | S_IWGRP, + ds28e16_ds_auth_BDCONST_status_read, + ds28e16_ds_auth_BDCONST_store); +static DEVICE_ATTR(ds_Auth_Result, S_IRUGO, ds28e16_ds_Auth_Result_status_read, + NULL); + +static struct attribute *ds_attributes[] = { + &dev_attr_ds_readstatus.attr, &dev_attr_ds_romid.attr, + &dev_attr_ds_pagenumber.attr, &dev_attr_ds_pagedata.attr, + &dev_attr_ds_time.attr, &dev_attr_ds_session_seed.attr, + &dev_attr_ds_challenge.attr, &dev_attr_ds_S_secret.attr, + &dev_attr_ds_auth_ANON.attr, &dev_attr_ds_auth_BDCONST.attr, + &dev_attr_ds_Auth_Result.attr, NULL, +}; + +static const struct attribute_group ds_attr_group = { + .attrs = ds_attributes, +}; + +static int authentic_period_ms = 5000; +#define AUTHENTIC_COUNT_MAX 5 +static int retry_authentic; +static void authentic_work(struct work_struct *work) +{ + int rc; + union power_supply_propval pval = { + 0, + }; + + struct ds28e16_data *ds28e16_data = + container_of(work, struct ds28e16_data, authentic_work.work); + + rc = power_supply_get_property(ds28e16_data->verify_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, &pval); + if (pval.intval != true) { + retry_authentic++; + if (retry_authentic < AUTHENTIC_COUNT_MAX) { + ds_log("battery authentic work begin to restart, retry = %d\n", + retry_authentic); + schedule_delayed_work( + &ds28e16_data->authentic_work, + msecs_to_jiffies(authentic_period_ms)); + } + + if (retry_authentic == AUTHENTIC_COUNT_MAX) { + ds_log("authentic result is %d\n", pval.intval); + } + } else { + ds_log("authentic result is %d\n", pval.intval); + } +} + +static int ds28e16_probe(struct platform_device *pdev) +{ + int retval = 0; + struct ds28e16_data *ds28e16_data; + union power_supply_propval b_val = { + 0, + }; + + ds_log("%s entry.", __func__); + ds_dbg("platform_device is %s", pdev->name); + if (strcmp(pdev->name, "soc:maxim_ds28e16_slave") != 0) + return -ENODEV; + + if (!pdev->dev.of_node || !of_device_is_available(pdev->dev.of_node)) + return -ENODEV; + + if (pdev->dev.of_node) { + ds28e16_data = devm_kzalloc( + &pdev->dev, sizeof(struct ds28e16_data), GFP_KERNEL); + if (!ds28e16_data) { + ds_err("Failed to allocate memory\n"); + return -ENOMEM; + } + + retval = ds28e16_parse_dt(&pdev->dev, ds28e16_data); + if (retval) { + retval = -EINVAL; + goto ds28e16_parse_dt_err; + } + } else { + ds28e16_data = pdev->dev.platform_data; + } + + if (!ds28e16_data) { + ds_err("No platform data found\n"); + return -EINVAL; + } + + ds28e16_data->dev = &pdev->dev; + ds28e16_data->pdev = pdev; + platform_set_drvdata(pdev, ds28e16_data); + INIT_DELAYED_WORK(&ds28e16_data->authentic_work, authentic_work); + + retval = verify_psy_register(ds28e16_data); + if (retval) { + ds_err("Failed to verify_psy_register, err:%d\n", retval); + goto ds28e16_psy_register_err; + } + + retval = sysfs_create_group(&ds28e16_data->dev->kobj, &ds_attr_group); + if (retval) { + ds_err("Failed to register sysfs, err:%d\n", retval); + goto ds28e16_create_group_err; + } + + retval = power_supply_get_property(ds28e16_data->verify_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, + &b_val); + if (b_val.intval != true) { + schedule_delayed_work(&ds28e16_data->authentic_work, + msecs_to_jiffies(0)); + } + return 0; + +ds28e16_create_group_err: +//sysfs_remove_groups(&ds28e16_data->dev->kobj, &(&ds_attr_group)); +ds28e16_psy_register_err: + dev_set_drvdata(ds28e16_data->dev, NULL); +ds28e16_parse_dt_err: + kfree(ds28e16_data); + return retval; +} + +static int ds28e16_remove(struct platform_device *pdev) +{ + struct ds28e16_data *ds28e16_data = platform_get_drvdata(pdev); + + verify_psy_unregister(ds28e16_data); + kfree(ds28e16_data); + return 0; +} + +static long ds28e16_dev_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + ds_log("%d, cmd: 0x%x\n", __LINE__, cmd); + return 0; +} +static int ds28e16_dev_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int ds28e16_dev_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations ds28e16_dev_fops = { + .owner = THIS_MODULE, + .open = ds28e16_dev_open, + .unlocked_ioctl = ds28e16_dev_ioctl, + .release = ds28e16_dev_release, +}; + +static const struct of_device_id ds28e16_dt_match[] = { + { .compatible = "maxim,ds28e16_slave" }, + {}, +}; + +static struct platform_driver ds28e16_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "maxim_ds28e16_slave", + .of_match_table = ds28e16_dt_match, + }, + .probe = ds28e16_probe, + .remove = ds28e16_remove, +}; + +static int __init ds28e16_init(void) +{ + ds_log("%s entry.", __func__); + + return platform_driver_register(&ds28e16_driver); +} + +static void __exit ds28e16_exit(void) +{ + ds_log("%s entry.", __func__); + platform_driver_unregister(&ds28e16_driver); +} + +static int __init early_parse_batt_verified_result(char *p) +{ + if (*(p + 2) == '1') { + batt_verified_result_from_uefi = true; + } else { + batt_verified_result_from_uefi = false; + } + if (*(p + 3) == '1') { + batt_chip_ok_result_from_uefi = true; + } else { + batt_chip_ok_result_from_uefi = false; + } + + return 0; +} + +early_param("androidboot.batt_verified_result", + early_parse_batt_verified_result); + +module_init(ds28e16_init); +module_exit(ds28e16_exit); + +MODULE_AUTHOR("xiaomi Inc."); +MODULE_DESCRIPTION("ds28e16 driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/maxim/ds28e16_slave.h b/drivers/power/supply/maxim/ds28e16_slave.h new file mode 100644 index 000000000000..dc1cbf3a9165 --- /dev/null +++ b/drivers/power/supply/maxim/ds28e16_slave.h @@ -0,0 +1,58 @@ +// DS28E16.h - Include file for DS28E16/DS28E50? +// +#ifndef __DS28E16_SLAVE_H__ +#define __DS28E16_SLAVE_H__ + +extern unsigned char last_result_byte_slave; + +// Command functions +// 1-Wire ROMID commands +unsigned char crc_low_first_slave(unsigned char *ptr, unsigned char len); +short Read_RomID_slave(unsigned char *RomID); + +// Common Functions +unsigned short docrc16_slave(unsigned short data); +int DS28E16_standard_cmd_flow_slave(unsigned char *write_buf, int delay_ms, + unsigned char *read_buf, int *read_len, + int write_len); + +// Command Functions (no high level verification) +int DS28E16_cmd_readStatus_slave( + unsigned char * + data); // 读入芯片的页é¢ä¿æŠ¤å±žæ€§ã€ä¸€ä¸ªMAN_ID字节和一个芯片版本字节，åˆè®¡6个字节 +int DS28E16_cmd_readMemory_slave( + int pg, + unsigned char * + data); // pg=0,1,2页é¢ï¼Œä¸€æ¬¡è¯»å…¥32个字节，å‰16个字节为有效数æ®ï¼ŒåŽç»­16个字节固定为0x00或0xFF +int DS28E16_cmd_writeMemory_slave( + int pg, unsigned char *data); // pg=0,1,2页é¢ï¼Œä¸€æ¬¡å¿…须完整写入16个字节 +int DS28E16_cmd_decrementCounter_slave( + void); // 执行此函数，完æˆ17ä½è®¡æ•°å™¨å‡1æ“作 +int DS28E16_cmd_setPageProtection_slave( + int pg, unsigned char prot); // 设置芯片的页é¢å±žæ€§ +int DS28E16_cmd_device_disable_slave( + int op, unsigned char *password); // 芯片自æ¯ï¼Œä¸èƒ½æ¢å¤ +int DS28E16_cmd_computeReadPageAuthentication_slave( + int anon, int pg, unsigned char *challenge, + unsigned char * + hmac); // 器件基于会è¯å¯†ç ã€éšæœºæ•°ã€é¡µé¢æ•°æ®å’ŒROMID，返回器件的算法结果 +int DS28E16_cmd_computeS_Secret_slave( + int anon, int bdconst, int pg, + unsigned char + *partial); // 基于主机å‘é€çš„密钥ç§å­ï¼Œå™¨ä»¶åœ¨å†…部计算出会è¯å¯†ç  + +// host functions +int AuthenticateDS28E16_slave(int anon, int bdconst, int S_Secret_PageNum, + int PageNum, unsigned char *Challenge, + unsigned char *Secret_Seeds, + unsigned char *S_Secret); + +static int ds28el16_Read_RomID_retry_slave(unsigned char *RomID); +static int ds28el16_get_page_status_retry_slave(unsigned char *data); +static int DS28E16_cmd_computeS_Secret_retry_slave(int anon, int bdconst, + int pg, + unsigned char *session_seed); +static int DS28E16_cmd_computeReadPageAuthentication_retry_slave( + int anon, int pg, unsigned char *challenge, unsigned char *hmac); +static int ds28el16_get_page_data_retry_slave(int page, unsigned char *data); +#endif diff --git a/drivers/power/supply/maxim/onewire_gpio.c b/drivers/power/supply/maxim/onewire_gpio.c new file mode 100644 index 000000000000..e9ece5dc3eaa --- /dev/null +++ b/drivers/power/supply/maxim/onewire_gpio.c @@ -0,0 +1,613 @@ +/* + * Copyright (c) 2016 xiaomi Inc. + */ +#define pr_fmt(fmt) "[Onewire] %s: " fmt, __func__ + +#include /* kfree() */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ow_info pr_err +#define ow_dbg pr_err +#define ow_err pr_err +#define ow_log pr_err + +#define DRV_STRENGTH_16MA (0x7 << 6) +#define DRV_STRENGTH_4MA (0x1 << 6) +#define GPIO_OUTPUT (0x1 << 9) +#define GPIO_INPUT (0x0 << 9) +#define GPIO_PULL_UP 0x3 +#define OUTPUT_HIGH (0x1 << 1) +#define OUTPUT_LOW 0x1 + +#define ONE_WIRE_CONFIG_OUT \ + writel_relaxed(DRV_STRENGTH_16MA | GPIO_OUTPUT | GPIO_PULL_UP, \ + g_onewire_data->gpio_cfg66_reg) // OUT +#define ONE_WIRE_CONFIG_IN \ + writel_relaxed(DRV_STRENGTH_16MA | GPIO_INPUT | GPIO_PULL_UP, \ + g_onewire_data->gpio_cfg66_reg) // IN +#define ONE_WIRE_OUT_HIGH \ + writel_relaxed(OUTPUT_HIGH, g_onewire_data->gpio_in_out_reg) // OUT: 1 +#define ONE_WIRE_OUT_LOW \ + writel_relaxed(OUTPUT_LOW, g_onewire_data->gpio_in_out_reg) // OUT: 0 + +struct onewire_gpio_data { + struct platform_device *pdev; + struct device *dev; + + int ow_gpio; + + struct gpio_desc *ow_gpio_desc; + struct gpio_chip *ow_gpio_chip; + void *gpio_in_out_reg; + void *gpio_cfg66_reg; + + raw_spinlock_t lock; + + struct pinctrl *ow_gpio_pinctrl; + struct pinctrl_state *pinctrl_state_active; + struct pinctrl_state *pinctrl_state_sleep; + + int version; + + int gpio_num; + + unsigned int onewire_gpio_cfg_addr; + unsigned int onewire_gpio_level_addr; + unsigned int gpio_offset; + unsigned int gpio_reg[2]; +}; + +static struct class *onewire_class; +static int onewire_major; + +static int onewire_gpio_detected; +static struct onewire_gpio_data *g_onewire_data; + +void Delay_us(unsigned int T) +{ + udelay(T); +} +EXPORT_SYMBOL(Delay_us); + +void Delay_ns(unsigned int T) +{ + ndelay(T); +} +EXPORT_SYMBOL(Delay_ns); + +unsigned char ow_reset(void) +{ + unsigned char presence = 0xFF; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_LOW; + Delay_us(50); // 48 + ONE_WIRE_OUT_HIGH; + ONE_WIRE_CONFIG_IN; + Delay_us(7); + presence = + (unsigned char)readl_relaxed(g_onewire_data->gpio_in_out_reg) & + 0x01; // Read + Delay_us(50); + + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); + return presence; +} +EXPORT_SYMBOL(ow_reset); + +unsigned char read_bit(void) +{ + unsigned int vamm; + + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_LOW; + Delay_us(1); //// + ONE_WIRE_CONFIG_IN; + Delay_ns(500); // + vamm = readl_relaxed(g_onewire_data->gpio_in_out_reg); // Read + Delay_us(5); + ONE_WIRE_OUT_HIGH; + ONE_WIRE_CONFIG_OUT; + Delay_us(6); + return ((unsigned char)vamm & 0x01); +} + +void write_bit(char bitval) +{ + ONE_WIRE_OUT_LOW; + Delay_us(1); // + if (bitval != 0) + ONE_WIRE_OUT_HIGH; + Delay_us(10); + ONE_WIRE_OUT_HIGH; + Delay_us(6); +} + +unsigned char read_byte(void) +{ + unsigned char i; + unsigned char value = 0; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + for (i = 0; i < 8; i++) { + if (read_bit()) + value |= + 0x01 + << i; // reads byte in, one byte at a time and then shifts it left + } + + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); + return value; +} +EXPORT_SYMBOL(read_byte); + +void write_byte(char val) +{ + unsigned char i; + unsigned char temp; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + ONE_WIRE_CONFIG_OUT; + // writes byte, one bit at a time + for (i = 0; i < 8; i++) { + temp = val >> i; // shifts val right ‘i’ spaces + temp &= 0x01; // copy that bit to temp + write_bit(temp); // write bit in temp into + } + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); +} +EXPORT_SYMBOL(write_byte); + +int onewire_gpio_get_status(void) +{ + return onewire_gpio_detected; +} +EXPORT_SYMBOL(onewire_gpio_get_status); + +// parse dts +static int onewire_gpio_parse_dt(struct device *dev, + struct onewire_gpio_data *pdata) +{ + int error, val; + struct device_node *np = dev->of_node; + + // parse version + pdata->version = 0; + error = of_property_read_u32(np, "xiaomi,version", &val); + if (error && (error != -EINVAL)) + ow_err("Unable to read version\n"); + else if (error != -EINVAL) + pdata->version = val; + + // parse gpio + pdata->ow_gpio = of_get_named_gpio_flags(np, "xiaomi,ow_gpio", 0, NULL); + ow_dbg("ow_gpio: %d\n", pdata->ow_gpio); + + // parse gpio_num + pdata->gpio_num = 0; + error = of_property_read_u32(np, "xiaomi,gpio_number", &val); + if (error && (error != -EINVAL)) + ow_err("Unable to read gpio number\n"); + else if (error != -EINVAL) + pdata->gpio_num = val; + + error = of_property_read_u32_array(np, "mi,onewire-gpio-cfg-addr", + pdata->gpio_reg, 2); + if (error < 0) + ow_err("Unable to read onewire gpio addr\n"); + + pdata->onewire_gpio_cfg_addr = pdata->gpio_reg[0]; + pdata->gpio_offset = pdata->gpio_reg[1]; + pdata->onewire_gpio_level_addr = + pdata->onewire_gpio_cfg_addr + pdata->gpio_offset; + + return 0; +} + +// pinctrl init +static int onewire_gpio_pinctrl_init(struct onewire_gpio_data *onewire_data) +{ + int retval; + + onewire_data->ow_gpio_pinctrl = + devm_pinctrl_get(&onewire_data->pdev->dev); + if (IS_ERR_OR_NULL(onewire_data->ow_gpio_pinctrl)) { + retval = PTR_ERR(onewire_data->ow_gpio_pinctrl); + ow_err("Target does not use pinctrl %d\n", retval); + goto ow_gpio_err_pinctrl_get; + } + + onewire_data->pinctrl_state_active = pinctrl_lookup_state( + onewire_data->ow_gpio_pinctrl, "onewire_active"); + if (IS_ERR_OR_NULL(onewire_data->pinctrl_state_active)) { + retval = PTR_ERR(onewire_data->pinctrl_state_active); + ow_err("Can not lookup onewire_active pinstate %d\n", retval); + goto ow_gpio_err_pinctrl_lookup; + } + + onewire_data->pinctrl_state_sleep = pinctrl_lookup_state( + onewire_data->ow_gpio_pinctrl, "onewire_sleep"); + if (IS_ERR_OR_NULL(onewire_data->pinctrl_state_sleep)) { + retval = PTR_ERR(onewire_data->pinctrl_state_sleep); + ow_err("Can not lookup onewire_sleep pinstate %d\n", retval); + goto ow_gpio_err_pinctrl_lookup; + } + + return 0; + +ow_gpio_err_pinctrl_get: + devm_pinctrl_put(onewire_data->ow_gpio_pinctrl); +ow_gpio_err_pinctrl_lookup: + onewire_data->ow_gpio_pinctrl = NULL; + + return retval; +} + +// read data from file +static ssize_t onewire_gpio_ow_gpio_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int status; + struct onewire_gpio_data *onewire_data = dev_get_drvdata(dev); + + status = gpio_get_value(onewire_data->ow_gpio); + + return scnprintf(buf, PAGE_SIZE, "%d", status); +} + +// write data to file +static ssize_t onewire_gpio_ow_gpio_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned char result = 0x01; + int buf_int; + unsigned char i; + unsigned char RomID[8] = { 0 }; + + if (sscanf(buf, "%1u", &buf_int) != 1) + return -EINVAL; + + if (buf_int == 0) { + ONE_WIRE_OUT_LOW; + ow_log("gpio : OUT 0"); + } else if (buf_int == 1) { + ONE_WIRE_OUT_HIGH; + ow_log("gpio : OUT 1"); + } else if (buf_int == 2) { + ONE_WIRE_CONFIG_OUT; + ow_log("gpio : OUT"); + } else if (buf_int == 3) { + ONE_WIRE_CONFIG_IN; + ow_log("gpio : IN"); + } else if (buf_int == 4) { + result = ow_reset(); + if (result) + ow_log("ow_reset: no device.result = %02x", result); + else + ow_log("ow_reset: device exist.result = %02x", result); + } else if (buf_int == 5) { + result = read_bit(); + ow_log("read_bit: %02x", result); + } else if (buf_int == 6) { + write_bit(0x01); + ow_log("write_bit 0"); + } else if (buf_int == 7) { + result = ow_reset(); + if (result) + ow_log("ow_reset: no device.result = %02x", result); + else + ow_log("ow_reset: device exist.result = %02x", result); + + ow_dbg("Ready to write 0x33 to maxim IC!\n"); + write_byte(0x33); + + for (i = 0; i < 8; i++) + RomID[i] = read_byte(); + + ow_log("RomID = %02x%02x%02x%02x%02x%02x%02x%02x\n", RomID[0], + RomID[1], RomID[2], RomID[3], RomID[4], RomID[5], + RomID[6], RomID[7]); + } else if (buf_int == 8) { + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + + Delay_us(1000); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + + Delay_us(1000); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + } + + return count; +} + +static DEVICE_ATTR(ow_gpio, S_IRUGO | S_IWUSR | S_IWGRP, + onewire_gpio_ow_gpio_status_read, + onewire_gpio_ow_gpio_store); + +static int onewire_gpio_probe(struct platform_device *pdev) +{ + int retval = 0; + struct onewire_gpio_data *onewire_data; + struct kobject *p; + + ow_log("onewire probe entry"); + + if (!pdev->dev.of_node || !of_device_is_available(pdev->dev.of_node)) + return -ENODEV; + ow_log("lvchen1\n"); + if (pdev->dev.of_node) { + onewire_data = devm_kzalloc(&pdev->dev, + sizeof(struct onewire_gpio_data), + GFP_KERNEL); + if (!onewire_data) { + ow_err("Failed to allocate memory\n"); + return -ENOMEM; + } + ow_log("lvchen2\n"); + retval = onewire_gpio_parse_dt(&pdev->dev, onewire_data); + if (retval) { + retval = -EINVAL; + ow_log("lvchen3\n"); + goto onewire_parse_dt_err; + } + } else { + onewire_data = pdev->dev.platform_data; + } + ow_log("lvchen4\n"); + if (!onewire_data) { + ow_err("No platform data found\n"); + return -EINVAL; + } + ow_log("lvchen5\n"); + g_onewire_data = onewire_data; + onewire_data->pdev = pdev; + platform_set_drvdata(pdev, onewire_data); + + raw_spin_lock_init(&g_onewire_data->lock); + + // pinctrl init + retval = onewire_gpio_pinctrl_init(onewire_data); + if (!retval && onewire_data->ow_gpio_pinctrl) { + retval = pinctrl_select_state( + onewire_data->ow_gpio_pinctrl, + onewire_data->pinctrl_state_active); + if (retval < 0) + ow_err("Failed to select active pinstate %d\n", retval); + } + if (retval) + goto onewire_pinctrl_err; + ow_log("lvchen6\n"); + // request onewire gpio + gpio_free(onewire_data->ow_gpio); + if (gpio_is_valid(onewire_data->ow_gpio)) { + retval = gpio_request(onewire_data->ow_gpio, "onewire gpio"); + } else { + retval = -EINVAL; + } + if (retval) { + ow_err("request onewire gpio failed, retval=%d\n", retval); + goto onewire_ow_gpio_err; + } + ow_log("lvchen7\n"); + // gpio output 1 + gpio_direction_output(onewire_data->ow_gpio, 1); + + onewire_data->ow_gpio_desc = gpio_to_desc(onewire_data->ow_gpio); + onewire_data->ow_gpio_chip = gpiod_to_chip(onewire_data->ow_gpio_desc); + + onewire_data->gpio_in_out_reg = devm_ioremap( + &pdev->dev, (uint32_t)onewire_data->onewire_gpio_level_addr, + 0x4); + onewire_data->gpio_cfg66_reg = devm_ioremap( + &pdev->dev, (uint32_t)onewire_data->onewire_gpio_cfg_addr, 0x4); + ow_log("onewire_gpio_level_addr is %x; onewire_gpio_cfg_addr is %x", + (uint32_t)(onewire_data->onewire_gpio_level_addr), + (uint32_t)(onewire_data->onewire_gpio_cfg_addr)); + ow_log("onewire_data->gpio_cfg66_reg is %x; onewire_data->gpio_in_out_reg is %x", + (uint32_t)(onewire_data->gpio_cfg66_reg), + (uint32_t)(onewire_data->gpio_in_out_reg)); + + // create device node + onewire_data->dev = + device_create(onewire_class, pdev->dev.parent->parent, + onewire_major, onewire_data, "onewirectrl"); + if (IS_ERR(onewire_data->dev)) { + ow_err("Failed to create interface device\n"); + goto onewire_interface_dev_create_err; + } + ow_log("lvchen8\n"); + p = &onewire_data->dev->kobj; + + // create attr file + retval = sysfs_create_file(p, &dev_attr_ow_gpio.attr); + if (retval < 0) { + ow_err("Failed to create sysfs attr file\n"); + goto onewire_sysfs_ow_gpio_err; + } + ow_log("lvchen9\n"); + retval = sysfs_create_link(&onewire_data->dev->kobj, &pdev->dev.kobj, + "pltdev"); + if (retval) { + ow_err("Failed to create sysfs link\n"); + goto onewire_syfs_create_link_err; + } + ow_log("lvchen10\n"); + return 0; +onewire_syfs_create_link_err: + if (gpio_is_valid(onewire_data->ow_gpio)) + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_ow_gpio.attr); +onewire_sysfs_ow_gpio_err: + device_destroy(onewire_class, onewire_major); +onewire_interface_dev_create_err: + if (gpio_is_valid(onewire_data->ow_gpio)) + gpio_free(onewire_data->ow_gpio); +onewire_ow_gpio_err: +onewire_pinctrl_err: +onewire_parse_dt_err: + kfree(onewire_data); + return retval; +} + +static int onewire_gpio_remove(struct platform_device *pdev) +{ + struct onewire_gpio_data *onewire_data = platform_get_drvdata(pdev); + + if (gpio_is_valid(onewire_data->ow_gpio)) { + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_ow_gpio.attr); + gpio_free(onewire_data->ow_gpio); + } + kfree(onewire_data); + + return 0; +} + +static long onewire_dev_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + ow_dbg("%d, cmd: 0x%x\n", __LINE__, cmd); + return 0; +} +static int onewire_dev_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int onewire_dev_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations onewire_dev_fops = { + .owner = THIS_MODULE, + .open = onewire_dev_open, + .unlocked_ioctl = onewire_dev_ioctl, + .release = onewire_dev_release, +}; + +static const struct of_device_id onewire_gpio_dt_match[] = { + { .compatible = "xiaomi,onewire_gpio" }, + {}, +}; + +static struct platform_driver onewire_gpio_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "onewire_gpio", + .of_match_table = onewire_gpio_dt_match, + }, + .probe = onewire_gpio_probe, + .remove = onewire_gpio_remove, +}; + +static int __init onewire_gpio_init(void) +{ + int retval; + onewire_gpio_detected = false; + + ow_log("onewire gpio init entry."); + + onewire_class = class_create(THIS_MODULE, "onewire"); + if (IS_ERR(onewire_class)) { + ow_err("coudn't create class"); + return PTR_ERR(onewire_class); + } + + onewire_major = register_chrdev(0, "onewirectrl", &onewire_dev_fops); + if (onewire_major < 0) { + ow_err("failed to allocate char dev\n"); + retval = onewire_major; + goto class_unreg; + } + + return platform_driver_register(&onewire_gpio_driver); + +class_unreg: + class_destroy(onewire_class); + return retval; +} + +static void __exit onewire_gpio_exit(void) +{ + ow_log("onewire gpio exit entry."); + platform_driver_unregister(&onewire_gpio_driver); + + unregister_chrdev(onewire_major, "onewirectrl"); + class_destroy(onewire_class); +} + +module_init(onewire_gpio_init); +module_exit(onewire_gpio_exit); + +MODULE_AUTHOR("xiaomi Inc."); +MODULE_DESCRIPTION("onewire driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/maxim/onewire_gpio.h b/drivers/power/supply/maxim/onewire_gpio.h new file mode 100644 index 000000000000..f62e4a73fb76 --- /dev/null +++ b/drivers/power/supply/maxim/onewire_gpio.h @@ -0,0 +1,10 @@ +#ifndef __ONEWIRE_GPIO_H__ +#define __ONEWIRE_GPIO_H__ + +void Delay_us(unsigned int T); +void Delay_ns(unsigned int T); +unsigned char ow_reset(void); +unsigned char read_byte(void); +void write_byte(char val); + +#endif diff --git a/drivers/power/supply/maxim/onewire_gpio_master.c b/drivers/power/supply/maxim/onewire_gpio_master.c new file mode 100644 index 000000000000..b7c6ec642f85 --- /dev/null +++ b/drivers/power/supply/maxim/onewire_gpio_master.c @@ -0,0 +1,604 @@ +/* + * Copyright (c) 2016 xiaomi Inc. + * Copyright (C) 2021 XiaoMi, Inc. + */ +#define pr_fmt(fmt) "[Onewire] %s: " fmt, __func__ + +#include /* kfree() */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ow_info pr_err +#define ow_dbg pr_err +#define ow_err pr_err +#define ow_log pr_err + +#define DRV_STRENGTH_16MA (0x7 << 6) +#define DRV_STRENGTH_4MA (0x1 << 6) +#define GPIO_OUTPUT (0x1 << 9) +#define GPIO_INPUT (0x0 << 9) +#define GPIO_PULL_UP 0x3 +#define OUTPUT_HIGH (0x1 << 1) +#define OUTPUT_LOW 0x1 + +#define ONE_WIRE_CONFIG_OUT \ + writel_relaxed(DRV_STRENGTH_16MA | GPIO_OUTPUT | GPIO_PULL_UP, \ + g_onewire_data->gpio_cfg66_reg) // OUT +#define ONE_WIRE_CONFIG_IN \ + writel_relaxed(DRV_STRENGTH_16MA | GPIO_INPUT | GPIO_PULL_UP, \ + g_onewire_data->gpio_cfg66_reg) // IN +#define ONE_WIRE_OUT_HIGH \ + writel_relaxed(OUTPUT_HIGH, g_onewire_data->gpio_in_out_reg) // OUT: 1 +#define ONE_WIRE_OUT_LOW \ + writel_relaxed(OUTPUT_LOW, g_onewire_data->gpio_in_out_reg) // OUT: 0 + +struct onewire_gpio_data { + struct platform_device *pdev; + struct device *dev; + + int ow_gpio; + + struct gpio_desc *ow_gpio_desc; + struct gpio_chip *ow_gpio_chip; + void *gpio_in_out_reg; + void *gpio_cfg66_reg; + + raw_spinlock_t lock; + + struct pinctrl *ow_gpio_pinctrl; + struct pinctrl_state *pinctrl_state_active; + struct pinctrl_state *pinctrl_state_sleep; + + int version; + + int gpio_num; + + unsigned int onewire_gpio_cfg_addr; + unsigned int onewire_gpio_level_addr; + unsigned int gpio_offset; + unsigned int gpio_reg[2]; +}; + +static struct class *onewire_class; +static int onewire_major; + +static int onewire_gpio_detected; +static struct onewire_gpio_data *g_onewire_data; + +void Delay_us(unsigned int T) +{ + udelay(T); +} +EXPORT_SYMBOL(Delay_us); + +void Delay_ns(unsigned int T) +{ + ndelay(T); +} +EXPORT_SYMBOL(Delay_ns); + +unsigned char ow_reset(void) +{ + unsigned char presence = 0xFF; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_LOW; + Delay_us(50); // 48 + ONE_WIRE_OUT_HIGH; + ONE_WIRE_CONFIG_IN; + Delay_us(7); + presence = + (unsigned char)readl_relaxed(g_onewire_data->gpio_in_out_reg) & + 0x01; // Read + Delay_us(50); + + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); + return presence; +} +EXPORT_SYMBOL(ow_reset); + +unsigned char read_bit(void) +{ + unsigned int vamm; + + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_LOW; + Delay_us(1); //// + ONE_WIRE_CONFIG_IN; + Delay_ns(500); // + vamm = readl_relaxed(g_onewire_data->gpio_in_out_reg); // Read + Delay_us(5); + ONE_WIRE_OUT_HIGH; + ONE_WIRE_CONFIG_OUT; + Delay_us(6); + return ((unsigned char)vamm & 0x01); +} + +void write_bit(char bitval) +{ + ONE_WIRE_OUT_LOW; + Delay_us(1); // + if (bitval != 0) + ONE_WIRE_OUT_HIGH; + Delay_us(10); + ONE_WIRE_OUT_HIGH; + Delay_us(6); +} + +unsigned char read_byte(void) +{ + unsigned char i; + unsigned char value = 0; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + for (i = 0; i < 8; i++) { + if (read_bit()) + value |= + 0x01 + << i; // reads byte in, one byte at a time and then shifts it left + } + + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); + return value; +} +EXPORT_SYMBOL(read_byte); + +void write_byte(char val) +{ + unsigned char i; + unsigned char temp; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + ONE_WIRE_CONFIG_OUT; + // writes byte, one bit at a time + for (i = 0; i < 8; i++) { + temp = val >> i; // shifts val right ‘i’ spaces + temp &= 0x01; // copy that bit to temp + write_bit(temp); // write bit in temp into + } + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); +} +EXPORT_SYMBOL(write_byte); + +int onewire_gpio_get_status(void) +{ + return onewire_gpio_detected; +} +EXPORT_SYMBOL(onewire_gpio_get_status); + +// parse dts +static int onewire_gpio_parse_dt(struct device *dev, + struct onewire_gpio_data *pdata) +{ + int error, val; + struct device_node *np = dev->of_node; + + // parse version + pdata->version = 0; + error = of_property_read_u32(np, "xiaomi,version", &val); + if (error && (error != -EINVAL)) + ow_err("Unable to read version\n"); + else if (error != -EINVAL) + pdata->version = val; + + // parse gpio + pdata->ow_gpio = of_get_named_gpio_flags(np, "xiaomi,ow_gpio", 0, NULL); + ow_dbg("ow_gpio: %d\n", pdata->ow_gpio); + + // parse gpio_num + pdata->gpio_num = 0; + error = of_property_read_u32(np, "xiaomi,gpio_number", &val); + if (error && (error != -EINVAL)) + ow_err("Unable to read gpio number\n"); + else if (error != -EINVAL) + pdata->gpio_num = val; + + error = of_property_read_u32_array(np, "mi,onewire-gpio-cfg-addr", + pdata->gpio_reg, 2); + if (error < 0) + ow_err("Unable to read onewire gpio addr\n"); + + pdata->onewire_gpio_cfg_addr = pdata->gpio_reg[0]; + pdata->gpio_offset = pdata->gpio_reg[1]; + pdata->onewire_gpio_level_addr = + pdata->onewire_gpio_cfg_addr + pdata->gpio_offset; + + return 0; +} + +// pinctrl init +static int onewire_gpio_pinctrl_init(struct onewire_gpio_data *onewire_data) +{ + int retval; + + onewire_data->ow_gpio_pinctrl = + devm_pinctrl_get(&onewire_data->pdev->dev); + if (IS_ERR_OR_NULL(onewire_data->ow_gpio_pinctrl)) { + retval = PTR_ERR(onewire_data->ow_gpio_pinctrl); + ow_err("Target does not use pinctrl %d\n", retval); + goto ow_gpio_err_pinctrl_get; + } + + onewire_data->pinctrl_state_active = pinctrl_lookup_state( + onewire_data->ow_gpio_pinctrl, "onewire_active"); + if (IS_ERR_OR_NULL(onewire_data->pinctrl_state_active)) { + retval = PTR_ERR(onewire_data->pinctrl_state_active); + ow_err("Can not lookup onewire_active pinstate %d\n", retval); + goto ow_gpio_err_pinctrl_lookup; + } + + onewire_data->pinctrl_state_sleep = pinctrl_lookup_state( + onewire_data->ow_gpio_pinctrl, "onewire_sleep"); + if (IS_ERR_OR_NULL(onewire_data->pinctrl_state_sleep)) { + retval = PTR_ERR(onewire_data->pinctrl_state_sleep); + ow_err("Can not lookup onewire_sleep pinstate %d\n", retval); + goto ow_gpio_err_pinctrl_lookup; + } + + return 0; + +ow_gpio_err_pinctrl_get: + devm_pinctrl_put(onewire_data->ow_gpio_pinctrl); +ow_gpio_err_pinctrl_lookup: + onewire_data->ow_gpio_pinctrl = NULL; + + return retval; +} + +// read data from file +static ssize_t onewire_gpio_ow_gpio_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int status; + struct onewire_gpio_data *onewire_data = dev_get_drvdata(dev); + + status = gpio_get_value(onewire_data->ow_gpio); + + return scnprintf(buf, PAGE_SIZE, "%d", status); +} + +// write data to file +static ssize_t onewire_gpio_ow_gpio_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned char result = 0x01; + int buf_int; + unsigned char i; + unsigned char RomID[8] = { 0 }; + + if (sscanf(buf, "%1u", &buf_int) != 1) + return -EINVAL; + + if (buf_int == 0) { + ONE_WIRE_OUT_LOW; + ow_log("gpio : OUT 0"); + } else if (buf_int == 1) { + ONE_WIRE_OUT_HIGH; + ow_log("gpio : OUT 1"); + } else if (buf_int == 2) { + ONE_WIRE_CONFIG_OUT; + ow_log("gpio : OUT"); + } else if (buf_int == 3) { + ONE_WIRE_CONFIG_IN; + ow_log("gpio : IN"); + } else if (buf_int == 4) { + result = ow_reset(); + if (result) + ow_log("ow_reset: no device.result = %02x", result); + else + ow_log("ow_reset: device exist.result = %02x", result); + } else if (buf_int == 5) { + result = read_bit(); + ow_log("read_bit: %02x", result); + } else if (buf_int == 6) { + write_bit(0x01); + ow_log("write_bit 0"); + } else if (buf_int == 7) { + result = ow_reset(); + if (result) + ow_log("ow_reset: no device.result = %02x", result); + else + ow_log("ow_reset: device exist.result = %02x", result); + + ow_dbg("Ready to write 0x33 to maxim IC!\n"); + write_byte(0x33); + + for (i = 0; i < 8; i++) + RomID[i] = read_byte(); + + ow_log("RomID = %02x%02x%02x%02x%02x%02x%02x%02x\n", RomID[0], + RomID[1], RomID[2], RomID[3], RomID[4], RomID[5], + RomID[6], RomID[7]); + } else if (buf_int == 8) { + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + + Delay_us(1000); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + ONE_WIRE_OUT_HIGH; + Delay_us(1); + ONE_WIRE_OUT_LOW; + Delay_us(1); + + Delay_us(1000); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + ONE_WIRE_OUT_HIGH; + Delay_us(5); + ONE_WIRE_OUT_LOW; + Delay_us(5); + } + + return count; +} + +static DEVICE_ATTR(ow_gpio, S_IRUGO | S_IWUSR | S_IWGRP, + onewire_gpio_ow_gpio_status_read, + onewire_gpio_ow_gpio_store); + +static int onewire_gpio_probe(struct platform_device *pdev) +{ + int retval = 0; + struct onewire_gpio_data *onewire_data; + struct kobject *p; + + ow_log("onewire probe entry"); + + if (!pdev->dev.of_node || !of_device_is_available(pdev->dev.of_node)) + return -ENODEV; + if (pdev->dev.of_node) { + onewire_data = devm_kzalloc(&pdev->dev, + sizeof(struct onewire_gpio_data), + GFP_KERNEL); + if (!onewire_data) { + ow_err("Failed to allocate memory\n"); + return -ENOMEM; + } + retval = onewire_gpio_parse_dt(&pdev->dev, onewire_data); + if (retval) { + retval = -EINVAL; + goto onewire_parse_dt_err; + } + } else { + onewire_data = pdev->dev.platform_data; + } + if (!onewire_data) { + ow_err("No platform data found\n"); + return -EINVAL; + } + g_onewire_data = onewire_data; + onewire_data->pdev = pdev; + platform_set_drvdata(pdev, onewire_data); + + raw_spin_lock_init(&g_onewire_data->lock); + + // pinctrl init + retval = onewire_gpio_pinctrl_init(onewire_data); + if (!retval && onewire_data->ow_gpio_pinctrl) { + retval = pinctrl_select_state( + onewire_data->ow_gpio_pinctrl, + onewire_data->pinctrl_state_active); + if (retval < 0) + ow_err("Failed to select active pinstate %d\n", retval); + } + if (retval) + goto onewire_pinctrl_err; + // request onewire gpio + gpio_free(onewire_data->ow_gpio); + if (gpio_is_valid(onewire_data->ow_gpio)) { + retval = gpio_request(onewire_data->ow_gpio, "onewire gpio"); + } else { + retval = -EINVAL; + } + if (retval) { + ow_err("request onewire gpio failed, retval=%d\n", retval); + goto onewire_ow_gpio_err; + } + // gpio output 1 + gpio_direction_output(onewire_data->ow_gpio, 1); + + onewire_data->ow_gpio_desc = gpio_to_desc(onewire_data->ow_gpio); + onewire_data->ow_gpio_chip = gpiod_to_chip(onewire_data->ow_gpio_desc); + + onewire_data->gpio_in_out_reg = devm_ioremap( + &pdev->dev, (uint32_t)onewire_data->onewire_gpio_level_addr, + 0x4); + onewire_data->gpio_cfg66_reg = devm_ioremap( + &pdev->dev, (uint32_t)onewire_data->onewire_gpio_cfg_addr, 0x4); + ow_log("onewire_gpio_level_addr is %x; onewire_gpio_cfg_addr is %x", + (uint32_t)(onewire_data->onewire_gpio_level_addr), + (uint32_t)(onewire_data->onewire_gpio_cfg_addr)); + ow_log("onewire_data->gpio_cfg66_reg is %x; onewire_data->gpio_in_out_reg is %x", + (uint32_t)(onewire_data->gpio_cfg66_reg), + (uint32_t)(onewire_data->gpio_in_out_reg)); + + // create device node + onewire_data->dev = + device_create(onewire_class, pdev->dev.parent->parent, + onewire_major, onewire_data, "onewirectrl"); + if (IS_ERR(onewire_data->dev)) { + ow_err("Failed to create interface device\n"); + goto onewire_interface_dev_create_err; + } + p = &onewire_data->dev->kobj; + + // create attr file + retval = sysfs_create_file(p, &dev_attr_ow_gpio.attr); + if (retval < 0) { + ow_err("Failed to create sysfs attr file\n"); + goto onewire_sysfs_ow_gpio_err; + } + retval = sysfs_create_link(&onewire_data->dev->kobj, &pdev->dev.kobj, + "pltdev"); + if (retval) { + ow_err("Failed to create sysfs link\n"); + goto onewire_syfs_create_link_err; + } + return 0; +onewire_syfs_create_link_err: + if (gpio_is_valid(onewire_data->ow_gpio)) + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_ow_gpio.attr); +onewire_sysfs_ow_gpio_err: + device_destroy(onewire_class, onewire_major); +onewire_interface_dev_create_err: + if (gpio_is_valid(onewire_data->ow_gpio)) + gpio_free(onewire_data->ow_gpio); +onewire_ow_gpio_err: +onewire_pinctrl_err: +onewire_parse_dt_err: + kfree(onewire_data); + return retval; +} + +static int onewire_gpio_remove(struct platform_device *pdev) +{ + struct onewire_gpio_data *onewire_data = platform_get_drvdata(pdev); + + if (gpio_is_valid(onewire_data->ow_gpio)) { + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_ow_gpio.attr); + gpio_free(onewire_data->ow_gpio); + } + kfree(onewire_data); + + return 0; +} + +static long onewire_dev_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + ow_dbg("%d, cmd: 0x%x\n", __LINE__, cmd); + return 0; +} +static int onewire_dev_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int onewire_dev_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations onewire_dev_fops = { + .owner = THIS_MODULE, + .open = onewire_dev_open, + .unlocked_ioctl = onewire_dev_ioctl, + .release = onewire_dev_release, +}; + +static const struct of_device_id onewire_gpio_dt_match[] = { + { .compatible = "xiaomi,onewire_gpio" }, + {}, +}; + +static struct platform_driver onewire_gpio_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "onewire_gpio", + .of_match_table = onewire_gpio_dt_match, + }, + .probe = onewire_gpio_probe, + .remove = onewire_gpio_remove, +}; + +static int __init onewire_gpio_init(void) +{ + int retval; + onewire_gpio_detected = false; + + ow_log("onewire gpio init entry."); + + onewire_class = class_create(THIS_MODULE, "onewire"); + if (IS_ERR(onewire_class)) { + ow_err("coudn't create class"); + return PTR_ERR(onewire_class); + } + + onewire_major = register_chrdev(0, "onewirectrl", &onewire_dev_fops); + if (onewire_major < 0) { + ow_err("failed to allocate char dev\n"); + retval = onewire_major; + goto class_unreg; + } + + return platform_driver_register(&onewire_gpio_driver); + +class_unreg: + class_destroy(onewire_class); + return retval; +} + +static void __exit onewire_gpio_exit(void) +{ + ow_log("onewire gpio exit entry."); + platform_driver_unregister(&onewire_gpio_driver); + + unregister_chrdev(onewire_major, "onewirectrl"); + class_destroy(onewire_class); +} + +module_init(onewire_gpio_init); +module_exit(onewire_gpio_exit); + +MODULE_AUTHOR("xiaomi Inc."); +MODULE_DESCRIPTION("onewire driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/maxim/onewire_gpio_master.h b/drivers/power/supply/maxim/onewire_gpio_master.h new file mode 100644 index 000000000000..b08c41182f64 --- /dev/null +++ b/drivers/power/supply/maxim/onewire_gpio_master.h @@ -0,0 +1,10 @@ +#ifndef __ONEWIRE_GPIO_MASTER_H__ +#define __ONEWIRE_GPIO_MASTER_H__ + +void Delay_us(unsigned int T); +void Delay_ns(unsigned int T); +unsigned char ow_reset(void); +unsigned char read_byte(void); +void write_byte(char val); + +#endif diff --git a/drivers/power/supply/maxim/onewire_gpio_slave.c b/drivers/power/supply/maxim/onewire_gpio_slave.c new file mode 100644 index 000000000000..4982d10f1b18 --- /dev/null +++ b/drivers/power/supply/maxim/onewire_gpio_slave.c @@ -0,0 +1,611 @@ +/* + * Copyright (c) 2016 xiaomi Inc. + * Copyright (C) 2021 XiaoMi, Inc. + */ +#define pr_fmt(fmt) "[Onewire] %s: " fmt, __func__ + +#include /* kfree() */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ow_info pr_err +#define ow_dbg pr_err +#define ow_err pr_err +#define ow_log pr_err + +#define DRV_STRENGTH_16MA (0x7 << 6) +#define DRV_STRENGTH_4MA (0x1 << 6) +#define GPIO_OUTPUT (0x1 << 9) +#define GPIO_INPUT (0x0 << 9) +#define GPIO_PULL_UP 0x3 +#define OUTPUT_HIGH (0x1 << 1) +#define OUTPUT_LOW 0x1 + +#define ONE_WIRE_CONFIG_OUT \ + writel_relaxed(DRV_STRENGTH_16MA | GPIO_OUTPUT | GPIO_PULL_UP, \ + g_onewire_data->gpio_cfg66_reg) // OUT +#define ONE_WIRE_CONFIG_IN \ + writel_relaxed(DRV_STRENGTH_16MA | GPIO_INPUT | GPIO_PULL_UP, \ + g_onewire_data->gpio_cfg66_reg) // IN +#define ONE_WIRE_OUT_HIGH \ + writel_relaxed(OUTPUT_HIGH, g_onewire_data->gpio_in_out_reg) // OUT: 1 +#define ONE_WIRE_OUT_LOW \ + writel_relaxed(OUTPUT_LOW, g_onewire_data->gpio_in_out_reg) // OUT: 0 + +struct onewire_gpio_data { + struct platform_device *pdev; + struct device *dev; + + int ow_gpio; + + struct gpio_desc *ow_gpio_desc; + struct gpio_chip *ow_gpio_chip; + void *gpio_in_out_reg; + void *gpio_cfg66_reg; + + raw_spinlock_t lock; + + struct pinctrl *ow_gpio_pinctrl; + struct pinctrl_state *pinctrl_state_active; + struct pinctrl_state *pinctrl_state_sleep; + + int version; + + int gpio_num; + + unsigned int onewire_gpio_cfg_addr; + unsigned int onewire_gpio_level_addr; + unsigned int gpio_offset; + unsigned int gpio_reg[2]; +}; + +static struct class *onewire_class; +static int onewire_major; + +static int onewire_gpio_detected; +static struct onewire_gpio_data *g_onewire_data; + +void Delay_us_slave(unsigned int T) +{ + udelay(T); +} +EXPORT_SYMBOL(Delay_us_slave); + +void Delay_ns_slave(unsigned int T) +{ + ndelay(T); +} +EXPORT_SYMBOL(Delay_ns_slave); + +unsigned char ow_reset_slave(void) +{ + unsigned char presence = 0xFF; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_LOW; + Delay_us_slave(50); // 48 + ONE_WIRE_OUT_HIGH; + ONE_WIRE_CONFIG_IN; + Delay_us_slave(7); + presence = + (unsigned char)readl_relaxed(g_onewire_data->gpio_in_out_reg) & + 0x01; // Read + Delay_us_slave(50); + + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); + return presence; +} +EXPORT_SYMBOL(ow_reset_slave); + +static unsigned char read_bit(void) +{ + unsigned int vamm; + + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_LOW; + Delay_us_slave(1); //// + ONE_WIRE_CONFIG_IN; + Delay_ns_slave(500); // + vamm = readl_relaxed(g_onewire_data->gpio_in_out_reg); // Read + Delay_us_slave(5); + ONE_WIRE_OUT_HIGH; + ONE_WIRE_CONFIG_OUT; + Delay_us_slave(6); + return ((unsigned char)vamm & 0x01); +} + +static void write_bit(char bitval) +{ + ONE_WIRE_OUT_LOW; + Delay_us_slave(1); // + if (bitval != 0) + ONE_WIRE_OUT_HIGH; + Delay_us_slave(10); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(6); +} + +unsigned char read_byte_slave(void) +{ + unsigned char i; + unsigned char value = 0; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + for (i = 0; i < 8; i++) { + if (read_bit()) + value |= + 0x01 + << i; // reads byte in, one byte at a time and then shifts it left + } + + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); + return value; +} +EXPORT_SYMBOL(read_byte_slave); + +void write_byte_slave(char val) +{ + unsigned char i; + unsigned char temp; + unsigned long flags; + + raw_spin_lock_irqsave(&g_onewire_data->lock, flags); + ONE_WIRE_CONFIG_OUT; + // writes byte, one bit at a time + for (i = 0; i < 8; i++) { + temp = val >> i; // shifts val right ‘i’ spaces + temp &= 0x01; // copy that bit to temp + write_bit(temp); // write bit in temp into + } + raw_spin_unlock_irqrestore(&g_onewire_data->lock, flags); +} +EXPORT_SYMBOL(write_byte_slave); + +int onewire_gpio_get_status_slave(void) +{ + return onewire_gpio_detected; +} +EXPORT_SYMBOL(onewire_gpio_get_status_slave); + +// parse dts +static int onewire_gpio_parse_dt(struct device *dev, + struct onewire_gpio_data *pdata) +{ + int error, val; + struct device_node *np = dev->of_node; + + // parse version + pdata->version = 0; + error = of_property_read_u32(np, "xiaomi,version", &val); + if (error && (error != -EINVAL)) + ow_err("Unable to read version\n"); + else if (error != -EINVAL) + pdata->version = val; + + // parse gpio + pdata->ow_gpio = of_get_named_gpio_flags(np, "xiaomi,ow_gpio", 0, NULL); + ow_dbg("ow_gpio: %d\n", pdata->ow_gpio); + + // parse gpio_num + pdata->gpio_num = 0; + error = of_property_read_u32(np, "xiaomi,gpio_number", &val); + if (error && (error != -EINVAL)) + ow_err("Unable to read gpio number\n"); + else if (error != -EINVAL) + pdata->gpio_num = val; + + error = of_property_read_u32_array(np, "mi,onewire-gpio-cfg-addr", + pdata->gpio_reg, 2); + if (error < 0) + ow_err("Unable to read onewire gpio addr\n"); + + pdata->onewire_gpio_cfg_addr = pdata->gpio_reg[0]; + pdata->gpio_offset = pdata->gpio_reg[1]; + pdata->onewire_gpio_level_addr = + pdata->onewire_gpio_cfg_addr + pdata->gpio_offset; + + return 0; +} + +// pinctrl init +static int onewire_gpio_pinctrl_init(struct onewire_gpio_data *onewire_data) +{ + int retval; + + onewire_data->ow_gpio_pinctrl = + devm_pinctrl_get(&onewire_data->pdev->dev); + if (IS_ERR_OR_NULL(onewire_data->ow_gpio_pinctrl)) { + retval = PTR_ERR(onewire_data->ow_gpio_pinctrl); + ow_err("Target does not use pinctrl %d\n", retval); + goto ow_gpio_err_pinctrl_get; + } + + onewire_data->pinctrl_state_active = pinctrl_lookup_state( + onewire_data->ow_gpio_pinctrl, "onewire_slave_active"); + if (IS_ERR_OR_NULL(onewire_data->pinctrl_state_active)) { + retval = PTR_ERR(onewire_data->pinctrl_state_active); + ow_err("Can not lookup onewire_slave_active pinstate %d\n", + retval); + goto ow_gpio_err_pinctrl_lookup; + } + + onewire_data->pinctrl_state_sleep = pinctrl_lookup_state( + onewire_data->ow_gpio_pinctrl, "onewire_slave_sleep"); + if (IS_ERR_OR_NULL(onewire_data->pinctrl_state_sleep)) { + retval = PTR_ERR(onewire_data->pinctrl_state_sleep); + ow_err("Can not lookup onewire_slave_sleep pinstate %d\n", + retval); + goto ow_gpio_err_pinctrl_lookup; + } + + return 0; + +ow_gpio_err_pinctrl_get: + devm_pinctrl_put(onewire_data->ow_gpio_pinctrl); +ow_gpio_err_pinctrl_lookup: + onewire_data->ow_gpio_pinctrl = NULL; + + return retval; +} + +// read data from file +static ssize_t onewire_gpio_ow_gpio_status_read(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int status; + struct onewire_gpio_data *onewire_data = dev_get_drvdata(dev); + + status = gpio_get_value(onewire_data->ow_gpio); + + return scnprintf(buf, PAGE_SIZE, "%d", status); +} + +// write data to file +static ssize_t onewire_gpio_ow_gpio_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned char result = 0x01; + int buf_int; + unsigned char i; + unsigned char RomID[8] = { 0 }; + + if (sscanf(buf, "%1u", &buf_int) != 1) + return -EINVAL; + + if (buf_int == 0) { + ONE_WIRE_OUT_LOW; + ow_log("gpio : OUT 0"); + } else if (buf_int == 1) { + ONE_WIRE_OUT_HIGH; + ow_log("gpio : OUT 1"); + } else if (buf_int == 2) { + ONE_WIRE_CONFIG_OUT; + ow_log("gpio : OUT"); + } else if (buf_int == 3) { + ONE_WIRE_CONFIG_IN; + ow_log("gpio : IN"); + } else if (buf_int == 4) { + result = ow_reset_slave(); + if (result) + ow_log("ow_reset_slave: no device.result = %02x", + result); + else + ow_log("ow_reset_slave: device exist.result = %02x", + result); + } else if (buf_int == 5) { + result = read_bit(); + ow_log("read_bit: %02x", result); + } else if (buf_int == 6) { + write_bit(0x01); + ow_log("write_bit 0"); + } else if (buf_int == 7) { + result = ow_reset_slave(); + if (result) + ow_log("ow_reset_slave: no device.result = %02x", + result); + else + ow_log("ow_reset_slave: device exist.result = %02x", + result); + + ow_dbg("Ready to write 0x33 to maxim IC!\n"); + write_byte_slave(0x33); + + for (i = 0; i < 8; i++) + RomID[i] = read_byte_slave(); + + ow_log("RomID = %02x%02x%02x%02x%02x%02x%02x%02x\n", RomID[0], + RomID[1], RomID[2], RomID[3], RomID[4], RomID[5], + RomID[6], RomID[7]); + } else if (buf_int == 8) { + ONE_WIRE_CONFIG_OUT; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + ONE_WIRE_OUT_HIGH; + ONE_WIRE_OUT_LOW; + + Delay_us_slave(1000); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(1); + ONE_WIRE_OUT_LOW; + Delay_us_slave(1); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(1); + ONE_WIRE_OUT_LOW; + Delay_us_slave(1); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(1); + ONE_WIRE_OUT_LOW; + Delay_us_slave(1); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(1); + ONE_WIRE_OUT_LOW; + Delay_us_slave(1); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(1); + ONE_WIRE_OUT_LOW; + Delay_us_slave(1); + + Delay_us_slave(1000); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(5); + ONE_WIRE_OUT_LOW; + Delay_us_slave(5); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(5); + ONE_WIRE_OUT_LOW; + Delay_us_slave(5); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(5); + ONE_WIRE_OUT_LOW; + Delay_us_slave(5); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(5); + ONE_WIRE_OUT_LOW; + Delay_us_slave(5); + ONE_WIRE_OUT_HIGH; + Delay_us_slave(5); + ONE_WIRE_OUT_LOW; + Delay_us_slave(5); + } + + return count; +} + +static DEVICE_ATTR(ow_gpio, S_IRUGO | S_IWUSR | S_IWGRP, + onewire_gpio_ow_gpio_status_read, + onewire_gpio_ow_gpio_store); + +static int onewire_gpio_probe(struct platform_device *pdev) +{ + int retval = 0; + struct onewire_gpio_data *onewire_data; + struct kobject *p; + + ow_log("onewire probe entry"); + + if (!pdev->dev.of_node || !of_device_is_available(pdev->dev.of_node)) + return -ENODEV; + if (pdev->dev.of_node) { + onewire_data = devm_kzalloc(&pdev->dev, + sizeof(struct onewire_gpio_data), + GFP_KERNEL); + if (!onewire_data) { + ow_err("Failed to allocate memory\n"); + return -ENOMEM; + } + retval = onewire_gpio_parse_dt(&pdev->dev, onewire_data); + if (retval) { + retval = -EINVAL; + goto onewire_parse_dt_err; + } + } else { + onewire_data = pdev->dev.platform_data; + } + if (!onewire_data) { + ow_err("No platform data found\n"); + return -EINVAL; + } + g_onewire_data = onewire_data; + onewire_data->pdev = pdev; + platform_set_drvdata(pdev, onewire_data); + + raw_spin_lock_init(&g_onewire_data->lock); + + // pinctrl init + retval = onewire_gpio_pinctrl_init(onewire_data); + if (!retval && onewire_data->ow_gpio_pinctrl) { + retval = pinctrl_select_state( + onewire_data->ow_gpio_pinctrl, + onewire_data->pinctrl_state_active); + if (retval < 0) + ow_err("Failed to select active pinstate %d\n", retval); + } + if (retval) + goto onewire_pinctrl_err; + // request onewire gpio + gpio_free(onewire_data->ow_gpio); + if (gpio_is_valid(onewire_data->ow_gpio)) { + retval = gpio_request(onewire_data->ow_gpio, "onewire gpio"); + } else { + retval = -EINVAL; + } + if (retval) { + ow_err("request onewire gpio failed, retval=%d\n", retval); + goto onewire_ow_gpio_err; + } + // gpio output 1 + gpio_direction_output(onewire_data->ow_gpio, 1); + + onewire_data->ow_gpio_desc = gpio_to_desc(onewire_data->ow_gpio); + onewire_data->ow_gpio_chip = gpiod_to_chip(onewire_data->ow_gpio_desc); + + onewire_data->gpio_in_out_reg = devm_ioremap( + &pdev->dev, (uint32_t)onewire_data->onewire_gpio_level_addr, + 0x4); + onewire_data->gpio_cfg66_reg = devm_ioremap( + &pdev->dev, (uint32_t)onewire_data->onewire_gpio_cfg_addr, 0x4); + ow_log("onewire_gpio_level_addr is %x; onewire_gpio_cfg_addr is %x", + (uint32_t)(onewire_data->onewire_gpio_level_addr), + (uint32_t)(onewire_data->onewire_gpio_cfg_addr)); + ow_log("onewire_data->gpio_cfg66_reg is %x; onewire_data->gpio_in_out_reg is %x", + (uint32_t)(onewire_data->gpio_cfg66_reg), + (uint32_t)(onewire_data->gpio_in_out_reg)); + + // create device node + onewire_data->dev = + device_create(onewire_class, pdev->dev.parent->parent, + onewire_major, onewire_data, "onewireslavectrl"); + if (IS_ERR(onewire_data->dev)) { + ow_err("Failed to create interface device\n"); + goto onewire_interface_dev_create_err; + } + p = &onewire_data->dev->kobj; + + // create attr file + retval = sysfs_create_file(p, &dev_attr_ow_gpio.attr); + if (retval < 0) { + ow_err("Failed to create sysfs attr file\n"); + goto onewire_sysfs_ow_gpio_err; + } + retval = sysfs_create_link(&onewire_data->dev->kobj, &pdev->dev.kobj, + "pltdev"); + if (retval) { + ow_err("Failed to create sysfs link\n"); + goto onewire_syfs_create_link_err; + } + return 0; +onewire_syfs_create_link_err: + if (gpio_is_valid(onewire_data->ow_gpio)) + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_ow_gpio.attr); +onewire_sysfs_ow_gpio_err: + device_destroy(onewire_class, onewire_major); +onewire_interface_dev_create_err: + if (gpio_is_valid(onewire_data->ow_gpio)) + gpio_free(onewire_data->ow_gpio); +onewire_ow_gpio_err: +onewire_pinctrl_err: +onewire_parse_dt_err: + kfree(onewire_data); + return retval; +} + +static int onewire_gpio_remove(struct platform_device *pdev) +{ + struct onewire_gpio_data *onewire_data = platform_get_drvdata(pdev); + + if (gpio_is_valid(onewire_data->ow_gpio)) { + sysfs_remove_file(&pdev->dev.kobj, &dev_attr_ow_gpio.attr); + gpio_free(onewire_data->ow_gpio); + } + kfree(onewire_data); + + return 0; +} + +static long onewire_dev_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + ow_dbg("%d, cmd: 0x%x\n", __LINE__, cmd); + return 0; +} +static int onewire_dev_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int onewire_dev_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations onewire_dev_fops = { + .owner = THIS_MODULE, + .open = onewire_dev_open, + .unlocked_ioctl = onewire_dev_ioctl, + .release = onewire_dev_release, +}; + +static const struct of_device_id onewire_gpio_dt_match[] = { + { .compatible = "xiaomi,onewire_slave_gpio" }, + {}, +}; + +static struct platform_driver onewire_gpio_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "onewire_slave_gpio", + .of_match_table = onewire_gpio_dt_match, + }, + .probe = onewire_gpio_probe, + .remove = onewire_gpio_remove, +}; + +static int __init onewire_gpio_init(void) +{ + int retval; + onewire_gpio_detected = false; + + ow_log("onewire gpio init entry."); + + onewire_class = class_create(THIS_MODULE, "onewire_slave"); + if (IS_ERR(onewire_class)) { + ow_err("coudn't create class"); + return PTR_ERR(onewire_class); + } + + onewire_major = + register_chrdev(0, "onewireslavectrl", &onewire_dev_fops); + if (onewire_major < 0) { + ow_err("failed to allocate char dev\n"); + retval = onewire_major; + goto class_unreg; + } + + return platform_driver_register(&onewire_gpio_driver); + +class_unreg: + class_destroy(onewire_class); + return retval; +} + +static void __exit onewire_gpio_exit(void) +{ + ow_log("onewire gpio exit entry."); + platform_driver_unregister(&onewire_gpio_driver); + + unregister_chrdev(onewire_major, "onewireslavectrl"); + class_destroy(onewire_class); +} + +module_init(onewire_gpio_init); +module_exit(onewire_gpio_exit); + +MODULE_AUTHOR("xiaomi Inc."); +MODULE_DESCRIPTION("onewire driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/maxim/onewire_gpio_slave.h b/drivers/power/supply/maxim/onewire_gpio_slave.h new file mode 100644 index 000000000000..c653b92fe1e6 --- /dev/null +++ b/drivers/power/supply/maxim/onewire_gpio_slave.h @@ -0,0 +1,10 @@ +#ifndef __ONEWIRE_GPIO_SLAVE_H__ +#define __ONEWIRE_GPIO_SLAVE_H__ + +void Delay_us_slave(unsigned int T); +void Delay_ns_slave(unsigned int T); +unsigned char ow_reset_slave(void); +unsigned char read_byte_slave(void); +void write_byte_slave(char val); + +#endif diff --git a/drivers/power/supply/maxim/sha384_software.c b/drivers/power/supply/maxim/sha384_software.c new file mode 100644 index 000000000000..c4766fa028cf --- /dev/null +++ b/drivers/power/supply/maxim/sha384_software.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +******************************************************************************* +*/ +// SHA3_HMAC - HMAC using SHA3-256 +#include "ucl_sha3.h" +#include +#define SHA3_256_HMAC +#include "sha384_software.h" + +//--------------------------------------------------------------------------- +/// Compute HMAC using SHA3-256. +/// +/// @param[in] key +/// buffer for key +/// @param[in] ken_len +/// length of key +/// @param[in] message +/// buffer for message +/// @param[in] msg_len +/// length of message +/// @param[out] mac +/// 32 byte output mac +/// +/// Restrictions: +/// Key length limited to 32 bytes. +/// Message Length is limited to 512 bytes. +/// +/// @return +/// TRUE - command successful @n +/// FALSE - command failed +/// +int sha3_256_hmac(unsigned char *key, int key_len, unsigned char *message, + int msg_len, unsigned char *mac) +{ + int i; + unsigned char thash[256]; + unsigned char tmac[256]; + unsigned char cat_input_thash[1024]; + unsigned char cat_input_final[1024]; + + int blocksize = 136; + int hashsize = 32; + unsigned char opad[136]; + unsigned char ipad[136]; + + memset(opad, 0x5C, blocksize); + memset(ipad, 0x36, blocksize); + + // Check to see if key is larger then blocksize + if (key_len > blocksize) + return 0; // Not supported + + // check for blocks too big + if (msg_len > 512) + return 0; + + // Loop through bytes of ipad/opad and XOR with key + for (i = 0; i < key_len; i++) { + // XOR ipad with key + ipad[i] ^= key[i]; + // XOR opad with key + opad[i] ^= key[i]; + } + + // thash = hash(ipad || message) + memcpy(cat_input_thash, ipad, blocksize); + memcpy(&cat_input_thash[blocksize], message, msg_len); + + ucl_sha3_256(thash, cat_input_thash, blocksize + msg_len); + + // return hash(opad || thash) + memcpy(cat_input_final, opad, blocksize); + memcpy(&cat_input_final[blocksize], thash, hashsize); + + ucl_sha3_256(tmac, cat_input_final, blocksize + hashsize); + + memcpy(mac, tmac, hashsize); + + return 1; +} diff --git a/drivers/power/supply/maxim/sha384_software.h b/drivers/power/supply/maxim/sha384_software.h new file mode 100644 index 000000000000..54986da60a40 --- /dev/null +++ b/drivers/power/supply/maxim/sha384_software.h @@ -0,0 +1,30 @@ +//------------Copyright (C) 2017 Maxim Integrated Products -------------- +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL MAXIM INTEGRATED PRODCUTS BE LIABLE FOR ANY CLAIM, DAMAGES +// OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +// OTHER DEALINGS IN THE SOFTWARE. +// +// Except as contained in this notice, the name of Maxim Integrated Products +// shall not be used except as stated in the Maxim Integrated Products +// Branding Policy. +// --------------------------------------------------------------------------- +// +// sha3_hmac.h - Include file for sha3_hmac module. +// + +int sha3_256_hmac(unsigned char *key, int key_len, unsigned char *message, + int msg_len, unsigned char *mac); diff --git a/drivers/power/supply/maxim/ucl_hash.h b/drivers/power/supply/maxim/ucl_hash.h new file mode 100644 index 000000000000..9a92ef044c15 --- /dev/null +++ b/drivers/power/supply/maxim/ucl_hash.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* Copyright (C) 2015 Maxim Integrated Products, Inc., All rights Reserved. +* * This software is protected by copyright laws of the United States and +* of foreign countries. This material may also be protected by patent laws +* and technology transfer regulations of the United States and of foreign +* countries. This software is furnished under a license agreement and/or a +* nondisclosure agreement and may only be used or reproduced in accordance +* with the terms of those agreements. Dissemination of this information to +* any party or parties not specified in the license agreement and/or +* nondisclosure agreement is expressly prohibited. +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +* Module Name: UCL +* Description: hash definition +* Filename: ucl_hash.h +* Author: LSL +* Compiler: gcc +* + ******************************************************************************* + */ +//these defines are used to select or not hash functions +//useful on platforms with limited resources + +#ifndef _UCL_HASH_H +#define _UCL_HASH_H + +#define HASH_SHA256 +#define HASH_SIA256 +#define HASH_SHA3 + +#define MAX_HASH_FUNCTIONS 3 + +extern int hash_size[MAX_HASH_FUNCTIONS]; +#endif //UCL_HASH diff --git a/drivers/power/supply/maxim/ucl_retdefs.h b/drivers/power/supply/maxim/ucl_retdefs.h new file mode 100644 index 000000000000..0483ecda112c --- /dev/null +++ b/drivers/power/supply/maxim/ucl_retdefs.h @@ -0,0 +1,237 @@ +/******************************************************************************* +* Copyright (C) 2015 Maxim Integrated Products, Inc., All rights Reserved. +* * This software is protected by copyright laws of the United States and +* of foreign countries. This material may also be protected by patent laws +* and technology transfer regulations of the United States and of foreign +* countries. This software is furnished under a license agreement and/or a +* nondisclosure agreement and may only be used or reproduced in accordance +* with the terms of those agreements. Dissemination of this information to +* any party or parties not specified in the license agreement and/or +* nondisclosure agreement is expressly prohibited. +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +* Module Name: UCL +* Description: return definition +* Filename: ucl_retdefs.h +* Author: LSL +* Compiler: gcc +* + ******************************************************************************* + */ +#ifndef UCL_RETDEFS_H_ +#define UCL_RETDEFS_H_ + +/** @file ucl_retdefs.h + * @defgroup UCL_RETURN Definitions of returns + * + * @par Header: + * @link ucl_retdefs.h ucl_retdefs.h @endlink + * + * @ingroup UCL_DEFINITIONS + */ + +/** Carry. + * @ingroup UCL_RETURN + */ +#define UCL_CARRY 1 + +/** True. + * @ingroup UCL_RETURN + */ +#define UCL_TRUE 1 +/** False. + * @ingroup UCL_RETURN + */ +#define UCL_FALSE 0 + +/* ========================================================================== */ + +/** No error occured. + * @ingroup UCL_RETURN + */ +#define UCL_OK 0 +/** Generic Error. + * @ingroup UCL_RETURN + */ +#define UCL_ERROR -1 +/** Not a failure but no operation was performed. + * @ingroup UCL_RETURN + */ +#define UCL_NOP -2 +/** Invalid cipher specified. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_CIPHER -3 +/** Invalid hash specified. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_HASH -4 +/** Generic invalid argument. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_ARG -5 +/** Invalid argument input. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_INPUT -6 +/** Invalid argument output. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_OUTPUT -7 +/** Invalid precision for Fixed-Precision Aritmetic. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_PRECISION -8 +/** Invalid RSA public key. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_RSAPUBKEY -9 +/** Invalid RSA private key. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_RSAPRIVKEY -10 +/** Invalid RSA CRT key. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_RSACRTKEY -11 +/** Invalid RSA CRT alternative key. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_RSACRTALTKEY -12 +/** Error during CRT recomposition. + * @ingroup UCL_RETURN + */ +#define UCL_RSACRT_ERROR -13 +/** Error, division by zero. + * @ingroup UCL_RETURN + */ +#define UCL_DIVISION_BY_ZERO -14 +/** Invalid chosen mode. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_MODE -15 +/** Large number with invalid sign. + * @ingroup UCL_RETURN + */ +#define UCL_INVALID_SIGN -16 +/** Invalid input for RSA. + * @ingroup UCL_RETURN + */ +#define UCL_RSA_INVALID_INPUT -17 +/** TRNG timeout. + * @ingroup UCL_RETURN + */ +#define UCL_RNGTIMEOUT -18 +/** RSA PKCS1-v1.5 decryption error. + * @ingroup UCL_RETURN + */ +#define UCL_RSAPKCS1_DECRYPTERR -19 +/** Overflow. + * @ingroup UCL_RETURN + */ +#define UCL_OVERFLOW -20 +/** Error in the case of the function is disabled. + * @ingroup UCL_RETURN + */ +#define UCL_FUNCTION_DISABLED -21 +/** (Big) Integer not odd. + * @ingroup UCL_RETURN + */ +#define UCL_INTEGER_NOT_ODD -22 +/** Invalid exponant of RSA key. + * @ingroup UCL_RETURN + */ +#define UCL_RSA_INVALID_EXPONANT -23 +/** UCL Stack overflow. + * Not enough memory. + * @ingroup UCL_RETURN + */ +#define UCL_STACK_OVERFLOW -24 +/** UCL Stack not init. + * @see ucl_stack_init + * @ingroup UCL_RETURN + */ +#define UCL_STACK_NOT_INIT -25 +/** Invalid UCL Stack free. + * @ingroup UCL_RETURN + */ +#define UCL_STACK_INVALID_FREE -26 +/** The UCL Stack is disabled. + * @ingroup UCL_RETURN + */ +#define UCL_STACK_DEFAULT -27 +/** Use default UCL stack. + * @ingroup UCL_RETURN + */ +#define UCL_STACK_ERROR -28 +/** General Warning. + * @ingroup UCL_RETURN + */ +#define UCL_WARNING -29 +/** PKCS1V25 Error - Invalid Signature . + * @ingroup UCL_RETURN + */ +#define UCL_PKCS1_INVALID_SIGNATURE -30 +/** No Interface for USIP® AES. + * @ingroup UCL_RETURN + */ +#define UCL_NO_UAES_INTERFACE -31 +/** USIP® AES Corrupted. + * @ingroup UCL_RETURN + */ +#define UCL_UAES_CORRUPTED -32 +/** USIP® AES Error. + * @ingroup UCL_RETURN + */ +#define UCL_UAES_ERROR -33 +/** USIP® TRNG Error. + * @ingroup UCL_RETURN + */ +#define UCL_TRNG_ERROR -34 +/** No Interface for USIP® TRNG. + * @ingroup UCL_RETURN + */ +#define UCL_NO_TRNG_INTERFACE -35 +/** No Interface for USIP® TRNG. + * @ingroup UCL_RETURN + */ +#define UCL_TRNG_CORRUPTED -36 +/** USIP® UCL Not Init. + * @ingroup UCL_RETURN + */ +#define UCL_NOT_INIT -37 +/** ECC key is invalid. + * @ingroup UCL_RETURN + */ +#define UCL_ECC_INVALID_KEY -38 + +/** RNG Interface Error. + * @ingroup UCL_RETURN + */ +#define UCL_RNG_ERROR -39 + +/** Functionality not implemented. + * @ingroup UCL_RETURN + */ +#define UCL_NOT_IMPLEMENTED -99 + +#endif /* UCL_RETDEFS_H_ */ diff --git a/drivers/power/supply/maxim/ucl_sha3.c b/drivers/power/supply/maxim/ucl_sha3.c new file mode 100644 index 000000000000..81d44d8de14e --- /dev/null +++ b/drivers/power/supply/maxim/ucl_sha3.c @@ -0,0 +1,429 @@ +//SHA3 implementation +//this implementation used the implementation from Markku-Juhani O.Saarinen +//as a starting point +/******************************************************************************* +* Copyright (C) 2017 Maxim Integrated Products, Inc., All rights Reserved. +* +* This software is protected by copyright laws of the United States and +* of foreign countries. This material may also be protected by patent laws +* and technology transfer regulations of the United States and of foreign +* countries. This software is furnished under a license agreement and/or a +* nondisclosure agreement and may only be used or reproduced in accordance +* with the terms of those agreements. Dissemination of this information to +* any party or parties not specified in the license agreement and/or +* nondisclosure agreement is expressly prohibited. +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +******************************************************************************* + +The MIT License (MIT) + +Copyright (c) 2015 Markku-Juhani O. Saarinen + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. +*/ +#include "ucl_hash.h" +#ifdef HASH_SHA3 + +#include +#include "ucl_retdefs.h" +#include "ucl_sha3.h" + +#define N_ROUNDS 24 // the specialization for keccak-f from keccak-p +#define ROTL64(x, y) \ + (((x) << (y)) | ((x) >> ((sizeof(unsigned long long) * 8) - (y)))) + +const unsigned long long kcf_rc[24] = { + 0x0000000000000001, 0x0000000000008082, 0x800000000000808a, + 0x8000000080008000, 0x000000000000808b, 0x0000000080000001, + 0x8000000080008081, 0x8000000000008009, 0x000000000000008a, + 0x0000000000000088, 0x0000000080008009, 0x000000008000000a, + 0x000000008000808b, 0x800000000000008b, 0x8000000000008089, + 0x8000000000008003, 0x8000000000008002, 0x8000000000000080, + 0x000000000000800a, 0x800000008000000a, 0x8000000080008081, + 0x8000000000008080, 0x0000000080000001, 0x8000000080008008 +}; +static const unsigned char kcf_rho[24] = { 1, 3, 6, 10, 15, 21, 28, 36, + 45, 55, 2, 14, 27, 41, 56, 8, + 25, 43, 62, 18, 39, 61, 20, 44 }; +static const unsigned char kcf_pilane[24] = { 10, 7, 11, 17, 18, 3, 5, 16, + 8, 21, 24, 4, 15, 23, 19, 13, + 12, 2, 20, 14, 22, 9, 6, 1 }; + +// generally called after SHA3_SPONGE_WORDS-ctx->capacityWords words +// are XORed into the state s +static void kcf(unsigned long long state[25]) +{ + int i, j, round; + unsigned long long t, c[5]; + + //I(chi(Pi(ro(theta( + for (round = 0; round < N_ROUNDS; round++) { + // Theta + for (i = 0; i < 5; i++) + c[i] = state[i] ^ state[i + 5] ^ state[i + 10] ^ + state[i + 15] ^ state[i + 20]; + + for (i = 0; i < 5; i++) { + t = c[(i + 4) % 5] ^ + (unsigned long long)ROTL64(c[(i + 1) % 5], 1); + for (j = 0; j < 25; j += 5) + state[j + i] ^= t; + } + + // Rho Pi + t = state[1]; + for (i = 0; i < 24; i++) { + j = (int)kcf_pilane[i]; + c[0] = state[j]; + state[j] = (unsigned long long)ROTL64(t, kcf_rho[i]); + t = c[0]; + } + + // Chi + for (j = 0; j < 25; j += 5) { + for (i = 0; i < 5; i++) + c[i] = state[j + i]; + for (i = 0; i < 5; i++) + state[j + i] ^= (~c[(i + 1) % 5]) & + c[(i + 2) % 5]; + } + // Iota + state[0] ^= kcf_rc[round]; + } +} + +int ucl_shake128_init(ucl_sha3_ctx_t *ctx) +{ + if (ctx == NULL) + return UCL_INVALID_INPUT; + memset(ctx, 0, sizeof(*ctx)); + ctx->capacityWords = 2 * 128 / (8 * sizeof(unsigned long long)); + return UCL_OK; +} + +int ucl_sha3_224_init(ucl_sha3_ctx_t *ctx) +{ + if (ctx == NULL) + return UCL_INVALID_INPUT; + memset(ctx, 0, sizeof(*ctx)); + ctx->capacityWords = 448 / (8 * sizeof(unsigned long long)); + return UCL_OK; +} + +int ucl_sha3_256_init(ucl_sha3_ctx_t *ctx) +{ + if (ctx == NULL) + return UCL_INVALID_INPUT; + memset(ctx, 0, sizeof(*ctx)); + ctx->capacityWords = 512 / (8 * sizeof(unsigned long long)); + return UCL_OK; +} + +int ucl_shake256_init(ucl_sha3_ctx_t *ctx) +{ + return ucl_sha3_256_init(ctx); +} + +int ucl_sha3_384_init(ucl_sha3_ctx_t *ctx) +{ + if (ctx == NULL) + return UCL_INVALID_INPUT; + memset(ctx, 0, sizeof(*ctx)); + ctx->capacityWords = 768 / (8 * sizeof(unsigned long long)); + return UCL_OK; +} + +int ucl_sha3_512_init(ucl_sha3_ctx_t *ctx) +{ + if (ctx == NULL) + return UCL_INVALID_INPUT; + memset(ctx, 0, sizeof(*ctx)); + ctx->capacityWords = 1024 / (8 * sizeof(unsigned long long)); + return UCL_OK; +} + +int ucl_sha3_core(ucl_sha3_ctx_t *ctx, const unsigned char *bufIn, + unsigned int len) +{ + unsigned int old_tail = (8 - ctx->byteIndex) & 7; + size_t words; + int tail; + size_t i; + const unsigned char *buf = bufIn; + + if (ctx == NULL) + return UCL_INVALID_INPUT; + if (bufIn == NULL) + return UCL_INVALID_INPUT; + if (len < old_tail) { + while (len--) + ctx->saved |= (unsigned long long)(*(buf++)) + << ((ctx->byteIndex++) * 8); + return UCL_OK; + } + + if (old_tail) { + len -= old_tail; + while (old_tail--) + ctx->saved |= (unsigned long long)(*(buf++)) + << ((ctx->byteIndex++) * 8); + ctx->s[ctx->wordIndex] ^= ctx->saved; + ctx->byteIndex = 0; + ctx->saved = 0; + if (++ctx->wordIndex == + ((int)SHA3_SPONGE_WORDS - ctx->capacityWords)) { + kcf(ctx->s); + ctx->wordIndex = 0; + } + } + + words = len / sizeof(unsigned long long); + tail = (int)(len - words * sizeof(unsigned long long)); + for (i = 0; i < words; i++, buf += sizeof(unsigned long long)) { + const unsigned long long t = + (unsigned long long)(buf[0]) | + ((unsigned long long)(buf[1]) << 8 * 1) | + ((unsigned long long)(buf[2]) << 8 * 2) | + ((unsigned long long)(buf[3]) << 8 * 3) | + ((unsigned long long)(buf[4]) << 8 * 4) | + ((unsigned long long)(buf[5]) << 8 * 5) | + ((unsigned long long)(buf[6]) << 8 * 6) | + ((unsigned long long)(buf[7]) << 8 * 7); + ctx->s[ctx->wordIndex] ^= t; + + if (++ctx->wordIndex == + ((int)SHA3_SPONGE_WORDS - ctx->capacityWords)) { + kcf(ctx->s); + ctx->wordIndex = 0; + } + } + + while (tail--) + ctx->saved |= (unsigned long long)(*(buf++)) + << ((ctx->byteIndex++) * 8); + + return UCL_OK; +} + +int ucl_sha3_finish(unsigned char *digest, ucl_sha3_ctx_t *ctx) +{ + int i; + + // SHA3 version + ctx->s[ctx->wordIndex] ^= + (ctx->saved ^ + ((unsigned long long)((unsigned long long)(0x02 | (1 << 2)) + << ((ctx->byteIndex) * 8)))); + ctx->s[(int)SHA3_SPONGE_WORDS - ctx->capacityWords - 1] ^= + (unsigned long long)0x8000000000000000UL; + kcf(ctx->s); + + if (digest == NULL) + return UCL_INVALID_OUTPUT; + if (ctx == NULL) + return UCL_INVALID_INPUT; + + for (i = 0; i < (int)SHA3_SPONGE_WORDS; i++) { + const unsigned int t1 = (unsigned int)ctx->s[i]; + const unsigned int t2 = (unsigned int)((ctx->s[i] >> 16) >> 16); + + ctx->sb[i * 8 + 0] = (unsigned char)(t1); + ctx->sb[i * 8 + 1] = (unsigned char)(t1 >> 8); + ctx->sb[i * 8 + 2] = (unsigned char)(t1 >> 16); + ctx->sb[i * 8 + 3] = (unsigned char)(t1 >> 24); + ctx->sb[i * 8 + 4] = (unsigned char)(t2); + ctx->sb[i * 8 + 5] = (unsigned char)(t2 >> 8); + ctx->sb[i * 8 + 6] = (unsigned char)(t2 >> 16); + ctx->sb[i * 8 + 7] = (unsigned char)(t2 >> 24); + } + + for (i = 0; i < (int)SHA3_SPONGE_WORDS * 8; i++) + digest[i] = ctx->sb[i]; + + return UCL_OK; +} + +int ucl_shake_finish(unsigned char *digest, ucl_sha3_ctx_t *ctx) +{ + int i; + + if (ctx == NULL) + return UCL_INVALID_INPUT; + if (digest == NULL) + return UCL_INVALID_OUTPUT; + + ctx->s[ctx->wordIndex] ^= (ctx->saved ^ ((unsigned long long)(0x1F) + << ((ctx->byteIndex) * 8))); + i = (int)SHA3_SPONGE_WORDS - ctx->capacityWords - 1; + ctx->s[(int)SHA3_SPONGE_WORDS - ctx->capacityWords - 1] ^= + (unsigned long long)(0x8000000000000000UL); + kcf(ctx->s); + + for (i = 0; i < (int)SHA3_SPONGE_WORDS; i++) { + const unsigned int t1 = (unsigned int)ctx->s[i]; + const unsigned int t2 = (unsigned int)((ctx->s[i] >> 16) >> 16); + + ctx->sb[i * 8 + 0] = (unsigned char)(t1); + ctx->sb[i * 8 + 1] = (unsigned char)(t1 >> 8); + ctx->sb[i * 8 + 2] = (unsigned char)(t1 >> 16); + ctx->sb[i * 8 + 3] = (unsigned char)(t1 >> 24); + ctx->sb[i * 8 + 4] = (unsigned char)(t2); + ctx->sb[i * 8 + 5] = (unsigned char)(t2 >> 8); + ctx->sb[i * 8 + 6] = (unsigned char)(t2 >> 16); + ctx->sb[i * 8 + 7] = (unsigned char)(t2 >> 24); + } + + for (i = 0; i < (int)SHA3_SPONGE_WORDS * 8; i++) + digest[i] = ctx->sb[i]; + + return UCL_OK; +} + +int ucl_sha3_224(unsigned char *digest, unsigned char *msg, unsigned int msgLen) +{ + ucl_sha3_ctx_t ctx; + + if (msg == NULL) + return UCL_INVALID_INPUT; + if (digest == NULL) + return UCL_INVALID_OUTPUT; + if (ucl_sha3_224_init(&ctx) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_core(&ctx, msg, msgLen) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_finish(digest, &ctx) != UCL_OK) + return (UCL_ERROR); + + return UCL_OK; +} + +int ucl_sha3_256(unsigned char *digest, unsigned char *msg, unsigned int msgLen) +{ + ucl_sha3_ctx_t ctx; + + if (msg == NULL) + return UCL_INVALID_INPUT; + if (digest == NULL) + return UCL_INVALID_OUTPUT; + + if (ucl_sha3_256_init(&ctx) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_core(&ctx, msg, msgLen) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_finish(digest, &ctx) != UCL_OK) + return (UCL_ERROR); + + return UCL_OK; +} + +int ucl_shake128(unsigned char *digest, unsigned char *msg, unsigned int msgLen) +{ + ucl_sha3_ctx_t ctx; + + if (msg == NULL) + return UCL_INVALID_INPUT; + if (digest == NULL) + return UCL_INVALID_OUTPUT; + + if (ucl_shake128_init(&ctx) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_core(&ctx, msg, msgLen) != UCL_OK) + return (UCL_ERROR); + if (ucl_shake_finish(digest, &ctx) != UCL_OK) + return (UCL_ERROR); + + return UCL_OK; +} + +int ucl_sha3_384(unsigned char *digest, unsigned char *msg, unsigned int msgLen) +{ + ucl_sha3_ctx_t ctx; + + if (msg == NULL) + return UCL_INVALID_INPUT; + if (digest == NULL) + return UCL_INVALID_OUTPUT; + + if (ucl_sha3_384_init(&ctx) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_core(&ctx, msg, msgLen) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_finish(digest, &ctx) != UCL_OK) + return (UCL_ERROR); + + return UCL_OK; +} + +int ucl_sha3_512(unsigned char *digest, unsigned char *msg, unsigned int msgLen) +{ + ucl_sha3_ctx_t ctx; + + if (msg == NULL) + return UCL_INVALID_INPUT; + if (digest == NULL) + return UCL_INVALID_OUTPUT; + + if (UCL_OK != ucl_sha3_512_init(&ctx)) + return (UCL_ERROR); + if (ucl_sha3_core(&ctx, msg, msgLen) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_finish(digest, &ctx) != UCL_OK) + return (UCL_ERROR); + + return UCL_OK; +} +int ucl_shake256(unsigned char *digest, unsigned char *msg, unsigned int msgLen) +{ + ucl_sha3_ctx_t ctx; + + if (msg == NULL) + return UCL_INVALID_INPUT; + if (digest == NULL) + return UCL_INVALID_OUTPUT; + + if (ucl_shake256_init(&ctx) != UCL_OK) + return (UCL_ERROR); + if (ucl_sha3_core(&ctx, msg, msgLen) != UCL_OK) + return (UCL_ERROR); + if (ucl_shake_finish(digest, &ctx) != UCL_OK) + return (UCL_ERROR); + + return UCL_OK; +} +#endif //SHA3 diff --git a/drivers/power/supply/maxim/ucl_sha3.h b/drivers/power/supply/maxim/ucl_sha3.h new file mode 100644 index 000000000000..706056d96b8f --- /dev/null +++ b/drivers/power/supply/maxim/ucl_sha3.h @@ -0,0 +1,269 @@ +/* sha3.h */ +#ifndef _UCL_SHA3_H +#define _UCL_SHA3_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define UCL_SHA3_224_HASHSIZE 28 +#define UCL_SHA3_256_HASHSIZE 32 +#define UCL_SHA3_384_HASHSIZE 48 +#define UCL_SHA3_512_HASHSIZE 64 +#define UCL_SHA3_MAX_PERMSIZE 25 +#define UCL_SHA3_MAXQRATE_QWORDS 24 + +#define UCL_SHA3 2 +#define UCL_SHA3_224 9 +#define UCL_SHA3_256 10 +#define UCL_SHA3_384 11 +#define UCL_SHA3_512 12 +/** +* SHA3 Algorithm context. +*/ +/** @file ucl_sha3.h +* @defgroup UCL_SHA3 SHA3 +* Secure Hash Algorithm 3, from FIPS 202. +* +* @par Header: +* @link ucl_sha3.h ucl_sha3.h @endlink +* +* SHA-3 is a data-digest algorithm and a component of +* the Standard FIPS 202. +* The algorithm takes as input a data of arbitrary length and +* produces as output 224-bit, 256-bit, 384-bit or 512-bit "fingerprint" or "data digest" +* of the input.@n +* @n +* +* SHA3 Descriptor: @n +* @li Hash length : 224/256/384/512 bits +* +* @ingroup UCL_HASH +*/ + +/** The SHA3 context. +* This structure is associated to the 'step by step' process. +* +* @ingroup UCL_SHA3 +*/ + +typedef struct sha3_ctx { + /* 1600 bits algorithm hashing state */ + unsigned long long hash[UCL_SHA3_MAX_PERMSIZE]; + /* 1536-bit buffer for leftovers */ + unsigned long long message[UCL_SHA3_MAXQRATE_QWORDS]; + /* count of bytes in the message[] buffer */ + unsigned int rest; + /* size of a message block processed at once */ + unsigned int block_size; +} sha3_ctx; + +#define SHA3_SPONGE_WORDS \ + (((1600) / 8 /*bits to byte*/) / sizeof(unsigned long long)) + +typedef struct sha3_context_ { + unsigned long long saved; + union { + unsigned long long s[SHA3_SPONGE_WORDS]; + unsigned char sb[SHA3_SPONGE_WORDS * 8]; + }; + int byteIndex; /* 0..7--the next byte after the set one + * (starts from 0; 0--none are buffered) */ + int wordIndex; /* 0..24--the next word to integrate input + * (starts from 0) */ + int capacityWords; /* the double size of the hash output in + * words (e.g. 16 for Keccak 512) */ +} ucl_sha3_ctx_t; + +// methods for calculating the hash function + +/*============================================================================*/ +/** SHA3-224 Init. +* The initialisation of SHA3-224. +* +* @param[in,out] context Pointer to the context +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_INPUT if @p context is #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_224_init(ucl_sha3_ctx_t *ctx); +/*============================================================================*/ +/** SHA3-256 Init. +* The initialisation of SHA3-256. +* +* @param[in,out] context Pointer to the context +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_INPUT if @p context is #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_256_init(ucl_sha3_ctx_t *ctx); +/*============================================================================*/ +/** SHA3-384 Init. +* The initialisation of SHA3-384. +* +* @param[in,out] context Pointer to the context +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_INPUT if @p context is #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_384_init(ucl_sha3_ctx_t *ctx); +/*============================================================================*/ +/** SHA3-512 Init. +* The initialisation of SHA3-512. +* +* @param[in,out] context Pointer to the context +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_INPUT if @p context is #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_512_init(ucl_sha3_ctx_t *ctx); +/*============================================================================*/ +/** SHA3 Core. +* The core of SHA3, common to all SHA3 hash functions. +* +* @param[in,out] context Pointer to the context +* @param[in] data Pointer to the data +* @param[in] data_byteLen Data byte length +* +* @warning #ucl_sha3-*_init must be processed before, and +* #ucl_sha3_finish should be processed to get the final hash. +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_NOP if @p data_byteLen = 0 or if @p data is the pointer #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_core(ucl_sha3_ctx_t *ctx, const unsigned char *bufIn, + unsigned int len); +/*============================================================================*/ +/** SHA3 Finish. +* Finish the process of SHA3, common to all SHA3 hash functions. +* +* @pre Hash byte length is equal to 28/32/48 or 64 bytes +* +* @param[out] hash Pointer to the digest +* @param[in,out] context Pointer to the context +* +* @warning #ucl_sha3_*_init and #ucl_sha3_core must be processed before. +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_OUTPUT if @p hash is the pointer #NULL +* @retval #UCL_INVALID_INPUT if @p context is the pointer #NULL +* +* @ingroup UCL_SHA3 +*/ + +int ucl_sha3_finish(unsigned char *digest, ucl_sha3_ctx_t *ctx); + +/*============================================================================*/ +/** SHA3-224. +* The complete process of SHA3-224. +* +* @pre Hash byte length is equal to 28 +* +* @param[out] hash Pointer to the digest +* @param[in] data Pointer to the data +* @param[in] data_byteLen Data byte length +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_OUTPUT if @p hash is #NULL +* +* @ingroup UCL_SHA3 +*/ + +int ucl_sha3_224(unsigned char *digest, unsigned char *msg, + unsigned int msgLen); + +/*============================================================================*/ +/** SHA3-256. +* The complete process of SHA3-256. +* +* @pre Hash byte length is equal to 32 +* +* @param[out] hash Pointer to the digest +* @param[in] data Pointer to the data +* @param[in] data_byteLen Data byte length +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_OUTPUT if @p hash is #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_256(unsigned char *digest, unsigned char *msg, + unsigned int msgLen); + +/*============================================================================*/ +/** SHA3-384. +* The complete process of SHA3-384. +* +* @pre Hash byte length is equal to 48 +* +* @param[out] hash Pointer to the digest +* @param[in] data Pointer to the data +* @param[in] data_byteLen Data byte length +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_OUTPUT if @p hash is #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_384(unsigned char *digest, unsigned char *msg, + unsigned int msgLen); + +/*============================================================================*/ +/** SHA3-512. +* The complete process of SHA3-512. +* +* @pre Hash byte length is equal to 64 +* +* @param[out] hash Pointer to the digest +* @param[in] data Pointer to the data +* @param[in] data_byteLen Data byte length +* +* @return Error code +* +* @retval #UCL_OK if no error occurred +* @retval #UCL_INVALID_OUTPUT if @p hash is #NULL +* +* @ingroup UCL_SHA3 +*/ +int ucl_sha3_512(unsigned char *digest, unsigned char *msg, + unsigned int msgLen); +int ucl_shake128_init(ucl_sha3_ctx_t *ctx); +int ucl_shake256_init(ucl_sha3_ctx_t *ctx); +int ucl_shake_finish(unsigned char *hash, ucl_sha3_ctx_t *ctx); +int ucl_shake128(unsigned char *digest, unsigned char *msg, + unsigned int msgLen); +int ucl_shake256(unsigned char *digest, unsigned char *msg, + unsigned int msgLen); +#ifdef __cplusplus +} /* extern "C" */ +#endif /* __cplusplus */ + +#endif /* _UCL_SHA3_H */ diff --git a/drivers/power/supply/nuvolta/Kconfig b/drivers/power/supply/nuvolta/Kconfig new file mode 100644 index 000000000000..416a0cecd229 --- /dev/null +++ b/drivers/power/supply/nuvolta/Kconfig @@ -0,0 +1,30 @@ +menu "NuVolta Technologies Inc. Charger support" + +config CHARGER_NU1618 + tristate "nuvolta nu1618 wireless charger driver" + help + say y here to enable support for nu1618 charger driver. + +config RX1619_TRIM + tristate "RX1619 TRIM" + depends on I2C + help + Say Y to include support for rx1619 wireless Charger. + RX1619 is a wireless battery charger chip. + The driver supports charger enable/disable. + The driver reports the charger status via the power supply framework. + The driver controls rx1619 via I2C and + supports device-tree interface. + +config RX1619 + tristate "RX1619 wireless Charger" + depends on I2C + help + Say Y to include support for rx1619 wireless Charger. + RX1619 is a wireless battery charger chip. + The driver supports charger enable/disable. + The driver reports the charger status via the power supply framework. + The driver controls rx1619 via I2C and + supports device-tree interface. + +endmenu diff --git a/drivers/power/supply/nuvolta/Makefile b/drivers/power/supply/nuvolta/Makefile new file mode 100644 index 000000000000..1de8b38b5eca --- /dev/null +++ b/drivers/power/supply/nuvolta/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_CHARGER_NU1618) += rx1618.o +obj-$(CONFIG_RX1619_TRIM) += rx1619_trim.o +obj-$(CONFIG_RX1619) += rx1619.o diff --git a/drivers/power/supply/nuvolta/rx1618.c b/drivers/power/supply/nuvolta/rx1618.c new file mode 100644 index 000000000000..f5d4edf23836 --- /dev/null +++ b/drivers/power/supply/nuvolta/rx1618.c @@ -0,0 +1,1635 @@ +/** + * @file rx1618.c + * @author + * @date Tuesday, January 9th 2018 + * + * @brief + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rx1618.h" + +#define RX1618_DELAY_MS 30000 +#define EPP_MODE 1 +#define BPP_MODE 0 +#define MIN_VBUCK 4000 +#define MAX_VBUCK 11000 +#define AP_REV_DATA_OK 0xaa +#define AP_SENT_DATA_OK 0x55 +#define PRIVATE_VBUCK_SET_CMD 0x80 +#define PRIVATE_ID_CMD 0x86 +#define PRIVATE_USB_TYPE_CMD 0x87 +#define PRIVATE_FAST_CHG_CMD 0x88 +#define PRIVATE_PRODUCT_TEST_CMD 0x89 +#define PRIVATE_FOD_TEST_CMD 0x8A +#define PRIVATE_TX_HW_ID_CMD 0x8b + +/* used registers define */ +#define REG_RX_SENT_CMD 0x0000 +#define REG_RX_SENT_DATA1 0x0001 +#define REG_RX_SENT_DATA2 0x0002 +#define REG_RX_SENT_DATA3 0x0003 +#define REG_RX_SENT_DATA4 0x0004 +#define REG_RX_SENT_DATA5 0x0005 +#define REG_RX_REV_CMD 0x0020 +#define REG_RX_REV_DATA1 0x0021 +#define REG_RX_REV_DATA2 0x0022 +#define REG_RX_REV_DATA3 0x0023 +#define REG_RX_REV_DATA4 0x0024 +#define REG_RX_REV_DATA5 0x0025 +#define REG_RX_VRECT 0x000a +#define REG_RX_IRECT 0x000b +#define REG_RX_VBUCK_1 0x0008 +#define REG_RX_VBUCK_2 0x0009 +#define REG_AP_RX_COMM 0x000C + +static struct rx1618_chg *g_chip; +static int g_Delta = 0; +static bool int_done_flag = false; +static u8 g_light_screen_flag = 0; +static u8 g_sar_done_flag = 0; +static u8 g_fast_chg_flag = 0; +static u8 g_id_done_flag = 0; +static u8 g_cali_done_flag = 0; +static u8 g_usb_type_flag = 0; +static u8 g_fw_id = 0; +static u8 g_hw_id_h, g_hw_id_l; +static u8 g_epp_or_bpp = BPP_MODE; + +struct rx1618_chg { + char *name; + struct i2c_client *client; + struct device *dev; + struct regmap *regmap; + int irq_gpio; + int enable_gpio; + int chip_enable; + int online; + struct delayed_work wireless_work; + struct delayed_work wireless_int_work; + struct mutex irq_complete; + struct mutex wireless_chg_lock; + struct mutex wireless_chg_int_lock; + + struct power_supply *wip_psy; + struct power_supply *dc_psy; + struct power_supply_desc wip_psy_d; + struct power_supply *wireless_psy; + int epp; + int auth; +}; + +static int rx1618_read(struct rx1618_chg *chip, u8 *val, u16 addr) +{ + unsigned int temp; + int rc; + + rc = regmap_read(chip->regmap, addr, &temp); + if (rc >= 0) { + *val = (u8)temp; + //dev_err(chip->dev, "[rx1618] [%s] [0x%04x] = [0x%x] \n", __func__, addr, *val); + } + + return rc; +} + +static int rx1618_write(struct rx1618_chg *chip, u8 val, u16 addr) +{ + int rc = 0; + + rc = regmap_write(chip->regmap, addr, val); + if (rc >= 0) { + //dev_err(chip->dev, "[rx1618] [%s] [0x%04x] = [0x%x] \n", __func__, addr, *val); + } + + return rc; +} + +unsigned int rx1618_get_rx_vrect(struct rx1618_chg *chip) +{ + u8 data = 0; + u16 vrect = 0; + + //if(!chip->online) + // return -EINVAL; + + rx1618_read(chip, &data, REG_RX_VRECT); + vrect = (22500 * data) >> 8; + + dev_err(chip->dev, "[rx1618] [%s] data = 0x%x, vrect=%d mV\n", __func__, + data, vrect); + + return vrect; +} + +unsigned int rx1618_get_rx_irect(struct rx1618_chg *chip) +{ + u8 data = 0; + u16 irect = 0; + + //if(!chip->online) + // return -EINVAL; + + rx1618_read(chip, &data, REG_RX_IRECT); + irect = (2500 * data) >> 8; + + dev_err(chip->dev, "[rx1618] [%s] data = 0x%x, irect=%d mA \n", + __func__, data, irect); + + return irect; +} + +unsigned int rx1618_get_rx_vbuck(struct rx1618_chg *chip) +{ + u16 vbuck = 0; + u8 data1 = 0; + u8 data2 = 0; + u16 data = 0; + + // if(!chip->online) + // return -EINVAL; + + rx1618_read(chip, &data1, REG_RX_VBUCK_1); + rx1618_read(chip, &data2, REG_RX_VBUCK_2); + + data = (data1 << 2) + (data2 & 0x03); + vbuck = (2500 * 590 / 120 * data) >> 10; + + dev_err(chip->dev, + "[rx1618] [%s] Vbuck: data=0x%x, vbuck=%d mV ,data1 = 0x%x, data2= 0x%x \n", + __func__, data, vbuck, data1, data2); + + return vbuck; +} + +unsigned int rx1618_get_rx_ibuck(struct rx1618_chg *chip) +{ + u16 ibuck = 0; + + //if(!chip->online) + // return -EINVAL; + + ibuck = (rx1618_get_rx_vrect(chip) * rx1618_get_rx_irect(chip) * 95) / + (rx1618_get_rx_vbuck(chip) * 100); + + dev_err(chip->dev, "[rx1618] [%s] Ibuck = %d mA\n", __func__, ibuck); + + return ibuck; +} + +bool rx1618_is_vbuck_on(struct rx1618_chg *chip) +{ + bool vbuck_status = false; + unsigned int voltage = 0; + + voltage = rx1618_get_rx_vbuck(chip); + + dev_err(chip->dev, "[rx1618] [%s] Vbuck = %d \n", __func__, voltage); + + if ((voltage > MIN_VBUCK) && (voltage < MAX_VBUCK)) //4V~11V + { + vbuck_status = true; + } else { + vbuck_status = false; + } + + return vbuck_status; +} + +int rx1618_set_vbuck(struct rx1618_chg *chip, int volt) +{ + u8 data = 0; + + if ((volt < 5166) && + (volt > 9609)) //V bus_set =5166000uV+21224uV*[Vbus_set(0:7)] DEC + { + data = 0; + } else { + data = (volt - 5166) * 1000 / 21224; + } + + data = data + g_Delta; + dev_err(chip->dev, "[rx1618] [%s] data = 0x%x, g_Delta=%d \n", __func__, + data, g_Delta); + + rx1618_write(chip, PRIVATE_VBUCK_SET_CMD, + REG_RX_SENT_CMD); //sent set vbuck cmd + rx1618_write(chip, data, REG_RX_SENT_DATA1); //sent data0 + + rx1618_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + + return 0; +} + +bool rx1618_check_firmware(struct rx1618_chg *chip) +{ + u8 *read_buffer = NULL; + int i = 0; + + read_buffer = (u8 *)vmalloc(20000); + + rx1618_write(chip, 0xB2, 0x0017); + rx1618_write(chip, 0xB3, 0x0017); + + dev_err(chip->dev, "[rx1618] [%s] enter \n", __func__); + + for (i = 0; i < (sizeof(fw_data) / 4); i++) { + rx1618_write(chip, ((0 + i * 4) / 256), 0x0010); //address_H + rx1618_write(chip, ((0 + i * 4) % 256), 0x0011); //address_L + + rx1618_read(chip, (read_buffer + 4 * i + 0), 0x0013); + rx1618_read(chip, (read_buffer + 4 * i + 1), 0x0014); + rx1618_read(chip, (read_buffer + 4 * i + 2), 0x0015); + rx1618_read(chip, (read_buffer + 4 * i + 3), 0x0016); + } + + rx1618_write(chip, 0xB2, 0x0017); + rx1618_write(chip, 0x00, 0x0017); + rx1618_write(chip, 0x55, 0x2017); + + for (i = 0; i < sizeof(fw_data); i++) { + if (read_buffer[i] != ((~fw_data[i]) & 0xff)) { + dev_err(chip->dev, + "[rx1618] [%s] fw download Fail! read_buffer[i]=0x%x, ~fw_data[i]=0x%x, i=%d, sizeof(fw_data)=%ld\n", + __func__, read_buffer[i], (~fw_data[i]) & 0xff, + i, sizeof(fw_data)); + + vfree(read_buffer); + return false; + } + } + + dev_err(chip->dev, "[rx1618] [%s] i=%d, sizeof(fw_data)=%ld\n", + __func__, i, sizeof(fw_data)); + + if (i == sizeof(fw_data)) { + dev_err(chip->dev, "[rx1618] [%s] fw download Success! \n", + __func__); + vfree(read_buffer); + return true; + } else { + vfree(read_buffer); + return false; + } +} + +bool rx1618_download_firmware(struct rx1618_chg *chip) +{ + bool check_status = false; + int i = 0; + + cancel_delayed_work_sync(&chip->wireless_work); + cancel_delayed_work_sync(&chip->wireless_int_work); + + rx1618_write(chip, 0x55, 0x2017); + rx1618_write(chip, 0x69, 0x2017); + rx1618_write(chip, 0x96, 0x2017); + rx1618_write(chip, 0x66, 0x2017); + rx1618_write(chip, 0x99, 0x2017); + rx1618_write(chip, 0x00, 0x2018); + rx1618_write(chip, 0x00, 0x2019); + rx1618_write(chip, 0x5A, 0x0001); + rx1618_write(chip, 0x3C, 0x0002); + rx1618_write(chip, 0xA5, 0x0003); + rx1618_write(chip, 0xC3, 0x0004); + rx1618_write(chip, 0x60, 0x1000); + rx1618_write(chip, 0x9C, 0x0017); + rx1618_write(chip, 0x9D, 0x0017); + rx1618_write(chip, 0x00, 0x0010); + rx1618_write(chip, 0x00, 0x0011); + rx1618_write(chip, 0x01, 0x0019); + mdelay(180); + rx1618_write(chip, 0x00, 0x0019); + rx1618_write(chip, 0x9C, 0x0017); + rx1618_write(chip, 0xA2, 0x0017); + rx1618_write(chip, 0xA3, 0x0017); + rx1618_write(chip, 0x01, 0x0019); + mdelay(20); + rx1618_write(chip, 0x00, 0x0019); + rx1618_write(chip, 0xA2, 0x0017); + rx1618_write(chip, 0x80, 0x0017); + mdelay(20); + rx1618_write(chip, 0x5A, 0x0001); + rx1618_write(chip, 0x3C, 0x0002); + rx1618_write(chip, 0xA5, 0x0003); + rx1618_write(chip, 0xC3, 0x0004); + rx1618_write(chip, 0x60, 0x1000); + rx1618_write(chip, 0x9C, 0x0017); + rx1618_write(chip, 0x9D, 0x0017); + rx1618_write(chip, 0x00, 0x0010); + rx1618_write(chip, 0x00, 0x0011); + rx1618_write(chip, 0x01, 0x0019); + mdelay(180); + rx1618_write(chip, 0x00, 0x0019); + rx1618_write(chip, 0x9C, 0x0017); + rx1618_write(chip, 0xA2, 0x0017); + rx1618_write(chip, 0xA3, 0x0017); + rx1618_write(chip, 0x01, 0x0019); + mdelay(20); + rx1618_write(chip, 0x00, 0x0019); + rx1618_write(chip, 0xA2, 0x0017); + rx1618_write(chip, 0x80, 0x0017); + rx1618_write(chip, 0x9C, 0x0017); + rx1618_write(chip, 0x9D, 0x0017); + rx1618_write(chip, 0x20, 0x0010); + rx1618_write(chip, 0x00, 0x0011); + rx1618_write(chip, 0x01, 0x0019); + rx1618_write(chip, 0x00, 0x0019); + rx1618_write(chip, 0x9C, 0x0017); + rx1618_write(chip, 0xA2, 0x0017); + rx1618_write(chip, 0xA3, 0x0017); + rx1618_write(chip, 0x01, 0x0019); + mdelay(20); + rx1618_write(chip, 0x00, 0x0019); + rx1618_write(chip, 0xA2, 0x0017); + rx1618_write(chip, 0x80, 0x0017); + rx1618_write(chip, 0x00, 0x0010); + rx1618_write(chip, 0x00, 0x0011); + + rx1618_write(chip, (~fw_data[0]), 0x0012); + rx1618_write(chip, 0x92, 0x0017); + rx1618_write(chip, 0x93, 0x0017); + rx1618_write(chip, 0x69, 0x001A); + + for (i = 1; i < (sizeof(fw_data)); i++) { + rx1618_write(chip, (~fw_data[i]), 0x0012); + udelay(20); + } + + dev_err(chip->dev, + "[rx1618] [%s] fw download Success! Firmware total data: %d bytes \n", + __func__, i); + + rx1618_write(chip, 0x92, 0x0017); + rx1618_write(chip, 0x80, 0x0017); + rx1618_write(chip, 0x77, 0x001A); + + mdelay(500); + check_status = rx1618_check_firmware(chip); + + if (check_status) { + dev_err(chip->dev, + "[rx1618] [%s] RX1618 download firmware and check firmware Success! \n", + __func__); + return true; + } else { + dev_err(chip->dev, + "[rx1618] [%s] RX1618 download firmware Fail, Please try again !!! \n", + __func__); + return false; + } +} + +static void determine_initial_status(struct rx1618_chg *chip) +{ + bool vbuck_on = false; + //union power_supply_propval prop = {0, }; + + vbuck_on = rx1618_is_vbuck_on(chip); + if (vbuck_on && !chip->online) { + chip->online = 1; + //prop.intval = vbuck_on; + //power_supply_set_property(chip->batt_psy, POWER_SUPPLY_PROP_WIRELESS_ONLINE, &prop); + } + + dev_err(chip->dev, "[rx1618] [%s] initial vbuck_on = %d, online = %d\n", + __func__, vbuck_on, chip->online); +} + +int rx1618_chip_init(struct rx1618_chg *chip) +{ + return 0; +} + +void rx1618_dump_reg(void) +{ + u8 data[32] = { 0 }; + + rx1618_read(g_chip, &data[0], 0x0000); + rx1618_read(g_chip, &data[1], 0x0001); + rx1618_read(g_chip, &data[2], 0x0002); + rx1618_read(g_chip, &data[3], 0x0003); + rx1618_read(g_chip, &data[4], 0x0004); + rx1618_read(g_chip, &data[5], 0x0005); + rx1618_read(g_chip, &data[6], 0x0008); + rx1618_read(g_chip, &data[7], 0x0009); + rx1618_read(g_chip, &data[8], 0x000A); + rx1618_read(g_chip, &data[9], 0x000B); + rx1618_read(g_chip, &data[10], 0x000C); + rx1618_read(g_chip, &data[11], 0x0020); + rx1618_read(g_chip, &data[12], 0x0021); + rx1618_read(g_chip, &data[13], 0x0022); + rx1618_read(g_chip, &data[14], 0x0023); + rx1618_read(g_chip, &data[15], 0x0024); + + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0000=0x%x\n", __func__, + data[0]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0001=0x%x\n", __func__, + data[1]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0002=0x%x\n", __func__, + data[2]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0003=0x%x\n", __func__, + data[3]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0004=0x%x\n", __func__, + data[4]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0005=0x%x\n", __func__, + data[5]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0008=0x%x\n", __func__, + data[6]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0009=0x%x\n", __func__, + data[7]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x000A=0x%x\n", __func__, + data[8]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x000B=0x%x\n", __func__, + data[9]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x000C=0x%x\n", __func__, + data[10]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0020=0x%x\n", __func__, + data[11]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0021=0x%x\n", __func__, + data[12]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0022=0x%x\n", __func__, + data[13]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0023=0x%x\n", __func__, + data[14]); + dev_err(g_chip->dev, "[rx1618] [%s] REG:0x0024=0x%x\n", __func__, + data[15]); +} + +#define N 2 +//0x000b[0:3] 0000:no charger, 0001:SDP, 0010:CDP, 0011:DCP, 0101:QC2-other, +//0110:QC3-other, 0111:PD, 1000:fail charger, 1001:QC3-27W, 1010:PD-27W +#define EPP_MODE_CURRENT 300000 * N +#define DC_OTHER_CURRENT 400000 * N +#define DC_LOW_CURRENT 100000 * N //200mA +#define DC_SDP_CURRENT 400000 * N +#define DC_DCP_CURRENT 400000 * N +#define DC_CDP_CURRENT 400000 * N +#define DC_QC2_CURRENT 500000 * N +#define DC_QC3_CURRENT 500000 * N +#define DC_QC3_20W_CURRENT 1000000 * N //2A +#define DC_PD_CURRENT 500000 * N +#define DC_PD_20W_CURRENT 1000000 * N //2A +void rx1618_set_pmi_icl(struct rx1618_chg *chip, int mA) +{ + union power_supply_propval val = { + 0, + }; + + if (!chip->dc_psy) { + chip->dc_psy = power_supply_get_by_name("dc"); + if (!chip->dc_psy) { + dev_err(chip->dev, "[rx1618] [%s] no dc_psy,return\n", + __func__); + return; + } + } + val.intval = mA; + power_supply_set_property(chip->dc_psy, POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + dev_err(chip->dev, "[rx1618] [%s] [rx1618] set icl: %d\n", __func__, + val.intval); +} + +static void rx1618_wireless_work(struct work_struct *work) +{ + struct rx1618_chg *chip = + container_of(work, struct rx1618_chg, wireless_work.work); + + mutex_lock(&chip->wireless_chg_lock); + schedule_delayed_work(&chip->wireless_work, + msecs_to_jiffies(RX1618_DELAY_MS)); + mutex_unlock(&chip->wireless_chg_lock); + + dev_err(chip->dev, "[rx1618] [%s] enter \n", __func__); + + return; +} + +static void rx1618_wireless_int_work(struct work_struct *work) +{ + int i = 0; + int uA = 0; + u16 irect = 0; + u16 vrect = 0; + u8 data1, data2, data3, data4, privite_cmd, tx_cmd, usb_type; + u8 data_h, data_l, header, header_length; + union power_supply_propval val = { + 0, + }; + + struct rx1618_chg *chip = + container_of(work, struct rx1618_chg, wireless_int_work.work); + + chip->wireless_psy = power_supply_get_by_name("wireless"); + if (!chip->wireless_psy) { + dev_err(chip->dev, "[rx1618] no wireless_psy,return\n"); + } + + mutex_lock(&chip->wireless_chg_int_lock); + dev_err(chip->dev, "[rx1618] [%s] enter \n", __func__); + + //read data + rx1618_read(chip, &privite_cmd, REG_RX_REV_CMD); + rx1618_read(chip, &data1, REG_RX_REV_DATA1); + rx1618_read(chip, &data2, REG_RX_REV_DATA2); + rx1618_read(chip, &data3, REG_RX_REV_DATA3); + rx1618_read(chip, &data4, REG_RX_REV_DATA4); + + dev_err(chip->dev, + "[rx1618] [%s] privite_cmd,data=0x%x,0x%x,0x%x,0x%x,0x%x\n", + __func__, privite_cmd, data1, data2, data3, data4); + + switch (privite_cmd) { + case 0x01: //Vrect10 + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + break; + case 0x02: //Duty L + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + break; + case 0x03: //Duty H + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + break; + case 0x04: //OVPH + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + break; + case 0x05: //OCPH + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + break; + case 0x06: //Plimit + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + break; + case 0x07: //FCM20 + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + break; + + case 0x08: //calibration + if (g_cali_done_flag == 0) { + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + chip->epp = 1; + g_cali_done_flag = 1; + dev_err(chip->dev, "[rx1618] [%s] Calibration OK! \n", + __func__); + + for (i = 0; i <= 2; i++) { + uA = (EPP_MODE_CURRENT + N * 50000 * i); + rx1618_set_pmi_icl(chip, uA); + msleep(100); + } + } + break; + + case 0x09: //ID ok + if (g_id_done_flag == 0) { + rx1618_write(chip, AP_REV_DATA_OK, + REG_AP_RX_COMM); //receive ok + msleep(10); + + rx1618_write(chip, PRIVATE_ID_CMD, + REG_RX_SENT_CMD); //sent sar + rx1618_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + g_id_done_flag = 1; + dev_err(chip->dev, "[rx1618] [%s] ID OK! \n", __func__); + } + break; + + case 0x0A: //SAR ok + if (g_sar_done_flag == 0) { + rx1618_write(chip, AP_REV_DATA_OK, + REG_AP_RX_COMM); //receive ok + msleep(10); + + rx1618_write(chip, PRIVATE_USB_TYPE_CMD, + REG_RX_SENT_CMD); //sent usb type + rx1618_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + g_sar_done_flag = 1; + dev_err(chip->dev, "[rx1618] [%s] SAR OK! \n", + __func__); + chip->auth = 1; + } + break; + + case 0x12: //fast charge ok + if (g_fast_chg_flag == 0) { + rx1618_write(chip, AP_REV_DATA_OK, + REG_AP_RX_COMM); //receive ok + msleep(10); + + g_fast_chg_flag = 1; + dev_err(chip->dev, "[rx1618] [%s] Fast charge ok! \n", + __func__); + + rx1618_write(chip, 0x18, REG_RX_SENT_DATA1); + rx1618_write(chip, 0x4c, REG_RX_SENT_DATA2); + rx1618_write(chip, PRIVATE_TX_HW_ID_CMD, + REG_RX_SENT_CMD); //sent tx hw id req + rx1618_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + dev_err(chip->dev, "[rx1618] [%s] sent tx hw id req\n", + __func__); + } + + break; + + case 0x0B: //USB type + if (g_usb_type_flag == 0) { + rx1618_write(chip, AP_REV_DATA_OK, + REG_AP_RX_COMM); //receive ok + msleep(10); + + rx1618_read(chip, &usb_type, 0x0021); + + rx1618_write(chip, PRIVATE_FAST_CHG_CMD, + REG_RX_SENT_CMD); //sent fast charge + rx1618_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + g_usb_type_flag = 1; + dev_err(chip->dev, "[rx1618] [%s] usb_type=0x%x \n", + __func__, usb_type); + + switch (usb_type) { + case 0: //other charger + if ((g_id_done_flag == 0) && + (g_epp_or_bpp == BPP_MODE)) //bpp and no id + { + rx1618_set_pmi_icl(chip, + DC_OTHER_CURRENT); + dev_err(chip->dev, + "[rx1618] [%s] bpp and no id---800mA \n", + __func__); + } else //ID ok + { + rx1618_set_pmi_icl(chip, + DC_LOW_CURRENT); + dev_err(chip->dev, + "[rx1618] [%s] bpp and id ok---200mA \n", + __func__); + } + break; + + case 1: //SDP--1W + rx1618_set_pmi_icl(chip, DC_SDP_CURRENT); + dev_err(chip->dev, "[rx1618] [%s] SDP--1W \n", + __func__); + break; + + case 2: //CDP--1W + rx1618_set_pmi_icl(chip, DC_CDP_CURRENT); + dev_err(chip->dev, "[rx1618] [%s] CDP--1W \n", + __func__); + break; + + case 3: //DCP--1W + rx1618_set_pmi_icl(chip, DC_DCP_CURRENT); + dev_err(chip->dev, "[rx1618] [%s] DCP--1W \n", + __func__); + break; + + case 5: //QC2-other -- 7.5W + for (i = 0; i <= 8; i++) { + uA = (DC_LOW_CURRENT + N * 50000 * i); + rx1618_set_pmi_icl(chip, uA); + msleep(100); + } + dev_err(chip->dev, + "[rx1618] [%s] QC2 other--7.5W \n", + __func__); + break; + + case 6: //QC3-other -- 10W + for (i = 0; i <= 8; i++) { + uA = (DC_LOW_CURRENT + N * 50000 * i); + rx1618_set_pmi_icl(chip, uA); + msleep(100); + } + dev_err(chip->dev, + "[rx1618] [%s] QC3 other--10W \n", + __func__); + break; + + case 7: //PD-other -- 10W + for (i = 0; i <= 8; i++) { + uA = (DC_LOW_CURRENT + N * 50000 * i); + rx1618_set_pmi_icl(chip, uA); + msleep(100); + } + dev_err(chip->dev, + "[rx1618] [%s] PD other--7.5W \n", + __func__); + break; + + case 8: //fail charger + break; + + case 9: //QC3-27W(20W) + for (i = 0; i <= 11; i++) { + uA = (DC_QC3_CURRENT + N * 50000 * i); + rx1618_set_pmi_icl(chip, uA); + msleep(100); + } + if (chip->epp && chip->auth && + chip->wireless_psy) { + val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, + &val); + } + dev_err(chip->dev, + "[rx1618] [%s] QC3-27W(20W) \n", + __func__); + break; + + case 10: //PD-27W(20W) + for (i = 0; i <= 11; i++) { + uA = (DC_QC3_CURRENT + N * 50000 * i); + rx1618_set_pmi_icl(chip, uA); + msleep(100); + } + if (chip->epp && chip->auth && + chip->wireless_psy) { + val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, + &val); + } + dev_err(chip->dev, + "[rx1618] [%s] PD-27W(20W) \n", + __func__); + break; + + default: + dev_err(chip->dev, + "[rx1618] [%s] other Usb_type\n", + __func__); + break; + } + } + break; + + case 0x0C: //Light screen + if (g_light_screen_flag == 0) { + rx1618_write(chip, AP_REV_DATA_OK, + REG_AP_RX_COMM); //receive ok + msleep(10); + + rx1618_read(chip, &g_hw_id_h, REG_RX_REV_DATA1); + rx1618_read(chip, &g_hw_id_l, REG_RX_REV_DATA2); + rx1618_read(chip, &g_fw_id, REG_RX_REV_DATA3); + rx1618_read(chip, &g_epp_or_bpp, REG_RX_REV_DATA4); + + if (g_epp_or_bpp == EPP_MODE) //EPP + { + rx1618_set_pmi_icl(chip, EPP_MODE_CURRENT); + dev_err(chip->dev, + "[rx1618] [%s] EPP--600mA \n", + __func__); + } else //BPP mode + { + rx1618_set_pmi_icl(chip, DC_LOW_CURRENT); + dev_err(chip->dev, + "[rx1618] [%s] BPP--200mA \n", + __func__); + } + + g_light_screen_flag = 1; + + dev_err(chip->dev, + "[rx1618] [%s] Light screen,fw_id,hw_id_h,hw_id_l,g_epp_or_bpp=0x%x, 0x%x, 0x%x, 0x%x\n", + __func__, g_fw_id, g_hw_id_h, g_hw_id_l, + g_epp_or_bpp); + } + break; + + case 0x4C: //tx hw id + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + + rx1618_read(chip, &data1, REG_RX_REV_DATA1); + rx1618_read(chip, &data2, REG_RX_REV_DATA2); + rx1618_read(chip, &data3, REG_RX_REV_DATA3); + + dev_err(chip->dev, + "[rx1618] [%s] tx hw id,data1-3=0x%x, 0x%x, 0x%x, 0x%x\n", + __func__, data1, data2, data3, data4); + break; + + case 0x0D: //TX test request + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + + rx1618_read(chip, &header, REG_RX_REV_DATA1); + header_length = ((header & 0xf0) >> 4); + + dev_err(chip->dev, + "[rx1618] [%s] product Test mode, header=0x%x, header_length=0x%x\n", + __func__, header, header_length); + + switch (header_length) { + case 1: + rx1618_read(chip, &tx_cmd, REG_RX_REV_DATA2); + break; + + case 2: + rx1618_read(chip, &tx_cmd, REG_RX_REV_DATA2); + rx1618_read(chip, &data1, REG_RX_REV_DATA3); + break; + + case 3: + rx1618_read(chip, &tx_cmd, REG_RX_REV_DATA2); + rx1618_read(chip, &data1, REG_RX_REV_DATA3); + rx1618_read(chip, &data2, REG_RX_REV_DATA4); + break; + + case 4: + rx1618_read(chip, &tx_cmd, REG_RX_REV_DATA2); + rx1618_read(chip, &data1, REG_RX_REV_DATA3); + rx1618_read(chip, &data2, REG_RX_REV_DATA4); + rx1618_read(chip, &data3, REG_RX_REV_DATA5); + break; + + default: + break; + } + + dev_err(chip->dev, + "[rx1618] [%s] tx_cmd,data=0x%x, 0x%x, 0x%x, 0x%x\n", + __func__, tx_cmd, data1, data2, data3); + + if (tx_cmd == 0x12) //irect + { + rx1618_write(chip, 0x38, + REG_RX_SENT_DATA1); //sent header + rx1618_write(chip, 0x12, REG_RX_SENT_DATA2); //sent cmd + + irect = rx1618_get_rx_irect(chip); + data_h = (irect & 0xff00) >> 8; + rx1618_write(chip, data_h, 0x0003); + data_l = (irect & 0x00ff); + rx1618_write(chip, data_l, 0x0004); + dev_err(chip->dev, + "[rx1618] [%s] product test--0x12--irect=%d \n", + __func__, irect); + } else if (tx_cmd == 0x13) //vrect + { + rx1618_write(chip, 0x38, + REG_RX_SENT_DATA1); //sent header + rx1618_write(chip, 0x13, REG_RX_SENT_DATA2); //sent cmd + + vrect = rx1618_get_rx_vrect(chip); + data_h = (vrect & 0xff00) >> 8; + rx1618_write(chip, data_h, 0x0003); + data_l = (vrect & 0x00ff); + rx1618_write(chip, data_l, 0x0004); + dev_err(chip->dev, + "[rx1618] [%s] product test--0x13--vrect=%d \n", + __func__, vrect); + } else if (tx_cmd == 0x24) //fw id + { + rx1618_write(chip, 0x28, + REG_RX_SENT_DATA1); //sent header + rx1618_write(chip, 0x24, REG_RX_SENT_DATA2); //sent cmd + rx1618_write(chip, g_fw_id, 0x0003); + dev_err(chip->dev, + "[rx1618] [%s] product test--0x24--g_fw_id=0x%x \n", + __func__, g_fw_id); + } else if (tx_cmd == 0x25) //hw id + { + rx1618_write(chip, 0x38, + REG_RX_SENT_DATA1); //sent header + rx1618_write(chip, 0x25, REG_RX_SENT_DATA2); //sent cmd + rx1618_write(chip, g_hw_id_h, 0x0003); + rx1618_write(chip, g_hw_id_l, 0x0004); + dev_err(chip->dev, + "[rx1618] [%s] product test--0x25--g_hw_id=0x%x, 0x%x \n", + __func__, g_hw_id_h, g_hw_id_l); + } else { + dev_err(chip->dev, + "[rx1618] [%s] product test--other cmd \n", + __func__); + break; + } + + dev_err(chip->dev, + "[rx1618] [%s] header,tx_cmd,data=0x%x, 0x%x, 0x%x, 0x%x, 0x%x \n", + __func__, header, tx_cmd, data1, data2, data3); + + rx1618_write(chip, PRIVATE_PRODUCT_TEST_CMD, + REG_RX_SENT_CMD); //sent test cmd + rx1618_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + break; + + default: + rx1618_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + msleep(10); + dev_err(chip->dev, "[rx1618] [%s] other private cmd \n", + __func__); + break; + } + + int_done_flag = false; + mutex_unlock(&chip->wireless_chg_int_lock); + + dev_err(chip->dev, "[rx1618] [%s] exit \n", __func__); + + return; +} + +static irqreturn_t rx1618_chg_stat_handler(int irq, void *dev_id) +{ + struct rx1618_chg *chip = dev_id; + u8 rev_cmd = 0; + + mutex_lock(&chip->irq_complete); + + if (!int_done_flag) { + rx1618_read(chip, &rev_cmd, REG_RX_REV_CMD); + if (rev_cmd == 0) { + mdelay(100); + int_done_flag = false; + //chip->online = 0; + g_light_screen_flag = 0; + g_cali_done_flag = 0; + g_id_done_flag = 0; + g_sar_done_flag = 0; + g_fast_chg_flag = 0; + g_usb_type_flag = 0; + g_epp_or_bpp = BPP_MODE; + chip->epp = 0; + chip->auth = 0; + cancel_delayed_work_sync(&chip->wireless_work); + cancel_delayed_work_sync(&chip->wireless_int_work); + dev_err(chip->dev, "[rx1618] [%s] Wireless Offline \n", + __func__); + } else { + int_done_flag = true; + //chip->online = 1; + + schedule_delayed_work(&chip->wireless_work, 0); + schedule_delayed_work(&chip->wireless_int_work, 0); + dev_err(chip->dev, "[rx1618] [%s] Wireless Online \n", + __func__); + } + } + + mutex_unlock(&chip->irq_complete); + + dev_err(chip->dev, "[rx1618] [%s] enter \n", __func__); + + return IRQ_HANDLED; +} + +static int rx1618_parse_dt(struct rx1618_chg *chip) +{ + int ret = 0; + + struct device_node *node = chip->dev->of_node; + if (!node) { + dev_err(chip->dev, "[rx1618] [%s] No DT data Failing Probe\n", + __func__); + return -EINVAL; + } + + //Get the Interrupt GPIO resource + chip->irq_gpio = of_get_named_gpio(node, "rx1618_irq_gpio", 0); + if (gpio_is_valid(chip->irq_gpio)) { + ret = gpio_request(chip->irq_gpio, "rx1618_irq_gpio"); + if (ret) { + dev_err(chip->dev, + "[rx1618] [%s] irq gpio request failed, ret = %d\n", + __func__, ret); + return -EPROBE_DEFER; + } + ret = gpio_direction_input(chip->irq_gpio); + if (ret) { + dev_err(chip->dev, + "[rx1618] [%s] set direction failed, ret = %d\n", + __func__, ret); + goto fail_irq_gpio; + } + + chip->client->irq = gpio_to_irq(chip->irq_gpio); + if (chip->client->irq) { + dev_err(chip->dev, + "[rx1618] [%s] gpio_to_irq Success! \n", + __func__); + } else { + dev_err(chip->dev, "[rx1618] [%s] gpio_to_irq Fail! \n", + __func__); + goto fail_irq_gpio; + } + } else { + goto fail_irq_gpio; + } + + return ret; + +fail_irq_gpio: + dev_err(chip->dev, "[rx1618] [%s] fail_irq_gpio \n", __func__); + if (gpio_is_valid(chip->irq_gpio)) + gpio_free(chip->irq_gpio); + + return ret; +} + +/*************FOD**************/ +//CMD : 0x8A +//DATA0 : Power Level, (2W, 4W, 8W, 6W, 10W… 20W) +//DATA1 : gain * 1024 hight 8bits +//DATA2 : gain * 1024 low 8bits +//DATA3: offset(mW) hight 8bits +//DATA4: offset(mW) low 8bits +/*************FOD**************/ +u8 g_power_level = 0; +u8 g_gain_h = 0; +u8 g_gain_l = 0; +u8 g_offset_h = 0; +u8 g_offset_l = 0; +void FODturring(void) +{ + rx1618_write(g_chip, g_power_level, REG_RX_SENT_DATA1); + rx1618_write(g_chip, g_gain_h, REG_RX_SENT_DATA2); + rx1618_write(g_chip, g_gain_l, REG_RX_SENT_DATA3); + rx1618_write(g_chip, g_offset_h, REG_RX_SENT_DATA4); + rx1618_write(g_chip, g_offset_l, REG_RX_SENT_DATA5); + + dev_err(g_chip->dev, + "[rx1618] [%s] FODturring:g_power_level,g_gain_h,g_gain_l,g_offset_h,g_offset_l %d,%d,%d,%d,%d\n", + __func__, g_power_level, g_gain_h, g_gain_l, g_offset_h, + g_offset_l); + + msleep(5); + + rx1618_write(g_chip, PRIVATE_FOD_TEST_CMD, REG_RX_SENT_CMD); + rx1618_write(g_chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); +} + +static ssize_t chip_fod_power_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int index; + index = (int)simple_strtoul(buf, NULL, 10); + + g_power_level = (index & 0xff); + dev_err(g_chip->dev, "[rx1618] [%s] g_power_level=0x%x \n", __func__, + g_power_level); + + return count; +} + +static ssize_t chip_fod_gain_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u16 index; + index = (u16)simple_strtoul(buf, NULL, 10); + + g_gain_l = (index & 0x00ff); + g_gain_h = (index & 0xff00) >> 8; + + dev_err(g_chip->dev, "[rx1618] [%s] g_gain_l=0x%x, g_gain_h=0x%x \n", + __func__, g_gain_l, g_gain_h); + + return count; +} + +static ssize_t chip_fod_offset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u16 index; + index = (u16)simple_strtoul(buf, NULL, 10); + + g_offset_l = (index & 0x00ff); + g_offset_h = (index & 0xff00) >> 8; + + dev_err(g_chip->dev, + "[rx1618] [%s] g_offset_l=0x%x, g_offset_h=0x%x \n", __func__, + g_offset_l, g_offset_h); + + FODturring(); + + return count; +} + +static ssize_t chip_ibuck_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int ibuck = 0; + + ibuck = rx1618_get_rx_ibuck(g_chip); + + return sprintf(buf, "rx1618 Ibuck: %d mA\n", ibuck); +} + +static ssize_t chip_vrect_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int vrect = 0; + + vrect = rx1618_get_rx_vrect(g_chip); + + return sprintf(buf, "rx1618 Vrect : %d mV\n", vrect); +} + +static ssize_t chip_irect_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int irect = 0; + + irect = rx1618_get_rx_irect(g_chip); + + return sprintf(buf, "rx1618 Irect: %d mA\n", irect); +} + +static ssize_t chip_vbuck_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int index; + + index = (int)simple_strtoul(buf, NULL, 10); + dev_err(g_chip->dev, "[rx1618] [%s] --Store output_voltage = %d\n", + __func__, index); + if ((index < 5166) || (index > 9609)) { + dev_err(g_chip->dev, + "[rx1618] [%s] Store Voltage %s is invalid\n", __func__, + buf); + rx1618_set_vbuck(g_chip, 0); + return count; + } + + rx1618_set_vbuck(g_chip, index); + + return count; +} + +static ssize_t chip_vbuck_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int vbuck = 0; + + vbuck = rx1618_get_rx_vbuck(g_chip); + + return sprintf(buf, "rx1618 Vbuck : %d mV\n", vbuck); +} + +static ssize_t chip_ap_req_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + //int index; + //index = (int)simple_strtoul(buf, NULL, 10); + return count; +} + +static ssize_t chip_ap_req_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 data = 0; + return sprintf(buf, "AP REQ DATA : 0x%x \n", data); +} + +static ssize_t chip_firmware_update_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + bool enable = strncmp(buf, "update", 6) ? false : true; + + dev_err(g_chip->dev, "[rx1618] [%s] Firmware Update enable = %d\n", + __func__, enable); + if (enable) { + int ret = rx1618_download_firmware(g_chip); + if (!ret) { + dev_err(g_chip->dev, + "[rx1618] [%s] Firmware Update failed! Please try again! \n", + __func__); + } + dev_err(g_chip->dev, + "[rx1618] [%s] Firmware Update Success!!! \n", + __func__); + } + + return count; +} + +static ssize_t chip_firmware_update_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + bool ret = rx1618_check_firmware(g_chip); + if (ret) { + return sprintf(buf, + "rx1618_download_firmware check Success!!!\n"); + } else { + return sprintf(buf, "rx1618_download_firmware check Fail!!!\n"); + } +} + +static ssize_t chip_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + //bool enable = strncmp(buf, "1", 1) ? false : true; + + //rx1618_chip_enable(g_chip, enable); + //dev_err(g_chip->dev, "[rx1618] [%s] chip enable:%d\n",__func__,enable); + + return count; +} + +static ssize_t chip_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "rx1618 chip enable status: %d \n", + g_chip->chip_enable); +} + +static ssize_t chip_fw_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "Firmware ID: 0x%x \t\n", g_fw_id); +} + +static ssize_t chip_hw_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "Hardware ID: 0x%x, 0x%x \t\n", g_hw_id_h, + g_hw_id_l); +} + +static ssize_t chip_vbuck_calibration_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int index = 0; + + index = (int)simple_strtoul(buf, NULL, 10); + + g_Delta = index; + dev_err(g_chip->dev, "[rx1618] [%s] g_Delta = %d \n", __func__, + g_Delta); + + return count; +} + +static DEVICE_ATTR(chip_fod_power, S_IWUSR, NULL, chip_fod_power_store); +static DEVICE_ATTR(chip_fod_gain, S_IWUSR, NULL, chip_fod_gain_store); +static DEVICE_ATTR(chip_fod_offset, S_IWUSR, NULL, chip_fod_offset_store); +static DEVICE_ATTR(chip_vrect, S_IRUGO, chip_vrect_show, NULL); +static DEVICE_ATTR(chip_irect, S_IRUGO, chip_irect_show, NULL); +static DEVICE_ATTR(chip_vbuck_calibration, S_IWUSR, NULL, + chip_vbuck_calibration_store); +static DEVICE_ATTR(chip_firmware_update, S_IWUSR | S_IRUGO, + chip_firmware_update_show, chip_firmware_update_store); +static DEVICE_ATTR(chip_fw_version, S_IRUGO, chip_fw_version_show, NULL); +static DEVICE_ATTR(chip_hw_version, S_IRUGO, chip_hw_version_show, NULL); +static DEVICE_ATTR(chip_enable, S_IWUSR | S_IRUGO, chip_enable_show, + chip_enable_store); +static DEVICE_ATTR(chip_vbuck, S_IWUSR | S_IRUGO, chip_vbuck_show, + chip_vbuck_store); +static DEVICE_ATTR(chip_ibuck, S_IRUGO, chip_ibuck_show, NULL); +static DEVICE_ATTR(chip_ap_req, S_IWUSR | S_IRUGO, chip_ap_req_show, + chip_ap_req_store); + +static struct attribute *rx1618_sysfs_attrs[] = { + &dev_attr_chip_vrect.attr, + &dev_attr_chip_irect.attr, + &dev_attr_chip_fw_version.attr, + &dev_attr_chip_hw_version.attr, + &dev_attr_chip_enable.attr, + &dev_attr_chip_vbuck.attr, + &dev_attr_chip_ibuck.attr, + &dev_attr_chip_ap_req.attr, + &dev_attr_chip_firmware_update.attr, + &dev_attr_chip_vbuck_calibration.attr, + &dev_attr_chip_fod_power.attr, + &dev_attr_chip_fod_gain.attr, + &dev_attr_chip_fod_offset.attr, + NULL, +}; + +static const struct attribute_group rx1618_sysfs_group_attrs = { + .attrs = rx1618_sysfs_attrs, +}; + +#if 1 +static enum power_supply_property rx1618_wireless_properties[] = { + /* + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_CHARGING_ENABLED, + POWER_SUPPLY_PROP_RX_CHIP_ID, //RX chip id + POWER_SUPPLY_PROP_RX_VRECT, //RX vrect + POWER_SUPPLY_PROP_RX_IOUT, //RX output current + POWER_SUPPLY_PROP_RX_VOUT, //RX output voltage + POWER_SUPPLY_PROP_RX_ILIMIT, //RX Main LDO output current limit + POWER_SUPPLY_PROP_VOUT_SET, //Vout voltage set + */ + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, +}; + +static int rx1618_wireless_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + int ret; + struct rx1618_chg *chip = power_supply_get_drvdata(psy); + int data; + + switch (prop) { + /* + case POWER_SUPPLY_PROP_PRESENT: + break; + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + rx1618_chip_enable(chip, val->intval); + break; + case POWER_SUPPLY_PROP_VOUT_SET: + ret = rx1618_set_vbuck(chip, val->intval); + if(ret < 0) + return ret; + break; + */ + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + data = val->intval / 1000; + ret = rx1618_set_vbuck(chip, data); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rx1618_wireless_get_property(struct power_supply *psy, + enum power_supply_property prop, + union power_supply_propval *val) +{ + struct rx1618_chg *chip = power_supply_get_drvdata(psy); + + switch (prop) { + /* + case POWER_SUPPLY_PROP_PRESENT: + val->intval = rx1618_is_rx_present(chip); + break; + case POWER_SUPPLY_PROP_ONLINE: + val->intval = chip->online; + break; + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + val->intval = chip->chip_enable; + break; + case POWER_SUPPLY_PROP_RX_CHIP_ID: + val->intval = rx1618_get_rx_chip_id(chip); + break; + case POWER_SUPPLY_PROP_RX_VRECT: + val->intval = rx1618_get_rx_vrect(chip); + break; + case POWER_SUPPLY_PROP_RX_IOUT: + val->intval = rx1618_get_rx_ibuck(chip); + break; + case POWER_SUPPLY_PROP_RX_VOUT: + val->intval = rx1618_get_rx_vbuck(chip); + break; + case POWER_SUPPLY_PROP_VOUT_SET: + val->intval = 0; + break; + */ + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + val->intval = rx1618_get_rx_vbuck(chip); + break; + default: + return -EINVAL; + } + return 0; +} +#endif + +// first step: define regmap_config +static const struct regmap_config rx1618_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0xFFFF, +}; + +static int rx1618_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + int rc; + + switch (psp) { + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + return 1; + default: + rc = 0; + break; + } + + return rc; +} + +static int rx1618_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct rx1618_chg *chip; + struct kobject *rx1618_kobj; + + struct power_supply_config wip_psy_cfg = {}; + int hw_id; + /* + struct power_supply *batt_psy; + + batt_psy = power_supply_get_by_name("battery"); + if (!batt_psy) { + dev_err(&client->dev, "Battery supply not found; defer probe\n"); + return -EPROBE_DEFER; + } + */ + + hw_id = get_hw_country_version(); + dev_info(&client->dev, "[rx1618] %s: hw_id is %d\n", __func__, hw_id); + if (hw_id) /*hw_id=1 is idt */ + return 0; + + chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) { + dev_err(&client->dev, + "i2c allocated device info data failed!\n"); + return -ENOMEM; + } + + chip->regmap = regmap_init_i2c(client, &rx1618_regmap_config); + if (!chip->regmap) { + dev_err(&client->dev, "parent regmap is missing\n"); + return -EINVAL; + } + + chip->client = client; + chip->dev = &client->dev; + + //chip->batt_psy = batt_psy; + //chip->online = 0; + chip->chip_enable = false; + + device_init_wakeup(&client->dev, true); + i2c_set_clientdata(client, chip); + + rx1618_parse_dt(chip); + + mutex_init(&chip->irq_complete); + mutex_init(&chip->wireless_chg_lock); + mutex_init(&chip->wireless_chg_int_lock); + INIT_DELAYED_WORK(&chip->wireless_work, rx1618_wireless_work); + INIT_DELAYED_WORK(&chip->wireless_int_work, rx1618_wireless_int_work); + + chip->wip_psy_d.name = "rx1618"; + chip->wip_psy_d.type = POWER_SUPPLY_TYPE_WIRELESS; + chip->wip_psy_d.get_property = rx1618_wireless_get_property; + chip->wip_psy_d.set_property = rx1618_wireless_set_property; + chip->wip_psy_d.properties = rx1618_wireless_properties; + chip->wip_psy_d.num_properties = ARRAY_SIZE(rx1618_wireless_properties); + chip->wip_psy_d.property_is_writeable = rx1618_prop_is_writeable, + + wip_psy_cfg.drv_data = chip; + + chip->wip_psy = devm_power_supply_register(chip->dev, &chip->wip_psy_d, + &wip_psy_cfg); + if (IS_ERR(chip->wip_psy)) { + dev_err(chip->dev, "Couldn't register wip psy rc=%ld\n", + PTR_ERR(chip->wip_psy)); + return ret; + } + + if (chip->client->irq) { + ret = devm_request_threaded_irq( + &chip->client->dev, chip->client->irq, NULL, + rx1618_chg_stat_handler, + (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | + IRQF_ONESHOT), + "rx1618_chg_stat_irq", chip); + if (ret) { + dev_err(chip->dev, "Failed irq = %d ret = %d\n", + chip->client->irq, ret); + } + } + + enable_irq_wake(chip->client->irq); + + rx1618_kobj = kobject_create_and_add("rx1618", NULL); + if (!rx1618_kobj) { + dev_err(chip->dev, "sysfs_create_group fail"); + goto error_sysfs; + } + ret = sysfs_create_group(rx1618_kobj, &rx1618_sysfs_group_attrs); + if (ret < 0) { + dev_err(chip->dev, "sysfs_create_group fail %d\n", ret); + goto error_sysfs; + } + + g_chip = chip; + + determine_initial_status(chip); + rx1618_chip_init(chip); + + rx1618_dump_reg(); + + dev_err(chip->dev, "[rx1618] [%s] success! \n", __func__); + + return 0; + +error_sysfs: + sysfs_remove_group(rx1618_kobj, &rx1618_sysfs_group_attrs); + dev_err(chip->dev, "[rx1618] [%s] rx1618 probe error_sysfs! \n", + __func__); + + mutex_destroy(&chip->irq_complete); + mutex_destroy(&chip->wireless_chg_lock); + mutex_destroy(&chip->wireless_chg_int_lock); + if (chip->irq_gpio > 0) + gpio_free(chip->irq_gpio); + + return 0; +} + +static int rx1618_remove(struct i2c_client *client) +{ + struct rx1618_chg *chip = i2c_get_clientdata(client); + + mutex_destroy(&chip->irq_complete); + cancel_delayed_work_sync(&chip->wireless_work); + cancel_delayed_work_sync(&chip->wireless_int_work); + + return 0; +} + +static const struct i2c_device_id rx1618_id[] = { + { rx1618_DRIVER_NAME, 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, rx1618_id); + +static struct of_device_id rx1618_match_table[] = { + { + .compatible = "nuvolta,wl_charger_rx1618", + }, + {} +}; + +static struct i2c_driver rx1618_driver = { + .driver = { + .name = rx1618_DRIVER_NAME, + .of_match_table = rx1618_match_table, + }, + .probe = rx1618_probe, + .remove = rx1618_remove, + .id_table = rx1618_id, +}; + +static int __init rx1618_init(void) +{ + int ret; + + ret = i2c_add_driver(&rx1618_driver); + if (ret) + printk(KERN_ERR "rx1618 i2c driver init failed!\n"); + + return ret; +} + +static void __exit rx1618_exit(void) +{ + i2c_del_driver(&rx1618_driver); +} + +module_init(rx1618_init); +module_exit(rx1618_exit); + +MODULE_AUTHOR("colin"); +MODULE_DESCRIPTION("NUVOLTA Wireless Power Charger Monitor driver"); +MODULE_LICENSE("GPL/BSD"); diff --git a/drivers/power/supply/nuvolta/rx1618.h b/drivers/power/supply/nuvolta/rx1618.h new file mode 100644 index 000000000000..dd4debdd0994 --- /dev/null +++ b/drivers/power/supply/nuvolta/rx1618.h @@ -0,0 +1,1263 @@ +/** + * @file rx1618.h + * @author + * @date Tuesday, January 9th 2018 + * + * @brief + * + * + */ +#ifndef __RX1618_H__ +#define __RX1618_H__ + +#define rx1618_DRIVER_NAME "rx1618" +#define rx1618_I2C_ADDR 0x60 + +/* bits mask */ +#define BIT0 (1 << 0) +#define BIT1 (1 << 1) +#define BIT2 (1 << 2) +#define BIT3 (1 << 3) +#define BIT4 (1 << 4) +#define BIT5 (1 << 5) +#define BIT6 (1 << 6) +#define BIT7 (1 << 7) + +const u8 fw_data[] = { + 0x60, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, + 0xC8, 0x01, 0x00, 0x00, 0xC8, 0x01, 0x00, 0x00, 0x84, 0x32, 0x00, 0x00, + 0x1C, 0x2D, 0x00, 0x00, 0x9C, 0x32, 0x00, 0x00, 0xA4, 0x32, 0x00, 0x00, + 0xAC, 0x32, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, 0x1C, 0x2B, 0x00, 0x00, + 0x3C, 0x2D, 0x00, 0x00, 0xB4, 0x32, 0x00, 0x00, 0xBC, 0x32, 0x00, 0x00, + 0xD0, 0x32, 0x00, 0x00, 0x58, 0x33, 0x00, 0x00, 0x94, 0x33, 0x00, 0x00, + 0x9C, 0x33, 0x00, 0x00, 0xA4, 0x33, 0x00, 0x00, 0xAC, 0x33, 0x00, 0x00, + 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, + 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, + 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, + 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, + 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, 0xB4, 0x33, 0x00, 0x00, + 0xB4, 0x33, 0x00, 0x00, 0x44, 0x74, 0x89, 0x74, 0x40, 0x3A, 0x0A, 0x0C, + 0xC3, 0x6C, 0x00, 0x20, 0x00, 0x2A, 0x89, 0x74, 0x08, 0x58, 0x20, 0xA3, + 0x00, 0x23, 0x0E, 0x64, 0xFD, 0x0B, 0x3C, 0x78, 0xC2, 0x14, 0x89, 0x74, + 0x40, 0x3A, 0x0C, 0x0C, 0xA3, 0x5A, 0x55, 0x75, 0x00, 0x25, 0x00, 0x33, + 0x4C, 0x58, 0x8C, 0x59, 0x80, 0x84, 0x80, 0xA2, 0x00, 0x23, 0x4E, 0x65, + 0xFA, 0x0B, 0x82, 0x14, 0x67, 0x10, 0x60, 0x83, 0x41, 0x3B, 0x03, 0x08, + 0x00, 0x30, 0x02, 0x04, 0x05, 0x10, 0x3C, 0x78, 0x04, 0x10, 0x3C, 0x78, + 0x00, 0x32, 0x62, 0x10, 0x40, 0xA3, 0x3C, 0x78, 0x14, 0x00, 0x00, 0x20, + 0x15, 0x00, 0x00, 0x20, 0x72, 0x10, 0x03, 0xC0, 0x20, 0x64, 0x52, 0x10, + 0x02, 0xC0, 0x21, 0x64, 0x31, 0x10, 0x87, 0x6F, 0xF1, 0x10, 0xD2, 0x10, + 0xB2, 0x10, 0x9C, 0x65, 0x07, 0x08, 0x80, 0x95, 0x80, 0xB7, 0x03, 0x25, + 0x03, 0x27, 0x9C, 0x65, 0xFB, 0x0F, 0x6F, 0x10, 0x4F, 0x10, 0x8E, 0x60, + 0x42, 0x4A, 0x40, 0x3A, 0x07, 0x0C, 0x00, 0x31, 0x20, 0xB3, 0x03, 0x23, + 0x00, 0x2A, 0x40, 0x3A, 0xFC, 0x0B, 0x00, 0xE0, 0x01, 0x13, 0x00, 0xE0, + 0xD3, 0x1A, 0x00, 0x04, 0x00, 0x01, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, + 0xF8, 0x01, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x14, 0x00, 0x00, 0x20, + 0xC4, 0x39, 0x00, 0x00, 0x14, 0x00, 0x00, 0x20, 0x28, 0x01, 0x00, 0x20, + 0x00, 0xE0, 0x16, 0x18, 0x00, 0xC0, 0x20, 0x40, 0x3C, 0x78, 0x00, 0x00, + 0x3C, 0x78, 0x00, 0x00, 0x03, 0x32, 0x62, 0x10, 0x40, 0xA3, 0x3C, 0x78, + 0x2B, 0x00, 0x00, 0x20, 0xD1, 0x14, 0x01, 0x75, 0x00, 0xE0, 0x56, 0x0F, + 0x40, 0x38, 0x04, 0x0C, 0x00, 0x32, 0x6A, 0x11, 0x40, 0xA3, 0x40, 0x33, + 0xD2, 0x64, 0x24, 0x0C, 0x0C, 0x65, 0x06, 0x0C, 0x41, 0x3C, 0x16, 0x0C, + 0x44, 0x3C, 0x2E, 0x08, 0x1D, 0x04, 0x80, 0x33, 0x61, 0x43, 0xD2, 0x64, + 0x19, 0x0C, 0x80, 0x33, 0x62, 0x43, 0xD2, 0x64, 0x15, 0x0C, 0x80, 0x33, + 0xD2, 0x64, 0x22, 0x08, 0x03, 0x32, 0x7E, 0x10, 0x40, 0xA3, 0x03, 0x30, + 0x00, 0xE0, 0x28, 0x0F, 0x1B, 0x04, 0x7B, 0x10, 0x60, 0x83, 0x42, 0x3B, + 0x17, 0x08, 0x00, 0x30, 0x00, 0x31, 0x00, 0x32, 0x00, 0xE0, 0x6E, 0x17, + 0x11, 0x04, 0x76, 0x10, 0x60, 0x83, 0x42, 0x3B, 0x0D, 0x08, 0x03, 0x32, + 0x73, 0x10, 0x40, 0xA3, 0x0C, 0x30, 0x00, 0xE0, 0xAD, 0x0A, 0x06, 0x30, + 0x00, 0xE0, 0x10, 0x0F, 0x00, 0x30, 0x00, 0xE0, 0x73, 0x03, 0x6E, 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0x00, + 0x0E, 0x07, 0x00, 0x00, 0x0E, 0x07, 0x00, 0x00, 0x0E, 0x07, 0x00, 0x00, + 0x38, 0x07, 0x00, 0x00, 0x44, 0x07, 0x00, 0x00, 0x52, 0x07, 0x00, 0x00, + 0x62, 0x07, 0x00, 0x00, 0xD0, 0x08, 0x00, 0x00, 0xE2, 0x08, 0x00, 0x00, + 0xF4, 0x08, 0x00, 0x00, 0x16, 0x09, 0x00, 0x00, 0x28, 0x09, 0x00, 0x00, + 0x28, 0x09, 0x00, 0x00, 0x05, 0x06, 0x04, 0x00, 0x06, 0x06, 0x06, 0x06, + 0x06, 0x0F, 0x14, 0x14, 0x06, 0x28, 0x28, 0x00, 0xE4, 0x09, 0x00, 0x00, + 0xCE, 0x09, 0x00, 0x00, 0xFA, 0x09, 0x00, 0x00, 0x10, 0x0A, 0x00, 0x00, + 0x26, 0x0A, 0x00, 0x00, 0x66, 0x0A, 0x00, 0x00, 0xF8, 0x0B, 0x00, 0x00, + 0x90, 0x0B, 0x00, 0x00, 0xC8, 0x19, 0x00, 0x00, 0x52, 0x1A, 0x00, 0x00, + 0x52, 0x1A, 0x00, 0x00, 0x52, 0x1A, 0x00, 0x00, 0xF2, 0x19, 0x00, 0x00, + 0xFA, 0x19, 0x00, 0x00, 0x0A, 0x1A, 0x00, 0x00, 0x12, 0x1A, 0x00, 0x00, + 0x1A, 0x1A, 0x00, 0x00, 0x22, 0x1A, 0x00, 0x00, 0x2A, 0x1A, 0x00, 0x00, + 0x84, 0x09, 0x00, 0x00, 0xF8, 0x04, 0x00, 0x00, 0xE4, 0x01, 0x00, 0x00, + 0xBC, 0x02, 0x00, 0x00, 0xD4, 0x01, 0x00, 0x00, 0xBC, 0x0C, 0x00, 0x00, + 0x90, 0x05, 0x00, 0x00, 0xE4, 0x1B, 0x00, 0x00, 0x60, 0x1D, 0x00, 0x00, + 0x5C, 0x29, 0x00, 0x00, 0x94, 0x22, 0x00, 0x00, 0xD4, 0x10, 0x00, 0x00, + 0xC8, 0x25, 0x00, 0x00, 0x48, 0x18, 0x00, 0x00, 0xA4, 0x10, 0x00, 0x00, + 0x34, 0x11, 0x00, 0x00, 0xBC, 0x31, 0x00, 0x00, 0xAC, 0x09, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD8, 0x04, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x50, 0x11, 0x00, 0x00, 0x68, 0x09, 0x00, 0x00, + 0x01, 0x02, 0x04, 0x08, 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10, 0xF0, 0xE1, 0xD2, 0xC3 +}; + +#endif diff --git a/drivers/power/supply/nuvolta/rx1619.c b/drivers/power/supply/nuvolta/rx1619.c new file mode 100644 index 000000000000..62fa5b97cc63 --- /dev/null +++ b/drivers/power/supply/nuvolta/rx1619.c @@ -0,0 +1,4695 @@ +/** + * Copyright “Copyright (C) 2019 XiaoMi, Inc + * Copyright (C) 2021 XiaoMi, Inc. + * + * L.D + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +/* add for get hw country */ +#include +#include "rx1619.h" + +#define rx1619_DRIVER_NAME "rx1619" + +#define GOOD 0 +#define STILL 1 +#define LIMIT 2 +#define EPP_MODE 1 +#define BPP_MODE 0 +#define MIN_VOUT 4000 +#define MAX_VOUT 15000 +#define AP_REV_DATA_OK 0xaa +#define AP_SENT_DATA_OK 0x55 +#define PRIVATE_VBUCK_SET_CMD 0x80 +#define PRIVATE_ID_CMD 0x86 +#define PRIVATE_USB_TYPE_CMD 0x87 +#define PRIVATE_FAST_CHG_CMD 0x88 +#define PRIVATE_PRODUCT_TEST_CMD 0x8D +#define PRIVATE_TX_HW_ID_CMD 0x8b +#define FW_ERROR_CODE 0xFE +#define FW_EMPTY_CODE 0xFF +/*adapter type*/ +#define ADAPTER_NONE 0x00 +#define ADAPTER_SDP 0x01 +#define ADAPTER_CDP 0x02 +#define ADAPTER_DCP 0x03 +#define ADAPTER_QC2 0x05 +#define ADAPTER_QC3 0x06 +#define ADAPTER_PD 0x07 +#define ADAPTER_AUTH_FAILED 0x08 +#define ADAPTER_XIAOMI_QC3 0x09 +#define ADAPTER_XIAOMI_PD 0x0a +#define ADAPTER_ZIMI_CAR_POWER 0x0b +#define ADAPTER_XIAOMI_PD_40W 0x0c +#define ADAPTER_VOICE_BOX 0x0d +#define ADAPTER_XIAOMI_PD_50W 0x0e +#define ADAPTER_XIAOMI_PD_60W 0x0f + +//0x000b[0:3] 0000:no charger, 0001:SDP, 0010:CDP, 0011:DCP, 0101:QC2-other, +//0110:QC3-other, 0111:PD, 1000:fail charger, 1001:QC3-27W, 1010:PD-27W +#define EPP_MODE_CURRENT 600000 +#define DC_OTHER_CURRENT 750000 +#define DC_LOW_CURRENT 200000 //200mA +#define DC_DCP_CURRENT 700000 +#define DC_CDP_CURRENT 800000 +#define DC_QC2_CURRENT 1000000 +#define DC_QC3_CURRENT 1800000 +#define DC_QC3_BPP_CURRENT 900000 +#define DC_TURBO_CURRENT 1100000 +#define DC_QC3_20W_CURRENT 2100000 //2.1A +#define DC_PD_CURRENT 1000000 +#define DC_PD_20W_CURRENT 2000000 //2A +#define DC_PD_40W_CURRENT 3100000 //3.1A +#define DC_BPP_CURRENT 850000 +#define DC_SDP_CURRENT 500000 +#define SCREEN_OFF_FUL_CURRENT 250000 +#define DC_FULL_CURRENT 350000 +#define DC_BPP_AUTH_FAIL_CURRENT 750000 +#define USB_20W_PLUS_BASE_CURRENT_UA 1000000 //1.0A +#define USB_20W_PLUS_CURRENT_UA 1800000 //1.8A + +#define ADAPTER_DEFAULT_VOL 6000 +#define ADAPTER_BPP_LIMIT_VOL 6500 +#define ADAPTER_VOUT_LIMIT_VOL 6000 +#define ADAPTER_BPP_PLUS_VOL 9000 +#define ADAPTER_EPP_QC3_VOL 11000 +#define EPP_VOL_THRESHOLD 12000 +#define ADAPTER_EPP_MI_VOL 15000 +#define ADAPTER_BPP_QC2_VOL 6500 + +#define LIMIT_SOC 95 +#define FULL_SOC 100 +#define LIMIT_EPP_IOUT 500 +#define EXCHANGE_9V 0x0 +#define EXCHANGE_5V 0x1 +#define EXCHANGE_15V 0x0 +#define EXCHANGE_10V 0x1 +#define ICL_EXCHANGE_COUNT 2 /*5 = 1min*/ +#define LIMIT_EPP_IOUT 500 +#define LIMIT_BPP_IOUT 500 +#define HIGH_THERMAL_LEVEL_THR 12 + +/* used registers define */ +#define REG_RX_SENT_CMD 0x0000 +#define REG_RX_SENT_DATA1 0x0001 +#define REG_RX_SENT_DATA2 0x0002 +#define REG_RX_SENT_DATA3 0x0003 +#define REG_RX_SENT_DATA4 0x0004 +#define REG_RX_SENT_DATA5 0x0005 +#define REG_RX_SENT_DATA6 0x0006 +#define REG_RX_REV_CMD 0x0020 +#define REG_RX_REV_DATA1 0x0021 +#define REG_RX_REV_DATA2 0x0022 +#define REG_RX_REV_DATA3 0x0023 +#define REG_RX_REV_DATA4 0x0024 + +#define REG_CEP_VALUE 0x0008 +#define REG_RX_VOUT 0x0009 +#define REG_RX_VRECT 0x000a +#define REG_RX_IOUT 0x000b + +#define REG_AP_RX_COMM 0x000C +#define ADDR_RX 256 +#define ADDR_TX 4864 + +#define ID_CMD 0x3b +#define AUTH_CMD 0x86 +#define UUID_CMD 0x90 + +u8 fod_param[8] = { 0x44, 0x64, 0x44, 0x78, 0x3A, 0x67, 0x37, 0x67 }; + +static struct rx1619_chg *g_chip; +static int g_Delta; +static u8 g_project_id_h; +static u8 g_project_id_l; +static u8 g_fw_boot_id; +static u8 g_id_done_flag; +static u8 g_fw_rx_id; +static u8 g_fw_tx_id; +static u8 g_hw_id_h, g_hw_id_l; +static u8 g_epp_or_bpp = BPP_MODE; +static u8 g_USB_TYPE = 0; +static int g_current_now = DC_LOW_CURRENT; +static bool g_rx1619_restart_flag = false; +static bool g_rx1619_first_flag; +static u8 rx_bin_project_id_h; +static u8 rx_bin_project_id_l; +static bool is_nvt_rx; + +static u32 g_fw_data_lenth; +static u8 boot_fw_version; +static u8 rx_fw_version; +static u8 tx_fw_version; + +static int rx_set_enable_mode(struct rx1619_chg *chip, int enable); +static int rx_get_reverse_chg_mode(struct rx1619_chg *chip); +static int rx_set_reverse_gpio(struct rx1619_chg *chip, int enable); +static int rx_set_reverse_chg_mode(struct rx1619_chg *chip, int enable); + +#define BOOT_AREA 0 +#define RX_AREA 1 +#define TX_AREA 2 + +#define NORMAL_MODE 0x1 +#define TAPER_MODE 0x2 +#define FULL_MODE 0x3 +#define RECHG_MODE 0x4 + +//fw version to update +#define FW_VERSION 0x15 + +struct rx1619_chg { + char *name; + struct i2c_client *client; + struct device *dev; + struct regmap *regmap; + unsigned int tx_on_gpio; + unsigned int irq_gpio; + unsigned int power_good_gpio; + unsigned int power_good_irq; + unsigned int enable_gpio; + unsigned int chip_enable; + int online; + struct pinctrl *rx_pinctrl; + struct pinctrl_state *rx_gpio_active; + struct pinctrl_state *rx_gpio_suspend; + struct delayed_work wireless_int_work; + struct delayed_work wpc_det_work; + struct delayed_work chg_monitor_work; + struct delayed_work chg_detect_work; + struct delayed_work reverse_sent_state_work; + struct delayed_work reverse_chg_state_work; + struct delayed_work reverse_dping_state_work; + struct delayed_work dc_check_work; + struct delayed_work cmd_timeout_work; + struct delayed_work fw_download_work; + struct delayed_work pan_tx_work; + struct delayed_work voice_tx_work; + struct delayed_work rx_first_boot; + struct mutex wireless_chg_lock; + struct mutex wireless_chg_int_lock; + struct mutex sysfs_op_lock; + + struct power_supply *wip_psy; + struct power_supply *dc_psy; + struct power_supply_desc wip_psy_d; + struct power_supply *wireless_psy; + struct power_supply *batt_psy; + struct power_supply *usb_psy; + struct power_supply *pc_port_psy; + struct power_supply *ln_psy; + struct alarm reverse_dping_alarm; + struct alarm reverse_chg_alarm; + struct alarm cmd_timeout_alarm; + int epp; + int auth; + int op_mode; + int dcin_present; + u8 epp_max_power; + int target_vol; + int target_curr; + int is_vin_limit; + int epp_exchange; + int count_5v; + int count_9v; + int count_10v; + int count_15v; + int status; + int last_vin; + int last_icl; + int exchange; + int last_qc3_icl; + int power_off_mode; + + /* product related */ + bool wireless_by_usbin; + int power_good_flag; + int ss; + int is_reverse_chg; + int is_reverse_gpio; + u8 fod_mode; + int is_car_tx; + int is_voice_box_tx; + int is_compatible_hwid; + int is_f1_tx; + u8 epp_tx_id_h; + u8 epp_tx_id_l; + u8 *rx_fw_bin; + int rx_fw_len; + bool enabled_aicl; + bool fw_update; + int fw_version; + int chip_ok; + int hw_country; + int reverse_gpio_state; + int is_otg_insert; + int is_pan_tx; + bool disable_bq; + struct votable *fcc_votable; +}; + +/*extern char *saved_command_line; +static int get_board_version(void) +{ + char boot[5] = {'\0'}; + char *match = (char *) strnstr(saved_command_line, + "androidboot.hwlevel=", + strlen(saved_command_line)); + if (match) { + memcpy(boot, (match + strlen("androidboot.hwlevel=")), + sizeof(boot) - 1); + printk("%s: hwlevel is %s\n", __func__, boot); + if (!strncmp(boot, "P1.2", strlen("P1.2"))) + return 1; + else if (!strncmp(boot, "P1.6", strlen("P1.6"))) + return 1; + } + return 0; +}*/ + +static int rx1619_read(struct rx1619_chg *chip, u8 *val, u16 addr) +{ + unsigned int temp; + int rc; + + rc = regmap_read(chip->regmap, addr, &temp); + if (rc >= 0) { + *val = (u8)temp; + //dev_err(chip->dev, "[rx1619] [%s] [0x%04x] = [0x%x] \n", __func__, addr, *val); + } + + return rc; +} + +static int rx1619_write(struct rx1619_chg *chip, u8 val, u16 addr) +{ + int rc = 0; + + rc = regmap_write(chip->regmap, addr, val); + if (rc >= 0) { + //dev_err(chip->dev, "[rx1619] [%s] [0x%04x] = [0x%x] \n", __func__, addr, *val); + } + + return rc; +} + +//mode1: gain_code = gain/1000*65535/100; offset_code = offset/100 +//mode2,3,4: gain_code = gain/1000*65535; offset_code = offset/10 +void rx1619_set_fod_param(struct rx1619_chg *chip, u8 mode) +{ + rx1619_write(chip, 0x85, REG_RX_SENT_CMD); //send fod parameters + + if (mode == 1) { + rx1619_write(chip, 0x1, REG_RX_SENT_DATA1); + rx1619_write(chip, fod_param[0], REG_RX_SENT_DATA2); + rx1619_write(chip, fod_param[1], REG_RX_SENT_DATA3); + chip->fod_mode = 0x1; + dev_info(chip->dev, "[%s] 0x%x,0x%x \n", __func__, fod_param[0], + fod_param[1]); + } else if (mode == 2) { + rx1619_write(chip, 0x2, REG_RX_SENT_DATA1); + rx1619_write(chip, fod_param[2], REG_RX_SENT_DATA2); + rx1619_write(chip, fod_param[3], REG_RX_SENT_DATA3); + chip->fod_mode = 0x2; + dev_info(chip->dev, "[%s] 0x%x,0x%x \n", __func__, fod_param[2], + fod_param[3]); + } else if (mode == 3) { + rx1619_write(chip, 0x3, REG_RX_SENT_DATA1); + rx1619_write(chip, fod_param[4], REG_RX_SENT_DATA2); + rx1619_write(chip, fod_param[5], REG_RX_SENT_DATA3); + chip->fod_mode = 0x3; + dev_info(chip->dev, "[%s] 0x%x,0x%x \n", __func__, fod_param[4], + fod_param[5]); + } else if (mode == 4) { + rx1619_write(chip, 0x4, REG_RX_SENT_DATA1); + rx1619_write(chip, fod_param[6], REG_RX_SENT_DATA2); + rx1619_write(chip, fod_param[7], REG_RX_SENT_DATA3); + chip->fod_mode = 0x4; + dev_info(chip->dev, "[%s] 0x%x,0x%x \n", __func__, fod_param[6], + fod_param[7]); + } + + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + dev_info(chip->dev, "[%s] mode = 0x%x \n", __func__, mode); +} + +void rx1619_set_adap_vol(struct rx1619_chg *chip, u16 mv) +{ + dev_info(chip->dev, "set adapter vol to %d\n", mv); + rx1619_write(chip, PRIVATE_FAST_CHG_CMD, + REG_RX_SENT_CMD); //0x87 usb type req + rx1619_write(chip, mv & 0xff, REG_RX_SENT_DATA1); //LSB + rx1619_write(chip, (mv >> 8) & 0xff, REG_RX_SENT_DATA2); //MSB + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); +} + +void rx1619_request_uuid(struct rx1619_chg *chip, int is_epp) +{ + rx1619_write(chip, UUID_CMD, REG_RX_SENT_CMD); //0x8f request high addr + + if (is_epp) { + rx1619_write(chip, 0x4C, REG_RX_SENT_DATA1); + chip->is_compatible_hwid = 0; + } else { + rx1619_write(chip, 0x3F, REG_RX_SENT_DATA1); + chip->is_compatible_hwid = 1; + } + + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); //0x8b sent BLEOK +} + +void rx1619_retry_id_auth(struct rx1619_chg *chip) +{ + rx1619_write(chip, PRIVATE_ID_CMD, REG_RX_SENT_CMD); + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); +} + +void rx1619_send_device_auth(struct rx1619_chg *chip) +{ + rx1619_write(chip, PRIVATE_USB_TYPE_CMD, REG_RX_SENT_CMD); + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); +} + +static int rx_get_property_names(struct rx1619_chg *chip) +{ + chip->batt_psy = power_supply_get_by_name("battery"); + if (!chip->batt_psy) { + dev_err(chip->dev, "no batt_psy,return\n"); + return -EINVAL; + } + + chip->dc_psy = power_supply_get_by_name("dc"); + if (!chip->dc_psy) { + dev_err(chip->dev, "no dc_psy,return\n"); + return -EINVAL; + } + + chip->wireless_psy = power_supply_get_by_name("wireless"); + if (!chip->wireless_psy) { + dev_err(chip->dev, "no wireless_psy,return\n"); + return -EINVAL; + } + + chip->usb_psy = power_supply_get_by_name("usb"); + if (!chip->usb_psy) { + dev_err(chip->dev, "[idt] no usb_psy,return\n"); + return -EINVAL; + } + + chip->pc_port_psy = power_supply_get_by_name("pc_port"); + if (!chip->pc_port_psy) { + dev_err(chip->dev, "[idt] no pc_port_psy,return\n"); + return -EINVAL; + } + + return 0; +} +/* +reverse charging function +*/ +unsigned int rx1619_start_tx_function(struct rx1619_chg *chip) +{ + u16 ret = 0; + + ret = rx1619_write(chip, 0x20, 0x000d); //0x10 rx, 0x20 tx + dev_info(chip->dev, "[%s] ret = %d\n", __func__, ret); + + return ret; +} + +unsigned int rx1619_is_tx_mode(struct rx1619_chg *chip) +{ + u8 data = 0; + + rx1619_read(chip, &data, 0x000d); + dev_info(chip->dev, "[%s] data = %d\n", __func__, data); + if (data == 0x20) + return 1; + else + return 0; +} + +/* +0x00 close TX mode +0x11 none otg mode +0x12 otg mode +*/ +/* +unsigned char rx1619_set_tx_mode(struct rx1619_chg *chip, u8 mode) +{ + u8 ret = 0; + + ret = rx1619_write(chip, mode, 0x0000); + dev_info(chip->dev, "[%s] mode = %d\n", __func__, mode); + + return ret; +} +*/ + +/* +unsigned int rx1619_get_tx_iout(struct rx1619_chg *chip) +{ + u8 data = 0; + u32 tx_iout = 0; + + //Iout = 2.5(A)*value/256 + rx1619_read(chip, &data, 0x0008);//0x0008 + tx_iout = 2500*data/256; + dev_err(chip->dev, "[rx1619] [%s] data=%d, tx_iout=%d \n", __func__, data,tx_iout); + + return tx_iout; +} + + +unsigned int rx1619_get_tx_vout(struct rx1619_chg *chip) +{ + u8 data = 0; + u32 tx_vout = 0; + + //Vout = 22.5(V)*value/256 + rx1619_read(chip, &data, 0x0009);//0x0009 + tx_vout = 22500*data/256; + dev_err(chip->dev, "[rx1619] [%s] data=%d, tx_vout=%d \n", __func__, data,tx_vout); + + return tx_vout; +} +*/ + +#define TX_NORMAL 0x00 +#define TX_OVP 0x01 +#define TX_OCP 0x02 +#define TX_UV 0x03 +#define TX_OTP 0x04 +#define TX_FOD 0x05 +#define TX_LOW 0x06 + +unsigned char rx1619_get_tx_status(struct rx1619_chg *chip) +{ + u8 data = 0; + + rx1619_read(chip, &data, 0x000a); //0x000a + dev_err(chip->dev, "[%s] data=%d\n", __func__, data); + + return data; +} + +/* +init 0x00 +ping phase 0x1 +power transfer 0x02 +power limit 0x03 +*/ +#define PING 0x1 +#define TRANSFER 0x2 +#define POWER_LIM 0x3 +#define CONFIGURE_CNF 0x4 +#define CONFIGURE_ERR 0x5 + +unsigned char rx1619_get_tx_phase(struct rx1619_chg *chip) +{ + u8 data = 0; + + rx1619_read(chip, &data, 0x000b); + dev_info(chip->dev, "[%s] data=%d\n", __func__, data); + + return data; +} + +unsigned int rx1619_get_rx_vrect(struct rx1619_chg *chip) +{ + u16 vrect = 0; + u8 data = 0; + + rx1619_read(chip, &data, 0x000A); //vrect-0x000A + vrect = (data * 27500) >> 8; + dev_err(chip->dev, "[rx1619] [%s] data=%d, Vrect=%d mV \n", __func__, + data, vrect); + + return vrect; +} + +unsigned int rx1619_get_rx_vout(struct rx1619_chg *chip) +{ + u16 vout = 0; + u8 data = 0; + + rx1619_read(chip, &data, 0x0009); //vout-0x0009 + vout = (int)(data * 22500) >> 8; + dev_err(chip->dev, "[rx1619] [%s] data=%d, Vout=%d mV \n", __func__, + data, vout); + + return vout; +} + +unsigned int rx1619_get_rx_iout(struct rx1619_chg *chip) +{ + u16 iout = 0; + u8 data = 0; + + rx1619_read(chip, &data, 0x000B); //Iout-0x000B + iout = (int)(data * 2500) >> 8; + dev_err(chip->dev, "[rx1619] [%s] data=%d, iout=%d mA \n", __func__, + data, iout); + + return iout; +} + +int rx1619_set_vout(struct rx1619_chg *chip, int volt) +{ + u8 value_h, value_l, ret; + u16 vout_set, vrect_set; + + if ((volt < 4000) && (volt > 21000)) { + volt = 6000; //6V + } + + volt += g_Delta; + dev_info(chip->dev, "[rx1619] [%s] volt = %d, g_Delta=%d \n", __func__, + volt, g_Delta); + + vout_set = (u16)((volt * 3352) >> 16); //(u16)(volt*1023/20000) + vrect_set = + (u16)(((volt + 200) * 2438) >> 16); //((volt+200)*1023/27500) + /* + dev_info(chip->dev, "[rx1619] [%s] vout_set = 0x%x, vrect_set=0x%x \n", + __func__, vout_set, vrect_set); +*/ + + value_h = (u8)(vout_set >> 8); + value_l = (u8)(vout_set & 0xFF); + ret = rx1619_write(chip, value_h, 0x0001); + ret = rx1619_write(chip, value_l, 0x0002); + /* + dev_info(chip->dev, "[rx1619] [%s] vout value_h = 0x%x, value_l=0x%x \n", + __func__, value_h, value_l); +*/ + + value_h = (u8)(vrect_set >> 8); + value_l = (u8)(vrect_set & 0xFF); + ret = rx1619_write(chip, value_h, 0x0003); + ret = rx1619_write(chip, value_l, 0x0004); + /* + dev_info(chip->dev, "[rx1619] [%s] vrect value_h = 0x%x, value_l=0x%x \n", + __func__, value_h, value_l); +*/ + + ret = rx1619_write(chip, 0x80, 0x0000); + ret = rx1619_write(chip, 0x55, 0x000C); + + return ret; +} + +bool rx1619_is_vout_on(struct rx1619_chg *chip) +{ + bool vout_status = false; + unsigned int voltage = 0; + + voltage = rx1619_get_rx_vout(chip); + + dev_err(chip->dev, "[rx1619] [%s] Vout = %d \n", __func__, voltage); + + if ((voltage > MIN_VOUT) && (voltage < MAX_VOUT)) //4V~15V + { + vout_status = true; + } else { + vout_status = false; + } + + return vout_status; +} + +#define REVERSE_PARAM_CMD 0x13 +#define REVERSE_PARAM_CMD_ADDR 0x0000 +#define REVERSE_PARAM_MODE_ADDE 0x0001 +#define REVERSE_PARAM_IIN_ADDR 0x0002 + +static void rx1619_set_reverse_parameter(struct rx1619_chg *chip, u8 mode, + u8 iin) +{ + dev_info(chip->dev, "mode: %d, iin:%d\n", mode, iin); + rx1619_write(chip, REVERSE_PARAM_CMD, REVERSE_PARAM_CMD_ADDR); + rx1619_write(chip, mode, REVERSE_PARAM_MODE_ADDE); + rx1619_write(chip, iin, REVERSE_PARAM_IIN_ADDR); + return; +} + +#define REVERSE_FOD_COMPENSATION_ADDR 0x0003 +#define REVERSE_FOD_THRESHOLD_ADDR 0x0004 + +static void rx1619_set_reverse_fod(struct rx1619_chg *chip, u8 compensation, + u8 threshold) +{ + dev_info(chip->dev, "compensation: %d, threshold:%d\n", compensation, + threshold); + rx1619_write(chip, compensation, REVERSE_FOD_COMPENSATION_ADDR); + rx1619_write(chip, threshold, REVERSE_FOD_THRESHOLD_ADDR); + return; +} + +static void determine_initial_status(struct rx1619_chg *chip) +{ + bool vout_on = false; + + vout_on = rx1619_is_vout_on(chip); + if (vout_on) { + g_rx1619_restart_flag = true; + } + + dev_err(chip->dev, "[%s] initial vout_on = %d \n", __func__, vout_on); +} + +static bool rx1619_check_firmware_version(struct rx1619_chg *chip, u8 area) +{ + static u16 addr; + u8 addr_h, addr_l; + int i = 0; + u8 read_buf[20]; + char *fw_data = NULL; + + dev_err(chip->dev, "[rx1619] [%s] enter \n", __func__); + + if (area == BOOT_AREA) { + addr = 0; + g_fw_data_lenth = sizeof(fw_data_boot); + fw_data = fw_data_boot; + } else if (area == RX_AREA) { + addr = 256; + g_fw_data_lenth = sizeof(fw_data_rx); + fw_data = fw_data_rx; + } else if (area == TX_AREA) { + addr = 4864; + g_fw_data_lenth = sizeof(fw_data_tx); + fw_data = fw_data_tx; + } + + /************prepare_for_mtp_read************/ + rx1619_write(chip, 0x69, 0x2017); + rx1619_write(chip, 0x96, 0x2017); + rx1619_write(chip, 0x66, 0x2017); + rx1619_write(chip, 0x99, 0x2017); + rx1619_write(chip, 0xff, 0x2018); + rx1619_write(chip, 0xff, 0x2019); + rx1619_write(chip, 0x5a, 0x0001); + rx1619_write(chip, 0xa5, 0x0003); + + rx1619_write(chip, 0x01, 0x0017); + /************prepare_for_mtp_read************/ + + msleep(10); + + /*************read 12 byte before fw_data_end addr************/ + addr += (g_fw_data_lenth / 4); + + for (i = 0; i < 12; i += 4) { + /************write_mtp_addr************/ + addr_h = (u8)(addr >> 8); + addr_l = (u8)(addr & 0xff); + rx1619_write(chip, addr_h, 0x0010); + rx1619_write(chip, addr_l, 0x0011); + /************write_mtp_addr************/ + + addr--; + + /************read pause************/ + rx1619_write(chip, 0x02, 0x0018); + rx1619_write(chip, 0x00, 0x0018); + /************read pause************/ + + /************read data************/ + rx1619_read(chip, &read_buf[i + 3], 0x0013); + rx1619_read(chip, &read_buf[i + 2], 0x0014); + rx1619_read(chip, &read_buf[i + 1], 0x0015); + rx1619_read(chip, &read_buf[i + 0], 0x0016); + /************read data************/ + } + /*************read 12 byte before fw_data_end addr************/ + + /***********end************/ + rx1619_write(chip, 0x00, 0x0017); + /***********end************/ + + /************exit dtm************/ + rx1619_write(chip, 0x00, 0x2018); + rx1619_write(chip, 0x00, 0x2019); + rx1619_write(chip, 0x00, 0x0001); + rx1619_write(chip, 0x00, 0x0003); + rx1619_write(chip, 0x55, 0x2017); + /************exit dtm************/ + + dev_info(chip->dev, "confirm data =0x%x, 0x%x, 0x%x, 0x%x\n", + read_buf[0], read_buf[1], read_buf[2], read_buf[3]); + + dev_info( + chip->dev, + "chip_data version=0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", + read_buf[4], read_buf[5], read_buf[6], read_buf[7], read_buf[8], + read_buf[9], read_buf[10], read_buf[11]); + + dev_info( + chip->dev, + "fw_data version=0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", + fw_data[g_fw_data_lenth - 4], fw_data[g_fw_data_lenth - 3], + fw_data[g_fw_data_lenth - 2], fw_data[g_fw_data_lenth - 1], + fw_data[g_fw_data_lenth - 8], fw_data[g_fw_data_lenth - 7], + fw_data[g_fw_data_lenth - 6], fw_data[g_fw_data_lenth - 5]); + + if (area == RX_AREA) { + if (read_buf[0] == 0x66) { + g_project_id_h = (~read_buf[5]); + g_project_id_l = (~read_buf[6]); + g_fw_rx_id = (~read_buf[7]); + g_hw_id_h = (~read_buf[10]); + g_hw_id_l = (~read_buf[11]); + } else { + g_project_id_h = 0x00; + g_project_id_l = 0x00; + g_fw_rx_id = FW_ERROR_CODE; + g_hw_id_h = 0x00; + g_hw_id_l = 0x00; + } + } else if (area == TX_AREA) { + if (read_buf[0] == 0x66) { + g_project_id_h = (~read_buf[5]); + g_project_id_l = (~read_buf[6]); + g_fw_tx_id = (~read_buf[7]); + } else { + g_project_id_h = 0x00; + g_project_id_l = 0x00; + g_fw_tx_id = FW_ERROR_CODE; + } + } else if (area == BOOT_AREA) { + if (read_buf[0] == 0x66) { + g_project_id_h = (~read_buf[5]); + g_project_id_l = (~read_buf[6]); + g_fw_boot_id = (~read_buf[7]); + } else { + g_project_id_h = 0x00; + g_project_id_l = 0x00; + g_fw_boot_id = FW_ERROR_CODE; + } + } + + if ((read_buf[7] == fw_data[g_fw_data_lenth - 1]) && + (read_buf[0] == + 0x66)) { //read_buf[7] is vesion, read_buf[0] is confirm value + dev_info(chip->dev, "g_fw_data_lenth=%d, fw version = 0x%x\n", + g_fw_data_lenth, (~read_buf[7]) & 0xff); + return true; + } + + return false; +} + +static bool rx1619_update_fw_confirm_data(struct rx1619_chg *chip, u8 area, + u8 confirm_data) +{ + u16 addr = 0; + u8 addr_h, addr_l; + u8 data[4] = { 0, 0, 0, 0 }; + + /************prepare_for_mtp_write************/ + rx1619_write(chip, 0x69, 0x2017); + rx1619_write(chip, 0x96, 0x2017); + rx1619_write(chip, 0x66, 0x2017); + rx1619_write(chip, 0x99, 0x2017); + rx1619_write(chip, 0xff, 0x2018); + rx1619_write(chip, 0xff, 0x2019); + rx1619_write(chip, 0x5a, 0x0001); + rx1619_write(chip, 0xa5, 0x0003); + + // rx1619_write(chip, 0x19, 0x0018); + rx1619_write(chip, 0x10, 0x1000); + rx1619_write(chip, 0x3e, 0x1130); + /************prepare_for_mtp_write************/ + + msleep(20); + + /************write_mtp_addr************/ + if (area == BOOT_AREA) { + addr = 0; + g_fw_data_lenth = sizeof(fw_data_boot); + } else if (area == RX_AREA) { + addr = 256; + g_fw_data_lenth = sizeof(fw_data_rx); + } else if (area == TX_AREA) { + addr = 4864; + g_fw_data_lenth = sizeof(fw_data_tx); + } + + addr += (g_fw_data_lenth / 4); + + addr_h = (u8)(addr >> 8); + addr_l = (u8)(addr & 0xff); + rx1619_write(chip, addr_h, 0x0010); + rx1619_write(chip, addr_l, 0x0011); + /************write_mtp_addr************/ + + /************enable write************/ + rx1619_write(chip, 0x01, 0x0017); + rx1619_write(chip, 0x30, 0x1000); + rx1619_write(chip, 0x5a, 0x001a); + /************enable write************/ + + /************write data************/ + usleep_range(2000, 2100); + rx1619_write(chip, 0x00, 0x0012); + usleep_range(2000, 2100); + rx1619_write(chip, 0x00, 0x0012); + usleep_range(2000, 2100); + rx1619_write(chip, 0x00, 0x0012); + usleep_range(2000, 2100); + rx1619_write(chip, confirm_data, 0x0012); + /************write data************/ + + /************end************/ + rx1619_write(chip, 0x00, 0x001a); + rx1619_write(chip, 0x00, 0x0017); + /************end************/ + + /************exit dtm************/ + rx1619_write(chip, 0x00, 0x2018); + rx1619_write(chip, 0x00, 0x2019); + rx1619_write(chip, 0x00, 0x0001); + rx1619_write(chip, 0x00, 0x0003); + rx1619_write(chip, 0x55, 0x2017); + /************exit dtm************/ + + msleep(100); // + + /************prepare_for_mtp_read************/ + rx1619_write(chip, 0x69, 0x2017); + rx1619_write(chip, 0x96, 0x2017); + rx1619_write(chip, 0x66, 0x2017); + rx1619_write(chip, 0x99, 0x2017); + rx1619_write(chip, 0xff, 0x2018); + rx1619_write(chip, 0xff, 0x2019); + rx1619_write(chip, 0x5a, 0x0001); + rx1619_write(chip, 0xa5, 0x0003); + + rx1619_write(chip, 0x01, 0x0017); + /************prepare_for_mtp_read************/ + + msleep(10); + + /************write_mtp_addr************/ + addr_h = (u8)(addr >> 8); + addr_l = (u8)(addr & 0xff); + rx1619_write(chip, addr_h, 0x0010); + rx1619_write(chip, addr_l, 0x0011); + /************write_mtp_addr************/ + + /************read pause************/ + rx1619_write(chip, 0x02, 0x0018); + rx1619_write(chip, 0x00, 0x0018); + /************read pause************/ + + /************read data************/ + rx1619_read(chip, &data[3], 0x0013); + rx1619_read(chip, &data[2], 0x0014); + rx1619_read(chip, &data[1], 0x0015); + rx1619_read(chip, &data[0], 0x0016); + /************read data************/ + + /***********end************/ + rx1619_write(chip, 0x00, 0x0017); + /***********end************/ + + /************exit dtm************/ + rx1619_write(chip, 0x00, 0x2018); + rx1619_write(chip, 0x00, 0x2019); + rx1619_write(chip, 0x00, 0x0001); + rx1619_write(chip, 0x00, 0x0003); + rx1619_write(chip, 0x55, 0x2017); + /************exit dtm************/ + + dev_err(chip->dev, "addr=%d confirm data = 0x%x, 0x%x, 0x%x, 0x%x\n", + addr, data[0], data[1], data[2], data[3]); + + if (data[0] == confirm_data) { + dev_err(chip->dev, "Update Confirm data Success!!!\n"); + return true; + } else { + dev_err(chip->dev, "Update Confirm data Failed!!! \n"); + return false; + } +} + +static bool rx1619_download_firmware(struct rx1619_chg *chip, u8 area) +{ + u16 addr = 0; + u8 addr_h, addr_l; + int i = 0; + u8 j = 0; + char *fw_data = NULL; + u32 count = 0; + + dev_err(chip->dev, "[rx1619] [%s] enter \n", __func__); + + /************prepare_for_mtp_write************/ + rx1619_write(chip, 0x69, 0x2017); + rx1619_write(chip, 0x96, 0x2017); + rx1619_write(chip, 0x66, 0x2017); + rx1619_write(chip, 0x99, 0x2017); + rx1619_write(chip, 0xff, 0x2018); + rx1619_write(chip, 0xff, 0x2019); + rx1619_write(chip, 0x5a, 0x0001); + rx1619_write(chip, 0xa5, 0x0003); + + // rx1619_write(chip, 0x19, 0x0018); + rx1619_write(chip, 0x10, 0x1000); + rx1619_write(chip, 0x3e, 0x1130); + /************prepare_for_mtp_write************/ + + msleep(20); + + /************write_mtp_addr************/ + if (area == BOOT_AREA) { + addr = 0; + g_fw_data_lenth = sizeof(fw_data_boot); + fw_data = fw_data_boot; + } else if (area == RX_AREA) { + addr = 256; + g_fw_data_lenth = sizeof(fw_data_rx); + fw_data = fw_data_rx; + } else if (area == TX_AREA) { + addr = 4864; + g_fw_data_lenth = sizeof(fw_data_tx); + fw_data = fw_data_tx; + } + addr_h = (u8)(addr >> 8); + addr_l = (u8)(addr & 0xff); + rx1619_write(chip, addr_h, 0x0010); + rx1619_write(chip, addr_l, 0x0011); + /************write_mtp_addr************/ + + /************enable write************/ + rx1619_write(chip, 0x01, 0x0017); + rx1619_write(chip, 0x30, 0x1000); + rx1619_write(chip, 0x5a, 0x001a); + /************enable write************/ + + /************write data************/ + for (i = 0; i < g_fw_data_lenth; i += 4) { + rx1619_write(chip, fw_data[i + 3], 0x0012); + for (j = 0; j < 4; j++) { + if (gpio_get_value(chip->power_good_gpio) == 1) { + usleep_range(300, 350); + if (gpio_get_value(chip->power_good_gpio) == + 0) { + break; + } + } else if (gpio_get_value(chip->power_good_gpio) == 0) { + usleep_range(900, 950); + count++; + break; + } + } + + rx1619_write(chip, fw_data[i + 2], 0x0012); + for (j = 0; j < 4; j++) { + if (gpio_get_value(chip->power_good_gpio) == 1) { + usleep_range(300, 350); + if (gpio_get_value(chip->power_good_gpio) == + 0) { + break; + } + } else if (gpio_get_value(chip->power_good_gpio) == 0) { + usleep_range(900, 950); + count++; + break; + } + } + + rx1619_write(chip, fw_data[i + 1], 0x0012); + for (j = 0; j < 4; j++) { + if (gpio_get_value(chip->power_good_gpio) == 1) { + usleep_range(300, 350); + if (gpio_get_value(chip->power_good_gpio) == + 0) { + break; + } + } else if (gpio_get_value(chip->power_good_gpio) == 0) { + usleep_range(900, 950); + count++; + break; + } + } + + rx1619_write(chip, fw_data[i + 0], 0x0012); + for (j = 0; j < 4; j++) { + if (gpio_get_value(chip->power_good_gpio) == 1) { + usleep_range(300, 350); + if (gpio_get_value(chip->power_good_gpio) == + 0) { + break; + } + } else if (gpio_get_value(chip->power_good_gpio) == 0) { + usleep_range(900, 950); + count++; + break; + } + } + } + /************write data************/ + + /************end************/ + rx1619_write(chip, 0x00, 0x001a); + rx1619_write(chip, 0x00, 0x0017); + /************end************/ + + /************exit dtm************/ + rx1619_write(chip, 0x00, 0x2018); + rx1619_write(chip, 0x00, 0x2019); + rx1619_write(chip, 0x00, 0x0001); + rx1619_write(chip, 0x00, 0x0003); + rx1619_write(chip, 0x55, 0x2017); + /************exit dtm************/ + + dev_err(chip->dev, + "[rx1619] [%s] area=%d,addr=%d, g_fw_data_lenth=%d, count=%d\n", + __func__, area, addr, g_fw_data_lenth, count); + dev_err(chip->dev, "[rx1619] [%s] exit \n", __func__); + + return 0; +} + +static int rx1619_check_firmware(struct rx1619_chg *chip, u8 area) +{ + u32 success_count = 0; + u16 addr = 0; + u8 addr_h, addr_l; + int i = 0; + int j = 0; + u8 read_buf[4] = { 0, 0, 0, 0 }; + char *fw_data = NULL; + + success_count = 0; + + dev_info(chip->dev, "[rx1619] [%s] enter \n", __func__); + + if (area == BOOT_AREA) { + addr = 0; + g_fw_data_lenth = sizeof(fw_data_boot); + fw_data = fw_data_boot; + } else if (area == RX_AREA) { + addr = 256; + g_fw_data_lenth = sizeof(fw_data_rx); + fw_data = fw_data_rx; + } else if (area == TX_AREA) { + addr = 4864; + g_fw_data_lenth = sizeof(fw_data_tx); + fw_data = fw_data_tx; + } + + /************prepare_for_mtp_read************/ + rx1619_write(chip, 0x69, 0x2017); + rx1619_write(chip, 0x96, 0x2017); + rx1619_write(chip, 0x66, 0x2017); + rx1619_write(chip, 0x99, 0x2017); + rx1619_write(chip, 0xff, 0x2018); + rx1619_write(chip, 0xff, 0x2019); + rx1619_write(chip, 0x5a, 0x0001); + rx1619_write(chip, 0xa5, 0x0003); + + rx1619_write(chip, 0x01, 0x0017); + /************prepare_for_mtp_read************/ + + msleep(10); + + for (i = 0; i < g_fw_data_lenth; i += 4) { + /************write_mtp_addr************/ + addr_h = (u8)(addr >> 8); + addr_l = (u8)(addr & 0xff); + rx1619_write(chip, addr_h, 0x0010); + rx1619_write(chip, addr_l, 0x0011); + /************write_mtp_addr************/ + + addr++; + + /************read pause************/ + rx1619_write(chip, 0x02, 0x0018); + rx1619_write(chip, 0x00, 0x0018); + /************read pause************/ + + /************read data************/ + rx1619_read(chip, &read_buf[3], 0x0013); + rx1619_read(chip, &read_buf[2], 0x0014); + rx1619_read(chip, &read_buf[1], 0x0015); + rx1619_read(chip, &read_buf[0], 0x0016); + /************read data************/ + + if ((read_buf[0] == fw_data[i + 0]) && + (read_buf[1] == fw_data[i + 1]) && + (read_buf[2] == fw_data[i + 2]) && + (read_buf[3] == fw_data[i + 3])) { + success_count++; + } else { + j++; + if (j >= 50) { //if error adrr >= 50,new IC + goto CCC; + } + } + } + +CCC: + /***********end************/ + rx1619_write(chip, 0x00, 0x0017); + /***********end************/ + + /************exit dtm************/ + rx1619_write(chip, 0x00, 0x2018); + rx1619_write(chip, 0x00, 0x2019); + rx1619_write(chip, 0x00, 0x0001); + rx1619_write(chip, 0x00, 0x0003); + rx1619_write(chip, 0x55, 0x2017); + /************exit dtm************/ + + dev_err(chip->dev, "error_conut= %d, success_count=%d\n", j, + success_count); + + dev_info( + chip->dev, + "(sizeof(fw_data_boot)) = %ld (sizeof(fw_data_rx)) = %ld (sizeof(fw_data_tx)) = %ld \n", + (sizeof(fw_data_boot)), (sizeof(fw_data_rx)), + (sizeof(fw_data_tx))); + + return success_count; +} + +static bool rx1619_push_rx_firmware(struct rx1619_chg *chip) +{ + u16 addr = 256; + u8 addr_h, addr_l; + int i = 0; + int j = 0; + u8 read_buf[4] = { 0, 0, 0, 0 }; + char *fw_data = NULL; + int pass_count = 0; + + if (chip->rx_fw_bin == NULL) { + dev_err(chip->dev, "[rx1619] g_chip->rx_fw_bin == NULL \n"); + return false; + } + + dev_err(chip->dev, "[rx1619] g_chip->rx_fw_bin != NULL \n"); + dev_err(chip->dev, "[rx1619] [%s] download rx enter \n", __func__); + + addr = 256; + g_fw_data_lenth = chip->rx_fw_len; + fw_data = chip->rx_fw_bin; + + /************prepare_for_mtp_write************/ + rx1619_write(chip, 0x69, 0x2017); + rx1619_write(chip, 0x96, 0x2017); + rx1619_write(chip, 0x66, 0x2017); + rx1619_write(chip, 0x99, 0x2017); + rx1619_write(chip, 0xff, 0x2018); + rx1619_write(chip, 0xff, 0x2019); + rx1619_write(chip, 0x5a, 0x0001); + rx1619_write(chip, 0xa5, 0x0003); + + //rx1619_write(chip, 0x19, 0x0018); + rx1619_write(chip, 0x10, 0x1000); + rx1619_write(chip, 0x3e, 0x1130); + /************prepare_for_mtp_write************/ + + msleep(20); + + /************write_mtp_addr************/ + addr_h = (u8)(addr >> 8); + addr_l = (u8)(addr & 0xff); + rx1619_write(chip, addr_h, 0x0010); + rx1619_write(chip, addr_l, 0x0011); + /************write_mtp_addr************/ + + /************enable write************/ + rx1619_write(chip, 0x01, 0x0017); + rx1619_write(chip, 0x30, 0x1000); + rx1619_write(chip, 0x5a, 0x001a); + /************enable write************/ + + /************write data************/ + for (i = 0; i < g_fw_data_lenth; i += 4) { + rx1619_write(chip, 0xff & (~fw_data[i + 3]), 0x0012); + usleep_range(1000, 1100); + rx1619_write(chip, 0xff & (~fw_data[i + 2]), 0x0012); + usleep_range(1000, 1100); + rx1619_write(chip, 0xff & (~fw_data[i + 1]), 0x0012); + usleep_range(1000, 1100); + rx1619_write(chip, 0xff & (~fw_data[i + 0]), 0x0012); + usleep_range(1000, 1100); + } + /************write data************/ + + /************end************/ + rx1619_write(chip, 0x00, 0x001a); + rx1619_write(chip, 0x00, 0x0017); + /************end************/ + + /************exit dtm************/ + rx1619_write(chip, 0x00, 0x2018); + rx1619_write(chip, 0x00, 0x2019); + rx1619_write(chip, 0x00, 0x0001); + rx1619_write(chip, 0x00, 0x0003); + rx1619_write(chip, 0x55, 0x2017); + /************exit dtm************/ + + dev_err(chip->dev, "[rx1619] [%s] download rx exit \n", __func__); + + msleep(500); + + dev_info(chip->dev, "[rx1619] [%s] check rx enter \n", __func__); + pass_count = 0; + + /************prepare_for_mtp_read************/ + rx1619_write(chip, 0x69, 0x2017); + rx1619_write(chip, 0x96, 0x2017); + rx1619_write(chip, 0x66, 0x2017); + rx1619_write(chip, 0x99, 0x2017); + rx1619_write(chip, 0xff, 0x2018); + rx1619_write(chip, 0xff, 0x2019); + rx1619_write(chip, 0x5a, 0x0001); + rx1619_write(chip, 0xa5, 0x0003); + + rx1619_write(chip, 0x01, 0x0017); + /************prepare_for_mtp_read************/ + + msleep(10); + + for (i = 0; i < g_fw_data_lenth; i += 4) { + /************write_mtp_addr************/ + addr_h = (u8)(addr >> 8); + addr_l = (u8)(addr & 0xff); + rx1619_write(chip, addr_h, 0x0010); + rx1619_write(chip, addr_l, 0x0011); + /************write_mtp_addr************/ + + addr++; + + /************read pause************/ + rx1619_write(chip, 0x02, 0x0018); + rx1619_write(chip, 0x00, 0x0018); + /************read pause************/ + + /************read data************/ + rx1619_read(chip, &read_buf[3], 0x0013); + rx1619_read(chip, &read_buf[2], 0x0014); + rx1619_read(chip, &read_buf[1], 0x0015); + rx1619_read(chip, &read_buf[0], 0x0016); + /************read data************/ + + if ((read_buf[0] == (0xff & (~fw_data[i + 0]))) && + (read_buf[1] == (0xff & (~fw_data[i + 1]))) && + (read_buf[2] == (0xff & (~fw_data[i + 2]))) && + (read_buf[3] == (0xff & (~fw_data[i + 3])))) { + pass_count++; + } else { + j++; + if (j >= 50) { + goto CCC; + } + } + } + +CCC: + /***********end************/ + rx1619_write(chip, 0x00, 0x0017); + /***********end************/ + + /************exit dtm************/ + rx1619_write(chip, 0x00, 0x2018); + rx1619_write(chip, 0x00, 0x2019); + rx1619_write(chip, 0x00, 0x0001); + rx1619_write(chip, 0x00, 0x0003); + rx1619_write(chip, 0x55, 0x2017); + /************exit dtm************/ + + dev_err(chip->dev, + "error_conut= %d, pass_count=%d, (sizeof(fw_data_rx)) = %ld \n", + j, pass_count, (sizeof(fw_data_rx))); + + dev_info(chip->dev, "fw_data version=0x%x, 0x%x, 0x%x, 0x%x \n", + 0xff & (~fw_data[g_fw_data_lenth - 4]), + 0xff & (~fw_data[g_fw_data_lenth - 3]), + 0xff & (~fw_data[g_fw_data_lenth - 2]), + 0xff & (~fw_data[g_fw_data_lenth - 1])); + + rx_fw_version = fw_data[g_fw_data_lenth - 1]; + rx_bin_project_id_h = fw_data[g_fw_data_lenth - 3]; + rx_bin_project_id_l = fw_data[g_fw_data_lenth - 2]; + + dev_info(chip->dev, "[rx1619] [%s] check rx exit \n", __func__); + + if (g_fw_data_lenth == (pass_count * 4)) { + dev_info(chip->dev, "[rx1619] [%s] Push rx success! \n", + __func__); + return true; + } else { + dev_info(chip->dev, "[rx1619] [%s] Push rx fail! \n", __func__); + return false; + } +} + +bool rx1619_check_i2c_is_ok(struct rx1619_chg *chip) +{ + u8 read_data = 0; + + rx1619_write(chip, 0x88, 0x0000); + msleep(10); + rx1619_read(chip, &read_data, 0x0000); + + if (read_data == 0x88) { + return true; + } else { + return false; + } +} + +#define RETRY_COUNT 2 +bool rx1619_download_area_firmware(struct rx1619_chg *chip, u8 area) +{ + bool status = false; + u8 count = 0; + u32 ret = 0; + + dev_err(chip->dev, "[rx1619] [%s] enter , area=%d \n", __func__, area); + + if (rx1619_check_firmware_version(chip, area) == true) { + dev_err(chip->dev, + "[rx1619] [%s] Same fw Version, no upgrade required! \n", + __func__); + return true; + } + msleep(20); + +RETRY: + count++; + dev_err(chip->dev, "count=%d \n", count); + status = rx1619_update_fw_confirm_data(chip, area, 0x00); //clear 0 + if (!status) { + return false; + } + rx1619_download_firmware(chip, area); + msleep(20); + ret = rx1619_check_firmware(chip, area); + dev_err(chip->dev, + "download_area:%d success_cout=%d, g_fw_data_lenth=%d\n", area, + ret, g_fw_data_lenth); + if (g_fw_data_lenth == (ret * 4)) { + status = rx1619_update_fw_confirm_data( + chip, area, 0x66); //0x66(check success) + if (!status) { + dev_err(chip->dev, + "area:%d update firmware confirm data fail! \n", + area); + return false; + } else { + dev_info(chip->dev, "download area:%d fw success! \n", + area); + } + } else { + if (count > RETRY_COUNT) { + dev_info(chip->dev, "download area:%d fw failed! \n", + area); + return false; + } else { + goto RETRY; + } + } + + return true; +} + +bool rx1619_onekey_download_firmware(struct rx1619_chg *chip) +{ + bool ret = false; + + dev_err(chip->dev, "[rx1619] [%s] enter \n", __func__); + + if (!rx1619_check_i2c_is_ok(chip)) { + dev_err(chip->dev, " i2c error! \n"); + return false; + } + + ret = rx1619_download_area_firmware(chip, BOOT_AREA); + if (!ret) { + dev_err(chip->dev, "BOOT_AREA download fail!!! \n"); + return false; + } + + msleep(20); + + ret = rx1619_download_area_firmware(chip, RX_AREA); + if (!ret) { + dev_err(chip->dev, "RX_AREA download fail!!! \n"); + return false; + } + + msleep(20); + + ret = rx1619_download_area_firmware(chip, TX_AREA); + if (!ret) { + dev_err(chip->dev, "TX_AREA download fail!!! \n"); + return false; + } + + msleep(20); + + return true; +} + +void rx1619_dump_reg(void) +{ + u8 data[32] = { 0 }; + + rx1619_read(g_chip, &data[0], 0x0000); + rx1619_read(g_chip, &data[1], 0x0001); + rx1619_read(g_chip, &data[2], 0x0002); + rx1619_read(g_chip, &data[3], 0x0003); + rx1619_read(g_chip, &data[4], 0x0004); + rx1619_read(g_chip, &data[5], 0x0005); + rx1619_read(g_chip, &data[6], 0x0008); + rx1619_read(g_chip, &data[7], 0x0009); + rx1619_read(g_chip, &data[8], 0x000A); + rx1619_read(g_chip, &data[9], 0x000B); + rx1619_read(g_chip, &data[10], 0x000C); + rx1619_read(g_chip, &data[11], 0x0020); + rx1619_read(g_chip, &data[12], 0x0021); + rx1619_read(g_chip, &data[13], 0x0022); + rx1619_read(g_chip, &data[14], 0x0023); + rx1619_read(g_chip, &data[15], 0x0024); + + dev_info(g_chip->dev, "reave--[rx1619] [%s] REG:0x0000=0x%x\n", + __func__, data[0]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0001=0x%x\n", __func__, + data[1]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0002=0x%x\n", __func__, + data[2]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0003=0x%x\n", __func__, + data[3]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0004=0x%x\n", __func__, + data[4]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0005=0x%x\n", __func__, + data[5]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0008=0x%x\n", __func__, + data[6]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0009=0x%x\n", __func__, + data[7]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x000A=0x%x\n", __func__, + data[8]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x000B=0x%x\n", __func__, + data[9]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x000C=0x%x\n", __func__, + data[10]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0020=0x%x\n", __func__, + data[11]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0021=0x%x\n", __func__, + data[12]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0022=0x%x\n", __func__, + data[13]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0023=0x%x\n", __func__, + data[14]); + dev_info(g_chip->dev, "[rx1619] [%s] REG:0x0024=0x%x\n", __func__, + data[15]); + rx1619_write(g_chip, AP_REV_DATA_OK, REG_AP_RX_COMM); +} + +void rx1619_set_pmi_icl(struct rx1619_chg *chip, int mA) +{ + union power_supply_propval val = { + 0, + }; + + val.intval = mA; + + if (chip->wireless_by_usbin) { + if (!chip->usb_psy) + chip->usb_psy = power_supply_get_by_name("usb"); + + if (chip->usb_psy) + power_supply_set_property(chip->usb_psy, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + + } else { + if (!chip->dc_psy) + chip->dc_psy = power_supply_get_by_name("dc"); + + if (chip->dc_psy) + power_supply_set_property(chip->dc_psy, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + } + + dev_info(chip->dev, "[rx1619] [%s] [rx1619] set icl: %d\n", __func__, + val.intval); +} + +void rx1619_get_pmi_icl(struct rx1619_chg *chip) +{ + union power_supply_propval val = { + 0, + }; + + if (chip->wireless_by_usbin) { + if (!chip->usb_psy) + chip->usb_psy = power_supply_get_by_name("usb"); + + if (chip->usb_psy) + power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + } else { + if (!chip->dc_psy) + chip->dc_psy = power_supply_get_by_name("dc"); + + if (chip->dc_psy) + power_supply_get_property(chip->dc_psy, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + } + + dev_info(chip->dev, "[rx1619] [%s] [rx1619] get icl: %d\n", __func__, + val.intval); + g_current_now = val.intval; +} + +void set_usb_type_current(struct rx1619_chg *chip, u8 data) +{ + int i = 0; + int uA = 0; + //int vol_now = 0; + union power_supply_propval val = { + 0, + }; + + dev_info(chip->dev, "[%s] data=0x%x \n", __func__, data); + + switch (data) { + case 0: //other charger + if ((chip->auth == 0) && (chip->epp == 0)) { //bpp and auth fail + rx1619_set_pmi_icl(chip, DC_OTHER_CURRENT); + dev_info(chip->dev, + "[rx1619] [%s] bpp and no id---800mA \n", + __func__); + } else { //auth ok + rx1619_set_pmi_icl(chip, DC_LOW_CURRENT); + dev_info(chip->dev, + "[rx1619] [%s] bpp and id ok---200mA \n", + __func__); + } + break; + + case 1: + rx1619_set_pmi_icl(chip, DC_SDP_CURRENT); + chip->target_vol = ADAPTER_DEFAULT_VOL; + chip->target_curr = DC_SDP_CURRENT; + break; + + case 2: + case 3: + rx1619_set_pmi_icl(chip, DC_BPP_AUTH_FAIL_CURRENT); + chip->target_vol = ADAPTER_DEFAULT_VOL; + chip->target_curr = DC_BPP_AUTH_FAIL_CURRENT; + break; + + case 5: //QC2-other -- 6.5W + for (i = 0; i <= 8; i++) { + uA = (DC_LOW_CURRENT + 100000 * i); + rx1619_set_pmi_icl(chip, uA); + msleep(100); + } + chip->target_vol = ADAPTER_BPP_QC2_VOL; + chip->target_curr = uA; + break; + + case 6: //QC3-other -- 10W + case 7: //PD-other -- 10W + if (chip->epp) { + for (i = 0; i <= 8; i++) { + uA = (DC_LOW_CURRENT + 200000 * i); + rx1619_set_pmi_icl(chip, uA); + msleep(100); + } + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = uA; + } else { + for (i = 0; i <= 9; i++) { + uA = (DC_LOW_CURRENT + 100000 * i); + rx1619_set_pmi_icl(chip, uA); + msleep(100); + } + chip->target_vol = ADAPTER_BPP_LIMIT_VOL; + chip->target_curr = uA; + } + chip->last_qc3_icl = chip->target_curr; + break; + + case 8: //fail charger + break; + + case 9: //QC3-27W(20W) + case 10: //PD-27W(20W) + case 11: //PD-27W(20W) + if (chip->op_mode != LN8282_OPMODE_SWITCHING) { + dev_info(chip->dev, + "[20W]not switch mode, don't rise voltage \n"); + break; + } + /* + chip->batt_psy = power_supply_get_by_name("battery"); + if (!chip->batt_psy) { + dev_err(chip->dev, "Battery supply not found\n"); + vol_now = 15000; + } else { + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, &val); + vol_now = val.intval; + vol_now = (vol_now*4) / 1000 + 200; //delta + } +*/ + chip->target_vol = ADAPTER_EPP_MI_VOL; + rx1619_set_pmi_icl(chip, 1000000); + msleep(100); + if (chip->epp && chip->auth && chip->wireless_psy) { + val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + msleep(200); + } + /* for usb-in design, set max usb icl to 1.8A*/ + for (i = 0; i <= 10; i++) { + uA = (USB_20W_PLUS_BASE_CURRENT_UA + 100000 * i); + rx1619_set_pmi_icl(chip, uA); + msleep(100); + } + chip->target_curr = uA; + chip->last_icl = chip->target_curr; + dev_info(chip->dev, "[%s] 27W adapter \n", __func__); + break; + + case 12: //40w + case 13: + case 14: + if (chip->op_mode != LN8282_OPMODE_SWITCHING) { + dev_info(chip->dev, + "[30W]not switch mode, don't rise voltage \n"); + break; + } + /* + chip->batt_psy = power_supply_get_by_name("battery"); + if (!chip->batt_psy) { + dev_err(chip->dev, "Battery supply not found\n"); + vol_now = 15000; + } else { + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, &val); + vol_now = val.intval; + vol_now = (vol_now*4) / 1000 + 200; //delta + } +*/ + chip->target_vol = ADAPTER_EPP_MI_VOL; + rx1619_set_pmi_icl(chip, 1000000); + msleep(100); + if (chip->epp && chip->auth && chip->wireless_psy) { + val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + msleep(200); + } + /* for usb-in design, set max usb icl to 1.8A*/ + for (i = 0; i <= 4; i++) { + uA = (USB_20W_PLUS_BASE_CURRENT_UA + 200000 * i); + rx1619_set_pmi_icl(chip, uA); + msleep(100); + } + chip->target_curr = uA; + chip->last_icl = chip->target_curr; + dev_info(chip->dev, "[%s] 40W adapter \n", __func__); + break; + + default: + dev_info(chip->dev, "[%s] other Usb_type\n", __func__); + break; + } +} + +static void rx_charging_info(struct rx1619_chg *chip) +{ + int vout, iout, vrect; + if (!chip) + return; + + vout = rx1619_get_rx_vout(chip); + iout = rx1619_get_rx_iout(chip); + vrect = rx1619_get_rx_vrect(chip); + + dev_info(chip->dev, "%s:Vout:%dmV, Iout:%dmA, Vrect:%dmV\n", __func__, + vout, iout, vrect); +} + +void get_usb_type_current(struct rx1619_chg *chip, u8 data) +{ + dev_info(chip->dev, "[%s] data=0x%x \n", __func__, data); + + switch (data) { + case ADAPTER_NONE: //other charger + if ((chip->auth == 0) && (chip->epp == 0)) { //bpp and auth fail + chip->target_curr = DC_OTHER_CURRENT; + dev_info(chip->dev, + "[rx1619] [%s] bpp and no id---800mA \n", + __func__); + } else { //auth ok + chip->target_curr = DC_LOW_CURRENT; + dev_info(chip->dev, + "[rx1619] [%s] bpp and id ok---200mA \n", + __func__); + } + break; + + case ADAPTER_SDP: + chip->target_vol = ADAPTER_DEFAULT_VOL; + chip->target_curr = DC_SDP_CURRENT; + break; + + case ADAPTER_CDP: + case ADAPTER_DCP: + chip->target_vol = ADAPTER_DEFAULT_VOL; + chip->target_curr = DC_BPP_AUTH_FAIL_CURRENT; + break; + + case ADAPTER_QC2: //QC2-other -- 6.5W + chip->target_vol = ADAPTER_BPP_QC2_VOL; + chip->target_curr = DC_QC2_CURRENT; //1A + break; + + case ADAPTER_QC3: //QC3-other -- 10W + case ADAPTER_PD: //PD-other -- 10W + if (chip->epp) { + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = DC_QC3_CURRENT; //1.8A + } else { + chip->target_vol = ADAPTER_DEFAULT_VOL; + chip->target_curr = DC_QC3_BPP_CURRENT; //0.9A + } + break; + + case ADAPTER_AUTH_FAILED: //fail charger + break; + + case ADAPTER_XIAOMI_QC3: //QC3-27W(20W) + case ADAPTER_XIAOMI_PD: //PD-27W(20W) + case ADAPTER_ZIMI_CAR_POWER: //PD-27W(20W) + chip->target_vol = ADAPTER_EPP_MI_VOL; + /* for usb-in design, set max usb icl to 1.8A*/ + chip->target_curr = USB_20W_PLUS_CURRENT_UA; //1.8A + break; + + case ADAPTER_XIAOMI_PD_40W: //40w + case ADAPTER_XIAOMI_PD_50W: + case ADAPTER_XIAOMI_PD_60W: + case ADAPTER_VOICE_BOX: + chip->target_vol = ADAPTER_EPP_MI_VOL; + /* for usb-in design, set max usb icl to 1.8A*/ + chip->target_curr = USB_20W_PLUS_CURRENT_UA; //1.8A + break; + + default: + break; + } +} +static void rx_set_charging_param(struct rx1619_chg *chip) +{ + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + int soc = 0, health = 0, batt_sts = 0; + int vol_now = 0, cur_now = 0, dc_level = 0; + int iout = 0, ret = 0; + bool vout_change = false; + int last_icl = 0; + int last_vin = 0; + + get_usb_type_current(chip, g_USB_TYPE); + + if (!chip->batt_psy) { + ret = rx_get_property_names(chip); + if (ret < 0) + return; + } + + power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_STATUS, + &val); + batt_sts = val.intval; + + power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_CAPACITY, + &val); + soc = val.intval; + + power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, + &val); + vol_now = val.intval; + + power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_CURRENT_NOW, + &val); + cur_now = val.intval; + + power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_HEALTH, + &val); + health = val.intval; + + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, &val); + dc_level = val.intval; + + dev_info( + chip->dev, + "soc:%d,vol_now:%d,cur_now:%d,health:%d, bat_status:%d, dc_level:%d\n", + soc, vol_now, cur_now, health, batt_sts, dc_level); + /*epp 10W*/ + if ((g_USB_TYPE >= 6 && g_USB_TYPE <= 7) && (chip->epp)) { + dev_info(chip->dev, "standard epp logic\n"); + if (soc >= 97) + chip->target_curr = DC_BPP_CURRENT; + if (soc == 100) + chip->target_curr = DC_SDP_CURRENT; + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + + if (chip->target_curr != chip->last_qc3_icl) { + dev_info(chip->dev, + "qc3_epp, set new icl: %d, last_icl: %d\n", + chip->target_curr, chip->last_qc3_icl); + chip->last_qc3_icl = chip->target_curr; + rx1619_set_pmi_icl(chip, chip->target_curr); + msleep(100); + } + } + /*epp plus*/ + if (g_USB_TYPE >= 9) { + if (chip->op_mode != LN8282_OPMODE_SWITCHING) { + dev_info(chip->dev, + "not switch mode, don't adjust voltage \n"); + goto out; + } + + if (chip->is_pan_tx) { + schedule_delayed_work(&chip->pan_tx_work, + msecs_to_jiffies(0)); + goto out; + } + + if (chip->is_voice_box_tx) { + dev_info(chip->dev, "enter voice work\n"); + schedule_delayed_work(&chip->voice_tx_work, + msecs_to_jiffies(0)); + goto out; + } + + if ((dc_level >= HIGH_THERMAL_LEVEL_THR) || + (soc >= LIMIT_SOC)) { + dev_info(chip->dev, + "set vin 12V for dc_level:%d, soc:%d\n", + dc_level, soc); + //chip->target_vol = EPP_VOL_THRESHOLD; + chip->is_vin_limit = 1; + } else + chip->is_vin_limit = 0; + + iout = rx1619_get_rx_iout(chip); + /* function start + * set adapter vol by iout value, threshold is 500mA + * lower than threshold will reduce to 12V, more than + * threshold will lift to 15V: + * 15V-->12V check 3 times + * 12V-->15v check 3 times + */ + if (iout < LIMIT_EPP_IOUT && + chip->epp_exchange == EXCHANGE_15V) { + chip->count_10v++; + chip->count_15v = 0; + } else if (iout > LIMIT_EPP_IOUT && + chip->epp_exchange == EXCHANGE_10V) { + chip->count_15v++; + chip->count_10v = 0; + } else { + chip->count_10v = 0; + chip->count_15v = 0; + } + if (chip->count_10v > ICL_EXCHANGE_COUNT || + (chip->epp_exchange == EXCHANGE_10V && + chip->count_15v <= ICL_EXCHANGE_COUNT)) { + dev_info(chip->dev, + "iout less than 500mA ,set vin to 12V\n"); + //chip->target_vol = EPP_VOL_THRESHOLD; + chip->epp_exchange = EXCHANGE_10V; + } else if (chip->count_15v > (ICL_EXCHANGE_COUNT)) + chip->epp_exchange = EXCHANGE_15V; + /* function end */ + switch (chip->status) { + case NORMAL_MODE: + if (soc >= 97) { + //chip->target_curr = min(DC_BPP_CURRENT, chip->target_curr); + dev_info(chip->dev, "set curr to %d\n", + chip->target_curr); + } + if (soc >= FULL_SOC) { + chip->status = TAPER_MODE; + //chip->target_vol = EPP_VOL_THRESHOLD; + //chip->target_curr = min(DC_SDP_CURRENT, chip->target_curr); + dev_info( + chip->dev, + "ready to taper_mode ,set vin to %d, curr to %d\n", + chip->target_vol, chip->target_curr); + } + break; + case TAPER_MODE: + //chip->target_vol = EPP_VOL_THRESHOLD; + //chip->target_curr = min(DC_SDP_CURRENT, chip->target_curr); + + dev_info( + chip->dev, + "ready to full_mode ,set vin to %d, curr to %d\n", + chip->target_vol, chip->target_curr); + if (soc == FULL_SOC && + batt_sts == POWER_SUPPLY_STATUS_FULL) + chip->status = FULL_MODE; + else if (soc < FULL_SOC - 1) + chip->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(chip->dev, "charge full set Vin 11V\n"); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + dev_info(chip->dev, + "full mode -> recharge mode\n"); + chip->status = RECHG_MODE; + chip->target_curr = DC_FULL_CURRENT; + } + break; + case RECHG_MODE: + if (batt_sts == POWER_SUPPLY_STATUS_FULL) { + dev_info(chip->dev, + "recharge mode -> full mode\n"); + chip->status = FULL_MODE; + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + chip->target_vol = ADAPTER_EPP_QC3_VOL; + if (chip->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + } + dev_info(chip->dev, "recharge mode set icl to 350mA\n"); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = DC_FULL_CURRENT; + + if (chip->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + default: + break; + } + switch (health) { + case POWER_SUPPLY_HEALTH_GOOD: + break; + case POWER_SUPPLY_HEALTH_COOL: + break; + case POWER_SUPPLY_HEALTH_WARM: + //chip->target_vol = min(EPP_VOL_THRESHOLD, chip->target_vol); + chip->target_curr = + min(DC_SDP_CURRENT, chip->target_curr); + break; + case POWER_SUPPLY_HEALTH_OVERVOLTAGE: + //chip->target_vol = min(EPP_VOL_THRESHOLD, chip->target_vol); + chip->target_curr = + min(SCREEN_OFF_FUL_CURRENT, chip->target_curr); + break; + case POWER_SUPPLY_HEALTH_COLD: + case POWER_SUPPLY_HEALTH_HOT: + //chip->target_vol = min(EPP_VOL_THRESHOLD, chip->target_vol); + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + break; + default: + break; + } + last_vin = chip->last_vin; + last_icl = chip->last_icl; + if (chip->target_vol > 0 && + chip->target_vol != chip->last_vin) { + ret = rx1619_set_vout(chip, chip->target_vol); + chip->last_vin = chip->target_vol; + vout_change = true; + + if (chip->target_vol <= EPP_VOL_THRESHOLD) { + val.intval = 0; + } else { + val.intval = 1; + } + if (chip->wireless_psy) { + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + } + if ((chip->target_curr > 0 && + chip->target_curr != chip->last_icl) || + vout_change) { + chip->last_icl = chip->target_curr; + rx1619_set_pmi_icl(chip, chip->target_curr); + } + } +out: + dev_info( + chip->dev, + "status:0x%x,adapter_vol=%d,icl_curr=%d,last_vin=%d,last_icl=%d\n", + chip->status, chip->target_vol, chip->target_curr, last_vin, + last_icl); +} + +static void rx1619_dc_check_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, dc_check_work.work); + + dev_info(chip->dev, "[rx1619] dc present: %d\n", chip->dcin_present); + if (chip->dcin_present) { + chip->ss = 1; + dev_info(chip->dev, "dcin present, quit dc check work\n"); + return; + } else { + chip->ss = 0; + dev_info(chip->dev, + "dcin no present, continue dc check work\n"); + schedule_delayed_work(&chip->dc_check_work, + msecs_to_jiffies(2500)); + } + if (chip->wireless_psy) + power_supply_changed(chip->wireless_psy); +} + +static void rx1619_cmd_timeout_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, cmd_timeout_work.work); + + dev_info(chip->dev, "[%s] Cmd timeout set 700mA \n", __func__); + rx1619_set_pmi_icl(chip, DC_BPP_AUTH_FAIL_CURRENT); + chip->target_curr = DC_BPP_AUTH_FAIL_CURRENT; +} + +static void rx1619_rx_first_boot(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, rx_first_boot.work); + g_rx1619_first_flag = true; + if (chip->wip_psy) + power_supply_changed(chip->wip_psy); +} +#define CHARGING_PERIOD_S 10 +static void rx_monitor_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, chg_monitor_work.work); + rx_charging_info(chip); + + rx_set_charging_param(chip); + + schedule_delayed_work(&chip->chg_monitor_work, CHARGING_PERIOD_S * HZ); +} + +static void rx1619_fw_download_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, fw_download_work.work); + + union power_supply_propval val = { + 0, + }; + bool is_valid_fw = true; + + if (chip->fw_update) { + dev_info(chip->dev, "[rx1619] [%s] FW Update is on going!\n", + __func__); + return; + } + + power_supply_get_property(chip->dc_psy, POWER_SUPPLY_PROP_ONLINE, &val); + if (!val.intval) { + pm_stay_awake(chip->dev); + chip->fw_update = true; + rx_set_reverse_gpio(chip, true); + msleep(100); + rx1619_check_firmware_version(chip, BOOT_AREA); + rx1619_check_firmware_version(chip, RX_AREA); + rx1619_check_firmware_version(chip, TX_AREA); + if (g_fw_rx_id == FW_EMPTY_CODE || + g_fw_rx_id == FW_ERROR_CODE || + g_fw_tx_id == FW_ERROR_CODE || + g_fw_boot_id == FW_ERROR_CODE) + is_valid_fw = false; + + chip->fw_version = g_fw_rx_id; + dev_info(chip->dev, "[rx1619] %s: FW Version is 0x%x\n", + __func__, g_fw_rx_id); + if (g_fw_rx_id) + chip->chip_ok = 1; + else + chip->chip_ok = 0; + + if (is_valid_fw && (g_fw_rx_id >= FW_VERSION)) { + dev_info( + chip->dev, + "[rx1619] %s: FW Version correct so skip upgrade\n", + __func__); + } else { + dev_info(chip->dev, "[rx1619] %s: FW download start\n", + __func__); + if (!rx1619_onekey_download_firmware(chip)) + dev_err(chip->dev, + "[rx1619] [%s] program fw failed!\n", + __func__); + else { + dev_info(chip->dev, + "[rx1619] [%s] FW Update Success!\n", + __func__); + boot_fw_version = + (~fw_data_boot[sizeof(fw_data_boot) - + 1]) & + 0xff; + tx_fw_version = + (~fw_data_tx[sizeof(fw_data_tx) - 1]) & + 0xff; + rx_fw_version = + (~fw_data_rx[sizeof(fw_data_rx) - 1]) & + 0xff; + dev_info( + chip->dev, + "boot_fw_version=0x%x, tx_fw_version=0x%x, rx_fw_version=0x%x\n", + boot_fw_version, tx_fw_version, + rx_fw_version); + chip->fw_version = g_fw_rx_id; + } + } + rx_set_reverse_gpio(chip, false); + chip->fw_update = false; + pm_relax(chip->dev); + } else + dev_err(chip->dev, + "%s: Skip FW download due to wireless charging\n", + __func__); +} + +static void rx1619_pan_tx_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, pan_tx_work.work); + + int soc = 0, batt_sts = 0, dc_level = 0; + int last_icl = 0; + int last_vin = 0; + int ret = 0; + unsigned int vout = 0; + bool vout_change = false; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + + chip->target_vol = ADAPTER_EPP_MI_VOL; + chip->target_curr = 2000000; + + if (chip->batt_psy) { + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, + &val); + dc_level = val.intval; + } + + dev_info(chip->dev, "soc:%d, dc_level:%d, bat_status:%d\n", soc, + dc_level, batt_sts); + + if (dc_level) { + dev_info(chip->dev, "Disable bq, dc_level:%d\n", dc_level); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + } + + switch (chip->status) { + case NORMAL_MODE: + if (soc >= FULL_SOC) + chip->status = TAPER_MODE; + break; + case TAPER_MODE: + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + chip->status = FULL_MODE; + else if (soc < FULL_SOC - 1) + chip->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(chip->dev, "[pan]charge full set Vin 11V\n"); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + dev_info(chip->dev, + "[pan]full mode -> recharge mode\n"); + chip->status = RECHG_MODE; + chip->target_curr = DC_LOW_CURRENT; + } + break; + case RECHG_MODE: + if (batt_sts == POWER_SUPPLY_STATUS_FULL) { + dev_info(chip->dev, + "[pan]recharge mode -> full mode\n"); + chip->status = FULL_MODE; + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + if (chip->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + } + + dev_info(chip->dev, "[pan]recharge mode set icl to 350mA\n"); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = DC_LOW_CURRENT; + + if (chip->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + } + break; + default: + break; + } + + last_vin = chip->last_vin; + last_icl = chip->last_icl; + + if (chip->target_vol > 0 && chip->target_vol != chip->last_vin) { + if (chip->target_vol == ADAPTER_EPP_MI_VOL) { + chip->disable_bq = false; + ret = rx1619_set_vout(chip, chip->target_vol); + if (chip->wireless_psy) { + val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + } else if (chip->target_vol == ADAPTER_EPP_QC3_VOL) { + chip->disable_bq = true; + /* enable 8150b charge */ + if (chip->batt_psy) { + val.intval = 1; + power_supply_set_property( + chip->batt_psy, + POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, + &val); + } + if (chip->wireless_psy) { + val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + + vout = rx1619_get_rx_vout(chip); + while (vout > ADAPTER_EPP_QC3_VOL) { + vout = vout - 1000; + ret = rx1619_set_vout(chip, vout); + msleep(200); + } + ret = rx1619_set_vout(chip, ADAPTER_EPP_QC3_VOL); + } + chip->last_vin = chip->target_vol; + vout_change = true; + } + + if ((chip->target_curr > 0 && chip->target_curr != chip->last_icl) || + vout_change) { + chip->last_icl = chip->target_curr; + rx1619_set_pmi_icl(chip, chip->target_curr); + } + + dev_info( + chip->dev, + "di->status:0x%x,adapter_vol=%d,icl_curr=%d,last_vin=%d,last_icl=%d, bq_dis:%d\n", + chip->status, chip->target_vol, chip->target_curr, + chip->last_vin, chip->last_icl, chip->disable_bq); +} + +static int rx1619_get_effective_fcc(struct rx1619_chg *chip) +{ + int effective_fcc_val = 0; + + if (!chip->fcc_votable) + chip->fcc_votable = find_votable("FCC"); + + if (!chip->fcc_votable) + return -EINVAL; + + effective_fcc_val = get_effective_result(chip->fcc_votable); + effective_fcc_val = effective_fcc_val / 1000; + dev_info(chip->dev, "effective_fcc: %d\n", effective_fcc_val); + return effective_fcc_val; +} + +#define VOICE_LIMIT_FCC_VOTER "VOICE_LIMIT_FCC_VOTER" +#define VOICE_LIMIT_FCC_1A_VOTER "VOICE_LIMIT_FCC_1A_VOTER" +static void rx1619_voice_tx_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, voice_tx_work.work); + + int soc = 0, batt_sts = 0, dc_level = 0, batt_temp = 0; + int last_icl = 0; + int last_vin = 0; + int ret = 0; + int effective_fcc = 0; + unsigned int vout = 0; + bool vout_change = false; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + + chip->target_vol = ADAPTER_EPP_MI_VOL; + chip->target_curr = 2000000; + + if (chip->batt_psy) { + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, + &val); + dc_level = val.intval; + + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_TEMP, &val); + batt_temp = val.intval; + } + + dev_info(chip->dev, + "soc:%d, dc_level:%d, bat_status:%d, batt_temp:%d\n", soc, + dc_level, batt_sts, batt_temp); + + if (batt_temp >= 402) { + dev_info(chip->dev, "[voice]Tbat limit fcc 1A\n"); + effective_fcc = rx1619_get_effective_fcc(chip); + if (chip->fcc_votable) { + effective_fcc = 1000; + vote(chip->fcc_votable, VOICE_LIMIT_FCC_1A_VOTER, true, + effective_fcc * 1000); + } + } else if (batt_temp < 400) { + if (chip->fcc_votable) + vote(chip->fcc_votable, VOICE_LIMIT_FCC_1A_VOTER, false, + 0); + } + + if (batt_temp >= 375) { + dev_info(chip->dev, "[voice]Tbat limit fcc 3.2A\n"); + effective_fcc = rx1619_get_effective_fcc(chip); + if (chip->fcc_votable) { + effective_fcc = 2600; + vote(chip->fcc_votable, VOICE_LIMIT_FCC_VOTER, true, + effective_fcc * 1000); + } + } else if (batt_temp < 367) { + if (chip->fcc_votable) + vote(chip->fcc_votable, VOICE_LIMIT_FCC_VOTER, false, + 0); + } + + if (dc_level > 2) { + dev_info(chip->dev, "[voice]Disable bq, dc_level:%d\n", + dc_level); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + } + + switch (chip->status) { + case NORMAL_MODE: + if (soc >= 95) + chip->status = TAPER_MODE; + break; + case TAPER_MODE: + dev_info(chip->dev, "[voice]taper mode set Vin 11V\n"); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + chip->status = FULL_MODE; + else if (soc < 95) + chip->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(chip->dev, "[voice]charge full set Vin 11V\n"); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + dev_info(chip->dev, + "[voice]full mode -> recharge mode\n"); + chip->status = RECHG_MODE; + chip->target_curr = DC_LOW_CURRENT; + } + break; + case RECHG_MODE: + if (batt_sts == POWER_SUPPLY_STATUS_FULL) { + dev_info(chip->dev, + "[voice]recharge mode -> full mode\n"); + chip->status = FULL_MODE; + chip->target_curr = SCREEN_OFF_FUL_CURRENT; + if (chip->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + } + + dev_info(chip->dev, "[voice]recharge mode set icl to 350mA\n"); + chip->target_vol = ADAPTER_EPP_QC3_VOL; + chip->target_curr = DC_LOW_CURRENT; + + if (chip->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + } + break; + default: + break; + } + + last_vin = chip->last_vin; + last_icl = chip->last_icl; + + if (chip->target_vol > 0 && chip->target_vol != chip->last_vin) { + if (chip->target_vol == ADAPTER_EPP_MI_VOL) { + chip->disable_bq = false; + ret = rx1619_set_vout(chip, chip->target_vol); + if (chip->wireless_psy) { + val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + } else if (chip->target_vol == ADAPTER_EPP_QC3_VOL) { + chip->disable_bq = true; + /* enable 8150b charge */ + if (chip->batt_psy) { + val.intval = 1; + power_supply_set_property( + chip->batt_psy, + POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, + &val); + } + if (chip->wireless_psy) { + val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + + vout = rx1619_get_rx_vout(chip); + while (vout > ADAPTER_EPP_QC3_VOL) { + vout = vout - 1000; + ret = rx1619_set_vout(chip, vout); + msleep(200); + } + ret = rx1619_set_vout(chip, ADAPTER_EPP_QC3_VOL); + } + chip->last_vin = chip->target_vol; + vout_change = true; + } + + if ((chip->target_curr > 0 && chip->target_curr != chip->last_icl) || + vout_change) { + chip->last_icl = chip->target_curr; + rx1619_set_pmi_icl(chip, chip->target_curr); + } + + dev_info( + chip->dev, + "di->status:0x%x,adapter_vol=%d,icl_curr=%d,last_vin=%d,last_icl=%d, bq_dis:%d\n", + chip->status, chip->target_vol, chip->target_curr, + chip->last_vin, chip->last_icl, chip->disable_bq); +} + +static void rx_chg_detect_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, chg_detect_work.work); + union power_supply_propval val = { + 0, + }; + union power_supply_propval pc_val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + int rc; + + dev_info(chip->dev, "[idt] enter %s\n", __func__); + + rc = rx_get_property_names(chip); + if (rc < 0) + return; + + g_chip = chip; + power_supply_get_property(chip->usb_psy, POWER_SUPPLY_PROP_ONLINE, + &val); + power_supply_get_property(chip->pc_port_psy, POWER_SUPPLY_PROP_ONLINE, + &pc_val); + if (val.intval || pc_val.intval) { + dev_info(chip->dev, + "usb_online:%d, pc online:%d set chip disable\n", + val.intval, pc_val.intval); + rx_set_enable_mode(chip, 0); + schedule_delayed_work(&chip->fw_download_work, 1 * HZ); + return; + } + + if (chip->dc_psy) { + power_supply_get_property(chip->dc_psy, + POWER_SUPPLY_PROP_ONLINE, &val); + dev_info(chip->dev, "dc_online %d\n", val.intval); + if (val.intval && chip->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + + if (!chip->power_off_mode) { + rx_set_enable_mode(chip, false); + usleep_range(20000, 25000); + rx_set_enable_mode(chip, true); + } + + schedule_delayed_work(&chip->wireless_int_work, + msecs_to_jiffies(30)); + } + } +} + +static void reverse_chg_sent_state_work(struct work_struct *work) +{ + struct rx1619_chg *chip = container_of(work, struct rx1619_chg, + reverse_sent_state_work.work); + + union power_supply_propval val = { + 0, + }; + + if (chip->wireless_psy) { + val.intval = chip->is_reverse_chg; + power_supply_set_property(chip->wireless_psy, + POWER_SUPPLY_PROP_REVERSE_CHG_STATE, + &val); + dev_info(chip->dev, "sent tx_mode_uevent\n"); + power_supply_changed(chip->wireless_psy); + } else + dev_err(chip->dev, "get wls property error\n"); +} + +static void reverse_chg_state_set_work(struct work_struct *work) +{ + struct rx1619_chg *chip = container_of(work, struct rx1619_chg, + reverse_chg_state_work.work); + int ret; + + dev_info(chip->dev, "no rx found and disable reverse charging\n"); + ret = rx_set_reverse_chg_mode(chip, false); + chip->is_reverse_chg = 1; + schedule_delayed_work(&chip->reverse_sent_state_work, 0); + + return; +} + +static void reverse_dping_state_set_work(struct work_struct *work) +{ + struct rx1619_chg *chip = container_of(work, struct rx1619_chg, + reverse_dping_state_work.work); + int ret; + + dev_info(chip->dev, "tx mode fault and disable reverse charging\n"); + ret = rx_set_reverse_chg_mode(chip, false); + chip->is_reverse_chg = 2; + schedule_delayed_work(&chip->reverse_sent_state_work, 0); + return; +} + +/* power good work */ +static void rx1619_wpc_det_work(struct work_struct *work) +{ + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, wpc_det_work.work); + union power_supply_propval val = { + 0, + }; + int ret = 0; + + chip->wireless_psy = power_supply_get_by_name("wireless"); + if (!chip->wireless_psy) { + dev_err(chip->dev, "[rx1619] no wireless_psy, return\n"); + return; + } + + if (gpio_is_valid(chip->power_good_gpio)) { + ret = gpio_get_value(chip->power_good_gpio); + if (ret) { + dev_info(chip->dev, + "power_good high, wireless attached\n"); + chip->power_good_flag = 1; + val.intval = 1; + schedule_delayed_work(&chip->dc_check_work, + msecs_to_jiffies(2500)); + } else { + dev_info(chip->dev, + "power_good low, wireless detached\n"); + cancel_delayed_work(&chip->dc_check_work); + chip->power_good_flag = 0; + chip->ss = 2; + val.intval = 0; + chip->ln_psy = power_supply_get_by_name("lionsemi"); + if (chip->ln_psy) + power_supply_set_property( + chip->ln_psy, + POWER_SUPPLY_PROP_RESET_DIV_2_MODE, + &val); + } + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, &val); + } +} +static void rx1619_enable_aicl(struct rx1619_chg *chip, bool enable) +{ + union power_supply_propval val = { + 0, + }; + if (chip->wireless_psy) { + if (chip->enabled_aicl != enable) { + val.intval = enable ? 1 : 0; + power_supply_set_property(chip->wireless_psy, + POWER_SUPPLY_PROP_AICL_ENABLE, + &val); + chip->enabled_aicl = enable; + return; + } + } + return; +} +/************AP->RX************/ +//AP set Vout = 0x80 +//AP set Iout = 0x81 +//charge done = 0x82 +//recharge = 0x83 +//sent EPT = 0x84 +//fod factor = 0x85 +//authen req = 0x86 +//usb type req = 0x87 +//fast charge req = 0x88 +//rx fw version = 0x89 +//ap private data pkt = 0x8D +/************AP->RX************/ + +/************RX->AP************/ +//RX NONE = 0x00 +//RX light screen = 0x01 +//RX cali start = 0x02 +//RX cali ok = 0x03 +//RX private id = 0x04 +//RX private authen res = 0x05 +//RX private usb type = 0x06 +//RX private fc status = 0x07 +//RX private data error = 0x0F +/************RX->AP************/ +#define REVERSE_CHG_CHECK_DELAY_MS 100000 +#define REVERSE_DPING_CHECK_DELAY_MS 10000 +#define CMD_TIMEOUT_DELAY_MS 5000 +#define REVERSE_CHG_TX_SWITCH_DONE 8 +static void rx1619_wireless_int_work(struct work_struct *work) +{ + int i = 0; + int uA = 0; + u16 iout = 0; + u16 vout = 0; + u8 usb_type; + u8 rx_rev_data[4] = { 0, 0, 0, 0 }; + u8 data_h, data_l; + u8 tx_req = 0; + u8 rx_req = 0; + u8 g_tx_id_h = 0; + u8 g_tx_id_l = 0; + u8 g_shaone_data_h = 0; + u8 g_shaone_data_l = 0; + u8 g_fc_status = 0; + u8 g_uuid_data[4] = { 0 }; + int tx_gpio, ret; + u8 tx_status, tx_phase; + u8 err_cmd; + static int retry; + static int retry_id; + int rc; + int cnt; + union power_supply_propval cp_val = { + 0, + }; + int fc_flag = 0; + int vol = 0; + + struct rx1619_chg *chip = + container_of(work, struct rx1619_chg, wireless_int_work.work); + + chip->wireless_psy = power_supply_get_by_name("wireless"); + if (!chip->wireless_psy) { + dev_err(chip->dev, "[rx1619] no wireless_psy, return\n"); + return; + } + + tx_gpio = rx_get_reverse_chg_mode(chip); + if (tx_gpio) { + if (rx1619_is_tx_mode(chip)) { + rx1619_write(chip, AP_REV_DATA_OK, + REG_AP_RX_COMM); //receive ok + tx_status = rx1619_get_tx_status(chip); + if (tx_status && + tx_status != REVERSE_CHG_TX_SWITCH_DONE) { + ret = rx_set_reverse_chg_mode(chip, false); + chip->is_reverse_chg = 2; + schedule_delayed_work( + &chip->reverse_sent_state_work, 0); + } else if (tx_status == REVERSE_CHG_TX_SWITCH_DONE) { + dev_err(chip->dev, + "[rx1619] restart because of OTG \n"); + } + tx_phase = rx1619_get_tx_phase(chip); + switch (tx_phase) { + case PING: + //schedule_delayed_work(&chip->reverse_chg_state_work, 80 * HZ); + alarm_start_relative( + &chip->reverse_chg_alarm, + ms_to_ktime( + REVERSE_CHG_CHECK_DELAY_MS)); + //cancel_delayed_work(&chip->reverse_dping_state_work); + rc = alarm_cancel(&chip->reverse_dping_alarm); + if (rc < 0) + dev_err(chip->dev, + "Couldn't cancel reverse_dping_alarm\n"); + pm_relax(chip->dev); + if (tx_status == REVERSE_CHG_TX_SWITCH_DONE) + dev_err(chip->dev, + "reverse restart because of otg insertion\n"); + break; + case TRANSFER: + //cancel_delayed_work(&chip->reverse_chg_state_work); + rc = alarm_cancel(&chip->reverse_chg_alarm); + if (rc < 0) + dev_err(chip->dev, + "Couldn't cancel reverse_dping_alarm\n"); + pm_stay_awake(chip->dev); + /* set reverse charging state to started*/ + chip->is_reverse_chg = 4; + schedule_delayed_work( + &chip->reverse_sent_state_work, 0); + dev_info(chip->dev, "tx mode power transfer\n"); + break; + case POWER_LIM: + dev_info(chip->dev, "tx mode power limit\n"); + break; + case CONFIGURE_CNF: + dev_info(chip->dev, "tx mode CONFIGURE_CNF\n"); + break; + + case CONFIGURE_ERR: + dev_err(chip->dev, "tx mode CONFIGURE_ERR\n"); + break; + default: + dev_err(chip->dev, "tx phase invalid\n"); + break; + } + } + return; + } + + rx1619_read(chip, &rx_req, REG_RX_REV_CMD); //0x0020 + if (rx_req <= 0) { + dev_info(chip->dev, "rx cmd error:%d\n", rx_req); + return; + } + + dev_info(chip->dev, "rx_req = 0x%x\n", rx_req); + + mutex_lock(&chip->wireless_chg_int_lock); + + //read data + rx1619_read(chip, &rx_rev_data[0], REG_RX_REV_DATA1); //0x0021 + rx1619_read(chip, &rx_rev_data[1], REG_RX_REV_DATA2); //0x0022 + rx1619_read(chip, &rx_rev_data[2], REG_RX_REV_DATA3); //0x0023 + rx1619_read(chip, &rx_rev_data[3], REG_RX_REV_DATA4); //0x0024 + + dev_err(chip->dev, "[%s] rx_req,rx_rev_data=0x%x,0x%x,0x%x,0x%x,0x%x\n", + __func__, rx_req, rx_rev_data[0], rx_rev_data[1], + rx_rev_data[2], rx_rev_data[3]); + + switch (rx_req) { + case 0x10: //get epp tx id + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + msleep(10); + chip->epp_tx_id_h = rx_rev_data[0]; //epp tx id high byte + chip->epp_tx_id_l = rx_rev_data[1]; //epp tx id low byte + + if (chip->epp_tx_id_l == 0x59) { + dev_info(chip->dev, + "mophie tx, start dc check after 8s\n"); + schedule_delayed_work(&chip->dc_check_work, + msecs_to_jiffies(8000)); + } else + schedule_delayed_work(&chip->dc_check_work, + msecs_to_jiffies(2500)); + + dev_info(chip->dev, "epp_tx_id_h = 0x%x, epp_tx_id_l = 0x%x\n", + chip->epp_tx_id_h, chip->epp_tx_id_l); + break; + + case 0x01: //LDO on Int + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + chip->epp_max_power = 5; + msleep(10); + + dev_info(chip->dev, "[%s] LDO on Int \n", __func__); + + chip->epp = (rx_rev_data[0] >> 7) & 0xff; + chip->epp_max_power = (rx_rev_data[0] & 0x7f); + g_hw_id_h = rx_rev_data[1]; //0x16 + g_hw_id_l = rx_rev_data[2]; //0x19 + g_fw_rx_id = rx_rev_data[3]; + g_fw_tx_id = (~(fw_data_tx[sizeof(fw_data_tx) - 1])) & 0xff; + if (chip->epp) { //EPP + chip->epp = 1; + rx1619_set_pmi_icl(chip, 30000); + dev_info(chip->dev, + "[%s] EPP--10mA and epp max power is %d\n", + __func__, chip->epp_max_power); + if (chip->wireless_psy) { + cp_val.intval = 2; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_DIV_2_MODE, &cp_val); + msleep(10); + power_supply_get_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_DIV_2_MODE, &cp_val); + chip->op_mode = cp_val.intval; + dev_info(chip->dev, + "loop ln8282 set switch and get: %d\n", + chip->op_mode); + } + msleep(50); + + if (chip->op_mode == LN8282_OPMODE_SWITCHING) { + for (i = 0; i <= 1; i++) { + uA = (600000 + 800000 * i); + rx1619_set_pmi_icl(chip, uA); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + } + } else { + for (i = 0; i <= 1; i++) { + uA = (300000 + 400000 * i); + rx1619_set_pmi_icl(chip, uA); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + usleep_range(10000, 11000); + } + } + } else + rx1619_set_pmi_icl(chip, DC_LOW_CURRENT); + + dev_info( + chip->dev, + "[%s] hw_id_h=0x%x,hw_id_l=0x%x,fw_rx_id=0x%x,g_fw_tx_id=0x%x,g_epp_or_bpp=0x%x\n", + __func__, g_hw_id_h, g_hw_id_l, g_fw_rx_id, g_fw_tx_id, + g_epp_or_bpp); + rx1619_set_fod_param(chip, 0x1); + rx1619_enable_aicl(chip, false); + break; + + case 0x02: //null + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + if (chip->fod_mode == 0x1) { + rx1619_set_fod_param(chip, 0x2); + } else if (chip->fod_mode == 0x2) { + rx1619_set_fod_param(chip, 0x3); + } else if (chip->fod_mode == 0x3) { + rx1619_set_fod_param(chip, 0x4); + } + dev_info(chip->dev, "[rx1619] [%s] fod param setting \n", + __func__); + break; + + case 0x03: //cali ok + rx1619_enable_aicl(chip, true); + + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + dev_info(chip->dev, "[rx1619] [%s] Calibration OK! \n", + __func__); + if (chip->epp && chip->epp_max_power == 10) { //EPP + if (chip->op_mode == LN8282_OPMODE_SWITCHING) + rx1619_set_pmi_icl(chip, 1800000); //10W + else + rx1619_set_pmi_icl(chip, 900000); + } + break; + + case 0x04: //id ok + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + msleep(10); + + rx1619_read(chip, &g_tx_id_h, REG_RX_REV_DATA1); //0x0021 + rx1619_read(chip, &g_tx_id_l, REG_RX_REV_DATA2); //0x0022 + + rx1619_write(chip, PRIVATE_ID_CMD, + REG_RX_SENT_CMD); //0x86 authen req + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + dev_err(chip->dev, "[rx1619] [%s] ID OK! \n", __func__); + break; + + case 0x05: //sha one ok + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + msleep(10); + + rx1619_read(chip, &g_shaone_data_h, REG_RX_REV_DATA1); //0x0021 + rx1619_read(chip, &g_shaone_data_l, REG_RX_REV_DATA2); //0x0022 + + rx1619_request_uuid(chip, chip->epp); + //rx1619_write(chip, PRIVATE_USB_TYPE_CMD, REG_RX_SENT_CMD);//0x87 usb type req + //rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + dev_info(chip->dev, "[rx1619] [%s] SHA ONE OK! \n", __func__); + chip->auth = 1; + if (!chip->epp) + alarm_start_relative(&chip->cmd_timeout_alarm, + ms_to_ktime(CMD_TIMEOUT_DELAY_MS)); + break; + + case 0x06: //USB type 0x6,0x14,0x0,0x19,0x5 + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + msleep(10); + + rx1619_read(chip, &usb_type, REG_RX_REV_DATA1); + + /* + rx1619_write(chip, PRIVATE_FAST_CHG_CMD, REG_RX_SENT_CMD); //0x88 fast charge req + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); +*/ + + if (chip->is_car_tx && (usb_type >= ADAPTER_XIAOMI_QC3)) + usb_type = ADAPTER_ZIMI_CAR_POWER; + + if (chip->is_voice_box_tx) + usb_type = ADAPTER_VOICE_BOX; + dev_info(chip->dev, "[rx1619] [%s] usb_type=0x%x\n", __func__, + usb_type); + g_USB_TYPE = usb_type; + switch (g_USB_TYPE) { + case ADAPTER_QC2: + if (!chip->epp && !chip->is_f1_tx) + chip->target_vol = ADAPTER_BPP_PLUS_VOL; + else + fc_flag = 1; + break; + case ADAPTER_AUTH_FAILED: + case ADAPTER_DCP: + case ADAPTER_CDP: + case ADAPTER_SDP: + fc_flag = 1; + break; + case ADAPTER_QC3: + case ADAPTER_PD: + if (!chip->epp) + chip->target_vol = ADAPTER_BPP_PLUS_VOL; + else + fc_flag = 1; + break; + case ADAPTER_XIAOMI_QC3: + case ADAPTER_XIAOMI_PD: + case ADAPTER_ZIMI_CAR_POWER: + case ADAPTER_XIAOMI_PD_40W: + case ADAPTER_XIAOMI_PD_50W: + case ADAPTER_XIAOMI_PD_60W: + case ADAPTER_VOICE_BOX: + chip->target_vol = ADAPTER_EPP_MI_VOL; + break; + default: + dev_info(chip->dev, "[%s] other Usb_type\n", __func__); + break; + } + if (fc_flag) { + set_usb_type_current(chip, g_USB_TYPE); + schedule_delayed_work(&chip->chg_monitor_work, + msecs_to_jiffies(1000)); + } else { + if (chip->target_vol > 0) { + rx1619_set_adap_vol(chip, chip->target_vol); + chip->last_vin = chip->target_vol; + } + } + + if (chip->wireless_psy) + power_supply_changed(chip->wireless_psy); + break; + + case 0x07: //FC status 0x7,0x1,0x0,0x19,0x5 + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + + rx1619_read(chip, &g_fc_status, REG_RX_REV_DATA1); + dev_info(chip->dev, "[%s] FC status = %d\n", __func__, + g_fc_status); + if (g_fc_status == 1) { + set_usb_type_current(chip, g_USB_TYPE); + dev_info(chip->dev, "[%s] fast charge success!!! \n", + __func__); + schedule_delayed_work(&chip->chg_monitor_work, + msecs_to_jiffies(1000)); + } else { + dev_info(chip->dev, "[%s] fast charge fail!!! \n", + __func__); + if (!chip->epp) { + rx1619_set_pmi_icl(chip, + DC_BPP_AUTH_FAIL_CURRENT); + chip->target_curr = DC_BPP_AUTH_FAIL_CURRENT; + } + } + break; + case 0x0d: + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + if (!chip->epp) + alarm_cancel(&chip->cmd_timeout_alarm); + if (chip->is_compatible_hwid) { + for (i = 0; i < 2; i++) + g_uuid_data[i] = rx_rev_data[i]; + + dev_info(chip->dev, "TX hwid: 0x%x 0x%x\n", + g_uuid_data[0], g_uuid_data[1]); + + if (g_uuid_data[0] == 0x12 && g_uuid_data[1]) + chip->is_f1_tx = 0; + + if (g_uuid_data[0] == 0x16 && g_uuid_data[1] == 0x11) + chip->is_f1_tx = 1; + } else { + for (i = 0; i < 4; i++) + g_uuid_data[i] = rx_rev_data[i]; + + dev_info( + chip->dev, + "vendor:0x%x, module:0x%x, hw:0x%x and power:0x%x\n", + g_uuid_data[0], g_uuid_data[1], g_uuid_data[2], + g_uuid_data[3]); + + if (g_uuid_data[3] == 0x01 && g_uuid_data[1] == 0x2 && + g_uuid_data[2] == 0x8 && g_uuid_data[0] == 0x6) { + chip->is_car_tx = 1; + } else if (g_uuid_data[3] == 0x07 && + g_uuid_data[1] == 0x8 && + g_uuid_data[2] == 0x6 && + g_uuid_data[0] == 0x9) { + chip->is_voice_box_tx = 1; + } else if (g_uuid_data[3] == 0x06 && + g_uuid_data[1] == 0x1 && + g_uuid_data[2] == 0x5 && + g_uuid_data[0] == 0x9) { + chip->is_pan_tx = 1; + } + } + rx1619_write(chip, PRIVATE_USB_TYPE_CMD, + REG_RX_SENT_CMD); //0x87 usb type req + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + + break; + case 0x0f: //error cmd + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + err_cmd = rx_rev_data[0]; + cnt = 0; + dev_info(chip->dev, "[%s] Receive error cmd %d\n", __func__, + err_cmd); + if (!chip->epp && + ((err_cmd == ID_CMD) || (err_cmd == AUTH_CMD) || + (err_cmd == UUID_CMD) || + (err_cmd == PRIVATE_USB_TYPE_CMD))) { + if (err_cmd == ID_CMD && (retry_id < 3)) { + //send device idauth + retry_id++; + rx1619_retry_id_auth(chip); + dev_info(chip->dev, + "[rx1619] id auth failed retry %d\n", + retry_id); + break; + } else if (err_cmd == AUTH_CMD && retry < 3) { + //send device auth + rx1619_send_device_auth(chip); + retry++; + dev_info(chip->dev, + "[rx1619] dev auth failed retry %d\n", + retry); + break; + } else { + retry = 0; + retry_id = 0; + } + g_USB_TYPE = ADAPTER_AUTH_FAILED; + dev_info( + chip->dev, + "[rx1619]auth failed tx charger type set 0x%x\n", + g_USB_TYPE); + alarm_cancel(&chip->cmd_timeout_alarm); + if (chip->epp) { + chip->target_vol = ADAPTER_EPP_QC3_VOL; + if (chip->epp_max_power < 10000) { + uA = ((chip->epp_max_power - 1000) / + 11) * + 1000; + if (chip->op_mode == + LN8282_OPMODE_SWITCHING) + uA = uA * 2; + } else { + if (chip->op_mode == + LN8282_OPMODE_SWITCHING) + uA = USB_20W_PLUS_CURRENT_UA; + else + uA = USB_20W_PLUS_CURRENT_UA / + 2; + } + rx1619_set_pmi_icl(chip, uA); + rx1619_set_vout(chip, chip->target_vol); + } else { + for (i = 0; i < 7; i++) { + uA = (100000 + 100000 * i); + rx1619_set_pmi_icl(chip, uA); + msleep(400); + vol = rx1619_get_rx_vout(chip); + if (vol < 5200) { + msleep(400); + vol = rx1619_get_rx_vout(chip); + if (vol < 5200 && uA > 200000) { + uA = (uA - 100000); + rx1619_set_pmi_icl(chip, + uA); + rx1619_set_vout(chip, + 6000); + break; + } + } + } + + if (i >= 7) { + /*do{ + msleep(400); + vol = rx1619_get_rx_vout(chip); + if (vol < 6300){ + uA = 500000; + rx1619_set_pmi_icl(chip, uA); + break; + } + }while(cnt++<3); + if (cnt == 3) + rx1619_set_pmi_icl(chip, 750000); + */ + rx1619_set_pmi_icl(chip, 750000); + } + dev_info(chip->dev, "[%s] BPP--750mA \n", + __func__); + chip->target_curr = DC_BPP_AUTH_FAIL_CURRENT; + } + } + + if (chip->wireless_psy) + power_supply_changed(chip->wireless_psy); + break; + + case 0x1f: //for product test + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); + msleep(10); + + rx1619_read(chip, &tx_req, REG_RX_REV_DATA1); //0x0021 + + dev_info(chip->dev, "[rx1619] [%s] tx_req=0x%x \n", __func__, + tx_req); + + if (tx_req == 0x12) { //iout + rx1619_write(chip, 0x38, + REG_RX_SENT_DATA1); //sent header + rx1619_write(chip, 0x12, REG_RX_SENT_DATA2); //sent cmd + + iout = rx1619_get_rx_iout(chip); + data_h = (iout & 0x00ff); + data_l = (iout & 0xff00) >> 8; + rx1619_write(chip, data_h, 0x0003); + rx1619_write(chip, data_l, 0x0004); + dev_info( + chip->dev, + "[rx1619] [%s] product test--0x12--0x%x,0x%x iout=%d \n", + __func__, data_h, data_l, iout); + } else if (tx_req == 0x13) { //vout + rx1619_write(chip, 0x38, + REG_RX_SENT_DATA1); //sent header + rx1619_write(chip, 0x13, REG_RX_SENT_DATA2); //sent cmd + + vout = rx1619_get_rx_vout(chip); + data_h = (vout & 0x00ff); + data_l = (vout & 0xff00) >> 8; + rx1619_write(chip, data_h, 0x0003); + rx1619_write(chip, data_l, 0x0004); + dev_info( + chip->dev, + "[rx1619] [%s] product test--0x13--0x%x,0x%x vout=%d \n", + __func__, data_h, data_l, vout); + } else if (tx_req == 0x24) { //firmware Version + rx1619_write(chip, 0x58, + REG_RX_SENT_DATA1); //sent header + rx1619_write(chip, 0x24, REG_RX_SENT_DATA2); //sent cmd + rx1619_write(chip, 0x00, REG_RX_SENT_DATA3); + rx1619_write(chip, 0x00, REG_RX_SENT_DATA4); + rx1619_write(chip, g_fw_rx_id, REG_RX_SENT_DATA5); + rx1619_write(chip, g_fw_tx_id, REG_RX_SENT_DATA6); + dev_info( + chip->dev, + "[rx1619] [%s] product test--0x24--rxtx_fw_version=0x%x,0x%x\n", + __func__, g_fw_rx_id, g_fw_tx_id); + } else if (tx_req == 0x23) { //RX chip ID + rx1619_write(chip, 0x38, + REG_RX_SENT_DATA1); //sent header + rx1619_write(chip, 0x23, REG_RX_SENT_DATA2); //sent cmd + rx1619_write(chip, g_hw_id_h, REG_RX_SENT_DATA3); + rx1619_write(chip, g_hw_id_l, REG_RX_SENT_DATA4); + dev_info( + chip->dev, + "[rx1619] [%s] product test--0x23--rx_hw_id=0x%x,0x%x\n", + __func__, g_hw_id_h, g_hw_id_l); + } else if (tx_req == 0x0b) { //USB type + rx1619_write(chip, 0x28, + REG_RX_SENT_DATA1); //sent header + rx1619_write(chip, 0x0b, REG_RX_SENT_DATA2); //sent cmd + rx1619_write(chip, g_USB_TYPE, REG_RX_SENT_DATA3); + dev_info( + chip->dev, + "[rx1619] [%s] product test--0x25--g_USB_TYPE=0x%x \n", + __func__, g_USB_TYPE); + } else + dev_err(chip->dev, + "[rx1619] [%s] product test--other cmd \n", + __func__); + + rx1619_write(chip, PRIVATE_PRODUCT_TEST_CMD, + REG_RX_SENT_CMD); //sent test cmd + rx1619_write(chip, AP_SENT_DATA_OK, REG_AP_RX_COMM); + break; + + default: + rx1619_write(chip, AP_REV_DATA_OK, REG_AP_RX_COMM); //receive ok + msleep(10); + dev_err(chip->dev, "[rx1619] [%s] other private cmd \n", + __func__); + break; + } + + mutex_unlock(&chip->wireless_chg_int_lock); + + return; +} + +static irqreturn_t rx1619_chg_stat_handler(int irq, void *dev_id) +{ + struct rx1619_chg *chip = dev_id; + //u8 rx_req = 0; + + dev_info(chip->dev, "[%s]\n", __func__); + + schedule_delayed_work(&chip->wireless_int_work, 0); + + return IRQ_HANDLED; +} + +static irqreturn_t rx1619_power_good_handler(int irq, void *dev_id) +{ + struct rx1619_chg *chip = dev_id; + + if (chip->fw_update) + return IRQ_HANDLED; + schedule_delayed_work(&chip->wpc_det_work, msecs_to_jiffies(0)); + + return IRQ_HANDLED; +} + +static int rx1619_parse_dt(struct rx1619_chg *chip) +{ + struct device_node *node = chip->dev->of_node; + + if (!node) { + dev_err(chip->dev, "[rx1619] [%s] No DT data Failing Probe\n", + __func__); + return -EINVAL; + } + + chip->tx_on_gpio = of_get_named_gpio(node, "rx,tx_on_gpio", 0); + if (!gpio_is_valid(chip->tx_on_gpio)) { + dev_err(chip->dev, "[rx1619] [%s] fail_tx_on gpio %d\n", + __func__, chip->tx_on_gpio); + return -EINVAL; + } + + chip->enable_gpio = of_get_named_gpio(node, "rx,enable", 0); + if ((!gpio_is_valid(chip->enable_gpio))) + return -EINVAL; + + chip->irq_gpio = of_get_named_gpio(node, "rx,irq_gpio", 0); + if (!gpio_is_valid(chip->irq_gpio)) { + dev_err(chip->dev, "[rx1619] [%s] fail_irq_gpio %d\n", __func__, + chip->irq_gpio); + return -EINVAL; + } + + chip->power_good_gpio = of_get_named_gpio(node, "rx,power_good", 0); + if (!gpio_is_valid(chip->power_good_gpio)) { + dev_err(chip->dev, "[rx1619] [%s] fail_power_good_gpio %d\n", + __func__, chip->power_good_gpio); + return -EINVAL; + } + + chip->wireless_by_usbin = + of_property_read_bool(node, "mi,wireless-by-usbin"); + + return 0; +} + +static int rx1619_gpio_init(struct rx1619_chg *chip) +{ + int ret = 0; + chip->rx_pinctrl = devm_pinctrl_get(chip->dev); + if (IS_ERR_OR_NULL(chip->rx_pinctrl)) { + dev_err(chip->dev, "No pinctrl config specified\n"); + ret = PTR_ERR(chip->dev); + return ret; + } + + chip->rx_gpio_active = + pinctrl_lookup_state(chip->rx_pinctrl, "nu_active"); + if (IS_ERR_OR_NULL(chip->rx_gpio_active)) { + dev_err(chip->dev, "No active config specified\n"); + ret = PTR_ERR(chip->rx_gpio_active); + return ret; + } + chip->rx_gpio_suspend = + pinctrl_lookup_state(chip->rx_pinctrl, "nu_suspend"); + if (IS_ERR_OR_NULL(chip->rx_gpio_suspend)) { + dev_err(chip->dev, "No suspend config specified\n"); + ret = PTR_ERR(chip->rx_gpio_suspend); + return ret; + } + + ret = pinctrl_select_state(chip->rx_pinctrl, chip->rx_gpio_active); + if (ret < 0) { + dev_err(chip->dev, "fail to select pinctrl active rc=%d\n", + ret); + return ret; + } + + if (gpio_is_valid(chip->irq_gpio)) { + chip->client->irq = gpio_to_irq(chip->irq_gpio); + if (chip->client->irq < 0) { + dev_err(chip->dev, "[rx1619] [%s] gpio_to_irq Fail! \n", + __func__); + goto fail_irq_gpio; + } + } else { + dev_err(chip->dev, "%s: irq gpio not provided\n", __func__); + goto fail_irq_gpio; + } + + if (gpio_is_valid(chip->power_good_gpio)) { + chip->power_good_irq = gpio_to_irq(chip->power_good_gpio); + if (chip->power_good_irq < 0) { + dev_err(chip->dev, "[rx1619] [%s] gpio_to_irq Fail! \n", + __func__); + goto fail_power_good_gpio; + } + } else { + dev_err(chip->dev, "%s: power good gpio not provided\n", + __func__); + goto fail_power_good_gpio; + } + + return ret; + +fail_irq_gpio: + gpio_free(chip->irq_gpio); +fail_power_good_gpio: + gpio_free(chip->power_good_gpio); + + return ret; +} + +/******************************************************* + * SET GPIO STATE TO SMB FOR IGNORE DC_POWER_ON IRQ* + *******************************************************/ +/* define for reverse state of wireless charging */ +#define REVERSE_GPIO_STATE_UNSET 0 +#define REVERSE_GPIO_STATE_START 1 +#define REVERSE_GPIO_STATE_END 2 +static int rx1619_set_reverse_gpio_state(struct rx1619_chg *chip, int enable) +{ + union power_supply_propval reverse_val = { + 0, + }; + chip->reverse_gpio_state = !!enable; + if (!chip->wireless_psy) + chip->wireless_psy = power_supply_get_by_name("wireless"); + + if (chip->wireless_psy) { + dev_dbg(chip->dev, "set_reverse_gpio_state\n", + reverse_val.intval); + if (enable) { + reverse_val.intval = REVERSE_GPIO_STATE_START; + } else { + reverse_val.intval = REVERSE_GPIO_STATE_END; + } + power_supply_set_property(chip->wireless_psy, + POWER_SUPPLY_PROP_REVERSE_GPIO_STATE, + &reverse_val); + } else { + dev_err(chip->dev, "no wireless_psy,return\n"); + return -EINVAL; + } + return 0; +} +static int rx_set_reverse_gpio(struct rx1619_chg *chip, int enable) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + chip->wireless_psy = power_supply_get_by_name("wireless"); + if (!chip->wireless_psy) { + dev_err(chip->dev, "[idt] no wireless_psy,return\n"); + return -EINVAL; + } + + if (enable) { + val.intval = 1; + power_supply_set_property(chip->wireless_psy, + POWER_SUPPLY_PROP_SW_DISABLE_DC_EN, + &val); + } else { + val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, &val); + } + + if (gpio_is_valid(chip->tx_on_gpio)) { + rx1619_set_reverse_gpio_state(chip, enable); + ret = gpio_request(chip->tx_on_gpio, "tx-on-gpio"); + if (ret) { + dev_err(chip->dev, + "%s: unable to request tx_on gpio 130\n", + __func__); + } + ret = gpio_direction_output(chip->tx_on_gpio, enable); + if (ret) { + dev_err(chip->dev, + "%s: cannot set direction for tx_on gpio 130\n", + __func__); + } + + ret = gpio_get_value(chip->tx_on_gpio); + dev_info(chip->dev, "txon gpio: %d\n", ret); + gpio_free(chip->tx_on_gpio); + } else + dev_err(chip->dev, "%s: unable to set tx_on gpio_130\n"); + + return ret; +} + +static int rx_get_reverse_chg_mode(struct rx1619_chg *chip) +{ + int ret; + + if (gpio_is_valid(chip->tx_on_gpio)) + ret = gpio_get_value(chip->tx_on_gpio); + else { + dev_err(chip->dev, "%s: txon gpio not provided\n", __func__); + ret = -1; + } + dev_info(chip->dev, "txon gpio: %d\n", ret); + + return ret; +} + +#define REVERSE_COUNTRY_DOMESTIC 0 +#define REVERSE_COUNTRY_INTERNATIONAL 1 + +#define REVERSE_CURRENT_1000MA 0x0A +#define REVERSE_CURRENT_500MA 0x05 + +static int rx_set_reverse_chg_mode(struct rx1619_chg *chip, int enable) +{ + union power_supply_propval cp_val = { + 0, + }; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + int ret, rc; + + chip->wireless_psy = power_supply_get_by_name("wireless"); + if (!chip->wireless_psy) { + dev_err(chip->dev, "[idt] no wireless_psy,return\n"); + return -EINVAL; + } + + if (enable) { + val.intval = 1; + power_supply_set_property(chip->wireless_psy, + POWER_SUPPLY_PROP_SW_DISABLE_DC_EN, + &val); + } else { + val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, &val); + } + + if (gpio_is_valid(chip->tx_on_gpio)) { + rx1619_set_reverse_gpio_state(chip, enable); + ret = gpio_request(chip->tx_on_gpio, "tx-on-gpio"); + if (ret) { + dev_err(chip->dev, + "%s: unable to request tx_on gpio 130\n", + __func__); + } + ret = gpio_direction_output(chip->tx_on_gpio, enable); + if (ret) { + dev_err(chip->dev, + "%s: cannot set direction for tx_on gpio 130\n", + __func__); + } + gpio_free(chip->tx_on_gpio); + power_supply_changed(chip->wireless_psy); + dev_info(chip->dev, + "reverse_charge, set ln8282 powerpath and opmode\n"); + msleep(100); + if (enable) { + if (chip->wireless_psy) { + cp_val.intval = 3; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_DIV_2_MODE, &cp_val); + wk_val.intval = 1; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + msleep(100); + /* set reverse mode according to hw country */ + if (chip->hw_country == CountryGlobal || + chip->is_otg_insert) { + rx1619_set_reverse_parameter( + chip, REVERSE_COUNTRY_INTERNATIONAL, + REVERSE_CURRENT_500MA); + } else { + rx1619_set_reverse_parameter( + chip, REVERSE_COUNTRY_DOMESTIC, + REVERSE_CURRENT_1000MA); + } + /* set reverse fod */ + rx1619_set_reverse_fod(chip, 0, 0); + rx1619_start_tx_function(chip); + alarm_start_relative( + &chip->reverse_dping_alarm, + ms_to_ktime(REVERSE_DPING_CHECK_DELAY_MS)); + //schedule_delayed_work(&chip->reverse_dping_state_work, 10 * HZ); + } else { + dev_info(chip->dev, + "disable reverse charging for wireless\n"); + if (chip->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + chip->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + cancel_delayed_work(&chip->reverse_chg_state_work); + cancel_delayed_work(&chip->reverse_dping_state_work); + + rc = alarm_cancel(&chip->reverse_dping_alarm); + if (rc < 0) + dev_err(chip->dev, + "Couldn't cancel reverse_dping_alarm\n"); + + rc = alarm_cancel(&chip->reverse_chg_alarm); + if (rc < 0) + dev_err(chip->dev, + "Couldn't cancel reverse_chg_alarm\n"); + pm_relax(chip->dev); + } + } else + dev_err(chip->dev, "%s: unable to set tx_on gpio_130\n"); + + return ret; +} + +static enum alarmtimer_restart reverse_chg_alarm_cb(struct alarm *alarm, + ktime_t now) +{ + struct rx1619_chg *chip = + container_of(alarm, struct rx1619_chg, reverse_chg_alarm); + + dev_info(chip->dev, " Reverse Chg Alarm Triggered %lld\n", + ktime_to_ms(now)); + + /* Atomic context, cannot use voter */ + pm_stay_awake(chip->dev); + schedule_delayed_work(&chip->reverse_chg_state_work, 0); + + return ALARMTIMER_NORESTART; +} + +static enum alarmtimer_restart cmd_timeout_alarm_cb(struct alarm *alarm, + ktime_t now) +{ + struct rx1619_chg *chip = + container_of(alarm, struct rx1619_chg, cmd_timeout_alarm); + + dev_info(chip->dev, " CMD_timeout_alarm Triggered %lld\n", + ktime_to_ms(now)); + + /* Atomic context, cannot use voter */ + schedule_delayed_work(&chip->cmd_timeout_work, 0); + + return ALARMTIMER_NORESTART; +} + +static enum alarmtimer_restart reverse_dping_alarm_cb(struct alarm *alarm, + ktime_t now) +{ + struct rx1619_chg *chip = + container_of(alarm, struct rx1619_chg, reverse_dping_alarm); + + dev_info(chip->dev, "Reverse Dping Alarm Triggered %lld\n", + ktime_to_ms(now)); + + /* Atomic context, cannot use voter */ + pm_stay_awake(chip->dev); + schedule_delayed_work(&chip->reverse_dping_state_work, 0); + + return ALARMTIMER_NORESTART; +} + +static void rx1619_set_present(struct rx1619_chg *chip, int enable) +{ + union power_supply_propval val = { + 0, + }; + + dev_info(chip->dev, "dc plug %s\n", enable ? "in" : "out"); + + if (enable) { + chip->dcin_present = 1; + } else { + chip->dcin_present = 0; + g_id_done_flag = 0; + g_epp_or_bpp = BPP_MODE; + chip->epp = 0; + chip->auth = 0; + chip->count_10v = 0; + chip->count_15v = 0; + chip->epp_exchange = 0; + chip->exchange = 0; + chip->last_vin = 0; + chip->last_icl = 0; + chip->last_qc3_icl = 0; + chip->op_mode = LN8282_OPMODE_UNKNOWN; + chip->status = NORMAL_MODE; + chip->target_vol = 0; + chip->target_curr = 0; + chip->is_car_tx = 0; + chip->is_voice_box_tx = 0; + g_USB_TYPE = 0; + chip->is_pan_tx = 0; + chip->disable_bq = false; + cancel_delayed_work_sync(&chip->wireless_int_work); + cancel_delayed_work(&chip->chg_monitor_work); + chip->ln_psy = power_supply_get_by_name("lionsemi"); + if (chip->ln_psy) + power_supply_set_property( + chip->ln_psy, + POWER_SUPPLY_PROP_RESET_DIV_2_MODE, &val); + + /* enable aicl if disabled by wireless earlier */ + rx1619_enable_aicl(chip, true); + if (chip->fcc_votable) { + vote(chip->fcc_votable, VOICE_LIMIT_FCC_VOTER, false, + 0); + vote(chip->fcc_votable, VOICE_LIMIT_FCC_1A_VOTER, false, + 0); + } + } +} +/* set otg state while reverse status */ +#define OTG_REG_ADDR 0x00 +#define OTG_PLUGIN_CMD 0x12 +#define OTG_PLUGOUT_CMD 0x11 +#define OTG_STATUS_CMD 0x0000 +#define OTG_TRIGGER_ADDR 0x000C +#define OTG_TRIGGER_CMD 0x55 + +static int rx_set_otg_state(struct rx1619_chg *chip, int plugin) +{ + int otg_status_cmd; + + chip->is_otg_insert = !!plugin; + + if (plugin) + otg_status_cmd = OTG_PLUGIN_CMD; + else + otg_status_cmd = OTG_PLUGOUT_CMD; + + dev_info(g_chip->dev, "set otg state: %d\n", plugin); + + if (chip->reverse_gpio_state) { + rx1619_write(chip, otg_status_cmd, OTG_REG_ADDR); + rx1619_write(chip, OTG_TRIGGER_CMD, OTG_TRIGGER_ADDR); + } + + return 0; +} + +static int rx_set_enable_mode(struct rx1619_chg *chip, int enable) +{ + int ret = 0; + int gpio_enable_val = 0; + + if (gpio_is_valid(chip->enable_gpio)) { + ret = gpio_request(chip->enable_gpio, "rx-enable-gpio"); + if (ret) { + dev_err(chip->dev, + "%s: unable to request enable gpio [%d]\n", + __func__, chip->enable_gpio); + } + + ret = gpio_direction_output(chip->enable_gpio, !enable); + if (ret) { + dev_err(chip->dev, + "%s: cannot set direction for idt enable gpio [%d]\n", + __func__, chip->enable_gpio); + } + gpio_enable_val = gpio_get_value(chip->enable_gpio); + pr_info("rx1619 enable gpio val is :%d\n", gpio_enable_val); + gpio_free(chip->enable_gpio); + } + + return ret; +} + +static ssize_t chip_vrect_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned int vrect = 0; + + vrect = rx1619_get_rx_vrect(g_chip); + + return scnprintf(buf, PAGE_SIZE, "rx1619 Vrect : %d mV\n", vrect); +} + +static ssize_t chip_vout_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + unsigned int vout = 0; + + vout = rx1619_get_rx_vout(g_chip); + + return scnprintf(buf, PAGE_SIZE, "%d\n", vout); +} + +static ssize_t chip_iout_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + unsigned int iout = 0; + + iout = rx1619_get_rx_iout(g_chip); + + return scnprintf(buf, PAGE_SIZE, "%d\n", iout); +} + +static ssize_t chip_vout_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int index; + + index = (int)simple_strtoul(buf, NULL, 10); + dev_info(g_chip->dev, "[rx1619] [%s] --Store output_voltage = %d\n", + __func__, index); + if ((index < 4000) || (index > 21000)) { + dev_err(g_chip->dev, + "[rx1619] [%s] Store Voltage %s is invalid\n", __func__, + buf); + rx1619_set_vout(g_chip, 0); + return count; + } + + rx1619_set_vout(g_chip, index); + + return count; +} + +static ssize_t chip_debug_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 data = 0; + + rx1619_dump_reg(); + msleep(100); + rx1619_get_rx_vout(g_chip); + rx1619_get_rx_vrect(g_chip); + rx1619_get_rx_iout(g_chip); + + return scnprintf(buf, PAGE_SIZE, "AP REQ DATA : 0x%x \n", data); +} + +static ssize_t chip_debug_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + return count; +} + +static ssize_t chip_fod_parameter_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int i; + for (i = 0; i < 8; i++) { + fod_param[i] = + (char)simple_strtoul(buf, NULL, 16); //fod_param[0] + buf += 3; + } + + for (i = 0; i < 8; i++) + dev_info(g_chip->dev, "[%s]: fod_param[%d] = 0x%x\n", __func__, + i, fod_param[i]); + + return count; +} + +static ssize_t chip_firmware_update_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + bool ret = false; + u8 boot_project_id_h = 0; + u8 boot_project_id_l = 0; + u8 tx_project_id_h = 0; + u8 tx_project_id_l = 0; + u8 rx_project_id_h = 0; + u8 rx_project_id_l = 0; + + dev_info(g_chip->dev, "[rx1619] [%s] Firmware Update begin\n", + __func__); + + if (g_chip->fw_update) { + dev_err(g_chip->dev, + "[rx1619] [%s] Firmware Update is on going!\n", + __func__); + return scnprintf(buf, PAGE_SIZE, "Firmware Update:Failed\n"); + } + + g_chip->fw_update = true; + rx_set_reverse_gpio(g_chip, true); + msleep(100); + ret = rx1619_onekey_download_firmware(g_chip); + if (!ret) { + dev_err(g_chip->dev, + "[rx1619] [%s] Firmware Update failed! Please try again!\n", + __func__); + rx_set_reverse_gpio(g_chip, false); + g_chip->fw_update = false; + return scnprintf(buf, PAGE_SIZE, "Firmware Update:Failed\n"); + + } else { + boot_fw_version = (~fw_data_boot[sizeof(fw_data_boot) - 1]) & + 0xff; + tx_fw_version = (~fw_data_tx[sizeof(fw_data_tx) - 1]) & 0xff; + rx_fw_version = (~fw_data_rx[sizeof(fw_data_rx) - 1]) & 0xff; + boot_project_id_h = (~fw_data_boot[sizeof(fw_data_boot) - 3]) & + 0xff; + boot_project_id_l = (~fw_data_boot[sizeof(fw_data_boot) - 2]) & + 0xff; + tx_project_id_h = (~fw_data_tx[sizeof(fw_data_tx) - 3]) & 0xff; + tx_project_id_l = (~fw_data_tx[sizeof(fw_data_tx) - 2]) & 0xff; + rx_project_id_h = (~fw_data_rx[sizeof(fw_data_rx) - 3]) & 0xff; + rx_project_id_l = (~fw_data_rx[sizeof(fw_data_rx) - 2]) & 0xff; + + dev_info( + g_chip->dev, + "boot_fw_version=%c%c_V%02x, tx_fw_version=%c%c_V%02x, rx_fw_version=%c%c_V%02x \n", + boot_project_id_h, boot_project_id_l, boot_fw_version, + tx_project_id_h, tx_project_id_l, tx_fw_version, + rx_project_id_h, rx_project_id_l, rx_fw_version); + + dev_info(g_chip->dev, + "[rx1619] [%s] Firmware Update Success!!! \n", + __func__); + rx_set_reverse_gpio(g_chip, false); + g_chip->fw_update = false; + g_chip->fw_version = g_fw_rx_id; + return scnprintf(buf, PAGE_SIZE, "Firmware Update:Success\n"); + } +} + +static ssize_t chip_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (!g_chip->fw_update) { + g_chip->fw_update = true; + rx_set_reverse_gpio(g_chip, true); + msleep(100); + rx1619_check_firmware_version(g_chip, BOOT_AREA); + rx1619_check_firmware_version(g_chip, TX_AREA); + rx1619_check_firmware_version(g_chip, RX_AREA); + rx_set_reverse_gpio(g_chip, false); + g_chip->fw_update = false; + return scnprintf(buf, PAGE_SIZE, + "app_ver:%02x.%02x.%02x.%x%x\n", g_fw_boot_id, + g_fw_tx_id, g_fw_rx_id, g_hw_id_h, g_hw_id_l); + } else { + return scnprintf(buf, PAGE_SIZE, + "fw update on going, cannot show version\n"); + } +} + +static ssize_t chip_vout_calibration_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int index = 0; + + index = (int)simple_strtoul(buf, NULL, 10); + + g_Delta = index; + dev_err(g_chip->dev, "[rx1619] [%s] g_Delta = %d \n", __func__, + g_Delta); + + return count; +} + +static ssize_t txon_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int mode; + + mode = rx_get_reverse_chg_mode(g_chip); + + return scnprintf(buf, PAGE_SIZE, "reverse chg mode : %d\n", mode); +} + +static ssize_t txon_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret, enable; + + ret = (int)simple_strtoul(buf, NULL, 10); + enable = !!ret; + + rx_set_reverse_gpio(g_chip, enable); + + return count; +} + +static ssize_t attr_firmware_bin_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + bool ret = false; + ret = rx1619_push_rx_firmware(g_chip); + if (!ret) { + dev_err(g_chip->dev, + "[rx1619] [%s] RX Firmware Push failed! Please try again!\n", + __func__); + return scnprintf( + buf, PAGE_SIZE, + "RX Firmware Push failed! Please try again! \n"); + + } else { + dev_info(g_chip->dev, "rx_fw_version=%c%c_V%02x \n", + rx_bin_project_id_h, rx_bin_project_id_l, + rx_fw_version); + dev_info(g_chip->dev, + "[rx1619] [%s] RX Firmware Push Success!!! \n", + __func__); + return scnprintf( + buf, PAGE_SIZE, + "RX Firmware Push Success!!! rx_fw_ver=%c%c_V%02x\n", + rx_bin_project_id_h, rx_bin_project_id_l, + rx_fw_version); + } +} + +static ssize_t attr_firmware_bin_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 *rx_fw_bin = NULL; + if (g_chip->rx_fw_len + count >= 3 * 1024 * 1024) { + dev_err(g_chip->dev, "The firmware is too large.\n"); + goto out; + } + + rx_fw_bin = kmalloc(count + g_chip->rx_fw_len, GFP_KERNEL); + if (rx_fw_bin == NULL) { + dev_err(g_chip->dev, "write %d bytes failed.\n", (int)count); + goto out; + } + + memcpy(rx_fw_bin, g_chip->rx_fw_bin, g_chip->rx_fw_len); + memcpy(rx_fw_bin + g_chip->rx_fw_len, buf, count); + if (g_chip->rx_fw_bin != NULL) { + kfree(g_chip->rx_fw_bin); + } + g_chip->rx_fw_bin = rx_fw_bin; + g_chip->rx_fw_len += count; + +out: + return count; +} +static DEVICE_ATTR(chip_vrect, S_IRUGO, chip_vrect_show, NULL); +static DEVICE_ATTR(chip_vout_calibration, S_IWUSR, NULL, + chip_vout_calibration_store); +static DEVICE_ATTR(chip_firmware_update, S_IWUSR | S_IRUGO, + chip_firmware_update_show, NULL); +static DEVICE_ATTR(chip_fw_bin, S_IWUSR | S_IRUGO, attr_firmware_bin_show, + attr_firmware_bin_store); +static DEVICE_ATTR(chip_version, S_IRUGO, chip_version_show, NULL); +static DEVICE_ATTR(chip_vout, S_IWUSR | S_IRUGO, chip_vout_show, + chip_vout_store); +static DEVICE_ATTR(chip_iout, S_IRUGO, chip_iout_show, NULL); +static DEVICE_ATTR(chip_debug, S_IWUSR | S_IRUGO, chip_debug_show, + chip_debug_store); +static DEVICE_ATTR(txon, S_IWUSR | S_IRUGO, txon_show, txon_store); +static DEVICE_ATTR(chip_fod_parameter, S_IWUSR | S_IRUGO, NULL, + chip_fod_parameter_store); + +static struct attribute *rx1619_sysfs_attrs[] = { + &dev_attr_chip_vrect.attr, + &dev_attr_chip_version.attr, + &dev_attr_chip_vout.attr, + &dev_attr_chip_iout.attr, + &dev_attr_chip_debug.attr, + &dev_attr_chip_fw_bin.attr, + &dev_attr_chip_firmware_update.attr, + &dev_attr_chip_vout_calibration.attr, + &dev_attr_txon.attr, + &dev_attr_chip_fod_parameter.attr, + NULL, +}; + +static const struct attribute_group rx1619_sysfs_group_attrs = { + .attrs = rx1619_sysfs_attrs, +}; + +#if 1 +static enum power_supply_property rx1619_wireless_properties[] = { + /* + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_CHARGING_ENABLED, + POWER_SUPPLY_PROP_RX_CHIP_ID, //RX chip id + POWER_SUPPLY_PROP_RX_VRECT, //RX vrect + POWER_SUPPLY_PROP_RX_IOUT, //RX output current + POWER_SUPPLY_PROP_RX_VOUT, //RX output voltage + POWER_SUPPLY_PROP_RX_ILIMIT, //RX Main LDO output current limit + POWER_SUPPLY_PROP_VOUT_SET, //Vout voltage set + */ + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, + POWER_SUPPLY_PROP_PIN_ENABLED, + POWER_SUPPLY_PROP_REVERSE_CHG_MODE, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT, + POWER_SUPPLY_PROP_RX_IOUT, + POWER_SUPPLY_PROP_TX_ADAPTER, + POWER_SUPPLY_PROP_WIRELESS_VERSION, + POWER_SUPPLY_PROP_WIRELESS_FW_VERSION, + POWER_SUPPLY_PROP_CHIP_OK, + POWER_SUPPLY_PROP_OTG_STATE, +}; + +static int rx1619_wireless_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + int ret; + struct rx1619_chg *chip = power_supply_get_drvdata(psy); + int data; + + switch (prop) { + /* + case POWER_SUPPLY_PROP_PRESENT: + break; + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + rx1619_chip_enable(chip, val->intval); + break; + case POWER_SUPPLY_PROP_VOUT_SET: + ret = rx1619_set_vout(chip, val->intval); + if(ret < 0) + return ret; + break; + */ + case POWER_SUPPLY_PROP_PRESENT: + rx1619_set_present(chip, val->intval); + break; + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + chip->ss = val->intval; + if (chip->wireless_psy) + power_supply_changed(chip->wireless_psy); + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + data = val->intval / 1000; + if (data < ADAPTER_VOUT_LIMIT_VOL) + data = ADAPTER_VOUT_LIMIT_VOL; + else if (data > 10000) + data = 10000; + if (chip->op_mode == LN8282_OPMODE_SWITCHING) + data *= 2; + else if (chip->epp) + data = EPP_VOL_THRESHOLD; + if (!chip->disable_bq) + ret = rx1619_set_vout(chip, data); + break; + case POWER_SUPPLY_PROP_PIN_ENABLED: + ret = rx_set_enable_mode(chip, val->intval); + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + if (chip->fw_update) { + dev_info(chip->dev, "fw update going, break\n"); + break; + } + chip->is_reverse_chg = 0; + schedule_delayed_work(&chip->reverse_sent_state_work, 0); + if (!chip->power_good_flag) { + ret = rx_set_reverse_chg_mode(chip, val->intval); + } else { + chip->is_reverse_chg = 3; + schedule_delayed_work(&chip->reverse_sent_state_work, + 0); + } + break; + case POWER_SUPPLY_PROP_OTG_STATE: + rx_set_otg_state(chip, val->intval); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rx1619_wireless_get_property(struct power_supply *psy, + enum power_supply_property prop, + union power_supply_propval *val) +{ + int tmp; + struct rx1619_chg *chip = power_supply_get_drvdata(psy); + + switch (prop) { + /* + case POWER_SUPPLY_PROP_ONLINE: + val->intval = chip->online; + break; + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + val->intval = chip->chip_enable; + break; + case POWER_SUPPLY_PROP_RX_CHIP_ID: + val->intval = rx1619_get_rx_chip_id(chip); + break; + case POWER_SUPPLY_PROP_RX_VRECT: + val->intval = rx1619_get_rx_vrect(chip); + break; + case POWER_SUPPLY_PROP_RX_IOUT: + val->intval = rx1619_get_rx_iout(chip); + break; + case POWER_SUPPLY_PROP_RX_VOUT: + val->intval = rx1619_get_rx_vout(chip); + break; + case POWER_SUPPLY_PROP_VOUT_SET: + val->intval = 0; + break; + */ + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + val->intval = chip->epp; + break; + case POWER_SUPPLY_PROP_WIRELESS_FW_VERSION: + val->intval = chip->fw_version; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = chip->dcin_present; + break; + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + val->intval = chip->ss; + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + if (!chip->power_good_flag) { + val->intval = 0; + break; + } + tmp = rx1619_get_rx_vout(chip); + if (chip->op_mode == LN8282_OPMODE_SWITCHING) + val->intval = tmp / 2; + else + val->intval = tmp; + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT: + val->intval = rx1619_get_rx_vrect(chip); + break; + case POWER_SUPPLY_PROP_RX_IOUT: + val->intval = rx1619_get_rx_iout(chip); + break; + case POWER_SUPPLY_PROP_PIN_ENABLED: + val->intval = !gpio_get_value(chip->enable_gpio); + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + val->intval = rx_get_reverse_chg_mode(chip); + break; + case POWER_SUPPLY_PROP_TX_ADAPTER: + val->intval = g_USB_TYPE; + break; + case POWER_SUPPLY_PROP_CHIP_OK: + val->intval = chip->chip_ok; + break; + default: + return -EINVAL; + } + return 0; +} +#endif + +// first step: define regmap_config +static const struct regmap_config rx1619_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0xFFFF, +}; + +static int rx1619_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + int rc; + + switch (psp) { + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + case POWER_SUPPLY_PROP_PIN_ENABLED: + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + case POWER_SUPPLY_PROP_PRESENT: + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + return 1; + default: + rc = 0; + break; + } + + return rc; +} + +extern char *saved_command_line; + +static int get_cmdline(struct rx1619_chg *chip) +{ + if (strnstr(saved_command_line, + "androidboot.mode=", strlen(saved_command_line))) { + chip->power_off_mode = 1; + dev_info(chip->dev, + "[idtp9220]: enter power off charging app\n"); + } else { + chip->power_off_mode = 0; + dev_info(chip->dev, "[idtp9220]: enter normal boot mode\n"); + } + return 1; +} + +static int rx1619_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct rx1619_chg *chip; + struct kobject *rx1619_kobj; + //int drv_load = 0; + + struct power_supply_config wip_psy_cfg = {}; + /* + drv_load = get_board_version(); + if (!drv_load) + return 0; +*/ + + /* + int hw_id; + + struct power_supply *batt_psy; + + batt_psy = power_supply_get_by_name("battery"); + if (!batt_psy) { + dev_err(&client->dev, "Battery supply not found; defer probe\n"); + return -EPROBE_DEFER; + } + + hw_id = get_hw_country_version(); + dev_info(&client->dev, "[rx1619] %s: hw_id is %d\n", __func__, hw_id); + if (hw_id) //hw_id=1 is idt + return 0; + */ + + chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) { + dev_err(&client->dev, + "i2c allocated device info data failed!\n"); + return -ENOMEM; + } + + chip->regmap = regmap_init_i2c(client, &rx1619_regmap_config); + if (!chip->regmap) { + dev_err(&client->dev, "parent regmap is missing\n"); + return -EINVAL; + } + + chip->client = client; + chip->dev = &client->dev; + + //chip->batt_psy = batt_psy; + //chip->online = 0; + chip->chip_enable = false; + chip->ss = 2; + chip->fw_update = false; + chip->fw_version = 0; + + device_init_wakeup(&client->dev, true); + i2c_set_clientdata(client, chip); + + rx1619_parse_dt(chip); + rx1619_gpio_init(chip); + + mutex_init(&chip->wireless_chg_lock); + mutex_init(&chip->wireless_chg_int_lock); + mutex_init(&chip->sysfs_op_lock); + INIT_DELAYED_WORK(&chip->wireless_int_work, rx1619_wireless_int_work); + INIT_DELAYED_WORK(&chip->wpc_det_work, rx1619_wpc_det_work); + INIT_DELAYED_WORK(&chip->chg_monitor_work, rx_monitor_work); + INIT_DELAYED_WORK(&chip->chg_detect_work, rx_chg_detect_work); + INIT_DELAYED_WORK(&chip->reverse_sent_state_work, + reverse_chg_sent_state_work); + INIT_DELAYED_WORK(&chip->reverse_chg_state_work, + reverse_chg_state_set_work); + INIT_DELAYED_WORK(&chip->reverse_dping_state_work, + reverse_dping_state_set_work); + INIT_DELAYED_WORK(&chip->dc_check_work, rx1619_dc_check_work); + INIT_DELAYED_WORK(&chip->cmd_timeout_work, rx1619_cmd_timeout_work); + INIT_DELAYED_WORK(&chip->fw_download_work, rx1619_fw_download_work); + INIT_DELAYED_WORK(&chip->rx_first_boot, rx1619_rx_first_boot); + INIT_DELAYED_WORK(&chip->pan_tx_work, rx1619_pan_tx_work); + INIT_DELAYED_WORK(&chip->voice_tx_work, rx1619_voice_tx_work); + + chip->wip_psy_d.name = "rx1619"; + chip->wip_psy_d.type = POWER_SUPPLY_TYPE_WIRELESS; + chip->wip_psy_d.get_property = rx1619_wireless_get_property; + chip->wip_psy_d.set_property = rx1619_wireless_set_property; + chip->wip_psy_d.properties = rx1619_wireless_properties; + chip->wip_psy_d.num_properties = ARRAY_SIZE(rx1619_wireless_properties); + chip->wip_psy_d.property_is_writeable = rx1619_prop_is_writeable, + + wip_psy_cfg.drv_data = chip; + + chip->wip_psy = devm_power_supply_register(chip->dev, &chip->wip_psy_d, + &wip_psy_cfg); + if (IS_ERR(chip->wip_psy)) { + dev_err(chip->dev, "Couldn't register wip psy rc=%ld\n", + PTR_ERR(chip->wip_psy)); + return ret; + } + + if (chip->client->irq) { + ret = devm_request_threaded_irq( + &chip->client->dev, chip->client->irq, NULL, + rx1619_chg_stat_handler, + (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | + IRQF_ONESHOT), + "rx1619_chg_stat_irq", chip); + if (ret) { + dev_err(chip->dev, "Failed irq = %d ret = %d\n", + chip->client->irq, ret); + } + } + enable_irq_wake(chip->client->irq); + + if (chip->power_good_irq) { + ret = devm_request_threaded_irq( + &chip->client->dev, chip->power_good_irq, NULL, + rx1619_power_good_handler, + (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | + IRQF_ONESHOT), + "rx1619_power_good_irq", chip); + if (ret) { + dev_err(chip->dev, "Failed irq = %d ret = %d\n", + chip->power_good_irq, ret); + } + } + enable_irq_wake(chip->power_good_irq); + + rx1619_kobj = kobject_create_and_add("rx1619", NULL); + if (!rx1619_kobj) { + dev_err(chip->dev, "sysfs_create_group fail"); + goto error_sysfs; + } + ret = sysfs_create_group(rx1619_kobj, &rx1619_sysfs_group_attrs); + if (ret < 0) { + dev_err(chip->dev, "sysfs_create_group fail %d\n", ret); + goto error_sysfs; + } + + determine_initial_status(chip); + + //rx1619_dump_reg(); + g_chip = chip; + + if (alarmtimer_get_rtcdev()) { + alarm_init(&chip->reverse_dping_alarm, ALARM_BOOTTIME, + reverse_dping_alarm_cb); + } else { + dev_err(chip->dev, + "Failed to initialize reverse dping alarm\n"); + return -ENODEV; + } + + if (alarmtimer_get_rtcdev()) { + alarm_init(&chip->reverse_chg_alarm, ALARM_BOOTTIME, + reverse_chg_alarm_cb); + } else { + dev_err(chip->dev, "Failed to initialize reverse chg alarm\n"); + return -ENODEV; + } + + if (alarmtimer_get_rtcdev()) { + alarm_init(&chip->cmd_timeout_alarm, ALARM_BOOTTIME, + cmd_timeout_alarm_cb); + } else { + dev_err(chip->dev, "Failed to initialize cmd_timeout_alarm\n"); + return -ENODEV; + } + chip->hw_country = get_hw_country_version(); + dev_info(&client->dev, "hw_country: %d\n", chip->hw_country); + + dev_err(chip->dev, "[rx1619] [%s] success! \n", __func__); + get_cmdline(chip); + + if (chip->power_off_mode) { + rx_set_enable_mode(chip, false); + usleep_range(20000, 25000); + rx_set_enable_mode(chip, true); + } else { + schedule_delayed_work(&chip->chg_detect_work, 3 * HZ); + } + if (!g_rx1619_first_flag) + schedule_delayed_work(&chip->rx_first_boot, + msecs_to_jiffies(45000)); + return 0; + +error_sysfs: + sysfs_remove_group(rx1619_kobj, &rx1619_sysfs_group_attrs); + dev_err(chip->dev, "[rx1619] [%s] rx1619 probe error_sysfs! \n", + __func__); + + if (chip->irq_gpio > 0) + gpio_free(chip->irq_gpio); + + return 0; +} + +static void rx1619_shutdown(struct i2c_client *client) +{ + struct rx1619_chg *chip = i2c_get_clientdata(client); + + if (chip->power_good_flag) { + rx_set_enable_mode(chip, false); + usleep_range(20000, 25000); + rx_set_enable_mode(chip, true); + } +} + +static int rx1619_remove(struct i2c_client *client) +{ + struct rx1619_chg *chip = i2c_get_clientdata(client); + cancel_delayed_work_sync(&chip->wireless_int_work); + + return 0; +} +static const struct i2c_device_id rx1619_id[] = { + { rx1619_DRIVER_NAME, 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, rx1619_id); + +static struct of_device_id rx1619_match_table[] = { + { + .compatible = "nuvolta,wl_charger_rx1619", + }, + {} +}; + +static struct i2c_driver rx1619_driver = { + .driver = { + .name = rx1619_DRIVER_NAME, + .of_match_table = rx1619_match_table, + }, + .probe = rx1619_probe, + .remove = rx1619_remove, + .shutdown = rx1619_shutdown, + .id_table = rx1619_id, +}; + +static int __init rx1619_init(void) +{ + int ret; + uint32_t hw_version = 0; +#ifdef CONFIG_RX1619_REMOVE + return 0; +#endif + hw_version = get_hw_version_platform(); + printk("rx1619: hw version: %d\n", hw_version); + + printk("is_nvt_rx flag is:%d\n", is_nvt_rx); + if (!is_nvt_rx) + return 0; + + ret = i2c_add_driver(&rx1619_driver); + if (ret) + printk(KERN_ERR "rx1619 i2c driver init failed!\n"); + + return ret; +} + +static void __exit rx1619_exit(void) +{ + i2c_del_driver(&rx1619_driver); +} + +static int __init early_parse_oled_pmic_id(char *p) +{ + if (p) { + if (!strcmp(p, "0B") || !strcmp(p, "0C")) + is_nvt_rx = true; + } + + return 0; +} +early_param("androidboot.oled_pmic_id", early_parse_oled_pmic_id); + +late_initcall(rx1619_init); +module_exit(rx1619_exit); + +MODULE_AUTHOR("colin"); +MODULE_DESCRIPTION("NUVOLTA Wireless Power Charger Monitor driver"); +MODULE_LICENSE("GPL/BSD"); diff --git a/drivers/power/supply/nuvolta/rx1619.h b/drivers/power/supply/nuvolta/rx1619.h new file mode 100644 index 000000000000..8791019582fe --- /dev/null +++ b/drivers/power/supply/nuvolta/rx1619.h @@ -0,0 +1,2741 @@ +u8 chip_default_data[2] = { 0x47, 0x10 }; + +//J2 fw version 0x15 +u8 fw_data_boot[1016] = { + 0xff, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, + 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xaf, 0xfe, 0xff, 0xff, + 0xb7, 0xfe, 0xff, 0xff, 0xa7, 0xfe, 0xff, 0xff, 0x8f, 0xfe, 0xff, 0xff, + 0x87, 0xfe, 0xff, 0xff, 0x7f, 0xfe, 0xff, 0xff, 0x77, 0xfe, 0xff, 0xff, + 0x6f, 0xfe, 0xff, 0xff, 0x67, 0xfe, 0xff, 0xff, 0x5f, 0xfe, 0xff, 0xff, + 0x57, 0xfe, 0xff, 0xff, 0x4f, 0xfe, 0xff, 0xff, 0x47, 0xfe, 0xff, 0xff, + 0x9f, 0xfe, 0xff, 0xff, 0x97, 0xfe, 0xff, 0xff, 0x3f, 0xfe, 0xff, 0xff, + 0x37, 0xfe, 0xff, 0xff, 0x2f, 0xfe, 0xff, 0xff, 0x27, 0xfe, 0xff, 0xff, + 0x1f, 0xfe, 0xff, 0xff, 0x17, 0xfe, 0xff, 0xff, 0x0f, 0xfe, 0xff, 0xff, + 0x07, 0xfe, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xf7, 0xfd, 0xff, 0xff, + 0xef, 0xfd, 0xff, 0xff, 0xef, 0xfd, 0xff, 0xff, 0xef, 0xfd, 0xff, 0xff, + 0xef, 0xfd, 0xff, 0xff, 0xef, 0xfd, 0xff, 0xff, 0xef, 0xfd, 0xff, 0xff, + 0xef, 0xfd, 0xff, 0xff, 0x94, 0xef, 0xfc, 0x3f, 0xdf, 0x9b, 0xb4, 0xef, + 0xfd, 0x3f, 0xde, 0x9b, 0xb5, 0xef, 0x9f, 0x6d, 0xbc, 0x14, 0xdf, 0xff, + 0xf8, 0xf7, 0xfd, 0x15, 0xff, 0xb3, 0x9f, 0x6d, 0xf3, 0x87, 0xff, 0x1f, + 0x7e, 0xff, 0xfd, 0x15, 0xff, 0xfb, 0x9f, 0x6d, 0xf3, 0x87, 0xff, 0xfb, + 0xff, 0xfe, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xef, 0x6f, 0xff, 0xbf, + 0xff, 0x1f, 0xfb, 0xff, 0xff, 0x3f, 0xdf, 0xbf, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, + 0x9c, 0xeb, 0x9e, 0xeb, 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, + 0x9f, 0xeb, 0x9d, 0xeb, 0x9c, 0xeb, 0x9e, 0xeb, 0xc3, 0x87, 0xff, 0xff, + 0xc3, 0x87, 0xff, 0xff, 0xff, 0xcf, 0xc3, 0x87, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xb1, 0xaa, 0xe9, 0xe6, 0xdf, 0xb5, 0xcd, 0xea +}; + +u8 fw_data_tx[13304] = { + 0xff, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, + 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, + 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x93, 0xb2, 0xff, 0xff, + 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, + 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, + 0x9b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, + 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, + 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, + 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, + 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, + 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x63, 0x8b, 0xff, 0xff, + 0xff, 0x8a, 0xff, 0xff, 0x4f, 0x8b, 0xff, 0xff, 0x2b, 0x8b, 0xff, 0xff, + 0x23, 0x8b, 0xff, 0xff, 0xeb, 0x8a, 0xff, 0xff, 0xe3, 0x8a, 0xff, 0xff, + 0x1b, 0x8b, 0xff, 0xff, 0x13, 0x8b, 0xff, 0xff, 0xcb, 0x8a, 0xff, 0xff, + 0x9f, 0x8a, 0xff, 0xff, 0x97, 0x8a, 0xff, 0xff, 0x8f, 0x8a, 0xff, 0xff, + 0x3b, 0x8b, 0xff, 0xff, 0x33, 0x8b, 0xff, 0xff, 0x87, 0x8a, 0xff, 0xff, + 0x7f, 0x8a, 0xff, 0xff, 0x77, 0x8a, 0xff, 0xff, 0x5b, 0x8a, 0xff, 0xff, + 0x53, 0x8a, 0xff, 0xff, 0x4b, 0x8a, 0xff, 0xff, 0x43, 0x8a, 0xff, 0xff, + 0x3b, 0x8a, 0xff, 0xff, 0x33, 0x8a, 0xff, 0xff, 0x2b, 0x8a, 0xff, 0xff, + 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, + 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, + 0x23, 0x8a, 0xff, 0xff, 0x8e, 0xef, 0xfc, 0x3f, 0xdf, 0x9b, 0xae, 0xef, + 0xfd, 0x3f, 0xde, 0x9b, 0xcf, 0xef, 0x78, 0x90, 0x0f, 0xef, 0x2e, 0xef, + 0x4e, 0xef, 0x63, 0x9a, 0xf8, 0xf7, 0x7f, 0x6a, 0x7f, 0x48, 0xfc, 0xda, + 0xfc, 0xd8, 0x63, 0x9a, 0x04, 0xf0, 0x91, 0xef, 0xb1, 0xef, 0x71, 0x9f, + 0xbd, 0xb5, 0xbf, 0xc5, 0xf8, 0xf3, 0xff, 0xce, 0xdf, 0x4c, 0xfc, 0xdc, + 0xff, 0xd5, 0xbf, 0xc5, 0x03, 0xf4, 0xff, 0x1f, 0x0a, 0xe9, 0xff, 0xfb, + 0xff, 0xfe, 0xff, 0x7f, 0xff, 0xb3, 0xff, 0xff, 0x07, 0xfd, 0xff, 0xdf, + 0xff, 0xff, 0xff, 0xdf, 0xfb, 0xff, 0xff, 0xdf, 0x47, 0x82, 0xff, 0xff, + 0xfb, 0xff, 0xff, 0xdf, 0x7f, 0xfe, 0xff, 0xdf, 0xff, 0x1f, 0xa7, 0xec, + 0xff, 0x3f, 0xdf, 0xbf, 0xff, 0x1f, 0x89, 0xec, 0xff, 0x3f, 0xdf, 0xbf, + 0xff, 0x1f, 0xd1, 0xec, 0xff, 0x3f, 0xdf, 0xbf, 0xbf, 0xc6, 0xfc, 0xf7, + 0xff, 0x3f, 0xdf, 0xd3, 0xbf, 0xc7, 0xfd, 0xf7, 0xc3, 0x87, 0x3d, 0xeb, + 0xbc, 0x92, 0xba, 0x92, 0x1f, 0x38, 0x7f, 0xd7, 0xfc, 0xf3, 0xfd, 0x93, + 0xff, 0xdf, 0x1e, 0x38, 0x7f, 0xd7, 0xfc, 0xf3, 0xb9, 0x93, 0xff, 0xde, + 0xfe, 0xcd, 0x3c, 0x93, 0xfc, 0x3b, 0xbb, 0x83, 0x6f, 0x8f, 0xef, 0x8f, + 0x38, 0x93, 0xfc, 0x3b, 0xbb, 0x83, 0xff, 0xdb, 0x3c, 0x93, 0x2e, 0x8f, + 0xed, 0x92, 0xdf, 0xdb, 0x6f, 0x8f, 0xef, 0x8f, 0xbf, 0xc5, 0xf6, 0xf3, + 0xff, 0x3b, 0xdf, 0xb3, 0x32, 0x9f, 0xb3, 0x9b, 0xfd, 0xf3, 0x39, 0x9f, + 0x76, 0x9f, 0x06, 0xf0, 0xf4, 0x93, 0xb0, 0x93, 0xfa, 0x3b, 0xda, 0xb3, + 0xfa, 0xf3, 0xfd, 0x93, 0xff, 0xdf, 0xb9, 0x93, 0xff, 0xde, 0x7d, 0xeb, + 0xbf, 0xc6, 0xfc, 0xf7, 0xff, 0x3f, 0xdf, 0xd3, 0xbf, 0xc7, 0xfd, 0xf7, + 0xc3, 0x87, 0x3e, 0xeb, 0xfe, 0xcd, 0x3c, 0x93, 0xfc, 0x3b, 0xbb, 0x83, + 0x6f, 0x8f, 0xef, 0x8f, 0x38, 0x93, 0xfc, 0x3b, 0xbb, 0x83, 0xff, 0xdb, + 0x3c, 0x93, 0x2e, 0x8f, 0xed, 0x92, 0xdf, 0xdb, 0x6f, 0x8f, 0xef, 0x8f, + 0xbf, 0xc5, 0xf6, 0xf3, 0xff, 0x3b, 0xdf, 0xb3, 0x32, 0x9f, 0xb3, 0x9b, + 0xfd, 0xf3, 0x39, 0x9f, 0x76, 0x9f, 0x06, 0xf0, 0xf4, 0x93, 0xb0, 0x93, + 0x7e, 0xeb, 0xff, 0xff, 0xbf, 0xc6, 0xfc, 0xf7, 0xff, 0x3f, 0xdf, 0xd3, + 0xbf, 0xc7, 0xfd, 0xf7, 0xc3, 0x87, 0x7c, 0x93, 0xfd, 0x3b, 0xbc, 0x83, + 0xfe, 0xcd, 0x73, 0x8f, 0xf3, 0x8f, 0xff, 0xcc, 0xff, 0x3b, 0xdf, 0xb3, + 0x32, 0x9f, 0xb3, 0x9b, 0xfd, 0xf3, 0x39, 0x9f, 0x76, 0x9f, 0x06, 0xf0, + 0xf0, 0x93, 0xc3, 0x87, 0x2e, 0xeb, 0x61, 0xce, 0xc8, 0xbe, 0xfc, 0x92, + 0xff, 0x1f, 0x9d, 0xfe, 0x1f, 0x38, 0x7f, 0xd7, 0xfa, 0xf3, 0xec, 0x93, + 0xff, 0x1f, 0x59, 0xfe, 0x6e, 0xeb, 0x61, 0xce, 0xc8, 0xbe, 0xec, 0x93, + 0xff, 0x1f, 0x31, 0xff, 0xff, 0x1f, 0x61, 0xfe, 0x7f, 0xcc, 0x87, 0xbc, + 0xf3, 0xa7, 0x6e, 0xeb, 0x3b, 0xeb, 0xde, 0xeb, 0x7f, 0x6f, 0xfe, 0xca, + 0xeb, 0x9a, 0xba, 0xf7, 0x9f, 0x6e, 0x2b, 0x9b, 0x7b, 0xf7, 0xbb, 0xc3, + 0x69, 0xf3, 0xbb, 0xc4, 0x7f, 0xf3, 0xbd, 0xc4, 0xa5, 0xf3, 0xbd, 0xc3, + 0x83, 0xf3, 0x9c, 0x6f, 0x7d, 0x6f, 0x1d, 0x6e, 0x9f, 0x47, 0x82, 0xa3, + 0x1c, 0x38, 0x7f, 0xd7, 0x5c, 0x6e, 0x70, 0x92, 0x92, 0xf7, 0xc0, 0xc1, + 0xcf, 0xf3, 0xdf, 0xc4, 0x8e, 0xf7, 0xfe, 0xcc, 0x27, 0x8f, 0xff, 0xd4, + 0x3a, 0x3b, 0xb8, 0xbf, 0xb3, 0x96, 0xbf, 0xc2, 0xff, 0x3b, 0xfa, 0xfa, + 0xa3, 0x92, 0x9e, 0x6f, 0xde, 0x6e, 0xb1, 0x9b, 0xd8, 0xf3, 0xbf, 0xc4, + 0xb6, 0xf3, 0x3f, 0x67, 0x46, 0xa2, 0x1a, 0x38, 0x7f, 0xd7, 0xb6, 0xf7, + 0xff, 0xc9, 0x3e, 0x4d, 0x7d, 0x4d, 0x5c, 0x4d, 0x9c, 0xa2, 0xe7, 0xee, + 0x3f, 0x9b, 0xf6, 0xf3, 0x9d, 0x6d, 0x5e, 0xba, 0xdc, 0xa2, 0xbf, 0x9b, + 0xff, 0xd4, 0x03, 0xf4, 0x5c, 0x4d, 0x9d, 0x4d, 0xfc, 0xcc, 0x1a, 0x38, + 0x7f, 0xd7, 0x9f, 0x4d, 0xea, 0xf7, 0xf4, 0x93, 0xfe, 0xeb, 0x7b, 0xeb, + 0xe2, 0x9a, 0xc9, 0xf3, 0x9e, 0x6f, 0xde, 0x6e, 0xb1, 0x9b, 0xff, 0xca, + 0x24, 0xf4, 0x3f, 0x67, 0x47, 0xa2, 0x9e, 0x4d, 0x1a, 0x38, 0x7f, 0xd7, + 0xfc, 0xcc, 0x7d, 0x4d, 0x5c, 0x4d, 0x9f, 0x4d, 0x12, 0xf0, 0x9a, 0x1b, + 0xfe, 0xdf, 0x5e, 0xb2, 0xb3, 0x92, 0x9d, 0x6d, 0xff, 0xdc, 0xf4, 0x93, + 0x5c, 0x4d, 0x9d, 0x4d, 0xfe, 0xeb, 0x7b, 0xeb, 0xbd, 0xc3, 0x1e, 0xf4, + 0x9f, 0x4d, 0x3e, 0x6f, 0x3e, 0x4d, 0x9d, 0x6f, 0x9d, 0x4d, 0x3c, 0x6f, + 0x3c, 0x4d, 0x9e, 0x6f, 0xde, 0x6e, 0x3b, 0x97, 0x9e, 0x4d, 0xf4, 0x93, + 0x2b, 0xf8, 0x9f, 0x67, 0x4a, 0xa4, 0x1a, 0x38, 0x7f, 0xd7, 0x46, 0xf0, + 0xfe, 0xcc, 0x9e, 0x4d, 0xff, 0xcc, 0x4a, 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0x7c, 0x9e, 0x7f, 0xfd, 0x7f, 0xff, 0x47, 0xf6, 0xef, 0x00, 0x1c, + 0x5a, 0x13, 0x00, 0x1c, 0x06, 0x06, 0x00, 0x1c, 0xb6, 0x08, 0x00, 0x1c, + 0x3e, 0x0d, 0x00, 0x1c, 0x32, 0x07, 0xff, 0xcf, 0xfe, 0xeb, 0x6f, 0xeb, + 0x89, 0xfe, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xdf, 0x87, 0x82, 0xff, 0xff, + 0xaf, 0xaa, 0xff, 0xff, 0xf7, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, + 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, + 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, + 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, + 0xe5, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, + 0x97, 0xaa, 0xff, 0xff, 0xa3, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, + 0xd3, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, 0x97, 0xaa, 0xff, 0xff, + 0xc1, 0xaa, 0xff, 0xff, 0xcf, 0xce, 0xcd, 0xcc, 0xcb, 0xca, 0xc9, 0xc8, + 0xc7, 0xc6, 0xbe, 0xbd, 0xbc, 0xbb, 0xba, 0xb9, 0x9f, 0x96, 0xff, 0xff, + 0x9f, 0x96, 0xff, 0xff, 0x05, 0x99, 0xff, 0xff, 0x9f, 0x96, 0xff, 0xff, + 0xb3, 0x98, 0xff, 0xff, 0x5b, 0x97, 0xff, 0xff, 0x9f, 0x96, 0xff, 0xff, + 0x0f, 0x97, 0xff, 0xff, 0x9f, 0x96, 0xff, 0xff, 0xd9, 0x96, 0xff, 0xff, + 0x9f, 0x96, 0xff, 0xff, 0x45, 0x98, 0xff, 0xff, 0x9f, 0x96, 0xff, 0xff, + 0xcd, 0x96, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0x3c, 0xb8, + 0xff, 0xff, 0xff, 0xc0, 0xd3, 0xdf, 0x8f, 0x96, 0x9b, 0xc5, 0xdf, 0xda, + 0x9b, 0xd7, 0x9a, 0x8d, 0x8d, 0xc5, 0xdf, 0xda, 0x9b, 0xd3, 0xdf, 0x96, + 0xc5, 0xda, 0x9b, 0xd3, 0xdf, 0x9b, 0xc5, 0xda, 0x9b, 0xd6, 0xff, 0xff, + 0xdf, 0x9a, 0x92, 0xc5, 0xda, 0x9b, 0xd3, 0xdf, 0x9c, 0x92, 0xc5, 0xdf, + 0xda, 0x9b, 0xd3, 0xdf, 0x99, 0x8d, 0x9a, 0x8e, 0xc5, 0xda, 0x9b, 0xd3, + 0xdf, 0x9b, 0x8a, 0x8b, 0x86, 0xdf, 0xda, 0x9b, 0xff, 0xff, 0xff, 0xff, + 0xdf, 0x96, 0xc5, 0xdf, 0xda, 0x9b, 0xdf, 0x92, 0xbe, 0xff, 0xff, 0xff, + 0xf2, 0xf5, 0xdf, 0x8d, 0x87, 0xc5, 0xda, 0x9b, 0xd3, 0xdf, 0x8b, 0x87, + 0xc5, 0xda, 0x9b, 0xd3, 0xdf, 0x96, 0xc5, 0xda, 0x9b, 0xd3, 0xdf, 0x93, + 0x90, 0x8c, 0x8c, 0xc5, 0xda, 0x9b, 0xff, 0xff, 0xf2, 0xf5, 0xdf, 0x9c, + 0x9e, 0x93, 0x96, 0xdf, 0x8d, 0x9a, 0x8c, 0xdf, 0x96, 0x8c, 0xdf, 0xda, + 0x9b, 0xff, 0xff, 0xff, 0xf2, 0xf5, 0xdf, 0x91, 0x88, 0x94, 0xdf, 0x8c, + 0x8b, 0x9e, 0x8b, 0x9a, 0xdf, 0x8b, 0x90, 0xdf, 0xda, 0x9b, 0xff, 0xff, + 0xf2, 0xf5, 0xff, 0xff, 0xdf, 0xda, 0xcf, 0xcd, 0x87, 0xff, 0xff, 0xff, + 0xdf, 0x9c, 0x97, 0x94, 0x8c, 0x8a, 0x92, 0xdf, 0x9a, 0x8d, 0x8d, 0xd1, + 0xd1, 0xd1, 0xff, 0xff, 0xdf, 0x9b, 0x92, 0xd2, 0xc1, 0xda, 0x9b, 0xff, + 0xf2, 0xf5, 0xdf, 0x97, 0x86, 0x8c, 0xd4, 0xff, 0xf2, 0xf5, 0xdf, 0x97, + 0x86, 0x8c, 0xd2, 0xff, 0xf2, 0xf5, 0xdf, 0x99, 0x8d, 0x9a, 0x8e, 0xd4, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0xf5, 0xdf, 0x8f, 0x90, 0x93, 0x9a, 0xd4, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0xf5, 0xdf, 0x8f, 0x90, 0x93, 0x9a, 0xd2, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0xf5, 0xdf, 0x9b, 0x92, 0xdf, 0x9c, 0x97, + 0x9e, 0x91, 0x98, 0x9a, 0x9b, 0xd1, 0xdf, 0xda, 0x9b, 0xff, 0xff, 0xff, + 0xf2, 0xf5, 0xdf, 0x8f, 0x9e, 0x9c, 0x94, 0x9a, 0x8b, 0xdf, 0x8b, 0x96, + 0x92, 0x9a, 0x90, 0x8a, 0x8b, 0xd1, 0xd1, 0xd1, 0xff, 0xff, 0xff, 0xff, + 0xf2, 0xf5, 0xdf, 0x8d, 0x8f, 0x8f, 0xdf, 0x8b, 0x96, 0x92, 0x9a, 0x90, + 0x8a, 0x8b, 0xff, 0xff, 0xf2, 0xf5, 0xdf, 0x99, 0x8d, 0x9a, 0x8e, 0xd2, + 0xff, 0xff, 0xff, 0xff, 0xf2, 0xf5, 0xdf, 0x8f, 0x97, 0x86, 0xdf, 0x8b, + 0x9e, 0x8c, 0x94, 0xdf, 0x96, 0x9b, 0xdf, 0x96, 0x8c, 0xdf, 0xda, 0x9b, + 0xff, 0xff, 0xff, 0xff, 0x8b, 0x87, 0xa0, 0x92, 0x90, 0x9b, 0x9a, 0xc2, + 0xdf, 0xda, 0x9b, 0xd3, 0xdf, 0x96, 0x96, 0x91, 0xa0, 0x92, 0x9e, 0x87, + 0xc2, 0xdf, 0xda, 0x9b, 0xd3, 0xdf, 0x99, 0x90, 0x9b, 0xa0, 0x90, 0x99, + 0x99, 0x8c, 0x9a, 0x8b, 0xc2, 0xdf, 0xda, 0x9b, 0xd3, 0xdf, 0x8f, 0x96, + 0x91, 0x98, 0xa0, 0x90, 0x99, 0x99, 0x8c, 0x9a, 0x8b, 0xc2, 0xdf, 0xda, + 0x9b, 0xdf, 0xf2, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xb1, 0xaa, 0xe9, 0xe6, 0xdf, 0xb5, 0xcd, 0xea +}; + +u8 fw_data_rx[18424] = { + 0xff, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, + 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0xff, 0xb9, 0xff, 0xff, + 0x67, 0xc1, 0xff, 0xff, 0x8b, 0xb9, 0xff, 0xff, 0x7b, 0xb9, 0xff, 0xff, + 0x73, 0xb9, 0xff, 0xff, 0xf3, 0xc6, 0xff, 0xff, 0x67, 0xc0, 0xff, 0xff, + 0x6b, 0xb9, 0xff, 0xff, 0x63, 0xb9, 0xff, 0xff, 0x4f, 0xb9, 0xff, 0xff, + 0x3b, 0xb9, 0xff, 0xff, 0x33, 0xb9, 0xff, 0xff, 0x2b, 0xb9, 0xff, 0xff, + 0xeb, 0xc6, 0xff, 0xff, 0x83, 0xb9, 0xff, 0xff, 0x23, 0xb9, 0xff, 0xff, + 0x1b, 0xb9, 0xff, 0xff, 0x13, 0xb9, 0xff, 0xff, 0x0b, 0xb9, 0xff, 0xff, + 0x03, 0xb9, 0xff, 0xff, 0xef, 0xb8, 0xff, 0xff, 0xe7, 0xb8, 0xff, 0xff, + 0xdf, 0xb8, 0xff, 0xff, 0xd7, 0xb8, 0xff, 0xff, 0xcf, 0xb8, 0xff, 0xff, + 0xc7, 0xb8, 0xff, 0xff, 0xc7, 0xb8, 0xff, 0xff, 0xc7, 0xb8, 0xff, 0xff, + 0xc7, 0xb8, 0xff, 0xff, 0xc7, 0xb8, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb1, 0xaa, 0xe9, 0xe6, + 0xdf, 0xb5, 0xcd, 0xea +}; diff --git a/drivers/power/supply/nuvolta/rx1619_trim.c b/drivers/power/supply/nuvolta/rx1619_trim.c new file mode 100644 index 000000000000..eeb652956e3f --- /dev/null +++ b/drivers/power/supply/nuvolta/rx1619_trim.c @@ -0,0 +1,170 @@ +/** + * @file rx1619_1.c + * @author + * @date 2019-04-09 + * + * @brief + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include + +#define rx1619_1_DRIVER_NAME "rx1619_trim" + +static struct rx1619_1_chg *g_chip; + +struct rx1619_1_chg { + char *name; + struct i2c_client *client; + struct device *dev; + struct regmap *regmap; +}; + +/* +static int rx1619_1_read(struct rx1619_1_chg *chip, u8 *val, u16 addr) +{ + unsigned int temp; + int rc; + + rc = regmap_read(chip->regmap, addr, &temp); + if (rc >= 0) { + *val = (u8)temp; + //dev_err(chip->dev, "[rx1619_1] [%s] [0x%04x] = [0x%x] \n", __func__, addr, *val); + } + + return rc; +}*/ + +static int rx1619_1_write(struct rx1619_1_chg *chip, u8 val, u16 addr) +{ + int rc = 0; + + rc = regmap_write(chip->regmap, addr, val); + + return rc; +} + +void rx1619_1_trim(void) +{ + printk("--------------rx1619_1_trim++\n"); + + /************prepare_for_mtp_write************/ + rx1619_1_write(g_chip, 0x69, 0x2017); + rx1619_1_write(g_chip, 0x96, 0x2017); + rx1619_1_write(g_chip, 0x66, 0x2017); + rx1619_1_write(g_chip, 0x99, 0x2017); + rx1619_1_write(g_chip, 0xff, 0x2018); + rx1619_1_write(g_chip, 0xff, 0x2019); + rx1619_1_write(g_chip, 0x5a, 0x0001); + rx1619_1_write(g_chip, 0xa5, 0x0003); + /************prepare_for_mtp_write************/ + + printk("--------------rx1619_1_trim--\n"); +} + +// first step: define regmap_config +static const struct regmap_config rx1619_1_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0xFFFF, +}; + +static int rx1619_1_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct rx1619_1_chg *chip; + + chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) { + dev_err(&client->dev, + "i2c allocated device info data failed!\n"); + return -ENOMEM; + } + + chip->regmap = regmap_init_i2c(client, &rx1619_1_regmap_config); + if (!chip->regmap) { + dev_err(&client->dev, "parent regmap is missing\n"); + return -EINVAL; + } + + chip->client = client; + chip->dev = &client->dev; + + device_init_wakeup(&client->dev, true); + i2c_set_clientdata(client, chip); + + //rx1619_1_dump_reg(); + g_chip = chip; + + dev_err(chip->dev, "[rx1619_1] [%s] success! \n", __func__); + + return 0; +} + +static int rx1619_1_remove(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id rx1619_1_id[] = { + { rx1619_1_DRIVER_NAME, 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, rx1619_1_id); + +static struct of_device_id rx1619_1_match_table[] = { + { + .compatible = "nuvolta,wl_rx1619_trim", + }, + {} +}; + +static struct i2c_driver rx1619_1_driver = { + .driver = { + .name = rx1619_1_DRIVER_NAME, + .of_match_table = rx1619_1_match_table, + }, + .probe = rx1619_1_probe, + .remove = rx1619_1_remove, + .id_table = rx1619_1_id, +}; + +static int __init rx1619_1_init(void) +{ + int ret; + + ret = i2c_add_driver(&rx1619_1_driver); + if (ret) + printk(KERN_ERR "rx1619_1 i2c driver init failed!\n"); + + return ret; +} + +static void __exit rx1619_1_exit(void) +{ + i2c_del_driver(&rx1619_1_driver); +} + +module_init(rx1619_1_init); +module_exit(rx1619_1_exit); + +MODULE_AUTHOR("colin"); +MODULE_DESCRIPTION("NUVOLTA Wireless Power Charger Monitor driver"); +MODULE_LICENSE("GPL/BSD"); diff --git a/drivers/power/supply/renesas/Kconfig b/drivers/power/supply/renesas/Kconfig new file mode 100644 index 000000000000..b28587484baa --- /dev/null +++ b/drivers/power/supply/renesas/Kconfig @@ -0,0 +1,25 @@ +menu "Renesas Electronics Corporation Charger support" + +config IDT_P9220 + tristate "idtp9220 wireless Charger" + depends on I2C + help + Say Y to include support for idtp9220 wireless Charger. + idtp9220 is a wireless battery charger. + The driver supports charger enable/disable. + The driver reports the charger status via the power supply framework. + The driver controls idtp9220 via I2C and + supports device-tree interface. + +config IDT_P9418 + tristate "idtp9418 wireless Charger" + depends on I2C + help + Say Y to include support for idtp9418 wireless Charger. + idtp9418 is a wireless battery charger. + The driver supports charger enable/disable. + The driver reports the charger status via the power supply framework. + The driver controls idtp9418 via I2C and + supports device-tree interface. + +endmenu diff --git a/drivers/power/supply/renesas/Makefile b/drivers/power/supply/renesas/Makefile new file mode 100644 index 000000000000..970140c2cb8b --- /dev/null +++ b/drivers/power/supply/renesas/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_IDT_P9220) += idtp9220.o +obj-$(CONFIG_IDT_P9418) += idtp9418.o diff --git a/drivers/power/supply/renesas/idtp9220.c b/drivers/power/supply/renesas/idtp9220.c new file mode 100644 index 000000000000..d6285209461b --- /dev/null +++ b/drivers/power/supply/renesas/idtp9220.c @@ -0,0 +1,2223 @@ +/** + * Copyright “Copyright (C) 2018 XiaoMi, Inc + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +/*add for sdm845 request*/ +#include +#include +#include +#include +#include +#include +#include +#include + +/* +#ifdef CONFIG_DRM +#include +#endif +*/ + +static struct idtp9220_device_info *g_di; + +struct idtp9220_access_func { + int (*read)(struct idtp9220_device_info *di, u16 reg, u8 *val); + int (*write)(struct idtp9220_device_info *di, u16 reg, u8 val); + int (*read_buf)(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size); + int (*write_buf)(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size); +}; + +struct idtp9220_dt_props { + unsigned int irq_gpio; + unsigned int enable_gpio; + unsigned int wpc_det_gpio; +}; + +struct idtp9220_device_info { + int chip_enable; + char *name; + struct device *dev; + struct idtp9220_access_func bus; + struct regmap *regmap; + struct idtp9220_dt_props dt_props; + int irq; + int wpc_irq; + struct delayed_work irq_work; + struct delayed_work wpc_det_work; + struct pinctrl *idt_pinctrl; + struct pinctrl_state *idt_gpio_active; + struct pinctrl_state *idt_gpio_suspend; + struct power_supply *usb_psy; + struct power_supply *dc_psy; + struct power_supply *batt_psy; + struct power_supply *idtp_psy; + struct power_supply *wireless_psy; + struct mutex read_lock; + struct mutex write_lock; + struct delayed_work chg_monitor_work; + struct delayed_work chg_detect_work; + struct delayed_work bpp_connect_load_work; + struct delayed_work epp_connect_load_work; + struct delayed_work cmd_check_work; + struct delayed_work vout_regulator_work; + struct delayed_work rx_vout_work; + struct delayed_work dc_check_work; + struct delayed_work fast_operate_work; + struct delayed_work mophie_tx_work; + struct delayed_work bpp_e5_tx_work; + struct delayed_work qc2_f1_tx_work; + struct delayed_work qc3_epp_work; + + bool screen_on; + int tx_charger_type; + int status; + int count_5v; + int count_9v; + int count_12v; + int count_15v; + int exchange; + int epp_exchange; + int dcin_present; + int epp; + int vbuck; + int power_off_mode; + int power_max; + u8 header; + u8 cmd; + int is_compatible_hwid; + int last_vin; + int last_vbuck; + int is_car_tx; + int last_icl; + int power_good_flag; + + /*idt9220 charging info*/ + int vout; + int iout; + int f; + int vrect; + int ss; + int is_vin_limit; + int is_epp_qc3; + /* bpp e5_tx info*/ + int last_bpp_icl; + int last_bpp_vout; + /* qc2+f1_tx info*/ + int is_f1_tx; + int bpp_vout_rise; + int last_qc2_vout; + int last_qc2_icl; + /* qc3_epp+f1_tx info*/ + int last_qc3_vout; + int last_qc3_icl; +}; + +void idtp922x_request_adapter(struct idtp9220_device_info *di); +static void idtp9220_set_charging_param(struct idtp9220_device_info *di); + +/*static int idt_signal_strength = 0; +module_param_named(ss, idt_signal_strength, int, 0600); +*/ + +static int idt_signal_range = 2; +module_param_named(signal_range, idt_signal_range, int, 0644); + +static int idtp9220_get_property_names(struct idtp9220_device_info *di) +{ + di->batt_psy = power_supply_get_by_name("battery"); + if (!di->batt_psy) { + dev_err(di->dev, "[idt] no batt_psy,return\n"); + return -EINVAL; + } + di->dc_psy = power_supply_get_by_name("dc"); + if (!di->dc_psy) { + dev_err(di->dev, "[idt] no dc_psy,return\n"); + return -EINVAL; + } + di->usb_psy = power_supply_get_by_name("usb"); + if (!di->usb_psy) { + dev_err(di->dev, "[idt] no usb_psy,return\n"); + return -EINVAL; + } + di->wireless_psy = power_supply_get_by_name("wireless"); + if (!di->wireless_psy) { + dev_err(di->dev, "[idt] no wireless_psy,return\n"); + return -EINVAL; + } + return 0; +} + +int idtp9220_read(struct idtp9220_device_info *di, u16 reg, u8 *val) +{ + unsigned int temp; + int rc; + + mutex_lock(&di->read_lock); + rc = regmap_read(di->regmap, reg, &temp); + if (rc >= 0) + *val = (u8)temp; + + mutex_unlock(&di->read_lock); + return rc; +} + +int idtp9220_write(struct idtp9220_device_info *di, u16 reg, u8 val) +{ + int rc = 0; + + mutex_lock(&di->write_lock); + rc = regmap_write(di->regmap, reg, val); + if (rc < 0) + dev_err(di->dev, "[idt] idtp9220 write error: %d\n", rc); + + mutex_unlock(&di->write_lock); + return rc; +} + +int idtp9220_read_buffer(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size) +{ + int rc = 0; + + while (size--) { + rc = di->bus.read(di, reg++, buf++); + if (rc < 0) { + dev_err(di->dev, "[idt] write error: %d\n", rc); + return rc; + } + } + + return rc; +} + +int idtp9220_write_buffer(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size) +{ + int rc = 0; + + while (size--) { + rc = di->bus.write(di, reg++, *buf++); + if (rc < 0) { + dev_err(di->dev, "[idt] write error: %d\n", rc); + return rc; + } + } + + return rc; +} + +u32 ExtractPacketSize(u8 hdr) +{ + if (hdr < 0x20) + return 1; + if (hdr < 0x80) + return (2 + ((hdr - 0x20) >> 4)); + if (hdr < 0xe0) + return (8 + ((hdr - 0x80) >> 3)); + return (20 + ((hdr - 0xe0) >> 2)); +} + +void idtp922x_clrInt(struct idtp9220_device_info *di, u8 *buf, u32 size) +{ + di->bus.write_buf(di, REG_SSINTCLR, buf, size); + di->bus.write(di, REG_SSCMND, CLRINT); +} + +void idtp922x_sendPkt(struct idtp9220_device_info *di, ProPkt_Type *pkt) +{ + u32 size = ExtractPacketSize(pkt->header) + 1; + di->bus.write_buf(di, REG_PROPPKT, (u8 *)pkt, + size); // write data into proprietary packet buffer + di->bus.write(di, REG_SSCMND, SENDPROPP); // send proprietary packet + + dev_info(di->dev, "pkt header: 0x%x and cmd: 0x%x\n", pkt->header, + pkt->cmd); + di->header = pkt->header; + di->cmd = pkt->cmd; +} + +void idtp922x_receivePkt(struct idtp9220_device_info *di, u8 *buf) +{ + u8 header; + int rc; + u32 size; + + di->bus.read(di, REG_BCHEADER, &header); + size = ExtractPacketSize(header) + 1; + rc = di->bus.read_buf(di, REG_BCDATA, buf, size); + if (rc < 0) + dev_err(di->dev, "[idt] read Tx data error: %d\n", rc); +} + +void idtp922x_set_adap_vol(struct idtp9220_device_info *di, u16 mv) +{ + dev_info(di->dev, "set adapter vol to %d\n", mv); + di->bus.write(di, REG_FC_VOLTAGE_L, mv & 0xff); + di->bus.write(di, REG_FC_VOLTAGE_H, (mv >> 8) & 0xff); + di->bus.write(di, REG_SSCMND, VSWITCH); +} + +void idtp922x_set_pmi_icl(struct idtp9220_device_info *di, int mA) +{ + union power_supply_propval val = { + 0, + }; + int rc; + + rc = idtp9220_get_property_names(di); + val.intval = mA; + power_supply_set_property(di->dc_psy, POWER_SUPPLY_PROP_CURRENT_MAX, + &val); +} + +/* Adapter Type */ +/* Adapter_list = {0x00:'ADAPTER_UNKNOWN', */ +/* 0x01:'SDP 500mA', */ +/* 0x02:'CDP 1.1A', */ +/* 0x03:'DCP 1.5A', */ +/* 0x05:'QC2.0', */ +/* 0x06:'QC3.0', */ +/* 0x07:'PD',} */ +void idtp922x_request_adapter(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = BC_ADAPTER_TYPE; + + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_request_uuid(struct idtp9220_device_info *di, int is_epp) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + if (is_epp) + pkt.cmd = BC_TX_HWID; + else + pkt.cmd = BC_TX_COMPATIBLE_HWID; + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_get_tx_vin(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = BC_READ_Vin; + + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_retry_cmd(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = di->header; + pkt.cmd = di->cmd; + + idtp922x_sendPkt(di, &pkt); +} + +static void idtp9220_int_enable(struct idtp9220_device_info *di) +{ + u8 int_val; + di->bus.read(di, REG_INTR_EN_L, &int_val); + di->bus.write(di, REG_INTR_EN_L, (int_val | OVER_EVENT_OCCUR)); + dev_info(di->dev, "[idtp9220]: int enabled status 0x%x\n", + (int_val | OVER_EVENT_OCCUR)); +} + +static int idtp9220_get_vout_regulator(struct idtp9220_device_info *di) +{ + u8 vout_l, vout_h; + u16 vout; + + if (!di) + return 0; + + di->bus.read(di, REG_REGULATOR_L, &vout_l); + di->bus.read(di, REG_REGULATOR_H, &vout_h); + vout = vout_l | ((vout_h & 0xff) << 8); + dev_info(di->dev, "vout regulator get vol: %d\n", vout); + + return vout; +} + +void idtp9220_set_toggle_mode(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = BC_TX_TOGGLE; + idtp922x_sendPkt(di, &pkt); +} + +void idtp9220_retry_id_auth(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY38; + pkt.cmd = BC_RX_ID_AUTH; + + pkt.data[0] = 0x02; + pkt.data[1] = 0xbb; + + idtp922x_sendPkt(di, &pkt); +} + +static int idtp9220_set_vout_regulator(struct idtp9220_device_info *di, int mv) +{ + u8 vout_l, vout_h; + u16 vout; + + if (!di) + return 0; + vout_l = mv & 0xff; + vout_h = mv >> 8; + + dev_info(di->dev, "vout regulator vout_l: 0x%x and vout_h: 0x%x\n", + vout_l, vout_h); + di->bus.write(di, REG_REGULATOR_L, vout_l); + di->bus.write(di, REG_REGULATOR_H, vout_h); + + vout = vout_l | ((vout_h & 0xff) << 8); + dev_info(di->dev, "vout regulator set vol: %d\n", vout); + + return vout; +} + +static int idtp9220_get_vbuck(struct idtp9220_device_info *di) +{ + u8 vbuck_l, vbuck_h; + u16 vbuck_ret; + + if (!di) + return 0; + + di->bus.read(di, 0x08, &vbuck_l); + di->bus.read(di, 0x09, &vbuck_h); + vbuck_ret = vbuck_l | (vbuck_h << 8); + + return vbuck_ret; +} + +static int idtp9220_get_vout(struct idtp9220_device_info *di) +{ + u8 vout_l, vout_h; + + if (!di) + return 0; + + di->bus.read(di, REG_ADC_VOUT_L, &vout_l); + di->bus.read(di, REG_ADC_VOUT_H, &vout_h); + di->vout = vout_l | ((vout_h & 0xf) << 8); + di->vout = di->vout * 10 * 21 * 1000 / 40950 + + ADJUST_METE_MV; //vout = val/4095*10*2.1 + + return di->vout; +} + +static void idtp9220_set_vout(struct idtp9220_device_info *di, int mv) +{ + u8 val; + if (!di) + return; + val = (mv - 3500) / 100; + di->bus.write(di, REG_VOUT_SET, val); + dev_info(di->dev, "[idtp9220]: set vout voltage is 0x%x\n", val); +} + +static void idtp9220_set_reset(struct idtp9220_device_info *di) +{ + if (!di) + return; + di->bus.write(di, REG_RX_RESET, 0x01); + dev_info(di->dev, "[idtp9220]: set RX reset\n"); +} +extern char *saved_command_line; + +static int get_cmdline(struct idtp9220_device_info *di) +{ + if (strnstr(saved_command_line, + "androidboot.mode=", strlen(saved_command_line))) { + di->power_off_mode = 1; + dev_info(di->dev, "[idtp9220]: enter power off charging app\n"); + } else { + di->power_off_mode = 0; + dev_info(di->dev, "[idtp9220]: enter normal boot mode\n"); + } + return 1; +} + +static int idtp9220_get_iout(struct idtp9220_device_info *di) +{ + u8 cout_l, cout_h; + + if (!di) + return 0; + + di->bus.read(di, REG_RX_LOUT_L, &cout_l); + di->bus.read(di, REG_RX_LOUT_H, &cout_h); + di->iout = cout_l | (cout_h << 8); + + return di->iout; +} + +static int idtp9220_get_power_profile(struct idtp9220_device_info *di) +{ + u8 mode; + int ret; + + di->bus.read(di, REG_WPC_MODE, &mode); + ret = mode & BIT(3); + dev_info(di->dev, "tx is epp ? ret is 0x%x\n", mode); + + return ret; +} + +static int idtp9220_get_freq(struct idtp9220_device_info *di) +{ + u8 data_list[2]; + + di->bus.read_buf(di, REG_FREQ_ADDR, data_list, 2); + di->f = 64 * HSCLK / (data_list[0] | (data_list[1] << 8)) / 10; + + return di->f; +} + +static int idtp9220_get_vrect(struct idtp9220_device_info *di) +{ + u8 data_list[2]; + + di->bus.read_buf(di, REG_ADC_VRECT, data_list, 2); + di->vrect = data_list[0] | ((data_list[1] & 0xf) << 8); + di->vrect = + di->vrect * 10 * 21 * 1000 / 40950; //vrect = val/4095*10*2.1 + + return di->vrect; +} + +static int idtp9220_get_power_max(struct idtp9220_device_info *di) +{ + int power_max; + u8 val; + + di->bus.read(di, REG_POWER_MAX, &val); + power_max = (val / 2) * 1000; + dev_info(di->dev, "rx power max is %dmW\n", power_max); + + return power_max; +} + +static void idtp9220_send_device_auth(struct idtp9220_device_info *di) +{ + di->bus.write(di, REG_SSCMND, SEND_DEVICE_AUTH); +} + +static ssize_t chip_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 chip_id_l, chip_id_h, chip_rev, cust_id, status, vset; + u8 fw_otp_ver[4], fw_app_ver[4]; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + di->bus.read(di, REG_STATUS_L, &status); + di->bus.read(di, REG_VOUT_SET, &vset); + + di->bus.read(di, REG_CHIP_ID_L, &chip_id_l); + di->bus.read(di, REG_CHIP_ID_H, &chip_id_h); + di->bus.read(di, REG_CHIP_REV, &chip_rev); + chip_rev = chip_rev >> 4; + di->bus.read(di, REG_CTM_ID, &cust_id); + di->bus.read_buf(di, REG_OTPFWVER_ADDR, fw_otp_ver, 4); + di->bus.read_buf(di, REG_EPRFWVER_ADDR, fw_app_ver, 4); + + return sprintf( + buf, + "chip_id_l:%02x\nchip_id_h:%02x\nchip_rev:%02x\ncust_id:%02x status:%02x vset:%02x\n otp_ver:%x.%x.%x.%x\n app_ver:%x.%x.%x.%x\n", + chip_id_l, chip_id_h, chip_rev, cust_id, status, vset, + fw_otp_ver[0], fw_otp_ver[1], fw_otp_ver[2], fw_otp_ver[3], + fw_app_ver[0], fw_app_ver[1], fw_app_ver[2], fw_app_ver[3]); +} + +/* voltage limit attrs */ +static ssize_t chip_vout_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int vout; + + vout = idtp9220_get_vout(di); + return sprintf(buf, "Vout ADC Value: %dMV\n", vout); +} + +static ssize_t chip_vout_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int index; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + index = (int)simple_strtoul(buf, NULL, 16); + /* + if ((index < VOUT_VAL_3500_MV) || (index > VOUT_VAL_5000_MV)) { + dev_err(di->dev, "Store Val %s is invalid!\n", buf); + return count; + } +*/ + + idtp9220_set_vout(di, index); + + return count; +} + +static ssize_t vout_regulator_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int vout; + + vout = idtp9220_get_vout_regulator(di); + + return sprintf(buf, "Vout ADC Value: %dMV\n", vout); +} + +#define VOUT_MIN_4900_MV 4900 +#define VOUT_MAX_10000_MV 10000 +static ssize_t vout_regulator_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int vout; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + vout = (int)simple_strtoul(buf, NULL, 10); + if ((vout <= VOUT_MIN_4900_MV) || (vout > VOUT_MAX_10000_MV)) { + dev_err(di->dev, "Store Val %s : %ld is invalid!\n", buf, vout); + return count; + } + idtp9220_set_vout_regulator(di, vout); + + return count; +} + +/* current attrs */ +static ssize_t chip_iout_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int cout; + + cout = idtp9220_get_iout(di); + + return sprintf(buf, "Output Current: %dMA\n", cout); +} + +static ssize_t chip_iout_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int index; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + index = (int)simple_strtoul(buf, NULL, 10); + + if ((index < CURR_VAL_100_MA) || (index > CURR_VAL_1300_MA)) { + dev_err(di->dev, "Store Val %s is invalid", buf); + return count; + } + + di->bus.write(di, REG_ILIM_SET, index); + + return count; +} + +static ssize_t chip_freq_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int f; + + f = idtp9220_get_freq(di); + + return sprintf(buf, "Output Current: %dkHz\n", f); +} + +static void idtp9220_charging_info(struct idtp9220_device_info *di) +{ + int vbuck_ret = 0; + if (!di) + return; + + idtp9220_get_vout(di); + idtp9220_get_iout(di); + idtp9220_get_freq(di); + idtp9220_get_vrect(di); + vbuck_ret = idtp9220_get_vbuck(di); + + dev_info( + di->dev, + "%s:Vout:%dmV,Iout:%dmA,Freq:%dKHz,Vrect:%dmV,SS:%d, Vbuck:%d\n", + __func__, di->vout, di->iout, di->f, di->vrect, di->ss, + vbuck_ret); +} + +/* chip enable attrs */ +static ssize_t chip_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + if (gpio_is_valid(di->dt_props.enable_gpio)) + ret = gpio_get_value(di->dt_props.enable_gpio); + else { + dev_err(di->dev, "%s: sleep gpio not provided\n", __func__); + ret = -1; + } + + dev_info(di->dev, "chip enable gpio: %d\n", ret); + + return sprintf(buf, "Chip enable: %d\n", !ret); +} + +static int idtp9220_set_present(struct idtp9220_device_info *di, int enable) +{ + int ret = 0; + + dev_info(di->dev, "[idtp] dc plug %s\n", enable ? "in" : "out"); + if (enable) { + di->dcin_present = true; + di->ss = 1; + } else { + schedule_delayed_work(&di->fast_operate_work, + msecs_to_jiffies(200)); + di->status = NORMAL_MODE; + di->count_9v = 0; + di->count_5v = 0; + di->count_12v = 0; + di->count_15v = 0; + di->exchange = 0; + di->epp_exchange = 0; + di->dcin_present = false; + idt_signal_range = 2; + di->ss = 2; + di->vbuck = 0; + di->epp = 0; + di->last_vin = 0; + di->last_icl = 0; + di->last_vbuck = 0; + di->is_car_tx = 0; + di->power_off_mode = 0; + di->is_epp_qc3 = 0; + di->is_vin_limit = 0; + di->bpp_vout_rise = 0; + di->is_f1_tx = 0; + di->last_bpp_vout = 0; + di->last_bpp_icl = 0; + di->last_qc2_vout = 0; + di->last_qc2_icl = 0; + di->last_qc3_vout = 0; + di->last_qc3_icl = 0; + di->tx_charger_type = ADAPTER_NONE; + cancel_delayed_work(&di->chg_monitor_work); + cancel_delayed_work(&di->cmd_check_work); + } + + return ret; +} + +static int idtp9220_set_enable_mode(struct idtp9220_device_info *di, int enable) +{ + int ret = 0; + + if (gpio_is_valid(di->dt_props.enable_gpio)) { + ret = gpio_request(di->dt_props.enable_gpio, "idt-enable-gpio"); + if (ret) { + dev_err(di->dev, + "%s: unable to request idt enable gpio [%d]\n", + __func__, di->dt_props.enable_gpio); + } + + ret = gpio_direction_output(di->dt_props.enable_gpio, !enable); + if (ret) { + dev_err(di->dev, + "%s: cannot set direction for idt enable gpio [%d]\n", + __func__, di->dt_props.enable_gpio); + } + gpio_free(di->dt_props.enable_gpio); + } + + return ret; +} + +static ssize_t chip_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int ret, enable; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + ret = (int)simple_strtoul(buf, NULL, 10); + enable = !!ret; + + idtp9220_set_enable_mode(di, enable); + + return count; +} + +static DEVICE_ATTR(chip_enable, S_IWUSR | S_IRUGO, chip_enable_show, + chip_enable_store); +static DEVICE_ATTR(chip_version, S_IRUGO, chip_version_show, NULL); +static DEVICE_ATTR(chip_vout, S_IWUSR | S_IRUGO, chip_vout_show, + chip_vout_store); +static DEVICE_ATTR(chip_iout, S_IWUSR | S_IRUGO, chip_iout_show, + chip_iout_store); +static DEVICE_ATTR(chip_freq, S_IRUGO, chip_freq_show, NULL); +static DEVICE_ATTR(vout_regulator, S_IWUSR | S_IRUGO, vout_regulator_show, + vout_regulator_store); + +static struct attribute *sysfs_attrs[] = { + &dev_attr_chip_version.attr, + &dev_attr_chip_vout.attr, + &dev_attr_chip_iout.attr, + &dev_attr_chip_freq.attr, + &dev_attr_chip_enable.attr, + &dev_attr_vout_regulator.attr, + NULL, +}; + +static const struct attribute_group sysfs_group_attrs = { + .attrs = sysfs_attrs, +}; + +static int idtp9220_parse_dt(struct idtp9220_device_info *di) +{ + struct device_node *node = di->dev->of_node; + + if (!node) { + dev_err(di->dev, "device tree node missing\n"); + return -EINVAL; + } + + di->dt_props.irq_gpio = of_get_named_gpio(node, "idt,irq", 0); + if ((!gpio_is_valid(di->dt_props.irq_gpio))) + return -EINVAL; + + di->dt_props.enable_gpio = of_get_named_gpio(node, "idt,enable", 0); + if ((!gpio_is_valid(di->dt_props.enable_gpio))) + return -EINVAL; + + di->dt_props.wpc_det_gpio = of_get_named_gpio(node, "idt,wpc-det", 0); + if ((!gpio_is_valid(di->dt_props.irq_gpio))) + return -EINVAL; + + return 0; +} + +static int idtp9220_gpio_init(struct idtp9220_device_info *di) +{ + int ret = 0; + int irqn = 0; + int wpc_irq = 0; + + di->idt_pinctrl = devm_pinctrl_get(di->dev); + if (IS_ERR_OR_NULL(di->idt_pinctrl)) { + dev_err(di->dev, "No pinctrl config specified\n"); + ret = PTR_ERR(di->dev); + return ret; + } + di->idt_gpio_active = + pinctrl_lookup_state(di->idt_pinctrl, "idt_active"); + if (IS_ERR_OR_NULL(di->idt_gpio_active)) { + dev_err(di->dev, "No active config specified\n"); + ret = PTR_ERR(di->idt_gpio_active); + return ret; + } + di->idt_gpio_suspend = + pinctrl_lookup_state(di->idt_pinctrl, "idt_suspend"); + if (IS_ERR_OR_NULL(di->idt_gpio_suspend)) { + dev_err(di->dev, "No suspend config specified\n"); + ret = PTR_ERR(di->idt_gpio_suspend); + return ret; + } + + ret = pinctrl_select_state(di->idt_pinctrl, di->idt_gpio_active); + if (ret < 0) { + dev_err(di->dev, "fail to select pinctrl active rc=%d\n", ret); + return ret; + } + + if (gpio_is_valid(di->dt_props.irq_gpio)) { + irqn = gpio_to_irq(di->dt_props.irq_gpio); + if (irqn < 0) { + ret = irqn; + goto err_irq_gpio; + } + di->irq = irqn; + } else { + dev_err(di->dev, "%s: irq gpio not provided\n", __func__); + goto err_irq_gpio; + } + + if (gpio_is_valid(di->dt_props.wpc_det_gpio)) { + wpc_irq = gpio_to_irq(di->dt_props.wpc_det_gpio); + if (wpc_irq < 0) { + ret = wpc_irq; + goto err_wpc_irq; + } + di->wpc_irq = wpc_irq; + } else { + dev_err(di->dev, "%s: wpc irq gpio not provided\n", __func__); + goto err_wpc_irq; + } + +err_wpc_irq: + gpio_free(di->dt_props.wpc_det_gpio); +err_irq_gpio: + gpio_free(di->dt_props.irq_gpio); + return ret; +} + +static bool need_irq_cleared(struct idtp9220_device_info *di) +{ + u8 int_buf[2]; + u16 int_val; + int rc = -1; + + rc = di->bus.read_buf(di, REG_INTR_L, int_buf, 2); + if (rc < 0) { + dev_err(di->dev, "%s: read int state error\n", __func__); + return true; + } + int_val = int_buf[0] | (int_buf[1] << 8); + if (int_val != 0) { + dev_info(di->dev, "irq not clear right: 0x%04x\n", int_val); + return true; + } + + if (gpio_is_valid(di->dt_props.irq_gpio)) + rc = gpio_get_value(di->dt_props.irq_gpio); + else { + dev_err(di->dev, "%s: irq gpio not provided\n", __func__); + rc = -1; + } + if (!rc) { + dev_info(di->dev, "irq low, need clear int: %d\n", rc); + return true; + } + return false; +} + +#define VBUCK_QC_VOL 7000 +#define VBUCK_FULL_VOL 7000 +#define VBUCK_DEFAULT_VOL 5500 +#define ADAPTER_BPP_QC_VOL 9000 +#define ADAPTER_BPP_LIMIT_VOL 6500 +#define BPP_VOL_THRESHOLD 8000 +#define ADAPTER_BPP_VOL 5000 +#define ADAPTER_EPP_MI_VOL 15000 +#define EPP_VOL_THRESHOLD 12000 +#define EPP_VOL_LIM_THRESHOLD 13000 +#define BPP_VOL_LIM_THRESHOLD 10000 +#define CHARGING_PERIOD_S 10 +#define TAPER_CURR_Limit 950000 + +static void idtp9220_monitor_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, chg_monitor_work.work); + + idtp9220_charging_info(di); + + idtp9220_set_charging_param(di); + + schedule_delayed_work(&di->chg_monitor_work, CHARGING_PERIOD_S * HZ); +} + +static void idtp9220_rx_vout_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, rx_vout_work.work); + + idtp9220_set_charging_param(di); +} + +static void idtp9220_dc_check_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, dc_check_work.work); + + dev_info(di->dev, "[idt] dc present: %d\n", di->dcin_present); + if (di->dcin_present) { + di->ss = 1; + dev_info(di->dev, "dcin present, quit dc check work\n"); + return; + } else { + di->ss = 0; + dev_info(di->dev, "dcin no present, continue dc check work\n"); + schedule_delayed_work(&di->dc_check_work, + msecs_to_jiffies(2500)); + } + power_supply_changed(di->idtp_psy); +} + +static void idtp9220_fast_operate_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, fast_operate_work.work); + int ret = -1; + int usb_present, typec_mode; + union power_supply_propval val = { + 0, + }; + + ret = idtp9220_get_property_names(di); + if (ret < 0) + return; + + power_supply_get_property(di->usb_psy, POWER_SUPPLY_PROP_PRESENT, &val); + usb_present = val.intval; + + power_supply_get_property(di->usb_psy, POWER_SUPPLY_PROP_TYPEC_MODE, + &val); + typec_mode = val.intval; + + dev_info(di->dev, "usb present:%d typec mode:%d\n", usb_present, + typec_mode); + + if (gpio_is_valid(di->dt_props.wpc_det_gpio)) { + ret = gpio_get_value(di->dt_props.wpc_det_gpio); + /* power good irq will not trigger after insert typec audio/charger + * connector while wireless charging. WR for this situation. + */ + if ((!usb_present && ret) || + (usb_present && ret && + (typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER || + typec_mode == POWER_SUPPLY_TYPEC_NONE))) { + dev_info( + di->dev, + "dc out but power_good high, reset by sleep\n"); + idtp9220_set_enable_mode(di, false); + msleep(10); + idtp9220_set_enable_mode(di, true); + } + } +} + +static void idtp9220_chg_detect_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, chg_detect_work.work); + + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + int rc; + + dev_info(di->dev, "[idt] enter %s\n", __func__); + + rc = idtp9220_get_property_names(di); + if (rc < 0) + return; + + /*set idtp9220 into sleep mode when usbin*/ + + power_supply_get_property(di->usb_psy, POWER_SUPPLY_PROP_ONLINE, &val); + if (val.intval) { + dev_info(di->dev, "[idt] usb_online:%d set chip disable\n", + val.intval); + idtp9220_set_enable_mode(di, false); + return; + } + + if (di->dc_psy) { + power_supply_get_property(di->dc_psy, POWER_SUPPLY_PROP_ONLINE, + &val); + dev_info(di->dev, "[idt] dc_online %d\n", val.intval); + if (val.intval && di->wireless_psy) { + idtp9220_int_enable(di); + wk_val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + di->epp = idtp9220_get_power_profile(di); + + get_cmdline(di); + if (!di->power_off_mode) + idtp9220_set_reset(di); + else + schedule_delayed_work(&di->irq_work, + msecs_to_jiffies(30)); + } + } +} + +#define DC_LOAD_CURRENT 2000000 +#define DC_FUL_CURRENT 50000 +#define SCREEN_OFF_FUL_CURRENT 220000 +#define DC_LOW_CURRENT 350000 +#define DC_SDP_CURRENT 500000 +#define DC_DCP_CURRENT 500000 +#define DC_PD_CURRENT 800000 +#define DC_MI_CURRENT 2100000 +#define DC_MI_STEP1_CURRENT 1200000 +#define DC_QC3_CURRENT 1400000 +#define DC_QC2_CURRENT 1100000 +#define DC_BPP_CURRENT 850000 +#define DC_BPP_AUTH_FAIL_CURRENT 800000 +#define ICL_EXCHANGE_CURRENT 600000 +#define ICL_EXCHANGE_COUNT 5 /*5 = 1min*/ +#define EXCHANGE_9V 0x0 +#define EXCHANGE_5V 0x1 +#define EXCHANGE_15V 0x0 +#define EXCHANGE_12V 0x1 +#define LIMIT_EPP_IOUT 500 +#define LIMIT_BPP_IOUT 400 +#define LIMIT_SOC 80 +#define TAPER_SOC 95 +#define FULL_SOC 100 +#define TAPER_VOL 4350000 +#define TAPER_CUR -500000 + +static void idtp9220_bpp_connect_load_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, bpp_connect_load_work.work); + + idtp922x_set_pmi_icl(di, DC_DCP_CURRENT); +} + +static void idtp9220_epp_connect_load_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, epp_connect_load_work.work); + int dc_load_curr = 0; + + if (di->power_max <= 10000) + dc_load_curr = (di->power_max - 1000) / 5 * 1000; + else + dc_load_curr = DC_LOAD_CURRENT; + + idtp922x_set_pmi_icl(di, dc_load_curr); +} + +static void idtp9220_cmd_check_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, cmd_check_work.work); + + dev_info(di->dev, "[idt] %s: \n", __func__); + idtp922x_get_tx_vin(di); + if (di->power_off_mode) { + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(10)); + } +} + +static void idtp9220_mophie_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, mophie_tx_work.work); + int ret = 0; + u8 buf[2] = { 0 }; + u16 int_val = 0; + + ret = idtp9220_get_power_profile(di); + if (ret) { + ret = di->bus.read_buf(di, REG_TX_TYPE, buf, 2); + if (ret < 0) + dev_err(di->dev, "read tx type error: %d\n", ret); + else { + int_val = buf[0] | (buf[1] << 8); + dev_info(di->dev, "tx type: 0x%04x\n", int_val); + if (int_val == 0x0059) { + dev_info(di->dev, "write vrect target\n"); + di->bus.write(di, 0x0090, 0x0); + di->bus.write(di, 0x0091, 0x8); + di->bus.write(di, 0x003E, 0x41); + } + } + } +} + +static void idtp9220_bpp_e5_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, bpp_e5_tx_work.work); + int icl_curr = 0, vbuck = 0, adapter_vol = 0; + int soc = 0, batt_sts = 0, health = 0; + int icl_setted = 0; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_HEALTH, &val); + health = val.intval; + } + + if (di->tx_charger_type == ADAPTER_QC3) { + adapter_vol = ADAPTER_BPP_QC_VOL; + vbuck = VBUCK_QC_VOL; + icl_curr = DC_QC3_CURRENT; + } else if (di->tx_charger_type == ADAPTER_QC2) { + adapter_vol = ADAPTER_BPP_QC_VOL; + vbuck = VBUCK_QC_VOL; + icl_curr = DC_QC2_CURRENT; + } + + if (di->iout < LIMIT_BPP_IOUT && di->exchange == EXCHANGE_9V) { + di->count_5v++; + di->count_9v = 0; + } else if (di->iout > LIMIT_BPP_IOUT && di->exchange == EXCHANGE_5V) { + di->count_9v++; + di->count_5v = 0; + } else { + di->count_5v = 0; + di->count_9v = 0; + } + /* + * 9V-->5V check 6 times + * 5V-->9v check 3 times + */ + if (di->count_5v > ICL_EXCHANGE_COUNT || + (di->exchange == EXCHANGE_5V && + di->count_9v <= ICL_EXCHANGE_COUNT - 3)) { + dev_info(di->dev, "iout less than 500mA ,set vout to 6.5v\n"); + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = DC_BPP_CURRENT; + di->exchange = EXCHANGE_5V; + } else if (di->count_9v > (ICL_EXCHANGE_COUNT - 3)) + di->exchange = EXCHANGE_9V; + + if (soc > 90) + icl_curr = DC_BPP_CURRENT; + + switch (di->status) { + case NORMAL_MODE: + if (soc >= TAPER_SOC) { + di->status = TAPER_MODE; + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = min(DC_SDP_CURRENT, icl_curr); + } + break; + case TAPER_MODE: + dev_info(di->dev, "[bpp] taper mode set vout to 6.5v\n"); + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = min(DC_SDP_CURRENT, icl_curr); + + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + di->status = FULL_MODE; + else if (soc < TAPER_SOC - 1) + di->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(di->dev, "[bpp] charge full set vout to 6.5v\n"); + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + di->status = RECHG_MODE; + icl_curr = DC_LOW_CURRENT; + } + break; + case RECHG_MODE: + dev_info(di->dev, "[bpp] recharge mode set icl to 300mA\n"); + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = DC_LOW_CURRENT; + + if (soc < TAPER_SOC - 1) + di->status = NORMAL_MODE; + else if (batt_sts == POWER_SUPPLY_STATUS_FULL) + di->status = FULL_MODE; + + if (di->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + } + break; + default: + break; + } + + switch (health) { + case POWER_SUPPLY_HEALTH_GOOD: + break; + case POWER_SUPPLY_HEALTH_COOL: + break; + case POWER_SUPPLY_HEALTH_WARM: + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = min(DC_SDP_CURRENT, icl_curr); + break; + case POWER_SUPPLY_HEALTH_OVERVOLTAGE: + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = min(SCREEN_OFF_FUL_CURRENT, icl_curr); + break; + case POWER_SUPPLY_HEALTH_COLD: + case POWER_SUPPLY_HEALTH_HOT: + adapter_vol = ADAPTER_BPP_LIMIT_VOL; + vbuck = VBUCK_DEFAULT_VOL; + icl_curr = SCREEN_OFF_FUL_CURRENT; + break; + default: + break; + } + + if (adapter_vol != di->last_bpp_vout) { + dev_info(di->dev, "bpp_10w, set new vout: %d, last_vout: %d\n", + adapter_vol, di->last_bpp_vout); + if (adapter_vol > BPP_VOL_THRESHOLD) { + idtp922x_set_adap_vol(di, adapter_vol); + msleep(200); + idtp9220_set_vout_regulator(di, vbuck); + msleep(200); + } else { + idtp9220_set_vout_regulator(di, 5800); + msleep(100); + idtp922x_set_pmi_icl(di, 100000); + msleep(100); + idtp922x_set_adap_vol(di, adapter_vol); + msleep(2000); + idtp922x_set_pmi_icl(di, DC_SDP_CURRENT); + msleep(100); + icl_setted = 1; + } + di->last_bpp_vout = adapter_vol; + } + + if ((icl_curr != di->last_bpp_icl) || (icl_setted)) { + dev_info(di->dev, "bpp_10w, set new icl: %d, last_icl: %d\n", + icl_curr, di->last_bpp_icl); + di->last_bpp_icl = icl_curr; + if ((adapter_vol == ADAPTER_BPP_QC_VOL) && + (!di->bpp_vout_rise)) { + dev_info(di->dev, + "bpp_10w, vout lower than 8v, set 500mA\n"); + icl_curr = min(DC_SDP_CURRENT, icl_curr); + } + idtp922x_set_pmi_icl(di, icl_curr); + } +} + +static void idtp9220_qc2_f1_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, qc2_f1_tx_work.work); + int soc = 0, batt_sts = 0; + int vout = VOUT_VAL_6500_MV; + int dc_icl = DC_QC2_CURRENT; + union power_supply_propval val = { + 0, + }; + + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + } + + if (vout != di->last_qc2_vout) { + dev_info(di->dev, + "qc2+f1_tx, set new vout: %d, last_vout: %d\n", vout, + di->last_qc2_vout); + di->last_qc2_vout = vout; + di->bus.write(di, 0x003E, vout); + msleep(100); + idtp9220_set_vout_regulator(di, VBUCK_DEFAULT_VOL); + msleep(100); + } + + if (dc_icl != di->last_qc2_icl) { + dev_info(di->dev, "qc2+f1_tx, set new icl: %d, last_icl: %d\n", + dc_icl, di->last_qc2_icl); + di->last_qc2_icl = dc_icl; + idtp922x_set_pmi_icl(di, dc_icl); + } +} + +static void idtp9220_qc3_epp_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, qc3_epp_work.work); + int adapter_vol = 0; + int dc_icl = DC_MI_STEP1_CURRENT; + + if (adapter_vol != di->last_qc3_vout) { + dev_info(di->dev, "qc3 epp, set new vout: %d, last_vout: %d\n", + adapter_vol, di->last_qc3_vout); + di->last_qc3_vout = adapter_vol; + idtp922x_set_adap_vol(di, adapter_vol); + msleep(200); + } + + if (dc_icl != di->last_qc3_icl) { + dev_info(di->dev, "qc3_epp, set new icl: %d, last_icl: %d\n", + dc_icl, di->last_qc3_icl); + di->last_qc3_icl = dc_icl; + if (dc_icl == DC_MI_STEP1_CURRENT) { + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(0)); + } + idtp922x_set_pmi_icl(di, dc_icl); + } +} + +static void idtp9220_vout_regulator_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, vout_regulator_work.work); + + union power_supply_propval val = { + 0, + }; + int ret; + int vinc = 0; + int soc = 0; + + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + } + + if (di) + idtp9220_get_vout(di); + else + return; + + if (di->epp) + vinc = (di->vout > EPP_VOL_THRESHOLD) ? 1 : 0; + else + vinc = (di->vout > BPP_VOL_THRESHOLD) ? 1 : 0; + + if (vinc && !di->epp) { + di->bpp_vout_rise = 1; + goto out; + } else if (!vinc && !di->epp) { + di->bpp_vout_rise = 0; + goto out; + } + + if (di->epp && (vinc || di->is_epp_qc3 || di->is_vin_limit) && + soc < 95) { + ret = idtp9220_get_property_names(di); + if (di->wireless_psy) { + val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + msleep(200); + if (!di->is_epp_qc3 && !di->is_vin_limit) + idtp922x_set_pmi_icl(di, DC_MI_CURRENT); + } else + dev_err(di->dev, "[idt] no wireless psy\n"); + } +out: + dev_info(di->dev, "[idt] %s: epp=%d vbuck=%d vout= %d\n", __func__, + di->epp, di->vbuck, di->vout); + return; +} + +static void idtp9220_set_charging_param(struct idtp9220_device_info *di) +{ + int soc = 0, health = 0, batt_sts = 0; + int adapter_vol = 0, icl_curr = 0; + int cur_now = 0, vol_now = 0, vin_inc = 0; + union power_supply_propval val = { + 0, + }; + + switch (di->tx_charger_type) { + case ADAPTER_QC2: + adapter_vol = ADAPTER_BPP_QC_VOL; + di->vbuck = VBUCK_QC_VOL; + icl_curr = DC_QC2_CURRENT; + break; + case ADAPTER_QC3: + if (!di->epp) { + adapter_vol = ADAPTER_BPP_QC_VOL; + di->vbuck = VBUCK_QC_VOL; + icl_curr = DC_QC3_CURRENT; + } else { + di->is_epp_qc3 = 1; + icl_curr = DC_MI_STEP1_CURRENT; + } + break; + case ADAPTER_XIAOMI_PD: + case ADAPTER_PD: + if (di->epp) { + di->vbuck = VBUCK_QC_VOL; + icl_curr = DC_QC3_CURRENT; + } else { + di->vbuck = VBUCK_DEFAULT_VOL; + icl_curr = DC_PD_CURRENT; + } + break; + case ADAPTER_AUTH_FAILED: + if (di->epp) { + di->vbuck = VBUCK_QC_VOL; + if (di->power_max <= 10000) + icl_curr = ((di->power_max - 1000) / + (VBUCK_QC_VOL / 1000)) * + 1000; + else + icl_curr = DC_QC3_CURRENT; + } else { + di->vbuck = VBUCK_DEFAULT_VOL; + icl_curr = DC_BPP_AUTH_FAIL_CURRENT; + } + break; + case ADAPTER_DCP: + case ADAPTER_CDP: + di->vbuck = VBUCK_DEFAULT_VOL; + if (di->is_compatible_hwid) + icl_curr = DC_BPP_AUTH_FAIL_CURRENT; + else + icl_curr = DC_DCP_CURRENT; + break; + case ADAPTER_SDP: + di->vbuck = VBUCK_DEFAULT_VOL; + icl_curr = DC_SDP_CURRENT; + break; + case ADAPTER_XIAOMI_QC3: + case ADAPTER_ZIMI_CAR_POWER: + case ADAPTER_XIAOMI_PD_40W: + if (di->epp) { + adapter_vol = ADAPTER_EPP_MI_VOL; + icl_curr = DC_MI_STEP1_CURRENT; + } else { + di->vbuck = VBUCK_QC_VOL; + icl_curr = DC_QC3_CURRENT; + } + break; + default: + icl_curr = 0; + break; + } + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_CAPACITY, + &val); + soc = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, + &val); + vol_now = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_CURRENT_NOW, + &val); + cur_now = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_HEALTH, &val); + health = val.intval; + + idtp9220_get_iout(di); + + if ((batt_sts == POWER_SUPPLY_STATUS_DISCHARGING) && di->dcin_present && + di->power_good_flag) { + dev_info(di->dev, + "discharge when dc and pwr present, reset chip\n"); + schedule_delayed_work(&di->fast_operate_work, + msecs_to_jiffies(0)); + return; + } + dev_info( + di->dev, + "[idtp] soc:%d,vol_now:%d,cur_now:%d,health:%d, bat_status:%d\n", + soc, vol_now, cur_now, health, batt_sts); + + /* adapter:qc2/qc3; tx:e5/d5x_10W; + * vout/vbuck/psns is setted in delayed work + */ + if (adapter_vol == ADAPTER_BPP_QC_VOL && di->is_compatible_hwid) { + schedule_delayed_work(&di->bpp_e5_tx_work, msecs_to_jiffies(0)); + goto out; + } + + /* adapter:qc2; tx:F1_27W; + * vout/vbuck/psns is setted in delayed work + */ + if (di->tx_charger_type == ADAPTER_QC2 && di->is_f1_tx) { + schedule_delayed_work(&di->qc2_f1_tx_work, msecs_to_jiffies(0)); + goto out; + } + + /* adapter:qc3_epp; tx:F1_27W; + * vout/vbuck/psns is setted in delayed work + */ + if (di->is_epp_qc3) { + schedule_delayed_work(&di->qc3_epp_work, msecs_to_jiffies(0)); + goto out; + } + + if (adapter_vol > 0 && adapter_vol != di->last_vin) { + idtp922x_set_adap_vol(di, adapter_vol); + vin_inc = 1; + di->last_vin = adapter_vol; + if (adapter_vol == ADAPTER_EPP_MI_VOL || + adapter_vol == EPP_VOL_THRESHOLD) { + msleep(100); + idtp922x_set_pmi_icl(di, icl_curr); + di->last_icl = icl_curr; + if (di->is_vin_limit) + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(0)); + } + } else { + if (((di->tx_charger_type == ADAPTER_QC2) || + (di->tx_charger_type == ADAPTER_QC3)) && + !di->epp && !di->bpp_vout_rise && icl_curr > DC_DCP_CURRENT) + dev_info( + di->dev, + "don't set curr with qc2/qc3 of bpp when vout low\n"); + else { + if (icl_curr > 0 && icl_curr != di->last_icl) { + idtp922x_set_pmi_icl(di, icl_curr); + di->last_icl = icl_curr; + } + msleep(150); + if (di->vbuck > 0 && di->vbuck != di->last_vbuck) { + idtp9220_set_vout_regulator(di, di->vbuck); + di->last_vbuck = di->vbuck; + } + } + } + + printk("[idtp] di->status:0x%x,adapter_vol =%d,icl_curr=%d, vbuck=%d, last_vin=%d, last_icl=%d\n", + di->status, adapter_vol, icl_curr, di->vbuck, di->last_vin, + di->last_icl); + + if (adapter_vol == ADAPTER_EPP_MI_VOL || + adapter_vol == ADAPTER_BPP_QC_VOL || + adapter_vol == VBUCK_FULL_VOL) { + if (vin_inc && (!di->is_vin_limit && !di->is_epp_qc3)) + schedule_delayed_work(&di->cmd_check_work, + msecs_to_jiffies(8000)); + } + +out: + return; +} + +static void idtp9220_wpc_det_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, wpc_det_work.work); + union power_supply_propval val = { + 0, + }; + int ret = 0; + + ret = idtp9220_get_property_names(di); + if (ret < 0) { + dev_err(di->dev, "get property error: %d\n", ret); + return; + } + + if (gpio_is_valid(di->dt_props.wpc_det_gpio)) { + ret = gpio_get_value(di->dt_props.wpc_det_gpio); + if (ret) { + /* check if mophie tx after 100ms */ + schedule_delayed_work(&di->mophie_tx_work, + msecs_to_jiffies(100)); + /* check dc present to judge device skewing */ + schedule_delayed_work(&di->dc_check_work, + msecs_to_jiffies(2500)); + di->power_good_flag = 1; + val.intval = 1; + idtp9220_int_enable(di); + } else { + cancel_delayed_work(&di->dc_check_work); + di->power_good_flag = 0; + val.intval = 0; + di->ss = 2; + } + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, &val); + } + + return; +} + +static void idtp9220_irq_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = + container_of(work, struct idtp9220_device_info, irq_work.work); + u8 int_buf[2] = { 0 }; + u16 int_val = 0; + int rc = 0; + u8 recive_data[5] = { 0 }; + static int retry = 0; + static int retry_id = 0; + static int retry_count = 0; + int tx_vin = 0; + int irq_level; + + if (gpio_is_valid(di->dt_props.irq_gpio)) + irq_level = gpio_get_value(di->dt_props.irq_gpio); + else { + dev_err(di->dev, "%s: irq gpio not provided\n", __func__); + irq_level = -1; + return; + } + if (irq_level) { + return; + } + + rc = di->bus.read_buf(di, REG_INTR_L, int_buf, 2); + if (rc < 0) { + dev_err(di->dev, "[idt]read int state error: %d\n", rc); + goto out; + } + /* clear int and enable irq immediately when read int register*/ + idtp922x_clrInt(di, int_buf, 2); + + int_val = int_buf[0] | (int_buf[1] << 8); + dev_info(di->dev, "[idt] int: 0x%04x\n", int_val); + + msleep(5); + + if (need_irq_cleared(di)) { + u8 clr_buf[2] = { 0xFF, 0xFF }; + idtp922x_clrInt(di, clr_buf, 2); + msleep(5); + } + if ((int_val & INT_OV_CURR) || (int_val & INT_OV_TEMP)) { + dev_info(di->dev, "[idt] ocp or otp found \n"); + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(0)); + goto out; + } + + if (int_val & INT_VOUT_ON) { + di->epp = idtp9220_get_power_profile(di); + if (di->epp) { + di->power_max = idtp9220_get_power_max(di); + schedule_delayed_work(&di->epp_connect_load_work, + msecs_to_jiffies(0)); + } else + schedule_delayed_work(&di->bpp_connect_load_work, + msecs_to_jiffies(0)); + if (int_val & INT_IDAUTH_SUCESS) + idtp9220_send_device_auth(di); + goto out; + } + + if (int_val & INT_VSWITCH_SUCESS) { + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(50)); + cancel_delayed_work(&di->cmd_check_work); + goto out; + } + + if (int_val & INT_IDAUTH_SUCESS) { + idtp9220_send_device_auth(di); + //idtp922x_request_adapter(di); + goto out; + } + + if (int_val & INT_AUTH_SUCESS) { + idtp922x_request_uuid(di, di->epp); + goto out; + } + /* + idtp9220_get_signal_strength(di); + di->tx_charger_type = ADAPTER_QC3; + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(0)); + goto out; +*/ + + if ((int_val & INT_IDAUTH_FAIL) || (int_val & INT_AUTH_FAIL) || + int_val == 0) { + if (((int_val & INT_AUTH_FAIL) || (int_val == 0)) && + (retry < 5)) { + idtp9220_send_device_auth(di); + retry++; + dev_info(di->dev, "[idtp] dev auth failed retry %d\n", + retry); + goto out; + } else if ((int_val & INT_IDAUTH_FAIL) && retry_id < 5) { + idtp9220_retry_id_auth(di); + retry_id++; + dev_info(di->dev, "[idtp] id auth failed retry %d\n", + retry); + goto out; + } else { + retry = 0; + retry_id = 0; + } + di->tx_charger_type = ADAPTER_AUTH_FAILED; + + schedule_delayed_work(&di->rx_vout_work, msecs_to_jiffies(0)); + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(0)); + goto out; + } else + retry = 0; + /* + if (int_val & INT_IDAUTH_FAIL) { + idtp922x_request_adapter(di); + goto out; + } +*/ + + if (int_val & INT_SEND_TIMEOUT) { + if (retry_count < 3) { + dev_info(di->dev, "timeout retry %d\n", retry_count); + idtp922x_retry_cmd(di); + retry_count++; + goto out; + } else { + dev_err(di->dev, "%s: retry failed\n", __func__); + di->tx_charger_type = ADAPTER_AUTH_FAILED; + schedule_delayed_work(&di->rx_vout_work, + msecs_to_jiffies(0)); + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(0)); + retry_count = 0; + goto out; + } + } else { + retry_count = 0; + } + + if (int_val & INT_TX_DATA_RECV) { + idtp922x_receivePkt(di, recive_data); + dev_info(di->dev, "[idt] cmd: %x\n", recive_data[0]); + + switch (recive_data[0]) { + case BC_TX_HWID: + if (recive_data[4] == 0x01 && recive_data[2] == 0x2 && + recive_data[3] == 0x8 && recive_data[1] == 0x6) { + di->is_car_tx = 1; + } + idtp922x_request_adapter(di); + break; + case BC_TX_COMPATIBLE_HWID: + if (recive_data[1] == 0x12 && recive_data[2]) + di->is_compatible_hwid = 1; + if (recive_data[1] == 0x16 && recive_data[2] == 0x11) + di->is_f1_tx = 1; + idtp922x_request_adapter(di); + break; + case BC_ADAPTER_TYPE: + if (di->is_car_tx && + (recive_data[1] == ADAPTER_XIAOMI_QC3)) + + di->tx_charger_type = ADAPTER_ZIMI_CAR_POWER; + else + di->tx_charger_type = recive_data[1]; + + if (!di->epp && (di->tx_charger_type == ADAPTER_QC3 || + di->tx_charger_type == ADAPTER_QC2)) { + idtp922x_set_adap_vol(di, ADAPTER_BPP_VOL); + } + schedule_delayed_work(&di->rx_vout_work, + msecs_to_jiffies(100)); + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(1000)); + if (di->wireless_psy) + power_supply_changed(di->wireless_psy); + break; + case BC_READ_Vin: + tx_vin = recive_data[1] | (recive_data[2] << 8); + if (!di->power_off_mode) { + if (di->epp) + idtp922x_set_adap_vol( + di, ADAPTER_EPP_MI_VOL); + else + idtp922x_set_adap_vol( + di, ADAPTER_BPP_QC_VOL); + } + break; + case BC_RX_ID_AUTH: + idtp9220_send_device_auth(di); + break; + default: + dev_info(di->dev, "[idt] unsupport cmd: %x\n", + recive_data[0]); + break; + } + } + +out: + return; +} + +static irqreturn_t idtp9220_wpc_det_irq_handler(int irq, void *dev_id) +{ + struct idtp9220_device_info *di = dev_id; + + schedule_delayed_work(&di->wpc_det_work, msecs_to_jiffies(0)); + + return IRQ_HANDLED; +} + +static irqreturn_t idtp9220_irq_handler(int irq, void *dev_id) +{ + struct idtp9220_device_info *di = dev_id; + + schedule_delayed_work(&di->irq_work, msecs_to_jiffies(30)); + + return IRQ_HANDLED; +} + +static int idtp9220_irq_request(struct idtp9220_device_info *di) +{ + int ret = 0; + + if (!di->irq) { + dev_err(di->dev, "%s: irq is wrong\n", __func__); + return -EINVAL; + } + + ret = request_irq(di->irq, idtp9220_irq_handler, IRQF_TRIGGER_FALLING, + di->name, di); + if (ret) { + dev_err(di->dev, "%s: request_irq failed\n", __func__); + return ret; + } + + ret = enable_irq_wake(di->irq); + if (ret) { + dev_err(di->dev, "%s: enable_irq_wake failed\n", __func__); + return ret; + } + + if (!di->wpc_irq) { + dev_err(di->dev, "%s: wpc irq is wrong\n", __func__); + return -EINVAL; + } + + ret = request_irq(di->wpc_irq, idtp9220_wpc_det_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "wpc_det", + di); + if (ret) { + dev_err(di->dev, "%s: wpc request_irq failed\n", __func__); + return ret; + } + + ret = enable_irq_wake(di->wpc_irq); + if (ret) { + dev_err(di->dev, "%s: enable_irq_wake failed\n", __func__); + return ret; + } + + return 0; +} + +static struct regmap_config i2c_idtp9220_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0xFFFF, +}; + +/* +static int idtp9220_get_version(struct idtp9220_device_info *di) +{ + int id_val = 0; + u8 chip_id[2] = {0}; + + di->bus.read_buf(di, REG_CHIP_ID_L, chip_id, 2); + id_val = (chip_id[1] << 8) | chip_id[0]; + + return id_val; +} +*/ + +static enum power_supply_property idtp9220_props[] = { + POWER_SUPPLY_PROP_PIN_ENABLED, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_WIRELESS_VERSION, + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, + POWER_SUPPLY_PROP_TX_ADAPTER, +}; + +static int idtp9220_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct idtp9220_device_info *di = power_supply_get_drvdata(psy); + + switch (psp) { + case POWER_SUPPLY_PROP_PIN_ENABLED: + val->intval = gpio_get_value(di->dt_props.enable_gpio); + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = di->dcin_present; + break; + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + val->intval = di->epp; + break; + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + val->intval = di->ss; + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + val->intval = idtp9220_get_vout_regulator(di); + break; + case POWER_SUPPLY_PROP_TX_ADAPTER: + val->intval = di->tx_charger_type; + break; + default: + return -EINVAL; + } + return 0; +} + +static int idtp9220_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct idtp9220_device_info *di = power_supply_get_drvdata(psy); + int rc = 0; + + int data; + + switch (psp) { + case POWER_SUPPLY_PROP_PIN_ENABLED: + rc = idtp9220_set_enable_mode(di, val->intval); + break; + case POWER_SUPPLY_PROP_PRESENT: + rc = idtp9220_set_present(di, val->intval); + break; + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + di->ss = val->intval; + power_supply_changed(di->idtp_psy); + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + data = val->intval / 1000; + if (data >= 6000) { + idtp9220_set_vout_regulator(di, data); + dev_info(di->dev, "[idt] set buck %s\n", __func__); + } + break; + default: + return -EINVAL; + } + + return rc; +} + +static int idtp9220_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + int rc; + + switch (psp) { + case POWER_SUPPLY_PROP_PIN_ENABLED: + case POWER_SUPPLY_PROP_PRESENT: + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + return 1; + default: + rc = 0; + break; + } + + return rc; +} + +static const struct power_supply_desc idtp_psy_desc = { + .name = "idt", + .type = POWER_SUPPLY_TYPE_WIRELESS, + .properties = idtp9220_props, + .num_properties = ARRAY_SIZE(idtp9220_props), + .get_property = idtp9220_get_prop, + .set_property = idtp9220_set_prop, + .property_is_writeable = idtp9220_prop_is_writeable, +}; + +static int idtp9220_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct idtp9220_device_info *di; + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + struct power_supply_config idtp_cfg = {}; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE)) { + dev_err(&client->dev, "i2c check functionality failed!\n"); + return -EIO; + } + + di = devm_kzalloc(&client->dev, sizeof(*di), GFP_KERNEL); + if (!di) { + dev_err(&client->dev, + "i2c allocated device info data failed!\n"); + return -ENOMEM; + } + + di->name = IDT_DRIVER_NAME; + di->dev = &client->dev; + di->chip_enable = 1; + di->ss = 2; + di->status = NORMAL_MODE; + di->regmap = devm_regmap_init_i2c(client, &i2c_idtp9220_regmap_config); + if (!di->regmap) + return -ENODEV; + di->bus.read = idtp9220_read; + di->bus.write = idtp9220_write; + di->bus.read_buf = idtp9220_read_buffer; + di->bus.write_buf = idtp9220_write_buffer; + INIT_DELAYED_WORK(&di->irq_work, idtp9220_irq_work); + INIT_DELAYED_WORK(&di->wpc_det_work, idtp9220_wpc_det_work); + mutex_init(&di->read_lock); + mutex_init(&di->write_lock); + device_init_wakeup(&client->dev, true); + i2c_set_clientdata(client, di); + g_di = di; + + ret = idtp9220_parse_dt(di); + if (ret < 0) { + dev_err(di->dev, "%s: parse dt error [%d]\n", __func__, ret); + goto cleanup; + } + + ret = idtp9220_gpio_init(di); + if (ret < 0) { + dev_err(di->dev, "%s: gpio init error [%d]\n", __func__, ret); + goto cleanup; + } + + ret = idtp9220_irq_request(di); + if (ret < 0) { + dev_err(di->dev, "%s: request irq error [%d]\n", __func__, ret); + goto cleanup; + } + + if (sysfs_create_group(&client->dev.kobj, &sysfs_group_attrs)) { + dev_err(&client->dev, "create sysfs attrs failed!\n"); + ret = -EIO; + goto cleanup; + } + idtp_cfg.drv_data = di; + di->idtp_psy = + power_supply_register(di->dev, &idtp_psy_desc, &idtp_cfg); + + INIT_DELAYED_WORK(&di->chg_monitor_work, idtp9220_monitor_work); + INIT_DELAYED_WORK(&di->chg_detect_work, idtp9220_chg_detect_work); + INIT_DELAYED_WORK(&di->bpp_connect_load_work, + idtp9220_bpp_connect_load_work); + INIT_DELAYED_WORK(&di->epp_connect_load_work, + idtp9220_epp_connect_load_work); + INIT_DELAYED_WORK(&di->cmd_check_work, idtp9220_cmd_check_work); + INIT_DELAYED_WORK(&di->vout_regulator_work, + idtp9220_vout_regulator_work); + INIT_DELAYED_WORK(&di->rx_vout_work, idtp9220_rx_vout_work); + INIT_DELAYED_WORK(&di->dc_check_work, idtp9220_dc_check_work); + INIT_DELAYED_WORK(&di->fast_operate_work, idtp9220_fast_operate_work); + INIT_DELAYED_WORK(&di->mophie_tx_work, idtp9220_mophie_tx_work); + INIT_DELAYED_WORK(&di->bpp_e5_tx_work, idtp9220_bpp_e5_tx_work); + INIT_DELAYED_WORK(&di->qc2_f1_tx_work, idtp9220_qc2_f1_tx_work); + INIT_DELAYED_WORK(&di->qc3_epp_work, idtp9220_qc3_epp_work); + + dev_info(di->dev, "[idt] success probe idtp922x driver\n"); + schedule_delayed_work(&di->chg_detect_work, 3 * HZ); + + return 0; + +cleanup: + free_irq(di->irq, di); + cancel_delayed_work_sync(&di->irq_work); + i2c_set_clientdata(client, NULL); + + return ret; +} + +static int idtp9220_remove(struct i2c_client *client) +{ + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + gpio_free(di->dt_props.enable_gpio); + cancel_delayed_work_sync(&di->irq_work); + i2c_set_clientdata(client, NULL); + + return 0; +} + +static void idtp9220_shutdown(struct i2c_client *client) +{ + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + if (di->power_good_flag) + idtp9220_set_reset(di); +} + +static const struct i2c_device_id idtp9220_id[] = { + { IDT_DRIVER_NAME, 0 }, + {}, +}; + +static const struct of_device_id idt_match_table[] = { { .compatible = + "idt,p9220" }, + {} }; + +MODULE_DEVICE_TABLE(i2c, idtp9220_id); + +static struct i2c_driver idtp9220_driver = { + .driver = { + .name = IDT_DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = idt_match_table, + }, + .probe = idtp9220_probe, + .remove = idtp9220_remove, + .shutdown = idtp9220_shutdown, + .id_table = idtp9220_id, +}; + +module_i2c_driver(idtp9220_driver); + +MODULE_AUTHOR("bsp-charging@xiaomi.com"); +MODULE_DESCRIPTION("IDTP9220 Wireless Power Charger Monitor driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/power/supply/renesas/idtp9220.h b/drivers/power/supply/renesas/idtp9220.h new file mode 100644 index 000000000000..f3a067e6358a --- /dev/null +++ b/drivers/power/supply/renesas/idtp9220.h @@ -0,0 +1,2263 @@ +/** + * @file idtp9220.h + * @author + * @date Sun Nov 22 11:49:55 2015 + * + * @brief + * + * + */ +#ifndef __IDTP9220_H__ +#define __IDTP9220_H__ + +#include +#include +#include + +#define IDT_DRIVER_NAME "idtp9220" +#define IDT_I2C_ADDR 0x61 + +#define HSCLK 60000 + +#define ADJUST_METE_MV 35 +#define IDTP9220_DELAY 2000 +#define CHARGING_FULL 100 +#define CHARGING_NEED 95 + +/* status low regiter bits define */ +#define STATUS_VOUT_ON (1 << 7) +#define STATUS_VOUT_OFF (1 << 6) +#define STATUS_TX_DATA_RECV (1 << 4) +#define STATUS_OV_TEMP (1 << 2) +#define STATUS_OV_VOL (1 << 1) +#define STATUS_OV_CURR (1 << 0) + +#define OVER_EVENT_OCCUR (STATUS_OV_TEMP | STATUS_OV_VOL | STATUS_OV_CURR) +#define TOGGLE_LDO_ON_OFF (1 << 1) + +/* interrupt register bits define */ +#define INT_IDAUTH_SUCESS (1 << 13) +#define INT_IDAUTH_FAIL (1 << 12) +#define INT_SEND_SUCESS (1 << 11) +#define INT_SEND_TIMEOUT (1 << 10) +#define INT_AUTH_SUCESS (1 << 9) +#define INT_AUTH_FAIL (1 << 8) +#define INT_VOUT_OFF (1 << 7) +#define INT_VOUT_ON (1 << 6) +#define INT_MODE_CHANGE (1 << 5) +#define INT_TX_DATA_RECV (1 << 4) +#define INT_VSWITCH_SUCESS (1 << 3) +#define INT_OV_TEMP (1 << 2) +#define INT_OV_VOL (1 << 1) +#define INT_OV_CURR (1 << 0) + +/* used registers define */ +#define REG_CHIP_ID_L 0x0000 +#define REG_CHIP_ID_H 0x0001 +#define REG_CHIP_REV 0x0002 +#define REG_CTM_ID 0x0003 +#define REG_OTPFWVER_ADDR 0x0004 // OTP firmware version +#define REG_EPRFWVER_ADDR 0x001c // EEPROM firmware version +#define REG_STATUS_L 0x0034 +#define REG_STATUS_H 0x0035 +#define REG_INTR_L 0x0036 +#define REG_INTR_H 0x0037 +#define REG_INTR_EN_L 0x0038 +#define REG_INTR_EN_H 0x0039 +#define REG_CHG_STATUS 0x003A +#define REG_ADC_VOUT_L 0x003C +#define REG_ADC_VOUT_H 0x003D +#define REG_VOUT_SET 0x003E +#define REG_VRECT_ADJ 0x003F +#define REG_ADC_VRECT 0x0040 +#define REG_RX_LOUT_L 0x0044 +#define REG_RX_LOUT_H 0x0045 +#define REG_FREQ_ADDR \ + 0x0048 // Operating Frequency, Fop(KHz) = 64 * 6000 /value * 256) +#define REG_ILIM_SET 0x004A +#define REG_SIGNAL_STRENGTH 0x004B +#define REG_WPC_MODE 0x004D +#define REG_SSCMND 0x004e // Command Register, COM (0x4E) +#define REG_RX_RESET 0x004F +#define REG_PROPPKT \ + 0x0050 // Proprietary Packet Header Register, PPP_Header (0x50) +#define REG_PPPDATA \ + 0x0051 // PPP Data Value Register(0X51, 0x52, 0x53, 0x54, 0x55) +#define REG_SSINTCLR 0x0056 // Interrupt Clear Registers, INT_Clear_L (0x56) +#define REG_BCHEADER 0x0058 // Back Channel Packet Register (0x58) +#define REG_BCDATA \ + 0x0059 // Back Channel Packet Register (0x59, 0x5A, 0x5B, 0x5C) +#define REG_FC_VOLTAGE_L 0x0078 // Fast Charging Voltage Register +#define REG_FC_VOLTAGE_H 0x0079 +#define REG_REGULATOR_L 0x000C +#define REG_REGULATOR_H 0x000d +#define REG_POWER_MAX 0x0084 //Get the TX power on EPP mode. +#define REG_TX_TYPE 0x00A2 //Get the TX type. + +// RX -> TX +#define PROPRIETARY18 0x18 +#define PROPRIETARY28 0x28 +#define PROPRIETARY38 0x38 +#define PROPRIETARY48 0x48 +#define PROPRIETARY58 0x58 + +// bitmap for customer command +#define BC_NONE 0x00 +#define BC_SET_FREQ 0x03 +#define BC_GET_FREQ 0x04 +#define BC_READ_FW_VER 0x05 +#define BC_READ_Iin 0x06 +#define BC_READ_Vin 0x07 +#define BC_SET_Vin 0x0a + +#define BC_ADAPTER_TYPE 0x0b +#define BC_RESET 0x0c +#define BC_READ_I2C 0x0d +#define BC_WRITE_I2C 0x0e +#define BC_VI2C_INIT 0x10 +#define BC_RX_ID_AUTH 0x3b +#define BC_TX_COMPATIBLE_HWID 0x3f +#define BC_TX_HWID 0x4c +#define BC_TX_TOGGLE 0xc4 + +//Factory test command +#define BC_READ_IOUT 0x12 +#define BC_READ_VOUT 0x13 +#define BC_START_CHARGE 0x30 +#define BC_SET_AP_OVERLOAD 0x31 +#define BC_ENABLE_FAST_CHARGE 0x32 + +/* Adapter_list = {0x00:'ADAPTER_UNKNOWN', */ +/* 0x01:'SDP 500mA', */ +/* 0x02:'CDP 1.1A', */ +/* 0x03:'DCP 1.5A', */ +/* 0x05:'QC2.0', */ +/* 0x06:'QC3.0', */ +/* 0x07:'PD',} */ +//define adapter type +#define ADAPTER_NONE 0x00 +#define ADAPTER_SDP 0x01 +#define ADAPTER_CDP 0x02 +#define ADAPTER_DCP 0x03 +#define ADAPTER_QC2 0x05 +#define ADAPTER_QC3 0x06 +#define ADAPTER_PD 0x07 +#define ADAPTER_AUTH_FAILED 0x08 +#define ADAPTER_XIAOMI_QC3 0x09 +#define ADAPTER_XIAOMI_PD 0x0a +#define ADAPTER_ZIMI_CAR_POWER 0x0b +#define ADAPTER_XIAOMI_PD_40W 0x0c + +#define NORMAL_MODE 0x1 +#define TAPER_MODE 0x2 +#define FULL_MODE 0x3 +#define RECHG_MODE 0x4 + +// bitmap for status flags +// 1: indicates a pending interrupt for LDO Vout state change – from OFF to ON +#define VOUTCHANGED BIT(7) // Stat_Vout_ON +// 1: indicates a pending interrupt for TX Data Received. (Change from “No Received Data†state to “Data Received†state) +#define TXDATARCVD BIT(4) // TX Data Received + +// bitmap for SSCmnd register 0x4e +#define VSWITCH BIT(7) +// If AP sets this bit to "1" then IDTP9220 M0 clears the interrupt corresponding to the bit(s) which has a value of “1†+#define CLRINT BIT(5) // Clear Interrupt +// If AP sets this bit to "1" then IDTP9220 M0 toggles LDO output once (from on to off, or from off to on), and then sets this bit to “0†+#define LDOTGL BIT(1) // Toggle LDO On/OFF +// If AP sets this bit to “1†then IDTP9220 M0 sends the Proprietary Packet +#define SENDPROPP BIT(0) // SEND RX Data + +#define SEND_DEVICE_AUTH BIT(2) + +enum VOUT_SET_VAL { + VOUT_VAL_3500_MV = 0, + VOUT_VAL_3600_MV, + VOUT_VAL_3700_MV, + VOUT_VAL_3800_MV, + VOUT_VAL_3900_MV, + VOUT_VAL_4000_MV, + VOUT_VAL_4100_MV, + VOUT_VAL_4200_MV, + VOUT_VAL_4300_MV, + VOUT_VAL_4400_MV, + VOUT_VAL_4500_MV, + VOUT_VAL_4600_MV, + VOUT_VAL_4700_MV, + VOUT_VAL_4800_MV, + VOUT_VAL_4900_MV, + VOUT_VAL_5000_MV, + VOUT_VAL_5100_MV, + VOUT_VAL_5200_MV, + VOUT_VAL_5300_MV, + VOUT_VAL_5400_MV, + VOUT_VAL_5500_MV, + VOUT_VAL_5600_MV, + VOUT_VAL_5700_MV, + VOUT_VAL_5800_MV, + VOUT_VAL_5900_MV, + VOUT_VAL_6000_MV, + VOUT_VAL_6100_MV, + VOUT_VAL_6200_MV, + VOUT_VAL_6300_MV, + VOUT_VAL_6400_MV, + VOUT_VAL_6500_MV, + VOUT_VAL_6600_MV, + VOUT_VAL_6700_MV, + VOUT_VAL_6800_MV, + VOUT_VAL_6900_MV, + VOUT_VAL_7000_MV, + VOUT_VAL_7100_MV, + VOUT_VAL_7200_MV, + VOUT_VAL_7300_MV, + VOUT_VAL_7400_MV, + VOUT_VAL_7500_MV, + VOUT_VAL_7600_MV, + VOUT_VAL_7700_MV, + VOUT_VAL_7800_MV, + VOUT_VAL_7900_MV, + VOUT_VAL_8000_MV, +}; + +enum IMIL_SET_VAL { + CURR_VAL_100_MA = 0, + CURR_VAL_200_MA, + CURR_VAL_300_MA, + CURR_VAL_400_MA, + CURR_VAL_500_MA, + CURR_VAL_600_MA, + CURR_VAL_700_MA, + CURR_VAL_800_MA, + CURR_VAL_900_MA, + CURR_VAL_1000_MA, + CURR_VAL_1100_MA, + CURR_VAL_1200_MA, + CURR_VAL_1300_MA, +}; + +struct vol_curr_table { + int index; + char *val; +}; +/* +struct idtp9220_platform_data { + enum VOUT_SET_VAL vout_val_default; + enum IMIL_SET_VAL curr_val_default; + unsigned long gpio_en; +}; +*/ +typedef struct { // write to structure at SRAM address 0x0400 + u16 status; // Read/Write by both 9220 and 9220 host + u16 startAddr; // OTP image address of the current packet + u16 codeLength; // The size of the OTP image data in the current packet + u16 dataChksum; // Checksum of the current packet + u8 dataBuf[128]; // OTP image data of the current packet +} idtp9220_packet_t; + +// proprietary packet type +typedef struct { + u8 header; // The header consists of a single byte that indicates the Packet type. + u8 cmd; // Back channel command + u8 data[4]; // Send data buffer +} ProPkt_Type; + +#if 1 +static char bootloader_data[] = { + 0x00, 0x04, 0x00, 0x20, 0xe3, 0x00, 0x00, 0x00, + 0x41, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, /// 0x10 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /// 0x20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, /// 0x30 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /// 0x40 + 0xfe, 0xe7, 0x00, 0x00, 0xf0, 0xb5, 0x3e, 0x49, + 0x00, 0x20, 0x0a, 0x88, 0x05, 0x46, 0x93, 0x06, /// 0x50 + 0x00, 0xd5, 0x04, 0x20, 0xd2, 0x06, 0x07, 0xd5, + 0x8a, 0x78, 0x0b, 0x79, 0x1a, 0x43, 0x92, 0x07, /// 0x60 + 0x02, 0xd1, 0x20, 0x22, 0x10, 0x43, 0x01, 0x25, + 0x36, 0x4b, 0x5a, 0x22, 0x1a, 0x74, 0x35, 0x4b, /// 0x70 + 0x20, 0x3b, 0x18, 0x72, 0x02, 0x20, 0x40, 0x1c, + 0x20, 0x28, 0xfc, 0xd3, 0x32, 0x4c, 0x00, 0x26, /// 0x80 + 0xa6, 0x81, 0x48, 0x88, 0xe2, 0x13, 0x82, 0x18, + 0x00, 0x2d, 0x09, 0xd0, 0x00, 0x20, 0x03, 0xe0, /// 0x90 + 0x45, 0x18, 0xad, 0x68, 0x15, 0x50, 0x00, 0x1d, + 0x8d, 0x88, 0x85, 0x42, 0xf8, 0xd8, 0x08, 0xe0, /// 0xa0 + 0x00, 0x20, 0x03, 0xe0, 0x45, 0x18, 0x2d, 0x7a, + 0x15, 0x54, 0x40, 0x1c, 0x8d, 0x88, 0x85, 0x42, /// 0xb0 + 0xf8, 0xd8, 0x1e, 0x72, 0x25, 0x48, 0xa0, 0x81, + 0x02, 0x20, 0x00, 0x24, 0x23, 0x46, 0x0b, 0xe0, /// 0xc0 + 0x5f, 0x18, 0x3e, 0x7a, 0xd5, 0x5c, 0xae, 0x42, + 0x05, 0xd0, 0x3d, 0x72, 0x00, 0x2c, 0x00, 0xd1, /// 0xd0 + 0x4b, 0x80, 0x04, 0x20, 0x64, 0x1c, 0x5b, 0x1c, + 0x8d, 0x88, 0x9d, 0x42, 0xf0, 0xd8, 0x8c, 0x80, /// 0xe0 + 0xf0, 0xbd, 0x1c, 0x49, 0x1a, 0x48, 0x08, 0x60, + 0x17, 0x48, 0x5a, 0x21, 0x40, 0x38, 0x01, 0x70, /// 0xf0 + 0x01, 0x21, 0x01, 0x71, 0x05, 0x21, 0x01, 0x72, + 0x17, 0x49, 0x81, 0x81, 0x08, 0x25, 0x10, 0x4f, /// 0x100 + 0x02, 0x26, 0x38, 0x78, 0x3c, 0x46, 0xc0, 0x07, + 0xfb, 0xd0, 0x60, 0x88, 0xa2, 0x88, 0x10, 0x18, /// 0x110 + 0x81, 0xb2, 0x00, 0x20, 0x04, 0xe0, 0x03, 0x19, + 0x1b, 0x7a, 0x59, 0x18, 0x89, 0xb2, 0x40, 0x1c, /// 0x120 + 0x82, 0x42, 0xf8, 0xd8, 0xe0, 0x88, 0x88, 0x42, + 0x01, 0xd0, 0x3d, 0x80, 0xe9, 0xe7, 0x00, 0x2a, /// 0x130 + 0x03, 0xd0, 0xff, 0xf7, 0x87, 0xff, 0x20, 0x80, + 0xe3, 0xe7, 0x3e, 0x80, 0xe1, 0xe7, 0x00, 0x00, /// 0x140 + 0x00, 0x04, 0x00, 0x20, 0x40, 0x5c, 0x00, 0x40, + 0x40, 0x30, 0x00, 0x40, 0xff, 0x01, 0x00, 0x00, /// 0x150 + 0xff, 0x0f, 0x00, 0x00, 0x80, 0xe1, 0x00, 0xe0, + 0x04, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +unsigned char idt_firmware_otp[] = { + /// ver 2.3.1.42 + 0x00, 0x08, 0x00, 0x20, 0xa9, 0x02, 0x00, 0x00, 0x71, 0x00, 0x00, 0x00, + 0x73, 0x00, 0x00, 0x00, /// 0x10 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /// 0x20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x75, 0x00, 0x00, 0x00, /// 0x30 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /// 0x40 + 0x81, 0x0e, 0x00, 0x00, 0x87, 0x0e, 0x00, 0x00, 0x8d, 0x0e, 0x00, 0x00, + 0x93, 0x0e, 0x00, 0x00, /// 0x50 + 0x99, 0x0e, 0x00, 0x00, 0x9f, 0x0e, 0x00, 0x00, 0xa5, 0x0e, 0x00, 0x00, + 0xab, 0x0e, 0x00, 0x00, /// 0x60 + 0xb1, 0x0e, 0x00, 0x00, 0xb7, 0x0e, 0x00, 0x00, 0xbd, 0x0e, 0x00, 0x00, + 0xc3, 0x0e, 0x00, 0x00, /// 0x70 + 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0x00, 0x20, + 0x00, 0x68, 0x80, 0xf3, /// 0x80 + 0x08, 0x88, 0x70, 0x47, 0xb6, 0x48, 0x00, 0x21, 0x01, 0x72, 0x41, 0x72, + 0x70, 0x47, 0x10, 0xb5, /// 0x90 + 0xb3, 0x4b, 0x1a, 0x7a, 0x5c, 0x7a, 0x51, 0x1c, 0x09, 0x07, 0x09, 0x0f, + 0x8c, 0x42, 0x01, 0xd1, /// 0xa0 + 0x01, 0x20, 0x10, 0xbd, 0xaf, 0x4c, 0x92, 0x00, 0x12, 0x19, 0xff, 0x32, + 0x01, 0x32, 0x90, 0x60, /// 0xb0 + 0x19, 0x72, 0x00, 0x20, 0x10, 0xbd, 0xab, 0x4e, 0x34, 0x46, 0xff, 0x34, + 0x41, 0x34, 0x21, 0x7a, /// 0xc0 + 0x60, 0x7a, 0x81, 0x42, 0x01, 0xd1, 0x30, 0xbf, 0xf9, 0xe7, 0x81, 0x00, + 0x89, 0x19, 0xff, 0x31, /// 0xd0 + 0x01, 0x31, 0x8d, 0x68, 0x00, 0x2d, 0x0c, 0xd0, 0x40, 0x1c, 0x00, 0x07, + 0x00, 0x0f, 0x60, 0x72, /// 0xe0 + 0xa8, 0x47, 0x00, 0x28, 0xeb, 0xd0, 0x72, 0xb6, 0x28, 0x46, 0xff, 0xf7, + 0xd0, 0xff, 0x62, 0xb6, /// 0xf0 + 0xe5, 0xe7, 0xff, 0xf7, 0xc7, 0xff, 0xe2, 0xe7, 0x9c, 0x49, 0x9b, 0x48, + 0x08, 0x60, 0xff, 0xf7, /// 0x100 + 0xbc, 0xff, 0x9b, 0x48, 0x5a, 0x21, 0x01, 0x70, 0x00, 0x24, 0x04, 0x71, + 0x09, 0x21, 0x01, 0x72, /// 0x110 + 0x98, 0x49, 0x81, 0x81, 0x0a, 0x21, 0x81, 0x82, 0x97, 0x49, 0x01, 0x83, + 0x08, 0x21, 0x81, 0x83, /// 0x120 + 0x93, 0x49, 0x02, 0x20, 0x20, 0x31, 0x08, 0x76, 0x94, 0x48, 0x84, 0x80, + 0x93, 0x49, 0x94, 0x48, /// 0x130 + 0x08, 0x80, 0x39, 0x20, 0x00, 0x02, 0x08, 0x82, 0x92, 0x48, 0x01, 0x26, + 0x06, 0x80, 0x81, 0x27, /// 0x140 + 0x07, 0x80, 0x90, 0x48, 0x90, 0x49, 0x20, 0x30, 0x01, 0x80, 0x90, 0x49, + 0x89, 0x78, 0x31, 0x43, /// 0x150 + 0x01, 0x71, 0x8f, 0x49, 0x40, 0x20, 0x08, 0x72, 0x20, 0x20, 0x08, 0x76, + 0x0c, 0x77, 0x8c, 0x49, /// 0x160 + 0x20, 0x31, 0x08, 0x70, 0x0c, 0x71, 0x08, 0x73, 0x08, 0x74, 0x8a, 0x48, + 0x81, 0xb2, 0x8a, 0x48, /// 0x170 + 0x00, 0xf0, 0xff, 0xfb, 0x30, 0x22, 0x89, 0x49, 0x89, 0x48, 0x00, 0xf0, + 0xea, 0xfb, 0x89, 0x4d, /// 0x180 + 0x0e, 0x20, 0xa8, 0x72, 0x07, 0x20, 0xe8, 0x73, 0x4b, 0x20, 0x00, 0x01, + 0x00, 0xf0, 0xdc, 0xfb, /// 0x190 + 0x85, 0x48, 0x06, 0x70, 0x07, 0x70, 0x84, 0x49, 0x3b, 0x20, 0x08, 0x71, + 0x3f, 0x20, 0x08, 0x81, /// 0x1a0 + 0x21, 0x20, 0x08, 0x70, 0x00, 0xf0, 0xec, 0xfb, 0x00, 0xf0, 0x6f, 0xfb, + 0x7f, 0x49, 0x06, 0x20, /// 0x1b0 + 0x08, 0x60, 0x6e, 0x49, 0x80, 0x39, 0x08, 0x60, 0x7d, 0x48, 0x06, 0x80, + 0x03, 0x21, 0x01, 0x80, /// 0x1c0 + 0x41, 0x21, 0x01, 0x76, 0x7b, 0x48, 0x00, 0xf0, 0x55, 0xf9, 0x7b, 0x48, + 0x04, 0x71, 0x7b, 0x48, /// 0x1d0 + 0x44, 0x70, 0x00, 0xf0, 0xd1, 0xfd, 0x2f, 0x46, 0x60, 0x3f, 0x78, 0x73, + 0x00, 0xf0, 0xe7, 0xfa, /// 0x1e0 + 0x75, 0x48, 0x01, 0x7a, 0x89, 0x07, 0xfc, 0xd5, 0x73, 0x49, 0x20, 0x31, + 0x0c, 0x70, 0x02, 0x21, /// 0x1f0 + 0x01, 0x72, 0x5b, 0x49, 0x10, 0x22, 0x4c, 0x31, 0x88, 0x18, 0x00, 0xf0, + 0xaa, 0xfb, 0x07, 0x22, /// 0x200 + 0x01, 0x21, 0x00, 0x20, 0x00, 0xf0, 0x20, 0xf9, 0x40, 0x03, 0x01, 0x0c, + 0x65, 0x48, 0x20, 0x38, /// 0x210 + 0x81, 0x85, 0x78, 0x7b, 0xc0, 0x07, 0x0d, 0xd0, 0x61, 0x48, 0x69, 0x49, + 0x81, 0x61, 0x48, 0x20, /// 0x220 + 0xe8, 0x72, 0x00, 0xf0, 0xab, 0xfa, 0x01, 0xf0, 0x07, 0xf9, 0x4d, 0x48, + 0x44, 0x30, 0x00, 0xf0, /// 0x230 + 0x21, 0xf9, 0x01, 0xe0, 0x00, 0xf0, 0xe8, 0xfa, 0x62, 0x48, 0x01, 0x7d, + 0x59, 0x4e, 0xa0, 0x3e, /// 0x240 + 0x31, 0x70, 0x01, 0x7c, 0x71, 0x70, 0x00, 0x7e, 0xb0, 0x70, 0x02, 0x20, + 0xf0, 0x70, 0xff, 0x20, /// 0x250 + 0x02, 0x30, 0x70, 0x60, 0x5c, 0x48, 0xf0, 0x61, 0x0d, 0x20, 0xb8, 0x72, + 0x30, 0x46, 0x01, 0x27, /// 0x260 + 0x60, 0x30, 0x87, 0x70, 0x00, 0xf0, 0xa8, 0xfd, 0xa8, 0x73, 0x00, 0xf0, + 0x51, 0xf9, 0x57, 0x48, /// 0x270 + 0x07, 0x70, 0x81, 0x21, 0x01, 0x70, 0x0d, 0x21, 0x01, 0x70, 0x54, 0x4a, + 0x95, 0x21, 0x20, 0x32, /// 0x280 + 0x11, 0x80, 0xff, 0x21, 0x81, 0x82, 0x03, 0x21, 0x09, 0x02, 0x01, 0x82, + 0x04, 0x71, 0x47, 0x49, /// 0x290 + 0x61, 0x20, 0x08, 0x60, 0x35, 0x49, 0x80, 0x39, 0x08, 0x60, 0x4d, 0x48, + 0x30, 0x87, 0x40, 0x48, /// 0x2a0 + 0x4c, 0x49, 0x41, 0x60, 0xff, 0xf7, 0x07, 0xff, 0x08, 0x20, 0x00, 0xf0, + 0x4d, 0xfb, 0x30, 0x48, /// 0x2b0 + 0x40, 0x30, 0x01, 0x78, 0x49, 0x06, 0xfc, 0xd4, 0xff, 0xf7, 0x1e, 0xff, + 0x30, 0xb5, 0x28, 0x4c, /// 0x2c0 + 0x38, 0x4d, 0x40, 0x3c, 0x20, 0x68, 0x40, 0x1c, 0x20, 0x3d, 0x20, 0x60, + 0x28, 0x78, 0x80, 0x07, /// 0x2d0 + 0x04, 0xd4, 0x72, 0xb6, 0x60, 0x68, 0xff, 0xf7, 0xda, 0xfe, 0x62, 0xb6, + 0x28, 0x78, 0x40, 0x07, /// 0x2e0 + 0x0a, 0xd5, 0x1f, 0x48, 0x20, 0x30, 0x81, 0x7d, 0xc0, 0x7d, 0x81, 0x42, + 0x04, 0xd0, 0x72, 0xb6, /// 0x2f0 + 0x39, 0x48, 0xff, 0xf7, 0xcc, 0xfe, 0x62, 0xb6, 0x72, 0xb6, 0xa0, 0x6f, + 0xff, 0xf7, 0xc7, 0xfe, /// 0x300 + 0x62, 0xb6, 0x00, 0x20, 0x30, 0xbd, 0x70, 0xb5, 0x00, 0x25, 0x27, 0x4c, + 0x08, 0x26, 0x0a, 0xe0, /// 0x310 + 0x20, 0x78, 0x30, 0x43, 0x20, 0x70, 0x6d, 0x1c, 0x0a, 0x2d, 0x01, 0xd3, + 0xff, 0xf7, 0xec, 0xfe, /// 0x320 + 0x14, 0x20, 0x00, 0xf0, 0x11, 0xfb, 0x20, 0x78, 0x00, 0x07, 0xf1, 0xd4, + 0x15, 0x48, 0x20, 0x30, /// 0x330 + 0x01, 0x88, 0xc9, 0x04, 0x11, 0xd5, 0x0a, 0x49, 0x40, 0x39, 0x0a, 0x68, + 0x80, 0x31, 0x09, 0x6e, /// 0x340 + 0x51, 0x1a, 0x02, 0x15, 0x91, 0x42, 0x08, 0xdb, 0x01, 0x88, 0x82, 0x14, + 0x91, 0x43, 0x01, 0x80, /// 0x350 + 0x07, 0x48, 0x01, 0x8b, 0x42, 0x14, 0x91, 0x43, 0x01, 0x83, 0x00, 0x20, + 0x70, 0xbd, 0x00, 0x00, /// 0x360 + 0x70, 0x02, 0x00, 0x20, 0x30, 0x01, 0x00, 0x20, 0xff, 0x0f, 0x00, 0x00, + 0x80, 0xe1, 0x00, 0xe0, /// 0x370 + 0x00, 0x30, 0x00, 0x40, 0x05, 0x1d, 0x00, 0x00, 0x3b, 0x23, 0x00, 0x00, + 0x00, 0x34, 0x00, 0x40, /// 0x380 + 0x01, 0x0a, 0x00, 0x00, 0x00, 0x38, 0x00, 0x40, 0x0e, 0x30, 0x00, 0x00, + 0x60, 0x47, 0x00, 0x00, /// 0x390 + 0x00, 0x6c, 0x00, 0x40, 0xc8, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, + 0xe4, 0x14, 0x00, 0x00, /// 0x3a0 + 0x00, 0x01, 0x00, 0x20, 0xa0, 0x00, 0x00, 0x20, 0x00, 0x3c, 0x00, 0x40, + 0x80, 0xe2, 0x00, 0xe0, /// 0x3b0 + 0x00, 0x44, 0x00, 0x40, 0xdc, 0x14, 0x00, 0x00, 0x00, 0x60, 0x00, 0x40, + 0x70, 0x03, 0x00, 0x20, /// 0x3c0 + 0xff, 0x0f, 0x00, 0x00, 0x60, 0x58, 0x00, 0x40, 0x46, 0x01, 0x03, 0x02, + 0x00, 0x64, 0x00, 0x40, /// 0x3d0 + 0x07, 0x40, 0x00, 0x00, 0x71, 0x10, 0x00, 0x00, 0x0d, 0x0e, 0x00, 0x00, + 0x70, 0xb5, 0xf7, 0x49, /// 0x3e0 + 0x8a, 0x88, 0xd2, 0x43, 0x92, 0x07, 0x06, 0xd0, 0xf5, 0x4a, 0x92, 0x7f, + 0x32, 0x2a, 0x02, 0xd3, /// 0x3f0 + 0x40, 0x09, 0x00, 0x23, 0x03, 0xe0, 0xc2, 0x00, 0x10, 0x1a, 0xc0, 0x09, + 0x01, 0x23, 0x3c, 0x28, /// 0x400 + 0x01, 0xd2, 0x3c, 0x20, 0x02, 0xe0, 0xff, 0x28, 0x00, 0xd9, 0xff, 0x20, + 0x0a, 0x8a, 0xed, 0x4c, /// 0x410 + 0x12, 0x0a, 0xc0, 0x1e, 0x82, 0x42, 0x15, 0xd0, 0x00, 0x2b, 0x02, 0xd1, + 0x25, 0x79, 0x01, 0x2d, /// 0x420 + 0x03, 0xd0, 0x55, 0x1d, 0xa8, 0x42, 0x00, 0xd9, 0x28, 0x46, 0x0a, 0x8a, + 0x40, 0x25, 0x2a, 0x43, /// 0x430 + 0x0a, 0x82, 0x0a, 0x8a, 0x4f, 0x26, 0x32, 0x40, 0x00, 0x02, 0x02, 0x43, + 0x0a, 0x82, 0x08, 0x8a, /// 0x440 + 0xa8, 0x43, 0x08, 0x82, 0x23, 0x71, 0x70, 0xbd, 0x70, 0xb5, 0x00, 0x23, + 0xde, 0x4d, 0x0b, 0xe0, /// 0x450 + 0x44, 0x00, 0x64, 0x19, 0xff, 0x34, 0x81, 0x34, 0xa4, 0x8b, 0x26, 0x0b, + 0x96, 0x42, 0x07, 0xd1, /// 0x460 + 0x24, 0x05, 0x24, 0x0d, 0xe3, 0x18, 0x40, 0x18, 0x08, 0x28, 0xf1, 0xd3, + 0x18, 0x46, 0x70, 0xbd, /// 0x470 + 0xd6, 0x48, 0x70, 0xbd, 0x10, 0xb5, 0xd6, 0x4a, 0x00, 0x21, 0x11, 0x70, + 0xd1, 0x4b, 0x01, 0x21, /// 0x480 + 0x40, 0x3b, 0x59, 0x70, 0xd3, 0x49, 0x03, 0x88, 0x8b, 0x80, 0x43, 0x88, + 0x0b, 0x81, 0x83, 0x88, /// 0x490 + 0x8b, 0x81, 0xc0, 0x88, 0x08, 0x82, 0xb4, 0x20, 0x10, 0x70, 0xca, 0x48, + 0xf4, 0x38, 0x10, 0x81, /// 0x4a0 + 0x07, 0x20, 0x90, 0x80, 0xca, 0x48, 0x02, 0x22, 0x20, 0x38, 0x02, 0x72, + 0x03, 0x79, 0x72, 0xb6, /// 0x4b0 + 0x13, 0x43, 0x03, 0x71, 0x62, 0xb6, 0x11, 0x20, 0x08, 0x80, 0x10, 0xbd, + 0x01, 0x88, 0x42, 0x88, /// 0x4c0 + 0x51, 0x18, 0x82, 0x88, 0xc0, 0x88, 0x51, 0x18, 0x40, 0x18, 0xc3, 0x49, + 0x00, 0x22, 0x8a, 0x5e, /// 0x4d0 + 0x80, 0x10, 0x80, 0x1a, 0x00, 0xd5, 0x00, 0x20, 0x70, 0x47, 0xc0, 0x49, + 0x4a, 0x14, 0x0b, 0x8b, /// 0x4e0 + 0x00, 0x28, 0x05, 0xd0, 0x93, 0x43, 0x0b, 0x83, 0x03, 0x28, 0x03, 0xd9, + 0x00, 0x22, 0x07, 0xe0, /// 0x4f0 + 0x13, 0x43, 0x0b, 0x83, 0x03, 0x21, 0x48, 0x40, 0x01, 0x21, 0x40, 0x03, + 0x09, 0x03, 0x42, 0x18, /// 0x500 + 0xb7, 0x48, 0x01, 0x88, 0x07, 0x23, 0x1b, 0x03, 0x99, 0x43, 0x11, 0x43, + 0x01, 0x80, 0x70, 0x47, /// 0x510 + 0xf8, 0xb5, 0xb2, 0x48, 0x00, 0x8b, 0x47, 0x26, 0xc0, 0x04, 0x36, 0x02, + 0xc1, 0x0e, 0xb5, 0x8a, /// 0x520 + 0x30, 0x8b, 0x4f, 0x1c, 0x2c, 0x1a, 0xaf, 0x48, 0x21, 0x46, 0x78, 0x43, + 0x00, 0xf0, 0x9e, 0xff, /// 0x530 + 0xa4, 0x49, 0xc8, 0x22, 0x40, 0x39, 0x00, 0x91, 0x88, 0x87, 0x28, 0x46, + 0x21, 0x46, 0x50, 0x43, /// 0x540 + 0x00, 0xf0, 0xaa, 0xff, 0xff, 0x21, 0x91, 0x31, 0x08, 0x1a, 0x00, 0x99, + 0xc8, 0x87, 0xf5, 0x8b, /// 0x550 + 0xf0, 0x8a, 0x29, 0x1a, 0xa4, 0x48, 0x78, 0x43, 0x00, 0xf0, 0x88, 0xff, + 0x99, 0x4c, 0x80, 0xb2, /// 0x560 + 0x20, 0x80, 0x39, 0x46, 0x15, 0x22, 0x68, 0x43, 0x51, 0x43, 0x00, 0xf0, + 0x7f, 0xff, 0x19, 0x21, /// 0x570 + 0x80, 0x09, 0x49, 0x01, 0x08, 0x1a, 0x00, 0xb2, 0x8d, 0x21, 0x48, 0x43, + 0xc1, 0x17, 0x09, 0x0e, /// 0x580 + 0x08, 0x18, 0x00, 0x12, 0x60, 0x80, 0xf8, 0xbd, 0x70, 0xb5, 0x05, 0x46, + 0x93, 0x48, 0x00, 0x8b, /// 0x590 + 0x8c, 0x4c, 0xc0, 0x04, 0x40, 0x3c, 0x61, 0x7a, 0xc0, 0x0e, 0x81, 0x42, + 0x02, 0xd0, 0x60, 0x72, /// 0x5a0 + 0xff, 0xf7, 0xb6, 0xff, 0x91, 0x48, 0x85, 0x42, 0x03, 0xd8, 0x3e, 0x22, + 0xa1, 0x8f, 0xa2, 0x5e, /// 0x5b0 + 0x1f, 0xe0, 0x8e, 0x49, 0x83, 0x48, 0x40, 0x31, 0x8d, 0x42, 0x03, 0xd3, + 0x02, 0x22, 0x01, 0x88, /// 0x5c0 + 0x82, 0x5e, 0x16, 0xe0, 0x89, 0x49, 0xa3, 0x8f, 0x49, 0x42, 0x6a, 0x18, + 0x01, 0x88, 0xc9, 0x1a, /// 0x5d0 + 0x51, 0x43, 0xce, 0x17, 0xb6, 0x0e, 0x71, 0x18, 0x89, 0x11, 0xc9, 0x18, + 0x02, 0x26, 0x3e, 0x23, /// 0x5e0 + 0x86, 0x5f, 0xe3, 0x5e, 0xf0, 0x1a, 0x50, 0x43, 0xc2, 0x17, 0x92, 0x0e, + 0x10, 0x18, 0x80, 0x11, /// 0x5f0 + 0xc2, 0x18, 0x4d, 0x43, 0x28, 0x0c, 0x80, 0x18, 0x00, 0xd5, 0x00, 0x20, + 0x70, 0xbd, 0xf8, 0xb5, /// 0x600 + 0x02, 0x22, 0x04, 0x21, 0x00, 0x20, 0xff, 0xf7, 0x1f, 0xff, 0x6e, 0x4d, + 0x6e, 0x4e, 0x20, 0x3d, /// 0x610 + 0xa9, 0x79, 0x09, 0x27, 0x49, 0x00, 0xc0, 0x03, 0x89, 0x19, 0xbf, 0x01, + 0x00, 0x0c, 0xc9, 0x19, /// 0x620 + 0x88, 0x81, 0x01, 0x22, 0x04, 0x21, 0x10, 0x46, 0xff, 0xf7, 0x0e, 0xff, + 0xa9, 0x79, 0xc0, 0x03, /// 0x630 + 0x49, 0x00, 0x89, 0x19, 0x00, 0x0c, 0xc9, 0x19, 0x88, 0x83, 0x03, 0x22, + 0x08, 0x21, 0x10, 0x46, /// 0x640 + 0xff, 0xf7, 0x02, 0xff, 0xa9, 0x79, 0x0f, 0x22, 0x49, 0x00, 0x89, 0x19, + 0xc9, 0x19, 0x88, 0x82, /// 0x650 + 0x04, 0x21, 0x02, 0x20, 0xff, 0xf7, 0xf8, 0xfe, 0xc0, 0x03, 0x01, 0x0c, + 0xa8, 0x79, 0x40, 0x00, /// 0x660 + 0x82, 0x19, 0x05, 0x20, 0xc0, 0x01, 0x10, 0x18, 0x81, 0x81, 0x04, 0x22, + 0x08, 0x21, 0x07, 0x20, /// 0x670 + 0xff, 0xf7, 0xea, 0xfe, 0x52, 0x4c, 0x20, 0x34, 0x23, 0x46, 0xe0, 0x80, + 0x40, 0x3b, 0x98, 0x69, /// 0x680 + 0x41, 0x00, 0x58, 0x69, 0xc2, 0x0f, 0x11, 0x43, 0x99, 0x61, 0x41, 0x00, + 0xa8, 0x79, 0x42, 0x00, /// 0x690 + 0x92, 0x19, 0xd2, 0x19, 0x12, 0x7b, 0x40, 0x1c, 0xd2, 0x07, 0xd2, 0x0f, + 0x11, 0x43, 0x80, 0x07, /// 0x6a0 + 0x80, 0x0f, 0x59, 0x61, 0xa8, 0x71, 0x28, 0x46, 0x14, 0x38, 0xff, 0xf7, + 0x07, 0xff, 0x21, 0x46, /// 0x6b0 + 0x60, 0x31, 0x0e, 0x22, 0x8a, 0x56, 0x80, 0x18, 0x20, 0x80, 0x28, 0x1f, + 0xff, 0xf7, 0xfe, 0xfe, /// 0x6c0 + 0x60, 0x87, 0x28, 0x46, 0x0c, 0x38, 0xff, 0xf7, 0xf9, 0xfe, 0x98, 0x87, + 0x28, 0x46, 0x2c, 0x30, /// 0x6d0 + 0xff, 0xf7, 0xf4, 0xfe, 0x40, 0x08, 0x01, 0x01, 0x40, 0x18, 0x27, 0x46, + 0x58, 0x81, 0x40, 0x37, /// 0x6e0 + 0x38, 0x78, 0xc0, 0x06, 0x48, 0xd5, 0x60, 0x8f, 0xff, 0xf7, 0x4e, 0xff, + 0xa1, 0x88, 0x08, 0x1a, /// 0x6f0 + 0x00, 0xd5, 0x40, 0x42, 0xc8, 0x28, 0x3f, 0xdd, 0xa8, 0x79, 0x40, 0x1e, + 0x80, 0x07, 0x40, 0x0f, /// 0x700 + 0x81, 0x19, 0x09, 0x20, 0x80, 0x01, 0x08, 0x18, 0x2e, 0x49, 0x80, 0x8b, + 0x40, 0x39, 0x88, 0x83, /// 0x710 + 0xc8, 0x83, 0x08, 0x84, 0x48, 0x84, 0x60, 0x87, 0xff, 0xf7, 0x36, 0xff, + 0xa1, 0x88, 0x05, 0x46, /// 0x720 + 0xa9, 0x42, 0x25, 0xd9, 0x38, 0x78, 0xc0, 0x07, 0x22, 0xd1, 0x40, 0x2d, + 0x01, 0xd2, 0xff, 0xf7, /// 0x730 + 0xd4, 0xfe, 0x22, 0x49, 0x80, 0x2d, 0x02, 0xd2, 0x01, 0x20, 0x88, 0x80, + 0x03, 0xe0, 0xff, 0x20, /// 0x740 + 0x41, 0x30, 0x85, 0x42, 0x01, 0xd2, 0x00, 0x20, 0x0c, 0xe0, 0xff, 0x20, + 0xe1, 0x30, 0x85, 0x42, /// 0x750 + 0x01, 0xd2, 0x01, 0x20, 0x06, 0xe0, 0x05, 0x20, 0xc0, 0x01, 0x85, 0x42, + 0x01, 0xd2, 0x02, 0x20, /// 0x760 + 0x00, 0xe0, 0x03, 0x20, 0x0a, 0x88, 0xf0, 0x23, 0x9a, 0x43, 0x80, 0x01, + 0x02, 0x43, 0x0a, 0x80, /// 0x770 + 0x1f, 0x48, 0xa5, 0x80, 0x32, 0x21, 0x41, 0x66, 0x00, 0x20, 0xf8, 0xbd, + 0x1d, 0x48, 0x01, 0x78, /// 0x780 + 0x42, 0x22, 0x11, 0x43, 0x01, 0x70, 0x1c, 0x49, 0xc0, 0x14, 0x08, 0x60, + 0x1b, 0x49, 0x08, 0x60, /// 0x790 + 0x70, 0x47, 0x0b, 0x49, 0x20, 0x39, 0xca, 0x8e, 0x02, 0x43, 0x08, 0x8f, + 0x10, 0x40, 0xc8, 0x86, /// 0x7a0 + 0x04, 0xd0, 0x17, 0x48, 0x01, 0x7f, 0xfb, 0x22, 0x11, 0x40, 0x01, 0x77, + 0x70, 0x47, 0x15, 0x48, /// 0x7b0 + 0x81, 0x21, 0x01, 0x80, 0x00, 0x21, 0x01, 0x80, 0x70, 0x47, 0x00, 0x00, + 0x00, 0x34, 0x00, 0x40, /// 0x7c0 + 0x20, 0x00, 0x00, 0x20, 0xb0, 0x03, 0x00, 0x20, 0x30, 0x01, 0x00, 0x20, + 0xff, 0xff, 0x00, 0x00, /// 0x7d0 + 0x20, 0x60, 0x00, 0x40, 0x00, 0x44, 0x00, 0x40, 0x20, 0x47, 0x00, 0x00, + 0x00, 0x30, 0x00, 0x40, /// 0x7e0 + 0x20, 0x38, 0x00, 0x40, 0x00, 0x1a, 0x04, 0x00, 0x80, 0x92, 0x08, 0x00, + 0xda, 0x02, 0x00, 0x00, /// 0x7f0 + 0xb0, 0x02, 0x00, 0x20, 0x00, 0x3c, 0x00, 0x40, 0x80, 0xe2, 0x00, 0xe0, + 0x00, 0xe1, 0x00, 0xe0, /// 0x800 + 0x20, 0x6c, 0x00, 0x40, 0x00, 0x4c, 0x00, 0x40, 0x10, 0xb5, 0xff, 0x49, + 0x08, 0x20, 0x88, 0x83, /// 0x810 + 0xfe, 0x48, 0x00, 0x22, 0x82, 0x80, 0xfe, 0x4b, 0x03, 0x80, 0x39, 0x23, + 0x1b, 0x02, 0x03, 0x82, /// 0x820 + 0xfc, 0x48, 0x08, 0x83, 0xfc, 0x49, 0x81, 0x20, 0x08, 0x80, 0xfc, 0x48, + 0x0e, 0x21, 0x81, 0x72, /// 0x830 + 0x07, 0x21, 0xc1, 0x73, 0xf8, 0x48, 0xfa, 0x49, 0x20, 0x30, 0x01, 0x80, + 0xf9, 0x49, 0x01, 0x23, /// 0x840 + 0x89, 0x78, 0x19, 0x43, 0x01, 0x71, 0xf8, 0x49, 0x09, 0x20, 0x08, 0x70, + 0xff, 0xf7, 0xaf, 0xff, /// 0x850 + 0xf7, 0x48, 0xf6, 0x49, 0x41, 0x60, 0xf7, 0x49, 0x0b, 0x78, 0xfb, 0x24, + 0x23, 0x40, 0x0b, 0x70, /// 0x860 + 0xf5, 0x49, 0x81, 0x67, 0x01, 0x68, 0x80, 0x30, 0x01, 0x66, 0xec, 0x48, + 0x60, 0x38, 0x01, 0x46, /// 0x870 + 0x42, 0x73, 0x40, 0x39, 0x88, 0x8e, 0x40, 0x22, 0x90, 0x43, 0x20, 0x22, + 0x10, 0x43, 0x88, 0x86, /// 0x880 + 0x10, 0x46, 0xff, 0xf7, 0x86, 0xff, 0x00, 0x20, 0x10, 0xbd, 0xec, 0x48, + 0x00, 0x21, 0x01, 0x72, /// 0x890 + 0x41, 0x72, 0xeb, 0x48, 0x01, 0x21, 0x01, 0x80, 0x01, 0x15, 0x81, 0x80, + 0x0f, 0x21, 0x01, 0x80, /// 0x8a0 + 0x02, 0x22, 0x02, 0x81, 0x01, 0x83, 0x04, 0x21, 0x81, 0x82, 0x85, 0xe7, + 0xe5, 0x48, 0x01, 0x21, /// 0x8b0 + 0x01, 0x80, 0x02, 0x15, 0x82, 0x80, 0x2b, 0x22, 0x02, 0x80, 0x01, 0x81, + 0xe1, 0x49, 0x96, 0x22, /// 0x8c0 + 0x20, 0x31, 0x0a, 0x80, 0x7d, 0x22, 0x8a, 0x80, 0x0f, 0x21, 0x01, 0x83, + 0x08, 0x21, 0x81, 0x82, /// 0x8d0 + 0x72, 0xe7, 0x00, 0x28, 0x09, 0xd0, 0x00, 0x29, 0x07, 0xd0, 0x81, 0x42, + 0x01, 0xd9, 0x41, 0x1e, /// 0x8e0 + 0x89, 0xb2, 0xd8, 0x4a, 0x20, 0x32, 0x91, 0x80, 0x10, 0x80, 0x65, 0xe7, + 0x40, 0x1a, 0x10, 0xb5, /// 0x8f0 + 0x00, 0x23, 0x02, 0xb2, 0x00, 0x2a, 0x02, 0xda, 0x01, 0x23, 0x50, 0x42, + 0x02, 0xb2, 0xc7, 0x48, /// 0x900 + 0xa0, 0x38, 0xc4, 0x7c, 0x94, 0x42, 0x1e, 0xda, 0x19, 0x24, 0x64, 0x01, + 0xa2, 0x42, 0x0b, 0xdc, /// 0x910 + 0x01, 0x46, 0x09, 0x8a, 0x00, 0x2b, 0x01, 0xd0, 0x49, 0x1e, 0x00, 0xe0, + 0x49, 0x1c, 0x01, 0x82, /// 0x920 + 0x09, 0x04, 0x09, 0x0c, 0x08, 0xd0, 0x09, 0xe0, 0xff, 0x22, 0x15, 0x32, + 0x51, 0x43, 0xc6, 0x4a, /// 0x930 + 0x51, 0x1a, 0x89, 0x00, 0x09, 0x0c, 0xf2, 0xe7, 0x01, 0x21, 0x01, 0x82, + 0x8a, 0xb2, 0xc1, 0x89, /// 0x940 + 0x8a, 0x42, 0x00, 0xd9, 0x01, 0x82, 0x10, 0xbd, 0x00, 0xe0, 0x00, 0xbf, + 0x40, 0x1e, 0xfc, 0xd2, /// 0x950 + 0x32, 0xe7, 0x82, 0x18, 0x01, 0xe0, 0x08, 0xc9, 0x08, 0xc0, 0x90, 0x42, + 0xfb, 0xd3, 0x2b, 0xe7, /// 0x960 + 0x82, 0x18, 0x03, 0xe0, 0x0b, 0x78, 0x03, 0x70, 0x40, 0x1c, 0x49, 0x1c, + 0x90, 0x42, 0xf9, 0xd3, /// 0x970 + 0x22, 0xe7, 0x41, 0x18, 0x00, 0x22, 0x00, 0xe0, 0x04, 0xc0, 0x88, 0x42, + 0xfc, 0xd3, 0x1b, 0xe7, /// 0x980 + 0xb2, 0x48, 0x01, 0x21, 0x01, 0x70, 0xb1, 0x4a, 0x05, 0x21, 0x40, 0x32, + 0x11, 0x80, 0x00, 0x22, /// 0x990 + 0x02, 0x74, 0xae, 0x49, 0x20, 0x31, 0x0a, 0x74, 0xad, 0x4a, 0x8a, 0x81, + 0x13, 0x22, 0x0a, 0x70, /// 0x9a0 + 0x07, 0x21, 0x01, 0x72, 0x08, 0xe7, 0x9d, 0x4a, 0xa0, 0x3a, 0x11, 0x46, + 0x40, 0x31, 0xd0, 0x8e, /// 0x9b0 + 0xcb, 0x8a, 0x98, 0x43, 0xd0, 0x86, 0x00, 0x22, 0xca, 0x82, 0x00, 0x28, + 0x05, 0xd1, 0x9d, 0x48, /// 0x9c0 + 0x20, 0x38, 0x01, 0x7f, 0x04, 0x22, 0x11, 0x43, 0x01, 0x77, 0xf5, 0xe6, + 0x8f, 0x48, 0x00, 0x21, /// 0x9d0 + 0x80, 0x88, 0x00, 0x07, 0x00, 0xd5, 0x02, 0x21, 0x8b, 0x48, 0x80, 0x8b, + 0xc0, 0x04, 0x01, 0xd5, /// 0x9e0 + 0x01, 0x20, 0x01, 0x43, 0x9b, 0x48, 0x80, 0x89, 0xc0, 0x06, 0x01, 0xd5, + 0x04, 0x20, 0x01, 0x43, /// 0x9f0 + 0x8a, 0x4b, 0xa0, 0x3b, 0x9a, 0x8e, 0x50, 0x07, 0x40, 0x0f, 0x48, 0x40, + 0x04, 0xd0, 0xd2, 0x08, /// 0xa00 + 0xd2, 0x00, 0x0a, 0x43, 0x9a, 0x86, 0xc4, 0xe6, 0xd6, 0xe6, 0x02, 0x46, + 0x00, 0x20, 0x02, 0xe0, /// 0xa10 + 0x13, 0x78, 0x58, 0x40, 0x52, 0x1c, 0x49, 0x1e, 0xfa, 0xd2, 0xcd, 0xe6, + 0x08, 0x22, 0x01, 0x21, /// 0xa20 + 0x01, 0xe0, 0x09, 0x18, 0x40, 0x08, 0x52, 0x1e, 0xfb, 0xd2, 0xc8, 0x07, + 0xc0, 0x0f, 0xc3, 0xe6, /// 0xa30 + 0xf8, 0xb5, 0x89, 0x4c, 0x00, 0x26, 0x20, 0x46, 0xff, 0x30, 0xa1, 0x30, + 0x84, 0x46, 0x0c, 0x30, /// 0xa40 + 0x01, 0x27, 0xff, 0x34, 0x35, 0x46, 0xc1, 0x34, 0x00, 0x90, 0x60, 0x7a, + 0x00, 0x28, 0x0e, 0xd1, /// 0xa50 + 0x60, 0x46, 0xa1, 0x7a, 0x00, 0x7b, 0x81, 0x42, 0x06, 0xd2, 0x01, 0x20, + 0xb0, 0x40, 0x49, 0x1c, /// 0xa60 + 0x05, 0x43, 0xa1, 0x72, 0xb6, 0x1c, 0x36, 0xe0, 0x00, 0x20, 0xa0, 0x72, + 0x67, 0x72, 0x61, 0x7a, /// 0xa70 + 0x20, 0x7a, 0x81, 0x42, 0x1d, 0xd2, 0xa0, 0x7a, 0x00, 0x28, 0x1d, 0xd0, + 0x09, 0x28, 0x06, 0xd2, /// 0xa80 + 0x00, 0x9a, 0x40, 0x1e, 0x89, 0x5c, 0xc1, 0x40, 0xc8, 0x07, 0xc0, 0x0f, + 0x14, 0xe0, 0x09, 0x28, /// 0xa90 + 0x05, 0xd0, 0xff, 0x22, 0x01, 0x20, 0xa2, 0x72, 0x49, 0x1c, 0x61, 0x72, + 0x0c, 0xe0, 0x00, 0x98, /// 0xaa0 + 0x08, 0x5c, 0xff, 0xf7, 0xbb, 0xff, 0x61, 0x46, 0x09, 0x7b, 0x00, 0x29, + 0x04, 0xd1, 0x78, 0x40, /// 0xab0 + 0x02, 0xe0, 0x60, 0x7d, 0xa7, 0x75, 0x78, 0x40, 0x61, 0x7d, 0x79, 0x40, + 0x48, 0x40, 0x60, 0x75, /// 0xac0 + 0x40, 0x00, 0x08, 0x43, 0xb0, 0x40, 0x05, 0x43, 0xa0, 0x7a, 0xb6, 0x1c, + 0x40, 0x1c, 0xa0, 0x72, /// 0xad0 + 0xa0, 0x7d, 0x01, 0x28, 0x01, 0xd0, 0x10, 0x2e, 0xb7, 0xd3, 0x76, 0x1e, + 0x26, 0x75, 0x65, 0x82, /// 0xae0 + 0xf8, 0xbd, 0x70, 0xb5, 0x05, 0x46, 0x41, 0x1c, 0x54, 0x48, 0x53, 0x38, + 0xff, 0xf7, 0x8d, 0xff, /// 0xaf0 + 0x59, 0x49, 0x52, 0x4c, 0x49, 0x19, 0xff, 0x31, 0xa1, 0x31, 0x88, 0x73, + 0x40, 0x3c, 0xed, 0x1c, /// 0xb00 + 0x25, 0x72, 0x20, 0x7b, 0xe0, 0x72, 0x00, 0x20, 0x60, 0x72, 0xa0, 0x72, + 0x60, 0x75, 0x02, 0x26, /// 0xb10 + 0xa6, 0x75, 0xff, 0xf7, 0x8d, 0xff, 0x40, 0x48, 0x20, 0x30, 0x01, 0x88, + 0xc9, 0x04, 0x61, 0x7b, /// 0xb20 + 0x03, 0xd5, 0x20, 0x22, 0x11, 0x43, 0x61, 0x73, 0x07, 0xe0, 0xdf, 0x22, + 0x11, 0x40, 0x61, 0x73, /// 0xb30 + 0x01, 0x88, 0x01, 0x22, 0x12, 0x03, 0x11, 0x43, 0x01, 0x80, 0x34, 0x49, + 0x0a, 0x8a, 0x0c, 0x23, /// 0xb40 + 0x1a, 0x43, 0x0a, 0x82, 0x03, 0x88, 0x03, 0x21, 0x09, 0x02, 0x8b, 0x43, + 0x33, 0x49, 0x30, 0x25, /// 0xb50 + 0xca, 0x7a, 0x15, 0x40, 0x2d, 0x01, 0x2b, 0x43, 0x03, 0x80, 0x2f, 0x4d, + 0x3f, 0x4b, 0xab, 0x80, /// 0xb60 + 0x2e, 0x81, 0x00, 0x23, 0xdb, 0x43, 0xab, 0x81, 0x48, 0x23, 0x1a, 0x40, + 0x25, 0x32, 0x2a, 0x80, /// 0xb70 + 0x62, 0x8a, 0x2a, 0x82, 0x22, 0x7d, 0x2a, 0x75, 0xa2, 0x7b, 0x00, 0x2a, + 0x14, 0xd1, 0x0a, 0x46, /// 0xb80 + 0x60, 0x3a, 0x33, 0x4b, 0xd2, 0x8f, 0xb4, 0x3b, 0x9a, 0x42, 0x0d, 0xd9, + 0xca, 0x7b, 0x1f, 0x2a, /// 0xb90 + 0x01, 0xd9, 0x1f, 0x22, 0xca, 0x73, 0x02, 0x88, 0xc9, 0x7b, 0x52, 0x09, + 0x52, 0x01, 0x0a, 0x43, /// 0xba0 + 0x02, 0x80, 0x01, 0x79, 0x31, 0x43, 0x01, 0x71, 0xff, 0xf7, 0x42, 0xff, + 0xff, 0x20, 0x00, 0x02, /// 0xbb0 + 0xa8, 0x81, 0x70, 0xbd, 0x70, 0xb5, 0x00, 0x20, 0xff, 0xf7, 0x8f, 0xfc, + 0x1d, 0x49, 0x08, 0x78, /// 0xbc0 + 0xdf, 0x22, 0x10, 0x40, 0x08, 0x70, 0x15, 0x48, 0xef, 0x24, 0xa0, 0x38, + 0x82, 0x7c, 0x22, 0x40, /// 0xbd0 + 0x82, 0x74, 0x0d, 0x4a, 0x08, 0x23, 0x93, 0x83, 0x1d, 0x4b, 0xac, 0x3b, + 0x13, 0x83, 0x39, 0x22, /// 0xbe0 + 0x0a, 0x4b, 0x12, 0x02, 0x1a, 0x82, 0x00, 0x22, 0x9a, 0x80, 0x1d, 0x88, + 0xf0, 0x26, 0xb5, 0x43, /// 0xbf0 + 0x1d, 0x80, 0x12, 0x4b, 0xfb, 0x25, 0x40, 0x3b, 0x5e, 0x7b, 0x2e, 0x40, + 0x5e, 0x73, 0x0b, 0x78, /// 0xc00 + 0x2b, 0x40, 0x0b, 0x70, 0x82, 0x87, 0x2b, 0xe0, 0x00, 0x30, 0x00, 0x40, + 0x00, 0x34, 0x00, 0x40, /// 0xc10 + 0x01, 0x0a, 0x00, 0x00, 0x3b, 0x3b, 0x00, 0x00, 0x00, 0x38, 0x00, 0x40, + 0xa0, 0x00, 0x00, 0x20, /// 0xc20 + 0x0e, 0x30, 0x00, 0x00, 0x60, 0x47, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x40, + 0x07, 0x03, 0x00, 0x00, /// 0xc30 + 0x30, 0x02, 0x00, 0x20, 0x40, 0x6c, 0x00, 0x40, 0x3d, 0x15, 0x00, 0x00, + 0x30, 0x03, 0x00, 0x20, /// 0xc40 + 0x00, 0x4c, 0x00, 0x40, 0x00, 0x50, 0x00, 0x40, 0x55, 0x32, 0x34, 0x00, + 0x00, 0x54, 0x00, 0x40, /// 0xc50 + 0xe7, 0x03, 0x00, 0x00, 0x20, 0x48, 0x00, 0x40, 0x30, 0x01, 0x00, 0x20, + 0xdb, 0x05, 0x00, 0x00, /// 0xc60 + 0x01, 0x46, 0x40, 0x31, 0x8a, 0x87, 0x8a, 0x80, 0x40, 0x31, 0x0a, 0x78, + 0x22, 0x40, 0x0a, 0x70, /// 0xc70 + 0x81, 0x8e, 0x80, 0x22, 0x11, 0x43, 0x81, 0x86, 0x10, 0x46, 0xff, 0xf7, + 0x8a, 0xfd, 0x70, 0xbd, /// 0xc80 + 0x51, 0x4a, 0x10, 0x8b, 0xc0, 0x04, 0xc1, 0x0e, 0x50, 0x48, 0x80, 0x7a, + 0x40, 0x00, 0x40, 0x1c, /// 0xc90 + 0x1f, 0x28, 0x00, 0xdd, 0x1f, 0x20, 0x81, 0x42, 0x00, 0xd2, 0x48, 0x1c, + 0x11, 0x8b, 0x1f, 0x23, /// 0xca0 + 0x1b, 0x02, 0x99, 0x43, 0x00, 0x02, 0x01, 0x43, 0x11, 0x83, 0x49, 0x49, + 0x08, 0x88, 0x07, 0x22, /// 0xcb0 + 0x12, 0x02, 0x90, 0x43, 0x45, 0x4a, 0x20, 0x32, 0x92, 0x78, 0x52, 0x07, + 0x52, 0x0d, 0x10, 0x43, /// 0xcc0 + 0x08, 0x80, 0x42, 0x48, 0x60, 0x30, 0x81, 0x7a, 0x1f, 0x29, 0x01, 0xd9, + 0x1f, 0x21, 0x81, 0x72, /// 0xcd0 + 0x40, 0x49, 0x0a, 0x88, 0x80, 0x7a, 0x52, 0x09, 0x52, 0x01, 0x02, 0x43, + 0x0a, 0x80, 0x6b, 0xe5, /// 0xce0 + 0xf8, 0xb5, 0x41, 0x09, 0x3c, 0x4a, 0x00, 0x29, 0x0a, 0xd0, 0x20, 0x29, + 0x01, 0xdb, 0x1f, 0x21, /// 0xcf0 + 0x06, 0xe0, 0x93, 0x7b, 0x8b, 0x42, 0x01, 0xda, 0x49, 0x1e, 0x01, 0xe0, + 0x8b, 0x42, 0x00, 0xdd, /// 0xd00 + 0x91, 0x73, 0x47, 0x21, 0x09, 0x02, 0x0e, 0x22, 0x8a, 0x56, 0x30, 0x49, + 0x20, 0x39, 0x8e, 0x7f, /// 0xd10 + 0xc9, 0x7f, 0xb3, 0x00, 0x8f, 0x07, 0xbf, 0x0f, 0x39, 0x46, 0xd2, 0x18, + 0x1c, 0x31, 0x51, 0x18, /// 0xd20 + 0x29, 0x4a, 0x11, 0x82, 0x23, 0x36, 0x7d, 0x21, 0x70, 0x43, 0xc9, 0x00, + 0x00, 0xf0, 0x9e, 0xfb, /// 0xd30 + 0x26, 0x4c, 0x40, 0x34, 0xa1, 0x7c, 0x08, 0x1a, 0x04, 0xd4, 0xe1, 0x7c, + 0x40, 0x43, 0x41, 0x43, /// 0xd40 + 0x48, 0x11, 0x00, 0xe0, 0x00, 0x20, 0xe1, 0x8a, 0x0d, 0x18, 0xa0, 0x8a, + 0xa8, 0x42, 0x00, 0xd2, /// 0xd50 + 0x05, 0x46, 0x96, 0x2e, 0x00, 0xd1, 0x00, 0x25, 0xb0, 0x00, 0xc0, 0x19, + 0x80, 0x02, 0xd2, 0x21, /// 0xd60 + 0x00, 0xf0, 0x84, 0xfb, 0x1e, 0x21, 0x61, 0x56, 0x40, 0x19, 0x08, 0x18, + 0x1b, 0x49, 0x88, 0x42, /// 0xd70 + 0x00, 0xd9, 0x08, 0x46, 0x20, 0x82, 0xf8, 0xbd, 0x17, 0x48, 0x17, 0x49, + 0x10, 0xb5, 0xc0, 0x38, /// 0xd80 + 0x17, 0x4a, 0x48, 0x31, 0x13, 0x78, 0x5b, 0x06, 0x02, 0xd4, 0x03, 0x68, + 0x05, 0x2b, 0x01, 0xd3, /// 0xd90 + 0x00, 0x20, 0x10, 0xbd, 0x0b, 0x78, 0x05, 0x2b, 0xf4, 0xd9, 0x0f, 0x48, + 0x81, 0x8d, 0xc2, 0x8d, /// 0xda0 + 0x51, 0x18, 0x02, 0x8e, 0x40, 0x8e, 0x51, 0x18, 0x41, 0x18, 0x0e, 0x48, + 0x00, 0xf0, 0x5e, 0xfb, /// 0xdb0 + 0x06, 0x49, 0x08, 0x84, 0x01, 0x20, 0x10, 0xbd, 0x0b, 0x48, 0x0c, 0x4a, + 0x01, 0x89, 0x51, 0x1a, /// 0xdc0 + 0x00, 0x22, 0x82, 0x5e, 0x88, 0x18, 0xf7, 0xe4, 0x00, 0x30, 0x00, 0x40, + 0x40, 0x00, 0x00, 0x20, /// 0xdd0 + 0x00, 0x34, 0x00, 0x40, 0x20, 0x38, 0x00, 0x40, 0xf0, 0x02, 0x00, 0x20, + 0xff, 0x0f, 0x00, 0x00, /// 0xde0 + 0x00, 0x3c, 0x00, 0x40, 0x00, 0x70, 0x17, 0x00, 0x20, 0x47, 0x00, 0x00, + 0x31, 0x04, 0x00, 0x00, /// 0xdf0 + 0x1e, 0x49, 0x1f, 0x4b, 0x8a, 0x7d, 0x92, 0x00, 0xd2, 0x18, 0xff, 0x32, + 0x01, 0x32, 0xd0, 0x64, /// 0xe00 + 0x88, 0x7d, 0x40, 0x1c, 0x40, 0x07, 0x40, 0x0f, 0x88, 0x75, 0x70, 0x47, + 0x30, 0xb5, 0x19, 0x48, /// 0xe10 + 0x01, 0x79, 0x89, 0x06, 0x28, 0xd4, 0x18, 0x49, 0x40, 0x22, 0x0a, 0x70, + 0x80, 0x22, 0x0a, 0x74, /// 0xe20 + 0x12, 0x4a, 0x13, 0x4d, 0xd4, 0x7d, 0xa3, 0x00, 0x5b, 0x19, 0xff, 0x33, + 0x4d, 0x33, 0x0b, 0x83, /// 0xe30 + 0x04, 0x23, 0x8b, 0x82, 0x01, 0x23, 0x0b, 0x72, 0x0d, 0x79, 0x72, 0xb6, + 0x1d, 0x43, 0x0d, 0x71, /// 0xe40 + 0x64, 0x1c, 0x61, 0x07, 0x49, 0x0f, 0xd1, 0x75, 0x05, 0x21, 0x51, 0x75, + 0x62, 0xb6, 0x58, 0x21, /// 0xe50 + 0x01, 0x77, 0xff, 0x21, 0x81, 0x82, 0x09, 0x49, 0x01, 0x82, 0x30, 0x21, + 0x01, 0x71, 0x0f, 0x21, /// 0xe60 + 0x01, 0x70, 0x01, 0x79, 0x19, 0x43, 0x01, 0x71, 0x00, 0x20, 0x30, 0xbd, + 0x90, 0x02, 0x00, 0x20, /// 0xe70 + 0x30, 0x01, 0x00, 0x20, 0x00, 0x64, 0x00, 0x40, 0x00, 0x60, 0x00, 0x40, + 0xc6, 0x03, 0x00, 0x00, /// 0xe80 + 0x95, 0x48, 0x00, 0x68, 0x00, 0x47, 0x94, 0x48, 0x40, 0x68, 0x00, 0x47, + 0x92, 0x48, 0x80, 0x68, /// 0xe90 + 0x00, 0x47, 0x91, 0x48, 0xc0, 0x68, 0x00, 0x47, 0x8f, 0x48, 0x00, 0x69, + 0x00, 0x47, 0x8e, 0x48, /// 0xea0 + 0x40, 0x69, 0x00, 0x47, 0x8c, 0x48, 0x80, 0x69, 0x00, 0x47, 0x8b, 0x48, + 0xc0, 0x69, 0x00, 0x47, /// 0xeb0 + 0x89, 0x48, 0x00, 0x6a, 0x00, 0x47, 0x88, 0x48, 0x40, 0x6a, 0x00, 0x47, + 0x86, 0x48, 0x80, 0x6a, /// 0xec0 + 0x00, 0x47, 0x85, 0x48, 0xc0, 0x6a, 0x00, 0x47, 0xf8, 0xb5, 0x84, 0x48, + 0x02, 0x7a, 0x01, 0x79, /// 0xed0 + 0x0a, 0x40, 0x02, 0x72, 0xd1, 0x07, 0x19, 0xd0, 0x01, 0x79, 0x49, 0x08, + 0x49, 0x00, 0x01, 0x71, /// 0xee0 + 0x00, 0x21, 0x01, 0x74, 0x01, 0x70, 0x7e, 0x4c, 0x65, 0x7d, 0x7e, 0x49, + 0x02, 0x23, 0x05, 0x2d, /// 0xef0 + 0x09, 0xd0, 0x0e, 0x79, 0x04, 0x25, 0x2e, 0x43, 0x0e, 0x71, 0x0e, 0x8a, + 0xc1, 0x27, 0xbf, 0x00, /// 0xf00 + 0xbe, 0x43, 0x0e, 0x82, 0x65, 0x75, 0x0c, 0x79, 0x1c, 0x43, 0x0c, 0x71, + 0x91, 0x07, 0x10, 0xd5, /// 0xf10 + 0x01, 0x79, 0xfd, 0x22, 0x11, 0x40, 0x01, 0x71, 0x70, 0x48, 0x00, 0x24, + 0x20, 0x30, 0x04, 0x70, /// 0xf20 + 0x6f, 0x49, 0x10, 0x22, 0x2c, 0x31, 0x88, 0x18, 0xff, 0xf7, 0x13, 0xfd, + 0x6c, 0x48, 0xe0, 0x30, /// 0xf30 + 0x44, 0x70, 0xf8, 0xbd, 0xf8, 0xb5, 0x6b, 0x4c, 0xa0, 0x8a, 0x21, 0x8a, + 0x08, 0x40, 0xff, 0x21, /// 0xf40 + 0xa1, 0x82, 0xc6, 0x21, 0x06, 0x46, 0xff, 0x22, 0x0e, 0x40, 0x67, 0x4d, + 0x6d, 0x32, 0x11, 0x1d, /// 0xf50 + 0x52, 0x59, 0x49, 0x5b, 0xff, 0x35, 0x02, 0x23, 0x61, 0x35, 0x00, 0x2e, + 0x25, 0xd0, 0xc4, 0x26, /// 0xf60 + 0x30, 0x40, 0x00, 0x26, 0x00, 0x28, 0x08, 0xd0, 0x20, 0x79, 0x18, 0x43, + 0x20, 0x71, 0x20, 0x20, /// 0xf70 + 0xff, 0xf7, 0xea, 0xfc, 0x06, 0x20, 0x68, 0x75, 0x07, 0xe0, 0x68, 0x7d, + 0x04, 0x28, 0x03, 0xd1, /// 0xf80 + 0x20, 0x7b, 0x51, 0x18, 0x20, 0x39, 0xc8, 0x77, 0x6e, 0x75, 0x0d, 0x20, + 0x20, 0x70, 0x03, 0x20, /// 0xf90 + 0x00, 0x02, 0x20, 0x82, 0xfc, 0x20, 0x20, 0x77, 0x26, 0x71, 0x50, 0x48, + 0x06, 0x70, 0x06, 0x74, /// 0xfa0 + 0x01, 0x79, 0x49, 0x08, 0x49, 0x00, 0x01, 0x71, 0xf8, 0xbd, 0x4d, 0x4e, + 0xc7, 0x07, 0x20, 0x3e, /// 0xfb0 + 0x76, 0x8e, 0x00, 0x2f, 0x03, 0xd0, 0x30, 0x0a, 0x20, 0x73, 0x6b, 0x75, + 0xf8, 0xbd, 0xc0, 0x06, /// 0xfc0 + 0xfc, 0xd5, 0x68, 0x7d, 0x02, 0x28, 0x12, 0xd0, 0x21, 0x20, 0x20, 0x71, + 0xff, 0x20, 0xc3, 0x30, /// 0xfd0 + 0x20, 0x82, 0x42, 0x48, 0x40, 0x23, 0x03, 0x70, 0x90, 0x23, 0x03, 0x74, + 0x02, 0x83, 0x89, 0x1e, /// 0xfe0 + 0x81, 0x82, 0x01, 0x21, 0x01, 0x72, 0x02, 0x79, 0x0a, 0x43, 0x02, 0x71, + 0xf8, 0xbd, 0x26, 0x73, /// 0xff0 + 0x03, 0x20, 0x68, 0x75, 0xf8, 0xbd, 0x3d, 0x49, 0x81, 0x20, 0x08, 0x80, + 0x70, 0x47, 0x70, 0xb5, /// 0x1000 + 0x3a, 0x4b, 0x30, 0x20, 0x18, 0x76, 0x36, 0x48, 0x00, 0x24, 0x60, 0x30, + 0x81, 0x7d, 0x00, 0x29, /// 0x1010 + 0x0a, 0xd0, 0x42, 0x8a, 0x1a, 0x82, 0x02, 0x7d, 0x1a, 0x75, 0x01, 0x29, + 0x02, 0xd0, 0xff, 0xf7, /// 0x1020 + 0x07, 0xfd, 0x70, 0xbd, 0x84, 0x75, 0x70, 0xbd, 0x30, 0x4a, 0x20, 0x32, + 0x11, 0x79, 0xfd, 0x25, /// 0x1030 + 0x29, 0x40, 0x11, 0x71, 0x2e, 0x49, 0x8d, 0x7a, 0x1f, 0x2d, 0x01, 0xd9, + 0x1f, 0x25, 0x8d, 0x72, /// 0x1040 + 0x15, 0x88, 0x89, 0x7a, 0x6d, 0x09, 0x6d, 0x01, 0x0d, 0x43, 0x15, 0x80, + 0x01, 0x21, 0x19, 0x80, /// 0x1050 + 0x04, 0x72, 0x28, 0x48, 0x01, 0x8a, 0x0c, 0x22, 0x91, 0x43, 0x01, 0x82, + 0x70, 0xbd, 0x20, 0x48, /// 0x1060 + 0x60, 0x38, 0x01, 0x68, 0x49, 0x1c, 0x01, 0x60, 0x23, 0x49, 0x07, 0x20, + 0x08, 0x72, 0x70, 0x47, /// 0x1070 + 0x10, 0xb5, 0x21, 0x4c, 0x20, 0x7a, 0x80, 0x07, 0x02, 0xd5, 0x20, 0x48, + 0xff, 0xf7, 0x07, 0xf8, /// 0x1080 + 0x07, 0x20, 0x20, 0x72, 0x10, 0xbd, 0x10, 0xb5, 0x1d, 0x49, 0x8b, 0x89, + 0x14, 0x48, 0x16, 0x4c, /// 0x1090 + 0xa0, 0x30, 0x02, 0x7a, 0x52, 0x00, 0x12, 0x19, 0xff, 0x32, 0xc1, 0x32, + 0x13, 0x85, 0x02, 0x7a, /// 0x10a0 + 0x52, 0x1c, 0x12, 0x07, 0x12, 0x0f, 0x02, 0x72, 0x0f, 0x20, 0x08, 0x83, + 0x10, 0xbd, 0x15, 0x49, /// 0x10b0 + 0x0f, 0x20, 0x08, 0x83, 0x70, 0x47, 0x10, 0xb5, 0x13, 0x48, 0x01, 0x78, + 0x49, 0x06, 0x04, 0xd5, /// 0x10c0 + 0x41, 0x21, 0x01, 0x70, 0x11, 0x48, 0xfe, 0xf7, 0xe2, 0xff, 0x11, 0x48, + 0x01, 0x79, 0xc9, 0x07, /// 0x10d0 + 0x01, 0xd0, 0x10, 0x21, 0x01, 0x71, 0x10, 0xbd, 0x00, 0x01, 0x00, 0x20, + 0x00, 0x60, 0x00, 0x40, /// 0x10e0 + 0x90, 0x02, 0x00, 0x20, 0x00, 0x64, 0x00, 0x40, 0x30, 0x01, 0x00, 0x20, + 0x00, 0x38, 0x00, 0x40, /// 0x10f0 + 0xa0, 0x00, 0x00, 0x20, 0x00, 0x34, 0x00, 0x40, 0x00, 0x54, 0x00, 0x40, + 0xbd, 0x02, 0x00, 0x00, /// 0x1100 + 0x00, 0x4c, 0x00, 0x40, 0x00, 0x50, 0x00, 0x40, 0x00, 0x3c, 0x00, 0x40, + 0x09, 0x08, 0x00, 0x00, /// 0x1110 + 0x40, 0x30, 0x00, 0x40, 0x00, 0x21, 0x41, 0x61, 0x81, 0x61, 0xbb, 0x4a, + 0x02, 0x60, 0xc1, 0x61, /// 0x1120 + 0xba, 0x4a, 0x42, 0x60, 0xb8, 0x4a, 0xd2, 0x43, 0x82, 0x60, 0xb8, 0x4a, + 0xd2, 0x43, 0xc2, 0x60, /// 0x1130 + 0xb7, 0x4a, 0x01, 0x66, 0x02, 0x61, 0x41, 0x66, 0x70, 0x47, 0xf0, 0xb5, + 0xb5, 0x4b, 0x84, 0x46, /// 0x1140 + 0x0f, 0xcb, 0xd9, 0xb0, 0x6c, 0x46, 0x0f, 0xc4, 0x00, 0x23, 0x09, 0xa8, + 0x9a, 0x00, 0x61, 0x46, /// 0x1150 + 0x54, 0x18, 0x20, 0x34, 0x21, 0x78, 0x5b, 0x1c, 0x09, 0x06, 0x81, 0x50, + 0x65, 0x78, 0x2d, 0x04, /// 0x1160 + 0x29, 0x43, 0x81, 0x50, 0xa5, 0x78, 0x2d, 0x02, 0x29, 0x43, 0x81, 0x50, + 0xe4, 0x78, 0x21, 0x43, /// 0x1170 + 0x81, 0x50, 0x10, 0x2b, 0xea, 0xdb, 0x10, 0x21, 0x8c, 0x00, 0x22, 0x18, + 0x80, 0x3a, 0x15, 0x6e, /// 0x1180 + 0x53, 0x6f, 0x6b, 0x40, 0x95, 0x6c, 0x12, 0x6c, 0x55, 0x40, 0x6b, 0x40, + 0x1f, 0x22, 0xd3, 0x41, /// 0x1190 + 0x49, 0x1c, 0x03, 0x51, 0x50, 0x29, 0xef, 0xdb, 0x61, 0x46, 0x0a, 0x68, + 0x08, 0x92, 0x49, 0x68, /// 0x11a0 + 0x63, 0x46, 0x07, 0x91, 0x9b, 0x68, 0x64, 0x46, 0x06, 0x93, 0xe4, 0x68, + 0x65, 0x46, 0x05, 0x94, /// 0x11b0 + 0x2d, 0x69, 0x00, 0x26, 0xb6, 0x46, 0x04, 0x95, 0x70, 0x46, 0x86, 0x00, + 0x09, 0xa8, 0x87, 0x59, /// 0x11c0 + 0x1b, 0x20, 0x16, 0x46, 0xc6, 0x41, 0xb8, 0x19, 0x0e, 0x46, 0x27, 0x46, + 0x1e, 0x40, 0x8f, 0x43, /// 0x11d0 + 0x3e, 0x43, 0x75, 0x19, 0x45, 0x19, 0x00, 0x98, 0x28, 0x18, 0x25, 0x46, + 0x1c, 0x46, 0x0b, 0x46, /// 0x11e0 + 0x02, 0x21, 0xcb, 0x41, 0x11, 0x46, 0x02, 0x46, 0x70, 0x46, 0x40, 0x1c, + 0x86, 0x46, 0x14, 0x28, /// 0x11f0 + 0xe2, 0xdb, 0x14, 0x20, 0x86, 0x46, 0x86, 0x00, 0x09, 0xa8, 0x87, 0x59, + 0x1b, 0x20, 0x16, 0x46, /// 0x1200 + 0xc6, 0x41, 0xb8, 0x19, 0x0e, 0x46, 0x5e, 0x40, 0x66, 0x40, 0x75, 0x19, + 0x45, 0x19, 0x01, 0x98, /// 0x1210 + 0x28, 0x18, 0x25, 0x46, 0x1c, 0x46, 0x0b, 0x46, 0x02, 0x21, 0xcb, 0x41, + 0x11, 0x46, 0x02, 0x46, /// 0x1220 + 0x70, 0x46, 0x40, 0x1c, 0x86, 0x46, 0x28, 0x28, 0xe5, 0xdb, 0x28, 0x20, + 0x86, 0x46, 0x86, 0x00, /// 0x1230 + 0x09, 0xa8, 0x87, 0x59, 0x1b, 0x20, 0x16, 0x46, 0xc6, 0x41, 0xbf, 0x19, + 0x1e, 0x46, 0x26, 0x43, /// 0x1240 + 0x18, 0x46, 0x0e, 0x40, 0x20, 0x40, 0x06, 0x43, 0x70, 0x19, 0x3d, 0x18, + 0x02, 0x98, 0x28, 0x18, /// 0x1250 + 0x25, 0x46, 0x1c, 0x46, 0x02, 0x23, 0xd9, 0x41, 0x0b, 0x46, 0x11, 0x46, + 0x02, 0x46, 0x70, 0x46, /// 0x1260 + 0x40, 0x1c, 0x86, 0x46, 0x3c, 0x28, 0xe2, 0xdb, 0x3c, 0x20, 0x86, 0x46, + 0x86, 0x00, 0x09, 0xa8, /// 0x1270 + 0x87, 0x59, 0x1b, 0x20, 0x16, 0x46, 0xc6, 0x41, 0xb8, 0x19, 0x0e, 0x46, + 0x5e, 0x40, 0x66, 0x40, /// 0x1280 + 0x75, 0x19, 0x45, 0x19, 0x03, 0x98, 0x28, 0x18, 0x25, 0x46, 0x1c, 0x46, + 0x02, 0x23, 0xd9, 0x41, /// 0x1290 + 0x0b, 0x46, 0x11, 0x46, 0x02, 0x46, 0x70, 0x46, 0x40, 0x1c, 0x86, 0x46, + 0x50, 0x28, 0xe5, 0xdb, /// 0x12a0 + 0x08, 0x98, 0x82, 0x18, 0x60, 0x46, 0x02, 0x60, 0x07, 0x98, 0x41, 0x18, + 0x60, 0x46, 0x41, 0x60, /// 0x12b0 + 0x06, 0x98, 0xc1, 0x18, 0x60, 0x46, 0x81, 0x60, 0x05, 0x98, 0x01, 0x19, + 0x60, 0x46, 0xc1, 0x60, /// 0x12c0 + 0x04, 0x98, 0x41, 0x19, 0x60, 0x46, 0x01, 0x61, 0x00, 0x21, 0xc1, 0x61, + 0x59, 0xb0, 0xf0, 0xbd, /// 0x12d0 + 0x70, 0xb5, 0x04, 0x46, 0xc0, 0x69, 0x25, 0x46, 0x41, 0x1c, 0x80, 0x22, + 0x20, 0x35, 0x00, 0x26, /// 0x12e0 + 0xe1, 0x61, 0x37, 0x28, 0x42, 0x55, 0x03, 0xdc, 0x13, 0xe0, 0x41, 0x1c, + 0xe1, 0x61, 0x46, 0x55, /// 0x12f0 + 0xe0, 0x69, 0x40, 0x28, 0xf9, 0xdb, 0x20, 0x46, 0xff, 0xf7, 0x1f, 0xff, + 0x02, 0xe0, 0x41, 0x1c, /// 0x1300 + 0xe1, 0x61, 0x46, 0x55, 0xe0, 0x69, 0x38, 0x28, 0xf9, 0xdb, 0x05, 0xe0, + 0x41, 0x1c, 0xe1, 0x61, /// 0x1310 + 0x46, 0x55, 0xe0, 0x69, 0x38, 0x28, 0xf9, 0xdb, 0xa1, 0x69, 0x20, 0x46, + 0x0a, 0x0e, 0x40, 0x30, /// 0x1320 + 0x02, 0x76, 0x0a, 0x0c, 0x42, 0x76, 0x0a, 0x0a, 0x82, 0x76, 0xc1, 0x76, + 0x61, 0x69, 0x0a, 0x0e, /// 0x1330 + 0x02, 0x77, 0x0a, 0x0c, 0x42, 0x77, 0x0a, 0x0a, 0x82, 0x77, 0xc1, 0x77, + 0x20, 0x46, 0xff, 0xf7, /// 0x1340 + 0xfc, 0xfe, 0x70, 0xbd, 0x30, 0xb5, 0x0d, 0x46, 0x04, 0x00, 0x08, 0xd0, + 0x00, 0x2d, 0x06, 0xd0, /// 0x1350 + 0x60, 0x6e, 0x00, 0x28, 0x04, 0xd1, 0x20, 0x6e, 0x00, 0x28, 0x02, 0xd0, + 0x10, 0xe0, 0x01, 0x20, /// 0x1360 + 0x30, 0xbd, 0x20, 0x46, 0xff, 0xf7, 0xb4, 0xff, 0x00, 0x20, 0x01, 0x46, + 0x22, 0x18, 0x20, 0x32, /// 0x1370 + 0x40, 0x1c, 0x11, 0x70, 0x40, 0x28, 0xf9, 0xdb, 0x61, 0x61, 0x01, 0x20, + 0xa1, 0x61, 0x20, 0x66, /// 0x1380 + 0x00, 0x20, 0x03, 0x22, 0x81, 0x08, 0x83, 0x07, 0x89, 0x00, 0x9b, 0x0f, + 0x61, 0x58, 0xd3, 0x1a, /// 0x1390 + 0xdb, 0x00, 0xd9, 0x40, 0x29, 0x54, 0x40, 0x1c, 0x14, 0x28, 0xf3, 0xdb, + 0x00, 0x20, 0x30, 0xbd, /// 0x13a0 + 0xf0, 0xb5, 0x15, 0x00, 0x0e, 0x46, 0x04, 0x46, 0x15, 0xd0, 0x00, 0x2c, + 0x07, 0xd0, 0x00, 0x2e, /// 0x13b0 + 0x05, 0xd0, 0x20, 0x6e, 0x00, 0x28, 0x04, 0xd0, 0x03, 0x20, 0x60, 0x66, + 0xf0, 0xbd, 0x01, 0x20, /// 0x13c0 + 0xf0, 0xbd, 0x60, 0x6e, 0x00, 0x28, 0xfb, 0xd1, 0x27, 0x46, 0x20, 0x37, + 0x6d, 0x1e, 0x02, 0xd3, /// 0x13d0 + 0x60, 0x6e, 0x00, 0x28, 0x01, 0xd0, 0x00, 0x20, 0xf0, 0xbd, 0xe0, 0x69, + 0x31, 0x78, 0x42, 0x1c, /// 0x13e0 + 0xe2, 0x61, 0xc1, 0x55, 0x60, 0x69, 0x08, 0x30, 0x60, 0x61, 0x05, 0xd1, + 0xa0, 0x69, 0x40, 0x1c, /// 0x13f0 + 0xa0, 0x61, 0x01, 0xd1, 0x01, 0x20, 0x60, 0x66, 0xe0, 0x69, 0x40, 0x28, + 0x02, 0xd1, 0x20, 0x46, /// 0x1400 + 0xff, 0xf7, 0x9b, 0xfe, 0x76, 0x1c, 0xe1, 0xe7, 0x01, 0x23, 0x45, 0x67, + 0x89, 0xab, 0xcd, 0xef, /// 0x1410 + 0xf0, 0xe1, 0xd2, 0xc3, 0x14, 0x15, 0x00, 0x00, 0x10, 0xb5, 0x06, 0x49, + 0x0c, 0x22, 0x0a, 0x73, /// 0x1420 + 0x19, 0x22, 0x4a, 0x73, 0x88, 0x73, 0x10, 0x20, 0x80, 0x31, 0xc8, 0x77, + 0x01, 0x20, 0xff, 0xf7, /// 0x1430 + 0x58, 0xfb, 0x10, 0xbd, 0xd0, 0x02, 0x00, 0x20, 0x10, 0xb5, 0x09, 0x48, + 0x07, 0x49, 0x41, 0x60, /// 0x1440 + 0x08, 0x49, 0x81, 0x67, 0x08, 0x22, 0x08, 0x49, 0x7c, 0x30, 0xff, 0xf7, + 0x82, 0xfa, 0x04, 0x48, /// 0x1450 + 0x08, 0x22, 0x05, 0x49, 0x84, 0x30, 0xff, 0xf7, 0x7c, 0xfa, 0x10, 0xbd, + 0xa5, 0x18, 0x00, 0x00, /// 0x1460 + 0x30, 0x02, 0x00, 0x20, 0x3d, 0x15, 0x00, 0x00, 0x64, 0x1b, 0x00, 0x00, + 0x30, 0xb5, 0x0b, 0x46, /// 0x1470 + 0x01, 0x46, 0x00, 0x20, 0x20, 0x22, 0x01, 0x24, 0x09, 0xe0, 0x0d, 0x46, + 0xd5, 0x40, 0x9d, 0x42, /// 0x1480 + 0x05, 0xd3, 0x1d, 0x46, 0x95, 0x40, 0x49, 0x1b, 0x25, 0x46, 0x95, 0x40, + 0x40, 0x19, 0x15, 0x46, /// 0x1490 + 0x52, 0x1e, 0x00, 0x2d, 0xf1, 0xdc, 0x30, 0xbd, 0x70, 0xb5, 0x00, 0x24, + 0x25, 0x46, 0x00, 0x28, /// 0x14a0 + 0x01, 0xda, 0x01, 0x24, 0x40, 0x42, 0x00, 0x29, 0x01, 0xda, 0x01, 0x25, + 0x49, 0x42, 0xff, 0xf7, /// 0x14b0 + 0xdd, 0xff, 0xac, 0x42, 0x00, 0xd0, 0x40, 0x42, 0x00, 0x2c, 0x00, 0xd0, + 0x49, 0x42, 0x70, 0xbd, /// 0x14c0 + 0x30, 0xb4, 0x74, 0x46, 0x64, 0x1e, 0x25, 0x78, 0x64, 0x1c, 0xab, 0x42, + 0x00, 0xd2, 0x1d, 0x46, /// 0x14d0 + 0x63, 0x5d, 0x5b, 0x00, 0xe3, 0x18, 0x30, 0xbc, 0x18, 0x47, 0x00, 0x00, + 0x07, 0x07, 0x07, 0x07, /// 0x14e0 + 0x07, 0x07, 0x07, 0x07, 0xc9, 0x0e, 0x00, 0x00, 0x5f, 0x10, 0x00, 0x00, + 0x87, 0x10, 0x00, 0x00, /// 0x14f0 + 0xaf, 0x10, 0x00, 0x00, 0x79, 0x00, 0x00, 0x00, 0x35, 0x0f, 0x00, 0x00, + 0xf7, 0x0f, 0x00, 0x00, /// 0x1500 + 0x79, 0x00, 0x00, 0x00, 0x79, 0x00, 0x00, 0x00, 0x79, 0x00, 0x00, 0x00, + 0x79, 0x00, 0x00, 0x00, /// 0x1510 + 0xb7, 0x10, 0x00, 0x00, 0x99, 0x79, 0x82, 0x5a, 0xa1, 0xeb, 0xd9, 0x6e, + 0xdc, 0xbc, 0x1b, 0x8f, /// 0x1520 + 0xd6, 0xc1, 0x62, 0xca, 0xfe, 0x48, 0x32, 0x21, 0x41, 0x66, 0x01, 0x46, + 0x08, 0x22, 0x40, 0x39, /// 0x1530 + 0x8a, 0x72, 0x40, 0x39, 0x09, 0x68, 0x32, 0x39, 0x81, 0x65, 0x70, 0x47, + 0xf8, 0xb5, 0xff, 0xf7, /// 0x1540 + 0x45, 0xfa, 0xf8, 0x4e, 0xf4, 0x89, 0x00, 0x2c, 0x6b, 0xd0, 0x00, 0x27, + 0x35, 0x46, 0xe0, 0x05, /// 0x1550 + 0x40, 0x35, 0xf7, 0x81, 0x00, 0x28, 0x0f, 0xda, 0xff, 0xf7, 0x2c, 0xfb, + 0x02, 0x20, 0xf2, 0x4a, /// 0x1560 + 0x28, 0x70, 0x5a, 0x21, 0x11, 0x70, 0xf0, 0x48, 0x10, 0x23, 0x40, 0x30, + 0x03, 0x70, 0x11, 0x70, /// 0x1570 + 0x07, 0x72, 0x80, 0x21, 0x01, 0x70, 0x54, 0xe0, 0xec, 0x48, 0x21, 0x04, + 0x04, 0xd5, 0x01, 0x8d, /// 0x1580 + 0x01, 0x22, 0x52, 0x02, 0x11, 0x43, 0x01, 0x85, 0xe1, 0x06, 0x04, 0xd5, + 0x01, 0x8d, 0xff, 0x22, /// 0x1590 + 0x01, 0x32, 0x11, 0x43, 0x01, 0x85, 0xe1, 0x07, 0x08, 0x22, 0x00, 0x29, + 0x02, 0xd0, 0x69, 0x78, /// 0x15a0 + 0x11, 0x43, 0x69, 0x70, 0xa1, 0x05, 0x15, 0xd5, 0xde, 0x49, 0x20, 0x39, + 0x8b, 0x79, 0x1b, 0x06, /// 0x15b0 + 0x06, 0xd5, 0x8f, 0x71, 0xcf, 0x71, 0x01, 0x8d, 0x01, 0x22, 0x11, 0x43, + 0x01, 0x85, 0x09, 0xe0, /// 0x15c0 + 0xda, 0x48, 0x0b, 0x7b, 0x00, 0x8d, 0x00, 0x2b, 0x0e, 0xd0, 0x20, 0x23, + 0x18, 0x43, 0xd7, 0x4b, /// 0x15d0 + 0x18, 0x85, 0xca, 0x71, 0xa0, 0x06, 0x01, 0xd5, 0xff, 0xf7, 0xe5, 0xf9, + 0x60, 0x06, 0x0b, 0xd5, /// 0x15e0 + 0x30, 0x7b, 0x5a, 0x28, 0x02, 0xd0, 0x07, 0xe0, 0x10, 0x23, 0xef, 0xe7, + 0x70, 0x7b, 0x40, 0x21, /// 0x15f0 + 0x08, 0x43, 0x70, 0x73, 0xce, 0x48, 0x80, 0x47, 0x20, 0x07, 0x01, 0xd5, + 0xff, 0xf7, 0x92, 0xff, /// 0x1600 + 0xa0, 0x07, 0x01, 0xd5, 0x00, 0xf0, 0xb0, 0xfd, 0x20, 0x06, 0x03, 0xd5, + 0xa8, 0x78, 0x01, 0x21, /// 0x1610 + 0x08, 0x43, 0xa8, 0x70, 0x60, 0x07, 0x03, 0xd5, 0xa8, 0x78, 0x20, 0x21, + 0x08, 0x43, 0xa8, 0x70, /// 0x1620 + 0x37, 0x73, 0x00, 0x20, 0xf8, 0xbd, 0xbe, 0x48, 0x10, 0xb5, 0x80, 0x38, + 0x01, 0x68, 0x80, 0x30, /// 0x1630 + 0x82, 0x6d, 0x43, 0x6e, 0x8a, 0x1a, 0x9a, 0x42, 0x0c, 0xdb, 0x81, 0x65, + 0x83, 0x21, 0x89, 0x00, /// 0x1640 + 0x81, 0x85, 0xb8, 0x48, 0x20, 0x38, 0xc1, 0x7e, 0xb5, 0x48, 0x20, 0x30, + 0x81, 0x73, 0x01, 0x20, /// 0x1650 + 0xff, 0xf7, 0x47, 0xfa, 0x10, 0xbd, 0xb3, 0x48, 0x10, 0xb5, 0x10, 0x22, + 0xb5, 0x49, 0x50, 0x30, /// 0x1660 + 0xff, 0xf7, 0x77, 0xf9, 0xaf, 0x48, 0x10, 0x22, 0xb3, 0x49, 0x28, 0x30, + 0xff, 0xf7, 0x71, 0xf9, /// 0x1670 + 0xac, 0x48, 0x19, 0x21, 0x20, 0x38, 0x02, 0x46, 0x81, 0x77, 0x40, 0x32, + 0xd1, 0x70, 0x00, 0x21, /// 0x1680 + 0xc1, 0x77, 0xa9, 0x49, 0x80, 0x20, 0x08, 0x82, 0x10, 0xbd, 0x10, 0xb5, + 0xff, 0xf7, 0xe3, 0xff, /// 0x1690 + 0xa4, 0x49, 0xf7, 0x22, 0x48, 0x7b, 0x10, 0x40, 0x48, 0x73, 0x08, 0x46, + 0xa7, 0x4a, 0x40, 0x30, /// 0x16a0 + 0xc2, 0x60, 0x82, 0x60, 0x9e, 0x48, 0xa6, 0x4a, 0x80, 0x30, 0x42, 0x81, + 0xff, 0x38, 0x01, 0x38, /// 0x16b0 + 0x02, 0x68, 0x80, 0x30, 0x02, 0x66, 0xc2, 0x65, 0x43, 0x6e, 0xd2, 0x1a, + 0x82, 0x65, 0x0f, 0x20, /// 0x16c0 + 0x88, 0x72, 0x98, 0x48, 0x03, 0x21, 0x20, 0x30, 0x81, 0x70, 0x95, 0x48, + 0x05, 0x21, 0x40, 0x38, /// 0x16d0 + 0x81, 0x72, 0x10, 0xbd, 0x70, 0xb5, 0x9b, 0x48, 0x01, 0x88, 0x07, 0x22, + 0x12, 0x02, 0x91, 0x43, /// 0x16e0 + 0x01, 0x80, 0x90, 0x48, 0x08, 0x22, 0x41, 0x7b, 0x04, 0x46, 0x11, 0x43, + 0x41, 0x73, 0x0f, 0x21, /// 0x16f0 + 0x81, 0x72, 0x90, 0x49, 0x00, 0x25, 0x20, 0x34, 0xa5, 0x70, 0x10, 0x22, + 0x10, 0x31, 0x50, 0x30, /// 0x1700 + 0xff, 0xf7, 0x27, 0xf9, 0x8c, 0x49, 0x20, 0x46, 0x10, 0x22, 0x10, 0x31, + 0x08, 0x30, 0xff, 0xf7, /// 0x1710 + 0x20, 0xf9, 0x20, 0x46, 0x8c, 0x49, 0x20, 0x30, 0x01, 0x82, 0xff, 0x21, + 0x82, 0x4a, 0x71, 0x31, /// 0x1720 + 0x11, 0x82, 0x01, 0x46, 0x55, 0x22, 0x60, 0x39, 0x8a, 0x77, 0xe2, 0x70, + 0xcd, 0x77, 0x87, 0x49, /// 0x1730 + 0xc1, 0x60, 0x82, 0x49, 0x81, 0x60, 0x7a, 0x48, 0x80, 0x30, 0x81, 0x66, + 0x04, 0x21, 0xc0, 0x38, /// 0x1740 + 0x81, 0x72, 0x70, 0xbd, 0x10, 0xb5, 0x76, 0x48, 0x81, 0x49, 0xc1, 0x62, + 0x41, 0x21, 0x49, 0x02, /// 0x1750 + 0x01, 0x86, 0x80, 0x21, 0x20, 0x30, 0x81, 0x74, 0x05, 0x20, 0xff, 0xf7, + 0xc2, 0xf9, 0x10, 0xbd, /// 0x1760 + 0x10, 0xb5, 0x6f, 0x48, 0x7b, 0x49, 0xc1, 0x62, 0x6e, 0x21, 0x01, 0x86, + 0x7a, 0x49, 0x20, 0x30, /// 0x1770 + 0xca, 0x7b, 0x82, 0x74, 0x0a, 0x7c, 0xc2, 0x74, 0x49, 0x7c, 0x01, 0x75, + 0x07, 0x20, 0xff, 0xf7, /// 0x1780 + 0xb0, 0xf9, 0x10, 0xbd, 0x10, 0xb5, 0x67, 0x49, 0x08, 0x88, 0xc0, 0x08, + 0xff, 0x28, 0x00, 0xd9, /// 0x1790 + 0xff, 0x20, 0xc8, 0x72, 0xff, 0x22, 0x62, 0x49, 0x0d, 0x32, 0x8a, 0x85, + 0x20, 0x31, 0x88, 0x73, /// 0x17a0 + 0x01, 0x20, 0xff, 0xf7, 0x9e, 0xf9, 0x10, 0xbd, 0xf8, 0xb5, 0x5e, 0x4d, + 0x5f, 0x4c, 0x40, 0x35, /// 0x17b0 + 0x68, 0x78, 0x26, 0x46, 0x27, 0x46, 0xc1, 0x06, 0x40, 0x36, 0xc0, 0x37, + 0x00, 0x29, 0x0a, 0xda, /// 0x17c0 + 0xef, 0x21, 0x08, 0x40, 0x68, 0x70, 0xa1, 0x8e, 0x01, 0x20, 0xc0, 0x02, + 0x01, 0x43, 0xa1, 0x86, /// 0x17d0 + 0xfe, 0xf7, 0xdf, 0xff, 0x10, 0xe0, 0x39, 0x79, 0x0a, 0x07, 0x06, 0xd5, + 0x32, 0x7e, 0x1e, 0x2a, /// 0x17e0 + 0x03, 0xd0, 0x20, 0x21, 0x08, 0x43, 0x68, 0x70, 0x06, 0xe0, 0x48, 0x06, + 0x04, 0xd5, 0xbf, 0x20, /// 0x17f0 + 0x01, 0x40, 0x80, 0x20, 0x01, 0x43, 0x39, 0x71, 0x38, 0x79, 0x81, 0x07, + 0x02, 0xd5, 0x31, 0x7e, /// 0x1800 + 0x3f, 0x29, 0x16, 0xd0, 0x69, 0x78, 0x49, 0x06, 0x02, 0xd5, 0x31, 0x7e, + 0x4f, 0x29, 0x13, 0xd0, /// 0x1810 + 0x00, 0x07, 0x09, 0xd5, 0x30, 0x7e, 0x1e, 0x28, 0x06, 0xd0, 0xa0, 0x8e, + 0x10, 0x21, 0x08, 0x43, /// 0x1820 + 0xa0, 0x86, 0x08, 0x46, 0xfe, 0xf7, 0xb5, 0xff, 0xa8, 0x78, 0xbf, 0x21, + 0x08, 0x40, 0xa8, 0x70, /// 0x1830 + 0xf8, 0xbd, 0x01, 0xf0, 0x52, 0xfc, 0xf7, 0xe7, 0x3a, 0x48, 0x19, 0x30, + 0x01, 0xf0, 0x28, 0xfc, /// 0x1840 + 0xf2, 0xe7, 0x10, 0xb5, 0x45, 0x49, 0x0d, 0x20, 0x08, 0x72, 0xff, 0xf7, + 0x2f, 0xf8, 0x37, 0x48, /// 0x1850 + 0x00, 0x21, 0x01, 0x81, 0x33, 0x49, 0x42, 0x4a, 0x49, 0x7b, 0x82, 0x81, + 0x0b, 0x07, 0x7d, 0x21, /// 0x1860 + 0x01, 0x82, 0x96, 0x21, 0xc1, 0x81, 0x2a, 0x21, 0xc1, 0x74, 0x81, 0x7c, + 0x20, 0x22, 0x11, 0x43, /// 0x1870 + 0x81, 0x74, 0x10, 0xbd, 0x10, 0xb5, 0x39, 0x48, 0x00, 0x7e, 0x80, 0x07, + 0x11, 0xd5, 0x01, 0x20, /// 0x1880 + 0x80, 0x03, 0xfe, 0xf7, 0x86, 0xff, 0xff, 0xf7, 0x95, 0xf9, 0x26, 0x48, + 0x02, 0x21, 0x40, 0x30, /// 0x1890 + 0x01, 0x70, 0x25, 0x49, 0x5a, 0x20, 0x08, 0x70, 0x23, 0x49, 0x80, 0x20, + 0x40, 0x31, 0x08, 0x70, /// 0x18a0 + 0xfe, 0xe7, 0x10, 0xbd, 0xfe, 0xb5, 0xff, 0xf7, 0xe5, 0xff, 0x2e, 0x48, + 0x01, 0x90, 0x00, 0x7d, /// 0x18b0 + 0x00, 0x28, 0x12, 0xd0, 0x40, 0x1e, 0x00, 0x06, 0x01, 0x99, 0x00, 0x0e, + 0x08, 0x75, 0x0c, 0xd1, /// 0x18c0 + 0x26, 0x48, 0x20, 0x30, 0x01, 0x78, 0x20, 0x22, 0x11, 0x43, 0x01, 0x70, + 0x17, 0x48, 0x10, 0x22, /// 0x18d0 + 0x81, 0x7c, 0x11, 0x43, 0x81, 0x74, 0xff, 0xf7, 0xb4, 0xff, 0x12, 0x4e, + 0x40, 0x36, 0xb0, 0x78, /// 0x18e0 + 0x40, 0x06, 0x01, 0xd5, 0xff, 0xf7, 0x60, 0xff, 0x0e, 0x48, 0x20, 0x38, + 0x81, 0x7f, 0x40, 0x30, /// 0x18f0 + 0x4b, 0x29, 0x01, 0xd9, 0x01, 0x21, 0x04, 0xe0, 0x23, 0x29, 0x01, 0xd9, + 0x00, 0x21, 0x00, 0xe0, /// 0x1900 + 0x03, 0x21, 0x81, 0x70, 0x17, 0x48, 0x06, 0x4d, 0x40, 0x38, 0x00, 0x90, + 0x40, 0x78, 0x40, 0x35, /// 0x1910 + 0x00, 0x28, 0x2d, 0xd1, 0x28, 0x7a, 0x00, 0x28, 0x2a, 0xd1, 0x28, 0x46, + 0x3c, 0x38, 0x23, 0xe0, /// 0x1920 + 0xb0, 0x02, 0x00, 0x20, 0x40, 0x00, 0x00, 0x20, 0x00, 0x30, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x20, /// 0x1930 + 0x11, 0x06, 0x00, 0x20, 0x6c, 0x1b, 0x00, 0x00, 0x44, 0x31, 0x00, 0x00, + 0x04, 0x0a, 0x0a, 0x00, /// 0x1940 + 0xdc, 0x05, 0x00, 0x00, 0x00, 0x34, 0x00, 0x40, 0x85, 0x09, 0x00, 0x00, + 0x31, 0x14, 0x14, 0x00, /// 0x1950 + 0x0c, 0x51, 0x0a, 0x00, 0x0c, 0x71, 0x12, 0x00, 0x20, 0x47, 0x00, 0x00, + 0x20, 0x6c, 0x00, 0x40, /// 0x1960 + 0x88, 0x13, 0x00, 0x00, 0xb0, 0x03, 0x00, 0x20, 0xfe, 0xf7, 0x84, 0xfd, + 0xfe, 0xf7, 0x47, 0xfe, /// 0x1970 + 0x72, 0x78, 0x73, 0x4f, 0xd0, 0x06, 0x00, 0x28, 0x11, 0xda, 0xbb, 0x89, + 0x39, 0x46, 0x58, 0x1c, /// 0x1980 + 0xb8, 0x81, 0xc0, 0x39, 0x48, 0x8c, 0x83, 0x42, 0x09, 0xd9, 0xef, 0x20, + 0x02, 0x40, 0x72, 0x70, /// 0x1990 + 0x8a, 0x8e, 0x01, 0x20, 0x80, 0x02, 0x02, 0x43, 0x8a, 0x86, 0xfe, 0xf7, + 0xfa, 0xfe, 0x30, 0x78, /// 0x19a0 + 0xc0, 0x06, 0x23, 0xd5, 0x66, 0x48, 0xc0, 0x38, 0x81, 0x7c, 0x02, 0x91, + 0x89, 0x06, 0x1b, 0xd5, /// 0x19b0 + 0x40, 0x89, 0x64, 0x49, 0x48, 0x43, 0x64, 0x49, 0xff, 0xf7, 0x58, 0xfd, + 0x60, 0x4c, 0x12, 0x30, /// 0x19c0 + 0x80, 0x3c, 0xe1, 0x78, 0x06, 0x29, 0x15, 0xd0, 0x22, 0x46, 0x40, 0x3a, + 0x13, 0x6b, 0x18, 0x18, /// 0x19d0 + 0x49, 0x1c, 0x10, 0x63, 0xe1, 0x70, 0x5a, 0x48, 0xc0, 0x38, 0x01, 0x8a, + 0xc0, 0x89, 0xfe, 0xf7, /// 0x19e0 + 0x78, 0xff, 0x30, 0x78, 0xc0, 0x06, 0x01, 0xd5, 0x01, 0xf0, 0xe9, 0xfa, + 0x28, 0x7a, 0x00, 0x28, /// 0x19f0 + 0x42, 0xd1, 0x1c, 0xe0, 0x52, 0x49, 0xc0, 0x39, 0x09, 0x6b, 0x08, 0x18, + 0x07, 0x21, 0xff, 0xf7, /// 0x1a00 + 0x35, 0xfd, 0x4f, 0x49, 0x80, 0xb2, 0xc0, 0x39, 0x08, 0x81, 0x4d, 0x4a, + 0x00, 0x21, 0xe1, 0x70, /// 0x1a10 + 0xc0, 0x3a, 0x11, 0x63, 0x02, 0x99, 0xc9, 0x07, 0xdd, 0xd1, 0x91, 0x89, + 0x43, 0x1a, 0x00, 0xd5, /// 0x1a20 + 0x5b, 0x42, 0xd2, 0x7c, 0x93, 0x42, 0xd6, 0xdd, 0xfe, 0xf7, 0x60, 0xff, + 0xd3, 0xe7, 0x47, 0x48, /// 0x1a30 + 0xe9, 0x7a, 0x04, 0x46, 0xff, 0x34, 0x41, 0x34, 0x20, 0x46, 0xc0, 0x30, + 0x02, 0x90, 0x00, 0x29, /// 0x1a40 + 0x1b, 0xd0, 0x49, 0x1e, 0xe9, 0x72, 0xa0, 0x7a, 0x03, 0x28, 0x76, 0xd3, + 0x72, 0xb6, 0x40, 0x48, /// 0x1a50 + 0xfe, 0xf7, 0x1d, 0xfb, 0x62, 0xb6, 0x28, 0x7b, 0xe9, 0x7a, 0x40, 0x1e, + 0x81, 0x42, 0x6c, 0xd1, /// 0x1a60 + 0x02, 0x99, 0x00, 0x20, 0x08, 0x82, 0x88, 0x81, 0x68, 0x7b, 0x80, 0x06, + 0x65, 0xd4, 0x39, 0x48, /// 0x1a70 + 0x01, 0x88, 0x82, 0x14, 0x91, 0x43, 0x01, 0x80, 0x5f, 0xe0, 0x00, 0x20, + 0x68, 0x74, 0xa0, 0x7a, /// 0x1a80 + 0x03, 0x00, 0xff, 0xf7, 0x1d, 0xfd, 0x09, 0x06, 0x15, 0x1a, 0x26, 0x3f, + 0x42, 0x45, 0x55, 0x58, /// 0x1a90 + 0x5a, 0x00, 0x31, 0x48, 0x00, 0x68, 0x1d, 0x28, 0x4f, 0xd9, 0x08, 0x20, + 0x28, 0x73, 0x2e, 0x48, /// 0x1aa0 + 0x32, 0x21, 0x80, 0x30, 0x41, 0x66, 0x01, 0x20, 0xa0, 0x72, 0xff, 0xf7, + 0x6b, 0xfe, 0x44, 0xe0, /// 0x1ab0 + 0xff, 0xf7, 0x56, 0xfe, 0x02, 0x20, 0xa0, 0x72, 0x3f, 0xe0, 0x34, 0x20, + 0xf0, 0x70, 0x1e, 0x20, /// 0x1ac0 + 0x28, 0x73, 0xff, 0xf7, 0x3f, 0xfe, 0x03, 0x20, 0xa0, 0x72, 0x24, 0x49, + 0x01, 0x20, 0xc8, 0x77, /// 0x1ad0 + 0x33, 0xe0, 0x00, 0x98, 0x00, 0x78, 0xc0, 0x07, 0x02, 0xd0, 0xff, 0xf7, + 0xfb, 0xfd, 0x01, 0xe0, /// 0x1ae0 + 0xff, 0xf7, 0xd3, 0xfd, 0x16, 0x49, 0xff, 0x20, 0xf5, 0x30, 0xc0, 0x39, + 0x48, 0x84, 0x00, 0x20, /// 0x1af0 + 0xb0, 0x64, 0xff, 0x22, 0x78, 0x71, 0x60, 0x32, 0xfa, 0x81, 0x01, 0x9a, + 0x10, 0x75, 0x18, 0x48, /// 0x1b00 + 0x08, 0x87, 0x1a, 0xe0, 0x01, 0xf0, 0x62, 0xf9, 0x17, 0xe0, 0x00, 0xf0, + 0xcb, 0xff, 0x14, 0xe0, /// 0x1b10 + 0x00, 0x98, 0x00, 0x78, 0xc0, 0x07, 0x01, 0xd0, 0x07, 0x20, 0x00, 0xe0, + 0x05, 0x20, 0xa0, 0x72, /// 0x1b20 + 0x0e, 0x49, 0x00, 0x20, 0x40, 0x31, 0xc8, 0x71, 0x02, 0x98, 0xb1, 0x68, + 0x81, 0x66, 0x04, 0xe0, /// 0x1b30 + 0x00, 0xf0, 0x59, 0xfb, 0x01, 0xe0, 0xff, 0xf7, 0x76, 0xfd, 0x00, 0x20, + 0xfe, 0xbd, 0x00, 0x00, /// 0x1b40 + 0xc0, 0x00, 0x00, 0x20, 0x34, 0x08, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, + 0x30, 0x01, 0x00, 0x20, /// 0x1b50 + 0x5f, 0x1f, 0x00, 0x00, 0x20, 0x38, 0x00, 0x40, 0x30, 0x02, 0x00, 0x20, + 0x50, 0x03, 0x00, 0x20, /// 0x1b60 + 0xd8, 0xbf, 0x00, 0x00, 0x32, 0x31, 0x3f, 0x03, 0x32, 0x31, 0x3f, 0x14, + 0xf3, 0x04, 0x19, 0x0c, /// 0x1b70 + 0xea, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x13, 0x08, 0x32, 0x04, /// 0x1b80 + 0x75, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x28, 0x01, 0xd2, /// 0x1b90 + 0x01, 0x20, 0x70, 0x47, 0x80, 0x28, 0x03, 0xd2, 0x20, 0x38, 0x00, 0x11, + 0x80, 0x1c, 0x70, 0x47, /// 0x1ba0 + 0xe0, 0x28, 0x03, 0xd2, 0x80, 0x38, 0xc0, 0x10, 0x08, 0x30, 0x70, 0x47, + 0xe0, 0x38, 0x80, 0x10, /// 0x1bb0 + 0x14, 0x30, 0x70, 0x47, 0x41, 0x07, 0x89, 0x0f, 0x03, 0x29, 0x0b, 0xd1, + 0x01, 0x07, 0x03, 0xd5, /// 0x1bc0 + 0x80, 0x09, 0x02, 0x28, 0x04, 0xd0, 0x05, 0xe0, 0x00, 0x09, 0x03, 0xd0, + 0x0c, 0x28, 0x01, 0xd8, /// 0x1bd0 + 0x01, 0x20, 0x70, 0x47, 0x00, 0x20, 0x70, 0x47, 0x1e, 0x28, 0x08, 0xd0, + 0xc1, 0x43, 0x09, 0x07, /// 0x1be0 + 0x07, 0xd1, 0x01, 0x09, 0x06, 0x29, 0x04, 0xd2, 0x00, 0x06, 0x00, 0x0f, + 0x01, 0xd0, 0x01, 0x20, /// 0x1bf0 + 0x70, 0x47, 0x00, 0x20, 0x70, 0x47, 0x10, 0xb5, 0xf9, 0x48, 0xf7, 0x22, + 0xc1, 0x79, 0x11, 0x40, /// 0x1c00 + 0xc1, 0x71, 0xf7, 0x49, 0x00, 0x20, 0x20, 0x39, 0x08, 0x85, 0x80, 0x20, + 0xfe, 0xf7, 0xc1, 0xfd, /// 0x1c10 + 0x10, 0xbd, 0xf8, 0xb5, 0xf3, 0x4a, 0x10, 0x7d, 0xff, 0xf7, 0xde, 0xff, + 0xf2, 0x49, 0x11, 0x24, /// 0x1c20 + 0x64, 0x01, 0x0f, 0x19, 0x85, 0x23, 0x09, 0x24, 0x9b, 0x00, 0xa4, 0x01, + 0xcb, 0x18, 0x0e, 0x19, /// 0x1c30 + 0x00, 0x28, 0x18, 0xd0, 0xf0, 0x79, 0x40, 0x1c, 0xc0, 0xb2, 0xf0, 0x71, + 0x06, 0x28, 0x01, 0xd9, /// 0x1c40 + 0x06, 0x20, 0xf0, 0x71, 0xc2, 0xb2, 0xe6, 0x48, 0x19, 0x46, 0x38, 0x30, + 0xfe, 0xf7, 0x88, 0xfe, /// 0x1c50 + 0xe3, 0x48, 0x40, 0x22, 0x60, 0x30, 0x81, 0x78, 0x11, 0x43, 0x81, 0x70, + 0xf8, 0x7f, 0xef, 0x21, /// 0x1c60 + 0x08, 0x40, 0xf8, 0x77, 0xf8, 0xbd, 0xde, 0x4c, 0x10, 0x7d, 0x20, 0x3c, + 0x25, 0x46, 0x20, 0x35, /// 0x1c70 + 0x15, 0x28, 0x17, 0xd0, 0xff, 0xf7, 0x9e, 0xff, 0x01, 0x1e, 0xdc, 0x48, + 0x57, 0xd0, 0x11, 0x7d, /// 0x1c80 + 0xea, 0x79, 0xc9, 0x07, 0xd2, 0x07, 0xc9, 0x0f, 0xd2, 0x0f, 0x91, 0x42, + 0x4a, 0xd1, 0xf1, 0x79, /// 0x1c90 + 0xeb, 0x7b, 0x8c, 0x46, 0xaa, 0x7b, 0x59, 0x18, 0x91, 0x42, 0x22, 0xd9, + 0xe9, 0x73, 0x20, 0x8d, /// 0x1ca0 + 0x02, 0x21, 0x41, 0xe0, 0x50, 0x7d, 0x01, 0x06, 0x14, 0xd5, 0xe9, 0x79, + 0x8a, 0x06, 0x92, 0x0f, /// 0x1cb0 + 0x02, 0xd0, 0x20, 0x8d, 0x04, 0x21, 0x37, 0xe0, 0x22, 0x8d, 0x08, 0x23, + 0x40, 0x06, 0x1a, 0x43, /// 0x1cc0 + 0x40, 0x0e, 0x22, 0x85, 0x40, 0x1c, 0xa8, 0x73, 0x00, 0x20, 0xe8, 0x73, + 0x48, 0x08, 0x40, 0x00, /// 0x1cd0 + 0xe8, 0x71, 0xf8, 0xbd, 0x03, 0x28, 0x01, 0xd1, 0xff, 0xf7, 0x8d, 0xff, + 0x20, 0x8d, 0x08, 0x21, /// 0x1ce0 + 0x22, 0xe0, 0xc0, 0x49, 0x18, 0x18, 0x62, 0x46, 0x15, 0x31, 0xfe, 0xf7, + 0x39, 0xfe, 0xe8, 0x7b, /// 0x1cf0 + 0xf1, 0x79, 0x01, 0x22, 0x40, 0x18, 0xc1, 0xb2, 0xe9, 0x73, 0xe8, 0x79, + 0x40, 0x23, 0x50, 0x40, /// 0x1d00 + 0xe8, 0x71, 0x22, 0x8d, 0x1a, 0x43, 0x22, 0x85, 0xb6, 0x4a, 0x32, 0x23, + 0x80, 0x3a, 0x53, 0x66, /// 0x1d10 + 0x05, 0x22, 0x3a, 0x77, 0xaa, 0x7b, 0x91, 0x42, 0xdb, 0xd1, 0x10, 0x21, + 0x08, 0x43, 0xe8, 0x71, /// 0x1d20 + 0x08, 0x46, 0x18, 0xe0, 0x20, 0x8d, 0x40, 0x21, 0x08, 0x43, 0x20, 0x85, + 0xf8, 0xbd, 0xe9, 0x79, /// 0x1d30 + 0x89, 0x06, 0x89, 0x0f, 0xbd, 0xd1, 0x21, 0x8d, 0x08, 0x22, 0x11, 0x43, + 0x21, 0x85, 0xf1, 0x79, /// 0x1d40 + 0x49, 0x1c, 0xca, 0xb2, 0xaa, 0x73, 0x19, 0x46, 0xfe, 0xf7, 0x0a, 0xfe, + 0xe8, 0x79, 0x20, 0x21, /// 0x1d50 + 0x08, 0x43, 0xe8, 0x71, 0x08, 0x46, 0xfe, 0xf7, 0x1c, 0xfd, 0xf8, 0xbd, + 0xf8, 0xb5, 0xa0, 0x4c, /// 0x1d60 + 0x61, 0x7b, 0x22, 0x7b, 0x26, 0x46, 0x20, 0x3e, 0xe0, 0x79, 0x91, 0x42, + 0x07, 0xd3, 0x32, 0x8d, /// 0x1d70 + 0x80, 0x21, 0x8a, 0x43, 0xf7, 0x21, 0x32, 0x85, 0x08, 0x40, 0xe0, 0x71, + 0xf8, 0xbd, 0x52, 0x1a, /// 0x1d80 + 0xd5, 0xb2, 0x08, 0x2d, 0x00, 0xd9, 0x08, 0x25, 0x2a, 0x07, 0x13, 0x0e, + 0x82, 0x07, 0x01, 0xd5, /// 0x1d90 + 0x07, 0x22, 0x00, 0xe0, 0x06, 0x22, 0x1a, 0x43, 0x02, 0x23, 0x58, 0x40, + 0xe0, 0x71, 0x91, 0x4f, /// 0x1da0 + 0x91, 0x48, 0x20, 0x37, 0x09, 0x18, 0x3a, 0x72, 0x38, 0x46, 0x2a, 0x46, + 0x09, 0x30, 0xfe, 0xf7, /// 0x1db0 + 0xd7, 0xfd, 0x60, 0x7b, 0x80, 0x21, 0x40, 0x19, 0x60, 0x73, 0x30, 0x8d, + 0x08, 0x43, 0x30, 0x85, /// 0x1dc0 + 0x38, 0x46, 0x32, 0x21, 0xa0, 0x38, 0x41, 0x66, 0x05, 0x20, 0x38, 0x77, + 0xf8, 0xbd, 0xfe, 0xb5, /// 0x1dd0 + 0x07, 0x46, 0x84, 0x48, 0x20, 0x30, 0x00, 0x90, 0xc0, 0x7f, 0x00, 0x28, + 0x06, 0xd1, 0x00, 0x2f, /// 0x1de0 + 0x01, 0xd0, 0x02, 0x20, 0x00, 0xe0, 0x08, 0x20, 0x00, 0x99, 0xc8, 0x77, + 0x00, 0x98, 0x7e, 0x4b, /// 0x1df0 + 0xc1, 0x7f, 0xf8, 0x01, 0x86, 0x46, 0x7a, 0x48, 0xde, 0x1d, 0xff, 0x36, + 0x20, 0x30, 0xfa, 0x36, /// 0x1e00 + 0x00, 0x89, 0x34, 0x8a, 0x01, 0x94, 0x09, 0x24, 0xa4, 0x01, 0x1c, 0x19, + 0x33, 0x7d, 0x8a, 0x07, /// 0x1e10 + 0xa5, 0x79, 0x9c, 0x46, 0x00, 0x2a, 0x4b, 0xd0, 0x62, 0x46, 0x52, 0x08, + 0x73, 0x46, 0x1a, 0x43, /// 0x1e20 + 0xd2, 0xb2, 0x32, 0x75, 0x00, 0x2d, 0x0a, 0xd0, 0x07, 0x2d, 0x10, 0xd3, + 0xff, 0x2a, 0x11, 0xd0, /// 0x1e30 + 0x00, 0x2a, 0x38, 0xd0, 0x55, 0x2a, 0x38, 0xd0, 0xaa, 0x2a, 0x36, 0xd0, + 0x83, 0xe0, 0x48, 0x21, /// 0x1e40 + 0x48, 0x43, 0x6b, 0x49, 0xff, 0xf7, 0x12, 0xfb, 0x01, 0x99, 0x40, 0x18, + 0x70, 0x82, 0x6d, 0x1c, /// 0x1e50 + 0xa5, 0x71, 0x82, 0xe0, 0x88, 0x07, 0x02, 0xd5, 0xff, 0xf7, 0x80, 0xff, + 0x73, 0xe0, 0x60, 0x4d, /// 0x1e60 + 0x20, 0x3d, 0x6a, 0x8d, 0x00, 0x2a, 0x1c, 0xd0, 0xd0, 0x07, 0x02, 0xd0, + 0xff, 0xf7, 0xc3, 0xfe, /// 0x1e70 + 0x11, 0xe0, 0x5b, 0x48, 0x93, 0x06, 0xc1, 0x79, 0x00, 0x2b, 0x07, 0xda, + 0x00, 0x22, 0x42, 0x73, /// 0x1e80 + 0xfd, 0x22, 0x11, 0x40, 0xc1, 0x71, 0xff, 0xf7, 0x69, 0xff, 0x04, 0xe0, + 0xd2, 0x06, 0x02, 0xd5, /// 0x1e90 + 0xf7, 0x22, 0x11, 0x40, 0xc1, 0x71, 0x28, 0x8d, 0x69, 0x8d, 0x88, 0x43, + 0x28, 0x85, 0x00, 0x20, /// 0x1ea0 + 0x68, 0x85, 0x01, 0x20, 0x02, 0xe0, 0x02, 0x20, 0x00, 0xe0, 0x04, 0x20, + 0x20, 0x70, 0x4a, 0xe0, /// 0x1eb0 + 0xc9, 0x06, 0x49, 0x0f, 0x47, 0xd0, 0x4b, 0x4a, 0x40, 0x32, 0xd1, 0x79, + 0x52, 0x79, 0x00, 0x2d, /// 0x1ec0 + 0x13, 0xd0, 0x48, 0x48, 0x14, 0x30, 0x09, 0x2d, 0x25, 0xd0, 0x0a, 0x2d, + 0x3d, 0xd3, 0x00, 0x2f, /// 0x1ed0 + 0x39, 0xd0, 0x00, 0x23, 0xa3, 0x71, 0x00, 0x2a, 0x25, 0xd0, 0x8a, 0x42, + 0x27, 0xd9, 0x89, 0x1c, /// 0x1ee0 + 0xfe, 0xf7, 0x93, 0xfd, 0x00, 0x28, 0x26, 0xd0, 0x2d, 0xe0, 0x00, 0x2f, + 0x2b, 0xd1, 0x01, 0x23, /// 0x1ef0 + 0xa3, 0x71, 0x00, 0x2a, 0x0c, 0xd0, 0x8a, 0x1a, 0x58, 0x21, 0x92, 0x1c, + 0x4a, 0x43, 0x08, 0x32, /// 0x1f00 + 0x50, 0x43, 0x3b, 0x49, 0xff, 0xf7, 0xb2, 0xfa, 0x01, 0x99, 0x40, 0x18, + 0x70, 0x82, 0x24, 0xe0, /// 0x1f10 + 0x60, 0x21, 0x48, 0x43, 0xf5, 0xe7, 0x0a, 0x21, 0xa1, 0x71, 0x10, 0x5c, + 0xfe, 0xf7, 0x7e, 0xfd, /// 0x1f20 + 0xb8, 0x42, 0x10, 0xd0, 0x19, 0xe0, 0x60, 0x46, 0xff, 0xf7, 0x30, 0xfe, + 0xe0, 0x71, 0x60, 0x79, /// 0x1f30 + 0x40, 0x1c, 0x60, 0x71, 0x11, 0xe0, 0x00, 0x98, 0xc0, 0x7f, 0x40, 0x07, + 0x01, 0xd5, 0x08, 0x20, /// 0x1f40 + 0xb4, 0xe7, 0xff, 0xf7, 0x66, 0xfe, 0x01, 0x20, 0xfe, 0xbd, 0x11, 0x5c, + 0x73, 0x46, 0x49, 0x08, /// 0x1f50 + 0x19, 0x43, 0x11, 0x54, 0xa0, 0x79, 0x40, 0x1c, 0xa0, 0x71, 0x00, 0x20, + 0xfe, 0xbd, 0xfe, 0xb5, /// 0x1f60 + 0x20, 0x4c, 0x24, 0x48, 0xa1, 0x89, 0x26, 0x46, 0x00, 0x27, 0x40, 0x3e, + 0x81, 0x42, 0x09, 0xd1, /// 0x1f70 + 0x60, 0x8a, 0x41, 0x1e, 0x61, 0x82, 0x03, 0xd3, 0x30, 0x7b, 0x40, 0x1e, + 0xf0, 0x72, 0xed, 0xe0, /// 0x1f80 + 0xf7, 0x72, 0xeb, 0xe0, 0x16, 0x48, 0x22, 0x8a, 0x20, 0x38, 0x01, 0x46, + 0x15, 0x4d, 0x40, 0x31, /// 0x1f90 + 0x80, 0x30, 0x40, 0x35, 0x01, 0x91, 0x00, 0x90, 0x00, 0x2a, 0x06, 0xd1, + 0x2f, 0x70, 0x6f, 0x71, /// 0x1fa0 + 0xaf, 0x71, 0x0f, 0x20, 0x60, 0x82, 0xfe, 0xf7, 0x70, 0xfc, 0x9b, 0xe0, + 0x41, 0x00, 0x0e, 0x4a, /// 0x1fb0 + 0x40, 0x1c, 0x89, 0x18, 0xff, 0x31, 0xc1, 0x31, 0x00, 0x07, 0x09, 0x8d, + 0x00, 0x0f, 0x60, 0x72, /// 0x1fc0 + 0xa0, 0x89, 0x40, 0x1c, 0x80, 0xb2, 0xa0, 0x81, 0x03, 0x28, 0x2f, 0xd8, + 0x01, 0x28, 0x13, 0xd0, /// 0x1fd0 + 0xe2, 0x89, 0x51, 0x18, 0x89, 0xb2, 0xe1, 0x81, 0x03, 0x28, 0x12, 0xd1, + 0x12, 0xe0, 0x00, 0x00, /// 0x1fe0 + 0x20, 0x00, 0x00, 0x20, 0x30, 0x03, 0x00, 0x20, 0x30, 0x01, 0x00, 0x20, + 0xb0, 0x01, 0x00, 0x20, /// 0x1ff0 + 0x70, 0x17, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0xe7, 0x81, 0xef, 0x70, + 0xaf, 0x70, 0xaf, 0x72, /// 0x2000 + 0xef, 0x72, 0x6f, 0xe0, 0x49, 0x1c, 0x48, 0x08, 0xe0, 0x81, 0x01, 0x99, + 0x08, 0x81, 0x00, 0x99, /// 0x2010 + 0x09, 0x78, 0xc9, 0x07, 0x01, 0xd1, 0xfe, 0xf7, 0xe1, 0xf9, 0xe1, 0x89, + 0x50, 0x4a, 0x48, 0x08, /// 0x2020 + 0x80, 0x18, 0xff, 0xf7, 0x23, 0xfa, 0x01, 0x99, 0xc8, 0x83, 0x5b, 0xe0, + 0x00, 0x98, 0xc2, 0x7a, /// 0x2030 + 0x06, 0x20, 0x93, 0x07, 0x9b, 0x0f, 0x98, 0x40, 0x80, 0x1e, 0x52, 0x07, + 0xe2, 0x89, 0x03, 0xd5, /// 0x2040 + 0x10, 0x18, 0x88, 0x42, 0x03, 0xd3, 0x20, 0xe0, 0x10, 0x1a, 0x88, 0x42, + 0x1d, 0xd9, 0xe8, 0x78, /// 0x2050 + 0x40, 0x1c, 0xc0, 0xb2, 0xe8, 0x70, 0x0a, 0x28, 0x53, 0xd8, 0xa8, 0x7a, + 0x00, 0x28, 0x12, 0xd0, /// 0x2060 + 0xa8, 0x78, 0x05, 0x28, 0x01, 0xd9, 0x00, 0x20, 0x05, 0xe0, 0x02, 0x28, + 0x0b, 0xd9, 0xe8, 0x7a, /// 0x2070 + 0x00, 0x28, 0x06, 0xd0, 0x01, 0x20, 0xff, 0xf7, 0xaa, 0xfe, 0x00, 0x28, + 0x41, 0xd1, 0xef, 0x72, /// 0x2080 + 0x01, 0xe0, 0x01, 0x20, 0xe8, 0x72, 0xaf, 0x70, 0x2c, 0xe0, 0xa8, 0x78, + 0x40, 0x1c, 0xc0, 0xb2, /// 0x2090 + 0xa8, 0x70, 0xa9, 0x7a, 0x00, 0x29, 0x0c, 0xd0, 0xe9, 0x7a, 0x00, 0x29, + 0x03, 0xd0, 0x05, 0x28, /// 0x20a0 + 0x0c, 0xd9, 0x01, 0x20, 0x02, 0xe0, 0x0a, 0x28, 0x08, 0xd9, 0x00, 0x20, + 0xff, 0xf7, 0x8f, 0xfe, /// 0x20b0 + 0x27, 0xe0, 0xe8, 0x78, 0x02, 0x28, 0x01, 0xd9, 0x01, 0x20, 0xa8, 0x72, + 0xe8, 0x78, 0x05, 0x28, /// 0x20c0 + 0x01, 0xd9, 0x00, 0x20, 0x05, 0xe0, 0x02, 0x28, 0x0b, 0xd9, 0xe8, 0x7a, + 0x00, 0x28, 0x06, 0xd0, /// 0x20d0 + 0x01, 0x20, 0xff, 0xf7, 0x7c, 0xfe, 0x00, 0x28, 0x13, 0xd1, 0xef, 0x72, + 0x01, 0xe0, 0x01, 0x20, /// 0x20e0 + 0xe8, 0x72, 0xef, 0x70, 0x21, 0x7a, 0x60, 0x7a, 0x81, 0x42, 0x00, 0xd0, + 0x5e, 0xe7, 0x30, 0x7b, /// 0x20f0 + 0x40, 0x1e, 0xf0, 0x72, 0x20, 0x8a, 0x40, 0x1c, 0x80, 0xb2, 0x20, 0x82, + 0x61, 0x8a, 0x88, 0x42, /// 0x2100 + 0x2c, 0xd9, 0xfe, 0xf7, 0x54, 0xfb, 0x00, 0x20, 0xc0, 0x43, 0xa0, 0x81, + 0x15, 0x48, 0xc7, 0x77, /// 0x2110 + 0x70, 0x7c, 0x00, 0x28, 0x01, 0xd0, 0x16, 0x20, 0x00, 0xe0, 0x05, 0x20, + 0x70, 0x74, 0x28, 0x78, /// 0x2120 + 0x00, 0x28, 0x01, 0xd0, 0x70, 0x7c, 0x10, 0xe0, 0x60, 0x8a, 0x0f, 0x28, + 0x04, 0xd9, 0x21, 0x8a, /// 0x2130 + 0x40, 0x1a, 0x71, 0x7c, 0x40, 0x18, 0x08, 0xe0, 0x20, 0x8a, 0x31, 0x7b, + 0x02, 0x1d, 0x8a, 0x42, /// 0x2140 + 0x02, 0xd2, 0xc0, 0xb2, 0x08, 0x1a, 0x00, 0xe0, 0x04, 0x20, 0x60, 0x82, + 0x20, 0x8a, 0x61, 0x8a, /// 0x2150 + 0x42, 0x18, 0x31, 0x7b, 0x8a, 0x42, 0x01, 0xd2, 0x08, 0x1a, 0x60, 0x82, + 0x00, 0x20, 0xfe, 0xbd, /// 0x2160 + 0x00, 0xdc, 0x05, 0x00, 0x50, 0x03, 0x00, 0x20, 0x10, 0xb5, 0xfe, 0x48, + 0x41, 0x7b, 0x0a, 0x07, /// 0x2170 + 0x03, 0xd5, 0xf7, 0x22, 0x11, 0x40, 0x41, 0x73, 0x10, 0xbd, 0x08, 0x22, + 0x11, 0x43, 0x41, 0x73, /// 0x2180 + 0xfe, 0xf7, 0x18, 0xfd, 0x10, 0xbd, 0xf7, 0x49, 0x00, 0x20, 0xf7, 0x4a, + 0x40, 0x31, 0x89, 0x6e, /// 0x2190 + 0x92, 0x68, 0x06, 0xe0, 0x0b, 0x46, 0x53, 0x40, 0x1b, 0x06, 0x00, 0xd0, + 0x40, 0x1c, 0x09, 0x0a, /// 0x21a0 + 0x12, 0x0a, 0x0b, 0x46, 0x13, 0x43, 0xf5, 0xd1, 0x70, 0x47, 0xee, 0x4a, + 0x10, 0xb5, 0xef, 0x4b, /// 0x21b0 + 0x40, 0x3a, 0x93, 0x85, 0x20, 0x32, 0x90, 0x73, 0xd1, 0x73, 0x11, 0x46, + 0x01, 0x20, 0x80, 0x31, /// 0x21c0 + 0xc8, 0x77, 0x02, 0x20, 0xfe, 0xf7, 0x8d, 0xfc, 0x10, 0xbd, 0xe6, 0x49, + 0x10, 0xb5, 0xe8, 0x4a, /// 0x21d0 + 0x40, 0x39, 0x8a, 0x85, 0x20, 0x31, 0x88, 0x73, 0x04, 0x20, 0x80, 0x31, + 0xc8, 0x77, 0x01, 0x20, /// 0x21e0 + 0xfe, 0xf7, 0x7f, 0xfc, 0x10, 0xbd, 0xf8, 0xb5, 0x09, 0x21, 0xe2, 0x4b, + 0xdd, 0x4c, 0x89, 0x01, /// 0x21f0 + 0x5d, 0x18, 0xa0, 0x34, 0xff, 0x33, 0xe0, 0x79, 0xff, 0x33, 0x02, 0x26, + 0xda, 0x4a, 0x02, 0x33, /// 0x2200 + 0x00, 0x28, 0x02, 0xd0, 0x01, 0x28, 0x0b, 0xd0, 0x3e, 0xe0, 0xd0, 0x79, + 0xc0, 0x07, 0x05, 0xd0, /// 0x2210 + 0x31, 0x20, 0xff, 0xf7, 0xda, 0xff, 0x01, 0x20, 0xe0, 0x71, 0xf8, 0xbd, + 0xe6, 0x71, 0x0c, 0xe0, /// 0x2220 + 0x28, 0x78, 0x00, 0x07, 0xfa, 0xd5, 0x18, 0x7d, 0x31, 0x28, 0xf7, 0xd1, + 0x58, 0x7d, 0x10, 0x71, /// 0x2230 + 0x98, 0x7d, 0x50, 0x71, 0xd8, 0x7d, 0x90, 0x71, 0xf0, 0xe7, 0xe7, 0x79, + 0x78, 0x08, 0xf9, 0x07, /// 0x2240 + 0x7f, 0x1c, 0xff, 0xb2, 0xe7, 0x71, 0xbc, 0x46, 0xc7, 0x4f, 0x80, 0x3f, + 0x00, 0x29, 0x0c, 0xd0, /// 0x2250 + 0x29, 0x78, 0xc9, 0x07, 0x18, 0xd0, 0x39, 0x18, 0xc6, 0x4f, 0x80, 0x31, + 0x38, 0x18, 0x13, 0x27, /// 0x2260 + 0x7f, 0x01, 0x09, 0x7b, 0xc0, 0x19, 0x01, 0x72, 0x0e, 0xe0, 0x3f, 0x18, + 0x80, 0x37, 0x39, 0x7b, /// 0x2270 + 0x3f, 0x7a, 0xb9, 0x42, 0x05, 0xd0, 0xc2, 0x07, 0x00, 0xd1, 0x04, 0x20, + 0xff, 0xf7, 0x95, 0xff, /// 0x2280 + 0xf8, 0xbd, 0x60, 0x46, 0x40, 0x1c, 0xe0, 0x71, 0xe0, 0x79, 0x08, 0x28, + 0xd5, 0xd3, 0x41, 0x1c, /// 0x2290 + 0xe1, 0x71, 0x08, 0x28, 0x06, 0xd0, 0x28, 0x78, 0xc0, 0x07, 0x08, 0xd0, + 0x98, 0x6e, 0x90, 0x60, /// 0x22a0 + 0xd6, 0x71, 0x06, 0xe0, 0xff, 0xf7, 0x6f, 0xff, 0xc1, 0xb2, 0x00, 0x20, + 0xe6, 0xe7, 0x04, 0x20, /// 0x22b0 + 0xd0, 0x71, 0xac, 0x48, 0x05, 0x21, 0x80, 0x38, 0x81, 0x72, 0xf8, 0xbd, + 0xa9, 0x48, 0x10, 0xb5, /// 0x22c0 + 0xad, 0x49, 0x40, 0x38, 0xc1, 0x62, 0xa7, 0x49, 0x01, 0x20, 0x60, 0x31, + 0xc8, 0x77, 0xfe, 0xf7, /// 0x22d0 + 0x08, 0xfc, 0x10, 0xbd, 0xa3, 0x48, 0x10, 0xb5, 0xa8, 0x49, 0x40, 0x38, + 0x81, 0x85, 0xa2, 0x48, /// 0x22e0 + 0x60, 0x38, 0x81, 0x7e, 0x9f, 0x48, 0x20, 0x38, 0x81, 0x73, 0x01, 0x20, + 0xfe, 0xf7, 0xf9, 0xfb, /// 0x22f0 + 0x10, 0xbd, 0x9c, 0x48, 0x10, 0xb5, 0x60, 0x30, 0x00, 0x7a, 0xff, 0xf7, + 0x47, 0xfc, 0x99, 0x49, /// 0x2300 + 0xc4, 0xb2, 0x68, 0x31, 0x08, 0x46, 0x62, 0x1c, 0x7b, 0x38, 0xfe, 0xf7, + 0x29, 0xfb, 0x95, 0x48, /// 0x2310 + 0x0c, 0x21, 0x20, 0x38, 0x01, 0x73, 0x20, 0x46, 0xfe, 0xf7, 0xe3, 0xfb, + 0x10, 0xbd, 0x91, 0x49, /// 0x2320 + 0x10, 0xb5, 0x0c, 0x22, 0x20, 0x39, 0x0a, 0x73, 0x15, 0x22, 0x4a, 0x73, + 0x88, 0x73, 0x01, 0x20, /// 0x2330 + 0xfe, 0xf7, 0xd7, 0xfb, 0x10, 0xbd, 0x10, 0xb5, 0x8e, 0x48, 0x00, 0x78, + 0xff, 0xf7, 0x26, 0xfc, /// 0x2340 + 0x04, 0x46, 0x42, 0x1c, 0x87, 0x48, 0x8b, 0x49, 0x13, 0x38, 0xfe, 0xf7, + 0x09, 0xfb, 0x85, 0x48, /// 0x2350 + 0x0c, 0x21, 0x20, 0x38, 0x01, 0x73, 0x20, 0x46, 0xfe, 0xf7, 0xc3, 0xfb, + 0x10, 0xbd, 0xf0, 0xb5, /// 0x2360 + 0x81, 0x48, 0x01, 0x78, 0x49, 0x06, 0x01, 0xd5, 0x00, 0x20, 0xf0, 0xbd, + 0x01, 0x8a, 0x7e, 0x48, /// 0x2370 + 0x40, 0x38, 0x00, 0x88, 0x0b, 0x1a, 0x02, 0xd5, 0x01, 0x25, 0x59, 0x42, + 0x01, 0xe0, 0x00, 0x25, /// 0x2380 + 0x19, 0x46, 0x78, 0x48, 0x04, 0x26, 0xa0, 0x30, 0x42, 0x7c, 0x94, 0x08, + 0x34, 0x1b, 0x4c, 0x43, /// 0x2390 + 0x61, 0x09, 0x05, 0xd0, 0x00, 0x2d, 0x01, 0xd0, 0x00, 0x24, 0x02, 0xe0, + 0x02, 0x24, 0x00, 0xe0, /// 0x23a0 + 0x01, 0x24, 0x10, 0x26, 0x86, 0x57, 0x02, 0x27, 0x7e, 0x40, 0x20, 0x27, + 0xa6, 0x42, 0x05, 0xd1, /// 0x23b0 + 0x0f, 0x2a, 0x01, 0xd2, 0x52, 0x1c, 0x0e, 0xe0, 0x87, 0x74, 0x0e, 0xe0, + 0x86, 0x7c, 0x00, 0x2e, /// 0x23c0 + 0x0b, 0xd0, 0x76, 0x1e, 0x36, 0x06, 0x36, 0x0e, 0x86, 0x74, 0x06, 0xd1, + 0x00, 0x2a, 0x04, 0xd0, /// 0x23d0 + 0xfc, 0x26, 0x52, 0x1e, 0x32, 0x40, 0x42, 0x74, 0xee, 0xe7, 0x04, 0x74, + 0x00, 0x24, 0x00, 0x29, /// 0x23e0 + 0x0b, 0xd0, 0xc4, 0x73, 0x84, 0x73, 0x08, 0x22, 0x02, 0x73, 0x7f, 0x29, + 0x00, 0xd9, 0x7f, 0x21, /// 0x23f0 + 0x00, 0x2d, 0x00, 0xd0, 0x49, 0x42, 0x48, 0xb2, 0xf0, 0xbd, 0x82, 0x7b, + 0xd2, 0x18, 0x56, 0xb2, /// 0x2400 + 0x86, 0x73, 0xc2, 0x7b, 0x52, 0x1c, 0xd3, 0xb2, 0xc3, 0x73, 0x9a, 0x07, + 0xf0, 0xd1, 0x02, 0x7b, /// 0x2410 + 0x96, 0x42, 0x02, 0xdd, 0x01, 0x21, 0x00, 0x25, 0x04, 0xe0, 0x57, 0x42, + 0xbe, 0x42, 0x07, 0xda, /// 0x2420 + 0x01, 0x21, 0x0d, 0x46, 0x0c, 0x2b, 0x01, 0xd3, 0x52, 0x1c, 0x02, 0x73, + 0x84, 0x73, 0xdc, 0xe7, /// 0x2430 + 0xc4, 0x73, 0x43, 0x7b, 0x5b, 0x1c, 0xdb, 0xb2, 0x43, 0x73, 0x20, 0x2b, + 0xf6, 0xd9, 0x44, 0x73, /// 0x2440 + 0x04, 0x2a, 0xf3, 0xd9, 0x52, 0x1e, 0xf0, 0xe7, 0xfe, 0xb5, 0x47, 0x48, + 0x4c, 0x49, 0x80, 0x38, /// 0x2450 + 0x80, 0x8f, 0x45, 0x4e, 0x48, 0x43, 0x00, 0x0c, 0x40, 0x3e, 0xb0, 0x87, + 0x30, 0x88, 0x41, 0x43, /// 0x2460 + 0x09, 0x0c, 0xf1, 0x87, 0x47, 0x49, 0x88, 0x42, 0x05, 0xd2, 0x47, 0x48, + 0x01, 0x8b, 0x1f, 0x22, /// 0x2470 + 0x12, 0x02, 0x91, 0x43, 0x01, 0x83, 0x3b, 0x4f, 0x3e, 0x4d, 0x78, 0x7b, + 0x3a, 0x4c, 0x41, 0x07, /// 0x2480 + 0xe8, 0x1d, 0xf9, 0x30, 0x80, 0x3c, 0x01, 0x90, 0x20, 0x46, 0x80, 0x30, + 0xff, 0x35, 0xa0, 0x34, /// 0x2490 + 0x81, 0x35, 0x00, 0x90, 0x00, 0x29, 0x4e, 0xda, 0x70, 0x8f, 0xfe, 0xf7, + 0x75, 0xf8, 0xb0, 0x80, /// 0x24a0 + 0x00, 0x99, 0x09, 0x78, 0xc9, 0x07, 0x2b, 0xd1, 0xfe, 0xf7, 0x1a, 0xfc, + 0xb8, 0x7b, 0xfe, 0xf7, /// 0x24b0 + 0x14, 0xf8, 0xb9, 0x7b, 0x35, 0x4a, 0x04, 0x29, 0x02, 0xd2, 0x01, 0x20, + 0x90, 0x80, 0x03, 0xe0, /// 0x24c0 + 0x03, 0x20, 0x90, 0x80, 0x0a, 0x29, 0x01, 0xd2, 0x00, 0x20, 0x08, 0xe0, + 0x0f, 0x29, 0x01, 0xd2, /// 0x24d0 + 0x01, 0x20, 0x04, 0xe0, 0x14, 0x29, 0x01, 0xd2, 0x02, 0x20, 0x00, 0xe0, + 0x03, 0x20, 0x2b, 0x4a, /// 0x24e0 + 0x12, 0x88, 0xf0, 0x23, 0x9a, 0x43, 0x80, 0x01, 0x02, 0x43, 0x28, 0x48, + 0x02, 0x80, 0x07, 0x29, /// 0x24f0 + 0x01, 0xd9, 0x16, 0x21, 0x00, 0xe0, 0x06, 0x21, 0x24, 0x48, 0x81, 0x81, + 0xfe, 0xf7, 0xc0, 0xfb, /// 0x2500 + 0xff, 0xf7, 0x2d, 0xff, 0x18, 0x49, 0x40, 0x31, 0x0a, 0x79, 0x94, 0x46, + 0x92, 0x07, 0x6b, 0xd1, /// 0x2510 + 0x8b, 0x79, 0x5a, 0x1c, 0x8a, 0x71, 0x03, 0x2b, 0x66, 0xd9, 0x72, 0x7b, + 0x12, 0x07, 0x63, 0xd4, /// 0x2520 + 0x62, 0x46, 0x06, 0x23, 0x1a, 0x43, 0x0a, 0x71, 0x01, 0x9a, 0x13, 0x68, + 0x00, 0x9a, 0x93, 0x64, /// 0x2530 + 0x00, 0x22, 0x4a, 0x71, 0x58, 0xe0, 0xff, 0xf7, 0x12, 0xff, 0x79, 0x7b, + 0x0a, 0x07, 0x53, 0xd4, /// 0x2540 + 0x00, 0x9a, 0x13, 0x8a, 0x0d, 0x4a, 0xaa, 0x32, 0x93, 0x42, 0x28, 0xd8, + 0x32, 0x88, 0x9a, 0x42, /// 0x2550 + 0x06, 0xd8, 0x01, 0x9a, 0x13, 0x68, 0x2a, 0x6e, 0x9a, 0x1a, 0x0d, 0x4b, + 0x9a, 0x42, 0x1c, 0xdb, /// 0x2560 + 0x22, 0x7a, 0x17, 0xe0, 0xf0, 0x02, 0x00, 0x20, 0x80, 0x00, 0x00, 0x20, + 0x0c, 0x20, 0x00, 0x00, /// 0x2570 + 0x0c, 0x07, 0x00, 0x00, 0x30, 0x01, 0x00, 0x20, 0x0c, 0x09, 0x00, 0x00, + 0x0c, 0x05, 0x00, 0x00, /// 0x2580 + 0x80, 0x20, 0x05, 0x00, 0x83, 0x02, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40, + 0x00, 0x34, 0x00, 0x40, /// 0x2590 + 0x88, 0x13, 0x00, 0x00, 0x10, 0x23, 0x1a, 0x43, 0x11, 0xe0, 0x37, 0x20, + 0x10, 0xe0, 0x22, 0x7a, /// 0x25a0 + 0x94, 0x46, 0x93, 0x07, 0x06, 0xd5, 0x01, 0x9b, 0x2a, 0x6e, 0x1b, 0x68, + 0x9b, 0x1a, 0xfe, 0x4a, /// 0x25b0 + 0x93, 0x42, 0x19, 0xdb, 0x62, 0x46, 0x10, 0x23, 0x1a, 0x43, 0x52, 0x08, + 0x52, 0x00, 0x22, 0x72, /// 0x25c0 + 0x22, 0x7a, 0x93, 0x07, 0x10, 0xd4, 0xd3, 0x06, 0x0e, 0xd5, 0x10, 0x07, + 0x02, 0xd5, 0xf8, 0x48, /// 0x25d0 + 0xf6, 0x4a, 0x42, 0x81, 0x07, 0x20, 0x01, 0x43, 0x79, 0x73, 0x32, 0x20, + 0x68, 0x66, 0x01, 0x98, /// 0x25e0 + 0x00, 0x68, 0x28, 0x38, 0xa8, 0x65, 0xfe, 0xbd, 0xf1, 0x49, 0x42, 0x1d, + 0x20, 0x31, 0x0a, 0x2a, /// 0x25f0 + 0x02, 0xd9, 0x7a, 0x7b, 0x12, 0x07, 0x0a, 0xd5, 0x00, 0x22, 0x8a, 0x77, + 0x0a, 0x7f, 0x00, 0x2a, /// 0x2600 + 0x02, 0xd0, 0x52, 0x1e, 0x0a, 0x77, 0x09, 0xe0, 0x96, 0x21, 0x69, 0x66, + 0x06, 0xe0, 0x32, 0x22, /// 0x2610 + 0x6a, 0x66, 0x8a, 0x7f, 0xff, 0x2a, 0x01, 0xd0, 0x52, 0x1c, 0x8a, 0x77, + 0x21, 0x7a, 0x0a, 0x07, /// 0x2620 + 0x11, 0xd5, 0x82, 0x1d, 0x0c, 0x2a, 0x04, 0xd8, 0x8a, 0x07, 0x09, 0xd5, + 0x49, 0x08, 0x49, 0x00, /// 0x2630 + 0x08, 0xe0, 0xdf, 0x4a, 0x80, 0x32, 0x52, 0x7d, 0x03, 0x2a, 0x04, 0xd9, + 0x8a, 0x07, 0x02, 0xd4, /// 0x2640 + 0xfb, 0x22, 0x11, 0x40, 0x21, 0x72, 0xb1, 0x88, 0x32, 0x29, 0x15, 0xd2, + 0x1e, 0x28, 0x03, 0xdd, /// 0x2650 + 0x00, 0x99, 0x49, 0x8c, 0x27, 0x29, 0x04, 0xd0, 0x00, 0x99, 0x49, 0x8c, + 0x28, 0x29, 0x02, 0xd0, /// 0x2660 + 0x0a, 0xe0, 0x1e, 0x20, 0x08, 0xe0, 0x09, 0x21, 0xc9, 0x43, 0x0a, 0x28, + 0x01, 0xdd, 0x0a, 0x20, /// 0x2670 + 0x02, 0xe0, 0x88, 0x42, 0x00, 0xda, 0x08, 0x46, 0xc3, 0x21, 0x89, 0x00, + 0xa9, 0x85, 0xcc, 0x49, /// 0x2680 + 0x60, 0x39, 0x88, 0x73, 0x00, 0x28, 0x01, 0xd0, 0x01, 0x20, 0x78, 0x74, + 0x01, 0x20, 0xfe, 0xf7, /// 0x2690 + 0x28, 0xfa, 0xc8, 0x48, 0x01, 0x8c, 0x49, 0x1c, 0x01, 0x84, 0xfe, 0xbd, + 0xc4, 0x48, 0x10, 0xb5, /// 0x26a0 + 0x0c, 0x21, 0x60, 0x38, 0x01, 0x73, 0x38, 0x21, 0x41, 0x73, 0x0a, 0x21, + 0x81, 0x73, 0xc1, 0x49, /// 0x26b0 + 0x40, 0x31, 0x09, 0x8f, 0xc1, 0x73, 0x09, 0x0a, 0x01, 0x74, 0xbd, 0x49, + 0x10, 0x20, 0x20, 0x31, /// 0x26c0 + 0xc8, 0x77, 0x03, 0x20, 0xfe, 0xf7, 0x0d, 0xfa, 0x10, 0xbd, 0xb9, 0x48, + 0x10, 0xb5, 0x0c, 0x21, /// 0x26d0 + 0x60, 0x38, 0x01, 0x73, 0x38, 0x21, 0x41, 0x73, 0x3b, 0x21, 0x81, 0x73, + 0x02, 0x21, 0xc1, 0x73, /// 0x26e0 + 0xbb, 0x21, 0x01, 0x74, 0xb2, 0x49, 0x10, 0x20, 0x20, 0x31, 0xc8, 0x77, + 0x03, 0x20, 0xfe, 0xf7, /// 0x26f0 + 0xf8, 0xf9, 0x10, 0xbd, 0xae, 0x4a, 0x10, 0xb5, 0x0c, 0x23, 0x60, 0x3a, + 0x13, 0x73, 0xa4, 0x23, /// 0x2700 + 0x53, 0x73, 0x90, 0x73, 0xaa, 0x48, 0x08, 0x22, 0x51, 0x38, 0xfe, 0xf7, + 0x29, 0xf9, 0xa8, 0x49, /// 0x2710 + 0x10, 0x20, 0x20, 0x31, 0xc8, 0x77, 0x0c, 0x20, 0xfe, 0xf7, 0xe3, 0xf9, + 0x10, 0xbd, 0x10, 0xb5, /// 0x2720 + 0xa5, 0xa1, 0x03, 0xc9, 0xa2, 0xb0, 0x01, 0x91, 0xa2, 0x49, 0x00, 0x90, + 0x14, 0x31, 0x08, 0x22, /// 0x2730 + 0x0c, 0x46, 0x1c, 0xa8, 0xfe, 0xf7, 0x14, 0xf9, 0x08, 0x22, 0x69, 0x46, + 0x1e, 0xa8, 0xfe, 0xf7, /// 0x2740 + 0x0f, 0xf9, 0x02, 0xa8, 0xfe, 0xf7, 0xe6, 0xfc, 0x10, 0x22, 0x1c, 0xa9, + 0x02, 0xa8, 0xfe, 0xf7, /// 0x2750 + 0x27, 0xfe, 0x98, 0x49, 0x02, 0xa8, 0xb0, 0x31, 0xfe, 0xf7, 0xf4, 0xfd, + 0x21, 0x46, 0x08, 0x20, /// 0x2760 + 0xff, 0xf7, 0xc8, 0xff, 0x22, 0xb0, 0x10, 0xbd, 0x92, 0x48, 0x10, 0xb5, + 0x40, 0x30, 0x00, 0x7c, /// 0x2770 + 0xff, 0xf7, 0x0c, 0xfa, 0x04, 0x46, 0x42, 0x1c, 0x8e, 0x49, 0x8d, 0x48, + 0x50, 0x31, 0x53, 0x38, /// 0x2780 + 0xfe, 0xf7, 0xee, 0xf8, 0x8a, 0x48, 0x0c, 0x21, 0x60, 0x38, 0x01, 0x73, + 0x88, 0x49, 0x10, 0x20, /// 0x2790 + 0x20, 0x31, 0xc8, 0x77, 0x20, 0x46, 0xfe, 0xf7, 0xa4, 0xf9, 0x10, 0xbd, + 0xfe, 0xb5, 0x85, 0x4d, /// 0x27a0 + 0x80, 0x35, 0x28, 0x7e, 0x2e, 0x46, 0x40, 0x1e, 0xc2, 0xb2, 0x20, 0x36, + 0x2a, 0x76, 0x00, 0x2a, /// 0x27b0 + 0x1a, 0xd0, 0x80, 0x49, 0x9c, 0x20, 0x40, 0x5a, 0x40, 0x31, 0x00, 0x91, + 0x08, 0x2a, 0x42, 0xd3, /// 0x27c0 + 0x91, 0x07, 0x10, 0xd1, 0x00, 0x99, 0x6b, 0x8b, 0x09, 0x88, 0x59, 0x18, + 0x89, 0xb2, 0x69, 0x83, /// 0x27d0 + 0x00, 0x9b, 0x5b, 0x8f, 0xc0, 0x18, 0x80, 0xb2, 0xa8, 0x83, 0x08, 0x2a, + 0x03, 0xd1, 0x09, 0x09, /// 0x27e0 + 0x69, 0x83, 0x00, 0x09, 0xa8, 0x83, 0xfe, 0xbd, 0x71, 0x48, 0xfd, 0x21, + 0x40, 0x30, 0x02, 0x78, /// 0x27f0 + 0x70, 0x48, 0xd3, 0x07, 0xa0, 0x30, 0x00, 0x7a, 0x01, 0x40, 0x00, 0x2b, + 0x16, 0xd0, 0x02, 0x07, /// 0x2800 + 0xf1, 0xd5, 0xc2, 0x07, 0x01, 0xd0, 0x40, 0x21, 0x0d, 0xe0, 0x82, 0x07, + 0x01, 0xd5, 0x31, 0x72, /// 0x2810 + 0xfe, 0xbd, 0x41, 0x07, 0x06, 0xd4, 0xf7, 0x21, 0x08, 0x40, 0x30, 0x72, + 0x64, 0x48, 0x68, 0x49, /// 0x2820 + 0x41, 0x81, 0xfe, 0xbd, 0x80, 0x21, 0x08, 0x43, 0x30, 0x72, 0xfe, 0xbd, + 0x92, 0x07, 0xfc, 0xd5, /// 0x2830 + 0x02, 0x07, 0xfa, 0xd5, 0xc2, 0x07, 0xf8, 0xd1, 0x82, 0x07, 0xf6, 0xd5, + 0x40, 0x06, 0xf4, 0xd5, /// 0x2840 + 0xbf, 0x20, 0x01, 0x40, 0xe3, 0xe7, 0x06, 0x2a, 0xef, 0xd8, 0xfd, 0xf7, + 0x9d, 0xfe, 0x04, 0x46, /// 0x2850 + 0x68, 0x8b, 0x0b, 0x21, 0x09, 0x07, 0x40, 0x18, 0xfe, 0xf7, 0xca, 0xfa, + 0x05, 0x20, 0x40, 0x07, /// 0x2860 + 0x20, 0x43, 0xfe, 0xf7, 0xc5, 0xfa, 0x53, 0x48, 0x81, 0x8f, 0x0d, 0x20, + 0x00, 0x07, 0x08, 0x18, /// 0x2870 + 0xfe, 0xf7, 0xbe, 0xfa, 0x00, 0x98, 0x0f, 0x21, 0x00, 0x89, 0x09, 0x07, + 0x40, 0x18, 0xfe, 0xf7, /// 0x2880 + 0xb7, 0xfa, 0x50, 0x48, 0x00, 0x88, 0x00, 0x0b, 0xc1, 0x07, 0x05, 0xd0, + 0x40, 0x07, 0x80, 0x0f, /// 0x2890 + 0x0a, 0x21, 0x40, 0x1c, 0x48, 0x43, 0x04, 0x19, 0x68, 0x8b, 0x15, 0x21, + 0x61, 0x43, 0x48, 0x43, /// 0x28a0 + 0x07, 0x0b, 0x00, 0x20, 0x68, 0x83, 0xa8, 0x83, 0x07, 0x21, 0x38, 0x46, + 0x49, 0x07, 0x08, 0x43, /// 0x28b0 + 0xfe, 0xf7, 0x9e, 0xfa, 0x44, 0x48, 0x80, 0x8b, 0xc0, 0x07, 0x0a, 0xd0, + 0x43, 0x48, 0x81, 0x88, /// 0x28c0 + 0x89, 0x07, 0x89, 0x0f, 0x01, 0x29, 0x06, 0xd0, 0x41, 0x49, 0x8c, 0x42, + 0x05, 0xd9, 0x05, 0x20, /// 0x28d0 + 0x07, 0xe0, 0x07, 0x20, 0x05, 0xe0, 0x00, 0x20, 0x03, 0xe0, 0x00, 0x88, + 0x00, 0x06, 0x80, 0x0f, /// 0x28e0 + 0x40, 0x1c, 0x68, 0x76, 0x00, 0x06, 0xc1, 0x0d, 0x32, 0x48, 0x09, 0x18, + 0x60, 0x31, 0x0a, 0x7a, /// 0x28f0 + 0x7a, 0x43, 0xd3, 0x09, 0x09, 0x22, 0x8a, 0x56, 0x0a, 0x21, 0x4a, 0x43, + 0xd4, 0x18, 0x00, 0xd5, /// 0x2900 + 0x00, 0x24, 0x34, 0x4f, 0x84, 0x84, 0x3b, 0x46, 0xff, 0x33, 0x2a, 0x7a, + 0x03, 0x21, 0x81, 0x33, /// 0x2910 + 0xff, 0x37, 0x89, 0x07, 0xa1, 0x37, 0x01, 0x93, 0x31, 0x2a, 0x0b, 0xd0, + 0x00, 0x22, 0x2a, 0x76, /// 0x2920 + 0x27, 0x4a, 0x80, 0x8f, 0x87, 0x3a, 0x90, 0x42, 0x66, 0xd8, 0x2b, 0x48, + 0x84, 0x42, 0x68, 0xd9, /// 0x2930 + 0x04, 0x46, 0x66, 0xe0, 0x1e, 0x4a, 0x01, 0x20, 0x28, 0x76, 0x20, 0x32, + 0xd0, 0x77, 0x30, 0x7a, /// 0x2940 + 0x02, 0x07, 0x0a, 0xd5, 0x80, 0x07, 0x01, 0xd5, 0x01, 0x26, 0x18, 0xe0, + 0x18, 0x4a, 0x02, 0x26, /// 0x2950 + 0x80, 0x32, 0x50, 0x7d, 0x40, 0x1c, 0x50, 0x75, 0x11, 0xe0, 0x16, 0x4a, + 0x00, 0x26, 0xc0, 0x32, /// 0x2960 + 0x10, 0x79, 0x83, 0x07, 0x0b, 0xd1, 0x00, 0x9b, 0x5b, 0x7b, 0x1b, 0x07, + 0x07, 0xd5, 0x06, 0x23, /// 0x2970 + 0x18, 0x43, 0x10, 0x71, 0x19, 0x48, 0x00, 0x68, 0xa8, 0x64, 0x00, 0x20, + 0x50, 0x71, 0x28, 0x78, /// 0x2980 + 0x00, 0x06, 0x00, 0xd5, 0x64, 0x08, 0x20, 0x46, 0x08, 0x43, 0xfe, 0xf7, + 0x31, 0xfa, 0xa9, 0x7a, /// 0x2990 + 0x7d, 0x20, 0xc0, 0x00, 0x41, 0x43, 0x20, 0x04, 0xfe, 0xf7, 0x68, 0xfd, + 0x10, 0x49, 0x88, 0x42, /// 0x29a0 + 0x00, 0xd9, 0x08, 0x46, 0x0f, 0x4a, 0x1f, 0xe0, 0x88, 0x13, 0x00, 0x00, + 0x6c, 0x07, 0x00, 0x00, /// 0x29b0 + 0x30, 0x03, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0xf9, 0x6e, 0xd4, 0xc1, + 0xe3, 0x2a, 0xb7, 0x58, /// 0x29c0 + 0xdc, 0x05, 0x00, 0x00, 0x20, 0x38, 0x00, 0x40, 0x00, 0x30, 0x00, 0x40, + 0x00, 0x34, 0x00, 0x40, /// 0x29d0 + 0x52, 0x03, 0x00, 0x00, 0x30, 0x01, 0x00, 0x20, 0xe8, 0x26, 0x00, 0x00, + 0x30, 0x02, 0x00, 0x20, /// 0x29e0 + 0xff, 0xff, 0x00, 0x00, 0x0c, 0x31, 0x00, 0x00, 0x01, 0x99, 0x8a, 0x85, + 0xbe, 0x73, 0x01, 0x0a, /// 0x29f0 + 0xf9, 0x73, 0x38, 0x74, 0x03, 0x20, 0x11, 0xe0, 0xfe, 0x48, 0x84, 0x42, + 0x00, 0xd9, 0x04, 0x46, /// 0x2a00 + 0x64, 0x08, 0x20, 0x46, 0x08, 0x43, 0xfe, 0xf7, 0xf3, 0xf9, 0xe0, 0x01, + 0xfa, 0x49, 0xfe, 0xf7, /// 0x2a10 + 0x2d, 0xfd, 0x01, 0x99, 0xf9, 0x4a, 0x8a, 0x85, 0xb8, 0x73, 0x01, 0x20, + 0xfe, 0xf7, 0x61, 0xf8, /// 0x2a20 + 0xfe, 0xbd, 0x10, 0xb5, 0xf6, 0x48, 0x01, 0x22, 0x41, 0x7b, 0x49, 0x1e, + 0xc9, 0xb2, 0x41, 0x73, /// 0x2a30 + 0x8b, 0x07, 0xf4, 0x48, 0x00, 0x2b, 0x03, 0xda, 0x81, 0x8b, 0x11, 0x43, + 0x81, 0x83, 0x10, 0xbd, /// 0x2a40 + 0xcb, 0x07, 0xf1, 0x49, 0x0c, 0xd0, 0x03, 0x8b, 0x8b, 0x43, 0x09, 0x21, + 0x09, 0x02, 0x59, 0x18, /// 0x2a50 + 0x01, 0x83, 0xee, 0x48, 0x82, 0x80, 0x01, 0x88, 0x30, 0x22, 0x91, 0x43, + 0x01, 0x80, 0x10, 0xbd, /// 0x2a60 + 0x02, 0x8b, 0x8a, 0x43, 0x1b, 0x21, 0x09, 0x02, 0x51, 0x18, 0x01, 0x83, + 0xe8, 0x48, 0x40, 0x7b, /// 0x2a70 + 0x00, 0x07, 0x04, 0xd4, 0xe7, 0x48, 0x01, 0x78, 0x04, 0x22, 0x11, 0x43, + 0x01, 0x70, 0xe0, 0x49, /// 0x2a80 + 0x0a, 0x20, 0xc0, 0x31, 0x08, 0x75, 0xe2, 0x48, 0x10, 0x22, 0x40, 0x30, + 0x01, 0x78, 0x11, 0x43, /// 0x2a90 + 0x01, 0x70, 0x80, 0x38, 0x81, 0x8e, 0x40, 0x22, 0x11, 0x43, 0x81, 0x86, + 0x10, 0x46, 0xfd, 0xf7, /// 0x2aa0 + 0x78, 0xfe, 0x10, 0xbd, 0xf0, 0xb5, 0xd6, 0x48, 0x8b, 0xb0, 0x40, 0x7b, + 0x80, 0x07, 0x03, 0xd0, /// 0x2ab0 + 0xff, 0xf7, 0xb7, 0xff, 0x0b, 0xb0, 0xf0, 0xbd, 0xd5, 0x4f, 0xd1, 0x49, + 0x80, 0x37, 0x38, 0x79, /// 0x2ac0 + 0xc0, 0x39, 0x3c, 0x46, 0x82, 0x07, 0x40, 0x3c, 0x06, 0x91, 0x00, 0x2a, + 0x1a, 0xda, 0x09, 0x68, /// 0x2ad0 + 0xa2, 0x6c, 0x89, 0x1a, 0xff, 0x22, 0x2d, 0x32, 0x91, 0x42, 0x13, 0xd9, + 0x79, 0x79, 0x03, 0x29, /// 0x2ae0 + 0x01, 0xd2, 0x04, 0x21, 0x0c, 0xe0, 0xca, 0x49, 0x01, 0x20, 0x40, 0x39, + 0x8a, 0x8e, 0x00, 0x03, /// 0x2af0 + 0x02, 0x43, 0x8a, 0x86, 0xfd, 0xf7, 0x4d, 0xfe, 0x38, 0x79, 0xfd, 0x21, + 0x08, 0x40, 0x01, 0x21, /// 0x2b00 + 0x08, 0x43, 0x38, 0x71, 0x60, 0x78, 0x41, 0x06, 0x13, 0xd5, 0x06, 0x99, + 0xa2, 0x6c, 0x09, 0x68, /// 0x2b10 + 0x89, 0x1a, 0xff, 0x22, 0xf5, 0x32, 0x91, 0x42, 0x0b, 0xd9, 0xbf, 0x21, + 0x08, 0x40, 0xbc, 0x49, /// 0x2b20 + 0x60, 0x70, 0x40, 0x39, 0x8a, 0x8e, 0xff, 0x20, 0x01, 0x30, 0x02, 0x43, + 0x8a, 0x86, 0xfd, 0xf7, /// 0x2b30 + 0x30, 0xfe, 0x20, 0x7e, 0x00, 0x28, 0x02, 0xd0, 0xff, 0xf7, 0x30, 0xfe, + 0xba, 0xe7, 0x06, 0x98, /// 0x2b40 + 0xaf, 0x4d, 0x00, 0x68, 0x40, 0x3d, 0x00, 0x90, 0xe9, 0x6d, 0x0a, 0x22, + 0x41, 0x1a, 0x28, 0x46, /// 0x2b50 + 0x80, 0x30, 0x08, 0x90, 0x82, 0x5e, 0x00, 0x98, 0x91, 0x42, 0x03, 0xdb, + 0xe8, 0x65, 0x48, 0x20, /// 0x2b60 + 0x20, 0x76, 0xe9, 0xe7, 0xa9, 0x6d, 0xa6, 0x4e, 0x41, 0x1a, 0xa9, 0x48, + 0x6a, 0x6e, 0x20, 0x38, /// 0x2b70 + 0x60, 0x36, 0x05, 0x90, 0x91, 0x42, 0x7d, 0xdb, 0x00, 0x98, 0xa8, 0x65, + 0x60, 0x78, 0x01, 0x07, /// 0x2b80 + 0x0b, 0xd5, 0xf7, 0x21, 0x08, 0x40, 0x32, 0x21, 0x69, 0x66, 0x10, 0x21, + 0x08, 0x43, 0x60, 0x70, /// 0x2b90 + 0x00, 0x20, 0xb8, 0x81, 0xff, 0xf7, 0xe8, 0xfd, 0x8c, 0xe7, 0x39, 0x79, + 0x0a, 0x07, 0x0f, 0xd5, /// 0x2ba0 + 0xa2, 0x78, 0x93, 0x06, 0x0c, 0xd5, 0xdf, 0x21, 0x0a, 0x40, 0xa2, 0x70, + 0x32, 0x21, 0x69, 0x66, /// 0x2bb0 + 0x40, 0x21, 0x08, 0x43, 0x60, 0x70, 0x00, 0x98, 0xa0, 0x64, 0xff, 0xf7, + 0xb0, 0xfd, 0x79, 0xe7, /// 0x2bc0 + 0x82, 0x06, 0x08, 0xd5, 0xdf, 0x21, 0x08, 0x40, 0x60, 0x70, 0x32, 0x20, + 0x68, 0x66, 0xff, 0x20, /// 0x2bd0 + 0xfe, 0xf7, 0x22, 0xfc, 0x6e, 0xe7, 0x48, 0x07, 0x0d, 0xd5, 0xfb, 0x20, + 0x01, 0x40, 0x39, 0x71, /// 0x2be0 + 0x32, 0x20, 0x68, 0x66, 0xff, 0xf7, 0x71, 0xfd, 0x06, 0x98, 0x00, 0x68, + 0xa0, 0x64, 0x78, 0x79, /// 0x2bf0 + 0x40, 0x1c, 0x78, 0x71, 0x5e, 0xe7, 0x08, 0x07, 0x23, 0xd5, 0xa7, 0x78, + 0xf8, 0x07, 0x20, 0xd0, /// 0x2c00 + 0x83, 0x48, 0x09, 0x90, 0x00, 0x8f, 0x64, 0x21, 0xfe, 0xf7, 0x30, 0xfc, + 0x05, 0x99, 0x89, 0x7f, /// 0x2c10 + 0x08, 0x1a, 0x79, 0x08, 0x49, 0x00, 0x23, 0x30, 0xa1, 0x70, 0x00, 0x28, + 0x00, 0xdc, 0x40, 0x42, /// 0x2c20 + 0x14, 0x28, 0x2d, 0xdb, 0x32, 0x20, 0x68, 0x66, 0x09, 0x98, 0x02, 0x88, + 0x74, 0x48, 0xc0, 0x30, /// 0x2c30 + 0xc2, 0x80, 0x02, 0x22, 0x11, 0x43, 0xa1, 0x70, 0x00, 0x99, 0x81, 0x60, + 0xff, 0xf7, 0x2e, 0xfd, /// 0x2c40 + 0x38, 0xe7, 0x73, 0x48, 0x40, 0x38, 0x00, 0x8d, 0x00, 0x28, 0x0a, 0xd0, + 0x70, 0x7f, 0x07, 0x28, /// 0x2c50 + 0x07, 0xd2, 0xb0, 0x7f, 0x0a, 0x28, 0x18, 0xd2, 0xff, 0xf7, 0x81, 0xfb, + 0xc0, 0x1d, 0x0e, 0x28, /// 0x2c60 + 0x0e, 0xd9, 0x00, 0x20, 0x70, 0x77, 0x30, 0x7f, 0x00, 0x28, 0x01, 0xd0, + 0x40, 0x1e, 0x30, 0x77, /// 0x2c70 + 0x06, 0x98, 0x00, 0xe0, 0x04, 0xe0, 0x00, 0x68, 0xa8, 0x65, 0xff, 0xf7, + 0xe5, 0xfb, 0x19, 0xe7, /// 0x2c80 + 0x63, 0x48, 0x40, 0x38, 0x00, 0x8d, 0x00, 0x28, 0x86, 0xd0, 0x70, 0x7f, + 0x60, 0x49, 0x40, 0x1c, /// 0x2c90 + 0x70, 0x77, 0x40, 0x39, 0x08, 0x8d, 0x80, 0x22, 0x83, 0x06, 0x00, 0x2b, + 0x39, 0xd0, 0xc3, 0x07, /// 0x2ca0 + 0x04, 0xd0, 0x01, 0x20, 0x48, 0x85, 0xf0, 0x77, 0x03, 0x20, 0x4a, 0xe0, + 0x83, 0x07, 0x05, 0xd5, /// 0x2cb0 + 0x02, 0x20, 0x48, 0x85, 0x01, 0x20, 0xf0, 0x77, 0x05, 0x20, 0x42, 0xe0, + 0x43, 0x07, 0x04, 0xd5, /// 0x2cc0 + 0x04, 0x22, 0x90, 0x43, 0x08, 0x85, 0x02, 0x20, 0x3b, 0xe0, 0x03, 0x07, + 0x04, 0xd5, 0x08, 0x22, /// 0x2cd0 + 0x90, 0x43, 0x08, 0x85, 0x01, 0x20, 0x34, 0xe0, 0xc3, 0x06, 0x0e, 0xd5, + 0x05, 0x9a, 0x92, 0x79, /// 0x2ce0 + 0x52, 0x06, 0x04, 0xd5, 0x10, 0x20, 0x48, 0x85, 0x01, 0x20, 0xf0, 0x77, + 0x02, 0xe0, 0x10, 0x22, /// 0x2cf0 + 0x90, 0x43, 0x08, 0x85, 0xff, 0xf7, 0x1f, 0xfb, 0xdc, 0xe6, 0x83, 0x06, + 0x09, 0xd5, 0x20, 0x20, /// 0x2d00 + 0x48, 0x85, 0x01, 0x20, 0xf0, 0x77, 0x05, 0x98, 0x00, 0x7b, 0x40, 0x1e, + 0x10, 0x43, 0xc0, 0xb2, /// 0x2d10 + 0x17, 0xe0, 0xc0, 0x22, 0x02, 0x40, 0x20, 0xd0, 0xc0, 0x2a, 0x06, 0xd1, + 0x05, 0x9a, 0xd2, 0x79, /// 0x2d20 + 0x52, 0x07, 0x01, 0xd5, 0x40, 0x22, 0x00, 0xe0, 0x80, 0x22, 0x52, 0x06, + 0x0c, 0xd5, 0x40, 0x22, /// 0x2d30 + 0x90, 0x43, 0x08, 0x85, 0x05, 0x98, 0xfb, 0x21, 0xc0, 0x79, 0x08, 0x40, + 0x05, 0x99, 0xc8, 0x71, /// 0x2d40 + 0x06, 0x20, 0xff, 0xf7, 0xec, 0xfa, 0xb5, 0xe6, 0x05, 0x98, 0x04, 0x21, + 0xc0, 0x79, 0x08, 0x43, /// 0x2d50 + 0x05, 0x99, 0xc8, 0x71, 0xff, 0xf7, 0xcd, 0xfa, 0xac, 0xe6, 0xc2, 0x05, + 0x06, 0xd5, 0xff, 0x22, /// 0x2d60 + 0x01, 0x32, 0x90, 0x43, 0x08, 0x85, 0xff, 0xf7, 0xb5, 0xfa, 0xa3, 0xe6, + 0x82, 0x05, 0x86, 0xd5, /// 0x2d70 + 0x06, 0x9a, 0xab, 0x6d, 0x12, 0x68, 0xd3, 0x1a, 0x64, 0x2b, 0xbd, 0xda, + 0xeb, 0x6d, 0x0a, 0x24, /// 0x2d80 + 0x9b, 0x1a, 0x08, 0x9a, 0x14, 0x5f, 0x1a, 0x19, 0xff, 0x23, 0x5f, 0x33, + 0x9a, 0x42, 0xb3, 0xdd, /// 0x2d90 + 0x01, 0x22, 0x52, 0x02, 0x90, 0x43, 0x08, 0x85, 0x19, 0x48, 0x06, 0x21, + 0x80, 0x38, 0x81, 0x72, /// 0x2da0 + 0xff, 0xf7, 0x8c, 0xfa, 0x86, 0xe6, 0x16, 0x48, 0x10, 0xb5, 0x1b, 0x49, + 0x40, 0x38, 0xc1, 0x62, /// 0x2db0 + 0x17, 0x48, 0x40, 0x30, 0xc1, 0x78, 0x12, 0x48, 0x20, 0x38, 0xc1, 0x73, + 0x10, 0x49, 0x01, 0x20, /// 0x2dc0 + 0x60, 0x31, 0xc8, 0x77, 0x02, 0x20, 0xfd, 0xf7, 0x8c, 0xfe, 0x10, 0xbd, + 0xf0, 0xb5, 0x09, 0x22, /// 0x2dd0 + 0x12, 0x49, 0x92, 0x01, 0x0a, 0x4c, 0x8a, 0x18, 0x15, 0x78, 0x20, 0x7c, + 0x13, 0x22, 0x52, 0x01, /// 0x2de0 + 0xc3, 0x07, 0x8a, 0x18, 0x87, 0xb0, 0x00, 0x2b, 0x25, 0xd0, 0x00, 0x2d, + 0x23, 0xd1, 0xd1, 0x79, /// 0x2df0 + 0x49, 0x1c, 0x15, 0xe0, 0xd0, 0x4d, 0x00, 0x00, 0x88, 0x13, 0x00, 0x00, + 0x0c, 0x04, 0x00, 0x00, /// 0x2e00 + 0xf0, 0x02, 0x00, 0x20, 0x00, 0x30, 0x00, 0x40, 0x00, 0x1f, 0x00, 0x00, + 0x00, 0x34, 0x00, 0x40, /// 0x2e10 + 0x40, 0x00, 0x00, 0x20, 0x40, 0x6c, 0x00, 0x40, 0x0c, 0x22, 0x00, 0x00, + 0x30, 0x01, 0x00, 0x20, /// 0x2e20 + 0xc9, 0xb2, 0xd1, 0x71, 0x03, 0x29, 0x02, 0xd2, 0x40, 0x1e, 0x20, 0x74, + 0x03, 0xe0, 0x40, 0x1c, /// 0x2e30 + 0x20, 0x74, 0x00, 0x20, 0xd0, 0x71, 0xbd, 0x4e, 0x27, 0x7c, 0x30, 0x7d, + 0x05, 0x90, 0x70, 0x7d, /// 0x2e40 + 0x01, 0x90, 0xbb, 0x48, 0x01, 0x46, 0xa0, 0x31, 0x80, 0x30, 0x00, 0x91, + 0xc1, 0x7b, 0x04, 0x91, /// 0x2e50 + 0x81, 0x7b, 0x02, 0x91, 0x41, 0x7b, 0x03, 0x7b, 0x03, 0x93, 0x3b, 0x00, + 0xfe, 0xf7, 0x30, 0xfb, /// 0x2e60 + 0x11, 0x0a, 0x0d, 0x13, 0x15, 0x1f, 0x23, 0x36, 0x3e, 0x43, 0x4a, 0x60, + 0x68, 0x6d, 0x78, 0x7d, /// 0x2e70 + 0x82, 0xa8, 0xaa, 0x00, 0xff, 0xf7, 0x97, 0xff, 0x9c, 0xe0, 0xa8, 0x07, + 0x00, 0xd5, 0xfe, 0xe7, /// 0x2e80 + 0x00, 0x20, 0xd0, 0x71, 0x96, 0xe0, 0x30, 0x20, 0x0a, 0xe0, 0x05, 0x99, + 0x30, 0x29, 0xf7, 0xd1, /// 0x2e90 + 0x00, 0x99, 0x01, 0x9b, 0x4b, 0x72, 0xf1, 0x8a, 0x49, 0xba, 0x41, 0x84, + 0xf0, 0xe7, 0x31, 0x20, /// 0x2ea0 + 0xff, 0xf7, 0x93, 0xf9, 0x86, 0xe0, 0x05, 0x9b, 0x31, 0x2b, 0xe9, 0xd1, + 0x01, 0x9d, 0x05, 0x71, /// 0x2eb0 + 0xb3, 0x7d, 0x43, 0x71, 0xf6, 0x7d, 0x86, 0x71, 0x8d, 0x42, 0x02, 0xd2, + 0x8b, 0x42, 0x00, 0xd2, /// 0x2ec0 + 0x43, 0x73, 0x02, 0x99, 0x8b, 0x42, 0xdb, 0xd2, 0x83, 0x73, 0xd9, 0xe7, + 0x00, 0x7a, 0x03, 0x99, /// 0x2ed0 + 0x81, 0x42, 0x01, 0xd0, 0x02, 0x20, 0x35, 0xe0, 0x07, 0x20, 0x37, 0xe0, + 0xe8, 0x07, 0xcf, 0xd0, /// 0x2ee0 + 0x03, 0x98, 0x10, 0x72, 0xcc, 0xe7, 0x40, 0x7a, 0x81, 0x42, 0x01, 0xd0, + 0x01, 0x20, 0x29, 0xe0, /// 0x2ef0 + 0x09, 0x20, 0x2b, 0xe0, 0x8e, 0x4b, 0xed, 0x07, 0x80, 0x33, 0x1b, 0x79, + 0x00, 0x2d, 0x09, 0xd0, /// 0x2f00 + 0x51, 0x72, 0x8b, 0x42, 0x00, 0xd2, 0x01, 0x71, 0x41, 0x8c, 0x27, 0x29, + 0xb8, 0xd1, 0x04, 0x21, /// 0x2f10 + 0x01, 0x71, 0xb5, 0xe7, 0x99, 0x42, 0xb3, 0xd9, 0x43, 0x73, 0x08, 0x20, + 0x20, 0x74, 0xaf, 0xe7, /// 0x2f20 + 0x80, 0x7a, 0x02, 0x99, 0x81, 0x42, 0x01, 0xd0, 0x04, 0x20, 0x0b, 0xe0, + 0x0b, 0x20, 0x0d, 0xe0, /// 0x2f30 + 0xe8, 0x07, 0xa5, 0xd0, 0x02, 0x98, 0x90, 0x72, 0xa2, 0xe7, 0xc0, 0x7a, + 0x04, 0x99, 0x81, 0x42, /// 0x2f40 + 0x03, 0xd0, 0x03, 0x20, 0xff, 0xf7, 0x31, 0xf9, 0x34, 0xe0, 0x0d, 0x20, + 0x20, 0x74, 0x31, 0xe0, /// 0x2f50 + 0xe8, 0x07, 0x95, 0xd0, 0x04, 0x98, 0xd0, 0x72, 0x92, 0xe7, 0xff, 0xf7, + 0x14, 0xf9, 0xc1, 0xb2, /// 0x2f60 + 0x00, 0x20, 0xef, 0xe7, 0xe9, 0x07, 0x1c, 0xd0, 0xb1, 0x6e, 0x81, 0x60, + 0xff, 0x20, 0xc3, 0x30, /// 0x2f70 + 0x70, 0x81, 0x70, 0x48, 0x01, 0x68, 0x80, 0x30, 0x0a, 0x46, 0xff, 0x3a, + 0x2d, 0x3a, 0xc2, 0x65, /// 0x2f80 + 0x01, 0x66, 0x42, 0x6e, 0x89, 0x1a, 0x81, 0x65, 0x6a, 0x49, 0x05, 0x20, + 0x40, 0x31, 0x88, 0x72, /// 0x2f90 + 0x00, 0x98, 0x0f, 0x21, 0x01, 0x72, 0x68, 0x48, 0x01, 0x78, 0x04, 0x22, + 0x11, 0x43, 0x01, 0x70, /// 0x2fa0 + 0x08, 0xe0, 0xa9, 0x07, 0x06, 0xd5, 0x80, 0x68, 0xb0, 0x66, 0x00, 0x20, + 0xd0, 0x71, 0x03, 0xe0, /// 0x2fb0 + 0xfe, 0xf7, 0x6b, 0xfb, 0x20, 0x7c, 0x40, 0x1c, 0x20, 0x74, 0x07, 0xb0, + 0xf0, 0xbd, 0xf8, 0xb5, /// 0x2fc0 + 0x5b, 0x4c, 0x80, 0x34, 0xa2, 0x78, 0x90, 0x07, 0x60, 0xd5, 0x58, 0x4d, + 0x20, 0x46, 0x40, 0x38, /// 0x2fd0 + 0x80, 0x35, 0x01, 0x88, 0xeb, 0x88, 0xc9, 0x1a, 0x00, 0x29, 0x00, 0xdc, + 0x49, 0x42, 0x54, 0x4b, /// 0x2fe0 + 0x53, 0x4f, 0xc0, 0x33, 0xdb, 0x89, 0xbe, 0x8e, 0x99, 0x42, 0x31, 0xdd, + 0xfd, 0x21, 0x0a, 0x40, /// 0x2ff0 + 0xa2, 0x70, 0x00, 0x8f, 0x64, 0x21, 0x00, 0x90, 0xfe, 0xf7, 0x38, 0xfa, + 0x3d, 0x46, 0x20, 0x35, /// 0x3000 + 0x23, 0x38, 0x29, 0x46, 0xa8, 0x77, 0x40, 0x31, 0xc8, 0x70, 0xaf, 0x21, + 0x00, 0x98, 0x09, 0x01, /// 0x3010 + 0x40, 0x1a, 0x19, 0x21, 0xfe, 0xf7, 0x40, 0xfa, 0x48, 0x49, 0x08, 0x82, + 0x08, 0x20, 0x06, 0x43, /// 0x3020 + 0xbe, 0x86, 0xfd, 0xf7, 0xb6, 0xfb, 0xa9, 0x7f, 0x28, 0x46, 0x80, 0x30, + 0x73, 0x29, 0x02, 0xd1, /// 0x3030 + 0xe9, 0x7f, 0x00, 0x29, 0x06, 0xd0, 0x21, 0x78, 0x49, 0x06, 0x49, 0x0e, + 0x21, 0x70, 0x48, 0x21, /// 0x3040 + 0xc1, 0x72, 0x23, 0xe0, 0x21, 0x78, 0x80, 0x22, 0x11, 0x43, 0x21, 0x70, + 0x30, 0x21, 0xf7, 0xe7, /// 0x3050 + 0x38, 0x49, 0x3b, 0x4b, 0x0a, 0x68, 0xa9, 0x68, 0x51, 0x1a, 0x99, 0x42, + 0x16, 0xdd, 0x69, 0x79, /// 0x3060 + 0x02, 0x29, 0x07, 0xd2, 0xc3, 0x89, 0x80, 0x24, 0x23, 0x43, 0xc3, 0x81, + 0x49, 0x1c, 0xaa, 0x60, /// 0x3070 + 0x69, 0x71, 0x0b, 0xe0, 0x01, 0x20, 0xc0, 0x03, 0x06, 0x43, 0xbe, 0x86, + 0xfd, 0xf7, 0x89, 0xfb, /// 0x3080 + 0xa0, 0x78, 0xfd, 0x21, 0x08, 0x40, 0xa0, 0x70, 0x00, 0x20, 0x68, 0x71, + 0x00, 0x20, 0xf8, 0xbd, /// 0x3090 + 0x70, 0xb5, 0x27, 0x49, 0x9f, 0x23, 0x80, 0x31, 0x4a, 0x78, 0x1a, 0x40, + 0x4a, 0x70, 0x0b, 0x46, /// 0x30a0 + 0x20, 0x33, 0x1c, 0x7c, 0x05, 0x78, 0x80, 0x39, 0x8a, 0x8e, 0xac, 0x42, + 0x0e, 0xd1, 0x5c, 0x7c, /// 0x30b0 + 0x45, 0x78, 0xac, 0x42, 0x0a, 0xd1, 0x9c, 0x7c, 0x85, 0x78, 0xac, 0x42, + 0x06, 0xd1, 0xdb, 0x7c, /// 0x30c0 + 0xc0, 0x78, 0x83, 0x42, 0x02, 0xd1, 0x01, 0x20, 0x40, 0x02, 0x01, 0xe0, + 0xff, 0x20, 0x01, 0x30, /// 0x30d0 + 0x02, 0x43, 0x8a, 0x86, 0xfd, 0xf7, 0x5d, 0xfb, 0x70, 0xbd, 0x70, 0xb5, + 0x14, 0x48, 0xdf, 0x22, /// 0x30e0 + 0x80, 0x30, 0x41, 0x78, 0x04, 0x46, 0x11, 0x40, 0x41, 0x70, 0x40, 0x3c, + 0x60, 0x7e, 0x3b, 0x28, /// 0x30f0 + 0x15, 0xd1, 0x23, 0x46, 0x80, 0x33, 0x18, 0x79, 0xfd, 0x21, 0x08, 0x40, + 0x01, 0x21, 0x08, 0x43, /// 0x3100 + 0x18, 0x71, 0x0b, 0x49, 0xa5, 0x7e, 0x8a, 0x8e, 0x02, 0x2d, 0x02, 0xd1, + 0xe4, 0x7e, 0xbb, 0x2c, /// 0x3110 + 0x06, 0xd0, 0x01, 0x20, 0x00, 0x03, 0x02, 0x43, 0x8a, 0x86, 0xfd, 0xf7, + 0x3a, 0xfb, 0x70, 0xbd, /// 0x3120 + 0x08, 0x24, 0x20, 0x43, 0x18, 0x71, 0xa0, 0x02, 0xf5, 0xe7, 0x00, 0x00, + 0x30, 0x03, 0x00, 0x20, /// 0x3130 + 0x00, 0x00, 0x00, 0x20, 0x30, 0x02, 0x00, 0x20, 0x40, 0x6c, 0x00, 0x40, + 0x00, 0x30, 0x00, 0x40, /// 0x3140 + 0xdc, 0x05, 0x00, 0x00, 0x94, 0x28, 0x94, 0x1f, 0x94, 0x15, 0x94, 0x15, + 0x94, 0x0f, 0x94, 0x14, /// 0x3150 + 0x14, 0x14, 0x00, 0x00, 0x93, 0x3e, 0x85, 0x4d, 0x89, 0x43, 0x86, 0x55, + 0x86, 0x5c, 0x86, 0x60, /// 0x3160 + 0x14, 0x00, 0x01, 0x50, 0x01, 0x00, 0x01, 0x00, 0x4e, 0x6f, 0x76, 0x20, + 0x32, 0x31, 0x20, 0x32, /// 0x3170 + 0x30, 0x31, 0x38, 0x00, 0x31, 0x34, 0x3a, 0x33, 0x39, 0x3a, 0x35, 0x36, +}; + +unsigned char idt_firmware_sram[] = { + 0x0c, 0x0b, 0x00, 0x20, 0x30, 0x11, 0x00, 0x20, + 0x08, 0x1d, 0x00, 0x00, 0xac, 0x29, 0x00, 0x00, /// 0x4010 + 0x09, 0x09, 0x00, 0x20, 0x97, 0x1a, 0x00, 0x00, + 0xa3, 0x1e, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /// 0x4020 + 0x20, 0x92, 0x02, 0x00, 0x87, 0x01, 0x01, 0x02, + 0xf3, 0x04, 0x1e, 0x12, 0xd4, 0x01, 0x09, 0x00, /// 0x4030 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x13, + 0x78, 0x05, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, /// 0x4040 + 0x23, 0x01, 0x9a, 0x02, 0x90, 0x01, 0xe8, 0x03, + 0x4c, 0x1d, 0x08, 0xff, 0x00, 0x00, 0x00, 0x00, /// 0x4050 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /// 0x4060 + 0x70, 0xb5, 0x72, 0xb6, 0x23, 0x48, 0x22, 0x49, + 0x41, 0x60, 0x23, 0x49, 0x23, 0x4c, 0x81, 0x67, /// 0x4070 + 0x23, 0x4d, 0x62, 0xb6, 0x60, 0x68, 0x21, 0x46, + 0xe8, 0x61, 0x10, 0x22, 0x08, 0x31, 0x21, 0x48, /// 0x4080 + 0x00, 0xf0, 0xea, 0xf9, 0x20, 0x49, 0x08, 0x78, + 0x00, 0x28, 0x00, 0xd1, 0x1f, 0x49, 0x1c, 0x48, /// 0x4090 + 0x10, 0x22, 0x68, 0x30, 0x00, 0xf0, 0xe6, 0xf9, + 0xa0, 0x78, 0xe8, 0x70, 0x58, 0x20, 0x28, 0x87, /// 0x40a0 + 0x20, 0x8b, 0x64, 0x21, 0x00, 0xf0, 0xe4, 0xf9, + 0x15, 0x49, 0x40, 0x1e, 0x40, 0x31, 0x88, 0x72, /// 0x40b0 + 0x13, 0x48, 0xa1, 0x7e, 0x60, 0x30, 0x81, 0x70, + 0x15, 0x49, 0x20, 0x20, 0x08, 0x81, 0x60, 0x22, /// 0x40c0 + 0x8a, 0x83, 0x13, 0x49, 0x20, 0x31, 0x8a, 0x89, + 0x02, 0x43, 0x8a, 0x81, 0xe0, 0x8a, 0x64, 0x21, /// 0x40d0 + 0x00, 0xf0, 0xce, 0xf9, 0x0a, 0x49, 0x21, 0x38, + 0x20, 0x31, 0x88, 0x77, 0xe0, 0x8a, 0xaf, 0x21, /// 0x40e0 + 0x09, 0x01, 0x40, 0x1a, 0x19, 0x21, 0x00, 0xf0, + 0xc9, 0xf9, 0x0a, 0x49, 0x08, 0x82, 0x70, 0xbd, /// 0x40f0 + 0x09, 0x09, 0x00, 0x20, 0x00, 0x01, 0x00, 0x20, + 0x0d, 0x0b, 0x00, 0x20, 0x20, 0x06, 0x00, 0x20, /// 0x4100 + 0x00, 0x00, 0x00, 0x20, 0xb0, 0x00, 0x00, 0x20, + 0x60, 0x3e, 0x00, 0x00, 0x20, 0x11, 0x00, 0x20, /// 0x4110 + 0x00, 0x6c, 0x00, 0x40, 0x00, 0x30, 0x00, 0x40, + 0x10, 0xb5, 0xc1, 0x48, 0x0c, 0x21, 0x01, 0x73, /// 0x4120 + 0x38, 0x21, 0x41, 0x73, 0x0a, 0x21, 0x81, 0x73, + 0xbe, 0x49, 0x09, 0x8f, 0xc1, 0x73, 0x09, 0x0a, /// 0x4130 + 0x01, 0x74, 0x03, 0x20, 0x00, 0xf0, 0xa8, 0xf9, + 0x10, 0xbd, 0xf8, 0xb5, 0xb8, 0x49, 0x20, 0x31, /// 0x4140 + 0x48, 0x7b, 0xc2, 0x06, 0x0e, 0xd5, 0xef, 0x22, + 0x10, 0x40, 0x48, 0x73, 0xb5, 0x48, 0x80, 0x22, /// 0x4150 + 0x40, 0x38, 0x81, 0x8e, 0x11, 0x43, 0x81, 0x86, + 0xb3, 0x48, 0x81, 0x89, 0x04, 0x22, 0x11, 0x43, /// 0x4160 + 0x81, 0x81, 0xf8, 0xbd, 0x43, 0x07, 0xfb, 0x22, + 0x00, 0x2b, 0x0b, 0xda, 0x10, 0x40, 0x10, 0x22, /// 0x4170 + 0x10, 0x43, 0x48, 0x73, 0xad, 0x48, 0x01, 0x21, + 0x81, 0x80, 0x01, 0x88, 0x30, 0x22, 0x91, 0x43, /// 0x4180 + 0x01, 0x80, 0xf8, 0xbd, 0xaa, 0x48, 0x01, 0x7e, + 0x00, 0x29, 0x02, 0xd0, 0x00, 0xf0, 0x52, 0xfb, /// 0x4190 + 0xf8, 0xbd, 0xa3, 0x49, 0xa2, 0x4c, 0x80, 0x39, + 0x0d, 0x68, 0xe1, 0x6b, 0xa5, 0x4b, 0x69, 0x1a, /// 0x41a0 + 0x99, 0x42, 0x03, 0xdb, 0x48, 0x21, 0xe5, 0x63, + 0x01, 0x76, 0xef, 0xe7, 0xa0, 0x6b, 0x21, 0x6c, /// 0x41b0 + 0x28, 0x1a, 0x88, 0x42, 0xec, 0xdb, 0x9e, 0x48, + 0xa5, 0x63, 0x20, 0x38, 0x41, 0x78, 0x4b, 0x07, /// 0x41c0 + 0x06, 0xd5, 0x11, 0x40, 0x41, 0x70, 0x32, 0x20, + 0x20, 0x64, 0x00, 0xf0, 0x63, 0xf9, 0xf8, 0xbd, /// 0x41d0 + 0x0a, 0x07, 0x07, 0xd5, 0xf7, 0x22, 0x11, 0x40, + 0x41, 0x70, 0x32, 0x20, 0x20, 0x64, 0x00, 0xf0, /// 0x41e0 + 0x5f, 0xf9, 0xf8, 0xbd, 0x86, 0x78, 0x31, 0x07, + 0x89, 0x0f, 0x02, 0xd0, 0x00, 0xf0, 0xcf, 0xfa, /// 0x41f0 + 0xf8, 0xbd, 0x8b, 0x4f, 0xf0, 0x07, 0x80, 0x37, + 0x00, 0x28, 0x22, 0xd0, 0x89, 0x48, 0x00, 0x90, /// 0x4200 + 0x00, 0x8f, 0x64, 0x21, 0x00, 0xf0, 0x34, 0xf9, + 0x86, 0x49, 0x72, 0x08, 0x20, 0x39, 0x89, 0x7f, /// 0x4210 + 0x52, 0x00, 0x08, 0x1a, 0x86, 0x49, 0x23, 0x30, + 0x20, 0x39, 0x8a, 0x70, 0x00, 0x28, 0x00, 0xdc, /// 0x4220 + 0x40, 0x42, 0x14, 0x28, 0xe4, 0xdb, 0x32, 0x20, + 0x20, 0x64, 0x00, 0x98, 0x03, 0x88, 0x7c, 0x48, /// 0x4230 + 0xc0, 0x30, 0x83, 0x80, 0x02, 0x20, 0x02, 0x43, + 0x8a, 0x70, 0x3d, 0x64, 0xff, 0xf7, 0x6c, 0xff, /// 0x4240 + 0xf8, 0xbd, 0x00, 0xf0, 0xba, 0xf9, 0x78, 0x7f, + 0x00, 0x28, 0xf9, 0xd0, 0x40, 0x1e, 0x78, 0x77, /// 0x4250 + 0xf8, 0xbd, 0x10, 0xb5, 0x75, 0x48, 0x00, 0x21, + 0x80, 0x88, 0x00, 0x07, 0x00, 0xd5, 0x02, 0x21, /// 0x4260 + 0x75, 0x48, 0x80, 0x8b, 0xc0, 0x04, 0x01, 0xd5, + 0x01, 0x20, 0x01, 0x43, 0x73, 0x48, 0x80, 0x89, /// 0x4270 + 0xc0, 0x06, 0x01, 0xd5, 0x04, 0x20, 0x01, 0x43, + 0x6a, 0x4b, 0x40, 0x3b, 0x9a, 0x8e, 0x50, 0x07, /// 0x4280 + 0x40, 0x0f, 0x48, 0x40, 0x05, 0xd0, 0xd2, 0x08, + 0xd2, 0x00, 0x0a, 0x43, 0x9a, 0x86, 0x00, 0xf0, /// 0x4290 + 0x0d, 0xf9, 0x10, 0xbd, 0x70, 0xb5, 0x66, 0x4a, + 0x20, 0x3a, 0x93, 0x78, 0x98, 0x07, 0x31, 0xd5, /// 0x42a0 + 0x5f, 0x4c, 0x60, 0x49, 0xc0, 0x34, 0x08, 0x88, + 0xa5, 0x88, 0x40, 0x1b, 0x00, 0x28, 0x00, 0xdc, /// 0x42b0 + 0x40, 0x42, 0x63, 0x4d, 0xa8, 0x42, 0x16, 0xdd, + 0xfd, 0x20, 0x03, 0x40, 0x93, 0x70, 0x0d, 0x8f, /// 0x42c0 + 0x64, 0x21, 0x28, 0x46, 0x00, 0xf0, 0xd4, 0xf8, + 0x56, 0x49, 0x23, 0x38, 0x20, 0x39, 0x88, 0x77, /// 0x42d0 + 0xaf, 0x20, 0x00, 0x01, 0x28, 0x1a, 0x19, 0x21, + 0x00, 0xf0, 0xd0, 0xf8, 0x56, 0x49, 0x08, 0x82, /// 0x42e0 + 0x00, 0x20, 0xa0, 0x71, 0x0e, 0xe0, 0x4e, 0x48, + 0x52, 0x4c, 0x80, 0x38, 0x02, 0x68, 0xff, 0x30, /// 0x42f0 + 0x01, 0x30, 0x03, 0x6c, 0xd3, 0x1a, 0xa3, 0x42, + 0x04, 0xdd, 0x8b, 0x7b, 0x80, 0x24, 0x23, 0x43, /// 0x4300 + 0x8b, 0x73, 0x02, 0x64, 0x00, 0x20, 0x70, 0xbd, + 0xf8, 0xb5, 0x45, 0x48, 0x4d, 0x49, 0x80, 0x38, /// 0x4310 + 0x80, 0x6f, 0x00, 0x26, 0x88, 0x42, 0x14, 0xd1, + 0x41, 0x4a, 0xa0, 0x32, 0x50, 0x79, 0x00, 0x28, /// 0x4320 + 0x14, 0xd0, 0x40, 0x49, 0x20, 0x39, 0x88, 0x79, + 0x43, 0x1c, 0x8b, 0x71, 0x0a, 0x28, 0x08, 0xd9, /// 0x4330 + 0x45, 0x48, 0x01, 0x23, 0x03, 0x80, 0x03, 0x23, + 0x03, 0x80, 0x41, 0x23, 0x03, 0x83, 0x56, 0x71, /// 0x4340 + 0x8e, 0x71, 0x38, 0x4f, 0xb8, 0x7b, 0x00, 0x28, + 0x07, 0xd1, 0x03, 0xe0, 0x3f, 0x48, 0x00, 0xf0, /// 0x4350 + 0xb3, 0xf8, 0xf6, 0xe7, 0x38, 0x7b, 0x00, 0x28, + 0x02, 0xd0, 0x3d, 0x48, 0x00, 0xf0, 0xb2, 0xf8, /// 0x4360 + 0x30, 0x48, 0x40, 0x38, 0x80, 0x8e, 0x00, 0x06, + 0x01, 0xd5, 0xff, 0xf7, 0x93, 0xff, 0xff, 0xf7, /// 0x4370 + 0x70, 0xff, 0x2b, 0x4d, 0x20, 0x35, 0x28, 0x7a, + 0x00, 0x28, 0x4e, 0xd1, 0xe8, 0x7a, 0x2c, 0x46, /// 0x4380 + 0x60, 0x3c, 0x00, 0x28, 0x11, 0xd0, 0x40, 0x1e, + 0xe8, 0x72, 0xa0, 0x7a, 0x05, 0x28, 0x44, 0xd1, /// 0x4390 + 0x30, 0x48, 0x00, 0xf0, 0x97, 0xf8, 0x28, 0x7b, + 0xe9, 0x7a, 0x40, 0x1e, 0x81, 0x42, 0x3c, 0xd1, /// 0x43a0 + 0x20, 0x46, 0x80, 0x30, 0x06, 0x86, 0x86, 0x85, + 0x37, 0xe0, 0xa0, 0x7a, 0x1c, 0x4e, 0x03, 0x00, /// 0x43b0 + 0x00, 0xf0, 0x8e, 0xf8, 0x07, 0x05, 0x16, 0x1a, + 0x1e, 0x22, 0x2e, 0x31, 0x33, 0x00, 0x18, 0x48, /// 0x43c0 + 0x79, 0x7b, 0x80, 0x38, 0x00, 0x68, 0xc9, 0x06, + 0x01, 0xd5, 0x1d, 0x21, 0x00, 0xe0, 0x03, 0x21, /// 0x43d0 + 0x88, 0x42, 0x22, 0xd9, 0x08, 0x20, 0x28, 0x73, + 0x32, 0x20, 0x30, 0x64, 0x01, 0x20, 0x15, 0xe0, /// 0x43e0 + 0x00, 0xf0, 0x7c, 0xf8, 0x02, 0x20, 0x11, 0xe0, + 0x00, 0xf0, 0x7e, 0xf8, 0x03, 0x20, 0x0d, 0xe0, /// 0x43f0 + 0x00, 0xf0, 0x80, 0xf8, 0x04, 0x20, 0x09, 0xe0, + 0xff, 0xf7, 0x32, 0xfe, 0x08, 0x48, 0x80, 0x38, /// 0x4400 + 0x00, 0x68, 0xf0, 0x63, 0xb0, 0x63, 0x1e, 0x20, + 0x28, 0x73, 0x05, 0x20, 0xa0, 0x72, 0x04, 0xe0, /// 0x4410 + 0xff, 0xf7, 0x93, 0xfe, 0x01, 0xe0, 0x00, 0xf0, + 0x73, 0xf8, 0x00, 0x20, 0xf8, 0xbd, 0x00, 0x00, /// 0x4420 + 0x80, 0x01, 0x00, 0x20, 0x40, 0x00, 0x00, 0x20, + 0x20, 0x6c, 0x00, 0x40, 0x00, 0x34, 0x00, 0x40, /// 0x4430 + 0xa0, 0x00, 0x00, 0x20, 0xdc, 0x05, 0x00, 0x00, + 0x00, 0x30, 0x00, 0x40, 0x20, 0x48, 0x00, 0x40, /// 0x4440 + 0x49, 0x02, 0x00, 0x00, 0x0d, 0x0b, 0x00, 0x20, + 0x00, 0x44, 0x00, 0x40, 0x18, 0x11, 0x00, 0x20, /// 0x4450 + 0x7d, 0x0f, 0x00, 0x20, 0x27, 0x0f, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x4460 + 0x7f, 0x05, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0x71, 0x05, 0x00, 0x00, /// 0x4470 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0xe9, 0x15, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x4480 + 0x01, 0x90, 0x01, 0xbd, 0x15, 0x16, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x4490 + 0x2f, 0x07, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0x2b, 0x12, 0x00, 0x00, /// 0x44a0 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0xfd, 0x11, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x44b0 + 0x01, 0x90, 0x01, 0xbd, 0xd5, 0x05, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x44c0 + 0xf5, 0x03, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0xb1, 0x00, 0x00, 0x00, /// 0x44d0 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0x3d, 0x16, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x44e0 + 0x01, 0x90, 0x01, 0xbd, 0x81, 0x12, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x44f0 + 0x5d, 0x12, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0x45, 0x12, 0x00, 0x00, /// 0x4500 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0x6d, 0x11, 0x00, 0x00, 0xf8, 0xb5, 0x02, 0x22, /// 0x4510 + 0x03, 0x21, 0x00, 0x20, 0x00, 0xf0, 0x94, 0xfa, + 0x03, 0x21, 0x00, 0xf0, 0x97, 0xfa, 0x05, 0x46, /// 0x4520 + 0xfe, 0x49, 0x00, 0xf0, 0x99, 0xfa, 0xfe, 0x4e, + 0xfc, 0x49, 0x30, 0x80, 0x28, 0x39, 0x88, 0x69, /// 0x4530 + 0x0c, 0x46, 0x42, 0x00, 0x48, 0x69, 0x20, 0x34, + 0xc3, 0x0f, 0x1a, 0x43, 0x8a, 0x61, 0xea, 0x07, /// 0x4540 + 0x40, 0x00, 0xd2, 0x0f, 0x10, 0x43, 0x48, 0x61, + 0xa1, 0x7e, 0xf6, 0x4f, 0x49, 0x00, 0xc9, 0x19, /// 0x4550 + 0xff, 0x31, 0x01, 0x31, 0x0d, 0x85, 0x01, 0x22, + 0x03, 0x21, 0x02, 0x20, 0x00, 0xf0, 0x70, 0xfa, /// 0x4560 + 0x45, 0x08, 0x21, 0x46, 0x14, 0x31, 0x28, 0x46, + 0x00, 0xf0, 0x76, 0xfa, 0x70, 0x87, 0xa0, 0x7e, /// 0x4570 + 0x03, 0x22, 0x40, 0x00, 0xc0, 0x19, 0xff, 0x30, + 0x01, 0x30, 0x85, 0x86, 0x11, 0x46, 0x01, 0x20, /// 0x4580 + 0x00, 0xf0, 0x5e, 0xfa, 0x03, 0x21, 0x00, 0xf0, + 0x61, 0xfa, 0x21, 0x46, 0x05, 0x46, 0x0e, 0x31, /// 0x4590 + 0x00, 0xf0, 0x62, 0xfa, 0x31, 0x46, 0x40, 0x39, + 0x88, 0x87, 0xa1, 0x7e, 0x49, 0x00, 0xc9, 0x19, /// 0x45a0 + 0xff, 0x31, 0x01, 0x31, 0xcd, 0x85, 0xa0, 0x7e, + 0x02, 0x28, 0x01, 0xd3, 0x00, 0x20, 0x00, 0xe0, /// 0x45b0 + 0x40, 0x1c, 0xa0, 0x76, 0x00, 0x20, 0x60, 0x71, + 0xf8, 0xbd, 0xf8, 0xb5, 0xd8, 0x4f, 0xda, 0x48, /// 0x45c0 + 0x39, 0x88, 0x81, 0x42, 0x05, 0xd2, 0xd9, 0x48, + 0x02, 0x8b, 0x1f, 0x23, 0x1b, 0x02, 0x9a, 0x43, /// 0x45d0 + 0x02, 0x83, 0xd2, 0x4e, 0x88, 0x3e, 0x72, 0x7b, + 0x35, 0x46, 0xd0, 0x07, 0x20, 0x3d, 0x00, 0x28, /// 0x45e0 + 0x60, 0xd0, 0x78, 0x8f, 0x00, 0xf0, 0x3e, 0xfa, + 0xc0, 0x1c, 0xd1, 0x49, 0xb8, 0x80, 0x09, 0x78, /// 0x45f0 + 0xc9, 0x07, 0x59, 0xd1, 0x00, 0xf0, 0x3c, 0xfa, + 0xcd, 0x48, 0xce, 0x4c, 0x40, 0x30, 0x80, 0x8f, /// 0x4600 + 0x6b, 0x38, 0x0b, 0x28, 0xb0, 0x7b, 0x32, 0xd3, + 0xcb, 0x49, 0xc9, 0x7e, 0x49, 0x09, 0x88, 0x42, /// 0x4610 + 0x04, 0xd2, 0xa2, 0x88, 0x92, 0x07, 0x01, 0xd5, + 0x01, 0x20, 0x05, 0xe0, 0x88, 0x42, 0x05, 0xd3, /// 0x4620 + 0xa1, 0x88, 0x89, 0x07, 0x02, 0xd4, 0x03, 0x20, + 0xa0, 0x80, 0x38, 0xe0, 0x00, 0xf0, 0x26, 0xfa, /// 0x4630 + 0xb1, 0x7b, 0x0a, 0x29, 0x01, 0xd2, 0x00, 0x20, + 0x08, 0xe0, 0x0f, 0x29, 0x01, 0xd2, 0x01, 0x20, /// 0x4640 + 0x04, 0xe0, 0x14, 0x29, 0x01, 0xd2, 0x02, 0x20, + 0x00, 0xe0, 0x03, 0x20, 0x22, 0x88, 0xf0, 0x23, /// 0x4650 + 0x9a, 0x43, 0x80, 0x01, 0x02, 0x43, 0x22, 0x80, + 0x02, 0x29, 0x01, 0xd9, 0x10, 0x20, 0x00, 0xe0, /// 0x4660 + 0x00, 0x20, 0xa0, 0x81, 0x38, 0x89, 0x00, 0xf0, + 0x0f, 0xfa, 0x20, 0x82, 0x17, 0xe0, 0x09, 0x28, /// 0x4670 + 0x01, 0xd2, 0x01, 0x21, 0x00, 0xe0, 0x03, 0x21, + 0xa1, 0x80, 0x21, 0x88, 0xf0, 0x22, 0x91, 0x43, /// 0x4680 + 0x12, 0x28, 0x01, 0xd2, 0x00, 0x22, 0x00, 0xe0, + 0xc0, 0x22, 0x11, 0x43, 0x21, 0x80, 0x02, 0x28, /// 0x4690 + 0x01, 0xd9, 0x10, 0x21, 0x00, 0xe0, 0x00, 0x21, + 0xa1, 0x81, 0x00, 0xf0, 0xef, 0xf9, 0x00, 0xf0, /// 0x46a0 + 0xf9, 0xf9, 0x01, 0xe0, 0x10, 0x07, 0x05, 0xd5, + 0x00, 0xf0, 0xfa, 0xf9, 0x41, 0x1d, 0x0a, 0x29, /// 0x46b0 + 0x23, 0xd8, 0x25, 0xe0, 0x9e, 0x4b, 0x37, 0x20, + 0x1c, 0x8e, 0x9a, 0x4b, 0xa1, 0x42, 0x1b, 0x68, /// 0x46c0 + 0x05, 0xd8, 0xe9, 0x6b, 0x7d, 0x24, 0x59, 0x1a, + 0xe4, 0x00, 0xa1, 0x42, 0x15, 0xdb, 0x94, 0x48, /// 0x46d0 + 0x9a, 0x49, 0x40, 0x38, 0x80, 0x8f, 0x88, 0x42, + 0x04, 0xd9, 0x94, 0x48, 0x81, 0x8a, 0x04, 0x15, /// 0x46e0 + 0x21, 0x43, 0x81, 0x82, 0x91, 0x48, 0x81, 0x8b, + 0x01, 0x24, 0x21, 0x43, 0x81, 0x83, 0x05, 0x20, /// 0x46f0 + 0x02, 0x43, 0x72, 0x73, 0x28, 0x3b, 0xab, 0x63, + 0xf8, 0xbd, 0x32, 0x21, 0x29, 0x64, 0x0f, 0xe0, /// 0x4700 + 0x71, 0x7b, 0x96, 0x22, 0xcb, 0x07, 0x00, 0x2b, + 0x07, 0xd0, 0x84, 0x4b, 0x28, 0x3b, 0x59, 0x7f, /// 0x4710 + 0x00, 0x29, 0x04, 0xd0, 0x49, 0x1e, 0x59, 0x77, + 0x02, 0xe0, 0x09, 0x07, 0x00, 0xd5, 0x2a, 0x64, /// 0x4720 + 0x83, 0x49, 0x81, 0x4b, 0x09, 0x8e, 0x3a, 0x3b, + 0xcb, 0x18, 0x7c, 0x49, 0x3a, 0x88, 0x08, 0x39, /// 0x4730 + 0x9a, 0x42, 0x19, 0xd9, 0x0a, 0x79, 0x0a, 0x2a, + 0x03, 0xd3, 0x7a, 0x48, 0x00, 0x68, 0xe8, 0x63, /// 0x4740 + 0xf8, 0xbd, 0x52, 0x1c, 0x0a, 0x71, 0xc3, 0x21, + 0x89, 0x00, 0xa9, 0x81, 0xa8, 0x73, 0x00, 0x28, /// 0x4750 + 0x01, 0xd0, 0x01, 0x20, 0x70, 0x74, 0x01, 0x20, + 0x00, 0xf0, 0xa8, 0xf9, 0x78, 0x48, 0x81, 0x89, /// 0x4760 + 0x80, 0x22, 0x51, 0x40, 0x81, 0x81, 0xf8, 0xbd, + 0x00, 0x22, 0xeb, 0xe7, 0x6d, 0x4a, 0x10, 0xb5, /// 0x4770 + 0x0c, 0x23, 0x80, 0x32, 0x13, 0x73, 0xa4, 0x23, + 0x53, 0x73, 0x90, 0x73, 0x69, 0x48, 0x08, 0x22, /// 0x4780 + 0x8f, 0x30, 0x00, 0xf0, 0x99, 0xf9, 0x0c, 0x20, + 0x00, 0xf0, 0x90, 0xf9, 0x10, 0xbd, 0x70, 0xb5, /// 0x4790 + 0x64, 0x48, 0x67, 0x4c, 0x00, 0x68, 0x21, 0x6f, + 0x6a, 0x4a, 0x41, 0x1a, 0x8a, 0xb0, 0x91, 0x42, /// 0x47a0 + 0x3e, 0xd9, 0xa1, 0x78, 0x68, 0x4e, 0x09, 0x07, + 0x15, 0xd5, 0x25, 0x46, 0x40, 0x35, 0xea, 0x8f, /// 0x47b0 + 0x51, 0x1c, 0xe9, 0x87, 0x03, 0x2a, 0x10, 0xd9, + 0x59, 0x48, 0x08, 0x22, 0x40, 0x38, 0x81, 0x8e, /// 0x47c0 + 0x11, 0x43, 0x81, 0x86, 0x10, 0x46, 0x00, 0xf0, + 0x7d, 0xf9, 0xa0, 0x78, 0xf7, 0x21, 0x08, 0x40, /// 0x47d0 + 0xa0, 0x70, 0x00, 0x20, 0xe8, 0x87, 0x0a, 0xb0, + 0x70, 0xbd, 0x5c, 0xa3, 0x0e, 0xcb, 0x01, 0xad, /// 0x47e0 + 0x0e, 0xc5, 0x4e, 0x49, 0x20, 0x67, 0x14, 0x39, + 0x08, 0x22, 0x0c, 0x46, 0x04, 0xa8, 0x00, 0xf0, /// 0x47f0 + 0x63, 0xf9, 0x08, 0x22, 0x01, 0xa9, 0x06, 0xa8, + 0x00, 0xf0, 0x5e, 0xf9, 0x30, 0x46, 0x00, 0xf0, /// 0x4800 + 0x67, 0xf9, 0x10, 0x22, 0x04, 0xa9, 0x30, 0x46, + 0x00, 0xf0, 0x68, 0xf9, 0x48, 0x49, 0x30, 0x46, /// 0x4810 + 0x0c, 0x31, 0x00, 0xf0, 0x69, 0xf9, 0x21, 0x46, + 0x08, 0x20, 0xff, 0xf7, 0xa7, 0xff, 0xda, 0xe7, /// 0x4820 + 0xff, 0xf7, 0xcb, 0xfe, 0x3d, 0x49, 0x28, 0x39, + 0x48, 0x7f, 0x00, 0x28, 0xd3, 0xd0, 0x40, 0x1e, /// 0x4830 + 0x48, 0x77, 0xd0, 0xe7, 0xf8, 0xb5, 0x3e, 0x4d, + 0x3d, 0x4c, 0x20, 0x35, 0x28, 0x7e, 0x38, 0x4b, /// 0x4840 + 0x40, 0x1e, 0xc2, 0xb2, 0x2a, 0x76, 0xa0, 0x8f, + 0x19, 0x88, 0x08, 0x2a, 0x10, 0xd3, 0x95, 0x07, /// 0x4850 + 0x0d, 0xd1, 0x65, 0x8f, 0x69, 0x18, 0x89, 0xb2, + 0x61, 0x87, 0x5b, 0x8f, 0xc0, 0x18, 0x80, 0xb2, /// 0x4860 + 0xa0, 0x87, 0x08, 0x2a, 0x03, 0xd1, 0x09, 0x09, + 0x61, 0x87, 0x00, 0x09, 0xa0, 0x87, 0xf8, 0xbd, /// 0x4870 + 0x06, 0x2a, 0xfc, 0xd8, 0x00, 0xf0, 0xf6, 0xf8, + 0x37, 0x49, 0x09, 0x88, 0x28, 0x4a, 0xc9, 0x05, /// 0x4880 + 0x20, 0x32, 0x00, 0x29, 0x01, 0xda, 0x11, 0x7d, + 0x08, 0x18, 0x2a, 0x49, 0x0b, 0x8a, 0x1b, 0x04, /// 0x4890 + 0x02, 0xd5, 0x15, 0x23, 0xd3, 0x56, 0x18, 0x18, + 0x62, 0x8f, 0x15, 0x23, 0x43, 0x43, 0x5a, 0x43, /// 0x48a0 + 0x8b, 0x88, 0x12, 0x0b, 0x00, 0x26, 0x01, 0x2b, + 0x05, 0xd0, 0x55, 0x23, 0xdb, 0x00, 0x98, 0x42, /// 0x48b0 + 0x03, 0xd9, 0x05, 0x20, 0x05, 0xe0, 0x6e, 0x76, + 0x04, 0xe0, 0x08, 0x88, 0x00, 0x06, 0x80, 0x0f, /// 0x48c0 + 0x40, 0x1c, 0x68, 0x76, 0x68, 0x7e, 0x41, 0x00, + 0x15, 0x48, 0x40, 0x38, 0x09, 0x18, 0x60, 0x31, /// 0x48d0 + 0x08, 0x7a, 0x50, 0x43, 0xc2, 0x09, 0x09, 0x20, + 0x08, 0x56, 0x0a, 0x21, 0x48, 0x43, 0x1f, 0x49, /// 0x48e0 + 0x80, 0x18, 0x01, 0xd5, 0x00, 0x20, 0x06, 0xe0, + 0x88, 0x42, 0x04, 0xd9, 0x1b, 0x4a, 0x52, 0x42, /// 0x48f0 + 0x82, 0x18, 0xd2, 0x08, 0x10, 0x18, 0x0e, 0x4a, + 0x40, 0x32, 0x92, 0x8f, 0x6b, 0x3a, 0x0a, 0x2a, /// 0x4900 + 0x01, 0xd8, 0x17, 0x4a, 0x80, 0x18, 0x17, 0x4a, + 0x90, 0x42, 0x00, 0xd9, 0x10, 0x46, 0x0b, 0x4a, /// 0x4910 + 0x04, 0x4f, 0x3d, 0x32, 0x80, 0x37, 0xba, 0x81, + 0xc0, 0x01, 0x25, 0xe0, 0x28, 0x02, 0x00, 0x20, /// 0x4920 + 0x40, 0x00, 0x00, 0x20, 0x00, 0x01, 0x00, 0x20, + 0x83, 0x02, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40, /// 0x4930 + 0x80, 0x00, 0x00, 0x20, 0x00, 0x34, 0x00, 0x40, + 0x20, 0x06, 0x00, 0x20, 0xcf, 0x03, 0x00, 0x00, /// 0x4940 + 0x20, 0x6c, 0x00, 0x40, 0x70, 0x17, 0x00, 0x00, + 0x40, 0x03, 0x00, 0x20, 0x58, 0x69, 0x61, 0x6f, /// 0x4950 + 0x6d, 0x69, 0x52, 0x78, 0x00, 0x00, 0x00, 0x00, + 0x20, 0x38, 0x00, 0x40, 0x88, 0x13, 0x00, 0x00, /// 0x4960 + 0xdc, 0x05, 0x00, 0x00, 0xe8, 0x26, 0x00, 0x00, + 0x00, 0xf0, 0x70, 0xf8, 0xb8, 0x73, 0x66, 0x87, /// 0x4970 + 0xa6, 0x87, 0x2e, 0x76, 0x01, 0x20, 0x00, 0xf0, + 0x99, 0xf8, 0xf8, 0xbd, 0xf8, 0xb5, 0x2b, 0x4c, /// 0x4980 + 0xa0, 0x7b, 0x80, 0x06, 0x01, 0xd5, 0x00, 0xf0, + 0xb5, 0xf8, 0xa0, 0x7b, 0x40, 0x06, 0x0a, 0xd5, /// 0x4990 + 0xe0, 0x7b, 0x5a, 0x28, 0x07, 0xd1, 0x60, 0x7b, + 0xef, 0x21, 0x08, 0x40, 0x40, 0x21, 0x08, 0x43, /// 0x49a0 + 0x60, 0x73, 0x23, 0x48, 0x80, 0x47, 0xa0, 0x7b, + 0x04, 0x27, 0xc1, 0x06, 0x21, 0x4d, 0x00, 0x29, /// 0x49b0 + 0x02, 0xda, 0x69, 0x78, 0x39, 0x43, 0x69, 0x70, + 0x00, 0x07, 0x04, 0xd5, 0x1b, 0x48, 0x20, 0x38, /// 0x49c0 + 0xc0, 0x7e, 0x00, 0xf0, 0x9d, 0xf8, 0xa0, 0x7b, + 0x08, 0x26, 0x80, 0x07, 0x00, 0x28, 0x15, 0xda, /// 0x49d0 + 0x19, 0x49, 0x48, 0x7b, 0x02, 0x07, 0x03, 0xd5, + 0xf7, 0x22, 0x10, 0x40, 0x48, 0x73, 0x0d, 0xe0, /// 0x49e0 + 0x30, 0x43, 0x48, 0x73, 0x00, 0xf0, 0x92, 0xf8, + 0x10, 0x48, 0x80, 0x22, 0x40, 0x38, 0x81, 0x8e, /// 0x49f0 + 0x91, 0x43, 0x81, 0x86, 0x11, 0x48, 0x81, 0x89, + 0xb9, 0x43, 0x81, 0x81, 0xa0, 0x7b, 0xc1, 0x07, /// 0x4a00 + 0x02, 0xd0, 0x69, 0x78, 0x31, 0x43, 0x69, 0x70, + 0x00, 0x06, 0x03, 0xd5, 0xa8, 0x78, 0x01, 0x21, /// 0x4a10 + 0x08, 0x43, 0xa8, 0x70, 0x20, 0x7b, 0xc0, 0x07, + 0x02, 0xd0, 0xa8, 0x78, 0x30, 0x43, 0xa8, 0x70, /// 0x4a20 + 0x00, 0x20, 0xe0, 0x73, 0x20, 0x73, 0xa0, 0x73, + 0xf8, 0xbd, 0x00, 0x00, 0x40, 0x00, 0x00, 0x20, /// 0x4a30 + 0x61, 0x06, 0x00, 0x20, 0x80, 0x00, 0x00, 0x20, + 0xa0, 0x01, 0x00, 0x20, 0x20, 0x6c, 0x00, 0x40, /// 0x4a40 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0xcb, 0x03, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x4a50 + 0x01, 0x90, 0x01, 0xbd, 0xe9, 0x15, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x4a60 + 0x49, 0x04, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0x9d, 0x04, 0x00, 0x00, /// 0x4a70 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0x7d, 0x08, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x4a80 + 0x01, 0x90, 0x01, 0xbd, 0x6b, 0x04, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x4a90 + 0xbf, 0x11, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0x39, 0x08, 0x00, 0x00, /// 0x4aa0 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0x97, 0x11, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x4ab0 + 0x01, 0x90, 0x01, 0xbd, 0x2f, 0x07, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x4ac0 + 0x7f, 0x05, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0xd5, 0x05, 0x00, 0x00, /// 0x4ad0 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0xe5, 0x12, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x4ae0 + 0x01, 0x90, 0x01, 0xbd, 0x71, 0x15, 0x00, 0x00, + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, /// 0x4af0 + 0x15, 0x15, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, + 0x01, 0x90, 0x01, 0xbd, 0xef, 0x05, 0x00, 0x00, /// 0x4b00 + 0x03, 0xb4, 0x01, 0x48, 0x01, 0x90, 0x01, 0xbd, + 0xa3, 0x12, 0x00, 0x00, 0x03, 0xb4, 0x01, 0x48, /// 0x4b10 + 0x01, 0x90, 0x01, 0xbd, 0x05, 0x0f, 0x00, 0x00, + 0x32, 0x33, 0x31, 0x32, 0x33, 0x31, 0x32, 0x33, /// 0x4b20 + 0xf0, 0x14, 0xac, 0x28, 0xac, 0x28, 0xac, 0x28, + 0xbe, 0x28, 0xb9, 0x28, 0x14, 0x14, 0x00, 0x00, +}; +#endif + +extern uint32_t get_hw_version_major(void); + +#endif diff --git a/drivers/power/supply/renesas/idtp9418.c b/drivers/power/supply/renesas/idtp9418.c new file mode 100644 index 000000000000..34834c24a32a --- /dev/null +++ b/drivers/power/supply/renesas/idtp9418.c @@ -0,0 +1,5971 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/*add for sdm845 request*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* add for get hw country */ +#include + +static struct idtp9220_device_info *g_di; +#ifdef CONFIG_FACTORY_BUILD +#define REVERSE_TEST_READY_CHECK_DELAY_MS 12000 +#define REVERSE_DPING_CHECK_DELAY_MS 15000 +#else +#define REVERSE_TEST_READY_CHECK_DELAY_MS 8000 +#define REVERSE_DPING_CHECK_DELAY_MS 10000 +#endif +#define REVERSE_CHG_CHECK_DELAY_MS 10000 +#define BPP_QC_7W_CURRENT 700000 +#define BPP_DEFAULT_CURRENT 800000 +#define EPP_DEFAULT_SWITCH_CURRENT 1800000 +#define EPP_DEFAULT_BYPASS_CURRENT 800000 +#define DEFAULT_40V_PSNS_CURRENT 100000 +#define CURRENT_CHANGE_2_TO_1 30000 +#define DC_LOAD_CURRENT 2000000 +#define DC_FUL_CURRENT 50000 +#define SCREEN_OFF_FUL_CURRENT 250000 +#define DC_LOW_CURRENT 350000 +#define DC_SDP_CURRENT 500000 +#define DC_DCP_CURRENT 500000 +#define DC_PD_CURRENT 800000 +#define DC_MI_CURRENT_20W 2100000 +#define DC_MI_CURRENT_30W 3100000 +#define WIRELESS_BY_USBIN_MI_CURRENT 2000000 +#define DC_MI_STEP1_CURRENT 1200000 +#define DC_QC3_CURRENT 500000 +#define DC_EPP_QC3_CURRENT 900000 +#define DC_QC2_CURRENT 1000000 +#define DC_BPP_CURRENT 850000 +#define DC_BPP_AUTH_FAIL_CURRENT 850000 +#define DC_PAN_CURRENT_UA 1200000 +#define ICL_EXCHANGE_CURRENT 600000 +#define ICL_EXCHANGE_COUNT 10 /*5 = 2min */ + +#define ICL_CP_2SBATT_40W_MA 1000000 +#define ICL_CP_2SBATT_30W_MA 1000000 +#define ICL_CP_2SBATT_20W_MA 1000000 + +#define ICL_TAPER_2SBATT_40W_MA 2000000 +#define ICL_TAPER_2SBATT_30W_MA 1800000 +#define ICL_TAPER_2SBATT_20W_MA 1200000 + +#define EXCHANGE_9V 0x0 +#define EXCHANGE_5V 0x1 +#define EXCHANGE_15V 0x0 +#define EXCHANGE_10V 0x1 +#define LIMIT_EPP_IOUT 500 +#define LIMIT_BPP_IOUT 500 +#define LIMIT_SOC 95 +#define TAPER_SOC 86 +#define EPP_TAPER_SOC 95 +#define FULL_SOC 100 +#define TAPER_VOL 4350000 +#define TAPER_CUR -500000 +#define HIGH_THERMAL_LEVEL_THR 12 +#define OCP_PROTECTION_VOTER "OCP_PROTECTION_VOTER" +#define VOICE_LIMIT_FCC_VOTER "VOICE_LIMIT_FCC_VOTER" +#define VOICE_LIMIT_FCC_1A_VOTER "VOICE_LIMIT_FCC_1A_VOTER" +#define IDTP_WAKE_VOTER "IDTP_WAKE_VOTER" +#define IDTP_DOWNLAOD_WAKE_VOTER "IDTP_DOWNLAOD_WAKE_VOTER" + +#define MAX_PMIC_ICL_UA 1500000 +#define EPP_PLUS_VOL 15 +#define BPP_PLUS_VOL 9 +#define EPP_BASE_VOL 12 +#define FULL_VOL 7 +#define CP_CLOSE_VOUT_MV 14200 +#define PAN_BBC_MAX_ICL_MA 1300000 + +//add for soc 100 retry +#define SOC_100_RETRY 6 + +#define MAC_LEN 6 + +struct idtp9220_access_func { + int (*read)(struct idtp9220_device_info *di, u16 reg, u8 *val); + int (*write)(struct idtp9220_device_info *di, u16 reg, u8 val); + int (*read_buf)(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size); + int (*write_buf)(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size); + int (*mask_write)(struct idtp9220_device_info *di, u16 reg, u8 mask, + u8 val); +}; + +struct idtp9220_dt_props { + unsigned int irq_gpio; + unsigned int hall3_gpio; + unsigned int hall4_gpio; + unsigned int wpc_det_gpio; + unsigned int reverse_gpio; + unsigned int rx_ovp_ctl_gpio; + unsigned int reverse_boost_enable_gpio; + bool wireless_by_usbin; + bool only_idt_on_cmi; + bool is_urd_device; +}; + +struct idtp9220_device_info { + int chip_enable; + char *name; + struct device *dev; + struct idtp9220_access_func bus; + struct regmap *regmap; + struct idtp9220_dt_props dt_props; + int irq; + int hall3_irq; + int hall4_irq; + int wpc_irq; + struct delayed_work irq_work; + struct delayed_work hall3_irq_work; + struct delayed_work hall4_irq_work; + struct delayed_work wpc_det_work; + struct pinctrl *idt_pinctrl; + struct pinctrl_state *idt_gpio_active; + struct pinctrl_state *idt_gpio_suspend; + struct power_supply *usb_psy; + struct power_supply *dc_psy; + struct power_supply *batt_psy; + struct power_supply *idtp_psy; + struct power_supply *wireless_psy; + struct power_supply *ln_psy; + struct power_supply *pc_port_psy; + struct mutex read_lock; + struct mutex write_lock; + struct mutex sysfs_op_lock; + struct mutex reverse_op_lock; + struct delayed_work chg_monitor_work; + struct delayed_work chg_detect_work; + struct delayed_work bpp_connect_load_work; + struct delayed_work epp_connect_load_work; + struct delayed_work cmd_check_work; + struct delayed_work vout_regulator_work; + struct delayed_work load_fod_param_work; + struct delayed_work rx_vout_work; + struct delayed_work dc_check_work; + struct delayed_work initial_tx_work; + struct delayed_work bpp_e5_tx_work; + struct delayed_work pan_tx_work; + struct delayed_work voice_tx_work; + struct delayed_work qc2_f1_tx_work; + struct delayed_work qc3_epp_work; + struct delayed_work oob_set_cep_work; + struct delayed_work oob_set_ept_work; + struct delayed_work rx_ready_check_work; + struct delayed_work rx_vout_cp_close_work; + struct delayed_work keep_awake_work; + struct delayed_work oob_clean_work; + struct delayed_work reverse_chg_work; + struct votable *icl_votable; + struct mutex wpc_det_lock; + struct votable *ocp_disable_votable; + bool wait_for_reverse_test; + /* +reverse work +*/ + struct delayed_work reverse_ept_type_work; + struct delayed_work reverse_chg_state_work; + struct delayed_work reverse_dping_state_work; + struct delayed_work reverse_test_state_work; + struct delayed_work reverse_sent_state_work; + struct alarm reverse_dping_alarm; + struct alarm reverse_chg_alarm; + struct alarm reverse_test_ready_alarm; + +//end +#ifdef IDTP9220_SRAM_UPDATE + struct delayed_work sram_update_work; +#endif + + /* +Factory Test Work +*/ + struct delayed_work get_vout_work; + struct delayed_work get_iout_work; + struct delayed_work fw_download_work; + struct delayed_work idt_first_boot; + + /* + #ifdef CONFIG_DRM + struct notifier_block wireless_fb_notif; + struct mutex screen_lock; + bool screen_icl_status; + #endif + */ + bool screen_on; + int tx_charger_type; + int status; + int count_5v; + int count_9v; + int exchange; + int dcin_present; + int epp; + int power_off_mode; + int power_max; + u8 header; + u8 cmd; + int is_compatible_hwid; + int last_vin; + int is_car_tx; + int is_ble_tx; + int is_zm_mobil_tx; + int is_zm_20w_tx; + int is_voice_box_tx; + int is_pan_tx; + int last_icl; + int power_good_flag; + int vout_on; + + /*idt9220 charging info */ + int vout; + int iout; + int f; + int vrect; + int ss; + int is_epp_qc3; + /* bpp e5_tx info */ + int last_bpp_icl; + int last_bpp_vout; + /* qc2+f1_tx info */ + int is_f1_tx; + int bpp_vout_rise; + int last_qc2_vout; + int last_qc2_icl; + /* qc3_epp+f1_tx info */ + int last_qc3_vout; + int last_qc3_icl; + bool fw_update; + int adapter_voltage; + bool first_rise_flag; + bool enable_ext5v; + bool vswitch_ok; + u8 mac_data[6]; + u8 pen_mac_data[6]; + int rpp_val; + int cep_val; + int is_reverse_mode; + int is_reverse_chg; + int is_boost_mode; + int fw_version; + int bpp_icl; + int chip_ok; + int otg_insert; + bool disable_cp; + struct votable *fcc_votable; + bool bpp_break; + bool cp_regulator_done; + int gpio_enable_val; + int reverse_pen_soc; + int reverse_vout; + int reverse_iout; + int hall3_online; + int hall4_online; +}; + +void idtp922x_request_adapter(struct idtp9220_device_info *di); +static void idtp9220_set_charging_param(struct idtp9220_device_info *di); +int program_fw(struct idtp9220_device_info *di, u16 destAddr, u8 *src, + u32 size); +static int program_crc_verify(struct idtp9220_device_info *di); +static int program_bootloader(struct idtp9220_device_info *di); +static int idtp9220_set_rpp(struct idtp9220_device_info *di); +static int idtp9220_set_cep(struct idtp9220_device_info *di); +static int idtp9220_set_ept(struct idtp9220_device_info *di); +static u8 oob_check_sum(u8 *buf, u32 size); +static int idtp9220_set_reverse_enable(struct idtp9220_device_info *di, + int enable); +static void idt_get_reverse_soc(struct idtp9220_device_info *di); + +/*static int idt_signal_strength = 0; + module_param_named(ss, idt_signal_strength, int, 0600); + */ + +static int idt_signal_range = 2; +static int idt_first_flag; +static int pen_soc_count = 0; + +module_param_named(signal_range, idt_signal_range, int, 0644); + +/* +#ifdef CONFIG_DRM +static int wireless_fb_notifier_cb(struct notifier_block *self, +unsigned long event, void *data); +#endif + */ + +static int idtp9220_get_property_names(struct idtp9220_device_info *di) +{ + di->batt_psy = power_supply_get_by_name("battery"); + if (!di->batt_psy) { + dev_err(di->dev, "[idt] no batt_psy,return\n"); + return -EINVAL; + } + di->dc_psy = power_supply_get_by_name("dc"); + if (!di->dc_psy) { + dev_err(di->dev, "[idt] no dc_psy,return\n"); + return -EINVAL; + } + di->usb_psy = power_supply_get_by_name("usb"); + if (!di->usb_psy) { + dev_err(di->dev, "[idt] no usb_psy,return\n"); + return -EINVAL; + } + di->wireless_psy = power_supply_get_by_name("wireless"); + if (!di->wireless_psy) { + dev_err(di->dev, "[idt] no wireless_psy,return\n"); + return -EINVAL; + } + di->pc_port_psy = power_supply_get_by_name("pc_port"); + if (!di->pc_port_psy) { + dev_err(di->dev, "[idt] no pc_port_psy,return\n"); + return -EINVAL; + } + return 0; +} + +int idtp9220_read(struct idtp9220_device_info *di, u16 reg, u8 *val) +{ + unsigned int temp; + int rc; + + mutex_lock(&di->read_lock); + rc = regmap_read(di->regmap, reg, &temp); + if (rc >= 0) + *val = (u8)temp; + + mutex_unlock(&di->read_lock); + return rc; +} + +int idtp9220_write(struct idtp9220_device_info *di, u16 reg, u8 val) +{ + int rc = 0; + + mutex_lock(&di->write_lock); + rc = regmap_write(di->regmap, reg, val); + if (rc < 0) + dev_err(di->dev, "[idt] idtp9220 write error: %d\n", rc); + + mutex_unlock(&di->write_lock); + return rc; +} + +int idtp9220_masked_write(struct idtp9220_device_info *di, u16 reg, u8 mask, + u8 val) +{ + int rc = 0; + + mutex_lock(&di->write_lock); + + rc = regmap_update_bits(di->regmap, reg, mask, val); + if (rc < 0) + dev_err(di->dev, "[idt] idtp9220 write mask error: %d\n", rc); + + mutex_unlock(&di->write_lock); + return rc; +} + +int idtp9220_read_buffer(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size) +{ + int rc = 0; + + while (size--) { + rc = di->bus.read(di, reg++, buf++); + if (rc < 0) { + dev_err(di->dev, "[idt] read buf error: %d\n", rc); + return rc; + } + } + + return rc; +} + +int idtp9220_write_buffer(struct idtp9220_device_info *di, u16 reg, u8 *buf, + u32 size) +{ + int rc = 0; + + while (size--) { + rc = di->bus.write(di, reg++, *buf++); + if (rc < 0) { + dev_err(di->dev, "[idt] write error: %d\n", rc); + return rc; + } + } + + return rc; +} + +u32 ExtractPacketSize(u8 hdr) +{ + if (hdr < 0x20) + return 1; + if (hdr < 0x80) + return (2 + ((hdr - 0x20) >> 4)); + if (hdr < 0xe0) + return (8 + ((hdr - 0x80) >> 3)); + return (20 + ((hdr - 0xe0) >> 2)); +} + +void idtp922x_clrInt(struct idtp9220_device_info *di, u8 *buf, u32 size) +{ + di->bus.write_buf(di, REG_SYS_INT_CLR, buf, size); + di->bus.write(di, REG_SSCMND, CLRINT); +} + +void reverse_clrInt(struct idtp9220_device_info *di, u8 *buf, u32 size) +{ + di->bus.write_buf(di, REG_SYS_INT_CLR, buf, size); + di->bus.write(di, REG_TX_CMD, TX_FOD_EN | TX_CLRINT); +} + +void idtp922x_enable_ext5v(struct idtp9220_device_info *di) +{ + dev_info(di->dev, "enable external 5v\n"); + di->bus.write(di, REG_EXTERNAL_5V, BIT(0)); +} + +void idtp922x_sendPkt(struct idtp9220_device_info *di, ProPkt_Type *pkt) +{ + u32 size = ExtractPacketSize(pkt->header) + 1; + di->bus.write_buf(di, REG_PROPPKT, (u8 *)pkt, + size); // write data into proprietary packet buffer + di->bus.write(di, REG_SSCMND, SENDPROPP); // send proprietary packet + + dev_info(di->dev, "pkt header: 0x%x and cmd: 0x%x\n", pkt->header, + pkt->cmd); + di->header = pkt->header; + di->cmd = pkt->cmd; +} + +void idtp922x_receivePkt(struct idtp9220_device_info *di, u8 *buf) +{ + u8 header; + int rc; + u32 size; + + di->bus.read(di, REG_BCHEADER, &header); + size = ExtractPacketSize(header) + 1; + rc = di->bus.read_buf(di, REG_BCDATA, buf, size); + if (rc < 0) + dev_err(di->dev, "[idt] read Tx data error: %d\n", rc); +} + +void idtp922x_receivePkt2(struct idtp9220_device_info *di, u8 *buf) +{ + int rc; + + rc = di->bus.read_buf(di, REG_PROPPKT, buf, 2); + if (rc < 0) + dev_err(di->dev, "[idt] read Tx data error: %d\n", rc); +} + +void idtp922x_set_adap_vol(struct idtp9220_device_info *di, u16 mv) +{ + dev_info(di->dev, "set adapter vol to %d\n", mv); + di->bus.write(di, REG_FC_VOLTAGE_L, mv & 0xff); + di->bus.write(di, REG_FC_VOLTAGE_H, (mv >> 8) & 0xff); + di->bus.write(di, REG_SSCMND, VSWITCH); +} + +void idtp922x_set_pmi_icl(struct idtp9220_device_info *di, int mA) +{ + union power_supply_propval val = { + 0, + }; + int rc; + if (!di->power_good_flag && val.intval) + return; + + rc = idtp9220_get_property_names(di); + val.intval = mA; + if (di->dt_props.wireless_by_usbin) { + if (di->usb_psy) + power_supply_set_property(di->usb_psy, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + } else { + /* set bbc icl only */ + if (di->dc_psy) + power_supply_set_property(di->dc_psy, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + } + dev_info(di->dev, "[%s] set wls icl %d\n", __func__, val.intval); +} + +/* Adapter Type */ +/* Adapter_list = {0x00:'ADAPTER_UNKNOWN', */ +/* 0x01:'SDP 500mA', */ +/* 0x02:'CDP 1.1A', */ +/* 0x03:'DCP 1.5A', */ +/* 0x05:'QC2.0', */ +/* 0x06:'QC3.0', */ +/* 0x07:'PD',} */ +void idtp922x_request_adapter(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = BC_ADAPTER_TYPE; + + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_request_uuid(struct idtp9220_device_info *di, int is_epp) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + if (is_epp) + pkt.cmd = BC_TX_HWID; + else + pkt.cmd = BC_TX_COMPATIBLE_HWID; + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_get_tx_vin(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = BC_READ_Vin; + + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_retry_cmd(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = di->header; + pkt.cmd = di->cmd; + + idtp922x_sendPkt(di, &pkt); +} + +static int idtp9220_get_vout_regulator(struct idtp9220_device_info *di) +{ + u8 vout_l, vout_h; + u16 vout; + + if (!di) + return 0; + + di->bus.read(di, REG_REGULATOR_L, &vout_l); + di->bus.read(di, REG_REGULATOR_H, &vout_h); + vout = vout_l | ((vout_h & 0xff) << 8); + dev_info(di->dev, "vout regulator get vol: %d\n", vout); + + return vout; +} + +/* + void idtp9220_set_toggle_mode(struct idtp9220_device_info *di) + { + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = BC_TX_TOGGLE; + idtp922x_sendPkt(di, &pkt); + } + */ +void idtp9220_retry_id_auth(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY38; + pkt.cmd = BC_RX_ID_AUTH; + + pkt.data[0] = 0x02; + pkt.data[1] = 0xbb; + + idtp922x_sendPkt(di, &pkt); +} + +static int idtp9220_set_vout_regulator(struct idtp9220_device_info *di, int mv) +{ + u8 vout_l, vout_h; + u16 vout; + + if (!di) + return 0; + vout_l = mv & 0xff; + vout_h = mv >> 8; + + dev_info(di->dev, "vout regulator vout_l: 0x%x and vout_h: 0x%x\n", + vout_l, vout_h); + di->bus.write(di, REG_REGULATOR_L, vout_l); + di->bus.write(di, REG_REGULATOR_H, vout_h); + + vout = vout_l | ((vout_h & 0xff) << 8); + dev_info(di->dev, "vout regulator set vol: %d\n", vout); + + return vout; +} + +#if 0 +static int idtp9220_get_vbuck(struct idtp9220_device_info *di) +{ + u8 vbuck_l, vbuck_h; + u16 vbuck_ret; + + if (!di) + return 0; + + di->bus.read(di, 0x08, &vbuck_l); + di->bus.read(di, 0x09, &vbuck_h); + vbuck_ret = vbuck_l | (vbuck_h << 8); + + return vbuck_ret; +} + +static void idtp9220_dump_regs(struct idtp9220_device_info *di) +{ + u8 VOut_l; + u8 VOut_h; + u8 VOutSet; + u8 VrectAdc; + u8 IOut_l; + u8 IOut_h; + u8 VrectTarget; + + di->bus.read(di, REG_ADC_VOUT_L, &VOut_l); + di->bus.read(di, REG_ADC_VOUT_H, &VOut_h); + di->bus.read(di, REG_VOUT_SET, &VOutSet); + di->bus.read(di, REG_ADC_VRECT, &VrectAdc); + di->bus.read(di, REG_RX_LOUT_L, &IOut_l); + di->bus.read(di, REG_RX_LOUT_H, &IOut_h); + di->bus.read(di, REG_VRECT_TAEGET, &VrectTarget); + + dev_info(di->dev, + "vout_l:%d, vout_h:%d, vout_set:%d, Vrect_adc:%d , iout_l:%d, iout_h:%d, Vrect_target:%d", + VOut_l, VOut_h, VOutSet, VrectAdc, IOut_l, IOut_h, + VrectTarget); +} +#endif + +static int idtp9220_get_vout(struct idtp9220_device_info *di) +{ + u8 vout_l, vout_h; + + if (!di) + return 0; + + di->bus.read(di, REG_ADC_VOUT_L, &vout_l); + di->bus.read(di, REG_ADC_VOUT_H, &vout_h); + di->vout = vout_l | ((vout_h & 0xf) << 8); + di->vout = di->vout * 10 * 21 * 1000 / 40950 + + ADJUST_METE_MV; //vout = val/4095*10*2.1 + dev_info(di->dev, "%s: vout is %d\n", __func__, di->vout); + return di->vout; +} + +static void idtp9220_set_vout(struct idtp9220_device_info *di, int mv) +{ + u16 val; + u8 vout_l, vout_h; + if (!di) + return; + if (!di->power_good_flag) + return; + val = (mv - 2800) * 10 / 84; + vout_l = val & 0xff; + vout_h = val >> 8; + di->bus.write(di, REG_VOUT_SET, vout_l); + di->bus.write(di, REG_VRECT_ADJ, vout_h); + dev_info(di->dev, "[idtp9220]: set vout voltage: %d %d\n", mv, val); +} + +static void idt_set_reverse_fod(struct idtp9220_device_info *di, int mw) +{ + u8 mw_l, mw_h; + if (!di) + return; + mw_l = mw & 0xff; + mw_h = mw >> 8; + di->bus.write(di, REG_FOD_LOW, mw_l); + di->bus.write(di, REG_FOD_HIGH, mw_h); + dev_info(di->dev, "set reverse fod: %d\n", mw); +} + +/* delete because idt9415 can't set rx reset +static void idtp9220_set_reset(struct idtp9220_device_info *di) +{ + if(!di) + return; + di->bus.write(di, REG_RX_RESET, 0x01); + dev_info(di->dev, "[idtp9220]: set RX reset\n"); +} +*/ + +extern char *saved_command_line; + +static int get_cmdline(struct idtp9220_device_info *di) +{ + if (strnstr(saved_command_line, + "androidboot.mode=", strlen(saved_command_line))) { + di->power_off_mode = 1; + dev_info(di->dev, "[idtp9220]: enter power off charging app\n"); + } else { + di->power_off_mode = 0; + dev_info(di->dev, "[idtp9220]: enter normal boot mode\n"); + } + return 1; +} + +#if 0 +static int get_board_version(void) +{ + char boot[5] = { '\0' }; + char *match = (char *)strnstr(saved_command_line, + "androidboot.hwlevel=", + strlen(saved_command_line)); + if (match) { + memcpy(boot, (match + strlen("androidboot.hwlevel=")), + sizeof(boot) - 1); + printk("%s: hwlevel is %s\n", __func__, boot); + if (!strncmp(boot, "P1.2", strlen("P1.2"))) + return 0; + else if (!strncmp(boot, "P1.6", strlen("P1.6"))) + return 0; + } + return 1; +} +#endif +static int idtp9220_get_tx_id(struct idtp9220_device_info *di) +{ + if (di->tx_charger_type == ADAPTER_XIAOMI_PD_40W && di->is_zm_mobil_tx) + return 1; + else + return 0; +} + +static int idtp9220_get_iout(struct idtp9220_device_info *di) +{ + u8 cout_l, cout_h; + + if (!di) + return 0; + + di->bus.read(di, REG_RX_LOUT_L, &cout_l); + di->bus.read(di, REG_RX_LOUT_H, &cout_h); + di->iout = cout_l | (cout_h << 8); + + return di->iout; +} + +static int idtp9220_get_power_profile(struct idtp9220_device_info *di) +{ + u8 mode; + int ret; + + di->bus.read(di, REG_WPC_MODE, &mode); + ret = mode & BIT(3); + dev_info(di->dev, "tx is epp ? ret is 0x%x\n", mode); + + return ret; +} + +static int idtp9220_get_freq(struct idtp9220_device_info *di) +{ + u8 data_list[2]; + + di->bus.read_buf(di, REG_FREQ_ADDR, data_list, 2); + di->f = 64 * HSCLK / (data_list[0] | (data_list[1] << 8)) / 10; + + return di->f; +} + +static int idtp9220_get_vrect(struct idtp9220_device_info *di) +{ + u8 data_list[2]; + + if (!di->power_good_flag) + return 0; + di->bus.read_buf(di, REG_ADC_VRECT, data_list, 2); + di->vrect = data_list[0] | ((data_list[1] & 0xf) << 8); + di->vrect = + di->vrect * 125 * 21 * 100 / 40950; //vrect = val/4095*12.5*2.1 + + return di->vrect; +} + +static int idtp9220_get_power_max(struct idtp9220_device_info *di) +{ + int power_max; + u8 val; + + di->bus.read(di, REG_POWER_MAX, &val); + power_max = (val / 2) * 1000; + dev_info(di->dev, "rx power max is %dmW\n", power_max); + + return power_max; +} + +/* + static int idtp9220_get_signal_strength(struct idtp9220_device_info *di) + { + u8 ss; + + di->bus.read(di, REG_SIGNAL_STRENGTH, &ss); + if(ss >= 95) + idt_signal_range = 1; + else + idt_signal_range = 0; + + dev_info(di->dev, "[idt] signal strength: %d\n", ss); + di->ss = idt_signal_range; + + return ss; + } + */ + +static void idtp9220_send_device_auth(struct idtp9220_device_info *di) +{ + di->bus.write(di, REG_SSCMND, SEND_DEVICE_AUTH); +} + +/*Factory Function*/ + +void idtp922x_sent_vout(struct idtp9220_device_info *di, u8 data_l, u8 data_h) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY38; + pkt.cmd = BC_READ_VOUT; + pkt.data[0] = data_l; + pkt.data[1] = data_h; + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_sent_iout(struct idtp9220_device_info *di, u8 data_l, u8 data_h) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY38; + pkt.cmd = BC_READ_IOUT; + pkt.data[0] = data_l; + pkt.data[1] = data_h; + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_request_low_addr(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = CMD_GET_BLEMAC_2_0; + + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_request_high_addr(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = CMD_GET_BLEMAC_5_3; + + idtp922x_sendPkt(di, &pkt); +} + +static void idtp9220_test_vout_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, get_vout_work.work); + int vol = 0; + u8 vout_l, vout_h; + + vol = idtp9220_get_vout(di); + dev_info(di->dev, "[Factory test] RX VOUT %d mV \n", vol); + vout_h = vol >> 8; + vout_l = vol & 0xff; + idtp922x_sent_vout(di, vout_l, vout_h); +} + +static void idtp9220_test_iout_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, get_iout_work.work); + int curr = 0; + u8 cout_l, cout_h; + + curr = idtp9220_get_iout(di); + dev_info(di->dev, " [Factory test] RX IOUT %d mA \n", curr); + cout_h = curr >> 8; + cout_l = curr & 0xff; + idtp922x_sent_iout(di, cout_l, cout_h); +} + +void idtp922x_sent_tx_mac(struct idtp9220_device_info *di) +{ + int64_t ble_mac = 0; + union power_supply_propval val = { + 0, + }; + memcpy(&ble_mac, di->mac_data, MAC_LEN); + val.int64val = ble_mac; + if (di->wireless_psy) + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_TX_MAC, &val); + else + dev_err(di->dev, "BLE mac addr get error:\n"); +} + +void idtp922x_sent_pen_mac(struct idtp9220_device_info *di) +{ + int64_t ble_mac = 0; + union power_supply_propval val = { + 0, + }; + memcpy(&ble_mac, di->pen_mac_data, MAC_LEN); + val.int64val = ble_mac; + if (di->wireless_psy) + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_PEN_MAC, &val); + else + dev_err(di->dev, "pen ble mac addr get error:\n"); +} + +void idtp922x_sent_chip_version(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + u8 chip_id_l, chip_id_h; + + di->bus.read(di, REG_CHIP_ID_L, &chip_id_l); + di->bus.read(di, REG_CHIP_ID_H, &chip_id_h); + + dev_info(di->dev, "Chip_ID: %02x%02x\n", chip_id_h, chip_id_l); + + pkt.header = PROPRIETARY38; + pkt.cmd = BC_RX_CHIP_VERSION; + pkt.data[0] = chip_id_h; + pkt.data[1] = chip_id_l; + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_sent_fw_version(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + u8 fw_app_ver[4]; + + di->bus.read_buf(di, REG_EPRFWVER_ADDR, fw_app_ver, 4); + + dev_info(di->dev, "RX FW version %x.%x.%x.%x\n", fw_app_ver[3], + fw_app_ver[2], fw_app_ver[1], fw_app_ver[0]); + + pkt.header = PROPRIETARY58; + pkt.cmd = BC_RX_FW_VERSION; + pkt.data[0] = fw_app_ver[3]; + pkt.data[1] = fw_app_ver[2]; + pkt.data[2] = fw_app_ver[1]; + pkt.data[3] = fw_app_ver[0]; + idtp922x_sendPkt(di, &pkt); +} + +void idtp922x_sent_reverse_cnf(struct idtp9220_device_info *di) +{ + ProPkt_Type pkt; + pkt.header = PROPRIETARY18; + pkt.cmd = CMD_FACOTRY_REVERSE; + idtp922x_sendPkt(di, &pkt); +} +/*Factory end*/ + +/******************************************************* + * SET GPIO STATE TO SMB FOR IGNORE DC_POWER_ON IRQ* + *******************************************************/ +/* define for reverse state of wireless charging */ +#define REVERSE_GPIO_STATE_UNSET 0 +#define REVERSE_GPIO_STATE_START 1 +#define REVERSE_GPIO_STATE_END 2 +static int idtp9220_set_reverse_gpio_state(struct idtp9220_device_info *di, + int enable) +{ + union power_supply_propval reverse_val = { + 0, + }; + + if (!di->wireless_psy) + di->wireless_psy = power_supply_get_by_name("wireless"); + + if (di->wireless_psy) { + dev_dbg(di->dev, "set_reverse_gpio_state\n", + reverse_val.intval); + if (enable) { + reverse_val.intval = REVERSE_GPIO_STATE_START; + } else { + reverse_val.intval = REVERSE_GPIO_STATE_END; + } + + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_REVERSE_GPIO_STATE, + &reverse_val); + + } else { + dev_err(di->dev, "no wireless_psy,return\n"); + return -EINVAL; + } + return 0; +} +static int +idtp9229_set_reverse_boost_enable_gpio(struct idtp9220_device_info *di, + int enable) +{ + int ret; + if (gpio_is_valid(di->dt_props.reverse_boost_enable_gpio)) { + ret = gpio_request(di->dt_props.reverse_boost_enable_gpio, + "reverse-boost-enable-gpio"); + if (ret) { + dev_err(di->dev, + "%s: unable to reverse_boost_enable_gpio [%d]\n", + __func__, + di->dt_props.reverse_boost_enable_gpio); + } + + ret = gpio_direction_output( + di->dt_props.reverse_boost_enable_gpio, !!enable); + if (ret) { + dev_err(di->dev, + "%s: cannot set direction for reverse_boost_enable_gpio gpio [%d]\n", + __func__, + di->dt_props.reverse_boost_enable_gpio); + } + gpio_free(di->dt_props.reverse_boost_enable_gpio); + } else + dev_err(di->dev, + "%s: unable to set reverse_boost_enable_gpio\n"); + + return ret; +} + +static int idtp9220_set_reverse_gpio(struct idtp9220_device_info *di, + int enable) +{ + int ret; + union power_supply_propval val = { + 0, + }; + if (!di->wireless_psy) + di->wireless_psy = power_supply_get_by_name("wireless"); + + if (!di->wireless_psy) { + dev_err(di->dev, "no wireless_psy,return\n"); + return -EINVAL; + } + + val.intval = !!enable; + + if (gpio_is_valid(di->dt_props.reverse_gpio)) { + if (enable) { + idtp9220_set_reverse_gpio_state(di, enable); + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_SW_DISABLE_DC_EN, &val); + idtp9229_set_reverse_boost_enable_gpio(di, enable); + } + ret = gpio_request(di->dt_props.reverse_gpio, + "reverse-enable-gpio"); + if (ret) { + dev_err(di->dev, + "%s: unable to request reverse gpio [%d]\n", + __func__, di->dt_props.reverse_gpio); + } + + ret = gpio_direction_output(di->dt_props.reverse_gpio, + !!enable); + if (ret) { + dev_err(di->dev, + "%s: cannot set direction for reverse enable gpio [%d]\n", + __func__, di->dt_props.reverse_gpio); + } + gpio_free(di->dt_props.reverse_gpio); + if (!enable) { + idtp9229_set_reverse_boost_enable_gpio(di, enable); + idtp9220_set_reverse_gpio_state(di, enable); + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_SW_DISABLE_DC_EN, &val); + } + + } else + dev_err(di->dev, "%s: unable to set tx_on\n"); + + di->wireless_psy = power_supply_get_by_name("wireless"); + if (!di->wireless_psy) + dev_err(di->dev, "[idt] no wireless_psy,return\n"); + else + power_supply_changed(di->wireless_psy); + return ret; +} + +static ssize_t chip_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + u8 chip_id_l, chip_id_h, chip_rev, cust_id, status, vset; + u8 fw_otp_ver[4], fw_app_ver[4]; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + if (!di->fw_update) { + di->fw_update = true; + idtp9220_set_reverse_gpio(di, true); + msleep(100); + di->bus.read(di, REG_STATUS_L, &status); + di->bus.read(di, REG_VOUT_SET, &vset); + + di->bus.read(di, REG_CHIP_ID_L, &chip_id_l); + di->bus.read(di, REG_CHIP_ID_H, &chip_id_h); + di->bus.read(di, REG_CHIP_REV, &chip_rev); + chip_rev = chip_rev >> 4; + di->bus.read(di, REG_CTM_ID, &cust_id); + di->bus.read_buf(di, REG_OTPFWVER_ADDR, fw_otp_ver, 4); + di->bus.read_buf(di, REG_EPRFWVER_ADDR, fw_app_ver, 4); + + /* add crc verify to ensure fw version is right, + * if crc failed, return app ver to 0xFE + */ + if (!program_crc_verify(di)) { + idtp9220_set_reverse_gpio(di, false); + dev_err(di->dev, "crc verify failed, fw: %x\n", + fw_app_ver[0]); + fw_app_ver[0] = 0xFE; + di->fw_update = false; + return snprintf( + buf, PAGE_SIZE, + "chip_id_l:%02x\nchip_id_h:%02x\nchip_rev:%02x\ncust_id:%02x status:%02x vset:%02x\n otp_ver:%x.%x.%x.%x\n app_ver:%x.%x.%x.%x\n", + chip_id_l, chip_id_h, chip_rev, cust_id, status, + vset, fw_otp_ver[0], fw_otp_ver[1], + fw_otp_ver[2], fw_otp_ver[3], fw_app_ver[0], + fw_app_ver[1], fw_app_ver[2], fw_app_ver[3]); + } else { + dev_info(di->dev, "crc verify success.\n"); + } + + idtp9220_set_reverse_gpio(di, false); + di->fw_update = false; + return snprintf( + buf, PAGE_SIZE, + "chip_id_l:%02x\nchip_id_h:%02x\nchip_rev:%02x\ncust_id:%02x status:%02x vset:%02x\n otp_ver:%x.%x.%x.%x\n app_ver:%x.%x.%x.%x\n", + chip_id_l, chip_id_h, chip_rev, cust_id, status, vset, + fw_otp_ver[0], fw_otp_ver[1], fw_otp_ver[2], + fw_otp_ver[3], fw_app_ver[0], fw_app_ver[1], + fw_app_ver[2], fw_app_ver[3]); + } else { + return snprintf(buf, PAGE_SIZE, + "fw update is ongoing ,can not get version\n"); + } +} + +/* voltage limit attrs */ +static ssize_t chip_vout_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int vout; + + vout = idtp9220_get_vout(di); + return snprintf(buf, PAGE_SIZE, "%d\n", vout); +} + +static ssize_t chip_vout_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int index; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + index = (int)simple_strtoul(buf, NULL, 16); + /* + if ((index < VOUT_VAL_3500_MV) || (index > VOUT_VAL_5000_MV)) { + dev_err(di->dev, "Store Val %s is invalid!\n", buf); + return count; + } + */ + + idtp9220_set_vout(di, index); + + return count; +} + +static ssize_t vout_regulator_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int vout; + + vout = idtp9220_get_vout_regulator(di); + + return snprintf(buf, PAGE_SIZE, "Vout ADC Value: %dMV\n", vout); +} + +#define VOUT_MIN_4900_MV 4900 +#define VOUT_MAX_10000_MV 10000 +static ssize_t vout_regulator_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int vout; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + vout = (int)simple_strtoul(buf, NULL, 10); + if ((vout <= VOUT_MIN_4900_MV) || (vout > VOUT_MAX_10000_MV)) { + dev_err(di->dev, "Store Val %s : %ld is invalid!\n", buf, vout); + return count; + } + idtp9220_set_vout_regulator(di, vout); + + return count; +} + +/* current attrs */ +static ssize_t chip_iout_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int cout; + + cout = idtp9220_get_iout(di); + + return snprintf(buf, PAGE_SIZE, "%d\n", cout); +} + +static ssize_t chip_iout_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int index; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + index = (int)simple_strtoul(buf, NULL, 10); + + if ((index < CURR_VAL_100_MA) || (index > CURR_VAL_1300_MA)) { + dev_err(di->dev, "Store Val %s is invalid", buf); + return count; + } + + di->bus.write(di, REG_ILIM_SET, index); + + return count; +} + +static ssize_t chip_freq_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + int f; + + f = idtp9220_get_freq(di); + + return snprintf(buf, sizeof(buf), "Output Current: %dkHz\n", f); +} + +static void idtp9220_charging_info(struct idtp9220_device_info *di) +{ + if (!di) + return; + + idtp9220_get_vout(di); + idtp9220_get_iout(di); + idtp9220_get_freq(di); + idtp9220_get_vrect(di); + + dev_info(di->dev, + "%s:Vout:%dmV,Iout:%dmA,Freq:%dKHz,Vrect:%dmV,SS:%d\n", + __func__, di->vout, di->iout, di->f, di->vrect, di->ss); +} + +static int idtp9220_reverse_charge_enable(struct idtp9220_device_info *di) +{ + u8 mode = 0; + int ret = 0, i = 0; + int fod_set = REVERSE_FOD; + + if (!di->fw_update) { + di->bus.read(di, REG_WPC_MODE, &mode); + dev_info(di->dev, "wpc mode(0x004D): 0x%x\n", mode); + ret = mode & BIT(0); + if (ret) { + dev_info(di->dev, + "rx mode, can not enable reverse charge\n"); + di->is_reverse_mode = 0; + di->is_reverse_chg = 1; + idtp9220_set_reverse_enable(di, false); + schedule_delayed_work(&di->reverse_sent_state_work, 0); + return 0; + } + } + + if (!di->fw_update) { + /* set reverse fod to REVERSE_FOD */ + idt_set_reverse_fod(di, fod_set); + for (i = 0; i < 3; i++) { + di->bus.write(di, REG_TX_CMD, TX_EN | TX_FOD_EN); + msleep(50); + di->bus.read(di, REG_TX_DATA, &mode); + dev_info(di->dev, "tx data(0078): 0x%x\n", mode); + if (mode & BIT(0)) { + di->is_reverse_mode = 1; + dev_info(di->dev, "start reverse charging\n"); + break; + } else { + dev_err(di->dev, + "idt set reverse charge failed, retry: %d\n", + i); + } + } + + if (i < 3) { + dev_info(di->dev, "reverse charging start success\n"); + return 1; + } else { + dev_info(di->dev, "reverse charging failed start\n"); + idtp9220_set_reverse_enable(di, false); + return 0; + } + } else { + return 0; + } +} + +static int idtp9220_set_reverse_enable(struct idtp9220_device_info *di, + int enable) +{ + int ret = 0; + union power_supply_propval wk_val = { + 0, + }; + + di->wireless_psy = power_supply_get_by_name("wireless"); + if (!di->wireless_psy) { + dev_err(di->dev, "[idt] no wireless_psy,return\n"); + if (!enable) { + di->is_reverse_mode = 0; + cancel_delayed_work(&di->reverse_chg_state_work); + cancel_delayed_work(&di->reverse_dping_state_work); + cancel_delayed_work(&di->reverse_ept_type_work); + idtp9220_set_reverse_gpio(di, false); + } + goto out; + } + + if (di->fw_update) { + goto out; + } + idtp9220_set_reverse_gpio(di, enable); + + if (enable) { + di->is_boost_mode = 1; + ret = idtp9220_reverse_charge_enable(di); + if (ret) { + if (di->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + alarm_start_relative( + &di->reverse_dping_alarm, + ms_to_ktime(REVERSE_DPING_CHECK_DELAY_MS)); + } + } else { + di->is_boost_mode = 0; + dev_info(di->dev, "disable reverse charging for wireless\n"); + if (di->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + } + di->is_reverse_mode = 0; + di->reverse_pen_soc = 255; + cancel_delayed_work(&di->reverse_chg_state_work); + cancel_delayed_work(&di->reverse_dping_state_work); + cancel_delayed_work(&di->reverse_ept_type_work); + cancel_delayed_work(&di->reverse_chg_work); + + ret = alarm_cancel(&di->reverse_dping_alarm); + if (ret < 0) + dev_err(di->dev, + "Couldn't cancel reverse_dping_alarm\n"); + + ret = alarm_cancel(&di->reverse_chg_alarm); + if (ret < 0) + dev_err(di->dev, "Couldn't cancel reverse_chg_alarm\n"); + pm_relax(di->dev); + } +out: + return ret; +} + +/* reverse enable attrs */ +static ssize_t reverse_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + if (gpio_is_valid(di->dt_props.reverse_gpio)) + ret = gpio_get_value(di->dt_props.reverse_gpio); + else { + dev_err(di->dev, "%s: reverse gpio not provided\n", __func__); + ret = -1; + } + + dev_info(di->dev, "reverse enable gpio: %d\n", ret); + + return snprintf(buf, sizeof(buf), "reverse enable: %d\n", ret); +} + +static ssize_t reverse_gpio_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret, enable; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + ret = (int)simple_strtoul(buf, NULL, 10); + enable = !!ret; + + idtp9220_set_reverse_gpio(di, enable); + + return count; +} + +/*ovp cntl*/ +static ssize_t ovp_gpio_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int ret; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + if (gpio_is_valid(di->dt_props.rx_ovp_ctl_gpio)) + ret = gpio_get_value(di->dt_props.rx_ovp_ctl_gpio); + else { + dev_err(di->dev, "%s: ovp cntl gpio not provided\n", __func__); + ret = -1; + } + + dev_info(di->dev, "ovp enable gpio: %d\n", ret); + + return scnprintf(buf, PAGE_SIZE, "ovp enable: %d\n", ret); +} + +static ssize_t ovp_gpio_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret, enable; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + ret = (int)simple_strtoul(buf, NULL, 10); + enable = !!ret; + + if (gpio_is_valid(di->dt_props.rx_ovp_ctl_gpio)) { + ret = gpio_request(di->dt_props.rx_ovp_ctl_gpio, + "ovp-enable-gpio"); + if (ret) { + dev_err(di->dev, + "%s: unable to request ovp_en_gpio [%d]\n", + __func__, di->dt_props.rx_ovp_ctl_gpio); + } + + ret = gpio_direction_output(di->dt_props.rx_ovp_ctl_gpio, + enable); + if (ret) { + dev_err(di->dev, + "%s: cannot set direction for ovp_en_gpio [%d]\n", + __func__, di->dt_props.rx_ovp_ctl_gpio); + } + gpio_free(di->dt_props.rx_ovp_ctl_gpio); + } else + dev_err(di->dev, "%s: unable to get ovp_en_gpio\n"); + + return count; +} + +static ssize_t reverse_gpio_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + if (gpio_is_valid(di->dt_props.reverse_gpio)) + ret = gpio_get_value(di->dt_props.reverse_gpio); + else { + dev_err(di->dev, "%s: reverse gpio not provided\n", __func__); + ret = -1; + } + + dev_info(di->dev, "reverse enable gpio: %d\n", ret); + + return scnprintf(buf, PAGE_SIZE, "reverse enable: %d\n", ret); +} + +static ssize_t reverse_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret, enable; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + ret = (int)simple_strtoul(buf, NULL, 10); + enable = !!ret; + di->is_reverse_chg = 0; + schedule_delayed_work(&di->reverse_sent_state_work, 0); + idtp9220_set_reverse_enable(di, enable); + return count; +} + +/* chip enable attrs */ +static ssize_t chip_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + + return snprintf(buf, PAGE_SIZE, "Chip enable: %d\n", !ret); + + /* + if (gpio_is_valid(di->dt_props.enable_gpio)) + ret = gpio_get_value(di->dt_props.enable_gpio); + else { + dev_err(di->dev, "%s: sleep gpio not provided\n", __func__); + ret = -1; + } + + dev_info(di->dev, "chip enable gpio: %d\n", ret); + + return snprintf(buf, PAGE_SIZE, "Chip enable: %d\n", !ret); +*/ +} + +static ssize_t chip_die_temp_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + u8 buff[2] = { 0 }; + int die_temp = 0; + ret = di->bus.read_buf(di, REG_RX_DIE_TEMP, buff, 2); + if (!ret) { + die_temp = buff[0] | ((buff[1] & 0x0f) << 8); + die_temp = (die_temp - 1350) * 83 / 444 - 273; + } + return snprintf(buf, PAGE_SIZE, "%d\n", die_temp); +} + +static enum alarmtimer_restart reverse_chg_alarm_cb(struct alarm *alarm, + ktime_t now) +{ + struct idtp9220_device_info *di = container_of( + alarm, struct idtp9220_device_info, reverse_chg_alarm); + + dev_info(di->dev, " Reverse Chg Alarm Triggered %lld\n", + ktime_to_ms(now)); + + /* Atomic context, cannot use voter */ + pm_stay_awake(di->dev); + + schedule_delayed_work(&di->reverse_chg_state_work, 0); + + return ALARMTIMER_NORESTART; +} + +static enum alarmtimer_restart reverse_dping_alarm_cb(struct alarm *alarm, + ktime_t now) +{ + struct idtp9220_device_info *di = container_of( + alarm, struct idtp9220_device_info, reverse_dping_alarm); + + dev_info(di->dev, "Reverse Dping Alarm Triggered %lld\n", + ktime_to_ms(now)); + + /* Atomic context, cannot use voter */ + pm_stay_awake(di->dev); + schedule_delayed_work(&di->reverse_dping_state_work, 0); + + return ALARMTIMER_NORESTART; +} + +static enum alarmtimer_restart reverse_test_ready_alarm_cb(struct alarm *alarm, + ktime_t now) +{ + struct idtp9220_device_info *di = container_of( + alarm, struct idtp9220_device_info, reverse_test_ready_alarm); + + dev_info( + di->dev, + "[ factory reverse test ] reverse_rest_ready_alarm Triggered\n"); + + /* Atomic context, cannot use voter */ + pm_stay_awake(di->dev); + schedule_delayed_work(&di->reverse_test_state_work, 0); + di->wait_for_reverse_test = false; + + return ALARMTIMER_NORESTART; +} + +static int idtp9220_set_present(struct idtp9220_device_info *di, int enable) +{ + int ret = 0; + + dev_info(di->dev, "[idtp] dc plug %s\n", enable ? "in" : "out"); + if (enable) { + di->dcin_present = true; + di->ss = 1; + } else { + schedule_delayed_work(&di->oob_set_ept_work, + msecs_to_jiffies(10)); + di->status = NORMAL_MODE; + di->count_9v = 0; + di->count_5v = 0; + di->exchange = 0; + di->dcin_present = false; + idt_signal_range = 2; + di->ss = 2; + di->epp = 0; + di->last_vin = 0; + di->last_icl = 0; + di->is_car_tx = 0; + di->is_voice_box_tx = 0; + di->is_zm_20w_tx = 0; + di->is_pan_tx = 0; + di->is_ble_tx = 0; + di->vout_on = 0; + di->is_zm_mobil_tx = 0; + di->power_off_mode = 0; + di->is_epp_qc3 = 0; + di->bpp_vout_rise = 0; + di->is_f1_tx = 0; + di->last_bpp_vout = 0; + di->last_bpp_icl = 0; + di->last_qc2_vout = 0; + di->last_qc2_icl = 0; + di->last_qc3_vout = 0; + di->last_qc3_icl = 0; + di->fw_update = false; + di->tx_charger_type = ADAPTER_NONE; + di->adapter_voltage = 0; + di->first_rise_flag = false; + di->enable_ext5v = false; + di->vswitch_ok = false; + di->bpp_icl = 0; + di->otg_insert = 0; + di->disable_cp = false; + di->bpp_break = false; + di->cp_regulator_done = false; + cancel_delayed_work(&di->rx_vout_work); + cancel_delayed_work(&di->chg_monitor_work); + cancel_delayed_work(&di->cmd_check_work); + cancel_delayed_work(&di->oob_set_cep_work); + cancel_delayed_work(&di->rx_vout_cp_close_work); + /* clear OOB messages */ + schedule_delayed_work(&di->oob_clean_work, + msecs_to_jiffies(100)); + } + + return ret; +} + +static int idtp9220_set_enable_mode(struct idtp9220_device_info *di, int enable) +{ + int ret = 0; + + return ret; + /* + printk("idtp9220_set_enable_mode: enable:%d\n", enable); + if (gpio_is_valid(di->dt_props.enable_gpio)) { + ret = gpio_request(di->dt_props.enable_gpio, "idt-enable-gpio"); + if (ret) { + dev_err(di->dev, + "%s: unable to request idt enable gpio [%d]\n", + __func__, di->dt_props.enable_gpio); + } + + ret = gpio_direction_output(di->dt_props.enable_gpio, !enable); + if (ret) { + dev_err(di->dev, + "%s: cannot set direction for idt enable gpio [%d]\n", + __func__, di->dt_props.enable_gpio); + } + di->gpio_enable_val = gpio_get_value(di->dt_props.enable_gpio); + pr_info("idtp9415 enable gpio val is :%d\n", di->gpio_enable_val); + gpio_free(di->dt_props.enable_gpio); + } +*/ +} + +static ssize_t chip_enable_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + int ret, enable; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + ret = (int)simple_strtoul(buf, NULL, 10); + enable = !!ret; + + idtp9220_set_enable_mode(di, enable); + + return count; +} + +/*print the result of fw program*/ +static ssize_t chip_fw_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int ret = 0; + int fw_ret = 0; + struct i2c_client *client = container_of(dev, struct i2c_client, dev); + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + if (di->fw_update) { + dev_err(&client->dev, + "[idtp9415] [%s] Firmware Update is on going!\n", + __func__); + return snprintf(buf, PAGE_SIZE, + "Firmware Update is on going!\n"); + } + pm_stay_awake(di->dev); + di->fw_update = true; + + idtp9220_set_reverse_gpio(di, true); + msleep(100); + + if (!program_fw(di, 0x0000, idt_firmware, sizeof(idt_firmware))) { + dev_err(&client->dev, "program fw failed.\n"); + fw_ret = 0; + } else { + dev_err(&client->dev, "program fw sucess.\n"); + di->fw_version = FW_VERSION; + fw_ret = 1; + } + idtp9220_set_reverse_gpio(di, false); + msleep(100); + + idtp9220_set_reverse_gpio(di, true); + msleep(100); + + /* start crc verify */ + if (!program_crc_verify(di)) { + dev_err(&client->dev, "crc verify failed.\n"); + ret = 0; + } else { + dev_err(&client->dev, "crc verify success.\n"); + ret = 1; + } + + idtp9220_set_reverse_gpio(di, false); + di->fw_update = false; + pm_relax(di->dev); + if (ret && fw_ret) + return snprintf(buf, PAGE_SIZE, "Firmware Update:Success\n"); + else + return snprintf(buf, PAGE_SIZE, "Firmware Update:Failed\n"); +} + +static DEVICE_ATTR(chip_enable, S_IWUSR | S_IRUGO, chip_enable_show, + chip_enable_store); +static DEVICE_ATTR(reverse_enable, S_IWUSR | S_IRUGO, reverse_enable_show, + reverse_enable_store); +static DEVICE_ATTR(chip_version, S_IRUGO, chip_version_show, NULL); +static DEVICE_ATTR(chip_vout, S_IWUSR | S_IRUGO, chip_vout_show, + chip_vout_store); +static DEVICE_ATTR(chip_iout, S_IWUSR | S_IRUGO, chip_iout_show, + chip_iout_store); +static DEVICE_ATTR(chip_freq, S_IRUGO, chip_freq_show, NULL); +static DEVICE_ATTR(vout_regulator, S_IWUSR | S_IRUGO, vout_regulator_show, + vout_regulator_store); +static DEVICE_ATTR(chip_fw, S_IWUSR | S_IRUGO, chip_fw_show, NULL); +static DEVICE_ATTR(reverse_set_gpio, S_IWUSR | S_IRUGO, reverse_gpio_show, + reverse_gpio_store); +static DEVICE_ATTR(ovp_set_gpio, S_IWUSR | S_IRUGO, ovp_gpio_show, + ovp_gpio_store); +static DEVICE_ATTR(chip_die_temp, S_IWUSR | S_IRUGO, chip_die_temp_show, NULL); + +static struct attribute *sysfs_attrs[] = { + &dev_attr_chip_version.attr, &dev_attr_chip_vout.attr, + &dev_attr_chip_iout.attr, &dev_attr_chip_freq.attr, + &dev_attr_chip_enable.attr, &dev_attr_reverse_enable.attr, + &dev_attr_vout_regulator.attr, &dev_attr_chip_fw.attr, + &dev_attr_reverse_set_gpio.attr, &dev_attr_ovp_set_gpio.attr, + &dev_attr_chip_die_temp.attr, NULL, +}; + +static const struct attribute_group sysfs_group_attrs = { + .attrs = sysfs_attrs, +}; + +#if 1 +static int program_bootloader(struct idtp9220_device_info *di) +{ + int i, rc = 0; + int len; + + len = sizeof(bootloader_data); + + for (i = 0; i < len; i++) { + rc = di->bus.write(di, 0x0800 + i, bootloader_data[i]); + if (rc) + return rc; + } + + return 0; +} + +static int program_crc_verify(struct idtp9220_device_info *di) +{ + u8 val; + int retry_cnt = 0; + + /* unlock system clock */ + if (di->bus.write(di, 0x3000, 0x5a)) + return false; + /* configure clocks and timing */ + if (di->bus.write(di, 0x3004, 0x00)) + return false; + if (di->bus.write(di, 0x3008, 0x09)) + return false; + if (di->bus.write(di, 0x300C, 0x05)) + return false; + if (di->bus.write(di, 0x300D, 0x1D)) + return false; + if (di->bus.write(di, 0x304C, 0x00)) + return false; + if (di->bus.write(di, 0x304D, 0x00)) + return false; + /* pause the processor and enable MTP */ + if (di->bus.write(di, 0x3040, 0x11)) + return false; + mdelay(10); + /* halt the mpu */ + if (di->bus.write(di, 0x3040, 0x10)) + return false; + mdelay(10); + + /* load the mtp downloader program */ + if (program_bootloader(di)) + return false; + + /* init the program structure and remap RAM */ + if (di->bus.write(di, 0x0400, 0x00)) + return false; + if (di->bus.write(di, 0x3048, 0xD0)) + return false; + /* reset mpu and run mtp downloader program, ignoreNAK */ + di->bus.write(di, 0x3040, 0x80); + mdelay(100); + + /* configure MTP crc check utility */ + /* step1 load start address */ + if (di->bus.write(di, 0x402, 0x00)) + return false; + if (di->bus.write(di, 0x403, 0x00)) + return false; + /* step2 load mtp data size 0x6000 */ + if (di->bus.write(di, 0x404, 0x00)) + return false; + if (di->bus.write(di, 0x405, 0x60)) + return false; + /* step3 write crc valuve */ + if (di->bus.write(di, 0x406, CRC_VERIFY_LOW)) + return false; + if (di->bus.write(di, 0x407, CRC_VERIFY_HIGH)) + return false; + /* start crc check */ + if (di->bus.write(di, 0x400, 0x11)) { + dev_err(di->dev, "on OTP buffer CRC validation error\n"); + return false; + } + + do { + mdelay(100); + di->bus.read(di, 0x400, &val); + if ((val & 1) != 0) + dev_info(di->dev, "Programming crc check val:%02x\n", + val); + if (retry_cnt++ > 50) + break; + } while ((val & 1) != 0); //check if crc program finishes "OK" + + if (retry_cnt > 50) { + dev_err(di->dev, "Programming CRC finished failed retry:%d\n", + retry_cnt); + return false; + } else { + di->bus.read(di, 0x401, &val); + if (val != 2) { + dev_err(di->dev, "crc check failed status:%d\n", val); + return false; + } else { + dev_info(di->dev, "crc check success!\n"); + return true; + } + } +} + +int program_fw(struct idtp9220_device_info *di, u16 destAddr, u8 *src, u32 size) +{ + int i, j; + u8 data = 0; + //u8 data_array[512]; + + // === Step-1 === + // Transfer 9220 boot loader code "OTPBootloader" to 9220 SRAM + // - Setup 9220 registers before transferring the boot loader code + // - Transfer the boot loader code to 9220 SRAM + // - Reset 9220 => 9220 M0 runs the boot loader + // + di->bus.read(di, 0x5870, &data); + printk(KERN_EMERG "0x5870 %s:%d :%02x\n", __func__, __LINE__, data); + di->bus.read(di, 0x5874, &data); + printk(KERN_EMERG "0x5874 %s:%d :%02x\n", __func__, __LINE__, data); + // configure the system + if (di->bus.write(di, 0x3000, 0x5a)) + return false; + if (di->bus.write(di, 0x3004, 0x00)) + return false; + if (di->bus.write(di, 0x3008, 0x09)) + return false; + if (di->bus.write(di, 0x300C, 0x05)) + return false; + if (di->bus.write(di, 0x300D, 0x1D)) + return false; + if (di->bus.write(di, 0x3040, 0x11)) + return false; + if (di->bus.write(di, 0x3040, 0x10)) + return false; + if (program_bootloader(di)) + return false; + + di->bus.write(di, 0x0400, 0x00); + if (di->bus.write(di, 0x3048, 0xD0)) + return false; + + /* ignoreNAK */ + di->bus.write(di, 0x3040, 0x80); + mdelay(100); + printk(KERN_EMERG "%s:%d\n", __func__, __LINE__); + +#if 0 + for (i = 0; i < 512; i++) { + di->bus.read(di, 0x1c00 + i, data_array[i]); + if (data_array[i] != bootloader_data[i]) { + printk(KERN_EMERG + "MAXUEYUE bootloader check err data[%d]:%02x != boot[%d]:%02x.\n", + i, data_array[i], i, bootloader_data[i]); + return 1; + } + printk(KERN_EMERG "%02x ", data_array[i]); + if (i + 1 % 16 == 0) + printk(KERN_EMERG "\n"); + } +#endif + // + // === Step-2 === + // Program OTP image data to 9220 OTP memory + // + for (i = destAddr; i < destAddr + size; + i += 128) { // program pages of 128 bytes + // + // Build a packet + // + char sBuf[136]; // 136=8+128 --- 8-byte header plus 128-byte data + u16 StartAddr = (u16)i; + u16 CheckSum = StartAddr; + u16 CodeLength = 128; + int retry_cnt = 0; + + memset(sBuf, 0, 136); + + //(1) Copy the 128 bytes of the OTP image data to the packet data buffer + // Array.Copy(srcData, i + srcOffs, sBuf, 8, 128);// Copy 128 bytes from srcData (starting at i+srcOffs) + memcpy(sBuf + 8, src, + 128); // Copy 128 bytes from srcData (starting at i+srcOffs) + src += 128; + // to sBuf (starting at 8) + //srcData --- source array + //i + srcOffs --- start index in source array + //sBuf --- destination array + //8 --- start index in destination array + //128 --- elements to copy + + /* + //(2) Calculate the packet checksum of the 128-byte data, StartAddr, and CodeLength + for (j = 127; j >= 0; j--) { // find the 1st non zero value byte from the end of the sBuf[] buffer + if (sBuf[j + 8] != 0) + break; + else + CodeLength--; + } + if (CodeLength == 0) + continue; // skip programming if nothing to program + */ + + for (j = 127; j >= 0; j--) + CheckSum += sBuf[j + 8]; // add the nonzero values + CheckSum += CodeLength; // finish calculation of the check sum + + //(3) Fill up StartAddr, CodeLength, CheckSum of the current packet. + memcpy(sBuf + 2, &StartAddr, 2); + memcpy(sBuf + 4, &CodeLength, 2); + memcpy(sBuf + 6, &CheckSum, 2); + + // + // Send the current packet to 9220 SRAM via I2C + // + + // read status is guaranteed to be != 1 at this point + for (j = 0; j < CodeLength + 8; j++) { + if (di->bus.write(di, 0x400 + j, sBuf[j])) { + printk("on writing to OTP buffer error"); + return false; + } + } + + // + // Write 1 to the Status in the SRAM. This informs the 9220 to start programming the new packet + // from SRAM to OTP memory + // + if (di->bus.write(di, 0x400, 1)) { + printk("on OTP buffer validation error"); + return false; + } + + // + // Wait for 9220 bootloader to complete programming the current packet image data from SRAM to the OTP. + // The boot loader will update the Status in the SRAM as follows: + // Status: + // "0" - reset value (from AP) + // "1" - buffer validated / busy (from AP) + // "2" - finish "OK" (from the boot loader) + // "4" - programming error (from the boot loader) + // "8" - wrong check sum (from the boot loader) + // "16"- programming not possible (try to write "0" to bit location already programmed to "1") + // (from the boot loader) + + // DateTime startT = DateTime.Now; + do { + mdelay(100); + di->bus.read(di, 0x400, sBuf); + if (sBuf[0] == 1) { + printk("Programming OTP buffer status sBuf:%02x i:%d\n", + sBuf[0], i); + } + if (retry_cnt++ > 5) + break; + } while (sBuf[0] == 1); //check if OTP programming finishes "OK" + + if (retry_cnt > 5) { + printk("Programming OTP buffer retry failed :%d\n", + retry_cnt); + return false; + } else { + di->bus.read(di, 0x401, sBuf); + if (sBuf[0] != 2) { + printk("buffer write to OTP returned status:%d :%s\n", + sBuf[0], "X4"); + return false; + } else { + printk("Program OTP 0x%04x\n", i); + } + } + + /* + if (sBuf[0] != 2) { // not OK + printk("buffer write to OTP returned status:%d :%s\n" , sBuf[0], "X4"); + return false; + } else { + printk("Program OTP 0x%04x\n", i); + } + */ + } + + // === Step-3 === + // Restore system (Need to reset or power cycle 9220 to run the OTP code) + // + if (di->bus.write(di, 0x3000, 0x5a)) + return false; // write key + if (di->bus.write(di, 0x3048, 0x00)) + return false; // remove code remapping + //if (!di->bus.write(0x3040, 0x80)) return false; // reset M0 + return true; +} +#endif + +static int idtp9220_parse_dt(struct idtp9220_device_info *di) +{ + struct device_node *node = di->dev->of_node; + + if (!node) { + dev_err(di->dev, "device tree node missing\n"); + return -EINVAL; + } + + di->dt_props.irq_gpio = of_get_named_gpio(node, "idt,irq", 0); + if ((!gpio_is_valid(di->dt_props.irq_gpio))) + return -EINVAL; + + di->dt_props.hall3_gpio = of_get_named_gpio(node, "hall,int3", 0); + if ((!gpio_is_valid(di->dt_props.hall3_gpio))) + return -EINVAL; + + di->dt_props.hall4_gpio = of_get_named_gpio(node, "hall,int4", 0); + if ((!gpio_is_valid(di->dt_props.hall4_gpio))) + return -EINVAL; + + di->dt_props.reverse_gpio = + of_get_named_gpio(node, "idt,reverse-enable", 0); + if ((!gpio_is_valid(di->dt_props.reverse_gpio))) + return -EINVAL; + + di->dt_props.wpc_det_gpio = of_get_named_gpio(node, "idt,wpc-det", 0); + if ((!gpio_is_valid(di->dt_props.wpc_det_gpio))) + return -EINVAL; + /* + di->dt_props.enable_gpio = of_get_named_gpio(node, "idt,rx-sleep", 0); + if ((!gpio_is_valid(di->dt_props.enable_gpio))) { + dev_err(di->dev, "get enable_gpio fault\n"); + return -EINVAL; + } +*/ + di->dt_props.reverse_boost_enable_gpio = + of_get_named_gpio(node, "idt,reverse-booset-enable", 0); + if ((!gpio_is_valid(di->dt_props.reverse_boost_enable_gpio))) { + dev_err(di->dev, "get reverse_boost_enable_gpio fault\n"); + return -EINVAL; + } + + di->dt_props.wireless_by_usbin = + of_property_read_bool(node, "mi,wireless-by-usbin"); + + di->dt_props.only_idt_on_cmi = + of_property_read_bool(node, "mi,only-idt-on-cmi"); + + di->dt_props.is_urd_device = + of_property_read_bool(node, "mi,urd-device"); + + return 0; +} + +static int idtp9220_gpio_init(struct idtp9220_device_info *di) +{ + int ret = 0; + int irqn = 0; + int wpc_irq = 0; + + di->idt_pinctrl = devm_pinctrl_get(di->dev); + if (IS_ERR_OR_NULL(di->idt_pinctrl)) { + dev_err(di->dev, "No pinctrl config specified\n"); + ret = PTR_ERR(di->dev); + return ret; + } + di->idt_gpio_active = + pinctrl_lookup_state(di->idt_pinctrl, "idt_active"); + if (IS_ERR_OR_NULL(di->idt_gpio_active)) { + dev_err(di->dev, "No active config specified\n"); + ret = PTR_ERR(di->idt_gpio_active); + return ret; + } + di->idt_gpio_suspend = + pinctrl_lookup_state(di->idt_pinctrl, "idt_suspend"); + if (IS_ERR_OR_NULL(di->idt_gpio_suspend)) { + dev_err(di->dev, "No suspend config specified\n"); + ret = PTR_ERR(di->idt_gpio_suspend); + return ret; + } + + ret = pinctrl_select_state(di->idt_pinctrl, di->idt_gpio_active); + if (ret < 0) { + dev_err(di->dev, "fail to select pinctrl active rc=%d\n", ret); + return ret; + } + + if (gpio_is_valid(di->dt_props.irq_gpio)) { + irqn = gpio_to_irq(di->dt_props.irq_gpio); + if (irqn < 0) { + ret = irqn; + goto err_irq_gpio; + } + di->irq = irqn; + } else { + dev_err(di->dev, "%s: irq gpio not provided\n", __func__); + goto err_irq_gpio; + } + + if (gpio_is_valid(di->dt_props.hall3_gpio)) { + irqn = gpio_to_irq(di->dt_props.hall3_gpio); + if (irqn < 0) { + ret = irqn; + goto err_irq_gpio; + } + di->hall3_irq = irqn; + } else { + dev_err(di->dev, "%s:hall3 irq gpio not provided\n", __func__); + goto err_hall3_irq_gpio; + } + + if (gpio_is_valid(di->dt_props.hall4_gpio)) { + irqn = gpio_to_irq(di->dt_props.hall4_gpio); + if (irqn < 0) { + ret = irqn; + goto err_irq_gpio; + } + di->hall4_irq = irqn; + } else { + dev_err(di->dev, "%s:hall4 irq gpio not provided\n", __func__); + goto err_hall4_irq_gpio; + } + + if (gpio_is_valid(di->dt_props.wpc_det_gpio)) { + wpc_irq = gpio_to_irq(di->dt_props.wpc_det_gpio); + if (wpc_irq < 0) { + ret = wpc_irq; + goto err_wpc_irq; + } + di->wpc_irq = wpc_irq; + } else { + dev_err(di->dev, "%s: wpc irq gpio not provided\n", __func__); + goto err_wpc_irq; + } + + if (ret) + goto err_wpc_irq; + +err_wpc_irq: + gpio_free(di->dt_props.wpc_det_gpio); +err_hall4_irq_gpio: + gpio_free(di->dt_props.hall4_gpio); +err_hall3_irq_gpio: + gpio_free(di->dt_props.hall3_gpio); +err_irq_gpio: + gpio_free(di->dt_props.irq_gpio); + return ret; +} + +static bool need_irq_cleared(struct idtp9220_device_info *di) +{ + u8 int_buf[4]; + u32 int_val; + int rc = -1; + + rc = di->bus.read_buf(di, REG_SYS_INT, int_buf, 4); + if (rc < 0) { + dev_err(di->dev, "%s: read int state error\n", __func__); + return true; + } + int_val = int_buf[0] | (int_buf[1] << 8) | (int_buf[2] << 16) | + (int_buf[3] << 24); + if (int_val != 0) { + dev_info(di->dev, "irq not clear right: 0x%08x\n", int_val); + return true; + } + + if (gpio_is_valid(di->dt_props.irq_gpio)) + rc = gpio_get_value(di->dt_props.irq_gpio); + else { + dev_err(di->dev, "%s: irq gpio not provided\n", __func__); + rc = -1; + } + if (!rc) { + dev_info(di->dev, "irq low, need clear int: %d\n", rc); + return true; + } + return false; +} + +static bool reverse_need_irq_cleared(struct idtp9220_device_info *di, u32 val) +{ + u8 int_buf[4]; + u32 int_val; + int rc = -1; + + rc = di->bus.read_buf(di, REG_SYS_INT, int_buf, 4); + if (rc < 0) { + dev_err(di->dev, "%s: read int state error\n", __func__); + return false; + } + int_val = int_buf[0] | (int_buf[1] << 8) | (int_buf[2] << 16) | + (int_buf[3] << 24); + if (int_val && (int_val == val)) { + dev_info(di->dev, "irq clear wrong, retry: 0x%08x\n", int_val); + return true; + } + + return false; +} + +#define VBUCK_QC_VOL 7000 +#define VBUCK_FULL_VOL 7000 +#define VBUCK_DEFAULT_VOL 5500 +#define ADAPTER_DEFAULT_VOL 6000 +#define ADAPTER_BPP_QC_VOL 10000 +#define ADAPTER_BPP_QC2_VOL 6500 +#define ADAPTER_EPP_QC3_VOL 11000 +#define ADAPTER_BPP_LIMIT_VOL 6500 +#define ADAPTER_VOUT_LIMIT_VOL 7000 +#define BPP_VOL_THRESHOLD 8000 +#define ADAPTER_BPP_VOL 5000 +#define ADAPTER_EPP_MI_VOL 15000 +#define EPP_VOL_THRESHOLD 12000 +#define EPP_VOL_LIM_THRESHOLD 13000 +#define BPP_VOL_LIM_THRESHOLD 10500 +#define CHARGING_PERIOD_S 10 +#define TAPER_CURR_Limit 950000 + +static void idtp9220_monitor_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, chg_monitor_work.work); + + idtp9220_charging_info(di); + + idtp9220_set_charging_param(di); + + schedule_delayed_work(&di->chg_monitor_work, CHARGING_PERIOD_S * HZ); +} + +static void idtp9220_rx_vout_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, rx_vout_work.work); + + idtp9220_set_charging_param(di); +} + +static void idtp9220_dc_check_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, dc_check_work.work); + + if (di->vout_on) { + di->ss = 1; + dev_info(di->dev, "dcin present, quit dc check work\n"); + return; + } else { + di->ss = 0; + dev_info(di->dev, "dcin no present, continue dc check work\n"); + schedule_delayed_work(&di->dc_check_work, + msecs_to_jiffies(2500)); + } +} + +static void idtp9220_chg_detect_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, chg_detect_work.work); + + union power_supply_propval val = { + 0, + }; + union power_supply_propval pc_val = { + 0, + }; + int rc; + bool valid_typec_mode = false; + + dev_info(di->dev, "[idt] enter %s\n", __func__); + + rc = idtp9220_get_property_names(di); + if (rc < 0) + return; + /*set idtp9220 into sleep mode when usbin */ + power_supply_get_property(di->usb_psy, POWER_SUPPLY_PROP_TYPEC_MODE, + &val); + power_supply_get_property(di->pc_port_psy, POWER_SUPPLY_PROP_ONLINE, + &pc_val); + if (val.intval >= POWER_SUPPLY_TYPEC_SOURCE_DEFAULT && + val.intval <= POWER_SUPPLY_TYPEC_SOURCE_HIGH) + valid_typec_mode = true; + + if (valid_typec_mode || pc_val.intval) { + dev_info(di->dev, + "typec_mode: %d or pc online: %d,set chip disable\n", + val.intval, pc_val.intval); + //idtp9220_set_enable_mode(di, false); + //schedule_delayed_work(&di->fw_download_work, 1 * HZ); + return; + } + + /* reset rx for bootup charging */ + idtp9220_set_enable_mode(di, false); + msleep(10); + idtp9220_set_enable_mode(di, true); +} + +static void idtp9220_bpp_connect_load_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, bpp_connect_load_work.work); + dev_info(di->dev, "[idt] %s: \n", __func__); + idtp922x_set_pmi_icl(di, BPP_DEFAULT_CURRENT / 3); + if (di->bpp_break || !di->power_good_flag) + return; + msleep(300); + idtp922x_set_pmi_icl(di, (BPP_DEFAULT_CURRENT / 3) * 2); + if (di->bpp_break || !di->power_good_flag) + return; + msleep(300); + idtp922x_set_pmi_icl(di, BPP_DEFAULT_CURRENT); +} + +static void idtp9220_epp_connect_load_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, epp_connect_load_work.work); + int dc_load_curr = 0; + + if (di->power_max < 10000) { + dc_load_curr = (di->power_max - 1000) / 11 * 1000; + + } else { + dc_load_curr = EPP_DEFAULT_BYPASS_CURRENT; + } + + idtp922x_set_pmi_icl(di, dc_load_curr); +} + +static void idtp9220_cmd_check_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, cmd_check_work.work); + + dev_info(di->dev, "[idt] %s: \n", __func__); + idtp922x_get_tx_vin(di); + if (di->power_off_mode) { + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(10)); + } +} + +static void idtp9220_initial_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, initial_tx_work.work); + int ret = 0; + u8 buf[2] = { 0 }; + u16 int_val = 0; + + ret = idtp9220_get_power_profile(di); + if (ret) { + ret = di->bus.read_buf(di, REG_TX_TYPE, buf, 2); + if (ret < 0) + dev_err(di->dev, "read tx type error: %d\n", ret); + else { + int_val = buf[0] | (buf[1] << 8); + dev_info(di->dev, "tx type: 0x%04x\n", int_val); + } + } + + /* check dc present to judge device skewing */ + if (int_val == 0x0059) { + dev_info(di->dev, "mophie tx, start check dc with 8s\n"); + schedule_delayed_work(&di->dc_check_work, + msecs_to_jiffies(8000)); + } else + schedule_delayed_work(&di->dc_check_work, + msecs_to_jiffies(2500)); +} + +static int idt_get_effective_fcc(struct idtp9220_device_info *di) +{ + int effective_fcc_val = 0; + + if (!di->fcc_votable) + di->fcc_votable = find_votable("FCC"); + + if (!di->fcc_votable) + return -EINVAL; + + effective_fcc_val = get_effective_result(di->fcc_votable); + effective_fcc_val = effective_fcc_val / 1000; + dev_info(di->dev, "effective_fcc: %d\n", effective_fcc_val); + return effective_fcc_val; +} + +#define VOICE_THERMAL_FCC_HOT_MA 500 +#define VOICE_THERMAL_FCC_WARM_MA 1300 +#define VOICE_TEMP_HOT_UP_LIMIT 402 +#define VOICE_TEMP_HOT_DOWN_LIMIT 400 +#define VOICE_TEMP_WARM_UP_LIMIT 375 +#define VOICE_TEMP_WARM_DOWN_LIMIT 367 +#define VOICE_MAX_ICL_UA 1500000 +static void idt_voice_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, voice_tx_work.work); + + int soc = 0, batt_sts = 0, dc_level = 0, batt_temp = 0; + int adapter_vol = ADAPTER_EPP_MI_VOL; + int icl_curr = VOICE_MAX_ICL_UA; + int effective_fcc = 0; + bool vout_change = false; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + int vout = 0; + di->bpp_break = 1; + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, + &val); + dc_level = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_TEMP, + &val); + batt_temp = val.intval; + } + + dev_info(di->dev, "soc:%d, dc_level:%d, bat_status:%d, batt_temp: %d\n", + soc, dc_level, batt_sts, batt_temp); + + switch (di->status) { + case NORMAL_MODE: + if (soc >= EPP_TAPER_SOC) + di->status = TAPER_MODE; + break; + case TAPER_MODE: + dev_info(di->dev, "[voice]taper mode set Vin 11V\n"); + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + di->status = FULL_MODE; + else if (soc < 95) + di->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(di->dev, "[voice]charge full set Vin 11V\n"); + adapter_vol = EPP_VOL_THRESHOLD; + icl_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + dev_info(di->dev, + "[voice]full mode -> recharge mode\n"); + di->status = RECHG_MODE; + icl_curr = DC_LOW_CURRENT; + } + break; + case RECHG_MODE: + if (batt_sts == POWER_SUPPLY_STATUS_FULL) { + dev_info(di->dev, + "[voice]recharge mode -> full mode\n"); + di->status = FULL_MODE; + icl_curr = SCREEN_OFF_FUL_CURRENT; + adapter_vol = EPP_VOL_THRESHOLD; + if (di->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + } + + dev_info(di->dev, "[voice]recharge mode set icl to 350mA\n"); + adapter_vol = EPP_VOL_THRESHOLD; + icl_curr = DC_LOW_CURRENT; + + if (di->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + } + break; + default: + break; + } + effective_fcc = idt_get_effective_fcc(di); + /* + if (batt_temp >= VOICE_TEMP_HOT_UP_LIMIT) { + dev_info(di->dev, "[voice]Tbat limit fcc 1A\n"); + effective_fcc = idt_get_effective_fcc(di); + if (di->fcc_votable) { + effective_fcc = VOICE_THERMAL_FCC_HOT_MA; + vote(di->fcc_votable, VOICE_LIMIT_FCC_1A_VOTER, + true, effective_fcc * 1000); + } + } else if (batt_temp < VOICE_TEMP_HOT_DOWN_LIMIT) { + if (di->fcc_votable) + vote(di->fcc_votable, VOICE_LIMIT_FCC_1A_VOTER, + false, 0); + } + + if (batt_temp >= VOICE_TEMP_WARM_UP_LIMIT) { + dev_info(di->dev, "[voice]Tbat limit fcc 3.2A\n"); + effective_fcc = idt_get_effective_fcc(di); + if (di->fcc_votable) { + effective_fcc = VOICE_THERMAL_FCC_WARM_MA; + vote(di->fcc_votable, VOICE_LIMIT_FCC_VOTER, + true, effective_fcc * 1000); + } + } else if (batt_temp < VOICE_TEMP_WARM_DOWN_LIMIT) { + if (di->fcc_votable) + vote(di->fcc_votable, VOICE_LIMIT_FCC_VOTER, + false, 0); + } +*/ + if (dc_level) { + di->disable_cp = true; + /* disable cp charger */ + if (di->wireless_psy) { + val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + dev_info(di->dev, "[voice]Disable cp, dc_level:%d\n", dc_level); + } + + if (di->cp_regulator_done) + adapter_vol = EPP_VOL_THRESHOLD; + + if (!di->enable_ext5v) { + di->enable_ext5v = true; + idtp922x_enable_ext5v(di); + } + + if (adapter_vol > 0 && adapter_vol != di->last_vin) { + if ((adapter_vol == ADAPTER_EPP_MI_VOL) && + !di->first_rise_flag) { + di->disable_cp = false; + di->first_rise_flag = true; + idtp922x_set_adap_vol(di, adapter_vol); + di->vswitch_ok = false; + msleep(110); + } else if ((adapter_vol == ADAPTER_EPP_MI_VOL) && + di->first_rise_flag) { + di->disable_cp = false; + idtp9220_set_vout(di, adapter_vol); + msleep(110); + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(400)); + } else if (adapter_vol == EPP_VOL_THRESHOLD) { + vout = idtp9220_get_vout(di); + while (vout > EPP_VOL_THRESHOLD) { + vout = vout - 1000; + idtp9220_set_vout(di, vout); + msleep(200); + } + idtp9220_set_vout(di, EPP_VOL_THRESHOLD); + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + } + vout_change = true; + di->last_vin = adapter_vol; + } + + if ((icl_curr > 0 && icl_curr != di->last_icl) || vout_change) { + di->last_icl = icl_curr; + idtp922x_set_pmi_icl(di, icl_curr); + msleep(100); + } + + dev_info( + di->dev, + "di->status:0x%x,adapter_vol=%d,icl_curr=%d,last_vin=%d,last_icl=%d, bq_dis:%d\n", + di->status, adapter_vol, icl_curr, di->last_vin, di->last_icl, + di->disable_cp); + + return; +} + +#define PAN_BBC_ICL_MA 1300000 +static void idt_pan_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, pan_tx_work.work); + + int soc = 0, batt_sts = 0, dc_level = 0; + int adapter_vol = ADAPTER_EPP_MI_VOL; + int icl_curr = DC_PAN_CURRENT_UA; + bool vout_change = false; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + int vout = 0; + di->bpp_break = 1; + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, + &val); + dc_level = val.intval; + } + + dev_info(di->dev, "soc:%d, dc_level:%d, bat_status:%d\n", soc, dc_level, + batt_sts); + + switch (di->status) { + case NORMAL_MODE: + if (soc >= FULL_SOC) + di->status = TAPER_MODE; + break; + case TAPER_MODE: + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + di->status = FULL_MODE; + else if (soc < FULL_SOC - 1) + di->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(di->dev, "[pan]charge full set Vin 12V\n"); + adapter_vol = EPP_VOL_THRESHOLD; + icl_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + dev_info(di->dev, "[pan]full mode -> recharge mode\n"); + di->status = RECHG_MODE; + icl_curr = DC_LOW_CURRENT; + } + break; + case RECHG_MODE: + if (batt_sts == POWER_SUPPLY_STATUS_FULL) { + dev_info(di->dev, "recharge mode -> full mode\n"); + di->status = FULL_MODE; + icl_curr = SCREEN_OFF_FUL_CURRENT; + adapter_vol = EPP_VOL_THRESHOLD; + if (di->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + } + + dev_info(di->dev, "recharge mode set icl to 350mA\n"); + adapter_vol = EPP_VOL_THRESHOLD; + icl_curr = DC_LOW_CURRENT; + + if (di->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + } + break; + default: + break; + } + + if (dc_level) { + dev_info(di->dev, "Disable bq, dc_level:%d\n", dc_level); + di->disable_cp = true; + if (di->wireless_psy) { + val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + + if (di->cp_regulator_done) { + adapter_vol = EPP_VOL_THRESHOLD; + icl_curr = PAN_BBC_MAX_ICL_MA; + } + } + + if (!di->enable_ext5v) { + di->enable_ext5v = true; + idtp922x_enable_ext5v(di); + } + + if (adapter_vol > 0 && adapter_vol != di->last_vin) { + if ((adapter_vol == ADAPTER_EPP_MI_VOL) && + !di->first_rise_flag) { + di->disable_cp = false; + di->first_rise_flag = true; + idtp922x_set_adap_vol(di, adapter_vol); + di->vswitch_ok = false; + msleep(110); + } else if ((adapter_vol == ADAPTER_EPP_MI_VOL) && + di->first_rise_flag) { + di->disable_cp = false; + idtp9220_set_vout(di, adapter_vol); + msleep(110); + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(400)); + } else if (adapter_vol == EPP_VOL_THRESHOLD) { + vout = idtp9220_get_vout(di); + while (vout > EPP_VOL_THRESHOLD) { + vout = vout - 1000; + idtp9220_set_vout(di, vout); + msleep(200); + } + idtp9220_set_vout(di, EPP_VOL_THRESHOLD); + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + } + vout_change = true; + di->last_vin = adapter_vol; + } + + if ((icl_curr > 0 && icl_curr != di->last_icl) || vout_change) { + di->last_icl = icl_curr; + idtp922x_set_pmi_icl(di, icl_curr); + msleep(100); + } + + dev_info( + di->dev, + "di->status:0x%x,adapter_vol=%d,icl_curr=%d,last_vin=%d,last_icl=%d, bq_dis:%d\n", + di->status, adapter_vol, icl_curr, di->last_vin, di->last_icl, + di->disable_cp); + + return; +} + +static void idtp9220_bpp_e5_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, bpp_e5_tx_work.work); + int icl_curr = BPP_QC_7W_CURRENT, adapter_vol = ADAPTER_BPP_QC_VOL; + int soc = 0, batt_sts = 0, health = 0; + int icl_setted = 0; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_HEALTH, &val); + health = val.intval; + } + + if (di->tx_charger_type == ADAPTER_QC2) + icl_curr = 750000; + + if (di->iout < LIMIT_BPP_IOUT && di->exchange == EXCHANGE_9V) { + di->count_5v++; + di->count_9v = 0; + } else if (di->iout > LIMIT_BPP_IOUT && di->exchange == EXCHANGE_5V) { + di->count_9v++; + di->count_5v = 0; + } else { + di->count_5v = 0; + di->count_9v = 0; + } + /* + * 9V-->5V check 6 times + * 5V-->9v check 3 times + */ + if (di->count_5v > ICL_EXCHANGE_COUNT || + (di->exchange == EXCHANGE_5V && + di->count_9v <= ICL_EXCHANGE_COUNT - 3)) { + dev_info(di->dev, "iout less than 400mA ,set vout to 5.5v\n"); + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = DC_BPP_CURRENT; + di->exchange = EXCHANGE_5V; + } else if (di->count_9v > (ICL_EXCHANGE_COUNT - 3)) + di->exchange = EXCHANGE_9V; + + if (soc > 90) + icl_curr = DC_BPP_CURRENT; + + switch (di->status) { + case NORMAL_MODE: + if (soc >= EPP_TAPER_SOC) { + di->status = TAPER_MODE; + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = min(DC_SDP_CURRENT, icl_curr); + } + break; + case TAPER_MODE: + dev_info(di->dev, "[bpp] taper mode set vout to 5.5v\n"); + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = min(DC_SDP_CURRENT, icl_curr); + + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + di->status = FULL_MODE; + else if (soc < EPP_TAPER_SOC - 1) + di->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(di->dev, "[bpp] charge full set vout to 5.5v\n"); + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + di->status = RECHG_MODE; + icl_curr = DC_LOW_CURRENT; + } + break; + case RECHG_MODE: + dev_info(di->dev, "[bpp] recharge mode set icl to 360mA\n"); + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = DC_LOW_CURRENT; + + if (soc < EPP_TAPER_SOC - 1) + di->status = NORMAL_MODE; + else if (batt_sts == POWER_SUPPLY_STATUS_FULL) + di->status = FULL_MODE; + + if (di->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, &wk_val); + } + break; + default: + break; + } + + switch (health) { + case POWER_SUPPLY_HEALTH_GOOD: + break; + case POWER_SUPPLY_HEALTH_COOL: + break; + case POWER_SUPPLY_HEALTH_WARM: + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = min(DC_SDP_CURRENT, icl_curr); + break; + case POWER_SUPPLY_HEALTH_OVERVOLTAGE: + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = min(SCREEN_OFF_FUL_CURRENT, icl_curr); + break; + case POWER_SUPPLY_HEALTH_COLD: + case POWER_SUPPLY_HEALTH_HOT: + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = SCREEN_OFF_FUL_CURRENT; + break; + default: + break; + } + + if (adapter_vol != di->last_bpp_vout) { + dev_info(di->dev, "bpp_10w, set new vout: %d, last_vout: %d\n", + adapter_vol, di->last_bpp_vout); + if (adapter_vol > BPP_VOL_THRESHOLD) { + idtp922x_set_adap_vol(di, adapter_vol); + idtp922x_enable_ext5v(di); + msleep(400); + } else { + idtp922x_set_pmi_icl(di, 100000); + msleep(100); + idtp922x_set_adap_vol(di, adapter_vol); + msleep(2000); + idtp922x_set_pmi_icl(di, DC_SDP_CURRENT); + msleep(100); + icl_setted = 1; + } + di->last_bpp_vout = adapter_vol; + } + + if ((icl_curr != di->last_bpp_icl) || (icl_setted)) { + dev_info(di->dev, "bpp_10w, set new icl: %d, last_icl: %d\n", + icl_curr, di->last_bpp_icl); + di->last_bpp_icl = icl_curr; + di->bpp_break = true; + cancel_delayed_work_sync(&di->bpp_connect_load_work); + if ((adapter_vol == ADAPTER_BPP_QC_VOL) && + (!di->bpp_vout_rise)) { + dev_info(di->dev, + "bpp_10w, vout lower than 8v, set 500mA\n"); + icl_curr = min(DC_SDP_CURRENT, icl_curr); + } + idtp922x_set_pmi_icl(di, icl_curr); + } +} + +static void idtp9220_qc2_f1_tx_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, qc2_f1_tx_work.work); + int soc = 0, batt_sts = 0; + int vout = ADAPTER_BPP_QC2_VOL; + int dc_icl = DC_QC2_CURRENT; + union power_supply_propval val = { + 0, + }; + + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + } + + if (soc >= 95) + dc_icl = DC_DCP_CURRENT; + if (soc == 100) + dc_icl = DC_LOW_CURRENT; + + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) { + dev_info(di->dev, + "qc2+f1_tx, full mode set vout to 8V,icl to 250mA\n"); + dc_icl = SCREEN_OFF_FUL_CURRENT; + } + + if (vout != di->last_qc2_vout) { + dev_info(di->dev, + "qc2+f1_tx, set new vout: %d, last_vout: %d\n", vout, + di->last_qc2_vout); + di->last_qc2_vout = vout; + idtp9220_set_vout(di, vout); + msleep(200); + if (vout == ADAPTER_BPP_QC_VOL) + idtp922x_enable_ext5v(di); + } + + if (dc_icl != di->last_qc2_icl) { + dev_info(di->dev, "qc2+f1_tx, set new icl: %d, last_icl: %d\n", + dc_icl, di->last_qc2_icl); + di->last_qc2_icl = dc_icl; + idtp922x_set_pmi_icl(di, dc_icl); + } +} + +static void idtp9220_qc3_epp_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, qc3_epp_work.work); + int soc = 0, batt_sts = 0; + int adapter_vol = ADAPTER_EPP_QC3_VOL; + int dc_icl = DC_EPP_QC3_CURRENT; + union power_supply_propval val = { + 0, + }; + + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + } + + if (soc >= 97) + dc_icl = DC_BPP_CURRENT; + + if (soc == 100) + dc_icl = DC_SDP_CURRENT; + + if (soc == FULL_SOC && batt_sts == POWER_SUPPLY_STATUS_FULL) + dc_icl = SCREEN_OFF_FUL_CURRENT; + + if (adapter_vol != di->last_qc3_vout) { + dev_info(di->dev, "qc3 epp, set new vout: %d, last_vout: %d\n", + adapter_vol, di->last_qc3_vout); + di->last_qc3_vout = adapter_vol; + idtp9220_set_vout(di, adapter_vol); + msleep(200); + if (adapter_vol == ADAPTER_EPP_QC3_VOL) + idtp922x_enable_ext5v(di); + } + + if (dc_icl != di->last_qc3_icl) { + dev_info(di->dev, "qc3_epp, set new icl: %d, last_icl: %d\n", + dc_icl, di->last_qc3_icl); + di->last_qc3_icl = dc_icl; + idtp922x_set_pmi_icl(di, dc_icl); + msleep(100); + } +} + +static void idtp9220_vout_regulator_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, vout_regulator_work.work); + + union power_supply_propval val = { + 0, + }; + int ret; + int vinc = 0; + int soc = 0; + int dc_level = 0; + int need_cp = true; + printk("idtp9220_vout_regulator_work\n"); + + if (di->batt_psy) { + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &val); + soc = val.intval; + + power_supply_get_property(di->batt_psy, + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, + &val); + dc_level = val.intval; + } + + if (di) + idtp9220_get_vout(di); + else + return; + + if (di->epp) + vinc = (di->vout > EPP_VOL_THRESHOLD) ? 1 : 0; + else + vinc = (di->vout > BPP_VOL_THRESHOLD) ? 1 : 0; + + if (vinc && !di->epp) { + di->bpp_vout_rise = 1; + goto out; + } else if (!vinc && !di->epp) { + di->bpp_vout_rise = 0; + goto out; + } + /* for pan and voice tx, do not open cp while thermal high */ + if ((di->is_pan_tx || di->is_voice_box_tx) && dc_level) { + need_cp = false; + } + + if (di->epp && vinc && soc < TAPER_SOC - 1 && need_cp) { + dev_info(di->dev, "%s: open charge pump by wireless\n", + __func__); + ret = idtp9220_get_property_names(di); + if (di->wireless_psy) { + val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } else { + dev_err(di->dev, "[idt] no wireless psy\n"); + } + } else { + dev_info(di->dev, "%s: close charge pump by wireless\n", + __func__); + if (di->wireless_psy) { + val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, &val); + } + // set vout to 14.2v + msleep(200); + idtp9220_set_vout(di, CP_CLOSE_VOUT_MV); + } + +out: + dev_info(di->dev, "%s: epp=%d vout= %d\n", __func__, di->epp, di->vout); + return; +} + +static int fod_over_write(struct idtp9220_device_info *di, int mode) +{ + int ret = 0; + + switch (mode) { + case EPP_PLUS_VOL: + if (di->is_zm_20w_tx) { + di->bus.write(di, 0x68, 0x98); + di->bus.write(di, 0x69, 0x46); + di->bus.write(di, 0x6A, 0x98); + di->bus.write(di, 0x6B, 0x46); + di->bus.write(di, 0x6C, 0x87); + di->bus.write(di, 0x6D, 0x69); + di->bus.write(di, 0x6E, 0x87); + di->bus.write(di, 0x6F, 0x69); + di->bus.write(di, 0x70, 0x95); + di->bus.write(di, 0x71, 0x1b); + di->bus.write(di, 0x72, 0x87); + di->bus.write(di, 0x73, 0x7D); + } else if (!di->is_f1_tx) { + di->bus.write(di, 0x68, 0x98); + di->bus.write(di, 0x69, 0x46); + di->bus.write(di, 0x6A, 0x98); + di->bus.write(di, 0x6B, 0x46); + di->bus.write(di, 0x6C, 0x87); + di->bus.write(di, 0x6D, 0x69); + di->bus.write(di, 0x6E, 0x87); + di->bus.write(di, 0x6F, 0x69); + di->bus.write(di, 0x70, 0x89); + di->bus.write(di, 0x71, 0x1b); + di->bus.write(di, 0x72, 0x87); + di->bus.write(di, 0x73, 0x7D); + } else { + di->bus.write(di, 0x68, 0x82); + di->bus.write(di, 0x69, 0x78); + di->bus.write(di, 0x6A, 0x82); + di->bus.write(di, 0x6B, 0x78); + di->bus.write(di, 0x6C, 0x80); + di->bus.write(di, 0x6D, 0x7d); + di->bus.write(di, 0x6E, 0x80); + di->bus.write(di, 0x6F, 0x7d); + di->bus.write(di, 0x70, 0x89); + di->bus.write(di, 0x71, 0x43); + di->bus.write(di, 0x72, 0x88); + di->bus.write(di, 0x73, 0x7f); + } + ret = 1; + break; + case EPP_BASE_VOL: + di->bus.write(di, 0x68, 0x93); + di->bus.write(di, 0x69, 0x44); + di->bus.write(di, 0x6A, 0x93); + di->bus.write(di, 0x6B, 0x44); + di->bus.write(di, 0x6C, 0x96); + di->bus.write(di, 0x6D, 0x17); + di->bus.write(di, 0x6E, 0x96); + di->bus.write(di, 0x6F, 0x17); + di->bus.write(di, 0x70, 0x95); + di->bus.write(di, 0x71, 0x16); + di->bus.write(di, 0x72, 0x91); + di->bus.write(di, 0x73, 0x39); + /* + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + */ + ret = 1; + break; + case BPP_PLUS_VOL: + di->bus.write(di, 0x68, 0x9C); + di->bus.write(di, 0x69, 0x29); + di->bus.write(di, 0x6A, 0x57); + di->bus.write(di, 0x6B, 0x7B); + di->bus.write(di, 0x6C, 0x57); + di->bus.write(di, 0x6D, 0x7B); + di->bus.write(di, 0x6E, 0x96); + di->bus.write(di, 0x6F, 0x00); + di->bus.write(di, 0x70, 0x93); + di->bus.write(di, 0x71, 0x0A); + di->bus.write(di, 0x72, 0x93); + di->bus.write(di, 0x73, 0x0A); + /* + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + */ + ret = 1; + break; + case FULL_VOL: + di->bus.write(di, 0x68, 0x9C); + di->bus.write(di, 0x69, 0x29); + di->bus.write(di, 0x6A, 0x57); + di->bus.write(di, 0x6B, 0x7B); + di->bus.write(di, 0x6C, 0x57); + di->bus.write(di, 0x6D, 0x7B); + di->bus.write(di, 0x6E, 0x9E); + di->bus.write(di, 0x6F, 0x08); + di->bus.write(di, 0x70, 0x9D); + di->bus.write(di, 0x71, 0x05); + di->bus.write(di, 0x72, 0x96); + di->bus.write(di, 0x73, 0x28); + /* + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + di->bus.write(di, 0xFF, 0x7F); + */ + ret = 1; + break; + default: + ret = 0; + break; + } + return ret; +} + +static int fod_param_verity(struct idtp9220_device_info *di, int mode) +{ + u8 data_l = 0, data_h = 0; + int ret = 0; + + di->bus.read(di, 0x72, &data_l); + di->bus.read(di, 0x73, &data_h); + + switch (mode) { + case EPP_PLUS_VOL: + if (data_l == 0x97 && data_h == 0xD1) + ret = 1; + else + ret = 0; + break; + case EPP_BASE_VOL: + if (data_l == 0x91 && data_h == 0x39) + ret = 1; + else + ret = 0; + break; + case BPP_PLUS_VOL: + if (data_l == 0x93 && data_h == 0x14) + ret = 1; + else + ret = 0; + break; + case FULL_VOL: + if (data_l == 0x96 && data_h == 0x28) + ret = 1; + else + ret = 0; + break; + default: + ret = 0; + break; + } + + return ret; +} + +static void reverse_chg_sent_state_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = + container_of(work, struct idtp9220_device_info, + reverse_sent_state_work.work); + union power_supply_propval val = { + 0, + }; + + if (di->wireless_psy) { + if (di->is_reverse_chg == 4) + idt_get_reverse_soc(di); + val.intval = di->is_reverse_chg; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_REVERSE_PEN_CHG_STATE, &val); + power_supply_changed(di->wireless_psy); + dev_info(di->dev, "uevent: %d for reverse charging state\n", + di->is_reverse_chg); + } else + dev_err(di->dev, "get wls property error\n"); +} + +static void reverse_chg_state_set_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, reverse_chg_state_work.work); + + dev_info(di->dev, "no rx found and disable reverse charging\n"); + + mutex_lock(&di->reverse_op_lock); + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 1; + mutex_unlock(&di->reverse_op_lock); + schedule_delayed_work(&di->reverse_sent_state_work, 0); + + return; +} + +static void reverse_dping_state_set_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = + container_of(work, struct idtp9220_device_info, + reverse_dping_state_work.work); + + dev_info(di->dev, "tx mode fault and disable reverse charging\n"); + + mutex_lock(&di->reverse_op_lock); + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 2; + mutex_unlock(&di->reverse_op_lock); + schedule_delayed_work(&di->reverse_sent_state_work, 0); + + return; +} +static void reverse_test_state_set_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = + container_of(work, struct idtp9220_device_info, + reverse_test_state_work.work); + + dev_info( + di->dev, + "[ factory reverse test ]tx mode fault and disable reverse charging\n"); + + mutex_lock(&di->reverse_op_lock); + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 2; + mutex_unlock(&di->reverse_op_lock); + schedule_delayed_work(&di->reverse_sent_state_work, 0); + pm_relax(di->dev); + return; +} + +static void reverse_ept_type_get_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, reverse_ept_type_work.work); + int rc; + u8 buf[2] = { 0 }; + u16 ept_val = 0; + + rc = di->bus.read_buf(di, REG_EPT_TYPE, buf, 2); + if (rc < 0) + dev_err(di->dev, "read tx ept type error: %d\n", rc); + else { + ept_val = buf[0] | (buf[1] << 8); + dev_info(di->dev, "tx ept type: 0x%04x\n", ept_val); + if (ept_val) { + if ((ept_val & EPT_FOD) || (ept_val & EPT_CMD) || + (ept_val & EPT_OCP) || (ept_val & EPT_OVP) || + (ept_val & EPT_LVP) || (ept_val & EPT_OTP) || + (ept_val & EPT_POCP)) { + dev_info( + di->dev, + "TX mode in ept and disable reverse charging\n"); + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 2; + schedule_delayed_work( + &di->reverse_sent_state_work, 0); + } else if (ept_val & EPT_CEP_TIMEOUT) { + dev_info(di->dev, "recheck ping state\n"); + di->is_reverse_chg = 5; + schedule_delayed_work( + &di->reverse_sent_state_work, 0); + } + } + } + + return; +} + +static void idtp9220_load_fod_param_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, load_fod_param_work.work); + int fod_param = 0; + int ret = 0, val = 0; + + if (!di->vout) + idtp9220_get_vout(di); + + if (di->vout > EPP_VOL_LIM_THRESHOLD) + fod_param = EPP_PLUS_VOL; + else if (di->vout > BPP_VOL_LIM_THRESHOLD && + di->vout < EPP_VOL_LIM_THRESHOLD) + fod_param = EPP_BASE_VOL; + else if (di->vout > BPP_VOL_THRESHOLD && + di->vout < BPP_VOL_LIM_THRESHOLD) + fod_param = BPP_PLUS_VOL; + else if (di->vout > 0 && di->vout < BPP_VOL_THRESHOLD) + fod_param = FULL_VOL; + + val = fod_over_write(di, fod_param); + msleep(50); + if (val) { + ret = fod_param_verity(di, fod_param); + if (!ret) + fod_over_write(di, fod_param); + } else + fod_over_write(di, fod_param); + + dev_info(di->dev, "[idt] %d mV fod load %s\n", di->vout, + (ret ? "success" : "fail")); + return; +} + +static int idtp9220_get_charging_current(struct idtp9220_device_info *di) +{ + switch (di->tx_charger_type) { + case ADAPTER_XIAOMI_QC3: + case ADAPTER_XIAOMI_PD: + case ADAPTER_ZIMI_CAR_POWER: + return ICL_CP_2SBATT_20W_MA; + case ADAPTER_XIAOMI_PD_40W: + case ADAPTER_VOICE_BOX: + return ICL_CP_2SBATT_30W_MA; + case ADAPTER_XIAOMI_PD_45W: + case ADAPTER_XIAOMI_PD_60W: + return ICL_CP_2SBATT_40W_MA; + default: + break; + } + return DC_QC3_CURRENT; +} +static int idtp9220_get_taper_charging_current(struct idtp9220_device_info *di) +{ + switch (di->tx_charger_type) { + case ADAPTER_XIAOMI_QC3: + case ADAPTER_XIAOMI_PD: + case ADAPTER_ZIMI_CAR_POWER: + return ICL_TAPER_2SBATT_20W_MA; + case ADAPTER_XIAOMI_PD_40W: + case ADAPTER_VOICE_BOX: + return ICL_TAPER_2SBATT_30W_MA; + case ADAPTER_XIAOMI_PD_45W: + case ADAPTER_XIAOMI_PD_60W: + return ICL_TAPER_2SBATT_40W_MA; + default: + break; + } + return DC_QC3_CURRENT; +} + +static void idtp9220_set_charging_param(struct idtp9220_device_info *di) +{ + int soc = 0, health = 0, batt_sts = 0; + int adapter_vol = 0, icl_curr = 0; + int cur_now = 0, vol_now = 0, vin_inc = 0; + bool vout_change = false; + union power_supply_propval val = { + 0, + }; + union power_supply_propval wk_val = { + 0, + }; + int vout = 0; + + switch (di->tx_charger_type) { + case ADAPTER_QC2: + adapter_vol = ADAPTER_BPP_QC2_VOL; //6.5V + di->bpp_break = 1; + icl_curr = DC_QC2_CURRENT; //1A + break; + case ADAPTER_QC3: + if (!di->epp) { + adapter_vol = ADAPTER_BPP_QC_VOL; + icl_curr = DC_QC3_CURRENT; //1A + } else { + di->is_epp_qc3 = 1; + adapter_vol = ADAPTER_EPP_QC3_VOL; //11V + icl_curr = DC_EPP_QC3_CURRENT; + } + break; + case ADAPTER_PD: + if (di->epp) { + adapter_vol = ADAPTER_EPP_QC3_VOL; + icl_curr = DC_EPP_QC3_CURRENT; + } else { + adapter_vol = ADAPTER_DEFAULT_VOL; //6V + icl_curr = DC_PD_CURRENT; //800mA + } + break; + case ADAPTER_AUTH_FAILED: + if (di->epp) { + adapter_vol = ADAPTER_EPP_QC3_VOL; + if (di->power_max < 10000) { + icl_curr = ((di->power_max - 1000) / 11) * 1000; + } else { + icl_curr = EPP_DEFAULT_BYPASS_CURRENT; + } + } else { + adapter_vol = ADAPTER_DEFAULT_VOL; //6V + icl_curr = di->bpp_icl; + } + break; + case ADAPTER_DCP: + case ADAPTER_CDP: + adapter_vol = ADAPTER_DEFAULT_VOL; //6V + if (di->is_compatible_hwid) + icl_curr = DC_BPP_AUTH_FAIL_CURRENT; //860mA + else + icl_curr = DC_BPP_AUTH_FAIL_CURRENT; + break; + case ADAPTER_SDP: + adapter_vol = ADAPTER_DEFAULT_VOL; + icl_curr = 500000; + break; + case ADAPTER_XIAOMI_QC3: + case ADAPTER_XIAOMI_PD: + case ADAPTER_ZIMI_CAR_POWER: + case ADAPTER_XIAOMI_PD_40W: + case ADAPTER_VOICE_BOX: + case ADAPTER_XIAOMI_PD_45W: + case ADAPTER_XIAOMI_PD_60W: + if (di->epp) { + adapter_vol = ADAPTER_EPP_MI_VOL; + icl_curr = idtp9220_get_charging_current(di); + } else { + adapter_vol = ADAPTER_BPP_QC_VOL; + icl_curr = DC_QC3_CURRENT; + } + break; + default: + icl_curr = 0; + break; + } + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_STATUS, &val); + batt_sts = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_CAPACITY, + &val); + soc = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, + &val); + vol_now = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_CURRENT_NOW, + &val); + cur_now = val.intval; + + power_supply_get_property(di->batt_psy, POWER_SUPPLY_PROP_HEALTH, &val); + health = val.intval; + + idtp9220_get_iout(di); + + if ((batt_sts == POWER_SUPPLY_STATUS_DISCHARGING) && di->dcin_present && + di->power_good_flag) { + dev_info(di->dev, + "discharge when dc and pwr present, reset chip\n"); + return; + } + dev_info( + di->dev, + "[idtp] soc:%d,vol_now:%d,cur_now:%d,health:%d, bat_status:%d\n", + soc, vol_now, cur_now, health, batt_sts); + + /* adapter:qc2/qc3; tx:e5/d5x_10W; + * vout/psns is setted in delayed work + */ + if (adapter_vol == ADAPTER_BPP_QC_VOL && di->is_compatible_hwid) { + schedule_delayed_work(&di->bpp_e5_tx_work, msecs_to_jiffies(0)); + goto out; + } + + /* adapter:qc2; tx:F1_27W; + * vout/psns is setted in delayed work + */ + if (di->tx_charger_type == ADAPTER_QC2 && di->is_f1_tx) { + schedule_delayed_work(&di->qc2_f1_tx_work, msecs_to_jiffies(0)); + goto out; + } + + /* adapter:qc3_epp; tx:F1_27W; + * vout/psns is setted in delayed work + */ + if (di->is_epp_qc3) { + schedule_delayed_work(&di->qc3_epp_work, msecs_to_jiffies(0)); + goto out; + } + + if ((adapter_vol == ADAPTER_EPP_QC3_VOL) && (di->epp)) { + dev_info(di->dev, "standard epp logic\n"); + + if (adapter_vol > 0 && adapter_vol != di->last_vin) { + idtp922x_set_adap_vol(di, adapter_vol); + di->last_vin = adapter_vol; + msleep(200); + } + + if ((icl_curr > 0) && (icl_curr != di->last_icl)) { + idtp922x_set_pmi_icl(di, icl_curr); + di->last_icl = icl_curr; + msleep(100); + } + + goto out; + } + + if ((adapter_vol == ADAPTER_DEFAULT_VOL) && (!di->epp)) { + dev_info(di->dev, "standard bpp logic\n"); + + if (adapter_vol > 0 && adapter_vol != di->last_vin) { + idtp922x_set_adap_vol(di, adapter_vol); + di->last_vin = adapter_vol; + msleep(200); + } + + if ((icl_curr > 0) && (icl_curr != di->last_icl)) { + idtp922x_set_pmi_icl(di, icl_curr); + di->last_icl = icl_curr; + msleep(100); + } + + goto out; + } + + if (adapter_vol == ADAPTER_EPP_MI_VOL && di->is_pan_tx) { + schedule_delayed_work(&di->pan_tx_work, msecs_to_jiffies(0)); + goto out; + } + if (adapter_vol == ADAPTER_EPP_MI_VOL && di->is_voice_box_tx) { + dev_info(di->dev, "voice box logic\n"); + schedule_delayed_work(&di->voice_tx_work, msecs_to_jiffies(0)); + goto out; + } + /* MI adapter, change vout only after vswitch success */ + if (adapter_vol == ADAPTER_EPP_MI_VOL && di->vswitch_ok) { + switch (di->status) { + case NORMAL_MODE: + if (soc >= EPP_TAPER_SOC) { + if (di->wireless_psy) { + power_supply_get_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, + &val); + if (!val.intval) { + icl_curr = + idtp9220_get_taper_charging_current( + di); + } + } else { + icl_curr = + idtp9220_get_taper_charging_current( + di); + } + /* close cp, avoid battery OV */ + if (di->wireless_psy) { + val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, + &val); + } + icl_curr = min(icl_curr, MAX_PMIC_ICL_UA); + } + if (soc >= FULL_SOC) { + di->status = TAPER_MODE; + } + break; + case TAPER_MODE: + if (soc == FULL_SOC && + batt_sts == POWER_SUPPLY_STATUS_FULL) + di->status = FULL_MODE; + else if (soc < FULL_SOC - 1) + di->status = NORMAL_MODE; + break; + case FULL_MODE: + dev_info(di->dev, "charge full set Vin 12V\n"); + adapter_vol = EPP_VOL_THRESHOLD; + icl_curr = SCREEN_OFF_FUL_CURRENT; + + if (batt_sts == POWER_SUPPLY_STATUS_CHARGING) { + dev_info(di->dev, + "full mode -> recharge mode\n"); + di->status = RECHG_MODE; + icl_curr = DC_LOW_CURRENT; + } + break; + case RECHG_MODE: + if (batt_sts == POWER_SUPPLY_STATUS_FULL) { + dev_info(di->dev, + "recharge mode -> full mode\n"); + di->status = FULL_MODE; + icl_curr = SCREEN_OFF_FUL_CURRENT; + adapter_vol = EPP_VOL_THRESHOLD; + if (di->wireless_psy) { + wk_val.intval = 0; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + } + + dev_info(di->dev, "recharge mode set icl to 350mA\n"); + adapter_vol = EPP_VOL_THRESHOLD; + icl_curr = DC_LOW_CURRENT; + + if (di->wireless_psy) { + wk_val.intval = 1; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + &wk_val); + } + break; + default: + break; + } + } + + if (!di->enable_ext5v) { + di->enable_ext5v = true; + idtp922x_enable_ext5v(di); + } + if (!di->power_good_flag) + return; + dev_info(di->dev, "%s: ready to set_vin vol\n", __func__); + if (adapter_vol > 0 && adapter_vol != di->last_vin) { + if ((adapter_vol == ADAPTER_EPP_MI_VOL) && + !di->first_rise_flag) { + di->first_rise_flag = true; + idtp922x_set_adap_vol(di, adapter_vol); + di->vswitch_ok = false; + vin_inc = 1; + msleep(110); + dev_info(di->dev, "%s:set adapter_vol %d\n", __func__, + adapter_vol); + } else if ((adapter_vol == ADAPTER_EPP_MI_VOL) && + di->first_rise_flag) { + idtp9220_set_vout(di, adapter_vol); + msleep(110); + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(400)); + dev_info(di->dev, "%s:set vout_vol %d\n", __func__, + adapter_vol); + } else if (adapter_vol == EPP_VOL_THRESHOLD) { + vout = idtp9220_get_vout(di); + while (vout > EPP_VOL_THRESHOLD) { + vout = vout - 1000; + idtp9220_set_vout(di, vout); + msleep(200); + } + idtp9220_set_vout(di, EPP_VOL_THRESHOLD); + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + } + vout_change = true; + di->last_vin = adapter_vol; + } + + if ((icl_curr > 0 && icl_curr != di->last_icl) || vout_change) { + di->last_icl = icl_curr; + idtp922x_set_pmi_icl(di, icl_curr); + msleep(100); + } + + dev_info( + di->dev, + "di->status:0x%x,adapter_vol=%d,icl_curr=%d,last_vin=%d,last_icl=%d\n", + di->status, adapter_vol, icl_curr, di->last_vin, di->last_icl); + + if (!di->vswitch_ok && vin_inc) { + di->adapter_voltage = adapter_vol; + schedule_delayed_work(&di->cmd_check_work, + msecs_to_jiffies(8000)); + } +out: + return; +} + +static void idtp9220_wpc_det_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, wpc_det_work.work); + union power_supply_propval val = { + 0, + }; + int ret = 0; + + ret = idtp9220_get_property_names(di); + if (ret < 0) { + dev_err(di->dev, "get property error: %d\n", ret); + return; + } + /* if power good is low return */ + if (!di->power_good_flag) + return; + + pm_stay_awake(di->dev); + + dev_info(di->dev, "power_good low, wireless detached\n"); + cancel_delayed_work(&di->dc_check_work); + di->power_good_flag = 0; + val.intval = 0; + di->ss = 2; + di->bpp_break = true; + cancel_delayed_work(&di->oob_set_cep_work); + cancel_delayed_work_sync(&di->chg_monitor_work); + cancel_delayed_work_sync(&di->epp_connect_load_work); + cancel_delayed_work_sync(&di->rx_vout_cp_close_work); + cancel_delayed_work_sync(&di->rx_vout_work); + vote(di->fcc_votable, VOICE_LIMIT_FCC_VOTER, false, 0); + vote(di->fcc_votable, VOICE_LIMIT_FCC_1A_VOTER, false, 0); + idtp9220_set_present(di, val.intval); + if (!di->icl_votable) + di->icl_votable = find_votable("dc_icl_votable"); + + if (di->icl_votable) + vote(di->icl_votable, OCP_PROTECTION_VOTER, false, 0); + + idtp922x_set_pmi_icl(di, 0); + + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, + &val); + + if (di->wait_for_reverse_test) { + msleep(2000); + idtp9220_set_reverse_enable(di, true); + dev_err(di->dev, + "[ factory reverse test ] wait for factory reverse charging test, power good low\n"); + alarm_start_relative( + &di->reverse_test_ready_alarm, + ms_to_ktime(REVERSE_TEST_READY_CHECK_DELAY_MS)); + } + schedule_delayed_work(&di->keep_awake_work, msecs_to_jiffies(5000)); + return; +} + +static void idtp9220_fw_download_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, fw_download_work.work); + + u8 fw_app_ver[4] = { 0 }; + union power_supply_propval val = { + 0, + }; + bool crc_ok = false; + int rc = 0; + + dev_info(di->dev, "[idt] enter %s\n", __func__); + + if (di->fw_update) { + dev_info(di->dev, "[idtp9415] [%s] FW Update is on going!\n", + __func__); + return; + } + + power_supply_get_property(di->dc_psy, POWER_SUPPLY_PROP_ONLINE, &val); + + if (!val.intval) { + pm_stay_awake(di->dev); + di->fw_update = true; + idtp9220_set_reverse_gpio(di, true); + msleep(100); + rc = di->bus.read_buf(di, REG_EPRFWVER_ADDR, fw_app_ver, 4); + dev_info(di->dev, "%s: RX_FW version %x.%x.%x.%x\n", __func__, + fw_app_ver[3], fw_app_ver[2], fw_app_ver[1], + fw_app_ver[0]); + + if (!rc) + di->chip_ok = 1; + else + di->chip_ok = 0; + + di->fw_version = fw_app_ver[0]; + if (!program_crc_verify(di)) { + dev_err(di->dev, "update crc verify failed.\n"); + crc_ok = false; + } else { + dev_info(di->dev, "update crc verify success.\n"); + crc_ok = true; + } + + idtp9220_set_reverse_gpio(di, false); + msleep(30); + + if ((fw_app_ver[3] == 0x2 && fw_app_ver[2] == 0x6 && + fw_app_ver[1] == 0x1 && fw_app_ver[0] >= FW_VERSION) && + (crc_ok)) { + dev_info(di->dev, "FW: 0x%x, crc: %d so skip upgrade\n", + fw_app_ver[0], crc_ok); + } else { +#ifndef CONFIG_FACTORY_BUILD + idtp9220_set_reverse_gpio(di, true); + msleep(100); + + dev_info(di->dev, "%s: FW download start\n", __func__); + if (!program_fw(di, 0x0000, idt_firmware, + sizeof(idt_firmware))) { + dev_err(di->dev, "program fw failed.\n"); + } else { + dev_info( + di->dev, + "[idt] %s: program fw %ld bytes done\n", + __func__, sizeof(idt_firmware)); + di->fw_version = FW_VERSION; + } + + idtp9220_set_reverse_gpio(di, false); + msleep(100); + /* start crc verify */ + idtp9220_set_reverse_gpio(di, true); + msleep(100); + + if (!program_crc_verify(di)) + dev_err(di->dev, "crc verify failed.\n"); + else + dev_info(di->dev, "crc verify success.\n"); + idtp9220_set_reverse_gpio(di, false); +#else + dev_info(di->dev, "%s: factory build, don't update\n", + __func__); +#endif + } + di->fw_update = false; + pm_relax(di->dev); + } else + dev_info(di->dev, + "%s: Skip FW download due to wireless charging\n", + __func__); +} + +static void idtp9220_rx_vout_cp_close_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, rx_vout_cp_close_work.work); + int vout = 0; + vout = idtp9220_get_vout(di); + while (vout > CP_CLOSE_VOUT_MV) { + vout = vout - 1000; + if (!di->power_good_flag) + return; + idtp9220_set_vout(di, vout); + msleep(300); + } + if (!di->power_good_flag) + return; + idtp9220_set_vout(di, CP_CLOSE_VOUT_MV); + + if (di->power_good_flag) + di->cp_regulator_done = true; +} +static void idtp9220_keep_awake_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, keep_awake_work.work); + pm_relax(di->dev); +} +static int idtp_get_effective_icl_val(struct idtp9220_device_info *di) +{ + int effective_icl_val = 0; + + if (!di->icl_votable) + di->icl_votable = find_votable("DC_ICL"); + + if (!di->icl_votable) + return -EINVAL; + + effective_icl_val = get_effective_result_locked(di->icl_votable); + pr_info("effective_icl_val: %d\n", effective_icl_val); + return effective_icl_val; +} + +static int idtp_set_effective_icl_val(struct idtp9220_device_info *di, int icl) +{ + int effective_icl_val = 0; + + if (!di->icl_votable) + di->icl_votable = find_votable("DC_ICL"); + + if (!di->icl_votable) + return -EINVAL; + + vote(di->icl_votable, OCP_PROTECTION_VOTER, true, icl); + pr_info("effective_icl_val: %d\n", effective_icl_val); + return 0; +} + +#ifndef CONFIG_FACTORY_BUILD +#define NEW_MAX_POWER_CMD 0x28 +#define RENEGOTIATION_CMD 0x80 +static void idtp9220_renegociation(struct idtp9220_device_info *di) +{ + if (di->tx_charger_type == ADAPTER_XIAOMI_PD_45W || + di->tx_charger_type == ADAPTER_XIAOMI_PD_60W) { + di->bus.write(di, REG_MAX_POWER, NEW_MAX_POWER_CMD); + di->bus.write(di, REG_RX_RESET, RENEGOTIATION_CMD); + } +} +#endif +static void idtp9220_start_to_load(struct idtp9220_device_info *di) +{ + union power_supply_propval val = { + 0, + }; + schedule_delayed_work(&di->rx_vout_work, msecs_to_jiffies(100)); + schedule_delayed_work(&di->chg_monitor_work, msecs_to_jiffies(1000)); + if (di->tx_charger_type == ADAPTER_XIAOMI_PD_40W || + di->tx_charger_type == ADAPTER_XIAOMI_PD_45W || + di->tx_charger_type == ADAPTER_XIAOMI_PD_60W) { + if (di->wireless_psy) { + val.intval = di->tx_charger_type; + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_QUICK_CHARGE_TYPE, &val); + } + msleep(100); + if (di->usb_psy) + power_supply_changed(di->usb_psy); + } + + if (di->wireless_psy) + power_supply_changed(di->wireless_psy); +} + +static void idtp9220_idt_first_boot(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, idt_first_boot.work); + idt_first_flag = true; + if (di->idtp_psy) + power_supply_changed(di->idtp_psy); +} + +static int idt_trx_get_ble_mac(struct idtp9220_device_info *di) +{ + int rc = 0, i = 0; + u8 mac_buf[MAC_LEN] = { 0 }; + + rc = di->bus.read_buf(di, REG_MAC_ADDR, mac_buf, MAC_LEN); + if (rc < 0) { + dev_err(di->dev, "trx read mac addr error: %d\n", rc); + return rc; + } + + dev_info(di->dev, "mac addr of pen: 0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n", + mac_buf[0], mac_buf[1], mac_buf[2], mac_buf[3], mac_buf[4], + mac_buf[5]); + + for (i = 0; i < MAC_LEN; i++) + di->pen_mac_data[i] = mac_buf[i]; + + idtp922x_sent_pen_mac(di); + + return rc; +} + +static void idtp9220_hall3_irq_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, hall3_irq_work.work); + if (di->hall3_online) + idtp9220_set_reverse_enable(di, true); + else if (!di->hall4_online) { + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 2; + schedule_delayed_work(&di->reverse_sent_state_work, 0); + } else { + dev_info( + di->dev, + "[hall3] hall4 online, don't disable reverse charge\n"); + } + + return; +} + +static void idtp9220_hall4_irq_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, hall4_irq_work.work); + + if (di->hall4_online) + idtp9220_set_reverse_enable(di, true); + else if (!di->hall3_online) { + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 2; + schedule_delayed_work(&di->reverse_sent_state_work, 0); + } else { + dev_info( + di->dev, + "[hall4] hall3 online, don't disable reverse charge\n"); + } + + return; +} + +#define OCP_LOWER_ICL_SETP_UA 500000; +static void idtp9220_irq_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = + container_of(work, struct idtp9220_device_info, irq_work.work); + union power_supply_propval val = { + 0, + }; + u8 int_buf[4] = { 0 }; + u32 int_val = 0; + int rc = 0; + u8 recive_data[5] = { 0 }; + static int retry; + static int retry_id; + static int retry_count; +#ifndef CONFIG_FACTORY_BUILD + static int renego_retry_count; +#endif + int tx_vin = 0; + int irq_level; + int i; + u8 clr_buf[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; + int lower_icl = 0; + if (gpio_is_valid(di->dt_props.irq_gpio)) + irq_level = gpio_get_value(di->dt_props.irq_gpio); + else { + dev_err(di->dev, "%s: irq gpio not provided\n", __func__); + irq_level = -1; + pm_relax(di->dev); + return; + } + if (irq_level) { + dev_info(di->dev, "irq is high level, ignore%d\n", irq_level); + pm_relax(di->dev); + return; + } + + rc = di->bus.read_buf(di, REG_SYS_INT, int_buf, 4); + if (rc < 0) { + dev_err(di->dev, "[idt]read int state error: %d\n", rc); + goto out; + } + + if (di->is_reverse_mode || di->is_boost_mode) { + reverse_clrInt(di, int_buf, 4); + int_val = int_buf[0] | (int_buf[1] << 8) | (int_buf[2] << 16) | + (int_buf[3] << 24); + dev_info(di->dev, "[idt] TRX int: 0x%08x\n", int_val); + /* add for confirm if irq is cleared start */ + msleep(5); + if (reverse_need_irq_cleared(di, int_val)) { + reverse_clrInt(di, clr_buf, 4); + msleep(5); + } + /* add for confirm if irq is cleared end */ + if (int_val & INT_EPT_TYPE) { + schedule_delayed_work(&di->reverse_ept_type_work, 0); + goto reverse_out; + } + + if (int_val & INT_GET_DPING) { + dev_info( + di->dev, + "[idt] TRX get dping and disable reverse charging \n"); + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 2; + schedule_delayed_work(&di->reverse_sent_state_work, 0); + goto reverse_out; + } + + if (int_val & INT_START_DPING) { + alarm_start_relative( + &di->reverse_chg_alarm, + ms_to_ktime(REVERSE_CHG_CHECK_DELAY_MS)); + rc = alarm_cancel(&di->reverse_dping_alarm); + if (rc < 0) + dev_err(di->dev, + "Couldn't cancel reverse_dping_alarm\n"); + pm_relax(di->dev); + } + if (int_val & INT_GET_CFG) { + //cancel_delayed_work(&di->reverse_chg_state_work); + dev_info(di->dev, "TRX get cfg, cancel 80s alarm\n"); + rc = alarm_cancel(&di->reverse_chg_alarm); + if (rc < 0) + dev_err(di->dev, + "Couldn't cancel reverse_dping_alarm\n"); + pm_stay_awake(di->dev); + schedule_delayed_work(&di->reverse_sent_state_work, 0); + di->bus.write(di, REG_TX_CMD, TX_EN); + msleep(50); + //start reverse chg infor work + cancel_delayed_work_sync(&di->reverse_chg_work); + msleep(10); + schedule_delayed_work(&di->reverse_chg_work, 0); + /* set reverse charging state to started */ + if (di->is_reverse_mode || di->is_boost_mode) { + di->is_reverse_chg = 4; + schedule_delayed_work( + &di->reverse_sent_state_work, 100); + } + } + if (int_val & INT_GET_SS) { + dev_info(di->dev, "TRX get ss\n"); + } + if (int_val & INT_GET_ID) { + dev_info(di->dev, "TRX get id\n"); + } + if (int_val & INT_INIT_TX) { + dev_info(di->dev, "[idt] TRX reset done\n"); + } + if (int_val & INT_GET_BLE_ADDR) { + dev_info(di->dev, "[idt] TRX get ble mac\n"); + idt_trx_get_ble_mac(di); + } + if (int_val & INT_GET_PPP) { + idtp922x_receivePkt2(di, recive_data); + dev_err(di->dev, + "[ factory reverse test ] receive dates: 0x%02x, 0x%02x\n", + recive_data[0], recive_data[1]); + if (recive_data[0] == 0x18 && recive_data[1] == 0x31) { + // done + dev_err(di->dev, + "[ factory reverse test ] receiver reverse test done\n"); + idtp9220_set_reverse_enable(di, false); + di->wait_for_reverse_test = false; + } else if (recive_data[0] == 0x18 && + recive_data[1] == 0x3D) { + //ready + dev_err(di->dev, + "[ factory reverse test ] receiver reverse test ready, cancel timer\n"); + alarm_cancel(&di->reverse_test_ready_alarm); + } + } +reverse_out: + goto out; + } + int_val = int_buf[0] | (int_buf[1] << 8) | (int_buf[2] << 16) | + (int_buf[3] << 24); + dev_info(di->dev, "[idt] int: 0x%08x\n", int_val); + + if (int_val & INT_MODE_CHANGE || int_val & INT_VOUT_OFF) { + if (di->power_good_flag) { + cancel_delayed_work_sync(&di->rx_ready_check_work); + schedule_delayed_work(&di->wpc_det_work, + msecs_to_jiffies(0)); + } + + idtp922x_clrInt(di, int_buf, 4); + msleep(5); + if (need_irq_cleared(di)) { + idtp922x_clrInt(di, clr_buf, 4); + msleep(5); + } + goto out; + } + + if (int_val & INT_OV_CURR) { + lower_icl = + idtp_get_effective_icl_val(di) - OCP_LOWER_ICL_SETP_UA; + + if (lower_icl > 0) + idtp_set_effective_icl_val(di, lower_icl); + + /* wait for icl works */ + msleep(1000); + idtp922x_clrInt(di, int_buf, 4); + msleep(5); + if (need_irq_cleared(di)) { + idtp922x_clrInt(di, clr_buf, 4); + msleep(5); + } + goto out; + } + + /* clear int and enable irq immediately when read int register */ + idtp922x_clrInt(di, int_buf, 4); + msleep(5); + if (need_irq_cleared(di)) { + idtp922x_clrInt(di, clr_buf, 4); + msleep(5); + } + + if (int_val & INT_RXREADY) { + cancel_delayed_work_sync(&di->rx_ready_check_work); + if (di->power_good_flag) { + schedule_delayed_work(&di->wpc_det_work, + msecs_to_jiffies(0)); + } + schedule_delayed_work(&di->initial_tx_work, + msecs_to_jiffies(100)); + di->power_good_flag = 1; + val.intval = 1; + if (!di->wireless_psy) + di->wireless_psy = power_supply_get_by_name("wireless"); + if (di->wireless_psy) + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, &val); + schedule_delayed_work(&di->rx_ready_check_work, + msecs_to_jiffies(100)); + } + if (int_val & INT_VOUT_ON) { + if (!di->power_good_flag) { + cancel_delayed_work_sync(&di->rx_ready_check_work); + if (di->power_good_flag) { + schedule_delayed_work(&di->wpc_det_work, + msecs_to_jiffies(0)); + } + schedule_delayed_work(&di->initial_tx_work, + msecs_to_jiffies(100)); + di->power_good_flag = 1; + val.intval = 1; + if (!di->wireless_psy) + di->wireless_psy = + power_supply_get_by_name("wireless"); + if (di->wireless_psy) + power_supply_set_property( + di->wireless_psy, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, + &val); + schedule_delayed_work(&di->rx_ready_check_work, + msecs_to_jiffies(100)); + } + di->vout_on = true; + di->epp = idtp9220_get_power_profile(di); + if (di->epp) { + di->power_max = idtp9220_get_power_max(di); + schedule_delayed_work(&di->epp_connect_load_work, + msecs_to_jiffies(200)); + } else + schedule_delayed_work(&di->bpp_connect_load_work, + msecs_to_jiffies(200)); + if (int_val & INT_IDAUTH_SUCESS) + idtp9220_send_device_auth(di); + goto out; + } + + if (int_val & INT_VSWITCH_SUCESS) { + di->vswitch_ok = true; + schedule_delayed_work(&di->load_fod_param_work, + msecs_to_jiffies(500)); + schedule_delayed_work(&di->vout_regulator_work, + msecs_to_jiffies(50)); + cancel_delayed_work(&di->cmd_check_work); + if (di->is_ble_tx) + idtp922x_request_low_addr(di); + goto out; + } + + if (int_val & INT_IDAUTH_SUCESS) { + idtp9220_send_device_auth(di); + //idtp922x_request_adapter(di); + goto out; + } + + if (int_val & INT_AUTH_SUCESS) { + idtp922x_request_uuid(di, di->epp); + goto out; + } + /* + idtp9220_get_signal_strength(di); + di->tx_charger_type = ADAPTER_QC3; + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(0)); + goto out; + */ + + if ((int_val & INT_IDAUTH_FAIL) || (int_val & INT_AUTH_FAIL) || + int_val == 0) { + if (((int_val & INT_AUTH_FAIL) || (int_val == 0)) && + (retry < 5)) { + idtp9220_send_device_auth(di); + retry++; + dev_info(di->dev, "[idtp] dev auth failed retry %d\n", + retry); + goto out; + } else if ((int_val & INT_IDAUTH_FAIL) && retry_id < 5) { + idtp9220_retry_id_auth(di); + retry_id++; + dev_info(di->dev, "[idtp] id auth failed retry %d\n", + retry); + goto out; + } else { + retry = 0; + retry_id = 0; + } + di->tx_charger_type = ADAPTER_AUTH_FAILED; + dev_info(di->dev, "[idtp] auth failed tx charger type set %d\n", + di->tx_charger_type); + + schedule_delayed_work(&di->rx_vout_work, msecs_to_jiffies(0)); + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(0)); + goto out; + } else + retry = 0; + /* + if (int_val & INT_IDAUTH_FAIL) { + idtp922x_request_adapter(di); + goto out; + } + */ + + if (int_val & INT_SEND_TIMEOUT) { + if (retry_count < 3) { + dev_info(di->dev, "timeout retry %d\n", retry_count); + idtp922x_retry_cmd(di); + retry_count++; + goto out; + } else { + dev_err(di->dev, "%s: retry failed\n", __func__); + if (!di->tx_charger_type) + di->tx_charger_type = ADAPTER_AUTH_FAILED; + schedule_delayed_work(&di->rx_vout_work, + msecs_to_jiffies(0)); + schedule_delayed_work(&di->chg_monitor_work, + msecs_to_jiffies(0)); + retry_count = 0; + goto out; + } + } else { + retry_count = 0; + } +#ifndef CONFIG_FACTORY_BUILD + if (int_val & RENEG_SUCCESS) { + if (di->tx_charger_type == ADAPTER_XIAOMI_PD_45W || + di->tx_charger_type == ADAPTER_XIAOMI_PD_60W) { + dev_err(di->dev, + "%s: max power renegociation success\n", + __func__); + idtp9220_start_to_load(di); + renego_retry_count = 0; + } + } + + if (int_val & RENEG_FAIL) { + if (di->tx_charger_type == ADAPTER_XIAOMI_PD_45W || + di->tx_charger_type == ADAPTER_XIAOMI_PD_60W) { + if (renego_retry_count < 3) { + idtp9220_renegociation(di); + dev_err(di->dev, "%s: retry renegociation\n", + __func__); + renego_retry_count++; + } else { + dev_err(di->dev, + "%s: retry limit exceed, set adapter type to 40W\n", + __func__); + di->tx_charger_type = ADAPTER_XIAOMI_PD_40W; + idtp9220_start_to_load(di); + renego_retry_count = 0; + } + } + } +#endif + + if (int_val & INT_TX_DATA_RECV) { + idtp922x_receivePkt(di, recive_data); + dev_info(di->dev, "[idt] cmd: %x\n", recive_data[0]); + + switch (recive_data[0]) { + case BC_TX_HWID: + dev_info( + di->dev, + "[idt] TX chip_vendor:0x%x, module:0x%x, hw:0x%x and power:0x%x\n", + recive_data[4], recive_data[2], recive_data[3], + recive_data[1]); + if (recive_data[4] == 0x07 && recive_data[2] == 0x1 && + recive_data[3] == 0x4 && + ((recive_data[1] == 0x9) || + (recive_data[1] == 0x1))) { + di->is_ble_tx = 1; + } else if (recive_data[4] == 0x01 && + recive_data[2] == 0x2 && + recive_data[3] == 0x8 && + recive_data[1] == 0x6) { + di->is_car_tx = 1; + } else if (recive_data[4] == 0x07 && + recive_data[2] == 0x8 && + recive_data[3] == 0x6 && + recive_data[1] == 0x9) { + di->is_voice_box_tx = 1; + di->is_ble_tx = 1; + } else if (recive_data[4] == 0x06 && + recive_data[2] == 0x1 && + recive_data[3] == 0x5 && + recive_data[1] == 0x9) { + di->is_pan_tx = 1; + } else if (recive_data[4] == 0x0B && + recive_data[2] == 0x1 && + recive_data[3] == 0x1 && + recive_data[1] == 0x9) { + di->is_ble_tx = 1; + } else if (recive_data[4] == 0x01 && + recive_data[2] == 0x1 && + recive_data[3] == 0x1 && + recive_data[1] == 0x6) { + di->is_f1_tx = 1; + } else if (recive_data[4] == 0x01 && + recive_data[2] == 0x3 && + recive_data[3] == 0x8 && + recive_data[1] == 0x7) { + di->is_zm_mobil_tx = 1; + } else if (recive_data[4] == 0x08 && + recive_data[2] == 0x8 && + recive_data[3] == 0x1 && + recive_data[1] == 0x9) { + di->is_zm_20w_tx = 1; + } +#ifdef CONFIG_FACTORY_BUILD + di->is_ble_tx = 0; +#endif + idtp922x_request_adapter(di); + break; + case BC_TX_COMPATIBLE_HWID: + dev_info(di->dev, "[idt] TX hwid: 0x%x 0x%x\n", + recive_data[1], recive_data[2]); + if (recive_data[1] == 0x12 && recive_data[2]) + di->is_compatible_hwid = 1; + if (recive_data[1] == 0x16 && recive_data[2] == 0x11) + di->is_f1_tx = 1; + idtp922x_request_adapter(di); + break; + case BC_ADAPTER_TYPE: + dev_info(di->dev, "[idt]adapter type: %d\n", + recive_data[1]); + + if (di->is_car_tx && + (recive_data[1] == ADAPTER_XIAOMI_QC3)) + di->tx_charger_type = ADAPTER_ZIMI_CAR_POWER; + else if (di->is_voice_box_tx) + di->tx_charger_type = ADAPTER_VOICE_BOX; + else + di->tx_charger_type = recive_data[1]; + + if (di->tx_charger_type == ADAPTER_XIAOMI_PD_40W && + di->is_zm_mobil_tx) { + //di->tx_charger_type = ADAPTER_VOICE_BOX; + di->is_voice_box_tx = 1; + } + /* + if(!di->epp && (di->tx_charger_type == ADAPTER_QC3 || + di->tx_charger_type == ADAPTER_QC2)) { + idtp922x_set_adap_vol(di, ADAPTER_BPP_VOL); + dev_info(di->dev, "[idt]bpp mode set 5v first\n"); + } + */ +#ifdef CONFIG_FACTORY_BUILD + idtp9220_start_to_load(di); +#else + if (di->tx_charger_type == ADAPTER_XIAOMI_PD_45W || + di->tx_charger_type == ADAPTER_XIAOMI_PD_60W) { + renego_retry_count = 0; + idtp9220_renegociation(di); + } else { + idtp9220_start_to_load(di); + } +#endif + break; + case BC_READ_Vin: + tx_vin = recive_data[1] | (recive_data[2] << 8); + if (!di->power_off_mode) { + if (di->epp) + idtp9220_set_vout(di, + di->adapter_voltage); + else + idtp9220_set_vout(di, + ADAPTER_BPP_QC_VOL); + } + dev_info(di->dev, "[idt] tx vin : %d\n", tx_vin); + break; + case BC_READ_VOUT: + schedule_delayed_work(&di->get_vout_work, + msecs_to_jiffies(0)); + break; + case BC_READ_IOUT: + schedule_delayed_work(&di->get_iout_work, + msecs_to_jiffies(0)); + break; + case BC_RX_CHIP_VERSION: + dev_info(di->dev, "[idt]Detect RX Chip version\n"); + idtp922x_sent_chip_version(di); + break; + case BC_RX_FW_VERSION: + dev_info(di->dev, "[idt]Detect RX FW version\n"); + idtp922x_sent_fw_version(di); + break; + case BC_RX_ID_AUTH: + dev_info(di->dev, + "[idt] ID Auth retry success: 0x%x, 0x%x\n", + recive_data[1], recive_data[2]); + idtp9220_send_device_auth(di); + break; + case CMD_GET_BLEMAC_2_0: + dev_info( + di->dev, + "[idt] get mac low 3 bytes: 0x%x, 0x%x, 0x%x\n", + recive_data[1], recive_data[2], recive_data[3]); + for (i = 0; i < 3; i++) { + di->mac_data[i] = recive_data[i + 1]; + } + idtp922x_request_high_addr(di); + break; + case CMD_GET_BLEMAC_5_3: + dev_info( + di->dev, + "[idt] get mac high 3 bytes: 0x%x, 0x%x, 0x%x\n", + recive_data[1], recive_data[2], recive_data[3]); + for (i = 0; i < 3; i++) { + di->mac_data[i + 3] = recive_data[i + 1]; + } + idtp922x_sent_tx_mac(di); + break; + case CMD_FACOTRY_REVERSE: + dev_info( + di->dev, + "[ factory reverse test ] send factory reverse cnf\n"); + idtp922x_sent_reverse_cnf(di); + di->wait_for_reverse_test = true; + break; + default: + dev_info(di->dev, "[idt] unsupport cmd: %x\n", + recive_data[0]); + break; + } + } + if (int_val & INT_RPP_READ) + rc = idtp9220_set_rpp(di); + +out: + pm_relax(di->dev); + return; +} + +static irqreturn_t idtp9220_wpc_det_irq_handler(int irq, void *dev_id) +{ + //struct idtp9220_device_info *di = dev_id; + + //pm_stay_awake(di->dev); + printk("idtp9220_wpc_det_irq_handler\n"); + //schedule_delayed_work(&di->wpc_det_work, msecs_to_jiffies(0)); + + return IRQ_HANDLED; +} + +static int idtp9220_ocp_disable_vote_cb(struct votable *votable, void *data, + int disable, const char *client) +{ + struct idtp9220_device_info *di = (struct idtp9220_device_info *)data; + di->bus.write(di, REG_OCP_CONFIG, !disable); + dev_err(di->dev, "idtp9220_ocp_disable_vote_cb enable:%d\n", !disable); + return 0; +} + +static irqreturn_t idtp9220_irq_handler(int irq, void *dev_id) +{ + struct idtp9220_device_info *di = dev_id; + pm_stay_awake(di->dev); + printk("idtp9220_irq_handler\n"); + schedule_delayed_work(&di->irq_work, msecs_to_jiffies(10)); + return IRQ_HANDLED; +} + +static irqreturn_t idtp9220_hall3_irq_handler(int irq, void *dev_id) +{ + struct idtp9220_device_info *di = dev_id; + + if (gpio_is_valid(di->dt_props.hall3_gpio)) { + if (gpio_get_value(di->dt_props.hall3_gpio)) { + dev_info(di->dev, + "idtp9220_hall3_irq_handler: pen detach\n"); + di->hall3_online = 0; + if (di->hall4_online) { + dev_info( + di->dev, + "idtp9220_hall3_irq_handler: hall4 online, return\n"); + return IRQ_HANDLED; + } + schedule_delayed_work(&di->hall3_irq_work, + msecs_to_jiffies(0)); + return IRQ_HANDLED; + } else { + dev_info(di->dev, + "idtp9220_hall3_irq_handler: pen attach\n"); + di->hall3_online = 1; + } + } + + if (di->hall4_online) { + dev_info(di->dev, + "[hall3] reverse charging already running, return\n"); + return IRQ_HANDLED; + } else + schedule_delayed_work(&di->hall3_irq_work, + msecs_to_jiffies(10)); + + return IRQ_HANDLED; +} + +static irqreturn_t idtp9220_hall4_irq_handler(int irq, void *dev_id) +{ + struct idtp9220_device_info *di = dev_id; + + if (gpio_is_valid(di->dt_props.hall4_gpio)) { + if (gpio_get_value(di->dt_props.hall4_gpio)) { + dev_info(di->dev, + "idtp9220_hall4_irq_handler: pen detach\n"); + di->hall4_online = 0; + if (di->hall3_online) { + dev_info( + di->dev, + "idtp9220_hall4_irq_handler: hall3 online, return\n"); + return IRQ_HANDLED; + } + schedule_delayed_work(&di->hall4_irq_work, + msecs_to_jiffies(0)); + return IRQ_HANDLED; + } else { + dev_info(di->dev, + "idtp9220_hall4_irq_handler: pen attach\n"); + di->hall4_online = 1; + } + } + + if (di->hall3_online) { + dev_info(di->dev, + "[hall4] reverse charging already running, return\n"); + return IRQ_HANDLED; + } else + schedule_delayed_work(&di->hall4_irq_work, + msecs_to_jiffies(10)); + + return IRQ_HANDLED; +} + +static int idtp9220_irq_request(struct idtp9220_device_info *di) +{ + int ret = 0; + + if (!di->irq) { + dev_err(di->dev, "%s: irq is wrong\n", __func__); + return -EINVAL; + } + + ret = request_irq(di->irq, idtp9220_irq_handler, IRQF_TRIGGER_FALLING, + di->name, di); + if (ret) { + dev_err(di->dev, "%s: request_irq failed\n", __func__); + return ret; + } + + ret = enable_irq_wake(di->irq); + if (ret) { + dev_err(di->dev, "%s: enable_irq_wake failed\n", __func__); + return ret; + } + + if (!di->hall3_irq) { + dev_err(di->dev, "%s: hall3 irq is wrong\n", __func__); + return -EINVAL; + } + + ret = request_irq(di->hall3_irq, idtp9220_hall3_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "hall3_irq", di); + if (ret) { + dev_err(di->dev, "%s: request hall3 irq failed\n", __func__); + return ret; + } + + ret = enable_irq_wake(di->hall3_irq); + if (ret) { + dev_err(di->dev, "%s: enable hall3 irq wake failed\n", + __func__); + return ret; + } + + if (!di->hall4_irq) { + dev_err(di->dev, "%s: hall4 irq is wrong\n", __func__); + return -EINVAL; + } + + ret = request_irq(di->hall4_irq, idtp9220_hall4_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "hall4_irq", di); + if (ret) { + dev_err(di->dev, "%s: request hall4 irq failed\n", __func__); + return ret; + } + + ret = enable_irq_wake(di->hall4_irq); + if (ret) { + dev_err(di->dev, "%s: enable hall4 irq wake failed\n", + __func__); + return ret; + } + + if (!di->wpc_irq) { + dev_err(di->dev, "%s: wpc irq is wrong\n", __func__); + return -EINVAL; + } + + ret = request_irq(di->wpc_irq, idtp9220_wpc_det_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "wpc_det", + di); + if (ret) { + dev_err(di->dev, "%s: wpc request_irq failed\n", __func__); + return ret; + } + + ret = enable_irq_wake(di->wpc_irq); + if (ret) { + dev_err(di->dev, "%s: enable_irq_wake failed\n", __func__); + return ret; + } + + return 0; +} + +static struct regmap_config i2c_idtp9220_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0xFFFF, +}; + +/* + static int idtp9220_get_version(struct idtp9220_device_info *di) + { + int id_val = 0; + u8 chip_id[2] = {0}; + + di->bus.read_buf(di, REG_CHIP_ID_L, chip_id, 2); + id_val = (chip_id[1] << 8) | chip_id[0]; + + return id_val; + } + */ + +static u8 oob_check_sum(u8 *buf, u32 size) +{ + u8 chksum = 0; + while (size--) { + chksum ^= *buf++; + } + + return chksum; +} + +static int idtp9220_set_ept(struct idtp9220_device_info *di) +{ + union power_supply_propval val = { + 0, + }; + int ept = 0; + u8 ept_raw = 0x0b; + u8 header[2] = { 0 }; + u8 chksum[4] = { 0 }; + int rc = 0; + + header[1] = 0x02; //add the ept header + + chksum[0] = header[1]; + chksum[1] = ept_raw; + header[0] = oob_check_sum(chksum, 2); + ept = header[0] | ept_raw << 8 | (header[1] << 16); + val.int64val = ept; + + if (di->wireless_psy) { + mutex_lock(&di->sysfs_op_lock); + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_RX_CEP, &val); + mutex_unlock(&di->sysfs_op_lock); + } else { + dev_err(di->dev, "BLE EPT set error:\n"); + rc = -EINVAL; + } + + dev_info(di->dev, "Header: 0x%x, ept_raw: 0x%x, checksum: 0x%x\n", + header[1], ept_raw, header[0]); + + return rc; +} + +static int idtp9220_set_rpp(struct idtp9220_device_info *di) +{ + int64_t rpp = 0; + int64_t header_ul = 0; + u8 rpp_raw[2] = { 0 }; + u8 header[2] = { 0 }; + u8 chksum[4] = { 0 }; + union power_supply_propval val = { + 0, + }; + int rc = 0; + + header[1] = 0x31; //add the rpp header + di->bus.read_buf(di, REG_RPP, rpp_raw, 2); + + chksum[0] = header[1]; + chksum[1] = rpp_raw[0]; + chksum[2] = rpp_raw[1]; + header[0] = oob_check_sum(chksum, 3); + + dev_info(di->dev, + "header: 0x%x, RPP_raw: 0x%x, 0x%x, checksum: 0x%x\n", + header[1], rpp_raw[1], rpp_raw[0], header[0]); + rpp = header[0] | (rpp_raw[0] << 8) | (rpp_raw[1] << 16); + header_ul = header[1]; + header_ul <<= 32; + header_ul |= rpp; + val.int64val = header_ul; + + if (di->wireless_psy) { + mutex_lock(&di->sysfs_op_lock); + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_RX_CR, &val); + mutex_unlock(&di->sysfs_op_lock); + } else { + dev_err(di->dev, "BLE RPP set error:\n"); + rc = -EINVAL; + } + return rc; +} + +static int idtp9220_set_cep(struct idtp9220_device_info *di) +{ + int cep = 0; + u8 cep_raw = 0; + u8 header[2] = { 0 }; + u8 chksum[4] = { 0 }; + union power_supply_propval val = { + 0, + }; + int rc = 0; + + header[1] = 0x03; //add the rpp header + di->bus.read(di, REG_CEP, &cep_raw); + + chksum[0] = header[1]; + chksum[1] = cep_raw; + header[0] = oob_check_sum(chksum, 2); + + dev_info(di->dev, "Header: 0x%x, CEP_raw: 0x%x, checksum: 0x%x\n", + header[1], cep_raw, header[0]); + cep = header[0] | cep_raw << 8 | (header[1] << 16); + val.int64val = cep; + if (di->wireless_psy) { + mutex_lock(&di->sysfs_op_lock); + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_RX_CEP, &val); + mutex_unlock(&di->sysfs_op_lock); + } else { + dev_err(di->dev, "BLE CEP set error:\n"); + rc = -EINVAL; + } + return rc; +} + +static void idtp_oob_set_cep_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, oob_set_cep_work.work); + int rc; + u8 ble_ok; + + di->bus.read(di, REG_BLE_FLAG, &ble_ok); + if (ble_ok & BIT(0)) + rc = idtp9220_set_cep(di); + + schedule_delayed_work(&di->oob_set_cep_work, 1 * HZ); + return; +} + +static void idt_get_reverse_vout(struct idtp9220_device_info *di) +{ + u8 vout_l, vout_h; + int vout = 0; + + if (!di) + return; + + di->bus.read(di, REG_REVERSE_VIN_LOW, &vout_l); + di->bus.read(di, REG_REVERSE_VIN_HIGH, &vout_h); + vout = vout_l | (vout_h << 8); + dev_info(di->dev, "[reverse] vout is %d\n", vout); + di->reverse_vout = vout; + return; +} + +static void idt_get_reverse_soc(struct idtp9220_device_info *di) +{ + u8 soc = 0; + + if (!di) + return; + + di->bus.read(di, REG_CHG_STATUS, &soc); + if ((soc < 0) || (soc > 0x64)) { + if (soc == 0xFF) { + dev_info(di->dev, "[reverse] soc is default 0xFF\n"); + di->reverse_pen_soc = 0xFF; + } else { + dev_info(di->dev, "[reverse] soc illegal: %d\n", soc); + return; + } + } + + dev_info(di->dev, "[reverse] soc is %d\n", soc); + di->reverse_pen_soc = soc; + + if ((di->reverse_pen_soc == 100) && (pen_soc_count < SOC_100_RETRY)) { + dev_info(di->dev, "[reverse] soc is 100 count: %d\n", + pen_soc_count); + pen_soc_count++; + } else { + pen_soc_count = 0; + } + + if (pen_soc_count == SOC_100_RETRY) { + dev_info( + di->dev, + "[reverse] soc is 100 exceed 6 times, disable reverse chg!\n"); + idtp9220_set_reverse_enable(di, false); + di->is_reverse_mode = 0; + di->is_reverse_chg = 2; + pen_soc_count = 0; + schedule_delayed_work(&di->reverse_sent_state_work, 0); + } + + return; +} + +static void idt_get_reverse_iin(struct idtp9220_device_info *di) +{ + u8 iin_l, iin_h; + int iin = 0; + + if (!di) + return; + + di->bus.read(di, REG_REVERSE_IIN_LOW, &iin_l); + di->bus.read(di, REG_REVERSE_IIN_HIGH, &iin_h); + iin = iin_l | (iin_h << 8); + dev_info(di->dev, "[reverse] iin is %d\n", iin); + di->reverse_iout = iin; + return; +} + +static void idt_get_reverse_temp(struct idtp9220_device_info *di) +{ + u8 temp = 0; + + if (!di) + return; + + di->bus.read(di, REG_REVERSE_TEMP, &temp); + dev_info(di->dev, "[reverse] temp is %d\n", temp); + return; +} + +static void idt_reverse_chg_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, reverse_chg_work.work); + + if (di->is_reverse_mode || di->is_boost_mode) { + idt_get_reverse_vout(di); + idt_get_reverse_iin(di); + idt_get_reverse_temp(di); + idt_get_reverse_soc(di); + } else { + dev_info(di->dev, "reverse chg closed, return\n"); + di->reverse_pen_soc = 255; + di->reverse_vout = 0; + di->reverse_iout = 0; + return; + } + + if (di->reverse_pen_soc == 255) + schedule_delayed_work(&di->reverse_chg_work, 100); + else + schedule_delayed_work(&di->reverse_chg_work, 10 * HZ); + return; +} + +static void idtp_oob_set_ept_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, oob_set_ept_work.work); + + idtp9220_set_ept(di); + + return; +} + +static void idtp_oob_clean_work(struct work_struct *work) +{ + union power_supply_propval val = { + 0, + }; + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, oob_clean_work.work); + memset(di->mac_data, 0x0, sizeof(di->mac_data)); + idtp922x_sent_tx_mac(di); + if (di->wireless_psy) { + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_RX_CR, &val); + power_supply_set_property(di->wireless_psy, + POWER_SUPPLY_PROP_RX_CEP, &val); + } + return; +} + +#define WPC_MODE_BPP 0x1 +#define WPC_MODE_EPP 0x9 + +static void idtp_rx_ready_check_work(struct work_struct *work) +{ + int rx_dead = 0; + u8 mode; + u8 buffer[2] = { 0, 0 }; + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, rx_ready_check_work.work); + rx_dead = di->bus.read(di, REG_WPC_MODE, &mode); + di->bus.read_buf(di, 0x2c, buffer, 2); + if (rx_dead) { + msleep(10); + rx_dead = di->bus.read(di, REG_WPC_MODE, &mode); + di->bus.read_buf(di, 0x2c, buffer, 2); + } + dev_info(di->dev, "rx status: %d mod:0x%x 2C_RISTER 0x%x 0x%x\n", + rx_dead, mode, buffer[0], buffer[1]); + if (rx_dead || (mode != WPC_MODE_BPP && mode != WPC_MODE_EPP)) { + dev_err(di->dev, "rx not respond, power good low\n"); + if (di->power_good_flag) { + schedule_delayed_work(&di->wpc_det_work, + msecs_to_jiffies(0)); + } + } else { + schedule_delayed_work(&di->rx_ready_check_work, + msecs_to_jiffies(500)); + } + return; +} +static int idtp9220_get_temperature(struct idtp9220_device_info *di, u8 *temp) +{ + int rc = 0; + rc = di->bus.read(di, REG_TEMPTER, temp); + return rc; +} + +static void idtp9220_power_off(struct idtp9220_device_info *di) +{ + dev_err(di->dev, "bbc or smb report power off, PG:%d\n", + di->power_good_flag); + if (di->power_good_flag && di->vout_on) { + schedule_delayed_work(&di->wpc_det_work, msecs_to_jiffies(0)); + } +} + +int idtp_op_ble_flag(int en) +{ + int rc; + if (!g_di) + return -EINVAL; + + dev_info(g_di->dev, "set ble flag: %d\n", en); + + if (en) { + rc = g_di->bus.mask_write(g_di, REG_BLE_FLAG, BIT(0), BIT(0)); + schedule_delayed_work(&g_di->oob_set_cep_work, 0); + } else { + rc = g_di->bus.mask_write(g_di, REG_BLE_FLAG, BIT(0), 0); + cancel_delayed_work_sync(&g_di->oob_set_cep_work); + } + + return rc; +} + +static int rx_set_otg_state(struct idtp9220_device_info *di, int plugin) +{ + u8 mode; + di->otg_insert = plugin; + dev_info(di->dev, "[otg]set otg state: %d\n", plugin); + + if (!plugin || !di->is_reverse_mode) + return 0; + + di->bus.read(di, REG_WROK_MODE, &mode); + if (mode & BIT(2)) { + dev_info(di->dev, "[otg]already 148K: 0x%x\n", mode); + return 0; + } else { + di->bus.write(di, REG_TX_CMD, TX_TOGGLE); + msleep(10); + di->bus.read(di, REG_WROK_MODE, &mode); + dev_info(di->dev, "[otg]007B: 0x%x\n", mode); + if (mode & BIT(2)) + dev_info(di->dev, "[otg]set 148K success: 0x%x\n", + mode); + else + dev_info(di->dev, "[otg]set 148K error: 0x%x\n", mode); + } + + return 0; +} + +static enum power_supply_property idtp9220_props[] = { + POWER_SUPPLY_PROP_PIN_ENABLED, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_WIRELESS_VERSION, + POWER_SUPPLY_PROP_WIRELESS_FW_VERSION, + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT, + POWER_SUPPLY_PROP_RX_IOUT, + POWER_SUPPLY_PROP_WIRELESS_TX_ID, + POWER_SUPPLY_PROP_TX_ADAPTER, + POWER_SUPPLY_PROP_REVERSE_CHG_MODE, + POWER_SUPPLY_PROP_CHIP_OK, + POWER_SUPPLY_PROP_DIV_2_MODE, + POWER_SUPPLY_PROP_OTG_STATE, + POWER_SUPPLY_PROP_REVERSE_CHG_HALL3, + POWER_SUPPLY_PROP_REVERSE_CHG_HALL4, + POWER_SUPPLY_PROP_REVERSE_PEN_SOC, + POWER_SUPPLY_PROP_REVERSE_VOUT, + POWER_SUPPLY_PROP_REVERSE_IOUT, +}; + +static int idtp9220_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct idtp9220_device_info *di = power_supply_get_drvdata(psy); + u8 temp = 0; + int rc = 0; + switch (psp) { + case POWER_SUPPLY_PROP_PIN_ENABLED: + val->intval = di->gpio_enable_val; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = di->dcin_present; + break; + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + val->intval = di->epp; + break; + case POWER_SUPPLY_PROP_WIRELESS_FW_VERSION: + val->intval = di->fw_version; + break; + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + val->intval = di->ss; + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + if (!di->power_good_flag) { + val->intval = 0; + break; + } + val->intval = idtp9220_get_vout(di); + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT: + if (!di->power_good_flag) { + val->intval = 0; + break; + } + val->intval = idtp9220_get_vrect(di); + break; + case POWER_SUPPLY_PROP_RX_IOUT: + if (!di->power_good_flag) { + val->intval = 0; + break; + } + val->intval = idtp9220_get_iout(di); + break; + case POWER_SUPPLY_PROP_WIRELESS_TX_ID: + val->intval = idtp9220_get_tx_id(di); + break; + case POWER_SUPPLY_PROP_TX_ADAPTER: + val->intval = di->tx_charger_type; + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + val->intval = gpio_get_value(di->dt_props.reverse_gpio); + break; + case POWER_SUPPLY_PROP_CHIP_OK: + val->intval = di->chip_ok; + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_HALL3: + if (gpio_is_valid(di->dt_props.hall3_gpio)) { + val->intval = gpio_get_value(di->dt_props.hall3_gpio); + dev_info(di->dev, "hall3 gpio:%d\n", val->intval); + } else { + val->intval = -1; + dev_err(di->dev, "hall3 gpio is not provided\n"); + } + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_HALL4: + if (gpio_is_valid(di->dt_props.hall4_gpio)) { + val->intval = gpio_get_value(di->dt_props.hall4_gpio); + dev_info(di->dev, "hall4 gpio:%d\n", val->intval); + } else { + val->intval = -1; + dev_err(di->dev, "hall4 gpio is not provided\n"); + } + break; + case POWER_SUPPLY_PROP_REVERSE_PEN_SOC: + if (di->is_reverse_mode || di->is_boost_mode) + val->intval = di->reverse_pen_soc; + else + val->intval = 50; + break; + case POWER_SUPPLY_PROP_REVERSE_VOUT: + if (di->is_reverse_mode || di->is_boost_mode) + val->intval = di->reverse_vout; + else + val->intval = 0; + break; + case POWER_SUPPLY_PROP_REVERSE_IOUT: + if (di->is_reverse_mode || di->is_boost_mode) + val->intval = di->reverse_iout; + else + val->intval = 0; + break; + case POWER_SUPPLY_PROP_OTG_STATE: + if (!di->power_good_flag) { + val->intval = 0; + break; + } + rc = idtp9220_get_temperature(di, &temp); + if (!rc) + val->intval = temp; + else + val->intval = 0; + default: + return -EINVAL; + } + return 0; +} + +#define RX_VOUT_MAX_MV 20000 +#define RX_VOUT_MIN_MV 12000 +#define RX_VOUT_OFFSET_MV 100 + +static int idtp9220_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct idtp9220_device_info *di = power_supply_get_drvdata(psy); + int rc = 0; + + int data; + + switch (psp) { + case POWER_SUPPLY_PROP_PIN_ENABLED: + rc = idtp9220_set_enable_mode(di, val->intval); + break; + case POWER_SUPPLY_PROP_PRESENT: + rc = idtp9220_set_present(di, val->intval); + break; + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + di->ss = val->intval; + if (di->idtp_psy) + power_supply_changed(di->idtp_psy); + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + data = val->intval / 1000; + + if (data > RX_VOUT_MAX_MV) + data = RX_VOUT_MAX_MV; + else if (data < RX_VOUT_MIN_MV) + data = RX_VOUT_MIN_MV + RX_VOUT_OFFSET_MV; + + if (di->power_good_flag) { + if (data == CP_CLOSE_VOUT_MV) + schedule_delayed_work( + &di->rx_vout_cp_close_work, 0); + else + idtp9220_set_vout(di, data); + } + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + if (di->fw_update) { + dev_info(di->dev, "fw update going, break\n"); + break; + } + + if (di->hall3_online || di->hall4_online) { + if (di->is_reverse_mode || di->is_boost_mode) { + dev_info(di->dev, + "reverse charge running, return\n"); + break; + } + } else { + dev_info(di->dev, + "pen detach, don't open reverse charge\n"); + break; + } + + di->is_reverse_chg = 0; + schedule_delayed_work(&di->reverse_sent_state_work, 0); + if (!di->power_good_flag) { + idtp9220_set_reverse_enable(di, val->intval); + } else { + di->is_reverse_chg = 3; + schedule_delayed_work(&di->reverse_sent_state_work, 0); + } + break; + case POWER_SUPPLY_PROP_OTG_STATE: + rx_set_otg_state(di, val->intval); + break; + case POWER_SUPPLY_PROP_DIV_2_MODE: + idtp9220_power_off(di); + break; + default: + return -EINVAL; + } + + return rc; +} + +static int idtp9220_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + int rc; + + switch (psp) { + case POWER_SUPPLY_PROP_PIN_ENABLED: + case POWER_SUPPLY_PROP_PRESENT: + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + return 1; + default: + rc = 0; + break; + } + + return rc; +} + +static const struct power_supply_desc idtp_psy_desc = { + .name = "idt", + .type = POWER_SUPPLY_TYPE_WIRELESS, + .properties = idtp9220_props, + .num_properties = ARRAY_SIZE(idtp9220_props), + .get_property = idtp9220_get_prop, + .set_property = idtp9220_set_prop, + .property_is_writeable = idtp9220_prop_is_writeable, +}; + +#ifdef IDTP9220_SRAM_UPDATE +static void idtp9220_sram_update_work(struct work_struct *work) +{ + struct idtp9220_device_info *di = container_of( + work, struct idtp9220_device_info, sram_update_work.work); + u8 data; + int size = sizeof(idt_firmware_sram); + u8 buffer[size]; + int i = 0; + + di->bus.read(di, 0x4D, &data); + dev_info(di->dev, "[idtp] %s: 0x4D data:%x, (data & BIT(4)):%lu\n", + __func__, data, (data & BIT(4))); + if (!(data & BIT(4))) + return; + + di->bus.write_buf(di, 0x0600, idt_firmware_sram, size); + di->bus.read_buf(di, 0x0600, buffer, size); + + while (size--) { + if (idt_firmware_sram[i] == buffer[i]) { + printk("buffer[%d]:0x%x", i, buffer[i]); + } else { + printk("[idt] sram data is not right\n"); + return; + } + i++; + } + + di->bus.write(di, 0x4F, 0x5A); + + di->bus.write(di, 0x4E, BIT(6)); + + mdelay(1000); + di->bus.read(di, 0x4D, &data); + dev_info(di->dev, "[idtp] %s: 0x4D data:%x\n", __func__, data); +} +#endif + +/* +#ifdef CONFIG_DRM +static int wireless_fb_notifier_cb(struct notifier_block *self, +unsigned long event, void *data) +{ + +struct drm_notify_data *evdata = data; +int *blank; + +struct idtp9220_device_info *di = +container_of(self, struct idtp9220_device_info, wireless_fb_notif); + +mutex_lock(&di->screen_lock); +if (evdata && evdata->data && di) { +if (event == DRM_EARLY_EVENT_BLANK) { +blank = evdata->data; +if (*blank == DRM_BLANK_UNBLANK) { +di->screen_on = true; +pr_info("%s: screen_on\n", __func__); +if(di->status & FULL_MODE) +idtp922x_set_pmi_icl(di, DC_FUL_CURRENT); +} else if (*blank == DRM_BLANK_POWERDOWN) { +di->screen_on = false; +pr_info("%s: screen_off\n", __func__); +if(di->status & FULL_MODE) +idtp922x_set_pmi_icl(di, SCREEN_OFF_FUL_CURRENT); +} +} +} else { +pr_err("%s: Couldn't get DRM event\n", __func__); +mutex_unlock(&di->screen_lock); +return 0; +} +mutex_unlock(&di->screen_lock); +return 0; +} +#endif + */ + +static int idtp9220_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + int hall3_val = 1, hall4_val = 1; + struct idtp9220_device_info *di; + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + struct power_supply_config idtp_cfg = {}; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE)) { + dev_err(&client->dev, "i2c check functionality failed!\n"); + return -EIO; + } + + di = devm_kzalloc(&client->dev, sizeof(*di), GFP_KERNEL); + if (!di) { + dev_err(&client->dev, + "i2c allocated device info data failed!\n"); + return -ENOMEM; + } + + di->name = IDT_DRIVER_NAME; + di->dev = &client->dev; + di->chip_enable = 1; + di->ss = 2; + di->fw_update = false; + di->fw_version = 0; + di->status = NORMAL_MODE; + // set reverse pen soc to default + di->reverse_pen_soc = 255; + di->regmap = devm_regmap_init_i2c(client, &i2c_idtp9220_regmap_config); + if (!di->regmap) + return -ENODEV; + di->bus.read = idtp9220_read; + di->bus.write = idtp9220_write; + di->bus.read_buf = idtp9220_read_buffer; + di->bus.write_buf = idtp9220_write_buffer; + di->bus.mask_write = idtp9220_masked_write; + INIT_DELAYED_WORK(&di->irq_work, idtp9220_irq_work); + INIT_DELAYED_WORK(&di->hall3_irq_work, idtp9220_hall3_irq_work); + INIT_DELAYED_WORK(&di->hall4_irq_work, idtp9220_hall4_irq_work); + INIT_DELAYED_WORK(&di->wpc_det_work, idtp9220_wpc_det_work); + mutex_init(&di->read_lock); + mutex_init(&di->write_lock); + mutex_init(&di->wpc_det_lock); + /* + #ifdef CONFIG_DRM + mutex_init(&di->screen_lock); + #endif + */ + device_init_wakeup(&client->dev, true); + i2c_set_clientdata(client, di); + g_di = di; + + ret = idtp9220_parse_dt(di); + if (ret < 0) { + dev_err(di->dev, "%s: parse dt error [%d]\n", __func__, ret); + goto cleanup; + } + + ret = idtp9220_gpio_init(di); + if (ret < 0) { + dev_err(di->dev, "%s: gpio init error [%d]\n", __func__, ret); + goto cleanup; + } + + ret = idtp9220_irq_request(di); + if (ret < 0) { + dev_err(di->dev, "%s: request irq error [%d]\n", __func__, ret); + goto cleanup; + } + + /* + * this func write config to otp when init, due to the config will be + * write to otp in factory, so delete it. + * + + if (!program_fw(di, 0x0000, idt_firmware, sizeof(idt_firmware))) { + dev_err(&client->dev, "program fw failed.\n"); + //goto cleanup; + } + */ + + if (sysfs_create_group(&client->dev.kobj, &sysfs_group_attrs)) { + dev_err(&client->dev, "create sysfs attrs failed!\n"); + ret = -EIO; + goto cleanup; + } + idtp_cfg.drv_data = di; + di->idtp_psy = + power_supply_register(di->dev, &idtp_psy_desc, &idtp_cfg); + + INIT_DELAYED_WORK(&di->chg_monitor_work, idtp9220_monitor_work); + INIT_DELAYED_WORK(&di->chg_detect_work, idtp9220_chg_detect_work); + INIT_DELAYED_WORK(&di->bpp_connect_load_work, + idtp9220_bpp_connect_load_work); + INIT_DELAYED_WORK(&di->epp_connect_load_work, + idtp9220_epp_connect_load_work); + INIT_DELAYED_WORK(&di->cmd_check_work, idtp9220_cmd_check_work); + INIT_DELAYED_WORK(&di->vout_regulator_work, + idtp9220_vout_regulator_work); + INIT_DELAYED_WORK(&di->load_fod_param_work, + idtp9220_load_fod_param_work); + INIT_DELAYED_WORK(&di->rx_vout_work, idtp9220_rx_vout_work); + INIT_DELAYED_WORK(&di->dc_check_work, idtp9220_dc_check_work); + INIT_DELAYED_WORK(&di->initial_tx_work, idtp9220_initial_tx_work); + INIT_DELAYED_WORK(&di->bpp_e5_tx_work, idtp9220_bpp_e5_tx_work); + INIT_DELAYED_WORK(&di->pan_tx_work, idt_pan_tx_work); + INIT_DELAYED_WORK(&di->voice_tx_work, idt_voice_tx_work); + INIT_DELAYED_WORK(&di->qc2_f1_tx_work, idtp9220_qc2_f1_tx_work); + INIT_DELAYED_WORK(&di->qc3_epp_work, idtp9220_qc3_epp_work); + INIT_DELAYED_WORK(&di->oob_set_cep_work, idtp_oob_set_cep_work); + INIT_DELAYED_WORK(&di->oob_set_ept_work, idtp_oob_set_ept_work); + INIT_DELAYED_WORK(&di->rx_ready_check_work, idtp_rx_ready_check_work); + INIT_DELAYED_WORK(&di->oob_clean_work, idtp_oob_clean_work); + + INIT_DELAYED_WORK(&di->reverse_ept_type_work, + reverse_ept_type_get_work); + INIT_DELAYED_WORK(&di->reverse_chg_state_work, + reverse_chg_state_set_work); + INIT_DELAYED_WORK(&di->reverse_dping_state_work, + reverse_dping_state_set_work); + INIT_DELAYED_WORK(&di->reverse_test_state_work, + reverse_test_state_set_work); + INIT_DELAYED_WORK(&di->reverse_sent_state_work, + reverse_chg_sent_state_work); + + INIT_DELAYED_WORK(&di->get_vout_work, idtp9220_test_vout_work); + INIT_DELAYED_WORK(&di->get_iout_work, idtp9220_test_iout_work); + INIT_DELAYED_WORK(&di->fw_download_work, idtp9220_fw_download_work); + INIT_DELAYED_WORK(&di->idt_first_boot, idtp9220_idt_first_boot); + INIT_DELAYED_WORK(&di->rx_vout_cp_close_work, + idtp9220_rx_vout_cp_close_work); + INIT_DELAYED_WORK(&di->keep_awake_work, idtp9220_keep_awake_work); + INIT_DELAYED_WORK(&di->reverse_chg_work, idt_reverse_chg_work); + mutex_init(&di->sysfs_op_lock); + mutex_init(&di->reverse_op_lock); + + di->ocp_disable_votable = + create_votable("IDTP_OCP_DISABLE", VOTE_SET_ANY, + idtp9220_ocp_disable_vote_cb, di); + if (IS_ERR_OR_NULL(di->ocp_disable_votable)) { + PTR_ERR_OR_ZERO(di->ocp_disable_votable); + dev_err(di->dev, "Failed to initialize ocp_disable_votable\n"); + return -ENODEV; + } + //ret = idtp9220_get_property_names(di); + /* + #ifdef CONFIG_DRM + if (&di->wireless_fb_notif) { + di->wireless_fb_notif.notifier_call = wireless_fb_notifier_cb; + rc = drm_register_client(&di->wireless_fb_notif); + if (rc < 0) { + dev_err(di->dev, + "Couldn't register notifier rc=%d\n", rc); + return rc; + } + //INIT_DELAYED_WORK(&di->screen_on_work, wireless_screen_on_work); + } else + dev_err(di->dev, "Unsupported fb notifier \n"); + #endif + */ + + if (alarmtimer_get_rtcdev()) { + alarm_init(&di->reverse_dping_alarm, ALARM_BOOTTIME, + reverse_dping_alarm_cb); + } else { + dev_err(di->dev, "Failed to initialize reverse dping alarm\n"); + return -ENODEV; + } + + if (alarmtimer_get_rtcdev()) { + alarm_init(&di->reverse_chg_alarm, ALARM_BOOTTIME, + reverse_chg_alarm_cb); + } else { + dev_err(di->dev, "Failed to initialize reverse chg alarm\n"); + return -ENODEV; + } + if (alarmtimer_get_rtcdev()) { + alarm_init(&di->reverse_test_ready_alarm, ALARM_BOOTTIME, + reverse_test_ready_alarm_cb); + } else { + dev_err(di->dev, + "Failed to initialize reverse_test_ready_alarm alarm\n"); + return -ENODEV; + } + + if (gpio_is_valid(di->dt_props.hall3_gpio)) { + hall3_val = gpio_get_value(di->dt_props.hall3_gpio); + if (!hall3_val) { + dev_info(di->dev, "pen online, start reverse charge\n"); + schedule_delayed_work(&di->hall3_irq_work, + msecs_to_jiffies(5000)); + } + } else + dev_err(di->dev, "%s: hall3 gpio not provided\n", __func__); + + if (gpio_is_valid(di->dt_props.hall4_gpio)) { + hall4_val = gpio_get_value(di->dt_props.hall4_gpio); + if (!hall4_val) { + dev_info(di->dev, "pen online, start reverse charge\n"); + schedule_delayed_work(&di->hall4_irq_work, + msecs_to_jiffies(5000)); + } + } else + dev_err(di->dev, "%s: hall4 gpio not provided\n", __func__); + + dev_info(di->dev, "[idt] success probe idtp922x driver\n"); + get_cmdline(di); + if (!di->power_off_mode) +#ifdef CONFIG_FACTORY_BUILD + schedule_delayed_work(&di->chg_detect_work, 3 * HZ); +#else + schedule_delayed_work(&di->chg_detect_work, 8 * HZ); +#endif + else { + dev_info(di->dev, "off-chg mode, reset chip\n"); + idtp9220_set_enable_mode(di, false); + msleep(10); + idtp9220_set_enable_mode(di, true); + } + + if (!idt_first_flag) + schedule_delayed_work(&di->idt_first_boot, + msecs_to_jiffies(30000)); +#ifdef IDTP9220_SRAM_UPDATE + INIT_DELAYED_WORK(&di->sram_update_work, idtp9220_sram_update_work); + schedule_delayed_work(&di->sram_update_work, 10 * HZ); +#endif + return 0; + +cleanup: + free_irq(di->irq, di); + cancel_delayed_work_sync(&di->irq_work); + cancel_delayed_work_sync(&di->hall3_irq_work); + cancel_delayed_work_sync(&di->hall4_irq_work); + i2c_set_clientdata(client, NULL); + + return ret; +} + +static int idtp9220_remove(struct i2c_client *client) +{ + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + gpio_free(di->dt_props.reverse_gpio); + gpio_free(di->dt_props.reverse_boost_enable_gpio); + cancel_delayed_work_sync(&di->irq_work); + cancel_delayed_work_sync(&di->hall3_irq_work); + cancel_delayed_work_sync(&di->hall4_irq_work); + i2c_set_clientdata(client, NULL); + + return 0; +} + +static void idtp9220_shutdown(struct i2c_client *client) +{ + struct idtp9220_device_info *di = i2c_get_clientdata(client); + + if (di->power_good_flag) { + msleep(30); + idtp9220_set_enable_mode(di, false); + msleep(10); + idtp9220_set_enable_mode(di, true); + } +} + +static const struct i2c_device_id idtp9220_id[] = { + { IDT_DRIVER_NAME, 0 }, + {}, +}; + +static const struct of_device_id idt_match_table[] = { { .compatible = + "idt,p9418" }, + {} }; + +MODULE_DEVICE_TABLE(i2c, idtp9220_id); + +static struct i2c_driver idtp9220_driver = { + .driver = { + .name = IDT_DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = idt_match_table, + }, + .probe = idtp9220_probe, + .remove = idtp9220_remove, + .shutdown = idtp9220_shutdown, + .id_table = idtp9220_id, +}; + +static int __init idt_init(void) +{ + int ret; + + ret = i2c_add_driver(&idtp9220_driver); + if (ret) + printk(KERN_ERR "idt i2c driver init failed!\n"); + + return ret; +} + +static void __exit idt_exit(void) +{ + i2c_del_driver(&idtp9220_driver); +} + +module_init(idt_init); +module_exit(idt_exit); + +MODULE_AUTHOR("bsp@xiaomi.com"); +MODULE_DESCRIPTION("IDTP9220 Wireless Power Charger Monitor driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/power/supply/renesas/idtp9418.h b/drivers/power/supply/renesas/idtp9418.h new file mode 100644 index 000000000000..93de90033cee --- /dev/null +++ b/drivers/power/supply/renesas/idtp9418.h @@ -0,0 +1,507 @@ +/** + * @file idtp9220.h + * @author + * @date Sun Nov 22 11:49:55 2015 + * + * @brief + * + * + */ +#ifndef __IDTP9220_H__ +#define __IDTP9220_H__ + +#include +#include +#include +#include "idtp9418_fw.h" +#define IDT_DRIVER_NAME "idtp9418" +#define IDT_I2C_ADDR 0x3b + +#define HSCLK 60000 + +#define ADJUST_METE_MV 35 +#define IDTP9220_DELAY 2000 +#define CHARGING_FULL 100 +#define CHARGING_NEED 95 + +/* status low regiter bits define */ +#define STATUS_VOUT_ON (1 << 7) +#define STATUS_VOUT_OFF (1 << 6) +#define STATUS_TX_DATA_RECV (1 << 4) +#define STATUS_OV_TEMP (1 << 2) +#define STATUS_OV_VOL (1 << 1) +#define STATUS_OV_CURR (1 << 0) + +#define OVER_EVENT_OCCUR (STATUS_OV_TEMP | STATUS_OV_VOL | STATUS_OV_CURR) +#define TOGGLE_LDO_ON_OFF (1 << 1) + +/* interrupt register bits define */ +#define INT_RXREADY (1 << 22) +#define INT_POWER_LOSS (1 << 21) +#define INT_OVERCURRENT_HIGH (1 << 20) +#define RENEG_FAIL (1 << 19) +#define RENEG_SUCCESS (1 << 18) +#define INT_RPP_READ (1 << 17) +#define INT_EXT5V_FAIL (1 << 16) +#define INT_VSWITCH_FAIL (1 << 15) +#define INT_SLEEPMODE (1 << 14) +#define INT_IDAUTH_SUCESS (1 << 13) +#define INT_IDAUTH_FAIL (1 << 12) +#define INT_SEND_SUCESS (1 << 11) +#define INT_SEND_TIMEOUT (1 << 10) +#define INT_AUTH_SUCESS (1 << 9) +#define INT_AUTH_FAIL (1 << 8) +#define INT_VOUT_OFF (1 << 7) +#define INT_VOUT_ON (1 << 6) +#define INT_MODE_CHANGE (1 << 5) +#define INT_TX_DATA_RECV (1 << 4) +#define INT_VSWITCH_SUCESS (1 << 3) +#define INT_OV_TEMP (1 << 2) +#define INT_OV_VOL (1 << 1) +#define INT_OV_CURR (1 << 0) + +/*TRX int bits define*/ +#define INT_GET_BLE_ADDR (1 << 8) +#define INT_INIT_TX (1 << 7) +#define INT_GET_DPING (1 << 6) +#define INT_GET_PPP (1 << 5) +#define INT_GET_CFG (1 << 4) +#define INT_GET_ID (1 << 3) +#define INT_GET_SS (1 << 2) +#define INT_START_DPING (1 << 1) +#define INT_EPT_TYPE (1 << 0) + +#define TX_TOGGLE BIT(6) // toggle work mode(148K or 190K) +#define TX_FOD_EN BIT(5) // enable FOD +#define TX_WD BIT(4) // enable WD +#define TX_SEND_FSK BIT(3) // SEND_FSK +#define TX_DIS BIT(2) // disable tx +#define TX_CLRINT BIT(1) // clr int +#define TX_EN BIT(0) // enable tx mode + +/* used registers define */ +#define REG_CHIP_ID_L 0x0000 +#define REG_CHIP_ID_H 0x0001 +#define REG_CHIP_REV 0x0002 +#define REG_CTM_ID 0x0003 +#define REG_OTPFWVER_ADDR 0x0004 // OTP firmware version +#define REG_EPRFWVER_ADDR 0x001c // EEPROM firmware version +#define REG_SYS_INT_CLR 0x0028 // int clear +#define REG_SYS_INT 0x0030 // interrupt +#define REG_STATUS_L 0x0034 +#define REG_STATUS_H 0x0035 +#define REG_INTR_L 0x0036 +#define REG_INTR_H 0x0037 +#define REG_INTR_EN_L 0x0038 +#define REG_INTR_EN_H 0x0039 +#define REG_CHG_STATUS 0x003A +#define REG_ADC_VOUT_L 0x003C +#define REG_ADC_VOUT_H 0x003D +#define REG_VOUT_SET 0x003E +#define REG_VRECT_ADJ 0x003F +#define REG_ADC_VRECT 0x0040 +#define REG_RX_LOUT_L 0x0044 +#define REG_RX_LOUT_H 0x0045 +#define REG_RX_DIE_TEMP 0x0046 +#define REG_FREQ_ADDR \ + 0x0048 // Operating Frequency, Fop(KHz) = 64 * 6000 /value * 256) +#define REG_ILIM_SET 0x004A +#define REG_SIGNAL_STRENGTH 0x004B +#define REG_WPC_MODE 0x004D +#define REG_SSCMND 0x004e // Command Register, COM (0x4E) +#define REG_RX_RESET 0x004F +#define REG_PROPPKT \ + 0x0050 // Proprietary Packet Header Register, PPP_Header (0x50) +#define REG_PPPDATA \ + 0x0051 // PPP Data Value Register(0X51, 0x52, 0x53, 0x54, 0x55) +#define REG_SSINTCLR 0x0056 // Interrupt Clear Registers, INT_Clear_L (0x56) +#define REG_BCHEADER 0x0058 // Back Channel Packet Register (0x58) +#define REG_BCDATA \ + 0x0059 // Back Channel Packet Register (0x59, 0x5A, 0x5B, 0x5C) +#define REG_FC_VOLTAGE_L 0x0078 // Fast Charging Voltage Register +#define REG_FC_VOLTAGE_H 0x0079 +#define REG_REGULATOR_L 0x000C +#define REG_REGULATOR_H 0x000d +#define REG_POWER_MAX 0x0084 //Get the TX power on EPP mode. +#define REG_TX_TYPE 0x00A2 //Get the TX type. +#define REG_BLE_FLAG 0x00A4 //Get the rx ble flag. +#define REG_CEP 0x00A5 //Get the CEP. +#define REG_RPP 0x00A6 //Get the RPP. +#define REG_MAX_POWER 0x008E +#define REG_OCP_CONFIG 0x00F1 +#define REG_TEMPTER 0x00F2 + +/*add for reverse charge*/ +#define REG_EPT_TYPE 0x0074 +#define REG_TX_CMD 0x0076 +#define REG_TX_DATA 0x0078 +#define REG_WROK_MODE 0x007B +#define REG_VRECT_TAEGET 0x0090 +#define REG_FOD_LOW 0x0092 +#define REG_FOD_HIGH 0x0093 +#define REG_MAC_ADDR 0x00be + +#define REG_REVERSE_IIN_LOW 0x006e +#define REG_REVERSE_IIN_HIGH 0x006f +#define REG_REVERSE_VIN_LOW 0x0070 +#define REG_REVERSE_VIN_HIGH 0x0071 +#define REG_REVERSE_TEMP 0x007a + +#define EPT_POCP BIT(15) +#define EPT_OTP BIT(14) +#define EPT_FOD BIT(13) +#define EPT_LVP BIT(12) +#define EPT_OVP BIT(11) +#define EPT_OCP BIT(10) +#define EPT_RPP_TIMEOUT BIT(9) +#define EPT_CEP_TIMEOUT BIT(8) +#define EPT_CMD BIT(0) + +#define REG_EXTERNAL_5V 0x00dc //external 5v enable + +// RX -> TX +#define PROPRIETARY18 0x18 +#define PROPRIETARY28 0x28 +#define PROPRIETARY38 0x38 +#define PROPRIETARY48 0x48 +#define PROPRIETARY58 0x58 + +// bitmap for customer command +#define BC_NONE 0x00 +#define BC_SET_FREQ 0x03 +#define BC_GET_FREQ 0x04 +#define BC_READ_FW_VER 0x05 +#define BC_READ_Iin 0x06 +#define BC_READ_Vin 0x07 +#define BC_SET_Vin 0x0a + +#define BC_ADAPTER_TYPE 0x0b +#define BC_RESET 0x0c +#define BC_READ_I2C 0x0d +#define BC_WRITE_I2C 0x0e +#define BC_VI2C_INIT 0x10 +#define BC_RX_ID_AUTH 0x3b +#define BC_TX_COMPATIBLE_HWID 0x3f +#define BC_TX_HWID 0x4c +#define BC_TX_TOGGLE 0xc4 +#define CMD_GET_BLEMAC_2_0 0xb6 +#define CMD_GET_BLEMAC_5_3 0xb7 +#define CMD_FACOTRY_REVERSE 0x30 + +//Factory test command +#define BC_READ_IOUT 0x12 +#define BC_READ_VOUT 0x13 +#define BC_RX_CHIP_VERSION 0x23 +#define BC_RX_FW_VERSION 0x24 +#define BC_START_CHARGE 0x30 +#define BC_SET_AP_OVERLOAD 0x31 +#define BC_ENABLE_FAST_CHARGE 0x32 + +/* Adapter_list = {0x00:'ADAPTER_UNKNOWN', */ +/* 0x01:'SDP 500mA', */ +/* 0x02:'CDP 1.1A', */ +/* 0x03:'DCP 1.5A', */ +/* 0x05:'QC2.0', */ +/* 0x06:'QC3.0', */ +/* 0x07:'PD',} */ +//define adapter type +#define ADAPTER_NONE 0x00 +#define ADAPTER_SDP 0x01 +#define ADAPTER_CDP 0x02 +#define ADAPTER_DCP 0x03 +#define ADAPTER_QC2 0x05 +#define ADAPTER_QC3 0x06 +#define ADAPTER_PD 0x07 +#define ADAPTER_AUTH_FAILED 0x08 +#define ADAPTER_XIAOMI_QC3 0x09 +#define ADAPTER_XIAOMI_PD 0x0a +#define ADAPTER_ZIMI_CAR_POWER 0x0b +#define ADAPTER_XIAOMI_PD_40W 0x0c +#define ADAPTER_VOICE_BOX 0x0d +#define ADAPTER_XIAOMI_PD_45W 0x0e +#define ADAPTER_XIAOMI_PD_60W 0x0f + +#define NORMAL_MODE 0x1 +#define TAPER_MODE 0x2 +#define FULL_MODE 0x3 +#define RECHG_MODE 0x4 + +//fw version to update +#define FW_VERSION 0x1 + +//add for crc verify +#define CRC_VERIFY_LOW 0xB5 +#define CRC_VERIFY_HIGH 0xA9 + +//add for reverse fod +#define REVERSE_FOD 500 + +/*CLRPOWERGOOD BIT(10), upper byte is 0x8*/ +#define CLRPOWERGOOD 0x04 +// bitmap for status flags +// 1: indicates a pending interrupt for LDO Vout state change – from OFF to ON +#define VOUTCHANGED BIT(7) // Stat_Vout_ON +// 1: indicates a pending interrupt for TX Data Received. (Change from “No Received Data†state to “Data Received†state) +#define TXDATARCVD BIT(4) // TX Data Received + +// bitmap for SSCmnd register 0x4e +#define VSWITCH BIT(7) +// If AP sets this bit to "1" then IDTP9220 M0 clears the interrupt corresponding to the bit(s) which has a value of “1†+#define CLRINT BIT(5) // Clear Interrupt +// If AP sets this bit to "1" then IDTP9220 M0 toggles LDO output once (from on to off, or from off to on), and then sets this bit to “0†+#define LDOTGL BIT(1) // Toggle LDO On/OFF +// If AP sets this bit to “1†then IDTP9220 M0 sends the Proprietary Packet +#define SENDPROPP BIT(0) // SEND RX Data + +#define SEND_DEVICE_AUTH BIT(2) + +enum VOUT_SET_VAL { + VOUT_VAL_3500_MV = 0, + VOUT_VAL_3600_MV, + VOUT_VAL_3700_MV, + VOUT_VAL_3800_MV, + VOUT_VAL_3900_MV, + VOUT_VAL_4000_MV, + VOUT_VAL_4100_MV, + VOUT_VAL_4200_MV, + VOUT_VAL_4300_MV, + VOUT_VAL_4400_MV, + VOUT_VAL_4500_MV, + VOUT_VAL_4600_MV, + VOUT_VAL_4700_MV, + VOUT_VAL_4800_MV, + VOUT_VAL_4900_MV, + VOUT_VAL_5000_MV, + VOUT_VAL_5100_MV, + VOUT_VAL_5200_MV, + VOUT_VAL_5300_MV, + VOUT_VAL_5400_MV, + VOUT_VAL_5500_MV, + VOUT_VAL_5600_MV, + VOUT_VAL_5700_MV, + VOUT_VAL_5800_MV, + VOUT_VAL_5900_MV, + VOUT_VAL_6000_MV, + VOUT_VAL_6100_MV, + VOUT_VAL_6200_MV, + VOUT_VAL_6300_MV, + VOUT_VAL_6400_MV, + VOUT_VAL_6500_MV, + VOUT_VAL_6600_MV, + VOUT_VAL_6700_MV, + VOUT_VAL_6800_MV, + VOUT_VAL_6900_MV, + VOUT_VAL_7000_MV, + VOUT_VAL_7100_MV, + VOUT_VAL_7200_MV, + VOUT_VAL_7300_MV, + VOUT_VAL_7400_MV, + VOUT_VAL_7500_MV, + VOUT_VAL_7600_MV, + VOUT_VAL_7700_MV, + VOUT_VAL_7800_MV, + VOUT_VAL_7900_MV, + VOUT_VAL_8000_MV, +}; + +enum IMIL_SET_VAL { + CURR_VAL_100_MA = 0, + CURR_VAL_200_MA, + CURR_VAL_300_MA, + CURR_VAL_400_MA, + CURR_VAL_500_MA, + CURR_VAL_600_MA, + CURR_VAL_700_MA, + CURR_VAL_800_MA, + CURR_VAL_900_MA, + CURR_VAL_1000_MA, + CURR_VAL_1100_MA, + CURR_VAL_1200_MA, + CURR_VAL_1300_MA, +}; + +struct vol_curr_table { + int index; + char *val; +}; +/* +struct idtp9220_platform_data { + enum VOUT_SET_VAL vout_val_default; + enum IMIL_SET_VAL curr_val_default; + unsigned long gpio_en; +}; +*/ +typedef struct { // write to structure at SRAM address 0x0400 + u16 status; // Read/Write by both 9220 and 9220 host + u16 startAddr; // OTP image address of the current packet + u16 codeLength; // The size of the OTP image data in the current packet + u16 dataChksum; // Checksum of the current packet + u8 dataBuf[128]; // OTP image data of the current packet +} idtp9220_packet_t; + +// proprietary packet type +typedef struct { + u8 header; // The header consists of a single byte that indicates the Packet type. + u8 cmd; // Back channel command + u8 data[4]; // Send data buffer +} ProPkt_Type; + +#if 1 +static char bootloader_data[] = { + 0x00, 0x02, 0x00, 0x20, 0x99, 0x00, 0x00, 0x00, 0x9D, 0x00, 0x00, 0x00, + 0x9F, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x02, 0xF8, 0x00, 0xF0, 0x30, 0xF8, + 0x0C, 0xA0, 0x30, 0xC8, 0x08, 0x38, 0x24, 0x18, 0x2D, 0x18, 0xA2, 0x46, + 0x67, 0x1E, 0xAB, 0x46, 0x54, 0x46, 0x5D, 0x46, 0xAC, 0x42, 0x01, 0xD1, + 0x00, 0xF0, 0x22, 0xF8, 0x7E, 0x46, 0x0F, 0x3E, 0x0F, 0xCC, 0xB6, 0x46, + 0x01, 0x26, 0x33, 0x42, 0x00, 0xD0, 0xFB, 0x1A, 0xA2, 0x46, 0xAB, 0x46, + 0x33, 0x43, 0x18, 0x47, 0xA8, 0x06, 0x00, 0x00, 0xB8, 0x06, 0x00, 0x00, + 0x00, 0x23, 0x00, 0x24, 0x00, 0x25, 0x00, 0x26, 0x10, 0x3A, 0x01, 0xD3, + 0x78, 0xC1, 0xFB, 0xD8, 0x52, 0x07, 0x00, 0xD3, 0x30, 0xC1, 0x00, 0xD5, + 0x0B, 0x60, 0x70, 0x47, 0x1F, 0xB5, 0x1F, 0xBD, 0x10, 0xB5, 0x10, 0xBD, + 0x00, 0xF0, 0x09, 0xFB, 0x11, 0x46, 0xFF, 0xF7, 0xF7, 0xFF, 0x00, 0xF0, + 0x45, 0xFA, 0x00, 0xF0, 0x21, 0xFB, 0x03, 0xB4, 0xFF, 0xF7, 0xF2, 0xFF, + 0x03, 0xBC, 0x00, 0xF0, 0x27, 0xFB, 0x00, 0x00, 0x05, 0x48, 0x00, 0x47, + 0xFE, 0xE7, 0xFE, 0xE7, 0xFE, 0xE7, 0x00, 0x00, 0x03, 0x48, 0x04, 0x49, + 0x02, 0x4A, 0x04, 0x4B, 0x70, 0x47, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, + 0x60, 0x00, 0x00, 0x20, 0x60, 0x01, 0x00, 0x20, 0x60, 0x00, 0x00, 0x20, + 0xFE, 0xB5, 0x04, 0x46, 0x00, 0x20, 0x02, 0x90, 0x10, 0x20, 0x20, 0x40, + 0x00, 0x28, 0x64, 0xD0, 0x01, 0x20, 0xFA, 0x4E, 0x30, 0x80, 0x80, 0x1E, + 0x30, 0x81, 0x01, 0x46, 0xF8, 0x4E, 0x31, 0x83, 0x08, 0x0C, 0x70, 0x83, + 0x00, 0x22, 0x44, 0xE0, 0xF6, 0x48, 0x40, 0x88, 0x80, 0x18, 0x83, 0xB2, + 0x01, 0x93, 0xD8, 0x13, 0x00, 0x28, 0x03, 0xD1, 0x01, 0x20, 0xC0, 0x03, + 0x18, 0x43, 0x01, 0x90, 0xEF, 0x48, 0xC2, 0x81, 0x03, 0x80, 0xEE, 0x4E, + 0x01, 0x98, 0x70, 0x80, 0x01, 0x98, 0x05, 0x78, 0xEA, 0x48, 0x85, 0x80, + 0x30, 0x46, 0x85, 0x80, 0x30, 0x20, 0x20, 0x40, 0x10, 0x28, 0x07, 0xD1, + 0x00, 0xBF, 0xE6, 0x48, 0x00, 0x88, 0x40, 0x06, 0xC0, 0x0F, 0x00, 0x28, + 0xF9, 0xD1, 0x1E, 0xE0, 0x00, 0x20, 0x00, 0x90, 0x18, 0xE0, 0xC8, 0x0F, + 0x07, 0x27, 0x00, 0x9E, 0xBE, 0x1B, 0x2F, 0x46, 0x37, 0x41, 0xFE, 0x07, + 0xF6, 0x0F, 0x70, 0x40, 0x00, 0x28, 0x01, 0xD0, 0xDE, 0x48, 0x00, 0xE0, + 0x00, 0x20, 0x4E, 0x00, 0x70, 0x40, 0x01, 0x46, 0xD9, 0x4E, 0x31, 0x83, + 0x08, 0x0C, 0x70, 0x83, 0x00, 0x98, 0x40, 0x1C, 0xC0, 0xB2, 0x00, 0x90, + 0x00, 0x98, 0x07, 0x28, 0xE3, 0xDD, 0x50, 0x1C, 0x82, 0xB2, 0xD4, 0x48, + 0x80, 0x88, 0x90, 0x42, 0xB6, 0xDC, 0x30, 0x20, 0x20, 0x40, 0x10, 0x28, + 0x13, 0xD1, 0xCE, 0x48, 0x00, 0x89, 0xCE, 0x4E, 0x70, 0x82, 0xCC, 0x48, + 0x00, 0x89, 0xCD, 0x4E, 0xF6, 0x88, 0xB0, 0x42, 0x02, 0xD1, 0x00, 0x20, + 0x02, 0x90, 0x2F, 0xE0, 0x01, 0x20, 0x02, 0x90, 0xC6, 0x48, 0x00, 0x89, + 0xC7, 0x4E, 0xF0, 0x80, 0x28, 0xE0, 0x88, 0xB2, 0xC5, 0x4E, 0xF6, 0x88, + 0xB0, 0x42, 0x01, 0xD1, 0x01, 0x20, 0x00, 0xE0, 0x00, 0x20, 0x0E, 0x02, + 0x36, 0x0E, 0xC1, 0x4F, 0x3F, 0x7A, 0xBE, 0x42, 0x01, 0xD1, 0x01, 0x26, + 0x00, 0xE0, 0x00, 0x26, 0x30, 0x40, 0x0E, 0x0E, 0xBC, 0x4F, 0x7F, 0x7A, + 0xBE, 0x42, 0x01, 0xD1, 0x01, 0x26, 0x00, 0xE0, 0x00, 0x26, 0x30, 0x40, + 0x00, 0x28, 0x02, 0xD0, 0x00, 0x20, 0x02, 0x90, 0x08, 0xE0, 0x01, 0x20, + 0x02, 0x90, 0xB5, 0x4E, 0xF1, 0x80, 0x08, 0x02, 0x00, 0x0E, 0x30, 0x72, + 0x08, 0x0E, 0x70, 0x72, 0x02, 0x98, 0xFE, 0xBD, 0x10, 0xB5, 0x02, 0x46, + 0xAE, 0x4B, 0x1B, 0x8A, 0x04, 0x24, 0x23, 0x43, 0xAC, 0x4C, 0x23, 0x82, + 0x63, 0x14, 0xAE, 0x4C, 0xA3, 0x81, 0x93, 0x00, 0x19, 0x60, 0xAD, 0x4B, + 0x1B, 0x88, 0xA4, 0x14, 0x23, 0x40, 0x18, 0x46, 0xA6, 0x4B, 0x1B, 0x8A, + 0x04, 0x24, 0xA3, 0x43, 0xA4, 0x4C, 0x23, 0x82, 0xA8, 0x4B, 0xA6, 0x4C, + 0xA3, 0x81, 0x10, 0xBD, 0x10, 0xB5, 0x02, 0x46, 0xA0, 0x4B, 0x1B, 0x8A, + 0x02, 0x24, 0x23, 0x43, 0x9E, 0x4C, 0x23, 0x82, 0x63, 0x14, 0xA0, 0x4C, + 0xA3, 0x81, 0x11, 0x70, 0x9F, 0x4B, 0x1B, 0x88, 0xA4, 0x14, 0x23, 0x40, + 0x18, 0x46, 0x99, 0x4B, 0x1B, 0x8A, 0x02, 0x24, 0xA3, 0x43, 0x97, 0x4C, + 0x23, 0x82, 0x9B, 0x4B, 0x98, 0x4C, 0xA3, 0x81, 0x10, 0xBD, 0xF1, 0xB5, + 0x88, 0xB0, 0x08, 0x9D, 0x00, 0x20, 0x00, 0x90, 0x91, 0x48, 0x00, 0x8A, + 0x08, 0x21, 0x88, 0x43, 0x8F, 0x49, 0x08, 0x82, 0x8F, 0x48, 0x00, 0x88, + 0x00, 0x07, 0x00, 0x0F, 0x03, 0x90, 0x8D, 0x48, 0x40, 0x88, 0x02, 0x90, + 0x8B, 0x48, 0x80, 0x88, 0x01, 0x90, 0x01, 0x99, 0x02, 0x98, 0x40, 0x18, + 0x40, 0x1E, 0x80, 0xB2, 0x05, 0x90, 0x05, 0x98, 0xC0, 0x13, 0x00, 0x28, + 0x04, 0xD1, 0x01, 0x21, 0xC9, 0x03, 0x05, 0x98, 0x08, 0x43, 0x05, 0x90, + 0x02, 0x98, 0x07, 0x90, 0x01, 0x99, 0x07, 0x98, 0x40, 0x18, 0x80, 0xB2, + 0x07, 0x90, 0x00, 0x27, 0x08, 0xE0, 0x7E, 0x48, 0x08, 0x30, 0xC1, 0x5D, + 0x07, 0x98, 0x08, 0x18, 0x80, 0xB2, 0x07, 0x90, 0x78, 0x1C, 0x87, 0xB2, + 0x01, 0x98, 0x87, 0x42, 0xF3, 0xDB, 0x77, 0x49, 0x07, 0x98, 0x48, 0x82, + 0x76, 0x48, 0xC1, 0x88, 0x07, 0x98, 0x81, 0x42, 0x73, 0xD1, 0x03, 0x98, + 0x01, 0x28, 0x01, 0xD1, 0x00, 0x20, 0x0C, 0xE0, 0x03, 0x98, 0x03, 0x28, + 0x01, 0xD1, 0x04, 0x20, 0x07, 0xE0, 0x03, 0x98, 0x05, 0x28, 0x01, 0xD1, + 0x24, 0x20, 0x02, 0xE0, 0x6F, 0x48, 0x20, 0x30, 0x00, 0x89, 0x6E, 0x49, + 0x20, 0x31, 0x08, 0x81, 0x00, 0x27, 0xBE, 0xE0, 0x02, 0x98, 0xC0, 0x19, + 0x80, 0xB2, 0x06, 0x90, 0x30, 0x0A, 0x66, 0x49, 0x08, 0x31, 0xC9, 0x5D, + 0x09, 0x06, 0x08, 0x43, 0x06, 0x46, 0x06, 0x9C, 0x61, 0x48, 0xC7, 0x81, + 0x60, 0x49, 0x06, 0x98, 0x08, 0x80, 0x30, 0x0C, 0xC8, 0x80, 0x8E, 0x80, + 0x06, 0x98, 0xC0, 0x13, 0x00, 0x28, 0x03, 0xD1, 0x89, 0x13, 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0x00, 0x20, 0x00, 0x90, 0x31, 0x48, 0x00, 0x8A, + 0x08, 0x21, 0x88, 0x43, 0x2F, 0x49, 0x08, 0x82, 0x00, 0x98, 0x00, 0x28, + 0x20, 0xD1, 0x31, 0x48, 0x20, 0x30, 0x00, 0x89, 0x20, 0x21, 0x88, 0x43, + 0x2E, 0x49, 0x20, 0x31, 0x08, 0x81, 0x08, 0x46, 0x00, 0x89, 0x04, 0x21, + 0x08, 0x43, 0x2B, 0x49, 0x20, 0x31, 0x08, 0x81, 0x31, 0x0E, 0x20, 0x46, + 0xFF, 0xF7, 0x04, 0xFF, 0x00, 0x28, 0x08, 0xD1, 0x20, 0x78, 0x04, 0x90, + 0x31, 0x0E, 0x04, 0x98, 0x81, 0x42, 0x2A, 0xD0, 0x68, 0x1C, 0x85, 0xB2, + 0x27, 0xE0, 0x68, 0x1C, 0x85, 0xB2, 0x24, 0xE0, 0xA0, 0x07, 0x80, 0x0F, + 0x03, 0x28, 0x20, 0xD1, 0x1E, 0x48, 0x20, 0x30, 0x00, 0x89, 0x20, 0x21, + 0x08, 0x43, 0x1C, 0x49, 0x20, 0x31, 0x08, 0x81, 0x08, 0x46, 0x00, 0x89, + 0x04, 0x21, 0x08, 0x43, 0x18, 0x49, 0x20, 0x31, 0x08, 0x81, 0xA0, 0x10, + 0x31, 0x46, 0xFF, 0xF7, 0xC3, 0xFE, 0x00, 0x28, 0x09, 0xD1, 0xA0, 0x10, + 0x80, 0x00, 0x00, 0x68, 0x04, 0x90, 0x04, 0x98, 0xB0, 0x42, 0x04, 0xD0, + 0x28, 0x1D, 0x85, 0xB2, 0x01, 0xE0, 0x28, 0x1D, 0x85, 0xB2, 0x0A, 0x48, + 0x85, 0x81, 0x78, 0x1C, 0x87, 0xB2, 0x01, 0x98, 0x87, 0x42, 0x00, 0xDA, + 0x3C, 0xE7, 0x06, 0xE0, 0x06, 0x48, 0x80, 0x88, 0x40, 0x19, 0x85, 0xB2, + 0x01, 0x20, 0xC0, 0x03, 0x05, 0x43, 0x28, 0x46, 0x09, 0xB0, 0xF0, 0xBD, + 0x00, 0x70, 0x00, 0x40, 0x00, 0x05, 0x00, 0x20, 0x00, 0x04, 0x00, 0x20, + 0xB7, 0x1D, 0xC1, 0x04, 0x40, 0x30, 0x00, 0x40, 0x00, 0x5C, 0x00, 0x40, + 0xFF, 0x1F, 0x00, 0x00, 0xFC, 0xFF, 0x00, 0x00, 0x0C, 0xB5, 0x00, 0x21, + 0x01, 0x91, 0x10, 0xE0, 0x00, 0x21, 0x00, 0x91, 0x04, 0xE0, 0x69, 0x46, + 0x09, 0x88, 0x49, 0x1C, 0x8A, 0xB2, 0x00, 0x92, 0x69, 0x46, 0x09, 0x88, + 0x02, 0x29, 0xF6, 0xDB, 0x69, 0x46, 0x89, 0x88, 0x49, 0x1C, 0x8A, 0xB2, + 0x01, 0x92, 0x69, 0x46, 0x89, 0x88, 0x81, 0x42, 0xEA, 0xDB, 0x0C, 0xBD, + 0x5A, 0x20, 0x53, 0x49, 0x08, 0x80, 0x05, 0x20, 0x88, 0x80, 0x04, 0x20, + 0x08, 0x81, 0x51, 0x48, 0x88, 0x81, 0x50, 0x20, 0xFF, 0xF7, 0xDA, 0xFF, + 0x4F, 0x48, 0x4D, 0x49, 0x88, 0x82, 0x4F, 0x48, 0x08, 0x82, 0x18, 0x20, + 0x88, 0x83, 0x08, 0x46, 0x00, 0x8B, 0x17, 0x21, 0x49, 0x02, 0x08, 0x43, + 0x47, 0x49, 0x08, 0x83, 0x08, 0x46, 0x00, 0x8B, 0x2E, 0x21, 0x08, 0x43, + 0x44, 0x49, 0x08, 0x83, 0x05, 0x20, 0xFF, 0xF7, 0xC3, 0xFF, 0x42, 0x48, + 0x80, 0x8B, 0x01, 0x21, 0x08, 0x43, 0x40, 0x49, 0x88, 0x83, 0x32, 0x20, + 0x42, 0x49, 0x08, 0x80, 0x94, 0x20, 0x42, 0x49, 0x08, 0x80, 0x15, 0x20, + 0x08, 0x80, 0x08, 0x46, 0x80, 0x8A, 0x60, 0x21, 0x88, 0x43, 0x3E, 0x49, + 0x88, 0x82, 0x00, 0x20, 0x3D, 0x49, 0x08, 0x80, 0x3D, 0x49, 0x08, 0x80, + 0x48, 0x80, 0x00, 0x24, 0x00, 0x27, 0x01, 0x25, 0x00, 0x26, 0x06, 0xE0, + 0x00, 0x20, 0x71, 0x00, 0x39, 0x4A, 0x89, 0x18, 0x08, 0x80, 0x70, 0x1C, + 0x86, 0xB2, 0x10, 0x2E, 0xF6, 0xDB, 0x5A, 0xE0, 0x34, 0x48, 0x00, 0x88, + 0xC0, 0x07, 0xC0, 0x0F, 0x00, 0x28, 0x54, 0xD0, 0x31, 0x48, 0x00, 0x88, + 0xC0, 0xB2, 0x30, 0x49, 0x08, 0x80, 0x5A, 0x20, 0x30, 0x49, 0x08, 0x82, + 0x00, 0x20, 0x26, 0x49, 0x60, 0x31, 0x08, 0x80, 0x2B, 0x48, 0x00, 0x88, + 0x11, 0x21, 0x08, 0x40, 0x01, 0x28, 0x27, 0xD1, 0x01, 0x25, 0x28, 0x48, + 0x00, 0x88, 0xC0, 0xB2, 0x29, 0x02, 0x08, 0x43, 0x25, 0x49, 0x08, 0x80, + 0x25, 0x48, 0x00, 0x8A, 0x01, 0x21, 0x08, 0x43, 0x23, 0x49, 0x08, 0x82, + 0x00, 0x20, 0xFF, 0xF7, 0x3A, 0xFE, 0x04, 0x46, 0x20, 0x48, 0x00, 0x8A, + 0xA8, 0x43, 0x1F, 0x49, 0x08, 0x82, 0x60, 0x04, 0x40, 0x0C, 0xC0, 0x19, + 0x87, 0xB2, 0x88, 0x13, 0x20, 0x40, 0x00, 0x28, 0x01, 0xD0, 0x08, 0x20, + 0x04, 0xE0, 0x00, 0x2C, 0x01, 0xD0, 0x04, 0x20, 0x00, 0xE0, 0x02, 0x20, + 0x05, 0x46, 0x11, 0xE0, 0x01, 0x25, 0x14, 0x48, 0x00, 0x88, 0xC0, 0xB2, + 0x29, 0x02, 0x08, 0x43, 0x11, 0x49, 0x08, 0x80, 0x08, 0x88, 0xFF, 0xF7, + 0x41, 0xFD, 0x04, 0x46, 0x00, 0x2C, 0x01, 0xD0, 0x08, 0x20, 0x00, 0xE0, + 0x02, 0x20, 0x05, 0x46, 0x0B, 0x48, 0x47, 0x80, 0x00, 0x88, 0xFE, 0x21, + 0x08, 0x40, 0x29, 0x02, 0x08, 0x43, 0x08, 0x49, 0x08, 0x80, 0xA3, 0xE7, + 0x00, 0x30, 0x00, 0x40, 0x01, 0x04, 0x00, 0x00, 0x0A, 0x20, 0x00, 0x00, + 0xFF, 0x07, 0x00, 0x00, 0x40, 0x54, 0x00, 0x40, 0x00, 0x58, 0x00, 0x40, + 0x40, 0x6C, 0x00, 0x40, 0x00, 0x04, 0x00, 0x20, 0x00, 0x05, 0x00, 0x20, + 0x40, 0x5C, 0x00, 0x40, 0x70, 0x47, 0x70, 0x47, 0x70, 0x47, 0x75, 0x46, + 0x00, 0xF0, 0x24, 0xF8, 0xAE, 0x46, 0x05, 0x00, 0x69, 0x46, 0x53, 0x46, + 0xC0, 0x08, 0xC0, 0x00, 0x85, 0x46, 0x18, 0xB0, 0x20, 0xB5, 0xFF, 0xF7, + 0xFD, 0xFC, 0x60, 0xBC, 0x00, 0x27, 0x49, 0x08, 0xB6, 0x46, 0x00, 0x26, + 0xC0, 0xC5, 0xC0, 0xC5, 0xC0, 0xC5, 0xC0, 0xC5, 0xC0, 0xC5, 0xC0, 0xC5, + 0xC0, 0xC5, 0xC0, 0xC5, 0x40, 0x3D, 0x49, 0x00, 0x8D, 0x46, 0x70, 0x47, + 0x10, 0xB5, 0x04, 0x46, 0xC0, 0x46, 0xC0, 0x46, 0x20, 0x46, 0xFF, 0xF7, + 0xD8, 0xFC, 0x10, 0xBD, 0x00, 0x48, 0x70, 0x47, 0x00, 0x00, 0x00, 0x20, + 0x01, 0x49, 0x18, 0x20, 0xAB, 0xBE, 0xFE, 0xE7, 0x26, 0x00, 0x02, 0x00, + 0x70, 0x47, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, + 0x60, 0x01, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00 +}; + +#endif + +extern uint32_t get_hw_version_major(void); + +#endif diff --git a/drivers/power/supply/renesas/idtp9418_fw.h b/drivers/power/supply/renesas/idtp9418_fw.h new file mode 100644 index 000000000000..a0c68039ec8b --- /dev/null +++ b/drivers/power/supply/renesas/idtp9418_fw.h @@ -0,0 +1,3083 @@ +/** +* @file./release/P9418_xiaomi_v2.8.0.c.h +* @author +* @date2021-07-3 +* @customerXiaomi +* @brief +* +*/ + +unsigned char idt_firmware[] = { + 0x00, 0x08, 0x00, 0x20, 0xff, 0x03, 0x00, 0x00, + 0x71, 0x00, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, /// 0x10 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /// 0x20 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, /// 0x30 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /// 0x40 + 0x5d, 0x13, 0x00, 0x00, 0x63, 0x13, 0x00, 0x00, + 0x69, 0x13, 0x00, 0x00, 0x6f, 0x13, 0x00, 0x00, /// 0x50 + 0x75, 0x13, 0x00, 0x00, 0x7b, 0x13, 0x00, 0x00, + 0x81, 0x13, 0x00, 0x00, 0x87, 0x13, 0x00, 0x00, /// 0x60 + 0x8d, 0x13, 0x00, 0x00, 0x93, 0x13, 0x00, 0x00, + 0x99, 0x13, 0x00, 0x00, 0x9f, 0x13, 0x00, 0x00, /// 0x70 + 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, 0xfe, 0xe7, + 0xfe, 0xe7, 0x00, 0x20, 0x00, 0x68, 0x80, 0xf3, /// 0x80 + 0x08, 0x88, 0x70, 0x47, 0xf3, 0x48, 0x00, 0x21, + 0x01, 0x73, 0x41, 0x73, 0x70, 0x47, 0x10, 0xb5, /// 0x90 + 0xf0, 0x4b, 0x1a, 0x7b, 0x5c, 0x7b, 0x51, 0x1c, + 0x09, 0x07, 0x09, 0x0f, 0x8c, 0x42, 0x01, 0xd1, /// 0xa0 + 0x01, 0x20, 0x10, 0xbd, 0xec, 0x4c, 0x92, 0x00, + 0x12, 0x19, 0xff, 0x32, 0x01, 0x32, 0xd0, 0x60, /// 0xb0 + 0x19, 0x73, 0x00, 0x20, 0x10, 0xbd, 0xe8, 0x4e, + 0x34, 0x46, 0xff, 0x34, 0x41, 0x34, 0x21, 0x7b, /// 0xc0 + 0x60, 0x7b, 0x81, 0x42, 0x01, 0xd1, 0x30, 0xbf, + 0xf9, 0xe7, 0x81, 0x00, 0x89, 0x19, 0xff, 0x31, /// 0xd0 + 0x01, 0x31, 0xcd, 0x68, 0x00, 0x2d, 0x0c, 0xd0, + 0x40, 0x1c, 0x00, 0x07, 0x00, 0x0f, 0x60, 0x73, /// 0xe0 + 0xa8, 0x47, 0x00, 0x28, 0xeb, 0xd0, 0x72, 0xb6, + 0x28, 0x46, 0xff, 0xf7, 0xd0, 0xff, 0x62, 0xb6, /// 0xf0 + 0xe5, 0xe7, 0xff, 0xf7, 0xc7, 0xff, 0xe2, 0xe7, + 0x08, 0xb5, 0xd9, 0x49, 0xd7, 0x48, 0x08, 0x60, /// 0x100 + 0xff, 0xf7, 0xbb, 0xff, 0xd7, 0x4f, 0x5a, 0x20, + 0x38, 0x70, 0x00, 0x24, 0x3c, 0x71, 0x09, 0x20, /// 0x110 + 0x38, 0x72, 0xd5, 0x48, 0xb8, 0x81, 0xd4, 0x48, + 0xfb, 0x38, 0xb8, 0x82, 0xd3, 0x48, 0x38, 0x83, /// 0x120 + 0xb8, 0x8a, 0x79, 0x14, 0x08, 0x43, 0xb8, 0x82, + 0x01, 0x25, 0x3d, 0x82, 0x4d, 0x20, 0x00, 0x01, /// 0x130 + 0xb8, 0x83, 0x14, 0x20, 0x00, 0xf0, 0x78, 0xfc, + 0xb8, 0x8b, 0x08, 0x26, 0x30, 0x43, 0xb8, 0x83, /// 0x140 + 0x14, 0x20, 0x00, 0xf0, 0x71, 0xfc, 0xb8, 0x8b, + 0x28, 0x43, 0xb8, 0x83, 0x14, 0x20, 0x00, 0xf0, /// 0x150 + 0x6b, 0xfc, 0xb8, 0x8b, 0xa8, 0x43, 0xb8, 0x83, + 0x14, 0x20, 0x00, 0xf0, 0x65, 0xfc, 0xb8, 0x8b, /// 0x160 + 0xb0, 0x43, 0xb8, 0x83, 0xbf, 0x49, 0x02, 0x20, + 0x20, 0x31, 0x08, 0x76, 0xc0, 0x48, 0x84, 0x80, /// 0x170 + 0xbf, 0x49, 0xc0, 0x48, 0x08, 0x80, 0x80, 0x20, + 0x88, 0x81, 0xbf, 0x49, 0x94, 0x20, 0x08, 0x70, /// 0x180 + 0x15, 0x20, 0x08, 0x70, 0xbc, 0x48, 0x20, 0x30, + 0x00, 0x7c, 0x02, 0x21, 0x08, 0x43, 0xba, 0x49, /// 0x190 + 0x20, 0x31, 0x08, 0x74, 0xb8, 0x48, 0x04, 0x70, + 0x39, 0x20, 0xb5, 0x49, 0x00, 0x02, 0x08, 0x82, /// 0x1a0 + 0xb6, 0x48, 0x05, 0x80, 0xb5, 0x49, 0x81, 0x20, + 0x08, 0x80, 0xac, 0x49, 0xb3, 0x48, 0x20, 0x31, /// 0x1b0 + 0x20, 0x30, 0x01, 0x80, 0xb2, 0x48, 0xb1, 0x49, + 0x80, 0x78, 0x28, 0x43, 0x20, 0x31, 0x08, 0x71, /// 0x1c0 + 0xb0, 0x48, 0x85, 0x83, 0x09, 0x88, 0xc2, 0x13, + 0x11, 0x43, 0xac, 0x4a, 0x20, 0x32, 0x11, 0x80, /// 0x1d0 + 0x03, 0x27, 0x57, 0x71, 0xac, 0x49, 0x0d, 0x74, + 0x8e, 0x82, 0xa2, 0x49, 0x40, 0x31, 0x09, 0x8a, /// 0x1e0 + 0x02, 0x15, 0x11, 0x43, 0x9f, 0x4a, 0x40, 0x32, + 0x11, 0x82, 0xa6, 0x4a, 0x40, 0x21, 0x40, 0x3a, /// 0x1f0 + 0x11, 0x72, 0x11, 0x73, 0x11, 0x74, 0x20, 0x21, + 0x11, 0x76, 0xa2, 0x4a, 0x20, 0x3a, 0x11, 0x70, /// 0x200 + 0x80, 0x21, 0x11, 0x71, 0xa1, 0x4a, 0xa5, 0x21, + 0x11, 0x80, 0x11, 0x89, 0x82, 0x15, 0x11, 0x43, /// 0x210 + 0x9e, 0x4a, 0x11, 0x81, 0x14, 0x80, 0x04, 0x83, + 0x9a, 0x49, 0x20, 0x20, 0x20, 0x39, 0x08, 0x72, /// 0x220 + 0x9b, 0x48, 0x6a, 0x21, 0x01, 0x77, 0x9b, 0x48, + 0x81, 0xb2, 0x9b, 0x48, 0x00, 0xf0, 0x72, 0xfc, /// 0x230 + 0x30, 0x22, 0x9a, 0x49, 0x9a, 0x48, 0x00, 0xf0, + 0x5d, 0xfc, 0x91, 0x49, 0x86, 0x48, 0x10, 0x22, /// 0x240 + 0x50, 0x39, 0x48, 0x30, 0x00, 0xf0, 0x5d, 0xfc, + 0x8d, 0x49, 0x83, 0x48, 0x10, 0x22, 0x30, 0x31, /// 0x250 + 0x58, 0x30, 0x00, 0xf0, 0x56, 0xfc, 0x93, 0x48, + 0x1f, 0x21, 0x00, 0x90, 0x81, 0x72, 0x06, 0x46, /// 0x260 + 0xc7, 0x73, 0x20, 0x36, 0x4b, 0x20, 0x34, 0x77, + 0x00, 0x01, 0x00, 0xf0, 0xdd, 0xfb, 0x8e, 0x48, /// 0x270 + 0x05, 0x70, 0x8d, 0x49, 0x81, 0x20, 0x08, 0x70, + 0x3b, 0x20, 0x08, 0x71, 0x3f, 0x20, 0x08, 0x81, /// 0x280 + 0x21, 0x20, 0x08, 0x70, 0x00, 0xf0, 0x55, 0xfc, + 0x00, 0xf0, 0x23, 0xfc, 0x87, 0x49, 0x06, 0x20, /// 0x290 + 0x08, 0x60, 0x73, 0x49, 0x80, 0x39, 0x08, 0x60, + 0x85, 0x48, 0x05, 0x80, 0x07, 0x80, 0x41, 0x21, /// 0x2a0 + 0x01, 0x76, 0x84, 0x48, 0x00, 0xf0, 0x69, 0xf9, + 0x83, 0x48, 0x04, 0x71, 0x83, 0x48, 0x44, 0x73, /// 0x2b0 + 0x00, 0xf0, 0xb5, 0xff, 0x37, 0x46, 0x80, 0x3f, + 0x78, 0x73, 0x00, 0xf0, 0xaf, 0xfb, 0x7e, 0x48, /// 0x2c0 + 0x01, 0x7a, 0x89, 0x07, 0xfc, 0xd5, 0x7c, 0x49, + 0x00, 0x24, 0x20, 0x31, 0x0c, 0x70, 0x02, 0x21, /// 0x2d0 + 0x01, 0x72, 0x60, 0x49, 0x10, 0x22, 0x58, 0x31, + 0x88, 0x18, 0x00, 0xf0, 0x0b, 0xfc, 0x0f, 0x22, /// 0x2e0 + 0x01, 0x21, 0x00, 0x20, 0x00, 0xf0, 0x31, 0xf9, + 0x40, 0x03, 0x01, 0x0c, 0x6d, 0x48, 0x5a, 0x4d, /// 0x2f0 + 0x20, 0x38, 0x81, 0x85, 0x96, 0x20, 0x68, 0x86, + 0x51, 0x21, 0xa9, 0x86, 0x30, 0x82, 0x71, 0x82, /// 0x300 + 0x05, 0xf0, 0x78, 0xfa, 0x00, 0xf0, 0x95, 0xfb, + 0x5b, 0x49, 0x60, 0x31, 0x0a, 0x7d, 0x65, 0x48, /// 0x310 + 0xa0, 0x38, 0x02, 0x70, 0x0a, 0x7c, 0x42, 0x70, + 0x09, 0x7e, 0x81, 0x70, 0x02, 0x21, 0xc1, 0x70, /// 0x320 + 0xff, 0x21, 0x02, 0x31, 0x41, 0x60, 0x66, 0x49, + 0xc1, 0x61, 0x04, 0x72, 0x12, 0x21, 0xb9, 0x72, /// 0x330 + 0x01, 0x46, 0x01, 0x22, 0x60, 0x31, 0x8a, 0x70, + 0x28, 0x23, 0x80, 0x31, 0x4b, 0x76, 0xbc, 0x70, /// 0x340 + 0x74, 0x83, 0x4a, 0x74, 0x5f, 0x21, 0x69, 0x76, + 0x05, 0x21, 0xa9, 0x76, 0x6c, 0x21, 0xe9, 0x76, /// 0x350 + 0x5c, 0x49, 0xec, 0x61, 0x29, 0x62, 0x29, 0x46, + 0x5b, 0x4a, 0x40, 0x31, 0x0a, 0x80, 0x80, 0x78, /// 0x360 + 0x05, 0x28, 0x47, 0x48, 0x04, 0xd3, 0x81, 0x78, + 0x44, 0x48, 0x20, 0x30, 0x01, 0x71, 0x05, 0xe0, /// 0x370 + 0x80, 0x78, 0x01, 0x21, 0x08, 0x43, 0x41, 0x49, + 0x20, 0x31, 0x08, 0x71, 0x00, 0xf0, 0x6e, 0xff, /// 0x380 + 0x00, 0x99, 0x3f, 0x4d, 0x88, 0x73, 0xa8, 0x8b, + 0x50, 0x4e, 0xb0, 0x42, 0x01, 0xd0, 0x00, 0xf0, /// 0x390 + 0x75, 0xff, 0x68, 0x8b, 0xb0, 0x42, 0x01, 0xd0, + 0x00, 0xf0, 0x81, 0xff, 0x00, 0xf0, 0x91, 0xff, /// 0x3a0 + 0x2e, 0x49, 0x46, 0x48, 0xf5, 0x31, 0x40, 0x30, + 0x01, 0x85, 0x01, 0x46, 0x20, 0x31, 0x2b, 0x4a, /// 0x3b0 + 0x0c, 0x73, 0x9c, 0x3a, 0x42, 0x85, 0x2b, 0x20, + 0x48, 0x73, 0x45, 0x48, 0x01, 0x21, 0x01, 0x80, /// 0x3c0 + 0x33, 0x48, 0x01, 0x70, 0x81, 0x21, 0x01, 0x70, + 0x0d, 0x21, 0x01, 0x70, 0x30, 0x4a, 0x95, 0x21, /// 0x3d0 + 0x20, 0x32, 0x11, 0x80, 0xff, 0x21, 0x81, 0x82, + 0x03, 0x21, 0x09, 0x02, 0x01, 0x82, 0x04, 0x71, /// 0x3e0 + 0x32, 0x49, 0x61, 0x20, 0x08, 0x60, 0x1e, 0x49, + 0x80, 0x39, 0x08, 0x60, 0x2d, 0x48, 0x39, 0x49, /// 0x3f0 + 0xa0, 0x38, 0x41, 0x63, 0x2a, 0x49, 0x38, 0x48, + 0x48, 0x60, 0xff, 0xf7, 0x5c, 0xfe, 0x08, 0x20, /// 0x400 + 0x00, 0xf0, 0x12, 0xfb, 0x17, 0x48, 0x40, 0x30, + 0x01, 0x78, 0x49, 0x06, 0xfc, 0xd4, 0xff, 0xf7, /// 0x410 + 0x73, 0xfe, 0x10, 0x48, 0x10, 0xb5, 0x40, 0x38, + 0x41, 0x68, 0x22, 0x4c, 0x49, 0x1c, 0x20, 0x3c, /// 0x420 + 0x41, 0x60, 0x21, 0x78, 0x89, 0x07, 0x04, 0xd4, + 0x72, 0xb6, 0x80, 0x68, 0xff, 0xf7, 0x2f, 0xfe, /// 0x430 + 0x62, 0xb6, 0x20, 0x78, 0x00, 0x07, 0x03, 0xd5, + 0x07, 0x48, 0xc1, 0x69, 0x49, 0x1c, 0xc1, 0x61, /// 0x440 + 0x72, 0xb6, 0x04, 0x48, 0x40, 0x30, 0x00, 0x68, + 0xff, 0xf7, 0x21, 0xfe, 0x62, 0xb6, 0x00, 0x20, /// 0x450 + 0x10, 0xbd, 0x00, 0x00, 0x70, 0x02, 0x00, 0x20, + 0x30, 0x01, 0x00, 0x20, 0xff, 0x0f, 0x00, 0x00, /// 0x460 + 0x80, 0xe1, 0x00, 0xe0, 0x00, 0x30, 0x00, 0x40, + 0x05, 0x1d, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00, /// 0x470 + 0x00, 0x34, 0x00, 0x40, 0xf9, 0x09, 0x00, 0x00, + 0x00, 0x58, 0x00, 0x40, 0x00, 0x38, 0x00, 0x40, /// 0x480 + 0x60, 0x67, 0x00, 0x00, 0x40, 0x6c, 0x00, 0x40, + 0x60, 0x40, 0x00, 0x40, 0x00, 0x74, 0x00, 0x40, /// 0x490 + 0x00, 0x64, 0x00, 0x40, 0x0c, 0x05, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x20, 0x40, 0x1a, 0x00, 0x00, /// 0x4a0 + 0x00, 0x01, 0x00, 0x20, 0xa0, 0x00, 0x00, 0x20, + 0x00, 0x3c, 0x00, 0x40, 0x80, 0xe2, 0x00, 0xe0, /// 0x4b0 + 0x00, 0x44, 0x00, 0x40, 0x38, 0x1a, 0x00, 0x00, + 0x00, 0x60, 0x00, 0x40, 0x70, 0x03, 0x00, 0x20, /// 0x4c0 + 0x0c, 0x00, 0x08, 0x02, 0x20, 0xbf, 0x02, 0x00, + 0xe4, 0x0c, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, /// 0x4d0 + 0x00, 0x48, 0x00, 0x40, 0x07, 0x40, 0x70, 0x00, + 0x53, 0x15, 0x00, 0x00, 0x70, 0xb5, 0xfe, 0x49, /// 0x4e0 + 0x8a, 0x88, 0xd2, 0x43, 0x92, 0x07, 0x07, 0xd0, + 0xfc, 0x4a, 0xfd, 0x4b, 0xd2, 0x8f, 0x9a, 0x42, /// 0x4f0 + 0x02, 0xd3, 0x40, 0x09, 0x00, 0x23, 0x03, 0xe0, + 0x82, 0x00, 0x80, 0x18, 0xc0, 0x09, 0x01, 0x23, /// 0x500 + 0x3c, 0x28, 0x01, 0xd2, 0x3c, 0x20, 0x02, 0xe0, + 0xff, 0x28, 0x00, 0xd9, 0xff, 0x20, 0x0a, 0x8a, /// 0x510 + 0xf4, 0x4c, 0x12, 0x0a, 0xc0, 0x1e, 0x82, 0x42, + 0x15, 0xd0, 0x00, 0x2b, 0x02, 0xd1, 0x25, 0x7b, /// 0x520 + 0x01, 0x2d, 0x03, 0xd0, 0x55, 0x1d, 0xa8, 0x42, + 0x00, 0xd9, 0x28, 0x46, 0x0a, 0x8a, 0x40, 0x25, /// 0x530 + 0x2a, 0x43, 0x0a, 0x82, 0x0a, 0x8a, 0x4f, 0x26, + 0x32, 0x40, 0x00, 0x02, 0x02, 0x43, 0x0a, 0x82, /// 0x540 + 0x08, 0x8a, 0xa8, 0x43, 0x08, 0x82, 0x23, 0x73, + 0x70, 0xbd, 0x70, 0xb5, 0x00, 0x23, 0x12, 0x07, /// 0x550 + 0x12, 0x0f, 0xe5, 0x4d, 0x0b, 0xe0, 0x44, 0x00, + 0x64, 0x19, 0xff, 0x34, 0x81, 0x34, 0x24, 0x8d, /// 0x560 + 0x26, 0x0b, 0x96, 0x42, 0x07, 0xd1, 0x24, 0x05, + 0x24, 0x0d, 0xe3, 0x18, 0x40, 0x18, 0x08, 0x28, /// 0x570 + 0xf1, 0xd3, 0x18, 0x46, 0x70, 0xbd, 0xdd, 0x48, + 0x70, 0xbd, 0x10, 0xb5, 0xdc, 0x4a, 0x00, 0x21, /// 0x580 + 0x11, 0x70, 0xd8, 0x4b, 0x01, 0x21, 0x40, 0x3b, + 0x59, 0x73, 0xda, 0x49, 0x03, 0x88, 0x8b, 0x80, /// 0x590 + 0x43, 0x88, 0x0b, 0x81, 0x83, 0x88, 0x8b, 0x81, + 0xc0, 0x88, 0x08, 0x82, 0xb4, 0x20, 0x10, 0x70, /// 0x5a0 + 0xd0, 0x48, 0xe8, 0x38, 0x10, 0x81, 0x07, 0x20, + 0x90, 0x80, 0xd1, 0x48, 0x02, 0x22, 0x20, 0x38, /// 0x5b0 + 0x02, 0x72, 0x03, 0x79, 0x72, 0xb6, 0x13, 0x43, + 0x03, 0x71, 0x62, 0xb6, 0x11, 0x20, 0x08, 0x80, /// 0x5c0 + 0x10, 0xbd, 0x01, 0x88, 0x42, 0x88, 0x51, 0x18, + 0x82, 0x88, 0xc0, 0x88, 0x51, 0x18, 0x40, 0x18, /// 0x5d0 + 0xc9, 0x49, 0x00, 0x22, 0x8a, 0x5e, 0x80, 0x10, + 0x80, 0x1a, 0x00, 0xd5, 0x00, 0x20, 0x70, 0x47, /// 0x5e0 + 0x01, 0x88, 0x42, 0x88, 0x51, 0x18, 0x82, 0x88, + 0xc0, 0x88, 0x51, 0x18, 0x40, 0x18, 0x80, 0x10, /// 0x5f0 + 0x00, 0xd5, 0x00, 0x20, 0x70, 0x47, 0xf8, 0xb5, + 0x09, 0x22, 0x04, 0x21, 0x00, 0x20, 0xff, 0xf7, /// 0x600 + 0xa4, 0xff, 0xb8, 0x4e, 0xb8, 0x4d, 0x20, 0x3e, + 0xb1, 0x7c, 0x09, 0x27, 0x49, 0x00, 0xc0, 0x03, /// 0x610 + 0x49, 0x19, 0xbf, 0x01, 0x00, 0x0c, 0xc9, 0x19, + 0x08, 0x83, 0x00, 0x22, 0x04, 0x21, 0x01, 0x20, /// 0x620 + 0xff, 0xf7, 0x93, 0xff, 0xb1, 0x7c, 0xc0, 0x03, + 0x49, 0x00, 0x49, 0x19, 0x00, 0x0c, 0xc9, 0x19, /// 0x630 + 0x08, 0x85, 0x02, 0x22, 0x08, 0x21, 0x03, 0x20, + 0xff, 0xf7, 0x87, 0xff, 0xb1, 0x7c, 0x03, 0x22, /// 0x640 + 0x49, 0x00, 0x49, 0x19, 0xc9, 0x19, 0x08, 0x84, + 0x04, 0x21, 0x02, 0x20, 0xff, 0xf7, 0x7d, 0xff, /// 0x650 + 0xb1, 0x7c, 0x05, 0x22, 0x49, 0x00, 0xc0, 0x03, + 0x49, 0x19, 0xd2, 0x01, 0x00, 0x0c, 0x89, 0x18, /// 0x660 + 0x9e, 0x4c, 0x88, 0x82, 0xa0, 0x69, 0x41, 0x00, + 0x60, 0x69, 0xc2, 0x0f, 0x11, 0x43, 0xa1, 0x61, /// 0x670 + 0x41, 0x00, 0xb0, 0x7c, 0x42, 0x00, 0x52, 0x19, + 0xd2, 0x19, 0x12, 0x7e, 0x40, 0x1c, 0xd2, 0x07, /// 0x680 + 0xd2, 0x0f, 0x11, 0x43, 0x80, 0x07, 0x80, 0x0f, + 0x61, 0x61, 0xb0, 0x74, 0x30, 0x46, 0x08, 0x38, /// 0x690 + 0xff, 0xf7, 0x97, 0xff, 0x25, 0x46, 0x98, 0x49, + 0x80, 0xb2, 0x40, 0x35, 0x28, 0x80, 0x40, 0x31, /// 0x6a0 + 0x49, 0x8b, 0x92, 0x4f, 0xb9, 0x42, 0x0a, 0xd0, + 0x94, 0x49, 0x0a, 0x68, 0x49, 0x68, 0x50, 0x43, /// 0x6b0 + 0x40, 0x18, 0x00, 0x13, 0x00, 0xb2, 0x00, 0x28, + 0x00, 0xda, 0x00, 0x20, 0x28, 0x80, 0xa0, 0x78, /// 0x6c0 + 0x05, 0x28, 0x06, 0xd3, 0x28, 0x88, 0x3b, 0x21, + 0x48, 0x43, 0x32, 0x21, 0x01, 0xf0, 0x7c, 0xf9, /// 0x6d0 + 0x28, 0x80, 0x84, 0x48, 0x18, 0x38, 0xff, 0xf7, + 0x83, 0xff, 0x80, 0xb2, 0x4b, 0x21, 0xc9, 0x00, /// 0x6e0 + 0x68, 0x87, 0x88, 0x42, 0x04, 0xd9, 0x7f, 0x48, + 0x14, 0x30, 0xff, 0xf7, 0x79, 0xff, 0x68, 0x87, /// 0x6f0 + 0x81, 0x48, 0x40, 0x30, 0x80, 0x8b, 0xb8, 0x42, + 0x30, 0x46, 0x27, 0xd0, 0xff, 0xf7, 0x70, 0xff, /// 0x700 + 0x80, 0xb2, 0x78, 0x49, 0xa0, 0x87, 0x0a, 0x6a, + 0x49, 0x6a, 0x50, 0x43, 0x40, 0x18, 0x00, 0x13, /// 0x710 + 0x00, 0xb2, 0x00, 0x28, 0x00, 0xda, 0x00, 0x20, + 0x73, 0x4d, 0xa0, 0x87, 0xa4, 0x8f, 0x68, 0x6a, /// 0x720 + 0x2f, 0x46, 0x00, 0x19, 0x20, 0x37, 0x68, 0x62, + 0x79, 0x7a, 0x49, 0x1c, 0xc9, 0xb2, 0x79, 0x72, /// 0x730 + 0x3e, 0x7a, 0xb1, 0x42, 0x06, 0xd1, 0x31, 0x46, + 0x01, 0xf0, 0x46, 0xf9, 0x68, 0x85, 0x00, 0x20, /// 0x740 + 0x78, 0x72, 0x68, 0x62, 0xe8, 0x6a, 0x00, 0x28, + 0x03, 0xd0, 0x05, 0xe0, 0xff, 0xf7, 0x39, 0xff, /// 0x750 + 0xe2, 0xe7, 0x20, 0x46, 0x70, 0x43, 0xe8, 0x62, + 0x07, 0x46, 0x31, 0x46, 0x01, 0xf0, 0x34, 0xf9, /// 0x760 + 0x38, 0x1a, 0x00, 0x19, 0x31, 0x46, 0xe8, 0x62, + 0x01, 0xf0, 0x2e, 0xf9, 0x28, 0x86, 0xff, 0x22, /// 0x770 + 0x01, 0x21, 0x25, 0x32, 0x49, 0x03, 0x62, 0x48, + 0x94, 0x42, 0x02, 0xd9, 0x82, 0x8b, 0xd2, 0x07, /// 0x780 + 0x04, 0xd0, 0x82, 0x8a, 0x8a, 0x43, 0x82, 0x82, + 0x00, 0x20, 0xf8, 0xbd, 0x82, 0x8a, 0x0a, 0x43, /// 0x790 + 0xf9, 0xe7, 0x30, 0xb5, 0x52, 0x4c, 0x5b, 0x49, + 0x5c, 0x34, 0x5b, 0x4a, 0x03, 0x46, 0xa0, 0x42, /// 0x7a0 + 0x31, 0xdb, 0x4f, 0x4c, 0x9c, 0x34, 0xa0, 0x42, + 0x0c, 0xda, 0x58, 0x48, 0x2d, 0x25, 0x18, 0x18, /// 0x7b0 + 0x04, 0x46, 0x68, 0x43, 0xc5, 0x17, 0xad, 0x0e, + 0x28, 0x18, 0x80, 0x11, 0x41, 0x18, 0x20, 0x46, /// 0x7c0 + 0x53, 0x4c, 0x16, 0xe0, 0x53, 0x4c, 0x3f, 0x21, + 0x89, 0x01, 0x53, 0x4a, 0xa0, 0x42, 0x1a, 0xdb, /// 0x7d0 + 0x50, 0x4c, 0x40, 0x34, 0xa3, 0x42, 0x13, 0xda, + 0x4e, 0x48, 0xa3, 0x25, 0x40, 0x42, 0x18, 0x18, /// 0x7e0 + 0x04, 0x46, 0x68, 0x43, 0xc5, 0x17, 0xad, 0x0e, + 0x28, 0x18, 0x80, 0x11, 0x41, 0x18, 0x20, 0x46, /// 0x7f0 + 0x4a, 0x4c, 0x60, 0x43, 0xc4, 0x17, 0xa4, 0x0e, + 0x20, 0x18, 0x80, 0x11, 0x82, 0x18, 0x02, 0xe0, /// 0x800 + 0x40, 0x49, 0x47, 0x4a, 0xd0, 0x31, 0x4b, 0x43, + 0x98, 0x1a, 0x00, 0x13, 0x00, 0xb2, 0x00, 0x28, /// 0x810 + 0x00, 0xda, 0x00, 0x20, 0x30, 0xbd, 0xff, 0x22, + 0x10, 0xb5, 0xe1, 0x32, 0x31, 0x49, 0x90, 0x42, /// 0x820 + 0x03, 0xd8, 0x06, 0x23, 0x8a, 0x88, 0xcb, 0x5e, + 0x07, 0xe0, 0xf7, 0x22, 0x92, 0x00, 0x90, 0x42, /// 0x830 + 0x00, 0xd9, 0x32, 0x49, 0x0a, 0x23, 0x0a, 0x89, + 0xcb, 0x5e, 0x50, 0x43, 0x80, 0x0a, 0xc0, 0x18, /// 0x840 + 0x40, 0x01, 0x19, 0x21, 0x01, 0xf0, 0xc0, 0xf8, + 0x00, 0xb2, 0x00, 0x28, 0x00, 0xda, 0x00, 0x20, /// 0x850 + 0x10, 0xbd, 0x10, 0xb5, 0xff, 0xf7, 0xdf, 0xff, + 0xff, 0xf7, 0x9b, 0xff, 0x10, 0xbd, 0xf8, 0xb5, /// 0x860 + 0x04, 0x22, 0x08, 0x21, 0x07, 0x20, 0xff, 0xf7, + 0x70, 0xfe, 0x20, 0x4e, 0x81, 0xb2, 0xb1, 0x42, /// 0x870 + 0x7e, 0xd0, 0x1a, 0x48, 0x40, 0x30, 0xc2, 0x88, + 0x13, 0x01, 0x9a, 0x1a, 0x51, 0x18, 0x09, 0x03, /// 0x880 + 0x09, 0x0c, 0xc1, 0x80, 0x09, 0x22, 0x04, 0x21, + 0x00, 0x20, 0xff, 0xf7, 0x5e, 0xfe, 0x80, 0xb2, /// 0x890 + 0xb0, 0x42, 0x6d, 0xd0, 0x11, 0x4c, 0x0e, 0x21, + 0xa0, 0x34, 0x61, 0x56, 0x40, 0x08, 0x40, 0x18, /// 0x8a0 + 0x27, 0x46, 0x80, 0xb2, 0x20, 0x37, 0x14, 0x4a, + 0x38, 0x84, 0x00, 0x21, 0x51, 0x5e, 0x88, 0x42, /// 0x8b0 + 0x01, 0xdb, 0x40, 0x1a, 0x00, 0xe0, 0x00, 0x20, + 0x80, 0xb2, 0x08, 0x4d, 0x38, 0x84, 0xa9, 0x78, /// 0x8c0 + 0x05, 0x29, 0x05, 0xd3, 0x3b, 0x21, 0x48, 0x43, + 0x32, 0x21, 0x01, 0xf0, 0x7d, 0xf8, 0x38, 0x84, /// 0x8d0 + 0x00, 0x22, 0x04, 0x21, 0x01, 0x20, 0x25, 0xe0, + 0x00, 0x34, 0x00, 0x40, 0x00, 0x00, 0x00, 0x20, /// 0x8e0 + 0xa6, 0x02, 0x00, 0x00, 0xb0, 0x03, 0x00, 0x20, + 0x30, 0x01, 0x00, 0x20, 0xff, 0xff, 0x00, 0x00, /// 0x8f0 + 0x20, 0x60, 0x00, 0x40, 0x00, 0x44, 0x00, 0x40, + 0x20, 0x67, 0x00, 0x00, 0x00, 0x05, 0x00, 0x20, /// 0x900 + 0x00, 0x30, 0x00, 0x40, 0x93, 0x0f, 0x00, 0x00, + 0xcb, 0x4f, 0x00, 0x00, 0xfe, 0xfc, 0xff, 0xff, /// 0x910 + 0x57, 0xf4, 0xff, 0xff, 0x7a, 0x08, 0x00, 0x00, + 0x22, 0x44, 0x00, 0x00, 0xe3, 0x7a, 0x05, 0x00, /// 0x920 + 0x05, 0xbf, 0x05, 0x00, 0xff, 0xf7, 0x11, 0xfe, + 0x80, 0xb2, 0xb0, 0x42, 0x3f, 0xd0, 0x4b, 0x21, /// 0x930 + 0x40, 0x08, 0xc9, 0x00, 0x88, 0x42, 0x08, 0xd9, + 0x03, 0x22, 0x04, 0x21, 0x02, 0x20, 0xff, 0xf7, /// 0x940 + 0x04, 0xfe, 0x80, 0xb2, 0xb0, 0x42, 0x32, 0xd0, + 0x40, 0x08, 0xff, 0xf7, 0x82, 0xff, 0xfd, 0x49, /// 0x950 + 0xfc, 0x4b, 0xc9, 0x8d, 0x01, 0x22, 0xc0, 0x3b, + 0x56, 0x00, 0xf6, 0x18, 0xc0, 0x36, 0xf6, 0x8d, /// 0x960 + 0x8e, 0x42, 0x00, 0xd9, 0x31, 0x46, 0x52, 0x1c, + 0xd2, 0xb2, 0x04, 0x2a, 0xf4, 0xd3, 0x00, 0xe0, /// 0x970 + 0x1d, 0xe0, 0xf4, 0x4a, 0x20, 0x32, 0x96, 0x7d, + 0x76, 0x00, 0xf3, 0x18, 0xc0, 0x33, 0xd8, 0x85, /// 0x980 + 0x93, 0x7d, 0x5b, 0x1c, 0x9b, 0x07, 0x9b, 0x0f, + 0x93, 0x75, 0x7d, 0x23, 0xdb, 0x00, 0xee, 0x4a, /// 0x990 + 0x98, 0x42, 0x0d, 0xd9, 0x93, 0x88, 0xdb, 0x43, + 0x9b, 0x07, 0x09, 0xd0, 0x03, 0x20, 0x90, 0x80, /// 0x9a0 + 0x10, 0x88, 0xf8, 0x21, 0x88, 0x43, 0x38, 0x21, + 0xc0, 0x30, 0x08, 0x43, 0x10, 0x80, 0xf8, 0xbd, /// 0x9b0 + 0xe6, 0x4b, 0x1b, 0x78, 0xdb, 0x06, 0xfa, 0xd5, + 0x93, 0x88, 0x00, 0x2b, 0xf7, 0xd0, 0x03, 0x46, /// 0x9c0 + 0xc8, 0x33, 0x99, 0x42, 0x01, 0xd9, 0x64, 0x28, + 0x05, 0xd3, 0x6b, 0x7a, 0x0a, 0x25, 0x6b, 0x43, /// 0x9d0 + 0x18, 0x18, 0x88, 0x42, 0xeb, 0xd2, 0x00, 0x20, + 0x90, 0x80, 0x08, 0x21, 0xdc, 0x48, 0xe1, 0x73, /// 0x9e0 + 0x41, 0x71, 0x01, 0x88, 0x82, 0x14, 0x11, 0x43, + 0x01, 0x80, 0xd6, 0x48, 0x32, 0x21, 0xc0, 0x30, /// 0x9f0 + 0x01, 0x67, 0x01, 0x46, 0x80, 0x39, 0x49, 0x68, + 0x42, 0x6e, 0x8a, 0x1a, 0x1e, 0x2a, 0xd6, 0xd3, /// 0xa00 + 0x1e, 0x39, 0x41, 0x66, 0xf8, 0xbd, 0xd3, 0x48, + 0x01, 0x78, 0x42, 0x22, 0x11, 0x43, 0x01, 0x70, /// 0xa10 + 0xd1, 0x49, 0xc0, 0x14, 0x08, 0x60, 0xd1, 0x49, + 0x08, 0x60, 0x70, 0x47, 0xd0, 0x48, 0x81, 0x21, /// 0xa20 + 0x01, 0x80, 0x00, 0x21, 0x01, 0x80, 0x70, 0x47, + 0x00, 0xe0, 0x00, 0xbf, 0x40, 0x1e, 0xfc, 0xd2, /// 0xa30 + 0x70, 0x47, 0x10, 0xb5, 0xc4, 0x4c, 0x00, 0x23, + 0xa3, 0x80, 0xc3, 0x48, 0x40, 0x30, 0x03, 0x74, /// 0xa40 + 0xc8, 0x48, 0x20, 0x80, 0xc9, 0x4a, 0xc8, 0x48, + 0x10, 0x82, 0x90, 0x8a, 0x51, 0x14, 0x08, 0x43, /// 0xa50 + 0x90, 0x82, 0xd8, 0x20, 0x90, 0x83, 0x64, 0x20, + 0xff, 0xf7, 0xe6, 0xff, 0xd0, 0x20, 0x90, 0x83, /// 0xa60 + 0x39, 0x20, 0x00, 0x02, 0x20, 0x82, 0xc2, 0x48, + 0x10, 0x83, 0xb9, 0x49, 0x81, 0x20, 0x20, 0x39, /// 0xa70 + 0x08, 0x80, 0xb6, 0x49, 0x1f, 0x20, 0x20, 0x31, + 0x88, 0x72, 0xb5, 0x48, 0xbd, 0x49, 0x01, 0x80, /// 0xa80 + 0xbd, 0x49, 0x01, 0x22, 0x89, 0x78, 0x11, 0x43, + 0x01, 0x71, 0xb2, 0x49, 0x09, 0x20, 0x08, 0x70, /// 0xa90 + 0xae, 0x48, 0x40, 0x30, 0x01, 0x7f, 0x91, 0x43, + 0xb8, 0x4a, 0x01, 0x77, 0x10, 0x78, 0x40, 0x08, /// 0xaa0 + 0x40, 0x00, 0x10, 0x70, 0xff, 0xf7, 0xba, 0xff, + 0xa6, 0x48, 0xb5, 0x49, 0x40, 0x30, 0x81, 0x60, /// 0xab0 + 0x11, 0x78, 0xfb, 0x24, 0x21, 0x40, 0x11, 0x70, + 0x41, 0x68, 0x80, 0x30, 0xc1, 0x66, 0xa3, 0x48, /// 0xac0 + 0x40, 0x22, 0x40, 0x38, 0x43, 0x73, 0x40, 0x38, + 0xc1, 0x6a, 0x91, 0x43, 0xc1, 0x62, 0x00, 0x20, /// 0xad0 + 0x10, 0xbd, 0xac, 0x48, 0x00, 0x21, 0x01, 0x75, + 0x41, 0x75, 0xa1, 0x48, 0x01, 0x21, 0x01, 0x80, /// 0xae0 + 0x01, 0x15, 0x81, 0x80, 0x0f, 0x21, 0x01, 0x80, + 0x02, 0x22, 0x02, 0x81, 0x01, 0x83, 0x04, 0x21, /// 0xaf0 + 0x81, 0x82, 0x70, 0x47, 0x82, 0x18, 0x01, 0xe0, + 0x08, 0xc9, 0x08, 0xc0, 0x90, 0x42, 0xfb, 0xd3, /// 0xb00 + 0x70, 0x47, 0x82, 0x18, 0x03, 0xe0, 0x0b, 0x78, + 0x03, 0x70, 0x40, 0x1c, 0x49, 0x1c, 0x90, 0x42, /// 0xb10 + 0xf9, 0xd3, 0x70, 0x47, 0x41, 0x18, 0x00, 0x22, + 0x00, 0xe0, 0x04, 0xc0, 0x88, 0x42, 0xfc, 0xd3, /// 0xb20 + 0x70, 0x47, 0x41, 0x18, 0x00, 0x22, 0x01, 0xe0, + 0x02, 0x70, 0x40, 0x1c, 0x88, 0x42, 0xfb, 0xd3, /// 0xb30 + 0x70, 0x47, 0x95, 0x48, 0x01, 0x21, 0x01, 0x70, + 0x93, 0x4a, 0x05, 0x21, 0x40, 0x32, 0x11, 0x80, /// 0xb40 + 0x00, 0x22, 0x02, 0x74, 0x90, 0x49, 0x20, 0x31, + 0x0a, 0x74, 0x90, 0x4a, 0x8a, 0x81, 0x13, 0x22, /// 0xb50 + 0x0a, 0x70, 0x07, 0x21, 0x01, 0x72, 0x70, 0x47, + 0x7c, 0x49, 0x80, 0x39, 0x0a, 0x6b, 0x02, 0x43, /// 0xb60 + 0x48, 0x6b, 0x10, 0x40, 0x08, 0x63, 0x05, 0xd0, + 0x84, 0x48, 0x20, 0x38, 0x01, 0x7f, 0xfb, 0x22, /// 0xb70 + 0x11, 0x40, 0x01, 0x77, 0x70, 0x47, 0x75, 0x48, + 0x80, 0x38, 0x82, 0x6a, 0xc1, 0x6a, 0x91, 0x43, /// 0xb80 + 0xc1, 0x62, 0x01, 0x6b, 0x91, 0x43, 0x00, 0x22, + 0x82, 0x62, 0x01, 0x63, 0x00, 0x29, 0x05, 0xd1, /// 0xb90 + 0x7a, 0x48, 0x20, 0x38, 0x01, 0x7f, 0x04, 0x22, + 0x11, 0x43, 0x01, 0x77, 0x70, 0x47, 0x6b, 0x49, /// 0xba0 + 0x10, 0xb5, 0x80, 0x39, 0xc9, 0x8f, 0x7a, 0x4a, + 0x91, 0x42, 0x01, 0xd9, 0x07, 0x21, 0x00, 0xe0, /// 0xbb0 + 0x00, 0x21, 0x6e, 0x4a, 0x13, 0x15, 0x94, 0x8b, + 0x02, 0x28, 0x01, 0xd8, 0x1c, 0x43, 0x00, 0xe0, /// 0xbc0 + 0x9c, 0x43, 0x94, 0x83, 0x61, 0x4c, 0x20, 0x34, + 0x01, 0x28, 0x01, 0xd9, 0x00, 0x20, 0x06, 0xe0, /// 0xbd0 + 0x01, 0x28, 0x10, 0xd0, 0x1c, 0x20, 0x40, 0x1a, + 0x07, 0x21, 0x00, 0xf0, 0x0b, 0xff, 0xe0, 0x73, /// 0xbe0 + 0xc1, 0xb2, 0x5b, 0x48, 0x41, 0x71, 0x42, 0x79, + 0x81, 0x14, 0x00, 0x2a, 0x02, 0x88, 0x04, 0xd0, /// 0xbf0 + 0x0a, 0x43, 0x02, 0x80, 0x10, 0xbd, 0x0e, 0x20, + 0xed, 0xe7, 0x8a, 0x43, 0xf9, 0xe7, 0x10, 0xb5, /// 0xc00 + 0x00, 0x20, 0xff, 0xf7, 0xcc, 0xff, 0x59, 0x4a, + 0x90, 0x8a, 0x51, 0x14, 0x08, 0x43, 0x90, 0x82, /// 0xc10 + 0x10, 0x8a, 0x01, 0x21, 0x08, 0x43, 0x10, 0x82, + 0xd8, 0x20, 0x90, 0x83, 0x64, 0x20, 0xff, 0xf7, /// 0xc20 + 0x03, 0xff, 0xd0, 0x20, 0x90, 0x83, 0x39, 0x20, + 0x47, 0x49, 0x00, 0x02, 0x08, 0x82, 0x00, 0x20, /// 0xc30 + 0x88, 0x80, 0x0a, 0x88, 0xc0, 0x23, 0x9a, 0x43, + 0x0a, 0x80, 0x52, 0x49, 0xfb, 0x23, 0x40, 0x39, /// 0xc40 + 0x4a, 0x7e, 0xef, 0x24, 0x1a, 0x40, 0x4a, 0x76, + 0x40, 0x4a, 0x80, 0x3a, 0x11, 0x46, 0x90, 0x87, /// 0xc50 + 0x40, 0x31, 0x88, 0x87, 0x88, 0x80, 0x3d, 0x48, + 0x01, 0x78, 0x21, 0x40, 0x01, 0x70, 0x39, 0x48, /// 0xc60 + 0xc0, 0x38, 0x00, 0x7d, 0x01, 0x28, 0x0a, 0xd0, + 0x44, 0x48, 0x01, 0x78, 0x19, 0x40, 0x01, 0x70, /// 0xc70 + 0xd0, 0x6a, 0x80, 0x21, 0x08, 0x43, 0xd0, 0x62, + 0x08, 0x46, 0xff, 0xf7, 0x6d, 0xff, 0x10, 0xbd, /// 0xc80 + 0xf8, 0xb5, 0x31, 0x48, 0x00, 0x24, 0x80, 0x88, + 0x3e, 0x49, 0x02, 0x07, 0x40, 0x39, 0xc8, 0x7e, /// 0xc90 + 0x00, 0x2a, 0x06, 0xda, 0xc2, 0x07, 0x02, 0xd1, + 0x01, 0x22, 0x10, 0x43, 0xc8, 0x76, 0x02, 0x24, /// 0xca0 + 0x0b, 0xe0, 0xc2, 0x07, 0x09, 0xd0, 0x2a, 0x4a, + 0x20, 0x3a, 0x13, 0x8b, 0x05, 0x25, 0x2d, 0x02, /// 0xcb0 + 0x2b, 0x43, 0x13, 0x83, 0x40, 0x08, 0x40, 0x00, + 0xc8, 0x76, 0x24, 0x4d, 0x4b, 0x21, 0x40, 0x3d, /// 0xcc0 + 0xe8, 0x88, 0x48, 0x43, 0x7d, 0x21, 0xc9, 0x00, + 0x00, 0xf0, 0x7e, 0xfe, 0xae, 0x28, 0x01, 0xd4, /// 0xcd0 + 0xae, 0x38, 0x00, 0xe0, 0x00, 0x20, 0x1d, 0x49, + 0x1c, 0x4e, 0x60, 0x31, 0x00, 0x91, 0x88, 0x74, /// 0xce0 + 0x18, 0x49, 0x80, 0x3e, 0xc0, 0x39, 0x37, 0x46, + 0x49, 0x7e, 0x20, 0x37, 0x80, 0x36, 0x81, 0x42, /// 0xcf0 + 0x17, 0xd2, 0x14, 0x4a, 0xc0, 0x3a, 0xd2, 0x69, + 0x00, 0x2a, 0x01, 0xd1, 0x04, 0x22, 0x14, 0x43, /// 0xd00 + 0x32, 0x78, 0x08, 0x23, 0x1a, 0x43, 0x32, 0x70, + 0x0e, 0x4a, 0xc0, 0x3a, 0xd3, 0x7e, 0x83, 0x42, /// 0xd10 + 0x07, 0xd2, 0x00, 0x23, 0xd3, 0x61, 0x03, 0x22, + 0xfa, 0x76, 0xea, 0x89, 0x08, 0x23, 0x1a, 0x43, /// 0xd20 + 0xea, 0x81, 0x08, 0x4a, 0xc0, 0x3a, 0x92, 0x7e, + 0x89, 0x1a, 0x81, 0x42, 0x30, 0x78, 0x31, 0xd9, /// 0xd30 + 0x01, 0x07, 0x02, 0xd5, 0xf7, 0x21, 0x08, 0x40, + 0x30, 0x70, 0x02, 0x49, 0x00, 0x20, 0xc0, 0x39, /// 0xd40 + 0xc8, 0x61, 0x36, 0xe0, 0xf0, 0x01, 0x00, 0x20, + 0x00, 0x34, 0x00, 0x40, 0x80, 0x00, 0x00, 0x20, /// 0xd50 + 0x20, 0x38, 0x00, 0x40, 0x00, 0x3c, 0x00, 0x40, + 0x80, 0xe2, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe0, /// 0xd60 + 0x00, 0x4c, 0x00, 0x40, 0x01, 0x0a, 0x00, 0x00, + 0xff, 0x07, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40, /// 0xd70 + 0x05, 0x3f, 0x00, 0x00, 0x1f, 0xb0, 0x00, 0x00, + 0x60, 0x67, 0x00, 0x00, 0x40, 0x6c, 0x00, 0x40, /// 0xd80 + 0x05, 0x53, 0x00, 0x00, 0x30, 0x03, 0x00, 0x20, + 0x00, 0x54, 0x00, 0x40, 0xe7, 0x03, 0x00, 0x00, /// 0xd90 + 0xf9, 0x04, 0x00, 0x00, 0x00, 0x07, 0x0c, 0xd5, + 0xfe, 0x48, 0x02, 0x6a, 0xc1, 0x69, 0x91, 0x42, /// 0xda0 + 0x07, 0xd3, 0x00, 0x21, 0xc1, 0x61, 0x03, 0x20, + 0xf8, 0x76, 0xe8, 0x89, 0x08, 0x21, 0x08, 0x43, /// 0xdb0 + 0xe8, 0x81, 0xf9, 0x48, 0x80, 0x89, 0x80, 0x06, + 0x0d, 0xd5, 0xf6, 0x48, 0xc0, 0x69, 0x00, 0x28, /// 0xdc0 + 0x07, 0xd1, 0x04, 0x20, 0x04, 0x43, 0x03, 0x20, + 0xf8, 0x76, 0xe8, 0x89, 0x08, 0x21, 0x08, 0x43, /// 0xdd0 + 0xe8, 0x81, 0xff, 0xf7, 0x14, 0xff, 0xf1, 0x48, + 0x80, 0x8b, 0xc1, 0x04, 0x00, 0x29, 0xf0, 0x48, /// 0xde0 + 0xf0, 0x49, 0x41, 0x56, 0x06, 0xda, 0x19, 0x29, + 0x02, 0xdd, 0x01, 0x20, 0x04, 0x43, 0x0b, 0xe0, /// 0xdf0 + 0x49, 0x1c, 0x03, 0xe0, 0x19, 0x22, 0xd1, 0x42, + 0x06, 0xdb, 0x49, 0x1e, 0x01, 0x74, 0xea, 0x48, /// 0xe00 + 0x80, 0x8d, 0xc0, 0x07, 0xc0, 0x0f, 0x04, 0x43, + 0xe2, 0x48, 0xc0, 0x30, 0xc1, 0x8d, 0x02, 0x8e, /// 0xe10 + 0x83, 0x8e, 0x89, 0x18, 0x42, 0x8e, 0xd2, 0x18, + 0x89, 0x18, 0xde, 0x4a, 0x89, 0x08, 0xd1, 0x60, /// 0xe20 + 0x00, 0x9a, 0x52, 0x7c, 0x00, 0x2a, 0x33, 0xd0, + 0x02, 0x46, 0x80, 0x3a, 0x13, 0x88, 0xa0, 0x32, /// 0xe30 + 0x94, 0x46, 0x8b, 0x42, 0x29, 0xd2, 0x60, 0x32, + 0xc8, 0x33, 0x8b, 0x42, 0x14, 0xd8, 0x81, 0x7f, /// 0xe40 + 0x49, 0x1c, 0xc9, 0xb2, 0x81, 0x77, 0x05, 0x29, + 0x22, 0xd3, 0x91, 0x7b, 0x0a, 0x29, 0x1f, 0xd0, /// 0xe50 + 0x00, 0x21, 0x81, 0x77, 0x01, 0x20, 0x00, 0x05, + 0x04, 0x43, 0x05, 0x20, 0xf8, 0x76, 0xe8, 0x89, /// 0xe60 + 0x08, 0x21, 0x08, 0x43, 0xe8, 0x81, 0x13, 0xe0, + 0x00, 0x21, 0x81, 0x77, 0x60, 0x46, 0x40, 0x7e, /// 0xe70 + 0x63, 0x46, 0x40, 0x1c, 0xc0, 0xb2, 0x58, 0x76, + 0x05, 0x28, 0x09, 0xd3, 0x90, 0x7b, 0x0a, 0x28, /// 0xe80 + 0x06, 0xd0, 0x01, 0x20, 0x59, 0x76, 0x04, 0x43, + 0x02, 0xe0, 0x00, 0x21, 0x51, 0x76, 0x81, 0x77, /// 0xe90 + 0xc6, 0x49, 0x70, 0x6f, 0x88, 0x42, 0x1a, 0xdd, + 0xa9, 0x88, 0x7d, 0x20, 0xc0, 0x00, 0x81, 0x42, /// 0xea0 + 0x15, 0xd9, 0x00, 0x98, 0x00, 0x99, 0x00, 0x7e, + 0x40, 0x1c, 0xc0, 0xb2, 0x08, 0x76, 0x28, 0x28, /// 0xeb0 + 0x10, 0xd3, 0x01, 0x21, 0x49, 0x05, 0x0c, 0x43, + 0x05, 0x21, 0xf9, 0x76, 0xe9, 0x89, 0x08, 0x22, /// 0xec0 + 0x11, 0x43, 0xe9, 0x81, 0x64, 0x28, 0x05, 0xd3, + 0xff, 0xf7, 0x99, 0xfe, 0x02, 0xe0, 0x00, 0x99, /// 0xed0 + 0x00, 0x20, 0x08, 0x76, 0xb4, 0x4a, 0xb6, 0x4b, + 0xd0, 0x6a, 0x01, 0x46, 0x18, 0x40, 0x60, 0x40, /// 0xee0 + 0x05, 0xd0, 0xdb, 0x43, 0x19, 0x40, 0x21, 0x43, + 0xd1, 0x62, 0xff, 0xf7, 0x35, 0xfe, 0xf8, 0xbd, /// 0xef0 + 0x02, 0x46, 0x00, 0x20, 0x02, 0xe0, 0x13, 0x78, + 0x58, 0x40, 0x52, 0x1c, 0x49, 0x1e, 0xfa, 0xd2, /// 0xf00 + 0x70, 0x47, 0x08, 0x22, 0x01, 0x21, 0x01, 0xe0, + 0x09, 0x18, 0x40, 0x08, 0x52, 0x1e, 0xfb, 0xd2, /// 0xf10 + 0xc8, 0x07, 0xc0, 0x0f, 0x70, 0x47, 0xf8, 0xb5, + 0x9e, 0x4c, 0x00, 0x27, 0x20, 0x46, 0xff, 0x30, /// 0xf20 + 0xa1, 0x30, 0x84, 0x46, 0x18, 0x30, 0x05, 0x46, + 0x28, 0x35, 0xff, 0x34, 0x3e, 0x46, 0xc1, 0x34, /// 0xf30 + 0x00, 0x90, 0x60, 0x7d, 0x00, 0x28, 0x0f, 0xd1, + 0x60, 0x46, 0xa1, 0x7d, 0x00, 0x7e, 0x81, 0x42, /// 0xf40 + 0x06, 0xd2, 0x01, 0x20, 0xb8, 0x40, 0x49, 0x1c, + 0x06, 0x43, 0xa1, 0x75, 0xbf, 0x1c, 0x3a, 0xe0, /// 0xf50 + 0x00, 0x20, 0xa0, 0x75, 0x01, 0x20, 0x60, 0x75, + 0xc1, 0xb2, 0x20, 0x7d, 0x81, 0x42, 0x1e, 0xd2, /// 0xf60 + 0xa0, 0x7d, 0x00, 0x28, 0x1f, 0xd0, 0x09, 0x28, + 0x06, 0xd2, 0x00, 0x9a, 0x40, 0x1e, 0x89, 0x5c, /// 0xf70 + 0xc1, 0x40, 0xc8, 0x07, 0xc0, 0x0f, 0x16, 0xe0, + 0x09, 0x28, 0x05, 0xd0, 0xff, 0x22, 0x01, 0x20, /// 0xf80 + 0xa2, 0x75, 0x49, 0x1c, 0x61, 0x75, 0x0e, 0xe0, + 0x00, 0x98, 0x08, 0x5c, 0xff, 0xf7, 0xb9, 0xff, /// 0xf90 + 0x61, 0x46, 0x09, 0x7e, 0x00, 0x29, 0x06, 0xd1, + 0x01, 0x21, 0x48, 0x40, 0x03, 0xe0, 0x68, 0x78, /// 0xfa0 + 0x01, 0x21, 0x48, 0x40, 0xa9, 0x70, 0x69, 0x78, + 0x01, 0x22, 0x51, 0x40, 0x48, 0x40, 0x68, 0x70, /// 0xfb0 + 0x40, 0x00, 0x08, 0x43, 0xb8, 0x40, 0x06, 0x43, + 0xa0, 0x7d, 0xbf, 0x1c, 0x40, 0x1c, 0xa0, 0x75, /// 0xfc0 + 0xa8, 0x78, 0x01, 0x28, 0x01, 0xd0, 0x10, 0x2f, + 0xb3, 0xd3, 0x7f, 0x1e, 0x2f, 0x70, 0xe6, 0x83, /// 0xfd0 + 0xf8, 0xbd, 0xf0, 0xb5, 0x04, 0x46, 0x41, 0x1c, + 0x71, 0x48, 0xa7, 0x38, 0xff, 0xf7, 0x88, 0xff, /// 0xfe0 + 0x6c, 0x49, 0x6f, 0x4d, 0x09, 0x19, 0xff, 0x31, + 0xa0, 0x3d, 0xa1, 0x31, 0x88, 0x76, 0xe4, 0x1c, /// 0xff0 + 0x2c, 0x75, 0x28, 0x7e, 0xe8, 0x75, 0x00, 0x20, + 0x68, 0x75, 0x2e, 0x46, 0xa8, 0x75, 0x20, 0x36, /// 0x1000 + 0x70, 0x70, 0x02, 0x27, 0xb7, 0x70, 0xff, 0xf7, + 0x86, 0xff, 0xa9, 0x7e, 0x69, 0x48, 0x00, 0x29, /// 0x1010 + 0x08, 0xd1, 0x65, 0x49, 0xa0, 0x31, 0xc9, 0x7b, + 0xc9, 0x1d, 0x41, 0x71, 0x01, 0x88, 0x82, 0x14, /// 0x1020 + 0x11, 0x43, 0x01, 0x80, 0x64, 0x49, 0x0a, 0x8a, + 0x0c, 0x23, 0x1a, 0x43, 0x0a, 0x82, 0x5e, 0x4a, /// 0x1030 + 0x62, 0x4b, 0xd2, 0x8f, 0x00, 0x21, 0x9a, 0x42, + 0x01, 0xd2, 0xc0, 0x22, 0x00, 0xe0, 0x30, 0x22, /// 0x1040 + 0xd3, 0x06, 0x01, 0xd5, 0xff, 0x21, 0x01, 0x31, + 0x93, 0x06, 0x02, 0xd5, 0x01, 0x23, 0x5b, 0x02, /// 0x1050 + 0x19, 0x43, 0x03, 0x88, 0x03, 0x24, 0x24, 0x02, + 0xa3, 0x43, 0x0b, 0x43, 0x01, 0x21, 0xc9, 0x03, /// 0x1060 + 0x0b, 0x43, 0x03, 0x80, 0x53, 0x4c, 0x56, 0x48, + 0x20, 0x3c, 0xa0, 0x80, 0x27, 0x81, 0x00, 0x20, /// 0x1070 + 0xc0, 0x43, 0xa0, 0x81, 0x00, 0x20, 0x51, 0x06, + 0x00, 0xd5, 0x08, 0x20, 0x11, 0x06, 0x01, 0xd5, /// 0x1080 + 0x40, 0x21, 0x08, 0x43, 0x25, 0x21, 0x08, 0x43, + 0x20, 0x80, 0x47, 0x48, 0x40, 0x30, 0x80, 0x78, /// 0x1090 + 0x01, 0x28, 0xe8, 0x8b, 0x00, 0xd1, 0xc0, 0x43, + 0x20, 0x82, 0x30, 0x78, 0x20, 0x75, 0xff, 0xf7, /// 0x10a0 + 0x3a, 0xff, 0xff, 0x20, 0x00, 0x02, 0xa0, 0x81, + 0xf0, 0xbd, 0x3c, 0x4a, 0x10, 0x8b, 0x45, 0x4b, /// 0x10b0 + 0x80, 0x04, 0x81, 0x0e, 0x3c, 0x48, 0x40, 0x30, + 0x80, 0x7a, 0x40, 0x1c, 0x58, 0x43, 0x00, 0x0a, /// 0x10c0 + 0x40, 0x1e, 0x3f, 0x28, 0x00, 0xdd, 0x3f, 0x20, + 0x81, 0x42, 0x00, 0xd2, 0x48, 0x1c, 0x11, 0x8b, /// 0x10d0 + 0x3f, 0x23, 0x1b, 0x02, 0x99, 0x43, 0x00, 0x02, + 0x01, 0x43, 0x11, 0x83, 0x36, 0x49, 0x08, 0x88, /// 0x10e0 + 0x07, 0x22, 0x12, 0x02, 0x90, 0x43, 0x30, 0x4a, + 0x60, 0x32, 0x92, 0x78, 0x52, 0x07, 0x52, 0x0d, /// 0x10f0 + 0x10, 0x43, 0x08, 0x80, 0x2c, 0x48, 0xa0, 0x30, + 0x81, 0x7a, 0x1f, 0x29, 0x01, 0xd9, 0x1f, 0x21, /// 0x1100 + 0x81, 0x72, 0x2c, 0x48, 0xc9, 0xb2, 0x02, 0x88, + 0x52, 0x09, 0x52, 0x01, 0xc3, 0x13, 0x1a, 0x43, /// 0x1110 + 0x11, 0x43, 0x01, 0x80, 0x70, 0x47, 0xf8, 0xb5, + 0x21, 0x49, 0x05, 0x46, 0x40, 0x09, 0xa0, 0x39, /// 0x1120 + 0x00, 0x28, 0x0a, 0xd0, 0x20, 0x28, 0x01, 0xdb, + 0x1f, 0x20, 0x06, 0xe0, 0x8a, 0x7e, 0x82, 0x42, /// 0x1130 + 0x01, 0xda, 0x40, 0x1e, 0x01, 0xe0, 0x82, 0x42, + 0x00, 0xdd, 0x88, 0x76, 0x1a, 0x48, 0x15, 0x21, /// 0x1140 + 0xc0, 0x8f, 0x06, 0x46, 0x48, 0x43, 0x19, 0x21, + 0x00, 0xf0, 0x3e, 0xfc, 0x04, 0x46, 0x1b, 0x48, /// 0x1150 + 0xff, 0x34, 0x19, 0x34, 0x56, 0x30, 0x84, 0x42, + 0x00, 0xd9, 0x64, 0x1c, 0x7d, 0x20, 0x00, 0x01, /// 0x1160 + 0x84, 0x42, 0x00, 0xd9, 0x04, 0x46, 0x67, 0x20, + 0x00, 0x02, 0x0e, 0x21, 0x41, 0x56, 0x70, 0x18, /// 0x1170 + 0x15, 0x49, 0x88, 0x42, 0x00, 0xd9, 0x08, 0x46, + 0x01, 0x21, 0x08, 0x43, 0x07, 0x49, 0x08, 0x82, /// 0x1180 + 0x65, 0x43, 0x28, 0x46, 0x11, 0x49, 0x00, 0xf0, + 0x1f, 0xfc, 0x07, 0x4d, 0x80, 0x35, 0xa9, 0x7c, /// 0x1190 + 0x08, 0x1a, 0x1d, 0xe0, 0x30, 0x01, 0x00, 0x20, + 0x20, 0x48, 0x00, 0x40, 0x00, 0x30, 0x00, 0x40, /// 0x11a0 + 0x90, 0x03, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x20, 0xc4, 0x09, 0x00, 0x00, /// 0x11b0 + 0x07, 0x00, 0x30, 0x00, 0x20, 0x38, 0x00, 0x40, + 0x00, 0x34, 0x00, 0x40, 0xbe, 0x04, 0x00, 0x00, /// 0x11c0 + 0xdb, 0x05, 0x00, 0x00, 0x55, 0x03, 0x00, 0x00, + 0xff, 0x07, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, /// 0x11d0 + 0x53, 0x49, 0x77, 0x39, 0x8e, 0x42, 0x06, 0xd8, + 0x00, 0x28, 0x04, 0xdb, 0xe9, 0x7c, 0x40, 0x43, /// 0x11e0 + 0x41, 0x43, 0x48, 0x11, 0x00, 0xe0, 0x00, 0x20, + 0xe9, 0x8a, 0x0f, 0x18, 0xa8, 0x8a, 0xb8, 0x42, /// 0x11f0 + 0x00, 0xd2, 0x07, 0x46, 0x4a, 0x48, 0x3b, 0x30, + 0x86, 0x42, 0x00, 0xd9, 0x0d, 0x27, 0x49, 0x49, /// 0x1200 + 0x60, 0x03, 0x40, 0x18, 0x49, 0x00, 0x00, 0xf0, + 0xdf, 0xfb, 0x1e, 0x21, 0x69, 0x56, 0xc0, 0x19, /// 0x1210 + 0x08, 0x18, 0x45, 0x49, 0x88, 0x42, 0x00, 0xd9, + 0x08, 0x46, 0x28, 0x82, 0xf8, 0xbd, 0x10, 0xb5, /// 0x1220 + 0x42, 0x48, 0x43, 0x49, 0x43, 0x4a, 0x13, 0x78, + 0x5b, 0x06, 0x02, 0xd4, 0x03, 0x68, 0x05, 0x2b, /// 0x1230 + 0x01, 0xd3, 0x00, 0x20, 0x10, 0xbd, 0x0b, 0x78, + 0x05, 0x2b, 0xf4, 0xd9, 0x3c, 0x48, 0x54, 0x38, /// 0x1240 + 0x01, 0x8f, 0x42, 0x8f, 0x51, 0x18, 0x82, 0x8f, + 0xc0, 0x8f, 0x51, 0x18, 0x41, 0x18, 0x3a, 0x48, /// 0x1250 + 0x00, 0xf0, 0xba, 0xfb, 0x39, 0x49, 0x08, 0x84, + 0x01, 0x20, 0x10, 0xbd, 0x37, 0x48, 0x40, 0x38, /// 0x1260 + 0x80, 0x78, 0x05, 0x28, 0x01, 0xd3, 0x36, 0x49, + 0x01, 0xe0, 0x35, 0x49, 0x83, 0x31, 0x35, 0x48, /// 0x1270 + 0x02, 0x89, 0x89, 0x1a, 0x00, 0x22, 0x82, 0x5e, + 0x88, 0x18, 0x70, 0x47, 0x31, 0x48, 0x10, 0xb5, /// 0x1280 + 0x40, 0x30, 0xc4, 0x8b, 0x80, 0x8b, 0x21, 0x1a, + 0x2f, 0x48, 0x00, 0xf0, 0x9d, 0xfb, 0x28, 0x49, /// 0x1290 + 0x2e, 0x4a, 0x6c, 0x31, 0x08, 0x62, 0x60, 0x43, + 0x10, 0x1a, 0x48, 0x62, 0x10, 0xbd, 0x29, 0x48, /// 0x12a0 + 0x10, 0xb5, 0x40, 0x30, 0x44, 0x8b, 0x27, 0x48, + 0x00, 0x89, 0x21, 0x1a, 0x9d, 0x20, 0xc0, 0x03, /// 0x12b0 + 0x00, 0xf0, 0x8a, 0xfb, 0x26, 0x49, 0x27, 0x4a, + 0x08, 0x60, 0x60, 0x43, 0x10, 0x1a, 0x48, 0x60, /// 0x12c0 + 0x10, 0xbd, 0xf8, 0xb5, 0x24, 0x48, 0x00, 0x8b, + 0xcf, 0x26, 0xf6, 0x01, 0x37, 0x8b, 0x19, 0x20, /// 0x12d0 + 0x39, 0x46, 0x80, 0x03, 0x00, 0xf0, 0x78, 0xfb, + 0x15, 0x4c, 0x6c, 0x34, 0xa0, 0x80, 0x00, 0x20, /// 0x12e0 + 0xe0, 0x80, 0x75, 0x8b, 0x19, 0x20, 0xe9, 0x1b, + 0x80, 0x03, 0x00, 0xf0, 0x83, 0xfb, 0x80, 0xb2, /// 0x12f0 + 0x20, 0x81, 0x68, 0x43, 0x19, 0x21, 0x80, 0x12, + 0x49, 0x01, 0x08, 0x1a, 0x60, 0x81, 0xb4, 0x8b, /// 0x1300 + 0x7d, 0x20, 0x61, 0x1b, 0x00, 0x03, 0x00, 0xf0, + 0x75, 0xfb, 0x11, 0x49, 0x80, 0xb2, 0x08, 0x81, /// 0x1310 + 0x03, 0x4a, 0x60, 0x43, 0x80, 0x12, 0x56, 0x32, + 0x10, 0x1a, 0x48, 0x81, 0xf8, 0xbd, 0x00, 0x00, /// 0x1320 + 0xbe, 0x04, 0x00, 0x00, 0x41, 0x0a, 0x00, 0x00, + 0xff, 0x0f, 0x00, 0x00, 0x34, 0x02, 0x00, 0x20, /// 0x1330 + 0x44, 0x03, 0x00, 0x20, 0x00, 0x3c, 0x00, 0x40, + 0x00, 0x70, 0x17, 0x00, 0x40, 0x00, 0x00, 0x20, /// 0x1340 + 0xd7, 0x02, 0x00, 0x00, 0x20, 0x67, 0x00, 0x00, + 0x00, 0xe0, 0x79, 0x00, 0x00, 0xd0, 0xb6, 0x00, /// 0x1350 + 0x00, 0x05, 0x00, 0x20, 0x00, 0xf0, 0x7b, 0x00, + 0x00, 0x30, 0x00, 0x40, 0xb5, 0x48, 0x00, 0x68, /// 0x1360 + 0x00, 0x47, 0xb4, 0x48, 0x40, 0x68, 0x00, 0x47, + 0xb2, 0x48, 0x80, 0x68, 0x00, 0x47, 0xb1, 0x48, /// 0x1370 + 0xc0, 0x68, 0x00, 0x47, 0xaf, 0x48, 0x00, 0x69, + 0x00, 0x47, 0xae, 0x48, 0x40, 0x69, 0x00, 0x47, /// 0x1380 + 0xac, 0x48, 0x80, 0x69, 0x00, 0x47, 0xab, 0x48, + 0xc0, 0x69, 0x00, 0x47, 0xa9, 0x48, 0x00, 0x6a, /// 0x1390 + 0x00, 0x47, 0xa8, 0x48, 0x40, 0x6a, 0x00, 0x47, + 0xa6, 0x48, 0x80, 0x6a, 0x00, 0x47, 0xa5, 0x48, /// 0x13a0 + 0xc0, 0x6a, 0x00, 0x47, 0xf8, 0xb5, 0xa4, 0x48, + 0x02, 0x7a, 0x01, 0x79, 0x0a, 0x40, 0x02, 0x72, /// 0x13b0 + 0xd1, 0x07, 0x19, 0xd0, 0x01, 0x79, 0x49, 0x08, + 0x49, 0x00, 0x01, 0x71, 0x00, 0x21, 0x01, 0x74, /// 0x13c0 + 0x01, 0x70, 0x9e, 0x4c, 0x65, 0x7e, 0x9e, 0x49, + 0x02, 0x23, 0x05, 0x2d, 0x09, 0xd0, 0x0e, 0x79, /// 0x13d0 + 0x04, 0x25, 0x2e, 0x43, 0x0e, 0x71, 0x0e, 0x8a, + 0xc1, 0x27, 0xbf, 0x00, 0xbe, 0x43, 0x0e, 0x82, /// 0x13e0 + 0x65, 0x76, 0x0c, 0x79, 0x1c, 0x43, 0x0c, 0x71, + 0x91, 0x07, 0x10, 0xd5, 0x01, 0x79, 0xfd, 0x22, /// 0x13f0 + 0x11, 0x40, 0x01, 0x71, 0x90, 0x48, 0x00, 0x24, + 0x20, 0x30, 0x04, 0x70, 0x8f, 0x49, 0x10, 0x22, /// 0x1400 + 0x38, 0x31, 0x88, 0x18, 0xff, 0xf7, 0x76, 0xfb, + 0x8c, 0x48, 0xe0, 0x30, 0x44, 0x73, 0xf8, 0xbd, /// 0x1410 + 0xf8, 0xb5, 0x8b, 0x4c, 0xa0, 0x8a, 0x21, 0x8a, + 0x08, 0x40, 0xff, 0x21, 0xa1, 0x82, 0xc6, 0x21, /// 0x1420 + 0x06, 0x46, 0xff, 0x22, 0x0e, 0x40, 0x87, 0x4d, + 0x71, 0x32, 0x11, 0x1d, 0x52, 0x59, 0x49, 0x5b, /// 0x1430 + 0xff, 0x35, 0x02, 0x23, 0x61, 0x35, 0x00, 0x2e, + 0x25, 0xd0, 0xc4, 0x26, 0x30, 0x40, 0x00, 0x26, /// 0x1440 + 0x00, 0x28, 0x08, 0xd0, 0x20, 0x79, 0x18, 0x43, + 0x20, 0x71, 0x20, 0x20, 0xff, 0xf7, 0xec, 0xfa, /// 0x1450 + 0x06, 0x20, 0x68, 0x76, 0x07, 0xe0, 0x68, 0x7e, + 0x04, 0x28, 0x03, 0xd1, 0x20, 0x7b, 0x51, 0x18, /// 0x1460 + 0x20, 0x39, 0xc8, 0x77, 0x6e, 0x76, 0x0d, 0x20, + 0x20, 0x70, 0x03, 0x20, 0x00, 0x02, 0x20, 0x82, /// 0x1470 + 0x6a, 0x20, 0x20, 0x77, 0x26, 0x71, 0x70, 0x48, + 0x06, 0x70, 0x06, 0x74, 0x01, 0x79, 0x49, 0x08, /// 0x1480 + 0x49, 0x00, 0x01, 0x71, 0xf8, 0xbd, 0x6d, 0x4e, + 0xc7, 0x07, 0x20, 0x3e, 0xf6, 0x8e, 0x00, 0x2f, /// 0x1490 + 0x03, 0xd0, 0x30, 0x0a, 0x20, 0x73, 0x6b, 0x76, + 0xf8, 0xbd, 0xc0, 0x06, 0xfc, 0xd5, 0x68, 0x7e, /// 0x14a0 + 0x02, 0x28, 0x12, 0xd0, 0x21, 0x20, 0x20, 0x71, + 0xff, 0x20, 0xc3, 0x30, 0x20, 0x82, 0x62, 0x48, /// 0x14b0 + 0x40, 0x23, 0x03, 0x70, 0x90, 0x23, 0x03, 0x74, + 0x02, 0x83, 0x89, 0x1e, 0x81, 0x82, 0x01, 0x21, /// 0x14c0 + 0x01, 0x72, 0x02, 0x79, 0x0a, 0x43, 0x02, 0x71, + 0xf8, 0xbd, 0x26, 0x73, 0x03, 0x20, 0x68, 0x76, /// 0x14d0 + 0xf8, 0xbd, 0x5d, 0x49, 0x81, 0x20, 0x08, 0x80, + 0x70, 0x47, 0x70, 0xb5, 0x5a, 0x48, 0x02, 0x8b, /// 0x14e0 + 0x02, 0x83, 0x91, 0x06, 0x8c, 0x0f, 0x55, 0x49, + 0x01, 0x23, 0x60, 0x31, 0x00, 0x2c, 0x1f, 0xd0, /// 0x14f0 + 0x0a, 0x46, 0x20, 0x32, 0x95, 0x78, 0x00, 0x24, + 0x00, 0x2d, 0x11, 0xd0, 0x53, 0x49, 0x8b, 0x78, /// 0x1500 + 0x11, 0x46, 0x20, 0x39, 0xc9, 0x8b, 0x01, 0x2b, + 0x00, 0xd1, 0xc9, 0x43, 0x01, 0x82, 0x11, 0x78, /// 0x1510 + 0x01, 0x75, 0x01, 0x2d, 0x02, 0xd0, 0xff, 0xf7, + 0xfe, 0xfc, 0x70, 0xbd, 0x94, 0x70, 0x70, 0xbd, /// 0x1520 + 0x03, 0x80, 0x4b, 0x48, 0x0c, 0x75, 0x01, 0x8a, + 0x0c, 0x22, 0x91, 0x43, 0x01, 0x82, 0x70, 0xbd, /// 0x1530 + 0x05, 0x20, 0x00, 0x03, 0x02, 0x42, 0xfa, 0xd0, + 0xc8, 0x7e, 0x18, 0x43, 0xc8, 0x76, 0x70, 0xbd, /// 0x1540 + 0x3e, 0x48, 0x60, 0x38, 0x41, 0x68, 0x49, 0x1c, + 0x41, 0x60, 0x42, 0x49, 0x07, 0x20, 0x08, 0x72, /// 0x1550 + 0x70, 0x47, 0x10, 0xb5, 0x3f, 0x4c, 0x20, 0x7a, + 0x80, 0x07, 0x02, 0xd5, 0x3e, 0x48, 0xfe, 0xf7, /// 0x1560 + 0x96, 0xfd, 0x07, 0x20, 0x20, 0x72, 0x10, 0xbd, + 0x10, 0xb5, 0x3c, 0x49, 0x8b, 0x89, 0x33, 0x48, /// 0x1570 + 0x34, 0x4c, 0xa0, 0x30, 0x02, 0x7d, 0x52, 0x00, + 0x12, 0x19, 0xff, 0x32, 0xc1, 0x32, 0x93, 0x86, /// 0x1580 + 0x02, 0x7d, 0x52, 0x1c, 0x12, 0x07, 0x12, 0x0f, + 0x02, 0x75, 0x0f, 0x20, 0x08, 0x83, 0x10, 0xbd, /// 0x1590 + 0x33, 0x49, 0x0f, 0x20, 0x08, 0x83, 0x70, 0x47, + 0x2d, 0x48, 0x10, 0xb5, 0x40, 0x30, 0x81, 0x88, /// 0x15a0 + 0x09, 0x07, 0x0c, 0xd5, 0x81, 0x88, 0x08, 0x22, + 0x11, 0x43, 0x81, 0x80, 0x28, 0x48, 0x81, 0x88, /// 0x15b0 + 0x89, 0x07, 0x04, 0xd5, 0x2b, 0x4a, 0x02, 0x21, + 0xd1, 0x77, 0x01, 0x21, 0x81, 0x80, 0x1f, 0x48, /// 0x15c0 + 0x20, 0x30, 0x40, 0x68, 0x00, 0x28, 0x00, 0xd0, + 0x80, 0x47, 0x27, 0x49, 0x0f, 0x20, 0x08, 0x76, /// 0x15d0 + 0x10, 0xbd, 0x10, 0xb5, 0x25, 0x48, 0x01, 0x78, + 0x49, 0x06, 0x22, 0xd5, 0x41, 0x21, 0x01, 0x70, /// 0x15e0 + 0x1a, 0x48, 0x20, 0x21, 0x40, 0x38, 0x42, 0x6b, + 0x0a, 0x43, 0x42, 0x63, 0xc2, 0x6a, 0x0a, 0x43, /// 0x15f0 + 0xc2, 0x62, 0x08, 0x46, 0xff, 0xf7, 0xb0, 0xfa, + 0x14, 0x48, 0x00, 0x21, 0x41, 0x73, 0x1d, 0x4c, /// 0x1600 + 0x1b, 0x48, 0x20, 0x82, 0xa0, 0x8a, 0x61, 0x14, + 0x08, 0x43, 0xa0, 0x82, 0xa0, 0x8b, 0x40, 0x08, /// 0x1610 + 0x40, 0x00, 0xa0, 0x83, 0x64, 0x20, 0xff, 0xf7, + 0x07, 0xfa, 0xa0, 0x8b, 0x08, 0x21, 0x88, 0x43, /// 0x1620 + 0xa0, 0x83, 0x14, 0x48, 0x40, 0x30, 0x01, 0x79, + 0xc9, 0x07, 0x01, 0xd0, 0x10, 0x21, 0x01, 0x71, /// 0x1630 + 0x10, 0xbd, 0x00, 0x00, 0x00, 0x01, 0x00, 0x20, + 0x00, 0x60, 0x00, 0x40, 0x90, 0x02, 0x00, 0x20, /// 0x1640 + 0x00, 0x64, 0x00, 0x40, 0x30, 0x01, 0x00, 0x20, + 0x00, 0x38, 0x00, 0x40, 0x40, 0x00, 0x00, 0x20, /// 0x1650 + 0x00, 0x34, 0x00, 0x40, 0x00, 0x54, 0x00, 0x40, + 0x13, 0x04, 0x00, 0x00, 0x00, 0x4c, 0x00, 0x40, /// 0x1660 + 0x00, 0x50, 0x00, 0x40, 0x90, 0x03, 0x00, 0x20, + 0x00, 0x40, 0x00, 0x40, 0x00, 0x3c, 0x00, 0x40, /// 0x1670 + 0xff, 0x07, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40, + 0x00, 0x21, 0x41, 0x61, 0x81, 0x61, 0xbb, 0x4a, /// 0x1680 + 0x02, 0x60, 0xc1, 0x61, 0xba, 0x4a, 0x42, 0x60, + 0xb8, 0x4a, 0xd2, 0x43, 0x82, 0x60, 0xb8, 0x4a, /// 0x1690 + 0xd2, 0x43, 0xc2, 0x60, 0xb7, 0x4a, 0x01, 0x66, + 0x02, 0x61, 0x41, 0x66, 0x70, 0x47, 0xf0, 0xb5, /// 0x16a0 + 0xb5, 0x4b, 0x84, 0x46, 0x0f, 0xcb, 0xd9, 0xb0, + 0x6c, 0x46, 0x0f, 0xc4, 0x00, 0x23, 0x09, 0xa8, /// 0x16b0 + 0x9a, 0x00, 0x61, 0x46, 0x54, 0x18, 0x20, 0x34, + 0x21, 0x78, 0x5b, 0x1c, 0x09, 0x06, 0x81, 0x50, /// 0x16c0 + 0x65, 0x78, 0x2d, 0x04, 0x29, 0x43, 0x81, 0x50, + 0xa5, 0x78, 0x2d, 0x02, 0x29, 0x43, 0x81, 0x50, /// 0x16d0 + 0xe4, 0x78, 0x21, 0x43, 0x81, 0x50, 0x10, 0x2b, + 0xea, 0xdb, 0x10, 0x21, 0x8c, 0x00, 0x22, 0x18, /// 0x16e0 + 0x80, 0x3a, 0x15, 0x6e, 0x53, 0x6f, 0x6b, 0x40, + 0x95, 0x6c, 0x12, 0x6c, 0x55, 0x40, 0x6b, 0x40, /// 0x16f0 + 0x1f, 0x22, 0xd3, 0x41, 0x49, 0x1c, 0x03, 0x51, + 0x50, 0x29, 0xef, 0xdb, 0x61, 0x46, 0x0a, 0x68, /// 0x1700 + 0x08, 0x92, 0x49, 0x68, 0x63, 0x46, 0x07, 0x91, + 0x9b, 0x68, 0x64, 0x46, 0x06, 0x93, 0xe4, 0x68, /// 0x1710 + 0x65, 0x46, 0x05, 0x94, 0x2d, 0x69, 0x00, 0x26, + 0xb6, 0x46, 0x04, 0x95, 0x70, 0x46, 0x86, 0x00, /// 0x1720 + 0x09, 0xa8, 0x87, 0x59, 0x1b, 0x20, 0x16, 0x46, + 0xc6, 0x41, 0xb8, 0x19, 0x0e, 0x46, 0x27, 0x46, /// 0x1730 + 0x1e, 0x40, 0x8f, 0x43, 0x3e, 0x43, 0x75, 0x19, + 0x45, 0x19, 0x00, 0x98, 0x28, 0x18, 0x25, 0x46, /// 0x1740 + 0x1c, 0x46, 0x0b, 0x46, 0x02, 0x21, 0xcb, 0x41, + 0x11, 0x46, 0x02, 0x46, 0x70, 0x46, 0x40, 0x1c, /// 0x1750 + 0x86, 0x46, 0x14, 0x28, 0xe2, 0xdb, 0x14, 0x20, + 0x86, 0x46, 0x86, 0x00, 0x09, 0xa8, 0x87, 0x59, /// 0x1760 + 0x1b, 0x20, 0x16, 0x46, 0xc6, 0x41, 0xb8, 0x19, + 0x0e, 0x46, 0x5e, 0x40, 0x66, 0x40, 0x75, 0x19, /// 0x1770 + 0x45, 0x19, 0x01, 0x98, 0x28, 0x18, 0x25, 0x46, + 0x1c, 0x46, 0x0b, 0x46, 0x02, 0x21, 0xcb, 0x41, /// 0x1780 + 0x11, 0x46, 0x02, 0x46, 0x70, 0x46, 0x40, 0x1c, + 0x86, 0x46, 0x28, 0x28, 0xe5, 0xdb, 0x28, 0x20, /// 0x1790 + 0x86, 0x46, 0x86, 0x00, 0x09, 0xa8, 0x87, 0x59, + 0x1b, 0x20, 0x16, 0x46, 0xc6, 0x41, 0xbf, 0x19, /// 0x17a0 + 0x1e, 0x46, 0x26, 0x43, 0x18, 0x46, 0x0e, 0x40, + 0x20, 0x40, 0x06, 0x43, 0x70, 0x19, 0x3d, 0x18, /// 0x17b0 + 0x02, 0x98, 0x28, 0x18, 0x25, 0x46, 0x1c, 0x46, + 0x02, 0x23, 0xd9, 0x41, 0x0b, 0x46, 0x11, 0x46, /// 0x17c0 + 0x02, 0x46, 0x70, 0x46, 0x40, 0x1c, 0x86, 0x46, + 0x3c, 0x28, 0xe2, 0xdb, 0x3c, 0x20, 0x86, 0x46, /// 0x17d0 + 0x86, 0x00, 0x09, 0xa8, 0x87, 0x59, 0x1b, 0x20, + 0x16, 0x46, 0xc6, 0x41, 0xb8, 0x19, 0x0e, 0x46, /// 0x17e0 + 0x5e, 0x40, 0x66, 0x40, 0x75, 0x19, 0x45, 0x19, + 0x03, 0x98, 0x28, 0x18, 0x25, 0x46, 0x1c, 0x46, /// 0x17f0 + 0x02, 0x23, 0xd9, 0x41, 0x0b, 0x46, 0x11, 0x46, + 0x02, 0x46, 0x70, 0x46, 0x40, 0x1c, 0x86, 0x46, /// 0x1800 + 0x50, 0x28, 0xe5, 0xdb, 0x08, 0x98, 0x82, 0x18, + 0x60, 0x46, 0x02, 0x60, 0x07, 0x98, 0x41, 0x18, /// 0x1810 + 0x60, 0x46, 0x41, 0x60, 0x06, 0x98, 0xc1, 0x18, + 0x60, 0x46, 0x81, 0x60, 0x05, 0x98, 0x01, 0x19, /// 0x1820 + 0x60, 0x46, 0xc1, 0x60, 0x04, 0x98, 0x41, 0x19, + 0x60, 0x46, 0x01, 0x61, 0x00, 0x21, 0xc1, 0x61, /// 0x1830 + 0x59, 0xb0, 0xf0, 0xbd, 0x70, 0xb5, 0x04, 0x46, + 0xc0, 0x69, 0x25, 0x46, 0x41, 0x1c, 0x80, 0x22, /// 0x1840 + 0x20, 0x35, 0x00, 0x26, 0xe1, 0x61, 0x37, 0x28, + 0x42, 0x55, 0x03, 0xdc, 0x13, 0xe0, 0x41, 0x1c, /// 0x1850 + 0xe1, 0x61, 0x46, 0x55, 0xe0, 0x69, 0x40, 0x28, + 0xf9, 0xdb, 0x20, 0x46, 0xff, 0xf7, 0x1f, 0xff, /// 0x1860 + 0x02, 0xe0, 0x41, 0x1c, 0xe1, 0x61, 0x46, 0x55, + 0xe0, 0x69, 0x38, 0x28, 0xf9, 0xdb, 0x05, 0xe0, /// 0x1870 + 0x41, 0x1c, 0xe1, 0x61, 0x46, 0x55, 0xe0, 0x69, + 0x38, 0x28, 0xf9, 0xdb, 0xa1, 0x69, 0x20, 0x46, /// 0x1880 + 0x0a, 0x0e, 0x40, 0x30, 0x02, 0x76, 0x0a, 0x0c, + 0x42, 0x76, 0x0a, 0x0a, 0x82, 0x76, 0xc1, 0x76, /// 0x1890 + 0x61, 0x69, 0x0a, 0x0e, 0x02, 0x77, 0x0a, 0x0c, + 0x42, 0x77, 0x0a, 0x0a, 0x82, 0x77, 0xc1, 0x77, /// 0x18a0 + 0x20, 0x46, 0xff, 0xf7, 0xfc, 0xfe, 0x70, 0xbd, + 0x30, 0xb5, 0x0d, 0x46, 0x04, 0x00, 0x08, 0xd0, /// 0x18b0 + 0x00, 0x2d, 0x06, 0xd0, 0x60, 0x6e, 0x00, 0x28, + 0x04, 0xd1, 0x20, 0x6e, 0x00, 0x28, 0x02, 0xd0, /// 0x18c0 + 0x10, 0xe0, 0x01, 0x20, 0x30, 0xbd, 0x20, 0x46, + 0xff, 0xf7, 0xb4, 0xff, 0x00, 0x20, 0x01, 0x46, /// 0x18d0 + 0x22, 0x18, 0x20, 0x32, 0x40, 0x1c, 0x11, 0x70, + 0x40, 0x28, 0xf9, 0xdb, 0x61, 0x61, 0x01, 0x20, /// 0x18e0 + 0xa1, 0x61, 0x20, 0x66, 0x00, 0x20, 0x03, 0x22, + 0x81, 0x08, 0x83, 0x07, 0x89, 0x00, 0x9b, 0x0f, /// 0x18f0 + 0x61, 0x58, 0xd3, 0x1a, 0xdb, 0x00, 0xd9, 0x40, + 0x29, 0x54, 0x40, 0x1c, 0x14, 0x28, 0xf3, 0xdb, /// 0x1900 + 0x00, 0x20, 0x30, 0xbd, 0xf0, 0xb5, 0x15, 0x00, + 0x0e, 0x46, 0x04, 0x46, 0x15, 0xd0, 0x00, 0x2c, /// 0x1910 + 0x07, 0xd0, 0x00, 0x2e, 0x05, 0xd0, 0x20, 0x6e, + 0x00, 0x28, 0x04, 0xd0, 0x03, 0x20, 0x60, 0x66, /// 0x1920 + 0xf0, 0xbd, 0x01, 0x20, 0xf0, 0xbd, 0x60, 0x6e, + 0x00, 0x28, 0xfb, 0xd1, 0x27, 0x46, 0x20, 0x37, /// 0x1930 + 0x6d, 0x1e, 0x02, 0xd3, 0x60, 0x6e, 0x00, 0x28, + 0x01, 0xd0, 0x00, 0x20, 0xf0, 0xbd, 0xe0, 0x69, /// 0x1940 + 0x31, 0x78, 0x42, 0x1c, 0xe2, 0x61, 0xc1, 0x55, + 0x60, 0x69, 0x08, 0x30, 0x60, 0x61, 0x05, 0xd1, /// 0x1950 + 0xa0, 0x69, 0x40, 0x1c, 0xa0, 0x61, 0x01, 0xd1, + 0x01, 0x20, 0x60, 0x66, 0xe0, 0x69, 0x40, 0x28, /// 0x1960 + 0x02, 0xd1, 0x20, 0x46, 0xff, 0xf7, 0x9b, 0xfe, + 0x76, 0x1c, 0xe1, 0xe7, 0x01, 0x23, 0x45, 0x67, /// 0x1970 + 0x89, 0xab, 0xcd, 0xef, 0xf0, 0xe1, 0xd2, 0xc3, + 0x70, 0x1a, 0x00, 0x00, 0x10, 0xb5, 0x06, 0x49, /// 0x1980 + 0x0c, 0x22, 0x0a, 0x76, 0x19, 0x22, 0x4a, 0x76, + 0x88, 0x76, 0x10, 0x20, 0xa0, 0x31, 0xc8, 0x72, /// 0x1990 + 0x01, 0x20, 0xff, 0xf7, 0x1e, 0xfb, 0x10, 0xbd, + 0xd0, 0x02, 0x00, 0x20, 0x10, 0xb5, 0x07, 0x48, /// 0x19a0 + 0x05, 0x49, 0x81, 0x60, 0x06, 0x49, 0x80, 0x30, + 0x01, 0x60, 0x08, 0x22, 0x05, 0x49, 0x10, 0x30, /// 0x19b0 + 0xff, 0xf7, 0xa0, 0xf8, 0x10, 0xbd, 0x00, 0x00, + 0x47, 0x1e, 0x00, 0x00, 0x30, 0x02, 0x00, 0x20, /// 0x19c0 + 0xad, 0x1a, 0x00, 0x00, 0xc4, 0x22, 0x00, 0x00, + 0x30, 0xb5, 0x0b, 0x46, 0x01, 0x46, 0x00, 0x20, /// 0x19d0 + 0x20, 0x22, 0x01, 0x24, 0x09, 0xe0, 0x0d, 0x46, + 0xd5, 0x40, 0x9d, 0x42, 0x05, 0xd3, 0x1d, 0x46, /// 0x19e0 + 0x95, 0x40, 0x49, 0x1b, 0x25, 0x46, 0x95, 0x40, + 0x40, 0x19, 0x15, 0x46, 0x52, 0x1e, 0x00, 0x2d, /// 0x19f0 + 0xf1, 0xdc, 0x30, 0xbd, 0x70, 0xb5, 0x00, 0x24, + 0x25, 0x46, 0x00, 0x28, 0x01, 0xda, 0x01, 0x24, /// 0x1a00 + 0x40, 0x42, 0x00, 0x29, 0x01, 0xda, 0x01, 0x25, + 0x49, 0x42, 0xff, 0xf7, 0xdd, 0xff, 0xac, 0x42, /// 0x1a10 + 0x00, 0xd0, 0x40, 0x42, 0x00, 0x2c, 0x00, 0xd0, + 0x49, 0x42, 0x70, 0xbd, 0x30, 0xb4, 0x74, 0x46, /// 0x1a20 + 0x64, 0x1e, 0x25, 0x78, 0x64, 0x1c, 0xab, 0x42, + 0x00, 0xd2, 0x1d, 0x46, 0x63, 0x5d, 0x5b, 0x00, /// 0x1a30 + 0xe3, 0x18, 0x30, 0xbc, 0x18, 0x47, 0x00, 0x00, + 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, /// 0x1a40 + 0xa5, 0x13, 0x00, 0x00, 0x41, 0x15, 0x00, 0x00, + 0x69, 0x15, 0x00, 0x00, 0x91, 0x15, 0x00, 0x00, /// 0x1a50 + 0x79, 0x00, 0x00, 0x00, 0x11, 0x14, 0x00, 0x00, + 0xd3, 0x14, 0x00, 0x00, 0x79, 0x00, 0x00, 0x00, /// 0x1a60 + 0x79, 0x00, 0x00, 0x00, 0x99, 0x15, 0x00, 0x00, + 0x79, 0x00, 0x00, 0x00, 0xd3, 0x15, 0x00, 0x00, /// 0x1a70 + 0x99, 0x79, 0x82, 0x5a, 0xa1, 0xeb, 0xd9, 0x6e, + 0xdc, 0xbc, 0x1b, 0x8f, 0xd6, 0xc1, 0x62, 0xca, /// 0x1a80 + 0xfe, 0x48, 0x32, 0x21, 0x01, 0x67, 0x01, 0x46, + 0x0a, 0x22, 0x40, 0x39, 0x8a, 0x73, 0x40, 0x39, /// 0x1a90 + 0x49, 0x68, 0x32, 0x39, 0x41, 0x66, 0xfa, 0x48, + 0x01, 0x7f, 0x49, 0x08, 0x49, 0x00, 0x01, 0x77, /// 0x1aa0 + 0xf8, 0x48, 0x01, 0x78, 0x49, 0x08, 0x49, 0x00, + 0x01, 0x70, 0x70, 0x47, 0xf8, 0xb5, 0xff, 0xf7, /// 0x1ab0 + 0xe7, 0xf8, 0xf3, 0x4e, 0x80, 0x3e, 0xf4, 0x89, + 0x00, 0x2c, 0x50, 0xd0, 0x00, 0x27, 0x35, 0x46, /// 0x1ac0 + 0xe0, 0x05, 0x40, 0x35, 0xf7, 0x81, 0x00, 0x28, + 0x15, 0xda, 0xff, 0xf7, 0x98, 0xf8, 0x02, 0x20, /// 0x1ad0 + 0x28, 0x70, 0xeb, 0x48, 0x01, 0x7f, 0x49, 0x08, + 0x49, 0x00, 0x01, 0x77, 0xe9, 0x48, 0x01, 0x78, /// 0x1ae0 + 0x49, 0x08, 0x49, 0x00, 0x01, 0x70, 0xe8, 0x49, + 0x5a, 0x20, 0x08, 0x70, 0xe6, 0x49, 0x10, 0x20, /// 0x1af0 + 0x40, 0x31, 0x08, 0x70, 0x33, 0xe0, 0xe5, 0x48, + 0x21, 0x04, 0x04, 0xd5, 0x01, 0x8f, 0x01, 0x22, /// 0x1b00 + 0x52, 0x02, 0x11, 0x43, 0x01, 0x87, 0xe1, 0x06, + 0x04, 0xd5, 0x01, 0x8f, 0xff, 0x22, 0x01, 0x32, /// 0x1b10 + 0x11, 0x43, 0x01, 0x87, 0xe0, 0x07, 0x03, 0xd0, + 0x68, 0x78, 0x08, 0x21, 0x08, 0x43, 0x68, 0x70, /// 0x1b20 + 0xa0, 0x06, 0x07, 0xd5, 0xda, 0x48, 0x01, 0x7d, + 0x01, 0x29, 0x01, 0xd1, 0x04, 0x21, 0x01, 0x75, /// 0x1b30 + 0xff, 0xf7, 0x21, 0xf8, 0x20, 0x07, 0x01, 0xd5, + 0xff, 0xf7, 0xa2, 0xff, 0xa0, 0x07, 0x01, 0xd5, /// 0x1b40 + 0x00, 0xf0, 0xde, 0xfe, 0x20, 0x06, 0x03, 0xd5, + 0xa8, 0x78, 0x01, 0x21, 0x08, 0x43, 0xa8, 0x70, /// 0x1b50 + 0x60, 0x07, 0x03, 0xd5, 0xa8, 0x78, 0x20, 0x21, + 0x08, 0x43, 0xa8, 0x70, 0x37, 0x73, 0x00, 0x20, /// 0x1b60 + 0xf8, 0xbd, 0xc6, 0x48, 0x10, 0xb5, 0x80, 0x38, + 0x41, 0x68, 0x80, 0x30, 0x42, 0x6e, 0x03, 0x6f, /// 0x1b70 + 0x8a, 0x1a, 0x9a, 0x42, 0x0c, 0xdb, 0x41, 0x66, + 0x83, 0x21, 0x89, 0x00, 0x01, 0x87, 0xc3, 0x48, /// 0x1b80 + 0x20, 0x30, 0xc1, 0x7e, 0xbd, 0x48, 0x20, 0x30, + 0x81, 0x76, 0x01, 0x20, 0xff, 0xf7, 0x21, 0xfa, /// 0x1b90 + 0x10, 0xbd, 0xbb, 0x48, 0x10, 0xb5, 0x10, 0x22, + 0xbe, 0x49, 0x30, 0x38, 0xfe, 0xf7, 0xaa, 0xff, /// 0x1ba0 + 0xb7, 0x48, 0x10, 0x22, 0xbc, 0x49, 0x58, 0x38, + 0xfe, 0xf7, 0xa4, 0xff, 0xff, 0x20, 0xb7, 0x49, /// 0x1bb0 + 0x7d, 0x30, 0xc8, 0x87, 0xb2, 0x48, 0x7c, 0x21, + 0x60, 0x38, 0xc1, 0x70, 0xff, 0x20, 0xb2, 0x49, /// 0x1bc0 + 0x7e, 0x30, 0x08, 0x82, 0x10, 0xbd, 0x10, 0xb5, + 0xff, 0xf7, 0xe3, 0xff, 0xaf, 0x4c, 0xf7, 0x21, /// 0x1bd0 + 0x40, 0x34, 0x60, 0x7b, 0x08, 0x40, 0x60, 0x73, + 0xac, 0x49, 0x01, 0x20, 0xca, 0x6a, 0x80, 0x05, /// 0x1be0 + 0x02, 0x43, 0xca, 0x62, 0xfe, 0xf7, 0xb8, 0xff, + 0x20, 0x46, 0xac, 0x49, 0x40, 0x30, 0xc1, 0x60, /// 0x1bf0 + 0x81, 0x60, 0xa2, 0x48, 0xaa, 0x49, 0x80, 0x30, + 0xc1, 0x82, 0xff, 0x38, 0x01, 0x38, 0x41, 0x68, /// 0x1c00 + 0x80, 0x30, 0xc1, 0x66, 0x81, 0x66, 0x02, 0x6f, + 0x89, 0x1a, 0x41, 0x66, 0x12, 0x20, 0xa0, 0x72, /// 0x1c10 + 0x20, 0x46, 0x03, 0x21, 0x20, 0x30, 0x81, 0x70, + 0x9d, 0x49, 0x04, 0x20, 0x08, 0x75, 0x97, 0x48, /// 0x1c20 + 0x07, 0x21, 0x40, 0x38, 0x81, 0x73, 0x10, 0xbd, + 0x70, 0xb5, 0x9e, 0x48, 0x01, 0x88, 0x07, 0x22, /// 0x1c30 + 0x12, 0x02, 0x91, 0x43, 0x01, 0x80, 0x95, 0x4c, + 0x08, 0x21, 0x40, 0x34, 0x60, 0x7b, 0x93, 0x4d, /// 0x1c40 + 0x08, 0x43, 0x60, 0x73, 0x01, 0x20, 0xe9, 0x6a, + 0x80, 0x05, 0x01, 0x43, 0xe9, 0x62, 0xfe, 0xf7, /// 0x1c50 + 0x83, 0xff, 0x12, 0x20, 0xa0, 0x72, 0x20, 0x34, + 0x8e, 0x49, 0x00, 0x26, 0x20, 0x46, 0xa6, 0x70, /// 0x1c60 + 0x10, 0x22, 0x10, 0x31, 0x30, 0x30, 0xfe, 0xf7, + 0x45, 0xff, 0x8b, 0x49, 0x20, 0x46, 0x10, 0x22, /// 0x1c70 + 0x10, 0x31, 0x08, 0x30, 0xfe, 0xf7, 0x3e, 0xff, + 0x20, 0x46, 0x8b, 0x49, 0x20, 0x30, 0x01, 0x82, /// 0x1c80 + 0x81, 0x4a, 0x8a, 0x49, 0x11, 0x82, 0xe9, 0x87, + 0x47, 0x21, 0xe1, 0x70, 0x88, 0x49, 0xc1, 0x60, /// 0x1c90 + 0x82, 0x49, 0x81, 0x60, 0x79, 0x48, 0x80, 0x30, + 0x41, 0x67, 0x7d, 0x48, 0x05, 0x21, 0x06, 0x75, /// 0x1ca0 + 0xff, 0x30, 0x41, 0x30, 0x81, 0x73, 0x70, 0xbd, + 0x10, 0xb5, 0x74, 0x48, 0x81, 0x49, 0x81, 0x63, /// 0x1cb0 + 0x41, 0x21, 0x49, 0x02, 0x81, 0x87, 0x80, 0x21, + 0x20, 0x30, 0x81, 0x77, 0x05, 0x20, 0xff, 0xf7, /// 0x1cc0 + 0x88, 0xf9, 0x10, 0xbd, 0x10, 0xb5, 0x6d, 0x48, + 0x7b, 0x49, 0x81, 0x63, 0x6e, 0x21, 0x81, 0x87, /// 0x1cd0 + 0x7a, 0x49, 0x20, 0x30, 0xca, 0x7b, 0x82, 0x77, + 0x0a, 0x7c, 0xc2, 0x77, 0x49, 0x7c, 0x20, 0x30, /// 0x1ce0 + 0x01, 0x70, 0x07, 0x20, 0xff, 0xf7, 0x75, 0xf9, + 0x10, 0xbd, 0x68, 0x49, 0x10, 0xb5, 0x40, 0x31, /// 0x1cf0 + 0x08, 0x88, 0xc0, 0x08, 0xff, 0x28, 0x00, 0xd9, + 0xff, 0x20, 0xc8, 0x72, 0xff, 0x22, 0x5f, 0x49, /// 0x1d00 + 0x0d, 0x32, 0x0a, 0x87, 0x20, 0x31, 0x88, 0x76, + 0x01, 0x20, 0xff, 0xf7, 0x62, 0xf9, 0x10, 0xbd, /// 0x1d10 + 0xf8, 0xb5, 0x5b, 0x4d, 0x5d, 0x4c, 0x40, 0x3d, + 0x68, 0x78, 0x26, 0x46, 0x27, 0x46, 0xc1, 0x06, /// 0x1d20 + 0x40, 0x36, 0xc0, 0x37, 0x00, 0x29, 0x0a, 0xda, + 0xef, 0x21, 0x08, 0x40, 0x68, 0x70, 0x01, 0x20, /// 0x1d30 + 0xe1, 0x6a, 0xc0, 0x02, 0x01, 0x43, 0xe1, 0x62, + 0xfe, 0xf7, 0x0e, 0xff, 0x10, 0xe0, 0x39, 0x79, /// 0x1d40 + 0x0a, 0x07, 0x06, 0xd5, 0x32, 0x7e, 0x1e, 0x2a, + 0x03, 0xd0, 0x20, 0x21, 0x08, 0x43, 0x68, 0x70, /// 0x1d50 + 0x06, 0xe0, 0x48, 0x06, 0x04, 0xd5, 0xbf, 0x20, + 0x01, 0x40, 0x80, 0x20, 0x01, 0x43, 0x39, 0x71, /// 0x1d60 + 0x38, 0x79, 0x81, 0x07, 0x02, 0xd5, 0x31, 0x7e, + 0x3f, 0x29, 0x16, 0xd0, 0x69, 0x78, 0x49, 0x06, /// 0x1d70 + 0x02, 0xd5, 0x31, 0x7e, 0x4f, 0x29, 0x13, 0xd0, + 0x00, 0x07, 0x09, 0xd5, 0x30, 0x7e, 0x1e, 0x28, /// 0x1d80 + 0x06, 0xd0, 0xe0, 0x6a, 0x10, 0x21, 0x08, 0x43, + 0xe0, 0x62, 0x08, 0x46, 0xfe, 0xf7, 0xe4, 0xfe, /// 0x1d90 + 0xa8, 0x78, 0xbf, 0x21, 0x08, 0x40, 0xa8, 0x70, + 0xf8, 0xbd, 0x01, 0xf0, 0xc8, 0xfe, 0xf7, 0xe7, /// 0x1da0 + 0x3a, 0x48, 0x59, 0x30, 0x01, 0xf0, 0x9f, 0xfe, + 0xf2, 0xe7, 0x10, 0xb5, 0x38, 0x48, 0x44, 0x49, /// 0x1db0 + 0xc4, 0x68, 0x36, 0x48, 0x3c, 0x4a, 0x40, 0x30, + 0x00, 0x88, 0x96, 0x32, 0x48, 0x43, 0x33, 0x49, /// 0x1dc0 + 0x89, 0x8f, 0x51, 0x43, 0x40, 0x1a, 0x64, 0x21, + 0xff, 0xf7, 0x14, 0xfe, 0x60, 0x43, 0xc1, 0x17, /// 0x1dd0 + 0x09, 0x0d, 0x08, 0x18, 0x2a, 0x49, 0x00, 0x13, + 0x40, 0x39, 0x48, 0x67, 0x10, 0xbd, 0x70, 0xb5, /// 0x1de0 + 0x28, 0x48, 0x20, 0x38, 0x00, 0x7d, 0x00, 0x07, + 0x22, 0xd5, 0x28, 0x4d, 0x20, 0x35, 0xe8, 0x7e, /// 0x1df0 + 0x0b, 0x28, 0x1d, 0xd0, 0x22, 0x4c, 0x20, 0x7f, + 0x40, 0x08, 0x40, 0x00, 0x20, 0x77, 0x21, 0x48, /// 0x1e00 + 0x01, 0x78, 0x49, 0x08, 0x49, 0x00, 0x01, 0x70, + 0x20, 0x49, 0x00, 0x14, 0xca, 0x6a, 0x02, 0x43, /// 0x1e10 + 0xca, 0x62, 0xfe, 0xf7, 0xa1, 0xfe, 0x61, 0x8b, + 0x20, 0x46, 0x40, 0x38, 0x00, 0x29, 0x08, 0xd0, /// 0x1e20 + 0x01, 0x78, 0xfd, 0x22, 0x11, 0x40, 0x01, 0x70, + 0x0b, 0x20, 0xe8, 0x76, 0xff, 0xf7, 0x28, 0xfe, /// 0x1e30 + 0x70, 0xbd, 0x02, 0x21, 0x01, 0x70, 0x14, 0x49, + 0x5a, 0x20, 0x08, 0x70, 0x12, 0x49, 0x10, 0x20, /// 0x1e40 + 0x40, 0x31, 0x08, 0x70, 0xfe, 0xe7, 0xf0, 0xb5, + 0x85, 0xb0, 0xff, 0xf7, 0xc8, 0xff, 0xff, 0xf7, /// 0x1e50 + 0xac, 0xff, 0x0f, 0x4e, 0x0a, 0x4f, 0x34, 0x46, + 0xe0, 0x1d, 0x31, 0x7d, 0xf9, 0x30, 0x60, 0x3f, /// 0x1e60 + 0x01, 0x90, 0x3d, 0x46, 0x80, 0x30, 0xff, 0x34, + 0x20, 0x35, 0xc1, 0x34, 0x04, 0x90, 0x01, 0x29, /// 0x1e70 + 0x4e, 0xd1, 0x01, 0x98, 0x31, 0x69, 0x40, 0x68, + 0x41, 0x1a, 0x23, 0xe0, 0xb0, 0x02, 0x00, 0x20, /// 0x1e80 + 0xc0, 0x00, 0x00, 0x20, 0x40, 0x6c, 0x00, 0x40, + 0x00, 0x30, 0x00, 0x40, 0x00, 0x00, 0x00, 0x20, /// 0x1e90 + 0x30, 0x01, 0x00, 0x20, 0xcc, 0x22, 0x00, 0x00, + 0xa4, 0x3b, 0x00, 0x00, 0x04, 0x0a, 0x0a, 0x00, /// 0x1ea0 + 0xdc, 0x05, 0x00, 0x00, 0x00, 0x34, 0x00, 0x40, + 0x9e, 0x07, 0x00, 0x00, 0x47, 0x04, 0x00, 0x00, /// 0x1eb0 + 0x31, 0x14, 0x14, 0x04, 0x0c, 0x51, 0x0a, 0x00, + 0x0c, 0x71, 0x12, 0x00, 0x20, 0x67, 0x00, 0x00, /// 0x1ec0 + 0x41, 0x0a, 0x00, 0x00, 0xf2, 0x48, 0x81, 0x42, + 0x66, 0xd9, 0xf0, 0x68, 0x50, 0x28, 0x12, 0xd2, /// 0x1ed0 + 0x70, 0x7d, 0x40, 0x1c, 0xc0, 0xb2, 0x70, 0x75, + 0x05, 0x28, 0x0e, 0xd1, 0x60, 0x7e, 0x08, 0x21, /// 0x1ee0 + 0x08, 0x43, 0x60, 0x76, 0xfe, 0xf7, 0x8b, 0xfe, + 0xea, 0x48, 0x28, 0x82, 0x02, 0x20, 0x30, 0x75, /// 0x1ef0 + 0x01, 0x98, 0x40, 0x68, 0x30, 0x61, 0x00, 0x20, + 0x70, 0x75, 0x01, 0x98, 0x31, 0x69, 0x40, 0x68, /// 0x1f00 + 0x40, 0x1a, 0xe3, 0x49, 0x08, 0x31, 0x88, 0x42, + 0x02, 0xd9, 0x04, 0x20, 0x30, 0x75, 0x43, 0xe0, /// 0x1f10 + 0x30, 0x7d, 0x02, 0x28, 0x02, 0xd0, 0x03, 0x28, + 0x1e, 0xd0, 0x3d, 0xe0, 0x01, 0x98, 0x31, 0x69, /// 0x1f20 + 0x40, 0x68, 0x7d, 0x22, 0x41, 0x1a, 0x12, 0x01, + 0x91, 0x42, 0x35, 0xd9, 0xff, 0x22, 0xda, 0x49, /// 0x1f30 + 0x7d, 0x32, 0xca, 0x87, 0x7c, 0x21, 0xf9, 0x70, + 0xd8, 0x49, 0x52, 0x1c, 0x0a, 0x82, 0x61, 0x7e, /// 0x1f40 + 0x07, 0x22, 0x11, 0x43, 0x61, 0x76, 0x04, 0x9a, + 0x32, 0x21, 0x11, 0x67, 0x01, 0x46, 0x28, 0x39, /// 0x1f50 + 0x51, 0x66, 0x03, 0x21, 0x31, 0x75, 0x30, 0x61, + 0x01, 0x98, 0x31, 0x69, 0x40, 0x68, 0x47, 0x23, /// 0x1f60 + 0x42, 0x1a, 0xcb, 0x48, 0xce, 0x49, 0x82, 0x42, + 0x24, 0xd2, 0xff, 0x22, 0xf0, 0x68, 0x91, 0x32, /// 0x1f70 + 0x90, 0x42, 0x0f, 0xd9, 0x70, 0x7d, 0x40, 0x1c, + 0xc0, 0xb2, 0x70, 0x75, 0x05, 0x28, 0x0b, 0xd1, /// 0x1f80 + 0x04, 0x20, 0x30, 0x75, 0x00, 0x20, 0x70, 0x75, + 0x29, 0x82, 0xc3, 0x49, 0xc5, 0x48, 0xc8, 0x87, /// 0x1f90 + 0xfb, 0x70, 0x01, 0xe0, 0x00, 0x20, 0x70, 0x75, + 0xbf, 0x49, 0x28, 0x8c, 0xc2, 0x4a, 0xa0, 0x31, /// 0x1fa0 + 0x00, 0x91, 0x90, 0x42, 0x11, 0xd0, 0x00, 0x28, + 0x0f, 0xd0, 0x40, 0x1e, 0x10, 0x40, 0x28, 0x84, /// 0x1fb0 + 0x03, 0xd0, 0x0a, 0xe0, 0x04, 0x20, 0x30, 0x75, + 0xe6, 0xe7, 0x08, 0x79, 0x41, 0x08, 0x00, 0x98, /// 0x1fc0 + 0x49, 0x00, 0x01, 0x71, 0x00, 0x20, 0xc0, 0x43, + 0x28, 0x84, 0x00, 0x98, 0x05, 0x26, 0x00, 0x79, /// 0x1fd0 + 0x01, 0x46, 0x31, 0x40, 0x04, 0x29, 0x03, 0xd1, + 0xfb, 0x21, 0x08, 0x40, 0x00, 0x99, 0x08, 0x71, /// 0x1fe0 + 0xa8, 0x78, 0x40, 0x06, 0x01, 0xd5, 0xff, 0xf7, + 0x93, 0xfe, 0xab, 0x48, 0xad, 0x49, 0xc0, 0x8f, /// 0x1ff0 + 0x88, 0x42, 0x07, 0xd9, 0xa8, 0x48, 0x80, 0x78, + 0x05, 0x28, 0x01, 0xd3, 0x06, 0x20, 0x08, 0xe0, /// 0x2000 + 0xbe, 0x70, 0x07, 0xe0, 0xff, 0x21, 0xf5, 0x31, + 0x88, 0x42, 0x01, 0xd9, 0x01, 0x20, 0x00, 0xe0, /// 0x2010 + 0x03, 0x20, 0xb8, 0x70, 0xa5, 0x48, 0x03, 0x90, + 0x40, 0x7b, 0x00, 0x28, 0x0a, 0xd1, 0xa3, 0x48, /// 0x2020 + 0xb0, 0x38, 0xfe, 0xf7, 0xaa, 0xfa, 0x20, 0x7d, + 0x00, 0x28, 0x01, 0xd1, 0xfe, 0xf7, 0xe3, 0xfa, /// 0x2030 + 0xfe, 0xf7, 0x15, 0xfc, 0x98, 0x4f, 0x98, 0x49, + 0xc0, 0x37, 0x9a, 0x4b, 0x38, 0x7f, 0xc9, 0x8f, /// 0x2040 + 0x77, 0x33, 0x02, 0x46, 0x99, 0x42, 0x03, 0xd3, + 0x3b, 0x8c, 0x92, 0x49, 0x8b, 0x42, 0x01, 0xd2, /// 0x2050 + 0x40, 0x08, 0x40, 0x00, 0x96, 0x49, 0x38, 0x77, + 0xc3, 0x07, 0x0b, 0x78, 0x02, 0xd0, 0x01, 0x26, /// 0x2060 + 0x33, 0x43, 0x06, 0xe0, 0xdb, 0x07, 0x01, 0xd0, + 0xc2, 0x43, 0xd2, 0xb2, 0x0b, 0x78, 0x5b, 0x08, /// 0x2070 + 0x5b, 0x00, 0x0b, 0x70, 0x90, 0x42, 0x07, 0xd0, + 0x87, 0x49, 0x01, 0x20, 0xca, 0x6a, 0x00, 0x04, /// 0x2080 + 0x02, 0x43, 0xca, 0x62, 0xfe, 0xf7, 0x68, 0xfd, + 0x6a, 0x78, 0xd0, 0x06, 0x10, 0xd5, 0xb8, 0x89, /// 0x2090 + 0x41, 0x1c, 0xb9, 0x81, 0x80, 0x49, 0x4b, 0x8c, + 0x98, 0x42, 0x09, 0xd9, 0xef, 0x20, 0x02, 0x40, /// 0x20a0 + 0x6a, 0x70, 0x01, 0x20, 0xca, 0x6a, 0x80, 0x02, + 0x02, 0x43, 0xca, 0x62, 0xfe, 0xf7, 0x54, 0xfd, /// 0x20b0 + 0x28, 0x78, 0xc0, 0x06, 0x01, 0xd5, 0x01, 0xf0, + 0xb5, 0xfc, 0x20, 0x7d, 0x00, 0x28, 0x27, 0xd1, /// 0x20c0 + 0x7c, 0x49, 0xe0, 0x7d, 0x0e, 0x46, 0xff, 0x36, + 0x41, 0x36, 0x31, 0x46, 0xc0, 0x31, 0x02, 0x91, /// 0x20d0 + 0x00, 0x28, 0x20, 0xd0, 0x40, 0x1e, 0xe0, 0x75, + 0xb0, 0x7b, 0x04, 0x28, 0x18, 0xd3, 0x72, 0xb6, /// 0x20e0 + 0x75, 0x48, 0xfd, 0xf7, 0xd4, 0xff, 0x62, 0xb6, + 0x20, 0x7e, 0xe1, 0x7d, 0x40, 0x1e, 0x81, 0x42, /// 0x20f0 + 0x0e, 0xd1, 0x02, 0x99, 0x00, 0x20, 0x88, 0x83, + 0x08, 0x83, 0x00, 0x98, 0xc1, 0x7b, 0x6f, 0x48, /// 0x2100 + 0x41, 0x71, 0x42, 0x79, 0x81, 0x14, 0x00, 0x2a, + 0x02, 0x88, 0x02, 0xd0, 0x0a, 0x43, 0x02, 0x80, /// 0x2110 + 0xb2, 0xe0, 0x8a, 0x43, 0xfb, 0xe7, 0x00, 0x20, + 0x60, 0x77, 0xb0, 0x7b, 0x03, 0x00, 0xff, 0xf7, /// 0x2120 + 0x7d, 0xfc, 0x0b, 0x07, 0xab, 0x4e, 0x53, 0x5f, + 0x85, 0xab, 0x88, 0x8b, 0x9b, 0x9e, 0xab, 0x00, /// 0x2130 + 0x59, 0x48, 0xff, 0x21, 0x80, 0x8f, 0x01, 0x27, + 0x25, 0x31, 0x7f, 0x03, 0x88, 0x42, 0x21, 0xd9, /// 0x2140 + 0x56, 0x4d, 0x01, 0x20, 0x28, 0x82, 0xa8, 0x8a, + 0x38, 0x43, 0xa8, 0x82, 0x14, 0x20, 0xfe, 0xf7, /// 0x2150 + 0x6b, 0xfc, 0xa8, 0x8b, 0x08, 0x27, 0x38, 0x43, + 0xa8, 0x83, 0x14, 0x20, 0xfe, 0xf7, 0x64, 0xfc, /// 0x2160 + 0xa8, 0x8b, 0x01, 0x21, 0x08, 0x43, 0xa8, 0x83, + 0x14, 0x20, 0xfe, 0xf7, 0x5d, 0xfc, 0xa8, 0x8b, /// 0x2170 + 0x40, 0x08, 0x40, 0x00, 0xa8, 0x83, 0x14, 0x20, + 0xfe, 0xf7, 0x56, 0xfc, 0xa8, 0x8b, 0xb8, 0x43, /// 0x2180 + 0xa8, 0x83, 0x0e, 0xe0, 0x45, 0x4d, 0xa8, 0x8b, + 0x40, 0x08, 0x40, 0x00, 0xa8, 0x83, 0x64, 0x20, /// 0x2190 + 0xfe, 0xf7, 0x4a, 0xfc, 0xa9, 0x8b, 0x08, 0x20, + 0x81, 0x43, 0xa9, 0x83, 0xa8, 0x8a, 0xb8, 0x43, /// 0x21a0 + 0xa8, 0x82, 0x01, 0x98, 0x40, 0x68, 0x1d, 0x28, + 0x66, 0xd9, 0x08, 0x20, 0x20, 0x76, 0x04, 0x99, /// 0x21b0 + 0x32, 0x20, 0x08, 0x67, 0x02, 0x20, 0xb0, 0x73, + 0xff, 0xf7, 0x97, 0xfd, 0x5c, 0xe0, 0xff, 0xf7, /// 0x21c0 + 0x81, 0xfd, 0x03, 0x20, 0xb0, 0x73, 0x57, 0xe0, + 0x31, 0x20, 0xe8, 0x70, 0x1e, 0x20, 0x20, 0x76, /// 0x21d0 + 0xff, 0xf7, 0x6a, 0xfd, 0x04, 0x20, 0xb0, 0x73, + 0x03, 0x99, 0x01, 0x20, 0xc8, 0x72, 0x4b, 0xe0, /// 0x21e0 + 0x03, 0x98, 0x00, 0x7b, 0xc0, 0x07, 0x02, 0xd0, + 0xff, 0xf7, 0x1e, 0xfd, 0x01, 0xe0, 0xff, 0xf7, /// 0x21f0 + 0xea, 0xfc, 0xff, 0x20, 0x28, 0x49, 0xf5, 0x30, + 0x48, 0x84, 0x00, 0x20, 0xa8, 0x64, 0x78, 0x71, /// 0x2200 + 0xc8, 0x22, 0xfa, 0x81, 0x01, 0x22, 0x7a, 0x77, + 0xff, 0x22, 0x4a, 0x72, 0x29, 0x4a, 0x80, 0x23, /// 0x2210 + 0x20, 0x32, 0x13, 0x72, 0x42, 0x1e, 0x2a, 0x84, + 0x00, 0x9a, 0x10, 0x71, 0x23, 0x4a, 0x40, 0x32, /// 0x2220 + 0x10, 0x77, 0x27, 0x4a, 0x48, 0x6b, 0x10, 0x43, + 0x48, 0x63, 0x25, 0xe0, 0x01, 0xf0, 0x04, 0xfb, /// 0x2230 + 0x22, 0xe0, 0x01, 0xf0, 0x41, 0xf9, 0x1f, 0xe0, + 0x03, 0x98, 0x00, 0x7b, 0xc0, 0x07, 0x01, 0xd0, /// 0x2240 + 0x09, 0x20, 0x00, 0xe0, 0x07, 0x20, 0xb0, 0x73, + 0x18, 0x49, 0x00, 0x20, 0x20, 0x31, 0xc8, 0x74, /// 0x2250 + 0x02, 0x98, 0xa9, 0x68, 0x41, 0x67, 0x0f, 0xe0, + 0x00, 0xf0, 0x91, 0xfb, 0x0c, 0xe0, 0x0e, 0x48, /// 0x2260 + 0x20, 0x30, 0xc1, 0x7e, 0x13, 0x48, 0xe0, 0x30, + 0x0b, 0x29, 0x08, 0xd0, 0x03, 0x29, 0x06, 0xd0, /// 0x2270 + 0x00, 0x21, 0xc1, 0x75, 0xff, 0xf7, 0x75, 0xfc, + 0x00, 0x20, 0x05, 0xb0, 0xf0, 0xbd, 0xc1, 0x7d, /// 0x2280 + 0x49, 0x1c, 0xc9, 0xb2, 0xc1, 0x75, 0x03, 0x29, + 0xf4, 0xd9, 0x04, 0x21, 0xc1, 0x75, 0xf3, 0xe7, /// 0x2290 + 0x98, 0x3a, 0x00, 0x00, 0x7c, 0x05, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x30, 0x00, 0x40, /// 0x22a0 + 0x9e, 0x07, 0x00, 0x00, 0x47, 0x04, 0x00, 0x00, + 0xff, 0xff, 0x00, 0x00, 0x70, 0x03, 0x00, 0x20, /// 0x22b0 + 0x40, 0x6c, 0x00, 0x40, 0x30, 0x01, 0x00, 0x20, + 0xc7, 0x26, 0x00, 0x00, 0x20, 0x38, 0x00, 0x40, /// 0x22c0 + 0xd8, 0xbf, 0x0f, 0x00, 0x69, 0x60, 0x63, 0x02, + 0x69, 0x60, 0x63, 0x24, 0xf6, 0x03, 0x19, 0x02, /// 0x22d0 + 0xbb, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x75, 0x06, 0x32, 0x04, /// 0x22e0 + 0x5d, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x20, 0x28, 0x01, 0xd2, /// 0x22f0 + 0x01, 0x20, 0x70, 0x47, 0x80, 0x28, 0x03, 0xd2, + 0x20, 0x38, 0x00, 0x11, 0x80, 0x1c, 0x70, 0x47, /// 0x2300 + 0xe0, 0x28, 0x03, 0xd2, 0x80, 0x38, 0xc0, 0x10, + 0x08, 0x30, 0x70, 0x47, 0xe0, 0x38, 0x80, 0x10, /// 0x2310 + 0x14, 0x30, 0x70, 0x47, 0x41, 0x07, 0x89, 0x0f, + 0x03, 0x29, 0x0b, 0xd1, 0x01, 0x07, 0x03, 0xd5, /// 0x2320 + 0x80, 0x09, 0x02, 0x28, 0x04, 0xd0, 0x05, 0xe0, + 0x00, 0x09, 0x03, 0xd0, 0x0c, 0x28, 0x01, 0xd8, /// 0x2330 + 0x01, 0x20, 0x70, 0x47, 0x00, 0x20, 0x70, 0x47, + 0x1e, 0x28, 0x08, 0xd0, 0xc1, 0x43, 0x09, 0x07, /// 0x2340 + 0x07, 0xd1, 0x01, 0x09, 0x06, 0x29, 0x04, 0xd2, + 0x00, 0x06, 0x00, 0x0f, 0x01, 0xd0, 0x01, 0x20, /// 0x2350 + 0x70, 0x47, 0x00, 0x20, 0x70, 0x47, 0x10, 0xb5, + 0xfc, 0x48, 0xf7, 0x22, 0xc1, 0x79, 0x11, 0x40, /// 0x2360 + 0xc1, 0x71, 0xfa, 0x49, 0x00, 0x20, 0x20, 0x39, + 0x08, 0x87, 0x80, 0x20, 0xfe, 0xf7, 0xf4, 0xfb, /// 0x2370 + 0x10, 0xbd, 0xf8, 0xb5, 0xf6, 0x4b, 0x18, 0x78, + 0xff, 0xf7, 0xde, 0xff, 0xf4, 0x4f, 0x20, 0x37, /// 0x2380 + 0x00, 0x28, 0x18, 0xd0, 0xf8, 0x7c, 0x40, 0x1c, + 0xc0, 0xb2, 0xf8, 0x74, 0x06, 0x28, 0x01, 0xd9, /// 0x2390 + 0x06, 0x20, 0xf8, 0x74, 0xc2, 0xb2, 0xed, 0x48, + 0x19, 0x46, 0x38, 0x30, 0xfe, 0xf7, 0xb1, 0xfb, /// 0x23a0 + 0xea, 0x48, 0x40, 0x22, 0x60, 0x30, 0x81, 0x78, + 0x11, 0x43, 0x81, 0x70, 0xf8, 0x7a, 0xef, 0x21, /// 0x23b0 + 0x08, 0x40, 0xf8, 0x72, 0xf8, 0xbd, 0xe5, 0x4c, + 0x18, 0x78, 0x20, 0x3c, 0x26, 0x46, 0x25, 0x46, /// 0x23c0 + 0x04, 0x22, 0x20, 0x36, 0xc0, 0x35, 0x15, 0x28, + 0x18, 0xd0, 0xff, 0xf7, 0xa3, 0xff, 0x01, 0x00, /// 0x23d0 + 0xe0, 0x48, 0x57, 0xd0, 0x19, 0x78, 0xf2, 0x79, + 0xc9, 0x07, 0xd2, 0x07, 0xc9, 0x0f, 0xd2, 0x0f, /// 0x23e0 + 0x91, 0x42, 0x4c, 0xd1, 0xf9, 0x7c, 0x6b, 0x7e, + 0x8c, 0x46, 0x2a, 0x7e, 0x59, 0x18, 0x91, 0x42, /// 0x23f0 + 0x24, 0xd9, 0x69, 0x76, 0x20, 0x8f, 0x02, 0x21, + 0x08, 0x43, 0x08, 0xe0, 0x58, 0x78, 0x01, 0x06, /// 0x2400 + 0x15, 0xd5, 0xf1, 0x79, 0x8b, 0x06, 0x9b, 0x0f, + 0x03, 0xd0, 0x20, 0x8f, 0x10, 0x43, 0x20, 0x87, /// 0x2410 + 0xf8, 0xbd, 0x22, 0x8f, 0x08, 0x23, 0x40, 0x06, + 0x1a, 0x43, 0x40, 0x0e, 0x22, 0x87, 0x40, 0x1c, /// 0x2420 + 0x28, 0x76, 0x00, 0x20, 0x68, 0x76, 0x48, 0x08, + 0x40, 0x00, 0xf0, 0x71, 0xf8, 0xbd, 0x03, 0x28, /// 0x2430 + 0x01, 0xd1, 0xff, 0xf7, 0x90, 0xff, 0x20, 0x8f, + 0x08, 0x21, 0xdd, 0xe7, 0xc4, 0x49, 0x18, 0x18, /// 0x2440 + 0x62, 0x46, 0x49, 0x1c, 0xfe, 0xf7, 0x5d, 0xfb, + 0x68, 0x7e, 0xf9, 0x7c, 0x01, 0x22, 0x40, 0x18, /// 0x2450 + 0xc1, 0xb2, 0x69, 0x76, 0xf0, 0x79, 0x40, 0x23, + 0x50, 0x40, 0xf0, 0x71, 0x22, 0x8f, 0x1a, 0x43, /// 0x2460 + 0x22, 0x87, 0xbb, 0x4a, 0x32, 0x23, 0xa0, 0x3a, + 0x13, 0x67, 0x05, 0x22, 0x3a, 0x72, 0x2a, 0x7e, /// 0x2470 + 0x91, 0x42, 0xdb, 0xd1, 0x10, 0x21, 0x08, 0x43, + 0xf0, 0x71, 0x08, 0x46, 0x16, 0xe0, 0x20, 0x8f, /// 0x2480 + 0x40, 0x21, 0xb9, 0xe7, 0xf1, 0x79, 0x89, 0x06, + 0x89, 0x0f, 0xbe, 0xd1, 0x21, 0x8f, 0x08, 0x22, /// 0x2490 + 0x11, 0x43, 0x21, 0x87, 0xf9, 0x7c, 0x49, 0x1c, + 0xca, 0xb2, 0x2a, 0x76, 0x19, 0x46, 0xfe, 0xf7, /// 0x24a0 + 0x30, 0xfb, 0xf0, 0x79, 0x20, 0x21, 0x08, 0x43, + 0xf0, 0x71, 0x08, 0x46, 0xfe, 0xf7, 0x54, 0xfb, /// 0x24b0 + 0xf8, 0xbd, 0xf8, 0xb5, 0xa5, 0x4e, 0xa0, 0x36, + 0x34, 0x46, 0xc0, 0x3c, 0x23, 0x46, 0xf2, 0x7d, /// 0x24c0 + 0xb1, 0x7d, 0x20, 0x33, 0xd8, 0x79, 0x8a, 0x42, + 0x07, 0xd3, 0x22, 0x8f, 0x80, 0x21, 0x8a, 0x43, /// 0x24d0 + 0xf7, 0x21, 0x22, 0x87, 0x08, 0x40, 0xd8, 0x71, + 0xf8, 0xbd, 0x89, 0x1a, 0xcd, 0xb2, 0x08, 0x2d, /// 0x24e0 + 0x00, 0xd9, 0x08, 0x25, 0x29, 0x07, 0x0f, 0x0e, + 0x81, 0x07, 0x01, 0xd5, 0x07, 0x21, 0x00, 0xe0, /// 0x24f0 + 0x06, 0x21, 0x39, 0x43, 0x02, 0x27, 0x78, 0x40, + 0xd8, 0x71, 0x95, 0x48, 0x01, 0x75, 0xff, 0x38, /// 0x2500 + 0xd9, 0x38, 0x11, 0x18, 0xff, 0x30, 0x2a, 0x46, + 0xee, 0x30, 0xfe, 0xf7, 0xfa, 0xfa, 0xf0, 0x7d, /// 0x2510 + 0x80, 0x21, 0x40, 0x19, 0xf0, 0x75, 0x20, 0x8f, + 0x08, 0x43, 0x20, 0x87, 0x8c, 0x48, 0x32, 0x21, /// 0x2520 + 0xa0, 0x38, 0x01, 0x67, 0x8a, 0x49, 0x05, 0x20, + 0x20, 0x31, 0x08, 0x72, 0xf8, 0xbd, 0xfe, 0xb5, /// 0x2530 + 0x87, 0x4c, 0x06, 0x46, 0x20, 0x34, 0xe0, 0x7a, + 0x00, 0x28, 0x05, 0xd1, 0x00, 0x2e, 0x01, 0xd0, /// 0x2540 + 0x02, 0x20, 0x00, 0xe0, 0x08, 0x20, 0xe0, 0x72, + 0xc0, 0xb2, 0x84, 0x46, 0x82, 0x07, 0x81, 0x49, /// 0x2550 + 0xf0, 0x01, 0x01, 0x90, 0x7e, 0x39, 0x7d, 0x48, + 0xcf, 0x1d, 0xff, 0x37, 0x20, 0x30, 0xfa, 0x37, /// 0x2560 + 0x00, 0x89, 0xbb, 0x8b, 0x00, 0x93, 0x09, 0x23, + 0x9b, 0x01, 0xcb, 0x18, 0x9d, 0x7c, 0x11, 0x23, /// 0x2570 + 0x5b, 0x01, 0xcb, 0x18, 0x19, 0x78, 0x00, 0x2a, + 0x8e, 0x46, 0x4e, 0xd0, 0x71, 0x46, 0x01, 0x9a, /// 0x2580 + 0x49, 0x08, 0x11, 0x43, 0xc9, 0xb2, 0x19, 0x70, + 0x00, 0x2d, 0x0a, 0xd0, 0x07, 0x2d, 0x10, 0xd3, /// 0x2590 + 0xff, 0x29, 0x11, 0xd0, 0x00, 0x29, 0x3b, 0xd0, + 0x55, 0x29, 0x3b, 0xd0, 0xaa, 0x29, 0x39, 0xd0, /// 0x25a0 + 0x85, 0xe0, 0x48, 0x21, 0x48, 0x43, 0x6c, 0x49, + 0xff, 0xf7, 0x0e, 0xfa, 0x00, 0x99, 0x40, 0x18, /// 0x25b0 + 0xf8, 0x83, 0x6d, 0x1c, 0xa5, 0x74, 0x84, 0xe0, + 0x60, 0x46, 0x80, 0x07, 0x02, 0xd5, 0xff, 0xf7, /// 0x25c0 + 0x78, 0xff, 0x74, 0xe0, 0x61, 0x4d, 0xa0, 0x35, + 0xa9, 0x8a, 0x00, 0x29, 0x1e, 0xd0, 0xc8, 0x07, /// 0x25d0 + 0x02, 0xd0, 0xff, 0xf7, 0xc0, 0xfe, 0x11, 0xe0, + 0x5c, 0x4a, 0x8b, 0x06, 0xd0, 0x79, 0x00, 0x2b, /// 0x25e0 + 0x07, 0xda, 0x00, 0x21, 0xe9, 0x75, 0xfd, 0x21, + 0x08, 0x40, 0xd0, 0x71, 0xff, 0xf7, 0x61, 0xff, /// 0x25f0 + 0x04, 0xe0, 0xc9, 0x06, 0x02, 0xd5, 0xf7, 0x21, + 0x08, 0x40, 0xd0, 0x71, 0x53, 0x48, 0xaa, 0x8a, /// 0x2600 + 0x20, 0x38, 0x01, 0x8f, 0x91, 0x43, 0x01, 0x87, + 0x00, 0x20, 0xa8, 0x82, 0x01, 0x20, 0x02, 0xe0, /// 0x2610 + 0x02, 0x20, 0x00, 0xe0, 0x04, 0x20, 0x20, 0x73, + 0x49, 0xe0, 0x61, 0x46, 0xc9, 0x06, 0x49, 0x0f, /// 0x2620 + 0x45, 0xd0, 0x4b, 0x4a, 0x20, 0x32, 0xd1, 0x7c, + 0x52, 0x7c, 0x00, 0x2d, 0x12, 0xd0, 0x09, 0x2d, /// 0x2630 + 0x26, 0xd0, 0x0a, 0x2d, 0x3d, 0xd3, 0x00, 0x2e, + 0x39, 0xd0, 0x00, 0x20, 0xa0, 0x74, 0x00, 0x2a, /// 0x2640 + 0x26, 0xd0, 0x8a, 0x42, 0x28, 0xd9, 0x18, 0x46, + 0x89, 0x1c, 0xfe, 0xf7, 0x51, 0xfc, 0x00, 0x28, /// 0x2650 + 0x26, 0xd0, 0x2c, 0xe0, 0x00, 0x2e, 0x2a, 0xd1, + 0x01, 0x23, 0xa3, 0x74, 0x00, 0x2a, 0x0c, 0xd0, /// 0x2660 + 0x8a, 0x1a, 0x58, 0x21, 0x92, 0x1c, 0x4a, 0x43, + 0x08, 0x32, 0x50, 0x43, 0x3a, 0x49, 0xff, 0xf7, /// 0x2670 + 0xab, 0xf9, 0x00, 0x99, 0x40, 0x18, 0xf8, 0x83, + 0x23, 0xe0, 0x60, 0x21, 0x48, 0x43, 0xf5, 0xe7, /// 0x2680 + 0x0a, 0x20, 0xa0, 0x74, 0xd0, 0x5c, 0xfe, 0xf7, + 0x3c, 0xfc, 0xb0, 0x42, 0x0f, 0xd0, 0x18, 0xe0, /// 0x2690 + 0x70, 0x46, 0xff, 0xf7, 0x2b, 0xfe, 0xe0, 0x74, + 0x60, 0x7c, 0x40, 0x1c, 0x60, 0x74, 0x10, 0xe0, /// 0x26a0 + 0xe0, 0x7a, 0x40, 0x07, 0x01, 0xd5, 0x08, 0x20, + 0xb5, 0xe7, 0xff, 0xf7, 0x62, 0xfe, 0x01, 0x20, /// 0x26b0 + 0xfe, 0xbd, 0xd0, 0x5c, 0x01, 0x99, 0x40, 0x08, + 0x08, 0x43, 0xd0, 0x54, 0xa0, 0x7c, 0x40, 0x1c, /// 0x26c0 + 0xa0, 0x74, 0x00, 0x20, 0xfe, 0xbd, 0xfe, 0xb5, + 0x21, 0x4c, 0x24, 0x48, 0x20, 0x3c, 0x21, 0x8b, /// 0x26d0 + 0x26, 0x46, 0x00, 0x27, 0x40, 0x3e, 0x81, 0x42, + 0x09, 0xd1, 0xe0, 0x8b, 0x41, 0x1e, 0xe1, 0x83, /// 0x26e0 + 0x03, 0xd3, 0x30, 0x7e, 0x40, 0x1e, 0xf0, 0x75, + 0x00, 0xe1, 0xf7, 0x75, 0xfe, 0xe0, 0x17, 0x48, /// 0x26f0 + 0xa1, 0x8b, 0x20, 0x38, 0x02, 0x46, 0x16, 0x4d, + 0x40, 0x32, 0x80, 0x30, 0x20, 0x35, 0x01, 0x92, /// 0x2700 + 0x00, 0x90, 0x00, 0x29, 0x06, 0xd1, 0x2f, 0x73, + 0x6f, 0x74, 0xaf, 0x74, 0x0f, 0x20, 0xe0, 0x83, /// 0x2710 + 0xfe, 0xf7, 0xdf, 0xf9, 0xaf, 0xe0, 0x41, 0x00, + 0x0e, 0x4a, 0x40, 0x1c, 0x7e, 0x3a, 0x89, 0x18, /// 0x2720 + 0xff, 0x31, 0xc1, 0x31, 0x00, 0x07, 0x89, 0x8e, + 0x00, 0x0f, 0x60, 0x75, 0x20, 0x8b, 0x40, 0x1c, /// 0x2730 + 0x80, 0xb2, 0x20, 0x83, 0x03, 0x28, 0x42, 0xd8, + 0x01, 0x28, 0x11, 0xd0, 0x62, 0x8b, 0x51, 0x18, /// 0x2740 + 0x89, 0xb2, 0x61, 0x83, 0x03, 0x28, 0x10, 0xd1, + 0x10, 0xe0, 0x00, 0x00, 0x20, 0x00, 0x00, 0x20, /// 0x2750 + 0x50, 0x03, 0x00, 0x20, 0xae, 0x01, 0x00, 0x20, + 0x70, 0x17, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, /// 0x2760 + 0x67, 0x83, 0xef, 0x73, 0xaf, 0x73, 0xaf, 0x75, + 0xef, 0x75, 0x84, 0xe0, 0x49, 0x1c, 0x48, 0x08, /// 0x2770 + 0x60, 0x83, 0x01, 0x99, 0x08, 0x81, 0x00, 0x99, + 0x09, 0x78, 0xc9, 0x07, 0x16, 0xd1, 0x5c, 0x49, /// 0x2780 + 0x5c, 0x4a, 0xc9, 0x8f, 0x91, 0x42, 0x02, 0xd2, + 0xfd, 0xf7, 0xa8, 0xfe, 0x0e, 0xe0, 0x5a, 0x48, /// 0x2790 + 0x02, 0x8a, 0x40, 0x21, 0x0a, 0x43, 0x02, 0x82, + 0x02, 0x8a, 0x4f, 0x23, 0x1a, 0x40, 0x39, 0x23, /// 0x27a0 + 0x1b, 0x02, 0xd2, 0x18, 0x02, 0x82, 0x02, 0x8a, + 0x8a, 0x43, 0x02, 0x82, 0x61, 0x8b, 0x53, 0x4a, /// 0x27b0 + 0x48, 0x08, 0x80, 0x18, 0xff, 0xf7, 0x08, 0xf9, + 0x01, 0x99, 0xc8, 0x83, 0x5b, 0xe0, 0x00, 0x98, /// 0x27c0 + 0xc2, 0x7a, 0x06, 0x20, 0x93, 0x07, 0x9b, 0x0f, + 0x98, 0x40, 0x80, 0x1e, 0x52, 0x07, 0x62, 0x8b, /// 0x27d0 + 0x03, 0xd5, 0x10, 0x18, 0x88, 0x42, 0x03, 0xd3, + 0x20, 0xe0, 0x10, 0x1a, 0x88, 0x42, 0x1d, 0xd9, /// 0x27e0 + 0xe8, 0x7b, 0x40, 0x1c, 0xc0, 0xb2, 0xe8, 0x73, + 0x0a, 0x28, 0x53, 0xd8, 0xa8, 0x7d, 0x00, 0x28, /// 0x27f0 + 0x12, 0xd0, 0xa8, 0x7b, 0x05, 0x28, 0x01, 0xd9, + 0x00, 0x20, 0x05, 0xe0, 0x02, 0x28, 0x0b, 0xd9, /// 0x2800 + 0xe8, 0x7d, 0x00, 0x28, 0x06, 0xd0, 0x01, 0x20, + 0xff, 0xf7, 0x91, 0xfe, 0x00, 0x28, 0x41, 0xd1, /// 0x2810 + 0xef, 0x75, 0x01, 0xe0, 0x01, 0x20, 0xe8, 0x75, + 0xaf, 0x73, 0x2c, 0xe0, 0xa8, 0x7b, 0x40, 0x1c, /// 0x2820 + 0xc0, 0xb2, 0xa8, 0x73, 0xa9, 0x7d, 0x00, 0x29, + 0x0c, 0xd0, 0xe9, 0x7d, 0x00, 0x29, 0x03, 0xd0, /// 0x2830 + 0x05, 0x28, 0x0c, 0xd9, 0x01, 0x20, 0x02, 0xe0, + 0x0a, 0x28, 0x08, 0xd9, 0x00, 0x20, 0xff, 0xf7, /// 0x2840 + 0x76, 0xfe, 0x27, 0xe0, 0xe8, 0x7b, 0x02, 0x28, + 0x01, 0xd9, 0x01, 0x20, 0xa8, 0x75, 0xe8, 0x7b, /// 0x2850 + 0x05, 0x28, 0x01, 0xd9, 0x00, 0x20, 0x05, 0xe0, + 0x02, 0x28, 0x0b, 0xd9, 0xe8, 0x7d, 0x00, 0x28, /// 0x2860 + 0x06, 0xd0, 0x01, 0x20, 0xff, 0xf7, 0x63, 0xfe, + 0x00, 0x28, 0x13, 0xd1, 0xef, 0x75, 0x01, 0xe0, /// 0x2870 + 0x01, 0x20, 0xe8, 0x75, 0xef, 0x73, 0x21, 0x7d, + 0x60, 0x7d, 0x81, 0x42, 0x00, 0xd0, 0x4a, 0xe7, /// 0x2880 + 0x30, 0x7e, 0x40, 0x1e, 0xf0, 0x75, 0xa0, 0x8b, + 0x40, 0x1c, 0x80, 0xb2, 0xa0, 0x83, 0xe1, 0x8b, /// 0x2890 + 0x88, 0x42, 0x2b, 0xd9, 0xfe, 0xf7, 0xc2, 0xf8, + 0x00, 0x20, 0xc0, 0x43, 0x20, 0x83, 0xef, 0x72, /// 0x28a0 + 0x70, 0x7f, 0x00, 0x28, 0x01, 0xd0, 0x16, 0x20, + 0x00, 0xe0, 0x05, 0x20, 0x70, 0x77, 0x28, 0x7b, /// 0x28b0 + 0x00, 0x28, 0x01, 0xd0, 0x70, 0x7f, 0x10, 0xe0, + 0xe0, 0x8b, 0x0f, 0x28, 0x04, 0xd9, 0xa1, 0x8b, /// 0x28c0 + 0x40, 0x1a, 0x71, 0x7f, 0x40, 0x18, 0x08, 0xe0, + 0xa0, 0x8b, 0x31, 0x7e, 0x02, 0x1d, 0x8a, 0x42, /// 0x28d0 + 0x02, 0xd2, 0xc0, 0xb2, 0x08, 0x1a, 0x00, 0xe0, + 0x04, 0x20, 0xe0, 0x83, 0xa0, 0x8b, 0xe1, 0x8b, /// 0x28e0 + 0x42, 0x18, 0x31, 0x7e, 0x8a, 0x42, 0x01, 0xd2, + 0x08, 0x1a, 0xe0, 0x83, 0x00, 0x20, 0xfe, 0xbd, /// 0x28f0 + 0x00, 0x00, 0x00, 0x20, 0xbe, 0x04, 0x00, 0x00, + 0x00, 0x34, 0x00, 0x40, 0x00, 0xdc, 0x05, 0x00, /// 0x2900 + 0x10, 0xb5, 0xfe, 0x48, 0x41, 0x7e, 0x0a, 0x07, + 0x03, 0xd5, 0xf7, 0x22, 0x11, 0x40, 0x41, 0x76, /// 0x2910 + 0x10, 0xbd, 0x08, 0x22, 0x11, 0x43, 0x41, 0x76, + 0xfe, 0xf7, 0x71, 0xf9, 0x10, 0xbd, 0xf7, 0x49, /// 0x2920 + 0x00, 0x20, 0xf7, 0x4a, 0x40, 0x31, 0x49, 0x6f, + 0x92, 0x68, 0x06, 0xe0, 0x0b, 0x46, 0x53, 0x40, /// 0x2930 + 0x1b, 0x06, 0x00, 0xd0, 0x40, 0x1c, 0x09, 0x0a, + 0x12, 0x0a, 0x0b, 0x46, 0x13, 0x43, 0xf5, 0xd1, /// 0x2940 + 0x70, 0x47, 0xee, 0x4a, 0x10, 0xb5, 0xef, 0x4b, + 0x40, 0x3a, 0x13, 0x87, 0x20, 0x32, 0x90, 0x76, /// 0x2950 + 0xd1, 0x76, 0x11, 0x46, 0x01, 0x20, 0xa0, 0x31, + 0xc8, 0x72, 0x02, 0x20, 0xfe, 0xf7, 0x39, 0xfb, /// 0x2960 + 0x10, 0xbd, 0xe6, 0x49, 0x10, 0xb5, 0xe8, 0x4a, + 0x40, 0x39, 0x0a, 0x87, 0x20, 0x31, 0x88, 0x76, /// 0x2970 + 0x04, 0x20, 0xa0, 0x31, 0xc8, 0x72, 0x01, 0x20, + 0xfe, 0xf7, 0x2b, 0xfb, 0x10, 0xbd, 0xf8, 0xb5, /// 0x2980 + 0xde, 0x4c, 0xdf, 0x4a, 0xa0, 0x34, 0x80, 0x3a, + 0xe0, 0x7c, 0x25, 0x46, 0x13, 0x46, 0x02, 0x26, /// 0x2990 + 0x20, 0x3d, 0x80, 0x33, 0x00, 0x28, 0x02, 0xd0, + 0x01, 0x28, 0x0b, 0xd0, 0x3e, 0xe0, 0xd8, 0x79, /// 0x29a0 + 0xc0, 0x07, 0x05, 0xd0, 0x31, 0x20, 0xff, 0xf7, + 0xdc, 0xff, 0x01, 0x20, 0xe0, 0x74, 0xf8, 0xbd, /// 0x29b0 + 0xe6, 0x74, 0x0e, 0xe0, 0x28, 0x7b, 0x00, 0x07, + 0xfa, 0xd5, 0xd0, 0x48, 0x60, 0x30, 0x01, 0x78, /// 0x29c0 + 0x31, 0x29, 0xf5, 0xd1, 0x41, 0x78, 0x19, 0x71, + 0x81, 0x78, 0x59, 0x71, 0xc0, 0x78, 0x98, 0x71, /// 0x29d0 + 0xee, 0xe7, 0xe7, 0x7c, 0x78, 0x08, 0xf9, 0x07, + 0x7f, 0x1c, 0xff, 0xb2, 0xe7, 0x74, 0xbc, 0x46, /// 0x29e0 + 0x00, 0x29, 0x0c, 0xd0, 0x29, 0x7b, 0xc9, 0x07, + 0x18, 0xd0, 0x11, 0x18, 0xc7, 0x4f, 0x80, 0x31, /// 0x29f0 + 0x38, 0x18, 0x13, 0x27, 0x7f, 0x01, 0x09, 0x7b, + 0xc0, 0x19, 0x01, 0x75, 0x0e, 0xe0, 0x17, 0x18, /// 0x2a00 + 0x80, 0x37, 0x39, 0x7b, 0x3f, 0x7a, 0xb9, 0x42, + 0x05, 0xd0, 0xc2, 0x07, 0x00, 0xd1, 0x04, 0x20, /// 0x2a10 + 0xff, 0xf7, 0x97, 0xff, 0xf8, 0xbd, 0x60, 0x46, + 0x40, 0x1c, 0xe0, 0x74, 0xe0, 0x7c, 0x08, 0x28, /// 0x2a20 + 0xd7, 0xd3, 0x41, 0x1c, 0xe1, 0x74, 0x08, 0x28, + 0x0c, 0xd0, 0xb9, 0x49, 0x28, 0x7b, 0xc9, 0x6a, /// 0x2a30 + 0xc0, 0x07, 0x0c, 0xd0, 0xb1, 0x48, 0x40, 0x30, + 0x40, 0x6f, 0x98, 0x60, 0x01, 0x20, 0xde, 0x71, /// 0x2a40 + 0x80, 0x04, 0x07, 0xe0, 0xff, 0xf7, 0x6b, 0xff, + 0xc1, 0xb2, 0x00, 0x20, 0xe0, 0xe7, 0x04, 0x20, /// 0x2a50 + 0xd8, 0x71, 0x40, 0x04, 0x01, 0x43, 0xd1, 0x62, + 0xfe, 0xf7, 0x7e, 0xf8, 0xa7, 0x48, 0x07, 0x21, /// 0x2a60 + 0x80, 0x38, 0x81, 0x73, 0xf8, 0xbd, 0xa5, 0x48, + 0x10, 0xb5, 0xaa, 0x49, 0x40, 0x38, 0x81, 0x63, /// 0x2a70 + 0xa2, 0x49, 0x01, 0x20, 0x80, 0x31, 0xc8, 0x72, + 0xfe, 0xf7, 0xab, 0xfa, 0x10, 0xbd, 0x9f, 0x48, /// 0x2a80 + 0x10, 0xb5, 0xa5, 0x49, 0x40, 0x38, 0x01, 0x87, + 0xa1, 0x48, 0x20, 0x30, 0x81, 0x7e, 0x9b, 0x48, /// 0x2a90 + 0x20, 0x38, 0x81, 0x76, 0x01, 0x20, 0xfe, 0xf7, + 0x9c, 0xfa, 0x10, 0xbd, 0x97, 0x48, 0x10, 0xb5, /// 0x2aa0 + 0x60, 0x30, 0x00, 0x7d, 0xff, 0xf7, 0x22, 0xfc, + 0x94, 0x49, 0xc4, 0xb2, 0x74, 0x31, 0x08, 0x46, /// 0x2ab0 + 0x62, 0x1c, 0x7b, 0x38, 0xfe, 0xf7, 0x25, 0xf8, + 0x90, 0x48, 0x0c, 0x21, 0x20, 0x38, 0x01, 0x76, /// 0x2ac0 + 0x20, 0x46, 0xfe, 0xf7, 0x86, 0xfa, 0x10, 0xbd, + 0x8c, 0x49, 0x10, 0xb5, 0x0c, 0x22, 0x20, 0x39, /// 0x2ad0 + 0x0a, 0x76, 0x15, 0x22, 0x4a, 0x76, 0x88, 0x76, + 0x01, 0x20, 0xfe, 0xf7, 0x7a, 0xfa, 0x10, 0xbd, /// 0x2ae0 + 0x8a, 0x48, 0x10, 0xb5, 0x40, 0x30, 0x00, 0x7a, + 0xff, 0xf7, 0x00, 0xfc, 0x04, 0x46, 0x42, 0x1c, /// 0x2af0 + 0x86, 0x49, 0x82, 0x48, 0x48, 0x31, 0xc0, 0x1f, + 0xfe, 0xf7, 0x03, 0xf8, 0x7f, 0x48, 0x0c, 0x21, /// 0x2b00 + 0x20, 0x38, 0x01, 0x76, 0x20, 0x46, 0xfe, 0xf7, + 0x64, 0xfa, 0x10, 0xbd, 0xf0, 0xb5, 0x7c, 0x48, /// 0x2b10 + 0x01, 0x78, 0x49, 0x06, 0x01, 0xd5, 0x00, 0x20, + 0xf0, 0xbd, 0x01, 0x8a, 0x78, 0x48, 0x40, 0x38, /// 0x2b20 + 0x00, 0x88, 0x0b, 0x1a, 0x02, 0xd5, 0x01, 0x25, + 0x59, 0x42, 0x01, 0xe0, 0x00, 0x25, 0x19, 0x46, /// 0x2b30 + 0x72, 0x48, 0x04, 0x26, 0xa0, 0x30, 0x42, 0x7f, + 0x94, 0x08, 0x34, 0x1b, 0x4c, 0x43, 0x61, 0x09, /// 0x2b40 + 0x05, 0xd0, 0x00, 0x2d, 0x01, 0xd0, 0x00, 0x24, + 0x02, 0xe0, 0x02, 0x24, 0x00, 0xe0, 0x01, 0x24, /// 0x2b50 + 0x1c, 0x26, 0x86, 0x57, 0x02, 0x27, 0x7e, 0x40, + 0x20, 0x27, 0xa6, 0x42, 0x05, 0xd1, 0x0f, 0x2a, /// 0x2b60 + 0x01, 0xd2, 0x52, 0x1c, 0x0e, 0xe0, 0x87, 0x77, + 0x0e, 0xe0, 0x86, 0x7f, 0x00, 0x2e, 0x0b, 0xd0, /// 0x2b70 + 0x76, 0x1e, 0x36, 0x06, 0x36, 0x0e, 0x86, 0x77, + 0x06, 0xd1, 0x00, 0x2a, 0x04, 0xd0, 0xfc, 0x26, /// 0x2b80 + 0x52, 0x1e, 0x32, 0x40, 0x42, 0x77, 0xee, 0xe7, + 0x04, 0x77, 0x00, 0x24, 0x00, 0x29, 0x0b, 0xd0, /// 0x2b90 + 0xc4, 0x76, 0x84, 0x76, 0x08, 0x22, 0x02, 0x76, + 0x7f, 0x29, 0x00, 0xd9, 0x7f, 0x21, 0x00, 0x2d, /// 0x2ba0 + 0x00, 0xd0, 0x49, 0x42, 0x48, 0xb2, 0xf0, 0xbd, + 0x82, 0x7e, 0xd2, 0x18, 0x56, 0xb2, 0x86, 0x76, /// 0x2bb0 + 0xc2, 0x7e, 0x52, 0x1c, 0xd3, 0xb2, 0xc3, 0x76, + 0x9a, 0x07, 0xf0, 0xd1, 0x02, 0x7e, 0x96, 0x42, /// 0x2bc0 + 0x02, 0xdd, 0x01, 0x21, 0x00, 0x25, 0x04, 0xe0, + 0x57, 0x42, 0xbe, 0x42, 0x07, 0xda, 0x01, 0x21, /// 0x2bd0 + 0x0d, 0x46, 0x0c, 0x2b, 0x01, 0xd3, 0x52, 0x1c, + 0x02, 0x76, 0x84, 0x76, 0xdc, 0xe7, 0xc4, 0x76, /// 0x2be0 + 0x43, 0x7e, 0x5b, 0x1c, 0xdb, 0xb2, 0x43, 0x76, + 0x20, 0x2b, 0xf6, 0xd9, 0x44, 0x76, 0x04, 0x2a, /// 0x2bf0 + 0xf3, 0xd9, 0x52, 0x1e, 0xf0, 0xe7, 0xf0, 0xb5, + 0x45, 0x48, 0x48, 0x49, 0x80, 0x8f, 0x40, 0x4f, /// 0x2c00 + 0x48, 0x43, 0x8d, 0xb0, 0x00, 0x0c, 0x40, 0x3f, + 0xb8, 0x87, 0x38, 0x88, 0x44, 0x49, 0x41, 0x43, /// 0x2c10 + 0x09, 0x0c, 0xf9, 0x87, 0x43, 0x49, 0x88, 0x42, + 0x05, 0xd2, 0x43, 0x48, 0x01, 0x8b, 0x3f, 0x22, /// 0x2c20 + 0x12, 0x02, 0x91, 0x43, 0x01, 0x83, 0x35, 0x48, + 0x08, 0x90, 0x40, 0x7e, 0x37, 0x4d, 0x41, 0x07, /// 0x2c30 + 0xe8, 0x1d, 0x37, 0x4e, 0xff, 0x30, 0xfa, 0x30, + 0x09, 0x90, 0x30, 0x46, 0x80, 0x30, 0x07, 0x90, /// 0x2c40 + 0xe8, 0x1d, 0x34, 0x46, 0xf9, 0x30, 0xff, 0x35, + 0xa0, 0x34, 0x81, 0x35, 0xc0, 0x36, 0x0a, 0x90, /// 0x2c50 + 0x00, 0x29, 0x6d, 0xda, 0x78, 0x8f, 0xfd, 0xf7, + 0xfc, 0xfd, 0x00, 0x90, 0xb8, 0x80, 0x07, 0x98, /// 0x2c60 + 0x00, 0x78, 0xc0, 0x07, 0x7e, 0xd1, 0x2a, 0x48, + 0xc1, 0x8f, 0x2b, 0x48, 0x4e, 0x38, 0x81, 0x42, /// 0x2c70 + 0x03, 0xd2, 0x38, 0x89, 0xfd, 0xf7, 0x32, 0xfc, + 0x0e, 0xe0, 0x2c, 0x48, 0x02, 0x8a, 0x40, 0x21, /// 0x2c80 + 0x0a, 0x43, 0x02, 0x82, 0x02, 0x8a, 0x4f, 0x23, + 0x1a, 0x40, 0x39, 0x23, 0x1b, 0x02, 0xd2, 0x18, /// 0x2c90 + 0x02, 0x82, 0x02, 0x8a, 0x8a, 0x43, 0x02, 0x82, + 0x1c, 0x48, 0x00, 0x7d, 0x03, 0x28, 0x02, 0xd0, /// 0x2ca0 + 0x00, 0x98, 0xfe, 0xf7, 0x38, 0xfa, 0x1a, 0x48, + 0xc1, 0x8f, 0xff, 0x20, 0xf5, 0x30, 0x81, 0x42, /// 0x2cb0 + 0x04, 0xd2, 0xff, 0x22, 0x01, 0x32, 0xff, 0x20, + 0x21, 0x30, 0x03, 0xe0, 0xff, 0x22, 0x61, 0x32, /// 0x2cc0 + 0xff, 0x20, 0x81, 0x30, 0x84, 0x46, 0xb8, 0x88, + 0x40, 0x28, 0x0b, 0xd2, 0x17, 0x4b, 0x9b, 0x88, /// 0x2cd0 + 0x00, 0x2b, 0x07, 0xd0, 0xff, 0x23, 0xf5, 0x33, + 0x99, 0x42, 0x03, 0xd3, 0x0e, 0x4b, 0x4e, 0x3b, /// 0x2ce0 + 0x99, 0x42, 0x09, 0xd3, 0x60, 0x28, 0x24, 0xd2, + 0x10, 0x4b, 0x9b, 0x88, 0x00, 0x2b, 0x2b, 0xd0, /// 0x2cf0 + 0x09, 0x4b, 0x4e, 0x3b, 0x99, 0x42, 0x27, 0xd3, + 0x00, 0x20, 0x40, 0xe0, 0xf0, 0x02, 0x00, 0x20, /// 0x2d00 + 0x80, 0x00, 0x00, 0x20, 0x0c, 0x20, 0x00, 0x00, + 0x0c, 0x07, 0x00, 0x00, 0x30, 0x01, 0x00, 0x20, /// 0x2d10 + 0x00, 0x00, 0x00, 0x20, 0x0c, 0x09, 0x00, 0x00, + 0x0c, 0x05, 0x00, 0x00, 0x80, 0x20, 0x05, 0x00, /// 0x2d20 + 0xa0, 0x68, 0x06, 0x00, 0x02, 0x02, 0x00, 0x00, + 0x00, 0x30, 0x00, 0x40, 0x00, 0x34, 0x00, 0x40, /// 0x2d30 + 0x6c, 0xe0, 0x60, 0x28, 0x08, 0xd9, 0x90, 0x42, + 0x06, 0xd2, 0xfe, 0x4b, 0x9b, 0x88, 0x01, 0x2b, /// 0x2d40 + 0x02, 0xd0, 0xfd, 0x4b, 0x99, 0x42, 0x27, 0xd3, + 0x80, 0x28, 0x08, 0xd9, 0x90, 0x42, 0x06, 0xd2, /// 0x2d50 + 0xf8, 0x4b, 0x9b, 0x88, 0x01, 0x2b, 0x02, 0xd0, + 0xf7, 0x4b, 0x99, 0x42, 0x1c, 0xd2, 0x60, 0x45, /// 0x2d60 + 0x12, 0xd9, 0x00, 0xe0, 0x3b, 0xe0, 0xf3, 0x49, + 0x8b, 0x88, 0x03, 0x2b, 0x0c, 0xd0, 0xf3, 0x4a, /// 0x2d70 + 0xd0, 0x7f, 0x00, 0x28, 0x05, 0xd0, 0xd0, 0x7f, + 0x40, 0x1e, 0xd0, 0x77, 0x2d, 0xe0, 0xed, 0x49, /// 0x2d80 + 0x00, 0xe0, 0x03, 0x20, 0x88, 0x80, 0x28, 0xe0, + 0xea, 0x49, 0x89, 0x88, 0x00, 0x29, 0x05, 0xd1, /// 0x2d90 + 0x90, 0x42, 0x03, 0xd3, 0x60, 0x45, 0x01, 0xd8, + 0x01, 0x20, 0xf0, 0xe7, 0x08, 0x98, 0x80, 0x7e, /// 0x2da0 + 0xfd, 0xf7, 0xfd, 0xfe, 0x08, 0x98, 0x80, 0x7e, + 0x0a, 0x28, 0x01, 0xd2, 0x01, 0x20, 0x06, 0xe0, /// 0x2db0 + 0x0f, 0x28, 0x01, 0xd3, 0x14, 0x28, 0x01, 0xd2, + 0x02, 0x20, 0x00, 0xe0, 0x03, 0x20, 0xdd, 0x49, /// 0x2dc0 + 0x0a, 0x88, 0xf8, 0x23, 0x9a, 0x43, 0x83, 0x01, + 0xc0, 0x00, 0x1a, 0x43, 0x20, 0x30, 0x02, 0x43, /// 0x2dd0 + 0x0a, 0x80, 0x88, 0x89, 0x06, 0x22, 0x10, 0x43, + 0x88, 0x81, 0xfe, 0xf7, 0x66, 0xf9, 0xff, 0xf7, /// 0x2de0 + 0x95, 0xfe, 0x31, 0x79, 0x8a, 0x07, 0x5f, 0xd1, + 0xb2, 0x79, 0x53, 0x1c, 0xb3, 0x71, 0x03, 0x2a, /// 0x2df0 + 0x5a, 0xd9, 0x7a, 0x7b, 0x12, 0x07, 0x57, 0xd4, + 0x06, 0x22, 0x11, 0x43, 0x31, 0x71, 0x0a, 0x99, /// 0x2e00 + 0x4a, 0x68, 0x07, 0x99, 0x8a, 0x64, 0x00, 0x21, + 0x71, 0x71, 0x4d, 0xe0, 0xff, 0xf7, 0x7e, 0xfe, /// 0x2e10 + 0x08, 0x99, 0x49, 0x7e, 0x8c, 0x46, 0x09, 0x07, + 0x46, 0xd4, 0x07, 0x99, 0xc6, 0x4a, 0x09, 0x8a, /// 0x2e20 + 0x2c, 0x3a, 0x91, 0x42, 0x10, 0xd8, 0x3a, 0x88, + 0x8a, 0x42, 0x07, 0xd8, 0x0a, 0x99, 0xea, 0x6e, /// 0x2e30 + 0x49, 0x68, 0x89, 0x1a, 0x7d, 0x22, 0x12, 0x01, + 0x91, 0x42, 0x03, 0xdb, 0x21, 0x7a, 0x10, 0x22, /// 0x2e40 + 0x11, 0x43, 0x0f, 0xe0, 0x37, 0x20, 0x0e, 0xe0, + 0x21, 0x7a, 0x8a, 0x07, 0x06, 0xd5, 0x0a, 0x9a, /// 0x2e50 + 0xeb, 0x6e, 0x52, 0x68, 0xd2, 0x1a, 0xba, 0x4b, + 0x9a, 0x42, 0x04, 0xdb, 0x10, 0x22, 0x11, 0x43, /// 0x2e60 + 0x49, 0x08, 0x49, 0x00, 0x21, 0x72, 0x71, 0x8b, + 0x00, 0x29, 0x06, 0xd1, 0x79, 0x7b, 0x09, 0x07, /// 0x2e70 + 0x03, 0xd5, 0x04, 0x21, 0xb3, 0x4a, 0xe1, 0x73, + 0x51, 0x71, 0x21, 0x7a, 0x8a, 0x07, 0x13, 0xd4, /// 0x2e80 + 0xca, 0x06, 0x11, 0xd5, 0x08, 0x07, 0x02, 0xd5, + 0x09, 0x98, 0xaf, 0x49, 0xc1, 0x82, 0x60, 0x46, /// 0x2e90 + 0x07, 0x21, 0x08, 0x43, 0x08, 0x99, 0x48, 0x76, + 0x32, 0x20, 0x28, 0x67, 0x0a, 0x98, 0x40, 0x68, /// 0x2ea0 + 0x28, 0x38, 0x68, 0x66, 0x0d, 0xb0, 0xf0, 0xbd, + 0xa4, 0x4a, 0x41, 0x1d, 0x20, 0x3a, 0x94, 0x46, /// 0x2eb0 + 0x0a, 0x29, 0x03, 0xd9, 0x08, 0x99, 0x49, 0x7e, + 0x09, 0x07, 0x0b, 0xd5, 0x00, 0x21, 0x91, 0x72, /// 0x2ec0 + 0x11, 0x7a, 0x00, 0x29, 0x03, 0xd0, 0x62, 0x46, + 0x49, 0x1e, 0x11, 0x72, 0x0a, 0xe0, 0x96, 0x21, /// 0x2ed0 + 0x29, 0x67, 0x07, 0xe0, 0x32, 0x21, 0x29, 0x67, + 0x91, 0x7a, 0xff, 0x29, 0x02, 0xd0, 0x62, 0x46, /// 0x2ee0 + 0x49, 0x1c, 0x91, 0x72, 0x0a, 0x99, 0x99, 0x4a, + 0x49, 0x68, 0x03, 0x91, 0x91, 0x42, 0x04, 0xd2, /// 0x2ef0 + 0x29, 0x6f, 0x96, 0x29, 0x01, 0xd1, 0x64, 0x21, + 0x29, 0x67, 0x21, 0x7a, 0x8f, 0x4a, 0x8e, 0x46, /// 0x2f00 + 0x09, 0x07, 0x20, 0x32, 0x00, 0x29, 0x13, 0xda, + 0x81, 0x1d, 0x0c, 0x29, 0x06, 0xd8, 0x71, 0x46, /// 0x2f10 + 0x89, 0x07, 0x09, 0xd5, 0x71, 0x46, 0x49, 0x08, + 0x49, 0x00, 0x08, 0xe0, 0x51, 0x7f, 0x03, 0x29, /// 0x2f20 + 0x06, 0xd9, 0x71, 0x46, 0x89, 0x07, 0x06, 0xd4, + 0x71, 0x46, 0xfb, 0x23, 0x19, 0x40, 0x21, 0x72, /// 0x2f30 + 0x21, 0x7a, 0x89, 0x07, 0x1a, 0xd5, 0x06, 0x28, + 0x18, 0xdd, 0x91, 0x7f, 0x09, 0x29, 0x06, 0xd9, /// 0x2f40 + 0xe5, 0x22, 0x83, 0x49, 0x92, 0x00, 0xca, 0x87, + 0x7f, 0x4a, 0xb8, 0x3a, 0x07, 0xe0, 0x06, 0x29, /// 0x2f50 + 0x07, 0xd1, 0x3d, 0x22, 0x7e, 0x49, 0x12, 0x01, + 0xca, 0x87, 0x7b, 0x4a, 0x6a, 0x3a, 0x07, 0x99, /// 0x2f60 + 0x0a, 0x82, 0x7b, 0x49, 0x7a, 0x4a, 0xc9, 0x8f, + 0x60, 0x32, 0xd1, 0x70, 0x03, 0x99, 0xaa, 0x6e, /// 0x2f70 + 0x8b, 0x1a, 0x09, 0x9a, 0x16, 0x21, 0x51, 0x5e, + 0xb4, 0x39, 0x8b, 0x42, 0x01, 0xdb, 0x01, 0x28, /// 0x2f80 + 0x01, 0xd0, 0x41, 0x1c, 0x00, 0xd1, 0x00, 0x20, + 0x07, 0x99, 0x3a, 0x88, 0x09, 0x8a, 0xff, 0x31, /// 0x2f90 + 0xd5, 0x31, 0x8a, 0x42, 0x1b, 0xd9, 0x61, 0x46, + 0x09, 0x7d, 0x0a, 0x29, 0x02, 0xd3, 0x03, 0x98, /// 0x2fa0 + 0xa8, 0x66, 0x7f, 0xe7, 0x62, 0x46, 0x49, 0x1c, + 0x11, 0x75, 0x60, 0x71, 0x00, 0x28, 0x05, 0xd0, /// 0x2fb0 + 0x08, 0x9a, 0x01, 0x21, 0x51, 0x77, 0x01, 0x1d, + 0x08, 0x29, 0x1d, 0xd8, 0x21, 0x79, 0x02, 0x22, /// 0x2fc0 + 0x11, 0x43, 0x21, 0x71, 0xca, 0x07, 0x05, 0xd0, + 0x04, 0x22, 0x11, 0x43, 0x04, 0xe0, 0x00, 0x21, /// 0x2fd0 + 0x62, 0x46, 0xe9, 0xe7, 0xfb, 0x22, 0x11, 0x40, + 0x21, 0x71, 0x49, 0x07, 0xe1, 0xd4, 0xc3, 0x21, /// 0x2fe0 + 0x89, 0x00, 0x29, 0x87, 0x55, 0x49, 0xc0, 0x39, + 0x88, 0x76, 0x01, 0x20, 0xfd, 0xf7, 0xf1, 0xff, /// 0x2ff0 + 0x70, 0x8b, 0x40, 0x1c, 0x70, 0x83, 0x55, 0xe7, + 0x21, 0x79, 0xfd, 0x22, 0x11, 0x40, 0x21, 0x71, /// 0x3000 + 0x4a, 0x07, 0xe7, 0xd4, 0xeb, 0xe7, 0x4d, 0x48, + 0x10, 0xb5, 0x0c, 0x21, 0xc0, 0x38, 0x01, 0x76, /// 0x3010 + 0x38, 0x21, 0x41, 0x76, 0x0a, 0x21, 0x81, 0x76, + 0x4d, 0x49, 0x40, 0x31, 0x09, 0x8f, 0xc1, 0x76, /// 0x3020 + 0x09, 0x0a, 0x01, 0x77, 0x45, 0x49, 0x10, 0x20, + 0x20, 0x39, 0xc8, 0x72, 0x03, 0x20, 0xfd, 0xf7, /// 0x3030 + 0xd0, 0xff, 0x10, 0xbd, 0x41, 0x48, 0x10, 0xb5, + 0x0c, 0x21, 0xc0, 0x38, 0x01, 0x76, 0x38, 0x21, /// 0x3040 + 0x41, 0x76, 0x3b, 0x21, 0x81, 0x76, 0x02, 0x21, + 0xc1, 0x76, 0xbb, 0x21, 0x01, 0x77, 0x3b, 0x49, /// 0x3050 + 0x10, 0x20, 0x20, 0x39, 0xc8, 0x72, 0x03, 0x20, + 0xfd, 0xf7, 0xbb, 0xff, 0x10, 0xbd, 0x37, 0x4a, /// 0x3060 + 0x10, 0xb5, 0x0c, 0x23, 0xc0, 0x3a, 0x13, 0x76, + 0xa4, 0x23, 0x53, 0x76, 0x90, 0x76, 0x33, 0x48, /// 0x3070 + 0x08, 0x22, 0xa5, 0x38, 0xfd, 0xf7, 0x45, 0xfd, + 0x30, 0x49, 0x10, 0x20, 0x20, 0x39, 0xc8, 0x72, /// 0x3080 + 0x0c, 0x20, 0xfd, 0xf7, 0xa6, 0xff, 0x10, 0xbd, + 0x10, 0xb5, 0x32, 0xa2, 0x07, 0xca, 0xa2, 0xb0, /// 0x3090 + 0x6b, 0x46, 0x07, 0xc3, 0x2e, 0x49, 0x08, 0x22, + 0x14, 0x31, 0x0c, 0x46, 0x1d, 0xa8, 0xfd, 0xf7, /// 0x30a0 + 0x30, 0xfd, 0x08, 0x22, 0x69, 0x46, 0x1f, 0xa8, + 0xfd, 0xf7, 0x2b, 0xfd, 0x03, 0xa8, 0xfe, 0xf7, /// 0x30b0 + 0xe3, 0xfa, 0x10, 0x22, 0x1d, 0xa9, 0x03, 0xa8, + 0xfe, 0xf7, 0x24, 0xfc, 0x24, 0x49, 0x03, 0xa8, /// 0x30c0 + 0xb0, 0x31, 0xfe, 0xf7, 0xf1, 0xfb, 0x21, 0x46, + 0x08, 0x20, 0xff, 0xf7, 0xc8, 0xff, 0x22, 0xb0, /// 0x30d0 + 0x10, 0xbd, 0x1f, 0x48, 0x10, 0xb5, 0x40, 0x30, + 0x00, 0x7c, 0xff, 0xf7, 0x07, 0xf9, 0x04, 0x46, /// 0x30e0 + 0x42, 0x1c, 0x1b, 0x49, 0x15, 0x48, 0x50, 0x31, + 0xa7, 0x38, 0xfd, 0xf7, 0x0a, 0xfd, 0x13, 0x48, /// 0x30f0 + 0x0c, 0x21, 0xc0, 0x38, 0x01, 0x76, 0x11, 0x49, + 0x10, 0x20, 0x20, 0x39, 0xc8, 0x72, 0x20, 0x46, /// 0x3100 + 0xfd, 0xf7, 0x67, 0xff, 0x10, 0xbd, 0xfe, 0xb5, + 0x11, 0x4c, 0x80, 0x34, 0x20, 0x7e, 0x25, 0x46, /// 0x3110 + 0x40, 0x1e, 0xc2, 0xb2, 0x09, 0x48, 0x22, 0x76, + 0x20, 0x38, 0x20, 0x35, 0x02, 0x90, 0x00, 0x2a, /// 0x3120 + 0x31, 0xd0, 0x0b, 0x49, 0x9c, 0x20, 0x40, 0x5a, + 0x40, 0x31, 0x00, 0x91, 0x08, 0x2a, 0x56, 0xd3, /// 0x3130 + 0x91, 0x07, 0x15, 0xe0, 0x00, 0x34, 0x00, 0x40, + 0xbe, 0x04, 0x00, 0x00, 0x90, 0x03, 0x00, 0x20, /// 0x3140 + 0x88, 0x13, 0x00, 0x00, 0x20, 0x38, 0x00, 0x40, + 0x6c, 0x07, 0x00, 0x00, 0x58, 0x1b, 0x00, 0x00, /// 0x3150 + 0x00, 0x00, 0x00, 0x20, 0x58, 0x69, 0x61, 0x6f, + 0x6d, 0x69, 0x52, 0x78, 0x00, 0x00, 0x00, 0x00, /// 0x3160 + 0x10, 0xd1, 0x00, 0x99, 0x63, 0x8b, 0x09, 0x88, + 0x59, 0x18, 0x89, 0xb2, 0x61, 0x83, 0x00, 0x9b, /// 0x3170 + 0x5b, 0x8f, 0xc0, 0x18, 0x80, 0xb2, 0xa0, 0x83, + 0x08, 0x2a, 0x03, 0xd1, 0x09, 0x09, 0x61, 0x83, /// 0x3180 + 0x00, 0x09, 0xa0, 0x83, 0xfe, 0xbd, 0x02, 0x7b, + 0xfa, 0x48, 0xfd, 0x21, 0x00, 0x7a, 0xd3, 0x07, /// 0x3190 + 0x01, 0x40, 0x00, 0x2b, 0x16, 0xd0, 0x02, 0x07, + 0xf4, 0xd5, 0xc2, 0x07, 0x01, 0xd0, 0x40, 0x21, /// 0x31a0 + 0x0d, 0xe0, 0x82, 0x07, 0x01, 0xd5, 0x29, 0x72, + 0xfe, 0xbd, 0x41, 0x07, 0x06, 0xd4, 0xf7, 0x21, /// 0x31b0 + 0x08, 0x40, 0x28, 0x72, 0xf1, 0x48, 0xf0, 0x49, + 0xc1, 0x82, 0xfe, 0xbd, 0x80, 0x21, 0x08, 0x43, /// 0x31c0 + 0x28, 0x72, 0xfe, 0xbd, 0x92, 0x07, 0xfc, 0xd5, + 0x02, 0x07, 0xfa, 0xd5, 0xc2, 0x07, 0xf8, 0xd1, /// 0x31d0 + 0x82, 0x07, 0xf6, 0xd5, 0x40, 0x06, 0xf4, 0xd5, + 0xbf, 0x20, 0x01, 0x40, 0xe3, 0xe7, 0x06, 0x2a, /// 0x31e0 + 0xef, 0xd8, 0xfd, 0xf7, 0x36, 0xfb, 0x06, 0x46, + 0x20, 0x78, 0xe4, 0x4f, 0xc0, 0x06, 0x40, 0x3f, /// 0x31f0 + 0x00, 0x28, 0x14, 0xda, 0x00, 0x98, 0x40, 0x8f, + 0xfd, 0xf7, 0x2b, 0xfb, 0x40, 0x09, 0x0a, 0xd0, /// 0x3200 + 0x20, 0x28, 0x01, 0xd3, 0x1f, 0x20, 0x06, 0xe0, + 0xb9, 0x7e, 0x81, 0x42, 0x01, 0xd2, 0x40, 0x1e, /// 0x3210 + 0x01, 0xe0, 0x81, 0x42, 0x00, 0xd9, 0xb8, 0x76, + 0xb8, 0x7e, 0xfd, 0xf7, 0xc0, 0xfc, 0xd8, 0x48, /// 0x3220 + 0x01, 0x88, 0xc9, 0x04, 0x0b, 0xd5, 0x40, 0x79, + 0x21, 0x78, 0xc0, 0x06, 0xc0, 0x0e, 0xc9, 0x06, /// 0x3230 + 0x03, 0xd5, 0xc1, 0x00, 0x08, 0x1a, 0x86, 0x19, + 0x01, 0xe0, 0xc1, 0x00, 0x0e, 0x1a, 0xcd, 0x49, /// 0x3240 + 0x60, 0x8b, 0x20, 0x31, 0x48, 0x85, 0x8e, 0x85, + 0x69, 0x22, 0x56, 0x43, 0x70, 0x43, 0x80, 0x0b, /// 0x3250 + 0xc8, 0x85, 0x00, 0x22, 0x62, 0x83, 0xa2, 0x83, + 0xca, 0x4a, 0x92, 0x8b, 0xd2, 0x07, 0x06, 0xd0, /// 0x3260 + 0xc9, 0x4a, 0x93, 0x88, 0xdb, 0x43, 0x9b, 0x07, + 0x03, 0xd0, 0x00, 0x22, 0x0a, 0xe0, 0x07, 0x22, /// 0x3270 + 0x08, 0xe0, 0xbb, 0x7e, 0x1a, 0x2b, 0x01, 0xd3, + 0x05, 0x22, 0x03, 0xe0, 0x12, 0x88, 0x12, 0x06, /// 0x3280 + 0x92, 0x0f, 0x52, 0x1c, 0xbb, 0x4f, 0xd6, 0xb2, + 0x62, 0x76, 0x73, 0x00, 0xa0, 0x3f, 0xda, 0x19, /// 0x3290 + 0x60, 0x32, 0x13, 0x7a, 0x43, 0x43, 0xdb, 0x09, + 0x07, 0x2e, 0x21, 0xd0, 0x09, 0x20, 0x10, 0x56, /// 0x32a0 + 0x0a, 0x22, 0x50, 0x43, 0xc0, 0x18, 0x00, 0xd5, + 0x00, 0x20, 0xb8, 0x4e, 0xb1, 0x4a, 0x33, 0x46, /// 0x32b0 + 0xa0, 0x3a, 0x90, 0x84, 0xff, 0x33, 0x22, 0x7a, + 0x81, 0x33, 0xff, 0x36, 0xa1, 0x36, 0x01, 0x93, /// 0x32c0 + 0x31, 0x2a, 0x11, 0xd0, 0x00, 0x21, 0x21, 0x76, + 0xaa, 0x49, 0xab, 0x4a, 0xa0, 0x39, 0x89, 0x8f, /// 0x32d0 + 0x87, 0x3a, 0x91, 0x42, 0x5d, 0xd8, 0xae, 0x49, + 0x88, 0x42, 0x5f, 0xd9, 0x08, 0x46, 0x5d, 0xe0, /// 0x32e0 + 0xa4, 0x48, 0x32, 0x38, 0x40, 0x7a, 0xdb, 0xe7, + 0x01, 0x22, 0x22, 0x76, 0x02, 0x9b, 0xda, 0x72, /// 0x32f0 + 0x2a, 0x7a, 0x13, 0x07, 0x10, 0xd5, 0xa1, 0x49, + 0x92, 0x07, 0x80, 0x31, 0x00, 0x2a, 0x05, 0xda, /// 0x3300 + 0x01, 0x22, 0x02, 0x92, 0x8a, 0x7f, 0x52, 0x1c, + 0x8a, 0x77, 0x16, 0xe0, 0x02, 0x22, 0x02, 0x92, /// 0x3310 + 0x4a, 0x7f, 0x52, 0x1c, 0x4a, 0x77, 0x10, 0xe0, + 0x00, 0x22, 0x02, 0x92, 0x0a, 0x79, 0x93, 0x07, /// 0x3320 + 0x0b, 0xd1, 0x00, 0x9b, 0x5b, 0x7b, 0x1b, 0x07, + 0x07, 0xd5, 0x06, 0x23, 0x1a, 0x43, 0x0a, 0x71, /// 0x3330 + 0x98, 0x4a, 0x52, 0x68, 0xa2, 0x64, 0x00, 0x22, + 0x4a, 0x71, 0x21, 0x78, 0x09, 0x06, 0x00, 0xd5, /// 0x3340 + 0x40, 0x08, 0xa1, 0x7a, 0x7d, 0x22, 0xd2, 0x00, + 0x51, 0x43, 0x00, 0x04, 0xfe, 0xf7, 0x3c, 0xfb, /// 0x3350 + 0x91, 0x49, 0x07, 0x46, 0x88, 0x42, 0x00, 0xd9, + 0x0f, 0x46, 0xe7, 0x84, 0x28, 0x79, 0xc0, 0x07, /// 0x3360 + 0x09, 0xd0, 0x84, 0x48, 0x01, 0x21, 0xa0, 0x38, + 0xc2, 0x6a, 0x49, 0x04, 0x0a, 0x43, 0xc2, 0x62, /// 0x3370 + 0x08, 0x46, 0xfd, 0xf7, 0xf1, 0xfb, 0x28, 0x79, + 0x40, 0x07, 0x00, 0xd5, 0x21, 0xe7, 0x01, 0x98, /// 0x3380 + 0x86, 0x49, 0x01, 0x87, 0x02, 0x98, 0xb0, 0x76, + 0x38, 0x0a, 0xf0, 0x76, 0x37, 0x77, 0x03, 0x20, /// 0x3390 + 0x0d, 0xe0, 0x83, 0x49, 0x88, 0x42, 0x00, 0xd9, + 0x08, 0x46, 0x40, 0x08, 0xc0, 0x01, 0x81, 0x49, /// 0x33a0 + 0xfe, 0xf7, 0x12, 0xfb, 0x01, 0x99, 0x80, 0x4a, + 0x0a, 0x87, 0xb0, 0x76, 0x01, 0x20, 0xfd, 0xf7, /// 0x33b0 + 0x10, 0xfe, 0xfe, 0xbd, 0xf8, 0xb5, 0x6f, 0x4a, + 0x7c, 0x49, 0x60, 0x3a, 0x10, 0x88, 0x48, 0x43, /// 0x33c0 + 0x7b, 0x49, 0x88, 0x42, 0x31, 0xd8, 0x6d, 0x4b, + 0x6e, 0x4c, 0x40, 0x3b, 0x59, 0x7e, 0xc8, 0x43, /// 0x33d0 + 0x85, 0x07, 0x78, 0x48, 0x11, 0xd1, 0x86, 0x8f, + 0xff, 0x27, 0x25, 0x37, 0x65, 0x14, 0xbe, 0x42, /// 0x33e0 + 0x08, 0xd9, 0xa1, 0x8a, 0x29, 0x43, 0xa1, 0x82, + 0x41, 0x6b, 0x80, 0x22, 0x11, 0x43, 0x41, 0x63, /// 0x33f0 + 0x10, 0x46, 0x5e, 0xe0, 0xa6, 0x8a, 0xae, 0x43, + 0xa6, 0x82, 0x49, 0x1e, 0xc9, 0xb2, 0x59, 0x76, /// 0x3400 + 0x8b, 0x07, 0x01, 0x25, 0x00, 0x2b, 0x11, 0xda, + 0x20, 0x8a, 0xd0, 0x84, 0x80, 0xb2, 0xcb, 0x28, /// 0x3410 + 0x01, 0xd9, 0xcb, 0x20, 0x20, 0x82, 0xa0, 0x8b, + 0x08, 0x21, 0x08, 0x43, 0xa0, 0x83, 0x64, 0x20, /// 0x3420 + 0xfd, 0xf7, 0x02, 0xfb, 0xa0, 0x8b, 0x28, 0x43, + 0xa0, 0x83, 0xf8, 0xbd, 0x61, 0x4b, 0xcf, 0x07, /// 0x3430 + 0x40, 0x33, 0xdb, 0x8c, 0x3f, 0x26, 0x01, 0x21, + 0x36, 0x02, 0x19, 0x43, 0x00, 0x2f, 0x12, 0xd0, /// 0x3440 + 0x5d, 0x4a, 0x93, 0x42, 0x00, 0xd9, 0x11, 0x46, + 0x21, 0x82, 0x21, 0x8b, 0x0f, 0x22, 0xb1, 0x43, /// 0x3450 + 0x12, 0x02, 0x89, 0x18, 0x21, 0x83, 0xc0, 0x8f, + 0xff, 0x21, 0xf5, 0x31, 0x88, 0x42, 0xe4, 0xd2, /// 0x3460 + 0x49, 0x48, 0x85, 0x80, 0xf8, 0xbd, 0x21, 0x82, + 0x21, 0x8b, 0x31, 0x43, 0x21, 0x83, 0xa1, 0x8b, /// 0x3470 + 0x01, 0x23, 0x5b, 0x02, 0x19, 0x43, 0xa1, 0x83, + 0x51, 0x7b, 0x0a, 0x07, 0x43, 0x49, 0x06, 0xd4, /// 0x3480 + 0x4e, 0x4a, 0x14, 0x78, 0x04, 0x23, 0x1c, 0x43, + 0x14, 0x70, 0x0b, 0x75, 0x06, 0xe0, 0x0a, 0x7d, /// 0x3490 + 0x00, 0x2a, 0x03, 0xd1, 0x3f, 0x4a, 0x52, 0x68, + 0x0a, 0x61, 0x0d, 0x75, 0x35, 0x49, 0x10, 0x23, /// 0x34a0 + 0x20, 0x39, 0x0a, 0x78, 0x1a, 0x43, 0x0a, 0x70, + 0xc1, 0x6a, 0x40, 0x22, 0x11, 0x43, 0xc1, 0x62, /// 0x34b0 + 0x10, 0x46, 0xfd, 0xf7, 0x51, 0xfb, 0xf8, 0xbd, + 0xf0, 0xb5, 0x30, 0x48, 0x8b, 0xb0, 0x40, 0x38, /// 0x34c0 + 0x40, 0x7e, 0x80, 0x07, 0x03, 0xd0, 0xff, 0xf7, + 0x75, 0xff, 0x0b, 0xb0, 0xf0, 0xbd, 0x29, 0x4c, /// 0x34d0 + 0x30, 0x49, 0x20, 0x34, 0x20, 0x79, 0x26, 0x46, + 0x82, 0x07, 0x40, 0x3e, 0x05, 0x91, 0x00, 0x2a, /// 0x34e0 + 0x19, 0xda, 0x49, 0x68, 0xb2, 0x6c, 0x89, 0x1a, + 0xff, 0x22, 0x2d, 0x32, 0x91, 0x42, 0x12, 0xd9, /// 0x34f0 + 0x61, 0x79, 0x03, 0x29, 0x01, 0xd2, 0x04, 0x21, + 0x0b, 0xe0, 0x2e, 0x49, 0x01, 0x20, 0xca, 0x6a, /// 0x3500 + 0x00, 0x03, 0x02, 0x43, 0xca, 0x62, 0xfd, 0xf7, + 0x27, 0xfb, 0x20, 0x79, 0xfd, 0x21, 0x08, 0x40, /// 0x3510 + 0x01, 0x21, 0x08, 0x43, 0x20, 0x71, 0x70, 0x78, + 0x41, 0x06, 0x12, 0xd5, 0x05, 0x99, 0xb2, 0x6c, /// 0x3520 + 0x49, 0x68, 0x89, 0x1a, 0xff, 0x22, 0xf5, 0x32, + 0x91, 0x42, 0x0a, 0xd9, 0xbf, 0x21, 0x08, 0x40, /// 0x3530 + 0x70, 0x70, 0x20, 0x49, 0xff, 0x20, 0xca, 0x6a, + 0x01, 0x30, 0x02, 0x43, 0xca, 0x62, 0xfd, 0xf7, /// 0x3540 + 0x0b, 0xfb, 0x30, 0x7e, 0x00, 0x28, 0x02, 0xd0, + 0xff, 0xf7, 0xdd, 0xfd, 0xbd, 0xe7, 0x05, 0x98, /// 0x3550 + 0x0a, 0x4d, 0x40, 0x68, 0x80, 0x3d, 0x00, 0x90, + 0xa9, 0x6e, 0x16, 0x22, 0x41, 0x1a, 0x07, 0x48, /// 0x3560 + 0x08, 0x90, 0x82, 0x5e, 0x00, 0x98, 0x91, 0x42, + 0x2a, 0xdb, 0xa8, 0x66, 0x48, 0x20, 0x30, 0x76, /// 0x3570 + 0xea, 0xe7, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x20, + 0xdc, 0x05, 0x00, 0x00, 0x30, 0x03, 0x00, 0x20, /// 0x3580 + 0x20, 0x38, 0x00, 0x40, 0x00, 0x30, 0x00, 0x40, + 0x00, 0x34, 0x00, 0x40, 0x30, 0x01, 0x00, 0x20, /// 0x3590 + 0xe8, 0x26, 0x00, 0x00, 0x30, 0x02, 0x00, 0x20, + 0xff, 0xff, 0x00, 0x00, 0x0c, 0x31, 0x00, 0x00, /// 0x35a0 + 0xd0, 0x4d, 0x00, 0x00, 0x88, 0x13, 0x00, 0x00, + 0x0c, 0x04, 0x00, 0x00, 0x41, 0x0a, 0x00, 0x00, /// 0x35b0 + 0xff, 0x8f, 0x70, 0x00, 0x00, 0x00, 0x00, 0x20, + 0xe3, 0x02, 0x00, 0x00, 0x40, 0x6c, 0x00, 0x40, /// 0x35c0 + 0x69, 0x6e, 0x42, 0x1a, 0x29, 0x6f, 0xf7, 0x48, + 0x04, 0x90, 0x8a, 0x42, 0x72, 0xdb, 0x00, 0x98, /// 0x35d0 + 0x68, 0x66, 0x70, 0x78, 0x01, 0x07, 0x0b, 0xd5, + 0xf7, 0x21, 0x08, 0x40, 0x32, 0x21, 0x29, 0x67, /// 0x35e0 + 0x10, 0x21, 0x08, 0x43, 0x70, 0x70, 0x00, 0x20, + 0xa0, 0x81, 0xff, 0xf7, 0x72, 0xfd, 0x6c, 0xe7, /// 0x35f0 + 0x23, 0x79, 0xdf, 0x22, 0x19, 0x07, 0x00, 0x29, + 0x0e, 0xda, 0xb1, 0x78, 0x8f, 0x06, 0x0b, 0xd5, /// 0x3600 + 0x11, 0x40, 0xb1, 0x70, 0x32, 0x21, 0x29, 0x67, + 0x40, 0x21, 0x08, 0x43, 0x70, 0x70, 0x00, 0x98, /// 0x3610 + 0xb0, 0x64, 0xff, 0xf7, 0x39, 0xfd, 0x58, 0xe7, + 0x81, 0x06, 0x07, 0xd5, 0x10, 0x40, 0x70, 0x70, /// 0x3620 + 0x32, 0x20, 0x28, 0x67, 0xff, 0x20, 0xfe, 0xf7, + 0xa9, 0xf9, 0x4e, 0xe7, 0x58, 0x07, 0x0d, 0xd5, /// 0x3630 + 0xfb, 0x20, 0x03, 0x40, 0x23, 0x71, 0x32, 0x20, + 0x28, 0x67, 0xff, 0xf7, 0xfb, 0xfc, 0x05, 0x98, /// 0x3640 + 0x40, 0x68, 0xb0, 0x64, 0x60, 0x79, 0x40, 0x1c, + 0x60, 0x71, 0x3e, 0xe7, 0x18, 0x07, 0x32, 0xd5, /// 0x3650 + 0xb0, 0x78, 0x07, 0x90, 0xc0, 0x07, 0x2e, 0xd0, + 0xd3, 0x48, 0x15, 0x21, 0xc0, 0x8f, 0x48, 0x43, /// 0x3660 + 0xfa, 0x21, 0xfe, 0xf7, 0xb1, 0xf9, 0x07, 0x46, + 0xcf, 0x48, 0x64, 0x21, 0x40, 0x30, 0x09, 0x90, /// 0x3670 + 0x00, 0x8f, 0xfe, 0xf7, 0xa9, 0xf9, 0x07, 0x99, + 0x38, 0x1a, 0x49, 0x08, 0x49, 0x00, 0x1c, 0x30, /// 0x3680 + 0xb1, 0x70, 0x00, 0x28, 0x00, 0xdc, 0x40, 0x42, + 0x14, 0x28, 0x33, 0xdb, 0x32, 0x20, 0x28, 0x67, /// 0x3690 + 0x09, 0x98, 0x02, 0x88, 0xc3, 0x48, 0x40, 0x30, + 0xc2, 0x81, 0x02, 0x22, 0x11, 0x43, 0xb1, 0x70, /// 0x36a0 + 0x00, 0x99, 0x01, 0x61, 0xc0, 0x48, 0xa0, 0x30, + 0x00, 0x79, 0x40, 0x07, 0x9f, 0xd4, 0xff, 0xf7, /// 0x36b0 + 0xaa, 0xfc, 0x0a, 0xe7, 0x1e, 0xe0, 0xbc, 0x48, + 0x00, 0x8f, 0x00, 0x28, 0x0c, 0xd0, 0x04, 0x98, /// 0x36c0 + 0x40, 0x7a, 0x07, 0x28, 0x08, 0xd2, 0x04, 0x98, + 0x80, 0x7a, 0x0a, 0x28, 0x16, 0xd2, 0xff, 0xf7, /// 0x36d0 + 0x1d, 0xfa, 0xc0, 0x1d, 0x0e, 0x28, 0x0d, 0xd9, + 0x04, 0x99, 0x00, 0x20, 0x48, 0x72, 0x08, 0x7a, /// 0x36e0 + 0x00, 0x28, 0x01, 0xd0, 0x40, 0x1e, 0x08, 0x72, + 0x05, 0x98, 0x40, 0x68, 0x68, 0x66, 0xff, 0xf7, /// 0x36f0 + 0x82, 0xfa, 0xea, 0xe6, 0xac, 0x48, 0x00, 0x8f, + 0x00, 0x28, 0x8c, 0xd0, 0x04, 0x98, 0x04, 0x99, /// 0x3700 + 0x40, 0x7a, 0x08, 0x23, 0x40, 0x1c, 0x48, 0x72, + 0xa7, 0x49, 0x80, 0x26, 0x08, 0x8f, 0x0a, 0x46, /// 0x3710 + 0x87, 0x06, 0x20, 0x32, 0x00, 0x2f, 0x3a, 0xd0, + 0xc7, 0x07, 0x05, 0xd0, 0x01, 0x20, 0xa0, 0x82, /// 0x3720 + 0x04, 0x99, 0xc8, 0x72, 0x03, 0x20, 0x47, 0xe0, + 0x87, 0x07, 0x06, 0xd5, 0x02, 0x20, 0xa0, 0x82, /// 0x3730 + 0x04, 0x99, 0x01, 0x20, 0xc8, 0x72, 0x05, 0x20, + 0x3e, 0xe0, 0x47, 0x07, 0x04, 0xd5, 0x04, 0x22, /// 0x3740 + 0x90, 0x43, 0x08, 0x87, 0x02, 0x20, 0x37, 0xe0, + 0x07, 0x07, 0x03, 0xd5, 0x98, 0x43, 0x08, 0x87, /// 0x3750 + 0x01, 0x20, 0x31, 0xe0, 0xc7, 0x06, 0x0e, 0xd5, + 0x92, 0x79, 0x52, 0x06, 0x05, 0xd5, 0x10, 0x20, /// 0x3760 + 0xa0, 0x82, 0x04, 0x99, 0x01, 0x20, 0xc8, 0x72, + 0x02, 0xe0, 0x10, 0x22, 0x90, 0x43, 0x08, 0x87, /// 0x3770 + 0xff, 0xf7, 0xb6, 0xf9, 0xa9, 0xe6, 0x87, 0x06, + 0x09, 0xd5, 0x20, 0x20, 0xa0, 0x82, 0x04, 0x99, /// 0x3780 + 0x01, 0x20, 0xc8, 0x72, 0xa0, 0x7d, 0x40, 0x1e, + 0x30, 0x43, 0xc0, 0xb2, 0x14, 0xe0, 0xc0, 0x24, /// 0x3790 + 0x04, 0x40, 0x1b, 0xd0, 0xc0, 0x2c, 0x05, 0xd1, + 0xd3, 0x79, 0x5b, 0x07, 0x01, 0xd5, 0x40, 0x24, /// 0x37a0 + 0x00, 0xe0, 0x80, 0x24, 0x63, 0x06, 0x0a, 0xd5, + 0x40, 0x23, 0x98, 0x43, 0x08, 0x87, 0xd0, 0x79, /// 0x37b0 + 0xfb, 0x21, 0x08, 0x40, 0xd0, 0x71, 0x06, 0x20, + 0xff, 0xf7, 0x86, 0xf9, 0x85, 0xe6, 0xd0, 0x79, /// 0x37c0 + 0x04, 0x21, 0x08, 0x43, 0xd0, 0x71, 0xff, 0xf7, + 0x69, 0xf9, 0x7e, 0xe6, 0xc2, 0x05, 0x06, 0xd5, /// 0x37d0 + 0xff, 0x22, 0x01, 0x32, 0x90, 0x43, 0x08, 0x87, + 0xff, 0xf7, 0x51, 0xf9, 0x75, 0xe6, 0x82, 0x05, /// 0x37e0 + 0x87, 0xd5, 0x05, 0x9a, 0x6c, 0x6e, 0x52, 0x68, + 0x14, 0x1b, 0x64, 0x2c, 0xc2, 0xda, 0xac, 0x6e, /// 0x37f0 + 0x16, 0x25, 0xa4, 0x1a, 0x08, 0x9a, 0x55, 0x5f, + 0x62, 0x19, 0xff, 0x24, 0x5f, 0x34, 0xa2, 0x42, /// 0x3800 + 0xb8, 0xdd, 0x01, 0x22, 0x52, 0x02, 0x90, 0x43, + 0x08, 0x87, 0x68, 0x48, 0x83, 0x73, 0xff, 0xf7, /// 0x3810 + 0x2a, 0xf9, 0x5a, 0xe6, 0x65, 0x48, 0x10, 0xb5, + 0x65, 0x49, 0x40, 0x30, 0x81, 0x63, 0x62, 0x48, /// 0x3820 + 0x80, 0x30, 0xc1, 0x78, 0x61, 0x48, 0x60, 0x30, + 0xc1, 0x76, 0x5e, 0x49, 0x01, 0x20, 0xc8, 0x72, /// 0x3830 + 0x02, 0x20, 0xfd, 0xf7, 0xce, 0xfb, 0x10, 0xbd, + 0xf0, 0xb5, 0x09, 0x22, 0x5d, 0x49, 0x59, 0x4c, /// 0x3840 + 0x92, 0x01, 0x8a, 0x18, 0x80, 0x3c, 0x15, 0x7b, + 0x20, 0x7f, 0x13, 0x22, 0x52, 0x01, 0xc3, 0x07, /// 0x3850 + 0x8a, 0x18, 0x8d, 0xb0, 0x00, 0x2b, 0x0e, 0xd0, + 0x00, 0x2d, 0x0c, 0xd1, 0xd1, 0x7c, 0x49, 0x1c, /// 0x3860 + 0xc9, 0xb2, 0xd1, 0x74, 0x03, 0x29, 0x02, 0xd2, + 0x40, 0x1e, 0x20, 0x77, 0x03, 0xe0, 0x40, 0x1c, /// 0x3870 + 0x20, 0x77, 0x00, 0x20, 0xd0, 0x74, 0x11, 0x20, + 0x4e, 0x4e, 0x40, 0x01, 0x30, 0x18, 0x27, 0x7f, /// 0x3880 + 0x09, 0x90, 0x00, 0x78, 0x0c, 0x90, 0x09, 0x98, + 0xff, 0x36, 0x40, 0x78, 0x06, 0x90, 0x46, 0x48, /// 0x3890 + 0xff, 0x36, 0x01, 0x46, 0xa0, 0x31, 0x80, 0x30, + 0x07, 0x91, 0xc1, 0x7b, 0x03, 0x91, 0x81, 0x7b, /// 0x38a0 + 0x04, 0x91, 0x41, 0x7b, 0x03, 0x7b, 0x05, 0x93, + 0x02, 0x36, 0x3b, 0x00, 0xfe, 0xf7, 0xb6, 0xf8, /// 0x38b0 + 0x11, 0x0a, 0x0d, 0x13, 0x15, 0x1f, 0x23, 0x38, + 0x40, 0x45, 0x4c, 0x62, 0x6a, 0x6f, 0x84, 0x89, /// 0x38c0 + 0x8e, 0xb3, 0xb5, 0x00, 0xff, 0xf7, 0xa6, 0xff, + 0xa7, 0xe0, 0xa8, 0x07, 0x00, 0xd5, 0xfe, 0xe7, /// 0x38d0 + 0x00, 0x20, 0xd0, 0x74, 0xa1, 0xe0, 0x30, 0x20, + 0x0a, 0xe0, 0x0c, 0x99, 0x30, 0x29, 0xf7, 0xd1, /// 0x38e0 + 0x07, 0x9b, 0x06, 0x99, 0x59, 0x72, 0x71, 0x8c, + 0x49, 0xba, 0x41, 0x84, 0xf0, 0xe7, 0x31, 0x20, /// 0x38f0 + 0xff, 0xf7, 0x37, 0xf8, 0x91, 0xe0, 0x0c, 0x9b, + 0x31, 0x2b, 0xe9, 0xd1, 0x06, 0x9d, 0x05, 0x71, /// 0x3900 + 0x09, 0x9b, 0x8d, 0x42, 0x9b, 0x78, 0x43, 0x71, + 0x09, 0x9e, 0xf6, 0x78, 0x86, 0x71, 0x02, 0xd2, /// 0x3910 + 0x8b, 0x42, 0x00, 0xd2, 0x43, 0x73, 0x04, 0x99, + 0x8b, 0x42, 0xd9, 0xd2, 0x83, 0x73, 0xd7, 0xe7, /// 0x3920 + 0x00, 0x7a, 0x05, 0x99, 0x81, 0x42, 0x01, 0xd0, + 0x02, 0x20, 0x35, 0xe0, 0x07, 0x20, 0x37, 0xe0, /// 0x3930 + 0xe8, 0x07, 0xcd, 0xd0, 0x05, 0x98, 0x10, 0x75, + 0xca, 0xe7, 0x40, 0x7a, 0x81, 0x42, 0x01, 0xd0, /// 0x3940 + 0x01, 0x20, 0x29, 0xe0, 0x09, 0x20, 0x2b, 0xe0, + 0x17, 0x4b, 0xed, 0x07, 0x80, 0x33, 0x1b, 0x79, /// 0x3950 + 0x00, 0x2d, 0x09, 0xd0, 0x51, 0x75, 0x8b, 0x42, + 0x00, 0xd2, 0x01, 0x71, 0x41, 0x8c, 0x27, 0x29, /// 0x3960 + 0xb6, 0xd1, 0x04, 0x21, 0x01, 0x71, 0xb3, 0xe7, + 0x99, 0x42, 0xb1, 0xd9, 0x43, 0x73, 0x08, 0x20, /// 0x3970 + 0x20, 0x77, 0xad, 0xe7, 0x80, 0x7a, 0x04, 0x99, + 0x81, 0x42, 0x01, 0xd0, 0x04, 0x20, 0x0b, 0xe0, /// 0x3980 + 0x0b, 0x20, 0x0d, 0xe0, 0xe8, 0x07, 0xa3, 0xd0, + 0x04, 0x98, 0x90, 0x75, 0xa0, 0xe7, 0xc0, 0x7a, /// 0x3990 + 0x03, 0x99, 0x81, 0x42, 0x03, 0xd0, 0x03, 0x20, + 0xfe, 0xf7, 0xd3, 0xff, 0x3d, 0xe0, 0x0d, 0x20, /// 0x39a0 + 0x20, 0x77, 0x3a, 0xe0, 0x70, 0x03, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x20, 0x70, 0x02, 0x00, 0x20, /// 0x39b0 + 0x0c, 0x22, 0x00, 0x00, 0x30, 0x01, 0x00, 0x20, + 0xe8, 0x07, 0x89, 0xd0, 0x03, 0x98, 0xd0, 0x75, /// 0x39c0 + 0x86, 0xe7, 0xfe, 0xf7, 0xac, 0xff, 0xc1, 0xb2, + 0x00, 0x20, 0xe5, 0xe7, 0xe9, 0x07, 0x1b, 0xd0, /// 0x39d0 + 0x71, 0x6f, 0x81, 0x60, 0xff, 0x20, 0xb7, 0x30, + 0xf0, 0x82, 0x6c, 0x48, 0x41, 0x68, 0x80, 0x30, /// 0x39e0 + 0x0a, 0x46, 0xcd, 0x3a, 0x82, 0x66, 0xc1, 0x66, + 0x02, 0x6f, 0x89, 0x1a, 0x41, 0x66, 0x67, 0x49, /// 0x39f0 + 0x07, 0x20, 0x40, 0x31, 0x88, 0x73, 0x07, 0x99, + 0x0f, 0x20, 0x08, 0x72, 0x64, 0x48, 0x01, 0x78, /// 0x3a00 + 0x04, 0x22, 0x11, 0x43, 0x01, 0x70, 0x08, 0xe0, + 0xa9, 0x07, 0x06, 0xd5, 0x80, 0x68, 0x70, 0x67, /// 0x3a10 + 0x00, 0x20, 0xd0, 0x74, 0x03, 0xe0, 0xfe, 0xf7, + 0xd6, 0xf8, 0x20, 0x7f, 0x40, 0x1c, 0x20, 0x77, /// 0x3a20 + 0x0d, 0xb0, 0xf0, 0xbd, 0xf8, 0xb5, 0x5b, 0x4c, + 0xa0, 0x78, 0x84, 0x46, 0x80, 0x07, 0x58, 0xd5, /// 0x3a30 + 0x20, 0x46, 0x59, 0x4e, 0x40, 0x38, 0x01, 0x88, + 0xf2, 0x89, 0x89, 0x1a, 0x00, 0x29, 0x00, 0xdc, /// 0x3a40 + 0x49, 0x42, 0x54, 0x4a, 0x40, 0x32, 0x15, 0x46, + 0xd3, 0x89, 0xc0, 0x3d, 0xef, 0x6a, 0x99, 0x42, /// 0x3a50 + 0x25, 0xdd, 0x61, 0x46, 0xfd, 0x22, 0x11, 0x40, + 0xa1, 0x70, 0x01, 0x8f, 0xaf, 0x20, 0x00, 0x01, /// 0x3a60 + 0x08, 0x1a, 0x0a, 0x21, 0x48, 0x43, 0x54, 0x21, + 0xfd, 0xf7, 0xc4, 0xff, 0x29, 0x46, 0xe8, 0x87, /// 0x3a70 + 0x60, 0x31, 0xc8, 0x70, 0x01, 0x21, 0x08, 0x43, + 0x48, 0x49, 0x08, 0x82, 0x08, 0x20, 0x07, 0x43, /// 0x3a80 + 0xef, 0x62, 0xfd, 0xf7, 0x69, 0xf8, 0xe9, 0x8f, + 0x45, 0x48, 0x81, 0x42, 0x20, 0x78, 0x02, 0xd1, /// 0x3a90 + 0x80, 0x21, 0x08, 0x43, 0x01, 0xe0, 0x40, 0x06, + 0x40, 0x0e, 0x20, 0x70, 0x21, 0xe0, 0x3b, 0x49, /// 0x3aa0 + 0x4b, 0x68, 0x31, 0x69, 0x9c, 0x46, 0x59, 0x1a, + 0x3d, 0x4b, 0x30, 0x33, 0x99, 0x42, 0x18, 0xdd, /// 0x3ab0 + 0x71, 0x7b, 0x52, 0x7f, 0x91, 0x42, 0x08, 0xd2, + 0xc2, 0x89, 0x80, 0x23, 0x1a, 0x43, 0xc2, 0x81, /// 0x3ac0 + 0x60, 0x46, 0x49, 0x1c, 0x30, 0x61, 0x71, 0x73, + 0x0b, 0xe0, 0x01, 0x20, 0xc0, 0x03, 0x07, 0x43, /// 0x3ad0 + 0xef, 0x62, 0xfd, 0xf7, 0x41, 0xf8, 0xa0, 0x78, + 0xfd, 0x21, 0x08, 0x40, 0xa0, 0x70, 0x00, 0x20, /// 0x3ae0 + 0x70, 0x73, 0x00, 0x20, 0xf8, 0xbd, 0x70, 0xb5, + 0x2a, 0x49, 0x9f, 0x23, 0x4a, 0x78, 0x1a, 0x40, /// 0x3af0 + 0x4a, 0x70, 0x0b, 0x46, 0x20, 0x33, 0x1c, 0x7c, + 0x05, 0x78, 0x80, 0x39, 0xca, 0x6a, 0xac, 0x42, /// 0x3b00 + 0x0e, 0xd1, 0x5c, 0x7c, 0x45, 0x78, 0xac, 0x42, + 0x0a, 0xd1, 0x9c, 0x7c, 0x85, 0x78, 0xac, 0x42, /// 0x3b10 + 0x06, 0xd1, 0xdb, 0x7c, 0xc0, 0x78, 0x83, 0x42, + 0x02, 0xd1, 0x01, 0x20, 0x40, 0x02, 0x01, 0xe0, /// 0x3b20 + 0xff, 0x20, 0x01, 0x30, 0x02, 0x43, 0xca, 0x62, + 0xfd, 0xf7, 0x16, 0xf8, 0x70, 0xbd, 0x70, 0xb5, /// 0x3b30 + 0x18, 0x4c, 0xdf, 0x21, 0x60, 0x78, 0x23, 0x46, + 0x08, 0x40, 0x60, 0x70, 0x40, 0x3b, 0x58, 0x7e, /// 0x3b40 + 0x3b, 0x28, 0x16, 0xd1, 0x1d, 0x46, 0x80, 0x35, + 0x28, 0x79, 0xfd, 0x21, 0x08, 0x40, 0x01, 0x21, /// 0x3b50 + 0x08, 0x43, 0x28, 0x71, 0x19, 0x46, 0x9e, 0x7e, + 0x40, 0x39, 0xca, 0x6a, 0x02, 0x2e, 0x02, 0xd1, /// 0x3b60 + 0xdb, 0x7e, 0xbb, 0x2b, 0x06, 0xd0, 0x01, 0x20, + 0x00, 0x03, 0x02, 0x43, 0xca, 0x62, 0xfc, 0xf7, /// 0x3b70 + 0xf3, 0xff, 0x70, 0xbd, 0x08, 0x23, 0x18, 0x43, + 0x28, 0x71, 0x98, 0x02, 0x02, 0x43, 0xca, 0x62, /// 0x3b80 + 0xfc, 0xf7, 0xea, 0xff, 0x09, 0x20, 0xe0, 0x82, + 0x70, 0xbd, 0x00, 0x00, 0x30, 0x02, 0x00, 0x20, /// 0x3b90 + 0x40, 0x6c, 0x00, 0x40, 0x80, 0x00, 0x00, 0x20, + 0xb0, 0x03, 0x00, 0x20, 0x00, 0x30, 0x00, 0x40, /// 0x3ba0 + 0xac, 0x05, 0x00, 0x00, 0x9a, 0x34, 0x9a, 0x34, + 0x8c, 0x26, 0x8c, 0x26, 0x9b, 0xef, 0x9b, 0xef, /// 0x3bb0 + 0x14, 0x14, 0x00, 0x00, 0x8b, 0x74, 0x8b, 0x74, + 0x8c, 0x4c, 0x8c, 0x4c, 0x8c, 0x48, 0x8c, 0x48, /// 0x3bc0 + 0x14, 0x00, 0x80, 0x45, 0x01, 0x00, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /// 0x3bd0 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xf0, 0xb5, 0x72, 0xb6, /// 0x3be0 + 0x72, 0x48, 0x89, 0xb0, 0x70, 0x49, 0x81, 0x60, + 0x71, 0x49, 0xc1, 0x67, 0x71, 0x49, 0x80, 0x30, /// 0x3bf0 + 0x01, 0x60, 0x71, 0x49, 0x74, 0x4f, 0x41, 0x60, + 0x71, 0x49, 0x70, 0x48, 0x3d, 0x46, 0x88, 0x61, /// 0x3c00 + 0x80, 0x35, 0x70, 0x4e, 0x71, 0x48, 0xfe, 0x61, + 0x28, 0x82, 0x04, 0x20, 0x2c, 0x46, 0x38, 0x84, /// 0x3c10 + 0x40, 0x3c, 0x60, 0x73, 0x62, 0xb6, 0x65, 0x48, + 0xb9, 0x78, 0x20, 0x38, 0x05, 0x29, 0x01, 0xd3, /// 0x3c20 + 0x02, 0x21, 0x00, 0xe0, 0x06, 0x21, 0x01, 0x76, + 0x01, 0xf0, 0xa7, 0xfa, 0x01, 0xf0, 0x98, 0xfa, /// 0x3c30 + 0x67, 0x48, 0xc3, 0x21, 0x00, 0x60, 0x40, 0x60, + 0x63, 0x48, 0x29, 0x22, 0x41, 0x63, 0x62, 0x49, /// 0x3c40 + 0x00, 0x20, 0xc8, 0x62, 0x63, 0x49, 0xff, 0x27, + 0x4e, 0x60, 0x5f, 0x49, 0xf5, 0x37, 0xce, 0x61, /// 0x3c50 + 0xff, 0x21, 0x9d, 0x31, 0xa1, 0x84, 0xe1, 0x84, + 0x21, 0x85, 0x5b, 0x49, 0xaf, 0x23, 0x60, 0x31, /// 0x3c60 + 0x07, 0x91, 0x4a, 0x76, 0x67, 0x85, 0x5c, 0x49, + 0xa1, 0x85, 0xf9, 0x00, 0x21, 0x84, 0x07, 0x99, /// 0x3c70 + 0x02, 0x22, 0x0a, 0x76, 0xa0, 0x87, 0xb9, 0x00, + 0xe1, 0x87, 0x55, 0x49, 0x08, 0x22, 0x78, 0x39, /// 0x3c80 + 0x0a, 0x71, 0xff, 0x22, 0x4a, 0x71, 0x49, 0x49, + 0xe0, 0x86, 0x9b, 0x00, 0xc0, 0x39, 0xff, 0x26, /// 0x3c90 + 0x4b, 0x80, 0x91, 0x36, 0x6e, 0x82, 0xae, 0x82, + 0x18, 0x26, 0xae, 0x76, 0xee, 0x76, 0x19, 0x26, /// 0x3ca0 + 0x76, 0x01, 0xee, 0x82, 0x05, 0x26, 0xae, 0x77, + 0x47, 0x4e, 0x73, 0x81, 0x33, 0x46, 0x9f, 0x81, /// 0x3cb0 + 0x37, 0x46, 0x11, 0x23, 0xe0, 0x37, 0xbb, 0x77, + 0x4c, 0x23, 0xfb, 0x77, 0x01, 0x26, 0xfe, 0x71, /// 0x3cc0 + 0x3e, 0x46, 0xc0, 0x3e, 0xb2, 0x76, 0x0a, 0x46, + 0x0a, 0x26, 0x40, 0x3a, 0x96, 0x70, 0x3e, 0x46, /// 0x3cd0 + 0x52, 0x8e, 0x20, 0x3e, 0x32, 0x82, 0x0a, 0x46, + 0x40, 0x3a, 0x92, 0x8e, 0x72, 0x82, 0x0a, 0x46, /// 0x3ce0 + 0x20, 0x3a, 0xd3, 0x77, 0x08, 0x71, 0x01, 0x23, + 0x4b, 0x71, 0xcb, 0x80, 0x09, 0x21, 0x91, 0x75, /// 0x3cf0 + 0x02, 0x21, 0x20, 0x3a, 0x11, 0x87, 0x39, 0x49, + 0x8f, 0x22, 0x4a, 0x87, 0x7b, 0x72, 0xe0, 0x85, /// 0x3d00 + 0x37, 0x49, 0x2a, 0x48, 0x0a, 0x8a, 0x37, 0x4b, + 0x40, 0x38, 0x06, 0x90, 0x9a, 0x42, 0x23, 0xd0, /// 0x3d10 + 0x08, 0x46, 0x0e, 0x21, 0x41, 0x5e, 0x08, 0x03, + 0x33, 0x49, 0xfd, 0xf7, 0x6b, 0xfe, 0x06, 0x99, /// 0x3d20 + 0x80, 0xb2, 0x48, 0x83, 0x00, 0x90, 0x2e, 0x48, + 0x10, 0x21, 0x41, 0x5e, 0x08, 0x03, 0x2e, 0x49, /// 0x3d30 + 0xfd, 0xf7, 0x60, 0xfe, 0x81, 0xb2, 0x06, 0x98, + 0x81, 0x83, 0x00, 0x98, 0x09, 0x1a, 0x7d, 0x20, /// 0x3d40 + 0x40, 0x03, 0xfd, 0xf7, 0x57, 0xfe, 0x01, 0xb2, + 0x71, 0x87, 0x00, 0x98, 0x41, 0x43, 0xc8, 0x12, /// 0x3d50 + 0xff, 0x21, 0x2d, 0x31, 0x08, 0x1a, 0x04, 0xe0, + 0x01, 0x20, 0xc0, 0x02, 0x70, 0x87, 0xe1, 0x20, /// 0x3d60 + 0x80, 0x00, 0x1b, 0x49, 0xb0, 0x87, 0x78, 0x39, + 0x08, 0x7b, 0xf7, 0x22, 0x40, 0x08, 0x40, 0x00, /// 0x3d70 + 0x10, 0x40, 0x08, 0x73, 0x00, 0x20, 0x08, 0x72, + 0x48, 0x73, 0x88, 0x73, 0x01, 0x22, 0xca, 0x76, /// 0x3d80 + 0x20, 0x73, 0xe0, 0x81, 0x28, 0x70, 0x07, 0x99, + 0xef, 0x22, 0xc9, 0x7e, 0x0e, 0x4c, 0x11, 0x40, /// 0x3d90 + 0x07, 0x9a, 0xd1, 0x76, 0x06, 0x99, 0x08, 0x83, + 0xf8, 0x74, 0x80, 0x20, 0xfc, 0xf7, 0xdc, 0xfe, /// 0x3da0 + 0x20, 0x6b, 0xe0, 0x62, 0x09, 0xb0, 0xf0, 0xbd, + 0x05, 0x53, 0x00, 0x00, 0x30, 0x02, 0x00, 0x20, /// 0x3db0 + 0x55, 0x4f, 0x00, 0x00, 0x25, 0x52, 0x00, 0x00, + 0x21, 0x40, 0x00, 0x00, 0xd5, 0x54, 0x00, 0x00, /// 0x3dc0 + 0x00, 0x01, 0x00, 0x20, 0x0c, 0x00, 0x08, 0x02, + 0x00, 0x00, 0x00, 0x20, 0xdc, 0x05, 0x00, 0x00, /// 0x3dd0 + 0xe8, 0x04, 0x00, 0x20, 0x40, 0x04, 0x00, 0x20, + 0xf8, 0x2a, 0x00, 0x00, 0x30, 0x01, 0x00, 0x20, /// 0x3de0 + 0x60, 0x67, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, + 0x34, 0x08, 0x00, 0x00, 0x70, 0xb5, 0x03, 0x46, /// 0x3df0 + 0xfe, 0x4a, 0x00, 0x20, 0x14, 0x24, 0x44, 0x43, + 0xa4, 0x18, 0x50, 0x34, 0x25, 0x78, 0x00, 0x2d, /// 0x3e00 + 0x03, 0xd0, 0x40, 0x1c, 0x02, 0x28, 0xf5, 0xdb, + 0x70, 0xbd, 0x0a, 0x46, 0x19, 0x46, 0x20, 0x46, /// 0x3e10 + 0xfc, 0xf7, 0x77, 0xfe, 0xf5, 0x48, 0x0c, 0x34, + 0xc1, 0x6f, 0xc4, 0x67, 0x78, 0x30, 0x03, 0xc4, /// 0x3e20 + 0x08, 0x3c, 0x0c, 0x60, 0x70, 0xbd, 0xf8, 0xb5, + 0x15, 0x46, 0x2c, 0x22, 0x50, 0x43, 0xf0, 0x4a, /// 0x3e30 + 0x87, 0x18, 0x14, 0x20, 0x41, 0x43, 0x7c, 0x18, + 0x20, 0x7a, 0x0a, 0x28, 0x6e, 0xd2, 0x20, 0x7a, /// 0x3e40 + 0x00, 0x28, 0x09, 0xd1, 0x28, 0x46, 0xfe, 0xf7, + 0x51, 0xfa, 0x80, 0x1c, 0xc0, 0xb2, 0x00, 0x2d, /// 0x3e50 + 0x64, 0xd0, 0x0c, 0x28, 0x62, 0xd8, 0xa0, 0x72, + 0x20, 0x7a, 0x21, 0x18, 0x40, 0x1c, 0x20, 0x72, /// 0x3e60 + 0x8d, 0x73, 0x60, 0x7a, 0x68, 0x40, 0x60, 0x72, + 0x20, 0x7a, 0xa1, 0x7a, 0xe1, 0x4e, 0x88, 0x42, /// 0x3e70 + 0x52, 0xd1, 0x60, 0x7a, 0x00, 0x28, 0x0f, 0xd0, + 0xdc, 0x4d, 0x2a, 0x7a, 0x0c, 0x2a, 0x4b, 0xd2, /// 0x3e80 + 0xdd, 0x48, 0xa3, 0x7b, 0x01, 0x46, 0x40, 0x31, + 0x01, 0x2b, 0x11, 0xd0, 0x08, 0x27, 0x71, 0x2b, /// 0x3e90 + 0x1e, 0xd0, 0x51, 0x2b, 0x2c, 0xd0, 0x3f, 0xe0, + 0xa1, 0x7a, 0x20, 0x46, 0x0e, 0x30, 0xff, 0xf7, /// 0x3ea0 + 0xa5, 0xff, 0x00, 0x20, 0x20, 0x72, 0xb8, 0x78, + 0xfb, 0x21, 0x08, 0x40, 0xb8, 0x70, 0x33, 0xe0, /// 0x3eb0 + 0x01, 0x2a, 0x31, 0xd1, 0x0a, 0x74, 0xc1, 0x6a, + 0x4a, 0x07, 0x05, 0xd4, 0x04, 0x22, 0x11, 0x43, /// 0x3ec0 + 0xc1, 0x62, 0x10, 0x46, 0xfc, 0xf7, 0x48, 0xfe, + 0x70, 0x68, 0x28, 0x60, 0x02, 0x20, 0x22, 0xe0, /// 0x3ed0 + 0x02, 0x2a, 0x21, 0xd1, 0x71, 0x22, 0x0a, 0x74, + 0xc1, 0x6a, 0x0a, 0x07, 0x04, 0xd4, 0x39, 0x43, /// 0x3ee0 + 0xc1, 0x62, 0x08, 0x20, 0xfc, 0xf7, 0x38, 0xfe, + 0x70, 0x68, 0x28, 0x60, 0x03, 0x20, 0x12, 0xe0, /// 0x3ef0 + 0x03, 0x2a, 0x11, 0xd1, 0x51, 0x22, 0x0a, 0x74, + 0xc1, 0x6a, 0xca, 0x06, 0x05, 0xd4, 0x10, 0x22, /// 0x3f00 + 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, 0xfc, 0xf7, + 0x27, 0xfe, 0xbb, 0x48, 0x60, 0x30, 0x07, 0x76, /// 0x3f10 + 0x70, 0x68, 0x28, 0x60, 0x0c, 0x20, 0x28, 0x72, + 0x70, 0x68, 0x60, 0x60, 0xf8, 0xbd, 0xf1, 0xb5, /// 0x3f20 + 0xb6, 0x4d, 0x82, 0xb0, 0x28, 0x7b, 0x02, 0x99, + 0x86, 0x07, 0x2c, 0x22, 0xb6, 0x0f, 0xb0, 0x48, /// 0x3f30 + 0x51, 0x43, 0x01, 0x2e, 0x46, 0xd0, 0x00, 0x22, + 0x42, 0x52, 0x43, 0x5a, 0x02, 0x9a, 0x2c, 0x24, /// 0x3f40 + 0x62, 0x43, 0xab, 0x4c, 0x14, 0x19, 0x09, 0x2b, + 0x02, 0xd3, 0xa2, 0x78, 0x52, 0x07, 0x05, 0xd5, /// 0x3f50 + 0x40, 0x5a, 0x0b, 0x28, 0x0a, 0xd3, 0xa0, 0x78, + 0x40, 0x07, 0x07, 0xd5, 0xa0, 0x78, 0xfb, 0x21, /// 0x3f60 + 0x08, 0x40, 0xa0, 0x70, 0xa0, 0x78, 0x01, 0x21, + 0x08, 0x43, 0xa0, 0x70, 0xa0, 0x78, 0xc0, 0x07, /// 0x3f70 + 0x34, 0xd0, 0x01, 0x2e, 0x32, 0xd9, 0xa0, 0x78, + 0x40, 0x08, 0x40, 0x00, 0xa0, 0x70, 0xa0, 0x78, /// 0x3f80 + 0x04, 0x21, 0x08, 0x43, 0xa0, 0x70, 0xa0, 0x78, + 0x02, 0x2e, 0x1e, 0xd0, 0xfd, 0x21, 0x08, 0x40, /// 0x3f90 + 0xa0, 0x70, 0x20, 0x1d, 0x28, 0x21, 0xfc, 0xf7, + 0xc4, 0xfd, 0x20, 0x46, 0x18, 0x30, 0x28, 0x21, /// 0x3fa0 + 0xfc, 0xf7, 0xbf, 0xfd, 0x03, 0x2e, 0x13, 0xd0, + 0x01, 0x20, 0x40, 0x02, 0xa0, 0x81, 0x11, 0x20, /// 0x3fb0 + 0x40, 0x02, 0x20, 0x84, 0x8d, 0x48, 0x01, 0x7a, + 0x0c, 0x29, 0x02, 0xd1, 0x8d, 0x49, 0x49, 0x68, /// 0x3fc0 + 0x01, 0x60, 0xfe, 0xbd, 0x42, 0x5a, 0x52, 0x1c, + 0xb6, 0xe7, 0x02, 0x21, 0x08, 0x43, 0xdf, 0xe7, /// 0x3fd0 + 0x03, 0x20, 0x00, 0x02, 0xa0, 0x81, 0x23, 0x20, + 0x00, 0x02, 0xea, 0xe7, 0xa0, 0x78, 0x40, 0x07, /// 0x3fe0 + 0xef, 0xd5, 0xa0, 0x78, 0x80, 0x07, 0x01, 0xd5, + 0x02, 0x20, 0x00, 0xe0, 0x01, 0x20, 0x00, 0x26, /// 0x3ff0 + 0x00, 0x90, 0x14, 0x20, 0x70, 0x43, 0x27, 0x18, + 0xb8, 0x89, 0xa8, 0x83, 0xa9, 0x8b, 0x09, 0x20, /// 0x4000 + 0x00, 0x03, 0x88, 0x43, 0x05, 0xd1, 0xa8, 0x8b, + 0xf1, 0xb2, 0xc2, 0xb2, 0x02, 0x98, 0xff, 0xf7, /// 0x4010 + 0x0a, 0xff, 0xa8, 0x8b, 0xb8, 0x81, 0x00, 0x98, + 0x76, 0x1c, 0x86, 0x42, 0xe9, 0xdb, 0xfe, 0xbd, /// 0x4020 + 0xf8, 0xb5, 0x76, 0x48, 0x40, 0x38, 0x06, 0x7f, + 0xff, 0x21, 0x01, 0x76, 0x00, 0x24, 0x01, 0x27, /// 0x4030 + 0x3d, 0x46, 0xa5, 0x40, 0x35, 0x42, 0x02, 0xd0, + 0xe0, 0xb2, 0xff, 0xf7, 0x70, 0xff, 0x64, 0x1c, /// 0x4040 + 0x02, 0x2c, 0xf5, 0xdb, 0x00, 0x20, 0xf8, 0xbd, + 0x01, 0x21, 0x6c, 0x48, 0xc9, 0x03, 0x40, 0x38, /// 0x4050 + 0x01, 0x80, 0x6a, 0x49, 0x0c, 0x22, 0x20, 0x31, + 0x8a, 0x82, 0x69, 0x4b, 0xa5, 0x22, 0x1a, 0x80, /// 0x4060 + 0x00, 0x22, 0x9a, 0x82, 0x01, 0x23, 0x0b, 0x74, + 0x10, 0x21, 0x01, 0x80, 0x08, 0x21, 0x01, 0x71, /// 0x4070 + 0x8d, 0x21, 0x01, 0x72, 0x60, 0x21, 0x01, 0x73, + 0x60, 0x49, 0x20, 0x39, 0x0a, 0x71, 0x61, 0x4a, /// 0x4080 + 0x8a, 0x83, 0x61, 0x4a, 0x0a, 0x82, 0x61, 0x4a, + 0x8a, 0x82, 0x61, 0x4a, 0x0a, 0x83, 0x61, 0x4a, /// 0x4090 + 0x0a, 0x81, 0x8a, 0x81, 0x60, 0x4a, 0x41, 0x15, + 0x11, 0x60, 0x60, 0x4a, 0x11, 0x60, 0x03, 0x21, /// 0x40a0 + 0x01, 0x82, 0xff, 0x21, 0x01, 0x76, 0x70, 0x47, + 0xff, 0x21, 0x10, 0xb5, 0x90, 0x31, 0x88, 0x42, /// 0x40b0 + 0x06, 0xd9, 0x64, 0x21, 0xfd, 0xf7, 0x88, 0xfc, + 0x0a, 0x21, 0x48, 0x43, 0x80, 0x1c, 0x00, 0xe0, /// 0x40c0 + 0x20, 0x20, 0xc1, 0xb2, 0x08, 0x02, 0x08, 0x43, + 0x4c, 0x49, 0x20, 0x39, 0x08, 0x81, 0x88, 0x81, /// 0x40d0 + 0x10, 0xbd, 0x49, 0x49, 0x10, 0xb5, 0x00, 0x22, + 0x80, 0x31, 0x4a, 0x76, 0x43, 0x49, 0x88, 0x71, /// 0x40e0 + 0x8a, 0x76, 0x02, 0x20, 0x08, 0x72, 0x43, 0x48, + 0x04, 0x22, 0x40, 0x68, 0x08, 0x60, 0x42, 0x48, /// 0x40f0 + 0xc1, 0x6a, 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, + 0xfc, 0xf7, 0x2e, 0xfd, 0x10, 0xbd, 0x01, 0x46, /// 0x4100 + 0x3a, 0x48, 0x10, 0xb5, 0x07, 0x22, 0x1c, 0x30, + 0xfc, 0xf7, 0xfb, 0xfc, 0x44, 0x49, 0xfb, 0x20, /// 0x4110 + 0x08, 0x80, 0x36, 0x48, 0x0c, 0x21, 0x01, 0x72, + 0x36, 0x49, 0x10, 0x22, 0x49, 0x68, 0x01, 0x60, /// 0x4120 + 0x35, 0x48, 0x08, 0x21, 0x60, 0x30, 0x01, 0x76, + 0x60, 0x38, 0xc1, 0x6a, 0x11, 0x43, 0xc1, 0x62, /// 0x4130 + 0x10, 0x46, 0xfc, 0xf7, 0x11, 0xfd, 0x10, 0xbd, + 0x01, 0x46, 0x2c, 0x48, 0x10, 0xb5, 0x07, 0x22, /// 0x4140 + 0x21, 0x30, 0xfc, 0xf7, 0xde, 0xfc, 0x29, 0x48, + 0x03, 0x21, 0x01, 0x72, 0x29, 0x49, 0x08, 0x22, /// 0x4150 + 0x49, 0x68, 0x01, 0x60, 0x28, 0x48, 0xc1, 0x6a, + 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, 0xfc, 0xf7, /// 0x4160 + 0xfb, 0xfc, 0x10, 0xbd, 0x21, 0x48, 0x03, 0x21, + 0x01, 0x72, 0x22, 0x49, 0x49, 0x68, 0x01, 0x60, /// 0x4170 + 0x70, 0x47, 0x10, 0xb5, 0x08, 0x28, 0x17, 0xd8, + 0x1f, 0x48, 0x80, 0x30, 0x41, 0x7e, 0x49, 0x1c, /// 0x4180 + 0xc9, 0xb2, 0x41, 0x76, 0x80, 0x38, 0x02, 0x8c, + 0x91, 0x42, 0x0d, 0xd3, 0x01, 0x46, 0x40, 0x31, /// 0x4190 + 0x8b, 0x8e, 0x01, 0x22, 0x13, 0x43, 0x8b, 0x86, + 0xc1, 0x6a, 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, /// 0x41a0 + 0xfc, 0xf7, 0xda, 0xfc, 0x00, 0xf0, 0x54, 0xfb, + 0x10, 0xbd, 0xf8, 0xb5, 0x07, 0x46, 0xc5, 0x09, /// 0x41b0 + 0x01, 0xd0, 0xf8, 0x43, 0x40, 0x1c, 0xc4, 0xb2, + 0x19, 0x48, 0x01, 0x88, 0x09, 0x06, 0xc9, 0x0e, /// 0x41c0 + 0x1f, 0x29, 0x01, 0xd0, 0xfb, 0x21, 0x01, 0x80, + 0x0b, 0x4e, 0xff, 0x20, 0x40, 0x36, 0x71, 0x8c, /// 0x41d0 + 0x9d, 0x30, 0x81, 0x42, 0x03, 0xd0, 0x05, 0x49, + 0x49, 0x79, 0x00, 0xf0, 0x98, 0xfb, 0x05, 0x48, /// 0x41e0 + 0x05, 0x49, 0xe0, 0x38, 0xc7, 0x75, 0x80, 0x31, + 0x48, 0x7e, 0x1b, 0xe0, 0x70, 0x04, 0x00, 0x20, /// 0x41f0 + 0xe0, 0x03, 0x00, 0x20, 0x30, 0x02, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x20, 0x40, 0x40, 0x00, 0x40, /// 0x4200 + 0x00, 0x74, 0x00, 0x40, 0x2c, 0x10, 0x00, 0x00, + 0x1d, 0x26, 0x00, 0x00, 0x15, 0x1d, 0x00, 0x00, /// 0x4210 + 0x0e, 0x15, 0x00, 0x00, 0x2a, 0x2a, 0x00, 0x00, + 0x80, 0xe2, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe0, /// 0x4220 + 0x00, 0x34, 0x00, 0x40, 0x00, 0x22, 0x00, 0x28, + 0x19, 0xd0, 0x08, 0x7e, 0x40, 0x1c, 0xc0, 0xb2, /// 0x4230 + 0x08, 0x76, 0x14, 0x28, 0x00, 0xd9, 0x4a, 0x76, + 0xfe, 0x48, 0xf7, 0x27, 0xc2, 0x80, 0xfe, 0x48, /// 0x4240 + 0x03, 0x7b, 0x3b, 0x40, 0x03, 0x73, 0xfd, 0x4b, + 0x00, 0x2c, 0x5b, 0x68, 0x03, 0x60, 0x08, 0xd0, /// 0x4250 + 0x04, 0x2c, 0x0a, 0xd2, 0x00, 0x2d, 0x06, 0xd0, + 0x00, 0x23, 0xdb, 0x43, 0x0f, 0xe0, 0x0a, 0x76, /// 0x4260 + 0xea, 0xe7, 0x42, 0x72, 0x2a, 0xe0, 0x01, 0x23, + 0x09, 0xe0, 0x73, 0x8c, 0xb7, 0x8c, 0xbb, 0x42, /// 0x4270 + 0x07, 0xd1, 0x00, 0x2d, 0x02, 0xd0, 0xa3, 0x08, + 0x5b, 0x42, 0x00, 0xe0, 0x63, 0x08, 0x43, 0x72, /// 0x4280 + 0x1c, 0xe0, 0xf6, 0x8c, 0xf3, 0x1a, 0x1b, 0x12, + 0x5b, 0x1c, 0x9b, 0xb2, 0x10, 0x2c, 0x00, 0xd9, /// 0x4290 + 0x10, 0x24, 0x00, 0x2d, 0x02, 0xd0, 0x66, 0x08, + 0x34, 0x19, 0xe4, 0xb2, 0x46, 0x79, 0xff, 0x2e, /// 0x42a0 + 0x05, 0xd0, 0xe4, 0x4e, 0x40, 0x36, 0x36, 0x79, + 0xf4, 0x40, 0x64, 0x1c, 0xe4, 0xb2, 0x00, 0x2d, /// 0x42b0 + 0x02, 0xd0, 0x5c, 0x43, 0x64, 0x42, 0x00, 0xe0, + 0x5c, 0x43, 0x44, 0x72, 0x09, 0x24, 0x04, 0x57, /// 0x42c0 + 0xdf, 0x4b, 0x00, 0x2c, 0x02, 0xdd, 0xdc, 0x7e, + 0x64, 0x07, 0x02, 0xd4, 0xdb, 0x7e, 0xdb, 0x06, /// 0x42d0 + 0x00, 0xd4, 0x42, 0x72, 0x48, 0x7f, 0x10, 0x28, + 0x00, 0xd2, 0x40, 0x1c, 0x48, 0x77, 0xf8, 0xbd, /// 0x42e0 + 0xf0, 0xb5, 0xd7, 0x4d, 0xd4, 0x4e, 0x20, 0x3d, + 0x2c, 0x46, 0x40, 0x34, 0x28, 0x8e, 0x31, 0x8a, /// 0x42f0 + 0x85, 0xb0, 0x62, 0x8a, 0x01, 0x92, 0xa2, 0x7e, + 0x03, 0x92, 0xe2, 0x8a, 0x00, 0x92, 0xa2, 0x7f, /// 0x4300 + 0x02, 0x92, 0x48, 0x43, 0x05, 0xd0, 0x7d, 0x21, + 0xc9, 0x00, 0xfd, 0xf7, 0x73, 0xfb, 0x07, 0x46, /// 0x4310 + 0x00, 0xe0, 0x00, 0x27, 0x31, 0x7f, 0xf0, 0x79, + 0x89, 0x06, 0x89, 0x0e, 0x7d, 0x22, 0x51, 0x43, /// 0x4320 + 0x48, 0x43, 0x46, 0x09, 0x00, 0x98, 0x87, 0x42, + 0x06, 0xd9, 0x03, 0x99, 0x38, 0x1a, 0x48, 0x43, /// 0x4330 + 0x64, 0x21, 0xfd, 0xf7, 0x49, 0xfb, 0x00, 0xe0, + 0x00, 0x20, 0xc1, 0x49, 0x38, 0x1a, 0x82, 0x1b, /// 0x4340 + 0x60, 0x39, 0x08, 0x46, 0xe0, 0x30, 0x0a, 0x61, + 0x80, 0x7f, 0x64, 0x23, 0x58, 0x43, 0xb0, 0x42, /// 0x4350 + 0x07, 0xd8, 0x01, 0x98, 0x82, 0x42, 0x06, 0xdc, + 0xba, 0x48, 0x86, 0x42, 0x03, 0xd2, 0x00, 0x20, /// 0x4360 + 0xe0, 0x77, 0x05, 0xb0, 0xf0, 0xbd, 0xe0, 0x7f, + 0x40, 0x1c, 0xc0, 0xb2, 0xe0, 0x77, 0x01, 0x9b, /// 0x4370 + 0x9b, 0x00, 0x93, 0x42, 0x01, 0xda, 0x40, 0x1c, + 0xe0, 0x77, 0xc2, 0xb2, 0x02, 0x98, 0x82, 0x42, /// 0x4380 + 0xef, 0xd3, 0x00, 0x20, 0xe0, 0x77, 0xa8, 0x8e, + 0x01, 0x22, 0x52, 0x03, 0x10, 0x43, 0xa8, 0x86, /// 0x4390 + 0xc8, 0x6a, 0x01, 0x22, 0x10, 0x43, 0xc8, 0x62, + 0x10, 0x46, 0xfc, 0xf7, 0xdd, 0xfb, 0x00, 0xf0, /// 0x43a0 + 0x57, 0xfa, 0xde, 0xe7, 0x70, 0xb5, 0xa4, 0x4d, + 0xa5, 0x4c, 0xe8, 0x71, 0x20, 0x34, 0x21, 0x7f, /// 0x43b0 + 0x08, 0x30, 0x81, 0x42, 0x01, 0xd9, 0x00, 0x20, + 0x60, 0x77, 0xa1, 0x48, 0x20, 0x38, 0xc0, 0x8e, /// 0x43c0 + 0x80, 0x06, 0x09, 0xd5, 0x60, 0x7f, 0x06, 0x28, + 0x06, 0xd9, 0x9b, 0x48, 0x20, 0x30, 0x40, 0x78, /// 0x43d0 + 0x00, 0x07, 0x01, 0xd0, 0xff, 0xf7, 0x84, 0xff, + 0xe8, 0x79, 0x20, 0x77, 0x70, 0xbd, 0x98, 0x49, /// 0x43e0 + 0x40, 0x39, 0x88, 0x76, 0x64, 0x28, 0x01, 0xd9, + 0x64, 0x20, 0x88, 0x76, 0x70, 0x47, 0x41, 0x1f, /// 0x43f0 + 0xc8, 0x29, 0x01, 0xd8, 0x90, 0x49, 0xc8, 0x72, + 0x70, 0x47, 0x10, 0xb5, 0x42, 0x78, 0x1e, 0x23, /// 0x4400 + 0x4a, 0x70, 0x36, 0x2a, 0x09, 0xd0, 0x37, 0x2a, + 0x06, 0xd1, 0x0b, 0x70, 0x81, 0x1c, 0x8c, 0x48, /// 0x4410 + 0x04, 0x22, 0x48, 0x38, 0xfc, 0xf7, 0x75, 0xfb, + 0x10, 0xbd, 0x0b, 0x70, 0x81, 0x1c, 0x88, 0x48, /// 0x4420 + 0x04, 0x22, 0x4c, 0x38, 0xf6, 0xe7, 0x70, 0xb5, + 0x42, 0x78, 0x1e, 0x25, 0x0c, 0x46, 0x4a, 0x70, /// 0x4430 + 0xc1, 0x2a, 0x16, 0xd0, 0xc3, 0x2a, 0x18, 0xd0, + 0x81, 0x49, 0x60, 0x31, 0xb6, 0x2a, 0x1c, 0xd0, /// 0x4440 + 0xb7, 0x2a, 0x19, 0xd1, 0x82, 0x78, 0x4a, 0x70, + 0xc2, 0x78, 0x8a, 0x70, 0x00, 0x79, 0xc8, 0x70, /// 0x4450 + 0xc0, 0x39, 0xff, 0x20, 0xca, 0x6a, 0x01, 0x30, + 0x02, 0x43, 0xca, 0x62, 0xfc, 0xf7, 0x7c, 0xfb, /// 0x4460 + 0x09, 0xe0, 0x01, 0x22, 0x41, 0x88, 0x92, 0x07, + 0x02, 0xe0, 0x41, 0x88, 0x01, 0x22, 0x52, 0x07, /// 0x4470 + 0x89, 0x18, 0x00, 0x79, 0x08, 0x70, 0x25, 0x70, + 0x70, 0xbd, 0x71, 0x4a, 0x83, 0x78, 0x40, 0x32, /// 0x4480 + 0x93, 0x77, 0xc3, 0x78, 0xd3, 0x77, 0xf4, 0xe7, + 0xf8, 0xb5, 0x0d, 0x46, 0x6c, 0x4c, 0x41, 0x78, /// 0x4490 + 0x6d, 0x4a, 0x1e, 0x27, 0x20, 0x3c, 0x69, 0x70, + 0xc8, 0x29, 0x1c, 0xd0, 0xff, 0x26, 0xc6, 0x29, /// 0x44a0 + 0x1f, 0xd0, 0xc7, 0x29, 0x2c, 0xd0, 0x2f, 0x22, + 0xc0, 0x29, 0x38, 0xd0, 0xc2, 0x29, 0x3a, 0xd0, /// 0x44b0 + 0x3d, 0x29, 0x0f, 0xd1, 0x81, 0x78, 0x22, 0x29, + 0x0c, 0xd1, 0xc0, 0x78, 0x07, 0x28, 0x09, 0xd1, /// 0x44c0 + 0x5f, 0x48, 0x2f, 0x70, 0xc1, 0x7e, 0x10, 0x22, + 0x11, 0x43, 0xc1, 0x76, 0xa0, 0x8e, 0x08, 0x21, /// 0x44d0 + 0x88, 0x43, 0xa0, 0x86, 0xf8, 0xbd, 0x41, 0x88, + 0x10, 0x46, 0xfd, 0xf7, 0x75, 0xfa, 0x20, 0x85, /// 0x44e0 + 0x0c, 0xe0, 0x41, 0x88, 0x10, 0x46, 0xfd, 0xf7, + 0x6f, 0xfa, 0x53, 0x4a, 0xe0, 0x84, 0x56, 0x71, /// 0x44f0 + 0x62, 0x8c, 0x31, 0x46, 0x82, 0x42, 0x0e, 0xd8, + 0x10, 0x46, 0x0c, 0xe0, 0x2f, 0x70, 0xf8, 0xbd, /// 0x4500 + 0x41, 0x88, 0x10, 0x46, 0xfd, 0xf7, 0x60, 0xfa, + 0x4b, 0x4a, 0xa0, 0x84, 0x56, 0x71, 0x62, 0x8c, /// 0x4510 + 0x31, 0x46, 0x82, 0x42, 0xf0, 0xd2, 0x60, 0x84, + 0x00, 0xf0, 0xf9, 0xf9, 0xee, 0xe7, 0x01, 0x21, /// 0x4520 + 0x40, 0x88, 0x89, 0x07, 0x02, 0xe0, 0x40, 0x88, + 0x01, 0x21, 0x49, 0x07, 0x40, 0x18, 0x2a, 0x70, /// 0x4530 + 0x00, 0x78, 0xa8, 0x70, 0xf8, 0xbd, 0x70, 0xb5, + 0x0c, 0x46, 0x41, 0x4a, 0x41, 0x78, 0x3e, 0x4b, /// 0x4540 + 0x20, 0x3a, 0x1e, 0x25, 0x61, 0x70, 0xc5, 0x29, + 0x09, 0xd0, 0xcd, 0x29, 0x06, 0xd1, 0x80, 0x78, /// 0x4550 + 0x18, 0x71, 0x59, 0x79, 0x50, 0x8c, 0x00, 0xf0, + 0xda, 0xf9, 0x25, 0x70, 0x70, 0xbd, 0x81, 0x78, /// 0x4560 + 0x59, 0x71, 0xf7, 0xe7, 0x70, 0xb5, 0x0c, 0x46, + 0x41, 0x78, 0x61, 0x70, 0x05, 0x29, 0x23, 0xd0, /// 0x4570 + 0x2f, 0x26, 0x31, 0x4b, 0xc9, 0x29, 0x2e, 0xd0, + 0x31, 0x4a, 0x33, 0x48, 0x20, 0x3a, 0x3f, 0x25, /// 0x4580 + 0xca, 0x29, 0x2b, 0xd0, 0xcb, 0x29, 0x2b, 0xd0, + 0xcc, 0x29, 0x31, 0xd0, 0x04, 0x29, 0x31, 0xd0, /// 0x4590 + 0x06, 0x29, 0x31, 0xd0, 0x07, 0x29, 0x31, 0xd0, + 0xce, 0x29, 0x31, 0xd0, 0xc4, 0x29, 0x0a, 0xd1, /// 0x45a0 + 0x18, 0x7b, 0x41, 0x08, 0x49, 0x00, 0xc0, 0x07, + 0xc2, 0x17, 0x01, 0x20, 0x90, 0x43, 0x01, 0x43, /// 0x45b0 + 0x19, 0x73, 0x1e, 0x20, 0x20, 0x70, 0x70, 0xbd, + 0x5f, 0x20, 0x20, 0x70, 0x23, 0x48, 0x01, 0x79, /// 0x45c0 + 0xa1, 0x70, 0x81, 0x88, 0x09, 0x0a, 0xe1, 0x70, + 0x41, 0x68, 0x09, 0x0c, 0x21, 0x71, 0x40, 0x68, /// 0x45d0 + 0x00, 0x0e, 0x60, 0x71, 0x70, 0xbd, 0x26, 0x70, + 0x58, 0x79, 0x13, 0xe0, 0xd1, 0x8c, 0x00, 0xe0, /// 0x45e0 + 0x91, 0x8c, 0xfd, 0xf7, 0xf1, 0xf9, 0x25, 0x70, + 0xa0, 0x70, 0x00, 0x0a, 0xe0, 0x70, 0x70, 0xbd, /// 0x45f0 + 0x11, 0x8d, 0xf6, 0xe7, 0x51, 0x8c, 0xf4, 0xe7, + 0xd0, 0x8d, 0xf4, 0xe7, 0x10, 0x8e, 0xf2, 0xe7, /// 0x4600 + 0x26, 0x70, 0x18, 0x79, 0xa0, 0x70, 0x70, 0xbd, + 0x3e, 0xb5, 0x04, 0x46, 0x00, 0x78, 0xfd, 0xf7, /// 0x4610 + 0x6d, 0xfe, 0x0b, 0x48, 0x06, 0x22, 0x21, 0x46, + 0x10, 0x38, 0xfc, 0xf7, 0x72, 0xfa, 0x00, 0x20, /// 0x4620 + 0x69, 0x46, 0x08, 0x70, 0x20, 0x78, 0x38, 0x28, + 0x2d, 0xd0, 0x16, 0xdc, 0x18, 0x28, 0x26, 0xd0, /// 0x4630 + 0x28, 0x28, 0x0d, 0xe0, 0x30, 0x01, 0x00, 0x20, + 0x70, 0x04, 0x00, 0x20, 0x30, 0x02, 0x00, 0x20, /// 0x4640 + 0x60, 0x00, 0x00, 0x20, 0x28, 0x23, 0x00, 0x00, + 0x60, 0xea, 0x00, 0x00, 0x40, 0x04, 0x00, 0x20, /// 0x4650 + 0x32, 0xd1, 0x20, 0x46, 0xff, 0xf7, 0x6f, 0xff, + 0x06, 0xe0, 0x48, 0x28, 0x17, 0xd0, 0x58, 0x28, /// 0x4660 + 0x2a, 0xd1, 0x20, 0x46, 0xff, 0xf7, 0xc9, 0xfe, + 0x68, 0x46, 0x00, 0x78, 0x00, 0x28, 0x23, 0xd0, /// 0x4670 + 0xfd, 0xf7, 0x3c, 0xfe, 0x69, 0x46, 0x09, 0x78, + 0x1e, 0x29, 0x0c, 0xd0, 0x0e, 0xe0, 0x20, 0x46, /// 0x4680 + 0xff, 0xf7, 0x70, 0xff, 0xf0, 0xe7, 0x20, 0x46, + 0xff, 0xf7, 0xfe, 0xfe, 0xec, 0xe7, 0x20, 0x46, /// 0x4690 + 0xff, 0xf7, 0xc9, 0xfe, 0xe8, 0xe7, 0xff, 0x21, + 0x6a, 0x46, 0x51, 0x70, 0x42, 0x1c, 0x69, 0x46, /// 0x46a0 + 0x52, 0x48, 0xfc, 0xf7, 0x2e, 0xfa, 0x51, 0x48, + 0x08, 0x22, 0x18, 0x38, 0xc1, 0x8e, 0x11, 0x43, /// 0x46b0 + 0xc1, 0x86, 0x03, 0x21, 0xa0, 0x30, 0xc1, 0x74, + 0x3e, 0xbd, 0x10, 0xb5, 0x04, 0x46, 0x4c, 0x48, /// 0x46c0 + 0x4a, 0x4b, 0x00, 0x7a, 0x08, 0x3b, 0x21, 0x78, + 0x0c, 0x28, 0x2e, 0xd0, 0x01, 0x29, 0x0b, 0xd0, /// 0x46d0 + 0x51, 0x29, 0x14, 0xd0, 0x71, 0x29, 0x1d, 0xd0, + 0x81, 0x29, 0x04, 0xd1, 0x71, 0x28, 0x02, 0xd1, /// 0x46e0 + 0x60, 0x1c, 0xff, 0xf7, 0x3f, 0xfd, 0x10, 0xbd, + 0x01, 0x28, 0xfc, 0xd1, 0x06, 0x22, 0x21, 0x46, /// 0x46f0 + 0x18, 0x46, 0xfc, 0xf7, 0x06, 0xfa, 0x60, 0x78, + 0xff, 0xf7, 0xeb, 0xfc, 0x10, 0xbd, 0x03, 0x28, /// 0x4700 + 0xfc, 0xd1, 0x06, 0x22, 0x21, 0x46, 0x18, 0x46, + 0xfc, 0xf7, 0xfb, 0xf9, 0x60, 0x1c, 0xff, 0xf7, /// 0x4710 + 0xf6, 0xfc, 0x10, 0xbd, 0x02, 0x28, 0xfc, 0xd1, + 0x06, 0x22, 0x21, 0x46, 0x18, 0x46, 0xfc, 0xf7, /// 0x4720 + 0xf0, 0xf9, 0x60, 0x1c, 0xff, 0xf7, 0x08, 0xfd, + 0x10, 0xbd, 0x05, 0x29, 0x26, 0xd0, 0x08, 0xdc, /// 0x4730 + 0x01, 0x29, 0xf9, 0xd0, 0x02, 0x29, 0x10, 0xd0, + 0x03, 0x29, 0x17, 0xd0, 0x04, 0x29, 0x08, 0xd1, /// 0x4740 + 0x18, 0xe0, 0x06, 0x29, 0x1e, 0xd0, 0x51, 0x29, + 0xee, 0xd0, 0x71, 0x29, 0xec, 0xd0, 0x81, 0x29, /// 0x4750 + 0xea, 0xd0, 0x20, 0x46, 0xff, 0xf7, 0x58, 0xff, + 0x10, 0xbd, 0x06, 0x22, 0x21, 0x46, 0x18, 0x46, /// 0x4760 + 0xfc, 0xf7, 0xcf, 0xf9, 0x60, 0x78, 0xff, 0xf7, + 0x04, 0xfd, 0x10, 0xbd, 0x60, 0x78, 0xff, 0xf7, /// 0x4770 + 0x1c, 0xfd, 0x10, 0xbd, 0x60, 0x78, 0xff, 0xf7, + 0x15, 0xfe, 0x10, 0xbd, 0x60, 0x78, 0xff, 0xf7, /// 0x4780 + 0x2e, 0xfe, 0x10, 0xbd, 0x60, 0x78, 0xff, 0xf7, + 0x32, 0xfe, 0x10, 0xbd, 0xf8, 0xb5, 0x18, 0x48, /// 0x4790 + 0x17, 0x4e, 0x80, 0x6f, 0x00, 0x27, 0x78, 0x36, + 0x04, 0x68, 0x10, 0xe0, 0x05, 0x46, 0x06, 0xc8, /// 0x47a0 + 0x4a, 0x60, 0x08, 0x38, 0x11, 0x60, 0x07, 0x60, + 0x0c, 0x3d, 0x47, 0x60, 0x28, 0x46, 0xff, 0xf7, /// 0x47b0 + 0x84, 0xff, 0x0a, 0x21, 0x28, 0x46, 0xfc, 0xf7, + 0xb4, 0xf9, 0x20, 0x46, 0x24, 0x68, 0xb0, 0x42, /// 0x47c0 + 0xec, 0xd1, 0xf8, 0xbd, 0x10, 0xb5, 0x0b, 0x4c, + 0x20, 0x7a, 0xc0, 0x07, 0x0c, 0xd0, 0x20, 0x7b, /// 0x47d0 + 0xfd, 0xf7, 0x8c, 0xfd, 0x40, 0x1c, 0xc1, 0xb2, + 0x20, 0x46, 0x0c, 0x30, 0xff, 0xf7, 0x06, 0xfb, /// 0x47e0 + 0x20, 0x7a, 0x40, 0x08, 0x40, 0x00, 0x20, 0x72, + 0x10, 0xbd, 0x00, 0x00, 0x58, 0x00, 0x00, 0x20, /// 0x47f0 + 0x70, 0x04, 0x00, 0x20, 0x40, 0x04, 0x00, 0x20, + 0x01, 0x21, 0xb3, 0x48, 0xc9, 0x03, 0x01, 0x80, /// 0x4800 + 0xb2, 0x49, 0x09, 0x7e, 0xc9, 0x00, 0x49, 0x1c, + 0x01, 0x80, 0x03, 0x21, 0x81, 0x80, 0x01, 0x88, /// 0x4810 + 0x02, 0x22, 0x11, 0x43, 0x01, 0x80, 0x70, 0x47, + 0xac, 0x48, 0x00, 0x7e, 0xc1, 0x00, 0xaa, 0x48, /// 0x4820 + 0x49, 0x1c, 0x01, 0x80, 0x01, 0x88, 0x02, 0x22, + 0x11, 0x43, 0x01, 0x80, 0x70, 0x47, 0x01, 0x20, /// 0x4830 + 0xa5, 0x49, 0xc0, 0x03, 0x08, 0x80, 0xa6, 0x49, + 0x00, 0x20, 0x08, 0x76, 0xa5, 0x4a, 0xd0, 0x21, /// 0x4840 + 0x91, 0x83, 0xa5, 0x49, 0x08, 0x72, 0xa2, 0x48, + 0x04, 0x21, 0x20, 0x38, 0x41, 0x73, 0x70, 0x47, /// 0x4850 + 0xf8, 0xb5, 0x9d, 0x48, 0x00, 0x25, 0x05, 0x83, + 0x9d, 0x4e, 0x9f, 0x4c, 0x01, 0x20, 0x25, 0x72, /// 0x4860 + 0x30, 0x76, 0x31, 0x46, 0xa5, 0x76, 0x80, 0x31, + 0xc8, 0x71, 0xff, 0x20, 0xc0, 0x39, 0x88, 0x76, /// 0x4870 + 0xf1, 0x7e, 0xef, 0x22, 0x11, 0x40, 0xf1, 0x76, + 0x94, 0x49, 0x94, 0x4f, 0x20, 0x39, 0x0d, 0x83, /// 0x4880 + 0x60, 0x71, 0x30, 0x46, 0x20, 0x30, 0xc5, 0x77, + 0x08, 0x46, 0x40, 0x30, 0x40, 0x68, 0x20, 0x60, /// 0x4890 + 0x20, 0x7b, 0xf7, 0x21, 0x08, 0x40, 0x20, 0x73, + 0xe0, 0x3f, 0x32, 0x46, 0x78, 0x8e, 0x60, 0x32, /// 0x48a0 + 0x10, 0x82, 0xb9, 0x8e, 0x51, 0x82, 0x00, 0xf0, + 0xbc, 0xff, 0xe0, 0x7e, 0x40, 0x1c, 0xc0, 0xb2, /// 0x48b0 + 0xe0, 0x76, 0x03, 0x28, 0x00, 0xd3, 0xe5, 0x76, + 0x83, 0x48, 0x01, 0x88, 0x02, 0x22, 0x91, 0x43, /// 0x48c0 + 0x01, 0x80, 0x83, 0x48, 0x85, 0x49, 0x20, 0x38, + 0x80, 0x8e, 0x08, 0x42, 0x0b, 0xd1, 0x01, 0x05, /// 0x48d0 + 0x09, 0xd4, 0xc1, 0x04, 0x07, 0xd4, 0x41, 0x04, + 0x05, 0xd4, 0x01, 0x04, 0x03, 0xd4, 0xc1, 0x06, /// 0x48e0 + 0x01, 0xd4, 0x80, 0x04, 0x04, 0xd5, 0x30, 0x7e, + 0x00, 0x28, 0x01, 0xd0, 0xff, 0xf7, 0x9f, 0xff, /// 0x48f0 + 0x0a, 0x20, 0xb8, 0x70, 0x00, 0x20, 0x7a, 0x4a, + 0xfb, 0x23, 0x2c, 0x21, 0x41, 0x43, 0x89, 0x18, /// 0x4900 + 0x8c, 0x78, 0x1c, 0x40, 0x8c, 0x70, 0x40, 0x1c, + 0x02, 0x28, 0xf6, 0xdb, 0xf8, 0xbd, 0xfe, 0xb5, /// 0x4910 + 0x6f, 0x4f, 0x04, 0x46, 0x80, 0x37, 0xf8, 0x79, + 0x65, 0x08, 0x01, 0x28, 0x0d, 0xd0, 0xff, 0x20, /// 0x4920 + 0x40, 0x1a, 0x68, 0x43, 0x00, 0x0a, 0x01, 0x90, + 0x60, 0x1e, 0x39, 0x7a, 0x80, 0xb2, 0x00, 0x90, /// 0x4930 + 0xa0, 0x1c, 0x86, 0xb2, 0x01, 0x29, 0x15, 0xd0, + 0x2a, 0xe0, 0x28, 0x46, 0x48, 0x43, 0x02, 0x0a, /// 0x4940 + 0x61, 0x48, 0x01, 0x21, 0x20, 0x30, 0x81, 0x81, + 0x05, 0x82, 0x69, 0x1c, 0x81, 0x82, 0x04, 0x83, /// 0x4950 + 0x5d, 0x4b, 0xa1, 0x1a, 0x99, 0x83, 0xaa, 0x1a, + 0x02, 0x80, 0x52, 0x1c, 0x82, 0x80, 0x49, 0x1e, /// 0x4960 + 0x01, 0x81, 0x24, 0xe0, 0x58, 0x48, 0x01, 0x21, + 0x20, 0x30, 0x81, 0x81, 0x05, 0x82, 0x85, 0x82, /// 0x4970 + 0x00, 0x9a, 0x02, 0x83, 0x81, 0x80, 0x06, 0x81, + 0x53, 0x49, 0x89, 0x8b, 0x49, 0x1d, 0x01, 0x80, /// 0x4980 + 0x55, 0x49, 0x09, 0x79, 0xff, 0x31, 0x01, 0x31, + 0x81, 0x83, 0x14, 0x20, 0xfc, 0xf7, 0x4c, 0xf8, /// 0x4990 + 0x4d, 0x48, 0x01, 0x21, 0x20, 0x30, 0x81, 0x81, + 0x01, 0x9a, 0xaa, 0x1a, 0x02, 0x82, 0x82, 0x82, /// 0x49a0 + 0x00, 0x9a, 0x02, 0x83, 0x48, 0x4a, 0x96, 0x83, + 0x06, 0x80, 0x81, 0x80, 0x06, 0x81, 0xf8, 0x79, /// 0x49b0 + 0x38, 0x72, 0x0f, 0x20, 0x00, 0x03, 0x44, 0x49, + 0x20, 0x43, 0x08, 0x83, 0x46, 0x48, 0x42, 0x49, /// 0x49c0 + 0x00, 0x79, 0x20, 0x31, 0xff, 0x30, 0x01, 0x30, + 0x88, 0x83, 0x41, 0x48, 0x20, 0x38, 0x44, 0x84, /// 0x49d0 + 0xfe, 0xbd, 0x3f, 0x4a, 0x10, 0xb5, 0x20, 0x3a, + 0x91, 0x8c, 0x51, 0x84, 0x00, 0x28, 0x02, 0xd0, /// 0x49e0 + 0x01, 0x28, 0x03, 0xd0, 0x04, 0xe0, 0x01, 0x23, + 0x9b, 0x03, 0x01, 0xe0, 0x01, 0x23, 0xdb, 0x03, /// 0x49f0 + 0x35, 0x48, 0x00, 0x22, 0x20, 0x30, 0x82, 0x81, + 0x01, 0x82, 0x82, 0x80, 0x01, 0x81, 0x82, 0x82, /// 0x4a00 + 0x01, 0x83, 0x31, 0x4c, 0xa2, 0x83, 0x01, 0x80, + 0x19, 0x43, 0x21, 0x83, 0x32, 0x49, 0x09, 0x79, /// 0x4a10 + 0xff, 0x31, 0x01, 0x31, 0x81, 0x83, 0x10, 0xbd, + 0x32, 0x48, 0x01, 0x21, 0x01, 0x80, 0x05, 0x22, /// 0x4a20 + 0x02, 0x80, 0x82, 0x80, 0x01, 0x81, 0x08, 0x22, + 0x82, 0x81, 0xff, 0x22, 0x02, 0x82, 0x2e, 0x4a, /// 0x4a30 + 0x11, 0x70, 0x04, 0x23, 0x13, 0x71, 0x07, 0x22, + 0x02, 0x80, 0x2a, 0x4a, 0x00, 0x23, 0x20, 0x32, /// 0x4a40 + 0x13, 0x80, 0x2a, 0x4b, 0x13, 0x80, 0x01, 0x75, + 0x70, 0x47, 0x30, 0xb4, 0x22, 0x4a, 0x20, 0x4b, /// 0x4a50 + 0x14, 0x7b, 0x20, 0x3b, 0x11, 0x46, 0xe5, 0x07, + 0x58, 0x8c, 0x49, 0x79, 0x00, 0x2d, 0x05, 0xd0, /// 0x4a60 + 0x63, 0x07, 0x2f, 0xd5, 0xfb, 0x23, 0x1c, 0x40, + 0x14, 0x73, 0x29, 0xe0, 0x09, 0x24, 0x14, 0x57, /// 0x4a70 + 0x00, 0x2c, 0x27, 0xd0, 0x10, 0xdd, 0xff, 0x29, + 0x02, 0xd0, 0x09, 0xd2, 0x49, 0x1c, 0x08, 0xe0, /// 0x4a80 + 0xd9, 0x8c, 0x88, 0x42, 0x01, 0xd2, 0x40, 0x1c, + 0x00, 0xe0, 0x08, 0x46, 0x58, 0x84, 0x01, 0xe0, /// 0x4a90 + 0xff, 0x21, 0x51, 0x71, 0x64, 0x1e, 0x10, 0xe0, + 0x9d, 0x8c, 0xa8, 0x42, 0x06, 0xd1, 0x14, 0x29, /// 0x4aa0 + 0x01, 0xd9, 0x49, 0x1e, 0x00, 0xe0, 0x14, 0x21, + 0x51, 0x71, 0x05, 0xe0, 0xa8, 0x42, 0x01, 0xd9, /// 0x4ab0 + 0x40, 0x1e, 0x00, 0xe0, 0x28, 0x46, 0x58, 0x84, + 0x64, 0x1c, 0x54, 0x72, 0x51, 0x79, 0x58, 0x8c, /// 0x4ac0 + 0x30, 0xbc, 0x24, 0xe7, 0x30, 0xbc, 0x70, 0x47, + 0x00, 0x34, 0x00, 0x40, 0x10, 0x02, 0x00, 0x20, /// 0x4ad0 + 0x60, 0x00, 0x00, 0x20, 0x00, 0x30, 0x00, 0x40, + 0x70, 0x04, 0x00, 0x20, 0x01, 0x04, 0x00, 0x00, /// 0x4ae0 + 0xe0, 0x03, 0x00, 0x20, 0x00, 0x38, 0x00, 0x40, + 0x00, 0x3c, 0x00, 0x40, 0x08, 0x80, 0x00, 0x00, /// 0x4af0 + 0x70, 0xb5, 0xfe, 0x48, 0x00, 0x24, 0x01, 0x7a, + 0x01, 0x29, 0x20, 0xd1, 0xfc, 0x4a, 0x2e, 0x23, /// 0x4b00 + 0x11, 0x46, 0x40, 0x39, 0xd3, 0x5e, 0x4d, 0x89, + 0xab, 0x42, 0x03, 0xdc, 0x03, 0x8a, 0x8d, 0x89, /// 0x4b10 + 0xab, 0x42, 0x14, 0xd9, 0x03, 0x7e, 0x5d, 0x1c, + 0x05, 0x76, 0x03, 0x2b, 0x0e, 0xd3, 0x04, 0x76, /// 0x4b20 + 0x90, 0x8e, 0x01, 0x23, 0xdb, 0x03, 0x18, 0x43, + 0x90, 0x86, 0xc8, 0x6a, 0x01, 0x22, 0x10, 0x43, /// 0x4b30 + 0xc8, 0x62, 0x10, 0x46, 0xfc, 0xf7, 0x10, 0xf8, + 0xff, 0xf7, 0x8a, 0xfe, 0x70, 0xbd, 0x04, 0x76, /// 0x4b40 + 0x70, 0xbd, 0xf8, 0xb5, 0xea, 0x4c, 0x05, 0x21, + 0xa0, 0x8e, 0x89, 0x02, 0x08, 0x42, 0x7d, 0xd1, /// 0x4b50 + 0x01, 0x05, 0x7b, 0xd4, 0x81, 0x04, 0x79, 0xd4, + 0xc1, 0x07, 0x77, 0xd1, 0x41, 0x04, 0x75, 0xd4, /// 0x4b60 + 0xc1, 0x06, 0x73, 0xd4, 0x00, 0x04, 0x71, 0xd4, + 0xe0, 0x4e, 0x20, 0x46, 0x31, 0x7a, 0xa0, 0x30, /// 0x4b70 + 0x00, 0x90, 0x01, 0x29, 0x14, 0xd8, 0xb0, 0x7e, + 0x00, 0x28, 0x11, 0xd0, 0x06, 0x28, 0x0f, 0xd8, /// 0x4b80 + 0x23, 0x21, 0x00, 0x9a, 0x41, 0x43, 0xd2, 0x7f, + 0x40, 0x1c, 0x89, 0x18, 0xb0, 0x76, 0xff, 0x29, /// 0x4b90 + 0x02, 0xd3, 0xff, 0x21, 0x00, 0x20, 0xb0, 0x76, + 0xc9, 0xb2, 0x20, 0x8d, 0xff, 0xf7, 0xb7, 0xfe, /// 0x4ba0 + 0xd2, 0x48, 0xd3, 0x4e, 0x00, 0x7a, 0xd3, 0x4f, + 0x20, 0x36, 0x03, 0x28, 0x06, 0xd0, 0x06, 0xdc, /// 0x4bb0 + 0x00, 0x28, 0x25, 0xd0, 0x01, 0x28, 0x7a, 0xd0, + 0x02, 0x28, 0x69, 0xd1, 0x8e, 0xe0, 0x0b, 0x28, /// 0x4bc0 + 0x76, 0xd0, 0x0c, 0x28, 0x64, 0xd1, 0xf0, 0x7e, + 0xc1, 0x06, 0xca, 0x48, 0x40, 0x38, 0x00, 0x29, /// 0x4bd0 + 0x6f, 0xdb, 0x01, 0x8b, 0x49, 0x1c, 0x89, 0xb2, + 0x01, 0x83, 0xc7, 0x48, 0x81, 0x42, 0x0e, 0xd3, /// 0x4be0 + 0xa0, 0x8e, 0x08, 0x21, 0x08, 0x43, 0xa0, 0x86, + 0xc1, 0x48, 0x01, 0x22, 0x40, 0x38, 0xc1, 0x6a, /// 0x4bf0 + 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, 0xfb, 0xf7, + 0xaf, 0xff, 0xff, 0xf7, 0x29, 0xfe, 0x78, 0xe0, /// 0x4c00 + 0xbc, 0x48, 0xbe, 0x49, 0x20, 0x38, 0x00, 0x7e, + 0xc0, 0x00, 0xc0, 0x1c, 0x08, 0x80, 0xb7, 0x4d, /// 0x4c10 + 0xbb, 0x49, 0xe8, 0x7e, 0x00, 0x02, 0x00, 0x1d, + 0x88, 0x82, 0x78, 0x68, 0x29, 0x68, 0x0a, 0x23, /// 0x4c20 + 0x42, 0x1a, 0x71, 0x7e, 0x59, 0x43, 0x8a, 0x42, + 0x32, 0xd9, 0xb6, 0x49, 0x0a, 0x8d, 0xb0, 0x49, /// 0x4c30 + 0x40, 0x31, 0x0a, 0x82, 0x31, 0x7e, 0xc9, 0x07, + 0x41, 0xd0, 0x20, 0x8e, 0xb2, 0x49, 0x40, 0x18, /// 0x4c40 + 0xb2, 0x49, 0x88, 0x42, 0x25, 0xd2, 0xaa, 0x4e, + 0x40, 0x3e, 0x00, 0xe0, 0x20, 0xe0, 0xb0, 0x8e, /// 0x4c50 + 0x40, 0x07, 0x04, 0xd4, 0x02, 0x20, 0xfb, 0xf7, + 0x7f, 0xff, 0x30, 0x6b, 0xf0, 0x62, 0xff, 0x21, /// 0x4c60 + 0x70, 0x6b, 0x3d, 0x31, 0x08, 0x43, 0x70, 0x63, + 0xa8, 0x7e, 0x40, 0x1c, 0xa8, 0x76, 0x00, 0x98, /// 0x4c70 + 0xc1, 0x7f, 0x20, 0x8d, 0xff, 0xf7, 0x4b, 0xfe, + 0xa0, 0x48, 0x01, 0x88, 0x02, 0x22, 0x11, 0x43, /// 0x4c80 + 0x01, 0x80, 0x29, 0x7b, 0xc9, 0x07, 0x15, 0xd0, + 0x0c, 0x21, 0x29, 0x72, 0xfb, 0x21, 0x01, 0x80, /// 0x4c90 + 0xf8, 0xbd, 0xa0, 0x8e, 0x10, 0x21, 0x08, 0x43, + 0xa0, 0x86, 0x95, 0x48, 0x01, 0x22, 0x40, 0x38, /// 0x4ca0 + 0xc1, 0x6a, 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, + 0xfb, 0xf7, 0x56, 0xff, 0xf8, 0xbd, 0x08, 0xe0, /// 0x4cb0 + 0x14, 0xe0, 0x1c, 0xe0, 0x78, 0x68, 0x28, 0x60, + 0x01, 0x20, 0x28, 0x72, 0xf6, 0xe7, 0x28, 0x60, /// 0x4cc0 + 0xf4, 0xe7, 0x8a, 0x48, 0x79, 0x68, 0x00, 0x68, + 0x08, 0x1a, 0x5a, 0x28, 0xee, 0xd9, 0xa0, 0x8e, /// 0x4cd0 + 0x8f, 0x49, 0x08, 0x40, 0xa0, 0x86, 0xff, 0xf7, + 0x0b, 0xff, 0x05, 0xe0, 0x83, 0x48, 0x79, 0x68, /// 0x4ce0 + 0x00, 0x68, 0x08, 0x1a, 0xaa, 0x28, 0xe1, 0xd9, + 0xff, 0xf7, 0xb2, 0xfd, 0xde, 0xe7, 0x00, 0x21, /// 0x4cf0 + 0x01, 0x83, 0x00, 0x98, 0x40, 0x7a, 0x00, 0x28, + 0x45, 0xd0, 0x7c, 0x48, 0x79, 0x68, 0x00, 0x68, /// 0x4d00 + 0x08, 0x1a, 0xff, 0x21, 0x91, 0x31, 0x88, 0x42, + 0x07, 0xd9, 0xf2, 0x7e, 0x08, 0x23, 0x1a, 0x43, /// 0x4d10 + 0xf2, 0x76, 0xfc, 0xf7, 0x59, 0xfe, 0xc5, 0xb2, + 0x02, 0xe0, 0x7e, 0x49, 0x00, 0x20, 0x08, 0x71, /// 0x4d20 + 0xf0, 0x7e, 0x01, 0x07, 0x2f, 0xd5, 0xf7, 0x21, + 0x08, 0x40, 0xf0, 0x76, 0x03, 0x2d, 0x00, 0xd3, /// 0x4d30 + 0x00, 0x25, 0x78, 0x48, 0x01, 0x79, 0xa9, 0x42, + 0x0b, 0xd0, 0x71, 0x49, 0x05, 0x71, 0x88, 0x8a, /// 0x4d40 + 0x40, 0x05, 0x40, 0x0f, 0x40, 0x1c, 0x04, 0x28, + 0x00, 0xd9, 0x00, 0x20, 0x00, 0x02, 0x00, 0x1d, /// 0x4d50 + 0x88, 0x82, 0x02, 0x2d, 0x17, 0xd3, 0x65, 0x48, + 0x01, 0x7b, 0x0a, 0x07, 0x02, 0xd5, 0x42, 0x7e, /// 0x4d60 + 0x1e, 0x2a, 0x10, 0xd9, 0x08, 0x22, 0x11, 0x43, + 0x01, 0x73, 0x00, 0x21, 0x41, 0x76, 0x41, 0x79, /// 0x4d70 + 0x4a, 0x1d, 0xff, 0x2a, 0x01, 0xd2, 0x49, 0x1d, + 0x00, 0xe0, 0xff, 0x21, 0xc9, 0xb2, 0x41, 0x71, /// 0x4d80 + 0x60, 0x8c, 0xff, 0xf7, 0xc4, 0xfd, 0x59, 0x48, + 0x01, 0x7b, 0xc9, 0x07, 0x19, 0xd1, 0x79, 0x68, /// 0x4d90 + 0x00, 0x68, 0x09, 0x1a, 0x58, 0x48, 0x81, 0x42, + 0x13, 0xd9, 0x55, 0x48, 0xff, 0x22, 0x40, 0x38, /// 0x4da0 + 0x41, 0x6b, 0x3d, 0x32, 0x91, 0x43, 0x41, 0x63, + 0xa1, 0x8e, 0xff, 0x22, 0x01, 0x32, 0x11, 0x43, /// 0x4db0 + 0xa1, 0x86, 0xc1, 0x6a, 0x01, 0x22, 0x11, 0x43, + 0xc1, 0x62, 0x10, 0x46, 0xfb, 0xf7, 0xcc, 0xfe, /// 0x4dc0 + 0x92, 0xe7, 0xe0, 0x8e, 0xc0, 0x06, 0x12, 0xd5, + 0xa0, 0x8f, 0x41, 0x1c, 0xa1, 0x87, 0xe1, 0x8f, /// 0x4dd0 + 0x88, 0x42, 0x8b, 0xd9, 0xa0, 0x8e, 0x80, 0x21, + 0x08, 0x43, 0xa0, 0x86, 0xff, 0xf7, 0x27, 0xfd, /// 0x4de0 + 0x00, 0x20, 0xa0, 0x87, 0xe0, 0x8e, 0x10, 0x21, + 0x88, 0x43, 0xe0, 0x86, 0x5e, 0xe7, 0x00, 0x20, /// 0x4df0 + 0xa0, 0x87, 0x5b, 0xe7, 0x10, 0xb5, 0x48, 0x48, + 0x80, 0x89, 0x80, 0x06, 0x80, 0x0f, 0x12, 0xd0, /// 0x4e00 + 0x3b, 0x49, 0x88, 0x8e, 0x42, 0x04, 0x0e, 0xd4, + 0x01, 0x22, 0x92, 0x03, 0x10, 0x43, 0x88, 0x86, /// 0x4e10 + 0x08, 0x46, 0x40, 0x38, 0xc1, 0x6a, 0x01, 0x22, + 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, 0xfb, 0xf7, /// 0x4e20 + 0x9b, 0xfe, 0xff, 0xf7, 0x15, 0xfd, 0x10, 0xbd, + 0xf8, 0xb5, 0x31, 0x4c, 0x01, 0x27, 0x20, 0x8e, /// 0x4e30 + 0x21, 0x8c, 0x25, 0x46, 0x40, 0x3d, 0x2d, 0x4e, + 0x88, 0x42, 0x13, 0xd2, 0xa1, 0x8e, 0xc8, 0x04, /// 0x4e40 + 0x12, 0xd4, 0x72, 0x7b, 0x50, 0x1c, 0x70, 0x73, + 0x28, 0x2a, 0x0d, 0xd9, 0x38, 0x03, 0x01, 0x43, /// 0x4e50 + 0xa1, 0x86, 0xe8, 0x6a, 0x38, 0x43, 0xe8, 0x62, + 0x01, 0x20, 0xfb, 0xf7, 0x7d, 0xfe, 0xff, 0xf7, /// 0x4e60 + 0xf7, 0xfc, 0x01, 0xe0, 0x00, 0x20, 0x70, 0x73, + 0x62, 0x8e, 0xa0, 0x8d, 0x01, 0x21, 0xc9, 0x02, /// 0x4e70 + 0x82, 0x42, 0x0d, 0xd9, 0xa0, 0x8e, 0x02, 0x05, + 0x12, 0xd4, 0x08, 0x43, 0xa0, 0x86, 0xe8, 0x6a, /// 0x4e80 + 0x38, 0x43, 0xe8, 0x62, 0x01, 0x20, 0xfb, 0xf7, + 0x67, 0xfe, 0xff, 0xf7, 0xe1, 0xfc, 0x07, 0xe0, /// 0x4e90 + 0x19, 0x4b, 0x5b, 0x42, 0xc0, 0x18, 0x82, 0x42, + 0x02, 0xda, 0xa0, 0x8e, 0x88, 0x43, 0xa0, 0x86, /// 0x4ea0 + 0x30, 0x8a, 0x61, 0x8d, 0x88, 0x42, 0x06, 0xd8, + 0x1a, 0x48, 0x2e, 0x21, 0x40, 0x30, 0x61, 0x5e, /// 0x4eb0 + 0x40, 0x88, 0x81, 0x42, 0x0e, 0xdd, 0xa0, 0x8e, + 0x41, 0x05, 0x0b, 0xd4, 0x01, 0x21, 0x89, 0x02, /// 0x4ec0 + 0x08, 0x43, 0xa0, 0x86, 0xe8, 0x6a, 0x38, 0x43, + 0xe8, 0x62, 0x01, 0x20, 0xfb, 0xf7, 0x44, 0xfe, /// 0x4ed0 + 0xff, 0xf7, 0xbe, 0xfc, 0x61, 0x8d, 0x06, 0x48, + 0x33, 0x8a, 0x0a, 0x46, 0xc8, 0x3a, 0x20, 0x30, /// 0x4ee0 + 0x93, 0x42, 0x1f, 0xdd, 0xc2, 0x7e, 0x54, 0x07, + 0x1c, 0xd4, 0x17, 0xe0, 0x70, 0x04, 0x00, 0x20, /// 0x4ef0 + 0x40, 0x00, 0x00, 0x20, 0x30, 0x02, 0x00, 0x20, + 0xdc, 0x05, 0x00, 0x00, 0x00, 0x34, 0x00, 0x40, /// 0x4f00 + 0x60, 0x40, 0x00, 0x40, 0x70, 0x03, 0x00, 0x20, + 0x8f, 0xe8, 0xff, 0xff, 0xcf, 0x07, 0x00, 0x00, /// 0x4f10 + 0xfe, 0xc3, 0xff, 0xff, 0x30, 0x01, 0x00, 0x20, + 0x20, 0x48, 0x00, 0x40, 0x04, 0x21, 0x0a, 0x43, /// 0x4f20 + 0xc2, 0x76, 0xc3, 0xe6, 0xff, 0x39, 0x2d, 0x39, + 0x8b, 0x42, 0xfa, 0xda, 0xc1, 0x7e, 0x4a, 0x07, /// 0x4f30 + 0xf7, 0xd5, 0xfb, 0x22, 0x11, 0x40, 0xc1, 0x76, + 0xb8, 0xe6, 0xfe, 0x49, 0x3a, 0x22, 0x8a, 0x5e, /// 0x4f40 + 0x89, 0x8f, 0x42, 0x43, 0xd0, 0x0a, 0x40, 0x18, + 0x00, 0xb2, 0x00, 0x28, 0x00, 0xda, 0x00, 0x20, /// 0x4f50 + 0x80, 0xb2, 0x70, 0x47, 0xf8, 0xb5, 0xf7, 0x4e, + 0x02, 0x21, 0x60, 0x3e, 0xf0, 0x7e, 0x09, 0x22, /// 0x4f60 + 0x08, 0x43, 0xf0, 0x76, 0x04, 0x21, 0x00, 0x20, + 0xfb, 0xf7, 0xef, 0xfa, 0xf2, 0x49, 0x88, 0x42, /// 0x4f70 + 0x7e, 0xd0, 0x09, 0x22, 0x04, 0x21, 0x00, 0x20, + 0xfb, 0xf7, 0xe7, 0xfa, 0xef, 0x4d, 0x40, 0x08, /// 0x4f80 + 0xa9, 0x7c, 0x2c, 0x46, 0x4a, 0x00, 0xee, 0x49, + 0x20, 0x3c, 0x52, 0x18, 0x09, 0x21, 0x89, 0x01, /// 0x4f90 + 0x51, 0x18, 0x08, 0x83, 0x20, 0x8b, 0x61, 0x8b, + 0xe2, 0x8b, 0x40, 0x18, 0xa1, 0x8b, 0x89, 0x18, /// 0x4fa0 + 0x40, 0x18, 0x81, 0x08, 0xe7, 0x48, 0x00, 0x88, + 0x08, 0x1a, 0x00, 0xb2, 0x00, 0x28, 0x00, 0xda, /// 0x4fb0 + 0x00, 0x20, 0x80, 0x01, 0x0a, 0x21, 0xfc, 0xf7, + 0x1d, 0xfd, 0xde, 0x49, 0xdd, 0x4f, 0xc0, 0x39, /// 0x4fc0 + 0x89, 0x78, 0x80, 0x3f, 0x80, 0xb2, 0x05, 0x29, + 0x04, 0xd3, 0x3b, 0x21, 0x48, 0x43, 0x32, 0x21, /// 0x4fd0 + 0xfc, 0xf7, 0xfa, 0xfc, 0x78, 0x86, 0x03, 0x22, + 0x04, 0x21, 0x01, 0x20, 0xfb, 0xf7, 0xb5, 0xfa, /// 0x4fe0 + 0xd5, 0x49, 0x88, 0x42, 0x44, 0xd0, 0x03, 0x22, + 0x04, 0x21, 0x01, 0x20, 0xfb, 0xf7, 0xad, 0xfa, /// 0x4ff0 + 0xc0, 0x03, 0x01, 0x0c, 0xa8, 0x7c, 0x42, 0x00, + 0xd1, 0x48, 0x12, 0x18, 0x09, 0x20, 0x80, 0x01, /// 0x5000 + 0x10, 0x18, 0x01, 0x85, 0xcd, 0x48, 0x08, 0x30, + 0xfb, 0xf7, 0xdb, 0xfa, 0x00, 0xb2, 0x00, 0x28, /// 0x5010 + 0x00, 0xda, 0x00, 0x20, 0xff, 0xf7, 0x91, 0xff, + 0x00, 0xb2, 0xcb, 0x4a, 0xf8, 0x85, 0xd1, 0x7b, /// 0x5020 + 0x49, 0x1c, 0xc9, 0xb2, 0xd1, 0x73, 0x05, 0x29, + 0x12, 0xd3, 0x00, 0x21, 0xd1, 0x73, 0x91, 0x8a, /// 0x5030 + 0x08, 0x18, 0x80, 0xb2, 0x90, 0x82, 0x91, 0x7c, + 0x49, 0x1c, 0xc9, 0xb2, 0x91, 0x74, 0x0f, 0x29, /// 0x5040 + 0x06, 0xd3, 0xfc, 0xf7, 0xc1, 0xfc, 0xc0, 0x49, + 0x08, 0x82, 0x00, 0x20, 0x88, 0x74, 0x88, 0x82, /// 0x5050 + 0x02, 0x22, 0x08, 0x21, 0x03, 0x20, 0xfb, 0xf7, + 0x78, 0xfa, 0xb7, 0x49, 0x88, 0x42, 0x43, 0xd0, /// 0x5060 + 0x02, 0x22, 0x08, 0x21, 0x03, 0x20, 0xfb, 0xf7, + 0x70, 0xfa, 0xa9, 0x7c, 0x4a, 0x00, 0x00, 0xe0, /// 0x5070 + 0x3a, 0xe0, 0xb3, 0x49, 0x52, 0x18, 0x09, 0x21, + 0x89, 0x01, 0x51, 0x18, 0x08, 0x84, 0x20, 0x8c, /// 0x5080 + 0x61, 0x8c, 0xe2, 0x8c, 0x40, 0x18, 0xa1, 0x8c, + 0x89, 0x18, 0x40, 0x18, 0x81, 0x08, 0xad, 0x48, /// 0x5090 + 0x00, 0x88, 0x08, 0x1a, 0x00, 0xb2, 0x00, 0x28, + 0x00, 0xda, 0x00, 0x20, 0x29, 0x21, 0x48, 0x43, /// 0x50a0 + 0xc1, 0x17, 0x49, 0x0f, 0x08, 0x18, 0x40, 0x03, + 0x00, 0x0c, 0x38, 0x86, 0x04, 0x22, 0x08, 0x21, /// 0x50b0 + 0x07, 0x20, 0xfb, 0xf7, 0x4a, 0xfa, 0xa0, 0x49, + 0x88, 0x42, 0x15, 0xd0, 0x04, 0x22, 0x08, 0x21, /// 0x50c0 + 0x07, 0x20, 0xfb, 0xf7, 0x42, 0xfa, 0xa1, 0x49, + 0x88, 0x42, 0x00, 0xd2, 0x08, 0x46, 0x4b, 0x21, /// 0x50d0 + 0x48, 0x43, 0x7d, 0x21, 0xc9, 0x00, 0xfc, 0xf7, + 0x77, 0xfc, 0xae, 0x38, 0xb0, 0x76, 0xa8, 0x7c, /// 0x50e0 + 0x03, 0x28, 0x03, 0xd3, 0x00, 0x20, 0x02, 0xe0, + 0x00, 0x20, 0xdf, 0xe5, 0x40, 0x1c, 0xa8, 0x74, /// 0x50f0 + 0xff, 0xf7, 0x9a, 0xfe, 0xff, 0xf7, 0x7e, 0xfe, + 0xf6, 0xe7, 0x90, 0x49, 0x10, 0xb5, 0x01, 0x20, /// 0x5100 + 0x20, 0x39, 0x48, 0x73, 0x92, 0x49, 0x00, 0x20, + 0x08, 0x70, 0x92, 0x48, 0x69, 0x22, 0x02, 0x71, /// 0x5110 + 0x63, 0x24, 0x44, 0x71, 0x02, 0x72, 0x02, 0x23, + 0x43, 0x72, 0x02, 0x73, 0x44, 0x73, 0x02, 0x74, /// 0x5120 + 0x24, 0x22, 0x42, 0x74, 0xb4, 0x22, 0x0a, 0x70, + 0x84, 0x4a, 0xc8, 0x3a, 0x0a, 0x81, 0x07, 0x22, /// 0x5130 + 0x8a, 0x80, 0x87, 0x49, 0x20, 0x39, 0x0b, 0x72, + 0x0a, 0x79, 0x72, 0xb6, 0x1a, 0x43, 0x0a, 0x71, /// 0x5140 + 0x84, 0x49, 0x62, 0xb6, 0x20, 0x31, 0x0a, 0x7a, + 0xfb, 0x23, 0x1a, 0x40, 0x0a, 0x72, 0x01, 0x88, /// 0x5150 + 0x10, 0x22, 0x11, 0x43, 0x01, 0x80, 0x10, 0xbd, + 0x7f, 0x49, 0x03, 0x20, 0x08, 0x80, 0x70, 0x47, /// 0x5160 + 0x7d, 0x49, 0x5a, 0x20, 0x20, 0x39, 0x08, 0x70, + 0x7b, 0x49, 0x08, 0x80, 0x71, 0x48, 0x60, 0x38, /// 0x5170 + 0xc1, 0x7e, 0x49, 0x08, 0x49, 0x00, 0xc1, 0x76, + 0x70, 0x47, 0x77, 0x48, 0x10, 0xb5, 0x5a, 0x21, /// 0x5180 + 0x20, 0x38, 0x01, 0x70, 0x81, 0x8a, 0x42, 0x14, + 0x11, 0x43, 0x81, 0x82, 0x71, 0x49, 0x0a, 0x88, /// 0x5190 + 0x83, 0x14, 0x1a, 0x43, 0x0a, 0x80, 0x71, 0x49, + 0x01, 0x82, 0x71, 0x49, 0x01, 0x83, 0x09, 0x21, /// 0x51a0 + 0x01, 0x72, 0x70, 0x49, 0x81, 0x81, 0x70, 0x48, + 0x01, 0x21, 0x01, 0x80, 0xff, 0x22, 0x82, 0x80, /// 0x51b0 + 0x05, 0x22, 0x02, 0x81, 0x60, 0x4a, 0x82, 0x81, + 0x07, 0x23, 0x03, 0x80, 0x6a, 0x4b, 0x6b, 0x4c, /// 0x51c0 + 0x20, 0x33, 0x1c, 0x80, 0x5f, 0x4c, 0x40, 0x34, + 0xa4, 0x78, 0x0c, 0x43, 0x1c, 0x71, 0x02, 0x82, /// 0x51d0 + 0x00, 0x22, 0x02, 0x75, 0x66, 0x48, 0x01, 0x81, + 0x59, 0x48, 0xe0, 0x30, 0x00, 0x7e, 0xc2, 0x00, /// 0x51e0 + 0x63, 0x48, 0x40, 0x38, 0xd2, 0x1c, 0x02, 0x80, + 0x81, 0x80, 0x30, 0x21, 0x81, 0x81, 0x10, 0xbd, /// 0x51f0 + 0x10, 0xb5, 0xff, 0xf7, 0x01, 0xfb, 0xff, 0xf7, + 0x0f, 0xfc, 0xfe, 0xf7, 0x25, 0xff, 0x00, 0x20, /// 0x5200 + 0x10, 0xbd, 0x55, 0x49, 0x5a, 0x20, 0x20, 0x39, + 0x08, 0x70, 0x53, 0x48, 0xc8, 0x21, 0x81, 0x80, /// 0x5210 + 0x04, 0x21, 0x01, 0x73, 0x01, 0x21, 0x01, 0x80, + 0x46, 0x48, 0x60, 0x38, 0xc2, 0x7e, 0x0a, 0x43, /// 0x5220 + 0xc2, 0x76, 0x70, 0x47, 0xf8, 0xb5, 0x43, 0x4c, + 0x80, 0x3c, 0xe0, 0x8e, 0x81, 0x07, 0x04, 0xd5, /// 0x5230 + 0x02, 0x21, 0x88, 0x43, 0xe0, 0x86, 0xfb, 0xf7, + 0x9e, 0xfc, 0xe0, 0x8e, 0x08, 0x26, 0xc1, 0x07, /// 0x5240 + 0x00, 0x29, 0x1f, 0xd0, 0x40, 0x08, 0x3b, 0x4b, + 0x40, 0x00, 0xe0, 0x86, 0x60, 0x3b, 0x18, 0x7e, /// 0x5250 + 0x02, 0x28, 0x1e, 0xd1, 0xff, 0xf7, 0xd5, 0xff, + 0x01, 0x20, 0x3f, 0x4d, 0x18, 0x76, 0x20, 0x3d, /// 0x5260 + 0xa8, 0x8b, 0x30, 0x43, 0xa8, 0x83, 0x64, 0x20, + 0xfb, 0xf7, 0xde, 0xfb, 0xa8, 0x8b, 0x11, 0x21, /// 0x5270 + 0x08, 0x43, 0xa8, 0x83, 0xa8, 0x8b, 0x69, 0x15, + 0x08, 0x43, 0xa8, 0x83, 0x3d, 0x48, 0xfa, 0xf7, /// 0x5280 + 0x06, 0xff, 0x06, 0xe0, 0x41, 0x07, 0x04, 0xd5, + 0x04, 0x21, 0x88, 0x43, 0xe0, 0x86, 0xff, 0xf7, /// 0x5290 + 0xce, 0xfa, 0x28, 0x49, 0x20, 0x31, 0xc8, 0x7c, + 0x00, 0x28, 0x02, 0xd0, 0x40, 0x1e, 0xc8, 0x74, /// 0x52a0 + 0x25, 0xe0, 0xe0, 0x8e, 0x00, 0x07, 0x22, 0xd5, + 0x20, 0x7e, 0xfd, 0xf7, 0x1f, 0xf8, 0x05, 0x46, /// 0x52b0 + 0x0a, 0x28, 0x19, 0xd2, 0x1f, 0x48, 0x69, 0x1c, + 0x68, 0x38, 0x07, 0x46, 0xfb, 0xf7, 0x18, 0xfe, /// 0x52c0 + 0x1c, 0x49, 0xc0, 0x39, 0x49, 0x19, 0x40, 0x31, + 0x48, 0x76, 0xa8, 0x1c, 0x82, 0xb2, 0x1e, 0x48, /// 0x52d0 + 0x39, 0x46, 0x2c, 0x30, 0x07, 0x46, 0x00, 0xf0, + 0x90, 0xf9, 0x16, 0x20, 0x45, 0x43, 0x2e, 0x35, /// 0x52e0 + 0xa9, 0xb2, 0x38, 0x46, 0x00, 0xf0, 0x71, 0xf9, + 0xe0, 0x8e, 0xb0, 0x43, 0xe0, 0x86, 0xe0, 0x8e, /// 0x52f0 + 0x41, 0x06, 0x05, 0xd5, 0x40, 0x21, 0x88, 0x43, + 0xe0, 0x86, 0xff, 0x20, 0x95, 0x30, 0x20, 0x85, /// 0x5300 + 0x00, 0x20, 0xd3, 0xe4, 0xf8, 0xb5, 0x10, 0x48, + 0x01, 0x7b, 0x88, 0x07, 0x05, 0xd4, 0x0e, 0x48, /// 0x5310 + 0x02, 0x22, 0x11, 0x43, 0x01, 0x73, 0xfe, 0xf7, + 0x61, 0xfc, 0x06, 0x4f, 0x08, 0x4c, 0x60, 0x3f, /// 0x5320 + 0x38, 0x7e, 0x3e, 0x46, 0xc1, 0x07, 0x00, 0x25, + 0x20, 0x3e, 0x00, 0x29, 0x26, 0xd0, 0x06, 0x49, /// 0x5330 + 0x09, 0x7a, 0x21, 0xe0, 0xc0, 0x00, 0x00, 0x20, + 0xff, 0xff, 0x00, 0x00, 0x90, 0x03, 0x00, 0x20, /// 0x5340 + 0x30, 0x01, 0x00, 0x20, 0x20, 0x67, 0x00, 0x00, + 0x70, 0x04, 0x00, 0x20, 0x5a, 0x0a, 0x00, 0x00, /// 0x5350 + 0x20, 0x60, 0x00, 0x40, 0x00, 0x44, 0x00, 0x40, + 0x20, 0x30, 0x00, 0x40, 0xff, 0x07, 0x00, 0x00, /// 0x5360 + 0x7f, 0x3f, 0x00, 0x00, 0x05, 0x1d, 0x00, 0x00, + 0x00, 0x38, 0x00, 0x40, 0x08, 0x80, 0x00, 0x00, /// 0x5370 + 0x40, 0x34, 0x00, 0x40, 0xf1, 0x51, 0x00, 0x00, + 0x00, 0x29, 0x25, 0xd1, 0x00, 0x07, 0x23, 0xd4, /// 0x5380 + 0xa0, 0x78, 0x00, 0x28, 0x02, 0xd0, 0x40, 0x1e, + 0xa0, 0x70, 0x1e, 0xe0, 0x49, 0x48, 0x01, 0x78, /// 0x5390 + 0x09, 0x07, 0x19, 0xd5, 0x01, 0x78, 0x08, 0x22, + 0x11, 0x43, 0x01, 0x70, 0xe0, 0x78, 0x40, 0x1c, /// 0x53a0 + 0xc0, 0xb2, 0xe0, 0x70, 0x0a, 0x28, 0x10, 0xd3, + 0xe5, 0x70, 0xb0, 0x8e, 0x11, 0x03, 0x08, 0x43, /// 0x53b0 + 0xb0, 0x86, 0x40, 0x20, 0xfb, 0xf7, 0xd0, 0xfb, + 0x3f, 0x48, 0x40, 0x22, 0xc1, 0x6a, 0x11, 0x43, /// 0x53c0 + 0xc1, 0x62, 0xff, 0xf7, 0x45, 0xfa, 0x00, 0xe0, + 0xe5, 0x70, 0xf8, 0x7e, 0xc1, 0x07, 0x07, 0xd0, /// 0x53d0 + 0x81, 0x07, 0x05, 0xd5, 0x39, 0x4a, 0x03, 0x21, + 0x11, 0x80, 0xfd, 0x21, 0x08, 0x40, 0xf8, 0x76, /// 0x53e0 + 0x37, 0x48, 0x01, 0x7a, 0x0c, 0x29, 0x07, 0xd0, + 0x45, 0x76, 0xe5, 0x80, 0x65, 0x71, 0x35, 0x48, /// 0x53f0 + 0x40, 0x7b, 0x00, 0x28, 0x3d, 0xd0, 0x40, 0xe0, + 0x01, 0x7b, 0x09, 0x07, 0x03, 0xd5, 0x41, 0x7e, /// 0x5400 + 0x49, 0x1c, 0x41, 0x76, 0x00, 0xe0, 0x45, 0x76, + 0xe0, 0x88, 0x4b, 0x21, 0x40, 0x1c, 0x80, 0xb2, /// 0x5410 + 0xc9, 0x01, 0xe0, 0x80, 0x88, 0x42, 0x17, 0xd2, + 0x19, 0x21, 0x89, 0x01, 0xfc, 0xf7, 0xd4, 0xfa, /// 0x5420 + 0xc0, 0xb2, 0x05, 0x28, 0x00, 0xd9, 0x00, 0x20, + 0x61, 0x79, 0x81, 0x42, 0xdf, 0xd0, 0x26, 0x49, /// 0x5430 + 0x60, 0x71, 0x88, 0x8a, 0x40, 0x05, 0x40, 0x0f, + 0x40, 0x1c, 0x04, 0x28, 0x00, 0xd9, 0x00, 0x20, /// 0x5440 + 0x00, 0x02, 0x00, 0x1d, 0x88, 0x82, 0xd2, 0xe7, + 0x1b, 0x48, 0xff, 0x22, 0x41, 0x6b, 0x3d, 0x32, /// 0x5450 + 0x91, 0x43, 0x41, 0x63, 0xb1, 0x8e, 0xff, 0x22, + 0x01, 0x32, 0x11, 0x43, 0xb1, 0x86, 0xc1, 0x6a, /// 0x5460 + 0x01, 0x22, 0x11, 0x43, 0xc1, 0x62, 0x10, 0x46, + 0xfb, 0xf7, 0x76, 0xfb, 0xff, 0xf7, 0xf0, 0xf9, /// 0x5470 + 0xbd, 0xe7, 0xff, 0xf7, 0x42, 0xfe, 0xff, 0xf7, + 0x6d, 0xfd, 0x14, 0x48, 0x00, 0x7f, 0x41, 0x07, /// 0x5480 + 0x13, 0x48, 0x00, 0x29, 0x0d, 0xdb, 0xc1, 0x7f, + 0x49, 0x1c, 0xc9, 0xb2, 0xc1, 0x77, 0x64, 0x29, /// 0x5490 + 0x08, 0xd3, 0xc5, 0x77, 0x08, 0x48, 0x02, 0x21, + 0x05, 0x63, 0xf0, 0x8e, 0x08, 0x43, 0xf0, 0x86, /// 0x54a0 + 0x00, 0xe0, 0xc5, 0x77, 0xff, 0xf7, 0x72, 0xf9, + 0xff, 0xf7, 0x4b, 0xfb, 0x00, 0xf0, 0xc6, 0xf9, /// 0x54b0 + 0x00, 0x20, 0x03, 0xe4, 0x00, 0x3c, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x20, 0x20, 0x30, 0x00, 0x40, /// 0x54c0 + 0x70, 0x04, 0x00, 0x20, 0x70, 0x03, 0x00, 0x20, + 0x60, 0x40, 0x00, 0x40, 0x20, 0x6c, 0x00, 0x40, /// 0x54d0 + 0xf0, 0x01, 0x00, 0x20, 0xc2, 0x48, 0x01, 0x8b, + 0x89, 0x06, 0x02, 0xd5, 0xc1, 0x49, 0x01, 0x22, /// 0x54e0 + 0x0a, 0x72, 0x30, 0x21, 0x01, 0x83, 0x70, 0x47, + 0x70, 0xb5, 0xbf, 0x48, 0xbf, 0x4d, 0x41, 0x8c, /// 0x54f0 + 0x28, 0x46, 0xfc, 0xf7, 0x69, 0xfa, 0xba, 0x4a, + 0x81, 0x21, 0x11, 0x80, 0x01, 0x24, 0x14, 0x80, /// 0x5500 + 0x35, 0x21, 0x11, 0x80, 0x07, 0x21, 0x91, 0x80, + 0x14, 0x81, 0x80, 0x21, 0x91, 0x81, 0xb8, 0x4a, /// 0x5510 + 0xf9, 0x21, 0x11, 0x80, 0x03, 0x21, 0x91, 0x80, + 0xff, 0x21, 0x11, 0x80, 0xc1, 0x1c, 0x28, 0x46, /// 0x5520 + 0xfc, 0xf7, 0x52, 0xfa, 0xb2, 0x49, 0x40, 0x31, + 0x08, 0x80, 0xb1, 0x48, 0x20, 0x30, 0x03, 0x8b, /// 0x5530 + 0xac, 0x4a, 0x20, 0x32, 0x13, 0x81, 0x03, 0x89, + 0x53, 0x81, 0x03, 0x8a, 0x93, 0x81, 0x03, 0x88, /// 0x5540 + 0xd3, 0x81, 0x03, 0x8b, 0x0a, 0x88, 0x52, 0x1e, + 0x93, 0x42, 0x02, 0xdd, 0x0a, 0x88, 0x52, 0x1e, /// 0x5550 + 0x02, 0x83, 0x03, 0x88, 0x0a, 0x88, 0x52, 0x1e, + 0x93, 0x42, 0x02, 0xdd, 0x0a, 0x88, 0x52, 0x1e, /// 0x5560 + 0x02, 0x80, 0x03, 0x8a, 0x0a, 0x88, 0x52, 0x1e, + 0x93, 0x42, 0x02, 0xdd, 0x0a, 0x88, 0x52, 0x1e, /// 0x5570 + 0x02, 0x82, 0x03, 0x89, 0x0a, 0x88, 0x52, 0x1e, + 0x93, 0x42, 0x02, 0xdd, 0x0a, 0x88, 0x52, 0x1e, /// 0x5580 + 0x02, 0x81, 0x30, 0x20, 0x88, 0x80, 0x0c, 0x81, + 0x70, 0xbd, 0x96, 0x48, 0x98, 0x49, 0x20, 0x30, /// 0x5590 + 0x02, 0x89, 0x20, 0x31, 0x0a, 0x83, 0x42, 0x89, + 0x0a, 0x81, 0x82, 0x89, 0x0a, 0x82, 0xc0, 0x89, /// 0x55a0 + 0x08, 0x80, 0x8f, 0x48, 0x01, 0x21, 0x01, 0x80, + 0x03, 0x21, 0x01, 0x80, 0x90, 0x49, 0xfb, 0x20, /// 0x55b0 + 0x08, 0x80, 0x70, 0x47, 0x8b, 0x4b, 0x00, 0x22, + 0x1a, 0x72, 0x89, 0x4a, 0x10, 0x82, 0x49, 0x1e, /// 0x55c0 + 0x11, 0x75, 0x18, 0x7a, 0x00, 0x28, 0xfc, 0xd0, + 0x70, 0x47, 0x70, 0xb5, 0x0c, 0x46, 0x05, 0x46, /// 0x55d0 + 0xff, 0xf7, 0x8a, 0xff, 0x08, 0xe0, 0x28, 0x88, + 0x10, 0x2c, 0x0a, 0xd9, 0x10, 0x21, 0xad, 0x1c, /// 0x55e0 + 0xff, 0xf7, 0xe8, 0xff, 0x10, 0x3c, 0xa4, 0xb2, + 0x00, 0x2c, 0xf4, 0xd1, 0xff, 0xf7, 0xcd, 0xff, /// 0x55f0 + 0x70, 0xbd, 0x21, 0x46, 0xff, 0xf7, 0xde, 0xff, + 0xf8, 0xe7, 0xf0, 0xb5, 0x00, 0x23, 0x02, 0x27, /// 0x5600 + 0x1c, 0x46, 0x9e, 0x46, 0x1d, 0x46, 0x8b, 0x54, + 0x05, 0xe0, 0x0e, 0x5d, 0xed, 0xb2, 0x75, 0x40, /// 0x5610 + 0x64, 0x1c, 0x8d, 0x54, 0xe4, 0xb2, 0x94, 0x42, + 0xf7, 0xd3, 0x52, 0x1c, 0x92, 0xb2, 0x94, 0x46, /// 0x5620 + 0x00, 0x22, 0x70, 0x4d, 0x14, 0x46, 0x20, 0x3d, + 0x56, 0x00, 0x76, 0x19, 0x52, 0x1c, 0xd2, 0xb2, /// 0x5630 + 0xb4, 0x85, 0x1c, 0x2a, 0xf8, 0xd3, 0x73, 0xe0, + 0x00, 0x2b, 0x01, 0xd0, 0x00, 0x23, 0x05, 0xe0, /// 0x5640 + 0x02, 0x78, 0x03, 0x23, 0xbb, 0x40, 0x1a, 0x43, + 0x02, 0x70, 0x01, 0x23, 0xbf, 0x1c, 0xfa, 0xb2, /// 0x5650 + 0x08, 0x2a, 0x01, 0xd1, 0x00, 0x22, 0x40, 0x1c, + 0x00, 0x24, 0x0d, 0x78, 0xe5, 0x40, 0xef, 0x07, /// 0x5660 + 0xff, 0x0f, 0x12, 0xd0, 0x00, 0x2b, 0x06, 0xd0, + 0x03, 0x78, 0x02, 0x25, 0x95, 0x40, 0x2b, 0x43, /// 0x5670 + 0x03, 0x70, 0x01, 0x23, 0x04, 0xe0, 0x05, 0x78, + 0x01, 0x26, 0x96, 0x40, 0x35, 0x43, 0x05, 0x70, /// 0x5680 + 0x75, 0x46, 0xed, 0x19, 0xed, 0xb2, 0xae, 0x46, + 0x09, 0xe0, 0x00, 0x2b, 0x01, 0xd0, 0x00, 0x23, /// 0x5690 + 0x05, 0xe0, 0x03, 0x78, 0x03, 0x25, 0x95, 0x40, + 0x2b, 0x43, 0x03, 0x70, 0x01, 0x23, 0x92, 0x1c, /// 0x56a0 + 0xd2, 0xb2, 0x08, 0x2a, 0x01, 0xd1, 0x00, 0x22, + 0x40, 0x1c, 0x64, 0x1c, 0xe4, 0xb2, 0x08, 0x2c, /// 0x56b0 + 0xd3, 0xd3, 0x74, 0x46, 0xe4, 0x07, 0x0d, 0xd0, + 0x00, 0x2b, 0x05, 0xd0, 0x03, 0x78, 0x02, 0x24, /// 0x56c0 + 0x94, 0x40, 0x23, 0x43, 0x03, 0x70, 0x0e, 0xe0, + 0x04, 0x78, 0x01, 0x25, 0x95, 0x40, 0x2c, 0x43, /// 0x56d0 + 0x04, 0x70, 0x09, 0xe0, 0x00, 0x2b, 0x01, 0xd0, + 0x00, 0x23, 0x05, 0xe0, 0x04, 0x78, 0x03, 0x23, /// 0x56e0 + 0x93, 0x40, 0x1c, 0x43, 0x04, 0x70, 0x01, 0x23, + 0x92, 0x1c, 0xd2, 0xb2, 0x08, 0x2a, 0x01, 0xd1, /// 0x56f0 + 0x00, 0x22, 0x40, 0x1c, 0x04, 0x78, 0x00, 0x2b, + 0x05, 0xd0, 0x02, 0x23, 0x93, 0x40, 0x1c, 0x43, /// 0x5700 + 0x04, 0x70, 0x01, 0x23, 0x03, 0xe0, 0x01, 0x25, + 0x95, 0x40, 0x2c, 0x43, 0x04, 0x70, 0x92, 0x1c, /// 0x5710 + 0xd7, 0xb2, 0x08, 0x2f, 0x01, 0xd1, 0x00, 0x27, + 0x40, 0x1c, 0x00, 0x22, 0x96, 0x46, 0x49, 0x1c, /// 0x5720 + 0x62, 0x46, 0x54, 0x1e, 0xa4, 0xb2, 0xa4, 0x46, + 0x00, 0x2a, 0x85, 0xd1, 0x00, 0x2b, 0x04, 0xd1, /// 0x5730 + 0x02, 0x78, 0x01, 0x21, 0xb9, 0x40, 0x0a, 0x43, + 0x02, 0x70, 0xf0, 0xbd, 0xf0, 0xb5, 0x00, 0x24, /// 0x5740 + 0x23, 0x46, 0x25, 0x46, 0x26, 0x46, 0x8c, 0x54, + 0x05, 0xe0, 0x4f, 0x5d, 0xf6, 0xb2, 0x7e, 0x40, /// 0x5750 + 0x6d, 0x1c, 0x8e, 0x54, 0xed, 0xb2, 0x95, 0x42, + 0xf7, 0xd3, 0x52, 0x1c, 0x92, 0xb2, 0x94, 0x46, /// 0x5760 + 0x00, 0x22, 0x20, 0x4e, 0x15, 0x46, 0x20, 0x3e, + 0x57, 0x00, 0xbf, 0x19, 0x52, 0x1c, 0xd2, 0xb2, /// 0x5770 + 0xbd, 0x85, 0x1c, 0x2a, 0xf8, 0xd3, 0x25, 0xe0, + 0x00, 0x22, 0x0d, 0x78, 0xd5, 0x40, 0xed, 0x07, /// 0x5780 + 0xed, 0x0f, 0x0a, 0xd0, 0x00, 0x2c, 0x02, 0xd0, + 0x04, 0x78, 0x02, 0x25, 0x0b, 0xe0, 0x05, 0x78, /// 0x5790 + 0x01, 0x26, 0x9e, 0x40, 0x35, 0x43, 0x05, 0x70, + 0x09, 0xe0, 0x00, 0x2c, 0x01, 0xd0, 0x00, 0x24, /// 0x57a0 + 0x05, 0xe0, 0x04, 0x78, 0x03, 0x25, 0x9d, 0x40, + 0x2c, 0x43, 0x04, 0x70, 0x01, 0x24, 0x9b, 0x1c, /// 0x57b0 + 0xdb, 0xb2, 0x08, 0x2b, 0x01, 0xd1, 0x00, 0x23, + 0x40, 0x1c, 0x52, 0x1c, 0xd2, 0xb2, 0x08, 0x2a, /// 0x57c0 + 0xdb, 0xd3, 0x49, 0x1c, 0x62, 0x46, 0x55, 0x1e, + 0xad, 0xb2, 0xac, 0x46, 0x00, 0x2a, 0xd3, 0xd1, /// 0x57d0 + 0x00, 0x2c, 0x04, 0xd1, 0x02, 0x78, 0x01, 0x21, + 0x99, 0x40, 0x0a, 0x43, 0x02, 0x70, 0xf0, 0xbd, /// 0x57e0 + 0x00, 0x38, 0x00, 0x40, 0x90, 0x04, 0x00, 0x20, + 0x40, 0x00, 0x00, 0x20, 0x60, 0xea, 0x00, 0x00, /// 0x57f0 + 0x00, 0x34, 0x00, 0x40, 0x65, 0x49, 0x0d, 0x20, + 0x08, 0x76, 0x65, 0x48, 0x01, 0x21, 0x01, 0x80, /// 0x5800 + 0x02, 0x15, 0x82, 0x80, 0x2b, 0x22, 0x02, 0x80, + 0x01, 0x81, 0x62, 0x49, 0x60, 0x4a, 0x0b, 0x8a, /// 0x5810 + 0x20, 0x32, 0x13, 0x80, 0x49, 0x8a, 0x91, 0x80, + 0x0f, 0x21, 0x01, 0x83, 0x08, 0x21, 0x81, 0x82, /// 0x5820 + 0x70, 0x47, 0x00, 0x28, 0x09, 0xd0, 0x00, 0x29, + 0x07, 0xd0, 0x81, 0x42, 0x01, 0xd9, 0x41, 0x1e, /// 0x5830 + 0x89, 0xb2, 0x57, 0x4a, 0x20, 0x32, 0x10, 0x80, + 0x91, 0x80, 0x70, 0x47, 0xf8, 0xb5, 0x56, 0x4b, /// 0x5840 + 0x54, 0x4c, 0x18, 0x7b, 0x61, 0x8a, 0xc2, 0x07, + 0x00, 0x2a, 0x05, 0xd0, 0x42, 0x07, 0x7d, 0xd5, /// 0x5850 + 0xfb, 0x22, 0x10, 0x40, 0x18, 0x73, 0x94, 0xe0, + 0x09, 0x22, 0x9a, 0x56, 0x00, 0x2a, 0x78, 0xd0, /// 0x5860 + 0x4d, 0x4d, 0x09, 0x20, 0x28, 0x56, 0x40, 0x42, + 0x00, 0x2a, 0x01, 0xdd, 0x15, 0x46, 0x00, 0xe0, /// 0x5870 + 0x05, 0x46, 0x4a, 0x4e, 0x00, 0x96, 0xb6, 0x7d, + 0xb5, 0x42, 0x01, 0xdd, 0x30, 0x46, 0x02, 0xe0, /// 0x5880 + 0x00, 0x2a, 0x00, 0xdd, 0x10, 0x46, 0x80, 0xb2, + 0x86, 0x46, 0x44, 0x48, 0x41, 0x4d, 0x20, 0x30, /// 0x5890 + 0xc6, 0x88, 0x40, 0x79, 0x80, 0x3d, 0x84, 0x46, + 0x3f, 0x48, 0x6f, 0x8c, 0x43, 0x79, 0x00, 0x2a, /// 0x58a0 + 0x2d, 0xdd, 0xff, 0x2b, 0x0c, 0xd2, 0x61, 0x46, + 0x59, 0x18, 0xff, 0x29, 0x00, 0xd3, 0xff, 0x21, /// 0x58b0 + 0x41, 0x71, 0x61, 0x46, 0x51, 0x1a, 0x00, 0x29, + 0x00, 0xdc, 0x00, 0x21, 0x41, 0x72, 0x2f, 0xe0, /// 0x58c0 + 0x36, 0x4b, 0x70, 0x46, 0x20, 0x3b, 0x1b, 0x8f, + 0x08, 0x1a, 0x98, 0x42, 0x07, 0xdd, 0x60, 0x82, /// 0x58d0 + 0x70, 0x46, 0x31, 0x49, 0x10, 0x1a, 0x00, 0x28, + 0x30, 0xdc, 0x00, 0x20, 0x2e, 0xe0, 0x99, 0x42, /// 0x58e0 + 0x0b, 0xd1, 0xe9, 0x8c, 0xb8, 0x19, 0x88, 0x42, + 0x00, 0xd3, 0x08, 0x46, 0x68, 0x84, 0x2a, 0x49, /// 0x58f0 + 0x90, 0x1b, 0x00, 0x28, 0x3c, 0xdd, 0x48, 0x72, + 0x12, 0xe0, 0x63, 0x82, 0x3b, 0xe0, 0xa8, 0x8c, /// 0x5900 + 0x87, 0x42, 0x0f, 0xd9, 0xb9, 0x1b, 0x81, 0x42, + 0x00, 0xdd, 0x08, 0x46, 0x80, 0xb2, 0x22, 0x4f, /// 0x5910 + 0x68, 0x84, 0x91, 0x19, 0x00, 0xd4, 0x00, 0x21, + 0x79, 0x72, 0x19, 0x46, 0xfe, 0xf7, 0xf7, 0xff, /// 0x5920 + 0x02, 0x20, 0x0d, 0xe0, 0x1d, 0x4e, 0x70, 0x46, + 0x20, 0x3e, 0x76, 0x8f, 0x08, 0x18, 0xb0, 0x42, /// 0x5930 + 0x10, 0xd2, 0x60, 0x82, 0x18, 0x49, 0x70, 0x46, + 0x10, 0x18, 0xce, 0xd5, 0x48, 0x72, 0x01, 0x20, /// 0x5940 + 0x81, 0x07, 0x1b, 0xd5, 0x14, 0x48, 0x41, 0x79, + 0x68, 0x8c, 0x00, 0xe0, 0x01, 0xe0, 0xfe, 0xf7, /// 0x5950 + 0xde, 0xff, 0xf8, 0xbd, 0xb1, 0x42, 0x0d, 0xd1, + 0x60, 0x46, 0x1b, 0x1a, 0x00, 0x98, 0x0e, 0x49, /// 0x5960 + 0xc0, 0x7f, 0x83, 0x42, 0x00, 0xdd, 0x18, 0x46, + 0x48, 0x71, 0x60, 0x46, 0x10, 0x18, 0xc2, 0xd4, /// 0x5970 + 0x00, 0x20, 0xc0, 0xe7, 0x66, 0x82, 0x00, 0x20, + 0x07, 0x49, 0xdf, 0xe7, 0xc0, 0x07, 0xe8, 0xd0, /// 0x5980 + 0x61, 0x8a, 0x20, 0x8a, 0xff, 0xf7, 0x4d, 0xff, + 0xf8, 0xbd, 0x00, 0x00, 0x00, 0x6c, 0x00, 0x40, /// 0x5990 + 0x00, 0x50, 0x00, 0x40, 0xc0, 0x00, 0x00, 0x20, + 0x70, 0x04, 0x00, 0x20, 0x50, 0x01, 0x00, 0x20, /// 0x59a0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x59b0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x59c0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x59d0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x59e0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x59f0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a00 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a10 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a20 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a30 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a40 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a50 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a60 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a70 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a80 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5a90 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5aa0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ab0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ac0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ad0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ae0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5af0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b00 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b10 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b20 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b30 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b40 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b50 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b60 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b70 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b80 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5b90 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ba0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5bb0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5bc0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5bd0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5be0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5bf0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c00 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c10 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c20 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c30 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c40 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c50 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c60 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c70 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c80 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5c90 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ca0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5cb0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5cc0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5cd0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ce0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5cf0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d00 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d10 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d20 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d30 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d40 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d50 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d60 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d70 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d80 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5d90 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5da0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5db0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5dc0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5dd0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5de0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5df0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e00 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e10 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e20 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e30 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e40 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e50 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e60 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e70 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e80 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5e90 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ea0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5eb0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ec0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ed0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ee0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ef0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f00 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f10 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f20 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f30 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f40 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f50 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f60 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f70 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f80 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5f90 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5fa0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5fb0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5fc0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5fd0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5fe0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /// 0x5ff0 + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; \ No newline at end of file diff --git a/drivers/power/supply/ti/Kconfig b/drivers/power/supply/ti/Kconfig new file mode 100644 index 000000000000..775441e0e570 --- /dev/null +++ b/drivers/power/supply/ti/Kconfig @@ -0,0 +1,24 @@ +menu "TI Technologies, Inc. Charger support" + +config FUEL_GAUGE_BQ27Z561 + tristate "TI bq27z561 battery gauge driver" + help + Say Y to enable support for TI bq27z561 fuel gauge driver + +config BQ2597X_CHARGE_PUMP + tristate "BQ2597X power supply framework based driver" + depends on I2C + help + Say Y to include support for BQ2597X Charge Pump driver based on + power supply framework. + BQ2597X is a div2 charge pump capable of delivering 8A charge current + with very high efficiency. + +config CHARGER_LN8000 + tristate "LionSemi LN8000 Battery Charger" + depends on I2C + select REGMAP_I2C + help + Say Y to enable support for the LN8000 charger + +endmenu diff --git a/drivers/power/supply/ti/Makefile b/drivers/power/supply/ti/Makefile new file mode 100644 index 000000000000..04ee88c8ba3e --- /dev/null +++ b/drivers/power/supply/ti/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_FUEL_GAUGE_BQ27Z561) += bq27z561_fg.o +obj-$(CONFIG_BQ2597X_CHARGE_PUMP) += bq2597x_charger.o pd_policy_manager.o cp_qc30.o +obj-$(CONFIG_CHARGER_LN8000) += ln8000_charger.o pd_policy_manager.o cp_qc30.o diff --git a/drivers/power/supply/ti/bq25970_reg.h b/drivers/power/supply/ti/bq25970_reg.h new file mode 100644 index 000000000000..71cedf04b552 --- /dev/null +++ b/drivers/power/supply/ti/bq25970_reg.h @@ -0,0 +1,791 @@ + +#ifndef __BQ2597X_HEADER__ +#define __BQ2597X_HEADER__ + +/* Register 00h */ +#define BQ2597X_REG_00 0x00 +#define BQ2597X_BAT_OVP_DIS_MASK 0x80 +#define BQ2597X_BAT_OVP_DIS_SHIFT 7 +#define BQ2597X_BAT_OVP_ENABLE 0 +#define BQ2597X_BAT_OVP_DISABLE 1 + +#define BQ2597X_BAT_OVP_MASK 0x3F +#define BQ2597X_BAT_OVP_SHIFT 0 +#define BQ2597X_BAT_OVP_BASE 3475 +#define BQ2597X_BAT_OVP_LSB 25 + +/* Register 01h */ +#define BQ2597X_REG_01 0x01 +#define BQ2597X_BAT_OVP_ALM_DIS_MASK 0x80 +#define BQ2597X_BAT_OVP_ALM_DIS_SHIFT 7 +#define BQ2597X_BAT_OVP_ALM_ENABLE 0 +#define BQ2597X_BAT_OVP_ALM_DISABLE 1 + +#define BQ2597X_BAT_OVP_ALM_MASK 0x3F +#define BQ2597X_BAT_OVP_ALM_SHIFT 0 +#define BQ2597X_BAT_OVP_ALM_BASE 3500 +#define BQ2597X_BAT_OVP_ALM_LSB 25 + +/* Register 02h */ +#define BQ2597X_REG_02 0x02 +#define BQ2597X_BAT_OCP_DIS_MASK 0x80 +#define BQ2597X_BAT_OCP_DIS_SHIFT 7 +#define BQ2597X_BAT_OCP_ENABLE 0 +#define BQ2597X_BAT_OCP_DISABLE 1 + +#define BQ2597X_BAT_OCP_MASK 0x7F +#define BQ2597X_BAT_OCP_SHIFT 0 +#define BQ2597X_BAT_OCP_BASE 2000 +#define BQ2597X_BAT_OCP_LSB 100 + +/* Register 03h */ +#define BQ2597X_REG_03 0x03 +#define BQ2597X_BAT_OCP_ALM_DIS_MASK 0x80 +#define BQ2597X_BAT_OCP_ALM_DIS_SHIFT 7 +#define BQ2597X_BAT_OCP_ALM_ENABLE 0 +#define BQ2597X_BAT_OCP_ALM_DISABLE 1 + +#define BQ2597X_BAT_OCP_ALM_MASK 0x7F +#define BQ2597X_BAT_OCP_ALM_SHIFT 0 +#define BQ2597X_BAT_OCP_ALM_BASE 2000 +#define BQ2597X_BAT_OCP_ALM_LSB 100 + +/* Register 04h */ +#define BQ2597X_REG_04 0x04 +#define BQ2597X_BAT_UCP_ALM_DIS_MASK 0x80 +#define BQ2597X_BAT_UCP_ALM_DIS_SHIFT 7 +#define BQ2597X_BAT_UCP_ALM_ENABLE 0 +#define BQ2597X_BAT_UCP_ALM_DISABLE 1 + +#define BQ2597X_BAT_UCP_ALM_MASK 0x7F +#define BQ2597X_BAT_UCP_ALM_SHIFT 0 +#define BQ2597X_BAT_UCP_ALM_BASE 0 +#define BQ2597X_BAT_UCP_ALM_LSB 50 + +/* Register 05h */ +#define BQ2597X_REG_05 0x05 +#define BQ2597X_AC_OVP_STAT_MASK 0x80 +#define BQ2597X_AC_OVP_STAT_SHIFT 7 + +#define BQ2597X_AC_OVP_FLAG_MASK 0x40 +#define BQ2597X_AC_OVP_FLAG_SHIFT 6 + +#define BQ2597X_AC_OVP_MASK_MASK 0x20 +#define BQ2597X_AC_OVP_MASK_SHIFT 5 + +#define BQ2597X_VDROP_THRESHOLD_SET_MASK 0x10 +#define BQ2597X_VDROP_THRESHOLD_SET_SHIFT 4 +#define BQ2597X_VDROP_THRESHOLD_300MV 0 +#define BQ2597X_VDROP_THRESHOLD_400MV 1 + +#define BQ2597X_VDROP_DEGLITCH_SET_MASK 0x08 +#define BQ2597X_VDROP_DEGLITCH_SET_SHIFT 3 +#define BQ2597X_VDROP_DEGLITCH_8US 0 +#define BQ2597X_VDROP_DEGLITCH_5MS 1 + +#define BQ2597X_AC_OVP_MASK 0x07 +#define BQ2597X_AC_OVP_SHIFT 0 +#define BQ2597X_AC_OVP_BASE 11 +#define BQ2597X_AC_OVP_LSB 1 +#define BQ2597X_AC_OVP_6P5V 65 + +/* Register 06h */ +#define BQ2597X_REG_06 0x06 +#define BQ2597X_VBUS_PD_EN_MASK 0x80 +#define BQ2597X_VBUS_PD_EN_SHIFT 7 +#define BQ2597X_VBUS_PD_ENABLE 1 +#define BQ2597X_VBUS_PD_DISABLE 0 + +#define BQ2597X_BUS_OVP_MASK 0x7F +#define BQ2597X_BUS_OVP_SHIFT 0 +#define BQ2597X_BUS_OVP_BASE 5950 +#define BQ2597X_BUS_OVP_LSB 50 + +/* Register 07h */ +#define BQ2597X_REG_07 0x07 +#define BQ2597X_BUS_OVP_ALM_DIS_MASK 0x80 +#define BQ2597X_BUS_OVP_ALM_DIS_SHIFT 7 +#define BQ2597X_BUS_OVP_ALM_ENABLE 0 +#define BQ2597X_BUS_OVP_ALM_DISABLE 1 + +#define BQ2597X_BUS_OVP_ALM_MASK 0x7F +#define BQ2597X_BUS_OVP_ALM_SHIFT 0 +#define BQ2597X_BUS_OVP_ALM_BASE 6000 +#define BQ2597X_BUS_OVP_ALM_LSB 50 + +/* Register 08h */ +#define BQ2597X_REG_08 0x08 +#define BQ2597X_BUS_OCP_DIS_MASK 0x80 +#define BQ2597X_BUS_OCP_DIS_SHIFT 7 +#define BQ2597X_BUS_OCP_ENABLE 0 +#define BQ2597X_BUS_OCP_DISABLE 1 + +#define BQ2597X_IBUS_UCP_RISE_FLAG_MASK 0x40 +#define BQ2597X_IBUS_UCP_RISE_FLAG_SHIFT 6 + +#define BQ2597X_IBUS_UCP_RISE_MASK_MASK 0x20 +#define BQ2597X_IBUS_UCP_RISE_MASK_SHIFT 5 +#define BQ2597X_IBUS_UCP_RISE_MASK_ENABLE 1 +#define BQ2597X_IBUS_UCP_RISE_MASK_DISABLE 0 + +#define BQ2597X_IBUS_UCP_FALL_FLAG_MASK 0x10 +#define BQ2597X_IBUS_UCP_FALL_FLAG_SHIFT 4 + +#define BQ2597X_BUS_OCP_MASK 0x0F +#define BQ2597X_BUS_OCP_SHIFT 0 +#define BQ2597X_BUS_OCP_BASE 1000 +#define BQ2597X_BUS_OCP_LSB 250 + +/* Register 09h */ +#define BQ2597X_REG_09 0x09 +#define BQ2597X_BUS_OCP_ALM_DIS_MASK 0x80 +#define BQ2597X_BUS_OCP_ALM_DIS_SHIFT 7 +#define BQ2597X_BUS_OCP_ALM_ENABLE 0 +#define BQ2597X_BUS_OCP_ALM_DISABLE 1 + +#define BQ2597X_BUS_OCP_ALM_MASK 0x7F +#define BQ2597X_BUS_OCP_ALM_SHIFT 0 +#define BQ2597X_BUS_OCP_ALM_BASE 0 +#define BQ2597X_BUS_OCP_ALM_LSB 50 + +/* Register 0Ah */ +#define BQ2597X_REG_0A 0x0A +#define BQ2597X_TSHUT_FLAG_MASK 0x80 +#define BQ2597X_TSHUT_FLAG_SHIFT 7 +#define VBUS_ERROR_LOW_MASK BIT(5) +#define VBUS_ERROR_HIGH_MASK BIT(4) + +#define BQ2597X_TSHUT_STAT_MASK 0x40 +#define BQ2597X_TSHUT_STAT_SHIFT 6 + +#define BQ2597X_VBUS_ERRORLO_STAT_MASK 0x20 +#define BQ2597X_VBUS_ERRORLO_STAT_SHIFT 5 + +#define BQ2597X_VBUS_ERRORHI_STAT_MASK 0x10 +#define BQ2597X_VBUS_ERRORHI_STAT_SHIFT 4 + +#define BQ2597X_SS_TIMEOUT_FLAG_MASK 0x08 +#define BQ2597X_SS_TIMEOUT_FLAG_SHIFT 3 + +#define BQ2597X_CONV_SWITCHING_STAT_MASK 0x04 +#define BQ2597X_CONV_SWITCHING_STAT_SHIFT 2 + +#define BQ2597X_CONV_OCP_FLAG_MASK 0x02 +#define BQ2597X_CONV_OCP_FLAG_SHIFT 1 + +#define BQ2597X_PIN_DIAG_FALL_FLAG_MASK 0x01 +#define BQ2597X_PIN_DIAG_FALL_FLAG_SHIFT 0 + +/* Register 0Bh */ +#define BQ2597X_REG_0B 0x0B +#define BQ2597X_REG_RST_MASK 0x80 +#define BQ2597X_REG_RST_SHIFT 7 +#define BQ2597X_REG_RST_ENABLE 1 +#define BQ2597X_REG_RST_DISABLE 0 + +#define BQ2597X_FSW_SET_MASK 0x70 +#define BQ2597X_FSW_SET_SHIFT 4 +#define BQ2597X_FSW_SET_187P5KHZ 0 +#define BQ2597X_FSW_SET_250KHZ 1 +#define BQ2597X_FSW_SET_300KHZ 2 +#define BQ2597X_FSW_SET_375KHZ 3 +#define BQ2597X_FSW_SET_500KHZ 4 +#define BQ2597X_FSW_SET_750KHZ 5 + +#define BQ2597X_WD_TIMEOUT_FLAG_MASK 0x08 +#define BQ2597X_WD_TIMEOUT_SHIFT 3 + +#define BQ2597X_WATCHDOG_DIS_MASK 0x04 +#define BQ2597X_WATCHDOG_DIS_SHIFT 2 +#define BQ2597X_WATCHDOG_ENABLE 0 +#define BQ2597X_WATCHDOG_DISABLE 1 + +#define BQ2597X_WATCHDOG_MASK 0x03 +#define BQ2597X_WATCHDOG_SHIFT 0 +#define BQ2597X_WATCHDOG_0P5S 0 +#define BQ2597X_WATCHDOG_1S 1 +#define BQ2597X_WATCHDOG_5S 2 +#define BQ2597X_WATCHDOG_30S 3 + +/* Register 0Ch */ +#define BQ2597X_REG_0C 0x0C +#define BQ2597X_CHG_EN_MASK 0x80 +#define BQ2597X_CHG_EN_SHIFT 7 +#define BQ2597X_CHG_ENABLE 1 +#define BQ2597X_CHG_DISABLE 0 + +#define BQ2597X_MS_MASK 0x60 +#define BQ2597X_MS_SHIFT 5 +#define BQ2597X_MS_STANDALONE 0 +#define BQ2597X_MS_SLAVE 1 +#define BQ2597X_MS_MASTER 2 + +#define BQ2597X_FREQ_SHIFT_MASK 0x18 +#define BQ2597X_FREQ_SHIFT_SHIFT 3 +#define BQ2597X_FREQ_SHIFT_NORMINAL 0 +#define BQ2597X_FREQ_SHIFT_POSITIVE10 1 +#define BQ2597X_FREQ_SHIFT_NEGATIVE10 2 +#define BQ2597X_FREQ_SHIFT_SPREAD_SPECTRUM 3 + +#define BQ2597X_TSBUS_DIS_MASK 0x04 +#define BQ2597X_TSBUS_DIS_SHIFT 2 +#define BQ2597X_TSBUS_ENABLE 0 +#define BQ2597X_TSBUS_DISABLE 1 + +#define BQ2597X_TSBAT_DIS_MASK 0x02 +#define BQ2597X_TSBAT_DIS_SHIFT 1 +#define BQ2597X_TSBAT_ENABLE 0 +#define BQ2597X_TSBAT_DISABLE 1 + +#define BQ2597X_TDIE_DIS_MASK 0x01 +#define BQ2597X_TDIE_DIS_SHIFT 0 +#define BQ2597X_TDIE_ENABLE 0 +#define BQ2597X_TDIE_DISABLE 1 + +/* Register 0Dh */ +#define BQ2597X_REG_0D 0x0D +#define BQ2597X_BAT_OVP_ALM_STAT_MASK 0x80 +#define BQ2597X_BAT_OVP_ALM_STAT_SHIFT 7 + +#define BQ2597X_BAT_OCP_ALM_STAT_MASK 0x40 +#define BQ2597X_BAT_OCP_ALM_STAT_SHIFT 6 + +#define BQ2597X_BUS_OVP_ALM_STAT_MASK 0x20 +#define BQ2597X_BUS_OVP_ALM_STAT_SHIFT 5 + +#define BQ2597X_BUS_OCP_ALM_STAT_MASK 0x10 +#define BQ2597X_BUS_OCP_ALM_STAT_SHIFT 4 + +#define BQ2597X_BAT_UCP_ALM_STAT_MASK 0x08 +#define BQ2597X_BAT_UCP_ALM_STAT_SHIFT 3 + +#define BQ2597X_ADAPTER_INSERT_STAT_MASK 0x04 +#define BQ2597X_ADAPTER_INSERT_STAT_SHIFT 2 + +#define BQ2597X_VBAT_INSERT_STAT_MASK 0x02 +#define BQ2597X_VBAT_INSERT_STAT_SHIFT 1 + +#define BQ2597X_ADC_DONE_STAT_MASK 0x01 +#define BQ2597X_ADC_DONE_STAT_SHIFT 0 +#define BQ2597X_ADC_DONE_STAT_COMPLETE 1 +#define BQ2597X_ADC_DONE_STAT_NOTCOMPLETE 0 + +/* Register 0Eh */ +#define BQ2597X_REG_0E 0x0E +#define BQ2597X_BAT_OVP_ALM_FLAG_MASK 0x80 +#define BQ2597X_BAT_OVP_ALM_FLAG_SHIFT 7 + +#define BQ2597X_BAT_OCP_ALM_FLAG_MASK 0x40 +#define BQ2597X_BAT_OCP_ALM_FLAG_SHIFT 6 + +#define BQ2597X_BUS_OVP_ALM_FLAG_MASK 0x20 +#define BQ2597X_BUS_OVP_ALM_FLAG_SHIFT 5 + +#define BQ2597X_BUS_OCP_ALM_FLAG_MASK 0x10 +#define BQ2597X_BUS_OCP_ALM_FLAG_SHIFT 4 + +#define BQ2597X_BAT_UCP_ALM_FLAG_MASK 0x08 +#define BQ2597X_BAT_UCP_ALM_FLAG_SHIFT 3 + +#define BQ2597X_ADAPTER_INSERT_FLAG_MASK 0x04 +#define BQ2597X_ADAPTER_INSERT_FLAG_SHIFT 2 + +#define BQ2597X_VBAT_INSERT_FLAG_MASK 0x02 +#define BQ2597X_VBAT_INSERT_FLAG_SHIFT 1 + +#define BQ2597X_ADC_DONE_FLAG_MASK 0x01 +#define BQ2597X_ADC_DONE_FLAG_SHIFT 0 +#define BQ2597X_ADC_DONE_FLAG_COMPLETE 1 +#define BQ2597X_ADC_DONE_FLAG_NOTCOMPLETE 0 + +/* Register 0Fh */ +#define BQ2597X_REG_0F 0x0F +#define BQ2597X_BAT_OVP_ALM_MASK_MASK 0x80 +#define BQ2597X_BAT_OVP_ALM_MASK_SHIFT 7 +#define BQ2597X_BAT_OVP_ALM_MASK_ENABLE 1 +#define BQ2597X_BAT_OVP_ALM_MASK_DISABLE 0 + +#define BQ2597X_BAT_OCP_ALM_MASK_MASK 0x40 +#define BQ2597X_BAT_OCP_ALM_MASK_SHIFT 6 +#define BQ2597X_BAT_OCP_ALM_MASK_ENABLE 1 +#define BQ2597X_BAT_OCP_ALM_MASK_DISABLE 0 + +#define BQ2597X_BUS_OVP_ALM_MASK_MASK 0x20 +#define BQ2597X_BUS_OVP_ALM_MASK_SHIFT 5 +#define BQ2597X_BUS_OVP_ALM_MASK_ENABLE 1 +#define BQ2597X_BUS_OVP_ALM_MASK_DISABLE 0 + +#define BQ2597X_BUS_OCP_ALM_MASK_MASK 0x10 +#define BQ2597X_BUS_OCP_ALM_MASK_SHIFT 4 +#define BQ2597X_BUS_OCP_ALM_MASK_ENABLE 1 +#define BQ2597X_BUS_OCP_ALM_MASK_DISABLE 0 + +#define BQ2597X_BAT_UCP_ALM_MASK_MASK 0x08 +#define BQ2597X_BAT_UCP_ALM_MASK_SHIFT 3 +#define BQ2597X_BAT_UCP_ALM_MASK_ENABLE 1 +#define BQ2597X_BAT_UCP_ALM_MASK_DISABLE 0 + +#define BQ2597X_ADAPTER_INSERT_MASK_MASK 0x04 +#define BQ2597X_ADAPTER_INSERT_MASK_SHIFT 2 +#define BQ2597X_ADAPTER_INSERT_MASK_ENABLE 1 +#define BQ2597X_ADAPTER_INSERT_MASK_DISABLE 0 + +#define BQ2597X_VBAT_INSERT_MASK_MASK 0x02 +#define BQ2597X_VBAT_INSERT_MASK_SHIFT 1 +#define BQ2597X_VBAT_INSERT_MASK_ENABLE 1 +#define BQ2597X_VBAT_INSERT_MASK_DISABLE 0 + +#define BQ2597X_ADC_DONE_MASK_MASK 0x01 +#define BQ2597X_ADC_DONE_MASK_SHIFT 0 +#define BQ2597X_ADC_DONE_MASK_ENABLE 1 +#define BQ2597X_ADC_DONE_MASK_DISABLE 0 + +/* Register 10h */ +#define BQ2597X_REG_10 0x10 +#define BQ2597X_BAT_OVP_FLT_STAT_MASK 0x80 +#define BQ2597X_BAT_OVP_FLT_STAT_SHIFT 7 + +#define BQ2597X_BAT_OCP_FLT_STAT_MASK 0x40 +#define BQ2597X_BAT_OCP_FLT_STAT_SHIFT 6 + +#define BQ2597X_BUS_OVP_FLT_STAT_MASK 0x20 +#define BQ2597X_BUS_OVP_FLT_STAT_SHIFT 5 + +#define BQ2597X_BUS_OCP_FLT_STAT_MASK 0x10 +#define BQ2597X_BUS_OCP_FLT_STAT_SHIFT 4 + +#define BQ2597X_TSBUS_TSBAT_ALM_STAT_MASK 0x08 +#define BQ2597X_TSBUS_TSBAT_ALM_STAT_SHIFT 3 + +#define BQ2597X_TSBAT_FLT_STAT_MASK 0x04 +#define BQ2597X_TSBAT_FLT_STAT_SHIFT 2 + +#define BQ2597X_TSBUS_FLT_STAT_MASK 0x02 +#define BQ2597X_TSBUS_FLT_STAT_SHIFT 1 + +#define BQ2597X_TDIE_ALM_STAT_MASK 0x01 +#define BQ2597X_TDIE_ALM_STAT_SHIFT 0 + +/* Register 11h */ +#define BQ2597X_REG_11 0x11 +#define BQ2597X_BAT_OVP_FLT_FLAG_MASK 0x80 +#define BQ2597X_BAT_OVP_FLT_FLAG_SHIFT 7 + +#define BQ2597X_BAT_OCP_FLT_FLAG_MASK 0x40 +#define BQ2597X_BAT_OCP_FLT_FLAG_SHIFT 6 + +#define BQ2597X_BUS_OVP_FLT_FLAG_MASK 0x20 +#define BQ2597X_BUS_OVP_FLT_FLAG_SHIFT 5 + +#define BQ2597X_BUS_OCP_FLT_FLAG_MASK 0x10 +#define BQ2597X_BUS_OCP_FLT_FLAG_SHIFT 4 + +#define BQ2597X_TSBUS_TSBAT_ALM_FLAG_MASK 0x08 +#define BQ2597X_TSBUS_TSBAT_ALM_FLAG_SHIFT 3 + +#define BQ2597X_TSBAT_FLT_FLAG_MASK 0x04 +#define BQ2597X_TSBAT_FLT_FLAG_SHIFT 2 + +#define BQ2597X_TSBUS_FLT_FLAG_MASK 0x02 +#define BQ2597X_TSBUS_FLT_FLAG_SHIFT 1 + +#define BQ2597X_TDIE_ALM_FLAG_MASK 0x01 +#define BQ2597X_TDIE_ALM_FLAG_SHIFT 0 + +/* Register 12h */ +#define BQ2597X_REG_12 0x12 +#define BQ2597X_BAT_OVP_FLT_MASK_MASK 0x80 +#define BQ2597X_BAT_OVP_FLT_MASK_SHIFT 7 +#define BQ2597X_BAT_OVP_FLT_MASK_ENABLE 1 +#define BQ2597X_BAT_OVP_FLT_MASK_DISABLE 0 + +#define BQ2597X_BAT_OCP_FLT_MASK_MASK 0x40 +#define BQ2597X_BAT_OCP_FLT_MASK_SHIFT 6 +#define BQ2597X_BAT_OCP_FLT_MASK_ENABLE 1 +#define BQ2597X_BAT_OCP_FLT_MASK_DISABLE 0 + +#define BQ2597X_BUS_OVP_FLT_MASK_MASK 0x20 +#define BQ2597X_BUS_OVP_FLT_MASK_SHIFT 5 +#define BQ2597X_BUS_OVP_FLT_MASK_ENABLE 1 +#define BQ2597X_BUS_OVP_FLT_MASK_DISABLE 0 + +#define BQ2597X_BUS_OCP_FLT_MASK_MASK 0x10 +#define BQ2597X_BUS_OCP_FLT_MASK_SHIFT 4 +#define BQ2597X_BUS_OCP_FLT_MASK_ENABLE 1 +#define BQ2597X_BUS_OCP_FLT_MASK_DISABLE 0 + +#define BQ2597X_TSBUS_TSBAT_ALM_MASK_MASK 0x08 +#define BQ2597X_TSBUS_TSBAT_ALM_MASK_SHIFT 3 +#define BQ2597X_TSBUS_TSBAT_ALM_MASK_ENABLE 1 +#define BQ2597X_TSBUS_TSBAT_ALM_MASK_DISABLE 0 + +#define BQ2597X_TSBAT_FLT_MASK_MASK 0x04 +#define BQ2597X_TSBAT_FLT_MASK_SHIFT 2 +#define BQ2597X_TSBAT_FLT_MASK_ENABLE 1 +#define BQ2597X_TSBAT_FLT_MASK_DISABLE 0 + +#define BQ2597X_TSBUS_FLT_MASK_MASK 0x02 +#define BQ2597X_TSBUS_FLT_MASK_SHIFT 1 +#define BQ2597X_TSBUS_FLT_MASK_ENABLE 1 +#define BQ2597X_TSBUS_FLT_MASK_DISABLE 0 + +#define BQ2597X_TDIE_ALM_MASK_MASK 0x01 +#define BQ2597X_TDIE_ALM_MASK_SHIFT 0 +#define BQ2597X_TDIE_ALM_MASK_ENABLE 1 +#define BQ2597X_TDIE_ALM_MASK_DISABLE 0 + +/* Register 13h */ +#define BQ2597X_REG_13 0x13 +#define BQ2597X_DEV_ID_MASK 0x0F +#define BQ2597X_DEV_ID_SHIFT 0 + +/* Register 14h */ +#define BQ2597X_REG_14 0x14 +#define BQ2597X_ADC_EN_MASK 0x80 +#define BQ2597X_ADC_EN_SHIFT 7 +#define BQ2597X_ADC_ENABLE 1 +#define BQ2597X_ADC_DISABLE 0 + +#define BQ2597X_ADC_RATE_MASK 0x40 +#define BQ2597X_ADC_RATE_SHIFT 6 +#define BQ2597X_ADC_RATE_CONTINOUS 0 +#define BQ2597X_ADC_RATE_ONESHOT 1 + +#define BQ2597X_ADC_AVG_MASK 0x20 +#define BQ2597X_ADC_AVG_SHIFT 5 +#define BQ2597X_ADC_AVG_DISABLE 0 +#define BQ2597X_ADC_AVG_ENABLE 1 + +#define BQ2597X_ADC_AVG_INIT_MASK 0x10 +#define BQ2597X_ADC_AVG_INIT_SHIFT 4 +#define BQ2597X_ADC_AVG_INIT_EXIST_REG_VAL 0 +#define BQ2597X_ADC_AVG_INIT_NEW_CONVERSION 1 + +#define BQ2597X_ADC_SAMPLE_MASK 0x0C +#define BQ2597X_ADC_SAMPLE_SHIFT 2 +#define BQ2597X_ADC_SAMPLE_15BITS 0 +#define BQ2597X_ADC_SAMPLE_14BITS 1 +#define BQ2597X_ADC_SAMPLE_13BITS 2 +#define BQ2597X_ADC_SAMPLE_12BITS 3 + +#define BQ2597X_IBUS_ADC_DIS_MASK 0x01 +#define BQ2597X_IBUS_ADC_DIS_SHIFT 0 +#define BQ2597X_IBUS_ADC_ENABLE 0 +#define BQ2597X_IBUS_ADC_DISABLE 1 + +/* Register 15h */ +#define BQ2597X_REG_15 0x15 +#define BQ2597X_VBUS_ADC_DIS_MASK 0x80 +#define BQ2597X_VBUS_ADC_DIS_SHIFT 7 +#define BQ2597X_VBUS_ADC_ENABLE 0 +#define BQ2597X_VBUS_ADC_DISABLE 1 + +#define BQ2597X_VAC_ADC_DIS_MASK 0x40 +#define BQ2597X_VAC_ADC_DIS_SHIFT 6 +#define BQ2597X_VAC_ADC_ENABLE 0 +#define BQ2597X_VAC_ADC_DISABLE 1 + +#define BQ2597X_VOUT_ADC_DIS_MASK 0x20 +#define BQ2597X_VOUT_ADC_DIS_SHIFT 5 +#define BQ2597X_VOUT_ADC_ENABLE 0 +#define BQ2597X_VOUT_ADC_DISABLE 1 + +#define BQ2597X_VBAT_ADC_DIS_MASK 0x10 +#define BQ2597X_VBAT_ADC_DIS_SHIFT 4 +#define BQ2597X_VBAT_ADC_ENABLE 0 +#define BQ2597X_VBAT_ADC_DISABLE 1 + +#define BQ2597X_IBAT_ADC_DIS_MASK 0x08 +#define BQ2597X_IBAT_ADC_DIS_SHIFT 3 +#define BQ2597X_IBAT_ADC_ENABLE 0 +#define BQ2597X_IBAT_ADC_DISABLE 1 + +#define BQ2597X_TSBUS_ADC_DIS_MASK 0x04 +#define BQ2597X_TSBUS_ADC_DIS_SHIFT 2 +#define BQ2597X_TSBUS_ADC_ENABLE 0 +#define BQ2597X_TSBUS_ADC_DISABLE 1 + +#define BQ2597X_TSBAT_ADC_DIS_MASK 0x02 +#define BQ2597X_TSBAT_ADC_DIS_SHIFT 1 +#define BQ2597X_TSBAT_ADC_ENABLE 0 +#define BQ2597X_TSBAT_ADC_DISABLE 1 + +#define BQ2597X_TDIE_ADC_DIS_MASK 0x01 +#define BQ2597X_TDIE_ADC_DIS_SHIFT 0 +#define BQ2597X_TDIE_ADC_ENABLE 0 +#define BQ2597X_TDIE_ADC_DISABLE 1 + +/* Register 16h */ +#define BQ2597X_REG_16 0x16 +#define BQ2597X_IBUS_POL_MASK 0x80 +#define BQ2597X_IBUS_POL_SHIFT 7 +#define BQ2597X_IBUS_POL_POSITIVE 0 +#define BQ2597X_IBUS_POL_NAGETIVE 1 + +#define BQ2597X_IBUS_ADC1_MASK 0x7F +#define BQ2597X_IBUS_ADC1_SHIFT 0 +#define BQ2597X_IBUS_ADC1_BASE 0 +#define BQ2597X_IBUS_ADC1_LSB 256 + +/* Register 17h */ +#define BQ2597X_REG_17 0x17 +#define BQ2597X_IBUS_ADC0_MASK 0xFF +#define BQ2597X_IBUS_ADC0_SHIFT 0 +#define BQ2597X_IBUS_ADC0_BASE 0 +#define BQ2597X_IBUS_ADC0_LSB 1 + +/* Register 18h */ +#define BQ2597X_REG_18 0x18 +#define BQ2597X_VBUS_POL_MASK 0x80 +#define BQ2597X_VBUS_POL_SHIFT 7 +#define BQ2597X_VBUS_POL_POSITIVE 0 +#define BQ2597X_VBUS_POL_NEGATIVE 1 + +#define BQ2597X_VBUS_ADC1_MASK 0x7F +#define BQ2597X_VBUS_ADC1_SHIFT 0 +#define BQ2597X_VBUS_ADC1_BASE 0 +#define BQ2597X_VBUS_ADC1_LSB 256 + +/* Register 19h */ +#define BQ2597X_REG_19 0x19 +#define BQ2597X_VBUS_ADC0_MASK 0xFF +#define BQ2597X_VBUS_ADC0_SHIFT 0 +#define BQ2597X_VBUS_ADC0_BASE 0 +#define BQ2597X_VBUS_ADC0_LSB 1 + +/* Register 1Ah */ +#define BQ2597X_REG_1A 0x1A +#define BQ2597X_VAC_POL_MASK 0x80 +#define BQ2597X_VAC_POL_SHIFT 7 +#define BQ2597X_VAC_POL_POSITIVE 0 +#define BQ2597X_VAC_POL_NEGATIVE 1 + +#define BQ2597X_VAC_ADC1_MASK 0x7F +#define BQ2597X_VAC_ADC1_SHIFT 0 +#define BQ2597X_VAC_ADC1_BASE 0 +#define BQ2597X_VAC_ADC1_LSB 256 + +/* Register 1Bh */ +#define BQ2597X_REG_1B 0x1B +#define BQ2597X_VAC_ADC0_MASK 0xFF +#define BQ2597X_VAC_ADC0_SHIFT 0 +#define BQ2597X_VAC_ADC0_BASE 0 +#define BQ2597X_VAC_ADC0_LSB 1 + +/* Register 1Ch */ +#define BQ2597X_REG_1C 0x1C +#define BQ2597X_VOUT_POL_MASK 0x80 +#define BQ2597X_VOUT_POL_SHIFT 7 +#define BQ2597X_VOUT_POL_POSITIVE 0 +#define BQ2597X_VOUT_POL_NEGATIVE 1 + +#define BQ2597X_VOUT_ADC1_MASK 0x7F +#define BQ2597X_VOUT_ADC1_SHIFT 0 +#define BQ2597X_VOUT_ADC1_BASE 0 +#define BQ2597X_VOUT_ADC1_LSB 256 + +/* Register 1Dh */ +#define BQ2597X_REG_1D 0x1D +#define BQ2597X_VOUT_ADC0_MASK 0xFF +#define BQ2597X_VOUT_ADC0_SHIFT 0 +#define BQ2597X_VOUT_ADC0_BASE 0 +#define BQ2597X_VOUT_ADC0_LSB 1 + +/* Register 1Eh */ +#define BQ2597X_REG_1E 0x1E +#define BQ2597X_VBAT_POL_MASK 0x80 +#define BQ2597X_VBAT_POL_SHIFT 7 +#define BQ2597X_VBAT_POL_POSITIVE 0 +#define BQ2597X_VBAT_POL_NEGATIVE 1 + +#define BQ2597X_VBAT_ADC1_MASK 0x7F +#define BQ2597X_VBAT_ADC1_SHIFT 0 +#define BQ2597X_VBAT_ADC1_BASE 0 +#define BQ2597X_VBAT_ADC1_LSB 256 + +/* Register 1Fh */ +#define BQ2597X_REG_1F 0x1F +#define BQ2597X_VBAT_ADC0_MASK 0xFF +#define BQ2597X_VBAT_ADC0_SHIFT 0 +#define BQ2597X_VBAT_ADC0_BASE 0 +#define BQ2597X_VBAT_ADC0_LSB 1 + +/* Register 20h */ +#define BQ2597X_REG_20 0x20 +#define BQ2597X_IBAT_POL_MASK 0x80 +#define BQ2597X_IBAT_POL_SHIFT 7 +#define BQ2597X_IBAT_POL_POSITIVE 0 +#define BQ2597X_IBAT_POL_NEGATIVE 1 + +#define BQ2597X_IBAT_ADC1_MASK 0x7F +#define BQ2597X_IBAT_ADC1_SHIFT 0 +#define BQ2597X_IBAT_ADC1_BASE 0 +#define BQ2597X_IBAT_ADC1_LSB 256 + +/* Register 21h */ +#define BQ2597X_REG_21 0x21 +#define BQ2597X_IBAT_ADC0_MASK 0xFF +#define BQ2597X_IBAT_ADC0_SHIFT 0 +#define BQ2597X_IBAT_ADC0_BASE 0 +#define BQ2597X_IBAT_ADC0_LSB 1 + +/* Register 22h */ +#define BQ2597X_REG_22 0x22 +#define BQ2597X_TSBUS_POL_MASK 0x80 +#define BQ2597X_TSBUS_POL_SHIFT 7 +#define BQ2597X_TSBUS_POL_POSITIVE 0 +#define BQ2597X_TSBUS_POL_NEGATIVE 1 + +#define BQ2597X_TSBUS_ADC1_MASK 0x7F +#define BQ2597X_TSBUS_ADC1_SHIFT 0 +#define BQ2597X_TSBUS_ADC1_BASE 0 +#define BQ2597X_TSBUS_ADC1_LSB 25 + +/* Register 23h */ +#define BQ2597X_REG_23 0x23 +#define BQ2597X_TSBUS_ADC0_MASK 0xFF +#define BQ2597X_TSBUS_ADC0_SHIFT 0 +#define BQ2597X_TSBUS_ADC0_BASE 0 +#define BQ2597X_TSBUS_ADC0_LSB 0.09766 + +/* Register 24h */ +#define BQ2597X_REG_24 0x24 +#define BQ2597X_TSBAT_POL_MASK 0x80 +#define BQ2597X_TSBAT_POL_SHIFT 7 +#define BQ2597X_TSBAT_POL_POSITIVE 0 +#define BQ2597X_TSBAT_POL_NEGATIVE 1 + +#define BQ2597X_TSBAT_ADC1_MASK 0x7F +#define BQ2597X_TSBAT_ADC1_SHIFT 0 +#define BQ2597X_TSBAT_ADC1_BASE 0 +#define BQ2597X_TSBAT_ADC1_LSB 25 + +/* Register 25h */ +#define BQ2597X_REG_25 0x25 +#define BQ2597X_TSBAT_ADC0_MASK 0xFF +#define BQ2597X_TSBAT_ADC0_SHIFT 0 +#define BQ2597X_TSBAT_ADC0_BASE 0 +#define BQ2597X_TSBAT_ADC0_LSB 0.09766 + +/* Register 26h */ +#define BQ2597X_REG_26 0x26 +#define BQ2597X_TDIE_POL_MASK 0x80 +#define BQ2597X_TDIE_POL_SHIFT 7 +#define BQ2597X_TDIE_POL_POSITIVE 0 +#define BQ2597X_TDIE_POL_NEGATIVE 1 + +#define BQ2597X_TDIE_ADC1_MASK 0x7F +#define BQ2597X_TDIE_ADC1_SHIFT 0 +#define BQ2597X_TDIE_ADC1_BASE 0 +#define BQ2597X_TDIE_ADC1_LSB 128 + +/* Register 27h */ +#define BQ2597X_REG_27 0x27 +#define BQ2597X_TDIE_ADC0_MASK 0xFF +#define BQ2597X_TDIE_ADC0_SHIFT 0 +#define BQ2597X_TDIE_ADC0_BASE 0 +#define BQ2597X_TDIE_ADC0_LSB 0.5 + +/* Register 28h */ +#define BQ2597X_REG_28 0x28 +#define BQ2597X_TSBUS_FLT1_MASK 0xFF +#define BQ2597X_TSBUS_FLT1_SHIFT 0 +#define BQ2597X_TSBUS_FLT1_BASE 0 +#define BQ2597X_TSBUS_FLT1_LSB 0.19531 + +/* Register 29h */ +#define BQ2597X_REG_29 0x29 +#define BQ2597X_TSBAT_FLT0_MASK 0xFF +#define BQ2597X_TSBAT_FLT0_SHIFT 0 +#define BQ2597X_TSBAT_FLT0_BASE 0 +#define BQ2597X_TSBAT_FLT0_LSB 0.19531 + +/* Register 2Ah */ +#define BQ2597X_REG_2A 0x2A +#define BQ2597X_TDIE_ALM_MASK 0xFF +#define BQ2597X_TDIE_ALM_SHIFT 0 +#define BQ2597X_TDIE_ALM_BASE 30 + +#define BQ2597X_TDIE_ALM_LSB \ + 2 /*careful + multiply is used for calc*/ + +/* Register 2Bh */ +#define BQ2597X_REG_2B 0x2B +#define BQ2597X_SS_TIMEOUT_SET_MASK 0xE0 +#define BQ2597X_SS_TIMEOUT_SET_SHIFT 5 +#define BQ2597X_SS_TIMEOUT_DISABLE 0 +#define BQ2597X_SS_TIMEOUT_12P5MS 1 +#define BQ2597X_SS_TIMEOUT_25MS 2 +#define BQ2597X_SS_TIMEOUT_50MS 3 +#define BQ2597X_SS_TIMEOUT_100MS 4 +#define BQ2597X_SS_TIMEOUT_400MS 5 +#define BQ2597X_SS_TIMEOUT_1500MS 6 +#define BQ2597X_SS_TIMEOUT_100000MS 7 + +#define BQ2597X_EN_REGULATION_MASK 0x10 +#define BQ2597X_EN_REGULATION_SHIFT 4 +#define BQ2597X_EN_REGULATION_ENABLE 1 +#define BQ2597X_EN_REGULATION_DISABLE 0 + +#define BQ2597X_VOUT_OVP_DIS_MASK 0x08 +#define BQ2597X_VOUT_OVP_DIS_SHIFT 3 +#define BQ2597X_VOUT_OVP_ENABLE 1 +#define BQ2597X_VOUT_OVP_DISABLE 0 + +#define BQ2597X_IBUS_UCP_RISE_TH_MASK 0x04 +#define BQ2597X_IBUS_UCP_RISE_TH_SHIFT 2 +#define BQ2597X_IBUS_UCP_RISE_300MA 0 +#define BQ2597X_IBUS_UCP_RISE_500MA 1 + +#define BQ2597X_SET_IBAT_SNS_RES_MASK 0x02 +#define BQ2597X_SET_IBAT_SNS_RES_SHIFT 1 +#define BQ2597X_SET_IBAT_SNS_RES_2MHM 0 +#define BQ2597X_SET_IBAT_SNS_RES_5MHM 1 + +#define BQ2597X_VAC_PD_EN_MASK 0x01 +#define BQ2597X_VAC_PD_EN_SHIFT 0 +#define BQ2597X_VAC_PD_ENABLE 1 +#define BQ2597X_VAC_PD_DISABLE 0 + +/* Register 2Ch */ +#define BQ2597X_REG_2C 0x2C +#define BQ2597X_IBAT_REG_MASK 0xC0 +#define BQ2597X_IBAT_REG_SHIFT 6 +#define BQ2597X_IBAT_REG_200MA 0 +#define BQ2597X_IBAT_REG_300MA 1 +#define BQ2597X_IBAT_REG_400MA 2 +#define BQ2597X_IBAT_REG_500MA 3 +#define BQ2597X_VBAT_REG_MASK 0x30 +#define BQ2597X_VBAT_REG_SHIFT 4 +#define BQ2597X_VBAT_REG_50MV 0 +#define BQ2597X_VBAT_REG_100MV 1 +#define BQ2597X_VBAT_REG_150MV 2 +#define BQ2597X_VBAT_REG_200MV 3 + +#define BQ2597X_VBAT_REG_ACTIVE_STAT_MASK 0x08 +#define BQ2597X_IBAT_REG_ACTIVE_STAT_MASK 0x04 +#define BQ2597X_VDROP_OVP_ACTIVE_STAT_MASK 0x02 +#define BQ2597X_VOUT_OVP_ACTIVE_STAT_MASK 0x01 + +#define BQ2597X_REG_2D 0x2D +#define BQ2597X_VBAT_REG_ACTIVE_FLAG_MASK 0x80 +#define BQ2597X_IBAT_REG_ACTIVE_FLAG_MASK 0x40 +#define BQ2597X_VDROP_OVP_FLAG_MASK 0x20 +#define BQ2597X_VOUT_OVP_FLAG_MASK 0x10 +#define BQ2597X_VBAT_REG_ACTIVE_MASK_MASK 0x08 +#define BQ2597X_IBAT_REG_ACTIVE_MASK_MASK 0x04 +#define BQ2597X_VDROP_OVP_MASK_MASK 0x02 +#define BQ2597X_VOUT_OVP_MASK_MASK 0x01 + +#define BQ2597X_REG_2E 0x2E +#define BQ2597X_VBUS_ERR_LOW_DG_MASK 0x10 +#define BQ2597X_VBUS_ERR_LOW_DG_SHIFT 4 +#define BQ2597X_VBUS_ERR_LOW_DG_10US 0 +#define BQ2597X_VBUS_ERR_LOW_DG_10MS 1 +#define BQ2597X_IBUS_LOW_DG_MASK 0x08 +#define BQ2597X_IBUS_LOW_DG_SHIFT 3 +#define BQ2597X_IBUS_LOW_DG_10US 0 +#define BQ2597X_IBUS_LOW_DG_5MS 1 + +#endif diff --git a/drivers/power/supply/ti/bq2597x_charger.c b/drivers/power/supply/ti/bq2597x_charger.c new file mode 100644 index 000000000000..304916983cab --- /dev/null +++ b/drivers/power/supply/ti/bq2597x_charger.c @@ -0,0 +1,2462 @@ +/* + * BQ2570x battery charging driver + * + * Copyright (C) 2017 Texas Instruments * + * Copyright (C) 2021 XiaoMi, Inc. + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#define pr_fmt(fmt) "[bq2597x] %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bq25970_reg.h" +/*#include "bq2597x.h"*/ + +enum { + VBUS_ERROR_NONE, + VBUS_ERROR_LOW, + VBUS_ERROR_HIGH, +}; + +enum { + ADC_IBUS, + ADC_VBUS, + ADC_VAC, + ADC_VOUT, + ADC_VBAT, + ADC_IBAT, + ADC_TBUS, + ADC_TBAT, + ADC_TDIE, + ADC_MAX_NUM, +}; + +#define BQ25970_ROLE_STDALONE 0 +#define BQ25970_ROLE_SLAVE 1 +#define BQ25970_ROLE_MASTER 2 + +enum { + BQ25970_STDALONE, + BQ25970_SLAVE, + BQ25970_MASTER, +}; + +static int bq2597x_mode_data[] = { + [BQ25970_STDALONE] = BQ25970_STDALONE, + [BQ25970_MASTER] = BQ25970_ROLE_MASTER, + [BQ25970_SLAVE] = BQ25970_ROLE_SLAVE, +}; + +#define BAT_OVP_ALARM BIT(7) +#define BAT_OCP_ALARM BIT(6) +#define BUS_OVP_ALARM BIT(5) +#define BUS_OCP_ALARM BIT(4) +#define BAT_UCP_ALARM BIT(3) +#define VBUS_INSERT BIT(2) +#define VBAT_INSERT BIT(1) +#define ADC_DONE BIT(0) + +#define BAT_OVP_FAULT BIT(7) +#define BAT_OCP_FAULT BIT(6) +#define BUS_OVP_FAULT BIT(5) +#define BUS_OCP_FAULT BIT(4) +#define TBUS_TBAT_ALARM BIT(3) +#define TS_BAT_FAULT BIT(2) +#define TS_BUS_FAULT BIT(1) +#define TS_DIE_FAULT BIT(0) + +/*below used for comm with other module*/ +#define BAT_OVP_FAULT_SHIFT 0 +#define BAT_OCP_FAULT_SHIFT 1 +#define BUS_OVP_FAULT_SHIFT 2 +#define BUS_OCP_FAULT_SHIFT 3 +#define BAT_THERM_FAULT_SHIFT 4 +#define BUS_THERM_FAULT_SHIFT 5 +#define DIE_THERM_FAULT_SHIFT 6 + +#define BAT_OVP_FAULT_MASK (1 << BAT_OVP_FAULT_SHIFT) +#define BAT_OCP_FAULT_MASK (1 << BAT_OCP_FAULT_SHIFT) +#define BUS_OVP_FAULT_MASK (1 << BUS_OVP_FAULT_SHIFT) +#define BUS_OCP_FAULT_MASK (1 << BUS_OCP_FAULT_SHIFT) +#define BAT_THERM_FAULT_MASK (1 << BAT_THERM_FAULT_SHIFT) +#define BUS_THERM_FAULT_MASK (1 << BUS_THERM_FAULT_SHIFT) +#define DIE_THERM_FAULT_MASK (1 << DIE_THERM_FAULT_SHIFT) + +#define BAT_OVP_ALARM_SHIFT 0 +#define BAT_OCP_ALARM_SHIFT 1 +#define BUS_OVP_ALARM_SHIFT 2 +#define BUS_OCP_ALARM_SHIFT 3 +#define BAT_THERM_ALARM_SHIFT 4 +#define BUS_THERM_ALARM_SHIFT 5 +#define DIE_THERM_ALARM_SHIFT 6 +#define BAT_UCP_ALARM_SHIFT 7 + +#define BAT_OVP_ALARM_MASK (1 << BAT_OVP_ALARM_SHIFT) +#define BAT_OCP_ALARM_MASK (1 << BAT_OCP_ALARM_SHIFT) +#define BUS_OVP_ALARM_MASK (1 << BUS_OVP_ALARM_SHIFT) +#define BUS_OCP_ALARM_MASK (1 << BUS_OCP_ALARM_SHIFT) +#define BAT_THERM_ALARM_MASK (1 << BAT_THERM_ALARM_SHIFT) +#define BUS_THERM_ALARM_MASK (1 << BUS_THERM_ALARM_SHIFT) +#define DIE_THERM_ALARM_MASK (1 << DIE_THERM_ALARM_SHIFT) +#define BAT_UCP_ALARM_MASK (1 << BAT_UCP_ALARM_SHIFT) + +#define VBAT_REG_STATUS_SHIFT 0 +#define IBAT_REG_STATUS_SHIFT 1 + +#define VBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT) +#define IBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT) + +#define bq_err(fmt, ...) \ + do { \ + if (bq->mode == BQ25970_ROLE_MASTER) \ + printk(KERN_ERR "[bq2597x-MASTER]:%s:" fmt, __func__, \ + ##__VA_ARGS__); \ + else if (bq->mode == BQ25970_ROLE_SLAVE) \ + printk(KERN_ERR "[bq2597x-SLAVE]:%s:" fmt, __func__, \ + ##__VA_ARGS__); \ + else \ + printk(KERN_ERR "[bq2597x-STANDALONE]:%s:" fmt, \ + __func__, ##__VA_ARGS__); \ + } while (0); + +#define bq_info(fmt, ...) \ + do { \ + if (bq->mode == BQ25970_ROLE_MASTER) \ + printk(KERN_INFO "[bq2597x-MASTER]:%s:" fmt, __func__, \ + ##__VA_ARGS__); \ + else if (bq->mode == BQ25970_ROLE_SLAVE) \ + printk(KERN_INFO "[bq2597x-SLAVE]:%s:" fmt, __func__, \ + ##__VA_ARGS__); \ + else \ + printk(KERN_INFO "[bq2597x-STANDALONE]:%s:" fmt, \ + __func__, ##__VA_ARGS__); \ + } while (0); + +#define bq_dbg(fmt, ...) \ + do { \ + if (bq->mode == BQ25970_ROLE_MASTER) \ + printk(KERN_DEBUG "[bq2597x-MASTER]:%s:" fmt, \ + __func__, ##__VA_ARGS__); \ + else if (bq->mode == BQ25970_ROLE_SLAVE) \ + printk(KERN_DEBUG "[bq2597x-SLAVE]:%s:" fmt, __func__, \ + ##__VA_ARGS__); \ + else \ + printk(KERN_DEBUG "[bq2597x-STANDALONE]:%s:" fmt, \ + __func__, ##__VA_ARGS__); \ + } while (0); + +enum hvdcp3_type { + HVDCP3_NONE = 0, + HVDCP3_CLASSA_18W, + HVDCP3_CLASSB_27W, + HVDCP3P5_CLASSA_18W, + HVDCP3P5_CLASSB_27W, +}; + +#define BUS_OVP_FOR_QC 10000 +#define BUS_OVP_ALARM_FOR_QC 9500 +#define BUS_OCP_FOR_QC_CLASS_A 3250 +#define BUS_OCP_ALARM_FOR_QC_CLASS_A 2000 +#define BUS_OCP_FOR_QC_CLASS_B 3750 +#define BUS_OCP_ALARM_FOR_QC_CLASS_B 2800 +#define BUS_OCP_FOR_QC3P5_CLASS_A 3000 +#define BUS_OCP_ALARM_FOR_QC3P5_CLASS_A 2500 +#define BUS_OCP_FOR_QC3P5_CLASS_B 3500 +#define BUS_OCP_ALARM_FOR_QC3P5_CLASS_B 3200 + +/*end*/ + +struct bq2597x_cfg { + bool bat_ovp_disable; + bool bat_ocp_disable; + bool bat_ovp_alm_disable; + bool bat_ocp_alm_disable; + + int bat_ovp_th; + int bat_ovp_alm_th; + int bat_ocp_th; + int bat_ocp_alm_th; + + bool bus_ovp_alm_disable; + bool bus_ocp_disable; + bool bus_ocp_alm_disable; + + int bus_ovp_th; + int bus_ovp_alm_th; + int bus_ocp_th; + int bus_ocp_alm_th; + + bool bat_ucp_alm_disable; + + int bat_ucp_alm_th; + int ac_ovp_th; + + bool bat_therm_disable; + bool bus_therm_disable; + bool die_therm_disable; + + int bat_therm_th; /*in %*/ + int bus_therm_th; /*in %*/ + int die_therm_th; /*in degC*/ + + int sense_r_mohm; +}; + +struct bq2597x { + struct device *dev; + struct i2c_client *client; + + int part_no; + int revision; + + int mode; + + struct mutex data_lock; + struct mutex i2c_rw_lock; + struct mutex charging_disable_lock; + struct mutex irq_complete; + + bool irq_waiting; + bool irq_disabled; + bool resume_completed; + + bool batt_present; + bool vbus_present; + + bool usb_present; + bool charge_enabled; /* Register bit status */ + + /* ADC reading */ + int vbat_volt; + int vbus_volt; + int vout_volt; + int vac_volt; + + int ibat_curr; + int ibus_curr; + + int bat_temp; + int bus_temp; + int die_temp; + + /* alarm/fault status */ + bool bat_ovp_fault; + bool bat_ocp_fault; + bool bus_ovp_fault; + bool bus_ocp_fault; + + bool bat_ovp_alarm; + bool bat_ocp_alarm; + bool bus_ovp_alarm; + bool bus_ocp_alarm; + + bool bat_ucp_alarm; + + bool bat_therm_alarm; + bool bus_therm_alarm; + bool die_therm_alarm; + + bool bat_therm_fault; + bool bus_therm_fault; + bool die_therm_fault; + + bool therm_shutdown_flag; + bool therm_shutdown_stat; + + bool vbat_reg; + bool ibat_reg; + + int prev_alarm; + int prev_fault; + + int chg_ma; + int chg_mv; + + int charge_state; + + struct bq2597x_cfg *cfg; + + int skip_writes; + int skip_reads; + + struct bq2597x_platform_data *platform_data; + + struct delayed_work monitor_work; + + struct dentry *debug_root; + + struct power_supply_desc psy_desc; + struct power_supply_config psy_cfg; + struct power_supply *fc2_psy; +}; + +static int bq_debug_flag; +module_param_named(bq_debug_flag, bq_debug_flag, int, 0600); + +/************************************************************************/ +static int __bq2597x_read_byte(struct bq2597x *bq, u8 reg, u8 *data) +{ + s32 ret; + + ret = i2c_smbus_read_byte_data(bq->client, reg); + if (ret < 0) { + bq_err("i2c read fail: can't read from reg 0x%02X\n", reg); + return ret; + } + + *data = (u8)ret; + + return 0; +} + +static int __bq2597x_write_byte(struct bq2597x *bq, int reg, u8 val) +{ + s32 ret; + + ret = i2c_smbus_write_byte_data(bq->client, reg, val); + if (ret < 0) { + bq_err("i2c write fail: can't write 0x%02X to reg 0x%02X: %d\n", + val, reg, ret); + return ret; + } + return 0; +} + +static int __bq2597x_read_word(struct bq2597x *bq, u8 reg, u16 *data) +{ + s32 ret; + + ret = i2c_smbus_read_word_data(bq->client, reg); + if (ret < 0) { + bq_err("i2c read fail: can't read from reg 0x%02X\n", reg); + return ret; + } + + *data = (u16)ret; + + return 0; +} + +static int bq2597x_read_byte(struct bq2597x *bq, u8 reg, u8 *data) +{ + int ret; + + if (bq->skip_reads) { + *data = 0; + return 0; + } + + mutex_lock(&bq->i2c_rw_lock); + ret = __bq2597x_read_byte(bq, reg, data); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} + +static int bq2597x_write_byte(struct bq2597x *bq, u8 reg, u8 data) +{ + int ret; + + if (bq->skip_writes) + return 0; + + mutex_lock(&bq->i2c_rw_lock); + ret = __bq2597x_write_byte(bq, reg, data); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} + +static int bq2597x_read_word(struct bq2597x *bq, u8 reg, u16 *data) +{ + int ret; + + if (bq->skip_reads) { + *data = 0; + return 0; + } + + mutex_lock(&bq->i2c_rw_lock); + ret = __bq2597x_read_word(bq, reg, data); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} + +static int bq2597x_update_bits(struct bq2597x *bq, u8 reg, u8 mask, u8 data) +{ + int ret; + u8 tmp; + + if (bq->skip_reads || bq->skip_writes) + return 0; + + mutex_lock(&bq->i2c_rw_lock); + ret = __bq2597x_read_byte(bq, reg, &tmp); + if (ret) { + bq_err("Failed: reg=%02X, ret=%d\n", reg, ret); + goto out; + } + + tmp &= ~mask; + tmp |= data & mask; + + ret = __bq2597x_write_byte(bq, reg, tmp); + if (ret) + bq_err("Failed: reg=%02X, ret=%d\n", reg, ret); + +out: + mutex_unlock(&bq->i2c_rw_lock); + return ret; +} + +/*********************************************************************/ + +static int bq2597x_enable_charge(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_CHG_ENABLE; + else + val = BQ2597X_CHG_DISABLE; + + val <<= BQ2597X_CHG_EN_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_0C, BQ2597X_CHG_EN_MASK, val); + + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_charge); + +static int bq2597x_check_charge_enabled(struct bq2597x *bq, bool *enabled) +{ + int ret; + u8 val; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_0C, &val); + if (!ret) + *enabled = !!(val & BQ2597X_CHG_EN_MASK); + return ret; +} + +static int bq2597x_enable_wdt(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_WATCHDOG_ENABLE; + else + val = BQ2597X_WATCHDOG_DISABLE; + + val <<= BQ2597X_WATCHDOG_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_0B, BQ2597X_WATCHDOG_DIS_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_wdt); + +static int bq2597x_set_wdt(struct bq2597x *bq, int ms) +{ + int ret; + u8 val; + + if (ms == 500) + val = BQ2597X_WATCHDOG_0P5S; + else if (ms == 1000) + val = BQ2597X_WATCHDOG_1S; + else if (ms == 5000) + val = BQ2597X_WATCHDOG_5S; + else if (ms == 30000) + val = BQ2597X_WATCHDOG_30S; + else + val = BQ2597X_WATCHDOG_30S; + + val <<= BQ2597X_WATCHDOG_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_0B, BQ2597X_WATCHDOG_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_wdt); + +static int bq2597x_enable_batovp(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BAT_OVP_ENABLE; + else + val = BQ2597X_BAT_OVP_DISABLE; + + val <<= BQ2597X_BAT_OVP_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_00, BQ2597X_BAT_OVP_DIS_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_batovp); + +static int bq2597x_set_batovp_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BAT_OVP_BASE) + threshold = BQ2597X_BAT_OVP_BASE; + + val = (threshold - BQ2597X_BAT_OVP_BASE) / BQ2597X_BAT_OVP_LSB; + + val <<= BQ2597X_BAT_OVP_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_00, BQ2597X_BAT_OVP_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_batovp_th); + +static int bq2597x_enable_batovp_alarm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BAT_OVP_ALM_ENABLE; + else + val = BQ2597X_BAT_OVP_ALM_DISABLE; + + val <<= BQ2597X_BAT_OVP_ALM_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_01, + BQ2597X_BAT_OVP_ALM_DIS_MASK, val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_batovp_alarm); + +static int bq2597x_set_batovp_alarm_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BAT_OVP_ALM_BASE) + threshold = BQ2597X_BAT_OVP_ALM_BASE; + + val = (threshold - BQ2597X_BAT_OVP_ALM_BASE) / BQ2597X_BAT_OVP_ALM_LSB; + + val <<= BQ2597X_BAT_OVP_ALM_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_01, BQ2597X_BAT_OVP_ALM_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_batovp_alarm_th); + +static int bq2597x_enable_batocp(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BAT_OCP_ENABLE; + else + val = BQ2597X_BAT_OCP_DISABLE; + + val <<= BQ2597X_BAT_OCP_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_02, BQ2597X_BAT_OCP_DIS_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_batocp); + +static int bq2597x_set_batocp_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BAT_OCP_BASE) + threshold = BQ2597X_BAT_OCP_BASE; + + val = (threshold - BQ2597X_BAT_OCP_BASE) / BQ2597X_BAT_OCP_LSB; + + val <<= BQ2597X_BAT_OCP_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_02, BQ2597X_BAT_OCP_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_batocp_th); + +static int bq2597x_enable_batocp_alarm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BAT_OCP_ALM_ENABLE; + else + val = BQ2597X_BAT_OCP_ALM_DISABLE; + + val <<= BQ2597X_BAT_OCP_ALM_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_03, + BQ2597X_BAT_OCP_ALM_DIS_MASK, val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_batocp_alarm); + +static int bq2597x_set_batocp_alarm_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BAT_OCP_ALM_BASE) + threshold = BQ2597X_BAT_OCP_ALM_BASE; + + val = (threshold - BQ2597X_BAT_OCP_ALM_BASE) / BQ2597X_BAT_OCP_ALM_LSB; + + val <<= BQ2597X_BAT_OCP_ALM_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_03, BQ2597X_BAT_OCP_ALM_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_batocp_alarm_th); + +static int bq2597x_set_busovp_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BUS_OVP_BASE) + threshold = BQ2597X_BUS_OVP_BASE; + + val = (threshold - BQ2597X_BUS_OVP_BASE) / BQ2597X_BUS_OVP_LSB; + + val <<= BQ2597X_BUS_OVP_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_06, BQ2597X_BUS_OVP_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_busovp_th); + +static int bq2597x_enable_busovp_alarm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BUS_OVP_ALM_ENABLE; + else + val = BQ2597X_BUS_OVP_ALM_DISABLE; + + val <<= BQ2597X_BUS_OVP_ALM_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_07, + BQ2597X_BUS_OVP_ALM_DIS_MASK, val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_busovp_alarm); + +static int bq2597x_set_busovp_alarm_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BUS_OVP_ALM_BASE) + threshold = BQ2597X_BUS_OVP_ALM_BASE; + + val = (threshold - BQ2597X_BUS_OVP_ALM_BASE) / BQ2597X_BUS_OVP_ALM_LSB; + + val <<= BQ2597X_BUS_OVP_ALM_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_07, BQ2597X_BUS_OVP_ALM_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_busovp_alarm_th); + +static int bq2597x_enable_busocp(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BUS_OCP_ENABLE; + else + val = BQ2597X_BUS_OCP_DISABLE; + + val <<= BQ2597X_BUS_OCP_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_08, BQ2597X_BUS_OCP_DIS_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_busocp); + +static int bq2597x_set_busocp_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BUS_OCP_BASE) + threshold = BQ2597X_BUS_OCP_BASE; + + val = (threshold - BQ2597X_BUS_OCP_BASE) / BQ2597X_BUS_OCP_LSB; + + val <<= BQ2597X_BUS_OCP_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_08, BQ2597X_BUS_OCP_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_busocp_th); + +static int bq2597x_enable_busocp_alarm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BUS_OCP_ALM_ENABLE; + else + val = BQ2597X_BUS_OCP_ALM_DISABLE; + + val <<= BQ2597X_BUS_OCP_ALM_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_09, + BQ2597X_BUS_OCP_ALM_DIS_MASK, val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_busocp_alarm); + +static int bq2597x_set_busocp_alarm_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BUS_OCP_ALM_BASE) + threshold = BQ2597X_BUS_OCP_ALM_BASE; + + val = (threshold - BQ2597X_BUS_OCP_ALM_BASE) / BQ2597X_BUS_OCP_ALM_LSB; + + val <<= BQ2597X_BUS_OCP_ALM_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_09, BQ2597X_BUS_OCP_ALM_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_busocp_alarm_th); + +static int bq2597x_enable_batucp_alarm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_BAT_UCP_ALM_ENABLE; + else + val = BQ2597X_BAT_UCP_ALM_DISABLE; + + val <<= BQ2597X_BAT_UCP_ALM_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_04, + BQ2597X_BAT_UCP_ALM_DIS_MASK, val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_batucp_alarm); + +static int bq2597x_set_batucp_alarm_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_BAT_UCP_ALM_BASE) + threshold = BQ2597X_BAT_UCP_ALM_BASE; + + val = (threshold - BQ2597X_BAT_UCP_ALM_BASE) / BQ2597X_BAT_UCP_ALM_LSB; + + val <<= BQ2597X_BAT_UCP_ALM_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_04, BQ2597X_BAT_UCP_ALM_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_batucp_alarm_th); + +static int bq2597x_set_acovp_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold < BQ2597X_AC_OVP_BASE) + threshold = BQ2597X_AC_OVP_BASE; + + if (threshold == BQ2597X_AC_OVP_6P5V) + val = 0x07; + else + val = (threshold - BQ2597X_AC_OVP_BASE) / BQ2597X_AC_OVP_LSB; + + val <<= BQ2597X_AC_OVP_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_05, BQ2597X_AC_OVP_MASK, val); + + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_acovp_th); + +static int bq2597x_set_vdrop_th(struct bq2597x *bq, int threshold) +{ + int ret; + u8 val; + + if (threshold == 300) + val = BQ2597X_VDROP_THRESHOLD_300MV; + else + val = BQ2597X_VDROP_THRESHOLD_400MV; + + val <<= BQ2597X_VDROP_THRESHOLD_SET_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_05, + BQ2597X_VDROP_THRESHOLD_SET_MASK, val); + + return ret; +} + +static int bq2597x_set_vdrop_deglitch(struct bq2597x *bq, int us) +{ + int ret; + u8 val; + + if (us == 8) + val = BQ2597X_VDROP_DEGLITCH_8US; + else + val = BQ2597X_VDROP_DEGLITCH_5MS; + + val <<= BQ2597X_VDROP_DEGLITCH_SET_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_05, + BQ2597X_VDROP_DEGLITCH_SET_MASK, val); + return ret; +} + +static int bq2597x_enable_bat_therm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_TSBAT_ENABLE; + else + val = BQ2597X_TSBAT_DISABLE; + + val <<= BQ2597X_TSBAT_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_0C, BQ2597X_TSBAT_DIS_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_bat_therm); + +/* + * the input threshold is the raw value that would write to register directly. + */ +static int bq2597x_set_bat_therm_th(struct bq2597x *bq, u8 threshold) +{ + int ret; + + ret = bq2597x_write_byte(bq, BQ2597X_REG_29, threshold); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_bat_therm_th); + +static int bq2597x_enable_bus_therm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_TSBUS_ENABLE; + else + val = BQ2597X_TSBUS_DISABLE; + + val <<= BQ2597X_TSBUS_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_0C, BQ2597X_TSBUS_DIS_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_bus_therm); + +/* + * the input threshold is the raw value that would write to register directly. + */ +static int bq2597x_set_bus_therm_th(struct bq2597x *bq, u8 threshold) +{ + int ret; + + ret = bq2597x_write_byte(bq, BQ2597X_REG_28, threshold); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_bus_therm_th); + +static int bq2597x_enable_die_therm(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_TDIE_ENABLE; + else + val = BQ2597X_TDIE_DISABLE; + + val <<= BQ2597X_TDIE_DIS_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_0C, BQ2597X_TDIE_DIS_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_die_therm); + +/* + * please be noted that the unit here is degC + */ +static int bq2597x_set_die_therm_th(struct bq2597x *bq, u8 threshold) +{ + int ret; + u8 val; + + /*BE careful, LSB is here is 1/LSB, so we use multiply here*/ + val = (threshold - BQ2597X_TDIE_ALM_BASE) * BQ2597X_TDIE_ALM_LSB; + val <<= BQ2597X_TDIE_ALM_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_2A, BQ2597X_TDIE_ALM_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_die_therm_th); + +static int bq2597x_enable_adc(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_ADC_ENABLE; + else + val = BQ2597X_ADC_DISABLE; + + val <<= BQ2597X_ADC_EN_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_14, BQ2597X_ADC_EN_MASK, val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_enable_adc); + +static int bq2597x_set_adc_average(struct bq2597x *bq, bool avg) +{ + int ret; + u8 val; + + if (avg) + val = BQ2597X_ADC_AVG_ENABLE; + else + val = BQ2597X_ADC_AVG_DISABLE; + + val <<= BQ2597X_ADC_AVG_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_14, BQ2597X_ADC_AVG_MASK, + val); + return 0; +} +EXPORT_SYMBOL_GPL(bq2597x_set_adc_average); + +static int bq2597x_set_adc_scanrate(struct bq2597x *bq, bool oneshot) +{ + int ret; + u8 val; + + if (oneshot) + val = BQ2597X_ADC_RATE_ONESHOT; + else + val = BQ2597X_ADC_RATE_CONTINOUS; + + val <<= BQ2597X_ADC_RATE_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_14, BQ2597X_ADC_EN_MASK, val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_adc_scanrate); + +static int bq2597x_set_adc_bits(struct bq2597x *bq, int bits) +{ + int ret; + u8 val; + + if (bits > 15) + bits = 15; + if (bits < 12) + bits = 12; + val = 15 - bits; + + val <<= BQ2597X_ADC_SAMPLE_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_14, BQ2597X_ADC_SAMPLE_MASK, + val); + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_adc_bits); + +#define ADC_REG_BASE 0x16 +static int bq2597x_get_adc_data(struct bq2597x *bq, int channel, int *result) +{ + int ret; + u16 val; + s16 t; + + if (channel > ADC_MAX_NUM) + return -EINVAL; + + ret = bq2597x_read_word(bq, ADC_REG_BASE + (channel << 1), &val); + if (ret < 0) + return ret; + t = val & 0xFF; + t <<= 8; + t |= (val >> 8) & 0xFF; + *result = t; + + return 0; +} +EXPORT_SYMBOL_GPL(bq2597x_get_adc_data); + +static int bq2597x_set_adc_scan(struct bq2597x *bq, int channel, bool enable) +{ + int ret; + u8 reg; + u8 mask; + u8 shift; + u8 val; + + if (channel > ADC_MAX_NUM) + return -EINVAL; + + if (channel == ADC_IBUS) { + reg = BQ2597X_REG_14; + shift = BQ2597X_IBUS_ADC_DIS_SHIFT; + mask = BQ2597X_IBUS_ADC_DIS_MASK; + } else { + reg = BQ2597X_REG_15; + shift = 8 - channel; + mask = 1 << shift; + } + + if (enable) + val = 0 << shift; + else + val = 1 << shift; + + ret = bq2597x_update_bits(bq, reg, mask, val); + + return ret; +} + +static int bq2597x_set_alarm_int_mask(struct bq2597x *bq, u8 mask) +{ + int ret; + u8 val; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_0F, &val); + if (ret) + return ret; + + val |= mask; + + ret = bq2597x_write_byte(bq, BQ2597X_REG_0F, val); + + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_alarm_int_mask); + +static int bq2597x_clear_alarm_int_mask(struct bq2597x *bq, u8 mask) +{ + int ret; + u8 val; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_0F, &val); + if (ret) + return ret; + + val &= ~mask; + + ret = bq2597x_write_byte(bq, BQ2597X_REG_0F, val); + + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_clear_alarm_int_mask); + +static int bq2597x_set_fault_int_mask(struct bq2597x *bq, u8 mask) +{ + int ret; + u8 val; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_12, &val); + if (ret) + return ret; + + val |= mask; + + ret = bq2597x_write_byte(bq, BQ2597X_REG_12, val); + + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_set_fault_int_mask); + +static int bq2597x_clear_fault_int_mask(struct bq2597x *bq, u8 mask) +{ + int ret; + u8 val; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_12, &val); + if (ret) + return ret; + + val &= ~mask; + + ret = bq2597x_write_byte(bq, BQ2597X_REG_12, val); + + return ret; +} +EXPORT_SYMBOL_GPL(bq2597x_clear_fault_int_mask); + +static int bq2597x_set_sense_resistor(struct bq2597x *bq, int r_mohm) +{ + int ret; + u8 val; + + if (r_mohm == 2) + val = BQ2597X_SET_IBAT_SNS_RES_2MHM; + else if (r_mohm == 5) + val = BQ2597X_SET_IBAT_SNS_RES_5MHM; + else + return -EINVAL; + + val <<= BQ2597X_SET_IBAT_SNS_RES_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_2B, + BQ2597X_SET_IBAT_SNS_RES_MASK, val); + return ret; +} + +static int bq2597x_set_ibus_ucp_thr(struct bq2597x *bq, int ibus_ucp_thr) +{ + int ret; + u8 val; + + if (ibus_ucp_thr == 300) + val = BQ2597X_IBUS_UCP_RISE_300MA; + else if (ibus_ucp_thr == 500) + val = BQ2597X_IBUS_UCP_RISE_500MA; + else + return -EINVAL; + + val <<= BQ2597X_IBUS_UCP_RISE_TH_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_2B, + BQ2597X_IBUS_UCP_RISE_TH_MASK, val); + return ret; +} + +static int bq2597x_enable_regulation(struct bq2597x *bq, bool enable) +{ + int ret; + u8 val; + + if (enable) + val = BQ2597X_EN_REGULATION_ENABLE; + else + val = BQ2597X_EN_REGULATION_DISABLE; + + val <<= BQ2597X_EN_REGULATION_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_2B, + BQ2597X_EN_REGULATION_MASK, val); + + return ret; +} + +static int bq2597x_set_ss_timeout(struct bq2597x *bq, int timeout) +{ + int ret; + u8 val; + + switch (timeout) { + case 0: + val = BQ2597X_SS_TIMEOUT_DISABLE; + break; + case 12: + val = BQ2597X_SS_TIMEOUT_12P5MS; + break; + case 25: + val = BQ2597X_SS_TIMEOUT_25MS; + break; + case 50: + val = BQ2597X_SS_TIMEOUT_50MS; + break; + case 100: + val = BQ2597X_SS_TIMEOUT_100MS; + break; + case 400: + val = BQ2597X_SS_TIMEOUT_400MS; + break; + case 1500: + val = BQ2597X_SS_TIMEOUT_1500MS; + break; + case 100000: + val = BQ2597X_SS_TIMEOUT_100000MS; + break; + default: + val = BQ2597X_SS_TIMEOUT_DISABLE; + break; + } + + val <<= BQ2597X_SS_TIMEOUT_SET_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_2B, + BQ2597X_SS_TIMEOUT_SET_MASK, val); + + return ret; +} + +static int bq2597x_set_ibat_reg_th(struct bq2597x *bq, int th_ma) +{ + int ret; + u8 val; + + if (th_ma == 200) + val = BQ2597X_IBAT_REG_200MA; + else if (th_ma == 300) + val = BQ2597X_IBAT_REG_300MA; + else if (th_ma == 400) + val = BQ2597X_IBAT_REG_400MA; + else if (th_ma == 500) + val = BQ2597X_IBAT_REG_500MA; + else + val = BQ2597X_IBAT_REG_500MA; + + val <<= BQ2597X_IBAT_REG_SHIFT; + ret = bq2597x_update_bits(bq, BQ2597X_REG_2C, BQ2597X_IBAT_REG_MASK, + val); + + return ret; +} + +static int bq2597x_set_vbat_reg_th(struct bq2597x *bq, int th_mv) +{ + int ret; + u8 val; + + if (th_mv == 50) + val = BQ2597X_VBAT_REG_50MV; + else if (th_mv == 100) + val = BQ2597X_VBAT_REG_100MV; + else if (th_mv == 150) + val = BQ2597X_VBAT_REG_150MV; + else + val = BQ2597X_VBAT_REG_200MV; + + val <<= BQ2597X_VBAT_REG_SHIFT; + + ret = bq2597x_update_bits(bq, BQ2597X_REG_2C, BQ2597X_VBAT_REG_MASK, + val); + + return ret; +} + +static int bq2597x_check_reg_status(struct bq2597x *bq) +{ + int ret; + u8 val; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_2C, &val); + if (!ret) { + bq->vbat_reg = !!(val & BQ2597X_VBAT_REG_ACTIVE_STAT_MASK); + bq->ibat_reg = !!(val & BQ2597X_IBAT_REG_ACTIVE_STAT_MASK); + } + + return ret; +} + +static int bq2597x_get_work_mode(struct bq2597x *bq, int *mode) +{ + int ret; + u8 val; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_0C, &val); + + if (ret) { + bq_err("Failed to read operation mode register\n"); + return ret; + } + + val = (val & BQ2597X_MS_MASK) >> BQ2597X_MS_SHIFT; + if (val == BQ2597X_MS_MASTER) + *mode = BQ25970_ROLE_MASTER; + else if (val == BQ2597X_MS_SLAVE) + *mode = BQ25970_ROLE_SLAVE; + else + *mode = BQ25970_ROLE_STDALONE; + + bq_info("work mode:%s\n", + *mode == BQ25970_ROLE_STDALONE ? + "Standalone" : + (*mode == BQ25970_ROLE_SLAVE ? "Slave" : "Master")); + return ret; +} + +static int bq2597x_detect_device(struct bq2597x *bq) +{ + int ret; + u8 data; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_13, &data); + if (ret == 0) { + bq->part_no = (data & BQ2597X_DEV_ID_MASK); + bq->part_no >>= BQ2597X_DEV_ID_SHIFT; + } + + return ret; +} + +static void bq2597x_dump_reg(struct bq2597x *bq); +#define RUNNING_PERIOD_S (60 * 1000) + +static void bq2597x_monitor_work(struct work_struct *work) +{ + struct bq2597x *bq = + container_of(work, struct bq2597x, monitor_work.work); + bq2597x_dump_reg(bq); + schedule_delayed_work(&bq->monitor_work, + msecs_to_jiffies(RUNNING_PERIOD_S)); +} + +static int bq2597x_parse_dt(struct bq2597x *bq, struct device *dev) +{ + int ret; + struct device_node *np = dev->of_node; + + bq->cfg = devm_kzalloc(dev, sizeof(struct bq2597x_cfg), GFP_KERNEL); + + if (!bq->cfg) + return -ENOMEM; + + bq->cfg->bat_ovp_disable = + of_property_read_bool(np, "ti,bq2597x,bat-ovp-disable"); + bq->cfg->bat_ocp_disable = + of_property_read_bool(np, "ti,bq2597x,bat-ocp-disable"); + bq->cfg->bat_ovp_alm_disable = + of_property_read_bool(np, "ti,bq2597x,bat-ovp-alarm-disable"); + bq->cfg->bat_ocp_alm_disable = + of_property_read_bool(np, "ti,bq2597x,bat-ocp-alarm-disable"); + bq->cfg->bus_ocp_disable = + of_property_read_bool(np, "ti,bq2597x,bus-ocp-disable"); + bq->cfg->bus_ovp_alm_disable = + of_property_read_bool(np, "ti,bq2597x,bus-ovp-alarm-disable"); + bq->cfg->bus_ocp_alm_disable = + of_property_read_bool(np, "ti,bq2597x,bus-ocp-alarm-disable"); + bq->cfg->bat_ucp_alm_disable = + of_property_read_bool(np, "ti,bq2597x,bat-ucp-alarm-disable"); + bq->cfg->bat_therm_disable = + of_property_read_bool(np, "ti,bq2597x,bat-therm-disable"); + bq->cfg->bus_therm_disable = + of_property_read_bool(np, "ti,bq2597x,bus-therm-disable"); + bq->cfg->die_therm_disable = + of_property_read_bool(np, "ti,bq2597x,die-therm-disable"); + + ret = of_property_read_u32(np, "ti,bq2597x,bat-ovp-threshold", + &bq->cfg->bat_ovp_th); + if (ret) { + bq_err("failed to read bat-ovp-threshold\n"); + return ret; + } + ret = of_property_read_u32(np, "ti,bq2597x,bat-ovp-alarm-threshold", + &bq->cfg->bat_ovp_alm_th); + if (ret) { + bq_err("failed to read bat-ovp-alarm-threshold\n"); + return ret; + } + /*ret = of_property_read_u32(np, "ti,bq2597x,bat-ocp-threshold", + &bq->cfg->bat_ocp_th); + if (ret) { + bq_err("failed to read bat-ocp-threshold\n"); + return ret; + } + ret = of_property_read_u32(np, "ti,bq2597x,bat-ocp-alarm-threshold", + &bq->cfg->bat_ocp_alm_th); + if (ret) { + bq_err("failed to read bat-ocp-alarm-threshold\n"); + return ret; + }*/ + ret = of_property_read_u32(np, "ti,bq2597x,bus-ovp-threshold", + &bq->cfg->bus_ovp_th); + if (ret) { + bq_err("failed to read bus-ovp-threshold\n"); + return ret; + } + ret = of_property_read_u32(np, "ti,bq2597x,bus-ovp-alarm-threshold", + &bq->cfg->bus_ovp_alm_th); + if (ret) { + bq_err("failed to read bus-ovp-alarm-threshold\n"); + return ret; + } + ret = of_property_read_u32(np, "ti,bq2597x,bus-ocp-threshold", + &bq->cfg->bus_ocp_th); + if (ret) { + bq_err("failed to read bus-ocp-threshold\n"); + return ret; + } + ret = of_property_read_u32(np, "ti,bq2597x,bus-ocp-alarm-threshold", + &bq->cfg->bus_ocp_alm_th); + if (ret) { + bq_err("failed to read bus-ocp-alarm-threshold\n"); + return ret; + } + /*ret = of_property_read_u32(np, "ti,bq2597x,bat-ucp-alarm-threshold", + &bq->cfg->bat_ucp_alm_th); + if (ret) { + bq_err("failed to read bat-ucp-alarm-threshold\n"); + return ret; + }*/ + ret = of_property_read_u32(np, "ti,bq2597x,bat-therm-threshold", + &bq->cfg->bat_therm_th); + if (ret) { + bq_err("failed to read bat-therm-threshold\n"); + return ret; + } + ret = of_property_read_u32(np, "ti,bq2597x,bus-therm-threshold", + &bq->cfg->bus_therm_th); + if (ret) { + bq_err("failed to read bus-therm-threshold\n"); + return ret; + } + ret = of_property_read_u32(np, "ti,bq2597x,die-therm-threshold", + &bq->cfg->die_therm_th); + if (ret) { + bq_err("failed to read die-therm-threshold\n"); + return ret; + } + + ret = of_property_read_u32(np, "ti,bq2597x,ac-ovp-threshold", + &bq->cfg->ac_ovp_th); + if (ret) { + bq_err("failed to read ac-ovp-threshold\n"); + return ret; + } + + /*ret = of_property_read_u32(np, "ti,bq2597x,sense-resistor-mohm", + &bq->cfg->sense_r_mohm); + if (ret) { + bq_err("failed to read sense-resistor-mohm\n"); + return ret; + }*/ + + return 0; +} + +static int bq2597x_init_protection(struct bq2597x *bq) +{ + int ret; + + ret = bq2597x_enable_batovp(bq, !bq->cfg->bat_ovp_disable); + bq_info("%s bat ovp %s\n", + bq->cfg->bat_ovp_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_batocp(bq, !bq->cfg->bat_ocp_disable); + bq_info("%s bat ocp %s\n", + bq->cfg->bat_ocp_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_batovp_alarm(bq, !bq->cfg->bat_ovp_alm_disable); + bq_info("%s bat ovp alarm %s\n", + bq->cfg->bat_ovp_alm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_batocp_alarm(bq, !bq->cfg->bat_ocp_alm_disable); + bq_info("%s bat ocp alarm %s\n", + bq->cfg->bat_ocp_alm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_batucp_alarm(bq, !bq->cfg->bat_ucp_alm_disable); + bq_info("%s bat ocp alarm %s\n", + bq->cfg->bat_ucp_alm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_busovp_alarm(bq, !bq->cfg->bus_ovp_alm_disable); + bq_info("%s bus ovp alarm %s\n", + bq->cfg->bus_ovp_alm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_busocp(bq, !bq->cfg->bus_ocp_disable); + bq_info("%s bus ocp %s\n", + bq->cfg->bus_ocp_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_busocp_alarm(bq, !bq->cfg->bus_ocp_alm_disable); + bq_info("%s bus ocp alarm %s\n", + bq->cfg->bus_ocp_alm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_bat_therm(bq, !bq->cfg->bat_therm_disable); + bq_info("%s bat therm %s\n", + bq->cfg->bat_therm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_bus_therm(bq, !bq->cfg->bus_therm_disable); + bq_info("%s bus therm %s\n", + bq->cfg->bus_therm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_enable_die_therm(bq, !bq->cfg->die_therm_disable); + bq_info("%s die therm %s\n", + bq->cfg->die_therm_disable ? "disable" : "enable", + !ret ? "successfullly" : "failed"); + + ret = bq2597x_set_batovp_th(bq, bq->cfg->bat_ovp_th); + bq_info("set bat ovp th %d %s\n", bq->cfg->bat_ovp_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_batovp_alarm_th(bq, bq->cfg->bat_ovp_alm_th); + bq_info("set bat ovp alarm threshold %d %s\n", bq->cfg->bat_ovp_alm_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_batocp_th(bq, bq->cfg->bat_ocp_th); + bq_info("set bat ocp threshold %d %s\n", bq->cfg->bat_ocp_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_batocp_alarm_th(bq, bq->cfg->bat_ocp_alm_th); + bq_info("set bat ocp alarm threshold %d %s\n", bq->cfg->bat_ocp_alm_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_busovp_th(bq, bq->cfg->bus_ovp_th); + bq_info("set bus ovp threshold %d %s\n", bq->cfg->bus_ovp_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_busovp_alarm_th(bq, bq->cfg->bus_ovp_alm_th); + bq_info("set bus ovp alarm threshold %d %s\n", bq->cfg->bus_ovp_alm_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_busocp_th(bq, bq->cfg->bus_ocp_th); + bq_info("set bus ocp threshold %d %s\n", bq->cfg->bus_ocp_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_busocp_alarm_th(bq, bq->cfg->bus_ocp_alm_th); + bq_info("set bus ocp alarm th %d %s\n", bq->cfg->bus_ocp_alm_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_batucp_alarm_th(bq, bq->cfg->bat_ucp_alm_th); + bq_info("set bat ucp threshold %d %s\n", bq->cfg->bat_ucp_alm_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_bat_therm_th(bq, bq->cfg->bat_therm_th); + bq_info("set die therm threshold %d %s\n", bq->cfg->bat_therm_th, + !ret ? "successfully" : "failed"); + ret = bq2597x_set_bus_therm_th(bq, bq->cfg->bus_therm_th); + bq_info("set bus therm threshold %d %s\n", bq->cfg->bus_therm_th, + !ret ? "successfully" : "failed"); + ret = bq2597x_set_die_therm_th(bq, bq->cfg->die_therm_th); + bq_info("set die therm threshold %d %s\n", bq->cfg->die_therm_th, + !ret ? "successfully" : "failed"); + + ret = bq2597x_set_acovp_th(bq, bq->cfg->ac_ovp_th); + bq_info("set ac ovp threshold %d %s\n", bq->cfg->ac_ovp_th, + !ret ? "successfully" : "failed"); + + return 0; +} + +static int bq2597x_set_bus_protection(struct bq2597x *bq, int hvdcp3_type) +{ + /* just return now, to do later */ + //return 0; + + pr_err("hvdcp3_type: %d\n", hvdcp3_type); + if (hvdcp3_type == HVDCP3_CLASSA_18W) { + bq2597x_set_busovp_th(bq, BUS_OVP_FOR_QC); + bq2597x_set_busovp_alarm_th(bq, BUS_OVP_ALARM_FOR_QC); + bq2597x_set_busocp_th(bq, BUS_OCP_FOR_QC_CLASS_A); + bq2597x_set_busocp_alarm_th(bq, BUS_OCP_ALARM_FOR_QC_CLASS_A); + } else if (hvdcp3_type == HVDCP3_CLASSB_27W) { + bq2597x_set_busovp_th(bq, BUS_OVP_FOR_QC); + bq2597x_set_busovp_alarm_th(bq, BUS_OVP_ALARM_FOR_QC); + bq2597x_set_busocp_th(bq, BUS_OCP_FOR_QC_CLASS_B); + bq2597x_set_busocp_alarm_th(bq, BUS_OCP_ALARM_FOR_QC_CLASS_B); + } else if (hvdcp3_type == HVDCP3P5_CLASSA_18W) { + bq2597x_set_busovp_th(bq, BUS_OVP_FOR_QC); + bq2597x_set_busovp_alarm_th(bq, BUS_OVP_ALARM_FOR_QC); + bq2597x_set_busocp_th(bq, BUS_OCP_FOR_QC3P5_CLASS_A); + bq2597x_set_busocp_alarm_th(bq, + BUS_OCP_ALARM_FOR_QC3P5_CLASS_A); + } else if (hvdcp3_type == HVDCP3P5_CLASSB_27W) { + bq2597x_set_busovp_th(bq, BUS_OVP_FOR_QC); + bq2597x_set_busovp_alarm_th(bq, BUS_OVP_ALARM_FOR_QC); + bq2597x_set_busocp_th(bq, BUS_OCP_FOR_QC3P5_CLASS_B); + bq2597x_set_busocp_alarm_th(bq, + BUS_OCP_ALARM_FOR_QC3P5_CLASS_B); + } else { + bq2597x_set_busovp_th(bq, bq->cfg->bus_ovp_th); + bq2597x_set_busovp_alarm_th(bq, bq->cfg->bus_ovp_alm_th); + bq2597x_set_busocp_th(bq, bq->cfg->bus_ocp_th); + bq2597x_set_busocp_alarm_th(bq, bq->cfg->bus_ocp_alm_th); + } + return 0; +} + +static int bq2597x_init_adc(struct bq2597x *bq) +{ + bq2597x_set_adc_scanrate(bq, false); + bq2597x_set_adc_bits(bq, 13); + bq2597x_set_adc_average(bq, true); + bq2597x_set_adc_scan(bq, ADC_IBUS, true); + bq2597x_set_adc_scan(bq, ADC_VBUS, true); + bq2597x_set_adc_scan(bq, ADC_VOUT, false); + bq2597x_set_adc_scan(bq, ADC_VBAT, true); + bq2597x_set_adc_scan(bq, ADC_IBAT, false); + bq2597x_set_adc_scan(bq, ADC_TBUS, false); + bq2597x_set_adc_scan(bq, ADC_TBAT, false); + bq2597x_set_adc_scan(bq, ADC_TDIE, false); + bq2597x_set_adc_scan(bq, ADC_VAC, true); + + bq2597x_enable_adc(bq, true); + + return 0; +} + +static int bq2597x_init_int_src(struct bq2597x *bq) +{ + int ret; + /*TODO:be careful ts bus and ts bat alarm bit mask is in + * fault mask register, so you need call + * bq2597x_set_fault_int_mask for tsbus and tsbat alarm + */ + ret = bq2597x_set_alarm_int_mask( + bq, ADC_DONE | BAT_OCP_ALARM | BAT_UCP_ALARM | BAT_OVP_ALARM); + if (ret) { + bq_err("failed to set alarm mask:%d\n", ret); + return ret; + } + //#if 0 + ret = bq2597x_set_fault_int_mask( + bq, TS_BUS_FAULT | TS_DIE_FAULT | TS_BAT_FAULT | BAT_OCP_FAULT); + if (ret) { + bq_err("failed to set fault mask:%d\n", ret); + return ret; + } + //#endif + return ret; +} + +static int bq2597x_init_regulation(struct bq2597x *bq) +{ + bq2597x_set_ibat_reg_th(bq, 200); + bq2597x_set_vbat_reg_th(bq, 50); + + bq2597x_set_vdrop_deglitch(bq, 5000); + bq2597x_set_vdrop_th(bq, 400); + + bq2597x_enable_regulation(bq, true); + + return 0; +} + +static int bq2597x_init_device(struct bq2597x *bq) +{ + bq2597x_enable_wdt(bq, false); + + bq2597x_set_ss_timeout(bq, 100000); + bq2597x_set_ibus_ucp_thr(bq, 300); + bq2597x_set_sense_resistor(bq, bq->cfg->sense_r_mohm); + + bq2597x_init_protection(bq); + bq2597x_init_adc(bq); + bq2597x_init_int_src(bq); + + bq2597x_init_regulation(bq); + + return 0; +} + +static int bq2597x_set_present(struct bq2597x *bq, bool present) +{ + bq->usb_present = present; + + if (present) + bq2597x_init_device(bq); + return 0; +} + +static ssize_t bq2597x_show_registers(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct bq2597x *bq = dev_get_drvdata(dev); + u8 addr; + u8 val; + u8 tmpbuf[300]; + int len; + int idx = 0; + int ret; + + idx = snprintf(buf, PAGE_SIZE, "%s:\n", "bq25970"); + for (addr = 0x0; addr <= 0x2A; addr++) { + ret = bq2597x_read_byte(bq, addr, &val); + if (ret == 0) { + len = snprintf(tmpbuf, PAGE_SIZE - idx, + "Reg[%.2X] = 0x%.2x\n", addr, val); + memcpy(&buf[idx], tmpbuf, len); + idx += len; + } + } + + return idx; +} + +static ssize_t bq2597x_store_register(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct bq2597x *bq = dev_get_drvdata(dev); + int ret; + unsigned int reg; + unsigned int val; + + ret = sscanf(buf, "%x %x", ®, &val); + if (ret == 2 && reg <= 0x2A) + bq2597x_write_byte(bq, (unsigned char)reg, (unsigned char)val); + + return count; +} + +static DEVICE_ATTR(registers, 0660, bq2597x_show_registers, + bq2597x_store_register); + +static struct attribute *bq2597x_attributes[] = { + &dev_attr_registers.attr, + NULL, +}; + +static const struct attribute_group bq2597x_attr_group = { + .attrs = bq2597x_attributes, +}; + +static enum power_supply_property bq2597x_charger_props[] = { + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_CHARGING_ENABLED, + POWER_SUPPLY_PROP_STATUS, + + POWER_SUPPLY_PROP_TI_BATTERY_PRESENT, + POWER_SUPPLY_PROP_TI_VBUS_PRESENT, + POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, + POWER_SUPPLY_PROP_TI_BATTERY_CURRENT, + POWER_SUPPLY_PROP_TI_BATTERY_TEMPERATURE, + POWER_SUPPLY_PROP_TI_BUS_VOLTAGE, + POWER_SUPPLY_PROP_TI_BUS_CURRENT, + POWER_SUPPLY_PROP_TI_BUS_TEMPERATURE, + POWER_SUPPLY_PROP_TI_DIE_TEMPERATURE, + POWER_SUPPLY_PROP_TI_ALARM_STATUS, + POWER_SUPPLY_PROP_TI_FAULT_STATUS, + POWER_SUPPLY_PROP_TI_REG_STATUS, + POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3, + POWER_SUPPLY_PROP_MODEL_NAME, +}; + +static void bq2597x_check_alarm_status(struct bq2597x *bq); +static void bq2597x_check_fault_status(struct bq2597x *bq); +static int bq2597x_check_vbus_error_status(struct bq2597x *bq); + +static int bq2597x_charger_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct bq2597x *bq = power_supply_get_drvdata(psy); + int result; + int ret; + u8 reg_val; + + switch (psp) { + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + bq2597x_check_charge_enabled(bq, &bq->charge_enabled); + val->intval = bq->charge_enabled; + break; + case POWER_SUPPLY_PROP_STATUS: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = bq->usb_present; + break; + case POWER_SUPPLY_PROP_TI_BATTERY_PRESENT: + ret = bq2597x_read_byte(bq, BQ2597X_REG_0D, ®_val); + if (!ret) + bq->batt_present = !!(reg_val & VBAT_INSERT); + val->intval = bq->batt_present; + break; + case POWER_SUPPLY_PROP_TI_VBUS_PRESENT: + ret = bq2597x_read_byte(bq, BQ2597X_REG_0D, ®_val); + if (!ret) + bq->vbus_present = !!(reg_val & VBUS_INSERT); + val->intval = bq->vbus_present; + break; + case POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE: + ret = bq2597x_get_adc_data(bq, ADC_VBAT, &result); + if (!ret) + bq->vbat_volt = result; + + val->intval = bq->vbat_volt; + break; + case POWER_SUPPLY_PROP_TI_BATTERY_CURRENT: + ret = bq2597x_get_adc_data(bq, ADC_IBAT, &result); + if (!ret) + bq->ibat_curr = result; + + val->intval = bq->ibat_curr; + break; + case POWER_SUPPLY_PROP_TI_BATTERY_TEMPERATURE: + ret = bq2597x_get_adc_data(bq, ADC_TBAT, &result); + if (!ret) + bq->bat_temp = result; + + val->intval = bq->bat_temp; + break; + case POWER_SUPPLY_PROP_TI_BUS_VOLTAGE: + ret = bq2597x_get_adc_data(bq, ADC_VBUS, &result); + if (!ret) + bq->vbus_volt = result; + + val->intval = bq->vbus_volt; + break; + case POWER_SUPPLY_PROP_TI_BUS_CURRENT: + ret = bq2597x_get_adc_data(bq, ADC_IBUS, &result); + if (!ret) + bq->ibus_curr = result; + + val->intval = bq->ibus_curr; + break; + case POWER_SUPPLY_PROP_TI_BUS_TEMPERATURE: + ret = bq2597x_get_adc_data(bq, ADC_TBUS, &result); + if (!ret) + bq->bus_temp = result; + + val->intval = bq->bus_temp; + break; + case POWER_SUPPLY_PROP_TI_DIE_TEMPERATURE: + ret = bq2597x_get_adc_data(bq, ADC_TDIE, &result); + if (!ret) + bq->die_temp = result; + + val->intval = bq->die_temp; + break; + case POWER_SUPPLY_PROP_TI_ALARM_STATUS: + + bq2597x_check_alarm_status(bq); + + val->intval = ((bq->bat_ovp_alarm << BAT_OVP_ALARM_SHIFT) | + (bq->bat_ocp_alarm << BAT_OCP_ALARM_SHIFT) | + (bq->bat_ucp_alarm << BAT_UCP_ALARM_SHIFT) | + (bq->bus_ovp_alarm << BUS_OVP_ALARM_SHIFT) | + (bq->bus_ocp_alarm << BUS_OCP_ALARM_SHIFT) | + (bq->bat_therm_alarm << BAT_THERM_ALARM_SHIFT) | + (bq->bus_therm_alarm << BUS_THERM_ALARM_SHIFT) | + (bq->die_therm_alarm << DIE_THERM_ALARM_SHIFT)); + break; + + case POWER_SUPPLY_PROP_TI_FAULT_STATUS: + bq2597x_check_fault_status(bq); + + val->intval = ((bq->bat_ovp_fault << BAT_OVP_FAULT_SHIFT) | + (bq->bat_ocp_fault << BAT_OCP_FAULT_SHIFT) | + (bq->bus_ovp_fault << BUS_OVP_FAULT_SHIFT) | + (bq->bus_ocp_fault << BUS_OCP_FAULT_SHIFT) | + (bq->bat_therm_fault << BAT_THERM_FAULT_SHIFT) | + (bq->bus_therm_fault << BUS_THERM_FAULT_SHIFT) | + (bq->die_therm_fault << DIE_THERM_FAULT_SHIFT)); + break; + + case POWER_SUPPLY_PROP_TI_REG_STATUS: + bq2597x_check_reg_status(bq); + val->intval = (bq->vbat_reg << VBAT_REG_STATUS_SHIFT) | + (bq->ibat_reg << IBAT_REG_STATUS_SHIFT); + break; + case POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_MODEL_NAME: + ret = bq2597x_get_work_mode(bq, &bq->mode); + if (ret) { + val->strval = "unknown"; + } else { + if (bq->mode == BQ25970_ROLE_MASTER) + val->strval = "bq2597x-master"; + else if (bq->mode == BQ25970_ROLE_SLAVE) + val->strval = "bq2597x-slave"; + else + val->strval = "bq2597x-standalone"; + } + break; + case POWER_SUPPLY_PROP_TI_BUS_ERROR_STATUS: + val->intval = bq2597x_check_vbus_error_status(bq); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int bq2597x_charger_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + struct bq2597x *bq = power_supply_get_drvdata(psy); + + switch (prop) { + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + bq2597x_enable_charge(bq, val->intval); + bq2597x_check_charge_enabled(bq, &bq->charge_enabled); + bq_info("POWER_SUPPLY_PROP_CHARGING_ENABLED: %s\n", + val->intval ? "enable" : "disable"); + break; + case POWER_SUPPLY_PROP_PRESENT: + bq2597x_set_present(bq, !!val->intval); + break; + case POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3: + bq2597x_set_bus_protection(bq, val->intval); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int bq2597x_check_vbus_error_status(struct bq2597x *bq) +{ + int ret; + u8 stat = 0; + + ret = bq2597x_read_byte(bq, BQ2597X_REG_0A, &stat); + if (!ret) { + bq_info("BQ2597X_REG_0A:0x%02x\n", stat); + if (stat & VBUS_ERROR_LOW_MASK) + return VBUS_ERROR_LOW; + else if (stat & VBUS_ERROR_HIGH_MASK) + return VBUS_ERROR_HIGH; + } + + return VBUS_ERROR_NONE; +} + +static int bq2597x_charger_is_writeable(struct power_supply *psy, + enum power_supply_property prop) +{ + int ret; + + switch (prop) { + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + case POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3: + ret = 1; + break; + default: + ret = 0; + break; + } + return ret; +} + +static int bq2597x_psy_register(struct bq2597x *bq) +{ + int ret; + + bq->psy_cfg.drv_data = bq; + bq->psy_cfg.of_node = bq->dev->of_node; + + if (bq->mode == BQ25970_ROLE_MASTER) + bq->psy_desc.name = "bq2597x-master"; + else if (bq->mode == BQ25970_ROLE_SLAVE) + bq->psy_desc.name = "bq2597x-slave"; + else + bq->psy_desc.name = "bq2597x-standalone"; + + bq->psy_desc.type = POWER_SUPPLY_TYPE_MAINS; + bq->psy_desc.properties = bq2597x_charger_props; + bq->psy_desc.num_properties = ARRAY_SIZE(bq2597x_charger_props); + bq->psy_desc.get_property = bq2597x_charger_get_property; + bq->psy_desc.set_property = bq2597x_charger_set_property; + bq->psy_desc.property_is_writeable = bq2597x_charger_is_writeable; + + bq->fc2_psy = devm_power_supply_register(bq->dev, &bq->psy_desc, + &bq->psy_cfg); + if (IS_ERR(bq->fc2_psy)) { + bq_err("failed to register fc2_psy:%d\n", ret); + return PTR_ERR(bq->fc2_psy); + } + + bq_info("%s power supply register successfully\n", bq->psy_desc.name); + + return 0; +} + +static void bq2597x_dump_reg(struct bq2597x *bq) +{ + int ret; + u8 val; + u8 addr; + if (bq_debug_flag) { + for (addr = 0x00; addr <= 0x2B; addr++) { + ret = bq2597x_read_byte(bq, addr, &val); + if (!ret) + bq_err("Reg[%02X] = 0x%02X\n", addr, val); + } + } +} +EXPORT_SYMBOL_GPL(bq2597x_dump_reg); + +static void bq2597x_check_alarm_status(struct bq2597x *bq) +{ + int ret; + u8 flag = 0; + u8 stat = 0; + + mutex_lock(&bq->data_lock); + + ret = bq2597x_read_byte(bq, BQ2597X_REG_08, &flag); + if (!ret && (flag & BQ2597X_IBUS_UCP_FALL_FLAG_MASK)) + bq_info("UCP_FLAG =0x%02X\n", + !!(flag & BQ2597X_IBUS_UCP_FALL_FLAG_MASK)); + + ret = bq2597x_read_byte(bq, BQ2597X_REG_2D, &flag); + if (!ret && (flag & BQ2597X_VDROP_OVP_FLAG_MASK)) + bq_info("VDROP_OVP_FLAG =0x%02X\n", + !!(flag & BQ2597X_VDROP_OVP_FLAG_MASK)); + + /*read to clear alarm flag*/ + ret = bq2597x_read_byte(bq, BQ2597X_REG_0E, &flag); + if (!ret && flag) + bq_info("INT_FLAG =0x%02X\n", flag); + + ret = bq2597x_read_byte(bq, BQ2597X_REG_0D, &stat); + if (!ret && stat != bq->prev_alarm) { + bq_info("INT_STAT = 0X%02x\n", stat); + bq->prev_alarm = stat; + bq->bat_ovp_alarm = !!(stat & BAT_OVP_ALARM); + bq->bat_ocp_alarm = !!(stat & BAT_OCP_ALARM); + bq->bus_ovp_alarm = !!(stat & BUS_OVP_ALARM); + bq->bus_ocp_alarm = !!(stat & BUS_OCP_ALARM); + bq->batt_present = !!(stat & VBAT_INSERT); + bq->vbus_present = !!(stat & VBUS_INSERT); + bq->bat_ucp_alarm = !!(stat & BAT_UCP_ALARM); + } + + ret = bq2597x_read_byte(bq, BQ2597X_REG_08, &stat); + if (!ret && (stat & 0x50)) + bq_err("Reg[08]BUS_UCPOVP = 0x%02X\n", stat); + + ret = bq2597x_read_byte(bq, BQ2597X_REG_0A, &stat); + if (!ret && (stat & 0x02)) + bq_err("Reg[0A]CONV_OCP = 0x%02X\n", stat); + + mutex_unlock(&bq->data_lock); +} + +static void bq2597x_check_fault_status(struct bq2597x *bq) +{ + int ret; + u8 flag = 0; + u8 stat = 0; + bool changed = false; + + mutex_lock(&bq->data_lock); + + ret = bq2597x_read_byte(bq, BQ2597X_REG_10, &stat); + if (!ret && stat) + bq_err("FAULT_STAT = 0x%02X\n", stat); + + ret = bq2597x_read_byte(bq, BQ2597X_REG_11, &flag); + if (!ret && flag) + bq_err("FAULT_FLAG = 0x%02X\n", flag); + + if (!ret && flag != bq->prev_fault) { + changed = true; + bq->prev_fault = flag; + bq->bat_ovp_fault = !!(flag & BAT_OVP_FAULT); + bq->bat_ocp_fault = !!(flag & BAT_OCP_FAULT); + bq->bus_ovp_fault = !!(flag & BUS_OVP_FAULT); + bq->bus_ocp_fault = !!(flag & BUS_OCP_FAULT); + bq->bat_therm_fault = !!(flag & TS_BAT_FAULT); + bq->bus_therm_fault = !!(flag & TS_BUS_FAULT); + + bq->bat_therm_alarm = !!(flag & TBUS_TBAT_ALARM); + bq->bus_therm_alarm = !!(flag & TBUS_TBAT_ALARM); + } + + mutex_unlock(&bq->data_lock); +} + +static void bq2597x_charger_info(struct bq2597x *bq) +{ + int vbat, vbus, ibus; + + bq2597x_get_adc_data(bq, ADC_VBAT, &vbat); + bq2597x_get_adc_data(bq, ADC_VBUS, &vbus); + bq2597x_get_adc_data(bq, ADC_IBUS, &ibus); + bq_info("charger info: vbat(%d), vbus(%d), ibus(%d)\n", vbat, vbus, + ibus); +} + +/* + * interrupt does nothing, just info event chagne, other module could get info + * through power supply interface + */ +static irqreturn_t bq2597x_charger_interrupt(int irq, void *dev_id) +{ + struct bq2597x *bq = dev_id; + + bq_info("INT OCCURED\n"); + mutex_lock(&bq->irq_complete); + bq->irq_waiting = true; + if (!bq->resume_completed) { + dev_dbg(bq->dev, "IRQ triggered before device-resume\n"); + if (!bq->irq_disabled) { + disable_irq_nosync(irq); + bq->irq_disabled = true; + } + mutex_unlock(&bq->irq_complete); + return IRQ_HANDLED; + } + bq->irq_waiting = false; + + /* TODO */ + bq2597x_check_alarm_status(bq); + bq2597x_check_fault_status(bq); + + bq2597x_charger_info(bq); + bq2597x_dump_reg(bq); + mutex_unlock(&bq->irq_complete); + power_supply_changed(bq->fc2_psy); + + return IRQ_HANDLED; +} + +static void determine_initial_status(struct bq2597x *bq) +{ + if (bq->client->irq) + bq2597x_charger_interrupt(bq->client->irq, bq); +} + +static int show_registers(struct seq_file *m, void *data) +{ + struct bq2597x *bq = m->private; + u8 addr; + int ret; + u8 val; + + for (addr = 0x0; addr <= 0x2B; addr++) { + ret = bq2597x_read_byte(bq, addr, &val); + if (!ret) + seq_printf(m, "Reg[%02X] = 0x%02X\n", addr, val); + } + return 0; +} + +static int reg_debugfs_open(struct inode *inode, struct file *file) +{ + struct bq2597x *bq = inode->i_private; + + return single_open(file, show_registers, bq); +} + +static const struct file_operations reg_debugfs_ops = { + .owner = THIS_MODULE, + .open = reg_debugfs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void create_debugfs_entry(struct bq2597x *bq) +{ + if (bq->mode == BQ25970_ROLE_MASTER) + bq->debug_root = debugfs_create_dir("bq2597x-master", NULL); + else if (bq->mode == BQ25970_ROLE_SLAVE) + bq->debug_root = debugfs_create_dir("bq2597x-slave", NULL); + else + bq->debug_root = debugfs_create_dir("bq2597x-standalone", NULL); + + if (!bq->debug_root) + bq_err("Failed to create debug dir\n"); + + if (bq->debug_root) { + debugfs_create_file("registers", S_IFREG | S_IRUGO, + bq->debug_root, bq, ®_debugfs_ops); + + debugfs_create_x32("skip_reads", S_IFREG | S_IWUSR | S_IRUGO, + bq->debug_root, &(bq->skip_reads)); + debugfs_create_x32("skip_writes", S_IFREG | S_IWUSR | S_IRUGO, + bq->debug_root, &(bq->skip_writes)); + } +} + +static struct of_device_id bq2597x_charger_match_table[] = { + { + .compatible = "ti,bq2597x-standalone", + .data = &bq2597x_mode_data[BQ25970_STDALONE], + }, + { + .compatible = "ti,bq2597x-master", + .data = &bq2597x_mode_data[BQ25970_MASTER], + }, + + { + .compatible = "ti,bq2597x-slave", + .data = &bq2597x_mode_data[BQ25970_SLAVE], + }, + {}, +}; +//MODULE_DEVICE_TABLE(of, bq2597x_charger_match_table); + +static int bq2597x_charger_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct bq2597x *bq; + const struct of_device_id *match; + struct device_node *node = client->dev.of_node; + int ret; + + bq = devm_kzalloc(&client->dev, sizeof(struct bq2597x), GFP_KERNEL); + if (!bq) + return -ENOMEM; + + bq->dev = &client->dev; + + bq->client = client; + i2c_set_clientdata(client, bq); + + mutex_init(&bq->i2c_rw_lock); + mutex_init(&bq->data_lock); + mutex_init(&bq->charging_disable_lock); + mutex_init(&bq->irq_complete); + + bq->resume_completed = true; + bq->irq_waiting = false; + + ret = bq2597x_detect_device(bq); + if (ret) { + bq_err("No bq2597x device found!\n"); + return -ENODEV; + } + + match = of_match_node(bq2597x_charger_match_table, node); + if (match == NULL) { + bq_err("device tree match not found!\n"); + return -ENODEV; + } + + bq2597x_get_work_mode(bq, &bq->mode); + + if (bq->mode != *(int *)match->data) { + bq_err("device operation mode mismatch with dts configuration\n"); + return -EINVAL; + } + + ret = bq2597x_parse_dt(bq, &client->dev); + if (ret) + return -EIO; + + ret = bq2597x_init_device(bq); + if (ret) { + bq_err("Failed to init device\n"); + return ret; + } + + ret = bq2597x_psy_register(bq); + if (ret) + return ret; + + if (client->irq) { + ret = devm_request_threaded_irq(&client->dev, client->irq, NULL, + bq2597x_charger_interrupt, + IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, + "bq2597x charger irq", bq); + if (ret < 0) { + bq_err("request irq for irq=%d failed, ret =%d\n", + client->irq, ret); + goto err_1; + } + enable_irq_wake(client->irq); + } + + INIT_DELAYED_WORK(&bq->monitor_work, bq2597x_monitor_work); + device_init_wakeup(bq->dev, 1); + create_debugfs_entry(bq); + + ret = sysfs_create_group(&bq->dev->kobj, &bq2597x_attr_group); + if (ret) { + bq_err("failed to register sysfs. err: %d\n", ret); + goto err_1; + } + + determine_initial_status(bq); + /* schedule_delayed_work(&bq->monitor_work, 60 * HZ); */ + bq_info("bq2597x probe successfully, Part Num:%d\n!", bq->part_no); + + return 0; + +err_1: + power_supply_unregister(bq->fc2_psy); + return ret; +} + +static inline bool is_device_suspended(struct bq2597x *bq) +{ + return !bq->resume_completed; +} + +static int bq2597x_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq2597x *bq = i2c_get_clientdata(client); + + mutex_lock(&bq->irq_complete); + bq->resume_completed = false; + mutex_unlock(&bq->irq_complete); + bq2597x_enable_adc(bq, false); + cancel_delayed_work_sync(&bq->monitor_work); + bq_err("Suspend successfully!"); + + return 0; +} + +static int bq2597x_suspend_noirq(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq2597x *bq = i2c_get_clientdata(client); + + if (bq->irq_waiting) { + pr_err_ratelimited( + "Aborting suspend, an interrupt was detected while suspending\n"); + return -EBUSY; + } + return 0; +} + +static int bq2597x_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq2597x *bq = i2c_get_clientdata(client); + + mutex_lock(&bq->irq_complete); + bq->resume_completed = true; + if (bq->irq_waiting) { + bq->irq_disabled = false; + enable_irq(client->irq); + mutex_unlock(&bq->irq_complete); + bq2597x_charger_interrupt(client->irq, bq); + } else { + mutex_unlock(&bq->irq_complete); + } + + bq2597x_enable_adc(bq, true); + power_supply_changed(bq->fc2_psy); + bq_err("Resume successfully!"); + + return 0; +} +static int bq2597x_charger_remove(struct i2c_client *client) +{ + struct bq2597x *bq = i2c_get_clientdata(client); + + bq2597x_enable_adc(bq, false); + + power_supply_unregister(bq->fc2_psy); + + mutex_destroy(&bq->charging_disable_lock); + mutex_destroy(&bq->data_lock); + mutex_destroy(&bq->i2c_rw_lock); + mutex_destroy(&bq->irq_complete); + + debugfs_remove_recursive(bq->debug_root); + + sysfs_remove_group(&bq->dev->kobj, &bq2597x_attr_group); + + return 0; +} + +static void bq2597x_charger_shutdown(struct i2c_client *client) +{ + struct bq2597x *bq = i2c_get_clientdata(client); + + bq2597x_enable_adc(bq, false); +} + +static const struct dev_pm_ops bq2597x_pm_ops = { + .resume = bq2597x_resume, + .suspend_noirq = bq2597x_suspend_noirq, + .suspend = bq2597x_suspend, +}; + +static const struct i2c_device_id bq2597x_charger_id[] = { + { "bq2597x-standalone", BQ25970_ROLE_STDALONE }, + { "bq2597x-master", BQ25970_ROLE_MASTER }, + { "bq2597x-slave", BQ25970_ROLE_SLAVE }, + {}, +}; + +static struct i2c_driver bq2597x_charger_driver = { + .driver = { + .name = "bq2597x-charger", + .owner = THIS_MODULE, + .of_match_table = bq2597x_charger_match_table, + .pm = &bq2597x_pm_ops, + }, + .id_table = bq2597x_charger_id, + + .probe = bq2597x_charger_probe, + .remove = bq2597x_charger_remove, + .shutdown = bq2597x_charger_shutdown, +}; + +module_i2c_driver(bq2597x_charger_driver); + +MODULE_DESCRIPTION("TI BQ2597x Charger Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Texas Instruments"); diff --git a/drivers/power/supply/ti/bq27z561_fg.c b/drivers/power/supply/ti/bq27z561_fg.c new file mode 100644 index 000000000000..f713af276273 --- /dev/null +++ b/drivers/power/supply/ti/bq27z561_fg.c @@ -0,0 +1,2134 @@ +/* + * bq27z561 fuel gauge driver + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define pr_fmt(fmt) "[bq27z561] %s: " fmt, __func__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum print_reason { + PR_INTERRUPT = BIT(0), + PR_REGISTER = BIT(1), + PR_OEM = BIT(2), + PR_DEBUG = BIT(3), +}; + +static int debug_mask = PR_OEM; +module_param_named(debug_mask, debug_mask, int, 0600); + +#define INVALID_REG_ADDR 0xFF + +#define FG_FLAGS_FD BIT(4) +#define FG_FLAGS_FC BIT(5) +#define FG_FLAGS_DSG BIT(6) +#define FG_FLAGS_RCA BIT(9) +#define FG_FLAGS_FASTCHAGE BIT(5) + +#define BATTERY_DIGEST_LEN 32 + +#define DEFUALT_FULL_DESIGN 100000 + +#define BQ_REPORT_FULL_SOC 9800 +#define BQ_CHARGE_FULL_SOC 9750 +#define BQ_RECHARGE_SOC 9900 + +#define PD_CHG_UPDATE_DELAY_US 20 /*20 sec*/ + +enum bq_fg_reg_idx { + BQ_FG_REG_CTRL = 0, + BQ_FG_REG_TEMP, /* Battery Temperature */ + BQ_FG_REG_VOLT, /* Battery Voltage */ + BQ_FG_REG_CN, /* Current Now */ + BQ_FG_REG_AI, /* Average Current */ + BQ_FG_REG_BATT_STATUS, /* BatteryStatus */ + BQ_FG_REG_TTE, /* Time to Empty */ + BQ_FG_REG_TTF, /* Time to Full */ + BQ_FG_REG_FCC, /* Full Charge Capacity */ + BQ_FG_REG_RM, /* Remaining Capacity */ + BQ_FG_REG_CC, /* Cycle Count */ + BQ_FG_REG_SOC, /* Relative State of Charge */ + BQ_FG_REG_SOH, /* State of Health */ + BQ_FG_REG_CHG_VOL, /* Charging Voltage*/ + BQ_FG_REG_CHG_CUR, /* Charging Current*/ + BQ_FG_REG_DC, /* Design Capacity */ + BQ_FG_REG_ALT_MAC, /* AltManufactureAccess*/ + BQ_FG_REG_MAC_DATA, /* MACData*/ + BQ_FG_REG_MAC_CHKSUM, /* MACChecksum */ + BQ_FG_REG_MAC_DATA_LEN, /* MACDataLen */ + NUM_REGS, +}; + +static u8 bq27z561_regs[NUM_REGS] = { + 0x00, /* CONTROL */ + 0x06, /* TEMP */ + 0x08, /* VOLT */ + 0x0C, /* CURRENT NOW */ + 0x14, /* AVG CURRENT */ + 0x0A, /* FLAGS */ + 0x16, /* Time to empty */ + 0x18, /* Time to full */ + 0x12, /* Full charge capacity */ + 0x10, /* Remaining Capacity */ + 0x2A, /* CycleCount */ + 0x2C, /* State of Charge */ + 0x2E, /* State of Health */ + 0x30, /* Charging Voltage*/ + 0x32, /* Charging Current*/ + 0x3C, /* Design Capacity */ + 0x3E, /* AltManufacturerAccess*/ + 0x40, /* MACData*/ + 0x60, /* MACChecksum */ + 0x61, /* MACDataLen */ +}; + +enum bq_fg_mac_cmd { + FG_MAC_CMD_CTRL_STATUS = 0x0000, + FG_MAC_CMD_DEV_TYPE = 0x0001, + FG_MAC_CMD_FW_VER = 0x0002, + FG_MAC_CMD_HW_VER = 0x0003, + FG_MAC_CMD_IF_SIG = 0x0004, + FG_MAC_CMD_CHEM_ID = 0x0006, + FG_MAC_CMD_GAUGING = 0x0021, + FG_MAC_CMD_SEAL = 0x0030, + FG_MAC_CMD_FASTCHARGE_EN = 0x003E, + FG_MAC_CMD_FASTCHARGE_DIS = 0x003F, + FG_MAC_CMD_DEV_RESET = 0x0041, + FG_MAC_CMD_MANU_NAME = 0x004C, + FG_MAC_CMD_CHARGING_STATUS = 0x0055, + FG_MAC_CMD_ITSTATUS1 = 0x0073, + FG_MAC_CMD_QMAX = 0x0075, + FG_MAC_CMD_RA_TABLE = 0x40C0, +}; + +enum { + SEAL_STATE_RSVED, + SEAL_STATE_UNSEALED, + SEAL_STATE_SEALED, + SEAL_STATE_FA, +}; + +enum bq_fg_device { + BQ27Z561, +}; + +static const unsigned char *device2str[] = { + "bq27z561", +}; + +struct cold_thermal { + int index; + int temp_l; + int temp_h; + int curr_th; +}; + +struct bq_fg_chip { + struct device *dev; + struct i2c_client *client; + struct regmap *regmap; + + struct mutex i2c_rw_lock; + struct mutex data_lock; + + int fw_ver; + int df_ver; + + u8 chip; + u8 regs[NUM_REGS]; + + /* status tracking */ + + bool batt_fc; + bool batt_fd; /* full depleted */ + + bool batt_dsg; + bool batt_rca; /* remaining capacity alarm */ + + int seal_state; /* 0 - Full Access, 1 - Unsealed, 2 - Sealed */ + int batt_tte; + int batt_soc; + int batt_fcc; /* Full charge capacity */ + int batt_rm; /* Remaining capacity */ + int batt_dc; /* Design Capacity */ + int batt_volt; + int batt_temp; + int batt_curr; + int batt_resistance; + int batt_cyclecnt; /* cycle count */ + int batt_st; + + /* debug */ + int skip_reads; + int skip_writes; + + int fake_soc; + int fake_temp; + int fake_volt; + + struct delayed_work monitor_work; + struct power_supply *fg_psy; + struct power_supply *usb_psy; + struct power_supply *batt_psy; + struct power_supply_desc fg_psy_d; + struct timeval suspend_time; + + u8 digest[BATTERY_DIGEST_LEN]; + bool verify_digest_success; + int constant_charge_current_max; + + bool charge_done; + bool charge_full; + int health; + int batt_recharge_vol; + + /* workaround for debug or other purpose */ + bool ignore_digest_for_debug; + bool old_hw; + + int *dec_rate_seq; + int dec_rate_len; + + struct cold_thermal *cold_thermal_seq; + int cold_thermal_len; + bool update_now; + bool fast_mode; +}; + +#define bq_dbg(reason, fmt, ...) \ + do { \ + if (debug_mask & (reason)) \ + pr_info(fmt, ##__VA_ARGS__); \ + else \ + pr_debug(fmt, ##__VA_ARGS__); \ + } while (0) + +static int bq_battery_soc_smooth_tracking(struct bq_fg_chip *chip, int raw_soc, + int soc, int temp, int curr); +static int fg_get_raw_soc(struct bq_fg_chip *bq); +static int fg_read_current(struct bq_fg_chip *bq, int *curr); +static int fg_read_temperature(struct bq_fg_chip *bq); +static int calc_delta_time(struct timeval *time_stamp, int *delta_time); +/* +static int __fg_read_byte(struct i2c_client *client, u8 reg, u8 *val) +{ + s32 ret; + + ret = i2c_smbus_read_byte_data(client, reg); + if (ret < 0) { + bq_dbg(PR_OEM, "i2c read byte fail: can't read from reg 0x%02X\n", reg); + return ret; + } + + *val = (u8)ret; + + return 0; +} +*/ + +static int __fg_write_byte(struct i2c_client *client, u8 reg, u8 val) +{ + s32 ret; + + ret = i2c_smbus_write_byte_data(client, reg, val); + if (ret < 0) { + bq_dbg(PR_REGISTER, + "i2c write byte fail: can't write 0x%02X to reg 0x%02X\n", + val, reg); + return ret; + } + + return 0; +} + +static int __fg_read_word(struct i2c_client *client, u8 reg, u16 *val) +{ + s32 ret; + + ret = i2c_smbus_read_word_data(client, reg); + if (ret < 0) { + bq_dbg(PR_REGISTER, + "i2c read word fail: can't read from reg 0x%02X\n", reg); + return ret; + } + + *val = (u16)ret; + + return 0; +} + +static int __fg_read_block(struct i2c_client *client, u8 reg, u8 *buf, u8 len) +{ + int ret; + int i; + + for (i = 0; i < len; i++) { + ret = i2c_smbus_read_byte_data(client, reg + i); + if (ret < 0) { + bq_dbg(PR_REGISTER, "i2c read reg 0x%02X faild\n", + reg + i); + return ret; + } + buf[i] = ret; + } + + return ret; +} + +static int __fg_write_block(struct i2c_client *client, u8 reg, u8 *buf, u8 len) +{ + int ret; + int i = 0; + + for (i = 0; i < len; i++) { + ret = i2c_smbus_write_byte_data(client, reg + i, buf[i]); + if (ret < 0) { + bq_dbg(PR_REGISTER, "i2c read reg 0x%02X faild\n", + reg + i); + return ret; + } + } + + return ret; +} + +/* +static int fg_read_byte(struct bq_fg_chip *bq, u8 reg, u8 *val) +{ + int ret; + + if (bq->skip_reads) { + *val = 0; + return 0; + } + + mutex_lock(&bq->i2c_rw_lock); + ret = __fg_read_byte(bq->client, reg, val); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} +*/ + +static int fg_write_byte(struct bq_fg_chip *bq, u8 reg, u8 val) +{ + int ret; + + if (bq->skip_writes) + return 0; + + mutex_lock(&bq->i2c_rw_lock); + ret = __fg_write_byte(bq->client, reg, val); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} + +static int fg_read_word(struct bq_fg_chip *bq, u8 reg, u16 *val) +{ + int ret; + + if (bq->skip_reads) { + *val = 0; + return 0; + } + + mutex_lock(&bq->i2c_rw_lock); + ret = __fg_read_word(bq->client, reg, val); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} + +static int fg_read_block(struct bq_fg_chip *bq, u8 reg, u8 *buf, u8 len) +{ + int ret; + + if (bq->skip_reads) + return 0; + mutex_lock(&bq->i2c_rw_lock); + ret = __fg_read_block(bq->client, reg, buf, len); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} + +static int fg_write_block(struct bq_fg_chip *bq, u8 reg, u8 *data, u8 len) +{ + int ret; + + if (bq->skip_writes) + return 0; + + mutex_lock(&bq->i2c_rw_lock); + ret = __fg_write_block(bq->client, reg, data, len); + mutex_unlock(&bq->i2c_rw_lock); + + return ret; +} + +static u8 checksum(u8 *data, u8 len) +{ + u8 i; + u16 sum = 0; + + for (i = 0; i < len; i++) { + sum += data[i]; + } + + sum &= 0xFF; + + return 0xFF - sum; +} + +static void fg_print_buf(const char *msg, u8 *buf, u8 len) +{ + int i; + int idx = 0; + int num; + u8 strbuf[128]; + + bq_dbg(PR_REGISTER, "%s buf: ", msg); + for (i = 0; i < len; i++) { + num = sprintf(&strbuf[idx], "%02X ", buf[i]); + idx += num; + } + bq_dbg(PR_REGISTER, "%s\n", strbuf); +} + +#if 0 +#define TIMEOUT_INIT_COMPLETED 100 +static int fg_check_init_completed(struct bq_fg_chip *bq) +{ + int ret; + int i = 0; + u16 status; + + while (i++ < TIMEOUT_INIT_COMPLETED) { + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_BATT_STATUS], &status); + if (ret >= 0 && (status & 0x0080)) + return 0; + msleep(100); + } + bq_dbg(PR_OEM, "wait for FG INITCOMP timeout\n"); + return ret; +} +#endif + +#if 0 +static int fg_get_seal_state(struct bq_fg_chip *bq) +{ + int ret; + u16 status; + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_CTRL], &status); + if (ret < 0) { + bq_dbg(PR_OEM, "Failed to read control status, ret = %d\n", ret); + return ret; + } + status &= 0x6000; + status >>= 13; + + if (status == 1) + bq->seal_state = SEAL_STATE_FA; + else if (status == 2) + bq->seal_state = SEAL_STATE_UNSEALED; + else if (status == 3) + bq->seal_state = SEAL_STATE_SEALED; + + return 0; +} + +static int fg_unseal_send_key(struct bq_fg_chip *bq, int key) +{ + int ret; + + ret = fg_write_word(bq, bq->regs[BQ_FG_REG_ALT_MAC], key & 0xFFFF); + + if (ret < 0) { + bq_dbg(PR_OEM, "unable to write unseal key step 1, ret = %d\n", ret); + return ret; + } + + msleep(5); + + ret = fg_write_word(bq, bq->regs[BQ_FG_REG_ALT_MAC], (key >> 16) & 0xFFFF); + if (ret < 0) { + bq_dbg(PR_OEM, "unable to write unseal key step 2, ret = %d\n", ret); + return ret; + } + + msleep(100); + + return 0; +} + +#define FG_DEFAULT_UNSEAL_KEY 0x80008000 +static int fg_unseal(struct bq_fg_chip *bq) +{ + int ret; + int retry = 0; + + ret = fg_unseal_send_key(bq, FG_DEFAULT_UNSEAL_KEY); + if (!ret) { + while (retry++ < 100) { + ret = fg_get_seal_state(bq); + if (bq->seal_state == SEAL_STATE_UNSEALED || + bq->seal_state == SEAL_STATE_FA) { + bq_dbg(PR_OEM, "FG is unsealed"); + return 0; + } + } + } + + return -EPERM; +} + +#define FG_DEFAULT_UNSEAL_FA_KEY 0x36724614 +static int fg_unseal_full_access(struct bq_fg_chip *bq) +{ + int ret; + int retry = 0; + + ret = fg_unseal_send_key(bq, FG_DEFAULT_UNSEAL_FA_KEY); + if (!ret) { + while (retry++ < 100) { + fg_get_seal_state(bq); + if (bq->seal_state == SEAL_STATE_FA) { + bq_dbg(PR_OEM, "FG is in full access."); + return 0; + } + msleep(200); + } + } + + return -EPERM; +} + + +static int fg_seal(struct bq_fg_chip *bq) +{ + int ret; + int retry = 0; + + ret = fg_write_word(bq, bq->regs[BQ_FG_REG_ALT_MAC], FG_MAC_CMD_SEAL); + + if (ret < 0) { + bq_dbg(PR_OEM, "Failed to send seal command\n"); + return ret; + } + + while (retry++ < 100) { + fg_get_seal_state(bq); + if (bq->seal_state == SEAL_STATE_SEALED) { + bq_dbg(PR_OEM, "FG is sealed successfully"); + return 0; + } + msleep(200); + } + + return -EPERM; +} +#endif + +static int fg_mac_read_block(struct bq_fg_chip *bq, u16 cmd, u8 *buf, u8 len) +{ + int ret; + u8 cksum_calc, cksum; + u8 t_buf[40]; + u8 t_len; + int i; + + t_buf[0] = (u8)cmd; + t_buf[1] = (u8)(cmd >> 8); + ret = fg_write_block(bq, bq->regs[BQ_FG_REG_ALT_MAC], t_buf, 2); + if (ret < 0) + return ret; + + msleep(4); + + ret = fg_read_block(bq, bq->regs[BQ_FG_REG_ALT_MAC], t_buf, 36); + if (ret < 0) + return ret; + + fg_print_buf("mac_read_block", t_buf, 36); + + cksum = t_buf[34]; + t_len = t_buf[35]; + + cksum_calc = checksum(t_buf, t_len - 2); + if (cksum_calc != cksum) + return 1; + + for (i = 0; i < len; i++) + buf[i] = t_buf[i + 2]; + + return 0; +} + +static int fg_sha256_auth(struct bq_fg_chip *bq, u8 *rand_num, int length) +{ + int ret; + u8 cksum_calc; + u8 t_buf[2]; + + /* + 1. The host writes 0x00 to 0x3E. + 2. The host writes 0x00 to 0x3F + */ + t_buf[0] = 0x00; + t_buf[1] = 0x00; + ret = fg_write_block(bq, bq->regs[BQ_FG_REG_ALT_MAC], t_buf, 2); + if (ret < 0) + return ret; + /* + 3. Write the random challenge should be written in a 32-byte block to address 0x40-0x5F + */ + msleep(2); + + ret = fg_write_block(bq, bq->regs[BQ_FG_REG_MAC_DATA], rand_num, + length); + if (ret < 0) + return ret; + + /*4. Write the checksum (2’s complement sum of (1), (2), and (3)) to address 0x60.*/ + cksum_calc = checksum(rand_num, length); + ret = fg_write_byte(bq, bq->regs[BQ_FG_REG_MAC_CHKSUM], cksum_calc); + if (ret < 0) + return ret; + + /*5. Write the length 0x24 to address 0x61.*/ + ret = fg_write_byte(bq, bq->regs[BQ_FG_REG_MAC_DATA_LEN], 0x24); + if (ret < 0) + return ret; + + msleep(300); + + ret = fg_read_block(bq, bq->regs[BQ_FG_REG_MAC_DATA], bq->digest, + length); + if (ret < 0) + return ret; + + return 0; +} + +static int fg_mac_write_block(struct bq_fg_chip *bq, u16 cmd, u8 *data, u8 len) +{ + int ret; + u8 cksum; + u8 t_buf[40]; + int i; + + if (len > 32) + return -EPERM; + + t_buf[0] = (u8)cmd; + t_buf[1] = (u8)(cmd >> 8); + for (i = 0; i < len; i++) + t_buf[i + 2] = data[i]; + + cksum = checksum(data, len + 2); + /*write command/addr, data*/ + ret = fg_write_block(bq, bq->regs[BQ_FG_REG_ALT_MAC], t_buf, len + 2); + if (ret < 0) + return ret; + t_buf[0] = cksum; + t_buf[1] = len + 4; /*buf length, cmd, CRC and len byte itself*/ + /*write checksum and length*/ + ret = fg_write_block(bq, bq->regs[BQ_FG_REG_MAC_CHKSUM], t_buf, 2); + + return ret; +} +/* +static int fg_get_fastcharge_mode(struct bq_fg_chip *bq) +{ + u8 data[3]; + int ret; + + ret = fg_mac_read_block(bq, FG_MAC_CMD_CHARGING_STATUS, data, 3); + if (ret < 0) { + bq_dbg(PR_OEM, "could not write fastcharge = %d\n", ret); + return ret; + } + + return (data[2] & FG_FLAGS_FASTCHAGE) >> 5; +} +*/ + +static int fg_set_fastcharge_mode(struct bq_fg_chip *bq, bool enable) +{ + u8 data[2]; + int ret; + + data[0] = enable; + + bq_dbg(PR_OEM, "set fastcharge mode: enable: %d\n", enable); + if (enable) { + ret = fg_mac_write_block(bq, FG_MAC_CMD_FASTCHARGE_EN, data, 2); + if (ret < 0) { + bq_dbg(PR_OEM, "could not write fastcharge = %d\n", + ret); + return ret; + } + } else { + ret = fg_mac_write_block(bq, FG_MAC_CMD_FASTCHARGE_DIS, data, + 2); + if (ret < 0) { + bq_dbg(PR_OEM, "could not write fastcharge = %d\n", + ret); + return ret; + } + } + bq->fast_mode = enable; + + return ret; +} + +static int fg_read_status(struct bq_fg_chip *bq) +{ + int ret; + u16 flags; + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_BATT_STATUS], &flags); + if (ret < 0) + return ret; + + bq->batt_fc = !!(flags & FG_FLAGS_FC); + bq->batt_fd = !!(flags & FG_FLAGS_FD); + bq->batt_rca = !!(flags & FG_FLAGS_RCA); + bq->batt_dsg = !!(flags & FG_FLAGS_DSG); + + return 0; +} + +#define TERMINATION 0 +#define TERMINATION_BYTE 6 +#define TERMINATION_BASE 30 +#define TERMINATION_STEP 5 + +#define RECHARGE_VOL 1 +#define RECHARGE_VOL_BYTE 7 +#define RECHARGE_VOL_BASE 4200 +#define RECHARGE_VOL_STEP 5 + +#define FFC_TERMINATION 2 +#define FFC_TERMINATION_BYTE 8 +#define FFC_TERMINATION_BASE 400 +#define FFC_TERMINATION_STEP 20 + +#define MANU_DATA_LEN 3 + +struct manu_data { + int byte; + int base; + int step; + int data; +}; + +struct manu_data manu_info[MANU_DATA_LEN] = { + { TERMINATION_BYTE, TERMINATION_BASE, TERMINATION_STEP }, + { RECHARGE_VOL_BYTE, RECHARGE_VOL_BASE, RECHARGE_VOL_STEP }, + { FFC_TERMINATION_BYTE, FFC_TERMINATION_BASE, FFC_TERMINATION_STEP }, +}; + +static int fg_get_manu_info(unsigned char val, int base, int step) +{ + int index = 0; + int data = 0; + + bq_dbg(PR_OEM, "val:%d, '0':%d, 'A':%d, 'a':%d\n", val, '0', 'A', 'a'); + if (val > '0' && val < '9') + index = val - '0'; + if (val > 'A' && val < 'Z') + index = val - 'A' + 10; + if (val > 'a' && val < 'z') + index = val - 'a' + 36; + + data = base + index * step; + + return data; +} + +static int fg_get_manufacture_data(struct bq_fg_chip *bq) +{ + u8 t_buf[40]; + int ret; + int i; + int byte, base, step; + + ret = fg_mac_read_block(bq, FG_MAC_CMD_MANU_NAME, t_buf, 32); + if (ret < 0) { + bq_dbg(PR_OEM, "failed to get MANE NAME\n"); + if (bq->ignore_digest_for_debug) + bq->old_hw = true; + } + + if (strncmp(t_buf, "MI", 2) != 0) { + bq_dbg(PR_OEM, "maybe not mi battery data\n"); + return 0; + } + + for (i = 0; i < MANU_DATA_LEN; i++) { + byte = manu_info[i].byte; + base = manu_info[i].base; + step = manu_info[i].step; + manu_info[i].data = fg_get_manu_info(t_buf[byte], base, step); + } + + return 0; +} + +static int fg_read_rsoc(struct bq_fg_chip *bq) +{ + static int last_soc; + int soc, ret; + + if (bq->fake_soc > 0) + return bq->fake_soc; + + ret = regmap_read(bq->regmap, bq->regs[BQ_FG_REG_SOC], &soc); + if (ret < 0) { + bq_dbg(PR_OEM, "could not read RSOC, ret = %d\n", ret); + if (!last_soc) + last_soc = 50; + return last_soc; + } + + last_soc = soc; + + return soc; +} + +#define FG_REPORT_FULL_SOC 9600 +#define FG_OPTIMIZ_FULL_TIME 40 + +static int fg_read_system_soc(struct bq_fg_chip *bq) +{ + int soc, curr, temp, raw_soc; + + soc = fg_read_rsoc(bq); + raw_soc = fg_get_raw_soc(bq); + + fg_read_current(bq, &curr); + temp = fg_read_temperature(bq); + + soc = bq_battery_soc_smooth_tracking(bq, raw_soc, soc, temp, curr); + + return soc; +} + +static int fg_read_temperature(struct bq_fg_chip *bq) +{ + int ret; + u16 temp = 0; + static int last_temp; + + if (bq->fake_temp > 0) + return bq->fake_temp; + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_TEMP], &temp); + if (ret < 0) { + bq_dbg(PR_OEM, "could not read temperature, ret = %d\n", ret); + if (!last_temp) + last_temp = 250; + return last_temp; + } + last_temp = temp - 2730; + + return temp - 2730; +} + +static int fg_read_volt(struct bq_fg_chip *bq) +{ + int ret; + u16 volt = 0; + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_VOLT], &volt); + if (ret < 0) { + bq_dbg(PR_OEM, "could not read voltage, ret = %d\n", ret); + return 3700; + } + + return volt; +} + +static int fg_read_avg_current(struct bq_fg_chip *bq, int *curr) +{ + int ret; + s16 avg_curr = 0; + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_AI], (u16 *)&avg_curr); + if (ret < 0) { + bq_dbg(PR_OEM, "could not read current, ret = %d\n", ret); + return ret; + } + *curr = -1 * avg_curr; + + return ret; +} + +static int fg_read_current(struct bq_fg_chip *bq, int *curr) +{ + int ret; + s16 avg_curr = 0; + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_CN], (u16 *)&avg_curr); + if (ret < 0) { + bq_dbg(PR_OEM, "could not read current, ret = %d\n", ret); + return ret; + } + *curr = -1 * avg_curr; + + return ret; +} + +static int fg_read_fcc(struct bq_fg_chip *bq) +{ + int ret; + u16 fcc; + + if (bq->regs[BQ_FG_REG_FCC] == INVALID_REG_ADDR) { + bq_dbg(PR_OEM, "FCC command not supported!\n"); + return 0; + } + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_FCC], &fcc); + + if (ret < 0) + bq_dbg(PR_OEM, "could not read FCC, ret=%d\n", ret); + + return fcc; +} + +static int fg_read_rm(struct bq_fg_chip *bq) +{ + int ret; + u16 rm; + + if (bq->regs[BQ_FG_REG_RM] == INVALID_REG_ADDR) { + bq_dbg(PR_OEM, "RemainingCapacity command not supported!\n"); + return 0; + } + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_RM], &rm); + + if (ret < 0) { + bq_dbg(PR_OEM, "could not read DC, ret=%d\n", ret); + return ret; + } + + return rm; +} + +static int fg_read_soh(struct bq_fg_chip *bq) +{ + int ret; + u16 soh; + + if (bq->regs[BQ_FG_REG_SOH] == INVALID_REG_ADDR) { + bq_dbg(PR_OEM, "SOH command not supported!\n"); + return 0; + } + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_SOH], &soh); + if (ret < 0) { + bq_dbg(PR_OEM, "could not read DC, ret=%d\n", ret); + return ret; + } + + return soh; +} + +static int fg_get_charge_counter(struct bq_fg_chip *bq, int *value) +{ + if (!bq) + return 0; + + *value = fg_read_rm(bq) * 1000; + + return 0; +} + +static int fg_read_cyclecount(struct bq_fg_chip *bq) +{ + int ret; + u16 cc; + + if (bq->regs[BQ_FG_REG_CC] == INVALID_REG_ADDR) { + bq_dbg(PR_OEM, "Cycle Count not supported!\n"); + return -EPERM; + } + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_CC], &cc); + + if (ret < 0) { + bq_dbg(PR_OEM, "could not read Cycle Count, ret=%d\n", ret); + return ret; + } + + return cc; +} + +static int fg_read_tte(struct bq_fg_chip *bq) +{ + int ret; + u16 tte; + + if (bq->regs[BQ_FG_REG_TTE] == INVALID_REG_ADDR) { + bq_dbg(PR_OEM, "Time To Empty not supported!\n"); + return -EPERM; + } + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_TTE], &tte); + + if (ret < 0) { + bq_dbg(PR_OEM, "could not read Time To Empty, ret=%d\n", ret); + return ret; + } + + if (ret == 0xFFFF) + return -ENODATA; + + return tte; +} + +static int fg_read_charging_current(struct bq_fg_chip *bq) +{ + int ret; + u16 cc; + + if (bq->regs[BQ_FG_REG_CHG_CUR] == INVALID_REG_ADDR) { + bq_dbg(PR_OEM, " not supported!\n"); + return -EPERM; + } + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_CHG_CUR], &cc); + + if (ret < 0) { + bq_dbg(PR_OEM, "could not read Time To Empty, ret=%d\n", ret); + return ret; + } + + if (ret == 0xFFFF) + return -ENODATA; + + return cc; +} + +static int fg_read_charging_voltage(struct bq_fg_chip *bq) +{ + int ret; + u16 cv; + + if (bq->regs[BQ_FG_REG_CHG_VOL] == INVALID_REG_ADDR) { + bq_dbg(PR_OEM, " not supported!\n"); + return -EPERM; + } + + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_CHG_VOL], &cv); + + if (ret < 0) { + bq_dbg(PR_OEM, "could not read Time To Empty, ret=%d\n", ret); + return ret; + } + + if (ret == 0xFFFF) + return -ENODATA; + + return cv; +} + +static int fg_get_batt_status(struct bq_fg_chip *bq) +{ + fg_read_status(bq); + + if (bq->batt_fc) + return POWER_SUPPLY_STATUS_FULL; + else if (bq->batt_dsg) + return POWER_SUPPLY_STATUS_DISCHARGING; + else if (bq->batt_curr > 0) + return POWER_SUPPLY_STATUS_CHARGING; + else + return POWER_SUPPLY_STATUS_NOT_CHARGING; +} + +static int fg_get_batt_capacity_level(struct bq_fg_chip *bq) +{ + if (bq->batt_fc) + return POWER_SUPPLY_CAPACITY_LEVEL_FULL; + else if (bq->batt_rca) + return POWER_SUPPLY_CAPACITY_LEVEL_LOW; + else if (bq->batt_fd) + return POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; + else + return POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; +} + +static int fg_get_soc_decimal_rate(struct bq_fg_chip *bq) +{ + int soc, i; + + if (bq->dec_rate_len <= 0) + return 0; + + soc = fg_read_rsoc(bq); + + for (i = 0; i < bq->dec_rate_len; i += 2) { + if (soc < bq->dec_rate_seq[i]) { + return bq->dec_rate_seq[i - 1]; + } + } + + return bq->dec_rate_seq[bq->dec_rate_len - 1]; +} + +static int fg_get_soc_decimal(struct bq_fg_chip *bq) +{ + int rsoc, raw_soc; + + if (!bq) + return 0; + + rsoc = fg_read_rsoc(bq); + raw_soc = fg_get_raw_soc(bq); + + if (bq->batt_soc > rsoc) + return 0; + + return raw_soc % 100; +} + +static int fg_get_cold_thermal_level(struct bq_fg_chip *bq) +{ + union power_supply_propval pval = { + 0, + }; + int curr, i, rc, temp, volt, status; + + if (!bq) + return -EINVAL; + + if (!bq->cold_thermal_len) + return 0; + + if (!bq->batt_psy) { + bq->batt_psy = power_supply_get_by_name("battery"); + if (!bq->batt_psy) { + return 0; + } + } + + rc = power_supply_get_property(bq->batt_psy, POWER_SUPPLY_PROP_STATUS, + &pval); + if (rc < 0) { + bq_dbg(PR_OEM, "failed get batt staus\n"); + return -EINVAL; + } + status = pval.intval; + + rc = power_supply_get_property(bq->batt_psy, POWER_SUPPLY_PROP_TEMP, + &pval); + if (rc < 0) { + bq_dbg(PR_OEM, "failed get batt temp\n"); + return -EINVAL; + } + temp = pval.intval; + + rc = power_supply_get_property(bq->batt_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, &pval); + if (rc < 0) { + bq_dbg(PR_OEM, "failed get batt temp\n"); + return -EINVAL; + } + volt = pval.intval; + + if (status == POWER_SUPPLY_STATUS_CHARGING || temp > 100 || + volt > 3500000) + return 0; + + fg_read_avg_current(bq, &curr); + + for (i = 0; i < bq->cold_thermal_len; i++) { + if (temp > bq->cold_thermal_seq[i].temp_l && + temp <= bq->cold_thermal_seq[i].temp_h && + curr > bq->cold_thermal_seq[i].curr_th) { + bq_dbg(PR_OEM, + "cold thermal trigger status:%d, temp:%d, volt:%d\n", + status, temp, volt); + bq_dbg(PR_OEM, + "curr:%d, bq->cold_thermal_seq[i].index:%d\n", + curr, bq->cold_thermal_seq[i].index); + return bq->cold_thermal_seq[i].index; + } + } + + return 0; +} + +static enum power_supply_property fg_props[] = { + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_CAPACITY_LEVEL, + POWER_SUPPLY_PROP_SOC_DECIMAL, + POWER_SUPPLY_PROP_SOC_DECIMAL_RATE, + POWER_SUPPLY_PROP_COLD_THERMAL_LEVEL, + POWER_SUPPLY_PROP_TEMP, + /*POWER_SUPPLY_PROP_HEALTH,*/ /*implement it in battery power_supply*/ + POWER_SUPPLY_PROP_CHARGE_FULL, + POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, + POWER_SUPPLY_PROP_CYCLE_COUNT, + POWER_SUPPLY_PROP_TECHNOLOGY, + POWER_SUPPLY_PROP_RESISTANCE_ID, + POWER_SUPPLY_PROP_UPDATE_NOW, + POWER_SUPPLY_PROP_CURRENT_MAX, + POWER_SUPPLY_PROP_VOLTAGE_MAX, + POWER_SUPPLY_PROP_AUTHENTIC, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, + POWER_SUPPLY_PROP_RESISTANCE, + POWER_SUPPLY_PROP_FASTCHARGE_MODE, + POWER_SUPPLY_PROP_CHARGE_COUNTER, + POWER_SUPPLY_PROP_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_FFC_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_RECHARGE_VBAT, + POWER_SUPPLY_PROP_MODEL_NAME, +}; + +static int fg_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct bq_fg_chip *bq = power_supply_get_drvdata(psy); + int ret; + u16 flags; + + switch (psp) { + case POWER_SUPPLY_PROP_MODEL_NAME: + if (bq->old_hw) { + val->strval = "unknown"; + break; + } + ret = fg_read_word(bq, bq->regs[BQ_FG_REG_BATT_STATUS], &flags); + if (ret < 0) + val->strval = "unknown"; + else + val->strval = "bq27z561"; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + if (bq->fake_volt != -EINVAL) { + val->intval = bq->fake_volt; + break; + } + if (bq->old_hw) { + val->intval = 3700 * 1000; + break; + } + ret = fg_read_volt(bq); + if (ret >= 0) + bq->batt_volt = ret; + val->intval = bq->batt_volt * 1000; + + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = 1; + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + if (bq->old_hw) { + val->intval = -500; + break; + } + fg_read_current(bq, &bq->batt_curr); + val->intval = bq->batt_curr * 1000; + break; + + case POWER_SUPPLY_PROP_CAPACITY: + if (bq->old_hw) { + val->intval = 50; + break; + } + val->intval = fg_read_system_soc(bq); + bq->batt_soc = val->intval; + break; + case POWER_SUPPLY_PROP_CAPACITY_LEVEL: + val->intval = fg_get_batt_capacity_level(bq); + break; + case POWER_SUPPLY_PROP_SOC_DECIMAL: + val->intval = fg_get_soc_decimal(bq); + break; + case POWER_SUPPLY_PROP_SOC_DECIMAL_RATE: + val->intval = fg_get_soc_decimal_rate(bq); + break; + case POWER_SUPPLY_PROP_COLD_THERMAL_LEVEL: + val->intval = fg_get_cold_thermal_level(bq); + break; + case POWER_SUPPLY_PROP_TEMP: + if (bq->fake_temp != -EINVAL) { + val->intval = bq->fake_temp; + break; + } + if (bq->old_hw) { + val->intval = 250; + break; + } + val->intval = bq->batt_temp; + break; + case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW: + if (bq->old_hw) { + val->intval = bq->batt_tte; + break; + } + ret = fg_read_tte(bq); + if (ret >= 0) + bq->batt_tte = ret; + + val->intval = bq->batt_tte; + break; + + case POWER_SUPPLY_PROP_CHARGE_FULL: + if (bq->old_hw) { + val->intval = 4050000; + break; + } + ret = fg_read_fcc(bq); + if (ret > 0) + bq->batt_fcc = ret; + val->intval = bq->batt_fcc * 1000; + break; + + case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: + val->intval = bq->batt_dc; + break; + + case POWER_SUPPLY_PROP_CYCLE_COUNT: + if (bq->old_hw) { + val->intval = 1; + break; + } + ret = fg_read_cyclecount(bq); + if (ret >= 0) + bq->batt_cyclecnt = ret; + val->intval = bq->batt_cyclecnt; + break; + + case POWER_SUPPLY_PROP_TECHNOLOGY: + val->intval = POWER_SUPPLY_TECHNOLOGY_LIPO; + break; + case POWER_SUPPLY_PROP_RESISTANCE: + val->intval = bq->batt_resistance; + break; + case POWER_SUPPLY_PROP_RESISTANCE_ID: + val->intval = 100000; + break; + case POWER_SUPPLY_PROP_UPDATE_NOW: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_CURRENT_MAX: + if (bq->old_hw) { + val->intval = 8000000; + break; + } + val->intval = fg_read_charging_current(bq); + if (bq->verify_digest_success == false && + !bq->ignore_digest_for_debug) { + val->intval = min(val->intval, 2000); + } + val->intval *= 1000; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX: + if (bq->old_hw) { + val->intval = 4450000; + break; + } + val->intval = fg_read_charging_voltage(bq); + val->intval *= 1000; + break; + case POWER_SUPPLY_PROP_AUTHENTIC: + val->intval = bq->verify_digest_success; + break; + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: + if (bq->constant_charge_current_max != 0) + val->intval = bq->constant_charge_current_max; + else + val->intval = fg_read_charging_current(bq); + break; + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + if (bq->old_hw) { + val->intval = 0; + break; + } + val->intval = bq->fast_mode; + break; + case POWER_SUPPLY_PROP_CHARGE_COUNTER: + if (bq->old_hw) { + val->intval = 4050000; + break; + } + ret = fg_get_charge_counter(bq, &val->intval); + break; + case POWER_SUPPLY_PROP_TERMINATION_CURRENT: + val->intval = manu_info[TERMINATION].data; + break; + case POWER_SUPPLY_PROP_FFC_TERMINATION_CURRENT: + val->intval = manu_info[FFC_TERMINATION].data; + break; + case POWER_SUPPLY_PROP_RECHARGE_VBAT: + if (bq->batt_recharge_vol > 0) + val->intval = bq->batt_recharge_vol; + else + val->intval = manu_info[RECHARGE_VOL].data; + break; + default: + return -EINVAL; + } + return 0; +} + +static int fg_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + struct bq_fg_chip *bq = power_supply_get_drvdata(psy); + + switch (prop) { + case POWER_SUPPLY_PROP_TEMP: + bq->fake_temp = val->intval; + break; + case POWER_SUPPLY_PROP_CAPACITY: + bq->fake_soc = val->intval; + power_supply_changed(bq->fg_psy); + break; + case POWER_SUPPLY_PROP_UPDATE_NOW: + break; + case POWER_SUPPLY_PROP_AUTHENTIC: + bq->verify_digest_success = !!val->intval; + break; + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: + bq->constant_charge_current_max = val->intval; + break; + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + fg_set_fastcharge_mode(bq, !!val->intval); + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + bq->fake_volt = val->intval; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int fg_prop_is_writeable(struct power_supply *psy, + enum power_supply_property prop) +{ + int ret; + + switch (prop) { + case POWER_SUPPLY_PROP_TEMP: + case POWER_SUPPLY_PROP_CAPACITY: + case POWER_SUPPLY_PROP_UPDATE_NOW: + case POWER_SUPPLY_PROP_AUTHENTIC: + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: + ret = 1; + break; + default: + ret = 0; + break; + } + return ret; +} + +static int fg_psy_register(struct bq_fg_chip *bq) +{ + struct power_supply_config fg_psy_cfg = {}; + + bq->fg_psy_d.name = "bms"; + bq->fg_psy_d.type = POWER_SUPPLY_TYPE_BMS; + bq->fg_psy_d.properties = fg_props; + bq->fg_psy_d.num_properties = ARRAY_SIZE(fg_props); + bq->fg_psy_d.get_property = fg_get_property; + bq->fg_psy_d.set_property = fg_set_property; + bq->fg_psy_d.property_is_writeable = fg_prop_is_writeable; + + fg_psy_cfg.drv_data = bq; + fg_psy_cfg.num_supplicants = 0; + bq->fg_psy = + devm_power_supply_register(bq->dev, &bq->fg_psy_d, &fg_psy_cfg); + if (IS_ERR(bq->fg_psy)) { + bq_dbg(PR_OEM, "Failed to register fg_psy"); + return PTR_ERR(bq->fg_psy); + } + + return 0; +} + +static void fg_psy_unregister(struct bq_fg_chip *bq) +{ + power_supply_unregister(bq->fg_psy); +} + +static const u8 fg_dump_regs[] = { + 0x00, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x0E, 0x10, 0x16, 0x18, 0x1A, + 0x1C, 0x1E, 0x20, 0x28, 0x2A, 0x2C, 0x2E, 0x30, 0x66, 0x68, 0x6C, 0x6E, +}; + +static ssize_t fg_attr_show_Ra_table(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + u8 t_buf[40]; + u8 temp_buf[40]; + int ret; + int i, idx, len; + + ret = fg_mac_read_block(bq, FG_MAC_CMD_RA_TABLE, t_buf, 32); + if (ret < 0) + return 0; + + idx = 0; + len = sprintf(temp_buf, "Ra Flag:0x%02X\n", t_buf[0] << 8 | t_buf[1]); + memcpy(&buf[idx], temp_buf, len); + idx += len; + len = sprintf(temp_buf, "RaTable:\n"); + memcpy(&buf[idx], temp_buf, len); + idx += len; + for (i = 1; i < 16; i++) { + len = sprintf(temp_buf, "%d ", + t_buf[i * 2] << 8 | t_buf[i * 2 + 1]); + memcpy(&buf[idx], temp_buf, len); + idx += len; + } + + return idx; +} + +static ssize_t fg_attr_show_Qmax(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int ret; + u8 t_buf[64]; + int len; + + memset(t_buf, 0, 64); + + ret = fg_mac_read_block(bq, FG_MAC_CMD_QMAX, t_buf, 2); + if (ret < 0) + return 0; + + len = snprintf(buf, sizeof(t_buf), "%d\n", (t_buf[1] << 8) | t_buf[0]); + + return len; +} + +static ssize_t fg_attr_show_fcc_soh(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int ret; + u8 t_buf[64]; + int len; + + memset(t_buf, 0, 64); + + ret = fg_mac_read_block(bq, 0x0077, t_buf, 2); + if (ret < 0) + return 0; + + len = snprintf(buf, sizeof(t_buf), "%d\n", (t_buf[1] << 8) | t_buf[0]); + + return len; +} + +static ssize_t fg_attr_show_rm(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int rm, len; + + rm = fg_read_rm(bq); + len = snprintf(buf, 1024, "%d\n", rm); + + return len; +} + +static ssize_t fg_attr_show_fcc(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int fcc, len; + + fcc = fg_read_fcc(bq); + len = snprintf(buf, 1024, "%d\n", fcc); + + return len; +} + +static ssize_t fg_attr_show_soh(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int soh, len; + + soh = fg_read_soh(bq); + len = snprintf(buf, 1024, "%d\n", soh); + + return len; +} + +static ssize_t verify_digest_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + u8 digest_buf[4]; + int i; + int len; + + for (i = 0; i < BATTERY_DIGEST_LEN; i++) { + memset(digest_buf, 0, sizeof(digest_buf)); + snprintf(digest_buf, sizeof(digest_buf) - 1, "%02x", + bq->digest[i]); + strlcat(buf, digest_buf, BATTERY_DIGEST_LEN * 2 + 1); + } + len = strlen(buf); + buf[len] = '\0'; + + return strlen(buf) + 1; +} + +int StringToHex(char *str, unsigned char *out, unsigned int *outlen) +{ + char *p = str; + char high = 0, low = 0; + int tmplen = strlen(p), cnt = 0; + tmplen = strlen(p); + while (cnt < (tmplen / 2)) { + high = ((*p > '9') && ((*p <= 'F') || (*p <= 'f'))) ? + *p - 48 - 7 : + *p - 48; + low = (*(++p) > '9' && ((*p <= 'F') || (*p <= 'f'))) ? + *(p)-48 - 7 : + *(p)-48; + out[cnt] = ((high & 0x0f) << 4 | (low & 0x0f)); + p++; + cnt++; + } + if (tmplen % 2 != 0) + out[cnt] = ((*p > '9') && ((*p <= 'F') || (*p <= 'f'))) ? + *p - 48 - 7 : + *p - 48; + + if (outlen != NULL) + *outlen = tmplen / 2 + tmplen % 2; + + return tmplen / 2 + tmplen % 2; +} + +ssize_t verify_digest_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int i; + u8 random[32] = { 0 }; + char kbuf[70] = { 0 }; + + memset(kbuf, 0, sizeof(kbuf)); + strncpy(kbuf, buf, count - 1); + + StringToHex(kbuf, random, &i); + fg_sha256_auth(bq, random, BATTERY_DIGEST_LEN); + + return count; +} + +static ssize_t fg_attr_show_TRemQ(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int ret; + u8 t_buf[64]; + int len; + + memset(t_buf, 0, 64); + + ret = fg_mac_read_block(bq, FG_MAC_CMD_ITSTATUS1, t_buf, 36); + if (ret < 0) + return 0; + + len = snprintf(buf, sizeof(t_buf), "%d\n", (t_buf[1] << 8) | t_buf[0]); + + return len; +} + +static ssize_t fg_attr_show_TFullChgQ(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int ret; + u8 t_buf[64]; + int len; + + memset(t_buf, 0, 64); + + ret = fg_mac_read_block(bq, FG_MAC_CMD_ITSTATUS1, t_buf, 36); + if (ret < 0) + return 0; + + len = snprintf(buf, sizeof(t_buf), "%d\n", (t_buf[9] << 8) | t_buf[8]); + + return len; +} + +static ssize_t fg_attr_show_TSim(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int ret; + u8 t_buf[64]; + int len; + + memset(t_buf, 0, 64); + + ret = fg_mac_read_block(bq, FG_MAC_CMD_ITSTATUS1, t_buf, 36); + if (ret < 0) + return 0; + + len = snprintf(buf, sizeof(t_buf), "%d\n", + (t_buf[13] << 8) | t_buf[12]); + + return len; +} + +static ssize_t fg_attr_show_TAmbient(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int ret; + u8 t_buf[64]; + int len; + + memset(t_buf, 0, 64); + + ret = fg_mac_read_block(bq, FG_MAC_CMD_ITSTATUS1, t_buf, 36); + if (ret < 0) + return 0; + + len = snprintf(buf, sizeof(t_buf), "%d\n", + (t_buf[15] << 8) | t_buf[14]); + + return len; +} + +static DEVICE_ATTR(verify_digest, 0660, verify_digest_show, + verify_digest_store); +static DEVICE_ATTR(RaTable, S_IRUGO, fg_attr_show_Ra_table, NULL); +static DEVICE_ATTR(Qmax, S_IRUGO, fg_attr_show_Qmax, NULL); +static DEVICE_ATTR(fcc_soh, S_IRUGO, fg_attr_show_fcc_soh, NULL); +static DEVICE_ATTR(rm, S_IRUGO, fg_attr_show_rm, NULL); +static DEVICE_ATTR(fcc, S_IRUGO, fg_attr_show_fcc, NULL); +static DEVICE_ATTR(soh, S_IRUGO, fg_attr_show_soh, NULL); +static DEVICE_ATTR(TRemQ, S_IRUGO, fg_attr_show_TRemQ, NULL); +static DEVICE_ATTR(TFullChgQ, S_IRUGO, fg_attr_show_TFullChgQ, NULL); +static DEVICE_ATTR(TSim, S_IRUGO, fg_attr_show_TSim, NULL); +static DEVICE_ATTR(TAmbient, S_IRUGO, fg_attr_show_TAmbient, NULL); + +static struct attribute *fg_attributes[] = { + &dev_attr_RaTable.attr, &dev_attr_Qmax.attr, + &dev_attr_fcc_soh.attr, &dev_attr_rm.attr, + &dev_attr_fcc.attr, &dev_attr_soh.attr, + &dev_attr_verify_digest.attr, &dev_attr_TRemQ.attr, + &dev_attr_TFullChgQ.attr, &dev_attr_TSim.attr, + &dev_attr_TAmbient.attr, NULL, +}; + +static const struct attribute_group fg_attr_group = { + .attrs = fg_attributes, +}; + +static int fg_dump_registers(struct bq_fg_chip *bq) +{ + int i; + int ret; + u16 val; + + for (i = 0; i < ARRAY_SIZE(fg_dump_regs); i++) { + ret = fg_read_word(bq, fg_dump_regs[i], &val); + if (!ret) + bq_dbg(PR_REGISTER, "Reg[%02X] = 0x%04X\n", + fg_dump_regs[i], val); + } + + return ret; +} + +static void fg_update_status(struct bq_fg_chip *bq) +{ + static int last_st, last_soc, last_temp; + int rm, fcc; + + mutex_lock(&bq->data_lock); + + bq->batt_soc = fg_read_system_soc(bq); + bq->batt_volt = fg_read_volt(bq); + fg_read_current(bq, &bq->batt_curr); + bq->batt_temp = fg_read_temperature(bq); + bq->batt_st = fg_get_batt_status(bq); + rm = fg_read_rm(bq); + fcc = fg_read_fcc(bq); + + mutex_unlock(&bq->data_lock); + + bq_dbg(PR_OEM, "SOC:%d,Volt:%d,Cur:%d,Temp:%d,RM:%d,FC:%d,FAST:%d", + bq->batt_soc, bq->batt_volt, bq->batt_curr, bq->batt_temp, rm, + fcc, bq->fast_mode); + + if ((last_soc != bq->batt_soc) || (last_temp != bq->batt_temp) || + (last_st != bq->batt_st)) { + if (bq->fg_psy) + power_supply_changed(bq->fg_psy); + } + + last_soc = bq->batt_soc; + last_temp = bq->batt_temp; + last_st = bq->batt_st; +} + +static int fg_get_raw_soc(struct bq_fg_chip *bq) +{ + int rm, fcc; + int raw_soc; + + rm = fg_read_rm(bq); + fcc = fg_read_fcc(bq); + + raw_soc = rm * 10000 / fcc; + + return raw_soc; +} + +static int calc_delta_time(struct timeval *time_start, int *delta_time) +{ + struct timeval time_now; + + *delta_time = 0; + + do_gettimeofday(&time_now); + *delta_time = (time_now.tv_sec - time_start->tv_sec); + if (*delta_time < 0) + *delta_time = 0; + + return 0; +} + +#define BATT_HIGH_AVG_CURRENT 1000000 +#define NORMAL_TEMP_CHARGING_DELTA 10 +#define NORMAL_DISTEMP_CHARGING_DELTA 60 +#define LOW_TEMP_CHARGING_DELTA 10 +#define LOW_TEMP_DISCHARGING_DELTA 20 +#define BATT_TEMP_LOW_THRED 150 +#define FFC_SMOOTH_LEN 4 +#define FG_RAW_SOC_FULL 10000 + +struct ffc_smooth { + int curr_lim; + int time; +}; + +struct ffc_smooth ffc_dischg_smooth[FFC_SMOOTH_LEN] = { + { 0, 300 }, + { 300, 150 }, + { 600, 72 }, + { 1000, 50 }, +}; + +static int bq_battery_soc_smooth_tracking(struct bq_fg_chip *bq, int raw_soc, + int batt_soc, int batt_temp, + int batt_ma) +{ + return batt_soc; +} + +static void fg_monitor_workfunc(struct work_struct *work) +{ + struct bq_fg_chip *bq = + container_of(work, struct bq_fg_chip, monitor_work.work); + int rc; + + if (!bq->old_hw) { + rc = fg_dump_registers(bq); + /*if (rc < 0) + return;*/ + fg_update_status(bq); + } + + schedule_delayed_work(&bq->monitor_work, 10 * HZ); +} +static int bq_parse_dt(struct bq_fg_chip *bq) +{ + struct device_node *node = bq->dev->of_node; + int ret, size; + + ret = of_property_read_u32(node, "bq,charge-full-design", &bq->batt_dc); + if (ret < 0) { + bq_dbg(PR_OEM, "failed to get bq,charge-full-designe\n"); + bq->batt_dc = DEFUALT_FULL_DESIGN; + return ret; + } + + ret = of_property_read_u32(node, "bq,recharge-voltage", + &bq->batt_recharge_vol); + if (ret < 0) { + bq_dbg(PR_OEM, "failed to get bq,recharge-voltage\n"); + bq->batt_recharge_vol = -EINVAL; + return ret; + } + + bq->ignore_digest_for_debug = + of_property_read_bool(node, "bq,ignore-digest-debug"); + + size = 0; + of_get_property(node, "bq,soc_decimal_rate", &size); + if (size) { + bq->dec_rate_seq = devm_kzalloc(bq->dev, size, GFP_KERNEL); + if (bq->dec_rate_seq) { + bq->dec_rate_len = (size / sizeof(*bq->dec_rate_seq)); + if (bq->dec_rate_len % 2) { + bq_dbg(PR_OEM, + "invalid soc decimal rate seq\n"); + return -EINVAL; + } + of_property_read_u32_array(node, "bq,soc_decimal_rate", + bq->dec_rate_seq, + bq->dec_rate_len); + } else { + bq_dbg(PR_OEM, + "error allocating memory for dec_rate_seq\n"); + } + } + + size = 0; + of_get_property(node, "bq,cold_thermal_seq", &size); + if (size) { + bq->cold_thermal_seq = devm_kzalloc(bq->dev, size, GFP_KERNEL); + if (bq->cold_thermal_seq) { + bq->cold_thermal_len = (size / sizeof(int)); + if (bq->cold_thermal_len % 4) { + bq_dbg(PR_OEM, "invalid cold thermal seq\n"); + return -EINVAL; + } + of_property_read_u32_array(node, "bq,cold_thermal_seq", + (int *)bq->cold_thermal_seq, + bq->cold_thermal_len); + bq->cold_thermal_len = bq->cold_thermal_len / 4; + } else { + bq_dbg(PR_OEM, + "error allocating memory for cold thermal seq\n"); + } + } + + return 0; +} + +static struct regmap_config i2c_bq27z561_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xFFFF, +}; + +static int bq_fg_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + struct bq_fg_chip *bq; + u8 *regs; + + bq = devm_kzalloc(&client->dev, sizeof(*bq), GFP_DMA); + + if (!bq) + return -ENOMEM; + + bq->dev = &client->dev; + bq->client = client; + bq->chip = id->driver_data; + + bq->batt_soc = -ENODATA; + bq->batt_fcc = -ENODATA; + bq->batt_rm = -ENODATA; + bq->batt_dc = -ENODATA; + bq->batt_volt = -ENODATA; + bq->batt_temp = -ENODATA; + bq->batt_curr = -ENODATA; + bq->batt_cyclecnt = -ENODATA; + bq->batt_tte = -ENODATA; + + bq->fake_soc = -EINVAL; + bq->fake_temp = -EINVAL; + bq->fake_volt = -EINVAL; + + if (bq->chip == BQ27Z561) { + regs = bq27z561_regs; + } else { + bq_dbg(PR_OEM, "unexpected fuel gauge: %d\n", bq->chip); + regs = bq27z561_regs; + } + memcpy(bq->regs, regs, NUM_REGS); + + i2c_set_clientdata(client, bq); + + bq_parse_dt(bq); + + bq->regmap = devm_regmap_init_i2c(client, &i2c_bq27z561_regmap_config); + if (!bq->regmap) + return -ENODEV; + + fg_get_manufacture_data(bq); + fg_set_fastcharge_mode(bq, false); + + mutex_init(&bq->i2c_rw_lock); + mutex_init(&bq->data_lock); + device_init_wakeup(bq->dev, 1); + + fg_psy_register(bq); + fg_update_status(bq); + + ret = sysfs_create_group(&bq->dev->kobj, &fg_attr_group); + if (ret) + bq_dbg(PR_OEM, "Failed to register sysfs, err:%d\n", ret); + + INIT_DELAYED_WORK(&bq->monitor_work, fg_monitor_workfunc); + schedule_delayed_work(&bq->monitor_work, 10 * HZ); + + bq_dbg(PR_OEM, "bq fuel gauge probe successfully, %s\n", + device2str[bq->chip]); + + return 0; +} + +static int bq_fg_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + + do_gettimeofday(&bq->suspend_time); + + cancel_delayed_work(&bq->monitor_work); + + return 0; +} +#define BQ_RESUME_UPDATE_TIME 600 + +static int bq_fg_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct bq_fg_chip *bq = i2c_get_clientdata(client); + int delta_time; + + calc_delta_time(&bq->suspend_time, &delta_time); + + if (delta_time > BQ_RESUME_UPDATE_TIME) { + bq_dbg(PR_OEM, "suspend more than %d, update soc now\n", + BQ_RESUME_UPDATE_TIME); + bq->update_now = true; + } + + schedule_delayed_work(&bq->monitor_work, HZ); + + return 0; +} + +static int bq_fg_remove(struct i2c_client *client) +{ + struct bq_fg_chip *bq = i2c_get_clientdata(client); + + fg_psy_unregister(bq); + + mutex_destroy(&bq->data_lock); + mutex_destroy(&bq->i2c_rw_lock); + + sysfs_remove_group(&bq->dev->kobj, &fg_attr_group); + + return 0; +} + +static void bq_fg_shutdown(struct i2c_client *client) +{ + bq_dbg(PR_OEM, "bq fuel gauge driver shutdown!\n"); +} + +static struct of_device_id bq_fg_match_table[] = { + { + .compatible = "ti,bq27z561", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, bq_fg_match_table); + +static const struct i2c_device_id bq_fg_id[] = { + { "bq27z561", BQ27Z561 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, bq_fg_id); + +static const struct dev_pm_ops bq_fg_pm_ops = { + .resume = bq_fg_resume, + .suspend = bq_fg_suspend, +}; + +static struct i2c_driver bq_fg_driver = { + .driver = { + .name = "bq_fg", + .owner = THIS_MODULE, + .of_match_table = bq_fg_match_table, + .pm = &bq_fg_pm_ops, + }, + .id_table = bq_fg_id, + + .probe = bq_fg_probe, + .remove = bq_fg_remove, + .shutdown = bq_fg_shutdown, + +}; + +module_i2c_driver(bq_fg_driver); + +MODULE_DESCRIPTION("TI BQ27Z561 Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Texas Instruments"); diff --git a/drivers/power/supply/ti/cp_qc30.c b/drivers/power/supply/ti/cp_qc30.c new file mode 100644 index 000000000000..47b23ede9bf8 --- /dev/null +++ b/drivers/power/supply/ti/cp_qc30.c @@ -0,0 +1,1527 @@ +/* + * State machine for qc3 when it works on cp + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#define pr_fmt(fmt) "[FC2-PM]: %s: " fmt, __func__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cp_qc30.h" + +#ifdef pr_debug +#undef pr_debug +#define pr_debug pr_err +#endif +#ifdef pr_info +#undef pr_info +#define pr_info pr_err +#endif + +#define BATT_MAX_CHG_VOLT 4400 +#define BATT_FAST_CHG_CURR 5400 +#define BUS_OVP_THRESHOLD 12000 +#define BUS_OVP_ALARM_THRESHOLD 9500 + +#define BUS_VOLT_INIT_UP 200 + +#define BAT_VOLT_LOOP_LMT BATT_MAX_CHG_VOLT +#define BAT_CURR_LOOP_LMT BATT_FAST_CHG_CURR +#define BUS_VOLT_LOOP_LMT BUS_OVP_THRESHOLD + +#define VOLT_UP true +#define VOLT_DOWN false + +#define ADC_ERR 1 +#define CP_ENABLE_FAIL 2 +#define TAPER_DONE 1 + +#ifdef CONFIG_CHARGER_LN8000 +#define VBUS_COMP 250 +#else +#define VBUS_COMP 150 +#endif + +enum { + VBUS_ERROR_NONE, + VBUS_ERROR_LOW, + VBUS_ERROR_HIGH, +}; + +static struct sys_config sys_config = { + .bat_volt_lp_lmt = BAT_VOLT_LOOP_LMT, + .ffc_bat_volt_lmt = BAT_VOLT_LOOP_LMT, + .bat_curr_lp_lmt = BAT_CURR_LOOP_LMT /* + 1000*/, + .bus_volt_lp_lmt = BUS_VOLT_LOOP_LMT, + .bus_curr_lp_lmt = BAT_CURR_LOOP_LMT >> 1, + + .ibus_minus_deviation_val = HVDCP3_IBUS_MINUS_DEV_VAL, + .ibus_plus_deviation_val = HVDCP3_IBUS_PLUS_DEV_VAL, + .ibat_minus_deviation_val = HVDCP3_IBAT_MINUS_DEV_VAL, + .ibat_plus_deviation_val = HVDCP3_IBAT_PLUS_DEV_VAL, + + .fc2_taper_current = 2200, + .flash2_policy.down_steps = -1, + .flash2_policy.volt_hysteresis = 50, + + .min_vbat_start_flash2 = 3500, + .cp_sec_enable = false, + .qc3p5_supported = false, +}; + +struct cp_qc30_data { + struct device *dev; + int bat_volt_max; + int ffc_bat_volt_max; + int bat_curr_max; + int bus_volt_max; + int bus_curr_max; + bool cp_sec_enable; + bool qc3p5_supported; + + /* notifiers */ + struct notifier_block nb; +}; + +static pm_t pm_state; + +static int fc2_taper_timer; +static int ibus_lmt_change_timer; + +static struct power_supply *cp_get_sw_psy(void) +{ + if (!pm_state.sw_psy) + pm_state.sw_psy = power_supply_get_by_name("battery"); + + return pm_state.sw_psy; +} + +static struct power_supply *cp_get_usb_psy(void) +{ + if (!pm_state.usb_psy) + pm_state.usb_psy = power_supply_get_by_name("usb"); + + return pm_state.usb_psy; +} + +static struct power_supply *cp_get_bms_psy(void) +{ + if (!pm_state.bms_psy) + pm_state.bms_psy = power_supply_get_by_name("bms"); + + return pm_state.bms_psy; +} + +static int cp_get_effective_fcc_val(pm_t pm_state) +{ + int effective_fcc_val = 0; + + if (!pm_state.fcc_votable) + pm_state.fcc_votable = find_votable("FCC"); + + if (!pm_state.fcc_votable) + return -EINVAL; + + effective_fcc_val = get_effective_result(pm_state.fcc_votable); + effective_fcc_val = effective_fcc_val / 1000; + pr_info("effective_fcc_val: %d\n", effective_fcc_val); + return effective_fcc_val; +} + +static struct power_supply *cp_get_fc_psy(void) +{ + if (!pm_state.fc_psy) { + if (sys_config.cp_sec_enable) + pm_state.fc_psy = + power_supply_get_by_name("bq2597x-master"); + else + pm_state.fc_psy = + power_supply_get_by_name("bq2597x-standalone"); + } + + return pm_state.fc_psy; +} + +static void cp_update_bms_ibat(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_bms_psy(); + if (!psy) + return; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_CURRENT_NOW, + &val); + if (!ret) + pm_state.ibat_now = -(val.intval / 1000); +} + +static int qc3_get_bms_fastcharge_mode(void) +{ + union power_supply_propval pval = { + 0, + }; + int rc; + + cp_get_bms_psy(); + + if (!pm_state.bms_psy) + return 0; + + rc = power_supply_get_property( + pm_state.bms_psy, POWER_SUPPLY_PROP_FASTCHARGE_MODE, &pval); + if (rc < 0) { + pr_info("Couldn't get fastcharge mode:%d\n", rc); + return 0; + } + + pm_state.bms_fastcharge_mode = pval.intval; + + return pval.intval; +} + +/* get thermal level from battery power supply property */ +static int qc3_get_batt_current_thermal_level(int *level) +{ + int ret, rc; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return 0; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT, &val); + + if (rc < 0) { + pr_info("Couldn't get themal level:%d\n", rc); + return rc; + } + + pr_err("val.intval: %d\n", val.intval); + + *level = val.intval; + return rc; +} + +/* determine whether to disable cp according to jeita status */ +static bool qc3_disable_cp_by_jeita_status(void) +{ + int batt_temp = 0, bq_input_suspend = 0; + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return false; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_BQ_INPUT_SUSPEND, + &val); + if (!ret) + bq_input_suspend = !!val.intval; + + psy = cp_get_bms_psy(); + if (!psy) + return false; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TEMP, &val); + + if (ret < 0) { + pr_info("Couldn't get batt temp prop:%d\n", ret); + return false; + } + + batt_temp = val.intval; + pr_err("batt_temp: %d\n", batt_temp); + + if (bq_input_suspend) { + return true; + } else { + if (batt_temp >= JEITA_WARM_THR && !pm_state.jeita_triggered) { + pm_state.jeita_triggered = true; + return true; + } else if (batt_temp <= JEITA_COOL_NOT_ALLOW_CP_THR && + !pm_state.jeita_triggered) { + pm_state.jeita_triggered = true; + return true; + } else if ((batt_temp <= (JEITA_WARM_THR - JEITA_HYSTERESIS)) && + (batt_temp >= + (JEITA_COOL_NOT_ALLOW_CP_THR + JEITA_HYSTERESIS)) && + pm_state.jeita_triggered) { + pm_state.jeita_triggered = false; + return false; + } else { + return pm_state.jeita_triggered; + } + } +} + +static int qc3_check_slowly_charging_enabled(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return false; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_SLOWLY_CHARGING, + &val); + if (!ret) + pm_state.slowly_charging = !!val.intval; + + return ret; +} + +static void cp_get_batt_capacity(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_CAPACITY, &val); + if (!ret) + pm_state.capacity = val.intval; + pr_info("capacity %d\n", pm_state.capacity); +} + +static void cp_update_fc_status(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_fc_psy(); + if (!psy) + return; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, &val); + if (!ret) + pm_state.bq2597x.vbat_volt = val.intval; + + /*ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TI_BATTERY_CURRENT, &val); + if (!ret) + pm_state.bq2597x.ibat_curr = val.intval; */ + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TI_BUS_VOLTAGE, + &val); + if (!ret) + pm_state.bq2597x.vbus_volt = val.intval; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TI_BUS_CURRENT, + &val); + if (!ret) + pm_state.bq2597x.ibus_curr = val.intval; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_TI_BUS_TEMPERATURE, &val); + if (!ret) + pm_state.bq2597x.bus_temp = val.intval; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_TI_BATTERY_TEMPERATURE, &val); + if (!ret) + pm_state.bq2597x.bat_temp = val.intval; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_TI_DIE_TEMPERATURE, &val); + if (!ret) + pm_state.bq2597x.die_temp = val.intval; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_TI_BATTERY_PRESENT, &val); + if (!ret) + pm_state.bq2597x.batt_pres = val.intval; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TI_VBUS_PRESENT, + &val); + if (!ret) + pm_state.bq2597x.vbus_pres = val.intval; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_TI_BUS_ERROR_STATUS, &val); + if (!ret) + pm_state.bq2597x.bus_error_status = val.intval; + + if (pm_state.bq2597x.vbus_pres == 1) { + cp_update_bms_ibat(); + pm_state.bq2597x.ibat_curr = pm_state.ibat_now; + } + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, + &val); + if (!ret) + pm_state.bq2597x.charge_enabled = val.intval; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TI_ALARM_STATUS, + &val); + if (!ret) { + pm_state.bq2597x.bat_ovp_alarm = + !!(val.intval & BAT_OVP_ALARM_MASK); + pm_state.bq2597x.bat_ocp_alarm = + !!(val.intval & BAT_OCP_ALARM_MASK); + pm_state.bq2597x.bus_ovp_alarm = + !!(val.intval & BUS_OVP_ALARM_MASK); + pm_state.bq2597x.bus_ocp_alarm = + !!(val.intval & BUS_OCP_ALARM_MASK); + pm_state.bq2597x.bat_ucp_alarm = + !!(val.intval & BAT_UCP_ALARM_MASK); + pm_state.bq2597x.bat_therm_alarm = + !!(val.intval & BAT_THERM_ALARM_MASK); + pm_state.bq2597x.bus_therm_alarm = + !!(val.intval & BUS_THERM_ALARM_MASK); + pm_state.bq2597x.die_therm_alarm = + !!(val.intval & DIE_THERM_ALARM_MASK); + } + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TI_FAULT_STATUS, + &val); + if (!ret) { + pm_state.bq2597x.bat_ovp_fault = + !!(val.intval & BAT_OVP_FAULT_MASK); + pm_state.bq2597x.bat_ocp_fault = + !!(val.intval & BAT_OCP_FAULT_MASK); + pm_state.bq2597x.bus_ovp_fault = + !!(val.intval & BUS_OVP_FAULT_MASK); + pm_state.bq2597x.bus_ocp_fault = + !!(val.intval & BUS_OCP_FAULT_MASK); + pm_state.bq2597x.bat_therm_fault = + !!(val.intval & BAT_THERM_FAULT_MASK); + pm_state.bq2597x.bus_therm_fault = + !!(val.intval & BUS_THERM_FAULT_MASK); + pm_state.bq2597x.die_therm_fault = + !!(val.intval & DIE_THERM_FAULT_MASK); + } + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_TI_REG_STATUS, + &val); + if (!ret) { + pm_state.bq2597x.vbat_reg = + !!(val.intval & VBAT_REG_STATUS_MASK); + pm_state.bq2597x.ibat_reg = + !!(val.intval & IBAT_REG_STATUS_MASK); + } +} + +static int cp_enable_fc(bool enable) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_fc_psy(); + if (!psy) + return -ENODEV; + + val.intval = enable; + ret = power_supply_set_property(psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, + &val); + + return ret; +} + +static int cp_set_qc_bus_protections(int hvdcp3_type) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_fc_psy(); + if (!psy) + return -ENODEV; + + val.intval = hvdcp3_type; + ret = power_supply_set_property( + psy, POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3, &val); + + return ret; +} + +static int cp_enable_sw(bool enable) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return -ENODEV; + + val.intval = enable; + ret = power_supply_set_property( + psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, &val); + + return ret; +} + +static int cp_limit_sw(bool enable) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return -ENODEV; + + val.intval = enable; + ret = power_supply_set_property( + psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED, &val); + + return ret; +} + +static int cp_check_fc_enabled(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_fc_psy(); + if (!psy) + return -ENODEV; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, + &val); + if (!ret) + pm_state.bq2597x.charge_enabled = !!val.intval; + + pr_info("pm_state.bq2597x.charge_enabled: %d\n", + pm_state.bq2597x.charge_enabled); + return ret; +} + +static int cp_check_sw_enabled(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return -ENODEV; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, &val); + if (!ret) + pm_state.sw_chager.charge_enabled = !!val.intval; + + pr_info("pm_state.sw_chager.charge_enabled: %d\n", + pm_state.sw_chager.charge_enabled); + return ret; +} + +static int cp_check_sw_limited(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return -ENODEV; + + ret = power_supply_get_property( + psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED, &val); + if (!ret) + pm_state.sw_chager.charge_limited = !!val.intval; + + pr_info("pm_state.sw_chager.charge_limited: %d\n", + pm_state.sw_chager.charge_limited); + return ret; +} + +static void cp_update_sw_status(void) +{ + cp_check_sw_enabled(); + cp_check_sw_limited(); +} + +static int cp_tune_vbus_volt(bool up) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return -ENODEV; + + if (up) + val.intval = POWER_SUPPLY_DP_DM_DP_PULSE; + else + val.intval = POWER_SUPPLY_DP_DM_DM_PULSE; + + ret = power_supply_set_property(psy, POWER_SUPPLY_PROP_DP_DM_BQ, &val); + + pr_info("tune adapter voltage %s %s\n", up ? "up" : "down", + ret ? "fail" : "successfully"); + + return ret; +} + +static int cp_get_qc_pulse_cnt(void) +{ + int ret = 0, cnt = 0; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_sw_psy(); + if (!psy) + return -ENODEV; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_DP_DM_BQ, &val); + if (!ret) + cnt = val.intval; + + pr_info("pulse_cnt:%d\n", cnt); + return cnt; +} + +static int cp_reset_vbus_volt(void) +{ + int ret; + int qc3p5_reset_vbus_retry = 0; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + if (pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + cp_update_fc_status(); + pr_err("vbat=%d,vbus=%d\n", pm_state.bq2597x.vbat_volt, + pm_state.bq2597x.vbus_volt); + while (pm_state.bq2597x.vbus_volt > 6550) { + cp_tune_vbus_volt(VOLT_DOWN); + cp_update_fc_status(); + qc3p5_reset_vbus_retry++; + usleep_range(10000, 10010); + pr_err("qc3p5_reset_vbus_retry=%d,vbus=%d\n", + qc3p5_reset_vbus_retry, + pm_state.bq2597x.vbus_volt); + if (qc3p5_reset_vbus_retry > 300) { + pr_err("Failed to reset qc3.5 adapter volt to 6.55v or less\n"); + break; + } + } + } else { + psy = cp_get_sw_psy(); + if (!psy) + return -ENODEV; + + val.intval = POWER_SUPPLY_DP_DM_FORCE_5V; + + ret = power_supply_set_property(psy, POWER_SUPPLY_PROP_DP_DM_BQ, + &val); + + pr_err("reset vbus volt %s\n", ret ? "fail" : "successfully"); + } + + return ret; +} + +static int cp_get_usb_type(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_usb_psy(); + if (!psy) + return -ENODEV; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_REAL_TYPE, &val); + if (!ret) + pm_state.usb_type = val.intval; + + return ret; +} + +static int cp_get_usb_present(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_usb_psy(); + if (!psy) + return -ENODEV; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_PRESENT, &val); + if (!ret) + pm_state.usb_present = val.intval; + + return ret; +} + +static int cp_get_qc_hvdcp3_type(void) +{ + int ret; + struct power_supply *psy; + union power_supply_propval val = { + 0, + }; + + psy = cp_get_usb_psy(); + if (!psy) + return -ENODEV; + + ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_HVDCP3_TYPE, + &val); + if (!ret) + pm_state.hvdcp3_type = val.intval; + pr_info("hvdcp3 type %s\n", pm_state.hvdcp3_type); + return ret; +} + +#define TAPER_TIMEOUT 10 +#define IBUS_CHANGE_TIMEOUT 5 +static int cp_flash2_charge(unsigned int port) +{ + static int ibus_limit, ibat_limit; + int thermal_level = 0; + uint16_t effective_fcc_val = cp_get_effective_fcc_val(pm_state); + uint16_t effective_ibus_val = effective_fcc_val / 2; + if (ibus_limit == 0) + ibus_limit = pm_state.ibus_lmt_curr; + ibus_limit = min(effective_ibus_val, pm_state.ibus_lmt_curr); + + qc3_get_bms_fastcharge_mode(); + if (pm_state.bms_fastcharge_mode) + sys_config.bat_volt_lp_lmt = sys_config.ffc_bat_volt_lmt; + pr_info("bat_volt_lp_lmt = %d\n", sys_config.bat_volt_lp_lmt); + pr_info("ibus_limit: %d\n", ibus_limit); + + pr_info("vbus=%d, ibus=%d, vbat=%d, ibat=%d, ibus_target_val=%d\n", + pm_state.bq2597x.vbus_volt, pm_state.bq2597x.ibus_curr, + pm_state.bq2597x.vbat_volt, pm_state.bq2597x.ibat_curr, + effective_ibus_val); + qc3_get_batt_current_thermal_level(&thermal_level); + qc3_check_slowly_charging_enabled(); + + pm_state.is_temp_out_fc2_range = qc3_disable_cp_by_jeita_status(); + pr_info("is_temp_out_fc2_range:%d\n", pm_state.is_temp_out_fc2_range); + + pr_info("bq2597x bat_ovp_fault: %d,bat_ocp_fault =%d,bus_ovp_fault=%d,bus_ocp_fault=%d,bat_ucp_alarm=%d,vbat_reg=%d\n", + pm_state.bq2597x.bat_ovp_fault, pm_state.bq2597x.bat_ocp_fault, + pm_state.bq2597x.bus_ovp_fault, pm_state.bq2597x.bus_ocp_fault, + pm_state.bq2597x.bat_ucp_alarm, pm_state.bq2597x.vbat_reg); + ibat_limit = min(effective_fcc_val, sys_config.bat_curr_lp_lmt); + if (!pm_state.batt_cell_volt_triggered) { + cp_get_batt_capacity(); + if (pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + if (pm_state.bq2597x.vbat_volt >= 4250 || + pm_state.capacity > 40) { + sys_config.ibus_minus_deviation_val = + HVDCP3P5_IBUS_MINUS_DEV_VAL; + sys_config.ibus_plus_deviation_val = + HVDCP3P5_IBUS_PLUS_DEV_VAL; + sys_config.ibat_minus_deviation_val = + HVDCP3P5_IBAT_MINUS_DEV_VAL + 100; + sys_config.ibat_plus_deviation_val = + HVDCP3P5_IBAT_PLUS_DEV_VAL - 50; + pm_state.batt_cell_volt_triggered = true; + pr_info("for qc3.5, cell_vbat > 4250mv or soc > 40%, modify bq adjust params\n"); + } + } else if (pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3) { + if (pm_state.bq2597x.vbat_volt >= 4200 || + pm_state.capacity > 29) { + sys_config.ibus_minus_deviation_val = + HVDCP3_IBUS_MINUS_DEV_VAL; + sys_config.ibus_plus_deviation_val = + HVDCP3_IBUS_PLUS_DEV_VAL; + sys_config.ibat_minus_deviation_val = + HVDCP3_IBAT_MINUS_DEV_VAL + 450; + sys_config.ibat_plus_deviation_val = + HVDCP3_IBAT_PLUS_DEV_VAL - 450; + pm_state.batt_cell_volt_triggered = true; + pr_info("for qc3.0, cell_vbat > 4200mv or soc > 29%, modify bq adjust params\n"); + } + } + } + + pr_info("target: t_vbus=%d, t_ibus=%d(m:%d, p:%d), t_vbat=%d, t_ibat=%d(m:%d, p:%d)\n", + 9500, ibus_limit, sys_config.ibus_minus_deviation_val, + sys_config.ibus_plus_deviation_val, sys_config.bat_volt_lp_lmt, + ibat_limit, sys_config.ibat_minus_deviation_val, + sys_config.ibat_plus_deviation_val); + + if (pm_state.bq2597x.vbus_volt < 10000 && + pm_state.bq2597x.ibus_curr < ibus_limit && + !pm_state.bq2597x.bus_ocp_alarm && + !pm_state.bq2597x.bus_ovp_alarm && + pm_state.bq2597x.vbat_volt < sys_config.bat_volt_lp_lmt - 50 && + pm_state.bq2597x.ibat_curr < sys_config.bat_curr_lp_lmt && + pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) + + cp_tune_vbus_volt(VOLT_UP); + + if (pm_state.bq2597x.vbus_volt <= 9500 && + pm_state.bq2597x.ibus_curr < + ibus_limit - sys_config.ibus_minus_deviation_val && + !pm_state.bq2597x.bus_ocp_alarm && + !pm_state.bq2597x.bus_ovp_alarm && + pm_state.bq2597x.vbat_volt < sys_config.bat_volt_lp_lmt - 50 && + pm_state.bq2597x.ibat_curr < + ibat_limit - sys_config.ibat_minus_deviation_val) { + cp_tune_vbus_volt(VOLT_UP); + } + + if (pm_state.bq2597x.bus_ocp_alarm || pm_state.bq2597x.bus_ovp_alarm || + pm_state.bq2597x.vbat_reg || + pm_state.bq2597x.vbat_volt > sys_config.bat_volt_lp_lmt || + pm_state.bq2597x.ibat_curr > + ibat_limit + sys_config.ibat_plus_deviation_val || + pm_state.bq2597x.ibus_curr > + ibus_limit + sys_config.ibus_plus_deviation_val) { + cp_tune_vbus_volt(VOLT_DOWN); + } + + cp_check_fc_enabled(); + + /* battery overheat, stop charge */ + if (pm_state.bq2597x.bat_therm_fault) + return -ADC_ERR; + else if (pm_state.bq2597x.bus_ocp_fault || + pm_state.bq2597x.bat_ovp_fault || + pm_state.bq2597x.bus_ovp_fault) + return -ADC_ERR; + else if (!pm_state.bq2597x.charge_enabled) + return -CP_ENABLE_FAIL; + else if (thermal_level >= MAX_THERMAL_LEVEL || + pm_state.is_temp_out_fc2_range) { + pr_info("thermal level too high or batt temp is out of fc2 range\n"); + return CP_ENABLE_FAIL; + } else if (pm_state.slowly_charging) { + pr_info("slowly charging feature is enabled!\n"); + return CP_ENABLE_FAIL; + } + if (pm_state.bq2597x.vbat_volt > sys_config.bat_volt_lp_lmt - 100 && + pm_state.bq2597x.ibat_curr < sys_config.fc2_taper_current) { + if (fc2_taper_timer++ > TAPER_TIMEOUT) { + fc2_taper_timer = 0; + return TAPER_DONE; + } + } else { + fc2_taper_timer = 0; + } + + return 0; +} + +const unsigned char *pm_state_str[] = { + "CP_STATE_ENTRY", + "CP_STATE_DISCONNECT", + "CP_STATE_SW_ENTRY", + "CP_STATE_SW_ENTRY_2", + // "CP_STATE_SW_ENTRY_3", + "CP_STATE_SW_LOOP", + "CP_STATE_FLASH2_ENTRY", + "CP_STATE_FLASH2_ENTRY_1", + // "CP_STATE_FLASH2_ENTRY_2", + "CP_STATE_FLASH2_ENTRY_3", + // "CP_STATE_FLASH2_GET_PPS_STATUS", + "CP_STATE_FLASH2_TUNE", + "CP_STATE_FLASH2_DELAY", + "CP_STATE_STOP_CHARGE", +}; + +static void cp_move_state(pm_sm_state_t state) +{ +#if 1 + pr_debug("pm_state change:%s -> %s\n", pm_state_str[pm_state.state], + pm_state_str[state]); + pm_state.state_log[pm_state.log_idx] = pm_state.state; + pm_state.log_idx++; + pm_state.log_idx %= PM_STATE_LOG_MAX; +#endif + pm_state.state = state; +} + +void cp_statemachine(unsigned int port) +{ + int ret; + static int tune_vbus_retry, tune_vbus_count, retry_enable_bq_count; + int thermal_level = 0; + static bool recovery; + + if (!pm_state.bq2597x.vbus_pres) { + pm_state.state = CP_STATE_DISCONNECT; + recovery = true; + pr_info("vbus disconnected\n"); + } else if (pm_state.state == CP_STATE_DISCONNECT) { + pr_info("vbus connected\n"); + recovery = true; + pm_state.jeita_triggered = false; + pm_state.is_temp_out_fc2_range = false; + cp_move_state(CP_STATE_ENTRY); + } + + switch (pm_state.state) { + case CP_STATE_DISCONNECT: + if (pm_state.bq2597x.charge_enabled) { + cp_enable_fc(false); + cp_check_fc_enabled(); + } + + if (!pm_state.sw_chager.charge_enabled || + pm_state.sw_chager.charge_limited) { + cp_reset_vbus_volt(); + cp_enable_sw(true); + cp_update_sw_status(); + } + + tune_vbus_count = 0; + retry_enable_bq_count = 0; + pm_state.usb_type = 0; + pm_state.sw_fc2_init_fail = false; + pm_state.sw_near_cv = false; + sys_config.bat_curr_lp_lmt = HVDCP3_CLASS_A_BAT_CURRENT_MA; + sys_config.bus_curr_lp_lmt = HVDCP3_CLASS_A_BUS_CURRENT_MA; + pm_state.ibus_lmt_curr = HVDCP3_CLASS_A_BUS_CURRENT_MA; + sys_config.ibus_minus_deviation_val = HVDCP3_IBUS_MINUS_DEV_VAL; + sys_config.ibus_plus_deviation_val = HVDCP3_IBUS_PLUS_DEV_VAL; + sys_config.ibat_minus_deviation_val = HVDCP3_IBAT_MINUS_DEV_VAL; + sys_config.ibat_plus_deviation_val = HVDCP3_IBAT_PLUS_DEV_VAL; + pm_state.batt_cell_volt_triggered = false; + cp_set_qc_bus_protections(HVDCP3_NONE); + break; + + case CP_STATE_ENTRY: + cp_get_usb_type(); + cp_get_batt_capacity(); + qc3_get_batt_current_thermal_level(&thermal_level); + qc3_check_slowly_charging_enabled(); + pm_state.is_temp_out_fc2_range = + qc3_disable_cp_by_jeita_status(); + pr_info("is_temp_out_fc2_range:%d\n", + pm_state.is_temp_out_fc2_range); + + if (pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3 || + pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + pr_info("vbus_volt:%d\n", pm_state.bq2597x.vbus_volt); + cp_reset_vbus_volt(); + msleep(100); + if (thermal_level >= MAX_THERMAL_LEVEL || + pm_state.slowly_charging || + pm_state.is_temp_out_fc2_range) { + cp_move_state(CP_STATE_SW_ENTRY); + pr_info("thermal too high or batt temp out of range or slowly charging, waiting...\n"); + } else if (pm_state.bq2597x.vbat_volt < + sys_config.min_vbat_start_flash2) { + cp_move_state(CP_STATE_SW_ENTRY); + } else if (pm_state.bq2597x.vbat_volt > + sys_config.bat_volt_lp_lmt - 100 || + pm_state.capacity >= HIGH_CAPACITY_TRH) { + pm_state.sw_near_cv = true; + cp_move_state(CP_STATE_SW_ENTRY); + } else { + cp_move_state(CP_STATE_FLASH2_ENTRY); + } + } + break; + + case CP_STATE_SW_ENTRY: + cp_reset_vbus_volt(); + if (pm_state.bq2597x.charge_enabled) { + cp_enable_fc(false); + cp_check_fc_enabled(); + } + + if (!pm_state.bq2597x.charge_enabled) + cp_move_state(CP_STATE_SW_ENTRY_2); + break; + + case CP_STATE_SW_ENTRY_2: + pr_info("enable sw charger and check enable\n"); + cp_enable_sw(true); + cp_update_sw_status(); + if (pm_state.sw_chager.charge_enabled) + cp_move_state(CP_STATE_SW_LOOP); + break; + + case CP_STATE_SW_LOOP: + qc3_get_batt_current_thermal_level(&thermal_level); + if (retry_enable_bq_count >= 5) { + pr_info("retry_enable_bq_count=%d\n", + retry_enable_bq_count); + break; + } + + pm_state.is_temp_out_fc2_range = + qc3_disable_cp_by_jeita_status(); + qc3_check_slowly_charging_enabled(); + if (thermal_level < MAX_THERMAL_LEVEL && + !pm_state.slowly_charging && + !pm_state.is_temp_out_fc2_range && recovery) { + if (tune_vbus_count >= 2) { + pr_info("unsupport qc3, use sw charging\n"); + break; + } + tune_vbus_count++; + pr_info("thermal or batt temp recovery...\n"); + recovery = false; + } else { + pr_info("thermal(%d) too high or batt temp out of range\n", + thermal_level); + } + cp_get_batt_capacity(); + if (pm_state.bq2597x.vbat_volt > + sys_config.bat_volt_lp_lmt - 100 || + pm_state.capacity >= HIGH_CAPACITY_TRH) { + pm_state.sw_near_cv = true; + } else { + pr_info("capacity(%d) too high or vbat_volt(%d) too low.\n", + pm_state.capacity, pm_state.bq2597x.vbat_volt); + } + if (!pm_state.sw_near_cv && !recovery) { + if (pm_state.bq2597x.vbat_volt > + sys_config.min_vbat_start_flash2) { + pr_info("battery volt: %d is ok, proceeding to flash charging...\n", + pm_state.bq2597x.vbat_volt); + cp_move_state(CP_STATE_FLASH2_ENTRY); + } + } + break; + + case CP_STATE_FLASH2_ENTRY: + if (!pm_state.sw_chager.charge_limited) { + cp_limit_sw(true); + cp_update_sw_status(); + } + + if (pm_state.sw_chager.charge_limited) { + cp_move_state(CP_STATE_FLASH2_ENTRY_1); + tune_vbus_retry = 0; + } + + cp_get_qc_hvdcp3_type(); + if (pm_state.hvdcp3_type == HVDCP3_CLASSB_27W) { + sys_config.bat_curr_lp_lmt = + HVDCP3_CLASS_B_BAT_CURRENT_MA; + sys_config.bus_curr_lp_lmt = + HVDCP3_CLASS_B_BUS_CURRENT_MA; + pm_state.ibus_lmt_curr = sys_config.bus_curr_lp_lmt; + cp_set_qc_bus_protections(HVDCP3_CLASSB_27W); + } else if (pm_state.hvdcp3_type == HVDCP3_CLASSA_18W) { + sys_config.bat_curr_lp_lmt = + HVDCP3_CLASS_A_BAT_CURRENT_MA; + sys_config.bus_curr_lp_lmt = + HVDCP3_CLASS_A_BUS_CURRENT_MA; + pm_state.ibus_lmt_curr = sys_config.bus_curr_lp_lmt; + cp_set_qc_bus_protections(HVDCP3_CLASSA_18W); + } else if (pm_state.hvdcp3_type == + HVDCP3P5_CLASSB_27W) { // QC3.5 27W + sys_config.ibus_minus_deviation_val = + HVDCP3P5_IBUS_MINUS_DEV_VAL; + sys_config.ibus_plus_deviation_val = + HVDCP3P5_IBUS_PLUS_DEV_VAL; + sys_config.ibat_minus_deviation_val = + HVDCP3P5_IBAT_MINUS_DEV_VAL; + sys_config.ibat_plus_deviation_val = + HVDCP3P5_IBAT_PLUS_DEV_VAL; + sys_config.bat_curr_lp_lmt = + HVDCP3P5_CLASS_B_BAT_CURRENT_MA; + sys_config.bus_curr_lp_lmt = + HVDCP3P5_CLASS_B_BUS_CURRENT_MA; + pm_state.ibus_lmt_curr = sys_config.bus_curr_lp_lmt; + cp_set_qc_bus_protections(HVDCP3P5_CLASSB_27W); + } else if (pm_state.hvdcp3_type == + HVDCP3P5_CLASSA_18W) { // QC3.5 18W + sys_config.ibus_minus_deviation_val = + HVDCP3P5_IBUS_MINUS_DEV_VAL; + sys_config.ibus_plus_deviation_val = + HVDCP3P5_IBUS_PLUS_DEV_VAL; + sys_config.ibat_minus_deviation_val = + HVDCP3P5_IBAT_MINUS_DEV_VAL; + sys_config.ibat_plus_deviation_val = + HVDCP3P5_IBAT_PLUS_DEV_VAL; + sys_config.bat_curr_lp_lmt = + HVDCP3P5_CLASS_A_BAT_CURRENT_MA; + sys_config.bus_curr_lp_lmt = + HVDCP3P5_CLASS_A_BUS_CURRENT_MA; + pm_state.ibus_lmt_curr = sys_config.bus_curr_lp_lmt; + cp_set_qc_bus_protections(HVDCP3P5_CLASSA_18W); + } else { + cp_set_qc_bus_protections(HVDCP3_NONE); + } + break; + + case CP_STATE_FLASH2_ENTRY_1: + cp_update_fc_status(); + if (sys_config.qc3p5_supported) { + if (pm_state.bq2597x.bus_error_status == + VBUS_ERROR_LOW || + pm_state.bq2597x.vbus_volt < + (pm_state.bq2597x.vbat_volt * 2 + + VBUS_COMP)) { + tune_vbus_retry = cp_get_qc_pulse_cnt(); + tune_vbus_retry++; + cp_tune_vbus_volt(VOLT_UP); + pr_info("vbus:%d, retry_times:%d, tuning...\n", + pm_state.bq2597x.vbus_volt, + tune_vbus_retry); + } else { + pr_err("vbus:%d, tuned above expected voltage, retry_times:%d\n", + pm_state.bq2597x.vbus_volt, + tune_vbus_retry); + cp_move_state(CP_STATE_FLASH2_ENTRY_3); + break; + } + if ((pm_state.usb_type == + POWER_SUPPLY_TYPE_USB_HVDCP_3 && + tune_vbus_retry > MAX_PLUSE_COUNT_ALLOWED) || + (pm_state.usb_type == + POWER_SUPPLY_TYPE_USB_HVDCP_3P5 && + tune_vbus_retry > + MAX_HVDCP3P5_PLUSE_COUNT_ALLOWED)) { + pr_err("Failed to tune adapter volt into valid range, charge with switching charger\n"); + pm_state.sw_fc2_init_fail = true; + cp_move_state(CP_STATE_SW_ENTRY); + } + break; + + } else { + if (pm_state.bq2597x.vbus_volt < + (pm_state.bq2597x.vbat_volt * 2 + BUS_VOLT_INIT_UP - + 50)) { + tune_vbus_retry++; + cp_tune_vbus_volt(VOLT_UP); + } else { + pr_err("voltage tuned above expected voltage, retry %d times\n", + tune_vbus_retry); + cp_move_state(CP_STATE_FLASH2_ENTRY_3); + break; + } + + if (tune_vbus_retry > 23) { + pr_err("Failed to tune adapter volt into valid range, charge with switching charger\n"); + pm_state.sw_fc2_init_fail = true; + cp_move_state(CP_STATE_SW_ENTRY); + } + break; + } + + case CP_STATE_FLASH2_ENTRY_3: + if (sys_config.qc3p5_supported) { + if (pm_state.bq2597x.bus_error_status == + VBUS_ERROR_HIGH || + pm_state.bq2597x.vbus_volt > + (pm_state.bq2597x.vbat_volt * 2 + + BUS_VOLT_INIT_UP + 200)) { + pr_err("vbus=%d, too high to open cp switcher, decrease it.\n", + pm_state.bq2597x.vbus_volt); + cp_tune_vbus_volt(VOLT_DOWN); + } else if (pm_state.bq2597x.bus_error_status == + VBUS_ERROR_LOW) { + pr_err("vbus=%d, too low to open cp switcher, increase it.\n", + pm_state.bq2597x.vbus_volt); + cp_tune_vbus_volt(VOLT_UP); + } else { + pr_err("vbat volt is ok, enable flash charging\n"); + if (!pm_state.bq2597x.charge_enabled) { + cp_enable_fc(true); + cp_check_fc_enabled(); + if (pm_state.bq2597x.charge_enabled) { + if (retry_enable_bq_count > 0) + retry_enable_bq_count = + 0; + cp_move_state( + CP_STATE_FLASH2_TUNE); + cp_enable_sw(false); + cp_update_sw_status(); + } else { + retry_enable_bq_count++; + if (retry_enable_bq_count < 5) + cp_move_state( + CP_STATE_FLASH2_ENTRY_3); + else + cp_move_state( + CP_STATE_SW_ENTRY); + } + } + ibus_lmt_change_timer = 0; + fc2_taper_timer = 0; + } + break; + } else { + if (pm_state.bq2597x.vbus_volt > + (pm_state.bq2597x.vbat_volt * 2 + BUS_VOLT_INIT_UP + + 200)) { + pr_err("vbat volt is too high, wait it down\n"); + /* voltage is too high, wait for voltage down, keep charge disabled to discharge */ + } else { + pr_err("vbat volt is ok, enable flash charging\n"); + if (!pm_state.bq2597x.charge_enabled) { + cp_enable_fc(true); + cp_check_fc_enabled(); + if (pm_state.bq2597x.charge_enabled) { + if (retry_enable_bq_count > 0) + retry_enable_bq_count = + 0; + cp_move_state( + CP_STATE_FLASH2_TUNE); + cp_enable_sw(false); + cp_update_sw_status(); + } else { + retry_enable_bq_count++; + if (retry_enable_bq_count < 5) + cp_move_state( + CP_STATE_FLASH2_ENTRY_3); + else + cp_move_state( + CP_STATE_SW_ENTRY); + } + } + ibus_lmt_change_timer = 0; + fc2_taper_timer = 0; + } + break; + } + + case CP_STATE_FLASH2_TUNE: + ret = cp_flash2_charge(port); + if (ret == -ADC_ERR) { + pr_err("Move to stop charging:%d\n", ret); + cp_move_state(CP_STATE_STOP_CHARGE); + break; + } else if (ret == -CP_ENABLE_FAIL || ret == TAPER_DONE) { + pr_err("Move to switch charging:%d\n", ret); + cp_move_state(CP_STATE_SW_ENTRY); + break; + } else if (ret == CP_ENABLE_FAIL) { + tune_vbus_count = 0; + pr_err("Move to switch charging, will try to recover to flash charging:%d\n", + ret); + recovery = true; + cp_move_state(CP_STATE_SW_ENTRY); + } else { // normal tune adapter output + cp_move_state(CP_STATE_FLASH2_DELAY); + } + break; + + case CP_STATE_FLASH2_DELAY: + cp_move_state(CP_STATE_FLASH2_TUNE); + break; + + case CP_STATE_STOP_CHARGE: + pr_err("Stop charging\n"); + if (pm_state.bq2597x.charge_enabled) { + cp_enable_fc(false); + cp_check_fc_enabled(); + } + if (pm_state.sw_chager.charge_enabled) { + cp_enable_sw(false); + cp_update_sw_status(); + } + break; + + default: + pr_err("No state defined! Move to stop charging\n"); + cp_move_state(CP_STATE_STOP_CHARGE); + break; + } +} + +static void cp_workfunc(struct work_struct *work) +{ + cp_get_usb_type(); + + cp_update_sw_status(); + cp_update_fc_status(); + + cp_statemachine(0); + + cp_get_usb_present(); + pr_info("pm_state.usb_present: %d\n", pm_state.usb_present); + /* check whether usb is present */ + if (pm_state.usb_present == 0) { + cp_set_qc_bus_protections(HVDCP3_NONE); +#ifdef CONFIG_CHARGER_LN8000 + pm_state.state = CP_STATE_DISCONNECT; +#endif + return; + } + + if (pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3) { + schedule_delayed_work(&pm_state.qc3_pm_work, HZ); + } else if (pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + schedule_delayed_work(&pm_state.qc3_pm_work, + msecs_to_jiffies(PM_WORK_TIME_100MS)); + } +} + +static int cp_qc30_notifier_call(struct notifier_block *nb, unsigned long ev, + void *v) +{ + struct power_supply *psy = v; + static bool usb_hvdcp3_on; + if (ev != PSY_EVENT_PROP_CHANGED) + return NOTIFY_OK; + + if (strcmp(psy->desc->name, "usb") == 0) { + cp_get_usb_type(); + if (pm_state.usb_type == POWER_SUPPLY_TYPE_USB_HVDCP_3) { + if (!usb_hvdcp3_on) { + schedule_delayed_work(&pm_state.qc3_pm_work, + 3 * HZ); + usb_hvdcp3_on = true; + } else { + schedule_delayed_work(&pm_state.qc3_pm_work, + msecs_to_jiffies(300)); + } + } else if (sys_config.qc3p5_supported && + pm_state.usb_type == + POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + if (!usb_hvdcp3_on) { + schedule_delayed_work(&pm_state.qc3_pm_work, + HZ); + usb_hvdcp3_on = true; + } else { + schedule_delayed_work(&pm_state.qc3_pm_work, + msecs_to_jiffies(100)); + } + } else if (pm_state.usb_type == POWER_SUPPLY_TYPE_UNKNOWN && + usb_hvdcp3_on == true) { + cancel_delayed_work(&pm_state.qc3_pm_work); + schedule_delayed_work(&pm_state.qc3_pm_work, 0); + pr_info("pm_state.usb_type: %d\n", pm_state.usb_type); + usb_hvdcp3_on = false; + } + } + + return NOTIFY_OK; +} + +static int cp_qc30_register_notifier(struct cp_qc30_data *chip) +{ + int rc; + + chip->nb.notifier_call = cp_qc30_notifier_call; + rc = power_supply_reg_notifier(&chip->nb); + if (rc < 0) { + pr_err("Couldn't register psy notifier rc = %d\n", rc); + return rc; + } + + return 0; +} + +static int cp_qc30_parse_dt(struct cp_qc30_data *chip) +{ + struct device_node *node = chip->dev->of_node; + int rc = 0; + + if (!node) { + pr_err("device tree node missing\n"); + return -EINVAL; + } + + rc = of_property_read_u32(node, "mi,qc3-bat-volt-max", + &chip->bat_volt_max); + if (rc < 0) + pr_err("qc3-bat-volt-max property missing, use default val\n"); + else + sys_config.bat_volt_lp_lmt = chip->bat_volt_max; + + rc = of_property_read_u32(node, "mi,qc3-ffc-bat-volt-max", + &chip->ffc_bat_volt_max); + if (rc < 0) + pr_err("qc3-ffc-bat-volt-max property missing, use default\n"); + else + sys_config.ffc_bat_volt_lmt = chip->ffc_bat_volt_max; + + rc = of_property_read_u32(node, "mi,qc3-bat-curr-max", + &chip->bat_curr_max); + if (rc < 0) + pr_err("qc3-bat-curr-max property missing, use default val\n"); + else + sys_config.bat_curr_lp_lmt = chip->bat_curr_max; + + rc = of_property_read_u32(node, "mi,qc3-bus-volt-max", + &chip->bus_volt_max); + if (rc < 0) + pr_err("qc3-bus-volt-max property missing, use default val\n"); + else + sys_config.bus_volt_lp_lmt = chip->bus_volt_max; + + rc = of_property_read_u32(node, "mi,qc3-bus-curr-max", + &chip->bus_curr_max); + if (rc < 0) + pr_err("qc3-bus-curr-max property missing, use default val\n"); + else + sys_config.bus_curr_lp_lmt = chip->bus_curr_max; + + chip->qc3p5_supported = + of_property_read_bool(node, "mi,support-qc3p5-without-smb"); + sys_config.qc3p5_supported = chip->qc3p5_supported; + + chip->cp_sec_enable = of_property_read_bool(node, "mi,cp-sec-enable"); + + sys_config.cp_sec_enable = chip->cp_sec_enable; + + return rc; +} + +static int cp_qc30_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct cp_qc30_data *chip; + + pr_info("%s enter\n", __func__); + + chip = devm_kzalloc(dev, sizeof(struct cp_qc30_data), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = dev; + ret = cp_qc30_parse_dt(chip); + if (ret < 0) { + pr_err("Couldn't parse device tree rc=%d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, chip); + + pm_state.state = CP_STATE_DISCONNECT; + pm_state.usb_type = POWER_SUPPLY_TYPE_UNKNOWN; + pm_state.ibus_lmt_curr = sys_config.bus_curr_lp_lmt; + + INIT_DELAYED_WORK(&pm_state.qc3_pm_work, cp_workfunc); + + cp_qc30_register_notifier(chip); + + pr_info("charge pump qc3 probe\n"); + + return ret; +} + +static int cp_qc30_remove(struct platform_device *pdev) +{ + cancel_delayed_work(&pm_state.qc3_pm_work); + return 0; +} + +static const struct of_device_id cp_qc30_of_match[] = { + { + .compatible = "xiaomi,cp-qc30", + }, + {}, +}; + +static struct platform_driver cp_qc30_driver = { + .driver = { + .name = "cp-qc30", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(cp_qc30_of_match), + }, + .probe = cp_qc30_probe, + .remove = cp_qc30_remove, +}; + +static int __init cp_qc30_init(void) +{ + return platform_driver_register(&cp_qc30_driver); +} + +late_initcall(cp_qc30_init); + +static void __exit cp_qc30_exit(void) +{ + return platform_driver_unregister(&cp_qc30_driver); +} +module_exit(cp_qc30_exit); + +MODULE_AUTHOR("Fei Jiang"); +MODULE_DESCRIPTION("Xiaomi cp qc30"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/ti/cp_qc30.h b/drivers/power/supply/ti/cp_qc30.h new file mode 100644 index 000000000000..660c1f6e76dc --- /dev/null +++ b/drivers/power/supply/ti/cp_qc30.h @@ -0,0 +1,251 @@ +/* + * cp_qc30.h + * + */ + +#ifndef SRC_PDLIB_USB_PD_POLICY_MANAGER_H_ +#define SRC_PDLIB_USB_PD_POLICY_MANAGER_H_ +#include +#include +#include + +typedef enum { + CP_STATE_ENTRY, + CP_STATE_DISCONNECT, + CP_STATE_SW_ENTRY, + CP_STATE_SW_ENTRY_2, + // CP_STATE_SW_ENTRY_3, + CP_STATE_SW_LOOP, + CP_STATE_FLASH2_ENTRY, + CP_STATE_FLASH2_ENTRY_1, + // CP_STATE_FLASH2_ENTRY_2, + CP_STATE_FLASH2_ENTRY_3, + // CP_STATE_FLASH2_GET_PPS_STATUS, + CP_STATE_FLASH2_TUNE, + CP_STATE_FLASH2_DELAY, + CP_STATE_STOP_CHARGE, +} pm_sm_state_t; + +#define BAT_OVP_FAULT_SHIFT 0 +#define BAT_OCP_FAULT_SHIFT 1 +#define BUS_OVP_FAULT_SHIFT 2 +#define BUS_OCP_FAULT_SHIFT 3 +#define BAT_THERM_FAULT_SHIFT 4 +#define BUS_THERM_FAULT_SHIFT 5 +#define DIE_THERM_FAULT_SHIFT 6 + +#define BAT_OVP_FAULT_MASK (1 << BAT_OVP_FAULT_SHIFT) +#define BAT_OCP_FAULT_MASK (1 << BAT_OCP_FAULT_SHIFT) +#define BUS_OVP_FAULT_MASK (1 << BUS_OVP_FAULT_SHIFT) +#define BUS_OCP_FAULT_MASK (1 << BUS_OCP_FAULT_SHIFT) +#define BAT_THERM_FAULT_MASK (1 << BAT_THERM_FAULT_SHIFT) +#define BUS_THERM_FAULT_MASK (1 << BUS_THERM_FAULT_SHIFT) +#define DIE_THERM_FAULT_MASK (1 << DIE_THERM_FAULT_SHIFT) + +#define BAT_OVP_ALARM_SHIFT 0 +#define BAT_OCP_ALARM_SHIFT 1 +#define BUS_OVP_ALARM_SHIFT 2 +#define BUS_OCP_ALARM_SHIFT 3 +#define BAT_THERM_ALARM_SHIFT 4 +#define BUS_THERM_ALARM_SHIFT 5 +#define DIE_THERM_ALARM_SHIFT 6 +#define BAT_UCP_ALARM_SHIFT 7 + +#define BAT_OVP_ALARM_MASK (1 << BAT_OVP_ALARM_SHIFT) +#define BAT_OCP_ALARM_MASK (1 << BAT_OCP_ALARM_SHIFT) +#define BUS_OVP_ALARM_MASK (1 << BUS_OVP_ALARM_SHIFT) +#define BUS_OCP_ALARM_MASK (1 << BUS_OCP_ALARM_SHIFT) +#define BAT_THERM_ALARM_MASK (1 << BAT_THERM_ALARM_SHIFT) +#define BUS_THERM_ALARM_MASK (1 << BUS_THERM_ALARM_SHIFT) +#define DIE_THERM_ALARM_MASK (1 << DIE_THERM_ALARM_SHIFT) +#define BAT_UCP_ALARM_MASK (1 << BAT_UCP_ALARM_SHIFT) + +#define VBAT_REG_STATUS_SHIFT 0 +#define IBAT_REG_STATUS_SHIFT 1 + +#define VBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT) +#define IBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT) + +enum hvdcp3_type { + HVDCP3_NONE = 0, + HVDCP3_CLASSA_18W, + HVDCP3_CLASSB_27W, + HVDCP3P5_CLASSA_18W, + HVDCP3P5_CLASSB_27W, +}; + +#define HVDCP3_CLASS_B_BAT_CURRENT_MA 5400 +#define HVDCP3_CLASS_B_BUS_CURRENT_MA 2700 +#define HVDCP3_CLASS_A_BAT_CURRENT_MA 3600 +#define HVDCP3_CLASS_A_BUS_CURRENT_MA 2100 +#define MAX_PLUSE_COUNT_ALLOWED 23 +#define HVDCP3_IBUS_MINUS_DEV_VAL 550 +#define HVDCP3_IBUS_PLUS_DEV_VAL 200 +#define HVDCP3_IBAT_MINUS_DEV_VAL 600 +#define HVDCP3_IBAT_PLUS_DEV_VAL 500 + +/* QC3.5 */ +#define HVDCP3P5_CLASS_B_BAT_CURRENT_MA 5400 +#define HVDCP3P5_CLASS_B_BUS_CURRENT_MA 2700 +#define HVDCP3P5_CLASS_A_BAT_CURRENT_MA 4200 +#define HVDCP3P5_CLASS_A_BUS_CURRENT_MA 2100 +#define MAX_HVDCP3P5_PLUSE_COUNT_ALLOWED 300 +#define HVDCP3P5_IBUS_MINUS_DEV_VAL 200 +#define HVDCP3P5_IBUS_PLUS_DEV_VAL 150 +#define HVDCP3P5_IBAT_MINUS_DEV_VAL 300 +#define HVDCP3P5_IBAT_PLUS_DEV_VAL 200 + +#define MAX_THERMAL_LEVEL 13 +/* jeita related */ +#define JEITA_WARM_THR 450 +#define JEITA_COOL_NOT_ALLOW_CP_THR 100 +/* + * add hysteresis for warm threshold to avoid flash + * charge and normal charge switch frequently at + * the warm threshold + */ +#define JEITA_HYSTERESIS 20 + +#define HIGH_CAPACITY_TRH 90 +#define PM_WORK_TIME_100MS 100 + +struct flash2_policy { + int down_steps; + uint16_t volt_hysteresis; +}; + +#if 0 +struct bq2597x_cfg { + uint16_t bat_ovp_th; + uint16_t bat_ocp_th; + uint16_t bus_ovp_th; + uint16_t bus_ocp_th; + + + uint16_t bat_ucp_alarm_th; + + uint16_t bat_ovp_alarm_th; + uint16_t bat_ocp_alarm_th; + uint16_t bus_ovp_alarm_th; + uint16_t bus_ocp_alarm_th; + + uint16_t ac_ovp_th; + uint16_t ts_bus_fault_th; + uint16_t ts_bat_fault_th; + uint16_t ts_die_fault_th; + + /* software protection threshold*/ + int32_t sw_bat_ovp_th; + int32_t sw_bat_ocp_th; + int32_t sw_bus_ovp_th; + int32_t sw_bus_ocp_th; + int32_t sw_bat_ucp_th; + int32_t taper_current; +}; +#endif + +struct bq2597x { + bool charge_enabled; + + bool batt_pres; + bool vbus_pres; + + /* alarm/fault status */ + bool bat_ovp_fault; + bool bat_ocp_fault; + bool bus_ovp_fault; + bool bus_ocp_fault; + + bool bat_ovp_alarm; + bool bat_ocp_alarm; + bool bus_ovp_alarm; + bool bus_ocp_alarm; + + bool bat_ucp_alarm; + + bool bat_therm_alarm; + bool bus_therm_alarm; + bool die_therm_alarm; + + bool bat_therm_fault; + bool bus_therm_fault; + bool die_therm_fault; + + bool therm_shutdown_flag; + bool therm_shutdown_stat; + + bool vbat_reg; + bool ibat_reg; + + int vout_volt; + int vbat_volt; + int vbus_volt; + int ibat_curr; + int ibus_curr; + + int bat_temp; + int bus_temp; + int die_temp; + int bus_error_status; +}; + +struct sw_charger { + bool charge_enabled; + bool charge_limited; +}; + +#define PM_STATE_LOG_MAX 32 +typedef struct { + bool sw_is_charging; + bool flash2_is_charging; + bool sw_near_cv; + bool sw_fc2_init_fail; + bool bms_fastcharge_mode; + + uint16_t ibus_lmt_curr; + pm_sm_state_t state; //state machine + pm_sm_state_t state_log[PM_STATE_LOG_MAX]; + uint8_t log_idx; + + int usb_type; + int hvdcp3_type; + int usb_present; + int ibat_now; + int capacity; + struct bq2597x bq2597x; + struct sw_charger sw_chager; + struct votable *fcc_votable; + + struct power_supply *fc_psy; + struct power_supply *sw_psy; + struct power_supply *usb_psy; + struct power_supply *bms_psy; + /* jeita or thermal related */ + bool jeita_triggered; + bool batt_cell_volt_triggered; + bool is_temp_out_fc2_range; + bool slowly_charging; + + struct delayed_work qc3_pm_work; +} pm_t; + +struct sys_config { + uint16_t bat_volt_lp_lmt; /*bat volt loop limit*/ + uint16_t ffc_bat_volt_lmt; + uint16_t bat_curr_lp_lmt; + uint16_t bus_volt_lp_lmt; + uint16_t bus_curr_lp_lmt; + uint16_t ibus_plus_deviation_val; + uint16_t ibus_minus_deviation_val; + uint16_t ibat_plus_deviation_val; + uint16_t ibat_minus_deviation_val; + int32_t fc2_taper_current; + + struct flash2_policy flash2_policy; + + uint16_t min_vbat_start_flash2; + bool cp_sec_enable; + bool qc3p5_supported; +}; + +#endif /* SRC_PDLIB_USB_PD_POLICY_MANAGER_H_ */ diff --git a/drivers/power/supply/ti/ln8000_charger.c b/drivers/power/supply/ti/ln8000_charger.c new file mode 100644 index 000000000000..7ecf5e0626f0 --- /dev/null +++ b/drivers/power/supply/ti/ln8000_charger.c @@ -0,0 +1,1826 @@ +/* + * ln8000-charger.c - Charger driver for LIONSEMI LN8000 + * + * Copyright (C) 2021 Lion Semiconductor Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include "ln8000_charger.h" +#include "cp_qc30.h" + +#define ln_err(fmt, ...) \ + do { \ + if (info->dev_role == LN_PRIMARY) \ + printk(KERN_ERR "ln8000@pri: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + else \ + printk(KERN_ERR "ln8000@sec: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + } while (0); + +#define ln_info(fmt, ...) \ + do { \ + if (info->dev_role == LN_PRIMARY) \ + printk(KERN_INFO "ln8000@pri: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + else \ + printk(KERN_INFO "ln8000@sec: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + } while (0); + +#define ln_dbg(fmt, ...) \ + do { \ + if (info->dev_role == LN_PRIMARY) \ + printk(KERN_DEBUG "ln8000@pri: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + else \ + printk(KERN_DEBUG "ln8000@sec: %s: " fmt, __func__, \ + ##__VA_ARGS__); \ + } while (0); + +#define LN8000_REG_PRINT(reg_addr, val) \ + do { \ + ln_info(" --> [%-20s] 0x%02X : 0x%02X\n", #reg_addr, \ + LN8000_REG_##reg_addr, (val) & 0xFF); \ + } while (0); + +#define LN8000_PARSE_PROP(ret, pdata, field, prop, default_prop) \ + do { \ + if (ret) { \ + ln_info("%s = %d (set to default)\n", #field, \ + default_prop); \ + pdata->field = default_prop; \ + } else { \ + ln_info("%s = %d\n", #field, prop); \ + pdata->field = prop; \ + } \ + } while (0); + +#define LN8000_BIT_CHECK(val, idx, desc) \ + if (val & (1 << idx)) \ + ln_info("-> %s\n", desc) +#define LN8000_IS_PRIMARY(info) (info->dev_role == LN_PRIMARY) +#define LN8000_ROLE(info) (LN8000_IS_PRIMARY(info) ? "prim" : "sec ") +#define LN8000_USE_GPIO(pdata) \ + ((pdata != NULL) && (!IS_ERR_OR_NULL(pdata->irq_gpio))) +#define LN8000_STATUS(val, mask) ((val & mask) ? true : false) + +/** + * I2C control functions : when occurred I2C tranfer fault, we + * will retry to it. (default count:3) + */ +#define I2C_RETRY_CNT 3 +static int ln8000_read_reg(struct ln8000_info *info, u8 addr, void *data) +{ + int i, ret = 0; + + mutex_lock(&info->i2c_lock); + for (i = 0; i < I2C_RETRY_CNT; ++i) { + ret = regmap_read(info->regmap, addr, data); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_info("failed-read, reg(0x%02X), ret(%d)\n", addr, + ret); + } else { + break; + } + } + mutex_unlock(&info->i2c_lock); + return ret; +} + +static int ln8000_bulk_read_reg(struct ln8000_info *info, u8 addr, void *data, + int count) +{ + int i, ret = 0; + + mutex_lock(&info->i2c_lock); + for (i = 0; i < I2C_RETRY_CNT; ++i) { + ret = regmap_bulk_read(info->regmap, addr, data, count); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_info("failed-bulk-read, reg(0x%02X, %d bytes), ret(%d)\n", + addr, count, ret); + } else { + break; + } + } + mutex_unlock(&info->i2c_lock); + return ret; +} + +static int ln8000_write_reg(struct ln8000_info *info, u8 addr, u8 data) +{ + int i, ret = 0; + + mutex_lock(&info->i2c_lock); + for (i = 0; i < I2C_RETRY_CNT; ++i) { + ret = regmap_write(info->regmap, addr, data); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_info("failed-write, reg(0x%02X), ret(%d)\n", addr, + ret); + } else { + break; + } + } + mutex_unlock(&info->i2c_lock); + return ret; +} + +static int ln8000_update_reg(struct ln8000_info *info, u8 addr, u8 mask, + u8 data) +{ + int i, ret = 0; + + mutex_lock(&info->i2c_lock); + for (i = 0; i < I2C_RETRY_CNT; ++i) { + ret = regmap_update_bits(info->regmap, addr, mask, data); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_info("failed-update, reg(0x%02X), ret(%d)\n", addr, + ret); + } else { + break; + } + } + mutex_unlock(&info->i2c_lock); + return ret; +} + +/** + * Register control functions + */ +#if 0 +static int ln8000_set_sw_freq(struct ln8000_info *info, unsigned int cfg) +{ + return ln8000_update_reg(info, LN8000_REG_SYS_CTRL, 0xF << 4, cfg << 4); +} +#endif + +static int ln8000_set_vac_ovp(struct ln8000_info *info, unsigned int ovp_th) +{ + u8 cfg; + + if (ovp_th <= 6500000) { + cfg = LN8000_VAC_OVP_6P5V; + } else if (ovp_th <= 11000000) { + cfg = LN8000_VAC_OVP_11V; + } else if (ovp_th <= 12000000) { + cfg = LN8000_VAC_OVP_12V; + } else { + cfg = LN8000_VAC_OVP_13V; + } + + return ln8000_update_reg(info, LN8000_REG_GLITCH_CTRL, 0x3 << 2, + cfg << 2); +} + +/* battery float voltage */ +static int ln8000_set_vbat_float(struct ln8000_info *info, unsigned int cfg) +{ + u8 val; + + if (cfg < LN8000_VBAT_FLOAT_MIN) + val = 0x00; + else if (cfg > LN8000_VBAT_FLOAT_MAX) + val = 0xFF; + else + val = (cfg - LN8000_VBAT_FLOAT_MIN) / LN8000_VBAT_FLOAT_LSB; + + return ln8000_write_reg(info, LN8000_REG_V_FLOAT_CTRL, val); +} + +static int ln8000_set_iin_limit(struct ln8000_info *info, unsigned int cfg) +{ + u8 val = cfg / LN8000_IIN_CFG_LSB; + + ln_info("iin_limit=%dmV(iin_ctrl=0x%x)\n", cfg / 1000, val); + + return ln8000_update_reg(info, LN8000_REG_IIN_CTRL, 0x7F, val); +} + +static int ln8000_set_ntc_alarm(struct ln8000_info *info, unsigned int cfg) +{ + int ret; + + /* update lower bits */ + ret = ln8000_write_reg(info, LN8000_REG_NTC_CTRL, (cfg & 0xFF)); + if (ret < 0) + return ret; + + /* update upper bits */ + ret = ln8000_update_reg(info, LN8000_REG_ADC_CTRL, 0x3, (cfg >> 8)); + return ret; +} + +/* battery voltage OV protection */ +static int ln8000_enable_vbat_ovp(struct ln8000_info *info, bool enable) +{ + u8 val; + + val = (enable) ? 0 : 1; //disable + val <<= LN8000_BIT_DISABLE_VBAT_OV; + + return ln8000_update_reg(info, LN8000_REG_FAULT_CTRL, + BIT(LN8000_BIT_DISABLE_VBAT_OV), val); +} + +static int ln8000_enable_vbat_regulation(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_REGULATION_CTRL, + 0x1 << LN8000_BIT_DISABLE_VFLOAT_LOOP, + !(enable) << LN8000_BIT_DISABLE_VFLOAT_LOOP); +} + +static int ln8000_enable_vbat_loop_int(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_REGULATION_CTRL, + 0x1 << LN8000_BIT_ENABLE_VFLOAT_LOOP_INT, + enable << LN8000_BIT_ENABLE_VFLOAT_LOOP_INT); +} + +/* input current OC protection */ +static int ln8000_enable_iin_ocp(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_FAULT_CTRL, + 0x1 << LN8000_BIT_DISABLE_IIN_OCP, + !(enable) << LN8000_BIT_DISABLE_IIN_OCP); +} + +static int ln8000_enable_iin_regulation(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_REGULATION_CTRL, + 0x1 << LN8000_BIT_DISABLE_IIN_LOOP, + !(enable) << LN8000_BIT_DISABLE_IIN_LOOP); +} + +static int ln8000_enable_iin_loop_int(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_REGULATION_CTRL, + 0x1 << LN8000_BIT_ENABLE_IIN_LOOP_INT, + enable << LN8000_BIT_ENABLE_IIN_LOOP_INT); +} + +static int ln8000_enable_vac_ov(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_FAULT_CTRL, + 0x1 << LN8000_BIT_DISABLE_VAC_OV, + !(enable) << LN8000_BIT_DISABLE_VAC_OV); +} + +static int ln8000_enable_tdie_prot(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_REGULATION_CTRL, + 0x1 << LN8000_BIT_TEMP_MAX_EN, + enable << LN8000_BIT_TEMP_MAX_EN); +} + +static int ln8000_enable_tdie_regulation(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_REGULATION_CTRL, + 0x1 << LN8000_BIT_TEMP_REG_EN, + enable << LN8000_BIT_TEMP_REG_EN); +} + +/* ADC channel enable */ +static int ln8000_set_adc_ch(struct ln8000_info *info, unsigned int ch, + bool enable) +{ + u8 mask; + u8 val; + int ret; + + if ((ch > LN8000_ADC_CH_ALL) || (ch < 1)) + return -EINVAL; + + if (ch == LN8000_ADC_CH_ALL) { + // update all channels + val = (enable) ? 0x3E : 0x00; + ret = ln8000_write_reg(info, LN8000_REG_ADC_CFG, val); + } else { + // update selected channel + mask = 1 << (ch - 1); + val = (enable) ? 1 : 0; + val <<= (ch - 1); + ret = ln8000_update_reg(info, LN8000_REG_ADC_CFG, mask, val); + } + + return ret; +} + +/* BUS temperature monitoring (protection+alarm) */ +static int ln8000_enable_tbus_monitor(struct ln8000_info *info, bool enable) +{ + int ret; + + /* enable BUS monitoring */ + ret = ln8000_update_reg(info, LN8000_REG_RECOVERY_CTRL, 0x1 << 1, + enable << 1); + if (ret < 0) + return ret; + + /* enable BUS ADC channel */ + if (enable) { + ret = ln8000_set_adc_ch(info, LN8000_ADC_CH_TSBUS, true); + } + return ret; +} + +/* BAT temperature monitoring (protection+alarm) */ +static int ln8000_enable_tbat_monitor(struct ln8000_info *info, bool enable) +{ + int ret; + + /* enable BAT monitoring */ + ret = ln8000_update_reg(info, LN8000_REG_RECOVERY_CTRL, 0x1 << 0, + enable << 0); + if (ret < 0) + return ret; + + /* enable BAT ADC channel */ + if (enable) { + ret = ln8000_set_adc_ch(info, LN8000_ADC_CH_TSBAT, true); + } + return ret; +} + +/* watchdog timer */ +static int ln8000_enable_wdt(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x1 << 7, + enable << 7); +} + +#if 0 +static int ln8000_set_wdt(struct ln8000_info *info, unsigned int cfg) +{ + if (cfg >= LN8000_WATCHDOG_MAX) { + cfg = LN8000_WATCHDOG_40SEC; + } + + return ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x3 << 5, cfg << 5); +} +#endif + +/* unplug / reverse-current detection */ +static int ln8000_enable_rcp(struct ln8000_info *info, bool enable) +{ + info->rcp_en = enable; + + return ln8000_update_reg(info, LN8000_REG_SYS_CTRL, + BIT(LN8000_BIT_REV_IIN_DET), + enable << LN8000_BIT_REV_IIN_DET); +} + +/* auto-recovery */ +static int ln8000_enable_auto_recovery(struct ln8000_info *info, bool enable) +{ + return ln8000_update_reg(info, LN8000_REG_RECOVERY_CTRL, 0xF << 4, + ((0xF << 4) * enable)); +} + +static int ln8000_set_adc_mode(struct ln8000_info *info, unsigned int cfg) +{ + return ln8000_update_reg(info, LN8000_REG_ADC_CTRL, 0x7 << 5, cfg << 5); +} + +static int ln8000_set_adc_hib_delay(struct ln8000_info *info, unsigned int cfg) +{ + return ln8000_update_reg(info, LN8000_REG_ADC_CTRL, 0x3 << 3, cfg << 3); +} + +/* check if device has been initialized (by SW) */ +#if defined(LN8000_DUAL_CONFIG) +static bool ln8000_is_sw_init(struct ln8000_info *info) +{ + u32 val; + + ln8000_read_reg(info, LN8000_REG_CHARGE_CTRL, &val); + + return (val >> 7); +} +#endif + +/* grab programmed battery float voltage (uV) */ +static int ln8000_get_vbat_float(struct ln8000_info *info) +{ + int ret, val; + + ret = ln8000_read_reg(info, LN8000_REG_V_FLOAT_CTRL, &val); + if (ret < 0) + return ret; + + return ((val & 0xFF) * LN8000_VBAT_FLOAT_LSB + + LN8000_VBAT_FLOAT_MIN); //uV +} + +/* grab programmed input current limit (uA) */ +static int ln8000_get_iin_limit(struct ln8000_info *info) +{ + int ret, val; + int iin; + + ret = ln8000_read_reg(info, LN8000_REG_IIN_CTRL, &val); + if (ret < 0) + return ret; + + iin = ((val & 0x7F) * LN8000_IIN_CFG_LSB); + + if (iin < LN8000_IIN_CFG_MIN) { + iin = LN8000_IIN_CFG_MIN; + } + + return iin; +} + +/* enable/disable STANDBY */ +static inline void ln8000_sw_standby(struct ln8000_info *info, bool standby) +{ + u8 val = (standby) ? BIT(LN8000_BIT_STANDBY_EN) : 0x00; + ln8000_update_reg(info, LN8000_REG_SYS_CTRL, BIT(LN8000_BIT_STANDBY_EN), + val); +} + +/* Convert Raw ADC Code */ +static void ln8000_convert_adc_code(struct ln8000_info *info, unsigned int ch, + u8 *sts, int *result) +{ + int adc_raw; // raw ADC value + int adc_final; // final (converted) ADC value + + switch (ch) { + case LN8000_ADC_CH_VOUT: + adc_raw = ((sts[1] & 0xFF) << 2) | ((sts[0] & 0xC0) >> 6); + adc_final = adc_raw * LN8000_ADC_VOUT_STEP; //uV + break; + case LN8000_ADC_CH_VIN: + adc_raw = ((sts[1] & 0x3F) << 4) | ((sts[0] & 0xF0) >> 4); + adc_final = adc_raw * LN8000_ADC_VIN_STEP; //uV + break; + case LN8000_ADC_CH_VBAT: + adc_raw = ((sts[1] & 0x03) << 8) | (sts[0] & 0xFF); + adc_final = adc_raw * LN8000_ADC_VBAT_STEP; //uV + break; + case LN8000_ADC_CH_VAC: + adc_raw = (((sts[1] & 0x0F) << 6) | ((sts[0] & 0xFC) >> 2)) + + LN8000_ADC_VAC_OS; + adc_final = adc_raw * LN8000_ADC_VAC_STEP; //uV + break; + case LN8000_ADC_CH_IIN: + adc_raw = ((sts[1] & 0x03) << 8) | (sts[0] & 0xFF); + adc_final = adc_raw * LN8000_ADC_IIN_STEP; //uA + break; + case LN8000_ADC_CH_DIETEMP: + adc_raw = ((sts[1] & 0x0F) << 6) | ((sts[0] & 0xFC) >> 2); + adc_final = (935 - adc_raw) * LN8000_ADC_DIETEMP_STEP / + LN8000_ADC_DIETEMP_DENOM; //dC + if (adc_final > LN8000_ADC_DIETEMP_MAX) + adc_final = LN8000_ADC_DIETEMP_MAX; + else if (adc_final < LN8000_ADC_DIETEMP_MIN) + adc_final = LN8000_ADC_DIETEMP_MIN; + break; + case LN8000_ADC_CH_TSBAT: + adc_raw = ((sts[1] & 0x3F) << 4) | ((sts[0] & 0xF0) >> 4); + adc_final = adc_raw * LN8000_ADC_NTCV_STEP; //(NTC) uV + break; + case LN8000_ADC_CH_TSBUS: + adc_raw = ((sts[1] & 0xFF) << 2) | ((sts[0] & 0xC0) >> 6); + adc_final = adc_raw * LN8000_ADC_NTCV_STEP; //(NTC) uV + break; + default: + adc_raw = -EINVAL; + adc_final = -EINVAL; + break; + } + + *result = adc_final; + return; +} + +static void ln8000_print_regmap(struct ln8000_info *info) +{ + const u8 print_reg_num = + (LN8000_REG_CHARGE_CTRL - LN8000_REG_INT1_MSK) + 1; + u32 regs[64] = { + 0x0, + }; + char temp_buf[128] = { + 0, + }; + int i, ret; + + for (i = 0; i < print_reg_num; ++i) { + ret = ln8000_read_reg(info, LN8000_REG_INT1_MSK + i, ®s[i]); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_err("fail to read reg for print_regmap[%d]\n", i); + regs[i] = 0xFF; + } + sprintf(temp_buf + strlen(temp_buf), "0x%02X[0x%02X],", + LN8000_REG_INT1_MSK + i, regs[i]); + if (((i + 1) % 10 == 0) || ((i + 1) == print_reg_num)) { + ln_info("%s\n", temp_buf); + memset(temp_buf, 0x0, sizeof(temp_buf)); + } + } +} + +/** + * LN8000 device driver control routines + */ +static int ln8000_check_status(struct ln8000_info *info) +{ + u8 val[4]; + + if (ln8000_bulk_read_reg(info, LN8000_REG_SYS_STS, val, 4) < 0) { + return -EINVAL; + } + + mutex_lock(&info->data_lock); + + info->vbat_regulated = + LN8000_STATUS(val[0], LN8000_MASK_VFLOAT_LOOP_STS); + info->iin_regulated = LN8000_STATUS(val[0], LN8000_MASK_IIN_LOOP_STS); + info->pwr_status = + val[0] & + (LN8000_MASK_BYPASS_ENABLED | LN8000_MASK_SWITCHING_ENABLED | + LN8000_MASK_STANDBY_STS | LN8000_MASK_SHUTDOWN_STS); + info->tdie_fault = LN8000_STATUS(val[1], LN8000_MASK_TEMP_MAX_STS); + info->tdie_alarm = + LN8000_STATUS(val[1], LN8000_MASK_TEMP_REGULATION_STS); + if (!info->pdata->tbat_mon_disable || !info->pdata->tbus_mon_disable) { + info->tbus_tbat_fault = LN8000_STATUS( + val[1], LN8000_MASK_NTC_SHUTDOWN_STS); //tbus or tbat + info->tbus_tbat_alarm = LN8000_STATUS( + val[1], LN8000_MASK_NTC_ALARM_STS); //tbus or tbat + } + info->iin_rc = LN8000_STATUS(val[1], LN8000_MASK_REV_IIN_STS); + + info->wdt_fault = LN8000_STATUS(val[2], LN8000_MASK_WATCHDOG_TIMER_STS); + info->vbat_ov = LN8000_STATUS(val[2], LN8000_MASK_VBAT_OV_STS); + info->vac_unplug = LN8000_STATUS(val[2], LN8000_MASK_VAC_UNPLUG_STS); + info->vac_ov = LN8000_STATUS(val[2], LN8000_MASK_VAC_OV_STS); + info->vbus_ov = LN8000_STATUS(val[2], LN8000_MASK_VIN_OV_STS); + info->volt_qual = !(LN8000_STATUS(val[2], 0x7F)); + if (info->volt_qual == 1 && info->chg_en == 1) { + info->volt_qual = !(LN8000_STATUS(val[3], 1 << 5)); + if (info->volt_qual == 0) { + ln_info("volt_fault_detected (volt_qual=%d)\n", + info->volt_qual); + /* clear latched status */ + ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x1 << 2, + 0x1 << 2); + ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x1 << 2, + 0x0 << 2); + } + } + info->iin_oc = LN8000_STATUS(val[3], LN8000_MASK_IIN_OC_DETECTED); + + mutex_unlock(&info->data_lock); + + return 0; +} + +static void ln8000_irq_sleep(struct ln8000_info *info, int suspend) +{ + if (info->client->irq <= 0) + return; + + if (suspend) { + ln_info("disable/suspend IRQ\n"); + disable_irq(info->client->irq); + } else { + ln_info("enable/resume IRQ\n"); + enable_irq(info->client->irq); + } +} + +#if 0 +static void ln8000_soft_reset(struct ln8000_info *info) +{ + ln8000_write_reg(info, LN8000_REG_LION_CTRL, 0xC6); + + ln8000_irq_sleep(info, 1); + + ln_info("(%s) Trigger soft-reset\n", LN8000_ROLE(info)); + ln8000_update_reg(info, LN8000_REG_BC_OP_2, 0x1 << 0, 0x1 << 0); + msleep(5 * 2); /* ln8000 min wait time 5ms (after POR) */ + + ln8000_irq_sleep(info, 0); +} +#endif + +static void ln8000_update_opmode(struct ln8000_info *info) +{ + unsigned int op_mode; + u32 val; + + /* chack mode status */ + ln8000_read_reg(info, LN8000_REG_SYS_STS, &val); + + if (val & LN8000_MASK_SHUTDOWN_STS) { + op_mode = LN8000_OPMODE_STANDBY; + } else if (val & LN8000_MASK_STANDBY_STS) { + op_mode = LN8000_OPMODE_STANDBY; + } else if (val & LN8000_MASK_SWITCHING_ENABLED) { + op_mode = LN8000_OPMODE_SWITCHING; + } else if (val & LN8000_MASK_BYPASS_ENABLED) { + op_mode = LN8000_OPMODE_BYPASS; + } else { + op_mode = LN8000_OPMODE_UNKNOWN; + } + + if (op_mode != info->op_mode) { + /* IC already has been entered standby_mode, need to trigger standbt_en bit */ + if (op_mode == LN8000_OPMODE_STANDBY) { + ln8000_update_reg(info, LN8000_REG_SYS_CTRL, + 1 << LN8000_BIT_STANDBY_EN, + 1 << LN8000_BIT_STANDBY_EN); + ln_info("forced trigger standby_en\n"); + info->chg_en = 0; + } + ln_info("op_mode has been changed [%d]->[%d] (sys_st=0x%x)\n", + info->op_mode, op_mode, val); + info->op_mode = op_mode; + } + + return; +} + +static int ln8000_change_opmode(struct ln8000_info *info, + unsigned int target_mode) +{ + int ret = 0; + u8 val, msk = (0x1 << LN8000_BIT_STANDBY_EN | + 0x1 << LN8000_BIT_EN_1TO1); + + switch (target_mode) { + case LN8000_OPMODE_STANDBY: + val = (1 << LN8000_BIT_STANDBY_EN); + break; + case LN8000_OPMODE_BYPASS: + val = (0 << LN8000_BIT_STANDBY_EN) | (1 << LN8000_BIT_EN_1TO1); + break; + case LN8000_OPMODE_SWITCHING: + val = (0 << LN8000_BIT_STANDBY_EN) | (0 << LN8000_BIT_EN_1TO1); + break; + default: + ln_err("invalid index (target_mode=%d)\n", target_mode); + return -EINVAL; + } + ret = ln8000_update_reg(info, LN8000_REG_SYS_CTRL, msk, val); + if (IS_ERR_VALUE((unsigned long)ret)) { + return -EINVAL; + } + ln_info("changed opmode [%d] -> [%d]\n", info->op_mode, target_mode); + info->op_mode = target_mode; + + return 0; +} + +static int ln8000_init_device(struct ln8000_info *info) +{ + unsigned int vbat_float; + + /* config default charging paramter by dt */ + vbat_float = info->pdata->bat_ovp_th * 100 / + 102; /* ovp thershold = v_float x 1.02 */ + vbat_float = (vbat_float / 1000) * 1000; + ln_info("bat_ovp_th=%d, vbat_float=%d\n", info->pdata->bat_ovp_th, + vbat_float); + ln8000_set_vbat_float(info, vbat_float); + info->vbat_ovp_alarm_th = info->pdata->bat_ovp_alarm_th; + ln8000_set_vac_ovp(info, info->pdata->bus_ovp_th); + info->vin_ovp_alarm_th = info->pdata->bus_ovp_alarm_th; + ln8000_set_iin_limit(info, info->pdata->bus_ocp_th - 700000); + info->iin_ocp_alarm_th = info->pdata->bus_ocp_alarm_th; + ln8000_set_ntc_alarm(info, info->pdata->ntc_alarm_cfg); + + ln8000_update_reg(info, LN8000_REG_REGULATION_CTRL, 0x3 << 2, + LN8000_NTC_SHUTDOWN_CFG); + ln8000_enable_auto_recovery(info, 0); + + /* config charging protection */ + ln8000_enable_vbat_ovp(info, !info->pdata->vbat_ovp_disable); + ln8000_enable_vbat_regulation(info, !info->pdata->vbat_reg_disable); + ln8000_enable_vbat_loop_int(info, !info->pdata->vbat_reg_disable); + ln8000_enable_iin_ocp(info, !info->pdata->iin_ocp_disable); + ln8000_enable_iin_regulation(info, !info->pdata->iin_reg_disable); + ln8000_enable_iin_loop_int(info, !info->pdata->iin_reg_disable); + ln8000_enable_tdie_regulation(info, !info->pdata->tdie_reg_disable); + ln8000_enable_tdie_prot(info, !info->pdata->tdie_prot_disable); + ln8000_enable_rcp(info, 0); + ln8000_change_opmode(info, LN8000_OPMODE_STANDBY); + ln8000_enable_vac_ov(info, 1); + + /* wdt : disable, adc : shutdown mode */ + ln8000_enable_wdt(info, false); + ln8000_set_adc_mode(info, ADC_SHUTDOWN_MODE); //disable before updating + ln8000_set_adc_hib_delay(info, ADC_HIBERNATE_4S); + ln8000_set_adc_ch(info, LN8000_ADC_CH_ALL, true); + ln8000_enable_tbus_monitor( + info, !info->pdata->tbus_mon_disable); //+enables ADC ch + ln8000_enable_tbat_monitor( + info, !info->pdata->tbat_mon_disable); //+enables ADC ch + ln8000_set_adc_mode(info, ADC_AUTO_HIB_MODE); + + /* mark sw initialized (used CHARGE_CTRL bit:7) */ + ln8000_update_reg(info, LN8000_REG_CHARGE_CTRL, 0x1 << 7, 0x1 << 7); + ln8000_write_reg(info, LN8000_REG_THRESHOLD_CTRL, 0x0E); + + ln8000_print_regmap(info); + + ln_info(" done.\n"); + + return 0; +} + +/** + * Support power_supply platform for charger block. + * propertis are compatible by Xiaomi platform + */ +static int ln8000_get_adc_data(struct ln8000_info *info, unsigned int ch, + int *result) +{ + int ret; + u8 sts[2]; + + /* pause adc update */ + ret = ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x1 << 1, + 0x1 << 1); + if (ret < 0) { + ln_err("fail to update bit PAUSE_ADC_UPDATE:1 (ret=%d)\n", ret); + return ret; + } + + switch (ch) { + case LN8000_ADC_CH_VOUT: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC04_STS, sts, 2); + break; + case LN8000_ADC_CH_VIN: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC03_STS, sts, 2); + break; + case LN8000_ADC_CH_VBAT: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC06_STS, sts, 2); + break; + case LN8000_ADC_CH_VAC: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC02_STS, sts, 2); + break; + case LN8000_ADC_CH_IIN: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC01_STS, sts, 2); + break; + case LN8000_ADC_CH_DIETEMP: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC07_STS, sts, 2); + break; + case LN8000_ADC_CH_TSBAT: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC08_STS, sts, 2); + break; + case LN8000_ADC_CH_TSBUS: + ret = ln8000_bulk_read_reg(info, LN8000_REG_ADC09_STS, sts, 2); + break; + default: + ln_err("invalid ch(%d)\n", ch); + ret = -EINVAL; + break; + } + + /* resume adc update */ + ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x1 << 1, 0x0 << 1); + + if (IS_ERR_VALUE((unsigned long)ret) == false) { + ln8000_convert_adc_code(info, ch, sts, result); + } + + return ret; +} + +static int psy_chg_get_charging_enabled(struct ln8000_info *info) +{ + int enabled = 0; /* disabled */ + + if (info->chg_en) { + ln8000_update_opmode(info); + if (info->op_mode >= LN8000_OPMODE_BYPASS) { + enabled = 1; + } + } + + return enabled; +} + +static int psy_chg_get_ti_alarm_status(struct ln8000_info *info) +{ + int alarm; + unsigned int v_offset; + bool bus_ovp, bus_ocp, bat_ovp; + u8 val[4]; + + ln8000_check_status(info); + ln8000_get_adc_data(info, LN8000_ADC_CH_VIN, &info->vbus_uV); + ln8000_get_adc_data(info, LN8000_ADC_CH_IIN, &info->iin_uA); + ln8000_get_adc_data(info, LN8000_ADC_CH_VBAT, &info->vbat_uV); + + bus_ovp = (info->vbus_uV > info->vin_ovp_alarm_th) ? 1 : 0; + bus_ocp = (info->iin_uA > info->iin_ocp_alarm_th) ? 1 : 0; + bat_ovp = (info->vbat_uV > info->vbat_ovp_alarm_th) ? 1 : 0; + + /* BAT alarm status not support (ovp/ocp/ucp) */ + alarm = ((bus_ovp << BUS_OVP_ALARM_SHIFT) | + (bus_ocp << BUS_OCP_ALARM_SHIFT) | + (bat_ovp << BAT_OVP_ALARM_SHIFT) | + (info->tbus_tbat_alarm << BAT_THERM_ALARM_SHIFT) | + (info->tbus_tbat_alarm << BUS_THERM_ALARM_SHIFT) | + (info->tdie_alarm << DIE_THERM_ALARM_SHIFT)); + + v_offset = info->vbus_uV - (info->vbat_uV * 2); + /* after charging-enabled, When the input current rises above rcp_th(over 200mA), it activates rcp. */ + if (info->chg_en && !(info->rcp_en)) { + if (info->iin_uA > 200000 && v_offset > 300000) { + ln8000_enable_rcp(info, 1); + ln_info("enabled rcp\n"); + } + } + /* If an unplug event occurs when vbus voltage lower then vin_start_up_th, switch to standby mode. */ + if (info->chg_en && !(info->rcp_en)) { + if (v_offset < 100000) { + ln8000_change_opmode(info, LN8000_OPMODE_STANDBY); + ln_info("forced change standby_mode for prevent reverse current\n"); + info->chg_en = 0; + } + } + + ln8000_bulk_read_reg(info, LN8000_REG_SYS_STS, val, 4); + ln_info("adc_vin=%d(th=%d), adc_iin=%d(th=%d), adc_vbat=%d(th=%d), v_offset=%d\n", + info->vbus_uV / 1000, info->vin_ovp_alarm_th / 1000, + info->iin_uA / 1000, info->iin_ocp_alarm_th / 1000, + info->vbat_uV / 1000, info->vbat_ovp_alarm_th / 1000, + v_offset / 1000); + ln_info("st:0x%x:0x%x:0x%x:0x%x alarm=0x%x\n", val[0], val[1], val[2], + val[3], alarm); + + return alarm; +} + +static int psy_chg_get_ti_fault_status(struct ln8000_info *info) +{ + int fault; + + ln8000_check_status(info); + + /* BAT ocp fault status not suppport */ + fault = ((info->vbat_ov << BAT_OVP_FAULT_SHIFT) | + (info->vbus_ov << BUS_OVP_FAULT_SHIFT) | + (info->iin_oc << BUS_OCP_FAULT_SHIFT) | + (info->tbus_tbat_fault << BAT_THERM_FAULT_SHIFT) | + (info->tbus_tbat_fault << BUS_THERM_FAULT_SHIFT) | + (info->tdie_fault << DIE_THERM_FAULT_SHIFT)); + + if (info->volt_qual == 0) { + fault |= ((1 << BAT_OVP_FAULT_SHIFT) | + (1 << BUS_OVP_FAULT_SHIFT)); + } + + if (fault) { + ln_info("fault=0x%x\n", fault); + } + + return fault; +} + +static int ln8000_charger_get_property(struct power_supply *psy, + enum power_supply_property prop, + union power_supply_propval *val) +{ + struct ln8000_info *info = power_supply_get_drvdata(psy); + + switch (prop) { + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + val->intval = psy_chg_get_charging_enabled(info); + break; + case POWER_SUPPLY_PROP_STATUS: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = info->usb_present; + break; + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + val->intval = ln8000_get_vbat_float(info); + break; + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: + val->intval = ln8000_get_iin_limit(info); + break; + case POWER_SUPPLY_PROP_TI_BATTERY_PRESENT: + ln8000_get_adc_data(info, LN8000_ADC_CH_VBAT, &info->vbat_uV); + if (info->vbat_uV > LN8000_ADC_VBAT_MIN) { + val->intval = 1; /* detected battery */ + } else { + val->intval = 0; /* non-detected battery */ + } + break; + case POWER_SUPPLY_PROP_TI_VBUS_PRESENT: + ln8000_check_status(info); + val->intval = !(info->vac_unplug); + break; + case POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE: + ln8000_get_adc_data(info, LN8000_ADC_CH_VBAT, &info->vbat_uV); + val->intval = info->vbat_uV / 1000; + break; + case POWER_SUPPLY_PROP_TI_BATTERY_CURRENT: /* ln8000 not support IBAT_ADC */ + ln8000_get_adc_data(info, LN8000_ADC_CH_IIN, &info->iin_uA); + val->intval = + (info->iin_uA * 2) / 1000; /* return to IBUS_ADC x 2 */ + break; + case POWER_SUPPLY_PROP_TI_BATTERY_TEMPERATURE: + if (info->pdata->tbat_mon_disable) { + val->intval = 0; + } else { + ln8000_get_adc_data(info, LN8000_ADC_CH_TSBAT, + &info->tbat_uV); + val->intval = info->tbat_uV; + ln_info("ti_battery_temperature: adc_tbat=%d\n", + val->intval); + } + break; + case POWER_SUPPLY_PROP_TI_BUS_VOLTAGE: + ln8000_get_adc_data(info, LN8000_ADC_CH_VIN, &info->vbus_uV); + val->intval = info->vbus_uV / 1000; + break; + case POWER_SUPPLY_PROP_TI_BUS_CURRENT: + ln8000_get_adc_data(info, LN8000_ADC_CH_IIN, &info->iin_uA); + val->intval = info->iin_uA / 1000; + break; + case POWER_SUPPLY_PROP_TI_BUS_TEMPERATURE: + if (info->pdata->tbus_mon_disable) { + val->intval = 0; + } else { + ln8000_get_adc_data(info, LN8000_ADC_CH_TSBUS, + &info->tbus_uV); + val->intval = info->tbus_uV; + ln_info("ti_bus_temperature: adc_tbus=%d\n", + val->intval); + } + break; + case POWER_SUPPLY_PROP_TI_DIE_TEMPERATURE: + ln8000_get_adc_data(info, LN8000_ADC_CH_DIETEMP, + &info->tdie_dC); + val->intval = info->tdie_dC; + ln_info("ti_die_temperature: adc_tdie=%d\n", val->intval); + break; + case POWER_SUPPLY_PROP_TI_ALARM_STATUS: + val->intval = psy_chg_get_ti_alarm_status(info); + break; + case POWER_SUPPLY_PROP_TI_FAULT_STATUS: + val->intval = psy_chg_get_ti_fault_status(info); + break; + case POWER_SUPPLY_PROP_TI_REG_STATUS: + ln8000_check_status(info); + val->intval = + ((info->vbat_regulated << VBAT_REG_STATUS_SHIFT) | + /* ln8000 not support ibat_reg, we are can be ibus_reg */ + (info->iin_regulated << IBAT_REG_STATUS_SHIFT)); + if (val->intval) { + ln_info("ti_reg_status: intavl=0x%x\n", val->intval); + } + break; + case POWER_SUPPLY_PROP_MODEL_NAME: + val->strval = "ln8000"; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int psy_chg_set_charging_enable(struct ln8000_info *info, int val) +{ + int op_mode; + + if (val) { + ln_info("start charging\n"); + op_mode = LN8000_OPMODE_SWITCHING; + } else { + ln_info("stop charging\n"); + op_mode = LN8000_OPMODE_STANDBY; + } + + /* when the start-up to charging, we need to disabled rcp. */ + ln8000_enable_rcp(info, 0); + + ln8000_change_opmode(info, op_mode); + msleep(10); + ln8000_update_opmode(info); + + ln8000_print_regmap(info); + info->chg_en = val; + + ln_info("op_mode=%d\n", info->op_mode); + + return 0; +} + +static int psy_chg_set_present(struct ln8000_info *info, int val) +{ + bool usb_present = (bool)val; + + if (usb_present != info->usb_present) { + ln_info("changed usb_present [%d] -> [%d]\n", info->usb_present, + usb_present); + if (usb_present) { + ln8000_init_device(info); + } + info->usb_present = usb_present; + } + + return 0; +} + +static int psy_chg_set_bus_protection_for_qc3(struct ln8000_info *info, + int hvdcp3_type) +{ + ln_info("hvdcp3_type: %d\n", hvdcp3_type); + + if (hvdcp3_type == HVDCP3_CLASSA_18W) { + ln8000_set_vac_ovp(info, BUS_OVP_FOR_QC); + info->vin_ovp_alarm_th = BUS_OVP_ALARM_FOR_QC; + ln8000_set_iin_limit(info, BUS_OCP_FOR_QC_CLASS_A - 700000); + info->iin_ocp_alarm_th = BUS_OCP_ALARM_FOR_QC_CLASS_A; + } else if (hvdcp3_type == HVDCP3_CLASSB_27W) { + ln8000_set_vac_ovp(info, BUS_OVP_FOR_QC); + info->vin_ovp_alarm_th = BUS_OVP_ALARM_FOR_QC; + ln8000_set_iin_limit(info, BUS_OCP_FOR_QC_CLASS_B - 700000); + info->iin_ocp_alarm_th = BUS_OCP_ALARM_FOR_QC_CLASS_B; + } else if (hvdcp3_type == HVDCP3P5_CLASSA_18W) { + ln8000_set_vac_ovp(info, BUS_OVP_FOR_QC); + info->vin_ovp_alarm_th = BUS_OVP_ALARM_FOR_QC; + ln8000_set_iin_limit(info, BUS_OCP_FOR_QC3P5_CLASS_A - 700000); + info->iin_ocp_alarm_th = BUS_OCP_ALARM_FOR_QC3P5_CLASS_A; + } else if (hvdcp3_type == HVDCP3P5_CLASSB_27W) { + ln8000_set_vac_ovp(info, BUS_OVP_FOR_QC); + info->vin_ovp_alarm_th = BUS_OVP_ALARM_FOR_QC; + ln8000_set_iin_limit(info, BUS_OCP_FOR_QC3P5_CLASS_B - 700000); + info->iin_ocp_alarm_th = BUS_OCP_ALARM_FOR_QC3P5_CLASS_B; + } else { + ln8000_set_vac_ovp(info, info->pdata->bus_ovp_th); + info->vin_ovp_alarm_th = info->pdata->bus_ovp_alarm_th; + ln8000_set_iin_limit(info, info->pdata->bus_ocp_th - 700000); + info->iin_ocp_alarm_th = info->pdata->bus_ocp_alarm_th; + } + + ln8000_print_regmap(info); + + return 0; +} + +static int ln8000_charger_set_property(struct power_supply *psy, + enum power_supply_property prop, + const union power_supply_propval *val) +{ + struct ln8000_info *info = power_supply_get_drvdata(psy); + int ret = 0; + + switch (prop) { + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + ret = psy_chg_set_charging_enable(info, val->intval); + break; + case POWER_SUPPLY_PROP_PRESENT: + ret = psy_chg_set_present(info, val->intval); + break; + case POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3: + ret = psy_chg_set_bus_protection_for_qc3(info, val->intval); + break; + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + ret = ln8000_set_vbat_float(info, val->intval); + break; + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: + ret = ln8000_set_iin_limit(info, val->intval); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int ln8000_charger_is_writeable(struct power_supply *psy, + enum power_supply_property prop) +{ + int ret; + + switch (prop) { + case POWER_SUPPLY_PROP_PRESENT: + case POWER_SUPPLY_PROP_CHARGING_ENABLED: + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: + case POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3: + ret = 1; + break; + default: + ret = 0; + break; + } + + return ret; +} + +static enum power_supply_property ln8000_charger_props[] = { + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_CHARGING_ENABLED, + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE, + POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, + /* support TI extended propertis */ + POWER_SUPPLY_PROP_TI_BATTERY_PRESENT, + POWER_SUPPLY_PROP_TI_VBUS_PRESENT, + POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, + POWER_SUPPLY_PROP_TI_BATTERY_CURRENT, + POWER_SUPPLY_PROP_TI_BATTERY_TEMPERATURE, + POWER_SUPPLY_PROP_TI_BUS_VOLTAGE, + POWER_SUPPLY_PROP_TI_BUS_CURRENT, + POWER_SUPPLY_PROP_TI_BUS_TEMPERATURE, + POWER_SUPPLY_PROP_TI_DIE_TEMPERATURE, + POWER_SUPPLY_PROP_TI_ALARM_STATUS, + POWER_SUPPLY_PROP_TI_FAULT_STATUS, + POWER_SUPPLY_PROP_TI_REG_STATUS, + POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3, + POWER_SUPPLY_PROP_MODEL_NAME, +}; + +static int read_reg(void *data, u64 *val) +{ + struct ln8000_info *info = data; + int ret; + unsigned int temp; + + ret = regmap_read(info->regmap, info->debug_address, &temp); + if (ret) { + ln_err("Unable to read reg(0x%02X), ret=%d\n", + info->debug_address, ret); + return -EAGAIN; + } + *val = temp; + return 0; +} + +static int write_reg(void *data, u64 val) +{ + struct ln8000_info *info = data; + int ret; + u8 temp = (u8)val; + + ret = regmap_write(info->regmap, info->debug_address, temp); + if (ret) { + ln_err("Unable to write reg(0x%02X), data(0x%02X), ret=%d\n", + info->debug_address, temp, ret); + return -EAGAIN; + } + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(register_debug_ops, read_reg, write_reg, "0x%02llX\n"); + +static int ln8000_create_debugfs_entries(struct ln8000_info *info) +{ + struct dentry *ent; + + info->debug_root = debugfs_create_dir( + (LN8000_IS_PRIMARY(info) ? "ln8000" : "ln8000-secondary"), + NULL); + if (!info->debug_root) { + ln_err("unable to create debug dir\n"); + return -ENOENT; + } else { + ent = debugfs_create_x32("address", S_IFREG | S_IWUSR | S_IRUGO, + info->debug_root, + &(info->debug_address)); + if (!ent) { + ln_err("unable to create address debug file\n"); + return -ENOENT; + } + ent = debugfs_create_file("data", S_IFREG | S_IWUSR | S_IRUGO, + info->debug_root, info, + ®ister_debug_ops); + if (!ent) { + ln_err("unable to create data debug file\n"); + return -ENOENT; + } + } + + return 0; +} + +/** + * Support IRQ interface + */ +static int ln8000_read_int_value(struct ln8000_info *info, u32 *reg_val) +{ + int ret; + + /* pause INT updates */ + ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x1, 0x1); + mdelay(1); + + ret = ln8000_read_reg(info, LN8000_REG_INT1, reg_val); + + /* resume INT updates */ + ln8000_update_reg(info, LN8000_REG_TIMER_CTRL, 0x1, 0x0); + + return ret; +} + +static void vac_ov_control_work(struct work_struct *work) +{ + struct ln8000_info *info = + container_of(work, struct ln8000_info, vac_ov_work.work); + int i, cnt, ta_detached, delay = 50; + u32 sys_st; + bool enable_vac_ov = 1; + + ta_detached = 0; + cnt = 5000 / delay; + for (i = 0; i < cnt; ++i) { + ln8000_get_adc_data(info, LN8000_ADC_CH_VIN, &info->vbus_uV); + ln8000_read_reg(info, LN8000_REG_SYS_STS, &sys_st); + + if (enable_vac_ov) { + /* Check ADC_VIN during the 5sec, if vin higher then 10V, disable to vac_ov */ + if (info->vbus_uV > 10000000) { + enable_vac_ov = 0; + ln8000_enable_vac_ov(info, enable_vac_ov); + ln_info("vac_ov=disable, vin=%dmV, i=%d, cnt=%d, delay=%d\n", + info->vbus_uV / 1000, i, cnt, delay); + } + } else { + /* After disabled vac_ov, if ADC_VIN lower then 7V goto the terminate work */ + if (info->vbus_uV < 7000000) { + enable_vac_ov = 1; + ln_info("vac_ov=enable, vin=%dmV, i=%d, cnt=%d, delay=%d\n", + info->vbus_uV / 1000, i, cnt, delay); + goto teminate_work; + } + } + /* If judged 3 times by TA disconnected, goto the terminate work */ + if (sys_st == 0x1) { /* it's means entered shutdown mode */ + ta_detached += 1; + ln_info("sys_st=0x%x, ta_detached=%d\n", sys_st, + ta_detached); + if (ta_detached > 2) { + goto teminate_work; + } + } + + msleep(delay); + } + +teminate_work: + ln8000_enable_vac_ov(info, 1); + info->vac_ov_work_on = 0; +} + +static void check_vac_ov_work(struct ln8000_info *info) +{ + u32 sys_st, fault1_st; + + ln8000_read_reg(info, LN8000_REG_SYS_STS, &sys_st); + ln8000_read_reg(info, LN8000_REG_FAULT1_STS, &fault1_st); + + if (sys_st == 0x02 && fault1_st == 0x00) { /* connected valid VBUS */ + if (info->vac_ov_work_on == 0) { /* vac_ov_work not worked */ + schedule_delayed_work(&info->vac_ov_work, + msecs_to_jiffies(0)); + info->vac_ov_work_on = 1; + ln_info("schedule_work : vac_ov_work\n"); + } + } +} + +static irqreturn_t ln8000_interrupt_handler(int irq, void *data) +{ + struct ln8000_info *info = data; + u32 int_reg, int_msk; + u8 masked_int; + int ret; + ln_err("ln8000_interrupt_handler enter!\n"); + ret = ln8000_read_int_value(info, &int_reg); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_err("fail to read INT reg (ret=%d)\n", ret); + return IRQ_NONE; + } + ln8000_read_reg(info, LN8000_REG_INT1_MSK, &int_msk); + masked_int = int_reg & ~int_msk; + + ln_info("int_reg=0x%x, int_msk=0x%x, masked_int=0x%x\n", int_reg, + int_msk, masked_int); + + ln8000_print_regmap(info); + LN8000_BIT_CHECK(masked_int, 7, "(INT) FAULT_INT"); + LN8000_BIT_CHECK(masked_int, 6, "(INT) NTC_PROT_INT"); + LN8000_BIT_CHECK(masked_int, 5, "(INT) CHARGE_PHASE_INT"); + LN8000_BIT_CHECK(masked_int, 4, "(INT) MODE_INT"); + LN8000_BIT_CHECK(masked_int, 3, "(INT) REV_CURR_INT"); + LN8000_BIT_CHECK(masked_int, 2, "(INT) TEMP_INT"); + LN8000_BIT_CHECK(masked_int, 1, "(INT) ADC_DONE_INT"); + LN8000_BIT_CHECK(masked_int, 0, "(INT) TIMER_INT"); + ln8000_check_status(info); + + if (masked_int & LN8000_MASK_FAULT_INT) { /* FAULT_INT */ + if (info->volt_qual) { + ln_info("connected to power_supplier\n"); + } else { + ln_info("FAULT_INT has occurred\n"); + } + } + if (masked_int & LN8000_MASK_NTC_PROT_INT) { /* NTC_PROT_INT */ + ln_info("NTC_PROT_INT has occurred(ntc_fault=%d, ntc_alarm=%d)\n", + info->tbus_tbat_fault, info->tbus_tbat_alarm); + } + if (masked_int & LN8000_MASK_CHARGE_PHASE_INT) { /* CHARGE_PHASE_INT */ + if (info->vbat_regulated) { + ln_info("CHARGE_PHASE_INT: VFLOAT regulated\n"); + } else if (info->iin_regulated) { + ln_info("CHARGE_PHASE_INT: IIN regulated\n"); + } + } + if (masked_int & LN8000_MASK_MODE_INT) { /* MODE_INT */ + switch (info->pwr_status) { + case LN8000_MASK_BYPASS_ENABLED: + ln_info("MODE_INT: device in BYPASS mode\n"); + break; + case LN8000_MASK_SWITCHING_ENABLED: + ln_info("MODE_INT: device in SWITCHING mode\n"); + break; + case LN8000_MASK_STANDBY_STS: + ln_info("MODE_INT: device in STANDBY mode\n"); + break; + case LN8000_MASK_SHUTDOWN_STS: + ln_info("MODE_INT: device in SHUTDOWN mode\n"); + break; + default: + ln_info("MODE_INT: device in unknown mode\n"); + break; + } + } + if (masked_int & LN8000_MASK_TEMP_INT) { /* TEMP_INT */ + ln_info("TEMP_INT has occurred(tdie_fault=%d, tdie_alarm=%d)\n", + info->tdie_fault, info->tdie_alarm); + } + if (masked_int & LN8000_MASK_TIMER_INT) { /* TIMER_INT */ + ln_info("Watchdog timer has expired(wdt_fault=%d)\n", + info->wdt_fault); + } + + check_vac_ov_work(info); + + return IRQ_HANDLED; +} + +static int ln8000_irq_init(struct ln8000_info *info) +{ + const struct ln8000_platform_data *pdata = info->pdata; + int ret; + u8 mask; + u32 int_reg; + + if (LN8000_IS_PRIMARY(info)) { + if (info->pdata->irq_gpio) { + info->client->irq = gpiod_to_irq(pdata->irq_gpio); + if (info->client->irq < 0) { + ln_err("fail to get irq from gpio(irq_gpio=%p)\n", + pdata->irq_gpio) info->client->irq = 0; + return -EINVAL; + } + ln_info("mapped GPIO to irq (%d)\n", info->client->irq); + } + } else { + /* grab IRQ from primary device */ + ln_info("mapped shared GPIO to (primary dev) irq (%d)\n", + info->client->irq); + } + /* interrupt mask setting */ + mask = LN8000_MASK_ADC_DONE_INT | LN8000_MASK_TIMER_INT | + LN8000_MASK_MODE_INT | LN8000_MASK_REV_CURR_INT; + if (info->pdata->tdie_prot_disable && info->pdata->tdie_reg_disable) + mask |= LN8000_MASK_TEMP_INT; + if (info->pdata->iin_reg_disable && info->pdata->vbat_reg_disable) + mask |= LN8000_MASK_CHARGE_PHASE_INT; + if (info->pdata->tbat_mon_disable && info->pdata->tbus_mon_disable) + mask |= LN8000_MASK_NTC_PROT_INT; + ln8000_write_reg(info, LN8000_REG_INT1_MSK, mask); + /* read clear int_reg */ + ret = ln8000_read_int_value(info, &int_reg); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_err("fail to read INT reg (ret=%d)\n", ret); + return IRQ_NONE; + } + ln_info("int1_msk=0x%x\n", mask); + + return 0; +} + +static void determine_initial_status(struct ln8000_info *info) +{ + if (info->client->irq) + ln8000_interrupt_handler(info->client->irq, info); +} + +static const struct of_device_id ln8000_dt_match[] = { + { .compatible = "lionsemi,ln8000", .data = (void *)LN_PRIMARY }, + { .compatible = "lionsemi,ln8000-secondary", + .data = (void *)LN_SECONDARY }, + {}, +}; +MODULE_DEVICE_TABLE(of, ln8000_dt_match); + +static const struct i2c_device_id ln8000_id[] = { { "ln8000", LN_PRIMARY }, + { "ln8000-secondary", + LN_SECONDARY }, + {} }; + +static const struct regmap_config ln8000_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = LN8000_REG_MAX, +}; + +static int ln8000_get_dev_role(struct i2c_client *client) +{ + const struct of_device_id *of_id; + + of_id = of_match_device(of_match_ptr(ln8000_dt_match), &client->dev); + if (of_id == NULL) { + dev_err(&client->dev, "%s: fail to matched of_device_id\n", + __func__); + return -EINVAL; + } + + dev_info(&client->dev, "%s: matched to %s\n", __func__, + of_id->compatible); + + return (int)of_id->data; +} + +static int ln8000_parse_dt(struct ln8000_info *info) +{ + struct device *dev = info->dev; + struct ln8000_platform_data *pdata = info->pdata; + struct device_node *np = dev->of_node; + u32 prop; + int ret; + + if (np == NULL) + return -EINVAL; + + /* first we try to used client->irq */ + if (info->client->irq == 0) { + /* sencond we try to used irq_index info */ + ret = of_property_read_u32(np, "ln8000_charger,irq_index", + &prop); + if (ret < 0) { + ln_err("can't get irq_index(ret=%d)\n", ret); + prop = 0; + } + info->client->irq = prop; + } + ln_info("info->client->irq=%d\n", info->client->irq); + + if (!info->client->irq) { + pdata->irq_gpio = gpiod_get(dev, "irqb", GPIOD_IN); + if (LN8000_USE_GPIO(pdata)) { + ln_info("[gpio] found valid GPIO/IRQ descriptor\n"); + } else { + ln_info("[gpio] unspecified or invalid GPIO descriptor\n"); + pdata->irq_gpio = 0; + } + } + + /* device configuration */ + ret = of_property_read_u32(np, "ln8000_charger,bat-ovp-threshold", + &prop); + LN8000_PARSE_PROP(ret, pdata, bat_ovp_th, (prop * 1000 /*uV*/), + LN8000_BAT_OVP_DEFAULT); + ret = of_property_read_u32(np, "ln8000_charger,bat-ovp-alarm-threshold", + &prop); + LN8000_PARSE_PROP(ret, pdata, bat_ovp_alarm_th, (prop * 1000 /*uV*/), + 0); + ret = of_property_read_u32(np, "ln8000_charger,bus-ovp-threshold", + &prop); + LN8000_PARSE_PROP(ret, pdata, bus_ovp_th, (prop * 1000 /*uV*/), + LN8000_BUS_OVP_DEFAULT); + ret = of_property_read_u32(np, "ln8000_charger,bus-ovp-alarm-threshold", + &prop); + LN8000_PARSE_PROP(ret, pdata, bus_ovp_alarm_th, (prop * 1000 /*uA*/), + 0); + ret = of_property_read_u32(np, "ln8000_charger,bus-ocp-threshold", + &prop); + LN8000_PARSE_PROP(ret, pdata, bus_ocp_th, (prop * 1000 /*uA*/), + LN8000_BUS_OCP_DEFAULT); + ret = of_property_read_u32(np, "ln8000_charger,bus-ocp-alarm-threshold", + &prop); + LN8000_PARSE_PROP(ret, pdata, bus_ocp_alarm_th, (prop * 1000 /*uA*/), + 0); + ret = of_property_read_u32(np, "ln8000_charger,ntc-alarm-cfg", &prop); + LN8000_PARSE_PROP(ret, pdata, ntc_alarm_cfg, prop, + LN8000_NTC_ALARM_CFG_DEFAULT); + + /* protection/alarm disable (defaults to enable) */ + pdata->vbat_ovp_disable = + of_property_read_bool(np, "ln8000_charger,vbat-ovp-disable"); + pdata->vbat_reg_disable = + of_property_read_bool(np, "ln8000_charger,vbat-reg-disable"); + pdata->iin_ocp_disable = + of_property_read_bool(np, "ln8000_charger,iin-ocp-disable"); + pdata->iin_reg_disable = + of_property_read_bool(np, "ln8000_charger,iin-reg-disable"); + pdata->tbus_mon_disable = + of_property_read_bool(np, "ln8000_charger,tbus-mon-disable"); + pdata->tbat_mon_disable = + of_property_read_bool(np, "ln8000_charger,tbat-mon-disable"); + pdata->tdie_prot_disable = + of_property_read_bool(np, "ln8000_charger,tdie-prot-disable"); + pdata->tdie_reg_disable = + of_property_read_bool(np, "ln8000_charger,tdie-reg-disable"); + pdata->revcurr_prot_disable = of_property_read_bool( + np, "ln8000_charger,revcurr-prot-disable"); + +#ifdef LN8000_DUAL_CONFIG + /* override device tree */ + if (info->dev_role == LN_PRIMARY) { + ln_info("disable TS_BAT monitor for primary device on dual-mode\n"); + pdata->tbat_mon_disable = true; + } else { + ln_info("disable VBAT_OVP and TS_BAT for secondary device on dual-mode\n"); + pdata->vbat_ovp_disable = true; + pdata->tbat_mon_disable = true; + } +#endif + ln_info("vbat_ovp_disable = %d\n", pdata->vbat_ovp_disable); + ln_info("vbat_reg_disable = %d\n", pdata->vbat_reg_disable); + ln_info("iin_ocp_disable = %d\n", pdata->iin_ocp_disable); + ln_info("iin_reg_disable = %d\n", pdata->iin_reg_disable); + ln_info("tbus_mon_disable = %d\n", pdata->tbus_mon_disable); + ln_info("tbat_mon_disable = %d\n", pdata->tbat_mon_disable); + ln_info("tdie_prot_disable = %d\n", pdata->tdie_prot_disable); + ln_info("tdie_reg_disable = %d\n", pdata->tdie_reg_disable); + ln_info("revcurr_prot_disable = %d\n", pdata->revcurr_prot_disable); + + return 0; +} + +static int ln8000_psy_register(struct ln8000_info *info) +{ + info->psy_cfg.drv_data = info; + info->psy_cfg.of_node = info->client->dev.of_node; + info->psy_desc.name = "bq2597x-standalone"; + info->psy_desc.type = POWER_SUPPLY_TYPE_MAINS; + info->psy_desc.properties = ln8000_charger_props; + info->psy_desc.num_properties = ARRAY_SIZE(ln8000_charger_props); + info->psy_desc.get_property = ln8000_charger_get_property; + info->psy_desc.set_property = ln8000_charger_set_property; + info->psy_desc.property_is_writeable = ln8000_charger_is_writeable; + info->psy_chg = devm_power_supply_register( + &info->client->dev, &info->psy_desc, &info->psy_cfg); + if (IS_ERR(info->psy_chg)) { + ln_err("(%s) failed to register power supply\n", + LN8000_ROLE(info)); + return PTR_ERR(info->psy_chg); + } + + ln_info("(%s) successfully registered power supply\n", + LN8000_ROLE(info)); + + return 0; +} + +static int ln8000_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ln8000_info *info; + int ret = 0; + + /* detect device on connected i2c bus */ + ret = i2c_smbus_read_byte_data(client, LN8000_REG_DEVICE_ID); + if (IS_ERR_VALUE((unsigned long)ret)) { + dev_err(&client->dev, + "fail to detect ln8000 on i2c_bus(addr=0x%x)\n", + client->addr); + return -ENODEV; + } + dev_info(&client->dev, "device id=0x%x\n", ret); + + info = devm_kzalloc(&client->dev, sizeof(struct ln8000_info), + GFP_KERNEL); + if (info == NULL) { + dev_err(&client->dev, + "%s: fail to alloc devm for ln8000_info\n", __func__); + return -ENOMEM; + } + info->dev_role = ln8000_get_dev_role(client); + if (IS_ERR_VALUE((unsigned long)info->dev_role)) { + kfree(info); + return -EINVAL; + } + + info->pdata = devm_kzalloc( + &client->dev, sizeof(struct ln8000_platform_data), GFP_KERNEL); + if (info->pdata == NULL) { + ln_err("fail to alloc devm for ln8000_platform_data\n"); + kfree(info); + return -ENOMEM; + } + info->dev = &client->dev; + info->client = client; + ret = ln8000_parse_dt(info); + if (IS_ERR_VALUE((unsigned long)ret)) { + ln_err("fail to parsed dt\n"); + goto err_devmem; + } + + info->regmap = devm_regmap_init_i2c(client, &ln8000_regmap_config); + if (IS_ERR(info->regmap)) { + ln_err("fail to initialize regmap\n"); + ret = PTR_ERR(info->regmap); + goto err_devmem; + } + + mutex_init(&info->data_lock); + mutex_init(&info->i2c_lock); + mutex_init(&info->irq_lock); + i2c_set_clientdata(client, info); + + ln8000_init_device(info); + + ret = ln8000_psy_register(info); + if (ret) { + goto err_cleanup; + } + + ret = ln8000_irq_init(info); + if (ret < 0) { + goto err_psy; + } + + if (client->irq) { + ret = devm_request_threaded_irq(&client->dev, client->irq, NULL, + ln8000_interrupt_handler, + IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, + "ln8000-charger-irq", info); + if (ret < 0) { + ln_err("request irq for irq=%d failed, ret =%d\n", + client->irq, ret); + goto err_wakeup; + } + enable_irq_wake(client->irq); + INIT_DELAYED_WORK(&info->vac_ov_work, vac_ov_control_work); + } else { + ln_info("don't support isr(irq=%d)\n", info->client->irq); + } + + device_init_wakeup(info->dev, 1); + + ret = ln8000_create_debugfs_entries(info); + if (IS_ERR_VALUE((unsigned long)ret)) { + goto err_wakeup; + } + + determine_initial_status(info); + + return 0; + +err_wakeup: + if (LN8000_IS_PRIMARY(info) && client->irq) { + free_irq(client->irq, info); + if (info->pdata->irq_gpio) { + gpiod_put(info->pdata->irq_gpio); + } + } +err_psy: + power_supply_unregister(info->psy_chg); + +err_cleanup: + i2c_set_clientdata(client, NULL); + mutex_destroy(&info->data_lock); + mutex_destroy(&info->i2c_lock); + mutex_destroy(&info->irq_lock); +err_devmem: + kfree(info->pdata); + kfree(info); + + return ret; +} + +static int ln8000_remove(struct i2c_client *client) +{ + struct ln8000_info *info = i2c_get_clientdata(client); + + ln8000_change_opmode(info, LN8000_OPMODE_STANDBY); + + debugfs_remove_recursive(info->debug_root); + + if (LN8000_IS_PRIMARY(info) && client->irq) { + free_irq(client->irq, info); + if (info->pdata->irq_gpio) { + gpiod_put(info->pdata->irq_gpio); + } + } + + power_supply_unregister(info->psy_chg); + i2c_set_clientdata(info->client, NULL); + + mutex_destroy(&info->data_lock); + mutex_destroy(&info->i2c_lock); + mutex_destroy(&info->irq_lock); + + kfree(info->pdata); + kfree(info); + + return 0; +} + +static void ln8000_shutdown(struct i2c_client *client) +{ + struct ln8000_info *info = i2c_get_clientdata(client); + + ln8000_change_opmode(info, LN8000_OPMODE_STANDBY); +} + +#if defined(CONFIG_PM) +static int ln8000_suspend(struct device *dev) +{ + struct ln8000_info *info = dev_get_drvdata(dev); + + if (device_may_wakeup(dev) && info->client->irq) + enable_irq_wake(info->client->irq); + + ln8000_irq_sleep(info, 1); + + return 0; +} + +static int ln8000_resume(struct device *dev) +{ + struct ln8000_info *info = dev_get_drvdata(dev); + + if (device_may_wakeup(dev) && info->client->irq) + disable_irq_wake(info->client->irq); + + ln8000_irq_sleep(info, 0); + + return 0; +} + +static const struct dev_pm_ops ln8000_pm_ops = { + .suspend = ln8000_suspend, + .resume = ln8000_resume, +}; +#endif + +static struct i2c_driver ln8000_driver = { + .driver = { + .name = "ln8000_charger", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(ln8000_dt_match), +#if defined(CONFIG_PM) + .pm = &ln8000_pm_ops, +#endif + }, + .probe = ln8000_probe, + .remove = ln8000_remove, + .shutdown = ln8000_shutdown, + .id_table = ln8000_id, +}; +module_i2c_driver(ln8000_driver); + +MODULE_AUTHOR("sungdae choi"); +MODULE_DESCRIPTION("LIONSEMI LN8000 charger driver"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("0.3.0"); diff --git a/drivers/power/supply/ti/ln8000_charger.h b/drivers/power/supply/ti/ln8000_charger.h new file mode 100644 index 000000000000..41a7d859bf49 --- /dev/null +++ b/drivers/power/supply/ti/ln8000_charger.h @@ -0,0 +1,344 @@ +/* + * ln8000-charger.h - Charger driver for LIONSEMI LN8000 + * + * Copyright (C) 2021 Lion Semiconductor Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __LN8000_CHARGER_H__ +#define __LN8000_CHARGER_H__ + +//#define LN8000_DUAL_CONFIG /* uncomment to enable DUAL chip operation */ +//#define LN8000_DEBUG_SUPPORT + +/** + * ln8000 device descripion definition + */ +#define ASSIGNED_BITS(_end, _start) ((BIT(_end) - BIT(_start)) + BIT(_end)) + +/* register map description */ +enum ln8000_int1_desc { + LN8000_MASK_FAULT_INT = BIT(7), + LN8000_MASK_NTC_PROT_INT = BIT(6), + LN8000_MASK_CHARGE_PHASE_INT = BIT(5), + LN8000_MASK_MODE_INT = BIT(4), + LN8000_MASK_REV_CURR_INT = BIT(3), + LN8000_MASK_TEMP_INT = BIT(2), + LN8000_MASK_ADC_DONE_INT = BIT(1), + LN8000_MASK_TIMER_INT = BIT(0), +}; + +enum ln8000_sys_sts_desc { + LN8000_MASK_IIN_LOOP_STS = BIT(7), + LN8000_MASK_VFLOAT_LOOP_STS = BIT(6), + LN8000_MASK_BYPASS_ENABLED = BIT(3), + LN8000_MASK_SWITCHING_ENABLED = BIT(2), + LN8000_MASK_STANDBY_STS = BIT(1), + LN8000_MASK_SHUTDOWN_STS = BIT(0), +}; + +enum ln8000_safety_sts_desc { + LN8000_MASK_TEMP_MAX_STS = BIT(6), + LN8000_MASK_TEMP_REGULATION_STS = BIT(5), + LN8000_MASK_NTC_ALARM_STS = BIT(4), + LN8000_MASK_NTC_SHUTDOWN_STS = BIT(3), + LN8000_MASK_REV_IIN_STS = BIT(2), +}; + +enum ln8000_fault1_sts_desc { + LN8000_MASK_WATCHDOG_TIMER_STS = BIT(7), + LN8000_MASK_VBAT_OV_STS = BIT(6), + LN8000_MASK_VAC_UNPLUG_STS = BIT(4), + LN8000_MASK_VAC_OV_STS = BIT(3), + LN8000_MASK_VIN_OV_STS = BIT(1), + LN8000_MASK_VFAULTS = ASSIGNED_BITS(6, 0), +}; + +enum ln8000_fault2_sts_desc { + LN8000_MASK_IIN_OC_DETECTED = BIT(7), +}; + +enum ln8000_ldo_sts_desc { + LN8000_MASK_VBAT_MIN_OK_STS = BIT(7), + LN8000_MASK_CHARGE_TERM_STS = BIT(5), + LN8000_MASK_RECHARGE_STS = BIT(4), +}; + +enum ln8000_regulation_ctrl_desc { + LN8000_BIT_ENABLE_VFLOAT_LOOP_INT = 7, + LN8000_BIT_ENABLE_IIN_LOOP_INT = 6, + LN8000_BIT_DISABLE_VFLOAT_LOOP = 5, + LN8000_BIT_DISABLE_IIN_LOOP = 4, + LN8000_BIT_TEMP_MAX_EN = 2, + LN8000_BIT_TEMP_REG_EN = 1, +}; + +enum ln8000_sys_ctrl_desc { + LN8000_BIT_STANDBY_EN = 3, + LN8000_BIT_REV_IIN_DET = 2, + LN8000_BIT_EN_1TO1 = 0, +}; + +enum ln8000_fault_ctrl_desc { + LN8000_BIT_DISABLE_IIN_OCP = 6, + LN8000_BIT_DISABLE_VBAT_OV = 5, + LN8000_BIT_DISABLE_VAC_OV = 4, + LN8000_BIT_DISABLE_VAC_UV = 3, + LN8000_BIT_DISABLE_VIN_OV = 2, +}; + +enum ln8000_bc_op1_desc { + LN8000_BIT_DUAL_FUNCTION_EN = 2, + LN8000_BIT_DUAL_CFG = 1, + LN8000_BIT_DUAL_LOCKOUT_EN = 0, +}; + +enum ln8000_reg_addr { + LN8000_REG_DEVICE_ID = 0x00, + LN8000_REG_INT1 = 0x01, + LN8000_REG_INT1_MSK = 0x02, + LN8000_REG_SYS_STS = 0x03, + LN8000_REG_SAFETY_STS = 0x04, + LN8000_REG_FAULT1_STS = 0x05, + LN8000_REG_FAULT2_STS = 0x06, + LN8000_REG_CURR1_STS = 0x07, + LN8000_REG_LDO_STS = 0x08, + LN8000_REG_ADC01_STS = 0x09, + LN8000_REG_ADC02_STS = 0x0A, + LN8000_REG_ADC03_STS = 0x0B, + LN8000_REG_ADC04_STS = 0x0C, + LN8000_REG_ADC05_STS = 0x0D, + LN8000_REG_ADC06_STS = 0x0E, + LN8000_REG_ADC07_STS = 0x0F, + LN8000_REG_ADC08_STS = 0x10, + LN8000_REG_ADC09_STS = 0x11, + LN8000_REG_ADC10_STS = 0x12, + LN8000_REG_IIN_CTRL = 0x1B, + LN8000_REG_REGULATION_CTRL = 0x1C, + LN8000_REG_PWR_CTRL = 0x1D, + LN8000_REG_SYS_CTRL = 0x1E, + LN8000_REG_LDO_CTRL = 0x1F, + LN8000_REG_GLITCH_CTRL = 0x20, + LN8000_REG_FAULT_CTRL = 0x21, + LN8000_REG_NTC_CTRL = 0x22, + LN8000_REG_ADC_CTRL = 0x23, + LN8000_REG_ADC_CFG = 0x24, + LN8000_REG_RECOVERY_CTRL = 0x25, + LN8000_REG_TIMER_CTRL = 0x26, + LN8000_REG_THRESHOLD_CTRL = 0x27, + LN8000_REG_V_FLOAT_CTRL = 0x28, + LN8000_REG_CHARGE_CTRL = 0x29, + LN8000_REG_LION_CTRL = 0x30, + LN8000_REG_BC_OP_1 = 0x41, + LN8000_REG_BC_OP_2 = 0x42, + LN8000_REG_BC_STS_A = 0x49, + LN8000_REG_BC_STS_B = 0x4A, + LN8000_REG_BC_STS_C = 0x4B, + LN8000_REG_BC_STS_D = 0x4C, + LN8000_REG_BC_STS_E = 0x4D, + LN8000_REG_MAX, +}; + +/* device feature configuration desc */ +#define LN8000_DEVICE_ID 0x42 + +enum ln8000_role { + LN_PRIMARY = 0x0, + LN_SECONDARY = 0x1, +}; + +enum ln8000_opmode_ { + LN8000_OPMODE_UNKNOWN = 0x0, + LN8000_OPMODE_STANDBY = 0x1, + LN8000_OPMODE_BYPASS = 0x2, + LN8000_OPMODE_SWITCHING = 0x3, +}; + +enum ln8000_vac_ov_cfg_desc { + LN8000_VAC_OVP_6P5V = 0x0, + LN8000_VAC_OVP_11V = 0x1, + LN8000_VAC_OVP_12V = 0x2, + LN8000_VAC_OVP_13V = 0x3, +}; + +enum ln8000_watchdpg_cfg_desc { + LN8000_WATCHDOG_5SEC = 0x0, + LN8000_WATCHDOG_10SEC = 0x1, + LN8000_WATCHDOG_20SEC = 0x2, + LN8000_WATCHDOG_40SEC = 0x3, + LN8000_WATCHDOG_MAX +}; + +enum ln8000_adc_channel_index { + LN8000_ADC_CH_VOUT = 1, + LN8000_ADC_CH_VIN, + LN8000_ADC_CH_VBAT, + LN8000_ADC_CH_VAC, + LN8000_ADC_CH_IIN, + LN8000_ADC_CH_DIETEMP, + LN8000_ADC_CH_TSBAT, + LN8000_ADC_CH_TSBUS, + LN8000_ADC_CH_ALL +}; + +enum ln8000_adc_mode_desc { /* used FORCE_ADC_MODE + ADC_SHUTDOWN_CFG */ + ADC_AUTO_HIB_MODE = 0x0, + ADC_AUTO_SHD_MODE = 0x1, + ADC_SHUTDOWN_MODE = 0x2, + ADC_HIBERNATE_MODE = 0x4, + ADC_NORMAL_MODE = 0x6, +}; + +enum ln8000_adc_hibernate_delay_desc { + ADC_HIBERNATE_500MS = 0x0, + ADC_HIBERNATE_1S = 0x1, + ADC_HIBERNATE_2S = 0x2, + ADC_HIBERNATE_4S = 0x3, +}; + +/* electrical numeric calculation unit description */ +#define LN8000_VBAT_FLOAT_MIN 3725000 /* unit = uV */ +#define LN8000_VBAT_FLOAT_MAX 5000000 +#define LN8000_VBAT_FLOAT_LSB 5000 +#define LN8000_ADC_VOUT_STEP 5000 /* 5mV= 5000uV LSB (0V ~ 5.115V) */ +#define LN8000_ADC_VIN_STEP 16000 /* 16mV=16000uV LSB (0V ~ 16.386V) */ +#define LN8000_ADC_VBAT_STEP 5000 /* 5mV= 5000uV LSB (0V ~ 5.115V) */ +#define LN8000_ADC_VBAT_MIN 1000000 /* 1V */ +#define LN8000_ADC_VAC_STEP 16000 /* 16mV=16000uV LSB (0V ~ 16.386V) */ +#define LN8000_ADC_VAC_OS 5 +#define LN8000_ADC_IIN_STEP 4890 /* 4.89mA=4890uA LSB (0A ~ 5A) */ +#define LN8000_ADC_DIETEMP_STEP \ + 4350 /* 0.435C LSB = 4350dC/1000 (-25C ~ 160C) */ +#define LN8000_ADC_DIETEMP_DENOM 1000 /* 1000 */ +#define LN8000_ADC_DIETEMP_MIN (-250) /* -25C = -250dC */ +#define LN8000_ADC_DIETEMP_MAX 1600 /* 160C = 1600dC */ +#define LN8000_ADC_NTCV_STEP 2933 /* 2.933mV=2933uV LSB (0V ~ 3V) */ +#define LN8000_IIN_CFG_MIN 500000 /* 500mA=500,000uA */ +#define LN8000_IIN_CFG_LSB 50000 /* 50mA=50,000uA */ + +/* device default values */ +#define LN8000_BAT_OVP_DEFAULT 4440000 +#define LN8000_BUS_OVP_DEFAULT 9500000 +#define LN8000_BUS_OCP_DEFAULT 2000000 + +#define LN8000_NTC_ALARM_CFG_DEFAULT 226 /* NTC alarm threshold (~40C) */ +#define LN8000_NTC_SHUTDOWN_CFG 2 /* NTC shutdown config (-16LSB ~ 4.3C) */ +#define LN8000_DEFAULT_FSW_CFG 8 /* 8=440kHz, switching freq */ +#define LN8000_IIN_CFG_DEFAULT 2000000 /* 2A=2,000,000uA, input current limit */ + +/* bus protection values for QC */ +#define BUS_OVP_FOR_QC \ + 13000000 /* ln8000 didn't used 10V, (support tot 6.5V, 11V, 12V, 13V) */ +#define BUS_OVP_ALARM_FOR_QC 9500000 +#define BUS_OCP_FOR_QC_CLASS_A 3250000 +#define BUS_OCP_ALARM_FOR_QC_CLASS_A 2000000 +#define BUS_OCP_FOR_QC_CLASS_B 3750000 +#define BUS_OCP_ALARM_FOR_QC_CLASS_B 2800000 +#define BUS_OCP_FOR_QC3P5_CLASS_A 3000000 +#define BUS_OCP_ALARM_FOR_QC3P5_CLASS_A 2500000 +#define BUS_OCP_FOR_QC3P5_CLASS_B 3500000 +#define BUS_OCP_ALARM_FOR_QC3P5_CLASS_B 3200000 + +/** + * driver instance structure definition + */ +struct ln8000_platform_data { + struct gpio_desc + *irq_gpio; /* GPIO pin for (generic/power-on) interrupt */ + + /* feature configuration */ + unsigned int bat_ovp_th; /* battery ovp threshold (mV) */ + unsigned int bat_ovp_alarm_th; /* battery ovp alarm threshold (mV) */ + unsigned int bus_ovp_th; /* IIN ovp threshold (mV) */ + unsigned int bus_ovp_alarm_th; /* IIN ovp alarm threshold (mV) */ + unsigned int bus_ocp_th; /* IIN ocp threshold (mA) */ + unsigned int bus_ocp_alarm_th; /* IIN ocp alarm threshold */ + unsigned int + ntc_alarm_cfg; /* input/battery NTC voltage threshold code: 0~1023 */ + + /* protection enable/disable */ + bool vbat_ovp_disable; /* disable battery voltage OVP */ + bool vbat_reg_disable; /* disable battery voltage (float) regulation */ + bool iin_ocp_disable; /* disable input current OCP */ + bool iin_reg_disable; /* disable input current regulation */ + bool tbus_mon_disable; /* disable BUS temperature monitor (prot/alarm) */ + bool tbat_mon_disable; /* disable BAT temperature monitor (prot/alarm) */ + bool tdie_prot_disable; /* disable die temperature protection */ + bool tdie_reg_disable; /* disable die temperature regulation */ + bool revcurr_prot_disable; /* disable reverse current protection */ +}; + +struct ln8000_info { + struct device *dev; + struct i2c_client *client; + struct ln8000_platform_data *pdata; + struct power_supply *psy_chg; + + struct mutex data_lock; + struct mutex i2c_lock; + struct mutex irq_lock; + struct regmap *regmap; + struct power_supply_config psy_cfg; + struct power_supply_desc psy_desc; + + unsigned int op_mode; /* target operation mode */ + unsigned int pwr_status; /* current device status */ + unsigned int dev_role; /* device role */ + + /* system/device status */ + bool vbat_regulated; /* vbat loop is active (+ OV alarm) */ + bool iin_regulated; /* iin loop is active (+ OC alarm) */ + bool tdie_fault; /* die temperature fault */ + bool tbus_tbat_fault; /* BUS/BAT temperature fault */ + bool tdie_alarm; /* die temperature alarm (regulated) */ + bool tbus_tbat_alarm; /* BUS/BAT temperature alarm */ + bool wdt_fault; /* watchdog timer expiration */ + bool vbat_ov; /* vbat OV fault */ + bool vac_ov; /* vac OV fault */ + bool vbus_ov; /* vbus OV fault */ + bool iin_oc; /* iin OC fault */ + bool vac_unplug; /* vac unplugged */ + bool iin_rc; /* iin reverse current detected */ + bool volt_qual; /* all voltages are qualified */ + bool usb_present; /* usb plugged (present) */ + bool chg_en; /* charging enavbled */ + bool rcp_en; /* reverse current protection enabled */ + int vbat_ovp_alarm_th; /* vbat ovp alarm threshold */ + int vin_ovp_alarm_th; /* vin ovp alarm threshold */ + int iin_ocp_alarm_th; /* iin ocp alarm threshold */ + + /* ADC readings */ + int tbat_uV; /* BAT temperature (NTC, uV) */ + int tbus_uV; /* BUS temperature (NTC, uV) */ + int tdie_dC; /* die temperature (deci-Celsius) */ + int vbat_uV; /* battery voltage (uV) */ + int vbus_uV; /* input voltage (uV) */ + int iin_uA; /* input current (uV) */ + + /* VAC_OV control for QC3 */ + struct delayed_work vac_ov_work; + bool vac_ov_work_on; + +#ifdef LN8000_ROLE_MASTER + bool ibat_term; /* battery current below termination threshold */ + bool vbat_rechg; /* battery voltage below recharge threshold */ + bool vbat_min; /* battery voltage above min. threshold */ +#endif + + /* debugfs */ + struct dentry *debug_root; + u32 debug_address; +}; + +#endif /* __LN8000_CHARGER_H__ */ diff --git a/drivers/power/supply/ti/pd_policy_manager.c b/drivers/power/supply/ti/pd_policy_manager.c new file mode 100644 index 000000000000..d65e013f8ffd --- /dev/null +++ b/drivers/power/supply/ti/pd_policy_manager.c @@ -0,0 +1,1589 @@ + +#define pr_fmt(fmt) "[USBPD-PM]: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pd_policy_manager.h" + +#ifdef pr_debug +#undef pr_debug +#define pr_debug pr_err +#endif + +#ifdef pr_info +#undef pr_info +#define pr_info pr_err +#endif + +#define PD_SRC_PDO_TYPE_FIXED 0 +#define PD_SRC_PDO_TYPE_BATTERY 1 +#define PD_SRC_PDO_TYPE_VARIABLE 2 +#define PD_SRC_PDO_TYPE_AUGMENTED 3 + +#define BATT_MAX_CHG_VOLT 4450 +#define BATT_FAST_CHG_CURR 6000 +#define BUS_OVP_THRESHOLD 12000 +#define BUS_OVP_ALARM_THRESHOLD 9500 +#define APDO_MAX_VOLT 11000 + +#define BUS_VOLT_INIT_UP 400 + +#define BAT_VOLT_LOOP_LMT BATT_MAX_CHG_VOLT +#define BAT_CURR_LOOP_LMT BATT_FAST_CHG_CURR +#define BUS_VOLT_LOOP_LMT BUS_OVP_THRESHOLD + +#define PM_WORK_RUN_NORMAL_INTERVAL 500 +#define PM_WORK_RUN_QUICK_INTERVAL 200 +#define PM_WORK_RUN_CRITICAL_INTERVAL 100 + +enum { + PM_ALGO_RET_OK, + PM_ALGO_RET_THERM_FAULT, + PM_ALGO_RET_OTHER_FAULT, + PM_ALGO_RET_CHG_DISABLED, + PM_ALGO_RET_TAPER_DONE, + PM_ALGO_RET_SLOWLY_CHARGING, +}; + +static struct pdpm_config pm_config = { + .bat_volt_lp_lmt = BAT_VOLT_LOOP_LMT, + .bat_curr_lp_lmt = BAT_CURR_LOOP_LMT + 1000, + .bus_volt_lp_lmt = BUS_VOLT_LOOP_LMT, + .bus_curr_lp_lmt = BAT_CURR_LOOP_LMT >> 1, + .bus_curr_compensate = 0, + + .fc2_taper_current = 2300, + .fc2_steps = 1, + + .min_adapter_volt_required = 10000, + .min_adapter_curr_required = 2000, + + .min_vbat_for_cp = 3500, + + .cp_sec_enable = false, + .fc2_disable_sw = true, +}; + +static struct usbpd_pm *__pdpm; + +static int fc2_taper_timer; +static int cool_overcharge_timer; +static int ibus_lmt_change_timer; + +static void usbpd_check_usb_psy(struct usbpd_pm *pdpm) +{ + if (!pdpm->usb_psy) { + pdpm->usb_psy = power_supply_get_by_name("usb"); + if (!pdpm->usb_psy) + pr_err("usb psy not found!\n"); + } +} + +static void usbpd_check_batt_psy(struct usbpd_pm *pdpm) +{ + if (!pdpm->sw_psy) { + pdpm->sw_psy = power_supply_get_by_name("battery"); + if (!pdpm->sw_psy) + pr_err("batt psy not found!\n"); + } +} + +static void usbpd_check_bms_psy(struct usbpd_pm *pdpm) +{ + if (!pdpm->bms_psy) { + pdpm->bms_psy = power_supply_get_by_name("bms"); + if (!pdpm->bms_psy) + pr_err("bms psy not found!\n"); + } +} + +/* get thermal level from battery power supply property */ +static int pd_get_batt_current_thermal_level(struct usbpd_pm *pdpm, int *level) +{ + union power_supply_propval pval = { + 0, + }; + int rc = 0; + + usbpd_check_batt_psy(pdpm); + + if (!pdpm->sw_psy) + return -ENODEV; + + rc = power_supply_get_property( + pdpm->sw_psy, POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT, &pval); + if (rc < 0) { + pr_info("Couldn't get fastcharge mode:%d\n", rc); + return rc; + } + + pr_debug("pval.intval: %d\n", pval.intval); + + *level = pval.intval; + return rc; +} + +static int pd_get_batt_capacity(struct usbpd_pm *pdpm, int *capacity) +{ + union power_supply_propval pval = { + 0, + }; + int rc = 0; + + usbpd_check_batt_psy(pdpm); + + if (!pdpm->sw_psy) + return -ENODEV; + + rc = power_supply_get_property(pdpm->sw_psy, POWER_SUPPLY_PROP_CAPACITY, + &pval); + if (rc < 0) { + pr_info("Couldn't get fastcharge mode:%d\n", rc); + return rc; + } + + pr_err("pval.intval: %d\n", pval.intval); + *capacity = pval.intval; + return rc; +} + +/* determine whether to disable cp according to jeita status */ +static bool pd_disable_cp_by_jeita_status(struct usbpd_pm *pdpm) +{ + union power_supply_propval pval = { + 0, + }; + int batt_temp = 0, bq_input_suspend = 0; + int rc; + + usbpd_check_batt_psy(pdpm); + + if (!pdpm->sw_psy) + return -ENODEV; + + rc = power_supply_get_property( + pdpm->sw_psy, POWER_SUPPLY_PROP_BQ_INPUT_SUSPEND, &pval); + + if (!rc) + bq_input_suspend = !!pval.intval; + + if (!pdpm->bms_psy) + return false; + + rc = power_supply_get_property(pdpm->bms_psy, POWER_SUPPLY_PROP_TEMP, + &pval); + if (rc < 0) { + pr_info("Couldn't get batt temp prop:%d\n", rc); + return false; + } + + batt_temp = pval.intval; + pr_debug("batt_temp: %d\n", batt_temp); + if (bq_input_suspend) { + return true; + } else { + if (batt_temp >= JEITA_WARM_THR && !pdpm->jeita_triggered) { + pdpm->jeita_triggered = true; + return true; + } else if (batt_temp <= JEITA_COOL_NOT_ALLOW_CP_THR) { + pdpm->jeita_triggered = true; + return true; + } else if ((batt_temp <= (JEITA_WARM_THR - JEITA_HYSTERESIS)) && + (batt_temp >= + (JEITA_COOL_NOT_ALLOW_CP_THR + JEITA_HYSTERESIS)) && + pdpm->jeita_triggered) { + pdpm->jeita_triggered = false; + return false; + } else { + return pdpm->jeita_triggered; + } + } +} + +static bool is_cool_charge(struct usbpd_pm *pdpm) +{ + union power_supply_propval pval = { + 0, + }; + int batt_temp = 0; + int rc; + + if (!pdpm->bms_psy) + return false; + + rc = power_supply_get_property(pdpm->bms_psy, POWER_SUPPLY_PROP_TEMP, + &pval); + if (rc < 0) { + pr_info("Couldn't get batt temp prop:%d\n", rc); + return false; + } + batt_temp = pval.intval; + + pr_debug("batt_temp: %d\n", batt_temp); + if (batt_temp < 150) + return true; + return false; +} + +/* get bq27z561 fastcharge mode to enable or disabled */ +static bool pd_get_bms_digest_verified(struct usbpd_pm *pdpm) +{ + union power_supply_propval pval = { + 0, + }; + int rc; + + return true; /*for temp debug*/ + + if (!pdpm->bms_psy) + return false; + + rc = power_supply_get_property(pdpm->bms_psy, + POWER_SUPPLY_PROP_AUTHENTIC, &pval); + if (rc < 0) { + pr_info("Couldn't get fastcharge mode:%d\n", rc); + return false; + } + + pr_err("battery verify is: %d\n", pval.intval); + + if (pval.intval == 1) + return true; + else + return false; +} + +/* get pd pps charger verified result */ +#if 0 +static bool pd_get_pps_charger_verified(struct usbpd_pm *pdpm) +{ + union power_supply_propval pval = {0,}; + int rc; + + if (!pdpm->usb_psy) + return false; + + rc = power_supply_get_property(pdpm->usb_psy, + POWER_SUPPLY_PROP_PD_AUTHENTICATION, &pval); + if (rc < 0) { + pr_info("Couldn't get pd_authentication result:%d\n", rc); + return false; + } + + pr_err("pval.intval: %d\n", pval.intval); + + if (pval.intval == 1) + return true; + else + return false; +} +#endif + +/* get bq27z561 fastcharge mode to enable or disabled */ +/* +static int pd_get_bms_charge_current_max(struct usbpd_pm *pdpm, int *fcc_ua) +{ + union power_supply_propval pval = {0,}; + int rc = 0; + + if (!pdpm->bms_psy) + return rc; + + rc = power_supply_get_property(pdpm->bms_psy, + POWER_SUPPLY_PROP_CURRENT_MAX, &pval); + if (rc < 0) { + pr_info("Couldn't get current max:%d\n", rc); + return rc; + } + + *fcc_ua = pval.intval; + return rc; + +} +*/ +/* +static int usbpd_set_new_fcc_voter(struct usbpd_pm *pdpm) +{ + int rc = 0; + int fcc_ua = 0; + + rc = pd_get_bms_charge_current_max(pdpm, &fcc_ua); + + if (rc < 0) + return rc; + + if (!pdpm->fcc_votable) + pdpm->fcc_votable = find_votable("FCC"); + + if (!pdpm->fcc_votable) + return -EINVAL; + + if (pdpm->fcc_votable) + vote(pdpm->fcc_votable, STEP_BMS_CHG_VOTER, true, fcc_ua); + + return rc; +} +*/ + +static void usbpd_check_cp_psy(struct usbpd_pm *pdpm) +{ + if (!pdpm->cp_psy) { + if (pm_config.cp_sec_enable) + pdpm->cp_psy = + power_supply_get_by_name("bq2597x-master"); + else + pdpm->cp_psy = + power_supply_get_by_name("bq2597x-standalone"); + if (!pdpm->cp_psy) { + pdpm->cp_psy = power_supply_get_by_name("ln8000"); + if (!pdpm->cp_psy) + pr_err("cp_psy not found\n"); + } + } +} + +static void usbpd_check_cp_sec_psy(struct usbpd_pm *pdpm) +{ + if (!pdpm->cp_sec_psy) { + pdpm->cp_sec_psy = power_supply_get_by_name("bq2597x-slave"); + if (!pdpm->cp_sec_psy) + pr_err("cp_sec_psy not found\n"); + } +} + +static int usbpd_get_effective_fcc_val(struct usbpd_pm *pdpm) +{ + int effective_fcc_val = 0; + + if (!pdpm->fcc_votable) + pdpm->fcc_votable = find_votable("FCC"); + + if (!pdpm->fcc_votable) + return -EINVAL; + + effective_fcc_val = get_effective_result(pdpm->fcc_votable); + effective_fcc_val = effective_fcc_val / 1000; + pr_info("effective_fcc_val: %d\n", effective_fcc_val); + return effective_fcc_val; +} + +static void usbpd_pm_update_cp_status(struct usbpd_pm *pdpm) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + usbpd_check_cp_psy(pdpm); + + if (!pdpm->cp_psy) + return; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, &val); + if (!ret) + pdpm->cp.vbat_volt = val.intval; + + ret = power_supply_get_property(pdpm->cp_psy, + POWER_SUPPLY_PROP_TI_BUS_VOLTAGE, &val); + if (!ret) + pdpm->cp.vbus_volt = val.intval; + + ret = power_supply_get_property(pdpm->cp_psy, + POWER_SUPPLY_PROP_TI_BUS_CURRENT, &val); + if (!ret) + pdpm->cp.ibus_curr = val.intval; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_BUS_TEMPERATURE, &val); + if (!ret) + pdpm->cp.bus_temp = val.intval; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_BATTERY_TEMPERATURE, &val); + if (!ret) + pdpm->cp.bat_temp = val.intval; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_DIE_TEMPERATURE, &val); + if (!ret) + pdpm->cp.die_temp = val.intval; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_BATTERY_PRESENT, &val); + if (!ret) + pdpm->cp.batt_pres = val.intval; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_VBUS_PRESENT, &val); + if (!ret) + pdpm->cp.vbus_pres = val.intval; + + usbpd_check_bms_psy(pdpm); + if (pdpm->bms_psy) { + ret = power_supply_get_property( + pdpm->bms_psy, POWER_SUPPLY_PROP_CURRENT_NOW, &val); + if (!ret) { + if (pdpm->cp.vbus_pres) + pdpm->cp.ibat_curr = -(val.intval / 1000); + } + ret = power_supply_get_property( + pdpm->bms_psy, POWER_SUPPLY_PROP_FASTCHARGE_MODE, &val); + if (!ret) { + if (val.intval) + pm_config.bat_volt_lp_lmt = + pdpm->ffc_bat_volt_max; + } + } + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, &val); + if (!ret) + pdpm->cp.charge_enabled = val.intval; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_ALARM_STATUS, &val); + if (!ret) { + pdpm->cp.bat_ovp_alarm = !!(val.intval & BAT_OVP_ALARM_MASK); + pdpm->cp.bat_ocp_alarm = !!(val.intval & BAT_OCP_ALARM_MASK); + pdpm->cp.bus_ovp_alarm = !!(val.intval & BUS_OVP_ALARM_MASK); + pdpm->cp.bus_ocp_alarm = !!(val.intval & BUS_OCP_ALARM_MASK); + pdpm->cp.bat_ucp_alarm = !!(val.intval & BAT_UCP_ALARM_MASK); + pdpm->cp.bat_therm_alarm = + !!(val.intval & BAT_THERM_ALARM_MASK); + pdpm->cp.bus_therm_alarm = + !!(val.intval & BUS_THERM_ALARM_MASK); + pdpm->cp.die_therm_alarm = + !!(val.intval & DIE_THERM_ALARM_MASK); + } + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_TI_FAULT_STATUS, &val); + if (!ret) { + pdpm->cp.bat_ovp_fault = !!(val.intval & BAT_OVP_FAULT_MASK); + pdpm->cp.bat_ocp_fault = !!(val.intval & BAT_OCP_FAULT_MASK); + pdpm->cp.bus_ovp_fault = !!(val.intval & BUS_OVP_FAULT_MASK); + pdpm->cp.bus_ocp_fault = !!(val.intval & BUS_OCP_FAULT_MASK); + pdpm->cp.bat_therm_fault = + !!(val.intval & BAT_THERM_FAULT_MASK); + pdpm->cp.bus_therm_fault = + !!(val.intval & BUS_THERM_FAULT_MASK); + pdpm->cp.die_therm_fault = + !!(val.intval & DIE_THERM_FAULT_MASK); + } + + ret = power_supply_get_property(pdpm->cp_psy, + POWER_SUPPLY_PROP_TI_REG_STATUS, &val); + if (!ret) { + pdpm->cp.vbat_reg = !!(val.intval & VBAT_REG_STATUS_MASK); + pdpm->cp.ibat_reg = !!(val.intval & IBAT_REG_STATUS_MASK); + } +} + +static void usbpd_pm_update_cp_sec_status(struct usbpd_pm *pdpm) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + if (!pm_config.cp_sec_enable) + return; + + usbpd_check_cp_sec_psy(pdpm); + + if (!pdpm->cp_sec_psy) + return; + + ret = power_supply_get_property(pdpm->cp_sec_psy, + POWER_SUPPLY_PROP_TI_BUS_CURRENT, &val); + if (!ret) + pdpm->cp_sec.ibus_curr = val.intval; + + ret = power_supply_get_property( + pdpm->cp_sec_psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, &val); + if (!ret) + pdpm->cp_sec.charge_enabled = val.intval; +} + +static int usbpd_pm_enable_cp(struct usbpd_pm *pdpm, bool enable) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + usbpd_check_cp_psy(pdpm); + + if (!pdpm->cp_psy) + return -ENODEV; + + val.intval = enable; + ret = power_supply_set_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, &val); + + return ret; +} + +static int usbpd_pm_enable_cp_sec(struct usbpd_pm *pdpm, bool enable) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + usbpd_check_cp_sec_psy(pdpm); + + if (!pdpm->cp_sec_psy) + return -ENODEV; + + val.intval = enable; + ret = power_supply_set_property( + pdpm->cp_sec_psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, &val); + + return ret; +} + +static int usbpd_pm_check_cp_enabled(struct usbpd_pm *pdpm) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + usbpd_check_cp_psy(pdpm); + + if (!pdpm->cp_psy) + return -ENODEV; + + ret = power_supply_get_property( + pdpm->cp_psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, &val); + if (!ret) + pdpm->cp.charge_enabled = !!val.intval; + + pr_info("pdpm->cp.charge_enabled:%d\n", pdpm->cp.charge_enabled); + + return ret; +} + +static int usbpd_pm_check_cp_sec_enabled(struct usbpd_pm *pdpm) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + usbpd_check_cp_sec_psy(pdpm); + + if (!pdpm->cp_sec_psy) + return -ENODEV; + + ret = power_supply_get_property( + pdpm->cp_sec_psy, POWER_SUPPLY_PROP_CHARGING_ENABLED, &val); + if (!ret) + pdpm->cp_sec.charge_enabled = !!val.intval; + pr_info("pdpm->cp_sec.charge_enabled:%d\n", + pdpm->cp_sec.charge_enabled); + return ret; +} + +static int usbpd_pm_enable_sw(struct usbpd_pm *pdpm, bool enable) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + if (!pdpm->sw_psy) { + pdpm->sw_psy = power_supply_get_by_name("battery"); + if (!pdpm->sw_psy) { + return -ENODEV; + } + } + + val.intval = enable; + ret = power_supply_set_property( + pdpm->sw_psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, &val); + + return ret; +} + +static int usbpd_pm_check_slowly_charging_enabled(struct usbpd_pm *pdpm) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + if (!pdpm->sw_psy) { + pdpm->sw_psy = power_supply_get_by_name("battery"); + if (!pdpm->sw_psy) { + return -ENODEV; + } + } + + ret = power_supply_get_property( + pdpm->sw_psy, POWER_SUPPLY_PROP_SLOWLY_CHARGING, &val); + if (!ret) + pdpm->sw.slowly_charging = !!val.intval; + + return ret; +} + +static int usbpd_pm_limit_sw(struct usbpd_pm *pdpm, bool enable) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + if (!pdpm->sw_psy) { + pdpm->sw_psy = power_supply_get_by_name("battery"); + if (!pdpm->sw_psy) { + return -ENODEV; + } + } + + val.intval = enable; + ret = power_supply_set_property( + pdpm->sw_psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED, &val); + + return ret; +} + +static int usbpd_pm_check_sw_limited(struct usbpd_pm *pdpm) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + if (!pdpm->sw_psy) { + pdpm->sw_psy = power_supply_get_by_name("battery"); + if (!pdpm->sw_psy) { + return -ENODEV; + } + } + + ret = power_supply_get_property( + pdpm->sw_psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED, &val); + if (!ret) + pdpm->sw.charge_limited = !!val.intval; + + return ret; +} + +static int usbpd_pm_check_sw_enabled(struct usbpd_pm *pdpm) +{ + int ret; + union power_supply_propval val = { + 0, + }; + + if (!pdpm->sw_psy) { + pdpm->sw_psy = power_supply_get_by_name("battery"); + if (!pdpm->sw_psy) { + return -ENODEV; + } + } + + ret = power_supply_get_property( + pdpm->sw_psy, POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, &val); + if (!ret) + pdpm->sw.charge_enabled = !!val.intval; + + return ret; +} + +static void usbpd_pm_update_sw_status(struct usbpd_pm *pdpm) +{ + usbpd_pm_check_sw_enabled(pdpm); + usbpd_pm_check_sw_limited(pdpm); +} + +static void usbpd_pm_evaluate_src_caps(struct usbpd_pm *pdpm) +{ + int ret; + int i; + union power_supply_propval pval = { + 0, + }; + + if (!pdpm->pd) { + pdpm->pd = smb_get_usbpd(); + if (!pdpm->pd) { + pr_err("couldn't get usbpd device\n"); + return; + } + } + + ret = usbpd_fetch_pdo(pdpm->pd, pdpm->pdo); + if (ret) { + pr_err("Failed to fetch pdo info\n"); + return; + } + + pdpm->apdo_max_volt = pm_config.min_adapter_volt_required; + pdpm->apdo_max_curr = pm_config.min_adapter_curr_required; + + for (i = 0; i < PDO_MAX_NUM; i++) { + if (pdpm->pdo[i].type == PD_SRC_PDO_TYPE_AUGMENTED && + pdpm->pdo[i].pps && pdpm->pdo[i].pos) { + if (pdpm->pdo[i].max_volt_mv >= pdpm->apdo_max_volt && + pdpm->pdo[i].curr_ma >= pdpm->apdo_max_curr && + pdpm->pdo[i].max_volt_mv <= APDO_MAX_VOLT) { + pdpm->apdo_max_volt = pdpm->pdo[i].max_volt_mv; + pdpm->apdo_max_curr = pdpm->pdo[i].curr_ma; + pdpm->apdo_selected_pdo = pdpm->pdo[i].pos; + pdpm->pps_supported = true; + } + } + } + + if (pdpm->pps_supported) { + pr_info("PPS supported, preferred APDO pos:%d, max volt:%d, current:%d\n", + pdpm->apdo_selected_pdo, pdpm->apdo_max_volt, + pdpm->apdo_max_curr); + if (pdpm->apdo_max_curr <= LOW_POWER_PPS_CURR_THR) + pdpm->apdo_max_curr = XIAOMI_LOW_POWER_PPS_CURR_MAX; + pval.intval = (pdpm->apdo_max_volt / 1000) * + (pdpm->apdo_max_curr / 1000); + power_supply_set_property(pdpm->usb_psy, + POWER_SUPPLY_PROP_APDO_MAX, &pval); + } else { + pr_info("Not qualified PPS adapter\n"); + } +} + +static void usbpd_update_pps_status(struct usbpd_pm *pdpm) +{ + int ret; + u32 status; + + /* we will use it later, to do */ + return; + + ret = usbpd_get_pps_status(pdpm->pd, &status); + + if (!ret) { + pr_info("get_pps_status: status_db :0x%x\n", status); + /*TODO: check byte order to insure data integrity*/ + pdpm->adapter_voltage = (status & 0xFFFF) * 20; + pdpm->adapter_current = ((status >> 16) & 0xFF) * 50; + pdpm->adapter_ptf = ((status >> 24) & 0x06) >> 1; + pdpm->adapter_omf = !!((status >> 24) & 0x08); + pr_info("adapter_volt:%d, adapter_current:%d\n", + pdpm->adapter_voltage, pdpm->adapter_current); + pr_info("pdpm->adapter_ptf:%d, pdpm->adapter_omf:%d\n", + pdpm->adapter_ptf, pdpm->adapter_omf); + } +} + +#define TAPER_TIMEOUT (25000 / PM_WORK_RUN_NORMAL_INTERVAL) +#define IBUS_CHANGE_TIMEOUT (2500 / PM_WORK_RUN_NORMAL_INTERVAL) +static int usbpd_pm_fc2_charge_algo(struct usbpd_pm *pdpm) +{ + int steps; + int sw_ctrl_steps = 0; + int hw_ctrl_steps = 0; + int step_vbat = 0; + int step_ibus = 0; + int step_ibat = 0; + int step_bat_reg = 0; + int ibus_total = 0; + int effective_fcc_val = 0; + int effective_fcc_taper = 0; + int thermal_level = 0; + static int curr_fcc_limit, curr_ibus_limit; + + static int ibus_limit; + + //usbpd_set_new_fcc_voter(pdpm); + + effective_fcc_val = usbpd_get_effective_fcc_val(pdpm); + + if (effective_fcc_val > 0) { + curr_fcc_limit = + min(pm_config.bat_curr_lp_lmt, effective_fcc_val); + curr_ibus_limit = curr_fcc_limit >> 1; + /* + * bq25970 alone compensate 100mA, bq25970 master ans slave compensate 300mA, + * for target curr_ibus_limit for bq adc accurancy is below standard and power suuply system current + */ + curr_ibus_limit += pm_config.bus_curr_compensate; + /* curr_ibus_limit should compare with apdo_max_curr here*/ + curr_ibus_limit = min(curr_ibus_limit, pdpm->apdo_max_curr); + pr_debug("curr_ibus_limit:%d\n", curr_ibus_limit); + } + + ibus_limit = curr_ibus_limit; + /* reduce bus current in cv loop */ + if (pdpm->cp.vbat_volt > pm_config.bat_volt_lp_lmt - BQ_TAPER_HYS_MV) { + if (ibus_lmt_change_timer++ > IBUS_CHANGE_TIMEOUT) { + ibus_lmt_change_timer = 0; + ibus_limit = curr_ibus_limit - 100; + effective_fcc_taper = usbpd_get_effective_fcc_val(pdpm); + effective_fcc_taper -= BQ_TAPER_DECREASE_STEP_MA; + pr_err("bq set taper fcc to: %d mA\n", + effective_fcc_taper); + if (pdpm->fcc_votable) + vote(pdpm->fcc_votable, BQ_TAPER_FCC_VOTER, + true, effective_fcc_taper * 1000); + } + } else if (pdpm->cp.vbat_volt < pm_config.bat_volt_lp_lmt - 250) { + ibus_limit = curr_ibus_limit + 100; + ibus_lmt_change_timer = 0; + } else { + ibus_lmt_change_timer = 0; + } + pr_info("ibus_limit:%d\n", ibus_limit); + + /* battery voltage loop*/ + if (pdpm->cp.vbat_volt > pm_config.bat_volt_lp_lmt) + step_vbat = -pm_config.fc2_steps; + else if (pdpm->cp.vbat_volt < pm_config.bat_volt_lp_lmt - 10) + step_vbat = pm_config.fc2_steps; + ; + + /* battery charge current loop*/ + if (pdpm->cp.ibat_curr < curr_fcc_limit) + step_ibat = pm_config.fc2_steps; + else if (pdpm->cp.ibat_curr > curr_fcc_limit + 50) + step_ibat = -pm_config.fc2_steps; + + /* bus current loop*/ + ibus_total = pdpm->cp.ibus_curr; + + if (pm_config.cp_sec_enable) + ibus_total += pdpm->cp_sec.ibus_curr; + + pr_info("ibus_total_ma: %d\n", ibus_total); + pr_info("vbus_mv: %d\n", pdpm->cp.vbus_volt); + pr_info("vbat_mv: %d\n", pdpm->cp.vbat_volt); + pr_info("ibat_ma: %d\n", pdpm->cp.ibat_curr); + + if (ibus_total < ibus_limit - 50) + step_ibus = pm_config.fc2_steps; + else if (ibus_total > ibus_limit) + step_ibus = -pm_config.fc2_steps; + pr_info("step_ibus:%d\n", step_ibus); + + pr_info("pdpm->cp.vbat_reg:%d, pdpm->cp.ibat_reg:%d\n", + pdpm->cp.vbat_reg, pdpm->cp.ibat_reg); + /* hardware regulation loop*/ + if (pdpm->cp.vbat_reg) /*|| pdpm->cp.ibat_reg*/ + step_bat_reg = 3 * (-pm_config.fc2_steps); + else + step_bat_reg = pm_config.fc2_steps; + + pr_info("step_bat_reg:%d\n", step_bat_reg); + sw_ctrl_steps = min(min(step_vbat, step_ibus), step_ibat); + sw_ctrl_steps = min(sw_ctrl_steps, step_bat_reg); + + pr_info("sw_ctrl_steps:%d\n", sw_ctrl_steps); + /* hardware alarm loop */ + if (pdpm->cp.bus_ocp_alarm || pdpm->cp.bus_ovp_alarm) + hw_ctrl_steps = -pm_config.fc2_steps; + else + hw_ctrl_steps = pm_config.fc2_steps; + pr_info("hw_ctrl_steps:%d\n", hw_ctrl_steps); + /* check if cp disabled due to other reason*/ + usbpd_pm_check_cp_enabled(pdpm); + + if (pm_config.cp_sec_enable) + usbpd_pm_check_cp_sec_enabled(pdpm); + + pd_get_batt_current_thermal_level(pdpm, &thermal_level); + + pdpm->is_temp_out_fc2_range = pd_disable_cp_by_jeita_status(pdpm); + pr_debug("is_temp_out_fc2_range:%d\n", pdpm->is_temp_out_fc2_range); + + /*check if slowly charging feature is enabled*/ + usbpd_pm_check_slowly_charging_enabled(pdpm); + + if (pdpm->cp.bat_therm_fault) { /* battery overheat, stop charge*/ + pr_info("bat_therm_fault:%d\n", pdpm->cp.bat_therm_fault); + return PM_ALGO_RET_THERM_FAULT; + } else if (thermal_level >= MAX_THERMAL_LEVEL || + pdpm->is_temp_out_fc2_range) { + pr_info("is_temp_out_fc2_range:%d,thermal_level:%d\n", + pdpm->is_temp_out_fc2_range, thermal_level); + pr_info("thermal level too high or batt temp is out of fc2 range\n"); + return PM_ALGO_RET_CHG_DISABLED; + } else if (pdpm->cp.bat_ocp_fault || pdpm->cp.bus_ocp_fault || + pdpm->cp.bat_ovp_fault || pdpm->cp.bus_ovp_fault) { + pr_info("bat_ocp_fault:%d, bus_ocp_fault:%d, bat_ovp_fault:%d, bus_ovp_fault:%d\n", + pdpm->cp.bat_ocp_fault, pdpm->cp.bus_ocp_fault, + pdpm->cp.bat_ovp_fault, pdpm->cp.bus_ovp_fault); + return PM_ALGO_RET_OTHER_FAULT; /* go to switch, and try to ramp up*/ + } else if (!pdpm->cp.charge_enabled || + (pm_config.cp_sec_enable && !pdpm->cp_sec.charge_enabled)) { + pr_info("cp.charge_enabled:%d, cp_sec.charge_enabled:%d\n", + pdpm->cp.charge_enabled, pdpm->cp_sec.charge_enabled); + return PM_ALGO_RET_CHG_DISABLED; + } else if (pdpm->sw.slowly_charging) { + pr_info("slowly charging enabled[%d]\n", + pdpm->sw.slowly_charging); + return PM_ALGO_RET_SLOWLY_CHARGING; + } + + /*check overcharge when it is cool*/ + if (pdpm->cp.vbat_volt > pm_config.bat_volt_lp_lmt && + is_cool_charge(pdpm)) { + if (cool_overcharge_timer++ > TAPER_TIMEOUT) { + pr_info("cool overcharge\n"); + cool_overcharge_timer = 0; + return PM_ALGO_RET_TAPER_DONE; + } + } else { + cool_overcharge_timer = 0; + } + /* charge pump taper charge */ + if (pdpm->cp.vbat_volt > pm_config.bat_volt_lp_lmt - TAPER_VOL_HYS && + pdpm->cp.ibat_curr < pm_config.fc2_taper_current) { + if (fc2_taper_timer++ > TAPER_TIMEOUT) { + pr_info("charge pump taper charging done\n"); + fc2_taper_timer = 0; + return PM_ALGO_RET_TAPER_DONE; + } + } else { + fc2_taper_timer = 0; + } + + /*TODO: customer can add hook here to check system level + * thermal mitigation*/ + + steps = min(sw_ctrl_steps, hw_ctrl_steps); + pr_info("steps: %d, sw_ctrl_steps:%d, hw_ctrl_steps:%d\n", steps, + sw_ctrl_steps, hw_ctrl_steps); + pdpm->request_voltage += steps * STEP_MV; + + pdpm->request_current = min(pdpm->apdo_max_curr, curr_ibus_limit); + + pr_info("steps: %d, pdpm->request_voltage: %d\n", steps, + pdpm->request_voltage); + + if (pdpm->apdo_max_volt == PPS_VOL_MAX) + pdpm->apdo_max_volt = pdpm->apdo_max_volt - PPS_VOL_HYS; + + if (pdpm->request_voltage > pdpm->apdo_max_volt) + pdpm->request_voltage = pdpm->apdo_max_volt; + + /*if (pdpm->adapter_voltage > 0 + && pdpm->request_voltage > pdpm->adapter_voltage + 500) + pdpm->request_voltage = pdpm->adapter_voltage + 500; */ + + return PM_ALGO_RET_OK; +} + +static const unsigned char *pm_str[] = { + "PD_PM_STATE_ENTRY", "PD_PM_STATE_FC2_ENTRY", + "PD_PM_STATE_FC2_ENTRY_1", "PD_PM_STATE_FC2_ENTRY_2", + "PD_PM_STATE_FC2_ENTRY_3", "PD_PM_STATE_FC2_TUNE", + "PD_PM_STATE_FC2_EXIT", +}; + +static void usbpd_pm_move_state(struct usbpd_pm *pdpm, enum pm_state state) +{ +#if 1 + pr_info("state change:%s -> %s\n", pm_str[pdpm->state], pm_str[state]); +#endif + pdpm->state = state; +} + +static int usbpd_pm_sm(struct usbpd_pm *pdpm) +{ + int ret; + int rc = 0; + static int tune_vbus_retry; + static bool stop_sw; + static bool recover; + int effective_fcc_val = 0; + int thermal_level = 0, capacity; + static int curr_fcc_lmt, curr_ibus_lmt, retry_count; + + switch (pdpm->state) { + case PD_PM_STATE_ENTRY: + stop_sw = false; + recover = false; + + usbpd_pm_check_slowly_charging_enabled(pdpm); + pd_get_batt_current_thermal_level(pdpm, &thermal_level); + pdpm->is_temp_out_fc2_range = + pd_disable_cp_by_jeita_status(pdpm); + pr_info("is_temp_out_fc2_range:%d\n", + pdpm->is_temp_out_fc2_range); + pd_get_batt_capacity(pdpm, &capacity); + effective_fcc_val = usbpd_get_effective_fcc_val(pdpm); + + if (effective_fcc_val > 0) { + curr_fcc_lmt = min(pm_config.bat_curr_lp_lmt, + effective_fcc_val); + curr_ibus_lmt = curr_fcc_lmt >> 1; + pr_info("curr_ibus_lmt:%d\n", curr_ibus_lmt); + } + + if (pdpm->cp.vbat_volt < pm_config.min_vbat_for_cp) { + pr_info("batt_volt %d, waiting...\n", + pdpm->cp.vbat_volt); + } else if ((pdpm->cp.vbat_volt > + pm_config.bat_volt_lp_lmt - 50) || + (capacity >= 95)) { + pr_info("batt_volt %d is too high for cp,\ + charging with switch charger\n", + pdpm->cp.vbat_volt); + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_EXIT); + if (pm_config.bat_volt_lp_lmt < BAT_VOLT_LOOP_LMT) + recover = true; + } else if (!pd_get_bms_digest_verified(pdpm)) { + pr_info("bms digest is not verified, waiting...\n"); + } else if (thermal_level >= MAX_THERMAL_LEVEL || + pdpm->is_temp_out_fc2_range) { + pr_info("thermal too high or batt temp is out of fc2 range, waiting...\n"); + } else if (pdpm->sw.slowly_charging) { + pr_info("slowly charging feature is on, waiting...\n"); + } else { + pr_info("batt_volt-%d is ok, start flash charging\n", + pdpm->cp.vbat_volt); + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_ENTRY); + } + break; + + case PD_PM_STATE_FC2_ENTRY: + if (pm_config.fc2_disable_sw) { + if (!pdpm->sw.charge_limited) { + usbpd_pm_limit_sw(pdpm, true); + usbpd_pm_update_sw_status(pdpm); + } + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_ENTRY_1); + } else { + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_ENTRY_1); + } + retry_count = 0; + break; + + case PD_PM_STATE_FC2_ENTRY_1: + pdpm->request_voltage = + pdpm->cp.vbat_volt * 2 + BUS_VOLT_INIT_UP; + pdpm->request_current = min(pdpm->apdo_max_curr, curr_ibus_lmt); + + usbpd_select_pdo(pdpm->pd, pdpm->apdo_selected_pdo, + pdpm->request_voltage * 1000, + pdpm->request_current * 1000); + pr_debug("request_voltage:%d, request_current:%d\n", + pdpm->request_voltage, pdpm->request_current); + + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_ENTRY_2); + + tune_vbus_retry = 0; + break; + + case PD_PM_STATE_FC2_ENTRY_2: + pr_info("tune adapter volt %d , vbatt %d\n", pdpm->cp.vbus_volt, + pdpm->cp.vbat_volt); + if (pdpm->cp.vbus_volt < + (pdpm->cp.vbat_volt * 2 + BUS_VOLT_INIT_UP - 50)) { + tune_vbus_retry++; + pdpm->request_voltage += STEP_MV; + usbpd_select_pdo(pdpm->pd, pdpm->apdo_selected_pdo, + pdpm->request_voltage * 1000, + pdpm->request_current * 1000); + } else if (pdpm->cp.vbus_volt > + (pdpm->cp.vbat_volt * 2 + BUS_VOLT_INIT_UP + 200)) { + tune_vbus_retry++; + pdpm->request_voltage -= STEP_MV; + usbpd_select_pdo(pdpm->pd, pdpm->apdo_selected_pdo, + pdpm->request_voltage * 1000, + pdpm->request_current * 1000); + } else { + pr_info("adapter volt tune ok, retry %d times\n", + tune_vbus_retry); + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_ENTRY_3); + break; + } + + if (tune_vbus_retry > 60) { + if (retry_count < 1) { + usbpd_pm_move_state(pdpm, + PD_PM_STATE_FC2_ENTRY_1); + retry_count++; + pr_info("Failed to tune adapter volt into valid range, retry again\n"); + } else { + pr_info("Failed to tune adapter volt into valid range, charge with switching charger\n"); + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_EXIT); + } + } + break; + + case PD_PM_STATE_FC2_ENTRY_3: + + if (pm_config.cp_sec_enable && !pdpm->cp_sec.charge_enabled) { + usbpd_pm_enable_cp_sec(pdpm, true); + msleep(30); + usbpd_pm_check_cp_sec_enabled(pdpm); + } + + if (!pdpm->cp.charge_enabled) { + usbpd_pm_enable_cp(pdpm, true); + msleep(30); + usbpd_pm_check_cp_enabled(pdpm); + } + + if (pdpm->cp.charge_enabled) { + if (pm_config.fc2_disable_sw) { + if (pdpm->sw.charge_enabled) { + usbpd_pm_enable_sw(pdpm, false); + usbpd_pm_update_sw_status(pdpm); + } + } + if ((pm_config.cp_sec_enable && + pdpm->cp_sec.charge_enabled) || + !pm_config.cp_sec_enable) { + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_TUNE); + ibus_lmt_change_timer = 0; + fc2_taper_timer = 0; + } + } + break; + + case PD_PM_STATE_FC2_TUNE: +#if 0 + if (pdpm->cp.vbat_volt < pm_config.min_vbat_for_cp - 400) { + usbpd_pm_move_state(PD_PM_STATE_SW_ENTRY); + break; + } +#endif + usbpd_update_pps_status(pdpm); + + ret = usbpd_pm_fc2_charge_algo(pdpm); + if (ret == PM_ALGO_RET_THERM_FAULT) { + pr_info("Move to stop charging:%d\n", ret); + stop_sw = true; + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_EXIT); + break; + } else if (ret == PM_ALGO_RET_OTHER_FAULT || + ret == PM_ALGO_RET_TAPER_DONE) { + pr_info("Move to switch charging:%d\n", ret); + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_EXIT); + break; + } else if (ret == PM_ALGO_RET_CHG_DISABLED) { + pr_info("Move to switch charging, will try to recover flash charging:%d\n", + ret); + recover = true; + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_EXIT); + break; + } else if (ret == PM_ALGO_RET_SLOWLY_CHARGING) { + recover = true; + pr_info("Slow Charging Feature is running %d\n", ret); + usbpd_pm_move_state(pdpm, PD_PM_STATE_FC2_EXIT); + } else { + usbpd_select_pdo(pdpm->pd, pdpm->apdo_selected_pdo, + pdpm->request_voltage * 1000, + pdpm->request_current * 1000); + pr_info("request_voltage:%d, request_current:%d\n", + pdpm->request_voltage, pdpm->request_current); + } + /*stop second charge pump if either of ibus is lower than 400ma during CV*/ + if (pm_config.cp_sec_enable && pdpm->cp_sec.charge_enabled && + pdpm->cp.vbat_volt > + pm_config.bat_volt_lp_lmt - TAPER_WITH_IBUS_HYS && + (pdpm->cp.ibus_curr < TAPER_IBUS_THR || + pdpm->cp_sec.ibus_curr < TAPER_IBUS_THR)) { + pr_info("second cp is disabled due to ibus < 450mA\n"); + usbpd_pm_enable_cp_sec(pdpm, false); + usbpd_pm_check_cp_sec_enabled(pdpm); + } + break; + + case PD_PM_STATE_FC2_EXIT: + /* select default 5V*/ + usbpd_select_pdo(pdpm->pd, 1, 0, 0); + if (pdpm->fcc_votable) + vote(pdpm->fcc_votable, BQ_TAPER_FCC_VOTER, false, 0); + + if (!stop_sw && + (!pdpm->sw.charge_enabled || pdpm->sw.charge_limited)) { + usbpd_pm_enable_sw(pdpm, true); + } + if (stop_sw && + (pdpm->sw.charge_enabled || pdpm->sw.charge_limited)) + usbpd_pm_enable_sw(pdpm, false); + usbpd_pm_update_sw_status(pdpm); + + if (pdpm->cp.charge_enabled) { + usbpd_pm_enable_cp(pdpm, false); + usbpd_pm_check_cp_enabled(pdpm); + } + + if (pm_config.cp_sec_enable && pdpm->cp_sec.charge_enabled) { + usbpd_pm_enable_cp_sec(pdpm, false); + usbpd_pm_check_cp_sec_enabled(pdpm); + } + + if (recover) + usbpd_pm_move_state(pdpm, PD_PM_STATE_ENTRY); + else + rc = 1; + + break; + default: + usbpd_pm_move_state(pdpm, PD_PM_STATE_ENTRY); + break; + } + + return rc; +} + +static void usbpd_pm_workfunc(struct work_struct *work) +{ + struct usbpd_pm *pdpm = + container_of(work, struct usbpd_pm, pm_work.work); + int internal = PM_WORK_RUN_NORMAL_INTERVAL; + + usbpd_pm_update_sw_status(pdpm); + usbpd_pm_update_cp_status(pdpm); + usbpd_pm_update_cp_sec_status(pdpm); + + pr_info("%s:pd_bat_volt_lp_lmt=%d, vbatt_now=%d\n", __func__, + pm_config.bat_volt_lp_lmt, pdpm->cp.vbat_volt); + + if (!usbpd_pm_sm(pdpm) && pdpm->pd_active) { + if (pdpm->state == PD_PM_STATE_FC2_ENTRY_2) + internal = PM_WORK_RUN_QUICK_INTERVAL; + else + internal = PM_WORK_RUN_NORMAL_INTERVAL; + + schedule_delayed_work(&pdpm->pm_work, + msecs_to_jiffies(internal)); + } +} + +static void usbpd_pm_disconnect(struct usbpd_pm *pdpm) +{ + union power_supply_propval pval = { + 0, + }; + + cancel_delayed_work_sync(&pdpm->pm_work); + + if (pdpm->fcc_votable) + vote(pdpm->fcc_votable, BQ_TAPER_FCC_VOTER, false, 0); + pdpm->pps_supported = false; + pdpm->jeita_triggered = false; + pdpm->is_temp_out_fc2_range = false; + pdpm->apdo_selected_pdo = 0; + memset(&pdpm->pdo, 0, sizeof(pdpm->pdo)); + pm_config.bat_curr_lp_lmt = pdpm->bat_curr_max; + if (!pdpm->sw.charge_enabled || pdpm->sw.charge_limited) { + usbpd_pm_enable_sw(pdpm, true); + usbpd_pm_check_sw_enabled(pdpm); + } + + pval.intval = 0; + power_supply_set_property(pdpm->usb_psy, POWER_SUPPLY_PROP_APDO_MAX, + &pval); + + usbpd_pm_enable_cp(pdpm, false); + + usbpd_pm_move_state(pdpm, PD_PM_STATE_ENTRY); +} + +static void usbpd_pd_contact(struct usbpd_pm *pdpm, bool connected) +{ + pdpm->pd_active = connected; + + pr_info("pd_active = %d\n", connected); + + if (connected) { + usbpd_pm_evaluate_src_caps(pdpm); + if (pdpm->pps_supported) + schedule_delayed_work(&pdpm->pm_work, 0); + } else { + usbpd_pm_disconnect(pdpm); + } +} + +static void usbpd_pps_non_verified_contact(struct usbpd_pm *pdpm, + bool connected) +{ + pdpm->pd_active = connected; + + pr_info("pd_active = %d\n", connected); + + if (connected) { + usbpd_pm_evaluate_src_caps(pdpm); + if (pdpm->pps_supported) + schedule_delayed_work(&pdpm->pm_work, 5 * HZ); + } else { + usbpd_pm_disconnect(pdpm); + } +} + +static void cp_psy_change_work(struct work_struct *work) +{ + struct usbpd_pm *pdpm = + container_of(work, struct usbpd_pm, cp_psy_change_work); +#if 0 + union power_supply_propval val = {0,}; + bool ac_pres = pdpm->cp.vbus_pres; + int ret; + + if (!pdpm->cp_psy) + return; + + ret = power_supply_get_property(pdpm->cp_psy, POWER_SUPPLY_PROP_TI_VBUS_PRESENT, &val); + if (!ret) + pdpm->cp.vbus_pres = val.intval; + + if (!ac_pres && pdpm->cp.vbus_pres) + schedule_delayed_work(&pdpm->pm_work, 0); +#endif + pdpm->psy_change_running = false; +} + +static void usb_psy_change_work(struct work_struct *work) +{ + struct usbpd_pm *pdpm = + container_of(work, struct usbpd_pm, usb_psy_change_work); + union power_supply_propval val = { + 0, + }; + union power_supply_propval pd_auth_val = { + 0, + }; + int ret = 0; + + ret = power_supply_get_property( + pdpm->usb_psy, POWER_SUPPLY_PROP_TYPEC_POWER_ROLE, &val); + if (ret) { + pr_err("Failed to read typec power role\n"); + goto out; + } + + if (val.intval != POWER_SUPPLY_TYPEC_PR_SINK && + val.intval != POWER_SUPPLY_TYPEC_PR_DUAL) + goto out; + + ret = power_supply_get_property(pdpm->usb_psy, + POWER_SUPPLY_PROP_PD_ACTIVE, &val); + if (ret) { + pr_err("Failed to get usb pd active state\n"); + goto out; + } + + ret = power_supply_get_property(pdpm->usb_psy, + POWER_SUPPLY_PROP_PD_AUTHENTICATION, + &pd_auth_val); + if (ret) { + pr_err("Failed to read typec power role\n"); + goto out; + } + + if (!pdpm->pd_active && (pd_auth_val.intval == 1) && + (val.intval == POWER_SUPPLY_PD_PPS_ACTIVE)) + usbpd_pd_contact(pdpm, true); + else if (!pdpm->pd_active && (val.intval == POWER_SUPPLY_PD_PPS_ACTIVE)) + usbpd_pps_non_verified_contact(pdpm, true); + else if (pdpm->pd_active && !val.intval) + usbpd_pd_contact(pdpm, false); +out: + pdpm->psy_change_running = false; +} + +static int usbpd_psy_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + struct usbpd_pm *pdpm = container_of(nb, struct usbpd_pm, nb); + struct power_supply *psy = data; + unsigned long flags; + + if (event != PSY_EVENT_PROP_CHANGED) + return NOTIFY_OK; + + usbpd_check_cp_psy(pdpm); + usbpd_check_usb_psy(pdpm); + + if (!pdpm->cp_psy || !pdpm->usb_psy) + return NOTIFY_OK; + + if (psy == pdpm->cp_psy || psy == pdpm->usb_psy) { + spin_lock_irqsave(&pdpm->psy_change_lock, flags); + if (!pdpm->psy_change_running) { + pdpm->psy_change_running = true; + if (psy == pdpm->cp_psy) + schedule_work(&pdpm->cp_psy_change_work); + else + schedule_work(&pdpm->usb_psy_change_work); + } + spin_unlock_irqrestore(&pdpm->psy_change_lock, flags); + } + + return NOTIFY_OK; +} + +static int pd_policy_parse_dt(struct usbpd_pm *pdpm) +{ + struct device_node *node = pdpm->dev->of_node; + int rc = 0; + + if (!node) { + pr_err("device tree node missing\n"); + return -EINVAL; + } + + rc = of_property_read_u32(node, "mi,pd-bat-volt-max", + &pdpm->bat_volt_max); + if (rc < 0) + pr_err("pd-bat-volt-max property missing, use default val\n"); + else + pm_config.bat_volt_lp_lmt = pdpm->bat_volt_max; + pr_info("pm_config.bat_volt_lp_lmt:%d\n", pm_config.bat_volt_lp_lmt); + + rc = of_property_read_u32(node, "mi,pd-bat-curr-max", + &pdpm->bat_curr_max); + if (rc < 0) + pr_err("pd-bat-curr-max property missing, use default val\n"); + else + pm_config.bat_curr_lp_lmt = pdpm->bat_curr_max; + pr_info("pm_config.bat_curr_lp_lmt:%d\n", pm_config.bat_curr_lp_lmt); + + rc = of_property_read_u32(node, "mi,pd-bus-volt-max", + &pdpm->bus_volt_max); + if (rc < 0) + pr_err("pd-bus-volt-max property missing, use default val\n"); + else + pm_config.bus_volt_lp_lmt = pdpm->bus_volt_max; + pr_info("pm_config.bus_volt_lp_lmt:%d\n", pm_config.bus_volt_lp_lmt); + + rc = of_property_read_u32(node, "mi,pd-bus-curr-max", + &pdpm->bus_curr_max); + if (rc < 0) + pr_err("pd-bus-curr-max property missing, use default val\n"); + else + pm_config.bus_curr_lp_lmt = pdpm->bus_curr_max; + pr_info("pm_config.bus_curr_lp_lmt:%d\n", pm_config.bus_curr_lp_lmt); + + rc = of_property_read_u32(node, "mi,pd-bus-curr-compensate", + &pdpm->bus_curr_compensate); + if (rc < 0) + pr_err("pd-bus-curr-compensate property missing, use default val\n"); + else + pm_config.bus_curr_compensate = pdpm->bus_curr_compensate; + pr_info("pm_config.bus_curr_compensate:%d\n", + pm_config.bus_curr_compensate); + + pdpm->cp_sec_enable = of_property_read_bool(node, "mi,cp-sec-enable"); + pm_config.cp_sec_enable = pdpm->cp_sec_enable; + + rc = of_property_read_u32(node, "mi,pd-ffc-bat-volt-max", + &pdpm->ffc_bat_volt_max); + pr_info("pdpm->ffc_bat_volt_max:%d\n", pdpm->ffc_bat_volt_max); + + return rc; +} + +static int usbpd_pm_probe(struct platform_device *pdev) +{ + int ret = 0; + struct device *dev = &pdev->dev; + struct usbpd_pm *pdpm; + + pr_info("%s enter\n", __func__); + + pdpm = kzalloc(sizeof(struct usbpd_pm), GFP_KERNEL); + if (!pdpm) + return -ENOMEM; + + __pdpm = pdpm; + + pdpm->dev = dev; + + ret = pd_policy_parse_dt(pdpm); + if (ret < 0) { + pr_err("Couldn't parse device tree rc=%d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, pdpm); + + spin_lock_init(&pdpm->psy_change_lock); + + usbpd_check_cp_psy(pdpm); + usbpd_check_cp_sec_psy(pdpm); + usbpd_check_usb_psy(pdpm); + + INIT_WORK(&pdpm->cp_psy_change_work, cp_psy_change_work); + INIT_WORK(&pdpm->usb_psy_change_work, usb_psy_change_work); + INIT_DELAYED_WORK(&pdpm->pm_work, usbpd_pm_workfunc); + + pdpm->nb.notifier_call = usbpd_psy_notifier_cb; + power_supply_reg_notifier(&pdpm->nb); + + return ret; +} + +static int usbpd_pm_remove(struct platform_device *pdev) +{ + power_supply_unreg_notifier(&__pdpm->nb); + cancel_delayed_work(&__pdpm->pm_work); + cancel_work(&__pdpm->cp_psy_change_work); + cancel_work(&__pdpm->usb_psy_change_work); + + return 0; +} + +static const struct of_device_id usbpd_pm_of_match[] = { + { + .compatible = "xiaomi,usbpd-pm", + }, + {}, +}; + +static struct platform_driver usbpd_pm_driver = { + .driver = { + .name = "usbpd-pm", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(usbpd_pm_of_match), + }, + .probe = usbpd_pm_probe, + .remove = usbpd_pm_remove, +}; + +static int __init usbpd_pm_init(void) +{ + return platform_driver_register(&usbpd_pm_driver); +} + +late_initcall(usbpd_pm_init); + +static void __exit usbpd_pm_exit(void) +{ + return platform_driver_unregister(&usbpd_pm_driver); +} +module_exit(usbpd_pm_exit); + +MODULE_AUTHOR("Fei Jiang"); +MODULE_DESCRIPTION("Xiaomi usb pd statemachine for bq"); +MODULE_LICENSE("GPL"); diff --git a/drivers/power/supply/ti/pd_policy_manager.h b/drivers/power/supply/ti/pd_policy_manager.h new file mode 100644 index 000000000000..465e0b66db14 --- /dev/null +++ b/drivers/power/supply/ti/pd_policy_manager.h @@ -0,0 +1,237 @@ +/* + * usb_pd_policy_manager.h + * + * Created on: Mar 27, 2017 + * Author: a0220433 + */ + +#ifndef SRC_PDLIB_USB_PD_POLICY_MANAGER_H_ +#define SRC_PDLIB_USB_PD_POLICY_MANAGER_H_ +#include +#include +#include +#include +#include +#include +#include + +enum pm_state { + PD_PM_STATE_ENTRY, + PD_PM_STATE_FC2_ENTRY, + PD_PM_STATE_FC2_ENTRY_1, + PD_PM_STATE_FC2_ENTRY_2, + PD_PM_STATE_FC2_ENTRY_3, + PD_PM_STATE_FC2_TUNE, + PD_PM_STATE_FC2_EXIT, +}; + +#define BAT_OVP_FAULT_SHIFT 0 +#define BAT_OCP_FAULT_SHIFT 1 +#define BUS_OVP_FAULT_SHIFT 2 +#define BUS_OCP_FAULT_SHIFT 3 +#define BAT_THERM_FAULT_SHIFT 4 +#define BUS_THERM_FAULT_SHIFT 5 +#define DIE_THERM_FAULT_SHIFT 6 + +#define BAT_OVP_FAULT_MASK (1 << BAT_OVP_FAULT_SHIFT) +#define BAT_OCP_FAULT_MASK (1 << BAT_OCP_FAULT_SHIFT) +#define BUS_OVP_FAULT_MASK (1 << BUS_OVP_FAULT_SHIFT) +#define BUS_OCP_FAULT_MASK (1 << BUS_OCP_FAULT_SHIFT) +#define BAT_THERM_FAULT_MASK (1 << BAT_THERM_FAULT_SHIFT) +#define BUS_THERM_FAULT_MASK (1 << BUS_THERM_FAULT_SHIFT) +#define DIE_THERM_FAULT_MASK (1 << DIE_THERM_FAULT_SHIFT) + +#define BAT_OVP_ALARM_SHIFT 0 +#define BAT_OCP_ALARM_SHIFT 1 +#define BUS_OVP_ALARM_SHIFT 2 +#define BUS_OCP_ALARM_SHIFT 3 +#define BAT_THERM_ALARM_SHIFT 4 +#define BUS_THERM_ALARM_SHIFT 5 +#define DIE_THERM_ALARM_SHIFT 6 +#define BAT_UCP_ALARM_SHIFT 7 + +#define BAT_OVP_ALARM_MASK (1 << BAT_OVP_ALARM_SHIFT) +#define BAT_OCP_ALARM_MASK (1 << BAT_OCP_ALARM_SHIFT) +#define BUS_OVP_ALARM_MASK (1 << BUS_OVP_ALARM_SHIFT) +#define BUS_OCP_ALARM_MASK (1 << BUS_OCP_ALARM_SHIFT) +#define BAT_THERM_ALARM_MASK (1 << BAT_THERM_ALARM_SHIFT) +#define BUS_THERM_ALARM_MASK (1 << BUS_THERM_ALARM_SHIFT) +#define DIE_THERM_ALARM_MASK (1 << DIE_THERM_ALARM_SHIFT) +#define BAT_UCP_ALARM_MASK (1 << BAT_UCP_ALARM_SHIFT) + +#define VBAT_REG_STATUS_SHIFT 0 +#define IBAT_REG_STATUS_SHIFT 1 + +#define VBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT) +#define IBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT) + +/* voters for usbpd */ +#define STEP_BMS_CHG_VOTER "STEP_BMS_CHG_VOTER" +#define BQ_TAPER_FCC_VOTER "BQ_TAPER_FCC_VOTER" + +/* defined for non_verified pps charger maxium fcc */ +#define NON_VERIFIED_PPS_FCC_MAX 3000 +#define MAX_THERMAL_LEVEL 13 +/* jeita related */ +#define JEITA_WARM_THR 450 +#define JEITA_COOL_NOT_ALLOW_CP_THR 100 +#define PDO_MAX_NUM 7 +/* + * add hysteresis for warm threshold to avoid flash + * charge and normal charge switch frequently at + * the warm threshold + */ +#define JEITA_HYSTERESIS 20 +/* product related */ +#define LOW_POWER_PPS_CURR_THR 2000 +#define XIAOMI_LOW_POWER_PPS_CURR_MAX 1500 +#define XIAOMI_LOW_POWER_PPS_CURR_MAX 1500 +#define PPS_VOL_MAX 11000 +#define PPS_VOL_HYS 1000 + +#define STEP_MV 20 +#define TAPER_VOL_HYS 80 +#define TAPER_WITH_IBUS_HYS 60 +#define TAPER_IBUS_THR 450 +#define BQ_TAPER_HYS_MV 10 +#define BQ_TAPER_DECREASE_STEP_MA 200 +struct sw_device { + bool charge_enabled; + bool charge_limited; + bool slowly_charging; +}; + +struct usbpd_pdo { + bool pps; + int type; + int max_volt_mv; + int min_volt_mv; + int curr_ma; + int pos; +}; + +struct cp_device { + bool charge_enabled; + + bool batt_pres; + bool vbus_pres; + + /* alarm/fault status */ + bool bat_ovp_fault; + bool bat_ocp_fault; + bool bus_ovp_fault; + bool bus_ocp_fault; + + bool bat_ovp_alarm; + bool bat_ocp_alarm; + bool bus_ovp_alarm; + bool bus_ocp_alarm; + + bool bat_ucp_alarm; + + bool bat_therm_alarm; + bool bus_therm_alarm; + bool die_therm_alarm; + + bool bat_therm_fault; + bool bus_therm_fault; + bool die_therm_fault; + + bool therm_shutdown_flag; + bool therm_shutdown_stat; + + bool vbat_reg; + bool ibat_reg; + + int vout_volt; + int vbat_volt; + int vbus_volt; + int ibat_curr; + int ibus_curr; + + int bat_temp; + int bus_temp; + int die_temp; +}; + +#define PM_STATE_LOG_MAX 32 +struct usbpd_pm { + struct device *dev; + + enum pm_state state; + + struct cp_device cp; + struct cp_device cp_sec; + + struct sw_device sw; + + bool pd_active; + bool pps_supported; + + int request_voltage; + int request_current; + + struct usbpd *pd; + struct usbpd_pdo pdo[7]; + + int apdo_max_volt; + int apdo_max_curr; + int apdo_selected_pdo; + + int adapter_voltage; + int adapter_current; + int adapter_ptf; + bool adapter_omf; + struct delayed_work pm_work; + + struct notifier_block nb; + + bool psy_change_running; + struct work_struct cp_psy_change_work; + struct work_struct usb_psy_change_work; + spinlock_t psy_change_lock; + + struct votable *fcc_votable; + struct power_supply *cp_psy; + struct power_supply *cp_sec_psy; + struct power_supply *sw_psy; + struct power_supply *usb_psy; + struct power_supply *bms_psy; + + /* dtsi properties */ + int bat_volt_max; + int ffc_bat_volt_max; + int bat_curr_max; + int bus_volt_max; + int bus_curr_max; + int bus_curr_compensate; + bool cp_sec_enable; + /* jeita or thermal related */ + bool jeita_triggered; + bool is_temp_out_fc2_range; +}; + +struct pdpm_config { + int bat_volt_lp_lmt; /*bat volt loop limit*/ + int bat_curr_lp_lmt; + int bus_volt_lp_lmt; + int bus_curr_lp_lmt; + int bus_curr_compensate; + + int fc2_taper_current; + int fc2_steps; + + int min_adapter_volt_required; + int min_adapter_curr_required; + int min_vbat_for_cp; + + bool cp_sec_enable; + bool fc2_disable_sw; /* disable switching charger during flash charge*/ +}; + +extern int usbpd_get_pps_status(struct usbpd *pd, u32 *status); +extern int usbpd_fetch_pdo(struct usbpd *pd, struct usbpd_pdo *pdos); +extern int usbpd_select_pdo(struct usbpd *pd, int pdo, int uv, int ua); +extern struct usbpd *smb_get_usbpd(void); + +#endif /* SRC_PDLIB_USB_PD_POLICY_MANAGER_H_ */ diff --git a/include/linux/power/ln8282.h b/include/linux/power/ln8282.h new file mode 100644 index 000000000000..39dd30b8d1f0 --- /dev/null +++ b/include/linux/power/ln8282.h @@ -0,0 +1,40 @@ +/* + * LIONSEMI LN8282 voltage regulator driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _LN8282_REGULATOR_H_ +#define _LN8282_REGULATOR_H_ + +enum { + LN8282_OPMODE_UNKNOWN = -1, + LN8282_OPMODE_STANDBY = 0, + LN8282_OPMODE_BYPASS = 1, + LN8282_OPMODE_SWITCHING = 2, + LN8282_OPMODE_SWITCHING_ALT = 3, +}; + +struct ln8282_info; + +void ln8282_use_ext_5V(struct ln8282_info *info, unsigned int enable); +void ln8282_set_infet(struct ln8282_info *info, unsigned int enable); +void ln8282_set_powerpath(struct ln8282_info *info, bool forward_path); +bool ln8282_change_opmode(struct ln8282_info *info, unsigned int target_mode); +int ln8282_hw_init(struct ln8282_info *info); +/*add for other module run*/ +/* +void ln8282_set_powerpath_ext(bool forward_path); +bool ln8282_change_opmode_ext(unsigned int target_mode); +unsigned int ln8282_get_opmode_ext(void); +*/ + +#endif From 982e22f12d3df2a529d55ce25bcda0882a2b1137 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Thu, 8 Jul 2021 15:19:41 +0200 Subject: [PATCH 084/226] drivers: power: supply: maxim: Extract S_secret from vayu stock kernel `cat /sys/devices/platform/soc/soc:maxim_ds28e16/ds_S_secret` Change-Id: I1d33a55e38b197aec5a36b2253eaece33996afbb Signed-off-by: firebird11 --- drivers/power/supply/maxim/ds28e16.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/power/supply/maxim/ds28e16.c b/drivers/power/supply/maxim/ds28e16.c index 2947b5b361c8..c3df48f55b4d 100644 --- a/drivers/power/supply/maxim/ds28e16.c +++ b/drivers/power/supply/maxim/ds28e16.c @@ -55,10 +55,10 @@ unsigned char session_seed[32] = { 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA }; -unsigned char S_secret[32] = { 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, - 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, - 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, - 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA }; +unsigned char S_secret[32] = { 0x0C, 0x99, 0x2B, 0xD3, 0x95, 0xDB, 0xA0, 0xB4, + 0xEF, 0x07, 0xB3, 0xD8, 0x75, 0xF3, 0xC7, 0xAE, + 0xDA, 0xC4, 0x41, 0x2F, 0x48, 0x93, 0xB5, 0xD9, + 0xE1, 0xE5, 0x4B, 0x20, 0x9B, 0xF3, 0x77, 0x39 }; unsigned char challenge[32] = { 0x00 }; int auth_ANON = 1; int auth_BDCONST = 1; @@ -633,9 +633,9 @@ int DS28E16_cmd_device_disable(int op, unsigned char *password) /// 'Compute and Read Page Authentication' command /// /// @param[in] anon - boolean parameter -/// @param[in] pg - Page number 2,计数å™? 0,page0; 1,page1; +/// @param[in] pg - Page number 2,计数�? 0,page0; 1,page1; /// @param[in] challenge -/// @param[out] hmac 返回的计算结æž?2个字èŠ?/// +/// @param[out] hmac 返回的计算结�?2个字�?/// /// @return /// DS_TRUE - command successful @n /// DS_FALSE - command failed From 115340ebd4d89eec627e9a06d4757ec3cb2b2895 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 12 Jul 2022 23:51:13 +0200 Subject: [PATCH 085/226] drivers: power: supply: qcom: rx1619: Extract firmware from crux stock kernel Change-Id: Ib3aa8c7a853d04180c1f101d09f6ab30031155fe Signed-off-by: firebird11 --- drivers/power/supply/nuvolta/rx1619.h | 4888 ++++++++++++------------- 1 file changed, 2444 insertions(+), 2444 deletions(-) diff --git a/drivers/power/supply/nuvolta/rx1619.h b/drivers/power/supply/nuvolta/rx1619.h index 8791019582fe..c076f24135ee 100644 --- a/drivers/power/supply/nuvolta/rx1619.h +++ b/drivers/power/supply/nuvolta/rx1619.h @@ -1,6 +1,6 @@ u8 chip_default_data[2] = { 0x47, 0x10 }; -//J2 fw version 0x15 +// Extracted from stock kernel - crux V13.0.1.0.RFXCNXM u8 fw_data_boot[1016] = { 0xff, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, 0xc7, 0xfe, 0xff, 0xff, @@ -86,725 +86,478 @@ u8 fw_data_boot[1016] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xb1, 0xaa, 0xe9, 0xe6, 0xdf, 0xb5, 0xcd, 0xea + 0xb1, 0xaa, 0xe9, 0xe6, 0xbd, 0xb0, 0xab, 0xb0 }; u8 fw_data_tx[13304] = { - 0xff, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, - 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, - 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x93, 0xb2, 0xff, 0xff, - 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, - 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, 0x9b, 0xb2, 0xff, 0xff, - 0x9b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, - 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, - 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, - 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, - 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, - 0x8b, 0xb2, 0xff, 0xff, 0x8b, 0xb2, 0xff, 0xff, 0x63, 0x8b, 0xff, 0xff, - 0xff, 0x8a, 0xff, 0xff, 0x4f, 0x8b, 0xff, 0xff, 0x2b, 0x8b, 0xff, 0xff, - 0x23, 0x8b, 0xff, 0xff, 0xeb, 0x8a, 0xff, 0xff, 0xe3, 0x8a, 0xff, 0xff, - 0x1b, 0x8b, 0xff, 0xff, 0x13, 0x8b, 0xff, 0xff, 0xcb, 0x8a, 0xff, 0xff, - 0x9f, 0x8a, 0xff, 0xff, 0x97, 0x8a, 0xff, 0xff, 0x8f, 0x8a, 0xff, 0xff, - 0x3b, 0x8b, 0xff, 0xff, 0x33, 0x8b, 0xff, 0xff, 0x87, 0x8a, 0xff, 0xff, - 0x7f, 0x8a, 0xff, 0xff, 0x77, 0x8a, 0xff, 0xff, 0x5b, 0x8a, 0xff, 0xff, - 0x53, 0x8a, 0xff, 0xff, 0x4b, 0x8a, 0xff, 0xff, 0x43, 0x8a, 0xff, 0xff, - 0x3b, 0x8a, 0xff, 0xff, 0x33, 0x8a, 0xff, 0xff, 0x2b, 0x8a, 0xff, 0xff, - 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, - 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, 0x23, 0x8a, 0xff, 0xff, - 0x23, 0x8a, 0xff, 0xff, 0x8e, 0xef, 0xfc, 0x3f, 0xdf, 0x9b, 0xae, 0xef, + 0x4f, 0xb1, 0xff, 0xff, 0xeb, 0xb0, 0xff, 0xff, 0xeb, 0xb0, 0xff, 0xff, + 0xeb, 0xb0, 0xff, 0xff, 0xeb, 0xb0, 0xff, 0xff, 0xeb, 0xb0, 0xff, 0xff, + 0xeb, 0xb0, 0xff, 0xff, 0xeb, 0xb0, 0xff, 0xff, 0xe3, 0xb0, 0xff, 0xff, + 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0xf8, 0xfb, 0xdd, 0xa7, 0xfb, 0x8b, 0xfc, 0xdd, 0xba, 0xc7, 0x10, 0xf4, 0x00, 0xcf, - 0x7d, 0xeb, 0xff, 0xff, 0xef, 0xfe, 0xff, 0xdf, 0xeb, 0xfe, 0xff, 0xdf, + 0x7d, 0xeb, 0xff, 0xff, 0x63, 0xff, 0xff, 0xdf, 0x5f, 0xff, 0xff, 0xdf, + 0x0f, 0xff, 0xff, 0xdf, 0xfb, 0xfe, 0xff, 0xdf, 0xf7, 0xfe, 0xff, 0xdf, 0x2b, 0xeb, 0xd8, 0xeb, 0xfe, 0x8b, 0xff, 0x47, 0x32, 0xc7, 0xef, 0xf3, 0xa5, 0xed, 0xff, 0xcc, 0x9f, 0x5d, 0xfc, 0xdd, 0x93, 0x5d, 0x92, 0x5d, 0x9f, 0x5d, 0x9c, 0x5d, 0x9b, 0x5d, 0x9d, 0x5d, 0x9e, 0x5d, 0x7f, 0xce, @@ -831,326 +584,471 @@ u8 fw_data_tx[13304] = { 0xf6, 0xf7, 0xdc, 0x67, 0xbc, 0xa6, 0x77, 0x8b, 0xbc, 0x47, 0xbf, 0xc5, 0xe9, 0xf7, 0xfc, 0xcb, 0xeb, 0xfb, 0xcb, 0xef, 0xb1, 0xa6, 0x93, 0x5d, 0xff, 0xcc, 0x9d, 0x5d, 0x5d, 0x67, 0x52, 0x4e, 0xfc, 0x67, 0xff, 0x5d, - 0x9c, 0x5d, 0x9b, 0x5d, 0x9e, 0x5d, 0xf7, 0xcf, 0x00, 0x1c, 0xff, 0x01, + 0x9c, 0x5d, 0x9b, 0x5d, 0x9e, 0x5d, 0xf7, 0xcf, 0x00, 0x1c, 0x0f, 0x02, 0xfc, 0x92, 0xbf, 0xc7, 0xdb, 0xf7, 0xd2, 0xfb, 0xdd, 0x67, 0xff, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -1198,1534 +1096,1635 @@ u8 fw_data_tx[13304] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xb1, 0xaa, 0xe9, 0xe6, 0xdf, 0xb5, 0xcd, 0xea + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xb1, 0xaa, 0xe9, 0xe6, 0xab, 0xa7, 0xd2, 0xb0 }; -u8 fw_data_rx[18424] = { - 0xff, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, - 0x97, 0xfa, 0xff, 0xff, 0x97, 0xfa, 0xff, 0xff, 0xff, 0xb9, 0xff, 0xff, - 0x67, 0xc1, 0xff, 0xff, 0x8b, 0xb9, 0xff, 0xff, 0x7b, 0xb9, 0xff, 0xff, - 0x73, 0xb9, 0xff, 0xff, 0xf3, 0xc6, 0xff, 0xff, 0x67, 0xc0, 0xff, 0xff, - 0x6b, 0xb9, 0xff, 0xff, 0x63, 0xb9, 0xff, 0xff, 0x4f, 0xb9, 0xff, 0xff, - 0x3b, 0xb9, 0xff, 0xff, 0x33, 0xb9, 0xff, 0xff, 0x2b, 0xb9, 0xff, 0xff, - 0xeb, 0xc6, 0xff, 0xff, 0x83, 0xb9, 0xff, 0xff, 0x23, 0xb9, 0xff, 0xff, - 0x1b, 0xb9, 0xff, 0xff, 0x13, 0xb9, 0xff, 0xff, 0x0b, 0xb9, 0xff, 0xff, - 0x03, 0xb9, 0xff, 0xff, 0xef, 0xb8, 0xff, 0xff, 0xe7, 0xb8, 0xff, 0xff, - 0xdf, 0xb8, 0xff, 0xff, 0xd7, 0xb8, 0xff, 0xff, 0xcf, 0xb8, 0xff, 0xff, - 0xc7, 0xb8, 0xff, 0xff, 0xc7, 0xb8, 0xff, 0xff, 0xc7, 0xb8, 0xff, 0xff, - 0xc7, 0xb8, 0xff, 0xff, 0xc7, 0xb8, 0xff, 0xff, 0xc7, 0xb8, 0xff, 0xff, - 0xc7, 0xb8, 0xff, 0xff, 0x8d, 0xef, 0xfc, 0x3f, 0xdf, 0x9b, 0xad, 0xef, - 0xfd, 0x3f, 0xde, 0x9b, 0xce, 0xef, 0x78, 0x90, 0x0e, 0xef, 0x2d, 0xef, - 0x4d, 0xef, 0x63, 0x9a, 0xf8, 0xf7, 0x7f, 0x6a, 0x7f, 0x48, 0xfc, 0xda, - 0xfc, 0xd8, 0x63, 0x9a, 0x04, 0xf0, 0x90, 0xef, 0xb0, 0xef, 0x71, 0x9f, - 0xbd, 0xb5, 0xbf, 0xc5, 0xf8, 0xf3, 0xff, 0xce, 0xdf, 0x4c, 0xfc, 0xdc, - 0xff, 0xd5, 0xbf, 0xc5, 0x03, 0xf4, 0xff, 0x1f, 0xe6, 0xff, 0xff, 0x1f, - 0x5a, 0xe7, 0xff, 0xfb, 0xff, 0xfe, 0xff, 0x7f, 0xff, 0xfb, 0xff, 0xff, - 0x07, 0xfd, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xdf, 0xd7, 0xff, 0xff, 0xdf, - 0xaf, 0xb4, 0xff, 0xff, 0xd7, 0xff, 0xff, 0xdf, 0x3f, 0xfe, 0xff, 0xdf, - 0xff, 0x1f, 0xd5, 0xdf, 0xff, 0x3f, 0xdf, 0xbf, 0x2b, 0xeb, 0xcc, 0xe9, - 0x8d, 0xed, 0xff, 0xce, 0xda, 0x4c, 0xd9, 0x4c, 0x5f, 0xcd, 0xbe, 0xbd, - 0xfc, 0xe7, 0xff, 0x1f, 0x00, 0xff, 0xdf, 0xca, 0x72, 0xed, 0xfe, 0xc9, - 0xff, 0xcf, 0xff, 0x1f, 0x3a, 0xe7, 0xe7, 0x97, 0xff, 0x8b, 0x9a, 0x6b, - 0x9f, 0x3b, 0xdf, 0xf7, 0xfa, 0x4b, 0xff, 0xcf, 0xff, 0x1f, 0x43, 0xe7, - 0xe7, 0x97, 0xff, 0x8b, 0x99, 0x6b, 0x9f, 0x3b, 0xdf, 0xf7, 0xf9, 0x4b, - 0xff, 0xd2, 0xab, 0x8a, 0xbf, 0xc2, 0x14, 0xf4, 0xfc, 0xe4, 0xbe, 0xed, - 0x3a, 0x6d, 0x3f, 0x4c, 0xb9, 0x6d, 0xbe, 0x4c, 0x00, 0xee, 0x1d, 0x4c, - 0xc0, 0xee, 0xdc, 0x4c, 0x7f, 0xcd, 0xa7, 0xbd, 0xbb, 0x4c, 0x7f, 0xc9, - 0x30, 0x4c, 0xf0, 0x92, 0xfc, 0x1b, 0x00, 0xff, 0xd7, 0x6c, 0xb2, 0x6c, - 0x7a, 0x93, 0xdd, 0x6c, 0x7a, 0x93, 0xdf, 0x6c, 0x7a, 0x93, 0xdd, 0x3b, - 0xfd, 0xb6, 0xaf, 0x4c, 0xfc, 0xdc, 0xf1, 0x9b, 0x0b, 0xf4, 0x0a, 0xee, - 0xca, 0xee, 0xe9, 0xee, 0xa9, 0xee, 0x48, 0xee, 0xff, 0xcc, 0x1f, 0x47, - 0xec, 0xc4, 0xf5, 0xf7, 0xbe, 0x3b, 0xb8, 0xdf, 0xbf, 0x3b, 0xd9, 0xdf, - 0x27, 0x92, 0x1e, 0x47, 0x2d, 0xee, 0x3d, 0x47, 0xd8, 0xfb, 0xd8, 0xc8, - 0x23, 0x9b, 0xf7, 0xf3, 0xbf, 0x3b, 0xb9, 0xdb, 0x7a, 0x92, 0x3e, 0x47, - 0x31, 0xee, 0x3d, 0x47, 0xe2, 0xfb, 0xc4, 0xc8, 0x23, 0x9b, 0xf2, 0xf3, - 0xfe, 0x3b, 0xd9, 0xdb, 0x77, 0x96, 0x3e, 0x47, 0xfe, 0x3b, 0xd9, 0xdf, - 0x1e, 0x67, 0x27, 0x92, 0x1e, 0x47, 0x37, 0xee, 0x3d, 0x47, 0xf1, 0xfb, - 0xb0, 0xc9, 0x27, 0x9b, 0xf7, 0xf3, 0xbf, 0x3b, 0xb9, 0xdb, 0x7a, 0x92, - 0x3e, 0x47, 0x1b, 0xee, 0x1d, 0x47, 0xfb, 0xfb, 0xff, 0xc9, 0x3d, 0x47, - 0x3e, 0x47, 0x3f, 0x6b, 0x1f, 0x67, 0x07, 0xa0, 0x5a, 0x3b, 0xf9, 0xb6, - 0x27, 0xa0, 0x1e, 0x67, 0x23, 0xa1, 0x1d, 0x67, 0x23, 0xa1, 0xff, 0xdc, - 0x33, 0x8b, 0xfc, 0xdb, 0xaf, 0xc8, 0x31, 0x9a, 0xf6, 0xf3, 0x3d, 0x38, - 0xf8, 0xb6, 0x68, 0x93, 0xdf, 0x47, 0xbc, 0x93, 0xe0, 0x93, 0xa4, 0x92, - 0x47, 0xf8, 0x95, 0xef, 0xbf, 0x6c, 0x37, 0xa1, 0x3f, 0x4c, 0xbe, 0x6c, - 0xb7, 0xa2, 0xbe, 0x4c, 0xbd, 0x6c, 0x57, 0xa2, 0x5d, 0x4c, 0xbc, 0x6c, - 0xf7, 0xa7, 0xfc, 0x4c, 0xbb, 0x6c, 0xd7, 0xa6, 0xdb, 0x4c, 0xec, 0xe9, - 0x6b, 0xeb, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xdf, 0x3e, 0x2b, 0x91, 0x06, - 0xa7, 0x48, 0xd5, 0x1c, 0x0f, 0x1e, 0x2d, 0x3c, 0x89, 0xab, 0xcd, 0xef, - 0x01, 0x23, 0x45, 0x67, 0x76, 0x54, 0x32, 0x10, 0xfe, 0xdc, 0xba, 0x98, - 0x66, 0x86, 0x7d, 0xa5, 0x5e, 0x14, 0x26, 0x91, 0x23, 0x43, 0xe4, 0x70, - 0x29, 0x3e, 0x9d, 0x35, 0x97, 0xef, 0xbf, 0x6c, 0xbf, 0x4f, 0xbe, 0x6c, - 0xbe, 0x4f, 0xbd, 0x6c, 0xbd, 0x4f, 0xbc, 0x6c, 0xbc, 0x4f, 0xbb, 0x6c, - 0xbb, 0x4f, 0xba, 0x6c, 0xba, 0x4f, 0x99, 0x6c, 0x99, 0x4f, 0xc3, 0x87, - 0xf3, 0xff, 0xff, 0xdf, 0xbf, 0xc6, 0xfc, 0xf7, 0xff, 0x3f, 0xdf, 0xd3, - 0xbf, 0xc7, 0xfd, 0xf7, 0xc3, 0x87, 0x3d, 0xeb, 0xbc, 0x92, 0xba, 0x92, - 0x1f, 0x38, 0x7f, 0xd7, 0xfc, 0xf3, 0xfd, 0x93, 0xff, 0xdf, 0x1e, 0x38, - 0x7f, 0xd7, 0xfc, 0xf3, 0xb9, 0x93, 0xff, 0xde, 0xfe, 0xcd, 0x3c, 0x93, - 0xfc, 0x3b, 0xbb, 0x83, 0x6f, 0x8f, 0xef, 0x8f, 0x38, 0x93, 0xfc, 0x3b, - 0xbb, 0x83, 0xff, 0xdb, 0x3c, 0x93, 0x2e, 0x8f, 0xed, 0x92, 0xdf, 0xdb, - 0x6f, 0x8f, 0xef, 0x8f, 0xbf, 0xc5, 0xf6, 0xf3, 0xff, 0x3b, 0xdf, 0xb3, - 0x32, 0x9f, 0xb3, 0x9b, 0xfd, 0xf3, 0x39, 0x9f, 0x76, 0x9f, 0x06, 0xf0, - 0xf4, 0x93, 0xb0, 0x93, 0xfa, 0x3b, 0xda, 0xb3, 0xfa, 0xf3, 0xfd, 0x93, - 0xff, 0xdf, 0xb9, 0x93, 0xff, 0xde, 0x7d, 0xeb, 0xbf, 0xc5, 0xda, 0xf3, - 0xbc, 0x90, 0x7f, 0x1a, 0xfc, 0xdf, 0xb3, 0x14, 0xff, 0xff, 0xdf, 0xf3, - 0xd2, 0x23, 0xff, 0xff, 0xff, 0xd5, 0xbf, 0xc5, 0xe5, 0xf3, 0x52, 0x1a, - 0xff, 0xff, 0x72, 0x1a, 0xfc, 0xdf, 0xb3, 0x14, 0xff, 0xff, 0xeb, 0xf3, - 0xd2, 0x23, 0xff, 0xff, 0xff, 0xd5, 0xbf, 0xc5, 0xf1, 0xf3, 0x52, 0x1a, - 0xff, 0xff, 0x72, 0x1a, 0xfc, 0xdf, 0xb3, 0x14, 0xff, 0xff, 0xf7, 0xf3, - 0xd2, 0x23, 0xff, 0xff, 0xff, 0xd5, 0x52, 0x1a, 0xff, 0xff, 0xfd, 0xfb, - 0xc3, 0x87, 0x97, 0xbe, 0xb3, 0x93, 0x8f, 0xbe, 0xb3, 0x93, 0xd0, 0xc5, - 0xf1, 0xf7, 0xd2, 0x23, 0xff, 0xdf, 0xd2, 0x23, 0xfe, 0xdf, 0xd2, 0x23, - 0xfd, 0xdf, 0xd2, 0x23, 0xfc, 0xdf, 0xf0, 0xd5, 0x52, 0x1a, 0xf0, 0xff, - 0xd0, 0xc5, 0x0b, 0xf0, 0xdc, 0xc5, 0xf7, 0xf7, 0xfc, 0xd5, 0xd2, 0x23, - 0xff, 0xdf, 0x52, 0x1a, 0xfc, 0xff, 0xdc, 0xc5, 0x05, 0xf0, 0xbf, 0xc5, - 0x1d, 0xf0, 0xff, 0xd5, 0xd2, 0x23, 0xff, 0xff, 0xbf, 0xc5, 0x22, 0xf0, - 0xff, 0xd5, 0xd2, 0x23, 0xfe, 0xff, 0xbf, 0xc5, 0x27, 0xf0, 0xd2, 0x23, - 0xfd, 0xff, 0xc3, 0x87, 0x3d, 0xeb, 0x77, 0x8b, 0xbf, 0xc5, 0xf3, 0xf3, +u8 fw_data_rx[18426] = { + 0x0b, 0xfa, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, + 0xa3, 0xf9, 0xff, 0xff, 0xa3, 0xf9, 0xff, 0xff, 0xfb, 0xbe, 0xff, 0xff, + 0x57, 0xc6, 0xff, 0xff, 0x8b, 0xcb, 0xff, 0xff, 0x8b, 0xbe, 0xff, 0xff, + 0x83, 0xbe, 0xff, 0xff, 0x93, 0xcb, 0xff, 0xff, 0x7f, 0xc5, 0xff, 0xff, + 0x7b, 0xbe, 0xff, 0xff, 0x73, 0xbe, 0xff, 0xff, 0x5f, 0xbe, 0xff, 0xff, + 0x4b, 0xbe, 0xff, 0xff, 0x43, 0xbe, 0xff, 0xff, 0x3b, 0xbe, 0xff, 0xff, + 0x9b, 0xbe, 0xff, 0xff, 0x93, 0xbe, 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0xe3, 0xff, 0xff, 0x57, 0xe3, 0xff, 0xff, 0x19, 0xe3, 0xff, 0xff, + 0x19, 0xe3, 0xff, 0xff, 0x19, 0xe3, 0xff, 0xff, 0x01, 0xe3, 0xff, 0xff, + 0x41, 0xe3, 0xff, 0xff, 0x19, 0xe3, 0xff, 0xff, 0x01, 0xe3, 0xff, 0xff, + 0x39, 0xe3, 0xff, 0xff, 0x89, 0xe3, 0xff, 0xff, 0x3b, 0xe0, 0xff, 0xff, + 0xb5, 0xe1, 0xff, 0xff, 0x3b, 0xe0, 0xff, 0xff, 0x45, 0xe2, 0xff, 0xff, + 0x31, 0xe2, 0xff, 0xff, 0xf5, 0xe1, 0xff, 0xff, 0x11, 0xe2, 0xff, 0xff, + 0xd5, 0xe1, 0xff, 0xff, 0x09, 0xe1, 0xff, 0xff, 0x6d, 0xe1, 0xff, 0xff, + 0x6d, 0xe1, 0xff, 0xff, 0xad, 0xe0, 0xff, 0xff, 0x95, 0xe0, 0xff, 0xff, + 0x41, 0xe1, 0xff, 0xff, 0x3b, 0xe0, 0xff, 0xff, 0x63, 0xe0, 0xff, 0xff, + 0x67, 0xe2, 0xff, 0xff, 0xd1, 0xdf, 0xff, 0xff, 0x71, 0xde, 0xff, 0xff, + 0x71, 0xde, 0xff, 0xff, 0x71, 0xde, 0xff, 0xff, 0xbb, 0xde, 0xff, 0xff, + 0x49, 0xdf, 0xff, 0xff, 0x85, 0xde, 0xff, 0xff, 0x85, 0xde, 0xff, 0xff, + 0x99, 0xde, 0xff, 0xff, 0xd3, 0xde, 0xff, 0xff, 0x71, 0xde, 0xff, 0xff, + 0x09, 0xdf, 0xff, 0xff, 0xc7, 0xde, 0xff, 0xff, 0xb3, 0xde, 0xff, 0xff, + 0x85, 0xde, 0xff, 0xff, 0x85, 0xde, 0xff, 0xff, 0x8f, 0xde, 0xff, 0xff, + 0xcf, 0xdc, 0xff, 0xff, 0x75, 0xdb, 0xff, 0xff, 0x75, 0xdb, 0xff, 0xff, + 0x75, 0xdb, 0xff, 0xff, 0xd5, 0xdb, 0xff, 0xff, 0x47, 0xdc, 0xff, 0xff, + 0x89, 0xdb, 0xff, 0xff, 0x89, 0xdb, 0xff, 0xff, 0xb3, 0xdb, 0xff, 0xff, + 0xed, 0xdb, 0xff, 0xff, 0x75, 0xdb, 0xff, 0xff, 0x23, 0xdc, 0xff, 0xff, + 0xe1, 0xdb, 0xff, 0xff, 0xcd, 0xdb, 0xff, 0xff, 0x89, 0xdb, 0xff, 0xff, + 0x89, 0xdb, 0xff, 0xff, 0x93, 0xdb, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, + 0x17, 0xff, 0xff, 0xdf, 0xfd, 0xff, 0xff, 0xff, 0x0f, 0xff, 0xff, 0xdf, + 0x7b, 0xf6, 0xff, 0xff, 0xd3, 0xf6, 0xff, 0xff, 0x8f, 0xf9, 0xff, 0xff, + 0xb3, 0xf8, 0xff, 0xff, 0x03, 0xf0, 0xff, 0xff, 0xdf, 0xfe, 0xeb, 0xff, + 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x01, 0x23, 0x45, 0x67, + 0x89, 0xab, 0xcd, 0xef, 0x0f, 0x1e, 0x2d, 0x3c, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -2735,7 +2734,8 @@ u8 fw_data_rx[18424] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbb, 0xe1, 0xbb, 0xc8, 0xc5, 0xb9, 0xc8, 0xa5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb1, 0xaa, 0xe9, 0xe6, - 0xdf, 0xb5, 0xcd, 0xea + 0xad, 0xa7, 0xd2, 0xb0, 0x00, 0x00 }; From 992549aa49b1769a630a0af4b9e3e05e803cb6d4 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 6 Jul 2021 02:47:50 +0200 Subject: [PATCH 086/226] drivers: power: supply: Import Xiaomi changes * From cepheus-q-oss + vayu-r-oss + nabu-r-oss Change-Id: Ib40c0b88fcbcc6df3215dd37ada30cf642758b1e Signed-off-by: firebird11 --- drivers/power/supply/power_supply_core.c | 4 + drivers/power/supply/power_supply_leds.c | 2 + drivers/power/supply/power_supply_sysfs.c | 257 ++ drivers/power/supply/qcom/battery.c | 27 + drivers/power/supply/qcom/fg-alg.c | 23 + drivers/power/supply/qcom/fg-alg.h | 3 + drivers/power/supply/qcom/fg-core.h | 97 + drivers/power/supply/qcom/fg-util.c | 18 + drivers/power/supply/qcom/qpnp-fg-gen4.c | 1541 +++++++ drivers/power/supply/qcom/qpnp-qg.c | 8 + drivers/power/supply/qcom/qpnp-smb5.c | 2285 +++++++++- drivers/power/supply/qcom/smb1390-charger.c | 128 + drivers/power/supply/qcom/smb5-lib.c | 4377 ++++++++++++++++++- drivers/power/supply/qcom/smb5-lib.h | 626 +++ drivers/power/supply/qcom/smb5-reg.h | 46 + drivers/power/supply/qcom/step-chg-jeita.c | 458 ++ drivers/power/supply/qcom/step-chg-jeita.h | 27 + include/linux/power_supply.h | 166 + 18 files changed, 9719 insertions(+), 374 deletions(-) diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c index cf7ec189a71b..eec3174898a9 100644 --- a/drivers/power/supply/power_supply_core.c +++ b/drivers/power/supply/power_supply_core.c @@ -358,7 +358,11 @@ static int __power_supply_is_system_supplied(struct device *dev, void *data) return 0; (*count)++; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if ((psy->desc->type != POWER_SUPPLY_TYPE_BATTERY) && (psy->desc->type != POWER_SUPPLY_TYPE_BMS)) +#else if (psy->desc->type != POWER_SUPPLY_TYPE_BATTERY) +#endif if (!psy->desc->get_property(psy, POWER_SUPPLY_PROP_ONLINE, &ret)) return ret.intval; diff --git a/drivers/power/supply/power_supply_leds.c b/drivers/power/supply/power_supply_leds.c index 9188b7ccdd4c..7585ec444272 100644 --- a/drivers/power/supply/power_supply_leds.c +++ b/drivers/power/supply/power_supply_leds.c @@ -114,6 +114,7 @@ static void power_supply_remove_bat_triggers(struct power_supply *psy) static void power_supply_update_gen_leds(struct power_supply *psy) { +#ifndef CONFIG_MACH_XIAOMI_SM8150 union power_supply_propval online; if (power_supply_get_property(psy, POWER_SUPPLY_PROP_ONLINE, &online)) @@ -125,6 +126,7 @@ static void power_supply_update_gen_leds(struct power_supply *psy) led_trigger_event(psy->online_trig, LED_FULL); else led_trigger_event(psy->online_trig, LED_OFF); +#endif } static int power_supply_create_gen_triggers(struct power_supply *psy) diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c index 58d89585bb90..7680bc49495b 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -47,6 +47,12 @@ static const char * const power_supply_type_text[] = { "USB_HVDCP", "USB_HVDCP_3", "USB_HVDCP_3P5", "Wireless", "USB_FLOAT", "BMS", "Parallel", "Main", "Wipower", "USB_C_UFP", "USB_C_DFP", "Charge_Pump", +#ifdef CONFIG_MACH_XIAOMI_SM8150 + "ZIMI_CAR_POWER", +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + "Batt_Verify", +#endif +#endif }; static const char * const power_supply_status_text[] = { @@ -162,8 +168,69 @@ static ssize_t power_supply_show_property(struct device *dev, else if (off >= POWER_SUPPLY_PROP_MODEL_NAME) return sprintf(buf, "%s\n", value.strval); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + else if ((off == POWER_SUPPLY_PROP_ROMID) || (off == POWER_SUPPLY_PROP_DS_STATUS)) + return scnprintf(buf, PAGE_SIZE, "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + value.arrayval[0], value.arrayval[1], value.arrayval[2], value.arrayval[3], + value.arrayval[4], value.arrayval[5], value.arrayval[6], value.arrayval[7]); + else if ((off == POWER_SUPPLY_PROP_PAGE0_DATA) || + (off == POWER_SUPPLY_PROP_PAGE1_DATA) || + (off == POWER_SUPPLY_PROP_PAGEDATA)) + return scnprintf(buf, PAGE_SIZE, "%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", + value.arrayval[0], value.arrayval[1], value.arrayval[2], value.arrayval[3], + value.arrayval[4], value.arrayval[5], value.arrayval[6], value.arrayval[7], + value.arrayval[8], value.arrayval[9], value.arrayval[10], value.arrayval[11], + value.arrayval[12], value.arrayval[13], value.arrayval[14], value.arrayval[15]); + else if (off == POWER_SUPPLY_PROP_VERIFY_MODEL_NAME) + return sprintf(buf, "%s\n", value.strval); +#endif if (off == POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT) return sprintf(buf, "%lld\n", value.int64val); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + else if (off == POWER_SUPPLY_PROP_WIRELESS_VERSION) + return scnprintf(buf, PAGE_SIZE, "0x%x\n", + value.intval); + else if (off == POWER_SUPPLY_PROP_WIRELESS_WAKELOCK) + return scnprintf(buf, PAGE_SIZE, "%d\n", + value.intval); + else if (off == POWER_SUPPLY_PROP_SIGNAL_STRENGTH) + return scnprintf(buf, PAGE_SIZE, "%d\n", + value.intval); + else if (off == POWER_SUPPLY_PROP_WIRELESS_CP_EN) + return scnprintf(buf, PAGE_SIZE, "%d\n", + value.intval); + else if (off == POWER_SUPPLY_PROP_TYPE_RECHECK) + return scnprintf(buf, PAGE_SIZE, "0x%x\n", + value.intval); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + else if (off == POWER_SUPPLY_PROP_TX_MAC) + return scnprintf(buf, PAGE_SIZE, "%llx\n", + value.int64val); +#ifdef CONFIG_MACH_XIAOMI_NABU + else if (off == POWER_SUPPLY_PROP_PEN_MAC) + return scnprintf(buf, PAGE_SIZE, "%llx\n", + value.int64val); + else if (off == POWER_SUPPLY_PROP_REVERSE_PEN_SOC) + return scnprintf(buf, PAGE_SIZE, "%d\n", + value.intval); + else if (off == POWER_SUPPLY_PROP_REVERSE_CHG_STATE) + return scnprintf(buf, PAGE_SIZE, "%d\n", + value.intval); + else if (off == POWER_SUPPLY_PROP_REVERSE_PEN_CHG_STATE) + return scnprintf(buf, PAGE_SIZE, "%d\n", + value.intval); +#endif + else if (off == POWER_SUPPLY_PROP_RX_CR) + return scnprintf(buf, PAGE_SIZE, "%llx\n", + value.int64val); + else if (off == POWER_SUPPLY_PROP_RX_CEP) + return scnprintf(buf, PAGE_SIZE, "%llx\n", + value.int64val); + else if (off == POWER_SUPPLY_PROP_BT_STATE) + return scnprintf(buf, PAGE_SIZE, "%x\n", + value.intval); +#endif +#endif else return sprintf(buf, "%d\n", value.intval); } @@ -175,6 +242,10 @@ static ssize_t power_supply_store_property(struct device *dev, struct power_supply *psy = dev_get_drvdata(dev); const ptrdiff_t off = attr - power_supply_attrs; union power_supply_propval value; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + long val; + int64_t num_long; +#endif /* maybe it is a enum property? */ switch (off) { @@ -196,6 +267,46 @@ static ssize_t power_supply_store_property(struct device *dev, case POWER_SUPPLY_PROP_SCOPE: ret = sysfs_match_string(power_supply_scope_text, buf); break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_BT_STATE: + case POWER_SUPPLY_PROP_RX_CR: + ret = kstrtol(buf, 16, &val); + if (ret < 0) + return ret; + ret = val; + break; + case POWER_SUPPLY_PROP_RX_CEP: + ret = kstrtol(buf, 16, &val); + if (ret < 0) + return ret; + ret = val; + break; + case POWER_SUPPLY_PROP_TX_MAC: + ret = kstrtoll(buf, 16, &num_long); + if (ret < 0) + return ret; + value.int64val = num_long; + ret = power_supply_set_property(psy, off, &value); + if (ret < 0) + return ret; + else + return count; + break; +#ifdef CONFIG_MACH_XIAOMI_NABU + case POWER_SUPPLY_PROP_PEN_MAC: + ret = kstrtoll(buf, 16, &num_long); + if (ret < 0) + return ret; + value.int64val = num_long; + ret = power_supply_set_property(psy, off, &value); + if (ret < 0) + return ret; + else + return count; + + break; +#endif +#endif default: ret = -EINVAL; } @@ -255,6 +366,10 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(charge_now), POWER_SUPPLY_ATTR(charge_avg), POWER_SUPPLY_ATTR(charge_counter), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(termination_current), + POWER_SUPPLY_ATTR(ffc_termination_current), +#endif POWER_SUPPLY_ATTR(constant_charge_current), POWER_SUPPLY_ATTR(constant_charge_current_max), POWER_SUPPLY_ATTR(constant_charge_voltage), @@ -272,6 +387,14 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(capacity_alert_min), POWER_SUPPLY_ATTR(capacity_alert_max), POWER_SUPPLY_ATTR(capacity_level), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(shutdown_delay), + POWER_SUPPLY_ATTR(shutdown_delay_en), + POWER_SUPPLY_ATTR(raw_capacity), + POWER_SUPPLY_ATTR(soc_decimal), + POWER_SUPPLY_ATTR(soc_decimal_rate), + POWER_SUPPLY_ATTR(cold_thermal_level), +#endif POWER_SUPPLY_ATTR(temp), POWER_SUPPLY_ATTR(temp_max), POWER_SUPPLY_ATTR(temp_min), @@ -295,6 +418,10 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(charge_enabled), POWER_SUPPLY_ATTR(set_ship_mode), POWER_SUPPLY_ATTR(real_type), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_ATTR(hvdcp3_type), + POWER_SUPPLY_ATTR(quick_charge_type), +#endif POWER_SUPPLY_ATTR(charge_now_raw), POWER_SUPPLY_ATTR(charge_now_error), POWER_SUPPLY_ATTR(capacity_raw), @@ -305,6 +432,10 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(pin_enabled), POWER_SUPPLY_ATTR(input_suspend), POWER_SUPPLY_ATTR(input_voltage_regulation), +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_ATTR(input_voltage_vrect), + POWER_SUPPLY_ATTR(rx_iout), +#endif POWER_SUPPLY_ATTR(input_current_max), POWER_SUPPLY_ATTR(input_current_trim), POWER_SUPPLY_ATTR(input_current_settled), @@ -333,6 +464,9 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(flash_trigger), POWER_SUPPLY_ATTR(force_tlim), POWER_SUPPLY_ATTR(dp_dm), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(dp_dm_bq), +#endif POWER_SUPPLY_ATTR(input_current_limited), POWER_SUPPLY_ATTR(input_current_now), POWER_SUPPLY_ATTR(charge_qnovo_enable), @@ -349,8 +483,17 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(typec_src_rp), POWER_SUPPLY_ATTR(pd_allowed), POWER_SUPPLY_ATTR(pd_active), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_ATTR(pd_authentication), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(pd_remove_compensation), +#endif +#endif POWER_SUPPLY_ATTR(pd_in_hard_reset), POWER_SUPPLY_ATTR(pd_current_max), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(apdo_max), +#endif POWER_SUPPLY_ATTR(pd_usb_suspend_supported), POWER_SUPPLY_ATTR(charger_temp), POWER_SUPPLY_ATTR(charger_temp_max), @@ -363,6 +506,10 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(parallel_mode), POWER_SUPPLY_ATTR(die_health), POWER_SUPPLY_ATTR(connector_health), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(connector_temp), + POWER_SUPPLY_ATTR(vbus_disable), +#endif POWER_SUPPLY_ATTR(ctm_current_max), POWER_SUPPLY_ATTR(hw_current_max), POWER_SUPPLY_ATTR(pr_swap), @@ -372,15 +519,75 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(pd_voltage_max), POWER_SUPPLY_ATTR(pd_voltage_min), POWER_SUPPLY_ATTR(sdp_current_max), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_ATTR(dc_thermal_levels), +#endif POWER_SUPPLY_ATTR(connector_type), POWER_SUPPLY_ATTR(parallel_batfet_mode), POWER_SUPPLY_ATTR(parallel_fcc_max), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_ATTR(wireless_version), +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_ATTR(wireless_fw_version), +#endif + POWER_SUPPLY_ATTR(signal_strength), + POWER_SUPPLY_ATTR(wireless_cp_en), + POWER_SUPPLY_ATTR(wireless_power_good_en), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(sw_disabel_dc_en), +#endif + POWER_SUPPLY_ATTR(wireless_wakelock), +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_ATTR(wireless_tx_id), +#endif + POWER_SUPPLY_ATTR(tx_adapter), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(tx_mac), + POWER_SUPPLY_ATTR(rx_cr), + POWER_SUPPLY_ATTR(rx_cep), + POWER_SUPPLY_ATTR(bt_state), +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_ATTR(pen_mac), +#endif +#endif POWER_SUPPLY_ATTR(min_icl), POWER_SUPPLY_ATTR(moisture_detected), POWER_SUPPLY_ATTR(batt_profile_version), POWER_SUPPLY_ATTR(batt_full_current), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(battery_charging_limited), + POWER_SUPPLY_ATTR(slowly_charging), + POWER_SUPPLY_ATTR(bq_input_suspend), +#endif POWER_SUPPLY_ATTR(recharge_soc), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(recharge_vbat), + POWER_SUPPLY_ATTR(sys_termination_current), + POWER_SUPPLY_ATTR(ffc_sys_termination_current), + POWER_SUPPLY_ATTR(vbatt_full_vol), + POWER_SUPPLY_ATTR(fcc_vbatt_full_vol), + POWER_SUPPLY_ATTR(ki_coeff_current), + /* battery verify properties */ + POWER_SUPPLY_ATTR(romid), + POWER_SUPPLY_ATTR(ds_status), + POWER_SUPPLY_ATTR(pagenumber), + POWER_SUPPLY_ATTR(pagedata), + POWER_SUPPLY_ATTR(authen_result), + POWER_SUPPLY_ATTR(session_seed), + POWER_SUPPLY_ATTR(s_secret), + POWER_SUPPLY_ATTR(challenge), + POWER_SUPPLY_ATTR(auth_anon), + POWER_SUPPLY_ATTR(auth_bdconst), + POWER_SUPPLY_ATTR(page0_data), + POWER_SUPPLY_ATTR(page1_data), + POWER_SUPPLY_ATTR(verify_model_name), + POWER_SUPPLY_ATTR(maxim_batt_cycle_count), +#endif POWER_SUPPLY_ATTR(hvdcp_opti_allowed), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(fastcharge_mode), +#endif POWER_SUPPLY_ATTR(smb_en_mode), POWER_SUPPLY_ATTR(smb_en_reason), POWER_SUPPLY_ATTR(esr_actual), @@ -390,6 +597,11 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(force_recharge), POWER_SUPPLY_ATTR(fcc_stepper_enable), POWER_SUPPLY_ATTR(toggle_stat), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_ATTR(type_recheck), + POWER_SUPPLY_ATTR(liquid_detection), + POWER_SUPPLY_ATTR(dynamic_fv_enabled), +#endif POWER_SUPPLY_ATTR(main_fcc_max), POWER_SUPPLY_ATTR(fg_reset), POWER_SUPPLY_ATTR(qc_opti_disable), @@ -397,6 +609,9 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(batt_age_level), POWER_SUPPLY_ATTR(voltage_vph), POWER_SUPPLY_ATTR(chip_version), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(chip_ok), +#endif POWER_SUPPLY_ATTR(therm_icl_limit), POWER_SUPPLY_ATTR(dc_reset), POWER_SUPPLY_ATTR(scale_mode_en), @@ -421,8 +636,50 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(cp_toggle_switcher), POWER_SUPPLY_ATTR(cp_irq_status), POWER_SUPPLY_ATTR(cp_ilim), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_ATTR(step_index), + /* Bq charge pump properties */ + POWER_SUPPLY_ATTR(ti_battery_present), + POWER_SUPPLY_ATTR(ti_vbus_present), + POWER_SUPPLY_ATTR(ti_battery_voltage), + POWER_SUPPLY_ATTR(ti_battery_current), + POWER_SUPPLY_ATTR(ti_battery_temperature), + POWER_SUPPLY_ATTR(ti_bus_voltage), + POWER_SUPPLY_ATTR(ti_bus_current), + POWER_SUPPLY_ATTR(ti_bus_temperature), + POWER_SUPPLY_ATTR(ti_die_temperature), + POWER_SUPPLY_ATTR(ti_alarm_status), + POWER_SUPPLY_ATTR(ti_fault_status), + POWER_SUPPLY_ATTR(ti_reg_status), + POWER_SUPPLY_ATTR(ti_set_bus_protection_for_qc3), + POWER_SUPPLY_ATTR(ti_bus_error_status), + POWER_SUPPLY_ATTR(ti_charge_mode), + POWER_SUPPLY_ATTR(ti_bypass_mode_enable), +#endif POWER_SUPPLY_ATTR(irq_status), POWER_SUPPLY_ATTR(parallel_output_mode), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* DIV 2 properties */ + POWER_SUPPLY_ATTR(div_2_mode), + POWER_SUPPLY_ATTR(reverse_chg_mode), + POWER_SUPPLY_ATTR(reverse_chg_state), +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_ATTR(reverse_pen_chg_state), + POWER_SUPPLY_ATTR(reverse_gpio_state), +#endif + POWER_SUPPLY_ATTR(reset_div_2_mode), +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_ATTR(aicl_enable), + POWER_SUPPLY_ATTR(otg_state), + POWER_SUPPLY_ATTR(reverse_chg_hall3), + POWER_SUPPLY_ATTR(reverse_chg_hall4), + POWER_SUPPLY_ATTR(reverse_pen_soc), + POWER_SUPPLY_ATTR(reverse_vout), + POWER_SUPPLY_ATTR(reverse_iout), +#endif + POWER_SUPPLY_ATTR(rx_op_ble), + POWER_SUPPLY_ATTR(op_ble), +#endif /* Local extensions of type int64_t */ POWER_SUPPLY_ATTR(charge_counter_ext), /* Properties of type `const char *' */ diff --git a/drivers/power/supply/qcom/battery.c b/drivers/power/supply/qcom/battery.c index 0c6a11b6961a..327357ecc34e 100644 --- a/drivers/power/supply/qcom/battery.c +++ b/drivers/power/supply/qcom/battery.c @@ -1348,6 +1348,33 @@ static int usb_icl_vote_callback(struct votable *votable, void *data, == POWER_SUPPLY_PL_USBMID_USBMID) cp_configure_ilim(chip, ICL_CHANGE_VOTER, icl_ua); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!chip->usb_psy) + chip->usb_psy = power_supply_get_by_name("usb"); + if (!chip->usb_psy) { + pr_err("Couldn't get usb psy\n"); + return -ENODEV; + } + + rc = power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_SMB_EN_REASON, &pval); + if (rc < 0) { + pr_err("Couldn't get cp reason rc=%d\n", rc); + return rc; + } + + if (chip->cp_ilim_votable) { + if (pval.intval != POWER_SUPPLY_CP_WIRELESS) + vote(chip->cp_ilim_votable, ICL_CHANGE_VOTER, true, icl_ua); + else + vote(chip->cp_ilim_votable, ICL_CHANGE_VOTER, false, 0); + } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + cp_configure_ilim(chip, ICL_CHANGE_VOTER, icl_ua); +#endif +#endif + return 0; } diff --git a/drivers/power/supply/qcom/fg-alg.c b/drivers/power/supply/qcom/fg-alg.c index c27f1d481cf3..f9283c86982d 100644 --- a/drivers/power/supply/qcom/fg-alg.c +++ b/drivers/power/supply/qcom/fg-alg.c @@ -277,6 +277,29 @@ int get_cycle_counts(struct cycle_counter *counter, const char **buf) return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +/** + * set_cycle_count - + * @counter: Cycle counter object + * @value: The cycle count value to be set + * + * Get average cycle count for all buckets + * + */ +int set_cycle_count(struct cycle_counter *counter, u16 count) +{ + int rc, id; + + for (id = 0; id < BUCKET_COUNT; id++) { + rc = counter->store_count(counter->data, &count, id, 2); + if (rc < 0) + pr_err("failed to clear cycle counter rc=%d\n", rc); + } + + return 0; +} +#endif + /** * cycle_count_init - * @counter: Cycle counter object diff --git a/drivers/power/supply/qcom/fg-alg.h b/drivers/power/supply/qcom/fg-alg.h index 0bf466cce465..4a84d76dba1e 100644 --- a/drivers/power/supply/qcom/fg-alg.h +++ b/drivers/power/supply/qcom/fg-alg.h @@ -157,6 +157,9 @@ void cycle_count_update(struct cycle_counter *counter, int batt_soc, int charge_status, bool charge_done, bool input_present); int get_cycle_count(struct cycle_counter *counter, int *count); int get_cycle_counts(struct cycle_counter *counter, const char **buf); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int set_cycle_count(struct cycle_counter *counter, u16 count); +#endif int cycle_count_init(struct cycle_counter *counter); void cap_learning_abort(struct cap_learning *cl); void cap_learning_update(struct cap_learning *cl, int batt_temp, diff --git a/drivers/power/supply/qcom/fg-core.h b/drivers/power/supply/qcom/fg-core.h index 267cdaf3b926..23d8256484e6 100644 --- a/drivers/power/supply/qcom/fg-core.h +++ b/drivers/power/supply/qcom/fg-core.h @@ -92,12 +92,26 @@ #define FULL_CAPACITY 100 #define FULL_SOC_RAW 255 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define FULL_SOC_REPORT_THR 250 +#endif #define DEBUG_BATT_SOC 67 #define BATT_MISS_SOC 50 #define ESR_SOH_SOC 50 #define EMPTY_SOC 0 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define VBAT_RESTART_FG_EMPTY_UV 3700000 +#define TEMP_THR_RESTART_FG 150 +#define RESTART_FG_START_WORK_MS 1000 +#define RESTART_FG_WORK_MS 2000 +#define EMPTY_REPORT_SOC 1 + +#define VBAT_CRITICAL_LOW_THR 2800 +#define EMPTY_DEBOUNCE_TIME_COUNT_MAX 5 +#endif + enum prof_load_status { PROFILE_MISSING, PROFILE_LOADED, @@ -332,12 +346,23 @@ struct fg_batt_props { char *batt_profile; int float_volt_uv; int vbatt_full_mv; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int ffc_vbatt_full_mv; +#endif int fastchg_curr_ma; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int nom_cap_uah; +#endif int *therm_coeffs; int therm_ctr_offset; int therm_pull_up_kohms; int *rslow_normal_coeffs; int *rslow_low_coeffs; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int ffc_term_curr_ma; + int ffc_low_temp_term_curr_ma; + int ffc_high_temp_term_curr_ma; +#endif }; struct fg_cyc_ctr_data { @@ -421,6 +446,24 @@ static const struct fg_pt fg_tsmc_osc_table[] = { { 90, 444992 }, }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define BATT_MA_AVG_SAMPLES 8 +struct batt_params { + bool update_now; + int batt_raw_soc; + int batt_soc; + int samples_num; + int samples_index; + int batt_ma_avg_samples[BATT_MA_AVG_SAMPLES]; + int batt_ma_avg; + int batt_ma_prev; + int batt_ma; + int batt_mv; + int batt_temp; + struct timespec last_soc_change_time; +}; +#endif + struct fg_memif { struct fg_dma_address *addr_map; int num_partitions; @@ -428,6 +471,15 @@ struct fg_memif { u8 num_bytes_per_word; }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +struct cold_thermal { + int index; + int temp_l; + int temp_h; + int curr_th; +}; +#endif + struct fg_dev { struct thermal_zone_device *tz_dev; struct device *dev; @@ -440,6 +492,12 @@ struct fg_dev { struct power_supply *dc_psy; struct power_supply *parallel_psy; struct power_supply *pc_port_psy; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct power_supply *max_verify_psy; +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + struct power_supply *max_verify_slave_psy; +#endif struct fg_irq_info *irqs; struct votable *awake_votable; struct votable *delta_bsoc_irq_en_votable; @@ -463,6 +521,9 @@ struct fg_dev { u32 mem_if_base; u32 rradc_base; u32 wa_flags; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int cycle_count; +#endif u32 esr_wakeup_ms; u32 awake_status; int batt_id_ohms; @@ -480,6 +541,10 @@ struct fg_dev { int last_recharge_volt_mv; int delta_temp_irq_count; enum esr_filter_status esr_flt_sts; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int vbatt_full_volt_uv; + int vbat_critical_low_count; +#endif bool profile_available; enum prof_load_status profile_load_status; bool battery_missing; @@ -490,19 +555,51 @@ struct fg_dev { bool use_ima_single_mode; bool usb_present; bool twm_state; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool report_full; +#endif bool use_dma; bool qnovo_enable; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool empty_restart_fg; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool profile_already_find; + bool input_present; + bool batt_temp_low; + bool shutdown_delay; + /* cold thermal related */ + struct cold_thermal *cold_thermal_seq; + int cold_thermal_len; + int curr_cold_thermal_level; +#else + bool input_present; +#endif +#endif enum fg_version version; bool suspended; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct batt_params param; + struct delayed_work soc_monitor_work; +#endif struct completion soc_update; struct completion soc_ready; struct delayed_work profile_load_work; struct work_struct status_change_work; struct work_struct esr_sw_work; struct delayed_work sram_dump_work; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int fake_authentic; + int fake_chip_ok; + int maxim_cycle_count; + int batt_fake_temp; +#endif struct work_struct esr_filter_work; struct alarm esr_filter_alarm; ktime_t last_delta_temp_time; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct delayed_work empty_restart_fg_work; + struct delayed_work soc_work; +#endif }; /* Debugfs data structures are below */ diff --git a/drivers/power/supply/qcom/fg-util.c b/drivers/power/supply/qcom/fg-util.c index c1b66cc1f400..7397089a4a68 100644 --- a/drivers/power/supply/qcom/fg-util.c +++ b/drivers/power/supply/qcom/fg-util.c @@ -407,6 +407,7 @@ void fg_notify_charger(struct fg_dev *fg) } } +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (fg->bp.fastchg_curr_ma > 0) { prop.intval = fg->bp.fastchg_curr_ma * 1000; rc = power_supply_set_property(fg->batt_psy, @@ -418,6 +419,7 @@ void fg_notify_charger(struct fg_dev *fg) return; } } +#endif } bool batt_psy_initialized(struct fg_dev *fg) @@ -867,6 +869,10 @@ int fg_restart(struct fg_dev *fg, int wait_time_ms) goto out; } out: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (fg->empty_restart_fg) + fg->empty_restart_fg = false; +#endif fg->fg_restarting = false; return rc; } @@ -916,10 +922,22 @@ int fg_get_msoc(struct fg_dev *fg, int *msoc) * of the values 1-254 will be scaled to 1-99. DIV_ROUND_UP will not * be suitable here as it rounds up any value higher than 252 to 100. */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if ((*msoc >= FULL_SOC_REPORT_THR - 2) + && (*msoc < FULL_SOC_RAW) && fg->report_full) { + *msoc = DIV_ROUND_CLOSEST(*msoc * FULL_CAPACITY, FULL_SOC_RAW) + 1; + if (*msoc >= FULL_CAPACITY) + *msoc = FULL_CAPACITY; + } else +#endif if (*msoc == FULL_SOC_RAW) *msoc = 100; else if (*msoc == 0) *msoc = 0; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + else if (*msoc >= FULL_SOC_REPORT_THR - 4 && *msoc <= FULL_SOC_REPORT_THR - 3 && fg->report_full) + *msoc = DIV_ROUND_CLOSEST(*msoc * FULL_CAPACITY, FULL_SOC_RAW); +#endif else *msoc = DIV_ROUND_CLOSEST((*msoc - 1) * (FULL_CAPACITY - 2), FULL_SOC_RAW - 2) + 1; diff --git a/drivers/power/supply/qcom/qpnp-fg-gen4.c b/drivers/power/supply/qcom/qpnp-fg-gen4.c index 892071fa67cc..642d1644be13 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen4.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen4.c @@ -23,6 +23,9 @@ #include #include #include +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include +#endif #include "fg-core.h" #include "fg-reg.h" #include "fg-alg.h" @@ -209,6 +212,9 @@ #define FIRST_LOG_CURRENT_v2_WORD 471 #define FIRST_LOG_CURRENT_v2_OFFSET 0 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define DEFAULT_FFC_TERM_CURRENT 1500 +#endif static struct fg_irq_info fg_irqs[FG_GEN4_IRQ_MAX]; /* DT parameters for FG device */ @@ -222,11 +228,19 @@ struct fg_dt_props { bool esr_calib_dischg; bool soc_hi_res; bool soc_scale_mode; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool shutdown_delay_enable; + int *dec_rate_seq; + int dec_rate_len; +#endif int cutoff_volt_mv; int empty_volt_mv; int sys_min_volt_mv; int cutoff_curr_ma; int sys_term_curr_ma; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int ffc_sys_term_curr_ma; +#endif int delta_soc_thr; int vbatt_scale_thr_mv; int scale_timer_ms; @@ -254,6 +268,10 @@ struct fg_dt_props { int ki_coeff_hi_chg; int ki_coeff_lo_med_chg_thr_ma; int ki_coeff_med_hi_chg_thr_ma; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int ffc_ki_coeff_lo_med_chg_thr_ma; + int ffc_ki_coeff_med_hi_chg_thr_ma; +#endif int ki_coeff_cutoff_gain; int ki_coeff_full_soc_dischg[2]; int ki_coeff_soc[KI_COEFF_SOC_LEVELS]; @@ -280,10 +298,37 @@ struct fg_gen4_chip { struct votable *parallel_current_en_votable; struct votable *mem_attn_irq_en_votable; struct work_struct esr_calib_work; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct work_struct vbat_sync_work; +#endif struct work_struct soc_scale_work; struct alarm esr_fast_cal_timer; struct alarm soc_scale_alarm_timer; struct delayed_work pl_enable_work; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct delayed_work battery_authentic_work; + int battery_authentic_result; +#ifdef CONFIG_MACH_XIAOMI_NABU + int battery_authentic_slave_result; + int battery_chip_ok; + int battery_chip_slave_ok; +#endif + struct delayed_work ds_romid_work; + unsigned char ds_romid[8]; +#ifdef CONFIG_MACH_XIAOMI_NABU + unsigned char ds_slave_romid[8]; +#endif + struct delayed_work ds_status_work; + unsigned char ds_status[8]; +#ifdef CONFIG_MACH_XIAOMI_NABU + unsigned char ds_slave_status[8]; +#endif + struct delayed_work ds_page0_work; + unsigned char ds_page0[16]; +#ifdef CONFIG_MACH_XIAOMI_NABU + unsigned char ds_slave_page0[16]; +#endif +#endif struct work_struct pl_current_en_work; struct completion mem_attn; struct mutex soc_scale_lock; @@ -324,6 +369,10 @@ struct fg_gen4_chip { bool vbatt_low; bool soc_scale_mode; bool chg_term_good; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool fastcharge_mode_enabled; + bool cold_thermal_support; +#endif }; struct bias_config { @@ -337,6 +386,11 @@ module_param_named( debug_mask, fg_gen4_debug_mask, int, 0600 ); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static bool is_batt_vendor_sunwoda; +static bool is_batt_vendor_nvt; +#endif + static bool fg_profile_dump; module_param_named( profile_dump, fg_profile_dump, bool, 0600 @@ -740,6 +794,13 @@ static int fg_gen4_get_battery_temp(struct fg_dev *fg, int *val) int rc = 0; u16 buf; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (fg->batt_fake_temp != -EINVAL) { + *val = fg->batt_fake_temp; + pr_err("use fake batt temp =%d\n", fg->batt_fake_temp); + return 0; + } +#endif rc = fg_sram_read(fg, BATT_TEMP_WORD, BATT_TEMP_OFFSET, (u8 *)&buf, 2, FG_IMA_DEFAULT); if (rc < 0) { @@ -917,6 +978,20 @@ static int fg_gen4_get_prop_capacity(struct fg_dev *fg, int *val) return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = fg_get_msoc(fg, &msoc); + if (rc < 0) + return rc; + + if (fg->empty_restart_fg && (msoc == 0)) + msoc = EMPTY_REPORT_SOC; + + if (chip->dt.linearize_soc && fg->delta_soc > 0) + *val = fg->maint_soc; + else + *val = msoc; +#endif + if (chip->soc_scale_mode) { mutex_lock(&chip->soc_scale_lock); *val = chip->soc_scale_msoc; @@ -968,6 +1043,48 @@ static int fg_gen4_get_prop_capacity_raw(struct fg_gen4_chip *chip, int *val) return 0; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int fg_gen4_get_prop_soc_decimal_rate(struct fg_gen4_chip *chip, int *val) +{ + struct fg_dev *fg = &chip->fg; + int i, soc, rc = 0; + + rc = fg_gen4_get_prop_capacity(fg, &soc); + if (rc < 0) { + pr_err("Failed to get battery capacity, rc=%d\n", rc); + return 0; + } + + for (i = 0; i < chip->dt.dec_rate_len; i += 2) { + if (soc < chip->dt.dec_rate_seq[i]) { + *val = chip->dt.dec_rate_seq[i - 1]; + return 0; + } + } + + *val = chip->dt.dec_rate_seq[chip->dt.dec_rate_len - 1]; + + return 0; +} + +static int fg_gen4_get_prop_soc_decimal(struct fg_gen4_chip *chip, int *val) +{ + int rc; + int soc_decimal, soc_decimal_rate; + + union power_supply_propval pval = {0,}; + + rc = fg_gen4_get_prop_capacity_raw(chip, &pval.intval); + soc_decimal = pval.intval % 100; + rc = fg_gen4_get_prop_soc_decimal_rate(chip, &soc_decimal_rate); + if (soc_decimal + soc_decimal_rate >= 100) + soc_decimal -= soc_decimal_rate; + + *val = soc_decimal; + return rc; +} +#endif + static inline void get_esr_meas_current(int curr_ma, u8 *val) { switch (curr_ma) { @@ -1684,6 +1801,10 @@ static int fg_gen4_rapid_soc_config(struct fg_gen4_chip *chip, bool en) return 0; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int retry_batt_profile; +#define BATT_PROFILE_RETRY_COUNT_MAX 5 +#endif static int fg_gen4_get_batt_profile(struct fg_dev *fg) { struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg); @@ -1703,8 +1824,72 @@ static int fg_gen4_get_batt_profile(struct fg_dev *fg) fg->batt_id_ohms / 1000, chip->batt_age_level, &avail_age_level); else +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + { + profile_node = ERR_PTR(-ENXIO); + /* if cmdline battery profile vendor is passed to fg driver, use cmdline result */ + if (is_batt_vendor_sunwoda && !fg->profile_already_find) { + pr_err("is_batt_vendor_sunwoda is %d\n", is_batt_vendor_sunwoda); + fg->profile_already_find = true; +#ifdef CONFIG_MACH_XIAOMI_NABU + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "K82_sunwoda_8720mah"); +#else + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "J20S_sunwoda_5160mah"); +#endif + } else if (is_batt_vendor_nvt && !fg->profile_already_find) { + pr_err("is_batt_vendor_nvt is %d\n", is_batt_vendor_nvt); + fg->profile_already_find = true; + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "J20S_nvt_5160mah"); + } else { + pr_err("cmdline of batt profile is not defined, read page0 to reload file\n"); + } + // the battery is xiaomi's batt; FC code, custom id + if ((chip->ds_romid[0] == 0x9F) && ((chip->ds_romid[5] & 0xF0) == 0xF0) + && (chip->ds_romid[6] == 04) && !fg->profile_already_find) { + if ((chip->ds_page0[0] == 'S') || (chip->ds_page0[0] == 'X')) { +#ifdef CONFIG_MACH_XIAOMI_NABU + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "K82_sunwoda_8720mah"); +#else + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "J20S_sunwoda_5160mah"); +#endif + } else if ((chip->ds_page0[0] == 'N') || (chip->ds_page0[0] == 'A')) { + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "J20S_nvt_5160mah"); + } else { + retry_batt_profile++; + } + } else if (!fg->profile_already_find) { + retry_batt_profile++; + } + + if (retry_batt_profile < BATT_PROFILE_RETRY_COUNT_MAX + && !fg->profile_already_find) { + if (profile_node == ERR_PTR(-ENXIO)) { + pr_warn("verifty battery fail. recheck after, retry:%d\n", + retry_batt_profile); + schedule_delayed_work(&fg->profile_load_work, 500); + } + } else if (!fg->profile_already_find) { +#ifdef CONFIG_MACH_XIAOMI_NABU + pr_warn("verifty battery fail. use default profile K82_sunwoda_8720mah\n"); + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "K82_sunwoda_8720mah"); +#else + pr_warn("verifty battery fail. use default profile J20S_nvt_5160mah\n"); + profile_node = of_batterydata_get_best_profile(batt_node, // comment for git + fg->batt_id_ohms / 1000, "J20S_nvt_5160mah"); +#endif + } + } +#else profile_node = of_batterydata_get_best_profile(batt_node, fg->batt_id_ohms / 1000, NULL); +#endif if (IS_ERR(profile_node)) return PTR_ERR(profile_node); @@ -1763,6 +1948,22 @@ static int fg_gen4_get_batt_profile(struct fg_dev *fg) fg->bp.fastchg_curr_ma = -EINVAL; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = of_property_read_u32(profile_node, "qcom,ffc-low-temp-term-current-ma", + &fg->bp.ffc_low_temp_term_curr_ma); + if (rc < 0) { + pr_err("battery system current unavailable, rc:%d\n", rc); + fg->bp.ffc_low_temp_term_curr_ma = -DEFAULT_FFC_TERM_CURRENT; + } + + rc = of_property_read_u32(profile_node, "qcom,ffc-high-temp-term-current-ma", + &fg->bp.ffc_high_temp_term_curr_ma); + if (rc < 0) { + pr_err("battery system current unavailable, rc:%d\n", rc); + fg->bp.ffc_high_temp_term_curr_ma = -DEFAULT_FFC_TERM_CURRENT; + } +#endif + rc = of_property_read_u32(profile_node, "qcom,fg-cc-cv-threshold-mv", &fg->bp.vbatt_full_mv); if (rc < 0) { @@ -1770,6 +1971,24 @@ static int fg_gen4_get_batt_profile(struct fg_dev *fg) fg->bp.vbatt_full_mv = -EINVAL; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = of_property_read_u32(profile_node, "qcom,fg-ffc-cc-cv-threshold-mv", + &fg->bp.ffc_vbatt_full_mv); + if (rc < 0) { + pr_err("battery ffc cc_cv threshold unavailable, rc:%d\n", rc); + fg->bp.ffc_vbatt_full_mv = -EINVAL; + } +#endif + + rc = of_property_read_u32(profile_node, "qcom,nom-batt-capacity-mah", + &fg->bp.nom_cap_uah); + if (rc < 0) { + pr_err("battery nominal capacity unavailable, rc:%d\n", rc); + fg->bp.nom_cap_uah = -EINVAL; + } +#endif + if (of_find_property(profile_node, "qcom,therm-coefficients", &len)) { len /= sizeof(u32); if (len == BATT_THERM_NUM_COEFFS) { @@ -2738,6 +2957,10 @@ static int fg_gen4_adjust_recharge_soc(struct fg_gen4_chip *chip) if (is_input_present(fg)) { if (fg->charge_done) { if (!fg->recharge_soc_adjusted) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (fg->health == POWER_SUPPLY_HEALTH_GOOD) + return 0; +#endif /* Get raw monotonic SOC for calculation */ rc = fg_get_msoc(fg, &msoc); if (rc < 0) { @@ -3407,6 +3630,9 @@ static irqreturn_t fg_vbatt_low_irq_handler(int irq, void *data) int rc, vbatt_mv, msoc_raw; s64 time_us; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + schedule_work(&chip->vbat_sync_work); +#endif rc = fg_get_battery_voltage(fg, &vbatt_mv); if (rc < 0) return IRQ_HANDLED; @@ -3435,6 +3661,20 @@ static irqreturn_t fg_vbatt_low_irq_handler(int irq, void *data) if (vbatt_mv < chip->dt.cutoff_volt_mv) { if (chip->dt.rapid_soc_dec_en) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* + * Set vbat_low debounce window to avoid shutdown in low temperature and high + * current scene, we set the counter to maxium 5, if fg_vbatt_low_irq trigger + * exceed 5 times, decrease soc to 0% very rapidly. + */ + fg->vbat_critical_low_count++; + if (fg->vbat_critical_low_count < EMPTY_DEBOUNCE_TIME_COUNT_MAX + && vbatt_mv > VBAT_CRITICAL_LOW_THR) { + if (batt_psy_initialized(fg)) + power_supply_changed(fg->batt_psy); + return IRQ_HANDLED; + } +#endif /* * Set this flag so that slope limiter coefficient * cannot be configured during rapid SOC decrease. @@ -3582,6 +3822,32 @@ static irqreturn_t fg_delta_bsoc_irq_handler(int irq, void *data) } #define CENTI_FULL_SOC 10000 + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static bool fg_is_input_suspend(struct fg_dev *fg) +{ + int rc = 0; + union power_supply_propval prop = {0, }; + int input_suspend = 0; + + if (fg->batt_psy) { + rc = power_supply_get_property(fg->batt_psy, + POWER_SUPPLY_PROP_INPUT_SUSPEND, + &prop); + if (rc < 0) { + pr_err("Error in getting input suspend property, rc=%d\n", rc); + return false; + } + input_suspend = prop.intval; + } + + if (input_suspend == 1) + return true; + else + return false; +} +#endif + static irqreturn_t fg_delta_msoc_irq_handler(int irq, void *data) { struct fg_dev *fg = data; @@ -3589,6 +3855,9 @@ static irqreturn_t fg_delta_msoc_irq_handler(int irq, void *data) int rc, batt_soc, batt_temp, msoc_raw; bool input_present = is_input_present(fg); u32 batt_soc_cp; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool input_suspend = false; +#endif rc = fg_get_msoc_raw(fg, &msoc_raw); if (!rc) @@ -3597,12 +3866,20 @@ static irqreturn_t fg_delta_msoc_irq_handler(int irq, void *data) get_batt_psy_props(fg); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + input_suspend = fg_is_input_suspend(fg); +#endif + rc = fg_get_sram_prop(fg, FG_SRAM_BATT_SOC, &batt_soc); if (rc < 0) pr_err("Failed to read battery soc rc: %d\n", rc); else cycle_count_update(chip->counter, (u32)batt_soc >> 24, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + fg->charge_status, fg->charge_done, (input_present & (!input_suspend))); +#else fg->charge_status, fg->charge_done, input_present); +#endif rc = fg_gen4_get_battery_temp(fg, &batt_temp); if (rc < 0) { @@ -4037,6 +4314,11 @@ static void pl_current_en_work(struct work_struct *work) return; vote(chip->parallel_current_en_votable, FG_PARALLEL_EN_VOTER, en, 0); + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* qcom patch to fix pm8150b ADC EOC bit not set issue */ + vote(chip->mem_attn_irq_en_votable, MEM_ATTN_IRQ_VOTER, false, 0); +#endif } static void pl_enable_work(struct work_struct *work) @@ -4053,6 +4335,166 @@ static void pl_enable_work(struct work_struct *work) vote(fg->awake_votable, ESR_FCC_VOTER, false, 0); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static void vbat_sync_work(struct work_struct *work) +{ + pr_err("sys_sync:vbat_sync_work\n"); + sys_sync(); +} + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int battery_authentic_period_ms = 1000; +#define BATTERY_AUTHENTIC_COUNT_MAX 5 +int retry_battery_authentic_result; +static void battery_authentic_work(struct work_struct *work) +{ + int rc; + //int count = 0; + union power_supply_propval pval = {0,}; + + struct fg_gen4_chip *chip = container_of(work, + struct fg_gen4_chip, + battery_authentic_work.work); + struct fg_dev *fg = &chip->fg; + + rc = power_supply_get_property(fg->fg_psy, + POWER_SUPPLY_PROP_AUTHENTIC, &pval); + if (pval.intval != true) { + retry_battery_authentic_result++; + if (retry_battery_authentic_result < BATTERY_AUTHENTIC_COUNT_MAX) { + pr_err("battery authentic work begin to restart.\n"); + schedule_delayed_work(&chip->battery_authentic_work, + msecs_to_jiffies(battery_authentic_period_ms)); + } + + if (retry_battery_authentic_result == BATTERY_AUTHENTIC_COUNT_MAX) { + pr_err("FG: authentic prop is %d\n", pval.intval); + } + } else { + pr_err("FG: authentic prop is %d\n", pval.intval); + schedule_delayed_work(&chip->ds_romid_work, + msecs_to_jiffies(0)); + schedule_delayed_work(&chip->ds_status_work, + msecs_to_jiffies(500)); + schedule_delayed_work(&chip->ds_page0_work, + msecs_to_jiffies(1000)); + } +} + +static int ds_romid_period_ms = 1000; +int retry_ds_romid; +#define DS_ROMID_COUNT_MAX 5 +static void ds_romid_work(struct work_struct *work) +{ + int rc; + //int count = 0; + union power_supply_propval pval = {0,}; + + struct fg_gen4_chip *chip = container_of(work, + struct fg_gen4_chip, + ds_romid_work.work); + struct fg_dev *fg = &chip->fg; + + rc = power_supply_get_property(fg->fg_psy, + POWER_SUPPLY_PROP_ROMID, &pval); + if (rc < 0) { + retry_ds_romid++; + if (retry_ds_romid < DS_ROMID_COUNT_MAX) { + pr_err("battery authentic work begin to restart.\n"); + schedule_delayed_work(&chip->ds_romid_work, + msecs_to_jiffies(ds_romid_period_ms)); + } + + if (retry_ds_romid == DS_ROMID_COUNT_MAX) { + pr_err("FG: romid prop is %02x %02x %02x %02x %02x %02x %02x %02x\n", + pval.arrayval[0], pval.arrayval[1], pval.arrayval[2], pval.arrayval[3], + pval.arrayval[4], pval.arrayval[5], pval.arrayval[6], pval.arrayval[7]); + } + } else { + pr_err("FG: romid prop is %02x %02x %02x %02x %02x %02x %02x %02x\n", + pval.arrayval[0], pval.arrayval[1], pval.arrayval[2], pval.arrayval[3], + pval.arrayval[4], pval.arrayval[5], pval.arrayval[6], pval.arrayval[7]); + } +} + +static int ds_status_period_ms = 1000; +#define DS_STATUS_COUNT_MAX 5 +int retry_ds_status; +static void ds_status_work(struct work_struct *work) +{ + int rc; + //int count = 0; + union power_supply_propval pval = {0,}; + + struct fg_gen4_chip *chip = container_of(work, + struct fg_gen4_chip, + ds_status_work.work); + struct fg_dev *fg = &chip->fg; + + rc = power_supply_get_property(fg->fg_psy, + POWER_SUPPLY_PROP_DS_STATUS, &pval); + if (rc < 0) { + retry_ds_status++; + if (retry_ds_status < DS_STATUS_COUNT_MAX) { + pr_err("battery authentic work begin to restart.\n"); + schedule_delayed_work(&chip->ds_status_work, + msecs_to_jiffies(ds_status_period_ms)); + } + + if (retry_ds_status == DS_STATUS_COUNT_MAX) { + pr_err("FG: ds_status prop is %02x %02x %02x %02x %02x %02x %02x %02x\n", + pval.arrayval[0], pval.arrayval[1], pval.arrayval[2], pval.arrayval[3], + pval.arrayval[4], pval.arrayval[5], pval.arrayval[6], pval.arrayval[7]); + } + } else { + pr_err("FG: ds_status prop is %02x %02x %02x %02x %02x %02x %02x %02x\n", + pval.arrayval[0], pval.arrayval[1], pval.arrayval[2], pval.arrayval[3], + pval.arrayval[4], pval.arrayval[5], pval.arrayval[6], pval.arrayval[7]); + } +} + +static int ds_page0_period_ms = 1000; +#define DS_PAGE0_COUNT_MAX 5 +int retry_ds_page0; +static void ds_page0_work(struct work_struct *work) +{ + int rc; + //int count = 0; + union power_supply_propval pval = {0,}; + + struct fg_gen4_chip *chip = container_of(work, + struct fg_gen4_chip, + ds_page0_work.work); + struct fg_dev *fg = &chip->fg; + + rc = power_supply_get_property(fg->fg_psy, + POWER_SUPPLY_PROP_PAGE0_DATA, &pval); + if (rc < 0) { + retry_ds_page0++; + if (retry_ds_page0 < DS_PAGE0_COUNT_MAX) { + pr_err("battery authentic work begin to restart.\n"); + schedule_delayed_work(&chip->ds_page0_work, + msecs_to_jiffies(ds_page0_period_ms)); + } + + if (retry_ds_page0 == DS_PAGE0_COUNT_MAX) { + pr_err("FG: ds_page0 prop is %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + pval.arrayval[0], pval.arrayval[1], pval.arrayval[2], pval.arrayval[3], + pval.arrayval[4], pval.arrayval[5], pval.arrayval[6], pval.arrayval[7], + pval.arrayval[8], pval.arrayval[9], pval.arrayval[10], pval.arrayval[11], + pval.arrayval[12], pval.arrayval[13], pval.arrayval[14], pval.arrayval[15]); + } + } else { + pr_err("FG: ds_page0 prop is %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + pval.arrayval[0], pval.arrayval[1], pval.arrayval[2], pval.arrayval[3], + pval.arrayval[4], pval.arrayval[5], pval.arrayval[6], pval.arrayval[7], + pval.arrayval[8], pval.arrayval[9], pval.arrayval[10], pval.arrayval[11], + pval.arrayval[12], pval.arrayval[13], pval.arrayval[14], pval.arrayval[15]); + } +} +#endif +#endif + static void status_change_work(struct work_struct *work) { struct fg_dev *fg = container_of(work, @@ -4061,6 +4503,10 @@ static void status_change_work(struct work_struct *work) int rc, batt_soc, batt_temp; bool input_present, qnovo_en; u32 batt_soc_cp; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int msoc_raw; + bool input_suspend = false; +#endif if (fg->battery_missing) { pm_relax(fg->dev); @@ -4085,6 +4531,18 @@ static void status_change_work(struct work_struct *work) get_batt_psy_props(fg); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (fg->charge_done && !fg->report_full) { + fg->report_full = true; + } else if (!fg->charge_done && fg->report_full) { + rc = fg_get_msoc_raw(fg, &msoc_raw); + if (rc < 0) + pr_err("Error in getting msoc, rc=%d\n", rc); + if (msoc_raw < FULL_SOC_REPORT_THR - 4) + fg->report_full = false; + } +#endif + rc = fg_get_sram_prop(fg, FG_SRAM_BATT_SOC, &batt_soc); if (rc < 0) { pr_err("Failed to read battery soc rc: %d\n", rc); @@ -4098,9 +4556,17 @@ static void status_change_work(struct work_struct *work) } input_present = is_input_present(fg); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + fg->input_present = input_present; + input_suspend = fg_is_input_suspend(fg); +#endif qnovo_en = is_qnovo_en(fg); cycle_count_update(chip->counter, (u32)batt_soc >> 24, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + fg->charge_status, fg->charge_done, (input_present & (!input_suspend))); +#else fg->charge_status, fg->charge_done, input_present); +#endif batt_soc_cp = div64_u64((u64)(u32)batt_soc * CENTI_FULL_SOC, BATT_SOC_32BIT); @@ -4148,6 +4614,69 @@ static void status_change_work(struct work_struct *work) pm_relax(fg->dev); } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define NORMAL_VOLTAGE_UV_THR 3700000 +static int fg_get_cold_thermal_level(struct fg_dev *fg) +{ + union power_supply_propval pval = {0, }; + int curr_ua, i, rc, temp, volt, status; + + if (!fg) + return -EINVAL; + + if (!fg->cold_thermal_len) + return 1; + + if (!fg->batt_psy) { + fg->batt_psy = power_supply_get_by_name("battery"); + if (!fg->batt_psy) { + return 1; + } + } + + rc = power_supply_get_property(fg->batt_psy, + POWER_SUPPLY_PROP_STATUS, &pval); + if (rc < 0) { + pr_err("failed get batt staus\n"); + return -EINVAL; + } + status = pval.intval; + + rc = fg_get_battery_voltage(fg, &volt); + if (rc < 0) + pr_err("failed to get voltage, rc=%d\n", rc); + + rc = fg_gen4_get_battery_temp(fg, &temp); + if (rc < 0) + pr_err("Error in getting batt_temp, rc=%d\n", rc); + + if (status == POWER_SUPPLY_STATUS_CHARGING || + !fg->batt_temp_low || volt > NORMAL_VOLTAGE_UV_THR) + return 1; + + rc = fg_get_battery_current(fg, &curr_ua); + if (rc < 0) + pr_err("failded to get battery current, rc=%d\n", rc); + + pr_err("volt: %d, temp: %d, curr_ua: %d\n", + volt, temp, curr_ua); + + for (i = 0; i < fg->cold_thermal_len; i++) { + if (temp > fg->cold_thermal_seq[i].temp_l && + temp <= fg->cold_thermal_seq[i].temp_h && + curr_ua > fg->cold_thermal_seq[i].curr_th) { + pr_err("cold thermal trigger status:%d, temp:%d, volt:%d\n", + status, temp, volt); + pr_err("curr_ua:%d, fg->cold_thermal_seq[i].index:%d\n", curr_ua, + fg->cold_thermal_seq[i].index); + return (fg->cold_thermal_seq[i].index + 1); + } + } + + return 1; +} +#endif + static void sram_dump_work(struct work_struct *work) { struct fg_dev *fg = container_of(work, struct fg_dev, @@ -4321,7 +4850,121 @@ static struct kernel_param_ops fg_esr_cal_ops = { module_param_cb(esr_fast_cal_en, &fg_esr_cal_ops, &fg_esr_fast_cal_en, 0644); /* All power supply functions here */ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int fg_gen4_set_vbatt_full_vol(struct fg_dev *fg, bool enable_ffc) +{ + int rc; + int volt; + if (enable_ffc) + volt = fg->bp.ffc_vbatt_full_mv; + else + volt = fg->bp.vbatt_full_mv; + if (volt < 0) + return rc; + rc = fg_set_constant_chg_voltage(fg, volt * 1000); + if (rc < 0) { + pr_err("Error in constant chg vol rc=%d\n", rc); + return rc; + } + fg->bp.float_volt_uv = volt * 1000 + 10000; + fg_dbg(fg, FG_STATUS, "set cc-cv volt:%d float_volt_uv:%d\n", volt, fg->bp.float_volt_uv); + return rc; +} +static int fg_gen4_set_sys_termi_curr(struct fg_dev *fg, bool enable_ffc) +{ + struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg); + u8 buf[4]; + int rc; + int curr; + if (enable_ffc) + curr = chip->dt.ffc_sys_term_curr_ma; + else + curr = chip->dt.sys_term_curr_ma; + if (chip->dt.ffc_sys_term_curr_ma == -EINVAL) + return 0; + fg_encode(fg->sp, FG_SRAM_SYS_TERM_CURR, curr, buf); + rc = fg_sram_write(fg, fg->sp[FG_SRAM_SYS_TERM_CURR].addr_word, + fg->sp[FG_SRAM_SYS_TERM_CURR].addr_byte, buf, + fg->sp[FG_SRAM_SYS_TERM_CURR].len, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing sys_term_curr, rc=%d\n", rc); + return rc; + } + fg_dbg(fg, FG_STATUS, "set sys termi curr:%d\n", curr); + return rc; +} +static int fg_gen4_set_ki_coeff_curr(struct fg_dev *fg, bool enable_ffc) +{ + struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg); + u8 val; + int rc; + int lo_med_curr, med_hi_curr; + if (enable_ffc) { + lo_med_curr = chip->dt.ffc_ki_coeff_lo_med_chg_thr_ma; + med_hi_curr = chip->dt.ffc_ki_coeff_med_hi_chg_thr_ma; + } else { + lo_med_curr = chip->dt.ki_coeff_lo_med_chg_thr_ma; + med_hi_curr = chip->dt.ki_coeff_med_hi_chg_thr_ma; + } + pr_err("enable_ffc:%d, low_med_curr:%d, med_hi_curr:%d\n", enable_ffc, lo_med_curr, med_hi_curr); + if (lo_med_curr == -EINVAL || med_hi_curr == -EINVAL) + return 0; + fg_encode(fg->sp, FG_SRAM_KI_COEFF_LO_MED_CHG_THR, + lo_med_curr, &val); + rc = fg_sram_write(fg, + fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].addr_word, + fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].addr_byte, + &val, fg->sp[FG_SRAM_KI_COEFF_LO_MED_CHG_THR].len, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing ki_coeff_lo_med_chg_thr_ma, rc=%d\n", + rc); + return rc; + } + fg_encode(fg->sp, FG_SRAM_KI_COEFF_MED_HI_CHG_THR, + med_hi_curr, &val); + rc = fg_sram_write(fg, + fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].addr_word, + fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].addr_byte, &val, + fg->sp[FG_SRAM_KI_COEFF_MED_HI_CHG_THR].len, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing ki_coeff_med_hi_chg_thr_ma, rc=%d\n", + rc); + return rc; + } + pr_err("==test lo_med_curr:%d, med_hi_curr:%d\n", lo_med_curr, med_hi_curr); + return rc; +} +static int fg_get_ffc_iterm_for_chg(struct fg_dev *fg) +{ + int rc = 0, batt_temp = 0, ffc_chg_iterm = 0; + rc = fg_gen4_get_battery_temp(fg, &batt_temp); + if (rc < 0){ + pr_err("Failed to get battery-temp, rc = %d\n", rc); + return -DEFAULT_FFC_TERM_CURRENT; + } + if (batt_temp < 350) + ffc_chg_iterm = fg->bp.ffc_low_temp_term_curr_ma; + else + ffc_chg_iterm = fg->bp.ffc_high_temp_term_curr_ma; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (ffc_chg_iterm == 0) { + if (batt_temp < 350) + ffc_chg_iterm = -1278; + else + ffc_chg_iterm = -1363; + } +#endif + + return ffc_chg_iterm; +} +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define SHUTDOWN_DELAY_VOL 3300 +#endif static int fg_psy_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *pval) @@ -4330,10 +4973,187 @@ static int fg_psy_get_property(struct power_supply *psy, struct fg_dev *fg = &chip->fg; int rc = 0, val; int64_t temp; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int vbatt_uv; + static bool shutdown_delay_cancel; + static bool last_shutdown_delay; +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + union power_supply_propval b_val = {0,}; + + if (fg->max_verify_psy == NULL) { + fg->max_verify_psy = power_supply_get_by_name("batt_verify"); + if (fg->max_verify_psy == NULL) { + pr_err("max_verify_psy is NULL\n"); + } + } + +#ifdef CONFIG_MACH_XIAOMI_NABU + if (fg->max_verify_slave_psy == NULL) { + fg->max_verify_slave_psy = power_supply_get_by_name("batt_verify_slave"); + if (fg->max_verify_slave_psy == NULL) { + pr_err("max_verify_slave_psy is NULL\n"); + } + } +#endif +#endif switch (psp) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_AUTHENTIC: + if (fg->fake_authentic != -EINVAL) { + pval->intval = fg->fake_authentic; + break; + } + + if (fg->max_verify_psy == NULL) + return -ENODATA; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (fg->max_verify_slave_psy == NULL) + return -ENODATA; +#endif + + rc = power_supply_get_property(fg->max_verify_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, &b_val); + chip->battery_authentic_result = b_val.intval; +#ifdef CONFIG_MACH_XIAOMI_NABU + rc = power_supply_get_property(fg->max_verify_slave_psy, + POWER_SUPPLY_PROP_AUTHEN_RESULT, &b_val); + chip->battery_authentic_slave_result = b_val.intval; +#endif + if (chip->battery_authentic_result == 1 +#ifdef CONFIG_MACH_XIAOMI_NABU + && chip->battery_authentic_slave_result == 1 +#endif + ) { + pval->intval = 1; + } else { + pval->intval = 0; + } + break; + case POWER_SUPPLY_PROP_ROMID: + if (fg->max_verify_psy == NULL) + return -ENODATA; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (fg->max_verify_slave_psy == NULL) + return -ENODATA; +#endif + + rc = power_supply_get_property(fg->max_verify_psy, + POWER_SUPPLY_PROP_ROMID, &b_val); + memcpy(pval->arrayval, b_val.arrayval, 8); + memcpy(chip->ds_romid, b_val.arrayval, 8); + +#ifdef CONFIG_MACH_XIAOMI_NABU + rc = power_supply_get_property(fg->max_verify_slave_psy, + POWER_SUPPLY_PROP_ROMID, &b_val); + memcpy(chip->ds_slave_romid, b_val.arrayval, 8); +#endif + + break; + case POWER_SUPPLY_PROP_CHIP_OK: + if (fg->fake_chip_ok != -EINVAL) { + pval->intval = fg->fake_chip_ok; + break; + } + if (fg->max_verify_psy == NULL) + return -ENODATA; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (fg->max_verify_slave_psy == NULL) + return -ENODATA; +#endif + + rc = power_supply_get_property(fg->max_verify_psy, + POWER_SUPPLY_PROP_CHIP_OK, &b_val); +#ifdef CONFIG_MACH_XIAOMI_NABU + chip->battery_chip_ok = b_val.intval; +#endif + pval->intval = b_val.intval; +#ifdef CONFIG_MACH_XIAOMI_NABU + rc = power_supply_get_property(fg->max_verify_slave_psy, + POWER_SUPPLY_PROP_CHIP_OK, &b_val); + chip->battery_chip_slave_ok = b_val.intval; + if (chip->battery_chip_ok == 1 && chip->battery_chip_slave_ok == 1) { + pval->intval = 1; + } else { + pval->intval = 0; + } +#endif + break; + case POWER_SUPPLY_PROP_DS_STATUS: + if (fg->max_verify_psy == NULL) + return -ENODATA; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (fg->max_verify_slave_psy == NULL) + return -ENODATA; +#endif + + rc = power_supply_get_property(fg->max_verify_psy, + POWER_SUPPLY_PROP_DS_STATUS, &b_val); + memcpy(pval->arrayval, b_val.arrayval, 8); + memcpy(chip->ds_status, b_val.arrayval, 8); +#ifdef CONFIG_MACH_XIAOMI_NABU + rc = power_supply_get_property(fg->max_verify_slave_psy, + POWER_SUPPLY_PROP_DS_STATUS, &b_val); + memcpy(chip->ds_slave_status, b_val.arrayval, 8); +#endif + break; + case POWER_SUPPLY_PROP_PAGE0_DATA: + if (fg->max_verify_psy == NULL) + return -ENODATA; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (fg->max_verify_slave_psy == NULL) + return -ENODATA; +#endif + + rc = power_supply_get_property(fg->max_verify_psy, + POWER_SUPPLY_PROP_PAGE0_DATA, &b_val); + memcpy(pval->arrayval, b_val.arrayval, 16); + memcpy(chip->ds_page0, b_val.arrayval, 16); +#ifdef CONFIG_MACH_XIAOMI_NABU + rc = power_supply_get_property(fg->max_verify_slave_psy, + POWER_SUPPLY_PROP_PAGE0_DATA, &b_val); + memcpy(chip->ds_slave_page0, b_val.arrayval, 16); +#endif + break; +#endif case POWER_SUPPLY_PROP_CAPACITY: rc = fg_gen4_get_prop_capacity(fg, &pval->intval); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + //Using smooth battery capacity. + if (fg->param.batt_soc >= 0 && !chip->rapid_soc_dec_en) + pval->intval = fg->param.batt_soc; + //shutdown delay feature + if (chip->dt.shutdown_delay_enable) { + if (pval->intval == 0) { + rc = fg_get_battery_voltage(fg, &vbatt_uv); + if (vbatt_uv/1000 > SHUTDOWN_DELAY_VOL + && fg->charge_status != POWER_SUPPLY_STATUS_CHARGING) { + fg->shutdown_delay = true; + pval->intval = 1; + } else if (fg->charge_status == POWER_SUPPLY_STATUS_CHARGING + && fg->shutdown_delay) { + fg->shutdown_delay = false; + shutdown_delay_cancel = true; + pval->intval = 1; + } else { + fg->shutdown_delay = false; + if (shutdown_delay_cancel) + pval->intval = 1; + } + } else { + fg->shutdown_delay = false; + shutdown_delay_cancel = false; + } + + if (last_shutdown_delay != fg->shutdown_delay) { + last_shutdown_delay = fg->shutdown_delay; + if (fg->fg_psy) + power_supply_changed(fg->fg_psy); + } + } +#endif break; case POWER_SUPPLY_PROP_REAL_CAPACITY: rc = fg_gen4_get_prop_real_capacity(fg, &pval->intval); @@ -4341,6 +5161,17 @@ static int fg_psy_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CAPACITY_RAW: rc = fg_gen4_get_prop_capacity_raw(chip, &pval->intval); break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_SHUTDOWN_DELAY: + pval->intval = fg->shutdown_delay; + break; + case POWER_SUPPLY_PROP_SOC_DECIMAL: + rc = fg_gen4_get_prop_soc_decimal(chip, &pval->intval); + break; + case POWER_SUPPLY_PROP_SOC_DECIMAL_RATE: + rc = fg_gen4_get_prop_soc_decimal_rate(chip, &pval->intval); + break; +#endif case POWER_SUPPLY_PROP_CC_SOC: rc = fg_get_sram_prop(&chip->fg, FG_SRAM_CC_SOC, &val); if (rc < 0) { @@ -4401,9 +5232,17 @@ static int fg_psy_get_property(struct power_supply *psy, pval->intval = (int)temp; break; case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (-EINVAL != fg->bp.nom_cap_uah) { + pval->intval = fg->bp.nom_cap_uah * 1000; + } else { +#endif rc = fg_gen4_get_nominal_capacity(chip, &temp); if (!rc) pval->intval = (int)temp; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } +#endif break; case POWER_SUPPLY_PROP_CHARGE_COUNTER: rc = fg_gen4_get_charge_counter(chip, &pval->intval); @@ -4457,6 +5296,15 @@ static int fg_psy_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CC_STEP_SEL: pval->intval = chip->ttf->cc_step.sel; break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_COLD_THERMAL_LEVEL: + if(chip->cold_thermal_support) { + pval->intval = fg_get_cold_thermal_level(fg); + if (pval->intval < fg->curr_cold_thermal_level) + pval->intval = fg->curr_cold_thermal_level; + } + break; +#endif case POWER_SUPPLY_PROP_BATT_AGE_LEVEL: pval->intval = chip->batt_age_level; break; @@ -4472,6 +5320,29 @@ static int fg_psy_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CALIBRATE: pval->intval = chip->calib_level; break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + pval->intval = chip->fastcharge_mode_enabled; + break; + case POWER_SUPPLY_PROP_FFC_TERMINATION_CURRENT: + pval->intval = fg_get_ffc_iterm_for_chg(fg); + break; + case POWER_SUPPLY_PROP_SYS_TERMINATION_CURRENT: + pval->intval = chip->dt.sys_term_curr_ma; + break; + case POWER_SUPPLY_PROP_FFC_SYS_TERMINATION_CURRENT: + pval->intval = chip->dt.ffc_sys_term_curr_ma; + break; + case POWER_SUPPLY_PROP_VBATT_FULL_VOL: + pval->intval = fg->bp.vbatt_full_mv; + break; + case POWER_SUPPLY_PROP_FFC_VBATT_FULL_VOL: + pval->intval = fg->bp.ffc_vbatt_full_mv; + break; + case POWER_SUPPLY_PROP_KI_COEFF_CURRENT: + pval->intval = chip->dt.ffc_ki_coeff_med_hi_chg_thr_ma; + break; +#endif default: pr_err("unsupported property %d\n", psp); rc = -EINVAL; @@ -4540,6 +5411,12 @@ static int fg_psy_set_property(struct power_supply *psy, if (chip->sp) soh_profile_update(chip->sp, chip->soh); break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_CYCLE_COUNT: + rc = set_cycle_count(chip->counter, pval->intval); + pr_info("Cycle count is modified to %d by userspace\n", pval->intval); + break; +#endif case POWER_SUPPLY_PROP_CLEAR_SOH: if (chip->first_profile_load && !pval->intval) { fg_dbg(fg, FG_STATUS, "Clearing first profile load bit\n"); @@ -4563,9 +5440,53 @@ static int fg_psy_set_property(struct power_supply *psy, chip->batt_age_level = pval->intval; schedule_delayed_work(&fg->profile_load_work, 0); break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: + if (fg->vbatt_full_volt_uv != pval->intval) + rc = fg_set_constant_chg_voltage(fg, pval->intval); + fg->vbatt_full_volt_uv = pval->intval; + break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_COLD_THERMAL_LEVEL: + if (chip->cold_thermal_support) { + fg->curr_cold_thermal_level = pval->intval; + if (fg->curr_cold_thermal_level > 3) + fg->curr_cold_thermal_level = 3; + else if (fg->curr_cold_thermal_level < 1) + fg->curr_cold_thermal_level = 1; + } + break; +#endif +#endif case POWER_SUPPLY_PROP_CALIBRATE: rc = fg_gen4_set_calibrate_level(chip, pval->intval); break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + chip->fastcharge_mode_enabled = pval->intval; + break; + case POWER_SUPPLY_PROP_SYS_TERMINATION_CURRENT: + rc = fg_gen4_set_sys_termi_curr(fg, pval->intval); + break; + case POWER_SUPPLY_PROP_VBATT_FULL_VOL: + rc = fg_gen4_set_vbatt_full_vol(fg, pval->intval); + break; + case POWER_SUPPLY_PROP_KI_COEFF_CURRENT: + rc = fg_gen4_set_ki_coeff_curr(fg, pval->intval); + break; + case POWER_SUPPLY_PROP_SHUTDOWN_DELAY_ENABLE: + chip->dt.shutdown_delay_enable = pval->intval; + break; + case POWER_SUPPLY_PROP_AUTHENTIC: + fg->fake_authentic = !!pval->intval; + break; + case POWER_SUPPLY_PROP_CHIP_OK: + fg->fake_chip_ok = !!pval->intval; + break; + case POWER_SUPPLY_PROP_TEMP: + fg->batt_fake_temp = pval->intval; + break; +#endif default: break; } @@ -4583,9 +5504,27 @@ static int fg_property_is_writeable(struct power_supply *psy, case POWER_SUPPLY_PROP_ESR_ACTUAL: case POWER_SUPPLY_PROP_ESR_NOMINAL: case POWER_SUPPLY_PROP_SOH: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_CYCLE_COUNT: +#endif case POWER_SUPPLY_PROP_CLEAR_SOH: case POWER_SUPPLY_PROP_BATT_AGE_LEVEL: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_COLD_THERMAL_LEVEL: +#endif +#endif case POWER_SUPPLY_PROP_CALIBRATE: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + case POWER_SUPPLY_PROP_SYS_TERMINATION_CURRENT: + case POWER_SUPPLY_PROP_VBATT_FULL_VOL: + case POWER_SUPPLY_PROP_KI_COEFF_CURRENT: + case POWER_SUPPLY_PROP_AUTHENTIC: + case POWER_SUPPLY_PROP_CHIP_OK: + case POWER_SUPPLY_PROP_TEMP: +#endif return 1; default: break; @@ -4595,8 +5534,20 @@ static int fg_property_is_writeable(struct power_supply *psy, } static enum power_supply_property fg_psy_props[] = { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_AUTHENTIC, + POWER_SUPPLY_PROP_ROMID, + POWER_SUPPLY_PROP_DS_STATUS, + POWER_SUPPLY_PROP_PAGE0_DATA, + POWER_SUPPLY_PROP_CHIP_OK, +#endif POWER_SUPPLY_PROP_CAPACITY, POWER_SUPPLY_PROP_REAL_CAPACITY, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_SHUTDOWN_DELAY, + POWER_SUPPLY_PROP_SOC_DECIMAL, + POWER_SUPPLY_PROP_SOC_DECIMAL_RATE, +#endif POWER_SUPPLY_PROP_CAPACITY_RAW, POWER_SUPPLY_PROP_CC_SOC, POWER_SUPPLY_PROP_TEMP, @@ -4617,6 +5568,9 @@ static enum power_supply_property fg_psy_props[] = { POWER_SUPPLY_PROP_CHARGE_FULL, POWER_SUPPLY_PROP_CHARGE_COUNTER, POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_CYCLE_COUNT, +#endif POWER_SUPPLY_PROP_CYCLE_COUNTS, POWER_SUPPLY_PROP_SOC_REPORTING_READY, POWER_SUPPLY_PROP_CLEAR_SOH, @@ -4628,11 +5582,23 @@ static enum power_supply_property fg_psy_props[] = { POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG, POWER_SUPPLY_PROP_CC_STEP, POWER_SUPPLY_PROP_CC_STEP_SEL, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_COLD_THERMAL_LEVEL, +#endif POWER_SUPPLY_PROP_BATT_AGE_LEVEL, POWER_SUPPLY_PROP_POWER_NOW, POWER_SUPPLY_PROP_POWER_AVG, POWER_SUPPLY_PROP_SCALE_MODE_EN, POWER_SUPPLY_PROP_CALIBRATE, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_FASTCHARGE_MODE, + POWER_SUPPLY_PROP_FFC_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_SYS_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_FFC_SYS_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_VBATT_FULL_VOL, + POWER_SUPPLY_PROP_FFC_VBATT_FULL_VOL, + POWER_SUPPLY_PROP_KI_COEFF_CURRENT, +#endif }; static const struct power_supply_desc fg_psy_desc = { @@ -4739,7 +5705,9 @@ static int fg_parallel_current_en_cb(struct votable *votable, void *data, struct fg_dev *fg = data; struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg); int rc; +#if !defined(CONFIG_MACH_XIAOMI_VAYU) && !defined(CONFIG_MACH_XIAOMI_NABU) u8 val, mask; +#endif vote(chip->mem_attn_irq_en_votable, MEM_ATTN_IRQ_VOTER, true, 0); @@ -4748,6 +5716,7 @@ static int fg_parallel_current_en_cb(struct votable *votable, void *data, if (rc < 0) return rc; +#if !defined(CONFIG_MACH_XIAOMI_VAYU) && !defined(CONFIG_MACH_XIAOMI_NABU) val = enable ? SMB_MEASURE_EN_BIT : 0; mask = SMB_MEASURE_EN_BIT; rc = fg_masked_write(fg, BATT_INFO_FG_CNV_CHAR_CFG(fg), mask, val); @@ -4757,6 +5726,7 @@ static int fg_parallel_current_en_cb(struct votable *votable, void *data, vote(chip->mem_attn_irq_en_votable, MEM_ATTN_IRQ_VOTER, false, 0); fg_dbg(fg, FG_STATUS, "Parallel current summing: %d\n", enable); +#endif return rc; } @@ -5433,6 +6403,16 @@ static int fg_parse_ki_coefficients(struct fg_dev *fg) of_property_read_u32(node, "qcom,ki-coeff-chg-med-hi-thresh-ma", &chip->dt.ki_coeff_med_hi_chg_thr_ma); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chip->dt.ffc_ki_coeff_lo_med_chg_thr_ma = -EINVAL; + of_property_read_u32(node, "qcom,ffc-ki-coeff-chg-low-med-thresh-ma", + &chip->dt.ffc_ki_coeff_lo_med_chg_thr_ma); + + chip->dt.ffc_ki_coeff_med_hi_chg_thr_ma = -EINVAL; + of_property_read_u32(node, "qcom,ffc-ki-coeff-chg-med-hi-thresh-ma", + &chip->dt.ffc_ki_coeff_med_hi_chg_thr_ma); +#endif + chip->dt.ki_coeff_lo_med_dchg_thr_ma = 50; of_property_read_u32(node, "qcom,ki-coeff-dischg-low-med-thresh-ma", &chip->dt.ki_coeff_lo_med_dchg_thr_ma); @@ -5605,6 +6585,9 @@ static int fg_gen4_parse_nvmem_dt(struct fg_gen4_chip *chip) #define DEFAULT_EMPTY_VOLT_MV 2812 #define DEFAULT_SYS_MIN_VOLT_MV 2800 #define DEFAULT_SYS_TERM_CURR_MA -125 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define DEFAULT_FFC_SYS_TERM_CURR_MA -1125 +#endif #define DEFAULT_CUTOFF_CURR_MA 200 #define DEFAULT_DELTA_SOC_THR 5 /* 0.5 % */ #define DEFAULT_CL_START_SOC 15 @@ -5616,7 +6599,11 @@ static int fg_gen4_parse_nvmem_dt(struct fg_gen4_chip *chip) #define DEFAULT_CL_MAX_LIM_DECIPERC 0 #define DEFAULT_CL_DELTA_BATT_SOC 10 #define BTEMP_DELTA_LOW 0 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define BTEMP_DELTA_HIGH 10 +#else #define BTEMP_DELTA_HIGH 3 +#endif #define DEFAULT_ESR_PULSE_THRESH_MA 47 #define DEFAULT_ESR_MEAS_CURR_MA 120 #define DEFAULT_SCALE_VBATT_THR_MV 3400 @@ -5628,6 +6615,9 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) u32 base, temp; u8 subtype; int rc; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int size; +#endif if (!node) { dev_err(fg->dev, "device tree node missing\n"); @@ -5750,6 +6740,14 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) else chip->dt.sys_term_curr_ma = temp; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = of_property_read_u32(node, "qcom,fg-ffc-sys-term-current", &temp); + if (rc < 0) + chip->dt.ffc_sys_term_curr_ma = DEFAULT_FFC_SYS_TERM_CURR_MA; + else + chip->dt.ffc_sys_term_curr_ma = temp; +#endif + rc = of_property_read_u32(node, "qcom,fg-delta-soc-thr", &temp); if (rc < 0) chip->dt.delta_soc_thr = DEFAULT_DELTA_SOC_THR; @@ -5762,6 +6760,29 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) return -EINVAL; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + size = 0; + of_get_property(node, "qcom,soc_decimal_rate", &size); + if (size) { + chip->dt.dec_rate_seq = devm_kzalloc(fg->dev, + size, GFP_KERNEL); + if (chip->dt.dec_rate_seq) { + chip->dt.dec_rate_len = + (size / sizeof(*chip->dt.dec_rate_seq)); + if (chip->dt.dec_rate_len % 2) { + pr_err("invalid soc decimal rate seq\n"); + return -EINVAL; + } + of_property_read_u32_array(node, + "qcom,soc_decimal_rate", + chip->dt.dec_rate_seq, + chip->dt.dec_rate_len); + } else { + pr_err("error allocating memory for dec_rate_seq\n"); + } + } +#endif + chip->dt.esr_timer_chg_fast[TIMER_RETRY] = -EINVAL; chip->dt.esr_timer_chg_fast[TIMER_MAX] = -EINVAL; rc = fg_parse_dt_property_u32_array(node, "qcom,fg-esr-timer-chg-fast", @@ -5795,6 +6816,11 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) chip->dt.force_load_profile = of_property_read_bool(node, "qcom,fg-force-load-profile"); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chip->dt.shutdown_delay_enable = of_property_read_bool(node, + "qcom,shutdown-delay-enable"); +#endif + rc = of_property_read_u32(node, "qcom,cl-start-capacity", &temp); if (rc < 0) chip->cl->dt.max_start_soc = DEFAULT_CL_START_SOC; @@ -5947,9 +6973,350 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) chip->dt.sys_min_volt_mv = DEFAULT_SYS_MIN_VOLT_MV; of_property_read_u32(node, "qcom,fg-sys-min-voltage", &chip->dt.sys_min_volt_mv); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chip->cold_thermal_support = of_property_read_bool(node, + "qcom,cold-thermal-support"); + + size = 0; + of_get_property(node, "mi,cold_thermal_seq", &size); + if (size) { + fg->cold_thermal_seq = devm_kzalloc(fg->dev, + size, GFP_KERNEL); + if (fg->cold_thermal_seq) { + fg->cold_thermal_len = + (size / sizeof(int)); + if (fg->cold_thermal_len % 4) { + pr_err("invalid cold thermal seq\n"); + return -EINVAL; + } + of_property_read_u32_array(node, + "mi,cold_thermal_seq", + (int *)fg->cold_thermal_seq, + fg->cold_thermal_len); + fg->cold_thermal_len = fg->cold_thermal_len / 4; + } else { + pr_err("error allocating memory for cold thermal seq\n"); + } + } +#endif + return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define SOC_WORK_MS 20000 +static void soc_work_fn(struct work_struct *work) +{ + struct fg_dev *fg = container_of(work, + struct fg_dev, soc_work.work); + struct fg_gen4_chip *chip = container_of(fg, + struct fg_gen4_chip, fg); + int msoc = 0, soc = 0, curr_ua = 0, volt_uv = 0, temp = 0; + int esr_uohms = 0; + int cycle_count; + int rc; + static int prev_soc = -EINVAL; + + rc = fg_gen4_get_prop_capacity(fg, &soc); + if (rc < 0) + pr_err("Error in getting capacity, rc=%d\n", rc); + + rc = fg_get_msoc_raw(fg, &msoc); + if (rc < 0) + pr_err("Error in getting msoc, rc=%d\n", rc); + + rc = fg_get_battery_resistance(fg, &esr_uohms); + if (rc < 0) + pr_err("Error in getting esr_uohms, rc=%d\n", rc); + + fg_get_battery_current(fg, &curr_ua); + if (rc < 0) + pr_err("failed to get current, rc=%d\n", rc); + + rc = fg_get_battery_voltage(fg, &volt_uv); + if (rc < 0) + pr_err("failed to get voltage, rc=%d\n", rc); + + rc = fg_gen4_get_battery_temp(fg, &temp); + if (rc < 0) + pr_err("Error in getting batt_temp, rc=%d\n", rc); + + rc = get_cycle_count(chip->counter, &cycle_count); + if (rc < 0) + pr_err("failed to get cycle count, rc=%d\n", rc); + + pr_info("adjust_soc: s %d r %d i %d v %d t %d cc %d m 0x%02x\n", + soc, + esr_uohms, + curr_ua/1000, + volt_uv/1000, + temp, + cycle_count, + msoc); + + if (temp < 450 && fg->last_batt_temp >= 450) { + /* follow the way that fg_notifier_cb use wake lock */ + pm_stay_awake(fg->dev); + schedule_work(&fg->status_change_work); + } + + fg->last_batt_temp = temp; + + /* if soc changes, report power supply changed uevent */ + if (soc != prev_soc) { + if (fg->batt_psy) + power_supply_changed(fg->batt_psy); + prev_soc = soc; + } + + schedule_delayed_work( + &fg->soc_work, + msecs_to_jiffies(SOC_WORK_MS)); +} + +static void empty_restart_fg_work(struct work_struct *work) +{ + struct fg_dev *fg = container_of(work, struct fg_dev, + empty_restart_fg_work.work); + union power_supply_propval prop = {0, }; + int usb_present = 0; + int rc; + + if (usb_psy_initialized(fg)) { + rc = power_supply_get_property(fg->usb_psy, + POWER_SUPPLY_PROP_PRESENT, &prop); + if (rc < 0) { + pr_err("Couldn't read usb present prop rc=%d\n", rc); + return; + } + usb_present = prop.intval; + } + + /* only when usb is absent, restart fg */ + if (!usb_present) { + if (fg->profile_load_status == PROFILE_LOADED) { + pr_info("soc empty after cold to warm, need to restart fg\n"); + fg->empty_restart_fg = true; + rc = fg_restart(fg, SOC_READY_WAIT_TIME_MS); + if (rc < 0) { + pr_err("Error in restarting FG, rc=%d\n", rc); + fg->empty_restart_fg = false; + return; + } + pr_info("FG restart done\n"); + if (batt_psy_initialized(fg)) + power_supply_changed(fg->batt_psy); + } else { + schedule_delayed_work( + &fg->empty_restart_fg_work, + msecs_to_jiffies(RESTART_FG_WORK_MS)); + } + } +} + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int calculate_delta_time(struct timespec *time_stamp, int *delta_time_s) +{ + struct timespec now_time; + + /* default to delta time = 0 if anything fails */ + *delta_time_s = 0; + + get_monotonic_boottime(&now_time); + *delta_time_s = (now_time.tv_sec - time_stamp->tv_sec); + + /* remember this time */ + *time_stamp = now_time; + return 0; // git +} // git + +static int calculate_average_current(struct fg_gen4_chip *chip) +{ + struct fg_dev *fg = &chip->fg; + int i; + int iavg_ma = fg->param.batt_ma; + + /* only continue if ibat has changed */ + if (fg->param.batt_ma == fg->param.batt_ma_prev) + goto unchanged; + else + fg->param.batt_ma_prev = fg->param.batt_ma; + + fg->param.batt_ma_avg_samples[fg->param.samples_index] = iavg_ma; + fg->param.samples_index = (fg->param.samples_index + 1) % BATT_MA_AVG_SAMPLES; + fg->param.samples_num++; + + if (fg->param.samples_num >= BATT_MA_AVG_SAMPLES) + fg->param.samples_num = BATT_MA_AVG_SAMPLES; + + if (fg->param.samples_num) { + iavg_ma = 0; + /* maintain a AVG_SAMPLES sample average of ibat */ + for (i = 0; i < fg->param.samples_num; i++) { + pr_debug("iavg_samples_ma[%d] = %d\n", i, fg->param.batt_ma_avg_samples[i]); + iavg_ma += fg->param.batt_ma_avg_samples[i]; + } + fg->param.batt_ma_avg = DIV_ROUND_CLOSEST(iavg_ma, fg->param.samples_num); + } + +unchanged: + pr_info("current_now_ma=%d averaged_iavg_ma=%d\n", + fg->param.batt_ma, fg->param.batt_ma_avg); + return fg->param.batt_ma_avg; +} + +static void fg_battery_soc_smooth_tracking(struct fg_gen4_chip *chip) +{ + struct fg_dev *fg = &chip->fg; + int delta_time = 0; + int soc_changed; + int last_batt_soc = fg->param.batt_soc; + int time_since_last_change_sec; + + struct timespec last_change_time = fg->param.last_soc_change_time; + + calculate_delta_time(&last_change_time, &time_since_last_change_sec); + + if (fg->param.batt_temp > 150) { + /* Battery in normal temperture */ + if (fg->param.batt_ma < 0 || + (abs(fg->param.batt_raw_soc - fg->param.batt_soc) > 2)) + delta_time = time_since_last_change_sec / 20; + else + delta_time = time_since_last_change_sec / 60; + } else { + /* Battery in low temperture */ + calculate_average_current(chip); + /* Calculated average current > 1000mA */ + if ((fg->param.batt_ma_avg > 1000000) || + (abs(fg->param.batt_raw_soc - fg->param.batt_soc) > 2)) + /* Heavy loading current, ignore battery soc limit*/ + delta_time = time_since_last_change_sec / 10; + else + delta_time = time_since_last_change_sec / 20; + } + + if (delta_time < 0) + delta_time = 0; + + soc_changed = min(1, delta_time); + + if (last_batt_soc >= 0) { + if (last_batt_soc != 100 + && fg->param.batt_raw_soc >= 95 + && fg->charge_status == POWER_SUPPLY_STATUS_FULL) + // Unlikely status + last_batt_soc = fg->param.update_now ? + 100 : last_batt_soc + soc_changed; + else if (last_batt_soc < fg->param.batt_raw_soc && + fg->param.batt_ma < 0) + /* Battery in charging status + * update the soc when resuming device + */ + last_batt_soc = fg->param.update_now ? + fg->param.batt_raw_soc : last_batt_soc + soc_changed; + else if (last_batt_soc > fg->param.batt_raw_soc +#ifdef CONFIG_MACH_XIAOMI_NABU + && fg->charge_status != POWER_SUPPLY_STATUS_FULL +#endif + && fg->param.batt_ma > 0) + /* Battery in discharging status + * update the soc when resuming device + */ + last_batt_soc = fg->param.update_now ? + fg->param.batt_raw_soc : last_batt_soc - soc_changed; + + fg->param.update_now = false; + } else { + last_batt_soc = fg->param.batt_raw_soc; + } + + if (fg->param.batt_soc != last_batt_soc) { + fg->param.batt_soc = last_batt_soc; + fg->param.last_soc_change_time = last_change_time; + if (batt_psy_initialized(fg)) + power_supply_changed(fg->batt_psy); + } + + pr_info("soc:%d, last_soc:%d, raw_soc:%d, soc_changed:%d.\n", + fg->param.batt_soc, last_batt_soc, + fg->param.batt_raw_soc, soc_changed); +} + +static int fg_dynamic_set_cutoff_voltage(struct fg_dev *fg, + int cut_off_mv) +{ + int rc; + u8 buf[4]; + + pr_err("set dynamic cutoff voltage to: %d\n", cut_off_mv); + + fg_encode(fg->sp, FG_SRAM_CUTOFF_VOLT, cut_off_mv, buf); + rc = fg_sram_write(fg, fg->sp[FG_SRAM_CUTOFF_VOLT].addr_word, + fg->sp[FG_SRAM_CUTOFF_VOLT].addr_byte, buf, + fg->sp[FG_SRAM_CUTOFF_VOLT].len, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing cutoff_volt, rc=%d\n", rc); + return rc; + } + + return rc; +} + +#define LOW_DISCHARGE_TEMP_TRH 150 +#define LOW_DISCHARGE_TEMP_HYS 20 +#define LOW_TEMP_CUTOFF_VOL_MV 3200 +#define MONITOR_SOC_WAIT_MS 1000 +#define MONITOR_SOC_WAIT_PER_MS 10000 +static void soc_monitor_work(struct work_struct *work) +{ + int rc; + struct fg_dev *fg = container_of(work, + struct fg_dev, + soc_monitor_work.work); + struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg); + + // Update battery information + rc = fg_get_battery_current(fg, &fg->param.batt_ma); + if (rc < 0) + pr_err("failded to get battery current, rc=%d\n", rc); + + rc = fg_gen4_get_prop_capacity(fg, &fg->param.batt_raw_soc); + if (rc < 0) + pr_err("failed to get battery capacity, rc=%d\n", rc); + + rc = fg_gen4_get_battery_temp(fg, &fg->param.batt_temp); + if (rc < 0) + pr_err("failed to get battery temperature, rc=%d\n", rc); + + if (fg->soc_reporting_ready) + fg_battery_soc_smooth_tracking(chip); + + pr_info("soc:%d, raw_soc:%d, c:%d, s:%d\n", + fg->param.batt_soc, fg->param.batt_raw_soc, + fg->param.batt_ma, fg->charge_status); + + if (chip->cold_thermal_support) { + if (!fg->batt_temp_low + && fg->param.batt_temp <= LOW_DISCHARGE_TEMP_TRH) { + rc = fg_dynamic_set_cutoff_voltage(fg, LOW_TEMP_CUTOFF_VOL_MV); + if (rc < 0) + pr_err("fg_dynamic_set_cutoff_voltage set failed\n"); + fg->batt_temp_low = true; + } else if (fg->batt_temp_low && (fg->param.batt_temp + > LOW_DISCHARGE_TEMP_TRH + LOW_DISCHARGE_TEMP_HYS)) { + fg_dynamic_set_cutoff_voltage(fg, chip->dt.cutoff_volt_mv); + fg->batt_temp_low = false; + } + } + + schedule_delayed_work(&fg->soc_monitor_work, + msecs_to_jiffies(MONITOR_SOC_WAIT_PER_MS)); +} +#endif +#endif + static void fg_gen4_cleanup(struct fg_gen4_chip *chip) { struct fg_dev *fg = &chip->fg; @@ -5961,7 +7328,13 @@ static void fg_gen4_cleanup(struct fg_gen4_chip *chip) fg_gen4_exit_soc_scale(chip); cancel_delayed_work_sync(&fg->profile_load_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cancel_delayed_work_sync(&fg->empty_restart_fg_work); +#endif cancel_delayed_work_sync(&fg->sram_dump_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cancel_delayed_work_sync(&fg->soc_work); +#endif cancel_work_sync(&chip->pl_current_en_work); power_supply_unreg_notifier(&fg->nb); @@ -6013,6 +7386,37 @@ static void fg_gen4_post_init(struct fg_gen4_chip *chip) fg_dbg(fg, FG_STATUS, "Disabled wakeable irqs for debug board\n"); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define IBAT_OLD_WORD 317 +#define IBAT_OLD_OFFSET 0 +#define BATT_CURRENT_NUMR 488281 +#define BATT_CURRENT_DENR 1000 +int fg_get_batt_isense(struct fg_dev *fg, int *val) +{ + int rc; + u8 buf[2]; + int64_t temp = 0; + + rc = fg_sram_read(fg, IBAT_OLD_WORD, IBAT_OLD_OFFSET, buf, 2, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in reading %04x[%d] rc=%d\n", IBAT_OLD_WORD, + IBAT_OLD_OFFSET, rc); + return rc; + } + + temp = buf[0] | buf[1] << 8; + + /* Sign bit is bit 15 */ + temp = sign_extend32(temp, 15); + *val = div_s64((s64)temp * BATT_CURRENT_NUMR, BATT_CURRENT_DENR); + pr_info("read batt isense: %d[%d]%d\n", + (*val)/10, *val, (*val)/1000); + + return 0; +} +#endif + static int fg_gen4_probe(struct platform_device *pdev) { struct fg_gen4_chip *chip; @@ -6034,7 +7438,42 @@ static int fg_gen4_probe(struct platform_device *pdev) chip->ki_coeff_full_soc[0] = -EINVAL; chip->ki_coeff_full_soc[1] = -EINVAL; chip->esr_soh_cycle_count = -EINVAL; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + fg->vbat_critical_low_count = 0; + fg->vbatt_full_volt_uv = 0; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + fg->curr_cold_thermal_level = 1; +#endif +#endif chip->calib_level = -EINVAL; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + fg->fake_authentic = -EINVAL; + fg->fake_chip_ok = -EINVAL; + fg->batt_fake_temp = -EINVAL; + chip->battery_authentic_result = -EINVAL; +#ifdef CONFIG_MACH_XIAOMI_NABU + chip->battery_authentic_slave_result = -EINVAL; + chip->battery_chip_ok = -EINVAL; + chip->battery_chip_slave_ok = -EINVAL; +#endif + memset(chip->ds_romid, 0, 8); +#ifdef CONFIG_MACH_XIAOMI_NABU + memset(chip->ds_slave_romid, 0, 8); +#endif + memset(chip->ds_status, 0, 8); +#ifdef CONFIG_MACH_XIAOMI_NABU + memset(chip->ds_slave_status, 0, 8); +#endif + memset(chip->ds_page0, 0, 16); +#ifdef CONFIG_MACH_XIAOMI_NABU + memset(chip->ds_slave_page0, 0, 16); +#endif + retry_batt_profile = 0; + retry_battery_authentic_result = 0; + retry_ds_romid = 0; + retry_ds_status = 0; + retry_ds_page0 = 0; +#endif fg->regmap = dev_get_regmap(fg->dev->parent, NULL); if (!fg->regmap) { dev_err(fg->dev, "Parent regmap is unavailable\n"); @@ -6051,11 +7490,25 @@ static int fg_gen4_probe(struct platform_device *pdev) init_completion(&chip->mem_attn); INIT_WORK(&fg->status_change_work, status_change_work); INIT_WORK(&chip->esr_calib_work, esr_calib_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + INIT_WORK(&chip->vbat_sync_work, vbat_sync_work); +#endif INIT_WORK(&chip->soc_scale_work, soc_scale_work); INIT_DELAYED_WORK(&fg->profile_load_work, profile_load_work); INIT_DELAYED_WORK(&fg->sram_dump_work, sram_dump_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + INIT_DELAYED_WORK(&fg->soc_work, soc_work_fn); + INIT_DELAYED_WORK(&fg->empty_restart_fg_work, empty_restart_fg_work); +#endif INIT_DELAYED_WORK(&chip->pl_enable_work, pl_enable_work); INIT_WORK(&chip->pl_current_en_work, pl_current_en_work); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + INIT_DELAYED_WORK(&fg->soc_monitor_work, soc_monitor_work); + INIT_DELAYED_WORK(&chip->battery_authentic_work, battery_authentic_work); + INIT_DELAYED_WORK(&chip->ds_romid_work, ds_romid_work); + INIT_DELAYED_WORK(&chip->ds_status_work, ds_status_work); + INIT_DELAYED_WORK(&chip->ds_page0_work, ds_page0_work); +#endif fg->awake_votable = create_votable("FG_WS", VOTE_SET_ANY, fg_awake_cb, fg); @@ -6153,6 +7606,12 @@ static int fg_gen4_probe(struct platform_device *pdev) goto exit; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + fg->max_verify_psy = power_supply_get_by_name("batt_verify"); +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + fg->max_verify_slave_psy = power_supply_get_by_name("batt_verify_slave"); +#endif /* Register the power supply */ fg_psy_cfg.drv_data = fg; fg_psy_cfg.of_node = NULL; @@ -6166,6 +7625,16 @@ static int fg_gen4_probe(struct platform_device *pdev) goto exit; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chip->battery_authentic_result != true +#ifdef CONFIG_MACH_XIAOMI_NABU + || chip->battery_authentic_slave_result != true +#endif + ) { + schedule_delayed_work(&chip->battery_authentic_work, + msecs_to_jiffies(0)); + } +#endif fg->nb.notifier_call = fg_notifier_cb; rc = power_supply_reg_notifier(&fg->nb); if (rc < 0) { @@ -6227,6 +7696,27 @@ static int fg_gen4_probe(struct platform_device *pdev) fg_gen4_post_init(chip); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + schedule_delayed_work(&fg->soc_work, 0); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + fg->param.batt_soc = -EINVAL; + schedule_delayed_work(&fg->soc_monitor_work, + msecs_to_jiffies(MONITOR_SOC_WAIT_MS)); +#endif + + /* + * if vbat is above 3.7V and msoc is 0% and battery temperature is + * above 15 degree, we restart fg to do new first soc calculate to + * improve user experience when device is shutdown in cold then + * try to power on in normal temperature room. + */ + if ((volt_uv >= VBAT_RESTART_FG_EMPTY_UV) + && (msoc == 0) && (batt_temp >= TEMP_THR_RESTART_FG)) + schedule_delayed_work(&fg->empty_restart_fg_work, + msecs_to_jiffies(RESTART_FG_START_WORK_MS)); +#endif + pr_debug("FG GEN4 driver probed successfully\n"); return 0; exit: @@ -6247,6 +7737,9 @@ static void fg_gen4_shutdown(struct platform_device *pdev) struct fg_gen4_chip *chip = dev_get_drvdata(&pdev->dev); struct fg_dev *fg = &chip->fg; int rc, bsoc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int msoc; +#endif fg_unregister_interrupts(fg, chip, FG_GEN4_IRQ_MAX); @@ -6260,13 +7753,25 @@ static void fg_gen4_shutdown(struct platform_device *pdev) rc); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = fg_gen4_get_prop_capacity(fg, &msoc); + if (rc < 0) { + pr_err("Error in getting capacity, rc=%d\n", rc); + return; + } +#endif + rc = fg_get_sram_prop(fg, FG_SRAM_BATT_SOC, &bsoc); if (rc < 0) { pr_err("Error in getting BATT_SOC, rc=%d\n", rc); return; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (fg->charge_full || (msoc == 100)) { +#else if (fg->charge_full) { +#endif /* We need 2 most significant bytes here */ bsoc = (u32)bsoc >> 16; @@ -6290,6 +7795,9 @@ static int fg_gen4_suspend(struct device *dev) struct fg_gen4_chip *chip = dev_get_drvdata(dev); struct fg_dev *fg = &chip->fg; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cancel_delayed_work_sync(&fg->soc_work); +#endif cancel_delayed_work_sync(&chip->ttf->ttf_work); if (fg_sram_dump) cancel_delayed_work_sync(&fg->sram_dump_work); @@ -6300,11 +7808,29 @@ static int fg_gen4_resume(struct device *dev) { struct fg_gen4_chip *chip = dev_get_drvdata(dev); struct fg_dev *fg = &chip->fg; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int val = 0; +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!fg->input_present) + fg_get_batt_isense(fg, &val); + + schedule_delayed_work( + &fg->soc_work, msecs_to_jiffies(SOC_WORK_MS)); +#endif schedule_delayed_work(&chip->ttf->ttf_work, 0); if (fg_sram_dump) schedule_delayed_work(&fg->sram_dump_work, msecs_to_jiffies(fg_sram_dump_period_ms)); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + fg->param.update_now = true; + schedule_delayed_work(&fg->soc_monitor_work, + msecs_to_jiffies(MONITOR_SOC_WAIT_MS)); +#endif + return 0; } @@ -6330,6 +7856,21 @@ static struct platform_driver fg_gen4_driver = { .shutdown = fg_gen4_shutdown, }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int __init early_parse_batt_profile_vendor_id(char *p) +{ + if (p) { + if (!strcmp(p, "0A")) + is_batt_vendor_sunwoda = true; + else if (!strcmp(p, "0B")) + is_batt_vendor_nvt = true; + } + + return 0; +} +early_param("androidboot.profile_vendor_id", early_parse_batt_profile_vendor_id); +#endif + module_platform_driver(fg_gen4_driver); MODULE_DESCRIPTION("QPNP Fuel gauge GEN4 driver"); diff --git a/drivers/power/supply/qcom/qpnp-qg.c b/drivers/power/supply/qcom/qpnp-qg.c index 5651c8c0ccf9..7672839bb7d1 100644 --- a/drivers/power/supply/qcom/qpnp-qg.c +++ b/drivers/power/supply/qcom/qpnp-qg.c @@ -4558,6 +4558,14 @@ static int qpnp_qg_probe(struct platform_device *pdev) return rc; } +#ifdef CONFIG_MACH_XIAOMI_VAYU + rc = qg_sanitize_sdam(chip); + if (rc < 0) { + pr_err("Failed to sanitize SDAM, rc=%d\n", rc); + return rc; + } +#endif + rc = qg_soc_init(chip); if (rc < 0) { pr_err("Failed to initialize SOC scaling init rc=%d\n", rc); diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c index 199c1f375882..9f7e1b81c73d 100644 --- a/drivers/power/supply/qcom/qpnp-smb5.c +++ b/drivers/power/supply/qcom/qpnp-smb5.c @@ -76,6 +76,15 @@ static struct smb_params smb5_pmi632_params = { .max_u = 1000000, .step_u = 250000, }, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + .dc_icl = { + .name = "DC input current limit", + .reg = DCDC_CFG_REF_MAX_PSNS_REG, + .min_u = 0, + .max_u = 1500000, + .step_u = 50000, + }, +#endif .jeita_cc_comp_hot = { .name = "jeita fcc reduction", .reg = JEITA_CCCOMP_CFG_HOT_REG, @@ -156,15 +165,24 @@ static struct smb_params smb5_pm8150b_params = { .name = "usb otg current limit", .reg = DCDC_OTG_CURRENT_LIMIT_CFG_REG, .min_u = 500000, +#ifdef CONFIG_MACH_XIAOMI_NABU + .max_u = 2000000, +#else .max_u = 3000000, +#endif .step_u = 500000, }, .dc_icl = { .name = "DC input current limit", .reg = DCDC_CFG_REF_MAX_PSNS_REG, .min_u = 0, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + .max_u = 1200000, + .step_u = 40000, +#else .max_u = DCIN_ICL_MAX_UA, .step_u = 50000, +#endif }, .jeita_cc_comp_hot = { .name = "jeita fcc reduction", @@ -210,6 +228,9 @@ static struct smb_params smb5_pm8150b_params = { struct smb_dt_props { int usb_icl_ua; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + int dc_icl_ua; +#endif struct device_node *revid_dev_node; enum float_options float_option; int chg_inhibit_thr_mv; @@ -222,6 +243,9 @@ struct smb_dt_props { int auto_recharge_vbat_mv; int wd_bark_time; int wd_snarl_time_cfg; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int batt_unverify_fcc_ua; +#endif int batt_profile_fcc_ua; int batt_profile_fv_uv; int term_current_src; @@ -236,6 +260,10 @@ struct smb5 { struct smb_dt_props dt; }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static struct smb_charger *__smbchg; +#endif + static int __debug_mask; module_param_named( debug_mask, __debug_mask, int, 0600 @@ -251,6 +279,13 @@ module_param_named( weak_chg_icl_ua, __weak_chg_icl_ua, int, 0600 ); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static bool disable_thermal = false; +module_param_named( + disable_thermal, disable_thermal, bool, 0600 +); +#endif + enum { BAT_THERM = 0, MISC_THERM, @@ -258,6 +293,62 @@ enum { SMB_THERM, }; +#ifdef CONFIG_MACH_XIAOMI_NABU +static BLOCKING_NOTIFIER_HEAD(pen_charge_state_notifier_list); + +int pen_charge_state_notifier_register_client(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&pen_charge_state_notifier_list, nb); +} +EXPORT_SYMBOL(pen_charge_state_notifier_register_client); + +int pen_charge_state_notifier_unregister_client(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&pen_charge_state_notifier_list, nb); +} +EXPORT_SYMBOL(pen_charge_state_notifier_unregister_client); + +int pen_charge_state_notifier_call_chain(unsigned long val, void *v) +{ + return blocking_notifier_call_chain(&pen_charge_state_notifier_list, val, v); +} +EXPORT_SYMBOL(pen_charge_state_notifier_call_chain); +#endif + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +static int smb5_get_prop_input_voltage_regulation(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; +/* + if (!chg->idtp_psy) { + chg->idtp_psy = power_supply_get_by_name("idt"); + if (!chg->idtp_psy) + return -EINVAL; + } +*/ + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + chg->wls_chip_psy = chg->idtp_psy; + else { + chg->wip_psy = power_supply_get_by_name("rx1618"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, val); + + val->intval = 1000*val->intval;//IDT in mV + + return rc; +} +#endif + static const struct clamp_config clamp_levels[] = { { {0x11C6, 0x11F9, 0x13F1}, {0x60, 0x2E, 0x90} }, { {0x11C6, 0x11F9, 0x13F1}, {0x60, 0x2B, 0x9C} }, @@ -387,21 +478,102 @@ static int smb5_configure_internal_pull(struct smb_charger *chg, int type, return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int read_step_chg_range_data_from_node(struct device_node *node, + const char *prop_str, struct six_pin_step_data *ranges) +{ + int rc = 0, length, per_tuple_length, tuples; + + if (!node || !prop_str || !ranges) { + pr_err("Invalid parameters passed\n"); + return -EINVAL; + } + + rc = of_property_count_elems_of_size(node, prop_str, sizeof(u32)); + if (rc < 0) { + pr_err("Count %s failed, rc=%d\n", prop_str, rc); + return rc; + } + + length = rc; + per_tuple_length = sizeof(struct six_pin_step_data) / sizeof(u32); + if (length % per_tuple_length) { + pr_err("%s length (%d) should be multiple of %d\n", + prop_str, length, per_tuple_length); + return -EINVAL; + } + tuples = length / per_tuple_length; + + if (tuples > MAX_STEP_ENTRIES) { + pr_err("too many entries(%d), only %d allowed\n", + tuples, MAX_STEP_ENTRIES); + return -EINVAL; + } + + rc = of_property_read_u32_array(node, prop_str, + (u32 *)ranges, length); + if (rc) { + pr_err("Read %s failed, rc=%d\n", prop_str, rc); + return rc; + } + + return rc; +} + +static int smb5_charge_step_charge_init(struct smb_charger *chg, + struct device_node *node) +{ + int rc = 0; + + rc = read_step_chg_range_data_from_node(node, + "mi,six-pin-step-chg-params", + chg->six_pin_step_cfg); + if (rc < 0) { + pr_debug("Read mi,six-pin-step-chg-params failed charger node, rc=%d\n", + rc); + chg->six_pin_step_charge_enable = false; + } + + return rc; +} +#endif + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +int smblib_change_psns_to_curr(struct smb_charger *chg, int uv) +{ + uv = uv * PSNS_CURRENT_SAMPLE_RATE / PSNS_CURRENT_SAMPLE_RESIS; + + return uv; +} +#endif + #define MICRO_1P5A 1500000 #define MICRO_P1A 100000 #define MICRO_1PA 1000000 #define MICRO_3PA 3000000 +#ifdef CONFIG_MACH_XIAOMI_NABU +#define MICRO_1P8A_FOR_DCP 2000000 +#elif defined(CONFIG_MACH_XIAOMI_SM8150) +#define MICRO_1P8A_FOR_DCP 1800000 +#endif #define MICRO_4PA 4000000 #define OTG_DEFAULT_DEGLITCH_TIME_MS 50 #define DEFAULT_WD_BARK_TIME 64 #define DEFAULT_WD_SNARL_TIME_8S 0x07 #define DEFAULT_FCC_STEP_SIZE_UA 100000 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define DEFAULT_FCC_STEP_UPDATE_DELAY_MS 100 +#else #define DEFAULT_FCC_STEP_UPDATE_DELAY_MS 1000 +#endif static int smb5_parse_dt(struct smb5 *chip) { struct smb_charger *chg = &chip->chg; struct device_node *node = chg->dev->of_node; int rc, byte_len, tmp; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int i; +#endif if (!node) { pr_err("device tree node missing\n"); @@ -427,11 +599,59 @@ static int smb5_parse_dt(struct smb5 *chip) chg->sw_jeita_enabled = of_property_read_bool(node, "qcom,sw-jeita-enable"); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->pps_fcc_therm_work_disabled = of_property_read_bool(node, + "mi,pps-thermal-setting-disable"); + + chg->use_bq_pump = of_property_read_bool(node, + "mi,use-bq-pump"); +#endif + chg->pd_not_supported = chg->pd_not_supported || of_property_read_bool(node, "qcom,usb-pd-disable"); chg->lpd_disabled = chg->lpd_disabled || of_property_read_bool(node, "qcom,lpd-disable"); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->lpd_enabled = of_property_read_bool(node, + "qcom,lpd-enable"); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->six_pin_step_charge_enable = of_property_read_bool(node, + "mi,six-pin-step-chg"); +#endif + + chg->dynamic_fv_enabled = of_property_read_bool(node, + "qcom,dynamic-fv-enable"); + + chg->qc_class_ab = of_property_read_bool(node, + "qcom,distinguish-qc-class-ab"); + + chg->support_wireless = of_property_read_bool(node, + "qcom,support-wireless"); + +#ifdef CONFIG_MACH_XIAOMI_NABU + chg->qc3p5_supported = of_property_read_bool(node, + "mi,support-qc3p5-without-smb"); +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->support_ffc = of_property_read_bool(node, + "mi,support-ffc"); + + rc = of_property_read_u32(node, "mi,ffc-low-tbat", &chg->ffc_low_tbat); + if (rc < 0) { + pr_info("use default ffc_low_tbat\n"); + chg->ffc_low_tbat = DEFAULT_FFC_LOW_TBAT; + } + + rc = of_property_read_u32(node, "mi,ffc-high-tbat", &chg->ffc_high_tbat); + if (rc < 0) { + pr_info("use default ffc_high_tbat\n"); + chg->ffc_high_tbat = DEFAULT_FFC_HIGH_TBAT; + } +#endif +#endif rc = of_property_read_u32(node, "qcom,wd-bark-time-secs", &chip->dt.wd_bark_time); @@ -451,6 +671,15 @@ static int smb5_parse_dt(struct smb5 *chip) if (rc < 0) chip->dt.batt_profile_fcc_ua = -EINVAL; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->batt_profile_fcc_ua = chip->dt.batt_profile_fcc_ua; + + rc = of_property_read_u32(node, + "mi,fcc-batt-unverify-ua", &chip->dt.batt_unverify_fcc_ua); + if (rc < 0) + chip->dt.batt_unverify_fcc_ua = -EINVAL; +#endif + rc = of_property_read_u32(node, "qcom,fv-max-uv", &chip->dt.batt_profile_fv_uv); if (rc < 0) @@ -461,6 +690,13 @@ static int smb5_parse_dt(struct smb5 *chip) if (rc < 0) chip->dt.usb_icl_ua = -EINVAL; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + rc = of_property_read_u32(node, + "qcom,dc-icl-ua", &chip->dt.dc_icl_ua); + if (rc < 0) + chip->dt.dc_icl_ua = -EINVAL; +#endif + rc = of_property_read_u32(node, "qcom,otg-cl-ua", &chg->otg_cl_ua); if (rc < 0) @@ -476,22 +712,27 @@ static int smb5_parse_dt(struct smb5 *chip) rc = of_property_read_u32(node, "qcom,chg-term-current-ma", &chip->dt.term_current_thresh_hi_ma); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->chg_term_current_thresh_hi_from_dts = chip->dt.term_current_thresh_hi_ma; +#endif + if (chip->dt.term_current_src == ITERM_SRC_ADC) rc = of_property_read_u32(node, "qcom,chg-term-base-current-ma", &chip->dt.term_current_thresh_lo_ma); - if (of_find_property(node, "qcom,thermal-mitigation", &byte_len)) { - chg->thermal_mitigation = devm_kzalloc(chg->dev, byte_len, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (of_find_property(node, "qcom,lpd_hwversion", &byte_len)) { + chg->lpd_hwversion = devm_kzalloc(chg->dev, byte_len, GFP_KERNEL); - if (chg->thermal_mitigation == NULL) + if (chg->lpd_hwversion == NULL) return -ENOMEM; - chg->thermal_levels = byte_len / sizeof(u32); + chg->lpd_levels = byte_len / sizeof(u32); rc = of_property_read_u32_array(node, - "qcom,thermal-mitigation", - chg->thermal_mitigation, - chg->thermal_levels); + "qcom,lpd_hwversion", + chg->lpd_hwversion, + byte_len / sizeof(u32)); if (rc < 0) { dev_err(chg->dev, "Couldn't read threm limits rc = %d\n", rc); @@ -499,101 +740,392 @@ static int smb5_parse_dt(struct smb5 *chip) } } - rc = of_property_read_u32(node, "qcom,charger-temp-max", - &chg->charger_temp_max); - if (rc < 0) - chg->charger_temp_max = -EINVAL; + if (of_find_property(node, "qcom,thermal-mitigation-dcp", &byte_len)) { + chg->thermal_mitigation_dcp = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); - rc = of_property_read_u32(node, "qcom,smb-temp-max", - &chg->smb_temp_max); - if (rc < 0) - chg->smb_temp_max = -EINVAL; + if (chg->thermal_mitigation_dcp == NULL) + return -ENOMEM; - rc = of_property_read_u32(node, "qcom,float-option", - &chip->dt.float_option); - if (!rc && (chip->dt.float_option < 0 || chip->dt.float_option > 4)) { - pr_err("qcom,float-option is out of range [0, 4]\n"); - return -EINVAL; + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-dcp", + chg->thermal_mitigation_dcp, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } } - chip->dt.hvdcp_disable = of_property_read_bool(node, - "qcom,hvdcp-disable"); - chg->hvdcp_disable = chip->dt.hvdcp_disable; +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (of_find_property(node, "qcom,thermal-mitigation-dc", &byte_len)) { + chg->thermal_mitigation_dc = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); - chip->dt.hvdcp_autonomous = of_property_read_bool(node, - "qcom,hvdcp-autonomous-enable"); + if (chg->thermal_mitigation_dc == NULL) + return -ENOMEM; - rc = of_property_read_u32(node, "qcom,chg-inhibit-threshold-mv", - &chip->dt.chg_inhibit_thr_mv); - if (!rc && (chip->dt.chg_inhibit_thr_mv < 0 || - chip->dt.chg_inhibit_thr_mv > 300)) { - pr_err("qcom,chg-inhibit-threshold-mv is incorrect\n"); - return -EINVAL; + chg->dc_thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-dc", + chg->thermal_mitigation_dc, + chg->dc_thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } } - chip->dt.auto_recharge_soc = -EINVAL; - rc = of_property_read_u32(node, "qcom,auto-recharge-soc", - &chip->dt.auto_recharge_soc); - if (!rc && (chip->dt.auto_recharge_soc < 0 || - chip->dt.auto_recharge_soc > 100)) { - pr_err("qcom,auto-recharge-soc is incorrect\n"); - return -EINVAL; - } - chg->auto_recharge_soc = chip->dt.auto_recharge_soc; + if (of_find_property(node, "qcom,thermal-mitigation-epp", &byte_len)) { + chg->thermal_mitigation_epp = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); - chip->dt.auto_recharge_vbat_mv = -EINVAL; - rc = of_property_read_u32(node, "qcom,auto-recharge-vbat-mv", - &chip->dt.auto_recharge_vbat_mv); - if (!rc && (chip->dt.auto_recharge_vbat_mv < 0)) { - pr_err("qcom,auto-recharge-vbat-mv is incorrect\n"); - return -EINVAL; + if (chg->thermal_mitigation_epp == NULL) + return -ENOMEM; + + chg->dc_thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-epp", + chg->thermal_mitigation_epp, + chg->dc_thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } } - chg->dcp_icl_ua = chip->dt.usb_icl_ua; + if (of_find_property(node, "qcom,thermal-mitigation-bpp-qc3", &byte_len)) { + chg->thermal_mitigation_bpp_qc3 = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); - chg->suspend_input_on_debug_batt = of_property_read_bool(node, - "qcom,suspend-input-on-debug-batt"); + if (chg->thermal_mitigation_bpp_qc3 == NULL) + return -ENOMEM; - chg->fake_chg_status_on_debug_batt = of_property_read_bool(node, - "qcom,fake-chg-status-on-debug-batt"); + chg->dc_thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-bpp-qc3", + chg->thermal_mitigation_bpp_qc3, + chg->dc_thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } - rc = of_property_read_u32(node, "qcom,otg-deglitch-time-ms", - &chg->otg_delay_ms); - if (rc < 0) - chg->otg_delay_ms = OTG_DEFAULT_DEGLITCH_TIME_MS; + if (of_find_property(node, "qcom,thermal-mitigation-bpp-qc2", &byte_len)) { + chg->thermal_mitigation_bpp_qc2 = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); - chg->fcc_stepper_enable = of_property_read_bool(node, - "qcom,fcc-stepping-enable"); + if (chg->thermal_mitigation_bpp_qc2 == NULL) + return -ENOMEM; - chg->uusb_moisture_protection_enabled = - chg->uusb_moisture_protection_enabled && - of_property_read_bool(node, - "qcom,uusb-moisture-protection-enable"); + chg->dc_thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-bpp-qc2", + chg->thermal_mitigation_bpp_qc2, + chg->dc_thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } - chg->hw_die_temp_mitigation = of_property_read_bool(node, - "qcom,hw-die-temp-mitigation"); + if (of_find_property(node, "qcom,thermal-mitigation-bpp", &byte_len)) { + chg->thermal_mitigation_bpp = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); - chg->hw_connector_mitigation = of_property_read_bool(node, - "qcom,hw-connector-mitigation"); + if (chg->thermal_mitigation_bpp == NULL) + return -ENOMEM; - chg->hw_skin_temp_mitigation = of_property_read_bool(node, - "qcom,hw-skin-temp-mitigation"); + chg->dc_thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-bpp", + chg->thermal_mitigation_bpp, + chg->dc_thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } +#endif - chg->en_skin_therm_mitigation = of_property_read_bool(node, - "qcom,en-skin-therm-mitigation"); + if (of_find_property(node, "qcom,thermal-mitigation-qc2", &byte_len)) { + chg->thermal_mitigation_qc2 = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); - chg->connector_pull_up = -EINVAL; - of_property_read_u32(node, "qcom,connector-internal-pull-kohm", - &chg->connector_pull_up); + if (chg->thermal_mitigation_qc2 == NULL) + return -ENOMEM; - chg->smb_pull_up = -EINVAL; - of_property_read_u32(node, "qcom,smb-internal-pull-kohm", - &chg->smb_pull_up); + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-qc2", + chg->thermal_mitigation_qc2, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } - chip->dt.adc_based_aicl = of_property_read_bool(node, - "qcom,adc-based-aicl"); + if (of_find_property(node, "qcom,thermal-mitigation-pd-base", &byte_len)) { + chg->thermal_mitigation_pd_base = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); + + if (chg->thermal_mitigation_pd_base == NULL) + return -ENOMEM; + + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-pd-base", + chg->thermal_mitigation_pd_base, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } + + if (of_find_property(node, "qcom,thermal-fcc-qc3-normal", &byte_len)) { + chg->thermal_fcc_qc3_normal = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); + + if (chg->thermal_fcc_qc3_normal == NULL) + return -ENOMEM; + + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-fcc-qc3-normal", + chg->thermal_fcc_qc3_normal, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } + + if (of_find_property(node, "qcom,thermal-fcc-qc3-cp", &byte_len)) { + chg->thermal_fcc_qc3_cp = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); + + if (chg->thermal_fcc_qc3_cp == NULL) + return -ENOMEM; + + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-fcc-qc3-cp", + chg->thermal_fcc_qc3_cp, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } + + if (of_find_property(node, "qcom,thermal-fcc-qc3-classb-cp", &byte_len)) { + chg->thermal_fcc_qc3_classb_cp = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); + + if (chg->thermal_fcc_qc3_classb_cp == NULL) + return -ENOMEM; + + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-fcc-qc3-classb-cp", + chg->thermal_fcc_qc3_classb_cp, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } + + if (of_find_property(node, "qcom,thermal-fcc-pps-cp", &byte_len)) { + chg->thermal_fcc_pps_cp = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); + + if (chg->thermal_fcc_pps_cp == NULL) + return -ENOMEM; + + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-fcc-pps-cp", + chg->thermal_fcc_pps_cp, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } + + if (of_find_property(node, "qcom,thermal-mitigation-icl", &byte_len)) { + chg->thermal_mitigation_icl = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); + + if (chg->thermal_mitigation_icl == NULL) + return -ENOMEM; + + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation-icl", + chg->thermal_mitigation_icl, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } +#else + if (of_find_property(node, "qcom,thermal-mitigation", &byte_len)) { + chg->thermal_mitigation = devm_kzalloc(chg->dev, byte_len, + GFP_KERNEL); + + if (chg->thermal_mitigation == NULL) + return -ENOMEM; + + chg->thermal_levels = byte_len / sizeof(u32); + rc = of_property_read_u32_array(node, + "qcom,thermal-mitigation", + chg->thermal_mitigation, + chg->thermal_levels); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't read threm limits rc = %d\n", rc); + return rc; + } + } +#endif + + rc = of_property_read_u32(node, "qcom,charger-temp-max", + &chg->charger_temp_max); + if (rc < 0) + chg->charger_temp_max = -EINVAL; + + rc = of_property_read_u32(node, "qcom,smb-temp-max", + &chg->smb_temp_max); + if (rc < 0) + chg->smb_temp_max = -EINVAL; + + rc = of_property_read_u32(node, "qcom,float-option", + &chip->dt.float_option); + if (!rc && (chip->dt.float_option < 0 || chip->dt.float_option > 4)) { + pr_err("qcom,float-option is out of range [0, 4]\n"); + return -EINVAL; + } + + chip->dt.hvdcp_disable = of_property_read_bool(node, + "qcom,hvdcp-disable"); + chg->hvdcp_disable = chip->dt.hvdcp_disable; + + chip->dt.hvdcp_autonomous = of_property_read_bool(node, + "qcom,hvdcp-autonomous-enable"); + + rc = of_property_read_u32(node, "qcom,chg-inhibit-threshold-mv", + &chip->dt.chg_inhibit_thr_mv); + if (!rc && (chip->dt.chg_inhibit_thr_mv < 0 || + chip->dt.chg_inhibit_thr_mv > 300)) { + pr_err("qcom,chg-inhibit-threshold-mv is incorrect\n"); + return -EINVAL; + } + + chip->dt.auto_recharge_soc = -EINVAL; + rc = of_property_read_u32(node, "qcom,auto-recharge-soc", + &chip->dt.auto_recharge_soc); + if (!rc && (chip->dt.auto_recharge_soc < 0 || + chip->dt.auto_recharge_soc > 100)) { + pr_err("qcom,auto-recharge-soc is incorrect\n"); + return -EINVAL; + } + chg->auto_recharge_soc = chip->dt.auto_recharge_soc; + + chip->dt.auto_recharge_vbat_mv = -EINVAL; + rc = of_property_read_u32(node, "qcom,auto-recharge-vbat-mv", + &chip->dt.auto_recharge_vbat_mv); + if (!rc && (chip->dt.auto_recharge_vbat_mv < 0)) { + pr_err("qcom,auto-recharge-vbat-mv is incorrect\n"); + return -EINVAL; + } + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->dcp_icl_ua = MICRO_1P8A_FOR_DCP; +#else + chg->dcp_icl_ua = chip->dt.usb_icl_ua; +#endif + + chg->suspend_input_on_debug_batt = of_property_read_bool(node, + "qcom,suspend-input-on-debug-batt"); + + chg->fake_chg_status_on_debug_batt = of_property_read_bool(node, + "qcom,fake-chg-status-on-debug-batt"); + + rc = of_property_read_u32(node, "qcom,otg-deglitch-time-ms", + &chg->otg_delay_ms); + if (rc < 0) + chg->otg_delay_ms = OTG_DEFAULT_DEGLITCH_TIME_MS; + + chg->fcc_stepper_enable = of_property_read_bool(node, + "qcom,fcc-stepping-enable"); + + chg->uusb_moisture_protection_enabled = + chg->uusb_moisture_protection_enabled && + of_property_read_bool(node, + "qcom,uusb-moisture-protection-enable"); + + chg->hw_die_temp_mitigation = of_property_read_bool(node, + "qcom,hw-die-temp-mitigation"); + + chg->hw_connector_mitigation = of_property_read_bool(node, + "qcom,hw-connector-mitigation"); + + chg->hw_skin_temp_mitigation = of_property_read_bool(node, + "qcom,hw-skin-temp-mitigation"); + + chg->en_skin_therm_mitigation = of_property_read_bool(node, + "qcom,en-skin-therm-mitigation"); + + chg->connector_pull_up = -EINVAL; + of_property_read_u32(node, "qcom,connector-internal-pull-kohm", + &chg->connector_pull_up); + + chg->smb_pull_up = -EINVAL; + of_property_read_u32(node, "qcom,smb-internal-pull-kohm", + &chg->smb_pull_up); + + chip->dt.adc_based_aicl = of_property_read_bool(node, + "qcom,adc-based-aicl"); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->six_pin_step_charge_enable) { + rc = smb5_charge_step_charge_init(chg, node); + if (!rc) { + for (i = 0; i < MAX_STEP_ENTRIES; i++) + pr_err("six-pin-step-chg-cfg: %duV, %duA\n", + chg->six_pin_step_cfg[i].vfloat_step_uv, + chg->six_pin_step_cfg[i].fcc_step_ua); + } + } +#endif /* Extract ADC channels */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_get_iio_channel(chg, "usb_in_voltage", + &chg->iio.usbin_v_chan); + if (rc < 0) + return rc; +#endif + rc = smblib_get_iio_channel(chg, "mid_voltage", &chg->iio.mid_chan); if (rc < 0) return rc; @@ -637,6 +1169,16 @@ static int smb5_parse_dt(struct smb5 *chip) if (rc < 0) return rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_get_iio_channel(chg, "hw_version_gpio5", &chg->iio.hw_version_gpio5); + if (rc < 0) + return rc; + + rc = smblib_get_iio_channel(chg, "project_gpio6", &chg->iio.project_gpio6); + if (rc < 0) + return rc; +#endif + chip->dt.disable_suspend_on_collapse = of_property_read_bool(node, "qcom,disable-suspend-on-collapse"); @@ -808,6 +1350,98 @@ static int smb5_set_prop_comp_clamp_level(struct smb_charger *chg, return rc; } +#ifdef CONFIG_MACH_XIAOMI_NABU +int smblib_set_prop_tx_mac(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc = 0; + chg->tx_bt_mac = val->int64val; + if (!chg->wls_psy) { + chg->wls_psy = power_supply_get_by_name("wireless"); + if (!chg->wls_psy) + return -ENODEV; + } + power_supply_changed(chg->wls_psy); + return rc; +} + +int smblib_set_prop_rx_cr(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc = 0; + if (!chg->wls_psy) { + chg->wls_psy = power_supply_get_by_name("wireless"); + if (!chg->wls_psy) { + return -ENODEV; + } + } + if (!val->int64val) + return rc; + chg->oob_rpp_msg_cnt %= 9; + chg->oob_rpp_msg_cnt++; + chg->rpp = (val->int64val | chg->oob_rpp_msg_cnt << 48); + power_supply_changed(chg->wls_psy); + return rc; +} + +int smblib_set_prop_rx_cep(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc = 0; + if (!chg->wls_psy) { + chg->wls_psy = power_supply_get_by_name("wireless"); + if (!chg->wls_psy) { + return -ENODEV; + } + } + if (!val->int64val) + return rc; + chg->oob_cep_msg_cnt %= 9; + chg->oob_cep_msg_cnt++; + chg->cep = (val->int64val | chg->oob_cep_msg_cnt << 48); + power_supply_changed(chg->wls_psy); + return rc; +} +#define BLE_CONNECT 1 +#define BLE_DISCONNECT 2 +#define BLE_CONNECTING 3 + +extern int idtp_op_ble_flag(int en); +extern int rx_op_ble_flag(int en); +int smblib_set_prop_bt_state(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int bt_state = -2; + + bt_state = val->intval; + +#if defined(CONFIG_IDT_P9415) || defined(CONFIG_RX1619) + switch (bt_state) { + case BLE_CONNECT: + if (chg->idtp_psy) + idtp_op_ble_flag(1); + else + rx_op_ble_flag(1); + chg->tx_bt_mac = 0; + break; + case BLE_DISCONNECT: + if (chg->idtp_psy) + idtp_op_ble_flag(0); + else + rx_op_ble_flag(0); + chg->tx_bt_mac = 0; + break; + case BLE_CONNECTING: + chg->tx_bt_mac = 0; + break; + default: + break; + } +#endif + return 0; +} +#endif + /************************ * USB PSY REGISTRATION * ************************/ @@ -823,6 +1457,13 @@ static enum power_supply_property smb5_usb_props[] = { POWER_SUPPLY_PROP_TYPEC_CC_ORIENTATION, POWER_SUPPLY_PROP_LOW_POWER, POWER_SUPPLY_PROP_PD_ACTIVE, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_PD_AUTHENTICATION, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_FASTCHARGE_MODE, + POWER_SUPPLY_PROP_PD_REMOVE_COMPENSATION, +#endif +#endif POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED, POWER_SUPPLY_PROP_INPUT_CURRENT_NOW, POWER_SUPPLY_PROP_BOOST_CURRENT, @@ -830,6 +1471,11 @@ static enum power_supply_property smb5_usb_props[] = { POWER_SUPPLY_PROP_CTM_CURRENT_MAX, POWER_SUPPLY_PROP_HW_CURRENT_MAX, POWER_SUPPLY_PROP_REAL_TYPE, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_HVDCP3_TYPE, + POWER_SUPPLY_PROP_QUICK_CHARGE_TYPE, + POWER_SUPPLY_PROP_PR_SWAP, +#endif POWER_SUPPLY_PROP_PD_VOLTAGE_MAX, POWER_SUPPLY_PROP_PD_VOLTAGE_MIN, POWER_SUPPLY_PROP_CONNECTOR_TYPE, @@ -839,6 +1485,9 @@ static enum power_supply_property smb5_usb_props[] = { POWER_SUPPLY_PROP_VOLTAGE_MAX_LIMIT, POWER_SUPPLY_PROP_SMB_EN_MODE, POWER_SUPPLY_PROP_SMB_EN_REASON, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_TYPE_RECHECK, +#endif POWER_SUPPLY_PROP_ADAPTER_CC_MODE, POWER_SUPPLY_PROP_SCOPE, POWER_SUPPLY_PROP_MOISTURE_DETECTED, @@ -849,6 +1498,9 @@ static enum power_supply_property smb5_usb_props[] = { POWER_SUPPLY_PROP_SKIN_HEALTH, POWER_SUPPLY_PROP_APSD_RERUN, POWER_SUPPLY_PROP_APSD_TIMEOUT, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_APDO_MAX, +#endif }; static int smb5_usb_get_prop(struct power_supply *psy, @@ -866,6 +1518,13 @@ static int smb5_usb_get_prop(struct power_supply *psy, rc = smblib_get_prop_usb_present(chg, val); break; case POWER_SUPPLY_PROP_ONLINE: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->report_usb_absent) { + val->intval = 0; + break; + } +#endif + rc = smblib_get_prop_usb_online(chg, val); if (!val->intval) break; @@ -913,6 +1572,55 @@ static int smb5_usb_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_REAL_TYPE: val->intval = chg->real_charger_type; break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_HVDCP3_TYPE: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->real_charger_type != POWER_SUPPLY_TYPE_USB_HVDCP_3 + && chg->real_charger_type != POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + val->intval = HVDCP3_NONE; /* 0: none hvdcp3 insert */ + } else { + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + if (chg->qc3p5_power_limit_w == 18) + val->intval = HVDCP3P5_CLASSA_18W; + else if (chg->qc3p5_power_limit_w == 27) + val->intval = HVDCP3P5_CLASSB_27W; + else + val->intval = HVDCP3_NONE; + } else { // QC3 + if (chg->qc_class_ab) { + if (chg->is_qc_class_a) + val->intval = HVDCP3_CLASSA_18W; /* 18W hvdcp3 insert */ + else if (chg->is_qc_class_b) + val->intval = HVDCP3_CLASSB_27W; /* 27W hvdcp3 insert */ + else + val->intval = HVDCP3_NONE; + } else {/* for F10 */ + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3) + val->intval = HVDCP3_CLASSA_18W; /* 18W hvdcp3 insert */ + else + val->intval = HVDCP3_NONE; + } + } + } +#else + if (chg->real_charger_type != POWER_SUPPLY_TYPE_USB_HVDCP_3) + val->intval = HVDCP3_NONE; /* 0: none hvdcp3 insert */ + else { + if (chg->is_qc_class_a) + val->intval = HVDCP3_CLASSA_18W; /* 18W hvdcp3 insert */ + else if (chg->is_qc_class_b) + val->intval = HVDCP3_CLASSB_27W; /* 27W hvdcp3 insert */ + else + val->intval = HVDCP3_NONE; + } +#endif + break; +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_QUICK_CHARGE_TYPE: + val->intval = smblib_get_quick_charge_type(chg); + break; +#endif case POWER_SUPPLY_PROP_TYPEC_MODE: if (chg->connector_type == POWER_SUPPLY_CONNECTOR_MICRO_USB) val->intval = POWER_SUPPLY_TYPEC_NONE; @@ -943,6 +1651,19 @@ static int smb5_usb_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_PD_ACTIVE: val->intval = chg->pd_active; break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_PD_AUTHENTICATION: + val->intval = chg->pd_verifed; + break; +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + val->intval = smblib_get_fastcharge_mode(chg); + break; + case POWER_SUPPLY_PROP_PD_REMOVE_COMPENSATION: + val->intval = chg->remove_comp; + break; +#endif case POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED: rc = smblib_get_prop_input_current_settled(chg, val); break; @@ -1006,6 +1727,11 @@ static int smb5_usb_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_SMB_EN_REASON: val->intval = chg->cp_reason; break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_TYPE_RECHECK: + rc = smblib_get_prop_type_recheck(chg, val); + break; +#endif case POWER_SUPPLY_PROP_MOISTURE_DETECTED: val->intval = chg->moisture_present; break; @@ -1038,6 +1764,11 @@ static int smb5_usb_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_APSD_TIMEOUT: val->intval = chg->apsd_ext_timeout; break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_APDO_MAX: + val->intval = chg->apdo_max; + break; +#endif default: pr_err("get prop %d is not supported in usb\n", psp); rc = -EINVAL; @@ -1074,6 +1805,31 @@ static int smb5_usb_set_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_PD_ACTIVE: rc = smblib_set_prop_pd_active(chg, val); break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_PD_AUTHENTICATION: + chg->pd_verifed = val->intval; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /*if set pd authentication auto set fastcharge mode*/ + /*do not break here*/ +#else + rc = vote(chg->usb_icl_votable, PD_VERIFED_VOTER, + !chg->pd_verifed, PD_UNVERIFED_CURRENT); + break; +#endif +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + power_supply_changed(chg->usb_psy); + if (chg->support_ffc) { + rc = smblib_set_fastcharge_mode(chg, val->intval); + } + schedule_delayed_work(&chg->report_soc_decimal_work, + msecs_to_jiffies(REPORT_SOC_DECIMAL_MS)); + break; + case POWER_SUPPLY_PROP_PD_REMOVE_COMPENSATION: + chg->remove_comp = val->intval; + break; +#endif case POWER_SUPPLY_PROP_PD_IN_HARD_RESET: rc = smblib_set_prop_pd_in_hard_reset(chg, val); break; @@ -1121,6 +1877,10 @@ static int smb5_usb_set_prop(struct power_supply *psy, else rc = -EINVAL; break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_TYPE_RECHECK: + rc = smblib_set_prop_type_recheck(chg, val); +#endif case POWER_SUPPLY_PROP_VOLTAGE_MAX_LIMIT: smblib_set_prop_usb_voltage_max_limit(chg, val); break; @@ -1132,6 +1892,11 @@ static int smb5_usb_set_prop(struct power_supply *psy, chg->apsd_ext_timeout = false; smblib_rerun_apsd(chg); break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_APDO_MAX: + chg->apdo_max = val->intval; + break; +#endif default: pr_err("set prop %d is not supported\n", psp); rc = -EINVAL; @@ -1150,7 +1915,17 @@ static int smb5_usb_prop_is_writeable(struct power_supply *psy, case POWER_SUPPLY_PROP_THERM_ICL_LIMIT: case POWER_SUPPLY_PROP_VOLTAGE_MAX_LIMIT: case POWER_SUPPLY_PROP_ADAPTER_CC_MODE: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_PD_AUTHENTICATION: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_FASTCHARGE_MODE: + case POWER_SUPPLY_PROP_PD_REMOVE_COMPENSATION: +#endif +#endif case POWER_SUPPLY_PROP_APSD_RERUN: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_APDO_MAX: +#endif return 1; default: break; @@ -1174,10 +1949,17 @@ static int smb5_init_usb_psy(struct smb5 *chip) struct power_supply_config usb_cfg = {}; struct smb_charger *chg = &chip->chg; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->usb_psy_desc = usb_psy_desc; +#endif usb_cfg.drv_data = chip; usb_cfg.of_node = chg->dev->of_node; chg->usb_psy = devm_power_supply_register(chg->dev, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + &chg->usb_psy_desc, +#else &usb_psy_desc, +#endif &usb_cfg); if (IS_ERR(chg->usb_psy)) { pr_err("Couldn't register USB power supply\n"); @@ -1210,6 +1992,13 @@ static int smb5_usb_port_get_prop(struct power_supply *psy, val->intval = POWER_SUPPLY_TYPE_USB; break; case POWER_SUPPLY_PROP_ONLINE: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->report_usb_absent) { + val->intval = 0; + break; + } +#endif + rc = smblib_get_prop_usb_online(chg, val); if (!val->intval) break; @@ -1396,6 +2185,9 @@ static int smb5_usb_main_set_prop(struct power_supply *psy, union power_supply_propval pval = {0, }; enum power_supply_type real_chg_type = chg->real_charger_type; int rc = 0, offset_ua = 0; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int parallel_output_mode = 0; +#endif switch (psp) { case POWER_SUPPLY_PROP_VOLTAGE_MAX: @@ -1407,8 +2199,33 @@ static int smb5_usb_main_set_prop(struct power_supply *psy, if (rc < 0) offset_ua = 0; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->six_pin_step_charge_enable) { + rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_TEMP, &pval); + /* if temp out of soft jeita normal zone, do not add fast charge current offset */ + if (pval.intval >= CP_WARM_THRESHOLD - SOFT_JEITA_HYSTERESIS || pval.intval <= CP_COOL_THRESHOLD + SOFT_JEITA_HYSTERESIS + || chg->index_vfloat == MAX_STEP_ENTRIES - 1) + + rc = smblib_set_charge_param(chg, &chg->param.fcc, val->intval); + else + rc = smblib_set_charge_param(chg, &chg->param.fcc,val->intval + offset_ua); + } else { + if (chg->cp_psy) { + rc = power_supply_get_property(chg->cp_psy, + POWER_SUPPLY_PROP_PARALLEL_OUTPUT_MODE, &pval); + if (rc >= 0) + parallel_output_mode = pval.intval; + } + /* only parallel output mode is output to vbat need add offset */ + if (parallel_output_mode == POWER_SUPPLY_PL_OUTPUT_VBAT) + rc = smblib_set_charge_param(chg, &chg->param.fcc, val->intval + offset_ua); + else + rc = smblib_set_charge_param(chg, &chg->param.fcc, val->intval); + } +#else rc = smblib_set_charge_param(chg, &chg->param.fcc, val->intval + offset_ua); +#endif break; case POWER_SUPPLY_PROP_CURRENT_MAX: rc = smblib_set_icl_current(chg, val->intval); @@ -1505,130 +2322,944 @@ static int smb5_usb_main_prop_is_writeable(struct power_supply *psy, return rc; } -static const struct power_supply_desc usb_main_psy_desc = { - .name = "main", - .type = POWER_SUPPLY_TYPE_MAIN, - .properties = smb5_usb_main_props, - .num_properties = ARRAY_SIZE(smb5_usb_main_props), - .get_property = smb5_usb_main_get_prop, - .set_property = smb5_usb_main_set_prop, - .property_is_writeable = smb5_usb_main_prop_is_writeable, -}; - -static int smb5_init_usb_main_psy(struct smb5 *chip) +static const struct power_supply_desc usb_main_psy_desc = { + .name = "main", + .type = POWER_SUPPLY_TYPE_MAIN, + .properties = smb5_usb_main_props, + .num_properties = ARRAY_SIZE(smb5_usb_main_props), + .get_property = smb5_usb_main_get_prop, + .set_property = smb5_usb_main_set_prop, + .property_is_writeable = smb5_usb_main_prop_is_writeable, +}; + +static int smb5_init_usb_main_psy(struct smb5 *chip) +{ + struct power_supply_config usb_main_cfg = {}; + struct smb_charger *chg = &chip->chg; + + usb_main_cfg.drv_data = chip; + usb_main_cfg.of_node = chg->dev->of_node; + chg->usb_main_psy = devm_power_supply_register(chg->dev, + &usb_main_psy_desc, + &usb_main_cfg); + if (IS_ERR(chg->usb_main_psy)) { + pr_err("Couldn't register USB main power supply\n"); + return PTR_ERR(chg->usb_main_psy); + } + + return 0; +} + +/************************* + * DC PSY REGISTRATION * + *************************/ + +static enum power_supply_property smb5_dc_props[] = { + POWER_SUPPLY_PROP_INPUT_SUSPEND, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_MAX, + POWER_SUPPLY_PROP_VOLTAGE_MAX, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, + POWER_SUPPLY_PROP_REAL_TYPE, + POWER_SUPPLY_PROP_DC_RESET, +}; + +static int smb5_dc_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct smb5 *chip = power_supply_get_drvdata(psy); + struct smb_charger *chg = &chip->chg; + int rc = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_INPUT_SUSPEND: + val->intval = get_effective_result(chg->dc_suspend_votable); + break; + case POWER_SUPPLY_PROP_PRESENT: + rc = smblib_get_prop_dc_present(chg, val); + break; + case POWER_SUPPLY_PROP_ONLINE: + rc = smblib_get_prop_dc_online(chg, val); + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + rc = smblib_get_prop_dc_voltage_now(chg, val); + break; + case POWER_SUPPLY_PROP_CURRENT_MAX: + rc = smblib_get_prop_dc_current_max(chg, val); + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX: + rc = smblib_get_prop_dc_voltage_max(chg, val); + break; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + smb5_get_prop_input_voltage_regulation(chg, val); + break; + case POWER_SUPPLY_PROP_REAL_TYPE: + val->intval = POWER_SUPPLY_TYPE_WIPOWER; + break; + case POWER_SUPPLY_PROP_DC_RESET: + val->intval = 0; + break; +#endif +#ifndef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + rc = smblib_get_prop_voltage_wls_output(chg, val); + break; +#endif + default: + return -EINVAL; + } + if (rc < 0) { + pr_debug("Couldn't get prop %d rc = %d\n", psp, rc); + return -ENODATA; + } + return 0; +} + +static int smb5_dc_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct smb5 *chip = power_supply_get_drvdata(psy); + struct smb_charger *chg = &chip->chg; + int rc = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_INPUT_SUSPEND: + rc = vote(chg->dc_suspend_votable, WBC_VOTER, + (bool)val->intval, 0); + break; + case POWER_SUPPLY_PROP_CURRENT_MAX: + rc = smblib_set_prop_dc_current_max(chg, val); + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + rc = smblib_set_prop_voltage_wls_output(chg, val); + break; + case POWER_SUPPLY_PROP_DC_RESET: + rc = smblib_set_prop_dc_reset(chg); + break; + default: + return -EINVAL; + } + + return rc; +} + +static int smb5_dc_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + switch (psp) { + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_INPUT_SUSPEND: + case POWER_SUPPLY_PROP_CURRENT_MAX: +#endif + return 1; + default: + break; + } + + return 0; +} + +static const struct power_supply_desc dc_psy_desc = { + .name = "dc", + .type = POWER_SUPPLY_TYPE_WIRELESS, + .properties = smb5_dc_props, + .num_properties = ARRAY_SIZE(smb5_dc_props), + .get_property = smb5_dc_get_prop, + .set_property = smb5_dc_set_prop, + .property_is_writeable = smb5_dc_prop_is_writeable, +}; + +static int smb5_init_dc_psy(struct smb5 *chip) +{ + struct power_supply_config dc_cfg = {}; + struct smb_charger *chg = &chip->chg; + + dc_cfg.drv_data = chip; + dc_cfg.of_node = chg->dev->of_node; + chg->dc_psy = devm_power_supply_register(chg->dev, + &dc_psy_desc, + &dc_cfg); + if (IS_ERR(chg->dc_psy)) { + pr_err("Couldn't register USB power supply\n"); + return PTR_ERR(chg->dc_psy); + } + + return 0; +} + +#ifdef CONFIG_MACH_XIAOMI_NABU +static int smb5_get_prop_input_voltage_regulation(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + //msleep(200); + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, val); + + val->intval = 1000*val->intval;//IDT in mV + + return rc; +} + +static int smb5_get_prop_input_voltage_vrect(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + //msleep(200); + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT, val); + + val->intval = 1000*val->intval;//IDT in mV + + return rc; +} + +static int smb5_get_prop_rx_iout(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + //msleep(100); + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_RX_IOUT, val); + + val->intval = 1000*val->intval;//IDT in mV + + return rc; +} + +static int smb5_get_prop_wireless_signal(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, val); + + return rc; +} + +static int smb5_set_prop_input_voltage_regulation(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_set_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, val); + + return rc; +} + +static int smb5_get_prop_wirless_type(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc = 0; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + chg->wls_chip_psy = chg->idtp_psy; + else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_TX_ADAPTER, val); + + return rc; +} + +static int smb5_get_prop_reverse_pen_soc(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc = 0; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + chg->wls_chip_psy = chg->idtp_psy; + else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_REVERSE_PEN_SOC, val); + + return rc; +} + +/*set mode of DIV 2*/ +static int smb5_set_prop_div2_mode(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc; + + dev_info(chg->dev, "%s: set mode is = %d\n", + __func__, val->intval); + + chg->ln_psy = power_supply_get_by_name("lionsemi"); + //chg->halo_psy = power_supply_get_by_name("halo"); + if (chg->ln_psy) + chg->cp_chip_psy = chg->ln_psy; + /*else if (chg->halo_psy) + chg->cp_chip_psy = chg->halo_psy;*/ + else + return -EINVAL; + + if (chg->cp_chip_psy) + rc = power_supply_set_property(chg->cp_chip_psy, + POWER_SUPPLY_PROP_DIV_2_MODE, val); + + return rc; +} + +static int smb5_get_prop_div2_mode(struct smb_charger *chg, + union power_supply_propval *val) +{ + dev_info(chg->dev, "%s: get div2 mode\n", __func__); + + chg->ln_psy = power_supply_get_by_name("lionsemi"); + //chg->halo_psy = power_supply_get_by_name("halo"); + + if (chg->ln_psy) + chg->cp_chip_psy = chg->ln_psy; + /*else if (chg->halo_psy) + chg->cp_chip_psy = chg->halo_psy;*/ + else + return -EINVAL; + + if (chg->cp_chip_psy) { + power_supply_get_property(chg->cp_chip_psy, + POWER_SUPPLY_PROP_DIV_2_MODE, val); + dev_info(chg->dev, "%s: get mode is = %d\n", + __func__, val->intval); + } + + return 1; +} +static int smb5_set_prop_reverse_chg_mode(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc; + + dev_info(chg->dev, "%s: set mode is = %d\n", + __func__, val->intval); + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_set_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_REVERSE_CHG_MODE, val); + + return rc; +} + +static int smb5_set_prop_otg_mode(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc; + + dev_info(chg->dev, "%s: set mode is = %d\n", + __func__, val->intval); + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_set_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_OTG_STATE, val); + + return rc; +} + +static int smb5_get_prop_reverse_chg_mode(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) { + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_REVERSE_CHG_MODE, val); + dev_info(chg->dev, "%s: get mode is = %d\n", + __func__, val->intval); + } + + return rc; +} + +static int smb5_get_prop_wirless_chip_ok(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) { + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_CHIP_OK, val); + dev_info(chg->dev, "%s: get chip status is = %d\n", + __func__, val->intval); + } + + return rc; +} + +int smblib_enable_aicl(struct smb_charger *chg, int enable) +{ + int rc = 0; + u8 mask = 0; + u8 val = 0; + + mask = USBIN_AICL_EN_BIT; + val = enable?USBIN_AICL_EN_BIT:0; + + rc = smblib_masked_write(chg, USBIN_AICL_OPTIONS_CFG_REG, + mask, val); + if (rc < 0) { + dev_err(chg->dev, "Couldn't config AICL enable rc=%d\n", rc); + return rc; + } + return 0; + +} + +/************************* + * WIRELESS PSY REGISTRATION * + *************************/ + +static enum power_supply_property smb5_wireless_props[] = { + POWER_SUPPLY_PROP_WIRELESS_VERSION, + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT, + POWER_SUPPLY_PROP_RX_IOUT, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, + POWER_SUPPLY_PROP_SW_DISABLE_DC_EN, + POWER_SUPPLY_PROP_TX_ADAPTER, + POWER_SUPPLY_PROP_TX_MAC, + POWER_SUPPLY_PROP_PEN_MAC, + POWER_SUPPLY_PROP_REVERSE_PEN_SOC, + POWER_SUPPLY_PROP_BT_STATE, + POWER_SUPPLY_PROP_RX_CR, + POWER_SUPPLY_PROP_RX_CEP, + POWER_SUPPLY_PROP_DC_RESET, + POWER_SUPPLY_PROP_DIV_2_MODE, + POWER_SUPPLY_PROP_REVERSE_CHG_MODE, + POWER_SUPPLY_PROP_REVERSE_PEN_CHG_STATE, + POWER_SUPPLY_PROP_REVERSE_GPIO_STATE, + POWER_SUPPLY_PROP_AICL_ENABLE, + POWER_SUPPLY_PROP_OTG_STATE, + POWER_SUPPLY_PROP_WIRELESS_FW_VERSION, + POWER_SUPPLY_PROP_CHIP_OK, +}; + +static int smb5_wireless_set_prop(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct smb5 *chip = power_supply_get_drvdata(psy); + struct smb_charger *chg = &chip->chg; + int rc = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + dev_info(chg->dev, "set version=%d\n", val->intval); + break; + case POWER_SUPPLY_PROP_WIRELESS_WAKELOCK: + rc = smblib_set_prop_wireless_wakelock(chg, val); + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + smb5_set_prop_input_voltage_regulation(chg, val); + break; + case POWER_SUPPLY_PROP_WIRELESS_CP_EN: + smblib_set_wirless_cp_enable(chg, val); + break; + case POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN: + smblib_set_wirless_power_good_enable(chg, val); + break; + case POWER_SUPPLY_PROP_SW_DISABLE_DC_EN: + smblib_set_sw_disable_dc_en(chg, val); + break; + case POWER_SUPPLY_PROP_DC_RESET: + rc = smblib_set_prop_dc_reset(chg); + break; + case POWER_SUPPLY_PROP_DIV_2_MODE: + rc = smb5_set_prop_div2_mode(chg, val); + break; + case POWER_SUPPLY_PROP_TX_MAC: + smblib_set_prop_tx_mac(chg, val); + break; + case POWER_SUPPLY_PROP_PEN_MAC: + smblib_set_prop_pen_mac(chg, val); + break; + case POWER_SUPPLY_PROP_RX_CR: + smblib_set_prop_rx_cr(chg, val); + break; + case POWER_SUPPLY_PROP_RX_CEP: + smblib_set_prop_rx_cep(chg, val); + break; + case POWER_SUPPLY_PROP_BT_STATE: + smblib_set_prop_bt_state(chg, val); + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + rc = smb5_set_prop_reverse_chg_mode(chg, val); + break; + case POWER_SUPPLY_PROP_REVERSE_PEN_CHG_STATE: + chg->reverse_chg_state = val->intval; + pen_charge_state_notifier_call_chain(chg->reverse_chg_state == 4, NULL); + break; + case POWER_SUPPLY_PROP_AICL_ENABLE: + rc = smblib_enable_aicl(chg, val->intval); + break; + case POWER_SUPPLY_PROP_REVERSE_GPIO_STATE: + chg->reverse_gpio_state = val->intval; + break; + case POWER_SUPPLY_PROP_OTG_STATE: + rc = smb5_set_prop_otg_mode(chg, val); + break; + default: + return -EINVAL; + } + + return rc; +} + +static int smb5_wireless_get_prop(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct smb5 *chip = power_supply_get_drvdata(psy); + struct smb_charger *chg = &chip->chg; + int rc = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + rc = smblib_get_prop_wireless_version(chg, val); + break; + case POWER_SUPPLY_PROP_WIRELESS_FW_VERSION: + rc = smblib_get_prop_wireless_fw_version(chg, val); + break; + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + smb5_get_prop_wireless_signal(chg, val); + break; + case POWER_SUPPLY_PROP_WIRELESS_WAKELOCK: + val->intval = 1; + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + smb5_get_prop_input_voltage_regulation(chg, val); + break; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT: + smb5_get_prop_input_voltage_vrect(chg, val); + break; + case POWER_SUPPLY_PROP_RX_IOUT: + smb5_get_prop_rx_iout(chg, val); + break; + case POWER_SUPPLY_PROP_WIRELESS_CP_EN: + if (chg->wireless_bq) + val->intval = chg->en_bq_flag; + else + val->intval = chg->flag_dc_present; + break; + case POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN: + val->intval = chg->power_good_en; + break; + case POWER_SUPPLY_PROP_TX_ADAPTER: + smb5_get_prop_wirless_type(chg, val); + break; + case POWER_SUPPLY_PROP_REVERSE_PEN_SOC: + smb5_get_prop_reverse_pen_soc(chg, val); + break; + case POWER_SUPPLY_PROP_DC_RESET: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_DIV_2_MODE: + smb5_get_prop_div2_mode(chg, val); + break; + case POWER_SUPPLY_PROP_TX_MAC: + val->int64val = chg->tx_bt_mac; + break; + case POWER_SUPPLY_PROP_PEN_MAC: + val->int64val = chg->pen_bt_mac; + break; + case POWER_SUPPLY_PROP_RX_CR: + val->int64val = chg->rpp; + break; + case POWER_SUPPLY_PROP_RX_CEP: + val->int64val = chg->cep; + break; + case POWER_SUPPLY_PROP_BT_STATE: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_SW_DISABLE_DC_EN: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + smb5_get_prop_reverse_chg_mode(chg, val); + break; + case POWER_SUPPLY_PROP_REVERSE_PEN_CHG_STATE: + val->intval = chg->reverse_chg_state; + break; + case POWER_SUPPLY_PROP_REVERSE_GPIO_STATE: + val->intval = chg->reverse_gpio_state; + break; + case POWER_SUPPLY_PROP_AICL_ENABLE: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_CHIP_OK: + smb5_get_prop_wirless_chip_ok(chg, val); + break; + case POWER_SUPPLY_PROP_OTG_STATE: + val->intval = 0; + break; + + default: + return -EINVAL; + } + if (rc < 0) { + pr_debug("Couldn't get prop %d rc = %d\n", psp, rc); + return -ENODATA; + } + return 0; +} + +static int smb5_wireless_prop_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + switch (psp) { + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + case POWER_SUPPLY_PROP_WIRELESS_WAKELOCK: + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + case POWER_SUPPLY_PROP_WIRELESS_CP_EN: + case POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN: + case POWER_SUPPLY_PROP_SW_DISABLE_DC_EN: + case POWER_SUPPLY_PROP_RX_CR: + case POWER_SUPPLY_PROP_RX_CEP: + case POWER_SUPPLY_PROP_TX_MAC: + case POWER_SUPPLY_PROP_PEN_MAC: + case POWER_SUPPLY_PROP_BT_STATE: + case POWER_SUPPLY_PROP_DIV_2_MODE: + case POWER_SUPPLY_PROP_REVERSE_CHG_MODE: + case POWER_SUPPLY_PROP_REVERSE_PEN_CHG_STATE: + case POWER_SUPPLY_PROP_CURRENT_MAX: + return 1; + default: + break; + } + + return 0; +} + +static const struct power_supply_desc wireless_psy_desc = { + .name = "wireless", + .type = POWER_SUPPLY_TYPE_WIRELESS, + .properties = smb5_wireless_props, + .num_properties = ARRAY_SIZE(smb5_wireless_props), + .get_property = smb5_wireless_get_prop, + .set_property = smb5_wireless_set_prop, + .property_is_writeable = smb5_wireless_prop_is_writeable, +}; + +static int smb5_init_wireless_psy(struct smb5 *chip) +{ + struct power_supply_config wireless_cfg = {}; + struct smb_charger *chg = &chip->chg; + + wireless_cfg.drv_data = chip; + wireless_cfg.of_node = chg->dev->of_node; + chg->wireless_psy = power_supply_register(chg->dev, + &wireless_psy_desc, + &wireless_cfg); + if (IS_ERR(chg->wireless_psy)) { + pr_err("Couldn't register wireless power supply\n"); + return PTR_ERR(chg->wireless_psy); + } + + return 0; +} +#endif + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +static int smb5_get_prop_wireless_signal(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + +/* + if (!chg->idtp_psy) { + chg->idtp_psy = power_supply_get_by_name("idt"); + if (!chg->idtp_psy) + return -EINVAL; + } +*/ + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + chg->wls_chip_psy = chg->idtp_psy; + else { + chg->wip_psy = power_supply_get_by_name("rx1618"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, val); + + return rc; +} + +static int smb5_set_prop_input_voltage_regulation(struct smb_charger *chg, + const union power_supply_propval *val) { - struct power_supply_config usb_main_cfg = {}; - struct smb_charger *chg = &chip->chg; + int rc; - usb_main_cfg.drv_data = chip; - usb_main_cfg.of_node = chg->dev->of_node; - chg->usb_main_psy = devm_power_supply_register(chg->dev, - &usb_main_psy_desc, - &usb_main_cfg); - if (IS_ERR(chg->usb_main_psy)) { - pr_err("Couldn't register USB main power supply\n"); - return PTR_ERR(chg->usb_main_psy); +/* + if (!chg->idtp_psy) { + chg->idtp_psy = power_supply_get_by_name("idt"); + if (!chg->idtp_psy) + return -EINVAL; + } +*/ + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + chg->wls_chip_psy = chg->idtp_psy; + else { + chg->wip_psy = power_supply_get_by_name("rx1618"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; } - return 0; + if (chg->wls_chip_psy) + rc = power_supply_set_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, val); + + return rc; +} + +static int smb5_get_prop_wirless_type(struct smb_charger *chg, + union power_supply_propval *val) +{ + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + power_supply_get_property(chg->idtp_psy, + POWER_SUPPLY_PROP_TX_ADAPTER, val); + + return 1; } /************************* - * DC PSY REGISTRATION * + * WIRELESS PSY REGISTRATION * *************************/ -static enum power_supply_property smb5_dc_props[] = { - POWER_SUPPLY_PROP_INPUT_SUSPEND, - POWER_SUPPLY_PROP_PRESENT, - POWER_SUPPLY_PROP_ONLINE, - POWER_SUPPLY_PROP_VOLTAGE_NOW, - POWER_SUPPLY_PROP_CURRENT_MAX, - POWER_SUPPLY_PROP_VOLTAGE_MAX, +static enum power_supply_property smb5_wireless_props[] = { + POWER_SUPPLY_PROP_WIRELESS_VERSION, + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, - POWER_SUPPLY_PROP_REAL_TYPE, - POWER_SUPPLY_PROP_DC_RESET, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, + POWER_SUPPLY_PROP_TX_ADAPTER, }; -static int smb5_dc_get_prop(struct power_supply *psy, +static int smb5_wireless_set_prop(struct power_supply *psy, enum power_supply_property psp, - union power_supply_propval *val) + const union power_supply_propval *val) { struct smb5 *chip = power_supply_get_drvdata(psy); struct smb_charger *chg = &chip->chg; int rc = 0; switch (psp) { - case POWER_SUPPLY_PROP_INPUT_SUSPEND: - val->intval = get_effective_result(chg->dc_suspend_votable); - break; - case POWER_SUPPLY_PROP_PRESENT: - rc = smblib_get_prop_dc_present(chg, val); - break; - case POWER_SUPPLY_PROP_ONLINE: - rc = smblib_get_prop_dc_online(chg, val); - break; - case POWER_SUPPLY_PROP_VOLTAGE_NOW: - rc = smblib_get_prop_dc_voltage_now(chg, val); - break; - case POWER_SUPPLY_PROP_CURRENT_MAX: - rc = smblib_get_prop_dc_current_max(chg, val); + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + dev_info(chg->dev, "set version=%d\n", val->intval); break; - case POWER_SUPPLY_PROP_VOLTAGE_MAX: - rc = smblib_get_prop_dc_voltage_max(chg, val); + case POWER_SUPPLY_PROP_WIRELESS_WAKELOCK: + rc = smblib_set_prop_wireless_wakelock(chg, val); break; - case POWER_SUPPLY_PROP_REAL_TYPE: - val->intval = POWER_SUPPLY_TYPE_WIPOWER; + case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + smb5_set_prop_input_voltage_regulation(chg, val); break; - case POWER_SUPPLY_PROP_DC_RESET: - val->intval = 0; + case POWER_SUPPLY_PROP_WIRELESS_CP_EN: + smblib_set_wirless_cp_enable(chg, val); break; - case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: - rc = smblib_get_prop_voltage_wls_output(chg, val); + case POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN: + smblib_set_wirless_power_good_enable(chg, val); break; default: return -EINVAL; } - if (rc < 0) { - pr_debug("Couldn't get prop %d rc = %d\n", psp, rc); - return -ENODATA; - } - return 0; + + return rc; } -static int smb5_dc_set_prop(struct power_supply *psy, +static int smb5_wireless_get_prop(struct power_supply *psy, enum power_supply_property psp, - const union power_supply_propval *val) + union power_supply_propval *val) { struct smb5 *chip = power_supply_get_drvdata(psy); struct smb_charger *chg = &chip->chg; int rc = 0; switch (psp) { - case POWER_SUPPLY_PROP_INPUT_SUSPEND: - rc = vote(chg->dc_suspend_votable, WBC_VOTER, - (bool)val->intval, 0); + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + rc = smblib_get_prop_wireless_version(chg, val); break; - case POWER_SUPPLY_PROP_CURRENT_MAX: - rc = smblib_set_prop_dc_current_max(chg, val); + case POWER_SUPPLY_PROP_SIGNAL_STRENGTH: + smb5_get_prop_wireless_signal(chg, val); + break; + case POWER_SUPPLY_PROP_WIRELESS_WAKELOCK: + val->intval = 1; break; case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: - rc = smblib_set_prop_voltage_wls_output(chg, val); + smb5_get_prop_input_voltage_regulation(chg, val); break; - case POWER_SUPPLY_PROP_DC_RESET: - rc = smblib_set_prop_dc_reset(chg); + case POWER_SUPPLY_PROP_WIRELESS_CP_EN: + val->intval = chg->flag_dc_present; + break; + case POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN: + val->intval = chg->power_good_en; + break; + case POWER_SUPPLY_PROP_TX_ADAPTER: + smb5_get_prop_wirless_type(chg, val); break; default: return -EINVAL; } - - return rc; + if (rc < 0) { + pr_debug("Couldn't get prop %d rc = %d\n", psp, rc); + return -ENODATA; + } + return 0; } -static int smb5_dc_prop_is_writeable(struct power_supply *psy, +static int smb5_wireless_prop_is_writeable(struct power_supply *psy, enum power_supply_property psp) { switch (psp) { + case POWER_SUPPLY_PROP_WIRELESS_VERSION: + case POWER_SUPPLY_PROP_WIRELESS_WAKELOCK: case POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION: + case POWER_SUPPLY_PROP_WIRELESS_CP_EN: + case POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN: return 1; default: break; @@ -1637,39 +3268,44 @@ static int smb5_dc_prop_is_writeable(struct power_supply *psy, return 0; } -static const struct power_supply_desc dc_psy_desc = { - .name = "dc", +static const struct power_supply_desc wireless_psy_desc = { + .name = "wireless", .type = POWER_SUPPLY_TYPE_WIRELESS, - .properties = smb5_dc_props, - .num_properties = ARRAY_SIZE(smb5_dc_props), - .get_property = smb5_dc_get_prop, - .set_property = smb5_dc_set_prop, - .property_is_writeable = smb5_dc_prop_is_writeable, + .properties = smb5_wireless_props, + .num_properties = ARRAY_SIZE(smb5_wireless_props), + .get_property = smb5_wireless_get_prop, + .set_property = smb5_wireless_set_prop, + .property_is_writeable = smb5_wireless_prop_is_writeable, }; -static int smb5_init_dc_psy(struct smb5 *chip) +static int smb5_init_wireless_psy(struct smb5 *chip) { - struct power_supply_config dc_cfg = {}; + struct power_supply_config wireless_cfg = {}; struct smb_charger *chg = &chip->chg; - dc_cfg.drv_data = chip; - dc_cfg.of_node = chg->dev->of_node; - chg->dc_psy = devm_power_supply_register(chg->dev, - &dc_psy_desc, - &dc_cfg); - if (IS_ERR(chg->dc_psy)) { - pr_err("Couldn't register USB power supply\n"); - return PTR_ERR(chg->dc_psy); + wireless_cfg.drv_data = chip; + wireless_cfg.of_node = chg->dev->of_node; + chg->wireless_psy = power_supply_register(chg->dev, + &wireless_psy_desc, + &wireless_cfg); + if (IS_ERR(chg->wireless_psy)) { + pr_err("Couldn't register wireless power supply\n"); + return PTR_ERR(chg->wireless_psy); } return 0; } +#endif /************************* * BATT PSY REGISTRATION * *************************/ static enum power_supply_property smb5_batt_props[] = { POWER_SUPPLY_PROP_INPUT_SUSPEND, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_LIQUID_DETECTION, + POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED, +#endif POWER_SUPPLY_PROP_STATUS, POWER_SUPPLY_PROP_HEALTH, POWER_SUPPLY_PROP_PRESENT, @@ -1704,9 +3340,18 @@ static enum power_supply_property smb5_batt_props[] = { POWER_SUPPLY_PROP_CHARGE_FULL, POWER_SUPPLY_PROP_FORCE_RECHARGE, POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_CAPACITY_LEVEL, +#endif POWER_SUPPLY_PROP_TIME_TO_FULL_NOW, POWER_SUPPLY_PROP_FCC_STEPPER_ENABLE, POWER_SUPPLY_PROP_CHARGING_ENABLED, +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, +#endif + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, +#endif }; #define DEBUG_ACCESSORY_TEMP_DECIDEGC 250 @@ -1733,6 +3378,11 @@ static int smb5_batt_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_CHARGE_TYPE: rc = smblib_get_prop_batt_charge_type(chg, val); break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_CAPACITY_LEVEL: + rc = smblib_get_prop_batt_capacity_level(chg, val); + break; +#endif case POWER_SUPPLY_PROP_CAPACITY: rc = smblib_get_prop_batt_capacity(chg, val); break; @@ -1742,6 +3392,11 @@ static int smb5_batt_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX: rc = smblib_get_prop_system_temp_level_max(chg, val); break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_DC_THERMAL_LEVELS: + rc = smblib_get_prop_dc_temp_level(chg, val); + break; +#endif case POWER_SUPPLY_PROP_CHARGER_TEMP: rc = smblib_get_prop_charger_temp(chg, val); break; @@ -1775,8 +3430,10 @@ static int smb5_batt_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_CURRENT_NOW: rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_CURRENT_NOW, val); +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (!rc) val->intval *= (-1); +#endif break; case POWER_SUPPLY_PROP_CURRENT_QNOVO: val->intval = get_client_vote_locked(chg->fcc_votable, @@ -1800,7 +3457,11 @@ static int smb5_batt_get_prop(struct power_supply *psy, POWER_SUPPLY_PROP_TEMP, val); break; case POWER_SUPPLY_PROP_TECHNOLOGY: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + val->intval = POWER_SUPPLY_TECHNOLOGY_LIPO; +#else val->intval = POWER_SUPPLY_TECHNOLOGY_LION; +#endif break; case POWER_SUPPLY_PROP_CHARGE_DONE: rc = smblib_get_prop_batt_charge_done(chg, val); @@ -1822,6 +3483,11 @@ static int smb5_batt_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_DP_DM: val->intval = chg->pulse_cnt; break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_DP_DM_BQ: + val->intval = chg->pulse_cnt; + break; +#endif case POWER_SUPPLY_PROP_RERUN_AICL: val->intval = 0; break; @@ -1857,6 +3523,31 @@ static int smb5_batt_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_FCC_STEPPER_ENABLE: val->intval = chg->fcc_stepper_enable; break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_LIQUID_DETECTION: + if (chg->support_liquid == true) + rc = smblib_get_prop_liquid_status(chg, val); + else + val->intval = 0; + break; + case POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED: + val->intval = chg->dynamic_fv_enabled; + break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED: + rc = smblib_get_prop_battery_charging_enabled(chg, val); + break; + case POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED: + rc = smblib_get_prop_battery_charging_limited(chg, val); + break; + case POWER_SUPPLY_PROP_SLOWLY_CHARGING: + rc = smblib_get_prop_battery_slowly_charging(chg, val); + break; + case POWER_SUPPLY_PROP_BQ_INPUT_SUSPEND: + rc = smblib_get_prop_battery_bq_input_suspend(chg, val); + break; +#endif +#endif default: pr_err("batt power supply prop %d not supported\n", psp); return -EINVAL; @@ -1876,6 +3567,9 @@ static int smb5_batt_set_prop(struct power_supply *psy, { int rc = 0; struct smb_charger *chg = power_supply_get_drvdata(psy); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + union power_supply_propval pval = {0,}; +#endif switch (prop) { case POWER_SUPPLY_PROP_STATUS: @@ -1885,8 +3579,20 @@ static int smb5_batt_set_prop(struct power_supply *psy, rc = smblib_set_prop_input_suspend(chg, val); break; case POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (disable_thermal) { + smblib_set_prop_system_temp_level(chg, &pval); + break; + } +#endif rc = smblib_set_prop_system_temp_level(chg, val); break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_DC_THERMAL_LEVELS: + if (chg->support_wireless) + rc = smblib_set_prop_dc_temp_level(chg, val); + break; +#endif case POWER_SUPPLY_PROP_CAPACITY: rc = smblib_set_prop_batt_capacity(chg, val); break; @@ -1908,6 +3614,11 @@ static int smb5_batt_set_prop(struct power_supply *psy, chg->batt_profile_fcc_ua = val->intval; vote(chg->fcc_votable, BATT_PROFILE_VOTER, true, val->intval); break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT: + smb5_config_iterm(chg, val->intval, 50); + break; +#endif case POWER_SUPPLY_PROP_CURRENT_QNOVO: vote(chg->pl_disable_votable, PL_QNOVO_VOTER, val->intval != -EINVAL && val->intval < 2000000, 0); @@ -1939,6 +3650,12 @@ static int smb5_batt_set_prop(struct power_supply *psy, if (!chg->flash_active) rc = smblib_dp_dm(chg, val->intval); break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_DP_DM_BQ: + if (chg->use_bq_pump) + rc = smblib_dp_dm_bq(chg, val->intval); + break; +#endif case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED: rc = smblib_set_prop_input_current_limited(chg, val); break; @@ -1958,9 +3675,53 @@ static int smb5_batt_set_prop(struct power_supply *psy, vote(chg->chg_disable_votable, FORCE_RECHARGE_VOTER, false, 0); break; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_LIQUID_DETECTION: + chg->lpd_status = val->intval; + power_supply_changed(chg->batt_psy); + break; + case POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED: + chg->dynamic_fv_enabled = !!val->intval; + break; +#endif case POWER_SUPPLY_PROP_FCC_STEPPER_ENABLE: chg->fcc_stepper_enable = val->intval; break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED: + if (chg->use_bq_pump) { + if (val->intval == 0) + vote(chg->usb_icl_votable, MAIN_CHG_VOTER, + true, MAIN_CHARGER_STOP_ICL); + else + vote(chg->usb_icl_votable, MAIN_CHG_VOTER, + false, 0); + rerun_election(chg->usb_icl_votable); + } + break; + case POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED: + if (chg->use_bq_pump) { + if (val->intval == 0) { + vote(chg->usb_icl_votable, MAIN_CHG_VOTER, + false, MAIN_CHARGER_ICL); + } else { + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3) + vote(chg->usb_icl_votable, MAIN_CHG_VOTER, + true, QC3_CHARGER_ICL); + else if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) + vote(chg->usb_icl_votable, MAIN_CHG_VOTER, + true, QC3P5_CHARGER_ICL); + else + vote(chg->usb_icl_votable, MAIN_CHG_VOTER, + true, MAIN_CHARGER_ICL); + } + rerun_election(chg->usb_icl_votable); + } + break; + case POWER_SUPPLY_PROP_SLOWLY_CHARGING: + rc = smblib_set_prop_battery_slowly_charging(chg, val); + break; +#endif default: rc = -EINVAL; } @@ -1979,10 +3740,23 @@ static int smb5_batt_prop_is_writeable(struct power_supply *psy, case POWER_SUPPLY_PROP_CAPACITY: case POWER_SUPPLY_PROP_PARALLEL_DISABLE: case POWER_SUPPLY_PROP_DP_DM: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_DP_DM_BQ: +#endif case POWER_SUPPLY_PROP_RERUN_AICL: case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED: case POWER_SUPPLY_PROP_STEP_CHARGING_ENABLED: case POWER_SUPPLY_PROP_DIE_HEALTH: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case POWER_SUPPLY_PROP_DC_THERMAL_LEVELS: + case POWER_SUPPLY_PROP_LIQUID_DETECTION: + case POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED: +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED: + case POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED: + case POWER_SUPPLY_PROP_SLOWLY_CHARGING: +#endif return 1; default: break; @@ -2530,10 +4304,23 @@ static int smb5_configure_iterm_thresholds_adc(struct smb5 *chip) max_limit_ma); raw_hi_thresh = sign_extend32(raw_hi_thresh, 15); buf = (u8 *)&raw_hi_thresh; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_write(chg, CHGR_ADC_ITERM_UP_THD_MSB_REG, + buf[1]); + if (rc < 0) { + dev_err(chg->dev, "Couldn't set term MSB rc=%d\n", + rc); + return rc; + } + + rc = smblib_write(chg, CHGR_ADC_ITERM_UP_THD_LSB_REG, + buf[0]); +#else raw_hi_thresh = buf[1] | (buf[0] << 8); rc = smblib_batch_write(chg, CHGR_ADC_ITERM_UP_THD_MSB_REG, (u8 *)&raw_hi_thresh, 2); +#endif if (rc < 0) { dev_err(chg->dev, "Couldn't configure ITERM threshold HIGH rc=%d\n", rc); @@ -2678,6 +4465,9 @@ static int smb5_init_hw(struct smb5 *chip) if (chip->dt.batt_profile_fv_uv < 0) smblib_get_charge_param(chg, &chg->param.fv, &chg->batt_profile_fv_uv); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->batt_profile_fv_uv = chip->dt.batt_profile_fv_uv; +#endif smblib_get_charge_param(chg, &chg->param.usb_icl, &chg->default_icl_ua); @@ -2688,6 +4478,14 @@ static int smb5_init_hw(struct smb5 *chip) &chg->default_aicl_cont_threshold_mv); chg->aicl_cont_threshold_mv = chg->default_aicl_cont_threshold_mv; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (chip->dt.dc_icl_ua < 0) { + smblib_get_charge_param(chg, &chg->param.dc_icl, + &chip->dt.dc_icl_ua); + chip->dt.dc_icl_ua = smblib_change_psns_to_curr(chg, chip->dt.dc_icl_ua); + } +#endif + if (chg->charger_temp_max == -EINVAL) { rc = smblib_get_thermal_threshold(chg, DIE_REG_H_THRESHOLD_MSB_REG, @@ -2819,12 +4617,25 @@ static int smb5_init_hw(struct smb5 *chip) chip->dt.batt_profile_fcc_ua > 0, chip->dt.batt_profile_fcc_ua); vote(chg->fv_votable, HW_LIMIT_VOTER, chip->dt.batt_profile_fv_uv > 0, chip->dt.batt_profile_fv_uv); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + vote(chg->fcc_votable, BATT_VERIFY_VOTER, + chip->dt.batt_unverify_fcc_ua > 0, chip->dt.batt_unverify_fcc_ua); + vote(chg->fv_votable, BATT_PROFILE_VOTER, + chg->batt_profile_fv_uv > 0, chg->batt_profile_fv_uv); + + /* if support ffc, default vfloat set to 4.4V, only fast charge need override to 4.45V */ + if (chg->support_ffc) + vote(chg->fv_votable, NON_FFC_VFLOAT_VOTER, + true, NON_FFC_VFLOAT_UV); +#endif vote(chg->fcc_votable, BATT_PROFILE_VOTER, chg->batt_profile_fcc_ua > 0, chg->batt_profile_fcc_ua); +#if !defined(CONFIG_MACH_XIAOMI_VAYU) && !defined(CONFIG_MACH_XIAOMI_NABU) vote(chg->fv_votable, BATT_PROFILE_VOTER, chg->batt_profile_fv_uv > 0, chg->batt_profile_fv_uv); +#endif /* Some h/w limit maximum supported ICL */ vote(chg->usb_icl_votable, HW_LIMIT_VOTER, @@ -2835,6 +4646,23 @@ static int smb5_init_hw(struct smb5 *chip) if (rc < 0) return rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + /* set dc icl by default voter */ + vote(chg->dc_icl_votable, + DCIN_ADAPTER_VOTER, true, chip->dt.dc_icl_ua); +#endif + + /* Disable DC Input missing poller function */ + rc = smblib_masked_write(chg, DCIN_LOAD_CFG_REG, + INPUT_MISS_POLL_EN_BIT, 0); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't disable DC Input missing poller rc=%d\n", rc); + return rc; + } +#endif + /* * AICL configuration: enable aicl and aicl rerun and based on DT * configuration enable/disable ADB based AICL and Suspend on collapse. @@ -2878,6 +4706,14 @@ static int smb5_init_hw(struct smb5 *chip) return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_masked_write(chg, DCIN_BASE + 0x65 , BIT(5), 0); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't configure IMP rc=%d\n", rc); + } +#endif + /* enable the charging path */ rc = vote(chg->chg_disable_votable, DEFAULT_VOTER, false, 0); if (rc < 0) { @@ -2914,6 +4750,9 @@ static int smb5_init_hw(struct smb5 *chip) rc = smblib_masked_write(chg, WD_CFG_REG, WATCHDOG_TRIGGER_AFP_EN_BIT | WDOG_TIMER_EN_ON_PLUGIN_BIT | +#ifdef CONFIG_MACH_XIAOMI_SM8150 + WDOG_TIMER_EN_BIT | +#endif BARK_WDOG_INT_EN_BIT, val); if (rc < 0) { pr_err("Couldn't configue WD config rc=%d\n", rc); @@ -2948,7 +4787,11 @@ static int smb5_init_hw(struct smb5 *chip) chg->float_cfg = val; /* Update float charger setting and set DCD timeout 300ms */ rc = smblib_masked_write(chg, USBIN_OPTIONS_2_CFG_REG, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + FLOAT_OPTIONS_MASK, val); +#else FLOAT_OPTIONS_MASK | DCD_TIMEOUT_SEL_BIT, val); +#endif if (rc < 0) { dev_err(chg->dev, "Couldn't change float charger setting rc=%d\n", rc); @@ -2989,8 +4832,13 @@ static int smb5_init_hw(struct smb5 *chip) return rc; } +#ifndef CONFIG_MACH_XIAOMI_NABU rc = smblib_write(chg, CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG, FAST_CHARGE_SAFETY_TIMER_768_MIN); +#else + rc = smblib_write(chg, CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG, + FAST_CHARGE_SAFETY_TIMER_1536_MIN); +#endif if (rc < 0) { dev_err(chg->dev, "Couldn't set CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG rc=%d\n", rc); @@ -3083,6 +4931,15 @@ static int smb5_init_hw(struct smb5 *chip) } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_masked_write(chg, TYPE_C_DEBUG_ACC_SNK_CFG, 0x1F, 0x07); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure TYPE_C_DEBUG_ACC_SNK_CFG rc=%d\n", + rc); + return rc; + } +#endif + if (chg->smb_pull_up != -EINVAL) { rc = smb5_configure_internal_pull(chg, SMB_THERM, get_valid_pullup(chg->smb_pull_up)); @@ -3142,10 +4999,22 @@ static int smb5_determine_initial_status(struct smb5 *chip) } chg->early_usb_attach = val.intval; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + rc = smblib_get_prop_dc_present(chg, &val); + if (rc < 0) { + pr_err("Couldn't get usb present rc=%d\n", rc); + return rc; + } + chg->early_dc_attach = val.intval; +#endif + if (chg->bms_psy) smblib_suspend_on_debug_battery(chg); usb_plugin_irq_handler(0, &irq_data); +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + dc_plugin_irq_handler(0, &irq_data); +#endif typec_attach_detach_irq_handler(0, &irq_data); typec_state_change_irq_handler(0, &irq_data); usb_source_change_irq_handler(0, &irq_data); @@ -3226,7 +5095,9 @@ static struct smb_irq_info smb5_irqs[] = { [BAT_TEMP_IRQ] = { .name = "bat-temp", .handler = batt_temp_changed_irq_handler, +#ifndef CONFIG_MACH_XIAOMI_SM8150 .wake = true, +#endif }, [ALL_CHNL_CONV_DONE_IRQ] = { .name = "all-chnl-conv-done", @@ -3296,7 +5167,11 @@ static struct smb_irq_info smb5_irqs[] = { }, [DCIN_UV_IRQ] = { .name = "dcin-uv", +#ifdef CONFIG_MACH_XIAOMI_SM8150 + .handler = dcin_uv_handler, +#else .handler = dcin_uv_irq_handler, +#endif .wake = true, }, [DCIN_OV_IRQ] = { @@ -3323,7 +5198,9 @@ static struct smb_irq_info smb5_irqs[] = { [TYPEC_OR_RID_DETECTION_CHANGE_IRQ] = { .name = "typec-or-rid-detect-change", .handler = typec_or_rid_detection_change_irq_handler, +#ifndef CONFIG_MACH_XIAOMI_SM8150 .wake = true, +#endif }, [TYPEC_VPD_DETECT_IRQ] = { .name = "typec-vpd-detect", @@ -3356,7 +5233,11 @@ static struct smb_irq_info smb5_irqs[] = { [WDOG_SNARL_IRQ] = { .name = "wdog-snarl", .handler = wdog_snarl_irq_handler, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + .wake = false, +#else .wake = true, +#endif }, [WDOG_BARK_IRQ] = { .name = "wdog-bark", @@ -3501,6 +5382,18 @@ static int smb5_request_interrupts(struct smb5 *chip) } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /*enable batt_temp irq when plugin usb poweron charging*/ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->irq_info[BAT_TEMP_IRQ].irq && (chg->early_usb_attach || chg->early_dc_attach)) { +#else + if (chg->irq_info[BAT_TEMP_IRQ].irq && (chg->early_usb_attach)) { +#endif + enable_irq_wake(chg->irq_info[BAT_TEMP_IRQ].irq); + chg->batt_temp_irq_enabled = true; + } +#endif + vote(chg->limited_irq_disable_votable, CHARGER_TYPE_VOTER, true, 0); vote(chg->hdc_irq_disable_votable, CHARGER_TYPE_VOTER, true, 0); @@ -3642,6 +5535,14 @@ static int smb5_show_charger_status(struct smb5 *chip) return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +struct usbpd *smb_get_usbpd(void) +{ + return __smbchg->pd; +} +EXPORT_SYMBOL(smb_get_usbpd); +#endif + static int smb5_probe(struct platform_device *pdev) { struct smb5 *chip; @@ -3658,11 +5559,21 @@ static int smb5_probe(struct platform_device *pdev) chg->pd_disabled = &__pd_disabled; chg->weak_chg_icl_ua = &__weak_chg_icl_ua; chg->mode = PARALLEL_MASTER; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->apdo_max = 0; +#endif chg->irq_info = smb5_irqs; chg->die_health = -EINVAL; chg->connector_health = -EINVAL; chg->otg_present = false; chg->main_fcc_max = -EINVAL; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + chg->fake_dc_on = false; +#endif + chg->support_liquid = false; + chg->init_once = false; +#endif mutex_init(&chg->adc_lock); chg->regmap = dev_get_regmap(chg->dev->parent, NULL); @@ -3684,12 +5595,22 @@ static int smb5_probe(struct platform_device *pdev) return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) + __smbchg = chg; +#endif + if (alarmtimer_get_rtcdev()) alarm_init(&chg->lpd_recheck_timer, ALARM_REALTIME, smblib_lpd_recheck_timer); else return -EPROBE_DEFER; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* wakeup init should be done at the beginning of smb5_probe */ + device_init_wakeup(chg->dev, true); +#endif + rc = smblib_init(chg); if (rc < 0) { pr_err("Smblib_init failed rc=%d\n", rc); @@ -3812,12 +5733,30 @@ static int smb5_probe(struct platform_device *pdev) goto cleanup; } +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + rc = smb5_init_wireless_psy(chip); + if (rc < 0) { + pr_err("Couldn't initialize wireless psy rc=%d\n", rc); + goto cleanup; + } +#endif + rc = smb5_request_interrupts(chip); if (rc < 0) { pr_err("Couldn't request interrupts rc=%d\n", rc); goto cleanup; } +#ifdef CONFIG_MACH_XIAOMI_NABU + if (chg->support_wireless) { + rc = smb5_init_wireless_psy(chip); + if (rc < 0) { + pr_err("Couldn't initialize wireless psy rc=%d\n", rc); + goto cleanup; + } + } +#endif + rc = smb5_post_init(chip); if (rc < 0) { pr_err("Failed in post init rc=%d\n", rc); @@ -3832,12 +5771,17 @@ static int smb5_probe(struct platform_device *pdev) goto free_irq; } +#ifndef CONFIG_MACH_XIAOMI_SM8150 device_init_wakeup(chg->dev, true); +#endif if (chg->dcin_uusb_over_gpio_en && gpio_is_valid(chg->micro_usb_gpio)) smb_micro_usb_irq_handler(chg->micro_usb_irq, chg); pr_info("QPNP SMB5 probed successfully\n"); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + smblib_support_liquid_feature(chg); +#endif return rc; @@ -3878,6 +5822,11 @@ static void smb5_shutdown(struct platform_device *pdev) smblib_masked_write(chg, TYPE_C_MODE_CFG_REG, TYPEC_POWER_ROLE_CMD_MASK, EN_SNK_ONLY_BIT); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /*fix PD bug.Set 0x1360 = 0x0c when shutdown*/ + smblib_write(chg, USBIN_ADAPTER_ALLOW_CFG_REG, USBIN_ADAPTER_ALLOW_5V_TO_12V); +#endif + /* force enable and rerun APSD */ smblib_apsd_enable(chg, true); smblib_hvdcp_exit_config(chg); diff --git a/drivers/power/supply/qcom/smb1390-charger.c b/drivers/power/supply/qcom/smb1390-charger.c index f8fd9dbcdd63..ffd0ba084261 100644 --- a/drivers/power/supply/qcom/smb1390-charger.c +++ b/drivers/power/supply/qcom/smb1390-charger.c @@ -87,6 +87,9 @@ #define ILIM_VOTER "ILIM_VOTER" #define FCC_VOTER "FCC_VOTER" #define ICL_VOTER "ICL_VOTER" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define ICL_CHANGE_VOTER "ICL_CHANGE_VOTER" +#endif #define TAPER_END_VOTER "TAPER_END_VOTER" #define WIRELESS_VOTER "WIRELESS_VOTER" #define SRC_VOTER "SRC_VOTER" @@ -139,6 +142,9 @@ struct smb1390 { int irqs[NUM_IRQS]; bool status_change_running; bool taper_work_running; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool taper_early_trigger; +#endif struct smb1390_iio iio; int irq_status; int taper_entry_fv; @@ -343,6 +349,22 @@ static ssize_t stat2_show(struct class *c, struct class_attribute *attr, } static CLASS_ATTR_RO(stat2); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static ssize_t model_name_show(struct class *c, struct class_attribute *attr, + char *buf) +{ + struct smb1390 *chip = container_of(c, struct smb1390, cp_class); + int rc, val; + + rc = smb1390_read(chip, CORE_STATUS1_REG, &val); + if (rc < 0) + return snprintf(buf, PAGE_SIZE, "%s\n", "unknown"); + else + return snprintf(buf, PAGE_SIZE, "%s\n", "smb1390"); +} +static CLASS_ATTR_RO(model_name); +#endif + static ssize_t enable_show(struct class *c, struct class_attribute *attr, char *buf) { @@ -469,6 +491,9 @@ static struct attribute *cp_class_attrs[] = { &class_attr_toggle_switcher.attr, &class_attr_die_temp.attr, &class_attr_isns.attr, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + &class_attr_model_name.attr, +#endif NULL, }; ATTRIBUTE_GROUPS(cp_class); @@ -519,7 +544,11 @@ static int smb1390_ilim_vote_cb(struct votable *votable, void *data, } /* ILIM less than 1A is not accurate; disable charging */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (ilim_uA < 900000) { +#else if (ilim_uA < 1000000) { +#endif pr_debug("ILIM %duA is too low to allow charging\n", ilim_uA); vote(chip->disable_votable, ILIM_VOTER, true, 0); } else { @@ -575,12 +604,20 @@ static int smb1390_notifier_cb(struct notifier_block *nb, return NOTIFY_OK; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define TAPER_CAPACITY_THR 55 +#define TAPER_CAPCITY_DELTA 1 +#define BATT_COOL_THR 220 +#endif static void smb1390_status_change_work(struct work_struct *work) { struct smb1390 *chip = container_of(work, struct smb1390, status_change_work); union power_supply_propval pval = {0, }; int max_fcc_ma, rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int capacity, batt_temp, charge_type; +#endif if (!is_psy_voter_available(chip)) goto out; @@ -612,6 +649,9 @@ static void smb1390_status_change_work(struct work_struct *work) */ if (pval.intval == POWER_SUPPLY_CP_WIRELESS) { vote(chip->ilim_votable, ICL_VOTER, false, 0); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + vote(chip->ilim_votable, ICL_CHANGE_VOTER, false, 0); +#endif rc = power_supply_get_property(chip->dc_psy, POWER_SUPPLY_PROP_CURRENT_MAX, &pval); if (rc < 0) @@ -650,6 +690,57 @@ static void smb1390_status_change_work(struct work_struct *work) if (get_effective_result(chip->disable_votable)) goto out; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &pval); + if (rc < 0) { + pr_err("Couldn't get batt capacity rc=%d\n", rc); + goto out; + } + capacity = pval.intval; + + rc = power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_TEMP, &pval); + if (rc < 0) { + pr_err("Couldn't get batt temp rc=%d\n", rc); + goto out; + } + batt_temp = pval.intval; + + rc = power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_CHARGE_TYPE, &pval); + if (rc < 0) { + pr_err("Couldn't get charge type rc=%d\n", rc); + goto out; + } + charge_type = pval.intval; + + pr_info("capacity:%d, batt_temp:%d, charge_type:%d\n", + capacity, batt_temp, charge_type); + + /* + * if taper happens too early due to battery esr is high caused by + * battery temperature is cool, vbat is easy to reach to near to vfloat, + * we will reset CP_VOTER here if early taper happens and battery + * temp recover to normal(above 22 degree by test) and charge type + * is FAST and battery capacity is below 55% to recover 1.5C charging + */ + if ((capacity < TAPER_CAPACITY_THR) + && (batt_temp >= BATT_COOL_THR) + && (charge_type == POWER_SUPPLY_CHARGE_TYPE_FAST) + && chip->taper_early_trigger) { + if (is_client_vote_enabled(chip->fcc_votable, + CP_VOTER)) { + /* reset cp_voter here */ + vote(chip->fcc_votable, CP_VOTER, false, 0); + /* input current is always half the charge current */ + vote(chip->ilim_votable, FCC_VOTER, true, + get_effective_result(chip->fcc_votable) / 2); + chip->taper_early_trigger = false; + } + } +#endif + rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_CHARGE_TYPE, &pval); if (rc < 0) { @@ -673,6 +764,9 @@ static void smb1390_status_change_work(struct work_struct *work) BATT_PROFILE_VOTER); vote(chip->fcc_votable, CP_VOTER, max_fcc_ma > 0 ? true : false, max_fcc_ma); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->taper_early_trigger = false; +#endif vote(chip->disable_votable, SOC_LEVEL_VOTER, true, 0); } @@ -686,12 +780,34 @@ static void smb1390_taper_work(struct work_struct *work) struct smb1390 *chip = container_of(work, struct smb1390, taper_work); union power_supply_propval pval = {0, }; int rc, fcc_uA; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int capacity; +#endif if (!is_psy_voter_available(chip)) goto out; chip->taper_entry_fv = get_effective_result(chip->fv_votable); while (true) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_CAPACITY, &pval); + if (rc < 0) { + pr_err("Couldn't get batt capacity rc=%d\n", rc); + goto out; + } + capacity = pval.intval; + /* + * if capacity is lower than 55% - 1%(delta) and taper charge comes + * we think it is a early taper, normaly due to battery temperature is low + * such as 10 to 22 degree, battery esr is high and high current charging + * (charge pump is working during 10 to 22 degree, not working below 10) + */ + if ((capacity < (TAPER_CAPACITY_THR - TAPER_CAPCITY_DELTA)) + && !chip->taper_early_trigger) + chip->taper_early_trigger = true; +#endif + rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_CHARGE_TYPE, &pval); if (rc < 0) { @@ -795,6 +911,9 @@ static void smb1390_destroy_votables(struct smb1390 *chip) static int smb1390_init_hw(struct smb1390 *chip) { int rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int val; +#endif /* * charge pump is initially disabled; this indirectly votes to allow @@ -820,6 +939,15 @@ static int smb1390_init_hw(struct smb1390 *chip) if (rc < 0) return rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smb1390_read(chip, 0x1032, &val); + + rc = smb1390_masked_write(chip, 0x1032, 0x0F, 0x07); + rc = smb1390_read(chip, 0x1032, &val); + + if (rc < 0) + return rc; +#endif return 0; } diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c index bea84df021e6..2df71494216e 100644 --- a/drivers/power/supply/qcom/smb5-lib.c +++ b/drivers/power/supply/qcom/smb5-lib.c @@ -50,8 +50,21 @@ || typec_mode == POWER_SUPPLY_TYPEC_SOURCE_HIGH) \ && (!chg->typec_legacy || chg->typec_legacy_use_rp_icl)) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static bool off_charge_flag; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static bool first_boot_flag; +#endif + +bool smblib_rsbux_low(struct smb_charger *chg, int r_thr); +static int smblib_get_prop_typec_mode(struct smb_charger *chg); +#endif + static void update_sw_icl_max(struct smb_charger *chg, int pst); static int smblib_get_prop_typec_mode(struct smb_charger *chg); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int smblib_get_prop_dfp_mode(struct smb_charger *chg); +#endif int smblib_read(struct smb_charger *chg, u16 addr, u8 *val) { @@ -109,6 +122,25 @@ int smblib_get_iio_channel(struct smb_charger *chg, const char *propname, return rc; } +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +static void smblib_wireless_set_enable(struct smb_charger *chg, int enable) +{ + int rc = 0; + union power_supply_propval val = {0, }; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + { + val.intval = enable; + rc = power_supply_set_property(chg->idtp_psy, POWER_SUPPLY_PROP_PIN_ENABLED, &val); + if (rc < 0) { + smblib_err(chg, "Could not set charger control limit =%d\n", rc); + return; + } + } +} +#endif + #define DIV_FACTOR_MICRO_V_I 1 #define DIV_FACTOR_MILI_V_I 1000 #define DIV_FACTOR_DECIDEGC 100 @@ -491,6 +523,9 @@ enum { FLOAT, HVDCP2, HVDCP3, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + HVDCP3P5, +#endif MAX_TYPES }; @@ -535,6 +570,12 @@ static const struct apsd_result smblib_apsd_results[] = { .bit = DCP_CHARGER_BIT | QC_3P0_BIT, .pst = POWER_SUPPLY_TYPE_USB_HVDCP_3, }, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + [HVDCP3P5] = { + .name = "HVDCP3P5", + .pst = POWER_SUPPLY_TYPE_USB_HVDCP_3P5, + }, +#endif }; static const struct apsd_result *smblib_get_apsd_result(struct smb_charger *chg) @@ -567,9 +608,24 @@ static const struct apsd_result *smblib_get_apsd_result(struct smb_charger *chg) } if (apsd_stat & QC_CHARGER_BIT) { +#ifdef CONFIG_MACH_XIAOMI_NABU + if (chg->qc3p5_supported) { + if (result == &smblib_apsd_results[HVDCP3] + && chg->qc3p5_authenticated) { + result = &smblib_apsd_results[HVDCP3P5]; + } else if ((result != &smblib_apsd_results[HVDCP3P5]) + && (result != &smblib_apsd_results[HVDCP3])) { + /* If not QC3 or QC3.5, return QC2 */ + result = &smblib_apsd_results[HVDCP2]; + } + } else { +#endif /* since its a qc_charger, either return HVDCP3 or HVDCP2 */ if (result != &smblib_apsd_results[HVDCP3]) result = &smblib_apsd_results[HVDCP2]; +#ifdef CONFIG_MACH_XIAOMI_NABU + } +#endif } return result; @@ -761,6 +817,253 @@ int smblib_set_dc_suspend(struct smb_charger *chg, bool suspend) return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_get_fastcharge_mode(struct smb_charger *chg) +{ + union power_supply_propval pval = {0,}; + int rc = 0; + + if (!chg->bms_psy) + return 0; + + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_FASTCHARGE_MODE, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't read fastcharge mode:%d\n", rc); + return rc; + } + + return pval.intval; +} + +static int smb5_config_sys_iterm(struct smb_charger *chg, bool ffc_enable) +{ + union power_supply_propval pval = {0,}; + int rc; + + pval.intval = ffc_enable; + + rc = power_supply_set_property(chg->bms_psy, + POWER_SUPPLY_PROP_SYS_TERMINATION_CURRENT, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't set ffc termination current:%d\n", rc); + return rc; + } + rc = power_supply_set_property(chg->bms_psy, + POWER_SUPPLY_PROP_VBATT_FULL_VOL, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't set ffc vabtt full:%d\n", rc); + return rc; + } + + rc = power_supply_set_property(chg->bms_psy, + POWER_SUPPLY_PROP_KI_COEFF_CURRENT, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't set ffc ki_coefet:%d\n", rc); + return rc; + } + return rc; +} + +int smb5_config_iterm(struct smb_charger *chg, int hi_thresh, int low_thresh) +{ + s16 raw_hi_thresh, raw_lo_thresh; + u8 *buf; + int rc = 0; + + rc = smblib_masked_write(chg, CHGR_ADC_TERM_CFG_REG, + TERM_BASED_ON_SYNC_CONV_OR_SAMPLE_CNT, + TERM_BASED_ON_SAMPLE_CNT); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure ADC_ITERM_CFG rc=%d\n", + rc); + return rc; + } + + /* + * Conversion: + * raw (A) = (scaled_mA * ADC_CHG_TERM_MASK) / (10 * 1000) + * Note: raw needs to be converted to big-endian format. + */ + + if (hi_thresh) { + raw_hi_thresh = ((hi_thresh * ADC_CHG_ITERM_MASK) / 10000); + raw_hi_thresh = sign_extend32(raw_hi_thresh, 15); + buf = (u8 *)&raw_hi_thresh; + rc = smblib_write(chg, CHGR_ADC_ITERM_UP_THD_MSB_REG, + buf[1]); + if (rc < 0) { + dev_err(chg->dev, "Couldn't set term MSB rc=%d\n", + rc); + return rc; + } + rc = smblib_write(chg, CHGR_ADC_ITERM_UP_THD_LSB_REG, + buf[0]); + if (rc < 0) { + dev_err(chg->dev, "Couldn't set term LSB rc=%d\n", + rc); + return rc; + } + } + + if (low_thresh) { + raw_lo_thresh = ((low_thresh * ADC_CHG_ITERM_MASK) / 10000); + raw_lo_thresh = sign_extend32(raw_lo_thresh, 15); + buf = (u8 *)&raw_lo_thresh; + raw_lo_thresh = buf[1] | (buf[0] << 8); + + rc = smblib_batch_write(chg, CHGR_ADC_ITERM_LO_THD_MSB_REG, + (u8 *)&raw_lo_thresh, 2); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure ITERM threshold LOW rc=%d\n", + rc); + return rc; + } + } + + return 0; +} + +#ifdef CONFIG_MACH_XIAOMI_NABU +static int set_ln8000_fv(struct smb_charger *chg) { + int rc; + union power_supply_propval val; + if (!chg->cp_psy) { + chg->cp_psy = power_supply_get_by_name("bq2597x-standalone"); + if (!chg->cp_psy){ + chg->cp_psy = power_supply_get_by_name("ln8000"); + if (!chg->cp_psy){ + pr_err("cp_psy not found\n"); + return 0; + } + } + } + + rc = power_supply_get_property(chg->cp_psy, + POWER_SUPPLY_PROP_MODEL_NAME, &val); + if (rc < 0) { + pr_err("Error in getting charge IC name, rc=%d\n", rc); + return 0; + } + + if (strcmp(val.strval, "ln8000") == 0) { + vote(chg->fv_votable, BATT_LN8000_VOTER, true, 4470000); + } + return 0; +} +#endif + +int smblib_set_fastcharge_mode(struct smb_charger *chg, bool enable) +{ + union power_supply_propval pval = {0,}; + int rc = 0; + int termi = -220, batt_temp; + + if (!chg->bms_psy) + return 0; + + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_AUTHENTIC, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get battery authentic:%d\n", rc); + return rc; + } + if (!pval.intval) + enable = false; + + /*if soc > 95 do not set fastcharge flag*/ + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_CAPACITY, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get bms capacity:%d\n", rc); + return rc; + } + if (enable && pval.intval >= 95) { + smblib_dbg(chg, PR_MISC, "soc:%d is more than 95" + "do not setfastcharge mode\n", pval.intval); + enable = false; + } + /*if temp > 450 or temp < 150 do not set fastcharge flag*/ + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_TEMP, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get bms capacity:%d\n", rc); + goto set_term; + } + batt_temp = pval.intval; + if (enable && (pval.intval >= chg->ffc_high_tbat || pval.intval <= chg->ffc_low_tbat)) { + pr_info("tbat out of range, don't enable ffc\n"); + enable = false; + } + + pval.intval = enable; + rc = power_supply_set_property(chg->bms_psy, + POWER_SUPPLY_PROP_FASTCHARGE_MODE, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't write fastcharge mode:%d\n", rc); + goto set_term; + } + + if (enable) { + /* ffc need clear non_fcc_vfloat_voter first */ + vote(chg->fv_votable, NON_FFC_VFLOAT_VOTER, false, 0); +#ifdef CONFIG_MACH_XIAOMI_NABU + set_ln8000_fv(chg); +#endif + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_FFC_TERMINATION_CURRENT, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't ffc termination current:%d\n", rc); + goto set_term; + } + termi = pval.intval; + + } else { + /* when disable fast charge mode, need set vfloat back to 4.4V */ + vote(chg->fv_votable, NON_FFC_VFLOAT_VOTER, + true, NON_FFC_VFLOAT_UV); + termi = chg->chg_term_current_thresh_hi_from_dts; + } + smb5_config_sys_iterm(chg, enable); +set_term: + smb5_config_iterm(chg, termi, 50); + + rc = vote(chg->fcc_votable, PD_VERIFED_VOTER, + !enable, PD_UNVERIFED_CURRENT); + + rc = vote(chg->fv_votable, PD_VERIFED_VOTER, + !enable, PD_UNVERIFED_VOLTAGE); + + pr_info("fastcharge mode:%d termi:%d\n", enable, termi); + + return 0; +} + +static void smblib_check_batt_authentic(struct smb_charger *chg) +{ + int rc = 0; + int authen_result = -1; + union power_supply_propval pval = {0,}; + if (chg->batt_verify_psy && chg->bms_psy) { + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_AUTHENTIC, &pval); + if (!rc) + authen_result = pval.intval; + pr_err("authen_result: %d\n", authen_result); + if (!authen_result) { + pval.intval = 1; + rc = power_supply_set_property(chg->batt_verify_psy, + POWER_SUPPLY_PROP_AUTHENTIC, &pval); + if (rc) + pr_err("set batt_verify authentic prop failed: %d\n", + rc); + } + /* notify smblib_notifier_call to reset BATT_VERIFY_VOTER fcc voter */ + power_supply_changed(chg->bms_psy); + } +} +#endif + static int smblib_usb_pd_adapter_allowance_override(struct smb_charger *chg, u8 allowed_voltage) { @@ -780,6 +1083,40 @@ static int smblib_usb_pd_adapter_allowance_override(struct smb_charger *chg, return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int smblib_set_adapter_allowance(struct smb_charger *chg, + u8 allowed_voltage) +{ + int rc = 0; + + /* PMI632 only support max. 9V */ + if (chg->chg_param.smb_version == PMI632_SUBTYPE) { + switch (allowed_voltage) { + case USBIN_ADAPTER_ALLOW_12V: + case USBIN_ADAPTER_ALLOW_9V_TO_12V: + allowed_voltage = USBIN_ADAPTER_ALLOW_9V; + break; + case USBIN_ADAPTER_ALLOW_5V_OR_12V: + case USBIN_ADAPTER_ALLOW_5V_OR_9V_TO_12V: + allowed_voltage = USBIN_ADAPTER_ALLOW_5V_OR_9V; + break; + case USBIN_ADAPTER_ALLOW_5V_TO_12V: + allowed_voltage = USBIN_ADAPTER_ALLOW_5V_TO_9V; + break; + } + } + + rc = smblib_write(chg, USBIN_ADAPTER_ALLOW_CFG_REG, allowed_voltage); + if (rc < 0) { + smblib_err(chg, "Couldn't write 0x%02x to USBIN_ADAPTER_ALLOW_CFG rc=%d\n", + allowed_voltage, rc); + return rc; + } + + return rc; +} +#endif + #define MICRO_5V 5000000 #define MICRO_9V 9000000 #define MICRO_12V 12000000 @@ -1083,6 +1420,9 @@ static const struct apsd_result *smblib_update_usb_type(struct smb_charger *chg) /* if PD is active, APSD is disabled so won't have a valid result */ if (chg->pd_active) { chg->real_charger_type = POWER_SUPPLY_TYPE_USB_PD; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->usb_psy_desc.type = POWER_SUPPLY_TYPE_USB_PD; +#endif } else if (chg->qc3p5_detected) { chg->real_charger_type = POWER_SUPPLY_TYPE_USB_HVDCP_3P5; } else { @@ -1090,9 +1430,23 @@ static const struct apsd_result *smblib_update_usb_type(struct smb_charger *chg) * Update real charger type only if its not FLOAT * detected as as SDP */ +#ifndef CONFIG_MACH_XIAOMI_NABU if (!(apsd_result->pst == POWER_SUPPLY_TYPE_USB_FLOAT && chg->real_charger_type == POWER_SUPPLY_TYPE_USB)) +#else + if (!(apsd_result->pst == POWER_SUPPLY_TYPE_USB_FLOAT && + chg->real_charger_type == POWER_SUPPLY_TYPE_USB) && + (!chg->qc3p5_supported || chg->qc3p5_auth_complete || + apsd_result->pst != POWER_SUPPLY_TYPE_USB_HVDCP_3)) +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 + { +#endif chg->real_charger_type = apsd_result->pst; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->usb_psy_desc.type = apsd_result->pst; + } +#endif } smblib_dbg(chg, PR_MISC, "APSD=%s PD=%d QC3P5=%d\n", @@ -1110,7 +1464,15 @@ static int smblib_notifier_call(struct notifier_block *nb, if (!chg->bms_psy) chg->bms_psy = psy; if (ev == PSY_EVENT_PROP_CHANGED) +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + { + if (!chg->batt_verified) + schedule_delayed_work(&chg->batt_verify_update_work, 0); +#endif schedule_work(&chg->bms_update_work); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + } // git don't pick this bracket +#endif } if (chg->jeita_configured == JEITA_CFG_NONE) @@ -1238,6 +1600,9 @@ static void smblib_uusb_removal(struct smb_charger *chg) del_timer_sync(&chg->apsd_timer); chg->apsd_ext_timeout = false; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->report_usb_absent = false; +#endif /* write back the default FLOAT charger configuration */ rc = smblib_masked_write(chg, USBIN_OPTIONS_2_CFG_REG, @@ -1309,6 +1674,9 @@ int smblib_rerun_apsd_if_required(struct smb_charger *chg) { union power_supply_propval val; int rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + const struct apsd_result *apsd_result; +#endif rc = smblib_get_prop_usb_present(chg, &val); if (rc < 0) { @@ -1316,15 +1684,40 @@ int smblib_rerun_apsd_if_required(struct smb_charger *chg) return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!val.intval || chg->fake_usb_insertion) +#else if (!val.intval) +#endif return 0; +#ifndef CONFIG_MACH_XIAOMI_SM8150 rc = smblib_request_dpdm(chg, true); if (rc < 0) smblib_err(chg, "Couldn't to enable DPDM rc=%d\n", rc); +#endif chg->uusb_apsd_rerun_done = true; + +#ifndef CONFIG_MACH_XIAOMI_SM8150 smblib_rerun_apsd(chg); +#else + if (!off_charge_flag) { + rc = smblib_request_dpdm(chg, true); + if (rc < 0) + smblib_err(chg, "Couldn't to enable DPDM rc=%d\n", rc); + smblib_rerun_apsd(chg); + } else { + apsd_result = smblib_update_usb_type(chg); + /* if apsd result is SDP and off-charge mode, no need rerun apsd */ + if (!(apsd_result->bit & SDP_CHARGER_BIT)) { + rc = smblib_request_dpdm(chg, true); + if (rc < 0) + smblib_err(chg, "Couldn't to enable DPDM rc=%d\n", rc); + smblib_rerun_apsd(chg); + } + } +#endif return 0; } @@ -1421,6 +1814,9 @@ int smblib_set_icl_current(struct smb_charger *chg, int icl_ua) if (!chg->dcin_uusb_over_gpio_en) { /* configure current */ if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB +#ifdef CONFIG_MACH_XIAOMI_SM8150 + && (icl_ua <= USBIN_500MA) +#endif && (chg->typec_legacy || chg->typec_mode == POWER_SUPPLY_TYPEC_SOURCE_DEFAULT || chg->connector_type == @@ -1438,7 +1834,11 @@ int smblib_set_icl_current(struct smb_charger *chg, int icl_ua) * or below for better accuracy; in case of error, * proceed to use USB high-current mode. */ +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (icl_ua < USBIN_100MA) { +#else if (icl_ua <= USBIN_500MA) { +#endif rc = set_sdp_current(chg, icl_ua); if (rc >= 0) goto unsuspend; @@ -1697,6 +2097,46 @@ static int smblib_dc_suspend_vote_callback(struct votable *votable, void *data, return smblib_set_dc_suspend(chg, (bool)suspend); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int smblib_dc_icl_vote_callback(struct votable *votable, void *data, + int icl_ua, const char *client) +{ + struct smb_charger *chg = data; + int rc = 0; + bool suspend; + int Vpsns; + + if (icl_ua < 0) { + smblib_dbg(chg, PR_MISC, "No Voter hence suspending\n"); + icl_ua = 0; + } + + suspend = (icl_ua <= USBIN_25MA); + if (suspend) + goto suspend; + + Vpsns = (icl_ua/PSNS_CURRENT_SAMPLE_RATE) * PSNS_CURRENT_SAMPLE_RESIS; + if (chg->dc_temp_level == 13 || chg->dc_temp_level == 9) + Vpsns += PSNS_COMP_UV_FOR_HIGH_THERMAL; + + rc = smblib_set_charge_param(chg, &chg->param.dc_icl, Vpsns); + if (rc < 0) { + smblib_err(chg, "Couldn't set DC input current limit rc=%d\n", + rc); + return rc; + } + +suspend: + rc = vote(chg->dc_suspend_votable, USER_VOTER, suspend, 0); + if (rc < 0) { + smblib_err(chg, "Couldn't vote to %s DC rc=%d\n", + suspend ? "suspend" : "resume", rc); + return rc; + } + return rc; +} +#endif + static int smblib_awake_vote_callback(struct votable *votable, void *data, int awake, const char *client) { @@ -1932,6 +2372,33 @@ int smblib_vbus_regulator_is_enabled(struct regulator_dev *rdev) return (cmd & OTG_EN_BIT) ? 1 : 0; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int smblib_get_batt_voltage_now(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + rc = smblib_get_prop_from_bms(chg, + POWER_SUPPLY_PROP_VOLTAGE_NOW, val); + + return rc; +} + +static void smblib_get_start_vbat_before_step_charge(struct smb_charger *chg) +{ + int rc; + union power_supply_propval pval = {0, }; + + rc = smblib_get_batt_voltage_now(chg, &pval); + if (!rc) + chg->start_step_vbat = pval.intval; + else + pr_err("could not get vbat vol from bms\n"); + + pr_err("chg->start_step_vbat: %d\n", chg->start_step_vbat); +} +#endif + /******************** * BATT PSY GETTERS * ********************/ @@ -1941,7 +2408,11 @@ int smblib_get_prop_input_suspend(struct smb_charger *chg, { val->intval = (get_client_vote(chg->usb_icl_votable, USER_VOTER) == 0) +#ifdef CONFIG_MACH_XIAOMI_SM8150 + || get_client_vote(chg->dc_suspend_votable, USER_VOTER); +#else && get_client_vote(chg->dc_suspend_votable, USER_VOTER); +#endif return 0; } @@ -1963,51 +2434,242 @@ int smblib_get_prop_batt_present(struct smb_charger *chg, return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_get_prop_batt_voltage_now(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + if (!chg->bms_psy) + return -EINVAL; + + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, val); + return rc; +} + +static void smblib_check_usb_status(struct smb_charger *chg) +{ + int rc; + int usb_present = 0, vbat_uv = 0; + union power_supply_propval pval = {0,}; + + rc = smblib_get_prop_usb_present(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return; + } + usb_present = pval.intval; + + if (!usb_present) + return; + + rc = smblib_get_prop_batt_voltage_now(chg, &pval); + if (rc < 0) { + pr_err("Couldn't get vbat rc=%d\n", rc); + return; + } + vbat_uv = pval.intval; + + /* + * if battery soc is 0%, vbat is below 3400mV and usb is present in + * normal mode(not power-off charging mode), set online to + * false to notify system to power off. + */ + if ((usb_present == 1) && (!off_charge_flag) + && (vbat_uv <= CUTOFF_VOL_THR)) { + chg->report_usb_absent = true; + power_supply_changed(chg->batt_psy); + } +} +#endif + int smblib_get_prop_batt_capacity(struct smb_charger *chg, union power_supply_propval *val) { int rc = -EINVAL; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->fake_capacity >= 0 && chg->fake_capacity <= 100) { +#else if (chg->fake_capacity >= 0) { +#endif val->intval = chg->fake_capacity; return 0; } rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_CAPACITY, val); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (val->intval == 0) + smblib_check_usb_status(chg); +#endif + return rc; } -static bool is_charging_paused(struct smb_charger *chg) +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_get_prop_batt_capacity_level(struct smb_charger *chg, + union power_supply_propval *val) { - int rc; - u8 val; + int rc,cap; + union power_supply_propval capacity = {0, }; - rc = smblib_read(chg, CHARGING_PAUSE_CMD_REG, &val); - if (rc < 0) { - smblib_err(chg, "Couldn't read CHARGING_PAUSE_CMD rc=%d\n", rc); - return false; - } + rc = smblib_get_prop_batt_capacity(chg, &capacity); - return val & CHARGING_PAUSE_CMD_BIT; + cap = capacity.intval; + if (cap <= 0) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; + if (cap > 0 && cap <= 20) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW; + if (cap > 20 && cap <= 80) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; + if (cap > 80 && cap <= 99) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_HIGH; + if (cap >= 100) + val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL; + return rc; // git } -int smblib_get_prop_batt_status(struct smb_charger *chg, - union power_supply_propval *val) +static bool smblib_is_jeita_warm_charging(struct smb_charger *chg) { union power_supply_propval pval = {0, }; bool usb_online, dc_online; - u8 stat; - int rc, suspend = 0; + int rc; - if (chg->fake_chg_status_on_debug_batt) { - rc = smblib_get_prop_from_bms(chg, - POWER_SUPPLY_PROP_DEBUG_BATTERY, &pval); - if (rc < 0) { - pr_err_ratelimited("Couldn't get debug battery prop rc=%d\n", - rc); - } else if (pval.intval == 1) { - val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + rc = smblib_get_prop_usb_online(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb online property rc=%d\n", + rc); + return rc; // git + } // git + usb_online = (bool)pval.intval; + + rc = smblib_get_prop_dc_online(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get dc online property rc=%d\n", + rc); + return rc; // git + } // git + dc_online = (bool)pval.intval; + + if (!usb_online && !dc_online) + return false; + + rc = smblib_get_prop_batt_health(chg, &pval); + if (rc < 0) + smblib_err(chg, "Couldn't get batt health rc=%d\n", rc); + + /* show charging when jeita warm if real charging status is not charging */ + if (POWER_SUPPLY_HEALTH_WARM == pval.intval) + return true; + else + return false; +} +#endif + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +static bool smblib_wireless_to_usb_charging(struct smb_charger *chg, + bool usb_online, bool dc_online) +{ + if ((usb_online || chg->typec_mode == POWER_SUPPLY_TYPEC_SOURCE_HIGH) + && chg->fake_dc_on) { + /* insert usb when wireless charging, set status + * to charge and charger type to DCP + * insert pd charger when wireless charging, power good irq will + * trigger very qucickly difference with other charger type. + */ + if (!chg->pd_active) { + chg->real_charger_type = POWER_SUPPLY_TYPE_USB_DCP; + chg->usb_psy_desc.type = POWER_SUPPLY_TYPE_USB_DCP; + } + return true; + } else if (smblib_get_prop_dfp_mode(chg) != POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER + && smblib_get_prop_dfp_mode(chg) != POWER_SUPPLY_TYPEC_NONE + && chg->power_good_en) { + smblib_dbg(chg, PR_WLS, "otg mode, set charging when pwr on\n"); + return true; + } + else + return false; +} + +static bool smblib_is_jeita_warm_charging(struct smb_charger *chg) +{ + union power_supply_propval pval = {0, }; + bool usb_online, dc_online; + int rc; + + rc = smblib_get_prop_usb_online(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb online property rc=%d\n", + rc); + return rc; + } + usb_online = (bool)pval.intval; + + rc = smblib_get_prop_dc_online(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get dc online property rc=%d\n", + rc); + return rc; + } + dc_online = (bool)pval.intval; + + if (!usb_online && !dc_online) + return false; + + rc = smblib_get_prop_batt_health(chg, &pval); + if (rc < 0) + smblib_err(chg, "Couldn't get batt health rc=%d\n", rc); + + if (POWER_SUPPLY_HEALTH_WARM == pval.intval) + return true; + else + return false; +} +#endif + +static bool is_charging_paused(struct smb_charger *chg) +{ + int rc; + u8 val; + + rc = smblib_read(chg, CHARGING_PAUSE_CMD_REG, &val); + if (rc < 0) { + smblib_err(chg, "Couldn't read CHARGING_PAUSE_CMD rc=%d\n", rc); + return false; + } + + return val & CHARGING_PAUSE_CMD_BIT; +} + +int smblib_get_prop_batt_status(struct smb_charger *chg, + union power_supply_propval *val) +{ + union power_supply_propval pval = {0, }; + bool usb_online, dc_online; + u8 stat; + int rc, suspend = 0; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + union power_supply_propval batt_capa = {0, }; +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump && (get_client_vote_locked(chg->usb_icl_votable, + MAIN_CHG_VOTER) == MAIN_CHARGER_STOP_ICL)) { + val->intval = POWER_SUPPLY_STATUS_CHARGING; + return 0; + } +#endif + + if (chg->fake_chg_status_on_debug_batt) { + rc = smblib_get_prop_from_bms(chg, + POWER_SUPPLY_PROP_DEBUG_BATTERY, &pval); + if (rc < 0) { + pr_err_ratelimited("Couldn't get debug battery prop rc=%d\n", + rc); + } else if (pval.intval == 1) { + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; return 0; } } @@ -2062,6 +2724,7 @@ int smblib_get_prop_batt_status(struct smb_charger *chg, stat = stat & BATTERY_CHARGER_STATUS_MASK; if (!usb_online && !dc_online) { +#ifndef CONFIG_MACH_XIAOMI_SM8150 switch (stat) { case TERMINATE_CHARGE: case INHIBIT_CHARGE: @@ -2071,9 +2734,47 @@ int smblib_get_prop_batt_status(struct smb_charger *chg, val->intval = POWER_SUPPLY_STATUS_DISCHARGING; break; } +#else + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; +#endif return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_get_prop_batt_health(chg, &pval); + if (rc < 0) + smblib_err(chg, "Couldn't get batt health rc=%d\n", rc); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = smblib_get_prop_from_bms(chg, + POWER_SUPPLY_PROP_CAPACITY, &batt_capa); + if (rc < 0) + smblib_err(chg, "Couldn't read SOC value, rc=%d\n", rc); +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (get_client_vote_locked(chg->usb_icl_votable, JEITA_VOTER) == 0) { +#else + if ((get_client_vote_locked(chg->usb_icl_votable, JEITA_VOTER) == 0) || + (get_client_vote_locked(chg->dc_suspend_votable, JEITA_VOTER) == 1)) { +#endif + /* show charging when JEITA_VOTER 0mA is vote to improve user experience */ + if (pval.intval != POWER_SUPPLY_HEALTH_OVERHEAT + && pval.intval != POWER_SUPPLY_HEALTH_COLD) { + val->intval = POWER_SUPPLY_STATUS_CHARGING; + return 0; + } + } + +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (pval.intval == POWER_SUPPLY_HEALTH_OVERHEAT || + pval.intval == POWER_SUPPLY_HEALTH_COLD) { + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + return 0; + } +#endif +#endif + switch (stat) { case TRICKLE_CHARGE: case PRE_CHARGE: @@ -2083,17 +2784,67 @@ int smblib_get_prop_batt_status(struct smb_charger *chg, break; case TERMINATE_CHARGE: case INHIBIT_CHARGE: +#ifndef CONFIG_MACH_XIAOMI_SM8150 val->intval = POWER_SUPPLY_STATUS_FULL; +#else + if (POWER_SUPPLY_HEALTH_WARM == pval.intval +#ifdef CONFIG_MACH_XIAOMI_VAYU + || batt_capa.intval <= 98 +#endif + || POWER_SUPPLY_HEALTH_OVERHEAT == pval.intval) + val->intval = POWER_SUPPLY_STATUS_CHARGING; + else { + val->intval = POWER_SUPPLY_STATUS_FULL; +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + chg->last_batt_stat = val->intval; +#endif + } +#endif break; case DISABLE_CHARGE: case PAUSE_CHARGE: +#ifndef CONFIG_MACH_XIAOMI_SM8150 val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; +#else + /* + * As from jeita status change, there is very short time not charging, + * to improve user experience, we report charging at this moment. + */ + if (smblib_is_jeita_warm_charging(chg) +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + || smblib_wireless_to_usb_charging(chg, usb_online, dc_online) +#endif + ) + val->intval = POWER_SUPPLY_STATUS_CHARGING; + else + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; +#endif break; default: val->intval = POWER_SUPPLY_STATUS_UNKNOWN; break; } +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (!usb_online && chg->typec_mode != POWER_SUPPLY_TYPEC_SOURCE_HIGH + && dc_online && chg->fake_dc_on) { + /* + * fix insert wireless charger the logo will show twice. + * Also include wireless swith to pd charger, "wireless charger stop" issue. + */ + if (val->intval == POWER_SUPPLY_STATUS_CHARGING) + chg->fake_dc_on = 0; + else if (chg->last_batt_stat == POWER_SUPPLY_STATUS_FULL && + val->intval != POWER_SUPPLY_STATUS_CHARGING) { + val->intval = POWER_SUPPLY_STATUS_FULL; + chg->last_batt_stat = val->intval; + } + else if (val->intval != POWER_SUPPLY_STATUS_FULL) + val->intval = POWER_SUPPLY_STATUS_CHARGING; + return 0; + } +#endif + if (is_charging_paused(chg)) { val->intval = POWER_SUPPLY_STATUS_CHARGING; return 0; @@ -2109,15 +2860,29 @@ int smblib_get_prop_batt_status(struct smb_charger *chg, return 0; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = smblib_get_prop_batt_health(chg, &pval); + if (rc < 0) + smblib_err(chg, "Couldn't get batt health rc=%d\n", rc); +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (val->intval != POWER_SUPPLY_STATUS_CHARGING || pval.intval == POWER_SUPPLY_HEALTH_WARM) +#else if (val->intval != POWER_SUPPLY_STATUS_CHARGING) +#endif return 0; if (!usb_online && dc_online && chg->fake_batt_status == POWER_SUPPLY_STATUS_FULL) { val->intval = POWER_SUPPLY_STATUS_FULL; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + chg->last_batt_stat = val->intval; +#endif return 0; } +#ifndef CONFIG_MACH_XIAOMI_SM8150 rc = smblib_read(chg, BATTERY_CHARGER_STATUS_5_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read BATTERY_CHARGER_STATUS_2 rc=%d\n", @@ -2130,6 +2895,7 @@ int smblib_get_prop_batt_status(struct smb_charger *chg, if (!stat) val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; +#endif return 0; } @@ -2165,6 +2931,24 @@ int smblib_get_prop_batt_charge_type(struct smb_charger *chg, return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static bool is_bq25970_available(struct smb_charger *chg) +{ + if (!chg->cp_psy) + chg->cp_psy = power_supply_get_by_name("bq2597x-standalone"); + +#ifdef CONFIG_MACH_XIAOMI_NABU + if (!chg->cp_psy) + chg->cp_psy = power_supply_get_by_name("ln8000"); +#endif + + if (!chg->cp_psy) + return false; + + return true; +} +#endif + int smblib_get_prop_batt_health(struct smb_charger *chg, union power_supply_propval *val) { @@ -2172,6 +2956,9 @@ int smblib_get_prop_batt_health(struct smb_charger *chg, int rc; int effective_fv_uv; u8 stat; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int over_voltage_thr_uv; +#endif rc = smblib_read(chg, BATTERY_CHARGER_STATUS_2_REG, &stat); if (rc < 0) { @@ -2183,6 +2970,13 @@ int smblib_get_prop_batt_health(struct smb_charger *chg, stat); if (stat & CHARGER_ERROR_STATUS_BAT_OV_BIT) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump && is_bq25970_available(chg)) { + rc = power_supply_get_property(chg->cp_psy, + POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, &pval); + pval.intval = pval.intval * 1000; + } else +#endif rc = smblib_get_prop_from_bms(chg, POWER_SUPPLY_PROP_VOLTAGE_NOW, &pval); if (!rc) { @@ -2190,8 +2984,30 @@ int smblib_get_prop_batt_health(struct smb_charger *chg, * If Vbatt is within 40mV above Vfloat, then don't * treat it as overvoltage. */ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + effective_fv_uv = get_effective_result_locked(chg->fv_votable); + /* + * as six pin battery vbat is much higher than cell voltage + * we should add more buffer to over voltage threshold + * to report over voltage health + */ + if (chg->six_pin_step_charge_enable) { + if (effective_fv_uv == WARM_VFLOAT_UV) + over_voltage_thr_uv = effective_fv_uv + 80000; + else + over_voltage_thr_uv = chg->batt_profile_fv_uv + 50000; + } else { + over_voltage_thr_uv = effective_fv_uv + 40000; + } + if (pval.intval >= over_voltage_thr_uv) { +#else +#ifdef CONFIG_MACH_XIAOMI_SM8150 + effective_fv_uv = get_effective_result_locked(chg->fv_votable); +#else effective_fv_uv = get_effective_result(chg->fv_votable); +#endif if (pval.intval >= effective_fv_uv + 40000) { +#endif val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE; smblib_err(chg, "battery over-voltage vbat_fg = %duV, fv = %duV\n", pval.intval, effective_fv_uv); @@ -2235,6 +3051,15 @@ int smblib_get_prop_system_temp_level_max(struct smb_charger *chg, return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_get_prop_dc_temp_level(struct smb_charger *chg, + union power_supply_propval *val) +{ + val->intval = chg->dc_temp_level; + return 0; +} +#endif + int smblib_get_prop_input_current_limited(struct smb_charger *chg, union power_supply_propval *val) { @@ -2301,11 +3126,33 @@ int smblib_get_prop_batt_iterm(struct smb_charger *chg, return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int smblib_set_wdog_bark_timer(struct smb_charger *chg, + int wdog_timer) +{ + u8 val = 0; + int rc; + + val = (ilog2(wdog_timer / 16) << BARK_WDOG_TIMEOUT_SHIFT) + & BARK_WDOG_TIMEOUT_MASK; + rc = smblib_masked_write(chg, SNARL_BARK_BITE_WD_CFG_REG, + BARK_WDOG_TIMEOUT_MASK, val); + if (rc < 0) { + pr_err("Couldn't configue WD config rc=%d\n", rc); + return rc; + } + return rc; +} +#endif + int smblib_get_prop_batt_charge_done(struct smb_charger *chg, union power_supply_propval *val) { int rc; u8 stat; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + union power_supply_propval pval = {0, }; +#endif rc = smblib_read(chg, BATTERY_CHARGER_STATUS_1_REG, &stat); if (rc < 0) { @@ -2316,9 +3163,153 @@ int smblib_get_prop_batt_charge_done(struct smb_charger *chg, stat = stat & BATTERY_CHARGER_STATUS_MASK; val->intval = (stat == TERMINATE_CHARGE); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = smblib_get_prop_batt_capacity(chg, &pval); + if (rc < 0) + smblib_err(chg, "Couldn't get batt capacity rc=%d\n", rc); + + /* if charge is done, clear CHG_AWAKE_VOTER */ + if (val->intval == 1 && pval.intval >= 95) { + /* when charge done, set bark timer to 128s to decrease wakeups */ + smblib_set_wdog_bark_timer(chg, BARK_TIMER_LONG); + /*disable FFC when charge done*/ + if (chg->support_ffc) { + if (smblib_get_fastcharge_mode(chg) == 1) + rc = smblib_set_fastcharge_mode(chg, false); + } + vote(chg->awake_votable, CHG_AWAKE_VOTER, false, 0); + } +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + if (val->intval == 1) { + vote(chg->awake_votable, CHG_AWAKE_VOTER, false, 0); + vote(chg->awake_votable, DC_AWAKE_VOTER, false, 0); + } +#endif + + return 0; +} + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_get_prop_liquid_status(struct smb_charger *chg, + union power_supply_propval *val) +{ + /* + * as qcom liquid detection have a bug that when connect a A to C + * to Type-C port, but A port of cable plug is float, liquid detection + * will be triggered, it is same with real liquid detection action + * so we do not report lpd_status true to UI side, we will check later. + */ + val->intval = 0; + + if (chg->lpd_status) { + val->intval = 1; + pr_info("liquid status is true\n"); + } else { + val->intval = 0; + pr_info("liquid status is false\n"); + } + return 0; +} + +#define HW_ER_RATIO 2 +#define RF_ADC 1875 + +bool smblib_support_liquid_feature(struct smb_charger *chg) +{ + int hw_version; + int rc, i, data; + int error_value = RF_ADC*HW_ER_RATIO/100; + + if (chg->lpd_enabled == true) { + if (chg->init_once == false) { + rc = smblib_read_iio_channel(chg, chg->iio.hw_version_gpio5, + DIV_FACTOR_MILI_V_I, &hw_version); + if (rc < 0) { + smblib_err(chg, "Couldn't read hw_version_gpio5, rc = %d\n", rc); + return rc; + } else { + smblib_err(chg, "hw_version_gpio5 ADC = %d\n", hw_version); + } + + chg->init_once = true; + + for (i = 0; i < chg->lpd_levels; i++) { + data = (chg->lpd_hwversion[i] * 100) / (100000 + chg->lpd_hwversion[i]); + if (abs(RF_ADC * data / 100 - hw_version) < error_value) { + chg->support_liquid = true; + break; + } + } + } + } + + smblib_err(chg, "support_liquid is %d\n", chg->support_liquid); + return chg->support_liquid; +} + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_get_prop_battery_charging_enabled(struct smb_charger *chg, + union power_supply_propval *val) +{ + val->intval = !(get_client_vote(chg->usb_icl_votable, MAIN_CHG_VOTER) + == MAIN_CHARGER_STOP_ICL); + return 0; +} + +int smblib_get_prop_battery_charging_limited(struct smb_charger *chg, + union power_supply_propval *val) +{ + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3) + val->intval = (get_client_vote(chg->usb_icl_votable, MAIN_CHG_VOTER) + == QC3_CHARGER_ICL); + else if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) + val->intval = (get_client_vote(chg->usb_icl_votable, MAIN_CHG_VOTER) + == QC3P5_CHARGER_ICL); + else + val->intval = (get_client_vote(chg->usb_icl_votable, MAIN_CHG_VOTER) + == MAIN_CHARGER_ICL); + return 0; +} + +int smblib_get_prop_battery_slowly_charging(struct smb_charger *chg, + union power_supply_propval *val) +{ + val->intval = chg->slowly_charging; + return 0; +} + +int smblib_set_prop_battery_slowly_charging(struct smb_charger *chg, + const union power_supply_propval *val) +{ + if (val->intval ^ chg->slowly_charging) { + if (val->intval) { + vote(chg->fcc_votable, SLOWLY_CHARGING_VOTER, + true, SLOWLY_CHARGING_CURRENT); + } else { + + vote(chg->fcc_votable, SLOWLY_CHARGING_VOTER, false, 0); + } + chg->slowly_charging = (bool)val->intval; + rerun_election(chg->fcc_votable); + pr_info("slowly charging enabled[%d]\n", val->intval); + } + + return 0; +} + +int smblib_get_prop_battery_bq_input_suspend(struct smb_charger *chg, + union power_supply_propval *val) +{ + val->intval = chg->bq_input_suspend; return 0; } +#define HW_ER_RATIO 2 +#define RF_ADC 1875 +#endif +#endif + /*********************** * BATTERY PSY SETTERS * ***********************/ @@ -2343,6 +3334,11 @@ int smblib_set_prop_input_suspend(struct smb_charger *chg, return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) + chg->bq_input_suspend = !!(val->intval); +#endif + power_supply_changed(chg->batt_psy); return rc; } @@ -2350,8 +3346,23 @@ int smblib_set_prop_input_suspend(struct smb_charger *chg, int smblib_set_prop_batt_capacity(struct smb_charger *chg, const union power_supply_propval *val) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + union power_supply_propval shutdown_delay_en = {0, }; + /* only enable write reasonable soc value */ + if (val->intval < 0) + chg->fake_capacity = 0; + else if (val->intval > 100) + chg->fake_capacity = 100; + else +#endif chg->fake_capacity = val->intval; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + power_supply_set_property(chg->bms_psy, + POWER_SUPPLY_PROP_SHUTDOWN_DELAY_ENABLE, + &shutdown_delay_en); +#endif + power_supply_changed(chg->batt_psy); return 0; @@ -2371,35 +3382,447 @@ int smblib_set_prop_batt_status(struct smb_charger *chg, return 0; } -int smblib_set_prop_system_temp_level(struct smb_charger *chg, - const union power_supply_propval *val) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#ifdef CONFIG_MACH_XIAOMI_NABU +int smblib_get_prop_wireless_version(struct smb_charger *chg, + union power_supply_propval *val) { - if (val->intval < 0) - return -EINVAL; - - if (chg->thermal_levels <= 0) - return -EINVAL; - - if (val->intval > chg->thermal_levels) - return -EINVAL; - - chg->system_temp_level = val->intval; - - if (chg->system_temp_level == chg->thermal_levels) - return vote(chg->chg_disable_votable, - THERMAL_DAEMON_VOTER, true, 0); + int rc; - vote(chg->chg_disable_votable, THERMAL_DAEMON_VOTER, false, 0); - if (chg->system_temp_level == 0) - return vote(chg->fcc_votable, THERMAL_DAEMON_VOTER, false, 0); + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } - vote(chg->fcc_votable, THERMAL_DAEMON_VOTER, true, - chg->thermal_mitigation[chg->system_temp_level]); - return 0; + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_WIRELESS_VERSION, val); + return rc; } -int smblib_set_prop_input_current_limited(struct smb_charger *chg, - const union power_supply_propval *val) +int smblib_get_prop_wireless_fw_version(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) { + chg->wls_chip_psy = chg->idtp_psy; + } else { + chg->wip_psy = power_supply_get_by_name("rx1619"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_WIRELESS_FW_VERSION, val); + return rc; +} +#endif + +#define ADAPTER_NONE 0x00 +#define ADAPTER_SDP 0x01 +#define ADAPTER_CDP 0x02 +#define ADAPTER_DCP 0x03 +#define ADAPTER_QC2 0x05 +#define ADAPTER_QC3 0x06 +#define ADAPTER_PD 0x07 +#define ADAPTER_AUTH_FAILED 0x08 +#define ADAPTER_XIAOMI_QC3 0x09 +#define ADAPTER_XIAOMI_PD 0x0a +#define ADAPTER_ZIMI_CAR_POWER 0x0b +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define ADAPTER_XIAOMI_PD_40W 0x0c +#define ADAPTER_VOICE_BOX 0x0d +#define ADAPTER_XIAOMI_PD_50W 0x0e +#endif + +static int smblib_dc_therm_charging(struct smb_charger *chg, + int temp_level) +{ + int thermal_icl_ua = 0; + int rc; + union power_supply_propval pval = {0, }; + union power_supply_propval val = {0, }; + + if (!chg->wls_psy) { + chg->wls_psy = power_supply_get_by_name("wireless"); + if (!chg->wls_psy) + return -ENODEV; + } + rc = power_supply_get_property(chg->wls_psy, + POWER_SUPPLY_PROP_TX_ADAPTER, + &pval); + + rc = power_supply_get_property(chg->wls_psy, + POWER_SUPPLY_PROP_WIRELESS_VERSION, + &val); + switch (pval.intval) { + case ADAPTER_XIAOMI_QC3: + case ADAPTER_ZIMI_CAR_POWER: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case ADAPTER_XIAOMI_PD_40W: + case ADAPTER_XIAOMI_PD_50W: + case ADAPTER_VOICE_BOX: +#endif + thermal_icl_ua = chg->thermal_mitigation_dc[temp_level]; + break; + case ADAPTER_QC2: + thermal_icl_ua = chg->thermal_mitigation_bpp_qc2[temp_level]; + break; + case ADAPTER_QC3: + if (val.intval == 1)/*is epp*/ + thermal_icl_ua = chg->thermal_mitigation_epp[temp_level]; + else + thermal_icl_ua = chg->thermal_mitigation_bpp_qc3[temp_level]; + break; + case ADAPTER_XIAOMI_PD: + case ADAPTER_PD: + if (val.intval == 1)/*is epp*/ + thermal_icl_ua = chg->thermal_mitigation_epp[temp_level]; + else + thermal_icl_ua = chg->thermal_mitigation_bpp[temp_level]; + break; + case ADAPTER_AUTH_FAILED: + if (val.intval == 1)/*is epp*/ + thermal_icl_ua = chg->thermal_mitigation_epp[temp_level]; + else + thermal_icl_ua = chg->thermal_mitigation_bpp[temp_level]; + break; + case ADAPTER_CDP: + case ADAPTER_DCP: + thermal_icl_ua = chg->thermal_mitigation_bpp[temp_level]; + break; + default: + thermal_icl_ua = chg->thermal_mitigation_bpp[temp_level]; + break; + } + vote(chg->dc_icl_votable, THERMAL_DAEMON_VOTER, true, thermal_icl_ua); + + return rc; +} + +int smblib_set_prop_dc_temp_level(struct smb_charger *chg, + const union power_supply_propval *val) +{ + union power_supply_propval dc_present; + union power_supply_propval batt_temp; + int rc; + + rc = smblib_get_prop_dc_present(chg, &dc_present); + if (rc < 0) { + pr_err("Couldn't get dc present rc=%d\n", rc); + return -EINVAL; + } + + rc = smblib_get_prop_from_bms(chg, + POWER_SUPPLY_PROP_TEMP, &batt_temp); + if (rc < 0) { + pr_err("Couldn't get batt temp rc=%d\n", rc); + return -EINVAL; + } + + if (val->intval < 0) + return -EINVAL; + if (chg->dc_thermal_levels <= 0) + return -EINVAL; + if (val->intval > chg->dc_thermal_levels) + return -EINVAL; + chg->dc_temp_level = val->intval; + + if (chg->dc_temp_level == chg->dc_thermal_levels) + return vote(chg->chg_disable_votable, + THERMAL_DAEMON_VOTER, true, 0); + + vote(chg->chg_disable_votable, THERMAL_DAEMON_VOTER, false, 0); + if (chg->dc_temp_level == 0) + return vote(chg->dc_icl_votable, THERMAL_DAEMON_VOTER, false, 0); + + smblib_dc_therm_charging(chg, val->intval); + + return 0; +} + +static int smblib_therm_charging(struct smb_charger *chg) +{ + int thermal_icl_ua = 0; + int thermal_fcc_ua = 0; + int rc; + + if (chg->system_temp_level >= MAX_TEMP_LEVEL) + return 0; + + switch (chg->real_charger_type) { + case POWER_SUPPLY_TYPE_USB_HVDCP: + thermal_icl_ua = chg->thermal_mitigation_qc2[chg->system_temp_level]; + break; + case POWER_SUPPLY_TYPE_USB_HVDCP_3: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) { + thermal_fcc_ua = + chg->thermal_fcc_qc3_cp[chg->system_temp_level]; + } else { +#endif + if (chg->cp_reason == POWER_SUPPLY_CP_HVDCP3) { + if (chg->is_qc_class_a) + thermal_fcc_ua = + chg->thermal_fcc_qc3_cp[chg->system_temp_level]; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + else if (chg->temp_27W_enable) + thermal_fcc_ua = + chg->thermal_fcc_qc3_classb_cp[chg->system_temp_level]; +#endif + else + thermal_fcc_ua = +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->thermal_fcc_qc3_cp[chg->system_temp_level]; +#else + chg->thermal_fcc_qc3_classb_cp[chg->system_temp_level]; +#endif + } else { + thermal_fcc_ua = + chg->thermal_fcc_qc3_normal[chg->system_temp_level]; + } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + } +#endif + break; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case POWER_SUPPLY_TYPE_USB_HVDCP_3P5: + thermal_fcc_ua = + chg->thermal_fcc_qc3_cp[chg->system_temp_level]; + break; +#endif + case POWER_SUPPLY_TYPE_USB_PD: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) { + if (chg->pps_thermal_level < 0) + chg->pps_thermal_level = chg->system_temp_level; + pr_err("chg->pps_thermal_level=%d,chg->system_temp_level=%d\n", chg->pps_thermal_level, chg->system_temp_level); + thermal_fcc_ua = + chg->thermal_fcc_pps_cp[chg->pps_thermal_level]; + } else { +#endif + if (chg->cp_reason == POWER_SUPPLY_CP_PPS) { + thermal_fcc_ua = + chg->thermal_fcc_pps_cp[chg->system_temp_level]; + } else { + if (chg->voltage_min_uv >= PD_MICRO_5V + && chg->voltage_min_uv < PD_MICRO_5P9V) + thermal_icl_ua = + chg->thermal_mitigation_pd_base[chg->system_temp_level]; + else if (chg->voltage_min_uv >= PD_MICRO_5P9V + && chg->voltage_min_uv < PD_MICRO_6P5V) + thermal_icl_ua = + chg->thermal_mitigation_pd_base[chg->system_temp_level] + * PD_6P5V_PERCENT / 100; + else if (chg->voltage_min_uv >= PD_MICRO_6P5V + && chg->voltage_min_uv < PD_MICRO_7P5V) + thermal_icl_ua = + chg->thermal_mitigation_pd_base[chg->system_temp_level] + * PD_7P5V_PERCENT / 100; + else if (chg->voltage_min_uv >= PD_MICRO_7P5V + && chg->voltage_min_uv <= PD_MICRO_8P5V) + thermal_icl_ua = + chg->thermal_mitigation_pd_base[chg->system_temp_level] + * PD_8P5V_PERCENT / 100; + else if (chg->voltage_min_uv >= PD_MICRO_8P5V) + thermal_icl_ua = + chg->thermal_mitigation_pd_base[chg->system_temp_level] + * PD_9V_PERCENT / 100; + else + thermal_icl_ua = + chg->thermal_mitigation_pd_base[chg->system_temp_level]; + } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + } +#endif + break; + case POWER_SUPPLY_TYPE_USB_DCP: + default: + thermal_icl_ua = chg->thermal_mitigation_dcp[chg->system_temp_level]; + break; + } + + if (chg->system_temp_level == 0) { + /* if therm_lvl_sel is 0, clear thermal voter */ + rc = vote(chg->usb_icl_votable, THERMAL_DAEMON_VOTER, false, 0); + if (rc < 0) + pr_err("Couldn't disable USB thermal ICL vote rc=%d\n", + rc); + rc = vote(chg->fcc_votable, THERMAL_DAEMON_VOTER, false, 0); + if (rc < 0) + pr_err("Couldn't disable USB thermal ICL vote rc=%d\n", + rc); + } else { + pr_info("thermal_icl_ua is %d, chg->system_temp_level: %d\n", + thermal_icl_ua, chg->system_temp_level); + pr_info("thermal_fcc_ua is %d\n", thermal_fcc_ua); + + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + || chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5 + || ((chg->cp_reason == POWER_SUPPLY_CP_PPS || chg->use_bq_pump) +#else + || (chg->cp_reason == POWER_SUPPLY_CP_PPS +#endif + && chg->real_charger_type == POWER_SUPPLY_TYPE_USB_PD)) { + /* if use qc3 or pps charge with cp, also limit icl when high level */ + if (chg->system_temp_level >= ICL_LIMIT_LEVEL_THR) + thermal_icl_ua = + chg->thermal_mitigation_icl[chg->system_temp_level]; + if (chg->system_temp_level >= ICL_LIMIT_LEVEL_THR) { + rc = vote(chg->usb_icl_votable, THERMAL_DAEMON_VOTER, + true, thermal_icl_ua); + if (rc < 0) + pr_err("Couldn't enable USB thermal ICL vote rc=%d\n", + rc); + } else { + /* + * if use qc3 or pps charge with cp, reset it when level decrease + * below level threshold(such as level 9) + */ + rc = vote(chg->usb_icl_votable, THERMAL_DAEMON_VOTER, + false, 0); + if (rc < 0) + pr_err("Couldn't disable USB thermal ICL vote rc=%d\n", + rc); + } + } else { + if (thermal_icl_ua > 0) { + rc = vote(chg->usb_icl_votable, THERMAL_DAEMON_VOTER, true, + thermal_icl_ua); + if (rc < 0) + pr_err("Couldn't enable USB thermal ICL vote rc=%d\n", + rc); + } + } + if (thermal_fcc_ua > 0) { + rc = vote(chg->fcc_votable, THERMAL_DAEMON_VOTER, true, + thermal_fcc_ua); + if (rc < 0) + pr_err("Couldn't enable USB thermal ICL vote rc=%d\n", + rc); + } + } + + return rc; +} + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static void smblib_thermal_setting_work(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + thermal_setting_work.work); + + if (chg->pps_thermal_level > chg->system_temp_level) { + if (chg->pps_thermal_level - chg->system_temp_level >= 2) + chg->pps_thermal_level -= 2; + else + chg->pps_thermal_level -= 1; + } else if (chg->pps_thermal_level < chg->system_temp_level) { + if (chg->system_temp_level - chg->pps_thermal_level >= 2) + chg->pps_thermal_level += 2; + else + chg->pps_thermal_level += 1; + } + + smblib_therm_charging(chg); + + if (chg->pps_thermal_level != chg->system_temp_level) + schedule_delayed_work(&chg->thermal_setting_work, 3 * HZ); +} +#endif +#endif + +int smblib_set_prop_system_temp_level(struct smb_charger *chg, + const union power_supply_propval *val) +{ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int rc; + union power_supply_propval batt_temp = {0, }; +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_get_prop_from_bms(chg, + POWER_SUPPLY_PROP_TEMP, &batt_temp); + if (rc < 0) { + pr_err("Couldn't get batt temp rc=%d\n", rc); + return -EINVAL; + } +#endif + + if (val->intval < 0) + return -EINVAL; + + if (chg->thermal_levels <= 0) + return -EINVAL; + + if (val->intval > chg->thermal_levels) + return -EINVAL; + + chg->system_temp_level = val->intval; + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!chg->use_bq_pump) { + if (chg->system_temp_level >= (chg->thermal_levels - 1)) { + if (!chg->cp_disable_votable) + chg->cp_disable_votable = find_votable("CP_DISABLE"); + if (chg->cp_disable_votable) + vote(chg->cp_disable_votable, THERMAL_DAEMON_VOTER, true, 0); + + return vote(chg->chg_disable_votable, + THERMAL_DAEMON_VOTER, true, 0); + } + } +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + if (chg->system_temp_level >= (chg->thermal_levels - 1)) + return vote(chg->chg_disable_votable, + THERMAL_DAEMON_VOTER, true, 0); +#else + if (chg->system_temp_level == chg->thermal_levels) + return vote(chg->chg_disable_votable, + THERMAL_DAEMON_VOTER, true, 0); +#endif + + vote(chg->chg_disable_votable, THERMAL_DAEMON_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!chg->use_bq_pump && chg->cp_disable_votable) + vote(chg->cp_disable_votable, THERMAL_DAEMON_VOTER, false, 0); + + if (chg->use_bq_pump + && chg->real_charger_type == POWER_SUPPLY_TYPE_USB_PD) { + if (chg->pps_fcc_therm_work_disabled) { + chg->pps_thermal_level = chg->system_temp_level; + smblib_therm_charging(chg); + } else + schedule_delayed_work(&chg->thermal_setting_work, 3 * HZ); + } else + smblib_therm_charging(chg); +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + smblib_therm_charging(chg); +#else + if (chg->system_temp_level == 0) + return vote(chg->fcc_votable, THERMAL_DAEMON_VOTER, false, 0); + + vote(chg->fcc_votable, THERMAL_DAEMON_VOTER, true, + chg->thermal_mitigation[chg->system_temp_level]); +#endif + + return 0; +} + +int smblib_set_prop_input_current_limited(struct smb_charger *chg, + const union power_supply_propval *val) { chg->fake_input_current_limited = val->intval; return 0; @@ -2411,6 +3834,15 @@ int smblib_set_prop_rechg_soc_thresh(struct smb_charger *chg, int rc; u8 new_thr = DIV_ROUND_CLOSEST(val->intval * 255, 100); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* + * As DIV_ROUND_CLOSEST cal cause new_thr to 252, we add 1 more to + * improve recharging UI soc still to 100% to improve user experience. + */ + if (val->intval == RECHARGE_SOC_THR) + new_thr += 1; +#endif + rc = smblib_write(chg, CHARGE_RCHG_SOC_THRESHOLD_CFG_REG, new_thr); if (rc < 0) { @@ -2547,6 +3979,13 @@ static void smblib_hvdcp_adaptive_voltage_change(struct smb_charger *chg) u8 stat; if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->qc2_unsupported) { + smblib_hvdcp_set_fsw(chg, QC_5V_BIT); + power_supply_changed(chg->usb_main_psy); + return; + } +#endif rc = smblib_read(chg, QC_CHANGE_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, @@ -2574,8 +4013,30 @@ int smblib_dp_dm(struct smb_charger *chg, int val) union power_supply_propval pval; u8 stat; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) { + pr_info("dp_dm is controled by our self\n"); + return rc; + } +#endif + + /* if raise_vbus work is running, ignore dp_dm pulses */ + if (chg->raise_vbus_to_detect) + return rc; +#endif + switch (val) { case POWER_SUPPLY_DP_DM_DP_PULSE: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* + * if hvdcp_opti wrongly send more than 30 dp pulse(11V) to smb5, + * ignore them to allow maxium vbus as 11V, as charge pump do not + * need the vin more than 11V, and protect the device. + */ + if (chg->pulse_cnt > MAX_PLUSE_COUNT_ALLOWED) + return rc; +#endif /* * Pre-emptively increment pulse count to enable the setting * of FSW prior to increasing voltage. @@ -2599,6 +4060,21 @@ int smblib_dp_dm(struct smb_charger *chg, int val) smblib_dbg(chg, PR_PARALLEL, "DP_DM_DP_PULSE rc=%d cnt=%d\n", rc, chg->pulse_cnt); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* + * if use class_a qc, and slave ic is charge pump, should limit + * maxium icl to 1.9A, as VBUS will raise to about 9V to 9.8V, + * so we set icl to 1.9A when vbus raise above 7.4V + */ + if (chg->is_qc_class_a && chg->sec_cp_present) { + if (chg->pulse_cnt >= HIGH_NUM_PULSE_THR + && !chg->high_vbus_detected) { + vote(chg->usb_icl_votable, QC_A_CP_ICL_MAX_VOTER, true, + HVDCP_CLASS_A_FOR_CP_UA); + chg->high_vbus_detected = true; + } + } +#endif break; case POWER_SUPPLY_DP_DM_DM_PULSE: rc = smblib_dm_pulse(chg); @@ -2606,6 +4082,20 @@ int smblib_dp_dm(struct smb_charger *chg, int val) chg->pulse_cnt--; smblib_dbg(chg, PR_PARALLEL, "DP_DM_DM_PULSE rc=%d cnt=%d\n", rc, chg->pulse_cnt); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* + * if use class_a qc, and slave ic is charge pump, should restore + * icl to 2.4A when charge pump is not working for class_a qc + */ + if (chg->is_qc_class_a && chg->sec_cp_present) { + if (chg->pulse_cnt < HIGH_NUM_PULSE_THR + && chg->high_vbus_detected) { + vote(chg->usb_icl_votable, QC_A_CP_ICL_MAX_VOTER, false, + 0); + chg->high_vbus_detected = false; + } + } +#endif break; case POWER_SUPPLY_DP_DM_ICL_DOWN: target_icl_ua = get_effective_result(chg->usb_icl_votable); @@ -2639,10 +4129,21 @@ int smblib_dp_dm(struct smb_charger *chg, int val) break; case POWER_SUPPLY_DP_DM_FORCE_5V: rc = smblib_force_vbus_voltage(chg, FORCE_5V_BIT); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->pulse_cnt = 0; +#endif if (rc < 0) pr_err("Failed to force 5V\n"); break; case POWER_SUPPLY_DP_DM_FORCE_9V: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* we use our own qc2 method to raise to 9V, so just return here */ + return 0; + + if (chg->qc2_unsupported) + return 0; +#endif + if (chg->qc2_unsupported_voltage == QC2_NON_COMPLIANT_9V) { smblib_err(chg, "Couldn't set 9V: unsupported\n"); return -EINVAL; @@ -2666,8 +4167,20 @@ int smblib_dp_dm(struct smb_charger *chg, int val) rc = smblib_force_vbus_voltage(chg, FORCE_9V_BIT); if (rc < 0) pr_err("Failed to force 9V\n"); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP2_CURRENT_UA); +#endif break; case POWER_SUPPLY_DP_DM_FORCE_12V: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* we use our own qc2 method to raise to 9V, so just return here */ + return 0; + + if (chg->qc2_unsupported) + return 0; +#endif + if (chg->qc2_unsupported_voltage == QC2_NON_COMPLIANT_12V) { smblib_err(chg, "Couldn't set 12V: unsupported\n"); return -EINVAL; @@ -2691,6 +4204,10 @@ int smblib_dp_dm(struct smb_charger *chg, int val) rc = smblib_force_vbus_voltage(chg, FORCE_12V_BIT); if (rc < 0) pr_err("Failed to force 12V\n"); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP2_CURRENT_UA); +#endif break; case POWER_SUPPLY_DP_DM_CONFIRMED_HVDCP3P5: chg->qc3p5_detected = true; @@ -2704,65 +4221,231 @@ int smblib_dp_dm(struct smb_charger *chg, int val) return rc; } -int smblib_disable_hw_jeita(struct smb_charger *chg, bool disable) -{ - int rc; - u8 mask; - - /* - * Disable h/w base JEITA compensation if s/w JEITA is enabled - */ - mask = JEITA_EN_COLD_SL_FCV_BIT - | JEITA_EN_HOT_SL_FCV_BIT - | JEITA_EN_HOT_SL_CCC_BIT - | JEITA_EN_COLD_SL_CCC_BIT, - rc = smblib_masked_write(chg, JEITA_EN_CFG_REG, mask, - disable ? 0 : mask); - if (rc < 0) { - dev_err(chg->dev, "Couldn't configure s/w jeita rc=%d\n", - rc); - return rc; - } - - return 0; -} - -static int smblib_set_sw_thermal_regulation(struct smb_charger *chg, - bool enable) +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_dp_dm_bq(struct smb_charger *chg, int val) { int rc = 0; +#ifdef CONFIG_MACH_XIAOMI_NABU + int qc3p5_dp_cnt = 0; +#endif - if (!(chg->wa_flags & SW_THERM_REGULATION_WA)) + /* if raise_vbus work is running, ignore dp_dm pulses */ + if (chg->raise_vbus_to_detect) return rc; - if (enable) { + switch (val) { + case POWER_SUPPLY_DP_DM_DP_PULSE: /* - * Configure min time to quickly address thermal - * condition. + * if hvdcp_opti wrongly send more than 30 dp pulse(11V) to smb5, + * ignore them to allow maxium vbus as 11V, as charge pump do not + * need the vin more than 11V, and protect the device. */ - rc = smblib_masked_write(chg, SNARL_BARK_BITE_WD_CFG_REG, - SNARL_WDOG_TIMEOUT_MASK, SNARL_WDOG_TMOUT_62P5MS); - if (rc < 0) { - smblib_err(chg, "Couldn't configure snarl wdog tmout, rc=%d\n", - rc); + if (chg->pulse_cnt > MAX_PLUSE_COUNT_ALLOWED +#ifdef CONFIG_MACH_XIAOMI_NABU + && chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3 +#endif + ) { return rc; +#ifdef CONFIG_MACH_XIAOMI_NABU + } else if (chg->qc3p5_supported + && chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + if (chg->pulse_cnt > MAX_QC3P5_PLUSE_COUNT_ALLOWED) + return rc; + else if (chg->pulse_cnt >= QC3P5_DP_RAPIDLY_TUNE_ALLOWED) + chg->qc3p5_dp_tune_rapidly = false; + else + chg->qc3p5_dp_tune_rapidly = true; +#endif } /* - * Schedule SW_THERM_REGULATION_WORK directly if USB input - * is suspended due to SW thermal regulation WA since WDOG - * IRQ won't trigger with input suspended. + * Pre-emptively increment pulse count to enable the setting + * of FSW prior to increasing voltage. */ - if (is_client_vote_enabled(chg->usb_icl_votable, - SW_THERM_REGULATION_VOTER)) { - vote(chg->awake_votable, SW_THERM_REGULATION_VOTER, - true, 0); - schedule_delayed_work(&chg->thermal_regulation_work, 0); - } - } else { - cancel_delayed_work_sync(&chg->thermal_regulation_work); - vote(chg->awake_votable, SW_THERM_REGULATION_VOTER, false, 0); - } +#ifdef CONFIG_MACH_XIAOMI_NABU + if (chg->qc3p5_dp_tune_rapidly) + chg->pulse_cnt += QC3P5_DP_RAPIDLY_TUNE_PULSE; + else + chg->pulse_cnt++; +#else + chg->pulse_cnt++; +#endif + + rc = smblib_hvdcp3_set_fsw(chg); + if (rc < 0) + smblib_err(chg, "Couldn't set QC3.0 Fsw rc=%d\n", rc); + +#ifdef CONFIG_MACH_XIAOMI_NABU + if (chg->qc3p5_dp_tune_rapidly) { + for (qc3p5_dp_cnt = 1; qc3p5_dp_cnt <= QC3P5_DP_RAPIDLY_TUNE_PULSE; qc3p5_dp_cnt++) { + rc = smblib_dp_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't increase pulse count rc=%d\n", rc); + chg->pulse_cnt--; + } + smblib_dbg(chg, PR_PARALLEL, "DP_DM_DP_PULSE rapidly rc=%d cnt=%d\n", + rc, chg->pulse_cnt - QC3P5_DP_RAPIDLY_TUNE_PULSE + qc3p5_dp_cnt); + usleep_range(8000, 8010); // delay 8ms + } + } else { +#endif + rc = smblib_dp_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't increase pulse count rc=%d\n", + rc); + /* + * Increment pulse count failed; + * reset to former value. + */ + chg->pulse_cnt--; + } +#ifdef CONFIG_MACH_XIAOMI_NABU + } +#endif + + smblib_dbg(chg, PR_PARALLEL, "DP_DM_DP_PULSE rc=%d cnt=%d\n", + rc, chg->pulse_cnt); + /* + * if use class_a qc, and slave ic is charge pump, should limit + * maxium icl to 1.9A, as VBUS will raise to about 9V to 9.8V, + * so we set icl to 1.9A when vbus raise above 7.4V + */ + if (chg->is_qc_class_a && chg->sec_cp_present) { + if (chg->pulse_cnt >= HIGH_NUM_PULSE_THR + && !chg->high_vbus_detected) { + vote(chg->usb_icl_votable, QC_A_CP_ICL_MAX_VOTER, true, + HVDCP_CLASS_A_FOR_CP_UA); + chg->high_vbus_detected = true; + } + } + break; + + case POWER_SUPPLY_DP_DM_DM_PULSE: + rc = smblib_dm_pulse(chg); + if (!rc && chg->pulse_cnt) + chg->pulse_cnt--; + smblib_dbg(chg, PR_PARALLEL, "DP_DM_DM_PULSE rc=%d cnt=%d\n", + rc, chg->pulse_cnt); + /* + * if use class_a qc, and slave ic is charge pump, should restore + * icl to 2.4A when charge pump is not working for class_a qc + */ + if (chg->is_qc_class_a && chg->use_bq_pump) { + if (chg->pulse_cnt < HIGH_NUM_PULSE_THR + && chg->high_vbus_detected) { + vote(chg->usb_icl_votable, QC_A_CP_ICL_MAX_VOTER, false, + 0); + chg->high_vbus_detected = false; + } + } + break; + + case POWER_SUPPLY_DP_DM_FORCE_5V: + rc = smblib_force_vbus_voltage(chg, FORCE_5V_BIT); + chg->pulse_cnt = 0; + if (rc < 0) + pr_err("Failed to force 5V\n"); + break; + + default: + break; + } + + return rc; +} +#endif + +int smblib_disable_hw_jeita(struct smb_charger *chg, bool disable) +{ + int rc; + u8 mask; + + /* + * Disable h/w base JEITA compensation if s/w JEITA is enabled + */ + mask = JEITA_EN_COLD_SL_FCV_BIT + | JEITA_EN_HOT_SL_FCV_BIT + | JEITA_EN_HOT_SL_CCC_BIT + | JEITA_EN_COLD_SL_CCC_BIT, + rc = smblib_masked_write(chg, JEITA_EN_CFG_REG, mask, + disable ? 0 : mask); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure s/w jeita rc=%d\n", + rc); + return rc; + } + + return 0; +} + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +int smblib_get_prop_wireless_version(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + +/* + if (!chg->idtp_psy) { + chg->idtp_psy = power_supply_get_by_name("idt"); + if (!chg->idtp_psy) + return -EINVAL; + } +*/ + + chg->idtp_psy = power_supply_get_by_name("idt"); + if (chg->idtp_psy) + chg->wls_chip_psy = chg->idtp_psy; + else { + chg->wip_psy = power_supply_get_by_name("rx1618"); + if (chg->wip_psy) + chg->wls_chip_psy = chg->wip_psy; + else + return -EINVAL; + } + + if (chg->wls_chip_psy) + rc = power_supply_get_property(chg->wls_chip_psy, + POWER_SUPPLY_PROP_WIRELESS_VERSION, val); + return rc; +} +#endif + +static int smblib_set_sw_thermal_regulation(struct smb_charger *chg, + bool enable) +{ + int rc = 0; + + if (!(chg->wa_flags & SW_THERM_REGULATION_WA)) + return rc; + + if (enable) { + /* + * Configure min time to quickly address thermal + * condition. + */ + rc = smblib_masked_write(chg, SNARL_BARK_BITE_WD_CFG_REG, + SNARL_WDOG_TIMEOUT_MASK, SNARL_WDOG_TMOUT_62P5MS); + if (rc < 0) { + smblib_err(chg, "Couldn't configure snarl wdog tmout, rc=%d\n", + rc); + return rc; + } + + /* + * Schedule SW_THERM_REGULATION_WORK directly if USB input + * is suspended due to SW thermal regulation WA since WDOG + * IRQ won't trigger with input suspended. + */ + if (is_client_vote_enabled(chg->usb_icl_votable, + SW_THERM_REGULATION_VOTER)) { + vote(chg->awake_votable, SW_THERM_REGULATION_VOTER, + true, 0); + schedule_delayed_work(&chg->thermal_regulation_work, 0); + } + } else { + cancel_delayed_work_sync(&chg->thermal_regulation_work); + vote(chg->awake_votable, SW_THERM_REGULATION_VOTER, false, 0); + } smblib_dbg(chg, PR_MISC, "WDOG SNARL INT %s\n", enable ? "Enabled" : "Disabled"); @@ -2852,6 +4535,23 @@ static int smblib_update_thermal_readings(struct smb_charger *chg) #define THERM_REG_RECHECK_DELAY_1S 1000 /* 1 sec */ #define THERM_REG_RECHECK_DELAY_8S 8000 /* 8 sec */ + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static void smblib_report_soc_decimal_work(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + report_soc_decimal_work.work); + int quick_charge_type; + + quick_charge_type = smblib_get_quick_charge_type(chg); + + if (QUICK_CHARGE_TURBE == quick_charge_type) { + pr_info("report bms uevent when enter turbe charge!\n "); + power_supply_changed(chg->bms_psy); + } +} +#endif + static int smblib_process_thermal_readings(struct smb_charger *chg) { int rc = 0, wdog_timeout = SNARL_WDOG_TMOUT_8S; @@ -2955,6 +4655,10 @@ static int smblib_process_thermal_readings(struct smb_charger *chg) */ if (chg->thermal_status == TEMP_SHUT_DOWN_SMB) goto exit; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) + chg->bq_input_suspend = !!suspend_input; +#endif /* Suspend input if SHDN threshold reached */ vote(chg->dc_suspend_votable, SW_THERM_REGULATION_VOTER, @@ -3037,6 +4741,10 @@ int smblib_get_prop_dc_online(struct smb_charger *chg, { int rc = 0; u8 stat; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int dc_present; + union power_supply_propval pval = {0, }; +#endif if (chg->chg_param.smb_version == PMI632_SUBTYPE) { val->intval = 0; @@ -3048,20 +4756,48 @@ int smblib_get_prop_dc_online(struct smb_charger *chg, return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (is_client_vote_enabled_locked(chg->dc_suspend_votable, +#else if (is_client_vote_enabled(chg->dc_suspend_votable, +#endif CHG_TERMINATION_VOTER)) { rc = smblib_get_prop_dc_present(chg, val); return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_get_prop_dc_present(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return rc; + } + + dc_present = pval.intval; + + + if (dc_present && + get_client_vote_locked(chg->dc_suspend_votable, JEITA_VOTER) == 1) { + val->intval = true; + return rc; + } + + if (chg->fake_dc_on) { + val->intval = true; + return rc; + } +#endif + rc = smblib_read(chg, POWER_PATH_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read POWER_PATH_STATUS rc=%d\n", rc); return rc; } +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) smblib_dbg(chg, PR_REGISTER, "POWER_PATH_STATUS = 0x%02x\n", stat); +#endif val->intval = (stat & USE_DCIN_BIT) && (stat & VALID_INPUT_POWER_SOURCE_STS_BIT); @@ -3069,10 +4805,31 @@ int smblib_get_prop_dc_online(struct smb_charger *chg, return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_set_prop_wireless_wakelock(struct smb_charger *chg, + const union power_supply_propval *val) +{ + if (val->intval) { + vote(chg->awake_votable, DC_AWAKE_VOTER, true, 0); + //schedule_delayed_work(&chg->dc_input_current_work, + // msecs_to_jiffies(100)); //need enable + } else { + vote(chg->awake_votable, DC_AWAKE_VOTER, false, 0); + //cancel_delayed_work_sync(&chg->dc_input_current_work); + } + return 0; +} +#endif + int smblib_get_prop_dc_current_max(struct smb_charger *chg, union power_supply_propval *val) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + val->intval = get_effective_result_locked(chg->dc_icl_votable); + return 0; +#else return smblib_get_charge_param(chg, &chg->param.dc_icl, &val->intval); +#endif } int smblib_get_prop_dc_voltage_max(struct smb_charger *chg, @@ -3112,7 +4869,14 @@ int smblib_get_prop_dc_voltage_now(struct smb_charger *chg, int smblib_set_prop_dc_current_max(struct smb_charger *chg, const union power_supply_propval *val) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int rc; + + rc = vote(chg->dc_icl_votable, DCIN_ADAPTER_VOTER, true, val->intval); + return rc; +#else return smblib_set_charge_param(chg, &chg->param.dc_icl, val->intval); +#endif } #define DCIN_AICL_RERUN_DELAY_MS 5000 @@ -3120,6 +4884,9 @@ int smblib_set_prop_voltage_wls_output(struct smb_charger *chg, const union power_supply_propval *val) { int rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + union power_supply_propval pval = {0, }; +#endif if (!chg->wls_psy) { chg->wls_psy = power_supply_get_by_name("wireless"); @@ -3127,6 +4894,35 @@ int smblib_set_prop_voltage_wls_output(struct smb_charger *chg, return -ENODEV; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = power_supply_get_property(chg->wls_psy, + POWER_SUPPLY_PROP_TX_ADAPTER, + &pval); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (pval.intval == 9 || pval.intval == 11 || pval.intval == 12 || pval.intval == 13 || pval.intval == 14) { +#else + if (pval.intval == 9 || pval.intval == 11 || pval.intval == 12) { +#endif + if (val->intval >= 9200000 && val->intval < 9500000) + vote(chg->dc_icl_votable, DCIN_LIMIT_VOTER, true, 2000000); + else if (val->intval > 9500000) + vote(chg->dc_icl_votable, DCIN_LIMIT_VOTER, true, 1800000); + else + vote(chg->dc_icl_votable, DCIN_LIMIT_VOTER, false, 0); + } else if (pval.intval == 6) { + if (val->intval > 9000000 && val->intval <= 9500000) + vote(chg->dc_icl_votable, DCIN_LIMIT_VOTER, true, 1100000); + else if (val->intval > 9500000) + vote(chg->dc_icl_votable, DCIN_LIMIT_VOTER, true, 1000000); + else + vote(chg->dc_icl_votable, DCIN_LIMIT_VOTER, false, 0); + } else { + smblib_dbg(chg, PR_WLS, "WLS chg type error %d\n", pval.intval); + return rc; + } +#endif + rc = power_supply_set_property(chg->wls_psy, POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, val); @@ -3202,6 +4998,23 @@ int smblib_set_prop_dc_reset(struct smb_charger *chg) return rc; } +#ifdef CONFIG_MACH_XIAOMI_NABU +void smblib_set_prop_pen_mac(struct smb_charger *chg, + const union power_supply_propval *val) +{ + smblib_dbg(chg, PR_WLS, "pen mac raw %llx\n", val->int64val); + chg->pen_bt_mac = val->int64val; + if (!chg->wls_psy) { + chg->wls_psy = power_supply_get_by_name("wireless"); + if (!chg->wls_psy) { + smblib_err(chg, "no wireless power supply, return\n"); + return; + } + } + power_supply_changed(chg->wls_psy); +} +#endif + /******************* * USB PSY GETTERS * *******************/ @@ -3227,18 +5040,77 @@ int smblib_get_prop_usb_online(struct smb_charger *chg, { int rc = 0; u8 stat; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int usb_present; + union power_supply_propval pval = {0, }; +#endif if (get_client_vote_locked(chg->usb_icl_votable, USER_VOTER) == 0) { val->intval = false; return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (get_client_vote_locked(chg->usb_icl_votable, JEITA_VOTER) == 0) { + /* show online when JEITA_VOTER 0mA is vote to improve user experience */ + val->intval = true; + return rc; + } +#endif + if (is_client_vote_enabled_locked(chg->usb_icl_votable, CHG_TERMINATION_VOTER)) { rc = smblib_get_prop_usb_present(chg, val); return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) { + rc = smblib_get_prop_usb_present(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return rc; + } + + usb_present = pval.intval; + + if (usb_present && chg->use_bq_pump + && (get_client_vote_locked(chg->usb_icl_votable, + MAIN_CHG_VOTER) == MAIN_CHARGER_STOP_ICL)) { + val->intval = true; + return rc; + } + } +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + rc = smblib_get_prop_usb_present(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return rc; + } + + usb_present = pval.intval; + + if (usb_present && chg->typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER) { + val->intval = true; + return rc; + } + + if (usb_present && + get_client_vote_locked(chg->usb_icl_votable, JEITA_VOTER) == 0) { + val->intval = true; + return rc; + } + + if (usb_present && chg->power_good_en) { + /* show online when insert usb in wireless charging */ + if (chg->typec_mode == POWER_SUPPLY_TYPEC_SINK) + val->intval = false; + else + val->intval = true; + return rc; + } +#endif + rc = smblib_read(chg, POWER_PATH_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read POWER_PATH_STATUS rc=%d\n", @@ -3467,6 +5339,52 @@ int smblib_get_prop_vph_voltage_now(struct smb_charger *chg, return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +/* + * we use usb in adc for distinguish qc_a and qc_b, so remain this func + * for this purpose + */ +int smblib_get_usb_in_voltage_now(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc, ret = 0; + + /* set 12V OV to 14.6V */ + /* if (chg->smb_version == PM8150B_SUBTYPE) { + rc = smblib_masked_write(chg, USB_ENG_SSUPPLY_USB2_REG, + ENG_SSUPPLY_12V_OV_OPT_BIT, + ENG_SSUPPLY_12V_OV_OPT_BIT); + if (rc < 0) { + smblib_err(chg, "Couldn't set USB_ENG_SSUPPLY_USB2_REG rc=%d\n", + rc); + return -ENODATA; + } + } */ + + if (chg->iio.usbin_v_chan) { + rc = iio_read_channel_processed(chg->iio.usbin_v_chan, + &val->intval); + if (rc < 0) + ret = -ENODATA; + } else { + ret = -ENODATA; + } + + /* restore 12V OV to 13.2V */ + /* if (chg->smb_version == PM8150B_SUBTYPE) { + rc = smblib_masked_write(chg, USB_ENG_SSUPPLY_USB2_REG, + ENG_SSUPPLY_12V_OV_OPT_BIT, 0); + if (rc < 0) { + smblib_err(chg, "Couldn't restore USB_ENG_SSUPPLY_USB2_REG rc=%d\n", + rc); + ret = -ENODATA; + } + } */ + + return ret; +} +#endif + bool smblib_rsbux_low(struct smb_charger *chg, int r_thr) { int r_sbu1, r_sbu2; @@ -3600,6 +5518,10 @@ static int smblib_get_prop_ufp_mode(struct smb_charger *chg) { int rc; u8 stat; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + union power_supply_propval val = {0, }; + int usb_present = 0; +#endif rc = smblib_read(chg, TYPE_C_SNK_STATUS_REG, &stat); if (rc < 0) { @@ -3620,11 +5542,37 @@ static int smblib_get_prop_ufp_mode(struct smb_charger *chg) case SNK_DAM_500MA_BIT: case SNK_DAM_1500MA_BIT: case SNK_DAM_3000MA_BIT: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + return POWER_SUPPLY_TYPEC_SOURCE_DEFAULT; +#else return POWER_SUPPLY_TYPEC_SINK_DEBUG_ACCESSORY; +#endif default: break; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* workaround for scp cable or similar A TO C cables */ + rc = smblib_read(chg, TYPE_C_SNK_DEBUG_ACC_STATUS_REG, &stat); + if (rc < 0) { + smblib_err(chg, "Couldn't read TYPE_C_STATUS_1 rc=%d\n", rc); + return POWER_SUPPLY_TYPEC_NONE; // git + } // git + + rc = smblib_get_prop_usb_present(chg, &val); + if (rc < 0) + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + else + usb_present = val.intval; + + if (chg->snk_debug_acc_detected && usb_present) { + return POWER_SUPPLY_TYPEC_SOURCE_DEFAULT; + } + if (stat & SNK_DEBUG_ACC_RPSTD_PRSTD_BIT && usb_present) { + chg->snk_debug_acc_detected = true; + return POWER_SUPPLY_TYPEC_SOURCE_DEFAULT; + } +#endif return POWER_SUPPLY_TYPEC_NONE; } @@ -3642,7 +5590,9 @@ static int smblib_get_prop_dfp_mode(struct smb_charger *chg) rc); return POWER_SUPPLY_TYPEC_NONE; } +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) smblib_dbg(chg, PR_REGISTER, "TYPE_C_SRC_STATUS_REG = 0x%02x\n", stat); +#endif switch (stat & DETECTED_SNK_TYPE_MASK) { case AUDIO_ACCESS_RA_RA_BIT: @@ -4024,6 +5974,10 @@ static int smblib_get_typec_connector_temp_status(struct smb_charger *chg) return POWER_SUPPLY_HEALTH_COOL; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define HVDCP_START_CURRENT_UA 1000000 +#endif + int smblib_get_skin_temp_status(struct smb_charger *chg) { int rc; @@ -4077,6 +6031,7 @@ int smblib_get_prop_connector_health(struct smb_charger *chg) return POWER_SUPPLY_HEALTH_COOL; } +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) static int get_rp_based_dcp_current(struct smb_charger *chg, int typec_mode) { int rp_ua; @@ -4094,6 +6049,7 @@ static int get_rp_based_dcp_current(struct smb_charger *chg, int typec_mode) return rp_ua; } +#endif /******************* * USB PSY SETTERS * @@ -4116,14 +6072,40 @@ int smblib_set_prop_pd_current_max(struct smb_charger *chg, return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define FLOAT_CHARGER_UA 1000000 +#define SUSPEND_CURRENT_UA 2000 +#endif static int smblib_handle_usb_current(struct smb_charger *chg, int usb_current) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int rc = 0, typec_mode; +#else int rc = 0, rp_ua, typec_mode; +#endif union power_supply_propval val = {0, }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool is_float = false; +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_FLOAT + && (usb_current == SUSPEND_CURRENT_UA)) + is_float = true; + + if ((usb_current > 0 && usb_current < USBIN_500MA) + || (usb_current == USBIN_900MA)) + usb_current = USBIN_500MA; +#endif if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_FLOAT) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (usb_current == -ETIMEDOUT || is_float) { +#else if (usb_current == -ETIMEDOUT) { +#endif +#ifndef CONFIG_MACH_XIAOMI_SM8150 if ((chg->float_cfg & FLOAT_OPTIONS_MASK) == FORCE_FLOAT_SDP_CFG_BIT) { /* @@ -4138,6 +6120,7 @@ static int smblib_handle_usb_current(struct smb_charger *chg, rc); return rc; } +#endif if (chg->connector_type == POWER_SUPPLY_CONNECTOR_TYPEC) { @@ -4146,10 +6129,20 @@ static int smblib_handle_usb_current(struct smb_charger *chg, * based of Rp. */ typec_mode = smblib_get_prop_typec_mode(chg); +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) rp_ua = get_rp_based_dcp_current(chg, typec_mode); +#endif +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (rp_ua == DCP_CURRENT_UA) + rp_ua = FLOAT_CHARGER_UA; +#endif rc = vote(chg->usb_icl_votable, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SW_ICL_MAX_VOTER, true, FLOAT_CHARGER_UA); +#else SW_ICL_MAX_VOTER, true, rp_ua); +#endif if (rc < 0) return rc; } else { @@ -4165,6 +6158,9 @@ static int smblib_handle_usb_current(struct smb_charger *chg, * real_charger_type */ chg->real_charger_type = POWER_SUPPLY_TYPE_USB; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->usb_psy_desc.type = POWER_SUPPLY_TYPE_USB; +#endif rc = vote(chg->usb_icl_votable, USB_PSY_VOTER, true, usb_current); if (rc < 0) @@ -4220,7 +6216,11 @@ int smblib_set_prop_sdp_current_max(struct smb_charger *chg, } /* handle the request only when USB is present */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (pval.intval && (val->intval != 0)) +#else if (pval.intval) +#endif rc = smblib_handle_usb_current(chg, val->intval); } else if (chg->system_suspend_supported) { if (val->intval <= USBIN_25MA) @@ -4233,7 +6233,35 @@ int smblib_set_prop_sdp_current_max(struct smb_charger *chg, return rc; } -int smblib_set_prop_boost_current(struct smb_charger *chg, +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_get_prop_type_recheck(struct smb_charger *chg, + union power_supply_propval *val) +{ + int status = 0; + + if (chg->recheck_charger) + status |= BIT(0) << 8; + + status |= chg->precheck_charger_type << 4; + status |= chg->real_charger_type; + + val->intval = status; + + return 0; +} + +int smblib_set_prop_type_recheck(struct smb_charger *chg, + const union power_supply_propval *val) +{ + if (val->intval == 0) { + cancel_delayed_work_sync(&chg->charger_type_recheck); + chg->recheck_charger = false; + } + return 0; +} +#endif + +int smblib_set_prop_boost_current(struct smb_charger *chg, const union power_supply_propval *val) { int rc = 0; @@ -4478,6 +6506,16 @@ int smblib_set_prop_pd_active(struct smb_charger *chg, smblib_apsd_enable(chg, !chg->pd_active); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!chg->pd && chg->use_bq_pump) { + chg->pd = devm_usbpd_get_by_phandle(chg->dev, + "qcom,usbpd-phandle"); + if (IS_ERR_OR_NULL(chg->pd)) + pr_err("Failed to get pd handle %ld\n", + PTR_ERR(chg->pd)); + } +#endif + update_sw_icl_max(chg, apsd->pst); if (chg->pd_active) { @@ -4495,6 +6533,19 @@ int smblib_set_prop_pd_active(struct smb_charger *chg, vote(chg->usb_icl_votable, USB_PSY_VOTER, false, 0); vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, false, 0); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /*set the icl to PD_UNVERIFED_CURRENT when pd is not verifed*/ + if (!chg->pd_verifed) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = vote(chg->fcc_votable, PD_VERIFED_VOTER, true, PD_UNVERIFED_CURRENT); +#else + rc = vote(chg->usb_icl_votable, PD_VERIFED_VOTER, true, PD_UNVERIFED_CURRENT); +#endif + if (rc < 0) + smblib_err(chg, "Couldn't unvote PD_VERIFED_VOTER, rc=%d\n", rc); + } +#endif + /* * For PPS, Charge Pump is preferred over parallel charger if * present. @@ -4507,7 +6558,21 @@ int smblib_set_prop_pd_active(struct smb_charger *chg, if (rc < 0) dev_err(chg->dev, "Couldn't enable secondary charger rc=%d\n", rc); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + else + chg->cp_reason = POWER_SUPPLY_CP_PPS; +#endif + } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->pd_active == POWER_SUPPLY_PD_PPS_ACTIVE + && chg->six_pin_step_charge_enable) { + /* start six pin battery step charge monitor work */ + schedule_delayed_work(&chg->six_pin_batt_step_chg_work, + msecs_to_jiffies(STEP_CHG_DELAYED_START_MS)); } + + smblib_therm_charging(chg); +#endif } else { vote(chg->usb_icl_votable, PD_VOTER, false, 0); vote(chg->limited_irq_disable_votable, CHARGER_TYPE_VOTER, @@ -4534,7 +6599,18 @@ int smblib_set_prop_pd_active(struct smb_charger *chg, smblib_usb_pd_adapter_allowance_override(chg, !!chg->pd_active ? FORCE_5V : FORCE_NULL); + +#if !(defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU))) smblib_update_usb_type(chg); +#else + if (!chg->fake_usb_insertion) + smblib_update_usb_type(chg); +#endif + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + smblib_therm_charging(chg); +#endif + power_supply_changed(chg->usb_psy); return rc; } @@ -4626,6 +6702,11 @@ static int smblib_soft_jeita_arb_wa(struct smb_charger *chg) int rc = 0; bool soft_jeita; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* we still use old soft jeita method */ + return 0; +#endif + rc = smblib_get_prop_batt_health(chg, &pval); if (rc < 0) { smblib_err(chg, "Couldn't get battery health rc=%d\n", rc); @@ -4766,12 +6847,34 @@ int smblib_get_charge_current(struct smb_charger *chg, typec_source_rd = smblib_get_prop_ufp_mode(chg); +#ifdef CONFIG_MACH_XIAOMI_NABU + /* QC 3.5 adapter */ + if (chg->qc3p5_supported && + (apsd_result->pst == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) && + (chg->qc3p5_power_limit_w == 40)) { + *total_current_ua = HVDCP3P5_40W_CURRENT_UA; + return 0; + } +#endif + /* QC 2.0/3.0 adapter */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (apsd_result->bit & QC_3P0_BIT) { +#else if (apsd_result->bit & (QC_3P0_BIT | QC_2P0_BIT)) { +#endif *total_current_ua = HVDCP_CURRENT_UA; return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* QC 2.0 adapter */ + if (apsd_result->bit & QC_2P0_BIT) { + *total_current_ua = HVDCP2_CURRENT_UA; + return 0; + } +#endif + if (non_compliant && !chg->typec_legacy_use_rp_icl) { switch (apsd_result->bit) { case CDP_CHARGER_BIT: @@ -4952,6 +7055,35 @@ static void smblib_eval_chg_termination(struct smb_charger *chg, u8 batt_status) } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +irqreturn_t dcin_uv_handler(int irq, void *data) +{ + struct smb_irq_data *irq_data = data; + struct smb_charger *chg = irq_data->parent_data; + + int rc; + u8 stat; + + rc = smblib_read(chg, POWER_PATH_STATUS_REG, &stat); + if (rc < 0) { + smblib_err(chg, "Couldn't read POWER_PATH_STATUS rc=%d\n", + rc); + return IRQ_HANDLED; + } + + if ((stat & POWER_PATH_MASK) == 0x2) { /*power by battery*/ + chg->fake_dc_on = 1; /*use for delay 1.8s*/ + chg->fake_dc_flag = 1; + schedule_delayed_work(&chg->dc_plug_out_delay_work, + msecs_to_jiffies(1800)); + vote(chg->awake_votable, DC_UV_AWAKE_VOTER, true, 0); + } + smblib_dbg(chg, PR_WLS, "Delay dc plug out and power path 0x%x\n", stat); + + return IRQ_HANDLED; +} +#endif + irqreturn_t chg_state_change_irq_handler(int irq, void *data) { struct smb_irq_data *irq_data = data; @@ -4995,6 +7127,12 @@ irqreturn_t batt_temp_changed_irq_handler(int irq, void *data) return IRQ_HANDLED; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* we still use old soft jeita method */ + rerun_election(chg->fcc_votable); + power_supply_changed(chg->batt_psy); +#endif + return IRQ_HANDLED; } @@ -5092,6 +7230,9 @@ irqreturn_t usbin_uv_irq_handler(int irq, void *data) /* Workaround for non-QC2.0-compliant chargers follows */ if (!chg->qc2_unsupported_voltage && +#ifdef CONFIG_MACH_XIAOMI_SM8150 + !chg->qc2_unsupported && +#endif apsd->pst == POWER_SUPPLY_TYPE_USB_HVDCP) { rc = smblib_read(chg, QC_CHANGE_STATUS_REG, &stat); if (rc < 0) @@ -5137,6 +7278,22 @@ irqreturn_t usbin_uv_irq_handler(int irq, void *data) rc); smblib_rerun_apsd(chg); + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + pr_info("qc2_unsupported charger detected\n"); + rc = smblib_force_vbus_voltage(chg, FORCE_5V_BIT); + if (rc < 0) + pr_err("Failed to force 5V\n"); + rc = smblib_set_adapter_allowance(chg, USBIN_ADAPTER_ALLOW_5V);; + if (rc < 0) + pr_err("Failed to set adapter allowance to 5V\n"); + rc = smblib_set_opt_switcher_freq(chg, chg->chg_freq.freq_5V); + if (rc < 0) + pr_err("Failed to set chg_freq.freq_5V\n"); + vote(chg->usb_icl_votable, QC2_UNSUPPORTED_VOTER, true, + QC2_UNSUPPORTED_UA); + chg->qc2_unsupported = true; +#endif } return IRQ_HANDLED; @@ -5196,6 +7353,243 @@ irqreturn_t icl_change_irq_handler(int irq, void *data) return IRQ_HANDLED; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static void smblib_cc_un_compliant_charge_work(struct work_struct *work) +{ + union power_supply_propval val = {0, }; + int rc, usb_present = 0; + + struct smb_charger *chg = container_of(work, struct smb_charger, + cc_un_compliant_charge_work.work); + + rc = smblib_get_prop_usb_present(chg, &val); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return; + } + + usb_present = val.intval; + + /* + * workaround for typec audio/charger connector charge issue + * when firstly insert earphone then insert charger, it will trigger usbin_plugin irq, + * but not trigger typec_attach_detach irq. so need force set charger type and ICL here. + */ + if (usb_present && chg->typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER) { + chg->real_charger_type = POWER_SUPPLY_TYPE_USB_FLOAT; + chg->usb_psy_desc.type = POWER_SUPPLY_TYPE_USB_FLOAT; + if ((strcmp(get_effective_client(chg->usb_icl_votable), "OTG_VOTER") == 0) && + (get_effective_result(chg->usb_icl_votable) == 0)) + vote(chg->usb_icl_votable, OTG_VOTER, false, 0); + + if (get_client_vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER) != 500000) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, 500000); + } + + /* + * if CC pin of C to A cable is not connected to the receptacle + * or CC pin is bad or short to VBUS or C to C cable CC line is float, + * disable APSD CC trigger since pm8150b CC protection voltage + * threshold is very high (22V), our wire charging maxium charging + * vbus is below 13.2V. + */ + if (usb_present + && (chg->typec_mode == POWER_SUPPLY_TYPEC_NONE || + chg->typec_mode == POWER_SUPPLY_TYPEC_NON_COMPLIANT || + chg->snk_debug_acc_detected == true) + && (chg->cc_un_compliant_detected == false)) { + chg->cc_un_compliant_detected = true; + //smblib_apsd_enable(chg, true); + smblib_hvdcp_detect_enable(chg, true); + smblib_rerun_apsd_if_required(chg); + } +} + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static void smb_check_init_boot(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + check_init_boot.work); + first_boot_flag = true; + if (chg->usb_psy) + power_supply_changed(chg->usb_psy); +} + +#ifdef CONFIG_MACH_XIAOMI_NABU +static int fv_over_limit_times; +#define OVER_FV_MAX_TIMES 10 +static void smblib_check_vbat_work(struct work_struct *work) +{ + int rc; + int effective_fv_uv; + union power_supply_propval val; + + struct smb_charger *chg = container_of(work, struct smb_charger, + check_vbat_work.work); + if (!chg->cp_psy) { + chg->cp_psy = power_supply_get_by_name("bq2597x-standalone"); + if (!chg->cp_psy){ + chg->cp_psy = power_supply_get_by_name("ln8000"); + if (!chg->cp_psy){ + pr_err("cp_psy not found\n"); + return; + } + } + } + + rc = power_supply_get_property(chg->cp_psy, + POWER_SUPPLY_PROP_MODEL_NAME, &val); + if (rc < 0) { + pr_err("Error in getting charge IC name, rc=%d\n", rc); + return; + } + + if (strcmp(val.strval, "bq2597x-standalone") == 0) { + rc = power_supply_get_property(chg->cp_psy, + POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, &val); + pr_err("getting ti battery voltage = %d\n", val.intval); + if (rc < 0) { + pr_err("Error in getting ti battery voltage, rc=%d\n", rc); + return; + } + if (val.intval > 4800) { + if (fv_over_limit_times++ > OVER_FV_MAX_TIMES) { + fv_over_limit_times = 0; + effective_fv_uv = get_effective_result_locked(chg->fv_votable); + vote(chg->fv_votable, BATT_BQ2597X_VOTER, true, effective_fv_uv - 10000); + } + } + } + schedule_delayed_work(&chg->check_vbat_work, msecs_to_jiffies(200)); + +} +#endif + +#define REDUCED_CURRENT 500000 +static int smblib_get_effective_fcc_val(struct smb_charger *chg) +{ + int effective_fcc_val = 0; + + effective_fcc_val = get_effective_result(chg->fcc_votable); + return effective_fcc_val; +} + +static int check_reduce_fcc_condition(struct smb_charger *chg) +{ + union power_supply_propval val = {0, }; + int rc, ibat = 0; + int effective_fcc = 0; + + if (!chg->cp_psy) { + chg->cp_psy = power_supply_get_by_name("bq2597x-standalone"); + } + +#ifdef CONFIG_MACH_XIAOMI_NABU + if (!chg->cp_psy){ + chg->cp_psy = power_supply_get_by_name("ln8000"); + } +#endif + + if (!chg->cp_psy) { + pr_err("cp_psy not found\n"); + return 0; + } + + rc = power_supply_get_property(chg->cp_psy, + POWER_SUPPLY_PROP_CHARGING_ENABLED, &val); + if (rc < 0) { + pr_err("Error in getting cp charge enable, rc=%d\n", rc); + return 0; + } + chg->cp_charge_enabled = !!val.intval; + + rc = power_supply_get_property(chg->batt_psy, POWER_SUPPLY_PROP_STATUS, + &val); + if (rc < 0) { + pr_err("Error in getting charging status, rc=%d\n", rc); + return 0; + } + chg->charge_status = val.intval; + + rc = power_supply_get_property(chg->batt_psy, + POWER_SUPPLY_PROP_CHARGE_TYPE, &val); + if (rc < 0) { + pr_err("Error in getting charge type, rc=%d\n", rc); + return 0; + } + chg->charge_type = val.intval; + + rc = power_supply_get_property(chg->batt_psy, POWER_SUPPLY_PROP_HEALTH, + &val); + if (rc < 0) { + pr_err("Error in getting charging status, rc=%d\n", rc); + return 0; + } + chg->batt_health = val.intval; + + pr_info("cp_charge_enabled(%d), charge_status(%d), charge_type(%d), batt_health(%d)\n", + chg->cp_charge_enabled, chg->charge_status, chg->charge_type, chg->batt_health); + + /* should add battery health later */ + if (!chg->cp_charge_enabled || + (chg->charge_status != POWER_SUPPLY_STATUS_CHARGING) || + (chg->charge_type != POWER_SUPPLY_CHARGE_TYPE_FAST) || + (chg->batt_health != POWER_SUPPLY_HEALTH_GOOD)) + return 0; + + rc = smblib_get_prop_from_bms(chg, + POWER_SUPPLY_PROP_CURRENT_NOW, &val); + if (rc < 0) + return 0; + + ibat = val.intval/1000; + if (ibat > -450) { + pr_info("Skip CHG ESR, Fails IBAT ibat(%d)\n", ibat); + return 0; + } + + effective_fcc = smblib_get_effective_fcc_val(chg); + if (effective_fcc < 0) + return 0; + + return effective_fcc; +} + +/* In order to calculate battery esr */ +static void reduce_fcc_work(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + reduce_fcc_work.work); + int effective_fcc; + int esr_work_time = ESR_WORK_TIME_180S; + bool reduce_fcc = false; + + effective_fcc = check_reduce_fcc_condition(chg); + if (effective_fcc > 0) { + if (chg->esr_work_status == ESR_CHECK_FCC_NOLIMIT) { + effective_fcc -= REDUCED_CURRENT; + chg->esr_work_status = ESR_CHECK_FCC_LIMITED; + reduce_fcc = true; + esr_work_time = ESR_WORK_TIME_2S; + } else { + chg->esr_work_status = ESR_CHECK_FCC_NOLIMIT; + reduce_fcc = false; + esr_work_time = ESR_WORK_TIME_180S; + } + } else { + chg->esr_work_status = ESR_CHECK_FCC_NOLIMIT; + reduce_fcc = false; + esr_work_time = ESR_WORK_TIME_180S; + pr_info("calculate esr condition not satisfy.\n"); + } + + vote(chg->fcc_votable, ESR_WORK_VOTER, reduce_fcc, effective_fcc); + schedule_delayed_work(&chg->reduce_fcc_work, + msecs_to_jiffies(esr_work_time)); +} +#endif +#endif + static void smblib_micro_usb_plugin(struct smb_charger *chg, bool vbus_rising) { if (!vbus_rising) { @@ -5205,6 +7599,9 @@ static void smblib_micro_usb_plugin(struct smb_charger *chg, bool vbus_rising) } } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static void typec_src_removal(struct smb_charger *chg); +#endif void smblib_usb_plugin_hard_reset_locked(struct smb_charger *chg) { int rc; @@ -5222,9 +7619,17 @@ void smblib_usb_plugin_hard_reset_locked(struct smb_charger *chg) vbus_rising = (bool)(stat & USBIN_PLUGIN_RT_STS_BIT); if (vbus_rising) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* hold chg_awake wakeup source when charger is present */ + vote(chg->awake_votable, CHG_AWAKE_VOTER, true, 0); +#endif /* Remove FCC_STEPPER 1.5A init vote to allow FCC ramp up */ if (chg->fcc_stepper_enable) vote(chg->fcc_votable, FCC_STEPPER_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->six_pin_step_charge_enable) + smblib_get_start_vbat_before_step_charge(chg); +#endif } else { if (chg->wa_flags & BOOST_BACK_WA) { data = chg->irq_info[SWITCHER_POWER_OK_IRQ].irq_data; @@ -5239,6 +7644,28 @@ void smblib_usb_plugin_hard_reset_locked(struct smb_charger *chg) } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cancel_delayed_work_sync(&chg->charger_type_recheck); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->hvdcp_recheck_status = false; +#endif + chg->recheck_charger = false; + chg->precheck_charger_type = POWER_SUPPLY_TYPE_UNKNOWN; + if (chg->cc_un_compliant_detected) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* disable apsd if cc_un_compliant detected after plug out */ + //smblib_apsd_enable(chg, false); + typec_src_removal(chg); +#else + smblib_hvdcp_detect_enable(chg, false); +#endif + chg->cc_un_compliant_detected = false; + } + + /* clear chg_awake wakeup source when charger is absent */ + vote(chg->awake_votable, CHG_AWAKE_VOTER, false, 0); +#endif + /* Force 1500mA FCC on USB removal if fcc stepper is enabled */ if (chg->fcc_stepper_enable) vote(chg->fcc_votable, FCC_STEPPER_VOTER, @@ -5265,131 +7692,614 @@ void smblib_usb_plugin_locked(struct smb_charger *chg) return; } - vbus_rising = (bool)(stat & USBIN_PLUGIN_RT_STS_BIT); - smblib_set_opt_switcher_freq(chg, vbus_rising ? chg->chg_freq.freq_5V : - chg->chg_freq.freq_removal); + vbus_rising = (bool)(stat & USBIN_PLUGIN_RT_STS_BIT); + smblib_set_opt_switcher_freq(chg, vbus_rising ? chg->chg_freq.freq_5V : + chg->chg_freq.freq_removal); + + if (vbus_rising) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* when vbus present, enable batt_temp irq wakeup */ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->irq_info[BAT_TEMP_IRQ].irq && !chg->batt_temp_irq_enabled) { + enable_irq_wake(chg->irq_info[BAT_TEMP_IRQ].irq); + chg->batt_temp_irq_enabled = true; + } +#endif + if (smblib_get_prop_dfp_mode(chg) != POWER_SUPPLY_TYPEC_NONE + && smblib_get_prop_dfp_mode(chg) + != POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER) { + chg->fake_usb_insertion = true; + return; + } + + /* hold a wakeup source when charger is present */ + vote(chg->awake_votable, CHG_AWAKE_VOTER, true, 0); +#endif + cancel_delayed_work_sync(&chg->pr_swap_detach_work); + vote(chg->awake_votable, DETACH_DETECT_VOTER, false, 0); + rc = smblib_request_dpdm(chg, true); + if (rc < 0) + smblib_err(chg, "Couldn't to enable DPDM rc=%d\n", rc); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + smblib_check_batt_authentic(chg); +#endif + + /* Enable SW Thermal regulation */ + rc = smblib_set_sw_thermal_regulation(chg, true); + if (rc < 0) + smblib_err(chg, "Couldn't start SW thermal regulation WA, rc=%d\n", + rc); + + /* Remove FCC_STEPPER 1.5A init vote to allow FCC ramp up */ + if (chg->fcc_stepper_enable) + vote(chg->fcc_votable, FCC_STEPPER_VOTER, false, 0); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->six_pin_step_charge_enable) + smblib_get_start_vbat_before_step_charge(chg); +#endif + + /* Schedule work to enable parallel charger */ + vote(chg->awake_votable, PL_DELAY_VOTER, true, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!first_boot_flag) + schedule_delayed_work(&chg->check_init_boot, msecs_to_jiffies(18000)); +#endif + schedule_delayed_work(&chg->pl_enable_work, + msecs_to_jiffies(PL_DELAY_MS)); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + schedule_delayed_work(&chg->charger_type_recheck, + msecs_to_jiffies(CHARGER_RECHECK_DELAY_MS)); + schedule_delayed_work(&chg->cc_un_compliant_charge_work, + msecs_to_jiffies(CC_UN_COMPLIANT_START_DELAY_MS)); +#ifdef CONFIG_MACH_XIAOMI_NABU + schedule_delayed_work(&chg->check_vbat_work, msecs_to_jiffies(200)); +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) + schedule_delayed_work(&chg->reduce_fcc_work, + msecs_to_jiffies(ESR_WORK_TIME_180S)); +#endif +#endif + } else { +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* when vbus absent, disable batt_temp irq wakeup */ + if (chg->irq_info[BAT_TEMP_IRQ].irq && chg->batt_temp_irq_enabled) { + disable_irq_wake(chg->irq_info[BAT_TEMP_IRQ].irq); + chg->batt_temp_irq_enabled = false; + } +#endif + + if (chg->fake_usb_insertion) { + chg->fake_usb_insertion = false; + return; + } + + cancel_delayed_work_sync(&chg->charger_type_recheck); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) { + cancel_delayed_work_sync(&chg->reduce_fcc_work); + vote(chg->fcc_votable, ESR_WORK_VOTER, false, 0); + } +#endif +#endif + + /* Disable SW Thermal Regulation */ + rc = smblib_set_sw_thermal_regulation(chg, false); + if (rc < 0) + smblib_err(chg, "Couldn't stop SW thermal regulation WA, rc=%d\n", + rc); + + if (chg->wa_flags & BOOST_BACK_WA) { + data = chg->irq_info[SWITCHER_POWER_OK_IRQ].irq_data; + if (data) { + wdata = &data->storm_data; + update_storm_count(wdata, + WEAK_CHG_STORM_COUNT); + vote(chg->usb_icl_votable, BOOST_BACK_VOTER, + false, 0); + vote(chg->usb_icl_votable, WEAK_CHARGER_VOTER, + false, 0); + } + } + + /* Force 1500mA FCC on removal if fcc stepper is enabled */ + if (chg->fcc_stepper_enable) + vote(chg->fcc_votable, FCC_STEPPER_VOTER, + true, 1500000); + + if (chg->wa_flags & WEAK_ADAPTER_WA) { + chg->aicl_5v_threshold_mv = + chg->default_aicl_5v_threshold_mv; + chg->aicl_cont_threshold_mv = + chg->default_aicl_cont_threshold_mv; + + smblib_set_charge_param(chg, + &chg->param.aicl_5v_threshold, + chg->aicl_5v_threshold_mv); + smblib_set_charge_param(chg, + &chg->param.aicl_cont_threshold, + chg->aicl_cont_threshold_mv); + chg->aicl_max_reached = false; + + if (chg->chg_param.smb_version == PMI632_SUBTYPE) + schgm_flash_torch_priority(chg, + TORCH_BUCK_MODE); + + data = chg->irq_info[USBIN_UV_IRQ].irq_data; + if (data) { + wdata = &data->storm_data; + reset_storm_count(wdata); + } + vote(chg->usb_icl_votable, AICL_THRESHOLD_VOTER, + false, 0); + } + + rc = smblib_request_dpdm(chg, false); + if (rc < 0) + smblib_err(chg, "Couldn't disable DPDM rc=%d\n", rc); + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->cc_un_compliant_detected) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* disable apsd if cc_un_compliant detected after plug out */ + //smblib_apsd_enable(chg, false); + typec_src_removal(chg); +#else + smblib_hvdcp_detect_enable(chg, false); +#endif + chg->cc_un_compliant_detected = false; + } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->hvdcp_recheck_status = false; +#endif + chg->recheck_charger = false; + chg->precheck_charger_type = POWER_SUPPLY_TYPE_UNKNOWN; + /* clear chg_awake wakeup source when charger is absent */ + vote(chg->awake_votable, CHG_AWAKE_VOTER, false, 0); +#endif + smblib_update_usb_type(chg); + } + + if (chg->connector_type == POWER_SUPPLY_CONNECTOR_MICRO_USB) + smblib_micro_usb_plugin(chg, vbus_rising); + + vote(chg->temp_change_irq_disable_votable, DEFAULT_VOTER, + !vbus_rising, 0); + + power_supply_changed(chg->usb_psy); + if (chg->dual_role) + dual_role_instance_changed(chg->dual_role); + smblib_dbg(chg, PR_INTERRUPT, "IRQ: usbin-plugin %s\n", + vbus_rising ? "attached" : "detached"); +} + +irqreturn_t usb_plugin_irq_handler(int irq, void *data) +{ + struct smb_irq_data *irq_data = data; + struct smb_charger *chg = irq_data->parent_data; + + if (chg->pd_hard_reset) + smblib_usb_plugin_hard_reset_locked(chg); + else + smblib_usb_plugin_locked(chg); + + return IRQ_HANDLED; +} + +static void smblib_handle_slow_plugin_timeout(struct smb_charger *chg, + bool rising) +{ + smblib_dbg(chg, PR_INTERRUPT, "IRQ: slow-plugin-timeout %s\n", + rising ? "rising" : "falling"); +} + +static void smblib_handle_sdp_enumeration_done(struct smb_charger *chg, + bool rising) +{ + smblib_dbg(chg, PR_INTERRUPT, "IRQ: sdp-enumeration-done %s\n", + rising ? "rising" : "falling"); +} + +#ifdef CONFIG_MACH_XIAOMI_NABU +static bool qc3p5_vbus_timeout_check(struct smb_charger *chg, + int timeout_ms, int vbus_lo_bound, + int vbus_hi_bound, int *vbus_uv) +{ + union power_supply_propval pval; + ktime_t start_kt, delta_kt; + int rc = 0; + + rc = power_supply_get_property(chg->usb_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get VBUS voltage rc=%d\n", rc); + return false; + } + + start_kt = ktime_get_boottime(); + delta_kt = ktime_sub(ktime_get_boottime(), start_kt); + while (((pval.intval <= vbus_lo_bound) || (pval.intval >= vbus_hi_bound)) + && (ktime_to_ms(delta_kt) < timeout_ms)) { + rc = power_supply_get_property(chg->usb_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get VBUS voltage rc=%d\n", rc); + return false; + } + delta_kt = ktime_sub(ktime_get_boottime(), start_kt); + } + + if ((pval.intval <= vbus_lo_bound) + || (pval.intval >= vbus_hi_bound) + || (ktime_to_ms(delta_kt) > timeout_ms)) { + smblib_err(chg, "QC3.5: VBUS failed to settle\n"); + return false; + } + + *vbus_uv = (int)pval.intval; + smblib_err(chg, "QC3.5: VBUS successfully settled\n"); + + return true; +} + +#define QC3P5_T_TA_DETECTION_TIMEOUT_PMIC_MS 200 +#define QC3P5_T_TA_CAP_TIMEOUT_PMIC_MS 250 +#define VBUS_5P5_V_UV 5500000 +#define VBUS_6P4_V_UV 6400000 +#define VBUS_6P65_V_UV 6650000 +#define VBUS_7P35_V_UV 7350000 +#define VBUS_7P6_V_UV 7600000 +#define VBUS_8P4_V_UV 8400000 +/*Use 8.55V and 9.8V to account for +10% and -5% spec on 9V for QC2/3 */ +#define VBUS_8P55_V_UV 8550000 +#define VBUS_9P8_V_UV 9800000 + +static int qc3p5_authenticate(struct smb_charger *chg) +{ + int i, vbus_uv, rc = 0; + + chg->qc3p5_authenticated = false; + chg->qc3p5_authentication_started = true; + chg->qc3p5_power_limit_w = 18;//Default to lowest power limit of 18W + + /* Set ICL to 500mA during QC3.5 Authentication */ + vote(chg->usb_icl_votable, QC3P5_VOTER, true, USBIN_500MA); + + /* + * * Fall back to QC3.0 Mode if VBUS doesn't settle between + * * 5.5V and 6.4V in 200ms + * */ + if (!qc3p5_vbus_timeout_check(chg, QC3P5_T_TA_DETECTION_TIMEOUT_PMIC_MS, + VBUS_5P5_V_UV, VBUS_6P4_V_UV, &vbus_uv)) { + smblib_err(chg, "VBUS doesn't reach 6V vbus=%d\n", vbus_uv); + return -ENODEV; + } + + smblib_err(chg, "QC3P5 AUTH: After QC3.0 Auth VBUS = %d\n", vbus_uv); + + /* Issue +-+-+- to request SRC CAP */ + for (i = 0; i < 3; i++) { + rc = smblib_dp_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't issue D+ pulse rc=%d\n", rc); + return rc; + } + usleep_range(5000, 5010); + + rc = smblib_dm_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't issue D- pulse rc=%d\n", rc); + return rc; + } + usleep_range(5000, 5010); + } + + /* Return to QC3.0 Mode if VBUS doesn't reach 7V in 200ms 50ms buffer */ + if (!qc3p5_vbus_timeout_check(chg, QC3P5_T_TA_CAP_TIMEOUT_PMIC_MS, + VBUS_6P65_V_UV, VBUS_9P8_V_UV, &vbus_uv)) { + smblib_err(chg, "VBUS doesn't reach 7V vbus=%d\n", vbus_uv); + return -ENODEV; + } + smblib_err(chg, "QC3P5 AUTH: SRC_CAP receieved\n"); + + /* Issue ++-- to confirm transition to QC3.5 */ + rc = smblib_dp_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't issue D+ pulse rc=%d\n", rc); + return rc; + } + usleep_range(5000, 5010); + + rc = smblib_dp_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't issue D+ pulse rc=%d\n", rc); + return rc; + } + usleep_range(5000, 5010); + + rc = smblib_dm_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't issue D- pulse rc=%d\n", rc); + return rc; + } + usleep_range(5000, 5010); + + rc = smblib_dm_pulse(chg); + if (rc < 0) { + smblib_err(chg, "Couldn't issue D- pulse rc=%d\n", rc); + return rc; + } + + /* SRC CAP 7V for 18W */ + if ((vbus_uv >= VBUS_6P65_V_UV) && (vbus_uv <= VBUS_7P35_V_UV)) { + chg->qc3p5_power_limit_w = 18; + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, QC3P5_CHARGER_ICL); + /* SRC CAP 8V for 27W */ + } else if ((vbus_uv >= VBUS_7P6_V_UV) && (vbus_uv <= VBUS_8P4_V_UV)) { + chg->qc3p5_power_limit_w = 27; + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, QC3P5_CHARGER_ICL); + /* SRC CAP 9V for 40W */ + } else if ((vbus_uv >= VBUS_8P55_V_UV) && (vbus_uv <= VBUS_9P8_V_UV)) { + chg->qc3p5_power_limit_w = 40; + // QC3.5 40W adapter's icl limited to 4A + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, HVDCP3P5_40W_CURRENT_UA); + } else { + smblib_err(chg, "not supported SRC CAP, vbus=%d\n", vbus_uv); + return -ENODEV; + } + + chg->qc3p5_authenticated = true; + vote(chg->fcc_votable, FCC_MAX_QC3P5_VOTER, true, HVDCP3P5_40W_CURRENT_UA); + + if (chg->support_ffc && !smblib_get_fastcharge_mode(chg)) + smblib_set_fastcharge_mode(chg, true); + + smblib_err(chg, "QC3P5 AUTH: QC3.5 Authenticated\n"); + smblib_err(chg, "QC3P5 AUTH: Power Limit = %d\n", + chg->qc3p5_power_limit_w); + + return rc; +} +#endif + +#define APSD_EXTENDED_TIMEOUT_MS 400 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int smblib_hvdcp3_raise_fsw(struct smb_charger *chg, int pulse_count) +{ + if (pulse_count < QC3_PULSES_FOR_6V) + smblib_set_opt_switcher_freq(chg, + chg->chg_freq.freq_5V); + else if (pulse_count < QC3_PULSES_FOR_9V) + smblib_set_opt_switcher_freq(chg, + chg->chg_freq.freq_6V_8V); + else if (pulse_count < QC3_PULSES_FOR_12V) + smblib_set_opt_switcher_freq(chg, + chg->chg_freq.freq_9V); + else + smblib_set_opt_switcher_freq(chg, + chg->chg_freq.freq_12V); + return 0; +} +#endif + +static void smblib_raise_qc3_vbus_work(struct work_struct *work) +{ + union power_supply_propval val = {0, }; + int i, usb_present = 0, vbus_now = 0; + int vol_qc_ab_thr = 0; + int rc; + struct smb_charger *chg = container_of(work, struct smb_charger, + raise_qc3_vbus_work.work); + + rc = smblib_get_prop_usb_present(chg, &val); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return; + } + + usb_present = val.intval; + if (usb_present) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->pd_hard_reset) { + if (chg->detect_low_power_qc3_charger) + chg->detect_low_power_qc3_charger = false; + if (chg->use_bq_pump) + vote(chg->usb_icl_votable, HVDCP3_START_ICL_VOTER, false, 0); + pr_info("pd hard reset, no need to raise vbus now\n"); + return; + } +#endif + + chg->raise_vbus_to_detect = true; + for (i = 0; i < MAX_PULSE; i++) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + smblib_hvdcp3_raise_fsw(chg, i); +#endif + rc = smblib_dp_pulse(chg); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + msleep(40); +#else + msleep(30); +#endif + } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + msleep(200); +#else + msleep(100); +#endif + rc = smblib_get_prop_usb_present(chg, &val); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return; + } - if (vbus_rising) { - cancel_delayed_work_sync(&chg->pr_swap_detach_work); - vote(chg->awake_votable, DETACH_DETECT_VOTER, false, 0); - rc = smblib_request_dpdm(chg, true); + usb_present = val.intval; + pr_info("usb_present is %d\n", usb_present); + if (!usb_present) { + chg->raise_vbus_to_detect = false; + rc = smblib_force_vbus_voltage(chg, FORCE_5V_BIT); + if (rc < 0) + pr_err("Failed to force 5V\n"); + return; + } + + rc = smblib_get_usb_in_voltage_now(chg, &val); if (rc < 0) - smblib_err(chg, "Couldn't to enable DPDM rc=%d\n", rc); + pr_err("Couldn't get usb voltage rc=%d\n", rc); + vbus_now = val.intval; + pr_info("vbus_now is %d\n", vbus_now); - /* Enable SW Thermal regulation */ - rc = smblib_set_sw_thermal_regulation(chg, true); + if (chg->snk_debug_acc_detected && usb_present) + vol_qc_ab_thr = VOL_THR_FOR_QC_CLASS_AB + + COMP_FOR_LOW_RESISTANCE_CABLE; + else + vol_qc_ab_thr = VOL_THR_FOR_QC_CLASS_AB; + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (vbus_now <= vol_qc_ab_thr + || chg->batt_profile_fcc_ua <= QC_CLASS_A_CURRENT_UA) { +#else + if (vbus_now <= vol_qc_ab_thr) { +#endif + pr_info("qc_class_a charger is detected, batt_profile_fcc=%d\n", chg->batt_profile_fcc_ua); + chg->is_qc_class_a = true; + vote(chg->fcc_votable, + CLASSA_QC_FCC_VOTER, true, QC_CLASS_A_CURRENT_UA); + } else { + pr_info("qc_class_b charger is detected\n"); + chg->is_qc_class_b = true; + if (chg->usb_psy) + power_supply_changed(chg->usb_psy); + } + rc = smblib_force_vbus_voltage(chg, FORCE_5V_BIT); if (rc < 0) - smblib_err(chg, "Couldn't start SW thermal regulation WA, rc=%d\n", - rc); + pr_err("Failed to force 5V\n"); - /* Remove FCC_STEPPER 1.5A init vote to allow FCC ramp up */ - if (chg->fcc_stepper_enable) - vote(chg->fcc_votable, FCC_STEPPER_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + msleep(100); - /* Schedule work to enable parallel charger */ - vote(chg->awake_votable, PL_DELAY_VOTER, true, 0); - schedule_delayed_work(&chg->pl_enable_work, - msecs_to_jiffies(PL_DELAY_MS)); - } else { - /* Disable SW Thermal Regulation */ - rc = smblib_set_sw_thermal_regulation(chg, false); - if (rc < 0) - smblib_err(chg, "Couldn't stop SW thermal regulation WA, rc=%d\n", - rc); + rc = smblib_dp_pulse(chg); +#endif - if (chg->wa_flags & BOOST_BACK_WA) { - data = chg->irq_info[SWITCHER_POWER_OK_IRQ].irq_data; - if (data) { - wdata = &data->storm_data; - update_storm_count(wdata, - WEAK_CHG_STORM_COUNT); - vote(chg->usb_icl_votable, BOOST_BACK_VOTER, - false, 0); - vote(chg->usb_icl_votable, WEAK_CHARGER_VOTER, - false, 0); + if (chg->is_qc_class_a) { + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP_CLASS_A_MAX_UA); + } else { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP_CLASS_B_CURRENT_UA); + if (chg->support_ffc) { + if (!smblib_get_fastcharge_mode(chg)) + smblib_set_fastcharge_mode(chg, true); } +#else + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP_CURRENT_UA); +#endif } - /* Force 1500mA FCC on removal if fcc stepper is enabled */ - if (chg->fcc_stepper_enable) - vote(chg->fcc_votable, FCC_STEPPER_VOTER, - true, 1500000); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) + vote(chg->usb_icl_votable, HVDCP3_START_ICL_VOTER, false, 0); - if (chg->wa_flags & WEAK_ADAPTER_WA) { - chg->aicl_5v_threshold_mv = - chg->default_aicl_5v_threshold_mv; - chg->aicl_cont_threshold_mv = - chg->default_aicl_cont_threshold_mv; + if (!chg->use_bq_pump) { +#endif + /* select charge pump as second charger */ + rc = smblib_select_sec_charger(chg, POWER_SUPPLY_CHARGER_SEC_CP, + POWER_SUPPLY_CP_HVDCP3, false); + if (rc < 0) + dev_err(chg->dev, + "Couldn't enable secondary chargers rc=%d\n", rc); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + } +#endif + +#ifdef CONFIG_THERMAL + if (chg->cp_reason == POWER_SUPPLY_CP_HVDCP3) + smblib_therm_charging(chg); +#endif + chg->raise_vbus_to_detect = false; + } +} + +struct quick_charge adapter_cap[] = { + { POWER_SUPPLY_TYPE_USB, QUICK_CHARGE_NORMAL }, + { POWER_SUPPLY_TYPE_USB_DCP, QUICK_CHARGE_NORMAL }, + { POWER_SUPPLY_TYPE_USB_CDP, QUICK_CHARGE_NORMAL }, + { POWER_SUPPLY_TYPE_USB_ACA, QUICK_CHARGE_NORMAL }, + { POWER_SUPPLY_TYPE_USB_FLOAT, QUICK_CHARGE_NORMAL }, + { POWER_SUPPLY_TYPE_USB_PD, QUICK_CHARGE_FAST }, + { POWER_SUPPLY_TYPE_USB_HVDCP, QUICK_CHARGE_FAST }, + { POWER_SUPPLY_TYPE_USB_HVDCP_3, QUICK_CHARGE_FAST }, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + { POWER_SUPPLY_TYPE_USB_HVDCP_3P5, QUICK_CHARGE_FLASH }, +#endif + { POWER_SUPPLY_TYPE_WIRELESS, QUICK_CHARGE_FAST }, + {0, 0}, +}; - smblib_set_charge_param(chg, - &chg->param.aicl_5v_threshold, - chg->aicl_5v_threshold_mv); - smblib_set_charge_param(chg, - &chg->param.aicl_cont_threshold, - chg->aicl_cont_threshold_mv); - chg->aicl_max_reached = false; +int smblib_get_quick_charge_type(struct smb_charger *chg) +{ + int i = 0, rc; + union power_supply_propval pval = {0, }; - if (chg->chg_param.smb_version == PMI632_SUBTYPE) - schgm_flash_torch_priority(chg, - TORCH_BUCK_MODE); + if (!chg) { + dev_err(chg->dev, "get quick charge type faied\n"); + return -EINVAL; + } - data = chg->irq_info[USBIN_UV_IRQ].irq_data; - if (data) { - wdata = &data->storm_data; - reset_storm_count(wdata); - } - vote(chg->usb_icl_votable, AICL_THRESHOLD_VOTER, - false, 0); - } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + rc = smblib_get_prop_batt_health(chg, &pval); + if (rc < 0) + smblib_err(chg, "Couldn't get batt health rc=%d\n", rc); - rc = smblib_request_dpdm(chg, false); - if (rc < 0) - smblib_err(chg, "Couldn't disable DPDM rc=%d\n", rc); + if ((pval.intval == POWER_SUPPLY_HEALTH_COLD) + || (pval.intval == POWER_SUPPLY_HEALTH_OVERHEAT)) + return 0; - smblib_update_usb_type(chg); + /* davinic do not need to report this type */ + if ((chg->real_charger_type == POWER_SUPPLY_TYPE_USB_PD) + && chg->pd_verifed && chg->qc_class_ab) { + return QUICK_CHARGE_TURBE; } - if (chg->connector_type == POWER_SUPPLY_CONNECTOR_MICRO_USB) - smblib_micro_usb_plugin(chg, vbus_rising); - - vote(chg->temp_change_irq_disable_votable, DEFAULT_VOTER, - !vbus_rising, 0); + if (chg->is_qc_class_b || chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5) + return QUICK_CHARGE_FLASH; - power_supply_changed(chg->usb_psy); - if (chg->dual_role) - dual_role_instance_changed(chg->dual_role); - smblib_dbg(chg, PR_INTERRUPT, "IRQ: usbin-plugin %s\n", - vbus_rising ? "attached" : "detached"); -} + if ((chg->real_charger_type == POWER_SUPPLY_TYPE_USB_DCP) && chg->hvdcp_recheck_status) + return QUICK_CHARGE_FAST; +#else + rc = smblib_get_prop_batt_status(chg, &pval); + if (rc < 0) + return -EINVAL; -irqreturn_t usb_plugin_irq_handler(int irq, void *data) -{ - struct smb_irq_data *irq_data = data; - struct smb_charger *chg = irq_data->parent_data; + if (pval.intval == POWER_SUPPLY_STATUS_DISCHARGING) + return 0; - if (chg->pd_hard_reset) - smblib_usb_plugin_hard_reset_locked(chg); - else - smblib_usb_plugin_locked(chg); + if ((chg->real_charger_type == POWER_SUPPLY_TYPE_USB_PD) && chg->pd_verifed) { + return QUICK_CHARGE_FLASH; + } - return IRQ_HANDLED; -} + if (chg->is_qc_class_b) + return QUICK_CHARGE_FLASH; +#endif -static void smblib_handle_slow_plugin_timeout(struct smb_charger *chg, - bool rising) -{ - smblib_dbg(chg, PR_INTERRUPT, "IRQ: slow-plugin-timeout %s\n", - rising ? "rising" : "falling"); -} + while (adapter_cap[i].adap_type != 0) { + if (chg->real_charger_type == adapter_cap[i].adap_type) { + return adapter_cap[i].adap_cap; + } + i++; + } -static void smblib_handle_sdp_enumeration_done(struct smb_charger *chg, - bool rising) -{ - smblib_dbg(chg, PR_INTERRUPT, "IRQ: sdp-enumeration-done %s\n", - rising ? "rising" : "falling"); + return 0; } +#endif -#define APSD_EXTENDED_TIMEOUT_MS 400 /* triggers when HVDCP 3.0 authentication has finished */ static void smblib_handle_hvdcp_3p0_auth_done(struct smb_charger *chg, bool rising) @@ -5400,12 +8310,98 @@ static void smblib_handle_hvdcp_3p0_auth_done(struct smb_charger *chg, if (!rising) return; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (chg->qc3p5_supported) { + /* Run QC3P5 Authentication */ + if (!chg->qc3p5_authentication_started) { + rc = qc3p5_authenticate(chg); + if (rc < 0) { + chg->qc3p5_authenticated = false; + dev_err(chg->dev, "QC3.5 Authentication Failed, rc=%d\n", rc); + } + chg->qc3p5_auth_complete = true; + /* Release 500mA QC3.5 Authentication vote */ + vote(chg->usb_icl_votable, QC3P5_VOTER, false, 0); + } + smblib_update_usb_type(chg); + } +#endif + if (chg->mode == PARALLEL_MASTER) vote(chg->pl_enable_votable_indirect, USBIN_V_VOTER, true, 0); /* the APSD done handler will set the USB supply type */ apsd_result = smblib_get_apsd_result(chg); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* for QC3, switch to CP if present */ + if ((apsd_result->bit & QC_3P0_BIT) + && (chg->sec_cp_present || chg->use_bq_pump)) { + if (!chg->qc_class_ab) { + rc = smblib_select_sec_charger(chg, POWER_SUPPLY_CHARGER_SEC_CP, + POWER_SUPPLY_CP_HVDCP3, false); + if (rc < 0) + dev_err(chg->dev, + "Couldn't enable secondary chargers rc=%d\n", rc); + } else { + if (!chg->detect_low_power_qc3_charger && + (!chg->qc3p5_supported || !chg->qc3p5_authenticated)) { + if (!chg->use_bq_pump) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP_START_CURRENT_UA); + else { + vote(chg->usb_icl_votable, HVDCP3_START_ICL_VOTER, true, + HVDCP_START_CURRENT_UA_FOR_BQ); + } + schedule_delayed_work(&chg->raise_qc3_vbus_work, 0); + chg->detect_low_power_qc3_charger = true; + } + } + /* start six pin battery step charge monitor work */ + if (chg->six_pin_step_charge_enable) { + if (!chg->already_start_step_charge_work) { + schedule_delayed_work(&chg->six_pin_batt_step_chg_work, + msecs_to_jiffies(STEP_CHG_DELAYED_START_MS)); + chg->already_start_step_charge_work = true; + } + } + } else if ((apsd_result->bit & QC_2P0_BIT) + && (!chg->qc2_unsupported)) { + pr_info("force 9V for QC2 charger\n"); + rc = smblib_force_vbus_voltage(chg, FORCE_9V_BIT); + if (rc < 0) + pr_err("Failed to force 9V\n"); + + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP2_CURRENT_UA); + } +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + /* for QC3, switch to CP if present */ + if ((apsd_result->bit & QC_3P0_BIT) && chg->sec_cp_present) { + if (!chg->qc_class_ab) { + rc = smblib_select_sec_charger(chg, POWER_SUPPLY_CHARGER_SEC_CP, + POWER_SUPPLY_CP_HVDCP3, false); + if (rc < 0) + dev_err(chg->dev, + "Couldn't enable secondary chargers rc=%d\n", rc); + } else { + if (!chg->detect_low_power_qc3_charger) { + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP_START_CURRENT_UA); + schedule_delayed_work(&chg->raise_qc3_vbus_work, 0); + chg->detect_low_power_qc3_charger = true; + } + } + } else if (apsd_result->bit & QC_2P0_BIT + && !chg->qc2_unsupported) { + pr_info("force 9V for QC2 charger\n"); + rc = smblib_force_vbus_voltage(chg, FORCE_9V_BIT); + if (rc < 0) + pr_err("Failed to force 9V\n"); + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, + HVDCP2_CURRENT_UA); + } +#else if (apsd_result->bit & QC_3P0_BIT) { /* for QC3, switch to CP if present */ if (chg->sec_cp_present) { @@ -5430,6 +8426,7 @@ static void smblib_handle_hvdcp_3p0_auth_done(struct smb_charger *chg, + jiffies); } } +#endif smblib_dbg(chg, PR_INTERRUPT, "IRQ: hvdcp-3p0-auth-done rising; %s detected\n", apsd_result->name); @@ -5446,8 +8443,40 @@ static void smblib_handle_hvdcp_check_timeout(struct smb_charger *chg, CHARGER_TYPE_VOTER, false, 0); vote(chg->hdc_irq_disable_votable, CHARGER_TYPE_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!chg->raise_vbus_to_detect + && chg->real_charger_type != POWER_SUPPLY_TYPE_USB_HVDCP_3P5) { + if (chg->is_qc_class_a) { + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, // git + HVDCP_CLASS_A_MAX_UA); + } else if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP) { + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, // git + HVDCP2_CURRENT_UA); + } else { + if (chg->six_pin_step_charge_enable || chg->use_bq_pump) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, // git + HVDCP_CLASS_B_CURRENT_UA); + else + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, // git + HVDCP_CLASS_A_FOR_CP_UA); + } + } +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + if (!chg->raise_vbus_to_detect) { + if (chg->is_qc_class_a) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, // git + HVDCP_CLASS_A_MAX_UA); + else if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, // git + HVDCP2_CURRENT_UA); + else + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, // git + HVDCP_CURRENT_UA); + } +#else vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, HVDCP_CURRENT_UA); +#endif } else { /* A plain DCP, enforce DCP ICL if specified */ vote(chg->usb_icl_votable, DCP_VOTER, @@ -5469,8 +8498,12 @@ static void smblib_handle_hvdcp_detect_done(struct smb_charger *chg, static void update_sw_icl_max(struct smb_charger *chg, int pst) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + union power_supply_propval val = {0, }; +#else int typec_mode; int rp_ua; +#endif /* while PD is active it should have complete ICL control */ if (chg->pd_active) @@ -5485,9 +8518,13 @@ static void update_sw_icl_max(struct smb_charger *chg, int pst) * HVDCP 2/3, handled separately */ if (pst == POWER_SUPPLY_TYPE_USB_HVDCP +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + || pst == POWER_SUPPLY_TYPE_USB_HVDCP_3P5 +#endif || pst == POWER_SUPPLY_TYPE_USB_HVDCP_3) return; +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) /* TypeC rp med or high, use rp value */ typec_mode = smblib_get_prop_typec_mode(chg); if (typec_rp_med_high(chg, typec_mode)) { @@ -5495,10 +8532,14 @@ static void update_sw_icl_max(struct smb_charger *chg, int pst) vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, rp_ua); return; } +#endif /* rp-std or legacy, USB BC 1.2 */ switch (pst) { case POWER_SUPPLY_TYPE_USB: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + smblib_get_prop_usb_present(chg, &val); +#endif /* * USB_PSY will vote to increase the current to 500/900mA once * enumeration is done. @@ -5517,21 +8558,56 @@ static void update_sw_icl_max(struct smb_charger *chg, int pst) DCP_CURRENT_UA); else /* if flash is active force 500mA */ +#if !defined(CONFIG_MACH_XIAOMI_SM8150) || defined(CONFIG_MACH_XIAOMI_VAYU) vote(chg->usb_icl_votable, USB_PSY_VOTER, true, is_flash_active(chg) ? SDP_CURRENT_UA : SDP_100_MA); +#elif defined(CONFIG_MACH_XIAOMI_NABU) + vote(chg->usb_icl_votable, USB_PSY_VOTER, true, SDP_CURRENT_UA); +#else + vote(chg->usb_icl_votable, USB_PSY_VOTER, true, + is_flash_active(chg) ? + SDP_CURRENT_UA : USBIN_500MA); +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, false, 0); +#endif } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + else if ((chg->typec_mode == POWER_SUPPLY_TYPEC_NONE) && (val.intval == true)) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, SDP_CURRENT_UA); + else +#endif vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, false, 0); break; case POWER_SUPPLY_TYPE_USB_CDP: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (is_client_vote_enabled(chg->usb_icl_votable, + USB_PSY_VOTER)) + vote(chg->usb_icl_votable, USB_PSY_VOTER, false, 0); +#endif vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, CDP_CURRENT_UA); break; case POWER_SUPPLY_TYPE_USB_DCP: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, DCP_CURRENT_UA); +#else +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (is_client_vote_enabled(chg->usb_icl_votable, + USB_PSY_VOTER)) + vote(chg->usb_icl_votable, USB_PSY_VOTER, false, 0); +#endif rp_ua = get_rp_based_dcp_current(chg, typec_mode); vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, rp_ua); +#endif break; case POWER_SUPPLY_TYPE_USB_FLOAT: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (is_client_vote_enabled(chg->usb_icl_votable, + USB_PSY_VOTER)) + vote(chg->usb_icl_votable, USB_PSY_VOTER, false, 0); +#endif /* * If DC_IN or uUSB is detected then vote * for DCP current. @@ -5547,8 +8623,16 @@ static void update_sw_icl_max(struct smb_charger *chg, int pst) * enumerate to check if this is a SDP and * appropriately set the current. */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!chg->recheck_charger) +#endif vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, SDP_100_MA); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + else + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, + true, FLOAT_CHARGER_UA); +#endif break; case POWER_SUPPLY_TYPE_UNKNOWN: default: @@ -5558,6 +8642,20 @@ static void update_sw_icl_max(struct smb_charger *chg, int pst) } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static void determine_thermal_current(struct smb_charger *chg) +{ + if (chg->system_temp_level > 0 + && chg->system_temp_level < (chg->thermal_levels - 1)) { + /* + * consider thermal limit only when it is active and not at + * the highest level + */ + smblib_therm_charging(chg); + } +} +#endif + static void smblib_handle_apsd_done(struct smb_charger *chg, bool rising) { const struct apsd_result *apsd_result; @@ -5581,14 +8679,35 @@ static void smblib_handle_apsd_done(struct smb_charger *chg, bool rising) smblib_notify_device_mode(chg, true); } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* if floated charger is detected, and audio accessory set icl to 500 */ + if (chg->typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, 500000); +#endif break; case OCP_CHARGER_BIT: case DCP_CHARGER_BIT: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER){ + chg->real_charger_type = POWER_SUPPLY_TYPE_USB_FLOAT; + chg->usb_psy_desc.type = POWER_SUPPLY_TYPE_USB_FLOAT; + if ((strcmp(get_effective_client(chg->usb_icl_votable), "OTG_VOTER") == 0) && + (get_effective_result(chg->usb_icl_votable) == 0)) + vote(chg->usb_icl_votable, OTG_VOTER, false, 0); + + if (get_client_vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER) != 500000) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, 500000); + } +#endif break; default: break; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + determine_thermal_current(chg); +#endif + smblib_dbg(chg, PR_INTERRUPT, "IRQ: apsd-done rising; %s detected\n", apsd_result->name); } @@ -5599,6 +8718,10 @@ irqreturn_t usb_source_change_irq_handler(int irq, void *data) struct smb_charger *chg = irq_data->parent_data; int rc = 0; u8 stat; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->fake_usb_insertion) + return IRQ_HANDLED; +#endif /* PD session is ongoing, ignore BC1.2 and QC detection */ if (chg->pd_active) @@ -5690,6 +8813,12 @@ enum alarmtimer_restart smblib_lpd_recheck_timer(struct alarm *alarm, chg->lpd_stage = LPD_STAGE_NONE; chg->lpd_reason = LPD_NONE; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->support_liquid == true) { + schedule_work(&chg->lpd_disable_chg_work); + } +#endif + return ALARMTIMER_NORESTART; } @@ -5723,6 +8852,15 @@ static bool smblib_src_lpd(struct smb_charger *chg) break; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->typec_mode = smblib_get_prop_typec_mode(chg); + if ((chg->typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER) + && (chg->support_liquid == true)) { + lpd_flag = false; + return lpd_flag; + } +#endif + if (lpd_flag) { chg->lpd_stage = LPD_STAGE_COMMIT; pval.intval = POWER_SUPPLY_TYPEC_PR_SINK; @@ -5731,6 +8869,19 @@ static bool smblib_src_lpd(struct smb_charger *chg) smblib_err(chg, "Couldn't write 0x%02x to TYPE_C_INTRPT_ENB_SOFTWARE_CTRL rc=%d\n", pval.intval, rc); chg->lpd_reason = LPD_MOISTURE_DETECTED; + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->lpd_status = true; + + if (chg->support_liquid == true) { + vote(chg->usb_icl_votable, LIQUID_DETECTION_VOTER, true, 0); + if (chg->batt_psy) + power_supply_changed(chg->batt_psy); + } + alarm_start_relative(&chg->lpd_recheck_timer, + ms_to_ktime(15000)); +#endif + chg->moisture_present = true; alarm_start_relative(&chg->lpd_recheck_timer, ms_to_ktime(60000)); @@ -5757,7 +8908,36 @@ static void typec_src_fault_condition_cfg(struct smb_charger *chg, bool src) static void typec_sink_insertion(struct smb_charger *chg) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int rc = 0; + int usb_present = 0; + int typec_mode; + union power_supply_propval pval = {0, }; +#else int rc; +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = smblib_get_prop_usb_present(chg, &pval); + if (rc < 0) { + smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); + return; + } + + usb_present = pval.intval; + + typec_mode = smblib_get_prop_typec_mode(chg); + if (usb_present && typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER) { + chg->real_charger_type = POWER_SUPPLY_TYPE_USB_FLOAT; + chg->usb_psy_desc.type = POWER_SUPPLY_TYPE_USB_FLOAT; + if (get_client_vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER) != 500000) + vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, 500000); + vote(chg->usb_icl_votable, OTG_VOTER, false, 0); + power_supply_changed(chg->batt_psy); + } else { + vote(chg->usb_icl_votable, OTG_VOTER, true, 0); + } +#endif typec_src_fault_condition_cfg(chg, true); rc = smblib_set_charge_param(chg, &chg->param.freq_switcher, @@ -5813,6 +8993,9 @@ static void typec_sink_removal(struct smb_charger *chg) { int rc; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + vote(chg->usb_icl_votable, OTG_VOTER, false, 0); +#endif typec_src_fault_condition_cfg(chg, false); rc = smblib_set_charge_param(chg, &chg->param.freq_switcher, chg->chg_freq.freq_removal); @@ -5842,7 +9025,20 @@ static void typec_src_removal(struct smb_charger *chg) dev_err(chg->dev, "Couldn't disable secondary charger rc=%d\n", rc); +#ifdef CONFIG_MACH_XIAOMI_NABU + /* Reset QC3.5 Flag and power limit*/ + chg->qc3p5_authenticated = false; + chg->qc3p5_auth_complete = false; + chg->qc3p5_authentication_started = false; + chg->qc3p5_dp_tune_rapidly = false; + chg->qc3p5_power_limit_w = 18; +#endif + chg->qc3p5_detected = false; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->snk_debug_acc_detected = false; +#endif + typec_src_fault_condition_cfg(chg, false); smblib_hvdcp_detect_enable(chg, false); smblib_update_usb_type(chg); @@ -5859,6 +9055,15 @@ static void typec_src_removal(struct smb_charger *chg) } cancel_delayed_work_sync(&chg->pl_enable_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cancel_delayed_work_sync(&chg->raise_qc3_vbus_work); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + cancel_delayed_work_sync(&chg->check_init_boot); +#endif +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + cancel_delayed_work_sync(&chg->check_vbat_work); +#endif /* reset input current limit voters */ vote(chg->usb_icl_votable, SW_ICL_MAX_VOTER, true, @@ -5867,10 +9072,16 @@ static void typec_src_removal(struct smb_charger *chg) vote(chg->usb_icl_votable, USB_PSY_VOTER, false, 0); vote(chg->usb_icl_votable, DCP_VOTER, false, 0); vote(chg->usb_icl_votable, SW_QC3_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + vote(chg->usb_icl_votable, OTG_VOTER, false, 0); +#endif vote(chg->usb_icl_votable, CTM_VOTER, false, 0); vote(chg->usb_icl_votable, HVDCP2_ICL_VOTER, false, 0); vote(chg->usb_icl_votable, CHG_TERMINATION_VOTER, false, 0); vote(chg->usb_icl_votable, THERMAL_THROTTLE_VOTER, false, 0); +#ifdef CONFIG_MACH_XIAOMI_NABU + vote(chg->usb_icl_votable, QC3P5_VOTER, false, 0); +#endif /* reset usb irq voters */ vote(chg->limited_irq_disable_votable, CHARGER_TYPE_VOTER, @@ -5884,6 +9095,28 @@ static void typec_src_removal(struct smb_charger *chg) vote(chg->pl_enable_votable_indirect, USBIN_I_VOTER, false, 0); vote(chg->pl_enable_votable_indirect, USBIN_V_VOTER, false, 0); vote(chg->awake_votable, PL_DELAY_VOTER, false, 0); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* reset our own voters */ + /* clear chg_awake wakeup source when typec removal */ + vote(chg->awake_votable, CHG_AWAKE_VOTER, false, 0); + vote(chg->fcc_votable, CLASSA_QC_FCC_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + vote(chg->fcc_votable, PD_REMOVE_COMP_VOTER, false, 0); + vote(chg->fcc_votable, PD_VERIFED_VOTER, true, PD_UNVERIFED_CURRENT); +#endif + vote(chg->usb_icl_votable, QC_A_CP_ICL_MAX_VOTER, false, 0); + vote(chg->usb_icl_votable, QC2_UNSUPPORTED_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) { + vote(chg->usb_icl_votable, HVDCP3_START_ICL_VOTER, false, 0); + vote(chg->usb_icl_votable, MAIN_CHG_VOTER, false, 0); + vote(chg->fcc_votable, SLOWLY_CHARGING_VOTER, false, 0); + } +#endif +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + vote(chg->usb_icl_votable, PD_VERIFED_VOTER, false, 0); +#endif +#endif /* Remove SW thermal regulation WA votes */ vote(chg->usb_icl_votable, SW_THERM_REGULATION_VOTER, false, 0); @@ -5905,8 +9138,26 @@ static void typec_src_removal(struct smb_charger *chg) chg->usbin_forced_max_uv = 0; chg->chg_param.forced_main_fcc = 0; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->six_pin_step_charge_enable) { + chg->init_start_vbat_checked = false; + chg->already_start_step_charge_work = false; + chg->trigger_taper_count = 0; + chg->index_vfloat = 0; + vote(chg->fv_votable, SIX_PIN_VFLOAT_VOTER, false, 0); + vote(chg->fcc_votable, SIX_PIN_VFLOAT_VOTER, false, 0); + cancel_delayed_work_sync(&chg->six_pin_batt_step_chg_work); + } +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + vote(chg->fv_votable, BATT_BQ2597X_VOTER, false, 0); +#endif + /* Reset CC mode votes */ vote(chg->fcc_main_votable, MAIN_FCC_VOTER, false, 0); +#ifdef CONFIG_MACH_XIAOMI_NABU + vote(chg->fcc_votable, FCC_MAX_QC3P5_VOTER, false, 0); +#endif chg->adapter_cc_mode = 0; chg->thermal_overheat = 0; vote_override(chg->fcc_votable, CC_MODE_VOTER, false, 0); @@ -5920,6 +9171,13 @@ static void typec_src_removal(struct smb_charger *chg) if (rc < 0) smblib_err(chg, "Couldn't write float charger options rc=%d\n", rc); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->qc_class_ab) { + rc = smblib_force_vbus_voltage(chg, FORCE_5V_BIT); + if (rc < 0) + pr_err("Failed to force 5V\n"); + } +#endif if (!chg->pr_swap_in_progress) { rc = smblib_usb_pd_adapter_allowance_override(chg, FORCE_NULL); @@ -5958,10 +9216,51 @@ static void typec_src_removal(struct smb_charger *chg) if (chg->use_extcon) smblib_notify_device_mode(chg, false); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->support_ffc) { + if (smblib_get_fastcharge_mode(chg) == 1) + smblib_set_fastcharge_mode(chg, false); + /* if support ffc, default vfloat set back to 4.4V when typec removal */ + vote(chg->fv_votable, NON_FFC_VFLOAT_VOTER, + true, NON_FFC_VFLOAT_UV); + } + + /* when src removal, set bark timer back to default 16s */ + smblib_set_wdog_bark_timer(chg, BARK_TIMER_NORMAL); +#endif + chg->typec_legacy = false; del_timer_sync(&chg->apsd_timer); chg->apsd_ext_timeout = false; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->detect_low_power_qc3_charger = false; + chg->raise_vbus_to_detect = false; + chg->is_qc_class_a = false; + chg->is_qc_class_b = false; + chg->high_vbus_detected = false; + chg->qc2_unsupported = false; + chg->cc_un_compliant_detected = false; + chg->recheck_charger = false; + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->slowly_charging = false; + chg->pps_thermal_level = -EINVAL; +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + fv_over_limit_times = 0; +#endif + pr_err("%s:", __func__); + if (chg->pd_verifed) { + chg->pd_verifed = false; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->support_ffc) { + if (smblib_get_fastcharge_mode(chg) == true) + smblib_set_fastcharge_mode(chg, false); + } +#endif + } +#endif } static void typec_mode_unattached(struct smb_charger *chg) @@ -6144,6 +9443,11 @@ irqreturn_t typec_attach_detach_irq_handler(int irq, void *data) if (attached) { smblib_lpd_clear_ra_open_work(chg); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->lpd_status) + chg->lpd_status = false; +#endif + rc = smblib_read(chg, TYPE_C_MISC_STATUS_REG, &stat); if (rc < 0) { smblib_err(chg, "Couldn't read TYPE_C_MISC_STATUS_REG rc=%d\n", @@ -6163,6 +9467,9 @@ irqreturn_t typec_attach_detach_irq_handler(int irq, void *data) } else { chg->sink_src_mode = SINK_MODE; typec_src_insertion(chg); +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + smblib_wireless_set_enable(chg, false); +#endif } if (chg->typec_role_swap_failed) { @@ -6180,6 +9487,9 @@ irqreturn_t typec_attach_detach_irq_handler(int irq, void *data) case SINK_MODE: case AUDIO_ACCESS_MODE: typec_src_removal(chg); +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + smblib_wireless_set_enable(chg, true); +#endif break; case UNATTACHED_MODE: default: @@ -6205,24 +9515,90 @@ irqreturn_t typec_attach_detach_irq_handler(int irq, void *data) } } - if (chg->lpd_stage == LPD_STAGE_FLOAT_CANCEL) - schedule_delayed_work(&chg->lpd_detach_work, - msecs_to_jiffies(1000)); - } + if (chg->lpd_stage == LPD_STAGE_FLOAT_CANCEL) + schedule_delayed_work(&chg->lpd_detach_work, + msecs_to_jiffies(1000)); + } + + rc = smblib_masked_write(chg, USB_CMD_PULLDOWN_REG, + EN_PULLDOWN_USB_IN_BIT, + attached ? 0 : EN_PULLDOWN_USB_IN_BIT); + if (rc < 0) + smblib_err(chg, "Couldn't configure pulldown on USB_IN rc=%d\n", + rc); + + power_supply_changed(chg->usb_psy); + if (chg->dual_role) + dual_role_instance_changed(chg->dual_role); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_MACH_XIAOMI_NABU +/*add for wireless reverse charge to disable dc*/ +int smblib_set_sw_disable_dc_en(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc = 0; + + if (val->intval) { + /* step1: enter dc suspend */ + rc = vote(chg->dc_suspend_votable, SW_DISABLE_DC_VOTER, + true, 0); + + /* step2: force dcin_en low */ + rc = smblib_masked_write(chg, DCIN_CMD_IL_REG, + DCIN_EN_OVERRIDE_BIT | DCIN_EN_BIT, + DCIN_EN_OVERRIDE_BIT); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure dc_en override rc=%d\n", rc); + return rc; + } + + /* step3: enable pull-down on dcin_pon and mid_chg */ + rc = smblib_masked_write(chg, DCIN_CMD_PULLDOWN_REG, + DCIN_PULLDOWN_EN_BIT | DCIN_MID_PULLDOWN_BIT, + DCIN_PULLDOWN_EN_BIT | DCIN_MID_PULLDOWN_BIT); + if (rc < 0) { + dev_err(chg->dev, "Couldn't enable dcin_pulldown rc=%d\n", rc); + return rc; + } + /* wait 10ms to pull mid_chg lower than Vsys+Vrevi */ + msleep(10); + + /* step4: exit dc suspend */ + rc = vote(chg->dc_suspend_votable, SW_DISABLE_DC_VOTER, + false, 0); + } else { + /* step1: enter dc suspend */ + rc = vote(chg->dc_suspend_votable, SW_DISABLE_DC_VOTER, + true, 0); - rc = smblib_masked_write(chg, USB_CMD_PULLDOWN_REG, - EN_PULLDOWN_USB_IN_BIT, - attached ? 0 : EN_PULLDOWN_USB_IN_BIT); - if (rc < 0) - smblib_err(chg, "Couldn't configure pulldown on USB_IN rc=%d\n", - rc); + /* step2: force dcin_en low */ + rc = smblib_masked_write(chg, DCIN_CMD_IL_REG, + DCIN_EN_OVERRIDE_BIT, 0); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure dc_en override rc=%d\n", rc); + return rc; + } - power_supply_changed(chg->usb_psy); - if (chg->dual_role) - dual_role_instance_changed(chg->dual_role); + /* step3: enable pull-down on dcin_pon and mid_chg */ + rc = smblib_masked_write(chg, DCIN_CMD_PULLDOWN_REG, + DCIN_PULLDOWN_EN_BIT | DCIN_MID_PULLDOWN_BIT, 0); + if (rc < 0) { + dev_err(chg->dev, "Couldn't disable dcin_pulldown rc=%d\n", rc); + return rc; + } + /* wait 10ms to pull mid_chg lower than Vsys+Vrevi */ + msleep(10); + /* step4: exit dc suspend */ + rc = vote(chg->dc_suspend_votable, SW_DISABLE_DC_VOTER, + false, 0); + } - return IRQ_HANDLED; + return 0; } +#endif static void dcin_aicl(struct smb_charger *chg) { @@ -6369,14 +9745,160 @@ irqreturn_t dcin_uv_irq_handler(int irq, void *data) return IRQ_HANDLED; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int smblib_get_wireless_output_vol(struct smb_charger *chg) +{ + + int rc,wireless_vout = 0; + + rc = iio_read_channel_processed(chg->iio.vph_v_chan, + &wireless_vout); + if (rc < 0) { + smblib_err(chg, "Couldn't get vph vol rc = %d\n", + rc); + return -ENODATA; + } + wireless_vout *= 2; + wireless_vout /= 100000; + wireless_vout *= 100000; + + return wireless_vout; + +} + +int smblib_set_wirless_cp_enable(struct smb_charger *chg, + const union power_supply_propval *val) +{ + union power_supply_propval pval; + int wireless_vout = 0; + int rc; + + wireless_vout = smblib_get_wireless_output_vol(chg); + if (wireless_vout < 0) { + dev_err(chg->dev, "Couldn't get vph_pwr wireless_vout=%d\n", + wireless_vout); + return -ENODATA; + } + + if (chg->flag_dc_present && val->intval) { + pval.intval = wireless_vout; + rc = smblib_set_prop_voltage_wls_output(chg, &pval); + if (rc < 0) + dev_err(chg->dev, "Couldn't set dc voltage to 2*vph rc=%d\n", + rc); + + rc = smblib_select_sec_charger(chg, POWER_SUPPLY_CHARGER_SEC_CP, + POWER_SUPPLY_CP_WIRELESS, false); + if (rc < 0) + dev_err(chg->dev, + "Couldn't enable secondary chargers rc=%d\n", rc); + } else + smblib_dbg(chg, PR_WLS, "dcin_not present or usbin_present\n"); + + return 0; +} + +int smblib_set_wirless_power_good_enable(struct smb_charger *chg, + const union power_supply_propval *val) +{ + int rc = 0; + + chg->power_good_en = val->intval; + if (chg->power_good_en) { + chg->fake_dc_on = 1; + chg->fake_dc_flag = 0; + chg->last_batt_stat = 0; + cancel_delayed_work(&chg->dc_plug_out_delay_work); + vote(chg->awake_votable, DC_UV_AWAKE_VOTER, false, 0); + + } + else { + if (!chg->fake_dc_flag) + chg->fake_dc_on = 0; + /* step1: enter dc suspend */ + rc = vote(chg->dc_suspend_votable, OTG_VOTER, + true, 0); + + /* step2: force dcin_en low */ + rc = smblib_masked_write(chg, DCIN_CMD_IL_REG, + DCIN_EN_OVERRIDE_BIT | DCIN_EN_BIT, + DCIN_EN_OVERRIDE_BIT); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure dc_en override rc=%d\n", rc); + return rc; + } + + /* step3: enable pull-down on dcin_pon and mid_chg */ + rc = smblib_masked_write(chg, DCIN_CMD_PULLDOWN_REG, + DCIN_PULLDOWN_EN_BIT | DCIN_MID_PULLDOWN_BIT, + DCIN_PULLDOWN_EN_BIT | DCIN_MID_PULLDOWN_BIT); + if (rc < 0) { + dev_err(chg->dev, "Couldn't enable dcin_pulldown rc=%d\n", rc); + return rc; + } + /* wait 10ms to pull mid_chg lower than Vsys+Vrevi */ + msleep(10); + + /* step4: disable pull-down on dcin_pon and mid_chg */ + rc = smblib_masked_write(chg, DCIN_CMD_PULLDOWN_REG, + DCIN_PULLDOWN_EN_BIT | DCIN_MID_PULLDOWN_BIT, + 0); + if (rc < 0) { + dev_err(chg->dev, "Couldn't disable dcin_pulldown rc=%d\n", rc); + return rc; + } + + /* step5: remove dcin_en low */ + rc = smblib_masked_write(chg, DCIN_CMD_IL_REG, + DCIN_EN_OVERRIDE_BIT | DCIN_EN_BIT, + 0); + if (rc < 0) { + dev_err(chg->dev, "Couldn't configure dc_en override rc=%d\n", rc); + return rc; + } + + /* step6: exit dc suspend */ + rc = vote(chg->dc_suspend_votable, OTG_VOTER, + false, 0); + } + power_supply_changed(chg->dc_psy); + power_supply_changed(chg->batt_psy); + if (chg->wls_psy) + power_supply_changed(chg->wls_psy); + + return 0; +} + +static void smblib_dc_plug_out_work(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + dc_plug_out_delay_work.work); + + chg->fake_dc_on = 0; /*use for delay 1.8s*/ + chg->fake_dc_flag = 0; + chg->last_batt_stat = 0; + power_supply_changed(chg->dc_psy); + smblib_dbg(chg, PR_WLS, "Delay timeout and clear dc fake value\n"); + vote(chg->awake_votable, DC_UV_AWAKE_VOTER, false, 0); +} +#endif + irqreturn_t dc_plugin_irq_handler(int irq, void *data) { struct smb_irq_data *irq_data = data; struct smb_charger *chg = irq_data->parent_data; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + union power_supply_propval pval = {0, }; +#else union power_supply_propval pval; +#endif int input_present; bool dcin_present, vbus_present; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int rc; +#else int rc, wireless_vout = 0; +#endif int sec_charger; rc = smblib_get_prop_vph_voltage_now(chg, &pval); @@ -6384,15 +9906,33 @@ irqreturn_t dc_plugin_irq_handler(int irq, void *data) return IRQ_HANDLED; /* 2*VPH, with a granularity of 100mV */ +#ifndef CONFIG_MACH_XIAOMI_SM8150 wireless_vout = ((pval.intval * 2) / 100000) * 100000; +#endif rc = smblib_is_input_present(chg, &input_present); if (rc < 0) return IRQ_HANDLED; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->idtp_psy = power_supply_get_by_name("idt"); + if (!chg->idtp_psy) + dev_err(chg->dev, "Could not get idtp psy\n"); +#endif + dcin_present = input_present & INPUT_PRESENT_DC; vbus_present = input_present & INPUT_PRESENT_USB; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* when dcin present and in otg mode, set vbus present to 0*/ + if (smblib_get_prop_dfp_mode(chg) != POWER_SUPPLY_TYPEC_NONE + && smblib_get_prop_dfp_mode(chg) + != POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER + && dcin_present) + vbus_present = 0; +#endif + +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (dcin_present && !vbus_present) { cancel_work_sync(&chg->dcin_aicl_work); @@ -6448,9 +9988,123 @@ irqreturn_t dc_plugin_irq_handler(int irq, void *data) chg->last_wls_vout = 0; } +#elif defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (dcin_present) { + if (!vbus_present && chg->sec_cp_present) { + chg->flag_dc_present = 1; + vote(chg->awake_votable, DC_AWAKE_VOTER, true, 0); + if (chg->idtp_psy) { + pval.intval = true; + power_supply_set_property(chg->idtp_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + } + /* when dc_in plug in, enable batt_temp irq wakeup */ + if (chg->irq_info[BAT_TEMP_IRQ].irq && !chg->batt_temp_irq_enabled) { + enable_irq_wake(chg->irq_info[BAT_TEMP_IRQ].irq); + chg->batt_temp_irq_enabled = true; + } + } + + schedule_work(&chg->dcin_aicl_work); + } else { + /* when dc_in plug out, disable batt_temp irq wakeup */ + if (chg->irq_info[BAT_TEMP_IRQ].irq && chg->batt_temp_irq_enabled) { + disable_irq_wake(chg->irq_info[BAT_TEMP_IRQ].irq); + chg->batt_temp_irq_enabled = false; + } + /* when dc plug out, set bark timer back to default 16s */ + smblib_set_wdog_bark_timer(chg, BARK_TIMER_NORMAL); + vote(chg->awake_votable, DC_AWAKE_VOTER, false, 0); + vote(chg->dc_icl_votable, DCIN_ADAPTER_VOTER, true, 100000); + chg->flag_dc_present = 0; + chg->cp_reason = POWER_SUPPLY_CP_NONE; + sec_charger = chg->sec_pl_present ? + POWER_SUPPLY_CHARGER_SEC_PL : + POWER_SUPPLY_CHARGER_SEC_NONE; + rc = smblib_select_sec_charger(chg, sec_charger, + POWER_SUPPLY_CP_NONE, false); + + if (rc < 0) + dev_err(chg->dev, + "Couldn't disable secondary charger rc=%d\n", + rc); + + if (chg->idtp_psy) { + pval.intval = false; + power_supply_set_property(chg->idtp_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + } + + if (chg->cp_reason == POWER_SUPPLY_CP_WIRELESS) { + sec_charger = chg->sec_pl_present ? + POWER_SUPPLY_CHARGER_SEC_PL : + POWER_SUPPLY_CHARGER_SEC_NONE; + rc = smblib_select_sec_charger(chg, sec_charger, + POWER_SUPPLY_CP_NONE, false); + if (rc < 0) + dev_err(chg->dev, "Couldn't disable secondary charger rc=%d\n", + rc); + } + + vote(chg->dc_suspend_votable, CHG_TERMINATION_VOTER, false, 0); + + chg->last_wls_vout = 0; + } +#else + if (dcin_present) { + if (!vbus_present && chg->sec_cp_present) { + chg->flag_dc_present = 1; + vote(chg->awake_votable, DC_AWAKE_VOTER, true, 0); + if (chg->idtp_psy) { + pval.intval = true; + power_supply_set_property(chg->idtp_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + } + } + } else { + vote(chg->awake_votable, DC_AWAKE_VOTER, false, 0); + vote(chg->dc_icl_votable, DCIN_ADAPTER_VOTER, true, 100000); + chg->flag_dc_present = 0; + chg->cp_reason = POWER_SUPPLY_CP_NONE; + sec_charger = chg->sec_pl_present ? + POWER_SUPPLY_CHARGER_SEC_PL : + POWER_SUPPLY_CHARGER_SEC_NONE; + rc = smblib_select_sec_charger(chg, sec_charger, + POWER_SUPPLY_CP_NONE, false); + + if (rc < 0) + dev_err(chg->dev, + "Couldn't disable secondary charger rc=%d\n", + rc); + + if (chg->idtp_psy) { + pval.intval = false; + power_supply_set_property(chg->idtp_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + } + + if (chg->cp_reason == POWER_SUPPLY_CP_WIRELESS) { + sec_charger = chg->sec_pl_present ? + POWER_SUPPLY_CHARGER_SEC_PL : + POWER_SUPPLY_CHARGER_SEC_NONE; + rc = smblib_select_sec_charger(chg, sec_charger, + POWER_SUPPLY_CP_NONE, false); + if (rc < 0) + dev_err(chg->dev, "Couldn't disable secondary charger rc=%d\n", + rc); + } + + vote(chg->dc_suspend_votable, CHG_TERMINATION_VOTER, false, 0); + } +#endif power_supply_changed(chg->dc_psy); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->wls_psy) + power_supply_changed(chg->wls_psy); +#endif + smblib_dbg(chg, (PR_WLS | PR_INTERRUPT), "dcin_present= %d, usbin_present= %d, cp_reason = %d\n", dcin_present, vbus_present, chg->cp_reason); @@ -6574,6 +10228,11 @@ irqreturn_t wdog_bark_irq_handler(int irq, void *data) if (rc < 0) smblib_err(chg, "Couldn't pet the dog rc=%d\n", rc); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->step_chg_enabled || chg->sw_jeita_enabled) + power_supply_changed(chg->batt_psy); +#endif + return IRQ_HANDLED; } @@ -6618,6 +10277,102 @@ static void smblib_usbov_dbc_work(struct work_struct *work) vote(chg->awake_votable, USBOV_DBC_VOTER, false, 0); } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int smblib_get_step_vfloat_index(struct smb_charger *chg, + int val) +{ + int i; + + /* select correct index by compare start_vbat and range vfloat threshold */ + for (i = 0; i <= ARRAY_SIZE(chg->six_pin_step_cfg) - 1; i++) { + if (val < (chg->six_pin_step_cfg[i].vfloat_step_uv - VBAT_FOR_STEP_HYS_UV)) + break; + } + + if (i >= ARRAY_SIZE(chg->six_pin_step_cfg) - 1) + return ARRAY_SIZE(chg->six_pin_step_cfg) - 1; + + return i; +} + +static void smblib_six_pin_batt_step_chg_work(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + six_pin_batt_step_chg_work.work); + + int rc = 0; + int input_present; + int main_charge_type; + int interval_ms = STEP_CHG_DELAYED_MONITOR_MS; + union power_supply_propval pval = {0, }; + + rc = smblib_is_input_present(chg, &input_present); + if (rc < 0) + return; + + pr_err("input_present: %d\n", input_present); + if (input_present == INPUT_NOT_PRESENT) { + if (is_client_vote_enabled(chg->fv_votable, + SIX_PIN_VFLOAT_VOTER)) + vote(chg->fv_votable, SIX_PIN_VFLOAT_VOTER, false, 0); + if (is_client_vote_enabled(chg->fcc_votable, + SIX_PIN_VFLOAT_VOTER)) + vote(chg->fcc_votable, SIX_PIN_VFLOAT_VOTER, false, 0); + return; + } + + if (chg->start_step_vbat >= VBAT_FOR_STEP_MIN_UV) { + pr_err("start step vbat is too high, no need do step charge\n"); + return; + } + + /* set init start vfloat according to chg->start_step_vbat */ + if (!chg->init_start_vbat_checked) { + chg->index_vfloat = + smblib_get_step_vfloat_index(chg, chg->start_step_vbat); + vote(chg->fv_votable, SIX_PIN_VFLOAT_VOTER, + true, chg->six_pin_step_cfg[chg->index_vfloat].vfloat_step_uv); + vote(chg->fcc_votable, SIX_PIN_VFLOAT_VOTER, + true, chg->six_pin_step_cfg[chg->index_vfloat].fcc_step_ua); + chg->init_start_vbat_checked = true; + } + + rc = smblib_get_prop_batt_charge_type(chg, &pval); + if (rc < 0) { + pr_err("Couldn't get batt charge type rc=%d\n", rc); + return; + } + main_charge_type = pval.intval; + pr_err("main_charge_type: %d\n", main_charge_type); + + if (main_charge_type == POWER_SUPPLY_CHARGE_TYPE_TAPER) + chg->trigger_taper_count++; + else + chg->trigger_taper_count = 0; + + if (chg->trigger_taper_count >= MAX_COUNT_OF_IBAT_STEP) { + chg->index_vfloat++; + chg->trigger_taper_count = 0; + if (chg->index_vfloat < MAX_STEP_ENTRIES) { + vote(chg->fcc_votable, SIX_PIN_VFLOAT_VOTER, + true, chg->six_pin_step_cfg[chg->index_vfloat].fcc_step_ua); + vote(chg->fv_votable, SIX_PIN_VFLOAT_VOTER, + true, chg->six_pin_step_cfg[chg->index_vfloat].vfloat_step_uv); + } + if (chg->index_vfloat >= MAX_STEP_ENTRIES) + chg->index_vfloat = MAX_STEP_ENTRIES - 1; + } + + if (main_charge_type == POWER_SUPPLY_CHARGE_TYPE_TAPER) + interval_ms = STEP_CHG_DELAYED_QUICK_MONITOR_MS; + else + interval_ms = STEP_CHG_DELAYED_MONITOR_MS; + + schedule_delayed_work(&chg->six_pin_batt_step_chg_work, + msecs_to_jiffies(interval_ms)); +} +#endif + #define USB_OV_DBC_PERIOD_MS 1000 irqreturn_t usbin_ov_irq_handler(int irq, void *data) { @@ -7352,6 +11107,12 @@ static void jeita_update_work(struct work_struct *work) chg->jeita_soft_thlds[1] + SOFT_JEITA_HYSTERESIS_OFFSET; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* we still use old soft jeita method */ + chg->jeita_configured = JEITA_CFG_COMPLETE; + return; +#endif + chg->jeita_soft_fcc[0] = chg->jeita_soft_fcc[1] = -EINVAL; chg->jeita_soft_fv[0] = chg->jeita_soft_fv[1] = -EINVAL; max_fcc_ma = max_fv_uv = -EINVAL; @@ -7438,6 +11199,15 @@ static void smblib_lpd_ra_open_work(struct work_struct *work) if (!(stat & TYPEC_WATER_DETECTION_STATUS_BIT) || (stat & TYPEC_TCCDEBOUNCE_DONE_STATUS_BIT)) { chg->lpd_stage = LPD_STAGE_NONE; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->lpd_status = false; + + if (chg->support_liquid == true) { + vote(chg->usb_icl_votable, LIQUID_DETECTION_VOTER, false, 0); + if (chg->batt_psy) + power_supply_changed(chg->batt_psy); + } +#endif goto out; } @@ -7466,8 +11236,18 @@ static void smblib_lpd_ra_open_work(struct work_struct *work) } chg->lpd_reason = LPD_MOISTURE_DETECTED; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->lpd_status = true; +#endif chg->moisture_present = true; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (chg->support_liquid == true) { + vote(chg->usb_icl_votable, LIQUID_DETECTION_VOTER, true, 0); + if (chg->batt_psy) + power_supply_changed(chg->batt_psy); + } +#endif } else { /* Floating cable, disable water detection irq temporarily */ rc = smblib_masked_write(chg, TYPE_C_INTERRUPT_EN_CFG_2_REG, @@ -7491,11 +11271,27 @@ static void smblib_lpd_ra_open_work(struct work_struct *work) } /* recheck in 60 seconds */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + alarm_start_relative(&chg->lpd_recheck_timer, ms_to_ktime(15000)); +#else alarm_start_relative(&chg->lpd_recheck_timer, ms_to_ktime(60000)); +#endif out: vote(chg->awake_votable, LPD_VOTER, false, 0); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static void smblib_lpd_disable_chg_work(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + lpd_disable_chg_work); + + vote(chg->usb_icl_votable, LIQUID_DETECTION_VOTER, false, 0); + if (chg->batt_psy) + power_supply_changed(chg->batt_psy); +} +#endif + static void smblib_lpd_detach_work(struct work_struct *work) { struct smb_charger *chg = container_of(work, struct smb_charger, @@ -7505,6 +11301,55 @@ static void smblib_lpd_detach_work(struct work_struct *work) chg->lpd_stage = LPD_STAGE_NONE; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static void smblib_charger_type_recheck(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + charger_type_recheck.work); + int recheck_time = TYPE_RECHECK_TIME_5S; + static int last_charger_type, check_count; + int rc; + smblib_update_usb_type(chg); + + if (last_charger_type != chg->real_charger_type) + check_count--; + last_charger_type = chg->real_charger_type; + + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3 || +#ifdef CONFIG_MACH_XIAOMI_NABU + chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3P5 || +#endif + chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP || + chg->pd_active || (check_count >= TYPE_RECHECK_COUNT) || + ((chg->real_charger_type == POWER_SUPPLY_TYPE_USB_FLOAT) && + (chg->typec_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER))) { + check_count = 0; + return; + } + + if (smblib_get_prop_dfp_mode(chg) != POWER_SUPPLY_TYPEC_NONE) + goto check_next; + + if (!chg->recheck_charger) + chg->precheck_charger_type = chg->real_charger_type; + chg->recheck_charger = true; + + if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_FLOAT) { + rc = smblib_request_dpdm(chg, false); + if (rc < 0) + smblib_err(chg, "Couldn't disable DPDM rc=%d\n", rc); + + msleep(500); + } + smblib_rerun_apsd_if_required(chg); + +check_next: + check_count++; + schedule_delayed_work(&chg->charger_type_recheck, + msecs_to_jiffies(recheck_time)); +} +#endif + static char *dr_mode_text[] = { "ufp", "dfp", "none" }; @@ -7600,6 +11445,39 @@ static void smblib_dual_role_check_work(struct work_struct *work) vote(chg->awake_votable, DR_SWAP_VOTER, false, 0); } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static void smblib_batt_verify_update_work(struct work_struct *work) +{ + struct smb_charger *chg = container_of(work, struct smb_charger, + batt_verify_update_work.work); + int rc; + union power_supply_propval pval = {0,}; + static int count; + + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_AUTHENTIC, &pval); + if (rc < 0) { + pr_err("Couldn't get batt verify status rc=%d\n", rc); + } + chg->batt_verified = pval.intval; + pr_err("batt_verified =%d\n", chg->batt_verified); + if (chg->batt_verified) { + vote(chg->fcc_votable, BATT_VERIFY_VOTER, false, 0); + count = 0; + return; + } + if (count < 3) { + count ++; + pr_err("battery verify failed, we will recheck it!\n"); + schedule_delayed_work(&chg->batt_verify_update_work, + msecs_to_jiffies(3000)); + } else { + count = 0; + } + +} +#endif + static int smblib_create_votables(struct smb_charger *chg) { int rc = 0; @@ -7668,6 +11546,16 @@ static int smblib_create_votables(struct smb_charger *chg) return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->dc_icl_votable = create_votable("DC_ICL", VOTE_MIN, + smblib_dc_icl_vote_callback, + chg); + if (IS_ERR(chg->dc_icl_votable)) { + rc = PTR_ERR(chg->dc_icl_votable); + return rc; + } +#endif + chg->awake_votable = create_votable("AWAKE", VOTE_SET_ANY, smblib_awake_vote_callback, chg); @@ -7777,6 +11665,9 @@ int smblib_init(struct smb_charger *chg) INIT_WORK(&chg->pl_update_work, pl_update_work); INIT_WORK(&chg->jeita_update_work, jeita_update_work); INIT_WORK(&chg->dcin_aicl_work, dcin_aicl_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + INIT_WORK(&chg->lpd_disable_chg_work, smblib_lpd_disable_chg_work); +#endif INIT_DELAYED_WORK(&chg->clear_hdc_work, clear_hdc_work); INIT_DELAYED_WORK(&chg->icl_change_work, smblib_icl_change_work); INIT_DELAYED_WORK(&chg->pl_enable_work, smblib_pl_enable_work); @@ -7784,13 +11675,38 @@ int smblib_init(struct smb_charger *chg) INIT_DELAYED_WORK(&chg->bb_removal_work, smblib_bb_removal_work); INIT_DELAYED_WORK(&chg->lpd_ra_open_work, smblib_lpd_ra_open_work); INIT_DELAYED_WORK(&chg->lpd_detach_work, smblib_lpd_detach_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + INIT_DELAYED_WORK(&chg->batt_verify_update_work, smblib_batt_verify_update_work); +#endif + INIT_DELAYED_WORK(&chg->raise_qc3_vbus_work, smblib_raise_qc3_vbus_work); + INIT_DELAYED_WORK(&chg->charger_type_recheck, smblib_charger_type_recheck); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + INIT_DELAYED_WORK(&chg->six_pin_batt_step_chg_work, + smblib_six_pin_batt_step_chg_work); +#endif + INIT_DELAYED_WORK(&chg->cc_un_compliant_charge_work, + smblib_cc_un_compliant_charge_work); +#endif INIT_DELAYED_WORK(&chg->thermal_regulation_work, smblib_thermal_regulation_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + INIT_DELAYED_WORK(&chg->dc_plug_out_delay_work, smblib_dc_plug_out_work); +#endif INIT_DELAYED_WORK(&chg->usbov_dbc_work, smblib_usbov_dbc_work); INIT_DELAYED_WORK(&chg->role_reversal_check, smblib_dual_role_check_work); INIT_DELAYED_WORK(&chg->pr_swap_detach_work, smblib_pr_swap_detach_work); +#ifdef CONFIG_MACH_XIAOMI_NABU + INIT_DELAYED_WORK(&chg->check_vbat_work, smblib_check_vbat_work); +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chg->use_bq_pump) { + INIT_DELAYED_WORK(&chg->reduce_fcc_work, reduce_fcc_work); + INIT_DELAYED_WORK(&chg->thermal_setting_work, smblib_thermal_setting_work); + } +#endif INIT_DELAYED_WORK(&chg->pr_lock_clear_work, smblib_pr_lock_clear_work); if (chg->dcin_uusb_over_gpio_en) @@ -7799,6 +11715,10 @@ int smblib_init(struct smb_charger *chg) setup_timer(&chg->apsd_timer, apsd_timer_cb, (unsigned long)chg); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + INIT_DELAYED_WORK(&chg->report_soc_decimal_work, smblib_report_soc_decimal_work); + INIT_DELAYED_WORK(&chg->check_init_boot, smb_check_init_boot); +#endif if (chg->wa_flags & CHG_TERMINATION_WA) { INIT_WORK(&chg->chg_termination_work, smblib_chg_termination_work); @@ -7825,6 +11745,10 @@ int smblib_init(struct smb_charger *chg) } } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->pps_thermal_level = -EINVAL; +#endif + if (alarmtimer_get_rtcdev()) { alarm_init(&chg->dcin_aicl_alarm, ALARM_REALTIME, dcin_aicl_alarm_cb); @@ -7841,7 +11765,14 @@ int smblib_init(struct smb_charger *chg) chg->sec_chg_selected = POWER_SUPPLY_CHARGER_SEC_NONE; chg->cp_reason = POWER_SUPPLY_CP_NONE; chg->thermal_status = TEMP_BELOW_RANGE; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chg->batt_temp_irq_enabled = false; +#endif chg->dr_mode = DUAL_ROLE_PROP_MODE_NONE; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->esr_work_status = ESR_CHECK_FCC_NOLIMIT; + chg->hvdcp_recheck_status = false; +#endif chg->typec_irq_en = true; switch (chg->mode) { @@ -7870,6 +11801,9 @@ int smblib_init(struct smb_charger *chg) chg->bms_psy = power_supply_get_by_name("bms"); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chg->batt_verify_psy = power_supply_get_by_name("batt_verify"); +#endif if (chg->sec_pl_present) { chg->pl.psy = power_supply_get_by_name("parallel"); if (chg->pl.psy) { @@ -7947,10 +11881,28 @@ int smblib_deinit(struct smb_charger *chg) cancel_delayed_work_sync(&chg->bb_removal_work); cancel_delayed_work_sync(&chg->lpd_ra_open_work); cancel_delayed_work_sync(&chg->lpd_detach_work); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + cancel_delayed_work_sync(&chg->batt_verify_update_work); +#endif + cancel_delayed_work_sync(&chg->raise_qc3_vbus_work); + cancel_delayed_work_sync(&chg->charger_type_recheck); + cancel_delayed_work_sync(&chg->cc_un_compliant_charge_work); +#endif cancel_delayed_work_sync(&chg->thermal_regulation_work); cancel_delayed_work_sync(&chg->usbov_dbc_work); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + cancel_delayed_work_sync(&chg->six_pin_batt_step_chg_work); +#endif cancel_delayed_work_sync(&chg->role_reversal_check); cancel_delayed_work_sync(&chg->pr_swap_detach_work); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + cancel_delayed_work_sync(&chg->report_soc_decimal_work); + cancel_delayed_work_sync(&chg->check_init_boot); +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + cancel_delayed_work_sync(&chg->check_vbat_work); +#endif power_supply_unreg_notifier(&chg->nb); smblib_destroy_votables(chg); qcom_step_chg_deinit(); @@ -7967,3 +11919,16 @@ int smblib_deinit(struct smb_charger *chg) return 0; } + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int __init early_parse_off_charge_flag(char *p) +{ + if (p) { + if (!strcmp(p, "charger")) + off_charge_flag = true; + } + + return 0; +} +early_param("androidboot.mode", early_parse_off_charge_flag); +#endif diff --git a/drivers/power/supply/qcom/smb5-lib.h b/drivers/power/supply/qcom/smb5-lib.h index 72eb66100c27..07b19e0e8098 100644 --- a/drivers/power/supply/qcom/smb5-lib.h +++ b/drivers/power/supply/qcom/smb5-lib.h @@ -26,6 +26,12 @@ #include #include "storm-watch.h" #include "battery.h" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#include +#include +#include +#include +#endif enum print_reason { PR_INTERRUPT = BIT(0), @@ -40,6 +46,9 @@ enum print_reason { #define USER_VOTER "USER_VOTER" #define PD_VOTER "PD_VOTER" #define DCP_VOTER "DCP_VOTER" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define CP_VOTER "CP_VOTER" +#endif #define QC_VOTER "QC_VOTER" #define USB_PSY_VOTER "USB_PSY_VOTER" #define PL_TAPER_WORK_RUNNING_VOTER "PL_TAPER_WORK_RUNNING_VOTER" @@ -59,6 +68,12 @@ enum print_reason { #define SW_ICL_MAX_VOTER "SW_ICL_MAX_VOTER" #define PL_QNOVO_VOTER "PL_QNOVO_VOTER" #define QNOVO_VOTER "QNOVO_VOTER" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define OTG_VOTER "OTG_VOTER" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define SW_DISABLE_DC_VOTER "SW_DISABLE_DC_VOTER" +#endif +#endif #define BATT_PROFILE_VOTER "BATT_PROFILE_VOTER" #define OTG_DELAY_VOTER "OTG_DELAY_VOTER" #define USBIN_I_VOTER "USBIN_I_VOTER" @@ -66,12 +81,37 @@ enum print_reason { #define PL_FCC_LOW_VOTER "PL_FCC_LOW_VOTER" #define WBC_VOTER "WBC_VOTER" #define HW_LIMIT_VOTER "HW_LIMIT_VOTER" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CHG_AWAKE_VOTER "CHG_AWAKE_VOTER" +#define DCIN_ADAPTER_VOTER "DCIN_ADAPTER_VOTER" +#define DCIN_LIMIT_VOTER "DCIN_LIMIT_VOTER" +#endif #define PL_SMB_EN_VOTER "PL_SMB_EN_VOTER" #define FORCE_RECHARGE_VOTER "FORCE_RECHARGE_VOTER" #define LPD_VOTER "LPD_VOTER" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define DC_AWAKE_VOTER "DC_AWAKE_VOTER" +#define DC_UV_AWAKE_VOTER "DC_UV_AWAKE_VOTER" +#define CLASSA_QC_FCC_VOTER "CLASSA_QC_FCC_VOTER" +#define QC_A_CP_ICL_MAX_VOTER "QC_A_CP_ICL_MAX_VOTER" +#define JEITA_VOTER "JEITA_VOTER" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define UNSTANDARD_QC2_VOTER "UNSTANDARD_QC2_VOTER" +#endif +#endif #define FCC_STEPPER_VOTER "FCC_STEPPER_VOTER" #define SW_THERM_REGULATION_VOTER "SW_THERM_REGULATION_VOTER" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define SW_CONN_THERM_VOTER "SW_CONN_THERM_VOTER" +#endif +#define LIQUID_DETECTION_VOTER "LIQUID_DETECTION_VOTER" +#define QC2_UNSUPPORTED_VOTER "QC2_UNSUPPORTED_VOTER" +#endif #define JEITA_ARB_VOTER "JEITA_ARB_VOTER" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define AFTER_FFC_VOTER "AFTER_FFC_VOTER" +#endif #define MOISTURE_VOTER "MOISTURE_VOTER" #define HVDCP2_ICL_VOTER "HVDCP2_ICL_VOTER" #define AICL_THRESHOLD_VOTER "AICL_THRESHOLD_VOTER" @@ -90,9 +130,109 @@ enum print_reason { #define OVERHEAT_LIMIT_VOTER "OVERHEAT_LIMIT_VOTER" #define GPIO_DCIN_VOTER "GPIO_DCIN_VOTER" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define FCC_VOTER "FCC_VOTER" +#define ICL_CHANGE_VOTER "ICL_CHANGE_VOTER" +#endif +#define PD_VERIFED_VOTER "PD_VERIFED_VOTER" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define PD_REMOVE_COMP_VOTER "PD_REMOVE_COMP_VOTER" +#define STEP_BMS_CHG_VOTER "STEP_BMS_CHG_VOTER" +#define STEP_CHG_VOTER "STEP_CHG_VOTER" +#define LOW_ILIM_VOTER "LOW_ILIM_VOTER" +/* used for bq charge pump solution */ +#define MAIN_CHG_VOTER "MAIN_CHG_VOTER" +#define HVDCP3_START_ICL_VOTER "HVDCP3_START_ICL_VOTER" +#define MAIN_CHG_SUSPEND_VOTER "MAIN_CHG_SUSPEND_VOTER" +#ifdef CONFIG_MACH_XIAOMI_NABU +/* use for QC3P5 */ +#define QC3P5_VOTER "QC3P5_VOTER" +#define FCC_MAX_QC3P5_VOTER "FCC_MAX_QC3P5_VOTER" +/* use for Ln8000 */ +#define BATT_LN8000_VOTER "BATT_LN8000_VOTER" +#define BATT_BQ2597X_VOTER "BATT_BQ2597X_VOTER" +#endif + +#define WLS_FCC_VOTER "WLS_FCC_VOTER" +#endif +#endif + #define BOOST_BACK_STORM_COUNT 3 #define WEAK_CHG_STORM_COUNT 8 +#ifdef CONFIG_MACH_XIAOMI_NABU +#define MAX_QC3P5_PLUSE_COUNT_ALLOWED 230 +#define QC3P5_DP_RAPIDLY_TUNE_ALLOWED 120 +#define QC3P5_DP_RAPIDLY_TUNE_PULSE 10 +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +/* defined for distinguish qc class_a and class_b */ +#define VOL_THR_FOR_QC_CLASS_AB 12300000 +#define COMP_FOR_LOW_RESISTANCE_CABLE 100000 +#define QC_CLASS_A_CURRENT_UA 3600000 +#define HVDCP_CLASS_A_MAX_UA 2500000 +#define HVDCP_CLASS_A_FOR_CP_UA 2000000 +#define MAX_PULSE 38 +#define MAX_PLUSE_COUNT_ALLOWED 30 +#define HIGH_NUM_PULSE_THR 12 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define PD_UNVERIFED_CURRENT 4800000 +#else +#define PD_UNVERIFED_CURRENT 3000000 +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define PD_UNVERIFED_VOLTAGE 4450000 +#define PD_REMOVE_COMP_CURRENT 7000000 +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +/* QC2.0 voltage UV threshold 7.8V */ +#define QC2_HVDCP_VOL_UV_THR 7800000 +#define CHECK_VBUS_WORK_DELAY_MS 200 +#define UNSTANDARD_HVDCP2_UA 1800000 + +#define BAT_TEMP_COLD 0 +#define BAT_TEMP_COOL 150 +#define BAT_TEMP_HOT 450 +#define BAT_TEMP_TOO_HOT 580 + +#define TEMP_COOL_RECHARGE_VBAT 4300 + +/*early attached report power supply changed*/ +#define EARLY_ATTACH_DELAY_MS 20000 +#endif + +/* thermal micros */ +#define MAX_TEMP_LEVEL 16 +/* percent of ICL compared to base 5V for different PD voltage_min voltage */ +#define PD_6P5V_PERCENT 85 +#define PD_7P5V_PERCENT 75 +#define PD_8P5V_PERCENT 70 +#define PD_9V_PERCENT 65 +#define PD_MICRO_5V 5000000 +#define PD_MICRO_5P9V 5900000 +#define PD_MICRO_6P5V 6500000 +#define PD_MICRO_7P5V 7500000 +#define PD_MICRO_8P5V 8500000 +#define PD_MICRO_9V 9000000 +#define ICL_LIMIT_LEVEL_THR 8 + +/* defined for qc2_unsupported */ +#define QC2_UNSUPPORTED_UA 1800000 +/* defined for HVDCP2 */ +#define HVDCP2_CURRENT_UA 1500000 + +/* defined for charger type recheck */ +#define CHARGER_RECHECK_DELAY_MS 30000 +#define TYPE_RECHECK_TIME_5S 5000 +#define TYPE_RECHECK_COUNT 3 + +/* defined for un_compliant Type-C cable */ +#define CC_UN_COMPLIANT_START_DELAY_MS 700 +#endif + #define VBAT_TO_VRAW_ADC(v) div_u64((u64)v * 1000000UL, 194637UL) #define ITERM_LIMITS_PMI632_MA 5000 @@ -102,14 +242,125 @@ enum print_reason { #define SDP_100_MA 100000 #define SDP_CURRENT_UA 500000 #define CDP_CURRENT_UA 1500000 +#ifdef CONFIG_MACH_XIAOMI_NABU +#define DCP_CURRENT_UA 2000000 +#elif defined(CONFIG_MACH_XIAOMI_SM8150) +#define DCP_CURRENT_UA 1600000 +#else #define DCP_CURRENT_UA 1500000 +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define HVDCP_CURRENT_UA 2800000 +#else #define HVDCP_CURRENT_UA 3000000 +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define HVDCP_CLASS_B_CURRENT_UA 3100000 +#define HVDCP_START_CURRENT_UA_FOR_BQ 500000 +#endif #define TYPEC_DEFAULT_CURRENT_UA 900000 #define TYPEC_MEDIUM_CURRENT_UA 1500000 #define TYPEC_HIGH_CURRENT_UA 3000000 #define DCIN_ICL_MIN_UA 100000 #define DCIN_ICL_MAX_UA 1500000 #define DCIN_ICL_STEP_UA 100000 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define SLOWLY_CHARGING_CURRENT 1000000 +#define ADC_CHG_TERM_MASK 32767 +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU +#define HVDCP3P5_40W_CURRENT_UA 4500000 +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +/*DCIN ICL*/ +#define PSNS_CURRENT_SAMPLE_RATE 1053 +#define PSNS_CURRENT_SAMPLE_RESIS 392 +#define PSNS_COMP_UV_FOR_HIGH_THERMAL 40000 + +/* cutoff voltage threshold */ +#define CUTOFF_VOL_THR 3400000 + +#define RECHARGE_SOC_THR 99 + + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define ESR_WORK_VOTER "ESR_WORK_VOTER" +#define SLOWLY_CHARGING_VOTER "SLOWLY_CHARGING_VOTER" +#define BATT_VERIFY_VOTER "BATT_VERIFY_VOTER" + +/* six pin new battery step charge micros */ +#define MAX_STEP_ENTRIES 3 +#define MAX_COUNT_OF_IBAT_STEP 2 + +#define STEP_CHG_DELAYED_MONITOR_MS 15000 +#define STEP_CHG_DELAYED_QUICK_MONITOR_MS 5000 +#define STEP_CHG_DELAYED_START_MS 100 +#define VBAT_FOR_STEP_MIN_UV 4300000 +#define VBAT_FOR_STEP_HYS_UV 20000 + +#define MAIN_ICL_MIN 100000 +#define SIX_PIN_VFLOAT_VOTER "SIX_PIN_VFLOAT_VOTER" +#define WARM_VFLOAT_UV 4100000 + +#define NON_FFC_VFLOAT_VOTER "NON_FFC_VFLOAT_VOTER" +#define NON_FFC_VFLOAT_UV 4450000 + +#define CP_COOL_THRESHOLD 150 +#define CP_WARM_THRESHOLD 450 +#define SOFT_JEITA_HYSTERESIS 5 + +/* used for bq charge pump solution */ +#define MAIN_CHARGER_ICL 2000000 +#define QC3_CHARGER_ICL 500000 +#ifdef CONFIG_MACH_XIAOMI_NABU +#define QC3P5_CHARGER_ICL 2000000 +#else +#define QC3P5_CHARGER_ICL 200000 +#endif + +#define MAIN_CHARGER_STOP_ICL 50000 +#define ESR_WORK_TIME_2S 2000 +#define ESR_WORK_TIME_180S 180000 + +/* six pin battery data struct */ +struct six_pin_step_data { + u32 vfloat_step_uv; + u32 fcc_step_ua; +}; + +#define DEFAULT_FFC_LOW_TBAT 150 +#define DEFAULT_FFC_HIGH_TBAT 450 + +enum esr_work_status { + ESR_CHECK_FCC_NOLIMIT, + ESR_CHECK_FCC_LIMITED, +}; + +#define REPORT_SOC_DECIMAL_MS 100 + +/* cutoff voltage threshold */ +#define CUTOFF_VOL_THR 3400000 +#define CUTOFF_VOL_HYS 50000 + +/* wdog bark timer */ +#define BARK_TIMER_LONG 128 +#define BARK_TIMER_NORMAL 16 + +/* for override ffc terminate current */ +#define OVERRIDE_FFC_TERM_CURRENT 820 +#endif + +enum hvdcp3_type { + HVDCP3_NONE = 0, + HVDCP3_CLASSA_18W, + HVDCP3_CLASSB_27W, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + HVDCP3P5_CLASSA_18W, + HVDCP3P5_CLASSB_27W, +#endif +}; +#endif #define ROLE_REVERSAL_DELAY_MS 2000 @@ -249,6 +500,21 @@ enum comp_clamp_levels { MAX_CLAMP_LEVEL, }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +enum quick_charge_type { + QUICK_CHARGE_NORMAL = 0, + QUICK_CHARGE_FAST, + QUICK_CHARGE_FLASH, + QUICK_CHARGE_TURBE, + QUICK_CHARGE_MAX, +}; + +struct quick_charge { + enum power_supply_type adap_type; + enum quick_charge_type adap_cap; +}; +#endif + struct clamp_config { u16 reg[3]; u16 val[3]; @@ -304,6 +570,10 @@ enum icl_override_mode { SW_OVERRIDE_USB51_MODE, /* ICL other than USB51 */ SW_OVERRIDE_HC_MODE, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* ICL in cc float mode */ + SW_OVERRIDE_NO_CC_MODE, +#endif }; /* EXTCON_USB and EXTCON_USB_HOST are mutually exclusive */ @@ -379,6 +649,10 @@ struct smb_iio { struct iio_channel *die_temp_chan; struct iio_channel *skin_temp_chan; struct iio_channel *smb_temp_chan; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct iio_channel *hw_version_gpio5; + struct iio_channel *project_gpio6; +#endif }; struct smb_charger { @@ -395,6 +669,14 @@ struct smb_charger { int otg_delay_ms; int *weak_chg_icl_ua; bool pd_not_supported; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool init_once; + bool support_liquid; + bool dynamic_fv_enabled; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool batt_verified; +#endif +#endif /* locks */ struct mutex smb_lock; @@ -411,11 +693,29 @@ struct smb_charger { struct power_supply *usb_psy; struct power_supply *dc_psy; struct power_supply *bms_psy; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct power_supply_desc usb_psy_desc; +#endif struct power_supply *usb_main_psy; struct power_supply *usb_port_psy; struct power_supply *wls_psy; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct power_supply *idtp_psy; + struct power_supply *wip_psy; + struct power_supply *wireless_psy; + struct power_supply *wls_chip_psy; +#endif struct power_supply *cp_psy; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct power_supply *ln_psy; + struct power_supply *halo_psy; + struct power_supply *cp_chip_psy; + struct power_supply *batt_verify_psy; +#endif enum power_supply_type real_charger_type; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + enum power_supply_type wireless_charger_type; +#endif /* dual role class */ struct dual_role_phy_instance *dual_role; @@ -441,6 +741,9 @@ struct smb_charger { struct votable *fcc_main_votable; struct votable *fv_votable; struct votable *usb_icl_votable; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct votable *dc_icl_votable; +#endif struct votable *awake_votable; struct votable *pl_disable_votable; struct votable *chg_disable_votable; @@ -450,6 +753,9 @@ struct smb_charger { struct votable *icl_irq_disable_votable; struct votable *limited_irq_disable_votable; struct votable *hdc_irq_disable_votable; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct votable *cp_ilim_votable; +#endif struct votable *temp_change_irq_disable_votable; /* work */ @@ -459,21 +765,56 @@ struct smb_charger { struct work_struct moisture_protection_work; struct work_struct chg_termination_work; struct work_struct dcin_aicl_work; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct work_struct lpd_disable_chg_work; +#endif struct delayed_work ps_change_timeout_work; struct delayed_work clear_hdc_work; struct delayed_work icl_change_work; struct delayed_work pl_enable_work; struct delayed_work uusb_otg_work; struct delayed_work bb_removal_work; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct delayed_work batt_verify_update_work; +#endif + struct delayed_work raise_qc3_vbus_work; +#endif struct delayed_work lpd_ra_open_work; struct delayed_work lpd_detach_work; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct delayed_work charger_type_recheck; + struct delayed_work cc_un_compliant_charge_work; +#endif struct delayed_work thermal_regulation_work; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct delayed_work conn_therm_work; + struct delayed_work after_ffc_chg_dis_work; + struct delayed_work after_ffc_chg_en_work; +#endif + struct delayed_work dc_plug_out_delay_work; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct delayed_work report_soc_decimal_work; +#endif +#endif struct delayed_work usbov_dbc_work; struct delayed_work role_reversal_check; struct delayed_work pr_swap_detach_work; struct delayed_work pr_lock_clear_work; struct delayed_work micro_usb_switch_work; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct delayed_work check_vbus_work; + struct delayed_work check_init_boot; + struct delayed_work early_attach; + struct delayed_work six_pin_batt_step_chg_work; + struct delayed_work reduce_fcc_work; + struct delayed_work thermal_setting_work; +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + struct delayed_work check_vbat_work; +#endif struct alarm lpd_recheck_timer; struct alarm moisture_protection_alarm; struct alarm chg_termination_alarm; @@ -487,15 +828,30 @@ struct smb_charger { bool sec_cp_present; int sec_chg_selected; int cp_reason; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int cp_mode; + int cp_fcc; + int cp_main_fcc; +#endif /* pd */ int voltage_min_uv; int voltage_max_uv; int pd_active; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int apdo_max; +#endif + int pd_verifed; +#endif bool pd_hard_reset; bool pr_lock_in_progress; bool pr_swap_in_progress; bool early_usb_attach; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool early_dc_attach; + bool batt_temp_irq_enabled; +#endif bool ok_to_pd; bool typec_legacy; bool typec_irq_en; @@ -505,14 +861,49 @@ struct smb_charger { bool system_suspend_supported; int boost_threshold_ua; int system_temp_level; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int pps_thermal_level; +#endif int thermal_levels; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int lpd_levels; + int dc_temp_level; + int dc_thermal_levels; + int *thermal_mitigation_dcp; + int *thermal_mitigation_qc2; + int *thermal_mitigation_pd_base; + int *thermal_mitigation_icl; + int *thermal_fcc_qc3_normal; + int *thermal_fcc_qc3_cp; + int *thermal_fcc_qc3_classb_cp; + int *thermal_fcc_pps_cp; + int *thermal_mitigation_dc; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int *thermal_mitigation_voice; +#endif + int *lpd_hwversion; + int *thermal_mitigation_epp; + int *thermal_mitigation_bpp_qc3; + int *thermal_mitigation_bpp_qc2; + int *thermal_mitigation_bpp; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int *thermal_mitigation_dc_20W; +#endif +#else int *thermal_mitigation; +#endif int dcp_icl_ua; int fake_capacity; int fake_batt_status; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int fake_conn_temp; +#endif bool step_chg_enabled; bool sw_jeita_enabled; bool typec_legacy_use_rp_icl; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool lpd_enabled; +#endif bool is_hdc; bool chg_done; int connector_type; @@ -534,6 +925,9 @@ struct smb_charger { bool hvdcp_disable; int hw_max_icl_ua; int auto_recharge_soc; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int auto_recharge_vbat; +#endif enum sink_src_mode sink_src_mode; enum power_supply_typec_power_role power_role; enum jeita_cfg_stat jeita_configured; @@ -543,13 +937,22 @@ struct smb_charger { enum lpd_stage lpd_stage; bool lpd_disabled; enum lpd_reason lpd_reason; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool lpd_status; +#endif bool fcc_stepper_enable; int die_temp; int smb_temp; int skin_temp; int connector_temp; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + u64 entry_time; +#endif int thermal_status; int main_fcc_max; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool report_usb_absent; +#endif u32 jeita_soft_thlds[2]; u32 jeita_soft_hys_thlds[2]; int jeita_soft_fcc[2]; @@ -580,6 +983,22 @@ struct smb_charger { bool dpdm_enabled; bool apsd_ext_timeout; bool qc3p5_detected; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int vbus_disable; +#ifdef CONFIG_MACH_XIAOMI_NABU + bool en_bq_flag; +#endif + int64_t rpp; + int64_t cep; + int64_t tx_bt_mac; +#ifdef CONFIG_MACH_XIAOMI_NABU + int64_t pen_bt_mac; +#endif + int reverse_chg_state; +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + int reverse_gpio_state; +#endif /* workaround flag */ u32 wa_flags; @@ -587,6 +1006,14 @@ struct smb_charger { int qc2_max_pulses; enum qc2_non_comp_voltage qc2_unsupported_voltage; bool dbc_usbov; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool fake_usb_insertion; + bool qc2_unsupported; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool check_vbus_once; + bool unstandard_hvdcp; +#endif +#endif /* extcon for VBUS / ID notification to USB for uUSB */ struct extcon_dev *extcon; @@ -600,6 +1027,15 @@ struct smb_charger { int die_health; int connector_health; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* raise qc3 vbus flag */ + bool qc_class_ab; + bool is_qc_class_a; + bool is_qc_class_b; + bool raise_vbus_to_detect; + bool detect_low_power_qc3_charger; + bool high_vbus_detected; +#endif /* flash */ u32 flash_derating_soc; @@ -623,6 +1059,89 @@ struct smb_charger { int micro_usb_pre_state; bool dcin_uusb_over_gpio_en; bool aicl_disable; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int wireless_vout; +#endif + int flag_dc_present; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int flag_cp_en; +#endif + int power_good_en; + int fake_dc_on; + int fake_dc_flag; + int last_batt_stat; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int last_vout_set; +#endif + /* charger type recheck */ + int recheck_charger; + int precheck_charger_type; + /* workarounds */ + bool cc_un_compliant_detected; + bool snk_debug_acc_detected; + bool support_wireless; +#ifdef CONFIG_MACH_XIAOMI_NABU + bool wireless_bq; +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool support_conn_therm; + bool ext_fg; + int conn_detect_count; + int vbus_disable_gpio; + int remove_comp; + u64 last_ffc_remove_time; +#endif +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* used for bq charge pump solution */ + struct usbpd *pd; + bool use_bq_pump; + + /* reduce fcc for esr cal*/ + int esr_work_status; + bool cp_charge_enabled; + int charge_type; + int charge_status; + int batt_health; + + bool override_ffc_term_current; + /* for 27W charge*/ + bool temp_27W_enable; + + /* used for 6pin new battery step charge */ + bool six_pin_step_charge_enable; + bool init_start_vbat_checked; + struct six_pin_step_data six_pin_step_cfg[MAX_STEP_ENTRIES]; + u32 start_step_vbat; + int trigger_taper_count; + int index_vfloat; + + /* fast full charge related */ + int chg_term_current_thresh_hi_from_dts; + bool support_ffc; + int ffc_low_tbat; + int ffc_high_tbat; + bool slowly_charging; + bool already_start_step_charge_work; + bool bq_input_suspend; + + bool hvdcp_recheck_status; + + /* QC3P5 related */ + bool qc3p5_supported; + bool qc3p5_auth_complete; + bool qc3p5_authenticated; + bool qc3p5_authentication_started; + bool qc3p5_dp_tune_rapidly; + int qc3p5_power_limit_w; + + bool pps_fcc_therm_work_disabled; + int wls_cp_vin; + int64_t oob_rpp_msg_cnt; + int64_t oob_cep_msg_cnt; +#endif }; int smblib_read(struct smb_charger *chg, u16 addr, u8 *val); @@ -641,6 +1160,10 @@ int smblib_set_charge_param(struct smb_charger *chg, int smblib_set_usb_suspend(struct smb_charger *chg, bool suspend); int smblib_set_dc_suspend(struct smb_charger *chg, bool suspend); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_change_psns_to_curr(struct smb_charger *chg, int uv); +#endif + int smblib_mapping_soc_from_field_value(struct smb_chg_param *param, int val_u, u8 *val_raw); int smblib_mapping_cc_delta_to_field_value(struct smb_chg_param *param, @@ -662,6 +1185,9 @@ int smblib_vconn_regulator_disable(struct regulator_dev *rdev); int smblib_vconn_regulator_is_enabled(struct regulator_dev *rdev); irqreturn_t default_irq_handler(int irq, void *data); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +irqreturn_t dcin_uv_handler(int irq, void *data); +#endif irqreturn_t smb_en_irq_handler(int irq, void *data); irqreturn_t chg_state_change_irq_handler(int irq, void *data); irqreturn_t batt_temp_changed_irq_handler(int irq, void *data); @@ -689,6 +1215,10 @@ int smblib_get_prop_batt_present(struct smb_charger *chg, union power_supply_propval *val); int smblib_get_prop_batt_capacity(struct smb_charger *chg, union power_supply_propval *val); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_get_prop_batt_capacity_level(struct smb_charger *chg, + union power_supply_propval *val); +#endif int smblib_get_prop_batt_status(struct smb_charger *chg, union power_supply_propval *val); int smblib_get_prop_batt_charge_type(struct smb_charger *chg, @@ -701,6 +1231,10 @@ int smblib_get_prop_system_temp_level(struct smb_charger *chg, union power_supply_propval *val); int smblib_get_prop_system_temp_level_max(struct smb_charger *chg, union power_supply_propval *val); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_get_prop_dc_temp_level(struct smb_charger *chg, + union power_supply_propval *val); +#endif int smblib_get_prop_input_current_limited(struct smb_charger *chg, union power_supply_propval *val); int smblib_get_prop_batt_iterm(struct smb_charger *chg, @@ -713,6 +1247,10 @@ int smblib_set_prop_batt_status(struct smb_charger *chg, const union power_supply_propval *val); int smblib_set_prop_system_temp_level(struct smb_charger *chg, const union power_supply_propval *val); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_set_prop_dc_temp_level(struct smb_charger *chg, + const union power_supply_propval *val); +#endif int smblib_set_prop_input_current_limited(struct smb_charger *chg, const union power_supply_propval *val); @@ -732,6 +1270,10 @@ int smblib_get_prop_voltage_wls_output(struct smb_charger *chg, union power_supply_propval *val); int smblib_set_prop_voltage_wls_output(struct smb_charger *chg, const union power_supply_propval *val); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_get_prop_wireless_version(struct smb_charger *chg, + union power_supply_propval *val); +#endif int smblib_set_prop_dc_reset(struct smb_charger *chg); int smblib_get_prop_usb_present(struct smb_charger *chg, union power_supply_propval *val); @@ -774,6 +1316,13 @@ int smblib_get_prop_input_current_max(struct smb_charger *chg, union power_supply_propval *val); int smblib_set_prop_thermal_overheat(struct smb_charger *chg, int therm_overheat); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_get_prop_vph_voltage_now(struct smb_charger *chg, + union power_supply_propval *val); +int smblib_get_prop_connector_temp(struct smb_charger *chg); +int smblib_set_vbus_disable(struct smb_charger *chg, + bool disable); +#endif int smblib_get_skin_temp_status(struct smb_charger *chg); int smblib_get_prop_vph_voltage_now(struct smb_charger *chg, union power_supply_propval *val); @@ -797,6 +1346,10 @@ int smblib_set_prop_ship_mode(struct smb_charger *chg, const union power_supply_propval *val); int smblib_set_prop_rechg_soc_thresh(struct smb_charger *chg, const union power_supply_propval *val); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_set_prop_rechg_vbat_thresh(struct smb_charger *chg, + const union power_supply_propval *val); +#endif void smblib_suspend_on_debug_battery(struct smb_charger *chg); int smblib_rerun_apsd_if_required(struct smb_charger *chg); void smblib_rerun_apsd(struct smb_charger *chg); @@ -804,11 +1357,21 @@ int smblib_get_prop_fcc_delta(struct smb_charger *chg, union power_supply_propval *val); int smblib_get_thermal_threshold(struct smb_charger *chg, u16 addr, int *val); int smblib_dp_dm(struct smb_charger *chg, int val); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_dp_dm_bq(struct smb_charger *chg, int val); +#endif int smblib_disable_hw_jeita(struct smb_charger *chg, bool disable); int smblib_run_aicl(struct smb_charger *chg, int type); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_rerun_aicl(struct smb_charger *chg); +#endif int smblib_set_icl_current(struct smb_charger *chg, int icl_ua); int smblib_get_icl_current(struct smb_charger *chg, int *icl_ua); int smblib_get_charge_current(struct smb_charger *chg, int *total_current_ua); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_get_charge_current_limit(struct smb_charger *chg, + int *total_current_ua); +#endif int smblib_get_prop_pr_swap_in_progress(struct smb_charger *chg, union power_supply_propval *val); int smblib_set_prop_pr_swap_in_progress(struct smb_charger *chg, @@ -825,6 +1388,49 @@ int smblib_configure_hvdcp_apsd(struct smb_charger *chg, bool enable); int smblib_icl_override(struct smb_charger *chg, enum icl_override_mode mode); enum alarmtimer_restart smblib_lpd_recheck_timer(struct alarm *alarm, ktime_t time); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int smblib_set_prop_wireless_wakelock(struct smb_charger *chg, + const union power_supply_propval *val); + +int smblib_set_prop_type_recheck(struct smb_charger *chg, + const union power_supply_propval *val); +int smblib_get_prop_type_recheck(struct smb_charger *chg, + union power_supply_propval *val); +int smblib_get_quick_charge_type(struct smb_charger *chg); +int smblib_set_wirless_cp_enable(struct smb_charger *chg, + const union power_supply_propval *val); +int smblib_set_wirless_power_good_enable(struct smb_charger *chg, + const union power_supply_propval *val); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_set_fastcharge_mode(struct smb_charger *chg, bool enable); +int smblib_get_fastcharge_mode(struct smb_charger *chg); +int smblib_set_sw_disable_dc_en(struct smb_charger *chg, + const union power_supply_propval *val); +#endif +int smblib_get_prop_liquid_status(struct smb_charger *chg, + union power_supply_propval *val); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_set_prop_tx_mac(struct smb_charger *chg, + const union power_supply_propval *val); +#ifdef CONFIG_MACH_XIAOMI_NABU +void smblib_set_prop_pen_mac(struct smb_charger *chg, + const union power_supply_propval *val); +#endif +int smblib_set_prop_rx_cr(struct smb_charger *chg, + const union power_supply_propval *val); +int smblib_set_prop_rx_cep(struct smb_charger *chg, + const union power_supply_propval *val); +int smblib_set_prop_bt_state(struct smb_charger *chg, + const union power_supply_propval *val); +#endif + +bool smblib_support_liquid_feature(struct smb_charger *chg); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smblib_set_prop_battery_charging_enabled(struct smb_charger *chg, + const union power_supply_propval *val); +#endif +#endif int smblib_toggle_smb_en(struct smb_charger *chg, int toggle); void smblib_hvdcp_detect_enable(struct smb_charger *chg, bool enable); void smblib_hvdcp_exit_config(struct smb_charger *chg); @@ -832,8 +1438,28 @@ void smblib_apsd_enable(struct smb_charger *chg, bool enable); int smblib_force_vbus_voltage(struct smb_charger *chg, u8 val); int smblib_get_irq_status(struct smb_charger *chg, union power_supply_propval *val); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int smb5_config_iterm(struct smb_charger *chg, int hi_thresh, int low_thresh); +int smblib_get_prop_battery_charging_enabled(struct smb_charger *chg, + union power_supply_propval *val); +int smblib_get_prop_battery_charging_limited(struct smb_charger *chg, + union power_supply_propval *val); +int smblib_get_prop_battery_slowly_charging(struct smb_charger *chg, + union power_supply_propval *val); +int smblib_set_prop_battery_slowly_charging(struct smb_charger *chg, + const union power_supply_propval *val); +int smblib_get_prop_battery_bq_input_suspend(struct smb_charger *chg, + union power_supply_propval *val); +#endif int smblib_get_qc3_main_icl_offset(struct smb_charger *chg, int *offset_ua); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +struct usbpd *smb_get_usbpd(void); +#endif int smblib_init(struct smb_charger *chg); int smblib_deinit(struct smb_charger *chg); +#ifdef CONFIG_MACH_XIAOMI_NABU +int smblib_get_prop_wireless_fw_version(struct smb_charger *chg, + union power_supply_propval *val); +#endif #endif /* __SMB5_CHARGER_H */ diff --git a/drivers/power/supply/qcom/smb5-reg.h b/drivers/power/supply/qcom/smb5-reg.h index 444841d67c82..214441ab03cc 100644 --- a/drivers/power/supply/qcom/smb5-reg.h +++ b/drivers/power/supply/qcom/smb5-reg.h @@ -281,6 +281,21 @@ enum { HVDCP_PULSE_COUNT_MAX_QC2_INVALID = 0xC0 }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define USBIN_ADAPTER_ALLOW_CFG_REG (USBIN_BASE + 0x60) +enum { + USBIN_ADAPTER_ALLOW_5V = 0, + USBIN_ADAPTER_ALLOW_9V = 2, + USBIN_ADAPTER_ALLOW_5V_OR_9V = 3, + USBIN_ADAPTER_ALLOW_12V = 4, + USBIN_ADAPTER_ALLOW_5V_OR_12V = 5, + USBIN_ADAPTER_ALLOW_9V_TO_12V = 6, + USBIN_ADAPTER_ALLOW_5V_OR_9V_TO_12V = 7, + USBIN_ADAPTER_ALLOW_5V_TO_9V = 8, + USBIN_ADAPTER_ALLOW_5V_TO_12V = 12, +}; +#endif + #define USBIN_OPTIONS_1_CFG_REG (USBIN_BASE + 0x62) #define HVDCP_AUTH_ALG_EN_CFG_BIT BIT(6) #define HVDCP_AUTONOMOUS_MODE_EN_CFG_BIT BIT(5) @@ -317,6 +332,11 @@ enum { #define USBIN_5V_AICL_THRESHOLD_REG (USBIN_BASE + 0x81) #define USBIN_CONT_AICL_THRESHOLD_REG (USBIN_BASE + 0x84) + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define APSD_START_ON_CC_BIT BIT(7) +#endif + /******************************** * DCIN Peripheral Registers * ********************************/ @@ -327,8 +347,17 @@ enum { #define DCIN_CMD_IL_REG (DCIN_BASE + 0x40) #define DCIN_SUSPEND_BIT BIT(0) #define DCIN_EN_OVERRIDE_BIT BIT(1) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define DCIN_EN_BIT BIT(2) +#endif #define DCIN_EN_MASK GENMASK(2, 1) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define DCIN_CMD_PULLDOWN_REG (DCIN_BASE + 0x45) +#define DCIN_PULLDOWN_EN_BIT BIT(0) +#define DCIN_MID_PULLDOWN_BIT BIT(1) +#endif + #define DCIN_CMD_PON_REG (DCIN_BASE + 0x45) #define DCIN_PON_BIT BIT(0) #define MID_CHG_BIT BIT(1) @@ -349,6 +378,11 @@ enum { #define SNK_RP_3P0_BIT BIT(1) #define SNK_RP_SHORT_BIT BIT(0) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define TYPE_C_SNK_DEBUG_ACC_STATUS_REG (TYPEC_BASE + 0x07) +#define SNK_DEBUG_ACC_RPSTD_PRSTD_BIT BIT(0) +#endif + #define TYPE_C_SRC_STATUS_REG (TYPEC_BASE + 0x08) #define DETECTED_SNK_TYPE_MASK GENMASK(4, 0) #define SRC_HIGH_BATT_BIT BIT(5) @@ -400,6 +434,12 @@ enum { #define TYPEC_CCOUT_VALUE_BIT BIT(1) #define TYPEC_CCOUT_SRC_BIT BIT(0) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define TYPE_C_DEBUG_ACC_SNK_CFG (TYPEC_BASE + 0x4A) +#define TYPEC_DEBUG_ACC_SNK_SEL_ICL BIT(2) +#define TYPEC_DEBUG_ACC_SNK_DIS_AICL BIT(3) +#endif + #define DEBUG_ACCESS_SRC_CFG_REG (TYPEC_BASE + 0x4C) #define EN_UNORIENTED_DEBUG_ACCESS_SRC_BIT BIT(0) @@ -457,6 +497,9 @@ enum { #define EN_MICRO_USB_WATER_PROTECTION_BIT BIT(4) #define MICRO_USB_DETECTION_ON_TIME_CFG_MASK GENMASK(3, 2) #define MICRO_USB_DETECTION_PERIOD_CFG_MASK GENMASK(1, 0) +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define TYPEC_MICRO_USB_MODE_REG (TYPEC_BASE + 0x73) +#endif #define PMI632_TYPEC_MICRO_USB_MODE_REG (TYPEC_BASE + 0x73) #define MICRO_USB_MODE_ONLY_BIT BIT(0) @@ -515,6 +558,9 @@ enum { #define WATCHDOG_TRIGGER_AFP_EN_BIT BIT(7) #define BARK_WDOG_INT_EN_BIT BIT(6) #define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define WDOG_TIMER_EN_BIT BIT(0) +#endif #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x53) #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7) diff --git a/drivers/power/supply/qcom/step-chg-jeita.c b/drivers/power/supply/qcom/step-chg-jeita.c index 72191eca56bb..43aa26996511 100644 --- a/drivers/power/supply/qcom/step-chg-jeita.c +++ b/drivers/power/supply/qcom/step-chg-jeita.c @@ -22,6 +22,9 @@ #define STEP_CHG_VOTER "STEP_CHG_VOTER" #define JEITA_VOTER "JEITA_VOTER" +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define DYNAMIC_FV_VOTER "DYNAMIC_FV_VOTER" +#endif #define is_between(left, right, value) \ (((left) >= (right) && (left) >= (value) \ @@ -44,38 +47,70 @@ struct jeita_fv_cfg { struct range_data fv_cfg[MAX_STEP_CHG_ENTRIES]; }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +struct dynamic_fv_cfg { + char *prop_name; + struct range_data fv_cfg[MAX_STEP_CHG_ENTRIES]; +}; +#endif + struct step_chg_info { struct device *dev; ktime_t step_last_update_time; ktime_t jeita_last_update_time; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + ktime_t dynamic_fv_last_update_time; +#endif bool step_chg_enable; bool sw_jeita_enable; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool dynamic_fv_enable; +#endif bool jeita_arb_en; bool config_is_read; bool step_chg_cfg_valid; bool sw_jeita_cfg_valid; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool dynamic_fv_cfg_valid; +#endif bool soc_based_step_chg; bool ocv_based_step_chg; bool vbat_avg_based_step_chg; bool batt_missing; bool taper_fcc; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool six_pin_battery; + bool use_bq_pump; +#endif int jeita_fcc_index; int jeita_fv_index; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int dynamic_fv_index; +#endif int step_index; int get_config_retry_count; struct step_chg_cfg *step_chg_config; struct jeita_fcc_cfg *jeita_fcc_config; struct jeita_fv_cfg *jeita_fv_config; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct dynamic_fv_cfg *dynamic_fv_config; +#endif struct votable *fcc_votable; struct votable *fv_votable; struct votable *usb_icl_votable; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct votable *dc_suspend_votable; +#endif struct wakeup_source *step_chg_ws; struct power_supply *batt_psy; struct power_supply *bms_psy; struct power_supply *usb_psy; struct power_supply *dc_psy; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + struct power_supply *bq_psy; +#endif struct delayed_work status_change_work; struct delayed_work get_config_work; struct notifier_block nb; @@ -123,6 +158,24 @@ static bool is_usb_available(struct step_chg_info *chip) return true; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static bool is_bq25970_available(struct step_chg_info *chip) +{ + if (!chip->bq_psy) + chip->bq_psy = power_supply_get_by_name("bq2597x-standalone"); + +#ifdef CONFIG_MACH_XIAOMI_NABU + if (!chip->bq_psy) + chip->bq_psy = power_supply_get_by_name("ln8000"); +#endif + + if (!chip->bq_psy) + return false; + + return true; +} +#endif + static bool is_input_present(struct step_chg_info *chip) { int rc = 0, input_present = 0; @@ -262,8 +315,13 @@ static int get_step_chg_jeita_setting_from_profile(struct step_chg_info *chip) if (batt_id_ohms < 0) return -EBUSY; +#ifndef CONFIG_MACH_XIAOMI_NABU profile_node = of_batterydata_get_best_profile(batt_node, batt_id_ohms / 1000, NULL); +#else + profile_node = of_batterydata_get_best_profile(batt_node, + batt_id_ohms / 1000, "K82_sunwoda_8720mah"); +#endif if (IS_ERR(profile_node)) return PTR_ERR(profile_node); @@ -360,6 +418,26 @@ static int get_step_chg_jeita_setting_from_profile(struct step_chg_info *chip) chip->sw_jeita_cfg_valid = false; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->dynamic_fv_cfg_valid = true; + rc = read_range_data_from_node(profile_node, + "qcom,dynamic-fv-ranges", + chip->dynamic_fv_config->fv_cfg, + BATT_HOT_DECIDEGREE_MAX, max_fv_uv); + if (rc < 0) { + pr_debug("Read qcom,dynamic-fv-ranges failed from battery profile, rc=%d\n", + rc); + chip->dynamic_fv_cfg_valid = false; + } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chip->six_pin_battery = + of_property_read_bool(profile_node, "mi,six-pin-battery"); + chip->use_bq_pump = + of_property_read_bool(profile_node, "qcom,use-bq-pump"); +#endif +#endif + return rc; } @@ -417,6 +495,16 @@ static int get_val(struct range_data *range, int hysteresis, int current_index, *new_index = -EINVAL; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + /* + * As battery temperature may be below 0, range.xxx is a unsigned int, but battery + * temperature is a signed int, so cannot compare them when battery temp is below 0, + * we treat it as 0 degree when the parameter threshold(battery temp) is below 0. + */ + if (threshold < 0) + threshold = 0; +#endif + /* * If the threshold is lesser than the minimum allowed range, * return -ENODATA. @@ -456,6 +544,16 @@ static int get_val(struct range_data *range, int hysteresis, int current_index, *val = range[*new_index].value; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (threshold < range[0].low_threshold) { + *new_index = 0; + *val = range[*new_index].value; + } else if (threshold > range[MAX_STEP_CHG_ENTRIES - 1].low_threshold) { + *new_index = MAX_STEP_CHG_ENTRIES - 1; + *val = range[*new_index].value; + } +#endif + /* * If we don't have a current_index return this * newfound value. There is no hysterisis from out of range @@ -538,10 +636,32 @@ static int handle_step_chg_config(struct step_chg_info *chip) union power_supply_propval pval = {0, }; int rc = 0, fcc_ua = 0, current_index; u64 elapsed_us; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int update_now = 0; + static int usb_present; +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!is_usb_available(chip)) + return 0; + rc = power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + if (rc < 0) { + pr_err("Get battery present status failed, rc=%d\n", rc); + return rc; + } + if (pval.intval && pval.intval != usb_present) + update_now = true; + usb_present = pval.intval; +#endif elapsed_us = ktime_us_delta(ktime_get(), chip->step_last_update_time); /* skip processing, event too early */ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (elapsed_us < STEP_CHG_HYSTERISIS_DELAY_US && !update_now) +#else if (elapsed_us < STEP_CHG_HYSTERISIS_DELAY_US) +#endif return 0; rc = power_supply_get_property(chip->batt_psy, @@ -557,12 +677,24 @@ static int handle_step_chg_config(struct step_chg_info *chip) goto update_time; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (chip->use_bq_pump) { + if (is_bq25970_available(chip)) { + rc = power_supply_get_property(chip->bq_psy, + POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, &pval); + pval.intval = pval.intval * 1000; + } + } else { +#endif if (chip->step_chg_config->param.use_bms) rc = power_supply_get_property(chip->bms_psy, chip->step_chg_config->param.psy_prop, &pval); else rc = power_supply_get_property(chip->batt_psy, chip->step_chg_config->param.psy_prop, &pval); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + } +#endif if (rc < 0) { pr_err("Couldn't read %s property rc=%d\n", @@ -614,12 +746,111 @@ static int handle_step_chg_config(struct step_chg_info *chip) return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int handle_dynamic_fv(struct step_chg_info *chip) +{ + union power_supply_propval pval = {0, }; + int rc = 0, fv_uv, cycle_count; + u64 elapsed_us; + int batt_vol = 0; + + rc = power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED, &pval); + if (rc < 0) + chip->dynamic_fv_enable = 0; + else + chip->dynamic_fv_enable = pval.intval; + + if (!chip->dynamic_fv_enable || !chip->dynamic_fv_cfg_valid) { + /*need recovery some setting*/ + if (chip->fv_votable) + vote(chip->fv_votable, DYNAMIC_FV_VOTER, false, 0); + return 0; + } + + elapsed_us = ktime_us_delta(ktime_get(), chip->dynamic_fv_last_update_time); + /* skip processing, event too early */ + if (elapsed_us < STEP_CHG_HYSTERISIS_DELAY_US) + return 0; + + rc = power_supply_get_property(chip->bms_psy, + POWER_SUPPLY_PROP_CYCLE_COUNT, &pval); + if (rc < 0) { + pr_err("Couldn't read %s property rc=%d\n", + chip->dynamic_fv_config->prop_name, rc); + return rc; + } + cycle_count = pval.intval; + + rc = get_val(chip->dynamic_fv_config->fv_cfg, + 0, + chip->dynamic_fv_index, + cycle_count, + &chip->dynamic_fv_index, + &fv_uv); + if (rc < 0) { + /* remove the vote if no step-based fv is found */ + if (chip->fv_votable) + vote(chip->fv_votable, DYNAMIC_FV_VOTER, false, 0); + goto update_time; + } + + power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, &pval); + batt_vol = pval.intval; + if (batt_vol >= fv_uv) { + goto update_time; + } + + chip->fv_votable = find_votable("FV"); + if (!chip->fv_votable) + goto update_time; + + vote(chip->fv_votable, DYNAMIC_FV_VOTER, true, fv_uv); + + /*set battery full voltage to FLOAT VOLTAGE - 10mV*/ + pval.intval = fv_uv - 10000; + rc = power_supply_set_property(chip->bms_psy, + POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE, &pval); + if (rc < 0) { + pr_err("Couldn't set CONSTANT VOLTAGE property rc=%d\n", rc); + return rc; + } + + pr_debug("%s:cycle_count:%d,Batt_full:%d,fv:%d,\n", + __func__, cycle_count, pval.intval, fv_uv); + +update_time: + chip->dynamic_fv_last_update_time = ktime_get(); + return 0; +} +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define JEITA_SUSPEND_HYST_UV 130000 +#elif defined(CONFIG_MACH_XIAOMI_SM8150) +#define JEITA_SUSPEND_HYST_UV 70000 +#else #define JEITA_SUSPEND_HYST_UV 50000 +#endif +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define JEITA_SIX_PIN_BATT_HYST_UV 100000 +#define WARM_VFLOAT_UV 4100000 +#endif static int handle_jeita(struct step_chg_info *chip) { union power_supply_propval pval = {0, }; int rc = 0, fcc_ua = 0, fv_uv = 0; u64 elapsed_us; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int update_now = 0; + int curr_vfloat_uv, curr_vbat_uv; + int temp, pd_authen_result = 0; + static bool fast_mode_dis, usb_present; + int batt_soc = 0, batt_temp = 0; + static bool ffc_temp_is_high; + bool set_term_curr_flag = false; +#endif rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_SW_JEITA_ENABLED, &pval); @@ -635,12 +866,35 @@ static int handle_jeita(struct step_chg_info *chip) vote(chip->fv_votable, JEITA_VOTER, false, 0); if (chip->usb_icl_votable) vote(chip->usb_icl_votable, JEITA_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (chip->dc_suspend_votable) + vote(chip->dc_suspend_votable, JEITA_VOTER, 0, 0); +#endif + return 0; + } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!is_usb_available(chip)) return 0; + + rc = power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_PRESENT, &pval); + if (rc < 0) { + pr_err("Get battery present status failed, rc=%d\n", rc); + return rc; } + if (pval.intval && pval.intval != usb_present) + update_now = true; + usb_present = pval.intval; +#endif elapsed_us = ktime_us_delta(ktime_get(), chip->jeita_last_update_time); /* skip processing, event too early */ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (elapsed_us < STEP_CHG_HYSTERISIS_DELAY_US && !update_now) +#else if (elapsed_us < STEP_CHG_HYSTERISIS_DELAY_US) +#endif return 0; if (chip->jeita_fcc_config->param.use_bms) @@ -656,6 +910,9 @@ static int handle_jeita(struct step_chg_info *chip) return rc; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + temp = pval.intval; +#endif rc = get_val(chip->jeita_fcc_config->fcc_cfg, chip->jeita_fcc_config->param.hysteresis, chip->jeita_fcc_index, @@ -671,6 +928,11 @@ static int handle_jeita(struct step_chg_info *chip) /* changing FCC is a must */ return -EINVAL; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (rc == -ENODATA) + vote(chip->fcc_votable, JEITA_VOTER, true, fcc_ua); + else +#endif vote(chip->fcc_votable, JEITA_VOTER, fcc_ua ? true : false, fcc_ua); rc = get_val(chip->jeita_fv_config->fv_cfg, @@ -682,6 +944,51 @@ static int handle_jeita(struct step_chg_info *chip) if (rc < 0) fv_uv = 0; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + batt_temp = pval.intval; + rc = power_supply_get_property(chip->bms_psy, + POWER_SUPPLY_PROP_CAPACITY, &pval); + if (rc < 0) { + pr_err("Couldn't read batt_soc fail rc=%d\n", rc); + return rc; + } + batt_soc = pval.intval; + pr_info("%s:batt_soc=%d\n", __func__, batt_soc); + rc = power_supply_get_property(chip->bms_psy, + POWER_SUPPLY_PROP_FASTCHARGE_MODE, &pval); + pr_err("%s:fastcharge_mode=%d\n", __func__, pval.intval); + if (rc < 0) { + pr_err("Couldn't read fastcharge mode fail rc=%d\n", rc); + return rc; + } + if (pval.intval) { + if (batt_soc < 95) { + if (!ffc_temp_is_high && batt_temp > FFC_CHG_TERM_TEMP_THRESHOLD +10) { + ffc_temp_is_high = true; + set_term_curr_flag = true; + } else if (ffc_temp_is_high && batt_temp < FFC_CHG_TERM_TEMP_THRESHOLD-10) { + ffc_temp_is_high = false; + set_term_curr_flag = true; + } + if (set_term_curr_flag) { + rc = power_supply_get_property(chip->bms_psy, + POWER_SUPPLY_PROP_FFC_TERMINATION_CURRENT, &pval); + if (rc < 0) { + pr_err("Couldn't read ffc_term_curr fail rc=%d\n", rc); + return rc; + } + rc = power_supply_set_property(chip->batt_psy, + POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT, &pval); + if (rc < 0) { + pr_err("Set charge_term_curr failed, rc=%d\n", rc); + return rc; + } + } + } + } + pval.intval = batt_temp; +#endif + chip->fv_votable = find_votable("FV"); if (!chip->fv_votable) goto update_time; @@ -692,6 +999,62 @@ static int handle_jeita(struct step_chg_info *chip) if (!chip->usb_icl_votable) goto set_jeita_fv; +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (!chip->dc_suspend_votable) + chip->dc_suspend_votable = find_votable("DC_SUSPEND"); + + if (!chip->dc_suspend_votable) + goto set_jeita_fv; +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* set and clear fast charge mode when soft jeita trigger and clear */ + if (chip->six_pin_battery) { + rc = power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_PD_AUTHENTICATION, &pval); + if (rc < 0) + pr_err("Get fastcharge mode status failed, rc=%d\n", rc); + pd_authen_result = pval.intval; + + rc = power_supply_get_property(chip->usb_psy, + POWER_SUPPLY_PROP_HVDCP3_TYPE, &pval); + if (rc < 0) + pr_err("get hvdcp3_type failed, rc=%d\n", rc); + + if ((pval.intval == HVDCP3_CLASS_B_27W) +#ifdef CONFIG_MACH_XIAOMI_NABU + || (pval.intval == HVDCP3P5_CLASS_A_18W) + || (pval.intval == HVDCP3P5_CLASS_B_27W) +#endif + || (pd_authen_result == 1)) { + if ((temp >= BATT_WARM_THRESHOLD || temp <= BATT_COOL_THRESHOLD) + && !fast_mode_dis) { + pval.intval = false; + rc = power_supply_set_property(chip->usb_psy, + POWER_SUPPLY_PROP_FASTCHARGE_MODE, &pval); + if (rc < 0) { + pr_err("Set fastcharge mode failed, rc=%d\n", rc); + return rc; + } + fast_mode_dis = true; + } else if ((temp < BATT_WARM_THRESHOLD - chip->jeita_fv_config->param.hysteresis) + && (temp > BATT_COOL_THRESHOLD + chip->jeita_fv_config->param.hysteresis) + && fast_mode_dis) { + pval.intval = true; + rc = power_supply_set_property(chip->usb_psy, + POWER_SUPPLY_PROP_FASTCHARGE_MODE, &pval); + if (rc < 0) { + pr_err("Set fastcharge mode failed, rc=%d\n", rc); + return rc; + } + fast_mode_dis = false; + } + } else { + fast_mode_dis = false; + } + } +#endif + /* * If JEITA float voltage is same as max-vfloat of battery then * skip any further VBAT specific checks. @@ -700,6 +1063,9 @@ static int handle_jeita(struct step_chg_info *chip) POWER_SUPPLY_PROP_VOLTAGE_MAX, &pval); if (rc || (pval.intval == fv_uv)) { vote(chip->usb_icl_votable, JEITA_VOTER, false, 0); +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + vote(chip->dc_suspend_votable, JEITA_VOTER, 0, 0); +#endif goto set_jeita_fv; } @@ -707,13 +1073,66 @@ static int handle_jeita(struct step_chg_info *chip) * Suspend USB input path if battery voltage is above * JEITA VFLOAT threshold. */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (fv_uv > 0) { +#else if (chip->jeita_arb_en && fv_uv > 0) { +#endif rc = power_supply_get_property(chip->batt_psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, &pval); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (rc < 0) { + pr_err("Get battery voltage failed, rc = %d\n", rc); + goto set_jeita_fv; + } + curr_vbat_uv = pval.intval; + + if (!chip->six_pin_battery) { + if ((curr_vbat_uv > fv_uv) && (temp >= BATT_WARM_THRESHOLD)) + vote(chip->usb_icl_votable, JEITA_VOTER, true, 0); + else if (curr_vbat_uv < (fv_uv - JEITA_SUSPEND_HYST_UV)) + vote(chip->usb_icl_votable, JEITA_VOTER, false, 0); + } else { + curr_vfloat_uv = get_effective_result(chip->fv_votable); + + rc = power_supply_get_property(chip->batt_psy, + POWER_SUPPLY_PROP_CHARGE_TYPE, &pval); + if (rc < 0) { + pr_err("Get charge type failed, rc = %d\n", rc); + goto set_jeita_fv; + } + + if (curr_vfloat_uv != WARM_VFLOAT_UV) { + if (curr_vbat_uv > fv_uv + JEITA_SIX_PIN_BATT_HYST_UV) { + if (pval.intval == POWER_SUPPLY_CHARGE_TYPE_TAPER && fv_uv == WARM_VFLOAT_UV) + vote(chip->usb_icl_votable, JEITA_VOTER, true, 0); + } else if (curr_vbat_uv < (fv_uv - JEITA_SUSPEND_HYST_UV)) { + vote(chip->usb_icl_votable, JEITA_VOTER, false, 0); + } + } else { + pr_info("curr_vbat_uv = %duV,FCC =%duA,FV = %duV\n",curr_vbat_uv, fcc_ua, fv_uv); + if (curr_vbat_uv > fv_uv + JEITA_SIX_PIN_BATT_HYST_UV) { + if (pval.intval == POWER_SUPPLY_CHARGE_TYPE_TAPER && fv_uv == WARM_VFLOAT_UV) + vote(chip->usb_icl_votable, JEITA_VOTER, true, 0); + } else if (curr_vbat_uv < (fv_uv - JEITA_SUSPEND_HYST_UV)) { + vote(chip->usb_icl_votable, JEITA_VOTER, false, 0); + } + } + } +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + if (!rc && (pval.intval > fv_uv)) { + vote(chip->usb_icl_votable, JEITA_VOTER, true, 0); + vote(chip->dc_suspend_votable, JEITA_VOTER, 1, 0); + } else if (pval.intval < (fv_uv - JEITA_SUSPEND_HYST_UV)) { + vote(chip->usb_icl_votable, JEITA_VOTER, false, 0); + vote(chip->dc_suspend_votable, JEITA_VOTER, 0, 0); + } +#else if (!rc && (pval.intval > fv_uv)) vote(chip->usb_icl_votable, JEITA_VOTER, true, 0); else if (pval.intval < (fv_uv - JEITA_SUSPEND_HYST_UV)) vote(chip->usb_icl_votable, JEITA_VOTER, false, 0); +#endif } set_jeita_fv: @@ -744,6 +1163,9 @@ static int handle_battery_insertion(struct step_chg_info *chip) if (chip->batt_missing) { chip->step_chg_cfg_valid = false; chip->sw_jeita_cfg_valid = false; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->dynamic_fv_cfg_valid = false; +#endif chip->get_config_retry_count = 0; } else { /* @@ -765,7 +1187,11 @@ static void status_change_work(struct work_struct *work) int rc = 0; union power_supply_propval prop = {0, }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (!is_batt_available(chip) || !is_bms_available(chip) || !is_usb_available(chip)) +#else if (!is_batt_available(chip) || !is_bms_available(chip)) +#endif goto exit_work; handle_battery_insertion(chip); @@ -775,6 +1201,12 @@ static void status_change_work(struct work_struct *work) if (rc < 0) pr_err("Couldn't handle sw jeita rc = %d\n", rc); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + rc = handle_dynamic_fv(chip); + if (rc < 0) + pr_err("Couldn't handle sw dynamic fv rc = %d\n", rc); +#endif + rc = handle_step_chg_config(chip); if (rc < 0) pr_err("Couldn't handle step rc = %d\n", rc); @@ -860,6 +1292,9 @@ int qcom_step_chg_init(struct device *dev, chip->step_index = -EINVAL; chip->jeita_fcc_index = -EINVAL; chip->jeita_fv_index = -EINVAL; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->dynamic_fv_index = -EINVAL; +#endif chip->step_chg_config = devm_kzalloc(dev, sizeof(struct step_chg_cfg), GFP_KERNEL); @@ -868,22 +1303,45 @@ int qcom_step_chg_init(struct device *dev, chip->step_chg_config->param.psy_prop = POWER_SUPPLY_PROP_VOLTAGE_NOW; chip->step_chg_config->param.prop_name = "VBATT"; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + chip->step_chg_config->param.hysteresis = 10000; +#else chip->step_chg_config->param.hysteresis = 100000; +#endif chip->jeita_fcc_config = devm_kzalloc(dev, sizeof(struct jeita_fcc_cfg), GFP_KERNEL); chip->jeita_fv_config = devm_kzalloc(dev, sizeof(struct jeita_fv_cfg), GFP_KERNEL); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->dynamic_fv_config = devm_kzalloc(dev, + sizeof(struct dynamic_fv_cfg), GFP_KERNEL); +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!chip->jeita_fcc_config || !chip->jeita_fv_config || !chip->dynamic_fv_config) +#else if (!chip->jeita_fcc_config || !chip->jeita_fv_config) +#endif return -ENOMEM; chip->jeita_fcc_config->param.psy_prop = POWER_SUPPLY_PROP_TEMP; chip->jeita_fcc_config->param.prop_name = "BATT_TEMP"; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->jeita_fcc_config->param.hysteresis = 5; +#else chip->jeita_fcc_config->param.hysteresis = 10; +#endif chip->jeita_fv_config->param.psy_prop = POWER_SUPPLY_PROP_TEMP; chip->jeita_fv_config->param.prop_name = "BATT_TEMP"; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->jeita_fv_config->param.hysteresis = 5; +#else chip->jeita_fv_config->param.hysteresis = 10; +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 + chip->dynamic_fv_config->prop_name = "BATT_CYCLE_COUNT"; +#endif INIT_DELAYED_WORK(&chip->status_change_work, status_change_work); INIT_DELAYED_WORK(&chip->get_config_work, get_config_work); diff --git a/drivers/power/supply/qcom/step-chg-jeita.h b/drivers/power/supply/qcom/step-chg-jeita.h index 26e74ed484e9..3016100a76a5 100644 --- a/drivers/power/supply/qcom/step-chg-jeita.h +++ b/drivers/power/supply/qcom/step-chg-jeita.h @@ -13,7 +13,31 @@ #ifndef __STEP_CHG_H__ #define __STEP_CHG_H__ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define MAX_STEP_CHG_ENTRIES 6 +#elif defined(CONFIG_MACH_XIAOMI_SM8150) +#define MAX_STEP_CHG_ENTRIES 5 +#else #define MAX_STEP_CHG_ENTRIES 8 +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define BATT_CP_COOL_THRESHOLD 100 +#define BATT_CP_WARM_THRESHOLD 450 + +#define BATT_COOL_THRESHOLD 150 +#define BATT_WARM_THRESHOLD 450 +#define FFC_CHG_TERM_TEMP_THRESHOLD 350 +enum hvdcp3_class_type { + HVDCP3_CLASS_NONE = 0, + HVDCP3_CLASS_A_18W, + HVDCP3_CLASS_B_27W, +#ifdef CONFIG_MACH_XIAOMI_NABU + HVDCP3P5_CLASS_A_18W, + HVDCP3P5_CLASS_B_27W, +#endif +}; +#endif struct step_chg_jeita_param { u32 psy_prop; @@ -34,4 +58,7 @@ void qcom_step_chg_deinit(void); int read_range_data_from_node(struct device_node *node, const char *prop_str, struct range_data *ranges, int max_threshold, u32 max_value); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int qcom_step_chg_get_step_index(void); +#endif #endif /* __STEP_CHG_H__ */ diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index b8c434c34c8c..578f91092c05 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -117,6 +117,16 @@ enum { POWER_SUPPLY_PL_USBMID_USBMID, }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +enum { + POWER_SUPPLY_CP_UNKNOWN, + POWER_SUPPLY_CP_MID, + POWER_SUPPLY_CP_MID_EXT, + POWER_SUPPLY_CP_USBIN, + POWER_SUPPLY_CP_USBIN_EXT, +}; +#endif + enum { POWER_SUPPLY_CHARGER_SEC_NONE = 0, POWER_SUPPLY_CHARGER_SEC_CP, @@ -127,7 +137,9 @@ enum { enum { POWER_SUPPLY_CP_NONE = 0, POWER_SUPPLY_CP_HVDCP3, +#ifndef CONFIG_MACH_XIAOMI_VAYU POWER_SUPPLY_CP_HVDCP3P5, +#endif POWER_SUPPLY_CP_PPS, POWER_SUPPLY_CP_WIRELESS, }; @@ -192,6 +204,10 @@ enum power_supply_property { POWER_SUPPLY_PROP_CHARGE_NOW, POWER_SUPPLY_PROP_CHARGE_AVG, POWER_SUPPLY_PROP_CHARGE_COUNTER, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_FFC_TERMINATION_CURRENT, +#endif POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT, POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE, @@ -209,6 +225,14 @@ enum power_supply_property { POWER_SUPPLY_PROP_CAPACITY_ALERT_MIN, /* in percents! */ POWER_SUPPLY_PROP_CAPACITY_ALERT_MAX, /* in percents! */ POWER_SUPPLY_PROP_CAPACITY_LEVEL, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_SHUTDOWN_DELAY, + POWER_SUPPLY_PROP_SHUTDOWN_DELAY_ENABLE, + POWER_SUPPLY_PROP_RAW_CAPACITY, + POWER_SUPPLY_PROP_SOC_DECIMAL, + POWER_SUPPLY_PROP_SOC_DECIMAL_RATE, + POWER_SUPPLY_PROP_COLD_THERMAL_LEVEL, +#endif POWER_SUPPLY_PROP_TEMP, POWER_SUPPLY_PROP_TEMP_MAX, POWER_SUPPLY_PROP_TEMP_MIN, @@ -232,6 +256,10 @@ enum power_supply_property { POWER_SUPPLY_PROP_CHARGE_ENABLED, POWER_SUPPLY_PROP_SET_SHIP_MODE, POWER_SUPPLY_PROP_REAL_TYPE, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_HVDCP3_TYPE, + POWER_SUPPLY_PROP_QUICK_CHARGE_TYPE, +#endif POWER_SUPPLY_PROP_CHARGE_NOW_RAW, POWER_SUPPLY_PROP_CHARGE_NOW_ERROR, POWER_SUPPLY_PROP_CAPACITY_RAW, @@ -242,6 +270,10 @@ enum power_supply_property { POWER_SUPPLY_PROP_PIN_ENABLED, POWER_SUPPLY_PROP_INPUT_SUSPEND, POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION, +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_PROP_INPUT_VOLTAGE_VRECT, + POWER_SUPPLY_PROP_RX_IOUT, +#endif POWER_SUPPLY_PROP_INPUT_CURRENT_MAX, POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM, POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED, @@ -270,6 +302,9 @@ enum power_supply_property { POWER_SUPPLY_PROP_FLASH_TRIGGER, POWER_SUPPLY_PROP_FORCE_TLIM, POWER_SUPPLY_PROP_DP_DM, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_DP_DM_BQ, +#endif POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED, POWER_SUPPLY_PROP_INPUT_CURRENT_NOW, POWER_SUPPLY_PROP_CHARGE_QNOVO_ENABLE, @@ -286,8 +321,17 @@ enum power_supply_property { POWER_SUPPLY_PROP_TYPEC_SRC_RP, POWER_SUPPLY_PROP_PD_ALLOWED, POWER_SUPPLY_PROP_PD_ACTIVE, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_PD_AUTHENTICATION, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_PD_REMOVE_COMPENSATION, +#endif +#endif POWER_SUPPLY_PROP_PD_IN_HARD_RESET, POWER_SUPPLY_PROP_PD_CURRENT_MAX, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_APDO_MAX, +#endif POWER_SUPPLY_PROP_PD_USB_SUSPEND_SUPPORTED, POWER_SUPPLY_PROP_CHARGER_TEMP, POWER_SUPPLY_PROP_CHARGER_TEMP_MAX, @@ -300,6 +344,10 @@ enum power_supply_property { POWER_SUPPLY_PROP_PARALLEL_MODE, POWER_SUPPLY_PROP_DIE_HEALTH, POWER_SUPPLY_PROP_CONNECTOR_HEALTH, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_CONNECTOR_TEMP, + POWER_SUPPLY_PROP_VBUS_DISABLE, +#endif POWER_SUPPLY_PROP_CTM_CURRENT_MAX, POWER_SUPPLY_PROP_HW_CURRENT_MAX, POWER_SUPPLY_PROP_PR_SWAP, @@ -309,15 +357,75 @@ enum power_supply_property { POWER_SUPPLY_PROP_PD_VOLTAGE_MAX, POWER_SUPPLY_PROP_PD_VOLTAGE_MIN, POWER_SUPPLY_PROP_SDP_CURRENT_MAX, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_DC_THERMAL_LEVELS, +#endif POWER_SUPPLY_PROP_CONNECTOR_TYPE, POWER_SUPPLY_PROP_PARALLEL_BATFET_MODE, POWER_SUPPLY_PROP_PARALLEL_FCC_MAX, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_WIRELESS_VERSION, +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_PROP_WIRELESS_FW_VERSION, +#endif + POWER_SUPPLY_PROP_SIGNAL_STRENGTH, + POWER_SUPPLY_PROP_WIRELESS_CP_EN, + POWER_SUPPLY_PROP_WIRELESS_POWER_GOOD_EN, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_SW_DISABLE_DC_EN, +#endif + POWER_SUPPLY_PROP_WIRELESS_WAKELOCK, +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_PROP_WIRELESS_TX_ID, +#endif + POWER_SUPPLY_PROP_TX_ADAPTER, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_TX_MAC, + POWER_SUPPLY_PROP_RX_CR, + POWER_SUPPLY_PROP_RX_CEP, + POWER_SUPPLY_PROP_BT_STATE, +#endif +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_PROP_PEN_MAC, +#endif +#endif POWER_SUPPLY_PROP_MIN_ICL, POWER_SUPPLY_PROP_MOISTURE_DETECTED, POWER_SUPPLY_PROP_BATT_PROFILE_VERSION, POWER_SUPPLY_PROP_BATT_FULL_CURRENT, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_BATTERY_CHARGING_LIMITED, + POWER_SUPPLY_PROP_SLOWLY_CHARGING, + POWER_SUPPLY_PROP_BQ_INPUT_SUSPEND, +#endif POWER_SUPPLY_PROP_RECHARGE_SOC, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_RECHARGE_VBAT, + POWER_SUPPLY_PROP_SYS_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_FFC_SYS_TERMINATION_CURRENT, + POWER_SUPPLY_PROP_VBATT_FULL_VOL, + POWER_SUPPLY_PROP_FFC_VBATT_FULL_VOL, + POWER_SUPPLY_PROP_KI_COEFF_CURRENT, + /* battery verify properties */ + POWER_SUPPLY_PROP_ROMID, + POWER_SUPPLY_PROP_DS_STATUS, + POWER_SUPPLY_PROP_PAGENUMBER, + POWER_SUPPLY_PROP_PAGEDATA, + POWER_SUPPLY_PROP_AUTHEN_RESULT, + POWER_SUPPLY_PROP_SESSION_SEED, + POWER_SUPPLY_PROP_S_SECRET, + POWER_SUPPLY_PROP_CHALLENGE, + POWER_SUPPLY_PROP_AUTH_ANON, + POWER_SUPPLY_PROP_AUTH_BDCONST, + POWER_SUPPLY_PROP_PAGE0_DATA, + POWER_SUPPLY_PROP_PAGE1_DATA, + POWER_SUPPLY_PROP_VERIFY_MODEL_NAME, + POWER_SUPPLY_PROP_MAXIM_BATT_CYCLE_COUNT, +#endif POWER_SUPPLY_PROP_HVDCP_OPTI_ALLOWED, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_FASTCHARGE_MODE, +#endif POWER_SUPPLY_PROP_SMB_EN_MODE, POWER_SUPPLY_PROP_SMB_EN_REASON, POWER_SUPPLY_PROP_ESR_ACTUAL, @@ -327,6 +435,11 @@ enum power_supply_property { POWER_SUPPLY_PROP_FORCE_RECHARGE, POWER_SUPPLY_PROP_FCC_STEPPER_ENABLE, POWER_SUPPLY_PROP_TOGGLE_STAT, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_PROP_TYPE_RECHECK, + POWER_SUPPLY_PROP_LIQUID_DETECTION, + POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED, +#endif POWER_SUPPLY_PROP_MAIN_FCC_MAX, POWER_SUPPLY_PROP_FG_RESET, POWER_SUPPLY_PROP_QC_OPTI_DISABLE, @@ -334,6 +447,9 @@ enum power_supply_property { POWER_SUPPLY_PROP_BATT_AGE_LEVEL, POWER_SUPPLY_PROP_VOLTAGE_VPH, POWER_SUPPLY_PROP_CHIP_VERSION, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_CHIP_OK, +#endif POWER_SUPPLY_PROP_THERM_ICL_LIMIT, POWER_SUPPLY_PROP_DC_RESET, POWER_SUPPLY_PROP_SCALE_MODE_EN, @@ -358,8 +474,49 @@ enum power_supply_property { POWER_SUPPLY_PROP_CP_TOGGLE_SWITCHER, POWER_SUPPLY_PROP_CP_IRQ_STATUS, POWER_SUPPLY_PROP_CP_ILIM, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_PROP_STEP_INDEX, + POWER_SUPPLY_PROP_TI_BATTERY_PRESENT, + POWER_SUPPLY_PROP_TI_VBUS_PRESENT, + POWER_SUPPLY_PROP_TI_BATTERY_VOLTAGE, + POWER_SUPPLY_PROP_TI_BATTERY_CURRENT, + POWER_SUPPLY_PROP_TI_BATTERY_TEMPERATURE, + POWER_SUPPLY_PROP_TI_BUS_VOLTAGE, + POWER_SUPPLY_PROP_TI_BUS_CURRENT, + POWER_SUPPLY_PROP_TI_BUS_TEMPERATURE, + POWER_SUPPLY_PROP_TI_DIE_TEMPERATURE, + POWER_SUPPLY_PROP_TI_ALARM_STATUS, + POWER_SUPPLY_PROP_TI_FAULT_STATUS, + POWER_SUPPLY_PROP_TI_REG_STATUS, + POWER_SUPPLY_PROP_TI_SET_BUS_PROTECTION_FOR_QC3, + POWER_SUPPLY_PROP_TI_BUS_ERROR_STATUS, + POWER_SUPPLY_PROP_TI_CHARGE_MODE, + POWER_SUPPLY_PROP_TI_BYPASS_MODE_ENABLED, +#endif POWER_SUPPLY_PROP_IRQ_STATUS, POWER_SUPPLY_PROP_PARALLEL_OUTPUT_MODE, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* DIV 2 properties */ + POWER_SUPPLY_PROP_DIV_2_MODE, + POWER_SUPPLY_PROP_REVERSE_CHG_MODE, + POWER_SUPPLY_PROP_REVERSE_CHG_STATE, +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_PROP_REVERSE_PEN_CHG_STATE, + POWER_SUPPLY_PROP_REVERSE_GPIO_STATE, +#endif + POWER_SUPPLY_PROP_RESET_DIV_2_MODE, +#ifdef CONFIG_MACH_XIAOMI_NABU + POWER_SUPPLY_PROP_AICL_ENABLE, + POWER_SUPPLY_PROP_OTG_STATE, + POWER_SUPPLY_PROP_REVERSE_CHG_HALL3, + POWER_SUPPLY_PROP_REVERSE_CHG_HALL4, + POWER_SUPPLY_PROP_REVERSE_PEN_SOC, + POWER_SUPPLY_PROP_REVERSE_VOUT, + POWER_SUPPLY_PROP_REVERSE_IOUT, +#endif + POWER_SUPPLY_PROP_RX_OP_BLE, + POWER_SUPPLY_PROP_OP_BLE, +#endif /* Local extensions of type int64_t */ POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT, /* Properties of type `const char *' */ @@ -395,6 +552,12 @@ enum power_supply_type { POWER_SUPPLY_TYPE_UFP, /* Type-C UFP */ POWER_SUPPLY_TYPE_DFP, /* Type-C DFP */ POWER_SUPPLY_TYPE_CHARGE_PUMP, /* Charge Pump */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + POWER_SUPPLY_TYPE_ZIMI_CAR_POWER, /* Zimi Car chargr */ +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + POWER_SUPPLY_TYPE_BATT_VERIFY, /* battery verify */ +#endif +#endif }; /* Indicates USB Type-C CC connection status */ @@ -436,6 +599,9 @@ union power_supply_propval { int intval; const char *strval; int64_t int64val; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + unsigned char arrayval[50]; +#endif }; struct device_node; From e6e0eaa57a153a6dd3a69520fbedaba5567a6219 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:32:27 +0200 Subject: [PATCH 087/226] drivers: regulator: Import Xiaomi changes Change-Id: Icbe3bfb4f35f9c7d0c7b04eeb2bbf0c53d31e4cd Signed-off-by: firebird11 --- drivers/regulator/qpnp-lcdb-regulator.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/regulator/qpnp-lcdb-regulator.c b/drivers/regulator/qpnp-lcdb-regulator.c index 396ed5415eea..a4c130279bd1 100644 --- a/drivers/regulator/qpnp-lcdb-regulator.c +++ b/drivers/regulator/qpnp-lcdb-regulator.c @@ -1283,6 +1283,19 @@ static int qpnp_lcdb_get_voltage(struct qpnp_lcdb *lcdb, return rc; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if ((val & 0x80) && (type == NCP))//NCP follow 0x71 LDO + { + offset = LCDB_LDO_OUTPUT_VOLTAGE_REG; + + rc = qpnp_lcdb_read(lcdb, lcdb->base + offset, &val, 1); + if (rc < 0) { + pr_err("Failed to read NCP volatge rc=%d\n", rc); + return rc; + } + } +#endif + val &= SET_OUTPUT_VOLTAGE_MASK; if (val < VOLTAGE_STEP_50MV_OFFSET) { *voltage_mv = VOLTAGE_MIN_STEP_100_MV + From c002beae8684e49df84076e43394ca49e1c72f4a Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:33:47 +0200 Subject: [PATCH 088/226] drivers: scsi: ufs: Import Xiaomi changes Change-Id: If39fe42fd22910e9ef55c0effa4a4a9b27cd6fed Signed-off-by: firebird11 --- drivers/scsi/ufs/ufs-qcom.c | 8 ++++++++ drivers/scsi/ufs/ufs_quirks.h | 3 +++ drivers/scsi/ufs/ufshcd.c | 25 +++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index 69ae57be7a5d..442694bd20d6 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -1268,9 +1268,17 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) if (enable) { if (host->hba->dev_info.quirks & UFS_DEVICE_QUIRK_WAIT_AFTER_REF_CLK_UNGATE) +#ifdef CONFIG_MACH_XIAOMI_SM8150 + usleep_range(960, 970); +#else usleep_range(50, 60); +#endif else +#ifdef CONFIG_MACH_XIAOMI_SM8150 + usleep_range(200, 210); +#else udelay(1); +#endif } host->is_dev_ref_clk_enabled = enable; diff --git a/drivers/scsi/ufs/ufs_quirks.h b/drivers/scsi/ufs/ufs_quirks.h index 07731d172fe6..98051585ef33 100644 --- a/drivers/scsi/ufs/ufs_quirks.h +++ b/drivers/scsi/ufs/ufs_quirks.h @@ -26,6 +26,9 @@ #define UFS_VENDOR_SAMSUNG 0x1CE #define UFS_VENDOR_SKHYNIX 0x1AD #define UFS_VENDOR_WDC 0x145 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define UFS_VENDOR_SANDISK 0x0145 +#endif /** * ufs_dev_fix - ufs device quirk info diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 994ee23ccd7f..7bfac837b605 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -213,6 +213,10 @@ static void ufshcd_update_uic_error_cnt(struct ufs_hba *hba, u32 reg, int type) /* UIC command timeout, unit: ms */ #define UIC_CMD_TIMEOUT 500 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define UIC_PWR_CTRL_TIMEOUT 3000 +#endif + /* NOP OUT retries waiting for NOP IN response */ #define NOP_OUT_RETRIES 10 /* Timeout after 30 msecs if NOP OUT hangs without response */ @@ -221,7 +225,11 @@ static void ufshcd_update_uic_error_cnt(struct ufs_hba *hba, u32 reg, int type) /* Query request retries */ #define QUERY_REQ_RETRIES 3 /* Query request timeout */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define QUERY_REQ_TIMEOUT 3000 /* 3.0 seconds */ +#else #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ +#endif /* Task management command timeout */ #define TM_CMD_TIMEOUT 100 /* msecs */ @@ -428,6 +436,10 @@ static struct ufs_dev_fix ufs_fixups[] = { UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME), UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_QUIRK_WAIT_AFTER_REF_CLK_UNGATE), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + UFS_FIX(UFS_VENDOR_SANDISK, UFS_ANY_MODEL, + UFS_DEVICE_QUIRK_WAIT_AFTER_REF_CLK_UNGATE), +#endif UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1", UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH), UFS_FIX(UFS_VENDOR_SKHYNIX, "hC8aL1", @@ -442,6 +454,10 @@ static struct ufs_dev_fix ufs_fixups[] = { UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH), UFS_FIX(UFS_VENDOR_SKHYNIX, "hC8HL1", UFS_DEVICE_QUIRK_HS_G1_TO_HS_G3_SWITCH), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + UFS_FIX(UFS_VENDOR_SANDISK, UFS_ANY_MODEL, + UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE), +#endif END_FIX }; @@ -5132,8 +5148,13 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) } more_wait: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!wait_for_completion_timeout(hba->uic_async_done, + msecs_to_jiffies(UIC_PWR_CTRL_TIMEOUT))) { +#else if (!wait_for_completion_timeout(hba->uic_async_done, msecs_to_jiffies(UIC_CMD_TIMEOUT))) { +#endif u32 intr_status = 0; s64 ts_since_last_intr; @@ -5644,7 +5665,11 @@ static int ufshcd_complete_dev_init(struct ufs_hba *hba) * Some vendor devices are taking longer time to complete its internal * initialization, so set fDeviceInit flag poll time to 5 secs */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + timeout = ktime_add_ms(ktime_get(), 8000); +#else timeout = ktime_add_ms(ktime_get(), 5000); +#endif /* poll for max. 5sec for fDeviceInit flag to clear */ while (1) { From 27a15c78bd11315170099f69bc5ce9dfef6dbd6e Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:36:43 +0200 Subject: [PATCH 089/226] drivers: sensors: Import Xiaomi changes Change-Id: I22bcac45b0f804931f9bf32a89e2fbd2e010f9c0 Signed-off-by: firebird11 --- drivers/sensors/sensors_ssc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/sensors/sensors_ssc.c b/drivers/sensors/sensors_ssc.c index dfdbd8e8df69..619b0bbdba16 100644 --- a/drivers/sensors/sensors_ssc.c +++ b/drivers/sensors/sensors_ssc.c @@ -123,6 +123,14 @@ static void slpi_load_fw(struct work_struct *slpi_ldr_work) fail: dev_err(&pdev->dev, "%s: SLPI image loading failed\n", __func__); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + priv->pil_h = subsystem_get_with_fwname("slpi", "slpi"); + if (IS_ERR(priv->pil_h)) { + dev_err(&pdev->dev, "%s: SLPI image re-loading failed\n", __func__); + } else { + dev_info(&pdev->dev, "%s: SLPI image is loaded\n", __func__); + } +#endif } static void slpi_loader_do(struct platform_device *pdev) From f86956688b35ed8c1083ac2d4287509764c6afc4 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:39:17 +0200 Subject: [PATCH 090/226] drivers: soc: qcom: Import Xiaomi changes Change-Id: Ic0c898b3ad242541751029d70958786d401ec054 Signed-off-by: firebird11 --- drivers/soc/qcom/fsa4480-i2c.c | 4 + drivers/soc/qcom/microdump_collector.c | 131 +++++++++++++++++++++++++ drivers/soc/qcom/socinfo.c | 87 ++++++++++++++++ drivers/soc/qcom/watchdog_v2.c | 4 + include/soc/qcom/socinfo.h | 37 +++++++ 5 files changed, 263 insertions(+) diff --git a/drivers/soc/qcom/fsa4480-i2c.c b/drivers/soc/qcom/fsa4480-i2c.c index cddb520ac4cf..1ff3d7c0d9fd 100644 --- a/drivers/soc/qcom/fsa4480-i2c.c +++ b/drivers/soc/qcom/fsa4480-i2c.c @@ -319,7 +319,11 @@ int fsa4480_switch_event(struct device_node *node, else switch_control = 0x7; fsa4480_usbc_update_settings(fsa_priv, switch_control, 0x9F); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + return 1; +#else break; +#endif case FSA_USBC_ORIENTATION_CC1: fsa4480_usbc_update_settings(fsa_priv, 0x18, 0xF8); return fsa4480_validate_display_port_settings(fsa_priv); diff --git a/drivers/soc/qcom/microdump_collector.c b/drivers/soc/qcom/microdump_collector.c index d55f3d177cdc..a4506ac2908d 100644 --- a/drivers/soc/qcom/microdump_collector.c +++ b/drivers/soc/qcom/microdump_collector.c @@ -8,7 +8,15 @@ #include #include #include +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include +#include +#include +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define MAX_SSR_REASON_LEN 130U +#endif #define SMEM_SSR_REASON_MSS0 421 #define SMEM_SSR_DATA_MSS0 611 #define SMEM_MODEM 1 @@ -19,6 +27,82 @@ * user space. */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define STR_NV_SIGNATURE_DESTROYED "CRITICAL_DATA_CHECK_FAILED" + +static struct kobject *checknv_kobj; +static struct kset *checknv_kset; + +static const struct sysfs_ops checknv_sysfs_ops = { +}; + +static void kobj_release(struct kobject *kobj) +{ + kfree(kobj); +} + +static struct kobj_type checknv_ktype = { + .sysfs_ops = &checknv_sysfs_ops, + .release = kobj_release, +}; + +static void checknv_kobj_clean(struct work_struct *work) +{ + kobject_uevent(checknv_kobj, KOBJ_REMOVE); + kobject_put(checknv_kobj); + kset_unregister(checknv_kset); +} + +static void checknv_kobj_create(struct work_struct *work) +{ + int ret; + + if (checknv_kset != NULL) { + pr_err("checknv_kset is not NULL, should clean up."); + kobject_uevent(checknv_kobj, KOBJ_REMOVE); + kobject_put(checknv_kobj); + } + + checknv_kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL); + if (!checknv_kobj) { + pr_err("kobject alloc failed."); + return; + } + + if (checknv_kset == NULL) { + checknv_kset = kset_create_and_add("checknv_errimei", NULL, NULL); + if (!checknv_kset) { + pr_err("kset creation failed."); + goto free_kobj; + } + } + + checknv_kobj->kset = checknv_kset; + + ret = kobject_init_and_add(checknv_kobj, &checknv_ktype, NULL, "%s", "errimei"); + if (ret) { + pr_err("%s: Error in creation kobject", __func__); + goto del_kobj; + } + + kobject_uevent(checknv_kobj, KOBJ_ADD); + return; + +del_kobj: + kobject_put(checknv_kobj); + kset_unregister(checknv_kset); + +free_kobj: + kfree(checknv_kobj); +} + +static DECLARE_DELAYED_WORK(create_kobj_work, checknv_kobj_create); +static DECLARE_WORK(clean_kobj_work, checknv_kobj_clean); + +static char last_modem_sfr_reason[MAX_SSR_REASON_LEN] = "none"; +static struct proc_dir_entry *last_modem_sfr_entry; +#endif + struct microdump_data { struct ramdump_device *microdump_dev; void *microdump_modem_notify_handler; @@ -65,6 +149,18 @@ static int microdump_modem_notifier_nb(struct notifier_block *nb, segment[1].v_address = crash_data; segment[1].size = size_data; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + strlcpy(last_modem_sfr_reason, crash_reason, MAX_SSR_REASON_LEN); + pr_err("modem subsystem failure reason: %s.\n", last_modem_sfr_reason); + + // If the NV protected file (critical_info) is destroyed, restart to recovery to inform user + if (strnstr(last_modem_sfr_reason, STR_NV_SIGNATURE_DESTROYED, strlen(last_modem_sfr_reason))) { + pr_err("errimei_dev: the NV has been destroyed, should restart to recovery\n"); + schedule_delayed_work(&create_kobj_work, msecs_to_jiffies(1*1000)); + goto out; + } +#endif + ret = do_ramdump(drv->microdump_dev, segment, 2); if (ret) pr_info("%s: do_ramdump() failed\n", __func__); @@ -99,6 +195,27 @@ static void microdump_modem_ssr_unregister_notifier(struct microdump_data *drv) drv->microdump_modem_notify_handler = NULL; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int last_modem_sfr_proc_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%s\n", last_modem_sfr_reason); + return 0; +} + +static int last_modem_sfr_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, last_modem_sfr_proc_show, NULL); +} + +static const struct file_operations last_modem_sfr_file_ops = { + .owner = THIS_MODULE, + .open = last_modem_sfr_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif + /* * microdump_init() - Registers kernel module for microdump collector * @@ -111,6 +228,13 @@ static int __init microdump_init(void) { int ret = -ENOMEM; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + last_modem_sfr_entry = proc_create("last_mcrash", S_IFREG | S_IRUGO, NULL, &last_modem_sfr_file_ops); + if (!last_modem_sfr_entry) { + printk(KERN_ERR "pil: cannot create proc entry last_mcrash\n"); + } +#endif + drv = kzalloc(sizeof(struct microdump_data), GFP_KERNEL); if (!drv) goto out; @@ -140,6 +264,13 @@ static int __init microdump_init(void) static void __exit microdump_exit(void) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + schedule_work(&clean_kobj_work); + if (last_modem_sfr_entry) { + remove_proc_entry("last_mcrash", NULL); + last_modem_sfr_entry = NULL; + } +#endif microdump_modem_ssr_unregister_notifier(drv); destroy_ramdump_device(drv->microdump_dev); kfree(drv); diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 9e749e559937..69217e749b9d 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -71,6 +71,14 @@ enum { HW_PLATFORM_HDK = 31, HW_PLATFORM_IOT = 32, HW_PLATFORM_IDP = 34, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + HW_PLATFORM_F1 = 37, + HW_PLATFORM_E5G = 39, + HW_PLATFORM_F11 = 40, + HW_PLATFORM_F1X = 43, + HW_PLATFORM_J20S = 47, + HW_PLATFORM_K82 = 48, +#endif HW_PLATFORM_INVALID }; @@ -96,6 +104,15 @@ const char *hw_platform[] = { [HW_PLATFORM_HDK] = "HDK", [HW_PLATFORM_IOT] = "IOT", [HW_PLATFORM_IDP] = "IDP" +#ifdef CONFIG_MACH_XIAOMI_SM8150 + , + [HW_PLATFORM_F1] = "CEPHEUS", + [HW_PLATFORM_E5G] = "ANDROMEDA", + [HW_PLATFORM_F11] = "RAPHAEL", + [HW_PLATFORM_F1X] = "CRUX", + [HW_PLATFORM_J20S] = "VAYU", + [HW_PLATFORM_K82] = "NABU", +#endif }; enum { @@ -1815,6 +1832,76 @@ static void socinfo_select_format(void) } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +const char *product_name_get(void) +{ + char *product_name = NULL; + size_t size; + uint32_t hw_type; + + hw_type = socinfo_get_platform_type(); + + product_name = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_ID_VENDOR1, &size); + if (IS_ERR_OR_NULL(product_name)) { + pr_warn("Can't find SMEM_ID_VENDOR1; falling back on dummy values.\n"); + return hw_platform[hw_type]; + } + + return product_name; +} + +EXPORT_SYMBOL(product_name_get); + +uint32_t get_hw_country_version(void) +{ + uint32_t version = socinfo_get_platform_version(); + return (version & HW_COUNTRY_VERSION_MASK) >> HW_COUNTRY_VERSION_SHIFT; +} + +EXPORT_SYMBOL(get_hw_country_version); + +uint32_t get_hw_version_platform(void) +{ + uint32_t hw_type = socinfo_get_platform_type(); + if (hw_type == HW_PLATFORM_F1) + return HARDWARE_PLATFORM_CEPHEUS; + else if (hw_type == HW_PLATFORM_E5G) + return HARDWARE_PLATFORM_ANDROMEDA; + else if (hw_type == HW_PLATFORM_F11) + return HARDWARE_PLATFORM_RAPHAEL; + else if (hw_type == HW_PLATFORM_F1X) + return HARDWARE_PLATFORM_CRUX; + else if (hw_type == HW_PLATFORM_J20S) + return HARDWARE_PLATFORM_VAYU; + else if (hw_type == HW_PLATFORM_K82) + return HARDWARE_PLATFORM_NABU; + else + return HARDWARE_PLATFORM_UNKNOWN; +} +EXPORT_SYMBOL(get_hw_version_platform); + +uint32_t get_hw_version_major(void) +{ + uint32_t version = socinfo_get_platform_version(); + return (version & HW_MAJOR_VERSION_MASK) >> HW_MAJOR_VERSION_SHIFT; +} +EXPORT_SYMBOL(get_hw_version_major); + +uint32_t get_hw_version_minor(void) +{ + uint32_t version = socinfo_get_platform_version(); + return (version & HW_MINOR_VERSION_MASK) >> HW_MINOR_VERSION_SHIFT; +} +EXPORT_SYMBOL(get_hw_version_minor); + +uint32_t get_hw_version_build(void) +{ + uint32_t version = socinfo_get_platform_version(); + return (version & HW_BUILD_VERSION_MASK) >> HW_BUILD_VERSION_SHIFT; +} +EXPORT_SYMBOL(get_hw_version_build); +#endif + int __init socinfo_init(void) { static bool socinfo_init_done; diff --git a/drivers/soc/qcom/watchdog_v2.c b/drivers/soc/qcom/watchdog_v2.c index e4eaa8b8e77e..4518d1e1ab5f 100644 --- a/drivers/soc/qcom/watchdog_v2.c +++ b/drivers/soc/qcom/watchdog_v2.c @@ -746,7 +746,11 @@ static void init_watchdog_data(struct msm_watchdog_data *wdog_dd) configure_bark_dump(wdog_dd); timeout = (wdog_dd->bark_time * WDT_HZ)/1000; __raw_writel(timeout, wdog_dd->base + WDT0_BARK_TIME); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + __raw_writel(timeout + 10*WDT_HZ, wdog_dd->base + WDT0_BITE_TIME); +#else __raw_writel(timeout + 3*WDT_HZ, wdog_dd->base + WDT0_BITE_TIME); +#endif wdog_dd->panic_blk.notifier_call = panic_wdog_handler; atomic_notifier_chain_register(&panic_notifier_list, diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index b9e3927081d3..ad076636242c 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -178,6 +178,9 @@ #define SMEM_IMAGE_VERSION_TABLE 469 #define SMEM_HW_SW_BUILD_ID 137 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define SMEM_ID_VENDOR1 135 +#endif enum msm_cpu { MSM_CPU_UNKNOWN = 0, MSM_CPU_8960, @@ -246,6 +249,32 @@ enum pmic_model { PMIC_MODEL_UNKNOWN = 0xFFFFFFFF }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define HARDWARE_PLATFORM_UNKNOWN 0 +#define HARDWARE_PLATFORM_CEPHEUS 1 +#define HARDWARE_PLATFORM_ANDROMEDA 3 +#define HARDWARE_PLATFORM_RAPHAEL 4 +#define HARDWARE_PLATFORM_VAYU 6 +#define HARDWARE_PLATFORM_CRUX 7 +#define HARDWARE_PLATFORM_NABU 8 + +#define HW_MAJOR_VERSION_SHIFT 16 +#define HW_MAJOR_VERSION_MASK 0xFFFF0000 +#define HW_MINOR_VERSION_SHIFT 0 +#define HW_MINOR_VERSION_MASK 0x0000FFFF +#define HW_COUNTRY_VERSION_MASK 0xFFF00000 +#define HW_COUNTRY_VERSION_SHIFT 20 +#define HW_BUILD_VERSION_MASK 0x000F0000 +#define HW_BUILD_VERSION_SHIFT 16 + +typedef enum { + CountryCN = 0, + CountryGlobal = 1, + CountryIndia = 2, + INVALID, +} CountryType; +#endif + enum msm_cpu socinfo_get_msm_cpu(void); uint32_t socinfo_get_id(void); uint32_t socinfo_get_version(void); @@ -258,6 +287,14 @@ uint32_t socinfo_get_platform_version(void); uint32_t socinfo_get_serial_number(void); enum pmic_model socinfo_get_pmic_model(void); uint32_t socinfo_get_pmic_die_revision(void); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +uint32_t get_hw_version_platform(void); +uint32_t get_hw_country_version(void); +uint32_t get_hw_version_major(void); +uint32_t get_hw_version_minor(void); +uint32_t get_hw_version_build(void); +const char *product_name_get(void); +#endif int __init socinfo_init(void) __must_check; #endif From 11b59db7ce5b417e6fd5d66fcb9c9fd18cfcaf7b Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:39:49 +0200 Subject: [PATCH 091/226] drivers: spi: Import Xiaomi changes Change-Id: Ic55a5b60361e6b9b5e4dd6d3b0adf4bf1780aeeb Signed-off-by: firebird11 --- drivers/spi/spi-geni-qcom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 25ac91e53fbd..4f470d580303 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -29,7 +29,11 @@ #include #define SPI_NUM_CHIPSELECT (4) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define SPI_XFER_TIMEOUT_MS (1500) +#else #define SPI_XFER_TIMEOUT_MS (250) +#endif #define SPI_AUTO_SUSPEND_DELAY (250) /* SPI SE specific registers */ #define SE_SPI_CPHA (0x224) From 9ed94fb2ec71c69780136ed9cc71cf51d78d5784 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:43:31 +0200 Subject: [PATCH 092/226] drivers: thermal: Import Xiaomi changes Change-Id: I990d079bb5611fa83cdeb467a11f14e72a4cd80f Signed-off-by: firebird11 --- drivers/thermal/cpu_cooling.c | 56 ++++++++ drivers/thermal/thermal_core.c | 229 +++++++++++++++++++++++++++++++++ include/linux/cpu_cooling.h | 4 + 3 files changed, 289 insertions(+) diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c index 786a9e2c4e4d..b31416a556c8 100644 --- a/drivers/thermal/cpu_cooling.c +++ b/drivers/thermal/cpu_cooling.c @@ -300,7 +300,11 @@ static int cpufreq_thermal_notifier(struct notifier_block *nb, unsigned long clipped_freq = ULONG_MAX, floor_freq = 0; struct cpufreq_cooling_device *cpufreq_cdev; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (event != CPUFREQ_THERMAL) +#else if (event != CPUFREQ_INCOMPATIBLE) +#endif return NOTIFY_DONE; mutex_lock(&cooling_list_lock); @@ -331,13 +335,45 @@ static int cpufreq_thermal_notifier(struct notifier_block *nb, * Similarly, if policy minimum set by the user is less than * the floor_frequency, then adjust the policy->min. */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cpufreq_verify_within_limits(policy, floor_freq, clipped_freq); +#else if (policy->max > clipped_freq || policy->min < floor_freq) cpufreq_verify_within_limits(policy, floor_freq, clipped_freq); +#endif mutex_unlock(&cooling_list_lock); return NOTIFY_OK; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +void cpu_limits_set_level(unsigned int cpu, unsigned int max_freq) +{ + struct cpufreq_cooling_device *cpufreq_cdev; + struct thermal_cooling_device *cdev; + unsigned int cdev_cpu; + unsigned int level; + + list_for_each_entry(cpufreq_cdev, &cpufreq_cdev_list, node) { + sscanf(cpufreq_cdev->cdev->type, "thermal-cpufreq-%d", &cdev_cpu); + if (cdev_cpu == cpu) { + for (level = 0; level < cpufreq_cdev->max_level; level++) { + int target_freq = cpufreq_cdev->freq_table[level].frequency; + if (max_freq >= target_freq) { + cdev = cpufreq_cdev->cdev; + if (cdev) + cdev->ops->set_cur_state(cdev, level); + + break; + } + } + + break; + } + } +} +#endif + /** * update_freq_table() - Update the freq table with power numbers * @cpufreq_cdev: the cpufreq cooling device in which to update the table @@ -674,7 +710,11 @@ static int cpufreq_set_cur_state(struct thermal_cooling_device *cdev, /* Request state should be less than max_level */ if (WARN_ON(state > cpufreq_cdev->max_level)) +#ifdef CONFIG_MACH_XIAOMI_SM8150 + state = cpufreq_cdev->max_level; +#else return -EINVAL; +#endif /* Check if the old cooling action is same as new cooling action */ if (cpufreq_cdev->cpufreq_state == state) @@ -720,6 +760,11 @@ static int cpufreq_set_cur_state(struct thermal_cooling_device *cdev, cpufreq_cdev->cpufreq_state = state; cpufreq_cdev->clipped_freq = clip_freq; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + get_online_cpus(); + cpufreq_update_policy(cpu); + put_online_cpus(); +#else /* Check if the device has a platform mitigation function that * can handle the CPU freq mitigation, if not, notify cpufreq * framework. @@ -731,6 +776,7 @@ static int cpufreq_set_cur_state(struct thermal_cooling_device *cdev, } else { cpufreq_update_policy(cpu); } +#endif return 0; } @@ -1087,7 +1133,11 @@ __cpufreq_cooling_register(struct device_node *np, list_add(&cpufreq_cdev->node, &cpufreq_cdev_list); mutex_unlock(&cooling_list_lock); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (first) +#else if (first && !cpufreq_cdev->plat_ops) +#endif cpufreq_register_notifier(&thermal_cpufreq_notifier_block, CPUFREQ_POLICY_NOTIFIER); if (!cpuhp_registered) { @@ -1280,10 +1330,16 @@ void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev) if (last) { unregister_pm_notifier(&cpufreq_cooling_pm_nb); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + cpufreq_unregister_notifier( + &thermal_cpufreq_notifier_block, + CPUFREQ_POLICY_NOTIFIER); +#else if (!cpufreq_cdev->plat_ops) cpufreq_unregister_notifier( &thermal_cpufreq_notifier_block, CPUFREQ_POLICY_NOTIFIER); +#endif } thermal_cooling_device_unregister(cpufreq_cdev->cdev); diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index 6df9a1c24217..9d769e1c4e39 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -25,6 +25,13 @@ #include #include #include +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include + +#ifdef CONFIG_DRM +#include +#endif +#endif #define CREATE_TRACE_POINTS #include @@ -38,6 +45,10 @@ MODULE_LICENSE("GPL v2"); #define THERMAL_MAX_ACTIVE 16 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define CPU_LIMITS_PARAM_NUM 2 +#endif + static DEFINE_IDA(thermal_tz_ida); static DEFINE_IDA(thermal_cdev_ida); @@ -56,6 +67,21 @@ static struct thermal_governor *def_governor; static struct workqueue_struct *thermal_passive_wq; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#ifdef CONFIG_DRM +struct screen_monitor { + struct notifier_block thermal_notifier; + int screen_state; /* 1: on; 0:off */ +}; + +struct screen_monitor sm; +#endif + +static atomic_t switch_mode = ATOMIC_INIT(-1); +static atomic_t temp_state = ATOMIC_INIT(0); +static char boost_buf[128]; +#endif + /* * Governor section: set of functions to handle thermal governors * @@ -944,6 +970,10 @@ static struct class thermal_class = { .dev_release = thermal_release, }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static struct device thermal_message_dev; +#endif + static inline void print_bind_err_msg(struct thermal_zone_device *tz, struct thermal_cooling_device *cdev, int ret) @@ -1624,6 +1654,185 @@ static struct notifier_block thermal_pm_nb = { .notifier_call = thermal_pm_notify, }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#ifdef CONFIG_DRM +static ssize_t +thermal_screen_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", sm.screen_state); +} + +static DEVICE_ATTR(screen_state, 0644, + thermal_screen_state_show, NULL); +#endif + +static ssize_t +thermal_sconfig_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", atomic_read(&switch_mode)); +} + +static ssize_t +thermal_sconfig_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t len) +{ + int val = -1; + + val = simple_strtol(buf, NULL, 10); + + atomic_set(&switch_mode, val); + + return len; +} + +static DEVICE_ATTR(sconfig, 0664, + thermal_sconfig_show, thermal_sconfig_store); + +static ssize_t +thermal_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, boost_buf); +} + +static ssize_t +thermal_boost_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t len) +{ + int ret; + ret = snprintf(boost_buf, PAGE_SIZE, buf); + return len; +} + +static DEVICE_ATTR(boost, 0644, + thermal_boost_show, thermal_boost_store); + +static ssize_t +thermal_temp_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", atomic_read(&temp_state)); +} + +static ssize_t +thermal_temp_state_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t len) +{ + int val = -1; + + val = simple_strtol(buf, NULL, 10); + + atomic_set(&temp_state, val); + + return len; +} + +static DEVICE_ATTR(temp_state, 0664, + thermal_temp_state_show, thermal_temp_state_store); + +static ssize_t +cpu_limits_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return 0; +} + +static ssize_t +cpu_limits_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t len) +{ + unsigned int cpu; + unsigned int max; + + if (sscanf(buf, "cpu%u %u", &cpu, &max) != CPU_LIMITS_PARAM_NUM) { + pr_err("input param error, can not prase param\n"); + return -EINVAL; + } + + cpu_limits_set_level(cpu, max); + + return len; +} + +static DEVICE_ATTR(cpu_limits, 0664, + cpu_limits_show, cpu_limits_store); + +static int create_thermal_message_node(void) +{ + int ret = 0; + + thermal_message_dev.class = &thermal_class; + + dev_set_name(&thermal_message_dev, "thermal_message"); + ret = device_register(&thermal_message_dev); + if (!ret) { +#ifdef CONFIG_DRM + ret = sysfs_create_file(&thermal_message_dev.kobj, &dev_attr_screen_state.attr); + if (ret < 0) + pr_warn("Thermal: create batt message node failed\n"); +#endif + ret = sysfs_create_file(&thermal_message_dev.kobj, &dev_attr_sconfig.attr); + if (ret < 0) + pr_warn("Thermal: create sconfig node failed\n"); + + ret = sysfs_create_file(&thermal_message_dev.kobj, &dev_attr_boost.attr); + if (ret < 0) + pr_warn("Thermal: create boost node failed\n"); + + ret = sysfs_create_file(&thermal_message_dev.kobj, &dev_attr_temp_state.attr); + if (ret < 0) + pr_warn("Thermal: create temp state node failed\n"); + + ret = sysfs_create_file(&thermal_message_dev.kobj, &dev_attr_cpu_limits.attr); + if (ret < 0) + pr_warn("Thermal: create cpu limits node failed\n"); + } + + return ret; +} + +static void destroy_thermal_message_node(void) +{ + sysfs_remove_file(&thermal_message_dev.kobj, &dev_attr_cpu_limits.attr); + sysfs_remove_file(&thermal_message_dev.kobj, &dev_attr_temp_state.attr); + sysfs_remove_file(&thermal_message_dev.kobj, &dev_attr_boost.attr); + sysfs_remove_file(&thermal_message_dev.kobj, &dev_attr_sconfig.attr); +#ifdef CONFIG_DRM + sysfs_remove_file(&thermal_message_dev.kobj, &dev_attr_screen_state.attr); +#endif + device_unregister(&thermal_message_dev); +} + +#ifdef CONFIG_DRM +static int screen_state_for_thermal_callback(struct notifier_block *nb, unsigned long val, void *data) +{ + struct msm_drm_notifier *evdata = data; + unsigned int blank; + + if (val != MSM_DRM_EVENT_BLANK || !evdata || !evdata->data) + return 0; + + blank = *(int *)(evdata->data); + switch (blank) { + case MSM_DRM_BLANK_POWERDOWN: + sm.screen_state = 0; + break; + case MSM_DRM_BLANK_UNBLANK: + sm.screen_state = 1; + break; + default: + break; + } + + sysfs_notify(&thermal_message_dev.kobj, NULL, "screen_state"); + + return NOTIFY_OK; +} +#endif +#endif + static int __init thermal_init(void) { int result; @@ -1655,6 +1864,20 @@ static int __init thermal_init(void) pr_warn("Thermal: Can not register suspend notifier, return %d\n", result); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + result = create_thermal_message_node(); + if (result) + pr_warn("Thermal: create thermal message node failed, return %d\n", + result); + +#ifdef CONFIG_DRM + sm.thermal_notifier.notifier_call = screen_state_for_thermal_callback; + if (msm_drm_register_client(&sm.thermal_notifier) < 0) { + pr_warn("Thermal: register screen state callback failed\n"); + } +#endif +#endif + return 0; exit_zone_parse: @@ -1674,6 +1897,12 @@ static int __init thermal_init(void) static void thermal_exit(void) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#ifdef CONFIG_DRM + msm_drm_unregister_client(&sm.thermal_notifier); +#endif + destroy_thermal_message_node(); +#endif unregister_pm_notifier(&thermal_pm_nb); of_thermal_destroy_zones(); destroy_workqueue(thermal_passive_wq); diff --git a/include/linux/cpu_cooling.h b/include/linux/cpu_cooling.h index f85fa59e6009..8ed9c87e81b7 100644 --- a/include/linux/cpu_cooling.h +++ b/include/linux/cpu_cooling.h @@ -54,6 +54,10 @@ struct thermal_cooling_device * cpufreq_platform_cooling_register(const struct cpumask *clip_cpus, struct cpu_cooling_ops *ops); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +void cpu_limits_set_level(unsigned int cpu, unsigned int max_freq); +#endif + /** * of_cpufreq_cooling_register - create cpufreq cooling device based on DT. * @np: a valid struct device_node to the cooling device device tree node. From b640c4a9e55bacd42428cd01925601e20466c9bd Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:44:13 +0200 Subject: [PATCH 093/226] drivers: Import Trusty TEE driver Change-Id: I48972b00e02dccc1382dfa329103417141410b35 Signed-off-by: firebird11 --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/trusty/Kconfig | 68 + drivers/trusty/Makefile | 17 + drivers/trusty/trusty-fiq-arm.c | 42 + drivers/trusty/trusty-fiq-arm64-glue.S | 60 + drivers/trusty/trusty-fiq-arm64.c | 173 ++ drivers/trusty/trusty-fiq.c | 88 + drivers/trusty/trusty-fiq.h | 17 + drivers/trusty/trusty-hee-irqs.c | 100 + drivers/trusty/trusty-ipc.c | 2438 ++++++++++++++++++++++++ drivers/trusty/trusty-irq.c | 598 ++++++ drivers/trusty/trusty-link-shbuf.c | 691 +++++++ drivers/trusty/trusty-link-shbuf.h | 58 + drivers/trusty/trusty-log.c | 275 +++ drivers/trusty/trusty-log.h | 17 + drivers/trusty/trusty-mem.c | 158 ++ drivers/trusty/trusty-shm.c | 209 ++ drivers/trusty/trusty-virq.c | 242 +++ drivers/trusty/trusty-virq.h | 55 + drivers/trusty/trusty-virtio.c | 761 ++++++++ drivers/trusty/trusty.c | 662 +++++++ include/linux/trusty/hvcall.h | 130 ++ include/linux/trusty/sm_err.h | 49 + include/linux/trusty/smcall.h | 136 ++ include/linux/trusty/trusty.h | 91 + include/linux/trusty/trusty_ipc.h | 89 + include/linux/trusty/trusty_shm.h | 26 + include/uapi/linux/virtio_ids.h | 1 + 29 files changed, 7254 insertions(+) create mode 100644 drivers/trusty/Kconfig create mode 100644 drivers/trusty/Makefile create mode 100644 drivers/trusty/trusty-fiq-arm.c create mode 100644 drivers/trusty/trusty-fiq-arm64-glue.S create mode 100644 drivers/trusty/trusty-fiq-arm64.c create mode 100644 drivers/trusty/trusty-fiq.c create mode 100644 drivers/trusty/trusty-fiq.h create mode 100644 drivers/trusty/trusty-hee-irqs.c create mode 100644 drivers/trusty/trusty-ipc.c create mode 100644 drivers/trusty/trusty-irq.c create mode 100644 drivers/trusty/trusty-link-shbuf.c create mode 100644 drivers/trusty/trusty-link-shbuf.h create mode 100644 drivers/trusty/trusty-log.c create mode 100644 drivers/trusty/trusty-log.h create mode 100644 drivers/trusty/trusty-mem.c create mode 100644 drivers/trusty/trusty-shm.c create mode 100644 drivers/trusty/trusty-virq.c create mode 100644 drivers/trusty/trusty-virq.h create mode 100644 drivers/trusty/trusty-virtio.c create mode 100644 drivers/trusty/trusty.c create mode 100644 include/linux/trusty/hvcall.h create mode 100644 include/linux/trusty/sm_err.h create mode 100644 include/linux/trusty/smcall.h create mode 100644 include/linux/trusty/trusty.h create mode 100644 include/linux/trusty/trusty_ipc.h create mode 100644 include/linux/trusty/trusty_shm.h diff --git a/drivers/Kconfig b/drivers/Kconfig index cfd0d22ebcca..673f6a1f6ac4 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -227,4 +227,6 @@ source "drivers/esoc/Kconfig" source "drivers/halls/Kconfig" +source "drivers/trusty/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 2f8e36eb37d5..ca8275dd8884 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -189,6 +189,7 @@ obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_SENSORS_SSC) += sensors/ obj-$(CONFIG_ESOC) += esoc/ obj-$(CONFIG_HALLS) += halls/ +obj-$(CONFIG_TRUSTY) += trusty/ # GNSS driver obj-$(CONFIG_GNSS_SIRF) += gnsssirf/ obj-$(CONFIG_GNSS) += gnss/ diff --git a/drivers/trusty/Kconfig b/drivers/trusty/Kconfig new file mode 100644 index 000000000000..32639a803d9f --- /dev/null +++ b/drivers/trusty/Kconfig @@ -0,0 +1,68 @@ +# +# Trusty +# + +menu "Trusty" + +config TRUSTY + tristate "Trusty" + default n + help + Trusty is a secure Operating System (OS) that provides a + Trusted Execution Environment (TEE) for Android. + Trusty is compatible with ARM and Intel processors. + Say N if unsure. + +config TRUSTY_VIRQ_SIMULATION + tristate "Trusty Virq Simulation" + default n + help + This module adds support for simulations of communications based + on virq with Trusty Services. + + It'll be called trusty-ipc, trusty-virtio. + Say N if unsure. + +config TRUSTY_FIQ + tristate + depends on TRUSTY + default n + +config TRUSTY_FIQ_ARM + tristate + depends on TRUSTY + depends on ARM + select FIQ_GLUE + select TRUSTY_FIQ + default n + +config TRUSTY_FIQ_ARM64 + tristate + depends on TRUSTY + depends on ARM64 + select FIQ_GLUE + select TRUSTY_FIQ + default n + +config TRUSTY_LOG + tristate + depends on TRUSTY + default y + +config TRUSTY_VIRTIO + tristate "Trusty virtio support" + depends on TRUSTY + select VIRTIO + default y + +config TRUSTY_VIRTIO_IPC + tristate "Trusty Virtio IPC driver" + depends on TRUSTY_VIRTIO + default y + help + This module adds support for communications with Trusty Services + + If you choose to build a module, it'll be called trusty-ipc. + Say N if unsure. + +endmenu diff --git a/drivers/trusty/Makefile b/drivers/trusty/Makefile new file mode 100644 index 000000000000..dd903e6fd525 --- /dev/null +++ b/drivers/trusty/Makefile @@ -0,0 +1,17 @@ +# +# Makefile for trusty components +# + +obj-$(CONFIG_TRUSTY) += trusty.o +obj-$(CONFIG_TRUSTY) += trusty-shm.o +obj-$(CONFIG_TRUSTY) += trusty-irq.o +obj-$(CONFIG_TRUSTY_FIQ) += trusty-fiq.o +obj-$(CONFIG_TRUSTY_FIQ_ARM) += trusty-fiq-arm.o +obj-$(CONFIG_TRUSTY_FIQ_ARM64) += trusty-fiq-arm64.o trusty-fiq-arm64-glue.o +obj-$(CONFIG_TRUSTY_LOG) += trusty-log.o +obj-$(CONFIG_TRUSTY) += trusty-mem.o +obj-$(CONFIG_TRUSTY_VIRTIO) += trusty-virtio.o +obj-$(CONFIG_TRUSTY_VIRTIO_IPC) += trusty-ipc.o +# OKL-HYP +obj-$(CONFIG_TRUSTY) += trusty-link-shbuf.o +obj-$(CONFIG_TRUSTY_VIRQ_SIMULATION) += trusty-hee-irqs.o diff --git a/drivers/trusty/trusty-fiq-arm.c b/drivers/trusty/trusty-fiq-arm.c new file mode 100644 index 000000000000..91ed5276e5f4 --- /dev/null +++ b/drivers/trusty/trusty-fiq-arm.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include "trusty-fiq.h" + +#define _STRINGIFY(x) #x +#define STRINGIFY(x) _STRINGIFY(x) + +static void __naked trusty_fiq_return(void) +{ + asm volatile(".arch_extension sec\n" + "mov r12, r0\n" + "ldr r0, =" STRINGIFY(SMC_FC_FIQ_EXIT) "\n" + "smc #0"); +} + +int trusty_fiq_arch_probe(struct platform_device *pdev) +{ + return fiq_glue_set_return_handler(trusty_fiq_return); +} + +void trusty_fiq_arch_remove(struct platform_device *pdev) +{ + fiq_glue_clear_return_handler(trusty_fiq_return); +} diff --git a/drivers/trusty/trusty-fiq-arm64-glue.S b/drivers/trusty/trusty-fiq-arm64-glue.S new file mode 100644 index 000000000000..b02fe617a545 --- /dev/null +++ b/drivers/trusty/trusty-fiq-arm64-glue.S @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +.macro push reg1,reg2,remregs:vararg + .ifnb \remregs + push \remregs + .endif + stp \reg1, \reg2, [sp, #-16]! +.endm + +.macro pop reg1,reg2,remregs:vararg + ldp \reg1, \reg2, [sp], #16 + .ifnb \remregs + pop \remregs + .endif +.endm + +ENTRY(trusty_fiq_glue_arm64) + sub sp, sp, #S_FRAME_SIZE - S_LR + push x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, \ + x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, \ + x26, x27, x28, x29 + ldr x0, =SMC_FC64_GET_FIQ_REGS + smc #0 + stp x0, x1, [sp, #S_PC] /* original pc, cpsr */ + tst x1, PSR_MODE_MASK + csel x2, x2, x3, eq /* sp el0, sp el1 */ + stp x30, x2, [sp, #S_LR] /* lr, original sp */ + mov x0, sp + mov x1, x3 + bl trusty_fiq_handler + pop x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, \ + x14, x15, x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, \ + x26, x27, x28, x29 + ldr x30, [sp], #S_FRAME_SIZE - S_LR /* load LR and restore SP */ + ldr x0, =SMC_FC_FIQ_EXIT + smc #0 + b . /* should not get here */ + +ENTRY(trusty_fiq_cpu_resume) + ldr x0, =SMC_FC_FIQ_RESUME + smc #0 + ret diff --git a/drivers/trusty/trusty-fiq-arm64.c b/drivers/trusty/trusty-fiq-arm64.c new file mode 100644 index 000000000000..bdd4c8e5d32d --- /dev/null +++ b/drivers/trusty/trusty-fiq-arm64.c @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "trusty-fiq.h" + +extern void trusty_fiq_glue_arm64(void); + +static struct device *trusty_dev; +static DEFINE_PER_CPU(void *, fiq_stack); +static struct fiq_glue_handler *fiq_handlers; +static DEFINE_MUTEX(fiq_glue_lock); + +void trusty_fiq_handler(struct pt_regs *regs, void *svc_sp) +{ + struct fiq_glue_handler *handler; + + for (handler = READ_ONCE(fiq_handlers); handler; + handler = READ_ONCE(handler->next)) { + /* Barrier paired with smp_wmb in fiq_glue_register_handler */ + smp_read_barrier_depends(); + handler->fiq(handler, regs, svc_sp); + } +} + +static void smp_nop_call(void *info) +{ + /* If this call is reached, the fiq handler is not currently running */ +} + +static void fiq_glue_clear_handler(void) +{ + int cpu; + int ret; + void *stack; + + for_each_possible_cpu(cpu) { + stack = per_cpu(fiq_stack, cpu); + if (!stack) + continue; + + ret = trusty_fast_call64(trusty_dev, SMC_FC64_SET_FIQ_HANDLER, + cpu, 0, 0); + if (ret) { + pr_err("%s: SMC_FC_SET_FIQ_HANDLER(%d, 0, 0) failed 0x%x, skip free stack\n", + __func__, cpu, ret); + continue; + } + + per_cpu(fiq_stack, cpu) = NULL; + smp_call_function_single(cpu, smp_nop_call, NULL, true); + free_pages((unsigned long)stack, THREAD_SIZE_ORDER); + } +} + +static int fiq_glue_set_handler(void) +{ + int ret; + int cpu; + void *stack; + unsigned long irqflags; + + for_each_possible_cpu(cpu) { + stack = (void *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); + if (WARN_ON(!stack)) { + ret = -ENOMEM; + goto err_alloc_fiq_stack; + } + per_cpu(fiq_stack, cpu) = stack; + stack += THREAD_START_SP; + + local_irq_save(irqflags); + ret = trusty_fast_call64(trusty_dev, SMC_FC64_SET_FIQ_HANDLER, + cpu, (uintptr_t)trusty_fiq_glue_arm64, + (uintptr_t)stack); + local_irq_restore(irqflags); + if (ret) { + pr_err("%s: SMC_FC_SET_FIQ_HANDLER(%d, %p, %p) failed 0x%x\n", + __func__, cpu, trusty_fiq_glue_arm64, stack, + ret); + ret = -EINVAL; + goto err_set_fiq_handler; + } + } + return 0; + +err_alloc_fiq_stack: +err_set_fiq_handler: + fiq_glue_clear_handler(); + return ret; +} + +int fiq_glue_register_handler(struct fiq_glue_handler *handler) +{ + int ret; + + if (!handler || !handler->fiq) { + ret = -EINVAL; + goto err_bad_arg; + } + + mutex_lock(&fiq_glue_lock); + + if (!trusty_dev) { + ret = -ENODEV; + goto err_no_trusty; + } + + handler->next = fiq_handlers; + /* + * Write barrier paired with smp_read_barrier_depends in + * trusty_fiq_handler. Make sure next pointer is updated before + * fiq_handlers so trusty_fiq_handler does not see an uninitialized + * value and terminate early or crash. + */ + smp_wmb(); + fiq_handlers = handler; + + smp_call_function(smp_nop_call, NULL, true); + + if (!handler->next) { + ret = fiq_glue_set_handler(); + if (ret) + goto err_set_fiq_handler; + } + + mutex_unlock(&fiq_glue_lock); + return 0; + +err_set_fiq_handler: + fiq_handlers = handler->next; +err_no_trusty: + mutex_unlock(&fiq_glue_lock); +err_bad_arg: + pr_err("%s: failed, %d\n", __func__, ret); + return ret; +} + +int trusty_fiq_arch_probe(struct platform_device *pdev) +{ + mutex_lock(&fiq_glue_lock); + trusty_dev = pdev->dev.parent; + mutex_unlock(&fiq_glue_lock); + + return 0; +} + +void trusty_fiq_arch_remove(struct platform_device *pdev) +{ + mutex_lock(&fiq_glue_lock); + fiq_glue_clear_handler(); + trusty_dev = NULL; + mutex_unlock(&fiq_glue_lock); +} diff --git a/drivers/trusty/trusty-fiq.c b/drivers/trusty/trusty-fiq.c new file mode 100644 index 000000000000..bb937bf33ce3 --- /dev/null +++ b/drivers/trusty/trusty-fiq.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#include "trusty-fiq.h" + +static int trusty_fiq_remove_child(struct device *dev, void *data) +{ + platform_device_unregister(to_platform_device(dev)); + return 0; +} + +static int trusty_fiq_probe(struct platform_device *pdev) +{ + int ret; + + ret = trusty_fiq_arch_probe(pdev); + if (ret) + goto err_set_fiq_return; + + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to add children: %d\n", ret); + goto err_add_children; + } + + return 0; + +err_add_children: + device_for_each_child(&pdev->dev, NULL, trusty_fiq_remove_child); + trusty_fiq_arch_remove(pdev); +err_set_fiq_return: + return ret; +} + +static int trusty_fiq_remove(struct platform_device *pdev) +{ + device_for_each_child(&pdev->dev, NULL, trusty_fiq_remove_child); + trusty_fiq_arch_remove(pdev); + return 0; +} + +static const struct of_device_id trusty_fiq_of_match[] = { + { + .compatible = "android,trusty-fiq-v1", + }, + {}, +}; + +static struct platform_driver trusty_fiq_driver = { + .probe = trusty_fiq_probe, + .remove = trusty_fiq_remove, + .driver = { + .name = "trusty-fiq", + .owner = THIS_MODULE, + .of_match_table = trusty_fiq_of_match, + }, +}; + +static int __init trusty_fiq_driver_init(void) +{ + return platform_driver_register(&trusty_fiq_driver); +} + +static void __exit trusty_fiq_driver_exit(void) +{ + platform_driver_unregister(&trusty_fiq_driver); +} + +subsys_initcall(trusty_fiq_driver_init); +module_exit(trusty_fiq_driver_exit); diff --git a/drivers/trusty/trusty-fiq.h b/drivers/trusty/trusty-fiq.h new file mode 100644 index 000000000000..ebc17e2351df --- /dev/null +++ b/drivers/trusty/trusty-fiq.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2014 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +int trusty_fiq_arch_probe(struct platform_device *pdev); +void trusty_fiq_arch_remove(struct platform_device *pdev); diff --git a/drivers/trusty/trusty-hee-irqs.c b/drivers/trusty/trusty-hee-irqs.c new file mode 100644 index 000000000000..057c8f7755fe --- /dev/null +++ b/drivers/trusty/trusty-hee-irqs.c @@ -0,0 +1,100 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* should not reach here */ +static irqreturn_t irq_handler(int irq, void *data) +{ + WARN_ON(true); + return IRQ_HANDLED; +} + +static int hee_irq_probe(struct platform_device *pdev) +{ + int ret; + u32 irq, cpu; + ulong hwirq; + void __iomem *gicd_base; + struct irq_desc *desc; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "platform_get_irq err %d\n", ret); + return -EINVAL; + } + + desc = irq_to_desc(irq); + if (!desc) { + dev_err(&pdev->dev, "irq_desc(%d) null\n", irq); + return -EINVAL; + } + hwirq = desc->irq_data.hwirq; + + ret = devm_request_irq(&pdev->dev, irq, irq_handler, + IRQF_TRIGGER_RISING, "hee_irq", NULL); + if (ret < 0) { + dev_err(&pdev->dev, "request_irq irq %d err %d\n", irq, ret); + return ret; + } + + gicd_base = ioremap_nocache(0x08000000, 1024 * 1024); + + for_each_possible_cpu(cpu) { + if (cpumask_test_cpu(cpu, cpu_online_mask)) + continue; + + /* Aff1/2/3 is 0 in Virt. :-) */ + gic_write_irouter(cpu, gicd_base + GICD_IROUTER + hwirq * 8); + break; + } + + iounmap(gicd_base); + + dev_dbg(&pdev->dev, "irq %d hwirq %lu configured.\n", irq, + desc->irq_data.hwirq); + + return 0; +} + +static const struct of_device_id hee_irq_of_match[] = { + { + .compatible = "nbl,hee-irq", + }, + {}, +}; + +static struct platform_driver hee_irq_driver = { + .probe = hee_irq_probe, + .driver = { + .name = "trusty-hee-irq", + .owner = THIS_MODULE, + .of_match_table = hee_irq_of_match, + }, +}; + +static int __init hee_irq_driver_init(void) +{ + return platform_driver_register(&hee_irq_driver); +} + +arch_initcall(hee_irq_driver_init); diff --git a/drivers/trusty/trusty-ipc.c b/drivers/trusty/trusty-ipc.c new file mode 100644 index 000000000000..32fd1b051366 --- /dev/null +++ b/drivers/trusty/trusty-ipc.c @@ -0,0 +1,2438 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * Copyright (C) 2015 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4, 10, 0) +#include +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) +#include +#endif +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "trusty-link-shbuf.h" + +#define MAX_DEVICES 4 + +#define REPLY_TIMEOUT 5000 +#define TXBUF_TIMEOUT 15000 + +#define MAX_SRV_NAME_LEN 256 +#define MAX_DEV_NAME_LEN 32 + +#define DEFAULT_MSG_BUF_SIZE PAGE_SIZE +#define DEFAULT_MSG_BUF_ALIGN PAGE_SIZE + +#define TIPC_CTRL_ADDR 53 +#define TIPC_ANY_ADDR 0xFFFFFFFF + +#define TIPC_MIN_LOCAL_ADDR 1024 +#define TIPC_MAX_LOCAL_ADDR 0x7FFFFFFF + +#define MAX_MEMREF_NUM 8 +#define MEMREF_ALIGN 8 +#define TIPC_MIN_MEMREF_ID 2048 +#define TIPC_MAX_MEMREF_ID 10000 +#define MAX_MREF_SIZE (2 * 1024 * 1024) + +#define TIPC_IOC_MAGIC 'r' +#define TIPC_IOC_CONNECT _IOW(TIPC_IOC_MAGIC, 0x80, char *) + +#define TIPC_MEMREF_PERM_RO (0x0U << 0) +#define TIPC_MEMREF_PERM_RW (0x1U << 0) + +struct tipc_shmem { + __u32 flags; + __u32 size[3]; + __u64 base[3]; +}; + +struct tipc_send_msg_req { + __u64 msgiov; + __u64 shmemv; + __u32 msgiov_cnt; + __u32 shmemv_cnt; +}; + +#define TIPC_IOC_SEND_MSG _IOW(TIPC_IOC_MAGIC, 0x81, struct tipc_send_msg_req) + +#if defined(CONFIG_COMPAT) +#define TIPC_IOC_CONNECT_COMPAT _IOW(TIPC_IOC_MAGIC, 0x80, compat_uptr_t) + +#endif + +struct tipc_virtio_dev; + +struct tipc_dev_config { + u32 msg_buf_max_size; + u32 msg_buf_alignment; + char dev_name[MAX_DEV_NAME_LEN]; +} __packed; + +struct tipc_msg_hdr { + u32 src; + u32 dst; + u32 reserved; + u16 len; + u16 flags; + u8 data[0]; +} __packed; + +struct tipc_msg_mref_hdr { + u32 id; + u32 flags; + u32 size; + u32 pg_inf_cnt; + struct ns_mem_page_info pg_inf[]; +} __packed; + +enum tipc_ctrl_msg_types { + TIPC_CTRL_MSGTYPE_GO_ONLINE = 1, + TIPC_CTRL_MSGTYPE_GO_OFFLINE, + TIPC_CTRL_MSGTYPE_CONN_REQ, + TIPC_CTRL_MSGTYPE_CONN_RSP, + TIPC_CTRL_MSGTYPE_DISC_REQ, + TIPC_CTRL_MSGTYPE_MREF_RELEASE_REQ, +}; + +struct tipc_ctrl_msg { + u32 type; + u32 body_len; + u8 body[0]; +} __packed; + +struct tipc_conn_req_body { + char name[MAX_SRV_NAME_LEN]; +} __packed; + +struct tipc_conn_rsp_body { + u32 target; + u32 status; + u32 remote; + u32 max_msg_size; + u32 max_msg_cnt; +} __packed; + +struct tipc_disc_req_body { + u32 target; +} __packed; + +struct tipc_mref_release_req_body { + u32 id; +} __packed; + +struct tipc_cdev_node { + struct cdev cdev; + struct device *dev; + unsigned int minor; +}; + +enum tipc_device_state { + VDS_OFFLINE = 0, + VDS_ONLINE, + VDS_DEAD, +}; + +struct tipc_virtio_dev { + struct kref refcount; + struct mutex lock; /* protects access to this device */ + struct virtio_device *vdev; + struct virtqueue *rxvq; + struct virtqueue *txvq; + uint msg_buf_cnt; + uint msg_buf_max_cnt; + size_t msg_buf_sz; + uint free_msg_buf_cnt; + struct list_head free_buf_list; + struct list_head stashed_buf_list; + wait_queue_head_t sendq; + struct idr addr_idr; + struct idr mref_idr; + struct mutex mref_lock; /* protects access to mref_idr */ + enum tipc_device_state state; + struct tipc_cdev_node cdev_node; + char cdev_name[MAX_DEV_NAME_LEN]; +}; + +enum tipc_chan_state { + TIPC_DISCONNECTED = 0, + TIPC_CONNECTING, + TIPC_CONNECTED, + TIPC_STALE, +}; + +struct tipc_chan { + struct mutex lock; /* protects channel state */ + struct kref refcount; + enum tipc_chan_state state; + struct tipc_virtio_dev *vds; + const struct tipc_chan_ops *ops; + void *ops_arg; + struct list_head mref_list; + wait_queue_head_t mrefq; + u32 remote; + u32 local; + u32 max_msg_size; + u32 max_msg_cnt; + char srv_name[MAX_SRV_NAME_LEN]; +}; + +struct tipc_memref { + struct tipc_chan *chan; + struct list_head node; + unsigned int pg_num; + unsigned int pg_pinned; + struct page *pages[]; +}; + +static struct class *tipc_class; +static unsigned int tipc_major; + +struct virtio_device *default_vdev; + +static DEFINE_IDR(tipc_devices); +static DEFINE_MUTEX(tipc_devices_lock); + +static int _tipc_send_msg(struct tipc_chan *chan, struct iov_iter *msg_iter, + struct tipc_shmem *shmv, uint shmv_cnt, bool user, + long timeout, bool intr); + +static int _match_any(int id, void *p, void *data) +{ + return id; +} + +static int _match_data(int id, void *p, void *data) +{ + return (p == data); +} + +static void *_alloc_shareable_mem(size_t sz, phys_addr_t *ppa, gfp_t gfp) +{ + return trusty_shm_alloc(sz, gfp); +} + +static void _free_shareable_mem(size_t sz, void *va, phys_addr_t pa) +{ + trusty_shm_free(va, sz); +} + +static struct tipc_msg_buf *_alloc_msg_buf(size_t sz) +{ + struct tipc_msg_buf *mb; + + /* allocate tracking structure */ + mb = kzalloc(sizeof(struct tipc_msg_buf), GFP_KERNEL); + if (!mb) + return NULL; + + /* allocate buffer that can be shared with secure world */ + mb->buf_va = _alloc_shareable_mem(sz, &mb->buf_pa, GFP_KERNEL); + if (!mb->buf_va) + goto err_alloc; + + mb->buf_sz = sz; + + return mb; + +err_alloc: + kfree(mb); + return NULL; +} + +static void _free_msg_buf(struct tipc_msg_buf *mb) +{ + _free_shareable_mem(mb->buf_sz, mb->buf_va, mb->buf_pa); + kfree(mb); +} + +static void _free_msg_buf_list(struct list_head *list) +{ + struct tipc_msg_buf *mb = NULL; + + mb = list_first_entry_or_null(list, struct tipc_msg_buf, node); + while (mb) { + list_del(&mb->node); + _free_msg_buf(mb); + mb = list_first_entry_or_null(list, struct tipc_msg_buf, node); + } +} + +static inline void mb_reset(struct tipc_msg_buf *mb) +{ + mb->wpos = 0; + mb->rpos = 0; +} + +static inline void mb_reset_read(struct tipc_msg_buf *mb) +{ + mb->rpos = 0; +} + +static inline void mb_align_read(struct tipc_msg_buf *mb, uint align) +{ + (void)mb_get_data(mb, ALIGN(mb->rpos, align) - mb->rpos); +} + +static inline void mb_align_write(struct tipc_msg_buf *mb, uint align) +{ + size_t cb = ALIGN(mb->wpos, align) - mb->wpos; + + memset(mb_put_data(mb, cb), 0, cb); +} + +static void _free_vds(struct kref *kref) +{ + struct tipc_virtio_dev *vds = + container_of(kref, struct tipc_virtio_dev, refcount); + kfree(vds); +} + +static void _free_chan(struct kref *kref) +{ + struct tipc_chan *ch = container_of(kref, struct tipc_chan, refcount); + + if (ch->ops && ch->ops->handle_release) + ch->ops->handle_release(ch->ops_arg); + + kref_put(&ch->vds->refcount, _free_vds); + kfree(ch); +} + +static struct tipc_msg_buf *vds_alloc_msg_buf(struct tipc_virtio_dev *vds) +{ + return _alloc_msg_buf(vds->msg_buf_sz); +} + +static void vds_free_msg_buf(struct tipc_virtio_dev *vds, + struct tipc_msg_buf *mb) +{ + _free_msg_buf(mb); +} + +static bool _put_txbuf_locked(struct tipc_virtio_dev *vds, + struct tipc_msg_buf *mb) +{ + if (mb->buf_sz > vds->msg_buf_sz) { + _free_msg_buf(mb); + + if (list_empty(&vds->stashed_buf_list)) { + vds->msg_buf_cnt--; + return true; + } + + /* take buf out of stashed list and put it on free list */ + mb = list_first_entry(&vds->stashed_buf_list, + struct tipc_msg_buf, node); + list_del(&mb->node); + } + list_add_tail(&mb->node, &vds->free_buf_list); + return vds->free_msg_buf_cnt++ == 0; +} + +static struct tipc_msg_buf *_get_txbuf_locked(struct tipc_virtio_dev *vds, + size_t sz) +{ + struct tipc_msg_buf *mb; + + if (vds->state != VDS_ONLINE) + return ERR_PTR(-ENODEV); + + if (sz < vds->msg_buf_sz) + sz = vds->msg_buf_sz; + + if (vds->free_msg_buf_cnt) { + /* peek head of free list */ + mb = list_first_entry(&vds->free_buf_list, struct tipc_msg_buf, + node); + + if (sz > vds->msg_buf_sz) { + struct tipc_msg_buf *newmb; + + /* allocate new one */ + newmb = _alloc_msg_buf(sz); + if (!newmb) + return ERR_PTR(-ENOMEM); + + /* remove from free list and put it on shashed list */ + list_del(&mb->node); + list_add_tail(&mb->node, &vds->stashed_buf_list); + + /* return a new one to caller */ + mb = newmb; + } else { + /* take it out of free list */ + list_del(&mb->node); + } + vds->free_msg_buf_cnt--; + } else { + if (vds->msg_buf_cnt >= vds->msg_buf_max_cnt) + return ERR_PTR(-EAGAIN); + + /* try to allocate it */ + mb = _alloc_msg_buf(sz); + if (!mb) + return ERR_PTR(-ENOMEM); + + vds->msg_buf_cnt++; + } + return mb; +} + +static struct tipc_msg_buf *_vds_get_txbuf(struct tipc_virtio_dev *vds, + size_t sz) +{ + struct tipc_msg_buf *mb; + + mutex_lock(&vds->lock); + mb = _get_txbuf_locked(vds, sz); + mutex_unlock(&vds->lock); + + return mb; +} + +static void vds_put_txbuf_locked(struct tipc_virtio_dev *vds, + struct tipc_msg_buf *mb) +{ + if (_put_txbuf_locked(vds, mb)) + wake_up(&vds->sendq); +} + +static void vds_put_txbuf(struct tipc_virtio_dev *vds, struct tipc_msg_buf *mb) +{ + mutex_lock(&vds->lock); + vds_put_txbuf_locked(vds, mb); + mutex_unlock(&vds->lock); +} + +static struct tipc_msg_buf *vds_get_txbuf(struct tipc_virtio_dev *vds, + size_t sz, long timeout, bool intr) +{ + struct tipc_msg_buf *mb; + unsigned int mode = intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; + + mb = _vds_get_txbuf(vds, sz); + + if ((PTR_ERR(mb) == -EAGAIN) && timeout) { + DEFINE_WAIT_FUNC(wait, woken_wake_function); + + timeout = msecs_to_jiffies(timeout); + add_wait_queue(&vds->sendq, &wait); + for (;;) { + timeout = wait_woken(&wait, mode, timeout); + if (!timeout) { + mb = ERR_PTR(-ETIMEDOUT); + break; + } + + if (intr) { + if (signal_pending(current)) { + mb = ERR_PTR(-ERESTARTSYS); + break; + } + } + + mb = _vds_get_txbuf(vds, sz); + if (PTR_ERR(mb) != -EAGAIN) + break; + } + remove_wait_queue(&vds->sendq, &wait); + } + + if (IS_ERR(mb)) + return mb; + + BUG_ON(!mb); + + /* reset and reserve space for message header */ + mb_reset(mb); + mb_put_data(mb, sizeof(struct tipc_msg_hdr)); + + return mb; +} + +static int vds_queue_txbuf(struct tipc_virtio_dev *vds, struct tipc_msg_buf *mb) +{ + int err; + struct scatterlist sg; + bool need_notify = false; + + mutex_lock(&vds->lock); + if (vds->state == VDS_ONLINE) { + sg_init_one(&sg, mb->buf_va, mb->wpos); + err = virtqueue_add_outbuf(vds->txvq, &sg, 1, mb, GFP_KERNEL); + need_notify = virtqueue_kick_prepare(vds->txvq); + } else { + err = -ENODEV; + } + mutex_unlock(&vds->lock); + + if (need_notify) + virtqueue_notify(vds->txvq); + + return err; +} + +static int vds_add_channel(struct tipc_virtio_dev *vds, struct tipc_chan *chan) +{ + int ret; + + mutex_lock(&vds->lock); + if (vds->state == VDS_ONLINE) { + ret = idr_alloc_cyclic(&vds->addr_idr, chan, + TIPC_MIN_LOCAL_ADDR, TIPC_MAX_LOCAL_ADDR, + GFP_KERNEL); + if (ret > 0) { + chan->local = ret; + kref_get(&chan->refcount); + ret = 0; + } + } else { + ret = -EINVAL; + } + mutex_unlock(&vds->lock); + + return ret; +} + +static void vds_del_channel(struct tipc_virtio_dev *vds, struct tipc_chan *chan) +{ + mutex_lock(&vds->lock); + if (chan->local) { + idr_remove(&vds->addr_idr, chan->local); + chan->local = 0; + chan->remote = 0; + kref_put(&chan->refcount, _free_chan); + } + mutex_unlock(&vds->lock); +} + +static struct tipc_chan *vds_lookup_channel(struct tipc_virtio_dev *vds, + u32 addr) +{ + int id; + struct tipc_chan *chan = NULL; + + mutex_lock(&vds->lock); + if (addr == TIPC_ANY_ADDR) { + id = idr_for_each(&vds->addr_idr, _match_any, NULL); + if (id > 0) + chan = idr_find(&vds->addr_idr, id); + } else { + chan = idr_find(&vds->addr_idr, addr); + } + if (chan) + kref_get(&chan->refcount); + mutex_unlock(&vds->lock); + + return chan; +} + +static struct tipc_chan *vds_create_channel(struct tipc_virtio_dev *vds, + const struct tipc_chan_ops *ops, + void *ops_arg) +{ + int ret; + struct tipc_chan *chan = NULL; + + if (!vds) + return ERR_PTR(-ENOENT); + + if (!ops) + return ERR_PTR(-EINVAL); + + chan = kzalloc(sizeof(*chan), GFP_KERNEL); + if (!chan) + return ERR_PTR(-ENOMEM); + + kref_get(&vds->refcount); + chan->vds = vds; + chan->ops = ops; + chan->ops_arg = ops_arg; + mutex_init(&chan->lock); + kref_init(&chan->refcount); + chan->state = TIPC_DISCONNECTED; + INIT_LIST_HEAD(&chan->mref_list); + init_waitqueue_head(&chan->mrefq); + + ret = vds_add_channel(vds, chan); + if (ret) { + kfree(chan); + kref_put(&vds->refcount, _free_vds); + return ERR_PTR(ret); + } + + return chan; +} + +static void fill_msg_hdr(struct tipc_msg_buf *mb, u32 src, u32 dst) +{ + struct tipc_msg_hdr *hdr = mb_get_data(mb, sizeof(*hdr)); + + hdr->src = src; + hdr->dst = dst; + hdr->len = mb_avail_data(mb); + hdr->flags = 0; + hdr->reserved = 0; +} + +/*****************************************************************************/ + +static int memref_preflight_check(struct tipc_shmem *shm) +{ + unsigned int i; + + if (!shm) + return -EINVAL; + + for (i = 0; i < 3; i++) { + /* size has to be page aligned */ + if (shm->size[i] & (PAGE_SIZE - 1)) + return -EINVAL; + + /* base address also has not be page aligned */ + if ((uintptr_t)shm->base[i] & (PAGE_SIZE - 1)) + return -EINVAL; + } + return 0; +} + +static int memrefv_preflight_check(struct tipc_shmem *shmv, uint shmv_cnt) +{ + int ret; + unsigned int i; + + if (shmv_cnt > MAX_MEMREF_NUM) + return -EINVAL; + + for (i = 0; i < shmv_cnt; i++) { + ret = memref_preflight_check(&shmv[i]); + if (ret < 0) + return ret; + } + return 0; +} + +static unsigned int memref_count_pages(struct tipc_shmem *shm) +{ + unsigned int i; + unsigned int pg_cnt = 0; + + for (i = 0; i < 3; i++) + pg_cnt += shm->size[i] / PAGE_SIZE; + return pg_cnt; +} + +static void memref_release_pages(struct tipc_memref *mref, bool dirty) +{ + unsigned int i; + + /* if pages are pinned, unpin them */ + for (i = 0; i < mref->pg_pinned; i++) { + if (dirty) + set_page_dirty(mref->pages[i]); + put_page(mref->pages[i]); + } + mref->pg_pinned = 0; +} + +static void vds_memref_release_locked(struct tipc_virtio_dev *vds, u32 id) +{ + struct tipc_memref *mref = idr_find(&vds->mref_idr, id); + + if (WARN_ON(!mref)) { + pr_err("%s: memref (id=%u) is not found\n", __func__, id); + return; + } + + pr_debug("%s: id=%u %u\n", __func__, id, mref->pg_pinned); + + /* remove id */ + idr_remove(&mref->chan->vds->mref_idr, id); + + /* dec refs */ + list_del(&mref->node); + if (list_empty(&mref->chan->mref_list)) + wake_up_all(&mref->chan->mrefq); + + kref_put(&mref->chan->refcount, _free_chan); + mref->chan = NULL; + + memref_release_pages(mref, true); + kfree(mref); +} + +static void vds_memref_release(struct tipc_virtio_dev *vds, const u32 *ids, + uint ids_num) +{ + uint i; + mutex_lock(&vds->mref_lock); + for (i = 0; i < ids_num; i++) + vds_memref_release_locked(vds, ids[i]); + mutex_unlock(&vds->mref_lock); +} + +static int build_user_page_info(struct ns_mem_page_info *ns, + struct vm_area_struct *vmas[], + struct page *pages[], unsigned long pg_num) +{ + int ret; + unsigned long i; + + for (i = 0; i < pg_num; i++, ns++) { + struct vm_area_struct *vma = vmas[i]; + + ret = trusty_encode_page_info(ns, pages[i], vma->vm_page_prot, + !!(vma->vm_flags & VM_WRITE)); + if (ret < 0) + return ret; + } + return 0; +} + +static int build_kern_page_info(struct ns_mem_page_info *ns, + struct vm_area_struct *vma, + struct page *pages[], unsigned long pg_num) +{ + int ret; + unsigned long i; + + for (i = 0; i < pg_num; i++, ns++) { + ret = trusty_encode_page_info(ns, pages[i], vma->vm_page_prot, + !!(vma->vm_flags & VM_WRITE)); + if (ret < 0) + return ret; + } + return 0; +} + +static int append_kernel_memref(struct tipc_msg_mref_hdr *hdr, + struct tipc_memref *mref, + struct tipc_shmem *shm) +{ + long ret; + unsigned int i; + unsigned int pg_num; + unsigned long pg_start; + unsigned long pfn; + struct vm_area_struct *vma; + + /* sanity check */ + if (WARN_ON(shm->size[0] || shm->base[0]) || + WARN_ON(shm->size[2] || shm->base[2])) + return -EINVAL; + + /* in shm case, we're interested in region 1 */ + pg_num = shm->size[1] / PAGE_SIZE; + pg_start = (unsigned long)shm->base[1]; + + if (WARN_ON(!pg_num || !pg_start)) + return -EINVAL; + + down_read(¤t->mm->mmap_sem); + + vma = find_extend_vma(current->mm, pg_start); + + if (WARN_ON(!vma)) { + ret = -EINVAL; + goto err_out; + } + + /* TODO: check pg_num * PAGE_SIZE is within vm_area */ + /* TODO: follow pte for all pages, not only the first one. */ + /* obtain physical frame number */ + follow_pfn(vma, pg_start, &pfn); + if (WARN_ON(!pfn)) { + ret = -EINVAL; + goto err_out; + } + + /* fill pages of memref */ + for (i = 0; i < pg_num; i++, pfn++) { + mref->pages[i] = pfn_to_page(pfn); + if (WARN_ON(!mref->pages[i])) { + ret = -EINVAL; + goto err_out; + } + } + + hdr->id = 0; /* will be filled later */ + hdr->flags = shm->flags & TIPC_MEMREF_PERM_RW; + hdr->size = shm->size[1]; + hdr->pg_inf_cnt = shm->size[1] / PAGE_SIZE; + ret = build_kern_page_info(hdr->pg_inf, vma, mref->pages, pg_num); + +err_out: + up_read(¤t->mm->mmap_sem); + return ret; +} + +static int append_user_memref(struct tipc_msg_mref_hdr *hdr, + struct tipc_memref *mref, struct tipc_shmem *shm) +{ + long ret; + unsigned int gup_flags; + unsigned int i; + unsigned int pg_num; + unsigned long pg_start; + struct vm_area_struct **vmas; + + vmas = kcalloc(mref->pg_num, sizeof(*vmas), GFP_KERNEL); + if (!vmas) + return -ENOMEM; + + gup_flags = (shm->flags & TIPC_MEMREF_PERM_RW) ? FOLL_WRITE : 0; + + down_read(¤t->mm->mmap_sem); + + /* for all 3 regions */ + for (i = 0; i < 3; i++) { + pg_num = shm->size[i] / PAGE_SIZE; + pg_start = (unsigned long)shm->base[i]; + + if (!pg_start || !pg_num) + continue; + + ret = get_user_pages(pg_start, pg_num, gup_flags, + mref->pages + mref->pg_pinned, + vmas + mref->pg_pinned); + if (ret < 0) + goto err_pinned; + + mref->pg_pinned += (unsigned int)ret; + + if ((unsigned int)ret != pg_num) { + /* partially succeeded */ + ret = -EINVAL; + goto err_bad_cnt; + } + } + + hdr->id = 0; /* will be filled later */ + hdr->flags = shm->flags & TIPC_MEMREF_PERM_RW; + hdr->size = mref->pg_pinned * PAGE_SIZE; + hdr->pg_inf_cnt = mref->pg_pinned; + ret = build_user_page_info(hdr->pg_inf, vmas, mref->pages, + mref->pg_pinned); + +err_bad_cnt: +err_pinned: + if (ret < 0) + memref_release_pages(mref, false); + up_read(¤t->mm->mmap_sem); + kfree(vmas); + return ret; +} + +static int append_memrefs(struct tipc_chan *chan, struct tipc_msg_buf *mb, + u32 *mr_ids, struct tipc_shmem *shmv, uint shmv_cnt, + bool user) +{ + uint i; + int ret; + size_t sz; + unsigned int pg_num; + struct tipc_memref *mref; + struct tipc_msg_mref_hdr *hdr; + struct tipc_virtio_dev *vds = chan->vds; + + /* align output buffer */ + mb_align_write(mb, MEMREF_ALIGN); + + /* for each memrefs */ + mutex_lock(&chan->vds->mref_lock); + for (i = 0; i < shmv_cnt; i++) { + /* create memref tracking obj */ + pg_num = memref_count_pages(&shmv[i]); + if (!pg_num) { + ret = -EINVAL; + goto err_create; + } + + mref = kzalloc(sizeof(*mref) + pg_num * sizeof(struct page *), + GFP_KERNEL); + if (!mref) { + ret = -ENOMEM; + goto err_create; + } + mref->pg_num = pg_num; + + /* reserve space for memref object */ + sz = sizeof(struct tipc_msg_mref_hdr) + + sizeof(struct ns_mem_page_info) * pg_num; + hdr = mb_put_data(mb, sz); + + if (user) + ret = append_user_memref(hdr, mref, &shmv[i]); + else + ret = append_kernel_memref(hdr, mref, &shmv[i]); + if (ret) + goto err_append; + + /* create memref id */ + ret = idr_alloc(&vds->mref_idr, mref, TIPC_MIN_MEMREF_ID, + TIPC_MAX_MEMREF_ID, GFP_KERNEL); + + if (ret < 0) + goto err_idr_alloc; + + hdr->id = ret; + mr_ids[i] = ret; + + /* attach memref to chan object */ + kref_get(&chan->refcount); + mref->chan = chan; + list_add_tail(&mref->node, &chan->mref_list); + } + mutex_unlock(&chan->vds->mref_lock); + + return 0; + +err_idr_alloc: +err_append: + memref_release_pages(mref, false); + kfree(mref); +err_create: + while (i--) + vds_memref_release_locked(vds, mr_ids[i]); + mutex_unlock(&chan->vds->mref_lock); + return ret; +} + +/*****************************************************************************/ + +struct tipc_chan *tipc_create_channel(struct device *dev, + const struct tipc_chan_ops *ops, + void *ops_arg) +{ + struct virtio_device *vd; + struct tipc_chan *chan; + struct tipc_virtio_dev *vds; + + mutex_lock(&tipc_devices_lock); + if (dev) { + vd = container_of(dev, struct virtio_device, dev); + } else { + vd = default_vdev; + if (!vd) { + mutex_unlock(&tipc_devices_lock); + return ERR_PTR(-ENOENT); + } + } + vds = vd->priv; + kref_get(&vds->refcount); + mutex_unlock(&tipc_devices_lock); + + chan = vds_create_channel(vds, ops, ops_arg); + kref_put(&vds->refcount, _free_vds); + return chan; +} +EXPORT_SYMBOL(tipc_create_channel); + +struct tipc_msg_buf *tipc_chan_get_rxbuf(struct tipc_chan *chan) +{ + return vds_alloc_msg_buf(chan->vds); +} +EXPORT_SYMBOL(tipc_chan_get_rxbuf); + +void tipc_chan_put_rxbuf(struct tipc_chan *chan, struct tipc_msg_buf *mb) +{ + vds_free_msg_buf(chan->vds, mb); +} +EXPORT_SYMBOL(tipc_chan_put_rxbuf); + +struct tipc_msg_buf *tipc_chan_get_txbuf_timeout(struct tipc_chan *chan, + long timeout) +{ + struct tipc_virtio_dev *vds = chan->vds; + + return vds_get_txbuf(vds, vds->msg_buf_sz, timeout, true); +} +EXPORT_SYMBOL(tipc_chan_get_txbuf_timeout); + +void tipc_chan_put_txbuf(struct tipc_chan *chan, struct tipc_msg_buf *mb) +{ + vds_put_txbuf(chan->vds, mb); +} +EXPORT_SYMBOL(tipc_chan_put_txbuf); + +static int _tipc_chan_queue_msg(struct tipc_chan *chan, struct tipc_msg_buf *mb, + struct tipc_shmem *shmv, uint shmv_cnt, + bool user) +{ + int err; + u32 mr_ids[MAX_MEMREF_NUM]; + + mutex_lock(&chan->lock); + switch (chan->state) { + case TIPC_CONNECTED: + fill_msg_hdr(mb, chan->local, chan->remote); + + /* append memrefs if any */ + if (shmv_cnt) { + err = append_memrefs(chan, mb, mr_ids, shmv, shmv_cnt, + user); + if (err < 0) { + pr_err("%s: failed to append memrefs (%d)\n", + __func__, err); + break; + } + } + + /* queue message */ + err = vds_queue_txbuf(chan->vds, mb); + if (err) { + /* this should never happen */ + pr_err("%s: failed to queue tx buffer (%d)\n", __func__, + err); + vds_memref_release(chan->vds, mr_ids, shmv_cnt); + } + break; + case TIPC_DISCONNECTED: + case TIPC_CONNECTING: + err = -ENOTCONN; + break; + case TIPC_STALE: + err = -ESHUTDOWN; + break; + default: + err = -EBADFD; + pr_err("%s: unexpected channel state %d\n", __func__, + chan->state); + } + mutex_unlock(&chan->lock); + return err; +} + +int tipc_chan_queue_msg(struct tipc_chan *chan, struct tipc_msg_buf *mb) +{ + return _tipc_chan_queue_msg(chan, mb, NULL, 0, false); +} +EXPORT_SYMBOL(tipc_chan_queue_msg); + +int tipc_chan_connect(struct tipc_chan *chan, const char *name) +{ + int err; + struct tipc_ctrl_msg *msg; + struct tipc_conn_req_body *body; + struct tipc_msg_buf *txbuf; + + txbuf = tipc_chan_get_txbuf_timeout(chan, TXBUF_TIMEOUT); + if (IS_ERR(txbuf)) + return PTR_ERR(txbuf); + + /* reserve space for connection request control message */ + msg = mb_put_data(txbuf, sizeof(*msg) + sizeof(*body)); + body = (struct tipc_conn_req_body *)msg->body; + + /* fill message */ + msg->type = TIPC_CTRL_MSGTYPE_CONN_REQ; + msg->body_len = sizeof(*body); + + strlcpy(body->name, name, sizeof(body->name)); + body->name[sizeof(body->name) - 1] = '\0'; + + mutex_lock(&chan->lock); + switch (chan->state) { + case TIPC_DISCONNECTED: + /* save service name we are connecting to */ + strlcpy(chan->srv_name, body->name, sizeof(chan->srv_name)); + + fill_msg_hdr(txbuf, chan->local, TIPC_CTRL_ADDR); + err = vds_queue_txbuf(chan->vds, txbuf); + if (err) { + /* this should never happen */ + pr_err("%s: failed to queue tx buffer (%d)\n", __func__, + err); + } else { + chan->state = TIPC_CONNECTING; + txbuf = NULL; /* prevents discarding buffer */ + } + break; + case TIPC_CONNECTED: + case TIPC_CONNECTING: + /* check if we are trying to connect to the same service */ + if (strcmp(chan->srv_name, body->name) == 0) + err = 0; + else if (chan->state == TIPC_CONNECTING) + err = -EALREADY; /* in progress */ + else + err = -EISCONN; /* already connected */ + break; + + case TIPC_STALE: + err = -ESHUTDOWN; + break; + default: + err = -EBADFD; + pr_err("%s: unexpected channel state %d\n", __func__, + chan->state); + break; + } + mutex_unlock(&chan->lock); + + if (txbuf) + tipc_chan_put_txbuf(chan, txbuf); /* discard it */ + + return err; +} +EXPORT_SYMBOL(tipc_chan_connect); + +static void wait_for_memrefs(struct tipc_chan *chan) +{ + DEFINE_WAIT_FUNC(wait, woken_wake_function); + + if (list_empty(&chan->mref_list)) + return; + + add_wait_queue(&chan->mrefq, &wait); + do { + wait_woken(&wait, TASK_UNINTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); + } while (!list_empty(&chan->mref_list)); + remove_wait_queue(&chan->mrefq, &wait); +} + +int tipc_chan_shutdown(struct tipc_chan *chan) +{ + int err; + struct tipc_ctrl_msg *msg; + struct tipc_disc_req_body *body; + struct tipc_msg_buf *txbuf = NULL; + + /* get tx buffer */ + txbuf = vds_get_txbuf(chan->vds, chan->vds->msg_buf_sz, TXBUF_TIMEOUT, + false); + if (IS_ERR(txbuf)) + return PTR_ERR(txbuf); + + mutex_lock(&chan->lock); + if (chan->state == TIPC_CONNECTED || chan->state == TIPC_CONNECTING) { + /* reserve space for disconnect request control message */ + msg = mb_put_data(txbuf, sizeof(*msg) + sizeof(*body)); + body = (struct tipc_disc_req_body *)msg->body; + + msg->type = TIPC_CTRL_MSGTYPE_DISC_REQ; + msg->body_len = sizeof(*body); + body->target = chan->remote; + + fill_msg_hdr(txbuf, chan->local, TIPC_CTRL_ADDR); + err = vds_queue_txbuf(chan->vds, txbuf); + if (err) { + /* this should never happen */ + pr_err("%s: failed to queue tx buffer (%d)\n", __func__, + err); + } + } else { + err = -ENOTCONN; + } + chan->state = TIPC_STALE; + mutex_unlock(&chan->lock); + + /* wait for all outstanding memref to be released by remote side */ + wait_for_memrefs(chan); + + if (err) { + /* release buffer */ + tipc_chan_put_txbuf(chan, txbuf); + } + + return err; +} +EXPORT_SYMBOL(tipc_chan_shutdown); + +void tipc_chan_destroy(struct tipc_chan *chan) +{ + vds_del_channel(chan->vds, chan); + kref_put(&chan->refcount, _free_chan); +} +EXPORT_SYMBOL(tipc_chan_destroy); + +/***************************************************************************/ +struct mref_shm { + unsigned long vm_start; + uintptr_t vaddr; + phys_addr_t paddr; + size_t size; + struct list_head node; +}; + +struct tipc_dn_chan { + int state; + struct mutex lock; /* protects rx_msg_queue list and channel state */ + struct tipc_chan *chan; + wait_queue_head_t readq; + struct completion reply_comp; + struct list_head rx_msg_queue; + struct list_head mref_shm_list; /* used in static shm allocation */ +}; + +static int dn_wait_for_reply(struct tipc_dn_chan *dn, int timeout) +{ + int ret; + + ret = wait_for_completion_interruptible_timeout( + &dn->reply_comp, msecs_to_jiffies(timeout)); + if (ret < 0) + return ret; + + mutex_lock(&dn->lock); + if (!ret) { + /* no reply from remote */ + dn->state = TIPC_STALE; + ret = -ETIMEDOUT; + } else { + /* got reply */ + if (dn->state == TIPC_CONNECTED) + ret = 0; + else if (dn->state == TIPC_DISCONNECTED) + if (!list_empty(&dn->rx_msg_queue)) + ret = 0; + else + ret = -ENOTCONN; + else + ret = -EIO; + } + mutex_unlock(&dn->lock); + + return ret; +} + +struct tipc_msg_buf *dn_handle_msg(void *data, struct tipc_msg_buf *rxbuf) +{ + struct tipc_dn_chan *dn = data; + struct tipc_msg_buf *newbuf = rxbuf; + + mutex_lock(&dn->lock); + if (dn->state == TIPC_CONNECTED) { + /* get new buffer */ + newbuf = tipc_chan_get_rxbuf(dn->chan); + if (newbuf) { + /* queue an old buffer and return a new one */ + list_add_tail(&rxbuf->node, &dn->rx_msg_queue); + wake_up_interruptible(&dn->readq); + } else { + /* + * return an old buffer effectively discarding + * incoming message + */ + pr_err("%s: discard incoming message\n", __func__); + newbuf = rxbuf; + } + } + mutex_unlock(&dn->lock); + + return newbuf; +} + +static void dn_connected(struct tipc_dn_chan *dn) +{ + mutex_lock(&dn->lock); + dn->state = TIPC_CONNECTED; + + /* complete all pending */ + complete(&dn->reply_comp); + + mutex_unlock(&dn->lock); +} + +static void dn_disconnected(struct tipc_dn_chan *dn) +{ + mutex_lock(&dn->lock); + dn->state = TIPC_DISCONNECTED; + + /* complete all pending */ + complete(&dn->reply_comp); + + /* wakeup all readers */ + wake_up_interruptible_all(&dn->readq); + + mutex_unlock(&dn->lock); +} + +static void dn_shutdown(struct tipc_dn_chan *dn) +{ + mutex_lock(&dn->lock); + + /* set state to STALE */ + dn->state = TIPC_STALE; + + /* complete all pending */ + complete(&dn->reply_comp); + + /* wakeup all readers */ + wake_up_interruptible_all(&dn->readq); + + mutex_unlock(&dn->lock); +} + +static void dn_handle_event(void *data, int event) +{ + struct tipc_dn_chan *dn = data; + + switch (event) { + case TIPC_CHANNEL_SHUTDOWN: + dn_shutdown(dn); + break; + + case TIPC_CHANNEL_DISCONNECTED: + dn_disconnected(dn); + break; + + case TIPC_CHANNEL_CONNECTED: + dn_connected(dn); + break; + + default: + pr_err("%s: unhandled event %d\n", __func__, event); + break; + } +} + +static void dn_handle_release(void *data) +{ + kfree(data); +} + +static struct tipc_chan_ops _dn_ops = { + .handle_msg = dn_handle_msg, + .handle_event = dn_handle_event, + .handle_release = dn_handle_release, +}; + +#define cdev_to_cdn(c) container_of((c), struct tipc_cdev_node, cdev) +#define cdn_to_vds(cdn) container_of((cdn), struct tipc_virtio_dev, cdev_node) + +static struct tipc_virtio_dev *_dn_lookup_vds(struct tipc_cdev_node *cdn) +{ + int ret; + struct tipc_virtio_dev *vds = NULL; + + mutex_lock(&tipc_devices_lock); + ret = idr_for_each(&tipc_devices, _match_data, cdn); + if (ret) { + vds = cdn_to_vds(cdn); + kref_get(&vds->refcount); + } + mutex_unlock(&tipc_devices_lock); + return vds; +} + +static int tipc_open(struct inode *inode, struct file *filp) +{ + int ret; + struct tipc_virtio_dev *vds; + struct tipc_dn_chan *dn; + struct tipc_cdev_node *cdn = cdev_to_cdn(inode->i_cdev); + + vds = _dn_lookup_vds(cdn); + if (!vds) { + ret = -ENOENT; + goto err_vds_lookup; + } + + dn = kzalloc(sizeof(*dn), GFP_KERNEL); + if (!dn) { + ret = -ENOMEM; + goto err_alloc_chan; + } + + mutex_init(&dn->lock); + init_waitqueue_head(&dn->readq); + init_completion(&dn->reply_comp); + INIT_LIST_HEAD(&dn->rx_msg_queue); + INIT_LIST_HEAD(&dn->mref_shm_list); + + dn->state = TIPC_DISCONNECTED; + + dn->chan = vds_create_channel(vds, &_dn_ops, dn); + if (IS_ERR(dn->chan)) { + ret = PTR_ERR(dn->chan); + goto err_create_chan; + } + + filp->private_data = dn; + kref_put(&vds->refcount, _free_vds); + return 0; + +err_create_chan: + kfree(dn); +err_alloc_chan: + kref_put(&vds->refcount, _free_vds); +err_vds_lookup: + return ret; +} + +static int dn_connect_ioctl(struct tipc_dn_chan *dn, char __user *usr_name) +{ + int err; + char name[MAX_SRV_NAME_LEN]; + + /* copy in service name from user space */ + err = strncpy_from_user(name, usr_name, sizeof(name)); + if (err < 0) { + pr_err("%s: copy_from_user (%p) failed (%d)\n", __func__, + usr_name, err); + return err; + } + name[sizeof(name) - 1] = '\0'; + + /* send connect request */ + err = tipc_chan_connect(dn->chan, name); + if (err) + return err; + + /* and wait for reply */ + return dn_wait_for_reply(dn, REPLY_TIMEOUT); +} + +#if !defined(CONFIG_COMPAT) +static int compat_import_iovec(int type, + const struct compat_iovec __user *uvector, + unsigned int nr_segs, unsigned int fast_segs, + struct iovec **iov, struct iov_iter *i) +{ + return -EINVAL; +} +#endif + +static long tipc_send_msg_ioctl(struct file *filp, unsigned long arg, + bool compat) +{ + ssize_t ret; + struct iov_iter msg_iter; + struct iovec iovstack[12]; + struct tipc_send_msg_req req; + struct tipc_shmem shmems[MAX_MEMREF_NUM]; + struct tipc_dn_chan *dn = filp->private_data; + struct iovec *iov = iovstack; + long timeout = (filp->f_flags & O_NONBLOCK) ? 0 : TXBUF_TIMEOUT; + bool mref_malloc = true; /* mref from malloc or mmap */ + struct mref_shm *mshm; + + /* copy in request */ + if (copy_from_user(&req, (const void __user *)arg, sizeof(req))) + return -EFAULT; + + if (req.shmemv_cnt > MAX_MEMREF_NUM) { + pr_err("%s: too many memrefs %u\n", __func__, req.shmemv_cnt); + return -EINVAL; + } + + /* import message iovecs */ + if (compat) + ret = compat_import_iovec(READ, (void *)(uintptr_t)req.msgiov, + req.msgiov_cnt, ARRAY_SIZE(iovstack), + &iov, &msg_iter); + else + ret = import_iovec(READ, (void *)(uintptr_t)req.msgiov, + req.msgiov_cnt, ARRAY_SIZE(iovstack), &iov, + &msg_iter); + if (ret < 0) + return ret; + + if (req.shmemv_cnt) { + /* import memref descriptors */ + if (copy_from_user(shmems, (const void __user *)req.shmemv, + req.shmemv_cnt * sizeof(shmems[0]))) { + ret = -EFAULT; + goto err_bad_descrs; + } + + /* + * NOTE(GRT): Since all of mref buffers either comes from + * malloc or mmap, check all buffers is not necessary. + * More, buffers from mref_mmap is always page-aligned, + * so we can skip the aux case, i.e., base[0] and base[2]. + */ + mutex_lock(&dn->lock); + list_for_each_entry(mshm, &dn->mref_shm_list, node) { + if (mshm->vm_start == shmems[0].base[1]) { + mref_malloc = false; + break; + } + } + mutex_unlock(&dn->lock); + } + + ret = _tipc_send_msg(dn->chan, &msg_iter, shmems, req.shmemv_cnt, + mref_malloc, timeout, true); + +err_bad_descrs: + kfree(iov); + return ret; +} + +static long tipc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + long ret; + struct tipc_dn_chan *dn = filp->private_data; + + if (_IOC_TYPE(cmd) != TIPC_IOC_MAGIC) + return -EINVAL; + + switch (cmd) { + case TIPC_IOC_CONNECT: + ret = dn_connect_ioctl(dn, (char __user *)arg); + break; + case TIPC_IOC_SEND_MSG: + ret = tipc_send_msg_ioctl(filp, arg, false); + break; + default: + pr_warn("%s: Unhandled ioctl cmd: 0x%x\n", __func__, cmd); + ret = -EINVAL; + } + return ret; +} + +#if defined(CONFIG_COMPAT) + +static long tipc_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + int ret; + struct tipc_dn_chan *dn = filp->private_data; + void __user *user_req = compat_ptr(arg); + + if (_IOC_TYPE(cmd) != TIPC_IOC_MAGIC) + return -EINVAL; + + switch (cmd) { + case TIPC_IOC_CONNECT_COMPAT: + ret = dn_connect_ioctl(dn, user_req); + break; + case TIPC_IOC_SEND_MSG: + ret = tipc_send_msg_ioctl(filp, arg, true); + break; + default: + pr_warn("%s: Unhandled ioctl cmd: 0x%x\n", __func__, cmd); + ret = -EINVAL; + } + return ret; +} +#endif + +static inline bool _got_rx(struct tipc_dn_chan *dn) +{ + if (dn->state != TIPC_CONNECTED) + return true; + + if (!list_empty(&dn->rx_msg_queue)) + return true; + + return false; +} + +static ssize_t tipc_read_iter(struct kiocb *iocb, struct iov_iter *iter) +{ + ssize_t ret; + size_t len; + struct tipc_msg_buf *mb; + struct file *filp = iocb->ki_filp; + struct tipc_dn_chan *dn = filp->private_data; + + mutex_lock(&dn->lock); + + while (list_empty(&dn->rx_msg_queue)) { + if (dn->state != TIPC_CONNECTED) { + if (dn->state == TIPC_CONNECTING) + ret = -ENOTCONN; + else if (dn->state == TIPC_DISCONNECTED) + ret = -ENOTCONN; + else if (dn->state == TIPC_STALE) + ret = -ESHUTDOWN; + else + ret = -EBADFD; + goto out; + } + + mutex_unlock(&dn->lock); + + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + + if (wait_event_interruptible(dn->readq, _got_rx(dn))) + return -ERESTARTSYS; + + mutex_lock(&dn->lock); + } + + mb = list_first_entry(&dn->rx_msg_queue, struct tipc_msg_buf, node); + + len = mb_avail_data(mb); + if (len > iov_iter_count(iter)) { + ret = -EMSGSIZE; + goto out; + } + + if (copy_to_iter(mb_get_data(mb, len), len, iter) != len) { + ret = -EFAULT; + goto out; + } + + ret = len; + list_del(&mb->node); + tipc_chan_put_rxbuf(dn->chan, mb); + +out: + mutex_unlock(&dn->lock); + return ret; +} + +static size_t aux_data_len(struct tipc_shmem *shmv, uint shmv_cnt) +{ + uint i; + size_t len; + unsigned int pg_num; + + len = shmv_cnt * sizeof(struct tipc_msg_mref_hdr); + for (i = 0; i < shmv_cnt; i++) { + pg_num = memref_count_pages(&shmv[i]); + len += pg_num * sizeof(struct ns_mem_page_info); + } + return len; +} + +static int _tipc_send_msg(struct tipc_chan *chan, struct iov_iter *msg_iter, + struct tipc_shmem *shmv, uint shmv_cnt, bool user, + long timeout, bool intr) +{ + int ret; + size_t len; + struct tipc_msg_buf *txbuf; + size_t aux_len = 0; + + /* pre flight check message length */ + len = iov_iter_count(msg_iter); + if (len > (chan->vds->msg_buf_sz - sizeof(struct tipc_msg_hdr))) + return -EMSGSIZE; + + if (shmv_cnt) { + /* do memref parameters check */ + ret = memrefv_preflight_check(shmv, shmv_cnt); + if (ret < 0) + return ret; + + /* calculate aux data size and add alignment */ + aux_len = + aux_data_len(shmv, shmv_cnt) + ALIGN(len, MEMREF_ALIGN); + } + + /* get or allocate tx buffer */ + txbuf = vds_get_txbuf(chan->vds, + sizeof(struct tipc_msg_hdr) + len + aux_len, + timeout, intr); + if (IS_ERR(txbuf)) + return PTR_ERR(txbuf); + + /* copy in message data */ + if (copy_from_iter(mb_put_data(txbuf, len), len, msg_iter) != len) { + ret = -EFAULT; + goto err_out; + } + + /* queue message */ + ret = _tipc_chan_queue_msg(chan, txbuf, shmv, shmv_cnt, user); + if (ret) + goto err_out; + + return len; + +err_out: + tipc_chan_put_txbuf(chan, txbuf); + return ret; +} + +static ssize_t tipc_write_iter(struct kiocb *iocb, struct iov_iter *iter) +{ + struct file *filp = iocb->ki_filp; + struct tipc_dn_chan *dn = filp->private_data; + long timeout = (filp->f_flags & O_NONBLOCK) ? 0 : TXBUF_TIMEOUT; + + return _tipc_send_msg(dn->chan, iter, NULL, 0, true, timeout, true); +} + +static unsigned int tipc_poll(struct file *filp, poll_table *wait) +{ + unsigned int mask = 0; + struct tipc_dn_chan *dn = filp->private_data; + + mutex_lock(&dn->lock); + + poll_wait(filp, &dn->readq, wait); + + /* Writes always succeed for now */ + mask |= POLLOUT | POLLWRNORM; + + if (!list_empty(&dn->rx_msg_queue)) + mask |= POLLIN | POLLRDNORM; + + if (dn->state != TIPC_CONNECTED) + mask |= POLLERR; + + mutex_unlock(&dn->lock); + return mask; +} + +void tipc_mref_vma_close(struct vm_area_struct *vma) +{ + struct mref_shm *mshm, *mshmtmp; + struct tipc_dn_chan *dn = vma->vm_private_data; + bool found = false; + + mutex_lock(&dn->lock); + + list_for_each_entry_safe(mshm, mshmtmp, &dn->mref_shm_list, node) { + if (mshm->vm_start == vma->vm_start) { + pr_info("%s: uva %lx sz %zx fl %lx kva %lx kpa %llx\n", + __func__, mshm->vm_start, mshm->size, + vma->vm_flags, mshm->vaddr, mshm->paddr); + _free_shareable_mem(mshm->size, (void *)mshm->vaddr, + mshm->paddr); + list_del(&mshm->node); + kfree(mshm); + found = true; + break; + } + } + + WARN_ON(unlikely(!found)); + + mutex_unlock(&dn->lock); +} + +static struct vm_operations_struct mref_vma_ops = { + .close = tipc_mref_vma_close, +}; + +static int tipc_mref_mmap(struct file *filp, struct vm_area_struct *vma) +{ + ulong offset, flags, pfn; + void *vaddr; + phys_addr_t paddr; + struct tipc_dn_chan *dn = filp->private_data; + size_t size; + pgprot_t prot; + struct mref_shm *mshm; + + if (!trusty_get_link_shbuf_device(0)) + return -ENODEV; + + flags = vma->vm_flags; + + if (WARN_ON((flags & VM_EXEC) && !(filp->f_mode & FMODE_EXEC))) + return -EINVAL; + + /* Check the mmap request is within bounds. */ + size = vma->vm_end - vma->vm_start; + if (WARN_ON(!PAGE_ALIGNED(size))) + return -EINVAL; + if (size > MAX_MREF_SIZE) + return -ENOMEM; + + offset = vma->vm_pgoff << PAGE_SHIFT; + if (WARN_ON(offset != 0)) + return -EINVAL; + + vaddr = _alloc_shareable_mem(size, NULL, GFP_KERNEL | __GFP_ZERO); + if (WARN_ON(!vaddr)) + return -ENOMEM; + paddr = trusty_shm_virt_to_phys(vaddr); + + mshm = kzalloc(sizeof(struct mref_shm), GFP_KERNEL); + if (WARN_ON(!mshm)) + return -ENOMEM; + + mshm->vm_start = vma->vm_start; + mshm->vaddr = (uintptr_t)vaddr; + mshm->paddr = paddr; + mshm->size = size; + list_add_tail(&mshm->node, &dn->mref_shm_list); + + pfn = (paddr + offset) >> PAGE_SHIFT; + prot = vm_get_page_prot(flags); + + vma->vm_ops = &mref_vma_ops; + vma->vm_private_data = dn; + + pr_info("%s: uva %lx sz %zx fl %lx kva %lx kpa %llx\n", __func__, + mshm->vm_start, mshm->size, vma->vm_flags, mshm->vaddr, + mshm->paddr); + + return remap_pfn_range(vma, vma->vm_start, pfn, size, prot); +} + +static int tipc_release(struct inode *inode, struct file *filp) +{ + struct tipc_dn_chan *dn = filp->private_data; + + dn_shutdown(dn); + + /* free all pending buffers */ + _free_msg_buf_list(&dn->rx_msg_queue); + + /* shutdown channel */ + tipc_chan_shutdown(dn->chan); + + /* and destroy it */ + tipc_chan_destroy(dn->chan); + + return 0; +} + +static const struct file_operations tipc_fops = { + .open = tipc_open, + .release = tipc_release, + .unlocked_ioctl = tipc_ioctl, +#if defined(CONFIG_COMPAT) + .compat_ioctl = tipc_compat_ioctl, +#endif + .read_iter = tipc_read_iter, + .write_iter = tipc_write_iter, + .poll = tipc_poll, + .mmap = tipc_mref_mmap, + .owner = THIS_MODULE, +}; + +/*****************************************************************************/ + +static void chan_trigger_event(struct tipc_chan *chan, int event) +{ + if (!event) + return; + + chan->ops->handle_event(chan->ops_arg, event); +} + +static void _cleanup_vq(struct virtqueue *vq) +{ + struct tipc_msg_buf *mb; + + while ((mb = virtqueue_detach_unused_buf(vq)) != NULL) + _free_msg_buf(mb); +} + +static int _create_cdev_node(struct device *parent, struct tipc_cdev_node *cdn, + const char *name) +{ + int ret; + dev_t devt; + + if (!name) { + dev_dbg(parent, "%s: cdev name has to be provided\n", __func__); + return -EINVAL; + } + + /* allocate minor */ + ret = idr_alloc(&tipc_devices, cdn, 0, MAX_DEVICES - 1, GFP_KERNEL); + if (ret < 0) { + dev_dbg(parent, "%s: failed (%d) to get id\n", __func__, ret); + return ret; + } + + cdn->minor = ret; + cdev_init(&cdn->cdev, &tipc_fops); + cdn->cdev.owner = THIS_MODULE; + + /* Add character device */ + devt = MKDEV(tipc_major, cdn->minor); + ret = cdev_add(&cdn->cdev, devt, 1); + if (ret) { + dev_dbg(parent, "%s: cdev_add failed (%d)\n", __func__, ret); + goto err_add_cdev; + } + + /* Create a device node */ + cdn->dev = device_create(tipc_class, parent, devt, NULL, + "trusty-ipc-%s", name); + if (IS_ERR(cdn->dev)) { + ret = PTR_ERR(cdn->dev); + dev_dbg(parent, "%s: device_create failed: %d\n", __func__, + ret); + goto err_device_create; + } + + return 0; + +err_device_create: + cdn->dev = NULL; + cdev_del(&cdn->cdev); +err_add_cdev: + idr_remove(&tipc_devices, cdn->minor); + return ret; +} + +static void create_cdev_node(struct tipc_virtio_dev *vds, + struct tipc_cdev_node *cdn) +{ + int err; + + mutex_lock(&tipc_devices_lock); + + if (!default_vdev) { + kref_get(&vds->refcount); + default_vdev = vds->vdev; + } + + if (vds->cdev_name[0] && !cdn->dev) { + kref_get(&vds->refcount); + err = _create_cdev_node(&vds->vdev->dev, cdn, vds->cdev_name); + if (err) { + dev_err(&vds->vdev->dev, + "failed (%d) to create cdev node\n", err); + kref_put(&vds->refcount, _free_vds); + } + } + mutex_unlock(&tipc_devices_lock); +} + +static void destroy_cdev_node(struct tipc_virtio_dev *vds, + struct tipc_cdev_node *cdn) +{ + mutex_lock(&tipc_devices_lock); + if (cdn->dev) { + device_destroy(tipc_class, MKDEV(tipc_major, cdn->minor)); + cdev_del(&cdn->cdev); + idr_remove(&tipc_devices, cdn->minor); + cdn->dev = NULL; + kref_put(&vds->refcount, _free_vds); + } + + if (default_vdev == vds->vdev) { + default_vdev = NULL; + kref_put(&vds->refcount, _free_vds); + } + + mutex_unlock(&tipc_devices_lock); +} + +static void _go_online(struct tipc_virtio_dev *vds) +{ + mutex_lock(&vds->lock); + if (vds->state == VDS_OFFLINE) + vds->state = VDS_ONLINE; + mutex_unlock(&vds->lock); + + create_cdev_node(vds, &vds->cdev_node); + + dev_info(&vds->vdev->dev, "is online\n"); +} + +static void _go_offline(struct tipc_virtio_dev *vds) +{ + struct tipc_chan *chan; + + /* change state to OFFLINE */ + mutex_lock(&vds->lock); + if (vds->state != VDS_ONLINE) { + mutex_unlock(&vds->lock); + return; + } + vds->state = VDS_OFFLINE; + mutex_unlock(&vds->lock); + + /* wakeup all waiters */ + wake_up_all(&vds->sendq); + + /* shutdown all channels */ + while ((chan = vds_lookup_channel(vds, TIPC_ANY_ADDR))) { + mutex_lock(&chan->lock); + chan->state = TIPC_STALE; + chan->remote = 0; + chan_trigger_event(chan, TIPC_CHANNEL_SHUTDOWN); + mutex_unlock(&chan->lock); + kref_put(&chan->refcount, _free_chan); + } + + /* shutdown device node */ + destroy_cdev_node(vds, &vds->cdev_node); + + dev_info(&vds->vdev->dev, "is offline\n"); +} + +static void _handle_conn_rsp(struct tipc_virtio_dev *vds, + struct tipc_conn_rsp_body *rsp, size_t len) +{ + struct tipc_chan *chan; + + if (sizeof(*rsp) != len) { + dev_err(&vds->vdev->dev, "%s: Invalid response length %zd\n", + __func__, len); + return; + } + + dev_dbg(&vds->vdev->dev, + "%s: connection response: for addr 0x%x: " + "status %d remote addr 0x%x\n", + __func__, rsp->target, rsp->status, rsp->remote); + + /* Lookup channel */ + chan = vds_lookup_channel(vds, rsp->target); + if (chan) { + mutex_lock(&chan->lock); + if (chan->state == TIPC_CONNECTING) { + if (!rsp->status) { + chan->state = TIPC_CONNECTED; + chan->remote = rsp->remote; + chan->max_msg_cnt = rsp->max_msg_cnt; + chan->max_msg_size = rsp->max_msg_size; + chan_trigger_event(chan, + TIPC_CHANNEL_CONNECTED); + } else { + chan->state = TIPC_DISCONNECTED; + chan->remote = 0; + chan_trigger_event(chan, + TIPC_CHANNEL_DISCONNECTED); + } + } + mutex_unlock(&chan->lock); + kref_put(&chan->refcount, _free_chan); + } +} + +static void _handle_disc_req(struct tipc_virtio_dev *vds, + struct tipc_disc_req_body *req, size_t len) +{ + struct tipc_chan *chan; + + if (sizeof(*req) != len) { + dev_err(&vds->vdev->dev, "%s: Invalid request length %zd\n", + __func__, len); + return; + } + + dev_dbg(&vds->vdev->dev, "%s: disconnect request: for addr 0x%x\n", + __func__, req->target); + + chan = vds_lookup_channel(vds, req->target); + if (chan) { + mutex_lock(&chan->lock); + if (chan->state == TIPC_CONNECTED || + chan->state == TIPC_CONNECTING) { + chan->state = TIPC_DISCONNECTED; + chan->remote = 0; + chan_trigger_event(chan, TIPC_CHANNEL_DISCONNECTED); + } + mutex_unlock(&chan->lock); + kref_put(&chan->refcount, _free_chan); + } +} + +static void _handle_mref_release_req(struct tipc_virtio_dev *vds, + struct tipc_mref_release_req_body *req, + size_t len) +{ + while (len >= sizeof(*req)) { + if (req->id) { + /* release memref with specified id */ + vds_memref_release(vds, &req->id, 1); + } + req++; + len -= sizeof(*req); + } + WARN_ON(len); +} + +static void _handle_ctrl_msg(struct tipc_virtio_dev *vds, void *data, int len, + u32 src) +{ + struct tipc_ctrl_msg *msg = data; + + if ((len < sizeof(*msg)) || (sizeof(*msg) + msg->body_len != len)) { + dev_err(&vds->vdev->dev, + "%s: Invalid message length ( %d vs. %d)\n", __func__, + (int)(sizeof(*msg) + msg->body_len), len); + return; + } + + dev_dbg(&vds->vdev->dev, + "%s: Incoming ctrl message: src 0x%x type %d len %d\n", + __func__, src, msg->type, msg->body_len); + + switch (msg->type) { + case TIPC_CTRL_MSGTYPE_GO_ONLINE: + _go_online(vds); + break; + + case TIPC_CTRL_MSGTYPE_GO_OFFLINE: + _go_offline(vds); + break; + + case TIPC_CTRL_MSGTYPE_CONN_RSP: + _handle_conn_rsp(vds, (struct tipc_conn_rsp_body *)msg->body, + msg->body_len); + break; + + case TIPC_CTRL_MSGTYPE_DISC_REQ: + _handle_disc_req(vds, (struct tipc_disc_req_body *)msg->body, + msg->body_len); + break; + + case TIPC_CTRL_MSGTYPE_MREF_RELEASE_REQ: { + struct tipc_mref_release_req_body *req = + (struct tipc_mref_release_req_body *)msg->body; + _handle_mref_release_req(vds, req, msg->body_len); + } break; + + default: + dev_warn(&vds->vdev->dev, "%s: Unexpected message type: %d\n", + __func__, msg->type); + } +} + +static int _handle_rxbuf(struct tipc_virtio_dev *vds, + struct tipc_msg_buf *rxbuf, size_t rxlen) +{ + int err; + struct scatterlist sg; + struct tipc_msg_hdr *msg; + struct device *dev = &vds->vdev->dev; + + /* message sanity check */ + if (rxlen > rxbuf->buf_sz) { + dev_warn(dev, "inbound msg is too big: %zd\n", rxlen); + goto drop_it; + } + + if (rxlen < sizeof(*msg)) { + dev_warn(dev, "inbound msg is too short: %zd\n", rxlen); + goto drop_it; + } + + /* reset buffer and put data */ + mb_reset(rxbuf); + mb_put_data(rxbuf, rxlen); + + /* get message header */ + msg = mb_get_data(rxbuf, sizeof(*msg)); + if (mb_avail_data(rxbuf) != msg->len) { + dev_warn(dev, "inbound msg length mismatch: (%d vs. %d)\n", + (uint)mb_avail_data(rxbuf), (uint)msg->len); + goto drop_it; + } + + dev_dbg(dev, "From: %d, To: %d, Len: %d, Flags: 0x%x, Reserved: %d\n", + msg->src, msg->dst, msg->len, msg->flags, msg->reserved); + + /* message directed to control endpoint is a special case */ + if (msg->dst == TIPC_CTRL_ADDR) { + _handle_ctrl_msg(vds, msg->data, msg->len, msg->src); + } else { + struct tipc_chan *chan = NULL; + /* Lookup channel */ + chan = vds_lookup_channel(vds, msg->dst); + if (chan) { + /* handle it */ + rxbuf = chan->ops->handle_msg(chan->ops_arg, rxbuf); + BUG_ON(!rxbuf); + kref_put(&chan->refcount, _free_chan); + } + } + +drop_it: + /* add the buffer back to the virtqueue */ + sg_init_one(&sg, rxbuf->buf_va, rxbuf->buf_sz); + err = virtqueue_add_inbuf(vds->rxvq, &sg, 1, rxbuf, GFP_KERNEL); + if (err < 0) { + dev_err(dev, "failed to add a virtqueue buffer: %d\n", err); + return err; + } + + return 0; +} + +static void _rxvq_cb(struct virtqueue *rxvq) +{ + unsigned int len; + struct tipc_msg_buf *mb; + unsigned int msg_cnt = 0; + struct tipc_virtio_dev *vds = rxvq->vdev->priv; + + while ((mb = virtqueue_get_buf(rxvq, &len)) != NULL) { + if (_handle_rxbuf(vds, mb, len)) + break; + msg_cnt++; + } + + /* tell the other size that we added rx buffers */ + if (msg_cnt) + virtqueue_kick(rxvq); +} + +static void _discard_ctrl_msg(struct tipc_virtio_dev *vds, + struct tipc_msg_buf *mb) +{ + /* nothing to do for control messages */ +} + +static void _discard_chan_msg(struct tipc_virtio_dev *vds, + struct tipc_msg_hdr *msg, struct tipc_msg_buf *mb) +{ + struct tipc_msg_mref_hdr *mhdr; + + /* skip message data */ + (void)mb_get_data(mb, msg->len); + + /* check if we have memrefs attached */ + if (!mb_avail_data(mb)) + return; /* no more data */ + + /* align for proper boundary */ + mb_align_read(mb, MEMREF_ALIGN); + + /* discard all memrefs */ + while (mb_avail_data(mb)) { + /* get memref */ + mhdr = mb_get_data(mb, sizeof(*mhdr)); + + /* release mref_by id */ + vds_memref_release(vds, &mhdr->id, 1); + + /* skip to next memref hdr */ + (void)mb_get_data(mb, + mhdr->pg_inf_cnt * sizeof(mhdr->pg_inf[0])); + } +} + +static void _txvq_cb(struct virtqueue *txvq) +{ + unsigned int len; + struct tipc_msg_buf *mb; + bool need_wakeup = false; + struct tipc_virtio_dev *vds = txvq->vdev->priv; + + dev_dbg(&txvq->vdev->dev, "%s\n", __func__); + + /* detach all buffers */ + mutex_lock(&vds->lock); + while ((mb = virtqueue_get_buf(txvq, &len)) != NULL) { + if ((int)len < 0) { + struct tipc_msg_hdr *msg; + + mb_reset_read(mb); + msg = mb_get_data(mb, sizeof(*msg)); + if (msg->dst == TIPC_CTRL_ADDR) + _discard_ctrl_msg(vds, mb); + else + _discard_chan_msg(vds, msg, mb); + } + need_wakeup |= _put_txbuf_locked(vds, mb); + } + mutex_unlock(&vds->lock); + + if (need_wakeup) { + /* wake up potential senders waiting for a tx buffer */ + wake_up_all(&vds->sendq); + } +} + +static int tipc_virtio_probe(struct virtio_device *vdev) +{ + int err, i; + struct tipc_virtio_dev *vds; + struct tipc_dev_config config; + struct virtqueue *vqs[2]; + vq_callback_t *vq_cbs[] = { _rxvq_cb, _txvq_cb }; + const char *vq_names[] = { "rx", "tx" }; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + bool *ctx = NULL; +#endif + + dev_dbg(&vdev->dev, "%s:\n", __func__); + + vds = kzalloc(sizeof(*vds), GFP_KERNEL); + if (!vds) + return -ENOMEM; + + vds->vdev = vdev; + + mutex_init(&vds->lock); + kref_init(&vds->refcount); + init_waitqueue_head(&vds->sendq); + INIT_LIST_HEAD(&vds->free_buf_list); + INIT_LIST_HEAD(&vds->stashed_buf_list); + idr_init(&vds->addr_idr); + idr_init(&vds->mref_idr); + mutex_init(&vds->mref_lock); + + /* set default max message size and alignment */ + memset(&config, 0, sizeof(config)); + config.msg_buf_max_size = DEFAULT_MSG_BUF_SIZE; + config.msg_buf_alignment = DEFAULT_MSG_BUF_ALIGN; + + /* get configuration if present */ + vdev->config->get(vdev, 0, &config, sizeof(config)); + + /* copy dev name */ + strlcpy(vds->cdev_name, config.dev_name, sizeof(vds->cdev_name)); + vds->cdev_name[sizeof(vds->cdev_name) - 1] = '\0'; + + /* find tx virtqueues (rx and tx and in this order) */ +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4, 10, 0) + err = vdev->config->find_vqs(vdev, 2, vqs, vq_cbs, vq_names); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + err = vdev->config->find_vqs(vdev, 2, vqs, vq_cbs, vq_names, ctx, NULL); +#endif + if (err) + goto err_find_vqs; + + vds->rxvq = vqs[0]; + vds->txvq = vqs[1]; + + /* save max buffer size and count */ + vds->msg_buf_sz = config.msg_buf_max_size; + vds->msg_buf_max_cnt = virtqueue_get_vring_size(vds->txvq); + + /* set up the receive buffers */ + for (i = 0; i < virtqueue_get_vring_size(vds->rxvq); i++) { + struct scatterlist sg; + struct tipc_msg_buf *rxbuf; + + rxbuf = _alloc_msg_buf(vds->msg_buf_sz); + if (!rxbuf) { + dev_err(&vdev->dev, "failed to allocate rx buffer\n"); + err = -ENOMEM; + goto err_free_rx_buffers; + } + + sg_init_one(&sg, rxbuf->buf_va, rxbuf->buf_sz); + err = virtqueue_add_inbuf(vds->rxvq, &sg, 1, rxbuf, GFP_KERNEL); + WARN_ON(err); /* sanity check; this can't really happen */ + } + + vdev->priv = vds; + vds->state = VDS_OFFLINE; + + dev_dbg(&vdev->dev, "%s: done\n", __func__); + return 0; + +err_free_rx_buffers: + _cleanup_vq(vds->rxvq); +err_find_vqs: + kref_put(&vds->refcount, _free_vds); + return err; +} + +static void tipc_virtio_remove(struct virtio_device *vdev) +{ + struct tipc_virtio_dev *vds = vdev->priv; + + _go_offline(vds); + + mutex_lock(&vds->lock); + vds->state = VDS_DEAD; + vds->vdev = NULL; + mutex_unlock(&vds->lock); + + vdev->config->reset(vdev); + + idr_destroy(&vds->mref_idr); + idr_destroy(&vds->addr_idr); + + _cleanup_vq(vds->rxvq); + _cleanup_vq(vds->txvq); + _free_msg_buf_list(&vds->free_buf_list); + _free_msg_buf_list(&vds->stashed_buf_list); + + vdev->config->del_vqs(vds->vdev); + + kref_put(&vds->refcount, _free_vds); +} + +static struct virtio_device_id tipc_virtio_id_table[] = { + { VIRTIO_ID_TRUSTY_IPC, VIRTIO_DEV_ANY_ID }, + { 0 }, +}; + +static unsigned int features[] = { + 0, +}; + +static struct virtio_driver virtio_tipc_driver = { + .feature_table = features, + .feature_table_size = ARRAY_SIZE(features), + .driver.name = KBUILD_MODNAME, + .driver.owner = THIS_MODULE, + .id_table = tipc_virtio_id_table, + .probe = tipc_virtio_probe, + .remove = tipc_virtio_remove, +}; + +static int __init tipc_init(void) +{ + int ret; + dev_t dev; + + ret = alloc_chrdev_region(&dev, 0, MAX_DEVICES, KBUILD_MODNAME); + if (ret) { + pr_err("%s: alloc_chrdev_region failed: %d\n", __func__, ret); + return ret; + } + + tipc_major = MAJOR(dev); + tipc_class = class_create(THIS_MODULE, KBUILD_MODNAME); + if (IS_ERR(tipc_class)) { + ret = PTR_ERR(tipc_class); + pr_err("%s: class_create failed: %d\n", __func__, ret); + goto err_class_create; + } + + ret = register_virtio_driver(&virtio_tipc_driver); + if (ret) { + pr_err("failed to register virtio driver: %d\n", ret); + goto err_register_virtio_drv; + } + + return 0; + +err_register_virtio_drv: + class_destroy(tipc_class); + +err_class_create: + unregister_chrdev_region(dev, MAX_DEVICES); + return ret; +} + +static void __exit tipc_exit(void) +{ + unregister_virtio_driver(&virtio_tipc_driver); + class_destroy(tipc_class); + unregister_chrdev_region(MKDEV(tipc_major, 0), MAX_DEVICES); +} + +/* We need to init this early */ +subsys_initcall(tipc_init); +module_exit(tipc_exit); + +MODULE_DEVICE_TABLE(tipc, tipc_virtio_id_table); +MODULE_DESCRIPTION("Trusty IPC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/trusty/trusty-irq.c b/drivers/trusty/trusty-irq.c new file mode 100644 index 000000000000..3de7ac28b9ee --- /dev/null +++ b/drivers/trusty/trusty-irq.c @@ -0,0 +1,598 @@ +/* + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct trusty_irq { + struct trusty_irq_state *is; + struct hlist_node node; + unsigned int irq; + bool percpu; + bool enable; + struct trusty_irq __percpu *percpu_ptr; +}; + +struct trusty_irq_irqset { + struct hlist_head pending; + struct hlist_head inactive; +}; + +struct trusty_irq_state { + struct device *dev; + struct device *trusty_dev; + struct trusty_irq_irqset normal_irqs; + spinlock_t normal_irqs_lock; + struct trusty_irq_irqset __percpu *percpu_irqs; + struct notifier_block trusty_call_notifier; + struct hlist_node cpuhp_node; +}; + +static int trusty_irq_cpuhp_slot = -1; + +static void trusty_irq_enable_pending_irqs(struct trusty_irq_state *is, + struct trusty_irq_irqset *irqset, + bool percpu) +{ + struct hlist_node *n; + struct trusty_irq *trusty_irq; + + hlist_for_each_entry_safe(trusty_irq, n, &irqset->pending, node) { + dev_dbg(is->dev, + "%s: enable pending irq %d, percpu %d, cpu %d\n", + __func__, trusty_irq->irq, percpu, smp_processor_id()); + if (percpu) + enable_percpu_irq(trusty_irq->irq, 0); + else + enable_irq(trusty_irq->irq); + hlist_del(&trusty_irq->node); + hlist_add_head(&trusty_irq->node, &irqset->inactive); + } +} + +static void trusty_irq_enable_irqset(struct trusty_irq_state *is, + struct trusty_irq_irqset *irqset) +{ + struct trusty_irq *trusty_irq; + + hlist_for_each_entry(trusty_irq, &irqset->inactive, node) { + if (trusty_irq->enable) { + dev_warn(is->dev, + "%s: percpu irq %d already enabled, cpu %d\n", + __func__, trusty_irq->irq, smp_processor_id()); + continue; + } + dev_dbg(is->dev, "%s: enable percpu irq %d, cpu %d\n", __func__, + trusty_irq->irq, smp_processor_id()); + enable_percpu_irq(trusty_irq->irq, 0); + trusty_irq->enable = true; + } +} + +static void trusty_irq_disable_irqset(struct trusty_irq_state *is, + struct trusty_irq_irqset *irqset) +{ + struct hlist_node *n; + struct trusty_irq *trusty_irq; + + hlist_for_each_entry(trusty_irq, &irqset->inactive, node) { + if (!trusty_irq->enable) { + dev_warn(is->dev, + "irq %d already disabled, percpu %d, cpu %d\n", + trusty_irq->irq, trusty_irq->percpu, + smp_processor_id()); + continue; + } + dev_dbg(is->dev, "%s: disable irq %d, percpu %d, cpu %d\n", + __func__, trusty_irq->irq, trusty_irq->percpu, + smp_processor_id()); + trusty_irq->enable = false; + if (trusty_irq->percpu) + disable_percpu_irq(trusty_irq->irq); + else + disable_irq_nosync(trusty_irq->irq); + } + hlist_for_each_entry_safe(trusty_irq, n, &irqset->pending, node) { + if (!trusty_irq->enable) { + dev_warn( + is->dev, + "pending irq %d already disabled, percpu %d, cpu %d\n", + trusty_irq->irq, trusty_irq->percpu, + smp_processor_id()); + } + dev_dbg(is->dev, + "%s: disable pending irq %d, percpu %d, cpu %d\n", + __func__, trusty_irq->irq, trusty_irq->percpu, + smp_processor_id()); + trusty_irq->enable = false; + hlist_del(&trusty_irq->node); + hlist_add_head(&trusty_irq->node, &irqset->inactive); + } +} + +static int trusty_irq_call_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct trusty_irq_state *is; + + BUG_ON(!irqs_disabled()); + + if (action != TRUSTY_CALL_PREPARE) + return NOTIFY_DONE; + + is = container_of(nb, struct trusty_irq_state, trusty_call_notifier); + + spin_lock(&is->normal_irqs_lock); + trusty_irq_enable_pending_irqs(is, &is->normal_irqs, false); + spin_unlock(&is->normal_irqs_lock); + trusty_irq_enable_pending_irqs(is, this_cpu_ptr(is->percpu_irqs), true); + + return NOTIFY_OK; +} + +irqreturn_t trusty_irq_handler(int irq, void *data) +{ + struct trusty_irq *trusty_irq = data; + struct trusty_irq_state *is = trusty_irq->is; + struct trusty_irq_irqset *irqset; + + dev_dbg(is->dev, "%s: irq %d, percpu %d, cpu %d, enable %d\n", __func__, + irq, trusty_irq->irq, smp_processor_id(), trusty_irq->enable); + + if (trusty_irq->percpu) { + disable_percpu_irq(irq); + irqset = this_cpu_ptr(is->percpu_irqs); + } else { + disable_irq_nosync(irq); + irqset = &is->normal_irqs; + } + + spin_lock(&is->normal_irqs_lock); + if (trusty_irq->enable) { + hlist_del(&trusty_irq->node); + hlist_add_head(&trusty_irq->node, &irqset->pending); + } + spin_unlock(&is->normal_irqs_lock); + + trusty_enqueue_nop(is->trusty_dev, NULL); + + dev_dbg(is->dev, "%s: irq %d done\n", __func__, irq); + + return IRQ_HANDLED; +} + +static int trusty_irq_cpu_up(unsigned int cpu, struct hlist_node *node) +{ + unsigned long irq_flags; + struct trusty_irq_state *is; + + is = container_of(node, struct trusty_irq_state, cpuhp_node); + + dev_dbg(is->dev, "%s: cpu %d\n", __func__, cpu); + + local_irq_save(irq_flags); + trusty_irq_enable_irqset(is, this_cpu_ptr(is->percpu_irqs)); + local_irq_restore(irq_flags); + + return 0; +} + +static int trusty_irq_cpu_down(unsigned int cpu, struct hlist_node *node) +{ + unsigned long irq_flags; + struct trusty_irq_state *is; + + is = container_of(node, struct trusty_irq_state, cpuhp_node); + + dev_dbg(is->dev, "%s: cpu %d\n", __func__, cpu); + + local_irq_save(irq_flags); + trusty_irq_disable_irqset(is, this_cpu_ptr(is->percpu_irqs)); + local_irq_restore(irq_flags); + + return 0; +} + +static int trusty_irq_create_irq_mapping(struct trusty_irq_state *is, int irq) +{ + int ret; + int index; + u32 irq_pos; + u32 templ_idx; + u32 range_base; + u32 range_end; + struct of_phandle_args oirq; + + /* check if "interrupt-ranges" property is present */ + if (!of_find_property(is->dev->of_node, "interrupt-ranges", NULL)) { + /* fallback to old behavior to be backward compatible with + * systems that do not need IRQ domains. + */ + return irq; + } + + /* find irq range */ + for (index = 0;; index += 3) { + ret = of_property_read_u32_index(is->dev->of_node, + "interrupt-ranges", index, + &range_base); + if (ret) + return ret; + + ret = of_property_read_u32_index(is->dev->of_node, + "interrupt-ranges", index + 1, + &range_end); + if (ret) + return ret; + + if (irq >= range_base && irq <= range_end) + break; + } + + /* read the rest of range entry: template index and irq_pos */ + ret = of_property_read_u32_index(is->dev->of_node, "interrupt-ranges", + index + 2, &templ_idx); + if (ret) + return ret; + + /* read irq template */ + ret = of_parse_phandle_with_args(is->dev->of_node, + "interrupt-templates", + "#interrupt-cells", templ_idx, &oirq); + if (ret) + return ret; + + WARN_ON(!oirq.np); + WARN_ON(!oirq.args_count); + + /* + * An IRQ template is a non empty array of u32 values describing group + * of interrupts having common properties. The u32 entry with index + * zero contains the position of irq_id in interrupt specifier array + * followed by data representing interrupt specifier array with irq id + * field omitted, so to convert irq template to interrupt specifier + * array we have to move down one slot the first irq_pos entries and + * replace the resulting gap with real irq id. + */ + irq_pos = oirq.args[0]; + + if (irq_pos >= oirq.args_count) { + dev_err(is->dev, "irq pos is out of range: %d\n", irq_pos); + return -EINVAL; + } + + for (index = 1; index <= irq_pos; index++) + oirq.args[index - 1] = oirq.args[index]; + + oirq.args[irq_pos] = irq - range_base; + + ret = irq_create_of_mapping(&oirq); + + return (!ret) ? -EINVAL : ret; +} + +static int trusty_irq_init_normal_irq(struct trusty_irq_state *is, int tirq) +{ + int ret; + int irq; + unsigned long irq_flags; + struct trusty_irq *trusty_irq; + + dev_dbg(is->dev, "%s: irq %d\n", __func__, tirq); + + irq = trusty_irq_create_irq_mapping(is, tirq); + if (irq < 0) { + dev_err(is->dev, "trusty_irq_create_irq_mapping failed (%d)\n", + irq); + return irq; + } + + trusty_irq = kzalloc(sizeof(*trusty_irq), GFP_KERNEL); + if (!trusty_irq) + return -ENOMEM; + + trusty_irq->is = is; + trusty_irq->irq = irq; + trusty_irq->enable = true; + + spin_lock_irqsave(&is->normal_irqs_lock, irq_flags); + hlist_add_head(&trusty_irq->node, &is->normal_irqs.inactive); + spin_unlock_irqrestore(&is->normal_irqs_lock, irq_flags); + + ret = request_irq(irq, trusty_irq_handler, IRQF_NO_THREAD, "trusty", + trusty_irq); + if (ret) { + dev_err(is->dev, "request_irq failed %d\n", ret); + goto err_request_irq; + } + return 0; + +err_request_irq: + spin_lock_irqsave(&is->normal_irqs_lock, irq_flags); + hlist_del(&trusty_irq->node); + spin_unlock_irqrestore(&is->normal_irqs_lock, irq_flags); + kfree(trusty_irq); + return ret; +} + +static int trusty_irq_init_per_cpu_irq(struct trusty_irq_state *is, int tirq) +{ + int ret; + int irq; + unsigned int cpu; + struct trusty_irq __percpu *trusty_irq_handler_data; + + dev_dbg(is->dev, "%s: irq %d\n", __func__, tirq); + + irq = trusty_irq_create_irq_mapping(is, tirq); + if (irq <= 0) { + dev_err(is->dev, "trusty_irq_create_irq_mapping failed (%d)\n", + irq); + return irq; + } + + trusty_irq_handler_data = alloc_percpu(struct trusty_irq); + if (!trusty_irq_handler_data) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + struct trusty_irq *trusty_irq; + struct trusty_irq_irqset *irqset; + + trusty_irq = per_cpu_ptr(trusty_irq_handler_data, cpu); + irqset = per_cpu_ptr(is->percpu_irqs, cpu); + + trusty_irq->is = is; + hlist_add_head(&trusty_irq->node, &irqset->inactive); + trusty_irq->irq = irq; + trusty_irq->percpu = true; + trusty_irq->percpu_ptr = trusty_irq_handler_data; + } + + ret = request_percpu_irq(irq, trusty_irq_handler, "trusty", + trusty_irq_handler_data); + if (ret) { + dev_err(is->dev, "request_percpu_irq failed %d\n", ret); + goto err_request_percpu_irq; + } + + return 0; + +err_request_percpu_irq: + for_each_possible_cpu(cpu) { + struct trusty_irq *trusty_irq; + + trusty_irq = per_cpu_ptr(trusty_irq_handler_data, cpu); + hlist_del(&trusty_irq->node); + } + + free_percpu(trusty_irq_handler_data); + return ret; +} + +static int trusty_smc_get_next_irq(struct trusty_irq_state *is, + unsigned long min_irq, bool per_cpu) +{ + return trusty_fast_call32(is->trusty_dev, SMC_FC_GET_NEXT_IRQ, min_irq, + per_cpu, 0); +} + +static int trusty_irq_init_one(struct trusty_irq_state *is, int irq, + bool per_cpu) +{ + int ret; + + irq = trusty_smc_get_next_irq(is, irq, per_cpu); + if (irq < 0) + return irq; + + if (per_cpu) + ret = trusty_irq_init_per_cpu_irq(is, irq); + else + ret = trusty_irq_init_normal_irq(is, irq); + + if (ret) { + dev_warn(is->dev, + "failed to initialize irq %d, irq will be ignored\n", + irq); + } + + return irq + 1; +} + +static void trusty_irq_free_irqs(struct trusty_irq_state *is) +{ + struct trusty_irq *irq; + struct hlist_node *n; + unsigned int cpu; + + hlist_for_each_entry_safe(irq, n, &is->normal_irqs.inactive, node) { + dev_dbg(is->dev, "%s: irq %d\n", __func__, irq->irq); + free_irq(irq->irq, irq); + hlist_del(&irq->node); + kfree(irq); + } + hlist_for_each_entry_safe( + irq, n, &this_cpu_ptr(is->percpu_irqs)->inactive, node) { + struct trusty_irq __percpu *trusty_irq_handler_data; + + dev_dbg(is->dev, "%s: percpu irq %d\n", __func__, irq->irq); + trusty_irq_handler_data = irq->percpu_ptr; + free_percpu_irq(irq->irq, trusty_irq_handler_data); + for_each_possible_cpu(cpu) { + struct trusty_irq *irq_tmp; + + irq_tmp = per_cpu_ptr(trusty_irq_handler_data, cpu); + hlist_del(&irq_tmp->node); + } + free_percpu(trusty_irq_handler_data); + } +} + +static int trusty_irq_probe(struct platform_device *pdev) +{ + int ret; + int irq; + unsigned long irq_flags; + struct trusty_irq_state *is; + + dev_dbg(&pdev->dev, "%s\n", __func__); + + is = kzalloc(sizeof(*is), GFP_KERNEL); + if (!is) { + ret = -ENOMEM; + goto err_alloc_is; + } + + is->dev = &pdev->dev; + is->trusty_dev = is->dev->parent; + spin_lock_init(&is->normal_irqs_lock); + is->percpu_irqs = alloc_percpu(struct trusty_irq_irqset); + if (!is->percpu_irqs) { + ret = -ENOMEM; + goto err_alloc_pending_percpu_irqs; + } + + platform_set_drvdata(pdev, is); + + is->trusty_call_notifier.notifier_call = trusty_irq_call_notify; + ret = trusty_call_notifier_register(is->trusty_dev, + &is->trusty_call_notifier); + if (ret) { + dev_err(&pdev->dev, + "failed to register trusty call notifier\n"); + goto err_trusty_call_notifier_register; + } + + for (irq = 0; irq >= 0;) + irq = trusty_irq_init_one(is, irq, true); + for (irq = 0; irq >= 0;) + irq = trusty_irq_init_one(is, irq, false); + + ret = cpuhp_state_add_instance(trusty_irq_cpuhp_slot, &is->cpuhp_node); + if (ret < 0) { + dev_err(&pdev->dev, "cpuhp_state_add_instance failed %d\n", + ret); + goto err_add_cpuhp_instance; + } + + return 0; + +err_add_cpuhp_instance: + spin_lock_irqsave(&is->normal_irqs_lock, irq_flags); + trusty_irq_disable_irqset(is, &is->normal_irqs); + spin_unlock_irqrestore(&is->normal_irqs_lock, irq_flags); + trusty_irq_free_irqs(is); + trusty_call_notifier_unregister(is->trusty_dev, + &is->trusty_call_notifier); +err_trusty_call_notifier_register: + free_percpu(is->percpu_irqs); +err_alloc_pending_percpu_irqs: + kfree(is); +err_alloc_is: + return ret; +} + +static int trusty_irq_remove(struct platform_device *pdev) +{ + int ret; + unsigned long irq_flags; + struct trusty_irq_state *is = platform_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "%s\n", __func__); + + ret = cpuhp_state_remove_instance(trusty_irq_cpuhp_slot, + &is->cpuhp_node); + if (WARN_ON(ret)) + return ret; + + spin_lock_irqsave(&is->normal_irqs_lock, irq_flags); + trusty_irq_disable_irqset(is, &is->normal_irqs); + spin_unlock_irqrestore(&is->normal_irqs_lock, irq_flags); + + trusty_irq_free_irqs(is); + + trusty_call_notifier_unregister(is->trusty_dev, + &is->trusty_call_notifier); + free_percpu(is->percpu_irqs); + kfree(is); + + return 0; +} + +static const struct of_device_id trusty_test_of_match[] = { + { + .compatible = "android,trusty-irq-v1", + }, + {}, +}; + +static struct platform_driver trusty_irq_driver = { + .probe = trusty_irq_probe, + .remove = trusty_irq_remove, + .driver = { + .name = "trusty-irq", + .owner = THIS_MODULE, + .of_match_table = trusty_test_of_match, + }, +}; + +static int __init trusty_irq_driver_init(void) +{ + int ret; + + /* allocate dynamic cpuhp state slot */ + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "trusty-irq:cpu:online", + trusty_irq_cpu_up, trusty_irq_cpu_down); + if (ret < 0) + return ret; + trusty_irq_cpuhp_slot = ret; + + /* Register platform driver */ + ret = platform_driver_register(&trusty_irq_driver); + if (ret < 0) + goto err_driver_register; + + return ret; + +err_driver_register: + /* undo cpuhp slot allocation */ + cpuhp_remove_multi_state(trusty_irq_cpuhp_slot); + trusty_irq_cpuhp_slot = -1; + + return ret; +} + +static void __exit trusty_irq_driver_exit(void) +{ + platform_driver_unregister(&trusty_irq_driver); + cpuhp_remove_multi_state(trusty_irq_cpuhp_slot); + trusty_irq_cpuhp_slot = -1; +} + +module_init(trusty_irq_driver_init); +module_exit(trusty_irq_driver_exit); diff --git a/drivers/trusty/trusty-link-shbuf.c b/drivers/trusty/trusty-link-shbuf.c new file mode 100644 index 000000000000..bbfa8e8bab27 --- /dev/null +++ b/drivers/trusty/trusty-link-shbuf.c @@ -0,0 +1,691 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "trusty-link-shbuf.h" + +#define MAX_LINK_SHBUF_DEV 4 +#define ENABLE_SHBUF_RAMCONSOLE (1) + +#if ENABLE_SHBUF_RAMCONSOLE +#define RAMCONSOLE_SIZE (64ul * 1024ul) // 64KB +#define RAMCONSOLE_OFFSET (sizeof(uint64_t)) // 64B +#endif + +static struct link_shbuf_data *link_shbuf_dev[MAX_LINK_SHBUF_DEV]; +static u32 link_shbuf_dev_num; +struct link_shbuf_data *gpriv; + +u32 trusty_virtio_devid = 0, trusty_virtio_vqid = 0; + +/* Sentinel values for indicating missing communication channels */ +#define NO_OUTGOING_IRQ (0) +#define NO_INCOMING_IRQ (-1) + +static bool link_shbuf_data_invariant(const struct link_shbuf_data *priv) +{ + if (!priv) + return false; + + if (!priv->base || (uintptr_t)priv->base % PAGE_SIZE != 0) + return false; + + if (resource_size(&priv->buffer) == 0) + return false; + + return true; +} + +struct link_shbuf_data *trusty_get_link_shbuf_device(u32 lsdidx) +{ + if (lsdidx >= MAX_LINK_SHBUF_DEV) + return NULL; + + return link_shbuf_dev[lsdidx]; +} + +s32 trusty_link_shbuf_recv(u32 lsdidx, ulong *out) +{ + ulong payload; + int ret; + struct link_shbuf_data *dev = trusty_get_link_shbuf_device(lsdidx); + + if (!dev) { + dev_err(dev->dev, "lsdidx %u invalid (should be < %u)\n", + lsdidx, link_shbuf_dev_num); + return -EINVAL; + } + + do { + ret = wait_event_interruptible_timeout(dev->virq_wq, + dev->virq_pending, + msecs_to_jiffies(30000)); + if (ret < 0) { + dev_err(dev->dev, + "wait failed ret %d virq_pending %u\n", ret, + dev->virq_pending); + return ret; + } else if (ret == 0) { + dev_err(dev->dev, + "wait timeout ret %d virq_pending %u\n", ret, + dev->virq_pending); + return -ETIMEDOUT; + } + } while (!xchg(&dev->virq_pending, 0)); + + /* Ensure all PEs see the latest payload. */ + smp_rmb(); + payload = atomic64_xchg(&dev->virq_payload, 0); + + if (out) + *out = payload; + + dev_dbg(dev->dev, "%s: virq %d hwirq %d payload 0x%lx\n", __func__, + dev->virq, dev->hwirq, payload); + + return 0; +} + +s32 trusty_link_shbuf_send(u32 lsdidx, ulong payload) +{ + okl4_error_t err; + struct link_shbuf_data *dev = trusty_get_link_shbuf_device(lsdidx); + + if (!dev) { + dev_err(dev->dev, "lsdidx %u invalid (should be < %u)\n", + lsdidx, link_shbuf_dev_num); + return -EINVAL; + } + + err = _okl4_sys_vinterrupt_raise(dev->virqline, payload); + if (err != OKL4_OK) { + dev_err(dev->dev, + "failed to raise virq %u err %u payload 0x%lx\n", + dev->virqline, err, payload); + return -EIO; + } + + dev_dbg(dev->dev, "%s: virqline %d payload 0x%lx\n", __func__, + dev->virqline, payload); + + return 0; +} + +static int shbuf_virq_show(struct seq_file *m, void *v) +{ + ulong out; + + trusty_link_shbuf_recv(0, &out); + seq_printf(m, "%lx\n", out); + return 0; +} + +ssize_t shbuf_virq_write(struct file *filp, const char __user *ubuf, + size_t size, loff_t *off) +{ + char kbuf[32]; + ulong payload; + + if (!size) + return 0; + if (!access_ok(VERIFY_READ, ubuf, size)) + return -EFAULT; + + if (size > sizeof(kbuf) - 1) + size = sizeof(kbuf) - 1; + + if (copy_from_user(kbuf, ubuf, size)) + return -EFAULT; + + kbuf[size] = '\0'; + + if (kstrtoul(kbuf, 0, &payload) == 0) { + dev_info(gpriv->dev, "shbuf_send payload 0x%lx\n", payload); + trusty_link_shbuf_send(0, payload); + } + + return size; +} + +static int shbuf_virq_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, shbuf_virq_show, NULL); +} + +static const struct file_operations shbuf_virq_fops = { + .open = shbuf_virq_open, + .read = seq_read, + .write = shbuf_virq_write, + .release = single_release, +}; + +static int shbuf_buffer_show(struct seq_file *m, void *v) +{ + struct link_shbuf_data *priv = m->private; +#if ENABLE_SHBUF_RAMCONSOLE + char *ramconsole_beg = NULL; + char *ramconsole_cur = NULL; + char *ramconsole_end = NULL; + + ramconsole_beg = priv->base; + ramconsole_cur = priv->base; + ramconsole_end = priv->base + RAMCONSOLE_SIZE; + + for (; ramconsole_cur < ramconsole_end; + ramconsole_cur += sizeof(uint64_t)) { + seq_printf(m, + "%08lx: %02x %02x %02x %02x %02x %02x %02x %02x\n", + ramconsole_cur - ramconsole_beg, + readb_relaxed(ramconsole_cur + 0), + readb_relaxed(ramconsole_cur + 1), + readb_relaxed(ramconsole_cur + 2), + readb_relaxed(ramconsole_cur + 3), + readb_relaxed(ramconsole_cur + 4), + readb_relaxed(ramconsole_cur + 5), + readb_relaxed(ramconsole_cur + 6), + readb_relaxed(ramconsole_cur + 7)); + } +#endif + + seq_printf(m, "%llx\n", readq_relaxed(priv->base)); + return 0; +} + +ssize_t shbuf_buffer_write(struct file *filp, const char __user *ubuf, + size_t size, loff_t *off) +{ + ulong offset; + void *ptr; + char kbuf[32]; + struct link_shbuf_data *priv = + ((struct seq_file *)filp->private_data)->private; + const uint64_t pattern = 0x11223344deadbeefULL; + + if (!size) + return 0; + if (!access_ok(VERIFY_READ, ubuf, size)) + return -EFAULT; + + if (size > sizeof(kbuf) - 1) + size = sizeof(kbuf) - 1; + + if (copy_from_user(kbuf, ubuf, size)) + return -EFAULT; + + kbuf[size] = '\0'; + + if (kstrtoul(kbuf, 0, &offset) == 0) { + if (offset > (RAMCONSOLE_SIZE - sizeof(uint64_t))) + offset = RAMCONSOLE_SIZE - sizeof(uint64_t); + ptr = (void *)((uintptr_t)priv->base + offset); + writeq_relaxed(pattern, ptr); + dev_info(gpriv->dev, "addr %p w:%llx r:%llx\n", ptr, pattern, + readq_relaxed(ptr)); + } + + return size; +} + +static int shbuf_buffer_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, shbuf_buffer_show, inode->i_private); +} + +static const struct file_operations shbuf_buffer_fops = { + .open = shbuf_buffer_open, + .read = seq_read, + .write = shbuf_buffer_write, + .release = single_release, +}; + +s32 trusty_link_shbuf_smc(u32 lsdidx, ulong r0, ulong r1, ulong r2, ulong r3) +{ + unsigned long ret = 0; + struct link_shbuf_data *dev = trusty_get_link_shbuf_device(lsdidx); + + trusty_link_shbuf_send(lsdidx, r0); + trusty_link_shbuf_recv(lsdidx, NULL); + trusty_link_shbuf_send(lsdidx, r1); + trusty_link_shbuf_recv(lsdidx, NULL); + trusty_link_shbuf_send(lsdidx, r2); + trusty_link_shbuf_recv(lsdidx, NULL); + trusty_link_shbuf_send(lsdidx, r3); + trusty_link_shbuf_recv(lsdidx, &ret); + + dev_dbg(dev->dev, "%s: 0x%lx 0x%lx 0x%lx 0x%lx done (0x%lx)\n", + __func__, r0, r1, r2, r3, ret); + + return ret; +} + +/* + * Interrupt handler. + * + * This function will be called when our link partner uses the ioctl on their + * shared memory device to send an outgoing interrupt. + */ +static irqreturn_t link_shbuf_irq_handler(int irq, void *data) +{ + u64 payload, old, new; + struct _okl4_sys_interrupt_get_payload_return _payload; + + /* Retrieve a pointer to our private data. */ + struct link_shbuf_data *priv = data; + + if (WARN_ON(!link_shbuf_data_invariant(priv))) + return IRQ_NONE; + + /* + * We should only ever be handling a single interrupt, and only if there + * was an incoming interrupt in the configuration. + */ + if (WARN_ON(priv->virq < 0 || priv->virq != irq)) + return IRQ_NONE; + + _payload = _okl4_sys_interrupt_get_payload(priv->hwirq); + payload = (u64)_payload.payload; + + dev_dbg(priv->dev, "irq %d payload %llx\n", irq, payload); + + if (payload == TRUSTY_PROBE_DEFER) { + trusty_probe_late(); + } else if ((payload >> 32) == SMC_NC_VDEV_KICK_VQ) { + trusty_virtio_devid = (u32)((payload & 0xFFFF0000) >> 16); + trusty_virtio_vqid = (u32)(payload & 0x0000FFFF); + trusty_notifier_call(); + } else { + /* + * At this point, it is possible the pending flag is already + * set. It is up to the user to synchronise their transmission + * and acknowledgement of interrupts. + */ + + /* atomic64_or which is not universally available. */ + do { + old = atomic64_read(&priv->virq_payload); + new = old | payload; + } while (atomic64_cmpxchg(&priv->virq_payload, old, new) != + old); + + priv->virq_pending = true; + /* Ensure all PEs see the latest payload/pending. */ + smp_wmb(); + wake_up_interruptible(&priv->virq_wq); + } + + return IRQ_HANDLED; +} + +static int link_shbuf_dev_compare(const void *lhs, const void *rhs) +{ + const struct link_shbuf_data *l = lhs; + const struct link_shbuf_data *r = rhs; + + return l->hwirq - r->hwirq; +} + +/* + * Discover and add a new shared-buffer link. + * + * In the following function, we are expecting to parse device tree entries + * looking like the following: + * + * hypervisor { + * ... + * interrupt-line@1d { + * compatible = "okl,microvisor-interrupt-line", + * "okl,microvisor-capability"; + * phandle = <0x7>; + * reg = <0x1d>; + * label = "foo_virqline"; + * }; + * ; + * + * foo@41003000 { + * compatible = "okl,microvisor-link-shbuf", + * "okl,microvisor-shared-memory"; + * phandle = <0xd>; + * reg = <0x0 0x41003000 0x2000>; + * label = "foo"; + * okl,rwx = <0x6>; + * okl,interrupt-line = <0x7>; + * interrupts = <0x0 0x4 0x1>; + * interrupt-parent = <0x1>; + * }; + */ +static int trusty_link_shbuf_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *node; + struct link_shbuf_data *priv; + const char *name; + u32 permissions; + struct dentry *debugfs_root; + + node = pdev->dev.of_node; + + if (!node) + return -ENODEV; + + ret = of_property_read_string(node, "label", &name); + if (ret < 0) { + dev_err(&pdev->dev, "failed to read label\n"); + return -ENODEV; + } + + if (strncmp(name, "mlvm_shm", strlen("mlvm_shm"))) { + dev_info(&pdev->dev, "label mismatch, expect %s was %s\n", + "mlvm_shm", name); + return -ENODEV; + } + + if (link_shbuf_dev_num >= MAX_LINK_SHBUF_DEV) { + dev_err(&pdev->dev, + "link-shbuf devices > MAX_LINK_SHBUF_DEV\n"); + return -ENOMEM; + } + + if (!gpriv) + gpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + priv = gpriv; + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + + init_waitqueue_head(&priv->virq_wq); + priv->virq_pending = false; + + /* Retrieve information about the shared memory region. */ + ret = of_address_to_resource(node, 0, &priv->buffer); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get buffer address\n"); + goto err_free_irq; + } + + /* + * We expect the Elfweaver to have validated that we have a non-NULL, + * page-aligned region. + */ + if (WARN_ON(priv->buffer.start == 0) || + WARN_ON(resource_size(&priv->buffer) % PAGE_SIZE != 0)) + goto err_free_irq; + + if (!devm_request_mem_region(&pdev->dev, priv->buffer.start, + resource_size(&priv->buffer), + dev_name(&pdev->dev))) { + ret = -EINVAL; + dev_err(&pdev->dev, + "failed to request_mem_region start %llx size %llx\n", + priv->buffer.start, resource_size(&priv->buffer)); + goto err_free_irq; + } + + priv->base = devm_memremap(&pdev->dev, priv->buffer.start, + resource_size(&priv->buffer), MEMREMAP_WB); + if (!priv->base) { + dev_err(&pdev->dev, + "failed to memremap, start %llx size %llx\n", + priv->buffer.start, resource_size(&priv->buffer)); + goto err_release_region; + } + +#if ENABLE_SHBUF_RAMCONSOLE + priv->ramconsole_size = RAMCONSOLE_SIZE; +#endif + + dev_info(&pdev->dev, + "shbuf pa %llx size %llx memremap_va 0x%lx rc_sz %zx\n", + priv->buffer.start, resource_size(&priv->buffer), + (uintptr_t)priv->base, priv->ramconsole_size); + + /* Read the permissions of the shared memory region. */ + ret = of_property_read_u32(node, "okl,rwx", &permissions); + if (ret < 0) { + dev_err(&pdev->dev, + "failed to read shared memory permissions\n"); + goto err_unmap_dev; + } + + if (permissions & ~(0007)) { + ret = -EINVAL; + dev_err(&pdev->dev, "invalid shared memory permissions %u\n", + permissions); + goto err_unmap_dev; + } + + priv->permissions = ((permissions & 0004) ? FMODE_READ : 0) | + ((permissions & 0002) ? FMODE_WRITE : 0) | + ((permissions & 0001) ? FMODE_EXEC : 0); + if (WARN_ON(priv->permissions == 0)) { + ret = -EINVAL; + dev_err(&pdev->dev, "shared memory permissions is 0\n"); + goto err_unmap_dev; + } + + debugfs_root = debugfs_create_dir(dev_name(&pdev->dev), NULL); + if (!IS_ERR_OR_NULL(debugfs_root)) { + debugfs_create_file("shbuf_virq", 0600, debugfs_root, NULL, + &shbuf_virq_fops); + debugfs_create_file("shbuf_buffer", 0600, debugfs_root, priv, + &shbuf_buffer_fops); + } else { + dev_err(&pdev->dev, "debugfs_create_dir '%s' failed ret %ld\n", + dev_name(&pdev->dev), PTR_ERR(debugfs_root)); + } + + dev_set_drvdata(&pdev->dev, priv); + + link_shbuf_dev[link_shbuf_dev_num++] = priv; + sort(link_shbuf_dev, link_shbuf_dev_num, sizeof(u64), + &link_shbuf_dev_compare, NULL); + + dev_info(&pdev->dev, "current %d link-shbuf devices registered.\n", + link_shbuf_dev_num); + + for (i = 0; i < link_shbuf_dev_num; i++) { + dev_info( + &pdev->dev, + " link_shbuf_dev[%d] virq %d hwirq %d virqline %d base 0x%lx remap_pa 0x%llx\n", + i, link_shbuf_dev[i]->virq, link_shbuf_dev[i]->hwirq, + link_shbuf_dev[i]->virqline, + (uintptr_t)link_shbuf_dev[i]->base, + page_to_phys(virt_to_page(link_shbuf_dev[i]->base))); + } + + return 0; + +err_unmap_dev: + dev_info(&pdev->dev, "%s: devm_memunmap %lx\n", __func__, + (uintptr_t)priv->base); + devm_memunmap(&pdev->dev, priv->base); +err_release_region: + devm_release_mem_region(&pdev->dev, priv->buffer.start, + resource_size(&priv->buffer)); +err_free_irq: + if (priv->virq != NO_INCOMING_IRQ) + devm_free_irq(&pdev->dev, priv->virq, priv); + devm_kfree(&pdev->dev, priv); + return ret; +} + +static int trusty_link_shbuf_remove(struct platform_device *pdev) +{ + struct link_shbuf_data *priv; + + priv = dev_get_drvdata(&pdev->dev); + WARN_ON(!link_shbuf_data_invariant(priv)); + + /* + * None of the following is strictly required, as these are all managed + * resources, but we clean it up anyway for clarity. + */ + + dev_info(&pdev->dev, "%s: devm_memunmap %lx\n", __func__, + (uintptr_t)priv->base); + + devm_memunmap(&pdev->dev, priv->base); + + devm_release_mem_region(&pdev->dev, priv->buffer.start, + resource_size(&priv->buffer)); + + if (priv->virq != NO_INCOMING_IRQ) + devm_free_irq(&pdev->dev, priv->virq, priv); + + devm_kfree(&pdev->dev, priv); + + return 0; +} + +static const struct of_device_id trusty_link_shbuf_match[] = { + { + .compatible = "okl,microvisor-shared-memory", + }, + {}, +}; + +static struct platform_driver trusty_link_shbuf_driver = { + .driver = { + .name = "trusty-link-shbuf", + .owner = THIS_MODULE, + .of_match_table = trusty_link_shbuf_match, + }, + .probe = trusty_link_shbuf_probe, + .remove = trusty_link_shbuf_remove, +}; + +/* Maximum number of minor device numbers */ +enum { + MAX_MINOR = 1 << MINORBITS, +}; + +static int __init trusty_link_shbuf_init(void) +{ + return platform_driver_register(&trusty_link_shbuf_driver); +} + +static void __exit trusty_link_shbuf_exit(void) +{ + platform_driver_unregister(&trusty_link_shbuf_driver); +} + +arch_initcall(trusty_link_shbuf_init); +module_exit(trusty_link_shbuf_exit); + +static int fifo_vipc_probe(struct platform_device *pdev) +{ + int ret; + struct device_node *node; + struct link_shbuf_data *priv; + const char *name; + struct irq_desc *desc; + + node = pdev->dev.of_node; + + if (!node) + return -ENODEV; + + ret = of_property_read_string(node, "label", &name); + if (ret < 0) { + dev_err(&pdev->dev, "failed to read label\n"); + return -ENODEV; + } + + priv = gpriv; + if (!priv) + return -ENOMEM; + + ret = of_property_read_u32(node, "reg", &priv->virqline); + if (ret < 0 || priv->virqline == OKL4_KCAP_INVALID) { + dev_err(&pdev->dev, + "failed to get \"reg\" of interrupt-line\n"); + return -ENODEV; + } + + /* Retrieve the incoming vIRQ number. Again, this is configurable and we + * anticipate that it may not exist. + */ + priv->virq = platform_get_irq(pdev, 0); + if (priv->virq < 0) { + dev_err(&pdev->dev, "failed to get platform irq\n"); + return -EINVAL; + } + + desc = irq_to_desc(priv->virq); + if (!desc) { + dev_err(&pdev->dev, "failed to get irq_desc\n"); + return -EINVAL; + } + priv->hwirq = desc->irq_data.hwirq; + + /* If we have a valid incoming vIRQ, register to handle it. */ + ret = devm_request_irq(&pdev->dev, priv->virq, link_shbuf_irq_handler, + 0, dev_name(&pdev->dev), priv); + if (ret < 0) { + dev_err(&pdev->dev, "failed to request_irq\n"); + return -EINVAL; + } + + dev_info(&pdev->dev, "%s: virq %d hwirq %d virqline %d\n", __func__, + priv->virq, priv->hwirq, priv->virqline); + +#if ENABLE_SHBUF_RAMCONSOLE + WARN_ON(!priv->base); + /* Notify HEE we're ready for virq communication */ + writeq_relaxed(TRUSTY_PROBE_DEFER, priv->base); + dev_info(&pdev->dev, "%s: TRUSTY_PROBE_DEFER %llx\n", __func__, + readq_relaxed(priv->base)); +#endif + return 0; +} + +static const struct of_device_id fifo_vipc_match[] = { + { + .compatible = "qcom,ipcr-fifo-xprt", + }, + {}, +}; + +static struct platform_driver fifo_vipc_driver = { + .driver = { + .name = "trusty-ipcr-fifo-xprt", + .owner = THIS_MODULE, + .of_match_table = fifo_vipc_match, + }, + .probe = fifo_vipc_probe, +}; + +static int __init fifo_vipc_init(void) +{ + return platform_driver_register(&fifo_vipc_driver); +} + +module_init(fifo_vipc_init); diff --git a/drivers/trusty/trusty-link-shbuf.h b/drivers/trusty/trusty-link-shbuf.h new file mode 100644 index 000000000000..8ffc20206bea --- /dev/null +++ b/drivers/trusty/trusty-link-shbuf.h @@ -0,0 +1,58 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _TRUSTY_LINK_SHBUF_H_ +#define _TRUSTY_LINK_SHBUF_H_ + +#include +#include + +/* Private data for this driver */ +struct link_shbuf_data { + /* Outgoing vIRQ */ + u32 virqline; + + /* Incoming vIRQ */ + int virq; + int hwirq; + atomic64_t virq_payload; + bool virq_pending; + wait_queue_head_t virq_wq; + + /* Shared memory region */ + void *base; + fmode_t permissions; + struct resource buffer; + size_t ramconsole_size; + + struct device *dev; +#ifdef CONFIG_TRUSTY_VIRQ_SIMULATION + void __iomem *gicd_base; +#endif +}; + +#ifdef CONFIG_TRUSTY_VIRQ_SIMULATION +/* Enabled only in QEMU environment. */ +extern int gic_set_affinity_possible(struct irq_data *d, + const struct cpumask *mask_val, + bool force); +#endif + +s32 trusty_link_shbuf_recv(u32 lsdidx, ulong *out); +s32 trusty_link_shbuf_send(u32 lsdidx, ulong payload); +s32 trusty_link_shbuf_smc(u32 lsdidx, ulong r0, ulong r1, ulong r2, ulong r3); +struct link_shbuf_data *trusty_get_link_shbuf_device(u32 lsdidx); + +#endif /* _TRUSTY_LINK_SHBUF_H_ */ diff --git a/drivers/trusty/trusty-log.c b/drivers/trusty/trusty-log.c new file mode 100644 index 000000000000..aef4718cdcb1 --- /dev/null +++ b/drivers/trusty/trusty-log.c @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2015 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "trusty-log.h" + +#define TRUSTY_LOG_SIZE (PAGE_SIZE * 2) +#define TRUSTY_LINE_BUFFER_SIZE 256 + +struct trusty_log_state { + struct device *dev; + struct device *trusty_dev; + + /* + * This lock is here to ensure only one consumer will read + * from the log ring buffer at a time. + */ + spinlock_t lock; + struct log_rb *log; + uint32_t get; + + struct page *log_pages; + + struct notifier_block call_notifier; + struct notifier_block panic_notifier; + char line_buffer[TRUSTY_LINE_BUFFER_SIZE]; +}; + +static int log_read_line(struct trusty_log_state *s, int put, int get) +{ + struct log_rb *log = s->log; + int i; + char c = '\0'; + size_t max_to_read = + min((size_t)(put - get), sizeof(s->line_buffer) - 1); + size_t mask = log->sz - 1; + + for (i = 0; i < max_to_read && c != '\n';) + s->line_buffer[i++] = c = log->data[get++ & mask]; + s->line_buffer[i] = '\0'; + + return i; +} + +static void trusty_dump_logs(struct trusty_log_state *s) +{ + struct log_rb *log = s->log; + uint32_t get, put, alloc; + int read_chars; + + BUG_ON(!is_power_of_2(log->sz)); + + /* + * For this ring buffer, at any given point, alloc >= put >= get. + * The producer side of the buffer is not locked, so the put and alloc + * pointers must be read in a defined order (put before alloc) so + * that the above condition is maintained. A read barrier is needed + * to make sure the hardware and compiler keep the reads ordered. + */ + get = s->get; + while ((put = log->put) != get) { + /* Make sure that the read of put occurs before the read of log data */ + rmb(); + + /* Read a line from the log */ + read_chars = log_read_line(s, put, get); + + /* Force the loads from log_read_line to complete. */ + rmb(); + alloc = log->alloc; + + /* + * Discard the line that was just read if the data could + * have been corrupted by the producer. + */ + if (alloc - get > log->sz) { + pr_err("trusty: log overflow."); + get = alloc - log->sz; + continue; + } + pr_info("trusty: %s", s->line_buffer); + get += read_chars; + } + s->get = get; +} + +static int trusty_log_call_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct trusty_log_state *s; + unsigned long flags; + + if (action != TRUSTY_CALL_RETURNED) + return NOTIFY_DONE; + + s = container_of(nb, struct trusty_log_state, call_notifier); + spin_lock_irqsave(&s->lock, flags); + trusty_dump_logs(s); + spin_unlock_irqrestore(&s->lock, flags); + return NOTIFY_OK; +} + +static int trusty_log_panic_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct trusty_log_state *s; + + /* + * Don't grab the spin lock to hold up the panic notifier, even + * though this is racy. + */ + s = container_of(nb, struct trusty_log_state, panic_notifier); + pr_info("trusty-log panic notifier - trusty version %s", + trusty_version_str_get(s->trusty_dev)); + trusty_dump_logs(s); + return NOTIFY_OK; +} + +static bool trusty_supports_logging(struct device *device) +{ + int result; + + result = trusty_std_call32(device, SMC_SC_SHARED_LOG_VERSION, + TRUSTY_LOG_API_VERSION, 0, 0); + if (result == SM_ERR_UNDEFINED_SMC) { + pr_info("trusty-log not supported on secure side.\n"); + return false; + } else if (result < 0) { + pr_err("trusty std call (SMC_SC_SHARED_LOG_VERSION) failed: %d\n", + result); + return false; + } + + if (result == TRUSTY_LOG_API_VERSION) { + return true; + } else { + pr_info("trusty-log unsupported api version: %d, supported: %d\n", + result, TRUSTY_LOG_API_VERSION); + return false; + } +} + +static int trusty_log_probe(struct platform_device *pdev) +{ + struct trusty_log_state *s; + int result; + phys_addr_t pa; + + dev_dbg(&pdev->dev, "%s\n", __func__); + if (!trusty_supports_logging(pdev->dev.parent)) { + return -ENXIO; + } + + s = kzalloc(sizeof(*s), GFP_KERNEL); + if (!s) { + result = -ENOMEM; + goto error_alloc_state; + } + + spin_lock_init(&s->lock); + s->dev = &pdev->dev; + s->trusty_dev = s->dev->parent; + s->get = 0; + + s->log = trusty_shm_alloc(TRUSTY_LOG_SIZE, GFP_KERNEL | __GFP_ZERO); + if (!s->log) { + result = -ENOMEM; + goto error_alloc_log; + } + s->log_pages = virt_to_page(s->log); + + pa = trusty_shm_virt_to_phys(s->log); + result = trusty_std_call32(s->trusty_dev, SMC_SC_SHARED_LOG_ADD, + (u32)(pa), (u32)(pa >> 32), TRUSTY_LOG_SIZE); + if (result < 0) { + pr_err("trusty std call (SMC_SC_SHARED_LOG_ADD) failed: %d %pa\n", + result, &pa); + goto error_std_call; + } + + s->call_notifier.notifier_call = trusty_log_call_notify; + result = + trusty_call_notifier_register(s->trusty_dev, &s->call_notifier); + if (result < 0) { + dev_err(&pdev->dev, + "failed to register trusty call notifier\n"); + goto error_call_notifier; + } + + s->panic_notifier.notifier_call = trusty_log_panic_notify; + result = atomic_notifier_chain_register(&panic_notifier_list, + &s->panic_notifier); + if (result < 0) { + dev_err(&pdev->dev, "failed to register panic notifier\n"); + goto error_panic_notifier; + } + platform_set_drvdata(pdev, s); + + return 0; + +error_panic_notifier: + trusty_call_notifier_unregister(s->trusty_dev, &s->call_notifier); +error_call_notifier: + trusty_std_call32(s->trusty_dev, SMC_SC_SHARED_LOG_RM, (u32)pa, + (u32)(pa >> 32), 0); +error_std_call: + trusty_shm_free(s->log, TRUSTY_LOG_SIZE); +error_alloc_log: + kfree(s); +error_alloc_state: + return result; +} + +static int trusty_log_remove(struct platform_device *pdev) +{ + int result; + struct trusty_log_state *s = platform_get_drvdata(pdev); + phys_addr_t pa = page_to_phys(s->log_pages); + + dev_dbg(&pdev->dev, "%s\n", __func__); + + atomic_notifier_chain_unregister(&panic_notifier_list, + &s->panic_notifier); + trusty_call_notifier_unregister(s->trusty_dev, &s->call_notifier); + + result = trusty_std_call32(s->trusty_dev, SMC_SC_SHARED_LOG_RM, (u32)pa, + (u32)(pa >> 32), 0); + if (result) { + pr_err("trusty std call (SMC_SC_SHARED_LOG_RM) failed: %d\n", + result); + } + trusty_shm_free(s->log, TRUSTY_LOG_SIZE); + kfree(s); + + return 0; +} + +static const struct of_device_id trusty_test_of_match[] = { + { + .compatible = "android,trusty-log-v1", + }, + {}, +}; + +static struct platform_driver trusty_log_driver = { + .probe = trusty_log_probe, + .remove = trusty_log_remove, + .driver = { + .name = "trusty-log", + .owner = THIS_MODULE, + .of_match_table = trusty_test_of_match, + }, +}; + +module_platform_driver(trusty_log_driver); diff --git a/drivers/trusty/trusty-log.h b/drivers/trusty/trusty-log.h new file mode 100644 index 000000000000..bcb1ad32028e --- /dev/null +++ b/drivers/trusty/trusty-log.h @@ -0,0 +1,17 @@ +#ifndef _TRUSTY_LOG_H_ +#define _TRUSTY_LOG_H_ + +/* + * Ring buffer that supports one secure producer thread and one + * linux side consumer thread. + */ +struct log_rb { + volatile uint32_t alloc; + volatile uint32_t put; + uint32_t sz; + volatile char data[0]; +} __packed; + +#define TRUSTY_LOG_API_VERSION 1 + +#endif diff --git a/drivers/trusty/trusty-mem.c b/drivers/trusty/trusty-mem.c new file mode 100644 index 000000000000..5653888d4877 --- /dev/null +++ b/drivers/trusty/trusty-mem.c @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2015-2018 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#if defined(CONFIG_ARM64) +static int encode_page_inf(struct ns_mem_page_info *inf, uint64_t pte, + pgprot_t pgprot, bool writable) +{ + uint64_t mair; + uint attr_index = (pgprot_val(pgprot) & PTE_ATTRINDX_MASK) >> 2; + + asm("mrs %0, mair_el1\n" : "=&r"(mair)); + mair = (mair >> (attr_index * 8)) & 0xff; + + /* add other attributes */ + pte |= pgprot_val(pgprot); + + /* reset RDONLY flag if needed */ + if (writable) + pte &= ~PTE_RDONLY; + + inf->attr = (pte & 0x0000FFFFFFFFFFFFull) | (mair << 48); + return 0; +} +#elif defined(CONFIG_ARM_LPAE) +static int encode_page_inf(struct ns_mem_page_info *inf, uint64_t pte, + pgprot_t pgprot, bool writable) +{ + u32 mair; + uint attr_index = ((pgprot_val(pgprot) & L_PTE_MT_MASK) >> 2); + + if (attr_index >= 4) { + attr_index -= 4; + asm volatile("mrc p15, 0, %0, c10, c2, 1\n" : "=&r"(mair)); + } else { + asm volatile("mrc p15, 0, %0, c10, c2, 0\n" : "=&r"(mair)); + } + mair = (mair >> (attr_index * 8)) & 0xff; + + /* add other attributes */ + pte |= pgprot_val(pgprot); + + /* reset RDONLY flag if needed */ + if (writable) + pte &= ~(1 << 7); + + inf->attr = (pte & 0x0000FFFFFFFFFFFFull) | ((uint64_t)mair << 48); + return 0; +} +#elif defined(CONFIG_ARM) +static int encode_page_inf(struct ns_mem_page_info *inf, uint64_t pte, + pgprot_t pgprot, bool writable) +{ + u32 mair; + + /* check memory type */ + switch (pgprot_val(pgprot) & L_PTE_MT_MASK) { + case L_PTE_MT_WRITEALLOC: + /* Normal: write back write allocate */ + mair = 0xFF; + break; + + case L_PTE_MT_BUFFERABLE: + /* Normal: non-cacheble */ + mair = 0x44; + break; + + case L_PTE_MT_WRITEBACK: + /* Normal: writeback, read allocate */ + mair = 0xEE; + break; + + case L_PTE_MT_WRITETHROUGH: + /* Normal: write through */ + mair = 0xAA; + break; + + case L_PTE_MT_UNCACHED: + /* strongly ordered */ + mair = 0x00; + break; + + case L_PTE_MT_DEV_SHARED: + case L_PTE_MT_DEV_NONSHARED: + /* device */ + mair = 0x04; + break; + + default: + return -EINVAL; + } + + /* add other attributes */ + if (pgprot_val(pgprot) & L_PTE_USER) + pte |= (1 << 6); + if (!writable && pgprot_val(pgprot) & L_PTE_RDONLY) + pte |= (1 << 7); + if (pgprot_val(pgprot) & L_PTE_SHARED) + pte |= (3 << 8); /* inner sharable */ + + inf->attr = (pte & 0x0000FFFFFFFFFFFFull) | ((uint64_t)mair << 48); + return 0; +} +#else +static int encode_page_inf(struct ns_mem_page_info *inf, uint64_t pte, + pgprot_t pgprot, bool writable) +{ + return -EINVAL; +} +#endif + +int trusty_encode_page_info(struct ns_mem_page_info *inf, struct page *page, + pgprot_t pgprot, bool writable) +{ + if (!inf || !page) + return -EINVAL; + + return encode_page_inf(inf, (uint64_t)page_to_phys(page), pgprot, + writable); +} + +int trusty_call32_mem_buf(struct device *dev, u32 smcnr, struct page *page, + u32 size, pgprot_t pgprot, bool writable) +{ + int ret; + struct ns_mem_page_info pg_inf; + + if (!dev || !page) + return -EINVAL; + + ret = trusty_encode_page_info(&pg_inf, page, pgprot, writable); + if (ret) + return ret; + + if (SMC_IS_FASTCALL(smcnr)) { + return trusty_fast_call32(dev, smcnr, (u32)pg_inf.attr, + (u32)(pg_inf.attr >> 32), size); + } else { + return trusty_std_call32(dev, smcnr, (u32)pg_inf.attr, + (u32)(pg_inf.attr >> 32), size); + } +} diff --git a/drivers/trusty/trusty-shm.c b/drivers/trusty/trusty-shm.c new file mode 100644 index 000000000000..595de5c56e7e --- /dev/null +++ b/drivers/trusty/trusty-shm.c @@ -0,0 +1,209 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include "trusty-link-shbuf.h" + +static struct gen_pool *gpool; +static struct device *gdev; /* trusty dev */ + +struct trusty_shm_ops { + void *(*alloc)(size_t size, gfp_t gfp_mask); /* alloc_pages_exact */ + void (*free)(void *vaddr, size_t size); /* free_pages_exact */ + /* arch/arm64/include/asm/memory.h */ + void *(*phys_to_virt)(phys_addr_t x); + phys_addr_t (*virt_to_phys)(const volatile void *x); +}; + +static void *default_shm_alloc(size_t sz, gfp_t gfp) +{ + return alloc_pages_exact(sz, gfp); +} + +static void default_shm_free(void *va, size_t sz) +{ + free_pages_exact(va, sz); +} + +static void *gpool_shm_alloc(size_t size, gfp_t gfp) +{ + unsigned long vaddr; + + BUG_ON(!gpool); + BUG_ON(!size); + + vaddr = gen_pool_alloc(gpool, size); + if (!vaddr) { + dev_err(gdev, + "%s: alloc shm failed, request 0x%zx avail 0x%zx\n", + __func__, size, gen_pool_avail(gpool)); + return NULL; + } + + if (gfp & __GFP_ZERO) + memset((void *)vaddr, 0, size); + + /* WARN if other gfp set ? */ + + dev_dbg(gdev, "%s: 0x%zx alloced, avail 0x%zx\n", __func__, size, + gen_pool_avail(gpool)); + + return (void *)vaddr; +} + +static void gpool_shm_free(void *vaddr, size_t size) +{ + BUG_ON(!gpool); + BUG_ON(!vaddr); + BUG_ON(!size); + + gen_pool_free(gpool, (uintptr_t)vaddr, size); + + dev_dbg(gdev, "%s: 0x%zx freed, avail 0x%zx\n", __func__, size, + gen_pool_avail(gpool)); +} + +static void *gpool_shm_phys_to_virt(phys_addr_t paddr) +{ + struct gen_pool_chunk *chunk; + size_t chunk_size = 0; + unsigned long vaddr = 0; + + BUG_ON(!gpool); + + rcu_read_lock(); + list_for_each_entry_rcu(chunk, &gpool->chunks, next_chunk) { + chunk_size = chunk->end_addr - chunk->start_addr + 1; + /* check addr is within chunk boundary */ + if (paddr >= chunk->phys_addr && + paddr <= (chunk->phys_addr + chunk_size)) { + vaddr = chunk->start_addr + (paddr - chunk->phys_addr); + break; + } + } + rcu_read_unlock(); + + return (void *)vaddr; +} + +static phys_addr_t gpool_shm_virt_to_phys(const volatile void *vaddr) +{ + BUG_ON(!gpool); + + return gen_pool_virt_to_phys(gpool, (uintptr_t)vaddr); +} + +static struct trusty_shm_ops shm_ops = { + .alloc = default_shm_alloc, + .free = default_shm_free, + .virt_to_phys = virt_to_phys, + .phys_to_virt = phys_to_virt, +}; + +void *trusty_shm_alloc(size_t size, gfp_t gfp) +{ + return shm_ops.alloc(size, gfp); +} + +void trusty_shm_free(void *vaddr, size_t size) +{ + shm_ops.free(vaddr, size); +} + +void *trusty_shm_phys_to_virt(unsigned long paddr) +{ + return shm_ops.phys_to_virt(paddr); +} + +phys_addr_t trusty_shm_virt_to_phys(void *vaddr) +{ + return shm_ops.virt_to_phys(vaddr); +} + +int trusty_shm_init_pool(struct device *dev) +{ + int rc; + unsigned long shm_pa = 0; + unsigned long shm_va = 0; + unsigned long shm_size = 0; + unsigned long shm_ioremap_pa = 0; /* for hee pa fixup */ + struct link_shbuf_data *shbuf_dev = NULL; + + gdev = dev; + shbuf_dev = trusty_get_link_shbuf_device(0); + + if (shbuf_dev) { + shm_pa = shbuf_dev->buffer.start + shbuf_dev->ramconsole_size; + shm_size = resource_size(&shbuf_dev->buffer) - + shbuf_dev->ramconsole_size; + shm_va = + (uintptr_t)shbuf_dev->base + shbuf_dev->ramconsole_size; + shm_ioremap_pa = page_to_phys(virt_to_page(shm_va)); + + dev_info(dev, "%s: pa %lx size %lx va %lx remap_pa %lx\n", + __func__, shm_pa, shm_size, shm_va, shm_ioremap_pa); + + gpool = gen_pool_create(3 /* 8 bytes aligned */, -1); + if (!gpool) { + dev_err(dev, "%s: gen_pool_create failed\n", __func__); + goto err_pool_create; + } + + gen_pool_set_algo(gpool, gen_pool_best_fit, NULL); + rc = gen_pool_add_virt(gpool, shm_va, shm_pa, shm_size, -1); + if (rc < 0) { + dev_err(dev, "%s: gen_pool_add_virt failed (%d)\n", + __func__, rc); + gen_pool_destroy(gpool); + goto err_pool_add_virt; + } + + shm_ops.alloc = gpool_shm_alloc; + shm_ops.free = gpool_shm_free; + shm_ops.virt_to_phys = gpool_shm_virt_to_phys; + shm_ops.phys_to_virt = gpool_shm_phys_to_virt; + /* + * ioremap va is not in kernel linear map, so we need + * to pass the offset between linear and non-linear + * mapping to hee for fixing up. + */ + trusty_fast_call32(dev, SMC_FC_IOREMAP_PA_INFO, + (u32)shm_ioremap_pa, + (u32)(shm_ioremap_pa >> 32), (u32)shm_size); + + dev_info(dev, "shm available, use shm alloc/free\n"); + return 0; + } + + /* fallback to alloc_pages_exact / free_pages_exact */ +err_pool_add_virt: + if (gpool) { + gen_pool_destroy(gpool); + gpool = NULL; + } +err_pool_create: + dev_info(dev, "shm not available, fallback to default alloc/free\n"); + return 0; +} + +void trusty_shm_destroy_pool(struct device *dev) +{ + if (gpool) + gen_pool_destroy(gpool); +} diff --git a/drivers/trusty/trusty-virq.c b/drivers/trusty/trusty-virq.c new file mode 100644 index 000000000000..9696fb1bc2f1 --- /dev/null +++ b/drivers/trusty/trusty-virq.c @@ -0,0 +1,242 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "trusty-virq.h" + +#define MAX_VIRQ_DEV 4 +#define LESS (-1) +#define EQUAL (0) +#define GREATER (1) + +static struct virq_device *virqdev[MAX_VIRQ_DEV]; +static u32 virqdev_num; + +static irqreturn_t virq_handler(int irq, void *data) +{ + struct virq_device *dev = data; + ulong payload = okl4_get_virq_payload(irq); + + dev->virq.payload |= payload; + + /* Ensure all PEs see the latest payload. */ + smp_wmb(); + dev->virq.raised = true; + + wake_up_interruptible(&dev->virq.wq); + return IRQ_HANDLED; +} + +struct virq_device *trusty_get_virq_device(u32 virqidx) +{ + if (virqidx >= MAX_VIRQ_DEV) + return NULL; + + return virqdev[virqidx]; +} + +s32 trusty_virq_recv(u32 virqidx, ulong *out) +{ + ulong payload; + int ret; + struct virq_device *dev = trusty_get_virq_device(virqidx); + + if (!dev) + return -EINVAL; + + do { + ret = wait_event_interruptible(dev->virq.wq, dev->virq.raised); + if (ret < 0) + return ret; + } while (!xchg(&dev->virq.raised, 0)); + + /* Ensure all PEs see the latest payload. */ + smp_rmb(); + payload = xchg(&dev->virq.payload, 0); + + if (out) + *out = payload; + + dev_dbg(dev->dev, "%s: irq %d hwirq %d payload 0x%lx\n", __func__, + dev->virq.irqno, dev->virq.hwirq, payload); + + return 0; +} + +s32 trusty_virq_send(u32 virqidx, ulong payload) +{ + okl4_error_t err; + struct virq_device *dev = trusty_get_virq_device(virqidx); + + if (!dev) { + dev_err(dev->dev, "virqidx %u invalid, virqdev_num = %u\n", + virqidx, virqdev_num); + return -EINVAL; + } + + err = _okl4_sys_vinterrupt_raise(dev->source.kcap, payload); + if (err != OKL4_OK) { + dev_err(dev->dev, + "failed to raise virq %u err %u payload 0x%lx\n", + dev->source.kcap, err, payload); + return -EIO; + } + + dev_dbg(dev->dev, "%s: irq %d hwirq %d payload 0x%lx\n", __func__, + dev->virq.irqno, dev->virq.hwirq, payload); + + return 0; +} + +s32 trusty_virq_smc(u32 virqidx, ulong r0, ulong r1, ulong r2, ulong r3) +{ + unsigned long ret = 0; + struct virq_device *dev = trusty_get_virq_device(virqidx); + + trusty_virq_send(virqidx, r0); + trusty_virq_recv(virqidx, NULL); + trusty_virq_send(virqidx, r1); + trusty_virq_recv(virqidx, NULL); + trusty_virq_send(virqidx, r2); + trusty_virq_recv(virqidx, NULL); + trusty_virq_send(virqidx, r3); + trusty_virq_recv(virqidx, &ret); + + dev_dbg(dev->dev, "%s(%u): 0x%lx 0x%lx 0x%lx 0x%lx done (0x%lx)\n", + __func__, virqidx, r0, r1, r2, r3, ret); + + return ret; +} + +static int virqdev_compare(const void *lhs, const void *rhs) +{ + const struct virq_device *l = lhs; + const struct virq_device *r = rhs; + + if (l->virq.hwirq < r->virq.hwirq) + return LESS; + if (l->virq.hwirq > r->virq.hwirq) + return GREATER; + return EQUAL; +} + +static int trusty_virq_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *node = pdev->dev.of_node; + struct virq_device *vdev = NULL; + struct irq_desc *desc; + + if (!node) { + dev_err(&pdev->dev, "of_node required\n"); + return -ENODEV; + } + + if (virqdev_num >= MAX_VIRQ_DEV) { + dev_err(&pdev->dev, "virq devices > MAX_VIRQ_DEV\n"); + return -ENOMEM; + } + + vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); + if (!vdev) + return -ENOMEM; + + vdev->dev = &pdev->dev; + vdev->virq.raised = false; + vdev->virq.payload = 0; + init_waitqueue_head(&vdev->virq.wq); + + if (!of_device_is_compatible(node, "okl,microvisor-interrupt-line")) { + ret = -EINVAL; + goto err_virq_register; + } + of_property_read_u32(node, "reg", &vdev->source.kcap); + + vdev->virq.irqno = platform_get_irq(pdev, 0); + if (vdev->virq.irqno < 0) { + ret = -EINVAL; + goto err_virq_register; + } + + ret = devm_request_irq(&pdev->dev, vdev->virq.irqno, virq_handler, 0, + "virq", vdev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to request_irq: %d\n", ret); + goto err_virq_register; + } + + desc = irq_to_desc(vdev->virq.irqno); + if (desc) + vdev->virq.hwirq = desc->irq_data.hwirq; + + virqdev[virqdev_num++] = vdev; + sort(virqdev, virqdev_num, sizeof(u64), &virqdev_compare, NULL); + + dev_info(&pdev->dev, "current %d virq devices registered.\n", + virqdev_num); + + for (i = 0; i < virqdev_num; i++) { + dev_info(&pdev->dev, + " virqdev[%d] irqno %d hwirq %d kcap %d\n", i, + virqdev[i]->virq.irqno, virqdev[i]->virq.hwirq, + virqdev[i]->source.kcap); + } + + return 0; + +err_virq_register: + kfree(vdev); + return ret; +} + +static const struct of_device_id trusty_virq_of_match[] = { + { + .compatible = "okl,user-virq", + }, + {}, +}; + +static struct platform_driver trusty_virq_driver = { + .probe = trusty_virq_probe, + .driver = { + .name = "trusty-virq", + .owner = THIS_MODULE, + .of_match_table = trusty_virq_of_match, + }, +}; + +static int __init trusty_virq_init(void) +{ + return platform_driver_register(&trusty_virq_driver); +} + +static void __exit trusty_virq_exit(void) +{ + platform_driver_unregister(&trusty_virq_driver); +} + +arch_initcall(trusty_virq_init); +module_exit(trusty_virq_exit); diff --git a/drivers/trusty/trusty-virq.h b/drivers/trusty/trusty-virq.h new file mode 100644 index 000000000000..9db067e38bb5 --- /dev/null +++ b/drivers/trusty/trusty-virq.h @@ -0,0 +1,55 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _TRUSTY_VIRQ_H_ +#define _TRUSTY_VIRQ_H_ + +#include +#include + +struct virq_data { + wait_queue_head_t wq; + int irqno; + int hwirq; + bool raised; + unsigned long payload; +}; + +struct source_data { + okl4_kcap_t kcap; +}; + +struct virq_device { + struct device *dev; + struct virq_data virq; /* notify from hee */ + struct source_data source; /* notify to hee */ +#ifdef CONFIG_TRUSTY_VIRQ_SIMULATION + void __iomem *gicd_base; +#endif +}; + +#ifdef CONFIG_TRUSTY_VIRQ_SIMULATION +/* Enabled only in QEMU environment. */ +extern int gic_set_affinity_possible(struct irq_data *d, + const struct cpumask *mask_val, + bool force); +#endif + +s32 trusty_virq_recv(u32 virqidx, ulong *out); +s32 trusty_virq_send(u32 virqidx, ulong payload); +s32 trusty_virq_smc(u32 virqidx, ulong r0, ulong r1, ulong r2, ulong r3); +struct virq_device *trusty_get_virq_device(u32 virqidx); + +#endif /* _TRUSTY_VIRQ_H_ */ diff --git a/drivers/trusty/trusty-virtio.c b/drivers/trusty/trusty-virtio.c new file mode 100644 index 000000000000..a47b076256b4 --- /dev/null +++ b/drivers/trusty/trusty-virtio.c @@ -0,0 +1,761 @@ +/* + * Trusty Virtio driver + * + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * Copyright (C) 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "trusty-link-shbuf.h" + +#define RSC_DESCR_VER 1 + +struct trusty_vdev; + +struct trusty_ctx { + struct device *dev; + void *shared_va; + size_t shared_sz; + struct work_struct check_vqs; + struct work_struct kick_vqs; + struct notifier_block call_notifier; + struct list_head vdev_list; + struct mutex mlock; /* protects vdev_list */ + struct workqueue_struct *kick_wq; + struct workqueue_struct *check_wq; +}; + +struct trusty_vring { + void *vaddr; + phys_addr_t paddr; + size_t size; + uint align; + uint elem_num; + u32 notifyid; + atomic_t needs_kick; + struct fw_rsc_vdev_vring *vr_descr; + struct virtqueue *vq; + struct trusty_vdev *tvdev; + struct trusty_nop kick_nop; +}; + +struct trusty_vdev { + struct list_head node; + struct virtio_device vdev; + struct trusty_ctx *tctx; + u32 notifyid; + uint config_len; + void *config; + struct fw_rsc_vdev *vdev_descr; + uint vring_num; + struct trusty_vring vrings[0]; +}; + +#define vdev_to_tvdev(vd) container_of((vd), struct trusty_vdev, vdev) + +static void check_all_vqs(struct work_struct *work) +{ + uint i; + struct trusty_ctx *tctx = + container_of(work, struct trusty_ctx, check_vqs); + struct trusty_vdev *tvdev; + + list_for_each_entry(tvdev, &tctx->vdev_list, node) { + for (i = 0; i < tvdev->vring_num; i++) + vring_interrupt(0, tvdev->vrings[i].vq); + } +} + +static int trusty_call_notify(struct notifier_block *nb, unsigned long action, + void *data) +{ + struct trusty_ctx *tctx; + + if (action != TRUSTY_CALL_RETURNED) + return NOTIFY_DONE; + + tctx = container_of(nb, struct trusty_ctx, call_notifier); + queue_work(tctx->check_wq, &tctx->check_vqs); + + return NOTIFY_OK; +} + +static void kick_vq(struct trusty_ctx *tctx, struct trusty_vdev *tvdev, + struct trusty_vring *tvr) +{ + int ret; + + dev_dbg(tctx->dev, "%s: vdev_id=%d: vq_id=%d\n", __func__, + tvdev->notifyid, tvr->notifyid); + + ret = trusty_std_call32(tctx->dev->parent, SMC_SC_VDEV_KICK_VQ, + tvdev->notifyid, tvr->notifyid, 0); + if (ret) { + dev_err(tctx->dev, "vq notify (%d, %d) returned %d\n", + tvdev->notifyid, tvr->notifyid, ret); + } +} + +static void kick_vqs(struct work_struct *work) +{ + uint i; + struct trusty_vdev *tvdev; + struct trusty_ctx *tctx = + container_of(work, struct trusty_ctx, kick_vqs); + mutex_lock(&tctx->mlock); + list_for_each_entry(tvdev, &tctx->vdev_list, node) { + for (i = 0; i < tvdev->vring_num; i++) { + struct trusty_vring *tvr = &tvdev->vrings[i]; + if (atomic_xchg(&tvr->needs_kick, 0)) + kick_vq(tctx, tvdev, tvr); + } + } + mutex_unlock(&tctx->mlock); +} + +static bool trusty_virtio_notify(struct virtqueue *vq) +{ + struct trusty_vring *tvr = vq->priv; + struct trusty_vdev *tvdev = tvr->tvdev; + struct trusty_ctx *tctx = tvdev->tctx; + u32 api_ver = trusty_get_api_version(tctx->dev->parent); + ulong smc_nr = SMC_NC_VDEV_KICK_VQ; + ulong payload = (smc_nr << 32) | (tvdev->notifyid << 16) | + (u16)tvr->notifyid; + + if (api_ver < TRUSTY_API_VERSION_SMP_NOP) { + atomic_set(&tvr->needs_kick, 1); + queue_work(tctx->kick_wq, &tctx->kick_vqs); + } else { + if (trusty_get_link_shbuf_device(0)) + trusty_link_shbuf_send(0, payload); + else + trusty_enqueue_nop(tctx->dev->parent, &tvr->kick_nop); + } + + return true; +} + +static int trusty_load_device_descr(struct trusty_ctx *tctx, void *va, + size_t sz) +{ + int ret; + + dev_dbg(tctx->dev, "%s: %zu bytes @ %p\n", __func__, sz, va); + + ret = trusty_call32_mem_buf(tctx->dev->parent, SMC_SC_VIRTIO_GET_DESCR, + virt_to_page(va), sz, PAGE_KERNEL, true); + if (ret < 0) { + dev_err(tctx->dev, "%s: virtio get descr returned (%d)\n", + __func__, ret); + return -ENODEV; + } + return ret; +} + +static void trusty_virtio_stop(struct trusty_ctx *tctx, void *va, size_t sz) +{ + int ret; + + dev_dbg(tctx->dev, "%s: %zu bytes @ %p\n", __func__, sz, va); + + ret = trusty_call32_mem_buf(tctx->dev->parent, SMC_SC_VIRTIO_STOP, + virt_to_page(va), sz, PAGE_KERNEL, false); + if (ret) { + dev_err(tctx->dev, "%s: virtio done returned (%d)\n", __func__, + ret); + return; + } +} + +static int trusty_virtio_start(struct trusty_ctx *tctx, void *va, size_t sz) +{ + int ret; + + dev_dbg(tctx->dev, "%s: %zu bytes @ %p\n", __func__, sz, va); + + ret = trusty_call32_mem_buf(tctx->dev->parent, SMC_SC_VIRTIO_START, + virt_to_page(va), sz, PAGE_KERNEL, false); + if (ret) { + dev_err(tctx->dev, "%s: virtio start returned (%d)\n", __func__, + ret); + return -ENODEV; + } + return 0; +} + +static void trusty_virtio_reset(struct virtio_device *vdev) +{ + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + struct trusty_ctx *tctx = tvdev->tctx; + + dev_dbg(&vdev->dev, "reset vdev_id=%d\n", tvdev->notifyid); + trusty_std_call32(tctx->dev->parent, SMC_SC_VDEV_RESET, tvdev->notifyid, + 0, 0); +} + +static u64 trusty_virtio_get_features(struct virtio_device *vdev) +{ + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + return tvdev->vdev_descr->dfeatures; +} + +static int trusty_virtio_finalize_features(struct virtio_device *vdev) +{ + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + + /* Make sure we don't have any features > 32 bits! */ + BUG_ON((u32)vdev->features != vdev->features); + + tvdev->vdev_descr->gfeatures = vdev->features; + return 0; +} + +static void trusty_virtio_get_config(struct virtio_device *vdev, + unsigned offset, void *buf, unsigned len) +{ + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + + dev_dbg(&vdev->dev, "%s: %d bytes @ offset %d\n", __func__, len, + offset); + + if (tvdev->config) { + if (offset + len <= tvdev->config_len) + memcpy(buf, tvdev->config + offset, len); + } +} + +static void trusty_virtio_set_config(struct virtio_device *vdev, + unsigned offset, const void *buf, + unsigned len) +{ + dev_dbg(&vdev->dev, "%s\n", __func__); +} + +static u8 trusty_virtio_get_status(struct virtio_device *vdev) +{ + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + return tvdev->vdev_descr->status; +} + +static void trusty_virtio_set_status(struct virtio_device *vdev, u8 status) +{ + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + tvdev->vdev_descr->status = status; +} + +static void _del_vqs(struct virtio_device *vdev) +{ + uint i; + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + struct trusty_vring *tvr = &tvdev->vrings[0]; + + for (i = 0; i < tvdev->vring_num; i++, tvr++) { + /* dequeue kick_nop */ + trusty_dequeue_nop(tvdev->tctx->dev->parent, &tvr->kick_nop); + + /* delete vq */ + if (tvr->vq) { + vring_del_virtqueue(tvr->vq); + tvr->vq = NULL; + } + /* delete vring */ + if (tvr->vaddr) { + trusty_shm_free(tvr->vaddr, tvr->size); + tvr->vaddr = NULL; + } + } +} + +static void trusty_virtio_del_vqs(struct virtio_device *vdev) +{ + dev_dbg(&vdev->dev, "%s\n", __func__); + _del_vqs(vdev); +} + +static struct virtqueue *_find_vq(struct virtio_device *vdev, unsigned id, + void (*callback)(struct virtqueue *vq), + const char *name +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + , + bool ctx +#endif +) +{ + struct trusty_vring *tvr; + struct trusty_vdev *tvdev = vdev_to_tvdev(vdev); + phys_addr_t pa; + + if (!name) + return ERR_PTR(-EINVAL); + + if (id >= tvdev->vring_num) + return ERR_PTR(-EINVAL); + + tvr = &tvdev->vrings[id]; + + /* actual size of vring (in bytes) */ + tvr->size = PAGE_ALIGN(vring_size(tvr->elem_num, tvr->align)); + + /* allocate memory for the vring. */ + tvr->vaddr = trusty_shm_alloc(tvr->size, GFP_KERNEL | __GFP_ZERO); + if (!tvr->vaddr) { + dev_err(&vdev->dev, "vring alloc failed\n"); + return ERR_PTR(-ENOMEM); + } + + pa = trusty_shm_virt_to_phys(tvr->vaddr); + /* save vring address to shared structure */ + tvr->vr_descr->da = (u32)pa; + /* da field is only 32 bit wide. Use previously unused 'reserved' field + * to store top 32 bits of 64-bit address + */ + tvr->vr_descr->pa = (u32)(pa >> 32); + + dev_info(&vdev->dev, "vring%d: va(pa) %p(%llx) qsz %d notifyid %d\n", + id, tvr->vaddr, (u64)tvr->paddr, tvr->elem_num, tvr->notifyid); + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4, 10, 0) + tvr->vq = vring_new_virtqueue(id, tvr->elem_num, tvr->align, vdev, true, + tvr->vaddr, trusty_virtio_notify, + callback, name); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + tvr->vq = vring_new_virtqueue(id, tvr->elem_num, tvr->align, vdev, true, + ctx, tvr->vaddr, trusty_virtio_notify, + callback, name); +#endif + if (!tvr->vq) { + dev_err(&vdev->dev, "vring_new_virtqueue %s failed\n", name); + goto err_new_virtqueue; + } + + tvr->vq->priv = tvr; + + return tvr->vq; + +err_new_virtqueue: + trusty_shm_free(tvr->vaddr, tvr->size); + tvr->vaddr = NULL; + return ERR_PTR(-ENOMEM); +} + +static int trusty_virtio_find_vqs(struct virtio_device *vdev, unsigned nvqs, + struct virtqueue *vqs[], + vq_callback_t *callbacks[], + const char *const names[] +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + , + const bool *ctx, struct irq_affinity *desc +#endif +) +{ + uint i; + int ret; + + for (i = 0; i < nvqs; i++) { +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4, 10, 0) + vqs[i] = _find_vq(vdev, i, callbacks[i], names[i]); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) + vqs[i] = _find_vq(vdev, i, callbacks[i], names[i], + ctx ? ctx[i] : false); +#endif + if (IS_ERR(vqs[i])) { + ret = PTR_ERR(vqs[i]); + _del_vqs(vdev); + return ret; + } + } + return 0; +} + +static const char *trusty_virtio_bus_name(struct virtio_device *vdev) +{ + return "trusty-virtio"; +} + +/* The ops structure which hooks everything together. */ +static const struct virtio_config_ops trusty_virtio_config_ops = { + .get_features = trusty_virtio_get_features, + .finalize_features = trusty_virtio_finalize_features, + .get = trusty_virtio_get_config, + .set = trusty_virtio_set_config, + .get_status = trusty_virtio_get_status, + .set_status = trusty_virtio_set_status, + .reset = trusty_virtio_reset, + .find_vqs = trusty_virtio_find_vqs, + .del_vqs = trusty_virtio_del_vqs, + .bus_name = trusty_virtio_bus_name, +}; + +static int trusty_virtio_add_device(struct trusty_ctx *tctx, + struct fw_rsc_vdev *vdev_descr, + struct fw_rsc_vdev_vring *vr_descr, + void *config) +{ + int i, ret; + struct trusty_vdev *tvdev; + + tvdev = kzalloc(sizeof(struct trusty_vdev) + + vdev_descr->num_of_vrings * + sizeof(struct trusty_vring), + GFP_KERNEL); + if (!tvdev) { + dev_err(tctx->dev, "Failed to allocate VDEV\n"); + return -ENOMEM; + } + + /* setup vdev */ + tvdev->tctx = tctx; + tvdev->vdev.dev.parent = tctx->dev; + tvdev->vdev.id.device = vdev_descr->id; + tvdev->vdev.config = &trusty_virtio_config_ops; + tvdev->vdev_descr = vdev_descr; + tvdev->notifyid = vdev_descr->notifyid; + + /* setup config */ + tvdev->config = config; + tvdev->config_len = vdev_descr->config_len; + + /* setup vrings and vdev resource */ + tvdev->vring_num = vdev_descr->num_of_vrings; + + for (i = 0; i < tvdev->vring_num; i++, vr_descr++) { + struct trusty_vring *tvr = &tvdev->vrings[i]; + tvr->tvdev = tvdev; + tvr->vr_descr = vr_descr; + tvr->align = vr_descr->align; + tvr->elem_num = vr_descr->num; + tvr->notifyid = vr_descr->notifyid; + trusty_nop_init(&tvr->kick_nop, SMC_NC_VDEV_KICK_VQ, + tvdev->notifyid, tvr->notifyid); + } + + /* register device */ + ret = register_virtio_device(&tvdev->vdev); + if (ret) { + dev_err(tctx->dev, + "Failed (%d) to register device dev type %u\n", ret, + vdev_descr->id); + goto err_register; + } + + /* add it to tracking list */ + list_add_tail(&tvdev->node, &tctx->vdev_list); + + return 0; + +err_register: + kfree(tvdev); + return ret; +} + +static int trusty_parse_device_descr(struct trusty_ctx *tctx, void *descr_va, + size_t descr_sz) +{ + u32 i; + struct resource_table *descr = descr_va; + + if (descr_sz < sizeof(*descr)) { + dev_err(tctx->dev, "descr table is too small (0x%x)\n", + (int)descr_sz); + return -ENODEV; + } + + if (descr->ver != RSC_DESCR_VER) { + dev_err(tctx->dev, "unexpected descr ver (0x%x)\n", + (int)descr->ver); + return -ENODEV; + } + + if (descr_sz < (sizeof(*descr) + descr->num * sizeof(u32))) { + dev_err(tctx->dev, "descr table is too small (0x%x)\n", + (int)descr->ver); + return -ENODEV; + } + + for (i = 0; i < descr->num; i++) { + struct fw_rsc_hdr *hdr; + struct fw_rsc_vdev *vd; + struct fw_rsc_vdev_vring *vr; + void *cfg; + size_t vd_sz; + + u32 offset = descr->offset[i]; + + if (offset >= descr_sz) { + dev_err(tctx->dev, "offset is out of bounds (%u)\n", + (uint)offset); + return -ENODEV; + } + + /* check space for rsc header */ + if ((descr_sz - offset) < sizeof(struct fw_rsc_hdr)) { + dev_err(tctx->dev, "no space for rsc header (%u)\n", + (uint)offset); + return -ENODEV; + } + hdr = (struct fw_rsc_hdr *)((u8 *)descr + offset); + offset += sizeof(struct fw_rsc_hdr); + + /* check type */ + if (hdr->type != RSC_VDEV) { + dev_err(tctx->dev, "unsupported rsc type (%u)\n", + (uint)hdr->type); + continue; + } + + /* got vdev: check space for vdev */ + if ((descr_sz - offset) < sizeof(struct fw_rsc_vdev)) { + dev_err(tctx->dev, "no space for vdev descr (%u)\n", + (uint)offset); + return -ENODEV; + } + vd = (struct fw_rsc_vdev *)((u8 *)descr + offset); + + /* check space for vrings and config area */ + vd_sz = sizeof(struct fw_rsc_vdev) + + vd->num_of_vrings * sizeof(struct fw_rsc_vdev_vring) + + vd->config_len; + + if ((descr_sz - offset) < vd_sz) { + dev_err(tctx->dev, "no space for vdev (%u)\n", + (uint)offset); + return -ENODEV; + } + vr = (struct fw_rsc_vdev_vring *)vd->vring; + cfg = (void *)(vr + vd->num_of_vrings); + + trusty_virtio_add_device(tctx, vd, vr, cfg); + } + + return 0; +} + +static void _remove_devices_locked(struct trusty_ctx *tctx) +{ + struct trusty_vdev *tvdev, *next; + + list_for_each_entry_safe(tvdev, next, &tctx->vdev_list, node) { + list_del(&tvdev->node); + unregister_virtio_device(&tvdev->vdev); + kfree(tvdev); + } +} + +static void trusty_virtio_remove_devices(struct trusty_ctx *tctx) +{ + mutex_lock(&tctx->mlock); + _remove_devices_locked(tctx); + mutex_unlock(&tctx->mlock); +} + +static int trusty_virtio_add_devices(struct trusty_ctx *tctx) +{ + int ret; + void *descr_va; + size_t descr_sz; + size_t descr_buf_sz; + + /* allocate buffer to load device descriptor into */ + descr_buf_sz = PAGE_SIZE; + descr_va = trusty_shm_alloc(descr_buf_sz, GFP_KERNEL | __GFP_ZERO); + if (!descr_va) { + dev_err(tctx->dev, "Failed to allocate shared area\n"); + return -ENOMEM; + } + + /* load device descriptors */ + ret = trusty_load_device_descr(tctx, descr_va, descr_buf_sz); + if (ret < 0) { + dev_err(tctx->dev, "failed (%d) to load device descr\n", ret); + goto err_load_descr; + } + + descr_sz = (size_t)ret; + + mutex_lock(&tctx->mlock); + + /* parse device descriptor and add virtio devices */ + ret = trusty_parse_device_descr(tctx, descr_va, descr_sz); + if (ret) { + dev_err(tctx->dev, "failed (%d) to parse device descr\n", ret); + goto err_parse_descr; + } + + /* register call notifier */ + ret = trusty_call_notifier_register(tctx->dev->parent, + &tctx->call_notifier); + if (ret) { + dev_err(tctx->dev, "%s: failed (%d) to register notifier\n", + __func__, ret); + goto err_register_notifier; + } + + /* start virtio */ + ret = trusty_virtio_start(tctx, descr_va, descr_sz); + if (ret) { + dev_err(tctx->dev, "failed (%d) to start virtio\n", ret); + goto err_start_virtio; + } + + /* attach shared area */ + tctx->shared_va = descr_va; + tctx->shared_sz = descr_buf_sz; + + mutex_unlock(&tctx->mlock); + + return 0; + +err_start_virtio: + trusty_call_notifier_unregister(tctx->dev->parent, + &tctx->call_notifier); + cancel_work_sync(&tctx->check_vqs); +err_register_notifier: +err_parse_descr: + _remove_devices_locked(tctx); + mutex_unlock(&tctx->mlock); + cancel_work_sync(&tctx->kick_vqs); + trusty_virtio_stop(tctx, descr_va, descr_sz); +err_load_descr: + trusty_shm_free(descr_va, descr_buf_sz); + return ret; +} + +static int trusty_virtio_probe(struct platform_device *pdev) +{ + int ret; + struct trusty_ctx *tctx; + + dev_info(&pdev->dev, "initializing\n"); + + tctx = kzalloc(sizeof(*tctx), GFP_KERNEL); + if (!tctx) { + dev_err(&pdev->dev, "Failed to allocate context\n"); + return -ENOMEM; + } + + tctx->dev = &pdev->dev; + tctx->call_notifier.notifier_call = trusty_call_notify; + mutex_init(&tctx->mlock); + INIT_LIST_HEAD(&tctx->vdev_list); + INIT_WORK(&tctx->check_vqs, check_all_vqs); + INIT_WORK(&tctx->kick_vqs, kick_vqs); + platform_set_drvdata(pdev, tctx); + + tctx->check_wq = alloc_workqueue("trusty-check-wq", WQ_UNBOUND, 0); + if (!tctx->check_wq) { + ret = -ENODEV; + dev_err(&pdev->dev, "Failed create trusty-check-wq\n"); + goto err_create_check_wq; + } + + tctx->kick_wq = alloc_workqueue("trusty-kick-wq", + WQ_UNBOUND | WQ_CPU_INTENSIVE, 0); + if (!tctx->kick_wq) { + ret = -ENODEV; + dev_err(&pdev->dev, "Failed create trusty-kick-wq\n"); + goto err_create_kick_wq; + } + + ret = trusty_virtio_add_devices(tctx); + if (ret) { + dev_err(&pdev->dev, "Failed to add virtio devices\n"); + goto err_add_devices; + } + + dev_info(&pdev->dev, "initializing done\n"); + return 0; + +err_add_devices: + destroy_workqueue(tctx->kick_wq); +err_create_kick_wq: + destroy_workqueue(tctx->check_wq); +err_create_check_wq: + kfree(tctx); + return ret; +} + +static int trusty_virtio_remove(struct platform_device *pdev) +{ + struct trusty_ctx *tctx = platform_get_drvdata(pdev); + + dev_err(&pdev->dev, "removing\n"); + + /* unregister call notifier and wait until workqueue is done */ + trusty_call_notifier_unregister(tctx->dev->parent, + &tctx->call_notifier); + cancel_work_sync(&tctx->check_vqs); + + /* remove virtio devices */ + trusty_virtio_remove_devices(tctx); + cancel_work_sync(&tctx->kick_vqs); + + /* destroy workqueues */ + destroy_workqueue(tctx->kick_wq); + destroy_workqueue(tctx->check_wq); + + /* notify remote that shared area goes away */ + trusty_virtio_stop(tctx, tctx->shared_va, tctx->shared_sz); + + /* free shared area */ + trusty_shm_free(tctx->shared_va, tctx->shared_sz); + + /* free context */ + kfree(tctx); + return 0; +} + +static const struct of_device_id trusty_of_match[] = { + { + .compatible = "android,trusty-virtio-v1", + }, +}; + +MODULE_DEVICE_TABLE(of, trusty_of_match); + +static struct platform_driver trusty_virtio_driver = { + .probe = trusty_virtio_probe, + .remove = trusty_virtio_remove, + .driver = { + .name = "trusty-virtio", + .owner = THIS_MODULE, + .of_match_table = trusty_of_match, + }, +}; + +module_platform_driver(trusty_virtio_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Trusty virtio driver"); diff --git a/drivers/trusty/trusty.c b/drivers/trusty/trusty.c new file mode 100644 index 000000000000..c690df2f263c --- /dev/null +++ b/drivers/trusty/trusty.c @@ -0,0 +1,662 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "trusty-link-shbuf.h" +#include "trusty-virq.h" + +struct trusty_state; + +struct trusty_work { + struct trusty_state *ts; + struct work_struct work; +}; + +struct trusty_state { + struct mutex smc_lock; + struct atomic_notifier_head notifier; + struct completion cpu_idle_completion; + char *version_str; + u32 api_version; + struct device *dev; + struct workqueue_struct *nop_wq; + struct trusty_work __percpu *nop_works; + struct list_head nop_queue; + spinlock_t nop_lock; /* protects nop_queue */ +}; + +struct trusty_state *tstate; + +#ifdef CONFIG_ARM64 +#define SMC_ARG0 "x0" +#define SMC_ARG1 "x1" +#define SMC_ARG2 "x2" +#define SMC_ARG3 "x3" +#define SMC_ARCH_EXTENSION "" +#define SMC_REGISTERS_TRASHED \ + "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", \ + "x15", "x16", "x17" +#else +#define SMC_ARG0 "r0" +#define SMC_ARG1 "r1" +#define SMC_ARG2 "r2" +#define SMC_ARG3 "r3" +#define SMC_ARCH_EXTENSION ".arch_extension sec\n" +#define SMC_REGISTERS_TRASHED "ip" +#endif + +static inline ulong smc(ulong r0, ulong r1, ulong r2, ulong r3) +{ + register ulong _r0 asm(SMC_ARG0) = r0; + register ulong _r1 asm(SMC_ARG1) = r1; + register ulong _r2 asm(SMC_ARG2) = r2; + register ulong _r3 asm(SMC_ARG3) = r3; + + asm volatile(__asmeq("%0", SMC_ARG0) __asmeq("%1", SMC_ARG1) __asmeq( + "%2", SMC_ARG2) __asmeq("%3", SMC_ARG3) + __asmeq("%4", SMC_ARG0) __asmeq("%5", SMC_ARG1) + __asmeq("%6", SMC_ARG2) + __asmeq("%7", SMC_ARG3) + SMC_ARCH_EXTENSION + "smc #0" /* switch to secure world */ + : "=r"(_r0), "=r"(_r1), "=r"(_r2), "=r"(_r3) + : "r"(_r0), "r"(_r1), "r"(_r2), "r"(_r3) + : SMC_REGISTERS_TRASHED); + return _r0; +} + +s32 trusty_fast_call32(struct device *dev, u32 smcnr, u32 a0, u32 a1, u32 a2) +{ + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + BUG_ON(!s); + BUG_ON(!SMC_IS_FASTCALL(smcnr)); + BUG_ON(SMC_IS_SMC64(smcnr)); + + if (trusty_get_link_shbuf_device(0)) + return trusty_link_shbuf_smc(0, smcnr, a0, a1, a2); + + return smc(smcnr, a0, a1, a2); +} +EXPORT_SYMBOL(trusty_fast_call32); + +#ifdef CONFIG_64BIT +s64 trusty_fast_call64(struct device *dev, u64 smcnr, u64 a0, u64 a1, u64 a2) +{ + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + BUG_ON(!s); + BUG_ON(!SMC_IS_FASTCALL(smcnr)); + BUG_ON(!SMC_IS_SMC64(smcnr)); + + return smc(smcnr, a0, a1, a2); +} +#endif + +static ulong trusty_std_call_inner(struct device *dev, ulong smcnr, ulong a0, + ulong a1, ulong a2) +{ + ulong ret; + int retry = 5; + + dev_dbg(dev, "%s(0x%lx 0x%lx 0x%lx 0x%lx)\n", __func__, smcnr, a0, a1, + a2); + while (true) { + ret = smc(smcnr, a0, a1, a2); + while ((s32)ret == SM_ERR_FIQ_INTERRUPTED) + ret = smc(SMC_SC_RESTART_FIQ, 0, 0, 0); + if ((int)ret != SM_ERR_BUSY || !retry) + break; + + dev_dbg(dev, + "%s(0x%lx 0x%lx 0x%lx 0x%lx) returned busy, retry\n", + __func__, smcnr, a0, a1, a2); + retry--; + } + + return ret; +} + +static ulong trusty_std_call_helper(struct device *dev, ulong smcnr, ulong a0, + ulong a1, ulong a2) +{ + ulong ret; + int sleep_time = 1; + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + while (true) { + local_irq_disable(); + atomic_notifier_call_chain(&s->notifier, TRUSTY_CALL_PREPARE, + NULL); + ret = trusty_std_call_inner(dev, smcnr, a0, a1, a2); + atomic_notifier_call_chain(&s->notifier, TRUSTY_CALL_RETURNED, + NULL); + local_irq_enable(); + + if ((int)ret != SM_ERR_BUSY) + break; + + if (sleep_time == 256) + dev_warn(dev, + "%s(0x%lx 0x%lx 0x%lx 0x%lx) returned busy\n", + __func__, smcnr, a0, a1, a2); + dev_dbg(dev, + "%s(0x%lx 0x%lx 0x%lx 0x%lx) returned busy, wait %d ms\n", + __func__, smcnr, a0, a1, a2, sleep_time); + + msleep(sleep_time); + if (sleep_time < 1000) + sleep_time <<= 1; + + dev_dbg(dev, "%s(0x%lx 0x%lx 0x%lx 0x%lx) retry\n", __func__, + smcnr, a0, a1, a2); + } + + if (sleep_time > 256) + dev_warn(dev, "%s(0x%lx 0x%lx 0x%lx 0x%lx) busy cleared\n", + __func__, smcnr, a0, a1, a2); + + return ret; +} + +static void trusty_std_call_cpu_idle(struct trusty_state *s) +{ + int ret; + + ret = wait_for_completion_timeout(&s->cpu_idle_completion, HZ * 10); + if (!ret) { + pr_warn("%s: timed out waiting for cpu idle to clear, retry anyway\n", + __func__); + } +} + +s32 trusty_std_call32(struct device *dev, u32 smcnr, u32 a0, u32 a1, u32 a2) +{ + int ret; + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + BUG_ON(SMC_IS_FASTCALL(smcnr)); + BUG_ON(SMC_IS_SMC64(smcnr)); + + if (trusty_get_link_shbuf_device(0)) { + ret = trusty_link_shbuf_smc(0, smcnr, a0, a1, a2); + atomic_notifier_call_chain(&s->notifier, TRUSTY_CALL_RETURNED, + NULL); + return ret; + } + + if (smcnr != SMC_SC_NOP) { + mutex_lock(&s->smc_lock); + reinit_completion(&s->cpu_idle_completion); + } + + dev_dbg(dev, "%s(0x%x 0x%x 0x%x 0x%x) started\n", __func__, smcnr, a0, + a1, a2); + + ret = trusty_std_call_helper(dev, smcnr, a0, a1, a2); + while (ret == SM_ERR_INTERRUPTED || ret == SM_ERR_CPU_IDLE) { + dev_dbg(dev, "%s(0x%x 0x%x 0x%x 0x%x) interrupted\n", __func__, + smcnr, a0, a1, a2); + if (ret == SM_ERR_CPU_IDLE) + trusty_std_call_cpu_idle(s); + ret = trusty_std_call_helper(dev, SMC_SC_RESTART_LAST, 0, 0, 0); + } + dev_dbg(dev, "%s(0x%x 0x%x 0x%x 0x%x) returned 0x%x\n", __func__, smcnr, + a0, a1, a2, ret); + + WARN_ONCE(ret == SM_ERR_PANIC, "trusty crashed"); + + if (smcnr == SMC_SC_NOP) + complete(&s->cpu_idle_completion); + else + mutex_unlock(&s->smc_lock); + + return ret; +} +EXPORT_SYMBOL(trusty_std_call32); + +int trusty_call_notifier_register(struct device *dev, struct notifier_block *n) +{ + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + return atomic_notifier_chain_register(&s->notifier, n); +} +EXPORT_SYMBOL(trusty_call_notifier_register); + +int trusty_call_notifier_unregister(struct device *dev, + struct notifier_block *n) +{ + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + return atomic_notifier_chain_unregister(&s->notifier, n); +} +EXPORT_SYMBOL(trusty_call_notifier_unregister); + +static int trusty_remove_child(struct device *dev, void *data) +{ + platform_device_unregister(to_platform_device(dev)); + return 0; +} + +ssize_t trusty_version_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + return scnprintf(buf, PAGE_SIZE, "%s\n", s->version_str); +} + +DEVICE_ATTR(trusty_version, S_IRUSR, trusty_version_show, NULL); + +const char *trusty_version_str_get(struct device *dev) +{ + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + return s->version_str; +} +EXPORT_SYMBOL(trusty_version_str_get); + +static void trusty_init_version(struct trusty_state *s, struct device *dev) +{ + int ret; + int i; + int version_str_len; + + ret = trusty_fast_call32(dev, SMC_FC_GET_VERSION_STR, -1, 0, 0); + if (ret <= 0) + goto err_get_size; + + version_str_len = ret; + + s->version_str = kmalloc(version_str_len + 1, GFP_KERNEL); + for (i = 0; i < version_str_len; i++) { + ret = trusty_fast_call32(dev, SMC_FC_GET_VERSION_STR, i, 0, 0); + if (ret < 0) + goto err_get_char; + s->version_str[i] = ret; + } + s->version_str[i] = '\0'; + + dev_info(dev, "trusty version: %s\n", s->version_str); + + ret = device_create_file(dev, &dev_attr_trusty_version); + if (ret) + goto err_create_file; + return; + +err_create_file: +err_get_char: + kfree(s->version_str); + s->version_str = NULL; +err_get_size: + dev_err(dev, "failed to get version: %d\n", ret); +} + +u32 trusty_get_api_version(struct device *dev) +{ + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + return s->api_version; +} +EXPORT_SYMBOL(trusty_get_api_version); + +static int trusty_init_api_version(struct trusty_state *s, struct device *dev) +{ + u32 api_version; + api_version = trusty_fast_call32(dev, SMC_FC_API_VERSION, + TRUSTY_API_VERSION_CURRENT, 0, 0); + if (api_version == SM_ERR_UNDEFINED_SMC) + api_version = 0; + + if (api_version > TRUSTY_API_VERSION_CURRENT) { + dev_err(dev, "unsupported api version %u > %u\n", api_version, + TRUSTY_API_VERSION_CURRENT); + return -EINVAL; + } + + dev_info(dev, "selected api version: %u (requested %u)\n", api_version, + TRUSTY_API_VERSION_CURRENT); + s->api_version = api_version; + + return 0; +} + +static bool dequeue_nop(struct trusty_state *s, u32 *args) +{ + unsigned long flags; + struct trusty_nop *nop = NULL; + + spin_lock_irqsave(&s->nop_lock, flags); + if (!list_empty(&s->nop_queue)) { + nop = list_first_entry(&s->nop_queue, struct trusty_nop, node); + list_del_init(&nop->node); + args[0] = nop->args[0]; + args[1] = nop->args[1]; + args[2] = nop->args[2]; + } else { + args[0] = 0; + args[1] = 0; + args[2] = 0; + } + spin_unlock_irqrestore(&s->nop_lock, flags); + return nop; +} + +static void locked_nop_work_func(struct work_struct *work) +{ + int ret; + struct trusty_work *tw = container_of(work, struct trusty_work, work); + struct trusty_state *s = tw->ts; + + dev_dbg(s->dev, "%s\n", __func__); + + ret = trusty_std_call32(s->dev, SMC_SC_LOCKED_NOP, 0, 0, 0); + if (ret != 0) + dev_err(s->dev, "%s: SMC_SC_LOCKED_NOP failed %d", __func__, + ret); + + dev_dbg(s->dev, "%s: done\n", __func__); +} + +static void nop_work_func(struct work_struct *work) +{ + int ret; + bool next; + u32 args[3]; + struct trusty_work *tw = container_of(work, struct trusty_work, work); + struct trusty_state *s = tw->ts; + + dev_dbg(s->dev, "%s:\n", __func__); + + dequeue_nop(s, args); + do { + dev_dbg(s->dev, "%s: %x %x %x\n", __func__, args[0], args[1], + args[2]); + + ret = trusty_std_call32(s->dev, SMC_SC_NOP, args[0], args[1], + args[2]); + + next = dequeue_nop(s, args); + + if (ret == SM_ERR_NOP_INTERRUPTED) + next = true; + else if (ret != SM_ERR_NOP_DONE) + dev_err(s->dev, "%s: SMC_SC_NOP failed %d", __func__, + ret); + } while (next); + + dev_dbg(s->dev, "%s: done\n", __func__); +} + +void trusty_enqueue_nop(struct device *dev, struct trusty_nop *nop) +{ + unsigned long flags; + struct trusty_work *tw; + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + preempt_disable(); + tw = this_cpu_ptr(s->nop_works); + if (nop) { + WARN_ON(s->api_version < TRUSTY_API_VERSION_SMP_NOP); + + spin_lock_irqsave(&s->nop_lock, flags); + if (list_empty(&nop->node)) + list_add_tail(&nop->node, &s->nop_queue); + spin_unlock_irqrestore(&s->nop_lock, flags); + } + queue_work(s->nop_wq, &tw->work); + preempt_enable(); +} +EXPORT_SYMBOL(trusty_enqueue_nop); + +void trusty_dequeue_nop(struct device *dev, struct trusty_nop *nop) +{ + unsigned long flags; + struct trusty_state *s = platform_get_drvdata(to_platform_device(dev)); + + if (WARN_ON(!nop)) + return; + + spin_lock_irqsave(&s->nop_lock, flags); + if (!list_empty(&nop->node)) + list_del_init(&nop->node); + spin_unlock_irqrestore(&s->nop_lock, flags); +} +EXPORT_SYMBOL(trusty_dequeue_nop); + +static struct platform_device *gpdev; +static struct workqueue_struct *late_init_wq; +static struct work_struct late_init_work; +static struct workqueue_struct *notif_call_wq; +static struct work_struct notif_call_work; + +void trusty_probe_late(void) +{ + queue_work(late_init_wq, &late_init_work); +} + +void trusty_notifier_call(void) +{ + queue_work(notif_call_wq, ¬if_call_work); +} + +static void notif_call_work_func(struct work_struct *work) +{ + atomic_notifier_call_chain(&tstate->notifier, TRUSTY_CALL_RETURNED, + NULL); +} + +static void late_init_work_func(struct work_struct *work) +{ + int ret; + unsigned int cpu; + work_func_t work_func; + struct trusty_state *s; + struct platform_device *pdev = gpdev; + + s = kzalloc(sizeof(*s), GFP_KERNEL); + if (!s) { + ret = -ENOMEM; + goto err_allocate_state; + } + + s->dev = &pdev->dev; + spin_lock_init(&s->nop_lock); + INIT_LIST_HEAD(&s->nop_queue); + mutex_init(&s->smc_lock); + ATOMIC_INIT_NOTIFIER_HEAD(&s->notifier); + init_completion(&s->cpu_idle_completion); + platform_set_drvdata(pdev, s); + + if (trusty_get_link_shbuf_device(0)) + dev_info(&pdev->dev, "using shbuf smc ...\n"); + else + dev_info(&pdev->dev, "using default smc ...\n"); + + trusty_init_version(s, &pdev->dev); + + ret = trusty_init_api_version(s, &pdev->dev); + if (ret < 0) + goto err_api_version; + + ret = trusty_shm_init_pool(&pdev->dev); + if (ret < 0) + goto err_shm_init_pool; + + s->nop_wq = alloc_workqueue("trusty-nop-wq", WQ_CPU_INTENSIVE, 0); + if (!s->nop_wq) { + ret = -ENODEV; + dev_err(&pdev->dev, "Failed create trusty-nop-wq\n"); + goto err_create_nop_wq; + } + + s->nop_works = alloc_percpu(struct trusty_work); + if (!s->nop_works) { + ret = -ENOMEM; + dev_err(&pdev->dev, "Failed to allocate works\n"); + goto err_alloc_works; + } + + if (s->api_version < TRUSTY_API_VERSION_SMP) + work_func = locked_nop_work_func; + else + work_func = nop_work_func; + + for_each_possible_cpu(cpu) { + struct trusty_work *tw = per_cpu_ptr(s->nop_works, cpu); + + tw->ts = s; + INIT_WORK(&tw->work, work_func); + } + + tstate = s; + + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to add children: %d\n", ret); + goto err_add_children; + } + + dev_info(&pdev->dev, "%s: done\n", __func__); + + return; + +err_add_children: + for_each_possible_cpu(cpu) { + struct trusty_work *tw = per_cpu_ptr(s->nop_works, cpu); + + flush_work(&tw->work); + } + free_percpu(s->nop_works); +err_alloc_works: + destroy_workqueue(s->nop_wq); +err_create_nop_wq: + trusty_shm_destroy_pool(&pdev->dev); +err_shm_init_pool: +err_api_version: + if (s->version_str) { + device_remove_file(&pdev->dev, &dev_attr_trusty_version); + kfree(s->version_str); + } + device_for_each_child(&pdev->dev, NULL, trusty_remove_child); + mutex_destroy(&s->smc_lock); + kfree(s); +err_allocate_state: + return; +} + +static int trusty_probe_early(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + + if (!node) { + dev_err(&pdev->dev, "of_node required\n"); + return -EINVAL; + } + + gpdev = pdev; + + late_init_wq = alloc_workqueue("trusty-late-init-wq", WQ_UNBOUND, 0); + if (!late_init_wq) { + dev_err(&pdev->dev, "Failed create trusty-late-init-wq\n"); + return -ENODEV; + } + INIT_WORK(&late_init_work, late_init_work_func); + + notif_call_wq = alloc_workqueue("trusty-notif-call-wq", WQ_UNBOUND, 0); + if (!notif_call_wq) { + destroy_workqueue(late_init_wq); + dev_err(&pdev->dev, "Failed create trusty-notif-call-wq\n"); + return -ENODEV; + } + INIT_WORK(¬if_call_work, notif_call_work_func); + + dev_info(&pdev->dev, "%s: done\n", __func__); + + if (!trusty_get_link_shbuf_device(0)) + late_init_work_func(&late_init_work); + + return 0; +} + +static int trusty_remove(struct platform_device *pdev) +{ + unsigned int cpu; + struct trusty_state *s = platform_get_drvdata(pdev); + + device_for_each_child(&pdev->dev, NULL, trusty_remove_child); + + for_each_possible_cpu(cpu) { + struct trusty_work *tw = per_cpu_ptr(s->nop_works, cpu); + + flush_work(&tw->work); + } + free_percpu(s->nop_works); + destroy_workqueue(s->nop_wq); + + trusty_shm_destroy_pool(&pdev->dev); + + mutex_destroy(&s->smc_lock); + if (s->version_str) { + device_remove_file(&pdev->dev, &dev_attr_trusty_version); + kfree(s->version_str); + } + kfree(s); + return 0; +} + +static const struct of_device_id trusty_of_match[] = { + { + .compatible = "android,trusty-smc-v1", + }, + {}, +}; + +static struct platform_driver trusty_driver = { + .probe = trusty_probe_early, + .remove = trusty_remove, + .driver = { + .name = "trusty", + .owner = THIS_MODULE, + .of_match_table = trusty_of_match, + }, +}; + +static int __init trusty_driver_init(void) +{ + return platform_driver_register(&trusty_driver); +} + +static void __exit trusty_driver_exit(void) +{ + platform_driver_unregister(&trusty_driver); +} + +subsys_initcall(trusty_driver_init); +module_exit(trusty_driver_exit); diff --git a/include/linux/trusty/hvcall.h b/include/linux/trusty/hvcall.h new file mode 100644 index 000000000000..91576f02e31e --- /dev/null +++ b/include/linux/trusty/hvcall.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2018 GoldenRiver Technology Co., Ltd. All rights reserved + * Copyright (C) 2021 XiaoMi, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files + * (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Copyright (c) 2013-2014 Google Inc. All rights reserved + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files + * (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __HV_CALL_H__ +#define __HV_CALL_H__ + +/* To prevent redefined with smcall.h */ +#ifndef SMC_NUM_ENTITIES +#define SMC_NUM_ENTITIES 64 +#define SMC_NUM_ARGS 4 +#define SMC_NUM_PARAMS (SMC_NUM_ARGS - 1) + +#define SMC_IS_FASTCALL(smc_nr) ((smc_nr) & 0x80000000) +#define SMC_IS_SMC64(smc_nr) ((smc_nr) & 0x40000000) +#define SMC_ENTITY(smc_nr) (((smc_nr) & 0x3F000000) >> 24) +#define SMC_FUNCTION(smc_nr) ((smc_nr) & 0x0000FFFF) + +#define SMC_NR(_entity, _fn, _fastcall, _smc64) \ + ((((_fastcall) & 0x1) << 31) | (((_smc64) & 0x1) << 30) | \ + (((_entity) & 0x3F) << 24) | ((_fn) & 0xFFFF)) + +#define SMC_FASTCALL_NR(entity, fn) SMC_NR((entity), (fn), 1, 0) +#define SMC_STDCALL_NR(entity, fn) SMC_NR((entity), (fn), 0, 0) +#define SMC_FASTCALL64_NR(entity, fn) SMC_NR((entity), (fn), 1, 1) +#define SMC_STDCALL64_NR(entity, fn) SMC_NR((entity), (fn), 0, 1) +#endif /* end of SMC_NUM_ENTITIES */ + +#define SMC_ENTITY_VM 52 /* VMM SMC Calls */ +#define SMC_ENTITY_PLAT 53 /* PLATFORM SMC Calls */ + +/****************************************************/ +/********** VMM Specific SMC Calls ******************/ +/****************************************************/ +#define SMC_FC_VM_INIT_DONE SMC_FASTCALL_NR(SMC_ENTITY_VM, 100) +#define SMC_FC_VM_STDCALL_SWITCH SMC_FASTCALL_NR(SMC_ENTITY_VM, 101) +#define SMC_FC_CPU_HOTPLUG_ON SMC_FASTCALL_NR(SMC_ENTITY_VM, 110) +#define SMC_FC_CPU_HOTPLUG_OFF SMC_FASTCALL_NR(SMC_ENTITY_VM, 111) +#define SMC_FC_KERNEL_SUSPEND_OFF SMC_FASTCALL_NR(SMC_ENTITY_VM, 112) +#define SMC_FC_KERNEL_SUSPEND_ON SMC_FASTCALL_NR(SMC_ENTITY_VM, 113) +#define SMC_FC_VM_TEST_ADD SMC_FASTCALL_NR(SMC_ENTITY_VM, 200) +#define SMC_FC_VM_TEST_MULTIPLY SMC_FASTCALL_NR(SMC_ENTITY_VM, 201) + +#define SMC_SC_VM_SMC_RETURN SMC_STDCALL_NR(SMC_ENTITY_VM, 100) +#define SMC_SC_VM_STDCALL_DONE SMC_STDCALL_NR(SMC_ENTITY_VM, 101) +#define SMC_SC_VM_SHARED_LOG_VERSION SMC_STDCALL_NR(SMC_ENTITY_VM, 110) +#define SMC_SC_VM_SHARED_LOG_ADD SMC_STDCALL_NR(SMC_ENTITY_VM, 111) +#define SMC_SC_VM_SHARED_LOG_RM SMC_STDCALL_NR(SMC_ENTITY_VM, 112) +#define SMC_SC_VM_NOP SMC_STDCALL_NR(SMC_ENTITY_VM, 120) +#define SMC_SC_VM_NOP_LOCKED SMC_STDCALL_NR(SMC_ENTITY_VM, 121) +#define SMC_SC_VM_RESTART_LAST SMC_STDCALL_NR(SMC_ENTITY_VM, 122) +#define SMC_SC_VM_VIRTIO_GET_DESCR SMC_STDCALL_NR(SMC_ENTITY_VM, 130) +#define SMC_SC_VM_VIRTIO_START SMC_STDCALL_NR(SMC_ENTITY_VM, 131) +#define SMC_SC_VM_VIRTIO_STOP SMC_STDCALL_NR(SMC_ENTITY_VM, 132) +#define SMC_SC_VM_VDEV_RESET SMC_STDCALL_NR(SMC_ENTITY_VM, 133) +#define SMC_SC_VM_VDEV_KICK_VQ SMC_STDCALL_NR(SMC_ENTITY_VM, 134) +#define SMC_SC_VM_TEST_ADD SMC_STDCALL_NR(SMC_ENTITY_VM, 200) +#define SMC_SC_VM_TEST_MULTIPLY SMC_STDCALL_NR(SMC_ENTITY_VM, 201) + +/****************************************************/ +/********** PLATFORM Specific SMC Calls *************/ +/****************************************************/ +#define SMC_FC_PLAT_GET_UART_PA SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 100) +#define SMC_FC_PLAT_REGISTER_IRQ SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 101) +#define SMC_FC_PLAT_GET_NEXT_IRQ SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 102) +#define SMC_FC_PLAT_GET_GIC_VERSION SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 103) +#define SMC_FC_PLAT_GET_GICD_PA SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 104) +#define SMC_FC_PLAT_GET_GICR_PA SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 105) +#define SMC_FC_PLAT_REGISTER_BOOT_ENTRY SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 106) +#define SMC_FC_PLAT_GET_RPMB_KEY SMC_FASTCALL_NR(SMC_ENTITY_PLAT, 107) + +#define SMC_SC_GZ_SHARED_LOG_VERSION SMC_STDCALL_NR(SMC_ENTITY_PLAT, 100) +#define SMC_SC_GZ_SHARED_LOG_ADD SMC_STDCALL_NR(SMC_ENTITY_PLAT, 101) +#define SMC_SC_GZ_SHARED_LOG_RM SMC_STDCALL_NR(SMC_ENTITY_PLAT, 102) +#define SMC_SC_GZ_NOP SMC_STDCALL_NR(SMC_ENTITY_PLAT, 110) +#define SMC_SC_GZ_NOP_LOCKED SMC_STDCALL_NR(SMC_ENTITY_PLAT, 111) +#define SMC_SC_GZ_RESTART_LAST SMC_STDCALL_NR(SMC_ENTITY_PLAT, 112) +#define SMC_SC_PLAT_TEST_MULTIPLY SMC_STDCALL_NR(SMC_ENTITY_PLAT, 115) +#define SMC_SC_PLAT_INIT_SHARE_MEMORY SMC_STDCALL_NR(SMC_ENTITY_PLAT, 120) +#define SMC_SC_PLAT_MTEE_SERVICE_CMD SMC_STDCALL_NR(SMC_ENTITY_PLAT, 121) +#define SMC_SC_GZ_VIRTIO_GET_DESCR SMC_STDCALL_NR(SMC_ENTITY_PLAT, 130) +#define SMC_SC_GZ_VIRTIO_START SMC_STDCALL_NR(SMC_ENTITY_PLAT, 131) +#define SMC_SC_GZ_VIRTIO_STOP SMC_STDCALL_NR(SMC_ENTITY_PLAT, 132) +#define SMC_SC_GZ_VDEV_RESET SMC_STDCALL_NR(SMC_ENTITY_PLAT, 133) +#define SMC_SC_GZ_VDEV_KICK_VQ SMC_STDCALL_NR(SMC_ENTITY_PLAT, 134) + +#endif /* __HV_CALL_H__ */ diff --git a/include/linux/trusty/sm_err.h b/include/linux/trusty/sm_err.h new file mode 100644 index 000000000000..1c096175ccf3 --- /dev/null +++ b/include/linux/trusty/sm_err.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013 Google Inc. All rights reserved + * Copyright (C) 2021 XiaoMi, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files + * (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __LINUX_TRUSTY_SM_ERR_H +#define __LINUX_TRUSTY_SM_ERR_H + +/* Errors from the secure monitor */ +#define SM_ERR_UNDEFINED_SMC \ + 0xFFFFFFFF /* Unknown SMC (defined by ARM DEN 0028A(0.9.0) */ +#define SM_ERR_INVALID_PARAMETERS -2 +#define SM_ERR_INTERRUPTED -3 /* Got interrupted. Call back with restart SMC */ +#define SM_ERR_UNEXPECTED_RESTART \ + -4 /* Got an restart SMC when we didn't expect it */ +#define SM_ERR_BUSY -5 /* Temporarily busy. Call back with original args */ +#define SM_ERR_INTERLEAVED_SMC \ + -6 /* Got a trusted_service SMC when a restart SMC is required */ +#define SM_ERR_INTERNAL_FAILURE -7 /* Unknown error */ +#define SM_ERR_NOT_SUPPORTED -8 +#define SM_ERR_NOT_ALLOWED -9 /* SMC call not allowed */ +#define SM_ERR_END_OF_INPUT -10 +#define SM_ERR_PANIC -11 /* Secure OS crashed */ +#define SM_ERR_FIQ_INTERRUPTED \ + -12 /* Got interrupted by FIQ. Call back with SMC_SC_RESTART_FIQ on same CPU */ +#define SM_ERR_CPU_IDLE -13 /* SMC call waiting for another CPU */ +#define SM_ERR_NOP_INTERRUPTED \ + -14 /* Got interrupted. Call back with new SMC_SC_NOP */ +#define SM_ERR_NOP_DONE -15 /* Cpu idle after SMC_SC_NOP (not an error) */ + +#endif diff --git a/include/linux/trusty/smcall.h b/include/linux/trusty/smcall.h new file mode 100644 index 000000000000..37aa533177b3 --- /dev/null +++ b/include/linux/trusty/smcall.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2018 GoldenRiver Technology Co., Ltd. All rights reserved + * Copyright (C) 2021 XiaoMi, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files + * (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Copyright (c) 2013-2014 Google Inc. All rights reserved + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files + * (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __LINUX_TRUSTY_SMCALL_H +#define __LINUX_TRUSTY_SMCALL_H + +#define SMC_NUM_ENTITIES 64 +#define SMC_NUM_ARGS 4 +#define SMC_NUM_PARAMS (SMC_NUM_ARGS - 1) + +#define SMC_IS_FASTCALL(smc_nr) ((smc_nr) & 0x80000000) +#define SMC_IS_SMC64(smc_nr) ((smc_nr) & 0x40000000) +#define SMC_ENTITY(smc_nr) (((smc_nr) & 0x3F000000) >> 24) +#define SMC_FUNCTION(smc_nr) ((smc_nr) & 0x0000FFFF) + +#define SMC_NR(_entity, _fn, _fastcall, _smc64) \ + ((((_fastcall) & 0x1) << 31) | (((_smc64) & 0x1) << 30) | \ + (((_entity) & 0x3F) << 24) | ((_fn) & 0xFFFF)) + +#define SMC_FASTCALL_NR(entity, fn) SMC_NR((entity), (fn), 1, 0) +#define SMC_STDCALL_NR(entity, fn) SMC_NR((entity), (fn), 0, 0) +#define SMC_FASTCALL64_NR(entity, fn) SMC_NR((entity), (fn), 1, 1) +#define SMC_STDCALL64_NR(entity, fn) SMC_NR((entity), (fn), 0, 1) + +#include "hvcall.h" + +#define SMC_ENTITY_ARCH 0 /* ARM Architecture calls */ +#define SMC_ENTITY_CPU 1 /* CPU Service calls */ +#define SMC_ENTITY_SIP 2 /* SIP Service calls */ +#define SMC_ENTITY_OEM 3 /* OEM Service calls */ +#define SMC_ENTITY_STD 4 /* Standard Service calls */ +#define SMC_ENTITY_RESERVED 5 /* Reserved for future use */ +#define SMC_ENTITY_TRUSTED_APP 48 /* Trusted Application calls */ +#define SMC_ENTITY_TRUSTED_OS SMC_ENTITY_VM /* Trusted OS calls */ +#define SMC_ENTITY_LOGGING \ + SMC_ENTITY_VM /* Used for secure -> nonsecure logging */ +#define SMC_ENTITY_SECURE_MONITOR \ + SMC_ENTITY_VM /* Trusted OS calls internal to secure monitor */ + +/****************************************************/ +/********** Secure Monitor SMC Calls ****************/ +/****************************************************/ +/* Standard call */ +#define SMC_SC_RESTART_LAST SMC_SC_VM_RESTART_LAST +#define SMC_SC_LOCKED_NOP SMC_SC_VM_NOP_LOCKED +#define SMC_SC_RESTART_FIQ SMC_STDCALL_NR(SMC_ENTITY_SECURE_MONITOR, 123) +#define SMC_SC_NOP SMC_SC_VM_NOP +#define SMC_SC_NS_RETURN SMC_SC_VM_SMC_RETURN +/* Fast call */ +#define SMC_FC_RESERVED SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 0) +#define SMC_FC_FIQ_EXIT SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 1) +#define SMC_FC_REQUEST_FIQ SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 2) +#define SMC_FC_GET_NEXT_IRQ SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 3) +#define SMC_FC_FIQ_ENTER SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 4) +#define SMC_FC64_SET_FIQ_HANDLER SMC_FASTCALL64_NR(SMC_ENTITY_SECURE_MONITOR, 5) +#define SMC_FC64_GET_FIQ_REGS SMC_FASTCALL64_NR(SMC_ENTITY_SECURE_MONITOR, 6) +#define SMC_FC_CPU_SUSPEND SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 7) +#define SMC_FC_CPU_RESUME SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 8) +#define SMC_FC_AARCH_SWITCH SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 9) +#define SMC_FC_GET_VERSION_STR SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 10) +#define SMC_FC_API_VERSION SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 11) +#define SMC_FC_FIQ_RESUME SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 12) +#define SMC_FC_IOREMAP_PA_INFO SMC_FASTCALL_NR(SMC_ENTITY_SECURE_MONITOR, 13) + +/****************************************************/ +/********** Trusted OS SMC Calls ********************/ +/****************************************************/ +/* Standard call */ +#define SMC_SC_VIRTIO_GET_DESCR SMC_SC_VM_VIRTIO_GET_DESCR +#define SMC_SC_VIRTIO_START SMC_SC_VM_VIRTIO_START +#define SMC_SC_VIRTIO_STOP SMC_SC_VM_VIRTIO_STOP +#define SMC_SC_VDEV_RESET SMC_SC_VM_VDEV_RESET +#define SMC_SC_VDEV_KICK_VQ SMC_SC_VM_VDEV_KICK_VQ +#define SMC_NC_VDEV_KICK_VQ SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 135) +#define SMC_SC_CREATE_QL_TIPC_DEV SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 136) +#define SMC_SC_SHUTDOWN_QL_TIPC_DEV SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 137) +#define SMC_SC_HANDLE_QL_TIPC_DEV_CMD SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 138) + +/****************************************************/ +/********** Logging SMC Calls ***********************/ +/****************************************************/ +/* Standard call */ +#define SMC_SC_SHARED_LOG_VERSION SMC_SC_VM_SHARED_LOG_VERSION +#define SMC_SC_SHARED_LOG_ADD SMC_SC_VM_SHARED_LOG_ADD +#define SMC_SC_SHARED_LOG_RM SMC_SC_VM_SHARED_LOG_RM + +#define TRUSTY_API_VERSION_RESTART_FIQ (1) +#define TRUSTY_API_VERSION_SMP (2) +#define TRUSTY_API_VERSION_SMP_NOP (3) +#define TRUSTY_API_VERSION_CURRENT (3) + +#endif /* __LINUX_TRUSTY_SMCALL_H */ diff --git a/include/linux/trusty/trusty.h b/include/linux/trusty/trusty.h new file mode 100644 index 000000000000..749f23d5a326 --- /dev/null +++ b/include/linux/trusty/trusty.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_TRUSTY_TRUSTY_H +#define __LINUX_TRUSTY_TRUSTY_H + +#include +#include +#include +#include + +#define TRUSTY_PROBE_DEFER (0x44425054) + +#ifdef CONFIG_TRUSTY +void trusty_probe_late(void); +void trusty_notifier_call(void); +s32 trusty_std_call32(struct device *dev, u32 smcnr, u32 a0, u32 a1, u32 a2); +s32 trusty_fast_call32(struct device *dev, u32 smcnr, u32 a0, u32 a1, u32 a2); +#ifdef CONFIG_64BIT +s64 trusty_fast_call64(struct device *dev, u64 smcnr, u64 a0, u64 a1, u64 a2); +#endif +#else +static inline s32 trusty_std_call32(struct device *dev, u32 smcnr, u32 a0, + u32 a1, u32 a2) +{ + return SM_ERR_UNDEFINED_SMC; +} +static inline s32 trusty_fast_call32(struct device *dev, u32 smcnr, u32 a0, + u32 a1, u32 a2) +{ + return SM_ERR_UNDEFINED_SMC; +} +#ifdef CONFIG_64BIT +static inline s64 trusty_fast_call64(struct device *dev, u64 smcnr, u64 a0, + u64 a1, u64 a2) +{ + return SM_ERR_UNDEFINED_SMC; +} +#endif +#endif + +struct notifier_block; +enum { + TRUSTY_CALL_PREPARE, + TRUSTY_CALL_RETURNED, +}; +int trusty_call_notifier_register(struct device *dev, struct notifier_block *n); +int trusty_call_notifier_unregister(struct device *dev, + struct notifier_block *n); +const char *trusty_version_str_get(struct device *dev); +u32 trusty_get_api_version(struct device *dev); + +struct ns_mem_page_info { + uint64_t attr; +}; + +int trusty_encode_page_info(struct ns_mem_page_info *inf, struct page *page, + pgprot_t pgprot, bool writable); + +int trusty_call32_mem_buf(struct device *dev, u32 smcnr, struct page *page, + u32 size, pgprot_t pgprot, bool writable); + +struct trusty_nop { + struct list_head node; + u32 args[3]; +}; + +static inline void trusty_nop_init(struct trusty_nop *nop, u32 arg0, u32 arg1, + u32 arg2) +{ + INIT_LIST_HEAD(&nop->node); + nop->args[0] = arg0; + nop->args[1] = arg1; + nop->args[2] = arg2; +} + +void trusty_enqueue_nop(struct device *dev, struct trusty_nop *nop); +void trusty_dequeue_nop(struct device *dev, struct trusty_nop *nop); + +#endif diff --git a/include/linux/trusty/trusty_ipc.h b/include/linux/trusty/trusty_ipc.h new file mode 100644 index 000000000000..14c53d3090d2 --- /dev/null +++ b/include/linux/trusty/trusty_ipc.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2015 Google, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_TRUSTY_TRUSTY_IPC_H +#define __LINUX_TRUSTY_TRUSTY_IPC_H + +struct tipc_chan; + +struct tipc_msg_buf { + void *buf_va; + phys_addr_t buf_pa; + size_t buf_sz; + size_t wpos; + size_t rpos; + struct list_head node; +}; + +enum tipc_chan_event { + TIPC_CHANNEL_CONNECTED = 1, + TIPC_CHANNEL_DISCONNECTED, + TIPC_CHANNEL_SHUTDOWN, +}; + +struct tipc_chan_ops { + void (*handle_event)(void *cb_arg, int event); + struct tipc_msg_buf *(*handle_msg)(void *cb_arg, + struct tipc_msg_buf *mb); + void (*handle_release)(void *cb_arg); +}; + +struct tipc_chan *tipc_create_channel(struct device *dev, + const struct tipc_chan_ops *ops, + void *cb_arg); + +int tipc_chan_connect(struct tipc_chan *chan, const char *port); + +int tipc_chan_queue_msg(struct tipc_chan *chan, struct tipc_msg_buf *mb); + +int tipc_chan_shutdown(struct tipc_chan *chan); + +void tipc_chan_destroy(struct tipc_chan *chan); + +struct tipc_msg_buf *tipc_chan_get_rxbuf(struct tipc_chan *chan); + +void tipc_chan_put_rxbuf(struct tipc_chan *chan, struct tipc_msg_buf *mb); + +struct tipc_msg_buf *tipc_chan_get_txbuf_timeout(struct tipc_chan *chan, + long timeout); + +void tipc_chan_put_txbuf(struct tipc_chan *chan, struct tipc_msg_buf *mb); + +static inline size_t mb_avail_space(struct tipc_msg_buf *mb) +{ + return mb->buf_sz - mb->wpos; +} + +static inline size_t mb_avail_data(struct tipc_msg_buf *mb) +{ + return mb->wpos - mb->rpos; +} + +static inline void *mb_put_data(struct tipc_msg_buf *mb, size_t len) +{ + void *pos = (u8 *)mb->buf_va + mb->wpos; + BUG_ON(mb->wpos + len > mb->buf_sz); + mb->wpos += len; + return pos; +} + +static inline void *mb_get_data(struct tipc_msg_buf *mb, size_t len) +{ + void *pos = (u8 *)mb->buf_va + mb->rpos; + BUG_ON(mb->rpos + len > mb->wpos); + mb->rpos += len; + return pos; +} + +#endif /* __LINUX_TRUSTY_TRUSTY_IPC_H */ diff --git a/include/linux/trusty/trusty_shm.h b/include/linux/trusty/trusty_shm.h new file mode 100644 index 000000000000..1f933f678553 --- /dev/null +++ b/include/linux/trusty/trusty_shm.h @@ -0,0 +1,26 @@ +/* + * Copyright 2018 GoldenRiver Technologies Co., Ltd. All rights reserved. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TRUSTY_SHM_H +#define __LINUX_TRUSTY_SHM_H + +void *trusty_shm_alloc(size_t size, gfp_t gfp); +void trusty_shm_free(void *virt, size_t size); +int trusty_shm_init_pool(struct device *dev); +void trusty_shm_destroy_pool(struct device *dev); +phys_addr_t trusty_shm_virt_to_phys(void *vaddr); +void *trusty_shm_phys_to_virt(unsigned long addr); + +#endif diff --git a/include/uapi/linux/virtio_ids.h b/include/uapi/linux/virtio_ids.h index b8947df69d7e..88a1fa044d6f 100644 --- a/include/uapi/linux/virtio_ids.h +++ b/include/uapi/linux/virtio_ids.h @@ -39,6 +39,7 @@ #define VIRTIO_ID_9P 9 /* 9p virtio console */ #define VIRTIO_ID_RPROC_SERIAL 11 /* virtio remoteproc serial link */ #define VIRTIO_ID_CAIF 12 /* Virtio caif */ +#define VIRTIO_ID_TRUSTY_IPC 13 /* virtio trusty ipc */ #define VIRTIO_ID_GPU 16 /* virtio GPU */ #define VIRTIO_ID_INPUT 18 /* virtio input */ #define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */ From b0920a3810fbb3c1909a0808e889e2bc10b918fe Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:46:21 +0200 Subject: [PATCH 094/226] drivers: usb: Import Xiaomi changes Change-Id: I0c11d47f789ffe489a08c9149e94a39c3bad27f0 Signed-off-by: firebird11 --- drivers/usb/core/hub.c | 2 + drivers/usb/dwc3/dwc3-msm.c | 2 + drivers/usb/gadget/configfs.c | 29 ++ drivers/usb/pd/policy_engine.c | 842 +++++++++++++++++++++++++++++++++ drivers/usb/pd/usbpd.h | 56 +++ 5 files changed, 931 insertions(+) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 95a9267f4ffc..db6d4f3c8fc1 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -4825,7 +4825,9 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, /* notify HCD that we have a device connected and addressed */ if (hcd->driver->update_device) hcd->driver->update_device(hcd, udev); +#ifndef CONFIG_MACH_XIAOMI_SM8150 /*disable USB 2.0 Link PM to fix long time usb storage recognition issue*/ hub_set_initial_usb2_lpm_policy(udev); +#endif fail: if (retval) { hub_port_disable(hub, port1, 0); diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index a3f9651b6763..102aaf99f850 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -4939,8 +4939,10 @@ static int dwc3_msm_gadget_vbus_draw(struct dwc3_msm *mdwc, unsigned int mA) * bail out if suspend happened with float cable * connected */ +#ifndef CONFIG_MACH_XIAOMI_SM8150 /* xiaomi charger driver need this current config float current, so remove this qcom default retuen feature. */ if (mA == 2) return 0; +#endif if (!mA) pval.intval = -ETIMEDOUT; diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c index d2a55c1ab7a0..7f29c9f0e568 100644 --- a/drivers/usb/gadget/configfs.c +++ b/drivers/usb/gadget/configfs.c @@ -5,6 +5,9 @@ #include #include #include +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include +#endif #include "configfs.h" #include "u_f.h" #include "u_os_desc.h" @@ -1435,6 +1438,29 @@ static int configfs_composite_bind(struct usb_gadget *gadget, return ret; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int smblib_canncel_recheck(void) +{ + union power_supply_propval pval = {0}; + struct power_supply *usb_psy = NULL; + int rc = 0; + + if (!usb_psy) { + usb_psy = power_supply_get_by_name("usb"); + if (!usb_psy) { + pr_err("Could not get usb psy by canncel recheck\n"); + return -ENODEV; + } + } + + pval.intval = 0; + rc = power_supply_set_property(usb_psy, + POWER_SUPPLY_PROP_TYPE_RECHECK, &pval); + + return rc; +} +#endif + #ifdef CONFIG_USB_CONFIGFS_UEVENT static void android_work(struct work_struct *data) { @@ -1472,6 +1498,9 @@ static void android_work(struct work_struct *data) kobject_uevent_env(&gi->dev->kobj, KOBJ_CHANGE, configured); pr_info("%s: sent uevent %s\n", __func__, configured[0]); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + smblib_canncel_recheck(); +#endif uevent_sent = true; } diff --git a/drivers/usb/pd/policy_engine.c b/drivers/usb/pd/policy_engine.c index ff13ee1e70de..62ed739d4d30 100644 --- a/drivers/usb/pd/policy_engine.c +++ b/drivers/usb/pd/policy_engine.c @@ -354,6 +354,15 @@ static void *usbpd_ipc_log; #define ID_HDR_PRODUCT_AMA 5 #define ID_HDR_PRODUCT_VPD 6 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define PD_VBUS_MAX_VOLTAGE_LIMIT 9000000 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define PD_MAX_CURRENT_LIMIT 4000000 +#endif +#define MAX_FIXED_PDO_MA 2000 +#define MAX_NON_COMPLIANT_PPS_UA 2000000 +#endif + static bool check_vsafe0v = true; module_param(check_vsafe0v, bool, 0600); @@ -454,6 +463,16 @@ struct usbpd { struct regulator *vconn; bool vbus_enabled; bool vconn_enabled; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool vconn_is_external; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + u32 limit_curr; + u32 pd_max_curr_limit; +#else + u32 limit_pd_vbus; + u32 pd_vbus_max_limit; +#endif +#endif u8 tx_msgid[SOPII_MSG + 1]; u8 rx_msgid[SOPII_MSG + 1]; @@ -469,12 +488,33 @@ struct usbpd { struct list_head svid_handlers; ktime_t svdm_start_time; bool vdm_in_suspend; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool verify_process; +#endif struct list_head instance; bool has_dp; u16 ss_lane_svid; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /*for xiaomi verifed pd adapter*/ + u32 adapter_id; + u32 adapter_svid; + struct usbpd_vdm_data vdm_data; + struct usbpd_svid_handler svid_handler; + bool verifed; + int uvdm_state; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool pps_weak_limit; +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* non-qcom pps control */ + bool non_qcom_pps_ctr; +#endif +#endif + /* ext msg support */ bool send_get_src_cap_ext; u8 src_cap_ext_db[PD_SRC_CAP_EXT_DB_LEN]; @@ -836,6 +876,131 @@ static int pd_select_pdo(struct usbpd *pd, int pdo_pos, int uv, int ua) pd->requested_voltage = PD_SRC_PDO_FIXED_VOLTAGE(pdo) * 50 * 1000; + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* pd request uv will less than pd vbus max 9V for fixed pdos */ + if (pd->requested_voltage > PD_VBUS_MAX_VOLTAGE_LIMIT) + return -ENOTSUPP; + + /* + * set maxium allowed current for fixed pdo to 2A if request + * voltage is 9V, as we should limit charger to 18W for more safety + * both for charger and our device(such as charge ic inductor) + */ + if (pd->requested_voltage == PD_VBUS_MAX_VOLTAGE_LIMIT + && curr >= MAX_FIXED_PDO_MA) + curr = MAX_FIXED_PDO_MA; +#endif + + pd->rdo = PD_RDO_FIXED(pdo_pos, 0, mismatch, 1, 1, curr / 10, + max_current / 10); + } else if (type == PD_SRC_PDO_TYPE_AUGMENTED) { + if ((uv / 100000) > PD_APDO_MAX_VOLT(pdo) || + (uv / 100000) < PD_APDO_MIN_VOLT(pdo) || + (ua / 50000) > PD_APDO_MAX_CURR(pdo) || (ua < 0)) { + usbpd_err(&pd->dev, "uv (%d) and ua (%d) out of range of APDO\n", + uv, ua); + return -EINVAL; + } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* use xiaomi pps control state machine */ + if (pd->non_qcom_pps_ctr) { + usbpd_err(&pd->dev, + "PPS is controlled by ourself, return not support\n"); + return -ENOTSUPP; + } + + /* if limit_pd_vbus is enabled, pd request uv will less than pd vbus max */ + if (pd->limit_curr && ua > pd->pd_max_curr_limit) { + ua = pd->pd_max_curr_limit; + } + + if ((pd->pps_weak_limit) && (ua > USBPD_WAKK_PPS_CURR_LIMIT)) { + ua = USBPD_WAKK_PPS_CURR_LIMIT; + } +#endif + + curr = ua / 1000; + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if !defined(CONFIG_MACH_XIAOMI_VAYU) && !defined(CONFIG_MACH_XIAOMI_NABU) + /* if limit_pd_vbus is enabled, pd request uv will less than pd vbus max */ + if (pd->limit_pd_vbus && uv > pd->pd_vbus_max_limit) + uv = pd->pd_vbus_max_limit; +#endif + + /* + * workaround for Zimi and similar non-compliant QC4+/PPS chargers: + * if PPS power limit bit is set and QC4+ not compliant PPS chargers, + * hvdcp_opti will set 0mA for these PPS chargers, we treat them as + * maxium 2A PPS chargers to avoid not charging issue. + */ + if (curr == 0) { + ua = MAX_NON_COMPLIANT_PPS_UA; + curr = ua / 1000; + } +#endif + + pd->requested_voltage = uv; + pd->rdo = PD_RDO_AUGMENTED(pdo_pos, mismatch, 1, 1, + uv / 20000, ua / 50000); + } else { + usbpd_err(&pd->dev, "Only Fixed or Programmable PDOs supported\n"); + return -ENOTSUPP; + } + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* Can't sink more than 5V if VCONN is sourced from the VBUS input */ + if (pd->vconn_enabled && !pd->vconn_is_external && + pd->requested_voltage > 5000000) + return -ENOTSUPP; +#endif + + pd->requested_current = curr; + pd->requested_pdo = pdo_pos; + + return 0; +} + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static int pd_select_pdo_for_bq(struct usbpd *pd, int pdo_pos, int uv, int ua) +{ + int curr; + int max_current; + bool mismatch = false; + u8 type; + u32 pdo = pd->received_pdos[pdo_pos - 1]; + + type = PD_SRC_PDO_TYPE(pdo); + if (type == PD_SRC_PDO_TYPE_FIXED) { + curr = max_current = PD_SRC_PDO_FIXED_MAX_CURR(pdo) * 10; + + /* + * Check if the PDO has enough current, otherwise set the + * Capability Mismatch flag + */ + if (curr < min_sink_current) { + mismatch = true; + max_current = min_sink_current; + } + + pd->requested_voltage = + PD_SRC_PDO_FIXED_VOLTAGE(pdo) * 50 * 1000; + + /* pd request uv will less than pd vbus max 9V for fixed pdos */ + if (pd->requested_voltage > PD_VBUS_MAX_VOLTAGE_LIMIT) + return -ENOTSUPP; + + /* + * set maxium allowed current for fixed pdo to 2A if request + * voltage is 9V, as we should limit charger to 18W for more safety + * both for charger and our device(such as charge ic inductor) + */ + if (pd->requested_voltage == PD_VBUS_MAX_VOLTAGE_LIMIT + && curr >= MAX_FIXED_PDO_MA) + curr = MAX_FIXED_PDO_MA; + pd->rdo = PD_RDO_FIXED(pdo_pos, 0, mismatch, 1, 1, curr / 10, max_current / 10); } else if (type == PD_SRC_PDO_TYPE_AUGMENTED) { @@ -847,7 +1012,27 @@ static int pd_select_pdo(struct usbpd *pd, int pdo_pos, int uv, int ua) return -EINVAL; } + /* if limit_pd_vbus is enabled, pd request uv will less than pd vbus max */ + if (pd->limit_curr && ua > pd->pd_max_curr_limit) { + ua = pd->pd_max_curr_limit; + } + if ((pd->pps_weak_limit) && (ua > USBPD_WAKK_PPS_CURR_LIMIT)) { + ua = USBPD_WAKK_PPS_CURR_LIMIT; + } + curr = ua / 1000; + + /* + * workaround for Zimi and similar non-compliant QC4+/PPS chargers: + * if PPS power limit bit is set and QC4+ not compliant PPS chargers, + * hvdcp_opti will set 0mA for these PPS chargers, we treat them as + * maxium 2A PPS chargers to avoid not charging issue. + */ + if (curr == 0) { + ua = MAX_NON_COMPLIANT_PPS_UA; + curr = ua / 1000; + } + pd->requested_voltage = uv; pd->rdo = PD_RDO_AUGMENTED(pdo_pos, mismatch, 1, 1, uv / 20000, ua / 50000); @@ -861,6 +1046,7 @@ static int pd_select_pdo(struct usbpd *pd, int pdo_pos, int uv, int ua) return 0; } +#endif static int pd_eval_src_caps(struct usbpd *pd) { @@ -868,6 +1054,10 @@ static int pd_eval_src_caps(struct usbpd *pd) union power_supply_propval val; bool pps_found = false; u32 first_pdo = pd->received_pdos[0]; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int max_volt, min_volt, max_curr; + int pps_min_power = 0; +#endif if (PD_SRC_PDO_TYPE(first_pdo) != PD_SRC_PDO_TYPE_FIXED) { usbpd_err(&pd->dev, "First src_cap invalid! %08x\n", first_pdo); @@ -894,6 +1084,34 @@ static int pd_eval_src_caps(struct usbpd *pd) } } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + for (i = 0; i < ARRAY_SIZE(pd->received_pdos); i++) { + u32 pdo = pd->received_pdos[i]; + + if (pdo == 0) + break; + + if (PD_SRC_PDO_TYPE(pdo) == PD_SRC_PDO_TYPE_FIXED) { + max_volt = PD_SRC_PDO_FIXED_VOLTAGE(pdo) * 50; + min_volt = PD_SRC_PDO_FIXED_VOLTAGE(pdo) * 50; + max_curr = PD_SRC_PDO_FIXED_MAX_CURR(pdo) * 10; + } else if (PD_SRC_PDO_TYPE(pdo) == PD_SRC_PDO_TYPE_AUGMENTED) { + max_volt = PD_APDO_MAX_VOLT(pdo) * 100; + min_volt = PD_APDO_MIN_VOLT(pdo) * 100; + max_curr = PD_APDO_MAX_CURR(pdo) * 50; + + if (pps_min_power < max_volt * max_curr || pps_min_power == 0) { + pps_min_power = max_volt * max_curr; + if (pps_min_power < USBPD_WEAK_PPS_POWER) + pd->pps_weak_limit = true; + } + } + usbpd_info(&pd->dev, "%s max_volt:%d,min_volt:%d,max_curr:%d\n", + (PD_SRC_PDO_TYPE(pdo) == PD_SRC_PDO_TYPE_AUGMENTED) ? "PPS" : "PD2.0", + max_volt, min_volt, max_curr); + } +#endif + val.intval = pps_found ? POWER_SUPPLY_PD_PPS_ACTIVE : POWER_SUPPLY_PD_ACTIVE; @@ -2019,6 +2237,15 @@ static void handle_vdm_rx(struct usbpd *pd, struct rx_msg *rx_msg) break; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (num_vdos != 0) { + for (i = 0; i < num_vdos; i++) { + pd->adapter_id = vdos[i] & 0xFFFF; + usbpd_info(&pd->dev, "pd->adapter_id:0x%x\n", pd->adapter_id); + } + } +#endif + pd->vdm_state = DISCOVERED_ID; usbpd_send_svdm(pd, USBPD_SID, USBPD_SVDM_DISCOVER_SVIDS, @@ -2084,6 +2311,9 @@ static void handle_vdm_rx(struct usbpd *pd, struct rx_msg *rx_msg) if (svid) { usbpd_dbg(&pd->dev, "Discovered SVID: 0x%04x\n", svid); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + pd->adapter_svid = svid; +#endif *psvid++ = svid; } } @@ -2127,6 +2357,9 @@ static void handle_vdm_rx(struct usbpd *pd, struct rx_msg *rx_msg) switch (cmd) { case USBPD_SVDM_DISCOVER_IDENTITY: case USBPD_SVDM_DISCOVER_SVIDS: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + pd->uvdm_state = USBPD_UVDM_NAN_ACK; +#endif break; default: break; @@ -2546,6 +2779,14 @@ static void usbpd_sm(struct work_struct *w) pd->peer_usb_comm = pd->peer_pr_swap = pd->peer_dr_swap = false; memset(&pd->received_pdos, 0, sizeof(pd->received_pdos)); rx_msg_cleanup(pd); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + pd->verifed = false; + pd->uvdm_state = USBPD_UVDM_DISCONNECT; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + pd->verify_process = 0; + pd->pps_weak_limit = false; +#endif +#endif power_supply_set_property(pd->usb_psy, POWER_SUPPLY_PROP_PD_IN_HARD_RESET, &val); @@ -4101,6 +4342,11 @@ static ssize_t select_pdo_store(struct device *dev, mutex_lock(&pd->swap_lock); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (pd->verify_process) + goto out; +#endif + /* Only allowed if we are already in explicit sink contract */ if (pd->current_state != PE_SNK_READY) { usbpd_err(&pd->dev, "select_pdo: Cannot select new PDO yet\n"); @@ -4283,6 +4529,11 @@ static ssize_t get_src_cap_ext_show(struct device *dev, int i, ret, len = 0; struct usbpd *pd = dev_get_drvdata(dev); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* as some pps charger do not support this message, do not send */ + return -EINVAL; +#endif + if (pd->spec_rev == USBPD_REV_20) return -EINVAL; @@ -4307,6 +4558,11 @@ static ssize_t get_status_show(struct device *dev, int i, ret, len = 0; struct usbpd *pd = dev_get_drvdata(dev); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* as some pps charger do not support this message, do not send */ + return -EINVAL; +#endif + if (pd->spec_rev == USBPD_REV_20) return -EINVAL; @@ -4331,6 +4587,11 @@ static ssize_t get_pps_status_show(struct device *dev, int ret; struct usbpd *pd = dev_get_drvdata(dev); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* as some pps charger do not support this message, do not send */ + return -EINVAL; +#endif + if (pd->spec_rev == USBPD_REV_20) return -EINVAL; @@ -4410,6 +4671,254 @@ static ssize_t get_battery_status_show(struct device *dev, } static DEVICE_ATTR_RW(get_battery_status); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static ssize_t current_state_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct usbpd *pd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s", + usbpd_state_strings[pd->current_state]); +} +static DEVICE_ATTR_RO(current_state); + +static ssize_t usbpd_verifed_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct usbpd *pd = dev_get_drvdata(dev); + int val, ret; + + if (sscanf(buf, "%d\n", &val) != 1) { + pd->verifed = 0; + return -EINVAL; + } + usbpd_err(&pd->dev, "batterysecret set usbpd verifed :%d\n", val); + + pd->verifed = val; + + if (pd->verifed) { + ret = pd_send_msg(pd, MSG_GET_SOURCE_CAP, NULL, 0, SOP_MSG); + if (ret) { + usbpd_set_state(pd, PE_SEND_SOFT_RESET); + return size; + } + } + + return size; +} + +static ssize_t usbpd_verifed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct usbpd *pd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", pd->verifed); +} +static DEVICE_ATTR_RW(usbpd_verifed); + +static ssize_t adapter_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct usbpd *pd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%08x", pd->adapter_id); +} +static DEVICE_ATTR_RO(adapter_id); + +static ssize_t adapter_svid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct usbpd *pd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%04x", pd->adapter_svid); +} +static DEVICE_ATTR_RO(adapter_svid); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static ssize_t verify_process_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct usbpd *pd = dev_get_drvdata(dev); + int val; + + if (sscanf(buf, "%d\n", &val) != 1) { + pd->verify_process = 0; + return -EINVAL; + } + + pd->verify_process = !!val; + usbpd_info(&pd->dev, "batterysecret verify process :%d\n", pd->verify_process); + + return size; +} + +static ssize_t verify_process_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct usbpd *pd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", pd->verify_process); +} +static DEVICE_ATTR_RW(verify_process); +#endif + +static ssize_t adapter_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct usbpd *pd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%08x", pd->vdm_data.ta_version); +} +static DEVICE_ATTR_RO(adapter_version); + +static int StringToHex(char *str, unsigned char *out, unsigned int *outlen) +{ + char *p = str; + char high = 0, low = 0; + int tmplen = strlen(p), cnt = 0; + tmplen = strlen(p); + while (cnt < (tmplen / 2)) { + high = ((*p > '9') && ((*p <= 'F') || (*p <= 'f'))) ? *p - 48 - 7 : *p - 48; + low = (*(++p) > '9' && ((*p <= 'F') || (*p <= 'f'))) ? *(p) - 48 - 7 : *(p) - 48; + out[cnt] = ((high & 0x0f) << 4 | (low & 0x0f)); + p++; + cnt++; + } + if (tmplen % 2 != 0) + out[cnt] = ((*p > '9') && ((*p <= 'F') || (*p <= 'f'))) ? *p - 48 - 7 : *p - 48; + + if (outlen != NULL) + *outlen = tmplen / 2 + tmplen % 2; + + return tmplen / 2 + tmplen % 2; +} + +#define BSWAP_32(x) \ + (u32)((((u32)(x) & 0xff000000) >> 24) | \ + (((u32)(x) & 0x00ff0000) >> 8) | \ + (((u32)(x) & 0x0000ff00) << 8) | \ + (((u32)(x) & 0x000000ff) << 24)) + +static void usbpd_sha256_bitswap32(unsigned int *array, int len) +{ + int i; + + for (i = 0; i < len; i++) { + array[i] = BSWAP_32(array[i]); + } +} + +static int usbpd_request_vdm_cmd(struct usbpd *pd, enum uvdm_state cmd, unsigned int *data) +{ + u32 vdm_hdr = 0; + int rc = 0; + struct usbpd_svid_handler *hdlr = &pd->svid_handler; + + vdm_hdr = VDM_HDR(hdlr->svid, USBPD_VDM_REQUEST, cmd); + + switch (cmd) { + case USBPD_UVDM_CHARGER_VERSION: + case USBPD_UVDM_CHARGER_TEMP: + case USBPD_UVDM_CHARGER_VOLTAGE: + rc = usbpd_send_vdm(pd, vdm_hdr, NULL, 0); + if (rc < 0) { + usbpd_err(&pd->dev, "failed to send %d\n", cmd); + return rc; + } + break; + case USBPD_UVDM_VERIFIED: +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + case USBPD_UVDM_REMOVE_COMPENSATION: + if (pd->non_qcom_pps_ctr) { + if (cmd == USBPD_UVDM_REMOVE_COMPENSATION) + break; + } +#endif + rc = usbpd_send_vdm(pd, vdm_hdr, data, USBPD_UVDM_VERIFIED_LEN); + if (rc < 0) { + usbpd_err(&pd->dev, "failed to send %d\n", cmd); + return rc; + } + break; + case USBPD_UVDM_SESSION_SEED: + case USBPD_UVDM_AUTHENTICATION: + usbpd_sha256_bitswap32(data, USBPD_UVDM_SS_LEN); + rc = usbpd_send_vdm(pd, vdm_hdr, data, USBPD_UVDM_SS_LEN); + if (rc < 0) { + usbpd_err(&pd->dev, "failed to send %d\n", cmd); + return rc; + } + break; + default: + usbpd_err(&pd->dev, "cmd:%d is not support\n", cmd); + break; + } + + return rc; +} + +static ssize_t request_vdm_cmd_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct usbpd *pd = dev_get_drvdata(dev); + int cmd, ret; + unsigned char buffer[64]; + unsigned char data[32]; + int count; + + ret = sscanf(buf, "%d,%s\n", &cmd, buffer); + + usbpd_dbg(&pd->dev, "%s:cmd:%d, buffer:%s\n", __func__, cmd, buffer); + + StringToHex(buffer, data, &count); + usbpd_request_vdm_cmd(pd, cmd, (unsigned int *)data); + + return size; +} + +static ssize_t request_vdm_cmd_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct usbpd *pd = dev_get_drvdata(dev); + int i; + char data[16], str_buf[128] = {0}; + int cmd = pd->uvdm_state; + + switch (cmd) { + case USBPD_UVDM_CHARGER_VERSION: + return snprintf(buf, PAGE_SIZE, "%d,%x", cmd, pd->vdm_data.ta_version); + break; + case USBPD_UVDM_CHARGER_TEMP: + return snprintf(buf, PAGE_SIZE, "%d,%d", cmd, pd->vdm_data.ta_temp); + break; + case USBPD_UVDM_CHARGER_VOLTAGE: + return snprintf(buf, PAGE_SIZE, "%d,%d", cmd, pd->vdm_data.ta_voltage); + break; + case USBPD_UVDM_SESSION_SEED: + case USBPD_UVDM_CONNECT: + case USBPD_UVDM_DISCONNECT: + case USBPD_UVDM_VERIFIED: + case USBPD_UVDM_NAN_ACK: + return snprintf(buf, PAGE_SIZE, "%d,Null", cmd); + break; + case USBPD_UVDM_AUTHENTICATION: + for (i = 0; i < USBPD_UVDM_SS_LEN; i++) { + memset(data, 0, sizeof(data)); + snprintf(data, sizeof(data), "%08lx", pd->vdm_data.digest[i]); + strlcat(str_buf, data, sizeof(str_buf)); + } + return snprintf(buf, PAGE_SIZE, "%d,%s", cmd, str_buf); + break; + default: + usbpd_err(&pd->dev, "feedbak cmd:%d is not support\n", cmd); + break; + } + return snprintf(buf, PAGE_SIZE, "%d,%s", cmd, str_buf); + +} +static DEVICE_ATTR_RW(request_vdm_cmd); +#endif + static struct attribute *usbpd_attrs[] = { &dev_attr_contract.attr, &dev_attr_initial_pr.attr, @@ -4434,6 +4943,17 @@ static struct attribute *usbpd_attrs[] = { &dev_attr_get_pps_status.attr, &dev_attr_get_battery_cap.attr, &dev_attr_get_battery_status.attr, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + &dev_attr_request_vdm_cmd.attr, + &dev_attr_current_state.attr, + &dev_attr_adapter_id.attr, + &dev_attr_adapter_svid.attr, + &dev_attr_adapter_version.attr, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + &dev_attr_verify_process.attr, +#endif + &dev_attr_usbpd_verifed.attr, +#endif NULL, }; ATTRIBUTE_GROUPS(usbpd); @@ -4504,6 +5024,257 @@ struct usbpd *devm_usbpd_get_by_phandle(struct device *dev, const char *phandle) } EXPORT_SYMBOL(devm_usbpd_get_by_phandle); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static void usbpd_mi_connect_cb(struct usbpd_svid_handler *hdlr, + bool peer_usb_comm) +{ + struct usbpd *pd; + + pd = container_of(hdlr, struct usbpd, svid_handler); + if(!pd) { + pr_err("get_usbpd phandle failed\n"); + return; + } + + pr_debug("peer_usb_comm: %d\n", peer_usb_comm); +// pd->dp_usbpd.base.peer_usb_comm = peer_usb_comm; + + pd->uvdm_state = USBPD_UVDM_CONNECT; + usbpd_info(&pd->dev, "hdlr->svid:%x has connect\n", hdlr->svid); + + return; +} + +static void usbpd_mi_disconnect_cb(struct usbpd_svid_handler *hdlr) +{ + struct usbpd *pd; + + pd = container_of(hdlr, struct usbpd, svid_handler); + + pd->adapter_id = 0; + pd->adapter_svid = 0; + pd->vdm_data.ta_version = 0; + pd->uvdm_state = USBPD_UVDM_DISCONNECT; + usbpd_info(&pd->dev, "hdlr->svid:%x has disconnect\n", hdlr->svid); + + return; +} + +static void usbpd_mi_vdm_received_cb(struct usbpd_svid_handler *hdlr, u32 vdm_hdr, + const u32 *vdos, int num_vdos) +{ + struct usbpd *pd; + int i, cmd; + int usb_current, usb_voltage, r_cable; + union power_supply_propval val = {0}; + int ret; + + pd = container_of(hdlr, struct usbpd, svid_handler); + cmd = UVDM_HDR_CMD(vdm_hdr); + + usbpd_dbg(&pd->dev, "hdlr->svid:0x%x, vdm_hdr:0x%x, num_vdos:%d, cmd:%d\n", + hdlr->svid, vdm_hdr, num_vdos); + + switch (cmd) { + case USBPD_UVDM_CHARGER_VERSION: + pd->vdm_data.ta_version = vdos[0]; + usbpd_dbg(&pd->dev, "ta_version:%x\n", pd->vdm_data.ta_version); + break; + case USBPD_UVDM_CHARGER_TEMP: + pd->vdm_data.ta_temp = (vdos[0] & 0xFFFF) * 10; + usbpd_dbg(&pd->dev, "pd->vdm_data.ta_temp:%d\n", pd->vdm_data.ta_temp); + break; + case USBPD_UVDM_CHARGER_VOLTAGE: + pd->vdm_data.ta_voltage = (vdos[0] & 0xFFFF) * 10; + pd->vdm_data.ta_voltage *= 1000; /*V->mV*/ + usbpd_dbg(&pd->dev, "ta_voltage:%d\n", pd->vdm_data.ta_voltage); + + ret = power_supply_get_property(pd->usb_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, &val); + if (ret) { + usbpd_err(&pd->dev, "failed to get usb voltage now\n"); + break; + } + usb_voltage = val.intval; + usbpd_dbg(&pd->dev, "usb voltage now:%d\n", usb_voltage); + ret = power_supply_get_property(pd->usb_psy, + POWER_SUPPLY_PROP_INPUT_CURRENT_NOW, &val); + if (ret) { + usbpd_err(&pd->dev, "failed to get usb current now\n"); + break; + } + usb_current = val.intval / 1000; + usbpd_dbg(&pd->dev, "usb current now:%d\n", usb_current); + + r_cable = (pd->vdm_data.ta_voltage - usb_voltage) / usb_current; + usbpd_dbg(&pd->dev, "usb r_cable now:%dmohm\n", r_cable); + break; + case USBPD_UVDM_SESSION_SEED: +#ifdef CONFIG_MACH_XIAOMI_NABU + if (num_vdos != 0) { + for (i = 0; i < num_vdos; i++) { + pd->vdm_data.s_secert[i] = vdos[i]; + usbpd_dbg(&pd->dev, "usbpd s_secert vdos[%d]=0x%x", i, vdos[i]); + } + } +#else + for (i = 0; i < USBPD_UVDM_SS_LEN; i++) { + pd->vdm_data.s_secert[i] = vdos[i]; + usbpd_dbg(&pd->dev, "usbpd s_secert vdos[%d]=0x%x", i, vdos[i]); + } +#endif + break; + case USBPD_UVDM_AUTHENTICATION: +#ifdef CONFIG_MACH_XIAOMI_NABU + if (num_vdos != 0) { + for (i = 0; i < num_vdos; i++) { + pd->vdm_data.digest[i] = vdos[i]; + usbpd_dbg(&pd->dev, "usbpd digest[%d]=0x%x", i, vdos[i]); + } + } +#else + for (i = 0; i < USBPD_UVDM_SS_LEN; i++) { + pd->vdm_data.digest[i] = vdos[i]; + usbpd_dbg(&pd->dev, "usbpd digest[%d]=0x%x", i, vdos[i]); + } +#endif + break; + default: + break; + } + pd->uvdm_state = cmd; +} + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +int usbpd_get_pps_status(struct usbpd *pd, u32 *pps_status) +{ + int ret; + + if (pd->spec_rev == USBPD_REV_20) + return -EINVAL; + + ret = trigger_tx_msg(pd, &pd->send_get_pps_status); + if (ret) + return ret; + + *pps_status = pd->pps_status_db; + + return ret; +} +EXPORT_SYMBOL(usbpd_get_pps_status); + +int usbpd_fetch_pdo(struct usbpd *pd, struct usbpd_pdo *pdos) +{ + int ret = 0; + int pdo; + int i; + + if (!pd || !pdos) + return -EINVAL; + + mutex_lock(&pd->swap_lock); + + if (pd->current_pr == PR_SRC) { + usbpd_err(&pd->dev, "not support in SRC mode\n"); + ret = -ENOTSUPP; + goto out; + } + + for (i = 0; i < 7; i++) { + pdo = pd->received_pdos[i]; + if (pdo == 0) + break; + + pdos[i].pos = i + 1; + pdos[i].pps = PD_APDO_PPS(pdo) == 0; + pdos[i].type = PD_SRC_PDO_TYPE(pdo); + + if (pdos[i].type == PD_SRC_PDO_TYPE_FIXED) { + pdos[i].curr_ma = PD_SRC_PDO_FIXED_MAX_CURR(pdo) * 10; + pdos[i].max_volt_mv = PD_SRC_PDO_FIXED_VOLTAGE(pdo) * 50; + pdos[i].min_volt_mv = PD_SRC_PDO_FIXED_VOLTAGE(pdo) * 50; + usbpd_info(&pd->dev, + "pdo:%d, Fixed supply, volt:%d(mv), max curr:%d\n", + i+1, pdos[i].max_volt_mv, + pdos[i].curr_ma); + } else if (pdos[i].type == PD_SRC_PDO_TYPE_AUGMENTED) { + pdos[i].max_volt_mv = PD_APDO_MAX_VOLT(pdo) * 100; + pdos[i].min_volt_mv = PD_APDO_MIN_VOLT(pdo) * 100; + pdos[i].curr_ma = PD_APDO_MAX_CURR(pdo) * 50; + usbpd_info(&pd->dev, + "pdo:%d, PPS, volt: %d(mv), max curr:%d\n", + i+1, pdos[i].max_volt_mv, + pdos[i].curr_ma); + } else { + usbpd_err(&pd->dev, "only fixed and pps pdo supported\n"); + } + } + +out: + mutex_unlock(&pd->swap_lock); + return ret; +} +EXPORT_SYMBOL(usbpd_fetch_pdo); + +int usbpd_select_pdo(struct usbpd *pd, int pdo, int uv, int ua) +{ + int ret; + + mutex_lock(&pd->swap_lock); + + if (pd->verify_process) + goto out; + + if (pd->current_pr != PR_SINK) { + ret = -ENOTSUPP; + goto out; + } + + /* Only allowed if we are already in explicit sink contract */ + if (pd->current_state != PE_SNK_READY || !is_sink_tx_ok(pd)) { + usbpd_err(&pd->dev, "select_pdo: Cannot select new PDO yet\n"); + ret = -EBUSY; + goto out; + } + + if (pdo < 1 || pdo > 7) { + usbpd_err(&pd->dev, "select_pdo: invalid PDO:%d\n", pdo); + ret = -EINVAL; + goto out; + } + + ret = pd_select_pdo_for_bq(pd, pdo, uv, ua); + if (ret) + goto out; + + reinit_completion(&pd->is_ready); + pd->send_request = true; + kick_sm(pd, 0); + + /* wait for operation to complete */ + if (!wait_for_completion_timeout(&pd->is_ready, + msecs_to_jiffies(1000))) { + usbpd_err(&pd->dev, "select_pdo: request timed out\n"); + ret = -ETIMEDOUT; + goto out; + } + + /* determine if request was accepted/rejected */ + if (pd->selected_pdo != pd->requested_pdo || + pd->current_voltage != pd->requested_voltage) { + usbpd_err(&pd->dev, "select_pdo: request rejected\n"); + ret = -EINVAL; + } + +out: + pd->send_request = false; + mutex_unlock(&pd->swap_lock); + return ret; +} +EXPORT_SYMBOL(usbpd_select_pdo); +#endif +#endif + static void usbpd_release(struct device *dev) { struct usbpd *pd = container_of(dev, struct usbpd, dev); @@ -4528,6 +5299,15 @@ struct usbpd *usbpd_create(struct device *parent) int ret; struct usbpd *pd; union power_supply_propval val = {0}; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct usbpd_svid_handler svid_handler = { + .svid = USB_PD_MI_SVID, + .vdm_received = &usbpd_mi_vdm_received_cb, + .connect = &usbpd_mi_connect_cb, + .svdm_received = NULL, + .disconnect = &usbpd_mi_disconnect_cb, + }; +#endif pd = kzalloc(sizeof(*pd), GFP_KERNEL); if (!pd) @@ -4614,6 +5394,60 @@ struct usbpd *usbpd_create(struct device *parent) extcon_set_property_capability(pd->extcon, EXTCON_USB_HOST, EXTCON_PROP_USB_SS); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + ret = of_property_read_u32(parent->of_node, "mi,pd_curr_limit", + &pd->limit_curr); + if (ret) { + usbpd_err(&pd->dev, "do not limit current\n"); + pd->limit_curr = false; + } + + if (pd->limit_curr) { + ret = of_property_read_u32(parent->of_node, "mi,pd_max_curr_limit", + &pd->pd_max_curr_limit); + if (ret) { + usbpd_err(&pd->dev, "failed to read pd vbus max limit\n"); + pd->pd_max_curr_limit = PD_MAX_CURRENT_LIMIT; + } + } + + pd->non_qcom_pps_ctr = of_property_read_bool(parent->of_node, + "mi,non-qcom-pps-ctrl"); +#else + pd->vbus = devm_regulator_get(parent, "vbus"); + if (IS_ERR(pd->vbus)) { + ret = PTR_ERR(pd->vbus); + goto put_psy; + } + + pd->vconn = devm_regulator_get(parent, "vconn"); + if (IS_ERR(pd->vconn)) { + ret = PTR_ERR(pd->vconn); + goto put_psy; + } + + ret = of_property_read_u32(parent->of_node, "mi,limit_pd_vbus", + &pd->limit_pd_vbus); + if (ret) { + usbpd_err(&pd->dev, "failed to read pd vbus limit\n"); + pd->limit_pd_vbus = false; + } + + if (pd->limit_pd_vbus) { + ret = of_property_read_u32(parent->of_node, "mi,pd_vbus_max_limit", + &pd->pd_vbus_max_limit); + if (ret) { + usbpd_err(&pd->dev, "failed to read pd vbus max limit\n"); + pd->pd_vbus_max_limit = PD_VBUS_MAX_VOLTAGE_LIMIT; + } + } +#endif + + pd->vconn_is_external = device_property_present(parent, + "qcom,vconn-uses-external-source"); +#endif + pd->num_sink_caps = device_property_read_u32_array(parent, "qcom,default-sink-caps", NULL, 0); if (pd->num_sink_caps > 0) { @@ -4704,6 +5538,14 @@ struct usbpd *usbpd_create(struct device *parent) if (ret) goto del_inst; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + pd->svid_handler = svid_handler; + ret = usbpd_register_svid(pd, &pd->svid_handler); + if (ret) { + usbpd_err(&pd->dev, "usbpd registration failed\n"); + } +#endif + /* force read initial power_supply values */ psy_changed(&pd->psy_nb, PSY_EVENT_PROP_CHANGED, pd->usb_psy); diff --git a/drivers/usb/pd/usbpd.h b/drivers/usb/pd/usbpd.h index 5c7c5cdf4c7d..fcc59291e332 100644 --- a/drivers/usb/pd/usbpd.h +++ b/drivers/usb/pd/usbpd.h @@ -110,4 +110,60 @@ static inline void pd_phy_close(void) { } #endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +enum uvdm_state { + USBPD_UVDM_DISCONNECT, + USBPD_UVDM_CHARGER_VERSION, + USBPD_UVDM_CHARGER_VOLTAGE, + USBPD_UVDM_CHARGER_TEMP, + USBPD_UVDM_SESSION_SEED, + USBPD_UVDM_AUTHENTICATION, + USBPD_UVDM_VERIFIED, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + USBPD_UVDM_REMOVE_COMPENSATION, +#endif + USBPD_UVDM_CONNECT, + USBPD_UVDM_NAN_ACK, +}; + +#define USB_PD_MI_SVID 0x2717 +#define USBPD_UVDM_SS_LEN 4 +#define USBPD_UVDM_VERIFIED_LEN 1 + +#define VDM_HDR(svid, cmd0, cmd1) \ + (((svid) << 16) | (0 << 15) | ((cmd0) << 8) \ + | (cmd1)) +#define UVDM_HDR_CMD(hdr) ((hdr) & 0xFF) + +#define USBPD_VDM_RANDOM_NUM 4 +#define USBPD_VDM_REQUEST 0x1 +#define USBPD_ACK 0x2 + +struct usbpd_vdm_data { + int ta_version; + int ta_temp; + int ta_voltage; + unsigned long s_secert[USBPD_UVDM_SS_LEN]; + unsigned long digest[USBPD_UVDM_SS_LEN]; +}; + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define USBPD_WEAK_PPS_POWER 18000000 +#define USBPD_WAKK_PPS_CURR_LIMIT 1500000 + +struct usbpd_pdo { + bool pps; + int type; + int max_volt_mv; + int min_volt_mv; + int curr_ma; + int pos; +}; + +int usbpd_get_pps_status(struct usbpd *pd, u32 *status); +int usbpd_fetch_pdo(struct usbpd *pd, struct usbpd_pdo *pdos); +#endif +#endif + #endif /* _USBPD_H */ From 0f2cbd1182223b14ea1b84a5d7d2df8f633c9e9d Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 28 Jan 2024 18:59:29 +0100 Subject: [PATCH 095/226] drivers: video: backlight: Import KTZ8866 driver * From nabu-r-oss * Run clang-format on source files Change-Id: I0a0aac3f9b239503bf2d955b57b847b253ab7316 Signed-off-by: firebird11 --- drivers/video/backlight/Kconfig | 6 + drivers/video/backlight/Makefile | 1 + drivers/video/backlight/ktz8866.c | 277 ++++++++++++++++++++++++++ include/linux/platform_data/ktz8866.h | 256 ++++++++++++++++++++++++ 4 files changed, 540 insertions(+) create mode 100644 drivers/video/backlight/ktz8866.c create mode 100644 include/linux/platform_data/ktz8866.h diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index 298ce75a2178..53087e6288f4 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig @@ -476,6 +476,12 @@ config BACKLIGHT_ARCXCNN If you have an ARCxCnnnn family backlight say Y to enable the backlight driver. +config BACKLIGHT_KTZ8866 + tristate "KTZ8866 Backlight" + depends on I2C + help + If you have a KTZ8866 say Y to enable the backlight driver. + endif # BACKLIGHT_CLASS_DEVICE endif # BACKLIGHT_LCD_SUPPORT diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index f6627e5e2120..fc0487774f7a 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -58,3 +58,4 @@ obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o obj-$(CONFIG_BACKLIGHT_TPS65217) += tps65217_bl.o obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o obj-$(CONFIG_BACKLIGHT_ARCXCNN) += arcxcnn_bl.o +obj-$(CONFIG_BACKLIGHT_KTZ8866) += ktz8866.o diff --git a/drivers/video/backlight/ktz8866.c b/drivers/video/backlight/ktz8866.c new file mode 100644 index 000000000000..b5d574a7e7ce --- /dev/null +++ b/drivers/video/backlight/ktz8866.c @@ -0,0 +1,277 @@ +/* + * KTZ Semiconductor KTZ8866 LED Driver + * + * Copyright (C) 2013 Ideas on board SPRL + * Copyright (C) 2021 XiaoMi, Inc. + * + * Contact: Zhang Teng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define u8 unsigned char + +struct ktz8866 { + struct i2c_client *client; + struct backlight_device *backlight; + struct ktz8866_platform_data *pdata; +}; + +struct ktz8866 *bd; + +static struct ktz8866_led g_ktz8866_led; + +int ktz8866_read(u8 reg, u8 *data) +{ + int ret; + + ret = i2c_smbus_read_byte_data(bd->client, reg); + if (ret < 0) { + dev_err(&bd->client->dev, "failed reading at 0x%02x\n", reg); + return ret; + } + + *data = (uint8_t)ret; + + return 0; +} +EXPORT_SYMBOL(ktz8866_read); + +int ktz8866_write(u8 reg, u8 data) +{ + return i2c_smbus_write_byte_data(bd->client, reg, data); +} +EXPORT_SYMBOL(ktz8866_write); + +static int ktz8866_backlight_update_status(struct backlight_device *backlight) +{ + //struct ktz8866 *bd = bl_get_data(backlight); + int exponential_bl = backlight->props.brightness; + int brightness = 0; + u8 v[2]; + brightness = bl_level_remap[exponential_bl]; + //brightness = exponential_bl; + + if (brightness < 0 || brightness > BL_LEVEL_MAX || + brightness == g_ktz8866_led.level) + return 0; + + mutex_lock(&g_ktz8866_led.lock); + + dev_warn(&bd->client->dev, + "ktz8866 backlight 0x%02x ,exponential brightness %d \n", + brightness, exponential_bl); + if (!g_ktz8866_led.ktz8866_status && brightness > 0) { + ktz8866_write(KTZ8866_DISP_BL_ENABLE, 0x5f); + g_ktz8866_led.ktz8866_status = 1; + dev_warn(&bd->client->dev, + "ktz8866 backlight enable,dimming close"); + } else if (brightness == 0) { + ktz8866_write(KTZ8866_DISP_BL_ENABLE, 0x1f); + g_ktz8866_led.ktz8866_status = 0; + usleep_range((10 * 1000), (10 * 1000) + 10); + dev_warn(&bd->client->dev, + "ktz8866 backlight disable,dimming close"); + } + v[0] = (brightness >> 3) & 0xff; + v[1] = (brightness - (brightness >> 3) * 8) & 0x7; + + //v[0] = brightness & 0xff; + //v[1] = (brightness >> 8) & 0x7; + + ktz8866_write(KTZ8866_DISP_BB_LSB, v[1]); + ktz8866_write(KTZ8866_DISP_BB_MSB, v[0]); + + if (!g_ktz8866_led.dimming_status) { + usleep_range((5 * 1000), (5 * 1000) + 10); + ktz8866_write(KTZ8866_DISP_BC2, 0xbd); + g_ktz8866_led.dimming_status = 1; + dev_warn(&bd->client->dev, "ktz8866 backlight dimming 128ms"); + } + g_ktz8866_led.level = brightness; + mutex_unlock(&g_ktz8866_led.lock); + return 0; +} + +static int ktz8866_backlight_get_brightness(struct backlight_device *backlight) +{ + //struct ktz8866 *bd = bl_get_data(backlight); + int brightness = backlight->props.brightness; + u8 v[2]; + + ktz8866_read(0x5, &v[0]); + ktz8866_read(0x4, &v[1]); + + brightness = (v[1] << 8) + v[0]; + + return brightness; +} + +static const struct backlight_ops ktz8866_backlight_ops = { + .options = BL_CORE_SUSPENDRESUME, + .update_status = ktz8866_backlight_update_status, + .get_brightness = ktz8866_backlight_get_brightness, +}; + +static int ktz8866_backlight_conf(struct ktz8866 *bd) +{ + int ret, i, reg_count; + u8 read; + + dev_warn(&bd->client->dev, "K81 ktz8866_backlight_conf \n"); + + reg_count = ARRAY_SIZE(ktz8866_regs_conf); + for (i = 0; i < reg_count; i++) { + ret = ktz8866_write(ktz8866_regs_conf[i].reg, + ktz8866_regs_conf[i].value); + ktz8866_read(ktz8866_regs_conf[i].reg, &read); + dev_err(&bd->client->dev, "K81 reading 0x%02x is 0x%02x\n", + ktz8866_regs_conf[i].reg, read); + } + + return ret; +} + +static int parse_dt(struct device *dev, struct ktz8866_platform_data *pdata) +{ + struct device_node *np = dev->of_node; + + pdata->hw_en_gpio = + of_get_named_gpio_flags(np, "ktz8866,hwen-gpio", 0, NULL); + + pdata->enp_gpio = + of_get_named_gpio_flags(np, "ktz8866,enp-gpio", 0, NULL); + + pdata->enn_gpio = + of_get_named_gpio_flags(np, "ktz8866,enn-gpio", 0, NULL); + + return 0; +} + +static int ktz8866_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + //struct ktz8866_platform_data *pdata = dev_get_platdata(&client->dev); + struct backlight_device *backlight; + struct backlight_properties props; + int ret; + u8 read; + + dev_warn(&client->dev, + "ktz8866_probe I2C adapter support I2C_FUNC_SMBUS_BYTE\n"); + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_warn( + &client->dev, + "ktz8866 I2C adapter doesn't support I2C_FUNC_SMBUS_BYTE\n"); + return -EIO; + } + dev_warn( + &client->dev, + "ktz8866 i2c_check_functionality I2C adapter support I2C_FUNC_SMBUS_BYTE\n"); + + bd = devm_kzalloc(&client->dev, sizeof(*bd), GFP_KERNEL); + if (!bd) + return -ENOMEM; + dev_warn(&client->dev, "ktz8866 bd = devm_kzalloc \n"); + + bd->client = client; + + bd->pdata = devm_kzalloc( + &client->dev, sizeof(struct ktz8866_platform_data), GFP_KERNEL); + if (!bd->pdata) + return -ENOMEM; + dev_warn(&client->dev, "bd->pdata = devm_kzalloc \n"); + + memset(&props, 0, sizeof(props)); + props.type = BACKLIGHT_RAW; + props.max_brightness = 2047; + props.brightness = clamp_t(unsigned int, 253, 16, props.max_brightness); + dev_warn(&client->dev, "ktz8866 devm_backlight_device_register \n"); + backlight = devm_backlight_device_register( + &client->dev, dev_name(&client->dev), &bd->client->dev, bd, + &ktz8866_backlight_ops, &props); + if (IS_ERR(backlight)) { + dev_err(&client->dev, "K81 failed to register backlight\n"); + return PTR_ERR(backlight); + } + dev_warn(&client->dev, "ktz8866 backlight_update_status \n"); + backlight_update_status(backlight); + dev_warn(&client->dev, "ktz8866 i2c_set_clientdata \n"); + i2c_set_clientdata(client, backlight); + + parse_dt(&client->dev, bd->pdata); + dev_warn(&client->dev, "ktz8866 parse_dt \n"); + + dev_warn(&client->dev, "ktz8866 ktz8866_probe KTZ8866_LCD_DRV_HW_EN\n"); + ret = devm_gpio_request_one(&client->dev, bd->pdata->hw_en_gpio, + GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "HW_EN"); + if (ret < 0) { + dev_err(&client->dev, "unable to request K81 HW_EN GPIO\n"); + return ret; + } + + dev_warn(&client->dev, "K81 ktz8866_backlight_conf \n"); + ktz8866_backlight_conf(bd); + + ktz8866_read(KTZ8866_DISP_FLAGS, &read); + dev_err(&bd->client->dev, "ktz8866 reading 0x%02x is 0x%02x\n", + KTZ8866_DISP_FLAGS, read); + + return ret; +} + +static int ktz8866_remove(struct i2c_client *client) +{ + struct backlight_device *backlight = i2c_get_clientdata(client); + + backlight->props.brightness = 0; + backlight_update_status(backlight); + + return 0; +} + +static const struct i2c_device_id ktz8866_ids[] = { + { "ktz8866", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, ktz8866_ids); + +static struct of_device_id ktz8866_match_table[] = { + { + .compatible = "ktz,ktz8866", + }, + {}, +}; + +static struct i2c_driver ktz8866_driver = { + .driver = { + .name = "ktz8866", + .owner = THIS_MODULE, + .of_match_table = ktz8866_match_table, + }, + .probe = ktz8866_probe, + .remove = ktz8866_remove, + .id_table = ktz8866_ids, +}; + +module_i2c_driver(ktz8866_driver); + +MODULE_DESCRIPTION("zhangteng3 ktz8866 Backlight Driver"); +MODULE_AUTHOR("Laurent Pinchart "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/platform_data/ktz8866.h b/include/linux/platform_data/ktz8866.h new file mode 100644 index 000000000000..b87ec0250a93 --- /dev/null +++ b/include/linux/platform_data/ktz8866.h @@ -0,0 +1,256 @@ +/* + * ktz8866.h - ktz8866 LEDs Driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __KTZ8866_H__ +#define __KTZ8866_H__ + +struct device; + +struct ktz8866_platform_data { + struct device *fbdev; + int hw_en_gpio; + int enp_gpio; + int enn_gpio; +}; + +/* KTZ8866 backlight I2C driver */ +#define KTZ8866_backlight_EN_MASK 0x40 +#define KTZ8866_backlight_EN_SHIFT 6 +#define KTZ8866_backlight_DISABLE 0 +#define KTZ8866_backlight_ENABLE 1 + +#define KTZ8866_LCD_DRV_HW_EN 27 /* GPIO for Active high hardware enable pin */ +#define KTZ8866_LCD_BIAS_ENP \ + 114 /* GPIO for Enable pin for positive power (OUTP) */ +#define KTZ8866_LCD_BIAS_ENN \ + 115 /* GPIO for Enable pin for negative power (OUTN) */ + +#define KTZ8866_LCD_DRV_I2C_SCL 1 /* I2C Clock pin */ +#define KTZ8866_LCD_DRV_I2C_SDA 0 /* I2C Data pin */ + +#define KTZ8866_DISP_ID 0x01 +#define KTZ8866_DISP_BC1 0x02 +#define KTZ8866_DISP_BC2 0x03 +#define KTZ8866_DISP_BB_LSB 0x04 +#define KTZ8866_DISP_BB_MSB 0x05 +#define KTZ8866_DISP_BL_ENABLE 0x08 +#define KTZ8866_DISP_BIAS_CONF1 0x09 +#define KTZ8866_DISP_BIAS_CONF2 0x0a +#define KTZ8866_DISP_BIAS_CONF3 0x0b +#define KTZ8866_DISP_BIAS_BOOST 0x0c +#define KTZ8866_DISP_BIAS_VPOS 0x0d +#define KTZ8866_DISP_BIAS_VNEG 0x0e +#define KTZ8866_DISP_FLAGS 0x0f +#define KTZ8866_DISP_OPTION1 0x10 +#define KTZ8866_DISP_OPTION2 0x11 +#define KTZ8866_DISP_PTD_LSB 0x12 +#define KTZ8866_DISP_PTD_MSB 0x13 +#define KTZ8866_DISP_DIMMING 0x14 +#define KTZ8866_DISP_FULL_CURRENT 0x15 +#define BL_LEVEL_MAX 2047 + +struct ktz8866_reg { + unsigned char reg; + unsigned char value; +}; + +struct ktz8866_led { + struct mutex lock; + int level; + bool ktz8866_status; + bool dimming_status; +}; + +static struct ktz8866_reg ktz8866_regs_conf[] = { + { KTZ8866_DISP_BB_LSB, 0x00 }, /* LSB: limit I2C code 1360 DBV level*/ + { KTZ8866_DISP_BB_MSB, 0xAA }, /* MSB: limit I2C code 1360 DBV level*/ + { KTZ8866_DISP_BC1, + 0x33 }, /* Backlight OVP 26.4V, exponential mapping*/ + { KTZ8866_DISP_FULL_CURRENT, + 0xb1 }, /* Backlight Full-scale LED Current 23mA*/ + { KTZ8866_DISP_BC2, 0xbd }, /* LED ramping time 128ms*/ + { KTZ8866_DISP_DIMMING, 0x11 }, /* LED on/off ramping time 1ms*/ + { KTZ8866_DISP_BIAS_CONF1, + 0x9f }, /* OUTP and OUTN enabled via pin ENP and ENN*/ + { KTZ8866_DISP_BL_ENABLE, 0x5f }, /* KTZ8866_DISP_BL_ENABLE BL_EN*/ +}; + +const int bl_level_remap[BL_LEVEL_MAX + 1] = { + 0, 17, 17, 31, 40, 54, 107, 132, 163, 186, 213, 222, + 241, 260, 279, 300, 321, 330, 349, 365, 379, 395, 408, 419, + 430, 440, 449, 458, 466, 485, 507, 525, 540, 558, 573, 583, + 594, 607, 621, 635, 646, 659, 669, 676, 681, 690, 703, 711, + 720, 728, 738, 746, 751, 759, 768, 775, 783, 789, 797, 804, + 810, 815, 821, 830, 835, 842, 847, 852, 859, 862, 868, 874, + 879, 886, 891, 897, 902, 911, 916, 921, 926, 930, 936, 940, + 944, 948, 952, 957, 962, 966, 970, 974, 978, 980, 984, 988, + 992, 996, 1000, 1004, 1008, 1011, 1014, 1018, 1022, 1025, 1029, 1032, + 1035, 1038, 1040, 1041, 1044, 1048, 1051, 1054, 1057, 1061, 1063, 1065, + 1068, 1071, 1075, 1078, 1081, 1084, 1087, 1090, 1091, 1094, 1096, 1099, + 1102, 1105, 1107, 1108, 1111, 1114, 1117, 1120, 1122, 1124, 1127, 1130, + 1132, 1135, 1138, 1140, 1142, 1146, 1148, 1151, 1153, 1154, 1156, 1159, + 1161, 1163, 1165, 1168, 1170, 1172, 1173, 1176, 1178, 1180, 1182, 1185, + 1187, 1189, 1190, 1193, 1195, 1197, 1199, 1202, 1204, 1206, 1208, 1209, + 1211, 1213, 1215, 1217, 1219, 1221, 1222, 1224, 1225, 1227, 1228, 1230, + 1232, 1234, 1236, 1237, 1238, 1240, 1242, 1243, 1245, 1247, 1249, 1251, + 1252, 1253, 1255, 1256, 1258, 1260, 1262, 1263, 1265, 1268, 1270, 1272, + 1274, 1275, 1276, 1279, 1280, 1282, 1283, 1284, 1286, 1287, 1289, 1290, + 1292, 1293, 1294, 1296, 1297, 1299, 1300, 1302, 1303, 1304, 1305, 1307, + 1308, 1310, 1311, 1313, 1314, 1316, 1317, 1318, 1319, 1321, 1322, 1323, + 1325, 1326, 1328, 1329, 1330, 1332, 1334, 1335, 1337, 1338, 1339, 1341, + 1342, 1343, 1345, 1346, 1347, 1348, 1349, 1351, 1352, 1353, 1354, 1355, + 1356, 1357, 1358, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, 1368, + 1369, 1370, 1371, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, + 1382, 1383, 1384, 1385, 1387, 1388, 1389, 1390, 1391, 1392, 1393, 1395, + 1396, 1397, 1398, 1399, 1400, 1401, 1402, 1403, 1404, 1405, 1406, 1407, + 1408, 1409, 1410, 1411, 1412, 1413, 1414, 1415, 1416, 1417, 1418, 1419, + 1420, 1421, 1422, 1423, 1424, 1425, 1426, 1427, 1428, 1429, 1430, 1431, + 1432, 1433, 1434, 1435, 1436, 1437, 1438, 1439, 1440, 1441, 1442, 1443, + 1444, 1445, 1446, 1447, 1448, 1449, 1450, 1451, 1452, 1453, 1454, 1455, + 1456, 1457, 1457, 1458, 1459, 1460, 1461, 1462, 1463, 1464, 1465, 1466, + 1467, 1467, 1468, 1469, 1470, 1471, 1471, 1472, 1473, 1473, 1474, 1475, + 1476, 1477, 1478, 1479, 1480, 1481, 1481, 1482, 1483, 1484, 1484, 1485, + 1486, 1487, 1488, 1489, 1490, 1490, 1491, 1492, 1493, 1494, 1495, 1496, + 1497, 1498, 1499, 1500, 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508, + 1509, 1510, 1511, 1512, 1513, 1514, 1515, 1516, 1517, 1518, 1519, 1520, + 1521, 1522, 1523, 1524, 1524, 1524, 1524, 1524, 1524, 1524, 1524, 1525, + 1526, 1527, 1528, 1529, 1530, 1531, 1532, 1533, 1534, 1535, 1536, 1537, + 1538, 1539, 1540, 1541, 1542, 1543, 1544, 1545, 1546, 1547, 1548, 1549, + 1550, 1551, 1552, 1552, 1552, 1552, 1552, 1552, 1552, 1552, 1552, 1552, + 1552, 1552, 1552, 1553, 1554, 1554, 1555, 1556, 1556, 1557, 1557, 1558, + 1559, 1559, 1560, 1561, 1562, 1562, 1563, 1564, 1564, 1565, 1565, 1566, + 1566, 1567, 1567, 1567, 1568, 1569, 1569, 1570, 1571, 1572, 1572, 1573, + 1574, 1574, 1575, 1575, 1576, 1577, 1578, 1578, 1579, 1580, 1581, 1582, + 1583, 1584, 1585, 1585, 1586, 1586, 1587, 1587, 1588, 1588, 1588, 1588, + 1589, 1589, 1589, 1589, 1590, 1590, 1590, 1590, 1591, 1592, 1593, 1593, + 1594, 1595, 1596, 1596, 1597, 1597, 1598, 1598, 1599, 1599, 1600, 1600, + 1601, 1602, 1603, 1603, 1604, 1604, 1605, 1605, 1606, 1606, 1607, 1607, + 1608, 1608, 1609, 1609, 1610, 1610, 1611, 1611, 1612, 1612, 1613, 1613, + 1614, 1615, 1615, 1616, 1617, 1617, 1618, 1618, 1619, 1619, 1620, 1620, + 1621, 1621, 1622, 1622, 1623, 1624, 1625, 1626, 1627, 1627, 1628, 1628, + 1629, 1629, 1630, 1630, 1631, 1631, 1632, 1632, 1633, 1633, 1634, 1634, + 1635, 1635, 1636, 1636, 1637, 1638, 1638, 1639, 1640, 1640, 1641, 1641, + 1642, 1642, 1643, 1643, 1644, 1644, 1645, 1645, 1646, 1647, 1647, 1648, + 1648, 1649, 1649, 1650, 1650, 1651, 1651, 1652, 1653, 1653, 1654, 1654, + 1655, 1656, 1656, 1657, 1657, 1658, 1658, 1659, 1659, 1660, 1660, 1661, + 1662, 1662, 1663, 1663, 1664, 1664, 1664, 1665, 1665, 1665, 1666, 1666, + 1667, 1667, 1668, 1668, 1669, 1669, 1670, 1670, 1671, 1671, 1672, 1672, + 1673, 1673, 1674, 1674, 1675, 1675, 1676, 1676, 1676, 1677, 1677, 1678, + 1678, 1679, 1679, 1679, 1680, 1680, 1681, 1681, 1682, 1682, 1683, 1683, + 1684, 1684, 1685, 1685, 1686, 1686, 1686, 1686, 1687, 1687, 1687, 1688, + 1688, 1689, 1689, 1690, 1690, 1691, 1692, 1693, 1693, 1694, 1694, 1695, + 1695, 1696, 1696, 1697, 1697, 1698, 1698, 1699, 1699, 1700, 1700, 1701, + 1701, 1701, 1702, 1702, 1702, 1703, 1703, 1704, 1704, 1705, 1705, 1706, + 1706, 1707, 1707, 1708, 1708, 1709, 1709, 1710, 1710, 1710, 1711, 1711, + 1711, 1712, 1712, 1713, 1713, 1714, 1714, 1715, 1715, 1716, 1716, 1717, + 1717, 1718, 1718, 1719, 1719, 1720, 1720, 1721, 1721, 1722, 1722, 1723, + 1723, 1724, 1724, 1724, 1724, 1725, 1725, 1725, 1726, 1726, 1726, 1727, + 1727, 1728, 1728, 1729, 1729, 1730, 1730, 1730, 1731, 1731, 1732, 1732, + 1732, 1733, 1733, 1733, 1734, 1734, 1734, 1735, 1735, 1736, 1736, 1736, + 1736, 1737, 1737, 1738, 1738, 1739, 1739, 1739, 1740, 1740, 1740, 1741, + 1741, 1741, 1742, 1742, 1743, 1743, 1743, 1744, 1744, 1744, 1745, 1745, + 1746, 1747, 1747, 1748, 1748, 1749, 1749, 1749, 1750, 1750, 1751, 1751, + 1751, 1752, 1752, 1752, 1752, 1753, 1753, 1754, 1754, 1755, 1755, 1756, + 1756, 1756, 1757, 1757, 1757, 1758, 1758, 1759, 1759, 1760, 1760, 1761, + 1761, 1761, 1762, 1762, 1762, 1763, 1763, 1763, 1764, 1764, 1765, 1765, + 1765, 1766, 1766, 1766, 1766, 1767, 1767, 1767, 1767, 1768, 1768, 1769, + 1769, 1770, 1770, 1770, 1771, 1771, 1771, 1772, 1772, 1772, 1773, 1773, + 1773, 1774, 1774, 1775, 1775, 1776, 1776, 1776, 1776, 1777, 1777, 1777, + 1778, 1778, 1778, 1779, 1779, 1779, 1780, 1780, 1781, 1781, 1782, 1782, + 1782, 1783, 1783, 1784, 1784, 1784, 1785, 1785, 1786, 1786, 1787, 1787, + 1788, 1788, 1789, 1789, 1789, 1789, 1790, 1790, 1791, 1791, 1792, 1792, + 1792, 1792, 1793, 1793, 1793, 1793, 1794, 1794, 1794, 1794, 1795, 1795, + 1796, 1796, 1796, 1797, 1797, 1798, 1798, 1799, 1799, 1799, 1800, 1800, + 1800, 1800, 1801, 1801, 1801, 1801, 1802, 1802, 1802, 1803, 1803, 1804, + 1804, 1804, 1805, 1805, 1805, 1805, 1806, 1806, 1806, 1806, 1807, 1807, + 1807, 1807, 1808, 1808, 1809, 1809, 1810, 1810, 1810, 1810, 1811, 1811, + 1811, 1811, 1812, 1812, 1813, 1813, 1814, 1814, 1814, 1814, 1815, 1815, + 1815, 1815, 1815, 1815, 1816, 1816, 1816, 1816, 1816, 1816, 1816, 1816, + 1816, 1816, 1817, 1817, 1817, 1817, 1818, 1818, 1818, 1818, 1819, 1819, + 1819, 1819, 1820, 1820, 1820, 1820, 1821, 1821, 1822, 1822, 1822, 1823, + 1823, 1823, 1824, 1824, 1824, 1824, 1825, 1825, 1825, 1825, 1826, 1826, + 1826, 1826, 1827, 1827, 1828, 1828, 1829, 1829, 1829, 1829, 1830, 1830, + 1830, 1831, 1831, 1832, 1832, 1832, 1833, 1833, 1833, 1833, 1834, 1834, + 1834, 1835, 1835, 1835, 1836, 1836, 1837, 1837, 1837, 1837, 1838, 1838, + 1838, 1838, 1839, 1839, 1840, 1840, 1841, 1841, 1841, 1841, 1842, 1842, + 1842, 1842, 1843, 1843, 1843, 1843, 1844, 1844, 1845, 1845, 1846, 1846, + 1846, 1846, 1847, 1847, 1847, 1848, 1848, 1849, 1849, 1849, 1850, 1850, + 1850, 1850, 1850, 1851, 1851, 1851, 1851, 1852, 1852, 1852, 1853, 1853, + 1854, 1854, 1854, 1855, 1855, 1855, 1855, 1856, 1856, 1856, 1856, 1857, + 1857, 1857, 1857, 1858, 1858, 1858, 1858, 1859, 1859, 1859, 1859, 1860, + 1860, 1861, 1861, 1862, 1862, 1862, 1862, 1863, 1863, 1863, 1863, 1864, + 1864, 1864, 1864, 1865, 1865, 1865, 1865, 1866, 1866, 1866, 1866, 1867, + 1867, 1867, 1867, 1868, 1868, 1868, 1868, 1869, 1869, 1869, 1869, 1870, + 1870, 1870, 1870, 1871, 1871, 1871, 1871, 1872, 1872, 1873, 1873, 1874, + 1874, 1874, 1874, 1875, 1875, 1875, 1875, 1876, 1876, 1876, 1876, 1877, + 1877, 1877, 1877, 1878, 1878, 1878, 1878, 1879, 1879, 1880, 1880, 1881, + 1881, 1881, 1881, 1882, 1882, 1882, 1882, 1883, 1883, 1883, 1883, 1884, + 1884, 1884, 1884, 1885, 1885, 1885, 1885, 1886, 1886, 1886, 1886, 1887, + 1887, 1887, 1887, 1888, 1888, 1888, 1888, 1889, 1889, 1889, 1889, 1890, + 1890, 1890, 1890, 1891, 1891, 1891, 1891, 1892, 1892, 1892, 1893, 1893, + 1893, 1894, 1894, 1895, 1895, 1895, 1895, 1896, 1896, 1896, 1896, 1897, + 1897, 1897, 1897, 1898, 1898, 1898, 1898, 1899, 1899, 1899, 1899, 1900, + 1900, 1900, 1900, 1901, 1901, 1901, 1901, 1902, 1902, 1902, 1902, 1903, + 1903, 1903, 1904, 1904, 1904, 1905, 1905, 1906, 1906, 1906, 1906, 1907, + 1907, 1907, 1907, 1908, 1908, 1908, 1908, 1909, 1909, 1909, 1909, 1910, + 1910, 1910, 1910, 1911, 1911, 1911, 1912, 1912, 1913, 1913, 1913, 1914, + 1914, 1914, 1914, 1914, 1915, 1915, 1915, 1915, 1916, 1916, 1916, 1916, + 1917, 1917, 1917, 1917, 1918, 1918, 1918, 1918, 1919, 1919, 1919, 1919, + 1920, 1920, 1920, 1920, 1921, 1921, 1921, 1921, 1922, 1922, 1922, 1922, + 1923, 1923, 1923, 1923, 1924, 1924, 1924, 1924, 1925, 1925, 1925, 1925, + 1925, 1925, 1925, 1925, 1926, 1926, 1926, 1926, 1927, 1927, 1927, 1927, + 1928, 1928, 1928, 1928, 1929, 1929, 1929, 1929, 1930, 1930, 1930, 1930, + 1931, 1931, 1931, 1931, 1932, 1932, 1932, 1932, 1933, 1933, 1933, 1933, + 1934, 1934, 1934, 1934, 1935, 1935, 1935, 1935, 1935, 1935, 1935, 1935, + 1936, 1936, 1936, 1936, 1937, 1937, 1937, 1937, 1938, 1938, 1938, 1939, + 1939, 1939, 1939, 1939, 1940, 1940, 1940, 1940, 1941, 1941, 1941, 1941, + 1942, 1942, 1942, 1942, 1943, 1943, 1943, 1943, 1944, 1944, 1944, 1944, + 1945, 1945, 1945, 1945, 1946, 1946, 1946, 1946, 1947, 1947, 1947, 1947, + 1948, 1948, 1948, 1948, 1949, 1949, 1949, 1949, 1950, 1950, 1950, 1950, + 1950, 1950, 1950, 1950, 1951, 1951, 1951, 1951, 1952, 1952, 1952, 1952, + 1952, 1952, 1952, 1952, 1953, 1953, 1953, 1953, 1954, 1954, 1954, 1954, + 1955, 1955, 1955, 1955, 1956, 1956, 1956, 1956, 1957, 1957, 1957, 1957, + 1958, 1958, 1958, 1958, 1959, 1959, 1959, 1959, 1960, 1960, 1960, 1960, + 1961, 1961, 1961, 1961, 1962, 1962, 1962, 1962, 1962, 1962, 1962, 1962, + 1963, 1963, 1963, 1963, 1964, 1964, 1964, 1964, 1965, 1965, 1965, 1965, + 1965, 1966, 1966, 1966, 1966, 1967, 1967, 1967, 1967, 1968, 1968, 1968, + 1968, 1969, 1969, 1969, 1969, 1970, 1970, 1970, 1970, 1971, 1971, 1971, + 1971, 1972, 1972, 1972, 1972, 1973, 1973, 1973, 1973, 1974, 1974, 1974, + 1974, 1975, 1975, 1975, 1975, 1976, 1976, 1976, 1976, 1977, 1977, 1977, + 1977, 1978, 1978, 1978, 1978, 1979, 1979, 1979, 1979, 1980, 1980, 1980, + 1980, 1981, 1981, 1981, 1981, 1982, 1982, 1982, 1982, 1983, 1983, 1983, + 1983, 1983, 1983, 1983, 1983, 1984, 1984, 1984, 1984, 1985, 1985, 1985, + 1985, 1986, 1986, 1986, 1986, 1986, 1986, 1986, 1986, 1987, 1987, 1987, + 1987, 1988, 1988, 1988, 1988, 1989, 1989, 1989, 1989, 1989, 1989, 1989, + 1989, 1990, 1990, 1990, 1990, 1991, 1991, 1991, 1991, 1992, 1992, 1992, + 1992, 1993, 1993, 1993, 1993, 1993, 1993, 1993, 1993, 1993, 1993, 1993, + 1993, 1995, 1995, 1995, 1995, 1996, 1996, 1996, 1996, 1996, 1996, 1996, + 1996, 1997, 1997, 1997, 1997, 1998, 1998, 1998, 1998, 1999, 1999, 1999, + 1999, 1999, 1999, 1999, 1999, 2000, 2000, 2000, 2000, 2001, 2001, 2001, + 2001, 2002, 2002, 2002, 2002, 2002, 2002, 2002, 2002, 2003, 2003, 2003, + 2003, 2004, 2004, 2004, 2004, 2004, 2004, 2004, 2004, 2005, 2005, 2005, + 2005, 2006, 2006, 2006, 2006, 2006, 2007, 2007, 2007, 2008, 2008, 2008, + 2008, 2008, 2008, 2008, 2008, 2009, 2009, 2009, 2009, 2010, 2010, 2010, + 2010, 2011, 2011, 2011, 2011, 2011, 2011, 2011, 2011, 2011, 2012, 2012, + 2012, 2012, 2013, 2013, 2013, 2013, 2014, 2014, 2014, 2014, 2015, 2015, + 2015, 2015, 2015, 2015, 2015, 2015, 2016, 2016, 2016, 2016, 2017, 2017, + 2017, 2017, 2018, 2018, 2018, 2018, 2019, 2019, 2019, 2019, 2019, 2019, + 2019, 2019, 2020, 2020, 2020, 2020, 2021, 2021, 2021, 2021, 2021, 2021, + 2021, 2021, 2022, 2022, 2022, 2022, 2023, 2023, 2023, 2023, 2024, 2024, + 2024, 2024, 2025, 2025, 2025, 2025, 2026, 2026, 2026, 2026, 2027, 2027, + 2027, 2027, 2027, 2027, 2027, 2027, 2028, 2028, 2028, 2028, 2029, 2029, + 2029, 2029, 2029, 2029, 2029, 2029, 2030, 2030, 2030, 2030, 2031, 2031, + 2031, 2031, 2032, 2032, 2032, 2032, 2032, 2032, 2033, 2033, 2033, 2033, + 2033, 2033, 2034, 2034, 2034, 2034, 2035, 2035, 2035, 2035, 2036, 2036, + 2036, 2036, 2037, 2037, 2037, 2037, 2037, 2037, 2037, 2037, 2038, 2038, + 2038, 2038, 2039, 2039, 2039, 2039, 2039, 2040, 2040, 2040, 2040, 2040, + 2040, 2041, 2041, 2041, 2041, 2041, 2042, 2042, 2042, 2042, 2042, 2042, + 2042, 2043, 2043, 2043, 2043, 2044, 2044, 2044, 2044, 2045, 2045, 2045, + 2045, 2045, 2046, 2046, 2046, 2047, 2047, 2047 +}; + +#endif From 190ffe45b693c9bbd8401914b86af9333197d66d Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:46:43 +0200 Subject: [PATCH 096/226] drivers: video: backlight: Import Xiaomi changes Change-Id: I0b3488cc6d49d4a9b3cbcaa699489e608e685713 Signed-off-by: firebird11 --- drivers/video/backlight/backlight.c | 12 ++++++++++++ include/linux/backlight.h | 10 ++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c index 8c835f16af82..361e7e5118bf 100644 --- a/drivers/video/backlight/backlight.c +++ b/drivers/video/backlight/backlight.c @@ -24,6 +24,9 @@ static struct list_head backlight_dev_list; static struct mutex backlight_dev_list_mutex; static struct blocking_notifier_head backlight_notifier; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int bl_event; +#endif static const char *const backlight_types[] = { [BACKLIGHT_RAW] = "raw", @@ -181,6 +184,15 @@ int backlight_device_set_brightness(struct backlight_device *bd, rc = -EINVAL; else { pr_debug("set brightness to %lu\n", brightness); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!brightness) { + bl_event = BACKLIGHT_OFF; + blocking_notifier_call_chain(&backlight_notifier, BACKLIGHT_UPDATED, &bl_event); + } else if (bl_event != BACKLIGHT_ON) { + bl_event = BACKLIGHT_ON; + blocking_notifier_call_chain(&backlight_notifier, BACKLIGHT_UPDATED, &bl_event); + } +#endif bd->props.brightness = brightness; rc = backlight_update_status(bd); } diff --git a/include/linux/backlight.h b/include/linux/backlight.h index 16f02e0718b4..f6abdbd274db 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -45,7 +45,17 @@ enum backlight_type { enum backlight_notification { BACKLIGHT_REGISTERED, BACKLIGHT_UNREGISTERED, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + BACKLIGHT_UPDATED, +#endif +}; + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +enum backlight_brightness { + BACKLIGHT_OFF, + BACKLIGHT_ON, }; +#endif struct backlight_device; struct fb_info; From 754b5b749942a688377d9fa9c415d68c65909b8c Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:47:55 +0200 Subject: [PATCH 097/226] fs: pstore: Import Xiaomi changes Change-Id: Icde2a6c8842c67dc8a0c7240069b07d66b149000 Signed-off-by: firebird11 --- fs/pstore/Kconfig | 8 ++++++++ fs/pstore/inode.c | 39 ++++++++++++++++++++++++++++++++++++++ fs/pstore/ram.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/fs/pstore/Kconfig b/fs/pstore/Kconfig index 144e5027fe84..45d5f7f99456 100644 --- a/fs/pstore/Kconfig +++ b/fs/pstore/Kconfig @@ -88,3 +88,11 @@ config PSTORE_RAM "ramoops.ko". For more information, see Documentation/admin-guide/ramoops.rst. + +config PSTORE_LAST_KMSG + bool "export /proc/last_kmsg" + default n + depends on PSTORE + help + When the option is enabled, pstore will export a proc filesystem + interface /proc/last_kmsg. diff --git a/fs/pstore/inode.c b/fs/pstore/inode.c index d814723fb27d..7f3a0f077006 100644 --- a/fs/pstore/inode.c +++ b/fs/pstore/inode.c @@ -36,6 +36,9 @@ #include #include #include +#ifdef CONFIG_PSTORE_LAST_KMSG +#include +#endif #include "internal.h" @@ -294,6 +297,24 @@ bool pstore_is_mounted(void) return pstore_sb != NULL; } +#ifdef CONFIG_PSTORE_LAST_KMSG +static char *console_buffer; +static ssize_t console_bufsize; + +static ssize_t last_kmsg_read(struct file *file, char __user *buf, + size_t len, loff_t *offset) +{ + return simple_read_from_buffer(buf, len, offset, + console_buffer, console_bufsize); +} + +static const struct file_operations last_kmsg_fops = { + .owner = THIS_MODULE, + .read = last_kmsg_read, + .llseek = default_llseek, +}; +#endif + /* * Make a regular file in the root directory of our file system. * Load it up with "size" bytes of data from "buf". @@ -400,6 +421,13 @@ int pstore_mkfile(struct dentry *root, struct pstore_record *record) list_add(&private->list, &allpstore); spin_unlock_irqrestore(&allpstore_lock, flags); +#ifdef CONFIG_PSTORE_LAST_KMSG + if (record->type == PSTORE_TYPE_CONSOLE) { + console_buffer = private->record->buf; + console_bufsize = size; + } +#endif + return 0; fail_private: @@ -485,6 +513,9 @@ static struct file_system_type pstore_fs_type = { static int __init init_pstore_fs(void) { int err; +#ifdef CONFIG_PSTORE_LAST_KMSG + struct proc_dir_entry *last_kmsg_entry = NULL; +#endif /* Create a convenient mount point for people to access pstore */ err = sysfs_create_mount_point(fs_kobj, "pstore"); @@ -495,6 +526,14 @@ static int __init init_pstore_fs(void) if (err < 0) sysfs_remove_mount_point(fs_kobj, "pstore"); +#ifdef CONFIG_PSTORE_LAST_KMSG + last_kmsg_entry = proc_create_data("last_kmsg", S_IFREG | S_IRUGO, + NULL, &last_kmsg_fops, NULL); + if (!last_kmsg_entry) { + pr_err("Failed to create last_kmsg\n"); + goto out; + } +#endif out: return err; } diff --git a/fs/pstore/ram.c b/fs/pstore/ram.c index 73aa3c297701..d9bebdd2a922 100644 --- a/fs/pstore/ram.c +++ b/fs/pstore/ram.c @@ -35,6 +35,9 @@ #include #include #include +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include +#endif #define RAMOOPS_KERNMSG_HDR "====" #define MIN_MEM_SIZE 4096UL @@ -963,6 +966,51 @@ static void ramoops_register_dummy(void) } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static struct ramoops_platform_data ramoops_data; + +static struct platform_device ramoops_dev = { + .name = "ramoops", + .dev = { + .platform_data = &ramoops_data, + }, +}; + +static int __init ramoops_memreserve(char *p) +{ + unsigned long size; + + if (!p) + return 1; + + size = memparse(p, &p) & PAGE_MASK; + ramoops_data.mem_size = size; + ramoops_data.mem_address = 0xB0000000; + ramoops_data.console_size = size / 2; + ramoops_data.pmsg_size = size / 2; + ramoops_data.dump_oops = 1; + + pr_info("msm_reserve_ramoops_memory addr=%llx,size=%lx\n", + ramoops_data.mem_address, ramoops_data.mem_size); + pr_info("msm_reserve_ramoops_memory record_size=%lx,ftrace_size=%lx\n", + ramoops_data.record_size, ramoops_data.ftrace_size); + + memblock_reserve(ramoops_data.mem_address, ramoops_data.mem_size); + + return 0; +} +early_param("ramoops_memreserve", ramoops_memreserve); + +static int __init msm_register_ramoops_device(void) +{ + pr_info("msm_register_ramoops_device\n"); + if (platform_device_register(&ramoops_dev)) + pr_info("Unable to register ramoops platform device\n"); + return 0; +} +core_initcall(msm_register_ramoops_device); +#endif + static int __init ramoops_init(void) { ramoops_register_dummy(); From 9bd7dae8e7496b3b2a773551980b4f1207d09cb0 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 22 Jun 2022 19:55:32 +0200 Subject: [PATCH 098/226] sound: soc: Import Xiaomi changes Change-Id: If6a6823c3d84e95330c37b0bd125e80328f03ebd Signed-off-by: firebird11 --- sound/soc/soc-pcm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c index be75e3fe5e4e..097b987d5ad5 100644 --- a/sound/soc/soc-pcm.c +++ b/sound/soc/soc-pcm.c @@ -46,6 +46,10 @@ static const struct snd_pcm_hardware no_host_hardware = { SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, .formats = SNDRV_PCM_FMTBIT_S16_LE | +#ifdef CONFIG_MACH_XIAOMI_SM8150 + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S24_3LE | +#endif SNDRV_PCM_FMTBIT_S32_LE, .period_bytes_min = PAGE_SIZE >> 2, .period_bytes_max = PAGE_SIZE >> 1, From cd69b16991cf3b1ff82f4f6d66b7b0cdc801e899 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 6 Nov 2023 12:57:40 +0100 Subject: [PATCH 099/226] techpack: audio: Allow ASoC codecs selection through Kconfig * Not every device may want all the additional codecs from OEM, especially on common kernel sources with a lot of codecs Change-Id: I1521f714c90e74f1f674495bee312e28e55cf87a Signed-off-by: firebird11 --- techpack/Kconfig | 2 ++ techpack/audio/Kconfig | 2 ++ techpack/audio/asoc/Kconfig | 1 + techpack/audio/asoc/codecs/Kconfig | 3 +++ techpack/audio/dsp/Kconfig | 3 +++ 5 files changed, 11 insertions(+) create mode 100644 techpack/audio/Kconfig create mode 100644 techpack/audio/asoc/Kconfig create mode 100644 techpack/audio/asoc/codecs/Kconfig create mode 100644 techpack/audio/dsp/Kconfig diff --git a/techpack/Kconfig b/techpack/Kconfig index b3c5013ad893..9f07eebc0410 100644 --- a/techpack/Kconfig +++ b/techpack/Kconfig @@ -1,5 +1,7 @@ menu "Tech packages" +source "techpack/audio/Kconfig" + source "techpack/data/Kconfig" endmenu diff --git a/techpack/audio/Kconfig b/techpack/audio/Kconfig new file mode 100644 index 000000000000..0fd02b6a725d --- /dev/null +++ b/techpack/audio/Kconfig @@ -0,0 +1,2 @@ +source "techpack/audio/asoc/Kconfig" +source "techpack/audio/dsp/Kconfig" diff --git a/techpack/audio/asoc/Kconfig b/techpack/audio/asoc/Kconfig new file mode 100644 index 000000000000..335df2d0d6b7 --- /dev/null +++ b/techpack/audio/asoc/Kconfig @@ -0,0 +1 @@ +source "techpack/audio/asoc/codecs/Kconfig" diff --git a/techpack/audio/asoc/codecs/Kconfig b/techpack/audio/asoc/codecs/Kconfig new file mode 100644 index 000000000000..6fbac4e91012 --- /dev/null +++ b/techpack/audio/asoc/codecs/Kconfig @@ -0,0 +1,3 @@ +menu "Qualcomm ASoC additional codecs" + +endmenu diff --git a/techpack/audio/dsp/Kconfig b/techpack/audio/dsp/Kconfig new file mode 100644 index 000000000000..9d6601d1e644 --- /dev/null +++ b/techpack/audio/dsp/Kconfig @@ -0,0 +1,3 @@ +menu "Qualcomm DSP" + +endmenu From 3ef25e49260a4d1e4cbf6c26e07030296a23ea38 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 7 Jul 2021 16:30:41 +0200 Subject: [PATCH 100/226] techpack: audio: Import Xiaomi drivers * cs35l41: From cepheus-q-oss * tas2557: From cepheus-q-oss * tfa98xx: From cepheus-q-oss * cirrus: From cepheus-q-oss * elliptic: From cepheus-q-oss * mius: From cepheus-q-oss * tas256x: From vayu-r-oss * cs35l41_v2: From nabu-r-oss * Run clang-format on source files Change-Id: If9f9dd884f924ef31d01623f11144134b2c8c206 Signed-off-by: firebird11 --- techpack/audio/Makefile | 8 + techpack/audio/asoc/codecs/Kbuild | 5 + techpack/audio/asoc/codecs/Kconfig | 6 + techpack/audio/asoc/codecs/cs35l41/Android.mk | 55 + techpack/audio/asoc/codecs/cs35l41/Kbuild | 114 + techpack/audio/asoc/codecs/cs35l41/Kconfig | 5 + techpack/audio/asoc/codecs/cs35l41/Makefile | 433 ++ .../audio/asoc/codecs/cs35l41/cs35l41-i2c.c | 123 + .../audio/asoc/codecs/cs35l41/cs35l41-spi.c | 113 + .../asoc/codecs/cs35l41/cs35l41-tables.c | 946 +++ techpack/audio/asoc/codecs/cs35l41/cs35l41.c | 2015 +++++++ techpack/audio/asoc/codecs/cs35l41/cs35l41.h | 766 +++ .../audio/asoc/codecs/cs35l41/cs35l41.txt | 184 + techpack/audio/asoc/codecs/cs35l41/wm_adsp.c | 5106 ++++++++++++++++ techpack/audio/asoc/codecs/cs35l41/wm_adsp.h | 208 + techpack/audio/asoc/codecs/cs35l41/wmfw.h | 202 + .../audio/asoc/codecs/cs35l41_v2/Android.mk | 55 + techpack/audio/asoc/codecs/cs35l41_v2/Kbuild | 125 + techpack/audio/asoc/codecs/cs35l41_v2/Kconfig | 5 + .../asoc/codecs/cs35l41_v2/cs35l41-i2c.c | 121 + .../asoc/codecs/cs35l41_v2/cs35l41-spi.c | 112 + .../asoc/codecs/cs35l41_v2/cs35l41-tables.c | 997 ++++ .../audio/asoc/codecs/cs35l41_v2/cs35l41.c | 3831 ++++++++++++ .../audio/asoc/codecs/cs35l41_v2/cs35l41.h | 842 +++ .../audio/asoc/codecs/cs35l41_v2/cs35l41.txt | 255 + .../codecs/cs35l41_v2/send_data_to_xlog.c | 49 + .../codecs/cs35l41_v2/send_data_to_xlog.h | 26 + .../audio/asoc/codecs/cs35l41_v2/wm_adsp.c | 5167 +++++++++++++++++ .../audio/asoc/codecs/cs35l41_v2/wm_adsp.h | 244 + techpack/audio/asoc/codecs/cs35l41_v2/wmfw.h | 223 + techpack/audio/asoc/codecs/tas2557/Android.mk | 55 + techpack/audio/asoc/codecs/tas2557/Kbuild | 115 + techpack/audio/asoc/codecs/tas2557/Kconfig | 23 + .../audio/asoc/codecs/tas2557/tas2557-codec.c | 673 +++ .../audio/asoc/codecs/tas2557/tas2557-codec.h | 31 + .../audio/asoc/codecs/tas2557/tas2557-core.c | 2397 ++++++++ .../audio/asoc/codecs/tas2557/tas2557-core.h | 86 + .../audio/asoc/codecs/tas2557/tas2557-misc.c | 702 +++ .../audio/asoc/codecs/tas2557/tas2557-misc.h | 60 + .../asoc/codecs/tas2557/tas2557-regmap.c | 964 +++ techpack/audio/asoc/codecs/tas2557/tas2557.h | 485 ++ techpack/audio/asoc/codecs/tas2557/tiload.c | 447 ++ techpack/audio/asoc/codecs/tas2557/tiload.h | 66 + techpack/audio/asoc/codecs/tas256x/Android.mk | 55 + techpack/audio/asoc/codecs/tas256x/Kbuild | 116 + techpack/audio/asoc/codecs/tas256x/Kconfig | 23 + techpack/audio/asoc/codecs/tas256x/Makefile | 9 + techpack/audio/asoc/codecs/tas256x/tas2562.h | 731 +++ techpack/audio/asoc/codecs/tas256x/tas2564.h | 718 +++ .../audio/asoc/codecs/tas256x/tas256x-codec.c | 1956 +++++++ .../audio/asoc/codecs/tas256x/tas256x-codec.h | 33 + .../asoc/codecs/tas256x/tas256x-device.h | 152 + .../asoc/codecs/tas256x/tas256x-regmap.c | 1931 ++++++ techpack/audio/asoc/codecs/tas256x/tas256x.c | 1557 +++++ techpack/audio/asoc/codecs/tas256x/tas256x.h | 647 +++ .../audio/asoc/codecs/tas256x/tas25xx-algo.c | 995 ++++ .../audio/asoc/codecs/tas256x/tas25xx-calib.c | 202 + .../audio/asoc/codecs/tas256x/tas25xx-calib.h | 29 + techpack/audio/asoc/codecs/tfa98xx/Android.mk | 55 + techpack/audio/asoc/codecs/tfa98xx/Kbuild | 120 + techpack/audio/asoc/codecs/tfa98xx/Kconfig | 5 + .../audio/asoc/codecs/tfa98xx/inc/config.h | 44 + .../audio/asoc/codecs/tfa98xx/inc/dbgprint.h | 200 + .../audio/asoc/codecs/tfa98xx/inc/spk-id.h | 33 + techpack/audio/asoc/codecs/tfa98xx/inc/tfa.h | 57 + .../codecs/tfa98xx/inc/tfa1_tfafieldnames.h | 1705 ++++++ .../tfa98xx/inc/tfa2_tfafieldnames_N1C.h | 2930 ++++++++++ .../tfa98xx/inc/tfa9872_tfafieldnames.h | 2312 ++++++++ .../tfa98xx/inc/tfa9874_tfafieldnames.h | 1612 +++++ .../tfa98xx/inc/tfa9887_tfafieldnames.h | 109 + .../tfa98xx/inc/tfa9890_tfafieldnames.h | 140 + .../asoc/codecs/tfa98xx/inc/tfa9891_genregs.h | 1099 ++++ .../tfa98xx/inc/tfa9891_tfafieldnames.h | 1000 ++++ .../tfa98xx/inc/tfa9894_tfafieldnames.h | 2102 +++++++ .../tfa98xx/inc/tfa9896_tfafieldnames.h | 1732 ++++++ .../audio/asoc/codecs/tfa98xx/inc/tfa98xx.h | 189 + .../codecs/tfa98xx/inc/tfa98xx_genregs_N1C.h | 3795 ++++++++++++ .../codecs/tfa98xx/inc/tfa98xx_parameters.h | 744 +++ .../tfa98xx/inc/tfa98xx_tfafieldnames.h | 149 + .../tfa98xx/inc/tfa9912_tfafieldnames.h | 3384 +++++++++++ .../asoc/codecs/tfa98xx/inc/tfa_container.h | 379 ++ .../asoc/codecs/tfa98xx/inc/tfa_device.h | 343 ++ .../asoc/codecs/tfa98xx/inc/tfa_dsp_fw.h | 169 + .../audio/asoc/codecs/tfa98xx/inc/tfa_ext.h | 64 + .../asoc/codecs/tfa98xx/inc/tfa_internal.h | 41 + .../inc/tfa_platform_interface_definition.h | 97 + .../asoc/codecs/tfa98xx/inc/tfa_service.h | 1057 ++++ .../audio/asoc/codecs/tfa98xx/inc/versions.h | 4 + .../audio/asoc/codecs/tfa98xx/src/tfa98xx.c | 4412 ++++++++++++++ .../asoc/codecs/tfa98xx/src/tfa_container.c | 2570 ++++++++ .../audio/asoc/codecs/tfa98xx/src/tfa_debug.c | 439 ++ .../audio/asoc/codecs/tfa98xx/src/tfa_dsp.c | 4165 +++++++++++++ .../audio/asoc/codecs/tfa98xx/src/tfa_init.c | 1727 ++++++ techpack/audio/dsp/Kbuild | 26 + techpack/audio/dsp/Kconfig | 10 + techpack/audio/dsp/apr_elliptic.c | 435 ++ techpack/audio/dsp/apr_mius.c | 464 ++ techpack/audio/dsp/elliptic/Makefile | 28 + techpack/audio/dsp/elliptic/elliptic.c | 776 +++ .../dsp/elliptic/elliptic_mixer_controls.c | 1367 +++++ techpack/audio/dsp/elliptic/elliptic_sysfs.c | 648 +++ .../audio/dsp/elliptic/elliptic_version.h | 8 + .../audio/dsp/elliptic/io_modules/Makefile | 2 + .../io_modules/msm/elliptic_data_msm_io.c | 105 + .../elliptic/io_modules/userspace/Makefile | 2 + .../userspace/elliptic_data_userspace_ctrl.c | 263 + .../userspace/elliptic_data_userspace_io.c | 143 + .../io_modules/userspace_test/Makefile | 2 + .../userspace_test/elliptic_data_io.c | 121 + techpack/audio/dsp/mius/Makefile | 28 + techpack/audio/dsp/mius/io_modules/Makefile | 2 + .../mius/io_modules/msm/mius_data_msm_io.c | 105 + .../dsp/mius/io_modules/userspace/Makefile | 2 + .../userspace/mius_data_userspace_ctrl.c | 263 + .../userspace/mius_data_userspace_io.c | 143 + .../mius/io_modules/userspace_test/Makefile | 2 + .../io_modules/userspace_test/mius_data_io.c | 120 + techpack/audio/dsp/mius/mius.c | 752 +++ techpack/audio/dsp/mius/mius_mixer_controls.c | 1344 +++++ techpack/audio/dsp/mius/mius_sysfs.c | 645 ++ techpack/audio/dsp/mius/mius_version.h | 8 + techpack/audio/dsp/msm-cirrus-playback-v2.c | 1405 +++++ techpack/audio/dsp/msm-cirrus-playback.c | 1550 +++++ techpack/audio/include/dsp/apr_elliptic.h | 41 + techpack/audio/include/dsp/apr_mius.h | 41 + .../include/dsp/msm-cirrus-playback-v2.h | 177 + .../audio/include/dsp/msm-cirrus-playback.h | 183 + techpack/audio/include/dsp/tas_smart_amp_v2.h | 177 + .../audio/include/elliptic/elliptic_data_io.h | 155 + .../audio/include/elliptic/elliptic_device.h | 50 + .../elliptic/elliptic_mixer_controls.h | 185 + .../audio/include/elliptic/elliptic_sysfs.h | 14 + techpack/audio/include/mius/mius_data_io.h | 155 + techpack/audio/include/mius/mius_device.h | 49 + .../audio/include/mius/mius_mixer_controls.h | 183 + techpack/audio/include/mius/mius_sysfs.h | 14 + techpack/audio/include/uapi/sound/cs35l41.h | 84 + .../audio/include/uapi/sound/cs35l41_v2.h | 137 + .../include/uapi/sound/msm-cirrus-playback.h | 119 + 139 files changed, 89115 insertions(+) create mode 100755 techpack/audio/asoc/codecs/cs35l41/Android.mk create mode 100755 techpack/audio/asoc/codecs/cs35l41/Kbuild create mode 100755 techpack/audio/asoc/codecs/cs35l41/Kconfig create mode 100755 techpack/audio/asoc/codecs/cs35l41/Makefile create mode 100644 techpack/audio/asoc/codecs/cs35l41/cs35l41-i2c.c create mode 100644 techpack/audio/asoc/codecs/cs35l41/cs35l41-spi.c create mode 100644 techpack/audio/asoc/codecs/cs35l41/cs35l41-tables.c create mode 100644 techpack/audio/asoc/codecs/cs35l41/cs35l41.c create mode 100644 techpack/audio/asoc/codecs/cs35l41/cs35l41.h create mode 100755 techpack/audio/asoc/codecs/cs35l41/cs35l41.txt create mode 100644 techpack/audio/asoc/codecs/cs35l41/wm_adsp.c create mode 100644 techpack/audio/asoc/codecs/cs35l41/wm_adsp.h create mode 100644 techpack/audio/asoc/codecs/cs35l41/wmfw.h create mode 100755 techpack/audio/asoc/codecs/cs35l41_v2/Android.mk create mode 100755 techpack/audio/asoc/codecs/cs35l41_v2/Kbuild create mode 100755 techpack/audio/asoc/codecs/cs35l41_v2/Kconfig create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-i2c.c create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-spi.c create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-tables.c create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.c create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.h create mode 100755 techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.txt create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.c create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.h create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.c create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.h create mode 100644 techpack/audio/asoc/codecs/cs35l41_v2/wmfw.h create mode 100755 techpack/audio/asoc/codecs/tas2557/Android.mk create mode 100755 techpack/audio/asoc/codecs/tas2557/Kbuild create mode 100644 techpack/audio/asoc/codecs/tas2557/Kconfig create mode 100644 techpack/audio/asoc/codecs/tas2557/tas2557-codec.c create mode 100755 techpack/audio/asoc/codecs/tas2557/tas2557-codec.h create mode 100644 techpack/audio/asoc/codecs/tas2557/tas2557-core.c create mode 100644 techpack/audio/asoc/codecs/tas2557/tas2557-core.h create mode 100644 techpack/audio/asoc/codecs/tas2557/tas2557-misc.c create mode 100644 techpack/audio/asoc/codecs/tas2557/tas2557-misc.h create mode 100644 techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c create mode 100644 techpack/audio/asoc/codecs/tas2557/tas2557.h create mode 100644 techpack/audio/asoc/codecs/tas2557/tiload.c create mode 100644 techpack/audio/asoc/codecs/tas2557/tiload.h create mode 100644 techpack/audio/asoc/codecs/tas256x/Android.mk create mode 100644 techpack/audio/asoc/codecs/tas256x/Kbuild create mode 100644 techpack/audio/asoc/codecs/tas256x/Kconfig create mode 100644 techpack/audio/asoc/codecs/tas256x/Makefile create mode 100644 techpack/audio/asoc/codecs/tas256x/tas2562.h create mode 100644 techpack/audio/asoc/codecs/tas256x/tas2564.h create mode 100644 techpack/audio/asoc/codecs/tas256x/tas256x-codec.c create mode 100644 techpack/audio/asoc/codecs/tas256x/tas256x-codec.h create mode 100644 techpack/audio/asoc/codecs/tas256x/tas256x-device.h create mode 100644 techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c create mode 100644 techpack/audio/asoc/codecs/tas256x/tas256x.c create mode 100644 techpack/audio/asoc/codecs/tas256x/tas256x.h create mode 100644 techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c create mode 100644 techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c create mode 100644 techpack/audio/asoc/codecs/tas256x/tas25xx-calib.h create mode 100755 techpack/audio/asoc/codecs/tfa98xx/Android.mk create mode 100755 techpack/audio/asoc/codecs/tfa98xx/Kbuild create mode 100644 techpack/audio/asoc/codecs/tfa98xx/Kconfig create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/config.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/dbgprint.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa1_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa2_tfafieldnames_N1C.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9872_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9874_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9887_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9890_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_genregs.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9894_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9896_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_genregs_N1C.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_parameters.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa9912_tfafieldnames.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa_container.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa_device.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa_dsp_fw.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa_ext.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa_internal.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa_platform_interface_definition.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/tfa_service.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/versions.h create mode 100644 techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c create mode 100644 techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c create mode 100644 techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c create mode 100644 techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c create mode 100644 techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c create mode 100644 techpack/audio/dsp/apr_elliptic.c create mode 100644 techpack/audio/dsp/apr_mius.c create mode 100644 techpack/audio/dsp/elliptic/Makefile create mode 100644 techpack/audio/dsp/elliptic/elliptic.c create mode 100644 techpack/audio/dsp/elliptic/elliptic_mixer_controls.c create mode 100644 techpack/audio/dsp/elliptic/elliptic_sysfs.c create mode 100755 techpack/audio/dsp/elliptic/elliptic_version.h create mode 100644 techpack/audio/dsp/elliptic/io_modules/Makefile create mode 100644 techpack/audio/dsp/elliptic/io_modules/msm/elliptic_data_msm_io.c create mode 100644 techpack/audio/dsp/elliptic/io_modules/userspace/Makefile create mode 100644 techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c create mode 100644 techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_io.c create mode 100644 techpack/audio/dsp/elliptic/io_modules/userspace_test/Makefile create mode 100644 techpack/audio/dsp/elliptic/io_modules/userspace_test/elliptic_data_io.c create mode 100644 techpack/audio/dsp/mius/Makefile create mode 100644 techpack/audio/dsp/mius/io_modules/Makefile create mode 100644 techpack/audio/dsp/mius/io_modules/msm/mius_data_msm_io.c create mode 100644 techpack/audio/dsp/mius/io_modules/userspace/Makefile create mode 100644 techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_ctrl.c create mode 100644 techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_io.c create mode 100644 techpack/audio/dsp/mius/io_modules/userspace_test/Makefile create mode 100644 techpack/audio/dsp/mius/io_modules/userspace_test/mius_data_io.c create mode 100644 techpack/audio/dsp/mius/mius.c create mode 100644 techpack/audio/dsp/mius/mius_mixer_controls.c create mode 100644 techpack/audio/dsp/mius/mius_sysfs.c create mode 100644 techpack/audio/dsp/mius/mius_version.h create mode 100644 techpack/audio/dsp/msm-cirrus-playback-v2.c create mode 100644 techpack/audio/dsp/msm-cirrus-playback.c create mode 100644 techpack/audio/include/dsp/apr_elliptic.h create mode 100644 techpack/audio/include/dsp/apr_mius.h create mode 100644 techpack/audio/include/dsp/msm-cirrus-playback-v2.h create mode 100644 techpack/audio/include/dsp/msm-cirrus-playback.h create mode 100644 techpack/audio/include/dsp/tas_smart_amp_v2.h create mode 100644 techpack/audio/include/elliptic/elliptic_data_io.h create mode 100644 techpack/audio/include/elliptic/elliptic_device.h create mode 100644 techpack/audio/include/elliptic/elliptic_mixer_controls.h create mode 100644 techpack/audio/include/elliptic/elliptic_sysfs.h create mode 100644 techpack/audio/include/mius/mius_data_io.h create mode 100644 techpack/audio/include/mius/mius_device.h create mode 100644 techpack/audio/include/mius/mius_mixer_controls.h create mode 100644 techpack/audio/include/mius/mius_sysfs.h create mode 100644 techpack/audio/include/uapi/sound/cs35l41.h create mode 100644 techpack/audio/include/uapi/sound/cs35l41_v2.h create mode 100644 techpack/audio/include/uapi/sound/msm-cirrus-playback.h diff --git a/techpack/audio/Makefile b/techpack/audio/Makefile index 304c00aa49d9..185b633a5716 100644 --- a/techpack/audio/Makefile +++ b/techpack/audio/Makefile @@ -45,8 +45,16 @@ USERINCLUDE += \ # Needed to be compatible with the O= option LINUXINCLUDE += \ -I$(srctree)/techpack/audio/include/uapi \ + -I$(srctree)/techpack/audio/include/elliptic \ -I$(srctree)/techpack/audio/include +#for mius start +ifeq ($(CONFIG_US_PROXIMITY), y) +LINUXINCLUDE += \ + -I$(srctree)/techpack/audio/include/mius +endif +#for mius end + ifeq ($(CONFIG_ARCH_SDM845), y) LINUXINCLUDE += \ -include $(srctree)/techpack/audio/config/sdm845autoconf.h diff --git a/techpack/audio/asoc/codecs/Kbuild b/techpack/audio/asoc/codecs/Kbuild index a52da6d08cac..13fd8bbc41c2 100644 --- a/techpack/audio/asoc/codecs/Kbuild +++ b/techpack/audio/asoc/codecs/Kbuild @@ -210,6 +210,11 @@ ifeq ($(KERNEL_BUILD), 1) obj-y += wcd9360/ obj-y += wcd937x/ obj-y += bolero/ + obj-y += cs35l41/ + obj-y += cs35l41_v2/ + obj-y += tas2557/ + obj-y += tas256x/ + obj-y += tfa98xx/ endif ifeq ($(CONFIG_SND_SOC_GCOV), y) diff --git a/techpack/audio/asoc/codecs/Kconfig b/techpack/audio/asoc/codecs/Kconfig index 6fbac4e91012..8f87d049ba09 100644 --- a/techpack/audio/asoc/codecs/Kconfig +++ b/techpack/audio/asoc/codecs/Kconfig @@ -1,3 +1,9 @@ menu "Qualcomm ASoC additional codecs" +source "techpack/audio/asoc/codecs/cs35l41/Kconfig" +source "techpack/audio/asoc/codecs/cs35l41_v2/Kconfig" +source "techpack/audio/asoc/codecs/tas2557/Kconfig" +source "techpack/audio/asoc/codecs/tas256x/Kconfig" +source "techpack/audio/asoc/codecs/tfa98xx/Kconfig" + endmenu diff --git a/techpack/audio/asoc/codecs/cs35l41/Android.mk b/techpack/audio/asoc/codecs/cs35l41/Android.mk new file mode 100755 index 000000000000..9b2b116f0487 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/Android.mk @@ -0,0 +1,55 @@ +# Android makefile for audio kernel modules + +# Assume no targets will be supported + +# Check if this driver needs be built for current target +ifeq ($(call is-board-platform,msmnile),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m +endif + +ifeq ($(call is-board-platform,$(MSMSTEPPE)),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m +endif + +AUDIO_CHIPSET := audio +# Build/Package only in case of supported target +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE)),true) + +LOCAL_PATH := $(call my-dir) + +# This makefile is only for DLKM +ifneq ($(findstring vendor,$(LOCAL_PATH)),) + +ifneq ($(findstring opensource,$(LOCAL_PATH)),) + #AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/vendor/qcom/opensource/audio-kernel + AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel +endif # opensource + +DLKM_DIR := $(TOP)/device/qcom/common/dlkm + +# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko +########################################################### +# This is set once per LOCAL_PATH, not per (kernel) module +KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR) + +# We are actually building audio.ko here, as per the +# requirement we are specifying _audio.ko as LOCAL_MODULE. +# This means we need to rename the module to _audio.ko +# after audio.ko is built. +KBUILD_OPTIONS += MODNAME=cs35l41_dlkm +KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM) +KBUILD_OPTIONS += $(AUDIO_SELECT) + +########################################################### +include $(CLEAR_VARS) +LOCAL_MODULE := $(AUDIO_CHIPSET)_cs35l41.ko +LOCAL_MODULE_KBUILD_NAME := cs35l41_dlkm.ko +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +include $(DLKM_DIR)/AndroidKernelModule.mk +########################################################### +########################################################### + +endif # DLKM check +endif # supported target check diff --git a/techpack/audio/asoc/codecs/cs35l41/Kbuild b/techpack/audio/asoc/codecs/cs35l41/Kbuild new file mode 100755 index 000000000000..e7af92f568a1 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/Kbuild @@ -0,0 +1,114 @@ +# We can build either as part of a standalone Kernel build or as +# an external module. Determine which mechanism is being used +ifeq ($(MODNAME),) + KERNEL_BUILD := 1 +else + KERNEL_BUILD := 0 +endif + + + +ifeq ($(KERNEL_BUILD), 1) + # These are configurable via Kconfig for kernel-based builds + # Need to explicitly configure for Android-based builds + AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/kernel/msm-4.14 + AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio +endif + +ifeq ($(KERNEL_BUILD), 0) + ifeq ($(CONFIG_ARCH_SM8150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + ifeq ($(CONFIG_ARCH_SM6150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + + ifeq ($(CONFIG_ARCH_SDMSHRIKE), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif +endif + +# As per target team, build is done as follows: +# Defconfig : build with default flags +# Slub : defconfig + CONFIG_SLUB_DEBUG := y + +# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y +# Perf : Using appropriate msmXXXX-perf_defconfig +# +# Shipment builds (user variants) should not have any debug feature +# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds +# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since +# there is no other way to identify defconfig builds, QTI internal +# representation of perf builds (identified using the string 'perf'), +# is used to identify if the build is a slub or defconfig one. This +# way no critical debug feature will be enabled for perf and shipment +# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT +# config. + +############ UAPI ############ +UAPI_DIR := uapi +UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR) + +############ COMMON ############ +COMMON_DIR := include +COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR) + +############ CS35L41 ############ + +# for CS35L41 Codec +ifdef CONFIG_SND_SOC_CS35L41 + CS35L41_OBJS += cs35l41.o + CS35L41_OBJS += cs35l41-i2c.o + CS35L41_OBJS += cs35l41-tables.o + CS35L41_OBJS += wm_adsp.o +endif + +LINUX_INC += -Iinclude/linux + +INCS += $(COMMON_INC) \ + $(UAPI_INC) + +EXTRA_CFLAGS += $(INCS) + + +CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ + -DANI_LITTLE_BIT_ENDIAN \ + -DDOT11F_LITTLE_ENDIAN_HOST \ + -DANI_COMPILER_TYPE_GCC \ + -DANI_OS_TYPE_ANDROID=6 \ + -DPTT_SOCK_SVC_ENABLE \ + -Wall\ + -Werror\ + -D__linux__ + +KBUILD_CPPFLAGS += $(CDEFINES) + +# Currently, for versions of gcc which support it, the kernel Makefile +# is disabling the maybe-uninitialized warning. Re-enable it for the +# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it +# will override the kernel settings. +ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y) +EXTRA_CFLAGS += -Wmaybe-uninitialized +endif +#EXTRA_CFLAGS += -Wmissing-prototypes + +ifeq ($(call cc-option-yn, -Wheader-guard),y) +EXTRA_CFLAGS += -Wheader-guard +endif + +ifeq ($(KERNEL_BUILD), 0) +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers +endif + +# Module information used by KBuild framework +obj-$(CONFIG_SND_SOC_CS35L41) += cs35l41_dlkm.o +cs35l41_dlkm-y := $(CS35L41_OBJS) diff --git a/techpack/audio/asoc/codecs/cs35l41/Kconfig b/techpack/audio/asoc/codecs/cs35l41/Kconfig new file mode 100755 index 000000000000..7a21d8b67413 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/Kconfig @@ -0,0 +1,5 @@ +config SND_SOC_CS35L41 + tristate "Cirrus Logic CS35L41 codec" + help + Say Y or M here if you want to add support for the Cirrus Logic + CS35L41 codec. diff --git a/techpack/audio/asoc/codecs/cs35l41/Makefile b/techpack/audio/asoc/codecs/cs35l41/Makefile new file mode 100755 index 000000000000..e7e3ce8cf43a --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/Makefile @@ -0,0 +1,433 @@ +snd-soc-88pm860x-objs := 88pm860x-codec.o +snd-soc-ab8500-codec-objs := ab8500-codec.o +snd-soc-ac97-objs := ac97.o +snd-soc-ad1836-objs := ad1836.o +snd-soc-ad193x-objs := ad193x.o +snd-soc-ad193x-spi-objs := ad193x-spi.o +snd-soc-ad193x-i2c-objs := ad193x-i2c.o +snd-soc-ad1980-objs := ad1980.o +snd-soc-ad73311-objs := ad73311.o +snd-soc-adau1373-objs := adau1373.o +snd-soc-adau1701-objs := adau1701.o +snd-soc-adau17x1-objs := adau17x1.o +snd-soc-adau1761-objs := adau1761.o +snd-soc-adau1761-i2c-objs := adau1761-i2c.o +snd-soc-adau1761-spi-objs := adau1761-spi.o +snd-soc-adau1781-objs := adau1781.o +snd-soc-adau1781-i2c-objs := adau1781-i2c.o +snd-soc-adau1781-spi-objs := adau1781-spi.o +snd-soc-adau1977-objs := adau1977.o +snd-soc-adau1977-spi-objs := adau1977-spi.o +snd-soc-adau1977-i2c-objs := adau1977-i2c.o +snd-soc-adav80x-objs := adav80x.o +snd-soc-adav801-objs := adav801.o +snd-soc-adav803-objs := adav803.o +snd-soc-ads117x-objs := ads117x.o +snd-soc-ak4104-objs := ak4104.o +snd-soc-ak4535-objs := ak4535.o +snd-soc-ak4554-objs := ak4554.o +snd-soc-ak4613-objs := ak4613.o +snd-soc-ak4641-objs := ak4641.o +snd-soc-ak4642-objs := ak4642.o +snd-soc-ak4671-objs := ak4671.o +snd-soc-ak5386-objs := ak5386.o +snd-soc-arizona-objs := arizona.o +snd-soc-cq93vc-objs := cq93vc.o +snd-soc-cirrus-psia-objs := cirrus-psia.o +snd-soc-cs35l32-objs := cs35l32.o +snd-soc-cs35l33-objs := cs35l33.o +snd-soc-cs35l34-objs := cs35l34.o +snd-soc-cs35l35-objs := cs35l35.o +snd-soc-cs35l36-objs := cs35l36.o cs35l36-tables.o +snd-soc-cs35l41-objs := cs35l41.o +snd-soc-cs35l41-spi-objs := cs35l41-spi.o cs35l41-tables.o +snd-soc-cs35l41-i2c-objs := cs35l41-i2c.o cs35l41-tables.o +snd-soc-cs42l42-objs := cs42l42.o +snd-soc-cs42l51-objs := cs42l51.o +snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o +snd-soc-cs42l52-objs := cs42l52.o +snd-soc-cs42l56-objs := cs42l56.o +snd-soc-cs42l73-objs := cs42l73.o +snd-soc-cs4265-objs := cs4265.o +snd-soc-cs4270-objs := cs4270.o +snd-soc-cs4271-objs := cs4271.o +snd-soc-cs4271-i2c-objs := cs4271-i2c.o +snd-soc-cs4271-spi-objs := cs4271-spi.o +snd-soc-cs42xx8-objs := cs42xx8.o +snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o +snd-soc-cs4349-objs := cs4349.o +snd-soc-cs43130-objs := cs43130.o +snd-soc-cs47l24-objs := cs47l24.o +snd-soc-cs53l30-objs := cs53l30.o +snd-soc-cx20442-objs := cx20442.o +snd-soc-da7210-objs := da7210.o +snd-soc-da7213-objs := da7213.o +snd-soc-da7218-objs := da7218.o +snd-soc-da7219-objs := da7219.o da7219-aad.o +snd-soc-da732x-objs := da732x.o +snd-soc-da9055-objs := da9055.o +snd-soc-bt-sco-objs := bt-sco.o +snd-soc-dmic-objs := dmic.o +snd-soc-es8328-objs := es8328.o +snd-soc-es8328-i2c-objs := es8328-i2c.o +snd-soc-es8328-spi-objs := es8328-spi.o +snd-soc-gtm601-objs := gtm601.o +snd-soc-hdac-hdmi-objs := hdac_hdmi.o +snd-soc-ics43432-objs := ics43432.o +snd-soc-inno-rk3036-objs := inno_rk3036.o +snd-soc-isabelle-objs := isabelle.o +snd-soc-jz4740-codec-objs := jz4740.o +snd-soc-l3-objs := l3.o +snd-soc-lm4857-objs := lm4857.o +snd-soc-lm49453-objs := lm49453.o +snd-soc-max9768-objs := max9768.o +snd-soc-max98088-objs := max98088.o +snd-soc-max98090-objs := max98090.o +snd-soc-max98095-objs := max98095.o +snd-soc-max98357a-objs := max98357a.o +snd-soc-max9867-objs := max9867.o +snd-soc-max98925-objs := max98925.o +snd-soc-max98926-objs := max98926.o +snd-soc-max9850-objs := max9850.o +snd-soc-mc13783-objs := mc13783.o +snd-soc-ml26124-objs := ml26124.o +snd-soc-nau8825-objs := nau8825.o +snd-soc-pcm1681-objs := pcm1681.o +snd-soc-pcm179x-codec-objs := pcm179x.o +snd-soc-pcm179x-i2c-objs := pcm179x-i2c.o +snd-soc-pcm179x-spi-objs := pcm179x-spi.o +snd-soc-pcm3008-objs := pcm3008.o +snd-soc-pcm3168a-objs := pcm3168a.o +snd-soc-pcm3168a-i2c-objs := pcm3168a-i2c.o +snd-soc-pcm3168a-spi-objs := pcm3168a-spi.o +snd-soc-pcm512x-objs := pcm512x.o +snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o +snd-soc-pcm512x-spi-objs := pcm512x-spi.o +snd-soc-rl6231-objs := rl6231.o +snd-soc-rl6347a-objs := rl6347a.o +snd-soc-rt286-objs := rt286.o +snd-soc-rt298-objs := rt298.o +snd-soc-rt5514-objs := rt5514.o +snd-soc-rt5616-objs := rt5616.o +snd-soc-rt5631-objs := rt5631.o +snd-soc-rt5640-objs := rt5640.o +snd-soc-rt5645-objs := rt5645.o +snd-soc-rt5651-objs := rt5651.o +snd-soc-rt5659-objs := rt5659.o +snd-soc-rt5670-objs := rt5670.o +snd-soc-rt5677-objs := rt5677.o +snd-soc-rt5677-spi-objs := rt5677-spi.o +snd-soc-sgtl5000-objs := sgtl5000.o +snd-soc-alc5623-objs := alc5623.o +snd-soc-alc5632-objs := alc5632.o +snd-soc-sigmadsp-objs := sigmadsp.o +snd-soc-sigmadsp-i2c-objs := sigmadsp-i2c.o +snd-soc-sigmadsp-regmap-objs := sigmadsp-regmap.o +snd-soc-si476x-objs := si476x.o +snd-soc-sirf-audio-codec-objs := sirf-audio-codec.o +snd-soc-sn95031-objs := sn95031.o +snd-soc-spdif-tx-objs := spdif_transmitter.o +snd-soc-spdif-rx-objs := spdif_receiver.o +snd-soc-ssm2518-objs := ssm2518.o +snd-soc-ssm2602-objs := ssm2602.o +snd-soc-ssm2602-spi-objs := ssm2602-spi.o +snd-soc-ssm2602-i2c-objs := ssm2602-i2c.o +snd-soc-ssm4567-objs := ssm4567.o +snd-soc-sta32x-objs := sta32x.o +snd-soc-sta350-objs := sta350.o +snd-soc-sta529-objs := sta529.o +snd-soc-stac9766-objs := stac9766.o +snd-soc-sti-sas-objs := sti-sas.o +snd-soc-tas5086-objs := tas5086.o +snd-soc-tas571x-objs := tas571x.o +snd-soc-tfa9879-objs := tfa9879.o +snd-soc-tlv320aic23-objs := tlv320aic23.o +snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o +snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o +snd-soc-tlv320aic26-objs := tlv320aic26.o +snd-soc-tlv320aic31xx-objs := tlv320aic31xx.o +snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o +snd-soc-tlv320aic3x-objs := tlv320aic3x.o +snd-soc-tlv320dac33-objs := tlv320dac33.o +snd-soc-ts3a227e-objs := ts3a227e.o +snd-soc-twl4030-objs := twl4030.o +snd-soc-twl6040-objs := twl6040.o +snd-soc-uda134x-objs := uda134x.o +snd-soc-uda1380-objs := uda1380.o +snd-soc-wl1273-objs := wl1273.o +snd-soc-wm-adsp-objs := wm_adsp.o +snd-soc-wm0010-objs := wm0010.o +snd-soc-wm1250-ev1-objs := wm1250-ev1.o +snd-soc-wm2000-objs := wm2000.o +snd-soc-wm2200-objs := wm2200.o +snd-soc-wm5100-objs := wm5100.o wm5100-tables.o +snd-soc-wm5102-objs := wm5102.o +snd-soc-wm5110-objs := wm5110.o +snd-soc-wm8350-objs := wm8350.o +snd-soc-wm8400-objs := wm8400.o +snd-soc-wm8510-objs := wm8510.o +snd-soc-wm8523-objs := wm8523.o +snd-soc-wm8580-objs := wm8580.o +snd-soc-wm8711-objs := wm8711.o +snd-soc-wm8727-objs := wm8727.o +snd-soc-wm8728-objs := wm8728.o +snd-soc-wm8731-objs := wm8731.o +snd-soc-wm8737-objs := wm8737.o +snd-soc-wm8741-objs := wm8741.o +snd-soc-wm8750-objs := wm8750.o +snd-soc-wm8753-objs := wm8753.o +snd-soc-wm8770-objs := wm8770.o +snd-soc-wm8776-objs := wm8776.o +snd-soc-wm8782-objs := wm8782.o +snd-soc-wm8804-objs := wm8804.o +snd-soc-wm8804-i2c-objs := wm8804-i2c.o +snd-soc-wm8804-spi-objs := wm8804-spi.o +snd-soc-wm8900-objs := wm8900.o +snd-soc-wm8903-objs := wm8903.o +snd-soc-wm8904-objs := wm8904.o +snd-soc-wm8996-objs := wm8996.o +snd-soc-wm8940-objs := wm8940.o +snd-soc-wm8955-objs := wm8955.o +snd-soc-wm8960-objs := wm8960.o +snd-soc-wm8961-objs := wm8961.o +snd-soc-wm8962-objs := wm8962.o +snd-soc-wm8971-objs := wm8971.o +snd-soc-wm8974-objs := wm8974.o +snd-soc-wm8978-objs := wm8978.o +snd-soc-wm8983-objs := wm8983.o +snd-soc-wm8985-objs := wm8985.o +snd-soc-wm8988-objs := wm8988.o +snd-soc-wm8990-objs := wm8990.o +snd-soc-wm8991-objs := wm8991.o +snd-soc-wm8993-objs := wm8993.o +snd-soc-wm8994-objs := wm8994.o wm8958-dsp2.o +snd-soc-wm8995-objs := wm8995.o +snd-soc-wm8997-objs := wm8997.o +snd-soc-wm8998-objs := wm8998.o +snd-soc-wm9081-objs := wm9081.o +snd-soc-wm9090-objs := wm9090.o +snd-soc-wm9705-objs := wm9705.o +snd-soc-wm9712-objs := wm9712.o +snd-soc-wm9713-objs := wm9713.o +snd-soc-wm-hubs-objs := wm_hubs.o + +# Amp +snd-soc-max9877-objs := max9877.o +snd-soc-tpa6130a2-objs := tpa6130a2.o +snd-soc-tas2552-objs := tas2552.o + +obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o +obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o +obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o +obj-$(CONFIG_SND_SOC_AD1836) += snd-soc-ad1836.o +obj-$(CONFIG_SND_SOC_AD193X) += snd-soc-ad193x.o +obj-$(CONFIG_SND_SOC_AD193X_SPI) += snd-soc-ad193x-spi.o +obj-$(CONFIG_SND_SOC_AD193X_I2C) += snd-soc-ad193x-i2c.o +obj-$(CONFIG_SND_SOC_AD1980) += snd-soc-ad1980.o +obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o +obj-$(CONFIG_SND_SOC_ADAU1373) += snd-soc-adau1373.o +obj-$(CONFIG_SND_SOC_ADAU1701) += snd-soc-adau1701.o +obj-$(CONFIG_SND_SOC_ADAU17X1) += snd-soc-adau17x1.o +obj-$(CONFIG_SND_SOC_ADAU1761) += snd-soc-adau1761.o +obj-$(CONFIG_SND_SOC_ADAU1761_I2C) += snd-soc-adau1761-i2c.o +obj-$(CONFIG_SND_SOC_ADAU1761_SPI) += snd-soc-adau1761-spi.o +obj-$(CONFIG_SND_SOC_ADAU1781) += snd-soc-adau1781.o +obj-$(CONFIG_SND_SOC_ADAU1781_I2C) += snd-soc-adau1781-i2c.o +obj-$(CONFIG_SND_SOC_ADAU1781_SPI) += snd-soc-adau1781-spi.o +obj-$(CONFIG_SND_SOC_ADAU1977) += snd-soc-adau1977.o +obj-$(CONFIG_SND_SOC_ADAU1977_SPI) += snd-soc-adau1977-spi.o +obj-$(CONFIG_SND_SOC_ADAU1977_I2C) += snd-soc-adau1977-i2c.o +obj-$(CONFIG_SND_SOC_ADAV80X) += snd-soc-adav80x.o +obj-$(CONFIG_SND_SOC_ADAV801) += snd-soc-adav801.o +obj-$(CONFIG_SND_SOC_ADAV803) += snd-soc-adav803.o +obj-$(CONFIG_SND_SOC_ADS117X) += snd-soc-ads117x.o +obj-$(CONFIG_SND_SOC_AK4104) += snd-soc-ak4104.o +obj-$(CONFIG_SND_SOC_AK4535) += snd-soc-ak4535.o +obj-$(CONFIG_SND_SOC_AK4554) += snd-soc-ak4554.o +obj-$(CONFIG_SND_SOC_AK4613) += snd-soc-ak4613.o +obj-$(CONFIG_SND_SOC_AK4641) += snd-soc-ak4641.o +obj-$(CONFIG_SND_SOC_AK4642) += snd-soc-ak4642.o +obj-$(CONFIG_SND_SOC_AK4671) += snd-soc-ak4671.o +obj-$(CONFIG_SND_SOC_AK5386) += snd-soc-ak5386.o +obj-$(CONFIG_SND_SOC_ALC5623) += snd-soc-alc5623.o +obj-$(CONFIG_SND_SOC_ALC5632) += snd-soc-alc5632.o +obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o +obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o +obj-$(CONFIG_SND_SOC_CIRRUS_PSIA) += snd-soc-cirrus-psia.o +obj-$(CONFIG_SND_SOC_CS35L32) += snd-soc-cs35l32.o +obj-$(CONFIG_SND_SOC_CS35L33) += snd-soc-cs35l33.o +obj-$(CONFIG_SND_SOC_CS35L34) += snd-soc-cs35l34.o +obj-$(CONFIG_SND_SOC_CS35L35) += snd-soc-cs35l35.o +obj-$(CONFIG_SND_SOC_CS35L41) += snd-soc-cs35l41.o +obj-$(CONFIG_SND_SOC_CS35L41_SPI) += snd-soc-cs35l41-spi.o +obj-$(CONFIG_SND_SOC_CS35L41_I2C) += snd-soc-cs35l41-i2c.o +obj-$(CONFIG_SND_SOC_CS35L36) += snd-soc-cs35l36.o +obj-$(CONFIG_SND_SOC_CS42L42) += snd-soc-cs42l42.o +obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o +obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o +obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o +obj-$(CONFIG_SND_SOC_CS42L56) += snd-soc-cs42l56.o +obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o +obj-$(CONFIG_SND_SOC_CS4265) += snd-soc-cs4265.o +obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o +obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o +obj-$(CONFIG_SND_SOC_CS4271_I2C) += snd-soc-cs4271-i2c.o +obj-$(CONFIG_SND_SOC_CS4271_SPI) += snd-soc-cs4271-spi.o +obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o +obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o +obj-$(CONFIG_SND_SOC_CS4349) += snd-soc-cs4349.o +obj-$(CONFIG_SND_SOC_CS43130) += snd-soc-cs43130.o +obj-$(CONFIG_SND_SOC_CS47L24) += snd-soc-cs47l24.o +obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o +obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o +obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o +obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o +obj-$(CONFIG_SND_SOC_DA7218) += snd-soc-da7218.o +obj-$(CONFIG_SND_SOC_DA7219) += snd-soc-da7219.o +obj-$(CONFIG_SND_SOC_DA732X) += snd-soc-da732x.o +obj-$(CONFIG_SND_SOC_DA9055) += snd-soc-da9055.o +obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o +obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o +obj-$(CONFIG_SND_SOC_ES8328) += snd-soc-es8328.o +obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o +obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o +obj-$(CONFIG_SND_SOC_GTM601) += snd-soc-gtm601.o +obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o +obj-$(CONFIG_SND_SOC_ICS43432) += snd-soc-ics43432.o +obj-$(CONFIG_SND_SOC_INNO_RK3036) += snd-soc-inno-rk3036.o +obj-$(CONFIG_SND_SOC_ISABELLE) += snd-soc-isabelle.o +obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o +obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o +obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o +obj-$(CONFIG_SND_SOC_LM49453) += snd-soc-lm49453.o +obj-$(CONFIG_SND_SOC_MAX9768) += snd-soc-max9768.o +obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o +obj-$(CONFIG_SND_SOC_MAX98090) += snd-soc-max98090.o +obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o +obj-$(CONFIG_SND_SOC_MAX98357A) += snd-soc-max98357a.o +obj-$(CONFIG_SND_SOC_MAX9867) += snd-soc-max9867.o +obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o +obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o +obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o +obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o +obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o +obj-$(CONFIG_SND_SOC_NAU8825) += snd-soc-nau8825.o +obj-$(CONFIG_SND_SOC_PCM1681) += snd-soc-pcm1681.o +obj-$(CONFIG_SND_SOC_PCM179X) += snd-soc-pcm179x-codec.o +obj-$(CONFIG_SND_SOC_PCM179X_I2C) += snd-soc-pcm179x-i2c.o +obj-$(CONFIG_SND_SOC_PCM179X_SPI) += snd-soc-pcm179x-spi.o +obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o +obj-$(CONFIG_SND_SOC_PCM3168A) += snd-soc-pcm3168a.o +obj-$(CONFIG_SND_SOC_PCM3168A_I2C) += snd-soc-pcm3168a-i2c.o +obj-$(CONFIG_SND_SOC_PCM3168A_SPI) += snd-soc-pcm3168a-spi.o +obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o +obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o +obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o +obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o +obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o +obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o +obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o +obj-$(CONFIG_SND_SOC_RT5514) += snd-soc-rt5514.o +obj-$(CONFIG_SND_SOC_RT5616) += snd-soc-rt5616.o +obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o +obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o +obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o +obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o +obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o +obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o +obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o +obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o +obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o +obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o +obj-$(CONFIG_SND_SOC_SIGMADSP_I2C) += snd-soc-sigmadsp-i2c.o +obj-$(CONFIG_SND_SOC_SIGMADSP_REGMAP) += snd-soc-sigmadsp-regmap.o +obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o +obj-$(CONFIG_SND_SOC_SN95031) +=snd-soc-sn95031.o +obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif-rx.o snd-soc-spdif-tx.o +obj-$(CONFIG_SND_SOC_SSM2518) += snd-soc-ssm2518.o +obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o +obj-$(CONFIG_SND_SOC_SSM2602_SPI) += snd-soc-ssm2602-spi.o +obj-$(CONFIG_SND_SOC_SSM2602_I2C) += snd-soc-ssm2602-i2c.o +obj-$(CONFIG_SND_SOC_SSM4567) += snd-soc-ssm4567.o +obj-$(CONFIG_SND_SOC_STA32X) += snd-soc-sta32x.o +obj-$(CONFIG_SND_SOC_STA350) += snd-soc-sta350.o +obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o +obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o +obj-$(CONFIG_SND_SOC_STI_SAS) += snd-soc-sti-sas.o +obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o +obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o +obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o +obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o +obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o +obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o +obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o +obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o +obj-$(CONFIG_SND_SOC_TLV320AIC31XX) += snd-soc-tlv320aic31xx.o +obj-$(CONFIG_SND_SOC_TLV320AIC32X4) += snd-soc-tlv320aic32x4.o +obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o +obj-$(CONFIG_SND_SOC_TLV320DAC33) += snd-soc-tlv320dac33.o +obj-$(CONFIG_SND_SOC_TS3A227E) += snd-soc-ts3a227e.o +obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o +obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o +obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o +obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o +obj-$(CONFIG_SND_SOC_WM0010) += snd-soc-wm0010.o +obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o +obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o +obj-$(CONFIG_SND_SOC_WM2200) += snd-soc-wm2200.o +obj-$(CONFIG_SND_SOC_WM5100) += snd-soc-wm5100.o +obj-$(CONFIG_SND_SOC_WM5102) += snd-soc-wm5102.o +obj-$(CONFIG_SND_SOC_WM5110) += snd-soc-wm5110.o +obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o +obj-$(CONFIG_SND_SOC_WM8400) += snd-soc-wm8400.o +obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o +obj-$(CONFIG_SND_SOC_WM8523) += snd-soc-wm8523.o +obj-$(CONFIG_SND_SOC_WM8580) += snd-soc-wm8580.o +obj-$(CONFIG_SND_SOC_WM8711) += snd-soc-wm8711.o +obj-$(CONFIG_SND_SOC_WM8727) += snd-soc-wm8727.o +obj-$(CONFIG_SND_SOC_WM8728) += snd-soc-wm8728.o +obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o +obj-$(CONFIG_SND_SOC_WM8737) += snd-soc-wm8737.o +obj-$(CONFIG_SND_SOC_WM8741) += snd-soc-wm8741.o +obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o +obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o +obj-$(CONFIG_SND_SOC_WM8770) += snd-soc-wm8770.o +obj-$(CONFIG_SND_SOC_WM8776) += snd-soc-wm8776.o +obj-$(CONFIG_SND_SOC_WM8782) += snd-soc-wm8782.o +obj-$(CONFIG_SND_SOC_WM8804) += snd-soc-wm8804.o +obj-$(CONFIG_SND_SOC_WM8804_I2C) += snd-soc-wm8804-i2c.o +obj-$(CONFIG_SND_SOC_WM8804_SPI) += snd-soc-wm8804-spi.o +obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o +obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o +obj-$(CONFIG_SND_SOC_WM8904) += snd-soc-wm8904.o +obj-$(CONFIG_SND_SOC_WM8996) += snd-soc-wm8996.o +obj-$(CONFIG_SND_SOC_WM8940) += snd-soc-wm8940.o +obj-$(CONFIG_SND_SOC_WM8955) += snd-soc-wm8955.o +obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o +obj-$(CONFIG_SND_SOC_WM8961) += snd-soc-wm8961.o +obj-$(CONFIG_SND_SOC_WM8962) += snd-soc-wm8962.o +obj-$(CONFIG_SND_SOC_WM8971) += snd-soc-wm8971.o +obj-$(CONFIG_SND_SOC_WM8974) += snd-soc-wm8974.o +obj-$(CONFIG_SND_SOC_WM8978) += snd-soc-wm8978.o +obj-$(CONFIG_SND_SOC_WM8983) += snd-soc-wm8983.o +obj-$(CONFIG_SND_SOC_WM8985) += snd-soc-wm8985.o +obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o +obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o +obj-$(CONFIG_SND_SOC_WM8991) += snd-soc-wm8991.o +obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o +obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o +obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o +obj-$(CONFIG_SND_SOC_WM8997) += snd-soc-wm8997.o +obj-$(CONFIG_SND_SOC_WM8998) += snd-soc-wm8998.o +obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o +obj-$(CONFIG_SND_SOC_WM9090) += snd-soc-wm9090.o +obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o +obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o +obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o +obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o +obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o + +# Amp +obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o +obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o diff --git a/techpack/audio/asoc/codecs/cs35l41/cs35l41-i2c.c b/techpack/audio/asoc/codecs/cs35l41/cs35l41-i2c.c new file mode 100644 index 000000000000..f9cb15f43f31 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/cs35l41-i2c.c @@ -0,0 +1,123 @@ +/* + * cs35l41-i2c.c -- CS35l41 I2C driver + * + * Copyright 2017 Cirrus Logic, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l41.h" +#include + +static struct regmap_config cs35l41_regmap_i2c = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + .max_register = CS35L41_LASTREG, + .reg_defaults = cs35l41_reg, + .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), + .volatile_reg = cs35l41_volatile_reg, + .readable_reg = cs35l41_readable_reg, + .precious_reg = cs35l41_precious_reg, + .cache_type = REGCACHE_RBTREE, +}; + +static const struct i2c_device_id cs35l41_id_i2c[] = { + { "cs35l40", 0 }, + { "cs35l41", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, cs35l41_id_i2c); + +static int cs35l41_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct cs35l41_private *cs35l41; + struct device *dev = &client->dev; + struct cs35l41_platform_data *pdata = dev_get_platdata(dev); + const struct regmap_config *regmap_config = &cs35l41_regmap_i2c; + int ret; + + dev_info(dev, "cs35l41 i2c probe start\n"); + + cs35l41 = devm_kzalloc(dev, sizeof(struct cs35l41_private), GFP_KERNEL); + + if (cs35l41 == NULL) + return -ENOMEM; + + cs35l41->dev = dev; + cs35l41->irq = client->irq; + cs35l41->bus_spi = false; + + i2c_set_clientdata(client, cs35l41); + cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config); + if (IS_ERR(cs35l41->regmap)) { + ret = PTR_ERR(cs35l41->regmap); + dev_err(cs35l41->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + return cs35l41_probe(cs35l41, pdata); +} + +static int cs35l41_i2c_remove(struct i2c_client *client) +{ + struct cs35l41_private *cs35l41 = i2c_get_clientdata(client); + + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); + wm_adsp2_remove(&cs35l41->dsp); + regulator_bulk_disable(cs35l41->num_supplies, cs35l41->supplies); + snd_soc_unregister_codec(cs35l41->dev); + return 0; +} + +static const struct of_device_id cs35l41_of_match[] = { + { .compatible = "cirrus,cs35l40" }, + { .compatible = "cirrus,cs35l41" }, + {}, +}; +MODULE_DEVICE_TABLE(of, cs35l41_of_match); + +static struct i2c_driver cs35l41_i2c_driver = { + .driver = { + .name = "cs35l41", + .of_match_table = cs35l41_of_match, + }, + .id_table = cs35l41_id_i2c, + .probe = cs35l41_i2c_probe, + .remove = cs35l41_i2c_remove, +}; + +module_i2c_driver(cs35l41_i2c_driver); + +MODULE_DESCRIPTION("I2C CS35L41 driver"); +MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l41/cs35l41-spi.c b/techpack/audio/asoc/codecs/cs35l41/cs35l41-spi.c new file mode 100644 index 000000000000..07af1c7fc7e3 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/cs35l41-spi.c @@ -0,0 +1,113 @@ +/* + * cs35l41-spi.c -- CS35l41 SPI driver + * + * Copyright 2017 Cirrus Logic, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l41.h" +#include + +static struct regmap_config cs35l41_regmap_spi = { + .reg_bits = 32, + .val_bits = 32, + .pad_bits = 16, + .reg_stride = 4, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + .max_register = CS35L41_LASTREG, + .reg_defaults = cs35l41_reg, + .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), + .volatile_reg = cs35l41_volatile_reg, + .readable_reg = cs35l41_readable_reg, + .cache_type = REGCACHE_RBTREE, +}; + +static const struct spi_device_id cs35l41_id_spi[] = { + { "cs35l40", 0 }, + { "cs35l41", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(spi, cs35l41_id_spi); + +static int cs35l41_spi_probe(struct spi_device *spi) +{ + const struct regmap_config *regmap_config = &cs35l41_regmap_spi; + struct cs35l41_platform_data *pdata = dev_get_platdata(&spi->dev); + struct cs35l41_private *cs35l41; + int ret; + + cs35l41 = devm_kzalloc(&spi->dev, sizeof(struct cs35l41_private), + GFP_KERNEL); + if (cs35l41 == NULL) + return -ENOMEM; + + spi_set_drvdata(spi, cs35l41); + cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config); + if (IS_ERR(cs35l41->regmap)) { + ret = PTR_ERR(cs35l41->regmap); + dev_err(&spi->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + cs35l41->dev = &spi->dev; + cs35l41->irq = spi->irq; + + return cs35l41_probe(cs35l41, pdata); +} + +static int cs35l41_spi_remove(struct spi_device *spi) +{ + struct cs35l41_private *cs35l41 = spi_get_drvdata(spi); + + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); + wm_adsp2_remove(&cs35l41->dsp); + regulator_bulk_disable(cs35l41->num_supplies, cs35l41->supplies); + snd_soc_unregister_codec(cs35l41->dev); + return 0; +} + +static const struct of_device_id cs35l41_of_match[] = { + { .compatible = "cirrus,cs35l40" }, + { .compatible = "cirrus,cs35l41" }, + {}, +}; +MODULE_DEVICE_TABLE(of, cs35l41_of_match); + +static struct spi_driver cs35l41_spi_driver = { + .driver = { + .name = "cs35l41", + .of_match_table = cs35l41_of_match, + }, + .id_table = cs35l41_id_spi, + .probe = cs35l41_spi_probe, + .remove = cs35l41_spi_remove, +}; + +module_spi_driver(cs35l41_spi_driver); + +MODULE_DESCRIPTION("SPI CS35L41 driver"); +MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l41/cs35l41-tables.c b/techpack/audio/asoc/codecs/cs35l41/cs35l41-tables.c new file mode 100644 index 000000000000..04c9cfd7b38a --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/cs35l41-tables.c @@ -0,0 +1,946 @@ +/* + * cs35l41-tables.c -- CS35L41 ALSA SoC audio driver + * + * Copyright 2018 Cirrus Logic, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: Brian Austin + * David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "cs35l41.h" + +const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = { + { CS35L41_TEST_KEY_CTL, 0x00000000 }, + { CS35L41_USER_KEY_CTL, 0x00000000 }, + { CS35L41_OTP_CTRL0, 0x00006418 }, + { CS35L41_OTP_CTRL1, 0x00000000 }, + { CS35L41_OTP_CTRL3, 0x00000000 }, + { CS35L41_OTP_CTRL4, 0x00000000 }, + { CS35L41_OTP_CTRL5, 0x00000030 }, + { CS35L41_OTP_CTRL6, 0x00000000 }, + { CS35L41_OTP_CTRL7, 0x00000000 }, + { CS35L41_OTP_CTRL8, 0x00000000 }, + { CS35L41_PWR_CTRL1, 0x00000000 }, + { CS35L41_PWR_CTRL3, 0x01000010 }, + { CS35L41_CTRL_OVRRIDE, 0x00000002 }, + { CS35L41_AMP_OUT_MUTE, 0x00000000 }, + { CS35L41_PROTECT_REL_ERR_IGN, 0x00000000 }, + { CS35L41_GPIO_PAD_CONTROL, 0x00000000 }, + { CS35L41_JTAG_CONTROL, 0x00000000 }, + { CS35L41_PLL_CLK_CTRL, 0x00000010 }, + { CS35L41_DSP_CLK_CTRL, 0x00000003 }, + { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, + { CS35L41_DATA_FS_SEL, 0x00000000 }, + { CS35L41_MDSYNC_EN, 0x00000200 }, + { CS35L41_MDSYNC_TX_ID, 0x00000000 }, + { CS35L41_MDSYNC_PWR_CTRL, 0x00000002 }, + { CS35L41_MDSYNC_DATA_TX, 0x00000000 }, + { CS35L41_MDSYNC_TX_STATUS, 0x00000002 }, + { CS35L41_MDSYNC_DATA_RX, 0x00000000 }, + { CS35L41_MDSYNC_RX_STATUS, 0x00000002 }, + { CS35L41_MDSYNC_ERR_STATUS, 0x00000000 }, + { CS35L41_MDSYNC_SYNC_PTE2, 0x00000000 }, + { CS35L41_MDSYNC_SYNC_PTE3, 0x00000000 }, + { CS35L41_MDSYNC_SYNC_MSM_STATUS, 0x00000000 }, + { CS35L41_BSTCVRT_VCTRL1, 0x00000000 }, + { CS35L41_BSTCVRT_VCTRL2, 0x00000001 }, + { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A }, + { CS35L41_BSTCVRT_SFT_RAMP, 0x00000003 }, + { CS35L41_BSTCVRT_COEFF, 0x00002424 }, + { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 }, + { CS35L41_BSTCVRT_SW_FREQ, 0x01008000 }, + { CS35L41_BSTCVRT_DCM_CTRL, 0x00002001 }, + { CS35L41_BSTCVRT_DCM_MODE_FORCE, 0x00000000 }, + { CS35L41_BSTCVRT_OVERVOLT_CTRL, 0x00000130 }, + { CS35L41_VI_VOL_POL, 0x08000800 }, + { CS35L41_DTEMP_WARN_THLD, 0x00000002 }, + { CS35L41_DTEMP_EN, 0x00000000 }, + { CS35L41_VPVBST_FS_SEL, 0x00000001 }, + { CS35L41_SP_ENABLES, 0x00000000 }, + { CS35L41_SP_RATE_CTRL, 0x00000028 }, + { CS35L41_SP_FORMAT, 0x10100200 }, + { CS35L41_SP_HIZ_CTRL, 0x00000002 }, + { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 }, + { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 }, + { CS35L41_SP_TX_WL, 0x00000010 }, + { CS35L41_SP_RX_WL, 0x00000018 }, + { CS35L41_DAC_PCM1_SRC, 0x00000008 }, + { CS35L41_ASP_TX1_SRC, 0x00000018 }, + { CS35L41_ASP_TX2_SRC, 0x00000019 }, + { CS35L41_ASP_TX3_SRC, 0x00000020 }, + { CS35L41_ASP_TX4_SRC, 0x00000021 }, + { CS35L41_DSP1_RX1_SRC, 0x00000008 }, + { CS35L41_DSP1_RX2_SRC, 0x00000009 }, + { CS35L41_DSP1_RX3_SRC, 0x00000018 }, + { CS35L41_DSP1_RX4_SRC, 0x00000019 }, + { CS35L41_DSP1_RX5_SRC, 0x00000020 }, + { CS35L41_DSP1_RX6_SRC, 0x00000021 }, + { CS35L41_DSP1_RX7_SRC, 0x0000003A }, + { CS35L41_DSP1_RX8_SRC, 0x00000001 }, + { CS35L41_NGATE1_SRC, 0x00000008 }, + { CS35L41_NGATE2_SRC, 0x00000009 }, + { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 }, + { CS35L41_VPBR_CFG, 0x02AA1905 }, + { CS35L41_VBBR_CFG, 0x02AA1905 }, + { CS35L41_VPBR_STATUS, 0x00000000 }, + { CS35L41_VBBR_STATUS, 0x00000000 }, + { CS35L41_OVERTEMP_CFG, 0x00000001 }, + { CS35L41_AMP_ERR_VOL, 0x00000000 }, + { CS35L41_VOL_STATUS_TO_DSP, 0x00000000 }, + { CS35L41_CLASSH_CFG, 0x000B0405 }, + { CS35L41_WKFET_CFG, 0x00000111 }, + { CS35L41_NG_CFG, 0x00000033 }, + { CS35L41_AMP_GAIN_CTRL, 0x00000273 }, + { CS35L41_DAC_MSM_CFG, 0x00580000 }, + { CS35L41_GPIO1_CTRL1, 0xE1000001 }, + { CS35L41_GPIO2_CTRL1, 0xE1000001 }, + { CS35L41_MIXER_NGATE_CFG, 0x00000000 }, + { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 }, + { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 }, + { CS35L41_CLOCK_DETECT_1, 0x00000000 }, + { CS35L41_TIMER1_CONTROL, 0x00000000 }, + { CS35L41_TIMER1_COUNT_PRESET, 0x00000000 }, + { CS35L41_TIMER1_START_STOP, 0x00000000 }, + { CS35L41_TIMER1_STATUS, 0x00000000 }, + { CS35L41_TIMER1_COUNT_READBACK, 0x00000000 }, + { CS35L41_TIMER1_DSP_CLK_CFG, 0x00000000 }, + { CS35L41_TIMER1_DSP_CLK_STATUS, 0x00000000 }, + { CS35L41_TIMER2_CONTROL, 0x00000000 }, + { CS35L41_TIMER2_COUNT_PRESET, 0x00000000 }, + { CS35L41_TIMER2_START_STOP, 0x00000000 }, + { CS35L41_TIMER2_STATUS, 0x00000000 }, + { CS35L41_TIMER2_COUNT_READBACK, 0x00000000 }, + { CS35L41_TIMER2_DSP_CLK_CFG, 0x00000000 }, + { CS35L41_TIMER2_DSP_CLK_STATUS, 0x00000000 }, + { CS35L41_DFT_JTAG_CONTROL, 0x00000000 }, + { CS35L41_DIE_STS1, 0x00000000 }, + { CS35L41_DIE_STS2, 0x00000000 }, + { CS35L41_TEMP_CAL1, 0x00000000 }, + { CS35L41_TEMP_CAL2, 0x00000000 }, +}; + +bool cs35l41_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L41_DEVID: + case CS35L41_REVID: + case CS35L41_FABID: + case CS35L41_RELID: + case CS35L41_OTPID: + case CS35L41_TEST_KEY_CTL: + case CS35L41_USER_KEY_CTL: + case CS35L41_OTP_CTRL0: + case CS35L41_OTP_CTRL3: + case CS35L41_OTP_CTRL4: + case CS35L41_OTP_CTRL5: + case CS35L41_OTP_CTRL6: + case CS35L41_OTP_CTRL7: + case CS35L41_OTP_CTRL8: + case CS35L41_PWR_CTRL1: + case CS35L41_PWR_CTRL2: + case CS35L41_PWR_CTRL3: + case CS35L41_CTRL_OVRRIDE: + case CS35L41_AMP_OUT_MUTE: + case CS35L41_PROTECT_REL_ERR_IGN: + case CS35L41_GPIO_PAD_CONTROL: + case CS35L41_JTAG_CONTROL: + case CS35L41_PLL_CLK_CTRL: + case CS35L41_DSP_CLK_CTRL: + case CS35L41_GLOBAL_CLK_CTRL: + case CS35L41_DATA_FS_SEL: + case CS35L41_MDSYNC_EN: + case CS35L41_MDSYNC_TX_ID: + case CS35L41_MDSYNC_PWR_CTRL: + case CS35L41_MDSYNC_DATA_TX: + case CS35L41_MDSYNC_TX_STATUS: + case CS35L41_MDSYNC_DATA_RX: + case CS35L41_MDSYNC_RX_STATUS: + case CS35L41_MDSYNC_ERR_STATUS: + case CS35L41_MDSYNC_SYNC_PTE2: + case CS35L41_MDSYNC_SYNC_PTE3: + case CS35L41_MDSYNC_SYNC_MSM_STATUS: + case CS35L41_BSTCVRT_VCTRL1: + case CS35L41_BSTCVRT_VCTRL2: + case CS35L41_BSTCVRT_PEAK_CUR: + case CS35L41_BSTCVRT_SFT_RAMP: + case CS35L41_BSTCVRT_COEFF: + case CS35L41_BSTCVRT_SLOPE_LBST: + case CS35L41_BSTCVRT_SW_FREQ: + case CS35L41_BSTCVRT_DCM_CTRL: + case CS35L41_BSTCVRT_DCM_MODE_FORCE: + case CS35L41_BSTCVRT_OVERVOLT_CTRL: + case CS35L41_VI_VOL_POL: + case CS35L41_DTEMP_WARN_THLD: + case CS35L41_DTEMP_CFG: + case CS35L41_DTEMP_EN: + case CS35L41_VPVBST_FS_SEL: + case CS35L41_SP_ENABLES: + case CS35L41_SP_RATE_CTRL: + case CS35L41_SP_FORMAT: + case CS35L41_SP_HIZ_CTRL: + case CS35L41_SP_FRAME_TX_SLOT: + case CS35L41_SP_FRAME_RX_SLOT: + case CS35L41_SP_TX_WL: + case CS35L41_SP_RX_WL: + case CS35L41_DAC_PCM1_SRC: + case CS35L41_ASP_TX1_SRC: + case CS35L41_ASP_TX2_SRC: + case CS35L41_ASP_TX3_SRC: + case CS35L41_ASP_TX4_SRC: + case CS35L41_DSP1_RX1_SRC: + case CS35L41_DSP1_RX2_SRC: + case CS35L41_DSP1_RX3_SRC: + case CS35L41_DSP1_RX4_SRC: + case CS35L41_DSP1_RX5_SRC: + case CS35L41_DSP1_RX6_SRC: + case CS35L41_DSP1_RX7_SRC: + case CS35L41_DSP1_RX8_SRC: + case CS35L41_NGATE1_SRC: + case CS35L41_NGATE2_SRC: + case CS35L41_AMP_DIG_VOL_CTRL: + case CS35L41_VPBR_CFG: + case CS35L41_VBBR_CFG: + case CS35L41_VPBR_STATUS: + case CS35L41_VBBR_STATUS: + case CS35L41_OVERTEMP_CFG: + case CS35L41_AMP_ERR_VOL: + case CS35L41_VOL_STATUS_TO_DSP: + case CS35L41_CLASSH_CFG: + case CS35L41_WKFET_CFG: + case CS35L41_NG_CFG: + case CS35L41_AMP_GAIN_CTRL: + case CS35L41_DAC_MSM_CFG: + case CS35L41_IRQ1_CFG: + case CS35L41_IRQ1_STATUS: + case CS35L41_IRQ1_STATUS1: + case CS35L41_IRQ1_STATUS2: + case CS35L41_IRQ1_STATUS3: + case CS35L41_IRQ1_STATUS4: + case CS35L41_IRQ1_RAW_STATUS1: + case CS35L41_IRQ1_RAW_STATUS2: + case CS35L41_IRQ1_RAW_STATUS3: + case CS35L41_IRQ1_RAW_STATUS4: + case CS35L41_IRQ1_MASK1: + case CS35L41_IRQ1_MASK2: + case CS35L41_IRQ1_MASK3: + case CS35L41_IRQ1_MASK4: + case CS35L41_IRQ1_FRC1: + case CS35L41_IRQ1_FRC2: + case CS35L41_IRQ1_FRC3: + case CS35L41_IRQ1_FRC4: + case CS35L41_IRQ1_EDGE1: + case CS35L41_IRQ1_EDGE4: + case CS35L41_IRQ1_POL1: + case CS35L41_IRQ1_POL2: + case CS35L41_IRQ1_POL3: + case CS35L41_IRQ1_POL4: + case CS35L41_IRQ1_DB3: + case CS35L41_IRQ2_CFG: + case CS35L41_IRQ2_STATUS: + case CS35L41_IRQ2_STATUS1: + case CS35L41_IRQ2_STATUS2: + case CS35L41_IRQ2_STATUS3: + case CS35L41_IRQ2_STATUS4: + case CS35L41_IRQ2_RAW_STATUS1: + case CS35L41_IRQ2_RAW_STATUS2: + case CS35L41_IRQ2_RAW_STATUS3: + case CS35L41_IRQ2_RAW_STATUS4: + case CS35L41_IRQ2_MASK1: + case CS35L41_IRQ2_MASK2: + case CS35L41_IRQ2_MASK3: + case CS35L41_IRQ2_MASK4: + case CS35L41_IRQ2_FRC1: + case CS35L41_IRQ2_FRC2: + case CS35L41_IRQ2_FRC3: + case CS35L41_IRQ2_FRC4: + case CS35L41_IRQ2_EDGE1: + case CS35L41_IRQ2_EDGE4: + case CS35L41_IRQ2_POL1: + case CS35L41_IRQ2_POL2: + case CS35L41_IRQ2_POL3: + case CS35L41_IRQ2_POL4: + case CS35L41_IRQ2_DB3: + case CS35L41_GPIO_STATUS1: + case CS35L41_GPIO1_CTRL1: + case CS35L41_GPIO2_CTRL1: + case CS35L41_MIXER_NGATE_CFG: + case CS35L41_MIXER_NGATE_CH1_CFG: + case CS35L41_MIXER_NGATE_CH2_CFG: + case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: + case CS35L41_CLOCK_DETECT_1: + case CS35L41_TIMER1_CONTROL: + case CS35L41_TIMER1_COUNT_PRESET: + case CS35L41_TIMER1_STATUS: + case CS35L41_TIMER1_COUNT_READBACK: + case CS35L41_TIMER1_DSP_CLK_CFG: + case CS35L41_TIMER1_DSP_CLK_STATUS: + case CS35L41_TIMER2_CONTROL: + case CS35L41_TIMER2_COUNT_PRESET: + case CS35L41_TIMER2_STATUS: + case CS35L41_TIMER2_COUNT_READBACK: + case CS35L41_TIMER2_DSP_CLK_CFG: + case CS35L41_TIMER2_DSP_CLK_STATUS: + case CS35L41_DFT_JTAG_CONTROL: + case CS35L41_DIE_STS1: + case CS35L41_DIE_STS2: + case CS35L41_TEMP_CAL1: + case CS35L41_TEMP_CAL2: + case CS35L41_DSP1_TIMESTAMP_COUNT: + case CS35L41_DSP1_SYS_ID: + case CS35L41_DSP1_SYS_VERSION: + case CS35L41_DSP1_SYS_CORE_ID: + case CS35L41_DSP1_SYS_AHB_ADDR: + case CS35L41_DSP1_SYS_XSRAM_SIZE: + case CS35L41_DSP1_SYS_YSRAM_SIZE: + case CS35L41_DSP1_SYS_PSRAM_SIZE: + case CS35L41_DSP1_SYS_PM_BOOT_SIZE: + case CS35L41_DSP1_SYS_FEATURES: + case CS35L41_DSP1_SYS_FIR_FILTERS: + case CS35L41_DSP1_SYS_LMS_FILTERS: + case CS35L41_DSP1_SYS_XM_BANK_SIZE: + case CS35L41_DSP1_SYS_YM_BANK_SIZE: + case CS35L41_DSP1_SYS_PM_BANK_SIZE: + case CS35L41_DSP1_AHBM_WIN0_CTRL0: + case CS35L41_DSP1_AHBM_WIN0_CTRL1: + case CS35L41_DSP1_AHBM_WIN1_CTRL0: + case CS35L41_DSP1_AHBM_WIN1_CTRL1: + case CS35L41_DSP1_AHBM_WIN2_CTRL0: + case CS35L41_DSP1_AHBM_WIN2_CTRL1: + case CS35L41_DSP1_AHBM_WIN3_CTRL0: + case CS35L41_DSP1_AHBM_WIN3_CTRL1: + case CS35L41_DSP1_AHBM_WIN4_CTRL0: + case CS35L41_DSP1_AHBM_WIN4_CTRL1: + case CS35L41_DSP1_AHBM_WIN5_CTRL0: + case CS35L41_DSP1_AHBM_WIN5_CTRL1: + case CS35L41_DSP1_AHBM_WIN6_CTRL0: + case CS35L41_DSP1_AHBM_WIN6_CTRL1: + case CS35L41_DSP1_AHBM_WIN7_CTRL0: + case CS35L41_DSP1_AHBM_WIN7_CTRL1: + case CS35L41_DSP1_AHBM_WIN_DBG_CTRL0: + case CS35L41_DSP1_AHBM_WIN_DBG_CTRL1: + case CS35L41_DSP1_DEBUG: + case CS35L41_DSP1_TIMER_CTRL: + case CS35L41_DSP1_RX1_RATE: + case CS35L41_DSP1_RX2_RATE: + case CS35L41_DSP1_RX3_RATE: + case CS35L41_DSP1_RX4_RATE: + case CS35L41_DSP1_RX5_RATE: + case CS35L41_DSP1_RX6_RATE: + case CS35L41_DSP1_RX7_RATE: + case CS35L41_DSP1_RX8_RATE: + case CS35L41_DSP1_TX1_RATE: + case CS35L41_DSP1_TX2_RATE: + case CS35L41_DSP1_TX3_RATE: + case CS35L41_DSP1_TX4_RATE: + case CS35L41_DSP1_TX5_RATE: + case CS35L41_DSP1_TX6_RATE: + case CS35L41_DSP1_TX7_RATE: + case CS35L41_DSP1_TX8_RATE: + case CS35L41_DSP1_NMI_CTRL1: + case CS35L41_DSP1_NMI_CTRL2: + case CS35L41_DSP1_NMI_CTRL3: + case CS35L41_DSP1_NMI_CTRL4: + case CS35L41_DSP1_NMI_CTRL5: + case CS35L41_DSP1_NMI_CTRL6: + case CS35L41_DSP1_NMI_CTRL7: + case CS35L41_DSP1_NMI_CTRL8: + case CS35L41_DSP1_RESUME_CTRL: + case CS35L41_DSP1_IRQ1_CTRL: + case CS35L41_DSP1_IRQ2_CTRL: + case CS35L41_DSP1_IRQ3_CTRL: + case CS35L41_DSP1_IRQ4_CTRL: + case CS35L41_DSP1_IRQ5_CTRL: + case CS35L41_DSP1_IRQ6_CTRL: + case CS35L41_DSP1_IRQ7_CTRL: + case CS35L41_DSP1_IRQ8_CTRL: + case CS35L41_DSP1_IRQ9_CTRL: + case CS35L41_DSP1_IRQ10_CTRL: + case CS35L41_DSP1_IRQ11_CTRL: + case CS35L41_DSP1_IRQ12_CTRL: + case CS35L41_DSP1_IRQ13_CTRL: + case CS35L41_DSP1_IRQ14_CTRL: + case CS35L41_DSP1_IRQ15_CTRL: + case CS35L41_DSP1_IRQ16_CTRL: + case CS35L41_DSP1_IRQ17_CTRL: + case CS35L41_DSP1_IRQ18_CTRL: + case CS35L41_DSP1_IRQ19_CTRL: + case CS35L41_DSP1_IRQ20_CTRL: + case CS35L41_DSP1_IRQ21_CTRL: + case CS35L41_DSP1_IRQ22_CTRL: + case CS35L41_DSP1_IRQ23_CTRL: + case CS35L41_DSP1_SCRATCH1: + case CS35L41_DSP1_SCRATCH2: + case CS35L41_DSP1_SCRATCH3: + case CS35L41_DSP1_SCRATCH4: + case CS35L41_DSP1_CCM_CORE_CTRL: + case CS35L41_DSP1_CCM_CLK_OVERRIDE: + case CS35L41_DSP1_XM_MSTR_EN: + case CS35L41_DSP1_XM_CORE_PRI: + case CS35L41_DSP1_XM_AHB_PACK_PL_PRI: + case CS35L41_DSP1_XM_AHB_UP_PL_PRI: + case CS35L41_DSP1_XM_ACCEL_PL0_PRI: + case CS35L41_DSP1_XM_NPL0_PRI: + case CS35L41_DSP1_YM_MSTR_EN: + case CS35L41_DSP1_YM_CORE_PRI: + case CS35L41_DSP1_YM_AHB_PACK_PL_PRI: + case CS35L41_DSP1_YM_AHB_UP_PL_PRI: + case CS35L41_DSP1_YM_ACCEL_PL0_PRI: + case CS35L41_DSP1_YM_NPL0_PRI: + case CS35L41_DSP1_PM_MSTR_EN: + case CS35L41_DSP1_PM_PATCH0_ADDR: + case CS35L41_DSP1_PM_PATCH0_EN: + case CS35L41_DSP1_PM_PATCH0_DATA_LO: + case CS35L41_DSP1_PM_PATCH0_DATA_HI: + case CS35L41_DSP1_PM_PATCH1_ADDR: + case CS35L41_DSP1_PM_PATCH1_EN: + case CS35L41_DSP1_PM_PATCH1_DATA_LO: + case CS35L41_DSP1_PM_PATCH1_DATA_HI: + case CS35L41_DSP1_PM_PATCH2_ADDR: + case CS35L41_DSP1_PM_PATCH2_EN: + case CS35L41_DSP1_PM_PATCH2_DATA_LO: + case CS35L41_DSP1_PM_PATCH2_DATA_HI: + case CS35L41_DSP1_PM_PATCH3_ADDR: + case CS35L41_DSP1_PM_PATCH3_EN: + case CS35L41_DSP1_PM_PATCH3_DATA_LO: + case CS35L41_DSP1_PM_PATCH3_DATA_HI: + case CS35L41_DSP1_PM_PATCH4_ADDR: + case CS35L41_DSP1_PM_PATCH4_EN: + case CS35L41_DSP1_PM_PATCH4_DATA_LO: + case CS35L41_DSP1_PM_PATCH4_DATA_HI: + case CS35L41_DSP1_PM_PATCH5_ADDR: + case CS35L41_DSP1_PM_PATCH5_EN: + case CS35L41_DSP1_PM_PATCH5_DATA_LO: + case CS35L41_DSP1_PM_PATCH5_DATA_HI: + case CS35L41_DSP1_PM_PATCH6_ADDR: + case CS35L41_DSP1_PM_PATCH6_EN: + case CS35L41_DSP1_PM_PATCH6_DATA_LO: + case CS35L41_DSP1_PM_PATCH6_DATA_HI: + case CS35L41_DSP1_PM_PATCH7_ADDR: + case CS35L41_DSP1_PM_PATCH7_EN: + case CS35L41_DSP1_PM_PATCH7_DATA_LO: + case CS35L41_DSP1_PM_PATCH7_DATA_HI: + case CS35L41_DSP1_MPU_XM_ACCESS0: + case CS35L41_DSP1_MPU_YM_ACCESS0: + case CS35L41_DSP1_MPU_WNDW_ACCESS0: + case CS35L41_DSP1_MPU_XREG_ACCESS0: + case CS35L41_DSP1_MPU_YREG_ACCESS0: + case CS35L41_DSP1_MPU_XM_ACCESS1: + case CS35L41_DSP1_MPU_YM_ACCESS1: + case CS35L41_DSP1_MPU_WNDW_ACCESS1: + case CS35L41_DSP1_MPU_XREG_ACCESS1: + case CS35L41_DSP1_MPU_YREG_ACCESS1: + case CS35L41_DSP1_MPU_XM_ACCESS2: + case CS35L41_DSP1_MPU_YM_ACCESS2: + case CS35L41_DSP1_MPU_WNDW_ACCESS2: + case CS35L41_DSP1_MPU_XREG_ACCESS2: + case CS35L41_DSP1_MPU_YREG_ACCESS2: + case CS35L41_DSP1_MPU_XM_ACCESS3: + case CS35L41_DSP1_MPU_YM_ACCESS3: + case CS35L41_DSP1_MPU_WNDW_ACCESS3: + case CS35L41_DSP1_MPU_XREG_ACCESS3: + case CS35L41_DSP1_MPU_YREG_ACCESS3: + case CS35L41_DSP1_MPU_XM_VIO_ADDR: + case CS35L41_DSP1_MPU_XM_VIO_STATUS: + case CS35L41_DSP1_MPU_YM_VIO_ADDR: + case CS35L41_DSP1_MPU_YM_VIO_STATUS: + case CS35L41_DSP1_MPU_PM_VIO_ADDR: + case CS35L41_DSP1_MPU_PM_VIO_STATUS: + case CS35L41_DSP1_MPU_LOCK_CONFIG: + case CS35L41_DSP1_MPU_WDT_RST_CTRL: + case CS35L41_DSP1_STRMARB_MSTR0_CFG0: + case CS35L41_DSP1_STRMARB_MSTR0_CFG1: + case CS35L41_DSP1_STRMARB_MSTR0_CFG2: + case CS35L41_DSP1_STRMARB_MSTR1_CFG0: + case CS35L41_DSP1_STRMARB_MSTR1_CFG1: + case CS35L41_DSP1_STRMARB_MSTR1_CFG2: + case CS35L41_DSP1_STRMARB_MSTR2_CFG0: + case CS35L41_DSP1_STRMARB_MSTR2_CFG1: + case CS35L41_DSP1_STRMARB_MSTR2_CFG2: + case CS35L41_DSP1_STRMARB_MSTR3_CFG0: + case CS35L41_DSP1_STRMARB_MSTR3_CFG1: + case CS35L41_DSP1_STRMARB_MSTR3_CFG2: + case CS35L41_DSP1_STRMARB_MSTR4_CFG0: + case CS35L41_DSP1_STRMARB_MSTR4_CFG1: + case CS35L41_DSP1_STRMARB_MSTR4_CFG2: + case CS35L41_DSP1_STRMARB_MSTR5_CFG0: + case CS35L41_DSP1_STRMARB_MSTR5_CFG1: + case CS35L41_DSP1_STRMARB_MSTR5_CFG2: + case CS35L41_DSP1_STRMARB_MSTR6_CFG0: + case CS35L41_DSP1_STRMARB_MSTR6_CFG1: + case CS35L41_DSP1_STRMARB_MSTR6_CFG2: + case CS35L41_DSP1_STRMARB_MSTR7_CFG0: + case CS35L41_DSP1_STRMARB_MSTR7_CFG1: + case CS35L41_DSP1_STRMARB_MSTR7_CFG2: + case CS35L41_DSP1_STRMARB_TX0_CFG0: + case CS35L41_DSP1_STRMARB_TX0_CFG1: + case CS35L41_DSP1_STRMARB_TX1_CFG0: + case CS35L41_DSP1_STRMARB_TX1_CFG1: + case CS35L41_DSP1_STRMARB_TX2_CFG0: + case CS35L41_DSP1_STRMARB_TX2_CFG1: + case CS35L41_DSP1_STRMARB_TX3_CFG0: + case CS35L41_DSP1_STRMARB_TX3_CFG1: + case CS35L41_DSP1_STRMARB_TX4_CFG0: + case CS35L41_DSP1_STRMARB_TX4_CFG1: + case CS35L41_DSP1_STRMARB_TX5_CFG0: + case CS35L41_DSP1_STRMARB_TX5_CFG1: + case CS35L41_DSP1_STRMARB_TX6_CFG0: + case CS35L41_DSP1_STRMARB_TX6_CFG1: + case CS35L41_DSP1_STRMARB_TX7_CFG0: + case CS35L41_DSP1_STRMARB_TX7_CFG1: + case CS35L41_DSP1_STRMARB_RX0_CFG0: + case CS35L41_DSP1_STRMARB_RX0_CFG1: + case CS35L41_DSP1_STRMARB_RX1_CFG0: + case CS35L41_DSP1_STRMARB_RX1_CFG1: + case CS35L41_DSP1_STRMARB_RX2_CFG0: + case CS35L41_DSP1_STRMARB_RX2_CFG1: + case CS35L41_DSP1_STRMARB_RX3_CFG0: + case CS35L41_DSP1_STRMARB_RX3_CFG1: + case CS35L41_DSP1_STRMARB_RX4_CFG0: + case CS35L41_DSP1_STRMARB_RX4_CFG1: + case CS35L41_DSP1_STRMARB_RX5_CFG0: + case CS35L41_DSP1_STRMARB_RX5_CFG1: + case CS35L41_DSP1_STRMARB_RX6_CFG0: + case CS35L41_DSP1_STRMARB_RX6_CFG1: + case CS35L41_DSP1_STRMARB_RX7_CFG0: + case CS35L41_DSP1_STRMARB_RX7_CFG1: + case CS35L41_DSP1_STRMARB_IRQ0_CFG0: + case CS35L41_DSP1_STRMARB_IRQ0_CFG1: + case CS35L41_DSP1_STRMARB_IRQ0_CFG2: + case CS35L41_DSP1_STRMARB_IRQ1_CFG0: + case CS35L41_DSP1_STRMARB_IRQ1_CFG1: + case CS35L41_DSP1_STRMARB_IRQ1_CFG2: + case CS35L41_DSP1_STRMARB_IRQ2_CFG0: + case CS35L41_DSP1_STRMARB_IRQ2_CFG1: + case CS35L41_DSP1_STRMARB_IRQ2_CFG2: + case CS35L41_DSP1_STRMARB_IRQ3_CFG0: + case CS35L41_DSP1_STRMARB_IRQ3_CFG1: + case CS35L41_DSP1_STRMARB_IRQ3_CFG2: + case CS35L41_DSP1_STRMARB_IRQ4_CFG0: + case CS35L41_DSP1_STRMARB_IRQ4_CFG1: + case CS35L41_DSP1_STRMARB_IRQ4_CFG2: + case CS35L41_DSP1_STRMARB_IRQ5_CFG0: + case CS35L41_DSP1_STRMARB_IRQ5_CFG1: + case CS35L41_DSP1_STRMARB_IRQ5_CFG2: + case CS35L41_DSP1_STRMARB_IRQ6_CFG0: + case CS35L41_DSP1_STRMARB_IRQ6_CFG1: + case CS35L41_DSP1_STRMARB_IRQ6_CFG2: + case CS35L41_DSP1_STRMARB_IRQ7_CFG0: + case CS35L41_DSP1_STRMARB_IRQ7_CFG1: + case CS35L41_DSP1_STRMARB_IRQ7_CFG2: + case CS35L41_DSP1_STRMARB_RESYNC_MSK: + case CS35L41_DSP1_STRMARB_ERR_STATUS: + case CS35L41_DSP1_INTPCTL_RES_STATIC: + case CS35L41_DSP1_INTPCTL_RES_DYN: + case CS35L41_DSP1_INTPCTL_NMI_CTRL: + case CS35L41_DSP1_INTPCTL_IRQ_INV: + case CS35L41_DSP1_INTPCTL_IRQ_MODE: + case CS35L41_DSP1_INTPCTL_IRQ_EN: + case CS35L41_DSP1_INTPCTL_IRQ_MSK: + case CS35L41_DSP1_INTPCTL_IRQ_ERR: + case CS35L41_DSP1_INTPCTL_IRQ_PEND: + case CS35L41_DSP1_INTPCTL_TESTBITS: + case CS35L41_DSP1_WDT_CONTROL: + case CS35L41_DSP1_WDT_STATUS: + case CS35L41_OTP_TRIM_1: + case CS35L41_OTP_TRIM_2: + case CS35L41_OTP_TRIM_3: + case CS35L41_OTP_TRIM_4: + case CS35L41_OTP_TRIM_5: + case CS35L41_OTP_TRIM_6: + case CS35L41_OTP_TRIM_7: + case CS35L41_OTP_TRIM_8: + case CS35L41_OTP_TRIM_9: + case CS35L41_OTP_TRIM_10: + case CS35L41_OTP_TRIM_11: + case CS35L41_OTP_TRIM_12: + case CS35L41_OTP_TRIM_13: + case CS35L41_OTP_TRIM_14: + case CS35L41_OTP_TRIM_15: + case CS35L41_OTP_TRIM_16: + case CS35L41_OTP_TRIM_17: + case CS35L41_OTP_TRIM_18: + case CS35L41_OTP_TRIM_19: + case CS35L41_OTP_TRIM_20: + case CS35L41_OTP_TRIM_21: + case CS35L41_OTP_TRIM_22: + case CS35L41_OTP_TRIM_23: + case CS35L41_OTP_TRIM_24: + case CS35L41_OTP_TRIM_25: + case CS35L41_OTP_TRIM_26: + case CS35L41_OTP_TRIM_27: + case CS35L41_OTP_TRIM_28: + case CS35L41_OTP_TRIM_29: + case CS35L41_OTP_TRIM_30: + case CS35L41_OTP_TRIM_31: + case CS35L41_OTP_TRIM_32: + case CS35L41_OTP_TRIM_33: + case CS35L41_OTP_TRIM_34: + case CS35L41_OTP_TRIM_35: + case CS35L41_OTP_TRIM_36: + case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: + case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: + case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: + case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: + case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: + case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: + case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: + case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: + /*test regs*/ + case CS35L41_PLL_OVR: + case CS35L41_BST_TEST_DUTY: + case CS35L41_DIGPWM_IOCTRL: + return true; + default: + return false; + } +} + +bool cs35l41_precious_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: + return true; + default: + return false; + } +} + +bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L41_DEVID: + case CS35L41_SFT_RESET: + case CS35L41_FABID: + case CS35L41_REVID: + case CS35L41_DTEMP_EN: + case CS35L41_IRQ1_STATUS: + case CS35L41_IRQ1_STATUS1: + case CS35L41_IRQ1_STATUS2: + case CS35L41_IRQ1_STATUS3: + case CS35L41_IRQ1_STATUS4: + case CS35L41_IRQ1_RAW_STATUS1: + case CS35L41_IRQ1_RAW_STATUS2: + case CS35L41_IRQ1_RAW_STATUS3: + case CS35L41_IRQ1_RAW_STATUS4: + case CS35L41_IRQ1_FRC1: + case CS35L41_IRQ1_FRC2: + case CS35L41_IRQ1_FRC3: + case CS35L41_IRQ1_FRC4: + case CS35L41_IRQ1_EDGE1: + case CS35L41_IRQ1_EDGE4: + case CS35L41_IRQ1_POL1: + case CS35L41_IRQ1_POL2: + case CS35L41_IRQ1_POL3: + case CS35L41_IRQ1_POL4: + case CS35L41_IRQ1_DB3: + case CS35L41_IRQ2_STATUS: + case CS35L41_IRQ2_STATUS1: + case CS35L41_IRQ2_STATUS2: + case CS35L41_IRQ2_STATUS3: + case CS35L41_IRQ2_STATUS4: + case CS35L41_IRQ2_RAW_STATUS1: + case CS35L41_IRQ2_RAW_STATUS2: + case CS35L41_IRQ2_RAW_STATUS3: + case CS35L41_IRQ2_RAW_STATUS4: + case CS35L41_IRQ2_FRC1: + case CS35L41_IRQ2_FRC2: + case CS35L41_IRQ2_FRC3: + case CS35L41_IRQ2_FRC4: + case CS35L41_IRQ2_EDGE1: + case CS35L41_IRQ2_EDGE4: + case CS35L41_IRQ2_POL1: + case CS35L41_IRQ2_POL2: + case CS35L41_IRQ2_POL3: + case CS35L41_IRQ2_POL4: + case CS35L41_IRQ2_DB3: + case CS35L41_GPIO_STATUS1: + case CS35L41_OTP_TRIM_1: + case CS35L41_OTP_TRIM_2: + case CS35L41_OTP_TRIM_3: + case CS35L41_OTP_TRIM_4: + case CS35L41_OTP_TRIM_5: + case CS35L41_OTP_TRIM_6: + case CS35L41_OTP_TRIM_7: + case CS35L41_OTP_TRIM_8: + case CS35L41_OTP_TRIM_9: + case CS35L41_OTP_TRIM_10: + case CS35L41_OTP_TRIM_11: + case CS35L41_OTP_TRIM_12: + case CS35L41_OTP_TRIM_13: + case CS35L41_OTP_TRIM_14: + case CS35L41_OTP_TRIM_15: + case CS35L41_OTP_TRIM_16: + case CS35L41_OTP_TRIM_17: + case CS35L41_OTP_TRIM_18: + case CS35L41_OTP_TRIM_19: + case CS35L41_OTP_TRIM_20: + case CS35L41_OTP_TRIM_21: + case CS35L41_OTP_TRIM_22: + case CS35L41_OTP_TRIM_23: + case CS35L41_OTP_TRIM_24: + case CS35L41_OTP_TRIM_25: + case CS35L41_OTP_TRIM_26: + case CS35L41_OTP_TRIM_27: + case CS35L41_OTP_TRIM_28: + case CS35L41_OTP_TRIM_29: + case CS35L41_OTP_TRIM_30: + case CS35L41_OTP_TRIM_31: + case CS35L41_OTP_TRIM_32: + case CS35L41_OTP_TRIM_33: + case CS35L41_OTP_TRIM_34: + case CS35L41_OTP_TRIM_35: + case CS35L41_OTP_TRIM_36: + case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: + case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: + case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: + case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: + case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: + case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: + case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: + case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: + case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS: + case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: + return true; + default: + return false; + } +} + +static const struct cs35l41_otp_packed_element_t + otp_map_1[CS35L41_NUM_OTP_ELEM] = { + /* addr shift size */ + { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ + { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ + { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ + { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ + { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ + { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ + { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ + { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ + { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ + { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ + { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ + { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ + { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ + { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ + { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ + { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ + { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ + { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ + { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ + { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ + { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ + { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ + { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ + { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ + { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ + { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ + { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ + { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ + { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ + { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ + { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ + { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ + { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ + { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ + { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ + { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ + { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ + { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ + { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ + { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ + { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ + { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ + { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ + { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ + { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ + { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ + { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ + { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ + { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ + { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ + { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ + { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ + { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ + { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ + { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ + { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ + { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ + { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ + { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ + { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ + { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ + { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ + { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ + { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ + { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ + { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ + { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ + { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ + { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ + { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ + { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ + { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ + { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ + { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ + { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ + { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ + { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ + { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ + { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ + { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ + { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ + { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ + { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ + { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ + { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ + { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ + { 0x00007434, 17, 1 }, /*FORCE_CAL*/ + { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ + { 0x00007068, 0, 9 }, /*MODIX*/ + { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ + { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ + { 0x00000000, 0, 1 }, /*extra bit*/ + { 0x00017040, 0, 8 }, /*X_COORDINATE*/ + { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ + { 0x00017040, 16, 8 }, /*WAFER_ID*/ + { 0x00017040, 24, 8 }, /*DVS*/ + { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ + }; + +static const struct cs35l41_otp_packed_element_t + otp_map_2[CS35L41_NUM_OTP_ELEM] = { + /* addr shift size */ + { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ + { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ + { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ + { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ + { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ + { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ + { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ + { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ + { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ + { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ + { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ + { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ + { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ + { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ + { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ + { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ + { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ + { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ + { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ + { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ + { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ + { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ + { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ + { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ + { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ + { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ + { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ + { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ + { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ + { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ + { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ + { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ + { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ + { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ + { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ + { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ + { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ + { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ + { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ + { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ + { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ + { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ + { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ + { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ + { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ + { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ + { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ + { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ + { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ + { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ + { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ + { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ + { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ + { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ + { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ + { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ + { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ + { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ + { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ + { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ + { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ + { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ + { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ + { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ + { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ + { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ + { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ + { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ + { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ + { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ + { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ + { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ + { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ + { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ + { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ + { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ + { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ + { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ + { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ + { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ + { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ + { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ + { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ + { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ + { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ + { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ + { 0x00007434, 17, 1 }, /*FORCE_CAL*/ + { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ + { 0x00007068, 0, 9 }, /*MODIX*/ + { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ + { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ + { 0x00004000, 11, 1 }, /*VMON_POL*/ + { 0x00017040, 0, 8 }, /*X_COORDINATE*/ + { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ + { 0x00017040, 16, 8 }, /*WAFER_ID*/ + { 0x00017040, 24, 8 }, /*DVS*/ + { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ + }; + +const struct cs35l41_otp_map_element_t + cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS] = { + { + .id = 0x01, + .map = otp_map_1, + .num_elements = CS35L41_NUM_OTP_ELEM, + .bit_offset = 16, + .word_offset = 2, + }, + { + .id = 0x02, + .map = otp_map_2, + .num_elements = CS35L41_NUM_OTP_ELEM, + .bit_offset = 16, + .word_offset = 2, + }, + { + .id = 0x06, + .map = otp_map_2, + .num_elements = CS35L41_NUM_OTP_ELEM, + .bit_offset = 16, + .word_offset = 2, + }, + }; diff --git a/techpack/audio/asoc/codecs/cs35l41/cs35l41.c b/techpack/audio/asoc/codecs/cs35l41/cs35l41.c new file mode 100644 index 000000000000..47150d81329d --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/cs35l41.c @@ -0,0 +1,2015 @@ +/* + * cs35l41.c -- CS35l41 ALSA SoC audio driver + * + * Copyright 2018 Cirrus Logic, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: David Rhodes + * Brian Austin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#define DEBUG 1 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l41.h" +#include + +static const char *const cs35l41_supplies[] = { + "VA", + "VP", +}; + +struct cs35l41_pll_sysclk_config { + int freq; + int clk_cfg; +}; + +static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { + { 32768, 0x00 }, { 8000, 0x01 }, { 11025, 0x02 }, + { 12000, 0x03 }, { 16000, 0x04 }, { 22050, 0x05 }, + { 24000, 0x06 }, { 32000, 0x07 }, { 44100, 0x08 }, + { 48000, 0x09 }, { 88200, 0x0A }, { 96000, 0x0B }, + { 128000, 0x0C }, { 176400, 0x0D }, { 192000, 0x0E }, + { 256000, 0x0F }, { 352800, 0x10 }, { 384000, 0x11 }, + { 512000, 0x12 }, { 705600, 0x13 }, { 750000, 0x14 }, + { 768000, 0x15 }, { 1000000, 0x16 }, { 1024000, 0x17 }, + { 1200000, 0x18 }, { 1411200, 0x19 }, { 1500000, 0x1A }, + { 1536000, 0x1B }, { 2000000, 0x1C }, { 2048000, 0x1D }, + { 2400000, 0x1E }, { 2822400, 0x1F }, { 3000000, 0x20 }, + { 3072000, 0x21 }, { 3200000, 0x22 }, { 4000000, 0x23 }, + { 4096000, 0x24 }, { 4800000, 0x25 }, { 5644800, 0x26 }, + { 6000000, 0x27 }, { 6144000, 0x28 }, { 6250000, 0x29 }, + { 6400000, 0x2A }, { 6500000, 0x2B }, { 6750000, 0x2C }, + { 7526400, 0x2D }, { 8000000, 0x2E }, { 8192000, 0x2F }, + { 9600000, 0x30 }, { 11289600, 0x31 }, { 12000000, 0x32 }, + { 12288000, 0x33 }, { 12500000, 0x34 }, { 12800000, 0x35 }, + { 13000000, 0x36 }, { 13500000, 0x37 }, { 19200000, 0x38 }, + { 22579200, 0x39 }, { 24000000, 0x3A }, { 24576000, 0x3B }, + { 25000000, 0x3C }, { 25600000, 0x3D }, { 26000000, 0x3E }, + { 27000000, 0x3F }, +}; + +static const unsigned char cs35l41_bst_k1_table[4][5] = { + { 0x24, 0x32, 0x32, 0x4F, 0x57 }, + { 0x24, 0x32, 0x32, 0x4F, 0x57 }, + { 0x40, 0x32, 0x32, 0x4F, 0x57 }, + { 0x40, 0x32, 0x32, 0x4F, 0x57 } +}; + +static const unsigned char cs35l41_bst_k2_table[4][5] = { + { 0x24, 0x49, 0x66, 0xA3, 0xEA }, + { 0x24, 0x49, 0x66, 0xA3, 0xEA }, + { 0x48, 0x49, 0x66, 0xA3, 0xEA }, + { 0x48, 0x49, 0x66, 0xA3, 0xEA } +}; + +static const unsigned char cs35l41_bst_slope_table[4] = { 0x75, 0x6B, 0x3B, + 0x28 }; + +static int cs35l41_codec_set_sysclk(struct snd_soc_codec *codec, int clk_id, + int source, unsigned int freq, int dir); + +static int cs35l41_dsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (cs35l41->halo_booted == false) + wm_halo_early_event(w, kcontrol, event); + else + cs35l41->dsp.booted = true; + + return 0; + case SND_SOC_DAPM_PRE_PMD: + if (cs35l41->halo_booted == false) { + wm_halo_early_event(w, kcontrol, event); + wm_halo_event(w, kcontrol, event); + } + default: + return 0; + } +} + +static int cs35l41_dsp_load_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (cs35l41->halo_booted == false) { + wm_halo_event(w, kcontrol, event); + cs35l41->halo_booted = true; + } + default: + return 0; + } +} + +static int cs35l41_halo_booted_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = cs35l41->halo_booted; + + return 0; +} + +static int cs35l41_halo_booted_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + cs35l41->halo_booted = ucontrol->value.integer.value[0]; + + return 0; +} + +static int vendor_id_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = VENDOR_ID_NONE; + + if (cs35l41->pdata.spk_id_gpio_p) + ucontrol->value.integer.value[0] = + spk_id_get(cs35l41->pdata.spk_id_gpio_p); + + return 0; +} + +static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 0, 0, + TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 1, + 913, TLV_DB_SCALE_ITEM(-10200, 25, 0)); +static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); + +static const struct snd_kcontrol_new dre_ctrl = + SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); + +static const char *const cs35l41_pcm_sftramp_text[] = { "Off", ".5ms", "1ms", + "2ms", "4ms", "8ms", + "15ms", "30ms" }; + +static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L41_AMP_DIG_VOL_CTRL, 0, + cs35l41_pcm_sftramp_text); + +static const char *const cs35l41_cspl_cmd_text[] = { + "CSPL_MBOX_CMD_RESUME", + "CSPL_MBOX_CMD_REINIT", + "CSPL_MBOX_CMD_STOP_PRE_REINIT", +}; + +static const unsigned int cs35l41_cspl_cmd_val[] = { + (unsigned int)CSPL_MBOX_CMD_RESUME, + (unsigned int)CSPL_MBOX_CMD_REINIT, + (unsigned int)CSPL_MBOX_CMD_STOP_PRE_REINIT, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_cspl_cmd, SND_SOC_NOPM, 0, 0, + cs35l41_cspl_cmd_text, cs35l41_cspl_cmd_val); + +static bool cs35l41_is_csplmboxsts_correct(enum cs35l41_cspl_mboxcmd cmd, + enum cs35l41_cspl_mboxstate sts) +{ + switch (cmd) { + case CSPL_MBOX_CMD_NONE: + case CSPL_MBOX_CMD_UNKNOWN_CMD: + return true; + case CSPL_MBOX_CMD_PAUSE: + return (sts == CSPL_MBOX_STS_PAUSED); + case CSPL_MBOX_CMD_RESUME: + return (sts == CSPL_MBOX_STS_RUNNING); + case CSPL_MBOX_CMD_REINIT: + return (sts == CSPL_MBOX_STS_RUNNING); + case CSPL_MBOX_CMD_STOP_PRE_REINIT: + return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); + default: + return false; + } +} + +static int cs35l41_set_csplmboxcmd(struct cs35l41_private *cs35l41, + enum cs35l41_cspl_mboxcmd cmd) +{ + int ret; + unsigned int sts; + + /* Reset DSP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ2_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT); + + /* Reset AP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT); + + /* + * Set mailbox cmd + */ + reinit_completion(&cs35l41->mbox_cmd); + /* Unmask DSP INT */ + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ2_MASK2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT, 0); + /* Unmask AP INT */ + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT, 0); + regmap_write(cs35l41->regmap, CS35L41_CSPL_MBOX_CMD_DRV, cmd); + ret = wait_for_completion_timeout(&cs35l41->mbox_cmd, + msecs_to_jiffies(CS35L41_MBOXWAIT)); + if (ret == 0) { + dev_err(cs35l41->dev, + "Timout waiting for DSP to set mbox cmd\n"); + ret = -ETIMEDOUT; + } + + /* Mask AP INT */ + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT); + /* Mask DSP INT */ + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ2_MASK2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT); + + if (regmap_read(cs35l41->regmap, CS35L41_CSPL_MBOX_STS, &sts) < 0) { + dev_err(cs35l41->dev, "Failed to read %u\n", + CS35L41_CSPL_MBOX_STS); + ret = -EACCES; + } + + if (!cs35l41_is_csplmboxsts_correct(cmd, + (enum cs35l41_cspl_mboxstate)sts)) { + dev_err(cs35l41->dev, + "Failed to set mailbox(cmd: %u, sts: %u)\n", cmd, sts); + ret = -ENOMSG; + } + + return ret; +} + +static int cs35l41_cspl_cmd_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + struct soc_enum *soc_enum; + unsigned int i = ucontrol->value.enumerated.item[0]; + + soc_enum = (struct soc_enum *)kcontrol->private_value; + + if (i >= soc_enum->items) { + dev_err(codec->dev, "Invalid mixer input (%u)\n", i); + return -EINVAL; + } + + cs35l41->cspl_cmd = soc_enum->values[i]; + + return 0; +} + +static int cs35l41_cspl_cmd_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + struct soc_enum *soc_enum; + unsigned int i; + int ret = 0; + + soc_enum = (struct soc_enum *)kcontrol->private_value; + + for (i = 0; i < soc_enum->items; i++) { + if (cs35l41->cspl_cmd == soc_enum->values[i]) + break; + } + + if (i >= soc_enum->items) { + /* Cannot find value */ + dev_err(cs35l41->dev, "Cannot find cspl cmd\n"); + i = 0; + ret = -EINVAL; + } + + ucontrol->value.enumerated.item[0] = i; + + return ret; +} +static const char *virt_text[] = { "None", "Ref" }; +static SOC_ENUM_SINGLE_DECL(virt_enum, SND_SOC_NOPM, 2, virt_text); + +static const struct snd_kcontrol_new virt_mux = + SOC_DAPM_ENUM("Virt Connect", virt_enum); + +static const char *const cs35l41_pcm_source_texts[] = { "None", "ASP", "DSP" }; +static const unsigned int cs35l41_pcm_source_values[] = { 0x00, 0x08, 0x32 }; +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, CS35L41_DAC_PCM1_SRC, + 0, CS35L41_ASP_SOURCE_MASK, + cs35l41_pcm_source_texts, + cs35l41_pcm_source_values); + +static const struct snd_kcontrol_new pcm_source_mux = + SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); + +static const char *const cs35l41_tx_input_texts[] = { + "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", "VPMON", "DSPTX1", "DSPTX2" +}; +static const unsigned int cs35l41_tx_input_values[] = { + 0x00, + CS35L41_INPUT_SRC_ASPRX1, + CS35L41_INPUT_SRC_ASPRX2, + CS35L41_INPUT_SRC_VMON, + CS35L41_INPUT_SRC_IMON, + CS35L41_INPUT_SRC_VPMON, + CS35L41_INPUT_DSP_TX1, + CS35L41_INPUT_DSP_TX2 +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, CS35L41_ASP_TX1_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx1_mux = + SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, CS35L41_ASP_TX2_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx2_mux = + SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, CS35L41_ASP_TX3_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx3_mux = + SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, CS35L41_ASP_TX4_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx4_mux = + SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, CS35L41_DSP1_RX1_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new dsp_rx1_mux = + SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, CS35L41_DSP1_RX2_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new dsp_rx2_mux = + SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); + +static const char *const vendor_id_text[] = { "None", "AAC", "SSI", "GOER", + "Unknown" }; +static const struct soc_enum vendor_id[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vendor_id_text), vendor_id_text), +}; + +static const struct snd_kcontrol_new cs35l41_aud_controls[] = { + SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 3, + 0x4CF, 0x391, dig_vol_tlv), + SOC_SINGLE_TLV("AMP PCM Gain", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, + amp_gain_tlv), + SOC_SINGLE_RANGE("ASPTX1 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 0, 0, + 7, 0), + SOC_SINGLE_RANGE("ASPTX2 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 8, 0, + 7, 0), + SOC_SINGLE_RANGE("ASPTX3 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 16, + 0, 7, 0), + SOC_SINGLE_RANGE("ASPTX4 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 24, + 0, 7, 0), + SOC_SINGLE_RANGE("ASPRX1 Slot Position", CS35L41_SP_FRAME_RX_SLOT, 0, 0, + 7, 0), + SOC_SINGLE_RANGE("ASPRX2 Slot Position", CS35L41_SP_FRAME_RX_SLOT, 8, 0, + 7, 0), + SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), + SOC_VALUE_ENUM_EXT("CSPL Command", cs35l41_cspl_cmd, + cs35l41_cspl_cmd_get, cs35l41_cspl_cmd_put), + SOC_SINGLE_EXT("DSP Booted", SND_SOC_NOPM, 0, 1, 0, + cs35l41_halo_booted_get, cs35l41_halo_booted_put), + WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), + SOC_ENUM_EXT("SPK ID", vendor_id, vendor_id_get, NULL), +}; + +static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) { + if (cs35l41_otp_map_map[i].id == otp_id) + return &cs35l41_otp_map_map[i]; + } + + return NULL; +} + +static int cs35l41_otp_unpack(void *data) +{ + struct cs35l41_private *cs35l41 = data; + u32 otp_mem[32]; + int i; + int bit_offset, word_offset; + unsigned int bit_sum = 8; + u32 otp_val, otp_id_reg; + const struct cs35l41_otp_map_element_t *otp_map_match; + const struct cs35l41_otp_packed_element_t *otp_map; + int ret; + struct spi_device *spi = NULL; + u32 orig_spi_freq = 0; + + ret = regmap_read(cs35l41->regmap, CS35L41_OTPID, &otp_id_reg); + if (ret < 0) { + dev_err(cs35l41->dev, "Read OTP ID failed\n"); + return -EINVAL; + } + + otp_map_match = cs35l41_find_otp_map(otp_id_reg); + + if (otp_map_match == NULL) { + dev_err(cs35l41->dev, "OTP Map matching ID %d not found\n", + otp_id_reg); + return -EINVAL; + } + + if (cs35l41->bus_spi) { + spi = to_spi_device(cs35l41->dev); + orig_spi_freq = spi->max_speed_hz; + spi->max_speed_hz = CS35L41_SPI_MAX_FREQ_OTP; + spi_setup(spi); + } + +#define MAX_BULK_READ_SIZE 4 + for (i = 0; i < CS35L41_OTP_SIZE_WORDS / MAX_BULK_READ_SIZE; i++) { + ret = regmap_bulk_read( + cs35l41->regmap, + CS35L41_OTP_MEM0 + i * 4 * MAX_BULK_READ_SIZE, + &otp_mem[i * MAX_BULK_READ_SIZE], MAX_BULK_READ_SIZE); + } + + if (ret < 0) { + dev_err(cs35l41->dev, "Read OTP Mem failed\n"); + return -EINVAL; + } + + if (cs35l41->bus_spi) { + spi->max_speed_hz = orig_spi_freq; + spi_setup(spi); + } + + otp_map = otp_map_match->map; + + bit_offset = otp_map_match->bit_offset; + word_offset = otp_map_match->word_offset; + + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000055); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Unlock key failed 1/2\n"); + return -EINVAL; + } + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000AA); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Unlock key failed 2/2\n"); + return -EINVAL; + } + + for (i = 0; i < otp_map_match->num_elements; i++) { + dev_dbg(cs35l41->dev, + "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d\n", + bit_offset, word_offset, bit_sum % 32); + if (bit_offset + otp_map[i].size - 1 >= 32) { + otp_val = (otp_mem[word_offset] & + GENMASK(31, bit_offset)) >> + bit_offset; + otp_val |= + (otp_mem[++word_offset] & + GENMASK(bit_offset + otp_map[i].size - 33, 0)) + << (32 - bit_offset); + bit_offset += otp_map[i].size - 32; + } else { + otp_val = (otp_mem[word_offset] & + GENMASK(bit_offset + otp_map[i].size - 1, + bit_offset)) >> + bit_offset; + bit_offset += otp_map[i].size; + } + bit_sum += otp_map[i].size; + + if (bit_offset == 32) { + bit_offset = 0; + word_offset++; + } + + if (otp_map[i].reg != 0) { + ret = regmap_update_bits( + cs35l41->regmap, otp_map[i].reg, + GENMASK(otp_map[i].shift + otp_map[i].size - 1, + otp_map[i].shift), + otp_val << otp_map[i].shift); + if (ret < 0) { + dev_err(cs35l41->dev, "Write OTP val failed\n"); + return -EINVAL; + } + } + } + + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000CC); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Lock key failed 1/2\n"); + return -EINVAL; + } + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000033); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Lock key failed 2/2\n"); + return -EINVAL; + } + + return 0; +} + +static irqreturn_t cs35l41_irq(int irq, void *data) +{ + struct cs35l41_private *cs35l41 = data; + unsigned int status[4]; + unsigned int masks[4]; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(status); i++) { + regmap_read(cs35l41->regmap, + CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), + &status[i]); + regmap_read(cs35l41->regmap, + CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), + &masks[i]); + } + + /* Check to see if unmasked bits are active */ + if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && + !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) + return IRQ_NONE; + + if (status[1] & (1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT)) { + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT); + complete(&cs35l41->mbox_cmd); + } + + if (status[0] & CS35L41_PUP_DONE_MASK) { + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_PUP_DONE_MASK); + complete(&cs35l41->global_pup_done); + } + + if (status[0] & CS35L41_PDN_DONE_MASK) { + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_PDN_DONE_MASK); + complete(&cs35l41->global_pdn_done); + } + + /* + * The following interrupts require a + * protection release cycle to get the + * speaker out of Safe-Mode. + */ + if (status[0] & CS35L41_AMP_SHORT_ERR) { + dev_crit(cs35l41->dev, "Amp short error\n"); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_AMP_SHORT_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_AMP_SHORT_ERR_RLS, + CS35L41_AMP_SHORT_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_AMP_SHORT_ERR_RLS, 0); + } + + if (status[0] & CS35L41_TEMP_WARN) { + dev_crit(cs35l41->dev, "Over temperature warning\n"); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_TEMP_WARN); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_WARN_ERR_RLS, + CS35L41_TEMP_WARN_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_WARN_ERR_RLS, 0); + } + + if (status[0] & CS35L41_TEMP_ERR) { + dev_crit(cs35l41->dev, "Over temperature error\n"); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_TEMP_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_ERR_RLS, CS35L41_TEMP_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_ERR_RLS, 0); + } + + if (status[0] & CS35L41_BST_OVP_ERR) { + dev_crit(cs35l41->dev, "VBST Over Voltage error\n"); + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, + CS35L41_BST_EN_MASK, 0); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_BST_OVP_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_OVP_ERR_RLS, + CS35L41_BST_OVP_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_OVP_ERR_RLS, 0); + regmap_update_bits( + cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); + } + + if (status[0] & CS35L41_BST_DCM_UVP_ERR) { + dev_crit(cs35l41->dev, "DCM VBST Under Voltage Error\n"); + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, + CS35L41_BST_EN_MASK, 0); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_BST_DCM_UVP_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_UVP_ERR_RLS, + CS35L41_BST_UVP_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_UVP_ERR_RLS, 0); + regmap_update_bits( + cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); + } + + if (status[0] & CS35L41_BST_SHORT_ERR) { + dev_crit(cs35l41->dev, "LBST error: powering off!\n"); + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, + CS35L41_BST_EN_MASK, 0); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_BST_SHORT_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_SHORT_ERR_RLS, + CS35L41_BST_SHORT_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_SHORT_ERR_RLS, 0); + regmap_update_bits( + cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); + } + + if (status[3] & CS35L41_OTP_BOOT_DONE) { + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, + CS35L41_OTP_BOOT_DONE, + CS35L41_OTP_BOOT_DONE); + } + + return IRQ_HANDLED; +} + +static const struct reg_sequence cs35l41_pup_patch[] = { + { 0x00000040, 0x00000055 }, { 0x00000040, 0x000000AA }, + { 0x00002084, 0x002F1AA0 }, { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +static const struct reg_sequence cs35l41_pdn_patch[] = { + { 0x00000040, 0x00000055 }, { 0x00000040, 0x000000AA }, + { 0x00002084, 0x002F1AA3 }, { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + pr_debug("++++>CSPL: %s, event = %d.\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_multi_reg_write_bypassed(cs35l41->regmap, + cs35l41_pup_patch, + ARRAY_SIZE(cs35l41_pup_patch)); + + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, + CS35L41_GLOBAL_EN_MASK, + 1 << CS35L41_GLOBAL_EN_SHIFT); + + usleep_range(1000, 1100); + + if (cs35l41->halo_booted) { + if (cs35l41->cspl_cmd == CSPL_MBOX_CMD_STOP_PRE_REINIT) + /* Send this command on power down event */ + ret = cs35l41_set_csplmboxcmd( + cs35l41, CSPL_MBOX_CMD_RESUME); + else + ret = cs35l41_set_csplmboxcmd( + cs35l41, cs35l41->cspl_cmd); + } + break; + case SND_SOC_DAPM_POST_PMD: + if (cs35l41->halo_booted) { + if (cs35l41->cspl_cmd == CSPL_MBOX_CMD_STOP_PRE_REINIT) + ret = cs35l41_set_csplmboxcmd( + cs35l41, cs35l41->cspl_cmd); + else + ret = cs35l41_set_csplmboxcmd( + cs35l41, CSPL_MBOX_CMD_PAUSE); + } + + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, + CS35L41_GLOBAL_EN_MASK, 0); + + usleep_range(1000, 1100); + + regmap_multi_reg_write_bypassed(cs35l41->regmap, + cs35l41_pdn_patch, + ARRAY_SIZE(cs35l41_pdn_patch)); + break; + default: + dev_err(codec->dev, "Invalid event = 0x%x\n", event); + ret = -EINVAL; + } + pr_debug("----CSPL: %s.\n", __func__); + return ret; +} + +static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { + + SND_SOC_DAPM_SPK("DSP1 Preload", NULL), + SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, + cs35l41_dsp_power_ev, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, + cs35l41_dsp_load_ev, SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_OUTPUT("SPK"), + + SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), + SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), + + SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L41_PWR_CTRL2, 12, 0), + SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L41_PWR_CTRL2, 13, 0), + SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L41_PWR_CTRL2, 8, 0), + SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L41_PWR_CTRL2, 9, 0), + SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, CS35L41_PWR_CTRL2, 10, 0), + SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), + + SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, + cs35l41_main_amp_event, + SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_INPUT("VP"), + SND_SOC_DAPM_INPUT("VBST"), + SND_SOC_DAPM_INPUT("ISENSE"), + SND_SOC_DAPM_INPUT("VSENSE"), + SND_SOC_DAPM_INPUT("TEMP"), + + SND_SOC_DAPM_MUX("ASPTX Ref", SND_SOC_NOPM, 0, 0, &virt_mux), + SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), + SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), + SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), + SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), + SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), + SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), + SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), + SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), + +}; + +static const struct snd_soc_dapm_route cs35l41_audio_map[] = { + + { "DSP1", NULL, "DSP1 Preloader" }, + { "DSP1 Preload", NULL, "DSP1 Preloader" }, + + { "DSP RX1 Source", "VMON", "VMON ADC" }, + { "DSP RX1 Source", "IMON", "IMON ADC" }, + { "DSP RX1 Source", "VPMON", "VPMON ADC" }, + { "DSP RX1 Source", "DSPTX1", "DSP1" }, + { "DSP RX1 Source", "DSPTX2", "DSP1" }, + { "DSP RX1 Source", "ASPRX1", "ASPRX1" }, + { "DSP RX1 Source", "ASPRX2", "ASPRX2" }, + { "DSP RX1 Source", "Zero", "ASPRX1" }, + { "DSP1", NULL, "DSP RX1 Source" }, + + { "DSP RX2 Source", "VMON", "VMON ADC" }, + { "DSP RX2 Source", "IMON", "IMON ADC" }, + { "DSP RX2 Source", "VPMON", "VPMON ADC" }, + { "DSP RX2 Source", "DSPTX1", "DSP1" }, + { "DSP RX2 Source", "DSPTX2", "DSP1" }, + { "DSP RX2 Source", "ASPRX1", "ASPRX1" }, + { "DSP RX2 Source", "ASPRX2", "ASPRX2" }, + { "DSP RX2 Source", "Zero", "ASPRX1" }, + { "DSP1", NULL, "DSP RX2 Source" }, + + { "ASP TX1 Source", "VMON", "VMON ADC" }, + { "ASP TX1 Source", "IMON", "IMON ADC" }, + { "ASP TX1 Source", "VPMON", "VPMON ADC" }, + { "ASP TX1 Source", "DSPTX1", "DSP1" }, + { "ASP TX1 Source", "DSPTX2", "DSP1" }, + { "ASP TX1 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX1 Source", "ASPRX2", "ASPRX2" }, + { "ASP TX2 Source", "VMON", "VMON ADC" }, + { "ASP TX2 Source", "IMON", "IMON ADC" }, + { "ASP TX2 Source", "VPMON", "VPMON ADC" }, + { "ASP TX2 Source", "DSPTX1", "DSP1" }, + { "ASP TX2 Source", "DSPTX2", "DSP1" }, + { "ASP TX2 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX2 Source", "ASPRX2", "ASPRX2" }, + { "ASP TX3 Source", "VMON", "VMON ADC" }, + { "ASP TX3 Source", "IMON", "IMON ADC" }, + { "ASP TX3 Source", "VPMON", "VPMON ADC" }, + { "ASP TX3 Source", "DSPTX1", "DSP1" }, + { "ASP TX3 Source", "DSPTX2", "DSP1" }, + { "ASP TX3 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX3 Source", "ASPRX2", "ASPRX2" }, + { "ASP TX4 Source", "VMON", "VMON ADC" }, + { "ASP TX4 Source", "IMON", "IMON ADC" }, + { "ASP TX4 Source", "VPMON", "VPMON ADC" }, + { "ASP TX4 Source", "DSPTX1", "DSP1" }, + { "ASP TX4 Source", "DSPTX2", "DSP1" }, + { "ASP TX4 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX4 Source", "ASPRX2", "ASPRX2" }, + { "ASPTX1", NULL, "ASP TX1 Source" }, + { "ASPTX2", NULL, "ASP TX2 Source" }, + { "ASPTX3", NULL, "ASP TX3 Source" }, + { "ASPTX4", NULL, "ASP TX4 Source" }, + { "AMP Capture", NULL, "ASPTX1" }, + { "AMP Capture", NULL, "ASPTX2" }, + { "AMP Capture", NULL, "ASPTX3" }, + { "AMP Capture", NULL, "ASPTX4" }, + + { "VMON ADC", NULL, "ASPRX1" }, + { "IMON ADC", NULL, "ASPRX1" }, + { "VPMON ADC", NULL, "ASPRX1" }, + { "TEMPMON ADC", NULL, "ASPRX1" }, + { "VBSTMON ADC", NULL, "ASPRX1" }, + + { "DSP1", NULL, "IMON ADC" }, + { "DSP1", NULL, "VMON ADC" }, + { "DSP1", NULL, "VBSTMON ADC" }, + { "DSP1", NULL, "VPMON ADC" }, + { "DSP1", NULL, "TEMPMON ADC" }, + + { "ASPRX1", NULL, "AMP Playback" }, + { "ASPRX2", NULL, "AMP Playback" }, + { "DRE", "Switch", "CLASS H" }, + { "Main AMP", NULL, "CLASS H" }, + { "Main AMP", NULL, "DRE" }, + { "SPK", NULL, "Main AMP" }, + { "Main AMP", NULL, "ASPTX Ref" }, + { "ASPTX Ref", "Ref", "ASPTX1" }, + { "ASPTX Ref", "Ref", "ASPTX2" }, + { "PCM Source", "ASP", "ASPRX1" }, + { "PCM Source", "DSP", "DSP1" }, + { "CLASS H", NULL, "PCM Source" }, + +}; + +static const struct wm_adsp_region cs35l41_dsp1_regions[] = { + { .type = WMFW_HALO_PM_PACKED, .base = CS35L41_DSP1_PMEM_0 }, + { .type = WMFW_HALO_XM_PACKED, .base = CS35L41_DSP1_XMEM_PACK_0 }, + { .type = WMFW_HALO_YM_PACKED, .base = CS35L41_DSP1_YMEM_PACK_0 }, + { .type = WMFW_ADSP2_XM, .base = CS35L41_DSP1_XMEM_UNPACK24_0 }, + { .type = WMFW_ADSP2_YM, .base = CS35L41_DSP1_YMEM_UNPACK24_0 }, +}; + +static int cs35l41_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct cs35l41_private *cs35l41 = + snd_soc_codec_get_drvdata(codec_dai->codec); + unsigned int asp_fmt, lrclk_fmt, sclk_fmt, slave_mode; + + pr_debug("++++>CSPL: %s, fmt = %d.\n", __func__, fmt); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + slave_mode = 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + slave_mode = 0; + break; + default: + dev_warn( + cs35l41->dev, + "cs35l41_set_dai_fmt: Mixed master mode unsupported\n"); + return -EINVAL; + } + + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_MSTR_MASK, + slave_mode << CS35L41_SCLK_MSTR_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_MSTR_MASK, + slave_mode << CS35L41_LRCLK_MSTR_SHIFT); + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + asp_fmt = 0; + cs35l41->i2s_mode = false; + cs35l41->dspa_mode = true; + break; + case SND_SOC_DAIFMT_I2S: + asp_fmt = 2; + cs35l41->i2s_mode = true; + cs35l41->dspa_mode = false; + break; + default: + dev_warn( + cs35l41->dev, + "cs35l41_set_dai_fmt: Invalid or unsupported DAI format\n"); + return -EINVAL; + } + + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_FMT_MASK, + asp_fmt << CS35L41_ASP_FMT_SHIFT); + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_IF: + lrclk_fmt = 1; + sclk_fmt = 0; + break; + case SND_SOC_DAIFMT_IB_NF: + lrclk_fmt = 0; + sclk_fmt = 1; + break; + case SND_SOC_DAIFMT_IB_IF: + lrclk_fmt = 1; + sclk_fmt = 1; + break; + case SND_SOC_DAIFMT_NB_NF: + lrclk_fmt = 0; + sclk_fmt = 0; + break; + default: + dev_warn(cs35l41->dev, + "cs35l41_set_dai_fmt: Invalid DAI clock INV\n"); + return -EINVAL; + } + + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_INV_MASK, + lrclk_fmt << CS35L41_LRCLK_INV_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_INV_MASK, + sclk_fmt << CS35L41_SCLK_INV_SHIFT); + + pr_debug("---->CSPL: %s, fmt = %d.\n", __func__, fmt); + return 0; +} + +struct cs35l41_global_fs_config { + int rate; + int fs_cfg; +}; + +static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { + { 12000, 0x01 }, { 24000, 0x02 }, { 48000, 0x03 }, { 96000, 0x04 }, + { 192000, 0x05 }, { 11025, 0x09 }, { 22050, 0x0A }, { 44100, 0x0B }, + { 88200, 0x0C }, { 176400, 0x0D }, { 8000, 0x11 }, { 16000, 0x12 }, + { 32000, 0x13 }, +}; + +static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(dai->codec); + int i; + unsigned int rate = params_rate(params); + u8 asp_width, asp_wl; + + pr_debug("++++>CSPL: %s.\n", __func__); + for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { + if (rate == cs35l41_fs_rates[i].rate) + break; + } + regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, + CS35L41_GLOBAL_FS_MASK, + cs35l41_fs_rates[i].fs_cfg + << CS35L41_GLOBAL_FS_SHIFT); + + asp_wl = params_width(params); + asp_width = params_physical_width(params); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_WIDTH_RX_MASK, + asp_width << CS35L41_ASP_WIDTH_RX_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, + CS35L41_ASP_RX_WL_MASK, + asp_wl << CS35L41_ASP_RX_WL_SHIFT); + if (cs35l41->i2s_mode || cs35l41->dspa_mode) { + regmap_update_bits( + cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT, + CS35L41_ASP_RX1_SLOT_MASK, + ((cs35l41->pdata.right_channel) ? 1 : 0) + << CS35L41_ASP_RX1_SLOT_SHIFT); + regmap_update_bits( + cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT, + CS35L41_ASP_RX2_SLOT_MASK, + ((cs35l41->pdata.right_channel) ? 0 : 1) + << CS35L41_ASP_RX2_SLOT_SHIFT); + } + } else { + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_WIDTH_TX_MASK, + asp_width << CS35L41_ASP_WIDTH_TX_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, + CS35L41_ASP_TX_WL_MASK, + asp_wl << CS35L41_ASP_TX_WL_SHIFT); + } + + pr_debug("---->CSPL: %s.\n", __func__); + return 0; +} + +static int cs35l41_get_clk_config(int freq) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { + if (cs35l41_pll_sysclk[i].freq == freq) + return cs35l41_pll_sysclk[i].clk_cfg; + } + + return -EINVAL; +} + +#if 0 +static const unsigned int cs35l41_src_rates[] = { + 8000, 12000, 11025, 16000, 22050, 24000, 32000, + 44100, 48000, 88200, 96000, 176400, 192000 +}; + +static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { + .count = ARRAY_SIZE(cs35l41_src_rates), + .list = cs35l41_src_rates, +}; +#endif + +static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + pr_debug("++++>CSPL: %s.\n", __func__); + + cs35l41_set_dai_fmt(dai, SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_I2S); + cs35l41_codec_set_sysclk(codec, 0, 0, 1536000, 0); +#if 0 + if (substream->runtime) + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, &cs35l41_constraints); +#endif + pr_debug("---->CSPL: %s.\n", __func__); + return 0; +} + +static int cs35l41_codec_set_sysclk(struct snd_soc_codec *codec, int clk_id, + int source, unsigned int freq, int dir) +{ + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + int val = 0; + cs35l41->extclk_freq = freq; + + pr_debug("++++>CSPL: %s: clk_id = %d, src = %d, freq = %d, dir = %d.\n", + __func__, clk_id, source, freq, dir); + dev_info(codec->dev, "%s: clk_id=%d, src=%d, freq=%d\n", __func__, + clk_id, source, freq); + + switch (clk_id) { + case 0: + cs35l41->clksrc = CS35L41_PLLSRC_SCLK; + break; + case 1: + cs35l41->clksrc = CS35L41_PLLSRC_LRCLK; + break; + case 2: + cs35l41->clksrc = CS35L41_PLLSRC_PDMCLK; + break; + case 3: + cs35l41->clksrc = CS35L41_PLLSRC_SELF; + break; + case 4: + cs35l41->clksrc = CS35L41_PLLSRC_MCLK; + break; + default: + dev_err(codec->dev, "Invalid CLK Config\n"); + return -EINVAL; + } + + cs35l41->extclk_cfg = cs35l41_get_clk_config(freq); + + if (cs35l41->extclk_cfg < 0) { + dev_err(codec->dev, "Invalid CLK Config: %d, freq: %u\n", + cs35l41->extclk_cfg, freq); + return -EINVAL; + } + + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_OPENLOOP_MASK, + 1 << CS35L41_PLL_OPENLOOP_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_REFCLK_FREQ_MASK, + cs35l41->extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_EN_MASK, + 0 << CS35L41_PLL_CLK_EN_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_SEL_MASK, cs35l41->clksrc); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_OPENLOOP_MASK, + 0 << CS35L41_PLL_OPENLOOP_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_EN_MASK, + 1 << CS35L41_PLL_CLK_EN_SHIFT); + + regmap_read(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, &val); + dev_info(codec->dev, "%s: 0x%x <== 0x%x\n", __func__, + CS35L41_PLL_CLK_CTRL, val); + pr_debug("---->CSPL: %s.\n", __func__); + + return 0; +} + +static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + pr_debug("++++>CSPL: %s: clk_id=%d, freq=%d, dir=%d\n", __func__, + clk_id, freq, dir); + if (cs35l41_get_clk_config(freq) < 0) { + dev_err(codec->dev, "Invalid CLK Config freq: %u\n", freq); + return -EINVAL; + } + + if (clk_id == CS35L41_PLLSRC_SCLK) + cs35l41->sclk = freq; + pr_debug("---->CSPL: %s.\n", __func__); + + return 0; +} + +static int cs35l41_digital_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(cs35l41->dev, "%s: %d\n", __func__, mute); + pr_debug("++++>CSPL: %s, mute = %d.\n", __func__, mute); + + if (mute) { + regmap_update_bits(cs35l41->regmap, 0x6000, 0x7ff << 3, + 0x400 << 3 | 0x7); + mdelay(30); + } else { + regmap_update_bits(cs35l41->regmap, 0x6000, 0x7ff << 3, + 0x0 << 3 | 0x4); + } + + pr_debug("---->CSPL: %s.\n", __func__); + return 0; +} + +static int cs35l41_boost_config(struct cs35l41_private *cs35l41, int boost_ind, + int boost_cap, int boost_ipk) +{ + int ret; + unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; + struct regmap *regmap = cs35l41->regmap; + struct device *dev = cs35l41->dev; + + switch (boost_ind) { + case 1000: /* 1.0 uH */ + bst_lbst_val = 0; + break; + case 1200: /* 1.2 uH */ + bst_lbst_val = 1; + break; + case 1500: /* 1.5 uH */ + bst_lbst_val = 2; + break; + case 2200: /* 2.2 uH */ + bst_lbst_val = 3; + break; + default: + dev_err(dev, "Invalid boost inductor value: %d nH\n", + boost_ind); + return -EINVAL; + } + + switch (boost_cap) { + case 0 ... 19: + bst_cbst_range = 0; + break; + case 20 ... 50: + bst_cbst_range = 1; + break; + case 51 ... 100: + bst_cbst_range = 2; + break; + case 101 ... 200: + bst_cbst_range = 3; + break; + default: /* 201 uF and greater */ + bst_cbst_range = 4; + } + + ret = regmap_update_bits( + regmap, CS35L41_BSTCVRT_COEFF, CS35L41_BST_K1_MASK, + cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] + << CS35L41_BST_K1_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost K1 coefficient\n"); + return ret; + } + + ret = regmap_update_bits( + regmap, CS35L41_BSTCVRT_COEFF, CS35L41_BST_K2_MASK, + cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range] + << CS35L41_BST_K2_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost K2 coefficient\n"); + return ret; + } + + ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, + CS35L41_BST_SLOPE_MASK, + cs35l41_bst_slope_table[bst_lbst_val] + << CS35L41_BST_SLOPE_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost slope coefficient\n"); + return ret; + } + + ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, + CS35L41_BST_LBST_VAL_MASK, + bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost inductor value\n"); + return ret; + } + + if ((boost_ipk < 1600) || (boost_ipk > 4500)) { + dev_err(dev, "Invalid boost inductor peak current: %d mA\n", + boost_ipk); + return -EINVAL; + } + bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; + + ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, + CS35L41_BST_IPK_MASK, + bst_ipk_scaled << CS35L41_BST_IPK_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost inductor peak current\n"); + return ret; + } + + return 0; +} + +static int cs35l41_codec_probe(struct snd_soc_codec *codec) +{ + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct classh_cfg *classh = &cs35l41->pdata.classh_config; + int ret; + + /* Set Platform Data */ + /* Required */ + if (cs35l41->pdata.bst_ipk && cs35l41->pdata.bst_ind && + cs35l41->pdata.bst_cap) { + ret = cs35l41_boost_config(cs35l41, cs35l41->pdata.bst_ind, + cs35l41->pdata.bst_cap, + cs35l41->pdata.bst_ipk); + if (ret) { + dev_err(cs35l41->dev, "Error in Boost DT config\n"); + return ret; + } + } else { + dev_err(cs35l41->dev, "Incomplete Boost component DT config\n"); + return -EINVAL; + } + + /* Optional */ + if (cs35l41->pdata.sclk_frc) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_FRC_MASK, + cs35l41->pdata.sclk_frc + << CS35L41_SCLK_FRC_SHIFT); + + if (cs35l41->pdata.lrclk_frc) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_FRC_MASK, + cs35l41->pdata.lrclk_frc + << CS35L41_LRCLK_FRC_SHIFT); + + if (cs35l41->pdata.amp_gain_zc) + regmap_update_bits(cs35l41->regmap, CS35L41_AMP_GAIN_CTRL, + CS35L41_AMP_GAIN_ZC_MASK, + cs35l41->pdata.amp_gain_zc + << CS35L41_AMP_GAIN_ZC_SHIFT); + + if (cs35l41->pdata.bst_vctrl) + regmap_update_bits(cs35l41->regmap, CS35L41_BSTCVRT_VCTRL1, + CS35L41_BST_CTL_MASK, + cs35l41->pdata.bst_vctrl); + + if (cs35l41->pdata.temp_warn_thld) + regmap_update_bits(cs35l41->regmap, CS35L41_DTEMP_WARN_THLD, + CS35L41_TEMP_THLD_MASK, + cs35l41->pdata.temp_warn_thld); + + if (cs35l41->pdata.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && + cs35l41->pdata.dout_hiz >= 0) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, + CS35L41_ASP_DOUT_HIZ_MASK, + cs35l41->pdata.dout_hiz); + + if (cs35l41->pdata.ng_enable) { + regmap_update_bits(cs35l41->regmap, CS35L41_MIXER_NGATE_CH1_CFG, + CS35L41_NG_ENABLE_MASK, + CS35L41_NG_ENABLE_MASK); + regmap_update_bits(cs35l41->regmap, CS35L41_MIXER_NGATE_CH2_CFG, + CS35L41_NG_ENABLE_MASK, + CS35L41_NG_ENABLE_MASK); + + if (cs35l41->pdata.ng_pcm_thld) { + regmap_update_bits(cs35l41->regmap, + CS35L41_MIXER_NGATE_CH1_CFG, + CS35L41_NG_THLD_MASK, + cs35l41->pdata.ng_pcm_thld); + regmap_update_bits(cs35l41->regmap, + CS35L41_MIXER_NGATE_CH2_CFG, + CS35L41_NG_THLD_MASK, + cs35l41->pdata.ng_pcm_thld); + } + + if (cs35l41->pdata.ng_delay) { + regmap_update_bits(cs35l41->regmap, + CS35L41_MIXER_NGATE_CH1_CFG, + CS35L41_NG_DELAY_MASK, + cs35l41->pdata.ng_delay + << CS35L41_NG_DELAY_SHIFT); + regmap_update_bits(cs35l41->regmap, + CS35L41_MIXER_NGATE_CH2_CFG, + CS35L41_NG_DELAY_MASK, + cs35l41->pdata.ng_delay + << CS35L41_NG_DELAY_SHIFT); + } + } + + if (classh->classh_algo_enable) { + if (classh->classh_bst_override) + regmap_update_bits(cs35l41->regmap, + CS35L41_BSTCVRT_VCTRL2, + CS35L41_BST_CTL_SEL_MASK, + CS35L41_BST_CTL_SEL_REG); + if (classh->classh_bst_max_limit) + regmap_update_bits(cs35l41->regmap, + CS35L41_BSTCVRT_VCTRL2, + CS35L41_BST_LIM_MASK, + classh->classh_bst_max_limit + << CS35L41_BST_LIM_SHIFT); + if (classh->classh_mem_depth) + regmap_update_bits( + cs35l41->regmap, CS35L41_CLASSH_CFG, + CS35L41_CH_MEM_DEPTH_MASK, + classh->classh_mem_depth + << CS35L41_CH_MEM_DEPTH_SHIFT); + if (classh->classh_headroom) + regmap_update_bits( + cs35l41->regmap, CS35L41_CLASSH_CFG, + CS35L41_CH_HDRM_CTL_MASK, + classh->classh_headroom + << CS35L41_CH_HDRM_CTL_SHIFT); + if (classh->classh_release_rate) + regmap_update_bits( + cs35l41->regmap, CS35L41_CLASSH_CFG, + CS35L41_CH_REL_RATE_MASK, + classh->classh_release_rate + << CS35L41_CH_REL_RATE_SHIFT); + if (classh->classh_wk_fet_delay) + regmap_update_bits( + cs35l41->regmap, CS35L41_WKFET_CFG, + CS35L41_CH_WKFET_DLY_MASK, + classh->classh_wk_fet_delay + << CS35L41_CH_WKFET_DLY_SHIFT); + if (classh->classh_wk_fet_thld) + regmap_update_bits( + cs35l41->regmap, CS35L41_WKFET_CFG, + CS35L41_CH_WKFET_THLD_MASK, + classh->classh_wk_fet_thld + << CS35L41_CH_WKFET_THLD_SHIFT); + } + + wm_adsp2_codec_probe(&cs35l41->dsp, codec); + + snd_soc_dapm_ignore_suspend(dapm, "AMP Playback"); + snd_soc_dapm_ignore_suspend(dapm, "AMP Capture"); + snd_soc_dapm_ignore_suspend(dapm, "Main AMP"); + snd_soc_dapm_ignore_suspend(dapm, "SPK"); + snd_soc_dapm_ignore_suspend(dapm, "VP"); + snd_soc_dapm_ignore_suspend(dapm, "VBST"); + snd_soc_dapm_ignore_suspend(dapm, "ISENSE"); + snd_soc_dapm_ignore_suspend(dapm, "VSENSE"); + snd_soc_dapm_ignore_suspend(dapm, "TEMP"); + snd_soc_dapm_ignore_suspend(dapm, "DSP1 Preloader"); + snd_soc_dapm_ignore_suspend(dapm, "DSP1 Preload"); + + return 0; +} + +static int cs35l41_irq_gpio_config(struct cs35l41_private *cs35l41) +{ + struct irq_cfg *irq_gpio_cfg1 = &cs35l41->pdata.irq_config1; + struct irq_cfg *irq_gpio_cfg2 = &cs35l41->pdata.irq_config2; + int irq_pol = IRQF_TRIGGER_NONE; + + if (irq_gpio_cfg1->is_present) { + if (irq_gpio_cfg1->irq_pol_inv) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, + CS35L41_GPIO_POL_MASK, + CS35L41_GPIO_POL_MASK); + if (irq_gpio_cfg1->irq_out_en) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, + CS35L41_GPIO_DIR_MASK, 0); + if (irq_gpio_cfg1->irq_src_sel) + regmap_update_bits(cs35l41->regmap, + CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO1_CTRL_MASK, + irq_gpio_cfg1->irq_src_sel + << CS35L41_GPIO1_CTRL_SHIFT); + } + + if (irq_gpio_cfg2->is_present) { + if (irq_gpio_cfg2->irq_pol_inv) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, + CS35L41_GPIO_POL_MASK, + CS35L41_GPIO_POL_MASK); + if (irq_gpio_cfg2->irq_out_en) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, + CS35L41_GPIO_DIR_MASK, 0); + if (irq_gpio_cfg2->irq_src_sel) + regmap_update_bits(cs35l41->regmap, + CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO2_CTRL_MASK, + irq_gpio_cfg2->irq_src_sel + << CS35L41_GPIO2_CTRL_SHIFT); + } + + if (irq_gpio_cfg2->irq_src_sel == + (CS35L41_GPIO_CTRL_ACTV_LO | CS35L41_VALID_PDATA)) + irq_pol = IRQF_TRIGGER_LOW; + else if (irq_gpio_cfg2->irq_src_sel == + (CS35L41_GPIO_CTRL_ACTV_HI | CS35L41_VALID_PDATA)) + irq_pol = IRQF_TRIGGER_HIGH; + + return irq_pol; +} + +static int cs35l41_codec_remove(struct snd_soc_codec *codec) +{ + struct cs35l41_private *cs35l41 = snd_soc_codec_get_drvdata(codec); + + wm_adsp2_codec_remove(&cs35l41->dsp, codec); + return 0; +} + +static const struct snd_soc_dai_ops cs35l41_ops = { + .startup = cs35l41_pcm_startup, + .set_fmt = cs35l41_set_dai_fmt, + .hw_params = cs35l41_pcm_hw_params, + .set_sysclk = cs35l41_dai_set_sysclk, + .digital_mute = cs35l41_digital_mute, +}; + +static struct snd_soc_dai_driver cs35l41_dai[] = { + { + .name = "cs35l41-pcm", + .id = 0, + .playback = { + .stream_name = "AMP Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_KNOT, + .formats = CS35L41_RX_FORMATS, + }, + .capture = { + .stream_name = "AMP Capture", + .channels_min = 1, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_KNOT, + .formats = CS35L41_TX_FORMATS, + }, + .ops = &cs35l41_ops, + .symmetric_rates = 1, + }, +}; + +static struct snd_soc_codec_driver soc_codec_dev_cs35l41 = { + .probe = cs35l41_codec_probe, + .remove = cs35l41_codec_remove, + .component_driver = { + .dapm_widgets = cs35l41_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), + .dapm_routes = cs35l41_audio_map, + .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), + .controls = cs35l41_aud_controls, + .num_controls = ARRAY_SIZE(cs35l41_aud_controls), + }, + .set_sysclk = cs35l41_codec_set_sysclk, + .ignore_pmdown_time = false, + .idle_bias_off = true, +}; + +int spk_id_get(struct device_node *np) +{ + int id; + int state; + + state = spk_id_get_pin_3state(np); + if (state < 0) { + pr_err("%s: Can not get id pin state, %d\n", __func__, state); + return VENDOR_ID_NONE; + } + + switch (state) { + case PIN_PULL_DOWN: + id = VENDOR_ID_AAC; + break; + case PIN_PULL_UP: + id = VENDOR_ID_UNKNOWN; + break; + case PIN_FLOAT: + id = VENDOR_ID_GOER; + break; + default: + id = VENDOR_ID_UNKNOWN; + break; + } + return id; +} + +static int cs35l41_handle_of_data(struct device *dev, + struct cs35l41_platform_data *pdata) +{ + struct device_node *np = dev->of_node; + unsigned int val; + int ret; + struct device_node *sub_node; + struct classh_cfg *classh_config = &pdata->classh_config; + struct irq_cfg *irq_gpio1_config = &pdata->irq_config1; + struct irq_cfg *irq_gpio2_config = &pdata->irq_config2; + + if (!np) + return 0; + + pdata->right_channel = + of_property_read_bool(np, "cirrus,right-channel-amp"); + pdata->sclk_frc = of_property_read_bool(np, "cirrus,sclk-force-output"); + pdata->lrclk_frc = + of_property_read_bool(np, "cirrus,lrclk-force-output"); + pdata->amp_gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc"); + + if (of_property_read_u32(np, "cirrus,temp-warn_threshold", &val) >= 0) + pdata->temp_warn_thld = val | CS35L41_VALID_PDATA; + + ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val); + if (ret >= 0) { + if (val < 2550 || val > 11000) { + dev_err(dev, "Invalid Boost Voltage %u mV\n", val); + return -EINVAL; + } + pdata->bst_vctrl = ((val - 2550) / 100) + 1; + } + + ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val); + if (ret >= 0) + pdata->bst_ipk = val; + + ret = of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val); + if (ret >= 0) + pdata->bst_ind = val; + + ret = of_property_read_u32(np, "cirrus,boost-cap-microfarad", &val); + if (ret >= 0) + pdata->bst_cap = val; + + ret = of_property_read_u32(np, "cirrus,asp-sdout-hiz", &val); + if (ret >= 0) + pdata->dout_hiz = val; + else + pdata->dout_hiz = -1; + + pdata->ng_enable = + of_property_read_bool(np, "cirrus,noise-gate-enable"); + if (of_property_read_u32(np, "cirrus,noise-gate-threshold", &val) >= 0) + pdata->ng_pcm_thld = val | CS35L41_VALID_PDATA; + if (of_property_read_u32(np, "cirrus,noise-gate-delay", &val) >= 0) + pdata->ng_delay = val | CS35L41_VALID_PDATA; + + pdata->spk_id_gpio_p = of_parse_phandle(np, "cirrus,spk-id-pin", 0); + if (!pdata->spk_id_gpio_p) { + dev_err(dev, "property %s not detected in node %s", + "cirrus,spk-id-pin", np->full_name); + pdata->mnSpkType = VENDOR_ID_NONE; + } else { + pdata->mnSpkType = spk_id_get(pdata->spk_id_gpio_p); + } + dev_info(dev, "spk is is %d", pdata->mnSpkType); + + sub_node = of_get_child_by_name(np, "cirrus,classh-internal-algo"); + classh_config->classh_algo_enable = sub_node ? true : false; + + if (classh_config->classh_algo_enable) { + classh_config->classh_bst_override = of_property_read_bool( + sub_node, "cirrus,classh-bst-overide"); + + ret = of_property_read_u32(sub_node, + "cirrus,classh-bst-max-limit", &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_bst_max_limit = val; + } + + ret = of_property_read_u32(sub_node, "cirrus,classh-mem-depth", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_mem_depth = val; + } + + ret = of_property_read_u32(sub_node, + "cirrus,classh-release-rate", &val); + if (ret >= 0) + classh_config->classh_release_rate = val; + + ret = of_property_read_u32(sub_node, "cirrus,classh-headroom", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_headroom = val; + } + + ret = of_property_read_u32(sub_node, + "cirrus,classh-wk-fet-delay", &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_wk_fet_delay = val; + } + + ret = of_property_read_u32(sub_node, + "cirrus,classh-wk-fet-thld", &val); + if (ret >= 0) + classh_config->classh_wk_fet_thld = val; + } + of_node_put(sub_node); + + /* GPIO1 Pin Config */ + sub_node = of_get_child_by_name(np, "cirrus,gpio-config1"); + irq_gpio1_config->is_present = sub_node ? true : false; + if (irq_gpio1_config->is_present) { + irq_gpio1_config->irq_pol_inv = of_property_read_bool( + sub_node, "cirrus,gpio-polarity-invert"); + irq_gpio1_config->irq_out_en = of_property_read_bool( + sub_node, "cirrus,gpio-output-enable"); + ret = of_property_read_u32(sub_node, "cirrus,gpio-src-select", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + irq_gpio1_config->irq_src_sel = val; + } + } + of_node_put(sub_node); + + /* GPIO2 Pin Config */ + sub_node = of_get_child_by_name(np, "cirrus,gpio-config2"); + irq_gpio2_config->is_present = sub_node ? true : false; + if (irq_gpio2_config->is_present) { + irq_gpio2_config->irq_pol_inv = of_property_read_bool( + sub_node, "cirrus,gpio-polarity-invert"); + irq_gpio2_config->irq_out_en = of_property_read_bool( + sub_node, "cirrus,gpio-output-enable"); + ret = of_property_read_u32(sub_node, "cirrus,gpio-src-select", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + irq_gpio2_config->irq_src_sel = val; + } + } + of_node_put(sub_node); + + return 0; +} + +static const struct reg_sequence cs35l41_reva0_errata_patch[] = { + { 0x00000040, 0x00005555 }, + { 0x00000040, 0x0000AAAA }, + { 0x00003854, 0x05180240 }, + { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, + { CS35L41_OTP_TRIM_30, 0x9091A1C8 }, + { 0x00003014, 0x0200EE0E }, + { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, + { 0x00000054, 0x00000004 }, + { CS35L41_IRQ1_DB3, 0x00000000 }, + { CS35L41_IRQ2_DB3, 0x00000000 }, + { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, + { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, + { CS35L41_ASP_CONTROL4, 0x00000000 }, + { 0x00000040, 0x0000CCCC }, + { 0x00000040, 0x00003333 }, +}; + +static const struct reg_sequence cs35l41_revb0_errata_patch[] = { + { 0x00000040, 0x00005555 }, + { 0x00000040, 0x0000AAAA }, + { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, + { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, + { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, + { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, + { CS35L41_ASP_CONTROL4, 0x00000000 }, + { 0x00000040, 0x0000CCCC }, + { 0x00000040, 0x00003333 }, +}; + +static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) +{ + struct wm_adsp *dsp; + int ret; + + dsp = &cs35l41->dsp; + dsp->part = "cs35l41"; + dsp->num = 1; + dsp->type = WMFW_HALO; + dsp->rev = 0; + dsp->dev = cs35l41->dev; + dsp->regmap = cs35l41->regmap; + + dsp->base = CS35L41_DSP1_CTRL_BASE; + dsp->base_sysinfo = CS35L41_DSP1_SYS_ID; + dsp->mem = cs35l41_dsp1_regions; + dsp->num_mems = ARRAY_SIZE(cs35l41_dsp1_regions); + dsp->unlock_all = true; + + dsp->n_rx_rates = CS35L41_DSP_N_RX_RATES; + dsp->n_tx_rates = CS35L41_DSP_N_TX_RATES; + ret = wm_halo_init(dsp); + cs35l41->halo_booted = false; + + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, + CS35L41_INPUT_SRC_VPMON); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, + CS35L41_INPUT_SRC_CLASSH); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, + CS35L41_INPUT_SRC_TEMPMON); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, + CS35L41_INPUT_SRC_RSVD); + + return ret; +} + +int cs35l41_probe(struct cs35l41_private *cs35l41, + struct cs35l41_platform_data *pdata) +{ + int ret; + u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; + int timeout = 100; + int irq_pol = 0; + + dev_info(cs35l41->dev, "cs35l41 proble\n"); + + /* Default to RESUME cmd */ + cs35l41->cspl_cmd = (unsigned int)CSPL_MBOX_CMD_RESUME; + + for (i = 0; i < ARRAY_SIZE(cs35l41_supplies); i++) + cs35l41->supplies[i].supply = cs35l41_supplies[i]; + + cs35l41->num_supplies = ARRAY_SIZE(cs35l41_supplies); + + ret = devm_regulator_bulk_get(cs35l41->dev, cs35l41->num_supplies, + cs35l41->supplies); + if (ret != 0) { + dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", + ret); + return ret; + } + + if (pdata) { + cs35l41->pdata = *pdata; + } else if (cs35l41->dev->of_node) { + ret = cs35l41_handle_of_data(cs35l41->dev, &cs35l41->pdata); + if (ret != 0) + return ret; + } else { + ret = -EINVAL; + goto err; + } + + ret = regulator_bulk_enable(cs35l41->num_supplies, cs35l41->supplies); + if (ret != 0) { + dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", + ret); + return ret; + } + + /* returning NULL can be an option if in stereo mode */ + cs35l41->reset_gpio = of_get_named_gpio(cs35l41->dev->of_node, + "cs,cdc-reset-gpio", 0); + + dev_err(cs35l41->dev, "Set GPIO %d as RESET pin\n", + cs35l41->reset_gpio); + if (!gpio_is_valid(cs35l41->reset_gpio)) { + dev_err(cs35l41->dev, "GPIO %d is invalid!\n", + cs35l41->reset_gpio); + } + + if (cs35l41->reset_gpio) { + dev_err(cs35l41->dev, "Reset cs35l41\n"); + /* satisfy minimum reset pulse width spec */ + usleep_range(2000, 2100); + + gpio_direction_output(cs35l41->reset_gpio, 0); + msleep(5); + gpio_direction_output(cs35l41->reset_gpio, 1); + msleep(2); + } + + usleep_range(2000, 2100); + + do { + if (timeout == 0) { + dev_err(cs35l41->dev, + "Timeout waiting for OTP_BOOT_DONE\n"); + ret = -EBUSY; + goto err; + } + usleep_range(1000, 1100); + regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS4, &int_status); + timeout--; + } while (!(int_status & CS35L41_OTP_BOOT_DONE)); + + regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); + if (int_status & CS35L41_OTP_BOOT_ERR) { + dev_err(cs35l41->dev, "OTP Boot error\n"); + ret = -EINVAL; + goto err; + } + + ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); + if (ret < 0) { + dev_err(cs35l41->dev, "Get Device ID failed\n"); + goto err; + } + + ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); + if (ret < 0) { + dev_err(cs35l41->dev, "Get Revision ID failed\n"); + goto err; + } + + mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; + + /* CS35L41 will have even MTLREVID + * CS35L41R will have odd MTLREVID + */ + chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; + if (regid != chipid_match) { + dev_err(cs35l41->dev, + "CS35L41 Device ID (%X). Expected ID %X\n", regid, + chipid_match); + ret = -ENODEV; + goto err; + } + + irq_pol = cs35l41_irq_gpio_config(cs35l41); + + init_completion(&cs35l41->global_pdn_done); + init_completion(&cs35l41->global_pup_done); + + init_completion(&cs35l41->mbox_cmd); + + ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, + cs35l41_irq, irq_pol | IRQF_ONESHOT, + "cs35l41", cs35l41); + + /* CS35L41 needs INT for PDN_DONE */ + if (ret != 0) { + dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", + cs35l41->irq); + //goto err; + } + + /* Set interrupt masks for critical errors */ + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, + CS35L41_INT1_MASK_DEFAULT); + + switch (reg_revid) { + case CS35L41_REVID_A0: + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_reva0_errata_patch, + ARRAY_SIZE(cs35l41_reva0_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply A0 errata patch %d\n", ret); + goto err; + } + break; + case CS35L41_REVID_B0: + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_revb0_errata_patch, + ARRAY_SIZE(cs35l41_revb0_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply B0 errata patch %d\n", ret); + goto err; + } + break; + } + + ret = cs35l41_otp_unpack(cs35l41); + if (ret < 0) { + dev_err(cs35l41->dev, "OTP Unpack failed\n"); + goto err; + } + + cs35l41_dsp_init(cs35l41); + + ret = snd_soc_register_codec(cs35l41->dev, &soc_codec_dev_cs35l41, + cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); + if (ret < 0) { + dev_err(cs35l41->dev, "%s: Register codec failed\n", __func__); + goto err; + } + + dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", + regid, reg_revid); + +err: + regulator_bulk_disable(cs35l41->num_supplies, cs35l41->supplies); + return ret; +} + +MODULE_DESCRIPTION("ASoC CS35L41 driver"); +MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l41/cs35l41.h b/techpack/audio/asoc/codecs/cs35l41/cs35l41.h new file mode 100644 index 000000000000..ce63c2b1daeb --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/cs35l41.h @@ -0,0 +1,766 @@ +/* + * cs35l41.h -- CS35L41 ALSA SoC audio driver + * + * Copyright 2018 Cirrus Logic, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: Brian Austin + * David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __CS35L41_H__ +#define __CS35L41_H__ + +#include + +#define CS35L41_FIRSTREG 0x00000000 +#define CS35L41_LASTREG 0x03804FE8 +#define CS35L41_DEVID 0x00000000 +#define CS35L41_REVID 0x00000004 +#define CS35L41_FABID 0x00000008 +#define CS35L41_RELID 0x0000000C +#define CS35L41_OTPID 0x00000010 +#define CS35L41_SFT_RESET 0x00000020 +#define CS35L41_TEST_KEY_CTL 0x00000040 +#define CS35L41_USER_KEY_CTL 0x00000044 +#define CS35L41_OTP_MEM0 0x00000400 +#define CS35L41_OTP_MEM31 0x0000047C +#define CS35L41_OTP_CTRL0 0x00000500 +#define CS35L41_OTP_CTRL1 0x00000504 +#define CS35L41_OTP_CTRL3 0x00000508 +#define CS35L41_OTP_CTRL4 0x0000050C +#define CS35L41_OTP_CTRL5 0x00000510 +#define CS35L41_OTP_CTRL6 0x00000514 +#define CS35L41_OTP_CTRL7 0x00000518 +#define CS35L41_OTP_CTRL8 0x0000051C +#define CS35L41_PWR_CTRL1 0x00002014 +#define CS35L41_PWR_CTRL2 0x00002018 +#define CS35L41_PWR_CTRL3 0x0000201C +#define CS35L41_CTRL_OVRRIDE 0x00002020 +#define CS35L41_AMP_OUT_MUTE 0x00002024 +#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034 +#define CS35L41_GPIO_PAD_CONTROL 0x0000242C +#define CS35L41_JTAG_CONTROL 0x00002438 +#define CS35L41_PLL_CLK_CTRL 0x00002C04 +#define CS35L41_DSP_CLK_CTRL 0x00002C08 +#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C +#define CS35L41_DATA_FS_SEL 0x00002C10 +#define CS35L41_MDSYNC_EN 0x00003400 +#define CS35L41_MDSYNC_TX_ID 0x00003408 +#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C +#define CS35L41_MDSYNC_DATA_TX 0x00003410 +#define CS35L41_MDSYNC_TX_STATUS 0x00003414 +#define CS35L41_MDSYNC_DATA_RX 0x0000341C +#define CS35L41_MDSYNC_RX_STATUS 0x00003420 +#define CS35L41_MDSYNC_ERR_STATUS 0x00003424 +#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528 +#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C +#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C +#define CS35L41_BSTCVRT_VCTRL1 0x00003800 +#define CS35L41_BSTCVRT_VCTRL2 0x00003804 +#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808 +#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C +#define CS35L41_BSTCVRT_COEFF 0x00003810 +#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814 +#define CS35L41_BSTCVRT_SW_FREQ 0x00003818 +#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C +#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820 +#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830 +#define CS35L41_VI_VOL_POL 0x00004000 +#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100 +#define CS35L41_DTEMP_WARN_THLD 0x00004220 +#define CS35L41_DTEMP_CFG 0x00004224 +#define CS35L41_DTEMP_EN 0x00004308 +#define CS35L41_VPVBST_FS_SEL 0x00004400 +#define CS35L41_SP_ENABLES 0x00004800 +#define CS35L41_SP_RATE_CTRL 0x00004804 +#define CS35L41_SP_FORMAT 0x00004808 +#define CS35L41_SP_HIZ_CTRL 0x0000480C +#define CS35L41_SP_FRAME_TX_SLOT 0x00004810 +#define CS35L41_SP_FRAME_RX_SLOT 0x00004820 +#define CS35L41_SP_TX_WL 0x00004830 +#define CS35L41_SP_RX_WL 0x00004840 +#define CS35L41_ASP_CONTROL4 0x00004854 +#define CS35L41_DAC_PCM1_SRC 0x00004C00 +#define CS35L41_ASP_TX1_SRC 0x00004C20 +#define CS35L41_ASP_TX2_SRC 0x00004C24 +#define CS35L41_ASP_TX3_SRC 0x00004C28 +#define CS35L41_ASP_TX4_SRC 0x00004C2C +#define CS35L41_DSP1_RX1_SRC 0x00004C40 +#define CS35L41_DSP1_RX2_SRC 0x00004C44 +#define CS35L41_DSP1_RX3_SRC 0x00004C48 +#define CS35L41_DSP1_RX4_SRC 0x00004C4C +#define CS35L41_DSP1_RX5_SRC 0x00004C50 +#define CS35L41_DSP1_RX6_SRC 0x00004C54 +#define CS35L41_DSP1_RX7_SRC 0x00004C58 +#define CS35L41_DSP1_RX8_SRC 0x00004C5C +#define CS35L41_NGATE1_SRC 0x00004C60 +#define CS35L41_NGATE2_SRC 0x00004C64 +#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000 +#define CS35L41_VPBR_CFG 0x00006404 +#define CS35L41_VBBR_CFG 0x00006408 +#define CS35L41_VPBR_STATUS 0x0000640C +#define CS35L41_VBBR_STATUS 0x00006410 +#define CS35L41_OVERTEMP_CFG 0x00006414 +#define CS35L41_AMP_ERR_VOL 0x00006418 +#define CS35L41_VOL_STATUS_TO_DSP 0x00006450 +#define CS35L41_CLASSH_CFG 0x00006800 +#define CS35L41_WKFET_CFG 0x00006804 +#define CS35L41_NG_CFG 0x00006808 +#define CS35L41_AMP_GAIN_CTRL 0x00006C04 +#define CS35L41_DAC_MSM_CFG 0x00007400 +#define CS35L41_IRQ1_CFG 0x00010000 +#define CS35L41_IRQ1_STATUS 0x00010004 +#define CS35L41_IRQ1_STATUS1 0x00010010 +#define CS35L41_IRQ1_STATUS2 0x00010014 +#define CS35L41_IRQ1_STATUS3 0x00010018 +#define CS35L41_IRQ1_STATUS4 0x0001001C +#define CS35L41_IRQ1_RAW_STATUS1 0x00010090 +#define CS35L41_IRQ1_RAW_STATUS2 0x00010094 +#define CS35L41_IRQ1_RAW_STATUS3 0x00010098 +#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C +#define CS35L41_IRQ1_MASK1 0x00010110 +#define CS35L41_IRQ1_MASK2 0x00010114 +#define CS35L41_IRQ1_MASK3 0x00010118 +#define CS35L41_IRQ1_MASK4 0x0001011C +#define CS35L41_IRQ1_FRC1 0x00010190 +#define CS35L41_IRQ1_FRC2 0x00010194 +#define CS35L41_IRQ1_FRC3 0x00010198 +#define CS35L41_IRQ1_FRC4 0x0001019C +#define CS35L41_IRQ1_EDGE1 0x00010210 +#define CS35L41_IRQ1_EDGE4 0x0001021C +#define CS35L41_IRQ1_POL1 0x00010290 +#define CS35L41_IRQ1_POL2 0x00010294 +#define CS35L41_IRQ1_POL3 0x00010298 +#define CS35L41_IRQ1_POL4 0x0001029C +#define CS35L41_IRQ1_DB3 0x00010318 +#define CS35L41_IRQ2_CFG 0x00010800 +#define CS35L41_IRQ2_STATUS 0x00010804 +#define CS35L41_IRQ2_STATUS1 0x00010810 +#define CS35L41_IRQ2_STATUS2 0x00010814 +#define CS35L41_IRQ2_STATUS3 0x00010818 +#define CS35L41_IRQ2_STATUS4 0x0001081C +#define CS35L41_IRQ2_RAW_STATUS1 0x00010890 +#define CS35L41_IRQ2_RAW_STATUS2 0x00010894 +#define CS35L41_IRQ2_RAW_STATUS3 0x00010898 +#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C +#define CS35L41_IRQ2_MASK1 0x00010910 +#define CS35L41_IRQ2_MASK2 0x00010914 +#define CS35L41_IRQ2_MASK3 0x00010918 +#define CS35L41_IRQ2_MASK4 0x0001091C +#define CS35L41_IRQ2_FRC1 0x00010990 +#define CS35L41_IRQ2_FRC2 0x00010994 +#define CS35L41_IRQ2_FRC3 0x00010998 +#define CS35L41_IRQ2_FRC4 0x0001099C +#define CS35L41_IRQ2_EDGE1 0x00010A10 +#define CS35L41_IRQ2_EDGE4 0x00010A1C +#define CS35L41_IRQ2_POL1 0x00010A90 +#define CS35L41_IRQ2_POL2 0x00010A94 +#define CS35L41_IRQ2_POL3 0x00010A98 +#define CS35L41_IRQ2_POL4 0x00010A9C +#define CS35L41_IRQ2_DB3 0x00010B18 +#define CS35L41_GPIO_STATUS1 0x00011000 +#define CS35L41_GPIO1_CTRL1 0x00011008 +#define CS35L41_GPIO2_CTRL1 0x0001100C +#define CS35L41_MIXER_NGATE_CFG 0x00012000 +#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004 +#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008 +#define CS35L41_DSP_MBOX_1 0x00013000 +#define CS35L41_DSP_MBOX_2 0x00013004 +#define CS35L41_DSP_MBOX_3 0x00013008 +#define CS35L41_DSP_MBOX_4 0x0001300C +#define CS35L41_DSP_MBOX_5 0x00013010 +#define CS35L41_DSP_MBOX_6 0x00013014 +#define CS35L41_DSP_MBOX_7 0x00013018 +#define CS35L41_DSP_MBOX_8 0x0001301C +#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020 +#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024 +#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028 +#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C +#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030 +#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034 +#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038 +#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C +#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040 +#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044 +#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048 +#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C +#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050 +#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054 +#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058 +#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C +#define CS35L41_CLOCK_DETECT_1 0x00014000 +#define CS35L41_TIMER1_CONTROL 0x00015000 +#define CS35L41_TIMER1_COUNT_PRESET 0x00015004 +#define CS35L41_TIMER1_START_STOP 0x0001500C +#define CS35L41_TIMER1_STATUS 0x00015010 +#define CS35L41_TIMER1_COUNT_READBACK 0x00015014 +#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018 +#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C +#define CS35L41_TIMER2_CONTROL 0x00015100 +#define CS35L41_TIMER2_COUNT_PRESET 0x00015104 +#define CS35L41_TIMER2_START_STOP 0x0001510C +#define CS35L41_TIMER2_STATUS 0x00015110 +#define CS35L41_TIMER2_COUNT_READBACK 0x00015114 +#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118 +#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C +#define CS35L41_DFT_JTAG_CONTROL 0x00016000 +#define CS35L41_DIE_STS1 0x00017040 +#define CS35L41_DIE_STS2 0x00017044 +#define CS35L41_TEMP_CAL1 0x00017048 +#define CS35L41_TEMP_CAL2 0x0001704C +#define CS35L41_DSP1_XMEM_PACK_0 0x02000000 +#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0 +#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000 +#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8 +#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800 +#define CS35L41_DSP1_SYS_ID 0x025E0000 +#define CS35L41_DSP1_SYS_VERSION 0x025E0004 +#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008 +#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C +#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010 +#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018 +#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020 +#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028 +#define CS35L41_DSP1_SYS_FEATURES 0x025E002C +#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030 +#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034 +#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038 +#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C +#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040 +#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000 +#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004 +#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008 +#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C +#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010 +#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014 +#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018 +#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C +#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020 +#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024 +#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028 +#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C +#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030 +#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034 +#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038 +#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040 +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044 +#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000 +#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4 +#define CS35L41_DSP1_CTRL_BASE 0x02B80000 +#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010 +#define CS35L41_DSP1_DEBUG 0x02B80040 +#define CS35L41_DSP1_TIMER_CTRL 0x02B80048 +#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050 +#define CS35L41_DSP1_RX1_RATE 0x02B80080 +#define CS35L41_DSP1_RX2_RATE 0x02B80088 +#define CS35L41_DSP1_RX3_RATE 0x02B80090 +#define CS35L41_DSP1_RX4_RATE 0x02B80098 +#define CS35L41_DSP1_RX5_RATE 0x02B800A0 +#define CS35L41_DSP1_RX6_RATE 0x02B800A8 +#define CS35L41_DSP1_RX7_RATE 0x02B800B0 +#define CS35L41_DSP1_RX8_RATE 0x02B800B8 +#define CS35L41_DSP1_TX1_RATE 0x02B80280 +#define CS35L41_DSP1_TX2_RATE 0x02B80288 +#define CS35L41_DSP1_TX3_RATE 0x02B80290 +#define CS35L41_DSP1_TX4_RATE 0x02B80298 +#define CS35L41_DSP1_TX5_RATE 0x02B802A0 +#define CS35L41_DSP1_TX6_RATE 0x02B802A8 +#define CS35L41_DSP1_TX7_RATE 0x02B802B0 +#define CS35L41_DSP1_TX8_RATE 0x02B802B8 +#define CS35L41_DSP1_NMI_CTRL1 0x02B80480 +#define CS35L41_DSP1_NMI_CTRL2 0x02B80488 +#define CS35L41_DSP1_NMI_CTRL3 0x02B80490 +#define CS35L41_DSP1_NMI_CTRL4 0x02B80498 +#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0 +#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8 +#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0 +#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8 +#define CS35L41_DSP1_RESUME_CTRL 0x02B80500 +#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508 +#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510 +#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518 +#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520 +#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528 +#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530 +#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538 +#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540 +#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548 +#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550 +#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558 +#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560 +#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568 +#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570 +#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578 +#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580 +#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588 +#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590 +#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598 +#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0 +#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8 +#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0 +#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8 +#define CS35L41_DSP1_SCRATCH1 0x02B805C0 +#define CS35L41_DSP1_SCRATCH2 0x02B805C8 +#define CS35L41_DSP1_SCRATCH3 0x02B805D0 +#define CS35L41_DSP1_SCRATCH4 0x02B805D8 +#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000 +#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008 +#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000 +#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008 +#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010 +#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018 +#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020 +#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078 +#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0 +#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8 +#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0 +#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8 +#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0 +#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138 +#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180 +#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188 +#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C +#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190 +#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194 +#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198 +#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C +#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0 +#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4 +#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8 +#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC +#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0 +#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4 +#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8 +#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC +#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0 +#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4 +#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8 +#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC +#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0 +#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4 +#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8 +#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC +#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0 +#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4 +#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8 +#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC +#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0 +#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4 +#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8 +#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC +#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200 +#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204 +#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000 +#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004 +#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008 +#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C +#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014 +#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018 +#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C +#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020 +#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024 +#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C +#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030 +#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034 +#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038 +#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C +#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044 +#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048 +#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C +#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050 +#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054 +#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C +#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100 +#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104 +#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108 +#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C +#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110 +#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114 +#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140 +#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078 +#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200 +#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204 +#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208 +#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C +#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210 +#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214 +#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218 +#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C +#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220 +#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224 +#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228 +#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C +#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230 +#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234 +#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238 +#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C +#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400 +#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404 +#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408 +#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C +#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410 +#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414 +#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418 +#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C +#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420 +#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424 +#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428 +#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C +#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430 +#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434 +#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438 +#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C +#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678 +#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00 +#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08 +#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000 +#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004 +#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008 +#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010 +#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014 +#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018 +#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C +#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024 +#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C +#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030 +#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034 +#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038 +#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040 +#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000 +#define CS35L41_DSP1_WDT_STATUS 0x02BC7008 +#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000 +#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0 +#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000 +#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8 +#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000 +#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4 +#define CS35L41_DSP1_PMEM_0 0x03800000 +#define CS35L41_DSP1_PMEM_5114 0x03804FE8 + +/*test regs for emulation bringup*/ +#define CS35L41_PLL_OVR 0x00003018 +#define CS35L41_BST_TEST_DUTY 0x00003900 +#define CS35L41_DIGPWM_IOCTRL 0x0000706C + +/*registers populated by OTP*/ +#define CS35L41_OTP_TRIM_1 0x0000208c +#define CS35L41_OTP_TRIM_2 0x00002090 +#define CS35L41_OTP_TRIM_3 0x00003010 +#define CS35L41_OTP_TRIM_4 0x0000300C +#define CS35L41_OTP_TRIM_5 0x0000394C +#define CS35L41_OTP_TRIM_6 0x00003950 +#define CS35L41_OTP_TRIM_7 0x00003954 +#define CS35L41_OTP_TRIM_8 0x00003958 +#define CS35L41_OTP_TRIM_9 0x0000395C +#define CS35L41_OTP_TRIM_10 0x0000416C +#define CS35L41_OTP_TRIM_11 0x00004160 +#define CS35L41_OTP_TRIM_12 0x00004170 +#define CS35L41_OTP_TRIM_13 0x00004360 +#define CS35L41_OTP_TRIM_14 0x00004448 +#define CS35L41_OTP_TRIM_15 0x0000444C +#define CS35L41_OTP_TRIM_16 0x00006E30 +#define CS35L41_OTP_TRIM_17 0x00006E34 +#define CS35L41_OTP_TRIM_18 0x00006E38 +#define CS35L41_OTP_TRIM_19 0x00006E3C +#define CS35L41_OTP_TRIM_20 0x00006E40 +#define CS35L41_OTP_TRIM_21 0x00006E44 +#define CS35L41_OTP_TRIM_22 0x00006E48 +#define CS35L41_OTP_TRIM_23 0x00006E4C +#define CS35L41_OTP_TRIM_24 0x00006E50 +#define CS35L41_OTP_TRIM_25 0x00006E54 +#define CS35L41_OTP_TRIM_26 0x00006E58 +#define CS35L41_OTP_TRIM_27 0x00006E5C +#define CS35L41_OTP_TRIM_28 0x00006E60 +#define CS35L41_OTP_TRIM_29 0x00006E64 +#define CS35L41_OTP_TRIM_30 0x00007418 +#define CS35L41_OTP_TRIM_31 0x0000741C +#define CS35L41_OTP_TRIM_32 0x00007434 +#define CS35L41_OTP_TRIM_33 0x00007068 +#define CS35L41_OTP_TRIM_34 0x0000410C +#define CS35L41_OTP_TRIM_35 0x0000400C +#define CS35L41_OTP_TRIM_36 0x00002030 + +#define CS35L41_MAX_CACHE_REG 0x0000006B +#define CS35L41_OTP_SIZE_WORDS 32 +#define CS35L41_NUM_OTP_ELEM 100 +#define CS35L41_NUM_OTP_MAPS 3 + +#define CS35L41_VALID_PDATA 0x80000000 + +#define CS35L41_SCLK_MSTR_MASK 0x10 +#define CS35L41_SCLK_MSTR_SHIFT 4 +#define CS35L41_LRCLK_MSTR_MASK 0x01 +#define CS35L41_LRCLK_MSTR_SHIFT 0 +#define CS35L41_SCLK_INV_MASK 0x40 +#define CS35L41_SCLK_INV_SHIFT 6 +#define CS35L41_LRCLK_INV_MASK 0x04 +#define CS35L41_LRCLK_INV_SHIFT 2 +#define CS35L41_SCLK_FRC_MASK 0x20 +#define CS35L41_SCLK_FRC_SHIFT 5 +#define CS35L41_LRCLK_FRC_MASK 0x02 +#define CS35L41_LRCLK_FRC_SHIFT 1 + +#define CS35L41_AMP_GAIN_ZC_MASK 0x0400 +#define CS35L41_AMP_GAIN_ZC_SHIFT 10 + +#define CS35L41_BST_CTL_MASK 0xFF +#define CS35L41_BST_CTL_SEL_MASK 0x03 +#define CS35L41_BST_CTL_SEL_REG 0x00 +#define CS35L41_BST_CTL_SEL_CLASSH 0x01 +#define CS35L41_BST_IPK_MASK 0x7F +#define CS35L41_BST_IPK_SHIFT 0 +#define CS35L41_BST_LIM_MASK 0x4 +#define CS35L41_BST_LIM_SHIFT 2 +#define CS35L41_BST_K1_MASK 0x000000FF +#define CS35L41_BST_K1_SHIFT 0 +#define CS35L41_BST_K2_MASK 0x0000FF00 +#define CS35L41_BST_K2_SHIFT 8 +#define CS35L41_BST_SLOPE_MASK 0x0000FF00 +#define CS35L41_BST_SLOPE_SHIFT 8 +#define CS35L41_BST_LBST_VAL_MASK 0x00000003 +#define CS35L41_BST_LBST_VAL_SHIFT 0 + +#define CS35L41_TEMP_THLD_MASK 0x03 +#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF +#define CS35L41_PDM_MODE_MASK 0x01 +#define CS35L41_PDM_MODE_SHIFT 0 + +#define CS35L41_CH_MEM_DEPTH_MASK 0x07 +#define CS35L41_CH_MEM_DEPTH_SHIFT 0 +#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000 +#define CS35L41_CH_HDRM_CTL_SHIFT 16 +#define CS35L41_CH_REL_RATE_MASK 0xFF00 +#define CS35L41_CH_REL_RATE_SHIFT 8 +#define CS35L41_CH_WKFET_DLY_MASK 0x001C +#define CS35L41_CH_WKFET_DLY_SHIFT 2 +#define CS35L41_CH_WKFET_THLD_MASK 0x0F00 +#define CS35L41_CH_WKFET_THLD_SHIFT 8 + +#define CS35L41_NG_ENABLE_MASK 0x00010000 +#define CS35L41_NG_ENABLE_SHIFT 16 +#define CS35L41_NG_THLD_MASK 0x7 +#define CS35L41_NG_THLD_SHIFT 0 +#define CS35L41_NG_DELAY_MASK 0x0F00 +#define CS35L41_NG_DELAY_SHIFT 8 + +#define CS35L41_ASP_FMT_MASK 0x0700 +#define CS35L41_ASP_FMT_SHIFT 8 +#define CS35L41_ASP_DOUT_HIZ_MASK 0x03 +#define CS35L41_ASP_DOUT_HIZ_SHIFT 0 +#define CS35L41_ASP_WIDTH_16 0x10 +#define CS35L41_ASP_WIDTH_24 0x18 +#define CS35L41_ASP_WIDTH_32 0x20 +#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000 +#define CS35L41_ASP_WIDTH_TX_SHIFT 16 +#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000 +#define CS35L41_ASP_WIDTH_RX_SHIFT 24 +#define CS35L41_ASP_RX1_SLOT_MASK 0x3F +#define CS35L41_ASP_RX1_SLOT_SHIFT 0 +#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00 +#define CS35L41_ASP_RX2_SLOT_SHIFT 8 +#define CS35L41_ASP_RX_WL_MASK 0x3F +#define CS35L41_ASP_TX_WL_MASK 0x3F +#define CS35L41_ASP_RX_WL_SHIFT 0 +#define CS35L41_ASP_TX_WL_SHIFT 0 +#define CS35L41_ASP_SOURCE_MASK 0x7F + +#define CS35L41_INPUT_SRC_ASPRX1 0x08 +#define CS35L41_INPUT_SRC_ASPRX2 0x09 +#define CS35L41_INPUT_SRC_VMON 0x18 +#define CS35L41_INPUT_SRC_IMON 0x19 +#define CS35L41_INPUT_SRC_CLASSH 0x21 +#define CS35L41_INPUT_SRC_VPMON 0x28 +#define CS35L41_INPUT_SRC_VBSTMON 0x29 +#define CS35L41_INPUT_SRC_TEMPMON 0x3A +#define CS35L41_INPUT_SRC_RSVD 0x3B +#define CS35L41_INPUT_DSP_TX1 0x32 +#define CS35L41_INPUT_DSP_TX2 0x33 + +#define CS35L41_PLL_CLK_SEL_MASK 0x07 +#define CS35L41_PLL_CLK_SEL_SHIFT 0 +#define CS35L41_PLL_CLK_EN_MASK 0x10 +#define CS35L41_PLL_CLK_EN_SHIFT 4 +#define CS35L41_PLL_OPENLOOP_MASK 0x0800 +#define CS35L41_PLL_OPENLOOP_SHIFT 11 +#define CS35L41_PLLSRC_SCLK 0 +#define CS35L41_PLLSRC_LRCLK 1 +#define CS35L41_PLLSRC_SELF 3 +#define CS35L41_PLLSRC_PDMCLK 4 +#define CS35L41_PLLSRC_MCLK 5 +#define CS35L41_PLLSRC_SWIRE 7 +#define CS35L41_REFCLK_FREQ_MASK 0x7E0 +#define CS35L41_REFCLK_FREQ_SHIFT 5 + +#define CS35L41_GLOBAL_FS_MASK 0x1F +#define CS35L41_GLOBAL_FS_SHIFT 0 + +#define CS35L41_GLOBAL_EN_MASK 0x01 +#define CS35L41_GLOBAL_EN_SHIFT 0 +#define CS35L41_BST_EN_MASK 0x0030 +#define CS35L41_BST_EN_SHIFT 4 +#define CS35L41_BST_EN_DEFAULT 0x2 + +#define CS35L41_PDN_DONE_MASK 0x00800000 +#define CS35L41_PDN_DONE_SHIFT 23 +#define CS35L41_PUP_DONE_MASK 0x01000000 +#define CS35L41_PUP_DONE_SHIFT 24 + +#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F +#define CS35L36_PUP_DONE_IRQ_MASK 0xBF + +#define CS35L41_AMP_SHORT_ERR 0x80000000 +#define CS35L41_BST_SHORT_ERR 0x0100 +#define CS35L41_TEMP_WARN 0x8000 +#define CS35L41_TEMP_ERR 0x00020000 +#define CS35L41_BST_OVP_ERR 0x40 +#define CS35L41_BST_DCM_UVP_ERR 0x80 +#define CS35L41_OTP_BOOT_DONE 0x02 +#define CS35L41_PLL_UNLOCK 0x10 +#define CS35L41_OTP_BOOT_ERR 0x80000000 + +#define CS35L41_AMP_SHORT_ERR_RLS 0x02 +#define CS35L41_BST_SHORT_ERR_RLS 0x04 +#define CS35L41_BST_OVP_ERR_RLS 0x08 +#define CS35L41_BST_UVP_ERR_RLS 0x10 +#define CS35L41_TEMP_WARN_ERR_RLS 0x20 +#define CS35L41_TEMP_ERR_RLS 0x40 + +#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F +#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF +#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF + +#define CS35L41_GPIO_DIR_MASK 0x80000000 +#define CS35L41_GPIO1_CTRL_MASK 0x00030000 +#define CS35L41_GPIO1_CTRL_SHIFT 16 +#define CS35L41_GPIO2_CTRL_MASK 0x07000000 +#define CS35L41_GPIO2_CTRL_SHIFT 24 +#define CS35L41_GPIO_CTRL_ACTV_LO 4 +#define CS35L41_GPIO_CTRL_ACTV_HI 5 +#define CS35L41_GPIO_POL_MASK 0x1000 +#define CS35L41_GPIO_POL_SHIFT 12 + +#define CS35L41_CHIP_ID 0x35a40 +#define CS35L41R_CHIP_ID 0x35b40 +#define CS35L41_MTLREVID_MASK 0x0F +#define CS35L41_REVID_A0 0xA0 +#define CS35L41_REVID_B0 0xB0 + +#define CS35L41_DSP_N_RX_RATES 8 +#define CS35L41_DSP_N_TX_RATES 8 +#define CS35L41_HALO_CORE_RESET 0x00000200 + +#define CS35L41_SPI_MAX_FREQ_OTP 4000000 + +#define CS35L41_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) +#define CS35L41_TX_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +bool cs35l41_readable_reg(struct device *dev, unsigned int reg); +bool cs35l41_precious_reg(struct device *dev, unsigned int reg); +bool cs35l41_volatile_reg(struct device *dev, unsigned int reg); + +struct cs35l41_otp_packed_element_t { + u32 reg; + u8 shift; + u8 size; +}; + +struct cs35l41_otp_map_element_t { + u32 id; + u32 num_elements; + const struct cs35l41_otp_packed_element_t *map; + u32 bit_offset; + u32 word_offset; +}; + +extern const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG]; +extern const struct cs35l41_otp_map_element_t + cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS]; + +#define CS35L41_REGSTRIDE 4 +#define CS35L41_MBOXWAIT 100 + +#define CS35L41_DSP_VIRT1_MBOX_SHIFT 20 +#define CS35L41_DSP_VIRT2_MBOX_SHIFT 21 +#define CS35L41_CSPL_MBOX_STS CS35L41_DSP_MBOX_2 +/* Firmware update following reg */ +#define CS35L41_CSPL_MBOX_CMD_FW CS35L41_DSP_VIRT2_MBOX_1 +#define CS35L41_CSPL_MBOX_CMD_FW_SHIFT CS35L41_DSP_VIRT2_MBOX_SHIFT +/* Driver update following reg */ +#define CS35L41_CSPL_MBOX_CMD_DRV CS35L41_DSP_VIRT1_MBOX_1 +#define CS35L41_CSPL_MBOX_CMD_DRV_SHIFT CS35L41_DSP_VIRT1_MBOX_SHIFT + +enum cs35l41_cspl_mboxstate { + CSPL_MBOX_STS_RUNNING = 0, + CSPL_MBOX_STS_PAUSED = 1, + CSPL_MBOX_STS_RDY_FOR_REINIT = 2, +}; + +enum cs35l41_cspl_mboxcmd { + CSPL_MBOX_CMD_NONE = 0, + CSPL_MBOX_CMD_PAUSE = 1, + CSPL_MBOX_CMD_RESUME = 2, + CSPL_MBOX_CMD_REINIT = 3, + CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, + CSPL_MBOX_CMD_UNKNOWN_CMD = -1, + CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, +}; + +#endif /*__CS35L41_H__*/ diff --git a/techpack/audio/asoc/codecs/cs35l41/cs35l41.txt b/techpack/audio/asoc/codecs/cs35l41/cs35l41.txt new file mode 100755 index 000000000000..9ce49ac9ac68 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/cs35l41.txt @@ -0,0 +1,184 @@ +CS35L41 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l41" + "cirrus,cs35l40" + + - reg : the SPI chip select line for the device + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + +Optional properties: + - cirrus,sclk-force-output : Audio serial port SCLK force + output control. Forces the SCLK to continue to drive even + if no ASP_TXn channels are enabled. + + - cirrus,lrclk-force-output : Audio serial port LRCLK force + output control. Forces the LRCLK to continue to drive even + if no ASP_TXn channels are enabled. + + - cirrus,right-channel-amp : Boolean to determine which channel + the amplifier is to receive the audio data on. If present the + amplifier receives data on the right channel of I2S data. + If not present the amplifier receives data on the left + channel of I2S data + + - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the + boost converter's output voltage in mV. The range is from 2550 mV to + 11000 mV with increments of 50 mV. + (Default) VP + + Boost hardware configuration: + + These three properties should be used together to specify the external + component configuration of the part. See section 4.3.6 of the datasheet + for details regarding how these values are used to configure the + digital boost converter's control loop. + + - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. + Configures the peak current by monitoring the current through the boost FET. + Range starts at 1600 mA and goes to a maximum of 4500 mA with increments + of 50 mA. + (Default) 4.50 Amps + + - cirrus,boost-ind-nanohenry : Boost inductor value, expressed in nH. Valid + values include 1000, 1200, 1500 and 2200. + + - cirrus,boost-cap-microfarad : Total equivalent boost capacitance on the VBST + and VAMP pins, derated at 11 volts DC. The value must be rounded to the + nearest integer and expressed in uF. + + - cirrus,amp-gain-zc : Boolean to determine whether to use the amplifier + gain-change zero-crossing feature. If the feature is enabled, any + user-controlled amplifier gain change will occur on a zero-crossing point. + (Default) Disabled + + - cirrus,temp-warn-threshold : Amplifier overtemperature warning threshold. + Configures the threshold at which the overtemperature warning condition occurs. + When the threshold is met, the ovetemperature warning attenuation is applied + and the TEMP_WARN_EINT interrupt status bit is set. + If TEMP_WARN_MASK = 0, INTb is asserted. + + 0 = 105C + 1 = 115C + 2 = 125C (Default) + 3 = 135C + + - cirrus,noise-gate-enable : DSP Noise Gate feature. If present, noise + gate feature will be enabled. + + - cirrus,noise-gate-threshold : Threshold of audio signal input which the + noise gate considers the input audio to be at a low enough level to be + valid to enter a noise gating state of operation. + + 0 = -66 dBFS + 1 = -72 dBFS + 2 = -78 dBFS + 3 = -84 dBFS (default) + 4 = -90 dBFS + 5 = -96 dBFS + 6 = -102 dBFS + 7 = -108 dBFS + + - cirrus,noise-gate-delay : Time that the incoming audio signal must be + below the noise gate threshold prior to entering a noise gated state + + 0 = 5 ms + 1 = 10 ms + 2 = 25 ms + 3 = 50 ms (default) + 4 = 100 ms + 5 = 250 ms + 6 = 500 ms + 7 = 1 s + 8 = 5 s + 9 = 10 s + 10 = 20 s + 11 = 30 s + 12 = 40 s + 13 = 50 s + 14 = 60 s + 15 = 120 s + +Optional H/G Algorithm sub-node: + + The cs35l41 node can have a single "cirrus,classh-internal-algo" sub-node + that will disable automatic control of the internal H/G Algorithm. + + It is strongly recommended that the Datasheet be referenced when adjusting + or using these Class H Algorithm controls over the internal Algorithm. + Serious damage can occur to the Device and surrounding components. + + - cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm + See Section 4.4 Internal Class H Algorithm in the Datasheet. + If not used, the device manages the ClassH Algorithm internally. + +Optional properties for the "cirrus,classh-internal-algo" Sub-node + + Section 7.9 Boost Control + - cirrus,classh-bst-overide : Boolean + - cirrus,classh-bst-max-limit + + Section 7.17 Class H, Weak-FET Control + - cirrus,classh-headroom + - cirrus,classh-release-rate + - cirrus,classh-mem-depth + - cirrus,classh-wk-fet-delay + - cirrus,classh-wk-fet-thld + + +Optional GPIO1 sub-node: + +The cs35l41 node can have an single "cirrus,gpio-config1" sub-node for +configuring the GPIO1 pin. + +- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO1 +level is inverted. If this property is not present the level is not inverted. + +- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO1 pin +is configured as an output. If this property is not present the +pin will be configured as an input. + +- cirrus,gpio-src-select : Configures the function of the GPIO1 pin. +Note that the options are different from the GPIO2 pin. + +0 = High Impedance (Default) +1 = GPIO +2 = Sync +3 = MCLK input + + +Optional GPIO2 sub-node: + +The cs35l41 node can have an single "cirrus,gpio-config2" sub-node for +configuring the GPIO1 pin. + +- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO2 +level is inverted. If this property is not present the level is not inverted. + +- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO2 pin +is configured as an output. If this property is not present the +pin will be configured as an input. + +- cirrus,gpio-src-select : Configures the function of the GPIO2 pin. +Note that the options are different from the GPIO1 pin. + +0 = High Impedance (Default) +1 = GPIO +2 = Open Drain INTB +3 = MCLK input +4 = Push-pull INTB (active low) +5 = Push-pull INT (active high) + + +Example: + +cs35l41: cs35l41@2 { + compatible = "cirrus,cs35l41"; + reg = <2>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; +}; diff --git a/techpack/audio/asoc/codecs/cs35l41/wm_adsp.c b/techpack/audio/asoc/codecs/cs35l41/wm_adsp.c new file mode 100644 index 000000000000..adc22ca13d92 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/wm_adsp.c @@ -0,0 +1,5106 @@ +/* + * wm_adsp.c -- Wolfson ADSP support + * + * Copyright 2012 Wolfson Microelectronics plc + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#define DEBUG +//#define WM_ADSP_DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" + +#define adsp_crit(_dsp, fmt, ...) \ + dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) +#define adsp_err(_dsp, fmt, ...) \ + dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) +#define adsp_warn(_dsp, fmt, ...) \ + dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) +#define adsp_info(_dsp, fmt, ...) \ + dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) +#define adsp_dbg(_dsp, fmt, ...) \ + dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) + +#define MAXBULK 4 /* Max byte I2C bulk limit */ + +#define ADSP1_CONTROL_1 0x00 +#define ADSP1_CONTROL_2 0x02 +#define ADSP1_CONTROL_3 0x03 +#define ADSP1_CONTROL_4 0x04 +#define ADSP1_CONTROL_5 0x06 +#define ADSP1_CONTROL_6 0x07 +#define ADSP1_CONTROL_7 0x08 +#define ADSP1_CONTROL_8 0x09 +#define ADSP1_CONTROL_9 0x0A +#define ADSP1_CONTROL_10 0x0B +#define ADSP1_CONTROL_11 0x0C +#define ADSP1_CONTROL_12 0x0D +#define ADSP1_CONTROL_13 0x0F +#define ADSP1_CONTROL_14 0x10 +#define ADSP1_CONTROL_15 0x11 +#define ADSP1_CONTROL_16 0x12 +#define ADSP1_CONTROL_17 0x13 +#define ADSP1_CONTROL_18 0x14 +#define ADSP1_CONTROL_19 0x16 +#define ADSP1_CONTROL_20 0x17 +#define ADSP1_CONTROL_21 0x18 +#define ADSP1_CONTROL_22 0x1A +#define ADSP1_CONTROL_23 0x1B +#define ADSP1_CONTROL_24 0x1C +#define ADSP1_CONTROL_25 0x1E +#define ADSP1_CONTROL_26 0x20 +#define ADSP1_CONTROL_27 0x21 +#define ADSP1_CONTROL_28 0x22 +#define ADSP1_CONTROL_29 0x23 +#define ADSP1_CONTROL_30 0x24 +#define ADSP1_CONTROL_31 0x26 + +/* + * ADSP1 Control 19 + */ +#define ADSP1_WDMA_BUFFER_LENGTH_MASK \ + 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ +#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ +#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ + +/* + * ADSP1 Control 30 + */ +#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ +#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ +#define ADSP1_START 0x0001 /* DSP1_START */ +#define ADSP1_START_MASK 0x0001 /* DSP1_START */ +#define ADSP1_START_SHIFT 0 /* DSP1_START */ +#define ADSP1_START_WIDTH 1 /* DSP1_START */ + +/* + * ADSP1 Control 31 + */ +#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2_CONTROL 0x0 +#define ADSP2_CLOCKING 0x1 +#define ADSP2V2_CLOCKING 0x2 +#define ADSP2_STATUS1 0x4 +#define ADSP2_WDMA_CONFIG_1 0x30 +#define ADSP2_WDMA_CONFIG_2 0x31 +#define ADSP2V2_WDMA_CONFIG_2 0x32 +#define ADSP2_RDMA_CONFIG_1 0x34 + +#define ADSP2_SCRATCH0 0x40 +#define ADSP2_SCRATCH1 0x41 +#define ADSP2_SCRATCH2 0x42 +#define ADSP2_SCRATCH3 0x43 + +#define ADSP2V2_SCRATCH0_1 0x40 +#define ADSP2V2_SCRATCH2_3 0x42 + +/* + * ADSP2 Control + */ + +#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ +#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ +#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ +#define ADSP2_START 0x0001 /* DSP1_START */ +#define ADSP2_START_MASK 0x0001 /* DSP1_START */ +#define ADSP2_START_SHIFT 0 /* DSP1_START */ +#define ADSP2_START_WIDTH 1 /* DSP1_START */ + +/* + * ADSP2 clocking + */ +#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ +#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ +#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +/* + * ADSP2V2 clocking + */ +#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ +#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ +#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ + +/* + * ADSP2 Status 1 + */ +#define ADSP2_RAM_RDY 0x0001 +#define ADSP2_RAM_RDY_MASK 0x0001 +#define ADSP2_RAM_RDY_SHIFT 0 +#define ADSP2_RAM_RDY_WIDTH 1 + +/* + * ADSP2 Lock support + */ +#define ADSP2_LOCK_CODE_0 0x5555 +#define ADSP2_LOCK_CODE_1 0xAAAA + +#define ADSP2_WATCHDOG 0x0A +#define ADSP2_BUS_ERR_ADDR 0x52 +#define ADSP2_REGION_LOCK_STATUS 0x64 +#define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 +#define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 +#define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A +#define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C +#define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E +#define ADSP2_LOCK_REGION_CTRL 0x7A +#define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C + +#define ADSP2_REGION_LOCK_ERR_MASK 0x8000 +#define ADSP2_SLAVE_ERR_MASK 0x4000 +#define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 +#define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 +#define ADSP2_CTRL_ERR_EINT 0x0001 + +#define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF +#define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF +#define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 +#define ADSP2_PMEM_ERR_ADDR_SHIFT 16 +#define ADSP2_WDT_ENA_MASK 0xFFFFFFFD + +#define ADSP2_LOCK_REGION_SHIFT 16 + +#define ADSP_MAX_STD_CTRL_SIZE 512 + +#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100 +#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10 +#define WM_ADSP_ACKED_CTL_MIN_VALUE 0 +#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF + +/* + * Event control messages + */ +#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001 + +/* + * HALO system info + */ +#define HALO_SYS_INFO_XM_SRAM_SIZE 0x00010 +#define HALO_SYS_INFO_YM_SRAM_SIZE 0x00018 +#define HALO_SYS_INFO_XM_BANK_SIZE 0x00038 +#define HALO_SYS_INFO_YM_BANK_SIZE 0x0003c +#define HALO_AHBM_WINDOW_DEBUG_0 0x02040 +#define HALO_AHBM_WINDOW_DEBUG_1 0x02044 + +/* + * HALO core + */ +#define HALO_SAMPLE_RATE_RX1 0x00080 +#define HALO_SAMPLE_RATE_TX1 0x00280 +#define HALO_SCRATCH1 0x005c0 +#define HALO_CCM_CORE_CONTROL 0x41000 + +/* + * HALO Lock support + */ +#define HALO_MPU_UNLOCK_CODE_0 0x5555 +#define HALO_MPU_UNLOCK_CODE_1 0xaaaa + +/* + * HALO MPU banks + */ +#define HALO_MPU_XMEM_ACCESS_0 0x43000 +#define HALO_MPU_YMEM_ACCESS_0 0x43004 +#define HALO_MPU_WINDOW_ACCESS_0 0x43008 +#define HALO_MPU_XREG_ACCESS_0 0x4300C +#define HALO_MPU_YREG_ACCESS_0 0x43014 +#define HALO_MPU_XMEM_ACCESS_1 0x43018 +#define HALO_MPU_YMEM_ACCESS_1 0x4301C +#define HALO_MPU_WINDOW_ACCESS_1 0x43020 +#define HALO_MPU_XREG_ACCESS_1 0x43024 +#define HALO_MPU_YREG_ACCESS_1 0x4302C +#define HALO_MPU_XMEM_ACCESS_2 0x43030 +#define HALO_MPU_YMEM_ACCESS_2 0x43034 +#define HALO_MPU_WINDOW_ACCESS_2 0x43038 +#define HALO_MPU_XREG_ACCESS_2 0x4303C +#define HALO_MPU_YREG_ACCESS_2 0x43044 +#define HALO_MPU_XMEM_ACCESS_3 0x43048 +#define HALO_MPU_YMEM_ACCESS_3 0x4304C +#define HALO_MPU_WINDOW_ACCESS_3 0x43050 +#define HALO_MPU_XREG_ACCESS_3 0x43054 +#define HALO_MPU_YREG_ACCESS_3 0x4305C +#define HALO_MPU_XM_VIO_ADDR 0x43100 +#define HALO_MPU_XM_VIO_STATUS 0x43104 +#define HALO_MPU_YM_VIO_ADDR 0x43108 +#define HALO_MPU_YM_VIO_STATUS 0x4310C +#define HALO_MPU_PM_VIO_ADDR 0x43110 +#define HALO_MPU_PM_VIO_STATUS 0x43114 +#define HALO_MPU_LOCK_CONFIG 0x43140 + +/* + * HALO stream arb + */ +#define HALO_STREAM_ARB_MSTR0_CONFIG_0 0x45000 +#define HALO_STREAM_ARB_MSTR0_CONFIG_1 0x45004 +#define HALO_STREAM_ARB_MSTR0_CONFIG_2 0x45008 +#define HALO_STREAM_ARB_MSTR1_CONFIG_0 0x45010 +#define HALO_STREAM_ARB_MSTR1_CONFIG_1 0x45014 +#define HALO_STREAM_ARB_MSTR1_CONFIG_2 0x45018 +#define HALO_STREAM_ARB_MSTR2_CONFIG_0 0x45020 +#define HALO_STREAM_ARB_MSTR2_CONFIG_1 0x45024 +#define HALO_STREAM_ARB_MSTR2_CONFIG_2 0x45028 +#define HALO_STREAM_ARB_MSTR3_CONFIG_0 0x45030 +#define HALO_STREAM_ARB_MSTR3_CONFIG_1 0x45034 +#define HALO_STREAM_ARB_MSTR3_CONFIG_2 0x45038 +#define HALO_STREAM_ARB_MSTR4_CONFIG_0 0x45040 +#define HALO_STREAM_ARB_MSTR4_CONFIG_1 0x45044 +#define HALO_STREAM_ARB_MSTR4_CONFIG_2 0x45048 +#define HALO_STREAM_ARB_MSTR5_CONFIG_0 0x45050 +#define HALO_STREAM_ARB_MSTR5_CONFIG_1 0x45054 +#define HALO_STREAM_ARB_MSTR5_CONFIG_2 0x45058 + +#define HALO_STREAM_ARB_TX1_CONFIG_0 0x45200 +#define HALO_STREAM_ARB_TX1_CONFIG_1 0x45204 +#define HALO_STREAM_ARB_TX2_CONFIG_0 0x45208 +#define HALO_STREAM_ARB_TX2_CONFIG_1 0x4520C +#define HALO_STREAM_ARB_TX3_CONFIG_0 0x45210 +#define HALO_STREAM_ARB_TX3_CONFIG_1 0x45214 +#define HALO_STREAM_ARB_TX4_CONFIG_0 0x45218 +#define HALO_STREAM_ARB_TX4_CONFIG_1 0x4521C +#define HALO_STREAM_ARB_TX5_CONFIG_0 0x45220 +#define HALO_STREAM_ARB_TX5_CONFIG_1 0x45224 +#define HALO_STREAM_ARB_TX6_CONFIG_0 0x45228 +#define HALO_STREAM_ARB_TX6_CONFIG_1 0x4522C +#define HALO_STREAM_ARB_TX7_CONFIG_0 0x45230 +#define HALO_STREAM_ARB_TX7_CONFIG_1 0x45234 +#define HALO_STREAM_ARB_TX8_CONFIG_0 0x45238 +#define HALO_STREAM_ARB_TX8_CONFIG_1 0x4523C +#define HALO_STREAM_ARB_RX1_CONFIG_0 0x45400 +#define HALO_STREAM_ARB_RX1_CONFIG_1 0x45404 +#define HALO_STREAM_ARB_RX2_CONFIG_0 0x45408 +#define HALO_STREAM_ARB_RX2_CONFIG_1 0x4540C +#define HALO_STREAM_ARB_RX3_CONFIG_0 0x45410 +#define HALO_STREAM_ARB_RX3_CONFIG_1 0x45414 +#define HALO_STREAM_ARB_RX4_CONFIG_0 0x45418 +#define HALO_STREAM_ARB_RX4_CONFIG_1 0x4541C +#define HALO_STREAM_ARB_RX5_CONFIG_0 0x45420 +#define HALO_STREAM_ARB_RX5_CONFIG_1 0x45424 +#define HALO_STREAM_ARB_RX6_CONFIG_0 0x45428 +#define HALO_STREAM_ARB_RX6_CONFIG_1 0x4542C +#define HALO_STREAM_ARB_RX7_CONFIG_0 0x45430 +#define HALO_STREAM_ARB_RX7_CONFIG_1 0x45434 +#define HALO_STREAM_ARB_RX8_CONFIG_0 0x45438 +#define HALO_STREAM_ARB_RX8_CONFIG_1 0x4543C + +#define HALO_STREAM_ARB_IRQ0_CONFIG_0 0x45600 +#define HALO_STREAM_ARB_IRQ0_CONFIG_1 0x45604 +#define HALO_STREAM_ARB_IRQ0_CONFIG_2 0x45608 +#define HALO_STREAM_ARB_IRQ1_CONFIG_0 0x45610 +#define HALO_STREAM_ARB_IRQ1_CONFIG_1 0x45614 +#define HALO_STREAM_ARB_IRQ1_CONFIG_2 0x45618 +#define HALO_STREAM_ARB_IRQ2_CONFIG_0 0x45620 +#define HALO_STREAM_ARB_IRQ2_CONFIG_1 0x45624 +#define HALO_STREAM_ARB_IRQ2_CONFIG_2 0x45628 +#define HALO_STREAM_ARB_IRQ3_CONFIG_0 0x45630 +#define HALO_STREAM_ARB_IRQ3_CONFIG_1 0x45634 +#define HALO_STREAM_ARB_IRQ3_CONFIG_2 0x45638 +#define HALO_STREAM_ARB_IRQ4_CONFIG_0 0x45640 +#define HALO_STREAM_ARB_IRQ4_CONFIG_1 0x45644 +#define HALO_STREAM_ARB_IRQ4_CONFIG_2 0x45648 +#define HALO_STREAM_ARB_IRQ5_CONFIG_0 0x45650 +#define HALO_STREAM_ARB_IRQ5_CONFIG_1 0x45654 +#define HALO_STREAM_ARB_IRQ5_CONFIG_2 0x45658 +#define HALO_STREAM_ARB_IRQ6_CONFIG_0 0x45660 +#define HALO_STREAM_ARB_IRQ6_CONFIG_1 0x45664 +#define HALO_STREAM_ARB_IRQ6_CONFIG_2 0x45668 +#define HALO_STREAM_ARB_IRQ7_CONFIG_0 0x45670 +#define HALO_STREAM_ARB_IRQ7_CONFIG_1 0x45674 +#define HALO_STREAM_ARB_IRQ7_CONFIG_2 0x45678 + +#define HALO_INTP_CTL_NMI_CONTROL 0x46008 + +/* + * HALO_AHBM_WINDOW_DEBUG_1 + */ +#define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00 +#define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8 +#define HALO_AHBM_ADDR_ERR_MASK 0x00000080 +#define HALO_AHBM_LOCKED_ERR_MASK 0x00000040 +#define HALO_AHBM_SIZE_ERR_MASK 0x00000020 +#define HALO_AHBM_MODE_ERR_MASK 0x00000010 +#define HALO_AHBM_AHB_ERR_MASK 0x00000001 + +/* + * HALO_SAMPLE_RATE_[RX|TX]n + */ +#define HALO_DSP_RATE_SHIFT 0 +#define HALO_DSP_RATE_MASK 0x1f + +/* + * HALO_CCM_CORE_CONTROL + */ +#define HALO_CORE_EN 0x00000001 +#define HALO_CORE_EN_MASK 0x00000001 +#define HALO_CORE_EN_SHIFT 0 +#define HALO_CORE_EN_WIDTH 1 +#define HALO_CORE_RESET 0x00000200 + +/* + * HALO_MPU_?M_VIO_STATUS + */ +#define HALO_MPU_VIO_STS_MASK 0x007e0000 +#define HALO_MPU_VIO_STS_SHIFT 17 +#define HALO_MPU_VIO_ERR_MASK 0x00010000 +#define HALO_MPU_VIO_ERR_SHIFT 16 +#define HALO_MPU_VIO_ERR_WR_MASK 0x00008000 +#define HALO_MPU_VIO_ERR_WR_SHIFT 15 +#define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff +#define HALO_MPU_VIO_ERR_SRC_SHIFT 0 + +#define HALO_MPU_VIO_SRAM 0x01 +#define HALO_MPU_VIO_REG 0x02 +#define HALO_MPU_VIO_AHB 0x04 +#define HALO_MPU_VIO_EREG 0x08 +#define HALO_MPU_VIO_EXTERNAL_MEM 0x10 +#define HALO_MPU_VIO_NON_EXIST 0x20 + +/* + * HALO_STREAM_ARB_MSTRn_CONFIG_0 + */ +#define HALO_STREAM_ARB_MSTR_EN_MASK 0x1 + +/* + * HALO_STREAM_ARB_[TX|RX]n_CONFIG_0 + * HALO_STREAM_ARB_IRQn_CONFIG_0 + */ +#define HALO_STREAM_ARB_MSTR_SEL_DEFAULT 0xfc + +static const unsigned int halo_mpu_access[18] = { + HALO_MPU_WINDOW_ACCESS_0, HALO_MPU_XREG_ACCESS_0, + HALO_MPU_YREG_ACCESS_0, HALO_MPU_XMEM_ACCESS_1, + HALO_MPU_YMEM_ACCESS_1, HALO_MPU_WINDOW_ACCESS_1, + HALO_MPU_XREG_ACCESS_1, HALO_MPU_YREG_ACCESS_1, + HALO_MPU_XMEM_ACCESS_2, HALO_MPU_YMEM_ACCESS_2, + HALO_MPU_WINDOW_ACCESS_2, HALO_MPU_XREG_ACCESS_2, + HALO_MPU_YREG_ACCESS_2, HALO_MPU_XMEM_ACCESS_3, + HALO_MPU_YMEM_ACCESS_3, HALO_MPU_WINDOW_ACCESS_3, + HALO_MPU_XREG_ACCESS_3, HALO_MPU_YREG_ACCESS_3, +}; + +struct wm_adsp_buf { + struct list_head list; + void *buf; +}; + +static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len, + struct list_head *list) +{ + struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL); + + if (buf == NULL) + return NULL; + + buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA); + if (!buf->buf) { + kfree(buf); + return NULL; + } + memcpy(buf->buf, src, len); + + if (list) + list_add_tail(&buf->list, list); + + return buf; +} + +static void wm_adsp_buf_free(struct list_head *list) +{ + while (!list_empty(list)) { + struct wm_adsp_buf *buf = + list_first_entry(list, struct wm_adsp_buf, list); + list_del(&buf->list); + kfree(buf->buf); + kfree(buf); + } +} + +#define WM_ADSP_FW_MBC_VSS 0 +#define WM_ADSP_FW_HIFI 1 +#define WM_ADSP_FW_TX 2 +#define WM_ADSP_FW_TX_SPK 3 +#define WM_ADSP_FW_RX 4 +#define WM_ADSP_FW_RX_ANC 5 +#define WM_ADSP_FW_CTRL 6 +#define WM_ADSP_FW_ASR 7 +#define WM_ADSP_FW_TRACE 8 +#define WM_ADSP_FW_SPK_PROT 9 +#define WM_ADSP_FW_DIAG 10 +#define WM_ADSP_FW_CALIB 11 + +#define WM_ADSP_NUM_FW 12 + +#define AMBIENT_DEFAULT 30 +#define CAL_R_DEFAULT 8392 +#define CAL_STATUS_DEFAULT 1 + +static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = { + [WM_ADSP_FW_MBC_VSS] = "MBC/VSS", [WM_ADSP_FW_HIFI] = "MasterHiFi", + [WM_ADSP_FW_TX] = "Tx", [WM_ADSP_FW_TX_SPK] = "Tx Speaker", + [WM_ADSP_FW_RX] = "Rx", [WM_ADSP_FW_RX_ANC] = "Rx ANC", + [WM_ADSP_FW_CTRL] = "Voice Ctrl", [WM_ADSP_FW_ASR] = "ASR Assist", + [WM_ADSP_FW_TRACE] = "Dbg Trace", [WM_ADSP_FW_SPK_PROT] = "Protection", + [WM_ADSP_FW_DIAG] = "Diag", [WM_ADSP_FW_CALIB] = "Diag Z", +}; + +struct wm_adsp_system_config_xm_hdr { + __be32 sys_enable; + __be32 fw_id; + __be32 fw_rev; + __be32 boot_status; + __be32 watchdog; + __be32 dma_buffer_size; + __be32 rdma[6]; + __be32 wdma[8]; + __be32 build_job_name[3]; + __be32 build_job_number; +}; + +struct wm_adsp_alg_xm_struct { + __be32 magic; + __be32 smoothing; + __be32 threshold; + __be32 host_buf_ptr; + __be32 start_seq; + __be32 high_water_mark; + __be32 low_water_mark; + __be64 smoothed_power; +}; + +struct wm_adsp_buffer { + __be32 X_buf_base; /* XM base addr of first X area */ + __be32 X_buf_size; /* Size of 1st X area in words */ + __be32 X_buf_base2; /* XM base addr of 2nd X area */ + __be32 X_buf_brk; /* Total X size in words */ + __be32 Y_buf_base; /* YM base addr of Y area */ + __be32 wrap; /* Total size X and Y in words */ + __be32 high_water_mark; /* Point at which IRQ is asserted */ + __be32 irq_count; /* bits 1-31 count IRQ assertions */ + __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */ + __be32 next_write_index; /* word index of next write */ + __be32 next_read_index; /* word index of next read */ + __be32 error; /* error if any */ + __be32 oldest_block_index; /* word index of oldest surviving */ + __be32 requested_rewind; /* how many blocks rewind was done */ + __be32 reserved_space; /* internal */ + __be32 min_free; /* min free space since stream start */ + __be32 blocks_written[2]; /* total blocks written (64 bit) */ + __be32 words_written[2]; /* total words written (64 bit) */ +}; + +struct wm_adsp_compr; + +struct wm_adsp_compr_buf { + struct wm_adsp *dsp; + struct wm_adsp_compr *compr; + + struct wm_adsp_buffer_region *regions; + u32 host_buf_ptr; + + u32 error; + u32 irq_count; + int read_index; + int avail; +}; + +struct wm_adsp_compr { + struct wm_adsp *dsp; + struct wm_adsp_compr_buf *buf; + + struct snd_compr_stream *stream; + struct snd_compressed_buffer size; + + u32 *raw_buf; + unsigned int copied_total; + + unsigned int sample_rate; +}; + +#define WM_ADSP_DATA_WORD_SIZE 3 + +#define WM_ADSP_MIN_FRAGMENTS 1 +#define WM_ADSP_MAX_FRAGMENTS 256 +#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE) +#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE) + +#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7 + +#define HOST_BUFFER_FIELD(field) \ + (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32)) + +#define ALG_XM_FIELD(field) \ + (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32)) + +static int wm_adsp_buffer_init(struct wm_adsp *dsp); +static int wm_adsp_buffer_free(struct wm_adsp *dsp); + +struct wm_adsp_buffer_region { + unsigned int offset; + unsigned int cumulative_size; + unsigned int mem_type; + unsigned int base_addr; +}; + +struct wm_adsp_buffer_region_def { + unsigned int mem_type; + unsigned int base_offset; + unsigned int size_offset; +}; + +static const struct wm_adsp_buffer_region_def default_regions[] = { + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(X_buf_base), + .size_offset = HOST_BUFFER_FIELD(X_buf_size), + }, + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(X_buf_base2), + .size_offset = HOST_BUFFER_FIELD(X_buf_brk), + }, + { + .mem_type = WMFW_ADSP2_YM, + .base_offset = HOST_BUFFER_FIELD(Y_buf_base), + .size_offset = HOST_BUFFER_FIELD(wrap), + }, +}; + +struct wm_adsp_fw_caps { + u32 id; + struct snd_codec_desc desc; + int num_regions; + const struct wm_adsp_buffer_region_def *region_defs; +}; + +static const struct wm_adsp_fw_caps ctrl_caps[] = { + { + .id = SND_AUDIOCODEC_BESPOKE, + .desc = { + .max_ch = 1, + .sample_rates = { 16000 }, + .num_sample_rates = 1, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .num_regions = ARRAY_SIZE(default_regions), + .region_defs = default_regions, + }, +}; + +static const struct wm_adsp_fw_caps trace_caps[] = { + { + .id = SND_AUDIOCODEC_BESPOKE, + .desc = { + .max_ch = 8, + .sample_rates = { + 4000, 8000, 11025, 12000, 16000, 22050, + 24000, 32000, 44100, 48000, 64000, 88200, + 96000, 176400, 192000 + }, + .num_sample_rates = 15, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .num_regions = ARRAY_SIZE(default_regions), + .region_defs = default_regions, + }, +}; + +static const struct { + const char *file; + int compr_direction; + int num_caps; + const struct wm_adsp_fw_caps *caps; + bool voice_trigger; +} wm_adsp_fw[WM_ADSP_NUM_FW] = { + [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, + [WM_ADSP_FW_HIFI] = { .file = "hifi" }, + [WM_ADSP_FW_TX] = { .file = "tx" }, + [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" }, + [WM_ADSP_FW_RX] = { .file = "rx" }, + [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" }, + [WM_ADSP_FW_CTRL] = { + .file = "ctrl", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(ctrl_caps), + .caps = ctrl_caps, + .voice_trigger = true, + }, + [WM_ADSP_FW_ASR] = { .file = "asr" }, + [WM_ADSP_FW_TRACE] = { + .file = "trace", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(trace_caps), + .caps = trace_caps, + }, + [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" }, + [WM_ADSP_FW_DIAG] = { .file = "diag" }, + [WM_ADSP_FW_CALIB] = { .file = "diag-z" }, +}; + +struct wm_coeff_ctl_ops { + int (*xget)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*xput)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +}; + +struct wm_coeff_ctl { + const char *name; + const char *fw_name; + struct wm_adsp_alg_region alg_region; + struct wm_coeff_ctl_ops ops; + struct wm_adsp *dsp; + unsigned int enabled : 1; + struct list_head list; + void *cache; + unsigned int offset; + size_t len; + unsigned int set : 1; + struct soc_bytes_ext bytes_ext; + unsigned int flags; + unsigned int type; +}; + +static const char *wm_adsp_mem_region_name(unsigned int type) +{ + switch (type) { + case WMFW_ADSP1_PM: + return "PM"; + case WMFW_HALO_PM_PACKED: + return "PM_PACKED"; + case WMFW_ADSP1_DM: + return "DM"; + case WMFW_ADSP2_XM: + return "XM"; + case WMFW_HALO_XM_PACKED: + return "XM_PACKED"; + case WMFW_ADSP2_YM: + return "YM"; + case WMFW_HALO_YM_PACKED: + return "YM_PACKED"; + case WMFW_ADSP1_ZM: + return "ZM"; + default: + return NULL; + } +} +static int wm_halo_apply_calibration(struct snd_soc_dapm_widget *w); +static int wm_adsp_k_ctl_put(struct wm_adsp *dsp, const char *name, int value); +static int wm_adsp_k_ctl_get(struct wm_adsp *dsp, const char *name); + +#ifdef CONFIG_DEBUG_FS +static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + kfree(dsp->wmfw_file_name); + dsp->wmfw_file_name = tmp; +} + +static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + kfree(dsp->bin_file_name); + dsp->bin_file_name = tmp; +} + +static void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ + kfree(dsp->wmfw_file_name); + kfree(dsp->bin_file_name); + dsp->wmfw_file_name = NULL; + dsp->bin_file_name = NULL; +} + +static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->wmfw_file_name || !dsp->booted) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->wmfw_file_name, + strlen(dsp->wmfw_file_name)); + + mutex_unlock(&dsp->pwr_lock); + return ret; +} + +static ssize_t wm_adsp_debugfs_bin_read(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->bin_file_name || !dsp->booted) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->bin_file_name, + strlen(dsp->bin_file_name)); + + mutex_unlock(&dsp->pwr_lock); + return ret; +} + +static const struct { + const char *name; + const struct file_operations fops; +} wm_adsp_debugfs_fops[] = { + { + .name = "wmfw_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_wmfw_read, + }, + }, + { + .name = "bin_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_bin_read, + }, + }, +}; + +static void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_codec *codec) +{ + struct dentry *root = NULL; + char *root_name; + int i; + + if (!codec->component.debugfs_root) { + adsp_err(dsp, "No codec debugfs root\n"); + goto err; + } + + root_name = kmalloc(PAGE_SIZE, GFP_KERNEL); + if (!root_name) + goto err; + + snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num); + root = debugfs_create_dir(root_name, codec->component.debugfs_root); + kfree(root_name); + + if (!root) + goto err; + + if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted)) + goto err; + + if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running)) + goto err; + + if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id)) + goto err; + + if (!debugfs_create_x32("fw_version", S_IRUGO, root, + &dsp->fw_id_version)) + goto err; + + for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) { + if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name, S_IRUGO, + root, dsp, + &wm_adsp_debugfs_fops[i].fops)) + goto err; + } + + dsp->debugfs_root = root; + return; + +err: + debugfs_remove_recursive(root); + adsp_err(dsp, "Failed to create debugfs\n"); +} + +static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ + wm_adsp_debugfs_clear(dsp); + debugfs_remove_recursive(dsp->debugfs_root); +} +#else +static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_codec *codec) +{ +} + +static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ +} + +static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ +} +#endif + +static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw; + + return 0; +} + +static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw) + return 0; + + if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW) + return -EINVAL; + + mutex_lock(&dsp[e->shift_l].pwr_lock); + + if (dsp[e->shift_l].booted || dsp[e->shift_l].compr) + ret = -EBUSY; + else + dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0]; + + mutex_unlock(&dsp[e->shift_l].pwr_lock); + + return ret; +} + +static int wm_adsp_cal_z_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = dsp->cal_z; + + return 0; +} + +static int wm_adsp_cal_z_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + dsp->cal_z = ucontrol->value.enumerated.item[0]; + dsp->cal_chksum = dsp->cal_z + CAL_STATUS_DEFAULT; + + dev_info(codec->dev, "cal_z = %d\n", dsp->cal_z); + + return 0; +} + +static int wm_adsp_ambient_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = dsp->ambient; + + return 0; +} + +static int wm_adsp_ambient_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + dsp->ambient = ucontrol->value.enumerated.item[0]; + + dev_info(codec->dev, "ambient = %d\n", dsp->ambient); + + return 0; +} + +static int wm_adsp_cal_status_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = dsp->cal_status; + + return 0; +} + +static int wm_adsp_cal_status_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + dsp->cal_status = ucontrol->value.enumerated.item[0]; + + dev_info(codec->dev, "cal_status = %d\n", dsp->cal_status); + + return 0; +} + +static int wm_adsp_cal_chksum_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = dsp->cal_chksum; + + return 0; +} + +static int wm_adsp_cal_chksum_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + dsp->cal_chksum = ucontrol->value.enumerated.item[0]; + + dev_info(codec->dev, "cal_chksum = %d\n", dsp->cal_chksum); + + return 0; +} + +static int wm_adsp_block_bypass_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = dsp->block_bypass; + + return 0; +} + +static int wm_adsp_block_bypass_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + dsp->block_bypass = ucontrol->value.enumerated.item[0]; + + switch (dsp->block_bypass) { + case 0: + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_IN_ENH", + 0x00000000); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_EQ", + 0x00000000); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_ACTI", + 0x00000000); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_MBL", + 0x00000000); + break; + case 1: + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_IN_ENH", + 0x00400001); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_EQ", + 0x00400001); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_ACTI", + 0x00400001); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_MBL", + 0x00400001); + break; + default: + break; + } + + dev_info(codec->dev, "block_bypass = %d\n", dsp->block_bypass); + + return 0; +} + +static int wm_adsp_block_bypass_in_enh_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.enumerated.item[0] = dsp->block_bypass_in_enh; + + return 0; +} + +static int wm_adsp_block_bypass_in_enh_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + dsp->block_bypass_in_enh = ucontrol->value.enumerated.item[0]; + + switch (dsp->block_bypass_in_enh) { + case 0: + dev_info(codec->dev, + "block_bypass_in_enh = %d, put 0x00000000.\n", + dsp->block_bypass_in_enh); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_IN_ENH", + 0x00000000); + break; + case 1: + dev_info(codec->dev, + "block_bypass_in_enh = %d, put 0x00400001.\n", + dsp->block_bypass_in_enh); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd BYPASS_IN_ENH", + 0x00400001); + break; + default: + break; + } + + dev_info(codec->dev, "block_bypass_in_enh = %d\n", + dsp->block_bypass_in_enh); + + return 0; +} + +static const struct soc_enum wm_adsp_fw_enum[] = { + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), +}; +static const char *wm_adsp_block_bypass_text[2] = { "Off", "On" }; +static const struct soc_enum wm_adsp_block_bypass_enum[] = { + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_block_bypass_text), + wm_adsp_block_bypass_text), +}; +const struct snd_kcontrol_new wm_adsp_fw_controls[] = { + SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0], wm_adsp_fw_get, + wm_adsp_fw_put), + SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1], wm_adsp_fw_get, + wm_adsp_fw_put), + SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2], wm_adsp_fw_get, + wm_adsp_fw_put), + SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3], wm_adsp_fw_get, + wm_adsp_fw_put), + SOC_ENUM_EXT("DSP5 Firmware", wm_adsp_fw_enum[4], wm_adsp_fw_get, + wm_adsp_fw_put), + SOC_ENUM_EXT("DSP6 Firmware", wm_adsp_fw_enum[5], wm_adsp_fw_get, + wm_adsp_fw_put), + SOC_ENUM_EXT("DSP7 Firmware", wm_adsp_fw_enum[6], wm_adsp_fw_get, + wm_adsp_fw_put), +}; + +const struct snd_kcontrol_new wm_adsp_cal_controls[] = { + /* In Halo DSP, values are 24-bit */ + SOC_SINGLE_EXT("DSP Set CAL_Z", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_z_get, wm_adsp_cal_z_put), + SOC_SINGLE_EXT("DSP Set AMBIENT", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_ambient_get, wm_adsp_ambient_put), + SOC_SINGLE_EXT("DSP Set CAL_STATUS", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_status_get, wm_adsp_cal_status_put), + SOC_SINGLE_EXT("DSP Set CAL_CHKSUM", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_chksum_get, wm_adsp_cal_chksum_put), + SOC_ENUM_EXT("DSP Block Bypass", wm_adsp_block_bypass_enum[0], + wm_adsp_block_bypass_get, wm_adsp_block_bypass_put), + SOC_ENUM_EXT("DSP Block Bypass_IN_ENH", wm_adsp_block_bypass_enum[0], + wm_adsp_block_bypass_in_enh_get, + wm_adsp_block_bypass_in_enh_put), +}; +EXPORT_SYMBOL_GPL(wm_adsp_cal_controls); + +static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, + int type) +{ + int i; + + for (i = 0; i < dsp->num_mems; i++) + if (dsp->mem[i].type == type) + return &dsp->mem[i]; + + return NULL; +} + +static unsigned int wm_adsp_region_to_reg(struct wm_adsp *dsp, + struct wm_adsp_region const *mem, + unsigned int offset) +{ + if (WARN_ON(!mem)) + return offset; + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + switch (mem->type) { + case WMFW_ADSP1_PM: + return mem->base + (offset * 3); + case WMFW_ADSP1_DM: + return mem->base + (offset * 2); + case WMFW_ADSP2_XM: + return mem->base + (offset * 2); + case WMFW_ADSP2_YM: + return mem->base + (offset * 2); + case WMFW_ADSP1_ZM: + return mem->base + (offset * 2); + default: + WARN(1, "Unknown memory region type"); + return offset; + } + case WMFW_HALO: + switch (mem->type) { + case WMFW_ADSP2_XM: + return mem->base + (offset * 4); + case WMFW_ADSP2_YM: + return mem->base + (offset * 4); + case WMFW_HALO_XM_PACKED: + return (mem->base + (offset * 3)) & ~0x3; + case WMFW_HALO_YM_PACKED: + return (mem->base + (offset * 3)) & ~0x3; + case WMFW_HALO_PM_PACKED: + return mem->base + (offset * 5); + default: + WARN(1, "Unknown memory region type"); + return offset; + } + default: + WARN(1, "Unknown DSP type"); + return offset; + } +} +static int wm_adsp2_raw_read(size_t maxbulk, struct regmap *map, + unsigned int reg, void *val, size_t len) +{ + int ret; + size_t read_len = 0; + size_t toread_len; + + while ((len - read_len) > 0) { + toread_len = + (len - read_len) > maxbulk ? maxbulk : (len - read_len); + ret = regmap_raw_read(map, reg + read_len, val + read_len, + toread_len); + if (ret < 0) { + printk("%s failed, toread_len:%u reg base:%u reg:%u read_len:%u\n", + __func__, toread_len, reg, reg + read_len, + read_len); + return ret; + } + read_len += toread_len; + } + + return 0; +} + +static void wm_adsp2_show_fw_status(struct wm_adsp *dsp) +{ + u16 scratch[4]; + int ret; + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, + dsp->base + ADSP2_SCRATCH0, scratch, + sizeof(scratch)); + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); + return; + } + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + be16_to_cpu(scratch[0]), be16_to_cpu(scratch[1]), + be16_to_cpu(scratch[2]), be16_to_cpu(scratch[3])); +} + +static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) +{ + u32 scratch[2]; + int ret; + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, + dsp->base + ADSP2V2_SCRATCH0_1, scratch, + sizeof(scratch)); + + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); + return; + } + + scratch[0] = be32_to_cpu(scratch[0]); + scratch[1] = be32_to_cpu(scratch[1]); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + scratch[0] & 0xFFFF, scratch[0] >> 16, scratch[1] & 0xFFFF, + scratch[1] >> 16); +} + +static void wm_halo_show_fw_status(struct wm_adsp *dsp) +{ + u32 scratch[4]; + int ret; + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, dsp->base + HALO_SCRATCH1, + scratch, sizeof(scratch)); + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); + return; + } + + adsp_dbg(dsp, "FW SCRATCH 1:0x%x 2:0x%x 3:0x%x 4:0x%x\n", + be32_to_cpu(scratch[0]), be32_to_cpu(scratch[1]), + be32_to_cpu(scratch[2]), be32_to_cpu(scratch[3])); +} + +static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext) +{ + return container_of(ext, struct wm_coeff_ctl, bytes_ext); +} + +static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) +{ + const struct wm_adsp_alg_region *alg_region = &ctl->alg_region; + struct wm_adsp *dsp = ctl->dsp; + const struct wm_adsp_region *mem; + + mem = wm_adsp_find_region(dsp, alg_region->type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", alg_region->type); + return -EINVAL; + } + + *reg = wm_adsp_region_to_reg(dsp, mem, + ctl->alg_region.base + ctl->offset); + + return 0; +} + +static int wm_coeff_info(struct snd_kcontrol *kctl, + struct snd_ctl_elem_info *uinfo) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE; + uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE; + uinfo->value.integer.step = 1; + uinfo->count = 1; + break; + default: + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = ctl->len; + break; + } + + return 0; +} + +static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl, + unsigned int event_id) +{ + struct wm_adsp *dsp = ctl->dsp; + u32 val = cpu_to_be32(event_id); + unsigned int reg; + int i, ret; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", + event_id, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); + + ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); + return ret; + } + + /* + * Poll for ack, we initially poll at ~1ms intervals for firmwares + * that respond quickly, then go to ~10ms polls. A firmware is unlikely + * to ack instantly so we do the first 1ms delay before reading the + * control to avoid a pointless bus transaction + */ + for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) { + switch (i) { + case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1: + usleep_range(1000, 2000); + i++; + break; + default: + usleep_range(10000, 20000); + i += 10; + break; + } + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, reg, &val, + sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); + return ret; + } + + if (val == 0) { + adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); + return 0; + } + } + + adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", reg, + ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); + + return -ETIMEDOUT; +} + +static int wm_coeff_write_control(struct wm_coeff_ctl *ctl, const void *buf, + size_t len) +{ + struct wm_adsp *dsp = ctl->dsp; + void *scratch; + int ret; + unsigned int reg; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + ret = regmap_raw_write(dsp->regmap, reg, scratch, len); + if (ret) { + adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", len, reg, + ret); + kfree(scratch); + return ret; + } + adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); + + kfree(scratch); + + return 0; +} + +static int wm_coeff_put(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + ret = -EPERM; + else + memcpy(ctl->cache, p, ctl->len); + + ctl->set = 1; + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_control(ctl, p, ctl->len); + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_tlv_put(struct snd_kcontrol *kctl, + const unsigned int __user *bytes, unsigned int size) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (copy_from_user(ctl->cache, bytes, size)) { + ret = -EFAULT; + } else { + ctl->set = 1; + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_control(ctl, ctl->cache, size); + else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + ret = -EPERM; + } + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_put_acked(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + unsigned int val = ucontrol->value.integer.value[0]; + int ret; + + if (val == 0) + return 0; /* 0 means no event */ + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_acked_control(ctl, val); + else + ret = -EPERM; + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_read_control(struct wm_coeff_ctl *ctl, void *buf, + size_t len) +{ + struct wm_adsp *dsp = ctl->dsp; + void *scratch; + int ret; + unsigned int reg; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, reg, scratch, len); + if (ret) { + adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", len, + reg, ret); + kfree(scratch); + return ret; + } + adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); + + memcpy(buf, scratch, len); + kfree(scratch); + + return 0; +} + +static int wm_coeff_get(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, p, ctl->len); + else + ret = -EPERM; + } else { + if (!ctl->flags && ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + + memcpy(p, ctl->cache, ctl->len); + } + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_tlv_get(struct snd_kcontrol *kctl, + unsigned int __user *bytes, unsigned int size) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, ctl->cache, size); + else + ret = -EPERM; + } else { + if (!ctl->flags && ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, ctl->cache, size); + } + + if (!ret && copy_to_user(bytes, ctl->cache, size)) + ret = -EFAULT; + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* + * Although it's not useful to read an acked control, we must satisfy + * user-side assumptions that all controls are readable and that a + * write of the same value should be filtered out (it's valid to send + * the same event number again to the firmware). We therefore return 0, + * meaning "no event" so valid event numbers will always be a change + */ + ucontrol->value.integer.value[0] = 0; + + return 0; +} + +struct wmfw_ctl_work { + struct wm_adsp *dsp; + struct wm_coeff_ctl *ctl; + struct work_struct work; +}; + +static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len) +{ + unsigned int out, rd, wr, vol; + + if (len > ADSP_MAX_STD_CTRL_SIZE) { + rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ; + wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE; + vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; + + out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK; + } else { + rd = SNDRV_CTL_ELEM_ACCESS_READ; + wr = SNDRV_CTL_ELEM_ACCESS_WRITE; + vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; + + out = 0; + } + + if (in) { + if (in & WMFW_CTL_FLAG_READABLE) + out |= rd; + if (in & WMFW_CTL_FLAG_WRITEABLE) + out |= wr; + if (in & WMFW_CTL_FLAG_VOLATILE) + out |= vol; + } else { + out |= rd | wr | vol; + } + + return out; +} + +static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl) +{ + struct snd_kcontrol_new *kcontrol; + int ret; + + if (!ctl || !ctl->name) + return -EINVAL; + + kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); + if (!kcontrol) + return -ENOMEM; + + kcontrol->name = ctl->name; + kcontrol->info = wm_coeff_info; + kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; + kcontrol->tlv.c = snd_soc_bytes_tlv_callback; + kcontrol->private_value = (unsigned long)&ctl->bytes_ext; + kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len); + + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + kcontrol->get = wm_coeff_get_acked; + kcontrol->put = wm_coeff_put_acked; + break; + default: + kcontrol->get = wm_coeff_get; + kcontrol->put = wm_coeff_put; + + ctl->bytes_ext.max = ctl->len; + ctl->bytes_ext.get = wm_coeff_tlv_get; + ctl->bytes_ext.put = wm_coeff_tlv_put; + break; + } + + ret = snd_soc_add_codec_controls(dsp->codec, kcontrol, 1); + if (ret < 0) + goto err_kcontrol; + + kfree(kcontrol); + + return 0; + +err_kcontrol: + kfree(kcontrol); + return ret; +} + +static int wm_coeff_init_control_caches(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (!ctl->enabled || ctl->set) + continue; + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + continue; + + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + if (ret < 0) + return ret; + } + + return 0; +} + +static int wm_coeff_sync_controls(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (!ctl->enabled) + continue; + if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) { + ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static void wm_adsp_signal_event_controls(struct wm_adsp *dsp, + unsigned int event) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) + continue; + + if (!ctl->enabled) + continue; + + ret = wm_coeff_write_acked_control(ctl, event); + if (ret) + adsp_warn( + dsp, + "Failed to send 0x%x event to alg 0x%x (%d)\n", + event, ctl->alg_region.alg, ret); + } +} + +static void wm_adsp_ctl_work(struct work_struct *work) +{ + struct wmfw_ctl_work *ctl_work = + container_of(work, struct wmfw_ctl_work, work); + + wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl); + kfree(ctl_work); +} + +static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl) +{ + kfree(ctl->cache); + kfree(ctl->name); + kfree(ctl); +} + +static int wm_adsp_create_control(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region, + unsigned int offset, unsigned int len, + const char *subname, unsigned int subname_len, + unsigned int flags, unsigned int type) +{ + struct wm_coeff_ctl *ctl; + struct wmfw_ctl_work *ctl_work; + char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; + const char *region_name; + int ret; + + region_name = wm_adsp_mem_region_name(alg_region->type); + if (!region_name) { + adsp_err(dsp, "Unknown region type: %d\n", alg_region->type); + return -EINVAL; + } + + switch (dsp->fw_ver) { + case 0: + case 1: + snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x", + dsp->num, region_name, alg_region->alg); + break; + default: + ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, + "DSP%d%c %.12s %x", dsp->num, *region_name, + wm_adsp_fw_text[dsp->fw], alg_region->alg); + + /* Truncate the subname from the start if it is too long */ + if (subname) { + int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2; + int skip = 0; + + if (subname_len > avail) + skip = subname_len - avail; + + snprintf(name + ret, + SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s", + subname_len - skip, subname + skip); + } + break; + } + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (!strcmp(ctl->name, name)) { + if (!ctl->enabled) + ctl->enabled = 1; + return 0; + } + } + + ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); + if (!ctl) + return -ENOMEM; + ctl->fw_name = wm_adsp_fw_text[dsp->fw]; + ctl->alg_region = *alg_region; + ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL); + if (!ctl->name) { + ret = -ENOMEM; + goto err_ctl; + } + ctl->enabled = 1; + ctl->set = 0; + ctl->ops.xget = wm_coeff_get; + ctl->ops.xput = wm_coeff_put; + ctl->dsp = dsp; + + ctl->flags = flags; + ctl->type = type; + ctl->offset = offset; + ctl->len = len; + ctl->cache = kzalloc(ctl->len, GFP_KERNEL); + if (!ctl->cache) { + ret = -ENOMEM; + goto err_ctl_name; + } + + list_add(&ctl->list, &dsp->ctl_list); + + if (flags & WMFW_CTL_FLAG_SYS) + return 0; + + ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL); + if (!ctl_work) { + ret = -ENOMEM; + goto err_ctl_cache; + } + + ctl_work->dsp = dsp; + ctl_work->ctl = ctl; + INIT_WORK(&ctl_work->work, wm_adsp_ctl_work); + schedule_work(&ctl_work->work); + + return 0; + +err_ctl_cache: + kfree(ctl->cache); +err_ctl_name: + kfree(ctl->name); +err_ctl: + kfree(ctl); + + return ret; +} + +struct wm_coeff_parsed_alg { + int id; + const u8 *name; + int name_len; + int ncoeff; +}; + +struct wm_coeff_parsed_coeff { + int offset; + int mem_type; + const u8 *name; + int name_len; + int ctl_type; + int flags; + int len; +}; + +static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str) +{ + int length; + + switch (bytes) { + case 1: + length = **pos; + break; + case 2: + length = le16_to_cpu(*((__le16 *)*pos)); + break; + default: + return 0; + } + + if (str) + *str = *pos + bytes; + + *pos += ((length + bytes) + 3) & ~0x03; + + return length; +} + +static int wm_coeff_parse_int(int bytes, const u8 **pos) +{ + int val = 0; + + switch (bytes) { + case 2: + val = le16_to_cpu(*((__le16 *)*pos)); + break; + case 4: + val = le32_to_cpu(*((__le32 *)*pos)); + break; + default: + break; + } + + *pos += bytes; + + return val; +} + +static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_alg *blk) +{ + const struct wmfw_adsp_alg_data *raw; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_alg_data *)*data; + *data = raw->data; + + blk->id = le32_to_cpu(raw->id); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ncoeff = le32_to_cpu(raw->ncoeff); + break; + default: + blk->id = wm_coeff_parse_int(sizeof(raw->id), data); + blk->name_len = + wm_coeff_parse_string(sizeof(u8), data, &blk->name); + wm_coeff_parse_string(sizeof(u16), data, NULL); + blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data); + break; + } + + adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); + adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); +} + +static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_coeff *blk) +{ + const struct wmfw_adsp_coeff_data *raw; + const u8 *tmp; + int length; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_coeff_data *)*data; + *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size); + + blk->offset = le16_to_cpu(raw->hdr.offset); + blk->mem_type = le16_to_cpu(raw->hdr.type); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ctl_type = le16_to_cpu(raw->ctl_type); + blk->flags = le16_to_cpu(raw->flags); + blk->len = le32_to_cpu(raw->len); + break; + default: + tmp = *data; + blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp); + blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp); + length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp); + blk->name_len = + wm_coeff_parse_string(sizeof(u8), &tmp, &blk->name); + wm_coeff_parse_string(sizeof(u8), &tmp, NULL); + wm_coeff_parse_string(sizeof(u16), &tmp, NULL); + blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp); + blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp); + blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp); + + *data = *data + sizeof(raw->hdr) + length; + break; + } + + adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); + adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); + adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); + adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); + adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); +} + +static int +wm_adsp_check_coeff_flags(struct wm_adsp *dsp, + const struct wm_coeff_parsed_coeff *coeff_blk, + unsigned int f_required, unsigned int f_illegal) +{ + if ((coeff_blk->flags & f_illegal) || + ((coeff_blk->flags & f_required) != f_required)) { + adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", + coeff_blk->flags, coeff_blk->ctl_type); + return -EINVAL; + } + + return 0; +} + +static int wm_adsp_parse_coeff(struct wm_adsp *dsp, + const struct wmfw_region *region) +{ + struct wm_adsp_alg_region alg_region = {}; + struct wm_coeff_parsed_alg alg_blk; + struct wm_coeff_parsed_coeff coeff_blk; + const u8 *data = region->data; + int i, ret; + + wm_coeff_parse_alg(dsp, &data, &alg_blk); + for (i = 0; i < alg_blk.ncoeff; i++) { + wm_coeff_parse_coeff(dsp, &data, &coeff_blk); + + switch (coeff_blk.ctl_type) { + case SNDRV_CTL_ELEM_TYPE_BYTES: + break; + case WMFW_CTL_TYPE_ACKED: + if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) + continue; /* ignore */ + + ret = wm_adsp_check_coeff_flags( + dsp, &coeff_blk, + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + case WMFW_CTL_TYPE_HOSTEVENT: + ret = wm_adsp_check_coeff_flags( + dsp, &coeff_blk, + WMFW_CTL_FLAG_SYS | WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + default: + adsp_err(dsp, "Unknown control type: %d\n", + coeff_blk.ctl_type); + return -EINVAL; + } + + alg_region.type = coeff_blk.mem_type; + alg_region.alg = alg_blk.id; + + ret = wm_adsp_create_control(dsp, &alg_region, coeff_blk.offset, + coeff_blk.len, coeff_blk.name, + coeff_blk.name_len, + coeff_blk.flags, + coeff_blk.ctl_type); + if (ret < 0) + adsp_err(dsp, "Failed to create control: %.*s, %d\n", + coeff_blk.name_len, coeff_blk.name, ret); + } + + return 0; +} + +static int wm_adsp_load(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + const struct firmware *firmware; + struct regmap *regmap = dsp->regmap; + unsigned int pos = 0; + const struct wmfw_header *header; + const struct wmfw_adsp1_sizes *adsp1_sizes; + const struct wmfw_adsp2_sizes *adsp2_sizes; + const struct wmfw_footer *footer; + const struct wmfw_region *region; + const struct wm_adsp_region *mem; + const char *region_name; + char *file, *text = NULL; + struct wm_adsp_buf *buf; +#ifdef WM_ADSP_DEBUG + void *bufVerify; +#endif + unsigned int reg; + int regions = 0; + int ret, offset, type, sizes; +#ifdef WM_ADSP_DEBUG + size_t i; + bool verifyOk = true; + int tempA, tempB; + int *pTempA, *pTempB; + int max_failures = 666666; + int num_failures = 0; + int whileLoopCount = 0; +#endif + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num, + wm_adsp_fw[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + + ret = request_firmware(&firmware, file, dsp->dev); + if (ret != 0) { + adsp_err(dsp, "Failed to request '%s'\n", file); + goto out; + } + ret = -EINVAL; + + pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); + if (pos >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", file, + firmware->size); + goto out_fw; + } + + header = (void *)&firmware->data[0]; + + if (memcmp(&header->magic[0], "WMFW", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + switch (header->ver) { + case 0: + adsp_warn(dsp, "%s: Deprecated file format %d\n", file, + header->ver); + break; + case 1: + case 2: + break; + default: + adsp_err(dsp, "%s: unknown file format %d\n", file, + header->ver); + goto out_fw; + } + break; + case WMFW_HALO: + switch (header->ver) { + case 1: + case 2: + /* + * we are required to load these for testing purposes + * but this format is not allowed for production fw + */ + adsp_warn( + dsp, + "%s: Not a production firmware (deprecated file format %d)\n", + file, header->ver); + break; + case 3: + break; + default: + adsp_err(dsp, "%s: unknown file format %d\n", file, + header->ver); + goto out_fw; + } + } + + adsp_info(dsp, "Firmware version: %d\n", header->ver); + dsp->fw_ver = header->ver; + + if (header->core != dsp->type) { + adsp_err(dsp, "%s: invalid core %d != %d\n", file, header->core, + dsp->type); + goto out_fw; + } + + switch (dsp->type) { + case WMFW_ADSP1: + pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); + adsp1_sizes = (void *)&(header[1]); + footer = (void *)&(adsp1_sizes[1]); + sizes = sizeof(*adsp1_sizes); + + adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, + le32_to_cpu(adsp1_sizes->dm), + le32_to_cpu(adsp1_sizes->pm), + le32_to_cpu(adsp1_sizes->zm)); + break; + + case WMFW_HALO: + case WMFW_ADSP2: + pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer); + adsp2_sizes = (void *)&(header[1]); + footer = (void *)&(adsp2_sizes[1]); + sizes = sizeof(*adsp2_sizes); + + adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, + le32_to_cpu(adsp2_sizes->xm), + le32_to_cpu(adsp2_sizes->ym), + le32_to_cpu(adsp2_sizes->pm), + le32_to_cpu(adsp2_sizes->zm)); + break; + + default: + WARN(1, "Unknown DSP type"); + goto out_fw; + } + + if (le32_to_cpu(header->len) != + sizeof(*header) + sizes + sizeof(*footer)) { + adsp_err(dsp, "%s: unexpected header length %d\n", file, + le32_to_cpu(header->len)); + goto out_fw; + } + + adsp_dbg(dsp, "%s: timestamp %llu\n", file, + le64_to_cpu(footer->timestamp)); + + while (pos < firmware->size && pos - firmware->size > sizeof(*region)) { +#ifdef WM_ADSP_DEBUG + num_failures = 0; +#endif + region = (void *)&(firmware->data[pos]); + region_name = "Unknown"; + reg = 0; + text = NULL; + offset = le32_to_cpu(region->offset) & 0xffffff; + type = be32_to_cpu(region->type) & 0xff; + mem = wm_adsp_find_region(dsp, type); + + switch (type) { + case WMFW_NAME_TEXT: + region_name = "Firmware name"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); + break; + case WMFW_ALGORITHM_DATA: + region_name = "Algorithm"; + ret = wm_adsp_parse_coeff(dsp, region); + if (ret != 0) + goto out_fw; + break; + case WMFW_INFO_TEXT: + region_name = "Information"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); + break; + case WMFW_ABSOLUTE: + region_name = "Absolute"; + reg = offset; + break; + case WMFW_ADSP1_PM: + case WMFW_ADSP1_DM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_ADSP1_ZM: + case WMFW_HALO_PM_PACKED: + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + region_name = wm_adsp_mem_region_name(type); + reg = wm_adsp_region_to_reg(dsp, mem, offset); + break; + default: + adsp_warn(dsp, + "%s.%d: Unknown region type %x at %d(%x)\n", + file, regions, type, pos, pos); + break; + } + + adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, regions, + le32_to_cpu(region->len), offset, region_name); + + if ((pos + le32_to_cpu(region->len) + sizeof(*region)) > + firmware->size) { + adsp_err( + dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, regions, region_name, + le32_to_cpu(region->len), firmware->size); + ret = -EINVAL; + goto out_fw; + } + + if (text) { + memcpy(text, region->data, le32_to_cpu(region->len)); + adsp_info(dsp, "%s: %s\n", file, text); + kfree(text); + text = NULL; + } + + if (reg) { + buf = wm_adsp_buf_alloc(region->data, + le32_to_cpu(region->len), + &buf_list); + if (!buf) { + adsp_err(dsp, "Out of memory\n"); + ret = -ENOMEM; + goto out_fw; + } +#ifdef WM_ADSP_DEBUG + bufVerify = vmalloc(le32_to_cpu(region->len)); + if (!bufVerify) { + adsp_err( + dsp, + "Could not allocate memory for verification buffer\n"); + ret = -ENOMEM; + goto out_fw; + } +#endif + + ret = regmap_raw_write_async(regmap, reg, buf->buf, + le32_to_cpu(region->len)); + + if (ret != 0) { + adsp_err( + dsp, + "%s.%d: Failed to write %d bytes at %d in %s: %d\n", + file, regions, le32_to_cpu(region->len), + offset, region_name, ret); + goto out_fw; + } +#ifdef WM_ADSP_DEBUG + /* abb. 3/5/18 - DEBUG. Wait for this write to complete + Then we will read back the registers and verify contents */ + adsp_info(dsp, "%s: Waiting to complete async write\n", + __func__); + ret = regmap_async_complete(regmap); + if (ret != 0) { + adsp_err( + dsp, + "[1] Failed to complete async write: %d\n", + ret); + goto out_fw; + } + adsp_err(dsp, "%s: Async write completed\n", __func__); + + ret = wm_adsp2_raw_read(MAXBULK, regmap, reg, bufVerify, + le32_to_cpu(region->len)); + + adsp_err(dsp, "%s: Beginning Verification (loop %d)\n", + __func__, whileLoopCount); + adsp_err(dsp, "%s: Total loop length: %d\n", __func__, + le32_to_cpu(region->len) / 4); + pTempA = (int *)buf->buf; + pTempB = (int *)bufVerify; + for (i = 0; i < le32_to_cpu(region->len) / 4; i++) { + tempA = pTempA[i]; + tempB = pTempB[i]; + + if (tempA != tempB) { + adsp_err( + dsp, + "** Verify failed on reg 0x%x at i=%zu (wrote 0x%x vs read 0x%x)\n", + reg, i, tempA, tempB); + verifyOk = false; + num_failures++; + } + + if (num_failures >= max_failures) { + adsp_err( + dsp, + "** Too many failed register verifies (hit max of %d). Exiting\n", + max_failures); + break; + } + } + + vfree(bufVerify); +#endif + } + + pos += le32_to_cpu(region->len) + sizeof(*region); + regions++; +#ifdef WM_ADSP_DEBUG + whileLoopCount++; +#endif + } + + ret = regmap_async_complete(regmap); + if (ret != 0) { + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + goto out_fw; + } + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, + regions, pos - firmware->size); + + wm_adsp_debugfs_save_wmfwname(dsp, file); + +out_fw: + regmap_async_complete(regmap); + wm_adsp_buf_free(&buf_list); + release_firmware(firmware); + kfree(text); +out: + kfree(file); +#ifdef WM_ADSP_DEBUG + adsp_err(dsp, "wm_adsp_load- with verifyOk = %d and ret = %d", verifyOk, + ret); +#endif + return ret; +} + +static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region) +{ + struct wm_coeff_ctl *ctl; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] && + alg_region->alg == ctl->alg_region.alg && + alg_region->type == ctl->alg_region.type) { + ctl->alg_region.base = alg_region->base; + } + } +} + +static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs, + unsigned int pos, unsigned int len) +{ + void *alg; + int ret; + __be32 val; + + if (n_algs == 0) { + adsp_err(dsp, "No algorithms\n"); + return ERR_PTR(-EINVAL); + } + + if (n_algs > 1024) { + adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); + return ERR_PTR(-EINVAL); + } + + /* Read the terminator first to validate the length */ + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, pos + len, &val, + sizeof(val)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list end: %d\n", ret); + return ERR_PTR(ret); + } + + if (be32_to_cpu(val) != 0xbedead) + adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", + pos + len, be32_to_cpu(val)); + + alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA); + if (!alg) + return ERR_PTR(-ENOMEM); + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, pos, alg, len * 2); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list: %d\n", ret); + kfree(alg); + return ERR_PTR(ret); + } + + return alg; +} + +static struct wm_adsp_alg_region * +wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id) +{ + struct wm_adsp_alg_region *alg_region; + + list_for_each_entry (alg_region, &dsp->alg_regions, list) { + if (id == alg_region->alg && type == alg_region->type) + return alg_region; + } + + return NULL; +} + +static struct wm_adsp_alg_region * +wm_adsp_create_region(struct wm_adsp *dsp, int type, __be32 id, __be32 base) +{ + struct wm_adsp_alg_region *alg_region; + + alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL); + if (!alg_region) + return ERR_PTR(-ENOMEM); + + alg_region->type = type; + alg_region->alg = be32_to_cpu(id); + alg_region->base = be32_to_cpu(base); + + list_add_tail(&alg_region->list, &dsp->alg_regions); + + if (dsp->fw_ver > 0) + wm_adsp_ctl_fixup_base(dsp, alg_region); + + return alg_region; +} + +static void wm_adsp_free_alg_regions(struct wm_adsp *dsp) +{ + struct wm_adsp_alg_region *alg_region; + + while (!list_empty(&dsp->alg_regions)) { + alg_region = list_first_entry(&dsp->alg_regions, + struct wm_adsp_alg_region, list); + list_del(&alg_region->list); + kfree(alg_region); + } +} + +static int wm_adsp1_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp1_id_hdr adsp1_id; + struct wmfw_adsp1_alg_hdr *adsp1_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, mem->base, &adsp1_id, + sizeof(adsp1_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); + return ret; + } + + n_algs = be32_to_cpu(adsp1_id.n_algs); + dsp->fw_id = be32_to_cpu(adsp1_id.fw.id); + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", dsp->fw_id, + (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_id.fw.ver) & 0xff, n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, adsp1_id.fw.id, + adsp1_id.zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, adsp1_id.fw.id, + adsp1_id.dm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(adsp1_id) / 2; + len = (sizeof(*adsp1_alg) * n_algs) / 2; + + adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len); + if (IS_ERR(adsp1_alg)) + return PTR_ERR(adsp1_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", i, + be32_to_cpu(adsp1_alg[i].alg.id), + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp1_alg[i].dm), + be32_to_cpu(adsp1_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, + adsp1_alg[i].alg.id, + adsp1_alg[i].dm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].dm); + len -= be32_to_cpu(adsp1_alg[i].dm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region DM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, + adsp1_alg[i].alg.id, + adsp1_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].zm); + len -= be32_to_cpu(adsp1_alg[i].zm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp1_alg); + return ret; +} + +static int wm_adsp2_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp2_id_hdr adsp2_id; + struct wmfw_adsp2_alg_hdr *adsp2_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, mem->base, &adsp2_id, + sizeof(adsp2_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); + return ret; + } + + n_algs = be32_to_cpu(adsp2_id.n_algs); + dsp->fw_id = be32_to_cpu(adsp2_id.fw.id); + dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver); + dsp->fw_vendor_id = 0; + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", dsp->fw_id, + (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, + n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, adsp2_id.fw.id, + adsp2_id.xm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, adsp2_id.fw.id, + adsp2_id.ym); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + switch (dsp->type) { + case WMFW_HALO: + pos = sizeof(adsp2_id); + len = sizeof(*adsp2_alg) * n_algs; + break; + default: + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_id.fw.id, adsp2_id.zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(adsp2_id) / 2; + len = (sizeof(*adsp2_alg) * n_algs) / 2; + break; + } + + adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len); + if (IS_ERR(adsp2_alg)) + return PTR_ERR(adsp2_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", i, + be32_to_cpu(adsp2_alg[i].alg.id), + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp2_alg[i].xm), + be32_to_cpu(adsp2_alg[i].ym), + be32_to_cpu(adsp2_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + adsp2_alg[i].alg.id, + adsp2_alg[i].xm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].xm); + len -= be32_to_cpu(adsp2_alg[i].xm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region XM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + adsp2_alg[i].alg.id, + adsp2_alg[i].ym); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].ym); + len -= be32_to_cpu(adsp2_alg[i].ym); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region YM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + /* no ZM on HALO */ + if (dsp->type == WMFW_HALO) + continue; + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_alg[i].alg.id, + adsp2_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].zm); + len -= be32_to_cpu(adsp2_alg[i].zm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp2_alg); + return ret; +} + +static int wm_halo_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_halo_id_hdr halo_id; + struct wmfw_halo_alg_hdr *halo_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len, block_rev; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, mem->base, &halo_id, + sizeof(halo_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); + return ret; + } + + block_rev = be32_to_cpu(halo_id.fw.block_rev) >> 16; + switch (block_rev) { + case 3: + break; + default: + adsp_err(dsp, "Unknown firmware ID block version 0x%x\n", + block_rev); + return -EINVAL; + } + + n_algs = be32_to_cpu(halo_id.n_algs); + dsp->fw_id = be32_to_cpu(halo_id.fw.id); + dsp->fw_id_version = be32_to_cpu(halo_id.fw.ver); + dsp->fw_vendor_id = be32_to_cpu(halo_id.fw.vendor_id); + adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %zu algorithms\n", + dsp->fw_id, dsp->fw_vendor_id, + (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, + n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, halo_id.fw.id, + halo_id.xm_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_XM_PACKED, + halo_id.fw.id, halo_id.xm_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, halo_id.fw.id, + halo_id.ym_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_YM_PACKED, + halo_id.fw.id, halo_id.ym_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(halo_id); + len = (sizeof(*halo_alg) * n_algs); + + halo_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len); + if (IS_ERR(halo_alg)) + return PTR_ERR(halo_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d XM@%x YM@%x\n", i, + be32_to_cpu(halo_alg[i].alg.id), + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(halo_alg[i].alg.ver) & 0xff, + be32_to_cpu(halo_alg[i].xm_base), + be32_to_cpu(halo_alg[i].ym_base)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + halo_alg[i].alg.id, + halo_alg[i].xm_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_XM_PACKED, + halo_alg[i].alg.id, + halo_alg[i].xm_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + halo_alg[i].alg.id, + halo_alg[i].ym_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_HALO_YM_PACKED, + halo_alg[i].alg.id, + halo_alg[i].ym_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + } + +out: + kfree(halo_alg); + return ret; +} + +static int wm_adsp_load_coeff(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + struct regmap *regmap = dsp->regmap; + struct wmfw_coeff_hdr *hdr; + struct wmfw_coeff_item *blk; + const struct firmware *firmware; + const struct wm_adsp_region *mem; + struct wm_adsp_alg_region *alg_region; + const char *region_name; + int ret, pos, blocks, type, offset, reg; + char *file; + struct wm_adsp_buf *buf; + + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num, + wm_adsp_fw[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + + ret = request_firmware(&firmware, file, dsp->dev); + if (ret != 0) { + adsp_warn(dsp, "Failed to request '%s'\n", file); + ret = 0; + goto out; + } + ret = -EINVAL; + + if (sizeof(*hdr) >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", file, + firmware->size); + goto out_fw; + } + + hdr = (void *)&firmware->data[0]; + if (memcmp(hdr->magic, "WMDR", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + switch (be32_to_cpu(hdr->rev) & 0xff) { + case 1: + break; + default: + adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", + file, be32_to_cpu(hdr->rev) & 0xff); + ret = -EINVAL; + goto out_fw; + } + + adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, + (le32_to_cpu(hdr->ver) >> 16) & 0xff, + (le32_to_cpu(hdr->ver) >> 8) & 0xff, + le32_to_cpu(hdr->ver) & 0xff); + + pos = le32_to_cpu(hdr->len); + + blocks = 0; + while (pos < firmware->size && pos - firmware->size > sizeof(*blk)) { + blk = (void *)(&firmware->data[pos]); + + type = le16_to_cpu(blk->type); + offset = le16_to_cpu(blk->offset); + + adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", file, blocks, + le32_to_cpu(blk->id), + (le32_to_cpu(blk->ver) >> 16) & 0xff, + (le32_to_cpu(blk->ver) >> 8) & 0xff, + le32_to_cpu(blk->ver) & 0xff); + adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", file, blocks, + le32_to_cpu(blk->len), offset, type); + + reg = 0; + region_name = "Unknown"; + switch (type) { + case (WMFW_NAME_TEXT << 8): + case (WMFW_INFO_TEXT << 8): + break; + case (WMFW_ABSOLUTE << 8): + /* + * Old files may use this for global + * coefficients. + */ + if (le32_to_cpu(blk->id) == dsp->fw_id && offset == 0) { + region_name = "global coefficients"; + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No ZM\n"); + break; + } + reg = wm_adsp_region_to_reg(dsp, mem, 0); + + } else { + region_name = "register"; + reg = offset; + } + break; + + case WMFW_ADSP1_DM: + case WMFW_ADSP1_ZM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + case WMFW_HALO_PM_PACKED: + adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", file, + blocks, le32_to_cpu(blk->len), type, + le32_to_cpu(blk->id)); + + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", type); + break; + } + + alg_region = wm_adsp_find_alg_region( + dsp, type, le32_to_cpu(blk->id)); + if (alg_region) { + reg = alg_region->base; + reg = wm_adsp_region_to_reg(dsp, mem, reg); + reg += offset; + } else { + adsp_err(dsp, "No %x for algorithm %x\n", type, + le32_to_cpu(blk->id)); + } + break; + + default: + adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", + file, blocks, type, pos); + break; + } + + if (reg) { + if ((pos + le32_to_cpu(blk->len) + sizeof(*blk)) > + firmware->size) { + adsp_err( + dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, blocks, region_name, + le32_to_cpu(blk->len), firmware->size); + ret = -EINVAL; + goto out_fw; + } + + buf = wm_adsp_buf_alloc( + blk->data, le32_to_cpu(blk->len), &buf_list); + if (!buf) { + adsp_err(dsp, "Out of memory\n"); + ret = -ENOMEM; + goto out_fw; + } + + adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", file, + blocks, le32_to_cpu(blk->len), reg); + ret = regmap_raw_write_async(regmap, reg, buf->buf, + le32_to_cpu(blk->len)); + if (ret != 0) { + adsp_err( + dsp, + "%s.%d: Failed to write to %x in %s: %d\n", + file, blocks, reg, region_name, ret); + } + } + + pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; + blocks++; + } + + ret = regmap_async_complete(regmap); + if (ret != 0) + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, + blocks, pos - firmware->size); + + wm_adsp_debugfs_save_binname(dsp, file); + +out_fw: + regmap_async_complete(regmap); + release_firmware(firmware); + wm_adsp_buf_free(&buf_list); +out: + kfree(file); + return ret; +} + +int wm_adsp1_init(struct wm_adsp *dsp) +{ + INIT_LIST_HEAD(&dsp->alg_regions); + + mutex_init(&dsp->pwr_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp1_init); + +int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + int ret; + unsigned int val; + + dsp->codec = codec; + + mutex_lock(&dsp->pwr_lock); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, ADSP1_SYS_ENA); + + /* + * For simplicity set the DSP clock rate to be the + * SYSCLK rate rather than making it configurable. + */ + if (dsp->sysclk_reg) { + ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); + if (ret != 0) { + adsp_err(dsp, + "Failed to read SYSCLK state: %d\n", + ret); + goto err_mutex; + } + + val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; + + ret = regmap_update_bits(dsp->regmap, + dsp->base + ADSP1_CONTROL_31, + ADSP1_CLK_SEL_MASK, val); + if (ret != 0) { + adsp_err(dsp, "Failed to set clock rate: %d\n", + ret); + goto err_mutex; + } + } + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp1_setup_algs(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err_ena; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err_ena; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err_ena; + + dsp->booted = true; + + /* Start the core running */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, + ADSP1_CORE_ENA | ADSP1_START); + + dsp->running = true; + break; + + case SND_SOC_DAPM_PRE_PMD: + dsp->running = false; + dsp->booted = false; + + /* Halt the core */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, + ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); + + list_for_each_entry (ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + break; + + default: + break; + } + + mutex_unlock(&dsp->pwr_lock); + + return 0; + +err_ena: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); +err_mutex: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp1_event); + +static int wm_adsp2_ena(struct wm_adsp *dsp) +{ + unsigned int val; + int ret, count; + + switch (dsp->rev) { + case 0: + ret = regmap_update_bits_async(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, ADSP2_SYS_ENA); + if (ret != 0) + return ret; + break; + default: + break; + } + + /* Wait for the RAM to start, should be near instantaneous */ + for (count = 0; count < 10; ++count) { + ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); + if (ret != 0) + return ret; + + if (val & ADSP2_RAM_RDY) + break; + + usleep_range(250, 500); + } + + if (!(val & ADSP2_RAM_RDY)) { + adsp_err(dsp, "Failed to start DSP RAM\n"); + return -EBUSY; + } + + adsp_dbg(dsp, "RAM ready after %d polls\n", count); + + return 0; +} + +static void wm_adsp2_boot_work(struct work_struct *work) +{ + struct wm_adsp *dsp = container_of(work, struct wm_adsp, boot_work); + int ret; + + mutex_lock(&dsp->pwr_lock); + + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, ADSP2_MEM_ENA); + if (ret != 0) + goto err_mutex; + + ret = wm_adsp2_ena(dsp); + if (ret != 0) + goto err_mem; + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp2_setup_algs(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err_ena; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err_ena; + + switch (dsp->rev) { + case 0: + /* Turn DSP back off until we are ready to run */ + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, 0); + if (ret != 0) + goto err_ena; + break; + default: + break; + } + + dsp->booted = true; + + mutex_unlock(&dsp->pwr_lock); + + return; + +err_ena: + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); +err_mem: + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); +err_mutex: + mutex_unlock(&dsp->pwr_lock); +} + +static int wm_halo_set_rate_block(struct wm_adsp *dsp, unsigned int rate_base, + unsigned int n_rates, const u8 *rate_cache) +{ + unsigned int addr = dsp->base + rate_base, val; + int ret, i; + + for (i = 0; i < n_rates; ++i) { + val = rate_cache[i] << HALO_DSP_RATE_SHIFT; + + ret = regmap_update_bits(dsp->regmap, addr + (i * 8), + HALO_DSP_RATE_MASK, val); + if (ret) { + adsp_err(dsp, "Failed to set rate: %d\n", ret); + return ret; + } + + adsp_dbg(dsp, "Set rate %d to 0x%x\n", i, val); + } + + return 0; +} + +static int wm_halo_clear_stream_arb(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + unsigned int dspbase = dsp->base, reg; + u32 values[3] = { 0, 0, 0 }; + int ret; + + /* disable stream arbiter masters */ + for (reg = dspbase + HALO_STREAM_ARB_MSTR0_CONFIG_0; + reg <= dspbase + HALO_STREAM_ARB_MSTR5_CONFIG_0; reg += 0x10) { + ret = regmap_update_bits(regmap, reg, + HALO_STREAM_ARB_MSTR_EN_MASK, 0); + if (ret) + goto error; + } + + /* clear stream arbiter masters */ + for (reg = dspbase + HALO_STREAM_ARB_MSTR0_CONFIG_0; + reg <= dspbase + HALO_STREAM_ARB_MSTR5_CONFIG_0; reg += 0x10) { + ret = regmap_bulk_write(regmap, reg, values, 3); + if (ret) + goto error; + } + + /* clear stream arbiter channel configs */ + for (reg = dspbase + HALO_STREAM_ARB_TX1_CONFIG_0; + reg <= dspbase + HALO_STREAM_ARB_RX8_CONFIG_0; reg += 0x8) { + ret = regmap_write(regmap, reg, + HALO_STREAM_ARB_MSTR_SEL_DEFAULT); + if (ret) + goto error; + } + + /* clear stream arbiter interrupt registers */ + values[0] = HALO_STREAM_ARB_MSTR_SEL_DEFAULT; + for (reg = dspbase + HALO_STREAM_ARB_IRQ0_CONFIG_0; + reg <= dspbase + HALO_STREAM_ARB_IRQ7_CONFIG_1; reg += 0x10) { + ret = regmap_bulk_write(regmap, reg, values, 2); + if (ret) + goto error; + } + return 0; + +error: + adsp_err(dsp, + "Error while clearing stream arbiter config (reg 0x%x): %d\n", + reg, ret); + return ret; +} + +static int wm_halo_configure_mpu(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + int i = 0, len = 0, ret; + unsigned int sysinfo_base = dsp->base_sysinfo, dsp_base = dsp->base; + unsigned int xm_sz, xm_bank_sz, ym_sz, ym_bank_sz; + unsigned int xm_acc_cfg, ym_acc_cfg; + unsigned int lock_cfg; + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_XM_BANK_SIZE, + &xm_bank_sz); + if (ret) { + adsp_err(dsp, "Failed to read XM bank size.\n"); + goto err; + } + + if (!xm_bank_sz) { + adsp_err(dsp, "Failed to configure MPU (XM_BANK_SIZE = 0)\n"); + goto err; + } + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_YM_BANK_SIZE, + &ym_bank_sz); + if (ret) { + adsp_err(dsp, "Failed to read YM bank size.\n"); + goto err; + } + + if (!ym_bank_sz) { + adsp_err(dsp, "Failed to configure MPU (YM_BANK_SIZE = 0)\n"); + goto err; + } + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_XM_SRAM_SIZE, + &xm_sz); + if (ret) { + adsp_err(dsp, "Failed to read XM size.\n"); + goto err; + } + + ret = regmap_read(regmap, sysinfo_base + HALO_SYS_INFO_YM_SRAM_SIZE, + &ym_sz); + if (ret) { + adsp_err(dsp, "Failed to read YM size.\n"); + goto err; + } + + adsp_dbg( + dsp, + "XM size 0x%x XM bank size 0x%x YM size 0x%x YM bank size 0x%x\n", + xm_sz, xm_bank_sz, ym_sz, ym_bank_sz); + + /* calculate amount of banks to unlock */ + xm_acc_cfg = (1 << (xm_sz / xm_bank_sz)) - 1; + ym_acc_cfg = (1 << (ym_sz / ym_bank_sz)) - 1; + + /* unlock MPU */ + ret = regmap_write(regmap, dsp_base + HALO_MPU_LOCK_CONFIG, + HALO_MPU_UNLOCK_CODE_0); + if (ret) { + adsp_err(dsp, "Error while unlocking MPU: %d\n", ret); + goto err; + } + + ret = regmap_write(regmap, dsp_base + HALO_MPU_LOCK_CONFIG, + HALO_MPU_UNLOCK_CODE_1); + if (ret) { + adsp_err(dsp, "Error while unlocking MPU: %d\n", ret); + goto err; + } + + adsp_dbg(dsp, "Unlocking XM (cfg: %x) and YM (cfg: %x)", xm_acc_cfg, + ym_acc_cfg); + + /* unlock XMEM and YMEM */ + ret = regmap_write(regmap, dsp_base + HALO_MPU_XMEM_ACCESS_0, + xm_acc_cfg); + if (ret) + goto err; + + ret = regmap_write(regmap, dsp_base + HALO_MPU_YMEM_ACCESS_0, + ym_acc_cfg); + if (ret) + goto err; + + len = sizeof(halo_mpu_access) / sizeof(halo_mpu_access[0]); + lock_cfg = (dsp->unlock_all) ? 0xFFFFFFFF : 0; + /* configure all other banks */ + for (i = 0; i < len; i++) { /* TODO: think if can be done without LUT */ + ret = regmap_write(regmap, dsp_base + halo_mpu_access[i], + lock_cfg); + if (ret) + goto err; + } + + /* lock MPU */ + ret = regmap_write(regmap, dsp_base + HALO_MPU_LOCK_CONFIG, 0); + if (ret) + adsp_err(dsp, "Error while locking MPU: %d\n", ret); + +err: + return ret; +} + +static void wm_halo_boot_work(struct work_struct *work) +{ + struct wm_adsp *dsp = container_of(work, struct wm_adsp, boot_work); + int ret; + + mutex_lock(&dsp->pwr_lock); + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err; + + switch (dsp->fw_ver) { + case 1: + case 2: + ret = wm_adsp2_setup_algs(dsp); + if (ret != 0) + goto err; + break; + default: + ret = wm_halo_setup_algs(dsp); + if (ret != 0) + goto err; + break; + } + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err; + + dsp->booted = true; + + mutex_unlock(&dsp->pwr_lock); + + return; + +err: + regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, 0); + mutex_unlock(&dsp->pwr_lock); +} + +static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq) +{ + int ret; + + switch (dsp->rev) { + case 0: + ret = regmap_update_bits_async(dsp->regmap, + dsp->base + ADSP2_CLOCKING, + ADSP2_CLK_SEL_MASK, + freq << ADSP2_CLK_SEL_SHIFT); + if (ret) { + adsp_err(dsp, "Failed to set clock rate: %d\n", ret); + return; + } + break; + default: + /* clock is handled by parent codec driver */ + break; + } +} + +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = dsp->preloaded; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get); + +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + char preload[32]; + + snprintf(preload, ARRAY_SIZE(preload), "DSP%u Preload", mc->shift); + + dsp->preloaded = ucontrol->value.integer.value[0]; + + if (ucontrol->value.integer.value[0]) + snd_soc_dapm_force_enable_pin(dapm, preload); + else + snd_soc_dapm_disable_pin(dapm, preload); + + snd_soc_dapm_sync(dapm); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put); + +static void wm_adsp_stop_watchdog(struct wm_adsp *dsp) +{ + switch (dsp->rev) { + case 0: + case 1: + return; + default: + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, + ADSP2_WDT_ENA_MASK, 0); + } +} + +int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event, + unsigned int freq) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + wm_adsp2_set_dspclk(dsp, freq); + queue_work(system_unbound_wq, &dsp->boot_work); + break; + case SND_SOC_DAPM_PRE_PMD: + mutex_lock(&dsp->pwr_lock); + + wm_adsp_debugfs_clear(dsp); + + dsp->fw_id = 0; + dsp->fw_id_version = 0; + + dsp->booted = false; + + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); + + list_for_each_entry (ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Shutdown complete\n"); + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_early_event); + +int wm_halo_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + int ret; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + ret = regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_RESET, HALO_CORE_RESET); + if (ret != 0) { + adsp_err(dsp, "Error while resetting core: %d\n", ret); + return ret; + } + + queue_work(system_unbound_wq, &dsp->boot_work); + break; + case SND_SOC_DAPM_PRE_PMD: + mutex_lock(&dsp->pwr_lock); + + wm_adsp_debugfs_clear(dsp); + + dsp->fw_id = 0; + dsp->fw_id_version = 0; + + dsp->booted = false; + + list_for_each_entry (ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Shutdown complete\n"); + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_halo_early_event); + +int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + flush_work(&dsp->boot_work); + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->booted) { + ret = -EIO; + goto err; + } + + ret = wm_adsp2_ena(dsp); + if (ret != 0) + goto err; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; + + wm_adsp2_lock(dsp, dsp->lock_regions); + + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, + ADSP2_CORE_ENA | ADSP2_START); + if (ret != 0) + goto err; + + if (wm_adsp_fw[dsp->fw].num_caps != 0) { + ret = wm_adsp_buffer_init(dsp); + if (ret < 0) + goto err; + } + + dsp->running = true; + + mutex_unlock(&dsp->pwr_lock); + + break; + + case SND_SOC_DAPM_PRE_PMD: + /* Tell the firmware to cleanup */ + wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); + + wm_adsp_stop_watchdog(dsp); + + /* Log firmware state, it can be useful for analysis */ + switch (dsp->rev) { + case 0: + wm_adsp2_show_fw_status(dsp); + break; + default: + wm_adsp2v2_show_fw_status(dsp); + break; + } + + mutex_lock(&dsp->pwr_lock); + + dsp->running = false; + + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, 0); + + /* Make sure DMAs are quiesced */ + switch (dsp->rev) { + case 0: + regmap_write(dsp->regmap, + dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2_WDMA_CONFIG_2, 0); + + regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, 0); + break; + default: + regmap_write(dsp->regmap, + dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); + break; + } + + if (wm_adsp_fw[dsp->fw].num_caps != 0) + wm_adsp_buffer_free(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Execution stopped\n"); + break; + + default: + break; + } + + return 0; +err: + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); + mutex_unlock(&dsp->pwr_lock); + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp2_event); + +int wm_halo_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + flush_work(&dsp->boot_work); + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->booted) { + ret = -EIO; + goto err; + } + wm_halo_apply_calibration(w); + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; + + //wm_halo_apply_calibration(w); + + adsp_dbg(dsp, "Setting RX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_RX1, + dsp->n_rx_rates, + dsp->rx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set RX rates.\n"); + goto err; + } + + adsp_dbg(dsp, "Setting TX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_TX1, + dsp->n_tx_rates, + dsp->tx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set TX rates.\n"); + goto err; + } + + ret = wm_halo_clear_stream_arb(dsp); + if (ret != 0) + goto err; + + /* disable NMI */ + ret = regmap_write(dsp->regmap, + dsp->base + HALO_INTP_CTL_NMI_CONTROL, 0); + if (ret != 0) { + adsp_err(dsp, "Error while disabling NMI: %d\n", ret); + goto err; + } + + ret = wm_halo_configure_mpu(dsp); + if (ret != 0) + goto err; + + ret = regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, HALO_CORE_EN); + + if (ret != 0) + goto err; + + if (wm_adsp_fw[dsp->fw].num_caps != 0) { + ret = wm_adsp_buffer_init(dsp); + if (ret < 0) + goto err; + } + + dsp->running = true; + + mutex_unlock(&dsp->pwr_lock); + + break; + case SND_SOC_DAPM_PRE_PMD: + /* Tell the firmware to cleanup */ + wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); + + /* Log firmware state, it can be useful for analysis */ + wm_halo_show_fw_status(dsp); + + mutex_lock(&dsp->pwr_lock); + + dsp->running = false; + + regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, 0); + + wm_halo_clear_stream_arb(dsp); + + if (wm_adsp_fw[dsp->fw].num_caps != 0) + wm_adsp_buffer_free(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_info(dsp, "Execution stopped\n"); + break; + default: + break; + } + + return 0; +err: + mutex_unlock(&dsp->pwr_lock); + regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, 0); + return ret; +} +EXPORT_SYMBOL_GPL(wm_halo_event); + +static int wm_coeff_k_put(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret = 0; + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + ret = 0; + } else + memcpy(ctl->cache, p, ctl->len); + + ctl->set = 1; + ret = wm_coeff_write_control(ctl, p, ctl->len); + + return ret; +} +static int wm_coeff_k_get(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret = 0; + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + ret = wm_coeff_read_control(ctl, p, ctl->len); + } else { + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + memcpy(p, ctl->cache, ctl->len); + } + + return ret; +} +static int wm_adsp_k_ctl_put(struct wm_adsp *dsp, const char *name, int value) +{ + struct snd_kcontrol *kctl = NULL; + struct snd_ctl_elem_value ucontrol; + struct snd_soc_card *card = dsp->codec->component.card; + + kctl = snd_soc_card_get_kcontrol(card, name); + if (kctl == NULL) { + adsp_warn(dsp, "%s: %s isn't found\n", __func__, name); + return -1; + } + + adsp_dbg(dsp, "%s: %s:0x%x\n", __func__, kctl->id.name, value); + value = cpu_to_be32(value); + memcpy((char *)ucontrol.value.bytes.data, (char *)&value, + sizeof(value)); + wm_coeff_k_put(kctl, &ucontrol); + + return 0; +} + +static int wm_adsp_k_ctl_get(struct wm_adsp *dsp, const char *name) +{ + struct snd_kcontrol *kctl = NULL; + struct snd_ctl_elem_value ucontrol; + struct snd_soc_card *card = dsp->codec->component.card; + + int value = 0; + + kctl = snd_soc_card_get_kcontrol(card, name); + if (kctl == NULL) { + adsp_warn(dsp, "%s: %s isn't found\n", __func__, name); + return -1; + } + + wm_coeff_k_get(kctl, &ucontrol); + memcpy((char *)&value, (char *)ucontrol.value.bytes.data, + sizeof(value)); + value = be32_to_cpu(value); + + adsp_dbg(dsp, "%s: %s:0x%x\n", __func__, kctl->id.name, value); + + return 0; +} + +static int wm_halo_apply_calibration(struct snd_soc_dapm_widget *w) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + + switch (dsp->fw) { + case WM_ADSP_FW_CALIB: + adsp_warn(dsp, "Set ambient %d, only for Z Diagnostic\n", + dsp->ambient); + wm_adsp_k_ctl_put(dsp, "DSP1X Diag Z cd CAL_AMBIENT", + dsp->ambient); + break; + case WM_ADSP_FW_DIAG: + adsp_warn(dsp, "Set ambient %d, only for Diagnostic\n", + dsp->ambient); + wm_adsp_k_ctl_put(dsp, "DSP1X Diag cd CAL_AMBIENT", + dsp->ambient); + break; + case WM_ADSP_FW_SPK_PROT: + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd CAL_R", dsp->cal_z); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd CAL_STATUS", + dsp->cal_status); + wm_adsp_k_ctl_put(dsp, "DSP1X Protection cd CAL_CHECKSUM", + dsp->cal_chksum); + wm_adsp_k_ctl_get(dsp, "DSP1X Protection cd CAL_R"); + wm_adsp_k_ctl_get(dsp, "DSP1X Protection cd CAL_STATUS"); + wm_adsp_k_ctl_get(dsp, "DSP1X Protection cd CAL_CHECKSUM"); + break; + default: + break; + } + + adsp_warn(dsp, "Do thing'\n"); + return 0; +} + +int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec) +{ + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + char preload[32]; + + snprintf(preload, ARRAY_SIZE(preload), "DSP%d Preload", dsp->num); + snd_soc_dapm_disable_pin(dapm, preload); + + wm_adsp2_init_debugfs(dsp, codec); + + dsp->codec = codec; + + snd_soc_add_codec_controls(codec, wm_adsp_cal_controls, + ARRAY_SIZE(wm_adsp_cal_controls)); + + return snd_soc_add_codec_controls( + codec, &wm_adsp_fw_controls[dsp->num - 1], 1); +} +EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe); + +int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec) +{ + wm_adsp2_cleanup_debugfs(dsp); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove); + +int wm_adsp2_init(struct wm_adsp *dsp) +{ + int ret; + + switch (dsp->rev) { + case 0: + /* + * Disable the DSP memory by default when in reset for a small + * power saving. + */ + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); + if (ret) { + adsp_err(dsp, "Failed to clear memory retention: %d\n", + ret); + return ret; + } + break; + default: + break; + } + + INIT_LIST_HEAD(&dsp->alg_regions); + INIT_LIST_HEAD(&dsp->ctl_list); + INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work); + + mutex_init(&dsp->pwr_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_init); + +int wm_halo_init(struct wm_adsp *dsp) +{ + INIT_LIST_HEAD(&dsp->alg_regions); + INIT_LIST_HEAD(&dsp->ctl_list); + INIT_WORK(&dsp->boot_work, wm_halo_boot_work); + + mutex_init(&dsp->pwr_lock); + + dsp->rx_rate_cache = kcalloc(dsp->n_rx_rates, sizeof(u8), GFP_KERNEL); + dsp->tx_rate_cache = kcalloc(dsp->n_tx_rates, sizeof(u8), GFP_KERNEL); + + dsp->ambient = AMBIENT_DEFAULT; + dsp->cal_z = CAL_R_DEFAULT; + dsp->cal_status = CAL_STATUS_DEFAULT; + dsp->cal_chksum = CAL_R_DEFAULT + CAL_STATUS_DEFAULT; + return 0; +} +EXPORT_SYMBOL_GPL(wm_halo_init); + +void wm_adsp2_remove(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + + while (!list_empty(&dsp->ctl_list)) { + ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl, + list); + list_del(&ctl->list); + wm_adsp_free_ctl_blk(ctl); + } + + kfree(dsp->rx_rate_cache); + kfree(dsp->tx_rate_cache); +} +EXPORT_SYMBOL_GPL(wm_adsp2_remove); + +static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr) +{ + return compr->buf != NULL; +} + +static int wm_adsp_compr_attach(struct wm_adsp_compr *compr) +{ + /* + * Note this will be more complex once each DSP can support multiple + * streams + */ + if (!compr->dsp->buffer) + return -EINVAL; + + compr->buf = compr->dsp->buffer; + compr->buf->compr = compr; + + return 0; +} + +static void wm_adsp_compr_detach(struct wm_adsp_compr *compr) +{ + if (!compr) + return; + + /* Wake the poll so it can see buffer is no longer attached */ + if (compr->stream) + snd_compr_fragment_elapsed(compr->stream); + + if (wm_adsp_compr_attached(compr)) { + compr->buf->compr = NULL; + compr->buf = NULL; + } +} + +int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream) +{ + struct wm_adsp_compr *compr; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + if (wm_adsp_fw[dsp->fw].num_caps == 0) { + adsp_err(dsp, "Firmware does not support compressed API\n"); + ret = -ENXIO; + goto out; + } + + if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) { + adsp_err(dsp, "Firmware does not support stream direction\n"); + ret = -EINVAL; + goto out; + } + + if (dsp->compr) { + /* It is expect this limitation will be removed in future */ + adsp_err(dsp, "Only a single stream supported per DSP\n"); + ret = -EBUSY; + goto out; + } + + compr = kzalloc(sizeof(*compr), GFP_KERNEL); + if (!compr) { + ret = -ENOMEM; + goto out; + } + + compr->dsp = dsp; + compr->stream = stream; + + dsp->compr = compr; + + stream->runtime->private_data = compr; + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_open); + +int wm_adsp_compr_free(struct snd_compr_stream *stream) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + + mutex_lock(&dsp->pwr_lock); + + wm_adsp_compr_detach(compr); + dsp->compr = NULL; + + kfree(compr->raw_buf); + kfree(compr); + + mutex_unlock(&dsp->pwr_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_free); + +static int wm_adsp_compr_check_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + const struct wm_adsp_fw_caps *caps; + const struct snd_codec_desc *desc; + int i, j; + + if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE || + params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE || + params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS || + params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS || + params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) { + adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n", + params->buffer.fragment_size, + params->buffer.fragments); + + return -EINVAL; + } + + for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) { + caps = &wm_adsp_fw[dsp->fw].caps[i]; + desc = &caps->desc; + + if (caps->id != params->codec.id) + continue; + + if (stream->direction == SND_COMPRESS_PLAYBACK) { + if (desc->max_ch < params->codec.ch_out) + continue; + } else { + if (desc->max_ch < params->codec.ch_in) + continue; + } + + if (!(desc->formats & (1 << params->codec.format))) + continue; + + for (j = 0; j < desc->num_sample_rates; ++j) + if (desc->sample_rates[j] == params->codec.sample_rate) + return 0; + } + + adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n", + params->codec.id, params->codec.ch_in, params->codec.ch_out, + params->codec.sample_rate, params->codec.format); + return -EINVAL; +} + +static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr) +{ + return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE; +} + +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + unsigned int size; + int ret; + + ret = wm_adsp_compr_check_params(stream, params); + if (ret) + return ret; + + compr->size = params->buffer; + + adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n", + compr->size.fragment_size, compr->size.fragments); + + size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf); + compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL); + if (!compr->raw_buf) + return -ENOMEM; + + compr->sample_rate = params->codec.sample_rate; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params); + +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + int fw = compr->dsp->fw; + int i; + + if (wm_adsp_fw[fw].caps) { + for (i = 0; i < wm_adsp_fw[fw].num_caps; i++) + caps->codecs[i] = wm_adsp_fw[fw].caps[i].id; + + caps->num_codecs = i; + caps->direction = wm_adsp_fw[fw].compr_direction; + + caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE; + caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE; + caps->min_fragments = WM_ADSP_MIN_FRAGMENTS; + caps->max_fragments = WM_ADSP_MAX_FRAGMENTS; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps); + +static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, + unsigned int num_words, u32 *data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); + unsigned int i, reg; + int ret; + + if (!mem) + return -EINVAL; + + reg = wm_adsp_region_to_reg(dsp, mem, mem_addr); + + ret = wm_adsp2_raw_read(MAXBULK, dsp->regmap, reg, data, + sizeof(*data) * num_words); + if (ret < 0) + return ret; + + for (i = 0; i < num_words; ++i) + data[i] = be32_to_cpu(data[i]) & 0x00ffffffu; + + return 0; +} + +static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 *data) +{ + return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data); +} + +static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); + unsigned int reg; + + if (!mem) + return -EINVAL; + + reg = wm_adsp_region_to_reg(dsp, mem, mem_addr); + + data = cpu_to_be32(data & 0x00ffffffu); + + return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data)); +} + +static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 *data) +{ + return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM, + buf->host_buf_ptr + field_offset, data); +} + +static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 data) +{ + return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM, + buf->host_buf_ptr + field_offset, data); +} + +static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf) +{ + struct wm_adsp_alg_region *alg_region; + struct wm_adsp *dsp = buf->dsp; + u32 xmalg, addr, magic; + int i, ret; + + alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id); + xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32); + + addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic); + if (ret < 0) + return ret; + + if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC) + return -EINVAL; + + addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr); + for (i = 0; i < 5; ++i) { + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, + &buf->host_buf_ptr); + if (ret < 0) + return ret; + + if (buf->host_buf_ptr) + break; + + usleep_range(1000, 2000); + } + + if (!buf->host_buf_ptr) + return -EIO; + + adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr); + + return 0; +} + +static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf) +{ + const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps; + struct wm_adsp_buffer_region *region; + u32 offset = 0; + int i, ret; + + for (i = 0; i < caps->num_regions; ++i) { + region = &buf->regions[i]; + + region->offset = offset; + region->mem_type = caps->region_defs[i].mem_type; + + ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset, + ®ion->base_addr); + if (ret < 0) + return ret; + + ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset, + &offset); + if (ret < 0) + return ret; + + region->cumulative_size = offset; + + adsp_dbg(buf->dsp, + "region=%d type=%d base=%04x off=%04x size=%04x\n", i, + region->mem_type, region->base_addr, region->offset, + region->cumulative_size); + } + + return 0; +} + +static int wm_adsp_buffer_init(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf; + int ret; + + buf = kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) + return -ENOMEM; + + buf->dsp = dsp; + buf->read_index = -1; + buf->irq_count = 0xFFFFFFFF; + + ret = wm_adsp_buffer_locate(buf); + if (ret < 0) { + adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret); + goto err_buffer; + } + + buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions, + sizeof(*buf->regions), GFP_KERNEL); + if (!buf->regions) { + ret = -ENOMEM; + goto err_buffer; + } + + ret = wm_adsp_buffer_populate(buf); + if (ret < 0) { + adsp_err(dsp, "Failed to populate host buffer: %d\n", ret); + goto err_regions; + } + + dsp->buffer = buf; + + return 0; + +err_regions: + kfree(buf->regions); +err_buffer: + kfree(buf); + return ret; +} + +static int wm_adsp_buffer_free(struct wm_adsp *dsp) +{ + if (dsp->buffer) { + wm_adsp_compr_detach(dsp->buffer->compr); + + kfree(dsp->buffer->regions); + kfree(dsp->buffer); + + dsp->buffer = NULL; + } + + return 0; +} + +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int ret = 0; + + adsp_dbg(dsp, "Trigger: %d\n", cmd); + + mutex_lock(&dsp->pwr_lock); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (wm_adsp_compr_attached(compr)) + break; + + ret = wm_adsp_compr_attach(compr); + if (ret < 0) { + adsp_err(dsp, "Failed to link buffer and stream: %d\n", + ret); + break; + } + + /* Trigger the IRQ at one fragment of data */ + ret = wm_adsp_buffer_write(compr->buf, + HOST_BUFFER_FIELD(high_water_mark), + wm_adsp_compr_frag_words(compr)); + if (ret < 0) { + adsp_err(dsp, "Failed to set high water mark: %d\n", + ret); + break; + } + break; + case SNDRV_PCM_TRIGGER_STOP: + break; + default: + ret = -EINVAL; + break; + } + + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger); + +static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf) +{ + int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1; + + return buf->regions[last_region].cumulative_size; +} + +static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf) +{ + u32 next_read_index, next_write_index; + int write_index, read_index, avail; + int ret; + + /* Only sync read index if we haven't already read a valid index */ + if (buf->read_index < 0) { + ret = wm_adsp_buffer_read(buf, + HOST_BUFFER_FIELD(next_read_index), + &next_read_index); + if (ret < 0) + return ret; + + read_index = sign_extend32(next_read_index, 23); + + if (read_index < 0) { + adsp_dbg(buf->dsp, "Avail check on unstarted stream\n"); + return 0; + } + + buf->read_index = read_index; + } + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index), + &next_write_index); + if (ret < 0) + return ret; + + write_index = sign_extend32(next_write_index, 23); + + avail = write_index - buf->read_index; + if (avail < 0) + avail += wm_adsp_buffer_size(buf); + + adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n", + buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE); + + buf->avail = avail; + + return 0; +} + +static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf) +{ + int ret; + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error); + if (ret < 0) { + adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret); + return ret; + } + if (buf->error != 0) { + adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error); + return -EIO; + } + + return 0; +} + +int wm_adsp_compr_handle_irq(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf; + struct wm_adsp_compr *compr; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + buf = dsp->buffer; + compr = dsp->compr; + + if (!buf) { + ret = -ENODEV; + goto out; + } + + adsp_dbg(dsp, "Handling buffer IRQ\n"); + + ret = wm_adsp_buffer_get_error(buf); + if (ret < 0) + goto out_notify; /* Wake poll to report error */ + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count), + &buf->irq_count); + if (ret < 0) { + adsp_err(dsp, "Failed to get irq_count: %d\n", ret); + goto out; + } + + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + adsp_err(dsp, "Error reading avail: %d\n", ret); + goto out; + } + + if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2) + ret = WM_ADSP_COMPR_VOICE_TRIGGER; + +out_notify: + if (compr && compr->stream) + snd_compr_fragment_elapsed(compr->stream); + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq); + +static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf) +{ + if (buf->irq_count & 0x01) + return 0; + + adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n", + buf->irq_count); + + buf->irq_count |= 0x01; + + return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack), + buf->irq_count); +} + +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + struct wm_adsp_compr_buf *buf; + int ret = 0; + + adsp_dbg(dsp, "Pointer request\n"); + + mutex_lock(&dsp->pwr_lock); + + buf = compr->buf; + + if (!compr->buf || compr->buf->error) { + snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN); + ret = -EIO; + goto out; + } + + if (buf->avail < wm_adsp_compr_frag_words(compr)) { + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + adsp_err(dsp, "Error reading avail: %d\n", ret); + goto out; + } + + /* + * If we really have less than 1 fragment available tell the + * DSP to inform us once a whole fragment is available. + */ + if (buf->avail < wm_adsp_compr_frag_words(compr)) { + ret = wm_adsp_buffer_get_error(buf); + if (ret < 0) { + if (compr->buf->error) + snd_compr_stop_error( + stream, SNDRV_PCM_STATE_XRUN); + goto out; + } + + ret = wm_adsp_buffer_reenable_irq(buf); + if (ret < 0) { + adsp_err(dsp, + "Failed to re-enable buffer IRQ: %d\n", + ret); + goto out; + } + } + } + + tstamp->copied_total = compr->copied_total; + tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE; + tstamp->sampling_rate = compr->sample_rate; + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); + +static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) +{ + struct wm_adsp_compr_buf *buf = compr->buf; + u8 *pack_in = (u8 *)compr->raw_buf; + u8 *pack_out = (u8 *)compr->raw_buf; + unsigned int adsp_addr; + int mem_type, nwords, max_read; + int i, j, ret; + + /* Calculate read parameters */ + for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i) + if (buf->read_index < buf->regions[i].cumulative_size) + break; + + if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions) + return -EINVAL; + + mem_type = buf->regions[i].mem_type; + adsp_addr = buf->regions[i].base_addr + + (buf->read_index - buf->regions[i].offset); + + max_read = wm_adsp_compr_frag_words(compr); + nwords = buf->regions[i].cumulative_size - buf->read_index; + + if (nwords > target) + nwords = target; + if (nwords > buf->avail) + nwords = buf->avail; + if (nwords > max_read) + nwords = max_read; + if (!nwords) + return 0; + + /* Read data from DSP */ + ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr, nwords, + compr->raw_buf); + if (ret < 0) + return ret; + + /* Remove the padding bytes from the data read from the DSP */ + for (i = 0; i < nwords; i++) { + for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++) + *pack_out++ = *pack_in++; + + pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE; + } + + /* update read index to account for words read */ + buf->read_index += nwords; + if (buf->read_index == wm_adsp_buffer_size(buf)) + buf->read_index = 0; + + ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index), + buf->read_index); + if (ret < 0) + return ret; + + /* update avail to account for words read */ + buf->avail -= nwords; + + return nwords; +} + +static int wm_adsp_compr_read(struct wm_adsp_compr *compr, char __user *buf, + size_t count) +{ + struct wm_adsp *dsp = compr->dsp; + int ntotal = 0; + int nwords, nbytes; + + adsp_dbg(dsp, "Requested read of %zu bytes\n", count); + + if (!compr->buf || compr->buf->error) { + snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN); + return -EIO; + } + + count /= WM_ADSP_DATA_WORD_SIZE; + + do { + nwords = wm_adsp_buffer_capture_block(compr, count); + if (nwords < 0) { + adsp_err(dsp, "Failed to capture block: %d\n", nwords); + return nwords; + } + + nbytes = nwords * WM_ADSP_DATA_WORD_SIZE; + + adsp_dbg(dsp, "Read %d bytes\n", nbytes); + + if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) { + adsp_err(dsp, "Failed to copy data to user: %d, %d\n", + ntotal, nbytes); + return -EFAULT; + } + + count -= nwords; + ntotal += nbytes; + } while (nwords > 0 && count > 0); + + compr->copied_total += ntotal; + + return ntotal; +} + +int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf, + size_t count) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int ret; + + mutex_lock(&dsp->pwr_lock); + + if (stream->direction == SND_COMPRESS_CAPTURE) + ret = wm_adsp_compr_read(compr, buf, count); + else + ret = -ENOTSUPP; + + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_copy); + +int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions) +{ + struct regmap *regmap = dsp->regmap; + unsigned int code0, code1, lock_reg; + + if (!(lock_regions & WM_ADSP2_REGION_ALL)) + return 0; + + lock_regions &= WM_ADSP2_REGION_ALL; + lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; + + while (lock_regions) { + code0 = code1 = 0; + if (lock_regions & BIT(0)) { + code0 = ADSP2_LOCK_CODE_0; + code1 = ADSP2_LOCK_CODE_1; + } + if (lock_regions & BIT(1)) { + code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT; + code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT; + } + regmap_write(regmap, lock_reg, code0); + regmap_write(regmap, lock_reg, code1); + lock_regions >>= 2; + lock_reg += 2; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_lock); + +irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp) +{ + unsigned int val; + struct regmap *regmap = dsp->regmap; + int ret = 0; + + ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); + if (ret) { + adsp_err(dsp, "Failed to read Region Lock Ctrl register: %d\n", + ret); + return IRQ_HANDLED; + } + + if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { + adsp_err(dsp, "watchdog timeout error\n"); + wm_adsp_stop_watchdog(dsp); + } + + if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { + if (val & ADSP2_SLAVE_ERR_MASK) + adsp_err(dsp, "bus error: slave error\n"); + else + adsp_err(dsp, "bus error: region lock error\n"); + + ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); + if (ret) { + adsp_err(dsp, + "Failed to read Bus Err Addr register: %d\n", + ret); + return IRQ_HANDLED; + } + + adsp_err(dsp, "bus error address = 0x%x\n", + val & ADSP2_BUS_ERR_ADDR_MASK); + + ret = regmap_read(regmap, + dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + &val); + if (ret) { + adsp_err( + dsp, + "Failed to read Pmem Xmem Err Addr register: %d\n", + ret); + return IRQ_HANDLED; + } + + adsp_err(dsp, "xmem error address = 0x%x\n", + val & ADSP2_XMEM_ERR_ADDR_MASK); + adsp_err(dsp, "pmem error address = 0x%x\n", + (val & ADSP2_PMEM_ERR_ADDR_MASK) >> + ADSP2_PMEM_ERR_ADDR_SHIFT); + } + + regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, + ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_adsp2_bus_error); + +static void wm_halo_dump_fault_info(struct wm_adsp *dsp, const char *region, + unsigned int addr, unsigned int status) +{ + unsigned int write = status & HALO_MPU_VIO_ERR_WR_MASK; + unsigned int type = + (status & HALO_MPU_VIO_STS_MASK) >> HALO_MPU_VIO_STS_SHIFT; + unsigned int src = (status & HALO_MPU_VIO_ERR_SRC_MASK) >> + HALO_MPU_VIO_ERR_SRC_SHIFT; + + adsp_warn(dsp, "%s: FAULT_ADDR:0x%x FAULT_STATUS:0x%x %s\n", region, + addr, status, write ? "write" : "read"); + + switch (src) { + case 0: + adsp_warn(dsp, "%s: SRC=HALO\n", region); + break; + default: + adsp_warn(dsp, "%s: SRC=Requestor%u\n", region, src); + break; + } + + adsp_warn(dsp, "%s: %s %s %s %s %s %s\n", region, + type & HALO_MPU_VIO_SRAM ? "SRAM" : "", + type & HALO_MPU_VIO_REG ? "REG" : "", + type & HALO_MPU_VIO_AHB ? "AHB" : "", + type & HALO_MPU_VIO_EREG ? "EREG" : "", + type & HALO_MPU_VIO_EXTERNAL_MEM ? "ExtMem" : "", + type & HALO_MPU_VIO_NON_EXIST ? "NotExist" : ""); +} + +irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + unsigned int fault[6], ahb_sts, reg; + int ret; + + mutex_lock(&dsp->pwr_lock); + + /* Ensure we log the fault even if we fail to read the fault info */ + adsp_warn(dsp, "MPU FAULT\n"); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, + &ahb_sts); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_1 (%d)\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB WINDOW: ADDR: 0x%x STATUS: 0x%x\n", + (ahb_sts & HALO_AHBM_CORE_ERR_ADDR_MASK) >> + HALO_AHBM_CORE_ERR_ADDR_SHIFT, + ahb_sts); + adsp_warn(dsp, "AHB WINDOW: %s %s %s %s\n", + (ahb_sts & HALO_AHBM_ADDR_ERR_MASK) ? "ADDR" : "", + (ahb_sts & HALO_AHBM_LOCKED_ERR_MASK) ? "LOCKED" : "", + (ahb_sts & HALO_AHBM_SIZE_ERR_MASK) ? "SIZE" : "", + (ahb_sts & HALO_AHBM_MODE_ERR_MASK) ? "MODE" : ""); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, + &ahb_sts); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_0 (%d)\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB SYS_ADDR: 0x%x\n", ahb_sts); + + ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, fault, + ARRAY_SIZE(fault)); + if (ret) { + adsp_warn(dsp, "Failed to read MPU fault info (%d)\n", ret); + goto exit_unlock; + } + + wm_halo_dump_fault_info(dsp, "XM", fault[0], fault[1]); + wm_halo_dump_fault_info(dsp, "YM", fault[2], fault[3]); + wm_halo_dump_fault_info(dsp, "PM", fault[4], fault[5]); + + /* Clear fault status */ + for (reg = HALO_MPU_XM_VIO_STATUS; reg <= HALO_MPU_PM_VIO_STATUS; + reg += 8) { + ret = regmap_write(regmap, dsp->base + reg, 0); + if (ret) + adsp_warn(dsp, + "Failed to clear MPU status @0x%x (%d)\n", + reg, ret); + } + +exit_unlock: + mutex_unlock(&dsp->pwr_lock); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_halo_bus_error); + +MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/cs35l41/wm_adsp.h b/techpack/audio/asoc/codecs/cs35l41/wm_adsp.h new file mode 100644 index 000000000000..6c58e4767817 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/wm_adsp.h @@ -0,0 +1,208 @@ +/* + * wm_adsp.h -- Wolfson ADSP support + * + * Copyright 2012 Wolfson Microelectronics plc + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __WM_ADSP_H +#define __WM_ADSP_H + +#include +#include +#include + +#include "wmfw.h" + +/* Return values for wm_adsp_compr_handle_irq */ +#define WM_ADSP_COMPR_OK 0 +#define WM_ADSP_COMPR_VOICE_TRIGGER 1 + +#define WM_ADSP2_REGION_0 BIT(0) +#define WM_ADSP2_REGION_1 BIT(1) +#define WM_ADSP2_REGION_2 BIT(2) +#define WM_ADSP2_REGION_3 BIT(3) +#define WM_ADSP2_REGION_4 BIT(4) +#define WM_ADSP2_REGION_5 BIT(5) +#define WM_ADSP2_REGION_6 BIT(6) +#define WM_ADSP2_REGION_7 BIT(7) +#define WM_ADSP2_REGION_8 BIT(8) +#define WM_ADSP2_REGION_9 BIT(9) +#define WM_ADSP2_REGION_1_9 \ + (WM_ADSP2_REGION_1 | WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \ + WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | WM_ADSP2_REGION_6 | \ + WM_ADSP2_REGION_7 | WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9) +#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9) + +struct wm_adsp_region { + int type; + unsigned int base; +}; + +struct wm_adsp_alg_region { + struct list_head list; + unsigned int alg; + int type; + unsigned int base; +}; + +struct wm_adsp_compr; +struct wm_adsp_compr_buf; + +struct wm_adsp { + const char *part; + int rev; + int num; + int type; + struct device *dev; + struct regmap *regmap; + struct snd_soc_codec *codec; + int cal_z; + int ambient; + int cal_status; + int cal_chksum; + int block_bypass; + int block_bypass_in_enh; + int base; + int base_sysinfo; + int sysclk_reg; + int sysclk_mask; + int sysclk_shift; + + struct list_head alg_regions; + + unsigned int fw_id; + unsigned int fw_id_version; + unsigned int fw_vendor_id; + + const struct wm_adsp_region *mem; + int num_mems; + + int fw; + int fw_ver; + + bool preloaded; + bool booted; + bool running; + + struct list_head ctl_list; + + struct work_struct boot_work; + + struct wm_adsp_compr *compr; + struct wm_adsp_compr_buf *buffer; + + struct mutex pwr_lock; + + unsigned int lock_regions; + bool unlock_all; + + unsigned int n_rx_rates; + unsigned int n_tx_rates; + + u8 *rx_rate_cache; + u8 *tx_rate_cache; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; + char *wmfw_file_name; + char *bin_file_name; +#endif +}; + +#define WM_ADSP1(wname, num) \ + SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, num, 0, NULL, 0, \ + wm_adsp1_event, \ + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD) + +#define WM_ADSP2_PRELOAD_SWITCH(wname, num) \ + SOC_SINGLE_EXT(wname " Preload Switch", SND_SOC_NOPM, num, 1, 0, \ + wm_adsp2_preloader_get, wm_adsp2_preloader_put) + +#define WM_ADSP2(wname, num, event_fn) \ + SND_SOC_DAPM_SPK(wname " Preload", NULL), \ + { .id = snd_soc_dapm_supply, \ + .name = wname " Preloader", \ + .reg = SND_SOC_NOPM, \ + .shift = num, \ + .event = event_fn, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \ + .subseq = 100, \ + /* Ensure we run after SYSCLK supply widget */ }, \ + { \ + .id = snd_soc_dapm_out_drv, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp2_event, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD \ + } + +#define WM_HALO(wname, num, event_fn) \ + SND_SOC_DAPM_SPK(wname " Preload", NULL), \ + { .id = snd_soc_dapm_supply, \ + .name = wname " Preloader", \ + .reg = SND_SOC_NOPM, \ + .shift = num, \ + .event = event_fn, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \ + .subseq = 100, \ + /* Ensure we run after SYSCLK supply widget */ }, \ + { \ + .id = snd_soc_dapm_out_drv, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = num, .event = wm_halo_event, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD \ + } + +extern const struct snd_kcontrol_new wm_adsp_fw_controls[]; + +int wm_adsp1_init(struct wm_adsp *dsp); +int wm_adsp2_init(struct wm_adsp *dsp); +void wm_adsp2_remove(struct wm_adsp *dsp); +int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec); +int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec); +int wm_halo_init(struct wm_adsp *dsp); +int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event); + +int wm_halo_set_clocking(struct wm_adsp *dsp, unsigned int freq, + struct mutex *rate_lock); + +int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event, + unsigned int freq); + +int wm_adsp2_lock(struct wm_adsp *adsp, unsigned int regions); +irqreturn_t wm_adsp2_bus_error(struct wm_adsp *adsp); +irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp); + +int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event); + +int wm_halo_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +int wm_halo_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event); + +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream); +int wm_adsp_compr_free(struct snd_compr_stream *stream); +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params); +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps); +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd); +int wm_adsp_compr_handle_irq(struct wm_adsp *dsp); +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp); +int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf, + size_t count); + +#endif diff --git a/techpack/audio/asoc/codecs/cs35l41/wmfw.h b/techpack/audio/asoc/codecs/cs35l41/wmfw.h new file mode 100644 index 000000000000..0a7c62e7107b --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41/wmfw.h @@ -0,0 +1,202 @@ +/* + * wmfw.h - Wolfson firmware format information + * + * Copyright 2012 Wolfson Microelectronics plc + * Copyright (C) 2019 XiaoMi, Inc. + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __WMFW_H +#define __WMFW_H + +#include + +#define WMFW_MAX_ALG_NAME 256 +#define WMFW_MAX_ALG_DESCR_NAME 256 + +#define WMFW_MAX_COEFF_NAME 256 +#define WMFW_MAX_COEFF_DESCR_NAME 256 + +#define WMFW_CTL_FLAG_SYS 0x8000 +#define WMFW_CTL_FLAG_VOLATILE 0x0004 +#define WMFW_CTL_FLAG_WRITEABLE 0x0002 +#define WMFW_CTL_FLAG_READABLE 0x0001 + +/* Non-ALSA coefficient types start at 0x1000 */ +#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */ +#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */ + +struct wmfw_header { + char magic[4]; + __le32 len; + __le16 rev; + u8 core; + u8 ver; +} __packed; + +struct wmfw_footer { + __le64 timestamp; + __le32 checksum; +} __packed; + +struct wmfw_adsp1_sizes { + __le32 dm; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_adsp2_sizes { + __le32 xm; + __le32 ym; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_region { + union { + __be32 type; + __le32 offset; + }; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_id_hdr { + __be32 core_id; + __be32 core_rev; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 dm; + __be32 n_algs; +} __packed; + +struct wmfw_adsp2_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 xm; + __be32 ym; + __be32 n_algs; +} __packed; + +struct wmfw_halo_fwid_hdr { + __be32 core_id; + __be32 block_rev; + __be32 vendor_id; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_halo_id_hdr { + struct wmfw_halo_fwid_hdr fw; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; + __be32 n_algs; +} __packed; + +struct wmfw_alg_hdr { + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 dm; +} __packed; + +struct wmfw_adsp2_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 xm; + __be32 ym; +} __packed; + +struct wmfw_halo_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; +} __packed; + +struct wmfw_adsp_alg_data { + __le32 id; + u8 name[WMFW_MAX_ALG_NAME]; + u8 descr[WMFW_MAX_ALG_DESCR_NAME]; + __le32 ncoeff; + u8 data[]; +} __packed; + +struct wmfw_adsp_coeff_data { + struct { + __le16 offset; + __le16 type; + __le32 size; + } hdr; + u8 name[WMFW_MAX_COEFF_NAME]; + u8 descr[WMFW_MAX_COEFF_DESCR_NAME]; + __le16 ctl_type; + __le16 flags; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_coeff_hdr { + u8 magic[4]; + __le32 len; + union { + __be32 rev; + __le32 ver; + }; + union { + __be32 core; + __le32 core_ver; + }; + u8 data[]; +} __packed; + +struct wmfw_coeff_item { + __le16 offset; + __le16 type; + __le32 id; + __le32 ver; + __le32 sr; + __le32 len; + u8 data[]; +} __packed; + +#define WMFW_ADSP1 1 +#define WMFW_ADSP2 2 +#define WMFW_HALO 4 + +#define WMFW_ABSOLUTE 0xf0 +#define WMFW_ALGORITHM_DATA 0xf2 +#define WMFW_NAME_TEXT 0xfe +#define WMFW_INFO_TEXT 0xff + +#define WMFW_ADSP1_PM 2 +#define WMFW_ADSP1_DM 3 +#define WMFW_ADSP1_ZM 4 + +#define WMFW_ADSP2_PM 2 +#define WMFW_ADSP2_ZM 4 +#define WMFW_ADSP2_XM 5 +#define WMFW_ADSP2_YM 6 + +#define WMFW_HALO_PM_PACKED 0x10 +#define WMFW_HALO_XM_PACKED 0x11 +#define WMFW_HALO_YM_PACKED 0x12 + +#endif diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/Android.mk b/techpack/audio/asoc/codecs/cs35l41_v2/Android.mk new file mode 100755 index 000000000000..9b2b116f0487 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/Android.mk @@ -0,0 +1,55 @@ +# Android makefile for audio kernel modules + +# Assume no targets will be supported + +# Check if this driver needs be built for current target +ifeq ($(call is-board-platform,msmnile),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m +endif + +ifeq ($(call is-board-platform,$(MSMSTEPPE)),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m +endif + +AUDIO_CHIPSET := audio +# Build/Package only in case of supported target +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE)),true) + +LOCAL_PATH := $(call my-dir) + +# This makefile is only for DLKM +ifneq ($(findstring vendor,$(LOCAL_PATH)),) + +ifneq ($(findstring opensource,$(LOCAL_PATH)),) + #AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/vendor/qcom/opensource/audio-kernel + AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel +endif # opensource + +DLKM_DIR := $(TOP)/device/qcom/common/dlkm + +# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko +########################################################### +# This is set once per LOCAL_PATH, not per (kernel) module +KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR) + +# We are actually building audio.ko here, as per the +# requirement we are specifying _audio.ko as LOCAL_MODULE. +# This means we need to rename the module to _audio.ko +# after audio.ko is built. +KBUILD_OPTIONS += MODNAME=cs35l41_dlkm +KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM) +KBUILD_OPTIONS += $(AUDIO_SELECT) + +########################################################### +include $(CLEAR_VARS) +LOCAL_MODULE := $(AUDIO_CHIPSET)_cs35l41.ko +LOCAL_MODULE_KBUILD_NAME := cs35l41_dlkm.ko +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +include $(DLKM_DIR)/AndroidKernelModule.mk +########################################################### +########################################################### + +endif # DLKM check +endif # supported target check diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/Kbuild b/techpack/audio/asoc/codecs/cs35l41_v2/Kbuild new file mode 100755 index 000000000000..2d57817c1d12 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/Kbuild @@ -0,0 +1,125 @@ +# We can build either as part of a standalone Kernel build or as +# an external module. Determine which mechanism is being used +ifeq ($(MODNAME),) + KERNEL_BUILD := 1 +else + KERNEL_BUILD := 0 +endif + + + +ifeq ($(KERNEL_BUILD), 1) + # These are configurable via Kconfig for kernel-based builds + # Need to explicitly configure for Android-based builds + AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.19 + AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio +endif + +ifeq ($(KERNEL_BUILD), 0) + ifeq ($(CONFIG_ARCH_SM8150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + ifeq ($(CONFIG_ARCH_SM6150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + + ifeq ($(CONFIG_ARCH_KONA), y) + include $(AUDIO_ROOT)/config/konaauto.conf + INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h + endif + + ifeq ($(CONFIG_ARCH_LITO), y) + include $(AUDIO_ROOT)/config/litoauto.conf + export + INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h + endif + + ifeq ($(CONFIG_ARCH_SDMSHRIKE), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif +endif + +# As per target team, build is done as follows: +# Defconfig : build with default flags +# Slub : defconfig + CONFIG_SLUB_DEBUG := y + +# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y +# Perf : Using appropriate msmXXXX-perf_defconfig +# +# Shipment builds (user variants) should not have any debug feature +# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds +# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since +# there is no other way to identify defconfig builds, QTI internal +# representation of perf builds (identified using the string 'perf'), +# is used to identify if the build is a slub or defconfig one. This +# way no critical debug feature will be enabled for perf and shipment +# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT +# config. + +############ UAPI ############ +UAPI_DIR := uapi +UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR) + +############ COMMON ############ +COMMON_DIR := include +COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR) + +############ CS35L41 ############ + +# for CS35L41 Codec +ifdef CONFIG_SND_SOC_CS35L41_V2 + CS35L41_V2_OBJS += cs35l41.o + CS35L41_V2_OBJS += cs35l41-i2c.o + CS35L41_V2_OBJS += cs35l41-tables.o + CS35L41_V2_OBJS += wm_adsp.o + #CS35L41_V2_OBJS += send_data_to_xlog.o +endif + +LINUX_INC += -Iinclude/linux + +INCS += $(COMMON_INC) \ + $(UAPI_INC) + +EXTRA_CFLAGS += $(INCS) + +CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ + -DANI_LITTLE_BIT_ENDIAN \ + -DDOT11F_LITTLE_ENDIAN_HOST \ + -DANI_COMPILER_TYPE_GCC \ + -DANI_OS_TYPE_ANDROID=6 \ + -DPTT_SOCK_SVC_ENABLE \ + -Wall\ + -Werror\ + -D__linux__ + +KBUILD_CPPFLAGS += $(CDEFINES) + +# Currently, for versions of gcc which support it, the kernel Makefile +# is disabling the maybe-uninitialized warning. Re-enable it for the +# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it +# will override the kernel settings. +ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y) +EXTRA_CFLAGS += -Wmaybe-uninitialized +endif +#EXTRA_CFLAGS += -Wmissing-prototypes + +ifeq ($(call cc-option-yn, -Wheader-guard),y) +EXTRA_CFLAGS += -Wheader-guard +endif + +ifeq ($(KERNEL_BUILD), 0) +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers +endif + +# Module information used by KBuild framework +obj-$(CONFIG_SND_SOC_CS35L41_V2) += cs35l41_v2_dlkm.o +cs35l41_v2_dlkm-y := $(CS35L41_V2_OBJS) diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/Kconfig b/techpack/audio/asoc/codecs/cs35l41_v2/Kconfig new file mode 100755 index 000000000000..62fc5be2bc16 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/Kconfig @@ -0,0 +1,5 @@ +config SND_SOC_CS35L41_V2 + tristate "Cirrus Logic CS35L41 codec" + help + Say Y or M here if you want to add support for the Cirrus Logic + CS35L41 codec. diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-i2c.c b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-i2c.c new file mode 100644 index 000000000000..ac959e8da733 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-i2c.c @@ -0,0 +1,121 @@ +/* + * cs35l41-i2c.c -- CS35l41 I2C driver + * + * Copyright 2017 Cirrus Logic, Inc. + * + * Author: David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l41.h" +#include + +static struct regmap_config cs35l41_regmap_i2c = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + .max_register = CS35L41_LASTREG, + .reg_defaults = cs35l41_reg, + .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), + .volatile_reg = cs35l41_volatile_reg, + .readable_reg = cs35l41_readable_reg, + .precious_reg = cs35l41_precious_reg, + .cache_type = REGCACHE_RBTREE, +}; + +static const struct i2c_device_id cs35l41_id_i2c[] = { + { "cs35l40", 0 }, + { "cs35l41", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, cs35l41_id_i2c); + +static int cs35l41_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct cs35l41_private *cs35l41; + struct device *dev = &client->dev; + struct cs35l41_platform_data *pdata = dev_get_platdata(dev); + const struct regmap_config *regmap_config = &cs35l41_regmap_i2c; + int ret; + + dev_info(dev, "ZL: cs35l41 i2c probe start\n"); + + cs35l41 = devm_kzalloc(dev, sizeof(struct cs35l41_private), GFP_KERNEL); + + if (cs35l41 == NULL) + return -ENOMEM; + + mutex_init(&cs35l41->rate_lock); + + cs35l41->dev = dev; + cs35l41->irq = client->irq; + cs35l41->bus_spi = false; + + i2c_set_clientdata(client, cs35l41); + cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config); + if (IS_ERR(cs35l41->regmap)) { + ret = PTR_ERR(cs35l41->regmap); + dev_err(cs35l41->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + dev_info(dev, "ZL: before cs35l41 probe\n"); + + return cs35l41_probe(cs35l41, pdata); +} + +static int cs35l41_i2c_remove(struct i2c_client *client) +{ + struct cs35l41_private *cs35l41 = i2c_get_clientdata(client); + + return cs35l41_remove(cs35l41); +} + +static const struct of_device_id cs35l41_of_match[] = { + { .compatible = "cirrus,cs35l40" }, + { .compatible = "cirrus,cs35l41" }, + {}, +}; +MODULE_DEVICE_TABLE(of, cs35l41_of_match); + +static struct i2c_driver cs35l41_i2c_driver = { + .driver = { + .name = "cs35l41", + .of_match_table = cs35l41_of_match, + }, + .id_table = cs35l41_id_i2c, + .probe = cs35l41_i2c_probe, + .remove = cs35l41_i2c_remove, +}; + +module_i2c_driver(cs35l41_i2c_driver); + +MODULE_DESCRIPTION("I2C CS35L41 driver"); +MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-spi.c b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-spi.c new file mode 100644 index 000000000000..54a104cdb777 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-spi.c @@ -0,0 +1,112 @@ +/* + * cs35l41-spi.c -- CS35l41 SPI driver + * + * Copyright 2017 Cirrus Logic, Inc. + * + * Author: David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l41.h" +#include + +static struct regmap_config cs35l41_regmap_spi = { + .reg_bits = 32, + .val_bits = 32, + .pad_bits = 16, + .reg_stride = 4, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, + .max_register = CS35L41_LASTREG, + .reg_defaults = cs35l41_reg, + .num_reg_defaults = ARRAY_SIZE(cs35l41_reg), + .volatile_reg = cs35l41_volatile_reg, + .readable_reg = cs35l41_readable_reg, + .precious_reg = cs35l41_precious_reg, + .cache_type = REGCACHE_RBTREE, +}; + +static const struct spi_device_id cs35l41_id_spi[] = { + { "cs35l40", 0 }, + { "cs35l41", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(spi, cs35l41_id_spi); + +static int cs35l41_spi_probe(struct spi_device *spi) +{ + const struct regmap_config *regmap_config = &cs35l41_regmap_spi; + struct cs35l41_platform_data *pdata = dev_get_platdata(&spi->dev); + struct cs35l41_private *cs35l41; + int ret; + + cs35l41 = devm_kzalloc(&spi->dev, sizeof(struct cs35l41_private), + GFP_KERNEL); + if (cs35l41 == NULL) + return -ENOMEM; + + mutex_init(&cs35l41->rate_lock); + + spi_set_drvdata(spi, cs35l41); + cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config); + if (IS_ERR(cs35l41->regmap)) { + ret = PTR_ERR(cs35l41->regmap); + dev_err(&spi->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + cs35l41->dev = &spi->dev; + cs35l41->irq = spi->irq; + cs35l41->bus_spi = true; + + return cs35l41_probe(cs35l41, pdata); +} + +static int cs35l41_spi_remove(struct spi_device *spi) +{ + struct cs35l41_private *cs35l41 = spi_get_drvdata(spi); + + return cs35l41_remove(cs35l41); +} + +static const struct of_device_id cs35l41_of_match[] = { + { .compatible = "cirrus,cs35l40" }, + { .compatible = "cirrus,cs35l41" }, + {}, +}; +MODULE_DEVICE_TABLE(of, cs35l41_of_match); + +static struct spi_driver cs35l41_spi_driver = { + .driver = { + .name = "cs35l41", + .of_match_table = cs35l41_of_match, + }, + .id_table = cs35l41_id_spi, + .probe = cs35l41_spi_probe, + .remove = cs35l41_spi_remove, +}; + +module_spi_driver(cs35l41_spi_driver); + +MODULE_DESCRIPTION("SPI CS35L41 driver"); +MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-tables.c b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-tables.c new file mode 100644 index 000000000000..5560bae7a209 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41-tables.c @@ -0,0 +1,997 @@ +/* + * cs35l41-tables.c -- CS35L41 ALSA SoC audio driver + * + * Copyright 2018 Cirrus Logic, Inc. + * + * Author: Brian Austin + * David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include "cs35l41.h" + +const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = { + { CS35L41_TEST_KEY_CTL, 0x00000000 }, + { CS35L41_USER_KEY_CTL, 0x00000000 }, + { CS35L41_OTP_CTRL0, 0x00006418 }, + { CS35L41_OTP_CTRL1, 0x00000000 }, + { CS35L41_OTP_CTRL3, 0x00000000 }, + { CS35L41_OTP_CTRL4, 0x00000000 }, + { CS35L41_OTP_CTRL5, 0x00000030 }, + { CS35L41_OTP_CTRL6, 0x00000000 }, + { CS35L41_OTP_CTRL7, 0x00000000 }, + { CS35L41_OTP_CTRL8, 0x00000000 }, + { CS35L41_PWR_CTRL1, 0x00000000 }, + { CS35L41_PWR_CTRL3, 0x01000010 }, + { CS35L41_CTRL_OVRRIDE, 0x00000002 }, + { CS35L41_AMP_OUT_MUTE, 0x00000000 }, + { CS35L41_PROTECT_REL_ERR_IGN, 0x00000000 }, + { CS35L41_GPIO_PAD_CONTROL, 0x00000000 }, + { CS35L41_JTAG_CONTROL, 0x00000000 }, + { CS35L41_PLL_CLK_CTRL, 0x00000010 }, + { CS35L41_DSP_CLK_CTRL, 0x00000003 }, + { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, + { CS35L41_DATA_FS_SEL, 0x00000000 }, + { CS35L41_MDSYNC_EN, 0x00000200 }, + { CS35L41_MDSYNC_TX_ID, 0x00000000 }, + { CS35L41_MDSYNC_PWR_CTRL, 0x00000002 }, + { CS35L41_MDSYNC_DATA_TX, 0x00000000 }, + { CS35L41_MDSYNC_TX_STATUS, 0x00000002 }, + { CS35L41_MDSYNC_DATA_RX, 0x00000000 }, + { CS35L41_MDSYNC_RX_STATUS, 0x00000002 }, + { CS35L41_MDSYNC_ERR_STATUS, 0x00000000 }, + { CS35L41_MDSYNC_SYNC_PTE2, 0x00000000 }, + { CS35L41_MDSYNC_SYNC_PTE3, 0x00000000 }, + { CS35L41_MDSYNC_SYNC_MSM_STATUS, 0x00000000 }, + { CS35L41_BSTCVRT_VCTRL1, 0x00000000 }, + { CS35L41_BSTCVRT_VCTRL2, 0x00000001 }, + { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A }, + { CS35L41_BSTCVRT_SFT_RAMP, 0x00000003 }, + { CS35L41_BSTCVRT_COEFF, 0x00002424 }, + { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 }, + { CS35L41_BSTCVRT_SW_FREQ, 0x01008000 }, + { CS35L41_BSTCVRT_DCM_CTRL, 0x00002001 }, + { CS35L41_BSTCVRT_DCM_MODE_FORCE, 0x00000000 }, + { CS35L41_BSTCVRT_OVERVOLT_CTRL, 0x00000130 }, + { CS35L41_VI_VOL_POL, 0x08000800 }, + { CS35L41_DTEMP_WARN_THLD, 0x00000002 }, + { CS35L41_DTEMP_EN, 0x00000000 }, + { CS35L41_VPVBST_FS_SEL, 0x00000001 }, + { CS35L41_SP_ENABLES, 0x00000000 }, + { CS35L41_SP_RATE_CTRL, 0x00000028 }, + { CS35L41_SP_FORMAT, 0x18180200 }, + { CS35L41_SP_HIZ_CTRL, 0x00000002 }, + { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 }, + { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 }, + { CS35L41_SP_TX_WL, 0x00000018 }, + { CS35L41_SP_RX_WL, 0x00000018 }, + { CS35L41_DAC_PCM1_SRC, 0x00000008 }, + { CS35L41_ASP_TX1_SRC, 0x00000018 }, + { CS35L41_ASP_TX2_SRC, 0x00000019 }, + { CS35L41_ASP_TX3_SRC, 0x00000020 }, + { CS35L41_ASP_TX4_SRC, 0x00000021 }, + { CS35L41_DSP1_RX1_SRC, 0x00000008 }, + { CS35L41_DSP1_RX2_SRC, 0x00000009 }, + { CS35L41_DSP1_RX3_SRC, 0x00000018 }, + { CS35L41_DSP1_RX4_SRC, 0x00000019 }, + { CS35L41_DSP1_RX5_SRC, 0x00000020 }, + { CS35L41_DSP1_RX6_SRC, 0x00000021 }, + { CS35L41_DSP1_RX7_SRC, 0x0000003A }, + { CS35L41_DSP1_RX8_SRC, 0x00000001 }, + { CS35L41_NGATE1_SRC, 0x00000008 }, + { CS35L41_NGATE2_SRC, 0x00000009 }, + { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 }, + { CS35L41_VPBR_CFG, 0x02AA1905 }, + { CS35L41_VBBR_CFG, 0x02AA1905 }, + { CS35L41_VPBR_STATUS, 0x00000000 }, + { CS35L41_VBBR_STATUS, 0x00000000 }, + { CS35L41_OVERTEMP_CFG, 0x00000001 }, + { CS35L41_AMP_ERR_VOL, 0x00000000 }, + { CS35L41_VOL_STATUS_TO_DSP, 0x00000000 }, + { CS35L41_CLASSH_CFG, 0x000B0405 }, + { CS35L41_WKFET_CFG, 0x00000111 }, + { CS35L41_NG_CFG, 0x00000033 }, + { CS35L41_AMP_GAIN_CTRL, 0x00000273 }, + { CS35L41_DAC_MSM_CFG, 0x00580000 }, + { CS35L41_GPIO1_CTRL1, 0xE1000001 }, + { CS35L41_GPIO2_CTRL1, 0xE1000001 }, + { CS35L41_MIXER_NGATE_CFG, 0x00000000 }, + { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 }, + { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 }, + { CS35L41_CLOCK_DETECT_1, 0x00000000 }, + { CS35L41_TIMER1_CONTROL, 0x00000000 }, + { CS35L41_TIMER1_COUNT_PRESET, 0x00000000 }, + { CS35L41_TIMER1_START_STOP, 0x00000000 }, + { CS35L41_TIMER1_STATUS, 0x00000000 }, + { CS35L41_TIMER1_COUNT_READBACK, 0x00000000 }, + { CS35L41_TIMER1_DSP_CLK_CFG, 0x00000000 }, + { CS35L41_TIMER1_DSP_CLK_STATUS, 0x00000000 }, + { CS35L41_TIMER2_CONTROL, 0x00000000 }, + { CS35L41_TIMER2_COUNT_PRESET, 0x00000000 }, + { CS35L41_TIMER2_START_STOP, 0x00000000 }, + { CS35L41_TIMER2_STATUS, 0x00000000 }, + { CS35L41_TIMER2_COUNT_READBACK, 0x00000000 }, + { CS35L41_TIMER2_DSP_CLK_CFG, 0x00000000 }, + { CS35L41_TIMER2_DSP_CLK_STATUS, 0x00000000 }, + { CS35L41_DFT_JTAG_CONTROL, 0x00000000 }, + { CS35L41_DIE_STS1, 0x00000000 }, + { CS35L41_DIE_STS2, 0x00000000 }, + { CS35L41_TEMP_CAL1, 0x00000000 }, + { CS35L41_TEMP_CAL2, 0x00000000 }, +}; + +bool cs35l41_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L41_DEVID: + case CS35L41_REVID: + case CS35L41_FABID: + case CS35L41_RELID: + case CS35L41_OTPID: + case CS35L41_TEST_KEY_CTL: + case CS35L41_USER_KEY_CTL: + case CS35L41_OTP_CTRL0: + case CS35L41_OTP_CTRL3: + case CS35L41_OTP_CTRL4: + case CS35L41_OTP_CTRL5: + case CS35L41_OTP_CTRL6: + case CS35L41_OTP_CTRL7: + case CS35L41_OTP_CTRL8: + case CS35L41_PWR_CTRL1: + case CS35L41_PWR_CTRL2: + case CS35L41_PWR_CTRL3: + case CS35L41_CTRL_OVRRIDE: + case CS35L41_AMP_OUT_MUTE: + case CS35L41_PROTECT_REL_ERR_IGN: + case CS35L41_GPIO_PAD_CONTROL: + case CS35L41_JTAG_CONTROL: + case CS35L41_DEVID_OTP: + case CS35L41_PLL_CLK_CTRL: + case CS35L41_DSP_CLK_CTRL: + case CS35L41_GLOBAL_CLK_CTRL: + case CS35L41_DATA_FS_SEL: + case CS35L41_MDSYNC_EN: + case CS35L41_MDSYNC_TX_ID: + case CS35L41_MDSYNC_PWR_CTRL: + case CS35L41_MDSYNC_DATA_TX: + case CS35L41_MDSYNC_TX_STATUS: + case CS35L41_MDSYNC_DATA_RX: + case CS35L41_MDSYNC_RX_STATUS: + case CS35L41_MDSYNC_ERR_STATUS: + case CS35L41_MDSYNC_SYNC_PTE2: + case CS35L41_MDSYNC_SYNC_PTE3: + case CS35L41_MDSYNC_SYNC_MSM_STATUS: + case CS35L41_BSTCVRT_VCTRL1: + case CS35L41_BSTCVRT_VCTRL2: + case CS35L41_BSTCVRT_PEAK_CUR: + case CS35L41_BSTCVRT_SFT_RAMP: + case CS35L41_BSTCVRT_COEFF: + case CS35L41_BSTCVRT_SLOPE_LBST: + case CS35L41_BSTCVRT_SW_FREQ: + case CS35L41_BSTCVRT_DCM_CTRL: + case CS35L41_BSTCVRT_DCM_MODE_FORCE: + case CS35L41_BSTCVRT_OVERVOLT_CTRL: + case CS35L41_VI_VOL_POL: + case CS35L41_DTEMP_WARN_THLD: + case CS35L41_DTEMP_CFG: + case CS35L41_DTEMP_EN: + case CS35L41_VPVBST_FS_SEL: + case CS35L41_SP_ENABLES: + case CS35L41_SP_RATE_CTRL: + case CS35L41_SP_FORMAT: + case CS35L41_SP_HIZ_CTRL: + case CS35L41_SP_FRAME_TX_SLOT: + case CS35L41_SP_FRAME_RX_SLOT: + case CS35L41_SP_TX_WL: + case CS35L41_SP_RX_WL: + case CS35L41_DAC_PCM1_SRC: + case CS35L41_ASP_TX1_SRC: + case CS35L41_ASP_TX2_SRC: + case CS35L41_ASP_TX3_SRC: + case CS35L41_ASP_TX4_SRC: + case CS35L41_DSP1_RX1_SRC: + case CS35L41_DSP1_RX2_SRC: + case CS35L41_DSP1_RX3_SRC: + case CS35L41_DSP1_RX4_SRC: + case CS35L41_DSP1_RX5_SRC: + case CS35L41_DSP1_RX6_SRC: + case CS35L41_DSP1_RX7_SRC: + case CS35L41_DSP1_RX8_SRC: + case CS35L41_NGATE1_SRC: + case CS35L41_NGATE2_SRC: + case CS35L41_AMP_DIG_VOL_CTRL: + case CS35L41_VPBR_CFG: + case CS35L41_VBBR_CFG: + case CS35L41_VPBR_STATUS: + case CS35L41_VBBR_STATUS: + case CS35L41_OVERTEMP_CFG: + case CS35L41_AMP_ERR_VOL: + case CS35L41_VOL_STATUS_TO_DSP: + case CS35L41_CLASSH_CFG: + case CS35L41_WKFET_CFG: + case CS35L41_NG_CFG: + case CS35L41_AMP_GAIN_CTRL: + case CS35L41_DAC_MSM_CFG: + case CS35L41_IRQ1_CFG: + case CS35L41_IRQ1_STATUS: + case CS35L41_IRQ1_STATUS1: + case CS35L41_IRQ1_STATUS2: + case CS35L41_IRQ1_STATUS3: + case CS35L41_IRQ1_STATUS4: + case CS35L41_IRQ1_RAW_STATUS1: + case CS35L41_IRQ1_RAW_STATUS2: + case CS35L41_IRQ1_RAW_STATUS3: + case CS35L41_IRQ1_RAW_STATUS4: + case CS35L41_IRQ1_MASK1: + case CS35L41_IRQ1_MASK2: + case CS35L41_IRQ1_MASK3: + case CS35L41_IRQ1_MASK4: + case CS35L41_IRQ1_FRC1: + case CS35L41_IRQ1_FRC2: + case CS35L41_IRQ1_FRC3: + case CS35L41_IRQ1_FRC4: + case CS35L41_IRQ1_EDGE1: + case CS35L41_IRQ1_EDGE4: + case CS35L41_IRQ1_POL1: + case CS35L41_IRQ1_POL2: + case CS35L41_IRQ1_POL3: + case CS35L41_IRQ1_POL4: + case CS35L41_IRQ1_DB3: + case CS35L41_IRQ2_CFG: + case CS35L41_IRQ2_STATUS: + case CS35L41_IRQ2_STATUS1: + case CS35L41_IRQ2_STATUS2: + case CS35L41_IRQ2_STATUS3: + case CS35L41_IRQ2_STATUS4: + case CS35L41_IRQ2_RAW_STATUS1: + case CS35L41_IRQ2_RAW_STATUS2: + case CS35L41_IRQ2_RAW_STATUS3: + case CS35L41_IRQ2_RAW_STATUS4: + case CS35L41_IRQ2_MASK1: + case CS35L41_IRQ2_MASK2: + case CS35L41_IRQ2_MASK3: + case CS35L41_IRQ2_MASK4: + case CS35L41_IRQ2_FRC1: + case CS35L41_IRQ2_FRC2: + case CS35L41_IRQ2_FRC3: + case CS35L41_IRQ2_FRC4: + case CS35L41_IRQ2_EDGE1: + case CS35L41_IRQ2_EDGE4: + case CS35L41_IRQ2_POL1: + case CS35L41_IRQ2_POL2: + case CS35L41_IRQ2_POL3: + case CS35L41_IRQ2_POL4: + case CS35L41_IRQ2_DB3: + case CS35L41_GPIO_STATUS1: + case CS35L41_GPIO1_CTRL1: + case CS35L41_GPIO2_CTRL1: + case CS35L41_MIXER_NGATE_CFG: + case CS35L41_MIXER_NGATE_CH1_CFG: + case CS35L41_MIXER_NGATE_CH2_CFG: + case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: + case CS35L41_CLOCK_DETECT_1: + case CS35L41_TIMER1_CONTROL: + case CS35L41_TIMER1_COUNT_PRESET: + case CS35L41_TIMER1_STATUS: + case CS35L41_TIMER1_COUNT_READBACK: + case CS35L41_TIMER1_DSP_CLK_CFG: + case CS35L41_TIMER1_DSP_CLK_STATUS: + case CS35L41_TIMER2_CONTROL: + case CS35L41_TIMER2_COUNT_PRESET: + case CS35L41_TIMER2_STATUS: + case CS35L41_TIMER2_COUNT_READBACK: + case CS35L41_TIMER2_DSP_CLK_CFG: + case CS35L41_TIMER2_DSP_CLK_STATUS: + case CS35L41_DFT_JTAG_CONTROL: + case CS35L41_DIE_STS1: + case CS35L41_DIE_STS2: + case CS35L41_TEMP_CAL1: + case CS35L41_TEMP_CAL2: + case CS35L41_DSP1_TIMESTAMP_COUNT: + case CS35L41_DSP1_SYS_ID: + case CS35L41_DSP1_SYS_VERSION: + case CS35L41_DSP1_SYS_CORE_ID: + case CS35L41_DSP1_SYS_AHB_ADDR: + case CS35L41_DSP1_SYS_XSRAM_SIZE: + case CS35L41_DSP1_SYS_YSRAM_SIZE: + case CS35L41_DSP1_SYS_PSRAM_SIZE: + case CS35L41_DSP1_SYS_PM_BOOT_SIZE: + case CS35L41_DSP1_SYS_FEATURES: + case CS35L41_DSP1_SYS_FIR_FILTERS: + case CS35L41_DSP1_SYS_LMS_FILTERS: + case CS35L41_DSP1_SYS_XM_BANK_SIZE: + case CS35L41_DSP1_SYS_YM_BANK_SIZE: + case CS35L41_DSP1_SYS_PM_BANK_SIZE: + case CS35L41_DSP1_AHBM_WIN0_CTRL0: + case CS35L41_DSP1_AHBM_WIN0_CTRL1: + case CS35L41_DSP1_AHBM_WIN1_CTRL0: + case CS35L41_DSP1_AHBM_WIN1_CTRL1: + case CS35L41_DSP1_AHBM_WIN2_CTRL0: + case CS35L41_DSP1_AHBM_WIN2_CTRL1: + case CS35L41_DSP1_AHBM_WIN3_CTRL0: + case CS35L41_DSP1_AHBM_WIN3_CTRL1: + case CS35L41_DSP1_AHBM_WIN4_CTRL0: + case CS35L41_DSP1_AHBM_WIN4_CTRL1: + case CS35L41_DSP1_AHBM_WIN5_CTRL0: + case CS35L41_DSP1_AHBM_WIN5_CTRL1: + case CS35L41_DSP1_AHBM_WIN6_CTRL0: + case CS35L41_DSP1_AHBM_WIN6_CTRL1: + case CS35L41_DSP1_AHBM_WIN7_CTRL0: + case CS35L41_DSP1_AHBM_WIN7_CTRL1: + case CS35L41_DSP1_AHBM_WIN_DBG_CTRL0: + case CS35L41_DSP1_AHBM_WIN_DBG_CTRL1: + case CS35L41_DSP1_DEBUG: + case CS35L41_DSP1_TIMER_CTRL: + case CS35L41_DSP1_RX1_RATE: + case CS35L41_DSP1_RX2_RATE: + case CS35L41_DSP1_RX3_RATE: + case CS35L41_DSP1_RX4_RATE: + case CS35L41_DSP1_RX5_RATE: + case CS35L41_DSP1_RX6_RATE: + case CS35L41_DSP1_RX7_RATE: + case CS35L41_DSP1_RX8_RATE: + case CS35L41_DSP1_TX1_RATE: + case CS35L41_DSP1_TX2_RATE: + case CS35L41_DSP1_TX3_RATE: + case CS35L41_DSP1_TX4_RATE: + case CS35L41_DSP1_TX5_RATE: + case CS35L41_DSP1_TX6_RATE: + case CS35L41_DSP1_TX7_RATE: + case CS35L41_DSP1_TX8_RATE: + case CS35L41_DSP1_NMI_CTRL1: + case CS35L41_DSP1_NMI_CTRL2: + case CS35L41_DSP1_NMI_CTRL3: + case CS35L41_DSP1_NMI_CTRL4: + case CS35L41_DSP1_NMI_CTRL5: + case CS35L41_DSP1_NMI_CTRL6: + case CS35L41_DSP1_NMI_CTRL7: + case CS35L41_DSP1_NMI_CTRL8: + case CS35L41_DSP1_RESUME_CTRL: + case CS35L41_DSP1_IRQ1_CTRL: + case CS35L41_DSP1_IRQ2_CTRL: + case CS35L41_DSP1_IRQ3_CTRL: + case CS35L41_DSP1_IRQ4_CTRL: + case CS35L41_DSP1_IRQ5_CTRL: + case CS35L41_DSP1_IRQ6_CTRL: + case CS35L41_DSP1_IRQ7_CTRL: + case CS35L41_DSP1_IRQ8_CTRL: + case CS35L41_DSP1_IRQ9_CTRL: + case CS35L41_DSP1_IRQ10_CTRL: + case CS35L41_DSP1_IRQ11_CTRL: + case CS35L41_DSP1_IRQ12_CTRL: + case CS35L41_DSP1_IRQ13_CTRL: + case CS35L41_DSP1_IRQ14_CTRL: + case CS35L41_DSP1_IRQ15_CTRL: + case CS35L41_DSP1_IRQ16_CTRL: + case CS35L41_DSP1_IRQ17_CTRL: + case CS35L41_DSP1_IRQ18_CTRL: + case CS35L41_DSP1_IRQ19_CTRL: + case CS35L41_DSP1_IRQ20_CTRL: + case CS35L41_DSP1_IRQ21_CTRL: + case CS35L41_DSP1_IRQ22_CTRL: + case CS35L41_DSP1_IRQ23_CTRL: + case CS35L41_DSP1_SCRATCH1: + case CS35L41_DSP1_SCRATCH2: + case CS35L41_DSP1_SCRATCH3: + case CS35L41_DSP1_SCRATCH4: + case CS35L41_DSP1_CCM_CORE_CTRL: + case CS35L41_DSP1_CCM_CLK_OVERRIDE: + case CS35L41_DSP1_XM_MSTR_EN: + case CS35L41_DSP1_XM_CORE_PRI: + case CS35L41_DSP1_XM_AHB_PACK_PL_PRI: + case CS35L41_DSP1_XM_AHB_UP_PL_PRI: + case CS35L41_DSP1_XM_ACCEL_PL0_PRI: + case CS35L41_DSP1_XM_NPL0_PRI: + case CS35L41_DSP1_YM_MSTR_EN: + case CS35L41_DSP1_YM_CORE_PRI: + case CS35L41_DSP1_YM_AHB_PACK_PL_PRI: + case CS35L41_DSP1_YM_AHB_UP_PL_PRI: + case CS35L41_DSP1_YM_ACCEL_PL0_PRI: + case CS35L41_DSP1_YM_NPL0_PRI: + case CS35L41_DSP1_PM_MSTR_EN: + case CS35L41_DSP1_PM_PATCH0_ADDR: + case CS35L41_DSP1_PM_PATCH0_EN: + case CS35L41_DSP1_PM_PATCH0_DATA_LO: + case CS35L41_DSP1_PM_PATCH0_DATA_HI: + case CS35L41_DSP1_PM_PATCH1_ADDR: + case CS35L41_DSP1_PM_PATCH1_EN: + case CS35L41_DSP1_PM_PATCH1_DATA_LO: + case CS35L41_DSP1_PM_PATCH1_DATA_HI: + case CS35L41_DSP1_PM_PATCH2_ADDR: + case CS35L41_DSP1_PM_PATCH2_EN: + case CS35L41_DSP1_PM_PATCH2_DATA_LO: + case CS35L41_DSP1_PM_PATCH2_DATA_HI: + case CS35L41_DSP1_PM_PATCH3_ADDR: + case CS35L41_DSP1_PM_PATCH3_EN: + case CS35L41_DSP1_PM_PATCH3_DATA_LO: + case CS35L41_DSP1_PM_PATCH3_DATA_HI: + case CS35L41_DSP1_PM_PATCH4_ADDR: + case CS35L41_DSP1_PM_PATCH4_EN: + case CS35L41_DSP1_PM_PATCH4_DATA_LO: + case CS35L41_DSP1_PM_PATCH4_DATA_HI: + case CS35L41_DSP1_PM_PATCH5_ADDR: + case CS35L41_DSP1_PM_PATCH5_EN: + case CS35L41_DSP1_PM_PATCH5_DATA_LO: + case CS35L41_DSP1_PM_PATCH5_DATA_HI: + case CS35L41_DSP1_PM_PATCH6_ADDR: + case CS35L41_DSP1_PM_PATCH6_EN: + case CS35L41_DSP1_PM_PATCH6_DATA_LO: + case CS35L41_DSP1_PM_PATCH6_DATA_HI: + case CS35L41_DSP1_PM_PATCH7_ADDR: + case CS35L41_DSP1_PM_PATCH7_EN: + case CS35L41_DSP1_PM_PATCH7_DATA_LO: + case CS35L41_DSP1_PM_PATCH7_DATA_HI: + case CS35L41_DSP1_MPU_XM_ACCESS0: + case CS35L41_DSP1_MPU_YM_ACCESS0: + case CS35L41_DSP1_MPU_WNDW_ACCESS0: + case CS35L41_DSP1_MPU_XREG_ACCESS0: + case CS35L41_DSP1_MPU_YREG_ACCESS0: + case CS35L41_DSP1_MPU_XM_ACCESS1: + case CS35L41_DSP1_MPU_YM_ACCESS1: + case CS35L41_DSP1_MPU_WNDW_ACCESS1: + case CS35L41_DSP1_MPU_XREG_ACCESS1: + case CS35L41_DSP1_MPU_YREG_ACCESS1: + case CS35L41_DSP1_MPU_XM_ACCESS2: + case CS35L41_DSP1_MPU_YM_ACCESS2: + case CS35L41_DSP1_MPU_WNDW_ACCESS2: + case CS35L41_DSP1_MPU_XREG_ACCESS2: + case CS35L41_DSP1_MPU_YREG_ACCESS2: + case CS35L41_DSP1_MPU_XM_ACCESS3: + case CS35L41_DSP1_MPU_YM_ACCESS3: + case CS35L41_DSP1_MPU_WNDW_ACCESS3: + case CS35L41_DSP1_MPU_XREG_ACCESS3: + case CS35L41_DSP1_MPU_YREG_ACCESS3: + case CS35L41_DSP1_MPU_XM_VIO_ADDR: + case CS35L41_DSP1_MPU_XM_VIO_STATUS: + case CS35L41_DSP1_MPU_YM_VIO_ADDR: + case CS35L41_DSP1_MPU_YM_VIO_STATUS: + case CS35L41_DSP1_MPU_PM_VIO_ADDR: + case CS35L41_DSP1_MPU_PM_VIO_STATUS: + case CS35L41_DSP1_MPU_LOCK_CONFIG: + case CS35L41_DSP1_MPU_WDT_RST_CTRL: + case CS35L41_DSP1_STRMARB_MSTR0_CFG0: + case CS35L41_DSP1_STRMARB_MSTR0_CFG1: + case CS35L41_DSP1_STRMARB_MSTR0_CFG2: + case CS35L41_DSP1_STRMARB_MSTR1_CFG0: + case CS35L41_DSP1_STRMARB_MSTR1_CFG1: + case CS35L41_DSP1_STRMARB_MSTR1_CFG2: + case CS35L41_DSP1_STRMARB_MSTR2_CFG0: + case CS35L41_DSP1_STRMARB_MSTR2_CFG1: + case CS35L41_DSP1_STRMARB_MSTR2_CFG2: + case CS35L41_DSP1_STRMARB_MSTR3_CFG0: + case CS35L41_DSP1_STRMARB_MSTR3_CFG1: + case CS35L41_DSP1_STRMARB_MSTR3_CFG2: + case CS35L41_DSP1_STRMARB_MSTR4_CFG0: + case CS35L41_DSP1_STRMARB_MSTR4_CFG1: + case CS35L41_DSP1_STRMARB_MSTR4_CFG2: + case CS35L41_DSP1_STRMARB_MSTR5_CFG0: + case CS35L41_DSP1_STRMARB_MSTR5_CFG1: + case CS35L41_DSP1_STRMARB_MSTR5_CFG2: + case CS35L41_DSP1_STRMARB_MSTR6_CFG0: + case CS35L41_DSP1_STRMARB_MSTR6_CFG1: + case CS35L41_DSP1_STRMARB_MSTR6_CFG2: + case CS35L41_DSP1_STRMARB_MSTR7_CFG0: + case CS35L41_DSP1_STRMARB_MSTR7_CFG1: + case CS35L41_DSP1_STRMARB_MSTR7_CFG2: + case CS35L41_DSP1_STRMARB_TX0_CFG0: + case CS35L41_DSP1_STRMARB_TX0_CFG1: + case CS35L41_DSP1_STRMARB_TX1_CFG0: + case CS35L41_DSP1_STRMARB_TX1_CFG1: + case CS35L41_DSP1_STRMARB_TX2_CFG0: + case CS35L41_DSP1_STRMARB_TX2_CFG1: + case CS35L41_DSP1_STRMARB_TX3_CFG0: + case CS35L41_DSP1_STRMARB_TX3_CFG1: + case CS35L41_DSP1_STRMARB_TX4_CFG0: + case CS35L41_DSP1_STRMARB_TX4_CFG1: + case CS35L41_DSP1_STRMARB_TX5_CFG0: + case CS35L41_DSP1_STRMARB_TX5_CFG1: + case CS35L41_DSP1_STRMARB_TX6_CFG0: + case CS35L41_DSP1_STRMARB_TX6_CFG1: + case CS35L41_DSP1_STRMARB_TX7_CFG0: + case CS35L41_DSP1_STRMARB_TX7_CFG1: + case CS35L41_DSP1_STRMARB_RX0_CFG0: + case CS35L41_DSP1_STRMARB_RX0_CFG1: + case CS35L41_DSP1_STRMARB_RX1_CFG0: + case CS35L41_DSP1_STRMARB_RX1_CFG1: + case CS35L41_DSP1_STRMARB_RX2_CFG0: + case CS35L41_DSP1_STRMARB_RX2_CFG1: + case CS35L41_DSP1_STRMARB_RX3_CFG0: + case CS35L41_DSP1_STRMARB_RX3_CFG1: + case CS35L41_DSP1_STRMARB_RX4_CFG0: + case CS35L41_DSP1_STRMARB_RX4_CFG1: + case CS35L41_DSP1_STRMARB_RX5_CFG0: + case CS35L41_DSP1_STRMARB_RX5_CFG1: + case CS35L41_DSP1_STRMARB_RX6_CFG0: + case CS35L41_DSP1_STRMARB_RX6_CFG1: + case CS35L41_DSP1_STRMARB_RX7_CFG0: + case CS35L41_DSP1_STRMARB_RX7_CFG1: + case CS35L41_DSP1_STRMARB_IRQ0_CFG0: + case CS35L41_DSP1_STRMARB_IRQ0_CFG1: + case CS35L41_DSP1_STRMARB_IRQ0_CFG2: + case CS35L41_DSP1_STRMARB_IRQ1_CFG0: + case CS35L41_DSP1_STRMARB_IRQ1_CFG1: + case CS35L41_DSP1_STRMARB_IRQ1_CFG2: + case CS35L41_DSP1_STRMARB_IRQ2_CFG0: + case CS35L41_DSP1_STRMARB_IRQ2_CFG1: + case CS35L41_DSP1_STRMARB_IRQ2_CFG2: + case CS35L41_DSP1_STRMARB_IRQ3_CFG0: + case CS35L41_DSP1_STRMARB_IRQ3_CFG1: + case CS35L41_DSP1_STRMARB_IRQ3_CFG2: + case CS35L41_DSP1_STRMARB_IRQ4_CFG0: + case CS35L41_DSP1_STRMARB_IRQ4_CFG1: + case CS35L41_DSP1_STRMARB_IRQ4_CFG2: + case CS35L41_DSP1_STRMARB_IRQ5_CFG0: + case CS35L41_DSP1_STRMARB_IRQ5_CFG1: + case CS35L41_DSP1_STRMARB_IRQ5_CFG2: + case CS35L41_DSP1_STRMARB_IRQ6_CFG0: + case CS35L41_DSP1_STRMARB_IRQ6_CFG1: + case CS35L41_DSP1_STRMARB_IRQ6_CFG2: + case CS35L41_DSP1_STRMARB_IRQ7_CFG0: + case CS35L41_DSP1_STRMARB_IRQ7_CFG1: + case CS35L41_DSP1_STRMARB_IRQ7_CFG2: + case CS35L41_DSP1_STRMARB_RESYNC_MSK: + case CS35L41_DSP1_STRMARB_ERR_STATUS: + case CS35L41_DSP1_INTPCTL_RES_STATIC: + case CS35L41_DSP1_INTPCTL_RES_DYN: + case CS35L41_DSP1_INTPCTL_NMI_CTRL: + case CS35L41_DSP1_INTPCTL_IRQ_INV: + case CS35L41_DSP1_INTPCTL_IRQ_MODE: + case CS35L41_DSP1_INTPCTL_IRQ_EN: + case CS35L41_DSP1_INTPCTL_IRQ_MSK: + case CS35L41_DSP1_INTPCTL_IRQ_ERR: + case CS35L41_DSP1_INTPCTL_IRQ_PEND: + case CS35L41_DSP1_INTPCTL_TESTBITS: + case CS35L41_DSP1_WDT_CONTROL: + case CS35L41_DSP1_WDT_STATUS: + case CS35L41_OTP_TRIM_1: + case CS35L41_OTP_TRIM_2: + case CS35L41_OTP_TRIM_3: + case CS35L41_OTP_TRIM_4: + case CS35L41_OTP_TRIM_5: + case CS35L41_OTP_TRIM_6: + case CS35L41_OTP_TRIM_7: + case CS35L41_OTP_TRIM_8: + case CS35L41_OTP_TRIM_9: + case CS35L41_OTP_TRIM_10: + case CS35L41_OTP_TRIM_11: + case CS35L41_OTP_TRIM_12: + case CS35L41_OTP_TRIM_13: + case CS35L41_OTP_TRIM_14: + case CS35L41_OTP_TRIM_15: + case CS35L41_OTP_TRIM_16: + case CS35L41_OTP_TRIM_17: + case CS35L41_OTP_TRIM_18: + case CS35L41_OTP_TRIM_19: + case CS35L41_OTP_TRIM_20: + case CS35L41_OTP_TRIM_21: + case CS35L41_OTP_TRIM_22: + case CS35L41_OTP_TRIM_23: + case CS35L41_OTP_TRIM_24: + case CS35L41_OTP_TRIM_25: + case CS35L41_OTP_TRIM_26: + case CS35L41_OTP_TRIM_27: + case CS35L41_OTP_TRIM_28: + case CS35L41_OTP_TRIM_29: + case CS35L41_OTP_TRIM_30: + case CS35L41_OTP_TRIM_31: + case CS35L41_OTP_TRIM_32: + case CS35L41_OTP_TRIM_33: + case CS35L41_OTP_TRIM_34: + case CS35L41_OTP_TRIM_35: + case CS35L41_OTP_TRIM_36: + case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: + case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: + case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: + case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: + case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: + case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: + case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: + case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: + /*test regs*/ + case CS35L41_PLL_OVR: + case CS35L41_BST_TEST_DUTY: + case CS35L41_DIGPWM_IOCTRL: + return true; + default: + return false; + } +} + +bool cs35l41_precious_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: + return true; + default: + return false; + } +} + +bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CS35L41_DEVID: + case CS35L41_SFT_RESET: + case CS35L41_FABID: + case CS35L41_REVID: + case CS35L41_DEVID_OTP: + case CS35L41_CTRL_OVRRIDE: + case CS35L41_DTEMP_EN: + case CS35L41_IRQ1_STATUS: + case CS35L41_IRQ1_STATUS1: + case CS35L41_IRQ1_STATUS2: + case CS35L41_IRQ1_STATUS3: + case CS35L41_IRQ1_STATUS4: + case CS35L41_IRQ1_RAW_STATUS1: + case CS35L41_IRQ1_RAW_STATUS2: + case CS35L41_IRQ1_RAW_STATUS3: + case CS35L41_IRQ1_RAW_STATUS4: + case CS35L41_IRQ1_FRC1: + case CS35L41_IRQ1_FRC2: + case CS35L41_IRQ1_FRC3: + case CS35L41_IRQ1_FRC4: + case CS35L41_IRQ1_EDGE1: + case CS35L41_IRQ1_EDGE4: + case CS35L41_IRQ1_POL1: + case CS35L41_IRQ1_POL2: + case CS35L41_IRQ1_POL3: + case CS35L41_IRQ1_POL4: + case CS35L41_IRQ1_DB3: + case CS35L41_IRQ2_STATUS: + case CS35L41_IRQ2_STATUS1: + case CS35L41_IRQ2_STATUS2: + case CS35L41_IRQ2_STATUS3: + case CS35L41_IRQ2_STATUS4: + case CS35L41_IRQ2_RAW_STATUS1: + case CS35L41_IRQ2_RAW_STATUS2: + case CS35L41_IRQ2_RAW_STATUS3: + case CS35L41_IRQ2_RAW_STATUS4: + case CS35L41_IRQ2_FRC1: + case CS35L41_IRQ2_FRC2: + case CS35L41_IRQ2_FRC3: + case CS35L41_IRQ2_FRC4: + case CS35L41_IRQ2_EDGE1: + case CS35L41_IRQ2_EDGE4: + case CS35L41_IRQ2_POL1: + case CS35L41_IRQ2_POL2: + case CS35L41_IRQ2_POL3: + case CS35L41_IRQ2_POL4: + case CS35L41_IRQ2_DB3: + case CS35L41_GPIO_STATUS1: + case CS35L41_OTP_TRIM_1: + case CS35L41_OTP_TRIM_2: + case CS35L41_OTP_TRIM_3: + case CS35L41_OTP_TRIM_4: + case CS35L41_OTP_TRIM_5: + case CS35L41_OTP_TRIM_6: + case CS35L41_OTP_TRIM_7: + case CS35L41_OTP_TRIM_8: + case CS35L41_OTP_TRIM_9: + case CS35L41_OTP_TRIM_10: + case CS35L41_OTP_TRIM_11: + case CS35L41_OTP_TRIM_12: + case CS35L41_OTP_TRIM_13: + case CS35L41_OTP_TRIM_14: + case CS35L41_OTP_TRIM_15: + case CS35L41_OTP_TRIM_16: + case CS35L41_OTP_TRIM_17: + case CS35L41_OTP_TRIM_18: + case CS35L41_OTP_TRIM_19: + case CS35L41_OTP_TRIM_20: + case CS35L41_OTP_TRIM_21: + case CS35L41_OTP_TRIM_22: + case CS35L41_OTP_TRIM_23: + case CS35L41_OTP_TRIM_24: + case CS35L41_OTP_TRIM_25: + case CS35L41_OTP_TRIM_26: + case CS35L41_OTP_TRIM_27: + case CS35L41_OTP_TRIM_28: + case CS35L41_OTP_TRIM_29: + case CS35L41_OTP_TRIM_30: + case CS35L41_OTP_TRIM_31: + case CS35L41_OTP_TRIM_32: + case CS35L41_OTP_TRIM_33: + case CS35L41_OTP_TRIM_34: + case CS35L41_OTP_TRIM_35: + case CS35L41_OTP_TRIM_36: + case CS35L41_DSP_MBOX_1 ... CS35L41_DSP_VIRT2_MBOX_8: + case CS35L41_DSP1_XMEM_PACK_0 ... CS35L41_DSP1_XMEM_PACK_3068: + case CS35L41_DSP1_XMEM_UNPACK32_0 ... CS35L41_DSP1_XMEM_UNPACK32_2046: + case CS35L41_DSP1_XMEM_UNPACK24_0 ... CS35L41_DSP1_XMEM_UNPACK24_4093: + case CS35L41_DSP1_YMEM_PACK_0 ... CS35L41_DSP1_YMEM_PACK_1532: + case CS35L41_DSP1_YMEM_UNPACK32_0 ... CS35L41_DSP1_YMEM_UNPACK32_1022: + case CS35L41_DSP1_YMEM_UNPACK24_0 ... CS35L41_DSP1_YMEM_UNPACK24_2045: + case CS35L41_DSP1_PMEM_0 ... CS35L41_DSP1_PMEM_5114: + case CS35L41_DSP1_CCM_CORE_CTRL ... CS35L41_DSP1_WDT_STATUS: + case CS35L41_OTP_MEM0 ... CS35L41_OTP_MEM31: + return true; + default: + return false; + } +} + +static const struct cs35l41_otp_packed_element_t otp_map_1[] = { + /* addr shift size */ + { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ + { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ + { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ + { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ + { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ + { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ + { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ + { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ + { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ + { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ + { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ + { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ + { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ + { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ + { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ + { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ + { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ + { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ + { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ + { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ + { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ + { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ + { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ + { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ + { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ + { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ + { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ + { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ + { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ + { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ + { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ + { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ + { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ + { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ + { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ + { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ + { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ + { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ + { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ + { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ + { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ + { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ + { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ + { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ + { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ + { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ + { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ + { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ + { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ + { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ + { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ + { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ + { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ + { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ + { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ + { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ + { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ + { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ + { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ + { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ + { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ + { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ + { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ + { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ + { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ + { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ + { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ + { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ + { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ + { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ + { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ + { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ + { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ + { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ + { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ + { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ + { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ + { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ + { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ + { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ + { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ + { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ + { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ + { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ + { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ + { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ + { 0x00007434, 17, 1 }, /*FORCE_CAL*/ + { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ + { 0x00007068, 0, 9 }, /*MODIX*/ + { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ + { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ + { 0x00000000, 0, 1 }, /*extra bit*/ + { 0x00017040, 0, 8 }, /*X_COORDINATE*/ + { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ + { 0x00017040, 16, 8 }, /*WAFER_ID*/ + { 0x00017040, 24, 8 }, /*DVS*/ + { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ +}; + +static const struct cs35l41_otp_packed_element_t otp_map_2[] = { + /* addr shift size */ + { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/ + { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/ + { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/ + { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/ + { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/ + { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/ + { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/ + { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/ + { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/ + { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/ + { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/ + { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/ + { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/ + { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/ + { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/ + { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/ + { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/ + { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/ + { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/ + { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/ + { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/ + { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/ + { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/ + { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/ + { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/ + { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/ + { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/ + { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ + { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/ + { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/ + { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/ + { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ + { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ + { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/ + { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/ + { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/ + { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/ + { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/ + { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/ + { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/ + { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/ + { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/ + { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/ + { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/ + { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/ + { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/ + { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/ + { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/ + { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/ + { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/ + { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/ + { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/ + { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/ + { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/ + { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/ + { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/ + { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/ + { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/ + { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/ + { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/ + { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/ + { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/ + { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/ + { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/ + { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/ + { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/ + { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/ + { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/ + { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/ + { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/ + { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/ + { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/ + { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/ + { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/ + { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/ + { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/ + { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/ + { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/ + { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/ + { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/ + { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/ + { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/ + { 0x00006E64, 0, 10 }, /*VOFF_INT1*/ + { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/ + { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/ + { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/ + { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/ + { 0x00007434, 17, 1 }, /*FORCE_CAL*/ + { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/ + { 0x00007068, 0, 9 }, /*MODIX*/ + { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/ + { 0x0000400C, 0, 7 }, /*VIMON_DLY*/ + { 0x00004000, 11, 1 }, /*VMON_POL*/ + { 0x00017040, 0, 8 }, /*X_COORDINATE*/ + { 0x00017040, 8, 8 }, /*Y_COORDINATE*/ + { 0x00017040, 16, 8 }, /*WAFER_ID*/ + { 0x00017040, 24, 8 }, /*DVS*/ + { 0x00017044, 0, 24 }, /*LOT_NUMBER*/ +}; + +const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[] = { + { + .devid_otp = CS35L41_CHIP_ID, /* unset by OTP */ + .id = 0x01, + .map = otp_map_1, + .num_elements = ARRAY_SIZE(otp_map_1), + .bit_offset = 16, + .word_offset = 2, + }, + { + .devid_otp = CS35L41_CHIP_ID, /* unset by OTP */ + .id = 0x02, + .map = otp_map_2, + .num_elements = ARRAY_SIZE(otp_map_2), + .bit_offset = 16, + .word_offset = 2, + }, + { + .devid_otp = 0, /* unset by OTP */ + .id = 0x03, + .map = otp_map_2, + .num_elements = ARRAY_SIZE(otp_map_2), + .bit_offset = 16, + .word_offset = 2, + }, + { + .devid_otp = CS35L41_CHIP_ID, /* unset by OTP */ + .id = 0x06, + .map = otp_map_2, + .num_elements = ARRAY_SIZE(otp_map_2), + .bit_offset = 16, + .word_offset = 2, + }, + { + .devid_otp = CS35L41_CHIP_ID, /* unset by OTP */ + .id = 0x08, + .map = otp_map_1, + .num_elements = ARRAY_SIZE(otp_map_1), + .bit_offset = 16, + .word_offset = 2, + }, + { + .devid_otp = CS35L41LV_CHIP_ID, + .id = 0x01, + .map = otp_map_1, + .num_elements = ARRAY_SIZE(otp_map_1), + .bit_offset = 16, + .word_offset = 4, + }, +}; + +const struct cs35l41_otp_maps cs35l41_otp_maps = { + .map = cs35l41_otp_map_map, + .len = ARRAY_SIZE(cs35l41_otp_map_map), +}; + +const unsigned int cs35l41_ctl_cache_regs[CS35L41_CTRL_CACHE_SIZE] = { + CS35L41_DAC_PCM1_SRC, CS35L41_DSP1_RX1_SRC, + CS35L41_DSP1_RX2_SRC, CS35L41_ASP_TX1_SRC, + CS35L41_ASP_TX2_SRC, CS35L41_ASP_TX3_SRC, + CS35L41_ASP_TX4_SRC, CS35L41_SP_FRAME_TX_SLOT, + CS35L41_AMP_GAIN_CTRL, CS35L41_AMP_DIG_VOL_CTRL, + CS35L41_PWR_CTRL1, CS35L41_PWR_CTRL2, + CS35L41_BSTCVRT_VCTRL1, CS35L41_BSTCVRT_VCTRL2, +}; + +const struct cs35l41_otp_trim_region_t + cs35l41_trim_cache_regs[CS35L41_TRIM_CACHE_REGIONS] = { + { 0x00002030, 1 }, { 0x0000208c, 2 }, { 0x0000300C, 1 }, + { 0x0000394C, 5 }, { 0x0000416C, 1 }, { 0x00004160, 1 }, + { 0x00004170, 1 }, { 0x00004360, 1 }, { 0x00004448, 2 }, + { 0x00006E30, 14 }, { 0x00007418, 2 }, { 0x00007434, 1 }, + { 0x00007068, 1 }, { 0x0000410C, 1 }, { 0x0000400C, 1 }, + { 0x00004000, 1 }, { 0x00017040, 2 }, + }; diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.c b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.c new file mode 100644 index 000000000000..d3e3ef245190 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.c @@ -0,0 +1,3831 @@ +/* + * cs35l41.c -- CS35l41 ALSA SoC audio driver + * + * Copyright 2018 Cirrus Logic, Inc. + * + * Author: David Rhodes + * Brian Austin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#define DEBUG + +//#define BRINGUP_IRQ_VERIFY +#define FAST_SWITCH_WORKAROUND + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" +#include "cs35l41.h" +#include + +static const char *const cs35l41_supplies[] = { + "VA", + "VP", +}; + +struct cs35l41_pll_sysclk_config { + int freq; + int clk_cfg; +}; + +static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { + { 32768, 0x00 }, { 8000, 0x01 }, { 11025, 0x02 }, + { 12000, 0x03 }, { 16000, 0x04 }, { 22050, 0x05 }, + { 24000, 0x06 }, { 32000, 0x07 }, { 44100, 0x08 }, + { 48000, 0x09 }, { 88200, 0x0A }, { 96000, 0x0B }, + { 128000, 0x0C }, { 176400, 0x0D }, { 192000, 0x0E }, + { 256000, 0x0F }, { 352800, 0x10 }, { 384000, 0x11 }, + { 512000, 0x12 }, { 705600, 0x13 }, { 750000, 0x14 }, + { 768000, 0x15 }, { 1000000, 0x16 }, { 1024000, 0x17 }, + { 1200000, 0x18 }, { 1411200, 0x19 }, { 1500000, 0x1A }, + { 1536000, 0x1B }, { 2000000, 0x1C }, { 2048000, 0x1D }, + { 2400000, 0x1E }, { 2822400, 0x1F }, { 3000000, 0x20 }, + { 3072000, 0x21 }, { 3200000, 0x22 }, { 4000000, 0x23 }, + { 4096000, 0x24 }, { 4800000, 0x25 }, { 5644800, 0x26 }, + { 6000000, 0x27 }, { 6144000, 0x28 }, { 6250000, 0x29 }, + { 6400000, 0x2A }, { 6500000, 0x2B }, { 6750000, 0x2C }, + { 7526400, 0x2D }, { 8000000, 0x2E }, { 8192000, 0x2F }, + { 9600000, 0x30 }, { 11289600, 0x31 }, { 12000000, 0x32 }, + { 12288000, 0x33 }, { 12500000, 0x34 }, { 12800000, 0x35 }, + { 13000000, 0x36 }, { 13500000, 0x37 }, { 19200000, 0x38 }, + { 22579200, 0x39 }, { 24000000, 0x3A }, { 24576000, 0x3B }, + { 25000000, 0x3C }, { 25600000, 0x3D }, { 26000000, 0x3E }, + { 27000000, 0x3F }, +}; + +static const unsigned char cs35l41_bst_k1_table[4][5] = { + { 0x24, 0x32, 0x32, 0x4F, 0x57 }, + { 0x24, 0x32, 0x32, 0x4F, 0x57 }, + { 0x40, 0x32, 0x32, 0x4F, 0x57 }, + { 0x40, 0x32, 0x32, 0x4F, 0x57 } +}; + +static const unsigned char cs35l41_bst_k2_table[4][5] = { + { 0x24, 0x49, 0x66, 0xA3, 0xEA }, + { 0x24, 0x49, 0x66, 0xA3, 0xEA }, + { 0x48, 0x49, 0x66, 0xA3, 0xEA }, + { 0x48, 0x49, 0x66, 0xA3, 0xEA } +}; + +static const unsigned char cs35l41_bst_slope_table[4] = { 0x75, 0x6B, 0x3B, + 0x28 }; + +static int cs35l41_enter_hibernate(struct cs35l41_private *cs35l41); +static int cs35l41_exit_hibernate(struct cs35l41_private *cs35l41); +static int cs35l41_restore(struct cs35l41_private *cs35l41); +static int cs35l41_component_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, + unsigned int freq, int dir); + +static int cs35l41_dsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l41->dev, "%s: event = 0x%x\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (cs35l41->halo_booted == false) + wm_adsp_early_event(w, kcontrol, event); + else + cs35l41->dsp.booted = true; + + return 0; + case SND_SOC_DAPM_PRE_PMD: + if (cs35l41->halo_booted == false) { + cancel_delayed_work(&cs35l41->hb_work); + mutex_lock(&cs35l41->hb_lock); + cs35l41_exit_hibernate(cs35l41); + mutex_unlock(&cs35l41->hb_lock); + + if (cs35l41->amp_hibernate != + CS35L41_HIBERNATE_INCOMPATIBLE) + cs35l41->amp_hibernate = + CS35L41_HIBERNATE_NOT_LOADED; + + wm_adsp_early_event(w, kcontrol, event); + wm_adsp_event(w, kcontrol, event); + } + default: + return 0; + } +} + +static int cs35l41_set_csplmboxcmd(struct cs35l41_private *cs35l41, + enum cs35l41_cspl_mboxcmd cmd); + +static int cs35l41_dsp_load_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + enum cs35l41_cspl_mboxcmd mboxcmd = CSPL_MBOX_CMD_NONE; + enum cs35l41_cspl_mboxstate fw_status = CSPL_MBOX_STS_RUNNING; + int ret = 0; + + dev_dbg(cs35l41->dev, "%s: event = 0x%x\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (cs35l41->halo_booted == false) { + wm_adsp_event(w, kcontrol, event); + cs35l41->halo_booted = true; + } + if (cs35l41->dsp.running) { + regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, + (unsigned int *)&fw_status); + switch (fw_status) { + case CSPL_MBOX_STS_RDY_FOR_REINIT: + mboxcmd = CSPL_MBOX_CMD_REINIT; + break; + case CSPL_MBOX_STS_PAUSED: + mboxcmd = CSPL_MBOX_CMD_RESUME; + break; + case CSPL_MBOX_STS_RUNNING: + /* + * First time playing audio + * means fw_status is running + */ + mboxcmd = CSPL_MBOX_CMD_RESUME; + break; + default: + dev_err(cs35l41->dev, + "Firmware status is invalid(%u)\n", + fw_status); + break; + } + ret = cs35l41_set_csplmboxcmd(cs35l41, mboxcmd); + } + break; + case SND_SOC_DAPM_PRE_PMD: + /* + * Workaround for PB 5.41.6 FW power consumption issue. + * FW sets bit FILT_GLOBAL_OVR, so it should be cleared + * after FW boot up + */ + regmap_update_bits(cs35l41->regmap, CS35L41_CTRL_OVRRIDE, + CS35L41_FILT_GLOBAL_OVR_MASK, 0); + break; + default: + break; + } + + return ret; +} + +static int cs35l41_halo_booted_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l41->dev, "%s: get=%d\n", __func__, cs35l41->halo_booted); + + ucontrol->value.integer.value[0] = cs35l41->halo_booted; + + return 0; +} + +static int cs35l41_halo_booted_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l41->dev, "%s: put=%ld\n", __func__, + ucontrol->value.integer.value[0]); + + cs35l41->halo_booted = ucontrol->value.integer.value[0]; + + return 0; +} + +static int cs35l41_force_int_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = cs35l41->force_int; + + return 0; +} + +static int cs35l41_force_int_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + bool force_int_changed = + (cs35l41->force_int != (bool)ucontrol->value.integer.value[0]); + + mutex_lock(&cs35l41->force_int_lock); + + cs35l41->force_int = ucontrol->value.integer.value[0]; + + if (force_int_changed) { + if (cs35l41->force_int) { + disable_irq(cs35l41->irq); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, + CS35L41_INT1_MASK_FORCE); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_FRC1, 1); + } else { + regmap_write(cs35l41->regmap, CS35L41_IRQ1_FRC1, 0); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, + CS35L41_INT1_MASK_DEFAULT); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 1); + enable_irq(cs35l41->irq); + } + } + + mutex_unlock(&cs35l41->force_int_lock); + + return 0; +} + +static int cs35l41_ccm_reset_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +static int cs35l41_ccm_reset_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + unsigned int val = 0; + int ret = 0; + + val = ucontrol->value.integer.value[0]; + + if (val) { + ret = regmap_update_bits(cs35l41->regmap, CS35L41_DSP_CLK_CTRL, + 0x3, 0x2); + ret = regmap_update_bits(cs35l41->regmap, + CS35L41_DSP1_CCM_CORE_CTRL, + CS35L41_HALO_CORE_RESET, + CS35L41_HALO_CORE_RESET); + ret = regmap_update_bits(cs35l41->regmap, CS35L41_DSP_CLK_CTRL, + 0x3, 0x3); + } + + return 0; +} + +static int cs35l41_hibernate_force_wake_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = cs35l41->hibernate_force_wake; + + return 0; +} + +static int cs35l41_hibernate_force_wake_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + bool valid_transition = cs35l41->hibernate_force_wake != + ucontrol->value.integer.value[0]; + unsigned int amp_active; + + regmap_read(cs35l41->regmap, CS35L41_PWR_CTRL1, &_active); + + if (cs35l41->amp_hibernate == CS35L41_HIBERNATE_AWAKE || + (cs35l41->amp_hibernate == CS35L41_HIBERNATE_NOT_LOADED && + cs35l41->dsp.running)) { + cs35l41->hibernate_force_wake = + ucontrol->value.integer.value[0]; + if (!cs35l41->hibernate_force_wake && valid_transition && + !(amp_active & CS35L41_GLOBAL_EN_MASK)) { + /* return to standby */ + queue_delayed_work(cs35l41->wq, &cs35l41->hb_work, + msecs_to_jiffies(100)); + } + } else if (cs35l41->amp_hibernate == CS35L41_HIBERNATE_STANDBY) { + cs35l41->hibernate_force_wake = + ucontrol->value.integer.value[0]; + if (cs35l41->hibernate_force_wake && valid_transition) { + /* wake from standby */ + cancel_delayed_work(&cs35l41->hb_work); + mutex_lock(&cs35l41->hb_lock); + cs35l41_exit_hibernate(cs35l41); + mutex_unlock(&cs35l41->hb_lock); + } + } + + return 0; +} + +static const char *cs35l41_fast_switch_text[] = { + "fast_switch1.txt", "fast_switch2.txt", "fast_switch3.txt", + "fast_switch4.txt", "fast_switch5.txt", +}; + +static int cs35l41_fast_switch_en_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = cs35l41->fast_switch_en; + + return 0; +} + +static int cs35l41_do_fast_switch(struct cs35l41_private *cs35l41) +{ + char val_str[CS35L41_BUFSIZE]; + const char *fw_name; + const struct firmware *fw; + int ret; + unsigned int i, j, k; + s32 data_ctl_len, val; + __be32 *data_ctl_buf, cmd_ctl, st_ctl; + bool fw_running = false; + + data_ctl_buf = NULL; + + fw_name = cs35l41->fast_switch_names[cs35l41->fast_switch_file_idx]; + dev_dbg(cs35l41->dev, "fw_name:%s\n", fw_name); + ret = request_firmware(&fw, fw_name, cs35l41->dev); + if (ret < 0) { + dev_err(cs35l41->dev, "Failed to request firmware:%s\n", + fw_name); + return -EIO; + } + + /* Parse number of data in file */ + for (i = 0, j = 0; (char)fw->data[i] != ','; i++) { + if ((char)fw->data[i] == ' ') { + /* Skip white space */ + } else { + /* fw->data[i] must be numerical digit */ + if (j < CS35L41_BUFSIZE - 1) { + val_str[j] = fw->data[i]; + j++; + } else { + dev_err(cs35l41->dev, "Invalid input\n"); + ret = -EINVAL; + goto exit; + } + } + } + i++; /* points to beginning of next number */ + val_str[j] = '\0'; + ret = kstrtos32(val_str, 10, &data_ctl_len); + if (ret < 0) { + dev_err(cs35l41->dev, "kstrtos32 failed (%d) val_str:%s\n", ret, + val_str); + goto exit; + } + + dev_dbg(cs35l41->dev, "data_ctl_len:%u\n", data_ctl_len); + + data_ctl_buf = kcalloc(1, data_ctl_len * sizeof(s32), GFP_KERNEL); + if (!data_ctl_buf) { + ret = -ENOMEM; + goto exit; + } + + data_ctl_buf[0] = cpu_to_be32(data_ctl_len); + + /* i continues from end of previous loop */ + for (j = 0, k = 1; i <= fw->size; i++) { + if (i == fw->size || (char)fw->data[i] == ',') { + /* + * Reached end of parameter + * delimited either by ',' or end of file + * Parse number and write parameter + */ + val_str[j] = '\0'; + ret = kstrtos32(val_str, 10, &val); + if (ret < 0) { + dev_err(cs35l41->dev, + "kstrtos32 failed (%d) val_str:%s\n", + ret, val_str); + goto exit; + } + data_ctl_buf[k] = cpu_to_be32(val); + j = 0; + k++; + } else if ((char)fw->data[i] == ' ') { + /* Skip white space */ + } else { + /* fw->data[i] must be numerical digit */ + if (j < CS35L41_BUFSIZE - 1) { + val_str[j] = fw->data[i]; + j++; + } else { + dev_err(cs35l41->dev, "Invalid input\n"); + ret = -EINVAL; + goto exit; + } + } + } + + wm_adsp_write_ctl(&cs35l41->dsp, "CSPL_UPDATE_PARAMS_CONFIG", + data_ctl_buf, data_ctl_len * sizeof(s32)); + + dev_dbg(cs35l41->dev, "Wrote %u reg for CSPL_UPDATE_PARAMS_CONFIG\n", + data_ctl_len); + +#ifdef DEBUG + wm_adsp_read_ctl(&cs35l41->dsp, "CSPL_UPDATE_PARAMS_CONFIG", + data_ctl_buf, data_ctl_len * sizeof(s32)); + dev_dbg(cs35l41->dev, "read CSPL_UPDATE_PARAMS_CONFIG:\n"); + for (i = 0; i < data_ctl_len; i++) + dev_dbg(cs35l41->dev, "%u\n", be32_to_cpu(data_ctl_buf[i])); +#endif + cmd_ctl = cpu_to_be32(CSPL_CMD_UPDATE_PARAM); + wm_adsp_write_ctl(&cs35l41->dsp, "CSPL_COMMAND", &cmd_ctl, sizeof(s32)); + + /* Verify CSPL COMMAND */ + for (i = 0; i < 5; i++) { + wm_adsp_read_ctl(&cs35l41->dsp, "CSPL_STATE", &st_ctl, + sizeof(s32)); + if (be32_to_cpu(st_ctl) == CSPL_ST_RUNNING) { + dev_dbg(cs35l41->dev, + "CSPL STATE == RUNNING (%u attempt)\n", i); + fw_running = true; + break; + } + + usleep_range(100, 110); + } + + if (!fw_running) { + dev_err(cs35l41->dev, "CSPL_STATE (%d) is not running\n", + st_ctl); + ret = -1; + goto exit; + } +exit: + kfree(data_ctl_buf); + release_firmware(fw); + return ret; +} + +static int cs35l41_fast_switch_en_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + +#if !defined(FAST_SWITCH_WORKAROUND) + if (!cs35l41->fast_switch_en && ucontrol->value.integer.value[0]) + /* + * Rising on fast switch enable + * Perform fast use case switching + */ + ret = cs35l41_do_fast_switch(cs35l41); +#endif + + cs35l41->fast_switch_en = ucontrol->value.integer.value[0]; + + return ret; +} + +static int cs35l41_fast_switch_file_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + struct soc_enum *soc_enum; + unsigned int i = ucontrol->value.enumerated.item[0]; + + soc_enum = (struct soc_enum *)kcontrol->private_value; + + if (i >= soc_enum->items) { + dev_err(cs35l41->dev, "Invalid mixer input (%u)\n", i); + return -EINVAL; + } + +#if defined(FAST_SWITCH_WORKAROUND) + if (!cs35l41->dsp.running) { + dev_err(cs35l41->dev, "DSP not running\n"); + return 0; + } + + if ((i != cs35l41->fast_switch_file_idx) && cs35l41->fast_switch_en) { + int ret; + + cs35l41->fast_switch_file_idx = i; + ret = cs35l41_do_fast_switch(cs35l41); + dev_dbg(cs35l41->dev, "%s: fast switch %s\n", __func__, + ret ? "fail" : "success"); + } +#endif + + return 0; +} + +static int cs35l41_fast_switch_file_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = cs35l41->fast_switch_file_idx; + + return 0; +} + +static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 0, 0, + TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 1, + CS35L41_MAX_PCM_VOL, + TLV_DB_MINMAX_ITEM(-10200, 1200)); +static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); + +static const struct snd_kcontrol_new dre_ctrl = + SOC_DAPM_SINGLE("DRE Switch", CS35L41_PWR_CTRL3, 20, 1, 0); + +static const struct snd_kcontrol_new vbstmon_out_ctrl = + SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); + +static const char *const cs35l41_pcm_sftramp_text[] = { "Off", ".5ms", "1ms", + "2ms", "4ms", "8ms", + "15ms", "30ms" }; + +static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L41_AMP_DIG_VOL_CTRL, 0, + cs35l41_pcm_sftramp_text); + +static int cs35l41_reload_tuning_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = cs35l41->reload_tuning; + + return 0; +} + +static int cs35l41_reload_tuning_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + cs35l41->reload_tuning = ucontrol->value.integer.value[0]; + + return 0; +} + +static bool cs35l41_is_csplmboxsts_correct(enum cs35l41_cspl_mboxcmd cmd, + enum cs35l41_cspl_mboxstate sts) +{ + switch (cmd) { + case CSPL_MBOX_CMD_NONE: + case CSPL_MBOX_CMD_UNKNOWN_CMD: + return true; + case CSPL_MBOX_CMD_PAUSE: + return (sts == CSPL_MBOX_STS_PAUSED); + case CSPL_MBOX_CMD_RESUME: + return (sts == CSPL_MBOX_STS_RUNNING); + case CSPL_MBOX_CMD_REINIT: + return (sts == CSPL_MBOX_STS_RUNNING); + case CSPL_MBOX_CMD_STOP_PRE_REINIT: + return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); + default: + return false; + } +} + +static int cs35l41_set_csplmboxcmd(struct cs35l41_private *cs35l41, + enum cs35l41_cspl_mboxcmd cmd) +{ + int ret = 0; + unsigned int sts, i; + bool ack = false; + + /* Reset DSP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ2_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT); + + /* Reset AP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT); + + /* + * Set mailbox cmd + */ + /* Unmask DSP INT */ + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ2_MASK2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT, 0); + regmap_write(cs35l41->regmap, CS35L41_CSPL_MBOX_CMD_DRV, cmd); + + /* Poll for DSP ACK */ + for (i = 0; i < 5; i++) { + usleep_range(1000, 1010); + ret = regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS2, &sts); + if (ret < 0) { + dev_err(cs35l41->dev, "regmap_read failed (%d)\n", ret); + continue; + } + if (sts & (1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT)) { + dev_dbg(cs35l41->dev, + "%u: Received ACK in EINT for mbox cmd (%d)\n", + i, cmd); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT); + ack = true; + break; + } + } + + if (!ack) { + dev_err(cs35l41->dev, + "Timeout waiting for DSP to set mbox cmd\n"); + ret = -ETIMEDOUT; + } + + /* Mask DSP INT */ + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ2_MASK2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT); + + if (regmap_read(cs35l41->regmap, CS35L41_CSPL_MBOX_STS, &sts) < 0) { + dev_err(cs35l41->dev, "Failed to read %u\n", + CS35L41_CSPL_MBOX_STS); + ret = -EACCES; + } + + if (!cs35l41_is_csplmboxsts_correct(cmd, + (enum cs35l41_cspl_mboxstate)sts)) { + dev_err(cs35l41->dev, + "Failed to set mailbox(cmd: %u, sts: %u)\n", cmd, sts); + ret = -ENOMSG; + } + + return ret; +} + +static void cs35l41_abort_ramp(struct cs35l41_private *cs35l41) +{ + if (!work_busy(&cs35l41->vol_ctl.ramp_work)) + return; + atomic_set(&cs35l41->vol_ctl.ramp_abort, 1); + cancel_work_sync(&cs35l41->vol_ctl.ramp_work); + flush_workqueue(cs35l41->vol_ctl.ramp_wq); + atomic_set(&cs35l41->vol_ctl.ramp_abort, 0); +} + +static int cs35l41_put_output_dev(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + struct soc_enum *soc_enum; + unsigned int i = ucontrol->value.enumerated.item[0]; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + dev_dbg(cs35l41->dev, "%s: output_dev = %u\n", __func__, i); + + soc_enum = (struct soc_enum *)kcontrol->private_value; + + if (i >= soc_enum->items) { + dev_err(component->dev, "Invalid mixer input (%u)\n", i); + return -EINVAL; + } + + if (atomic_read(&cs35l41->vol_ctl.playback) && + cs35l41->vol_ctl.auto_ramp_timeout > 0 && + cs35l41->vol_ctl.output_dev == CS35L41_OUTPUT_DEV_RCV && + soc_enum->values[i] == CS35L41_OUTPUT_DEV_SPK) { + /* + * While audio is playing, + * auto volume ramp is enabled, + * output device changes from RCV to SPK. + * In this case, perform volume ramp. + */ + cs35l41_abort_ramp(cs35l41); + queue_work(cs35l41->vol_ctl.ramp_wq, + &cs35l41->vol_ctl.ramp_work); + } + + cs35l41->vol_ctl.output_dev = soc_enum->values[i]; + + return 0; +} + +static int cs35l41_get_output_dev(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + int ret = 0; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = cs35l41->vol_ctl.output_dev; + + return ret; +} + +static const char *const channel_swap_texts[] = { "Off", "On" }; +static SOC_ENUM_SINGLE_DECL(channel_swap_enum, SND_SOC_NOPM, 0, + channel_swap_texts); + +static const char *virt_text[] = { "None", "Ref" }; +static SOC_ENUM_SINGLE_DECL(virt_enum, SND_SOC_NOPM, 2, virt_text); + +static const struct snd_kcontrol_new virt_mux = + SOC_DAPM_ENUM("Virt Connect", virt_enum); + +static const char *const cs35l41_pcm_source_texts[] = { "None", "ASP", "DSP" }; +static const unsigned int cs35l41_pcm_source_values[] = { 0x00, 0x08, 0x32 }; +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, CS35L41_DAC_PCM1_SRC, + 0, CS35L41_ASP_SOURCE_MASK, + cs35l41_pcm_source_texts, + cs35l41_pcm_source_values); + +static const struct snd_kcontrol_new pcm_source_mux = + SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); + +static const char *const cs35l41_tx_input_texts[] = { + "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", + "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" +}; +static const unsigned int cs35l41_tx_input_values[] = { + 0x00, + CS35L41_INPUT_SRC_ASPRX1, + CS35L41_INPUT_SRC_ASPRX2, + CS35L41_INPUT_SRC_VMON, + CS35L41_INPUT_SRC_IMON, + CS35L41_INPUT_SRC_VPMON, + CS35L41_INPUT_SRC_VBSTMON, + CS35L41_INPUT_DSP_TX1, + CS35L41_INPUT_DSP_TX2 +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, CS35L41_ASP_TX1_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx1_mux = + SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, CS35L41_ASP_TX2_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx2_mux = + SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, CS35L41_ASP_TX3_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx3_mux = + SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, CS35L41_ASP_TX4_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new asp_tx4_mux = + SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, CS35L41_DSP1_RX1_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new dsp_rx1_mux = + SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, CS35L41_DSP1_RX2_SRC, 0, + CS35L41_ASP_SOURCE_MASK, + cs35l41_tx_input_texts, + cs35l41_tx_input_values); + +static const struct snd_kcontrol_new dsp_rx2_mux = + SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); + +static void cs35l41_set_vol(int vol, struct cs35l41_private *cs35l41) +{ + unsigned int val; + int ret; + + mutex_lock(&cs35l41->vol_ctl.vol_mutex); + + if (vol < 0 || vol > CS35L41_MAX_PCM_VOL) { + dev_err(cs35l41->dev, "Invalid PCM VOLUME %d\n", vol); + goto exit; + } + + if (vol < CS35L41_ZERO_PCM_VOL) + /* PCM Volume is attenuation */ + val = (unsigned int)(vol + CS35L41_AMP_PCM_VOL_MUTE); + else + /* CS35L41_ZERO_PCM_VOL <= dig_vol <= CS35L41_MAX_PCM_VOL */ + val = (unsigned int)(vol - CS35L41_ZERO_PCM_VOL); + ret = regmap_update_bits(cs35l41->regmap, CS35L41_AMP_DIG_VOL_CTRL, + CS35L41_AMP_PCM_VOL_MASK, + val << CS35L41_AMP_PCM_VOL_SHIFT); + if (ret < 0) + dev_err(cs35l41->dev, "Failed to set PCM VOLUME %d\n", ret); + +exit: + mutex_unlock(&cs35l41->vol_ctl.vol_mutex); +} + +static int cs35l41_vol_ramp0(struct cs35l41_private *cs35l41, long final_x, + long init_y, long final_y) +{ + long curr_x = 0; + long curr_y = init_y; + long delta_x = final_x; + long delta_y = final_y - init_y; + long step_x, step_y; + int ret = 0; + + if (final_x < 0 || final_y < 0 || init_y < 0) { + ret = -EINVAL; + goto exit; + } + + if (final_y <= init_y) { + dev_info(cs35l41->dev, "Vol ramp slope is not positive\n"); + cs35l41_set_vol((int)init_y, cs35l41); + usleep_range(final_x, final_x + 1); + cs35l41_set_vol((int)final_y, cs35l41); + goto exit; + } + + step_y = 1; /* 1/8 dB, min IC supported step */ + step_x = delta_x / delta_y; /* in micro-second */ + if (step_x == 0) + /* Take care of case where delta_x < delta_y */ + step_x = 1; + + dev_dbg(cs35l41->dev, "vol ramp delta x:%ld delta y:%ld step x:%ld\n", + delta_x, delta_y, step_x); + while (1) { + if (atomic_read(&cs35l41->vol_ctl.ramp_abort)) { + ret = -EINTR; + goto exit; + } + if (curr_x >= final_x) { + /* Delay is complete */ + cs35l41_set_vol((int)final_y, cs35l41); + break; + } + if (curr_y == final_y) { + /* Volume ramp is completed */ + usleep_range(final_x - curr_x, final_x - curr_x + 1); + break; + } + cs35l41_set_vol((int)curr_y, cs35l41); + curr_y += step_y; + curr_x += step_x; + usleep_range(step_x, step_x + 1); + } +exit: + return ret; +} + +static void cs35l41_vol_ramp(struct work_struct *wk) +{ + struct cs35l41_vol_ctl *vol_ctl; + struct cs35l41_private *cs35l41; + long final_x_knee, final_x_end; + long init_y_knee, init_y_end, final_y_end; + int ret = 0; + + vol_ctl = container_of(wk, struct cs35l41_vol_ctl, ramp_work); + cs35l41 = container_of(vol_ctl, struct cs35l41_private, vol_ctl); + dev_dbg(cs35l41->dev, "%s: dig_vol = %d\n", __func__, + cs35l41->vol_ctl.dig_vol); + + atomic_set(&cs35l41->vol_ctl.vol_ramp, 1); + /* + * vol_ramp must be true at this point, + * which guarantee ramp_init_att, ramp_knee_att, + * ramp_knee_time, ramp_end_time cannot be changed + */ + final_x_knee = (long)(cs35l41->vol_ctl.ramp_knee_time) * 1000; /* us */ + final_x_end = (long)(cs35l41->vol_ctl.ramp_end_time) * 1000; + /* 1/8 dB minimum step */ + init_y_knee = (long)(cs35l41->vol_ctl.dig_vol - + cs35l41->vol_ctl.ramp_init_att * 8); + if (init_y_knee < 0) + /* Hit floor */ + init_y_knee = 0; + init_y_end = (long)(cs35l41->vol_ctl.dig_vol - + cs35l41->vol_ctl.ramp_knee_att * 8); + if (init_y_end < 0) + /* Hit floor */ + init_y_end = 0; + final_y_end = (long)cs35l41->vol_ctl.dig_vol; + if (final_y_end < 0) + /* Hit floor */ + final_y_end = 0; + ret = cs35l41_vol_ramp0(cs35l41, final_x_knee, init_y_knee, init_y_end); + if (ret == -EINTR) { + /* Abort ramp */ + cs35l41_set_vol(cs35l41->vol_ctl.dig_vol, cs35l41); + goto exit; + } + ret = cs35l41_vol_ramp0(cs35l41, final_x_end, init_y_end, final_y_end); + if (ret == -EINTR) { + /* Abort ramp */ + cs35l41_set_vol(cs35l41->vol_ctl.dig_vol, cs35l41); + goto exit; + } +exit: + atomic_set(&cs35l41->vol_ctl.vol_ramp, 0); + /* Make manual ramp one-shot */ + atomic_set(&cs35l41->vol_ctl.manual_ramp, 0); +} + +static int cs35l41_get_vol(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = (long)cs35l41->vol_ctl.dig_vol; + + return 0; +} + +static int cs35l41_put_vol(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + int ret = 0; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > CS35L41_MAX_PCM_VOL) + return -EINVAL; + + if (atomic_read(&cs35l41->vol_ctl.vol_ramp) == 0) { + cs35l41->vol_ctl.dig_vol = + (int)ucontrol->value.integer.value[0]; + cs35l41_set_vol(cs35l41->vol_ctl.dig_vol, cs35l41); + } + + return ret; +} + +static int cs35l41_get_ramp_status(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = + (long)atomic_read(&cs35l41->vol_ctl.vol_ramp); + + return 0; +} + +static int cs35l41_put_ramp_status(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + dev_info(cs35l41->dev, "Volume ramp status cannot be set\n"); + return 0; +} + +static int cs35l41_get_manual_ramp(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = + (long)atomic_read(&cs35l41->vol_ctl.manual_ramp); + + return 0; +} + +static int cs35l41_put_manual_ramp(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > 1) + return -EINVAL; + + if (atomic_read(&cs35l41->vol_ctl.manual_ramp) == 0 && + ucontrol->value.integer.value[0] == 1) { + /* Rising edge */ + if (atomic_read(&cs35l41->vol_ctl.playback)) { + /* Stop existing ramp and start new ramp */ + cs35l41_abort_ramp(cs35l41); + queue_work(cs35l41->vol_ctl.ramp_wq, + &cs35l41->vol_ctl.ramp_work); + } + /* + * In else case, + * let DAPM event handle ramp on playback start. + */ + } else if (atomic_read(&cs35l41->vol_ctl.manual_ramp) == 1 && + ucontrol->value.integer.value[0] == 0) { + /* Falling edge */ + if (atomic_read(&cs35l41->vol_ctl.playback)) + /* Stop existing ramp */ + cs35l41_abort_ramp(cs35l41); + } + atomic_set(&cs35l41->vol_ctl.manual_ramp, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int cs35l41_get_init_attenuation(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = (long)cs35l41->vol_ctl.ramp_init_att; + return 0; +} + +static int cs35l41_put_init_attenuation(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > CS35L41_MAX_VOL_ATT) + return -EINVAL; + + if (atomic_read(&cs35l41->vol_ctl.vol_ramp) == 0) + cs35l41->vol_ctl.ramp_init_att = + (int)ucontrol->value.integer.value[0]; + return 0; +} + +static int cs35l41_get_knee_attenuation(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = (long)cs35l41->vol_ctl.ramp_knee_att; + return 0; +} + +static int cs35l41_put_knee_attenuation(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > CS35L41_MAX_VOL_ATT) + return -EINVAL; + + if (atomic_read(&cs35l41->vol_ctl.vol_ramp) == 0) + cs35l41->vol_ctl.ramp_knee_att = + (int)ucontrol->value.integer.value[0]; + return 0; +} + +static int cs35l41_get_ramp_end_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = (long)cs35l41->vol_ctl.ramp_end_time; + return 0; +} + +static int cs35l41_put_ramp_end_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > CS35L41_MAX_AUTO_RAMP_TIMEOUT) + return -EINVAL; + + if (atomic_read(&cs35l41->vol_ctl.vol_ramp) == 0) + cs35l41->vol_ctl.ramp_end_time = + (unsigned int)ucontrol->value.integer.value[0]; + return 0; +} + +static int cs35l41_get_auto_ramp_timeout(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = + (long)cs35l41->vol_ctl.auto_ramp_timeout; + return 0; +} + +static int cs35l41_put_auto_ramp_timeout(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > CS35L41_MAX_AUTO_RAMP_TIMEOUT) + return -EINVAL; + + cs35l41->vol_ctl.auto_ramp_timeout = + (unsigned int)ucontrol->value.integer.value[0]; + + return 0; +} + +static int cs35l41_get_ramp_knee_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = + (long)cs35l41->vol_ctl.ramp_knee_time; + return 0; +} + +static int cs35l41_put_ramp_knee_time(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component; + struct cs35l41_private *cs35l41; + + component = snd_soc_kcontrol_component(kcontrol); + cs35l41 = snd_soc_component_get_drvdata(component); + + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > CS35L41_MAX_AUTO_RAMP_TIMEOUT) + return -EINVAL; + + if (atomic_read(&cs35l41->vol_ctl.vol_ramp) == 0) + cs35l41->vol_ctl.ramp_knee_time = + (unsigned int)ucontrol->value.integer.value[0]; + return 0; +} + +static int cs35l41_channel_swap_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + int swapped = 0; + int val; + if (cs35l41->dsp.booted) { + wm_adsp_read_ctl(&cs35l41->dsp, "CH_BAL", (void *)&val, + sizeof(__be32)); + + dev_dbg(cs35l41->dev, "%s: CH_BAL = 0x%08x\n", __func__, + be32_to_cpu(val)); + swapped = (0x400000 == be32_to_cpu(val)) ? 1 : 0; + } + + ucontrol->value.integer.value[0] = swapped; + + return 0; +} + +static int cs35l41_channel_swap_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + int val; + + if (cs35l41->dsp.booted) { + if (ucontrol->value.integer.value[0]) + val = 0x400000; + else + val = 0; + + val = cpu_to_be32(val); + wm_adsp_write_ctl(&cs35l41->dsp, "CH_BAL", (void *)&val, + sizeof(__be32)); + } + + return 0; +} + +static const char *const cs35l41_output_dev_text[] = { + "Speaker", + "Receiver", +}; + +/* Ensure SPK and RCV defined values match array index */ +static const unsigned int cs35l41_output_dev_val[] = { + CS35L41_OUTPUT_DEV_SPK, + CS35L41_OUTPUT_DEV_RCV, +}; + +static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_output_dev, SND_SOC_NOPM, 0, 0, + cs35l41_output_dev_text, + cs35l41_output_dev_val); + +static const struct snd_kcontrol_new cs35l41_aud_controls[] = { + SOC_SINGLE_RANGE_EXT_TLV("Digital PCM Volume", SND_SOC_NOPM, 0, 0, + CS35L41_MAX_PCM_VOL, 0, cs35l41_get_vol, + cs35l41_put_vol, dig_vol_tlv), + SOC_SINGLE_TLV("AMP PCM Gain", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, + amp_gain_tlv), + SOC_SINGLE_RANGE("ASPTX1 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 0, 0, + 7, 0), + SOC_SINGLE_RANGE("ASPTX2 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 8, 0, + 7, 0), + SOC_SINGLE_RANGE("ASPTX3 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 16, + 0, 7, 0), + SOC_SINGLE_RANGE("ASPTX4 Slot Position", CS35L41_SP_FRAME_TX_SLOT, 24, + 0, 7, 0), + SOC_SINGLE_RANGE("ASPRX1 Slot Position", CS35L41_SP_FRAME_RX_SLOT, 0, 0, + 7, 0), + SOC_SINGLE_RANGE("ASPRX2 Slot Position", CS35L41_SP_FRAME_RX_SLOT, 8, 0, + 7, 0), + SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), + SOC_SINGLE_EXT("DSP Booted", SND_SOC_NOPM, 0, 1, 0, + cs35l41_halo_booted_get, cs35l41_halo_booted_put), + SOC_SINGLE_EXT("CCM Reset", CS35L41_DSP1_CCM_CORE_CTRL, 0, 1, 0, + cs35l41_ccm_reset_get, cs35l41_ccm_reset_put), + SOC_SINGLE_EXT("Force Interrupt", SND_SOC_NOPM, 0, 1, 0, + cs35l41_force_int_get, cs35l41_force_int_put), + SOC_SINGLE_EXT("Fast Use Case Switch Enable", SND_SOC_NOPM, 0, 1, 0, + cs35l41_fast_switch_en_get, cs35l41_fast_switch_en_put), + SOC_SINGLE_EXT("Firmware Reload Tuning", SND_SOC_NOPM, 0, 1, 0, + cs35l41_reload_tuning_get, cs35l41_reload_tuning_put), + SOC_ENUM_EXT("Channel Swap", channel_swap_enum, + cs35l41_channel_swap_get, cs35l41_channel_swap_put), + SOC_SINGLE("VPBR Config", CS35L41_VPBR_CFG, 0, 0x7FFFFFF, 0), + SOC_SINGLE("Noise Gate Config", CS35L41_NG_CFG, 0, 0x3FFF, 0), + SOC_SINGLE("GLOBAL_EN from GPIO Control", CS35L41_PWR_CTRL1, 8, 1, 0), + SOC_SINGLE("Boost Converter Enable", CS35L41_PWR_CTRL2, 4, 3, 0), + SOC_SINGLE("AMP Enable", CS35L41_PWR_CTRL2, 0, 1, 0), + WM_ADSP_FW_CONTROL("DSP1", 0), + SOC_SINGLE_BOOL_EXT("Safety Volume Ramp Status", 0, + cs35l41_get_ramp_status, cs35l41_put_ramp_status), + SOC_SINGLE_BOOL_EXT("Manual Ramp Control", 0, cs35l41_get_manual_ramp, + cs35l41_put_manual_ramp), + SOC_SINGLE_EXT("Initial Ramp Volume Attenuation", SND_SOC_NOPM, 0, + CS35L41_MAX_VOL_ATT, 0, cs35l41_get_init_attenuation, + cs35l41_put_init_attenuation), + SOC_SINGLE_EXT("Knee Ramp Volume Attenuation", SND_SOC_NOPM, 0, + CS35L41_MAX_VOL_ATT, 0, cs35l41_get_knee_attenuation, + cs35l41_put_knee_attenuation), + SOC_SINGLE_EXT("Ramp Knee Time", SND_SOC_NOPM, 0, + CS35L41_MAX_AUTO_RAMP_TIMEOUT, 0, + cs35l41_get_ramp_knee_time, cs35l41_put_ramp_knee_time), + SOC_SINGLE_EXT("Ramp End Time", SND_SOC_NOPM, 0, + CS35L41_MAX_AUTO_RAMP_TIMEOUT, 0, + cs35l41_get_ramp_end_time, cs35l41_put_ramp_end_time), + SOC_SINGLE_EXT("Auto Ramp Safety Timeout", SND_SOC_NOPM, 0, + CS35L41_MAX_AUTO_RAMP_TIMEOUT, 0, + cs35l41_get_auto_ramp_timeout, + cs35l41_put_auto_ramp_timeout), + SOC_VALUE_ENUM_EXT("Audio Output Device", cs35l41_output_dev, + cs35l41_get_output_dev, cs35l41_put_output_dev), + WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), +}; + +static const struct snd_kcontrol_new cs35l41_bst_ctl[] = { + SOC_SINGLE("Boost Class-H Tracking Enable", CS35L41_BSTCVRT_VCTRL2, 0, + 1, 0), + SOC_SINGLE("Boost Target Voltage", CS35L41_BSTCVRT_VCTRL1, 0, 0xAA, 0), + SOC_SINGLE_EXT("Hibernate Force Wake", SND_SOC_NOPM, 0, 1, 0, + cs35l41_hibernate_force_wake_get, + cs35l41_hibernate_force_wake_put), +}; + +static const struct snd_kcontrol_new cs35l41_lv_ctl[] = { + SOC_SINGLE("Boost Target Voltage", CS35L41_BSTCVRT_VCTRL1, 0, 0x8C, 0), +}; + +static const struct cs35l41_otp_map_element_t * +cs35l41_find_otp_map(u32 otp_id, u32 devid_otp) +{ + int i; + + for (i = 0; i < cs35l41_otp_maps.len; i++) { + if (cs35l41_otp_maps.map[i].id == otp_id && + cs35l41_otp_maps.map[i].devid_otp == devid_otp) + return &cs35l41_otp_maps.map[i]; + } + + return NULL; +} + +static int cs35l41_otp_unpack(void *data) +{ + struct cs35l41_private *cs35l41 = data; + u32 *otp_mem; + int i; + int bit_offset, word_offset; + unsigned int bit_sum = 8; + u32 otp_val, otp_id_reg; + const struct cs35l41_otp_map_element_t *otp_map_match; + const struct cs35l41_otp_packed_element_t *otp_map; + int ret; + struct spi_device *spi = NULL; + u32 orig_spi_freq = 0; + u32 devid_otp; + + otp_mem = kmalloc_array(32, sizeof(*otp_mem), GFP_KERNEL); + if (!otp_mem) + return -ENOMEM; + + ret = regmap_read(cs35l41->regmap, CS35L41_OTPID, &otp_id_reg); + if (ret < 0) { + dev_err(cs35l41->dev, "Read OTP ID failed\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + + ret = regmap_read(cs35l41->regmap, CS35L41_DEVID_OTP, &devid_otp); + if (ret < 0) { + dev_err(cs35l41->dev, "Read DEVID OTP failed\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + + otp_map_match = cs35l41_find_otp_map(otp_id_reg, devid_otp); + + if (otp_map_match == NULL) { + dev_err(cs35l41->dev, "OTP Map matching ID %d not found\n", + otp_id_reg); + ret = -EINVAL; + goto err_otp_unpack; + } + + if (cs35l41->bus_spi) { + spi = to_spi_device(cs35l41->dev); + orig_spi_freq = spi->max_speed_hz; + spi->max_speed_hz = CS35L41_SPI_MAX_FREQ_OTP; + spi_setup(spi); + } + + ret = regmap_bulk_read(cs35l41->regmap, CS35L41_OTP_MEM0, otp_mem, + CS35L41_OTP_SIZE_WORDS); + if (ret < 0) { + dev_err(cs35l41->dev, "Read OTP Mem failed\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + + if (cs35l41->bus_spi) { + spi->max_speed_hz = orig_spi_freq; + spi_setup(spi); + } + + otp_map = otp_map_match->map; + + bit_offset = otp_map_match->bit_offset; + word_offset = otp_map_match->word_offset; + + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000055); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Unlock key failed 1/2\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000AA); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Unlock key failed 2/2\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + + for (i = 0; i < otp_map_match->num_elements; i++) { + dev_dbg(cs35l41->dev, + "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d\n", + bit_offset, word_offset, bit_sum % 32); + if (bit_offset + otp_map[i].size - 1 >= 32) { + otp_val = (otp_mem[word_offset] & + GENMASK(31, bit_offset)) >> + bit_offset; + otp_val |= + (otp_mem[++word_offset] & + GENMASK(bit_offset + otp_map[i].size - 33, 0)) + << (32 - bit_offset); + bit_offset += otp_map[i].size - 32; + } else { + otp_val = (otp_mem[word_offset] & + GENMASK(bit_offset + otp_map[i].size - 1, + bit_offset)) >> + bit_offset; + bit_offset += otp_map[i].size; + } + bit_sum += otp_map[i].size; + + if (bit_offset == 32) { + bit_offset = 0; + word_offset++; + } + + if (otp_map[i].reg != 0) { + ret = regmap_update_bits( + cs35l41->regmap, otp_map[i].reg, + GENMASK(otp_map[i].shift + otp_map[i].size - 1, + otp_map[i].shift), + otp_val << otp_map[i].shift); + if (ret < 0) { + dev_err(cs35l41->dev, "Write OTP val failed\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + } + } + + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000CC); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Lock key failed 1/2\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000033); + if (ret < 0) { + dev_err(cs35l41->dev, "Write Lock key failed 2/2\n"); + ret = -EINVAL; + goto err_otp_unpack; + } + ret = 0; + +err_otp_unpack: + kfree(otp_mem); + return ret; +} + +static irqreturn_t cs35l41_irq(int irq, void *data) +{ + struct cs35l41_private *cs35l41 = data; + unsigned int status[4]; + unsigned int masks[4]; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(status); i++) { + regmap_read(cs35l41->regmap, + CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), + &status[i]); + regmap_read(cs35l41->regmap, + CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), + &masks[i]); + } + + /* Check to see if unmasked bits are active */ + if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && + !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) + return IRQ_NONE; + + /* + * The following interrupts require a + * protection release cycle to get the + * speaker out of Safe-Mode. + */ + if (status[0] & CS35L41_AMP_SHORT_ERR) { + dev_crit(cs35l41->dev, "Amp short error\n"); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_AMP_SHORT_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_AMP_SHORT_ERR_RLS, + CS35L41_AMP_SHORT_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_AMP_SHORT_ERR_RLS, 0); + } + + if (status[0] & CS35L41_TEMP_WARN) { + dev_crit(cs35l41->dev, "Over temperature warning\n"); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_TEMP_WARN); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_WARN_ERR_RLS, + CS35L41_TEMP_WARN_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_WARN_ERR_RLS, 0); + } + + if (status[0] & CS35L41_TEMP_ERR) { + dev_crit(cs35l41->dev, "Over temperature error\n"); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_TEMP_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_ERR_RLS, CS35L41_TEMP_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_TEMP_ERR_RLS, 0); + } + + if (status[0] & CS35L41_BST_OVP_ERR) { + dev_crit(cs35l41->dev, "VBST Over Voltage error\n"); + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, + CS35L41_BST_EN_MASK, 0); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_BST_OVP_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_OVP_ERR_RLS, + CS35L41_BST_OVP_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_OVP_ERR_RLS, 0); + regmap_update_bits( + cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); + } + + if (status[0] & CS35L41_BST_DCM_UVP_ERR) { + dev_crit(cs35l41->dev, "DCM VBST Under Voltage Error\n"); + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, + CS35L41_BST_EN_MASK, 0); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_BST_DCM_UVP_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_UVP_ERR_RLS, + CS35L41_BST_UVP_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_UVP_ERR_RLS, 0); + regmap_update_bits( + cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); + } + + if (status[0] & CS35L41_BST_SHORT_ERR) { + dev_crit(cs35l41->dev, "LBST error: powering off!\n"); + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, + CS35L41_BST_EN_MASK, 0); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_BST_SHORT_ERR); + regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_SHORT_ERR_RLS, + CS35L41_BST_SHORT_ERR_RLS); + regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, + CS35L41_BST_SHORT_ERR_RLS, 0); + regmap_update_bits( + cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK, + CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); + } + + if (status[3] & CS35L41_OTP_BOOT_DONE) { + regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, + CS35L41_OTP_BOOT_DONE, + CS35L41_OTP_BOOT_DONE); + } + +#if defined(BRINGUP_IRQ_VERIFY) + if (status[0] & CS35L41_PUP_DONE_MASK) { + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_PUP_DONE_MASK); + dev_dbg(cs35l41->dev, "AMP powered up\n"); + } +#endif + + return IRQ_HANDLED; +} + +static const struct reg_sequence cs35l41_pup_patch[] = { + { 0x00000040, 0x00000055 }, { 0x00000040, 0x000000AA }, + { 0x00002084, 0x002F1AA0 }, { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +static const struct reg_sequence cs35l41_pdn_patch[] = { + { 0x00000040, 0x00000055 }, { 0x00000040, 0x000000AA }, + { 0x00002084, 0x002F1AA3 }, { 0x00000040, 0x000000CC }, + { 0x00000040, 0x00000033 }, +}; + +static void cs35l41_hibernate_work(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct cs35l41_private *cs35l41 = + container_of(dwork, struct cs35l41_private, hb_work); + + mutex_lock(&cs35l41->hb_lock); + cs35l41_enter_hibernate(cs35l41); + mutex_unlock(&cs35l41->hb_lock); +} + +static int cs35l41_hibernate(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + int ret = 0; + + if (!cs35l41->dsp.running || + cs35l41->amp_hibernate == CS35L41_HIBERNATE_INCOMPATIBLE || + cs35l41->hibernate_force_wake) + return 0; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + cancel_delayed_work(&cs35l41->hb_work); + mutex_lock(&cs35l41->hb_lock); + ret = cs35l41_exit_hibernate(cs35l41); + mutex_unlock(&cs35l41->hb_lock); + break; + case SND_SOC_DAPM_POST_PMD: + queue_delayed_work(cs35l41->wq, &cs35l41->hb_work, + msecs_to_jiffies(2000)); + break; + default: + dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); + ret = -EINVAL; + } + return ret; +} + +static bool cs35l41_need_auto_vol_ramp(struct cs35l41_private *cs35l41) +{ + bool ramp = false; + ktime_t curr_timestamp; + s64 dev_timeout = (s64)cs35l41->vol_ctl.auto_ramp_timeout * 1000000; + s64 elapsed_time; + + if (cs35l41->vol_ctl.prev_active_dev == CS35L41_OUTPUT_DEV_RCV && + cs35l41->vol_ctl.output_dev == CS35L41_OUTPUT_DEV_SPK) { + if (cs35l41->vol_ctl.auto_ramp_timeout == 0) { + /* Never ramp */ + } else if (cs35l41->vol_ctl.auto_ramp_timeout == + CS35L41_MAX_AUTO_RAMP_TIMEOUT) { + /* Always ramp */ + ramp = true; + } else { + /* + * Guaranteed: + * 0 < auto_ramp_timeout < CS35L41_MAX_AUTO_RAMP_TIMEOUT + */ + curr_timestamp = ktime_get(); + elapsed_time = + ktime_to_ns(curr_timestamp) - + ktime_to_ns(cs35l41->vol_ctl.dev_timestamp); + if (elapsed_time < dev_timeout) + ramp = true; + dev_dbg(cs35l41->dev, + "elapsed_time:%lld dev_timeout:%lld\n", + elapsed_time, dev_timeout); + } + } + + return ramp; +} + +static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + enum cs35l41_cspl_mboxcmd mboxcmd = CSPL_MBOX_CMD_NONE; + int ret = 0; + int i; + bool pdn; + unsigned int val; + + dev_dbg(cs35l41->dev, "%s: event = 0x%x\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_multi_reg_write_bypassed(cs35l41->regmap, + cs35l41_pup_patch, + ARRAY_SIZE(cs35l41_pup_patch)); + + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, + CS35L41_GLOBAL_EN_MASK, + 1 << CS35L41_GLOBAL_EN_SHIFT); + + usleep_range(1000, 1100); + + atomic_set(&cs35l41->vol_ctl.playback, 1); + if (atomic_read(&cs35l41->vol_ctl.manual_ramp) || + cs35l41_need_auto_vol_ramp(cs35l41)) + /* Enable volume ramp */ + queue_work(cs35l41->vol_ctl.ramp_wq, + &cs35l41->vol_ctl.ramp_work); + break; + case SND_SOC_DAPM_POST_PMD: + if (cs35l41->dsp.running) { + if (cs35l41->reload_tuning) { + mboxcmd = CSPL_MBOX_CMD_STOP_PRE_REINIT; + /* + * Reset reload_tuning, so driver does not + * continuously reload tuning file + */ + cs35l41->reload_tuning = false; + } else { + mboxcmd = CSPL_MBOX_CMD_PAUSE; + } + ret = cs35l41_set_csplmboxcmd(cs35l41, mboxcmd); + } + + regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, + CS35L41_GLOBAL_EN_MASK, 0); + + pdn = false; + for (i = 0; i < 100; i++) { + regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + &val); + if (val & CS35L41_PDN_DONE_MASK) { + pdn = true; + break; + } + usleep_range(1000, 1010); + } + + if (!pdn) + dev_warn(cs35l41->dev, "PDN failed\n"); + + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, + CS35L41_PDN_DONE_MASK); + + regmap_multi_reg_write_bypassed(cs35l41->regmap, + cs35l41_pdn_patch, + ARRAY_SIZE(cs35l41_pdn_patch)); + atomic_set(&cs35l41->vol_ctl.playback, 0); + cs35l41_abort_ramp(cs35l41); + cs35l41->vol_ctl.prev_active_dev = cs35l41->vol_ctl.output_dev; + if (cs35l41->vol_ctl.output_dev == CS35L41_OUTPUT_DEV_RCV && + cs35l41->vol_ctl.auto_ramp_timeout > 0 && + cs35l41->vol_ctl.auto_ramp_timeout < + CS35L41_MAX_AUTO_RAMP_TIMEOUT) + /* Auto Receiver Timeout is used */ + cs35l41->vol_ctl.dev_timestamp = ktime_get(); + break; + default: + dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); + ret = -EINVAL; + } + return ret; +} + +static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { + + SND_SOC_DAPM_SPK("DSP1 Preload", NULL), + SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, + cs35l41_dsp_power_ev, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, + cs35l41_dsp_load_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_OUTPUT("SPK"), + + SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), + SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), + SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), + + SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L41_PWR_CTRL2, 12, 0), + SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L41_PWR_CTRL2, 13, 0), + SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L41_PWR_CTRL2, 8, 0), + SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L41_PWR_CTRL2, 9, 0), + SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, CS35L41_PWR_CTRL2, 10, 0), + SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), + + SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, + cs35l41_main_amp_event, + SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_INPUT("VP"), + SND_SOC_DAPM_INPUT("VBST"), + SND_SOC_DAPM_INPUT("ISENSE"), + SND_SOC_DAPM_INPUT("VSENSE"), + SND_SOC_DAPM_INPUT("TEMP"), + + SND_SOC_DAPM_MUX("ASPTX Ref", SND_SOC_NOPM, 0, 0, &virt_mux), + SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), + SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), + SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), + SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), + SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), + SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), + SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), + SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), + SND_SOC_DAPM_SWITCH("VBSTMON Output", SND_SOC_NOPM, 0, 0, + &vbstmon_out_ctrl), +}; + +static const struct snd_soc_dapm_widget cs35l41_hib_widgets[] = { + SND_SOC_DAPM_SUPPLY("Hibernate", SND_SOC_NOPM, 0, 0, cs35l41_hibernate, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), +}; + +static const struct snd_soc_dapm_route cs35l41_audio_map[] = { + + { "DSP1", NULL, "DSP1 Preloader" }, + { "DSP1 Preload", NULL, "DSP1 Preloader" }, + + { "DSP RX1 Source", "VMON", "VMON ADC" }, + { "DSP RX1 Source", "IMON", "IMON ADC" }, + { "DSP RX1 Source", "VPMON", "VPMON ADC" }, + { "DSP RX1 Source", "DSPTX1", "DSP1" }, + { "DSP RX1 Source", "DSPTX2", "DSP1" }, + { "DSP RX1 Source", "ASPRX1", "ASPRX1" }, + { "DSP RX1 Source", "ASPRX2", "ASPRX2" }, + { "DSP RX1 Source", "Zero", "ASPRX1" }, + { "DSP1", NULL, "DSP RX1 Source" }, + + { "DSP RX2 Source", "VMON", "VMON ADC" }, + { "DSP RX2 Source", "IMON", "IMON ADC" }, + { "DSP RX2 Source", "VPMON", "VPMON ADC" }, + { "DSP RX2 Source", "DSPTX1", "DSP1" }, + { "DSP RX2 Source", "DSPTX2", "DSP1" }, + { "DSP RX2 Source", "ASPRX1", "ASPRX1" }, + { "DSP RX2 Source", "ASPRX2", "ASPRX2" }, + { "DSP RX2 Source", "Zero", "ASPRX1" }, + { "DSP1", NULL, "DSP RX2 Source" }, + + { "ASP TX1 Source", "VMON", "VMON ADC" }, + { "ASP TX1 Source", "IMON", "IMON ADC" }, + { "ASP TX1 Source", "VPMON", "VPMON ADC" }, + { "ASP TX1 Source", "VBSTMON", "VBSTMON ADC" }, + { "ASP TX1 Source", "DSPTX1", "DSP1" }, + { "ASP TX1 Source", "DSPTX2", "DSP1" }, + { "ASP TX1 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX1 Source", "ASPRX2", "ASPRX2" }, + { "ASP TX2 Source", "VMON", "VMON ADC" }, + { "ASP TX2 Source", "IMON", "IMON ADC" }, + { "ASP TX2 Source", "VPMON", "VPMON ADC" }, + { "ASP TX2 Source", "VBSTMON", "VBSTMON ADC" }, + { "ASP TX2 Source", "DSPTX1", "DSP1" }, + { "ASP TX2 Source", "DSPTX2", "DSP1" }, + { "ASP TX2 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX2 Source", "ASPRX2", "ASPRX2" }, + { "ASP TX3 Source", "VMON", "VMON ADC" }, + { "ASP TX3 Source", "IMON", "IMON ADC" }, + { "ASP TX3 Source", "VPMON", "VPMON ADC" }, + { "ASP TX3 Source", "VBSTMON", "VBSTMON ADC" }, + { "ASP TX3 Source", "DSPTX1", "DSP1" }, + { "ASP TX3 Source", "DSPTX2", "DSP1" }, + { "ASP TX3 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX3 Source", "ASPRX2", "ASPRX2" }, + { "ASP TX4 Source", "VMON", "VMON ADC" }, + { "ASP TX4 Source", "IMON", "IMON ADC" }, + { "ASP TX4 Source", "VPMON", "VPMON ADC" }, + { "ASP TX4 Source", "VBSTMON", "VBSTMON ADC" }, + { "ASP TX4 Source", "DSPTX1", "DSP1" }, + { "ASP TX4 Source", "DSPTX2", "DSP1" }, + { "ASP TX4 Source", "ASPRX1", "ASPRX1" }, + { "ASP TX4 Source", "ASPRX2", "ASPRX2" }, + { "ASPTX1", NULL, "ASP TX1 Source" }, + { "ASPTX2", NULL, "ASP TX2 Source" }, + { "ASPTX3", NULL, "ASP TX3 Source" }, + { "ASPTX4", NULL, "ASP TX4 Source" }, + { "AMP Capture", NULL, "ASPTX1" }, + { "AMP Capture", NULL, "ASPTX2" }, + { "AMP Capture", NULL, "ASPTX3" }, + { "AMP Capture", NULL, "ASPTX4" }, + + { "VMON ADC", NULL, "ASPRX1" }, + { "IMON ADC", NULL, "ASPRX1" }, + { "VPMON ADC", NULL, "ASPRX1" }, + { "TEMPMON ADC", NULL, "ASPRX1" }, + { "VBSTMON ADC", NULL, "ASPRX1" }, + + { "VBSTMON Output", "Switch", "VBST" }, + { "CLASS H", NULL, "VBSTMON Output" }, + { "VBSTMON ADC", NULL, "VBSTMON Output" }, + + { "DSP1", NULL, "IMON ADC" }, + { "DSP1", NULL, "VMON ADC" }, + { "DSP1", NULL, "VBSTMON ADC" }, + { "DSP1", NULL, "VPMON ADC" }, + { "DSP1", NULL, "TEMPMON ADC" }, + + { "ASPRX1", NULL, "AMP Playback" }, + { "ASPRX2", NULL, "AMP Playback" }, + { "DRE", "DRE Switch", "CLASS H" }, + { "ASPTX Ref", "Ref", "ASPTX1" }, + { "ASPTX Ref", "Ref", "ASPTX2" }, + { "Main AMP", NULL, "ASPTX Ref" }, + { "Main AMP", NULL, "CLASS H" }, + { "Main AMP", NULL, "DRE" }, + { "SPK", NULL, "Main AMP" }, + + { "PCM Source", "ASP", "ASPRX1" }, + { "PCM Source", "DSP", "DSP1" }, + { "CLASS H", NULL, "PCM Source" }, + +}; + +static const struct snd_soc_dapm_route cs35l41_hib_map[] = { + { "SPK", NULL, "Hibernate" }, +}; + +static const struct wm_adsp_region cs35l41_dsp1_regions[] = { + { .type = WMFW_HALO_PM_PACKED, .base = CS35L41_DSP1_PMEM_0 }, + { .type = WMFW_HALO_XM_PACKED, .base = CS35L41_DSP1_XMEM_PACK_0 }, + { .type = WMFW_HALO_YM_PACKED, .base = CS35L41_DSP1_YMEM_PACK_0 }, + { .type = WMFW_ADSP2_XM, .base = CS35L41_DSP1_XMEM_UNPACK24_0 }, + { .type = WMFW_ADSP2_YM, .base = CS35L41_DSP1_YMEM_UNPACK24_0 }, +}; + +static int cs35l41_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) +{ + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(codec_dai->component); + unsigned int asp_fmt, lrclk_fmt, sclk_fmt, slave_mode; + + dev_dbg(cs35l41->dev, "%s: fmt = 0x%x\n", __func__, fmt); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + slave_mode = 1; + break; + case SND_SOC_DAIFMT_CBS_CFS: + slave_mode = 0; + break; + default: + dev_warn(cs35l41->dev, "%s: Mixed master mode unsupported\n", + __func__); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_DSP_A: + asp_fmt = 0; + cs35l41->i2s_mode = false; + cs35l41->dspa_mode = true; + break; + case SND_SOC_DAIFMT_I2S: + asp_fmt = 2; + cs35l41->i2s_mode = true; + cs35l41->dspa_mode = false; + break; + default: + dev_warn(cs35l41->dev, + "%s: Invalid or unsupported DAI format\n", __func__); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_IF: + lrclk_fmt = 1; + sclk_fmt = 0; + break; + case SND_SOC_DAIFMT_IB_NF: + lrclk_fmt = 0; + sclk_fmt = 1; + break; + case SND_SOC_DAIFMT_IB_IF: + lrclk_fmt = 1; + sclk_fmt = 1; + break; + case SND_SOC_DAIFMT_NB_NF: + lrclk_fmt = 0; + sclk_fmt = 0; + break; + default: + dev_warn(cs35l41->dev, "%s: Invalid DAI clock INV\n", __func__); + return -EINVAL; + } + + cs35l41->reset_cache.slave_mode = slave_mode; + cs35l41->reset_cache.asp_fmt = asp_fmt; + cs35l41->reset_cache.lrclk_fmt = lrclk_fmt; + cs35l41->reset_cache.sclk_fmt = sclk_fmt; + /* Amp is in reset. Cache values to be applied later. */ + if (cs35l41->amp_hibernate == CS35L41_HIBERNATE_STANDBY) + return 0; + + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_FMT_MASK, + asp_fmt << CS35L41_ASP_FMT_SHIFT); + + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_MSTR_MASK, + slave_mode << CS35L41_SCLK_MSTR_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_MSTR_MASK, + slave_mode << CS35L41_LRCLK_MSTR_SHIFT); + + cs35l41->lrclk_fmt = lrclk_fmt; + cs35l41->sclk_fmt = sclk_fmt; + + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_INV_MASK, + lrclk_fmt << CS35L41_LRCLK_INV_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_INV_MASK, + sclk_fmt << CS35L41_SCLK_INV_SHIFT); + + return 0; +} + +struct cs35l41_global_fs_config { + int rate; + int fs_cfg; +}; + +static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { + { 12000, 0x01 }, { 24000, 0x02 }, { 48000, 0x03 }, { 96000, 0x04 }, + { 192000, 0x05 }, { 11025, 0x09 }, { 22050, 0x0A }, { 44100, 0x0B }, + { 88200, 0x0C }, { 176400, 0x0D }, { 8000, 0x11 }, { 16000, 0x12 }, + { 32000, 0x13 }, +}; + +static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(dai->component); + int i; + unsigned int rate = params_rate(params); + u8 asp_width, asp_wl; + + for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { + if (rate == cs35l41_fs_rates[i].rate) + break; + } + + asp_wl = params_width(params); + asp_width = params_physical_width(params); + + dev_dbg(cs35l41->dev, "%s: rate = %u, asp_wl = %u, asp_width = %u\n", + __func__, rate, asp_wl, asp_width); + + cs35l41->reset_cache.asp_wl = asp_wl; + cs35l41->reset_cache.asp_width = asp_width; + if (i < ARRAY_SIZE(cs35l41_fs_rates)) + cs35l41->reset_cache.fs_cfg = cs35l41_fs_rates[i].fs_cfg; + + /* Amp is in reset. Cache values to be applied later */ + if (cs35l41->amp_hibernate == CS35L41_HIBERNATE_STANDBY) + return 0; + + regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, + CS35L41_GLOBAL_FS_MASK, + cs35l41_fs_rates[i].fs_cfg + << CS35L41_GLOBAL_FS_SHIFT); + + cs35l41_component_set_sysclk(dai->component, 0, 0, 8 * rate * asp_width, + 0); + + /* Note: To keep RX and TX using same data width */ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || + substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + //if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_WIDTH_RX_MASK, + asp_width << CS35L41_ASP_WIDTH_RX_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, + CS35L41_ASP_RX_WL_MASK, + asp_wl << CS35L41_ASP_RX_WL_SHIFT); + if (cs35l41->i2s_mode) { + regmap_update_bits( + cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT, + CS35L41_ASP_RX1_SLOT_MASK, + ((cs35l41->pdata.right_channel) ? 1 : 0) + << CS35L41_ASP_RX1_SLOT_SHIFT); + regmap_update_bits( + cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT, + CS35L41_ASP_RX2_SLOT_MASK, + ((cs35l41->pdata.right_channel) ? 0 : 1) + << CS35L41_ASP_RX2_SLOT_SHIFT); + } + //} else { + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_WIDTH_TX_MASK, + asp_width << CS35L41_ASP_WIDTH_TX_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, + CS35L41_ASP_TX_WL_MASK, + asp_wl << CS35L41_ASP_TX_WL_SHIFT); + } + + return 0; +} + +static int cs35l41_get_clk_config(int freq) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { + if (cs35l41_pll_sysclk[i].freq == freq) + return cs35l41_pll_sysclk[i].clk_cfg; + } + + return -EINVAL; +} + +static const unsigned int cs35l41_src_rates[] = { 8000, 12000, 11025, 16000, + 22050, 24000, 32000, 44100, + 48000, 88200, 96000, 176400, + 192000 }; + +static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { + .count = ARRAY_SIZE(cs35l41_src_rates), + .list = cs35l41_src_rates, +}; + +static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(dai->component); + + dev_dbg(cs35l41->dev, "%s\n", __func__); + cs35l41_set_dai_fmt(dai, SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_DSP_A); + + if (substream->runtime) + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &cs35l41_constraints); + return 0; +} + +static int cs35l41_component_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, + unsigned int freq, int dir) +{ + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + dev_dbg(cs35l41->dev, + "%s: clk_id = %d, source = %d, freq = %u, dir = %d\n", __func__, + clk_id, source, freq, dir); + + cs35l41->extclk_freq = freq; + + switch (clk_id) { + case 0: + cs35l41->clksrc = CS35L41_PLLSRC_SCLK; + break; + case 1: + cs35l41->clksrc = CS35L41_PLLSRC_LRCLK; + break; + case 2: + cs35l41->clksrc = CS35L41_PLLSRC_PDMCLK; + break; + case 3: + cs35l41->clksrc = CS35L41_PLLSRC_SELF; + break; + case 4: + cs35l41->clksrc = CS35L41_PLLSRC_MCLK; + break; + default: + dev_err(cs35l41->dev, "Invalid CLK Config\n"); + return -EINVAL; + } + + cs35l41->extclk_cfg = cs35l41_get_clk_config(freq); + + if (cs35l41->extclk_cfg < 0) { + dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", + cs35l41->extclk_cfg, freq); + return -EINVAL; + } + + cs35l41->reset_cache.extclk_cfg = true; + /* Amp is in reset. Set flag to restore clock config */ + if (cs35l41->amp_hibernate == CS35L41_HIBERNATE_STANDBY) + return 0; + + regmap_read(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, &freq); + freq &= (CS35L41_REFCLK_FREQ_MASK | CS35L41_PLL_CLK_EN_MASK | + CS35L41_PLL_CLK_SEL_MASK); + if ((cs35l41->extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT | + CS35L41_PLL_CLK_EN_MASK | cs35l41->clksrc) == freq) { + dev_dbg(cs35l41->dev, "%s: Ignore duplicate PLL setting\n", + __func__); + return 0; + } + + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_OPENLOOP_MASK, + 1 << CS35L41_PLL_OPENLOOP_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_REFCLK_FREQ_MASK, + cs35l41->extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_EN_MASK, + 0 << CS35L41_PLL_CLK_EN_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_SEL_MASK, cs35l41->clksrc); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_OPENLOOP_MASK, + 0 << CS35L41_PLL_OPENLOOP_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_EN_MASK, + 1 << CS35L41_PLL_CLK_EN_SHIFT); + + return 0; +} + +static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(dai->component); + unsigned int fs1_val = 0; + unsigned int fs2_val = 0; + unsigned int val; + + dev_dbg(cs35l41->dev, "%s: clk_id = %d, freq = %u, dir = %d\n", + __func__, clk_id, freq, dir); + + if (cs35l41_get_clk_config(freq) < 0) { + dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); + return -EINVAL; + } + + /* Need the SCLK Frequency regardless of sysclk source */ + cs35l41->sclk = freq; + + dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); + if (cs35l41->sclk > 6000000) { + fs1_val = 3 * 4 + 4; + fs2_val = 8 * 4 + 4; + } + + if (cs35l41->sclk <= 6000000) { + fs1_val = 3 * ((24000000 + cs35l41->sclk - 1) / cs35l41->sclk) + + 4; + fs2_val = 5 * ((24000000 + cs35l41->sclk - 1) / cs35l41->sclk) + + 4; + } + + val = fs1_val; + val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000055); + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000AA); + regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000CC); + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000033); + + return 0; +} + +static int cs35l41_boost_config(struct cs35l41_private *cs35l41, int boost_ind, + int boost_cap, int boost_ipk) +{ + int ret; + unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; + struct regmap *regmap = cs35l41->regmap; + struct device *dev = cs35l41->dev; + + switch (boost_ind) { + case 1000: /* 1.0 uH */ + bst_lbst_val = 0; + break; + case 1200: /* 1.2 uH */ + bst_lbst_val = 1; + break; + case 1500: /* 1.5 uH */ + bst_lbst_val = 2; + break; + case 2200: /* 2.2 uH */ + bst_lbst_val = 3; + break; + default: + dev_err(dev, "Invalid boost inductor value: %d nH\n", + boost_ind); + return -EINVAL; + } + + switch (boost_cap) { + case 0 ... 19: + bst_cbst_range = 0; + break; + case 20 ... 50: + bst_cbst_range = 1; + break; + case 51 ... 100: + bst_cbst_range = 2; + break; + case 101 ... 200: + bst_cbst_range = 3; + break; + default: /* 201 uF and greater */ + bst_cbst_range = 4; + } + + ret = regmap_update_bits( + regmap, CS35L41_BSTCVRT_COEFF, CS35L41_BST_K1_MASK, + cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] + << CS35L41_BST_K1_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost K1 coefficient\n"); + return ret; + } + + ret = regmap_update_bits( + regmap, CS35L41_BSTCVRT_COEFF, CS35L41_BST_K2_MASK, + cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range] + << CS35L41_BST_K2_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost K2 coefficient\n"); + return ret; + } + + ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, + CS35L41_BST_SLOPE_MASK, + cs35l41_bst_slope_table[bst_lbst_val] + << CS35L41_BST_SLOPE_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost slope coefficient\n"); + return ret; + } + + ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, + CS35L41_BST_LBST_VAL_MASK, + bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost inductor value\n"); + return ret; + } + + if ((boost_ipk < 1600) || (boost_ipk > 4500)) { + dev_err(dev, "Invalid boost inductor peak current: %d mA\n", + boost_ipk); + return -EINVAL; + } + bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; + + ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, + CS35L41_BST_IPK_MASK, + bst_ipk_scaled << CS35L41_BST_IPK_SHIFT); + if (ret) { + dev_err(dev, "Failed to write boost inductor peak current\n"); + return ret; + } + + return 0; +} + +static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) +{ + struct classh_cfg *classh = &cs35l41->pdata.classh_config; + int ret; + u32 devid_otp; + + /* Set Platform Data */ + /* Required */ + if (cs35l41->pdata.bst_ipk && cs35l41->pdata.bst_ind && + cs35l41->pdata.bst_cap) { + ret = cs35l41_boost_config(cs35l41, cs35l41->pdata.bst_ind, + cs35l41->pdata.bst_cap, + cs35l41->pdata.bst_ipk); + if (ret) { + dev_err(cs35l41->dev, "Error in Boost DT config\n"); + return ret; + } + } else { + dev_err(cs35l41->dev, "Incomplete Boost component DT config\n"); + return -EINVAL; + } + + /* Optional */ + if (cs35l41->pdata.sclk_frc) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_FRC_MASK, + cs35l41->pdata.sclk_frc + << CS35L41_SCLK_FRC_SHIFT); + + if (cs35l41->pdata.lrclk_frc) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_FRC_MASK, + cs35l41->pdata.lrclk_frc + << CS35L41_LRCLK_FRC_SHIFT); + + if (cs35l41->pdata.amp_gain_zc) + regmap_update_bits(cs35l41->regmap, CS35L41_AMP_GAIN_CTRL, + CS35L41_AMP_GAIN_ZC_MASK, + cs35l41->pdata.amp_gain_zc + << CS35L41_AMP_GAIN_ZC_SHIFT); + + if (cs35l41->pdata.bst_vctrl) + regmap_update_bits(cs35l41->regmap, CS35L41_BSTCVRT_VCTRL1, + CS35L41_BST_CTL_MASK, + cs35l41->pdata.bst_vctrl); + + if (cs35l41->pdata.temp_warn_thld) + regmap_update_bits(cs35l41->regmap, CS35L41_DTEMP_WARN_THLD, + CS35L41_TEMP_THLD_MASK, + cs35l41->pdata.temp_warn_thld); + + if (cs35l41->pdata.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && + cs35l41->pdata.dout_hiz >= 0) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, + CS35L41_ASP_DOUT_HIZ_MASK, + cs35l41->pdata.dout_hiz); + + if (cs35l41->pdata.invert_pcm) + regmap_update_bits(cs35l41->regmap, CS35L41_AMP_DIG_VOL_CTRL, + CS35L41_AMP_INV_PCM_MASK, + cs35l41->pdata.invert_pcm + << CS35L41_AMP_INV_PCM_SHIFT); + + if (cs35l41->pdata.dsp_ng_enable) { + regmap_update_bits(cs35l41->regmap, CS35L41_MIXER_NGATE_CH1_CFG, + CS35L41_DSP_NG_ENABLE_MASK, + CS35L41_DSP_NG_ENABLE_MASK); + regmap_update_bits(cs35l41->regmap, CS35L41_MIXER_NGATE_CH2_CFG, + CS35L41_DSP_NG_ENABLE_MASK, + CS35L41_DSP_NG_ENABLE_MASK); + + if (cs35l41->pdata.dsp_ng_pcm_thld) { + regmap_update_bits(cs35l41->regmap, + CS35L41_MIXER_NGATE_CH1_CFG, + CS35L41_DSP_NG_THLD_MASK, + cs35l41->pdata.dsp_ng_pcm_thld); + regmap_update_bits(cs35l41->regmap, + CS35L41_MIXER_NGATE_CH2_CFG, + CS35L41_DSP_NG_THLD_MASK, + cs35l41->pdata.dsp_ng_pcm_thld); + } + + if (cs35l41->pdata.dsp_ng_delay) { + regmap_update_bits( + cs35l41->regmap, CS35L41_MIXER_NGATE_CH1_CFG, + CS35L41_DSP_NG_DELAY_MASK, + cs35l41->pdata.dsp_ng_delay + << CS35L41_DSP_NG_DELAY_SHIFT); + regmap_update_bits( + cs35l41->regmap, CS35L41_MIXER_NGATE_CH2_CFG, + CS35L41_DSP_NG_DELAY_MASK, + cs35l41->pdata.dsp_ng_delay + << CS35L41_DSP_NG_DELAY_SHIFT); + } + } + + if (cs35l41->pdata.hw_ng_sel) + regmap_update_bits( + cs35l41->regmap, CS35L41_NG_CFG, CS35L41_HW_NG_SEL_MASK, + cs35l41->pdata.hw_ng_sel << CS35L41_HW_NG_SEL_SHIFT); + + if (cs35l41->pdata.hw_ng_thld) + regmap_update_bits(cs35l41->regmap, CS35L41_NG_CFG, + CS35L41_HW_NG_THLD_MASK, + cs35l41->pdata.hw_ng_thld + << CS35L41_HW_NG_THLD_SHIFT); + + if (cs35l41->pdata.hw_ng_delay) + regmap_update_bits( + cs35l41->regmap, CS35L41_NG_CFG, CS35L41_HW_NG_DLY_MASK, + cs35l41->pdata.hw_ng_delay << CS35L41_HW_NG_DLY_SHIFT); + + if (regmap_read(cs35l41->regmap, CS35L41_DEVID_OTP, &devid_otp) < 0) { + dev_err(cs35l41->dev, "Read DEVID OTP failed\n"); + return -EINVAL; + } + if (classh->classh_algo_enable) { + if (classh->classh_bst_override && + devid_otp != CS35L41LV_CHIP_ID) + regmap_update_bits(cs35l41->regmap, + CS35L41_BSTCVRT_VCTRL2, + CS35L41_BST_CTL_SEL_MASK, + CS35L41_BST_CTL_SEL_REG); + if (classh->classh_bst_max_limit && + devid_otp != CS35L41LV_CHIP_ID) + regmap_update_bits(cs35l41->regmap, + CS35L41_BSTCVRT_VCTRL2, + CS35L41_BST_LIM_MASK, + classh->classh_bst_max_limit + << CS35L41_BST_LIM_SHIFT); + if (classh->classh_mem_depth) + regmap_update_bits( + cs35l41->regmap, CS35L41_CLASSH_CFG, + CS35L41_CH_MEM_DEPTH_MASK, + classh->classh_mem_depth + << CS35L41_CH_MEM_DEPTH_SHIFT); + if (classh->classh_headroom) + regmap_update_bits( + cs35l41->regmap, CS35L41_CLASSH_CFG, + CS35L41_CH_HDRM_CTL_MASK, + classh->classh_headroom + << CS35L41_CH_HDRM_CTL_SHIFT); + if (classh->classh_release_rate) + regmap_update_bits( + cs35l41->regmap, CS35L41_CLASSH_CFG, + CS35L41_CH_REL_RATE_MASK, + classh->classh_release_rate + << CS35L41_CH_REL_RATE_SHIFT); + if (classh->classh_wk_fet_delay) + regmap_update_bits( + cs35l41->regmap, CS35L41_WKFET_CFG, + CS35L41_CH_WKFET_DLY_MASK, + classh->classh_wk_fet_delay + << CS35L41_CH_WKFET_DLY_SHIFT); + if (classh->classh_wk_fet_thld) + regmap_update_bits( + cs35l41->regmap, CS35L41_WKFET_CFG, + CS35L41_CH_WKFET_THLD_MASK, + classh->classh_wk_fet_thld + << CS35L41_CH_WKFET_THLD_SHIFT); + } + + return 0; +} + +static int cs35l41_component_probe(struct snd_soc_component *component) +{ + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + struct snd_kcontrol_new *kcontrol; + int ret = 0; + u32 devid_otp; + + dev_info(cs35l41->dev, "cs35l41_component_probe E\n"); + component->regmap = cs35l41->regmap; + + cs35l41_set_pdata(cs35l41); + ret = regmap_read(cs35l41->regmap, CS35L41_DEVID_OTP, &devid_otp); + if (ret < 0) { + dev_err(cs35l41->dev, "Read DEVID OTP failed\n"); + ret = -EINVAL; + goto exit; + } + if (devid_otp == CS35L41LV_CHIP_ID) + /* BST_CTL_LIM_EN = 1 BST_CTL_SEL = b'01 (Class H tracking) */ + regmap_write(cs35l41->regmap, CS35L41_BSTCVRT_VCTRL2, 0x5); + + dev_err(cs35l41->dev, "skip wm_adsp\n"); + /* These should only run once, not every hibernate cycle */ + if (!(cs35l41->skip_codec_probe)) { + wm_adsp2_component_probe(&cs35l41->dsp, component); + cs35l41->skip_codec_probe = true; + + /* Add run-time mixer control for fast use case switch */ + kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); + if (!kcontrol) { + ret = -ENOMEM; + goto exit; + } + kcontrol->name = "Fast Use Case Delta File"; + kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; + kcontrol->info = snd_soc_info_enum_double; + kcontrol->get = cs35l41_fast_switch_file_get; + kcontrol->put = cs35l41_fast_switch_file_put; + kcontrol->private_value = + (unsigned long)&cs35l41->fast_switch_enum; + ret = snd_soc_add_component_controls(component, kcontrol, 1); + if (ret < 0) + dev_err(cs35l41->dev, + "snd_soc_add_codec_controls failed (%d)\n", + ret); + + dev_dbg(cs35l41->dev, "Start queue boot_work\n"); + //queue_work(system_highpri_wq, &cs35l41->dsp.boot_work); + queue_work(cs35l41->dsp.work_queue, &cs35l41->dsp.boot_work); + kfree(kcontrol); + } +exit: + dev_info(cs35l41->dev, "cs35l41_component_probe X\n"); + return ret; +} + +static int cs35l41_irq_gpio_config(struct cs35l41_private *cs35l41) +{ + struct irq_cfg *irq_gpio_cfg1 = &cs35l41->pdata.irq_config1; + struct irq_cfg *irq_gpio_cfg2 = &cs35l41->pdata.irq_config2; + int irq_pol = IRQF_TRIGGER_NONE; + + if (irq_gpio_cfg1->is_present) { + if (irq_gpio_cfg1->irq_pol_inv) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, + CS35L41_GPIO_POL_MASK, + CS35L41_GPIO_POL_MASK); + if (irq_gpio_cfg1->irq_out_en) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, + CS35L41_GPIO_DIR_MASK, 0); + if (irq_gpio_cfg1->irq_src_sel) + regmap_update_bits(cs35l41->regmap, + CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO1_CTRL_MASK, + irq_gpio_cfg1->irq_src_sel + << CS35L41_GPIO1_CTRL_SHIFT); + } + + if (irq_gpio_cfg2->is_present) { + if (irq_gpio_cfg2->irq_pol_inv) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, + CS35L41_GPIO_POL_MASK, + CS35L41_GPIO_POL_MASK); + if (irq_gpio_cfg2->irq_out_en) + regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, + CS35L41_GPIO_DIR_MASK, 0); + if (irq_gpio_cfg2->irq_src_sel) + regmap_update_bits(cs35l41->regmap, + CS35L41_GPIO_PAD_CONTROL, + CS35L41_GPIO2_CTRL_MASK, + irq_gpio_cfg2->irq_src_sel + << CS35L41_GPIO2_CTRL_SHIFT); + } + + if (irq_gpio_cfg2->irq_src_sel == + (CS35L41_GPIO_CTRL_ACTV_LO | CS35L41_VALID_PDATA)) + irq_pol = IRQF_TRIGGER_LOW; + else if (irq_gpio_cfg2->irq_src_sel == + (CS35L41_GPIO_CTRL_ACTV_HI | CS35L41_VALID_PDATA)) + irq_pol = IRQF_TRIGGER_HIGH; + + return irq_pol; +} + +static void cs35l41_component_remove(struct snd_soc_component *component) +{ + struct cs35l41_private *cs35l41 = + snd_soc_component_get_drvdata(component); + + wm_adsp2_component_remove(&cs35l41->dsp, component); +} + +static const struct snd_soc_dai_ops cs35l41_ops = { + .startup = cs35l41_pcm_startup, + .set_fmt = cs35l41_set_dai_fmt, + .hw_params = cs35l41_pcm_hw_params, + .set_sysclk = cs35l41_dai_set_sysclk, +}; + +static struct snd_soc_dai_driver cs35l41_dai[] = { + { + .name = "cs35l41-pcm", + .id = 0, + .playback = { + .stream_name = "AMP Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_KNOT, + .formats = CS35L41_RX_FORMATS, + }, + .capture = { + .stream_name = "AMP Capture", + .channels_min = 1, + .channels_max = 8, + .rates = SNDRV_PCM_RATE_KNOT, + .formats = CS35L41_TX_FORMATS, + }, + .ops = &cs35l41_ops, + .symmetric_rates = 1, + }, +}; + +static struct snd_soc_component_driver soc_component_dev_cs35l41 = { + .probe = cs35l41_component_probe, + .remove = cs35l41_component_remove, + + .dapm_widgets = cs35l41_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), + + .set_sysclk = cs35l41_component_set_sysclk, +}; + +static int cs35l41_handle_of_data(struct device *dev, + struct cs35l41_platform_data *pdata, + struct cs35l41_private *cs35l41) +{ + struct device_node *np = dev->of_node; + unsigned int val; + int ret; + size_t num_fast_switch; + struct device_node *sub_node; + struct classh_cfg *classh_config = &pdata->classh_config; + struct irq_cfg *irq_gpio1_config = &pdata->irq_config1; + struct irq_cfg *irq_gpio2_config = &pdata->irq_config2; + unsigned int i; + + if (!np) + return 0; + + ret = of_property_count_strings(np, "cirrus,fast-switch"); + if (ret < 0) { + /* + * device tree do not provide file name. + * Use default value + */ + num_fast_switch = ARRAY_SIZE(cs35l41_fast_switch_text); + cs35l41->fast_switch_enum.items = + ARRAY_SIZE(cs35l41_fast_switch_text); + cs35l41->fast_switch_enum.texts = cs35l41_fast_switch_text; + cs35l41->fast_switch_names = cs35l41_fast_switch_text; + } else { + /* Device tree provides file name */ + num_fast_switch = (size_t)ret; + dev_info(dev, "num_fast_switch:%zu\n", num_fast_switch); + cs35l41->fast_switch_names = devm_kmalloc( + dev, num_fast_switch * sizeof(char *), GFP_KERNEL); + if (!cs35l41->fast_switch_names) + return -ENOMEM; + of_property_read_string_array(np, "cirrus,fast-switch", + cs35l41->fast_switch_names, + num_fast_switch); + for (i = 0; i < num_fast_switch; i++) { + dev_info(dev, "%d:%s\n", i, + cs35l41->fast_switch_names[i]); + } + cs35l41->fast_switch_enum.items = num_fast_switch; + cs35l41->fast_switch_enum.texts = cs35l41->fast_switch_names; + } + + cs35l41->fast_switch_enum.reg = SND_SOC_NOPM; + cs35l41->fast_switch_enum.shift_l = 0; + cs35l41->fast_switch_enum.shift_r = 0; + cs35l41->fast_switch_enum.mask = + roundup_pow_of_two(num_fast_switch) - 1; + + pdata->right_channel = + of_property_read_bool(np, "cirrus,right-channel-amp"); + pdata->sclk_frc = of_property_read_bool(np, "cirrus,sclk-force-output"); + pdata->lrclk_frc = + of_property_read_bool(np, "cirrus,lrclk-force-output"); + pdata->amp_gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc"); + pdata->tuning_has_prefix = + of_property_read_bool(np, "cirrus,tuning-has-prefix"); + pdata->invert_pcm = of_property_read_bool(np, "cirrus,invert-pcm"); + + pdata->fwname_use_revid = + of_property_read_bool(np, "cirrus,fwname-use-revid"); + + if (of_property_read_u32(np, "cirrus,temp-warn_threshold", &val) >= 0) + pdata->temp_warn_thld = val | CS35L41_VALID_PDATA; + + ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val); + if (ret >= 0) { + if (val < 2550 || val > 11000) { + dev_err(dev, "Invalid Boost Voltage %u mV\n", val); + return -EINVAL; + } + pdata->bst_vctrl = ((val - 2550) / 100) + 1; + } + + ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val); + if (ret >= 0) + pdata->bst_ipk = val; + + ret = of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val); + if (ret >= 0) + pdata->bst_ind = val; + + ret = of_property_read_u32(np, "cirrus,boost-cap-microfarad", &val); + if (ret >= 0) + pdata->bst_cap = val; + + ret = of_property_read_u32(np, "cirrus,asp-sdout-hiz", &val); + if (ret >= 0) + pdata->dout_hiz = val; + else + pdata->dout_hiz = -1; + + pdata->dsp_ng_enable = + of_property_read_bool(np, "cirrus,dsp-noise-gate-enable"); + if (of_property_read_u32(np, "cirrus,dsp-noise-gate-threshold", &val) >= + 0) + pdata->dsp_ng_pcm_thld = val | CS35L41_VALID_PDATA; + if (of_property_read_u32(np, "cirrus,dsp-noise-gate-delay", &val) >= 0) + pdata->dsp_ng_delay = val | CS35L41_VALID_PDATA; + + if (of_property_read_u32(np, "cirrus,hw-noise-gate-select", &val) >= 0) + pdata->hw_ng_sel = val | CS35L41_VALID_PDATA; + if (of_property_read_u32(np, "cirrus,hw-noise-gate-threshold", &val) >= + 0) + pdata->hw_ng_thld = val | CS35L41_VALID_PDATA; + if (of_property_read_u32(np, "cirrus,hw-noise-gate-delay", &val) >= 0) + pdata->hw_ng_delay = val | CS35L41_VALID_PDATA; + + sub_node = of_get_child_by_name(np, "cirrus,classh-internal-algo"); + classh_config->classh_algo_enable = sub_node ? true : false; + + if (classh_config->classh_algo_enable) { + classh_config->classh_bst_override = of_property_read_bool( + sub_node, "cirrus,classh-bst-overide"); + + ret = of_property_read_u32(sub_node, + "cirrus,classh-bst-max-limit", &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_bst_max_limit = val; + } + + ret = of_property_read_u32(sub_node, "cirrus,classh-mem-depth", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_mem_depth = val; + } + + ret = of_property_read_u32(sub_node, + "cirrus,classh-release-rate", &val); + if (ret >= 0) + classh_config->classh_release_rate = val; + + ret = of_property_read_u32(sub_node, "cirrus,classh-headroom", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_headroom = val; + } + + ret = of_property_read_u32(sub_node, + "cirrus,classh-wk-fet-delay", &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + classh_config->classh_wk_fet_delay = val; + } + + ret = of_property_read_u32(sub_node, + "cirrus,classh-wk-fet-thld", &val); + if (ret >= 0) + classh_config->classh_wk_fet_thld = val; + } + of_node_put(sub_node); + + /* GPIO1 Pin Config */ + sub_node = of_get_child_by_name(np, "cirrus,gpio-config1"); + irq_gpio1_config->is_present = sub_node ? true : false; + if (irq_gpio1_config->is_present) { + irq_gpio1_config->irq_pol_inv = of_property_read_bool( + sub_node, "cirrus,gpio-polarity-invert"); + irq_gpio1_config->irq_out_en = of_property_read_bool( + sub_node, "cirrus,gpio-output-enable"); + ret = of_property_read_u32(sub_node, "cirrus,gpio-src-select", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + irq_gpio1_config->irq_src_sel = val; + } + } + of_node_put(sub_node); + + /* GPIO2 Pin Config */ + sub_node = of_get_child_by_name(np, "cirrus,gpio-config2"); + irq_gpio2_config->is_present = sub_node ? true : false; + if (irq_gpio2_config->is_present) { + irq_gpio2_config->irq_pol_inv = of_property_read_bool( + sub_node, "cirrus,gpio-polarity-invert"); + irq_gpio2_config->irq_out_en = of_property_read_bool( + sub_node, "cirrus,gpio-output-enable"); + ret = of_property_read_u32(sub_node, "cirrus,gpio-src-select", + &val); + if (ret >= 0) { + val |= CS35L41_VALID_PDATA; + irq_gpio2_config->irq_src_sel = val; + } + } + of_node_put(sub_node); + + pdata->hibernate_enable = + of_property_read_bool(np, "cirrus,hibernate-enable"); + + return 0; +} + +static const struct reg_sequence cs35l41_reva0_errata_patch[] = { + { 0x00000040, 0x00005555 }, + { 0x00000040, 0x0000AAAA }, + { 0x00003854, 0x05180240 }, + { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, + { 0x00004310, 0x00000000 }, + { CS35L41_VPVBST_FS_SEL, 0x00000000 }, + { CS35L41_OTP_TRIM_30, 0x9091A1C8 }, + { 0x00003014, 0x0200EE0E }, + { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, + { 0x00000054, 0x00000004 }, + { CS35L41_IRQ1_DB3, 0x00000000 }, + { CS35L41_IRQ2_DB3, 0x00000000 }, + { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, + { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, + { 0x00000040, 0x0000CCCC }, + { 0x00000040, 0x00003333 }, +}; + +static const struct reg_sequence cs35l41_revb0_errata_patch[] = { + { 0x00000040, 0x00005555 }, + { 0x00000040, 0x0000AAAA }, + { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, + { 0x00004310, 0x00000000 }, + { CS35L41_VPVBST_FS_SEL, 0x00000000 }, + { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, + { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, + { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, + { 0x00000040, 0x0000CCCC }, + { 0x00000040, 0x00003333 }, +}; + +static const struct reg_sequence cs35l41_revb2_errata_patch[] = { + { 0x00000040, 0x00005555 }, + { 0x00000040, 0x0000AAAA }, + { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, + { 0x00004310, 0x00000000 }, + { CS35L41_VPVBST_FS_SEL, 0x00000000 }, + { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, + { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, + { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, + { 0x00000040, 0x0000CCCC }, + { 0x00000040, 0x00003333 }, +}; + +static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) +{ + struct wm_adsp *dsp; + int ret, i; + + dsp = &cs35l41->dsp; + dsp->num = 1; + dsp->type = WMFW_HALO; + dsp->rev = 0; + dsp->dev = cs35l41->dev; + dsp->regmap = cs35l41->regmap; + dsp->tuning_has_prefix = cs35l41->pdata.tuning_has_prefix; + dsp->first_booting = true; + + if (!cs35l41->pdata.fwname_use_revid) + dsp->part = "cs35l41"; + + dsp->base = CS35L41_DSP1_CTRL_BASE; + dsp->base_sysinfo = CS35L41_DSP1_SYS_ID; + dsp->mem = cs35l41_dsp1_regions; + dsp->num_mems = ARRAY_SIZE(cs35l41_dsp1_regions); + dsp->lock_regions = 0xFFFFFFFF; + + dsp->n_rx_channels = CS35L41_DSP_N_RX_RATES; + dsp->n_tx_channels = CS35L41_DSP_N_TX_RATES; + + mutex_init(&cs35l41->rate_lock); + ret = wm_halo_init(dsp, &cs35l41->rate_lock); + cs35l41->halo_booted = false; + + for (i = 0; i < CS35L41_DSP_N_RX_RATES; i++) + dsp->rx_rate_cache[i] = 0x1; + for (i = 0; i < CS35L41_DSP_N_TX_RATES; i++) + dsp->tx_rate_cache[i] = 0x1; + + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, + CS35L41_INPUT_SRC_VPMON); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, + CS35L41_INPUT_SRC_CLASSH); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, + CS35L41_INPUT_SRC_TEMPMON); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, + CS35L41_INPUT_SRC_RSVD); + + return ret; +} + +static int cs35l41_enter_hibernate(struct cs35l41_private *cs35l41) +{ + int i; + + dev_dbg(cs35l41->dev, "%s: hibernate state %d\n", __func__, + cs35l41->amp_hibernate); + + if (cs35l41->amp_hibernate == CS35L41_HIBERNATE_STANDBY) + return 0; + + /* read all ctl regs */ + for (i = 0; i < CS35L41_CTRL_CACHE_SIZE; i++) + regmap_read(cs35l41->regmap, cs35l41_ctl_cache_regs[i], + &cs35l41->ctl_cache[i]); + + /* Disable interrupts */ + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); + disable_irq(cs35l41->irq); + + /* Reset DSP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ2_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT); + + /* Reset AP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT); + + regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0088); + regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0188); + + regmap_write(cs35l41->regmap, CS35L41_CSPL_MBOX_CMD_DRV, + CSPL_MBOX_CMD_HIBERNATE); + + regcache_cache_only(cs35l41->regmap, true); + + cs35l41->amp_hibernate = CS35L41_HIBERNATE_STANDBY; + return 0; +} + +static int cs35l41_wait_for_pwrmgt_sts(struct cs35l41_private *cs35l41) +{ + int i, ret = 0; + unsigned int wrpend_sts = 0x2; + + for (i = 0; (i < 10) && (wrpend_sts & 0x2); i++) + ret = regmap_read(cs35l41->regmap, CS35L41_PWRMGT_STS, + &wrpend_sts); + return ret; +} + +static int cs35l41_exit_hibernate(struct cs35l41_private *cs35l41) +{ + int timeout = 10, ret; + unsigned int status; + int retries = 5, i; + u32 *p_trim_data; + + dev_dbg(cs35l41->dev, "%s: hibernate state %d\n", __func__, + cs35l41->amp_hibernate); + + if (cs35l41->amp_hibernate != CS35L41_HIBERNATE_STANDBY) + return 0; + + /* update any regs that changed while in cache-only mode */ + for (i = 0; i < CS35L41_CTRL_CACHE_SIZE; i++) + regmap_read(cs35l41->regmap, cs35l41_ctl_cache_regs[i], + &cs35l41->ctl_cache[i]); + + regcache_cache_only(cs35l41->regmap, false); + + do { + do { + ret = regmap_write(cs35l41->regmap, + CS35L41_CSPL_MBOX_CMD_DRV, + CSPL_MBOX_CMD_OUT_OF_HIBERNATE); + if (ret < 0) + dev_dbg(cs35l41->dev, "%s: wakeup write fail\n", + __func__); + + usleep_range(1000, 1100); + + ret = regmap_read(cs35l41->regmap, + CS35L41_CSPL_MBOX_STS, &status); + if (ret < 0) + dev_err(cs35l41->dev, + "%s: mbox status read fail\n", + __func__); + + } while (status != CSPL_MBOX_STS_PAUSED && --timeout > 0); + + if (timeout != 0) + break; + + dev_err(cs35l41->dev, "hibernate wake failed\n"); + + cs35l41_wait_for_pwrmgt_sts(cs35l41); + regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0088); + + cs35l41_wait_for_pwrmgt_sts(cs35l41); + regmap_write(cs35l41->regmap, CS35L41_WAKESRC_CTL, 0x0188); + + cs35l41_wait_for_pwrmgt_sts(cs35l41); + regmap_write(cs35l41->regmap, CS35L41_PWRMGT_CTL, 0x3); + + timeout = 10; + + } while (--retries > 0); + + /* Reset DSP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ2_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_DRV_SHIFT); + + /* Reset AP sticky bit */ + regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS2, + 1 << CS35L41_CSPL_MBOX_CMD_FW_SHIFT); + + cs35l41->amp_hibernate = CS35L41_HIBERNATE_AWAKE; + + /* invalidate all cached values which have now been reset */ + regcache_drop_region(cs35l41->regmap, CS35L41_DEVID, + CS35L41_MIXER_NGATE_CH2_CFG); + + /* sync all control regs to cache value */ + for (i = 0; i < CS35L41_CTRL_CACHE_SIZE; i++) + regmap_write(cs35l41->regmap, cs35l41_ctl_cache_regs[i], + cs35l41->ctl_cache[i]); + + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000055); + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000AA); + + /* trim with cache values */ + p_trim_data = cs35l41->trim_cache; + for (i = 0; i < CS35L41_TRIM_CACHE_REGIONS; i++) { + regmap_raw_write(cs35l41->regmap, + cs35l41_trim_cache_regs[i].reg, p_trim_data, + cs35l41_trim_cache_regs[i].size * sizeof(u32)); + p_trim_data += cs35l41_trim_cache_regs[i].size; + } + + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000CC); + regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000033); + + retries = 5; + + do { + dev_dbg(cs35l41->dev, "cs35l41_restore attempt %d\n", + 6 - retries); + ret = cs35l41_restore(cs35l41); + usleep_range(4000, 5000); + } while (ret < 0 && --retries > 0); + + if (retries < 0) + dev_err(cs35l41->dev, "Failed to exit from hibernate\n"); + else + dev_dbg(cs35l41->dev, "cs35l41 restored in %d attempts\n", + 6 - retries); + + enable_irq(cs35l41->irq); + + return ret; +} + +/* Restore amp state after hibernate */ +static int cs35l41_restore(struct cs35l41_private *cs35l41) +{ + int ret; + u32 regid, reg_revid, mtl_revid, chipid_match; + u32 devid_otp; + + ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); + if (ret < 0) { + dev_err(cs35l41->dev, "%s: Get Device ID fail\n", __func__); + return -ENODEV; + } + + ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); + if (ret < 0) { + dev_err(cs35l41->dev, "Get Revision ID failed\n"); + return -ENODEV; + } + + mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; + chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; + if (regid != chipid_match && regid != CS35L41LV_CHIP_ID) { + dev_err(cs35l41->dev, + "CS35L41 Device ID (%X). Expected ID %X\n", regid, + chipid_match); + return -ENODEV; + } + + cs35l41_irq_gpio_config(cs35l41); + + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, + CS35L41_INT1_MASK_DEFAULT); + + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, + CS35L41_INPUT_SRC_VPMON); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, + CS35L41_INPUT_SRC_CLASSH); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, + CS35L41_INPUT_SRC_TEMPMON); + regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, + CS35L41_INPUT_SRC_RSVD); + + switch (reg_revid) { + case CS35L41_REVID_A0: + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_reva0_errata_patch, + ARRAY_SIZE(cs35l41_reva0_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply A0 errata patch %d\n", ret); + } + break; + case CS35L41_REVID_B0: + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_revb0_errata_patch, + ARRAY_SIZE(cs35l41_revb0_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply B0 errata patch %d\n", ret); + } + break; + case CS35L41_REVID_B2: + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_revb2_errata_patch, + ARRAY_SIZE(cs35l41_revb2_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply B2 errata patch %d\n", ret); + } + break; + } + + dev_dbg(cs35l41->dev, "Restored CS35L41 (%x), Revision: %02X\n", regid, + reg_revid); + + cs35l41_set_pdata(cs35l41); + ret = regmap_read(cs35l41->regmap, CS35L41_DEVID_OTP, &devid_otp); + if (ret < 0) { + dev_err(cs35l41->dev, "Read DEVID OTP failed\n"); + return -EINVAL; + } + if (devid_otp == CS35L41LV_CHIP_ID) + /* BST_CTL_LIM_EN = 1 BST_CTL_SEL = b'01 (Class H tracking) */ + regmap_write(cs35l41->regmap, CS35L41_BSTCVRT_VCTRL2, 0x5); + + /* Restore cached values set by ALSA during or before amp reset */ + + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT, + CS35L41_ASP_RX1_SLOT_MASK, + ((cs35l41->pdata.right_channel) ? 1 : 0) + << CS35L41_ASP_RX1_SLOT_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT, + CS35L41_ASP_RX2_SLOT_MASK, + ((cs35l41->pdata.right_channel) ? 0 : 1) + << CS35L41_ASP_RX2_SLOT_SHIFT); + + if (cs35l41->reset_cache.extclk_cfg) { + /* These values are already cached in cs35l41_private struct */ + + if (cs35l41->clksrc == CS35L41_PLLSRC_SCLK) + regmap_update_bits(cs35l41->regmap, + CS35L41_SP_RATE_CTRL, 0x3F, + cs35l41->extclk_cfg); + + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_OPENLOOP_MASK, + 1 << CS35L41_PLL_OPENLOOP_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_REFCLK_FREQ_MASK, + cs35l41->extclk_cfg + << CS35L41_REFCLK_FREQ_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_EN_MASK, + 0 << CS35L41_PLL_CLK_EN_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_SEL_MASK, cs35l41->clksrc); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_OPENLOOP_MASK, + 0 << CS35L41_PLL_OPENLOOP_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, + CS35L41_PLL_CLK_EN_MASK, + 1 << CS35L41_PLL_CLK_EN_SHIFT); + } + + if (cs35l41->reset_cache.asp_width >= 0) { + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_WIDTH_RX_MASK, + cs35l41->reset_cache.asp_width + << CS35L41_ASP_WIDTH_RX_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_WIDTH_TX_MASK, + cs35l41->reset_cache.asp_width + << CS35L41_ASP_WIDTH_TX_SHIFT); + } + + if (cs35l41->reset_cache.asp_wl >= 0) { + regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, + CS35L41_ASP_RX_WL_MASK, + cs35l41->reset_cache.asp_wl + << CS35L41_ASP_RX_WL_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, + CS35L41_ASP_TX_WL_MASK, + cs35l41->reset_cache.asp_wl + << CS35L41_ASP_TX_WL_SHIFT); + } + + if (cs35l41->reset_cache.asp_fmt >= 0) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_ASP_FMT_MASK, + cs35l41->reset_cache.asp_fmt + << CS35L41_ASP_FMT_SHIFT); + + if (cs35l41->reset_cache.lrclk_fmt >= 0) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_INV_MASK, + cs35l41->reset_cache.lrclk_fmt + << CS35L41_LRCLK_INV_SHIFT); + + if (cs35l41->reset_cache.sclk_fmt >= 0) + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_INV_MASK, + cs35l41->reset_cache.sclk_fmt + << CS35L41_SCLK_INV_SHIFT); + + if (cs35l41->reset_cache.slave_mode >= 0) { + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_SCLK_MSTR_MASK, + cs35l41->reset_cache.slave_mode + << CS35L41_SCLK_MSTR_SHIFT); + regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, + CS35L41_LRCLK_MSTR_MASK, + cs35l41->reset_cache.slave_mode + << CS35L41_LRCLK_MSTR_SHIFT); + } + + if (cs35l41->reset_cache.fs_cfg >= 0) + regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, + CS35L41_GLOBAL_FS_MASK, + cs35l41->reset_cache.fs_cfg + << CS35L41_GLOBAL_FS_SHIFT); + + return 0; +} + +static int cs35l41_preset_sample_rate(struct cs35l41_private *cs35l41, int rate) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { + if (rate == cs35l41_fs_rates[i].rate) + break; + } + + if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { + dev_err(cs35l41->dev, "%s: Invalid sample rate = %d\n", + __func__, rate); + return -EINVAL; + } + + regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, + CS35L41_GLOBAL_FS_MASK, + cs35l41_fs_rates[i].fs_cfg + << CS35L41_GLOBAL_FS_SHIFT); + + return 0; +} + +int cs35l41_probe(struct cs35l41_private *cs35l41, + struct cs35l41_platform_data *pdata) +{ + int ret; + u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; + int timeout = 100; + int irq_pol = 0; + u32 *p_trim_data; + struct snd_kcontrol_new *cs35l41_ctl; + struct snd_soc_dapm_route *cs35l41_map; + struct snd_soc_dapm_widget *cs35l41_widgets; + const struct snd_kcontrol_new *cs35l41_tmp_ctl; + const struct snd_soc_dapm_route *cs35l41_tmp_map; + const struct snd_soc_dapm_widget *cs35l41_tmp_widgets; + int num_cs35l41_tmp_ctl; + int num_cs35l41_tmp_map; + int num_cs35l41_tmp_widgets; + u32 devid_otp; + + dev_info(cs35l41->dev, "cs35l41 probe E\n"); + + cs35l41->fast_switch_en = false; + cs35l41->fast_switch_file_idx = 0; + cs35l41->reload_tuning = false; + + for (i = 0; i < ARRAY_SIZE(cs35l41_supplies); i++) + cs35l41->supplies[i].supply = cs35l41_supplies[i]; + + cs35l41->num_supplies = ARRAY_SIZE(cs35l41_supplies); + + ret = devm_regulator_bulk_get(cs35l41->dev, cs35l41->num_supplies, + cs35l41->supplies); + if (ret != 0) { + dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", + ret); + return ret; + } + + if (pdata) { + cs35l41->pdata = *pdata; + } else if (cs35l41->dev->of_node) { + ret = cs35l41_handle_of_data(cs35l41->dev, &cs35l41->pdata, + cs35l41); + if (ret != 0) + return ret; + } else { + ret = -EINVAL; + goto err; + } + + ret = regulator_bulk_enable(cs35l41->num_supplies, cs35l41->supplies); + if (ret != 0) { + dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", + ret); + return ret; + } + + /* returning NULL can be an option if in stereo mode */ + cs35l41->reset_gpio = + devm_gpiod_get_optional(cs35l41->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(cs35l41->reset_gpio)) { + ret = PTR_ERR(cs35l41->reset_gpio); + cs35l41->reset_gpio = NULL; + if (ret == -EBUSY) { + dev_info(cs35l41->dev, + "Reset line busy, assuming shared reset\n"); + } else { + dev_err(cs35l41->dev, "Failed to get reset GPIO: %d\n", + ret); + goto err; + } + } + if (cs35l41->reset_gpio) { + /* satisfy minimum reset pulse width spec */ + usleep_range(2000, 2100); + gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); + } + + usleep_range(2000, 2100); + + do { + if (timeout == 0) { + dev_err(cs35l41->dev, + "Timeout waiting for OTP_BOOT_DONE\n"); + ret = -EBUSY; + goto err; + } + usleep_range(1000, 1100); + regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS4, &int_status); + timeout--; + } while (!(int_status & CS35L41_OTP_BOOT_DONE)); + + regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); + if (int_status & CS35L41_OTP_BOOT_ERR) { + dev_err(cs35l41->dev, "OTP Boot error\n"); + ret = -EINVAL; + goto err; + } + + ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); + if (ret < 0) { + dev_err(cs35l41->dev, "Get Device ID failed\n"); + goto err; + } + + ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); + if (ret < 0) { + dev_err(cs35l41->dev, "Get Revision ID failed\n"); + goto err; + } + + mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; + + /* CS35L41 will have even MTLREVID + * CS35L41R will have odd MTLREVID + */ + chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; + if (regid != chipid_match && regid != CS35L41LV_CHIP_ID) { + dev_err(cs35l41->dev, + "CS35L41 Device ID (%X). Expected ID %X\n", regid, + chipid_match); + ret = -ENODEV; + goto err; + } + + irq_pol = cs35l41_irq_gpio_config(cs35l41); + + mutex_init(&cs35l41->vol_ctl.vol_mutex); + cs35l41->vol_ctl.dig_vol = 0; + cs35l41->vol_ctl.ramp_init_att = 0; + cs35l41->vol_ctl.ramp_knee_att = 0; + cs35l41->vol_ctl.ramp_knee_time = 0; + cs35l41->vol_ctl.ramp_end_time = 0; + atomic_set(&cs35l41->vol_ctl.playback, 0); + atomic_set(&cs35l41->vol_ctl.vol_ramp, 0); + atomic_set(&cs35l41->vol_ctl.manual_ramp, 0); + atomic_set(&cs35l41->vol_ctl.ramp_abort, 0); + cs35l41->vol_ctl.auto_ramp_timeout = 0; + cs35l41->vol_ctl.output_dev = CS35L41_OUTPUT_DEV_SPK; + cs35l41->vol_ctl.prev_active_dev = CS35L41_OUTPUT_DEV_SPK; + cs35l41->vol_ctl.ramp_wq = + create_singlethread_workqueue("cs35l41_ramp"); + INIT_WORK(&cs35l41->vol_ctl.ramp_work, cs35l41_vol_ramp); + + ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, + cs35l41_irq, + IRQF_ONESHOT | IRQF_SHARED | irq_pol, + "cs35l41", cs35l41); + + /* CS35L41 needs INT for PDN_DONE */ + if (ret != 0) { + dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); + //goto err; + } + + /* Set interrupt masks for critical errors */ +#if defined(BRINGUP_IRQ_VERIFY) + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, + CS35L41_INT1_MASK_DEFAULT & CS35L41_INT1_UNMASK_PUP); +#else + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, + CS35L41_INT1_MASK_DEFAULT); +#endif + + mutex_init(&cs35l41->force_int_lock); + + switch (reg_revid) { + case CS35L41_REVID_A0: + cs35l41->amp_hibernate = CS35L41_HIBERNATE_INCOMPATIBLE; + if (cs35l41->pdata.fwname_use_revid) + cs35l41->dsp.part = "cs35l41-revA"; + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_reva0_errata_patch, + ARRAY_SIZE(cs35l41_reva0_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply A0 errata patch %d\n", ret); + goto err; + } + break; + case CS35L41_REVID_B0: + cs35l41->amp_hibernate = CS35L41_HIBERNATE_INCOMPATIBLE; + if (cs35l41->pdata.fwname_use_revid) + cs35l41->dsp.part = "cs35l41-revB0"; + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_revb0_errata_patch, + ARRAY_SIZE(cs35l41_revb0_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply B0 errata patch %d\n", ret); + goto err; + } + break; + case CS35L41_REVID_B2: + if (cs35l41->pdata.fwname_use_revid) + cs35l41->dsp.part = "cs35l41-revB2"; + ret = regmap_multi_reg_write( + cs35l41->regmap, cs35l41_revb2_errata_patch, + ARRAY_SIZE(cs35l41_revb2_errata_patch)); + if (ret < 0) { + dev_err(cs35l41->dev, + "Failed to apply B2 errata patch %d\n", ret); + goto err; + } + + if (cs35l41->pdata.hibernate_enable && + devid_otp != CS35L41LV_CHIP_ID) + cs35l41->amp_hibernate = CS35L41_HIBERNATE_NOT_LOADED; + else + cs35l41->amp_hibernate = CS35L41_HIBERNATE_INCOMPATIBLE; + + cs35l41->reset_cache.extclk_cfg = false; + cs35l41->reset_cache.asp_wl = -1; + cs35l41->reset_cache.asp_width = -1; + cs35l41->reset_cache.asp_fmt = -1; + cs35l41->reset_cache.sclk_fmt = -1; + cs35l41->reset_cache.slave_mode = -1; + cs35l41->reset_cache.lrclk_fmt = -1; + cs35l41->reset_cache.fs_cfg = -1; + break; + } + + ret = cs35l41_otp_unpack(cs35l41); + if (ret < 0) { + dev_err(cs35l41->dev, "OTP Unpack failed\n"); + goto err; + } + + /* read all trim regs */ + p_trim_data = cs35l41->trim_cache; + for (i = 0; i < CS35L41_TRIM_CACHE_REGIONS; i++) { + regmap_raw_read(cs35l41->regmap, cs35l41_trim_cache_regs[i].reg, + p_trim_data, + cs35l41_trim_cache_regs[i].size * sizeof(u32)); + p_trim_data += cs35l41_trim_cache_regs[i].size; + } + + regmap_write(cs35l41->regmap, CS35L41_DSP1_CCM_CORE_CTRL, 0); + cs35l41_dsp_init(cs35l41); + + ret = regmap_read(cs35l41->regmap, CS35L41_DEVID_OTP, &devid_otp); + if (ret < 0) { + dev_err(cs35l41->dev, "Read DEVID OTP failed\n"); + ret = -EINVAL; + goto err; + } + if (devid_otp == CS35L41LV_CHIP_ID) { + cs35l41_tmp_ctl = cs35l41_lv_ctl; + num_cs35l41_tmp_ctl = ARRAY_SIZE(cs35l41_lv_ctl); + cs35l41_tmp_map = NULL; + num_cs35l41_tmp_map = 0; + cs35l41_tmp_widgets = NULL; + num_cs35l41_tmp_widgets = 0; + } else { + cs35l41_tmp_ctl = cs35l41_bst_ctl; + num_cs35l41_tmp_ctl = ARRAY_SIZE(cs35l41_bst_ctl); + cs35l41_tmp_map = cs35l41_hib_map; + num_cs35l41_tmp_map = ARRAY_SIZE(cs35l41_hib_map); + cs35l41_tmp_widgets = cs35l41_hib_widgets; + num_cs35l41_tmp_widgets = ARRAY_SIZE(cs35l41_hib_widgets); + } + cs35l41_ctl = devm_kmalloc(cs35l41->dev, + sizeof(struct snd_kcontrol_new) * + (num_cs35l41_tmp_ctl + + ARRAY_SIZE(cs35l41_aud_controls)), + GFP_KERNEL); + if (!cs35l41_ctl) { + ret = -ENOMEM; + goto err; + } + memcpy(cs35l41_ctl, cs35l41_tmp_ctl, + num_cs35l41_tmp_ctl * sizeof(struct snd_kcontrol_new)); + memcpy(cs35l41_ctl + num_cs35l41_tmp_ctl, cs35l41_aud_controls, + ARRAY_SIZE(cs35l41_aud_controls) * + sizeof(struct snd_kcontrol_new)); + soc_component_dev_cs35l41.controls = cs35l41_ctl; + soc_component_dev_cs35l41.num_controls = + num_cs35l41_tmp_ctl + ARRAY_SIZE(cs35l41_aud_controls); + cs35l41_map = devm_kmalloc( + cs35l41->dev, + sizeof(struct snd_soc_dapm_route) * + (num_cs35l41_tmp_map + ARRAY_SIZE(cs35l41_audio_map)), + GFP_KERNEL); + if (!cs35l41_map) { + ret = -ENOMEM; + goto err; + } + memcpy(cs35l41_map, cs35l41_tmp_map, + num_cs35l41_tmp_map * sizeof(struct snd_soc_dapm_route)); + memcpy(cs35l41_map + num_cs35l41_tmp_map, cs35l41_audio_map, + ARRAY_SIZE(cs35l41_audio_map) * + sizeof(struct snd_soc_dapm_route)); + soc_component_dev_cs35l41.dapm_routes = cs35l41_map; + soc_component_dev_cs35l41.num_dapm_routes = + num_cs35l41_tmp_map + ARRAY_SIZE(cs35l41_audio_map); + cs35l41_widgets = + devm_kmalloc(cs35l41->dev, + sizeof(struct snd_soc_dapm_widget) * + (num_cs35l41_tmp_widgets + + ARRAY_SIZE(cs35l41_dapm_widgets)), + GFP_KERNEL); + if (!cs35l41_widgets) { + ret = -ENOMEM; + goto err; + } + memcpy(cs35l41_widgets, cs35l41_tmp_widgets, + num_cs35l41_tmp_widgets * sizeof(struct snd_soc_dapm_widget)); + memcpy(cs35l41_widgets + num_cs35l41_tmp_widgets, cs35l41_dapm_widgets, + ARRAY_SIZE(cs35l41_dapm_widgets) * + sizeof(struct snd_soc_dapm_widget)); + soc_component_dev_cs35l41.dapm_widgets = cs35l41_widgets; + soc_component_dev_cs35l41.num_dapm_widgets = + num_cs35l41_tmp_widgets + ARRAY_SIZE(cs35l41_dapm_widgets); + ret = snd_soc_register_component(cs35l41->dev, + &soc_component_dev_cs35l41, + cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); + if (ret < 0) { + dev_err(cs35l41->dev, "%s: Register codec failed\n", __func__); + goto err; + } + + dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", + regid, reg_revid); + + cs35l41->wq = create_singlethread_workqueue("cs35l41"); + if (cs35l41->wq == NULL) { + ret = -ENOMEM; + goto err; + } + + INIT_DELAYED_WORK(&cs35l41->hb_work, cs35l41_hibernate_work); + mutex_init(&cs35l41->hb_lock); + + /* Workarounds for specific project: */ + // Preset sample rate + cs35l41_preset_sample_rate(cs35l41, 48000); + + dev_info(cs35l41->dev, "cs35l41 probe X\n"); + + return 0; + +err: + regulator_bulk_disable(cs35l41->num_supplies, cs35l41->supplies); + return ret; +} + +int cs35l41_remove(struct cs35l41_private *cs35l41) +{ + destroy_workqueue(cs35l41->wq); + mutex_destroy(&cs35l41->hb_lock); + regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); + mutex_destroy(&cs35l41->force_int_lock); + wm_adsp2_remove(&cs35l41->dsp); + regulator_bulk_disable(cs35l41->num_supplies, cs35l41->supplies); + snd_soc_unregister_component(cs35l41->dev); + return 0; +} + +MODULE_DESCRIPTION("ASoC CS35L41 driver"); +MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.h b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.h new file mode 100644 index 000000000000..14933bddc28f --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.h @@ -0,0 +1,842 @@ +/* + * cs35l41.h -- CS35L41 ALSA SoC audio driver + * + * Copyright 2018 Cirrus Logic, Inc. + * + * Author: Brian Austin + * David Rhodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __CS35L41_H__ +#define __CS35L41_H__ + +#include + +#define CS35L41_FIRSTREG 0x00000000 +#define CS35L41_LASTREG 0x03804FE8 +#define CS35L41_DEVID 0x00000000 +#define CS35L41_REVID 0x00000004 +#define CS35L41_FABID 0x00000008 +#define CS35L41_RELID 0x0000000C +#define CS35L41_OTPID 0x00000010 +#define CS35L41_SFT_RESET 0x00000020 +#define CS35L41_TEST_KEY_CTL 0x00000040 +#define CS35L41_USER_KEY_CTL 0x00000044 +#define CS35L41_OTP_MEM0 0x00000400 +#define CS35L41_OTP_MEM31 0x0000047C +#define CS35L41_OTP_CTRL0 0x00000500 +#define CS35L41_OTP_CTRL1 0x00000504 +#define CS35L41_OTP_CTRL3 0x00000508 +#define CS35L41_OTP_CTRL4 0x0000050C +#define CS35L41_OTP_CTRL5 0x00000510 +#define CS35L41_OTP_CTRL6 0x00000514 +#define CS35L41_OTP_CTRL7 0x00000518 +#define CS35L41_OTP_CTRL8 0x0000051C +#define CS35L41_PWR_CTRL1 0x00002014 +#define CS35L41_PWR_CTRL2 0x00002018 +#define CS35L41_PWR_CTRL3 0x0000201C +#define CS35L41_CTRL_OVRRIDE 0x00002020 +#define CS35L41_AMP_OUT_MUTE 0x00002024 +#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034 +#define CS35L41_GPIO_PAD_CONTROL 0x0000242C +#define CS35L41_JTAG_CONTROL 0x00002438 +#define CS35L41_DEVID_OTP 0x00002850 +#define CS35L41_PWRMGT_CTL 0x00002900 +#define CS35L41_WAKESRC_CTL 0x00002904 +#define CS35L41_PWRMGT_STS 0x00002908 +#define CS35L41_PLL_CLK_CTRL 0x00002C04 +#define CS35L41_DSP_CLK_CTRL 0x00002C08 +#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C +#define CS35L41_DATA_FS_SEL 0x00002C10 +#define CS35L41_TST_FS_MON0 0x00002D10 +#define CS35L41_MDSYNC_EN 0x00003400 +#define CS35L41_MDSYNC_TX_ID 0x00003408 +#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C +#define CS35L41_MDSYNC_DATA_TX 0x00003410 +#define CS35L41_MDSYNC_TX_STATUS 0x00003414 +#define CS35L41_MDSYNC_DATA_RX 0x0000341C +#define CS35L41_MDSYNC_RX_STATUS 0x00003420 +#define CS35L41_MDSYNC_ERR_STATUS 0x00003424 +#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528 +#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C +#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C +#define CS35L41_BSTCVRT_VCTRL1 0x00003800 +#define CS35L41_BSTCVRT_VCTRL2 0x00003804 +#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808 +#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C +#define CS35L41_BSTCVRT_COEFF 0x00003810 +#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814 +#define CS35L41_BSTCVRT_SW_FREQ 0x00003818 +#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C +#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820 +#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830 +#define CS35L41_VI_VOL_POL 0x00004000 +#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100 +#define CS35L41_DTEMP_WARN_THLD 0x00004220 +#define CS35L41_DTEMP_CFG 0x00004224 +#define CS35L41_DTEMP_EN 0x00004308 +#define CS35L41_VPVBST_FS_SEL 0x00004400 +#define CS35L41_SP_ENABLES 0x00004800 +#define CS35L41_SP_RATE_CTRL 0x00004804 +#define CS35L41_SP_FORMAT 0x00004808 +#define CS35L41_SP_HIZ_CTRL 0x0000480C +#define CS35L41_SP_FRAME_TX_SLOT 0x00004810 +#define CS35L41_SP_FRAME_RX_SLOT 0x00004820 +#define CS35L41_SP_TX_WL 0x00004830 +#define CS35L41_SP_RX_WL 0x00004840 +#define CS35L41_ASP_CONTROL4 0x00004854 +#define CS35L41_DAC_PCM1_SRC 0x00004C00 +#define CS35L41_ASP_TX1_SRC 0x00004C20 +#define CS35L41_ASP_TX2_SRC 0x00004C24 +#define CS35L41_ASP_TX3_SRC 0x00004C28 +#define CS35L41_ASP_TX4_SRC 0x00004C2C +#define CS35L41_DSP1_RX1_SRC 0x00004C40 +#define CS35L41_DSP1_RX2_SRC 0x00004C44 +#define CS35L41_DSP1_RX3_SRC 0x00004C48 +#define CS35L41_DSP1_RX4_SRC 0x00004C4C +#define CS35L41_DSP1_RX5_SRC 0x00004C50 +#define CS35L41_DSP1_RX6_SRC 0x00004C54 +#define CS35L41_DSP1_RX7_SRC 0x00004C58 +#define CS35L41_DSP1_RX8_SRC 0x00004C5C +#define CS35L41_NGATE1_SRC 0x00004C60 +#define CS35L41_NGATE2_SRC 0x00004C64 +#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000 +#define CS35L41_VPBR_CFG 0x00006404 +#define CS35L41_VBBR_CFG 0x00006408 +#define CS35L41_VPBR_STATUS 0x0000640C +#define CS35L41_VBBR_STATUS 0x00006410 +#define CS35L41_OVERTEMP_CFG 0x00006414 +#define CS35L41_AMP_ERR_VOL 0x00006418 +#define CS35L41_VOL_STATUS_TO_DSP 0x00006450 +#define CS35L41_CLASSH_CFG 0x00006800 +#define CS35L41_WKFET_CFG 0x00006804 +#define CS35L41_NG_CFG 0x00006808 +#define CS35L41_AMP_GAIN_CTRL 0x00006C04 +#define CS35L41_DAC_MSM_CFG 0x00007400 +#define CS35L41_IRQ1_CFG 0x00010000 +#define CS35L41_IRQ1_STATUS 0x00010004 +#define CS35L41_IRQ1_STATUS1 0x00010010 +#define CS35L41_IRQ1_STATUS2 0x00010014 +#define CS35L41_IRQ1_STATUS3 0x00010018 +#define CS35L41_IRQ1_STATUS4 0x0001001C +#define CS35L41_IRQ1_RAW_STATUS1 0x00010090 +#define CS35L41_IRQ1_RAW_STATUS2 0x00010094 +#define CS35L41_IRQ1_RAW_STATUS3 0x00010098 +#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C +#define CS35L41_IRQ1_MASK1 0x00010110 +#define CS35L41_IRQ1_MASK2 0x00010114 +#define CS35L41_IRQ1_MASK3 0x00010118 +#define CS35L41_IRQ1_MASK4 0x0001011C +#define CS35L41_IRQ1_FRC1 0x00010190 +#define CS35L41_IRQ1_FRC2 0x00010194 +#define CS35L41_IRQ1_FRC3 0x00010198 +#define CS35L41_IRQ1_FRC4 0x0001019C +#define CS35L41_IRQ1_EDGE1 0x00010210 +#define CS35L41_IRQ1_EDGE4 0x0001021C +#define CS35L41_IRQ1_POL1 0x00010290 +#define CS35L41_IRQ1_POL2 0x00010294 +#define CS35L41_IRQ1_POL3 0x00010298 +#define CS35L41_IRQ1_POL4 0x0001029C +#define CS35L41_IRQ1_DB3 0x00010318 +#define CS35L41_IRQ2_CFG 0x00010800 +#define CS35L41_IRQ2_STATUS 0x00010804 +#define CS35L41_IRQ2_STATUS1 0x00010810 +#define CS35L41_IRQ2_STATUS2 0x00010814 +#define CS35L41_IRQ2_STATUS3 0x00010818 +#define CS35L41_IRQ2_STATUS4 0x0001081C +#define CS35L41_IRQ2_RAW_STATUS1 0x00010890 +#define CS35L41_IRQ2_RAW_STATUS2 0x00010894 +#define CS35L41_IRQ2_RAW_STATUS3 0x00010898 +#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C +#define CS35L41_IRQ2_MASK1 0x00010910 +#define CS35L41_IRQ2_MASK2 0x00010914 +#define CS35L41_IRQ2_MASK3 0x00010918 +#define CS35L41_IRQ2_MASK4 0x0001091C +#define CS35L41_IRQ2_FRC1 0x00010990 +#define CS35L41_IRQ2_FRC2 0x00010994 +#define CS35L41_IRQ2_FRC3 0x00010998 +#define CS35L41_IRQ2_FRC4 0x0001099C +#define CS35L41_IRQ2_EDGE1 0x00010A10 +#define CS35L41_IRQ2_EDGE4 0x00010A1C +#define CS35L41_IRQ2_POL1 0x00010A90 +#define CS35L41_IRQ2_POL2 0x00010A94 +#define CS35L41_IRQ2_POL3 0x00010A98 +#define CS35L41_IRQ2_POL4 0x00010A9C +#define CS35L41_IRQ2_DB3 0x00010B18 +#define CS35L41_GPIO_STATUS1 0x00011000 +#define CS35L41_GPIO1_CTRL1 0x00011008 +#define CS35L41_GPIO2_CTRL1 0x0001100C +#define CS35L41_MIXER_NGATE_CFG 0x00012000 +#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004 +#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008 +#define CS35L41_DSP_MBOX_1 0x00013000 +#define CS35L41_DSP_MBOX_2 0x00013004 +#define CS35L41_DSP_MBOX_3 0x00013008 +#define CS35L41_DSP_MBOX_4 0x0001300C +#define CS35L41_DSP_MBOX_5 0x00013010 +#define CS35L41_DSP_MBOX_6 0x00013014 +#define CS35L41_DSP_MBOX_7 0x00013018 +#define CS35L41_DSP_MBOX_8 0x0001301C +#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020 +#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024 +#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028 +#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C +#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030 +#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034 +#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038 +#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C +#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040 +#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044 +#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048 +#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C +#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050 +#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054 +#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058 +#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C +#define CS35L41_CLOCK_DETECT_1 0x00014000 +#define CS35L41_TIMER1_CONTROL 0x00015000 +#define CS35L41_TIMER1_COUNT_PRESET 0x00015004 +#define CS35L41_TIMER1_START_STOP 0x0001500C +#define CS35L41_TIMER1_STATUS 0x00015010 +#define CS35L41_TIMER1_COUNT_READBACK 0x00015014 +#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018 +#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C +#define CS35L41_TIMER2_CONTROL 0x00015100 +#define CS35L41_TIMER2_COUNT_PRESET 0x00015104 +#define CS35L41_TIMER2_START_STOP 0x0001510C +#define CS35L41_TIMER2_STATUS 0x00015110 +#define CS35L41_TIMER2_COUNT_READBACK 0x00015114 +#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118 +#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C +#define CS35L41_DFT_JTAG_CONTROL 0x00016000 +#define CS35L41_DIE_STS1 0x00017040 +#define CS35L41_DIE_STS2 0x00017044 +#define CS35L41_TEMP_CAL1 0x00017048 +#define CS35L41_TEMP_CAL2 0x0001704C +#define CS35L41_DSP1_XMEM_PACK_0 0x02000000 +#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0 +#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000 +#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8 +#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800 +#define CS35L41_DSP1_SYS_ID 0x025E0000 +#define CS35L41_DSP1_SYS_VERSION 0x025E0004 +#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008 +#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C +#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010 +#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018 +#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020 +#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028 +#define CS35L41_DSP1_SYS_FEATURES 0x025E002C +#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030 +#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034 +#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038 +#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C +#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040 +#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000 +#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004 +#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008 +#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C +#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010 +#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014 +#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018 +#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C +#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020 +#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024 +#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028 +#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C +#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030 +#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034 +#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038 +#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040 +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044 +#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000 +#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4 +#define CS35L41_DSP1_CTRL_BASE 0x02B80000 +#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010 +#define CS35L41_DSP1_DEBUG 0x02B80040 +#define CS35L41_DSP1_TIMER_CTRL 0x02B80048 +#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050 +#define CS35L41_DSP1_RX1_RATE 0x02B80080 +#define CS35L41_DSP1_RX2_RATE 0x02B80088 +#define CS35L41_DSP1_RX3_RATE 0x02B80090 +#define CS35L41_DSP1_RX4_RATE 0x02B80098 +#define CS35L41_DSP1_RX5_RATE 0x02B800A0 +#define CS35L41_DSP1_RX6_RATE 0x02B800A8 +#define CS35L41_DSP1_RX7_RATE 0x02B800B0 +#define CS35L41_DSP1_RX8_RATE 0x02B800B8 +#define CS35L41_DSP1_TX1_RATE 0x02B80280 +#define CS35L41_DSP1_TX2_RATE 0x02B80288 +#define CS35L41_DSP1_TX3_RATE 0x02B80290 +#define CS35L41_DSP1_TX4_RATE 0x02B80298 +#define CS35L41_DSP1_TX5_RATE 0x02B802A0 +#define CS35L41_DSP1_TX6_RATE 0x02B802A8 +#define CS35L41_DSP1_TX7_RATE 0x02B802B0 +#define CS35L41_DSP1_TX8_RATE 0x02B802B8 +#define CS35L41_DSP1_NMI_CTRL1 0x02B80480 +#define CS35L41_DSP1_NMI_CTRL2 0x02B80488 +#define CS35L41_DSP1_NMI_CTRL3 0x02B80490 +#define CS35L41_DSP1_NMI_CTRL4 0x02B80498 +#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0 +#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8 +#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0 +#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8 +#define CS35L41_DSP1_RESUME_CTRL 0x02B80500 +#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508 +#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510 +#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518 +#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520 +#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528 +#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530 +#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538 +#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540 +#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548 +#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550 +#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558 +#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560 +#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568 +#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570 +#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578 +#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580 +#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588 +#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590 +#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598 +#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0 +#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8 +#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0 +#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8 +#define CS35L41_DSP1_SCRATCH1 0x02B805C0 +#define CS35L41_DSP1_SCRATCH2 0x02B805C8 +#define CS35L41_DSP1_SCRATCH3 0x02B805D0 +#define CS35L41_DSP1_SCRATCH4 0x02B805D8 +#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000 +#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008 +#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000 +#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008 +#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010 +#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018 +#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020 +#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078 +#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0 +#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8 +#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0 +#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8 +#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0 +#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138 +#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180 +#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188 +#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C +#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190 +#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194 +#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198 +#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C +#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0 +#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4 +#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8 +#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC +#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0 +#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4 +#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8 +#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC +#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0 +#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4 +#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8 +#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC +#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0 +#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4 +#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8 +#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC +#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0 +#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4 +#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8 +#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC +#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0 +#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4 +#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8 +#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC +#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200 +#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204 +#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000 +#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004 +#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008 +#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C +#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014 +#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018 +#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C +#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020 +#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024 +#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C +#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030 +#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034 +#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038 +#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C +#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044 +#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048 +#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C +#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050 +#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054 +#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C +#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100 +#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104 +#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108 +#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C +#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110 +#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114 +#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140 +#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078 +#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200 +#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204 +#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208 +#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C +#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210 +#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214 +#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218 +#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C +#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220 +#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224 +#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228 +#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C +#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230 +#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234 +#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238 +#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C +#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400 +#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404 +#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408 +#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C +#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410 +#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414 +#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418 +#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C +#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420 +#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424 +#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428 +#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C +#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430 +#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434 +#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438 +#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C +#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678 +#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00 +#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08 +#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000 +#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004 +#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008 +#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010 +#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014 +#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018 +#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C +#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024 +#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C +#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030 +#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034 +#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038 +#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040 +#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000 +#define CS35L41_DSP1_WDT_STATUS 0x02BC7008 +#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000 +#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0 +#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000 +#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8 +#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000 +#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4 +#define CS35L41_DSP1_PMEM_0 0x03800000 +#define CS35L41_DSP1_PMEM_5114 0x03804FE8 + +/*test regs for emulation bringup*/ +#define CS35L41_PLL_OVR 0x00003018 +#define CS35L41_BST_TEST_DUTY 0x00003900 +#define CS35L41_DIGPWM_IOCTRL 0x0000706C + +/*registers populated by OTP*/ +#define CS35L41_OTP_TRIM_1 0x0000208c +#define CS35L41_OTP_TRIM_2 0x00002090 +#define CS35L41_OTP_TRIM_3 0x00003010 +#define CS35L41_OTP_TRIM_4 0x0000300C +#define CS35L41_OTP_TRIM_5 0x0000394C +#define CS35L41_OTP_TRIM_6 0x00003950 +#define CS35L41_OTP_TRIM_7 0x00003954 +#define CS35L41_OTP_TRIM_8 0x00003958 +#define CS35L41_OTP_TRIM_9 0x0000395C +#define CS35L41_OTP_TRIM_10 0x0000416C +#define CS35L41_OTP_TRIM_11 0x00004160 +#define CS35L41_OTP_TRIM_12 0x00004170 +#define CS35L41_OTP_TRIM_13 0x00004360 +#define CS35L41_OTP_TRIM_14 0x00004448 +#define CS35L41_OTP_TRIM_15 0x0000444C +#define CS35L41_OTP_TRIM_16 0x00006E30 +#define CS35L41_OTP_TRIM_17 0x00006E34 +#define CS35L41_OTP_TRIM_18 0x00006E38 +#define CS35L41_OTP_TRIM_19 0x00006E3C +#define CS35L41_OTP_TRIM_20 0x00006E40 +#define CS35L41_OTP_TRIM_21 0x00006E44 +#define CS35L41_OTP_TRIM_22 0x00006E48 +#define CS35L41_OTP_TRIM_23 0x00006E4C +#define CS35L41_OTP_TRIM_24 0x00006E50 +#define CS35L41_OTP_TRIM_25 0x00006E54 +#define CS35L41_OTP_TRIM_26 0x00006E58 +#define CS35L41_OTP_TRIM_27 0x00006E5C +#define CS35L41_OTP_TRIM_28 0x00006E60 +#define CS35L41_OTP_TRIM_29 0x00006E64 +#define CS35L41_OTP_TRIM_30 0x00007418 +#define CS35L41_OTP_TRIM_31 0x0000741C +#define CS35L41_OTP_TRIM_32 0x00007434 +#define CS35L41_OTP_TRIM_33 0x00007068 +#define CS35L41_OTP_TRIM_34 0x0000410C +#define CS35L41_OTP_TRIM_35 0x0000400C +#define CS35L41_OTP_TRIM_36 0x00002030 + +#define CS35L41_MAX_CACHE_REG 0x0000006B +#define CS35L41_OTP_SIZE_WORDS 32 + +#define CS35L41_VALID_PDATA 0x80000000 + +#define CS35L41_SCLK_MSTR_MASK 0x10 +#define CS35L41_SCLK_MSTR_SHIFT 4 +#define CS35L41_LRCLK_MSTR_MASK 0x01 +#define CS35L41_LRCLK_MSTR_SHIFT 0 +#define CS35L41_SCLK_INV_MASK 0x40 +#define CS35L41_SCLK_INV_SHIFT 6 +#define CS35L41_LRCLK_INV_MASK 0x04 +#define CS35L41_LRCLK_INV_SHIFT 2 +#define CS35L41_SCLK_FRC_MASK 0x20 +#define CS35L41_SCLK_FRC_SHIFT 5 +#define CS35L41_LRCLK_FRC_MASK 0x02 +#define CS35L41_LRCLK_FRC_SHIFT 1 + +#define CS35L41_AMP_GAIN_ZC_MASK 0x0400 +#define CS35L41_AMP_GAIN_ZC_SHIFT 10 + +#define CS35L41_BST_CTL_MASK 0xFF +#define CS35L41_BST_CTL_SEL_MASK 0x03 +#define CS35L41_BST_CTL_SEL_REG 0x00 +#define CS35L41_BST_CTL_SEL_CLASSH 0x01 +#define CS35L41_BST_IPK_MASK 0x7F +#define CS35L41_BST_IPK_SHIFT 0 +#define CS35L41_BST_LIM_MASK 0x4 +#define CS35L41_BST_LIM_SHIFT 2 +#define CS35L41_BST_K1_MASK 0x000000FF +#define CS35L41_BST_K1_SHIFT 0 +#define CS35L41_BST_K2_MASK 0x0000FF00 +#define CS35L41_BST_K2_SHIFT 8 +#define CS35L41_BST_SLOPE_MASK 0x0000FF00 +#define CS35L41_BST_SLOPE_SHIFT 8 +#define CS35L41_BST_LBST_VAL_MASK 0x00000003 +#define CS35L41_BST_LBST_VAL_SHIFT 0 + +#define CS35L41_TEMP_THLD_MASK 0x03 +#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF +#define CS35L41_PDM_MODE_MASK 0x01 +#define CS35L41_PDM_MODE_SHIFT 0 + +#define CS35L41_CH_MEM_DEPTH_MASK 0x07 +#define CS35L41_CH_MEM_DEPTH_SHIFT 0 +#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000 +#define CS35L41_CH_HDRM_CTL_SHIFT 16 +#define CS35L41_CH_REL_RATE_MASK 0xFF00 +#define CS35L41_CH_REL_RATE_SHIFT 8 +#define CS35L41_CH_WKFET_DLY_MASK 0x001C +#define CS35L41_CH_WKFET_DLY_SHIFT 2 +#define CS35L41_CH_WKFET_THLD_MASK 0x0F00 +#define CS35L41_CH_WKFET_THLD_SHIFT 8 + +#define CS35L41_HW_NG_SEL_MASK 0x3F00 +#define CS35L41_HW_NG_SEL_SHIFT 8 +#define CS35L41_HW_NG_DLY_MASK 0x0070 +#define CS35L41_HW_NG_DLY_SHIFT 4 +#define CS35L41_HW_NG_THLD_MASK 0x0007 +#define CS35L41_HW_NG_THLD_SHIFT 0 + +#define CS35L41_DSP_NG_ENABLE_MASK 0x00010000 +#define CS35L41_DSP_NG_ENABLE_SHIFT 16 +#define CS35L41_DSP_NG_THLD_MASK 0x7 +#define CS35L41_DSP_NG_THLD_SHIFT 0 +#define CS35L41_DSP_NG_DELAY_MASK 0x0F00 +#define CS35L41_DSP_NG_DELAY_SHIFT 8 + +#define CS35L41_ASP_FMT_MASK 0x0700 +#define CS35L41_ASP_FMT_SHIFT 8 +#define CS35L41_ASP_DOUT_HIZ_MASK 0x03 +#define CS35L41_ASP_DOUT_HIZ_SHIFT 0 +#define CS35L41_ASP_WIDTH_16 0x10 +#define CS35L41_ASP_WIDTH_24 0x18 +#define CS35L41_ASP_WIDTH_32 0x20 +#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000 +#define CS35L41_ASP_WIDTH_TX_SHIFT 16 +#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000 +#define CS35L41_ASP_WIDTH_RX_SHIFT 24 +#define CS35L41_ASP_RX1_SLOT_MASK 0x3F +#define CS35L41_ASP_RX1_SLOT_SHIFT 0 +#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00 +#define CS35L41_ASP_RX2_SLOT_SHIFT 8 +#define CS35L41_ASP_RX_WL_MASK 0x3F +#define CS35L41_ASP_TX_WL_MASK 0x3F +#define CS35L41_ASP_RX_WL_SHIFT 0 +#define CS35L41_ASP_TX_WL_SHIFT 0 +#define CS35L41_ASP_SOURCE_MASK 0x7F + +#define CS35L41_INPUT_SRC_ASPRX1 0x08 +#define CS35L41_INPUT_SRC_ASPRX2 0x09 +#define CS35L41_INPUT_SRC_VMON 0x18 +#define CS35L41_INPUT_SRC_IMON 0x19 +#define CS35L41_INPUT_SRC_CLASSH 0x21 +#define CS35L41_INPUT_SRC_VPMON 0x28 +#define CS35L41_INPUT_SRC_VBSTMON 0x29 +#define CS35L41_INPUT_SRC_TEMPMON 0x3A +#define CS35L41_INPUT_SRC_RSVD 0x3B +#define CS35L41_INPUT_DSP_TX1 0x32 +#define CS35L41_INPUT_DSP_TX2 0x33 + +#define CS35L41_PLL_CLK_SEL_MASK 0x07 +#define CS35L41_PLL_CLK_SEL_SHIFT 0 +#define CS35L41_PLL_CLK_EN_MASK 0x10 +#define CS35L41_PLL_CLK_EN_SHIFT 4 +#define CS35L41_PLL_OPENLOOP_MASK 0x0800 +#define CS35L41_PLL_OPENLOOP_SHIFT 11 +#define CS35L41_PLL_FORCE_EN_MASK 0x10000 +#define CS35L41_PLL_FORCE_EN_SHIFT 16 +#define CS35L41_PLLSRC_SCLK 0 +#define CS35L41_PLLSRC_LRCLK 1 +#define CS35L41_PLLSRC_SELF 3 +#define CS35L41_PLLSRC_PDMCLK 4 +#define CS35L41_PLLSRC_MCLK 5 +#define CS35L41_PLLSRC_SWIRE 7 +#define CS35L41_REFCLK_FREQ_MASK 0x7E0 +#define CS35L41_REFCLK_FREQ_SHIFT 5 + +#define CS35L41_GLOBAL_FS_MASK 0x1F +#define CS35L41_GLOBAL_FS_SHIFT 0 + +#define CS35L41_GLOBAL_EN_MASK 0x01 +#define CS35L41_GLOBAL_EN_SHIFT 0 +#define CS35L41_BST_EN_MASK 0x0030 +#define CS35L41_BST_EN_SHIFT 4 +#define CS35L41_BST_EN_DEFAULT 0x2 + +#define CS35L41_PDN_DONE_MASK 0x00800000 +#define CS35L41_PDN_DONE_SHIFT 23 +#define CS35L41_PUP_DONE_MASK 0x01000000 +#define CS35L41_PUP_DONE_SHIFT 24 + +#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F +#define CS35L36_PUP_DONE_IRQ_MASK 0xBF + +#define CS35L41_AMP_SHORT_ERR 0x80000000 +#define CS35L41_BST_SHORT_ERR 0x0100 +#define CS35L41_TEMP_WARN 0x8000 +#define CS35L41_TEMP_ERR 0x00020000 +#define CS35L41_BST_OVP_ERR 0x40 +#define CS35L41_BST_DCM_UVP_ERR 0x80 +#define CS35L41_OTP_BOOT_DONE 0x02 +#define CS35L41_PLL_UNLOCK 0x10 +#define CS35L41_OTP_BOOT_ERR 0x80000000 + +#define CS35L41_AMP_SHORT_ERR_RLS 0x02 +#define CS35L41_BST_SHORT_ERR_RLS 0x04 +#define CS35L41_BST_OVP_ERR_RLS 0x08 +#define CS35L41_BST_UVP_ERR_RLS 0x10 +#define CS35L41_TEMP_WARN_ERR_RLS 0x20 +#define CS35L41_TEMP_ERR_RLS 0x40 + +#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F +#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF +#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF +#define CS35L41_INT1_MASK_FORCE 0xFFFFFFFE + +#define CS35L41_GPIO_DIR_MASK 0x80000000 +#define CS35L41_GPIO1_CTRL_MASK 0x00030000 +#define CS35L41_GPIO1_CTRL_SHIFT 16 +#define CS35L41_GPIO2_CTRL_MASK 0x07000000 +#define CS35L41_GPIO2_CTRL_SHIFT 24 +#define CS35L41_GPIO_CTRL_ACTV_LO 4 +#define CS35L41_GPIO_CTRL_ACTV_HI 5 +#define CS35L41_GPIO_POL_MASK 0x1000 +#define CS35L41_GPIO_POL_SHIFT 12 + +#define CS35L41_AMP_INV_PCM_SHIFT 14 +#define CS35L41_AMP_INV_PCM_MASK (1 << CS35L41_AMP_INV_PCM_SHIFT) +#define CS35L41_AMP_PCM_VOL_SHIFT 3 +#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3) +#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF + +#define CS35L41_FILT_GLOBAL_OVR_MASK 0x4 + +#define CS35L41_CHIP_ID 0x35a40 +#define CS35L41R_CHIP_ID 0x35b40 +#define CS35L41LV_CHIP_ID 0x35a41 +#define CS35L41_MTLREVID_MASK 0x0F +#define CS35L41_REVID_A0 0xA0 +#define CS35L41_REVID_B0 0xB0 +#define CS35L41_REVID_B2 0xB2 + +#define CS35L41_DSP_N_RX_RATES 8 +#define CS35L41_DSP_N_TX_RATES 8 +#define CS35L41_HALO_CORE_RESET 0x00000200 + +#define CS35L41_FS1_WINDOW_MASK 0x000007FF +#define CS35L41_FS2_WINDOW_MASK 0x00FFF800 +#define CS35L41_FS2_WINDOW_SHIFT 12 + +#define CS35L41_SPI_MAX_FREQ_OTP 4000000 + +#define CS35L41_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) +#define CS35L41_TX_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +#define CS35L41_MAX_AUTO_RAMP_TIMEOUT 65535 +#define CS35L41_MAX_PCM_VOL 913 +#define CS35L41_MAX_VOL_ATT 120 +#define CS35L41_ZERO_PCM_VOL 817 +#define CS35L41_OUTPUT_DEV_SPK 0 +#define CS35L41_OUTPUT_DEV_RCV 1 + +bool cs35l41_readable_reg(struct device *dev, unsigned int reg); +bool cs35l41_precious_reg(struct device *dev, unsigned int reg); +bool cs35l41_volatile_reg(struct device *dev, unsigned int reg); + +struct cs35l41_otp_packed_element_t { + u32 reg; + u8 shift; + u8 size; +}; + +struct cs35l41_otp_map_element_t { + u32 devid_otp; + u32 id; + u32 num_elements; + const struct cs35l41_otp_packed_element_t *map; + u32 bit_offset; + u32 word_offset; +}; + +struct cs35l41_otp_trim_region_t { + u32 reg; + u8 size; +}; + +struct cs35l41_otp_maps { + const struct cs35l41_otp_map_element_t *map; + int len; +}; + +extern const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG]; +extern const struct cs35l41_otp_maps cs35l41_otp_maps; + +#define CS35L41_REGSTRIDE 4 +#define CS35L41_BUFSIZE 64 + +#define CS35L41_DSP_VIRT1_MBOX_SHIFT 20 +#define CS35L41_DSP_VIRT2_MBOX_SHIFT 21 +#define CS35L41_CSPL_MBOX_STS CS35L41_DSP_MBOX_2 +/* Firmware update following reg */ +#define CS35L41_CSPL_MBOX_CMD_FW CS35L41_DSP_VIRT2_MBOX_1 +#define CS35L41_CSPL_MBOX_CMD_FW_SHIFT CS35L41_DSP_VIRT2_MBOX_SHIFT +/* Driver update following reg */ +#define CS35L41_CSPL_MBOX_CMD_DRV CS35L41_DSP_VIRT1_MBOX_1 +#define CS35L41_CSPL_MBOX_CMD_DRV_SHIFT CS35L41_DSP_VIRT1_MBOX_SHIFT + +#define CS35L41_CTRL_CACHE_SIZE 14 +#define CS35L41_TRIM_CACHE_REGIONS 18 +#define CS35L41_TRIM_CACHE_SIZE 38 + +extern const unsigned int cs35l41_ctl_cache_regs[CS35L41_CTRL_CACHE_SIZE]; +extern const struct cs35l41_otp_trim_region_t + cs35l41_trim_cache_regs[CS35L41_TRIM_CACHE_REGIONS]; + +enum cs35l41_cspl_mboxstate { + CSPL_MBOX_STS_RUNNING = 0, + CSPL_MBOX_STS_PAUSED = 1, + CSPL_MBOX_STS_RDY_FOR_REINIT = 2, + CSPL_MBOX_STS_HIBERNATE = 3, +}; + +enum cs35l41_cspl_mboxcmd { + CSPL_MBOX_CMD_NONE = 0, + CSPL_MBOX_CMD_PAUSE = 1, + CSPL_MBOX_CMD_RESUME = 2, + CSPL_MBOX_CMD_REINIT = 3, + CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, + CSPL_MBOX_CMD_HIBERNATE = 5, + CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, + CSPL_MBOX_CMD_UNKNOWN_CMD = -1, + CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, +}; + +enum cs35l41_cspl_cmd { + CSPL_CMD_NONE = 0, + CSPL_CMD_MUTE = 1, + CSPL_CMD_UNMUTE = 2, + CSPL_CMD_UPDATE_PARAM = 8, +}; + +enum cs35l41_cspl_st { + CSPL_ST_RUNNING = 0, + CSPL_ST_ERROR = 1, + CSPL_ST_MUTED = 2, + CSPL_ST_REINITING = 3, + CSPL_ST_DIAGNOSING = 6, +}; + +enum cs35l41_hibernate_state { + CS35L41_HIBERNATE_AWAKE = 0, + CS35L41_HIBERNATE_STANDBY = 1, + CS35L41_HIBERNATE_NOT_LOADED = 2, + CS35L41_HIBERNATE_INCOMPATIBLE = 3, +}; + +#endif /*__CS35L41_H__*/ diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.txt b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.txt new file mode 100755 index 000000000000..ecd422bec9b4 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/cs35l41.txt @@ -0,0 +1,255 @@ +CS35L41 Speaker Amplifier + +Required properties: + + - compatible : "cirrus,cs35l41" + "cirrus,cs35l40" + + - reg : the SPI chip select line for the device + + - VA-supply, VP-supply : power supplies for the device, + as covered in + Documentation/devicetree/bindings/regulator/regulator.txt. + + + Boost hardware configuration: + + These three properties should be used together to specify the external + component configuration of the part. See section 4.3.6 of the datasheet + for details regarding how these values are used to configure the + digital boost converter's control loop. + + - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. + Configures the peak current by monitoring the current through the boost FET. + Range starts at 1600 mA and goes to a maximum of 4500 mA with increments + of 50 mA. + (Default) 4.50 Amps + + - cirrus,boost-ind-nanohenry : Boost inductor value, expressed in nH. Valid + values include 1000, 1200, 1500 and 2200. + + - cirrus,boost-cap-microfarad : Total equivalent boost capacitance on the VBST + and VAMP pins, derated at 11 volts DC. The value must be rounded to the + nearest integer and expressed in uF. + + +Optional properties: + - cirrus,sclk-force-output : Audio serial port SCLK force + output control. Forces the SCLK to continue to drive even + if no ASP_TXn channels are enabled. + + - cirrus,lrclk-force-output : Audio serial port LRCLK force + output control. Forces the LRCLK to continue to drive even + if no ASP_TXn channels are enabled. + + - cirrus,right-channel-amp : Boolean to determine which channel + the amplifier is to receive the audio data on. If present the + amplifier receives data on the right channel of I2S data. + If not present the amplifier receives data on the left + channel of I2S data + + - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the + boost converter's output voltage in mV. The range is from 2550 mV to + 11000 mV with increments of 50 mV. + (Default) VP + + - cirrus,amp-gain-zc : Boolean to determine whether to use the amplifier + gain-change zero-crossing feature. If the feature is enabled, any + user-controlled amplifier gain change will occur on a zero-crossing point. + (Default) Disabled + + - cirrus,asp-sdout-hiz : Audio serial port SDOUT Hi-Z control. Sets the Hi-Z + configuration for SDOUT pin of amplifier. + + 0 = Logic 0 during unused slots, and while all transmit channels disabled + 1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled + 2 = (Default) Logic 0 during unused slots, but Hi-Z while all transmit channels disabled + 3 = Hi-Z during unused slots and while all transmit channels disabled + + - cirrus,temp-warn-threshold : Amplifier overtemperature warning threshold. + Configures the threshold at which the overtemperature warning condition occurs. + When the threshold is met, the ovetemperature warning attenuation is applied + and the TEMP_WARN_EINT interrupt status bit is set. + If TEMP_WARN_MASK = 0, INTb is asserted. + + 0 = 105C + 1 = 115C + 2 = 125C (Default) + 3 = 135C + + - cirrus,hw-noise-gate-select : Hardware Noise Gate feature. Each bit selects + a different block for detection. + + 000000 - All noise gating functionality disabled + xxxxx1 - Amplifier noise gating detection enabled + xxxx1x - Boost converter DCM detection enabled + xxx1xx - VMON low power mode detection enabled + xx1xxx - IMON low power mode detection enabled + x1xxxx - VP brownout prevention detection enabled + 1xxxxx - VBST brownout prevention detection enabled + + - cirrus,hw-noise-gate-delay : Time that the incoming audio signal must be + below the noise gate threshold prior to entering a noise gated state + + 0 = 5 ms + 1 = 10 ms + 2 = 25 ms + 3 = 50 ms (default) + 4 = 100 ms + 5 = 250 ms + 6 = 500 ms + 7 = 1 s + + - cirrus,hw-noise-gate-threshold : Threshold of audio signal input which the + noise gate considers the input audio to be at a low enough level to be + valid to enter a noise gating state of operation. + + 0 = 0.654 mVpk + 1 = 0.328 mVpk + 2 = 0.164 mVpk + 3 = 0.082 mVpk (default) + 4 = 0.041 mVpk + 5 = 0.021 mVpk + 6 = 0.010 mVpk + 7 = True zero data (no LSB dither) + + - cirrus,dsp-noise-gate-enable : DSP Noise Gate feature. If present, noise + gate feature will be enabled. + + - cirrus,dsp-noise-gate-threshold : Threshold of audio signal input which the + noise gate considers the input audio to be at a low enough level to be + valid to enter a noise gating state of operation. + + 0 = -66 dBFS + 1 = -72 dBFS + 2 = -78 dBFS + 3 = -84 dBFS (default) + 4 = -90 dBFS + 5 = -96 dBFS + 6 = -102 dBFS + 7 = -108 dBFS + + - cirrus,dsp-noise-gate-delay : Time that the incoming audio signal must be + below the noise gate threshold prior to entering a noise gated state + + 0 = 5 ms + 1 = 10 ms + 2 = 25 ms + 3 = 50 ms (default) + 4 = 100 ms + 5 = 250 ms + 6 = 500 ms + 7 = 1 s + 8 = 5 s + 9 = 10 s + 10 = 20 s + 11 = 30 s + 12 = 40 s + 13 = 50 s + 14 = 60 s + 15 = 120 s + + - cirrus,tuning-has-prefix : Add ALSA component name prefix to + DSP firmware tuning file name. + For example, if the AMP prefix is 'Left' and FW set to 'Protection' + the driver will look for a .bin file named + Left-cs35l41-dsp1-spk-prot.bin + + - cirrus,fwname-use-revid : Add Rev ID prefix to DSP firmware file name. + For example, if FW is set to 'Protection' + CS35l41 Rev A: cs35l41-revA-dsp1-spk-prot.wmfw + CS35l41 Rev B0: cs35l41-revB0-dsp1-spk-prot.wmfw + CS35l41 Rev B2: cs35l41-revB2-dsp1-spk-prot.wmfw + + - cirrus,fast-switch : Specify file names for Fast Use Case Switching DSP + feature. Files names are comma-separated strings. + + - cirrus,invert-pcm : Inverts the polarity of the audio signal output from + the Class-D amplifier. + +Optional H/G Algorithm sub-node: + + The cs35l41 node can have a single "cirrus,classh-internal-algo" sub-node + that will disable automatic control of the internal H/G Algorithm. + + It is strongly recommended that the Datasheet be referenced when adjusting + or using these Class H Algorithm controls over the internal Algorithm. + Serious damage can occur to the Device and surrounding components. + + - cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm + See Section 4.4 Internal Class H Algorithm in the Datasheet. + If not used, the device manages the ClassH Algorithm internally. + +Optional properties for the "cirrus,classh-internal-algo" Sub-node + + Section 7.9 Boost Control + - cirrus,classh-bst-overide : Boolean + - cirrus,classh-bst-max-limit + + Above two controls are unavailable for cs35l41l (Low voltage variant) + + Section 7.17 Class H, Weak-FET Control + - cirrus,classh-headroom + - cirrus,classh-release-rate + - cirrus,classh-mem-depth + - cirrus,classh-wk-fet-delay + - cirrus,classh-wk-fet-thld + + +Optional GPIO1 sub-node: + +The cs35l41 node can have an single "cirrus,gpio-config1" sub-node for +configuring the GPIO1 pin. + +- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO1 +level is inverted. If this property is not present the level is not inverted. + +- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO1 pin +is configured as an output. If this property is not present the +pin will be configured as an input. + +- cirrus,gpio-src-select : Configures the function of the GPIO1 pin. +Note that the options are different from the GPIO2 pin. + +0 = High Impedance (Default) +1 = GPIO +2 = Sync +3 = MCLK input + + +Optional GPIO2 sub-node: + +The cs35l41 node can have an single "cirrus,gpio-config2" sub-node for +configuring the GPIO1 pin. + +- cirrus,gpio-polarity-invert : Boolean which specifies whether the GPIO2 +level is inverted. If this property is not present the level is not inverted. + +- cirrus,gpio-output-enable : Boolean which specifies whether the GPIO2 pin +is configured as an output. If this property is not present the +pin will be configured as an input. + +- cirrus,gpio-src-select : Configures the function of the GPIO2 pin. +Note that the options are different from the GPIO1 pin. + +0 = High Impedance (Default) +1 = GPIO +2 = Open Drain INTB +3 = MCLK input +4 = Push-pull INTB (active low) +5 = Push-pull INT (active high) + + +Example: + +cs35l41: cs35l41@2 { + compatible = "cirrus,cs35l41"; + reg = <2>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,fast-switch = "sample_fast_switch1.txt", "sample_fast_switch2.txt"; +}; diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.c b/techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.c new file mode 100644 index 000000000000..34a87fcdcf19 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.c @@ -0,0 +1,49 @@ +#include "send_data_to_xlog.h" +#include + +char msg_format[] = + "{\"name\":\"DC detection\",\"audio_event\":{\"count\":\"%d\",\"reason\":\"%s\"},\"dgt\":\"null\",\"audio_ext\":\"null\" }"; + +#define MAX_LEN 512 + +void send_DC_data_to_xlog(int dc_current_cnt, char *reason) +{ + int ret = -1; + pr_info("%s: dc_current_cnt: %d, reason: %s", __func__, dc_current_cnt, + reason); + ret = xlog_send_int(dc_current_cnt, reason); + if (ret < 0) { + pr_info("%s: failed", __func__); + } else { + pr_info("%s: success", __func__); + } + j; + lkj;:w +} + +int xlog_send_int(int dc_current_cnt, char *reason) +{ + int ret = 0; + char msg[512]; + pr_info("%s: cs35l41->dc_current_cnt: %d, reason: %s", __func__, + dc_current_cnt, reason); + ret = xlog_format_msg_int(msg, dc_current_cnt, reason); + if (ret < 0) { + return ret; + } + xlogchar_kwrite(msg, sizeof(msg)); + pr_info("%s: send msg: %s", __func__, msg); + return ret; +} + +int xlog_format_msg_int(char *msg, int dc_current_cnt, char *reason) +{ + if (msg == NULL) { + pr_info("%s: the msg is NULL", __func__); + return -EINVAL; + } + pr_info("%s start", __func__); + snprintf(msg, MAX_LEN, msg_format, dc_current_cnt, reason); + pr_info("%s end", __func__); + return 0; +} diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.h b/techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.h new file mode 100644 index 000000000000..bcf593a05b93 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/send_data_to_xlog.h @@ -0,0 +1,26 @@ +#ifndef SEND_DATA_TO_XLOG +#define SEND_DATA_TO_XLOG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern ssize_t xlogchar_kwrite(const char __user *buf, size_t count); + +void send_DC_data_to_xlog(int dc_current_cnt, char *reason); +int xlog_send_int(int dc_current_cnt, char *reason); +int xlog_format_msg_int(char *msg, int dc_current_cnt, char *reason); + +#endif diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.c b/techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.c new file mode 100644 index 000000000000..ccc75edeef1f --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.c @@ -0,0 +1,5167 @@ +/* + * wm_adsp.c -- Wolfson ADSP support + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wm_adsp.h" + +#define MAX_BULKSIZE 1024 +#define REG_BYTESIZE 4 + +#define adsp_crit(_dsp, fmt, ...) \ + dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_err(_dsp, fmt, ...) \ + dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_warn(_dsp, fmt, ...) \ + dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_info(_dsp, fmt, ...) \ + dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) +#define adsp_dbg(_dsp, fmt, ...) \ + dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) + +#define compr_err(_obj, fmt, ...) \ + adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ + ##__VA_ARGS__) +#define compr_dbg(_obj, fmt, ...) \ + adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ + ##__VA_ARGS__) + +#define ADSP1_CONTROL_1 0x00 +#define ADSP1_CONTROL_2 0x02 +#define ADSP1_CONTROL_3 0x03 +#define ADSP1_CONTROL_4 0x04 +#define ADSP1_CONTROL_5 0x06 +#define ADSP1_CONTROL_6 0x07 +#define ADSP1_CONTROL_7 0x08 +#define ADSP1_CONTROL_8 0x09 +#define ADSP1_CONTROL_9 0x0A +#define ADSP1_CONTROL_10 0x0B +#define ADSP1_CONTROL_11 0x0C +#define ADSP1_CONTROL_12 0x0D +#define ADSP1_CONTROL_13 0x0F +#define ADSP1_CONTROL_14 0x10 +#define ADSP1_CONTROL_15 0x11 +#define ADSP1_CONTROL_16 0x12 +#define ADSP1_CONTROL_17 0x13 +#define ADSP1_CONTROL_18 0x14 +#define ADSP1_CONTROL_19 0x16 +#define ADSP1_CONTROL_20 0x17 +#define ADSP1_CONTROL_21 0x18 +#define ADSP1_CONTROL_22 0x1A +#define ADSP1_CONTROL_23 0x1B +#define ADSP1_CONTROL_24 0x1C +#define ADSP1_CONTROL_25 0x1E +#define ADSP1_CONTROL_26 0x20 +#define ADSP1_CONTROL_27 0x21 +#define ADSP1_CONTROL_28 0x22 +#define ADSP1_CONTROL_29 0x23 +#define ADSP1_CONTROL_30 0x24 +#define ADSP1_CONTROL_31 0x26 + +/* + * ADSP1 Control 19 + */ +#define ADSP1_WDMA_BUFFER_LENGTH_MASK \ + 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ +#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ +#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ + +/* + * ADSP1 Control 30 + */ +#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ +#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ +#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ +#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ +#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ +#define ADSP1_START 0x0001 /* DSP1_START */ +#define ADSP1_START_MASK 0x0001 /* DSP1_START */ +#define ADSP1_START_SHIFT 0 /* DSP1_START */ +#define ADSP1_START_WIDTH 1 /* DSP1_START */ + +/* + * ADSP1 Control 31 + */ +#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ +#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2_CONTROL 0x0 +#define ADSP2_CLOCKING 0x1 +#define ADSP2V2_CLOCKING 0x2 +#define ADSP2_STATUS1 0x4 +#define ADSP2_WDMA_CONFIG_1 0x30 +#define ADSP2_WDMA_CONFIG_2 0x31 +#define ADSP2V2_WDMA_CONFIG_2 0x32 +#define ADSP2_RDMA_CONFIG_1 0x34 + +#define ADSP2_SCRATCH0 0x40 +#define ADSP2_SCRATCH1 0x41 +#define ADSP2_SCRATCH2 0x42 +#define ADSP2_SCRATCH3 0x43 + +#define ADSP2V2_SCRATCH0_1 0x40 +#define ADSP2V2_SCRATCH2_3 0x42 + +/* + * ADSP2 Control + */ + +#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ +#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ +#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ +#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ +#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ +#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ +#define ADSP2_START 0x0001 /* DSP1_START */ +#define ADSP2_START_MASK 0x0001 /* DSP1_START */ +#define ADSP2_START_SHIFT 0 /* DSP1_START */ +#define ADSP2_START_WIDTH 1 /* DSP1_START */ + +/* + * ADSP2 clocking + */ +#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ +#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ +#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +/* + * ADSP2V2 clocking + */ +#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ +#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ +#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ + +/* + * ADSP2 Status 1 + */ +#define ADSP2_RAM_RDY 0x0001 +#define ADSP2_RAM_RDY_MASK 0x0001 +#define ADSP2_RAM_RDY_SHIFT 0 +#define ADSP2_RAM_RDY_WIDTH 1 + +/* + * ADSP2 Lock support + */ +#define ADSP2_LOCK_CODE_0 0x5555 +#define ADSP2_LOCK_CODE_1 0xAAAA + +#define ADSP2_WATCHDOG 0x0A +#define ADSP2_BUS_ERR_ADDR 0x52 +#define ADSP2_REGION_LOCK_STATUS 0x64 +#define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 +#define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 +#define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A +#define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C +#define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E +#define ADSP2_LOCK_REGION_CTRL 0x7A +#define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C + +#define ADSP2_REGION_LOCK_ERR_MASK 0x8000 +#define ADSP2_SLAVE_ERR_MASK 0x4000 +#define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 +#define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 +#define ADSP2_CTRL_ERR_EINT 0x0001 + +#define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF +#define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF +#define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 +#define ADSP2_PMEM_ERR_ADDR_SHIFT 16 +#define ADSP2_WDT_ENA_MASK 0xFFFFFFFD + +#define ADSP2_LOCK_REGION_SHIFT 16 + +#define ADSP_MAX_STD_CTRL_SIZE 512 + +#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100 +#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10 +#define WM_ADSP_ACKED_CTL_MIN_VALUE 0 +#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF + +/* + * Event control messages + */ +#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001 + +/* + * HALO system info + */ +#define HALO_AHBM_WINDOW_DEBUG_0 0x02040 +#define HALO_AHBM_WINDOW_DEBUG_1 0x02044 + +/* + * HALO core + */ +#define HALO_SAMPLE_RATE_RX1 0x00080 +#define HALO_SAMPLE_RATE_TX1 0x00280 +#define HALO_SCRATCH1 0x005c0 +#define HALO_SCRATCH2 0x005c8 +#define HALO_SCRATCH3 0x005d0 +#define HALO_SCRATCH4 0x005d8 +#define HALO_CCM_CORE_CONTROL 0x41000 +#define HALO_CORE_SOFT_RESET 0x00010 +#define HALO_WDT_CONTROL 0x47000 + +/* + * HALO MPU banks + */ +#define HALO_MPU_XMEM_ACCESS_0 0x43000 +#define HALO_MPU_YMEM_ACCESS_0 0x43004 +#define HALO_MPU_WINDOW_ACCESS_0 0x43008 +#define HALO_MPU_XREG_ACCESS_0 0x4300C +#define HALO_MPU_YREG_ACCESS_0 0x43014 +#define HALO_MPU_XMEM_ACCESS_1 0x43018 +#define HALO_MPU_YMEM_ACCESS_1 0x4301C +#define HALO_MPU_WINDOW_ACCESS_1 0x43020 +#define HALO_MPU_XREG_ACCESS_1 0x43024 +#define HALO_MPU_YREG_ACCESS_1 0x4302C +#define HALO_MPU_XMEM_ACCESS_2 0x43030 +#define HALO_MPU_YMEM_ACCESS_2 0x43034 +#define HALO_MPU_WINDOW_ACCESS_2 0x43038 +#define HALO_MPU_XREG_ACCESS_2 0x4303C +#define HALO_MPU_YREG_ACCESS_2 0x43044 +#define HALO_MPU_XMEM_ACCESS_3 0x43048 +#define HALO_MPU_YMEM_ACCESS_3 0x4304C +#define HALO_MPU_WINDOW_ACCESS_3 0x43050 +#define HALO_MPU_XREG_ACCESS_3 0x43054 +#define HALO_MPU_YREG_ACCESS_3 0x4305C +#define HALO_MPU_XM_VIO_ADDR 0x43100 +#define HALO_MPU_XM_VIO_STATUS 0x43104 +#define HALO_MPU_YM_VIO_ADDR 0x43108 +#define HALO_MPU_YM_VIO_STATUS 0x4310C +#define HALO_MPU_PM_VIO_ADDR 0x43110 +#define HALO_MPU_PM_VIO_STATUS 0x43114 +#define HALO_MPU_LOCK_CONFIG 0x43140 + +/* + * HALO_AHBM_WINDOW_DEBUG_1 + */ +#define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00 +#define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8 +#define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff + +/* + * HALO_SAMPLE_RATE_[RX|TX]n + */ +#define HALO_DSP_RATE_SHIFT 0 +#define HALO_DSP_RATE_MASK 0x1f + +/* + * HALO_CCM_CORE_CONTROL + */ +#define HALO_CORE_EN 0x00000001 + +/* + * HALO_CORE_SOFT_RESET + */ +#define HALO_CORE_SOFT_RESET_MASK 0x00000001 + +/* + * HALO_WDT_CONTROL + */ +#define HALO_WDT_EN_MASK 0x00000001 + +/* + * HALO_MPU_?M_VIO_STATUS + */ +#define HALO_MPU_VIO_STS_MASK 0x007e0000 +#define HALO_MPU_VIO_STS_SHIFT 17 +#define HALO_MPU_VIO_ERR_WR_MASK 0x00008000 +#define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff +#define HALO_MPU_VIO_ERR_SRC_SHIFT 0 + +#define HALO_MPU_VIO_SRAM 0x01 +#define HALO_MPU_VIO_REG 0x02 +#define HALO_MPU_VIO_AHB 0x04 +#define HALO_MPU_VIO_EREG 0x08 +#define HALO_MPU_VIO_EXTERNAL_MEM 0x10 +#define HALO_MPU_VIO_NON_EXIST 0x20 + +static struct wm_adsp_ops wm_adsp1_ops; +static struct wm_adsp_ops wm_adsp2_ops[]; +static struct wm_adsp_ops wm_halo_ops; +static struct wm_adsp_ops wm_vpu_ops; + +struct wm_adsp_buf { + struct list_head list; + void *buf; +}; + +static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len, + struct list_head *list) +{ + struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL); + + if (buf == NULL) + return NULL; + + buf->buf = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!buf->buf) { + kfree(buf); + return NULL; + } + memcpy(buf->buf, src, len); + + if (list) + list_add_tail(&buf->list, list); + + return buf; +} + +static void wm_adsp_buf_free(struct list_head *list) +{ + while (!list_empty(list)) { + struct wm_adsp_buf *buf = + list_first_entry(list, struct wm_adsp_buf, list); + list_del(&buf->list); + kfree(buf->buf); + kfree(buf); + } +} + +// Speaker calibration default value +#define CAL_R_DEFAULT 8392 +#define AMBIENT_DEFAULT 30 +#define CAL_STATUS_DEFAULT 1 + +#define WM_ADSP_FW_MBC_VSS 0 +#define WM_ADSP_FW_HIFI 1 +#define WM_ADSP_FW_TX 2 +#define WM_ADSP_FW_TX_SPK 3 +#define WM_ADSP_FW_RX 4 +#define WM_ADSP_FW_RX_ANC 5 +#define WM_ADSP_FW_CTRL 6 +#define WM_ADSP_FW_ASR 7 +#define WM_ADSP_FW_TRACE 8 +#define WM_ADSP_FW_SPK_PROT 9 +#define WM_ADSP_FW_SPK_CALI 10 +#define WM_ADSP_FW_SPK_DIAG 11 +#define WM_ADSP_FW_MISC 12 + +#define WM_ADSP_NUM_FW 13 + +static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = { + [WM_ADSP_FW_MBC_VSS] = "MBC/VSS", + [WM_ADSP_FW_HIFI] = "MasterHiFi", + [WM_ADSP_FW_TX] = "Tx", + [WM_ADSP_FW_TX_SPK] = "Tx Speaker", + [WM_ADSP_FW_RX] = "Rx", + [WM_ADSP_FW_RX_ANC] = "Rx ANC", + [WM_ADSP_FW_CTRL] = "Voice Ctrl", + [WM_ADSP_FW_ASR] = "ASR Assist", + [WM_ADSP_FW_TRACE] = "Dbg Trace", + [WM_ADSP_FW_SPK_PROT] = "Protection", + [WM_ADSP_FW_SPK_CALI] = "Calibration", + [WM_ADSP_FW_SPK_DIAG] = "Diagnostic", + [WM_ADSP_FW_MISC] = "Misc", +}; + +struct wm_adsp_system_config_xm_hdr { + __be32 sys_enable; + __be32 fw_id; + __be32 fw_rev; + __be32 boot_status; + __be32 watchdog; + __be32 dma_buffer_size; + __be32 rdma[6]; + __be32 wdma[8]; + __be32 build_job_name[3]; + __be32 build_job_number; +}; + +struct wm_halo_system_config_xm_hdr { + __be32 halo_heartbeat; + __be32 build_job_name[3]; + __be32 build_job_number; +}; + +struct wm_adsp_alg_xm_struct { + __be32 magic; + __be32 smoothing; + __be32 threshold; + __be32 host_buf_ptr; + __be32 start_seq; + __be32 high_water_mark; + __be32 low_water_mark; + __be64 smoothed_power; +}; + +struct wm_adsp_host_buf_coeff_v1 { + __be32 host_buf_ptr; /* Host buffer pointer */ + __be32 versions; /* Version numbers */ + __be32 name[4]; /* The buffer name */ +}; + +struct wm_adsp_buffer { + __be32 buf1_base; /* Base addr of first buffer area */ + __be32 buf1_size; /* Size of buf1 area in DSP words */ + __be32 buf2_base; /* Base addr of 2nd buffer area */ + __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */ + __be32 buf3_base; /* Base addr of buf3 area */ + __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */ + __be32 high_water_mark; /* Point at which IRQ is asserted */ + __be32 irq_count; /* bits 1-31 count IRQ assertions */ + __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */ + __be32 next_write_index; /* word index of next write */ + __be32 next_read_index; /* word index of next read */ + __be32 error; /* error if any */ + __be32 oldest_block_index; /* word index of oldest surviving */ + __be32 requested_rewind; /* how many blocks rewind was done */ + __be32 reserved_space; /* internal */ + __be32 min_free; /* min free space since stream start */ + __be32 blocks_written[2]; /* total blocks written (64 bit) */ + __be32 words_written[2]; /* total words written (64 bit) */ +}; + +struct wm_adsp_compr; + +struct wm_adsp_compr_buf { + struct list_head list; + struct wm_adsp *dsp; + struct wm_adsp_compr *compr; + + struct wm_adsp_buffer_region *regions; + u32 host_buf_ptr; + + u32 error; + u32 irq_count; + int read_index; + int avail; + int host_buf_mem_type; + int num_regions; + const struct wm_adsp_buffer_region_def *region_def; + + char *name; +}; + +struct wm_adsp_compr { + struct list_head list; + struct wm_adsp *dsp; + struct wm_adsp_compr_buf *buf; + + struct snd_compr_stream *stream; + struct snd_compressed_buffer size; + + u32 *raw_buf; + unsigned int copied_total; + + unsigned int sample_rate; + + const char *name; +}; + +#define WM_ADSP_DATA_WORD_SIZE_DEFAULT 3 +#define WM_ADSP_DATA_WORD_SIZE_VPU 4 + +#define WM_ADSP_DATA_WORD_MASK_DEFAULT 0x00ffffffu +#define WM_ADSP_DATA_WORD_MASK_VPU 0xffffffffu + +#define WM_ADSP_MIN_FRAGMENTS 1 +#define WM_ADSP_MAX_FRAGMENTS 256 +#define WM_ADSP_MIN_FRAGMENT_SIZE_WORDS 64 +#define WM_ADSP_MAX_FRAGMENT_SIZE_WORDS 4096 + +#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7 + +#define HOST_BUFFER_FIELD(field) \ + (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32)) + +#define ALG_XM_FIELD(field) \ + (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32)) + +#define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1 + +#define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00 +#define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8 + +static int wm_adsp_buffer_init(struct wm_adsp *dsp); +static int wm_adsp_buffer_free(struct wm_adsp *dsp); + +struct wm_adsp_buffer_region { + unsigned int offset; + unsigned int cumulative_size; + unsigned int mem_type; + unsigned int base_addr; +}; + +struct wm_adsp_buffer_region_def { + unsigned int mem_type; + unsigned int base_offset; + unsigned int size_offset; +}; + +static const struct wm_adsp_buffer_region_def default_regions[] = { + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(buf1_base), + .size_offset = HOST_BUFFER_FIELD(buf1_size), + }, + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(buf2_base), + .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size), + }, + { + .mem_type = WMFW_ADSP2_YM, + .base_offset = HOST_BUFFER_FIELD(buf3_base), + .size_offset = HOST_BUFFER_FIELD(buf_total_size), + }, +}; + +static const struct wm_adsp_buffer_region_def vpu_regions[] = { + { + .mem_type = WMFW_VPU_DM, + .base_offset = HOST_BUFFER_FIELD(buf1_base), + .size_offset = HOST_BUFFER_FIELD(buf1_size), + }, + { + .mem_type = WMFW_VPU_DM, + .base_offset = HOST_BUFFER_FIELD(buf2_base), + .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size), + }, + { + .mem_type = WMFW_VPU_DM, + .base_offset = HOST_BUFFER_FIELD(buf3_base), + .size_offset = HOST_BUFFER_FIELD(buf_total_size), + }, +}; + +struct wm_adsp_fw_caps { + u32 id; + struct snd_codec_desc desc; +}; + +static const struct wm_adsp_fw_caps ctrl_caps[] = { + { + .id = SND_AUDIOCODEC_BESPOKE, + .desc = { + .max_ch = 8, + .sample_rates = { 16000 }, + .num_sample_rates = 1, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + }, +}; + +static const struct wm_adsp_fw_caps trace_caps[] = { + { + .id = SND_AUDIOCODEC_BESPOKE, + .desc = { + .max_ch = 8, + .sample_rates = { + 4000, 8000, 11025, 12000, 16000, 22050, + 24000, 32000, 44100, 48000, 64000, 88200, + 96000, 176400, 192000 + }, + .num_sample_rates = 15, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + }, +}; + +static const struct { + const char *file; + int compr_direction; + int num_caps; + const struct wm_adsp_fw_caps *caps; + bool voice_trigger; +} wm_adsp_fw[WM_ADSP_NUM_FW] = { + [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, + [WM_ADSP_FW_HIFI] = { .file = "hifi" }, + [WM_ADSP_FW_TX] = { .file = "tx" }, + [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" }, + [WM_ADSP_FW_RX] = { .file = "rx" }, + [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" }, + [WM_ADSP_FW_CTRL] = { + .file = "ctrl", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(ctrl_caps), + .caps = ctrl_caps, + .voice_trigger = true, + }, + [WM_ADSP_FW_ASR] = { .file = "asr" }, + [WM_ADSP_FW_TRACE] = { + .file = "trace", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(trace_caps), + .caps = trace_caps, + }, + [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" }, + [WM_ADSP_FW_SPK_CALI] = { .file = "spk-cali" }, + [WM_ADSP_FW_SPK_DIAG] = { .file = "spk-diag" }, + [WM_ADSP_FW_MISC] = { .file = "misc" }, +}; + +struct wm_coeff_ctl_ops { + int (*xget)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*xput)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +}; + +struct wm_coeff_ctl { + const char *name; + const char *fw_name; + /* Subname is needed to match with firmwanre */ + const char *subname; + unsigned int subname_len; + struct wm_adsp_alg_region alg_region; + struct wm_coeff_ctl_ops ops; + struct wm_adsp *dsp; + unsigned int enabled : 1; + struct list_head list; + void *cache; + unsigned int offset; + size_t len; + unsigned int set : 1; + struct soc_bytes_ext bytes_ext; + unsigned int flags; + unsigned int type; +}; + +static const char *wm_adsp_mem_region_name(unsigned int type) +{ + switch (type) { + case WMFW_ADSP1_PM: + return "PM"; + case WMFW_HALO_PM_PACKED: + return "PM_PACKED"; + case WMFW_ADSP1_DM: + return "DM"; + case WMFW_ADSP2_XM: + return "XM"; + case WMFW_HALO_XM_PACKED: + return "XM_PACKED"; + case WMFW_ADSP2_YM: + return "YM"; + case WMFW_HALO_YM_PACKED: + return "YM_PACKED"; + case WMFW_ADSP1_ZM: + return "ZM"; + case WMFW_VPU_DM: + return "DM"; + default: + return NULL; + } +} + +#ifdef CONFIG_DEBUG_FS +static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + kfree(dsp->wmfw_file_name); + dsp->wmfw_file_name = tmp; +} + +static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + kfree(dsp->bin_file_name); + dsp->bin_file_name = tmp; +} + +static void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ + kfree(dsp->wmfw_file_name); + kfree(dsp->bin_file_name); + dsp->wmfw_file_name = NULL; + dsp->bin_file_name = NULL; +} + +static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->wmfw_file_name || !dsp->booted) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->wmfw_file_name, + strlen(dsp->wmfw_file_name)); + + mutex_unlock(&dsp->pwr_lock); + return ret; +} + +static ssize_t wm_adsp_debugfs_bin_read(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->bin_file_name || !dsp->booted) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->bin_file_name, + strlen(dsp->bin_file_name)); + + mutex_unlock(&dsp->pwr_lock); + return ret; +} + +static const struct { + const char *name; + const struct file_operations fops; +} wm_adsp_debugfs_fops[] = { + { + .name = "wmfw_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_wmfw_read, + }, + }, + { + .name = "bin_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_bin_read, + }, + }, +}; + +static void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_component *component) +{ + struct dentry *root = NULL; + int i; + + if (!component->debugfs_root) { + adsp_err(dsp, "No codec debugfs root\n"); + goto err; + } + + root = debugfs_create_dir(dsp->name, component->debugfs_root); + + if (!root) + goto err; + + if (!debugfs_create_bool("booted", 0444, root, &dsp->booted)) + goto err; + + if (!debugfs_create_bool("running", 0444, root, &dsp->running)) + goto err; + + if (!debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id)) + goto err; + + if (!debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version)) + goto err; + + for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) { + if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, + root, dsp, + &wm_adsp_debugfs_fops[i].fops)) + goto err; + } + + dsp->debugfs_root = root; + return; + +err: + debugfs_remove_recursive(root); + adsp_err(dsp, "Failed to create debugfs\n"); +} + +static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ + wm_adsp_debugfs_clear(dsp); + debugfs_remove_recursive(dsp->debugfs_root); +} +#else +static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_component *component) +{ +} + +static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ +} + +static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ +} +#endif + +int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_fw_get); + +int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + int ret = 0; + + if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw) + return 0; + + if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW) + return -EINVAL; + + mutex_lock(&dsp[e->shift_l].pwr_lock); + + if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list)) + ret = -EBUSY; + else + dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0]; + + mutex_unlock(&dsp[e->shift_l].pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_fw_put); + +const struct soc_enum wm_adsp_fw_enum[] = { + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), +}; +EXPORT_SYMBOL_GPL(wm_adsp_fw_enum); + +static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, + int type) +{ + int i; + + for (i = 0; i < dsp->num_mems; i++) + if (dsp->mem[i].type == type) + return &dsp->mem[i]; + + return NULL; +} + +static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem, + unsigned int offset) +{ + switch (mem->type) { + case WMFW_ADSP1_PM: + return mem->base + (offset * 3); + case WMFW_ADSP1_DM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_ADSP1_ZM: + return mem->base + (offset * 2); + default: + WARN(1, "Unknown memory region type"); + return offset; + } +} + +static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem, + unsigned int offset) +{ + switch (mem->type) { + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + return mem->base + (offset * 4); + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + return (mem->base + (offset * 3)) & ~0x3; + case WMFW_HALO_PM_PACKED: + return mem->base + (offset * 5); + default: + WARN(1, "Unknown memory region type"); + return offset; + } +} + +static unsigned int wm_vpu_region_to_reg(struct wm_adsp_region const *mem, + unsigned int offset) +{ + switch (mem->type) { + case WMFW_VPU_DM: + return mem->base + (offset * 4); + default: + WARN(1, "Unknown memory region type"); + return offset; + } +} + +static void wm_adsp_read_fw_status(struct wm_adsp *dsp, int noffs, + unsigned int *offs) +{ + unsigned int *scratch; + unsigned int i; + int ret; + + scratch = kmalloc(sizeof(*scratch), GFP_KERNEL | GFP_DMA); + if (!scratch) + return; + + for (i = 0; i < noffs; ++i) { + ret = regmap_read(dsp->regmap, dsp->base + offs[i], scratch); + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); + goto out; + } + + offs[i] = *scratch; + } + +out: + kfree(scratch); +} + +static void wm_adsp2_show_fw_status(struct wm_adsp *dsp) +{ + unsigned int offs[] = { + ADSP2_SCRATCH0, + ADSP2_SCRATCH1, + ADSP2_SCRATCH2, + ADSP2_SCRATCH3, + }; + + wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", offs[0], + offs[1], offs[2], offs[3]); +} + +static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) +{ + unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 }; + + wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + offs[0] & 0xFFFF, offs[0] >> 16, offs[1] & 0xFFFF, + offs[1] >> 16); +} + +static void wm_halo_show_fw_status(struct wm_adsp *dsp) +{ + unsigned int offs[] = { + HALO_SCRATCH1, + HALO_SCRATCH2, + HALO_SCRATCH3, + HALO_SCRATCH4, + }; + + wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", offs[0], + offs[1], offs[2], offs[3]); +} + +static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext) +{ + return container_of(ext, struct wm_coeff_ctl, bytes_ext); +} + +static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) +{ + const struct wm_adsp_alg_region *alg_region = &ctl->alg_region; + struct wm_adsp *dsp = ctl->dsp; + const struct wm_adsp_region *mem; + + mem = wm_adsp_find_region(dsp, alg_region->type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", alg_region->type); + return -EINVAL; + } + + *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset); + + return 0; +} + +static int wm_coeff_info(struct snd_kcontrol *kctl, + struct snd_ctl_elem_info *uinfo) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE; + uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE; + uinfo->value.integer.step = 1; + uinfo->count = 1; + break; + default: + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = ctl->len; + break; + } + + return 0; +} + +static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl, + unsigned int event_id) +{ + struct wm_adsp *dsp = ctl->dsp; + u32 val = cpu_to_be32(event_id); + unsigned int reg; + int i, ret; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", + event_id, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); + + ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); + return ret; + } + + /* + * Poll for ack, we initially poll at ~1ms intervals for firmwares + * that respond quickly, then go to ~10ms polls. A firmware is unlikely + * to ack instantly so we do the first 1ms delay before reading the + * control to avoid a pointless bus transaction + */ + for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) { + switch (i) { + case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1: + usleep_range(1000, 2000); + i++; + break; + default: + usleep_range(10000, 20000); + i += 10; + break; + } + + ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); + return ret; + } + + if (val == 0) { + adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); + return 0; + } + } + + adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", reg, + ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); + + return -ETIMEDOUT; +} + +static int wm_coeff_write_control(struct wm_coeff_ctl *ctl, const void *buf, + size_t len) +{ + struct wm_adsp *dsp = ctl->dsp; + void *scratch; + int ret; + unsigned int reg; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + ret = regmap_raw_write(dsp->regmap, reg, scratch, len); + if (ret) { + adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", len, reg, + ret); + kfree(scratch); + return ret; + } + adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); + + kfree(scratch); + + return 0; +} + +static int wm_coeff_put(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + ret = -EPERM; + else + memcpy(ctl->cache, p, ctl->len); + + ctl->set = 1; + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_control(ctl, p, ctl->len); + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_tlv_put(struct snd_kcontrol *kctl, + const unsigned int __user *bytes, unsigned int size) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (copy_from_user(ctl->cache, bytes, size)) { + ret = -EFAULT; + } else { + ctl->set = 1; + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_control(ctl, ctl->cache, size); + else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + ret = -EPERM; + } + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_put_acked(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + unsigned int val = ucontrol->value.integer.value[0]; + int ret; + + if (val == 0) + return 0; /* 0 means no event */ + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_write_acked_control(ctl, val); + else + ret = -EPERM; + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_read_control(struct wm_coeff_ctl *ctl, void *buf, + size_t len) +{ + struct wm_adsp *dsp = ctl->dsp; + void *scratch; + int ret; + unsigned int reg; + int read_len = 0; + int toread_len; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + while ((len - read_len) > 0) { + toread_len = (len - read_len) > MAX_BULKSIZE ? MAX_BULKSIZE : + (len - read_len); + regmap_raw_read(dsp->regmap, reg + read_len / REG_BYTESIZE, + scratch + read_len, toread_len); + if (ret) { + adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", + toread_len, reg + read_len / REG_BYTESIZE, + ret); + kfree(scratch); + return ret; + } + adsp_dbg(dsp, "Read %zu bytes from %x\n", toread_len, + reg + read_len / REG_BYTESIZE); + read_len += toread_len; + } + + memcpy(buf, scratch, len); + kfree(scratch); + + return 0; +} + +static int wm_coeff_get(struct snd_kcontrol *kctl, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + char *p = ucontrol->value.bytes.data; + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, p, ctl->len); + else + ret = -EPERM; + } else { + if (!ctl->flags && ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + + memcpy(p, ctl->cache, ctl->len); + } + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_tlv_get(struct snd_kcontrol *kctl, + unsigned int __user *bytes, unsigned int size) +{ + struct soc_bytes_ext *bytes_ext = + (struct soc_bytes_ext *)kctl->private_value; + struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); + int ret = 0; + + mutex_lock(&ctl->dsp->pwr_lock); + + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + if (ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, ctl->cache, size); + else + ret = -EPERM; + } else { + if (!ctl->flags && ctl->enabled && ctl->dsp->running) + ret = wm_coeff_read_control(ctl, ctl->cache, size); + } + + if (!ret && copy_to_user(bytes, ctl->cache, size)) + ret = -EFAULT; + + mutex_unlock(&ctl->dsp->pwr_lock); + + return ret; +} + +static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* + * Although it's not useful to read an acked control, we must satisfy + * user-side assumptions that all controls are readable and that a + * write of the same value should be filtered out (it's valid to send + * the same event number again to the firmware). We therefore return 0, + * meaning "no event" so valid event numbers will always be a change + */ + ucontrol->value.integer.value[0] = 0; + + return 0; +} + +struct wmfw_ctl_work { + struct wm_adsp *dsp; + struct wm_coeff_ctl *ctl; + struct work_struct work; +}; + +static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len) +{ + unsigned int out, rd, wr, vol; + + if (len > ADSP_MAX_STD_CTRL_SIZE) { + rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ; + wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE; + vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; + + out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK; + } else { + rd = SNDRV_CTL_ELEM_ACCESS_READ; + wr = SNDRV_CTL_ELEM_ACCESS_WRITE; + vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; + + out = 0; + } + + if (in) { + if (in & WMFW_CTL_FLAG_READABLE) + out |= rd; + if (in & WMFW_CTL_FLAG_WRITEABLE) + out |= wr; + if (in & WMFW_CTL_FLAG_VOLATILE) + out |= vol; + } else { + out |= rd | wr | vol; + } + + return out; +} + +static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl) +{ + struct snd_kcontrol_new *kcontrol; + int ret; + + if (!ctl || !ctl->name) + return -EINVAL; + + kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); + if (!kcontrol) + return -ENOMEM; + + kcontrol->name = ctl->name; + kcontrol->info = wm_coeff_info; + kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; + kcontrol->tlv.c = snd_soc_bytes_tlv_callback; + kcontrol->private_value = (unsigned long)&ctl->bytes_ext; + kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len); + + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + kcontrol->get = wm_coeff_get_acked; + kcontrol->put = wm_coeff_put_acked; + break; + default: + if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { + ctl->bytes_ext.max = ctl->len; + ctl->bytes_ext.get = wm_coeff_tlv_get; + ctl->bytes_ext.put = wm_coeff_tlv_put; + } else { + kcontrol->get = wm_coeff_get; + kcontrol->put = wm_coeff_put; + } + break; + } + + ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1); + if (ret < 0) + goto err_kcontrol; + + kfree(kcontrol); + + return 0; + +err_kcontrol: + kfree(kcontrol); + return ret; +} + +static int wm_coeff_init_control_caches(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (!ctl->enabled || ctl->set) + continue; + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + continue; + + /* + * For readable controls populate the cache from the DSP memory. + * For non-readable controls the cache was zero-filled when + * created so we don't need to do anything. + */ + if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) { + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static int wm_coeff_sync_controls(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (!ctl->enabled) + continue; + if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) { + ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static void wm_adsp_signal_event_controls(struct wm_adsp *dsp, + unsigned int event) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) + continue; + + if (!ctl->enabled) + continue; + + ret = wm_coeff_write_acked_control(ctl, event); + if (ret) + adsp_warn( + dsp, + "Failed to send 0x%x event to alg 0x%x (%d)\n", + event, ctl->alg_region.alg, ret); + } +} + +static void wm_adsp_ctl_work(struct work_struct *work) +{ + struct wmfw_ctl_work *ctl_work = + container_of(work, struct wmfw_ctl_work, work); + + wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl); + kfree(ctl_work); +} + +static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl) +{ + kfree(ctl->cache); + kfree(ctl->name); + kfree(ctl->subname); + kfree(ctl); +} + +static int wm_adsp_create_control(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region, + unsigned int offset, unsigned int len, + const char *subname, unsigned int subname_len, + unsigned int flags, unsigned int type) +{ + struct wm_coeff_ctl *ctl; + struct wmfw_ctl_work *ctl_work; + char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; + const char *region_name; + const char *fw_txt; + int ret; + + region_name = wm_adsp_mem_region_name(alg_region->type); + if (!region_name) { + adsp_err(dsp, "Unknown region type: %d\n", alg_region->type); + return -EINVAL; + } + + fw_txt = wm_adsp_fw_text[dsp->fw]; + + switch (dsp->fw_ver) { + case 0: + case 1: + snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x", + dsp->name, region_name, alg_region->alg); + subname = NULL; /* don't append subname */ + break; + case 2: + ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, + "%s%c %.12s %x", dsp->name, *region_name, fw_txt, + alg_region->alg); + break; + default: + ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, + "%s %.12s %x", dsp->name, fw_txt, + alg_region->alg); + break; + } + + if (subname) { + int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2; + int skip = 0; + + if (dsp->component->name_prefix) + avail -= strlen(dsp->component->name_prefix) + 1; + + /* Truncate the subname from the start if it is too long */ + if (subname_len > avail) + skip = subname_len - avail; + + snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, + " %.*s", subname_len - skip, subname + skip); + } + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (!strcmp(ctl->name, name)) { + if (!ctl->enabled) + ctl->enabled = 1; + return 0; + } + } + + ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); + if (!ctl) + return -ENOMEM; + ctl->fw_name = fw_txt; + ctl->alg_region = *alg_region; + ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL); + if (!ctl->name) { + ret = -ENOMEM; + goto err_ctl; + } + ctl->subname_len = subname_len; + if (subname) + ctl->subname = + kmemdup(subname, strlen(subname) + 1, GFP_KERNEL); + else + ctl->subname = NULL; + if (!ctl->subname) { + ret = -ENOMEM; + goto err_ctl; + } + ctl->enabled = 1; + ctl->set = 0; + ctl->ops.xget = wm_coeff_get; + ctl->ops.xput = wm_coeff_put; + ctl->dsp = dsp; + + ctl->flags = flags; + ctl->type = type; + ctl->offset = offset; + ctl->len = len; + ctl->cache = kzalloc(ctl->len, GFP_KERNEL); + if (!ctl->cache) { + ret = -ENOMEM; + goto err_ctl_name; + } + + list_add(&ctl->list, &dsp->ctl_list); + + if (flags & WMFW_CTL_FLAG_SYS) + return 0; + + ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL); + if (!ctl_work) { + ret = -ENOMEM; + goto err_ctl_cache; + } + + ctl_work->dsp = dsp; + ctl_work->ctl = ctl; + INIT_WORK(&ctl_work->work, wm_adsp_ctl_work); + schedule_work(&ctl_work->work); + + return 0; + +err_ctl_cache: + kfree(ctl->cache); +err_ctl_name: + kfree(ctl->name); +err_ctl: + kfree(ctl->subname); + kfree(ctl); + + return ret; +} + +struct wm_coeff_parsed_alg { + int id; + const u8 *name; + int name_len; + int ncoeff; +}; + +struct wm_coeff_parsed_coeff { + int offset; + int mem_type; + const u8 *name; + int name_len; + int ctl_type; + int flags; + int len; +}; + +static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str) +{ + int length; + + switch (bytes) { + case 1: + length = **pos; + break; + case 2: + length = le16_to_cpu(*((__le16 *)*pos)); + break; + default: + return 0; + } + + if (str) + *str = *pos + bytes; + + *pos += ((length + bytes) + 3) & ~0x03; + + return length; +} + +static int wm_coeff_parse_int(int bytes, const u8 **pos) +{ + int val = 0; + + switch (bytes) { + case 2: + val = le16_to_cpu(*((__le16 *)*pos)); + break; + case 4: + val = le32_to_cpu(*((__le32 *)*pos)); + break; + default: + break; + } + + *pos += bytes; + + return val; +} + +static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_alg *blk) +{ + const struct wmfw_adsp_alg_data *raw; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_alg_data *)*data; + *data = raw->data; + + blk->id = le32_to_cpu(raw->id); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ncoeff = le32_to_cpu(raw->ncoeff); + break; + default: + blk->id = wm_coeff_parse_int(sizeof(raw->id), data); + blk->name_len = + wm_coeff_parse_string(sizeof(u8), data, &blk->name); + wm_coeff_parse_string(sizeof(u16), data, NULL); + blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data); + break; + } + + adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); + adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); +} + +static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_coeff *blk) +{ + const struct wmfw_adsp_coeff_data *raw; + const u8 *tmp; + int length; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_coeff_data *)*data; + *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size); + + blk->offset = le16_to_cpu(raw->hdr.offset); + blk->mem_type = le16_to_cpu(raw->hdr.type); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ctl_type = le16_to_cpu(raw->ctl_type); + blk->flags = le16_to_cpu(raw->flags); + blk->len = le32_to_cpu(raw->len); + break; + default: + tmp = *data; + blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp); + blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp); + length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp); + blk->name_len = + wm_coeff_parse_string(sizeof(u8), &tmp, &blk->name); + wm_coeff_parse_string(sizeof(u8), &tmp, NULL); + wm_coeff_parse_string(sizeof(u16), &tmp, NULL); + blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp); + blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp); + blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp); + + *data = *data + sizeof(raw->hdr) + length; + break; + } + + adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); + adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); + adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); + adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); + adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); +} + +static int +wm_adsp_check_coeff_flags(struct wm_adsp *dsp, + const struct wm_coeff_parsed_coeff *coeff_blk, + unsigned int f_required, unsigned int f_illegal) +{ + if ((coeff_blk->flags & f_illegal) || + ((coeff_blk->flags & f_required) != f_required)) { + adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", + coeff_blk->flags, coeff_blk->ctl_type); + return -EINVAL; + } + + return 0; +} + +static int wm_adsp_parse_coeff(struct wm_adsp *dsp, + const struct wmfw_region *region) +{ + struct wm_adsp_alg_region alg_region = {}; + struct wm_coeff_parsed_alg alg_blk; + struct wm_coeff_parsed_coeff coeff_blk; + const u8 *data = region->data; + int i, ret; + + wm_coeff_parse_alg(dsp, &data, &alg_blk); + for (i = 0; i < alg_blk.ncoeff; i++) { + wm_coeff_parse_coeff(dsp, &data, &coeff_blk); + + switch (coeff_blk.ctl_type) { + case SNDRV_CTL_ELEM_TYPE_BYTES: + break; + case WMFW_CTL_TYPE_ACKED: + if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) + continue; /* ignore */ + + ret = wm_adsp_check_coeff_flags( + dsp, &coeff_blk, + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + case WMFW_CTL_TYPE_HOSTEVENT: + ret = wm_adsp_check_coeff_flags( + dsp, &coeff_blk, + WMFW_CTL_FLAG_SYS | WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + case WMFW_CTL_TYPE_HOST_BUFFER: + ret = wm_adsp_check_coeff_flags( + dsp, &coeff_blk, + WMFW_CTL_FLAG_SYS | WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + default: + adsp_err(dsp, "Unknown control type: %d\n", + coeff_blk.ctl_type); + return -EINVAL; + } + + alg_region.type = coeff_blk.mem_type; + alg_region.alg = alg_blk.id; + + ret = wm_adsp_create_control(dsp, &alg_region, coeff_blk.offset, + coeff_blk.len, coeff_blk.name, + coeff_blk.name_len, + coeff_blk.flags, + coeff_blk.ctl_type); + if (ret < 0) + adsp_err(dsp, "Failed to create control: %.*s, %d\n", + coeff_blk.name_len, coeff_blk.name, ret); + } + + return 0; +} + +static int wm_adsp_write_blocks(struct wm_adsp *dsp, const u8 *data, size_t len, + unsigned int reg, struct list_head *list, + size_t burst_multiple) + +{ + size_t to_write = PAGE_SIZE - (PAGE_SIZE % burst_multiple); + size_t remain = len; + struct wm_adsp_buf *buf; + unsigned int addr_div; + int ret; + + switch (dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + addr_div = 2; + break; + default: + addr_div = 1; + break; + } + + while (remain > 0) { + if (remain < to_write) + to_write = remain; + + buf = wm_adsp_buf_alloc(data, to_write, list); + if (!buf) { + adsp_err(dsp, "Out of memory\n"); + return -ENOMEM; + } + + ret = regmap_raw_write_async(dsp->regmap, reg, buf->buf, + to_write); + if (ret != 0) { + adsp_err(dsp, "Failed to write %zd bytes at %d\n", + to_write, reg); + + return ret; + } + + data += to_write; + reg += to_write / addr_div; + remain -= to_write; + } + + return 0; +} + +static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp, + const char *const file, + unsigned int pos, + const struct firmware *firmware) +{ + const struct wmfw_adsp1_sizes *adsp1_sizes; + + adsp1_sizes = (void *)&firmware->data[pos]; + + adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, + le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm), + le32_to_cpu(adsp1_sizes->zm)); + + return pos + sizeof(*adsp1_sizes); +} + +static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp, + const char *const file, + unsigned int pos, + const struct firmware *firmware) +{ + const struct wmfw_adsp2_sizes *adsp2_sizes; + + adsp2_sizes = (void *)&firmware->data[pos]; + + adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, + le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym), + le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm)); + + return pos + sizeof(*adsp2_sizes); +} + +static unsigned int wm_vpu_parse_sizes(struct wm_adsp *dsp, + const char *const file, unsigned int pos, + const struct firmware *firmware) +{ + const struct wmfw_vpu_sizes *vpu_sizes; + + vpu_sizes = (void *)&firmware->data[pos]; + + return pos + sizeof(*vpu_sizes); +} + +static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version) +{ + switch (version) { + case 0: + adsp_warn(dsp, "Deprecated file format %d\n", version); + return true; + case 1: + case 2: + return true; + default: + return false; + } +} + +static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version) +{ + switch (version) { + case 3: + return true; + default: + return false; + } +} + +static int wm_adsp_load(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + const struct firmware *firmware; + struct regmap *regmap = dsp->regmap; + unsigned int pos = 0; + const struct wmfw_header *header; + const struct wmfw_adsp1_sizes *adsp1_sizes; + const struct wmfw_footer *footer; + const struct wmfw_region *region; + const struct wm_adsp_region *mem; + const char *region_name; + char *file, *text = NULL; + unsigned int reg; + int regions = 0; + int ret, offset, type; + unsigned int burst_multiple; + + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + if (dsp->first_booting) + dsp->fw = WM_ADSP_FW_SPK_PROT; + + snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name, + wm_adsp_fw[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + adsp_info(dsp, "download fw algo %s, pid %d.\n", file, current->pid); + + ret = request_firmware(&firmware, file, dsp->dev); + if (ret != 0) { + adsp_err(dsp, "Failed to request '%s'\n", file); + goto out; + } + ret = -EINVAL; + + pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); + if (pos >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", file, + firmware->size); + goto out_fw; + } + + header = (void *)&firmware->data[0]; + + if (memcmp(&header->magic[0], "WMFW", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + if (!dsp->ops->validate_version(dsp, header->ver)) { + adsp_err(dsp, "%s: unknown file format %d\n", file, + header->ver); + goto out_fw; + } + + adsp_info(dsp, "Firmware version: %d\n", header->ver); + dsp->fw_ver = header->ver; + + if (header->core != dsp->type) { + adsp_err(dsp, "%s: invalid core %d != %d\n", file, header->core, + dsp->type); + goto out_fw; + } + + pos = sizeof(*header); + pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); + + footer = (void *)&firmware->data[pos]; + pos += sizeof(*footer); + + if (le32_to_cpu(header->len) != pos) { + adsp_err(dsp, "%s: unexpected header length %d\n", file, + le32_to_cpu(header->len)); + goto out_fw; + } + + adsp_dbg(dsp, "%s: timestamp %llu\n", file, + le64_to_cpu(footer->timestamp)); + + while (pos < firmware->size && sizeof(*region) < firmware->size - pos) { + region = (void *)&(firmware->data[pos]); + region_name = "Unknown"; + reg = 0; + burst_multiple = 4; + text = NULL; + offset = le32_to_cpu(region->offset) & 0xffffff; + type = be32_to_cpu(region->type) & 0xff; + + switch (type) { + case WMFW_NAME_TEXT: + region_name = "Firmware name"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); + break; + case WMFW_ALGORITHM_DATA: + region_name = "Algorithm"; + ret = wm_adsp_parse_coeff(dsp, region); + if (ret != 0) + goto out_fw; + break; + case WMFW_INFO_TEXT: + region_name = "Information"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); + break; + case WMFW_ABSOLUTE: + region_name = "Absolute"; + reg = offset; + break; + case WMFW_ADSP1_PM: + case WMFW_ADSP1_DM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_ADSP1_ZM: + case WMFW_HALO_PM_PACKED: + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No region of type: %x\n", type); + goto out_fw; + } + region_name = wm_adsp_mem_region_name(type); + reg = dsp->ops->region_to_reg(mem, offset); + + if (type == WMFW_HALO_PM_PACKED) + burst_multiple = 20; + else if ((type == WMFW_HALO_XM_PACKED) || + (type == WMFW_HALO_YM_PACKED)) + burst_multiple = 12; + + break; + default: + adsp_warn(dsp, + "%s.%d: Unknown region type %x at %d(%x)\n", + file, regions, type, pos, pos); + break; + } + + adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, regions, + le32_to_cpu(region->len), offset, region_name); + + if (le32_to_cpu(region->len) > + firmware->size - pos - sizeof(*region)) { + adsp_err( + dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, regions, region_name, + le32_to_cpu(region->len), firmware->size); + ret = -EINVAL; + goto out_fw; + } + + if (text) { + memcpy(text, region->data, le32_to_cpu(region->len)); + adsp_info(dsp, "%s: %s\n", file, text); + kfree(text); + text = NULL; + } + + if (reg) { + ret = wm_adsp_write_blocks(dsp, region->data, + le32_to_cpu(region->len), + reg, &buf_list, + burst_multiple); + if (ret != 0) { + adsp_err( + dsp, + "%s.%d: Failed writing data at %d in %s: %d\n", + file, regions, offset, region_name, + ret); + goto out_fw; + } + } + + pos += le32_to_cpu(region->len) + sizeof(*region); + regions++; + } + + ret = regmap_async_complete(regmap); + if (ret != 0) { + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + goto out_fw; + } + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, + regions, pos - firmware->size); + + wm_adsp_debugfs_save_wmfwname(dsp, file); + +out_fw: + regmap_async_complete(regmap); + wm_adsp_buf_free(&buf_list); + release_firmware(firmware); + kfree(text); +out: + kfree(file); + + return ret; +} + +/* + * Find wm_coeff_ctl with input name as its subname + * If not found, return NULL + */ +static struct wm_coeff_ctl *wm_adsp_get_ctl(struct wm_adsp *dsp, + const char *name) +{ + struct wm_coeff_ctl *pos, *rslt = NULL; + + list_for_each_entry (pos, &dsp->ctl_list, list) { + if (strncmp(pos->subname, name, pos->subname_len) == 0 && + pos->enabled) { + rslt = pos; + break; + } + } + + return rslt; +} + +int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, const void *buf, + size_t len) +{ + struct wm_coeff_ctl *ctl; + + ctl = wm_adsp_get_ctl(dsp, name); + if (!ctl) + return -EINVAL; + + if (len > ctl->len) + return -EINVAL; + + return wm_coeff_write_control(ctl, buf, len); +} +EXPORT_SYMBOL_GPL(wm_adsp_write_ctl); + +int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, void *buf, + size_t len) +{ + struct wm_coeff_ctl *ctl; + + ctl = wm_adsp_get_ctl(dsp, name); + if (!ctl) + return -EINVAL; + + if (len > ctl->len) + return -EINVAL; + + return wm_coeff_read_control(ctl, buf, len); +} +EXPORT_SYMBOL_GPL(wm_adsp_read_ctl); + +static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region) +{ + struct wm_coeff_ctl *ctl; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] && + alg_region->alg == ctl->alg_region.alg && + alg_region->type == ctl->alg_region.type) { + ctl->alg_region.base = alg_region->base; + } + } +} + +static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs, + const struct wm_adsp_region *mem, + unsigned int pos, unsigned int len) +{ + void *alg; + unsigned int reg; + int ret; + __be32 val; + + if (n_algs == 0) { + adsp_err(dsp, "No algorithms\n"); + return ERR_PTR(-EINVAL); + } + + if (n_algs > 1024) { + adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); + return ERR_PTR(-EINVAL); + } + + /* Read the terminator first to validate the length */ + reg = dsp->ops->region_to_reg(mem, pos + len); + + ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list end: %d\n", ret); + return ERR_PTR(ret); + } + + if (be32_to_cpu(val) != 0xbedead) + adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", reg, + be32_to_cpu(val)); + + /* Convert length from DSP words to bytes */ + len *= sizeof(u32); + + alg = kzalloc(len, GFP_KERNEL | GFP_DMA); + if (!alg) + return ERR_PTR(-ENOMEM); + + reg = dsp->ops->region_to_reg(mem, pos); + + ret = regmap_raw_read(dsp->regmap, reg, alg, len); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list: %d\n", ret); + kfree(alg); + return ERR_PTR(ret); + } + + return alg; +} + +static struct wm_adsp_alg_region * +wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id) +{ + struct wm_adsp_alg_region *alg_region; + + list_for_each_entry (alg_region, &dsp->alg_regions, list) { + if (id == alg_region->alg && type == alg_region->type) + return alg_region; + } + + return NULL; +} + +static struct wm_adsp_alg_region * +wm_adsp_create_region(struct wm_adsp *dsp, int type, __be32 id, __be32 base) +{ + struct wm_adsp_alg_region *alg_region; + + alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL); + if (!alg_region) + return ERR_PTR(-ENOMEM); + + alg_region->type = type; + alg_region->alg = be32_to_cpu(id); + alg_region->base = be32_to_cpu(base); + + list_add_tail(&alg_region->list, &dsp->alg_regions); + + if (dsp->fw_ver > 0) + wm_adsp_ctl_fixup_base(dsp, alg_region); + + return alg_region; +} + +static void wm_adsp_free_alg_regions(struct wm_adsp *dsp) +{ + struct wm_adsp_alg_region *alg_region; + + while (!list_empty(&dsp->alg_regions)) { + alg_region = list_first_entry(&dsp->alg_regions, + struct wm_adsp_alg_region, list); + list_del(&alg_region->list); + kfree(alg_region); + } +} + +static void wmfw_parse_id_header(struct wm_adsp *dsp, struct wmfw_id_hdr *fw, + int nalgs) +{ + dsp->fw_id = be32_to_cpu(fw->id); + dsp->fw_id_version = be32_to_cpu(fw->ver); + + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", dsp->fw_id, + (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, + nalgs); +} + +static void wmfw_v3_parse_id_header(struct wm_adsp *dsp, + struct wmfw_v3_id_hdr *fw, int nalgs) +{ + dsp->fw_id = be32_to_cpu(fw->id); + dsp->fw_id_version = be32_to_cpu(fw->ver); + dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); + + adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", + dsp->fw_id, dsp->fw_vendor_id, + (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, + nalgs); +} + +static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions, + int *type, __be32 *base) +{ + struct wm_adsp_alg_region *alg_region; + int i; + + for (i = 0; i < nregions; i++) { + alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + } + + return 0; +} + +static int wm_adsp1_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp1_id_hdr *adsp1_id; + struct wmfw_adsp1_alg_hdr *adsp1_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); + if (WARN_ON(!mem)) + return -EINVAL; + + adsp1_id = kmalloc(sizeof(*adsp1_id), GFP_KERNEL | GFP_DMA); + if (!adsp1_id) + return -ENOMEM; + + ret = regmap_raw_read(dsp->regmap, mem->base, adsp1_id, + sizeof(*adsp1_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); + goto out_adsp1_id; + } + + n_algs = be32_to_cpu(adsp1_id->n_algs); + + wmfw_parse_id_header(dsp, &adsp1_id->fw, n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, adsp1_id->fw.id, + adsp1_id->zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out_adsp1_id; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, adsp1_id->fw.id, + adsp1_id->dm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out_adsp1_id; + } + + /* Calculate offset and length in DSP words */ + pos = sizeof(*adsp1_id) / sizeof(u32); + len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32); + + adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); + if (IS_ERR(adsp1_alg)) { + ret = PTR_ERR(adsp1_alg); + goto out_adsp1_id; + } + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", i, + be32_to_cpu(adsp1_alg[i].alg.id), + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp1_alg[i].dm), + be32_to_cpu(adsp1_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, + adsp1_alg[i].alg.id, + adsp1_alg[i].dm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].dm); + len -= be32_to_cpu(adsp1_alg[i].dm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region DM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, + adsp1_alg[i].alg.id, + adsp1_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].zm); + len -= be32_to_cpu(adsp1_alg[i].zm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp1_alg); +out_adsp1_id: + kfree(adsp1_id); + return ret; +} + +static int wm_adsp2_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp2_id_hdr *adsp2_id; + struct wmfw_adsp2_alg_hdr *adsp2_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + adsp2_id = kmalloc(sizeof(*adsp2_id), GFP_KERNEL | GFP_DMA); + if (!adsp2_id) + return -ENOMEM; + + ret = regmap_raw_read(dsp->regmap, mem->base, adsp2_id, + sizeof(*adsp2_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); + goto out_adsp2_id; + } + + n_algs = be32_to_cpu(adsp2_id->n_algs); + + wmfw_parse_id_header(dsp, &adsp2_id->fw, n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, adsp2_id->fw.id, + adsp2_id->xm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out_adsp2_id; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, adsp2_id->fw.id, + adsp2_id->ym); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out_adsp2_id; + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, adsp2_id->fw.id, + adsp2_id->zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + /* Calculate offset and length in DSP words */ + pos = sizeof(*adsp2_id) / sizeof(u32); + len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32); + + adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); + if (IS_ERR(adsp2_alg)) { + ret = PTR_ERR(adsp2_alg); + goto out_adsp2_id; + } + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", i, + be32_to_cpu(adsp2_alg[i].alg.id), + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp2_alg[i].xm), + be32_to_cpu(adsp2_alg[i].ym), + be32_to_cpu(adsp2_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + adsp2_alg[i].alg.id, + adsp2_alg[i].xm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].xm); + len -= be32_to_cpu(adsp2_alg[i].xm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region XM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + adsp2_alg[i].alg.id, + adsp2_alg[i].ym); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].ym); + len -= be32_to_cpu(adsp2_alg[i].ym); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region YM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_alg[i].alg.id, + adsp2_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].zm); + len -= be32_to_cpu(adsp2_alg[i].zm); + len *= 4; + wm_adsp_create_control( + dsp, alg_region, 0, len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn( + dsp, + "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp2_alg); +out_adsp2_id: + kfree(adsp2_id); + return ret; +} + +static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id, + __be32 xm_base, __be32 ym_base) +{ + int types[] = { WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED, WMFW_ADSP2_YM, + WMFW_HALO_YM_PACKED }; + __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; + + return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases); +} + +static int wm_halo_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_halo_id_hdr *halo_id; + struct wmfw_halo_alg_hdr *halo_alg; + const struct wm_adsp_region *mem; + unsigned int pos, len, block_rev; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + halo_id = kmalloc(sizeof(*halo_id), GFP_KERNEL | GFP_DMA); + if (!halo_id) + return -ENOMEM; + + ret = regmap_raw_read(dsp->regmap, mem->base, halo_id, + sizeof(*halo_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); + goto out_halo_id; + } + + block_rev = be32_to_cpu(halo_id->fw.block_rev) >> 16; + switch (block_rev) { + case 3: + break; + default: + adsp_err(dsp, "Unknown firmware ID block version 0x%x\n", + block_rev); + ret = -EINVAL; + goto out_halo_id; + } + + n_algs = be32_to_cpu(halo_id->n_algs); + + wmfw_v3_parse_id_header(dsp, &halo_id->fw, n_algs); + + ret = wm_halo_create_regions(dsp, halo_id->fw.id, halo_id->xm_base, + halo_id->ym_base); + if (ret) + return ret; + + /* Calculate offset and length in DSP words */ + pos = sizeof(*halo_id) / sizeof(u32); + len = (sizeof(*halo_alg) * n_algs) / sizeof(u32); + + halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); + if (IS_ERR(halo_alg)) { + ret = PTR_ERR(halo_alg); + goto out_halo_id; + } + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d XM@%x YM@%x\n", i, + be32_to_cpu(halo_alg[i].alg.id), + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(halo_alg[i].alg.ver) & 0xff, + be32_to_cpu(halo_alg[i].xm_base), + be32_to_cpu(halo_alg[i].ym_base)); + + ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id, + halo_alg[i].xm_base, + halo_alg[i].ym_base); + if (ret) + goto out; + } + +out: + kfree(halo_alg); +out_halo_id: + kfree(halo_id); + return ret; +} + +static int wm_vpu_setup_algs(struct wm_adsp *vpu) +{ + const struct wm_adsp_region *mem; + struct wmfw_vpu_id_hdr *vpu_id; + struct wmfw_vpu_alg_hdr *vpu_alg; + unsigned int pos, len, block_rev; + struct wm_adsp_alg_region *alg_region; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(vpu, WMFW_VPU_DM); + if (WARN_ON(!mem)) + return -EINVAL; + + vpu_id = kmalloc(sizeof(*vpu_id), GFP_KERNEL | GFP_DMA); + if (!vpu_id) + return -ENOMEM; + + ret = regmap_raw_read(vpu->regmap, mem->base, vpu_id, sizeof(*vpu_id)); + if (ret != 0) { + adsp_err(vpu, "Failed to read algorithm info: %d\n", ret); + goto out_vpu_id; + } + + block_rev = be32_to_cpu(vpu_id->fw.block_rev) >> 16; + switch (block_rev) { + case 3: + break; + default: + adsp_err(vpu, "Unknown firmware ID block version 0x%x\n", + block_rev); + ret = -EINVAL; + goto out_vpu_id; + } + + n_algs = be32_to_cpu(vpu_id->n_algs); + + wmfw_v3_parse_id_header(vpu, &vpu_id->fw, n_algs); + + alg_region = wm_adsp_create_region(vpu, WMFW_VPU_DM, vpu_id->fw.id, + vpu_id->dm_base); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(*vpu_id) / sizeof(u32); + len = (sizeof(*vpu_alg) * n_algs) / sizeof(u32); + + vpu_alg = wm_adsp_read_algs(vpu, n_algs, mem, pos, len); + if (IS_ERR(vpu_alg)) { + ret = PTR_ERR(vpu_alg); + goto out_vpu_id; + } + + for (i = 0; i < n_algs; i++) { + adsp_info(vpu, "%d: ID %x v%d.%d.%d DM@%x\n", i, + be32_to_cpu(vpu_alg[i].alg.id), + (be32_to_cpu(vpu_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(vpu_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(vpu_alg[i].alg.ver) & 0xff, + be32_to_cpu(vpu_alg[i].dm_base)); + + alg_region = wm_adsp_create_region(vpu, WMFW_VPU_DM, + vpu_alg[i].alg.id, + vpu_alg[i].dm_base); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + } + +out: + kfree(vpu_alg); +out_vpu_id: + kfree(vpu_id); + return ret; +} + +static int wm_adsp_load_coeff(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + struct regmap *regmap = dsp->regmap; + struct wmfw_coeff_hdr *hdr; + struct wmfw_coeff_item *blk; + const struct firmware *firmware; + const struct wm_adsp_region *mem; + struct wm_adsp_alg_region *alg_region; + const char *region_name; + int ret, pos, blocks, type, offset, reg; + char *file; + unsigned int burst_multiple; + + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + if (dsp->tuning_has_prefix || dsp->component->name_prefix) + snprintf(file, PAGE_SIZE, "%s-%s-%s-%s.bin", + dsp->component->name_prefix, dsp->part, dsp->fwf_name, + wm_adsp_fw[dsp->fw].file); + else + snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, + dsp->fwf_name, wm_adsp_fw[dsp->fw].file); + + file[PAGE_SIZE - 1] = '\0'; + adsp_info(dsp, "download fw parm %s\n", file); + + ret = request_firmware(&firmware, file, dsp->dev); + if (ret != 0) { + adsp_warn(dsp, "Failed to request '%s'\n", file); + ret = 0; + goto out; + } + ret = -EINVAL; + + if (sizeof(*hdr) >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", file, + firmware->size); + goto out_fw; + } + + hdr = (void *)&firmware->data[0]; + if (memcmp(hdr->magic, "WMDR", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + switch (be32_to_cpu(hdr->rev) & 0xff) { + case 1: + break; + default: + adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", + file, be32_to_cpu(hdr->rev) & 0xff); + ret = -EINVAL; + goto out_fw; + } + + adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, + (le32_to_cpu(hdr->ver) >> 16) & 0xff, + (le32_to_cpu(hdr->ver) >> 8) & 0xff, + le32_to_cpu(hdr->ver) & 0xff); + + pos = le32_to_cpu(hdr->len); + + blocks = 0; + while (pos < firmware->size && sizeof(*blk) < firmware->size - pos) { + blk = (void *)(&firmware->data[pos]); + + type = le16_to_cpu(blk->type); + offset = le16_to_cpu(blk->offset); + + adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", file, blocks, + le32_to_cpu(blk->id), + (le32_to_cpu(blk->ver) >> 16) & 0xff, + (le32_to_cpu(blk->ver) >> 8) & 0xff, + le32_to_cpu(blk->ver) & 0xff); + adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", file, blocks, + le32_to_cpu(blk->len), offset, type); + + reg = 0; + burst_multiple = 4; + region_name = "Unknown"; + switch (type) { + case (WMFW_NAME_TEXT << 8): + case (WMFW_INFO_TEXT << 8): + case (WMFW_METADATA << 8): + break; + case (WMFW_ABSOLUTE << 8): + /* + * Old files may use this for global + * coefficients. + */ + if (le32_to_cpu(blk->id) == dsp->fw_id && offset == 0) { + region_name = "global coefficients"; + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No ZM\n"); + break; + } + reg = dsp->ops->region_to_reg(mem, 0); + + } else { + region_name = "register"; + reg = offset; + } + break; + case WMFW_HALO_PM_PACKED: + burst_multiple += 8; /* plus the 8 below yields 20 */ + /* fall through */ + case WMFW_HALO_XM_PACKED: + case WMFW_HALO_YM_PACKED: + burst_multiple += 8; /* yields 12 */ + /* fall through */ + case WMFW_VPU_DM: + case WMFW_ADSP1_DM: + case WMFW_ADSP1_ZM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", file, + blocks, le32_to_cpu(blk->len), type, + le32_to_cpu(blk->id)); + + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", type); + break; + } + + alg_region = wm_adsp_find_alg_region( + dsp, type, le32_to_cpu(blk->id)); + if (alg_region) { + reg = alg_region->base; + reg = dsp->ops->region_to_reg(mem, reg); + reg += offset; + } else { + adsp_err(dsp, "No %x for algorithm %x\n", type, + le32_to_cpu(blk->id)); + } + break; + + default: + adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", + file, blocks, type, pos); + break; + } + + if (reg) { + if (le32_to_cpu(blk->len) > + firmware->size - pos - sizeof(*blk)) { + adsp_err( + dsp, + "%s.%d: %s region len %d bytes exceeds file length %zu\n", + file, blocks, region_name, + le32_to_cpu(blk->len), firmware->size); + ret = -EINVAL; + goto out_fw; + } + + adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", file, + blocks, le32_to_cpu(blk->len), reg); + ret = wm_adsp_write_blocks(dsp, blk->data, + le32_to_cpu(blk->len), reg, + &buf_list, burst_multiple); + if (ret != 0) { + adsp_err( + dsp, + "%s.%d: Failed to write to %x in %s: %d\n", + file, blocks, reg, region_name, ret); + } + } + + pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; + blocks++; + } + + ret = regmap_async_complete(regmap); + if (ret != 0) + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, + blocks, pos - firmware->size); + + wm_adsp_debugfs_save_binname(dsp, file); + +out_fw: + regmap_async_complete(regmap); + release_firmware(firmware); + wm_adsp_buf_free(&buf_list); +out: + kfree(file); + return ret; +} + +static int wm_adsp_create_name(struct wm_adsp *dsp) +{ + char *p; + + if (!dsp->name) { + dsp->name = + devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", dsp->num); + if (!dsp->name) + return -ENOMEM; + } + + if (!dsp->fwf_name) { + p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL); + if (!p) + return -ENOMEM; + + dsp->fwf_name = p; + for (; *p != 0; ++p) + *p = tolower(*p); + } + + return 0; +} + +static int wm_adsp_common_init(struct wm_adsp *dsp) +{ + int ret; + + ret = wm_adsp_create_name(dsp); + if (ret) + return ret; + + INIT_LIST_HEAD(&dsp->alg_regions); + INIT_LIST_HEAD(&dsp->ctl_list); + INIT_LIST_HEAD(&dsp->compr_list); + INIT_LIST_HEAD(&dsp->buffer_list); + + mutex_init(&dsp->pwr_lock); + + return 0; +} + +int wm_adsp1_init(struct wm_adsp *dsp) +{ + dsp->ops = &wm_adsp1_ops; + + return wm_adsp_common_init(dsp); +} +EXPORT_SYMBOL_GPL(wm_adsp1_init); + +int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + int ret; + unsigned int val; + + dsp->component = component; + + mutex_lock(&dsp->pwr_lock); + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, ADSP1_SYS_ENA); + + /* + * For simplicity set the DSP clock rate to be the + * SYSCLK rate rather than making it configurable. + */ + if (dsp->sysclk_reg) { + ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); + if (ret != 0) { + adsp_err(dsp, + "Failed to read SYSCLK state: %d\n", + ret); + goto err_mutex; + } + + val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; + + ret = regmap_update_bits(dsp->regmap, + dsp->base + ADSP1_CONTROL_31, + ADSP1_CLK_SEL_MASK, val); + if (ret != 0) { + adsp_err(dsp, "Failed to set clock rate: %d\n", + ret); + goto err_mutex; + } + } + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp1_setup_algs(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err_ena; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err_ena; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err_ena; + + dsp->booted = true; + + /* Start the core running */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, + ADSP1_CORE_ENA | ADSP1_START); + + dsp->running = true; + break; + + case SND_SOC_DAPM_PRE_PMD: + dsp->running = false; + dsp->booted = false; + + /* Halt the core */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, + ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); + + list_for_each_entry (ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + break; + + default: + break; + } + + mutex_unlock(&dsp->pwr_lock); + + return 0; + +err_ena: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); +err_mutex: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp1_event); + +static int wm_adsp2v2_enable_core(struct wm_adsp *dsp) +{ + unsigned int val; + int ret, count; + + /* Wait for the RAM to start, should be near instantaneous */ + for (count = 0; count < 10; ++count) { + ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); + if (ret != 0) + return ret; + + if (val & ADSP2_RAM_RDY) + break; + + usleep_range(250, 500); + } + + if (!(val & ADSP2_RAM_RDY)) { + adsp_err(dsp, "Failed to start DSP RAM\n"); + return -EBUSY; + } + + adsp_dbg(dsp, "RAM ready after %d polls\n", count); + + return 0; +} + +static int wm_adsp2_enable_core(struct wm_adsp *dsp) +{ + int ret; + + ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, ADSP2_SYS_ENA); + if (ret != 0) + return ret; + + return wm_adsp2v2_enable_core(dsp); +} + +static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions) +{ + struct regmap *regmap = dsp->regmap; + unsigned int code0, code1, lock_reg; + + if (!(lock_regions & WM_ADSP2_REGION_ALL)) + return 0; + + lock_regions &= WM_ADSP2_REGION_ALL; + lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; + + while (lock_regions) { + code0 = code1 = 0; + if (lock_regions & BIT(0)) { + code0 = ADSP2_LOCK_CODE_0; + code1 = ADSP2_LOCK_CODE_1; + } + if (lock_regions & BIT(1)) { + code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT; + code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT; + } + regmap_write(regmap, lock_reg, code0); + regmap_write(regmap, lock_reg, code1); + lock_regions >>= 2; + lock_reg += 2; + } + + return 0; +} + +static int wm_adsp2_enable_memory(struct wm_adsp *dsp) +{ + return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, ADSP2_MEM_ENA); +} + +static void wm_adsp2_disable_memory(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); +} + +static void wm_adsp2_disable_core(struct wm_adsp *dsp) +{ + regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, 0); +} + +static void wm_adsp2v2_disable_core(struct wm_adsp *dsp) +{ + regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); +} + +void wm_adsp_boot_work(struct work_struct *work) +{ + struct wm_adsp *dsp = container_of(work, struct wm_adsp, boot_work); + int ret; + + mutex_lock(&dsp->pwr_lock); + + if (dsp->ops->enable_memory) { + ret = dsp->ops->enable_memory(dsp); + if (ret != 0) + goto err_mutex; + } + + if (dsp->ops->enable_core) { + ret = dsp->ops->enable_core(dsp); + if (ret != 0) + goto err_mem; + } + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err_ena; + + ret = dsp->ops->setup_algs(dsp); + if (ret != 0) + goto err_ena; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err_ena; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err_ena; + + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); + + dsp->booted = true; + + mutex_unlock(&dsp->pwr_lock); + + return; + +err_ena: + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); +err_mem: + if (dsp->ops->disable_memory) + dsp->ops->disable_memory(dsp); +err_mutex: + mutex_unlock(&dsp->pwr_lock); +} + +static int wm_halo_set_rate_block(struct wm_adsp *dsp, unsigned int rate_base, + unsigned int n_rates, const u8 *rate_cache) +{ + unsigned int addr = dsp->base + rate_base, val; + int ret, i; + + mutex_lock(dsp->rate_lock); + + for (i = 0; i < n_rates; ++i) { + val = rate_cache[i] << HALO_DSP_RATE_SHIFT; + + ret = regmap_update_bits(dsp->regmap, addr + (i * 8), + HALO_DSP_RATE_MASK, val); + if (ret) { + adsp_err(dsp, "Failed to set rate: %d\n", ret); + mutex_unlock(dsp->rate_lock); + return ret; + } + + // adsp_dbg(dsp, "Set rate %d to 0x%x\n", i, val); + } + + udelay(300); + + mutex_unlock(dsp->rate_lock); + + return 0; +} + +static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions) +{ + struct reg_sequence config[] = { + { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, + { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, + { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, + { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, + { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, + { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, + { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, + { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, + { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, + { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, + }; + + return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); +} + +int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret; + + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, + ADSP2_CLK_SEL_MASK, + freq << ADSP2_CLK_SEL_SHIFT); + if (ret) + adsp_err(dsp, "Failed to set clock rate: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk); + +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct wm_adsp *dsp = &dsps[mc->shift - 1]; + + ucontrol->value.integer.value[0] = dsp->preloaded; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get); + +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct wm_adsp *dsp = &dsps[mc->shift - 1]; + char preload[32]; + + snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); + + dsp->preloaded = ucontrol->value.integer.value[0]; + + if (ucontrol->value.integer.value[0]) + snd_soc_component_force_enable_pin(component, preload); + else + snd_soc_component_disable_pin(component, preload); + + snd_soc_dapm_sync(dapm); + + //flush_work(&dsp->boot_work); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put); + +static void wm_adsp_stop_watchdog(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, + ADSP2_WDT_ENA_MASK, 0); +} + +static void wm_halo_stop_watchdog(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, + HALO_WDT_EN_MASK, 0); +} + +int wm_adsp_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (dsp->first_booting) { + adsp_dbg( + dsp, + "During first time booting, not queue boot_work again.\n"); + flush_work(&dsp->boot_work); + dsp->first_booting = false; + } else + queue_work(dsp->work_queue, &dsp->boot_work); + + break; + case SND_SOC_DAPM_PRE_PMD: + mutex_lock(&dsp->pwr_lock); + + wm_adsp_debugfs_clear(dsp); + + dsp->fw_id = 0; + dsp->fw_id_version = 0; + + dsp->booted = false; + + if (dsp->ops->disable_memory) + dsp->ops->disable_memory(dsp); + + list_for_each_entry (ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Shutdown complete\n"); + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_early_event); + +static int wm_adsp2_start_core(struct wm_adsp *dsp) +{ + return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, + ADSP2_CORE_ENA | ADSP2_START); +} + +static void wm_adsp2_stop_core(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, 0); +} + +static int wm_halo_apply_calibration(struct snd_soc_dapm_widget *w) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret, val; + + adsp_dbg(dsp, "%s:\n", __func__); + + switch (dsp->fw) { + case WM_ADSP_FW_SPK_CALI: + val = cpu_to_be32(dsp->cal_ambient); + ret = wm_adsp_write_ctl(dsp, "CAL_AMBIENT", (void *)&val, + sizeof(__be32)); + if (ret) + adsp_dbg(dsp, "%s: Write CAL_AMBIENT, ret=%d\n", + __func__, ret); + break; + case WM_ADSP_FW_SPK_PROT: + val = cpu_to_be32(dsp->cal_r); + ret = wm_adsp_write_ctl(dsp, "CAL_R", (void *)&val, + sizeof(__be32)); + if (ret) + adsp_dbg(dsp, "%s: Write CAL_R, ret=%d\n", __func__, + ret); + + val = cpu_to_be32(dsp->cal_status); + ret = wm_adsp_write_ctl(dsp, "CAL_STATUS", (void *)&val, + sizeof(__be32)); + if (ret) + adsp_dbg(dsp, "%s: Write CAL_STATUS ret=%d\n", __func__, + ret); + + val = cpu_to_be32(dsp->cal_checksum); + ret = wm_adsp_write_ctl(dsp, "CAL_CHECKSUM", (void *)&val, + sizeof(__be32)); + if (ret) + adsp_dbg(dsp, "%s: Write CAL_CHECKSUM ret=%d\n", + __func__, ret); + +#if 0 // DC detection + val = cpu_to_be32(150); + ret = wm_adsp_write_ctl(dsp, "DC_OFFSET_HOLD_TIME", (void *)&val, sizeof(__be32)); + if (ret) + adsp_warn(dsp, "%s: Write DC_OFFSET_HOLD_TIME ret=%d\n", __func__, ret); +#endif + break; + default: + adsp_dbg(dsp, "Do nothing\n"); + break; + } + + return 0; +} + +int wm_adsp_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); + struct wm_adsp *dsp = &dsps[w->shift]; + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + flush_work(&dsp->boot_work); + + mutex_lock(&dsp->pwr_lock); + + if (!dsp->booted) { + ret = -EIO; + goto err; + } + + if (dsp->ops->enable_core) { + ret = dsp->ops->enable_core(dsp); + if (ret != 0) + goto err; + } + + wm_halo_apply_calibration(w); + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; + + if (dsp->ops->lock_memory) { + ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); + if (ret != 0) { + adsp_err(dsp, "Error configuring MPU: %d\n", + ret); + goto err; + } + } + + if (dsp->ops->start_core) { + ret = dsp->ops->start_core(dsp); + if (ret != 0) + goto err; + } + + if (wm_adsp_fw[dsp->fw].num_caps != 0) { + ret = wm_adsp_buffer_init(dsp); + if (ret < 0) + goto err; + } + + dsp->running = true; + + mutex_unlock(&dsp->pwr_lock); + adsp_dbg(dsp, "Execution started\n"); + break; + + case SND_SOC_DAPM_PRE_PMD: + /* Tell the firmware to cleanup */ + wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); + + if (dsp->ops->stop_watchdog) + dsp->ops->stop_watchdog(dsp); + + /* Log firmware state, it can be useful for analysis */ + if (dsp->ops->show_fw_status) + dsp->ops->show_fw_status(dsp); + + mutex_lock(&dsp->pwr_lock); + + dsp->running = false; + + if (dsp->ops->stop_core) + dsp->ops->stop_core(dsp); + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); + + if (wm_adsp_fw[dsp->fw].num_caps != 0) + wm_adsp_buffer_free(dsp); + + dsp->fatal_error = false; + + mutex_unlock(&dsp->pwr_lock); + + adsp_dbg(dsp, "Execution stopped\n"); + break; + + default: + break; + } + + return 0; +err: + if (dsp->ops->stop_core) + dsp->ops->stop_core(dsp); + if (dsp->ops->disable_core) + dsp->ops->disable_core(dsp); + mutex_unlock(&dsp->pwr_lock); + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_event); + +static int wm_halo_start_core(struct wm_adsp *dsp) +{ + int ret; + + adsp_dbg(dsp, "Setting RX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_RX1, + dsp->n_rx_channels, dsp->rx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set RX rates.\n"); + return ret; + } + + adsp_dbg(dsp, "Setting TX rates.\n"); + ret = wm_halo_set_rate_block(dsp, HALO_SAMPLE_RATE_TX1, + dsp->n_tx_channels, dsp->tx_rate_cache); + if (ret) { + adsp_err(dsp, "Failed to set TX rates.\n"); + return ret; + } + + return regmap_update_bits(dsp->regmap, + dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, HALO_CORE_EN); +} + +static void wm_halo_stop_core(struct wm_adsp *dsp) +{ + regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, + HALO_CORE_EN, 0); + + /* reset halo core with CORE_SOFT_RESET */ + regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, + HALO_CORE_SOFT_RESET_MASK, 1); +} + +static int wm_adsp_cal_ambient_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->cal_ambient; + adsp_dbg(dsp, "get ambient = %d\n", ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_cal_ambient_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->cal_ambient = ucontrol->value.enumerated.item[0]; + + adsp_dbg(dsp, "put ambient = %d\n", dsp->cal_ambient); + + return 0; +} + +static int wm_adsp_cal_r_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->cal_r; + adsp_dbg(dsp, "get cal_r = %d\n", ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_cal_r_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->cal_r = ucontrol->value.enumerated.item[0]; + dsp->cal_checksum = dsp->cal_r + CAL_STATUS_DEFAULT; + + adsp_dbg(dsp, "put cal_r = %d, cal_checksum = %d\n", dsp->cal_r, + dsp->cal_checksum); + + return 0; +} + +static int wm_adsp_cal_status_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->cal_status; + adsp_dbg(dsp, "get calib status = %d\n", + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_cal_status_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->cal_status = ucontrol->value.enumerated.item[0]; + + adsp_dbg(dsp, "put calib status = %d\n", dsp->cal_status); + + return 0; +} + +static int wm_adsp_cal_checksum_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + ucontrol->value.enumerated.item[0] = dsp->cal_checksum; + adsp_dbg(dsp, "get calib checksum = %d\n", + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int wm_adsp_cal_checksum_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); + + dsp->cal_checksum = ucontrol->value.enumerated.item[0]; + + adsp_dbg(dsp, "put calib checksum = %d\n", dsp->cal_checksum); + + return 0; +} + +const struct snd_kcontrol_new wm_adsp_cal_controls[] = { + /* In Halo DSP, values are 24-bit */ + SOC_SINGLE_EXT("DSP Set CAL_AMBIENT", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_ambient_get, wm_adsp_cal_ambient_put), + SOC_SINGLE_EXT("DSP Set CAL_R", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_r_get, wm_adsp_cal_r_put), + SOC_SINGLE_EXT("DSP Set CAL_STATUS", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_status_get, wm_adsp_cal_status_put), + SOC_SINGLE_EXT("DSP Set CAL_CHECKSUM", SND_SOC_NOPM, 0, 0xFFFFFF, 0, + wm_adsp_cal_checksum_get, wm_adsp_cal_checksum_put), +}; +EXPORT_SYMBOL_GPL(wm_adsp_cal_controls); + +int wm_adsp2_component_probe(struct wm_adsp *dsp, + struct snd_soc_component *component) +{ + char preload[32]; + + if (!dsp->no_preloader) { + snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); + snd_soc_component_disable_pin(component, preload); + } + + wm_adsp2_init_debugfs(dsp, component); + + dsp->component = component; + + snd_soc_add_component_controls(component, wm_adsp_cal_controls, + ARRAY_SIZE(wm_adsp_cal_controls)); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_component_probe); + +int wm_adsp2_component_remove(struct wm_adsp *dsp, + struct snd_soc_component *component) +{ + wm_adsp2_cleanup_debugfs(dsp); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_component_remove); + +int wm_adsp2_init(struct wm_adsp *dsp) +{ + int ret; + + ret = wm_adsp_common_init(dsp); + if (ret) + return ret; + + switch (dsp->rev) { + case 0: + /* + * Disable the DSP memory by default when in reset for a small + * power saving. + */ + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); + if (ret) { + adsp_err(dsp, "Failed to clear memory retention: %d\n", + ret); + return ret; + } + + dsp->ops = &wm_adsp2_ops[0]; + break; + case 1: + dsp->ops = &wm_adsp2_ops[1]; + break; + default: + dsp->ops = &wm_adsp2_ops[2]; + break; + } + + INIT_WORK(&dsp->boot_work, wm_adsp_boot_work); + + dsp->data_word_size = WM_ADSP_DATA_WORD_SIZE_DEFAULT; + dsp->data_word_mask = WM_ADSP_DATA_WORD_MASK_DEFAULT; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_init); + +int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock) +{ + int ret; + + ret = wm_adsp_common_init(dsp); + if (ret) + return ret; + + dsp->ops = &wm_halo_ops; + dsp->work_queue = create_workqueue("cirrus_fw"); + INIT_WORK(&dsp->boot_work, wm_adsp_boot_work); + + dsp->rate_lock = rate_lock; + dsp->rx_rate_cache = + kcalloc(dsp->n_rx_channels, sizeof(u8), GFP_KERNEL); + dsp->tx_rate_cache = + kcalloc(dsp->n_tx_channels, sizeof(u8), GFP_KERNEL); + + dsp->data_word_size = WM_ADSP_DATA_WORD_SIZE_DEFAULT; + dsp->data_word_mask = WM_ADSP_DATA_WORD_MASK_DEFAULT; + + // Preset speaker calibration default value + dsp->cal_ambient = AMBIENT_DEFAULT; + dsp->cal_r = CAL_R_DEFAULT; + dsp->cal_status = CAL_STATUS_DEFAULT; + dsp->cal_checksum = CAL_R_DEFAULT + CAL_STATUS_DEFAULT; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_halo_init); + +int wm_vpu_init(struct wm_adsp *vpu) +{ + int ret; + + ret = wm_adsp_common_init(vpu); + if (ret) + return ret; + + vpu->ops = &wm_vpu_ops; + + INIT_WORK(&vpu->boot_work, wm_adsp_boot_work); + + vpu->data_word_size = WM_ADSP_DATA_WORD_SIZE_VPU; + vpu->data_word_mask = WM_ADSP_DATA_WORD_MASK_VPU; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_vpu_init); + +void wm_adsp2_remove(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + + while (!list_empty(&dsp->ctl_list)) { + ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl, + list); + list_del(&ctl->list); + wm_adsp_free_ctl_blk(ctl); + } + + kfree(dsp->rx_rate_cache); + kfree(dsp->tx_rate_cache); +} +EXPORT_SYMBOL_GPL(wm_adsp2_remove); + +static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr) +{ + return compr->buf != NULL; +} + +static int wm_adsp_compr_attach(struct wm_adsp_compr *compr) +{ + struct wm_adsp_compr_buf *buf = NULL, *tmp; + + if (compr->dsp->fatal_error) + return -EINVAL; + + list_for_each_entry (tmp, &compr->dsp->buffer_list, list) { + if (!tmp->name || !strcmp(compr->name, tmp->name)) { + buf = tmp; + break; + } + } + + if (!buf) + return -EINVAL; + + compr->buf = buf; + buf->compr = compr; + + return 0; +} + +static void wm_adsp_compr_detach(struct wm_adsp_compr *compr) +{ + if (!compr) + return; + + /* Wake the poll so it can see buffer is no longer attached */ + if (compr->stream) + snd_compr_fragment_elapsed(compr->stream); + + if (wm_adsp_compr_attached(compr)) { + compr->buf->compr = NULL; + compr->buf = NULL; + } +} + +int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream) +{ + struct wm_adsp_compr *compr, *tmp; + struct snd_soc_pcm_runtime *rtd = stream->private_data; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + if (wm_adsp_fw[dsp->fw].num_caps == 0) { + adsp_err(dsp, "%s: Firmware does not support compressed API\n", + rtd->codec_dai->name); + ret = -ENXIO; + goto out; + } + + if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) { + adsp_err(dsp, + "%s: Firmware does not support stream direction\n", + rtd->codec_dai->name); + ret = -EINVAL; + goto out; + } + + list_for_each_entry (tmp, &dsp->compr_list, list) { + if (!strcmp(tmp->name, rtd->codec_dai->name)) { + adsp_err(dsp, + "%s: Only a single stream supported per dai\n", + rtd->codec_dai->name); + ret = -EBUSY; + goto out; + } + } + + compr = kzalloc(sizeof(*compr), GFP_KERNEL); + if (!compr) { + ret = -ENOMEM; + goto out; + } + + compr->dsp = dsp; + compr->stream = stream; + compr->name = rtd->codec_dai->name; + + list_add_tail(&compr->list, &dsp->compr_list); + + stream->runtime->private_data = compr; + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_open); + +int wm_adsp_compr_free(struct snd_compr_stream *stream) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + + mutex_lock(&dsp->pwr_lock); + + wm_adsp_compr_detach(compr); + list_del(&compr->list); + + kfree(compr->raw_buf); + kfree(compr); + + mutex_unlock(&dsp->pwr_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_free); + +static int wm_adsp_compr_check_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + const struct wm_adsp_fw_caps *caps; + const struct snd_codec_desc *desc; + int i, j; + + if (params->buffer.fragment_size < + (WM_ADSP_MIN_FRAGMENT_SIZE_WORDS * dsp->data_word_size) || + params->buffer.fragment_size > + (WM_ADSP_MAX_FRAGMENT_SIZE_WORDS * dsp->data_word_size) || + params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS || + params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS || + params->buffer.fragment_size % dsp->data_word_size) { + compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n", + params->buffer.fragment_size, + params->buffer.fragments); + + return -EINVAL; + } + + for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) { + caps = &wm_adsp_fw[dsp->fw].caps[i]; + desc = &caps->desc; + + if (caps->id != params->codec.id) + continue; + + if (stream->direction == SND_COMPRESS_PLAYBACK) { + if (desc->max_ch < params->codec.ch_out) + continue; + } else { + if (desc->max_ch < params->codec.ch_in) + continue; + } + + if (!(desc->formats & (1 << params->codec.format))) + continue; + + for (j = 0; j < desc->num_sample_rates; ++j) + if (desc->sample_rates[j] == params->codec.sample_rate) + return 0; + } + + compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n", + params->codec.id, params->codec.ch_in, params->codec.ch_out, + params->codec.sample_rate, params->codec.format); + return -EINVAL; +} + +static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr) +{ + return compr->size.fragment_size / compr->dsp->data_word_size; +} + +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + unsigned int size; + int ret; + + ret = wm_adsp_compr_check_params(stream, params); + if (ret) + return ret; + + compr->size = params->buffer; + + compr_dbg(compr, "fragment_size=%d fragments=%d\n", + compr->size.fragment_size, compr->size.fragments); + + size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf); + compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL); + if (!compr->raw_buf) + return -ENOMEM; + + compr->sample_rate = params->codec.sample_rate; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params); + +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int fw = compr->dsp->fw; + int i; + + if (wm_adsp_fw[fw].caps) { + for (i = 0; i < wm_adsp_fw[fw].num_caps; i++) + caps->codecs[i] = wm_adsp_fw[fw].caps[i].id; + + caps->num_codecs = i; + caps->direction = wm_adsp_fw[fw].compr_direction; + + caps->min_fragment_size = + WM_ADSP_MIN_FRAGMENT_SIZE_WORDS * dsp->data_word_size; + caps->max_fragment_size = + WM_ADSP_MAX_FRAGMENT_SIZE_WORDS * dsp->data_word_size; + caps->min_fragments = WM_ADSP_MIN_FRAGMENTS; + caps->max_fragments = WM_ADSP_MAX_FRAGMENTS; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps); + +static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, + unsigned int num_words, u32 *data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); + unsigned int i, reg; + unsigned int data_word_mask = dsp->data_word_mask; + int ret; + + if (!mem) + return -EINVAL; + + reg = dsp->ops->region_to_reg(mem, mem_addr); + + ret = regmap_raw_read(dsp->regmap, reg, data, + sizeof(*data) * num_words); + if (ret < 0) + return ret; + + for (i = 0; i < num_words; ++i) + data[i] = be32_to_cpu(data[i]) & data_word_mask; + + return 0; +} + +static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 *data) +{ + return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data); +} + +static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); + unsigned int reg; + + if (!mem) + return -EINVAL; + + reg = dsp->ops->region_to_reg(mem, mem_addr); + + data = cpu_to_be32(data & dsp->data_word_mask); + + return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data)); +} + +static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 *data) +{ + return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type, + buf->host_buf_ptr + field_offset, data); +} + +static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 data) +{ + return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type, + buf->host_buf_ptr + field_offset, data); +} + +static void wm_adsp_remove_padding(u32 *buf, int nwords, int data_word_size) +{ + u8 *pack_in = (u8 *)buf; + u8 *pack_out = (u8 *)buf; + int i, j; + + /* Remove the padding bytes from the data read from the DSP */ + for (i = 0; i < nwords; i++) { + for (j = 0; j < data_word_size; j++) + *pack_out++ = *pack_in++; + + pack_in += sizeof(*buf) - data_word_size; + } +} + +static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf) +{ + struct wm_adsp_buffer_region *region; + u32 offset = 0; + int i, ret; + + switch (buf->dsp->type) { + case WMFW_ADSP1: + case WMFW_ADSP2: + case WMFW_HALO: + buf->num_regions = ARRAY_SIZE(default_regions); + buf->region_def = default_regions; + break; + case WMFW_VPU: + buf->num_regions = ARRAY_SIZE(vpu_regions); + buf->region_def = vpu_regions; + break; + default: + return -EINVAL; + } + + buf->regions = + kcalloc(buf->num_regions, sizeof(*buf->regions), GFP_KERNEL); + if (!buf->regions) + return -ENOMEM; + + for (i = 0; i < buf->num_regions; ++i) { + region = &buf->regions[i]; + + region->offset = offset; + region->mem_type = buf->region_def[i].mem_type; + + ret = wm_adsp_buffer_read(buf, buf->region_def[i].base_offset, + ®ion->base_addr); + if (ret < 0) + return ret; + + ret = wm_adsp_buffer_read(buf, buf->region_def[i].size_offset, + &offset); + if (ret < 0) + return ret; + + region->cumulative_size = offset; + + compr_dbg(buf, + "region=%d type=%d base=%08x off=%08x size=%08x\n", i, + region->mem_type, region->base_addr, region->offset, + region->cumulative_size); + } + + return 0; +} + +static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf) +{ + buf->irq_count = 0xFFFFFFFF; + buf->read_index = -1; + buf->avail = 0; +} + +static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf; + + buf = kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) + return NULL; + + buf->dsp = dsp; + + wm_adsp_buffer_clear(buf); + + list_add_tail(&buf->list, &dsp->buffer_list); + + return buf; +} + +static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp) +{ + struct wm_adsp_alg_region *alg_region; + struct wm_adsp_compr_buf *buf; + u32 xmalg, addr, magic; + int i, ret; + + alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id); + if (!alg_region) { + adsp_err(dsp, "No algorithm region found\n"); + return -EINVAL; + } + + buf = wm_adsp_buffer_alloc(dsp); + if (!buf) + return -ENOMEM; + + xmalg = dsp->ops->sys_config_size / sizeof(__be32); + + addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic); + if (ret < 0) + return ret; + + if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC) + return -ENODEV; + + addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr); + for (i = 0; i < 5; ++i) { + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, + &buf->host_buf_ptr); + if (ret < 0) + return ret; + + if (buf->host_buf_ptr) + break; + + usleep_range(1000, 2000); + } + + if (!buf->host_buf_ptr) + return -EIO; + + buf->host_buf_mem_type = WMFW_ADSP2_XM; + + ret = wm_adsp_buffer_populate(buf); + if (ret < 0) + return ret; + + compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr); + + return 0; +} + +static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl) +{ + int ret, i; + unsigned int val, reg; + struct wm_adsp_host_buf_coeff_v1 coeff_v1; + struct wm_adsp_compr_buf *buf; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + for (i = 0; i < 5; ++i) { + ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val)); + if (ret < 0) + return ret; + + if (val) + break; + + usleep_range(1000, 2000); + } + + if (!val) { + adsp_err(ctl->dsp, "Failed to acquire host buffer\n"); + return -EIO; + } + + buf = wm_adsp_buffer_alloc(ctl->dsp); + if (!buf) + return -ENOMEM; + + buf->host_buf_mem_type = ctl->alg_region.type; + buf->host_buf_ptr = be32_to_cpu(val); + + ret = wm_adsp_buffer_populate(buf); + if (ret < 0) + return ret; + + /* + * v0 host_buffer coefficients didn't have versioning, so if the + * control is one word, assume version 0. + */ + if (ctl->len == 4) { + compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr); + return 0; + } + + ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1, + sizeof(coeff_v1)); + if (ret < 0) + return ret; + + coeff_v1.versions = be32_to_cpu(coeff_v1.versions); + val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK; + val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT; + + if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) { + adsp_err(ctl->dsp, + "Host buffer coeff ver %u > supported version %u\n", + val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(coeff_v1.name); i++) + coeff_v1.name[i] = be32_to_cpu(coeff_v1.name[i]); + + wm_adsp_remove_padding((u32 *)&coeff_v1.name, ARRAY_SIZE(coeff_v1.name), + ctl->dsp->data_word_size); + + buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part, + (char *)&coeff_v1.name); + + compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n", buf->host_buf_ptr, + val); + + return val; +} + +static int wm_adsp_buffer_init(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry (ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER) + continue; + + if (!ctl->enabled) + continue; + + ret = wm_adsp_buffer_parse_coeff(ctl); + if (ret < 0) { + adsp_err(dsp, "Failed to parse coeff: %d\n", ret); + goto error; + } else if (ret == 0) { + /* Only one buffer supported for version 0 */ + return 0; + } + } + + if (list_empty(&dsp->buffer_list)) { + /* Fall back to legacy support */ + ret = wm_adsp_buffer_parse_legacy(dsp); + if (ret) { + adsp_err(dsp, "Failed to parse legacy: %d\n", ret); + goto error; + } + } + + return 0; + +error: + wm_adsp_buffer_free(dsp); + return ret; +} + +static int wm_adsp_buffer_free(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf, *tmp; + + list_for_each_entry_safe (buf, tmp, &dsp->buffer_list, list) { + wm_adsp_compr_detach(buf->compr); + + kfree(buf->name); + kfree(buf->regions); + list_del(&buf->list); + kfree(buf); + } + + return 0; +} + +static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf) +{ + int ret; + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error); + if (ret < 0) { + compr_err(buf, "Failed to check buffer error: %d\n", ret); + return ret; + } + if (buf->error != 0) { + compr_err(buf, "Buffer error occurred: %d\n", buf->error); + return -EIO; + } + + return 0; +} + +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int ret = 0; + + compr_dbg(compr, "Trigger: %d\n", cmd); + + mutex_lock(&dsp->pwr_lock); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (!wm_adsp_compr_attached(compr)) { + ret = wm_adsp_compr_attach(compr); + if (ret < 0) { + compr_err( + compr, + "Failed to link buffer and stream: %d\n", + ret); + break; + } + } + + ret = wm_adsp_buffer_get_error(compr->buf); + if (ret < 0) + break; + + /* Trigger the IRQ at one fragment of data */ + ret = wm_adsp_buffer_write(compr->buf, + HOST_BUFFER_FIELD(high_water_mark), + wm_adsp_compr_frag_words(compr)); + if (ret < 0) { + compr_err(compr, "Failed to set high water mark: %d\n", + ret); + break; + } + break; + case SNDRV_PCM_TRIGGER_STOP: + if (wm_adsp_compr_attached(compr)) + wm_adsp_buffer_clear(compr->buf); + break; + default: + ret = -EINVAL; + break; + } + + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger); + +static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf) +{ + int last_region = buf->num_regions - 1; + + return buf->regions[last_region].cumulative_size; +} + +static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf) +{ + u32 next_read_index, next_write_index; + int write_index, read_index, avail; + int ret; + + /* Only sync read index if we haven't already read a valid index */ + if (buf->read_index < 0) { + ret = wm_adsp_buffer_read(buf, + HOST_BUFFER_FIELD(next_read_index), + &next_read_index); + if (ret < 0) + return ret; + + read_index = sign_extend32(next_read_index, 23); + + if (read_index < 0) { + compr_dbg(buf, "Avail check on unstarted stream\n"); + return 0; + } + + buf->read_index = read_index; + } + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index), + &next_write_index); + if (ret < 0) + return ret; + + write_index = sign_extend32(next_write_index, 23); + + avail = write_index - buf->read_index; + if (avail < 0) + avail += wm_adsp_buffer_size(buf); + + compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n", + buf->read_index, write_index, + avail * buf->dsp->data_word_size); + + buf->avail = avail; + + return 0; +} + +int wm_adsp_compr_handle_irq(struct wm_adsp *dsp) +{ + struct wm_adsp_compr_buf *buf; + struct wm_adsp_compr *compr; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + if (list_empty(&dsp->buffer_list)) { + ret = -ENODEV; + goto out; + } + + adsp_dbg(dsp, "Handling buffer IRQ\n"); + + list_for_each_entry (buf, &dsp->buffer_list, list) { + compr = buf->compr; + + ret = wm_adsp_buffer_get_error(buf); + if (ret < 0) + goto out_notify; /* Wake poll to report error */ + + ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count), + &buf->irq_count); + if (ret < 0) { + compr_err(buf, "Failed to get irq_count: %d\n", ret); + goto out; + } + + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + compr_err(buf, "Error reading avail: %d\n", ret); + goto out; + } + + if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2) + ret = WM_ADSP_COMPR_VOICE_TRIGGER; + + out_notify: + if (compr && compr->stream) + snd_compr_fragment_elapsed(compr->stream); + } + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq); + +static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf) +{ + if (buf->irq_count & 0x01) + return 0; + + compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count); + + buf->irq_count |= 0x01; + + return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack), + buf->irq_count); +} + +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + struct wm_adsp_compr_buf *buf; + int ret = 0; + + compr_dbg(compr, "Pointer request\n"); + + mutex_lock(&dsp->pwr_lock); + + buf = compr->buf; + + if (dsp->fatal_error || !buf || buf->error) { + snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN); + ret = -EIO; + goto out; + } + + if (buf->avail < wm_adsp_compr_frag_words(compr)) { + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + compr_err(compr, "Error reading avail: %d\n", ret); + goto out; + } + + /* + * If we really have less than 1 fragment available tell the + * DSP to inform us once a whole fragment is available. + */ + if (buf->avail < wm_adsp_compr_frag_words(compr)) { + ret = wm_adsp_buffer_get_error(buf); + if (ret < 0) { + if (buf->error) + snd_compr_stop_error( + stream, SNDRV_PCM_STATE_XRUN); + goto out; + } + + ret = wm_adsp_buffer_reenable_irq(buf); + if (ret < 0) { + compr_err( + compr, + "Failed to re-enable buffer IRQ: %d\n", + ret); + goto out; + } + } + } + + tstamp->copied_total = compr->copied_total; + tstamp->copied_total += buf->avail * dsp->data_word_size; + tstamp->sampling_rate = compr->sample_rate; + +out: + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); + +static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) +{ + struct wm_adsp_compr_buf *buf = compr->buf; + unsigned int adsp_addr; + int mem_type, nwords, max_read; + int i, ret; + int data_word_size = buf->dsp->data_word_size; + + /* Calculate read parameters */ + for (i = 0; i < buf->num_regions; ++i) + if (buf->read_index < buf->regions[i].cumulative_size) + break; + + if (i == buf->num_regions) + return -EINVAL; + + mem_type = buf->regions[i].mem_type; + adsp_addr = buf->regions[i].base_addr + + (buf->read_index - buf->regions[i].offset); + + max_read = wm_adsp_compr_frag_words(compr); + nwords = buf->regions[i].cumulative_size - buf->read_index; + + if (nwords > target) + nwords = target; + if (nwords > buf->avail) + nwords = buf->avail; + if (nwords > max_read) + nwords = max_read; + if (!nwords) + return 0; + + /* Read data from DSP */ + ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr, nwords, + compr->raw_buf); + if (ret < 0) + return ret; + + wm_adsp_remove_padding(compr->raw_buf, nwords, data_word_size); + + /* update read index to account for words read */ + buf->read_index += nwords; + if (buf->read_index == wm_adsp_buffer_size(buf)) + buf->read_index = 0; + + ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index), + buf->read_index); + if (ret < 0) + return ret; + + /* update avail to account for words read */ + buf->avail -= nwords; + + return nwords; +} + +static int wm_adsp_compr_read(struct wm_adsp_compr *compr, char __user *buf, + size_t count) +{ + struct wm_adsp *dsp = compr->dsp; + int ntotal = 0; + int nwords, nbytes; + + compr_dbg(compr, "Requested read of %zu bytes\n", count); + + if (dsp->fatal_error || !compr->buf || compr->buf->error) { + snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN); + return -EIO; + } + + count /= dsp->data_word_size; + + do { + nwords = wm_adsp_buffer_capture_block(compr, count); + if (nwords < 0) { + compr_err(compr, "Failed to capture block: %d\n", + nwords); + return nwords; + } + + nbytes = nwords * dsp->data_word_size; + + compr_dbg(compr, "Read %d bytes\n", nbytes); + + if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) { + compr_err(compr, + "Failed to copy data to user: %d, %d\n", + ntotal, nbytes); + return -EFAULT; + } + + count -= nwords; + ntotal += nbytes; + } while (nwords > 0 && count > 0); + + compr->copied_total += ntotal; + + return ntotal; +} + +int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf, + size_t count) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int ret; + + mutex_lock(&dsp->pwr_lock); + + if (stream->direction == SND_COMPRESS_CAPTURE) + ret = wm_adsp_compr_read(compr, buf, count); + else + ret = -ENOTSUPP; + + mutex_unlock(&dsp->pwr_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_copy); + +static void wm_adsp_fatal_error(struct wm_adsp *dsp) +{ + struct wm_adsp_compr *compr; + + dsp->fatal_error = true; + + list_for_each_entry (compr, &dsp->compr_list, list) { + if (compr->stream) + snd_compr_fragment_elapsed(compr->stream); + } +} + +irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp) +{ + unsigned int val; + struct regmap *regmap = dsp->regmap; + int ret = 0; + + mutex_lock(&dsp->pwr_lock); + + ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); + if (ret) { + adsp_err(dsp, "Failed to read Region Lock Ctrl register: %d\n", + ret); + goto error; + } + + if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { + adsp_err(dsp, "watchdog timeout error\n"); + dsp->ops->stop_watchdog(dsp); + wm_adsp_fatal_error(dsp); + } + + if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { + if (val & ADSP2_SLAVE_ERR_MASK) + adsp_err(dsp, "bus error: slave error\n"); + else + adsp_err(dsp, "bus error: region lock error\n"); + + ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); + if (ret) { + adsp_err(dsp, + "Failed to read Bus Err Addr register: %d\n", + ret); + goto error; + } + + adsp_err(dsp, "bus error address = 0x%x\n", + val & ADSP2_BUS_ERR_ADDR_MASK); + + ret = regmap_read(regmap, + dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + &val); + if (ret) { + adsp_err( + dsp, + "Failed to read Pmem Xmem Err Addr register: %d\n", + ret); + goto error; + } + + adsp_err(dsp, "xmem error address = 0x%x\n", + val & ADSP2_XMEM_ERR_ADDR_MASK); + adsp_err(dsp, "pmem error address = 0x%x\n", + (val & ADSP2_PMEM_ERR_ADDR_MASK) >> + ADSP2_PMEM_ERR_ADDR_SHIFT); + } + + regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, + ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); + +error: + mutex_unlock(&dsp->pwr_lock); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_adsp2_bus_error); + +irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp) +{ + struct regmap *regmap = dsp->regmap; + unsigned int *fault; + struct reg_sequence clear[] = { + { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, + { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, + { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, + }; + int ret; + + fault = kcalloc(6, sizeof(*fault), GFP_KERNEL | GFP_DMA); + if (!fault) + return IRQ_NONE; + + mutex_lock(&dsp->pwr_lock); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, + fault); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", + *fault & HALO_AHBM_FLAGS_ERR_MASK, + (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >> + HALO_AHBM_CORE_ERR_ADDR_SHIFT); + + ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, + fault); + if (ret) { + adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); + + ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, fault, + 6); + if (ret) { + adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); + goto exit_unlock; + } + + adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); + adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); + adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); + + ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); + if (ret) + adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); + +exit_unlock: + mutex_unlock(&dsp->pwr_lock); + kfree(fault); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_halo_bus_error); + +irqreturn_t wm_halo_wdt_expire(int irq, void *data) +{ + struct wm_adsp *dsp = data; + + mutex_lock(&dsp->pwr_lock); + + adsp_warn(dsp, "WDT Expiry Fault\n"); + dsp->ops->stop_watchdog(dsp); + wm_adsp_fatal_error(dsp); + + mutex_unlock(&dsp->pwr_lock); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(wm_halo_wdt_expire); + +static struct wm_adsp_ops wm_adsp1_ops = { + .validate_version = wm_adsp_validate_version, + .parse_sizes = wm_adsp1_parse_sizes, + .region_to_reg = wm_adsp_region_to_reg, +}; + +static struct wm_adsp_ops wm_adsp2_ops[] = { + { + .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_adsp_validate_version, + .setup_algs = wm_adsp2_setup_algs, + .region_to_reg = wm_adsp_region_to_reg, + + .show_fw_status = wm_adsp2_show_fw_status, + + .enable_memory = wm_adsp2_enable_memory, + .disable_memory = wm_adsp2_disable_memory, + + .enable_core = wm_adsp2_enable_core, + .disable_core = wm_adsp2_disable_core, + + .start_core = wm_adsp2_start_core, + .stop_core = wm_adsp2_stop_core, + + }, + { + .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_adsp_validate_version, + .setup_algs = wm_adsp2_setup_algs, + .region_to_reg = wm_adsp_region_to_reg, + + .show_fw_status = wm_adsp2v2_show_fw_status, + + .enable_memory = wm_adsp2_enable_memory, + .disable_memory = wm_adsp2_disable_memory, + .lock_memory = wm_adsp2_lock, + + .enable_core = wm_adsp2v2_enable_core, + .disable_core = wm_adsp2v2_disable_core, + + .start_core = wm_adsp2_start_core, + .stop_core = wm_adsp2_stop_core, + }, + { + .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_adsp_validate_version, + .setup_algs = wm_adsp2_setup_algs, + .region_to_reg = wm_adsp_region_to_reg, + + .show_fw_status = wm_adsp2v2_show_fw_status, + .stop_watchdog = wm_adsp_stop_watchdog, + + .enable_memory = wm_adsp2_enable_memory, + .disable_memory = wm_adsp2_disable_memory, + .lock_memory = wm_adsp2_lock, + + .enable_core = wm_adsp2v2_enable_core, + .disable_core = wm_adsp2v2_disable_core, + + .start_core = wm_adsp2_start_core, + .stop_core = wm_adsp2_stop_core, + }, +}; + +static struct wm_adsp_ops wm_halo_ops = { + .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr), + .parse_sizes = wm_adsp2_parse_sizes, + .validate_version = wm_halo_validate_version, + .setup_algs = wm_halo_setup_algs, + .region_to_reg = wm_halo_region_to_reg, + + .show_fw_status = wm_halo_show_fw_status, + .stop_watchdog = wm_halo_stop_watchdog, + + .lock_memory = wm_halo_configure_mpu, + + .start_core = wm_halo_start_core, + .stop_core = wm_halo_stop_core, +}; + +static struct wm_adsp_ops wm_vpu_ops = { + .parse_sizes = wm_vpu_parse_sizes, + .validate_version = wm_halo_validate_version, + .setup_algs = wm_vpu_setup_algs, + .region_to_reg = wm_vpu_region_to_reg, +}; + +MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.h b/techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.h new file mode 100644 index 000000000000..74caf0ce9ef0 --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/wm_adsp.h @@ -0,0 +1,244 @@ +/* + * wm_adsp.h -- Wolfson ADSP support + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __WM_ADSP_H +#define __WM_ADSP_H + +#include +#include +#include + +#include "wmfw.h" + +/* Return values for wm_adsp_compr_handle_irq */ +#define WM_ADSP_COMPR_OK 0 +#define WM_ADSP_COMPR_VOICE_TRIGGER 1 + +#define WM_ADSP2_REGION_0 BIT(0) +#define WM_ADSP2_REGION_1 BIT(1) +#define WM_ADSP2_REGION_2 BIT(2) +#define WM_ADSP2_REGION_3 BIT(3) +#define WM_ADSP2_REGION_4 BIT(4) +#define WM_ADSP2_REGION_5 BIT(5) +#define WM_ADSP2_REGION_6 BIT(6) +#define WM_ADSP2_REGION_7 BIT(7) +#define WM_ADSP2_REGION_8 BIT(8) +#define WM_ADSP2_REGION_9 BIT(9) +#define WM_ADSP2_REGION_1_9 \ + (WM_ADSP2_REGION_1 | WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \ + WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | WM_ADSP2_REGION_6 | \ + WM_ADSP2_REGION_7 | WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9) +#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9) + +struct wm_adsp_region { + int type; + unsigned int base; +}; + +struct wm_adsp_alg_region { + struct list_head list; + unsigned int alg; + int type; + unsigned int base; +}; + +struct wm_adsp_compr; +struct wm_adsp_compr_buf; +struct wm_adsp_ops; + +struct wm_adsp { + const char *part; + const char *name; + const char *fwf_name; + int rev; + int num; + int type; + struct device *dev; + struct regmap *regmap; + struct snd_soc_component *component; + + struct wm_adsp_ops *ops; + + unsigned int base; + unsigned int base_sysinfo; + unsigned int sysclk_reg; + unsigned int sysclk_mask; + unsigned int sysclk_shift; + + // Speaker calibration parameters + int cal_ambient; + int cal_r; + int cal_status; + int cal_checksum; + + struct list_head alg_regions; + + unsigned int fw_id; + unsigned int fw_id_version; + unsigned int fw_vendor_id; + + const struct wm_adsp_region *mem; + int num_mems; + + int fw; + int fw_ver; + + bool no_preloader; + bool preloaded; + bool booted; + bool running; + bool fatal_error; + bool tuning_has_prefix; + bool first_booting; + struct list_head ctl_list; + + struct workqueue_struct *work_queue; + struct work_struct boot_work; + + struct list_head compr_list; + struct list_head buffer_list; + + struct mutex pwr_lock; + + unsigned int lock_regions; + + unsigned int n_rx_channels; + unsigned int n_tx_channels; + + struct mutex *rate_lock; + u8 *rx_rate_cache; + u8 *tx_rate_cache; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; + char *wmfw_file_name; + char *bin_file_name; +#endif + unsigned int data_word_mask; + int data_word_size; +}; + +struct wm_adsp_ops { + unsigned int sys_config_size; + + bool (*validate_version)(struct wm_adsp *dsp, unsigned int version); + unsigned int (*parse_sizes)(struct wm_adsp *dsp, const char *const file, + unsigned int pos, + const struct firmware *firmware); + int (*setup_algs)(struct wm_adsp *dsp); + unsigned int (*region_to_reg)(struct wm_adsp_region const *mem, + unsigned int offset); + + void (*show_fw_status)(struct wm_adsp *dsp); + void (*stop_watchdog)(struct wm_adsp *dsp); + + int (*enable_memory)(struct wm_adsp *dsp); + void (*disable_memory)(struct wm_adsp *dsp); + int (*lock_memory)(struct wm_adsp *dsp, unsigned int lock_regions); + + int (*enable_core)(struct wm_adsp *dsp); + void (*disable_core)(struct wm_adsp *dsp); + + int (*start_core)(struct wm_adsp *dsp); + void (*stop_core)(struct wm_adsp *dsp); +}; + +#define WM_ADSP_PRELOADER(wname, num, event_fn) \ + { \ + .id = snd_soc_dapm_supply, .name = wname " Preloader", \ + .reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD, \ + .subseq = 100, /* Ensure we run after SYSCLK supply widget */ \ + } + +#define WM_ADSP1(wname, num) \ + SND_SOC_DAPM_PGA_E(wname, SND_SOC_NOPM, num, 0, NULL, 0, \ + wm_adsp1_event, \ + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD) + +#define WM_ADSP2_PRELOAD_SWITCH(wname, num) \ + SOC_SINGLE_EXT(wname " Preload Switch", SND_SOC_NOPM, num, 1, 0, \ + wm_adsp2_preloader_get, wm_adsp2_preloader_put) + +#define WM_ADSP2(wname, num, event_fn) \ + SND_SOC_DAPM_SPK(wname " Preload", NULL), \ + WM_ADSP_PRELOADER(wname, num, event_fn), \ + { \ + .id = snd_soc_dapm_out_drv, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp_event, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD \ + } + +#define WM_HALO(wname, num, event_fn) WM_ADSP2(wname, num, event_fn) + +#define WM_ADSP_FW_CONTROL(dspname, num) \ + SOC_ENUM_EXT(dspname " Firmware", wm_adsp_fw_enum[num], \ + wm_adsp_fw_get, wm_adsp_fw_put) + +extern const struct soc_enum wm_adsp_fw_enum[]; + +int wm_adsp1_init(struct wm_adsp *dsp); +int wm_adsp2_init(struct wm_adsp *dsp); +void wm_adsp2_remove(struct wm_adsp *dsp); +int wm_adsp2_component_probe(struct wm_adsp *dsp, + struct snd_soc_component *component); +int wm_adsp2_component_remove(struct wm_adsp *dsp, + struct snd_soc_component *component); +void wm_adsp_queue_boot_work(struct wm_adsp *dsp); +int wm_vpu_init(struct wm_adsp *vpu); +int wm_halo_init(struct wm_adsp *dsp, struct mutex *rate_lock); + +int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event); + +int wm_adsp_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +irqreturn_t wm_adsp2_bus_error(struct wm_adsp *adsp); +irqreturn_t wm_halo_bus_error(struct wm_adsp *dsp); +irqreturn_t wm_halo_wdt_expire(int irq, void *data); + +int wm_adsp_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event); +int wm_vpu_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, + int event); + +int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq); + +int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream); +int wm_adsp_compr_free(struct snd_compr_stream *stream); +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params); +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps); +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd); +int wm_adsp_compr_handle_irq(struct wm_adsp *dsp); +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp); +int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf, + size_t count); +int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, const void *buf, + size_t len); +int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, void *buf, + size_t len); +void wm_adsp_boot_work(struct work_struct *work); + +#endif diff --git a/techpack/audio/asoc/codecs/cs35l41_v2/wmfw.h b/techpack/audio/asoc/codecs/cs35l41_v2/wmfw.h new file mode 100644 index 000000000000..4134ba23adfa --- /dev/null +++ b/techpack/audio/asoc/codecs/cs35l41_v2/wmfw.h @@ -0,0 +1,223 @@ +/* + * wmfw.h - Wolfson firmware format information + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __WMFW_H +#define __WMFW_H + +#include + +#define WMFW_MAX_ALG_NAME 256 +#define WMFW_MAX_ALG_DESCR_NAME 256 + +#define WMFW_MAX_COEFF_NAME 256 +#define WMFW_MAX_COEFF_DESCR_NAME 256 + +#define WMFW_CTL_FLAG_SYS 0x8000 +#define WMFW_CTL_FLAG_VOLATILE 0x0004 +#define WMFW_CTL_FLAG_WRITEABLE 0x0002 +#define WMFW_CTL_FLAG_READABLE 0x0001 + +/* Non-ALSA coefficient types start at 0x1000 */ +#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */ +#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */ +#define WMFW_CTL_TYPE_HOST_BUFFER 0x1002 /* host buffer pointer */ + +struct wmfw_header { + char magic[4]; + __le32 len; + __le16 rev; + u8 core; + u8 ver; +} __packed; + +struct wmfw_footer { + __le64 timestamp; + __le32 checksum; +} __packed; + +struct wmfw_adsp1_sizes { + __le32 dm; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_adsp2_sizes { + __le32 xm; + __le32 ym; + __le32 pm; + __le32 zm; +} __packed; + +struct wmfw_vpu_sizes { + __le32 dm; +} __packed; + +struct wmfw_region { + union { + __be32 type; + __le32 offset; + }; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_id_hdr { + __be32 core_id; + __be32 core_rev; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_v3_id_hdr { + __be32 core_id; + __be32 block_rev; + __be32 vendor_id; + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 dm; + __be32 n_algs; +} __packed; + +struct wmfw_adsp2_id_hdr { + struct wmfw_id_hdr fw; + __be32 zm; + __be32 xm; + __be32 ym; + __be32 n_algs; +} __packed; + +struct wmfw_halo_id_hdr { + struct wmfw_v3_id_hdr fw; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; + __be32 n_algs; +} __packed; + +struct wmfw_vpu_id_hdr { + struct wmfw_v3_id_hdr fw; + __be32 dm_base; + __be32 dm_size; + __be32 n_algs; +} __packed; + +struct wmfw_alg_hdr { + __be32 id; + __be32 ver; +} __packed; + +struct wmfw_adsp1_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 dm; +} __packed; + +struct wmfw_adsp2_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 zm; + __be32 xm; + __be32 ym; +} __packed; + +struct wmfw_vpu_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 dm_base; + __be32 dm_size; +} __packed; + +struct wmfw_halo_alg_hdr { + struct wmfw_alg_hdr alg; + __be32 xm_base; + __be32 xm_size; + __be32 ym_base; + __be32 ym_size; +} __packed; + +struct wmfw_adsp_alg_data { + __le32 id; + u8 name[WMFW_MAX_ALG_NAME]; + u8 descr[WMFW_MAX_ALG_DESCR_NAME]; + __le32 ncoeff; + u8 data[]; +} __packed; + +struct wmfw_adsp_coeff_data { + struct { + __le16 offset; + __le16 type; + __le32 size; + } hdr; + u8 name[WMFW_MAX_COEFF_NAME]; + u8 descr[WMFW_MAX_COEFF_DESCR_NAME]; + __le16 ctl_type; + __le16 flags; + __le32 len; + u8 data[]; +} __packed; + +struct wmfw_coeff_hdr { + u8 magic[4]; + __le32 len; + union { + __be32 rev; + __le32 ver; + }; + union { + __be32 core; + __le32 core_ver; + }; + u8 data[]; +} __packed; + +struct wmfw_coeff_item { + __le16 offset; + __le16 type; + __le32 id; + __le32 ver; + __le32 sr; + __le32 len; + u8 data[]; +} __packed; + +#define WMFW_ADSP1 1 +#define WMFW_ADSP2 2 +#define WMFW_HALO 4 +#define WMFW_VPU 0x45 + +#define WMFW_ABSOLUTE 0xf0 +#define WMFW_ALGORITHM_DATA 0xf2 +#define WMFW_METADATA 0xfc +#define WMFW_NAME_TEXT 0xfe +#define WMFW_INFO_TEXT 0xff + +#define WMFW_ADSP1_PM 2 +#define WMFW_ADSP1_DM 3 +#define WMFW_ADSP1_ZM 4 + +#define WMFW_ADSP2_PM 2 +#define WMFW_ADSP2_ZM 4 +#define WMFW_ADSP2_XM 5 +#define WMFW_ADSP2_YM 6 + +#define WMFW_HALO_PM_PACKED 0x10 +#define WMFW_HALO_XM_PACKED 0x11 +#define WMFW_HALO_YM_PACKED 0x12 + +#define WMFW_VPU_DM 0x30 + +#endif diff --git a/techpack/audio/asoc/codecs/tas2557/Android.mk b/techpack/audio/asoc/codecs/tas2557/Android.mk new file mode 100755 index 000000000000..279ede3ee009 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/Android.mk @@ -0,0 +1,55 @@ +# Android makefile for audio kernel modules + +# Assume no targets will be supported + +# Check if this driver needs be built for current target +ifeq ($(call is-board-platform,msmnile),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m +endif + +ifeq ($(call is-board-platform,$(MSMSTEPPE)),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m +endif + +AUDIO_CHIPSET := audio +# Build/Package only in case of supported target +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE)),true) + +LOCAL_PATH := $(call my-dir) + +# This makefile is only for DLKM +ifneq ($(findstring vendor,$(LOCAL_PATH)),) + +ifneq ($(findstring opensource,$(LOCAL_PATH)),) + #AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/vendor/qcom/opensource/audio-kernel + AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel +endif # opensource + +DLKM_DIR := $(TOP)/device/qcom/common/dlkm + +# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko +########################################################### +# This is set once per LOCAL_PATH, not per (kernel) module +KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR) + +# We are actually building audio.ko here, as per the +# requirement we are specifying _audio.ko as LOCAL_MODULE. +# This means we need to rename the module to _audio.ko +# after audio.ko is built. +KBUILD_OPTIONS += MODNAME=tas2557_dlkm +KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM) +KBUILD_OPTIONS += $(AUDIO_SELECT) + +########################################################### +include $(CLEAR_VARS) +LOCAL_MODULE := $(AUDIO_CHIPSET)_tas2557.ko +LOCAL_MODULE_KBUILD_NAME := tas2557_dlkm.ko +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +include $(DLKM_DIR)/AndroidKernelModule.mk +########################################################### +########################################################### + +endif # DLKM check +endif # supported target check diff --git a/techpack/audio/asoc/codecs/tas2557/Kbuild b/techpack/audio/asoc/codecs/tas2557/Kbuild new file mode 100755 index 000000000000..2215081edeb1 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/Kbuild @@ -0,0 +1,115 @@ +# We can build either as part of a standalone Kernel build or as +# an external module. Determine which mechanism is being used +ifeq ($(MODNAME),) + KERNEL_BUILD := 1 +else + KERNEL_BUILD := 0 +endif + + + +ifeq ($(KERNEL_BUILD), 1) + # These are configurable via Kconfig for kernel-based builds + # Need to explicitly configure for Android-based builds + AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/kernel/msm-4.14 + AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio +endif + +ifeq ($(KERNEL_BUILD), 0) + ifeq ($(CONFIG_ARCH_SM8150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + ifeq ($(CONFIG_ARCH_SM6150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + + ifeq ($(CONFIG_ARCH_SDMSHRIKE), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif +endif + +# As per target team, build is done as follows: +# Defconfig : build with default flags +# Slub : defconfig + CONFIG_SLUB_DEBUG := y + +# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y +# Perf : Using appropriate msmXXXX-perf_defconfig +# +# Shipment builds (user variants) should not have any debug feature +# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds +# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since +# there is no other way to identify defconfig builds, QTI internal +# representation of perf builds (identified using the string 'perf'), +# is used to identify if the build is a slub or defconfig one. This +# way no critical debug feature will be enabled for perf and shipment +# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT +# config. + +############ UAPI ############ +UAPI_DIR := uapi +UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR) + +############ COMMON ############ +COMMON_DIR := include +COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR) + +############ CS35L41 ############ + +# for CS35L41 Codec +ifdef CONFIG_SND_SOC_TAS2557 + TAS2557_OBJS += tas2557-core.o + TAS2557_OBJS += tas2557-misc.o + TAS2557_OBJS += tas2557-codec.o + TAS2557_OBJS += tas2557-regmap.o + TAS2557_OBJS += tiload.o +endif + +LINUX_INC += -Iinclude/linux + +INCS += $(COMMON_INC) \ + $(UAPI_INC) + +EXTRA_CFLAGS += $(INCS) + + +CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ + -DANI_LITTLE_BIT_ENDIAN \ + -DDOT11F_LITTLE_ENDIAN_HOST \ + -DANI_COMPILER_TYPE_GCC \ + -DANI_OS_TYPE_ANDROID=6 \ + -DPTT_SOCK_SVC_ENABLE \ + -Wall\ + -Werror\ + -D__linux__ + +KBUILD_CPPFLAGS += $(CDEFINES) + +# Currently, for versions of gcc which support it, the kernel Makefile +# is disabling the maybe-uninitialized warning. Re-enable it for the +# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it +# will override the kernel settings. +ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y) +EXTRA_CFLAGS += -Wmaybe-uninitialized +endif +#EXTRA_CFLAGS += -Wmissing-prototypes + +ifeq ($(call cc-option-yn, -Wheader-guard),y) +EXTRA_CFLAGS += -Wheader-guard +endif + +ifeq ($(KERNEL_BUILD), 0) +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers +endif + +# Module information used by KBuild framework +obj-$(CONFIG_SND_SOC_TAS2557) += tas2557_dlkm.o +tas2557_dlkm-y := $(TAS2557_OBJS) diff --git a/techpack/audio/asoc/codecs/tas2557/Kconfig b/techpack/audio/asoc/codecs/tas2557/Kconfig new file mode 100644 index 000000000000..ecac9592e4bb --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/Kconfig @@ -0,0 +1,23 @@ +config SND_SOC_TAS2557 + tristate "Texas Instruments TAS2557 Smart Amplifier" + help + Say Y here if you want to add support for the TAS2557 Smart Amplifier. + +if SND_SOC_TAS2557 + +config TAS2557_REGMAP + bool "Texas Instruments TAS2557 Regmap" + help + Say Y here if you want to add support for the TAS2557 Regmap. + +config TAS2557_CODEC + bool "Texas Instruments TAS2557 Codec" + help + Say Y here if you want to add support for the TAS2557 Codec. + +config TAS2557_MISC + bool "Texas Instruments TAS2557 Misc" + help + Say Y here if you want to add support for the TAS2557 Misc. + +endif diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-codec.c b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.c new file mode 100644 index 000000000000..03f964805ad0 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.c @@ -0,0 +1,673 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557-codec.c +** +** Description: +** ALSA SoC driver for Texas Instruments TAS2557 High Performance 4W Smart Amplifier +** +** ============================================================================= +*/ + +#ifdef CONFIG_TAS2557_CODEC + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tas2557-core.h" +#include "tas2557-codec.h" + +#define KCONTROL_CODEC + +static unsigned int tas2557_codec_read(struct snd_soc_codec *pCodec, + unsigned int nRegister) +{ + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + int ret = 0; + unsigned int Value = 0; + + mutex_lock(&pTAS2557->codec_lock); + + ret = pTAS2557->read(pTAS2557, nRegister, &Value); + if (ret < 0) + dev_err(pTAS2557->dev, "%s, %d, ERROR happen=%d\n", __func__, + __LINE__, ret); + else + ret = Value; + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static int tas2557_codec_write(struct snd_soc_codec *pCodec, + unsigned int nRegister, unsigned int nValue) +{ + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + int ret = 0; + + mutex_lock(&pTAS2557->codec_lock); + + ret = pTAS2557->write(pTAS2557, nRegister, nValue); + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static int tas2557_codec_suspend(struct snd_soc_codec *pCodec) +{ + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + int ret = 0; + + mutex_lock(&pTAS2557->codec_lock); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + pTAS2557->runtime_suspend(pTAS2557); + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static int tas2557_codec_resume(struct snd_soc_codec *pCodec) +{ + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + int ret = 0; + + mutex_lock(&pTAS2557->codec_lock); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + pTAS2557->runtime_resume(pTAS2557); + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static const struct snd_soc_dapm_widget tas2557_dapm_widgets[] = { + SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("ASI2", "ASI2 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("ASIM", "ASIM Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_OUT_DRV("ClassD", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("NDivider", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_OUTPUT("OUT") +}; + +static const struct snd_soc_dapm_route tas2557_audio_map[] = { + { "DAC", NULL, "ASI1" }, { "DAC", NULL, "ASI2" }, + { "DAC", NULL, "ASIM" }, { "ClassD", NULL, "DAC" }, + { "OUT", NULL, "ClassD" }, { "DAC", NULL, "PLL" }, + { "DAC", NULL, "NDivider" }, +}; + +static int tas2557_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + return 0; +} + +static void tas2557_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); +} + +static int tas2557_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = dai->codec; + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + mutex_lock(&pTAS2557->codec_lock); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + tas2557_enable(pTAS2557, !mute); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_set_dai_sysclk(struct snd_soc_dai *pDAI, int nClkID, + unsigned int nFreqency, int nDir) +{ + struct snd_soc_codec *pCodec = pDAI->codec; + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + + dev_dbg(pTAS2557->dev, "tas2557_set_dai_sysclk: freq = %u\n", + nFreqency); + + return 0; +} + +static int tas2557_hw_params(struct snd_pcm_substream *pSubstream, + struct snd_pcm_hw_params *pParams, + struct snd_soc_dai *pDAI) +{ + struct snd_soc_codec *pCodec = pDAI->codec; + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + + mutex_lock(&pTAS2557->codec_lock); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + /* do bit rate setting during platform data */ + /* tas2557_set_bit_rate(pTAS2557, channel_both, snd_pcm_format_width(params_format(pParams))); */ + tas2557_set_sampling_rate(pTAS2557, params_rate(pParams)); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_set_dai_fmt(struct snd_soc_dai *pDAI, unsigned int nFormat) +{ + struct snd_soc_codec *codec = pDAI->codec; + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + return 0; +} + +static int tas2557_prepare(struct snd_pcm_substream *pSubstream, + struct snd_soc_dai *pDAI) +{ + struct snd_soc_codec *codec = pDAI->codec; + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + return 0; +} + +static int tas2557_set_bias_level(struct snd_soc_codec *pCodec, + enum snd_soc_bias_level eLevel) +{ + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + + dev_dbg(pTAS2557->dev, "%s: %d\n", __func__, eLevel); + return 0; +} + +static int tas2557_codec_probe(struct snd_soc_codec *pCodec) +{ + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(pCodec); + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + return 0; +} + +static int tas2557_codec_remove(struct snd_soc_codec *pCodec) +{ + return 0; +} +static int tas2557_mute_ctrl_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + mutex_lock(&pTAS2557->codec_lock); + + pValue->value.integer.value[0] = pTAS2557->mbMute; + dev_dbg(pTAS2557->dev, "tas2557_mute_ctrl_get = %d\n", + pTAS2557->mbMute); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_mute_ctrl_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + int mbMute = pValue->value.integer.value[0]; + + mutex_lock(&pTAS2557->codec_lock); + + dev_dbg(pTAS2557->dev, "tas2557_mute_ctrl_put = %d\n", mbMute); + + tas2557_permanent_mute(pTAS2557, mbMute); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_power_ctrl_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + mutex_lock(&pTAS2557->codec_lock); + + pValue->value.integer.value[0] = pTAS2557->mbPowerUp; + dev_dbg(pTAS2557->dev, "tas2557_power_ctrl_get = %d\n", + pTAS2557->mbPowerUp); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_power_ctrl_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + int nPowerOn = pValue->value.integer.value[0]; + + mutex_lock(&pTAS2557->codec_lock); + + dev_dbg(pTAS2557->dev, "tas2557_power_ctrl_put = %d\n", nPowerOn); + tas2557_enable(pTAS2557, (nPowerOn != 0)); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int vendor_id_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = VENDOR_ID_NONE; + + if (pTAS2557->spk_id_gpio_p) + ucontrol->value.integer.value[0] = + spk_id_get(pTAS2557->spk_id_gpio_p); + + return 0; +} + +static int pa_version_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = 0; + + if (pTAS2557->mnPGID == TAS2557_PG_VERSION_1P0) + ucontrol->value.integer.value[0] = 1; + else if (pTAS2557->mnPGID == TAS2557_PG_VERSION_2P0) + ucontrol->value.integer.value[0] = 2; + else if (pTAS2557->mnPGID == TAS2557_PG_VERSION_2P1) + ucontrol->value.integer.value[0] = 3; + return 0; +} + +static int tas2557_fs_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + int nFS = 48000; + + mutex_lock(&pTAS2557->codec_lock); + + if (pTAS2557->mpFirmware->mnConfigurations) + nFS = pTAS2557->mpFirmware + ->mpConfigurations[pTAS2557->mnCurrentConfiguration] + .mnSamplingRate; + pValue->value.integer.value[0] = nFS; + dev_dbg(pTAS2557->dev, "tas2557_fs_get = %d\n", nFS); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_fs_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + int ret = 0; + int nFS = pValue->value.integer.value[0]; + + mutex_lock(&pTAS2557->codec_lock); + + dev_info(pTAS2557->dev, "tas2557_fs_put = %d\n", nFS); + ret = tas2557_set_sampling_rate(pTAS2557, nFS); + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static int tas2557_Cali_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + bool ret = 0; + int prm_r0 = 0; + + mutex_lock(&pTAS2557->codec_lock); + + ret = tas2557_get_Cali_prm_r0(pTAS2557, &prm_r0); + if (ret) + pValue->value.integer.value[0] = prm_r0; + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_program_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + mutex_lock(&pTAS2557->codec_lock); + + pValue->value.integer.value[0] = pTAS2557->mnCurrentProgram; + dev_dbg(pTAS2557->dev, "tas2557_program_get = %d\n", + pTAS2557->mnCurrentProgram); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_program_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + unsigned int nProgram = pValue->value.integer.value[0]; + int ret = 0, nConfiguration = -1; + + mutex_lock(&pTAS2557->codec_lock); + + if (nProgram == pTAS2557->mnCurrentProgram) + nConfiguration = pTAS2557->mnCurrentConfiguration; + ret = tas2557_set_program(pTAS2557, nProgram, nConfiguration); + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static int tas2557_configuration_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + mutex_lock(&pTAS2557->codec_lock); + + pValue->value.integer.value[0] = pTAS2557->mnCurrentConfiguration; + dev_dbg(pTAS2557->dev, "tas2557_configuration_get = %d\n", + pTAS2557->mnCurrentConfiguration); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_configuration_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + unsigned int nConfiguration = pValue->value.integer.value[0]; + int ret = 0; + + mutex_lock(&pTAS2557->codec_lock); + + dev_info(pTAS2557->dev, "%s = %d\n", __func__, nConfiguration); + ret = tas2557_set_config(pTAS2557, nConfiguration); + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static int tas2557_calibration_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + + mutex_lock(&pTAS2557->codec_lock); + + pValue->value.integer.value[0] = pTAS2557->mnCurrentCalibration; + dev_info(pTAS2557->dev, "tas2557_calibration_get = %d\n", + pTAS2557->mnCurrentCalibration); + + mutex_unlock(&pTAS2557->codec_lock); + return 0; +} + +static int tas2557_calibration_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#ifdef KCONTROL_CODEC + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); +#else + struct snd_soc_codec *codec = snd_kcontrol_chip(pKcontrol); +#endif + struct tas2557_priv *pTAS2557 = snd_soc_codec_get_drvdata(codec); + unsigned int nCalibration = pValue->value.integer.value[0]; + int ret = 0; + + mutex_lock(&pTAS2557->codec_lock); + + ret = tas2557_set_calibration(pTAS2557, nCalibration); + + mutex_unlock(&pTAS2557->codec_lock); + return ret; +} + +static const char *const vendor_id_text[] = { "None", "AAC", "SSI", "GOER", + "Unknown" }; +static const struct soc_enum vendor_id[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vendor_id_text), vendor_id_text), +}; + +static const char *const pa_version_text[] = { "Unknown", "tas2557_v1.0", + "tas2557_v2.0", "tas2557_v2.1" }; +static const struct soc_enum pa_version[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(pa_version_text), pa_version_text), +}; + +static const struct snd_kcontrol_new tas2557_snd_controls[] = { + SOC_SINGLE_EXT("PowerCtrl", SND_SOC_NOPM, 0, 0x0001, 0, + tas2557_power_ctrl_get, tas2557_power_ctrl_put), + SOC_SINGLE_EXT("Program", SND_SOC_NOPM, 0, 0x00FF, 0, + tas2557_program_get, tas2557_program_put), + SOC_SINGLE_EXT("Configuration", SND_SOC_NOPM, 0, 0x00FF, 0, + tas2557_configuration_get, tas2557_configuration_put), + SOC_SINGLE_EXT("FS", SND_SOC_NOPM, 8000, 48000, 0, tas2557_fs_get, + tas2557_fs_put), + SOC_SINGLE_EXT("Get Cali_Re", SND_SOC_NOPM, 0, 0x7f000000, 0, + tas2557_Cali_get, NULL), + SOC_SINGLE_EXT("Calibration", SND_SOC_NOPM, 0, 0x00FF, 0, + tas2557_calibration_get, tas2557_calibration_put), + SOC_ENUM_EXT("SPK ID", vendor_id, vendor_id_get, NULL), + SOC_ENUM_EXT("SmartPA Version", pa_version, pa_version_get, NULL), + SOC_SINGLE_EXT("SmartPA Mute", SND_SOC_NOPM, 0, 0x0001, 0, + tas2557_mute_ctrl_get, tas2557_mute_ctrl_put), + +}; + +static struct snd_soc_codec_driver soc_codec_driver_tas2557 = { + .probe = tas2557_codec_probe, + .remove = tas2557_codec_remove, + .read = tas2557_codec_read, + .write = tas2557_codec_write, + .suspend = tas2557_codec_suspend, + .resume = tas2557_codec_resume, + .set_bias_level = tas2557_set_bias_level, + .idle_bias_off = true, + .component_driver = { + .controls = tas2557_snd_controls, + .num_controls = ARRAY_SIZE(tas2557_snd_controls), + .dapm_widgets = tas2557_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(tas2557_dapm_widgets), + .dapm_routes = tas2557_audio_map, + .num_dapm_routes = ARRAY_SIZE(tas2557_audio_map), + }, +}; + +static struct snd_soc_dai_ops tas2557_dai_ops = { + .startup = tas2557_startup, + .shutdown = tas2557_shutdown, + .digital_mute = tas2557_mute, + .hw_params = tas2557_hw_params, + .prepare = tas2557_prepare, + .set_sysclk = tas2557_set_dai_sysclk, + .set_fmt = tas2557_set_dai_fmt, +}; + +#define TAS2557_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) +static struct snd_soc_dai_driver tas2557_dai_driver[] = { + { + .name = "tas2557 ASI1", + .id = 0, + .playback = { + .stream_name = "ASI1 Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = TAS2557_FORMATS, + }, + .ops = &tas2557_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "tas2557 ASI2", + .id = 1, + .playback = { + .stream_name = "ASI2 Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = TAS2557_FORMATS, + }, + .ops = &tas2557_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "tas2557 ASIM", + .id = 2, + .playback = { + .stream_name = "ASIM Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = TAS2557_FORMATS, + }, + .ops = &tas2557_dai_ops, + .symmetric_rates = 1, + }, +}; + +int tas2557_register_codec(struct tas2557_priv *pTAS2557) +{ + int nResult = 0; + + dev_info(pTAS2557->dev, "%s, enter\n", __func__); + nResult = + snd_soc_register_codec(pTAS2557->dev, &soc_codec_driver_tas2557, + tas2557_dai_driver, + ARRAY_SIZE(tas2557_dai_driver)); + return nResult; +} + +int tas2557_deregister_codec(struct tas2557_priv *pTAS2557) +{ + snd_soc_unregister_codec(pTAS2557->dev); + return 0; +} + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TAS2557 ALSA SOC Smart Amplifier driver"); +MODULE_LICENSE("GPL v2"); +#endif diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-codec.h b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.h new file mode 100755 index 000000000000..20babdde5025 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.h @@ -0,0 +1,31 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557-codec.h +** +** Description: +** header file for tas2557-codec.c +** +** ============================================================================= +*/ + +#ifndef _TAS2557_CODEC_H +#define _TAS2557_CODEC_H + +#include "tas2557.h" + +int tas2557_register_codec(struct tas2557_priv *pTAS2557); +int tas2557_deregister_codec(struct tas2557_priv *pTAS2557); + +#endif /* _TAS2557_CODEC_H */ diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-core.c b/techpack/audio/asoc/codecs/tas2557/tas2557-core.c new file mode 100644 index 000000000000..45f6e9b3264e --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-core.c @@ -0,0 +1,2397 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557-core.c +** +** Description: +** TAS2557 common functions for Android Linux +** +** ============================================================================= +*/ + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tas2557.h" +#include "tas2557-core.h" + +#define PPC_DRIVER_CRCCHK 0x00000200 +#define PPC_DRIVER_CONFDEV 0x00000300 +#define PPC_DRIVER_MTPLLSRC 0x00000400 +#define PPC_DRIVER_CFGDEV_NONCRC 0x00000101 + +#define TAS2557_CAL_NAME "/mnt/vendor/persist/audio/tas2557_cal.bin" +#define RESTART_MAX 3 + +static int tas2557_load_calibration(struct tas2557_priv *pTAS2557, + char *pFileName); +static int tas2557_load_data(struct tas2557_priv *pTAS2557, struct TData *pData, + unsigned int nType); +static void tas2557_clear_firmware(struct TFirmware *pFirmware); +static int tas2557_load_block(struct tas2557_priv *pTAS2557, + struct TBlock *pBlock); +static int tas2557_load_configuration(struct tas2557_priv *pTAS2557, + unsigned int nConfiguration, + bool bLoadSame); + +#define TAS2557_UDELAY 0xFFFFFFFE +#define TAS2557_MDELAY 0xFFFFFFFD + +#define TAS2557_BLOCK_PLL 0x00 +#define TAS2557_BLOCK_PGM_ALL 0x0d +#define TAS2557_BLOCK_PGM_DEV_A 0x01 +#define TAS2557_BLOCK_PGM_DEV_B 0x08 +#define TAS2557_BLOCK_CFG_COEFF_DEV_A 0x03 +#define TAS2557_BLOCK_CFG_COEFF_DEV_B 0x0a +#define TAS2557_BLOCK_CFG_PRE_DEV_A 0x04 +#define TAS2557_BLOCK_CFG_PRE_DEV_B 0x0b +#define TAS2557_BLOCK_CFG_POST 0x05 +#define TAS2557_BLOCK_CFG_POST_POWER 0x06 + +static unsigned int p_tas2557_default_data[] = { + TAS2557_SAR_ADC2_REG, + 0x05, /* enable SAR ADC */ + TAS2557_CLK_ERR_CTRL2, + 0x21, /*clk1:clock hysteresis, 0.34ms; clock halt, 22ms*/ + TAS2557_CLK_ERR_CTRL3, + 0x21, /*clk2: rampDown 15dB/us, clock hysteresis, 10.66us; clock halt, 22ms */ + TAS2557_SAFE_GUARD_REG, + TAS2557_SAFE_GUARD_PATTERN, /* safe guard */ + 0xFFFFFFFF, + 0xFFFFFFFF +}; + +static unsigned int p_tas2557_irq_config[] = { + TAS2557_CLK_HALT_REG, + 0x71, /* enable clk halt detect2 interrupt */ + TAS2557_INT_GEN1_REG, + 0x11, /* enable spk OC and OV */ + TAS2557_INT_GEN2_REG, + 0x11, /* enable clk err1 and die OT */ + TAS2557_INT_GEN3_REG, + 0x11, /* enable clk err2 and brownout */ + TAS2557_INT_GEN4_REG, + 0x01, /* disable SAR, enable clk halt */ + TAS2557_GPIO4_PIN_REG, + 0x07, /* set GPIO4 as int1, default */ + TAS2557_INT_MODE_REG, + 0x80, /* active high until INT_STICKY_1 and INT_STICKY_2 are read to be cleared. */ + 0xFFFFFFFF, + 0xFFFFFFFF +}; + +static unsigned int p_tas2557_startup_data[] = { + TAS2557_GPI_PIN_REG, + 0x15, /* enable DIN, MCLK, CCI */ + TAS2557_GPIO1_PIN_REG, + 0x01, /* enable BCLK */ + TAS2557_GPIO2_PIN_REG, + 0x01, /* enable WCLK */ + TAS2557_POWER_CTRL2_REG, + 0xA0, /* Class-D, Boost power up */ + TAS2557_POWER_CTRL2_REG, + 0xA3, /* Class-D, Boost, IV sense power up */ + TAS2557_POWER_CTRL1_REG, + 0xF8, /* PLL, DSP, clock dividers power up */ + TAS2557_UDELAY, + 2000, /* delay */ + TAS2557_CLK_ERR_CTRL, + 0x2b, /* enable clock error detection */ + 0xFFFFFFFF, + 0xFFFFFFFF +}; + +static unsigned int p_tas2557_unmute_data[] = { TAS2557_MUTE_REG, + 0x00, /* unmute */ + TAS2557_SOFT_MUTE_REG, + 0x00, /* soft unmute */ + 0xFFFFFFFF, + 0xFFFFFFFF }; + +static unsigned int p_tas2557_shutdown_data[] = { + TAS2557_CLK_ERR_CTRL, + 0x00, /* disable clock error detection */ + TAS2557_SOFT_MUTE_REG, + 0x01, /* soft mute */ + TAS2557_UDELAY, + 10000, /* delay 10ms */ + TAS2557_MUTE_REG, + 0x03, /* mute */ + TAS2557_POWER_CTRL1_REG, + 0x60, /* DSP power down */ + TAS2557_UDELAY, + 2000, /* delay 2ms */ + TAS2557_POWER_CTRL2_REG, + 0x00, /* Class-D, Boost power down */ + TAS2557_POWER_CTRL1_REG, + 0x00, /* all power down */ + TAS2557_GPIO1_PIN_REG, + 0x00, /* disable BCLK */ + TAS2557_GPIO2_PIN_REG, + 0x00, /* disable WCLK */ + TAS2557_GPI_PIN_REG, + 0x00, /* disable DIN, MCLK, CCI */ + 0xFFFFFFFF, + 0xFFFFFFFF +}; + +static int tas2557_dev_load_data(struct tas2557_priv *pTAS2557, + unsigned int *pData) +{ + int ret = 0; + unsigned int n = 0; + unsigned int nRegister; + unsigned int nData; + + do { + nRegister = pData[n * 2]; + nData = pData[n * 2 + 1]; + if (nRegister == TAS2557_UDELAY) + udelay(nData); + else if (nRegister != 0xFFFFFFFF) { + ret = pTAS2557->write(pTAS2557, nRegister, nData); + if (ret < 0) + break; + } + n++; + } while (nRegister != 0xFFFFFFFF); + return ret; +} + +int tas2557_configIRQ(struct tas2557_priv *pTAS2557) +{ + return tas2557_dev_load_data(pTAS2557, p_tas2557_irq_config); +} + +int tas2557_set_bit_rate(struct tas2557_priv *pTAS2557, unsigned int nBitRate) +{ + int ret = 0, n = -1; + + dev_dbg(pTAS2557->dev, "tas2557_set_bit_rate: nBitRate = %d\n", + nBitRate); + + switch (nBitRate) { + case 16: + n = 0; + break; + case 20: + n = 1; + break; + case 24: + n = 2; + break; + case 32: + n = 3; + break; + } + + if (n >= 0) + ret = pTAS2557->update_bits( + pTAS2557, TAS2557_ASI1_DAC_FORMAT_REG, 0x18, n << 3); + return ret; +} + +int tas2557_get_bit_rate(struct tas2557_priv *pTAS2557, unsigned char *pBitRate) +{ + int ret = 0; + unsigned int nValue = 0; + unsigned char bitRate; + + ret = pTAS2557->read(pTAS2557, TAS2557_ASI1_DAC_FORMAT_REG, &nValue); + if (ret >= 0) { + bitRate = (nValue & 0x18) >> 3; + if (bitRate == 0) + bitRate = 16; + else if (bitRate == 1) + bitRate = 20; + else if (bitRate == 2) + bitRate = 24; + else if (bitRate == 3) + bitRate = 32; + *pBitRate = bitRate; + } + + return ret; +} + +int tas2557_get_DAC_gain(struct tas2557_priv *pTAS2557, unsigned char *pnGain) +{ + int ret = 0; + unsigned int nValue = 0; + + ret = pTAS2557->read(pTAS2557, TAS2557_SPK_CTRL_REG, &nValue); + if (ret >= 0) + *pnGain = ((nValue & TAS2557_DAC_GAIN_MASK) >> + TAS2557_DAC_GAIN_SHIFT); + + return ret; +} + +int tas2557_set_DAC_gain(struct tas2557_priv *pTAS2557, unsigned int nGain) +{ + int ret = 0; + + ret = pTAS2557->update_bits(pTAS2557, TAS2557_SPK_CTRL_REG, + TAS2557_DAC_GAIN_MASK, + (nGain << TAS2557_DAC_GAIN_SHIFT)); + return ret; +} + +/* +* die temperature calculation: +* DieTemp = readout / 2^23 +*/ +int tas2557_get_die_temperature(struct tas2557_priv *pTAS2557, + int *pTemperature) +{ + int nResult = 0; + unsigned char nBuf[4]; + int temp; + + if (!pTAS2557->mpFirmware->mnConfigurations) { + dev_err(pTAS2557->dev, "%s, firmware not loaded\n", __func__); + goto end; + } + + if (!pTAS2557->mbPowerUp) { + dev_err(pTAS2557->dev, "%s, device not powered on\n", __func__); + goto end; + } + + nResult = pTAS2557->bulk_read(pTAS2557, TAS2557_DIE_TEMP_REG, nBuf, 4); + if (nResult >= 0) { + temp = ((int)nBuf[0] << 24) | ((int)nBuf[1] << 16) | + ((int)nBuf[2] << 8) | nBuf[3]; + *pTemperature = temp; + } + +end: + + return nResult; +} + +int tas2557_load_platdata(struct tas2557_priv *pTAS2557) +{ + int nResult = 0; + + if (gpio_is_valid(pTAS2557->mnGpioINT)) { + nResult = tas2557_configIRQ(pTAS2557); + if (nResult < 0) + goto end; + } + + nResult = tas2557_set_bit_rate(pTAS2557, pTAS2557->mnI2SBits); + +end: + + return nResult; +} + +int tas2557_load_default(struct tas2557_priv *pTAS2557) +{ + int nResult = 0; + + nResult = tas2557_dev_load_data(pTAS2557, p_tas2557_default_data); + if (nResult < 0) + goto end; + + nResult = tas2557_load_platdata(pTAS2557); + if (nResult < 0) + goto end; + + /* enable DOUT tri-state for extra BCLKs */ + nResult = pTAS2557->update_bits(pTAS2557, TAS2557_ASI1_DAC_FORMAT_REG, + 0x01, 0x01); +end: + + return nResult; +} + +static void failsafe(struct tas2557_priv *pTAS2557) +{ + dev_err(pTAS2557->dev, "%s\n", __func__); + pTAS2557->mnErrCode |= ERROR_FAILSAFE; + if (hrtimer_active(&pTAS2557->mtimer)) + hrtimer_cancel(&pTAS2557->mtimer); + if (pTAS2557->mnRestart < RESTART_MAX) { + pTAS2557->mnRestart++; + msleep(100); + dev_err(pTAS2557->dev, "I2C COMM error, restart SmartAmp.\n"); + schedule_delayed_work(&pTAS2557->irq_work, + msecs_to_jiffies(100)); + return; + } + pTAS2557->enableIRQ(pTAS2557, false); + tas2557_dev_load_data(pTAS2557, p_tas2557_shutdown_data); + pTAS2557->mbPowerUp = false; + pTAS2557->hw_reset(pTAS2557); + pTAS2557->write(pTAS2557, TAS2557_SW_RESET_REG, 0x01); + udelay(1000); + pTAS2557->write(pTAS2557, TAS2557_SPK_CTRL_REG, 0x04); + if (pTAS2557->mpFirmware != NULL) + tas2557_clear_firmware(pTAS2557->mpFirmware); +} + +int tas2557_checkPLL(struct tas2557_priv *pTAS2557) +{ + int nResult = 0; + /* +* TO DO +*/ + + return nResult; +} + +/* +* tas2557_load_coefficient +*/ +static int tas2557_load_coefficient(struct tas2557_priv *pTAS2557, + int nPrevConfig, int nNewConfig, + bool bPowerOn) +{ + int nResult = 0; + struct TPLL *pPLL; + struct TProgram *pProgram; + struct TConfiguration *pPrevConfiguration; + struct TConfiguration *pNewConfiguration; + bool bRestorePower = false; + + if (!pTAS2557->mpFirmware->mnConfigurations) { + dev_err(pTAS2557->dev, "%s, firmware not loaded\n", __func__); + goto end; + } + + if (nNewConfig >= pTAS2557->mpFirmware->mnConfigurations) { + dev_err(pTAS2557->dev, + "%s, invalid configuration New=%d, total=%d\n", + __func__, nNewConfig, + pTAS2557->mpFirmware->mnConfigurations); + goto end; + } + + if (nPrevConfig < 0) + pPrevConfiguration = NULL; + else if (nPrevConfig == nNewConfig) { + dev_dbg(pTAS2557->dev, "%s, config [%d] already loaded\n", + __func__, nNewConfig); + goto end; + } else + pPrevConfiguration = + &(pTAS2557->mpFirmware->mpConfigurations[nPrevConfig]); + + pNewConfiguration = + &(pTAS2557->mpFirmware->mpConfigurations[nNewConfig]); + pTAS2557->mnCurrentConfiguration = nNewConfig; + if (pPrevConfiguration) { + if (pPrevConfiguration->mnPLL == pNewConfiguration->mnPLL) { + dev_dbg(pTAS2557->dev, "%s, PLL same\n", __func__); + goto prog_coefficient; + } + } + + pProgram = + &(pTAS2557->mpFirmware->mpPrograms[pTAS2557->mnCurrentProgram]); + if (bPowerOn) { + dev_dbg(pTAS2557->dev, "%s, power down to load new PLL\n", + __func__); + if (hrtimer_active(&pTAS2557->mtimer)) + hrtimer_cancel(&pTAS2557->mtimer); + + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) + pTAS2557->enableIRQ(pTAS2557, false); + + nResult = tas2557_dev_load_data(pTAS2557, + p_tas2557_shutdown_data); + if (nResult < 0) + goto end; + bRestorePower = true; + } + + /* load PLL */ + pPLL = &(pTAS2557->mpFirmware->mpPLLs[pNewConfiguration->mnPLL]); + dev_dbg(pTAS2557->dev, "load PLL: %s block for Configuration %s\n", + pPLL->mpName, pNewConfiguration->mpName); + nResult = tas2557_load_block(pTAS2557, &(pPLL->mBlock)); + if (nResult < 0) + goto end; + pTAS2557->mnCurrentSampleRate = pNewConfiguration->mnSamplingRate; + + dev_dbg(pTAS2557->dev, "load configuration %s conefficient pre block\n", + pNewConfiguration->mpName); + nResult = tas2557_load_data(pTAS2557, &(pNewConfiguration->mData), + TAS2557_BLOCK_CFG_PRE_DEV_A); + if (nResult < 0) + goto end; + +prog_coefficient: + dev_dbg(pTAS2557->dev, "load new configuration: %s, coeff block data\n", + pNewConfiguration->mpName); + nResult = tas2557_load_data(pTAS2557, &(pNewConfiguration->mData), + TAS2557_BLOCK_CFG_COEFF_DEV_A); + if (nResult < 0) + goto end; + + if (pTAS2557->mpCalFirmware->mnCalibrations) { + nResult = tas2557_set_calibration( + pTAS2557, pTAS2557->mnCurrentCalibration); + if (nResult < 0) + goto end; + } + + if (bRestorePower) { + pTAS2557->clearIRQ(pTAS2557); + dev_dbg(pTAS2557->dev, "device powered up, load startup\n"); + nResult = + tas2557_dev_load_data(pTAS2557, p_tas2557_startup_data); + if (nResult < 0) + goto end; + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + nResult = tas2557_checkPLL(pTAS2557); + if (nResult < 0) { + nResult = tas2557_dev_load_data( + pTAS2557, p_tas2557_shutdown_data); + pTAS2557->mbPowerUp = false; + goto end; + } + } + dev_dbg(pTAS2557->dev, "device powered up, load unmute\n"); + nResult = + tas2557_dev_load_data(pTAS2557, p_tas2557_unmute_data); + if (nResult < 0) + goto end; + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + pTAS2557->enableIRQ(pTAS2557, true); + if (!hrtimer_active(&pTAS2557->mtimer)) { + pTAS2557->mnDieTvReadCounter = 0; + hrtimer_start( + &pTAS2557->mtimer, + ns_to_ktime( + (u64)LOW_TEMPERATURE_CHECK_PERIOD * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + } + } +end: + + pTAS2557->mnNewConfiguration = pTAS2557->mnCurrentConfiguration; + return nResult; +} + +int tas2557_permanent_mute(struct tas2557_priv *pTAS2557, bool bmute) +{ + int nResult = 0; + + nResult = tas2557_enable(pTAS2557, !bmute); + if (nResult) { + dev_dbg(pTAS2557->dev, "set mute = %d faild\n", bmute); + goto end; + } + + pTAS2557->mbMute = bmute; + + if (bmute) { //make sure codec is permanent mute + p_tas2557_unmute_data[1] = 0x03; + p_tas2557_unmute_data[3] = 0x01; + } else { + p_tas2557_unmute_data[1] = 0x00; + p_tas2557_unmute_data[3] = 0x00; + } + +end: + return nResult; +} +int tas2557_enable(struct tas2557_priv *pTAS2557, bool bEnable) +{ + int nResult = 0; + unsigned int nValue; + const char *pFWName; + struct TProgram *pProgram; + + dev_dbg(pTAS2557->dev, "Enable: %d\n", bEnable); + + if ((pTAS2557->mpFirmware->mnPrograms == 0) || + (pTAS2557->mpFirmware->mnConfigurations == 0)) { + dev_err(pTAS2557->dev, + "%s, firmware not loaded, try to load again\n", + __func__); + /*Load firmware*/ + if (pTAS2557->mnPGID == TAS2557_PG_VERSION_2P1) { + dev_info(pTAS2557->dev, "PG2.1 Silicon found\n"); + pFWName = TAS2557_AAC_FW_NAME; + } else if (pTAS2557->mnPGID == TAS2557_PG_VERSION_1P0) { + dev_info(pTAS2557->dev, "PG1.0 Silicon found\n"); + pFWName = TAS2557_PG1P0_FW_NAME; + } else { + nResult = -ENOTSUPP; + dev_info(pTAS2557->dev, "unsupport Silicon 0x%x\n", + pTAS2557->mnPGID); + goto end; + } + if (pTAS2557->mnSpkType == VENDOR_ID_GOER) + pFWName = TAS2557_GOER_FW_NAME; + else if (pTAS2557->mnSpkType == VENDOR_ID_AAC) + pFWName = TAS2557_AAC_FW_NAME; + else + pFWName = TAS2557_DEFAULT_FW_NAME; + + nResult = request_firmware_nowait(THIS_MODULE, 1, pFWName, + pTAS2557->dev, GFP_KERNEL, + pTAS2557, tas2557_fw_ready); + if (nResult < 0) + goto end; + dev_err(pTAS2557->dev, "%s, firmware is loaded\n", __func__); + } + + /* check safe guard*/ + nResult = pTAS2557->read(pTAS2557, TAS2557_SAFE_GUARD_REG, &nValue); + if (nResult < 0) + goto end; + if ((nValue & 0xff) != TAS2557_SAFE_GUARD_PATTERN) { + dev_err(pTAS2557->dev, "ERROR safe guard failure!\n"); + nResult = -EPIPE; + pTAS2557->mnErrCode = ERROR_SAFE_GUARD; + pTAS2557->mbPowerUp = true; + goto end; + } + + pProgram = + &(pTAS2557->mpFirmware->mpPrograms[pTAS2557->mnCurrentProgram]); + if (bEnable) { + if (!pTAS2557->mbPowerUp) { + if (!pTAS2557->mbCalibrationLoaded) { + if (tas2557_set_calibration(pTAS2557, 0xFF) < 0) + dev_err(pTAS2557->dev, + "calibration data load fail!\n"); + else + pTAS2557->mbCalibrationLoaded = true; + } + if (pTAS2557->mbLoadConfigurationPrePowerUp) { + dev_dbg(pTAS2557->dev, + "load coefficient before power\n"); + pTAS2557->mbLoadConfigurationPrePowerUp = false; + nResult = tas2557_load_coefficient( + pTAS2557, + pTAS2557->mnCurrentConfiguration, + pTAS2557->mnNewConfiguration, false); + if (nResult < 0) + goto end; + } + + pTAS2557->clearIRQ(pTAS2557); + /* power on device */ + dev_dbg(pTAS2557->dev, + "Enable: load startup sequence\n"); + nResult = tas2557_dev_load_data(pTAS2557, + p_tas2557_startup_data); + if (nResult < 0) + goto end; + + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + nResult = tas2557_checkPLL(pTAS2557); + if (nResult < 0) { + nResult = tas2557_dev_load_data( + pTAS2557, + p_tas2557_shutdown_data); + goto end; + } + } + dev_dbg(pTAS2557->dev, + "Enable: load unmute sequence\n"); + nResult = tas2557_dev_load_data(pTAS2557, + p_tas2557_unmute_data); + if (nResult < 0) + goto end; + + pTAS2557->mbPowerUp = true; + + nResult = + tas2557_get_die_temperature(pTAS2557, &nValue); + if ((nValue == 0x80000000) || (nResult < 0)) { + dev_err(pTAS2557->dev, + "%s, thermal sensor is wrong, mute output, mbPower: %d\n", + __func__, pTAS2557->mbPowerUp); + nResult = tas2557_dev_load_data( + pTAS2557, p_tas2557_shutdown_data); + pTAS2557->mbPowerUp = false; + goto end; + } + + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + /* turn on IRQ */ + pTAS2557->enableIRQ(pTAS2557, true); + if (!hrtimer_active(&pTAS2557->mtimer)) { + pTAS2557->mnDieTvReadCounter = 0; + hrtimer_start( + &pTAS2557->mtimer, + ns_to_ktime( + (u64)LOW_TEMPERATURE_CHECK_PERIOD * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + } + pTAS2557->mnRestart = 0; + } + } else { + if (pTAS2557->mbPowerUp) { + if (hrtimer_active(&pTAS2557->mtimer)) + hrtimer_cancel(&pTAS2557->mtimer); + + dev_dbg(pTAS2557->dev, + "Enable: load shutdown sequence\n"); + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + /* turn off IRQ */ + pTAS2557->enableIRQ(pTAS2557, false); + } + nResult = tas2557_dev_load_data( + pTAS2557, p_tas2557_shutdown_data); + if (nResult < 0) + goto end; + + pTAS2557->mbPowerUp = false; + pTAS2557->mnRestart = 0; + } + } + + nResult = 0; + +end: + if (nResult < 0) { + if (pTAS2557->mnErrCode & + (ERROR_DEVA_I2C_COMM | ERROR_PRAM_CRCCHK | + ERROR_YRAM_CRCCHK | ERROR_SAFE_GUARD)) + failsafe(pTAS2557); + } + + return nResult; +} + +int tas2557_set_sampling_rate(struct tas2557_priv *pTAS2557, + unsigned int nSamplingRate) +{ + int nResult = 0; + struct TConfiguration *pConfiguration; + unsigned int nConfiguration; + + dev_dbg(pTAS2557->dev, + "tas2557_setup_clocks: nSamplingRate = %d [Hz]\n", + nSamplingRate); + + if ((!pTAS2557->mpFirmware->mpPrograms) || + (!pTAS2557->mpFirmware->mpConfigurations)) { + dev_err(pTAS2557->dev, "Firmware not loaded\n"); + nResult = -EINVAL; + goto end; + } + + pConfiguration = + &(pTAS2557->mpFirmware + ->mpConfigurations[pTAS2557->mnCurrentConfiguration]); + if (pConfiguration->mnSamplingRate == nSamplingRate) { + dev_info( + pTAS2557->dev, + "Sampling rate for current configuration matches: %d\n", + nSamplingRate); + nResult = 0; + goto end; + } + + for (nConfiguration = 0; + nConfiguration < pTAS2557->mpFirmware->mnConfigurations; + nConfiguration++) { + pConfiguration = &( + pTAS2557->mpFirmware->mpConfigurations[nConfiguration]); + if ((pConfiguration->mnSamplingRate == nSamplingRate) && + (pConfiguration->mnProgram == pTAS2557->mnCurrentProgram)) { + dev_info( + pTAS2557->dev, + "Found configuration: %s, with compatible sampling rate %d\n", + pConfiguration->mpName, nSamplingRate); + nResult = tas2557_load_configuration( + pTAS2557, nConfiguration, false); + goto end; + } + } + + dev_err(pTAS2557->dev, + "Cannot find a configuration that supports sampling rate: %d\n", + nSamplingRate); + +end: + + return nResult; +} + +static void fw_print_header(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware) +{ + dev_info(pTAS2557->dev, "FW Size = %d", pFirmware->mnFWSize); + dev_info(pTAS2557->dev, "Checksum = 0x%04X", + pFirmware->mnChecksum); + dev_info(pTAS2557->dev, "PPC Version = 0x%04X", + pFirmware->mnPPCVersion); + dev_info(pTAS2557->dev, "FW Version = 0x%04X", + pFirmware->mnFWVersion); + dev_info(pTAS2557->dev, "Driver Version= 0x%04X", + pFirmware->mnDriverVersion); + dev_info(pTAS2557->dev, "Timestamp = %d", pFirmware->mnTimeStamp); + dev_info(pTAS2557->dev, "DDC Name = %s", pFirmware->mpDDCName); + dev_info(pTAS2557->dev, "Description = %s", pFirmware->mpDescription); +} + +inline unsigned int fw_convert_number(unsigned char *pData) +{ + return pData[3] + (pData[2] << 8) + (pData[1] << 16) + (pData[0] << 24); +} + +static int fw_parse_header(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware, unsigned char *pData, + unsigned int nSize) +{ + unsigned char *pDataStart = pData; + unsigned int n; + unsigned char pMagicNumber[] = { 0x35, 0x35, 0x35, 0x32 }; + + if (nSize < 104) { + dev_err(pTAS2557->dev, "Firmware: Header too short"); + return -EINVAL; + } + + if (memcmp(pData, pMagicNumber, 4)) { + dev_err(pTAS2557->dev, "Firmware: Magic number doesn't match"); + return -EINVAL; + } + pData += 4; + + pFirmware->mnFWSize = fw_convert_number(pData); + pData += 4; + + pFirmware->mnChecksum = fw_convert_number(pData); + pData += 4; + + pFirmware->mnPPCVersion = fw_convert_number(pData); + pData += 4; + + pFirmware->mnFWVersion = fw_convert_number(pData); + pData += 4; + + pFirmware->mnDriverVersion = fw_convert_number(pData); + pData += 4; + + pFirmware->mnTimeStamp = fw_convert_number(pData); + pData += 4; + + memcpy(pFirmware->mpDDCName, pData, 64); + pData += 64; + + n = strlen(pData); + pFirmware->mpDescription = kmemdup(pData, n + 1, GFP_KERNEL); + pData += n + 1; + if ((pData - pDataStart) >= nSize) { + dev_err(pTAS2557->dev, + "Firmware: Header too short after DDC description"); + return -EINVAL; + } + + pFirmware->mnDeviceFamily = fw_convert_number(pData); + pData += 4; + if (pFirmware->mnDeviceFamily != 0) { + dev_err(pTAS2557->dev, "deviceFamily %d, not TAS device", + pFirmware->mnDeviceFamily); + return -EINVAL; + } + + pFirmware->mnDevice = fw_convert_number(pData); + pData += 4; + + if (pFirmware->mnDevice != 2) { + dev_err(pTAS2557->dev, "device %d, not TAS2557 Dual Mono", + pFirmware->mnDevice); + return -EINVAL; + } + + fw_print_header(pTAS2557, pFirmware); + return pData - pDataStart; +} + +static int fw_parse_block_data(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware, + struct TBlock *pBlock, unsigned char *pData) +{ + unsigned char *pDataStart = pData; + unsigned int n; + + pBlock->mnType = fw_convert_number(pData); + pData += 4; + + if (pFirmware->mnDriverVersion >= PPC_DRIVER_CRCCHK) { + pBlock->mbPChkSumPresent = pData[0]; + pData++; + + pBlock->mnPChkSum = pData[0]; + pData++; + + pBlock->mbYChkSumPresent = pData[0]; + pData++; + + pBlock->mnYChkSum = pData[0]; + pData++; + } else { + pBlock->mbPChkSumPresent = 0; + pBlock->mbYChkSumPresent = 0; + } + + pBlock->mnCommands = fw_convert_number(pData); + pData += 4; + + n = pBlock->mnCommands * 4; + pBlock->mpData = kmemdup(pData, n, GFP_KERNEL); + pData += n; + return pData - pDataStart; +} + +static int fw_parse_data(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware, struct TData *pImageData, + unsigned char *pData) +{ + unsigned char *pDataStart = pData; + unsigned int nBlock; + unsigned int n; + + memcpy(pImageData->mpName, pData, 64); + pData += 64; + + n = strlen(pData); + pImageData->mpDescription = kmemdup(pData, n + 1, GFP_KERNEL); + pData += n + 1; + + pImageData->mnBlocks = (pData[0] << 8) + pData[1]; + pData += 2; + + pImageData->mpBlocks = kmalloc( + sizeof(struct TBlock) * pImageData->mnBlocks, GFP_KERNEL); + + for (nBlock = 0; nBlock < pImageData->mnBlocks; nBlock++) { + n = fw_parse_block_data(pTAS2557, pFirmware, + &(pImageData->mpBlocks[nBlock]), pData); + pData += n; + } + return pData - pDataStart; +} + +static int fw_parse_pll_data(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware, unsigned char *pData) +{ + unsigned char *pDataStart = pData; + unsigned int n; + unsigned int nPLL; + struct TPLL *pPLL; + + pFirmware->mnPLLs = (pData[0] << 8) + pData[1]; + pData += 2; + + if (pFirmware->mnPLLs == 0) + goto end; + + pFirmware->mpPLLs = kmalloc_array(pFirmware->mnPLLs, + sizeof(struct TPLL), GFP_KERNEL); + for (nPLL = 0; nPLL < pFirmware->mnPLLs; nPLL++) { + pPLL = &(pFirmware->mpPLLs[nPLL]); + + memcpy(pPLL->mpName, pData, 64); + pData += 64; + + n = strlen(pData); + pPLL->mpDescription = kmemdup(pData, n + 1, GFP_KERNEL); + pData += n + 1; + + n = fw_parse_block_data(pTAS2557, pFirmware, &(pPLL->mBlock), + pData); + pData += n; + } + +end: + return pData - pDataStart; +} + +static int fw_parse_program_data(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware, + unsigned char *pData) +{ + unsigned char *pDataStart = pData; + unsigned int n; + unsigned int nProgram; + struct TProgram *pProgram; + + pFirmware->mnPrograms = (pData[0] << 8) + pData[1]; + pData += 2; + + if (pFirmware->mnPrograms == 0) + goto end; + + pFirmware->mpPrograms = kmalloc( + sizeof(struct TProgram) * pFirmware->mnPrograms, GFP_KERNEL); + for (nProgram = 0; nProgram < pFirmware->mnPrograms; nProgram++) { + pProgram = &(pFirmware->mpPrograms[nProgram]); + memcpy(pProgram->mpName, pData, 64); + pData += 64; + + n = strlen(pData); + pProgram->mpDescription = kmemdup(pData, n + 1, GFP_KERNEL); + pData += n + 1; + + pProgram->mnAppMode = pData[0]; + pData++; + + pProgram->mnBoost = (pData[0] << 8) + pData[1]; + pData += 2; + + n = fw_parse_data(pTAS2557, pFirmware, &(pProgram->mData), + pData); + pData += n; + } + +end: + + return pData - pDataStart; +} + +static int fw_parse_configuration_data(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware, + unsigned char *pData) +{ + unsigned char *pDataStart = pData; + unsigned int n; + unsigned int nConfiguration; + struct TConfiguration *pConfiguration; + + pFirmware->mnConfigurations = (pData[0] << 8) + pData[1]; + pData += 2; + + if (pFirmware->mnConfigurations == 0) + goto end; + + pFirmware->mpConfigurations = kmalloc( + sizeof(struct TConfiguration) * pFirmware->mnConfigurations, + GFP_KERNEL); + for (nConfiguration = 0; nConfiguration < pFirmware->mnConfigurations; + nConfiguration++) { + pConfiguration = &(pFirmware->mpConfigurations[nConfiguration]); + memcpy(pConfiguration->mpName, pData, 64); + pData += 64; + + n = strlen(pData); + pConfiguration->mpDescription = + kmemdup(pData, n + 1, GFP_KERNEL); + pData += n + 1; + + if ((pFirmware->mnDriverVersion >= PPC_DRIVER_CONFDEV) || + ((pFirmware->mnDriverVersion >= PPC_DRIVER_CFGDEV_NONCRC) && + (pFirmware->mnDriverVersion < PPC_DRIVER_CRCCHK))) { + pConfiguration->mnDevices = (pData[0] << 8) + pData[1]; + pData += 2; + } else + pConfiguration->mnDevices = 1; + + pConfiguration->mnProgram = pData[0]; + pData++; + + pConfiguration->mnPLL = pData[0]; + pData++; + + pConfiguration->mnSamplingRate = fw_convert_number(pData); + pData += 4; + + if (pFirmware->mnDriverVersion >= PPC_DRIVER_MTPLLSRC) { + pConfiguration->mnPLLSrc = pData[0]; + pData++; + + pConfiguration->mnPLLSrcRate = fw_convert_number(pData); + pData += 4; + } + + n = fw_parse_data(pTAS2557, pFirmware, &(pConfiguration->mData), + pData); + pData += n; + } + +end: + + return pData - pDataStart; +} + +int fw_parse_calibration_data(struct tas2557_priv *pTAS2557, + struct TFirmware *pFirmware, unsigned char *pData) +{ + unsigned char *pDataStart = pData; + unsigned int n; + unsigned int nCalibration; + struct TCalibration *pCalibration; + + pFirmware->mnCalibrations = (pData[0] << 8) + pData[1]; + pData += 2; + + if (pFirmware->mnCalibrations == 0) + goto end; + + pFirmware->mpCalibrations = + kmalloc(sizeof(struct TCalibration) * pFirmware->mnCalibrations, + GFP_KERNEL); + for (nCalibration = 0; nCalibration < pFirmware->mnCalibrations; + nCalibration++) { + pCalibration = &(pFirmware->mpCalibrations[nCalibration]); + memcpy(pCalibration->mpName, pData, 64); + pData += 64; + + n = strlen(pData); + pCalibration->mpDescription = kmemdup(pData, n + 1, GFP_KERNEL); + pData += n + 1; + + pCalibration->mnProgram = pData[0]; + pData++; + + pCalibration->mnConfiguration = pData[0]; + pData++; + + n = fw_parse_data(pTAS2557, pFirmware, &(pCalibration->mData), + pData); + pData += n; + } + +end: + + return pData - pDataStart; +} + +static int fw_parse(struct tas2557_priv *pTAS2557, struct TFirmware *pFirmware, + unsigned char *pData, unsigned int nSize) +{ + int nPosition = 0; + + nPosition = fw_parse_header(pTAS2557, pFirmware, pData, nSize); + if (nPosition < 0) { + dev_err(pTAS2557->dev, "Firmware: Wrong Header"); + return -EINVAL; + } + + if (nPosition >= nSize) { + dev_err(pTAS2557->dev, "Firmware: Too short"); + return -EINVAL; + } + + pData += nPosition; + nSize -= nPosition; + nPosition = 0; + + nPosition = fw_parse_pll_data(pTAS2557, pFirmware, pData); + + pData += nPosition; + nSize -= nPosition; + nPosition = 0; + + nPosition = fw_parse_program_data(pTAS2557, pFirmware, pData); + + pData += nPosition; + nSize -= nPosition; + nPosition = 0; + + nPosition = fw_parse_configuration_data(pTAS2557, pFirmware, pData); + + pData += nPosition; + nSize -= nPosition; + nPosition = 0; + + if (nSize > 64) + nPosition = + fw_parse_calibration_data(pTAS2557, pFirmware, pData); + return 0; +} + +static const unsigned char crc8_lookup_table[CRC8_TABLE_SIZE] = { + 0x00, 0x4D, 0x9A, 0xD7, 0x79, 0x34, 0xE3, 0xAE, 0xF2, 0xBF, 0x68, 0x25, + 0x8B, 0xC6, 0x11, 0x5C, 0xA9, 0xE4, 0x33, 0x7E, 0xD0, 0x9D, 0x4A, 0x07, + 0x5B, 0x16, 0xC1, 0x8C, 0x22, 0x6F, 0xB8, 0xF5, 0x1F, 0x52, 0x85, 0xC8, + 0x66, 0x2B, 0xFC, 0xB1, 0xED, 0xA0, 0x77, 0x3A, 0x94, 0xD9, 0x0E, 0x43, + 0xB6, 0xFB, 0x2C, 0x61, 0xCF, 0x82, 0x55, 0x18, 0x44, 0x09, 0xDE, 0x93, + 0x3D, 0x70, 0xA7, 0xEA, 0x3E, 0x73, 0xA4, 0xE9, 0x47, 0x0A, 0xDD, 0x90, + 0xCC, 0x81, 0x56, 0x1B, 0xB5, 0xF8, 0x2F, 0x62, 0x97, 0xDA, 0x0D, 0x40, + 0xEE, 0xA3, 0x74, 0x39, 0x65, 0x28, 0xFF, 0xB2, 0x1C, 0x51, 0x86, 0xCB, + 0x21, 0x6C, 0xBB, 0xF6, 0x58, 0x15, 0xC2, 0x8F, 0xD3, 0x9E, 0x49, 0x04, + 0xAA, 0xE7, 0x30, 0x7D, 0x88, 0xC5, 0x12, 0x5F, 0xF1, 0xBC, 0x6B, 0x26, + 0x7A, 0x37, 0xE0, 0xAD, 0x03, 0x4E, 0x99, 0xD4, 0x7C, 0x31, 0xE6, 0xAB, + 0x05, 0x48, 0x9F, 0xD2, 0x8E, 0xC3, 0x14, 0x59, 0xF7, 0xBA, 0x6D, 0x20, + 0xD5, 0x98, 0x4F, 0x02, 0xAC, 0xE1, 0x36, 0x7B, 0x27, 0x6A, 0xBD, 0xF0, + 0x5E, 0x13, 0xC4, 0x89, 0x63, 0x2E, 0xF9, 0xB4, 0x1A, 0x57, 0x80, 0xCD, + 0x91, 0xDC, 0x0B, 0x46, 0xE8, 0xA5, 0x72, 0x3F, 0xCA, 0x87, 0x50, 0x1D, + 0xB3, 0xFE, 0x29, 0x64, 0x38, 0x75, 0xA2, 0xEF, 0x41, 0x0C, 0xDB, 0x96, + 0x42, 0x0F, 0xD8, 0x95, 0x3B, 0x76, 0xA1, 0xEC, 0xB0, 0xFD, 0x2A, 0x67, + 0xC9, 0x84, 0x53, 0x1E, 0xEB, 0xA6, 0x71, 0x3C, 0x92, 0xDF, 0x08, 0x45, + 0x19, 0x54, 0x83, 0xCE, 0x60, 0x2D, 0xFA, 0xB7, 0x5D, 0x10, 0xC7, 0x8A, + 0x24, 0x69, 0xBE, 0xF3, 0xAF, 0xE2, 0x35, 0x78, 0xD6, 0x9B, 0x4C, 0x01, + 0xF4, 0xB9, 0x6E, 0x23, 0x8D, 0xC0, 0x17, 0x5A, 0x06, 0x4B, 0x9C, 0xD1, + 0x7F, 0x32, 0xE5, 0xA8 +}; + +static int isInPageYRAM(struct tas2557_priv *pTAS2557, struct TYCRC *pCRCData, + unsigned char nBook, unsigned char nPage, + unsigned char nReg, unsigned char len) +{ + int nResult = 0; + + if (nBook == TAS2557_YRAM_BOOK1) { + if (nPage == TAS2557_YRAM1_PAGE) { + if (nReg >= TAS2557_YRAM1_START_REG) { + pCRCData->mnOffset = nReg; + pCRCData->mnLen = len; + nResult = 1; + } else if ((nReg + len) > TAS2557_YRAM1_START_REG) { + pCRCData->mnOffset = TAS2557_YRAM1_START_REG; + pCRCData->mnLen = + len - (TAS2557_YRAM1_START_REG - nReg); + nResult = 1; + } else + nResult = 0; + } else if (nPage == TAS2557_YRAM3_PAGE) { + if (nReg > TAS2557_YRAM3_END_REG) { + nResult = 0; + } else if (nReg >= TAS2557_YRAM3_START_REG) { + if ((nReg + len) > TAS2557_YRAM3_END_REG) { + pCRCData->mnOffset = nReg; + pCRCData->mnLen = + TAS2557_YRAM3_END_REG - nReg + + 1; + nResult = 1; + } else { + pCRCData->mnOffset = nReg; + pCRCData->mnLen = len; + nResult = 1; + } + } else { + if ((nReg + (len - 1)) < + TAS2557_YRAM3_START_REG) + nResult = 0; + else { + pCRCData->mnOffset = + TAS2557_YRAM3_START_REG; + pCRCData->mnLen = + len - (TAS2557_YRAM3_START_REG - + nReg); + nResult = 1; + } + } + } + } else if (nBook == TAS2557_YRAM_BOOK2) { + if (nPage == TAS2557_YRAM5_PAGE) { + if (nReg > TAS2557_YRAM5_END_REG) { + nResult = 0; + } else if (nReg >= TAS2557_YRAM5_START_REG) { + if ((nReg + len) > TAS2557_YRAM5_END_REG) { + pCRCData->mnOffset = nReg; + pCRCData->mnLen = + TAS2557_YRAM5_END_REG - nReg + + 1; + nResult = 1; + } else { + pCRCData->mnOffset = nReg; + pCRCData->mnLen = len; + nResult = 1; + } + } else { + if ((nReg + (len - 1)) < + TAS2557_YRAM5_START_REG) + nResult = 0; + else { + pCRCData->mnOffset = + TAS2557_YRAM5_START_REG; + pCRCData->mnLen = + len - (TAS2557_YRAM5_START_REG - + nReg); + nResult = 1; + } + } + } + } else + nResult = 0; + + return nResult; +} + +static int isInBlockYRAM(struct tas2557_priv *pTAS2557, struct TYCRC *pCRCData, + unsigned char nBook, unsigned char nPage, + unsigned char nReg, unsigned char len) +{ + int nResult; + + if (nBook == TAS2557_YRAM_BOOK1) { + if (nPage < TAS2557_YRAM2_START_PAGE) + nResult = 0; + else if (nPage <= TAS2557_YRAM2_END_PAGE) { + if (nReg > TAS2557_YRAM2_END_REG) + nResult = 0; + else if (nReg >= TAS2557_YRAM2_START_REG) { + pCRCData->mnOffset = nReg; + pCRCData->mnLen = len; + nResult = 1; + } else { + if ((nReg + (len - 1)) < + TAS2557_YRAM2_START_REG) + nResult = 0; + else { + pCRCData->mnOffset = + TAS2557_YRAM2_START_REG; + pCRCData->mnLen = + nReg + len - + TAS2557_YRAM2_START_REG; + nResult = 1; + } + } + } else + nResult = 0; + } else if (nBook == TAS2557_YRAM_BOOK2) { + if (nPage < TAS2557_YRAM4_START_PAGE) + nResult = 0; + else if (nPage <= TAS2557_YRAM4_END_PAGE) { + if (nReg > TAS2557_YRAM2_END_REG) + nResult = 0; + else if (nReg >= TAS2557_YRAM2_START_REG) { + pCRCData->mnOffset = nReg; + pCRCData->mnLen = len; + nResult = 1; + } else { + if ((nReg + (len - 1)) < + TAS2557_YRAM2_START_REG) + nResult = 0; + else { + pCRCData->mnOffset = + TAS2557_YRAM2_START_REG; + pCRCData->mnLen = + nReg + len - + TAS2557_YRAM2_START_REG; + nResult = 1; + } + } + } else + nResult = 0; + } else + nResult = 0; + + return nResult; +} + +static int isYRAM(struct tas2557_priv *pTAS2557, struct TYCRC *pCRCData, + unsigned char nBook, unsigned char nPage, unsigned char nReg, + unsigned char len) +{ + int nResult; + + nResult = isInPageYRAM(pTAS2557, pCRCData, nBook, nPage, nReg, len); + + if (nResult == 0) + nResult = isInBlockYRAM(pTAS2557, pCRCData, nBook, nPage, nReg, + len); + + return nResult; +} + +/* + * crc8 - calculate a crc8 over the given input data. + * + * table: crc table used for calculation. + * pdata: pointer to data buffer. + * nbytes: number of bytes in data buffer. + * crc: previous returned crc8 value. + */ +static u8 ti_crc8(const u8 table[CRC8_TABLE_SIZE], u8 *pdata, size_t nbytes, + u8 crc) +{ + /* loop over the buffer data */ + while (nbytes-- > 0) + crc = table[(crc ^ *pdata++) & 0xff]; + + return crc; +} + +static int doSingleRegCheckSum(struct tas2557_priv *pTAS2557, + unsigned char nBook, unsigned char nPage, + unsigned char nReg, unsigned char nValue) +{ + int nResult = 0; + struct TYCRC sCRCData; + unsigned int nData1 = 0; + + if ((nBook == TAS2557_BOOK_ID(TAS2557_SA_COEFF_SWAP_REG)) && + (nPage == TAS2557_PAGE_ID(TAS2557_SA_COEFF_SWAP_REG)) && + (nReg >= TAS2557_PAGE_REG(TAS2557_SA_COEFF_SWAP_REG)) && + (nReg <= (TAS2557_PAGE_REG(TAS2557_SA_COEFF_SWAP_REG) + 4))) { + /* DSP swap command, pass */ + nResult = 0; + goto end; + } + + nResult = isYRAM(pTAS2557, &sCRCData, nBook, nPage, nReg, 1); + if (nResult == 1) { + nResult = pTAS2557->read( + pTAS2557, TAS2557_REG(nBook, nPage, nReg), &nData1); + if (nResult < 0) + goto end; + + if (nData1 != nValue) { + dev_err(pTAS2557->dev, + "error2 (line %d),B[0x%x]P[0x%x]R[0x%x] W[0x%x], R[0x%x]\n", + __LINE__, nBook, nPage, nReg, nValue, nData1); + nResult = -EAGAIN; + goto end; + } + + nResult = ti_crc8(crc8_lookup_table, &nValue, 1, 0); + } + +end: + + return nResult; +} + +static int doMultiRegCheckSum(struct tas2557_priv *pTAS2557, + unsigned char nBook, unsigned char nPage, + unsigned char nReg, unsigned int len) +{ + int nResult = 0, i; + unsigned char nCRCChkSum = 0; + unsigned char nBuf1[128]; + struct TYCRC TCRCData; + + if ((nReg + len - 1) > 127) { + nResult = -EINVAL; + dev_err(pTAS2557->dev, "firmware error\n"); + goto end; + } + + if ((nBook == TAS2557_BOOK_ID(TAS2557_SA_COEFF_SWAP_REG)) && + (nPage == TAS2557_PAGE_ID(TAS2557_SA_COEFF_SWAP_REG)) && + (nReg == TAS2557_PAGE_REG(TAS2557_SA_COEFF_SWAP_REG)) && + (len == 4)) { + /* DSP swap command, pass */ + nResult = 0; + goto end; + } + + nResult = isYRAM(pTAS2557, &TCRCData, nBook, nPage, nReg, len); + if (nResult == 1) { + if (len == 1) { + dev_err(pTAS2557->dev, "firmware error\n"); + nResult = -EINVAL; + goto end; + } else { + nResult = pTAS2557->bulk_read( + pTAS2557, + TAS2557_REG(nBook, nPage, TCRCData.mnOffset), + nBuf1, TCRCData.mnLen); + if (nResult < 0) + goto end; + + for (i = 0; i < TCRCData.mnLen; i++) { + if ((nBook == + TAS2557_BOOK_ID( + TAS2557_SA_COEFF_SWAP_REG)) && + (nPage == + TAS2557_PAGE_ID( + TAS2557_SA_COEFF_SWAP_REG)) && + ((i + TCRCData.mnOffset) >= + TAS2557_PAGE_REG( + TAS2557_SA_COEFF_SWAP_REG)) && + ((i + TCRCData.mnOffset) <= + (TAS2557_PAGE_REG( + TAS2557_SA_COEFF_SWAP_REG) + + 4))) { + /* DSP swap command, bypass */ + continue; + } else + nCRCChkSum += ti_crc8(crc8_lookup_table, + &nBuf1[i], 1, 0); + } + + nResult = nCRCChkSum; + } + } + +end: + + return nResult; +} + +static int tas2557_load_block(struct tas2557_priv *pTAS2557, + struct TBlock *pBlock) +{ + int nResult = 0; + unsigned int nCommand = 0; + unsigned char nBook; + unsigned char nPage; + unsigned char nOffset; + unsigned char nData; + unsigned int nLength; + unsigned int nSleep; + unsigned char nCRCChkSum = 0; + unsigned int nValue1; + int nRetry = 6; + unsigned char *pData = pBlock->mpData; + + dev_dbg(pTAS2557->dev, "TAS2557 load block: Type = %d, commands = %d\n", + pBlock->mnType, pBlock->mnCommands); +start: + if (pBlock->mbPChkSumPresent) { + nResult = pTAS2557->write(pTAS2557, TAS2557_CRC_RESET_REG, 1); + if (nResult < 0) + goto end; + } + + if (pBlock->mbYChkSumPresent) + nCRCChkSum = 0; + + nCommand = 0; + + while (nCommand < pBlock->mnCommands) { + pData = pBlock->mpData + nCommand * 4; + + nBook = pData[0]; + nPage = pData[1]; + nOffset = pData[2]; + nData = pData[3]; + + nCommand++; + + if (nOffset <= 0x7F) { + nResult = pTAS2557->write( + pTAS2557, TAS2557_REG(nBook, nPage, nOffset), + nData); + if (nResult < 0) + goto end; + if (pBlock->mbYChkSumPresent) { + nResult = doSingleRegCheckSum( + pTAS2557, nBook, nPage, nOffset, nData); + if (nResult < 0) + goto check; + nCRCChkSum += (unsigned char)nResult; + } + } else if (nOffset == 0x81) { + nSleep = (nBook << 8) + nPage; + msleep(nSleep); + } else if (nOffset == 0x85) { + pData += 4; + nLength = (nBook << 8) + nPage; + nBook = pData[0]; + nPage = pData[1]; + nOffset = pData[2]; + if (nLength > 1) { + nResult = pTAS2557->bulk_write( + pTAS2557, + TAS2557_REG(nBook, nPage, nOffset), + pData + 3, nLength); + if (nResult < 0) + goto end; + if (pBlock->mbYChkSumPresent) { + nResult = doMultiRegCheckSum( + pTAS2557, nBook, nPage, nOffset, + nLength); + if (nResult < 0) + goto check; + nCRCChkSum += (unsigned char)nResult; + } + } else { + nResult = pTAS2557->write( + pTAS2557, + TAS2557_REG(nBook, nPage, nOffset), + pData[3]); + if (nResult < 0) + goto end; + if (pBlock->mbYChkSumPresent) { + nResult = doSingleRegCheckSum( + pTAS2557, nBook, nPage, nOffset, + pData[3]); + if (nResult < 0) + goto check; + nCRCChkSum += (unsigned char)nResult; + } + } + + nCommand++; + + if (nLength >= 2) + nCommand += ((nLength - 2) / 4) + 1; + } + } + if (pBlock->mbPChkSumPresent) { + nResult = pTAS2557->read(pTAS2557, TAS2557_CRC_CHECKSUM_REG, + &nValue1); + if (nResult < 0) + goto end; + if ((nValue1 & 0xff) != pBlock->mnPChkSum) { + dev_err(pTAS2557->dev, + "Block PChkSum Error: FW = 0x%x, Reg = 0x%x\n", + pBlock->mnPChkSum, (nValue1 & 0xff)); + nResult = -EAGAIN; + pTAS2557->mnErrCode |= ERROR_PRAM_CRCCHK; + goto check; + } + + nResult = 0; + pTAS2557->mnErrCode &= ~ERROR_PRAM_CRCCHK; + dev_dbg(pTAS2557->dev, "Block[0x%x] PChkSum match\n", + pBlock->mnType); + } + + if (pBlock->mbYChkSumPresent) { + if (nCRCChkSum != pBlock->mnYChkSum) { + dev_err(pTAS2557->dev, + "Block YChkSum Error: FW = 0x%x, YCRC = 0x%x\n", + pBlock->mnYChkSum, nCRCChkSum); + nResult = -EAGAIN; + pTAS2557->mnErrCode |= ERROR_YRAM_CRCCHK; + goto check; + } + pTAS2557->mnErrCode &= ~ERROR_YRAM_CRCCHK; + nResult = 0; + dev_dbg(pTAS2557->dev, "Block[0x%x] YChkSum match\n", + pBlock->mnType); + } + +check: + if (nResult == -EAGAIN) { + nRetry--; + if (nRetry > 0) + goto start; + } + +end: + if (nResult < 0) { + dev_err(pTAS2557->dev, "Block (%d) load error\n", + pBlock->mnType); + } + return nResult; +} + +static int tas2557_load_data(struct tas2557_priv *pTAS2557, struct TData *pData, + unsigned int nType) +{ + int nResult = 0; + unsigned int nBlock; + struct TBlock *pBlock; + + dev_dbg(pTAS2557->dev, + "TAS2557 load data: %s, Blocks = %d, Block Type = %d\n", + pData->mpName, pData->mnBlocks, nType); + + for (nBlock = 0; nBlock < pData->mnBlocks; nBlock++) { + pBlock = &(pData->mpBlocks[nBlock]); + if (pBlock->mnType == nType) { + nResult = tas2557_load_block(pTAS2557, pBlock); + if (nResult < 0) + break; + } + } + + return nResult; +} + +static int tas2557_load_configuration(struct tas2557_priv *pTAS2557, + unsigned int nConfiguration, + bool bLoadSame) +{ + int nResult = 0; + struct TConfiguration *pCurrentConfiguration = NULL; + struct TConfiguration *pNewConfiguration = NULL; + + dev_dbg(pTAS2557->dev, "%s: %d\n", __func__, nConfiguration); + + if ((!pTAS2557->mpFirmware->mpPrograms) || + (!pTAS2557->mpFirmware->mpConfigurations)) { + dev_err(pTAS2557->dev, "Firmware not loaded\n"); + nResult = 0; + goto end; + } + + if (nConfiguration >= pTAS2557->mpFirmware->mnConfigurations) { + dev_err(pTAS2557->dev, "Configuration %d doesn't exist\n", + nConfiguration); + nResult = 0; + goto end; + } + + if ((!pTAS2557->mbLoadConfigurationPrePowerUp) && + (nConfiguration == pTAS2557->mnCurrentConfiguration) && + (!bLoadSame)) { + dev_info(pTAS2557->dev, "Configuration %d is already loaded\n", + nConfiguration); + nResult = 0; + goto end; + } + + pCurrentConfiguration = + &(pTAS2557->mpFirmware + ->mpConfigurations[pTAS2557->mnCurrentConfiguration]); + pNewConfiguration = + &(pTAS2557->mpFirmware->mpConfigurations[nConfiguration]); + if (pNewConfiguration->mnProgram != pCurrentConfiguration->mnProgram) { + dev_err(pTAS2557->dev, + "Configuration %d, %s doesn't share the same program as current %d\n", + nConfiguration, pNewConfiguration->mpName, + pCurrentConfiguration->mnProgram); + nResult = 0; + goto end; + } + + if (pNewConfiguration->mnPLL >= pTAS2557->mpFirmware->mnPLLs) { + dev_err(pTAS2557->dev, + "Configuration %d, %s doesn't have a valid PLL index %d\n", + nConfiguration, pNewConfiguration->mpName, + pNewConfiguration->mnPLL); + nResult = 0; + goto end; + } + + if (pTAS2557->mbPowerUp) { + pTAS2557->mbLoadConfigurationPrePowerUp = false; + nResult = tas2557_load_coefficient( + pTAS2557, pTAS2557->mnCurrentConfiguration, + nConfiguration, true); + } else { + dev_dbg(pTAS2557->dev, + "TAS2557 was powered down, will load coefficient when power up\n"); + pTAS2557->mbLoadConfigurationPrePowerUp = true; + pTAS2557->mnNewConfiguration = nConfiguration; + } + +end: + + if (nResult < 0) { + if (pTAS2557->mnErrCode & + (ERROR_DEVA_I2C_COMM | ERROR_PRAM_CRCCHK | + ERROR_YRAM_CRCCHK)) + failsafe(pTAS2557); + } + + return nResult; +} + +int tas2557_set_config(struct tas2557_priv *pTAS2557, int config) +{ + struct TConfiguration *pConfiguration; + struct TProgram *pProgram; + unsigned int nProgram = pTAS2557->mnCurrentProgram; + unsigned int nConfiguration = config; + int nResult = 0; + + if ((!pTAS2557->mpFirmware->mpPrograms) || + (!pTAS2557->mpFirmware->mpConfigurations)) { + dev_err(pTAS2557->dev, "Firmware not loaded\n"); + nResult = -EINVAL; + goto end; + } + + if (nConfiguration >= pTAS2557->mpFirmware->mnConfigurations) { + dev_err(pTAS2557->dev, "Configuration %d doesn't exist\n", + nConfiguration); + nResult = -EINVAL; + goto end; + } + + pConfiguration = + &(pTAS2557->mpFirmware->mpConfigurations[nConfiguration]); + pProgram = &(pTAS2557->mpFirmware->mpPrograms[nProgram]); + + if (nProgram != pConfiguration->mnProgram) { + dev_err(pTAS2557->dev, + "Configuration %d, %s with Program %d isn't compatible with existing Program %d, %s\n", + nConfiguration, pConfiguration->mpName, + pConfiguration->mnProgram, nProgram, pProgram->mpName); + nResult = -EINVAL; + goto end; + } + + nResult = tas2557_load_configuration(pTAS2557, nConfiguration, false); + +end: + + return nResult; +} + +void tas2557_clear_firmware(struct TFirmware *pFirmware) +{ + unsigned int n, nn; + + if (!pFirmware) + return; + + kfree(pFirmware->mpDescription); + + if (pFirmware->mpPLLs != NULL) { + for (n = 0; n < pFirmware->mnPLLs; n++) { + kfree(pFirmware->mpPLLs[n].mpDescription); + kfree(pFirmware->mpPLLs[n].mBlock.mpData); + } + kfree(pFirmware->mpPLLs); + } + + if (pFirmware->mpPrograms != NULL) { + for (n = 0; n < pFirmware->mnPrograms; n++) { + kfree(pFirmware->mpPrograms[n].mpDescription); + kfree(pFirmware->mpPrograms[n].mData.mpDescription); + for (nn = 0; + nn < pFirmware->mpPrograms[n].mData.mnBlocks; nn++) + kfree(pFirmware->mpPrograms[n] + .mData.mpBlocks[nn] + .mpData); + kfree(pFirmware->mpPrograms[n].mData.mpBlocks); + } + kfree(pFirmware->mpPrograms); + } + + if (pFirmware->mpConfigurations != NULL) { + for (n = 0; n < pFirmware->mnConfigurations; n++) { + kfree(pFirmware->mpConfigurations[n].mpDescription); + kfree(pFirmware->mpConfigurations[n] + .mData.mpDescription); + for (nn = 0; + nn < pFirmware->mpConfigurations[n].mData.mnBlocks; + nn++) + kfree(pFirmware->mpConfigurations[n] + .mData.mpBlocks[nn] + .mpData); + kfree(pFirmware->mpConfigurations[n].mData.mpBlocks); + } + kfree(pFirmware->mpConfigurations); + } + + if (pFirmware->mpCalibrations != NULL) { + for (n = 0; n < pFirmware->mnCalibrations; n++) { + kfree(pFirmware->mpCalibrations[n].mpDescription); + kfree(pFirmware->mpCalibrations[n].mData.mpDescription); + for (nn = 0; + nn < pFirmware->mpCalibrations[n].mData.mnBlocks; + nn++) + kfree(pFirmware->mpCalibrations[n] + .mData.mpBlocks[nn] + .mpData); + kfree(pFirmware->mpCalibrations[n].mData.mpBlocks); + } + kfree(pFirmware->mpCalibrations); + } + + memset(pFirmware, 0x00, sizeof(struct TFirmware)); +} + +static int tas2557_load_calibration(struct tas2557_priv *pTAS2557, + char *pFileName) +{ + int nResult = 0; + struct file *nFile = NULL; + mm_segment_t fs; + unsigned char pBuffer[1000]; + int nSize = 0; + loff_t pos = 0; + + dev_dbg(pTAS2557->dev, "%s:\n", __func__); + fs = get_fs(); + set_fs(KERNEL_DS); + nFile = filp_open(pFileName, O_RDONLY, 0); + + dev_info(pTAS2557->dev, "TAS2557 calibration file = %s\n", pFileName); + if (IS_ERR(nFile)) { + if (PTR_ERR(nFile) == -ENOENT) + dev_err(pTAS2557->dev, + "TAS2557 calibration file %s is not exit\n", + pFileName); + else + dev_err(pTAS2557->dev, + "TAS2557 cannot open calibration file: %s errno:%d\n", + pFileName, (int)PTR_ERR(nFile)); + } else { + pos = nFile->f_pos; + nSize = vfs_read(nFile, pBuffer, 1000, &pos); + filp_close(nFile, NULL); + } + + set_fs(fs); + if (!nSize) + goto end; + + tas2557_clear_firmware(pTAS2557->mpCalFirmware); + dev_info(pTAS2557->dev, "TAS2557 calibration file size = %d\n", nSize); + nResult = fw_parse(pTAS2557, pTAS2557->mpCalFirmware, pBuffer, nSize); + + if (nResult) + dev_err(pTAS2557->dev, "TAS2557 calibration file is corrupt\n"); + else + dev_info(pTAS2557->dev, + "TAS2557 calibration: %d calibrations\n", + pTAS2557->mpCalFirmware->mnCalibrations); + +end: + return nResult; +} + +static bool tas2557_get_coefficient_in_block(struct tas2557_priv *pTAS2557, + struct TBlock *pBlock, int nReg, + int *pnValue) +{ + int nCoefficient = 0; + bool bFound = false; + unsigned char *pCommands; + int nBook, nPage, nOffset, len; + int i, n; + + pCommands = pBlock->mpData; + for (i = 0; i < pBlock->mnCommands;) { + nBook = pCommands[4 * i + 0]; + nPage = pCommands[4 * i + 1]; + nOffset = pCommands[4 * i + 2]; + if ((nOffset < 0x7f) || (nOffset == 0x81)) + i++; + else if (nOffset == 0x85) { + len = ((int)nBook << 8) | nPage; + nBook = pCommands[4 * i + 4]; + nPage = pCommands[4 * i + 5]; + nOffset = pCommands[4 * i + 6]; + n = 4 * i + 7; + i += 2; + i += ((len - 1) / 4); + if ((len - 1) % 4) + i++; + if ((nBook != TAS2557_BOOK_ID(nReg)) || + (nPage != TAS2557_PAGE_ID(nReg))) + continue; + if (nOffset > TAS2557_PAGE_REG(nReg)) + continue; + if ((len + nOffset) >= (TAS2557_PAGE_REG(nReg) + 4)) { + n += (TAS2557_PAGE_REG(nReg) - nOffset); + nCoefficient = ((int)pCommands[n] << 24) | + ((int)pCommands[n + 1] << 16) | + ((int)pCommands[n + 2] << 8) | + (int)pCommands[n + 3]; + bFound = true; + break; + } + } else { + dev_err(pTAS2557->dev, "%s, format error %d\n", + __func__, nOffset); + break; + } + } + + if (bFound) { + *pnValue = nCoefficient; + dev_dbg(pTAS2557->dev, "%s, B[0x%x]P[0x%x]R[0x%x]=0x%x\n", + __func__, TAS2557_BOOK_ID(nReg), TAS2557_PAGE_ID(nReg), + TAS2557_PAGE_REG(nReg), nCoefficient); + } + + return bFound; +} + +static bool tas2557_get_coefficient_in_data(struct tas2557_priv *pTAS2557, + struct TData *pData, int blockType, + int nReg, int *pnValue) +{ + bool bFound = false; + struct TBlock *pBlock; + int i; + + for (i = 0; i < pData->mnBlocks; i++) { + pBlock = &(pData->mpBlocks[i]); + if (pBlock->mnType == blockType) { + bFound = tas2557_get_coefficient_in_block( + pTAS2557, pBlock, nReg, pnValue); + if (bFound) + break; + } + } + + return bFound; +} + +static bool +tas2557_find_Tmax_in_configuration(struct tas2557_priv *pTAS2557, + struct TConfiguration *pConfiguration, + int *pnTMax) +{ + struct TData *pData; + bool bFound = false; + int nBlockType, nReg, nCoefficient; + + if (pTAS2557->mnPGID == TAS2557_PG_VERSION_2P1) + nReg = TAS2557_PG2P1_CALI_T_REG; + else + nReg = TAS2557_PG1P0_CALI_T_REG; + + nBlockType = TAS2557_BLOCK_CFG_COEFF_DEV_A; + + pData = &(pConfiguration->mData); + bFound = tas2557_get_coefficient_in_data(pTAS2557, pData, nBlockType, + nReg, &nCoefficient); + if (bFound) + *pnTMax = nCoefficient; + + return bFound; +} + +void tas2557_fw_ready(const struct firmware *pFW, void *pContext) +{ + struct tas2557_priv *pTAS2557 = (struct tas2557_priv *)pContext; + int nResult; + unsigned int nProgram = 0; + unsigned int nSampleRate = 0; + +#ifdef CONFIG_TAS2557_CODEC + mutex_lock(&pTAS2557->codec_lock); +#endif + +#ifdef CONFIG_TAS2557_MISC + mutex_lock(&pTAS2557->file_lock); +#endif + + dev_info(pTAS2557->dev, "%s:\n", __func__); + + if (unlikely(!pFW) || unlikely(!pFW->data)) { + dev_err(pTAS2557->dev, "firmware is not loaded.\n"); + goto end; + } + + if (pTAS2557->mpFirmware->mpConfigurations) { + nProgram = pTAS2557->mnCurrentProgram; + nSampleRate = pTAS2557->mnCurrentSampleRate; + dev_dbg(pTAS2557->dev, "clear current firmware\n"); + tas2557_clear_firmware(pTAS2557->mpFirmware); + } + + nResult = fw_parse(pTAS2557, pTAS2557->mpFirmware, + (unsigned char *)(pFW->data), pFW->size); + release_firmware(pFW); + if (nResult < 0) { + dev_err(pTAS2557->dev, "firmware is corrupt\n"); + goto end; + } + + if (!pTAS2557->mpFirmware->mnPrograms) { + dev_err(pTAS2557->dev, "firmware contains no programs\n"); + nResult = -EINVAL; + goto end; + } + + if (!pTAS2557->mpFirmware->mnConfigurations) { + dev_err(pTAS2557->dev, "firmware contains no configurations\n"); + nResult = -EINVAL; + goto end; + } + + if (nProgram >= pTAS2557->mpFirmware->mnPrograms) { + dev_info(pTAS2557->dev, + "no previous program, set to default\n"); + nProgram = 0; + } + + pTAS2557->mnCurrentSampleRate = nSampleRate; + nResult = tas2557_set_program(pTAS2557, nProgram, -1); + +end: + +#ifdef CONFIG_TAS2557_CODEC + mutex_unlock(&pTAS2557->codec_lock); +#endif + +#ifdef CONFIG_TAS2557_MISC + mutex_unlock(&pTAS2557->file_lock); +#endif +} + +int tas2557_set_program(struct tas2557_priv *pTAS2557, unsigned int nProgram, + int nConfig) +{ + struct TProgram *pProgram; + unsigned int nConfiguration = 0; + unsigned int nSampleRate = 0; + unsigned char nGain; + bool bFound = false; + int nResult = 0; + + if ((!pTAS2557->mpFirmware->mpPrograms) || + (!pTAS2557->mpFirmware->mpConfigurations)) { + dev_err(pTAS2557->dev, "Firmware not loaded\n"); + nResult = 0; + goto end; + } + + if (nProgram >= pTAS2557->mpFirmware->mnPrograms) { + dev_err(pTAS2557->dev, "TAS2557: Program %d doesn't exist\n", + nProgram); + nResult = 0; + goto end; + } + + if (nConfig < 0) { + nConfiguration = 0; + nSampleRate = pTAS2557->mnCurrentSampleRate; + while (!bFound && (nConfiguration < + pTAS2557->mpFirmware->mnConfigurations)) { + if (pTAS2557->mpFirmware + ->mpConfigurations[nConfiguration] + .mnProgram == nProgram) { + if (nSampleRate == 0) { + bFound = true; + dev_info( + pTAS2557->dev, + "find default configuration %d\n", + nConfiguration); + } else if (nSampleRate == + pTAS2557->mpFirmware + ->mpConfigurations + [nConfiguration] + .mnSamplingRate) { + bFound = true; + dev_info( + pTAS2557->dev, + "find matching configuration %d\n", + nConfiguration); + } else { + nConfiguration++; + } + } else { + nConfiguration++; + } + } + if (!bFound) { + dev_err(pTAS2557->dev, + "Program %d, no valid configuration found for sample rate %d, ignore\n", + nProgram, nSampleRate); + nResult = 0; + goto end; + } + } else { + if (pTAS2557->mpFirmware->mpConfigurations[nConfig].mnProgram != + nProgram) { + dev_err(pTAS2557->dev, + "%s, configuration program doesn't match\n", + __func__); + nResult = 0; + goto end; + } + nConfiguration = nConfig; + } + + pProgram = &(pTAS2557->mpFirmware->mpPrograms[nProgram]); + if (pTAS2557->mbPowerUp) { + dev_info( + pTAS2557->dev, + "device powered up, power down to load program %d (%s)\n", + nProgram, pProgram->mpName); + if (hrtimer_active(&pTAS2557->mtimer)) + hrtimer_cancel(&pTAS2557->mtimer); + + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) + pTAS2557->enableIRQ(pTAS2557, false); + + nResult = tas2557_dev_load_data(pTAS2557, + p_tas2557_shutdown_data); + if (nResult < 0) + goto end; + } + + pTAS2557->hw_reset(pTAS2557); + nResult = pTAS2557->write(pTAS2557, TAS2557_SW_RESET_REG, 0x01); + if (nResult < 0) + goto end; + msleep(1); + nResult = tas2557_load_default(pTAS2557); + if (nResult < 0) + goto end; + + dev_info(pTAS2557->dev, "load program %d (%s)\n", nProgram, + pProgram->mpName); + nResult = tas2557_load_data(pTAS2557, &(pProgram->mData), + TAS2557_BLOCK_PGM_DEV_A); + if (nResult < 0) + goto end; + pTAS2557->mnCurrentProgram = nProgram; + + nResult = tas2557_get_DAC_gain(pTAS2557, &nGain); + if (nResult < 0) + goto end; + pTAS2557->mnDevGain = nGain; + pTAS2557->mnDevCurrentGain = nGain; + + nResult = tas2557_load_coefficient(pTAS2557, -1, nConfiguration, false); + if (nResult < 0) + goto end; + + if (pTAS2557->mbPowerUp) { + pTAS2557->clearIRQ(pTAS2557); + dev_dbg(pTAS2557->dev, "device powered up, load startup\n"); + nResult = + tas2557_dev_load_data(pTAS2557, p_tas2557_startup_data); + if (nResult < 0) + goto end; + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + nResult = tas2557_checkPLL(pTAS2557); + if (nResult < 0) { + nResult = tas2557_dev_load_data( + pTAS2557, p_tas2557_shutdown_data); + pTAS2557->mbPowerUp = false; + goto end; + } + } + dev_dbg(pTAS2557->dev, "device powered up, load unmute\n"); + nResult = + tas2557_dev_load_data(pTAS2557, p_tas2557_unmute_data); + if (nResult < 0) + goto end; + + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + pTAS2557->enableIRQ(pTAS2557, true); + if (!hrtimer_active(&pTAS2557->mtimer)) { + pTAS2557->mnDieTvReadCounter = 0; + hrtimer_start( + &pTAS2557->mtimer, + ns_to_ktime( + (u64)LOW_TEMPERATURE_CHECK_PERIOD * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + } + } + +end: + + if (nResult < 0) { + if (pTAS2557->mnErrCode & + (ERROR_DEVA_I2C_COMM | ERROR_PRAM_CRCCHK | + ERROR_YRAM_CRCCHK)) + failsafe(pTAS2557); + } + return nResult; +} + +int tas2557_set_calibration(struct tas2557_priv *pTAS2557, int nCalibration) +{ + struct TCalibration *pCalibration = NULL; + struct TConfiguration *pConfiguration; + struct TProgram *pProgram; + int nTmax = 0; + bool bFound = false; + int nResult = 0; + + if ((!pTAS2557->mpFirmware->mpPrograms) || + (!pTAS2557->mpFirmware->mpConfigurations)) { + dev_err(pTAS2557->dev, "Firmware not loaded\n\r"); + nResult = 0; + goto end; + } + + if (nCalibration == 0x00FF) { + nResult = tas2557_load_calibration(pTAS2557, TAS2557_CAL_NAME); + if (nResult < 0) { + dev_info(pTAS2557->dev, + "load new calibration file %s fail %d\n", + TAS2557_CAL_NAME, nResult); + goto end; + } + nCalibration = 0; + } + + if (nCalibration >= pTAS2557->mpCalFirmware->mnCalibrations) { + dev_err(pTAS2557->dev, "Calibration %d doesn't exist\n", + nCalibration); + nResult = 0; + goto end; + } + + pTAS2557->mnCurrentCalibration = nCalibration; + if (pTAS2557->mbLoadConfigurationPrePowerUp) + goto end; + + pCalibration = &(pTAS2557->mpCalFirmware->mpCalibrations[nCalibration]); + pProgram = + &(pTAS2557->mpFirmware->mpPrograms[pTAS2557->mnCurrentProgram]); + pConfiguration = + &(pTAS2557->mpFirmware + ->mpConfigurations[pTAS2557->mnCurrentConfiguration]); + if (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE) { + if (pTAS2557->mbBypassTMax) { + bFound = tas2557_find_Tmax_in_configuration( + pTAS2557, pConfiguration, &nTmax); + if (bFound && (nTmax == TAS2557_COEFFICIENT_TMAX)) { + dev_dbg(pTAS2557->dev, + "%s, config[%s] bypass load calibration\n", + __func__, pConfiguration->mpName); + goto end; + } + } + + dev_dbg(pTAS2557->dev, "%s, load calibration\n", __func__); + nResult = tas2557_load_data(pTAS2557, &(pCalibration->mData), + TAS2557_BLOCK_CFG_COEFF_DEV_A); + if (nResult < 0) + goto end; + } + +end: + if (nResult < 0) { + tas2557_clear_firmware(pTAS2557->mpCalFirmware); + nResult = tas2557_set_program(pTAS2557, + pTAS2557->mnCurrentProgram, + pTAS2557->mnCurrentConfiguration); + } + + return nResult; +} + +bool tas2557_get_Cali_prm_r0(struct tas2557_priv *pTAS2557, int *prm_r0) +{ + struct TCalibration *pCalibration; + struct TData *pData; + int nReg; + int nCali_Re; + bool bFound = false; + int nBlockType; + + if (!pTAS2557->mpCalFirmware->mnCalibrations) { + dev_err(pTAS2557->dev, "%s, no calibration data\n", __func__); + goto end; + } + + if (pTAS2557->mnPGID == TAS2557_PG_VERSION_2P1) + nReg = TAS2557_PG2P1_CALI_R0_REG; + else + nReg = TAS2557_PG1P0_CALI_R0_REG; + + nBlockType = TAS2557_BLOCK_CFG_COEFF_DEV_A; + + pCalibration = + &(pTAS2557->mpCalFirmware + ->mpCalibrations[pTAS2557->mnCurrentCalibration]); + pData = &(pCalibration->mData); + + bFound = tas2557_get_coefficient_in_data(pTAS2557, pData, nBlockType, + nReg, &nCali_Re); + +end: + + if (bFound) + *prm_r0 = nCali_Re; + + return bFound; +} + +int spk_id_get(struct device_node *np) +{ + int id; + int state; + + state = spk_id_get_pin_3state(np); + if (state < 0) { + pr_err("%s: Can not get id pin state, %d\n", __func__, state); + return VENDOR_ID_NONE; + } + + switch (state) { + case PIN_PULL_DOWN: + id = VENDOR_ID_AAC; + break; + case PIN_PULL_UP: + id = VENDOR_ID_UNKNOWN; + break; + case PIN_FLOAT: + id = VENDOR_ID_GOER; + break; + default: + id = VENDOR_ID_UNKNOWN; + break; + } + return id; +} + +int tas2557_parse_dt(struct device *dev, struct tas2557_priv *pTAS2557) +{ + struct device_node *np = dev->of_node; + int rc = 0, ret = 0; + unsigned int value; + + pTAS2557->spk_id_gpio_p = of_parse_phandle(np, "ti,spk-id-pin", 0); + if (!pTAS2557->spk_id_gpio_p) { + dev_dbg(pTAS2557->dev, "property %s not detected in node %s", + "ti,spk-id-pin", np->full_name); + pTAS2557->mnSpkType = VENDOR_ID_NONE; + } else { + pTAS2557->mnSpkType = spk_id_get(pTAS2557->spk_id_gpio_p); + } + dev_dbg(pTAS2557->dev, "spk is is %d", pTAS2557->mnSpkType); + + pTAS2557->mnResetGPIO = of_get_named_gpio(np, "ti,cdc-reset-gpio", 0); + if (!gpio_is_valid(pTAS2557->mnResetGPIO)) { + dev_err(pTAS2557->dev, + "Looking up %s property in node %s failed %d\n", + "ti,cdc-reset-gpio", np->full_name, + pTAS2557->mnResetGPIO); + ret = -EINVAL; + goto end; + } else + dev_dbg(pTAS2557->dev, "ti,cdc-reset-gpio=%d\n", + pTAS2557->mnResetGPIO); + + pTAS2557->mnGpioINT = of_get_named_gpio(np, "ti,irq-gpio", 0); + if (!gpio_is_valid(pTAS2557->mnGpioINT)) + dev_err(pTAS2557->dev, + "Looking up %s property in node %s failed %d\n", + "ti,irq-gpio", np->full_name, pTAS2557->mnGpioINT); + + rc = of_property_read_u32(np, "ti,i2s-bits", &value); + if (rc) + dev_err(pTAS2557->dev, + "Looking up %s property in node %s failed %d\n", + "ti,i2s-bits", np->full_name, rc); + else + pTAS2557->mnI2SBits = value; + + rc = of_property_read_u32(np, "ti,bypass-tmax", &value); + if (rc) + dev_err(pTAS2557->dev, + "Looking up %s property in node %s failed %d\n", + "ti,bypass-tmax", np->full_name, rc); + else + pTAS2557->mbBypassTMax = (value > 0); + +end: + + return ret; +} + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TAS2557 common functions for Android Linux"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-core.h b/techpack/audio/asoc/codecs/tas2557/tas2557-core.h new file mode 100644 index 000000000000..95a544f45547 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-core.h @@ -0,0 +1,86 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557-core.h +** +** Description: +** header file for tas2557-core.c +** +** ============================================================================= +*/ + +#ifndef _TAS2557_CORE_H +#define _TAS2557_CORE_H + +#include "tas2557.h" + +#define TAS2557_YRAM_BOOK1 140 + +#define TAS2557_YRAM1_PAGE 42 +#define TAS2557_YRAM1_START_REG 88 +#define TAS2557_YRAM1_END_REG 127 + +#define TAS2557_YRAM2_START_PAGE 43 +#define TAS2557_YRAM2_END_PAGE 49 +#define TAS2557_YRAM2_START_REG 8 +#define TAS2557_YRAM2_END_REG 127 + +#define TAS2557_YRAM3_PAGE 50 +#define TAS2557_YRAM3_START_REG 8 +#define TAS2557_YRAM3_END_REG 27 + +/* should not include B0_P53_R44-R47 */ +#define TAS2557_YRAM_BOOK2 0 +#define TAS2557_YRAM4_START_PAGE 50 +#define TAS2557_YRAM4_END_PAGE 60 +#define TAS2557_YRAM4_START_REG 8 +#define TAS2557_YRAM4_END_REG 127 + +#define TAS2557_YRAM5_PAGE 61 +#define TAS2557_YRAM5_START_REG 8 +#define TAS2557_YRAM5_END_REG 27 + +#define TAS2557_COEFFICIENT_TMAX 0x7fffffff +#define TAS2557_SAFE_GUARD_PATTERN 0x5a +#define LOW_TEMPERATURE_CHECK_PERIOD 5000 /* 5 second */ + +struct TYCRC { + unsigned char mnOffset; + unsigned char mnLen; +}; + +int tas2557_enable(struct tas2557_priv *pTAS2557, bool bEnable); +int tas2557_permanent_mute(struct tas2557_priv *pTAS2557, bool bmute); +int tas2557_SA_DevChnSetup(struct tas2557_priv *pTAS2557, unsigned int mode); +int tas2557_get_die_temperature(struct tas2557_priv *pTAS2557, + int *pTemperature); +int tas2557_set_sampling_rate(struct tas2557_priv *pTAS2557, + unsigned int nSamplingRate); +int tas2557_set_bit_rate(struct tas2557_priv *pTAS2557, unsigned int nBitRate); +int tas2557_get_bit_rate(struct tas2557_priv *pTAS2557, + unsigned char *pBitRate); +int tas2557_set_config(struct tas2557_priv *pTAS2557, int config); +void tas2557_fw_ready(const struct firmware *pFW, void *pContext); +bool tas2557_get_Cali_prm_r0(struct tas2557_priv *pTAS2557, int *prm_r0); +int tas2557_set_program(struct tas2557_priv *pTAS2557, unsigned int nProgram, + int nConfig); +int tas2557_set_calibration(struct tas2557_priv *pTAS2557, int nCalibration); +int tas2557_load_default(struct tas2557_priv *pTAS2557); +int tas2557_parse_dt(struct device *dev, struct tas2557_priv *pTAS2557); +int tas2557_get_DAC_gain(struct tas2557_priv *pTAS2557, unsigned char *pnGain); +int tas2557_set_DAC_gain(struct tas2557_priv *pTAS2557, unsigned int nGain); +int tas2557_configIRQ(struct tas2557_priv *pTAS2557); +int spk_id_get(struct device_node *np); + +#endif /* _TAS2557_CORE_H */ diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-misc.c b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.c new file mode 100644 index 000000000000..5ef257de8ea0 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.c @@ -0,0 +1,702 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557-misc.c +** +** Description: +** misc driver for Texas Instruments TAS2557 High Performance 4W Smart Amplifier +** +** ============================================================================= +*/ + +#ifdef CONFIG_TAS2557_MISC + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tas2557.h" +#include "tas2557-core.h" +#include "tas2557-misc.h" + +static int g_logEnable = 1; +static struct tas2557_priv *g_tas2557; + +static int tas2557_file_open(struct inode *inode, struct file *file) +{ + struct tas2557_priv *pTAS2557 = g_tas2557; + + if (!try_module_get(THIS_MODULE)) + return -ENODEV; + + file->private_data = (void *)pTAS2557; + if (g_logEnable) + dev_info(pTAS2557->dev, "%s\n", __func__); + return 0; +} + +static int tas2557_file_release(struct inode *inode, struct file *file) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)file->private_data; + + if (g_logEnable) + dev_info(pTAS2557->dev, "%s\n", __func__); + file->private_data = (void *)NULL; + module_put(THIS_MODULE); + + return 0; +} + +static ssize_t tas2557_file_read(struct file *file, char *buf, size_t count, + loff_t *ppos) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)file->private_data; + int ret = 0; + unsigned int nValue = 0; + unsigned char value = 0; + unsigned char *p_kBuf = NULL; + + mutex_lock(&pTAS2557->file_lock); + + switch (pTAS2557->mnDBGCmd) { + case TIAUDIO_CMD_REG_READ: { + if (g_logEnable) + dev_info( + pTAS2557->dev, + "TIAUDIO_CMD_REG_READ: current_reg = 0x%x, count=%d\n", + pTAS2557->mnCurrentReg, (int)count); + if (count == 1) { + ret = pTAS2557->read(pTAS2557, pTAS2557->mnCurrentReg, + &nValue); + if (ret < 0) + break; + + value = (u8)nValue; + if (g_logEnable) + dev_info( + pTAS2557->dev, + "TIAUDIO_CMD_REG_READ: nValue=0x%x, value=0x%x\n", + nValue, value); + ret = copy_to_user(buf, &value, 1); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, "copy to user fail %d\n", + ret); + } + } else if (count > 1) { + p_kBuf = kzalloc(count, GFP_KERNEL); + if (p_kBuf != NULL) { + ret = pTAS2557->bulk_read( + pTAS2557, pTAS2557->mnCurrentReg, + p_kBuf, count); + if (ret < 0) + break; + ret = copy_to_user(buf, p_kBuf, count); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, + "copy to user fail %d\n", ret); + } + kfree(p_kBuf); + } else + dev_err(pTAS2557->dev, "read no mem\n"); + } + } break; + + case TIAUDIO_CMD_PROGRAM: { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_PROGRAM: count = %d\n", + (int)count); + + if (count == PROGRAM_BUF_SIZE) { + p_kBuf = kzalloc(count, GFP_KERNEL); + if (p_kBuf != NULL) { + struct TProgram *pProgram = &( + pTAS2557->mpFirmware->mpPrograms + [pTAS2557->mnCurrentProgram]); + p_kBuf[0] = + pTAS2557->mpFirmware->mnPrograms; + p_kBuf[1] = pTAS2557->mnCurrentProgram; + p_kBuf[2] = pProgram->mnAppMode; + p_kBuf[3] = + (pProgram->mnBoost & 0xff00) >> + 8; + p_kBuf[4] = + (pProgram->mnBoost & 0x00ff); + memcpy(&p_kBuf[5], pProgram->mpName, + FW_NAME_SIZE); + strlcpy(&p_kBuf[5 + FW_NAME_SIZE], + pProgram->mpDescription, + strlen(pProgram->mpDescription) + + 1); + ret = copy_to_user(buf, p_kBuf, count); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, + "copy to user fail %d\n", + ret); + } + kfree(p_kBuf); + } else + dev_err(pTAS2557->dev, "read no mem\n"); + } else + dev_err(pTAS2557->dev, + "read buffer not sufficient\n"); + } else + dev_err(pTAS2557->dev, "%s, firmware not loaded\n", + __func__); + } break; + + case TIAUDIO_CMD_CONFIGURATION: { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) { + if (g_logEnable) + dev_info( + pTAS2557->dev, + "TIAUDIO_CMD_CONFIGURATION: count = %d\n", + (int)count); + if (count == CONFIGURATION_BUF_SIZE) { + p_kBuf = kzalloc(count, GFP_KERNEL); + if (p_kBuf != NULL) { + struct TConfiguration *pConfiguration = &( + pTAS2557->mpFirmware->mpConfigurations + [pTAS2557->mnCurrentConfiguration]); + + p_kBuf[0] = pTAS2557->mpFirmware + ->mnConfigurations; + p_kBuf[1] = + pTAS2557->mnCurrentConfiguration; + memcpy(&p_kBuf[2], + pConfiguration->mpName, + FW_NAME_SIZE); + p_kBuf[2 + FW_NAME_SIZE] = + pConfiguration->mnProgram; + p_kBuf[3 + FW_NAME_SIZE] = + pConfiguration->mnPLL; + p_kBuf[4 + FW_NAME_SIZE] = + (pConfiguration->mnSamplingRate & + 0x000000ff); + p_kBuf[5 + FW_NAME_SIZE] = + ((pConfiguration->mnSamplingRate & + 0x0000ff00) >> + 8); + p_kBuf[6 + FW_NAME_SIZE] = + ((pConfiguration->mnSamplingRate & + 0x00ff0000) >> + 16); + p_kBuf[7 + FW_NAME_SIZE] = + ((pConfiguration->mnSamplingRate & + 0xff000000) >> + 24); + strlcpy(&p_kBuf[8 + FW_NAME_SIZE], + pConfiguration->mpDescription, + strlen(pConfiguration + ->mpDescription) + + 1); + ret = copy_to_user(buf, p_kBuf, count); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, + "copy to user fail %d\n", + ret); + } + kfree(p_kBuf); + } else + dev_err(pTAS2557->dev, "read no mem\n"); + } else + dev_err(pTAS2557->dev, + "read buffer not sufficient\n"); + } else + dev_err(pTAS2557->dev, "%s, firmware not loaded\n", + __func__); + } break; + + case TIAUDIO_CMD_FW_TIMESTAMP: { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_FW_TIMESTAMP: count = %d\n", + (int)count); + + if (count == 4) { + p_kBuf = kzalloc(count, GFP_KERNEL); + if (p_kBuf != NULL) { + p_kBuf[0] = (pTAS2557->mpFirmware->mnTimeStamp & + 0x000000ff); + p_kBuf[1] = + ((pTAS2557->mpFirmware->mnTimeStamp & + 0x0000ff00) >> + 8); + p_kBuf[2] = + ((pTAS2557->mpFirmware->mnTimeStamp & + 0x00ff0000) >> + 16); + p_kBuf[3] = + ((pTAS2557->mpFirmware->mnTimeStamp & + 0xff000000) >> + 24); + ret = copy_to_user(buf, p_kBuf, count); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, + "copy to user fail %d\n", ret); + } + kfree(p_kBuf); + } else + dev_err(pTAS2557->dev, "read no mem\n"); + } + } break; + + case TIAUDIO_CMD_CALIBRATION: { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_CALIBRATION: count = %d\n", + (int)count); + + if (count == 1) { + unsigned char curCal = pTAS2557->mnCurrentCalibration; + + ret = copy_to_user(buf, &curCal, 1); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, "copy to user fail %d\n", + ret); + } + } + } break; + + case TIAUDIO_CMD_SAMPLERATE: { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_SAMPLERATE: count = %d\n", + (int)count); + if (count == 4) { + p_kBuf = kzalloc(count, GFP_KERNEL); + if (p_kBuf != NULL) { + struct TConfiguration *pConfiguration = &( + pTAS2557->mpFirmware->mpConfigurations + [pTAS2557->mnCurrentConfiguration]); + + p_kBuf[0] = (pConfiguration->mnSamplingRate & + 0x000000ff); + p_kBuf[1] = ((pConfiguration->mnSamplingRate & + 0x0000ff00) >> + 8); + p_kBuf[2] = ((pConfiguration->mnSamplingRate & + 0x00ff0000) >> + 16); + p_kBuf[3] = ((pConfiguration->mnSamplingRate & + 0xff000000) >> + 24); + + ret = copy_to_user(buf, p_kBuf, count); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, + "copy to user fail %d\n", ret); + } + + kfree(p_kBuf); + } else + dev_err(pTAS2557->dev, "read no mem\n"); + } + } break; + + case TIAUDIO_CMD_BITRATE: { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_BITRATE: count = %d\n", + (int)count); + + if (count == 1) { + unsigned char bitRate = 0; + ret = tas2557_get_bit_rate(pTAS2557, &bitRate); + if (ret >= 0) { + ret = copy_to_user(buf, &bitRate, 1); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, + "copy to user fail %d\n", ret); + } + } + } + } break; + + case TIAUDIO_CMD_DACVOLUME: { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_DACVOLUME: count = %d\n", + (int)count); + + if (count == 1) { + unsigned char volume = 0; + + ret = tas2557_get_DAC_gain(pTAS2557, &volume); + if (ret >= 0) { + ret = copy_to_user(buf, &volume, 1); + if (ret != 0) { + /* Failed to copy all the data, exit */ + dev_err(pTAS2557->dev, + "copy to user fail %d\n", ret); + } + } + } + } break; + } + pTAS2557->mnDBGCmd = 0; + + mutex_unlock(&pTAS2557->file_lock); + return count; +} + +static ssize_t tas2557_file_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)file->private_data; + int ret = 0; + unsigned char *p_kBuf = NULL; + unsigned int reg = 0; + unsigned int len = 0; + + mutex_lock(&pTAS2557->file_lock); + + p_kBuf = kzalloc(count, GFP_KERNEL); + if (p_kBuf == NULL) { + dev_err(pTAS2557->dev, "write no mem\n"); + goto err; + } + + ret = copy_from_user(p_kBuf, buf, count); + if (ret != 0) { + dev_err(pTAS2557->dev, "copy_from_user failed.\n"); + goto err; + } + + pTAS2557->mnDBGCmd = p_kBuf[0]; + switch (pTAS2557->mnDBGCmd) { + case TIAUDIO_CMD_REG_WITE: + if (count > 5) { + reg = ((unsigned int)p_kBuf[1] << 24) + + ((unsigned int)p_kBuf[2] << 16) + + ((unsigned int)p_kBuf[3] << 8) + + (unsigned int)p_kBuf[4]; + len = count - 5; + if (len == 1) { + ret = pTAS2557->write(pTAS2557, reg, p_kBuf[5]); + if (g_logEnable) + dev_info( + pTAS2557->dev, + "TIAUDIO_CMD_REG_WITE, Reg=0x%x, Val=0x%x\n", + reg, p_kBuf[5]); + } else + ret = pTAS2557->bulk_write(pTAS2557, reg, + &p_kBuf[5], len); + } else + dev_err(pTAS2557->dev, + "%s, write len fail, count=%d.\n", __func__, + (int)count); + pTAS2557->mnDBGCmd = 0; + break; + + case TIAUDIO_CMD_REG_READ: + if (count == 5) { + pTAS2557->mnCurrentReg = + ((unsigned int)p_kBuf[1] << 24) + + ((unsigned int)p_kBuf[2] << 16) + + ((unsigned int)p_kBuf[3] << 8) + + (unsigned int)p_kBuf[4]; + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_REG_READ whole=0x%x\n", + pTAS2557->mnCurrentReg); + } else + dev_err(pTAS2557->dev, "read len fail.\n"); + break; + + case TIAUDIO_CMD_DEBUG_ON: + if (count == 2) + g_logEnable = p_kBuf[1]; + + pTAS2557->mnDBGCmd = 0; + break; + + case TIAUDIO_CMD_PROGRAM: { + if (count == 2) { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) { + int config = -1; + + if (p_kBuf[1] == pTAS2557->mnCurrentProgram) + config = + pTAS2557->mnCurrentConfiguration; + if (g_logEnable) + dev_info( + pTAS2557->dev, + "TIAUDIO_CMD_PROGRAM, set to %d, cfg=%d\n", + p_kBuf[1], config); + tas2557_set_program(pTAS2557, p_kBuf[1], + config); + pTAS2557->mnDBGCmd = 0; + } else + dev_err(pTAS2557->dev, + "%s, firmware not loaded\n", __func__); + } + } break; + + case TIAUDIO_CMD_CONFIGURATION: { + if (count == 2) { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) { + if (g_logEnable) + dev_info( + pTAS2557->dev, + "TIAUDIO_CMD_CONFIGURATION, set to %d\n", + p_kBuf[1]); + tas2557_set_config(pTAS2557, p_kBuf[1]); + pTAS2557->mnDBGCmd = 0; + } else + dev_err(pTAS2557->dev, + "%s, firmware not loaded\n", __func__); + } + } break; + + case TIAUDIO_CMD_FW_TIMESTAMP: + /*let go*/ + break; + + case TIAUDIO_CMD_CALIBRATION: { + if (count == 2) { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) { + if (g_logEnable) + dev_info( + pTAS2557->dev, + "TIAUDIO_CMD_CALIBRATION, set to %d\n", + p_kBuf[1]); + tas2557_set_calibration(pTAS2557, p_kBuf[1]); + pTAS2557->mnDBGCmd = 0; + } + } + } break; + + case TIAUDIO_CMD_SAMPLERATE: + if (count == 5) { + unsigned int nSampleRate = + ((unsigned int)p_kBuf[1] << 24) + + ((unsigned int)p_kBuf[2] << 16) + + ((unsigned int)p_kBuf[3] << 8) + + (unsigned int)p_kBuf[4]; + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_SAMPLERATE, set to %d\n", + nSampleRate); + + tas2557_set_sampling_rate(pTAS2557, nSampleRate); + } + break; + + case TIAUDIO_CMD_BITRATE: + if (count == 2) { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_BITRATE, set to %d\n", + p_kBuf[1]); + + tas2557_set_bit_rate(pTAS2557, p_kBuf[1]); + } + break; + + case TIAUDIO_CMD_DACVOLUME: + if (count == 2) { + unsigned char volume; + + volume = (p_kBuf[1] & 0x0f); + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_DACVOLUME, set to %d\n", + volume); + + tas2557_set_DAC_gain(pTAS2557, volume); + } + break; + + case TIAUDIO_CMD_SPEAKER: + if (count == 2) { + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_SPEAKER, set to %d\n", + p_kBuf[1]); + tas2557_enable(pTAS2557, (p_kBuf[1] > 0)); + } + break; + + case TIAUDIO_CMD_FW_RELOAD: + if (count == 1) { + const char *pFWName; + if (pTAS2557->mnPGID == TAS2557_PG_VERSION_2P1) + pFWName = TAS2557_AAC_FW_NAME; + else if (pTAS2557->mnPGID == TAS2557_PG_VERSION_1P0) + pFWName = TAS2557_PG1P0_FW_NAME; + else + break; + + if (pTAS2557->mnSpkType == VENDOR_ID_GOER) + pFWName = TAS2557_GOER_FW_NAME; + else if (pTAS2557->mnSpkType == VENDOR_ID_AAC) + pFWName = TAS2557_AAC_FW_NAME; + else if (pTAS2557->mnSpkType == VENDOR_ID_SSI) + pFWName = TAS2557_SSI_FW_NAME; + else + pFWName = TAS2557_DEFAULT_FW_NAME; + + ret = request_firmware_nowait(THIS_MODULE, 1, pFWName, + pTAS2557->dev, GFP_KERNEL, + pTAS2557, + tas2557_fw_ready); + + if (g_logEnable) + dev_info(pTAS2557->dev, + "TIAUDIO_CMD_FW_RELOAD: ret = %d\n", + ret); + } + break; + + default: + pTAS2557->mnDBGCmd = 0; + break; + } + +err: + if (p_kBuf != NULL) + kfree(p_kBuf); + + mutex_unlock(&pTAS2557->file_lock); + + return count; +} + +static long tas2557_file_unlocked_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct tas2557_priv *pTAS2557 = file->private_data; + int ret = 0; + + mutex_lock(&pTAS2557->file_lock); + + switch (cmd) { + case SMARTPA_SPK_DAC_VOLUME: { + } break; + + case SMARTPA_SPK_POWER_ON: { + tas2557_enable(pTAS2557, true); + } break; + + case SMARTPA_SPK_POWER_OFF: { + tas2557_enable(pTAS2557, false); + } break; + + case SMARTPA_SPK_SWITCH_PROGRAM: { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) + tas2557_set_program(pTAS2557, arg, -1); + } break; + + case SMARTPA_SPK_SWITCH_CONFIGURATION: { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) + tas2557_set_config(pTAS2557, arg); + } break; + + case SMARTPA_SPK_SWITCH_CALIBRATION: { + if ((pTAS2557->mpFirmware->mnConfigurations > 0) && + (pTAS2557->mpFirmware->mnPrograms > 0)) + tas2557_set_calibration(pTAS2557, arg); + } break; + + case SMARTPA_SPK_SET_SAMPLERATE: { + tas2557_set_sampling_rate(pTAS2557, arg); + } break; + + case SMARTPA_SPK_SET_BITRATE: { + tas2557_set_bit_rate(pTAS2557, arg); + } break; + } + + mutex_unlock(&pTAS2557->file_lock); + return ret; +} + +static const struct file_operations fops = { + .owner = THIS_MODULE, + .read = tas2557_file_read, + .write = tas2557_file_write, + .unlocked_ioctl = tas2557_file_unlocked_ioctl, + .open = tas2557_file_open, + .release = tas2557_file_release, +}; + +#define MODULE_NAME "tas2557" +static struct miscdevice tas2557_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = MODULE_NAME, + .fops = &fops, +}; + +int tas2557_register_misc(struct tas2557_priv *pTAS2557) +{ + int ret = 0; + + g_tas2557 = pTAS2557; + + ret = misc_register(&tas2557_misc); + if (ret) + dev_err(pTAS2557->dev, "TAS2557 misc fail: %d\n", ret); + + dev_info(pTAS2557->dev, "%s, leave\n", __func__); + + return ret; +} + +int tas2557_deregister_misc(struct tas2557_priv *pTAS2557) +{ + misc_deregister(&tas2557_misc); + return 0; +} + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TAS2557 Misc Smart Amplifier driver"); +MODULE_LICENSE("GPL v2"); +#endif diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-misc.h b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.h new file mode 100644 index 000000000000..c9336ccc66f6 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.h @@ -0,0 +1,60 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557-misc.h +** +** Description: +** header file for tas2557-misc.c +** +** ============================================================================= +*/ + +#ifndef _TAS2557_MISC_H +#define _TAS2557_MISC_H + +#define FW_NAME_SIZE 64 +#define FW_DESCRIPTION_SIZE 256 +#define PROGRAM_BUF_SIZE (5 + FW_NAME_SIZE + FW_DESCRIPTION_SIZE) +#define CONFIGURATION_BUF_SIZE (8 + FW_NAME_SIZE + FW_DESCRIPTION_SIZE) + +#define TIAUDIO_CMD_REG_WITE 1 +#define TIAUDIO_CMD_REG_READ 2 +#define TIAUDIO_CMD_DEBUG_ON 3 +#define TIAUDIO_CMD_PROGRAM 4 +#define TIAUDIO_CMD_CONFIGURATION 5 +#define TIAUDIO_CMD_FW_TIMESTAMP 6 +#define TIAUDIO_CMD_CALIBRATION 7 +#define TIAUDIO_CMD_SAMPLERATE 8 +#define TIAUDIO_CMD_BITRATE 9 +#define TIAUDIO_CMD_DACVOLUME 10 +#define TIAUDIO_CMD_SPEAKER 11 +#define TIAUDIO_CMD_FW_RELOAD 12 + +#define TAS2557_MAGIC_NUMBER 0x3235 /* '2557' */ + +#define SMARTPA_SPK_DAC_VOLUME _IOWR(TAS2557_MAGIC_NUMBER, 1, unsigned long) +#define SMARTPA_SPK_POWER_ON _IOWR(TAS2557_MAGIC_NUMBER, 2, unsigned long) +#define SMARTPA_SPK_POWER_OFF _IOWR(TAS2557_MAGIC_NUMBER, 3, unsigned long) +#define SMARTPA_SPK_SWITCH_PROGRAM _IOWR(TAS2557_MAGIC_NUMBER, 4, unsigned long) +#define SMARTPA_SPK_SWITCH_CONFIGURATION \ + _IOWR(TAS2557_MAGIC_NUMBER, 5, unsigned long) +#define SMARTPA_SPK_SWITCH_CALIBRATION \ + _IOWR(TAS2557_MAGIC_NUMBER, 6, unsigned long) +#define SMARTPA_SPK_SET_SAMPLERATE _IOWR(TAS2557_MAGIC_NUMBER, 7, unsigned long) +#define SMARTPA_SPK_SET_BITRATE _IOWR(TAS2557_MAGIC_NUMBER, 8, unsigned long) + +int tas2557_register_misc(struct tas2557_priv *pTAS2557); +int tas2557_deregister_misc(struct tas2557_priv *pTAS2557); + +#endif /* _TAS2557_MISC_H */ diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c b/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c new file mode 100644 index 000000000000..9923660efa97 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c @@ -0,0 +1,964 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557-regmap.c +** +** Description: +** I2C driver with regmap for Texas Instruments TAS2557 High Performance 4W Smart Amplifier +** +** ============================================================================= +*/ + +#ifdef CONFIG_TAS2557_REGMAP + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tas2557.h" +#include "tas2557-core.h" +#include +#include +#ifdef CONFIG_TAS2557_CODEC +#include "tas2557-codec.h" +#endif + +#ifdef CONFIG_TAS2557_MISC +#include "tas2557-misc.h" +#endif + +#define ENABLE_TILOAD +#ifdef ENABLE_TILOAD +#include "tiload.h" +#endif +#include "../spk-id.h" + +#define LOW_TEMPERATURE_GAIN 6 +#define LOW_TEMPERATURE_COUNTER 12 + +static int tas2557_change_book_page(struct tas2557_priv *pTAS2557, + unsigned char nBook, unsigned char nPage) +{ + int nResult = 0; + + if ((pTAS2557->mnCurrentBook == nBook) && + pTAS2557->mnCurrentPage == nPage) + goto end; + + if (pTAS2557->mnCurrentBook != nBook) { + nResult = regmap_write(pTAS2557->mpRegmap, TAS2557_BOOKCTL_PAGE, + 0); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + goto end; + } + pTAS2557->mnCurrentPage = 0; + nResult = regmap_write(pTAS2557->mpRegmap, TAS2557_BOOKCTL_REG, + nBook); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + goto end; + } + pTAS2557->mnCurrentBook = nBook; + if (nPage != 0) { + nResult = regmap_write(pTAS2557->mpRegmap, + TAS2557_BOOKCTL_PAGE, nPage); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + goto end; + } + pTAS2557->mnCurrentPage = nPage; + } + } else if (pTAS2557->mnCurrentPage != nPage) { + nResult = regmap_write(pTAS2557->mpRegmap, TAS2557_BOOKCTL_PAGE, + nPage); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + goto end; + } + pTAS2557->mnCurrentPage = nPage; + } + +end: + if (nResult < 0) + pTAS2557->mnErrCode |= ERROR_DEVA_I2C_COMM; + else + pTAS2557->mnErrCode &= ~ERROR_DEVA_I2C_COMM; + + return nResult; +} + +static int tas2557_dev_read(struct tas2557_priv *pTAS2557, + unsigned int nRegister, unsigned int *pValue) +{ + int nResult = 0; + unsigned int Value = 0; + + mutex_lock(&pTAS2557->dev_lock); + + if (pTAS2557->mbTILoadActive) { + if (!(nRegister & 0x80000000)) + goto end; /* let only reads from TILoad pass. */ + nRegister &= ~0x80000000; + + dev_dbg(pTAS2557->dev, "TiLoad R REG B[%d]P[%d]R[%d]\n", + TAS2557_BOOK_ID(nRegister), TAS2557_PAGE_ID(nRegister), + TAS2557_PAGE_REG(nRegister)); + } + + nResult = tas2557_change_book_page(pTAS2557, TAS2557_BOOK_ID(nRegister), + TAS2557_PAGE_ID(nRegister)); + if (nResult >= 0) { + nResult = regmap_read(pTAS2557->mpRegmap, + TAS2557_PAGE_REG(nRegister), &Value); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + pTAS2557->mnErrCode |= ERROR_DEVA_I2C_COMM; + goto end; + } else + pTAS2557->mnErrCode &= ~ERROR_DEVA_I2C_COMM; + *pValue = Value; + } + +end: + + mutex_unlock(&pTAS2557->dev_lock); + return nResult; +} + +static int tas2557_dev_write(struct tas2557_priv *pTAS2557, + unsigned int nRegister, unsigned int nValue) +{ + int nResult = 0; + + mutex_lock(&pTAS2557->dev_lock); + if ((nRegister == 0xAFFEAFFE) && (nValue == 0xBABEBABE)) { + pTAS2557->mbTILoadActive = true; + goto end; + } + + if ((nRegister == 0xBABEBABE) && (nValue == 0xAFFEAFFE)) { + pTAS2557->mbTILoadActive = false; + goto end; + } + + if (pTAS2557->mbTILoadActive) { + if (!(nRegister & 0x80000000)) + goto end; /* let only writes from TILoad pass. */ + nRegister &= ~0x80000000; + + dev_dbg(pTAS2557->dev, "TiLoad W REG B[%d]P[%d]R[%d] =0x%x\n", + TAS2557_BOOK_ID(nRegister), TAS2557_PAGE_ID(nRegister), + TAS2557_PAGE_REG(nRegister), nValue); + } + + nResult = tas2557_change_book_page(pTAS2557, TAS2557_BOOK_ID(nRegister), + TAS2557_PAGE_ID(nRegister)); + if (nResult >= 0) { + nResult = regmap_write(pTAS2557->mpRegmap, + TAS2557_PAGE_REG(nRegister), nValue); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + pTAS2557->mnErrCode |= ERROR_DEVA_I2C_COMM; + } else + pTAS2557->mnErrCode &= ~ERROR_DEVA_I2C_COMM; + } + +end: + + mutex_unlock(&pTAS2557->dev_lock); + + return nResult; +} + +static int tas2557_dev_bulk_read(struct tas2557_priv *pTAS2557, + unsigned int nRegister, u8 *pData, + unsigned int nLength) +{ + int nResult = 0; + int i; + + mutex_lock(&pTAS2557->dev_lock); + if (pTAS2557->mbTILoadActive) { + if (!(nRegister & 0x80000000)) + goto end; /* let only writes from TILoad pass. */ + + nRegister &= ~0x80000000; + dev_dbg(pTAS2557->dev, + "TiLoad BR REG B[%d]P[%d]R[%d], count=%d\n", + TAS2557_BOOK_ID(nRegister), TAS2557_PAGE_ID(nRegister), + TAS2557_PAGE_REG(nRegister), nLength); + } + + nResult = tas2557_change_book_page(pTAS2557, TAS2557_BOOK_ID(nRegister), + TAS2557_PAGE_ID(nRegister)); + if (nResult >= 0) { +#define STRIDE 4 + /* Read chunk bytes defined by STRIDE */ + for (i = 0; i < (nLength / STRIDE); i++) { + nResult = regmap_bulk_read( + pTAS2557->mpRegmap, + TAS2557_PAGE_REG((nRegister + i * STRIDE)), + &pData[i * STRIDE], STRIDE); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + pTAS2557->mnErrCode |= ERROR_DEVA_I2C_COMM; + } else { + pTAS2557->mnErrCode &= ~ERROR_DEVA_I2C_COMM; + } + } + + /* Read remaining bytes */ + if ((nLength % STRIDE) != 0) { + nResult = regmap_bulk_read( + pTAS2557->mpRegmap, + TAS2557_PAGE_REG(nRegister + i * STRIDE), + &pData[i * STRIDE], (nLength % STRIDE)); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + pTAS2557->mnErrCode |= ERROR_DEVA_I2C_COMM; + } else { + pTAS2557->mnErrCode &= ~ERROR_DEVA_I2C_COMM; + } + } + } + +end: + mutex_unlock(&pTAS2557->dev_lock); + return nResult; +} + +static int tas2557_dev_bulk_write(struct tas2557_priv *pTAS2557, + unsigned int nRegister, u8 *pData, + unsigned int nLength) +{ + int nResult = 0; + + mutex_lock(&pTAS2557->dev_lock); + if (pTAS2557->mbTILoadActive) { + if (!(nRegister & 0x80000000)) + goto end; /* let only writes from TILoad pass. */ + + nRegister &= ~0x80000000; + + dev_dbg(pTAS2557->dev, + "TiLoad BW REG B[%d]P[%d]R[%d], count=%d\n", + TAS2557_BOOK_ID(nRegister), TAS2557_PAGE_ID(nRegister), + TAS2557_PAGE_REG(nRegister), nLength); + } + + nResult = tas2557_change_book_page(pTAS2557, TAS2557_BOOK_ID(nRegister), + TAS2557_PAGE_ID(nRegister)); + if (nResult >= 0) { + nResult = regmap_bulk_write(pTAS2557->mpRegmap, + TAS2557_PAGE_REG(nRegister), pData, + nLength); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + pTAS2557->mnErrCode |= ERROR_DEVA_I2C_COMM; + } else + pTAS2557->mnErrCode &= ~ERROR_DEVA_I2C_COMM; + } + +end: + + mutex_unlock(&pTAS2557->dev_lock); + return nResult; +} + +static int tas2557_dev_update_bits(struct tas2557_priv *pTAS2557, + unsigned int nRegister, unsigned int nMask, + unsigned int nValue) +{ + int nResult = 0; + + mutex_lock(&pTAS2557->dev_lock); + + if (pTAS2557->mbTILoadActive) { + if (!(nRegister & 0x80000000)) + goto end; /* let only writes from TILoad pass. */ + + nRegister &= ~0x80000000; + dev_dbg(pTAS2557->dev, + "TiLoad SB REG B[%d]P[%d]R[%d], mask=0x%x, value=0x%x\n", + TAS2557_BOOK_ID(nRegister), TAS2557_PAGE_ID(nRegister), + TAS2557_PAGE_REG(nRegister), nMask, nValue); + } + + nResult = tas2557_change_book_page(pTAS2557, TAS2557_BOOK_ID(nRegister), + TAS2557_PAGE_ID(nRegister)); + if (nResult >= 0) { + nResult = regmap_update_bits(pTAS2557->mpRegmap, + TAS2557_PAGE_REG(nRegister), nMask, + nValue); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s, %d, I2C error %d\n", + __func__, __LINE__, nResult); + pTAS2557->mnErrCode |= ERROR_DEVA_I2C_COMM; + } else + pTAS2557->mnErrCode &= ~ERROR_DEVA_I2C_COMM; + } + +end: + mutex_unlock(&pTAS2557->dev_lock); + return nResult; +} + +void tas2557_clearIRQ(struct tas2557_priv *pTAS2557) +{ + unsigned int nValue; + int nResult = 0; + + nResult = pTAS2557->read(pTAS2557, TAS2557_FLAGS_1, &nValue); + if (nResult >= 0) + pTAS2557->read(pTAS2557, TAS2557_FLAGS_2, &nValue); +} + +void tas2557_enableIRQ(struct tas2557_priv *pTAS2557, bool enable) +{ + if (enable) { + if (!pTAS2557->mbIRQEnable) { + if (gpio_is_valid(pTAS2557->mnGpioINT)) { + enable_irq(pTAS2557->mnIRQ); + /* check after 10 ms */ + schedule_delayed_work(&pTAS2557->irq_work, + msecs_to_jiffies(10)); + pTAS2557->mbIRQEnable = true; + } + } + } else { + if (gpio_is_valid(pTAS2557->mnGpioINT)) + disable_irq_nosync(pTAS2557->mnIRQ); + pTAS2557->mbIRQEnable = false; + } +} + +static void tas2557_hw_reset(struct tas2557_priv *pTAS2557) +{ + if (gpio_is_valid(pTAS2557->mnResetGPIO)) { + gpio_direction_output(pTAS2557->mnResetGPIO, 0); + msleep(5); + gpio_direction_output(pTAS2557->mnResetGPIO, 1); + msleep(2); + } + + pTAS2557->mnCurrentBook = -1; + pTAS2557->mnCurrentPage = -1; + if (pTAS2557->mnErrCode) + dev_info(pTAS2557->dev, "before reset, ErrCode=0x%x\n", + pTAS2557->mnErrCode); + pTAS2557->mnErrCode = 0; +} + +static void irq_work_routine(struct work_struct *work) +{ + int nResult = 0; + unsigned int nDevInt1Status = 0, nDevInt2Status = 0; + unsigned int nDevPowerUpFlag = 0; + int nCounter = 2; + struct tas2557_priv *pTAS2557 = + container_of(work, struct tas2557_priv, irq_work.work); + +#ifdef CONFIG_TAS2557_CODEC + mutex_lock(&pTAS2557->codec_lock); +#endif + +#ifdef CONFIG_TAS2557_MISC + mutex_lock(&pTAS2557->file_lock); +#endif + + if (pTAS2557->mnErrCode & ERROR_FAILSAFE) + goto program; + + if (pTAS2557->mbRuntimeSuspend) { + dev_info(pTAS2557->dev, "%s, Runtime Suspended\n", __func__); + goto end; + } + + if (!pTAS2557->mbPowerUp) { + dev_info(pTAS2557->dev, "%s, device not powered\n", __func__); + goto end; + } + + if ((!pTAS2557->mpFirmware->mnConfigurations) || + (!pTAS2557->mpFirmware->mnPrograms)) { + dev_info(pTAS2557->dev, "%s, firmware not loaded\n", __func__); + goto end; + } + + nResult = tas2557_dev_read(pTAS2557, TAS2557_FLAGS_1, &nDevInt1Status); + if (nResult >= 0) + nResult = tas2557_dev_read(pTAS2557, TAS2557_FLAGS_2, + &nDevInt2Status); + + if (nResult < 0) + goto program; + + if (((nDevInt1Status & 0xfc) != 0) || ((nDevInt2Status & 0x0c) != 0)) { + /* in case of INT_OC, INT_UV, INT_OT, INT_BO, INT_CL, INT_CLK1, INT_CLK2 */ + dev_err(pTAS2557->dev, "critical error: 0x%x, 0x%x\n", + nDevInt1Status, nDevInt2Status); + if (nDevInt1Status & 0x80) { + pTAS2557->mnErrCode |= ERROR_OVER_CURRENT; + dev_err(pTAS2557->dev, "DEVA SPK over current!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_OVER_CURRENT; + + if (nDevInt1Status & 0x40) { + pTAS2557->mnErrCode |= ERROR_UNDER_VOLTAGE; + dev_err(pTAS2557->dev, "DEVA SPK under voltage!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_UNDER_VOLTAGE; + + if (nDevInt1Status & 0x20) { + pTAS2557->mnErrCode |= ERROR_CLK_HALT; + dev_err(pTAS2557->dev, "DEVA clk halted!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_CLK_HALT; + + if (nDevInt1Status & 0x10) { + pTAS2557->mnErrCode |= ERROR_DIE_OVERTEMP; + dev_err(pTAS2557->dev, "DEVA die over temperature!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_DIE_OVERTEMP; + + if (nDevInt1Status & 0x08) { + pTAS2557->mnErrCode |= ERROR_BROWNOUT; + dev_err(pTAS2557->dev, "DEVA brownout!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_BROWNOUT; + + if (nDevInt1Status & 0x04) { + pTAS2557->mnErrCode |= ERROR_CLK_LOST; + dev_err(pTAS2557->dev, "DEVA clock lost!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_CLK_LOST; + + if (nDevInt2Status & 0x08) { + pTAS2557->mnErrCode |= ERROR_CLK_DET1; + dev_err(pTAS2557->dev, "DEVA clk detection 1!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_CLK_DET1; + + if (nDevInt2Status & 0x04) { + pTAS2557->mnErrCode |= ERROR_CLK_DET2; + dev_err(pTAS2557->dev, "DEVA clk detection 2!\n"); + } else + pTAS2557->mnErrCode &= ~ERROR_CLK_DET2; + + goto program; + } else { + dev_dbg(pTAS2557->dev, "IRQ Status: 0x%x, 0x%x\n", + nDevInt1Status, nDevInt2Status); + nCounter = 2; + while (nCounter > 0) { + nResult = tas2557_dev_read(pTAS2557, + TAS2557_POWER_UP_FLAG_REG, + &nDevPowerUpFlag); + if (nResult < 0) + goto program; + if ((nDevPowerUpFlag & 0xc0) == 0xc0) + break; + nCounter--; + if (nCounter > 0) { + /* in case check pow status just after power on TAS2557 */ + dev_dbg(pTAS2557->dev, + "PowSts: 0x%x, check again after 10ms\n", + nDevPowerUpFlag); + msleep(10); + } + } + if ((nDevPowerUpFlag & 0xc0) != 0xc0) { + dev_err(pTAS2557->dev, + "%s, Critical ERROR B[%d]_P[%d]_R[%d]= 0x%x\n", + __func__, + TAS2557_BOOK_ID(TAS2557_POWER_UP_FLAG_REG), + TAS2557_PAGE_ID(TAS2557_POWER_UP_FLAG_REG), + TAS2557_PAGE_REG(TAS2557_POWER_UP_FLAG_REG), + nDevPowerUpFlag); + pTAS2557->mnErrCode |= ERROR_CLASSD_PWR; + goto program; + } + pTAS2557->mnErrCode &= ~ERROR_CLASSD_PWR; + + dev_dbg(pTAS2557->dev, + "%s: INT1=0x%x, INT2=0x%x; PowerUpFlag=0x%x\n", + __func__, nDevInt1Status, nDevInt2Status, + nDevPowerUpFlag); + goto end; + } + +program: + /* hardware reset and reload */ + tas2557_set_program(pTAS2557, pTAS2557->mnCurrentProgram, + pTAS2557->mnCurrentConfiguration); + +end: + +#ifdef CONFIG_TAS2557_MISC + mutex_unlock(&pTAS2557->file_lock); +#endif + +#ifdef CONFIG_TAS2557_CODEC + mutex_unlock(&pTAS2557->codec_lock); +#endif +} + +static irqreturn_t tas2557_irq_handler(int irq, void *dev_id) +{ + struct tas2557_priv *pTAS2557 = (struct tas2557_priv *)dev_id; + + tas2557_enableIRQ(pTAS2557, false); + /* get IRQ status after 100 ms */ + schedule_delayed_work(&pTAS2557->irq_work, msecs_to_jiffies(100)); + return IRQ_HANDLED; +} + +static enum hrtimer_restart temperature_timer_func(struct hrtimer *timer) +{ + struct tas2557_priv *pTAS2557 = + container_of(timer, struct tas2557_priv, mtimer); + + if (pTAS2557->mbPowerUp) { + schedule_work(&pTAS2557->mtimerwork); + schedule_delayed_work(&pTAS2557->irq_work, msecs_to_jiffies(1)); + } + return HRTIMER_NORESTART; +} + +static void timer_work_routine(struct work_struct *work) +{ + struct tas2557_priv *pTAS2557 = + container_of(work, struct tas2557_priv, mtimerwork); + int nResult, nTemp, nActTemp; + struct TProgram *pProgram; + static int nAvg; + +#ifdef CONFIG_TAS2557_CODEC + mutex_lock(&pTAS2557->codec_lock); +#endif + +#ifdef CONFIG_TAS2557_MISC + mutex_lock(&pTAS2557->file_lock); +#endif + + if (pTAS2557->mbRuntimeSuspend) { + dev_info(pTAS2557->dev, "%s, Runtime Suspended\n", __func__); + goto end; + } + + if (!pTAS2557->mpFirmware->mnConfigurations) { + dev_info(pTAS2557->dev, "%s, firmware not loaded\n", __func__); + goto end; + } + + pProgram = + &(pTAS2557->mpFirmware->mpPrograms[pTAS2557->mnCurrentProgram]); + if (!pTAS2557->mbPowerUp || + (pProgram->mnAppMode != TAS2557_APP_TUNINGMODE)) { + dev_info(pTAS2557->dev, "%s, pass, Pow=%d, program=%s\n", + __func__, pTAS2557->mbPowerUp, pProgram->mpName); + goto end; + } + + nResult = tas2557_get_die_temperature(pTAS2557, &nTemp); + if (nResult >= 0) { + nActTemp = (int)(nTemp >> 23); + dev_dbg(pTAS2557->dev, "Die=0x%x, degree=%d\n", nTemp, + nActTemp); + if (!pTAS2557->mnDieTvReadCounter) + nAvg = 0; + pTAS2557->mnDieTvReadCounter++; + nAvg += nActTemp; + if (!(pTAS2557->mnDieTvReadCounter % LOW_TEMPERATURE_COUNTER)) { + nAvg /= LOW_TEMPERATURE_COUNTER; + dev_dbg(pTAS2557->dev, "check : avg=%d\n", nAvg); + if (nAvg < -6) { + /* if Die temperature is below -6 degree C */ + if (pTAS2557->mnDevCurrentGain != + LOW_TEMPERATURE_GAIN) { + nResult = tas2557_set_DAC_gain( + pTAS2557, LOW_TEMPERATURE_GAIN); + if (nResult < 0) + goto end; + pTAS2557->mnDevCurrentGain = + LOW_TEMPERATURE_GAIN; + dev_dbg(pTAS2557->dev, + "LOW Temp: set gain to %d\n", + LOW_TEMPERATURE_GAIN); + } + } else if (nAvg > 5) { + /* if Die temperature is above 5 degree C */ + if (pTAS2557->mnDevCurrentGain != + pTAS2557->mnDevGain) { + nResult = tas2557_set_DAC_gain( + pTAS2557, pTAS2557->mnDevGain); + if (nResult < 0) + goto end; + pTAS2557->mnDevCurrentGain = + pTAS2557->mnDevGain; + dev_dbg(pTAS2557->dev, + "LOW Temp: set gain to original\n"); + } + } + nAvg = 0; + } + + if (pTAS2557->mbPowerUp) + hrtimer_start( + &pTAS2557->mtimer, + ns_to_ktime((u64)LOW_TEMPERATURE_CHECK_PERIOD * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + +end: + +#ifdef CONFIG_TAS2557_MISC + mutex_unlock(&pTAS2557->file_lock); +#endif + +#ifdef CONFIG_TAS2557_CODEC + mutex_unlock(&pTAS2557->codec_lock); +#endif +} + +static int tas2557_runtime_suspend(struct tas2557_priv *pTAS2557) +{ + dev_dbg(pTAS2557->dev, "%s\n", __func__); + + pTAS2557->mbRuntimeSuspend = true; + + if (hrtimer_active(&pTAS2557->mtimer)) { + dev_dbg(pTAS2557->dev, "cancel die temp timer\n"); + hrtimer_cancel(&pTAS2557->mtimer); + } + if (work_pending(&pTAS2557->mtimerwork)) { + dev_dbg(pTAS2557->dev, "cancel timer work\n"); + cancel_work_sync(&pTAS2557->mtimerwork); + } + if (delayed_work_pending(&pTAS2557->irq_work)) { + dev_dbg(pTAS2557->dev, "cancel IRQ work\n"); + cancel_delayed_work_sync(&pTAS2557->irq_work); + } + + return 0; +} + +static int tas2557_runtime_resume(struct tas2557_priv *pTAS2557) +{ + struct TProgram *pProgram; + + dev_dbg(pTAS2557->dev, "%s\n", __func__); + if (!pTAS2557->mpFirmware->mpPrograms) { + dev_dbg(pTAS2557->dev, "%s, firmware not loaded\n", __func__); + goto end; + } + + if (pTAS2557->mnCurrentProgram >= pTAS2557->mpFirmware->mnPrograms) { + dev_err(pTAS2557->dev, "%s, firmware corrupted\n", __func__); + goto end; + } + + pProgram = + &(pTAS2557->mpFirmware->mpPrograms[pTAS2557->mnCurrentProgram]); + if (pTAS2557->mbPowerUp && + (pProgram->mnAppMode == TAS2557_APP_TUNINGMODE)) { + if (!hrtimer_active(&pTAS2557->mtimer)) { + dev_dbg(pTAS2557->dev, + "%s, start Die Temp check timer\n", __func__); + pTAS2557->mnDieTvReadCounter = 0; + hrtimer_start( + &pTAS2557->mtimer, + ns_to_ktime((u64)LOW_TEMPERATURE_CHECK_PERIOD * + NSEC_PER_MSEC), + HRTIMER_MODE_REL); + } + } + + pTAS2557->mbRuntimeSuspend = false; +end: + + return 0; +} + +static bool tas2557_volatile(struct device *pDev, unsigned int nRegister) +{ + return true; +} + +static bool tas2557_writeable(struct device *pDev, unsigned int nRegister) +{ + return true; +} + +static const struct regmap_config tas2557_i2c_regmap = { + .reg_bits = 8, + .val_bits = 8, + .writeable_reg = tas2557_writeable, + .volatile_reg = tas2557_volatile, + .cache_type = REGCACHE_NONE, + .max_register = 128, +}; + +/* tas2557_i2c_probe : +* platform dependent +* should implement hardware reset functionality +*/ +static int tas2557_i2c_probe(struct i2c_client *pClient, + const struct i2c_device_id *pID) +{ + struct tas2557_priv *pTAS2557; + int nResult = 0; + unsigned int nValue = 0; + const char *pFWName; + + dev_info(&pClient->dev, "%s enter\n", __func__); + + pTAS2557 = devm_kzalloc(&pClient->dev, sizeof(struct tas2557_priv), + GFP_KERNEL); + if (!pTAS2557) { + nResult = -ENOMEM; + goto err; + } + + pTAS2557->dev = &pClient->dev; + i2c_set_clientdata(pClient, pTAS2557); + dev_set_drvdata(&pClient->dev, pTAS2557); + + pTAS2557->mpRegmap = devm_regmap_init_i2c(pClient, &tas2557_i2c_regmap); + if (IS_ERR(pTAS2557->mpRegmap)) { + nResult = PTR_ERR(pTAS2557->mpRegmap); + dev_err(&pClient->dev, "Failed to allocate register map: %d\n", + nResult); + goto err; + } + + if (pClient->dev.of_node) + tas2557_parse_dt(&pClient->dev, pTAS2557); + + if (gpio_is_valid(pTAS2557->mnResetGPIO)) { + nResult = gpio_request(pTAS2557->mnResetGPIO, "TAS2557-RESET"); + if (nResult < 0) { + dev_err(pTAS2557->dev, "%s: GPIO %d request error\n", + __func__, pTAS2557->mnResetGPIO); + goto err; + } + tas2557_hw_reset(pTAS2557); + } + + pTAS2557->read = tas2557_dev_read; + pTAS2557->write = tas2557_dev_write; + pTAS2557->bulk_read = tas2557_dev_bulk_read; + pTAS2557->bulk_write = tas2557_dev_bulk_write; + pTAS2557->update_bits = tas2557_dev_update_bits; + pTAS2557->enableIRQ = tas2557_enableIRQ; + pTAS2557->clearIRQ = tas2557_clearIRQ; + pTAS2557->set_config = tas2557_set_config; + pTAS2557->set_calibration = tas2557_set_calibration; + pTAS2557->hw_reset = tas2557_hw_reset; + pTAS2557->runtime_suspend = tas2557_runtime_suspend; + pTAS2557->runtime_resume = tas2557_runtime_resume; + pTAS2557->mnRestart = 0; + + mutex_init(&pTAS2557->dev_lock); + + /* Reset the chip */ + nResult = tas2557_dev_write(pTAS2557, TAS2557_SW_RESET_REG, 0x01); + if (nResult < 0) { + dev_err(&pClient->dev, "I2c fail, %d\n", nResult); + goto err; + } + + msleep(1); + { + int i; + for (i = 0; i < 0x10; i++) { + tas2557_dev_read(pTAS2557, i, &nValue); + dev_err(pTAS2557->dev, "address:%x value: %x\n", i, + nValue); + } + } + + /* Ti's original codes logic (which firmware binary selected) */ + tas2557_dev_read(pTAS2557, TAS2557_REV_PGID_REG, &nValue); + pTAS2557->mnPGID = nValue; + if (pTAS2557->mnPGID == TAS2557_PG_VERSION_2P1) { + dev_info(pTAS2557->dev, "PG2.1 Silicon found\n"); + pFWName = TAS2557_AAC_FW_NAME; + } else if (pTAS2557->mnPGID == TAS2557_PG_VERSION_1P0) { + dev_info(pTAS2557->dev, "PG1.0 Silicon found\n"); + pFWName = TAS2557_PG1P0_FW_NAME; + } else { + nResult = -ENOTSUPP; + dev_info(pTAS2557->dev, "unsupport Silicon 0x%x\n", + pTAS2557->mnPGID); + goto err; + } + + /* Use our codecs logic to select Firmware binary */ + if (pTAS2557->mnSpkType == VENDOR_ID_GOER) + pFWName = TAS2557_GOER_FW_NAME; + else if (pTAS2557->mnSpkType == VENDOR_ID_AAC) + pFWName = TAS2557_AAC_FW_NAME; + else if (pTAS2557->mnSpkType == VENDOR_ID_SSI) + pFWName = TAS2557_SSI_FW_NAME; + else + pFWName = TAS2557_DEFAULT_FW_NAME; + + if (gpio_is_valid(pTAS2557->mnGpioINT)) { + nResult = gpio_request(pTAS2557->mnGpioINT, "TAS2557-IRQ"); + if (nResult < 0) { + dev_err(pTAS2557->dev, + "%s: GPIO %d request INT error\n", __func__, + pTAS2557->mnGpioINT); + goto err; + } + + gpio_direction_input(pTAS2557->mnGpioINT); + pTAS2557->mnIRQ = gpio_to_irq(pTAS2557->mnGpioINT); + dev_dbg(pTAS2557->dev, "irq = %d\n", pTAS2557->mnIRQ); + INIT_DELAYED_WORK(&pTAS2557->irq_work, irq_work_routine); + nResult = request_threaded_irq(pTAS2557->mnIRQ, + tas2557_irq_handler, NULL, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + pClient->name, pTAS2557); + if (nResult < 0) { + dev_err(pTAS2557->dev, "request_irq failed, %d\n", + nResult); + goto err; + } + disable_irq_nosync(pTAS2557->mnIRQ); + } + + pTAS2557->mpFirmware = devm_kzalloc( + &pClient->dev, sizeof(struct TFirmware), GFP_KERNEL); + if (!pTAS2557->mpFirmware) { + nResult = -ENOMEM; + goto err; + } + + pTAS2557->mpCalFirmware = devm_kzalloc( + &pClient->dev, sizeof(struct TFirmware), GFP_KERNEL); + if (!pTAS2557->mpCalFirmware) { + nResult = -ENOMEM; + goto err; + } + +#ifdef CONFIG_TAS2557_CODEC + mutex_init(&pTAS2557->codec_lock); + tas2557_register_codec(pTAS2557); +#endif + +#ifdef CONFIG_TAS2557_MISC + mutex_init(&pTAS2557->file_lock); + tas2557_register_misc(pTAS2557); +#endif + +#ifdef ENABLE_TILOAD + tiload_driver_init(pTAS2557); +#endif + dev_dbg(pTAS2557->dev, " firmware name %s\n", pFWName); + hrtimer_init(&pTAS2557->mtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + pTAS2557->mtimer.function = temperature_timer_func; + INIT_WORK(&pTAS2557->mtimerwork, timer_work_routine); + + nResult = + request_firmware_nowait(THIS_MODULE, 1, pFWName, pTAS2557->dev, + GFP_KERNEL, pTAS2557, tas2557_fw_ready); + +err: + + return nResult; +} + +static int tas2557_i2c_remove(struct i2c_client *pClient) +{ + struct tas2557_priv *pTAS2557 = i2c_get_clientdata(pClient); + + dev_info(pTAS2557->dev, "%s\n", __func__); + +#ifdef CONFIG_TAS2557_CODEC + tas2557_deregister_codec(pTAS2557); + mutex_destroy(&pTAS2557->codec_lock); +#endif + +#ifdef CONFIG_TAS2557_MISC + tas2557_deregister_misc(pTAS2557); + mutex_destroy(&pTAS2557->file_lock); +#endif + + mutex_destroy(&pTAS2557->dev_lock); + return 0; +} + +static const struct i2c_device_id tas2557_i2c_id[] = { + { "tas2557", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, tas2557_i2c_id); + +#if defined(CONFIG_OF) +static const struct of_device_id tas2557_of_match[] = { + { .compatible = "ti,tas2557" }, + {}, +}; + +MODULE_DEVICE_TABLE(of, tas2557_of_match); +#endif + +static struct i2c_driver tas2557_i2c_driver = { + .driver = { + .name = "tas2557", + .owner = THIS_MODULE, +#if defined(CONFIG_OF) + .of_match_table = of_match_ptr(tas2557_of_match), +#endif + }, + .probe = tas2557_i2c_probe, + .remove = tas2557_i2c_remove, + .id_table = tas2557_i2c_id, +}; + +module_i2c_driver(tas2557_i2c_driver); + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TAS2557 I2C Smart Amplifier driver"); +MODULE_LICENSE("GPL v2"); + +#endif diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557.h b/techpack/audio/asoc/codecs/tas2557/tas2557.h new file mode 100644 index 000000000000..b99b129e2a63 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tas2557.h @@ -0,0 +1,485 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas2557.h +** +** Description: +** definitions and data structures for TAS2557 Android Linux driver +** +** ============================================================================= +*/ + +#ifndef _TAS2557_H +#define _TAS2557_H + +#include +#include +#include + +/* Page Control Register */ +#define TAS2557_PAGECTL_REG 0 + +/* Book Control Register (available in page0 of each book) */ +#define TAS2557_BOOKCTL_PAGE 0 +#define TAS2557_BOOKCTL_REG 127 + +/* 0000 0000 0BBB BBBB BPPP PPPP PRRR RRRR */ + +#define TAS2557_REG(book, page, reg) \ + ((((unsigned int)book * 256 * 128) + ((unsigned int)page * 128)) + reg) + +#define TAS2557_BOOK_ID(reg) ((unsigned char)(reg / (256 * 128))) +#define TAS2557_PAGE_ID(reg) ((unsigned char)((reg % (256 * 128)) / 128)) +#define TAS2557_BOOK_REG(reg) ((unsigned char)(reg % (256 * 128))) +#define TAS2557_PAGE_REG(reg) ((unsigned char)((reg % (256 * 128)) % 128)) + +/* Book0, Page0 registers */ +#define TAS2557_SW_RESET_REG TAS2557_REG(0, 0, 1) + +#define TAS2557_REV_PGID_REG TAS2557_REG(0, 0, 3) +#define TAS2557_PG_VERSION_1P0 0x80 +#define TAS2557_PG_VERSION_2P0 0x90 +#define TAS2557_PG_VERSION_2P1 0xa0 + +#define TAS2557_POWER_CTRL1_REG TAS2557_REG(0, 0, 4) +#define TAS2557_POWER_CTRL2_REG TAS2557_REG(0, 0, 5) + +#define TAS2557_SPK_CTRL_REG TAS2557_REG(0, 0, 6) +/* B0P0R6 - TAS2557_SPK_CTRL_REG */ +#define TAS2557_DAC_GAIN_MASK (0xf << 3) +#define TAS2557_DAC_GAIN_SHIFT 0x03 + +#define TAS2557_MUTE_REG TAS2557_REG(0, 0, 7) +#define TAS2557_SNS_CTRL_REG TAS2557_REG(0, 0, 8) +#define TAS2557_ADC_INPUT_SEL_REG TAS2557_REG(0, 0, 9) +#define TAS2557_DBOOST_CTL_REG TAS2557_REG(0, 0, 10) +#define TAS2557_NONAME11_REG TAS2557_REG(0, 0, 11) +#define TAS2557_NONAME12_REG TAS2557_REG(0, 0, 12) +#define TAS2557_NONAME13_REG TAS2557_REG(0, 0, 13) +#define TAS2557_NONAME14_REG TAS2557_REG(0, 0, 14) +#define TAS2557_NONAME15_REG TAS2557_REG(0, 0, 15) +#define TAS2557_NONAME16_REG TAS2557_REG(0, 0, 16) +#define TAS2557_NONAME17_REG TAS2557_REG(0, 0, 17) +#define TAS2557_NONAME18_REG TAS2557_REG(0, 0, 18) +#define TAS2557_SAR_SAMPLING_TIME_REG TAS2557_REG(0, 0, 19) +#define TAS2557_SAR_ADC1_REG TAS2557_REG(0, 0, 20) +#define TAS2557_SAR_ADC2_REG TAS2557_REG(0, 0, 21) /* B0_P0_R0x15*/ +#define TAS2557_CRC_CHECKSUM_REG TAS2557_REG(0, 0, 32) +#define TAS2557_CRC_RESET_REG TAS2557_REG(0, 0, 33) +#define TAS2557_DSP_MODE_SELECT_REG TAS2557_REG(0, 0, 34) +#define TAS2557_SAFE_GUARD_REG TAS2557_REG(0, 0, 37) +#define TAS2557_ASI_CTL1_REG TAS2557_REG(0, 0, 42) +#define TAS2557_CLK_ERR_CTRL TAS2557_REG(0, 0, 44) /* B0_P0_R0x2c*/ +#define TAS2557_CLK_ERR_CTRL2 TAS2557_REG(0, 0, 45) /* B0_P0_R0x2d*/ +#define TAS2557_CLK_ERR_CTRL3 TAS2557_REG(0, 0, 46) /* B0_P0_R0x2e*/ +#define TAS2557_DBOOST_CFG_REG TAS2557_REG(0, 0, 52) +#define TAS2557_POWER_UP_FLAG_REG TAS2557_REG(0, 0, 100) +#define TAS2557_FLAGS_1 TAS2557_REG(0, 0, 104) /* B0_P0_R0x68*/ +#define TAS2557_FLAGS_2 TAS2557_REG(0, 0, 108) /* B0_P0_R0x6c*/ + +/* Book0, Page1 registers */ +#define TAS2557_ASI1_DAC_FORMAT_REG TAS2557_REG(0, 1, 1) +#define TAS2557_ASI1_ADC_FORMAT_REG TAS2557_REG(0, 1, 2) +#define TAS2557_ASI1_OFFSET1_REG TAS2557_REG(0, 1, 3) +#define TAS2557_ASI1_ADC_PATH_REG TAS2557_REG(0, 1, 7) +#define TAS2557_ASI1_DAC_BCLK_REG TAS2557_REG(0, 1, 8) +#define TAS2557_ASI1_DAC_WCLK_REG TAS2557_REG(0, 1, 9) +#define TAS2557_ASI1_ADC_BCLK_REG TAS2557_REG(0, 1, 10) +#define TAS2557_ASI1_ADC_WCLK_REG TAS2557_REG(0, 1, 11) +#define TAS2557_ASI1_DIN_DOUT_MUX_REG TAS2557_REG(0, 1, 12) +#define TAS2557_ASI1_BDIV_CLK_SEL_REG TAS2557_REG(0, 1, 13) +#define TAS2557_ASI1_BDIV_CLK_RATIO_REG TAS2557_REG(0, 1, 14) +#define TAS2557_ASI1_WDIV_CLK_RATIO_REG TAS2557_REG(0, 1, 15) +#define TAS2557_ASI1_DAC_CLKOUT_REG TAS2557_REG(0, 1, 16) +#define TAS2557_ASI1_ADC_CLKOUT_REG TAS2557_REG(0, 1, 17) +#define TAS2557_ASI2_DAC_FORMAT_REG TAS2557_REG(0, 1, 21) +#define TAS2557_ASI2_ADC_FORMAT_REG TAS2557_REG(0, 1, 22) +#define TAS2557_ASI2_OFFSET1_REG TAS2557_REG(0, 1, 23) +#define TAS2557_ASI2_ADC_PATH_REG TAS2557_REG(0, 1, 27) +#define TAS2557_ASI2_DAC_BCLK_REG TAS2557_REG(0, 1, 28) +#define TAS2557_ASI2_DAC_WCLK_REG TAS2557_REG(0, 1, 29) +#define TAS2557_ASI2_ADC_BCLK_REG TAS2557_REG(0, 1, 30) +#define TAS2557_ASI2_ADC_WCLK_REG TAS2557_REG(0, 1, 31) +#define TAS2557_ASI2_DIN_DOUT_MUX_REG TAS2557_REG(0, 1, 32) +#define TAS2557_ASI2_BDIV_CLK_SEL_REG TAS2557_REG(0, 1, 33) +#define TAS2557_ASI2_BDIV_CLK_RATIO_REG TAS2557_REG(0, 1, 34) +#define TAS2557_ASI2_WDIV_CLK_RATIO_REG TAS2557_REG(0, 1, 35) +#define TAS2557_ASI2_DAC_CLKOUT_REG TAS2557_REG(0, 1, 36) +#define TAS2557_ASI2_ADC_CLKOUT_REG TAS2557_REG(0, 1, 37) +#define TAS2557_GPIO1_PIN_REG TAS2557_REG(0, 1, 61) /*B0_P1_R0x3d */ +#define TAS2557_GPIO2_PIN_REG TAS2557_REG(0, 1, 62) /*B0_P1_R0x3e */ +#define TAS2557_GPIO3_PIN_REG TAS2557_REG(0, 1, 63) /*B0_P1_R0x3f */ +#define TAS2557_GPIO4_PIN_REG TAS2557_REG(0, 1, 64) /*B0_P1_R0x40 */ +#define TAS2557_GPIO5_PIN_REG TAS2557_REG(0, 1, 65) +#define TAS2557_GPIO6_PIN_REG TAS2557_REG(0, 1, 66) +#define TAS2557_GPIO7_PIN_REG TAS2557_REG(0, 1, 67) +#define TAS2557_GPIO8_PIN_REG TAS2557_REG(0, 1, 68) +#define TAS2557_GPIO9_PIN_REG TAS2557_REG(0, 1, 69) +#define TAS2557_GPIO10_PIN_REG TAS2557_REG(0, 1, 70) +#define TAS2557_GPI_PIN_REG TAS2557_REG(0, 1, 77) /*B0_P1_R0x4d */ +#define TAS2557_GPIO_HIZ_CTRL1_REG TAS2557_REG(0, 1, 79) +#define TAS2557_GPIO_HIZ_CTRL2_REG TAS2557_REG(0, 1, 80) /*B0_P1_R0x50 */ +#define TAS2557_GPIO_HIZ_CTRL3_REG TAS2557_REG(0, 1, 81) +#define TAS2557_GPIO_HIZ_CTRL4_REG TAS2557_REG(0, 1, 82) +#define TAS2557_GPIO_HIZ_CTRL5_REG TAS2557_REG(0, 1, 83) +#define TAS2557_BIT_BANG_CTRL_REG TAS2557_REG(0, 1, 87) +#define TAS2557_BIT_BANG_OUT1_REG TAS2557_REG(0, 1, 88) +#define TAS2557_BIT_BANG_OUT2_REG TAS2557_REG(0, 1, 89) +#define TAS2557_BIT_BANG_IN1_REG TAS2557_REG(0, 1, 90) +#define TAS2557_BIT_BANG_IN2_REG TAS2557_REG(0, 1, 91) +#define TAS2557_BIT_BANG_IN3_REG TAS2557_REG(0, 1, 92) +#define TAS2557_PDM_IN_CLK_REG TAS2557_REG(0, 1, 94) +#define TAS2557_PDM_IN_PIN_REG TAS2557_REG(0, 1, 95) +#define TAS2557_ASIM_IFACE1_REG TAS2557_REG(0, 1, 98) +#define TAS2557_ASIM_FORMAT_REG TAS2557_REG(0, 1, 99) +#define TAS2557_ASIM_IFACE3_REG TAS2557_REG(0, 1, 100) +#define TAS2557_ASIM_IFACE4_REG TAS2557_REG(0, 1, 101) +#define TAS2557_ASIM_IFACE5_REG TAS2557_REG(0, 1, 102) +#define TAS2557_ASIM_IFACE6_REG TAS2557_REG(0, 1, 103) +#define TAS2557_ASIM_IFACE7_REG TAS2557_REG(0, 1, 104) +#define TAS2557_ASIM_IFACE8_REG TAS2557_REG(0, 1, 105) +#define TAS2557_CLK_HALT_REG TAS2557_REG(0, 1, 106) /* B0_P1_R0x6a */ +#define TAS2557_INT_GEN1_REG TAS2557_REG(0, 1, 108) /* B0_P1_R0x6c */ +#define TAS2557_INT_GEN2_REG TAS2557_REG(0, 1, 109) /* B0_P1_R0x6d */ +#define TAS2557_INT_GEN3_REG TAS2557_REG(0, 1, 110) /* B0_P1_R0x6e */ +#define TAS2557_INT_GEN4_REG TAS2557_REG(0, 1, 111) /* B0_P1_R0x6f */ +#define TAS2557_INT_MODE_REG TAS2557_REG(0, 1, 114) /* B0_P1_R0x72 */ +#define TAS2557_MAIN_CLKIN_REG TAS2557_REG(0, 1, 115) +#define TAS2557_PLL_CLKIN_REG TAS2557_REG(0, 1, 116) +#define TAS2557_CLKOUT_MUX_REG TAS2557_REG(0, 1, 117) +#define TAS2557_CLKOUT_CDIV_REG TAS2557_REG(0, 1, 118) +#define TAS2557_HACK_GP01_REG TAS2557_REG(0, 1, 122) + +#define TAS2557_HACK01_REG TAS2557_REG(0, 2, 10) + +#define TAS2557_ISENSE_THRESHOLD TAS2557_REG(0, 50, 104) +#define TAS2557_BOOSTON_EFFICIENCY TAS2557_REG(0, 51, 16) +#define TAS2557_BOOSTOFF_EFFICIENCY TAS2557_REG(0, 51, 20) +#define TAS2557_BOOST_HEADROOM TAS2557_REG(0, 51, 24) +#define TAS2557_THERMAL_FOLDBACK_REG TAS2557_REG(0, 51, 100) + +#define TAS2557_SA_PG2P1_CHL_CTRL_REG \ + TAS2557_REG(0, 53, 20) /* B0_P0x35_R0x14 */ +#define TAS2557_SA_COEFF_SWAP_REG TAS2557_REG(0, 53, 44) /* B0_P0x35_R0x2c */ + +#define TAS2557_SA_PG1P0_CHL_CTRL_REG \ + TAS2557_REG(0, 58, 120) /* B0_P0x3a_R0x78 */ + +#define TAS2557_TEST_MODE_REG TAS2557_REG(0, 253, 13) /* B0_P0xfd_R0x0d */ +#define TAS2557_BROADCAST_REG TAS2557_REG(0, 253, 54) /* B0_P0xfd_R0x36 */ +#define TAS2557_CRYPTIC_REG TAS2557_REG(0, 253, 71) +#define TAS2557_PG2P1_CALI_R0_REG TAS2557_REG(0x8c, 0x2f, 0x40) +#define TAS2557_PG1P0_CALI_R0_REG TAS2557_REG(0x8c, 0x2f, 0x28) +#define TAS2557_PG2P1_CALI_T_REG TAS2557_REG(0x8c, 0x30, 0x20) +#define TAS2557_PG1P0_CALI_T_REG TAS2557_REG(0x8c, 0x30, 0x08) + +#define TAS2557_DAC_INTERPOL_REG TAS2557_REG(100, 0, 1) +#define TAS2557_SOFT_MUTE_REG TAS2557_REG(100, 0, 7) +#define TAS2557_PLL_P_VAL_REG TAS2557_REG(100, 0, 27) +#define TAS2557_PLL_J_VAL_REG TAS2557_REG(100, 0, 28) +#define TAS2557_PLL_D_VAL_MSB_REG TAS2557_REG(100, 0, 29) +#define TAS2557_PLL_D_VAL_LSB_REG TAS2557_REG(100, 0, 30) +#define TAS2557_CLK_MISC_REG TAS2557_REG(100, 0, 31) +#define TAS2557_PLL_N_VAL_REG TAS2557_REG(100, 0, 32) +#define TAS2557_DAC_MADC_VAL_REG TAS2557_REG(100, 0, 33) +#define TAS2557_ISENSE_DIV_REG TAS2557_REG(100, 0, 42) +#define TAS2557_RAMP_CLK_DIV_MSB_REG TAS2557_REG(100, 0, 43) +#define TAS2557_RAMP_CLK_DIV_LSB_REG TAS2557_REG(100, 0, 44) + +#define TAS2557_DIE_TEMP_REG TAS2557_REG(130, 2, 124) /* B0x82_P0x02_R0x7C */ + +/* Bits */ +/* B0P0R4 - TAS2557_POWER_CTRL1_REG */ +#define TAS2557_SW_SHUTDOWN (0x1 << 0) +#define TAS2557_MADC_POWER_UP (0x1 << 3) +#define TAS2557_MDAC_POWER_UP (0x1 << 4) +#define TAS2557_NDIV_POWER_UP (0x1 << 5) +#define TAS2557_PLL_POWER_UP (0x1 << 6) +#define TAS2557_DSP_POWER_UP (0x1 << 7) + +/* B0P0R5 - TAS2557_POWER_CTRL2_REG */ +#define TAS2557_VSENSE_ENABLE (0x1 << 0) +#define TAS2557_ISENSE_ENABLE (0x1 << 1) +#define TAS2557_BOOST_ENABLE (0x1 << 5) +#define TAS2557_CLASSD_ENABLE (0x1 << 7) + +/* B0P0R7 - TAS2557_MUTE_REG */ +#define TAS2557_CLASSD_MUTE (0x1 << 0) +#define TAS2557_ISENSE_MUTE (0x1 << 1) + +/* B0P253R13 - TAS2557_TEST_MODE_REG */ +#define TAS2557_TEST_MODE_ENABLE (13) +#define TAS2557_TEST_MODE_MASK (0xf << 0) + +/* B0P253R71 - TAS2557_CRYPTIC_REG */ +#define TAS2557_OSC_TRIM_CAP(x) ((x & 0x3f) << 0) +#define TAS2557_DISABLE_ENCRYPTION (0x1 << 6) +#define TAS2557_SL_COMP (0x1 << 7) + +/* B0P1R115/6 - TAS2557_MAIN/PLL_CLKIN_REG */ +#define TAS2557_XXX_CLKIN_GPIO1 (0) +#define TAS2557_XXX_CLKIN_GPIO2 (1) +#define TAS2557_XXX_CLKIN_GPIO3 (2) +#define TAS2557_XXX_CLKIN_GPIO4 (3) +#define TAS2557_XXX_CLKIN_GPIO5 (4) +#define TAS2557_XXX_CLKIN_GPIO6 (5) +#define TAS2557_XXX_CLKIN_GPIO7 (6) +#define TAS2557_XXX_CLKIN_GPIO8 (7) +#define TAS2557_XXX_CLKIN_GPIO9 (8) +#define TAS2557_XXX_CLKIN_GPIO10 (9) +#define TAS2557_XXX_CLKIN_GPI1 (12) +#define TAS2557_XXX_CLKIN_GPI2 (13) +#define TAS2557_XXX_CLKIN_GPI3 (14) +#define TAS2557_NDIV_CLKIN_PLL (15) +#define TAS2557_PLL_CLKIN_INT_OSC (15) + +#define TAS2557_MCLK_CLKIN_SRC_GPIO1 (0) +#define TAS2557_MCLK_CLKIN_SRC_GPIO2 (1) +#define TAS2557_MCLK_CLKIN_SRC_GPIO3 (2) +#define TAS2557_MCLK_CLKIN_SRC_GPIO4 (3) +#define TAS2557_MCLK_CLKIN_SRC_GPIO5 (4) +#define TAS2557_MCLK_CLKIN_SRC_GPIO6 (5) +#define TAS2557_MCLK_CLKIN_SRC_GPIO7 (6) +#define TAS2557_MCLK_CLKIN_SRC_GPIO8 (7) +#define TAS2557_MCLK_CLKIN_SRC_GPIO9 (8) +#define TAS2557_MCLK_CLKIN_SRC_GPIO10 (9) +#define TAS2557_MCLK_CLKIN_SRC_GPI1 (12) +#define TAS2557_MCLK_CLKIN_SRC_GPI2 (13) +#define TAS2557_MCLK_CLKIN_SRC_GPI3 (14) + +#define TAS2557_FORMAT_I2S (0x0 << 5) +#define TAS2557_FORMAT_DSP (0x1 << 5) +#define TAS2557_FORMAT_RIGHT_J (0x2 << 5) +#define TAS2557_FORMAT_LEFT_J (0x3 << 5) +#define TAS2557_FORMAT_MONO_PCM (0x4 << 5) +#define TAS2557_FORMAT_MASK (0x7 << 5) + +#define TAS2557_WORDLENGTH_16BIT (0x0 << 3) +#define TAS2557_WORDLENGTH_20BIT (0x1 << 3) +#define TAS2557_WORDLENGTH_24BIT (0x2 << 3) +#define TAS2557_WORDLENGTH_32BIT (0x3 << 3) +#define TAS2557_WORDLENGTH_MASK TAS2557_WORDLENGTH_32BIT + +/* B100P0R7 - TAS2557_SOFT_MUTE_REG */ +#define TAS2557_PDM_SOFT_MUTE (0x1 << 0) +#define TAS2557_VSENSE_SOFT_MUTE (0x1 << 1) +#define TAS2557_ISENSE_SOFT_MUTE (0x1 << 2) +#define TAS2557_CLASSD_SOFT_MUTE (0x1 << 3) + +/* B100P0R27 - TAS2557_PLL_P_VAL_REG */ +#define TAS2557_PLL_P_VAL_MASK (0x3f << 0) + +/* B100P0R28 - TAS2557_PLL_J_VAL_REG */ +#define TAS2557_PLL_J_VAL_MASK ((unsigned int)(0x7f << 0)) +#define TAS2557_PLL_J_VAL_MASKX 0x00 + +/* B100P0R29-30 - TAS2557_PLL_D_VAL_MSB/LSB_REG */ +#define TAS2557_PLL_D_MSB_VAL(x) ((x >> 8) & 0x3f) +#define TAS2557_PLL_D_LSB_VAL(x) (x & 0xff) + +/* B100P0R31 - TAS2557_CLK_MISC_REG */ +#define TAS2557_DSP_CLK_FROM_PLL (0x1 << 5) + +#define TAS2557_AAC_FW_NAME "tas2557_uCDSP_aac.bin" +#define TAS2557_GOER_FW_NAME "tas2557_uCDSP_goer.bin" +#define TAS2557_SSI_FW_NAME "tas2557_uCDSP_ssi.bin" +#define TAS2557_DEFAULT_FW_NAME "tas2557_uCDSP.bin" + +#define TAS2557_PG1P0_FW_NAME "tas2557_pg1p0_uCDSP.bin" + +#define TAS2557_APP_ROM1MODE 0 +#define TAS2557_APP_ROM2MODE 1 +#define TAS2557_APP_TUNINGMODE 2 +#define TAS2557_APP_ROM1_96KHZ 3 +#define TAS2557_APP_ROM2_96KHZ 4 +#define TAS2557_APP_RAMMODE 5 + +#define TAS2557_BOOST_OFF 0 +#define TAS2557_BOOST_DEVA 1 +#define TAS2557_BOOST_DEVB 2 +#define TAS2557_BOOST_BOTH 3 + +#define ERROR_NONE 0x00000000 +#define ERROR_PLL_ABSENT 0x00000001 +#define ERROR_DEVA_I2C_COMM 0x00000002 +#define ERROR_PRAM_CRCCHK 0x00000008 +#define ERROR_YRAM_CRCCHK 0x00000010 +#define ERROR_CLK_DET2 0x00000020 +#define ERROR_CLK_DET1 0x00000040 +#define ERROR_CLK_LOST 0x00000080 +#define ERROR_BROWNOUT 0x00000100 +#define ERROR_DIE_OVERTEMP 0x00000200 +#define ERROR_CLK_HALT 0x00000400 +#define ERROR_UNDER_VOLTAGE 0x00000800 +#define ERROR_OVER_CURRENT 0x00001000 +#define ERROR_CLASSD_PWR 0x00002000 +#define ERROR_SAFE_GUARD 0x00004000 +#define ERROR_FAILSAFE 0x40000000 + +struct TBlock { + unsigned int mnType; + unsigned char mbPChkSumPresent; + unsigned char mnPChkSum; + unsigned char mbYChkSumPresent; + unsigned char mnYChkSum; + unsigned int mnCommands; + unsigned char *mpData; +}; + +struct TData { + char mpName[64]; + char *mpDescription; + unsigned int mnBlocks; + struct TBlock *mpBlocks; +}; + +struct TProgram { + char mpName[64]; + char *mpDescription; + unsigned char mnAppMode; + unsigned short mnBoost; + struct TData mData; +}; + +struct TPLL { + char mpName[64]; + char *mpDescription; + struct TBlock mBlock; +}; + +struct TConfiguration { + char mpName[64]; + char *mpDescription; + unsigned int mnDevices; + unsigned int mnProgram; + unsigned int mnPLL; + unsigned int mnSamplingRate; + unsigned char mnPLLSrc; + unsigned int mnPLLSrcRate; + struct TData mData; +}; + +struct TCalibration { + char mpName[64]; + char *mpDescription; + unsigned int mnProgram; + unsigned int mnConfiguration; + struct TData mData; +}; + +struct TFirmware { + unsigned int mnFWSize; + unsigned int mnChecksum; + unsigned int mnPPCVersion; + unsigned int mnFWVersion; + unsigned int mnDriverVersion; + unsigned int mnTimeStamp; + char mpDDCName[64]; + char *mpDescription; + unsigned int mnDeviceFamily; + unsigned int mnDevice; + unsigned int mnPLLs; + struct TPLL *mpPLLs; + unsigned int mnPrograms; + struct TProgram *mpPrograms; + unsigned int mnConfigurations; + struct TConfiguration *mpConfigurations; + unsigned int mnCalibrations; + struct TCalibration *mpCalibrations; +}; + +struct tas2557_register { + int book; + int page; + int reg; +}; + +struct tas2557_priv { + struct device *dev; + struct regmap *mpRegmap; + int mnPGID; + int mnResetGPIO; + struct mutex dev_lock; + struct TFirmware *mpFirmware; + struct TFirmware *mpCalFirmware; + unsigned int mnCurrentProgram; + unsigned int mnCurrentSampleRate; + unsigned int mnNewConfiguration; + unsigned int mnCurrentConfiguration; + unsigned int mnCurrentCalibration; + unsigned char mnCurrentBook; + unsigned char mnCurrentPage; + bool mbTILoadActive; + bool mbPowerUp; + bool mbMute; + bool mbLoadConfigurationPrePowerUp; + bool mbLoadCalibrationPostPowerUp; + bool mbCalibrationLoaded; + int (*read)(struct tas2557_priv *pTAS2557, unsigned int reg, + unsigned int *pValue); + int (*write)(struct tas2557_priv *pTAS2557, unsigned int reg, + unsigned int Value); + int (*bulk_read)(struct tas2557_priv *pTAS2557, unsigned int reg, + unsigned char *pData, unsigned int len); + int (*bulk_write)(struct tas2557_priv *pTAS2557, unsigned int reg, + unsigned char *pData, unsigned int len); + int (*update_bits)(struct tas2557_priv *pTAS2557, unsigned int reg, + unsigned int mask, unsigned int value); + int (*set_config)(struct tas2557_priv *pTAS2557, int config); + int (*set_calibration)(struct tas2557_priv *pTAS2557, int calibration); + void (*clearIRQ)(struct tas2557_priv *pTAS2557); + void (*enableIRQ)(struct tas2557_priv *pTAS2557, bool enable); + void (*hw_reset)(struct tas2557_priv *pTAS2557); + /* device is working, but system is suspended */ + int (*runtime_suspend)(struct tas2557_priv *pTAS2557); + int (*runtime_resume)(struct tas2557_priv *pTAS2557); + + int mnGpioINT; + struct delayed_work irq_work; + unsigned int mnIRQ; + bool mbIRQEnable; + unsigned char mnI2SBits; + + /* for low temperature check */ + unsigned int mnDevGain; + unsigned int mnDevCurrentGain; + unsigned int mnDieTvReadCounter; + struct hrtimer mtimer; + struct work_struct mtimerwork; + + /* device is working, but system is suspended */ + bool mbRuntimeSuspend; + + unsigned int mnErrCode; + unsigned int mnRestart; + + /* for configurations with maximum TLimit 0x7fffffff, + * bypass calibration update, usually used in factory test + */ + bool mbBypassTMax; + +#ifdef CONFIG_TAS2557_CODEC + struct mutex codec_lock; +#endif + +#ifdef CONFIG_TAS2557_MISC + int mnDBGCmd; + int mnCurrentReg; + struct mutex file_lock; +#endif + int mnSpkType; + struct device_node *spk_id_gpio_p; +}; + +#endif /* _TAS2557_H */ diff --git a/techpack/audio/asoc/codecs/tas2557/tiload.c b/techpack/audio/asoc/codecs/tas2557/tiload.c new file mode 100644 index 000000000000..bc88bf6cca0c --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tiload.c @@ -0,0 +1,447 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tiload.c +** +** Description: +** utility for TAS2557 Android in-system tuning +** +** ============================================================================= +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tiload.h" + +/* enable debug prints in the driver */ +#define DEBUG + +static struct cdev *tiload_cdev; +static int tiload_major; /* Dynamic allocation of Mjr No. */ +static int tiload_opened; /* Dynamic allocation of Mjr No. */ +static struct tas2557_priv *g_TAS2557; +struct class *tiload_class; +static unsigned int magic_num; + +static char gPage; +static char gBook; +/******************************** Debug section *****************************/ + +/*---------------------------------------------------------------------------- + * Function : tiload_open + * + * Purpose : open method for tiload programming interface + *---------------------------------------------------------------------------- + */ +static int tiload_open(struct inode *in, struct file *filp) +{ + struct tas2557_priv *pTAS2557 = g_TAS2557; + + dev_info(pTAS2557->dev, "%s\n", __func__); + + if (tiload_opened) { + dev_info(pTAS2557->dev, "%s device is already opened\n", + "tiload"); + return -EINVAL; + } + filp->private_data = (void *)pTAS2557; + tiload_opened++; + return 0; +} + +/*---------------------------------------------------------------------------- + * Function : tiload_release + * + * Purpose : close method for tiload programming interface + *---------------------------------------------------------------------------- + */ +static int tiload_release(struct inode *in, struct file *filp) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)filp->private_data; + + dev_info(pTAS2557->dev, "%s\n", __func__); + filp->private_data = NULL; + tiload_opened--; + return 0; +} + +#define MAX_LENGTH 128 +/*---------------------------------------------------------------------------- + * Function : tiload_read + * + * Purpose : read from codec + *---------------------------------------------------------------------------- + */ +static ssize_t tiload_read(struct file *filp, char __user *buf, size_t count, + loff_t *offset) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)filp->private_data; + char *rd_data; + unsigned int nCompositeRegister = 0, Value = 0; + char reg_addr; + size_t size; + int ret = 0; +#ifdef DEBUG + /* int i; */ +#endif + + dev_info(pTAS2557->dev, "%s\n", __func__); + if (count > MAX_LENGTH) { + dev_err(pTAS2557->dev, "Max %d bytes can be read\n", + MAX_LENGTH); + return -EINVAL; + } + + /* copy register address from user space */ + size = copy_from_user(®_addr, buf, 1); + if (size != 0) { + dev_err(pTAS2557->dev, "read: copy_from_user failure\n"); + return -EINVAL; + } + + size = count; + + rd_data = kmalloc(MAX_LENGTH + 1, GFP_KERNEL | GFP_DMA); + + if (rd_data == NULL) { + dev_err(pTAS2557->dev, "kmalloc fail \n"); + return -EINVAL; + } + + nCompositeRegister = BPR_REG(gBook, gPage, reg_addr); + if (count == 1) { + ret = pTAS2557->read(pTAS2557, 0x80000000 | nCompositeRegister, + &Value); + if (ret >= 0) + rd_data[0] = (char)Value; + } else if (count > 1) { + ret = pTAS2557->bulk_read(pTAS2557, + 0x80000000 | nCompositeRegister, + rd_data, size); + } + if (ret < 0) + dev_err(pTAS2557->dev, + "%s, %d, ret=%d, count=%zu error happen!\n", __func__, + __LINE__, ret, count); + +#ifdef DEBUG + dev_info(pTAS2557->dev, "read size = %d, reg_addr= %x , count = %d\n", + (int)size, reg_addr, (int)count); +/* for (i = 0; i < (int) size; i++) { +* dev_dbg(pTAS2557->dev, "rd_data[%d]=%x\n", i, rd_data[i]); +* } +*/ +#endif + if (size != count) + dev_err(pTAS2557->dev, "read %d registers from the codec\n", + (int)size); + + if (copy_to_user(buf, rd_data, size) != 0) { + dev_err(pTAS2557->dev, "copy_to_user failed\n"); + kfree(rd_data); + return -EINVAL; + } + + kfree(rd_data); + return size; +} + +/* + *---------------------------------------------------------------------------- + * Function : tiload_write + * + * Purpose : write to codec + *---------------------------------------------------------------------------- + */ +static ssize_t tiload_write(struct file *filp, const char __user *buf, + size_t count, loff_t *offset) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)filp->private_data; + char *wr_data; + char *pData; + size_t size; + unsigned int nCompositeRegister = 0; + unsigned int nRegister; + int ret = 0; +#ifdef DEBUG + /* int i; */ +#endif + dev_info(pTAS2557->dev, "%s\n", __func__); + + if (count > MAX_LENGTH) { + dev_err(pTAS2557->dev, "Max %d bytes can be read\n", + MAX_LENGTH); + return -EINVAL; + } + + wr_data = kmalloc(MAX_LENGTH + 1, GFP_KERNEL | GFP_DMA); + if (wr_data == NULL) { + dev_err(pTAS2557->dev, "kmalloc fail \n"); + return -EINVAL; + } + pData = wr_data; + + /* copy buffer from user space */ + size = copy_from_user(wr_data, buf, count); + if (size != 0) { + dev_err(pTAS2557->dev, "copy_from_user failure %d\n", + (int)size); + kfree(wr_data); + return -EINVAL; + } +#ifdef DEBUG + dev_info(pTAS2557->dev, "write size = %zu\n", count); +/* for (i = 0; i < (int) count; i++) { +* dev_info(pTAS2557->dev, "wr_data[%d]=%x\n", i, wr_data[i]); +* } +*/ +#endif + nRegister = wr_data[0]; + size = count; + if ((nRegister == 127) && (gPage == 0)) { + gBook = wr_data[1]; + kfree(wr_data); + return size; + } + + if (nRegister == 0) { + gPage = wr_data[1]; + pData++; + count--; + } + + nCompositeRegister = BPR_REG(gBook, gPage, nRegister); + if (count == 2) { + ret = pTAS2557->write(pTAS2557, 0x80000000 | nCompositeRegister, + pData[1]); + } else if (count > 2) { + ret = pTAS2557->bulk_write(pTAS2557, + 0x80000000 | nCompositeRegister, + &pData[1], count - 1); + } + + if (ret < 0) + dev_err(pTAS2557->dev, + "%s, %d, ret=%d, count=%zu, ERROR Happen\n", __func__, + __LINE__, ret, count); + kfree(wr_data); + return size; +} + +static void tiload_route_IO(struct tas2557_priv *pTAS2557, unsigned int bLock) +{ + if (bLock) + pTAS2557->write(pTAS2557, 0xAFFEAFFE, 0xBABEBABE); + else + pTAS2557->write(pTAS2557, 0xBABEBABE, 0xAFFEAFFE); +} + +static long tiload_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)filp->private_data; + long num = 0; + void __user *argp = (void __user *)arg; + int val; + struct BPR bpr; + + dev_info(pTAS2557->dev, "%s, cmd=0x%x\n", __func__, cmd); + /* if (_IOC_TYPE(cmd) != TILOAD_IOC_MAGIC) + * return -ENOTTY; + */ + + switch (cmd) { + case TILOAD_IOMAGICNUM_GET: + num = copy_to_user(argp, &magic_num, sizeof(int)); + break; + case TILOAD_IOMAGICNUM_SET: + num = copy_from_user(&magic_num, argp, sizeof(int)); + dev_info(pTAS2557->dev, "TILOAD_IOMAGICNUM_SET\n"); + tiload_route_IO(pTAS2557, magic_num); + break; + case TILOAD_BPR_READ: + break; + case TILOAD_BPR_WRITE: + num = copy_from_user(&bpr, argp, sizeof(struct BPR)); + dev_info(pTAS2557->dev, + "TILOAD_BPR_WRITE: 0x%02X, 0x%02X, 0x%02X\n\r", + bpr.nBook, bpr.nPage, bpr.nRegister); + break; + case TILOAD_IOCTL_SET_CHL: + break; + case TILOAD_IOCTL_SET_CONFIG: + num = copy_from_user(&val, argp, sizeof(val)); + pTAS2557->set_config(pTAS2557, val); + break; + case TILOAD_IOCTL_SET_CALIBRATION: + num = copy_from_user(&val, argp, sizeof(val)); + pTAS2557->set_calibration(pTAS2557, val); + break; + default: + break; + } + return num; +} + +#ifdef CONFIG_COMPAT +static long tiload_compat_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct tas2557_priv *pTAS2557 = + (struct tas2557_priv *)filp->private_data; + long nResult = 0; + + switch (cmd) { + case TILOAD_COMPAT_IOMAGICNUM_GET: + dev_info(pTAS2557->dev, + "%s, TILOAD_COMPAT_IOMAGICNUM_GET=0x%x\n", __func__, + cmd); + nResult = tiload_ioctl(filp, TILOAD_IOMAGICNUM_GET, + (unsigned long)compat_ptr(arg)); + break; + + case TILOAD_COMPAT_IOMAGICNUM_SET: + dev_info(pTAS2557->dev, + "%s, TILOAD_COMPAT_IOMAGICNUM_SET=0x%x\n", __func__, + cmd); + nResult = tiload_ioctl(filp, TILOAD_IOMAGICNUM_SET, + (unsigned long)compat_ptr(arg)); + break; + + case TILOAD_COMPAT_BPR_READ: + dev_info(pTAS2557->dev, "%s, TILOAD_COMPAT_BPR_READ=0x%x\n", + __func__, cmd); + nResult = tiload_ioctl(filp, TILOAD_BPR_READ, + (unsigned long)compat_ptr(arg)); + break; + + case TILOAD_COMPAT_BPR_WRITE: + dev_info(pTAS2557->dev, "%s, TILOAD_COMPAT_BPR_WRITE=0x%x\n", + __func__, cmd); + nResult = tiload_ioctl(filp, TILOAD_BPR_WRITE, + (unsigned long)compat_ptr(arg)); + break; + + case TILOAD_COMPAT_IOCTL_SET_CHL: + dev_info(pTAS2557->dev, + "%s, TILOAD_COMPAT_IOCTL_SET_CHL=0x%x\n", __func__, + cmd); + nResult = tiload_ioctl(filp, TILOAD_IOCTL_SET_CHL, + (unsigned long)compat_ptr(arg)); + break; + + case TILOAD_COMPAT_IOCTL_SET_CONFIG: + dev_info(pTAS2557->dev, + "%s, TILOAD_COMPAT_IOCTL_SET_CONFIG=0x%x\n", __func__, + cmd); + nResult = tiload_ioctl(filp, TILOAD_IOCTL_SET_CONFIG, + (unsigned long)compat_ptr(arg)); + break; + + case TILOAD_COMPAT_IOCTL_SET_CALIBRATION: + dev_info(pTAS2557->dev, + "%s, TILOAD_COMPAT_IOCTL_SET_CALIBRATION=0x%x\n", + __func__, cmd); + nResult = tiload_ioctl(filp, TILOAD_IOCTL_SET_CALIBRATION, + (unsigned long)compat_ptr(arg)); + break; + + default: + dev_err(pTAS2557->dev, "%s, unsupport compat ioctl=0x%x\n", + __func__, cmd); + break; + } + + return nResult; +} +#endif + +/*********** File operations structure for tiload *************/ +static const struct file_operations tiload_fops = { + .owner = THIS_MODULE, + .open = tiload_open, + .release = tiload_release, + .read = tiload_read, + .write = tiload_write, + .unlocked_ioctl = tiload_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = tiload_compat_ioctl, +#endif +}; + +/*---------------------------------------------------------------------------- + * Function : tiload_driver_init + * + * Purpose : Register a char driver for dynamic tiload programming + *---------------------------------------------------------------------------- + */ +int tiload_driver_init(struct tas2557_priv *pTAS2557) +{ + int result; + dev_t dev = MKDEV(tiload_major, 0); + + g_TAS2557 = pTAS2557; + + dev_info(pTAS2557->dev, "%s\n", __func__); + + result = alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME); + if (result < 0) { + dev_err(pTAS2557->dev, "cannot allocate major number %d\n", + tiload_major); + return result; + } + tiload_class = class_create(THIS_MODULE, DEVICE_NAME); + tiload_major = MAJOR(dev); + dev_info(pTAS2557->dev, "allocated Major Number: %d\n", tiload_major); + + tiload_cdev = cdev_alloc(); + cdev_init(tiload_cdev, &tiload_fops); + tiload_cdev->owner = THIS_MODULE; + tiload_cdev->ops = &tiload_fops; + + if (device_create(tiload_class, NULL, dev, NULL, "tiload_node") == NULL) + dev_err(pTAS2557->dev, "Device creation failed\n"); + + if (cdev_add(tiload_cdev, dev, 1) < 0) { + dev_err(pTAS2557->dev, "tiload_driver: cdev_add failed\n"); + unregister_chrdev_region(dev, 1); + tiload_cdev = NULL; + return 1; + } + dev_info(pTAS2557->dev, "Registered TiLoad driver, Major number: %d\n", + tiload_major); + /* class_device_create(tiload_class, NULL, dev, NULL, DEVICE_NAME, 0); */ + return 0; +} + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("Utility for TAS2557 Android in-system tuning"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/tas2557/tiload.h b/techpack/audio/asoc/codecs/tas2557/tiload.h new file mode 100644 index 000000000000..832093771f7f --- /dev/null +++ b/techpack/audio/asoc/codecs/tas2557/tiload.h @@ -0,0 +1,66 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2019 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tiload.h +** +** Description: +** header file for tiload.c +** +** ============================================================================= +*/ + +#ifndef _TILOAD_H +#define _TILOAD_H + +#ifdef CONFIG_COMPAT +#include +#endif + +#include "tas2557.h" + +#define BPR_REG(book, page, reg) (((book * 256 * 128) + (page * 128)) + reg) + +/* typedefs required for the included header files */ +struct BPR { + unsigned char nBook; + unsigned char nPage; + unsigned char nRegister; +}; + +/* defines */ +#define DEVICE_NAME "tiload_node" + +#define TILOAD_IOC_MAGIC 0xE0 +#define TILOAD_IOMAGICNUM_GET _IOR(TILOAD_IOC_MAGIC, 1, int) +#define TILOAD_IOMAGICNUM_SET _IOW(TILOAD_IOC_MAGIC, 2, int) +#define TILOAD_BPR_READ _IOR(TILOAD_IOC_MAGIC, 3, struct BPR) +#define TILOAD_BPR_WRITE _IOW(TILOAD_IOC_MAGIC, 4, struct BPR) +#define TILOAD_IOCTL_SET_CHL _IOW(TILOAD_IOC_MAGIC, 5, int) +#define TILOAD_IOCTL_SET_CONFIG _IOW(TILOAD_IOC_MAGIC, 6, int) +#define TILOAD_IOCTL_SET_CALIBRATION _IOW(TILOAD_IOC_MAGIC, 7, int) + +#ifdef CONFIG_COMPAT +#define TILOAD_COMPAT_IOMAGICNUM_GET _IOR(TILOAD_IOC_MAGIC, 1, compat_int_t) +#define TILOAD_COMPAT_IOMAGICNUM_SET _IOW(TILOAD_IOC_MAGIC, 2, compat_int_t) +#define TILOAD_COMPAT_BPR_READ _IOR(TILOAD_IOC_MAGIC, 3, struct BPR) +#define TILOAD_COMPAT_BPR_WRITE _IOW(TILOAD_IOC_MAGIC, 4, struct BPR) +#define TILOAD_COMPAT_IOCTL_SET_CHL _IOW(TILOAD_IOC_MAGIC, 5, compat_int_t) +#define TILOAD_COMPAT_IOCTL_SET_CONFIG _IOW(TILOAD_IOC_MAGIC, 6, compat_int_t) +#define TILOAD_COMPAT_IOCTL_SET_CALIBRATION \ + _IOW(TILOAD_IOC_MAGIC, 7, compat_int_t) +#endif + +int tiload_driver_init(struct tas2557_priv *pTAS2557); + +#endif diff --git a/techpack/audio/asoc/codecs/tas256x/Android.mk b/techpack/audio/asoc/codecs/tas256x/Android.mk new file mode 100644 index 000000000000..a8e7721869ec --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/Android.mk @@ -0,0 +1,55 @@ +# Android makefile for audio kernel modules + +# Assume no targets will be supported + +# Check if this driver needs be built for current target +ifeq ($(call is-board-platform,msmnile),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m +endif + +ifeq ($(call is-board-platform,$(MSMSTEPPE)),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m +endif + +AUDIO_CHIPSET := audio +# Build/Package only in case of supported target +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE)),true) + +LOCAL_PATH := $(call my-dir) + +# This makefile is only for DLKM +ifneq ($(findstring vendor,$(LOCAL_PATH)),) + +ifneq ($(findstring opensource,$(LOCAL_PATH)),) + #AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/vendor/qcom/opensource/audio-kernel + AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel +endif # opensource + +DLKM_DIR := $(TOP)/device/qcom/common/dlkm + +# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko +########################################################### +# This is set once per LOCAL_PATH, not per (kernel) module +KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR) + +# We are actually building audio.ko here, as per the +# requirement we are specifying _audio.ko as LOCAL_MODULE. +# This means we need to rename the module to _audio.ko +# after audio.ko is built. +KBUILD_OPTIONS += MODNAME=tas256x_dlkm +KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM) +KBUILD_OPTIONS += $(AUDIO_SELECT) + +########################################################### +include $(CLEAR_VARS) +LOCAL_MODULE := $(AUDIO_CHIPSET)_tas256x.ko +LOCAL_MODULE_KBUILD_NAME := tas256x_dlkm.ko +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +include $(DLKM_DIR)/AndroidKernelModule.mk +########################################################### +########################################################### + +endif # DLKM check +endif # supported target check diff --git a/techpack/audio/asoc/codecs/tas256x/Kbuild b/techpack/audio/asoc/codecs/tas256x/Kbuild new file mode 100644 index 000000000000..b86ec227a743 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/Kbuild @@ -0,0 +1,116 @@ +# We can build either as part of a standalone Kernel build or as +# an external module. Determine which mechanism is being used +ifeq ($(MODNAME),) + KERNEL_BUILD := 1 +else + KERNEL_BUILD := 0 +endif + + + +ifeq ($(KERNEL_BUILD), 1) + # These are configurable via Kconfig for kernel-based builds + # Need to explicitly configure for Android-based builds + AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/kernel/msm-4.14 + AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio +endif + +ifeq ($(KERNEL_BUILD), 0) + ifeq ($(CONFIG_ARCH_SM8150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + ifeq ($(CONFIG_ARCH_SM6150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + + ifeq ($(CONFIG_ARCH_SDMSHRIKE), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif +endif + +# As per target team, build is done as follows: +# Defconfig : build with default flags +# Slub : defconfig + CONFIG_SLUB_DEBUG := y + +# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y +# Perf : Using appropriate msmXXXX-perf_defconfig +# +# Shipment builds (user variants) should not have any debug feature +# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds +# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since +# there is no other way to identify defconfig builds, QTI internal +# representation of perf builds (identified using the string 'perf'), +# is used to identify if the build is a slub or defconfig one. This +# way no critical debug feature will be enabled for perf and shipment +# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT +# config. + +############ UAPI ############ +UAPI_DIR := uapi +UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR) + +############ COMMON ############ +COMMON_DIR := include +COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR) + +############ TAS2562 ############ + +# for TAS2562 Codec +ifdef CONFIG_SND_SOC_TAS256X + TAS256X_OBJS := tas256x-codec.o tas256x-regmap.o tas256x.o +endif +# for TAS2562 Algo +ifdef CONFIG_TAS25XX_ALGO + EXTRA_CFLAGS += -DCONFIG_TAS25XX_ALGO + TAS256X_OBJS += tas25xx-algo.o tas25xx-calib.o +endif + +LINUX_INC += -Iinclude/linux + +INCS += $(COMMON_INC) \ + $(UAPI_INC) + +EXTRA_CFLAGS += $(INCS) + + +CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ + -DANI_LITTLE_BIT_ENDIAN \ + -DDOT11F_LITTLE_ENDIAN_HOST \ + -DANI_COMPILER_TYPE_GCC \ + -DANI_OS_TYPE_ANDROID=6 \ + -DPTT_SOCK_SVC_ENABLE \ + -Wall\ + -Werror\ + -D__linux__ + +KBUILD_CPPFLAGS += $(CDEFINES) + +# Currently, for versions of gcc which support it, the kernel Makefile +# is disabling the maybe-uninitialized warning. Re-enable it for the +# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it +# will override the kernel settings. +ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y) +EXTRA_CFLAGS += -Wmaybe-uninitialized +endif +#EXTRA_CFLAGS += -Wmissing-prototypes + +ifeq ($(call cc-option-yn, -Wheader-guard),y) +EXTRA_CFLAGS += -Wheader-guard +endif + +ifeq ($(KERNEL_BUILD), 0) +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers +endif + +# Module information used by KBuild framework +obj-$(CONFIG_SND_SOC_TAS256X) += tas256x_dlkm.o +tas256x_dlkm-y := $(TAS256X_OBJS) diff --git a/techpack/audio/asoc/codecs/tas256x/Kconfig b/techpack/audio/asoc/codecs/tas256x/Kconfig new file mode 100644 index 000000000000..ffc6b777ce89 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/Kconfig @@ -0,0 +1,23 @@ +# +# TAS256X codec +# + +menuconfig SND_SOC_TAS256X + tristate "SND_SOC_TAS256X" + default n + +if SND_SOC_TAS256X + +config TAS256X_CODEC + tristate "TAS256X_CODEC" + default n + +config TAS256X_REGMAP + tristate "TAS256X_REGMAP" + default n + +config TAS25XX_ALGO + tristate "TAS25XX_ALGO" + default n + +endif diff --git a/techpack/audio/asoc/codecs/tas256x/Makefile b/techpack/audio/asoc/codecs/tas256x/Makefile new file mode 100644 index 000000000000..60b4454a6fab --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/Makefile @@ -0,0 +1,9 @@ +ccflags-y += -I$(srctree)/sound/soc/codecs/tas256x + +obj-y += snd-soc-tas256x.o + +snd-soc-tas256x-y := tas256x-codec.o \ + tas256x-regmap.o \ + tas256x.o +snd-soc-tas256x-$(CONFIG_TAS25XX_ALGO) += algo/src/tas25xx-algo.o \ + algo/src/tas25xx-calib.o diff --git a/techpack/audio/asoc/codecs/tas256x/tas2562.h b/techpack/audio/asoc/codecs/tas256x/tas2562.h new file mode 100644 index 000000000000..efd60f0849eb --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas2562.h @@ -0,0 +1,731 @@ +#ifndef __TAS2562_ +#define __TAS2562_ +/* Software Reset */ +#define TAS2562_SOFTWARERESET (TAS256X_SOFTWARERESET) +#define TAS2562_SOFTWARERESET_SOFTWARERESET_MASK \ + (TAS256X_SOFTWARERESET_SOFTWARERESET_MASK) +#define TAS2562_SOFTWARERESET_SOFTWARERESET_DONTRESET \ + (TAS256X_SOFTWARERESET_SOFTWARERESET_DONTRESET) +#define TAS2562_SOFTWARERESET_SOFTWARERESET_RESET \ + (TAS256X_SOFTWARERESET_SOFTWARERESET_RESET) + +/* Power Control */ +#define TAS2562_POWERCONTROL (TAS256X_POWERCONTROL) +#define TAS2562_POWERCONTROL_ISNSPOWER_MASK \ + (TAS256X_POWERCONTROL_ISNSPOWER_MASK) +#define TAS2562_POWERCONTROL_ISNSPOWER_ACTIVE \ + (TAS256X_POWERCONTROL_ISNSPOWER_ACTIVE) +#define TAS2562_POWERCONTROL_ISNSPOWER_POWEREDDOWN \ + (TAS256X_POWERCONTROL_ISNSPOWER_POWEREDDOWN) +#define TAS2562_POWERCONTROL_VSNSPOWER_MASK \ + (TAS256X_POWERCONTROL_VSNSPOWER_MASK) +#define TAS2562_POWERCONTROL_VSNSPOWER_ACTIVE \ + (TAS256X_POWERCONTROL_VSNSPOWER_ACTIVE) +#define TAS2562_POWERCONTROL_VSNSPOWER_POWEREDDOWN \ + (TAS256X_POWERCONTROL_VSNSPOWER_POWEREDDOWN) +#define TAS2562_POWERCONTROL_OPERATIONALMODE10_MASK \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_MASK) +#define TAS2562_POWERCONTROL_OPERATIONALMODE10_ACTIVE \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_ACTIVE) +#define TAS2562_POWERCONTROL_OPERATIONALMODE10_MUTE \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_MUTE) +#define TAS2562_POWERCONTROL_OPERATIONALMODE10_SHUTDOWN \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_SHUTDOWN) + +/* Playback Configuration Reg0 */ +#define TAS2562_PLAYBACKCONFIGURATIONREG0 (TAS256X_PLAYBACKCONFIGURATIONREG0) +#define TAS2562_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_MASK \ + (TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_MASK) +#define TAS2562_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_ENABLED \ + (TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_ENABLED) +#define TAS2562_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_DISABLED \ + (TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_DISABLED) +#define TAS2562_PLAYBACKCONFIGURATIONREG0_AMPLIFIERLEVEL51_MASK (0x1f << 1) + +/* Misc Configuration Reg0 */ +#define TAS2562_MISCCONFIGURATIONREG0 (TAS256X_MISCCONFIGURATIONREG0) +#define TAS2562_MISCCONFIGURATIONREG0_CPPGRETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_MASK) +#define TAS2562_MISCCONFIGURATIONREG0_CPPGRETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_DONOTRETRY) +#define TAS2562_MISCCONFIGURATIONREG0_CPPGRETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_RETRY) +#define TAS2562_MISCCONFIGURATIONREG0_VBATPRORETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_MASK) +#define TAS2562_MISCCONFIGURATIONREG0_VBATPRORETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_DONOTRETRY) +#define TAS2562_MISCCONFIGURATIONREG0_VBATPRORETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_RETRY) +#define TAS2562_MISCCONFIGURATIONREG0_OCERETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_OCERETRY_MASK) +#define TAS2562_MISCCONFIGURATIONREG0_OCERETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OCERETRY_DONOTRETRY) +#define TAS2562_MISCCONFIGURATIONREG0_OCERETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OCERETRY_RETRY) +#define TAS2562_MISCCONFIGURATIONREG0_OTERETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_OTERETRY_MASK) +#define TAS2562_MISCCONFIGURATIONREG0_OTERETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OTERETRY_DONOTRETRY) +#define TAS2562_MISCCONFIGURATIONREG0_OTERETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OTERETRY_RETRY) +#define TAS2562_MISCCONFIGURATIONREG0_IRQZPULL_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_MASK) +#define TAS2562_MISCCONFIGURATIONREG0_IRQZPULL_DISABLED \ + (TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_DISABLED) +#define TAS2562_MISCCONFIGURATIONREG0_IRQZPULL_ENABLED \ + (TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_ENABLED) +#define TAS2562_MISCCONFIGURATIONREG0_AMPSS_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_AMPSS_MASK) +#define TAS2562_MISCCONFIGURATIONREG0_AMPSS_DISABLED \ + (TAS256X_MISCCONFIGURATIONREG0_AMPSS_DISABLED) +#define TAS2562_MISCCONFIGURATIONREG0_AMPSS_ENABLED \ + (TAS256X_MISCCONFIGURATIONREG0_AMPSS_ENABLED) + +/* TDM Configuration Reg0 */ +#define TAS2562_TDMCONFIGURATIONREG0 (TAS256X_TDMCONFIGURATIONREG0) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ) +#define TAS2562_TDMCONFIGURATIONREG0_DETECTSAMPRATE_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_MASK) +#define TAS2562_TDMCONFIGURATIONREG0_DETECTSAMPRATE_DISABLED \ + (TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_DISABLED) +#define TAS2562_TDMCONFIGURATIONREG0_DETECTSAMPRATE_ENABLED \ + (TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_ENABLED) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATE31_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATE31_14_7_16KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_14_7_16KHZ) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATE31_44_1_48KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_44_1_48KHZ) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATE31_88_2_96KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_88_2_96KHZ) +#define TAS2562_TDMCONFIGURATIONREG0_SAMPRATE31_176_4_192KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_176_4_192KHZ) +#define TAS2562_TDMCONFIGURATIONREG0_FRAMESTART_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_MASK) +#define TAS2562_TDMCONFIGURATIONREG0_FRAMESTART_LOWTOHIGH \ + (TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_LOWTOHIGH) +#define TAS2562_TDMCONFIGURATIONREG0_FRAMESTART_HIGHTOLOW \ + (TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_HIGHTOLOW) + +/* TDM Configuration Reg1 */ +#define TAS2562_TDMCONFIGURATIONREG1 (TAS256X_TDMCONFIGURATIONREG1) +#define TAS2562_TDMCONFIGURATIONREG1_RXJUSTIFY_MASK \ + (TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_MASK) +#define TAS2562_TDMCONFIGURATIONREG1_RXJUSTIFY_LEFT \ + (TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_LEFT) +#define TAS2562_TDMCONFIGURATIONREG1_RXJUSTIFY_RIGHT \ + (TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_RIGHT) +#define TAS2562_TDMCONFIGURATIONREG1_RXOFFSET51_MASK \ + (TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_MASK) +#define TAS2562_TDMCONFIGURATIONREG1_RXOFFSET51_SHIFT \ + (TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_SHIFT) +#define TAS2562_TDMCONFIGURATIONREG1_RXEDGE_MASK \ + (TAS256X_TDMCONFIGURATIONREG1_RXEDGE_MASK) +#define TAS2562_TDMCONFIGURATIONREG1_RXEDGE_RISING \ + (TAS256X_TDMCONFIGURATIONREG1_RXEDGE_RISING) +#define TAS2562_TDMCONFIGURATIONREG1_RXEDGE_FALLING \ + (TAS256X_TDMCONFIGURATIONREG1_RXEDGE_FALLING) + +/* TDM Configuration Reg2 */ +#define TAS2562_TDMCONFIGURATIONREG2 (TAS256X_TDMCONFIGURATIONREG2) +#define TAS2562_TDMCONFIGURATIONREG2_IVLEN76_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK) +#define TAS2562_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS) +#define TAS2562_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS) +#define TAS2562_TDMCONFIGURATIONREG2_IVLENCFG76_8BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_8BITS) +#define TAS2562_TDMCONFIGURATIONREG2_IVMONLEN76_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_MASK) +#define TAS2562_TDMCONFIGURATIONREG2_IVMONLEN76_8BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_8BITS) +#define TAS2562_TDMCONFIGURATIONREG2_IVMONLEN76_12BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_12BITS) +#define TAS2562_TDMCONFIGURATIONREG2_IVMONLEN76_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_16BITS) +#define TAS2562_TDMCONFIGURATIONREG2_RXSCFG54_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MASK) +#define TAS2562_TDMCONFIGURATIONREG2_RXSCFG54_MONO_I2C \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_I2C) +#define TAS2562_TDMCONFIGURATIONREG2_RXSCFG54_MONO_LEFT \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_LEFT) +#define TAS2562_TDMCONFIGURATIONREG2_RXSCFG54_MONO_RIGHT \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_RIGHT) +#define TAS2562_TDMCONFIGURATIONREG2_RXSCFG54_STEREO_DOWNMIX \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_STEREO_DOWNMIX) +#define TAS2562_TDMCONFIGURATIONREG2_RXWLEN32_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_MASK) +#define TAS2562_TDMCONFIGURATIONREG2_RXWLEN32_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_16BITS) +#define TAS2562_TDMCONFIGURATIONREG2_RXWLEN32_20BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_20BITS) +#define TAS2562_TDMCONFIGURATIONREG2_RXWLEN32_24BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_24BITS) +#define TAS2562_TDMCONFIGURATIONREG2_RXWLEN32_32BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_32BITS) +#define TAS2562_TDMCONFIGURATIONREG2_RXSLEN10_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_MASK) +#define TAS2562_TDMCONFIGURATIONREG2_RXSLEN10_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_16BITS) +#define TAS2562_TDMCONFIGURATIONREG2_RXSLEN10_24BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_24BITS) +#define TAS2562_TDMCONFIGURATIONREG2_RXSLEN10_32BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_32BITS) + +/* TDM Configuration Reg3 */ +#define TAS2562_TDMCONFIGURATIONREG3 TAS256X_REG(0x0, 0x0, 0x09) +#define TAS2562_TDMCONFIGURATIONREG3_RXSLOTRIGHT74_MASK (0xf << 4) +#define TAS2562_TDMCONFIGURATIONREG3_RXSLOTLeft30_Mask (0xf << 0) + +/* TDM Configuration Reg4 */ +#define TAS2562_TDMConfigurationReg4 (TAS256X_TDMConfigurationReg4) +#define TAS2562_TDMCONFIGURATIONREG4_TXKEEPER_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_MASK) +#define TAS2562_TDMCONFIGURATIONREG4_TXKEEPER_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_DISABLE) +#define TAS2562_TDMCONFIGURATIONREG4_TXKEEPER_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_ENABLE) +#define TAS2562_TDMCONFIGURATIONREG4_TXFILL_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXFILL_MASK) +#define TAS2562_TDMCONFIGURATIONREG4_TXFILL_TRANSMIT0 \ + (TAS256X_TDMCONFIGURATIONREG4_TXFILL_TRANSMIT0) +#define TAS2562_TDMCONFIGURATIONREG4_TXFILL_TRANSMITHIZ \ + (TAS256X_TDMCONFIGURATIONREG4_TXFILL_TRANSMITHIZ) +#define TAS2562_TDMCONFIGURATIONREG4_TXOFFSET31_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXOFFSET31_MASK) +#define TAS2562_TDMCONFIGURATIONREG4_TXEDGE_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXEDGE_MASK) +#define TAS2562_TDMCONFIGURATIONREG4_TXEDGE_RISING \ + (TAS256X_TDMCONFIGURATIONREG4_TXEDGE_RISING) +#define TAS2562_TDMCONFIGURATIONREG4_TXEDGE_FALLING \ + (TAS256X_TDMCONFIGURATIONREG4_TXEDGE_FALLING) + +/* TDM Configuration Reg5 */ +#define TAS2562_TDMCONFIGURATIONREG5 (TAS256X_TDMCONFIGURATIONREG5) +#define TAS2562_TDMCONFIGURATIONREG5_VSNSTX_MASK \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSTX_MASK) +#define TAS2562_TDMCONFIGURATIONREG5_VSNSTX_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSTX_DISABLE) +#define TAS2562_TDMCONFIGURATIONREG5_VSNSTX_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSTX_ENABLE) +#define TAS2562_TDMCONFIGURATIONREG5_VSNSSLOT50_MASK \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSSLOT50_MASK) + +/* TDM Configuration Reg6 */ +#define TAS2562_TDMCONFIGURATIONREG6 (TAS256X_TDMCONFIGURATIONREG6) +#define TAS2562_TDMCONFIGURATIONREG6_ISNSTX_MASK \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSTX_MASK) +#define TAS2562_TDMCONFIGURATIONREG6_ISNSTX_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSTX_DISABLE) +#define TAS2562_TDMCONFIGURATIONREG6_ISNSTX_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSTX_ENABLE) +#define TAS2562_TDMCONFIGURATIONREG6_ISNSSLOT50_MASK \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSSLOT50_MASK) + +/* TDM Configuration Reg7 */ +#define TAS2562_TDMCONFIGURATIONREG7 (TAS256X_TDMCONFIGURATIONREG7) +#define TAS2562_TDMCONFIGURATIONREG7_VBATSLEN_MASK \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_MASK) +#define TAS2562_TDMCONFIGURATIONREG7_VBATSLEN_8BITS \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_8BITS) +#define TAS2562_TDMCONFIGURATIONREG7_VBATSLEN_16BITS \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_16BITS) +#define TAS2562_TDMCONFIGURATIONREG7_VBATTX_MASK \ + (TAS256X_TDMCONFIGURATIONREG7_VBATTX_MASK) +#define TAS2562_TDMCONFIGURATIONREG7_VBATTX_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG7_VBATTX_DISABLE) +#define TAS2562_TDMCONFIGURATIONREG7_VBATTX_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG7_VBATTX_ENABLE) +#define TAS2562_TDMCONFIGURATIONREG7_VBATSLOT50_MASK \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLOT50_MASK) + +/* TDM Configuration Reg8 */ +#define TAS2562_TDMCONFIGURATIONREG8 TAS256X_REG(0x0, 0x0, 0x0E) +#define TAS2562_TDMCONFIGURATIONREG8_TEMPTX_MASK (0x1 << 6) +#define TAS2562_TDMCONFIGURATIONREG8_TEMPTX_DISABLE (0x0 << 6) +#define TAS2562_TDMCONFIGURATIONREG8_TEMPTX_ENABLE (0x1 << 6) +#define TAS2562_TDMCONFIGURATIONREG8_TEMPSLOT50_MASK (0x3f << 0) + +/* TDM Configuration Reg9 */ +#define TAS2562_TDMCONFIGURATIONREG9 TAS256X_REG(0x0, 0x0, 0x0F) +#define TAS2562_TDMCONFIGURATIONREG9_GAINTX_MASK (0x1 << 6) +#define TAS2562_TDMCONFIGURATIONREG9_GAINTX_DISABLE (0x0 << 6) +#define TAS2562_TDMCONFIGURATIONREG9_GAINTX_ENABLE (0x1 << 6) +#define TAS2562_TDMCONFIGURATIONREG9_GAINSLOT50_MASK (0x3f << 0) + +/* Limiter Configuration Reg0 */ +#define TAS2562_LIMITERCONFIGURATIONREG0 TAS256X_REG(0x0, 0x0, 0x12) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKST54_MASK (0x3 << 4) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKST54_1 (0x2 << 4) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKST54_2 (0x3 << 4) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKST54_0_25 (0x0 << 4) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKST54_0_5 (0x1 << 4) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_MASK (0x7 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_5 (0x0 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_10 (0x1 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_20 (0x2 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_40 (0x3 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_80 (0x4 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_160 (0x5 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_320 (0x6 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMATKRT31_640 (0x7 << 1) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMEN_MASK (0x1 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMEN_DISABLED (0x0 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG0_LIMEN_ENABLED (0x1 << 0) + +/* Limiter Configuration Reg1 */ +#define TAS2562_LIMITERCONFIGURATIONREG1 TAS256X_REG(0x0, 0x0, 0x13) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSST76_MASK (0x3 << 6) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSST76_1 (0x2 << 6) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSST76_2 (0x3 << 6) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSST76_0_25 (0x0 << 6) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSST76_0_5 (0x1 << 6) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_MASK (0x7 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_10 (0x0 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_50 (0x1 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_100 (0x2 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_250 (0x3 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_500 (0x4 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_750 (0x5 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_1000 (0x6 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMRLSRT53_1500 (0x7 << 3) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_MASK (0x7 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_0 (0x0 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_10 (0x1 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_25 (0x2 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_50 (0x3 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_100 (0x4 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_250 (0x5 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_500 (0x6 << 0) +#define TAS2562_LIMITERCONFIGURATIONREG1_LIMHLDTM20_1000 (0x7 << 0) + +/* Brown Out Prevention Reg0 */ +#define TAS2562_BROWNOUTPREVENTIONREG0 TAS256X_REG(0x0, 0x0, 0x14) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPSDEN_MASK (0x1 << 4) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPSDEN_DISABLED (0x0 << 4) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPSDEN_ENABLED (0x1 << 4) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPHLDCLR_MASK (0x1 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPHLDCLR_DONTCLEAR (0x0 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPHLDCLR_CLEAR (0x1 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPINFHLD_MASK (0x1 << 2) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPINFHLD_USEHOLDTIME (0x0 << 2) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPINFHLD_HOLDUNTILCLEARED (0x1 << 2) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPMUTE_MASK (0x1 << 1) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPMUTE_DONOTMUTE (0x0 << 1) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPMUTE_MUTE (0x1 << 1) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPEN_MASK (0x1 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPEN_DISABLED (0x0 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG0_BOPEN_ENABLED (0x1 << 0) + +/* Brown Out Prevention Reg1 */ +#define TAS2562_BROWNOUTPREVENTIONREG1 TAS256X_REG(0x0, 0x0, 0x15) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_MASK (0x7 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_1 (0x0 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_2 (0x1 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_4 (0x2 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_8 (0x3 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_16 (0x4 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_32 (0x5 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_64 (0x6 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKRT75_128 (0x7 << 5) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKST43_MASK (0x3 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKST43_1 (0x1 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKST43_2 (0x3 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKST43_0_5 (0x0 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPATKST43_1_5 (0x2 << 3) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_MASK (0x7 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_0 (0x0 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_10 (0x1 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_25 (0x2 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_50 (0x3 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_100 (0x4 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_250 (0x5 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_500 (0x6 << 0) +#define TAS2562_BROWNOUTPREVENTIONREG1_BOPHLDTM20_1000 (0x7 << 0) + +/* Interrupt Mask Reg0 */ +#define TAS2562_INTERRUPTMASKREG0 (TAS256X_INTERRUPTMASKREG0) +#define TAS2562_INTERRUPTMASKREG0_LIMMUTEINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_LIMMUTEINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_LIMMUTEINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_LIMINFHLDINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_LIMINFHLDINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_LIMINFHLDINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_LIMMAXATNINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_LIMMAXATNINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_LIMMAXATNINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_OCEINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_OCEINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_OCEINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_OCEINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_OCEINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_OCEINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_OTEINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_OTEINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG0_OTEINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_OTEINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG0_OTEINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_OTEINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG0_DISABLE (TAS256X_INTERRUPTMASKREG0_DISABLE) + +/* Interrupt Mask Reg1 */ +#define TAS2562_INTERRUPTMASKREG1 (TAS256X_INTERRUPTMASKREG1) +#define TAS2562_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG1_CRCINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_CRCINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG1_CRCINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_CRCINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG1_CRCINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_CRCINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG1_VBATOVLOINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG1_VBATOVLOINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG1_VBATOVLOINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG1_VBATUVLOINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG1_VBATUVLOINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG1_VBATUVLOINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_MASK) +#define TAS2562_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_UNMASK) +#define TAS2562_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_DISABLE) +#define TAS2562_INTERRUPTMASKREG1_DISABLE (TAS256X_INTERRUPTMASKREG1_DISABLE) + +/* Interrupt Mask Reg2 */ +#define TAS2562_INTERRUPTMASKREG2 TAS256X_REG(0x0, 0x0, 0x1C) +#define TAS2562_INTERRUPTMASKREG2_DACLKINTMASK_MASK (0x1 << 7) +#define TAS2562_INTERRUPTMASKREG2_DACLKINTMASK_UNMASK (0x0 << 7) +#define TAS2562_INTERRUPTMASKREG2_DACLKINTMASK_DISABLE (0x1 << 7) +#define TAS2562_INTERRUPTMASKREG2_BSTCLKINTMASK_MASK (0x1 << 6) +#define TAS2562_INTERRUPTMASKREG2_BSTCLKINTMASK_UNMASK (0x0 << 6) +#define TAS2562_INTERRUPTMASKREG2_BSTCLKINTMASK_DISABLE (0x1 << 6) +#define TAS2562_INTERRUPTMASKREG2_VBATPORCLKINTMASK_MASK (0x1 << 5) +#define TAS2562_INTERRUPTMASKREG2_VBATPORCLKINTMASK_UNMASK (0x0 << 5) +#define TAS2562_INTERRUPTMASKREG2_VBATPORCLKINTMASK_DISABLE (0x1 << 5) +#define TAS2562_INTERRUPTMASKREG2_PLLOCKINTMASK_MASK (0x1 << 4) +#define TAS2562_INTERRUPTMASKREG2_PLLOCKINTMASK_UNMASK (0x0 << 4) +#define TAS2562_INTERRUPTMASKREG2_PLLOCKINTMASK_DISABLE (0x1 << 4) +#define TAS2562_INTERRUPTMASKREG2_DCDETECTINTMASK_MASK (0x1 << 3) +#define TAS2562_INTERRUPTMASKREG2_DCDETECTINTMASK_UNMASK (0x0 << 3) +#define TAS2562_INTERRUPTMASKREG2_DCDETECTINTMASK_DISABLE (0x1 << 3) + +/* Live-Interrupt Reg0 */ +#define TAS2562_LIVEINTERRUPTREG0 TAS256X_REG(0x0, 0x0, 0x1F) +#define TAS2562_LIVEINTERRUPTREG0_LIMMUTE_MASK (0x1 << 7) +#define TAS2562_LIVEINTERRUPTREG0_LIMMUTE_NOINTERRUPT (0x0 << 7) +#define TAS2562_LIVEINTERRUPTREG0_LIMMUTE_INTERRUPT (0x1 << 7) +#define TAS2562_LIVEINTERRUPTREG0_LIMINFHLD_MASK (0x1 << 6) +#define TAS2562_LIVEINTERRUPTREG0_LIMINFHLD_NOINTERRUPT (0x0 << 6) +#define TAS2562_LIVEINTERRUPTREG0_LIMINFHLD_INTERRUPT (0x1 << 6) +#define TAS2562_LIVEINTERRUPTREG0_LIMMAXATN_MASK (0x1 << 5) +#define TAS2562_LIVEINTERRUPTREG0_LIMMAXATN_NOINTERRUPT (0x0 << 5) +#define TAS2562_LIVEINTERRUPTREG0_LIMMAXATN_INTERRUPT (0x1 << 5) +#define TAS2562_LIVEINTERRUPTREG0_VBATLESSTHANINF_MASK (0x1 << 4) +#define TAS2562_LIVEINTERRUPTREG0_VBATLESSTHANINF_NOINTERRUPT (0x0 << 4) +#define TAS2562_LIVEINTERRUPTREG0_VBATLESSTHANINF_INTERRUPT (0x1 << 4) +#define TAS2562_LIVEINTERRUPTREG0_LIMACTIVEFLAG_MASK (0x1 << 3) +#define TAS2562_LIVEINTERRUPTREG0_LIMACTIVEFLAG_NOINTERRUPT (0x0 << 3) +#define TAS2562_LIVEINTERRUPTREG0_LIMACTIVEFLAG_INTERRUPT (0x1 << 3) +#define TAS2562_LIVEINTERRUPTREG0_TDMCLOCKERROR_MASK (0x1 << 2) +#define TAS2562_LIVEINTERRUPTREG0_TDMCLOCKERROR_NOINTERRUPT (0x0 << 2) +#define TAS2562_LIVEINTERRUPTREG0_TDMCLOCKERROR_INTERRUPT (0x1 << 2) +#define TAS2562_LIVEINTERRUPTREG0_OCEFLAG_MASK (0x1 << 1) +#define TAS2562_LIVEINTERRUPTREG0_OCEFLAG_NOINTERRUPT (0x0 << 1) +#define TAS2562_LIVEINTERRUPTREG0_OCEFLAG_INTERRUPT (0x1 << 1) +#define TAS2562_LIVEINTERRUPTREG0_OTEFLAG_MASK (0x1 << 0) +#define TAS2562_LIVEINTERRUPTREG0_OTEFLAG_NOINTERRUPT (0x0 << 0) +#define TAS2562_LIVEINTERRUPTREG0_OTEFLAG_INTERRUPT (0x1 << 0) + +/* Live-Interrupt Reg1 */ +#define TAS2562_LIVEINTERRUPTREG1 TAS256X_REG(0x0, 0x0, 0x20) +#define TAS2562_LIVEINTERRUPTREG1_DSPINTOUTPUT_MASK (0x1 << 7) +#define TAS2562_LIVEINTERRUPTREG1_DSPINTOUTPUT_NOINTERRUPT (0x0 << 7) +#define TAS2562_LIVEINTERRUPTREG1_DSPINTOUTPUT_INTERRUPT (0x1 << 7) +#define TAS2562_LIVEINTERRUPTREG1_OTPCRC_MASK (0x1 << 6) +#define TAS2562_LIVEINTERRUPTREG1_OTPCRC_NOINTERRUPT (0x0 << 6) +#define TAS2562_LIVEINTERRUPTREG1_OTPCRC_INTERRUPT (0x1 << 6) +#define TAS2562_LIVEINTERRUPTREG1_BROWNOUTFLAG_MASK (0x1 << 1) +#define TAS2562_LIVEINTERRUPTREG1_BROWNOUTFLAG_NOINTERRUPT (0x0 << 1) +#define TAS2562_LIVEINTERRUPTREG1_BROWNOUTFLAG_INTERRUPT (0x1 << 1) +#define TAS2562_LIVEINTERRUPTREG1_BROWNOUTDETECTED_MASK (0x1 << 1) +#define TAS2562_LIVEINTERRUPTREG1_BROWNOUTDETECTED_NOINTERRUPT (0x0 << 1) +#define TAS2562_LIVEINTERRUPTREG1_BROWNOUTDETECTED_INTERRUPT (0x1 << 1) + +/* Latched-Interrupt Reg0 */ +#define TAS2562_LATCHEDINTERRUPTREG0 (TAS256X_LATCHEDINTERRUPTREG0) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_INTERRUPT) + +/* Latched-Interrupt Reg1 */ +#define TAS2562_LATCHEDINTERRUPTREG1 (TAS256X_LATCHEDINTERRUPTREG1) +#define TAS2562_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_INTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_MASK) +#define TAS2562_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_NOINTERRUPT) +#define TAS2562_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_INTERRUPT) + +/* VBAT MSB */ +#define TAS2562_VBATMSB TAS256X_REG(0x0, 0x0, 0x2A) +#define TAS2562_VBATMSB_VBATMSB70_MASK (0xff << 0) + +/* VBAT LSB */ +#define TAS2562_VBATLSB TAS256X_REG(0x0, 0x0, 0x2B) +#define TAS2562_VBATLSB_VBATLSB74_MASK (0xf << 4) + +/* TEMP */ +#define TAS2562_TEMP TAS256X_REG(0x0, 0x0, 0x2C) +#define TAS2562_TEMP_TEMPMSB70_MASK (0xff << 0) + +/* Interrupt Configuration */ +#define TAS2562_INTERRUPTCONFIGURATION (TAS256X_INTERRUPTCONFIGURATION) +#define TAS2562_INTERRUPTCONFIGURATION_LTCHINTCLEAR_MASK \ + (TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR_MASK) +#define TAS2562_INTERRUPTCONFIGURATION_LTCHINTCLEAR \ + (TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR) +#define TAS2562_INTERRUPTCONFIGURATION_PININTCONFIG10_MASK \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_MASK) +#define TAS2562_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLIVEINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLIVEINTERRUPTS) +#define TAS2562_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLATCHEDINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLATCHEDINTERRUPTS) +#define TAS2562_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLIVEINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLIVEINTERRUPTS) +#define TAS2562_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLATCHEDINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLATCHEDINTERRUPTS) + +/* Digital Input Pin Pull Down */ +#define TAS2562_DIGITALINPUTPINPULLDOWN TAS256X_REG(0x0, 0x0, 0x31) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSDOUT_MASK (0x1 << 7) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSDOUT_DISABLED (0x0 << 7) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSDOUT_ENABLED (0x1 << 7) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSDIN_MASK (0x1 << 6) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSDIN_DISABLED (0x0 << 6) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSDIN_ENABLED (0x1 << 6) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNFSYNC_MASK (0x1 << 5) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNFSYNC_DISABLED (0x0 << 5) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNFSYNC_ENABLED (0x1 << 5) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSBCLK_MASK (0x1 << 4) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSBCLK_DISABLED (0x0 << 4) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNSBCLK_ENABLED (0x1 << 4) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMD0_MASK (0x1 << 3) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMD0_DISABLED (0x0 << 3) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMD0_ENABLED (0x1 << 3) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMD1_MASK (0x1 << 2) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMD1_DISABLED (0x0 << 2) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMD1_ENABLED (0x1 << 2) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMCK0_MASK (0x1 << 1) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMCK0_DISABLED (0x0 << 1) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMCK0_ENABLED (0x1 << 1) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMCK1_MASK (0x1 << 0) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMCK1_DISABLED (0x0 << 0) +#define TAS2562_DIGITALINPUTPINPULLDOWN_WKPULLDOWNPDMCK1_ENABLED (0x1 << 0) + +/* Misc IRQ */ +#define TAS2562_MISCIRQ TAS256X_REG(0x0, 0x0, 0x32) +#define TAS2562_MISCIRQ_IRQZREQD_MASK (0x1 << 7) +#define TAS2562_MISCIRQ_IRQZREQD_ACTIVEHIGH (0x0 << 7) +#define TAS2562_MISCIRQ_IRQZREQD_ACTIVELOW (0x1 << 7) +#define TAS2562_MISCIRQ_IRQZBITBANG_MASK (0x1 << 0) +#define TAS2562_MISCIRQ_IRQZBITBANG_IRQZINPUTBUF0 (0x0 << 0) +#define TAS2562_MISCIRQ_IRQZBITBANG_IRQZINPUTBUF1 (0x1 << 0) + +#define TAS2562_BOOSTCONFIGURATION2 TAS256X_REG(0x0, 0x0, 0x34) +#define TAS2562_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_MASK (0x0f << 0) +#define TAS2562_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_SHIFT 0 +#define TAS2562_BOOSTCONFIGURATION4 (TAS256X_BOOSTCONFIGURATION4) +#define TAS2562_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_MASK \ + (TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_MASK) +#define TAS2562_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_SHIFT \ + (TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_SHIFT) + +#define TAS2562_BOOSTSLOPE (TAS256X_BOOSTSLOPE) +#define TAS2562_BOOSTSLOPE_MASK (TAS256X_BOOSTSLOPE_MASK) +#define TAS2562_BOOSTSLOPE_3AV (0x1 << 2) +#define TAS2562_BOOSTSLOPE_2AV (0x2 << 2) + +/* Clock Configuration */ +#define TAS2562_CLOCKCONFIGURATION (TAS256X_CLOCKCONFIGURATION) +#define TAS2562_CLOCKCONFIGURATION_SBCLKTOFS52_MASK \ + (TAS256X_CLOCKCONFIGURATION_SBCLKTOFS52_MASK) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_16 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_16) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_24 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_24) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_32 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_32) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_48 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_48) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_64 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_64) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_96 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_96) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_128 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_128) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_192 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_192) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_256 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_256) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_384 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_384) +#define TAS2562_CLOCKCONFIGURATION_SBCLKtoFS52_512 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_512) +#define TAS2562_CLOCKCONFIGURATION_DISCLKRATEDETECT10_MASK \ + (TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_MASK) +#define TAS2562_CLOCKCONFIGURATION_DISCLKRATEDETECT10_DISABLED \ + (TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_DISABLED) +#define TAS2562_CLOCKCONFIGURATION_DISCLKRATEDETECT10_ENABLED \ + (TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_ENABLED) + +#define TAS2562_VBATFILTER (TAS256X_VBATFILTER) +#define TAS2562_CLASSHRELEASETIMER (TAS256X_CLASSHRELEASETIMER) + +#define TAS2562_BOOST_CFG4 (TAS256X_BOOST_CFG4) +#define TAS2562_BOOST_CFG4_PEAK_CURRENT_LIMIT_MASK (0xff << 0) + +#define TAS2562_ICN_THRESHOLD_REG (TAS256X_ICN_THRESHOLD_REG) +#define TAS2562_ICN_HYSTERESIS_REG (TAS256X_ICN_HYSTERESIS_REG) + +#define TAS2562_ICN_SW_REG (TAS256X_ICN_SW_REG) +#define TAS2562_ICN_SW_MASK (TAS256X_ICN_SW_MASK) +#define TAS2562_ICN_SW_ENABLE (TAS256X_ICN_SW_ENABLE) +#define TAS2562_ICN_SW_DISABLE (TAS256X_ICN_SW_DISABLE) +#define TAS2562_TESTPAGECONFIGURATION (TAS256X_TESTPAGECONFIGURATION) +#define TAS2562_CLASSDCONFIGURATION1 (TAS256X_CLASSDCONFIGURATION1) +#define TAS2562_CLASSDCONFIGURATION2 (TAS256X_CLASSDCONFIGURATION2) +#define TAS2562_CLASSDCONFIGURATION3 (TAS256X_CLASSDCONFIGURATION3) +#define TAS2562_CLASSDCONFIGURATION4 (TAS256X_CLASSDCONFIGURATION4) +#define TAS2562_EFFICIENCYCONFIGURATION (TAS256X_EFFICIENCYCONFIGURATION) + +#define TAS2562_HPF (TAS256X_HPF) +#define TAS2562_CLASSHHEADROOM (TAS256X_CLASSHHEADROOM) +#define TAS2562_CLASSHHYSTERESIS (TAS256X_CLASSHHYSTERESIS) +#define TAS2562_CLASSHMTCT (TAS256X_CLASSHMTCT) + +/* Revision and PG ID */ +#define TAS2562_REVISIONANDPGID TAS256X_REG(0x0, 0x0, 0x7D) +#define TAS2562_REVISIONANDPGID_REVISIONID74_MASK (0xf << 4) +#define TAS2562_REVISIONANDPGID_PGID30_MASK (0xf << 0) + +/* I2C Checksum */ +#define TAS2562_I2CCHECKSUM TAS256X_REG(0x0, 0x0, 0x7E) +#define TAS2562_I2CCHECKSUM_I2CCHECKSUM70_MASK (0xff << 0) + +/* Book */ +#define TAS2562_BOOK (TAS256X_BOOK) +#define TAS2562_BOOK_BOOK70_MASK (TAS256X_BOOK_BOOK70_MASK) +#endif /* __TAS2562_ */ \ No newline at end of file diff --git a/techpack/audio/asoc/codecs/tas256x/tas2564.h b/techpack/audio/asoc/codecs/tas256x/tas2564.h new file mode 100644 index 000000000000..d42707f18ed7 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas2564.h @@ -0,0 +1,718 @@ +#ifndef __TAS2564_ +#define __TAS2564_ +/* Software Reset */ +#define TAS2564_SOFTWARERESET (TAS256X_SOFTWARERESET) +#define TAS2564_SOFTWARERESET_SOFTWARERESET_MASK \ + (TAS256X_SOFTWARERESET_SOFTWARERESET_MASK) +#define TAS2564_SOFTWARERESET_SOFTWARERESET_DONTRESET \ + (TAS256X_SOFTWARERESET_SOFTWARERESET_DONTRESET) +#define TAS2564_SOFTWARERESET_SOFTWARERESET_RESET \ + (TAS256X_SOFTWARERESET_SOFTWARERESET_RESET) + +/* Power Control */ +#define TAS2564_POWERCONTROL (TAS256X_POWERCONTROL) +//NEW Beging +#define TAS2564_POWERCONTROL_VSNS2_PD_MASK (0x1 << 7) +#define TAS2564_POWERCONTROL_VSNS2_PD_ACTIVE (0x0 << 7) +#define TAS2564_POWERCONTROL_VSNS2_PD_POWEREDDOWN (0x1 << 7) +//NEW End +#define TAS2564_POWERCONTROL_ISNSPOWER_MASK \ + (TAS256X_POWERCONTROL_ISNSPOWER_MASK) +#define TAS2564_POWERCONTROL_ISNSPOWER_ACTIVE \ + (TAS256X_POWERCONTROL_ISNSPOWER_ACTIVE) +#define TAS2564_POWERCONTROL_ISNSPOWER_POWEREDDOWN \ + (TAS256X_POWERCONTROL_ISNSPOWER_POWEREDDOWN) +#define TAS2564_POWERCONTROL_VSNSPOWER_MASK \ + (TAS256X_POWERCONTROL_VSNSPOWER_MASK) +#define TAS2564_POWERCONTROL_VSNSPOWER_ACTIVE \ + (TAS256X_POWERCONTROL_VSNSPOWER_ACTIVE) +#define TAS2564_POWERCONTROL_VSNSPOWER_POWEREDDOWN \ + (TAS256X_POWERCONTROL_VSNSPOWER_POWEREDDOWN) +#define TAS2564_POWERCONTROL_OPERATIONALMODE10_MASK \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_MASK) +#define TAS2564_POWERCONTROL_OPERATIONALMODE10_ACTIVE \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_ACTIVE) +#define TAS2564_POWERCONTROL_OPERATIONALMODE10_MUTE \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_MUTE) +#define TAS2564_POWERCONTROL_OPERATIONALMODE10_SHUTDOWN \ + (TAS256X_POWERCONTROL_OPERATIONALMODE10_SHUTDOWN) + +/* Playback Configuration Reg0 */ +#define TAS2564_PLAYBACKCONFIGURATIONREG0 (TAS256X_PLAYBACKCONFIGURATIONREG0) +#define TAS2564_PLAYBACKCONFIGURATION_AMP_LEVEL_MASK (0x1F << 1) +#define TAS2564_AMP_LEVEL_16dBV (0x0D << 1) + +//NEW Begin +#define TAS2564_PLAYBACKCONFIGURATIONREG_RX_SPKR_MODE_MASK (0x1 << 7) +#define TAS2564_PLAYBACKCONFIGURATIONREG_SPKR_MODE (0x0 << 7) +#define TAS2564_PLAYBACKCONFIGURATIONREG_RX_MODE (0x1 << 7) +//NEW End +#define TAS2564_BOOSTCONFIGURATION2 TAS256X_REG(0x0, 0x0, 0x48) +#define TAS2564_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_MASK (0x1f << 3) +#define TAS2564_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_MASK_SHIFT 3 +#define TAS2564_BOOSTCONFIGURATION4 (TAS256X_BOOSTCONFIGURATION4) +#define TAS2564_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_MASK \ + (TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_MASK) +#define TAS2564_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_SHIFT \ + (TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_SHIFT) + +#define TAS2564_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_MASK \ + (TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_MASK) +#define TAS2564_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_ENABLED \ + (TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_ENABLED) +#define TAS2564_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_DISABLED \ + (TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_DISABLED) +#define TAS2564_PLAYBACKCONFIGURATIONREG0_AMPLIFIERLEVEL51_MASK (0x1f << 1) + +/* Misc Configuration Reg0 */ +#define TAS2564_MISCCONFIGURATIONREG0 (TAS256X_MISCCONFIGURATIONREG0) +#define TAS2564_MISCCONFIGURATIONREG0_CPPGRETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_MASK) +#define TAS2564_MISCCONFIGURATIONREG0_CPPGRETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_DONOTRETRY) +#define TAS2564_MISCCONFIGURATIONREG0_CPPGRETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_RETRY) +#define TAS2564_MISCCONFIGURATIONREG0_VBATPRORETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_MASK) +#define TAS2564_MISCCONFIGURATIONREG0_VBATPRORETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_DONOTRETRY) +#define TAS2564_MISCCONFIGURATIONREG0_VBATPRORETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_RETRY) +#define TAS2564_MISCCONFIGURATIONREG0_OCERETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_OCERETRY_MASK) +#define TAS2564_MISCCONFIGURATIONREG0_OCERETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OCERETRY_DONOTRETRY) +#define TAS2564_MISCCONFIGURATIONREG0_OCERETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OCERETRY_RETRY) +#define TAS2564_MISCCONFIGURATIONREG0_OTERETRY_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_OTERETRY_MASK) +#define TAS2564_MISCCONFIGURATIONREG0_OTERETRY_DONOTRETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OTERETRY_DONOTRETRY) +#define TAS2564_MISCCONFIGURATIONREG0_OTERETRY_RETRY \ + (TAS256X_MISCCONFIGURATIONREG0_OTERETRY_RETRY) +#define TAS2564_MISCCONFIGURATIONREG0_IRQZPULL_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_MASK) +#define TAS2564_MISCCONFIGURATIONREG0_IRQZPULL_DISABLED \ + (TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_DISABLED) +#define TAS2564_MISCCONFIGURATIONREG0_IRQZPULL_ENABLED \ + (TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_ENABLED) +#define TAS2564_MISCCONFIGURATIONREG0_AMPSS_MASK \ + (TAS256X_MISCCONFIGURATIONREG0_AMPSS_MASK) +#define TAS2564_MISCCONFIGURATIONREG0_AMPSS_DISABLED \ + (TAS256X_MISCCONFIGURATIONREG0_AMPSS_DISABLED) +#define TAS2564_MISCCONFIGURATIONREG0_AMPSS_ENABLED \ + (TAS256X_MISCCONFIGURATIONREG0_AMPSS_ENABLED) + +/* TDM Configuration Reg0 */ +#define TAS2564_TDMCONFIGURATIONREG0 (TAS256X_TDMCONFIGURATIONREG0) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ) +#define TAS2564_TDMCONFIGURATIONREG0_DETECTSAMPRATE_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_MASK) +#define TAS2564_TDMCONFIGURATIONREG0_DETECTSAMPRATE_DISABLED \ + (TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_DISABLED) +#define TAS2564_TDMCONFIGURATIONREG0_DETECTSAMPRATE_ENABLED \ + (TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_ENABLED) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATE31_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATE31_14_7_16KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_14_7_16KHZ) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATE31_44_1_48KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_44_1_48KHZ) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATE31_88_2_96KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_88_2_96KHZ) +#define TAS2564_TDMCONFIGURATIONREG0_SAMPRATE31_176_4_192KHZ \ + (TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_176_4_192KHZ) +#define TAS2564_TDMCONFIGURATIONREG0_FRAMESTART_MASK \ + (TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_MASK) +#define TAS2564_TDMCONFIGURATIONREG0_FRAMESTART_LOWTOHIGH \ + (TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_LOWTOHIGH) +#define TAS2564_TDMCONFIGURATIONREG0_FRAMESTART_HIGHTOLOW \ + (TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_HIGHTOLOW) + +/* TDM Configuration Reg1 */ +#define TAS2564_TDMCONFIGURATIONREG1 (TAS256X_TDMCONFIGURATIONREG1) +#define TAS2564_TDMCONFIGURATIONREG1_RXJUSTIFY_MASK \ + (TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_MASK) +#define TAS2564_TDMCONFIGURATIONREG1_RXJUSTIFY_LEFT \ + (TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_LEFT) +#define TAS2564_TDMCONFIGURATIONREG1_RXJUSTIFY_RIGHT \ + (TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_RIGHT) +#define TAS2564_TDMCONFIGURATIONREG1_RXOFFSET51_MASK \ + (TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_MASK) +#define TAS2564_TDMCONFIGURATIONREG1_RXOFFSET51_SHIFT \ + (TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_SHIFT) +#define TAS2564_TDMCONFIGURATIONREG1_RXEDGE_MASK \ + (TAS256X_TDMCONFIGURATIONREG1_RXEDGE_MASK) +#define TAS2564_TDMCONFIGURATIONREG1_RXEDGE_RISING \ + (TAS256X_TDMCONFIGURATIONREG1_RXEDGE_RISING) +#define TAS2564_TDMCONFIGURATIONREG1_RXEDGE_FALLING \ + (TAS256X_TDMCONFIGURATIONREG1_RXEDGE_FALLING) + +/* TDM Configuration Reg2 */ +#define TAS2564_TDMCONFIGURATIONREG2 (TAS256X_TDMCONFIGURATIONREG2) +#define TAS2564_TDMCONFIGURATIONREG2_IVLEN76_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK) +#define TAS2564_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS) +#define TAS2564_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS) +#define TAS2564_TDMCONFIGURATIONREG2_IVLENCFG76_8BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_8BITS) +#define TAS2564_TDMCONFIGURATIONREG2_IVMONLEN76_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_MASK) +#define TAS2564_TDMCONFIGURATIONREG2_IVMONLEN76_8BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_8BITS) +#define TAS2564_TDMCONFIGURATIONREG2_IVMONLEN76_12BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_12BITS) +#define TAS2564_TDMCONFIGURATIONREG2_IVMONLEN76_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_16BITS) +#define TAS2564_TDMCONFIGURATIONREG2_RXSCFG54_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MASK) +#define TAS2564_TDMCONFIGURATIONREG2_RXSCFG54_MONO_I2C \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_I2C) +#define TAS2564_TDMCONFIGURATIONREG2_RXSCFG54_MONO_LEFT \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_LEFT) +#define TAS2564_TDMCONFIGURATIONREG2_RXSCFG54_MONO_RIGHT \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_RIGHT) +#define TAS2564_TDMCONFIGURATIONREG2_RXSCFG54_STEREO_DOWNMIX \ + (TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_STEREO_DOWNMIX) +#define TAS2564_TDMCONFIGURATIONREG2_RXWLEN32_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_MASK) +#define TAS2564_TDMCONFIGURATIONREG2_RXWLEN32_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_16BITS) +#define TAS2564_TDMCONFIGURATIONREG2_RXWLEN32_20BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_20BITS) +#define TAS2564_TDMCONFIGURATIONREG2_RXWLEN32_24BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_24BITS) +#define TAS2564_TDMCONFIGURATIONREG2_RXWLEN32_32BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_32BITS) +#define TAS2564_TDMCONFIGURATIONREG2_RXSLEN10_MASK \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_MASK) +#define TAS2564_TDMCONFIGURATIONREG2_RXSLEN10_16BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_16BITS) +#define TAS2564_TDMCONFIGURATIONREG2_RXSLEN10_24BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_24BITS) +#define TAS2564_TDMCONFIGURATIONREG2_RXSLEN10_32BITS \ + (TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_32BITS) + +/* TDM Configuration Reg3 */ +#define TAS2564_TDMCONFIGURATIONREG3 TAS256X_REG(0x0, 0x0, 0x09) +#define TAS2564_TDMCONFIGURATIONREG3_RXSLOTRIGHT74_MASK (0xf << 4) +#define TAS2564_TDMCONFIGURATIONREG3_RXSLOTLeft30_Mask (0xf << 0) + +/* TDM Configuration Reg4 */ +#define TAS2564_TDMConfigurationReg4 (TAS256X_TDMConfigurationReg4) +#define TAS2564_TDMCONFIGURATIONREG4_TXKEEPER_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_MASK) +#define TAS2564_TDMCONFIGURATIONREG4_TXKEEPER_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_DISABLE) +#define TAS2564_TDMCONFIGURATIONREG4_TXKEEPER_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_ENABLE) +#define TAS2564_TDMCONFIGURATIONREG4_TXFILL_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXFILL_MASK) +#define TAS2564_TDMCONFIGURATIONREG4_TXFILL_TRANSMIT0 \ + (TAS256X_TDMCONFIGURATIONREG4_TXFILL_TRANSMIT0) +#define TAS2564_TDMCONFIGURATIONREG4_TXFILL_TRANSMITHIZ \ + (TAS256X_TDMCONFIGURATIONREG4_TXFILL_TRANSMITHIZ) +#define TAS2564_TDMCONFIGURATIONREG4_TXOFFSET31_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXOFFSET31_MASK) +#define TAS2564_TDMCONFIGURATIONREG4_TXEDGE_MASK \ + (TAS256X_TDMCONFIGURATIONREG4_TXEDGE_MASK) +#define TAS2564_TDMCONFIGURATIONREG4_TXEDGE_RISING \ + (TAS256X_TDMCONFIGURATIONREG4_TXEDGE_RISING) +#define TAS2564_TDMCONFIGURATIONREG4_TXEDGE_FALLING \ + (TAS256X_TDMCONFIGURATIONREG4_TXEDGE_FALLING) + +/* TDM Configuration Reg5 */ +#define TAS2564_TDMCONFIGURATIONREG5 (TAS256X_TDMCONFIGURATIONREG5) +#define TAS2564_TDMCONFIGURATIONREG5_VSNSTX_MASK \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSTX_MASK) +#define TAS2564_TDMCONFIGURATIONREG5_VSNSTX_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSTX_DISABLE) +#define TAS2564_TDMCONFIGURATIONREG5_VSNSTX_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSTX_ENABLE) +#define TAS2564_TDMCONFIGURATIONREG5_VSNSSLOT50_MASK \ + (TAS256X_TDMCONFIGURATIONREG5_VSNSSLOT50_MASK) + +/* TDM Configuration Reg6 */ +#define TAS2564_TDMCONFIGURATIONREG6 (TAS256X_TDMCONFIGURATIONREG6) +#define TAS2564_TDMCONFIGURATIONREG6_ISNSTX_MASK \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSTX_MASK) +#define TAS2564_TDMCONFIGURATIONREG6_ISNSTX_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSTX_DISABLE) +#define TAS2564_TDMCONFIGURATIONREG6_ISNSTX_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSTX_ENABLE) +#define TAS2564_TDMCONFIGURATIONREG6_ISNSSLOT50_MASK \ + (TAS256X_TDMCONFIGURATIONREG6_ISNSSLOT50_MASK) + +/* TDM Configuration Reg7 */ +#define TAS2564_TDMCONFIGURATIONREG7 (TAS256X_TDMCONFIGURATIONREG7) +#define TAS2564_TDMCONFIGURATIONREG7_VBATSLEN_MASK \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_MASK) +#define TAS2564_TDMCONFIGURATIONREG7_VBATSLEN_8BITS \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_8BITS) +#define TAS2564_TDMCONFIGURATIONREG7_VBATSLEN_16BITS \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_16BITS) +#define TAS2564_TDMCONFIGURATIONREG7_VBATTX_MASK \ + (TAS256X_TDMCONFIGURATIONREG7_VBATTX_MASK) +#define TAS2564_TDMCONFIGURATIONREG7_VBATTX_DISABLE \ + (TAS256X_TDMCONFIGURATIONREG7_VBATTX_DISABLE) +#define TAS2564_TDMCONFIGURATIONREG7_VBATTX_ENABLE \ + (TAS256X_TDMCONFIGURATIONREG7_VBATTX_ENABLE) +#define TAS2564_TDMCONFIGURATIONREG7_VBATSLOT50_MASK \ + (TAS256X_TDMCONFIGURATIONREG7_VBATSLOT50_MASK) + +/* TDM Configuration Reg8 */ +#define TAS2564_TDMCONFIGURATIONREG8 TAS256X_REG(0x0, 0x0, 0x0E) +#define TAS2564_TDMCONFIGURATIONREG8_TEMPTX_MASK (0x1 << 6) +#define TAS2564_TDMCONFIGURATIONREG8_TEMPTX_DISABLE (0x0 << 6) +#define TAS2564_TDMCONFIGURATIONREG8_TEMPTX_ENABLE (0x1 << 6) +#define TAS2564_TDMCONFIGURATIONREG8_TEMPSLOT50_MASK (0x3f << 0) + +/* TDM Configuration Reg9 */ +#define TAS2564_TDMCONFIGURATIONREG9 TAS256X_REG(0x0, 0x0, 0x0F) +#define TAS2564_TDMCONFIGURATIONREG9_GAINTX_MASK (0x1 << 6) +#define TAS2564_TDMCONFIGURATIONREG9_GAINTX_DISABLE (0x0 << 6) +#define TAS2564_TDMCONFIGURATIONREG9_GAINTX_ENABLE (0x1 << 6) +#define TAS2564_TDMCONFIGURATIONREG9_GAINSLOT50_MASK (0x3f << 0) + +/* Limiter Configuration Reg0 */ +#define TAS2564_LIMITERCONFIGURATIONREG0 TAS256X_REG(0x0, 0x0, 0x12) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKST54_MASK (0x3 << 4) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKST54_1 (0x2 << 4) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKST54_2 (0x3 << 4) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKST54_0_25 (0x0 << 4) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKST54_0_5 (0x1 << 4) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_MASK (0x7 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_5 (0x0 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_10 (0x1 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_20 (0x2 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_40 (0x3 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_80 (0x4 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_160 (0x5 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_320 (0x6 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMATKRT31_640 (0x7 << 1) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMEN_MASK (0x1 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMEN_DISABLED (0x0 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG0_LIMEN_ENABLED (0x1 << 0) + +/* Limiter Configuration Reg1 */ +#define TAS2564_LIMITERCONFIGURATIONREG1 TAS256X_REG(0x0, 0x0, 0x13) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSST76_MASK (0x3 << 6) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSST76_1 (0x2 << 6) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSST76_2 (0x3 << 6) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSST76_0_25 (0x0 << 6) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSST76_0_5 (0x1 << 6) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_MASK (0x7 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_10 (0x0 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_50 (0x1 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_100 (0x2 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_250 (0x3 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_500 (0x4 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_750 (0x5 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_1000 (0x6 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMRLSRT53_1500 (0x7 << 3) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_MASK (0x7 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_0 (0x0 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_10 (0x1 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_25 (0x2 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_50 (0x3 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_100 (0x4 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_250 (0x5 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_500 (0x6 << 0) +#define TAS2564_LIMITERCONFIGURATIONREG1_LIMHLDTM20_1000 (0x7 << 0) + +/* Brown Out Prevention Reg0 */ +#define TAS2564_BROWNOUTPREVENTIONREG0 TAS256X_REG(0x0, 0x0, 0x14) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPSDEN_MASK (0x1 << 4) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPSDEN_DISABLED (0x0 << 4) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPSDEN_ENABLED (0x1 << 4) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPHLDCLR_MASK (0x1 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPHLDCLR_DONTCLEAR (0x0 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPHLDCLR_CLEAR (0x1 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPINFHLD_MASK (0x1 << 2) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPINFHLD_USEHOLDTIME (0x0 << 2) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPINFHLD_HOLDUNTILCLEARED (0x1 << 2) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPMUTE_MASK (0x1 << 1) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPMUTE_DONOTMUTE (0x0 << 1) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPMUTE_MUTE (0x1 << 1) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPEN_MASK (0x1 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPEN_DISABLED (0x0 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG0_BOPEN_ENABLED (0x1 << 0) + +/* Brown Out Prevention Reg1 */ +#define TAS2564_BROWNOUTPREVENTIONREG1 TAS256X_REG(0x0, 0x0, 0x15) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_MASK (0x7 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_1 (0x0 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_2 (0x1 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_4 (0x2 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_8 (0x3 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_16 (0x4 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_32 (0x5 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_64 (0x6 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKRT75_128 (0x7 << 5) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKST43_MASK (0x3 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKST43_1 (0x1 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKST43_2 (0x3 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKST43_0_5 (0x0 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPATKST43_1_5 (0x2 << 3) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_MASK (0x7 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_0 (0x0 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_10 (0x1 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_25 (0x2 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_50 (0x3 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_100 (0x4 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_250 (0x5 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_500 (0x6 << 0) +#define TAS2564_BROWNOUTPREVENTIONREG1_BOPHLDTM20_1000 (0x7 << 0) + +/* Interrupt Mask Reg0 */ +#define TAS2564_INTERRUPTMASKREG0 (TAS256X_INTERRUPTMASKREG0) +#define TAS2564_INTERRUPTMASKREG0_LIMMUTEINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_LIMMUTEINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_LIMMUTEINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_LIMINFHLDINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_LIMINFHLDINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_LIMINFHLDINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_LIMMAXATNINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_LIMMAXATNINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_LIMMAXATNINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_OCEINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_OCEINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_OCEINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_OCEINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_OCEINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_OCEINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_OTEINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG0_OTEINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG0_OTEINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG0_OTEINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG0_OTEINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG0_OTEINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG0_DISABLE (TAS256X_INTERRUPTMASKREG0_DISABLE) + +/* Interrupt Mask Reg1 */ +#define TAS2564_INTERRUPTMASKREG1 (TAS256X_INTERRUPTMASKREG1) +#define TAS2564_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG1_CRCINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_CRCINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG1_CRCINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_CRCINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG1_CRCINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_CRCINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG1_VBATOVLOINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG1_VBATOVLOINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG1_VBATOVLOINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG1_VBATUVLOINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG1_VBATUVLOINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG1_VBATUVLOINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_MASK \ + (TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_MASK) +#define TAS2564_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_UNMASK \ + (TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_UNMASK) +#define TAS2564_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_DISABLE \ + (TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_DISABLE) +#define TAS2564_INTERRUPTMASKREG1_DISABLE (TAS256X_INTERRUPTMASKREG1_DISABLE) + +/* Interrupt Mask Reg2 */ +#define TAS2564_INTERRUPTMASKREG2 TAS256X_REG(0x0, 0x0, 0x1C) +#define TAS2564_INTERRUPTMASKREG2_DACLKINTMASK_MASK (0x1 << 7) +#define TAS2564_INTERRUPTMASKREG2_DACLKINTMASK_UNMASK (0x0 << 7) +#define TAS2564_INTERRUPTMASKREG2_DACLKINTMASK_DISABLE (0x1 << 7) +#define TAS2564_INTERRUPTMASKREG2_BSTCLKINTMASK_MASK (0x1 << 6) +#define TAS2564_INTERRUPTMASKREG2_BSTCLKINTMASK_UNMASK (0x0 << 6) +#define TAS2564_INTERRUPTMASKREG2_BSTCLKINTMASK_DISABLE (0x1 << 6) +#define TAS2564_INTERRUPTMASKREG2_VBATPORCLKINTMASK_MASK (0x1 << 5) +#define TAS2564_INTERRUPTMASKREG2_VBATPORCLKINTMASK_UNMASK (0x0 << 5) +#define TAS2564_INTERRUPTMASKREG2_VBATPORCLKINTMASK_DISABLE (0x1 << 5) +#define TAS2564_INTERRUPTMASKREG2_PLLOCKINTMASK_MASK (0x1 << 4) +#define TAS2564_INTERRUPTMASKREG2_PLLOCKINTMASK_UNMASK (0x0 << 4) +#define TAS2564_INTERRUPTMASKREG2_PLLOCKINTMASK_DISABLE (0x1 << 4) +#define TAS2564_INTERRUPTMASKREG2_DCDETECTINTMASK_MASK (0x1 << 3) +#define TAS2564_INTERRUPTMASKREG2_DCDETECTINTMASK_UNMASK (0x0 << 3) +#define TAS2564_INTERRUPTMASKREG2_DCDETECTINTMASK_DISABLE (0x1 << 3) + +//NEW Begin +/* Interrupt Mask Reg4 */ +#define TAS2564_INTERRUPTMASKREG4 TAS256X_REG(0x0, 0x0, 0x1E) +#define TAS2564_INTERRUPTMASKREG4_DSP_DC_DETECT_FLAG_MASK (0x1 << 7) +#define TAS2564_INTERRUPTMASKREG4_DSP_DC_DETECT_FLAG_UNMASK (0x0 << 7) +#define TAS2564_INTERRUPTMASKREG4_DSP_DC_DETECT_FLAG_DISABLE (0x1 << 7) +//NEW End + +/* Latched-Interrupt Reg0 */ +#define TAS2564_LATCHEDINTERRUPTREG0 (TAS256X_LATCHEDINTERRUPTREG0) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_INTERRUPT) + +/* Latched-Interrupt Reg1 */ +#define TAS2564_LATCHEDINTERRUPTREG1 (TAS256X_LATCHEDINTERRUPTREG1) +#define TAS2564_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_INTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_MASK \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_MASK) +#define TAS2564_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_NOINTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_NOINTERRUPT) +#define TAS2564_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_INTERRUPT \ + (TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_INTERRUPT) + +//NEW Begin +/* Latched-Interrupt Reg4 */ +#define TAS2564_LATCHEDINTERRUPTREG4 TAS256X_REG(0x0, 0x0, 0x28) +#define TAS2564_LATCHEDINTERRUPTREG4_DSP_DC_DETECT_FLAG_MASK (0x1 << 7) +#define TAS2564_LATCHEDINTERRUPTREG4_DSP_DC_DETECT_FLAG_UNMASK (0x0 << 7) +#define TAS2564_LATCHEDINTERRUPTREG4_DSP_DC_DETECT_FLAG_DISABLE (0x1 << 7) +//NEW End + +/* VBAT MSB */ +#define TAS2564_VBATMSB TAS256X_REG(0x0, 0x0, 0x2A) +#define TAS2564_VBATMSB_VBATMSB70_MASK (0xff << 0) + +/* VBAT LSB */ +#define TAS2564_VBATLSB TAS256X_REG(0x0, 0x0, 0x2B) +#define TAS2564_VBATLSB_VBATLSB74_MASK (0xf << 4) + +/* TEMP */ +#define TAS2564_TEMP TAS256X_REG(0x0, 0x0, 0x2C) +#define TAS2564_TEMP_TEMPMSB70_MASK (0xff << 0) + +/* Interrupt Configuration */ +#define TAS2564_INTERRUPTCONFIGURATION (TAS256X_INTERRUPTCONFIGURATION) +#define TAS2564_INTERRUPTCONFIGURATION_LTCHINTCLEAR_MASK \ + (TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR_MASK) +#define TAS2564_INTERRUPTCONFIGURATION_LTCHINTCLEAR \ + (TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR) +#define TAS2564_INTERRUPTCONFIGURATION_PININTCONFIG10_MASK \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_MASK) +#define TAS2564_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLIVEINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLIVEINTERRUPTS) +#define TAS2564_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLATCHEDINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLATCHEDINTERRUPTS) +#define TAS2564_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLIVEINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLIVEINTERRUPTS) +#define TAS2564_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLATCHEDINTERRUPTS \ + (TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLATCHEDINTERRUPTS) + +/* Digital Input Pin Pull Down */ +//NEW Begin +#define TAS2564_DIGITALINPUTPINPULLDOWN TAS256X_REG(0x0, 0x0, 0x31) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_AD1_MASK (0x1 << 5) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_AD1_DISABLED (0x0 << 5) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_AD1_ENABLED (0x1 << 5) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_AD0_MASK (0x1 << 4) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_AD0_DISABLED (0x0 << 4) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_AD0_ENABLED (0x1 << 4) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SDOUT_MASK (0x1 << 3) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SDOUT_DISABLED (0x0 << 3) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SDOUT_ENABLED (0x1 << 3) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SDIN_MASK (0x1 << 2) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SDIN_DISABLED (0x0 << 2) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SDIN_ENABLED (0x1 << 2) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_FSYNC_MASK (0x1 << 1) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_FSYNC_DISABLED (0x0 << 1) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_FSYNC_ENABLED (0x1 << 1) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SBCLK_MASK (0x1 << 0) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SBCLK_DISABLED (0x0 << 0) +#define TAS2564_DIGITALINPUTPINPULLDOWN_WKPULLDOWN_SBCLK_ENABLED (0x1 << 0) +//NEW End + +/* Misc IRQ */ +#define TAS2564_MISCIRQ TAS256X_REG(0x0, 0x0, 0x32) +#define TAS2564_MISCIRQ_IRQZREQD_MASK (0x1 << 7) +#define TAS2564_MISCIRQ_IRQZREQD_ACTIVEHIGH (0x0 << 7) +#define TAS2564_MISCIRQ_IRQZREQD_ACTIVELOW (0x1 << 7) +#define TAS2564_MISCIRQ_IRQZBITBANG_MASK (0x1 << 0) +#define TAS2564_MISCIRQ_IRQZBITBANG_IRQZINPUTBUF0 (0x0 << 0) +#define TAS2564_MISCIRQ_IRQZBITBANG_IRQZINPUTBUF1 (0x1 << 0) + +#define TAS2564_BOOSTSLOPE (TAS256X_BOOSTSLOPE) +#define TAS2564_BOOSTSLOPE_MASK (TAS256X_BOOSTSLOPE_MASK) +#define TAS2564_BOOSTSLOPE_3DOT67AV (0x1 << 2) +#define TAS2564_BOOSTSLOPE_2DOT93AV (0x2 << 2) + +/* Clock Configuration */ +#define TAS2564_CLOCKCONFIGURATION (TAS256X_CLOCKCONFIGURATION) +#define TAS2564_CLOCKCONFIGURATION_SBCLKTOFS52_MASK \ + (TAS256X_CLOCKCONFIGURATION_SBCLKTOFS52_MASK) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_16 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_16) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_24 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_24) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_32 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_32) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_48 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_48) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_64 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_64) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_96 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_96) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_128 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_128) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_192 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_192) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_256 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_256) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_384 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_384) +#define TAS2564_CLOCKCONFIGURATION_SBCLKtoFS52_512 \ + (TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_512) +#define TAS2564_CLOCKCONFIGURATION_DISCLKRATEDETECT10_MASK \ + (TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_MASK) +#define TAS2564_CLOCKCONFIGURATION_DISCLKRATEDETECT10_DISABLED \ + (TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_DISABLED) +#define TAS2564_CLOCKCONFIGURATION_DISCLKRATEDETECT10_ENABLED \ + (TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_ENABLED) + +#define TAS2564_VBATFILTER (TAS256X_VBATFILTER) +#define TAS2564_CLASSHRELEASETIMER (TAS256X_CLASSHRELEASETIMER) + +#define TAS2564_BOOST_CFG4 (TAS256X_BOOST_CFG4) +#define TAS2564_BOOST_CFG4_PEAK_CURRENT_LIMIT_MASK (0x3f << 0) + +#define TAS2564_BOOST_CFG5 TAS256X_REG(0x0, 0x0, 0x48) +#define TAS2564_BOOST_CFG5_BOOSTMAXVOLTAGE_MASK (0x1f << 3) +#define TAS2564_BOOST_CFG5_BOOSTMAXVOLTAGE_6V (0x7 << 3) + +#define TAS2564_ICN_THRESHOLD_REG (TAS256X_ICN_THRESHOLD_REG) +#define TAS2564_ICN_HYSTERESIS_REG (TAS256X_ICN_HYSTERESIS_REG) + +#define TAS2564_ICN_SW_REG (TAS256X_ICN_SW_REG) +#define TAS2564_ICN_SW_MASK (TAS256X_ICN_SW_MASK) +#define TAS2564_ICN_SW_ENABLE (TAS256X_ICN_SW_ENABLE) +#define TAS2564_ICN_SW_DISABLE (TAS256X_ICN_SW_DISABLE) +#define TAS2564_TESTPAGECONFIGURATION (TAS256X_TESTPAGECONFIGURATION) +#define TAS2564_CLASSDCONFIGURATION1 (TAS256X_CLASSDCONFIGURATION1) +#define TAS2564_CLASSDCONFIGURATION2 (TAS256X_CLASSDCONFIGURATION2) +#define TAS2564_CLASSDCONFIGURATION3 (TAS256X_CLASSDCONFIGURATION3) +#define TAS2564_CLASSDCONFIGURATION4 (TAS256X_CLASSDCONFIGURATION4) +#define TAS2564_EFFICIENCYCONFIGURATION (TAS256X_EFFICIENCYCONFIGURATION) + +#define TAS2564_HPF (TAS256X_HPF) +#define TAS2564_CLASSHHEADROOM (TAS256X_CLASSHHEADROOM) +#define TAS2564_CLASSHHYSTERESIS (TAS256X_CLASSHHYSTERESIS) +#define TAS2564_CLASSHMTCT (TAS256X_CLASSHMTCT) + +/* Revision and PG ID */ +#define TAS2564_REVISIONANDPGID TAS256X_REG(0x0, 0x0, 0x7D) +#define TAS2564_REVISIONANDPGID_REVISIONID74_MASK (0xf << 4) +#define TAS2564_REVISIONANDPGID_PGID30_MASK (0xf << 0) + +/* I2C Checksum */ +#define TAS2564_I2CCHECKSUM TAS256X_REG(0x0, 0x0, 0x7E) +#define TAS2564_I2CCHECKSUM_I2CCHECKSUM70_MASK (0xff << 0) + +/* Book */ +#define TAS2564_BOOK (TAS256X_BOOK) +#define TAS2564_BOOK_BOOK70_MASK (TAS256X_BOOK_BOOK70_MASK) +#endif /* __TAS2564_ */ \ No newline at end of file diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x-codec.c b/techpack/audio/asoc/codecs/tas256x/tas256x-codec.c new file mode 100644 index 000000000000..b95e7e03a3ca --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas256x-codec.c @@ -0,0 +1,1956 @@ +/* + * ============================================================================= + * Copyright (c) 2016 Texas Instruments Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE.See the GNU General Public License for more details. + * + * File: + * tas256x-codec.c + * + * Description: + * ALSA SoC driver for Texas Instruments TAS256X High Performance 4W Smart + * Amplifier + * + * ============================================================================= + */ + +#ifdef CONFIG_TAS256X_CODEC +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tas256x.h" +#include "tas256x-device.h" +#ifdef CONFIG_TAS25XX_ALGO +#ifdef CONFIG_PLATFORM_EXYNOS +#include +#else +#include +#endif /*CONFIG_PLATFORM_EXYNOS*/ +#include "tas25xx-calib.h" +#endif /*CONFIG_TAS25XX_ALGO*/ + +#define TAS256X_MDELAY 0xFFFFFFFE +#define TAS256X_MSLEEP 0xFFFFFFFD +#define TAS256X_IVSENSER_ENABLE 1 +#define TAS256X_IVSENSER_DISABLE 0 +/* #define TAS2558_CODEC */ + +static char const *iv_enable_text[] = { "Off", "On" }; + +static const struct soc_enum tas256x_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(iv_enable_text), iv_enable_text), +}; +static int tas256x_set_fmt(struct tas256x_priv *p_tas256x, unsigned int fmt); +static int tas256x_system_mute_ctrl_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue); +static int tas256x_system_mute_ctrl_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue); +static int tas256x_mute_ctrl_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue); +static int tas256x_mute_ctrl_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue); + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE +static unsigned int tas256x_codec_read(struct snd_soc_component *codec, + unsigned int reg) +{ + unsigned int value = 0; + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); + int ret = 0; + + switch (reg) { + case TAS256X_LEFT_SWITCH: + value = p_tas256x->devs[0]->spk_control; + break; + case TAS256X_RIGHT_SWITCH: + value = p_tas256x->devs[1]->spk_control; + break; + case RX_SCFG_LEFT: + value = p_tas256x->devs[0]->rx_cfg; + break; + case RX_SCFG_RIGHT: + value = p_tas256x->devs[1]->rx_cfg; + break; + default: + ret = p_tas256x->read(p_tas256x, channel_left, reg, &value); + break; + } + + dev_dbg(p_tas256x->dev, "%s, reg=%d, value=%d", __func__, reg, value); + + if (ret == 0) + return value; + else + return ret; +} +#else +static unsigned int tas256x_codec_read(struct snd_soc_codec *codec, + unsigned int reg) +{ + unsigned int value = 0; + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); + + int ret = 0; + + switch (reg) { + case TAS256X_LEFT_SWITCH: + value = p_tas256x->devs[0]->spk_control; + break; + case TAS256X_RIGHT_SWITCH: + value = p_tas256x->devs[1]->spk_control; + break; + case RX_SCFG_LEFT: + value = p_tas256x->devs[0]->rx_cfg; + break; + case RX_SCFG_RIGHT: + value = p_tas256x->devs[1]->rx_cfg; + break; + default: + ret = p_tas256x->read(p_tas256x, channel_left, reg, &value); + break; + } + + dev_dbg(p_tas256x->dev, "%s, reg=%d, value=%d", __func__, reg, value); + + if (ret == 0) + return value; + else + return ret; + + return value; +} +#endif + +static int tas256xiv_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct tas256x_priv *p_tas256x = NULL; + int iv_enable = 0, n_result = 0; + + if (codec == NULL) { + pr_err("%s:codec is NULL\n", __func__); + return 0; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return 0; + } + + iv_enable = ucontrol->value.integer.value[0]; + + n_result = + tas256x_iv_sense_enable_set(p_tas256x, iv_enable, channel_both); + + pr_debug("%s: tas256x->iv_enable = %d\n", __func__, + p_tas256x->iv_enable); + + return n_result; +} + +static int tas256xiv_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct tas256x_priv *p_tas256x = NULL; + + if (codec == NULL) { + pr_err("%s:codec is NULL\n", __func__); + return 0; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return 0; + } + + ucontrol->value.integer.value[0] = + tas256x_iv_sense_enable_get(p_tas256x, channel_left); + p_tas256x->iv_enable = ucontrol->value.integer.value[0]; + + dev_info(p_tas256x->dev, "p_tas256x->iv_enable %d\n", + p_tas256x->iv_enable); + + return 0; +} + +static const struct snd_kcontrol_new tas256x_controls[] = { + SOC_ENUM_EXT("TAS256X IVSENSE ENABLE", tas256x_enum[0], tas256xiv_get, + tas256xiv_put), +}; + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE +static int tas256x_codec_write(struct snd_soc_component *codec, + unsigned int reg, unsigned int value) +{ + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); + int ret = 0; + + dev_dbg(p_tas256x->dev, "%s: %d, %d", __func__, reg, value); + + switch (reg) { + case TAS256X_LEFT_SWITCH: + p_tas256x->devs[0]->spk_control = value; + break; + case TAS256X_RIGHT_SWITCH: + p_tas256x->devs[1]->spk_control = value; + break; + case RX_SCFG_LEFT: + ret = tas256x_update_rx_cfg(p_tas256x, value, channel_left); + break; + case RX_SCFG_RIGHT: + ret = tas256x_update_rx_cfg(p_tas256x, value, channel_right); + break; + default: + ret = p_tas256x->write(p_tas256x, channel_both, reg, value); + break; + } + + return ret; +} +#else +static int tas256x_codec_write(struct snd_soc_codec *codec, unsigned int reg, + unsigned int value) +{ + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + dev_dbg(p_tas256x->dev, "%s: %d, %d", __func__, reg, value); + + switch (reg) { + case TAS256X_LEFT_SWITCH: + p_tas256x->devs[0]->spk_control = value; + break; + case TAS256X_RIGHT_SWITCH: + p_tas256x->devs[1]->spk_control = value; + break; + case RX_SCFG_LEFT: + ret = tas256x_update_rx_cfg(p_tas256x, value, channel_left); + break; + case RX_SCFG_RIGHT: + ret = tas256x_update_rx_cfg(p_tas256x, value, channel_right); + break; + default: + ret = p_tas256x->write(p_tas256x, channel_both, reg, value); + break; + } + + return ret; +} +#endif + +#ifdef CODEC_PM +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE +static int tas256x_codec_suspend(struct snd_soc_component *codec) +{ + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); + int ret = 0; + + mutex_lock(&p_tas256x->codec_lock); + + dev_dbg(p_tas256x->dev, "%s\n", __func__); + p_tas256x->runtime_suspend(p_tas256x); + + mutex_unlock(&p_tas256x->codec_lock); + return ret; +} + +static int tas256x_codec_resume(struct snd_soc_component *codec) +{ + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); + int ret = 0; + + mutex_lock(&p_tas256x->codec_lock); + + dev_dbg(p_tas256x->dev, "%s\n", __func__); + p_tas256x->runtime_resume(p_tas256x); + + mutex_unlock(&p_tas256x->codec_lock); + return ret; +} +#else +static int tas256x_codec_suspend(struct snd_soc_codec *codec) +{ + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + mutex_lock(&p_tas256x->codec_lock); + + dev_dbg(p_tas256x->dev, "%s\n", __func__); + p_tas256x->runtime_suspend(p_tas256x); + + mutex_unlock(&p_tas256x->codec_lock); + return ret; +} + +static int tas256x_codec_resume(struct snd_soc_codec *codec) +{ + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + mutex_lock(&p_tas256x->codec_lock); + + dev_dbg(p_tas256x->dev, "%s\n", __func__); + p_tas256x->runtime_resume(p_tas256x); + + mutex_unlock(&p_tas256x->codec_lock); + return ret; +} +#endif +#endif + +static int tas256x_set_power_state(struct tas256x_priv *p_tas256x, + enum channel chn, int state) +{ + int n_result = 0, i = 0; + + if ((p_tas256x->mb_mute) && (state == TAS256X_POWER_ACTIVE)) + state = TAS256X_POWER_MUTE; + dev_info(p_tas256x->dev, "set power state: %d\n", state); + + switch (state) { + case TAS256X_POWER_ACTIVE: + /* if set format was not called by asoc, then set it default */ + if (p_tas256x->mn_asi_format == 0) + p_tas256x->mn_asi_format = SND_SOC_DAIFMT_CBS_CFS | + SND_SOC_DAIFMT_IB_NF | + SND_SOC_DAIFMT_I2S; + n_result = tas256x_set_fmt(p_tas256x, p_tas256x->mn_asi_format); + if (n_result < 0) + return n_result; + tas256x_iv_sense_enable_set(p_tas256x, 1, chn); +#ifdef CONFIG_TAS25XX_ALGO + //tas25xx_send_algo_calibration(); + + /*Moved to probe*/ + /*tas25xx_set_iv_bit_fomat (p_tas256x->mn_iv_width, + *p_tas256x->mn_vbat, 1); + */ +#endif + /* Clear latched IRQ before power on */ + + tas256x_interrupt_clear(p_tas256x, chn); + + /*Mask interrupt for TDM*/ + n_result = tas256x_interrupt_enable(p_tas256x, 0 /*Disable*/, + channel_both); +#ifdef CONFIG_TAS256X_BIN_PARSER + // tas256x_select_cfg_blk(p_tas256x, 0, TAS256X_BIN_BLK_PRE_POWER_UP);//Normal + tas256x_select_cfg_blk(p_tas256x, 1, + TAS256X_BIN_BLK_PRE_POWER_UP); //Swap + dev_info(p_tas256x->dev, + "IRQ reg is: %s tas256x_select_cfg_blk %d\n", __func__, + __LINE__); + +#endif + n_result = tas256x_set_power_up(p_tas256x, chn); + + pr_info("%s: set ICN to -80dB\n", __func__); + n_result = tas256x_icn_data(p_tas256x, chn); + p_tas256x->mb_power_up = true; + p_tas256x->mn_power_state = TAS256X_POWER_ACTIVE; + schedule_delayed_work(&p_tas256x->init_work, + msecs_to_jiffies(50)); + break; + + case TAS256X_POWER_MUTE: + n_result = tas256x_set_power_mute(p_tas256x, chn); + p_tas256x->mb_power_up = true; + p_tas256x->mn_power_state = TAS256X_POWER_MUTE; + + /*Mask interrupt for TDM*/ + n_result = + tas256x_interrupt_enable(p_tas256x, 0 /*Disable*/, chn); + break; + + case TAS256X_POWER_SHUTDOWN: + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->device_id == DEVICE_TAS2564) { + if (chn & (i + 1)) { + /*Mask interrupt for TDM*/ + n_result = tas256x_interrupt_enable( + p_tas256x, 0 /*Disable*/, + i + 1); + n_result = tas256x_set_power_mute( + p_tas256x, i + 1); + n_result = tas256x_iv_sense_enable_set( + p_tas256x, 0, i + 1); + p_tas256x->mb_power_up = false; + p_tas256x->mn_power_state = + TAS256X_POWER_SHUTDOWN; + } + } else { + n_result = tas256x_set_power_shutdown(p_tas256x, + i + 1); + n_result = tas256x_iv_sense_enable_set( + p_tas256x, 0, i + 1); + p_tas256x->mb_power_up = false; + p_tas256x->mn_power_state = + TAS256X_POWER_SHUTDOWN; + /*Mask interrupt for TDM*/ + n_result = tas256x_interrupt_enable( + p_tas256x, 0 /*Disable*/, i + 1); + } + } + msleep(20); + p_tas256x->enable_irq(p_tas256x, false); +#ifdef CONFIG_TAS25XX_ALGO + //tas25xx_update_big_data(); +#endif + break; + + default: + dev_err(p_tas256x->dev, "wrong power state setting %d\n", + state); + } + + return n_result; +} + +void failsafe(struct tas256x_priv *p_tas256x) +{ + int n_result; + + dev_err(p_tas256x->dev, "%s\n", __func__); + p_tas256x->mn_err_code |= ERROR_FAILSAFE; + + if (p_tas256x->mnRestart < RESTART_MAX) { + p_tas256x->mnRestart++; + msleep(100); + dev_err(p_tas256x->dev, "I2C COMM error, restart SmartAmp.\n"); + tas256x_set_power_state(p_tas256x, channel_both, + p_tas256x->mn_power_state); + return; + } + + n_result = tas256x_set_power_shutdown(p_tas256x, channel_both); + p_tas256x->mb_power_up = false; + p_tas256x->mn_power_state = TAS256X_POWER_SHUTDOWN; + msleep(20); + /*Mask interrupt for TDM*/ + n_result = tas256x_interrupt_enable(p_tas256x, 0 /*Disable*/, + channel_both); + p_tas256x->enable_irq(p_tas256x, false); + p_tas256x->hw_reset(p_tas256x); + p_tas256x->write(p_tas256x, channel_both, TAS256X_SOFTWARERESET, + TAS256X_SOFTWARERESET_SOFTWARERESET_RESET); + udelay(1000); + /*pTAS256x->write(pTAS256x, channel_both, TAS256X_SPK_CTRL_REG, 0x04);*/ +} + +static int tas256x_dac_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + switch (event) { + case SND_SOC_DAPM_POST_PMU: + dev_info(p_tas256x->dev, "SND_SOC_DAPM_POST_PMU\n"); + break; + case SND_SOC_DAPM_PRE_PMD: + dev_info(p_tas256x->dev, "SND_SOC_DAPM_PRE_PMD\n"); + break; + } + + return 0; +} + +static const char *const tas256x_ASI1_src[] = { + "I2C offset", + "Left", + "Right", + "LeftRightDiv2", +}; + +static SOC_ENUM_SINGLE_DECL(tas2562_ASI1_src_left_enum, RX_SCFG_LEFT, 0, + tas256x_ASI1_src); +static SOC_ENUM_SINGLE_DECL(tas2562_ASI1_src_right_enum, RX_SCFG_RIGHT, 0, + tas256x_ASI1_src); + +static const struct snd_kcontrol_new dapm_switch_left = + SOC_DAPM_SINGLE("Switch", TAS256X_LEFT_SWITCH, 0, 1, 0); +static const struct snd_kcontrol_new dapm_switch_right = + SOC_DAPM_SINGLE("Switch", TAS256X_RIGHT_SWITCH, 0, 1, 0); +static const struct snd_kcontrol_new tas256x_asi1_left_mux = + SOC_DAPM_ENUM("Mux", tas2562_ASI1_src_left_enum); +static const struct snd_kcontrol_new tas256x_asi1_right_mux = + SOC_DAPM_ENUM("Mux", tas2562_ASI1_src_right_enum); + +static const struct snd_soc_dapm_widget tas256x_dapm_widgets_stereo[] = { + SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_SWITCH("TAS256X ASI Left", SND_SOC_NOPM, 0, 0, + &dapm_switch_left), + SND_SOC_DAPM_SWITCH("TAS256X ASI Right", SND_SOC_NOPM, 0, 0, + &dapm_switch_right), + SND_SOC_DAPM_MUX("TAS256X ASI1 SEL LEFT", SND_SOC_NOPM, 0, 0, + &tas256x_asi1_left_mux), + SND_SOC_DAPM_MUX("TAS256X ASI1 SEL RIGHT", SND_SOC_NOPM, 0, 0, + &tas256x_asi1_right_mux), + SND_SOC_DAPM_AIF_OUT("Voltage Sense", "ASI1 Capture", 0, SND_SOC_NOPM, + 0, 0), + SND_SOC_DAPM_AIF_OUT("Current Sense", "ASI1 Capture", 0, SND_SOC_NOPM, + 0, 0), + SND_SOC_DAPM_DAC_E("DAC1", NULL, SND_SOC_NOPM, 0, 0, tas256x_dac_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_DAC_E("DAC2", NULL, SND_SOC_NOPM, 0, 0, tas256x_dac_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_OUTPUT("OUT1"), + SND_SOC_DAPM_OUTPUT("OUT2"), + SND_SOC_DAPM_SIGGEN("VMON"), + SND_SOC_DAPM_SIGGEN("IMON") +}; + +static const struct snd_soc_dapm_route tas256x_audio_map_stereo[] = { + { "TAS256X ASI1 SEL LEFT", "Left", "ASI1" }, + { "TAS256X ASI1 SEL LEFT", "Right", "ASI1" }, + { "TAS256X ASI1 SEL LEFT", "LeftRightDiv2", "ASI1" }, + { "TAS256X ASI1 SEL RIGHT", "Left", "ASI1" }, + { "TAS256X ASI1 SEL RIGHT", "Right", "ASI1" }, + { "TAS256X ASI1 SEL RIGHT", "LeftRightDiv2", "ASI1" }, + { "DAC1", NULL, "TAS256X ASI1 SEL LEFT" }, + { "DAC2", NULL, "TAS256X ASI1 SEL RIGHT" }, + { "TAS256X ASI Left", "Switch", "DAC1" }, + { "TAS256X ASI Right", "Switch", "DAC2" }, + { "OUT1", NULL, "TAS256X ASI Left" }, + { "OUT2", NULL, "TAS256X ASI Right" }, + { "Voltage Sense", NULL, "VMON" }, + { "Current Sense", NULL, "IMON" } +}; + +static const struct snd_soc_dapm_widget tas256x_dapm_widgets_mono[] = { + SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_SWITCH("TAS256X ASI", SND_SOC_NOPM, 0, 0, + &dapm_switch_left), + SND_SOC_DAPM_MUX("TAS256X ASI1 SEL", SND_SOC_NOPM, 0, 0, + &tas256x_asi1_left_mux), + SND_SOC_DAPM_AIF_OUT("Voltage Sense", "ASI1 Capture", 1, + TAS256X_POWERCONTROL, 2, 1), + SND_SOC_DAPM_AIF_OUT("Current Sense", "ASI1 Capture", 0, + TAS256X_POWERCONTROL, 3, 1), + SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas256x_dac_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_OUTPUT("OUT"), + SND_SOC_DAPM_SIGGEN("VMON"), + SND_SOC_DAPM_SIGGEN("IMON") +}; + +static const struct snd_soc_dapm_route tas256x_audio_map_mono[] = { + { "TAS256X ASI1 SEL", "Left", "ASI1" }, + { "TAS256X ASI1 SEL", "Right", "ASI1" }, + { "TAS256X ASI1 SEL", "LeftRightDiv2", "ASI1" }, + { "DAC", NULL, "TAS256X ASI1 SEL" }, + { "TAS256X ASI", "Switch", "DAC" }, + { "OUT", NULL, "TAS256X ASI" }, + { "Voltage Sense", NULL, "VMON" }, + { "Current Sense", NULL, "IMON" } +}; + +static int tas256x_set_bitwidth(struct tas256x_priv *p_tas256x, int bitwidth, + int stream) +{ + int slot_width_tmp = 16; + + dev_info(p_tas256x->dev, "%s %d\n", __func__, bitwidth); + switch (bitwidth) { + case SNDRV_PCM_FORMAT_S16_LE: + p_tas256x->mn_ch_size = 16; + slot_width_tmp = 16; + break; + case SNDRV_PCM_FORMAT_S24_LE: + p_tas256x->mn_ch_size = 24; + slot_width_tmp = 32; + break; + case SNDRV_PCM_FORMAT_S32_LE: + p_tas256x->mn_ch_size = 32; + slot_width_tmp = 32; + break; + } + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + tas256x_rx_set_bitwidth(p_tas256x, p_tas256x->mn_ch_size); + tas256x_rx_set_slot(p_tas256x, slot_width_tmp); + } else { /*stream == SNDRV_PCM_STREAM_CAPTURE*/ + tas256x_iv_slot_config(p_tas256x); + tas256x_iv_bitwidth_config(p_tas256x); + } + + dev_info(p_tas256x->dev, "mn_ch_size: %d\n", p_tas256x->mn_ch_size); + p_tas256x->mn_pcm_format = bitwidth; + + return 0; +} + +static int tas256x_system_mute_ctrl_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + pValue->value.integer.value[0] = p_tas256x->mb_mute; + dev_dbg(p_tas256x->dev, "%s = %d\n", __func__, p_tas256x->mb_mute); + + return 0; +} + +static int tas256x_system_mute_ctrl_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + int mb_mute = pValue->value.integer.value[0]; + + dev_dbg(p_tas256x->dev, "%s = %d\n", __func__, mb_mute); + + p_tas256x->mb_mute = !!mb_mute; + + return 0; +} + +static int tas256x_mute_ctrl_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + pValue->value.integer.value[0] = p_tas256x->mb_mute; + + if ((p_tas256x->mb_power_up == true) && + (p_tas256x->mn_power_state == TAS256X_POWER_ACTIVE)) + pValue->value.integer.value[0] = 0; + else + pValue->value.integer.value[0] = 1; + + dev_dbg(p_tas256x->dev, "%s = %ld\n", __func__, + pValue->value.integer.value[0]); + + return 0; +} + +static int tas256x_mute_ctrl_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + enum channel chn = channel_left; + int mute = pValue->value.integer.value[0]; + int i = 0, chnTemp = 0; + + dev_dbg(p_tas256x->dev, "%s, %d\n", __func__, mute); + mutex_lock(&p_tas256x->codec_lock); + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->spk_control == 1) + chnTemp |= 1 << i; + } + chn = (chnTemp == 0) ? chn : (enum channel)chnTemp; + + if (mute) { + tas256x_set_power_state(p_tas256x, chn, TAS256X_POWER_MUTE); + } else { + tas256x_set_power_state(p_tas256x, chn, TAS256X_POWER_ACTIVE); + } + mutex_unlock(&p_tas256x->codec_lock); + return 0; +} + +static int tas256x_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = dai->component; + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = dai->codec; + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + /* int blr_clk_ratio; */ + int n_result = 0; + + dev_dbg(p_tas256x->dev, "%s, stream %s format: %d\n", __func__, + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? + ("Playback") : + ("Capture"), + params_format(params)); + + mutex_lock(&p_tas256x->codec_lock); + + n_result = tas256x_set_bitwidth(p_tas256x, params_format(params), + substream->stream); + if (n_result < 0) { + dev_info(p_tas256x->dev, "set bitwidth failed, %d\n", n_result); + goto ret; + } + + dev_info(p_tas256x->dev, "%s, stream %s sample rate: %d\n", __func__, + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? + ("Playback") : + ("Capture"), + params_rate(params)); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + n_result = + tas256x_set_samplerate(p_tas256x, params_rate(params)); + +ret: + if (n_result < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } + + mutex_unlock(&p_tas256x->codec_lock); + return n_result; +} + +static int tas256x_set_fmt(struct tas256x_priv *p_tas256x, unsigned int fmt) +{ + u8 tdm_rx_start_slot = 0, asi_cfg_1 = 0; + int ret = 0; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + asi_cfg_1 = 0x00; + break; + default: + dev_err(p_tas256x->dev, "ASI format master is not found\n"); + ret = -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + dev_info(p_tas256x->dev, "INV format: NBNF\n"); + asi_cfg_1 = 1; /* Rising */ + break; + case SND_SOC_DAIFMT_IB_NF: + dev_info(p_tas256x->dev, "INV format: IBNF\n"); + asi_cfg_1 = 0; /* Faling */ + break; + default: + dev_err(p_tas256x->dev, "ASI format Inverse is not found\n"); + ret = -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case (SND_SOC_DAIFMT_I2S): + tdm_rx_start_slot = 1; + break; + case (SND_SOC_DAIFMT_DSP_A): + case (SND_SOC_DAIFMT_DSP_B): + tdm_rx_start_slot = 1; + break; + case (SND_SOC_DAIFMT_LEFT_J): + tdm_rx_start_slot = 0; + break; + default: + dev_err(p_tas256x->dev, "DAI Format is not found, fmt=0x%x\n", + fmt); + ret = -EINVAL; + break; + } + + ret = tas256x_rx_set_fmt(p_tas256x, asi_cfg_1, tdm_rx_start_slot); + + p_tas256x->mn_asi_format = fmt; + + if (ret < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } + + return 0; +} + +static int tas256x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = dai->component; + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = dai->codec; + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + int ret = 0; + + dev_dbg(p_tas256x->dev, "%s, format=0x%x\n", __func__, fmt); + + return ret; +} + +static int tas256x_set_dai_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, + int slots, int slot_width) +{ + int ret = 0; +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = dai->component; + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = dai->codec; + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + dev_dbg(p_tas256x->dev, "%s, tx_mask:%d, rx_mask:%d", __func__, tx_mask, + rx_mask); + dev_dbg(p_tas256x->dev, "%s, slots:%d,slot_width:%d", __func__, slots, + slot_width); + + p_tas256x->mn_slot_width = slot_width; + + if (rx_mask) + ret = tas256x_rx_set_slot(p_tas256x, slot_width); + else + ret = tas256x_iv_slot_config(p_tas256x); + + if (ret < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } + + return ret; +} + +static int tas256x_mute_stream(struct snd_soc_dai *dai, int mute, int stream) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = dai->component; + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = dai->codec; + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + enum channel chn = channel_left; + int i = 0, chnTemp = 0; + int ret = 0; + + dev_info(p_tas256x->dev, "%s =>stream %s mute %d\n", __func__, + (stream == SNDRV_PCM_STREAM_PLAYBACK) ? ("Playback") : + ("Capture"), + mute); + mutex_lock(&p_tas256x->codec_lock); + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + if (mute) { + ret = tas256x_set_power_state(p_tas256x, channel_both, + TAS256X_POWER_SHUTDOWN); + } else { + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->spk_control == 1) + chnTemp |= 1 << i; + } + chn = (chnTemp == 0) ? chn : (enum channel)chnTemp; + ret = tas256x_set_power_state(p_tas256x, chn, + TAS256X_POWER_ACTIVE); + } + } + + mutex_unlock(&p_tas256x->codec_lock); + + if (ret < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } + + return 0; +} + +static void tas256x_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = dai->component; + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = dai->codec; + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + int n_result = 0; + int i = 0, chnTemp = 0; + enum channel chn = channel_left; + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->spk_control == 1) + chnTemp |= 1 << i; + } + chn = (chnTemp == 0) ? chn : (enum channel)chnTemp; + + dev_dbg(p_tas256x->dev, "%s, stream %s\n", __func__, + (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? + ("Playback") : + ("Capture")); + if (p_tas256x->mb_power_up == true && + substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + n_result = tas256x_set_power_state(p_tas256x, chn, + TAS256X_POWER_SHUTDOWN); +} + +static struct snd_soc_dai_ops tas256x_dai_ops = { + .hw_params = tas256x_hw_params, + .set_fmt = tas256x_set_dai_fmt, + .set_tdm_slot = tas256x_set_dai_tdm_slot, + .mute_stream = tas256x_mute_stream, + .shutdown = tas256x_shutdown, +}; + +#define TAS256X_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver tas256x_dai_driver[] = { + { + .name = "tas256x ASI1", + .id = 0, + .playback = { + .stream_name = "ASI1 Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = TAS256X_FORMATS, + }, + .capture = { + .stream_name = "ASI1 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = TAS256X_FORMATS, + }, + .ops = &tas256x_dai_ops, + .symmetric_rates = 1, + }, +}; + +static int tas256x_load_init(struct tas256x_priv *p_tas256x) +{ + int ret = 0, i; + + ret = tas256x_set_misc_config(p_tas256x, 0 /*Ignored*/, channel_both); + if (ret < 0) + goto end; + ret = tas256x_set_tx_config(p_tas256x, 0 /*Ignored*/, channel_both); + if (ret < 0) + goto end; + ret = tas256x_set_clock_config(p_tas256x, 0 /*Ignored*/, channel_both); + if (ret < 0) + goto end; + /*ICN Improve Performance*/ + ret = tas256x_icn_config(p_tas256x, 0 /*Ignored*/, channel_both); + if (ret < 0) + goto end; + /*Disable the HPF in Forward Path*/ + ret = tas256x_HPF_FF_Bypass(p_tas256x, 0 /*Ignored*/, channel_both); + if (ret < 0) + goto end; + /*Disable the HPF in Reverse Path*/ + ret = tas256x_HPF_FB_Bypass(p_tas256x, 0 /*Ignored*/, channel_both); + if (ret < 0) + goto end; + ret = tas256x_set_classH_config(p_tas256x, 0 /*Ignored*/, channel_both); + if (ret < 0) + goto end; + + /* To Overwrite the defaults */ + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->dev_ops.tas_init) + ret |= (p_tas256x->devs[i]->dev_ops.tas_init)(p_tas256x, + i + 1); + } +end: + return ret; +} + +#ifdef CONFIG_TAS256X_BIN_PARSER +static char *fw_name = "tas256x_reg.bin"; + +const char *blocktype[5] = { "COEFF", "POST_POWER_UP", "PRE_SHUTDOWN", + "PRE_POWER_UP", "POST_SHUTDOWN" }; + +static int tas256x_process_block(void *pContext, unsigned char *data, + unsigned char dev_idx, int sublocksize) +{ + struct tas256x_priv *pTAS256x = (struct tas256x_priv *)pContext; + unsigned char subblk_typ = data[1]; + int subblk_offset = 2; + enum channel chn = + (0 == dev_idx) ? channel_both : (enum channel)dev_idx; + + switch (subblk_typ) { + case TAS256X_CMD_SING_W: { + int i = 0; + unsigned short len = SMS_HTONS(data[2], data[3]); + subblk_offset += 2; + if (subblk_offset + 4 * len > sublocksize) { + dev_err(pTAS256x->dev, "Out of memory %s: %u\n", + __func__, __LINE__); + break; + } + + for (i = 0; i < len; i++) { + pTAS256x->write(pTAS256x, chn, + TAS256X_REG(data[subblk_offset], + data[subblk_offset + 1], + data[subblk_offset + 2]), + data[subblk_offset + 3]); + subblk_offset += 4; + } + } break; + case TAS256X_CMD_BURST: { + // int i = 0; + unsigned short len = SMS_HTONS(data[2], data[3]); + subblk_offset += 2; + if (subblk_offset + 4 + len > sublocksize) { + dev_err(pTAS256x->dev, "Out of memory %s: %u\n", + __func__, __LINE__); + break; + } + if (len % 4) { + dev_err(pTAS256x->dev, "Burst len is wrong\n"); + break; + } + + pTAS256x->bulk_write(pTAS256x, chn, + TAS256X_REG(data[subblk_offset], + data[subblk_offset + 1], + data[subblk_offset + 2]), + &(data[subblk_offset + 4]), len); + subblk_offset += (len + 4); + + } break; + case TAS256X_CMD_DELAY: { + unsigned short delay_time = 0; + if (subblk_offset + 2 > sublocksize) { + dev_err(pTAS256x->dev, "Out of memory %s: %u\n", + __func__, __LINE__); + break; + } + delay_time = SMS_HTONS(data[2], data[3]); + usleep_range(delay_time * 1000, delay_time * 1000); + subblk_offset += 2; + } break; + case TAS256X_CMD_FIELD_W: + if (subblk_offset + 6 > sublocksize) { + dev_err(pTAS256x->dev, "Out of memory %s: %u\n", + __func__, __LINE__); + } + pTAS256x->update_bits(pTAS256x, chn, + TAS256X_REG(data[subblk_offset + 2], + data[subblk_offset + 3], + data[subblk_offset + 4]), + data[subblk_offset + 1], + data[subblk_offset + 5]); + subblk_offset += 6; + break; + default: + break; + }; + + return subblk_offset; +} + +void tas256x_select_cfg_blk(void *pContext, int conf_no, + unsigned char block_type) +{ + struct tas256x_priv *pTAS256x = (struct tas256x_priv *)pContext; + struct tas256x_config_info **cfg_info = pTAS256x->cfg_info; + int i = 0, j = 0, k = 0; + + if (conf_no > pTAS256x->ncfgs || conf_no < 0 || NULL == cfg_info) { + dev_err(pTAS256x->dev, + "ERROR!!!conf_no shoud be in range from 0 to %u\n", + pTAS256x->ncfgs - 1); + goto EXIT; + } + for (i = 0; i < pTAS256x->ncfgs; i++) { + if (conf_no == i) { + for (j = 0; j < (int)cfg_info[i]->real_nblocks; j++) { + unsigned int length = 0, rc = 0; + if (block_type > 5 || block_type < 2) { + dev_err(pTAS256x->dev, + "ERROR!!!block_type shoud be in range from 2 to 5\n"); + goto EXIT; + } + if (block_type != + cfg_info[i]->blk_data[j]->block_type) + continue; + dev_info(pTAS256x->dev, "conf %d\n", i); + dev_info( + pTAS256x->dev, + "\tblock type:%s\t device idx = 0x%02x\n", + blocktype[cfg_info[i] + ->blk_data[j] + ->block_type - + 1], + cfg_info[i]->blk_data[j]->dev_idx); + for (k = 0; + k < + (int)cfg_info[i]->blk_data[j]->nSublocks; + k++) { + rc = tas256x_process_block( + pTAS256x, + cfg_info[i]->blk_data[j] + ->regdata + + length, + cfg_info[i] + ->blk_data[j] + ->dev_idx, + cfg_info[i]->blk_data[j] + ->block_size - + length); + length += rc; + if (cfg_info[i]->blk_data[j]->block_size < + length) { + dev_err(pTAS256x->dev, + "%s:%u:ERROR:%u %u out of memory\n", + __func__, __LINE__, + length, + cfg_info[i] + ->blk_data[j] + ->block_size); + break; + } + } + if (length != + cfg_info[i]->blk_data[j]->block_size) { + dev_err(pTAS256x->dev, + "%s:%u:ERROR: %u %u size is not same\n", + __func__, __LINE__, length, + cfg_info[i] + ->blk_data[j] + ->block_size); + } + } + } else + continue; + } +EXIT: + return; +} + +static struct tas256x_config_info * +tas256x_add_config(unsigned char *config_data, unsigned int config_size) +{ + struct tas256x_config_info *cfg_info = NULL; + int config_offset = 0, i = 0; + cfg_info = (struct tas256x_config_info *)kzalloc( + sizeof(struct tas256x_config_info), GFP_KERNEL); + if (!cfg_info) { + pr_err("%s:%u:Memory alloc failed!\n", __func__, __LINE__); + goto EXIT; + } + if (config_offset + 4 > (int)config_size) { + pr_err("%s:%u:Out of memory\n", __func__, __LINE__); + goto EXIT; + } + cfg_info->nblocks = SMS_HTONL(config_data[config_offset], + config_data[config_offset + 1], + config_data[config_offset + 2], + config_data[config_offset + 3]); + config_offset += 4; + pr_info("cfg_info->num_blocks = %u\n", cfg_info->nblocks); + cfg_info->blk_data = (struct tas256x_block_data **)kzalloc( + cfg_info->nblocks * sizeof(struct tas256x_block_data *), + GFP_KERNEL); + if (!cfg_info->blk_data) { + pr_err("%s:%u:Memory alloc failed!\n", __func__, __LINE__); + goto EXIT; + } + cfg_info->real_nblocks = 0; + for (i = 0; i < (int)cfg_info->nblocks; i++) { + if (config_offset + 12 > config_size) { + pr_err("%s:%u:Out of memory: i = %d nblocks = %u!\n", + __func__, __LINE__, i, cfg_info->nblocks); + break; + } + cfg_info->blk_data[i] = (struct tas256x_block_data *)kzalloc( + sizeof(struct tas256x_block_data), GFP_KERNEL); + if (!cfg_info->blk_data[i]) { + pr_err("%s:%u:Memory alloc failed!\n", __func__, + __LINE__); + break; + } + cfg_info->blk_data[i]->dev_idx = config_data[config_offset]; + config_offset++; + pr_info("blk_data(%d).dev_idx = 0x%02x\n", i, + cfg_info->blk_data[i]->dev_idx); + cfg_info->blk_data[i]->block_type = config_data[config_offset]; + config_offset++; + pr_info("blk_data(%d).block_type = 0x%02x\n", i, + cfg_info->blk_data[i]->block_type); + cfg_info->blk_data[i]->yram_checksum = + SMS_HTONS(config_data[config_offset], + config_data[config_offset + 1]); + config_offset += 2; + cfg_info->blk_data[i]->block_size = + SMS_HTONL(config_data[config_offset], + config_data[config_offset + 1], + config_data[config_offset + 2], + config_data[config_offset + 3]); + config_offset += 4; + pr_info("blk_data(%d).block_size = %u\n", i, + cfg_info->blk_data[i]->block_size); + cfg_info->blk_data[i]->nSublocks = + SMS_HTONL(config_data[config_offset], + config_data[config_offset + 1], + config_data[config_offset + 2], + config_data[config_offset + 3]); + pr_info("blk_data(%d).num_subblocks = %u\n", i, + cfg_info->blk_data[i]->nSublocks); + config_offset += 4; + pr_info("config_offset = %d\n", config_offset); + cfg_info->blk_data[i]->regdata = (unsigned char *)kzalloc( + cfg_info->blk_data[i]->block_size, GFP_KERNEL); + if (!cfg_info->blk_data[i]->regdata) { + pr_err("%s:%u:Memory alloc failed!\n", __func__, + __LINE__); + goto EXIT; + } + if (config_offset + cfg_info->blk_data[i]->block_size > + config_size) { + pr_err("%s:%u:Out of memory: i = %d nblocks = %u!\n", + __func__, __LINE__, i, cfg_info->nblocks); + break; + } + memcpy(cfg_info->blk_data[i]->regdata, + &config_data[config_offset], + cfg_info->blk_data[i]->block_size); + config_offset += cfg_info->blk_data[i]->block_size; + cfg_info->real_nblocks += 1; + } + +EXIT: + return cfg_info; +} + +static void tas256x_fw_ready(const struct firmware *pFW, void *pContext) +{ + struct tas256x_priv *pTAS256x = (struct tas256x_priv *)pContext; + struct tas256x_fw_hdr *fw_hdr = &(pTAS256x->fw_hdr); + struct tas256x_config_info **cfg_info = NULL; + unsigned char *buf = NULL; + int offset = 0, i = 0; + unsigned int total_config_sz = 0; + + pTAS256x->fw_state = TAS256X_DSP_FW_FAIL; + + if (unlikely(!pFW) || unlikely(!pFW->data)) { + dev_err(pTAS256x->dev, + "Failed to read %s, no side-effect on driver running\n", + fw_name); + return; + } + buf = (unsigned char *)pFW->data; +#ifdef CONFIG_TAS256X_CODEC + mutex_lock(&pTAS256x->codec_lock); +#endif +#ifdef CONFIG_TAS256X_MISC + mutex_lock(&pTAS256x->file_lock); +#endif + dev_info(pTAS256x->dev, "%s: start\n", __func__); + fw_hdr->img_sz = SMS_HTONL(buf[offset], buf[offset + 1], + buf[offset + 2], buf[offset + 3]); + offset += 4; + if (fw_hdr->img_sz != pFW->size) { + dev_err(pTAS256x->dev, "File size not match, %d %d", + (int)pFW->size, (int)fw_hdr->img_sz); + goto EXIT; + } + + fw_hdr->checksum = SMS_HTONL(buf[offset], buf[offset + 1], + buf[offset + 2], buf[offset + 3]); + offset += 4; + fw_hdr->binnary_version_num = SMS_HTONL( + buf[offset], buf[offset + 1], buf[offset + 2], buf[offset + 3]); + offset += 4; + fw_hdr->drv_fw_version = SMS_HTONL(buf[offset], buf[offset + 1], + buf[offset + 2], buf[offset + 3]); + offset += 4; + fw_hdr->timestamp = SMS_HTONL(buf[offset], buf[offset + 1], + buf[offset + 2], buf[offset + 3]); + offset += 4; + fw_hdr->plat_type = buf[offset]; + offset += 1; + fw_hdr->dev_family = buf[offset]; + offset += 1; + fw_hdr->reserve = buf[offset]; + offset += 1; + fw_hdr->ndev = buf[offset]; + offset += 1; + + dev_info(pTAS256x->dev, "ndev = %u\n", fw_hdr->ndev); + + if (offset + TAS256X_DEVICE_SUM > fw_hdr->img_sz) { + dev_err(pTAS256x->dev, "%s:%u:Out of Memory!\n", __func__, + __LINE__); + goto EXIT; + } + + for (i = 0; i < TAS256X_DEVICE_SUM; i++) { + fw_hdr->devs[i] = buf[offset]; + offset += 1; + dev_info(pTAS256x->dev, "devs[%d] = %u\n", i, fw_hdr->devs[i]); + } + fw_hdr->nconfig = SMS_HTONL(buf[offset], buf[offset + 1], + buf[offset + 2], buf[offset + 3]); + offset += 4; + dev_info(pTAS256x->dev, "nconfig = %u\n", fw_hdr->nconfig); + for (i = 0; i < TAS256X_CONFIG_SIZE; i++) { + fw_hdr->config_size[i] = + SMS_HTONL(buf[offset], buf[offset + 1], buf[offset + 2], + buf[offset + 3]); + offset += 4; + dev_info(pTAS256x->dev, "config_size[%d] = %u\n", i, + fw_hdr->config_size[i]); + total_config_sz += fw_hdr->config_size[i]; + } + dev_info(pTAS256x->dev, + "img_sz = %u total_config_sz = %u offset = %d\n", + fw_hdr->img_sz, total_config_sz, offset); + if (fw_hdr->img_sz - total_config_sz != (unsigned int)offset) { + dev_err(pTAS256x->dev, "Bin file error!\n"); + goto EXIT; + } + cfg_info = (struct tas256x_config_info **)kzalloc( + fw_hdr->nconfig * sizeof(struct tas256x_config_info *), + GFP_KERNEL); + if (!cfg_info) { + dev_err(pTAS256x->dev, "%s:%u:Memory alloc failed!\n", __func__, + __LINE__); + goto EXIT; + } + pTAS256x->cfg_info = cfg_info; + pTAS256x->ncfgs = 0; + for (i = 0; i < (int)fw_hdr->nconfig; i++) { + cfg_info[i] = tas256x_add_config(&buf[offset], + fw_hdr->config_size[i]); + if (!cfg_info[i]) { + dev_err(pTAS256x->dev, "%s:%u:Memory alloc failed!\n", + __func__, __LINE__); + break; + } + offset += (int)fw_hdr->config_size[i]; + pTAS256x->ncfgs += 1; + } + + pTAS256x->fw_state = TAS256X_DSP_FW_OK; + +EXIT: +#ifdef CONFIG_TAS256X_MISC + mutex_unlock(&pTAS256x->file_lock); +#endif +#ifdef CONFIG_TAS256X_CODEC + mutex_unlock(&pTAS256x->codec_lock); +#endif + release_firmware(pFW); + dev_info(pTAS256x->dev, "%s: Firmware init complete\n", __func__); + return; +} + +static int tas256x_load_container(struct tas256x_priv *pTAS256x) +{ + pTAS256x->fw_state = TAS256X_DSP_FW_PENDING; + return request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, fw_name, + pTAS256x->dev, GFP_KERNEL, pTAS256x, + tas256x_fw_ready); +} +static void tas256x_config_info_remove(void *pContext) +{ + struct tas256x_priv *pTAS256x = (struct tas256x_priv *)pContext; + struct tas256x_config_info **cfg_info = pTAS256x->cfg_info; + int i = 0, j = 0; + + if (cfg_info) { + for (i = 0; i < pTAS256x->ncfgs; i++) { + if (cfg_info[i]) { + for (j = 0; j < (int)cfg_info[i]->real_nblocks; + j++) { + if (cfg_info[i]->blk_data[j]->regdata) + kfree(cfg_info[i] + ->blk_data[j] + ->regdata); + if (cfg_info[i]->blk_data[j]) + kfree(cfg_info[i]->blk_data[j]); + } + if (cfg_info[i]->blk_data) + kfree(cfg_info[i]->blk_data); + kfree(cfg_info[i]); + } + } + kfree(cfg_info); + } +} +#endif + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE +static int tas256x_codec_probe(struct snd_soc_component *codec) +{ + int ret, i; + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); + + ret = snd_soc_add_component_controls(codec, tas256x_controls, + ARRAY_SIZE(tas256x_controls)); + if (ret < 0) { + pr_err("%s: add_codec_controls failed, err %d\n", __func__, + ret); + return ret; + } + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->dev_ops.tas_probe) + ret |= (p_tas256x->devs[i]->dev_ops.tas_probe)( + p_tas256x, codec, i + 1); + } + + ret = tas256x_load_init(p_tas256x); + if (ret < 0) + goto end; + ret = tas256x_iv_sense_enable_set(p_tas256x, 1, channel_both); + if (ret < 0) + goto end; +#ifdef CONFIG_TAS25XX_ALGO + tas_smartamp_add_algo_controls(codec); + /*Send IV Vbat format but don't update to algo yet*/ + tas25xx_set_iv_bit_fomat(p_tas256x->mn_iv_width, p_tas256x->mn_vbat, 0); +#endif +#ifdef CONFIG_TAS256X_BIN_PARSER + ret = tas256x_load_container(p_tas256x); + dev_info(p_tas256x->dev, "%s Bin file loading requested: %d\n", + __func__, ret); +#endif + dev_dbg(p_tas256x->dev, "%s\n", __func__); + +end: + if (ret < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } + return ret; +} +#else +static int tas256x_codec_probe(struct snd_soc_codec *codec) +{ + int ret, i; + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); + + dev_info(p_tas256x->dev, "Driver Tag: %s\n", TAS256X_DRIVER_TAG); + ret = snd_soc_add_codec_controls(codec, tas256x_controls, + ARRAY_SIZE(tas256x_controls)); + if (ret < 0) { + pr_err("%s: add_codec_controls failed, err %d\n", __func__, + ret); + return ret; + } + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->dev_ops.tas_probe) + ret |= (p_tas256x->devs[i]->dev_ops.tas_probe)( + p_tas256x, codec, i + 1); + } + + ret = tas256x_load_init(p_tas256x); + if (ret < 0) + goto end; + ret = tas256x_iv_sense_enable_set(p_tas256x, 1, channel_both); + if (ret < 0) + goto end; +#ifdef CONFIG_TAS25XX_ALGO + tas_smartamp_add_algo_controls(codec); + /*Send IV Vbat format but don't update to algo yet*/ + tas25xx_set_iv_bit_fomat(p_tas256x->mn_iv_width, p_tas256x->mn_vbat, 0); +#endif +#ifdef CONFIG_TAS256X_BIN_PARSER + ret = tas256x_load_container(p_tas256x); + dev_info(p_tas256x->dev, "%s Bin file loading requested: %d\n", + __func__, ret); +#endif + dev_dbg(p_tas256x->dev, "%s\n", __func__); + +end: + if (ret < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } + + return ret; +} +#endif + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE +static void tas256x_codec_remove(struct snd_soc_component *codec) +{ +#ifdef CONFIG_TAS256X_BIN_PARSER + struct tas2562_priv *pTAS256x = snd_soc_component_get_drvdata(codec); + tas256x_config_info_remove(pTAS256x); +#endif +} +#else +static int tas256x_codec_remove(struct snd_soc_codec *codec) +{ +#ifdef CONFIG_TAS256X_BIN_PARSER + struct tas256x_priv *pTAS256x = snd_soc_codec_get_drvdata(codec); + //struct tas2562_priv *pTAS256x = snd_soc_component_get_drvdata(codec); + tas256x_config_info_remove(pTAS256x); +#endif + return 0; +} +#endif + +static DECLARE_TLV_DB_SCALE(tas256x_digital_tlv, 1100, 50, 0); + +static const char *const icn_sw_text[] = { "Enable", "Disable" }; +static const struct soc_enum icn_sw_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(icn_sw_text), icn_sw_text), +}; +static int tas256x_get_icn_switch(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *p_u_control) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + dev_info(p_tas256x->dev, "%s, icn_sw = %ld\n", __func__, + p_u_control->value.integer.value[0]); + p_u_control->value.integer.value[0] = p_tas256x->icn_sw; + return 0; +} +static int tas256x_set_icn_switch(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *p_u_control) +{ + int ret = 0; +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + p_tas256x->icn_sw = p_u_control->value.integer.value[0]; + ret = tas256x_icn_enable(p_tas256x, p_tas256x->icn_sw, channel_both); + + return ret; +} + +static int tas256x_dac_mute_ctrl_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + pValue->value.integer.value[0] = p_tas256x->dac_mute; + + dev_dbg(p_tas256x->dev, "%s = %ld\n", __func__, + pValue->value.integer.value[0]); + + return 0; +} + +static int tas256x_dac_mute_ctrl_put(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pValue) +{ + int n_result = 0; + enum channel chn = channel_left; + int mute = pValue->value.integer.value[0]; + int i = 0, chnTemp = 0; +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_component_get_drvdata(codec); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(pKcontrol); + struct tas256x_priv *p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + dev_dbg(p_tas256x->dev, "%s, %d\n", __func__, mute); + mutex_lock(&p_tas256x->codec_lock); + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->spk_control == 1) + chnTemp |= 1 << i; + } + chn = (chnTemp == 0) ? chn : (enum channel)chnTemp; + + if (mute) + n_result = tas256x_set_power_mute(p_tas256x, chn); + else + n_result = tas256x_set_power_up(p_tas256x, chn); + + p_tas256x->dac_mute = mute; + mutex_unlock(&p_tas256x->codec_lock); + + return n_result; +} + +static const struct snd_kcontrol_new tas256x_snd_controls[] = { + SOC_SINGLE_TLV("Amp Output Level", TAS256X_PLAYBACKCONFIGURATIONREG0, 1, + 0x16, 0, tas256x_digital_tlv), + SOC_SINGLE_EXT("SmartPA System Mute", SND_SOC_NOPM, 0, 0x0001, 0, + tas256x_system_mute_ctrl_get, + tas256x_system_mute_ctrl_put), + SOC_SINGLE_EXT("SmartPA Mute", SND_SOC_NOPM, 0, 0x0001, 0, + tas256x_mute_ctrl_get, tas256x_mute_ctrl_put), + SOC_SINGLE_EXT("TAS256X DAC Mute", SND_SOC_NOPM, 0, 0x0001, 0, + tas256x_dac_mute_ctrl_get, tas256x_dac_mute_ctrl_put), + SOC_ENUM_EXT("TAS256X ICN Switch", icn_sw_enum[0], + tas256x_get_icn_switch, tas256x_set_icn_switch), +}; + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE +static const struct snd_soc_component_driver soc_codec_driver_tas256x = { + .probe = tas256x_codec_probe, + .remove = tas256x_codec_remove, + .read = tas256x_codec_read, + .write = tas256x_codec_write, +#ifdef CODEC_PM + .suspend = tas256x_codec_suspend, + .resume = tas256x_codec_resume, +#endif + .controls = tas256x_snd_controls, + .num_controls = ARRAY_SIZE(tas256x_snd_controls), + .dapm_widgets = tas256x_dapm_widgets_mono, + .num_dapm_widgets = ARRAY_SIZE(tas256x_dapm_widgets_mono), + .dapm_routes = tas256x_audio_map_stereo, + .num_dapm_routes = ARRAY_SIZE(tas256x_audio_map_stereo), +}; +#else +static struct snd_soc_codec_driver soc_codec_driver_tas256x = { + .probe = tas256x_codec_probe, + .remove = tas256x_codec_remove, + .read = tas256x_codec_read, + .write = tas256x_codec_write, +#ifdef CODEC_PM + .suspend = tas256x_codec_suspend, + .resume = tas256x_codec_resume, +#endif + .component_driver = { + .controls = tas256x_snd_controls, + .num_controls = ARRAY_SIZE(tas256x_snd_controls), + .dapm_widgets = tas256x_dapm_widgets_mono, + .num_dapm_widgets = ARRAY_SIZE(tas256x_dapm_widgets_mono), + .dapm_routes = tas256x_audio_map_mono, + .num_dapm_routes = ARRAY_SIZE(tas256x_audio_map_mono), + }, +}; +#endif + +int tas256x_register_codec(struct tas256x_priv *p_tas256x) +{ + int n_result = 0; + + dev_info(p_tas256x->dev, "%s, enter\n", __func__); + + if (p_tas256x->mn_channels == 2) { +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + soc_codec_driver_tas256x.dapm_widgets = + tas256x_dapm_widgets_stereo; + soc_codec_driver_tas256x.num_dapm_widgets = + ARRAY_SIZE(tas256x_dapm_widgets_stereo); + soc_codec_driver_tas256x.dapm_routes = tas256x_audio_map_stereo; + soc_codec_driver_tas256x.num_dapm_routes = + ARRAY_SIZE(tas256x_audio_map_stereo); +#else + soc_codec_driver_tas256x.component_driver.dapm_widgets = + tas256x_dapm_widgets_stereo; + soc_codec_driver_tas256x.component_driver.num_dapm_widgets = + ARRAY_SIZE(tas256x_dapm_widgets_stereo); + soc_codec_driver_tas256x.component_driver.dapm_routes = + tas256x_audio_map_stereo; + soc_codec_driver_tas256x.component_driver.num_dapm_routes = + ARRAY_SIZE(tas256x_audio_map_stereo); +#endif + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + n_result = devm_snd_soc_register_component( + p_tas256x->dev, &soc_codec_driver_tas256x, tas256x_dai_driver, + ARRAY_SIZE(tas256x_dai_driver)); +#else + n_result = snd_soc_register_codec(p_tas256x->dev, + &soc_codec_driver_tas256x, + tas256x_dai_driver, + ARRAY_SIZE(tas256x_dai_driver)); +#endif + return n_result; +} + +int tas256x_deregister_codec(struct tas256x_priv *p_tas256x) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + snd_soc_unregister_component(p_tas256x->dev); +#else + snd_soc_unregister_codec(p_tas256x->dev); +#endif + return 0; +} + +int tas256x_load_ctrl_values(struct tas256x_priv *p_tas256x, int ch) +{ + int n_result = 0; + + n_result |= tas256x_update_playback_volume( + p_tas256x, p_tas256x->devs[ch - 1]->dvc_pcm, ch); + + n_result |= tas256x_update_lim_max_attenuation( + p_tas256x, p_tas256x->devs[ch - 1]->lim_max_attn, ch); + + n_result |= tas256x_update_lim_max_thr( + p_tas256x, p_tas256x->devs[ch - 1]->lim_thr_max, ch); + + n_result |= tas256x_update_lim_min_thr( + p_tas256x, p_tas256x->devs[ch - 1]->lim_thr_min, ch); + + n_result |= tas256x_update_lim_inflection_point( + p_tas256x, p_tas256x->devs[ch - 1]->lim_infl_pt, ch); + + n_result |= tas256x_update_lim_slope( + p_tas256x, p_tas256x->devs[ch - 1]->lim_trk_slp, ch); + + n_result |= tas256x_update_bop_thr( + p_tas256x, p_tas256x->devs[ch - 1]->bop_thd, ch); + + n_result |= tas256x_update_bosd_thr( + p_tas256x, p_tas256x->devs[ch - 1]->bosd_thd, ch); + + n_result |= tas256x_update_boost_voltage( + p_tas256x, p_tas256x->devs[ch - 1]->bst_vltg, ch); + + n_result |= tas256x_update_current_limit( + p_tas256x, p_tas256x->devs[ch - 1]->bst_ilm, ch); + + n_result |= tas256x_update_limiter_enable( + p_tas256x, p_tas256x->devs[ch - 1]->lim_switch, ch); + + n_result |= tas256x_update_limiter_attack_rate( + p_tas256x, p_tas256x->devs[ch - 1]->lim_att_rate, ch); + + n_result |= tas256x_update_limiter_attack_step_size( + p_tas256x, p_tas256x->devs[ch - 1]->lim_att_stp_size, ch); + + n_result |= tas256x_update_limiter_release_rate( + p_tas256x, p_tas256x->devs[ch - 1]->lim_rel_rate, ch); + + n_result |= tas256x_update_limiter_release_step_size( + p_tas256x, p_tas256x->devs[ch - 1]->lim_rel_stp_size, ch); + + n_result |= tas256x_update_bop_enable( + p_tas256x, p_tas256x->devs[ch - 1]->bop_enable, ch); + + n_result |= tas256x_update_bop_mute( + p_tas256x, p_tas256x->devs[ch - 1]->bop_mute, ch); + + n_result |= tas256x_update_bop_shutdown_enable( + p_tas256x, p_tas256x->devs[ch - 1]->bosd_enable, ch); + + n_result |= tas256x_update_bop_attack_rate( + p_tas256x, p_tas256x->devs[ch - 1]->bop_att_rate, ch); + + n_result |= tas256x_update_bop_attack_step_size( + p_tas256x, p_tas256x->devs[ch - 1]->bop_att_stp_size, ch); + + n_result |= tas256x_update_bop_hold_time( + p_tas256x, p_tas256x->devs[ch - 1]->bop_hld_time, ch); + + n_result |= tas256x_update_vbat_lpf( + p_tas256x, p_tas256x->devs[ch - 1]->vbat_lpf, ch); + + n_result |= tas256x_update_rx_cfg(p_tas256x, + p_tas256x->devs[ch - 1]->rx_cfg, ch); + + /* TAS2564 Specific*/ + if (p_tas256x->devs[ch - 1]->device_id == DEVICE_TAS2564) + n_result |= tas2564_rx_mode_update( + p_tas256x, p_tas256x->devs[ch - 1]->rx_mode, ch); + + return n_result; +} + +void tas256x_load_config(struct tas256x_priv *p_tas256x) +{ + int ret = 0; + + p_tas256x->hw_reset(p_tas256x); + msleep(20); + + ret = tas56x_software_reset(p_tas256x, channel_both); + if (ret < 0) + goto end; + ret = tas256x_iv_slot_config(p_tas256x); + if (ret < 0) + goto end; + ret = tas256x_load_init(p_tas256x); + if (ret < 0) + goto end; + ret = tas256x_update_rx_cfg(p_tas256x, p_tas256x->devs[0]->rx_cfg, + channel_left); + if (ret < 0) + goto end; + ret |= tas256x_load_ctrl_values(p_tas256x, channel_left); + if (ret < 0) + goto end; + if (p_tas256x->mn_channels == 2) { + ret = tas256x_update_rx_cfg( + p_tas256x, p_tas256x->devs[1]->rx_cfg, channel_right); + if (ret < 0) + goto end; + ret |= tas256x_load_ctrl_values(p_tas256x, channel_right); + if (ret < 0) + goto end; + } + ret = tas256x_rx_set_slot(p_tas256x, p_tas256x->mn_slot_width); + if (ret < 0) + goto end; + ret = tas256x_set_fmt(p_tas256x, p_tas256x->mn_asi_format); + if (ret < 0) + goto end; + ret = tas256x_set_bitwidth(p_tas256x, p_tas256x->mn_pcm_format, + SNDRV_PCM_STREAM_PLAYBACK); + if (ret < 0) + goto end; + ret = tas256x_set_bitwidth(p_tas256x, p_tas256x->mn_pcm_format, + SNDRV_PCM_STREAM_CAPTURE); + if (ret < 0) + goto end; + ret = tas256x_set_samplerate(p_tas256x, p_tas256x->mn_sampling_rate); + if (ret < 0) + goto end; + ret = tas256x_set_power_state(p_tas256x, channel_both, + p_tas256x->mn_power_state); + if (ret < 0) + goto end; + +end: + /* power up failed, restart later */ + if (ret < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } +} + +void tas_reload(struct tas256x_priv *p_tas256x, int chn) +{ + int ret = 0; + /*To be used later*/ + (void)chn; + + p_tas256x->enable_irq(p_tas256x, false); + + ret = tas56x_software_reset(p_tas256x, channel_both); + if (ret < 0) + goto end; + ret = tas256x_load_init(p_tas256x); + if (ret < 0) + goto end; + ret |= tas256x_load_ctrl_values(p_tas256x, chn); + if (ret < 0) + goto end; + ret = tas256x_rx_set_slot(p_tas256x, p_tas256x->mn_slot_width); + if (ret < 0) + goto end; + ret = tas256x_set_fmt(p_tas256x, p_tas256x->mn_asi_format); + if (ret < 0) + goto end; + ret = tas256x_set_bitwidth(p_tas256x, p_tas256x->mn_pcm_format, + SNDRV_PCM_STREAM_PLAYBACK); + if (ret < 0) + goto end; + ret = tas256x_set_bitwidth(p_tas256x, p_tas256x->mn_pcm_format, + SNDRV_PCM_STREAM_CAPTURE); + if (ret < 0) + goto end; + ret = tas256x_set_samplerate(p_tas256x, p_tas256x->mn_sampling_rate); + if (ret < 0) + goto end; + ret = tas256x_set_power_state(p_tas256x, channel_both, + p_tas256x->mn_power_state); + if (ret < 0) + goto end; + +end: + /* power up failed, restart later */ + if (ret < 0) { + if (p_tas256x->mn_err_code & + (ERROR_DEVA_I2C_COMM | ERROR_DEVB_I2C_COMM)) + failsafe(p_tas256x); + } + + p_tas256x->enable_irq(p_tas256x, true); +} + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TAS256X ALSA SOC Smart Amplifier driver"); +MODULE_LICENSE("GPL v2"); +#endif /* CONFIG_TAS256X_CODEC */ diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x-codec.h b/techpack/audio/asoc/codecs/tas256x/tas256x-codec.h new file mode 100644 index 000000000000..a16782176815 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas256x-codec.h @@ -0,0 +1,33 @@ +/* + * ============================================================================= + * Copyright (c) 2016 Texas Instruments Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE.See the GNU General Public License for more details. + * + * File: + * tas256x-codec.h + * + * Description: + * header file for tas256x-codec.c + * + * ============================================================================= + */ + +#ifndef _TAS256X_CODEC_H +#define _TAS256X_CODEC_H + +#include "tas256x.h" + +int tas256x_register_codec(struct tas256x_priv *p_tas256x); +int tas256x_deregister_codec(struct tas256x_priv *p_tas256x); +int tas256x_load_config(struct tas256x_priv *p_tas256x); +void tas_reload(struct tas256x_priv *p_tas256x, int chn); + +#endif /* _TAS256X_CODEC_H */ diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x-device.h b/techpack/audio/asoc/codecs/tas256x/tas256x-device.h new file mode 100644 index 000000000000..03da258b6df7 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas256x-device.h @@ -0,0 +1,152 @@ +#ifndef __TAS256X_DEVICE_ +#define __TAS256X_DEVICE_ + +#include "tas256x.h" +#include +#define DEVICE_TAS2558 0x2558 +#define DEVICE_TAS2562 0x2562 +#define DEVICE_TAS2564 0x2564 + +#define DVC_PCM 0x1 +#define LIM_MAX_ATN 0x2 +#define LIMB_TH_MAX_MIN 0x3 +#define LIMB_INF_PT 0x4 +#define LIMB_SLOPE 0x5 +#define BOP_BOSD_TH 0x6 +#define LIMB_ATK_RT 0x7 +#define LIMB_RLS_RT 0x8 +#define LIMB_ATK_ST 0x9 +#define LIMB_RLS_ST 0xA +#define BOP_ATK_RT 0xB +#define BOP_ATK_ST 0xC +#define BOP_HLD_TM 0xD +#define BST_VREG 0xE +#define BST_ILIM 0xF + +int tas56x_software_reset(struct tas256x_priv *p_tas256x, int ch); + +int tas56x_get_chipid(struct tas256x_priv *p_tas256x, int *chipid, int ch); + +/* Power Up related functions */ +int tas256x_set_power_up(struct tas256x_priv *p_tas256x, enum channel chn); + +int tas256x_set_power_mute(struct tas256x_priv *p_tas256x, enum channel chn); + +int tas256x_set_power_shutdown(struct tas256x_priv *p_tas256x, + enum channel chn); + +int tas256x_power_check(struct tas256x_priv *p_tas256x, int *state, int ch); + +/* IV Sense Format Related functions */ +int tas256x_iv_sense_enable_set(struct tas256x_priv *p_tas256x, bool enable, + int ch); + +bool tas256x_iv_sense_enable_get(struct tas256x_priv *p_tas256x, int ch); + +int tas256x_iv_slot_config(struct tas256x_priv *p_tas256x); + +int tas256x_iv_bitwidth_config(struct tas256x_priv *p_tas256x); + +int tas256x_set_tx_config(struct tas256x_priv *p_tas256x, int value, int ch); + +/* Rx Format Related functions */ +int tas256x_set_samplerate(struct tas256x_priv *p_tas256x, int samplerate); + +int tas256x_rx_set_fmt(struct tas256x_priv *p_tas256x, unsigned int rx_edge, + unsigned int rx_start_slot); + +int tas256x_rx_set_slot(struct tas256x_priv *p_tas256x, int slot_width); + +int tas256x_rx_set_bitwidth(struct tas256x_priv *p_tas256x, int bitwidth); + +/* Interrupt Related Functions */ +int tas256x_interrupt_clear(struct tas256x_priv *p_tas256x, int ch); + +int tas256x_interrupt_enable(struct tas256x_priv *p_tas256x, int val, int ch); + +int tas256x_interrupt_read(struct tas256x_priv *p_tas256x, int *intr1, + int *intr2, int ch); + +int tas256x_interrupt_determine(struct tas256x_priv *p_tas256x, int ch, + int int1status, int int2status); + +/* ICN Related Functions */ +int tas256x_icn_enable(struct tas256x_priv *p_tas256x, int enable, int ch); + +int tas256x_icn_data(struct tas256x_priv *p_tas256x, int ch); + +int tas256x_icn_config(struct tas256x_priv *p_tas256x, int value, int ch); + +/* Boost/Volt Related functions */ +int tas256x_boost_volt_update(struct tas256x_priv *p_tas256x, int value, + int ch); + +int tas256x_set_misc_config(struct tas256x_priv *p_tas256x, int value, int ch); + +/* Clock Configuration */ +int tas256x_set_clock_config(struct tas256x_priv *p_tas256x, int value, int ch); + +/* ClassH Configuration*/ +int tas256x_set_classH_config(struct tas256x_priv *p_tas256x, int value, + int ch); + +/* HPF Related functions*/ +int tas256x_HPF_FF_Bypass(struct tas256x_priv *p_tas256x, int value, int ch); + +int tas256x_HPF_FB_Bypass(struct tas256x_priv *p_tas256x, int value, int ch); + +/*Speaker Receiever mode - specific to TAS2564*/ +int tas2564_rx_mode_update(struct tas256x_priv *p_tas256x, int rx_mode, int ch); + +/*Playback Volume*/ +int tas256x_update_playback_volume(struct tas256x_priv *p_tas256x, int value, + int ch); + +/*Limiter Related functions*/ +int tas256x_update_lim_max_attenuation(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_lim_max_thr(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_lim_min_thr(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_lim_inflection_point(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_lim_slope(struct tas256x_priv *p_tas256x, int value, int ch); + +/*Brown Out Protection related functions*/ +int tas256x_update_bop_thr(struct tas256x_priv *p_tas256x, int value, int ch); +int tas256x_update_bosd_thr(struct tas256x_priv *p_tas256x, int value, int ch); + +int tas256x_update_boost_voltage(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_current_limit(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_limiter_enable(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_limiter_attack_rate(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_limiter_attack_step_size(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_limiter_release_rate(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_limiter_release_step_size(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_bop_enable(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_bop_mute(struct tas256x_priv *p_tas256x, int value, int ch); +int tas256x_update_bop_shutdown_enable(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_bop_attack_rate(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_bop_attack_step_size(struct tas256x_priv *p_tas256x, + int value, int ch); +int tas256x_update_bop_hold_time(struct tas256x_priv *p_tas256x, int value, + int ch); +int tas256x_update_vbat_lpf(struct tas256x_priv *p_tas256x, int value, int ch); + +/*Initialize to defaults*/ +int tas256x_update_default_params(struct tas256x_priv *p_tas256x, int ch); + +int tas256x_update_rx_cfg(struct tas256x_priv *p_tas256x, int value, int ch); + +#endif /* __TAS256X_DEVICE_ */ \ No newline at end of file diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c b/techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c new file mode 100644 index 000000000000..02f8090cbf13 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c @@ -0,0 +1,1931 @@ +/* + * ALSA SoC Texas Instruments TAS256X High Performance 4W Smart Amplifier + * + * Copyright (C) 2016 Texas Instruments, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * Author: saiprasad + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ +#ifdef CONFIG_TAS256X_REGMAP +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "tas256x.h" +#include "tas2562.h" +#include "tas2564.h" +#include "tas256x-device.h" +#include "tas256x-codec.h" + +#ifdef CONFIG_TAS25XX_ALGO +#ifdef CONFIG_PLATFORM_EXYNOS +#include +#else +#include +#endif +static dc_detection_data_t s_dc_detect; +#endif /*CONFIG_TAS25XX_ALGO*/ + +/*For mixer_control implementation*/ +#define MAX_STRING 200 + +static const char *dts_tag[][3] = { + { "ti,left-channel", "ti,reset-gpio", "ti,irq-gpio" }, + { "ti,right-channel", "ti,reset-gpio2", "ti,irq-gpio2" } +}; + +static const char *reset_gpio_label[2] = { "TAS256X_RESET", "TAS256X_RESET2" }; + +static const char *irq_gpio_label[2] = { "TAS256X-IRQ", "TAS256X-IRQ2" }; + +static int tas256x_regmap_write(struct tas256x_priv *p_tas256x, + unsigned int reg, unsigned int value) +{ + int nResult = 0; + int retry_count = TAS256X_I2C_RETRY_COUNT; + + if (p_tas256x->i2c_suspend) + return ERROR_I2C_SUSPEND; + + while (retry_count--) { + nResult = regmap_write(p_tas256x->regmap, reg, value); + if (nResult >= 0) + break; + msleep(20); + } + if (retry_count == -1) + return ERROR_I2C_FAILED; + else + return 0; +} + +static int tas256x_regmap_bulk_write(struct tas256x_priv *p_tas256x, + unsigned int reg, unsigned char *pData, + unsigned int nLength) +{ + int nResult = 0; + int retry_count = TAS256X_I2C_RETRY_COUNT; + + if (p_tas256x->i2c_suspend) + return ERROR_I2C_SUSPEND; + + while (retry_count--) { + nResult = regmap_bulk_write(p_tas256x->regmap, reg, pData, + nLength); + if (nResult >= 0) + break; + msleep(20); + } + if (retry_count == -1) + return ERROR_I2C_FAILED; + else + return 0; +} + +static int tas256x_regmap_read(struct tas256x_priv *p_tas256x, unsigned int reg, + unsigned int *value) +{ + int nResult = 0; + int retry_count = TAS256X_I2C_RETRY_COUNT; + + if (p_tas256x->i2c_suspend) + return ERROR_I2C_SUSPEND; + + while (retry_count--) { + nResult = regmap_read(p_tas256x->regmap, reg, value); + if (nResult >= 0) + break; + msleep(20); + } + if (retry_count == -1) + return ERROR_I2C_FAILED; + else + return 0; +} + +static int tas256x_regmap_bulk_read(struct tas256x_priv *p_tas256x, + unsigned int reg, unsigned char *pData, + unsigned int nLength) +{ + int nResult = 0; + int retry_count = TAS256X_I2C_RETRY_COUNT; + + if (p_tas256x->i2c_suspend) + return ERROR_I2C_SUSPEND; + + while (retry_count--) { + nResult = regmap_bulk_read(p_tas256x->regmap, reg, pData, + nLength); + if (nResult >= 0) + break; + msleep(20); + } + if (retry_count == -1) + return ERROR_I2C_FAILED; + else + return 0; +} + +static int tas256x_regmap_update_bits(struct tas256x_priv *p_tas256x, + unsigned int reg, unsigned int mask, + unsigned int value) +{ + int nResult = 0; + int retry_count = TAS256X_I2C_RETRY_COUNT; + + if (p_tas256x->i2c_suspend) + return ERROR_I2C_SUSPEND; + + while (retry_count--) { + nResult = + regmap_update_bits(p_tas256x->regmap, reg, mask, value); + if (nResult >= 0) + break; + msleep(20); + } + if (retry_count == -1) + return ERROR_I2C_FAILED; + else + return 0; +} + +static int tas256x_change_book_page(struct tas256x_priv *p_tas256x, + enum channel chn, int book, int page) +{ + int n_result = 0, rc = 0; + int i = 0; + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (((chn & channel_left) && (i == 0)) || + ((chn & channel_right) && (i == 1))) { + p_tas256x->client->addr = p_tas256x->devs[i]->mn_addr; + if (p_tas256x->devs[i]->mn_current_book != book) { + n_result = tas256x_regmap_write( + p_tas256x, TAS256X_BOOKCTL_PAGE, 0); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "%s, ERROR, L=%d, E=%d\n", + __func__, __LINE__, n_result); + rc |= n_result; + continue; + } + p_tas256x->devs[i]->mn_current_page = 0; + n_result = tas256x_regmap_write( + p_tas256x, TAS256X_BOOKCTL_REG, book); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "%s, ERROR, L=%d, E=%d\n", + __func__, __LINE__, n_result); + rc |= n_result; + continue; + } + p_tas256x->devs[i]->mn_current_book = book; + } + + if (p_tas256x->devs[i]->mn_current_page != page) { + n_result = tas256x_regmap_write( + p_tas256x, TAS256X_BOOKCTL_PAGE, page); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "%s, ERROR, L=%d, E=%d\n", + __func__, __LINE__, n_result); + rc |= n_result; + continue; + } + p_tas256x->devs[i]->mn_current_page = page; + } + } + } + if (rc < 0) { + if (chn & channel_left) + p_tas256x->mn_err_code |= ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code |= ERROR_DEVB_I2C_COMM; + } else { + if (chn & channel_left) + p_tas256x->mn_err_code &= ~ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code &= ~ERROR_DEVB_I2C_COMM; + } + + return rc; +} + +static int tas256x_dev_read(struct tas256x_priv *p_tas256x, enum channel chn, + unsigned int reg, unsigned int *pValue) +{ + int n_result = 0; + + mutex_lock(&p_tas256x->dev_lock); + + n_result = tas256x_change_book_page( + p_tas256x, chn, TAS256X_BOOK_ID(reg), TAS256X_PAGE_ID(reg)); + if (n_result < 0) + goto end; + + /*Force left incase of mono*/ + if ((chn == channel_right) && (p_tas256x->mn_channels == 1)) + chn = channel_left; + + if ((chn == channel_left) || (p_tas256x->mn_channels == 1)) + p_tas256x->client->addr = p_tas256x->devs[chn >> 1]->mn_addr; + else if (chn == channel_right) + p_tas256x->client->addr = p_tas256x->devs[chn >> 1]->mn_addr; + else + dev_err(p_tas256x->dev, "%s, wrong channel number\n", __func__); + + n_result = + tas256x_regmap_read(p_tas256x, TAS256X_PAGE_REG(reg), pValue); + if (n_result < 0) { + dev_err(p_tas256x->dev, "%s, ERROR, L=%d, E=%d\n", __func__, + __LINE__, n_result); + if (chn & channel_left) + p_tas256x->mn_err_code |= ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code |= ERROR_DEVB_I2C_COMM; + } else { + dev_dbg(p_tas256x->dev, + "%s: chn:%x:BOOK:PAGE:REG 0x%02x:0x%02x:0x%02x,0x%02x\n", + __func__, p_tas256x->client->addr, TAS256X_BOOK_ID(reg), + TAS256X_PAGE_ID(reg), TAS256X_PAGE_REG(reg), *pValue); + if (chn & channel_left) + p_tas256x->mn_err_code &= ~ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code &= ~ERROR_DEVB_I2C_COMM; + } +end: + mutex_unlock(&p_tas256x->dev_lock); + return n_result; +} + +static int tas256x_dev_write(struct tas256x_priv *p_tas256x, enum channel chn, + unsigned int reg, unsigned int value) +{ + int n_result = 0, rc = 0; + int i = 0; + + mutex_lock(&p_tas256x->dev_lock); + + n_result = tas256x_change_book_page( + p_tas256x, chn, TAS256X_BOOK_ID(reg), TAS256X_PAGE_ID(reg)); + if (n_result < 0) + goto end; + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (((chn & channel_left) && (i == 0)) || + ((chn & channel_right) && (i == 1))) { + p_tas256x->client->addr = p_tas256x->devs[i]->mn_addr; + + n_result = tas256x_regmap_write( + p_tas256x, TAS256X_PAGE_REG(reg), value); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "%s, ERROR, L=%u, chn=0x%02x, E=%d\n", + __func__, __LINE__, + p_tas256x->client->addr, n_result); + rc |= n_result; + if (chn & channel_left) + p_tas256x->mn_err_code |= + ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code |= + ERROR_DEVB_I2C_COMM; + } else { + dev_dbg(p_tas256x->dev, + "%s: %u: chn:0x%02x:BOOK:PAGE:REG 0x%02x:0x%02x:0x%02x, VAL: 0x%02x\n", + __func__, __LINE__, + p_tas256x->client->addr, + TAS256X_BOOK_ID(reg), + TAS256X_PAGE_ID(reg), + TAS256X_PAGE_REG(reg), value); + if (chn & channel_left) + p_tas256x->mn_err_code &= + ~ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code &= + ~ERROR_DEVB_I2C_COMM; + } + } + } +end: + mutex_unlock(&p_tas256x->dev_lock); + return rc; +} + +static int tas256x_dev_bulk_write(struct tas256x_priv *p_tas256x, + enum channel chn, unsigned int reg, + unsigned char *p_data, unsigned int n_length) +{ + int n_result = 0, rc = 0; + int i = 0; + + mutex_lock(&p_tas256x->dev_lock); + + n_result = tas256x_change_book_page( + p_tas256x, chn, TAS256X_BOOK_ID(reg), TAS256X_PAGE_ID(reg)); + if (n_result < 0) + goto end; + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (((chn & channel_left) && (i == 0)) || + ((chn & channel_right) && (i == 1))) { + p_tas256x->client->addr = p_tas256x->devs[i]->mn_addr; + n_result = + tas256x_regmap_bulk_write(p_tas256x, + TAS256X_PAGE_REG(reg), + p_data, n_length); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "%s, ERROR, L=%u, chn=0x%02x: E=%d\n", + __func__, __LINE__, + p_tas256x->client->addr, n_result); + rc |= n_result; + if (chn & channel_left) + p_tas256x->mn_err_code |= + ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code |= + ERROR_DEVB_I2C_COMM; + } else { + dev_dbg(p_tas256x->dev, + "%s: chn%x:BOOK:PAGE:REG 0x%02x:0x%02x:0x%02x, len: %u\n", + __func__, p_tas256x->client->addr, + TAS256X_BOOK_ID(reg), + TAS256X_PAGE_ID(reg), + TAS256X_PAGE_REG(reg), n_length); + if (chn & channel_left) + p_tas256x->mn_err_code &= + ~ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code &= + ~ERROR_DEVB_I2C_COMM; + } + } + } + +end: + mutex_unlock(&p_tas256x->dev_lock); + return rc; +} + +static int tas256x_dev_bulk_read(struct tas256x_priv *p_tas256x, + enum channel chn, unsigned int reg, + unsigned char *p_data, unsigned int n_length) +{ + int n_result = 0; + + mutex_lock(&p_tas256x->dev_lock); + + if ((chn == channel_left) || (p_tas256x->mn_channels == 1)) + p_tas256x->client->addr = p_tas256x->devs[chn >> 1]->mn_addr; + else if (chn == channel_right) + p_tas256x->client->addr = p_tas256x->devs[chn >> 1]->mn_addr; + else + dev_err(p_tas256x->dev, "%s, wrong channel number\n", __func__); + + n_result = tas256x_change_book_page( + p_tas256x, chn, TAS256X_BOOK_ID(reg), TAS256X_PAGE_ID(reg)); + if (n_result < 0) + goto end; + + n_result = tas256x_regmap_bulk_read(p_tas256x, TAS256X_PAGE_REG(reg), + p_data, n_length); + if (n_result < 0) { + dev_err(p_tas256x->dev, "%s, ERROR, L=%d, E=%d\n", __func__, + __LINE__, n_result); + if (chn & channel_left) + p_tas256x->mn_err_code |= ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code |= ERROR_DEVB_I2C_COMM; + } else { + dev_dbg(p_tas256x->dev, + "%s: chn%x:BOOK:PAGE:REG %u:%u:%u, len: 0x%02x\n", + __func__, p_tas256x->client->addr, TAS256X_BOOK_ID(reg), + TAS256X_PAGE_ID(reg), TAS256X_PAGE_REG(reg), n_length); + if (chn & channel_left) + p_tas256x->mn_err_code &= ~ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code &= ~ERROR_DEVB_I2C_COMM; + } +end: + mutex_unlock(&p_tas256x->dev_lock); + return n_result; +} + +static int tas256x_dev_update_bits(struct tas256x_priv *p_tas256x, + enum channel chn, unsigned int reg, + unsigned int mask, unsigned int value) +{ + int n_result = 0, rc = 0; + int i = 0; + + mutex_lock(&p_tas256x->dev_lock); + n_result = tas256x_change_book_page( + p_tas256x, chn, TAS256X_BOOK_ID(reg), TAS256X_PAGE_ID(reg)); + if (n_result < 0) { + rc = n_result; + goto end; + } + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (((chn & channel_left) && (i == 0)) || + ((chn & channel_right) && (i == 1))) { + p_tas256x->client->addr = p_tas256x->devs[i]->mn_addr; + n_result = tas256x_regmap_update_bits( + p_tas256x, TAS256X_PAGE_REG(reg), mask, value); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "%s, ERROR, L=%u, chn=0x%02x: E=%d\n", + __func__, __LINE__, + p_tas256x->client->addr, n_result); + rc |= n_result; + if (chn & channel_left) + p_tas256x->mn_err_code |= + ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code |= + ERROR_DEVB_I2C_COMM; + } else { + dev_dbg(p_tas256x->dev, + "%s: chn%x:BOOK:PAGE:REG 0x%02x:0x%02x:0x%02x, mask: 0x%02x, val: 0x%02x\n", + __func__, p_tas256x->client->addr, + TAS256X_BOOK_ID(reg), + TAS256X_PAGE_ID(reg), + TAS256X_PAGE_REG(reg), mask, value); + if (chn & channel_left) + p_tas256x->mn_err_code &= + ~ERROR_DEVA_I2C_COMM; + if (chn & channel_right) + p_tas256x->mn_err_code &= + ~ERROR_DEVB_I2C_COMM; + } + } + } + +end: + mutex_unlock(&p_tas256x->dev_lock); + return rc; +} + +static int tas2558_specific(struct tas256x_priv *p_tas256x, int chn) +{ + int ret = 0; + + ret = tas256x_boost_volt_update(p_tas256x, DEVICE_TAS2558, chn); + + return ret; +} + +static int tas2564_specific(struct tas256x_priv *p_tas256x, int chn) +{ + int ret = 0; + + ret = tas256x_boost_volt_update(p_tas256x, DEVICE_TAS2564, chn); + ret |= tas2564_rx_mode_update(p_tas256x, 0, chn); + + return ret; +} + +static char const *tas2564_rx_mode_text[] = { "Speaker", "Receiver" }; + +static const struct soc_enum tas2564_rx_mode_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas2564_rx_mode_text), + tas2564_rx_mode_text), +}; + +static int tas2564_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct tas256x_priv *p_tas256x = NULL; + int ret = -1; + + if (codec == NULL) { + pr_err("%s:codec is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + if (strnstr(ucontrol->id.name, "LEFT", MAX_STRING)) + ret = tas2564_rx_mode_update(p_tas256x, + ucontrol->value.integer.value[0], + channel_left); + else if (strnstr(ucontrol->id.name, "RIGHT", MAX_STRING)) + ret = tas2564_rx_mode_update(p_tas256x, + ucontrol->value.integer.value[0], + channel_right); + else + dev_err(p_tas256x->dev, "Invalid Channel %s\n", + ucontrol->id.name); + + return ret; +} + +static int tas2564_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = -1; +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct tas256x_priv *p_tas256x = NULL; + + if (codec == NULL) { + pr_err("%s:codec is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + if (strnstr(ucontrol->id.name, "LEFT", MAX_STRING)) + ucontrol->value.integer.value[0] = p_tas256x->devs[0]->rx_mode; + else if (strnstr(ucontrol->id.name, "RIGHT", MAX_STRING)) + ucontrol->value.integer.value[0] = p_tas256x->devs[1]->rx_mode; + else + dev_err(p_tas256x->dev, "Invalid Channel %s\n", + ucontrol->id.name); + + return 0; +} + +static int tas256x_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct tas256x_priv *p_tas256x = NULL; + int ret = -1; + + if ((codec == NULL) || (mc == NULL)) { + pr_err("%s:codec or control is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + if (ucontrol->value.integer.value[0] > mc->max) + return ret; + + switch (mc->reg) { + case DVC_PCM: + ret = tas256x_update_playback_volume( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case LIM_MAX_ATN: + ret = tas256x_update_lim_max_attenuation( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case LIMB_INF_PT: + ret = tas256x_update_lim_inflection_point( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case LIMB_SLOPE: + ret = tas256x_update_lim_slope( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case LIMB_ATK_RT: + ret = tas256x_update_limiter_attack_rate( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case LIMB_RLS_RT: + ret = tas256x_update_limiter_release_rate( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case LIMB_RLS_ST: + ret = tas256x_update_limiter_release_step_size( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case LIMB_ATK_ST: + ret = tas256x_update_limiter_attack_step_size( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case BOP_ATK_RT: + ret = tas256x_update_bop_attack_rate( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case BOP_ATK_ST: + ret = tas256x_update_bop_attack_step_size( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case BOP_HLD_TM: + ret = tas256x_update_bop_hold_time( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case BST_VREG: + ret = tas256x_update_boost_voltage( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + case BST_ILIM: + ret = tas256x_update_current_limit( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + break; + } + return ret; +} + +static int tas256x_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct tas256x_priv *p_tas256x = NULL; + int ret = -1; + + if ((codec == NULL) || (mc == NULL)) { + pr_err("%s:codec or control is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + switch (mc->reg) { + case DVC_PCM: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->dvc_pcm; + break; + case LIM_MAX_ATN: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_max_attn; + break; + case LIMB_INF_PT: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_infl_pt; + break; + case LIMB_SLOPE: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_trk_slp; + break; + case LIMB_ATK_RT: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_att_rate; + break; + case LIMB_RLS_RT: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_rel_rate; + break; + case LIMB_RLS_ST: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_rel_stp_size; + break; + case LIMB_ATK_ST: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_att_stp_size; + break; + case BOP_ATK_RT: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->bop_att_rate; + break; + case BOP_ATK_ST: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->bop_att_stp_size; + break; + case BOP_HLD_TM: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->bop_hld_time; + break; + case BST_VREG: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->bst_vltg; + break; + case BST_ILIM: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->bst_ilm; + break; + } + return 0; +} + +static int tas256x_multi_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct soc_multi_mixer_control *mc = + (struct soc_multi_mixer_control *)kcontrol->private_value; + struct tas256x_priv *p_tas256x = NULL; + int ret = -1; + + if ((codec == NULL) || (mc == NULL)) { + pr_err("%s:codec or control is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + if ((ucontrol->value.integer.value[0] > mc->max) || + (ucontrol->value.integer.value[1] > mc->max)) + return ret; + + switch (mc->reg) { + case LIMB_TH_MAX_MIN: + ret = tas256x_update_lim_max_thr( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + ret = tas256x_update_lim_min_thr( + p_tas256x, ucontrol->value.integer.value[1], mc->shift); + break; + case BOP_BOSD_TH: + ret = tas256x_update_bop_thr( + p_tas256x, ucontrol->value.integer.value[0], mc->shift); + ret = tas256x_update_bosd_thr( + p_tas256x, ucontrol->value.integer.value[1], mc->shift); + break; + } + return ret; +} + +static int tas256x_multi_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct soc_multi_mixer_control *mc = + (struct soc_multi_mixer_control *)kcontrol->private_value; + struct tas256x_priv *p_tas256x = NULL; + int ret = -1; + + if ((codec == NULL) || (mc == NULL)) { + pr_err("%s:codec or control is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + switch (mc->reg) { + case LIMB_TH_MAX_MIN: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->lim_thr_max; + ucontrol->value.integer.value[1] = + p_tas256x->devs[mc->shift - 1]->lim_thr_min; + break; + case BOP_BOSD_TH: + ucontrol->value.integer.value[0] = + p_tas256x->devs[mc->shift - 1]->bop_thd; + ucontrol->value.integer.value[1] = + p_tas256x->devs[mc->shift - 1]->bosd_thd; + break; + } + return 0; +} + +static int tas256x_enum_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = -1; +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct tas256x_priv *p_tas256x = NULL; + + if (codec == NULL) { + pr_err("%s:codec is NULL\n", __func__); + return ret; + } + + if (ucontrol == NULL) { + pr_err("%s:ucontrol is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + if (strnstr(ucontrol->id.name, "LEFT", MAX_STRING)) { + if (strnstr(ucontrol->id.name, "LIMITER SWITCH", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[0]->lim_switch; + else if (strnstr(ucontrol->id.name, "BOP ENABLE", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[0]->bop_enable; + else if (strnstr(ucontrol->id.name, "BOP MUTE", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[0]->bop_mute; + else if (strnstr(ucontrol->id.name, "BROWNOUT SHUTDOWN", + MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[0]->bosd_enable; + else if (strnstr(ucontrol->id.name, "VBAT LPF", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[0]->vbat_lpf; + else + dev_err(p_tas256x->dev, "Invalid controll %s\n", + ucontrol->id.name); + } else if (strnstr(ucontrol->id.name, "RIGHT", MAX_STRING)) { + if (strnstr(ucontrol->id.name, "LIMITER SWITCH", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[1]->lim_switch; + else if (strnstr(ucontrol->id.name, "BOP ENABLE", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[1]->bop_enable; + else if (strnstr(ucontrol->id.name, "BOP MUTE", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[1]->bop_mute; + else if (strnstr(ucontrol->id.name, "BROWNOUT SHUTDOWN", + MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[1]->bosd_enable; + else if (strnstr(ucontrol->id.name, "VBAT LPF", MAX_STRING)) + ucontrol->value.integer.value[0] = + p_tas256x->devs[1]->vbat_lpf; + else + dev_err(p_tas256x->dev, "Invalid controll %s\n", + ucontrol->id.name); + } else { + dev_err(p_tas256x->dev, "Invalid Channel %s\n", + ucontrol->id.name); + } + return 0; +} + +static int tas256x_enum_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol); +#else + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); +#endif + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct tas256x_priv *p_tas256x = NULL; + int ret = -1; + + if ((codec == NULL) || (mc == NULL)) { + pr_err("%s:codec or control is NULL\n", __func__); + return ret; + } + +#if KERNEL_VERSION(4, 19, 0) <= LINUX_VERSION_CODE + p_tas256x = snd_soc_component_get_drvdata(codec); +#else + p_tas256x = snd_soc_codec_get_drvdata(codec); +#endif + if (p_tas256x == NULL) { + pr_err("%s:p_tas256x is NULL\n", __func__); + return ret; + } + + if (strnstr(ucontrol->id.name, "LEFT", MAX_STRING)) { + if (strnstr(ucontrol->id.name, "LIMITER SWITCH", MAX_STRING)) + ret = tas256x_update_limiter_enable( + p_tas256x, ucontrol->value.integer.value[0], + channel_left); + else if (strnstr(ucontrol->id.name, "BOP ENABLE", MAX_STRING)) + ret = tas256x_update_bop_enable( + p_tas256x, ucontrol->value.integer.value[0], + channel_left); + else if (strnstr(ucontrol->id.name, "BOP MUTE", MAX_STRING)) + ret = tas256x_update_bop_mute( + p_tas256x, ucontrol->value.integer.value[0], + channel_left); + else if (strnstr(ucontrol->id.name, "BROWNOUT SHUTDOWN", + MAX_STRING)) + ret = tas256x_update_bop_shutdown_enable( + p_tas256x, ucontrol->value.integer.value[0], + channel_left); + else if (strnstr(ucontrol->id.name, "VBAT LPF", MAX_STRING)) + ret = tas256x_update_vbat_lpf( + p_tas256x, ucontrol->value.integer.value[0], + channel_left); + else + dev_err(p_tas256x->dev, "Invalid Control %s\n", + ucontrol->id.name); + } else if (strnstr(ucontrol->id.name, "RIGHT", MAX_STRING)) { + if (strnstr(ucontrol->id.name, "LIMITER SWITCH", MAX_STRING)) + ret = tas256x_update_limiter_enable( + p_tas256x, ucontrol->value.integer.value[0], + channel_right); + else if (strnstr(ucontrol->id.name, "BOP ENABLE", MAX_STRING)) + ret = tas256x_update_bop_enable( + p_tas256x, ucontrol->value.integer.value[0], + channel_right); + else if (strnstr(ucontrol->id.name, "BOP MUTE", MAX_STRING)) + ret = tas256x_update_bop_mute( + p_tas256x, ucontrol->value.integer.value[0], + channel_right); + else if (strnstr(ucontrol->id.name, "BROWNOUT SHUTDOWN", + MAX_STRING)) + ret = tas256x_update_bop_shutdown_enable( + p_tas256x, ucontrol->value.integer.value[0], + channel_right); + else if (strnstr(ucontrol->id.name, "VBAT LPF", MAX_STRING)) + ret = tas256x_update_vbat_lpf( + p_tas256x, ucontrol->value.integer.value[0], + channel_right); + else + dev_err(p_tas256x->dev, "Invalid control %s\n", + ucontrol->id.name); + } else { + dev_err(p_tas256x->dev, "Invalid Channel %s\n", + ucontrol->id.name); + } + return ret; +} + +static char const *tas256x_rx_switch_text[] = { "DISABLE", "ENABLE" }; +static const struct soc_enum tas256x_rx_switch_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas256x_rx_switch_text), + tas256x_rx_switch_text), +}; + +static const struct snd_kcontrol_new tas256x_left_controls[] = { + SOC_SINGLE_EXT("TAS256X PLAYBACK VOLUME LEFT", DVC_PCM, 1, 56, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM MAX ATTN LEFT", LIM_MAX_ATN, 1, 15, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_MULTI_EXT("TAS256X LIM THR MAX MIN LEFT", LIMB_TH_MAX_MIN, 1, + 26, 0, 2, tas256x_multi_get, tas256x_multi_put), + SOC_SINGLE_EXT("TAS256X LIM INFLECTION POINT LEFT", LIMB_INF_PT, 1, 40, + 0, tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM SLOPE LEFT", LIMB_SLOPE, 1, 6, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_MULTI_EXT("TAS256X BOP THR SHUTDOWN THR LEFT", BOP_BOSD_TH, + 1, 15, 0, 2, tas256x_multi_get, tas256x_multi_put), + SOC_SINGLE_EXT("TAS256X LIM ATTACT RATE LEFT", LIMB_ATK_RT, 1, 7, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM RELEASE RATE LEFT", LIMB_RLS_RT, 1, 7, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM ATTACK STEP LEFT", LIMB_ATK_ST, 1, 3, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM RELEASE STEP LEFT", LIMB_RLS_ST, 1, 3, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOP ATTACK RATE LEFT", BOP_ATK_RT, 1, 7, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOP ATTACK STEP LEFT", BOP_ATK_ST, 1, 3, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOP HOLD TIME LEFT", BOP_HLD_TM, 1, 7, 0, + tas256x_get, tas256x_put), + SOC_ENUM_EXT("TAS256X LIMITER SWITCH LEFT", tas256x_rx_switch_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_ENUM_EXT("TAS256X BOP ENABLE LEFT", tas256x_rx_switch_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_ENUM_EXT("TAS256X BOP MUTE LEFT", tas256x_rx_switch_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_ENUM_EXT("TAS256X BROWNOUT SHUTDOWN LEFT", + tas256x_rx_switch_enum[0], tas256x_enum_get, + tas256x_enum_put), +}; + +static const struct snd_kcontrol_new tas256x_right_controls[] = { + SOC_SINGLE_EXT("TAS256X PLAYBACK VOLUME RIGHT", DVC_PCM, 2, 56, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM MAX ATTN RIGHT", LIM_MAX_ATN, 2, 15, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_MULTI_EXT("TAS256X LIM THR MAX MIN RIGHT", LIMB_TH_MAX_MIN, + 2, 26, 0, 2, tas256x_multi_get, tas256x_multi_put), + SOC_SINGLE_EXT("TAS256X LIM INFLECTION POINT RIGHT", LIMB_INF_PT, 2, 40, + 0, tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM SLOPE RIGHT", LIMB_SLOPE, 2, 6, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_MULTI_EXT("TAS256X BOP THR SHUTDOWN THR RIGHT", BOP_BOSD_TH, + 2, 15, 0, 2, tas256x_multi_get, tas256x_multi_put), + SOC_SINGLE_EXT("TAS256X LIM ATTACT RATE RIGHT", LIMB_ATK_RT, 2, 7, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM RELEASE RATE RIGHT", LIMB_RLS_RT, 2, 7, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM ATTACK STEP RIGHT", LIMB_ATK_ST, 2, 3, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X LIM RELEASE STEP RIGHT", LIMB_RLS_ST, 2, 3, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOP ATTACK RATE RIGHT", BOP_ATK_RT, 2, 7, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOP ATTACK STEP RIGHT", BOP_ATK_ST, 2, 3, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOP HOLD TIME RIGHT", BOP_HLD_TM, 2, 7, 0, + tas256x_get, tas256x_put), + SOC_ENUM_EXT("TAS256X LIMITER SWITCH RIGHT", tas256x_rx_switch_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_ENUM_EXT("TAS256X BOP ENABLE RIGHT", tas256x_rx_switch_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_ENUM_EXT("TAS256X BOP MUTE RIGHT", tas256x_rx_switch_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_ENUM_EXT("TAS256X BROWNOUT SHUTDOWN RIGHT", + tas256x_rx_switch_enum[0], tas256x_enum_get, + tas256x_enum_put), +}; + +static char const *tas2564_vbat_lpf_text[] = { "DISABLE", "HZ_10", "HZ_100", + "KHZ_1" }; +static const struct soc_enum tas2564_vbat_lpf_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas2564_vbat_lpf_text), + tas2564_vbat_lpf_text), +}; + +static char const *tas2562_vbat_lpf_text[] = { "DISABLE", "HZ_100", "KHZ_1", + "KHZ_10" }; +static const struct soc_enum tas2562_vbat_lpf_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas2562_vbat_lpf_text), + tas2562_vbat_lpf_text), +}; + +static const struct snd_kcontrol_new tas2564_left_controls[] = { + SOC_ENUM_EXT("TAS256X RX MODE LEFT", tas2564_rx_mode_enum[0], + tas2564_get, tas2564_put), + SOC_ENUM_EXT("TAS256X VBAT LPF LEFT", tas2564_vbat_lpf_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_SINGLE_EXT("TAS256X BOOST VOLTAGE LEFT", BST_VREG, 1, 15, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOOST CURRENT LEFT", BST_ILIM, 1, 63, 0, + tas256x_get, tas256x_put), +}; + +static const struct snd_kcontrol_new tas2564_right_controls[] = { + SOC_ENUM_EXT("TAS256X RX MODE RIGHT", tas2564_rx_mode_enum[0], + tas2564_get, tas2564_put), + SOC_ENUM_EXT("TAS256X VBAT LPF RIGHT", tas2564_vbat_lpf_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_SINGLE_EXT("TAS256X BOOST VOLTAGE RIGHT", BST_VREG, 2, 15, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOOST CURRENT RIGHT", BST_ILIM, 2, 63, 0, + tas256x_get, tas256x_put), +}; + +static const struct snd_kcontrol_new tas2562_left_controls[] = { + SOC_ENUM_EXT("TAS256X VBAT LPF LEFT", tas2562_vbat_lpf_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_SINGLE_EXT("TAS256X BOOST VOLTAGE LEFT", BST_VREG, 1, 12, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOOST CURRENT LEFT", BST_ILIM, 1, 55, 0, + tas256x_get, tas256x_put), +}; + +static const struct snd_kcontrol_new tas2562_right_controls[] = { + SOC_ENUM_EXT("TAS256X VBAT LPF RIGHT", tas2562_vbat_lpf_enum[0], + tas256x_enum_get, tas256x_enum_put), + SOC_SINGLE_EXT("TAS256X BOOST VOLTAGE RIGHT", BST_VREG, 2, 12, 0, + tas256x_get, tas256x_put), + SOC_SINGLE_EXT("TAS256X BOOST CURRENT RIGHT", BST_ILIM, 2, 55, 0, + tas256x_get, tas256x_put), +}; + +static int tas2564_probe(struct tas256x_priv *p_tas256x, + struct snd_soc_codec *codec, int chn) +{ + int ret = -1; + + if ((!p_tas256x) || (!codec)) { + pr_err("tas256x:%s p_tas256x or codec is Null\n", __func__); + return ret; + } + dev_dbg(p_tas256x->dev, "%s channel %d", __func__, chn); + + tas256x_update_default_params(p_tas256x, chn); + if (chn == channel_left) { + ret = snd_soc_add_codec_controls( + codec, tas256x_left_controls, + ARRAY_SIZE(tas256x_left_controls)); + ret = snd_soc_add_codec_controls( + codec, tas2564_left_controls, + ARRAY_SIZE(tas2564_left_controls)); + } else if (chn == channel_right) { + ret = snd_soc_add_codec_controls( + codec, tas256x_right_controls, + ARRAY_SIZE(tas256x_right_controls)); + ret = snd_soc_add_codec_controls( + codec, tas2564_right_controls, + ARRAY_SIZE(tas2564_right_controls)); + } else { + dev_err(p_tas256x->dev, "Invalid Channel %d\n", chn); + } + + return ret; +} + +static int tas2562_probe(struct tas256x_priv *p_tas256x, + struct snd_soc_codec *codec, int chn) +{ + int ret = -1; + + if ((!p_tas256x) || (!codec)) { + pr_err("tas256x:%s p_tas256x or codec is Null\n", __func__); + return ret; + } + dev_dbg(p_tas256x->dev, "%s channel %d", __func__, chn); + + tas256x_update_default_params(p_tas256x, chn); + if (chn == channel_left) { + ret = snd_soc_add_codec_controls( + codec, tas256x_left_controls, + ARRAY_SIZE(tas256x_left_controls)); + ret = snd_soc_add_codec_controls( + codec, tas2562_left_controls, + ARRAY_SIZE(tas2562_left_controls)); + } else if (chn == channel_right) { + ret = snd_soc_add_codec_controls( + codec, tas256x_right_controls, + ARRAY_SIZE(tas256x_right_controls)); + ret = snd_soc_add_codec_controls( + codec, tas2562_right_controls, + ARRAY_SIZE(tas2562_right_controls)); + } else { + dev_err(p_tas256x->dev, "Invalid Channel %d\n", chn); + } + + return ret; +} + +static bool tas256x_volatile(struct device *dev, unsigned int reg) +{ + return true; +} + +static bool tas256x_writeable(struct device *dev, unsigned int reg) +{ + return true; +} +static const struct regmap_config tas256x_i2c_regmap = { + .reg_bits = 8, + .val_bits = 8, + .writeable_reg = tas256x_writeable, + .volatile_reg = tas256x_volatile, + .cache_type = REGCACHE_NONE, + .max_register = 1 * 128, +}; + +static void tas256x_hw_reset(struct tas256x_priv *p_tas256x) +{ + int i = 0; + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (gpio_is_valid(p_tas256x->devs[i]->mn_reset_gpio)) { + gpio_direction_output(p_tas256x->devs[i]->mn_reset_gpio, + 0); + } + } + msleep(20); + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (gpio_is_valid(p_tas256x->devs[i]->mn_reset_gpio)) { + gpio_direction_output(p_tas256x->devs[i]->mn_reset_gpio, + 1); + } + p_tas256x->devs[i]->mn_current_book = -1; + p_tas256x->devs[i]->mn_current_page = -1; + } + msleep(20); + + dev_info(p_tas256x->dev, "reset gpio up !!\n"); +} + +void tas256x_enable_irq(struct tas256x_priv *p_tas256x, bool enable) +{ + static int irq_enabled[2]; + struct irq_desc *desc = NULL; + int i = 0; + + if (enable) { + if (p_tas256x->mb_irq_eable) + return; + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (gpio_is_valid(p_tas256x->devs[i]->mn_irq_gpio) && + irq_enabled[i] == 0) { + if (i == 0) { + desc = irq_to_desc( + p_tas256x->devs[i]->mn_irq); + if (desc && desc->depth > 0) + enable_irq(p_tas256x->devs[i] + ->mn_irq); + else + dev_info( + p_tas256x->dev, + "### irq already enabled"); + } else { + enable_irq(p_tas256x->devs[i]->mn_irq); + } + irq_enabled[i] = 1; + } + } + p_tas256x->mb_irq_eable = true; + } else { + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (gpio_is_valid(p_tas256x->devs[i]->mn_irq_gpio) && + irq_enabled[i] == 1) { + disable_irq_nosync(p_tas256x->devs[i]->mn_irq); + irq_enabled[i] = 0; + } + } + p_tas256x->mb_irq_eable = false; + } +} + +static void irq_work_routine(struct work_struct *work) +{ + struct tas256x_priv *p_tas256x = + container_of(work, struct tas256x_priv, irq_work.work); + unsigned int nDevInt1Status = 0, nDevInt2Status = 0, nDevInt3Status = 0, + nDevInt4Status = 0; + int n_counter = 2; + int n_result = 0; + int irqreg, irqreg2, i, chnTemp = 0; + enum channel chn = channel_left; + + dev_info(p_tas256x->dev, "%s\n", __func__); +#ifdef CONFIG_TAS256X_CODEC + mutex_lock(&p_tas256x->codec_lock); +#endif + tas256x_enable_irq(p_tas256x, false); + + if (p_tas256x->mn_err_code & ERROR_FAILSAFE) + goto reload; + + if (p_tas256x->mb_runtime_suspend) { + dev_info(p_tas256x->dev, "%s, Runtime Suspended\n", __func__); + goto end; + } + + if (p_tas256x->mn_power_state == TAS256X_POWER_SHUTDOWN) { + dev_info(p_tas256x->dev, "%s, device not powered\n", __func__); + goto end; + } + + n_result = tas256x_interrupt_enable(p_tas256x, 0 /*Disable*/, + channel_both); + if (n_result < 0) + goto reload; + + /*Reset error codes*/ + p_tas256x->mn_err_code = 0; + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (p_tas256x->devs[i]->spk_control == 1) + chnTemp |= 1 << i; + } + chn = (chnTemp == 0) ? chn : (enum channel)chnTemp; + + if (chn & channel_left) { + n_result = + tas256x_interrupt_read(p_tas256x, &nDevInt1Status, + &nDevInt2Status, channel_left); + if (n_result < 0) + goto reload; + p_tas256x->mn_err_code = + tas256x_interrupt_determine(p_tas256x, channel_left, + nDevInt1Status, + nDevInt2Status); + } + + if (chn & channel_right) { + n_result = + tas256x_interrupt_read(p_tas256x, &nDevInt3Status, + &nDevInt4Status, channel_right); + if (n_result < 0) + goto reload; + p_tas256x->mn_err_code |= + tas256x_interrupt_determine(p_tas256x, channel_right, + nDevInt3Status, + nDevInt4Status); + } + + dev_dbg(p_tas256x->dev, + "IRQ status : 0x%x, 0x%x, 0x%x, 0x%x mn_err_code %d\n", + nDevInt1Status, nDevInt2Status, nDevInt3Status, nDevInt4Status, + p_tas256x->mn_err_code); + + if (p_tas256x->mn_err_code) + goto reload; + else { + n_counter = 2; + + while (n_counter > 0) { + if (chn & channel_left) + n_result = tas256x_power_check(p_tas256x, + &nDevInt1Status, + channel_left); + if (n_result < 0) + goto reload; + if (chn & channel_right) + n_result = tas256x_power_check(p_tas256x, + &nDevInt3Status, + channel_right); + if (n_result < 0) + goto reload; + + if (nDevInt1Status) { + /* If only left should be power on */ + if (chn == channel_left) + break; + /* If both should be power on */ + if (nDevInt3Status) + break; + } else if (chn == channel_right) { + /*If only right should be power on */ + if (nDevInt3Status) + break; + } + + tas256x_interrupt_read(p_tas256x, &irqreg, &irqreg2, + channel_left); + dev_info(p_tas256x->dev, "IRQ reg is: %s %d, %d\n", + __func__, irqreg, __LINE__); + tas256x_interrupt_read(p_tas256x, &irqreg, &irqreg2, + channel_right); + dev_info(p_tas256x->dev, "IRQ reg is: %s %d, %d\n", + __func__, irqreg, __LINE__); + + n_counter--; + if (n_counter > 0) { + /* in case check pow status + *just after power on TAS256x + */ + dev_dbg(p_tas256x->dev, + "PowSts B: 0x%x, check again after 10ms\n", + nDevInt1Status); + msleep(20); + } + } + + if (((!nDevInt1Status) && (chn & channel_left)) || + ((!nDevInt3Status) && (chn & channel_right))) { + dev_err(p_tas256x->dev, + "%s, Critical ERROR REG[POWERCONTROL] = 0x%x\n", + __func__, nDevInt1Status); + goto reload; + } + } + + n_result = + tas256x_interrupt_enable(p_tas256x, 1 /*Enable*/, channel_both); + if (n_result < 0) + goto reload; + + goto end; + +reload: + /* hardware reset and reload */ + tas256x_load_config(p_tas256x); + +end: + tas256x_enable_irq(p_tas256x, true); +#ifdef CONFIG_TAS256X_CODEC + mutex_unlock(&p_tas256x->codec_lock); +#endif +} + +static void init_work_routine(struct work_struct *work) +{ + struct tas256x_priv *p_tas256x = + container_of(work, struct tas256x_priv, init_work.work); + int n_result = 0; + int irqreg = 0, irqreg2 = 0; + + pr_info("%s:\n", __func__); + + tas256x_interrupt_read(p_tas256x, &irqreg, &irqreg2, channel_left); + dev_info(p_tas256x->dev, "IRQ reg is: %s %d, %d\n", __func__, irqreg, + __LINE__); + tas256x_interrupt_read(p_tas256x, &irqreg, &irqreg2, channel_right); + dev_info(p_tas256x->dev, "IRQ reg is: %s %d, %d\n", __func__, irqreg, + __LINE__); + + /* Clear latched IRQ before power on */ + n_result = tas256x_interrupt_clear(p_tas256x, channel_both); + + /*Un-Mask interrupt for TDM*/ + n_result = + tas256x_interrupt_enable(p_tas256x, 1 /*Enable*/, channel_both); + + p_tas256x->enable_irq(p_tas256x, true); +} + +static irqreturn_t tas256x_irq_handler(int irq, void *dev_id) +{ + struct tas256x_priv *p_tas256x = (struct tas256x_priv *)dev_id; + + /* get IRQ status after 100 ms */ + schedule_delayed_work(&p_tas256x->irq_work, msecs_to_jiffies(100)); + return IRQ_HANDLED; +} + +static int tas256x_runtime_suspend(struct tas256x_priv *p_tas256x) +{ + dev_dbg(p_tas256x->dev, "%s\n", __func__); + + p_tas256x->mb_runtime_suspend = true; + + if (delayed_work_pending(&p_tas256x->irq_work)) { + dev_dbg(p_tas256x->dev, "cancel IRQ work\n"); + cancel_delayed_work_sync(&p_tas256x->irq_work); + } + + return 0; +} + +static int tas256x_runtime_resume(struct tas256x_priv *p_tas256x) +{ + dev_dbg(p_tas256x->dev, "%s\n", __func__); + + p_tas256x->mb_runtime_suspend = false; + + return 0; +} + +static int tas256x_pm_suspend(struct device *dev) +{ + struct tas256x_priv *p_tas256x = dev_get_drvdata(dev); + + if (!p_tas256x) { + dev_err(p_tas256x->dev, "drvdata is NULL\n"); + return -EINVAL; + } + + mutex_lock(&p_tas256x->codec_lock); + p_tas256x->i2c_suspend = true; + tas256x_runtime_suspend(p_tas256x); + mutex_unlock(&p_tas256x->codec_lock); + return 0; +} + +static int tas256x_pm_resume(struct device *dev) +{ + struct tas256x_priv *p_tas256x = dev_get_drvdata(dev); + + if (!p_tas256x) { + dev_err(p_tas256x->dev, "drvdata is NULL\n"); + return -EINVAL; + } + mutex_lock(&p_tas256x->codec_lock); + p_tas256x->i2c_suspend = false; + tas256x_runtime_resume(p_tas256x); + mutex_unlock(&p_tas256x->codec_lock); + return 0; +} + +#ifdef CONFIG_TAS25XX_ALGO +/*TODO: FIX Use of private data causes crash*/ +struct tas256x_priv *g_p_tas256x; + +void tas256x_software_reset(void *prv_data) +{ + pr_err("[TI-SmartPA:%s]\n", __func__); + schedule_delayed_work(&g_p_tas256x->dc_work, msecs_to_jiffies(10)); +} + +static void dc_work_routine(struct work_struct *work) +{ + struct tas256x_priv *p_tas256x = + container_of(work, struct tas256x_priv, dc_work.work); + + pr_err("[TI-SmartPA:%s] DC in channel = %d\n", __func__, + s_dc_detect.channel); +#ifdef CONFIG_TAS2562_CODEC + mutex_lock(&p_tas256x->codec_lock); +#endif + tas_reload(p_tas256x, s_dc_detect.channel); + +#ifdef CONFIG_TAS2562_CODEC + mutex_unlock(&p_tas256x->codec_lock); +#endif +} +#endif /*CONFIG_TAS25XX_ALGO*/ + +static int tas256x_parse_dt(struct device *dev, struct tas256x_priv *p_tas256x) +{ + struct device_node *np = dev->of_node; + int rc = 0, i = 0; + + rc = of_property_read_u32(np, "ti,channels", &p_tas256x->mn_channels); + if (rc) { + dev_err(p_tas256x->dev, + "Looking up %s property in node %s failed %d\n", + "ti,channels", np->full_name, rc); + goto EXIT; + } else { + dev_dbg(p_tas256x->dev, "ti,channels=%d", + p_tas256x->mn_channels); + } + + /*the device structures array*/ + p_tas256x->devs = + kmalloc(p_tas256x->mn_channels * sizeof(struct tas_device *), + GFP_KERNEL); + for (i = 0; i < p_tas256x->mn_channels; i++) { + p_tas256x->devs[i] = + kmalloc(sizeof(struct tas_device), GFP_KERNEL); + if (p_tas256x->devs[i] == NULL) { + dev_err(p_tas256x->dev, "%s:%u:kmalloc failed!\n", + __func__, __LINE__); + rc = -1; + break; + } + p_tas256x->devs[i]->i2c = p_tas256x->client; + p_tas256x->devs[i]->regmap = p_tas256x->regmap; + + rc = of_property_read_u32(np, dts_tag[i][0], + &p_tas256x->devs[i]->mn_addr); + if (rc) { + dev_err(p_tas256x->dev, + "Looking up %s property in node %s failed %d\n", + dts_tag[i][0], np->full_name, rc); + break; + } else { + dev_dbg(p_tas256x->dev, "%s = 0x%02x", dts_tag[i][0], + p_tas256x->devs[i]->mn_addr); + } + + p_tas256x->devs[i]->mn_reset_gpio = + of_get_named_gpio(np, dts_tag[i][1], 0); + if (!gpio_is_valid(p_tas256x->devs[i]->mn_reset_gpio)) + dev_err(p_tas256x->dev, + "Looking up %s property in node %s failed %d\n", + dts_tag[i][1], np->full_name, + p_tas256x->devs[i]->mn_reset_gpio); + else + dev_dbg(p_tas256x->dev, "%s = %d", dts_tag[i][1], + p_tas256x->devs[i]->mn_reset_gpio); + + p_tas256x->devs[i]->mn_irq_gpio = + of_get_named_gpio(np, dts_tag[i][2], 0); + if (!gpio_is_valid(p_tas256x->devs[i]->mn_irq_gpio)) { + dev_err(p_tas256x->dev, + "Looking up %s property in node %s failed %d\n", + dts_tag[i][2], np->full_name, + p_tas256x->devs[i]->mn_irq_gpio); + } else { + dev_dbg(p_tas256x->dev, "%s = %d", dts_tag[i][2], + p_tas256x->devs[i]->mn_irq_gpio); + } + p_tas256x->devs[i]->spk_control = 1; + } + + if (rc) + goto EXIT; + + rc = of_property_read_u32(np, "ti,iv-width", &p_tas256x->mn_iv_width); + if (rc) { + dev_err(p_tas256x->dev, + "Looking up %s property in node %s failed %d\n", + "ti,iv-width", np->full_name, rc); + } else { + dev_dbg(p_tas256x->dev, "ti,iv-width=0x%x", + p_tas256x->mn_iv_width); + } + + rc = of_property_read_u32(np, "ti,vbat-mon", &p_tas256x->mn_vbat); + if (rc) { + dev_err(p_tas256x->dev, + "Looking up %s property in node %s failed %d\n", + "ti,vbat-mon", np->full_name, rc); + } else { + dev_dbg(p_tas256x->dev, "ti,vbat-mon=0x%x", p_tas256x->mn_vbat); + } +#ifdef CONFIG_TAS25XX_ALGO + /*TODO: Enable if feature is needed*/ + /*tas25xx_parse_algo_dt(np);*/ +#endif /*CONFIG_TAS25XX_ALGO*/ +EXIT: + return rc; +} + +static int tas256x_i2c_probe(struct i2c_client *p_client, + const struct i2c_device_id *id) +{ + struct tas256x_priv *p_tas256x; + int n_result = 0; + int i = 0; + + dev_info(&p_client->dev, "Driver Tag: %s\n", TAS256X_DRIVER_TAG); + dev_info(&p_client->dev, "%s enter\n", __func__); + + p_tas256x = devm_kzalloc(&p_client->dev, sizeof(struct tas256x_priv), + GFP_KERNEL); + if (p_tas256x == NULL) { + /* dev_err(&p_client->dev, "failed to get i2c device\n"); */ + n_result = -ENOMEM; + goto err; + } + + p_tas256x->client = p_client; + p_tas256x->dev = &p_client->dev; + i2c_set_clientdata(p_client, p_tas256x); + dev_set_drvdata(&p_client->dev, p_tas256x); + + p_tas256x->regmap = devm_regmap_init_i2c(p_client, &tas256x_i2c_regmap); + if (IS_ERR(p_tas256x->regmap)) { + n_result = PTR_ERR(p_tas256x->regmap); + dev_err(&p_client->dev, "Failed to allocate register map: %d\n", + n_result); + goto err; + } + + mutex_init(&p_tas256x->dev_lock); + + p_tas256x->read = tas256x_dev_read; + p_tas256x->write = tas256x_dev_write; + p_tas256x->bulk_read = tas256x_dev_bulk_read; + p_tas256x->bulk_write = tas256x_dev_bulk_write; + p_tas256x->update_bits = tas256x_dev_update_bits; + p_tas256x->hw_reset = tas256x_hw_reset; + p_tas256x->enable_irq = tas256x_enable_irq; +#ifdef CODEC_PM + p_tas256x->runtime_suspend = tas256x_runtime_suspend; + p_tas256x->runtime_resume = tas256x_runtime_resume; + p_tas256x->mn_power_state = TAS256X_POWER_SHUTDOWN; +#endif + p_tas256x->mn_power_state = TAS256X_POWER_SHUTDOWN; + + if (p_client->dev.of_node) + tas256x_parse_dt(&p_client->dev, p_tas256x); + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (gpio_is_valid(p_tas256x->devs[i]->mn_reset_gpio)) { + n_result = + gpio_request(p_tas256x->devs[i]->mn_reset_gpio, + reset_gpio_label[i]); + if (n_result) { + dev_err(p_tas256x->dev, + "%s: Failed to request gpio %d\n", + __func__, + p_tas256x->devs[i]->mn_reset_gpio); + n_result = -EINVAL; + goto err; + } + } + } + + tas256x_hw_reset(p_tas256x); + + dev_info(&p_client->dev, "Before SW reset\n"); + /* Reset the chip */ + n_result = tas56x_software_reset(p_tas256x, channel_both); + if (n_result < 0) { + dev_err(&p_client->dev, "I2c fail, %d\n", n_result); + goto err; + } + dev_info(&p_client->dev, "After SW reset\n"); + + for (i = 0; i < p_tas256x->mn_channels; i++) { + n_result = tas56x_get_chipid( + p_tas256x, &(p_tas256x->devs[i]->mChipID), + (i == 0) ? channel_left : channel_right); + switch (p_tas256x->devs[i]->mChipID) { + case 0x10: + case 0x20: + dev_dbg(p_tas256x->dev, "TAS2562 chip"); + p_tas256x->devs[i]->device_id = DEVICE_TAS2562; + p_tas256x->devs[i]->dev_ops.tas_init = NULL; + p_tas256x->devs[i]->dev_ops.tas_probe = tas2562_probe; + break; + case 0x00: + dev_dbg(p_tas256x->dev, "TAS2564 chip"); + p_tas256x->devs[i]->device_id = DEVICE_TAS2564; + p_tas256x->devs[i]->dev_ops.tas_init = tas2564_specific; + p_tas256x->devs[i]->dev_ops.tas_probe = tas2564_probe; + break; + default: + dev_dbg(p_tas256x->dev, "TAS2558 chip"); + p_tas256x->devs[i]->device_id = DEVICE_TAS2558; + p_tas256x->devs[i]->dev_ops.tas_init = tas2558_specific; + p_tas256x->devs[i]->dev_ops.tas_probe = NULL; + break; + } + } + + INIT_DELAYED_WORK(&p_tas256x->irq_work, irq_work_routine); + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (gpio_is_valid(p_tas256x->devs[i]->mn_irq_gpio)) { + n_result = gpio_request(p_tas256x->devs[i]->mn_irq_gpio, + irq_gpio_label[i]); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "%s:%u: ch 0x%02x: GPIO %d request error\n", + __func__, __LINE__, + p_tas256x->devs[i]->mn_addr, + p_tas256x->devs[i]->mn_irq_gpio); + goto err; + } + gpio_direction_input(p_tas256x->devs[i]->mn_irq_gpio); + /*tas256x_dev_write(p_tas256x, + * (i == 0)? channel_left : channel_right, + * TAS256X_MISCCONFIGURATIONREG0, 0xce); + */ + tas256x_set_misc_config(p_tas256x, 0, + (i == 0) ? channel_left : + channel_right); + + p_tas256x->devs[i]->mn_irq = + gpio_to_irq(p_tas256x->devs[i]->mn_irq_gpio); + dev_info(p_tas256x->dev, "irq = %d\n", + p_tas256x->devs[i]->mn_irq); + + n_result = request_threaded_irq( + p_tas256x->devs[i]->mn_irq, tas256x_irq_handler, + NULL, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + p_client->name, p_tas256x); + if (n_result < 0) { + dev_err(p_tas256x->dev, + "request_irq failed, %d\n", n_result); + goto err; + } + disable_irq_nosync(p_tas256x->devs[i]->mn_irq); + } + } + + tas256x_enable_irq(p_tas256x, true); + INIT_DELAYED_WORK(&p_tas256x->init_work, init_work_routine); + +#ifdef CONFIG_TAS256X_CODEC + mutex_init(&p_tas256x->codec_lock); + n_result = tas256x_register_codec(p_tas256x); + if (n_result < 0) { + dev_err(p_tas256x->dev, "register codec failed, %d\n", + n_result); + goto err; + } +#endif + +#ifdef CONFIG_TAS256X_MISC + mutex_init(&p_tas256x->file_lock); + n_result = tas256x_register_misc(p_tas256x); + if (n_result < 0) { + dev_err(p_tas256x->dev, "register codec failed %d\n", n_result); + goto err; + } +#endif + +#ifdef CONFIG_TAS25XX_ALGO + INIT_DELAYED_WORK(&p_tas256x->dc_work, dc_work_routine); + g_p_tas256x = p_tas256x; + register_tas256x_reset_func(tas256x_software_reset, &s_dc_detect); +#endif /*CONFIG_TAS25XX_ALGO*/ + +err: + return n_result; +} + +static int tas256x_i2c_remove(struct i2c_client *p_client) +{ + int i = 0; + struct tas256x_priv *p_tas256x = i2c_get_clientdata(p_client); + + dev_info(p_tas256x->dev, "%s\n", __func__); + +#ifdef CONFIG_TAS256X_CODEC + tas256x_deregister_codec(p_tas256x); + mutex_destroy(&p_tas256x->codec_lock); +#endif + +#ifdef CONFIG_TAS256X_MISC + tas256x_deregister_misc(p_tas256x); + mutex_destroy(&p_tas256x->file_lock); +#endif + + for (i = 0; i < p_tas256x->mn_channels; i++) { + if (gpio_is_valid(p_tas256x->devs[i]->mn_reset_gpio)) + gpio_free(p_tas256x->devs[i]->mn_reset_gpio); + if (gpio_is_valid(p_tas256x->devs[i]->mn_irq_gpio)) + gpio_free(p_tas256x->devs[i]->mn_irq_gpio); + if (p_tas256x->devs[i]) + kfree(p_tas256x->devs[i]); + } + + if (p_tas256x->devs) + kfree(p_tas256x->devs); + + return 0; +} + +static const struct i2c_device_id tas256x_i2c_id[] = { + { "tas256x", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, tas256x_i2c_id); + +#if defined(CONFIG_OF) +static const struct of_device_id tas256x_of_match[] = { + { .compatible = "ti, tas256x" }, + { .compatible = "ti, tas2562" }, + { .compatible = "ti, tas2564" }, + {}, +}; +MODULE_DEVICE_TABLE(of, tas256x_of_match); +#endif + +static const struct dev_pm_ops tas256x_pm_ops = { .suspend = tas256x_pm_suspend, + .resume = tas256x_pm_resume }; + +static struct i2c_driver tas256x_i2c_driver = { + .driver = { + .name = "tas256x", + .owner = THIS_MODULE, +#if defined(CONFIG_OF) + .of_match_table = of_match_ptr(tas256x_of_match), +#endif + .pm = &tas256x_pm_ops, + }, + .probe = tas256x_i2c_probe, + .remove = tas256x_i2c_remove, + .id_table = tas256x_i2c_id, +}; + +module_i2c_driver(tas256x_i2c_driver); + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("TAS256X I2C Smart Amplifier driver"); +MODULE_LICENSE("GPL v2"); +#endif diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x.c b/techpack/audio/asoc/codecs/tas256x/tas256x.c new file mode 100644 index 000000000000..d785c8fcebea --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas256x.c @@ -0,0 +1,1557 @@ +#include "tas256x.h" +#include "tas2562.h" +#include "tas2564.h" +#include "tas256x-device.h" + +#define LOG_TAG "[tas256x]" + +#define TAS256X_MDELAY 0xFFFFFFFE +#define TAS256X_MSLEEP 0xFFFFFFFD +#define TAS256X_IVSENSER_ENABLE 1 +#define TAS256X_IVSENSER_DISABLE 0 +static char p_icn_threshold[] = { 0x00, 0x01, 0x2f, 0x2c }; +static char p_icn_hysteresis[] = { 0x00, 0x01, 0x5d, 0xc0 }; + +static unsigned int p_tas256x_classh_d_data[] = { + /* reg address size values */ + TAS256X_CLASSHHEADROOM, + 0x4, + 0x09, + 0x99, + 0x99, + 0x9a, + TAS256X_CLASSHHYSTERESIS, + 0x4, + 0x0, + 0x0, + 0x0, + 0x0, + TAS256X_CLASSHMTCT, + 0x4, + 0xb, + 0x0, + 0x0, + 0x0, + TAS256X_VBATFILTER, + 0x1, + 0x38, + TAS256X_CLASSHRELEASETIMER, + 0x1, + 0x3c, + TAS256X_BOOSTSLOPE, + 0x1, + 0x78, + TAS256X_TESTPAGECONFIGURATION, + 0x1, + 0xd, + TAS256X_CLASSDCONFIGURATION3, + 0x1, + 0x8e, + TAS256X_CLASSDCONFIGURATION2, + 0x1, + 0x49, + TAS256X_CLASSDCONFIGURATION4, + 0x1, + 0x21, + TAS256X_CLASSDCONFIGURATION1, + 0x1, + 0x80, + TAS256X_EFFICIENCYCONFIGURATION, + 0x1, + 0xc1, + 0xFFFFFFFF, + 0xFFFFFFFF +}; + +static char HPF_reverse_path[] = { 0x7F, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + +static char dvc_pcm[57][4] = { + { 0x00, 0x00, 0x0D, 0x43 }, { 0x00, 0x00, 0x10, 0xB3 }, + { 0x00, 0x00, 0x15, 0x05 }, { 0x00, 0x00, 0x1A, 0x77 }, + { 0x00, 0x00, 0x21, 0x51 }, { 0x00, 0x00, 0x29, 0xF1 }, + { 0x00, 0x00, 0x34, 0xCE }, { 0x00, 0x00, 0x42, 0x7A }, + { 0x00, 0x00, 0x53, 0xB0 }, { 0x00, 0x00, 0x69, 0x5B }, + { 0x00, 0x00, 0x84, 0xA3 }, { 0x00, 0x00, 0xA6, 0xFA }, + { 0x00, 0x00, 0xD2, 0x37 }, { 0x00, 0x01, 0x08, 0xA5 }, + { 0x00, 0x01, 0x4D, 0x2A }, { 0x00, 0x01, 0xA3, 0x6E }, + { 0x00, 0x02, 0x10, 0x08 }, { 0x00, 0x02, 0x98, 0xC1 }, + { 0x00, 0x03, 0x44, 0xE0 }, { 0x00, 0x04, 0x1D, 0x90 }, + { 0x00, 0x05, 0x2E, 0x5B }, { 0x00, 0x06, 0x85, 0xC8 }, + { 0x00, 0x08, 0x36, 0x22 }, { 0x00, 0x0A, 0x56, 0x6D }, + { 0x00, 0x0D, 0x03, 0xA7 }, { 0x00, 0x10, 0x62, 0x4E }, + { 0x00, 0x14, 0xA0, 0x51 }, { 0x00, 0x19, 0xF7, 0x86 }, + { 0x00, 0x20, 0xB0, 0xBD }, { 0x00, 0x29, 0x27, 0x9E }, + { 0x00, 0x33, 0xCF, 0x8E }, { 0x00, 0x41, 0x39, 0xD3 }, + { 0x00, 0x52, 0x1D, 0x51 }, { 0x00, 0x67, 0x60, 0x45 }, + { 0x00, 0x82, 0x24, 0x8A }, { 0x00, 0xA3, 0xD7, 0x0A }, + { 0x00, 0xCE, 0x43, 0x29 }, { 0x01, 0x03, 0xAB, 0x3D }, + { 0x01, 0x46, 0xE7, 0x5E }, { 0x01, 0x9B, 0x8C, 0x27 }, + { 0x02, 0x06, 0x1B, 0x8A }, { 0x02, 0x8C, 0x42, 0x40 }, + { 0x03, 0x35, 0x25, 0x29 }, { 0x04, 0x09, 0xC2, 0xB1 }, + { 0x05, 0x15, 0x6D, 0x69 }, { 0x06, 0x66, 0x66, 0x66 }, + { 0x08, 0x0E, 0x9F, 0x97 }, { 0x0A, 0x24, 0xB0, 0x63 }, + { 0x0C, 0xC5, 0x09, 0xAC }, { 0x10, 0x13, 0x79, 0x88 }, + { 0x14, 0x3D, 0x13, 0x62 }, { 0x19, 0x7A, 0x96, 0x7F }, + { 0x20, 0x13, 0x73, 0x9E }, { 0x28, 0x61, 0x9A, 0xEA }, + { 0x32, 0xD6, 0x46, 0x18 }, { 0x40, 0x00, 0x00, 0x00 }, + { 0x50, 0x92, 0x3B, 0xE4 } +}; + +static char lim_max_attn[16][4] = { + { 0x14, 0x49, 0x60, 0xC5 }, { 0x16, 0xC3, 0x10, 0xE3 }, + { 0x19, 0x8A, 0x13, 0x57 }, { 0x1C, 0xA7, 0xD7, 0x68 }, + { 0x20, 0x26, 0xF3, 0x10 }, { 0x24, 0x13, 0x46, 0xF6 }, + { 0x28, 0x7A, 0x26, 0xC5 }, { 0x2D, 0x6A, 0x86, 0x6F }, + { 0x32, 0xF5, 0x2C, 0xFF }, { 0x39, 0x2C, 0xED, 0x8E }, + { 0x40, 0x26, 0xE7, 0x3D }, { 0x47, 0xFA, 0xCC, 0xF0 }, + { 0x50, 0xC3, 0x35, 0xD4 }, { 0x5A, 0x9D, 0xF7, 0xAC }, + { 0x65, 0xAC, 0x8C, 0x2F }, { 0x72, 0x14, 0x82, 0xC0 } +}; + +static char vbat_lim_max_thd[27][4] = { + { 0x14, 0x00, 0x00, 0x00 }, { 0x18, 0x00, 0x00, 0x00 }, + { 0x1C, 0x00, 0x00, 0x00 }, { 0x20, 0x00, 0x00, 0x00 }, + { 0x24, 0x00, 0x00, 0x00 }, { 0x28, 0x00, 0x00, 0x00 }, + { 0x2C, 0x00, 0x00, 0x00 }, { 0x30, 0x00, 0x00, 0x00 }, + { 0x34, 0x00, 0x00, 0x00 }, { 0x38, 0x00, 0x00, 0x00 }, + { 0x3C, 0x00, 0x00, 0x00 }, { 0x40, 0x00, 0x00, 0x00 }, + { 0x44, 0x00, 0x00, 0x00 }, { 0x48, 0x00, 0x00, 0x00 }, + { 0x4C, 0x00, 0x00, 0x00 }, { 0x50, 0x00, 0x00, 0x00 }, + { 0x54, 0x00, 0x00, 0x00 }, { 0x58, 0x00, 0x00, 0x00 }, + { 0x5C, 0x00, 0x00, 0x00 }, { 0x60, 0x00, 0x00, 0x00 }, + { 0x64, 0x00, 0x00, 0x00 }, { 0x68, 0x00, 0x00, 0x00 }, + { 0x6C, 0x00, 0x00, 0x00 }, { 0x70, 0x00, 0x00, 0x00 }, + { 0x74, 0x00, 0x00, 0x00 }, { 0x78, 0x00, 0x00, 0x00 }, + { 0x7C, 0x00, 0x00, 0x00 } +}; + +static char vbat_lim_min_thd[27][4] = { + { 0x14, 0x00, 0x00, 0x00 }, { 0x18, 0x00, 0x00, 0x00 }, + { 0x1C, 0x00, 0x00, 0x00 }, { 0x20, 0x00, 0x00, 0x00 }, + { 0x24, 0x00, 0x00, 0x00 }, { 0x28, 0x00, 0x00, 0x00 }, + { 0x2C, 0x00, 0x00, 0x00 }, { 0x30, 0x00, 0x00, 0x00 }, + { 0x34, 0x00, 0x00, 0x00 }, { 0x38, 0x00, 0x00, 0x00 }, + { 0x3C, 0x00, 0x00, 0x00 }, { 0x40, 0x00, 0x00, 0x00 }, + { 0x44, 0x00, 0x00, 0x00 }, { 0x48, 0x00, 0x00, 0x00 }, + { 0x4C, 0x00, 0x00, 0x00 }, { 0x50, 0x00, 0x00, 0x00 }, + { 0x54, 0x00, 0x00, 0x00 }, { 0x58, 0x00, 0x00, 0x00 }, + { 0x5C, 0x00, 0x00, 0x00 }, { 0x60, 0x00, 0x00, 0x00 }, + { 0x64, 0x00, 0x00, 0x00 }, { 0x68, 0x00, 0x00, 0x00 }, + { 0x6C, 0x00, 0x00, 0x00 }, { 0x70, 0x00, 0x00, 0x00 }, + { 0x74, 0x00, 0x00, 0x00 }, { 0x78, 0x00, 0x00, 0x00 }, + { 0x7C, 0x00, 0x00, 0x00 } +}; + +static char vbat_lim_infl_pt[41][4] = { + { 0x20, 0x00, 0x00, 0x00 }, { 0x21, 0x99, 0x99, 0x99 }, + { 0x23, 0x33, 0x33, 0x33 }, { 0x24, 0xCC, 0xCC, 0xCC }, + { 0x26, 0x66, 0x66, 0x66 }, { 0x28, 0x00, 0x00, 0x00 }, + { 0x29, 0x99, 0x99, 0x99 }, { 0x2B, 0x33, 0x33, 0x33 }, + { 0x2C, 0xCC, 0xCC, 0xCC }, { 0x2E, 0x66, 0x66, 0x66 }, + { 0x30, 0x00, 0x00, 0x00 }, { 0x31, 0x99, 0x99, 0x99 }, + { 0x33, 0x33, 0x33, 0x33 }, { 0x34, 0xCC, 0xCC, 0xCC }, + { 0x36, 0x66, 0x66, 0x66 }, { 0x38, 0x00, 0x00, 0x00 }, + { 0x39, 0x99, 0x99, 0x99 }, { 0x3B, 0x33, 0x33, 0x33 }, + { 0x3C, 0xCC, 0xCC, 0xCC }, { 0x3E, 0x66, 0x66, 0x66 }, + { 0x40, 0x00, 0x00, 0x00 }, { 0x41, 0x99, 0x99, 0x99 }, + { 0x43, 0x33, 0x33, 0x33 }, { 0x44, 0xCC, 0xCC, 0xCC }, + { 0x46, 0x66, 0x66, 0x66 }, { 0x48, 0x00, 0x00, 0x00 }, + { 0x49, 0x99, 0x99, 0x99 }, { 0x4B, 0x33, 0x33, 0x33 }, + { 0x4C, 0xCC, 0xCC, 0xCC }, { 0x4E, 0x66, 0x66, 0x66 }, + { 0x4F, 0xFF, 0xFF, 0xFF }, { 0x51, 0x99, 0x99, 0x99 }, + { 0x53, 0x33, 0x33, 0x33 }, { 0x54, 0xCC, 0xCC, 0xCC }, + { 0x56, 0x66, 0x66, 0x66 }, { 0x57, 0xFF, 0xFF, 0xFF }, + { 0x59, 0x99, 0x99, 0x99 }, { 0x5B, 0x33, 0x33, 0x33 }, + { 0x5C, 0xCC, 0xCC, 0xCC }, { 0x5E, 0x66, 0x66, 0x66 }, + { 0x5F, 0xFF, 0xFF, 0xFF } +}; + +static char vbat_lim_track_slope[7][4] = { + { 0x10, 0x00, 0x00, 0x00 }, { 0x18, 0x00, 0x00, 0x00 }, + { 0x20, 0x00, 0x00, 0x00 }, { 0x28, 0x00, 0x00, 0x00 }, + { 0x30, 0x00, 0x00, 0x00 }, { 0x38, 0x00, 0x00, 0x00 }, + { 0x40, 0x00, 0x00, 0x00 } +}; + +static char bop_thd[16][4] = { + { 0x28, 0x00, 0x00, 0x00 }, { 0x29, 0x99, 0x99, 0x99 }, + { 0x2B, 0x33, 0x33, 0x33 }, { 0x2C, 0xCC, 0xCC, 0xCC }, + { 0x2E, 0x66, 0x66, 0x66 }, { 0x30, 0x00, 0x00, 0x00 }, + { 0x31, 0x99, 0x99, 0x99 }, { 0x33, 0x33, 0x33, 0x33 }, + { 0x34, 0xCC, 0xCC, 0xCC }, { 0x36, 0x66, 0x66, 0x66 }, + { 0x38, 0x00, 0x00, 0x00 }, { 0x39, 0x99, 0x99, 0x99 }, + { 0x3B, 0x33, 0x33, 0x33 }, { 0x3C, 0xCC, 0xCC, 0xCC }, + { 0x3E, 0x66, 0x66, 0x66 }, { 0x40, 0x00, 0x00, 0x00 } +}; + +static char bsd_thd[16][4] = { + { 0x28, 0x00, 0x00, 0x00 }, { 0x29, 0x99, 0x99, 0x99 }, + { 0x2B, 0x33, 0x33, 0x33 }, { 0x2C, 0xCC, 0xCC, 0xCC }, + { 0x2E, 0x66, 0x66, 0x66 }, { 0x30, 0x00, 0x00, 0x00 }, + { 0x31, 0x99, 0x99, 0x99 }, { 0x33, 0x33, 0x33, 0x33 }, + { 0x34, 0xCC, 0xCC, 0xCC }, { 0x36, 0x66, 0x66, 0x66 }, + { 0x38, 0x00, 0x00, 0x00 }, { 0x39, 0x99, 0x99, 0x99 }, + { 0x3B, 0x33, 0x33, 0x33 }, { 0x3C, 0xCC, 0xCC, 0xCC }, + { 0x3E, 0x66, 0x66, 0x66 }, { 0x40, 0x00, 0x00, 0x00 } +}; + +static int tas256x_i2c_load_data(struct tas256x_priv *p_tas256x, + enum channel chn, unsigned int *p_data) +{ + unsigned int n_register; + unsigned int *n_data; + unsigned char buf[128]; + unsigned int n_length = 0; + unsigned int i = 0; + unsigned int n_size = 0; + int n_result = 0; + + do { + n_register = p_data[n_length]; + n_size = p_data[n_length + 1]; + n_data = &p_data[n_length + 2]; + if (n_register == TAS256X_MSLEEP) { + msleep(n_data[0]); + pr_debug("%s %s, msleep = %d\n", LOG_TAG, __func__, + n_data[0]); + } else if (n_register == TAS256X_MDELAY) { + msleep(n_data[0]); + pr_debug("%s %s, mdelay = %d\n", LOG_TAG, __func__, + n_data[0]); + } else { + if (n_register != 0xFFFFFFFF) { + if (n_size > 128) { + pr_err("%s %s, Line=%d, invalid size, maximum is 128 bytes!\n", + LOG_TAG, __func__, __LINE__); + break; + } + if (n_size > 1) { + for (i = 0; i < n_size; i++) + buf[i] = (unsigned char) + n_data[i]; + n_result = p_tas256x->bulk_write( + p_tas256x, chn, n_register, buf, + n_size); + if (n_result < 0) + break; + } else if (n_size == 1) { + n_result = + p_tas256x->write(p_tas256x, chn, + n_register, + n_data[0]); + if (n_result < 0) + break; + } else { + pr_err("%s %s, Line=%d,invalid size, minimum is 1 bytes!\n", + LOG_TAG, __func__, __LINE__); + } + } + } + n_length = n_length + 2 + p_data[n_length + 1]; + } while (n_register != 0xFFFFFFFF); + return n_result; +} + +int tas256x_update_default_params(struct tas256x_priv *p_tas256x, int ch) +{ + int n_result = 0; + + /*Initialize to default values*/ + if (p_tas256x->devs[ch - 1]->device_id == DEVICE_TAS2562) { + p_tas256x->devs[ch - 1]->dvc_pcm = 55; /*0dB*/ + p_tas256x->devs[ch - 1]->lim_max_attn = 7; /*-9dB*/ + p_tas256x->devs[ch - 1]->lim_thr_max = 13; /*9V*/ + p_tas256x->devs[ch - 1]->lim_thr_min = 3; /*4V*/ + p_tas256x->devs[ch - 1]->lim_infl_pt = 13; /*3.3V*/ + p_tas256x->devs[ch - 1]->lim_trk_slp = 0; /*1 V/V*/ + p_tas256x->devs[ch - 1]->bop_thd = 4; /*2.9 V*/ + p_tas256x->devs[ch - 1]->bosd_thd = 2; /*2.7 V*/ + p_tas256x->devs[ch - 1]->bst_vltg = 0xA; /*Mode = speaker*/ + p_tas256x->devs[ch - 1]->bst_ilm = 0x36; /*0dB*/ + p_tas256x->devs[ch - 1]->lim_switch = 0; /*-9dB*/ + p_tas256x->devs[ch - 1]->lim_att_rate = 1; /*9V*/ + p_tas256x->devs[ch - 1]->lim_att_stp_size = 1; /*4V*/ + p_tas256x->devs[ch - 1]->lim_rel_rate = 6; /*3.3V*/ + p_tas256x->devs[ch - 1]->lim_rel_stp_size = 1; /*1 V/V*/ + p_tas256x->devs[ch - 1]->bop_enable = 1; /*2.9 V*/ + p_tas256x->devs[ch - 1]->bop_mute = 0; /*2.7 V*/ + p_tas256x->devs[ch - 1]->bosd_enable = 0; /*3.3V*/ + p_tas256x->devs[ch - 1]->bop_att_rate = 1; /*1 V/V*/ + p_tas256x->devs[ch - 1]->bop_att_stp_size = 1; /*2.9 V*/ + p_tas256x->devs[ch - 1]->bop_hld_time = 6; /*2.7 V*/ + p_tas256x->devs[ch - 1]->vbat_lpf = 2; /*2.7 V*/ + p_tas256x->devs[ch - 1]->rx_cfg = 0; + } else if (p_tas256x->devs[ch - 1]->device_id == DEVICE_TAS2564) { + p_tas256x->devs[ch - 1]->rx_mode = 0; /*Mode = speaker*/ + p_tas256x->devs[ch - 1]->dvc_pcm = 55; /*0dB*/ + p_tas256x->devs[ch - 1]->lim_max_attn = 7; /*-9dB*/ + p_tas256x->devs[ch - 1]->lim_thr_max = 13; /*9V*/ + p_tas256x->devs[ch - 1]->lim_thr_min = 3; /*4V*/ + p_tas256x->devs[ch - 1]->lim_infl_pt = 13; /*3.3V*/ + p_tas256x->devs[ch - 1]->lim_trk_slp = 0; /*1 V/V*/ + p_tas256x->devs[ch - 1]->bop_thd = 4; /*2.9 V*/ + p_tas256x->devs[ch - 1]->bosd_thd = 2; /*2.7 V*/ + p_tas256x->devs[ch - 1]->bst_vltg = 13; /*Mode = speaker*/ + p_tas256x->devs[ch - 1]->bst_ilm = 0x39; /*0dB*/ + p_tas256x->devs[ch - 1]->lim_switch = 0; /*-9dB*/ + p_tas256x->devs[ch - 1]->lim_att_rate = 1; /*9V*/ + p_tas256x->devs[ch - 1]->lim_att_stp_size = 1; /*4V*/ + p_tas256x->devs[ch - 1]->lim_rel_rate = 6; /*3.3V*/ + p_tas256x->devs[ch - 1]->lim_rel_stp_size = 1; /*1 V/V*/ + p_tas256x->devs[ch - 1]->bop_enable = 1; /*2.9 V*/ + p_tas256x->devs[ch - 1]->bop_mute = 0; /*2.7 V*/ + p_tas256x->devs[ch - 1]->bosd_enable = 0; /*3.3V*/ + p_tas256x->devs[ch - 1]->bop_att_rate = 1; /*1 V/V*/ + p_tas256x->devs[ch - 1]->bop_att_stp_size = 1; /*2.9 V*/ + p_tas256x->devs[ch - 1]->bop_hld_time = 6; /*2.7 V*/ + p_tas256x->devs[ch - 1]->vbat_lpf = 2; /*2.7 V*/ + p_tas256x->devs[ch - 1]->rx_cfg = 0; + } + return n_result; +} + +int tas256x_set_power_up(struct tas256x_priv *p_tas256x, enum channel chn) +{ + int n_result = 0; + + n_result = p_tas256x->update_bits( + p_tas256x, chn, TAS256X_POWERCONTROL, + TAS256X_POWERCONTROL_OPERATIONALMODE10_MASK, + TAS256X_POWERCONTROL_OPERATIONALMODE10_ACTIVE); + + /* Let Power on the device */ + msleep(20); + + /* Enable Comparator Hysteresis */ + n_result = p_tas256x->update_bits(p_tas256x, chn, TAS256X_MISC_CLASSD, + TAS256X_CMP_HYST_MASK, + (0x01 << TAS256X_CMP_HYST_SHIFT)); + return n_result; +} + +int tas256x_set_power_mute(struct tas256x_priv *p_tas256x, enum channel chn) +{ + int n_result = 0; + + /*Disable Comparator Hysteresis before Power Mute */ + n_result = p_tas256x->update_bits(p_tas256x, chn, TAS256X_MISC_CLASSD, + TAS256X_CMP_HYST_MASK, + (0x00 << TAS256X_CMP_HYST_SHIFT)); + + n_result = p_tas256x->update_bits( + p_tas256x, chn, TAS256X_POWERCONTROL, + TAS256X_POWERCONTROL_OPERATIONALMODE10_MASK, + TAS256X_POWERCONTROL_OPERATIONALMODE10_MUTE); + + return n_result; +} + +int tas256x_set_power_shutdown(struct tas256x_priv *p_tas256x, enum channel chn) +{ + int n_result = 0; + /*Disable Comparator Hysteresis before Power Down */ + n_result = p_tas256x->update_bits(p_tas256x, chn, TAS256X_MISC_CLASSD, + TAS256X_CMP_HYST_MASK, + (0x00 << TAS256X_CMP_HYST_SHIFT)); + + n_result = p_tas256x->update_bits( + p_tas256x, chn, TAS256X_POWERCONTROL, + TAS256X_POWERCONTROL_OPERATIONALMODE10_MASK, + TAS256X_POWERCONTROL_OPERATIONALMODE10_SHUTDOWN); + + /*Device Shutdown need 20ms after shutdown writes are made*/ + msleep(20); + + return n_result; +} + +int tas256x_power_check(struct tas256x_priv *p_tas256x, int *state, int ch) +{ + int n_result = 0; + int status; + + n_result = + p_tas256x->read(p_tas256x, ch, TAS256X_POWERCONTROL, &status); + + status &= TAS256X_POWERCONTROL_OPERATIONALMODE10_MASK; + + if ((status != TAS256X_POWERCONTROL_OPERATIONALMODE10_SHUTDOWN) && + (status != TAS256X_POWERCONTROL_OPERATIONALMODE10_MUTE)) + *state = 1; + else + *state = 0; + + return n_result; +} + +/* + *bool enable = 1; IV Sense Power UP = 0; + * IV Sense Power Down + */ +int tas256x_iv_sense_enable_set(struct tas256x_priv *p_tas256x, bool enable, + int ch) +{ + int n_result = 0; + + if (enable) /*IV Sense Power Up*/ + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_POWERCONTROL, + TAS256X_POWERCONTROL_ISNSPOWER_MASK | + TAS256X_POWERCONTROL_VSNSPOWER_MASK, + TAS256X_POWERCONTROL_VSNSPOWER_ACTIVE | + TAS256X_POWERCONTROL_ISNSPOWER_ACTIVE); + else /*IV Sense Power Down*/ + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_POWERCONTROL, + TAS256X_POWERCONTROL_ISNSPOWER_MASK | + TAS256X_POWERCONTROL_VSNSPOWER_MASK, + TAS256X_POWERCONTROL_VSNSPOWER_POWEREDDOWN | + TAS256X_POWERCONTROL_ISNSPOWER_POWEREDDOWN); + + p_tas256x->iv_enable = enable; + return n_result; +} + +bool tas256x_iv_sense_enable_get(struct tas256x_priv *p_tas256x, int ch) +{ + int n_result = 0; + bool enable = 0; + int value = 0; + + n_result = p_tas256x->read(p_tas256x, ch, TAS256X_POWERCONTROL, &value); + if (n_result < 0) + pr_err("%s can't get ivsensor state %s, L=%d\n", LOG_TAG, + __func__, __LINE__); + else if (((value & TAS256X_POWERCONTROL_ISNSPOWER_MASK) == + TAS256X_POWERCONTROL_ISNSPOWER_ACTIVE) && + ((value & TAS256X_POWERCONTROL_VSNSPOWER_MASK) == + TAS256X_POWERCONTROL_VSNSPOWER_ACTIVE)) { + enable = TAS256X_IVSENSER_ENABLE; + } else { + enable = TAS256X_IVSENSER_DISABLE; + } + return enable; +} + +/*No need channel argument*/ +int tas256x_iv_slot_config(struct tas256x_priv *p_tas256x) +{ + int n_result = 0; + + if (p_tas256x->mn_channels == 2) { + if (p_tas256x->mn_slot_width == 16) { + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG5, + 0xff, 0x41); + + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG6, + 0xff, 0x40); + + p_tas256x->update_bits(p_tas256x, channel_right, + TAS256X_TDMCONFIGURATIONREG5, + 0xff, 0x43); + + p_tas256x->update_bits(p_tas256x, channel_right, + TAS256X_TDMCONFIGURATIONREG6, + 0xff, 0x42); + } else { + if (p_tas256x->mn_iv_width == 8) { + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG5, 0xff, + 0x41); + + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG6, 0xff, + 0x40); + + p_tas256x->update_bits( + p_tas256x, channel_right, + TAS256X_TDMCONFIGURATIONREG5, 0xff, + 0x45); + + p_tas256x->update_bits( + p_tas256x, channel_right, + TAS256X_TDMCONFIGURATIONREG6, 0xff, + 0x44); + + if (p_tas256x->mn_vbat == 1) { + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG7, + 0xff, 0x42); + + p_tas256x->update_bits( + p_tas256x, channel_right, + TAS256X_TDMCONFIGURATIONREG7, + 0xff, 0x46); + } + } else { + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG5, 0xff, + 0x42); + + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG6, 0xff, + 0x40); + + p_tas256x->update_bits( + p_tas256x, channel_right, + TAS256X_TDMCONFIGURATIONREG5, 0xff, + 0x46); + + p_tas256x->update_bits( + p_tas256x, channel_right, + TAS256X_TDMCONFIGURATIONREG6, 0xff, + 0x44); + } + } + } else if ((p_tas256x->mn_channels == 1) && + (p_tas256x->mn_slot_width == 32)) { + if (p_tas256x->mn_iv_width == 16) { + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK, + TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS); + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG5, + 0xff, 0x44); + + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG6, + 0xff, 0x40); + } else if (p_tas256x->mn_iv_width == 12) { + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK, + TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS); + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG5, + 0xff, 0x41); + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG6, + 0xff, 0x40); + if (p_tas256x->mn_vbat == 1) + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG7, 0xff, + 0x44); + } + } else if ((p_tas256x->mn_channels == 1) && + (p_tas256x->mn_slot_width == 16)) { + if (p_tas256x->mn_iv_width == 16) { + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK, + TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS); + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG5, + 0xff, 0x42); + + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG6, + 0xff, 0x40); + } else if (p_tas256x->mn_iv_width == 12) { + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK, + TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS); + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG5, + 0xff, 0x41); + p_tas256x->update_bits(p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG6, + 0xff, 0x40); + if (p_tas256x->mn_vbat == 1) + p_tas256x->update_bits( + p_tas256x, channel_left, + TAS256X_TDMCONFIGURATIONREG7, 0xff, + 0x43); + } + } else { + pr_err("%s %s, wrong params, slot %d\n", LOG_TAG, __func__, + p_tas256x->mn_slot_width); + } + + return n_result; +} + +/*No need channel argument*/ +int tas256x_iv_bitwidth_config(struct tas256x_priv *p_tas256x) +{ + int n_result = 0; + + if (p_tas256x->mn_iv_width == 8) + n_result = p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_MASK, + TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_8BITS); + else if (p_tas256x->mn_iv_width == 12) + n_result = p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK, + TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS); + else /*mn_iv_width == 16*/ + n_result = p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK, + TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS); + + return n_result; +} + +/**/ +int tas256x_set_samplerate(struct tas256x_priv *p_tas256x, int samplerate) +{ + int n_result = 0; + + switch (samplerate) { + case 48000: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ); + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_44_1_48KHZ); + break; + case 44100: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ); + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_44_1_48KHZ); + break; + case 96000: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ); + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_88_2_96KHZ); + break; + case 88200: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ); + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_88_2_96KHZ); + break; + case 19200: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ); + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_176_4_192KHZ); + break; + case 17640: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ); + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG0, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK, + TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_176_4_192KHZ); + break; + default: + pr_info("%s %s, unsupported sample rate, %d\n", LOG_TAG, + __func__, samplerate); + } + + p_tas256x->mn_sampling_rate = samplerate; + + return n_result; +} + +/* + *rx_edge = 0; Falling + *= 1; Rising + */ +int tas256x_rx_set_fmt(struct tas256x_priv *p_tas256x, unsigned int rx_edge, + unsigned int rx_start_slot) +{ + int n_result = 0; + + if (rx_edge) + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG1, + TAS256X_TDMCONFIGURATIONREG1_RXEDGE_MASK, + TAS256X_TDMCONFIGURATIONREG1_RXEDGE_RISING); + else + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG1, + TAS256X_TDMCONFIGURATIONREG1_RXEDGE_MASK, + TAS256X_TDMCONFIGURATIONREG1_RXEDGE_FALLING); + + p_tas256x->update_bits( + p_tas256x, channel_left, TAS256X_TDMCONFIGURATIONREG1, + TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_MASK, + (rx_start_slot + << TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_SHIFT)); + + if (p_tas256x->mn_channels == 2) + p_tas256x->update_bits( + p_tas256x, channel_right, TAS256X_TDMCONFIGURATIONREG1, + TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_MASK, + (rx_start_slot + << TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_SHIFT)); + + return n_result; +} + +int tas256x_rx_set_slot(struct tas256x_priv *p_tas256x, int slot_width) +{ + int n_result = -1; + + switch (slot_width) { + case 16: + n_result = p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_MASK, + TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_16BITS); + break; + case 24: + n_result = p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_MASK, + TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_24BITS); + break; + case 32: + n_result = p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_MASK, + TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_32BITS); + break; + case 0: + /* Do not change slot width */ + break; + } + + if (n_result == 0) + p_tas256x->mn_slot_width = slot_width; + + return n_result; +} + +int tas256x_rx_set_bitwidth(struct tas256x_priv *p_tas256x, int bitwidth) +{ + int n_result = 0; + + switch (bitwidth) { + case 16: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_MASK, + TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_16BITS); + break; + case 24: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_MASK, + TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_24BITS); + break; + case 32: + p_tas256x->update_bits( + p_tas256x, channel_both, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_MASK, + TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_32BITS); + break; + + default: + pr_info("%s Not supported params format\n", LOG_TAG); + break; + } + + return n_result; +} + +int tas256x_interrupt_clear(struct tas256x_priv *p_tas256x, int ch) +{ + int n_result = 0; + + p_tas256x->update_bits(p_tas256x, ch, TAS256X_INTERRUPTCONFIGURATION, + TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR_MASK, + TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR); + + return n_result; +} + +int tas256x_interrupt_enable(struct tas256x_priv *p_tas256x, int val, int ch) +{ + int n_result = 0; + + if (val) { + /*Enable Interrupts*/ + n_result = p_tas256x->write(p_tas256x, ch, + TAS256X_INTERRUPTMASKREG0, 0xf8); + n_result = p_tas256x->write(p_tas256x, ch, + TAS256X_INTERRUPTMASKREG1, 0xb1); + } else { + /*Disable Interrupts*/ + n_result = p_tas256x->write(p_tas256x, ch, + TAS256X_INTERRUPTMASKREG0, + TAS256X_INTERRUPTMASKREG0_DISABLE); + n_result = p_tas256x->write(p_tas256x, ch, + TAS256X_INTERRUPTMASKREG1, + TAS256X_INTERRUPTMASKREG1_DISABLE); + } + + return n_result; +} + +int tas256x_interrupt_read(struct tas256x_priv *p_tas256x, int *intr1, + int *intr2, int ch) +{ + int n_result = 0; + + n_result = p_tas256x->read(p_tas256x, ch, TAS256X_LATCHEDINTERRUPTREG0, + intr1); + n_result = p_tas256x->read(p_tas256x, ch, TAS256X_LATCHEDINTERRUPTREG1, + intr2); + + return n_result; +} + +int tas256x_icn_enable(struct tas256x_priv *p_tas256x, int enable, int ch) +{ + int n_result = 0; + + if (enable) { /*Enable*/ + p_tas256x->update_bits(p_tas256x, ch, TAS256X_ICN_SW_REG, + TAS256X_ICN_SW_MASK, + TAS256X_ICN_SW_ENABLE); + pr_info("%s %s: ICN Enable!\n", LOG_TAG, __func__); + } else { /*Disable*/ + p_tas256x->update_bits(p_tas256x, ch, TAS256X_ICN_SW_REG, + TAS256X_ICN_SW_MASK, + TAS256X_ICN_SW_DISABLE); + pr_info("%s %s: ICN Disable!\n", LOG_TAG, __func__); + } + + return n_result; +} + +/* icn_hysteresis & p_icn_thresholds*/ +int tas256x_icn_data(struct tas256x_priv *p_tas256x, int ch) +{ + int n_result = 0; + + pr_info("%s set ICN to -80dB\n", LOG_TAG); + n_result = + p_tas256x->bulk_write(p_tas256x, ch, TAS256X_ICN_THRESHOLD_REG, + p_icn_threshold, sizeof(p_icn_threshold)); + n_result = + p_tas256x->bulk_write(p_tas256x, ch, TAS256X_ICN_HYSTERESIS_REG, + p_icn_hysteresis, + sizeof(p_icn_hysteresis)); + + return n_result; +} + +int tas256x_icn_config(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + + n_result = + p_tas256x->write(p_tas256x, ch, TAS256X_REG(0, 253, 13), 0x0d); + if (n_result < 0) + return n_result; + + n_result = + p_tas256x->write(p_tas256x, ch, TAS256X_REG(0, 253, 25), 0x80); + + return n_result; +} + +int tas256x_boost_volt_update(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + + if (value == DEVICE_TAS2558) { + /* Max voltage to 9V */ + /*TODO: Need to be fixed*/ + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS2562_BOOSTCONFIGURATION2, + TAS2562_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_MASK, 0x7); + if (n_result < 0) + return n_result; + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS2562_PLAYBACKCONFIGURATIONREG0, + TAS2562_PLAYBACKCONFIGURATIONREG0_AMPLIFIERLEVEL51_MASK, + 0xd << 1); + } else if (value == DEVICE_TAS2562) { + /*TODO: ??*/ + } else if (value == DEVICE_TAS2564) { + /*Update Channel Gain to 16dBV*/ + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_PLAYBACKCONFIGURATIONREG0, + TAS2564_PLAYBACKCONFIGURATION_AMP_LEVEL_MASK, + TAS2564_AMP_LEVEL_16dBV); + } + return n_result; +} + +int tas256x_set_misc_config(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + + n_result = p_tas256x->write(p_tas256x, ch, + TAS256X_MISCCONFIGURATIONREG0, 0xcf); + + return n_result; +} + +int tas256x_set_tx_config(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + +#ifdef CONFIG_PLATFORM_EXYNOS + if (p_tas256x->mn_channels == 2) { + n_result = p_tas256x->write(p_tas256x, channel_left, + TAS256X_TDMConfigurationReg4, 0xf3); + if (n_result < 0) + return n_result; + n_result = p_tas256x->write(p_tas256x, channel_right, + TAS256X_TDMConfigurationReg4, 0x13); + if (n_result < 0) + return n_result; + } else { + n_result = p_tas256x->write(p_tas256x, channel_both, + TAS256X_TDMConfigurationReg4, 0x03); + if (n_result < 0) + return n_result; + } +#else + if (p_tas256x->mn_channels == 2) { + n_result = p_tas256x->write(p_tas256x, channel_left, + TAS256X_TDMConfigurationReg4, 0xf1); + if (n_result < 0) + return n_result; + n_result = p_tas256x->write(p_tas256x, channel_right, + TAS256X_TDMConfigurationReg4, 0x11); + if (n_result < 0) + return n_result; + } else { + n_result = p_tas256x->write(p_tas256x, channel_both, + TAS256X_TDMConfigurationReg4, 0x01); + if (n_result < 0) + return n_result; + } +#endif + + return n_result; +} + +int tas256x_set_clock_config(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + + n_result = p_tas256x->write(p_tas256x, ch, TAS256X_CLOCKCONFIGURATION, + 0x0c); + + /* Increase the clock halt timer to 838ms to avoid + * TDM Clock errors during playback start/stop + */ + n_result |= p_tas256x->update_bits(p_tas256x, ch, + TAS256X_INTERRUPTCONFIGURATION, + TAS256X_CLOCK_HALT_TIMER_MASK, + TAS256X_CLOCK_HALT_838MS); + return n_result; +} + +int tas256x_set_classH_config(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + + n_result = + tas256x_i2c_load_data(p_tas256x, ch, p_tas256x_classh_d_data); + + return n_result; +} + +int tas256x_HPF_FF_Bypass(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_PLAYBACKCONFIGURATIONREG0, + TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_MASK, + TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_DISABLED); + + return n_result; +} + +int tas256x_HPF_FB_Bypass(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = 0; + + n_result = p_tas256x->bulk_write( + p_tas256x, ch, TAS256X_HPF, HPF_reverse_path, + sizeof(HPF_reverse_path) / sizeof(HPF_reverse_path[0])); + + return n_result; +} + +int tas56x_software_reset(struct tas256x_priv *p_tas256x, int ch) +{ + int n_result = 0; + + n_result = p_tas256x->write(p_tas256x, ch, TAS256X_SOFTWARERESET, + TAS256X_SOFTWARERESET_SOFTWARERESET_RESET); + + msleep(20); + + return n_result; +} + +int tas256x_interrupt_determine(struct tas256x_priv *p_tas256x, int ch, + int int1status, int int2status) +{ + int mn_err_code = 0; + + if (((int1status & 0x7) != 0) || ((int2status & 0x0f) != 0)) { + if (int1status & + TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_INTERRUPT) { + mn_err_code |= ERROR_CLOCK; + pr_err("%s TDM clock error!\n", LOG_TAG); + } else { + mn_err_code &= ~ERROR_CLOCK; + } + + if (int1status & + TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_INTERRUPT) { + mn_err_code |= ERROR_OVER_CURRENT; + pr_err("%s SPK over current!\n", LOG_TAG); + } else { + mn_err_code &= ~ERROR_OVER_CURRENT; + } + + if (int1status & + TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_INTERRUPT) { + mn_err_code |= ERROR_DIE_OVERTEMP; + pr_err("%s die over temperature!\n", LOG_TAG); + } else { + mn_err_code &= ~ERROR_DIE_OVERTEMP; + } + + if (int2status & + TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_INTERRUPT) { + mn_err_code |= ERROR_OVER_VOLTAGE; + pr_err("%s SPK over voltage!\n", LOG_TAG); + } else { + mn_err_code &= ~ERROR_OVER_VOLTAGE; + } + + if (int2status & + TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_INTERRUPT) { + mn_err_code |= ERROR_UNDER_VOLTAGE; + pr_err("%s SPK under voltage!\n", LOG_TAG); + } else { + mn_err_code &= ~ERROR_UNDER_VOLTAGE; + } + + if (int2status & + TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_INTERRUPT) { + mn_err_code |= ERROR_BROWNOUT; + pr_err("%s brownout!\n", LOG_TAG); + } else { + mn_err_code &= ~ERROR_BROWNOUT; + } + } else { + return 0; + } + + return mn_err_code; +} + +int tas56x_get_chipid(struct tas256x_priv *p_tas256x, int *chipid, int ch) +{ + int n_result = 0; + + n_result = p_tas256x->read(p_tas256x, ch, TAS256X_CHIPID, chipid); + + return n_result; +} + +int tas2564_rx_mode_update(struct tas256x_priv *p_tas256x, int rx_mode, int ch) +{ + int n_result = 0; + + if (rx_mode) { + /* Default code */ + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS2564_PLAYBACKCONFIGURATIONREG0, + TAS2564_PLAYBACKCONFIGURATIONREG_RX_SPKR_MODE_MASK, + TAS2564_PLAYBACKCONFIGURATIONREG_RX_MODE); + + /*Unlock test page*/ + n_result = p_tas256x->write(p_tas256x, ch, + TAS256X_TEST_PAGE_LOCK, 0xd); + /*Keep DAC modulator dither to minimum*/ + n_result |= p_tas256x->write(p_tas256x, ch, + TAS256X_DAC_MODULATOR, 0xc0); + /* ICN improvement*/ + n_result |= p_tas256x->write(p_tas256x, ch, TAS256X_ICN_IMPROVE, + 0x1f); + /* LSFB strength bias current 9uA -> 3uA*/ + n_result |= p_tas256x->write( + p_tas256x, ch, TAS256X_CLASSDCONFIGURATION2, 0x08); + /*Enable IRQ pull-up, disable SSM*/ + n_result |= p_tas256x->write( + p_tas256x, ch, TAS256X_MISCCONFIGURATIONREG0, 0xca); + /*Mask reaction of idle channel detect on IV sense*/ + n_result |= p_tas256x->write(p_tas256x, ch, TAS256X_ICN_SW_REG, + 0x00); + } else { + /* Default code */ + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS2564_PLAYBACKCONFIGURATIONREG0, + TAS2564_PLAYBACKCONFIGURATIONREG_RX_SPKR_MODE_MASK, + TAS2564_PLAYBACKCONFIGURATIONREG_SPKR_MODE); + + /*Unlock test page*/ + n_result = p_tas256x->write(p_tas256x, ch, + TAS256X_TEST_PAGE_LOCK, 0xd); + /*Keep DAC modulator dither to minimum*/ + n_result |= p_tas256x->write(p_tas256x, ch, + TAS256X_DAC_MODULATOR, 0x00); + /* ICN improvement*/ + n_result |= p_tas256x->write(p_tas256x, ch, TAS256X_ICN_IMPROVE, + 0x1f); + /* Default value = 0x28; LSFB strength = 9uA max.*/ + n_result |= p_tas256x->write( + p_tas256x, ch, TAS256X_CLASSDCONFIGURATION2, 0x28); + /*Enable IRQ pull-up, disable SSM*/ + n_result |= p_tas256x->write( + p_tas256x, ch, TAS256X_MISCCONFIGURATIONREG0, 0xc6); + /*Mask reaction of idle channel detect on IV sense*/ + n_result |= p_tas256x->write(p_tas256x, ch, TAS256X_ICN_SW_REG, + 0x10); + } + if (n_result == 0) + p_tas256x->devs[ch - 1]->rx_mode = rx_mode; + + return n_result; +} + +int tas256x_update_playback_volume(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 57)) { + n_result = p_tas256x->bulk_write(p_tas256x, ch, TAS256X_DVC_PCM, + (char *)&(dvc_pcm[value][0]), + sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->dvc_pcm = value; + } + + return n_result; +} + +int tas256x_update_lim_max_attenuation(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 16)) { + n_result = p_tas256x->bulk_write( + p_tas256x, ch, TAS256X_LIM_MAX_ATN, + (char *)&(lim_max_attn[value][0]), sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_max_attn = value; + } + + return n_result; +} + +int tas256x_update_lim_max_thr(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 27)) { + n_result = p_tas256x->bulk_write( + p_tas256x, ch, TAS256X_LIMB_TH_MAX, + (char *)&(vbat_lim_max_thd[value][0]), sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_thr_max = value; + } + + return n_result; +} + +int tas256x_update_lim_min_thr(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 27)) { + n_result = p_tas256x->bulk_write( + p_tas256x, ch, TAS256X_LIMB_TH_MIN, + (char *)&(vbat_lim_min_thd[value][0]), sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_thr_min = value; + } + + return n_result; +} + +int tas256x_update_lim_inflection_point(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 41)) { + n_result = p_tas256x->bulk_write( + p_tas256x, ch, TAS256X_LIMB_INF_PT, + (char *)&(vbat_lim_infl_pt[value][0]), sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_infl_pt = value; + } + + return n_result; +} + +int tas256x_update_lim_slope(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 7)) { + n_result = p_tas256x->bulk_write( + p_tas256x, ch, TAS256X_LIMB_SLOPE, + (char *)&(vbat_lim_track_slope[value][0]), sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_trk_slp = value; + } + + return n_result; +} + +int tas256x_update_bop_thr(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 16)) { + n_result = p_tas256x->bulk_write(p_tas256x, ch, TAS256X_BOP_TH, + (char *)&(bop_thd[value][0]), + sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->bop_thd = value; + } + return n_result; +} + +int tas256x_update_bosd_thr(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 16)) { + n_result = p_tas256x->bulk_write(p_tas256x, ch, TAS256X_BOSD_TH, + (char *)&(bsd_thd[value][0]), + sizeof(int)); + if (n_result == 0) + p_tas256x->devs[ch - 1]->bosd_thd = value; + } + + return n_result; +} + +int tas256x_update_boost_voltage(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if (p_tas256x->devs[ch - 1]->device_id == DEVICE_TAS2562) { + if ((value >= 0) && (value < 16)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS2562_BOOSTCONFIGURATION2, + TAS2562_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_MASK, + (value + + 1) << TAS2562_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_SHIFT); + } else if (p_tas256x->devs[ch - 1]->device_id == DEVICE_TAS2564) { + if ((value >= 0) && (value < 32)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS2564_BOOSTCONFIGURATION2, + TAS2564_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_MASK, + (value + + 7) << TAS2562_BOOSTCONFIGURATION2_BOOSTMAXVOLTAGE_SHIFT); + } + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bst_vltg = value; + + return n_result; +} + +int tas256x_update_current_limit(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 64)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_BOOSTCONFIGURATION4, + TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_MASK, + (value) << TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bst_ilm = value; + + return n_result; +} + +int tas256x_update_limiter_enable(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 2)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_LIMITERCONFIGURATION0, + TAS256X_LIMITER_ENABLE_MASK, + (value) << TAS256X_LIMITER_ENABLE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_switch = value; + + return n_result; +} + +int tas256x_update_limiter_attack_rate(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 8)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_LIMITERCONFIGURATION0, + TAS256X_LIMITER_ATTACKRATE_MASK, + (value) << TAS256X_LIMITER_ATTACKRATE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_att_rate = value; + + return n_result; +} + +int tas256x_update_limiter_attack_step_size(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 4)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_LIMITERCONFIGURATION0, + TAS256X_LIMITER_ATTACKSTEPSIZE_MASK, + (value) << TAS256X_LIMITER_ATTACKSTEPSIZE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_att_stp_size = value; + + return n_result; +} + +int tas256x_update_limiter_release_rate(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 8)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_LIMITERCONFIGURATION1, + TAS256X_LIMITER_RELEASERATE_MASK, + (value) << TAS256X_LIMITER_RELEASERATE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_rel_rate = value; + + return n_result; +} + +int tas256x_update_limiter_release_step_size(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 4)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_LIMITERCONFIGURATION1, + TAS256X_LIMITER_RELEASESTEPSIZE_MASK, + (value) << TAS256X_LIMITER_RELEASESTEPSIZE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->lim_rel_stp_size = value; + + return n_result; +} + +int tas256x_update_bop_enable(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 2)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_BOPCONFIGURATION0, + TAS256X_BOP_ENABLE_MASK, + (value) << TAS256X_BOP_ENABLE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bop_enable = value; + + return n_result; +} + +int tas256x_update_bop_mute(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 2)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_BOPCONFIGURATION0, + TAS256X_BOP_MUTE_MASK, + (value) << TAS256X_BOP_MUTE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bop_mute = value; + + return n_result; +} + +int tas256x_update_bop_shutdown_enable(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 2)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_BOPCONFIGURATION0, + TAS256X_BOP_SHUTDOWN_ENABLE_MASK, + (value) << TAS256X_BOP_SHUTDOWN_ENABLE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bosd_enable = value; + + return n_result; +} + +int tas256x_update_bop_attack_rate(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 8)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_BOPCONFIGURATION1, + TAS256X_BOP_ATTACKRATE_MASK, + (value) << TAS256X_BOP_ATTACKRATE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bop_att_rate = value; + + return n_result; +} + +int tas256x_update_bop_attack_step_size(struct tas256x_priv *p_tas256x, + int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 4)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_BOPCONFIGURATION1, + TAS256X_BOP_ATTACKSTEPSIZE_MASK, + (value) << TAS256X_BOP_ATTACKSTEPSIZE_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bop_att_stp_size = value; + + return n_result; +} + +int tas256x_update_bop_hold_time(struct tas256x_priv *p_tas256x, int value, + int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 8)) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_BOPCONFIGURATION1, + TAS256X_BOP_HOLDTIME_MASK, + (value) << TAS256X_BOP_HOLDTIME_SHIFT); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->bop_hld_time = value; + + return n_result; +} + +int tas256x_update_vbat_lpf(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = -1; + + if ((value >= 0) && (value < 4)) { + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_VBATFILTER, + TAS256X_VBAT_LPF_MASK, + (value) << TAS256X_VBAT_LPF_SHIFT); + if (n_result == 0) + p_tas256x->devs[ch - 1]->vbat_lpf = value; + } + + return n_result; +} + +int tas256x_update_rx_cfg(struct tas256x_priv *p_tas256x, int value, int ch) +{ + int n_result = -1; + int data = -1; + + switch (value) { + case 0: + data = TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_I2C; + break; + case 1: + data = TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_LEFT; + break; + case 2: + data = TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_RIGHT; + break; + case 3: + data = TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_STEREO_DOWNMIX; + break; + } + + if (data >= 0) + n_result = p_tas256x->update_bits( + p_tas256x, ch, TAS256X_TDMCONFIGURATIONREG2, + TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MASK, data); + + if (n_result == 0) + p_tas256x->devs[ch - 1]->rx_cfg = value; + + return n_result; +} diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x.h b/techpack/audio/asoc/codecs/tas256x/tas256x.h new file mode 100644 index 000000000000..960f0946931a --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas256x.h @@ -0,0 +1,647 @@ +#ifndef __TAS256X_ +#define __TAS256X_ + +#include +#include +#include +#include +#include +#include +#define CODEC_PM +#define TAS256X_DRIVER_TAG "202003201710" + +/* Page Control Register */ +#define TAS256X_PAGECTL_REG 0 +#define CONFIG_TAS256X_BIN_PARSER +/* Book Control Register (available in page0 of each book) */ +#define TAS256X_BOOKCTL_PAGE 0 +#define TAS256X_BOOKCTL_REG 127 + +#define TAS256X_REG(book, page, reg) (((book * 256 * 128) + (page * 128)) + reg) + +#define TAS256X_BOOK_ID(reg) (reg / (256 * 128)) + +#define TAS256X_PAGE_ID(reg) ((reg % (256 * 128)) / 128) + +#define TAS256X_BOOK_REG(reg) (reg % (256 * 128)) + +#define TAS256X_PAGE_REG(reg) ((reg % (256 * 128)) % 128) + +/* Software Reset */ +#define TAS256X_SOFTWARERESET TAS256X_REG(0x0, 0x0, 0x01) +#define TAS256X_SOFTWARERESET_SOFTWARERESET_MASK (0x1 << 0) +#define TAS256X_SOFTWARERESET_SOFTWARERESET_DONTRESET (0x0 << 0) +#define TAS256X_SOFTWARERESET_SOFTWARERESET_RESET (0x1 << 0) + +/* Power Control */ +#define TAS256X_POWERCONTROL TAS256X_REG(0x0, 0x0, 0x02) +#define TAS256X_POWERCONTROL_ISNSPOWER_MASK (0x1 << 3) +#define TAS256X_POWERCONTROL_ISNSPOWER_ACTIVE (0x0 << 3) +#define TAS256X_POWERCONTROL_ISNSPOWER_POWEREDDOWN (0x1 << 3) +#define TAS256X_POWERCONTROL_VSNSPOWER_MASK (0x1 << 2) +#define TAS256X_POWERCONTROL_VSNSPOWER_ACTIVE (0x0 << 2) +#define TAS256X_POWERCONTROL_VSNSPOWER_POWEREDDOWN (0x1 << 2) +#define TAS256X_POWERCONTROL_OPERATIONALMODE10_MASK (0x3 << 0) +#define TAS256X_POWERCONTROL_OPERATIONALMODE10_ACTIVE (0x0 << 0) +#define TAS256X_POWERCONTROL_OPERATIONALMODE10_MUTE (0x1 << 0) +#define TAS256X_POWERCONTROL_OPERATIONALMODE10_SHUTDOWN (0x2 << 0) + +/* Playback Configuration Reg0 */ +#define TAS256X_PLAYBACKCONFIGURATIONREG0 TAS256X_REG(0x0, 0x0, 0x03) +#define TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_MASK (0x1 << 6) +#define TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_ENABLED (0x0 << 6) +#define TAS256X_PLAYBACKCONFIGURATIONREG0_DCBLOCKER_DISABLED (0x1 << 6) + +/* Misc Configuration Reg0 */ +#define TAS256X_MISCCONFIGURATIONREG0 TAS256X_REG(0x0, 0x0, 0x04) +#define TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_MASK (0x1 << 7) +#define TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_DONOTRETRY (0x0 << 7) +#define TAS256X_MISCCONFIGURATIONREG0_CPPGRETRY_RETRY (0x1 << 7) +#define TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_MASK (0x1 << 6) +#define TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_DONOTRETRY (0x0 << 6) +#define TAS256X_MISCCONFIGURATIONREG0_VBATPRORETRY_RETRY (0x1 << 6) +#define TAS256X_MISCCONFIGURATIONREG0_OCERETRY_MASK (0x1 << 5) +#define TAS256X_MISCCONFIGURATIONREG0_OCERETRY_DONOTRETRY (0x0 << 5) +#define TAS256X_MISCCONFIGURATIONREG0_OCERETRY_RETRY (0x1 << 5) +#define TAS256X_MISCCONFIGURATIONREG0_OTERETRY_MASK (0x1 << 4) +#define TAS256X_MISCCONFIGURATIONREG0_OTERETRY_DONOTRETRY (0x0 << 4) +#define TAS256X_MISCCONFIGURATIONREG0_OTERETRY_RETRY (0x1 << 4) +#define TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_MASK (0x1 << 3) +#define TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_DISABLED (0x0 << 3) +#define TAS256X_MISCCONFIGURATIONREG0_IRQZPULL_ENABLED (0x1 << 3) +#define TAS256X_MISCCONFIGURATIONREG0_AMPSS_MASK (0x1 << 2) +#define TAS256X_MISCCONFIGURATIONREG0_AMPSS_DISABLED (0x0 << 2) +#define TAS256X_MISCCONFIGURATIONREG0_AMPSS_ENABLED (0x1 << 2) + +/* TDM Configuration Reg0 */ +#define TAS256X_TDMCONFIGURATIONREG0 TAS256X_REG(0x0, 0x0, 0x06) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_MASK (0x1 << 5) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_48KHZ (0x0 << 5) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATERAMP_44_1KHZ (0x1 << 5) +#define TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_MASK (0x1 << 4) +#define TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_DISABLED (0x1 << 4) +#define TAS256X_TDMCONFIGURATIONREG0_DETECTSAMPRATE_ENABLED (0x0 << 4) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_MASK (0x7 << 1) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_14_7_16KHZ (0x1 << 1) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_44_1_48KHZ (0x4 << 1) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_88_2_96KHZ (0x5 << 1) +#define TAS256X_TDMCONFIGURATIONREG0_SAMPRATE31_176_4_192KHZ (0x6 << 1) +#define TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_MASK (0x1 << 0) +#define TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_LOWTOHIGH (0x0 << 0) +#define TAS256X_TDMCONFIGURATIONREG0_FRAMESTART_HIGHTOLOW (0x1 << 0) + +/* TDM Configuration Reg1 */ +#define TAS256X_TDMCONFIGURATIONREG1 TAS256X_REG(0x0, 0x0, 0x07) +#define TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_MASK (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_LEFT (0x0 << 6) +#define TAS256X_TDMCONFIGURATIONREG1_RXJUSTIFY_RIGHT (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_MASK (0x1f << 1) +#define TAS256X_TDMCONFIGURATIONREG1_RXOFFSET51_SHIFT (1) +#define TAS256X_TDMCONFIGURATIONREG1_RXEDGE_MASK (0x1 << 0) +#define TAS256X_TDMCONFIGURATIONREG1_RXEDGE_RISING (0x0 << 0) +#define TAS256X_TDMCONFIGURATIONREG1_RXEDGE_FALLING (0x1 << 0) + +/* TDM Configuration Reg2 */ +#define TAS256X_TDMCONFIGURATIONREG2 TAS256X_REG(0x0, 0x0, 0x08) +#define TAS256X_TDMCONFIGURATIONREG2_IVLEN76_MASK (0X3 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_16BITS (0x0 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_12BITS (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_IVLENCFG76_8BITS (0x2 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_MASK (0x3 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_8BITS (0x2 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_12BITS (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_IVMONLEN76_16BITS (0x0 << 6) +#define TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MASK (0x3 << 4) +#define TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_I2C (0x0 << 4) +#define TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_LEFT (0x1 << 4) +#define TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_MONO_RIGHT (0x2 << 4) +#define TAS256X_TDMCONFIGURATIONREG2_RXSCFG54_STEREO_DOWNMIX (0x3 << 4) +#define TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_MASK (0x3 << 2) +#define TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_16BITS (0x0 << 2) +#define TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_20BITS (0x1 << 2) +#define TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_24BITS (0x2 << 2) +#define TAS256X_TDMCONFIGURATIONREG2_RXWLEN32_32BITS (0x3 << 2) +#define TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_MASK (0x3 << 0) +#define TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_16BITS (0x0 << 0) +#define TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_24BITS (0x1 << 0) +#define TAS256X_TDMCONFIGURATIONREG2_RXSLEN10_32BITS (0x2 << 0) + +/* TDM Configuration Reg4 */ +#define TAS256X_TDMConfigurationReg4 TAS256X_REG(0x0, 0x0, 0x0A) +#define TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_MASK (0x1 << 5) +#define TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_DISABLE (0x0 << 5) +#define TAS256X_TDMCONFIGURATIONREG4_TXKEEPER_ENABLE (0x1 << 5) +#define TAS256X_TDMCONFIGURATIONREG4_TXFILL_MASK (0x1 << 4) +#define TAS256X_TDMCONFIGURATIONREG4_TXFILL_TRANSMIT0 (0x0 << 4) +#define TAS256X_TDMCONFIGURATIONREG4_TXFILL_TRANSMITHIZ (0x1 << 4) +#define TAS256X_TDMCONFIGURATIONREG4_TXOFFSET31_MASK (0x7 << 1) +#define TAS256X_TDMCONFIGURATIONREG4_TXEDGE_MASK (0x1 << 0) +#define TAS256X_TDMCONFIGURATIONREG4_TXEDGE_RISING (0x0 << 0) +#define TAS256X_TDMCONFIGURATIONREG4_TXEDGE_FALLING (0x1 << 0) + +/* TDM Configuration Reg5 */ +#define TAS256X_TDMCONFIGURATIONREG5 TAS256X_REG(0x0, 0x0, 0x0B) +#define TAS256X_TDMCONFIGURATIONREG5_VSNSTX_MASK (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG5_VSNSTX_DISABLE (0x0 << 6) +#define TAS256X_TDMCONFIGURATIONREG5_VSNSTX_ENABLE (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG5_VSNSSLOT50_MASK (0x3f << 0) + +/* TDM Configuration Reg6 */ +#define TAS256X_TDMCONFIGURATIONREG6 TAS256X_REG(0x0, 0x0, 0x0C) +#define TAS256X_TDMCONFIGURATIONREG6_ISNSTX_MASK (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG6_ISNSTX_DISABLE (0x0 << 6) +#define TAS256X_TDMCONFIGURATIONREG6_ISNSTX_ENABLE (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG6_ISNSSLOT50_MASK (0x3f << 0) + +/* TDM Configuration Reg7 */ +#define TAS256X_TDMCONFIGURATIONREG7 TAS256X_REG(0x0, 0x0, 0x0D) +#define TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_MASK (0x1 << 7) +#define TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_8BITS (0x0 << 7) +#define TAS256X_TDMCONFIGURATIONREG7_VBATSLEN_16BITS (0x1 << 7) +#define TAS256X_TDMCONFIGURATIONREG7_VBATTX_MASK (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG7_VBATTX_DISABLE (0x0 << 6) +#define TAS256X_TDMCONFIGURATIONREG7_VBATTX_ENABLE (0x1 << 6) +#define TAS256X_TDMCONFIGURATIONREG7_VBATSLOT50_MASK (0x3f << 0) + +/* Interrupt Mask Reg0 */ +#define TAS256X_INTERRUPTMASKREG0 TAS256X_REG(0x0, 0x0, 0x1A) +#define TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_MASK (0x1 << 7) +#define TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_UNMASK (0x0 << 7) +#define TAS256X_INTERRUPTMASKREG0_LIMMUTEINTMASK_DISABLE (0x1 << 7) +#define TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_MASK (0x1 << 6) +#define TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_UNMASK (0x0 << 6) +#define TAS256X_INTERRUPTMASKREG0_LIMINFHLDINTMASK_DISABLE (0x1 << 6) +#define TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_MASK (0x1 << 5) +#define TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_UNMASK (0x0 << 5) +#define TAS256X_INTERRUPTMASKREG0_LIMMAXATNINTMASK_DISABLE (0x1 << 5) +#define TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_MASK (0x1 << 4) +#define TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_UNMASK (0x0 << 4) +#define TAS256X_INTERRUPTMASKREG0_VBATLESSTHANINFINTMASK_DISABLE (0x1 << 4) +#define TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_MASK (0x1 << 3) +#define TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_UNMASK (0x0 << 3) +#define TAS256X_INTERRUPTMASKREG0_LIMACTIVEFLAGINTMASK_DISABLE (0x1 << 3) +#define TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_MASK (0x1 << 2) +#define TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_UNMASK (0x0 << 2) +#define TAS256X_INTERRUPTMASKREG0_TDMCLOCKERRORINTMASK_DISABLE (0x1 << 2) +#define TAS256X_INTERRUPTMASKREG0_OCEINTMASK_MASK (0x1 << 1) +#define TAS256X_INTERRUPTMASKREG0_OCEINTMASK_UNMASK (0x0 << 1) +#define TAS256X_INTERRUPTMASKREG0_OCEINTMASK_DISABLE (0x1 << 1) +#define TAS256X_INTERRUPTMASKREG0_OTEINTMASK_MASK (0x1 << 0) +#define TAS256X_INTERRUPTMASKREG0_OTEINTMASK_UNMASK (0x0 << 0) +#define TAS256X_INTERRUPTMASKREG0_OTEINTMASK_DISABLE (0x1 << 0) +#define TAS256X_INTERRUPTMASKREG0_DISABLE 0xff + +/* Interrupt Mask Reg1 */ +#define TAS256X_INTERRUPTMASKREG1 TAS256X_REG(0x0, 0x0, 0x1B) +#define TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_MASK (0x1 << 7) +#define TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_UNMASK (0x0 << 7) +#define TAS256X_INTERRUPTMASKREG1_DSPOUTPUTINTMASK_DISABLE (0x1 << 7) +#define TAS256X_INTERRUPTMASKREG1_CRCINTMASK_MASK (0x1 << 6) +#define TAS256X_INTERRUPTMASKREG1_CRCINTMASK_UNMASK (0x0 << 6) +#define TAS256X_INTERRUPTMASKREG1_CRCINTMASK_DISABLE (0x1 << 6) +#define TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_MASK (0x1 << 2) +#define TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_UNMASK (0x0 << 2) +#define TAS256X_INTERRUPTMASKREG1_VBATOVLOINTMASK_DISABLE (0x1 << 2) +#define TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_MASK (0x1 << 1) +#define TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_UNMASK (0x0 << 1) +#define TAS256X_INTERRUPTMASKREG1_VBATUVLOINTMASK_DISABLE (0x1 << 1) +#define TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_MASK (0x1 << 0) +#define TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_UNMASK (0x0 << 0) +#define TAS256X_INTERRUPTMASKREG1_BROWNOUTFLAGINTMASK_DISABLE (0x1 << 0) +#define TAS256X_INTERRUPTMASKREG1_DISABLE 0xff + +/* Latched-Interrupt Reg0 */ +#define TAS256X_LATCHEDINTERRUPTREG0 TAS256X_REG(0x0, 0x0, 0x24) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_MASK (0x1 << 7) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_NOINTERRUPT (0x0 << 7) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMMUTESTICKY_INTERRUPT (0x1 << 7) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_MASK (0x1 << 6) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_NOINTERRUPT (0x0 << 6) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMINFHLDSTICKY_INTERRUPT (0x1 << 6) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_MASK (0x1 << 5) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_NOINTERRUPT (0x0 << 5) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMMAXATNSTICKY_INTERRUPT (0x1 << 5) +#define TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_MASK (0x1 << 4) +#define TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_NOINTERRUPT \ + (0x0 << 4) +#define TAS256X_LATCHEDINTERRUPTREG0_VBATLESSTHANINFSTICKY_INTERRUPT (0x1 << 4) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_MASK (0x1 << 3) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_NOINTERRUPT (0x0 << 3) +#define TAS256X_LATCHEDINTERRUPTREG0_LIMACTIVEFLAGSTICKY_INTERRUPT (0x1 << 3) +#define TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_MASK (0x1 << 2) +#define TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_NOINTERRUPT (0x0 << 2) +#define TAS256X_LATCHEDINTERRUPTREG0_TDMCLOCKERRORSTICKY_INTERRUPT (0x1 << 2) +#define TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_MASK (0x1 << 1) +#define TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_NOINTERRUPT (0x0 << 1) +#define TAS256X_LATCHEDINTERRUPTREG0_OCEFLAGSTICKY_INTERRUPT (0x1 << 1) +#define TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_MASK (0x1 << 0) +#define TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_NOINTERRUPT (0x0 << 0) +#define TAS256X_LATCHEDINTERRUPTREG0_OTEFLAGSTICKY_INTERRUPT (0x1 << 0) + +/* Latched-Interrupt Reg1 */ +#define TAS256X_LATCHEDINTERRUPTREG1 TAS256X_REG(0x0, 0x0, 0x25) +#define TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_MASK (0x1 << 7) +#define TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_NOINTERRUPT \ + (0x0 << 7) +#define TAS256X_LATCHEDINTERRUPTREG1_PDMAUDDATAINVALIDSTICKY_INTERRUPT \ + (0x1 << 7) +#define TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_MASK (0x1 << 3) +#define TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_NOINTERRUPT (0x0 << 3) +#define TAS256X_LATCHEDINTERRUPTREG1_VBATOVLOSTICKY_INTERRUPT (0x1 << 3) +#define TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_MASK (0x1 << 2) +#define TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_NOINTERRUPT (0x0 << 2) +#define TAS256X_LATCHEDINTERRUPTREG1_VBATUVLOSTICKY_INTERRUPT (0x1 << 2) +#define TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_MASK (0x1 << 1) +#define TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_NOINTERRUPT (0x0 << 1) +#define TAS256X_LATCHEDINTERRUPTREG1_BROWNOUTFLAGSTICKY_INTERRUPT (0x1 << 1) +#define TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_MASK (0x1 << 0) +#define TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_NOINTERRUPT (0x0 << 0) +#define TAS256X_LATCHEDINTERRUPTREG1_PDMCLOCKERRORSTICKY_INTERRUPT (0x1 << 0) + +/* Interrupt Configuration */ +#define TAS256X_INTERRUPTCONFIGURATION TAS256X_REG(0x0, 0x0, 0x30) +#define TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR_MASK (0x1 << 2) +#define TAS256X_INTERRUPTCONFIGURATION_LTCHINTCLEAR (0x1 << 2) +#define TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_MASK (0x3 << 0) +#define TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLIVEINTERRUPTS \ + (0x0 << 0) +#define TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERTONLATCHEDINTERRUPTS \ + (0x1 << 0) +#define TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLIVEINTERRUPTS \ + (0x2 << 0) +#define TAS256X_INTERRUPTCONFIGURATION_PININTCONFIG10_ASSERT2MSONLATCHEDINTERRUPTS \ + (0x3 << 0) + +#define TAS256X_CLOCK_HALT_TIMER_MASK (0x7 << 3) +#define TAS256X_CLOCK_HALT_1MS (0x0 << 3) +#define TAS256X_CLOCK_HALT_3MS (0x1 << 3) +#define TAS256X_CLOCK_HALT_26MS (0x2 << 3) +#define TAS256X_CLOCK_HALT_52MS (0x3 << 3) +#define TAS256X_CLOCK_HALT_104MS (0x4 << 3) +#define TAS256X_CLOCK_HALT_209MS (0x5 << 3) +#define TAS256X_CLOCK_HALT_419MS (0x6 << 3) +#define TAS256X_CLOCK_HALT_838MS (0x7 << 3) +#define TAS256X_BOOSTSLOPE TAS256X_REG(0x0, 0x0, 0x35) +#define TAS256X_BOOSTSLOPE_MASK (0x3 << 2) + +/* Clock Configuration */ +#define TAS256X_CLOCKCONFIGURATION TAS256X_REG(0x0, 0x0, 0x38) +#define TAS256X_CLOCKCONFIGURATION_SBCLKTOFS52_MASK (0xf << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_16 (0x0 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_24 (0x1 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_32 (0x2 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_48 (0x3 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_64 (0x4 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_96 (0x5 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_128 (0x6 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_192 (0x7 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_256 (0x8 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_384 (0x9 << 2) +#define TAS256X_CLOCKCONFIGURATION_SBCLKtoFS52_512 (0xa << 2) +#define TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_MASK (0x3 << 0) +#define TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_DISABLED (0x1 << 0) +#define TAS256X_CLOCKCONFIGURATION_DISCLKRATEDETECT10_ENABLED (0x0 << 0) + +#define TAS256X_VBATFILTER TAS256X_REG(0x0, 0x0, 0x3b) +#define TAS256X_VBAT_LPF_MASK (0x3 << 5) +#define TAS256X_VBAT_LPF_SHIFT 5 + +#define TAS256X_CLASSHRELEASETIMER TAS256X_REG(0x0, 0x0, 0x3c) + +#define TAS256X_BOOST_CFG4 TAS256X_REG(0x0, 0x0, 0x40) + +#define TAS256X_CHIPID TAS256X_REG(0x0, 0x0, 0x7D) + +#define TAS256X_ICN_THRESHOLD_REG TAS256X_REG(0x0, 0x2, 0x64) +#define TAS256X_ICN_HYSTERESIS_REG TAS256X_REG(0x0, 0x2, 0x6c) + +#define TAS256X_ICN_SW_REG TAS256X_REG(0x0, 0x0, 0x3e) +#define TAS256X_ICN_SW_MASK (0x01 << 4) +#define TAS256X_ICN_SW_ENABLE (0x10) +#define TAS256X_ICN_SW_DISABLE (0x00) +#define TAS256X_TESTPAGECONFIGURATION TAS256X_REG(0x0, 0xfd, 0xd) +#define TAS256X_CLASSDCONFIGURATION1 TAS256X_REG(0x0, 0xfd, 0x19) +#define TAS256X_CLASSDCONFIGURATION2 TAS256X_REG(0x0, 0xfd, 0x32) +#define TAS256X_CLASSDCONFIGURATION3 TAS256X_REG(0x0, 0xfd, 0x33) +#define TAS256X_CLASSDCONFIGURATION4 TAS256X_REG(0x0, 0xfd, 0x3f) +#define TAS256X_EFFICIENCYCONFIGURATION TAS256X_REG(0x0, 0xfd, 0x5f) + +#define TAS256X_HPF TAS256X_REG(0x0, 0x2, 0x70) +#define TAS256X_CLASSHHEADROOM TAS256X_REG(0x64, 0x7, 0x48) +#define TAS256X_CLASSHHYSTERESIS TAS256X_REG(0x64, 0x7, 0x4c) +#define TAS256X_CLASSHMTCT TAS256X_REG(0x64, 0x5, 0x4c) + +/*PCM Digital Volume Control*/ +#define TAS256X_DVC_PCM TAS256X_REG(0x0, 0x2, 0x0c) + +/*Limiter Controls*/ +#define TAS256X_LIM_MAX_ATN TAS256X_REG(0x0, 0x2, 0x14) +#define TAS256X_LIMB_TH_MAX TAS256X_REG(0x0, 0x2, 0x18) +#define TAS256X_LIMB_TH_MIN TAS256X_REG(0x0, 0x2, 0x1c) +#define TAS256X_LIMB_INF_PT TAS256X_REG(0x0, 0x2, 0x20) +#define TAS256X_LIMB_SLOPE TAS256X_REG(0x0, 0x2, 0x24) + +/*Brown Out Protection Control*/ +#define TAS256X_BOP_TH TAS256X_REG(0x0, 0x2, 0x28) +#define TAS256X_BOSD_TH TAS256X_REG(0x0, 0x2, 0x2c) + +#define TAS256X_BOOSTCONFIGURATION4 TAS256X_REG(0x0, 0x0, 0x40) +#define TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_MASK (0x3f << 0) +#define TAS256X_BOOSTCONFIGURATION4_BOOSTCURRENTLIMIT_SHIFT 0 + +#define TAS256X_LIMITERCONFIGURATION0 TAS256X_REG(0x0, 0x0, 0x12) +#define TAS256X_LIMITER_ENABLE_MASK (0x1 << 0) +#define TAS256X_LIMITER_ENABLE_SHIFT 0x0 +#define TAS256X_LIMITER_ATTACKRATE_MASK (0x7 << 1) +#define TAS256X_LIMITER_ATTACKRATE_SHIFT 0x1 +#define TAS256X_LIMITER_ATTACKSTEPSIZE_MASK (0x3 << 4) +#define TAS256X_LIMITER_ATTACKSTEPSIZE_SHIFT 0x4 + +#define TAS256X_LIMITERCONFIGURATION1 TAS256X_REG(0x0, 0x0, 0x13) +#define TAS256X_LIMITER_RELEASERATE_MASK (0x7 << 3) +#define TAS256X_LIMITER_RELEASERATE_SHIFT 0x3 +#define TAS256X_LIMITER_RELEASESTEPSIZE_MASK (0x3 << 6) +#define TAS256X_LIMITER_RELEASESTEPSIZE_SHIFT 0x6 + +#define TAS256X_BOPCONFIGURATION0 TAS256X_REG(0x0, 0x0, 0x14) +#define TAS256X_BOP_ENABLE_MASK (0x1 << 0) +#define TAS256X_BOP_ENABLE_SHIFT 0x0 +#define TAS256X_BOP_MUTE_MASK (0x1 << 1) +#define TAS256X_BOP_MUTE_SHIFT 0x1 +#define TAS256X_BOP_SHUTDOWN_ENABLE_MASK (0x1 << 4) +#define TAS256X_BOP_SHUTDOWN_ENABLE_SHIFT 0x4 + +#define TAS256X_BOPCONFIGURATION1 TAS256X_REG(0x0, 0x0, 0x15) +#define TAS256X_BOP_ATTACKRATE_MASK (0x7 << 5) +#define TAS256X_BOP_ATTACKRATE_SHIFT 0x5 +#define TAS256X_BOP_ATTACKSTEPSIZE_MASK (0x3 << 0x3) +#define TAS256X_BOP_ATTACKSTEPSIZE_SHIFT 0x3 +#define TAS256X_BOP_HOLDTIME_MASK (0x7 << 0x0) +#define TAS256X_BOP_HOLDTIME_SHIFT 0x0 + +/*Test Page*/ +#define TAS256X_TEST_PAGE_LOCK TAS256X_REG(0x00, 0xfd, 0x0d) +#define TAS256X_DAC_MODULATOR TAS256X_REG(0x00, 0xfd, 0x12) +#define TAS256X_DAC_MUTE TAS256X_REG(0x00, 0xfd, 0x47) +#define TAS256X_ICN_MODE TAS256X_REG(0x00, 0xfd, 0x64) +#define TAS256X_ICN_IMPROVE TAS256X_REG(0x00, 0xfd, 0x46) + +#define TAS256X_MISC_CLASSD TAS256X_REG(0x0, 0x01, 0x21) +#define TAS256X_CMP_HYST_MASK (0x1 << 3) +#define TAS256X_CMP_HYST_SHIFT (0x3) + +/* Book */ +#define TAS256X_BOOK TAS256X_REG(0x0, 0x0, 0x7F) +#define TAS256X_BOOK_BOOK70_MASK (0xff << 0) + +/* data format */ +#define TAS256X_DATAFORMAT_SHIFT 2 +#define TAS256X_DATAFORMAT_I2S 0x0 +#define TAS256X_DATAFORMAT_DSP 0x1 +#define TAS256X_DATAFORMAT_RIGHT_J 0x2 +#define TAS256X_DATAFORMAT_LEFT_J 0x3 + +#define TAS256X_DAI_FMT_MASK (0x7 << TAS256X_DATAFORMAT_SHIFT) + +#define TAS256X_POWER_ACTIVE 0 +#define TAS256X_POWER_MUTE 1 +#define TAS256X_POWER_SHUTDOWN 2 + +#define ERROR_NONE 0x0000000 +#define ERROR_PLL_ABSENT 0x0000001 +#define ERROR_DEVA_I2C_COMM 0x0000002 +#define ERROR_DEVB_I2C_COMM 0x0000004 +#define ERROR_CLOCK 0x0000008 +#define ERROR_YRAM_CRCCHK 0x0000010 +#define ERROR_OVER_CURRENT 0x0000020 +#define ERROR_DIE_OVERTEMP 0x0000040 +#define ERROR_OVER_VOLTAGE 0x0000080 +#define ERROR_UNDER_VOLTAGE 0x0000100 +#define ERROR_BROWNOUT 0x0000200 +#define ERROR_CLASSD_PWR 0x0000400 +#define ERROR_FAILSAFE 0x0000800 + +#define CHECK_PERIOD 5000 /* 5 second */ + +#define TAS256X_I2C_RETRY_COUNT 3 +#define ERROR_I2C_SUSPEND -1 +#define ERROR_I2C_FAILED -2 + +#define TAS256X_LEFT_SWITCH 0x10000001 +#define TAS256X_RIGHT_SWITCH 0x10000002 +#define RX_SCFG_LEFT 0x10000003 +#define RX_SCFG_RIGHT 0x10000004 + +#define RESTART_MAX 3 + +struct tas256x_priv; + +#ifdef CONFIG_TAS256X_BIN_PARSER +#define TAS256X_CONFIG_SIZE (10) +#define TAS256X_DEVICE_SUM (8) + +#define TAS256X_CMD_SING_W (0x1) +#define TAS256X_CMD_BURST (0x2) +#define TAS256X_CMD_DELAY (0x3) +#define TAS256X_CMD_FIELD_W (0x4) + +#define SMS_HTONS(a, b) ((((a) & 0x00FF) << 8) | ((b) & 0x00FF)) +#define SMS_HTONL(a, b, c, d) \ + ((((a) & 0x000000FF) << 24) | (((b) & 0x000000FF) << 16) | \ + (((c) & 0x000000FF) << 8) | ((d) & 0x000000FF)) + +enum tas256x_dsp_fw_state { + TAS256X_DSP_FW_NONE = 0, + TAS256X_DSP_FW_PENDING, + TAS256X_DSP_FW_FAIL, + TAS256X_DSP_FW_OK, +}; + +enum tas256x_bin_blk_type { + TAS256X_BIN_BLK_COEFF = 1, + TAS256X_BIN_BLK_POST_POWER_UP, + TAS256X_BIN_BLK_PRE_SHUTDOWN, + TAS256X_BIN_BLK_PRE_POWER_UP, + TAS256X_BIN_BLK_POST_SHUTDOWN +}; + +struct tas256x_fw_hdr { + unsigned int img_sz; + unsigned int checksum; + unsigned int binnary_version_num; + unsigned int drv_fw_version; + unsigned int timestamp; + unsigned char plat_type; + unsigned char dev_family; + unsigned char reserve; + unsigned char ndev; + unsigned char devs[TAS256X_DEVICE_SUM]; + unsigned int nconfig; + unsigned int config_size[TAS256X_CONFIG_SIZE]; +}; + +struct tas256x_block_data { + unsigned char dev_idx; + unsigned char block_type; + unsigned short yram_checksum; + unsigned int block_size; + unsigned int nSublocks; + unsigned char *regdata; +}; + +struct tas256x_config_info { + unsigned int nblocks; + unsigned int real_nblocks; + struct tas256x_block_data **blk_data; +}; + +void tas256x_select_cfg_blk(void *pContext, int conf_no, + unsigned char block_type); +#endif //CONFIG_TAS256X_BIN_PARSER + +struct tas256x_register { + int book; + int page; + int reg; +}; + +struct tas256x_dai_cfg { + unsigned int dai_fmt; + unsigned int tdm_delay; +}; + +/*struct tas256x_buf_cfg { + unsigned short bufSize; + unsigned char *buf; +};*/ + +enum channel { + channel_left = 0x01, + channel_right = 0x02, + channel_both = channel_left | channel_right +}; + +/* + * device ops function structure + */ +struct tas_device_ops { + int (*tas_init)( + struct tas256x_priv *p_tas256x, + int chn); /**< init typically for loading optimal settings */ + int (*tas_probe)(struct tas256x_priv *p_tas256x, + struct snd_soc_codec *codec, int chn); + //TODO: +}; + +struct tas_device { + int mChipID; + int mn_current_book; + int mn_current_page; + int mn_addr; + int mn_reset_gpio; + int mn_irq_gpio; + int mn_irq; + int spk_control; + int device_id; + int rx_mode; + int dvc_pcm; + int bst_vltg; + int bst_ilm; + int lim_switch; + int lim_max_attn; + int lim_thr_max; + int lim_thr_min; + int lim_att_rate; + int lim_rel_rate; + int lim_att_stp_size; + int lim_rel_stp_size; + int lim_max_thd; + int lim_min_thd; + int lim_infl_pt; + int lim_trk_slp; + int bop_enable; + int bop_thd; + int bop_att_rate; + int bop_att_stp_size; + int bop_hld_time; + int bop_mute; + int bosd_enable; + int bosd_thd; + int vbat_lpf; + int rx_cfg; + struct i2c_client *i2c; + struct regmap *regmap; + struct tas_device_ops dev_ops; +}; + +struct tas256x_priv { + struct device *dev; + struct i2c_client *client; + struct regmap *regmap; + struct mutex dev_lock; + struct delayed_work irq_work; + struct delayed_work init_work; + struct delayed_work dc_work; + struct hrtimer mtimer; + bool mb_power_up; + int mn_power_state; + int mn_asi_format; + bool mb_irq_eable; + int mn_sampling_rate; + int mn_frame_size; + int mn_ppg; + int mn_ch_size; + int mn_slot_width; + int mn_pcm_format; + int mn_iv_width; + int mn_vbat; + bool mb_mute; + bool dac_mute; + bool i2c_suspend; + int mn_channels; + struct tas_device **devs; + int icn_sw; + int (*read)(struct tas256x_priv *p_tas256x, enum channel chn, + unsigned int reg, unsigned int *pValue); + int (*write)(struct tas256x_priv *p_tas256x, enum channel chn, + unsigned int reg, unsigned int Value); + int (*bulk_read)(struct tas256x_priv *p_tas256x, enum channel chn, + unsigned int reg, unsigned char *p_data, + unsigned int len); + int (*bulk_write)(struct tas256x_priv *p_tas256x, enum channel chn, + unsigned int reg, unsigned char *p_data, + unsigned int len); + int (*update_bits)(struct tas256x_priv *p_tas256x, enum channel chn, + unsigned int reg, unsigned int mask, + unsigned int value); + void (*hw_reset)(struct tas256x_priv *p_tas256x); + void (*clear_irq)(struct tas256x_priv *p_tas256x); + void (*enable_irq)(struct tas256x_priv *p_tas256x, bool enable); + /* device is working, but system is suspended */ + int (*runtime_suspend)(struct tas256x_priv *p_tas256x); + int (*runtime_resume)(struct tas256x_priv *p_tas256x); + bool mb_runtime_suspend; + + unsigned int mn_err_code; + unsigned int mnRestart; +#ifdef CONFIG_TAS256X_CODEC + struct mutex codec_lock; +#endif + +#ifdef CONFIG_TAS256X_MISC + int mn_dbg_cmd; + int mn_current_reg; + //struct tas256x_buf_cfg misc_buf; + struct mutex file_lock; +#endif + + int iv_enable; +#ifdef CONFIG_TAS256X_BIN_PARSER + int fw_state; + struct tas256x_fw_hdr fw_hdr; + int ncfgs; + struct tas256x_config_info **cfg_info; +#endif +}; + +#endif /* __TAS256X_ */ diff --git a/techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c b/techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c new file mode 100644 index 000000000000..4da82e22090d --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c @@ -0,0 +1,995 @@ +#include +#include +#include +#include +#include +#include "tas25xx-calib.h" + +#define USE_VFS 1 +#define CODEC_CONTROL 1 +#define POISON_VAL 0xDEADDEAD +#define MAX_STRING (300) + +/*Master Control to Bypass the Smartamp TI CAPIv2 module*/ +static int s_tas_smartamp_bypass; +static int s_tas_smartamp_enable; +static int s_debug_enable; +static int s_calib_test_flag; +static int s_profile_id; +static struct mutex routing_lock; +static int32_t g_fmt; + +bool tas25xx_set_iv_bit_fomat(int iv_data_with, int vbat, int update_now) +{ + int32_t param_id; + int32_t ret; + bool success; + + if ((vbat == 1) && (iv_data_with == 12)) + g_fmt = IV_SENSE_FORMAT_12_BIT_WITH_8BIT_VBAT; + else if ((vbat == 1) && (iv_data_with == 8)) + g_fmt = IV_SENSE_FORMAT_8_BIT_WITH_8BIT_VBAT; + else + g_fmt = IV_SENSE_FORMAT_NO_VBAT; + + success = true; + + if (update_now) { + param_id = TAS_CALC_PARAM_IDX(TAS_SA_IV_VBAT_FMT, 1, CHANNEL0); + pr_info("TI-SmartPA: %s: Sending IV,Vbat format %d\n", __func__, + g_fmt); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&g_fmt, param_id, + TAS_SET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + pr_err("TI-SmartPA: %s: Failed to set config\n", + __func__); + success = false; + } + } + + return success; +} + +#ifdef CONFIG_SET_RE_IN_KERNEL +static int get_calibrated_re_tcalib(uint32_t *rdc_fix, uint32_t *tv_fix, + int channel_count) +{ + struct file *file = NULL; + char calib_data[MAX_STRING] = { 0 }; + char filepath[128] = SMARTAMP_SPEAKER_CALIBDATA_FILE; + mm_segment_t fs; + int ret = 0; + static uint32_t s_rdc_fix[2] = { POISON_VAL, POISON_VAL }; + static uint32_t s_tv_fix = POISON_VAL; + +#if USE_VFS + loff_t pos = 0; +#else + int size; + int fd; +#endif + + if ((s_rdc_fix[0] == POISON_VAL) && (s_rdc_fix[1] == POISON_VAL)) { + fs = get_fs(); + set_fs(get_ds()); +#if USE_VFS + file = filp_open(filepath, O_RDONLY, 0); + if (!IS_ERR(file)) { + vfs_read(file, calib_data, MAX_STRING - 1, &pos); + + if (channel_count == 1) { + if (sscanf(calib_data, "%d;%d;", s_rdc_fix, + &s_tv_fix) != 2) { + pr_err("TI-SmartPA: %s: file %s read error\n", + __func__, filepath); + ret = -EIO; + } + } else if (channel_count == 2) { + if (sscanf(calib_data, "%d;%d;%d;", + &s_rdc_fix[0], &s_rdc_fix[1], + &s_tv_fix) != 3) { + pr_err("TI-SmartPA: %s: file %s read error\n", + __func__, filepath); + ret = -EIO; + } + } + filp_close(file, NULL); + + } else { + pr_err("TI-SmartPA: %s: file %s open failed %p \n ", + __func__, filepath, file); + ret = -EIO; + } +#else + fd = sys_open(filepath, O_RDONLY, 0); + if (fd > 0) { + memset(calib_data, 0, sizeof(calib_data)); + size = sys_read(fd, calib_data, MAX_STRING - 1); + sys_close(fd); + + pr_info("TI-SmartPA: %s: *** sys_read size = %d\n", + __func__, size); + + if (channel_count == 1) { + if (sscanf(calib_data, "%d;%d;", &rdc_fix[0], + tv_fix) != 2) { + pr_err("TI-SmartPA: %s: file %s read error\n", + __func__, filepath); + ret = -EIO; + } + } else if (channel_count == 2) { + if (sscanf(calib_data, "%d;%d;%d;", &rdc_fix[0], + &rdc_fix[1], tv_fix) != 3) { + pr_err("TI-SmartPA: %s: file %s read error\n", + __func__, filepath); + ret = -EIO; + } + } + } else { + pr_err("TI-SmartPA: %s: file %s open failed %p \n ", + __func__, filepath, file); + ret = -EIO; + } +#endif + set_fs(fs); + } + + if (ret == 0) { + if (rdc_fix) { + rdc_fix[0] = (uint32_t)s_rdc_fix[0]; + if (channel_count == 2) + rdc_fix[1] = (uint32_t)s_rdc_fix[1]; + } + if (tv_fix) + *tv_fix = (uint32_t)s_tv_fix; + } + return ret; +} +#endif //CONFIG_SET_RE_IN_KERNEL + +static int tas25xx_smartamp_get_set(u8 *user_data, uint32_t param_id, + uint8_t get_set, uint32_t length, + uint32_t module_id) +{ + int ret = 0; + + switch (get_set) { + case TAS_SET_PARAM: + if (s_tas_smartamp_bypass) { + pr_err("TI-SmartPA: %s: SmartAmp is bypassed no control set\n", + __func__); + goto fail_cmd; + } + ret = afe_tas_smartamp_set_calib_data(module_id, param_id, + length, user_data); + break; + + case TAS_GET_PARAM: + if (!s_tas_smartamp_bypass) { + memset(user_data, 0, length); + ret = afe_tas_smartamp_get_calib_data( + module_id, param_id, length, user_data); + } + break; + + default: + goto fail_cmd; + } + +fail_cmd: + return ret; +} + +/*Wrapper arround set/get parameter, + *all set/get commands pass through this wrapper + */ +int tas25xx_smartamp_algo_ctrl(u8 *user_data, uint32_t param_id, + uint8_t get_set, uint32_t length, + uint32_t module_id) +{ + int ret = 0; + + mutex_lock(&routing_lock); + ret = tas25xx_smartamp_get_set(user_data, param_id, get_set, length, + module_id); + mutex_unlock(&routing_lock); + return ret; +} +EXPORT_SYMBOL(tas25xx_smartamp_algo_ctrl); + +/*Control-1: Set Profile*/ +static const char *profile_index_text[] = { "NONE", TAS_ALGO_PROFILE_LIST, + "CALIB" }; +static const struct soc_enum profile_index_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(profile_index_text), profile_index_text), +}; + +static int tas25xx_set_profile(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret; + int profile_id = pUcontrol->value.integer.value[0]; + int param_id = 0; + int max_number_of_profiles = + sizeof(profile_index_text) / sizeof(profile_index_text[0]); + + if ((profile_id >= max_number_of_profiles) || (profile_id < 0)) + return -EINVAL; + + s_profile_id = profile_id; + + pr_info("TI-SmartPA: %s: Setting profile %s \n", __func__, + profile_index_text[profile_id]); + if (profile_id) + profile_id -= 1; + else + return 0; + + param_id = TAS_CALC_PARAM_IDX(TAS_SA_SET_PROFILE, 1, CHANNEL0); + pr_info("TI-SmartPA: %s: Sending set profile\n", __func__); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&profile_id, param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) + pr_err("TI-SmartPA: %s: Failed to set config\n", __func__); + return ret; +} + +static int tas25xx_get_profile(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret; + int profile_id = 0; + int param_id = 0; + int max_number_of_profiles = + sizeof(profile_index_text) / sizeof(profile_index_text[0]); + + if (s_tas_smartamp_enable && s_debug_enable) { + param_id = TAS_CALC_PARAM_IDX(TAS_SA_SET_PROFILE, 1, CHANNEL0); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&profile_id, param_id, + TAS_GET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + pr_err("TI-SmartPA: %s: Failed to get profile\n", + __func__); + profile_id = 0; + } else { + profile_id += 1; + } + } else { + profile_id = s_profile_id; + } + + pUcontrol->value.integer.value[0] = profile_id; + + if ((profile_id < max_number_of_profiles) && (profile_id > -1)) + pr_info("TI-SmartPA: %s: getting profile %s\n", __func__, + profile_index_text[profile_id]); + + return 0; +} + +/*Control-2: Set Calibrated Rdc*/ +static int tas25xx_set_Re_common(int re_value_in, int channel) +{ + int ret; + int param_id = 0; + int re_value = re_value_in; + + param_id = TAS_CALC_PARAM_IDX(TAS_SA_SET_RE, 1, channel); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&re_value, param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + + return ret; +} + +static int tas25xx_set_Re_left(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int re_value = pUcontrol->value.integer.value[0]; + + pr_info("TI-SmartPA: %s: Setting Re %d", __func__, re_value); + return tas25xx_set_Re_common(re_value, CHANNEL0); +} + +static int tas25xx_dummy_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + + pUcontrol->value.integer.value[0] = 0; + return ret; +} + +static int tas25xx_dummy_set(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + return 0; +} + +/*Control-3: Calibration and Test(F0,Q,Tv) Controls*/ +static const char *tas25xx_calib_test_text[] = { "NONE", "CALIB_START", + "CALIB_STOP", "TEST_START", + "TEST_STOP" }; + +static const struct soc_enum tas25xx_calib_test_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas25xx_calib_test_text), + tas25xx_calib_test_text), +}; + +static int tas25xx_calib_test_set_common(int calib_command, int channel) +{ + int ret = 0; + int param_id = 0; + int data = 1; + + switch (calib_command) { + case CALIB_START: + pr_info("TI-SmartPA: %s: CALIB_START", __func__); + s_calib_test_flag = 1; + param_id = TAS_CALC_PARAM_IDX(TAS_SA_CALIB_INIT, 1, channel); + break; + + case CALIB_STOP: + pr_info("TI-SmartPA: %s: CALIB_STOP", __func__); + s_calib_test_flag = 0; + param_id = TAS_CALC_PARAM_IDX(TAS_SA_CALIB_DEINIT, 1, channel); + break; + + case TEST_START: + s_calib_test_flag = 1; + break; + + case TEST_STOP: + s_calib_test_flag = 0; + break; + + default: + pr_info("TI-SmartPA: %s: no impl calib_command %d\n", __func__, + calib_command); + ret = -EINVAL; + break; + } + + if (param_id) { + ret = tas25xx_smartamp_algo_ctrl((u8 *)&data, param_id, + TAS_SET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + s_calib_test_flag = 0; + pr_err("TI-SmartPA: %s: Failed to set calib/test, ret=%d\n", + __func__, ret); + } + } + + return ret; +} + +static int tas25xx_calib_test_set(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + int user_data = pUcontrol->value.integer.value[0]; + + ret = tas25xx_calib_test_set_common(user_data, CHANNEL0); + + if (ret == 0) { +#ifdef CONFIG_TAS25XX_ALGO_STEREO + ret = tas25xx_calib_test_set_common(user_data, CHANNEL1); +#endif + } + + return ret; +} + +/*Control-4: Get Re*/ +//returns -ve error or +ve re value, 0 if not called +static int tas25xx_get_re_common(int channel) +{ + int ret = 0; + int re_value = 0; + int param_id = 0; + + pr_info("TI-SmartPA: %s, channel=%d\n", __func__, channel); + + if (s_tas_smartamp_enable && (s_calib_test_flag || s_debug_enable)) { + param_id = TAS_CALC_PARAM_IDX(TAS_SA_GET_RE, 1, channel); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&re_value, param_id, + TAS_GET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) + pr_err("TI-SmartPA: %s: Failed to get Re\n", __func__); + else + ret = re_value; + } + + return ret; +} + +static int tas25xx_get_re_left(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = tas25xx_get_re_common(CHANNEL0); + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + ret = 0; + pr_info("TI-SmartPA: %s: Getting Re %d\n", __func__, ret); + } + + return ret; +} + +/*Control-5: Get F0*/ +static int tas25xx_get_f0_common(int channel) +{ + int f0_value = 0; + int param_id = 0; + int ret = 0; + + pr_info("TI-SmartPA: %s, channel=%d\n", __func__, channel); + + if (s_tas_smartamp_enable && (s_calib_test_flag || s_debug_enable)) { + param_id = TAS_CALC_PARAM_IDX(TAS_SA_GET_F0, 1, channel); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&f0_value, param_id, + TAS_GET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) + pr_err("TI-SmartPA: %s: Failed to get F0\n", __func__); + else + ret = f0_value; + } + + return ret; +} + +static int tas25xx_get_f0_left(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = tas25xx_get_f0_common(CHANNEL0); + + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + pr_info("TI-SmartPA: %s: Getting F0 val=%d\n", __func__, ret); + ret = 0; + } + + return ret; +} + +/*Control-6: Get Q*/ +static int tas25xx_get_q_common(int channel) +{ + int ret = 0; + int q_value = 0; + int param_id = 0; + + pr_info("TI-SmartPA: %s, channel=%d", __func__, channel); + + if (s_tas_smartamp_enable && (s_calib_test_flag || s_debug_enable)) { + param_id = TAS_CALC_PARAM_IDX(TAS_SA_GET_Q, 1, channel); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&q_value, param_id, + TAS_GET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) + pr_err("TI-SmartPA: %s: Failed to get F0\n", __func__); + else + ret = q_value; + } + + return ret; +} + +static int tas25xx_get_q_left(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = tas25xx_get_q_common(CHANNEL0); + + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + pr_info("TI-SmartPA: %s: Getting Q %d\n", __func__, ret); + ret = 0; + } + + return ret; +} + +/*Control-7: Get Tv*/ +static int tas25xx_get_tv_common(int channel) +{ + int ret = 0; + int tv_value = 0; + int param_id = 0; + + pr_info("TI-SmartPA: %s, channel=%d", __func__, channel); + + if (s_tas_smartamp_enable && (s_calib_test_flag || s_debug_enable)) { + param_id = TAS_CALC_PARAM_IDX(TAS_SA_GET_TV, 1, channel); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&tv_value, param_id, + TAS_GET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) + pr_err("TI-SmartPA: %s: Failed to get Tv\n", __func__); + else + ret = tv_value; + } + + return ret; +} + +static int tas25xx_get_tv_left(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = tas25xx_get_tv_common(CHANNEL0); + + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + pr_info("TI-SmartPA: %s: Getting Tv %d\n", __func__, ret); + ret = 0; + } + + return ret; +} + +/*Control-8: Smartamp Enable*/ +static const char *tas25xx_smartamp_enable_text[] = { "DISABLE", "ENABLE" }; + +static const struct soc_enum tas25xx_smartamp_enable_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas25xx_smartamp_enable_text), + tas25xx_smartamp_enable_text), +}; + +static int tas25xx_smartamp_enable_set(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + int param_id = 0; + int user_data = pUcontrol->value.integer.value[0]; +#ifdef CONFIG_SET_RE_IN_KERNEL + uint32_t calibration_data[3]; +#endif + +#ifdef CONFIG_TAS25XX_ALGO_STEREO + int number_of_ch = 2; +#else + int number_of_ch = 1; +#endif + + if (s_tas_smartamp_bypass) { + pr_info("TI-SmartPA: bypass enabled, not enabling\n"); + return 0; + } + + pr_info("TI-SmartPA: %s: case %d, number_of_ch=%d\n", __func__, + user_data, number_of_ch); + + s_tas_smartamp_enable = user_data; + if (s_tas_smartamp_enable == 0) { + s_profile_id = 0; + s_calib_test_flag = 0; + pr_info("TI-SmartPA: %s: Disable called\n", __func__); + return 0; + } + + pr_info("TI-SmartPA: %s: Setting the feedback module info for TAS\n", + __func__); + ret = afe_spk_prot_feed_back_cfg(TAS_TX_PORT, TAS_RX_PORT, 1, 0, 1); + if (ret) + pr_err("TI-SmartPA: %s: FB Path Info failed ignoring ret = 0x%x\n", + __func__, ret); + + pr_info("TI-SmartPA: %s: Sending TX Enable\n", __func__); + param_id = CAPI_V2_TAS_TX_ENABLE; + ret = tas25xx_smartamp_algo_ctrl((u8 *)&user_data, param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_TX); + if (ret) { + pr_err("TI-SmartPA: %s: TX Enable Failed ret = 0x%x\n", + __func__, ret); + goto fail_cmd; + } + + user_data = 0xB1B1B1B1; + pr_info("TI-SmartPA: %s: Sending TX Config\n", __func__); + param_id = CAPI_V2_TAS_TX_CFG; + ret = tas25xx_smartamp_algo_ctrl((u8 *)&user_data, param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_TX); + if (ret < 0) { + pr_err("TI-SmartPA: %s: Failed to set config\n", __func__); + goto fail_cmd; + } + + user_data = 1; + pr_info("TI-SmartPA: %s: Sending RX Enable\n", __func__); + param_id = CAPI_V2_TAS_RX_ENABLE; + ret = tas25xx_smartamp_algo_ctrl((u8 *)&user_data, param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret) { + pr_err("TI-SmartPA: %s: RX Enable Failed ret = 0x%x\n", + __func__, ret); + goto fail_cmd; + } + + user_data = 0xB1B1B1B1; + pr_info("TI-SmartPA: %s: Sending RX Config\n", __func__); + param_id = CAPI_V2_TAS_RX_CFG; + ret = tas25xx_smartamp_algo_ctrl((u8 *)&user_data, param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + pr_err("TI-SmartPA: %s: Failed to set config\n", __func__); + goto fail_cmd; + } + + param_id = TAS_CALC_PARAM_IDX(TAS_SA_IV_VBAT_FMT, 1, CHANNEL0); + pr_info("TI-SmartPA: %s: Sending IV,Vbat format %d\n", __func__, g_fmt); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&g_fmt, param_id, TAS_SET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + pr_err("TI-SmartPA: %s: Failed to set config\n", __func__); + goto fail_cmd; + } + + s_tas_smartamp_enable = true; + +#ifdef CONFIG_SET_RE_IN_KERNEL + if (number_of_ch == 2) + ret = get_calibrated_re_tcalib( + calibration_data, &calibration_data[2], number_of_ch); + else + ret = get_calibrated_re_tcalib( + calibration_data, &calibration_data[1], number_of_ch); + + if (ret) { + pr_err("[Smartamp:%s] unable to get the calibration data = 0x%x\n", + __func__, ret); + //TODO: Ignore the calibration read error + ret = 0; + } else { + int32_t t_cal; + if (number_of_ch == 2) { + t_cal = calibration_data[2]; + pr_info("[Smartamp:%s] setting re %d,%d and tcal %d\n", + __func__, calibration_data[0], + calibration_data[1], calibration_data[2]); + } else { + t_cal = calibration_data[1]; + pr_info("[Smartamp:%s] setting re %d and tcal %d\n", + __func__, calibration_data[0], + calibration_data[1]); + } + + param_id = TAS_CALC_PARAM_IDX(TAS_SA_SET_TCAL, 1, CHANNEL0); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&t_cal, param_id, + TAS_SET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + pr_err("[Smartamp:%s] Failed to set Tcal\n", __func__); + goto fail_cmd; + } + + param_id = TAS_CALC_PARAM_IDX(TAS_SA_SET_RE, 1, CHANNEL0); + ret = tas25xx_smartamp_algo_ctrl((u8 *)(&(calibration_data[0])), + param_id, TAS_SET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + pr_err("TI-SmartPA: %s: Failed to set Re\n", __func__); + goto fail_cmd; + } + + if (number_of_ch == 2) { + param_id = + TAS_CALC_PARAM_IDX(TAS_SA_SET_RE, 1, CHANNEL1); + ret = tas25xx_smartamp_algo_ctrl( + (u8 *)&(calibration_data[1]), param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) { + pr_err("TI-SmartPA: %s: Failed to set Re\n", + __func__); + goto fail_cmd; + } + } + } +#endif //CONFIG_SET_RE_IN_KERNEL + +fail_cmd: + return ret; +} + +static int tas25xx_smartamp_enable_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + int user_data = s_tas_smartamp_enable; + + pUcontrol->value.integer.value[0] = user_data; + pr_info("TI-SmartPA: %s: case %d(0=DISABLE, 1=ENABLE)\n", __func__, + user_data); + return ret; +} + +/*Control-9: Smartamp Bypass */ +static const char *tas25xx_smartamp_bypass_text[] = { "FALSE", "TRUE" }; + +static const struct soc_enum tas25xx_smartamp_bypass_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas25xx_smartamp_bypass_text), + tas25xx_smartamp_bypass_text), +}; + +static int tas25xx_smartamp_bypass_set(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + int user_data = pUcontrol->value.integer.value[0]; + + if (s_tas_smartamp_enable) { + pr_debug( + "TI-SmartPA: %s: cannot update while smartamp enabled\n", + __func__); + return -EINVAL; + } + + s_tas_smartamp_bypass = user_data; + pr_info("TI-SmartPA: %s: case %d(FALSE=0,TRUE=1)\n", __func__, + user_data); + return ret; +} + +static int tas25xx_smartamp_bypass_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + + pUcontrol->value.integer.value[0] = s_tas_smartamp_bypass; + pr_info("TI-SmartPA: %s: case %d\n", __func__, s_tas_smartamp_bypass); + return ret; +} + +/*Control-9: Smartamp Bypass */ +static const char *tas25xx_smartamp_debug_enable_text[] = { "FALSE", "TRUE" }; + +static const struct soc_enum tas25xx_smartamp_debug_enable_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tas25xx_smartamp_debug_enable_text), + tas25xx_smartamp_debug_enable_text), +}; + +static int +tas25xx_smartamp_debug_enable_set(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + int user_data = pUcontrol->value.integer.value[0]; + + s_debug_enable = user_data; + pr_info("TI-SmartPA: %s: case %d(FALSE=0,TRUE=1)\n", __func__, + user_data); + return ret; +} + +static int +tas25xx_smartamp_debug_enable_get(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + + pUcontrol->value.integer.value[0] = s_debug_enable; + pr_info("TI-SmartPA: %s: case %d\n", __func__, s_debug_enable); + return ret; +} + +static int tas25xx_set_spk_id(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + int speaker_id = pUcontrol->value.integer.value[0]; + int param_id = 0; + + pr_info("TI-SmartPA: %s: spk-id set %d\n", __func__, speaker_id); + param_id = TAS_CALC_PARAM_IDX(TAS_SA_SET_SPKID, 1, CHANNEL0); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&speaker_id, param_id, + TAS_SET_PARAM, sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) + pr_err("TI-SmartPA: %s: Failed to set spk id\n", __func__); + + return ret; +} + +static int tas25xx_set_t_calib(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = 0; + int calib_temp = pUcontrol->value.integer.value[0]; + int param_id = 0; + + pr_info("TI-SmartPA: %s: tcalib set %d\n", __func__, calib_temp); + if (s_tas_smartamp_enable) { + param_id = TAS_CALC_PARAM_IDX(TAS_SA_SET_TCAL, 1, CHANNEL0); + ret = tas25xx_smartamp_algo_ctrl((u8 *)&calib_temp, param_id, + TAS_SET_PARAM, + sizeof(uint32_t), + AFE_SMARTAMP_MODULE_RX); + if (ret < 0) + pr_err("TI-SmartPA: %s: Failed to set spk id\n", + __func__); + } + + return ret; +} + +#ifdef CONFIG_TAS25XX_ALGO_STEREO +static int tas25xx_set_Re_right(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int re_value = pUcontrol->value.integer.value[0]; + + pr_info("TI-SmartPA: %s: Setting Re %d\n", __func__, re_value); + return tas25xx_set_Re_common(re_value, CHANNEL1); +} + +static int tas25xx_get_re_right(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret; + + ret = tas25xx_get_re_common(CHANNEL1); + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + ret = 0; + pr_info("TI-SmartPA: %s: Getting Re value=%d\n", __func__, ret); + } + + return ret; +} + +static int tas25xx_get_f0_right(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = tas25xx_get_f0_common(CHANNEL1); + + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + pr_info("TI-SmartPA: %s: Getting F0 valu=%d\n", __func__, ret); + ret = 0; + } + + return ret; +} + +static int tas25xx_get_q_right(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = tas25xx_get_q_common(CHANNEL1); + + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + pr_info("TI-SmartPA: %s: Getting Q val=%d\n", __func__, ret); + ret = 0; + } + + return ret; +} + +static int tas25xx_get_tv_right(struct snd_kcontrol *pKcontrol, + struct snd_ctl_elem_value *pUcontrol) +{ + int ret = tas25xx_get_tv_common(CHANNEL1); + + if (ret >= 0) { + pUcontrol->value.integer.value[0] = ret; + pr_info("TI-SmartPA: %s: Getting Tv %d\n", __func__, ret); + ret = 0; + } + + return ret; +} +#endif + +static const struct snd_kcontrol_new smartamp_tas25xx_mixer_controls[] = { + SOC_ENUM_EXT("TAS25XX_DEBUG_ENABLE", + tas25xx_smartamp_debug_enable_enum[0], + tas25xx_smartamp_debug_enable_get, + tas25xx_smartamp_debug_enable_set), + SOC_ENUM_EXT("TAS25XX_ALGO_PROFILE", profile_index_enum[0], + tas25xx_get_profile, tas25xx_set_profile), + SOC_ENUM_EXT("TAS25XX_ALGO_CALIB_TEST", tas25xx_calib_test_enum[0], + tas25xx_dummy_get, tas25xx_calib_test_set), + SOC_SINGLE_EXT("TAS25XX_SET_SPK_ID", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_dummy_get, tas25xx_set_spk_id), + SOC_SINGLE_EXT("TAS25XX_SET_T_CALIB", SND_SOC_NOPM, 0, 100, 0, + tas25xx_dummy_get, tas25xx_set_t_calib), + + //left + SOC_SINGLE_EXT("TAS25XX_SET_RE_LEFT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_dummy_get, tas25xx_set_Re_left), + SOC_SINGLE_EXT("TAS25XX_GET_RE_LEFT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_re_left, tas25xx_dummy_set), + SOC_SINGLE_EXT("TAS25XX_GET_F0_LEFT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_f0_left, tas25xx_dummy_set), + SOC_SINGLE_EXT("TAS25XX_GET_Q_LEFT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_q_left, tas25xx_dummy_set), + SOC_SINGLE_EXT("TAS25XX_GET_TV_LEFT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_tv_left, tas25xx_dummy_set), + +//Right +#ifdef CONFIG_TAS25XX_ALGO_STEREO + SOC_SINGLE_EXT("TAS25XX_SET_RE_RIGHT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_dummy_get, tas25xx_set_Re_right), + SOC_SINGLE_EXT("TAS25XX_GET_RE_RIGHT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_re_right, tas25xx_dummy_set), + SOC_SINGLE_EXT("TAS25XX_GET_F0_RIGHT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_f0_right, tas25xx_dummy_set), + SOC_SINGLE_EXT("TAS25XX_GET_Q_RIGHT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_q_right, tas25xx_dummy_set), + SOC_SINGLE_EXT("TAS25XX_GET_TV_RIGHT", SND_SOC_NOPM, 0, 0x7fffffff, 0, + tas25xx_get_tv_right, tas25xx_dummy_set), +#endif + SOC_ENUM_EXT("TAS25XX_SMARTPA_ENABLE", tas25xx_smartamp_enable_enum[0], + tas25xx_smartamp_enable_get, tas25xx_smartamp_enable_set), + + SOC_ENUM_EXT("TAS25XX_ALGO_BYPASS", tas25xx_smartamp_bypass_enum[0], + tas25xx_smartamp_bypass_get, tas25xx_smartamp_bypass_set), +}; + +#if CODEC_CONTROL +void tas_smartamp_add_algo_controls(struct snd_soc_codec *codec) +{ + pr_err("TI-SmartPA: %s: Adding smartamp controls\n", __func__); + + /*Initialize all to global variables to 0s*/ + s_tas_smartamp_bypass = 0; + s_tas_smartamp_enable = 0; + s_debug_enable = 0; + s_calib_test_flag = 0; + s_profile_id = 0; + g_fmt = 0; + + mutex_init(&routing_lock); + snd_soc_add_codec_controls(codec, smartamp_tas25xx_mixer_controls, + ARRAY_SIZE(smartamp_tas25xx_mixer_controls)); + tas_calib_init(); +} +EXPORT_SYMBOL(tas_smartamp_add_algo_controls); +#else +void tas_smartamp_add_algo_controls_for_platform( + struct snd_soc_platform *platform) +{ + pr_err("TI-SmartPA: %s: Adding smartamp controls\n", __func__); + + /*Initialize all to global variables to 0s*/ + s_tas_smartamp_bypass = 0; + s_tas_smartamp_enable = 0; + s_debug_enable = 0; + s_calib_test_flag = 0; + s_profile_id = 0; + g_fmt = 0; + + mutex_init(&routing_lock); + snd_soc_add_platform_controls( + platform, smartamp_tas25xx_mixer_controls, + ARRAY_SIZE(smartamp_tas25xx_mixer_controls)); + tas_calib_init(); +} +EXPORT_SYMBOL(tas_smartamp_add_algo_controls_for_platform); +#endif + +void tas_smartamp_remove_algo_controls(struct snd_soc_codec *codec) +{ + (void)codec; + tas_calib_exit(); +} +EXPORT_SYMBOL(tas_smartamp_remove_algo_controls); diff --git a/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c b/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c new file mode 100644 index 000000000000..862025d74c0b --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c @@ -0,0 +1,202 @@ +/* +** ============================================================================= +** Copyright (c) 2017 Texas Instruments Inc. +** Copyright (C) 2021 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas25xx-calib.c +** +** Description: +** misc driver for interfacing for Texas Instruments TAS25xx algorithm +** +** ============================================================================= +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Holds the Packet data required for processing */ +struct tas_dsp_pkt { + u8 slave_id; + u8 book; + u8 page; + u8 offset; + u8 data[TAS_PAYLOAD_SIZE * 4]; +}; + +static int smartamp_params_ctrl(uint8_t *input, u8 dir, u8 count) +{ + u32 length = count / 4; + u32 paramid = 0; + u32 index; + int ret = 0; + int special_index = 0; + struct tas_dsp_pkt *ppacket; + + ppacket = (struct tas_dsp_pkt *)kmalloc(sizeof(struct tas_dsp_pkt), + GFP_KERNEL); + if (!ppacket) { + pr_err("TI-SmartPA: %s: kmalloc failed!", __func__); + return -ENOMEM; + } + + memset(ppacket, 0, sizeof(struct tas_dsp_pkt)); + ret = copy_from_user(ppacket, input, sizeof(struct tas_dsp_pkt)); + if (ret) { + pr_err("TI-SmartPA: %s: Error copying from user\n", __func__); + kfree(ppacket); + return -EFAULT; + } + + index = (ppacket->page - 1) * 30 + (ppacket->offset - 8) / 4; + special_index = TAS_SA_IS_SPL_IDX(index); + pr_info("TI-SmartPA: %s: index = %d", __func__, index); + if (special_index == 0) { + if ((index < 0 || index > MAX_DSP_PARAM_INDEX)) { + pr_err("TI-SmartPA: %s: invalid index !\n", __func__); + kfree(ppacket); + return -EINVAL; + } + } + pr_info("TI-SmartPA: %s: Valid Index. special = %s\n", __func__, + special_index ? "Yes" : "No"); + + /* speakers are differentiated by slave ids */ + if (ppacket->slave_id == SLAVE1) { + paramid = (paramid | (index) | (length << 16) | (1 << 24)); + pr_err("TI-SmartPA: %s: Rcvd Slave id for slave 1, %x\n", + __func__, ppacket->slave_id); + } else if (ppacket->slave_id == SLAVE2) { + paramid = (paramid | (index) | (length << 16) | (2 << 24)); + pr_err("TI-SmartPA: %s: Rcvd Slave id for slave 2, %x\n", + __func__, ppacket->slave_id); + } else { + pr_err("TI-SmartPA: %s: Wrong slaveid = %x\n", __func__, + ppacket->slave_id); + } + + /* + * Note: In any case calculated paramid should not match with + */ + if ((paramid == CAPI_V2_TAS_RX_ENABLE) || + (paramid == CAPI_V2_TAS_TX_ENABLE) || + (paramid == CAPI_V2_TAS_RX_CFG) || + (paramid == CAPI_V2_TAS_TX_CFG)) { + pr_err("TI-SmartPA: %s: %s Slave 0x%x params failed, paramid mismatch\n", + __func__, dir == TAS_GET_PARAM ? "get" : "set", + ppacket->slave_id); + kfree(ppacket); + return -EINVAL; + } + + ret = tas25xx_smartamp_algo_ctrl(ppacket->data, paramid, dir, + length * 4, AFE_SMARTAMP_MODULE_RX); + if (ret) + pr_err("TI-SmartPA: %s: %s Slave 0x%x params failed from afe, ret=%x\n", + __func__, dir == TAS_GET_PARAM ? "get" : "set", + ppacket->slave_id, ret); + else + pr_info("TI-SmartPA: %s: Algo control returned %d\n", __func__, + ret); + + if (dir == TAS_GET_PARAM) { + ret = copy_to_user(input, ppacket, sizeof(struct tas_dsp_pkt)); + if (ret) { + pr_err("TI-SmartPA: %s: Error copying to user after DSP", + __func__); + ret = -EFAULT; + } + } + + kfree(ppacket); + return ret; +} + +static int tas_calib_open(struct inode *inode, struct file *fd) +{ + return 0; +} + +static ssize_t tas_calib_write(struct file *file, const char __user *buffer, + size_t count, loff_t *offp) +{ + int rc = 0; + + rc = smartamp_params_ctrl((uint8_t *)buffer, TAS_SET_PARAM, count); + return rc; +} + +static ssize_t tas_calib_read(struct file *file, char __user *buffer, + size_t count, loff_t *ptr) +{ + int rc; + + rc = smartamp_params_ctrl((uint8_t *)buffer, TAS_GET_PARAM, count); + if (rc < 0) + count = rc; + return count; +} + +static long tas_calib_ioctl(struct file *filp, uint cmd, ulong arg) +{ + return 0; +} + +static int tas_calib_release(struct inode *inode, struct file *fd) +{ + return 0; +} + +const struct file_operations tas_calib_fops = { + .owner = THIS_MODULE, + .open = tas_calib_open, + .write = tas_calib_write, + .read = tas_calib_read, + .release = tas_calib_release, + .unlocked_ioctl = tas_calib_ioctl, +}; + +static struct miscdevice tas_calib_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = "tas_calib", + .fops = &tas_calib_fops, +}; + +int tas_calib_init(void) +{ + int rc; + + pr_err("TI-SmartPA: %s", __func__); + rc = misc_register(&tas_calib_misc); + if (rc) + pr_err("TI-SmartPA: %s: register calib misc failed\n", + __func__); + return rc; +} + +void tas_calib_exit(void) +{ + misc_deregister(&tas_calib_misc); +} + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("tas2560 Misc driver"); +MODULE_LICENSE("GPL v2"); diff --git a/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.h b/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.h new file mode 100644 index 000000000000..8f8d24519d98 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.h @@ -0,0 +1,29 @@ +/* +** ============================================================================= +** Copyright (c) 2016 Texas Instruments Inc. +** Copyright (C) 2021 XiaoMi, Inc. +** +** This program is free software; you can redistribute it and/or modify it under +** the terms of the GNU General Public License as published by the Free Software +** Foundation; version 2. +** +** This program is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +** FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +** +** File: +** tas25xx-calib.h +** +** Description: +** header file for tas25xx-calib.c +** +** ============================================================================= +*/ + +#ifndef _TAS25XX_CALIB_H_ +#define _TAS25XX_CALIB_H_ + +int tas_calib_init(void); +void tas_calib_exit(void); + +#endif /* _TAS25XX_CALIB_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/Android.mk b/techpack/audio/asoc/codecs/tfa98xx/Android.mk new file mode 100755 index 000000000000..f7bdf5f3a10f --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/Android.mk @@ -0,0 +1,55 @@ +# Android makefile for audio kernel modules + +# Assume no targets will be supported + +# Check if this driver needs be built for current target +ifeq ($(call is-board-platform,msmnile),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m +endif + +ifeq ($(call is-board-platform,$(MSMSTEPPE)),true) +AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m +endif + +AUDIO_CHIPSET := audio +# Build/Package only in case of supported target +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE)),true) + +LOCAL_PATH := $(call my-dir) + +# This makefile is only for DLKM +ifneq ($(findstring vendor,$(LOCAL_PATH)),) + +ifneq ($(findstring opensource,$(LOCAL_PATH)),) + #AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/vendor/qcom/opensource/audio-kernel + AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel +endif # opensource + +DLKM_DIR := $(TOP)/device/qcom/common/dlkm + +# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko +########################################################### +# This is set once per LOCAL_PATH, not per (kernel) module +KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR) + +# We are actually building audio.ko here, as per the +# requirement we are specifying _audio.ko as LOCAL_MODULE. +# This means we need to rename the module to _audio.ko +# after audio.ko is built. +KBUILD_OPTIONS += MODNAME=tfa98xx_dlkm +KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM) +KBUILD_OPTIONS += $(AUDIO_SELECT) + +########################################################### +include $(CLEAR_VARS) +LOCAL_MODULE := $(AUDIO_CHIPSET)_tfa98xx.ko +LOCAL_MODULE_KBUILD_NAME := tfa98xx_dlkm.ko +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +include $(DLKM_DIR)/AndroidKernelModule.mk +########################################################### +########################################################### + +endif # DLKM check +endif # supported target check diff --git a/techpack/audio/asoc/codecs/tfa98xx/Kbuild b/techpack/audio/asoc/codecs/tfa98xx/Kbuild new file mode 100755 index 000000000000..d0ffa5848306 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/Kbuild @@ -0,0 +1,120 @@ +# We can build either as part of a standalone Kernel build or as +# an external module. Determine which mechanism is being used +ifeq ($(MODNAME),) + KERNEL_BUILD := 1 +else + KERNEL_BUILD := 0 +endif + + + +ifeq ($(KERNEL_BUILD), 1) + # These are configurable via Kconfig for kernel-based builds + # Need to explicitly configure for Android-based builds + AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/kernel/msm-4.14 + AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio +endif + +ifeq ($(KERNEL_BUILD), 0) + ifeq ($(CONFIG_ARCH_SM8150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + ifeq ($(CONFIG_ARCH_SM6150), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif + + ifeq ($(CONFIG_ARCH_SDMSHRIKE), y) + include $(AUDIO_ROOT)/config/sm8150auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h + endif +endif + +# As per target team, build is done as follows: +# Defconfig : build with default flags +# Slub : defconfig + CONFIG_SLUB_DEBUG := y + +# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y +# Perf : Using appropriate msmXXXX-perf_defconfig +# +# Shipment builds (user variants) should not have any debug feature +# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds +# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since +# there is no other way to identify defconfig builds, QTI internal +# representation of perf builds (identified using the string 'perf'), +# is used to identify if the build is a slub or defconfig one. This +# way no critical debug feature will be enabled for perf and shipment +# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT +# config. + +############ UAPI ############ +UAPI_DIR := uapi +UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR) + +############ COMMON ############ +COMMON_DIR := include +COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR) +TFA_INC := -I$(AUDIO_ROOT)/asoc/codecs/tfa98xx/inc + +# for TFA9874 Amplifer +ifdef CONFIG_SND_SOC_TFA9874 + TFA98XX_OBJS += src/tfa98xx.o + TFA98XX_OBJS += src/tfa_container.o + TFA98XX_OBJS += src/tfa_dsp.o + TFA98XX_OBJS += src/tfa_init.o + #TFA98XX_OBJS += src/tfa_debug.o +endif + +LINUX_INC += -Iinclude/linux + +INCS += $(COMMON_INC) \ + $(UAPI_INC) \ + $(TFA_INC) + +EXTRA_CFLAGS += $(INCS) + +CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ + -DANI_LITTLE_BIT_ENDIAN \ + -DDOT11F_LITTLE_ENDIAN_HOST \ + -DANI_COMPILER_TYPE_GCC \ + -DANI_OS_TYPE_ANDROID=6 \ + -DPTT_SOCK_SVC_ENABLE \ + -Wall\ + -Werror\ + -D__linux__ \ + -DDEBUG + + +ifeq (y,$(filter y,$(CONFIG_MACH_XIAOMI_RAPHAEL))) + CDEFINES += -DTFA_NON_DSP_SOLUTION +endif + +KBUILD_CPPFLAGS += $(CDEFINES) + +# Currently, for versions of gcc which support it, the kernel Makefile +# is disabling the maybe-uninitialized warning. Re-enable it for the +# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it +# will override the kernel settings. +ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y) +EXTRA_CFLAGS += -Wmaybe-uninitialized +endif +#EXTRA_CFLAGS += -Wmissing-prototypes + +ifeq ($(call cc-option-yn, -Wheader-guard),y) +EXTRA_CFLAGS += -Wheader-guard +endif + +ifeq ($(KERNEL_BUILD), 0) +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers +KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers +endif + +# Module information used by KBuild framework +obj-$(CONFIG_SND_SOC_TFA9874) += tfa98xx_dlkm.o +tfa98xx_dlkm-y := $(TFA98XX_OBJS) diff --git a/techpack/audio/asoc/codecs/tfa98xx/Kconfig b/techpack/audio/asoc/codecs/tfa98xx/Kconfig new file mode 100644 index 000000000000..82115774f64e --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/Kconfig @@ -0,0 +1,5 @@ +config SND_SOC_TFA9874 + tristate "NXP TFA9874A audio amplifier" + help + Say Y here if you want to add support for the NXP TFA9874A audio + amplifier. diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/config.h b/techpack/audio/asoc/codecs/tfa98xx/inc/config.h new file mode 100644 index 000000000000..d057bc3394fb --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/config.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + Linux kernel specific definitions used by code shared with + Linux/Windows user space. +*/ + +#ifndef __CONFIG_LINUX_KERNEL_INC__ +#define __CONFIG_LINUX_KERNEL_INC__ + +#include +#include +#include +#include +#include + +#define _ASSERT(e) +#define PRINT_ASSERT(e) \ + if ((e)) \ + printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n", \ + __FUNCTION__, __FILE__, __LINE__, e) + +#if defined(CONFIG_TRACING) && defined(DEBUG) +#define tfa98xx_trace_printk(...) trace_printk(__VA_ARGS__) +#else +#define tfa98xx_trace_printk(...) +#endif + +#endif /* __CONFIG_LINUX_KERNEL_INC__ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/dbgprint.h b/techpack/audio/asoc/codecs/tfa98xx/inc/dbgprint.h new file mode 100644 index 000000000000..1abaf5fecb7f --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/dbgprint.h @@ -0,0 +1,200 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _DBGPRINT_H +#define _DBGPRINT_H + +/* Debugging macro's. */ +#ifndef DEBUG +#define DEBUG +#endif + +#ifndef ASSERT +//#define ASSERT +#endif +//TODO wwwim +#ifndef _ASSERT +#define _ASSERT(e) +#endif + +#ifndef PREFIX +#define PREFIX "tfa98xx: " +#define DRIVER_NAME "tfa98xx" +#endif + +#ifdef __KERNEL__ + +#ifdef DEBUG +#define _DEBUG(level, fmt, va...) \ + do { \ + if (unlikely(debug >= (level))) \ + printk(KERN_INFO PREFIX "%s:%d: " fmt, __func__, \ + __LINE__, ##va); \ + } while (0) + +#else +#define _DEBUG(level, fmt, va...) \ + do { \ + } while (0) +#endif + +#define MSG(fmt, va...) \ + printk(KERN_INFO PREFIX "%s:%d: " fmt, __func__, __LINE__, ##va) +#define _ERRORMSG(fmt, va...) \ + printk(KERN_ERR PREFIX "ERROR %s:%d: " fmt, __func__, __LINE__, ##va) + +#define DEBUG0(x...) MSG(x) +#define DEBUG1(x...) _DEBUG(1, x) +#define DEBUG2(x...) _DEBUG(2, x) +#define DEBUG3(x...) _DEBUG(3, x) +#define ERRORMSG(x...) _ERRORMSG(x) +#define PRINT(x...) printk(x) +#define PRINT_ERROR(x...) printk(KERN_INFO PREFIX " **ERROR** " x) +#define PRINT_ASSERT(e) \ + if ((e)) \ + printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n", \ + __FUNCTION__, __FILE__, __LINE__, e) + +#define PRINT_ENTRY DEBUG2("+[%s]\n", __func__) +#define PRINT_EXIT DEBUG2("-[%s]\n", __func__) + +#ifdef ASSERT +#define assert(cond, action) \ + do { \ + if (unlikely(!(cond))) { \ + DEBUG0("Assert: %s\n", #cond); \ + action; \ + } \ + } while (0) +#else +#define assert(cond, action) \ + do { \ + } while (0) +#endif + +#else /* __KERNEL__ */ +#if defined(WIN32) || defined(_X64) +#include +/* user mode */ +#ifdef DEBUG +#define _DEBUGMSG(level, fmt, ...) \ + printf(PREFIX "%s:%d: " fmt, __FUNCTION__, __LINE__, __VA_ARGS__); +#else +#define _DEBUGMSG(level, fmt, ...) \ + do { \ + } while (0) +#endif + +#define _ERRORMSG(fmt, ...) \ + printf(PREFIX "%s:%s:%d: " fmt, __FILE__, __FUNCTION__, __LINE__, \ + __VA_ARGS__) + +#define DEBUG0(...) MSG(__VA_ARGS__) +#define DEBUG1(...) _DEBUGMSG(1, __VA_ARGS__) +#define DEBUG2(...) _DEBUGMSG(2, __VA_ARGS__) +#define DEBUG3(...) _DEBUGMSG(3, __VA_ARGS__) +#define ERRORMSG(fmt, ...) _ERRORMSG(fmt, __VA_ARGS__) +#define PRINT(...) printf(__VA_ARGS__) +/* +# define PRINT(...) { FILE *stream; \ + if((stream = freopen("nxp_tfa.txt", "ab+", stdout)) == NULL) exit(-1); \ + printf(__VA_ARGS__); \ + freopen( "CON", "ab+", stdout ); \ + } +*/ +#define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__) +#define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__) +#define PRINT_ASSERT(e) \ + if ((e)) \ + fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n", \ + __FUNCTION__, __FILE__, __LINE__, e) +//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e)) + +#elif defined(__CODE_RED) +#include "app_global.h" +#ifdef DEBUG +#define _DEBUG(level, fmt, va...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, va)) +//printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va); +#else +#define _DEBUG(level, fmt, va...) \ + do { \ + } while (0) +#endif + +#define MSG(fmt, ...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__)) +//printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va) +//TB_TRACE_INF(TbTracePfx2(APP_PFX,TB_FUNC,"path=%s, chan=%u, muted=%s, vol=%d\n", +// path->isRecording ? "recording" : "playback", +// i, +// channelVol.currentMuteValue ? "YES" : "NO", +// channelVol.currentVolumeValue +// )); +//# define _ERRORMSG(fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va)) +#define ERRORMSG(...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, __VA_ARGS__)) +//fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va) + +#define DEBUG0(x...) MSG(x) +#define DEBUG1(x...) _DEBUG(1, x) +#define DEBUG2(x...) _DEBUG(2, x) +#define DEBUG3(x...) _DEBUG(3, x) +//# define ERRORMSG(x...) _ERRORMSG(x) +#define PRINT(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x)) +//printf(x) +#define PRINT_ERROR(x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x)) +//fprintf(stderr,__VA_ARGS__) +#define PRINT_FILE(file, x...) TB_TRACE_INF(TbTracePfx2("tfa", TB_FUNC, x)) +//fprintf(file,__VA_ARGS__) +#define PRINT_ASSERT(e) +//TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,Tfa98xx_GetErrorString(e))) +//if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e)) +#else +#include +/* user mode */ +#ifdef DEBUG +#define _DEBUG(level, fmt, va...) \ + printf(PREFIX "%s:%d: " fmt, __func__, __LINE__, ##va); +#else +#define _DEBUG(level, fmt, va...) \ + do { \ + } while (0) +#endif + +#define MSG(fmt, va...) \ + printf(PREFIX "%s:%s:%d: " fmt, __FILE__, __func__, __LINE__, ##va) +#define _ERRORMSG(fmt, va...) \ + fprintf(stderr, PREFIX "ERROR %s:%s:%d: " fmt, __FILE__, __func__, \ + __LINE__, ##va) + +#define DEBUG0(x...) MSG(x) +#define DEBUG1(x...) _DEBUG(1, x) +#define DEBUG2(x...) _DEBUG(2, x) +#define DEBUG3(x...) _DEBUG(3, x) +#define ERRORMSG(x...) _ERRORMSG(x) +#define PRINT(x...) printf(x) +#define PRINT_ERROR(...) fprintf(stderr, __VA_ARGS__) +#define PRINT_FILE(file, ...) fprintf(file, __VA_ARGS__) +#define PRINT_ASSERT(e) \ + if ((e)) \ + fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n", \ + __FUNCTION__, __FILE__, __LINE__, e) +//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e)) + +#endif /* WIN32 */ + +#endif /* user */ + +#endif /* _DBGPRINT_H --------------- */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h b/techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h new file mode 100644 index 000000000000..8303b93c3498 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h @@ -0,0 +1,33 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPK_ID_H_ +#define __SPK_ID_H_ + +#include +#include + +#define PIN_PULL_DOWN 0 +#define PIN_PULL_UP 1 +#define PIN_FLOAT 2 + +#define VENDOR_ID_NONE 0 +#define VENDOR_ID_AAC 1 +#define VENDOR_ID_SSI 2 +#define VENDOR_ID_GOER 3 + +#define VENDOR_ID_UNKNOWN 4 + +extern int spk_id_get_pin_3state(struct device_node *np); + +#endif diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa.h new file mode 100644 index 000000000000..9c1762dba314 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa.h @@ -0,0 +1,57 @@ +/* + * Copyright 2015-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef TFA_H_ +#define TFA_H_ + +/* set the limit for the container file length */ +#define TFA_MAX_CNT_LENGTH (256 * 1024) + +extern struct tfa_device **devs; + +/** + * tfa error return codes + */ +enum tfa_error { + tfa_error_ok, /**< no error */ + tfa_error_device, /**< no response from device */ + tfa_error_bad_param, /**< parameter no accepted */ + tfa_error_noclock, /**< required clock not present */ + tfa_error_timeout, /**< a timeout occurred */ + tfa_error_dsp, /**< a DSP error was returned */ + tfa_error_container, /**< no or wrong container file */ + tfa_error_max /**< impossible value, max enum */ +}; + +enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx); + +struct tfa_device **tfa_devs_create(int count); +void tfa_devs_destroy(int count); + +struct tfa_device **tfa_get_device_struct(void); + +/*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ +#ifdef __KERNEL__ +int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep, + u8 pcm_format); +#else +int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep); +#endif +/*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ +void tfa_lp_mode_interrupt(struct tfa_device *tfa); + +#endif /* TFA_H_ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa1_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa1_tfafieldnames.h new file mode 100644 index 000000000000..53a7db921df7 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa1_tfafieldnames.h @@ -0,0 +1,1705 @@ +/** Filename: Tfa1_TfaFieldnames.h + * This file was generated automatically on 03/20/2015 at 01:55:46 PM. + * Source file: TFA9897N1B_I2C_list_URT_Source_v34.xls + */ +#define TFA9897_I2CVERSION 34 +typedef enum nxpTfa1BfEnumList { + TFA1_BF_VDDS = + 0x0000, /*!< Power-on-reset flag */ + TFA1_BF_PLLS = + 0x0010, /*!< PLL lock */ + TFA1_BF_OTDS = + 0x0020, /*!< Over Temperature Protection alarm */ + TFA1_BF_OVDS = + 0x0030, /*!< Over Voltage Protection alarm */ + TFA1_BF_UVDS = + 0x0040, /*!< Under Voltage Protection alarm */ + TFA1_BF_OCDS = + 0x0050, /*!< Over Current Protection alarm */ + TFA1_BF_CLKS = + 0x0060, /*!< Clocks stable flag */ + TFA1_BF_CLIPS = + 0x0070, /*!< Amplifier clipping */ + TFA1_BF_MTPB = + 0x0080, /*!< MTP busy */ + TFA1_BF_NOCLK = + 0x0090, /*!< Flag lost clock from clock generation unit */ + TFA1_BF_SPKS = + 0x00a0, /*!< Speaker error flag */ + TFA1_BF_ACS = + 0x00b0, /*!< Cold Start flag */ + TFA1_BF_SWS = + 0x00c0, /*!< Flag Engage */ + TFA1_BF_WDS = + 0x00d0, /*!< Flag watchdog reset */ + TFA1_BF_AMPS = + 0x00e0, /*!< Amplifier is enabled by manager */ + TFA1_BF_AREFS = + 0x00f0, /*!< References are enabled by manager */ + TFA1_BF_BATS = + 0x0109, /*!< Battery voltage readout; 0 .. 5.5 [V] */ + TFA1_BF_TEMPS = + 0x0208, /*!< Temperature readout from the temperature sensor */ + TFA1_BF_REV = + 0x030b, /*!< Device type number is B97 */ + TFA1_BF_RCV = + 0x0420, /*!< Enable Receiver Mode */ + TFA1_BF_CHS12 = + 0x0431, /*!< Channel Selection TDM input for Coolflux */ + TFA1_BF_INPLVL = + 0x0450, /*!< Input level selection control */ + TFA1_BF_CHSA = + 0x0461, /*!< Input selection for amplifier */ + TFA1_BF_I2SDOE = + 0x04b0, /*!< Enable data output */ + TFA1_BF_AUDFS = + 0x04c3, /*!< Audio sample rate setting */ + TFA1_BF_BSSCR = + 0x0501, /*!< Protection Attack Time */ + TFA1_BF_BSST = + 0x0523, /*!< ProtectionThreshold */ + TFA1_BF_BSSRL = + 0x0561, /*!< Protection Maximum Reduction */ + TFA1_BF_BSSRR = + 0x0582, /*!< Battery Protection Release Time */ + TFA1_BF_BSSHY = + 0x05b1, /*!< Battery Protection Hysteresis */ + TFA1_BF_BSSR = + 0x05e0, /*!< battery voltage for I2C read out only */ + TFA1_BF_BSSBY = + 0x05f0, /*!< bypass clipper battery protection */ + TFA1_BF_DPSA = + 0x0600, /*!< Enable dynamic powerstage activation */ + TFA1_BF_CFSM = + 0x0650, /*!< Soft mute in CoolFlux */ + TFA1_BF_BSSS = + 0x0670, /*!< BatSenseSteepness */ + TFA1_BF_VOL = + 0x0687, /*!< volume control (in CoolFlux) */ + TFA1_BF_DCVO = + 0x0702, /*!< Boost Voltage */ + TFA1_BF_DCMCC = + 0x0733, /*!< Max boost coil current - step of 175 mA */ + TFA1_BF_DCIE = + 0x07a0, /*!< Adaptive boost mode */ + TFA1_BF_DCSR = + 0x07b0, /*!< Soft RampUp/Down mode for DCDC controller */ + TFA1_BF_DCPAVG = + 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */ + TFA1_BF_TROS = + 0x0800, /*!< Select external temperature also the ext_temp will be put on the temp read out */ + TFA1_BF_EXTTS = + 0x0818, /*!< external temperature setting to be given by host */ + TFA1_BF_PWDN = + 0x0900, /*!< Device Mode */ + TFA1_BF_I2CR = + 0x0910, /*!< I2C Reset */ + TFA1_BF_CFE = + 0x0920, /*!< Enable CoolFlux */ + TFA1_BF_AMPE = + 0x0930, /*!< Enable Amplifier */ + TFA1_BF_DCA = + 0x0940, /*!< EnableBoost */ + TFA1_BF_SBSL = + 0x0950, /*!< Coolflux configured */ + TFA1_BF_AMPC = + 0x0960, /*!< Selection on how Amplifier is enabled */ + TFA1_BF_DCDIS = + 0x0970, /*!< DCDC not connected */ + TFA1_BF_PSDR = + 0x0980, /*!< IDDQ test amplifier */ + TFA1_BF_DCCV = + 0x0991, /*!< Coil Value */ + TFA1_BF_CCFD = + 0x09b0, /*!< Selection CoolFlux Clock */ + TFA1_BF_INTPAD = + 0x09c1, /*!< INT pad configuration control */ + TFA1_BF_IPLL = + 0x09e0, /*!< PLL input reference clock selection */ + TFA1_BF_MTPK = + 0x0b07, /*!< 5Ah, 90d To access KEY1_Protected registers (Default for engineering) */ + TFA1_BF_CVFDLY = + 0x0c25, /*!< Fractional delay adjustment between current and voltage sense */ + TFA1_BF_TDMPRF = + 0x1011, /*!< TDM_usecase */ + TFA1_BF_TDMEN = + 0x1030, /*!< TDM interface control */ + TFA1_BF_TDMCKINV = + 0x1040, /*!< TDM clock inversion */ + TFA1_BF_TDMFSLN = + 0x1053, /*!< TDM FS length */ + TFA1_BF_TDMFSPOL = + 0x1090, /*!< TDM FS polarity */ + TFA1_BF_TDMSAMSZ = + 0x10a4, /*!< TDM Sample Size for all tdm sinks/sources */ + TFA1_BF_TDMSLOTS = + 0x1103, /*!< Number of slots */ + TFA1_BF_TDMSLLN = + 0x1144, /*!< Slot length */ + TFA1_BF_TDMBRMG = + 0x1194, /*!< Bits remaining */ + TFA1_BF_TDMDDEL = + 0x11e0, /*!< Data delay */ + TFA1_BF_TDMDADJ = + 0x11f0, /*!< Data adjustment */ + TFA1_BF_TDMTXFRM = + 0x1201, /*!< TXDATA format */ + TFA1_BF_TDMUUS0 = + 0x1221, /*!< TXDATA format unused slot sd0 */ + TFA1_BF_TDMUUS1 = + 0x1241, /*!< TXDATA format unused slot sd1 */ + TFA1_BF_TDMSI0EN = + 0x1270, /*!< TDM sink0 enable */ + TFA1_BF_TDMSI1EN = + 0x1280, /*!< TDM sink1 enable */ + TFA1_BF_TDMSI2EN = + 0x1290, /*!< TDM sink2 enable */ + TFA1_BF_TDMSO0EN = + 0x12a0, /*!< TDM source0 enable */ + TFA1_BF_TDMSO1EN = + 0x12b0, /*!< TDM source1 enable */ + TFA1_BF_TDMSO2EN = + 0x12c0, /*!< TDM source2 enable */ + TFA1_BF_TDMSI0IO = + 0x12d0, /*!< tdm_sink0_io */ + TFA1_BF_TDMSI1IO = + 0x12e0, /*!< tdm_sink1_io */ + TFA1_BF_TDMSI2IO = + 0x12f0, /*!< tdm_sink2_io */ + TFA1_BF_TDMSO0IO = + 0x1300, /*!< tdm_source0_io */ + TFA1_BF_TDMSO1IO = + 0x1310, /*!< tdm_source1_io */ + TFA1_BF_TDMSO2IO = + 0x1320, /*!< tdm_source2_io */ + TFA1_BF_TDMSI0SL = + 0x1333, /*!< sink0_slot [GAIN IN] */ + TFA1_BF_TDMSI1SL = + 0x1373, /*!< sink1_slot [CH1 IN] */ + TFA1_BF_TDMSI2SL = + 0x13b3, /*!< sink2_slot [CH2 IN] */ + TFA1_BF_TDMSO0SL = + 0x1403, /*!< source0_slot [GAIN OUT] */ + TFA1_BF_TDMSO1SL = + 0x1443, /*!< source1_slot [Voltage Sense] */ + TFA1_BF_TDMSO2SL = + 0x1483, /*!< source2_slot [Current Sense] */ + TFA1_BF_NBCK = + 0x14c3, /*!< NBCK */ + TFA1_BF_INTOVDDS = + 0x2000, /*!< flag_por_int_out */ + TFA1_BF_INTOPLLS = + 0x2010, /*!< flag_pll_lock_int_out */ + TFA1_BF_INTOOTDS = + 0x2020, /*!< flag_otpok_int_out */ + TFA1_BF_INTOOVDS = + 0x2030, /*!< flag_ovpok_int_out */ + TFA1_BF_INTOUVDS = + 0x2040, /*!< flag_uvpok_int_out */ + TFA1_BF_INTOOCDS = + 0x2050, /*!< flag_ocp_alarm_int_out */ + TFA1_BF_INTOCLKS = + 0x2060, /*!< flag_clocks_stable_int_out */ + TFA1_BF_INTOCLIPS = + 0x2070, /*!< flag_clip_int_out */ + TFA1_BF_INTOMTPB = + 0x2080, /*!< mtp_busy_int_out */ + TFA1_BF_INTONOCLK = + 0x2090, /*!< flag_lost_clk_int_out */ + TFA1_BF_INTOSPKS = + 0x20a0, /*!< flag_cf_speakererror_int_out */ + TFA1_BF_INTOACS = + 0x20b0, /*!< flag_cold_started_int_out */ + TFA1_BF_INTOSWS = + 0x20c0, /*!< flag_engage_int_out */ + TFA1_BF_INTOWDS = + 0x20d0, /*!< flag_watchdog_reset_int_out */ + TFA1_BF_INTOAMPS = + 0x20e0, /*!< flag_enbl_amp_int_out */ + TFA1_BF_INTOAREFS = + 0x20f0, /*!< flag_enbl_ref_int_out */ + TFA1_BF_INTOACK = + 0x2201, /*!< Interrupt status register output - Corresponding flag */ + TFA1_BF_INTIVDDS = + 0x2300, /*!< flag_por_int_in */ + TFA1_BF_INTIPLLS = + 0x2310, /*!< flag_pll_lock_int_in */ + TFA1_BF_INTIOTDS = + 0x2320, /*!< flag_otpok_int_in */ + TFA1_BF_INTIOVDS = + 0x2330, /*!< flag_ovpok_int_in */ + TFA1_BF_INTIUVDS = + 0x2340, /*!< flag_uvpok_int_in */ + TFA1_BF_INTIOCDS = + 0x2350, /*!< flag_ocp_alarm_int_in */ + TFA1_BF_INTICLKS = + 0x2360, /*!< flag_clocks_stable_int_in */ + TFA1_BF_INTICLIPS = + 0x2370, /*!< flag_clip_int_in */ + TFA1_BF_INTIMTPB = + 0x2380, /*!< mtp_busy_int_in */ + TFA1_BF_INTINOCLK = + 0x2390, /*!< flag_lost_clk_int_in */ + TFA1_BF_INTISPKS = + 0x23a0, /*!< flag_cf_speakererror_int_in */ + TFA1_BF_INTIACS = + 0x23b0, /*!< flag_cold_started_int_in */ + TFA1_BF_INTISWS = + 0x23c0, /*!< flag_engage_int_in */ + TFA1_BF_INTIWDS = + 0x23d0, /*!< flag_watchdog_reset_int_in */ + TFA1_BF_INTIAMPS = + 0x23e0, /*!< flag_enbl_amp_int_in */ + TFA1_BF_INTIAREFS = + 0x23f0, /*!< flag_enbl_ref_int_in */ + TFA1_BF_INTIACK = + 0x2501, /*!< Interrupt register input */ + TFA1_BF_INTENVDDS = + 0x2600, /*!< flag_por_int_enable */ + TFA1_BF_INTENPLLS = + 0x2610, /*!< flag_pll_lock_int_enable */ + TFA1_BF_INTENOTDS = + 0x2620, /*!< flag_otpok_int_enable */ + TFA1_BF_INTENOVDS = + 0x2630, /*!< flag_ovpok_int_enable */ + TFA1_BF_INTENUVDS = + 0x2640, /*!< flag_uvpok_int_enable */ + TFA1_BF_INTENOCDS = + 0x2650, /*!< flag_ocp_alarm_int_enable */ + TFA1_BF_INTENCLKS = + 0x2660, /*!< flag_clocks_stable_int_enable */ + TFA1_BF_INTENCLIPS = + 0x2670, /*!< flag_clip_int_enable */ + TFA1_BF_INTENMTPB = + 0x2680, /*!< mtp_busy_int_enable */ + TFA1_BF_INTENNOCLK = + 0x2690, /*!< flag_lost_clk_int_enable */ + TFA1_BF_INTENSPKS = + 0x26a0, /*!< flag_cf_speakererror_int_enable */ + TFA1_BF_INTENACS = + 0x26b0, /*!< flag_cold_started_int_enable */ + TFA1_BF_INTENSWS = + 0x26c0, /*!< flag_engage_int_enable */ + TFA1_BF_INTENWDS = + 0x26d0, /*!< flag_watchdog_reset_int_enable */ + TFA1_BF_INTENAMPS = + 0x26e0, /*!< flag_enbl_amp_int_enable */ + TFA1_BF_INTENAREFS = + 0x26f0, /*!< flag_enbl_ref_int_enable */ + TFA1_BF_INTENACK = + 0x2801, /*!< Interrupt enable register */ + TFA1_BF_INTPOLVDDS = + 0x2900, /*!< flag_por_int_pol */ + TFA1_BF_INTPOLPLLS = + 0x2910, /*!< flag_pll_lock_int_pol */ + TFA1_BF_INTPOLOTDS = + 0x2920, /*!< flag_otpok_int_pol */ + TFA1_BF_INTPOLOVDS = + 0x2930, /*!< flag_ovpok_int_pol */ + TFA1_BF_INTPOLUVDS = + 0x2940, /*!< flag_uvpok_int_pol */ + TFA1_BF_INTPOLOCDS = + 0x2950, /*!< flag_ocp_alarm_int_pol */ + TFA1_BF_INTPOLCLKS = + 0x2960, /*!< flag_clocks_stable_int_pol */ + TFA1_BF_INTPOLCLIPS = + 0x2970, /*!< flag_clip_int_pol */ + TFA1_BF_INTPOLMTPB = + 0x2980, /*!< mtp_busy_int_pol */ + TFA1_BF_INTPOLNOCLK = + 0x2990, /*!< flag_lost_clk_int_pol */ + TFA1_BF_INTPOLSPKS = + 0x29a0, /*!< flag_cf_speakererror_int_pol */ + TFA1_BF_INTPOLACS = + 0x29b0, /*!< flag_cold_started_int_pol */ + TFA1_BF_INTPOLSWS = + 0x29c0, /*!< flag_engage_int_pol */ + TFA1_BF_INTPOLWDS = + 0x29d0, /*!< flag_watchdog_reset_int_pol */ + TFA1_BF_INTPOLAMPS = + 0x29e0, /*!< flag_enbl_amp_int_pol */ + TFA1_BF_INTPOLAREFS = + 0x29f0, /*!< flag_enbl_ref_int_pol */ + TFA1_BF_INTPOLACK = + 0x2b01, /*!< Interrupt status flags polarity register */ + TFA1_BF_CLIP = + 0x4900, /*!< Bypass clip control */ + TFA1_BF_CIMTP = + 0x62b0, /*!< start copying all the data from i2cregs_mtp to mtp [Key 2 protected] */ + TFA1_BF_RST = + 0x7000, /*!< Reset CoolFlux DSP */ + TFA1_BF_DMEM = + 0x7011, /*!< Target memory for access */ + TFA1_BF_AIF = + 0x7030, /*!< Autoincrement-flag for memory-address */ + TFA1_BF_CFINT = + 0x7040, /*!< Interrupt CoolFlux DSP */ + TFA1_BF_REQ = + 0x7087, /*!< request for access (8 channels) */ + TFA1_BF_REQCMD = + 0x7080, /*!< Firmware event request rpc command */ + TFA1_BF_REQRST = + 0x7090, /*!< Firmware event request reset restart */ + TFA1_BF_REQMIPS = + 0x70a0, /*!< Firmware event request short on mips */ + TFA1_BF_REQMUTED = + 0x70b0, /*!< Firmware event request mute sequence ready */ + TFA1_BF_REQVOL = + 0x70c0, /*!< Firmware event request volume ready */ + TFA1_BF_REQDMG = + 0x70d0, /*!< Firmware event request speaker damage detected */ + TFA1_BF_REQCAL = + 0x70e0, /*!< Firmware event request calibration completed */ + TFA1_BF_REQRSV = + 0x70f0, /*!< Firmware event request reserved */ + TFA1_BF_MADD = + 0x710f, /*!< memory-address to be accessed */ + TFA1_BF_MEMA = + 0x720f, /*!< activate memory access (24- or 32-bits data is written/read to/from memory */ + TFA1_BF_ERR = + 0x7307, /*!< Coolflux error flags */ + TFA1_BF_ACK = + 0x7387, /*!< acknowledge of requests (8 channels) */ + TFA1_BF_MTPOTC = + 0x8000, /*!< Calibration schedule (key2 protected) */ + TFA1_BF_MTPEX = + 0x8010, /*!< (key2 protected) */ +} nxpTfa1BfEnumList_t; +#define TFA1_NAMETABLE \ + static tfaBfName_t Tfa1DatasheetNames[] = { \ + { 0x0, \ + "VDDS" }, /* Power-on-reset flag , */ \ + { 0x10, \ + "PLLS" }, /* PLL lock , */ \ + { 0x20, \ + "OTDS" }, /* Over Temperature Protection alarm , */ \ + { 0x30, \ + "OVDS" }, /* Over Voltage Protection alarm , */ \ + { 0x40, \ + "UVDS" }, /* Under Voltage Protection alarm , */ \ + { 0x50, \ + "OCDS" }, /* Over Current Protection alarm , */ \ + { 0x60, \ + "CLKS" }, /* Clocks stable flag , */ \ + { 0x70, \ + "CLIPS" }, /* Amplifier clipping , */ \ + { 0x80, \ + "MTPB" }, /* MTP busy , */ \ + { 0x90, \ + "NOCLK" }, /* Flag lost clock from clock generation unit , */ \ + { 0xa0, \ + "SPKS" }, /* Speaker error flag , */ \ + { 0xb0, \ + "ACS" }, /* Cold Start flag , */ \ + { 0xc0, \ + "SWS" }, /* Flag Engage , */ \ + { 0xd0, \ + "WDS" }, /* Flag watchdog reset , */ \ + { 0xe0, \ + "AMPS" }, /* Amplifier is enabled by manager , */ \ + { 0xf0, \ + "AREFS" }, /* References are enabled by manager , */ \ + { 0x109, \ + "BATS" }, /* Battery voltage readout; 0 .. 5.5 [V] , */ \ + { 0x208, \ + "TEMPS" }, /* Temperature readout from the temperature sensor , */ \ + { 0x30b, \ + "REV" }, /* Device type number is B97 , */ \ + { 0x420, \ + "RCV" }, /* Enable Receiver Mode , */ \ + { 0x431, \ + "CHS12" }, /* Channel Selection TDM input for Coolflux , */ \ + { 0x450, \ + "INPLVL" }, /* Input level selection control , */ \ + { 0x461, \ + "CHSA" }, /* Input selection for amplifier , */ \ + { 0x4b0, \ + "I2SDOE" }, /* Enable data output , */ \ + { 0x4c3, \ + "AUDFS" }, /* Audio sample rate setting , */ \ + { 0x501, \ + "SSCR" }, /* Protection Attack Time , */ \ + { 0x523, \ + "SST" }, /* ProtectionThreshold , */ \ + { 0x561, \ + "SSRL" }, /* Protection Maximum Reduction , */ \ + { 0x582, \ + "SSRR" }, /* Battery Protection Release Time , */ \ + { 0x5b1, \ + "SSHY" }, /* Battery Protection Hysteresis , */ \ + { 0x5e0, \ + "SSR" }, /* battery voltage for I2C read out only , */ \ + { 0x5f0, \ + "SSBY" }, /* bypass clipper battery protection , */ \ + { 0x600, \ + "DPSA" }, /* Enable dynamic powerstage activation , */ \ + { 0x650, \ + "CFSM" }, /* Soft mute in CoolFlux , */ \ + { 0x670, \ + "SSS" }, /* BatSenseSteepness , */ \ + { 0x687, \ + "VOL" }, /* volume control (in CoolFlux) , */ \ + { 0x702, \ + "DCVO" }, /* Boost Voltage , */ \ + { 0x733, \ + "DCMCC" }, /* Max boost coil current - step of 175 mA , */ \ + { 0x7a0, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x7b0, \ + "DCSR" }, /* Soft RampUp/Down mode for DCDC controller , */ \ + { 0x7c0, \ + "DCPAVG" }, /* ctrl_peak2avg for analog part of DCDC , */ \ + { 0x800, \ + "TROS" }, /* Select external temperature also the ext_temp will be put on the temp read out , */ \ + { 0x818, \ + "EXTTS" }, /* external temperature setting to be given by host , */ \ + { 0x900, \ + "PWDN" }, /* Device Mode , */ \ + { 0x910, \ + "I2CR" }, /* I2C Reset , */ \ + { 0x920, \ + "CFE" }, /* Enable CoolFlux , */ \ + { 0x930, \ + "AMPE" }, /* Enable Amplifier , */ \ + { 0x940, \ + "DCA" }, /* EnableBoost , */ \ + { 0x950, \ + "SBSL" }, /* Coolflux configured , */ \ + { 0x960, \ + "AMPC" }, /* Selection on how Amplifier is enabled , */ \ + { 0x970, \ + "DCDIS" }, /* DCDC not connected , */ \ + { 0x980, \ + "PSDR" }, /* IDDQ test amplifier , */ \ + { 0x991, \ + "DCCV" }, /* Coil Value , */ \ + { 0x9b0, \ + "CCFD" }, /* Selection CoolFlux Clock , */ \ + { 0x9c1, \ + "INTPAD" }, /* INT pad configuration control , */ \ + { 0x9e0, \ + "IPLL" }, /* PLL input reference clock selection , */ \ + { 0xb07, \ + "MTPK" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0xc25, \ + "CVFDLY" }, /* Fractional delay adjustment between current and voltage sense, */ \ + { 0x1011, \ + "TDMPRF" }, /* TDM_usecase , */ \ + { 0x1030, \ + "TDMEN" }, /* TDM interface control , */ \ + { 0x1040, \ + "TDMCKINV" }, /* TDM clock inversion , */ \ + { 0x1053, \ + "TDMFSLN" }, /* TDM FS length , */ \ + { 0x1090, \ + "TDMFSPOL" }, /* TDM FS polarity , */ \ + { 0x10a4, \ + "TDMSAMSZ" }, /* TDM Sample Size for all tdm sinks/sources , */ \ + { 0x1103, \ + "TDMSLOTS" }, /* Number of slots , */ \ + { 0x1144, \ + "TDMSLLN" }, /* Slot length , */ \ + { 0x1194, \ + "TDMBRMG" }, /* Bits remaining , */ \ + { 0x11e0, \ + "TDMDDEL" }, /* Data delay , */ \ + { 0x11f0, \ + "TDMDADJ" }, /* Data adjustment , */ \ + { 0x1201, \ + "TDMTXFRM" }, /* TXDATA format , */ \ + { 0x1221, \ + "TDMUUS0" }, /* TXDATA format unused slot sd0 , */ \ + { 0x1241, \ + "TDMUUS1" }, /* TXDATA format unused slot sd1 , */ \ + { 0x1270, \ + "TDMSI0EN" }, /* TDM sink0 enable , */ \ + { 0x1280, \ + "TDMSI1EN" }, /* TDM sink1 enable , */ \ + { 0x1290, \ + "TDMSI2EN" }, /* TDM sink2 enable , */ \ + { 0x12a0, \ + "TDMSO0EN" }, /* TDM source0 enable , */ \ + { 0x12b0, \ + "TDMSO1EN" }, /* TDM source1 enable , */ \ + { 0x12c0, \ + "TDMSO2EN" }, /* TDM source2 enable , */ \ + { 0x12d0, \ + "TDMSI0IO" }, /* tdm_sink0_io , */ \ + { 0x12e0, \ + "TDMSI1IO" }, /* tdm_sink1_io , */ \ + { 0x12f0, \ + "TDMSI2IO" }, /* tdm_sink2_io , */ \ + { 0x1300, \ + "TDMSO0IO" }, /* tdm_source0_io , */ \ + { 0x1310, \ + "TDMSO1IO" }, /* tdm_source1_io , */ \ + { 0x1320, \ + "TDMSO2IO" }, /* tdm_source2_io , */ \ + { 0x1333, \ + "TDMSI0SL" }, /* sink0_slot [GAIN IN] , */ \ + { 0x1373, \ + "TDMSI1SL" }, /* sink1_slot [CH1 IN] , */ \ + { 0x13b3, \ + "TDMSI2SL" }, /* sink2_slot [CH2 IN] , */ \ + { 0x1403, \ + "TDMSO0SL" }, /* source0_slot [GAIN OUT] , */ \ + { 0x1443, \ + "TDMSO1SL" }, /* source1_slot [Voltage Sense] , */ \ + { 0x1483, \ + "TDMSO2SL" }, /* source2_slot [Current Sense] , */ \ + { 0x14c3, \ + "NBCK" }, /* NBCK , */ \ + { 0x2000, \ + "INTOVDDS" }, /* flag_por_int_out , */ \ + { 0x2010, \ + "INTOPLLS" }, /* flag_pll_lock_int_out , */ \ + { 0x2020, \ + "INTOOTDS" }, /* flag_otpok_int_out , */ \ + { 0x2030, \ + "INTOOVDS" }, /* flag_ovpok_int_out , */ \ + { 0x2040, \ + "INTOUVDS" }, /* flag_uvpok_int_out , */ \ + { 0x2050, \ + "INTOOCDS" }, /* flag_ocp_alarm_int_out , */ \ + { 0x2060, \ + "INTOCLKS" }, /* flag_clocks_stable_int_out , */ \ + { 0x2070, \ + "INTOCLIPS" }, /* flag_clip_int_out , */ \ + { 0x2080, \ + "INTOMTPB" }, /* mtp_busy_int_out , */ \ + { 0x2090, \ + "INTONOCLK" }, /* flag_lost_clk_int_out , */ \ + { 0x20a0, \ + "INTOSPKS" }, /* flag_cf_speakererror_int_out , */ \ + { 0x20b0, \ + "INTOACS" }, /* flag_cold_started_int_out , */ \ + { 0x20c0, \ + "INTOSWS" }, /* flag_engage_int_out , */ \ + { 0x20d0, \ + "INTOWDS" }, /* flag_watchdog_reset_int_out , */ \ + { 0x20e0, \ + "INTOAMPS" }, /* flag_enbl_amp_int_out , */ \ + { 0x20f0, \ + "INTOAREFS" }, /* flag_enbl_ref_int_out , */ \ + { 0x2201, \ + "INTOACK" }, /* Interrupt status register output - Corresponding flag, */ \ + { 0x2300, \ + "INTIVDDS" }, /* flag_por_int_in , */ \ + { 0x2310, \ + "INTIPLLS" }, /* flag_pll_lock_int_in , */ \ + { 0x2320, \ + "INTIOTDS" }, /* flag_otpok_int_in , */ \ + { 0x2330, \ + "INTIOVDS" }, /* flag_ovpok_int_in , */ \ + { 0x2340, \ + "INTIUVDS" }, /* flag_uvpok_int_in , */ \ + { 0x2350, \ + "INTIOCDS" }, /* flag_ocp_alarm_int_in , */ \ + { 0x2360, \ + "INTICLKS" }, /* flag_clocks_stable_int_in , */ \ + { 0x2370, \ + "INTICLIPS" }, /* flag_clip_int_in , */ \ + { 0x2380, \ + "INTIMTPB" }, /* mtp_busy_int_in , */ \ + { 0x2390, \ + "INTINOCLK" }, /* flag_lost_clk_int_in , */ \ + { 0x23a0, \ + "INTISPKS" }, /* flag_cf_speakererror_int_in , */ \ + { 0x23b0, \ + "INTIACS" }, /* flag_cold_started_int_in , */ \ + { 0x23c0, \ + "INTISWS" }, /* flag_engage_int_in , */ \ + { 0x23d0, \ + "INTIWDS" }, /* flag_watchdog_reset_int_in , */ \ + { 0x23e0, \ + "INTIAMPS" }, /* flag_enbl_amp_int_in , */ \ + { 0x23f0, \ + "INTIAREFS" }, /* flag_enbl_ref_int_in , */ \ + { 0x2501, \ + "INTIACK" }, /* Interrupt register input , */ \ + { 0x2600, \ + "INTENVDDS" }, /* flag_por_int_enable , */ \ + { 0x2610, \ + "INTENPLLS" }, /* flag_pll_lock_int_enable , */ \ + { 0x2620, \ + "INTENOTDS" }, /* flag_otpok_int_enable , */ \ + { 0x2630, \ + "INTENOVDS" }, /* flag_ovpok_int_enable , */ \ + { 0x2640, \ + "INTENUVDS" }, /* flag_uvpok_int_enable , */ \ + { 0x2650, \ + "INTENOCDS" }, /* flag_ocp_alarm_int_enable , */ \ + { 0x2660, \ + "INTENCLKS" }, /* flag_clocks_stable_int_enable , */ \ + { 0x2670, \ + "INTENCLIPS" }, /* flag_clip_int_enable , */ \ + { 0x2680, \ + "INTENMTPB" }, /* mtp_busy_int_enable , */ \ + { 0x2690, \ + "INTENNOCLK" }, /* flag_lost_clk_int_enable , */ \ + { 0x26a0, \ + "INTENSPKS" }, /* flag_cf_speakererror_int_enable , */ \ + { 0x26b0, \ + "INTENACS" }, /* flag_cold_started_int_enable , */ \ + { 0x26c0, \ + "INTENSWS" }, /* flag_engage_int_enable , */ \ + { 0x26d0, \ + "INTENWDS" }, /* flag_watchdog_reset_int_enable , */ \ + { 0x26e0, \ + "INTENAMPS" }, /* flag_enbl_amp_int_enable , */ \ + { 0x26f0, \ + "INTENAREFS" }, /* flag_enbl_ref_int_enable , */ \ + { 0x2801, \ + "INTENACK" }, /* Interrupt enable register , */ \ + { 0x2900, \ + "INTPOLVDDS" }, /* flag_por_int_pol , */ \ + { 0x2910, \ + "INTPOLPLLS" }, /* flag_pll_lock_int_pol , */ \ + { 0x2920, \ + "INTPOLOTDS" }, /* flag_otpok_int_pol , */ \ + { 0x2930, \ + "INTPOLOVDS" }, /* flag_ovpok_int_pol , */ \ + { 0x2940, \ + "INTPOLUVDS" }, /* flag_uvpok_int_pol , */ \ + { 0x2950, \ + "INTPOLOCDS" }, /* flag_ocp_alarm_int_pol , */ \ + { 0x2960, \ + "INTPOLCLKS" }, /* flag_clocks_stable_int_pol , */ \ + { 0x2970, \ + "INTPOLCLIPS" }, /* flag_clip_int_pol , */ \ + { 0x2980, \ + "INTPOLMTPB" }, /* mtp_busy_int_pol , */ \ + { 0x2990, \ + "INTPOLNOCLK" }, /* flag_lost_clk_int_pol , */ \ + { 0x29a0, \ + "INTPOLSPKS" }, /* flag_cf_speakererror_int_pol , */ \ + { 0x29b0, \ + "INTPOLACS" }, /* flag_cold_started_int_pol , */ \ + { 0x29c0, \ + "INTPOLSWS" }, /* flag_engage_int_pol , */ \ + { 0x29d0, \ + "INTPOLWDS" }, /* flag_watchdog_reset_int_pol , */ \ + { 0x29e0, \ + "INTPOLAMPS" }, /* flag_enbl_amp_int_pol , */ \ + { 0x29f0, \ + "INTPOLAREFS" }, /* flag_enbl_ref_int_pol , */ \ + { 0x2b01, \ + "INTPOLACK" }, /* Interrupt status flags polarity register , */ \ + { 0x4900, \ + "CLIP" }, /* Bypass clip control , */ \ + { 0x62b0, \ + "CIMTP" }, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */ \ + { 0x7000, \ + "RST" }, /* Reset CoolFlux DSP , */ \ + { 0x7011, \ + "DMEM" }, /* Target memory for access , */ \ + { 0x7030, \ + "AIF" }, /* Autoincrement-flag for memory-address , */ \ + { 0x7040, \ + "CFINT" }, /* Interrupt CoolFlux DSP , */ \ + { 0x7087, \ + "REQ" }, /* request for access (8 channels) , */ \ + { 0x7080, \ + "REQCMD" }, /* Firmware event request rpc command , */ \ + { 0x7090, \ + "REQRST" }, /* Firmware event request reset restart , */ \ + { 0x70a0, \ + "REQMIPS" }, /* Firmware event request short on mips , */ \ + { 0x70b0, \ + "REQMUTED" }, /* Firmware event request mute sequence ready , */ \ + { 0x70c0, \ + "REQVOL" }, /* Firmware event request volume ready , */ \ + { 0x70d0, \ + "REQDMG" }, /* Firmware event request speaker damage detected , */ \ + { 0x70e0, \ + "REQCAL" }, /* Firmware event request calibration completed , */ \ + { 0x70f0, \ + "REQRSV" }, /* Firmware event request reserved , */ \ + { 0x710f, \ + "MADD" }, /* memory-address to be accessed , */ \ + { 0x720f, \ + "MEMA" }, /* activate memory access (24- or 32-bits data is written/read to/from memory, */ \ + { 0x7307, \ + "ERR" }, /* Coolflux error flags , */ \ + { 0x7387, \ + "ACK" }, /* acknowledge of requests (8 channels) , */ \ + { 0x7380, \ + "ACKCMD" }, /* Firmware event acknowledge rpc command , */ \ + { 0x7390, \ + "ACKRST" }, /* Firmware event acknowledge reset restart , */ \ + { 0x73a0, \ + "ACKMIPS" }, /* Firmware event acknowledge short on mips , */ \ + { 0x73b0, \ + "ACKMUTED" }, /* Firmware event acknowledge mute sequence ready , */ \ + { 0x73c0, \ + "ACKVOL" }, /* Firmware event acknowledge volume ready , */ \ + { 0x73d0, \ + "ACKDMG" }, /* Firmware event acknowledge speaker damage detected, */ \ + { 0x73e0, \ + "ACKCAL" }, /* Firmware event acknowledge calibration completed , */ \ + { 0x73f0, \ + "ACKRSV" }, /* Firmware event acknowledge reserved , */ \ + { 0x8000, \ + "MTPOTC" }, /* Calibration schedule (key2 protected) , */ \ + { 0x8010, \ + "MTPEX" }, /* (key2 protected) , */ \ + { 0x8045, "SWPROFIL" }, \ + { 0x80a5, "SWVSTEP" }, \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA1_BITNAMETABLE \ + static tfaBfName_t Tfa1BitNames[] = { \ + { 0x0, \ + "flag_por" }, /* Power-on-reset flag , */ \ + { 0x10, \ + "flag_pll_lock" }, /* PLL lock , */ \ + { 0x20, \ + "flag_otpok" }, /* Over Temperature Protection alarm , */ \ + { 0x30, \ + "flag_ovpok" }, /* Over Voltage Protection alarm , */ \ + { 0x40, \ + "flag_uvpok" }, /* Under Voltage Protection alarm , */ \ + { 0x50, \ + "flag_ocp_alarm" }, /* Over Current Protection alarm , */ \ + { 0x60, \ + "flag_clocks_stable" }, /* Clocks stable flag , */ \ + { 0x70, \ + "flag_clip" }, /* Amplifier clipping , */ \ + { 0x80, \ + "mtp_busy" }, /* MTP busy , */ \ + { 0x90, \ + "flag_lost_clk" }, /* Flag lost clock from clock generation unit , */ \ + { 0xa0, \ + "flag_cf_speakererror" }, /* Speaker error flag , */ \ + { 0xb0, \ + "flag_cold_started" }, /* Cold Start flag , */ \ + { 0xc0, \ + "flag_engage" }, /* Flag Engage , */ \ + { 0xd0, \ + "flag_watchdog_reset" }, /* Flag watchdog reset , */ \ + { 0xe0, \ + "flag_enbl_amp" }, /* Amplifier is enabled by manager , */ \ + { 0xf0, \ + "flag_enbl_ref" }, /* References are enabled by manager , */ \ + { 0x109, \ + "bat_adc" }, /* Battery voltage readout; 0 .. 5.5 [V] , */ \ + { 0x208, \ + "temp_adc" }, /* Temperature readout from the temperature sensor , */ \ + { 0x30b, \ + "rev_reg" }, /* Device type number is B97 , */ \ + { 0x420, \ + "ctrl_rcv" }, /* Enable Receiver Mode , */ \ + { 0x431, \ + "chan_sel" }, /* Channel Selection TDM input for Coolflux , */ \ + { 0x450, \ + "input_level" }, /* Input level selection control , */ \ + { 0x461, \ + "vamp_sel" }, /* Input selection for amplifier , */ \ + { 0x4c3, \ + "audio_fs" }, /* Audio sample rate setting , */ \ + { 0x501, \ + "vbat_prot_attacktime" }, /* Protection Attack Time , */ \ + { 0x523, \ + "vbat_prot_thlevel" }, /* ProtectionThreshold , */ \ + { 0x561, \ + "vbat_prot_max_reduct" }, /* Protection Maximum Reduction , */ \ + { 0x582, \ + "vbat_prot_release_t" }, /* Battery Protection Release Time , */ \ + { 0x5b1, \ + "vbat_prot_hysterese" }, /* Battery Protection Hysteresis , */ \ + { 0x5d0, \ + "reset_min_vbat" }, /* reset clipper , */ \ + { 0x5e0, \ + "sel_vbat" }, /* battery voltage for I2C read out only , */ \ + { 0x5f0, \ + "bypass_clipper" }, /* bypass clipper battery protection , */ \ + { 0x600, \ + "dpsa" }, /* Enable dynamic powerstage activation , */ \ + { 0x650, \ + "cf_mute" }, /* Soft mute in CoolFlux , */ \ + { 0x670, \ + "batsense_steepness" }, /* BatSenseSteepness , */ \ + { 0x687, \ + "vol" }, /* volume control (in CoolFlux) , */ \ + { 0x702, \ + "boost_volt" }, /* Boost Voltage , */ \ + { 0x733, \ + "boost_cur" }, /* Max boost coil current - step of 175 mA , */ \ + { 0x7a0, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x7b0, \ + "boost_speed" }, /* Soft RampUp/Down mode for DCDC controller , */ \ + { 0x7c0, \ + "boost_peak2avg" }, /* ctrl_peak2avg for analog part of DCDC , */ \ + { 0x800, \ + "ext_temp_sel" }, /* Select external temperature also the ext_temp will be put on the temp read out , */ \ + { 0x818, \ + "ext_temp" }, /* external temperature setting to be given by host , */ \ + { 0x8b2, \ + "dcdc_synchronisation" }, /* DCDC synchronisation off + 7 positions , */ \ + { 0x900, \ + "powerdown" }, /* Device Mode , */ \ + { 0x910, \ + "reset" }, /* I2C Reset , */ \ + { 0x920, \ + "enbl_coolflux" }, /* Enable CoolFlux , */ \ + { 0x930, \ + "enbl_amplifier" }, /* Enable Amplifier , */ \ + { 0x940, \ + "enbl_boost" }, /* EnableBoost , */ \ + { 0x950, \ + "coolflux_configured" }, /* Coolflux configured , */ \ + { 0x960, \ + "sel_enbl_amplifier" }, /* Selection on how Amplifier is enabled , */ \ + { 0x970, \ + "dcdcoff_mode" }, /* DCDC not connected , */ \ + { 0x980, \ + "iddqtest" }, /* IDDQ test amplifier , */ \ + { 0x991, \ + "coil_value" }, /* Coil Value , */ \ + { 0x9b0, \ + "sel_cf_clock" }, /* Selection CoolFlux Clock , */ \ + { 0x9c1, \ + "int_pad_io" }, /* INT pad configuration control , */ \ + { 0x9e0, \ + "sel_fs_bck" }, /* PLL input reference clock selection , */ \ + { 0x9f0, \ + "sel_scl_cf_clock" }, /* Coolflux sub-system clock , */ \ + { 0xb07, \ + "mtpkey2" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0xc00, \ + "enbl_volt_sense" }, /* Voltage sense enabling control bit , */ \ + { 0xc10, \ + "vsense_pwm_sel" }, /* Voltage sense PWM source selection control , */ \ + { 0xc25, \ + "vi_frac_delay" }, /* Fractional delay adjustment between current and voltage sense, */ \ + { 0xc80, \ + "sel_voltsense_out" }, /* TDM output data selection control , */ \ + { 0xc90, \ + "vsense_bypass_avg" }, /* Voltage Sense Average Block Bypass , */ \ + { 0xd05, \ + "cf_frac_delay" }, /* Fractional delay adjustment between current and voltage sense by firmware, */ \ + { 0xe00, \ + "bypass_dcdc_curr_prot" }, /* Control to switch off dcdc current reduction with bat protection, */ \ + { 0xe80, \ + "disable_clock_sh_prot" }, /* disable clock_sh protection , */ \ + { 0xe96, \ + "reserve_reg_1_15_9" }, /* , */ \ + { 0x1011, \ + "tdm_usecase" }, /* TDM_usecase , */ \ + { 0x1030, \ + "tdm_enable" }, /* TDM interface control , */ \ + { 0x1040, \ + "tdm_clk_inversion" }, /* TDM clock inversion , */ \ + { 0x1053, \ + "tdm_fs_ws_length" }, /* TDM FS length , */ \ + { 0x1090, \ + "tdm_fs_ws_polarity" }, /* TDM FS polarity , */ \ + { 0x10a4, \ + "tdm_sample_size" }, /* TDM Sample Size for all tdm sinks/sources , */ \ + { 0x1103, \ + "tdm_nb_of_slots" }, /* Number of slots , */ \ + { 0x1144, \ + "tdm_slot_length" }, /* Slot length , */ \ + { 0x1194, \ + "tdm_bits_remaining" }, /* Bits remaining , */ \ + { 0x11e0, \ + "tdm_data_delay" }, /* Data delay , */ \ + { 0x11f0, \ + "tdm_data_adjustment" }, /* Data adjustment , */ \ + { 0x1201, \ + "tdm_txdata_format" }, /* TXDATA format , */ \ + { 0x1221, \ + "tdm_txdata_format_unused_slot_sd0" }, /* TXDATA format unused slot sd0 , */ \ + { 0x1241, \ + "tdm_txdata_format_unused_slot_sd1" }, /* TXDATA format unused slot sd1 , */ \ + { 0x1270, \ + "tdm_sink0_enable" }, /* TDM sink0 enable , */ \ + { 0x1280, \ + "tdm_sink1_enable" }, /* TDM sink1 enable , */ \ + { 0x1290, \ + "tdm_sink2_enable" }, /* TDM sink2 enable , */ \ + { 0x12a0, \ + "tdm_source0_enable" }, /* TDM source0 enable , */ \ + { 0x12b0, \ + "tdm_source1_enable" }, /* TDM source1 enable , */ \ + { 0x12c0, \ + "tdm_source2_enable" }, /* TDM source2 enable , */ \ + { 0x12d0, \ + "tdm_sink0_io" }, /* tdm_sink0_io , */ \ + { 0x12e0, \ + "tdm_sink1_io" }, /* tdm_sink1_io , */ \ + { 0x12f0, \ + "tdm_sink2_io" }, /* tdm_sink2_io , */ \ + { 0x1300, \ + "tdm_source0_io" }, /* tdm_source0_io , */ \ + { 0x1310, \ + "tdm_source1_io" }, /* tdm_source1_io , */ \ + { 0x1320, \ + "tdm_source2_io" }, /* tdm_source2_io , */ \ + { 0x1333, \ + "tdm_sink0_slot" }, /* sink0_slot [GAIN IN] , */ \ + { 0x1373, \ + "tdm_sink1_slot" }, /* sink1_slot [CH1 IN] , */ \ + { 0x13b3, \ + "tdm_sink2_slot" }, /* sink2_slot [CH2 IN] , */ \ + { 0x1403, \ + "tdm_source0_slot" }, /* source0_slot [GAIN OUT] , */ \ + { 0x1443, \ + "tdm_source1_slot" }, /* source1_slot [Voltage Sense] , */ \ + { 0x1483, \ + "tdm_source2_slot" }, /* source2_slot [Current Sense] , */ \ + { 0x14c3, \ + "tdm_nbck" }, /* NBCK , */ \ + { 0x1500, \ + "flag_tdm_lut_error" }, /* TDM LUT error flag , */ \ + { 0x1512, \ + "flag_tdm_status" }, /* TDM interface status bits , */ \ + { 0x1540, \ + "flag_tdm_error" }, /* TDM interface error indicator , */ \ + { 0x2000, \ + "flag_por_int_out" }, /* flag_por_int_out , */ \ + { 0x2010, \ + "flag_pll_lock_int_out" }, /* flag_pll_lock_int_out , */ \ + { 0x2020, \ + "flag_otpok_int_out" }, /* flag_otpok_int_out , */ \ + { 0x2030, \ + "flag_ovpok_int_out" }, /* flag_ovpok_int_out , */ \ + { 0x2040, \ + "flag_uvpok_int_out" }, /* flag_uvpok_int_out , */ \ + { 0x2050, \ + "flag_ocp_alarm_int_out" }, /* flag_ocp_alarm_int_out , */ \ + { 0x2060, \ + "flag_clocks_stable_int_out" }, /* flag_clocks_stable_int_out , */ \ + { 0x2070, \ + "flag_clip_int_out" }, /* flag_clip_int_out , */ \ + { 0x2080, \ + "mtp_busy_int_out" }, /* mtp_busy_int_out , */ \ + { 0x2090, \ + "flag_lost_clk_int_out" }, /* flag_lost_clk_int_out , */ \ + { 0x20a0, \ + "flag_cf_speakererror_int_out" }, /* flag_cf_speakererror_int_out , */ \ + { 0x20b0, \ + "flag_cold_started_int_out" }, /* flag_cold_started_int_out , */ \ + { 0x20c0, \ + "flag_engage_int_out" }, /* flag_engage_int_out , */ \ + { 0x20d0, \ + "flag_watchdog_reset_int_out" }, /* flag_watchdog_reset_int_out , */ \ + { 0x20e0, \ + "flag_enbl_amp_int_out" }, /* flag_enbl_amp_int_out , */ \ + { 0x20f0, \ + "flag_enbl_ref_int_out" }, /* flag_enbl_ref_int_out , */ \ + { 0x2100, \ + "flag_voutcomp_int_out" }, /* flag_voutcomp_int_out , */ \ + { 0x2110, \ + "flag_voutcomp93_int_out" }, /* flag_voutcomp93_int_out , */ \ + { 0x2120, \ + "flag_voutcomp86_int_out" }, /* flag_voutcomp86_int_out , */ \ + { 0x2130, \ + "flag_hiz_int_out" }, /* flag_hiz_int_out , */ \ + { 0x2140, \ + "flag_ocpokbst_int_out" }, /* flag_ocpokbst_int_out , */ \ + { 0x2150, \ + "flag_peakcur_int_out" }, /* flag_peakcur_int_out , */ \ + { 0x2160, \ + "flag_ocpokap_int_out" }, /* flag_ocpokap_int_out , */ \ + { 0x2170, \ + "flag_ocpokan_int_out" }, /* flag_ocpokan_int_out , */ \ + { 0x2180, \ + "flag_ocpokbp_int_out" }, /* flag_ocpokbp_int_out , */ \ + { 0x2190, \ + "flag_ocpokbn_int_out" }, /* flag_ocpokbn_int_out , */ \ + { 0x21a0, \ + "flag_adc10_ready_int_out" }, /* flag_adc10_ready_int_out , */ \ + { 0x21b0, \ + "flag_clipa_high_int_out" }, /* flag_clipa_high_int_out , */ \ + { 0x21c0, \ + "flag_clipa_low_int_out" }, /* flag_clipa_low_int_out , */ \ + { 0x21d0, \ + "flag_clipb_high_int_out" }, /* flag_clipb_high_int_out , */ \ + { 0x21e0, \ + "flag_clipb_low_int_out" }, /* flag_clipb_low_int_out , */ \ + { 0x21f0, \ + "flag_tdm_error_int_out" }, /* flag_tdm_error_int_out , */ \ + { 0x2201, \ + "interrupt_out3" }, /* Interrupt status register output - Corresponding flag, */ \ + { 0x2300, \ + "flag_por_int_in" }, /* flag_por_int_in , */ \ + { 0x2310, \ + "flag_pll_lock_int_in" }, /* flag_pll_lock_int_in , */ \ + { 0x2320, \ + "flag_otpok_int_in" }, /* flag_otpok_int_in , */ \ + { 0x2330, \ + "flag_ovpok_int_in" }, /* flag_ovpok_int_in , */ \ + { 0x2340, \ + "flag_uvpok_int_in" }, /* flag_uvpok_int_in , */ \ + { 0x2350, \ + "flag_ocp_alarm_int_in" }, /* flag_ocp_alarm_int_in , */ \ + { 0x2360, \ + "flag_clocks_stable_int_in" }, /* flag_clocks_stable_int_in , */ \ + { 0x2370, \ + "flag_clip_int_in" }, /* flag_clip_int_in , */ \ + { 0x2380, \ + "mtp_busy_int_in" }, /* mtp_busy_int_in , */ \ + { 0x2390, \ + "flag_lost_clk_int_in" }, /* flag_lost_clk_int_in , */ \ + { 0x23a0, \ + "flag_cf_speakererror_int_in" }, /* flag_cf_speakererror_int_in , */ \ + { 0x23b0, \ + "flag_cold_started_int_in" }, /* flag_cold_started_int_in , */ \ + { 0x23c0, \ + "flag_engage_int_in" }, /* flag_engage_int_in , */ \ + { 0x23d0, \ + "flag_watchdog_reset_int_in" }, /* flag_watchdog_reset_int_in , */ \ + { 0x23e0, \ + "flag_enbl_amp_int_in" }, /* flag_enbl_amp_int_in , */ \ + { 0x23f0, \ + "flag_enbl_ref_int_in" }, /* flag_enbl_ref_int_in , */ \ + { 0x2400, \ + "flag_voutcomp_int_in" }, /* flag_voutcomp_int_in , */ \ + { 0x2410, \ + "flag_voutcomp93_int_in" }, /* flag_voutcomp93_int_in , */ \ + { 0x2420, \ + "flag_voutcomp86_int_in" }, /* flag_voutcomp86_int_in , */ \ + { 0x2430, \ + "flag_hiz_int_in" }, /* flag_hiz_int_in , */ \ + { 0x2440, \ + "flag_ocpokbst_int_in" }, /* flag_ocpokbst_int_in , */ \ + { 0x2450, \ + "flag_peakcur_int_in" }, /* flag_peakcur_int_in , */ \ + { 0x2460, \ + "flag_ocpokap_int_in" }, /* flag_ocpokap_int_in , */ \ + { 0x2470, \ + "flag_ocpokan_int_in" }, /* flag_ocpokan_int_in , */ \ + { 0x2480, \ + "flag_ocpokbp_int_in" }, /* flag_ocpokbp_int_in , */ \ + { 0x2490, \ + "flag_ocpokbn_int_in" }, /* flag_ocpokbn_int_in , */ \ + { 0x24a0, \ + "flag_adc10_ready_int_in" }, /* flag_adc10_ready_int_in , */ \ + { 0x24b0, \ + "flag_clipa_high_int_in" }, /* flag_clipa_high_int_in , */ \ + { 0x24c0, \ + "flag_clipa_low_int_in" }, /* flag_clipa_low_int_in , */ \ + { 0x24d0, \ + "flag_clipb_high_int_in" }, /* flag_clipb_high_int_in , */ \ + { 0x24e0, \ + "flag_clipb_low_int_in" }, /* flag_clipb_low_int_in , */ \ + { 0x24f0, \ + "flag_tdm_error_int_in" }, /* flag_tdm_error_int_in , */ \ + { 0x2501, \ + "interrupt_in3" }, /* Interrupt register input , */ \ + { 0x2600, \ + "flag_por_int_enable" }, /* flag_por_int_enable , */ \ + { 0x2610, \ + "flag_pll_lock_int_enable" }, /* flag_pll_lock_int_enable , */ \ + { 0x2620, \ + "flag_otpok_int_enable" }, /* flag_otpok_int_enable , */ \ + { 0x2630, \ + "flag_ovpok_int_enable" }, /* flag_ovpok_int_enable , */ \ + { 0x2640, \ + "flag_uvpok_int_enable" }, /* flag_uvpok_int_enable , */ \ + { 0x2650, \ + "flag_ocp_alarm_int_enable" }, /* flag_ocp_alarm_int_enable , */ \ + { 0x2660, \ + "flag_clocks_stable_int_enable" }, /* flag_clocks_stable_int_enable , */ \ + { 0x2670, \ + "flag_clip_int_enable" }, /* flag_clip_int_enable , */ \ + { 0x2680, \ + "mtp_busy_int_enable" }, /* mtp_busy_int_enable , */ \ + { 0x2690, \ + "flag_lost_clk_int_enable" }, /* flag_lost_clk_int_enable , */ \ + { 0x26a0, \ + "flag_cf_speakererror_int_enable" }, /* flag_cf_speakererror_int_enable , */ \ + { 0x26b0, \ + "flag_cold_started_int_enable" }, /* flag_cold_started_int_enable , */ \ + { 0x26c0, \ + "flag_engage_int_enable" }, /* flag_engage_int_enable , */ \ + { 0x26d0, \ + "flag_watchdog_reset_int_enable" }, /* flag_watchdog_reset_int_enable , */ \ + { 0x26e0, \ + "flag_enbl_amp_int_enable" }, /* flag_enbl_amp_int_enable , */ \ + { 0x26f0, \ + "flag_enbl_ref_int_enable" }, /* flag_enbl_ref_int_enable , */ \ + { 0x2700, \ + "flag_voutcomp_int_enable" }, /* flag_voutcomp_int_enable , */ \ + { 0x2710, \ + "flag_voutcomp93_int_enable" }, /* flag_voutcomp93_int_enable , */ \ + { 0x2720, \ + "flag_voutcomp86_int_enable" }, /* flag_voutcomp86_int_enable , */ \ + { 0x2730, \ + "flag_hiz_int_enable" }, /* flag_hiz_int_enable , */ \ + { 0x2740, \ + "flag_ocpokbst_int_enable" }, /* flag_ocpokbst_int_enable , */ \ + { 0x2750, \ + "flag_peakcur_int_enable" }, /* flag_peakcur_int_enable , */ \ + { 0x2760, \ + "flag_ocpokap_int_enable" }, /* flag_ocpokap_int_enable , */ \ + { 0x2770, \ + "flag_ocpokan_int_enable" }, /* flag_ocpokan_int_enable , */ \ + { 0x2780, \ + "flag_ocpokbp_int_enable" }, /* flag_ocpokbp_int_enable , */ \ + { 0x2790, \ + "flag_ocpokbn_int_enable" }, /* flag_ocpokbn_int_enable , */ \ + { 0x27a0, \ + "flag_adc10_ready_int_enable" }, /* flag_adc10_ready_int_enable , */ \ + { 0x27b0, \ + "flag_clipa_high_int_enable" }, /* flag_clipa_high_int_enable , */ \ + { 0x27c0, \ + "flag_clipa_low_int_enable" }, /* flag_clipa_low_int_enable , */ \ + { 0x27d0, \ + "flag_clipb_high_int_enable" }, /* flag_clipb_high_int_enable , */ \ + { 0x27e0, \ + "flag_clipb_low_int_enable" }, /* flag_clipb_low_int_enable , */ \ + { 0x27f0, \ + "flag_tdm_error_int_enable" }, /* flag_tdm_error_int_enable , */ \ + { 0x2801, \ + "interrupt_enable3" }, /* Interrupt enable register , */ \ + { 0x2900, \ + "flag_por_int_pol" }, /* flag_por_int_pol , */ \ + { 0x2910, \ + "flag_pll_lock_int_pol" }, /* flag_pll_lock_int_pol , */ \ + { 0x2920, \ + "flag_otpok_int_pol" }, /* flag_otpok_int_pol , */ \ + { 0x2930, \ + "flag_ovpok_int_pol" }, /* flag_ovpok_int_pol , */ \ + { 0x2940, \ + "flag_uvpok_int_pol" }, /* flag_uvpok_int_pol , */ \ + { 0x2950, \ + "flag_ocp_alarm_int_pol" }, /* flag_ocp_alarm_int_pol , */ \ + { 0x2960, \ + "flag_clocks_stable_int_pol" }, /* flag_clocks_stable_int_pol , */ \ + { 0x2970, \ + "flag_clip_int_pol" }, /* flag_clip_int_pol , */ \ + { 0x2980, \ + "mtp_busy_int_pol" }, /* mtp_busy_int_pol , */ \ + { 0x2990, \ + "flag_lost_clk_int_pol" }, /* flag_lost_clk_int_pol , */ \ + { 0x29a0, \ + "flag_cf_speakererror_int_pol" }, /* flag_cf_speakererror_int_pol , */ \ + { 0x29b0, \ + "flag_cold_started_int_pol" }, /* flag_cold_started_int_pol , */ \ + { 0x29c0, \ + "flag_engage_int_pol" }, /* flag_engage_int_pol , */ \ + { 0x29d0, \ + "flag_watchdog_reset_int_pol" }, /* flag_watchdog_reset_int_pol , */ \ + { 0x29e0, \ + "flag_enbl_amp_int_pol" }, /* flag_enbl_amp_int_pol , */ \ + { 0x29f0, \ + "flag_enbl_ref_int_pol" }, /* flag_enbl_ref_int_pol , */ \ + { 0x2a00, \ + "flag_voutcomp_int_pol" }, /* flag_voutcomp_int_pol , */ \ + { 0x2a10, \ + "flag_voutcomp93_int_pol" }, /* flag_voutcomp93_int_pol , */ \ + { 0x2a20, \ + "flag_voutcomp86_int_pol" }, /* flag_voutcomp86_int_pol , */ \ + { 0x2a30, \ + "flag_hiz_int_pol" }, /* flag_hiz_int_pol , */ \ + { 0x2a40, \ + "flag_ocpokbst_int_pol" }, /* flag_ocpokbst_int_pol , */ \ + { 0x2a50, \ + "flag_peakcur_int_pol" }, /* flag_peakcur_int_pol , */ \ + { 0x2a60, \ + "flag_ocpokap_int_pol" }, /* flag_ocpokap_int_pol , */ \ + { 0x2a70, \ + "flag_ocpokan_int_pol" }, /* flag_ocpokan_int_pol , */ \ + { 0x2a80, \ + "flag_ocpokbp_int_pol" }, /* flag_ocpokbp_int_pol , */ \ + { 0x2a90, \ + "flag_ocpokbn_int_pol" }, /* flag_ocpokbn_int_pol , */ \ + { 0x2aa0, \ + "flag_adc10_ready_int_pol" }, /* flag_adc10_ready_int_pol , */ \ + { 0x2ab0, \ + "flag_clipa_high_int_pol" }, /* flag_clipa_high_int_pol , */ \ + { 0x2ac0, \ + "flag_clipa_low_int_pol" }, /* flag_clipa_low_int_pol , */ \ + { 0x2ad0, \ + "flag_clipb_high_int_pol" }, /* flag_clipb_high_int_pol , */ \ + { 0x2ae0, \ + "flag_clipb_low_int_pol" }, /* flag_clipb_low_int_pol , */ \ + { 0x2af0, \ + "flag_tdm_error_int_pol" }, /* flag_tdm_error_int_pol , */ \ + { 0x2b01, \ + "status_polarity3" }, /* Interrupt status flags polarity register , */ \ + { 0x3000, \ + "flag_voutcomp" }, /* flag_voutcomp, indication Vset is larger than Vbat, */ \ + { 0x3010, \ + "flag_voutcomp93" }, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat, */ \ + { 0x3020, \ + "flag_voutcomp86" }, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat, */ \ + { 0x3030, \ + "flag_hiz" }, /* flag_hiz, indication Vbst is larger than Vbat , */ \ + { 0x3040, \ + "flag_ocpokbst" }, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */ \ + { 0x3050, \ + "flag_peakcur" }, /* flag_peakcur, indication current is max in dcdc converter, */ \ + { 0x3060, \ + "flag_ocpokap" }, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */ \ + { 0x3070, \ + "flag_ocpokan" }, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */ \ + { 0x3080, \ + "flag_ocpokbp" }, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */ \ + { 0x3090, \ + "flag_ocpokbn" }, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */ \ + { 0x30a0, \ + "flag_adc10_ready" }, /* flag_adc10_ready, indication adc10 is ready , */ \ + { 0x30b0, \ + "flag_clipa_high" }, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */ \ + { 0x30c0, \ + "flag_clipa_low" }, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */ \ + { 0x30d0, \ + "flag_clipb_high" }, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */ \ + { 0x30e0, \ + "flag_clipb_low" }, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */ \ + { 0x310f, \ + "mtp_man_data_out" }, /* single word read from MTP (manual copy) , */ \ + { 0x3200, \ + "key01_locked" }, /* key01_locked, indication key 1 is locked , */ \ + { 0x3210, \ + "key02_locked" }, /* key02_locked, indication key 2 is locked , */ \ + { 0x3225, \ + "mtp_ecc_tcout" }, /* mtp_ecc_tcout , */ \ + { 0x3280, \ + "mtpctrl_valid_test_rd" }, /* mtp test readout for read , */ \ + { 0x3290, \ + "mtpctrl_valid_test_wr" }, /* mtp test readout for write , */ \ + { 0x32a0, \ + "flag_in_alarm_state" }, /* Alarm state , */ \ + { 0x32b0, \ + "mtp_ecc_err2" }, /* two or more bit errors detected in MTP, can not reconstruct value, */ \ + { 0x32c0, \ + "mtp_ecc_err1" }, /* one bit error detected in MTP, reconstructed value, */ \ + { 0x32d0, \ + "mtp_mtp_hvf" }, /* high voltage ready flag for MTP , */ \ + { 0x32f0, \ + "mtp_zero_check_fail" }, /* zero check failed (tbd) for MTP , */ \ + { 0x3309, \ + "data_adc10_tempbat" }, /* data_adc10_tempbat[9;0], adc 10 data output for testing, */ \ + { 0x400f, \ + "hid_code" }, /* 5A6Bh, 23147d to access registers (Default for engineering), */ \ + { 0x4100, \ + "bypass_hp" }, /* Bypass_High Pass Filter , */ \ + { 0x4110, \ + "hard_mute" }, /* Hard Mute , */ \ + { 0x4120, \ + "soft_mute" }, /* Soft Mute , */ \ + { 0x4134, \ + "pwm_delay" }, /* PWM DelayBits to set the delay , */ \ + { 0x4180, \ + "pwm_shape" }, /* PWM Shape , */ \ + { 0x4190, \ + "pwm_bitlength" }, /* PWM Bitlength in noise shaper , */ \ + { 0x4203, \ + "drive" }, /* Drive bits to select amount of power stage amplifier, */ \ + { 0x4240, \ + "reclock_pwm" }, /* , */ \ + { 0x4250, \ + "reclock_voltsense" }, /* , */ \ + { 0x4281, \ + "dpsalevel" }, /* DPSA Threshold level , */ \ + { 0x42a1, \ + "dpsa_release" }, /* DPSA Release time , */ \ + { 0x42c0, \ + "coincidence" }, /* Prevent simultaneously switching of output stage , */ \ + { 0x42d0, \ + "kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x4306, \ + "drivebst" }, /* Drive bits to select the powertransistor sections boost converter, */ \ + { 0x43a0, \ + "ocptestbst" }, /* Boost OCP. For old ocp (ctrl_reversebst is 0);For new ocp (ctrl_reversebst is 1);, */ \ + { 0x43d0, \ + "test_abistfft_enbl" }, /* FFT coolflux , */ \ + { 0x43f0, \ + "test_bcontrol" }, /* test _bcontrol , */ \ + { 0x4400, \ + "reversebst" }, /* OverCurrent Protection selection of power stage boost converter, */ \ + { 0x4410, \ + "sensetest" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0x4420, \ + "enbl_engagebst" }, /* Enable power stage dcdc controller , */ \ + { 0x4470, \ + "enbl_slopecur" }, /* Enable bit of max-current dac , */ \ + { 0x4480, \ + "enbl_voutcomp" }, /* Enable vout comparators , */ \ + { 0x4490, \ + "enbl_voutcomp93" }, /* Enable vout-93 comparators , */ \ + { 0x44a0, \ + "enbl_voutcomp86" }, /* Enable vout-86 comparators , */ \ + { 0x44b0, \ + "enbl_hizcom" }, /* Enable hiz comparator , */ \ + { 0x44c0, \ + "enbl_peakcur" }, /* Enable peak current , */ \ + { 0x44d0, \ + "bypass_ovpglitch" }, /* Bypass OVP Glitch Filter , */ \ + { 0x44e0, \ + "enbl_windac" }, /* Enable window dac , */ \ + { 0x44f0, \ + "enbl_powerbst" }, /* Enable line of the powerstage , */ \ + { 0x4507, \ + "ocp_thr" }, /* ocp_thr threshold level for OCP , */ \ + { 0x4580, \ + "bypass_glitchfilter" }, /* Bypass glitch filter , */ \ + { 0x4590, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0x45a0, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0x45b0, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0x45c0, \ + "bypass_ocp" }, /* Bypass OCP , */ \ + { 0x45d0, \ + "bypass_ocpcounter" }, /* BypassOCPCounter , */ \ + { 0x45e0, \ + "bypass_lost_clk" }, /* Bypasslost_clk detector , */ \ + { 0x45f0, \ + "vpalarm" }, /* vpalarm (uvp ovp handling) , */ \ + { 0x4600, \ + "bypass_gc" }, /* bypass_gc, bypasses the CS gain correction , */ \ + { 0x4610, \ + "cs_gain_control" }, /* gain control by means of MTP or i2c; 0 is MTP , */ \ + { 0x4627, \ + "cs_gain" }, /* + / - 128 steps in steps of 1/4 percent 2's compliment, */ \ + { 0x46a0, \ + "bypass_lp" }, /* bypass Low-Pass filter in temperature sensor , */ \ + { 0x46b0, \ + "bypass_pwmcounter" }, /* bypass_pwmcounter , */ \ + { 0x46c0, \ + "cs_negfixed" }, /* does not switch to neg , */ \ + { 0x46d2, \ + "cs_neghyst" }, /* switches to neg depending on level , */ \ + { 0x4700, \ + "switch_fb" }, /* switch_fb , */ \ + { 0x4713, \ + "se_hyst" }, /* se_hyst , */ \ + { 0x4754, \ + "se_level" }, /* se_level , */ \ + { 0x47a5, \ + "ktemp" }, /* temperature compensation trimming , */ \ + { 0x4800, \ + "cs_negin" }, /* negin , */ \ + { 0x4810, \ + "cs_sein" }, /* cs_sein , */ \ + { 0x4820, \ + "cs_coincidence" }, /* Coincidence current sense , */ \ + { 0x4830, \ + "iddqtestbst" }, /* for iddq testing in powerstage of boost convertor , */ \ + { 0x4840, \ + "coincidencebst" }, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */ \ + { 0x4876, \ + "delay_se_neg" }, /* delay of se and neg , */ \ + { 0x48e1, \ + "cs_ttrack" }, /* sample & hold track time , */ \ + { 0x4900, \ + "bypass_clip" }, /* Bypass clip control , */ \ + { 0x4920, \ + "cf_cgate_off" }, /* to disable clock gating in the coolflux , */ \ + { 0x4940, \ + "clipfast" }, /* clock switch for battery protection clipper, it switches back to old frequency, */ \ + { 0x4950, \ + "cs_8ohm" }, /* 8 ohm mode for current sense (gain mode) , */ \ + { 0x4974, \ + "delay_clock_sh" }, /* delay_sh, tunes S7H delay , */ \ + { 0x49c0, \ + "inv_clksh" }, /* Invert the sample/hold clock for current sense ADC, */ \ + { 0x49d0, \ + "inv_neg" }, /* Invert neg signal , */ \ + { 0x49e0, \ + "inv_se" }, /* Invert se signal , */ \ + { 0x49f0, \ + "setse" }, /* switches between Single Ende and differential mode; 1 is single ended, */ \ + { 0x4a12, \ + "adc10_sel" }, /* select the input to convert the 10b ADC , */ \ + { 0x4a60, \ + "adc10_reset" }, /* Global asynchronous reset (active HIGH) 10 bit ADC, */ \ + { 0x4a81, \ + "adc10_test" }, /* Test mode selection signal 10 bit ADC , */ \ + { 0x4aa0, \ + "bypass_lp_vbat" }, /* lp filter in batt sensor , */ \ + { 0x4ae0, \ + "dc_offset" }, /* switch offset control on/off, is decimator offset control, */ \ + { 0x4af0, \ + "tsense_hibias" }, /* bit to set the biasing in temp sensor to high , */ \ + { 0x4b00, \ + "adc13_iset" }, /* Micadc Setting of current consumption. Debug use only, */ \ + { 0x4b14, \ + "adc13_gain" }, /* Micadc gain setting (2-compl) , */ \ + { 0x4b61, \ + "adc13_slowdel" }, /* Micadc Delay setting for internal clock. Debug use only, */ \ + { 0x4b83, \ + "adc13_offset" }, /* Micadc ADC offset setting , */ \ + { 0x4bc0, \ + "adc13_bsoinv" }, /* Micadc bit stream output invert mode for test , */ \ + { 0x4bd0, \ + "adc13_resonator_enable" }, /* Micadc Give extra SNR with less stability. Debug use only, */ \ + { 0x4be0, \ + "testmicadc" }, /* Mux at input of MICADC for test purpose , */ \ + { 0x4c0f, \ + "abist_offset" }, /* offset control for ABIST testing , */ \ + { 0x4d05, \ + "windac" }, /* for testing direct control windac , */ \ + { 0x4dc3, \ + "pwm_dcc_cnt" }, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0x4e04, \ + "slopecur" }, /* for testing direct control slopecur , */ \ + { 0x4e50, \ + "ctrl_dem" }, /* dyn element matching control, rest of codes are optional, */ \ + { 0x4ed0, \ + "enbl_pwm_dcc" }, /* to enable direct control of pwm duty cycle , */ \ + { 0x5007, \ + "gain" }, /* Gain setting of the gain multiplier , */ \ + { 0x5081, \ + "sourceb" }, /* Set OUTB to , */ \ + { 0x50a1, \ + "sourcea" }, /* Set OUTA to , */ \ + { 0x50c1, \ + "sourcebst" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0x50e0, \ + "tdm_enable_loopback" }, /* TDM loopback test , */ \ + { 0x5104, \ + "pulselengthbst" }, /* pulse length setting test input for boost converter, */ \ + { 0x5150, \ + "bypasslatchbst" }, /* bypass_latch in boost converter , */ \ + { 0x5160, \ + "invertbst" }, /* invert pwmbst test signal , */ \ + { 0x5174, \ + "pulselength" }, /* pulse length setting test input for amplifier , */ \ + { 0x51c0, \ + "bypasslatch" }, /* bypass_latch in PWM source selection module , */ \ + { 0x51d0, \ + "invertb" }, /* invert pwmb test signal , */ \ + { 0x51e0, \ + "inverta" }, /* invert pwma test signal , */ \ + { 0x51f0, \ + "bypass_ctrlloop" }, /* bypass_ctrlloop bypasses the control loop of the amplifier, */ \ + { 0x5210, \ + "test_rdsona" }, /* tbd for rdson testing , */ \ + { 0x5220, \ + "test_rdsonb" }, /* tbd for rdson testing , */ \ + { 0x5230, \ + "test_rdsonbst" }, /* tbd for rdson testing , */ \ + { 0x5240, \ + "test_cvia" }, /* tbd for rdson testing , */ \ + { 0x5250, \ + "test_cvib" }, /* tbd for rdson testing , */ \ + { 0x5260, \ + "test_cvibst" }, /* tbd for rdson testing , */ \ + { 0x5306, \ + "digimuxa_sel" }, /* DigimuxA input selection control (see Digimux list for details), */ \ + { 0x5376, \ + "digimuxb_sel" }, /* DigimuxB input selection control (see Digimux list for details), */ \ + { 0x5400, \ + "hs_mode" }, /* hs_mode, high speed mode I2C bus , */ \ + { 0x5412, \ + "test_parametric_io" }, /* test_parametric_io for testing pads , */ \ + { 0x5440, \ + "enbl_ringo" }, /* enbl_ringo, for test purpose to check with ringo , */ \ + { 0x5456, \ + "digimuxc_sel" }, /* DigimuxC input selection control (see Digimux list for details), */ \ + { 0x54c0, \ + "dio_ehs" }, /* Slew control for DIO in output mode , */ \ + { 0x54d0, \ + "gainio_ehs" }, /* Slew control for GAINIO in output mode , */ \ + { 0x550d, \ + "enbl_amp" }, /* enbl_amp for testing to enable all analoge blocks in amplifier, */ \ + { 0x5600, \ + "use_direct_ctrls" }, /* use_direct_ctrls, to overrule several functions direct for testing, */ \ + { 0x5610, \ + "rst_datapath" }, /* rst_datapath, datapath reset , */ \ + { 0x5620, \ + "rst_cgu" }, /* rst_cgu, cgu reset , */ \ + { 0x5637, \ + "enbl_ref" }, /* for testing to enable all analoge blocks in references, */ \ + { 0x56b0, \ + "enbl_engage" }, /* Enable output stage amplifier , */ \ + { 0x56c0, \ + "use_direct_clk_ctrl" }, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */ \ + { 0x56d0, \ + "use_direct_pll_ctrl" }, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */ \ + { 0x56e0, \ + "use_direct_ctrls_2" }, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */ \ + { 0x5707, \ + "anamux" }, /* Anamux control , */ \ + { 0x57c0, \ + "ocptest" }, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */ \ + { 0x57e0, \ + "otptest" }, /* otptest, test mode otp amplifier , */ \ + { 0x57f0, \ + "reverse" }, /* 1: Normal mode, slope is controlled , */ \ + { 0x5813, \ + "pll_selr" }, /* pll_selr , */ \ + { 0x5854, \ + "pll_selp" }, /* pll_selp , */ \ + { 0x58a5, \ + "pll_seli" }, /* pll_seli , */ \ + { 0x5950, \ + "pll_mdec_msb" }, /* most significant bits of pll_mdec[16] , */ \ + { 0x5960, \ + "pll_ndec_msb" }, /* most significant bits of pll_ndec[9] , */ \ + { 0x5970, \ + "pll_frm" }, /* pll_frm , */ \ + { 0x5980, \ + "pll_directi" }, /* pll_directi , */ \ + { 0x5990, \ + "pll_directo" }, /* pll_directo , */ \ + { 0x59a0, \ + "enbl_pll" }, /* enbl_pll , */ \ + { 0x59f0, \ + "pll_bypass" }, /* pll_bypass , */ \ + { 0x5a0f, \ + "tsig_freq" }, /* tsig_freq, internal sinus test generator, frequency control, */ \ + { 0x5b02, \ + "tsig_freq_msb" }, /* select internal sinus test generator, frequency control msb bits, */ \ + { 0x5b30, \ + "inject_tsig" }, /* inject_tsig, control bit to switch to internal sinus test generator, */ \ + { 0x5b44, \ + "adc10_prog_sample" }, /* control ADC10 , */ \ + { 0x5c0f, \ + "pll_mdec" }, /* bits 15..0 of pll_mdec[16;0] , */ \ + { 0x5d06, \ + "pll_pdec" }, /* pll_pdec , */ \ + { 0x5d78, \ + "pll_ndec" }, /* bits 8..0 of pll_ndec[9;0] , */ \ + { 0x6007, \ + "mtpkey1" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0x6185, \ + "mtp_ecc_tcin" }, /* Mtp_ecc_tcin , */ \ + { 0x6203, \ + "mtp_man_address_in" }, /* address from I2C regs for writing one word single mtp, */ \ + { 0x6260, \ + "mtp_ecc_eeb" }, /* enable code bit generation (active low!) , */ \ + { 0x6270, \ + "mtp_ecc_ecb" }, /* enable correction signal (active low!) , */ \ + { 0x6280, \ + "man_copy_mtp_to_iic" }, /* start copying single word from mtp to i2cregs_mtp , */ \ + { 0x6290, \ + "man_copy_iic_to_mtp" }, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */ \ + { 0x62a0, \ + "auto_copy_mtp_to_iic" }, /* start copying all the data from mtp to i2cregs_mtp, */ \ + { 0x62b0, \ + "auto_copy_iic_to_mtp" }, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */ \ + { 0x62d2, \ + "mtp_speed_mode" }, /* Speed mode , */ \ + { 0x6340, \ + "mtp_direct_enable" }, /* mtp_direct_enable (key1 protected) , */ \ + { 0x6350, \ + "mtp_direct_wr" }, /* mtp_direct_wr (key1 protected) , */ \ + { 0x6360, \ + "mtp_direct_rd" }, /* mtp_direct_rd (key1 protected) , */ \ + { 0x6370, \ + "mtp_direct_rst" }, /* mtp_direct_rst (key1 protected) , */ \ + { 0x6380, \ + "mtp_direct_ers" }, /* mtp_direct_ers (key1 protected) , */ \ + { 0x6390, \ + "mtp_direct_prg" }, /* mtp_direct_prg (key1 protected) , */ \ + { 0x63a0, \ + "mtp_direct_epp" }, /* mtp_direct_epp (key1 protected) , */ \ + { 0x63b4, \ + "mtp_direct_test" }, /* mtp_direct_test (key1 protected) , */ \ + { 0x640f, \ + "mtp_man_data_in" }, /* single word to be written to MTP (manual copy) , */ \ + { 0x7000, \ + "cf_rst_dsp" }, /* Reset CoolFlux DSP , */ \ + { 0x7011, \ + "cf_dmem" }, /* Target memory for access , */ \ + { 0x7030, \ + "cf_aif" }, /* Autoincrement-flag for memory-address , */ \ + { 0x7040, \ + "cf_int" }, /* Interrupt CoolFlux DSP , */ \ + { 0x7087, \ + "cf_req" }, /* request for access (8 channels) , */ \ + { 0x710f, \ + "cf_madd" }, /* memory-address to be accessed , */ \ + { 0x720f, \ + "cf_mema" }, /* activate memory access (24- or 32-bits data is written/read to/from memory, */ \ + { 0x7307, \ + "cf_err" }, /* Coolflux error flags , */ \ + { 0x7387, \ + "cf_ack" }, /* acknowledge of requests (8 channels) , */ \ + { 0x8000, \ + "calibration_onetime" }, /* Calibration schedule (key2 protected) , */ \ + { 0x8010, \ + "calibr_ron_done" }, /* (key2 protected) , */ \ + { 0x8105, \ + "calibr_vout_offset" }, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */ \ + { 0x8163, \ + "calibr_delta_gain" }, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */ \ + { 0x81a5, \ + "calibr_offs_amp" }, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */ \ + { 0x8207, \ + "calibr_gain_cs" }, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */ \ + { 0x8284, \ + "calibr_temp_offset" }, /* temperature offset 2's compliment (key1 protected), */ \ + { 0x82d2, \ + "calibr_temp_gain" }, /* temperature gain 2's compliment (key1 protected) , */ \ + { 0x830f, \ + "calibr_ron" }, /* Ron resistance of coil (key1 protected) , */ \ + { 0x8505, \ + "type_bits_HW" }, /* Key1_Protected_MTP5 , */ \ + { 0x8601, \ + "type_bits_1_0_SW" }, /* MTP-control SW , */ \ + { 0x8681, \ + "type_bits_8_9_SW" }, /* MTP-control SW , */ \ + { 0x870f, \ + "type_bits2_SW" }, /* MTP-control SW2 , */ \ + { 0x8806, \ + "htol_iic_addr" }, /* 7-bit I2C address to be used during HTOL testing , */ \ + { 0x8870, \ + "htol_iic_addr_en" }, /* HTOL_I2C_Address_Enable , */ \ + { 0x8881, \ + "ctrl_ovp_response" }, /* OVP response control , */ \ + { 0x88a0, \ + "disable_ovp_alarm_state" }, /* OVP alarm state control , */ \ + { 0x88b0, \ + "enbl_stretch_ovp" }, /* OVP alram strech control , */ \ + { 0x88c0, \ + "cf_debug_mode" }, /* Coolflux debug mode , */ \ + { 0x8a0f, \ + "production_data1" }, /* (key1 protected) , */ \ + { 0x8b0f, \ + "production_data2" }, /* (key1 protected) , */ \ + { 0x8c0f, \ + "production_data3" }, /* (key1 protected) , */ \ + { 0x8d0f, \ + "production_data4" }, /* (key1 protected) , */ \ + { 0x8e0f, \ + "production_data5" }, /* (key1 protected) , */ \ + { 0x8f0f, \ + "production_data6" }, /* (key1 protected) , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +enum tfa1_irq { + tfa1_irq_vdds = 0, + tfa1_irq_plls = 1, + tfa1_irq_ds = 2, + tfa1_irq_vds = 3, + tfa1_irq_uvds = 4, + tfa1_irq_cds = 5, + tfa1_irq_clks = 6, + tfa1_irq_clips = 7, + tfa1_irq_mtpb = 8, + tfa1_irq_clk = 9, + tfa1_irq_spks = 10, + tfa1_irq_acs = 11, + tfa1_irq_sws = 12, + tfa1_irq_wds = 13, + tfa1_irq_amps = 14, + tfa1_irq_arefs = 15, + tfa1_irq_ack = 32, + tfa1_irq_max = 33, + tfa1_irq_all = -1 /* all irqs */ +}; + +#define TFA1_IRQ_NAMETABLE \ + static tfaIrqName_t Tfa1IrqNames[] = { \ + { 0, "VDDS" }, { 1, "PLLS" }, { 2, "DS" }, { 3, "VDS" }, \ + { 4, "UVDS" }, { 5, "CDS" }, { 6, "CLKS" }, { 7, "CLIPS" }, \ + { 8, "MTPB" }, { 9, "CLK" }, { 10, "SPKS" }, { 11, "ACS" }, \ + { 12, "SWS" }, { 13, "WDS" }, { 14, "AMPS" }, { 15, "AREFS" }, \ + { 16, "16" }, { 17, "17" }, { 18, "18" }, { 19, "19" }, \ + { 20, "20" }, { 21, "21" }, { 22, "22" }, { 23, "23" }, \ + { 24, "24" }, { 25, "25" }, { 26, "26" }, { 27, "27" }, \ + { 28, "28" }, { 29, "29" }, { 30, "30" }, { 31, "31" }, \ + { 32, "ACK" }, { 33, "33" }, \ + }; diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa2_tfafieldnames_N1C.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa2_tfafieldnames_N1C.h new file mode 100644 index 000000000000..afe0bfcd31d3 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa2_tfafieldnames_N1C.h @@ -0,0 +1,2930 @@ +/** Filename: Tfa98xx_TfaFieldnames.h + * This file was generated automatically on 09/01/15 at 09:40:28. + * Source file: TFA9888_N1C_I2C_regmap_V1.xlsx + */ +#define TFA9888_I2CVERSION 18 +typedef enum nxpTfa2BfEnumList { + TFA2_BF_PWDN = + 0x0000, /*!< Powerdown selection */ + TFA2_BF_I2CR = + 0x0010, /*!< I2C Reset - Auto clear */ + TFA2_BF_CFE = + 0x0020, /*!< Enable CoolFlux */ + TFA2_BF_AMPE = + 0x0030, /*!< Activate Amplifier */ + TFA2_BF_DCA = + 0x0040, /*!< Activate DC-to-DC converter */ + TFA2_BF_SBSL = + 0x0050, /*!< Coolflux configured */ + TFA2_BF_AMPC = + 0x0060, /*!< CoolFlux controls amplifier */ + TFA2_BF_INTP = + 0x0071, /*!< Interrupt config */ + TFA2_BF_FSSSEL = + 0x0091, /*!< Audio sample reference */ + TFA2_BF_BYPOCP = + 0x00b0, /*!< Bypass OCP */ + TFA2_BF_TSTOCP = + 0x00c0, /*!< OCP testing control */ + TFA2_BF_AMPINSEL = + 0x0101, /*!< Amplifier input selection */ + TFA2_BF_MANSCONF = + 0x0120, /*!< I2C configured */ + TFA2_BF_MANCOLD = + 0x0130, /*!< Execute cold start */ + TFA2_BF_MANAOOSC = + 0x0140, /*!< Internal osc off at PWDN */ + TFA2_BF_MANROBOD = + 0x0150, /*!< Reaction on BOD */ + TFA2_BF_BODE = + 0x0160, /*!< BOD Enable */ + TFA2_BF_BODHYS = + 0x0170, /*!< BOD Hysteresis */ + TFA2_BF_BODFILT = + 0x0181, /*!< BOD filter */ + TFA2_BF_BODTHLVL = + 0x01a1, /*!< BOD threshold */ + TFA2_BF_MUTETO = + 0x01d0, /*!< Time out SB mute sequence */ + TFA2_BF_RCVNS = + 0x01e0, /*!< Noise shaper selection */ + TFA2_BF_MANWDE = + 0x01f0, /*!< Watchdog manager reaction */ + TFA2_BF_AUDFS = + 0x0203, /*!< Sample rate (fs) */ + TFA2_BF_INPLEV = + 0x0240, /*!< TDM output attenuation */ + TFA2_BF_FRACTDEL = + 0x0255, /*!< V/I Fractional delay */ + TFA2_BF_BYPHVBF = + 0x02b0, /*!< Bypass HVBAT filter */ + TFA2_BF_LDOBYP = + 0x02c0, /*!< Receiver LDO bypass */ + TFA2_BF_REV = + 0x030f, /*!< Revision info */ + TFA2_BF_REFCKEXT = + 0x0401, /*!< PLL external ref clock */ + TFA2_BF_REFCKSEL = + 0x0420, /*!< PLL internal ref clock */ + TFA2_BF_SSLEFTE = + 0x0500, /*!< Enable left channel */ + TFA2_BF_SSRIGHTE = + 0x0510, /*!< Enable right channel */ + TFA2_BF_VSLEFTE = + 0x0520, /*!< Voltage sense left */ + TFA2_BF_VSRIGHTE = + 0x0530, /*!< Voltage sense right */ + TFA2_BF_CSLEFTE = + 0x0540, /*!< Current sense left */ + TFA2_BF_CSRIGHTE = + 0x0550, /*!< Current sense right */ + TFA2_BF_SSPDME = + 0x0560, /*!< Sub-system PDM */ + TFA2_BF_STGAIN = + 0x0d18, /*!< Side tone gain */ + TFA2_BF_PDMSMUTE = + 0x0da0, /*!< Side tone soft mute */ + TFA2_BF_SWVSTEP = + 0x0e06, /*!< Register for the host SW to record the current active vstep */ + TFA2_BF_VDDS = + 0x1000, /*!< POR */ + TFA2_BF_PLLS = + 0x1010, /*!< PLL lock */ + TFA2_BF_OTDS = + 0x1020, /*!< OTP alarm */ + TFA2_BF_OVDS = + 0x1030, /*!< OVP alarm */ + TFA2_BF_UVDS = + 0x1040, /*!< UVP alarm */ + TFA2_BF_CLKS = + 0x1050, /*!< Clocks stable */ + TFA2_BF_MTPB = + 0x1060, /*!< MTP busy */ + TFA2_BF_NOCLK = + 0x1070, /*!< Lost clock */ + TFA2_BF_SPKS = + 0x1080, /*!< Speaker error */ + TFA2_BF_ACS = + 0x1090, /*!< Cold Start */ + TFA2_BF_SWS = + 0x10a0, /*!< Amplifier engage */ + TFA2_BF_WDS = + 0x10b0, /*!< Watchdog */ + TFA2_BF_AMPS = + 0x10c0, /*!< Amplifier enable */ + TFA2_BF_AREFS = + 0x10d0, /*!< References enable */ + TFA2_BF_ADCCR = + 0x10e0, /*!< Control ADC */ + TFA2_BF_BODNOK = + 0x10f0, /*!< BOD */ + TFA2_BF_DCIL = + 0x1100, /*!< DCDC current limiting */ + TFA2_BF_DCDCA = + 0x1110, /*!< DCDC active */ + TFA2_BF_DCOCPOK = + 0x1120, /*!< DCDC OCP nmos */ + TFA2_BF_DCHVBAT = + 0x1140, /*!< DCDC level 1x */ + TFA2_BF_DCH114 = + 0x1150, /*!< DCDC level 1.14x */ + TFA2_BF_DCH107 = + 0x1160, /*!< DCDC level 1.07x */ + TFA2_BF_STMUTEB = + 0x1170, /*!< side tone (un)mute busy */ + TFA2_BF_STMUTE = + 0x1180, /*!< side tone mute state */ + TFA2_BF_TDMLUTER = + 0x1190, /*!< TDM LUT error */ + TFA2_BF_TDMSTAT = + 0x11a2, /*!< TDM status bits */ + TFA2_BF_TDMERR = + 0x11d0, /*!< TDM error */ + TFA2_BF_HAPTIC = + 0x11e0, /*!< Status haptic driver */ + TFA2_BF_OCPOAPL = + 0x1200, /*!< OCPOK pmos A left */ + TFA2_BF_OCPOANL = + 0x1210, /*!< OCPOK nmos A left */ + TFA2_BF_OCPOBPL = + 0x1220, /*!< OCPOK pmos B left */ + TFA2_BF_OCPOBNL = + 0x1230, /*!< OCPOK nmos B left */ + TFA2_BF_CLIPAHL = + 0x1240, /*!< Clipping A left to Vddp */ + TFA2_BF_CLIPALL = + 0x1250, /*!< Clipping A left to gnd */ + TFA2_BF_CLIPBHL = + 0x1260, /*!< Clipping B left to Vddp */ + TFA2_BF_CLIPBLL = + 0x1270, /*!< Clipping B left to gnd */ + TFA2_BF_OCPOAPRC = + 0x1280, /*!< OCPOK pmos A RCV */ + TFA2_BF_OCPOANRC = + 0x1290, /*!< OCPOK nmos A RCV */ + TFA2_BF_OCPOBPRC = + 0x12a0, /*!< OCPOK pmos B RCV */ + TFA2_BF_OCPOBNRC = + 0x12b0, /*!< OCPOK nmos B RCV */ + TFA2_BF_RCVLDOR = + 0x12c0, /*!< RCV LDO regulates */ + TFA2_BF_RCVLDOBR = + 0x12d0, /*!< Receiver LDO ready */ + TFA2_BF_OCDSL = + 0x12e0, /*!< OCP left amplifier */ + TFA2_BF_CLIPSL = + 0x12f0, /*!< Amplifier left clipping */ + TFA2_BF_OCPOAPR = + 0x1300, /*!< OCPOK pmos A right */ + TFA2_BF_OCPOANR = + 0x1310, /*!< OCPOK nmos A right */ + TFA2_BF_OCPOBPR = + 0x1320, /*!< OCPOK pmos B right */ + TFA2_BF_OCPOBNR = + 0x1330, /*!< OCPOK nmos B right */ + TFA2_BF_CLIPAHR = + 0x1340, /*!< Clipping A right to Vddp */ + TFA2_BF_CLIPALR = + 0x1350, /*!< Clipping A right to gnd */ + TFA2_BF_CLIPBHR = + 0x1360, /*!< Clipping B left to Vddp */ + TFA2_BF_CLIPBLR = + 0x1370, /*!< Clipping B right to gnd */ + TFA2_BF_OCDSR = + 0x1380, /*!< OCP right amplifier */ + TFA2_BF_CLIPSR = + 0x1390, /*!< Amplifier right clipping */ + TFA2_BF_OCPOKMC = + 0x13a0, /*!< OCPOK MICVDD */ + TFA2_BF_MANALARM = + 0x13b0, /*!< Alarm state */ + TFA2_BF_MANWAIT1 = + 0x13c0, /*!< Wait HW I2C settings */ + TFA2_BF_MANWAIT2 = + 0x13d0, /*!< Wait CF config */ + TFA2_BF_MANMUTE = + 0x13e0, /*!< Audio mute sequence */ + TFA2_BF_MANOPER = + 0x13f0, /*!< Operating state */ + TFA2_BF_SPKSL = + 0x1400, /*!< Left speaker status */ + TFA2_BF_SPKSR = + 0x1410, /*!< Right speaker status */ + TFA2_BF_CLKOOR = + 0x1420, /*!< External clock status */ + TFA2_BF_MANSTATE = + 0x1433, /*!< Device manager status */ + TFA2_BF_BATS = + 0x1509, /*!< Battery voltage (V) */ + TFA2_BF_TEMPS = + 0x1608, /*!< IC Temperature (C) */ + TFA2_BF_TDMUC = + 0x2003, /*!< Usecase setting */ + TFA2_BF_TDME = + 0x2040, /*!< Enable interface */ + TFA2_BF_TDMMODE = + 0x2050, /*!< Slave/master */ + TFA2_BF_TDMCLINV = + 0x2060, /*!< Reception data to BCK clock */ + TFA2_BF_TDMFSLN = + 0x2073, /*!< FS length (master mode only) */ + TFA2_BF_TDMFSPOL = + 0x20b0, /*!< FS polarity */ + TFA2_BF_TDMNBCK = + 0x20c3, /*!< N-BCK's in FS */ + TFA2_BF_TDMSLOTS = + 0x2103, /*!< N-slots in Frame */ + TFA2_BF_TDMSLLN = + 0x2144, /*!< N-bits in slot */ + TFA2_BF_TDMBRMG = + 0x2194, /*!< N-bits remaining */ + TFA2_BF_TDMDEL = + 0x21e0, /*!< data delay to FS */ + TFA2_BF_TDMADJ = + 0x21f0, /*!< data adjustment */ + TFA2_BF_TDMOOMP = + 0x2201, /*!< Received audio compression */ + TFA2_BF_TDMSSIZE = + 0x2224, /*!< Sample size per slot */ + TFA2_BF_TDMTXDFO = + 0x2271, /*!< Format unused bits */ + TFA2_BF_TDMTXUS0 = + 0x2291, /*!< Format unused slots GAINIO */ + TFA2_BF_TDMTXUS1 = + 0x22b1, /*!< Format unused slots DIO1 */ + TFA2_BF_TDMTXUS2 = + 0x22d1, /*!< Format unused slots DIO2 */ + TFA2_BF_TDMLE = + 0x2310, /*!< Control audio left */ + TFA2_BF_TDMRE = + 0x2320, /*!< Control audio right */ + TFA2_BF_TDMVSRE = + 0x2340, /*!< Control voltage sense right */ + TFA2_BF_TDMCSRE = + 0x2350, /*!< Control current sense right */ + TFA2_BF_TDMVSLE = + 0x2360, /*!< Voltage sense left control */ + TFA2_BF_TDMCSLE = + 0x2370, /*!< Current sense left control */ + TFA2_BF_TDMCFRE = + 0x2380, /*!< DSP out right control */ + TFA2_BF_TDMCFLE = + 0x2390, /*!< DSP out left control */ + TFA2_BF_TDMCF3E = + 0x23a0, /*!< AEC ref left control */ + TFA2_BF_TDMCF4E = + 0x23b0, /*!< AEC ref right control */ + TFA2_BF_TDMPD1E = + 0x23c0, /*!< PDM 1 control */ + TFA2_BF_TDMPD2E = + 0x23d0, /*!< PDM 2 control */ + TFA2_BF_TDMLIO = + 0x2421, /*!< IO audio left */ + TFA2_BF_TDMRIO = + 0x2441, /*!< IO audio right */ + TFA2_BF_TDMVSRIO = + 0x2481, /*!< IO voltage sense right */ + TFA2_BF_TDMCSRIO = + 0x24a1, /*!< IO current sense right */ + TFA2_BF_TDMVSLIO = + 0x24c1, /*!< IO voltage sense left */ + TFA2_BF_TDMCSLIO = + 0x24e1, /*!< IO current sense left */ + TFA2_BF_TDMCFRIO = + 0x2501, /*!< IO dspout right */ + TFA2_BF_TDMCFLIO = + 0x2521, /*!< IO dspout left */ + TFA2_BF_TDMCF3IO = + 0x2541, /*!< IO AEC ref left control */ + TFA2_BF_TDMCF4IO = + 0x2561, /*!< IO AEC ref right control */ + TFA2_BF_TDMPD1IO = + 0x2581, /*!< IO pdm1 */ + TFA2_BF_TDMPD2IO = + 0x25a1, /*!< IO pdm2 */ + TFA2_BF_TDMLS = + 0x2643, /*!< Position audio left */ + TFA2_BF_TDMRS = + 0x2683, /*!< Position audio right */ + TFA2_BF_TDMVSRS = + 0x2703, /*!< Position voltage sense right */ + TFA2_BF_TDMCSRS = + 0x2743, /*!< Position current sense right */ + TFA2_BF_TDMVSLS = + 0x2783, /*!< Position voltage sense left */ + TFA2_BF_TDMCSLS = + 0x27c3, /*!< Position current sense left */ + TFA2_BF_TDMCFRS = + 0x2803, /*!< Position dspout right */ + TFA2_BF_TDMCFLS = + 0x2843, /*!< Position dspout left */ + TFA2_BF_TDMCF3S = + 0x2883, /*!< Position AEC ref left control */ + TFA2_BF_TDMCF4S = + 0x28c3, /*!< Position AEC ref right control */ + TFA2_BF_TDMPD1S = + 0x2903, /*!< Position pdm1 */ + TFA2_BF_TDMPD2S = + 0x2943, /*!< Position pdm2 */ + TFA2_BF_PDMSM = + 0x3100, /*!< PDM control */ + TFA2_BF_PDMSTSEL = + 0x3111, /*!< Side tone input */ + TFA2_BF_PDMLSEL = + 0x3130, /*!< PDM data selection for left channel during PDM direct mode */ + TFA2_BF_PDMRSEL = + 0x3140, /*!< PDM data selection for right channel during PDM direct mode */ + TFA2_BF_MICVDDE = + 0x3150, /*!< Enable MICVDD */ + TFA2_BF_PDMCLRAT = + 0x3201, /*!< PDM BCK/Fs ratio */ + TFA2_BF_PDMGAIN = + 0x3223, /*!< PDM gain */ + TFA2_BF_PDMOSEL = + 0x3263, /*!< PDM output selection - RE/FE data combination */ + TFA2_BF_SELCFHAPD = + 0x32a0, /*!< Select the source for haptic data output (not for customer) */ + TFA2_BF_HAPTIME = + 0x3307, /*!< Duration (ms) */ + TFA2_BF_HAPLEVEL = + 0x3387, /*!< DC value (FFS) */ + TFA2_BF_GPIODIN = + 0x3403, /*!< Receiving value */ + TFA2_BF_GPIOCTRL = + 0x3500, /*!< GPIO master control over GPIO1/2 ports (not for customer) */ + TFA2_BF_GPIOCONF = + 0x3513, /*!< Configuration */ + TFA2_BF_GPIODOUT = + 0x3553, /*!< Transmitting value */ + TFA2_BF_ISTVDDS = + 0x4000, /*!< Status POR */ + TFA2_BF_ISTPLLS = + 0x4010, /*!< Status PLL lock */ + TFA2_BF_ISTOTDS = + 0x4020, /*!< Status OTP alarm */ + TFA2_BF_ISTOVDS = + 0x4030, /*!< Status OVP alarm */ + TFA2_BF_ISTUVDS = + 0x4040, /*!< Status UVP alarm */ + TFA2_BF_ISTCLKS = + 0x4050, /*!< Status clocks stable */ + TFA2_BF_ISTMTPB = + 0x4060, /*!< Status MTP busy */ + TFA2_BF_ISTNOCLK = + 0x4070, /*!< Status lost clock */ + TFA2_BF_ISTSPKS = + 0x4080, /*!< Status speaker error */ + TFA2_BF_ISTACS = + 0x4090, /*!< Status cold start */ + TFA2_BF_ISTSWS = + 0x40a0, /*!< Status amplifier engage */ + TFA2_BF_ISTWDS = + 0x40b0, /*!< Status watchdog */ + TFA2_BF_ISTAMPS = + 0x40c0, /*!< Status amplifier enable */ + TFA2_BF_ISTAREFS = + 0x40d0, /*!< Status Ref enable */ + TFA2_BF_ISTADCCR = + 0x40e0, /*!< Status Control ADC */ + TFA2_BF_ISTBODNOK = + 0x40f0, /*!< Status BOD */ + TFA2_BF_ISTBSTCU = + 0x4100, /*!< Status DCDC current limiting */ + TFA2_BF_ISTBSTHI = + 0x4110, /*!< Status DCDC active */ + TFA2_BF_ISTBSTOC = + 0x4120, /*!< Status DCDC OCP */ + TFA2_BF_ISTBSTPKCUR = + 0x4130, /*!< Status bst peakcur */ + TFA2_BF_ISTBSTVC = + 0x4140, /*!< Status DCDC level 1x */ + TFA2_BF_ISTBST86 = + 0x4150, /*!< Status DCDC level 1.14x */ + TFA2_BF_ISTBST93 = + 0x4160, /*!< Status DCDC level 1.07x */ + TFA2_BF_ISTRCVLD = + 0x4170, /*!< Status rcvldop ready */ + TFA2_BF_ISTOCPL = + 0x4180, /*!< Status ocp alarm left */ + TFA2_BF_ISTOCPR = + 0x4190, /*!< Status ocp alarm right */ + TFA2_BF_ISTMWSRC = + 0x41a0, /*!< Status Waits HW I2C settings */ + TFA2_BF_ISTMWCFC = + 0x41b0, /*!< Status waits CF config */ + TFA2_BF_ISTMWSMU = + 0x41c0, /*!< Status Audio mute sequence */ + TFA2_BF_ISTCFMER = + 0x41d0, /*!< Status cfma error */ + TFA2_BF_ISTCFMAC = + 0x41e0, /*!< Status cfma ack */ + TFA2_BF_ISTCLKOOR = + 0x41f0, /*!< Status flag_clk_out_of_range */ + TFA2_BF_ISTTDMER = + 0x4200, /*!< Status tdm error */ + TFA2_BF_ISTCLPL = + 0x4210, /*!< Status clip left */ + TFA2_BF_ISTCLPR = + 0x4220, /*!< Status clip right */ + TFA2_BF_ISTOCPM = + 0x4230, /*!< Status mic ocpok */ + TFA2_BF_ICLVDDS = + 0x4400, /*!< Clear POR */ + TFA2_BF_ICLPLLS = + 0x4410, /*!< Clear PLL lock */ + TFA2_BF_ICLOTDS = + 0x4420, /*!< Clear OTP alarm */ + TFA2_BF_ICLOVDS = + 0x4430, /*!< Clear OVP alarm */ + TFA2_BF_ICLUVDS = + 0x4440, /*!< Clear UVP alarm */ + TFA2_BF_ICLCLKS = + 0x4450, /*!< Clear clocks stable */ + TFA2_BF_ICLMTPB = + 0x4460, /*!< Clear mtp busy */ + TFA2_BF_ICLNOCLK = + 0x4470, /*!< Clear lost clk */ + TFA2_BF_ICLSPKS = + 0x4480, /*!< Clear speaker error */ + TFA2_BF_ICLACS = + 0x4490, /*!< Clear cold started */ + TFA2_BF_ICLSWS = + 0x44a0, /*!< Clear amplifier engage */ + TFA2_BF_ICLWDS = + 0x44b0, /*!< Clear watchdog */ + TFA2_BF_ICLAMPS = + 0x44c0, /*!< Clear enbl amp */ + TFA2_BF_ICLAREFS = + 0x44d0, /*!< Clear ref enable */ + TFA2_BF_ICLADCCR = + 0x44e0, /*!< Clear control ADC */ + TFA2_BF_ICLBODNOK = + 0x44f0, /*!< Clear BOD */ + TFA2_BF_ICLBSTCU = + 0x4500, /*!< Clear DCDC current limiting */ + TFA2_BF_ICLBSTHI = + 0x4510, /*!< Clear DCDC active */ + TFA2_BF_ICLBSTOC = + 0x4520, /*!< Clear DCDC OCP */ + TFA2_BF_ICLBSTPC = + 0x4530, /*!< Clear bst peakcur */ + TFA2_BF_ICLBSTVC = + 0x4540, /*!< Clear DCDC level 1x */ + TFA2_BF_ICLBST86 = + 0x4550, /*!< Clear DCDC level 1.14x */ + TFA2_BF_ICLBST93 = + 0x4560, /*!< Clear DCDC level 1.07x */ + TFA2_BF_ICLRCVLD = + 0x4570, /*!< Clear rcvldop ready */ + TFA2_BF_ICLOCPL = + 0x4580, /*!< Clear ocp alarm left */ + TFA2_BF_ICLOCPR = + 0x4590, /*!< Clear ocp alarm right */ + TFA2_BF_ICLMWSRC = + 0x45a0, /*!< Clear wait HW I2C settings */ + TFA2_BF_ICLMWCFC = + 0x45b0, /*!< Clear wait cf config */ + TFA2_BF_ICLMWSMU = + 0x45c0, /*!< Clear audio mute sequence */ + TFA2_BF_ICLCFMER = + 0x45d0, /*!< Clear cfma err */ + TFA2_BF_ICLCFMAC = + 0x45e0, /*!< Clear cfma ack */ + TFA2_BF_ICLCLKOOR = + 0x45f0, /*!< Clear flag_clk_out_of_range */ + TFA2_BF_ICLTDMER = + 0x4600, /*!< Clear tdm error */ + TFA2_BF_ICLCLPL = + 0x4610, /*!< Clear clip left */ + TFA2_BF_ICLCLPR = + 0x4620, /*!< Clear clip right */ + TFA2_BF_ICLOCPM = + 0x4630, /*!< Clear mic ocpok */ + TFA2_BF_IEVDDS = + 0x4800, /*!< Enable por */ + TFA2_BF_IEPLLS = + 0x4810, /*!< Enable pll lock */ + TFA2_BF_IEOTDS = + 0x4820, /*!< Enable OTP alarm */ + TFA2_BF_IEOVDS = + 0x4830, /*!< Enable OVP alarm */ + TFA2_BF_IEUVDS = + 0x4840, /*!< Enable UVP alarm */ + TFA2_BF_IECLKS = + 0x4850, /*!< Enable clocks stable */ + TFA2_BF_IEMTPB = + 0x4860, /*!< Enable mtp busy */ + TFA2_BF_IENOCLK = + 0x4870, /*!< Enable lost clk */ + TFA2_BF_IESPKS = + 0x4880, /*!< Enable speaker error */ + TFA2_BF_IEACS = + 0x4890, /*!< Enable cold started */ + TFA2_BF_IESWS = + 0x48a0, /*!< Enable amplifier engage */ + TFA2_BF_IEWDS = + 0x48b0, /*!< Enable watchdog */ + TFA2_BF_IEAMPS = + 0x48c0, /*!< Enable enbl amp */ + TFA2_BF_IEAREFS = + 0x48d0, /*!< Enable ref enable */ + TFA2_BF_IEADCCR = + 0x48e0, /*!< Enable Control ADC */ + TFA2_BF_IEBODNOK = + 0x48f0, /*!< Enable BOD */ + TFA2_BF_IEBSTCU = + 0x4900, /*!< Enable DCDC current limiting */ + TFA2_BF_IEBSTHI = + 0x4910, /*!< Enable DCDC active */ + TFA2_BF_IEBSTOC = + 0x4920, /*!< Enable DCDC OCP */ + TFA2_BF_IEBSTPC = + 0x4930, /*!< Enable bst peakcur */ + TFA2_BF_IEBSTVC = + 0x4940, /*!< Enable DCDC level 1x */ + TFA2_BF_IEBST86 = + 0x4950, /*!< Enable DCDC level 1.14x */ + TFA2_BF_IEBST93 = + 0x4960, /*!< Enable DCDC level 1.07x */ + TFA2_BF_IERCVLD = + 0x4970, /*!< Enable rcvldop ready */ + TFA2_BF_IEOCPL = + 0x4980, /*!< Enable ocp alarm left */ + TFA2_BF_IEOCPR = + 0x4990, /*!< Enable ocp alarm right */ + TFA2_BF_IEMWSRC = + 0x49a0, /*!< Enable waits HW I2C settings */ + TFA2_BF_IEMWCFC = + 0x49b0, /*!< Enable man wait cf config */ + TFA2_BF_IEMWSMU = + 0x49c0, /*!< Enable man Audio mute sequence */ + TFA2_BF_IECFMER = + 0x49d0, /*!< Enable cfma err */ + TFA2_BF_IECFMAC = + 0x49e0, /*!< Enable cfma ack */ + TFA2_BF_IECLKOOR = + 0x49f0, /*!< Enable flag_clk_out_of_range */ + TFA2_BF_IETDMER = + 0x4a00, /*!< Enable tdm error */ + TFA2_BF_IECLPL = + 0x4a10, /*!< Enable clip left */ + TFA2_BF_IECLPR = + 0x4a20, /*!< Enable clip right */ + TFA2_BF_IEOCPM1 = + 0x4a30, /*!< Enable mic ocpok */ + TFA2_BF_IPOVDDS = + 0x4c00, /*!< Polarity por */ + TFA2_BF_IPOPLLS = + 0x4c10, /*!< Polarity pll lock */ + TFA2_BF_IPOOTDS = + 0x4c20, /*!< Polarity OTP alarm */ + TFA2_BF_IPOOVDS = + 0x4c30, /*!< Polarity OVP alarm */ + TFA2_BF_IPOUVDS = + 0x4c40, /*!< Polarity UVP alarm */ + TFA2_BF_IPOCLKS = + 0x4c50, /*!< Polarity clocks stable */ + TFA2_BF_IPOMTPB = + 0x4c60, /*!< Polarity mtp busy */ + TFA2_BF_IPONOCLK = + 0x4c70, /*!< Polarity lost clk */ + TFA2_BF_IPOSPKS = + 0x4c80, /*!< Polarity speaker error */ + TFA2_BF_IPOACS = + 0x4c90, /*!< Polarity cold started */ + TFA2_BF_IPOSWS = + 0x4ca0, /*!< Polarity amplifier engage */ + TFA2_BF_IPOWDS = + 0x4cb0, /*!< Polarity watchdog */ + TFA2_BF_IPOAMPS = + 0x4cc0, /*!< Polarity enbl amp */ + TFA2_BF_IPOAREFS = + 0x4cd0, /*!< Polarity ref enable */ + TFA2_BF_IPOADCCR = + 0x4ce0, /*!< Polarity Control ADC */ + TFA2_BF_IPOBODNOK = + 0x4cf0, /*!< Polarity BOD */ + TFA2_BF_IPOBSTCU = + 0x4d00, /*!< Polarity DCDC current limiting */ + TFA2_BF_IPOBSTHI = + 0x4d10, /*!< Polarity DCDC active */ + TFA2_BF_IPOBSTOC = + 0x4d20, /*!< Polarity DCDC OCP */ + TFA2_BF_IPOBSTPC = + 0x4d30, /*!< Polarity bst peakcur */ + TFA2_BF_IPOBSTVC = + 0x4d40, /*!< Polarity DCDC level 1x */ + TFA2_BF_IPOBST86 = + 0x4d50, /*!< Polarity DCDC level 1.14x */ + TFA2_BF_IPOBST93 = + 0x4d60, /*!< Polarity DCDC level 1.07x */ + TFA2_BF_IPORCVLD = + 0x4d70, /*!< Polarity rcvldop ready */ + TFA2_BF_IPOOCPL = + 0x4d80, /*!< Polarity ocp alarm left */ + TFA2_BF_IPOOCPR = + 0x4d90, /*!< Polarity ocp alarm right */ + TFA2_BF_IPOMWSRC = + 0x4da0, /*!< Polarity waits HW I2C settings */ + TFA2_BF_IPOMWCFC = + 0x4db0, /*!< Polarity man wait cf config */ + TFA2_BF_IPOMWSMU = + 0x4dc0, /*!< Polarity man audio mute sequence */ + TFA2_BF_IPOCFMER = + 0x4dd0, /*!< Polarity cfma err */ + TFA2_BF_IPOCFMAC = + 0x4de0, /*!< Polarity cfma ack */ + TFA2_BF_IPCLKOOR = + 0x4df0, /*!< Polarity flag_clk_out_of_range */ + TFA2_BF_IPOTDMER = + 0x4e00, /*!< Polarity tdm error */ + TFA2_BF_IPOCLPL = + 0x4e10, /*!< Polarity clip left */ + TFA2_BF_IPOCLPR = + 0x4e20, /*!< Polarity clip right */ + TFA2_BF_IPOOCPM = + 0x4e30, /*!< Polarity mic ocpok */ + TFA2_BF_BSSCR = + 0x5001, /*!< Battery protection attack Time */ + TFA2_BF_BSST = + 0x5023, /*!< Battery protection threshold voltage level */ + TFA2_BF_BSSRL = + 0x5061, /*!< Battery protection maximum reduction */ + TFA2_BF_BSSRR = + 0x5082, /*!< Battery protection release time */ + TFA2_BF_BSSHY = + 0x50b1, /*!< Battery protection hysteresis */ + TFA2_BF_BSSR = + 0x50e0, /*!< Battery voltage read out */ + TFA2_BF_BSSBY = + 0x50f0, /*!< Bypass HW clipper */ + TFA2_BF_BSSS = + 0x5100, /*!< Vbat prot steepness */ + TFA2_BF_INTSMUTE = + 0x5110, /*!< Soft mute HW */ + TFA2_BF_CFSML = + 0x5120, /*!< Soft mute FW left */ + TFA2_BF_CFSMR = + 0x5130, /*!< Soft mute FW right */ + TFA2_BF_HPFBYPL = + 0x5140, /*!< Bypass HPF left */ + TFA2_BF_HPFBYPR = + 0x5150, /*!< Bypass HPF right */ + TFA2_BF_DPSAL = + 0x5160, /*!< Enable DPSA left */ + TFA2_BF_DPSAR = + 0x5170, /*!< Enable DPSA right */ + TFA2_BF_VOL = + 0x5187, /*!< FW volume control for primary audio channel */ + TFA2_BF_HNDSFRCV = + 0x5200, /*!< Selection receiver */ + TFA2_BF_CLIPCTRL = + 0x5222, /*!< Clip control setting */ + TFA2_BF_AMPGAIN = + 0x5257, /*!< Amplifier gain */ + TFA2_BF_SLOPEE = + 0x52d0, /*!< Enables slope control */ + TFA2_BF_SLOPESET = + 0x52e1, /*!< Set slope */ + TFA2_BF_VOLSEC = + 0x5a07, /*!< FW volume control for secondary audio channel */ + TFA2_BF_SWPROFIL = + 0x5a87, /*!< Software profile data */ + TFA2_BF_DCVO = + 0x7002, /*!< Boost voltage */ + TFA2_BF_DCMCC = + 0x7033, /*!< Max coil current */ + TFA2_BF_DCCV = + 0x7071, /*!< Coil Value */ + TFA2_BF_DCIE = + 0x7090, /*!< Adaptive boost mode */ + TFA2_BF_DCSR = + 0x70a0, /*!< Soft ramp up/down */ + TFA2_BF_DCSYNCP = + 0x70b2, /*!< DCDC synchronization off + 7 positions */ + TFA2_BF_DCDIS = + 0x70e0, /*!< DCDC on/off */ + TFA2_BF_RST = + 0x9000, /*!< Reset */ + TFA2_BF_DMEM = + 0x9011, /*!< Target memory */ + TFA2_BF_AIF = + 0x9030, /*!< Auto increment */ + TFA2_BF_CFINT = + 0x9040, /*!< Interrupt - auto clear */ + TFA2_BF_CFCGATE = + 0x9050, /*!< Coolflux clock gating disabling control */ + TFA2_BF_REQ = + 0x9087, /*!< request for access (8 channels) */ + TFA2_BF_REQCMD = + 0x9080, /*!< Firmware event request rpc command */ + TFA2_BF_REQRST = + 0x9090, /*!< Firmware event request reset restart */ + TFA2_BF_REQMIPS = + 0x90a0, /*!< Firmware event request short on mips */ + TFA2_BF_REQMUTED = + 0x90b0, /*!< Firmware event request mute sequence ready */ + TFA2_BF_REQVOL = + 0x90c0, /*!< Firmware event request volume ready */ + TFA2_BF_REQDMG = + 0x90d0, /*!< Firmware event request speaker damage detected */ + TFA2_BF_REQCAL = + 0x90e0, /*!< Firmware event request calibration completed */ + TFA2_BF_REQRSV = + 0x90f0, /*!< Firmware event request reserved */ + TFA2_BF_MADD = + 0x910f, /*!< Memory address */ + TFA2_BF_MEMA = + 0x920f, /*!< Activate memory access */ + TFA2_BF_ERR = + 0x9307, /*!< Error flags */ + TFA2_BF_ACK = + 0x9387, /*!< Acknowledge of requests */ + TFA2_BF_ACKCMD = + 0x9380, /*!< Firmware event acknowledge rpc command */ + TFA2_BF_ACKRST = + 0x9390, /*!< Firmware event acknowledge reset restart */ + TFA2_BF_ACKMIPS = + 0x93a0, /*!< Firmware event acknowledge short on mips */ + TFA2_BF_ACKMUTED = + 0x93b0, /*!< Firmware event acknowledge mute sequence ready */ + TFA2_BF_ACKVOL = + 0x93c0, /*!< Firmware event acknowledge volume ready */ + TFA2_BF_ACKDMG = + 0x93d0, /*!< Firmware event acknowledge speaker damage detected */ + TFA2_BF_ACKCAL = + 0x93e0, /*!< Firmware event acknowledge calibration completed */ + TFA2_BF_ACKRSV = + 0x93f0, /*!< Firmware event acknowledge reserved */ + TFA2_BF_MTPK = + 0xa107, /*!< MTP KEY2 register */ + TFA2_BF_KEY1LOCKED = + 0xa200, /*!< Indicates KEY1 is locked */ + TFA2_BF_KEY2LOCKED = + 0xa210, /*!< Indicates KEY2 is locked */ + TFA2_BF_CIMTP = + 0xa360, /*!< Start copying data from I2C mtp registers to mtp */ + TFA2_BF_MTPRDMSB = + 0xa50f, /*!< MSB word of MTP manual read data */ + TFA2_BF_MTPRDLSB = + 0xa60f, /*!< LSB word of MTP manual read data */ + TFA2_BF_EXTTS = + 0xb108, /*!< External temperature (C) */ + TFA2_BF_TROS = + 0xb190, /*!< Select temp Speaker calibration */ + TFA2_BF_MTPOTC = + 0xf000, /*!< Calibration schedule */ + TFA2_BF_MTPEX = + 0xf010, /*!< Calibration Ron executed */ + TFA2_BF_DCMCCAPI = + 0xf020, /*!< Calibration current limit DCDC */ + TFA2_BF_DCMCCSB = + 0xf030, /*!< Sign bit for delta calibration current limit DCDC */ + TFA2_BF_USERDEF = + 0xf042, /*!< Calibration delta current limit DCDC */ + TFA2_BF_R25CL = + 0xf40f, /*!< Ron resistance of left channel speaker coil */ + TFA2_BF_R25CR = + 0xf50f, /*!< Ron resistance of right channel speaker coil */ +} nxpTfa2BfEnumList_t; +#define TFA2_NAMETABLE \ + static tfaBfName_t Tfa2DatasheetNames[] = { \ + { 0x0, \ + "PWDN" }, /* Powerdown selection , */ \ + { 0x10, \ + "I2CR" }, /* I2C Reset - Auto clear , */ \ + { 0x20, \ + "CFE" }, /* Enable CoolFlux , */ \ + { 0x30, \ + "AMPE" }, /* Activate Amplifier , */ \ + { 0x40, \ + "DCA" }, /* Activate DC-to-DC converter , */ \ + { 0x50, \ + "SBSL" }, /* Coolflux configured , */ \ + { 0x60, \ + "AMPC" }, /* CoolFlux controls amplifier , */ \ + { 0x71, \ + "INTP" }, /* Interrupt config , */ \ + { 0x91, \ + "FSSSEL" }, /* Audio sample reference , */ \ + { 0xb0, \ + "BYPOCP" }, /* Bypass OCP , */ \ + { 0xc0, \ + "TSTOCP" }, /* OCP testing control , */ \ + { 0x101, \ + "AMPINSEL" }, /* Amplifier input selection , */ \ + { 0x120, \ + "MANSCONF" }, /* I2C configured , */ \ + { 0x130, \ + "MANCOLD" }, /* Execute cold start , */ \ + { 0x140, \ + "MANAOOSC" }, /* Internal osc off at PWDN , */ \ + { 0x150, \ + "MANROBOD" }, /* Reaction on BOD , */ \ + { 0x160, \ + "BODE" }, /* BOD Enable , */ \ + { 0x170, \ + "BODHYS" }, /* BOD Hysteresis , */ \ + { 0x181, \ + "BODFILT" }, /* BOD filter , */ \ + { 0x1a1, \ + "BODTHLVL" }, /* BOD threshold , */ \ + { 0x1d0, \ + "MUTETO" }, /* Time out SB mute sequence , */ \ + { 0x1e0, \ + "RCVNS" }, /* Noise shaper selection , */ \ + { 0x1f0, \ + "MANWDE" }, /* Watchdog manager reaction , */ \ + { 0x203, \ + "AUDFS" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "INPLEV" }, /* TDM output attenuation , */ \ + { 0x255, \ + "FRACTDEL" }, /* V/I Fractional delay , */ \ + { 0x2b0, \ + "BYPHVBF" }, /* Bypass HVBAT filter , */ \ + { 0x2c0, \ + "LDOBYP" }, /* Receiver LDO bypass , */ \ + { 0x30f, \ + "REV" }, /* Revision info , */ \ + { 0x401, \ + "REFCKEXT" }, /* PLL external ref clock , */ \ + { 0x420, \ + "REFCKSEL" }, /* PLL internal ref clock , */ \ + { 0x500, \ + "SSLEFTE" }, /* Enable left channel , */ \ + { 0x510, \ + "SSRIGHTE" }, /* Enable right channel , */ \ + { 0x520, \ + "VSLEFTE" }, /* Voltage sense left , */ \ + { 0x530, \ + "VSRIGHTE" }, /* Voltage sense right , */ \ + { 0x540, \ + "CSLEFTE" }, /* Current sense left , */ \ + { 0x550, \ + "CSRIGHTE" }, /* Current sense right , */ \ + { 0x560, \ + "SSPDME" }, /* Sub-system PDM , */ \ + { 0xd18, \ + "STGAIN" }, /* Side tone gain , */ \ + { 0xda0, \ + "PDMSMUTE" }, /* Side tone soft mute , */ \ + { 0xe06, \ + "SWVSTEP" }, /* Register for the host SW to record the current active vstep, */ \ + { 0x1000, \ + "VDDS" }, /* POR , */ \ + { 0x1010, \ + "PLLS" }, /* PLL lock , */ \ + { 0x1020, \ + "OTDS" }, /* OTP alarm , */ \ + { 0x1030, \ + "OVDS" }, /* OVP alarm , */ \ + { 0x1040, \ + "UVDS" }, /* UVP alarm , */ \ + { 0x1050, \ + "CLKS" }, /* Clocks stable , */ \ + { 0x1060, \ + "MTPB" }, /* MTP busy , */ \ + { 0x1070, \ + "NOCLK" }, /* Lost clock , */ \ + { 0x1080, \ + "SPKS" }, /* Speaker error , */ \ + { 0x1090, \ + "ACS" }, /* Cold Start , */ \ + { 0x10a0, \ + "SWS" }, /* Amplifier engage , */ \ + { 0x10b0, \ + "WDS" }, /* Watchdog , */ \ + { 0x10c0, \ + "AMPS" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "AREFS" }, /* References enable , */ \ + { 0x10e0, \ + "ADCCR" }, /* Control ADC , */ \ + { 0x10f0, \ + "BODNOK" }, /* BOD , */ \ + { 0x1100, \ + "DCIL" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "DCDCA" }, /* DCDC active , */ \ + { 0x1120, \ + "DCOCPOK" }, /* DCDC OCP nmos , */ \ + { 0x1140, \ + "DCHVBAT" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "DCH114" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "DCH107" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "STMUTEB" }, /* side tone (un)mute busy , */ \ + { 0x1180, \ + "STMUTE" }, /* side tone mute state , */ \ + { 0x1190, \ + "TDMLUTER" }, /* TDM LUT error , */ \ + { 0x11a2, \ + "TDMSTAT" }, /* TDM status bits , */ \ + { 0x11d0, \ + "TDMERR" }, /* TDM error , */ \ + { 0x11e0, \ + "HAPTIC" }, /* Status haptic driver , */ \ + { 0x1200, \ + "OCPOAPL" }, /* OCPOK pmos A left , */ \ + { 0x1210, \ + "OCPOANL" }, /* OCPOK nmos A left , */ \ + { 0x1220, \ + "OCPOBPL" }, /* OCPOK pmos B left , */ \ + { 0x1230, \ + "OCPOBNL" }, /* OCPOK nmos B left , */ \ + { 0x1240, \ + "CLIPAHL" }, /* Clipping A left to Vddp , */ \ + { 0x1250, \ + "CLIPALL" }, /* Clipping A left to gnd , */ \ + { 0x1260, \ + "CLIPBHL" }, /* Clipping B left to Vddp , */ \ + { 0x1270, \ + "CLIPBLL" }, /* Clipping B left to gnd , */ \ + { 0x1280, \ + "OCPOAPRC" }, /* OCPOK pmos A RCV , */ \ + { 0x1290, \ + "OCPOANRC" }, /* OCPOK nmos A RCV , */ \ + { 0x12a0, \ + "OCPOBPRC" }, /* OCPOK pmos B RCV , */ \ + { 0x12b0, \ + "OCPOBNRC" }, /* OCPOK nmos B RCV , */ \ + { 0x12c0, \ + "RCVLDOR" }, /* RCV LDO regulates , */ \ + { 0x12d0, \ + "RCVLDOBR" }, /* Receiver LDO ready , */ \ + { 0x12e0, \ + "OCDSL" }, /* OCP left amplifier , */ \ + { 0x12f0, \ + "CLIPSL" }, /* Amplifier left clipping , */ \ + { 0x1300, \ + "OCPOAPR" }, /* OCPOK pmos A right , */ \ + { 0x1310, \ + "OCPOANR" }, /* OCPOK nmos A right , */ \ + { 0x1320, \ + "OCPOBPR" }, /* OCPOK pmos B right , */ \ + { 0x1330, \ + "OCPOBNR" }, /* OCPOK nmos B right , */ \ + { 0x1340, \ + "CLIPAHR" }, /* Clipping A right to Vddp , */ \ + { 0x1350, \ + "CLIPALR" }, /* Clipping A right to gnd , */ \ + { 0x1360, \ + "CLIPBHR" }, /* Clipping B left to Vddp , */ \ + { 0x1370, \ + "CLIPBLR" }, /* Clipping B right to gnd , */ \ + { 0x1380, \ + "OCDSR" }, /* OCP right amplifier , */ \ + { 0x1390, \ + "CLIPSR" }, /* Amplifier right clipping , */ \ + { 0x13a0, \ + "OCPOKMC" }, /* OCPOK MICVDD , */ \ + { 0x13b0, \ + "MANALARM" }, /* Alarm state , */ \ + { 0x13c0, \ + "MANWAIT1" }, /* Wait HW I2C settings , */ \ + { 0x13d0, \ + "MANWAIT2" }, /* Wait CF config , */ \ + { 0x13e0, \ + "MANMUTE" }, /* Audio mute sequence , */ \ + { 0x13f0, \ + "MANOPER" }, /* Operating state , */ \ + { 0x1400, \ + "SPKSL" }, /* Left speaker status , */ \ + { 0x1410, \ + "SPKSR" }, /* Right speaker status , */ \ + { 0x1420, \ + "CLKOOR" }, /* External clock status , */ \ + { 0x1433, \ + "MANSTATE" }, /* Device manager status , */ \ + { 0x1509, \ + "BATS" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "TEMPS" }, /* IC Temperature (C) , */ \ + { 0x2003, \ + "TDMUC" }, /* Usecase setting , */ \ + { 0x2040, \ + "TDME" }, /* Enable interface , */ \ + { 0x2050, \ + "TDMMODE" }, /* Slave/master , */ \ + { 0x2060, \ + "TDMCLINV" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "TDMFSLN" }, /* FS length (master mode only) , */ \ + { 0x20b0, \ + "TDMFSPOL" }, /* FS polarity , */ \ + { 0x20c3, \ + "TDMNBCK" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "TDMSLOTS" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "TDMSLLN" }, /* N-bits in slot , */ \ + { 0x2194, \ + "TDMBRMG" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "TDMDEL" }, /* data delay to FS , */ \ + { 0x21f0, \ + "TDMADJ" }, /* data adjustment , */ \ + { 0x2201, \ + "TDMOOMP" }, /* Received audio compression , */ \ + { 0x2224, \ + "TDMSSIZE" }, /* Sample size per slot , */ \ + { 0x2271, \ + "TDMTXDFO" }, /* Format unused bits , */ \ + { 0x2291, \ + "TDMTXUS0" }, /* Format unused slots GAINIO , */ \ + { 0x22b1, \ + "TDMTXUS1" }, /* Format unused slots DIO1 , */ \ + { 0x22d1, \ + "TDMTXUS2" }, /* Format unused slots DIO2 , */ \ + { 0x2310, \ + "TDMLE" }, /* Control audio left , */ \ + { 0x2320, \ + "TDMRE" }, /* Control audio right , */ \ + { 0x2340, \ + "TDMVSRE" }, /* Control voltage sense right , */ \ + { 0x2350, \ + "TDMCSRE" }, /* Control current sense right , */ \ + { 0x2360, \ + "TDMVSLE" }, /* Voltage sense left control , */ \ + { 0x2370, \ + "TDMCSLE" }, /* Current sense left control , */ \ + { 0x2380, \ + "TDMCFRE" }, /* DSP out right control , */ \ + { 0x2390, \ + "TDMCFLE" }, /* DSP out left control , */ \ + { 0x23a0, \ + "TDMCF3E" }, /* AEC ref left control , */ \ + { 0x23b0, \ + "TDMCF4E" }, /* AEC ref right control , */ \ + { 0x23c0, \ + "TDMPD1E" }, /* PDM 1 control , */ \ + { 0x23d0, \ + "TDMPD2E" }, /* PDM 2 control , */ \ + { 0x2421, \ + "TDMLIO" }, /* IO audio left , */ \ + { 0x2441, \ + "TDMRIO" }, /* IO audio right , */ \ + { 0x2481, \ + "TDMVSRIO" }, /* IO voltage sense right , */ \ + { 0x24a1, \ + "TDMCSRIO" }, /* IO current sense right , */ \ + { 0x24c1, \ + "TDMVSLIO" }, /* IO voltage sense left , */ \ + { 0x24e1, \ + "TDMCSLIO" }, /* IO current sense left , */ \ + { 0x2501, \ + "TDMCFRIO" }, /* IO dspout right , */ \ + { 0x2521, \ + "TDMCFLIO" }, /* IO dspout left , */ \ + { 0x2541, \ + "TDMCF3IO" }, /* IO AEC ref left control , */ \ + { 0x2561, \ + "TDMCF4IO" }, /* IO AEC ref right control , */ \ + { 0x2581, \ + "TDMPD1IO" }, /* IO pdm1 , */ \ + { 0x25a1, \ + "TDMPD2IO" }, /* IO pdm2 , */ \ + { 0x2643, \ + "TDMLS" }, /* Position audio left , */ \ + { 0x2683, \ + "TDMRS" }, /* Position audio right , */ \ + { 0x2703, \ + "TDMVSRS" }, /* Position voltage sense right , */ \ + { 0x2743, \ + "TDMCSRS" }, /* Position current sense right , */ \ + { 0x2783, \ + "TDMVSLS" }, /* Position voltage sense left , */ \ + { 0x27c3, \ + "TDMCSLS" }, /* Position current sense left , */ \ + { 0x2803, \ + "TDMCFRS" }, /* Position dspout right , */ \ + { 0x2843, \ + "TDMCFLS" }, /* Position dspout left , */ \ + { 0x2883, \ + "TDMCF3S" }, /* Position AEC ref left control , */ \ + { 0x28c3, \ + "TDMCF4S" }, /* Position AEC ref right control , */ \ + { 0x2903, \ + "TDMPD1S" }, /* Position pdm1 , */ \ + { 0x2943, \ + "TDMPD2S" }, /* Position pdm2 , */ \ + { 0x3100, \ + "PDMSM" }, /* PDM control , */ \ + { 0x3111, \ + "PDMSTSEL" }, /* Side tone input , */ \ + { 0x3130, \ + "PDMLSEL" }, /* PDM data selection for left channel during PDM direct mode, */ \ + { 0x3140, \ + "PDMRSEL" }, /* PDM data selection for right channel during PDM direct mode, */ \ + { 0x3150, \ + "MICVDDE" }, /* Enable MICVDD , */ \ + { 0x3201, \ + "PDMCLRAT" }, /* PDM BCK/Fs ratio , */ \ + { 0x3223, \ + "PDMGAIN" }, /* PDM gain , */ \ + { 0x3263, \ + "PDMOSEL" }, /* PDM output selection - RE/FE data combination , */ \ + { 0x32a0, \ + "SELCFHAPD" }, /* Select the source for haptic data output (not for customer), */ \ + { 0x3307, \ + "HAPTIME" }, /* Duration (ms) , */ \ + { 0x3387, \ + "HAPLEVEL" }, /* DC value (FFS) , */ \ + { 0x3403, \ + "GPIODIN" }, /* Receiving value , */ \ + { 0x3500, \ + "GPIOCTRL" }, /* GPIO master control over GPIO1/2 ports (not for customer), */ \ + { 0x3513, \ + "GPIOCONF" }, /* Configuration , */ \ + { 0x3553, \ + "GPIODOUT" }, /* Transmitting value , */ \ + { 0x4000, \ + "ISTVDDS" }, /* Status POR , */ \ + { 0x4010, \ + "ISTPLLS" }, /* Status PLL lock , */ \ + { 0x4020, \ + "ISTOTDS" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "ISTOVDS" }, /* Status OVP alarm , */ \ + { 0x4040, \ + "ISTUVDS" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "ISTCLKS" }, /* Status clocks stable , */ \ + { 0x4060, \ + "ISTMTPB" }, /* Status MTP busy , */ \ + { 0x4070, \ + "ISTNOCLK" }, /* Status lost clock , */ \ + { 0x4080, \ + "ISTSPKS" }, /* Status speaker error , */ \ + { 0x4090, \ + "ISTACS" }, /* Status cold start , */ \ + { 0x40a0, \ + "ISTSWS" }, /* Status amplifier engage , */ \ + { 0x40b0, \ + "ISTWDS" }, /* Status watchdog , */ \ + { 0x40c0, \ + "ISTAMPS" }, /* Status amplifier enable , */ \ + { 0x40d0, \ + "ISTAREFS" }, /* Status Ref enable , */ \ + { 0x40e0, \ + "ISTADCCR" }, /* Status Control ADC , */ \ + { 0x40f0, \ + "ISTBODNOK" }, /* Status BOD , */ \ + { 0x4100, \ + "ISTBSTCU" }, /* Status DCDC current limiting , */ \ + { 0x4110, \ + "ISTBSTHI" }, /* Status DCDC active , */ \ + { 0x4120, \ + "ISTBSTOC" }, /* Status DCDC OCP , */ \ + { 0x4130, \ + "ISTBSTPKCUR" }, /* Status bst peakcur , */ \ + { 0x4140, \ + "ISTBSTVC" }, /* Status DCDC level 1x , */ \ + { 0x4150, \ + "ISTBST86" }, /* Status DCDC level 1.14x , */ \ + { 0x4160, \ + "ISTBST93" }, /* Status DCDC level 1.07x , */ \ + { 0x4170, \ + "ISTRCVLD" }, /* Status rcvldop ready , */ \ + { 0x4180, \ + "ISTOCPL" }, /* Status ocp alarm left , */ \ + { 0x4190, \ + "ISTOCPR" }, /* Status ocp alarm right , */ \ + { 0x41a0, \ + "ISTMWSRC" }, /* Status Waits HW I2C settings , */ \ + { 0x41b0, \ + "ISTMWCFC" }, /* Status waits CF config , */ \ + { 0x41c0, \ + "ISTMWSMU" }, /* Status Audio mute sequence , */ \ + { 0x41d0, \ + "ISTCFMER" }, /* Status cfma error , */ \ + { 0x41e0, \ + "ISTCFMAC" }, /* Status cfma ack , */ \ + { 0x41f0, \ + "ISTCLKOOR" }, /* Status flag_clk_out_of_range , */ \ + { 0x4200, \ + "ISTTDMER" }, /* Status tdm error , */ \ + { 0x4210, \ + "ISTCLPL" }, /* Status clip left , */ \ + { 0x4220, \ + "ISTCLPR" }, /* Status clip right , */ \ + { 0x4230, \ + "ISTOCPM" }, /* Status mic ocpok , */ \ + { 0x4400, \ + "ICLVDDS" }, /* Clear POR , */ \ + { 0x4410, \ + "ICLPLLS" }, /* Clear PLL lock , */ \ + { 0x4420, \ + "ICLOTDS" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "ICLOVDS" }, /* Clear OVP alarm , */ \ + { 0x4440, \ + "ICLUVDS" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "ICLCLKS" }, /* Clear clocks stable , */ \ + { 0x4460, \ + "ICLMTPB" }, /* Clear mtp busy , */ \ + { 0x4470, \ + "ICLNOCLK" }, /* Clear lost clk , */ \ + { 0x4480, \ + "ICLSPKS" }, /* Clear speaker error , */ \ + { 0x4490, \ + "ICLACS" }, /* Clear cold started , */ \ + { 0x44a0, \ + "ICLSWS" }, /* Clear amplifier engage , */ \ + { 0x44b0, \ + "ICLWDS" }, /* Clear watchdog , */ \ + { 0x44c0, \ + "ICLAMPS" }, /* Clear enbl amp , */ \ + { 0x44d0, \ + "ICLAREFS" }, /* Clear ref enable , */ \ + { 0x44e0, \ + "ICLADCCR" }, /* Clear control ADC , */ \ + { 0x44f0, \ + "ICLBODNOK" }, /* Clear BOD , */ \ + { 0x4500, \ + "ICLBSTCU" }, /* Clear DCDC current limiting , */ \ + { 0x4510, \ + "ICLBSTHI" }, /* Clear DCDC active , */ \ + { 0x4520, \ + "ICLBSTOC" }, /* Clear DCDC OCP , */ \ + { 0x4530, \ + "ICLBSTPC" }, /* Clear bst peakcur , */ \ + { 0x4540, \ + "ICLBSTVC" }, /* Clear DCDC level 1x , */ \ + { 0x4550, \ + "ICLBST86" }, /* Clear DCDC level 1.14x , */ \ + { 0x4560, \ + "ICLBST93" }, /* Clear DCDC level 1.07x , */ \ + { 0x4570, \ + "ICLRCVLD" }, /* Clear rcvldop ready , */ \ + { 0x4580, \ + "ICLOCPL" }, /* Clear ocp alarm left , */ \ + { 0x4590, \ + "ICLOCPR" }, /* Clear ocp alarm right , */ \ + { 0x45a0, \ + "ICLMWSRC" }, /* Clear wait HW I2C settings , */ \ + { 0x45b0, \ + "ICLMWCFC" }, /* Clear wait cf config , */ \ + { 0x45c0, \ + "ICLMWSMU" }, /* Clear audio mute sequence , */ \ + { 0x45d0, \ + "ICLCFMER" }, /* Clear cfma err , */ \ + { 0x45e0, \ + "ICLCFMAC" }, /* Clear cfma ack , */ \ + { 0x45f0, \ + "ICLCLKOOR" }, /* Clear flag_clk_out_of_range , */ \ + { 0x4600, \ + "ICLTDMER" }, /* Clear tdm error , */ \ + { 0x4610, \ + "ICLCLPL" }, /* Clear clip left , */ \ + { 0x4620, \ + "ICLCLPR" }, /* Clear clip right , */ \ + { 0x4630, \ + "ICLOCPM" }, /* Clear mic ocpok , */ \ + { 0x4800, \ + "IEVDDS" }, /* Enable por , */ \ + { 0x4810, \ + "IEPLLS" }, /* Enable pll lock , */ \ + { 0x4820, \ + "IEOTDS" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "IEOVDS" }, /* Enable OVP alarm , */ \ + { 0x4840, \ + "IEUVDS" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "IECLKS" }, /* Enable clocks stable , */ \ + { 0x4860, \ + "IEMTPB" }, /* Enable mtp busy , */ \ + { 0x4870, \ + "IENOCLK" }, /* Enable lost clk , */ \ + { 0x4880, \ + "IESPKS" }, /* Enable speaker error , */ \ + { 0x4890, \ + "IEACS" }, /* Enable cold started , */ \ + { 0x48a0, \ + "IESWS" }, /* Enable amplifier engage , */ \ + { 0x48b0, \ + "IEWDS" }, /* Enable watchdog , */ \ + { 0x48c0, \ + "IEAMPS" }, /* Enable enbl amp , */ \ + { 0x48d0, \ + "IEAREFS" }, /* Enable ref enable , */ \ + { 0x48e0, \ + "IEADCCR" }, /* Enable Control ADC , */ \ + { 0x48f0, \ + "IEBODNOK" }, /* Enable BOD , */ \ + { 0x4900, \ + "IEBSTCU" }, /* Enable DCDC current limiting , */ \ + { 0x4910, \ + "IEBSTHI" }, /* Enable DCDC active , */ \ + { 0x4920, \ + "IEBSTOC" }, /* Enable DCDC OCP , */ \ + { 0x4930, \ + "IEBSTPC" }, /* Enable bst peakcur , */ \ + { 0x4940, \ + "IEBSTVC" }, /* Enable DCDC level 1x , */ \ + { 0x4950, \ + "IEBST86" }, /* Enable DCDC level 1.14x , */ \ + { 0x4960, \ + "IEBST93" }, /* Enable DCDC level 1.07x , */ \ + { 0x4970, \ + "IERCVLD" }, /* Enable rcvldop ready , */ \ + { 0x4980, \ + "IEOCPL" }, /* Enable ocp alarm left , */ \ + { 0x4990, \ + "IEOCPR" }, /* Enable ocp alarm right , */ \ + { 0x49a0, \ + "IEMWSRC" }, /* Enable waits HW I2C settings , */ \ + { 0x49b0, \ + "IEMWCFC" }, /* Enable man wait cf config , */ \ + { 0x49c0, \ + "IEMWSMU" }, /* Enable man Audio mute sequence , */ \ + { 0x49d0, \ + "IECFMER" }, /* Enable cfma err , */ \ + { 0x49e0, \ + "IECFMAC" }, /* Enable cfma ack , */ \ + { 0x49f0, \ + "IECLKOOR" }, /* Enable flag_clk_out_of_range , */ \ + { 0x4a00, \ + "IETDMER" }, /* Enable tdm error , */ \ + { 0x4a10, \ + "IECLPL" }, /* Enable clip left , */ \ + { 0x4a20, \ + "IECLPR" }, /* Enable clip right , */ \ + { 0x4a30, \ + "IEOCPM1" }, /* Enable mic ocpok , */ \ + { 0x4c00, \ + "IPOVDDS" }, /* Polarity por , */ \ + { 0x4c10, \ + "IPOPLLS" }, /* Polarity pll lock , */ \ + { 0x4c20, \ + "IPOOTDS" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "IPOOVDS" }, /* Polarity OVP alarm , */ \ + { 0x4c40, \ + "IPOUVDS" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "IPOCLKS" }, /* Polarity clocks stable , */ \ + { 0x4c60, \ + "IPOMTPB" }, /* Polarity mtp busy , */ \ + { 0x4c70, \ + "IPONOCLK" }, /* Polarity lost clk , */ \ + { 0x4c80, \ + "IPOSPKS" }, /* Polarity speaker error , */ \ + { 0x4c90, \ + "IPOACS" }, /* Polarity cold started , */ \ + { 0x4ca0, \ + "IPOSWS" }, /* Polarity amplifier engage , */ \ + { 0x4cb0, \ + "IPOWDS" }, /* Polarity watchdog , */ \ + { 0x4cc0, \ + "IPOAMPS" }, /* Polarity enbl amp , */ \ + { 0x4cd0, \ + "IPOAREFS" }, /* Polarity ref enable , */ \ + { 0x4ce0, \ + "IPOADCCR" }, /* Polarity Control ADC , */ \ + { 0x4cf0, \ + "IPOBODNOK" }, /* Polarity BOD , */ \ + { 0x4d00, \ + "IPOBSTCU" }, /* Polarity DCDC current limiting , */ \ + { 0x4d10, \ + "IPOBSTHI" }, /* Polarity DCDC active , */ \ + { 0x4d20, \ + "IPOBSTOC" }, /* Polarity DCDC OCP , */ \ + { 0x4d30, \ + "IPOBSTPC" }, /* Polarity bst peakcur , */ \ + { 0x4d40, \ + "IPOBSTVC" }, /* Polarity DCDC level 1x , */ \ + { 0x4d50, \ + "IPOBST86" }, /* Polarity DCDC level 1.14x , */ \ + { 0x4d60, \ + "IPOBST93" }, /* Polarity DCDC level 1.07x , */ \ + { 0x4d70, \ + "IPORCVLD" }, /* Polarity rcvldop ready , */ \ + { 0x4d80, \ + "IPOOCPL" }, /* Polarity ocp alarm left , */ \ + { 0x4d90, \ + "IPOOCPR" }, /* Polarity ocp alarm right , */ \ + { 0x4da0, \ + "IPOMWSRC" }, /* Polarity waits HW I2C settings , */ \ + { 0x4db0, \ + "IPOMWCFC" }, /* Polarity man wait cf config , */ \ + { 0x4dc0, \ + "IPOMWSMU" }, /* Polarity man audio mute sequence , */ \ + { 0x4dd0, \ + "IPOCFMER" }, /* Polarity cfma err , */ \ + { 0x4de0, \ + "IPOCFMAC" }, /* Polarity cfma ack , */ \ + { 0x4df0, \ + "IPCLKOOR" }, /* Polarity flag_clk_out_of_range , */ \ + { 0x4e00, \ + "IPOTDMER" }, /* Polarity tdm error , */ \ + { 0x4e10, \ + "IPOCLPL" }, /* Polarity clip left , */ \ + { 0x4e20, \ + "IPOCLPR" }, /* Polarity clip right , */ \ + { 0x4e30, \ + "IPOOCPM" }, /* Polarity mic ocpok , */ \ + { 0x5001, \ + "BSSCR" }, /* Battery protection attack Time , */ \ + { 0x5023, \ + "BSST" }, /* Battery protection threshold voltage level , */ \ + { 0x5061, \ + "BSSRL" }, /* Battery protection maximum reduction , */ \ + { 0x5082, \ + "BSSRR" }, /* Battery protection release time , */ \ + { 0x50b1, \ + "BSSHY" }, /* Battery protection hysteresis , */ \ + { 0x50e0, \ + "BSSR" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "BSSBY" }, /* Bypass HW clipper , */ \ + { 0x5100, \ + "BSSS" }, /* Vbat prot steepness , */ \ + { 0x5110, \ + "INTSMUTE" }, /* Soft mute HW , */ \ + { 0x5120, \ + "CFSML" }, /* Soft mute FW left , */ \ + { 0x5130, \ + "CFSMR" }, /* Soft mute FW right , */ \ + { 0x5140, \ + "HPFBYPL" }, /* Bypass HPF left , */ \ + { 0x5150, \ + "HPFBYPR" }, /* Bypass HPF right , */ \ + { 0x5160, \ + "DPSAL" }, /* Enable DPSA left , */ \ + { 0x5170, \ + "DPSAR" }, /* Enable DPSA right , */ \ + { 0x5187, \ + "VOL" }, /* FW volume control for primary audio channel , */ \ + { 0x5200, \ + "HNDSFRCV" }, /* Selection receiver , */ \ + { 0x5222, \ + "CLIPCTRL" }, /* Clip control setting , */ \ + { 0x5257, \ + "AMPGAIN" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "SLOPEE" }, /* Enables slope control , */ \ + { 0x52e1, \ + "SLOPESET" }, /* Set slope , */ \ + { 0x5a07, \ + "VOLSEC" }, /* FW volume control for secondary audio channel , */ \ + { 0x5a87, \ + "SWPROFIL" }, /* Software profile data , */ \ + { 0x7002, \ + "DCVO" }, /* Boost voltage , */ \ + { 0x7033, \ + "DCMCC" }, /* Max coil current , */ \ + { 0x7071, \ + "DCCV" }, /* Coil Value , */ \ + { 0x7090, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "DCSR" }, /* Soft ramp up/down , */ \ + { 0x70b2, \ + "DCSYNCP" }, /* DCDC synchronization off + 7 positions , */ \ + { 0x70e0, \ + "DCDIS" }, /* DCDC on/off , */ \ + { 0x9000, \ + "RST" }, /* Reset , */ \ + { 0x9011, \ + "DMEM" }, /* Target memory , */ \ + { 0x9030, \ + "AIF" }, /* Auto increment , */ \ + { 0x9040, \ + "CFINT" }, /* Interrupt - auto clear , */ \ + { 0x9050, \ + "CFCGATE" }, /* Coolflux clock gating disabling control , */ \ + { 0x9080, \ + "REQCMD" }, /* Firmware event request rpc command , */ \ + { 0x9090, \ + "REQRST" }, /* Firmware event request reset restart , */ \ + { 0x90a0, \ + "REQMIPS" }, /* Firmware event request short on mips , */ \ + { 0x90b0, \ + "REQMUTED" }, /* Firmware event request mute sequence ready , */ \ + { 0x90c0, \ + "REQVOL" }, /* Firmware event request volume ready , */ \ + { 0x90d0, \ + "REQDMG" }, /* Firmware event request speaker damage detected , */ \ + { 0x90e0, \ + "REQCAL" }, /* Firmware event request calibration completed , */ \ + { 0x90f0, \ + "REQRSV" }, /* Firmware event request reserved , */ \ + { 0x910f, \ + "MADD" }, /* Memory address , */ \ + { 0x920f, \ + "MEMA" }, /* Activate memory access , */ \ + { 0x9307, \ + "ERR" }, /* Error flags , */ \ + { 0x9387, \ + "ACK" }, /* Acknowledge of requests , */ \ + { 0x9380, \ + "ACKCMD" }, /* Firmware event acknowledge rpc command , */ \ + { 0x9390, \ + "ACKRST" }, /* Firmware event acknowledge reset restart , */ \ + { 0x93a0, \ + "ACKMIPS" }, /* Firmware event acknowledge short on mips , */ \ + { 0x93b0, \ + "ACKMUTED" }, /* Firmware event acknowledge mute sequence ready , */ \ + { 0x93c0, \ + "ACKVOL" }, /* Firmware event acknowledge volume ready , */ \ + { 0x93d0, \ + "ACKDMG" }, /* Firmware event acknowledge speaker damage detected, */ \ + { 0x93e0, \ + "ACKCAL" }, /* Firmware event acknowledge calibration completed , */ \ + { 0x93f0, \ + "ACKRSV" }, /* Firmware event acknowledge reserved , */ \ + { 0xa107, \ + "MTPK" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "KEY1LOCKED" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "KEY2LOCKED" }, /* Indicates KEY2 is locked , */ \ + { 0xa360, \ + "CIMTP" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa50f, \ + "MTPRDMSB" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "MTPRDLSB" }, /* LSB word of MTP manual read data , */ \ + { 0xb108, \ + "EXTTS" }, /* External temperature (C) , */ \ + { 0xb190, \ + "TROS" }, /* Select temp Speaker calibration , */ \ + { 0xf000, \ + "MTPOTC" }, /* Calibration schedule , */ \ + { 0xf010, \ + "MTPEX" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "DCMCCAPI" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "DCMCCSB" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "USERDEF" }, /* Calibration delta current limit DCDC , */ \ + { 0xf40f, \ + "R25CL" }, /* Ron resistance of left channel speaker coil , */ \ + { 0xf50f, \ + "R25CR" }, /* Ron resistance of right channel speaker coil , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA2_BITNAMETABLE \ + static tfaBfName_t Tfa2BitNames[] = { \ + { 0x0, \ + "powerdown" }, /* Powerdown selection , */ \ + { 0x10, \ + "reset" }, /* I2C Reset - Auto clear , */ \ + { 0x20, \ + "enbl_coolflux" }, /* Enable CoolFlux , */ \ + { 0x30, \ + "enbl_amplifier" }, /* Activate Amplifier , */ \ + { 0x40, \ + "enbl_boost" }, /* Activate DC-to-DC converter , */ \ + { 0x50, \ + "coolflux_configured" }, /* Coolflux configured , */ \ + { 0x60, \ + "sel_enbl_amplifier" }, /* CoolFlux controls amplifier , */ \ + { 0x71, \ + "int_pad_io" }, /* Interrupt config , */ \ + { 0x91, \ + "fs_pulse_sel" }, /* Audio sample reference , */ \ + { 0xb0, \ + "bypass_ocp" }, /* Bypass OCP , */ \ + { 0xc0, \ + "test_ocp" }, /* OCP testing control , */ \ + { 0x101, \ + "vamp_sel" }, /* Amplifier input selection , */ \ + { 0x120, \ + "src_set_configured" }, /* I2C configured , */ \ + { 0x130, \ + "execute_cold_start" }, /* Execute cold start , */ \ + { 0x140, \ + "enbl_osc1m_auto_off" }, /* Internal osc off at PWDN , */ \ + { 0x150, \ + "man_enbl_brown_out" }, /* Reaction on BOD , */ \ + { 0x160, \ + "enbl_bod" }, /* BOD Enable , */ \ + { 0x170, \ + "enbl_bod_hyst" }, /* BOD Hysteresis , */ \ + { 0x181, \ + "bod_delay" }, /* BOD filter , */ \ + { 0x1a1, \ + "bod_lvlsel" }, /* BOD threshold , */ \ + { 0x1d0, \ + "disable_mute_time_out" }, /* Time out SB mute sequence , */ \ + { 0x1e0, \ + "pwm_sel_rcv_ns" }, /* Noise shaper selection , */ \ + { 0x1f0, \ + "man_enbl_watchdog" }, /* Watchdog manager reaction , */ \ + { 0x203, \ + "audio_fs" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "input_level" }, /* TDM output attenuation , */ \ + { 0x255, \ + "cs_frac_delay" }, /* V/I Fractional delay , */ \ + { 0x2b0, \ + "bypass_hvbat_filter" }, /* Bypass HVBAT filter , */ \ + { 0x2c0, \ + "ctrl_rcvldop_bypass" }, /* Receiver LDO bypass , */ \ + { 0x30f, \ + "device_rev" }, /* Revision info , */ \ + { 0x401, \ + "pll_clkin_sel" }, /* PLL external ref clock , */ \ + { 0x420, \ + "pll_clkin_sel_osc" }, /* PLL internal ref clock , */ \ + { 0x500, \ + "enbl_spkr_ss_left" }, /* Enable left channel , */ \ + { 0x510, \ + "enbl_spkr_ss_right" }, /* Enable right channel , */ \ + { 0x520, \ + "enbl_volsense_left" }, /* Voltage sense left , */ \ + { 0x530, \ + "enbl_volsense_right" }, /* Voltage sense right , */ \ + { 0x540, \ + "enbl_cursense_left" }, /* Current sense left , */ \ + { 0x550, \ + "enbl_cursense_right" }, /* Current sense right , */ \ + { 0x560, \ + "enbl_pdm_ss" }, /* Sub-system PDM , */ \ + { 0xd00, \ + "side_tone_gain_sel" }, /* PDM side tone gain selector , */ \ + { 0xd18, \ + "side_tone_gain" }, /* Side tone gain , */ \ + { 0xda0, \ + "mute_side_tone" }, /* Side tone soft mute , */ \ + { 0xe06, \ + "ctrl_digtoana" }, /* Register for the host SW to record the current active vstep, */ \ + { 0xe70, \ + "enbl_cmfb_left" }, /* Current sense common mode feedback control for left channel, */ \ + { 0xf0f, \ + "hidden_code" }, /* 5A6Bh, 23147d to access registers (default for engineering), */ \ + { 0x1000, \ + "flag_por" }, /* POR , */ \ + { 0x1010, \ + "flag_pll_lock" }, /* PLL lock , */ \ + { 0x1020, \ + "flag_otpok" }, /* OTP alarm , */ \ + { 0x1030, \ + "flag_ovpok" }, /* OVP alarm , */ \ + { 0x1040, \ + "flag_uvpok" }, /* UVP alarm , */ \ + { 0x1050, \ + "flag_clocks_stable" }, /* Clocks stable , */ \ + { 0x1060, \ + "flag_mtp_busy" }, /* MTP busy , */ \ + { 0x1070, \ + "flag_lost_clk" }, /* Lost clock , */ \ + { 0x1080, \ + "flag_cf_speakererror" }, /* Speaker error , */ \ + { 0x1090, \ + "flag_cold_started" }, /* Cold Start , */ \ + { 0x10a0, \ + "flag_engage" }, /* Amplifier engage , */ \ + { 0x10b0, \ + "flag_watchdog_reset" }, /* Watchdog , */ \ + { 0x10c0, \ + "flag_enbl_amp" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "flag_enbl_ref" }, /* References enable , */ \ + { 0x10e0, \ + "flag_adc10_ready" }, /* Control ADC , */ \ + { 0x10f0, \ + "flag_bod_vddd_nok" }, /* BOD , */ \ + { 0x1100, \ + "flag_bst_bstcur" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "flag_bst_hiz" }, /* DCDC active , */ \ + { 0x1120, \ + "flag_bst_ocpok" }, /* DCDC OCP nmos , */ \ + { 0x1130, \ + "flag_bst_peakcur" }, /* Indicates current is max in DC-to-DC converter , */ \ + { 0x1140, \ + "flag_bst_voutcomp" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "flag_bst_voutcomp86" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "flag_bst_voutcomp93" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "flag_soft_mute_busy" }, /* side tone (un)mute busy , */ \ + { 0x1180, \ + "flag_soft_mute_state" }, /* side tone mute state , */ \ + { 0x1190, \ + "flag_tdm_lut_error" }, /* TDM LUT error , */ \ + { 0x11a2, \ + "flag_tdm_status" }, /* TDM status bits , */ \ + { 0x11d0, \ + "flag_tdm_error" }, /* TDM error , */ \ + { 0x11e0, \ + "flag_haptic_busy" }, /* Status haptic driver , */ \ + { 0x1200, \ + "flag_ocpokap_left" }, /* OCPOK pmos A left , */ \ + { 0x1210, \ + "flag_ocpokan_left" }, /* OCPOK nmos A left , */ \ + { 0x1220, \ + "flag_ocpokbp_left" }, /* OCPOK pmos B left , */ \ + { 0x1230, \ + "flag_ocpokbn_left" }, /* OCPOK nmos B left , */ \ + { 0x1240, \ + "flag_clipa_high_left" }, /* Clipping A left to Vddp , */ \ + { 0x1250, \ + "flag_clipa_low_left" }, /* Clipping A left to gnd , */ \ + { 0x1260, \ + "flag_clipb_high_left" }, /* Clipping B left to Vddp , */ \ + { 0x1270, \ + "flag_clipb_low_left" }, /* Clipping B left to gnd , */ \ + { 0x1280, \ + "flag_ocpokap_rcv" }, /* OCPOK pmos A RCV , */ \ + { 0x1290, \ + "flag_ocpokan_rcv" }, /* OCPOK nmos A RCV , */ \ + { 0x12a0, \ + "flag_ocpokbp_rcv" }, /* OCPOK pmos B RCV , */ \ + { 0x12b0, \ + "flag_ocpokbn_rcv" }, /* OCPOK nmos B RCV , */ \ + { 0x12c0, \ + "flag_rcvldop_ready" }, /* RCV LDO regulates , */ \ + { 0x12d0, \ + "flag_rcvldop_bypassready" }, /* Receiver LDO ready , */ \ + { 0x12e0, \ + "flag_ocp_alarm_left" }, /* OCP left amplifier , */ \ + { 0x12f0, \ + "flag_clip_left" }, /* Amplifier left clipping , */ \ + { 0x1300, \ + "flag_ocpokap_right" }, /* OCPOK pmos A right , */ \ + { 0x1310, \ + "flag_ocpokan_right" }, /* OCPOK nmos A right , */ \ + { 0x1320, \ + "flag_ocpokbp_right" }, /* OCPOK pmos B right , */ \ + { 0x1330, \ + "flag_ocpokbn_right" }, /* OCPOK nmos B right , */ \ + { 0x1340, \ + "flag_clipa_high_right" }, /* Clipping A right to Vddp , */ \ + { 0x1350, \ + "flag_clipa_low_right" }, /* Clipping A right to gnd , */ \ + { 0x1360, \ + "flag_clipb_high_right" }, /* Clipping B left to Vddp , */ \ + { 0x1370, \ + "flag_clipb_low_right" }, /* Clipping B right to gnd , */ \ + { 0x1380, \ + "flag_ocp_alarm_right" }, /* OCP right amplifier , */ \ + { 0x1390, \ + "flag_clip_right" }, /* Amplifier right clipping , */ \ + { 0x13a0, \ + "flag_mic_ocpok" }, /* OCPOK MICVDD , */ \ + { 0x13b0, \ + "flag_man_alarm_state" }, /* Alarm state , */ \ + { 0x13c0, \ + "flag_man_wait_src_settings" }, /* Wait HW I2C settings , */ \ + { 0x13d0, \ + "flag_man_wait_cf_config" }, /* Wait CF config , */ \ + { 0x13e0, \ + "flag_man_start_mute_audio" }, /* Audio mute sequence , */ \ + { 0x13f0, \ + "flag_man_operating_state" }, /* Operating state , */ \ + { 0x1400, \ + "flag_cf_speakererror_left" }, /* Left speaker status , */ \ + { 0x1410, \ + "flag_cf_speakererror_right" }, /* Right speaker status , */ \ + { 0x1420, \ + "flag_clk_out_of_range" }, /* External clock status , */ \ + { 0x1433, \ + "man_state" }, /* Device manager status , */ \ + { 0x1509, \ + "bat_adc" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "temp_adc" }, /* IC Temperature (C) , */ \ + { 0x2003, \ + "tdm_usecase" }, /* Usecase setting , */ \ + { 0x2040, \ + "tdm_enable" }, /* Enable interface , */ \ + { 0x2050, \ + "tdm_mode" }, /* Slave/master , */ \ + { 0x2060, \ + "tdm_clk_inversion" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "tdm_fs_ws_length" }, /* FS length (master mode only) , */ \ + { 0x20b0, \ + "tdm_fs_ws_polarity" }, /* FS polarity , */ \ + { 0x20c3, \ + "tdm_nbck" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "tdm_nb_of_slots" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "tdm_slot_length" }, /* N-bits in slot , */ \ + { 0x2194, \ + "tdm_bits_remaining" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "tdm_data_delay" }, /* data delay to FS , */ \ + { 0x21f0, \ + "tdm_data_adjustment" }, /* data adjustment , */ \ + { 0x2201, \ + "tdm_audio_sample_compression" }, /* Received audio compression , */ \ + { 0x2224, \ + "tdm_sample_size" }, /* Sample size per slot , */ \ + { 0x2271, \ + "tdm_txdata_format" }, /* Format unused bits , */ \ + { 0x2291, \ + "tdm_txdata_format_unused_slot_sd0" }, /* Format unused slots GAINIO , */ \ + { 0x22b1, \ + "tdm_txdata_format_unused_slot_sd1" }, /* Format unused slots DIO1 , */ \ + { 0x22d1, \ + "tdm_txdata_format_unused_slot_sd2" }, /* Format unused slots DIO2 , */ \ + { 0x2300, \ + "tdm_sink0_enable" }, /* Control gainin (not used in DSP) , */ \ + { 0x2310, \ + "tdm_sink1_enable" }, /* Control audio left , */ \ + { 0x2320, \ + "tdm_sink2_enable" }, /* Control audio right , */ \ + { 0x2330, \ + "tdm_source0_enable" }, /* Control gainout (not used in DSP) , */ \ + { 0x2340, \ + "tdm_source1_enable" }, /* Control voltage sense right , */ \ + { 0x2350, \ + "tdm_source2_enable" }, /* Control current sense right , */ \ + { 0x2360, \ + "tdm_source3_enable" }, /* Voltage sense left control , */ \ + { 0x2370, \ + "tdm_source4_enable" }, /* Current sense left control , */ \ + { 0x2380, \ + "tdm_source5_enable" }, /* DSP out right control , */ \ + { 0x2390, \ + "tdm_source6_enable" }, /* DSP out left control , */ \ + { 0x23a0, \ + "tdm_source7_enable" }, /* AEC ref left control , */ \ + { 0x23b0, \ + "tdm_source8_enable" }, /* AEC ref right control , */ \ + { 0x23c0, \ + "tdm_source9_enable" }, /* PDM 1 control , */ \ + { 0x23d0, \ + "tdm_source10_enable" }, /* PDM 2 control , */ \ + { 0x2401, \ + "tdm_sink0_io" }, /* IO gainin (not used in DSP) , */ \ + { 0x2421, \ + "tdm_sink1_io" }, /* IO audio left , */ \ + { 0x2441, \ + "tdm_sink2_io" }, /* IO audio right , */ \ + { 0x2461, \ + "tdm_source0_io" }, /* IO gainout (not used in DSP) , */ \ + { 0x2481, \ + "tdm_source1_io" }, /* IO voltage sense right , */ \ + { 0x24a1, \ + "tdm_source2_io" }, /* IO current sense right , */ \ + { 0x24c1, \ + "tdm_source3_io" }, /* IO voltage sense left , */ \ + { 0x24e1, \ + "tdm_source4_io" }, /* IO current sense left , */ \ + { 0x2501, \ + "tdm_source5_io" }, /* IO dspout right , */ \ + { 0x2521, \ + "tdm_source6_io" }, /* IO dspout left , */ \ + { 0x2541, \ + "tdm_source7_io" }, /* IO AEC ref left control , */ \ + { 0x2561, \ + "tdm_source8_io" }, /* IO AEC ref right control , */ \ + { 0x2581, \ + "tdm_source9_io" }, /* IO pdm1 , */ \ + { 0x25a1, \ + "tdm_source10_io" }, /* IO pdm2 , */ \ + { 0x2603, \ + "tdm_sink0_slot" }, /* Position gainin (not used in DSP) , */ \ + { 0x2643, \ + "tdm_sink1_slot" }, /* Position audio left , */ \ + { 0x2683, \ + "tdm_sink2_slot" }, /* Position audio right , */ \ + { 0x26c3, \ + "tdm_source0_slot" }, /* Position gainout (not used in DSP) , */ \ + { 0x2703, \ + "tdm_source1_slot" }, /* Position voltage sense right , */ \ + { 0x2743, \ + "tdm_source2_slot" }, /* Position current sense right , */ \ + { 0x2783, \ + "tdm_source3_slot" }, /* Position voltage sense left , */ \ + { 0x27c3, \ + "tdm_source4_slot" }, /* Position current sense left , */ \ + { 0x2803, \ + "tdm_source5_slot" }, /* Position dspout right , */ \ + { 0x2843, \ + "tdm_source6_slot" }, /* Position dspout left , */ \ + { 0x2883, \ + "tdm_source7_slot" }, /* Position AEC ref left control , */ \ + { 0x28c3, \ + "tdm_source8_slot" }, /* Position AEC ref right control , */ \ + { 0x2903, \ + "tdm_source9_slot" }, /* Position pdm1 , */ \ + { 0x2943, \ + "tdm_source10_slot" }, /* Position pdm2 , */ \ + { 0x3100, \ + "pdm_mode" }, /* PDM control , */ \ + { 0x3111, \ + "pdm_side_tone_sel" }, /* Side tone input , */ \ + { 0x3130, \ + "pdm_left_sel" }, /* PDM data selection for left channel during PDM direct mode, */ \ + { 0x3140, \ + "pdm_right_sel" }, /* PDM data selection for right channel during PDM direct mode, */ \ + { 0x3150, \ + "enbl_micvdd" }, /* Enable MICVDD , */ \ + { 0x3160, \ + "bypass_micvdd_ocp" }, /* Bypass control for the MICVDD OCP flag processing , */ \ + { 0x3201, \ + "pdm_nbck" }, /* PDM BCK/Fs ratio , */ \ + { 0x3223, \ + "pdm_gain" }, /* PDM gain , */ \ + { 0x3263, \ + "sel_pdm_out_data" }, /* PDM output selection - RE/FE data combination , */ \ + { 0x32a0, \ + "sel_cf_haptic_data" }, /* Select the source for haptic data output (not for customer), */ \ + { 0x3307, \ + "haptic_duration" }, /* Duration (ms) , */ \ + { 0x3387, \ + "haptic_data" }, /* DC value (FFS) , */ \ + { 0x3403, \ + "gpio_datain" }, /* Receiving value , */ \ + { 0x3500, \ + "gpio_ctrl" }, /* GPIO master control over GPIO1/2 ports (not for customer), */ \ + { 0x3513, \ + "gpio_dir" }, /* Configuration , */ \ + { 0x3553, \ + "gpio_dataout" }, /* Transmitting value , */ \ + { 0x4000, \ + "int_out_flag_por" }, /* Status POR , */ \ + { 0x4010, \ + "int_out_flag_pll_lock" }, /* Status PLL lock , */ \ + { 0x4020, \ + "int_out_flag_otpok" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "int_out_flag_ovpok" }, /* Status OVP alarm , */ \ + { 0x4040, \ + "int_out_flag_uvpok" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "int_out_flag_clocks_stable" }, /* Status clocks stable , */ \ + { 0x4060, \ + "int_out_flag_mtp_busy" }, /* Status MTP busy , */ \ + { 0x4070, \ + "int_out_flag_lost_clk" }, /* Status lost clock , */ \ + { 0x4080, \ + "int_out_flag_cf_speakererror" }, /* Status speaker error , */ \ + { 0x4090, \ + "int_out_flag_cold_started" }, /* Status cold start , */ \ + { 0x40a0, \ + "int_out_flag_engage" }, /* Status amplifier engage , */ \ + { 0x40b0, \ + "int_out_flag_watchdog_reset" }, /* Status watchdog , */ \ + { 0x40c0, \ + "int_out_flag_enbl_amp" }, /* Status amplifier enable , */ \ + { 0x40d0, \ + "int_out_flag_enbl_ref" }, /* Status Ref enable , */ \ + { 0x40e0, \ + "int_out_flag_adc10_ready" }, /* Status Control ADC , */ \ + { 0x40f0, \ + "int_out_flag_bod_vddd_nok" }, /* Status BOD , */ \ + { 0x4100, \ + "int_out_flag_bst_bstcur" }, /* Status DCDC current limiting , */ \ + { 0x4110, \ + "int_out_flag_bst_hiz" }, /* Status DCDC active , */ \ + { 0x4120, \ + "int_out_flag_bst_ocpok" }, /* Status DCDC OCP , */ \ + { 0x4130, \ + "int_out_flag_bst_peakcur" }, /* Status bst peakcur , */ \ + { 0x4140, \ + "int_out_flag_bst_voutcomp" }, /* Status DCDC level 1x , */ \ + { 0x4150, \ + "int_out_flag_bst_voutcomp86" }, /* Status DCDC level 1.14x , */ \ + { 0x4160, \ + "int_out_flag_bst_voutcomp93" }, /* Status DCDC level 1.07x , */ \ + { 0x4170, \ + "int_out_flag_rcvldop_ready" }, /* Status rcvldop ready , */ \ + { 0x4180, \ + "int_out_flag_ocp_alarm_left" }, /* Status ocp alarm left , */ \ + { 0x4190, \ + "int_out_flag_ocp_alarm_right" }, /* Status ocp alarm right , */ \ + { 0x41a0, \ + "int_out_flag_man_wait_src_settings" }, /* Status Waits HW I2C settings , */ \ + { 0x41b0, \ + "int_out_flag_man_wait_cf_config" }, /* Status waits CF config , */ \ + { 0x41c0, \ + "int_out_flag_man_start_mute_audio" }, /* Status Audio mute sequence , */ \ + { 0x41d0, \ + "int_out_flag_cfma_err" }, /* Status cfma error , */ \ + { 0x41e0, \ + "int_out_flag_cfma_ack" }, /* Status cfma ack , */ \ + { 0x41f0, \ + "int_out_flag_clk_out_of_range" }, /* Status flag_clk_out_of_range , */ \ + { 0x4200, \ + "int_out_flag_tdm_error" }, /* Status tdm error , */ \ + { 0x4210, \ + "int_out_flag_clip_left" }, /* Status clip left , */ \ + { 0x4220, \ + "int_out_flag_clip_right" }, /* Status clip right , */ \ + { 0x4230, \ + "int_out_flag_mic_ocpok" }, /* Status mic ocpok , */ \ + { 0x4400, \ + "int_in_flag_por" }, /* Clear POR , */ \ + { 0x4410, \ + "int_in_flag_pll_lock" }, /* Clear PLL lock , */ \ + { 0x4420, \ + "int_in_flag_otpok" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "int_in_flag_ovpok" }, /* Clear OVP alarm , */ \ + { 0x4440, \ + "int_in_flag_uvpok" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "int_in_flag_clocks_stable" }, /* Clear clocks stable , */ \ + { 0x4460, \ + "int_in_flag_mtp_busy" }, /* Clear mtp busy , */ \ + { 0x4470, \ + "int_in_flag_lost_clk" }, /* Clear lost clk , */ \ + { 0x4480, \ + "int_in_flag_cf_speakererror" }, /* Clear speaker error , */ \ + { 0x4490, \ + "int_in_flag_cold_started" }, /* Clear cold started , */ \ + { 0x44a0, \ + "int_in_flag_engage" }, /* Clear amplifier engage , */ \ + { 0x44b0, \ + "int_in_flag_watchdog_reset" }, /* Clear watchdog , */ \ + { 0x44c0, \ + "int_in_flag_enbl_amp" }, /* Clear enbl amp , */ \ + { 0x44d0, \ + "int_in_flag_enbl_ref" }, /* Clear ref enable , */ \ + { 0x44e0, \ + "int_in_flag_adc10_ready" }, /* Clear control ADC , */ \ + { 0x44f0, \ + "int_in_flag_bod_vddd_nok" }, /* Clear BOD , */ \ + { 0x4500, \ + "int_in_flag_bst_bstcur" }, /* Clear DCDC current limiting , */ \ + { 0x4510, \ + "int_in_flag_bst_hiz" }, /* Clear DCDC active , */ \ + { 0x4520, \ + "int_in_flag_bst_ocpok" }, /* Clear DCDC OCP , */ \ + { 0x4530, \ + "int_in_flag_bst_peakcur" }, /* Clear bst peakcur , */ \ + { 0x4540, \ + "int_in_flag_bst_voutcomp" }, /* Clear DCDC level 1x , */ \ + { 0x4550, \ + "int_in_flag_bst_voutcomp86" }, /* Clear DCDC level 1.14x , */ \ + { 0x4560, \ + "int_in_flag_bst_voutcomp93" }, /* Clear DCDC level 1.07x , */ \ + { 0x4570, \ + "int_in_flag_rcvldop_ready" }, /* Clear rcvldop ready , */ \ + { 0x4580, \ + "int_in_flag_ocp_alarm_left" }, /* Clear ocp alarm left , */ \ + { 0x4590, \ + "int_in_flag_ocp_alarm_right" }, /* Clear ocp alarm right , */ \ + { 0x45a0, \ + "int_in_flag_man_wait_src_settings" }, /* Clear wait HW I2C settings , */ \ + { 0x45b0, \ + "int_in_flag_man_wait_cf_config" }, /* Clear wait cf config , */ \ + { 0x45c0, \ + "int_in_flag_man_start_mute_audio" }, /* Clear audio mute sequence , */ \ + { 0x45d0, \ + "int_in_flag_cfma_err" }, /* Clear cfma err , */ \ + { 0x45e0, \ + "int_in_flag_cfma_ack" }, /* Clear cfma ack , */ \ + { 0x45f0, \ + "int_in_flag_clk_out_of_range" }, /* Clear flag_clk_out_of_range , */ \ + { 0x4600, \ + "int_in_flag_tdm_error" }, /* Clear tdm error , */ \ + { 0x4610, \ + "int_in_flag_clip_left" }, /* Clear clip left , */ \ + { 0x4620, \ + "int_in_flag_clip_right" }, /* Clear clip right , */ \ + { 0x4630, \ + "int_in_flag_mic_ocpok" }, /* Clear mic ocpok , */ \ + { 0x4800, \ + "int_enable_flag_por" }, /* Enable por , */ \ + { 0x4810, \ + "int_enable_flag_pll_lock" }, /* Enable pll lock , */ \ + { 0x4820, \ + "int_enable_flag_otpok" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "int_enable_flag_ovpok" }, /* Enable OVP alarm , */ \ + { 0x4840, \ + "int_enable_flag_uvpok" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "int_enable_flag_clocks_stable" }, /* Enable clocks stable , */ \ + { 0x4860, \ + "int_enable_flag_mtp_busy" }, /* Enable mtp busy , */ \ + { 0x4870, \ + "int_enable_flag_lost_clk" }, /* Enable lost clk , */ \ + { 0x4880, \ + "int_enable_flag_cf_speakererror" }, /* Enable speaker error , */ \ + { 0x4890, \ + "int_enable_flag_cold_started" }, /* Enable cold started , */ \ + { 0x48a0, \ + "int_enable_flag_engage" }, /* Enable amplifier engage , */ \ + { 0x48b0, \ + "int_enable_flag_watchdog_reset" }, /* Enable watchdog , */ \ + { 0x48c0, \ + "int_enable_flag_enbl_amp" }, /* Enable enbl amp , */ \ + { 0x48d0, \ + "int_enable_flag_enbl_ref" }, /* Enable ref enable , */ \ + { 0x48e0, \ + "int_enable_flag_adc10_ready" }, /* Enable Control ADC , */ \ + { 0x48f0, \ + "int_enable_flag_bod_vddd_nok" }, /* Enable BOD , */ \ + { 0x4900, \ + "int_enable_flag_bst_bstcur" }, /* Enable DCDC current limiting , */ \ + { 0x4910, \ + "int_enable_flag_bst_hiz" }, /* Enable DCDC active , */ \ + { 0x4920, \ + "int_enable_flag_bst_ocpok" }, /* Enable DCDC OCP , */ \ + { 0x4930, \ + "int_enable_flag_bst_peakcur" }, /* Enable bst peakcur , */ \ + { 0x4940, \ + "int_enable_flag_bst_voutcomp" }, /* Enable DCDC level 1x , */ \ + { 0x4950, \ + "int_enable_flag_bst_voutcomp86" }, /* Enable DCDC level 1.14x , */ \ + { 0x4960, \ + "int_enable_flag_bst_voutcomp93" }, /* Enable DCDC level 1.07x , */ \ + { 0x4970, \ + "int_enable_flag_rcvldop_ready" }, /* Enable rcvldop ready , */ \ + { 0x4980, \ + "int_enable_flag_ocp_alarm_left" }, /* Enable ocp alarm left , */ \ + { 0x4990, \ + "int_enable_flag_ocp_alarm_right" }, /* Enable ocp alarm right , */ \ + { 0x49a0, \ + "int_enable_flag_man_wait_src_settings" }, /* Enable waits HW I2C settings , */ \ + { 0x49b0, \ + "int_enable_flag_man_wait_cf_config" }, /* Enable man wait cf config , */ \ + { 0x49c0, \ + "int_enable_flag_man_start_mute_audio" }, /* Enable man Audio mute sequence , */ \ + { 0x49d0, \ + "int_enable_flag_cfma_err" }, /* Enable cfma err , */ \ + { 0x49e0, \ + "int_enable_flag_cfma_ack" }, /* Enable cfma ack , */ \ + { 0x49f0, \ + "int_enable_flag_clk_out_of_range" }, /* Enable flag_clk_out_of_range , */ \ + { 0x4a00, \ + "int_enable_flag_tdm_error" }, /* Enable tdm error , */ \ + { 0x4a10, \ + "int_enable_flag_clip_left" }, /* Enable clip left , */ \ + { 0x4a20, \ + "int_enable_flag_clip_right" }, /* Enable clip right , */ \ + { 0x4a30, \ + "int_enable_flag_mic_ocpok" }, /* Enable mic ocpok , */ \ + { 0x4c00, \ + "int_polarity_flag_por" }, /* Polarity por , */ \ + { 0x4c10, \ + "int_polarity_flag_pll_lock" }, /* Polarity pll lock , */ \ + { 0x4c20, \ + "int_polarity_flag_otpok" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "int_polarity_flag_ovpok" }, /* Polarity OVP alarm , */ \ + { 0x4c40, \ + "int_polarity_flag_uvpok" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "int_polarity_flag_clocks_stable" }, /* Polarity clocks stable , */ \ + { 0x4c60, \ + "int_polarity_flag_mtp_busy" }, /* Polarity mtp busy , */ \ + { 0x4c70, \ + "int_polarity_flag_lost_clk" }, /* Polarity lost clk , */ \ + { 0x4c80, \ + "int_polarity_flag_cf_speakererror" }, /* Polarity speaker error , */ \ + { 0x4c90, \ + "int_polarity_flag_cold_started" }, /* Polarity cold started , */ \ + { 0x4ca0, \ + "int_polarity_flag_engage" }, /* Polarity amplifier engage , */ \ + { 0x4cb0, \ + "int_polarity_flag_watchdog_reset" }, /* Polarity watchdog , */ \ + { 0x4cc0, \ + "int_polarity_flag_enbl_amp" }, /* Polarity enbl amp , */ \ + { 0x4cd0, \ + "int_polarity_flag_enbl_ref" }, /* Polarity ref enable , */ \ + { 0x4ce0, \ + "int_polarity_flag_adc10_ready" }, /* Polarity Control ADC , */ \ + { 0x4cf0, \ + "int_polarity_flag_bod_vddd_nok" }, /* Polarity BOD , */ \ + { 0x4d00, \ + "int_polarity_flag_bst_bstcur" }, /* Polarity DCDC current limiting , */ \ + { 0x4d10, \ + "int_polarity_flag_bst_hiz" }, /* Polarity DCDC active , */ \ + { 0x4d20, \ + "int_polarity_flag_bst_ocpok" }, /* Polarity DCDC OCP , */ \ + { 0x4d30, \ + "int_polarity_flag_bst_peakcur" }, /* Polarity bst peakcur , */ \ + { 0x4d40, \ + "int_polarity_flag_bst_voutcomp" }, /* Polarity DCDC level 1x , */ \ + { 0x4d50, \ + "int_polarity_flag_bst_voutcomp86" }, /* Polarity DCDC level 1.14x , */ \ + { 0x4d60, \ + "int_polarity_flag_bst_voutcomp93" }, /* Polarity DCDC level 1.07x , */ \ + { 0x4d70, \ + "int_polarity_flag_rcvldop_ready" }, /* Polarity rcvldop ready , */ \ + { 0x4d80, \ + "int_polarity_flag_ocp_alarm_left" }, /* Polarity ocp alarm left , */ \ + { 0x4d90, \ + "int_polarity_flag_ocp_alarm_right" }, /* Polarity ocp alarm right , */ \ + { 0x4da0, \ + "int_polarity_flag_man_wait_src_settings" }, /* Polarity waits HW I2C settings , */ \ + { 0x4db0, \ + "int_polarity_flag_man_wait_cf_config" }, /* Polarity man wait cf config , */ \ + { 0x4dc0, \ + "int_polarity_flag_man_start_mute_audio" }, /* Polarity man audio mute sequence , */ \ + { 0x4dd0, \ + "int_polarity_flag_cfma_err" }, /* Polarity cfma err , */ \ + { 0x4de0, \ + "int_polarity_flag_cfma_ack" }, /* Polarity cfma ack , */ \ + { 0x4df0, \ + "int_polarity_flag_clk_out_of_range" }, /* Polarity flag_clk_out_of_range , */ \ + { 0x4e00, \ + "int_polarity_flag_tdm_error" }, /* Polarity tdm error , */ \ + { 0x4e10, \ + "int_polarity_flag_clip_left" }, /* Polarity clip left , */ \ + { 0x4e20, \ + "int_polarity_flag_clip_right" }, /* Polarity clip right , */ \ + { 0x4e30, \ + "int_polarity_flag_mic_ocpok" }, /* Polarity mic ocpok , */ \ + { 0x5001, \ + "vbat_prot_attack_time" }, /* Battery protection attack Time , */ \ + { 0x5023, \ + "vbat_prot_thlevel" }, /* Battery protection threshold voltage level , */ \ + { 0x5061, \ + "vbat_prot_max_reduct" }, /* Battery protection maximum reduction , */ \ + { 0x5082, \ + "vbat_prot_release_time" }, /* Battery protection release time , */ \ + { 0x50b1, \ + "vbat_prot_hysterese" }, /* Battery protection hysteresis , */ \ + { 0x50d0, \ + "rst_min_vbat" }, /* Reset clipper - Auto clear , */ \ + { 0x50e0, \ + "sel_vbat" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "bypass_clipper" }, /* Bypass HW clipper , */ \ + { 0x5100, \ + "batsense_steepness" }, /* Vbat prot steepness , */ \ + { 0x5110, \ + "soft_mute" }, /* Soft mute HW , */ \ + { 0x5120, \ + "cf_mute_left" }, /* Soft mute FW left , */ \ + { 0x5130, \ + "cf_mute_right" }, /* Soft mute FW right , */ \ + { 0x5140, \ + "bypass_hp_left" }, /* Bypass HPF left , */ \ + { 0x5150, \ + "bypass_hp_right" }, /* Bypass HPF right , */ \ + { 0x5160, \ + "enbl_dpsa_left" }, /* Enable DPSA left , */ \ + { 0x5170, \ + "enbl_dpsa_right" }, /* Enable DPSA right , */ \ + { 0x5187, \ + "cf_volume" }, /* FW volume control for primary audio channel , */ \ + { 0x5200, \ + "ctrl_rcv" }, /* Selection receiver , */ \ + { 0x5210, \ + "ctrl_rcv_fb_100k" }, /* Selection of feedback resistor for receiver mode (not for customer), */ \ + { 0x5222, \ + "ctrl_cc" }, /* Clip control setting , */ \ + { 0x5257, \ + "gain" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "ctrl_slopectrl" }, /* Enables slope control , */ \ + { 0x52e1, \ + "ctrl_slope" }, /* Set slope , */ \ + { 0x5301, \ + "dpsa_level" }, /* DPSA threshold levels , */ \ + { 0x5321, \ + "dpsa_release" }, /* DPSA Release time , */ \ + { 0x5340, \ + "clipfast" }, /* Clock selection for HW clipper for battery protection, */ \ + { 0x5350, \ + "bypass_lp" }, /* Bypass the low power filter inside temperature sensor, */ \ + { 0x5360, \ + "enbl_low_latency" }, /* CF low latency outputs for add module , */ \ + { 0x5400, \ + "first_order_mode" }, /* Overrule to 1st order mode of control stage when clipping, */ \ + { 0x5410, \ + "bypass_ctrlloop" }, /* Switch amplifier into open loop configuration , */ \ + { 0x5420, \ + "fb_hz" }, /* Feedback resistor set to high ohmic , */ \ + { 0x5430, \ + "icomp_engage" }, /* Engage of icomp , */ \ + { 0x5440, \ + "ctrl_kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x5450, \ + "icomp_engage_overrule" }, /* To overrule the functional icomp_engage signal during validation, */ \ + { 0x5503, \ + "ctrl_dem" }, /* Enable DEM icomp and DEM one bit dac , */ \ + { 0x5543, \ + "ctrl_dem_mismatch" }, /* Enable DEM icomp mismatch for testing , */ \ + { 0x5581, \ + "dpsa_drive" }, /* Control of the number of power stage sections, total of 4 sections. Each section is 1/4 of the total power stages., */ \ + { 0x560a, \ + "enbl_amp_left" }, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Left channel, */ \ + { 0x56b0, \ + "enbl_engage_left" }, /* Enables/engage power stage and control loop - left channel, */ \ + { 0x570a, \ + "enbl_amp_right" }, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually - Right channel, */ \ + { 0x57b0, \ + "enbl_engage_right" }, /* Enables/engage power stage and control loop - right channel, */ \ + { 0x5800, \ + "hard_mute_left" }, /* Hard mute - PWM module left , */ \ + { 0x5810, \ + "hard_mute_right" }, /* Hard mute - PWM module right , */ \ + { 0x5820, \ + "pwm_shape" }, /* PWM shape , */ \ + { 0x5830, \ + "pwm_bitlength" }, /* PWM bit length in noise shaper , */ \ + { 0x5844, \ + "pwm_delay" }, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */ \ + { 0x5890, \ + "reclock_pwm" }, /* Reclock the pwm signal inside analog , */ \ + { 0x58a0, \ + "reclock_voltsense" }, /* Reclock the voltage sense pwm signal , */ \ + { 0x58b0, \ + "enbl_pwm_phase_shift_left" }, /* Control for pwm phase shift, inverted function - left channel, */ \ + { 0x58c0, \ + "enbl_pwm_phase_shift_right" }, /* Control for pwm phase shift - right channel , */ \ + { 0x5900, \ + "ctrl_rcvldop_pulldown" }, /* Pulldown of LDO (2.7V) , */ \ + { 0x5910, \ + "ctrl_rcvldop_test_comp" }, /* Enable testing of LDO comparator , */ \ + { 0x5920, \ + "ctrl_rcvldop_test_loadedldo" }, /* Load connected to rcvldo , */ \ + { 0x5930, \ + "enbl_rcvldop" }, /* Enables the LDO (2.7) , */ \ + { 0x5a07, \ + "cf_volume_sec" }, /* FW volume control for secondary audio channel , */ \ + { 0x5a87, \ + "sw_profile" }, /* Software profile data , */ \ + { 0x7002, \ + "boost_volt" }, /* Boost voltage , */ \ + { 0x7033, \ + "boost_cur" }, /* Max coil current , */ \ + { 0x7071, \ + "bst_coil_value" }, /* Coil Value , */ \ + { 0x7090, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "boost_speed" }, /* Soft ramp up/down , */ \ + { 0x70b2, \ + "dcdc_synchronisation" }, /* DCDC synchronization off + 7 positions , */ \ + { 0x70e0, \ + "dcdcoff_mode" }, /* DCDC on/off , */ \ + { 0x7104, \ + "bst_drive" }, /* Binary coded drive setting for boost converter power stage, */ \ + { 0x7151, \ + "bst_scalecur" }, /* For testing direct control scale current , */ \ + { 0x7174, \ + "bst_slopecur" }, /* For testing direct control slope current , */ \ + { 0x71c1, \ + "bst_slope" }, /* Boost slope speed , */ \ + { 0x71e0, \ + "bst_bypass_bstcur" }, /* Bypass control for boost current settings , */ \ + { 0x71f0, \ + "bst_bypass_bstfoldback" }, /* Bypass control for boost foldback , */ \ + { 0x7200, \ + "enbl_bst_engage" }, /* Enable power stage dcdc controller , */ \ + { 0x7210, \ + "enbl_bst_hizcom" }, /* Enable hiz comparator , */ \ + { 0x7220, \ + "enbl_bst_peak2avg" }, /* Enable boost peak2avg functionality , */ \ + { 0x7230, \ + "enbl_bst_peakcur" }, /* Enable peak current , */ \ + { 0x7240, \ + "enbl_bst_power" }, /* Enable line of the powerstage , */ \ + { 0x7250, \ + "enbl_bst_slopecur" }, /* Enable bit of max-current dac , */ \ + { 0x7260, \ + "enbl_bst_voutcomp" }, /* Enable vout comparators , */ \ + { 0x7270, \ + "enbl_bst_voutcomp86" }, /* Enable vout-86 comparators , */ \ + { 0x7280, \ + "enbl_bst_voutcomp93" }, /* Enable vout-93 comparators , */ \ + { 0x7290, \ + "enbl_bst_windac" }, /* Enable window dac , */ \ + { 0x72a5, \ + "bst_windac" }, /* for testing direct control windac , */ \ + { 0x7300, \ + "boost_alg" }, /* Control for boost adaptive loop gain , */ \ + { 0x7311, \ + "boost_loopgain" }, /* DCDC boost loopgain setting , */ \ + { 0x7332, \ + "bst_freq" }, /* DCDC bost frequency control , */ \ + { 0x8001, \ + "sel_clk_cs" }, /* Current sense clock duty cycle control , */ \ + { 0x8021, \ + "micadc_speed" }, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */ \ + { 0x8040, \ + "cs_dc_offset" }, /* Current sense decimator offset control , */ \ + { 0x8050, \ + "cs_gain_control" }, /* Current sense gain control , */ \ + { 0x8060, \ + "cs_bypass_gc" }, /* Bypasses the CS gain correction , */ \ + { 0x8087, \ + "cs_gain" }, /* Current sense gain , */ \ + { 0x8110, \ + "invertpwm_left" }, /* Current sense common mode feedback pwm invert control for left channel, */ \ + { 0x8122, \ + "cmfb_gain_left" }, /* Current sense common mode feedback control gain for left channel, */ \ + { 0x8154, \ + "cmfb_offset_left" }, /* Current sense common mode feedback control offset for left channel, */ \ + { 0x8200, \ + "enbl_cmfb_right" }, /* Current sense common mode feedback control for right channel, */ \ + { 0x8210, \ + "invertpwm_right" }, /* Current sense common mode feedback pwm invert control for right channel, */ \ + { 0x8222, \ + "cmfb_gain_right" }, /* Current sense common mode feedback control gain for right channel, */ \ + { 0x8254, \ + "cmfb_offset_right" }, /* Current sense common mode feedback control offset for right channel, */ \ + { 0x8305, \ + "cs_ktemp" }, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */ \ + { 0x8400, \ + "cs_adc_bsoinv" }, /* Bitstream inversion for current sense ADC , */ \ + { 0x8421, \ + "cs_adc_hifreq" }, /* Frequency mode current sense ADC , */ \ + { 0x8440, \ + "cs_adc_nortz" }, /* Return to zero for current sense ADC , */ \ + { 0x8453, \ + "cs_adc_offset" }, /* Micadc ADC offset setting , */ \ + { 0x8490, \ + "cs_adc_slowdel" }, /* Select delay for current sense ADC (internal decision circuitry), */ \ + { 0x84a4, \ + "cs_adc_gain" }, /* Gain setting for current sense ADC (two's complement), */ \ + { 0x8500, \ + "cs_resonator_enable" }, /* Enable for resonator to improve SRN , */ \ + { 0x8510, \ + "cs_classd_tran_skip" }, /* Skip current sense connection during a classD amplifier transition, */ \ + { 0x8530, \ + "cs_inn_short" }, /* Short current sense negative to common mode , */ \ + { 0x8540, \ + "cs_inp_short" }, /* Short current sense positive to common mode , */ \ + { 0x8550, \ + "cs_ldo_bypass" }, /* Bypass current sense LDO , */ \ + { 0x8560, \ + "cs_ldo_pulldown" }, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */ \ + { 0x8574, \ + "cs_ldo_voset" }, /* Current sense LDO voltage level setting (two's complement), */ \ + { 0x8600, \ + "enbl_cs_adc_left" }, /* Enable current sense ADC , */ \ + { 0x8610, \ + "enbl_cs_inn1_left" }, /* Enable connection of current sense negative1 , */ \ + { 0x8630, \ + "enbl_cs_inp1_left" }, /* Enable connection of current sense positive1 , */ \ + { 0x8650, \ + "enbl_cs_ldo_left" }, /* Enable current sense LDO , */ \ + { 0x8660, \ + "enbl_cs_nofloating_n_left" }, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8670, \ + "enbl_cs_nofloating_p_left" }, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8680, \ + "enbl_cs_vbatldo_left" }, /* Enable of current sense LDO , */ \ + { 0x8700, \ + "enbl_cs_adc_right" }, /* Enable current sense ADC , */ \ + { 0x8710, \ + "enbl_cs_inn1_right" }, /* Enable connection of current sense negative1 , */ \ + { 0x8730, \ + "enbl_cs_inp1_right" }, /* Enable connection of current sense positive1 , */ \ + { 0x8750, \ + "enbl_cs_ldo_right" }, /* Enable current sense LDO , */ \ + { 0x8760, \ + "enbl_cs_nofloating_n_right" }, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8770, \ + "enbl_cs_nofloating_p_right" }, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8780, \ + "enbl_cs_vbatldo_right" }, /* Enable of current sense LDO , */ \ + { 0x8800, \ + "volsense_pwm_sel" }, /* Voltage sense PWM source selection control , */ \ + { 0x8810, \ + "volsense_dc_offset" }, /* Voltage sense decimator offset control , */ \ + { 0x9000, \ + "cf_rst_dsp" }, /* Reset , */ \ + { 0x9011, \ + "cf_dmem" }, /* Target memory , */ \ + { 0x9030, \ + "cf_aif" }, /* Auto increment , */ \ + { 0x9040, \ + "cf_int" }, /* Interrupt - auto clear , */ \ + { 0x9050, \ + "cf_cgate_off" }, /* Coolflux clock gating disabling control , */ \ + { 0x9080, \ + "cf_req_cmd" }, /* Firmware event request rpc command , */ \ + { 0x9090, \ + "cf_req_reset" }, /* Firmware event request reset restart , */ \ + { 0x90a0, \ + "cf_req_mips" }, /* Firmware event request short on mips , */ \ + { 0x90b0, \ + "cf_req_mute_ready" }, /* Firmware event request mute sequence ready , */ \ + { 0x90c0, \ + "cf_req_volume_ready" }, /* Firmware event request volume ready , */ \ + { 0x90d0, \ + "cf_req_damage" }, /* Firmware event request speaker damage detected , */ \ + { 0x90e0, \ + "cf_req_calibrate_ready" }, /* Firmware event request calibration completed , */ \ + { 0x90f0, \ + "cf_req_reserved" }, /* Firmware event request reserved , */ \ + { 0x910f, \ + "cf_madd" }, /* Memory address , */ \ + { 0x920f, \ + "cf_mema" }, /* Activate memory access , */ \ + { 0x9307, \ + "cf_err" }, /* Error flags , */ \ + { 0x9387, \ + "cf_ack" }, /* Acknowledge of requests , */ \ + { 0x9380, \ + "cf_ack_cmd" }, /* Firmware event acknowledge rpc command , */ \ + { 0x9390, \ + "cf_ack_reset" }, /* Firmware event acknowledge reset restart , */ \ + { 0x93a0, \ + "cf_ack_mips" }, /* Firmware event acknowledge short on mips , */ \ + { 0x93b0, \ + "cf_ack_mute_ready" }, /* Firmware event acknowledge mute sequence ready , */ \ + { 0x93c0, \ + "cf_ack_volume_ready" }, /* Firmware event acknowledge volume ready , */ \ + { 0x93d0, \ + "cf_ack_damage" }, /* Firmware event acknowledge speaker damage detected, */ \ + { 0x93e0, \ + "cf_ack_calibrate_ready" }, /* Firmware event acknowledge calibration completed , */ \ + { 0x93f0, \ + "cf_ack_reserved" }, /* Firmware event acknowledge reserved , */ \ + { 0x980f, \ + "ivt_addr0_msb" }, /* Coolflux interrupt vector table address0 MSB , */ \ + { 0x990f, \ + "ivt_addr0_lsb" }, /* Coolflux interrupt vector table address0 LSB , */ \ + { 0x9a0f, \ + "ivt_addr1_msb" }, /* Coolflux interrupt vector table address1 MSB , */ \ + { 0x9b0f, \ + "ivt_addr1_lsb" }, /* Coolflux interrupt vector table address1 LSB , */ \ + { 0x9c0f, \ + "ivt_addr2_msb" }, /* Coolflux interrupt vector table address2 MSB , */ \ + { 0x9d0f, \ + "ivt_addr2_lsb" }, /* Coolflux interrupt vector table address2 LSB , */ \ + { 0x9e0f, \ + "ivt_addr3_msb" }, /* Coolflux interrupt vector table address3 MSB , */ \ + { 0x9f0f, \ + "ivt_addr3_lsb" }, /* Coolflux interrupt vector table address3 LSB , */ \ + { 0xa007, \ + "mtpkey1" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0xa107, \ + "mtpkey2" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "key01_locked" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "key02_locked" }, /* Indicates KEY2 is locked , */ \ + { 0xa302, \ + "mtp_man_address_in" }, /* MTP address from I2C register for read/writing mtp in manual single word mode, */ \ + { 0xa330, \ + "man_copy_mtp_to_iic" }, /* Start copying single word from mtp to I2C mtp register, */ \ + { 0xa340, \ + "man_copy_iic_to_mtp" }, /* Start copying single word from I2C mtp register to mtp, */ \ + { 0xa350, \ + "auto_copy_mtp_to_iic" }, /* Start copying all the data from mtp to I2C mtp registers, */ \ + { 0xa360, \ + "auto_copy_iic_to_mtp" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa400, \ + "faim_set_clkws" }, /* Sets the faim controller clock wait state register, */ \ + { 0xa410, \ + "faim_sel_evenrows" }, /* All even rows of the faim are selected, active high, */ \ + { 0xa420, \ + "faim_sel_oddrows" }, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */ \ + { 0xa430, \ + "faim_program_only" }, /* Skip the erase access at wr_faim command (write-program-marginread), */ \ + { 0xa440, \ + "faim_erase_only" }, /* Skip the program access at wr_faim command (write-erase-marginread), */ \ + { 0xa50f, \ + "mtp_man_data_out_msb" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "mtp_man_data_out_lsb" }, /* LSB word of MTP manual read data , */ \ + { 0xa70f, \ + "mtp_man_data_in_msb" }, /* MSB word of write data for MTP manual write , */ \ + { 0xa80f, \ + "mtp_man_data_in_lsb" }, /* LSB word of write data for MTP manual write , */ \ + { 0xb010, \ + "bypass_ocpcounter" }, /* Bypass OCP Counter , */ \ + { 0xb020, \ + "bypass_glitchfilter" }, /* Bypass glitch filter , */ \ + { 0xb030, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0xb040, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0xb050, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0xb060, \ + "bypass_lost_clk" }, /* Bypass lost clock detector , */ \ + { 0xb070, \ + "ctrl_vpalarm" }, /* vpalarm (uvp ovp handling) , */ \ + { 0xb087, \ + "ocp_threshold" }, /* OCP threshold level , */ \ + { 0xb108, \ + "ext_temp" }, /* External temperature (C) , */ \ + { 0xb190, \ + "ext_temp_sel" }, /* Select temp Speaker calibration , */ \ + { 0xc000, \ + "use_direct_ctrls" }, /* Direct control to overrule several functions for testing, */ \ + { 0xc010, \ + "rst_datapath" }, /* Direct control for datapath reset , */ \ + { 0xc020, \ + "rst_cgu" }, /* Direct control for cgu reset , */ \ + { 0xc038, \ + "enbl_ref" }, /* Switch on the analog references, each part of the references can be switched on/off individually, */ \ + { 0xc0d0, \ + "enbl_ringo" }, /* Enable the ring oscillator for test purpose , */ \ + { 0xc0e0, \ + "use_direct_clk_ctrl" }, /* Direct clock control to overrule several functions for testing, */ \ + { 0xc0f0, \ + "use_direct_pll_ctrl" }, /* Direct PLL control to overrule several functions for testing, */ \ + { 0xc100, \ + "enbl_tsense" }, /* Temperature sensor enable control - I2C direct mode, */ \ + { 0xc110, \ + "tsense_hibias" }, /* Bit to set the biasing in temp sensor to high , */ \ + { 0xc120, \ + "enbl_flag_vbg" }, /* Enable flagging of bandgap out of control , */ \ + { 0xc20f, \ + "abist_offset" }, /* Offset control for ABIST testing (two's complement), */ \ + { 0xc300, \ + "bypasslatch" }, /* Bypass latch , */ \ + { 0xc311, \ + "sourcea" }, /* Set OUTA to , */ \ + { 0xc331, \ + "sourceb" }, /* Set OUTB to , */ \ + { 0xc350, \ + "inverta" }, /* Invert pwma test signal , */ \ + { 0xc360, \ + "invertb" }, /* Invert pwmb test signal , */ \ + { 0xc374, \ + "pulselength" }, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */ \ + { 0xc3c0, \ + "tdm_enable_loopback" }, /* TDM loopback test , */ \ + { 0xc3d0, \ + "test_abistfft_enbl" }, /* FFT Coolflux , */ \ + { 0xc3e0, \ + "test_pwr_switch" }, /* Test mode for digital power switches core sw/mem sw/micvdd sw, */ \ + { 0xc400, \ + "bst_bypasslatch" }, /* Bypass latch in boost converter , */ \ + { 0xc411, \ + "bst_source" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0xc430, \ + "bst_invertb" }, /* Invert pwmbst test signal , */ \ + { 0xc444, \ + "bst_pulselength" }, /* Pulse length setting test input for boost converter , */ \ + { 0xc490, \ + "test_bst_ctrlsthv" }, /* Test mode for boost control stage , */ \ + { 0xc4a0, \ + "test_bst_iddq" }, /* IDDQ testing in power stage of boost converter , */ \ + { 0xc4b0, \ + "test_bst_rdson" }, /* RDSON testing - boost power stage , */ \ + { 0xc4c0, \ + "test_bst_cvi" }, /* CVI testing - boost power stage , */ \ + { 0xc4d0, \ + "test_bst_ocp" }, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */ \ + { 0xc4e0, \ + "test_bst_sense" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0xc500, \ + "test_cvi" }, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */ \ + { 0xc510, \ + "test_discrete" }, /* Test function noise measurement , */ \ + { 0xc520, \ + "test_iddq" }, /* Set the power stages in iddq mode for gate stress., */ \ + { 0xc540, \ + "test_rdson" }, /* Analog BIST, switch to enable Rdson measurement , */ \ + { 0xc550, \ + "test_sdelta" }, /* Analog BIST, noise test , */ \ + { 0xc570, \ + "test_enbl_cs" }, /* Enable for digimux mode of current sense , */ \ + { 0xc600, \ + "enbl_pwm_dcc" }, /* Enables direct control of pwm duty cycle for DCDC power stage, */ \ + { 0xc613, \ + "pwm_dcc_cnt" }, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0xc650, \ + "enbl_ldo_stress" }, /* Enable stress of internal supply voltages powerstages, */ \ + { 0xc660, \ + "bypass_diosw_ovp" }, /* Bypass ovp for memory switch diosw , */ \ + { 0xc670, \ + "enbl_powerswitch" }, /* Vddd core power switch control - overrules the manager control, */ \ + { 0xc707, \ + "digimuxa_sel" }, /* DigimuxA input selection control routed to GPIO1 (see Digimux list for details), */ \ + { 0xc787, \ + "digimuxb_sel" }, /* DigimuxB input selection control routed to GPIO2 (see Digimux list for details), */ \ + { 0xc807, \ + "digimuxc_sel" }, /* DigimuxC input selection control routed to GPIO3 (see Digimux list for details), */ \ + { 0xc887, \ + "digimuxd_sel" }, /* DigimuxD input selection control routed to GPIO4 (see Digimux list for details), */ \ + { 0xc901, \ + "dio1_ehs" }, /* Speed/load setting for DIO1 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc921, \ + "dio2_ehs" }, /* Speed/load setting for DIO2 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc941, \ + "gainio_ehs" }, /* Speed/load setting for GAINIO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc961, \ + "pdmo_ehs" }, /* Speed/load setting for PDMO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc981, \ + "int_ehs" }, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc9a1, \ + "tdo_ehs" }, /* Speed/load setting for TDO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc9c0, \ + "hs_mode" }, /* I2C high speed mode control , */ \ + { 0xca00, \ + "enbl_anamux1" }, /* Enable anamux1 , */ \ + { 0xca10, \ + "enbl_anamux2" }, /* Enable anamux2 , */ \ + { 0xca20, \ + "enbl_anamux3" }, /* Enable anamux3 , */ \ + { 0xca30, \ + "enbl_anamux4" }, /* Enable anamux4 , */ \ + { 0xca40, \ + "enbl_anamux5" }, /* Enable anamux5 , */ \ + { 0xca50, \ + "enbl_anamux6" }, /* Enable anamux6 , */ \ + { 0xca60, \ + "enbl_anamux7" }, /* Enable anamux7 , */ \ + { 0xca74, \ + "anamux1" }, /* Anamux selection control - anamux on TEST1 , */ \ + { 0xcb04, \ + "anamux2" }, /* Anamux selection control - anamux on TEST2 , */ \ + { 0xcb54, \ + "anamux3" }, /* Anamux selection control - anamux on TEST3 , */ \ + { 0xcba4, \ + "anamux4" }, /* Anamux selection control - anamux on TEST4 , */ \ + { 0xcc04, \ + "anamux5" }, /* Anamux selection control - anamux on TEST5 , */ \ + { 0xcc54, \ + "anamux6" }, /* Anamux selection control - anamux on TEST6 , */ \ + { 0xcca4, \ + "anamux7" }, /* Anamux selection control - anamux on TEST7 , */ \ + { 0xcd05, \ + "pll_seli" }, /* PLL SELI - I2C direct PLL control mode only , */ \ + { 0xcd64, \ + "pll_selp" }, /* PLL SELP - I2C direct PLL control mode only , */ \ + { 0xcdb3, \ + "pll_selr" }, /* PLL SELR - I2C direct PLL control mode only , */ \ + { 0xcdf0, \ + "pll_frm" }, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */ \ + { 0xce09, \ + "pll_ndec" }, /* PLL NDEC - I2C direct PLL control mode only , */ \ + { 0xcea0, \ + "pll_mdec_msb" }, /* MSB of pll_mdec - I2C direct PLL control mode only, */ \ + { 0xceb0, \ + "enbl_pll" }, /* Enables PLL in I2C direct PLL control mode only , */ \ + { 0xcec0, \ + "enbl_osc" }, /* Enables OSC1M in I2C direct control mode only , */ \ + { 0xced0, \ + "pll_bypass" }, /* PLL bypass control in I2C direct PLL control mode only, */ \ + { 0xcee0, \ + "pll_directi" }, /* PLL directi control in I2C direct PLL control mode only, */ \ + { 0xcef0, \ + "pll_directo" }, /* PLL directo control in I2C direct PLL control mode only, */ \ + { 0xcf0f, \ + "pll_mdec_lsb" }, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */ \ + { 0xd006, \ + "pll_pdec" }, /* PLL PDEC - I2C direct PLL control mode only , */ \ + { 0xd10f, \ + "tsig_freq_lsb" }, /* Internal sinus test generator frequency control , */ \ + { 0xd202, \ + "tsig_freq_msb" }, /* Select internal sinus test generator, frequency control msb bits, */ \ + { 0xd230, \ + "inject_tsig" }, /* Control bit to switch to internal sinus test generator, */ \ + { 0xd243, \ + "tsig_gain_left" }, /* Test signal gain for left channel , */ \ + { 0xd283, \ + "tsig_gain_right" }, /* Test signal gain for right channel , */ \ + { 0xd300, \ + "adc10_reset" }, /* Reset for ADC10 - I2C direct control mode , */ \ + { 0xd311, \ + "adc10_test" }, /* Test mode selection signal for ADC10 - I2C direct control mode, */ \ + { 0xd332, \ + "adc10_sel" }, /* Select the input to convert for ADC10 - I2C direct control mode, */ \ + { 0xd364, \ + "adc10_prog_sample" }, /* ADC10 program sample setting - I2C direct control mode, */ \ + { 0xd3b0, \ + "adc10_enbl" }, /* Enable ADC10 - I2C direct control mode , */ \ + { 0xd3c0, \ + "bypass_lp_vbat" }, /* Bypass control for Low pass filter in batt sensor , */ \ + { 0xd409, \ + "data_adc10_tempbat" }, /* ADC 10 data output data for testing , */ \ + { 0xd506, \ + "ctrl_digtoana_hidden" }, /* Spare digital to analog control bits - Hidden , */ \ + { 0xd570, \ + "enbl_clk_out_of_range" }, /* Clock out of range , */ \ + { 0xf000, \ + "calibration_onetime" }, /* Calibration schedule , */ \ + { 0xf010, \ + "calibr_ron_done" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "calibr_dcdc_api_calibrate" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "calibr_dcdc_delta_sign" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "calibr_dcdc_delta" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "calibr_speaker_info" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf105, \ + "calibr_vout_offset" }, /* DCDC offset calibration 2's complement (key1 protected), */ \ + { 0xf163, \ + "calibr_gain_left" }, /* HW gain module - left channel (2's complement) , */ \ + { 0xf1a5, \ + "calibr_offset_left" }, /* Offset for amplifier, HW gain module - left channel (2's complement), */ \ + { 0xf203, \ + "calibr_gain_right" }, /* HW gain module - right channel (2's complement) , */ \ + { 0xf245, \ + "calibr_offset_right" }, /* Offset for amplifier, HW gain module - right channel (2's complement), */ \ + { 0xf2a3, \ + "calibr_rcvldop_trim" }, /* Trimming of LDO (2.7V) , */ \ + { 0xf307, \ + "calibr_gain_cs_left" }, /* Current sense gain - left channel (signed two's complement format), */ \ + { 0xf387, \ + "calibr_gain_cs_right" }, /* Current sense gain - right channel (signed two's complement format), */ \ + { 0xf40f, \ + "calibr_R25C_L" }, /* Ron resistance of left channel speaker coil , */ \ + { 0xf50f, \ + "calibr_R25C_R" }, /* Ron resistance of right channel speaker coil , */ \ + { 0xf606, \ + "ctrl_offset_a_left" }, /* Offset of left amplifier level shifter A , */ \ + { 0xf686, \ + "ctrl_offset_b_left" }, /* Offset of left amplifier level shifter B , */ \ + { 0xf706, \ + "ctrl_offset_a_right" }, /* Offset of right amplifier level shifter A , */ \ + { 0xf786, \ + "ctrl_offset_b_right" }, /* Offset of right amplifier level shifter B , */ \ + { 0xf806, \ + "htol_iic_addr" }, /* 7-bit I2C address to be used during HTOL testing , */ \ + { 0xf870, \ + "htol_iic_addr_en" }, /* HTOL I2C address enable control , */ \ + { 0xf884, \ + "calibr_temp_offset" }, /* Temperature offset 2's compliment (key1 protected), */ \ + { 0xf8d2, \ + "calibr_temp_gain" }, /* Temperature gain 2's compliment (key1 protected) , */ \ + { 0xf900, \ + "mtp_lock_dcdcoff_mode" }, /* Disable function dcdcoff_mode , */ \ + { 0xf910, \ + "mtp_lock_enbl_coolflux" }, /* Disable function enbl_coolflux , */ \ + { 0xf920, \ + "mtp_lock_bypass_clipper" }, /* Disable function bypass_clipper , */ \ + { 0xf930, \ + "mtp_lock_max_dcdc_voltage" }, /* Disable programming of max dcdc boost voltage , */ \ + { 0xf943, \ + "calibr_vbg_trim" }, /* Bandgap trimming control , */ \ + { 0xf987, \ + "type_bits_fw" }, /* MTP-control FW - See Firmware I2C API document for details, */ \ + { 0xfa0f, \ + "mtpdataA" }, /* MTPdataA (key1 protected) , */ \ + { 0xfb0f, \ + "mtpdataB" }, /* MTPdataB (key1 protected) , */ \ + { 0xfc0f, \ + "mtpdataC" }, /* MTPdataC (key1 protected) , */ \ + { 0xfd0f, \ + "mtpdataD" }, /* MTPdataD (key1 protected) , */ \ + { 0xfe0f, \ + "mtpdataE" }, /* MTPdataE (key1 protected) , */ \ + { 0xff05, \ + "calibr_osc_delta_ndiv" }, /* Calibration data for OSC1M, signed number representation, */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +enum tfa2_irq { + tfa2_irq_stvdds = 0, + tfa2_irq_stplls = 1, + tfa2_irq_stotds = 2, + tfa2_irq_stovds = 3, + tfa2_irq_stuvds = 4, + tfa2_irq_stclks = 5, + tfa2_irq_stmtpb = 6, + tfa2_irq_stnoclk = 7, + tfa2_irq_stspks = 8, + tfa2_irq_stacs = 9, + tfa2_irq_stsws = 10, + tfa2_irq_stwds = 11, + tfa2_irq_stamps = 12, + tfa2_irq_starefs = 13, + tfa2_irq_stadccr = 14, + tfa2_irq_stbodnok = 15, + tfa2_irq_stbstcu = 16, + tfa2_irq_stbsthi = 17, + tfa2_irq_stbstoc = 18, + tfa2_irq_stbstpkcur = 19, + tfa2_irq_stbstvc = 20, + tfa2_irq_stbst86 = 21, + tfa2_irq_stbst93 = 22, + tfa2_irq_strcvld = 23, + tfa2_irq_stocpl = 24, + tfa2_irq_stocpr = 25, + tfa2_irq_stmwsrc = 26, + tfa2_irq_stmwcfc = 27, + tfa2_irq_stmwsmu = 28, + tfa2_irq_stcfmer = 29, + tfa2_irq_stcfmac = 30, + tfa2_irq_stclkoor = 31, + tfa2_irq_sttdmer = 32, + tfa2_irq_stclpl = 33, + tfa2_irq_stclpr = 34, + tfa2_irq_stocpm = 35, + tfa2_irq_max = 36, + tfa2_irq_all = -1 /* all irqs */ +}; + +#define TFA2_IRQ_NAMETABLE \ + static tfaIrqName_t Tfa2IrqNames[] = { \ + { 0, "STVDDS" }, { 1, "STPLLS" }, { 2, "STOTDS" }, \ + { 3, "STOVDS" }, { 4, "STUVDS" }, { 5, "STCLKS" }, \ + { 6, "STMTPB" }, { 7, "STNOCLK" }, { 8, "STSPKS" }, \ + { 9, "STACS" }, { 10, "STSWS" }, { 11, "STWDS" }, \ + { 12, "STAMPS" }, { 13, "STAREFS" }, { 14, "STADCCR" }, \ + { 15, "STBODNOK" }, { 16, "STBSTCU" }, { 17, "STBSTHI" }, \ + { 18, "STBSTOC" }, { 19, "STBSTPKCUR" }, { 20, "STBSTVC" }, \ + { 21, "STBST86" }, { 22, "STBST93" }, { 23, "STRCVLD" }, \ + { 24, "STOCPL" }, { 25, "STOCPR" }, { 26, "STMWSRC" }, \ + { 27, "STMWCFC" }, { 28, "STMWSMU" }, { 29, "STCFMER" }, \ + { 30, "STCFMAC" }, { 31, "STCLKOOR" }, { 32, "STTDMER" }, \ + { 33, "STCLPL" }, { 34, "STCLPR" }, { 35, "STOCPM" }, \ + { 36, "36" }, \ + }; diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9872_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9872_tfafieldnames.h new file mode 100644 index 000000000000..c3615273e3ed --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9872_tfafieldnames.h @@ -0,0 +1,2312 @@ +/** Filename: Tfa9872_TfaFieldnames.h + * This file was generated automatically on 10/11/16 at 10:19:27. + * Source file: TFA9872N1B2_DefaultI2CSettings -v16.xlsx + */ + +#ifndef _TFA9872_TFAFIELDNAMES_H +#define _TFA9872_TFAFIELDNAMES_H + +#define TFA9872_I2CVERSION_N1A 26 +#define TFA9872_I2CVERSION_N1B 29 +#define TFA9872_I2CVERSION_N1B2 21 + +typedef enum nxpTfa9872BfEnumList { + TFA9872_BF_PWDN = + 0x0000, /*!< Powerdown selection */ + TFA9872_BF_I2CR = + 0x0010, /*!< I2C Reset - Auto clear */ + TFA9872_BF_AMPE = + 0x0030, /*!< Activate Amplifier */ + TFA9872_BF_DCA = + 0x0040, /*!< Activate DC-to-DC converter */ + TFA9872_BF_INTP = + 0x0071, /*!< Interrupt config */ + TFA9872_BF_BYPOCP = + 0x00b0, /*!< Bypass OCP */ + TFA9872_BF_TSTOCP = + 0x00c0, /*!< OCP testing control */ + TFA9872_BF_MANSCONF = + 0x0120, /*!< I2C configured */ + TFA9872_BF_MANAOOSC = + 0x0140, /*!< Internal osc off at PWDN */ + TFA9872_BF_MUTETO = + 0x01d0, /*!< Time out SB mute sequence */ + TFA9872_BF_RCVNS = + 0x01e0, /*!< Noise shaper selection */ + TFA9872_BF_AUDFS = + 0x0203, /*!< Sample rate (fs) */ + TFA9872_BF_INPLEV = + 0x0240, /*!< TDM output attenuation */ + TFA9872_BF_FRACTDEL = + 0x0255, /*!< V/I Fractional delay */ + TFA9872_BF_BYPHVBF = + 0x02b0, /*!< Bypass HVBAT filter */ + TFA9872_BF_REV = + 0x030f, /*!< Revision info */ + TFA9872_BF_REFCKEXT = + 0x0401, /*!< PLL external ref clock */ + TFA9872_BF_REFCKSEL = + 0x0420, /*!< PLL internal ref clock */ + TFA9872_BF_SSE = + 0x0510, /*!< Enable speaker path */ + TFA9872_BF_VSE = + 0x0530, /*!< Voltage sense */ + TFA9872_BF_CSE = + 0x0550, /*!< Current sense */ + TFA9872_BF_SSPDME = + 0x0560, /*!< Sub-system PDM */ + TFA9872_BF_PGAE = + 0x0580, /*!< Enable PGA chop clock */ + TFA9872_BF_SSTDME = + 0x0590, /*!< Sub-system TDM */ + TFA9872_BF_SSPBSTE = + 0x05a0, /*!< Sub-system boost */ + TFA9872_BF_SSADCE = + 0x05b0, /*!< Sub-system ADC */ + TFA9872_BF_SSFAIME = + 0x05c0, /*!< Sub-system FAIM */ + TFA9872_BF_STGAIN = + 0x0d18, /*!< Side tone gain */ + TFA9872_BF_STSMUTE = + 0x0da0, /*!< Side tone soft mute */ + TFA9872_BF_ST1C = + 0x0db0, /*!< side tone one s complement */ + TFA9872_BF_VDDS = + 0x1000, /*!< POR */ + TFA9872_BF_PLLS = + 0x1010, /*!< PLL lock */ + TFA9872_BF_OTDS = + 0x1020, /*!< OTP alarm */ + TFA9872_BF_OVDS = + 0x1030, /*!< OVP alarm */ + TFA9872_BF_UVDS = + 0x1040, /*!< UVP alarm */ + TFA9872_BF_CLKS = + 0x1050, /*!< Clocks stable */ + TFA9872_BF_MTPB = + 0x1060, /*!< MTP busy */ + TFA9872_BF_NOCLK = + 0x1070, /*!< Lost clock */ + TFA9872_BF_SWS = + 0x10a0, /*!< Amplifier engage */ + TFA9872_BF_AMPS = + 0x10c0, /*!< Amplifier enable */ + TFA9872_BF_AREFS = + 0x10d0, /*!< References enable */ + TFA9872_BF_ADCCR = + 0x10e0, /*!< Control ADC */ + TFA9872_BF_DCIL = + 0x1100, /*!< DCDC current limiting */ + TFA9872_BF_DCDCA = + 0x1110, /*!< DCDC active */ + TFA9872_BF_DCOCPOK = + 0x1120, /*!< DCDC OCP nmos */ + TFA9872_BF_DCHVBAT = + 0x1140, /*!< DCDC level 1x */ + TFA9872_BF_DCH114 = + 0x1150, /*!< DCDC level 1.14x */ + TFA9872_BF_DCH107 = + 0x1160, /*!< DCDC level 1.07x */ + TFA9872_BF_STMUTEB = + 0x1170, /*!< side tone (un)mute busy */ + TFA9872_BF_STMUTE = + 0x1180, /*!< side tone mute state */ + TFA9872_BF_TDMLUTER = + 0x1190, /*!< TDM LUT error */ + TFA9872_BF_TDMSTAT = + 0x11a2, /*!< TDM status bits */ + TFA9872_BF_TDMERR = + 0x11d0, /*!< TDM error */ + TFA9872_BF_OCPOAP = + 0x1300, /*!< OCPOK pmos A */ + TFA9872_BF_OCPOAN = + 0x1310, /*!< OCPOK nmos A */ + TFA9872_BF_OCPOBP = + 0x1320, /*!< OCPOK pmos B */ + TFA9872_BF_OCPOBN = + 0x1330, /*!< OCPOK nmos B */ + TFA9872_BF_CLIPAH = + 0x1340, /*!< Clipping A to Vddp */ + TFA9872_BF_CLIPAL = + 0x1350, /*!< Clipping A to gnd */ + TFA9872_BF_CLIPBH = + 0x1360, /*!< Clipping B to Vddp */ + TFA9872_BF_CLIPBL = + 0x1370, /*!< Clipping B to gnd */ + TFA9872_BF_OCDS = + 0x1380, /*!< OCP amplifier */ + TFA9872_BF_CLIPS = + 0x1390, /*!< Amplifier clipping */ + TFA9872_BF_OCPOKMC = + 0x13a0, /*!< OCPOK MICVDD */ + TFA9872_BF_MANALARM = + 0x13b0, /*!< Alarm state */ + TFA9872_BF_MANWAIT1 = + 0x13c0, /*!< Wait HW I2C settings */ + TFA9872_BF_MANMUTE = + 0x13e0, /*!< Audio mute sequence */ + TFA9872_BF_MANOPER = + 0x13f0, /*!< Operating state */ + TFA9872_BF_CLKOOR = + 0x1420, /*!< External clock status */ + TFA9872_BF_MANSTATE = + 0x1433, /*!< Device manager status */ + TFA9872_BF_DCMODE = + 0x1471, /*!< DCDC mode status bits */ + TFA9872_BF_BATS = + 0x1509, /*!< Battery voltage (V) */ + TFA9872_BF_TEMPS = + 0x1608, /*!< IC Temperature (C) */ + TFA9872_BF_VDDPS = + 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/9.5 V) */ + TFA9872_BF_TDME = + 0x2040, /*!< Enable interface */ + TFA9872_BF_TDMMODE = + 0x2050, /*!< Slave/master */ + TFA9872_BF_TDMCLINV = + 0x2060, /*!< Reception data to BCK clock */ + TFA9872_BF_TDMFSLN = + 0x2073, /*!< FS length (master mode only) */ + TFA9872_BF_TDMFSPOL = + 0x20b0, /*!< FS polarity */ + TFA9872_BF_TDMNBCK = + 0x20c3, /*!< N-BCK's in FS */ + TFA9872_BF_TDMSLOTS = + 0x2103, /*!< N-slots in Frame */ + TFA9872_BF_TDMSLLN = + 0x2144, /*!< N-bits in slot */ + TFA9872_BF_TDMBRMG = + 0x2194, /*!< N-bits remaining */ + TFA9872_BF_TDMDEL = + 0x21e0, /*!< data delay to FS */ + TFA9872_BF_TDMADJ = + 0x21f0, /*!< data adjustment */ + TFA9872_BF_TDMOOMP = + 0x2201, /*!< Received audio compression */ + TFA9872_BF_TDMSSIZE = + 0x2224, /*!< Sample size per slot */ + TFA9872_BF_TDMTXDFO = + 0x2271, /*!< Format unused bits */ + TFA9872_BF_TDMTXUS0 = + 0x2291, /*!< Format unused slots DATAO */ + TFA9872_BF_TDMSPKE = + 0x2300, /*!< Control audio tdm channel in 0 (spkr + dcdc) */ + TFA9872_BF_TDMDCE = + 0x2310, /*!< Control audio tdm channel in 1 (dcdc) */ + TFA9872_BF_TDMCSE = + 0x2330, /*!< current sense vbat temperature and vddp feedback */ + TFA9872_BF_TDMVSE = + 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */ + TFA9872_BF_TDMSPKS = + 0x2603, /*!< tdm slot for sink 0 (speaker + dcdc) */ + TFA9872_BF_TDMDCS = + 0x2643, /*!< tdm slot for sink 1 (dcdc) */ + TFA9872_BF_TDMCSS = + 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */ + TFA9872_BF_TDMVSS = + 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */ + TFA9872_BF_PDMSTSEL = + 0x3111, /*!< Side tone input */ + TFA9872_BF_ISTVDDS = + 0x4000, /*!< Status POR */ + TFA9872_BF_ISTPLLS = + 0x4010, /*!< Status PLL lock */ + TFA9872_BF_ISTOTDS = + 0x4020, /*!< Status OTP alarm */ + TFA9872_BF_ISTOVDS = + 0x4030, /*!< Status OVP alarm */ + TFA9872_BF_ISTUVDS = + 0x4040, /*!< Status UVP alarm */ + TFA9872_BF_ISTCLKS = + 0x4050, /*!< Status clocks stable */ + TFA9872_BF_ISTMTPB = + 0x4060, /*!< Status MTP busy */ + TFA9872_BF_ISTNOCLK = + 0x4070, /*!< Status lost clock */ + TFA9872_BF_ISTSWS = + 0x40a0, /*!< Status amplifier engage */ + TFA9872_BF_ISTAMPS = + 0x40c0, /*!< Status amplifier enable */ + TFA9872_BF_ISTAREFS = + 0x40d0, /*!< Status Ref enable */ + TFA9872_BF_ISTADCCR = + 0x40e0, /*!< Status Control ADC */ + TFA9872_BF_ISTBSTCU = + 0x4100, /*!< Status DCDC current limiting */ + TFA9872_BF_ISTBSTHI = + 0x4110, /*!< Status DCDC active */ + TFA9872_BF_ISTBSTOC = + 0x4120, /*!< Status DCDC OCP */ + TFA9872_BF_ISTBSTPKCUR = + 0x4130, /*!< Status bst peakcur */ + TFA9872_BF_ISTBSTVC = + 0x4140, /*!< Status DCDC level 1x */ + TFA9872_BF_ISTBST86 = + 0x4150, /*!< Status DCDC level 1.14x */ + TFA9872_BF_ISTBST93 = + 0x4160, /*!< Status DCDC level 1.07x */ + TFA9872_BF_ISTOCPR = + 0x4190, /*!< Status ocp alarm */ + TFA9872_BF_ISTMWSRC = + 0x41a0, /*!< Status Waits HW I2C settings */ + TFA9872_BF_ISTMWSMU = + 0x41c0, /*!< Status Audio mute sequence */ + TFA9872_BF_ISTCLKOOR = + 0x41f0, /*!< Status flag_clk_out_of_range */ + TFA9872_BF_ISTTDMER = + 0x4200, /*!< Status tdm error */ + TFA9872_BF_ISTCLPR = + 0x4220, /*!< Status clip */ + TFA9872_BF_ISTLP0 = + 0x4240, /*!< Status low power mode0 */ + TFA9872_BF_ISTLP1 = + 0x4250, /*!< Status low power mode1 */ + TFA9872_BF_ISTLA = + 0x4260, /*!< Status low noise detection */ + TFA9872_BF_ISTVDDPH = + 0x4270, /*!< Status VDDP greater than VBAT */ + TFA9872_BF_ICLVDDS = + 0x4400, /*!< Clear POR */ + TFA9872_BF_ICLPLLS = + 0x4410, /*!< Clear PLL lock */ + TFA9872_BF_ICLOTDS = + 0x4420, /*!< Clear OTP alarm */ + TFA9872_BF_ICLOVDS = + 0x4430, /*!< Clear OVP alarm */ + TFA9872_BF_ICLUVDS = + 0x4440, /*!< Clear UVP alarm */ + TFA9872_BF_ICLCLKS = + 0x4450, /*!< Clear clocks stable */ + TFA9872_BF_ICLMTPB = + 0x4460, /*!< Clear mtp busy */ + TFA9872_BF_ICLNOCLK = + 0x4470, /*!< Clear lost clk */ + TFA9872_BF_ICLSWS = + 0x44a0, /*!< Clear amplifier engage */ + TFA9872_BF_ICLAMPS = + 0x44c0, /*!< Clear enbl amp */ + TFA9872_BF_ICLAREFS = + 0x44d0, /*!< Clear ref enable */ + TFA9872_BF_ICLADCCR = + 0x44e0, /*!< Clear control ADC */ + TFA9872_BF_ICLBSTCU = + 0x4500, /*!< Clear DCDC current limiting */ + TFA9872_BF_ICLBSTHI = + 0x4510, /*!< Clear DCDC active */ + TFA9872_BF_ICLBSTOC = + 0x4520, /*!< Clear DCDC OCP */ + TFA9872_BF_ICLBSTPC = + 0x4530, /*!< Clear bst peakcur */ + TFA9872_BF_ICLBSTVC = + 0x4540, /*!< Clear DCDC level 1x */ + TFA9872_BF_ICLBST86 = + 0x4550, /*!< Clear DCDC level 1.14x */ + TFA9872_BF_ICLBST93 = + 0x4560, /*!< Clear DCDC level 1.07x */ + TFA9872_BF_ICLOCPR = + 0x4590, /*!< Clear ocp alarm */ + TFA9872_BF_ICLMWSRC = + 0x45a0, /*!< Clear wait HW I2C settings */ + TFA9872_BF_ICLMWSMU = + 0x45c0, /*!< Clear audio mute sequence */ + TFA9872_BF_ICLCLKOOR = + 0x45f0, /*!< Clear flag_clk_out_of_range */ + TFA9872_BF_ICLTDMER = + 0x4600, /*!< Clear tdm error */ + TFA9872_BF_ICLCLPR = + 0x4620, /*!< Clear clip */ + TFA9872_BF_ICLLP0 = + 0x4640, /*!< Clear low power mode0 */ + TFA9872_BF_ICLLP1 = + 0x4650, /*!< Clear low power mode1 */ + TFA9872_BF_ICLLA = + 0x4660, /*!< Clear low noise detection */ + TFA9872_BF_ICLVDDPH = + 0x4670, /*!< Clear VDDP greater then VBAT */ + TFA9872_BF_IEVDDS = + 0x4800, /*!< Enable por */ + TFA9872_BF_IEPLLS = + 0x4810, /*!< Enable pll lock */ + TFA9872_BF_IEOTDS = + 0x4820, /*!< Enable OTP alarm */ + TFA9872_BF_IEOVDS = + 0x4830, /*!< Enable OVP alarm */ + TFA9872_BF_IEUVDS = + 0x4840, /*!< Enable UVP alarm */ + TFA9872_BF_IECLKS = + 0x4850, /*!< Enable clocks stable */ + TFA9872_BF_IEMTPB = + 0x4860, /*!< Enable mtp busy */ + TFA9872_BF_IENOCLK = + 0x4870, /*!< Enable lost clk */ + TFA9872_BF_IESWS = + 0x48a0, /*!< Enable amplifier engage */ + TFA9872_BF_IEAMPS = + 0x48c0, /*!< Enable enbl amp */ + TFA9872_BF_IEAREFS = + 0x48d0, /*!< Enable ref enable */ + TFA9872_BF_IEADCCR = + 0x48e0, /*!< Enable Control ADC */ + TFA9872_BF_IEBSTCU = + 0x4900, /*!< Enable DCDC current limiting */ + TFA9872_BF_IEBSTHI = + 0x4910, /*!< Enable DCDC active */ + TFA9872_BF_IEBSTOC = + 0x4920, /*!< Enable DCDC OCP */ + TFA9872_BF_IEBSTPC = + 0x4930, /*!< Enable bst peakcur */ + TFA9872_BF_IEBSTVC = + 0x4940, /*!< Enable DCDC level 1x */ + TFA9872_BF_IEBST86 = + 0x4950, /*!< Enable DCDC level 1.14x */ + TFA9872_BF_IEBST93 = + 0x4960, /*!< Enable DCDC level 1.07x */ + TFA9872_BF_IEOCPR = + 0x4990, /*!< Enable ocp alarm */ + TFA9872_BF_IEMWSRC = + 0x49a0, /*!< Enable waits HW I2C settings */ + TFA9872_BF_IEMWSMU = + 0x49c0, /*!< Enable man Audio mute sequence */ + TFA9872_BF_IECLKOOR = + 0x49f0, /*!< Enable flag_clk_out_of_range */ + TFA9872_BF_IETDMER = + 0x4a00, /*!< Enable tdm error */ + TFA9872_BF_IECLPR = + 0x4a20, /*!< Enable clip */ + TFA9872_BF_IELP0 = + 0x4a40, /*!< Enable low power mode0 */ + TFA9872_BF_IELP1 = + 0x4a50, /*!< Enable low power mode1 */ + TFA9872_BF_IELA = + 0x4a60, /*!< Enable low noise detection */ + TFA9872_BF_IEVDDPH = + 0x4a70, /*!< Enable VDDP greater tehn VBAT */ + TFA9872_BF_IPOVDDS = + 0x4c00, /*!< Polarity por */ + TFA9872_BF_IPOPLLS = + 0x4c10, /*!< Polarity pll lock */ + TFA9872_BF_IPOOTDS = + 0x4c20, /*!< Polarity OTP alarm */ + TFA9872_BF_IPOOVDS = + 0x4c30, /*!< Polarity OVP alarm */ + TFA9872_BF_IPOUVDS = + 0x4c40, /*!< Polarity UVP alarm */ + TFA9872_BF_IPOCLKS = + 0x4c50, /*!< Polarity clocks stable */ + TFA9872_BF_IPOMTPB = + 0x4c60, /*!< Polarity mtp busy */ + TFA9872_BF_IPONOCLK = + 0x4c70, /*!< Polarity lost clk */ + TFA9872_BF_IPOSWS = + 0x4ca0, /*!< Polarity amplifier engage */ + TFA9872_BF_IPOAMPS = + 0x4cc0, /*!< Polarity enbl amp */ + TFA9872_BF_IPOAREFS = + 0x4cd0, /*!< Polarity ref enable */ + TFA9872_BF_IPOADCCR = + 0x4ce0, /*!< Polarity Control ADC */ + TFA9872_BF_IPOBSTCU = + 0x4d00, /*!< Polarity DCDC current limiting */ + TFA9872_BF_IPOBSTHI = + 0x4d10, /*!< Polarity DCDC active */ + TFA9872_BF_IPOBSTOC = + 0x4d20, /*!< Polarity DCDC OCP */ + TFA9872_BF_IPOBSTPC = + 0x4d30, /*!< Polarity bst peakcur */ + TFA9872_BF_IPOBSTVC = + 0x4d40, /*!< Polarity DCDC level 1x */ + TFA9872_BF_IPOBST86 = + 0x4d50, /*!< Polarity DCDC level 1.14x */ + TFA9872_BF_IPOBST93 = + 0x4d60, /*!< Polarity DCDC level 1.07x */ + TFA9872_BF_IPOOCPR = + 0x4d90, /*!< Polarity ocp alarm */ + TFA9872_BF_IPOMWSRC = + 0x4da0, /*!< Polarity waits HW I2C settings */ + TFA9872_BF_IPOMWSMU = + 0x4dc0, /*!< Polarity man audio mute sequence */ + TFA9872_BF_IPCLKOOR = + 0x4df0, /*!< Polarity flag_clk_out_of_range */ + TFA9872_BF_IPOTDMER = + 0x4e00, /*!< Polarity tdm error */ + TFA9872_BF_IPOCLPR = + 0x4e20, /*!< Polarity clip right */ + TFA9872_BF_IPOLP0 = + 0x4e40, /*!< Polarity low power mode0 */ + TFA9872_BF_IPOLP1 = + 0x4e50, /*!< Polarity low power mode1 */ + TFA9872_BF_IPOLA = + 0x4e60, /*!< Polarity low noise mode */ + TFA9872_BF_IPOVDDPH = + 0x4e70, /*!< Polarity VDDP greater than VBAT */ + TFA9872_BF_BSSCR = + 0x5001, /*!< Battery Safeguard attack time */ + TFA9872_BF_BSST = + 0x5023, /*!< Battery Safeguard threshold voltage level */ + TFA9872_BF_BSSRL = + 0x5061, /*!< Battery Safeguard maximum reduction */ + TFA9872_BF_BSSR = + 0x50e0, /*!< Battery voltage read out */ + TFA9872_BF_BSSBY = + 0x50f0, /*!< Bypass battery safeguard */ + TFA9872_BF_BSSS = + 0x5100, /*!< Vbat prot steepness */ + TFA9872_BF_INTSMUTE = + 0x5110, /*!< Soft mute HW */ + TFA9872_BF_HPFBYP = + 0x5150, /*!< Bypass HPF */ + TFA9872_BF_DPSA = + 0x5170, /*!< Enable DPSA */ + TFA9872_BF_CLIPCTRL = + 0x5222, /*!< Clip control setting */ + TFA9872_BF_AMPGAIN = + 0x5257, /*!< Amplifier gain */ + TFA9872_BF_SLOPEE = + 0x52d0, /*!< Enables slope control */ + TFA9872_BF_SLOPESET = + 0x52e0, /*!< Slope speed setting (bin. coded) */ + TFA9872_BF_PGAGAIN = + 0x6081, /*!< PGA gain selection */ + TFA9872_BF_PGALPE = + 0x60b0, /*!< Lowpass enable */ + TFA9872_BF_LPM0BYP = + 0x6110, /*!< bypass low power idle mode */ + TFA9872_BF_TDMDCG = + 0x6123, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */ + TFA9872_BF_TDMSPKG = + 0x6163, /*!< Total gain depending on INPLEV setting (channel 0) */ + TFA9872_BF_STIDLEEN = + 0x61b0, /*!< enable idle feature for channel 1 */ + TFA9872_BF_LNMODE = + 0x62e1, /*!< ctrl select mode */ + TFA9872_BF_LPM1MODE = + 0x64e1, /*!< low power mode control */ + TFA9872_BF_LPM1DIS = + 0x65c0, /*!< low power mode1 detector control */ + TFA9872_BF_TDMSRCMAP = + 0x6801, /*!< tdm source mapping */ + TFA9872_BF_TDMSRCAS = + 0x6821, /*!< Sensed value A */ + TFA9872_BF_TDMSRCBS = + 0x6841, /*!< Sensed value B */ + TFA9872_BF_ANCSEL = + 0x6881, /*!< anc input */ + TFA9872_BF_ANC1C = + 0x68a0, /*!< ANC one s complement */ + TFA9872_BF_SAMMODE = + 0x6901, /*!< sam enable */ + TFA9872_BF_SAMSEL = + 0x6920, /*!< sam source */ + TFA9872_BF_PDMOSELH = + 0x6931, /*!< pdm out value when pdm_clk is higth */ + TFA9872_BF_PDMOSELL = + 0x6951, /*!< pdm out value when pdm_clk is low */ + TFA9872_BF_SAMOSEL = + 0x6970, /*!< ram output on mode sam and audio */ + TFA9872_BF_LP0 = + 0x6e00, /*!< low power mode 0 detection */ + TFA9872_BF_LP1 = + 0x6e10, /*!< low power mode 1 detection */ + TFA9872_BF_LA = + 0x6e20, /*!< low amplitude detection */ + TFA9872_BF_VDDPH = + 0x6e30, /*!< vddp greater than vbat */ + TFA9872_BF_DELCURCOMP = + 0x6f02, /*!< delay to allign compensation signal with current sense signal */ + TFA9872_BF_SIGCURCOMP = + 0x6f40, /*!< polarity of compensation for current sense */ + TFA9872_BF_ENCURCOMP = + 0x6f50, /*!< enable current sense compensation */ + TFA9872_BF_SELCLPPWM = + 0x6f60, /*!< Select pwm clip flag */ + TFA9872_BF_LVLCLPPWM = + 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */ + TFA9872_BF_DCVOS = + 0x7002, /*!< Second boost voltage level */ + TFA9872_BF_DCMCC = + 0x7033, /*!< Max coil current */ + TFA9872_BF_DCCV = + 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */ + TFA9872_BF_DCIE = + 0x7090, /*!< Adaptive boost mode */ + TFA9872_BF_DCSR = + 0x70a0, /*!< Soft ramp up/down */ + TFA9872_BF_DCDIS = + 0x70e0, /*!< DCDC on/off */ + TFA9872_BF_DCPWM = + 0x70f0, /*!< DCDC PWM only mode */ + TFA9872_BF_DCVOF = + 0x7402, /*!< 1st boost voltage level */ + TFA9872_BF_DCTRACK = + 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */ + TFA9872_BF_DCTRIP = + 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */ + TFA9872_BF_DCHOLD = + 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */ + TFA9872_BF_DCTRIP2 = + 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */ + TFA9872_BF_DCTRIPT = + 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */ + TFA9872_BF_MTPK = + 0xa107, /*!< MTP KEY2 register */ + TFA9872_BF_KEY1LOCKED = + 0xa200, /*!< Indicates KEY1 is locked */ + TFA9872_BF_KEY2LOCKED = + 0xa210, /*!< Indicates KEY2 is locked */ + TFA9872_BF_CMTPI = + 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers */ + TFA9872_BF_CIMTP = + 0xa360, /*!< Start copying data from I2C mtp registers to mtp */ + TFA9872_BF_MTPRDMSB = + 0xa50f, /*!< MSB word of MTP manual read data */ + TFA9872_BF_MTPRDLSB = + 0xa60f, /*!< LSB word of MTP manual read data */ + TFA9872_BF_EXTTS = + 0xb108, /*!< External temperature (C) */ + TFA9872_BF_TROS = + 0xb190, /*!< Select temp Speaker calibration */ + TFA9872_BF_SWPROFIL = + 0xee0f, /*!< Software profile data */ + TFA9872_BF_SWVSTEP = + 0xef0f, /*!< Software vstep information */ + TFA9872_BF_MTPOTC = + 0xf000, /*!< Calibration schedule */ + TFA9872_BF_MTPEX = + 0xf010, /*!< Calibration Ron executed */ + TFA9872_BF_DCMCCAPI = + 0xf020, /*!< Calibration current limit DCDC */ + TFA9872_BF_DCMCCSB = + 0xf030, /*!< Sign bit for delta calibration current limit DCDC */ + TFA9872_BF_USERDEF = + 0xf042, /*!< Calibration delta current limit DCDC */ + TFA9872_BF_CUSTINFO = + 0xf078, /*!< Reserved space for allowing customer to store speaker information */ + TFA9872_BF_R25C = + 0xf50f, /*!< Ron resistance of speaker coil */ +} nxpTfa9872BfEnumList_t; +#define TFA9872_NAMETABLE \ + static tfaBfName_t Tfa9872DatasheetNames[] = { \ + { 0x0, \ + "PWDN" }, /* Powerdown selection , */ \ + { 0x10, \ + "I2CR" }, /* I2C Reset - Auto clear , */ \ + { 0x30, \ + "AMPE" }, /* Activate Amplifier , */ \ + { 0x40, \ + "DCA" }, /* Activate DC-to-DC converter , */ \ + { 0x71, \ + "INTP" }, /* Interrupt config , */ \ + { 0xb0, \ + "BYPOCP" }, /* Bypass OCP , */ \ + { 0xc0, \ + "TSTOCP" }, /* OCP testing control , */ \ + { 0x120, \ + "MANSCONF" }, /* I2C configured , */ \ + { 0x140, \ + "MANAOOSC" }, /* Internal osc off at PWDN , */ \ + { 0x1d0, \ + "MUTETO" }, /* Time out SB mute sequence , */ \ + { 0x1e0, \ + "RCVNS" }, /* Noise shaper selection , */ \ + { 0x203, \ + "AUDFS" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "INPLEV" }, /* TDM output attenuation , */ \ + { 0x255, \ + "FRACTDEL" }, /* V/I Fractional delay , */ \ + { 0x2b0, \ + "BYPHVBF" }, /* Bypass HVBAT filter , */ \ + { 0x30f, \ + "REV" }, /* Revision info , */ \ + { 0x401, \ + "REFCKEXT" }, /* PLL external ref clock , */ \ + { 0x420, \ + "REFCKSEL" }, /* PLL internal ref clock , */ \ + { 0x510, \ + "SSE" }, /* Enable speaker path , */ \ + { 0x530, \ + "VSE" }, /* Voltage sense , */ \ + { 0x550, \ + "CSE" }, /* Current sense , */ \ + { 0x560, \ + "SSPDME" }, /* Sub-system PDM , */ \ + { 0x580, \ + "PGAE" }, /* Enable PGA chop clock , */ \ + { 0x590, \ + "SSTDME" }, /* Sub-system TDM , */ \ + { 0x5a0, \ + "SSPBSTE" }, /* Sub-system boost , */ \ + { 0x5b0, \ + "SSADCE" }, /* Sub-system ADC , */ \ + { 0x5c0, \ + "SSFAIME" }, /* Sub-system FAIM , */ \ + { 0xd18, \ + "STGAIN" }, /* Side tone gain , */ \ + { 0xda0, \ + "STSMUTE" }, /* Side tone soft mute , */ \ + { 0xdb0, \ + "ST1C" }, /* side tone one s complement , */ \ + { 0x1000, \ + "VDDS" }, /* POR , */ \ + { 0x1010, \ + "PLLS" }, /* PLL lock , */ \ + { 0x1020, \ + "OTDS" }, /* OTP alarm , */ \ + { 0x1030, \ + "OVDS" }, /* OVP alarm , */ \ + { 0x1040, \ + "UVDS" }, /* UVP alarm , */ \ + { 0x1050, \ + "CLKS" }, /* Clocks stable , */ \ + { 0x1060, \ + "MTPB" }, /* MTP busy , */ \ + { 0x1070, \ + "NOCLK" }, /* Lost clock , */ \ + { 0x10a0, \ + "SWS" }, /* Amplifier engage , */ \ + { 0x10c0, \ + "AMPS" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "AREFS" }, /* References enable , */ \ + { 0x10e0, \ + "ADCCR" }, /* Control ADC , */ \ + { 0x1100, \ + "DCIL" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "DCDCA" }, /* DCDC active , */ \ + { 0x1120, \ + "DCOCPOK" }, /* DCDC OCP nmos , */ \ + { 0x1140, \ + "DCHVBAT" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "DCH114" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "DCH107" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "STMUTEB" }, /* side tone (un)mute busy , */ \ + { 0x1180, \ + "STMUTE" }, /* side tone mute state , */ \ + { 0x1190, \ + "TDMLUTER" }, /* TDM LUT error , */ \ + { 0x11a2, \ + "TDMSTAT" }, /* TDM status bits , */ \ + { 0x11d0, \ + "TDMERR" }, /* TDM error , */ \ + { 0x1300, \ + "OCPOAP" }, /* OCPOK pmos A , */ \ + { 0x1310, \ + "OCPOAN" }, /* OCPOK nmos A , */ \ + { 0x1320, \ + "OCPOBP" }, /* OCPOK pmos B , */ \ + { 0x1330, \ + "OCPOBN" }, /* OCPOK nmos B , */ \ + { 0x1340, \ + "CLIPAH" }, /* Clipping A to Vddp , */ \ + { 0x1350, \ + "CLIPAL" }, /* Clipping A to gnd , */ \ + { 0x1360, \ + "CLIPBH" }, /* Clipping B to Vddp , */ \ + { 0x1370, \ + "CLIPBL" }, /* Clipping B to gnd , */ \ + { 0x1380, \ + "OCDS" }, /* OCP amplifier , */ \ + { 0x1390, \ + "CLIPS" }, /* Amplifier clipping , */ \ + { 0x13a0, \ + "OCPOKMC" }, /* OCPOK MICVDD , */ \ + { 0x13b0, \ + "MANALARM" }, /* Alarm state , */ \ + { 0x13c0, \ + "MANWAIT1" }, /* Wait HW I2C settings , */ \ + { 0x13e0, \ + "MANMUTE" }, /* Audio mute sequence , */ \ + { 0x13f0, \ + "MANOPER" }, /* Operating state , */ \ + { 0x1420, \ + "CLKOOR" }, /* External clock status , */ \ + { 0x1433, \ + "MANSTATE" }, /* Device manager status , */ \ + { 0x1471, \ + "DCMODE" }, /* DCDC mode status bits , */ \ + { 0x1509, \ + "BATS" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "TEMPS" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "VDDPS" }, /* IC VDDP voltage ( 1023*VDDP/9.5 V) , */ \ + { 0x2040, \ + "TDME" }, /* Enable interface , */ \ + { 0x2050, \ + "TDMMODE" }, /* Slave/master , */ \ + { 0x2060, \ + "TDMCLINV" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "TDMFSLN" }, /* FS length (master mode only) , */ \ + { 0x20b0, \ + "TDMFSPOL" }, /* FS polarity , */ \ + { 0x20c3, \ + "TDMNBCK" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "TDMSLOTS" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "TDMSLLN" }, /* N-bits in slot , */ \ + { 0x2194, \ + "TDMBRMG" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "TDMDEL" }, /* data delay to FS , */ \ + { 0x21f0, \ + "TDMADJ" }, /* data adjustment , */ \ + { 0x2201, \ + "TDMOOMP" }, /* Received audio compression , */ \ + { 0x2224, \ + "TDMSSIZE" }, /* Sample size per slot , */ \ + { 0x2271, \ + "TDMTXDFO" }, /* Format unused bits , */ \ + { 0x2291, \ + "TDMTXUS0" }, /* Format unused slots DATAO , */ \ + { 0x2300, \ + "TDMSPKE" }, /* Control audio tdm channel in 0 (spkr + dcdc) , */ \ + { 0x2310, \ + "TDMDCE" }, /* Control audio tdm channel in 1 (dcdc) , */ \ + { 0x2330, \ + "TDMCSE" }, /* current sense vbat temperature and vddp feedback , */ \ + { 0x2340, \ + "TDMVSE" }, /* Voltage sense vbat temperature and vddp feedback , */ \ + { 0x2603, \ + "TDMSPKS" }, /* tdm slot for sink 0 (speaker + dcdc) , */ \ + { 0x2643, \ + "TDMDCS" }, /* tdm slot for sink 1 (dcdc) , */ \ + { 0x26c3, \ + "TDMCSS" }, /* Slot Position of current sense vbat temperature and vddp feedback, */ \ + { 0x2703, \ + "TDMVSS" }, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */ \ + { 0x3111, \ + "PDMSTSEL" }, /* Side tone input , */ \ + { 0x4000, \ + "ISTVDDS" }, /* Status POR , */ \ + { 0x4010, \ + "ISTPLLS" }, /* Status PLL lock , */ \ + { 0x4020, \ + "ISTOTDS" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "ISTOVDS" }, /* Status OVP alarm , */ \ + { 0x4040, \ + "ISTUVDS" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "ISTCLKS" }, /* Status clocks stable , */ \ + { 0x4060, \ + "ISTMTPB" }, /* Status MTP busy , */ \ + { 0x4070, \ + "ISTNOCLK" }, /* Status lost clock , */ \ + { 0x40a0, \ + "ISTSWS" }, /* Status amplifier engage , */ \ + { 0x40c0, \ + "ISTAMPS" }, /* Status amplifier enable , */ \ + { 0x40d0, \ + "ISTAREFS" }, /* Status Ref enable , */ \ + { 0x40e0, \ + "ISTADCCR" }, /* Status Control ADC , */ \ + { 0x4100, \ + "ISTBSTCU" }, /* Status DCDC current limiting , */ \ + { 0x4110, \ + "ISTBSTHI" }, /* Status DCDC active , */ \ + { 0x4120, \ + "ISTBSTOC" }, /* Status DCDC OCP , */ \ + { 0x4130, \ + "ISTBSTPKCUR" }, /* Status bst peakcur , */ \ + { 0x4140, \ + "ISTBSTVC" }, /* Status DCDC level 1x , */ \ + { 0x4150, \ + "ISTBST86" }, /* Status DCDC level 1.14x , */ \ + { 0x4160, \ + "ISTBST93" }, /* Status DCDC level 1.07x , */ \ + { 0x4190, \ + "ISTOCPR" }, /* Status ocp alarm , */ \ + { 0x41a0, \ + "ISTMWSRC" }, /* Status Waits HW I2C settings , */ \ + { 0x41c0, \ + "ISTMWSMU" }, /* Status Audio mute sequence , */ \ + { 0x41f0, \ + "ISTCLKOOR" }, /* Status flag_clk_out_of_range , */ \ + { 0x4200, \ + "ISTTDMER" }, /* Status tdm error , */ \ + { 0x4220, \ + "ISTCLPR" }, /* Status clip , */ \ + { 0x4240, \ + "ISTLP0" }, /* Status low power mode0 , */ \ + { 0x4250, \ + "ISTLP1" }, /* Status low power mode1 , */ \ + { 0x4260, \ + "ISTLA" }, /* Status low noise detection , */ \ + { 0x4270, \ + "ISTVDDPH" }, /* Status VDDP greater than VBAT , */ \ + { 0x4400, \ + "ICLVDDS" }, /* Clear POR , */ \ + { 0x4410, \ + "ICLPLLS" }, /* Clear PLL lock , */ \ + { 0x4420, \ + "ICLOTDS" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "ICLOVDS" }, /* Clear OVP alarm , */ \ + { 0x4440, \ + "ICLUVDS" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "ICLCLKS" }, /* Clear clocks stable , */ \ + { 0x4460, \ + "ICLMTPB" }, /* Clear mtp busy , */ \ + { 0x4470, \ + "ICLNOCLK" }, /* Clear lost clk , */ \ + { 0x44a0, \ + "ICLSWS" }, /* Clear amplifier engage , */ \ + { 0x44c0, \ + "ICLAMPS" }, /* Clear enbl amp , */ \ + { 0x44d0, \ + "ICLAREFS" }, /* Clear ref enable , */ \ + { 0x44e0, \ + "ICLADCCR" }, /* Clear control ADC , */ \ + { 0x4500, \ + "ICLBSTCU" }, /* Clear DCDC current limiting , */ \ + { 0x4510, \ + "ICLBSTHI" }, /* Clear DCDC active , */ \ + { 0x4520, \ + "ICLBSTOC" }, /* Clear DCDC OCP , */ \ + { 0x4530, \ + "ICLBSTPC" }, /* Clear bst peakcur , */ \ + { 0x4540, \ + "ICLBSTVC" }, /* Clear DCDC level 1x , */ \ + { 0x4550, \ + "ICLBST86" }, /* Clear DCDC level 1.14x , */ \ + { 0x4560, \ + "ICLBST93" }, /* Clear DCDC level 1.07x , */ \ + { 0x4590, \ + "ICLOCPR" }, /* Clear ocp alarm , */ \ + { 0x45a0, \ + "ICLMWSRC" }, /* Clear wait HW I2C settings , */ \ + { 0x45c0, \ + "ICLMWSMU" }, /* Clear audio mute sequence , */ \ + { 0x45f0, \ + "ICLCLKOOR" }, /* Clear flag_clk_out_of_range , */ \ + { 0x4600, \ + "ICLTDMER" }, /* Clear tdm error , */ \ + { 0x4620, \ + "ICLCLPR" }, /* Clear clip , */ \ + { 0x4640, \ + "ICLLP0" }, /* Clear low power mode0 , */ \ + { 0x4650, \ + "ICLLP1" }, /* Clear low power mode1 , */ \ + { 0x4660, \ + "ICLLA" }, /* Clear low noise detection , */ \ + { 0x4670, \ + "ICLVDDPH" }, /* Clear VDDP greater then VBAT , */ \ + { 0x4800, \ + "IEVDDS" }, /* Enable por , */ \ + { 0x4810, \ + "IEPLLS" }, /* Enable pll lock , */ \ + { 0x4820, \ + "IEOTDS" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "IEOVDS" }, /* Enable OVP alarm , */ \ + { 0x4840, \ + "IEUVDS" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "IECLKS" }, /* Enable clocks stable , */ \ + { 0x4860, \ + "IEMTPB" }, /* Enable mtp busy , */ \ + { 0x4870, \ + "IENOCLK" }, /* Enable lost clk , */ \ + { 0x48a0, \ + "IESWS" }, /* Enable amplifier engage , */ \ + { 0x48c0, \ + "IEAMPS" }, /* Enable enbl amp , */ \ + { 0x48d0, \ + "IEAREFS" }, /* Enable ref enable , */ \ + { 0x48e0, \ + "IEADCCR" }, /* Enable Control ADC , */ \ + { 0x4900, \ + "IEBSTCU" }, /* Enable DCDC current limiting , */ \ + { 0x4910, \ + "IEBSTHI" }, /* Enable DCDC active , */ \ + { 0x4920, \ + "IEBSTOC" }, /* Enable DCDC OCP , */ \ + { 0x4930, \ + "IEBSTPC" }, /* Enable bst peakcur , */ \ + { 0x4940, \ + "IEBSTVC" }, /* Enable DCDC level 1x , */ \ + { 0x4950, \ + "IEBST86" }, /* Enable DCDC level 1.14x , */ \ + { 0x4960, \ + "IEBST93" }, /* Enable DCDC level 1.07x , */ \ + { 0x4990, \ + "IEOCPR" }, /* Enable ocp alarm , */ \ + { 0x49a0, \ + "IEMWSRC" }, /* Enable waits HW I2C settings , */ \ + { 0x49c0, \ + "IEMWSMU" }, /* Enable man Audio mute sequence , */ \ + { 0x49f0, \ + "IECLKOOR" }, /* Enable flag_clk_out_of_range , */ \ + { 0x4a00, \ + "IETDMER" }, /* Enable tdm error , */ \ + { 0x4a20, \ + "IECLPR" }, /* Enable clip , */ \ + { 0x4a40, \ + "IELP0" }, /* Enable low power mode0 , */ \ + { 0x4a50, \ + "IELP1" }, /* Enable low power mode1 , */ \ + { 0x4a60, \ + "IELA" }, /* Enable low noise detection , */ \ + { 0x4a70, \ + "IEVDDPH" }, /* Enable VDDP greater tehn VBAT , */ \ + { 0x4c00, \ + "IPOVDDS" }, /* Polarity por , */ \ + { 0x4c10, \ + "IPOPLLS" }, /* Polarity pll lock , */ \ + { 0x4c20, \ + "IPOOTDS" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "IPOOVDS" }, /* Polarity OVP alarm , */ \ + { 0x4c40, \ + "IPOUVDS" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "IPOCLKS" }, /* Polarity clocks stable , */ \ + { 0x4c60, \ + "IPOMTPB" }, /* Polarity mtp busy , */ \ + { 0x4c70, \ + "IPONOCLK" }, /* Polarity lost clk , */ \ + { 0x4ca0, \ + "IPOSWS" }, /* Polarity amplifier engage , */ \ + { 0x4cc0, \ + "IPOAMPS" }, /* Polarity enbl amp , */ \ + { 0x4cd0, \ + "IPOAREFS" }, /* Polarity ref enable , */ \ + { 0x4ce0, \ + "IPOADCCR" }, /* Polarity Control ADC , */ \ + { 0x4d00, \ + "IPOBSTCU" }, /* Polarity DCDC current limiting , */ \ + { 0x4d10, \ + "IPOBSTHI" }, /* Polarity DCDC active , */ \ + { 0x4d20, \ + "IPOBSTOC" }, /* Polarity DCDC OCP , */ \ + { 0x4d30, \ + "IPOBSTPC" }, /* Polarity bst peakcur , */ \ + { 0x4d40, \ + "IPOBSTVC" }, /* Polarity DCDC level 1x , */ \ + { 0x4d50, \ + "IPOBST86" }, /* Polarity DCDC level 1.14x , */ \ + { 0x4d60, \ + "IPOBST93" }, /* Polarity DCDC level 1.07x , */ \ + { 0x4d90, \ + "IPOOCPR" }, /* Polarity ocp alarm , */ \ + { 0x4da0, \ + "IPOMWSRC" }, /* Polarity waits HW I2C settings , */ \ + { 0x4dc0, \ + "IPOMWSMU" }, /* Polarity man audio mute sequence , */ \ + { 0x4df0, \ + "IPCLKOOR" }, /* Polarity flag_clk_out_of_range , */ \ + { 0x4e00, \ + "IPOTDMER" }, /* Polarity tdm error , */ \ + { 0x4e20, \ + "IPOCLPR" }, /* Polarity clip right , */ \ + { 0x4e40, \ + "IPOLP0" }, /* Polarity low power mode0 , */ \ + { 0x4e50, \ + "IPOLP1" }, /* Polarity low power mode1 , */ \ + { 0x4e60, \ + "IPOLA" }, /* Polarity low noise mode , */ \ + { 0x4e70, \ + "IPOVDDPH" }, /* Polarity VDDP greater than VBAT , */ \ + { 0x5001, \ + "BSSCR" }, /* Battery Safeguard attack time , */ \ + { 0x5023, \ + "BSST" }, /* Battery Safeguard threshold voltage level , */ \ + { 0x5061, \ + "BSSRL" }, /* Battery Safeguard maximum reduction , */ \ + { 0x50e0, \ + "BSSR" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "BSSBY" }, /* Bypass battery safeguard , */ \ + { 0x5100, \ + "BSSS" }, /* Vbat prot steepness , */ \ + { 0x5110, \ + "INTSMUTE" }, /* Soft mute HW , */ \ + { 0x5150, \ + "HPFBYP" }, /* Bypass HPF , */ \ + { 0x5170, \ + "DPSA" }, /* Enable DPSA , */ \ + { 0x5222, \ + "CLIPCTRL" }, /* Clip control setting , */ \ + { 0x5257, \ + "AMPGAIN" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "SLOPEE" }, /* Enables slope control , */ \ + { 0x52e0, \ + "SLOPESET" }, /* Slope speed setting (bin. coded) , */ \ + { 0x6081, \ + "PGAGAIN" }, /* PGA gain selection , */ \ + { 0x60b0, \ + "PGALPE" }, /* Lowpass enable , */ \ + { 0x6110, \ + "LPM0BYP" }, /* bypass low power idle mode , */ \ + { 0x6123, \ + "TDMDCG" }, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */ \ + { 0x6163, \ + "TDMSPKG" }, /* Total gain depending on INPLEV setting (channel 0), */ \ + { 0x61b0, \ + "STIDLEEN" }, /* enable idle feature for channel 1 , */ \ + { 0x62e1, \ + "LNMODE" }, /* ctrl select mode , */ \ + { 0x64e1, \ + "LPM1MODE" }, /* low power mode control , */ \ + { 0x65c0, \ + "LPM1DIS" }, /* low power mode1 detector control , */ \ + { 0x6801, \ + "TDMSRCMAP" }, /* tdm source mapping , */ \ + { 0x6821, \ + "TDMSRCAS" }, /* Sensed value A , */ \ + { 0x6841, \ + "TDMSRCBS" }, /* Sensed value B , */ \ + { 0x6881, \ + "ANCSEL" }, /* anc input , */ \ + { 0x68a0, \ + "ANC1C" }, /* ANC one s complement , */ \ + { 0x6901, \ + "SAMMODE" }, /* sam enable , */ \ + { 0x6920, \ + "SAMSEL" }, /* sam source , */ \ + { 0x6931, \ + "PDMOSELH" }, /* pdm out value when pdm_clk is higth , */ \ + { 0x6951, \ + "PDMOSELL" }, /* pdm out value when pdm_clk is low , */ \ + { 0x6970, \ + "SAMOSEL" }, /* ram output on mode sam and audio , */ \ + { 0x6e00, \ + "LP0" }, /* low power mode 0 detection , */ \ + { 0x6e10, \ + "LP1" }, /* low power mode 1 detection , */ \ + { 0x6e20, \ + "LA" }, /* low amplitude detection , */ \ + { 0x6e30, \ + "VDDPH" }, /* vddp greater than vbat , */ \ + { 0x6f02, \ + "DELCURCOMP" }, /* delay to allign compensation signal with current sense signal, */ \ + { 0x6f40, \ + "SIGCURCOMP" }, /* polarity of compensation for current sense , */ \ + { 0x6f50, \ + "ENCURCOMP" }, /* enable current sense compensation , */ \ + { 0x6f60, \ + "SELCLPPWM" }, /* Select pwm clip flag , */ \ + { 0x6f72, \ + "LVLCLPPWM" }, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */ \ + { 0x7002, \ + "DCVOS" }, /* Second boost voltage level , */ \ + { 0x7033, \ + "DCMCC" }, /* Max coil current , */ \ + { 0x7071, \ + "DCCV" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7090, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "DCSR" }, /* Soft ramp up/down , */ \ + { 0x70e0, \ + "DCDIS" }, /* DCDC on/off , */ \ + { 0x70f0, \ + "DCPWM" }, /* DCDC PWM only mode , */ \ + { 0x7402, \ + "DCVOF" }, /* 1st boost voltage level , */ \ + { 0x7430, \ + "DCTRACK" }, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */ \ + { 0x7444, \ + "DCTRIP" }, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7494, \ + "DCHOLD" }, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */ \ + { 0x7534, \ + "DCTRIP2" }, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7584, \ + "DCTRIPT" }, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0xa107, \ + "MTPK" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "KEY1LOCKED" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "KEY2LOCKED" }, /* Indicates KEY2 is locked , */ \ + { 0xa350, \ + "CMTPI" }, /* Start copying all the data from mtp to I2C mtp registers, */ \ + { 0xa360, \ + "CIMTP" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa50f, \ + "MTPRDMSB" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "MTPRDLSB" }, /* LSB word of MTP manual read data , */ \ + { 0xb108, \ + "EXTTS" }, /* External temperature (C) , */ \ + { 0xb190, \ + "TROS" }, /* Select temp Speaker calibration , */ \ + { 0xee0f, \ + "SWPROFIL" }, /* Software profile data , */ \ + { 0xef0f, \ + "SWVSTEP" }, /* Software vstep information , */ \ + { 0xf000, \ + "MTPOTC" }, /* Calibration schedule , */ \ + { 0xf010, \ + "MTPEX" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "DCMCCAPI" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "DCMCCSB" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "USERDEF" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "CUSTINFO" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf50f, \ + "R25C" }, /* Ron resistance of speaker coil , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9872_BITNAMETABLE \ + static tfaBfName_t Tfa9872BitNames[] = { \ + { 0x0, \ + "powerdown" }, /* Powerdown selection , */ \ + { 0x10, \ + "reset" }, /* I2C Reset - Auto clear , */ \ + { 0x30, \ + "enbl_amplifier" }, /* Activate Amplifier , */ \ + { 0x40, \ + "enbl_boost" }, /* Activate DC-to-DC converter , */ \ + { 0x71, \ + "int_pad_io" }, /* Interrupt config , */ \ + { 0xb0, \ + "bypass_ocp" }, /* Bypass OCP , */ \ + { 0xc0, \ + "test_ocp" }, /* OCP testing control , */ \ + { 0x120, \ + "src_set_configured" }, /* I2C configured , */ \ + { 0x140, \ + "enbl_osc1m_auto_off" }, /* Internal osc off at PWDN , */ \ + { 0x1d0, \ + "disable_mute_time_out" }, /* Time out SB mute sequence , */ \ + { 0x203, \ + "audio_fs" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "input_level" }, /* TDM output attenuation , */ \ + { 0x255, \ + "cs_frac_delay" }, /* V/I Fractional delay , */ \ + { 0x2b0, \ + "bypass_hvbat_filter" }, /* Bypass HVBAT filter , */ \ + { 0x2d0, \ + "sel_hysteresis" }, /* Select hysteresis for clock range detector , */ \ + { 0x30f, \ + "device_rev" }, /* Revision info , */ \ + { 0x401, \ + "pll_clkin_sel" }, /* PLL external ref clock , */ \ + { 0x420, \ + "pll_clkin_sel_osc" }, /* PLL internal ref clock , */ \ + { 0x510, \ + "enbl_spkr_ss" }, /* Enable speaker path , */ \ + { 0x530, \ + "enbl_volsense" }, /* Voltage sense , */ \ + { 0x550, \ + "enbl_cursense" }, /* Current sense , */ \ + { 0x560, \ + "enbl_pdm_ss" }, /* Sub-system PDM , */ \ + { 0x580, \ + "enbl_pga_chop" }, /* Enable PGA chop clock , */ \ + { 0x590, \ + "enbl_tdm_ss" }, /* Sub-system TDM , */ \ + { 0x5a0, \ + "enbl_bst_ss" }, /* Sub-system boost , */ \ + { 0x5b0, \ + "enbl_adc_ss" }, /* Sub-system ADC , */ \ + { 0x5c0, \ + "enbl_faim_ss" }, /* Sub-system FAIM , */ \ + { 0xd18, \ + "side_tone_gain" }, /* Side tone gain , */ \ + { 0xda0, \ + "mute_side_tone" }, /* Side tone soft mute , */ \ + { 0xdb0, \ + "side_tone_1scomplement" }, /* side tone one s complement , */ \ + { 0xe07, \ + "ctrl_digtoana" }, /* Spare control from digital to analog , */ \ + { 0xf0f, \ + "hidden_code" }, /* 5A6Bh, 23147d to access registers (default for engineering), */ \ + { 0x1000, \ + "flag_por" }, /* POR , */ \ + { 0x1010, \ + "flag_pll_lock" }, /* PLL lock , */ \ + { 0x1020, \ + "flag_otpok" }, /* OTP alarm , */ \ + { 0x1030, \ + "flag_ovpok" }, /* OVP alarm , */ \ + { 0x1040, \ + "flag_uvpok" }, /* UVP alarm , */ \ + { 0x1050, \ + "flag_clocks_stable" }, /* Clocks stable , */ \ + { 0x1060, \ + "flag_mtp_busy" }, /* MTP busy , */ \ + { 0x1070, \ + "flag_lost_clk" }, /* Lost clock , */ \ + { 0x10a0, \ + "flag_engage" }, /* Amplifier engage , */ \ + { 0x10c0, \ + "flag_enbl_amp" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "flag_enbl_ref" }, /* References enable , */ \ + { 0x10e0, \ + "flag_adc10_ready" }, /* Control ADC , */ \ + { 0x1100, \ + "flag_bst_bstcur" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "flag_bst_hiz" }, /* DCDC active , */ \ + { 0x1120, \ + "flag_bst_ocpok" }, /* DCDC OCP nmos , */ \ + { 0x1130, \ + "flag_bst_peakcur" }, /* Indicates current is max in DC-to-DC converter , */ \ + { 0x1140, \ + "flag_bst_voutcomp" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "flag_bst_voutcomp86" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "flag_bst_voutcomp93" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "flag_soft_mute_busy" }, /* side tone (un)mute busy , */ \ + { 0x1180, \ + "flag_soft_mute_state" }, /* side tone mute state , */ \ + { 0x1190, \ + "flag_tdm_lut_error" }, /* TDM LUT error , */ \ + { 0x11a2, \ + "flag_tdm_status" }, /* TDM status bits , */ \ + { 0x11d0, \ + "flag_tdm_error" }, /* TDM error , */ \ + { 0x1300, \ + "flag_ocpokap" }, /* OCPOK pmos A , */ \ + { 0x1310, \ + "flag_ocpokan" }, /* OCPOK nmos A , */ \ + { 0x1320, \ + "flag_ocpokbp" }, /* OCPOK pmos B , */ \ + { 0x1330, \ + "flag_ocpokbn" }, /* OCPOK nmos B , */ \ + { 0x1340, \ + "flag_clipa_high" }, /* Clipping A to Vddp , */ \ + { 0x1350, \ + "flag_clipa_low" }, /* Clipping A to gnd , */ \ + { 0x1360, \ + "flag_clipb_high" }, /* Clipping B to Vddp , */ \ + { 0x1370, \ + "flag_clipb_low" }, /* Clipping B to gnd , */ \ + { 0x1380, \ + "flag_ocp_alarm" }, /* OCP amplifier , */ \ + { 0x1390, \ + "flag_clip" }, /* Amplifier clipping , */ \ + { 0x13b0, \ + "flag_man_alarm_state" }, /* Alarm state , */ \ + { 0x13c0, \ + "flag_man_wait_src_settings" }, /* Wait HW I2C settings , */ \ + { 0x13e0, \ + "flag_man_start_mute_audio" }, /* Audio mute sequence , */ \ + { 0x13f0, \ + "flag_man_operating_state" }, /* Operating state , */ \ + { 0x1420, \ + "flag_clk_out_of_range" }, /* External clock status , */ \ + { 0x1433, \ + "man_state" }, /* Device manager status , */ \ + { 0x1471, \ + "status_bst_mode" }, /* DCDC mode status bits , */ \ + { 0x1509, \ + "bat_adc" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "temp_adc" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "vddp_adc" }, /* IC VDDP voltage ( 1023*VDDP/9.5 V) , */ \ + { 0x2040, \ + "tdm_enable" }, /* Enable interface , */ \ + { 0x2050, \ + "tdm_mode" }, /* Slave/master , */ \ + { 0x2060, \ + "tdm_clk_inversion" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "tdm_fs_ws_length" }, /* FS length (master mode only) , */ \ + { 0x20b0, \ + "tdm_fs_ws_polarity" }, /* FS polarity , */ \ + { 0x20c3, \ + "tdm_nbck" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "tdm_nb_of_slots" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "tdm_slot_length" }, /* N-bits in slot , */ \ + { 0x2194, \ + "tdm_bits_remaining" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "tdm_data_delay" }, /* data delay to FS , */ \ + { 0x21f0, \ + "tdm_data_adjustment" }, /* data adjustment , */ \ + { 0x2201, \ + "tdm_audio_sample_compression" }, /* Received audio compression , */ \ + { 0x2224, \ + "tdm_sample_size" }, /* Sample size per slot , */ \ + { 0x2271, \ + "tdm_txdata_format" }, /* Format unused bits , */ \ + { 0x2291, \ + "tdm_txdata_format_unused_slot_sd0" }, /* Format unused slots DATAO , */ \ + { 0x2300, \ + "tdm_sink0_enable" }, /* Control audio tdm channel in 0 (spkr + dcdc) , */ \ + { 0x2310, \ + "tdm_sink1_enable" }, /* Control audio tdm channel in 1 (dcdc) , */ \ + { 0x2330, \ + "tdm_source0_enable" }, /* current sense vbat temperature and vddp feedback , */ \ + { 0x2340, \ + "tdm_source1_enable" }, /* Voltage sense vbat temperature and vddp feedback , */ \ + { 0x2603, \ + "tdm_sink0_slot" }, /* tdm slot for sink 0 (speaker + dcdc) , */ \ + { 0x2643, \ + "tdm_sink1_slot" }, /* tdm slot for sink 1 (dcdc) , */ \ + { 0x26c3, \ + "tdm_source0_slot" }, /* Slot Position of current sense vbat temperature and vddp feedback, */ \ + { 0x2703, \ + "tdm_source1_slot" }, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */ \ + { 0x3111, \ + "pdm_side_tone_sel" }, /* Side tone input , */ \ + { 0x3201, \ + "pdm_nbck" }, /* PDM BCK/Fs ratio , */ \ + { 0x4000, \ + "int_out_flag_por" }, /* Status POR , */ \ + { 0x4010, \ + "int_out_flag_pll_lock" }, /* Status PLL lock , */ \ + { 0x4020, \ + "int_out_flag_otpok" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "int_out_flag_ovpok" }, /* Status OVP alarm , */ \ + { 0x4040, \ + "int_out_flag_uvpok" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "int_out_flag_clocks_stable" }, /* Status clocks stable , */ \ + { 0x4060, \ + "int_out_flag_mtp_busy" }, /* Status MTP busy , */ \ + { 0x4070, \ + "int_out_flag_lost_clk" }, /* Status lost clock , */ \ + { 0x40a0, \ + "int_out_flag_engage" }, /* Status amplifier engage , */ \ + { 0x40c0, \ + "int_out_flag_enbl_amp" }, /* Status amplifier enable , */ \ + { 0x40d0, \ + "int_out_flag_enbl_ref" }, /* Status Ref enable , */ \ + { 0x40e0, \ + "int_out_flag_adc10_ready" }, /* Status Control ADC , */ \ + { 0x4100, \ + "int_out_flag_bst_bstcur" }, /* Status DCDC current limiting , */ \ + { 0x4110, \ + "int_out_flag_bst_hiz" }, /* Status DCDC active , */ \ + { 0x4120, \ + "int_out_flag_bst_ocpok" }, /* Status DCDC OCP , */ \ + { 0x4130, \ + "int_out_flag_bst_peakcur" }, /* Status bst peakcur , */ \ + { 0x4140, \ + "int_out_flag_bst_voutcomp" }, /* Status DCDC level 1x , */ \ + { 0x4150, \ + "int_out_flag_bst_voutcomp86" }, /* Status DCDC level 1.14x , */ \ + { 0x4160, \ + "int_out_flag_bst_voutcomp93" }, /* Status DCDC level 1.07x , */ \ + { 0x4190, \ + "int_out_flag_ocp_alarm" }, /* Status ocp alarm , */ \ + { 0x41a0, \ + "int_out_flag_man_wait_src_settings" }, /* Status Waits HW I2C settings , */ \ + { 0x41c0, \ + "int_out_flag_man_start_mute_audio" }, /* Status Audio mute sequence , */ \ + { 0x41f0, \ + "int_out_flag_clk_out_of_range" }, /* Status flag_clk_out_of_range , */ \ + { 0x4200, \ + "int_out_flag_tdm_error" }, /* Status tdm error , */ \ + { 0x4220, \ + "int_out_flag_clip" }, /* Status clip , */ \ + { 0x4240, \ + "int_out_flag_lp_detect_mode0" }, /* Status low power mode0 , */ \ + { 0x4250, \ + "int_out_flag_lp_detect_mode1" }, /* Status low power mode1 , */ \ + { 0x4260, \ + "int_out_flag_low_amplitude" }, /* Status low noise detection , */ \ + { 0x4270, \ + "int_out_flag_vddp_gt_vbat" }, /* Status VDDP greater than VBAT , */ \ + { 0x4400, \ + "int_in_flag_por" }, /* Clear POR , */ \ + { 0x4410, \ + "int_in_flag_pll_lock" }, /* Clear PLL lock , */ \ + { 0x4420, \ + "int_in_flag_otpok" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "int_in_flag_ovpok" }, /* Clear OVP alarm , */ \ + { 0x4440, \ + "int_in_flag_uvpok" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "int_in_flag_clocks_stable" }, /* Clear clocks stable , */ \ + { 0x4460, \ + "int_in_flag_mtp_busy" }, /* Clear mtp busy , */ \ + { 0x4470, \ + "int_in_flag_lost_clk" }, /* Clear lost clk , */ \ + { 0x44a0, \ + "int_in_flag_engage" }, /* Clear amplifier engage , */ \ + { 0x44c0, \ + "int_in_flag_enbl_amp" }, /* Clear enbl amp , */ \ + { 0x44d0, \ + "int_in_flag_enbl_ref" }, /* Clear ref enable , */ \ + { 0x44e0, \ + "int_in_flag_adc10_ready" }, /* Clear control ADC , */ \ + { 0x4500, \ + "int_in_flag_bst_bstcur" }, /* Clear DCDC current limiting , */ \ + { 0x4510, \ + "int_in_flag_bst_hiz" }, /* Clear DCDC active , */ \ + { 0x4520, \ + "int_in_flag_bst_ocpok" }, /* Clear DCDC OCP , */ \ + { 0x4530, \ + "int_in_flag_bst_peakcur" }, /* Clear bst peakcur , */ \ + { 0x4540, \ + "int_in_flag_bst_voutcomp" }, /* Clear DCDC level 1x , */ \ + { 0x4550, \ + "int_in_flag_bst_voutcomp86" }, /* Clear DCDC level 1.14x , */ \ + { 0x4560, \ + "int_in_flag_bst_voutcomp93" }, /* Clear DCDC level 1.07x , */ \ + { 0x4590, \ + "int_in_flag_ocp_alarm" }, /* Clear ocp alarm , */ \ + { 0x45a0, \ + "int_in_flag_man_wait_src_settings" }, /* Clear wait HW I2C settings , */ \ + { 0x45c0, \ + "int_in_flag_man_start_mute_audio" }, /* Clear audio mute sequence , */ \ + { 0x45f0, \ + "int_in_flag_clk_out_of_range" }, /* Clear flag_clk_out_of_range , */ \ + { 0x4600, \ + "int_in_flag_tdm_error" }, /* Clear tdm error , */ \ + { 0x4620, \ + "int_in_flag_clip" }, /* Clear clip , */ \ + { 0x4640, \ + "int_in_flag_lp_detect_mode0" }, /* Clear low power mode0 , */ \ + { 0x4650, \ + "int_in_flag_lp_detect_mode1" }, /* Clear low power mode1 , */ \ + { 0x4660, \ + "int_in_flag_low_amplitude" }, /* Clear low noise detection , */ \ + { 0x4670, \ + "int_in_flag_vddp_gt_vbat" }, /* Clear VDDP greater then VBAT , */ \ + { 0x4800, \ + "int_enable_flag_por" }, /* Enable por , */ \ + { 0x4810, \ + "int_enable_flag_pll_lock" }, /* Enable pll lock , */ \ + { 0x4820, \ + "int_enable_flag_otpok" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "int_enable_flag_ovpok" }, /* Enable OVP alarm , */ \ + { 0x4840, \ + "int_enable_flag_uvpok" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "int_enable_flag_clocks_stable" }, /* Enable clocks stable , */ \ + { 0x4860, \ + "int_enable_flag_mtp_busy" }, /* Enable mtp busy , */ \ + { 0x4870, \ + "int_enable_flag_lost_clk" }, /* Enable lost clk , */ \ + { 0x48a0, \ + "int_enable_flag_engage" }, /* Enable amplifier engage , */ \ + { 0x48c0, \ + "int_enable_flag_enbl_amp" }, /* Enable enbl amp , */ \ + { 0x48d0, \ + "int_enable_flag_enbl_ref" }, /* Enable ref enable , */ \ + { 0x48e0, \ + "int_enable_flag_adc10_ready" }, /* Enable Control ADC , */ \ + { 0x4900, \ + "int_enable_flag_bst_bstcur" }, /* Enable DCDC current limiting , */ \ + { 0x4910, \ + "int_enable_flag_bst_hiz" }, /* Enable DCDC active , */ \ + { 0x4920, \ + "int_enable_flag_bst_ocpok" }, /* Enable DCDC OCP , */ \ + { 0x4930, \ + "int_enable_flag_bst_peakcur" }, /* Enable bst peakcur , */ \ + { 0x4940, \ + "int_enable_flag_bst_voutcomp" }, /* Enable DCDC level 1x , */ \ + { 0x4950, \ + "int_enable_flag_bst_voutcomp86" }, /* Enable DCDC level 1.14x , */ \ + { 0x4960, \ + "int_enable_flag_bst_voutcomp93" }, /* Enable DCDC level 1.07x , */ \ + { 0x4990, \ + "int_enable_flag_ocp_alarm" }, /* Enable ocp alarm , */ \ + { 0x49a0, \ + "int_enable_flag_man_wait_src_settings" }, /* Enable waits HW I2C settings , */ \ + { 0x49c0, \ + "int_enable_flag_man_start_mute_audio" }, /* Enable man Audio mute sequence , */ \ + { 0x49f0, \ + "int_enable_flag_clk_out_of_range" }, /* Enable flag_clk_out_of_range , */ \ + { 0x4a00, \ + "int_enable_flag_tdm_error" }, /* Enable tdm error , */ \ + { 0x4a20, \ + "int_enable_flag_clip" }, /* Enable clip , */ \ + { 0x4a40, \ + "int_enable_flag_lp_detect_mode0" }, /* Enable low power mode0 , */ \ + { 0x4a50, \ + "int_enable_flag_lp_detect_mode1" }, /* Enable low power mode1 , */ \ + { 0x4a60, \ + "int_enable_flag_low_amplitude" }, /* Enable low noise detection , */ \ + { 0x4a70, \ + "int_enable_flag_vddp_gt_vbat" }, /* Enable VDDP greater tehn VBAT , */ \ + { 0x4c00, \ + "int_polarity_flag_por" }, /* Polarity por , */ \ + { 0x4c10, \ + "int_polarity_flag_pll_lock" }, /* Polarity pll lock , */ \ + { 0x4c20, \ + "int_polarity_flag_otpok" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "int_polarity_flag_ovpok" }, /* Polarity OVP alarm , */ \ + { 0x4c40, \ + "int_polarity_flag_uvpok" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "int_polarity_flag_clocks_stable" }, /* Polarity clocks stable , */ \ + { 0x4c60, \ + "int_polarity_flag_mtp_busy" }, /* Polarity mtp busy , */ \ + { 0x4c70, \ + "int_polarity_flag_lost_clk" }, /* Polarity lost clk , */ \ + { 0x4ca0, \ + "int_polarity_flag_engage" }, /* Polarity amplifier engage , */ \ + { 0x4cc0, \ + "int_polarity_flag_enbl_amp" }, /* Polarity enbl amp , */ \ + { 0x4cd0, \ + "int_polarity_flag_enbl_ref" }, /* Polarity ref enable , */ \ + { 0x4ce0, \ + "int_polarity_flag_adc10_ready" }, /* Polarity Control ADC , */ \ + { 0x4d00, \ + "int_polarity_flag_bst_bstcur" }, /* Polarity DCDC current limiting , */ \ + { 0x4d10, \ + "int_polarity_flag_bst_hiz" }, /* Polarity DCDC active , */ \ + { 0x4d20, \ + "int_polarity_flag_bst_ocpok" }, /* Polarity DCDC OCP , */ \ + { 0x4d30, \ + "int_polarity_flag_bst_peakcur" }, /* Polarity bst peakcur , */ \ + { 0x4d40, \ + "int_polarity_flag_bst_voutcomp" }, /* Polarity DCDC level 1x , */ \ + { 0x4d50, \ + "int_polarity_flag_bst_voutcomp86" }, /* Polarity DCDC level 1.14x , */ \ + { 0x4d60, \ + "int_polarity_flag_bst_voutcomp93" }, /* Polarity DCDC level 1.07x , */ \ + { 0x4d90, \ + "int_polarity_flag_ocp_alarm" }, /* Polarity ocp alarm , */ \ + { 0x4da0, \ + "int_polarity_flag_man_wait_src_settings" }, /* Polarity waits HW I2C settings , */ \ + { 0x4dc0, \ + "int_polarity_flag_man_start_mute_audio" }, /* Polarity man audio mute sequence , */ \ + { 0x4df0, \ + "int_polarity_flag_clk_out_of_range" }, /* Polarity flag_clk_out_of_range , */ \ + { 0x4e00, \ + "int_polarity_flag_tdm_error" }, /* Polarity tdm error , */ \ + { 0x4e20, \ + "int_polarity_flag_clip" }, /* Polarity clip right , */ \ + { 0x4e40, \ + "int_polarity_flag_lp_detect_mode0" }, /* Polarity low power mode0 , */ \ + { 0x4e50, \ + "int_polarity_flag_lp_detect_mode1" }, /* Polarity low power mode1 , */ \ + { 0x4e60, \ + "int_polarity_flag_low_amplitude" }, /* Polarity low noise mode , */ \ + { 0x4e70, \ + "int_polarity_flag_vddp_gt_vbat" }, /* Polarity VDDP greater than VBAT , */ \ + { 0x5001, \ + "vbat_prot_attack_time" }, /* Battery Safeguard attack time , */ \ + { 0x5023, \ + "vbat_prot_thlevel" }, /* Battery Safeguard threshold voltage level , */ \ + { 0x5061, \ + "vbat_prot_max_reduct" }, /* Battery Safeguard maximum reduction , */ \ + { 0x50d0, \ + "rst_min_vbat" }, /* Reset clipper - Auto clear , */ \ + { 0x50e0, \ + "sel_vbat" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "bypass_clipper" }, /* Bypass battery safeguard , */ \ + { 0x5100, \ + "batsense_steepness" }, /* Vbat prot steepness , */ \ + { 0x5110, \ + "soft_mute" }, /* Soft mute HW , */ \ + { 0x5150, \ + "bypass_hp" }, /* Bypass HPF , */ \ + { 0x5170, \ + "enbl_dpsa" }, /* Enable DPSA , */ \ + { 0x5222, \ + "ctrl_cc" }, /* Clip control setting , */ \ + { 0x5257, \ + "gain" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "ctrl_slopectrl" }, /* Enables slope control , */ \ + { 0x52e0, \ + "ctrl_slope" }, /* Slope speed setting (bin. coded) , */ \ + { 0x5301, \ + "dpsa_level" }, /* DPSA threshold levels , */ \ + { 0x5321, \ + "dpsa_release" }, /* DPSA Release time , */ \ + { 0x5340, \ + "clipfast" }, /* Clock selection for HW clipper for Battery Safeguard, */ \ + { 0x5350, \ + "bypass_lp" }, /* Bypass the low power filter inside temperature sensor, */ \ + { 0x5400, \ + "first_order_mode" }, /* Overrule to 1st order mode of control stage when clipping, */ \ + { 0x5410, \ + "bypass_ctrlloop" }, /* Switch amplifier into open loop configuration , */ \ + { 0x5420, \ + "fb_hz" }, /* Feedback resistor set to high ohmic , */ \ + { 0x5430, \ + "icomp_engage" }, /* Engage of icomp , */ \ + { 0x5440, \ + "ctrl_kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x5450, \ + "icomp_engage_overrule" }, /* To overrule the functional icomp_engage signal during validation, */ \ + { 0x5503, \ + "ctrl_dem" }, /* Enable DEM icomp and DEM one bit dac , */ \ + { 0x5543, \ + "ctrl_dem_mismatch" }, /* Enable DEM icomp mismatch for testing , */ \ + { 0x5582, \ + "dpsa_drive" }, /* Drive setting (bin. coded) , */ \ + { 0x570a, \ + "enbl_amp" }, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */ \ + { 0x57b0, \ + "enbl_engage" }, /* Enables/engage power stage and control loop , */ \ + { 0x57c0, \ + "enbl_engage_pst" }, /* Enables/engage power stage and control loop , */ \ + { 0x5810, \ + "hard_mute" }, /* Hard mute - PWM , */ \ + { 0x5820, \ + "pwm_shape" }, /* PWM shape , */ \ + { 0x5844, \ + "pwm_delay" }, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */ \ + { 0x5890, \ + "reclock_pwm" }, /* Reclock the pwm signal inside analog , */ \ + { 0x58a0, \ + "reclock_voltsense" }, /* Reclock the voltage sense pwm signal , */ \ + { 0x58c0, \ + "enbl_pwm_phase_shift" }, /* Control for pwm phase shift , */ \ + { 0x6081, \ + "pga_gain_set" }, /* PGA gain selection , */ \ + { 0x60b0, \ + "pga_lowpass_enable" }, /* Lowpass enable , */ \ + { 0x60c0, \ + "pga_pwr_enable" }, /* Power enable, directcontrol mode only , */ \ + { 0x60d0, \ + "pga_switch_enable" }, /* Switch enable, directcontrol mode only , */ \ + { 0x60e0, \ + "pga_switch_aux_enable" }, /* Switch enable aux, directcontrol mode only , */ \ + { 0x6100, \ + "force_idle" }, /* force low power in idle mode , */ \ + { 0x6110, \ + "bypass_idle" }, /* bypass low power idle mode , */ \ + { 0x6123, \ + "ctrl_attl" }, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */ \ + { 0x6163, \ + "ctrl_attr" }, /* Total gain depending on INPLEV setting (channel 0), */ \ + { 0x61a0, \ + "idle_cnt" }, /* idle counter , */ \ + { 0x61b0, \ + "enbl_idle_ch1" }, /* enable idle feature for channel 1 , */ \ + { 0x6265, \ + "zero_lvl" }, /* low noise gain switch zero trigger level , */ \ + { 0x62c1, \ + "ctrl_fb_classd" }, /* class D gain ctrl_fb_50k ctrl_fb_100k , */ \ + { 0x62e1, \ + "lownoisegain_mode" }, /* ctrl select mode , */ \ + { 0x6305, \ + "threshold_lvl" }, /* low noise gain switch trigger level , */ \ + { 0x6365, \ + "hold_time" }, /* ctrl hold time before low audio is reckoned to be low audio, */ \ + { 0x6405, \ + "lpm1_cal_offset" }, /* low power mode1 detector ctrl cal_offset from gain module , */ \ + { 0x6465, \ + "lpm1_zero_lvl" }, /* low power mode1 zero crossing detection level , */ \ + { 0x64e1, \ + "lpm1_mode" }, /* low power mode control , */ \ + { 0x6505, \ + "lpm1_threshold_lvl" }, /* low power mode1 amplitude trigger level , */ \ + { 0x6565, \ + "lpm1_hold_time" }, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */ \ + { 0x65c0, \ + "disable_low_power_mode" }, /* low power mode1 detector control , */ \ + { 0x6600, \ + "dcdc_pfm20khz_limit" }, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */ \ + { 0x6611, \ + "dcdc_ctrl_maxzercnt" }, /* DCDC. Number of zero current flags to count before going to pfm mode, */ \ + { 0x6656, \ + "dcdc_vbat_delta_detect" }, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */ \ + { 0x66c0, \ + "dcdc_ignore_vbat" }, /* Ignore an increase on Vbat , */ \ + { 0x6700, \ + "enbl_minion" }, /* Enables minion (small) power stage , */ \ + { 0x6713, \ + "vth_vddpvbat" }, /* select vddp-vbat thres signal , */ \ + { 0x6750, \ + "lpen_vddpvbat" }, /* select vddp-vbat filtred vs unfiltered compare , */ \ + { 0x6801, \ + "tdm_source_mapping" }, /* tdm source mapping , */ \ + { 0x6821, \ + "tdm_sourcea_frame_sel" }, /* Sensed value A , */ \ + { 0x6841, \ + "tdm_sourceb_frame_sel" }, /* Sensed value B , */ \ + { 0x6881, \ + "pdm_anc_sel" }, /* anc input , */ \ + { 0x68a0, \ + "anc_1scomplement" }, /* ANC one s complement , */ \ + { 0x6901, \ + "sam_mode" }, /* sam enable , */ \ + { 0x6920, \ + "sam_src" }, /* sam source , */ \ + { 0x6931, \ + "pdmdat_h_sel" }, /* pdm out value when pdm_clk is higth , */ \ + { 0x6951, \ + "pdmdat_l_sel" }, /* pdm out value when pdm_clk is low , */ \ + { 0x6970, \ + "sam_spkr_sel" }, /* ram output on mode sam and audio , */ \ + { 0x6a02, \ + "rst_min_vbat_delay" }, /* rst_min_vbat delay (nb fs) , */ \ + { 0x6b00, \ + "disable_auto_engage" }, /* disable auto engange , */ \ + { 0x6b10, \ + "sel_tdm_data_valid" }, /* select tdm valid for speaker subsystem , */ \ + { 0x6c02, \ + "ns_hp2ln_criterion" }, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */ \ + { 0x6c32, \ + "ns_ln2hp_criterion" }, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */ \ + { 0x6c69, \ + "spare_out" }, /* spare_out , */ \ + { 0x6d0f, \ + "spare_in" }, /* spare_in , */ \ + { 0x6e00, \ + "flag_lp_detect_mode0" }, /* low power mode 0 detection , */ \ + { 0x6e10, \ + "flag_lp_detect_mode1" }, /* low power mode 1 detection , */ \ + { 0x6e20, \ + "flag_low_amplitude" }, /* low amplitude detection , */ \ + { 0x6e30, \ + "flag_vddp_gt_vbat" }, /* vddp greater than vbat , */ \ + { 0x6f02, \ + "cursense_comp_delay" }, /* delay to allign compensation signal with current sense signal, */ \ + { 0x6f40, \ + "cursense_comp_sign" }, /* polarity of compensation for current sense , */ \ + { 0x6f50, \ + "enbl_cursense_comp" }, /* enable current sense compensation , */ \ + { 0x6f60, \ + "sel_clip_pwms" }, /* Select pwm clip flag , */ \ + { 0x6f72, \ + "pwms_clip_lvl" }, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */ \ + { 0x7002, \ + "scnd_boost_voltage" }, /* Second boost voltage level , */ \ + { 0x7033, \ + "boost_cur" }, /* Max coil current , */ \ + { 0x7071, \ + "bst_slpcmplvl" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7090, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "boost_speed" }, /* Soft ramp up/down , */ \ + { 0x70e0, \ + "dcdcoff_mode" }, /* DCDC on/off , */ \ + { 0x70f0, \ + "dcdc_pwmonly" }, /* DCDC PWM only mode , */ \ + { 0x7104, \ + "bst_drive" }, /* Binary coded drive setting for boost converter power stage, */ \ + { 0x7151, \ + "bst_scalecur" }, /* For testing direct control scale current , */ \ + { 0x7174, \ + "bst_slopecur" }, /* For testing direct control slope current , */ \ + { 0x71c1, \ + "bst_slope" }, /* Boost slope speed , */ \ + { 0x71e0, \ + "bst_bypass_bstcur" }, /* Bypass control for boost current settings , */ \ + { 0x71f0, \ + "bst_bypass_bstfoldback" }, /* Bypass control for boost foldback , */ \ + { 0x7200, \ + "enbl_bst_engage" }, /* Enable power stage dcdc controller , */ \ + { 0x7210, \ + "enbl_bst_hizcom" }, /* Enable hiz comparator , */ \ + { 0x7220, \ + "enbl_bst_peak2avg" }, /* Enable boost peak2avg functionality , */ \ + { 0x7230, \ + "enbl_bst_peakcur" }, /* Enable peak current , */ \ + { 0x7240, \ + "enbl_bst_power" }, /* Enable line of the powerstage , */ \ + { 0x7250, \ + "enbl_bst_slopecur" }, /* Enable bit of max-current dac , */ \ + { 0x7260, \ + "enbl_bst_voutcomp" }, /* Enable vout comparators , */ \ + { 0x7270, \ + "enbl_bst_voutcomp86" }, /* Enable vout-86 comparators , */ \ + { 0x7280, \ + "enbl_bst_voutcomp93" }, /* Enable vout-93 comparators , */ \ + { 0x7290, \ + "enbl_bst_windac" }, /* Enable window dac , */ \ + { 0x72a5, \ + "bst_windac" }, /* for testing direct control windac , */ \ + { 0x7300, \ + "boost_alg" }, /* Control for boost adaptive loop gain , */ \ + { 0x7311, \ + "boost_loopgain" }, /* DCDC boost loopgain setting , */ \ + { 0x7331, \ + "bst_freq" }, /* DCDC boost frequency control , */ \ + { 0x7402, \ + "frst_boost_voltage" }, /* 1st boost voltage level , */ \ + { 0x7430, \ + "boost_track" }, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */ \ + { 0x7444, \ + "boost_trip_lvl_1st" }, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7494, \ + "boost_hold_time" }, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */ \ + { 0x74e0, \ + "sel_dcdc_envelope_8fs" }, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */ \ + { 0x74f0, \ + "ignore_flag_voutcomp86" }, /* Ignore flag_voutcomp86 , */ \ + { 0x7502, \ + "track_decay" }, /* DCDC Boost decay speed after a peak value, effective only when boost_track is set to 1, */ \ + { 0x7534, \ + "boost_trip_lvl_2nd" }, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7584, \ + "boost_trip_lvl_track" }, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0x7620, \ + "pga_test_ldo_bypass" }, /* bypass internal PGA LDO , */ \ + { 0x8001, \ + "sel_clk_cs" }, /* Current sense clock duty cycle control , */ \ + { 0x8021, \ + "micadc_speed" }, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */ \ + { 0x8050, \ + "cs_gain_control" }, /* Current sense gain control , */ \ + { 0x8060, \ + "cs_bypass_gc" }, /* Bypasses the CS gain correction , */ \ + { 0x8087, \ + "cs_gain" }, /* Current sense gain , */ \ + { 0x8200, \ + "enbl_cmfb" }, /* Current sense common mode feedback control , */ \ + { 0x8210, \ + "invertpwm" }, /* Current sense common mode feedback pwm invert control, */ \ + { 0x8222, \ + "cmfb_gain" }, /* Current sense common mode feedback control gain , */ \ + { 0x8254, \ + "cmfb_offset" }, /* Current sense common mode feedback control offset , */ \ + { 0x82a0, \ + "cs_sam_set" }, /* Enable SAM input for current sense , */ \ + { 0x8305, \ + "cs_ktemp" }, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */ \ + { 0x8400, \ + "cs_adc_bsoinv" }, /* Bitstream inversion for current sense ADC , */ \ + { 0x8421, \ + "cs_adc_hifreq" }, /* Frequency mode current sense ADC , */ \ + { 0x8440, \ + "cs_adc_nortz" }, /* Return to zero for current sense ADC , */ \ + { 0x8453, \ + "cs_adc_offset" }, /* Micadc ADC offset setting , */ \ + { 0x8490, \ + "cs_adc_slowdel" }, /* Select delay for current sense ADC (internal decision circuitry), */ \ + { 0x84a4, \ + "cs_adc_gain" }, /* Gain setting for current sense ADC (two's complement), */ \ + { 0x8500, \ + "cs_resonator_enable" }, /* Enable for resonator to improve SRN , */ \ + { 0x8510, \ + "cs_classd_tran_skip" }, /* Skip current sense connection during a classD amplifier transition, */ \ + { 0x8530, \ + "cs_inn_short" }, /* Short current sense negative to common mode , */ \ + { 0x8540, \ + "cs_inp_short" }, /* Short current sense positive to common mode , */ \ + { 0x8550, \ + "cs_ldo_bypass" }, /* Bypass current sense LDO , */ \ + { 0x8560, \ + "cs_ldo_pulldown" }, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */ \ + { 0x8574, \ + "cs_ldo_voset" }, /* Current sense LDO voltage level setting (two's complement), */ \ + { 0x8700, \ + "enbl_cs_adc" }, /* Enable current sense ADC , */ \ + { 0x8710, \ + "enbl_cs_inn1" }, /* Enable connection of current sense negative1 , */ \ + { 0x8720, \ + "enbl_cs_inn2" }, /* Enable connection of current sense negative2 , */ \ + { 0x8730, \ + "enbl_cs_inp1" }, /* Enable connection of current sense positive1 , */ \ + { 0x8740, \ + "enbl_cs_inp2" }, /* Enable connection of current sense positive2 , */ \ + { 0x8750, \ + "enbl_cs_ldo" }, /* Enable current sense LDO , */ \ + { 0x8760, \ + "enbl_cs_nofloating_n" }, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8770, \ + "enbl_cs_nofloating_p" }, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8780, \ + "enbl_cs_vbatldo" }, /* Enable of current sense LDO , */ \ + { 0x8800, \ + "volsense_pwm_sel" }, /* Voltage sense PWM source selection control , */ \ + { 0x8810, \ + "vol_cur_sense_dc_offset" }, /* voltage and current sense decimator offset control, */ \ + { 0xa007, \ + "mtpkey1" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0xa107, \ + "mtpkey2" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "key01_locked" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "key02_locked" }, /* Indicates KEY2 is locked , */ \ + { 0xa302, \ + "mtp_man_address_in" }, /* MTP address from I2C register for read/writing mtp in manual single word mode, */ \ + { 0xa330, \ + "man_copy_mtp_to_iic" }, /* Start copying single word from mtp to I2C mtp register, */ \ + { 0xa340, \ + "man_copy_iic_to_mtp" }, /* Start copying single word from I2C mtp register to mtp, */ \ + { 0xa350, \ + "auto_copy_mtp_to_iic" }, /* Start copying all the data from mtp to I2C mtp registers, */ \ + { 0xa360, \ + "auto_copy_iic_to_mtp" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa400, \ + "faim_set_clkws" }, /* Sets the faim controller clock wait state register, */ \ + { 0xa410, \ + "faim_sel_evenrows" }, /* All even rows of the faim are selected, active high, */ \ + { 0xa420, \ + "faim_sel_oddrows" }, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */ \ + { 0xa430, \ + "faim_program_only" }, /* Skip the erase access at wr_faim command (write-program-marginread), */ \ + { 0xa440, \ + "faim_erase_only" }, /* Skip the program access at wr_faim command (write-erase-marginread), */ \ + { 0xa50f, \ + "mtp_man_data_out_msb" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "mtp_man_data_out_lsb" }, /* LSB word of MTP manual read data , */ \ + { 0xa70f, \ + "mtp_man_data_in_msb" }, /* MSB word of write data for MTP manual write , */ \ + { 0xa80f, \ + "mtp_man_data_in_lsb" }, /* LSB word of write data for MTP manual write , */ \ + { 0xb010, \ + "bypass_ocpcounter" }, /* Bypass OCP Counter , */ \ + { 0xb020, \ + "bypass_glitchfilter" }, /* Bypass glitch filter , */ \ + { 0xb030, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0xb040, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0xb050, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0xb060, \ + "bypass_lost_clk" }, /* Bypass lost clock detector , */ \ + { 0xb070, \ + "ctrl_vpalarm" }, /* vpalarm (uvp ovp handling) , */ \ + { 0xb087, \ + "ocp_threshold" }, /* OCP threshold level , */ \ + { 0xb108, \ + "ext_temp" }, /* External temperature (C) , */ \ + { 0xb190, \ + "ext_temp_sel" }, /* Select temp Speaker calibration , */ \ + { 0xc000, \ + "use_direct_ctrls" }, /* Direct control to overrule several functions for testing, */ \ + { 0xc010, \ + "rst_datapath" }, /* Direct control for datapath reset , */ \ + { 0xc020, \ + "rst_cgu" }, /* Direct control for cgu reset , */ \ + { 0xc038, \ + "enbl_ref" }, /* Switch on the analog references, each part of the references can be switched on/off individually, */ \ + { 0xc0d0, \ + "enbl_ringo" }, /* Enable the ring oscillator for test purpose , */ \ + { 0xc0e0, \ + "use_direct_clk_ctrl" }, /* Direct clock control to overrule several functions for testing, */ \ + { 0xc0f0, \ + "use_direct_pll_ctrl" }, /* Direct PLL control to overrule several functions for testing, */ \ + { 0xc100, \ + "enbl_tsense" }, /* Temperature sensor enable control - I2C direct mode, */ \ + { 0xc110, \ + "tsense_hibias" }, /* Bit to set the biasing in temp sensor to high , */ \ + { 0xc120, \ + "enbl_flag_vbg" }, /* Enable flagging of bandgap out of control , */ \ + { 0xc20f, \ + "abist_offset" }, /* Offset control for ABIST testing (two's complement), */ \ + { 0xc300, \ + "bypasslatch" }, /* Bypass latch , */ \ + { 0xc311, \ + "sourcea" }, /* Set OUTA to , */ \ + { 0xc331, \ + "sourceb" }, /* Set OUTB to , */ \ + { 0xc350, \ + "inverta" }, /* Invert pwma test signal , */ \ + { 0xc360, \ + "invertb" }, /* Invert pwmb test signal , */ \ + { 0xc374, \ + "pulselength" }, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */ \ + { 0xc3c0, \ + "tdm_enable_loopback" }, /* TDM loopback test , */ \ + { 0xc400, \ + "bst_bypasslatch" }, /* Bypass latch in boost converter , */ \ + { 0xc411, \ + "bst_source" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0xc430, \ + "bst_invertb" }, /* Invert pwmbst test signal , */ \ + { 0xc444, \ + "bst_pulselength" }, /* Pulse length setting test input for boost converter , */ \ + { 0xc490, \ + "test_bst_ctrlsthv" }, /* Test mode for boost control stage , */ \ + { 0xc4a0, \ + "test_bst_iddq" }, /* IDDQ testing in power stage of boost converter , */ \ + { 0xc4b0, \ + "test_bst_rdson" }, /* RDSON testing - boost power stage , */ \ + { 0xc4c0, \ + "test_bst_cvi" }, /* CVI testing - boost power stage , */ \ + { 0xc4d0, \ + "test_bst_ocp" }, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */ \ + { 0xc4e0, \ + "test_bst_sense" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0xc500, \ + "test_cvi" }, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */ \ + { 0xc510, \ + "test_discrete" }, /* Test function noise measurement , */ \ + { 0xc520, \ + "test_iddq" }, /* Set the power stages in iddq mode for gate stress., */ \ + { 0xc540, \ + "test_rdson" }, /* Analog BIST, switch to enable Rdson measurement , */ \ + { 0xc550, \ + "test_sdelta" }, /* Analog BIST, noise test , */ \ + { 0xc570, \ + "test_enbl_cs" }, /* Enable for digimux mode of current sense , */ \ + { 0xc5b0, \ + "pga_test_enable" }, /* Enable PGA test mode , */ \ + { 0xc5c0, \ + "pga_test_offset_enable" }, /* Enable PGA test offset , */ \ + { 0xc5d0, \ + "pga_test_shortinput_enable" }, /* Enable PGA test shortinput , */ \ + { 0xc600, \ + "enbl_pwm_dcc" }, /* Enables direct control of pwm duty cycle for DCDC power stage, */ \ + { 0xc613, \ + "pwm_dcc_cnt" }, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0xc650, \ + "enbl_ldo_stress" }, /* Enable stress of internal supply voltages powerstages, */ \ + { 0xc707, \ + "digimuxa_sel" }, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */ \ + { 0xc787, \ + "digimuxb_sel" }, /* DigimuxB input selection control routed to INT (see Digimux list for details), */ \ + { 0xc807, \ + "digimuxc_sel" }, /* DigimuxC input selection control routed to PDMDAT (see Digimux list for details), */ \ + { 0xc981, \ + "int_ehs" }, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc9c0, \ + "hs_mode" }, /* I2C high speed mode control , */ \ + { 0xca00, \ + "enbl_anamux1" }, /* Enable anamux1 , */ \ + { 0xca10, \ + "enbl_anamux2" }, /* Enable anamux2 , */ \ + { 0xca20, \ + "enbl_anamux3" }, /* Enable anamux3 , */ \ + { 0xca30, \ + "enbl_anamux4" }, /* Enable anamux4 , */ \ + { 0xca74, \ + "anamux1" }, /* Anamux selection control - anamux on TEST1 , */ \ + { 0xcb04, \ + "anamux2" }, /* Anamux selection control - anamux on TEST2 , */ \ + { 0xcb54, \ + "anamux3" }, /* Anamux selection control - anamux on TEST3 , */ \ + { 0xcba4, \ + "anamux4" }, /* Anamux selection control - anamux on TEST4 , */ \ + { 0xcd05, \ + "pll_seli" }, /* PLL SELI - I2C direct PLL control mode only , */ \ + { 0xcd64, \ + "pll_selp" }, /* PLL SELP - I2C direct PLL control mode only , */ \ + { 0xcdb3, \ + "pll_selr" }, /* PLL SELR - I2C direct PLL control mode only , */ \ + { 0xcdf0, \ + "pll_frm" }, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */ \ + { 0xce09, \ + "pll_ndec" }, /* PLL NDEC - I2C direct PLL control mode only , */ \ + { 0xcea0, \ + "pll_mdec_msb" }, /* MSB of pll_mdec - I2C direct PLL control mode only, */ \ + { 0xceb0, \ + "enbl_pll" }, /* Enables PLL in I2C direct PLL control mode only , */ \ + { 0xcec0, \ + "enbl_osc" }, /* Enables OSC1M in I2C direct control mode only , */ \ + { 0xced0, \ + "pll_bypass" }, /* PLL bypass control in I2C direct PLL control mode only, */ \ + { 0xcee0, \ + "pll_directi" }, /* PLL directi control in I2C direct PLL control mode only, */ \ + { 0xcef0, \ + "pll_directo" }, /* PLL directo control in I2C direct PLL control mode only, */ \ + { 0xcf0f, \ + "pll_mdec_lsb" }, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */ \ + { 0xd006, \ + "pll_pdec" }, /* PLL PDEC - I2C direct PLL control mode only , */ \ + { 0xd10f, \ + "tsig_freq_lsb" }, /* Internal sinus test generator frequency control , */ \ + { 0xd202, \ + "tsig_freq_msb" }, /* Select internal sinus test generator, frequency control msb bits, */ \ + { 0xd230, \ + "inject_tsig" }, /* Control bit to switch to internal sinus test generator, */ \ + { 0xd283, \ + "tsig_gain" }, /* Test signal gain , */ \ + { 0xd300, \ + "adc10_reset" }, /* Reset for ADC10 - I2C direct control mode , */ \ + { 0xd311, \ + "adc10_test" }, /* Test mode selection signal for ADC10 - I2C direct control mode, */ \ + { 0xd332, \ + "adc10_sel" }, /* Select the input to convert for ADC10 - I2C direct control mode, */ \ + { 0xd364, \ + "adc10_prog_sample" }, /* ADC10 program sample setting - I2C direct control mode, */ \ + { 0xd3b0, \ + "adc10_enbl" }, /* Enable ADC10 - I2C direct control mode , */ \ + { 0xd3c0, \ + "bypass_lp_vbat" }, /* Bypass control for Low pass filter in batt sensor , */ \ + { 0xd409, \ + "data_adc10_tempbat" }, /* ADC 10 data output data for testing , */ \ + { 0xd507, \ + "ctrl_digtoana_hidden" }, /* Spare digital to analog control bits - Hidden , */ \ + { 0xd580, \ + "enbl_clk_out_of_range" }, /* Clock out of range , */ \ + { 0xd621, \ + "clkdiv_audio_sel" }, /* Audio clock divider selection in direct clock control mode, */ \ + { 0xd641, \ + "clkdiv_muxa_sel" }, /* DCDC MUXA clock divider selection in direct clock control mode, */ \ + { 0xd661, \ + "clkdiv_muxb_sel" }, /* DCDC MUXB clock divider selection in direct clock control mode, */ \ + { 0xd701, \ + "pdmdat_ehs" }, /* Speed/load setting for PDMDAT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xd721, \ + "datao_ehs" }, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xd740, \ + "bck_ehs" }, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xd750, \ + "datai_ehs" }, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xd760, \ + "pdmclk_ehs" }, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xd800, \ + "source_in_testmode" }, /* tdm source in test mode (return only current and voltage sense), */ \ + { 0xd810, \ + "gainatt_feedback" }, /* gainatt feedback to tdm , */ \ + { 0xd822, \ + "test_parametric_io" }, /* test io parametric , */ \ + { 0xd850, \ + "ctrl_bst_clk_lp1" }, /* boost clock control in low power mode1 , */ \ + { 0xd861, \ + "test_spare_out1" }, /* test spare out 1 , */ \ + { 0xd880, \ + "bst_dcmbst" }, /* dcm boost , */ \ + { 0xd890, \ + "pdm_loopback" }, /* pdm loop back to tdm , */ \ + { 0xd8a1, \ + "force_pga_clock" }, /* force pga clock , */ \ + { 0xd8c3, \ + "test_spare_out2" }, /* test spare out 1 , */ \ + { 0xee0f, \ + "sw_profile" }, /* Software profile data , */ \ + { 0xef0f, \ + "sw_vstep" }, /* Software vstep information , */ \ + { 0xf000, \ + "calibration_onetime" }, /* Calibration schedule , */ \ + { 0xf010, \ + "calibr_ron_done" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "calibr_dcdc_api_calibrate" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "calibr_dcdc_delta_sign" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "calibr_dcdc_delta" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "calibr_speaker_info" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf105, \ + "calibr_vout_offset" }, /* DCDC offset calibration 2's complement (key1 protected), */ \ + { 0xf163, \ + "spare_mpt1_9_6" }, /* HW gain module - left channel (2's complement) , */ \ + { 0xf1a5, \ + "spare_mpt1_15_10" }, /* Offset for amplifier, HW gain module - left channel (2's complement), */ \ + { 0xf203, \ + "calibr_gain" }, /* HW gain module (2's complement) , */ \ + { 0xf245, \ + "calibr_offset" }, /* Offset for amplifier, HW gain module (2's complement), */ \ + { 0xf2a3, \ + "spare_mpt2_13_10" }, /* Trimming of LDO (2.7V) , */ \ + { 0xf307, \ + "spare_mpt3_7_0" }, /* SPARE , */ \ + { 0xf387, \ + "calibr_gain_cs" }, /* Current sense gain (signed two's complement format), */ \ + { 0xf40f, \ + "spare_mtp4_15_0" }, /* SPARE , */ \ + { 0xf50f, \ + "calibr_R25C_R" }, /* Ron resistance of speaker coil , */ \ + { 0xf606, \ + "spare_mpt6_6_0" }, /* SPARE , */ \ + { 0xf686, \ + "spare_mpt6_14_8" }, /* Offset of left amplifier level shifter B , */ \ + { 0xf706, \ + "ctrl_offset_a" }, /* Offset of level shifter A , */ \ + { 0xf786, \ + "ctrl_offset_b" }, /* Offset of amplifier level shifter B , */ \ + { 0xf806, \ + "htol_iic_addr" }, /* 7-bit I2C address to be used during HTOL testing , */ \ + { 0xf870, \ + "htol_iic_addr_en" }, /* HTOL I2C address enable control , */ \ + { 0xf884, \ + "calibr_temp_offset" }, /* Temperature offset 2's compliment (key1 protected), */ \ + { 0xf8d2, \ + "calibr_temp_gain" }, /* Temperature gain 2's compliment (key1 protected) , */ \ + { 0xf900, \ + "mtp_lock_dcdcoff_mode" }, /* Disable function dcdcoff_mode , */ \ + { 0xf910, \ + "disable_sam_mode" }, /* Disable same mode , */ \ + { 0xf920, \ + "mtp_lock_bypass_clipper" }, /* Disable function bypass_clipper , */ \ + { 0xf930, \ + "mtp_lock_max_dcdc_voltage" }, /* Disable programming of max dcdc boost voltage , */ \ + { 0xf943, \ + "calibr_vbg_trim" }, /* Bandgap trimming control , */ \ + { 0xf980, \ + "mtp_enbl_amp_in_state_alarm" }, /* Enbl_amp in alarm state , */ \ + { 0xf990, \ + "mtp_enbl_pwm_delay_clock_gating" }, /* pwm delay clock auto gating , */ \ + { 0xf9a0, \ + "mtp_enbl_ocp_clock_gating" }, /* ocpclock auto gating , */ \ + { 0xf9b0, \ + "mtp_gate_cgu_clock_for_test" }, /* cgu test clock control , */ \ + { 0xf9c3, \ + "spare_mtp9_15_12" }, /* MTP-control FW - See Firmware I2C API document for details, */ \ + { 0xfa0f, \ + "mtpdataA" }, /* MTPdataA (key1 protected) , */ \ + { 0xfb0f, \ + "mtpdataB" }, /* MTPdataB (key1 protected) , */ \ + { 0xfc0f, \ + "mtpdataC" }, /* MTPdataC (key1 protected) , */ \ + { 0xfd0f, \ + "mtpdataD" }, /* MTPdataD (key1 protected) , */ \ + { 0xfe0f, \ + "mtpdataE" }, /* MTPdataE (key1 protected) , */ \ + { 0xff07, \ + "calibr_osc_delta_ndiv" }, /* Calibration data for OSC1M, signed number representation, */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +enum TFA9872_irq { + TFA9872_irq_stvdds = 0, + TFA9872_irq_stplls = 1, + TFA9872_irq_stotds = 2, + TFA9872_irq_stovds = 3, + TFA9872_irq_stuvds = 4, + TFA9872_irq_stclks = 5, + TFA9872_irq_stmtpb = 6, + TFA9872_irq_stnoclk = 7, + TFA9872_irq_stsws = 10, + TFA9872_irq_stamps = 12, + TFA9872_irq_starefs = 13, + TFA9872_irq_stadccr = 14, + TFA9872_irq_stbstcu = 16, + TFA9872_irq_stbsthi = 17, + TFA9872_irq_stbstoc = 18, + TFA9872_irq_stbstpkcur = 19, + TFA9872_irq_stbstvc = 20, + TFA9872_irq_stbst86 = 21, + TFA9872_irq_stbst93 = 22, + TFA9872_irq_stocpr = 25, + TFA9872_irq_stmwsrc = 26, + TFA9872_irq_stmwsmu = 28, + TFA9872_irq_stclkoor = 31, + TFA9872_irq_sttdmer = 32, + TFA9872_irq_stclpr = 34, + TFA9872_irq_stlp0 = 36, + TFA9872_irq_stlp1 = 37, + TFA9872_irq_stla = 38, + TFA9872_irq_stvddph = 39, + TFA9872_irq_max = 40, + TFA9872_irq_all = -1 /* all irqs */ +}; + +#define TFA9872_IRQ_NAMETABLE \ + static tfaIrqName_t Tfa9872IrqNames[] = { \ + { 0, "STVDDS" }, { 1, "STPLLS" }, { 2, "STOTDS" }, \ + { 3, "STOVDS" }, { 4, "STUVDS" }, { 5, "STCLKS" }, \ + { 6, "STMTPB" }, { 7, "STNOCLK" }, { 8, "8" }, \ + { 9, "9" }, { 10, "STSWS" }, { 11, "11" }, \ + { 12, "STAMPS" }, { 13, "STAREFS" }, { 14, "STADCCR" }, \ + { 15, "15" }, { 16, "STBSTCU" }, { 17, "STBSTHI" }, \ + { 18, "STBSTOC" }, { 19, "STBSTPKCUR" }, { 20, "STBSTVC" }, \ + { 21, "STBST86" }, { 22, "STBST93" }, { 23, "23" }, \ + { 24, "24" }, { 25, "STOCPR" }, { 26, "STMWSRC" }, \ + { 27, "27" }, { 28, "STMWSMU" }, { 29, "29" }, \ + { 30, "30" }, { 31, "STCLKOOR" }, { 32, "STTDMER" }, \ + { 33, "33" }, { 34, "STCLPR" }, { 35, "35" }, \ + { 36, "STLP0" }, { 37, "STLP1" }, { 38, "STLA" }, \ + { 39, "STVDDPH" }, { 40, "40" }, \ + }; +#endif /* _TFA9872_TFAFIELDNAMES_H */ \ No newline at end of file diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9874_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9874_tfafieldnames.h new file mode 100644 index 000000000000..06aba84cb547 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9874_tfafieldnames.h @@ -0,0 +1,1612 @@ +/** Filename: tfa9874_tfafieldnames.h + * This file was generated automatically on 08/22/17 at 13:43:43. + * Source file: TFA9874N1C0_DefaultI2CSettings.xlsx + */ + +#ifndef _TFA9874_TFAFIELDNAMES_H +#define _TFA9874_TFAFIELDNAMES_H + +#define TFA9874_I2CVERSION 1 + +typedef enum nxpTfa9874BfEnumList { + TFA9874_BF_PWDN = + 0x0000, /*!< Powerdown selection */ + TFA9874_BF_I2CR = + 0x0010, /*!< I2C Reset - Auto clear */ + TFA9874_BF_AMPE = + 0x0030, /*!< Activate Amplifier */ + TFA9874_BF_DCA = + 0x0040, /*!< Activate DC-to-DC converter */ + TFA9874_BF_INTP = + 0x0071, /*!< Interrupt config */ + TFA9874_BF_BYPOCP = + 0x00b0, /*!< Bypass OCP */ + TFA9874_BF_TSTOCP = + 0x00c0, /*!< OCP testing control */ + TFA9874_BF_MANSCONF = + 0x0120, /*!< I2C configured */ + TFA9874_BF_MANAOOSC = + 0x0140, /*!< Internal osc off at PWDN */ + TFA9874_BF_MUTETO = + 0x01d0, /*!< Time out SB mute sequence */ + TFA9874_BF_OPENMTP = + 0x01e0, /*!< Control for FAIM protection */ + TFA9874_BF_AUDFS = + 0x0203, /*!< Sample rate (fs) */ + TFA9874_BF_INPLEV = + 0x0240, /*!< TDM output attenuation */ + TFA9874_BF_FRACTDEL = + 0x0255, /*!< V/I Fractional delay */ + TFA9874_BF_REV = + 0x030f, /*!< Revision info */ + TFA9874_BF_REFCKEXT = + 0x0401, /*!< PLL external ref clock */ + TFA9874_BF_REFCKSEL = + 0x0420, /*!< PLL internal ref clock */ + TFA9874_BF_SSFAIME = + 0x05c0, /*!< Sub-system FAIM */ + TFA9874_BF_AMPOCRT = + 0x0802, /*!< Amplifier on-off criteria for shutdown */ + TFA9874_BF_VDDS = + 0x1000, /*!< POR */ + TFA9874_BF_DCOCPOK = + 0x1010, /*!< DCDC OCP nmos (sticky register , clear on read) */ + TFA9874_BF_OTDS = + 0x1020, /*!< OTP alarm (sticky register , clear on read) */ + TFA9874_BF_OCDS = + 0x1030, /*!< OCP amplifier (sticky register , clear on read) */ + TFA9874_BF_UVDS = + 0x1040, /*!< UVP alarm (sticky register , clear on read) */ + TFA9874_BF_MANALARM = + 0x1050, /*!< Alarm state */ + TFA9874_BF_TDMERR = + 0x1060, /*!< TDM error */ + TFA9874_BF_NOCLK = + 0x1070, /*!< Lost clock (sticky register , clear on read) */ + TFA9874_BF_DCIL = + 0x1100, /*!< DCDC current limiting */ + TFA9874_BF_DCDCA = + 0x1110, /*!< DCDC active (sticky register , clear on read) */ + TFA9874_BF_DCHVBAT = + 0x1130, /*!< DCDC level 1x */ + TFA9874_BF_DCH114 = + 0x1140, /*!< DCDC level 1.14x */ + TFA9874_BF_DCH107 = + 0x1150, /*!< DCDC level 1.07x */ + TFA9874_BF_PLLS = + 0x1160, /*!< PLL lock */ + TFA9874_BF_CLKS = + 0x1170, /*!< Clocks stable */ + TFA9874_BF_TDMLUTER = + 0x1180, /*!< TDM LUT error */ + TFA9874_BF_TDMSTAT = + 0x1192, /*!< TDM status bits */ + TFA9874_BF_MTPB = + 0x11c0, /*!< MTP busy */ + TFA9874_BF_SWS = + 0x11d0, /*!< Amplifier engage */ + TFA9874_BF_AMPS = + 0x11e0, /*!< Amplifier enable */ + TFA9874_BF_AREFS = + 0x11f0, /*!< References enable */ + TFA9874_BF_OCPOAP = + 0x1300, /*!< OCPOK pmos A */ + TFA9874_BF_OCPOAN = + 0x1310, /*!< OCPOK nmos A */ + TFA9874_BF_OCPOBP = + 0x1320, /*!< OCPOK pmos B */ + TFA9874_BF_OCPOBN = + 0x1330, /*!< OCPOK nmos B */ + TFA9874_BF_OVDS = + 0x1380, /*!< OVP alarm */ + TFA9874_BF_CLIPS = + 0x1390, /*!< Amplifier clipping */ + TFA9874_BF_ADCCR = + 0x13a0, /*!< Control ADC */ + TFA9874_BF_MANWAIT1 = + 0x13c0, /*!< Wait HW I2C settings */ + TFA9874_BF_MANMUTE = + 0x13e0, /*!< Audio mute sequence */ + TFA9874_BF_MANOPER = + 0x13f0, /*!< Operating state */ + TFA9874_BF_CLKOOR = + 0x1420, /*!< External clock status */ + TFA9874_BF_MANSTATE = + 0x1433, /*!< Device manager status */ + TFA9874_BF_DCMODE = + 0x1471, /*!< DCDC mode status bits */ + TFA9874_BF_BATS = + 0x1509, /*!< Battery voltage (V) */ + TFA9874_BF_TEMPS = + 0x1608, /*!< IC Temperature (C) */ + TFA9874_BF_VDDPS = + 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */ + TFA9874_BF_TDME = + 0x2040, /*!< Enable interface */ + TFA9874_BF_TDMMODE = + 0x2050, /*!< Slave/master */ + TFA9874_BF_TDMCLINV = + 0x2060, /*!< Reception data to BCK clock */ + TFA9874_BF_TDMFSLN = + 0x2073, /*!< FS length (master mode only) */ + TFA9874_BF_TDMFSPOL = + 0x20b0, /*!< FS polarity */ + TFA9874_BF_TDMNBCK = + 0x20c3, /*!< N-BCK's in FS */ + TFA9874_BF_TDMSLOTS = + 0x2103, /*!< N-slots in Frame */ + TFA9874_BF_TDMSLLN = + 0x2144, /*!< N-bits in slot */ + TFA9874_BF_TDMBRMG = + 0x2194, /*!< N-bits remaining */ + TFA9874_BF_TDMDEL = + 0x21e0, /*!< data delay to FS */ + TFA9874_BF_TDMADJ = + 0x21f0, /*!< data adjustment */ + TFA9874_BF_TDMOOMP = + 0x2201, /*!< Received audio compression */ + TFA9874_BF_TDMSSIZE = + 0x2224, /*!< Sample size per slot */ + TFA9874_BF_TDMTXDFO = + 0x2271, /*!< Format unused bits */ + TFA9874_BF_TDMTXUS0 = + 0x2291, /*!< Format unused slots DATAO */ + TFA9874_BF_TDMSPKE = + 0x2300, /*!< Control audio tdm channel in 0 (spkr + dcdc) */ + TFA9874_BF_TDMDCE = + 0x2310, /*!< Control audio tdm channel in 1 (dcdc) */ + TFA9874_BF_TDMCSE = + 0x2330, /*!< current sense vbat temperature and vddp feedback */ + TFA9874_BF_TDMVSE = + 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */ + TFA9874_BF_TDMSPKS = + 0x2603, /*!< tdm slot for sink 0 (speaker + dcdc) */ + TFA9874_BF_TDMDCS = + 0x2643, /*!< tdm slot for sink 1 (dcdc) */ + TFA9874_BF_TDMCSS = + 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */ + TFA9874_BF_TDMVSS = + 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */ + TFA9874_BF_ISTVDDS = + 0x4000, /*!< Status POR */ + TFA9874_BF_ISTBSTOC = + 0x4010, /*!< Status DCDC OCP */ + TFA9874_BF_ISTOTDS = + 0x4020, /*!< Status OTP alarm */ + TFA9874_BF_ISTOCPR = + 0x4030, /*!< Status ocp alarm */ + TFA9874_BF_ISTUVDS = + 0x4040, /*!< Status UVP alarm */ + TFA9874_BF_ISTMANALARM = + 0x4050, /*!< Status nanager Alarm state */ + TFA9874_BF_ISTTDMER = + 0x4060, /*!< Status tdm error */ + TFA9874_BF_ISTNOCLK = + 0x4070, /*!< Status lost clock */ + TFA9874_BF_ICLVDDS = + 0x4400, /*!< Clear POR */ + TFA9874_BF_ICLBSTOC = + 0x4410, /*!< Clear DCDC OCP */ + TFA9874_BF_ICLOTDS = + 0x4420, /*!< Clear OTP alarm */ + TFA9874_BF_ICLOCPR = + 0x4430, /*!< Clear ocp alarm */ + TFA9874_BF_ICLUVDS = + 0x4440, /*!< Clear UVP alarm */ + TFA9874_BF_ICLMANALARM = + 0x4450, /*!< clear nanager Alarm state */ + TFA9874_BF_ICLTDMER = + 0x4460, /*!< Clear tdm error */ + TFA9874_BF_ICLNOCLK = + 0x4470, /*!< Clear lost clk */ + TFA9874_BF_IEVDDS = + 0x4800, /*!< Enable por */ + TFA9874_BF_IEBSTOC = + 0x4810, /*!< Enable DCDC OCP */ + TFA9874_BF_IEOTDS = + 0x4820, /*!< Enable OTP alarm */ + TFA9874_BF_IEOCPR = + 0x4830, /*!< Enable ocp alarm */ + TFA9874_BF_IEUVDS = + 0x4840, /*!< Enable UVP alarm */ + TFA9874_BF_IEMANALARM = + 0x4850, /*!< Enable nanager Alarm state */ + TFA9874_BF_IETDMER = + 0x4860, /*!< Enable tdm error */ + TFA9874_BF_IENOCLK = + 0x4870, /*!< Enable lost clk */ + TFA9874_BF_IPOVDDS = + 0x4c00, /*!< Polarity por */ + TFA9874_BF_IPOBSTOC = + 0x4c10, /*!< Polarity DCDC OCP */ + TFA9874_BF_IPOOTDS = + 0x4c20, /*!< Polarity OTP alarm */ + TFA9874_BF_IPOOCPR = + 0x4c30, /*!< Polarity ocp alarm */ + TFA9874_BF_IPOUVDS = + 0x4c40, /*!< Polarity UVP alarm */ + TFA9874_BF_IPOMANALARM = + 0x4c50, /*!< Polarity nanager Alarm state */ + TFA9874_BF_IPOTDMER = + 0x4c60, /*!< Polarity tdm error */ + TFA9874_BF_IPONOCLK = + 0x4c70, /*!< Polarity lost clk */ + TFA9874_BF_BSSCR = + 0x5001, /*!< Battery Safeguard attack time */ + TFA9874_BF_BSST = + 0x5023, /*!< Battery Safeguard threshold voltage level */ + TFA9874_BF_BSSRL = + 0x5061, /*!< Battery Safeguard maximum reduction */ + TFA9874_BF_VBATFLTL = + 0x5080, /*!< vbat filter limit */ + TFA9874_BF_BSSR = + 0x50e0, /*!< Battery voltage read out */ + TFA9874_BF_BSSBY = + 0x50f0, /*!< Bypass battery safeguard */ + TFA9874_BF_BSSS = + 0x5100, /*!< Vbat prot steepness */ + TFA9874_BF_HPFBYP = + 0x5150, /*!< Bypass HPF */ + TFA9874_BF_DPSA = + 0x5170, /*!< Enable DPSA */ + TFA9874_BF_CLIPCTRL = + 0x5222, /*!< Clip control setting */ + TFA9874_BF_AMPGAIN = + 0x5257, /*!< Amplifier gain */ + TFA9874_BF_SLOPEE = + 0x52d0, /*!< Enables slope control */ + TFA9874_BF_SLOPESET = + 0x52e0, /*!< Slope speed setting (bin. coded) */ + TFA9874_BF_TDMDCG = + 0x6123, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */ + TFA9874_BF_TDMSPKG = + 0x6163, /*!< Total gain depending on INPLEV setting (channel 0) */ + TFA9874_BF_LNMODE = + 0x62e1, /*!< ctrl select mode */ + TFA9874_BF_LPM1MODE = + 0x64e1, /*!< low power mode control */ + TFA9874_BF_TDMSRCMAP = + 0x6802, /*!< tdm source mapping */ + TFA9874_BF_TDMSRCAS = + 0x6831, /*!< Sensed value A */ + TFA9874_BF_TDMSRCBS = + 0x6851, /*!< Sensed value B */ + TFA9874_BF_TDMSRCACLIP = + 0x6871, /*!< clip information (analog /digital) for source0 */ + TFA9874_BF_TDMSRCBCLIP = + 0x6891, /*!< clip information (analog /digital) for source1 */ + TFA9874_BF_LP1 = + 0x6e10, /*!< low power mode 1 detection */ + TFA9874_BF_LA = + 0x6e20, /*!< low amplitude detection */ + TFA9874_BF_VDDPH = + 0x6e30, /*!< vddp greater than vbat */ + TFA9874_BF_DELCURCOMP = + 0x6f02, /*!< delay to allign compensation signal with current sense signal */ + TFA9874_BF_SIGCURCOMP = + 0x6f40, /*!< polarity of compensation for current sense */ + TFA9874_BF_ENCURCOMP = + 0x6f50, /*!< enable current sense compensation */ + TFA9874_BF_LVLCLPPWM = + 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */ + TFA9874_BF_DCMCC = + 0x7033, /*!< Max coil current */ + TFA9874_BF_DCCV = + 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */ + TFA9874_BF_DCIE = + 0x7090, /*!< Adaptive boost mode */ + TFA9874_BF_DCSR = + 0x70a0, /*!< Soft ramp up/down */ + TFA9874_BF_DCDIS = + 0x70e0, /*!< DCDC on/off */ + TFA9874_BF_DCPWM = + 0x70f0, /*!< DCDC PWM only mode */ + TFA9874_BF_DCTRACK = + 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */ + TFA9874_BF_DCTRIP = + 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */ + TFA9874_BF_DCHOLD = + 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */ + TFA9874_BF_DCTRIP2 = + 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */ + TFA9874_BF_DCTRIPT = + 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */ + TFA9874_BF_DCTRIPHYSTE = + 0x75f0, /*!< Enable hysteresis on booster trip levels */ + TFA9874_BF_DCVOF = + 0x7635, /*!< First boost voltage level */ + TFA9874_BF_DCVOS = + 0x7695, /*!< Second boost voltage level */ + TFA9874_BF_MTPK = + 0xa107, /*!< MTP KEY2 register */ + TFA9874_BF_KEY1LOCKED = + 0xa200, /*!< Indicates KEY1 is locked */ + TFA9874_BF_KEY2LOCKED = + 0xa210, /*!< Indicates KEY2 is locked */ + TFA9874_BF_CIMTP = + 0xa360, /*!< Start copying data from I2C mtp registers to mtp */ + TFA9874_BF_MTPRDMSB = + 0xa50f, /*!< MSB word of MTP manual read data */ + TFA9874_BF_MTPRDLSB = + 0xa60f, /*!< LSB word of MTP manual read data */ + TFA9874_BF_EXTTS = + 0xb108, /*!< External temperature (C) */ + TFA9874_BF_TROS = + 0xb190, /*!< Select temp Speaker calibration */ + TFA9874_BF_SWPROFIL = + 0xee0f, /*!< Software profile data */ + TFA9874_BF_SWVSTEP = + 0xef0f, /*!< Software vstep information */ + TFA9874_BF_MTPOTC = + 0xf000, /*!< Calibration schedule */ + TFA9874_BF_MTPEX = + 0xf010, /*!< Calibration Ron executed */ + TFA9874_BF_DCMCCAPI = + 0xf020, /*!< Calibration current limit DCDC */ + TFA9874_BF_DCMCCSB = + 0xf030, /*!< Sign bit for delta calibration current limit DCDC */ + TFA9874_BF_USERDEF = + 0xf042, /*!< Calibration delta current limit DCDC */ + TFA9874_BF_CUSTINFO = + 0xf078, /*!< Reserved space for allowing customer to store speaker information */ + TFA9874_BF_R25C = + 0xf50f, /*!< Ron resistance of speaker coil */ +} nxpTfa9874BfEnumList_t; +#define TFA9874_NAMETABLE \ + static tfaBfName_t Tfa9874DatasheetNames[] = { \ + { 0x0, \ + "PWDN" }, /* Powerdown selection , */ \ + { 0x10, \ + "I2CR" }, /* I2C Reset - Auto clear , */ \ + { 0x30, \ + "AMPE" }, /* Activate Amplifier , */ \ + { 0x40, \ + "DCA" }, /* Activate DC-to-DC converter , */ \ + { 0x71, \ + "INTP" }, /* Interrupt config , */ \ + { 0xb0, \ + "BYPOCP" }, /* Bypass OCP , */ \ + { 0xc0, \ + "TSTOCP" }, /* OCP testing control , */ \ + { 0x120, \ + "MANSCONF" }, /* I2C configured , */ \ + { 0x140, \ + "MANAOOSC" }, /* Internal osc off at PWDN , */ \ + { 0x1d0, \ + "MUTETO" }, /* Time out SB mute sequence , */ \ + { 0x1e0, \ + "OPENMTP" }, /* Control for FAIM protection , */ \ + { 0x203, \ + "AUDFS" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "INPLEV" }, /* TDM output attenuation , */ \ + { 0x255, \ + "FRACTDEL" }, /* V/I Fractional delay , */ \ + { 0x30f, \ + "REV" }, /* Revision info , */ \ + { 0x401, \ + "REFCKEXT" }, /* PLL external ref clock , */ \ + { 0x420, \ + "REFCKSEL" }, /* PLL internal ref clock , */ \ + { 0x5c0, \ + "SSFAIME" }, /* Sub-system FAIM , */ \ + { 0x802, \ + "AMPOCRT" }, /* Amplifier on-off criteria for shutdown , */ \ + { 0x1000, \ + "VDDS" }, /* POR , */ \ + { 0x1010, \ + "DCOCPOK" }, /* DCDC OCP nmos (sticky register , clear on read) , */ \ + { 0x1020, \ + "OTDS" }, /* OTP alarm (sticky register , clear on read) , */ \ + { 0x1030, \ + "OCDS" }, /* OCP amplifier (sticky register , clear on read), */ \ + { 0x1040, \ + "UVDS" }, /* UVP alarm (sticky register , clear on read) , */ \ + { 0x1050, \ + "MANALARM" }, /* Alarm state , */ \ + { 0x1060, \ + "TDMERR" }, /* TDM error , */ \ + { 0x1070, \ + "NOCLK" }, /* Lost clock (sticky register , clear on read) , */ \ + { 0x1100, \ + "DCIL" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "DCDCA" }, /* DCDC active (sticky register , clear on read) , */ \ + { 0x1130, \ + "DCHVBAT" }, /* DCDC level 1x , */ \ + { 0x1140, \ + "DCH114" }, /* DCDC level 1.14x , */ \ + { 0x1150, \ + "DCH107" }, /* DCDC level 1.07x , */ \ + { 0x1160, \ + "PLLS" }, /* PLL lock , */ \ + { 0x1170, \ + "CLKS" }, /* Clocks stable , */ \ + { 0x1180, \ + "TDMLUTER" }, /* TDM LUT error , */ \ + { 0x1192, \ + "TDMSTAT" }, /* TDM status bits , */ \ + { 0x11c0, \ + "MTPB" }, /* MTP busy , */ \ + { 0x11d0, \ + "SWS" }, /* Amplifier engage , */ \ + { 0x11e0, \ + "AMPS" }, /* Amplifier enable , */ \ + { 0x11f0, \ + "AREFS" }, /* References enable , */ \ + { 0x1300, \ + "OCPOAP" }, /* OCPOK pmos A , */ \ + { 0x1310, \ + "OCPOAN" }, /* OCPOK nmos A , */ \ + { 0x1320, \ + "OCPOBP" }, /* OCPOK pmos B , */ \ + { 0x1330, \ + "OCPOBN" }, /* OCPOK nmos B , */ \ + { 0x1380, \ + "OVDS" }, /* OVP alarm , */ \ + { 0x1390, \ + "CLIPS" }, /* Amplifier clipping , */ \ + { 0x13a0, \ + "ADCCR" }, /* Control ADC , */ \ + { 0x13c0, \ + "MANWAIT1" }, /* Wait HW I2C settings , */ \ + { 0x13e0, \ + "MANMUTE" }, /* Audio mute sequence , */ \ + { 0x13f0, \ + "MANOPER" }, /* Operating state , */ \ + { 0x1420, \ + "CLKOOR" }, /* External clock status , */ \ + { 0x1433, \ + "MANSTATE" }, /* Device manager status , */ \ + { 0x1471, \ + "DCMODE" }, /* DCDC mode status bits , */ \ + { 0x1509, \ + "BATS" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "TEMPS" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "VDDPS" }, /* IC VDDP voltage ( 1023*VDDP/13 V) , */ \ + { 0x2040, \ + "TDME" }, /* Enable interface , */ \ + { 0x2050, \ + "TDMMODE" }, /* Slave/master , */ \ + { 0x2060, \ + "TDMCLINV" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "TDMFSLN" }, /* FS length (master mode only) , */ \ + { 0x20b0, \ + "TDMFSPOL" }, /* FS polarity , */ \ + { 0x20c3, \ + "TDMNBCK" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "TDMSLOTS" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "TDMSLLN" }, /* N-bits in slot , */ \ + { 0x2194, \ + "TDMBRMG" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "TDMDEL" }, /* data delay to FS , */ \ + { 0x21f0, \ + "TDMADJ" }, /* data adjustment , */ \ + { 0x2201, \ + "TDMOOMP" }, /* Received audio compression , */ \ + { 0x2224, \ + "TDMSSIZE" }, /* Sample size per slot , */ \ + { 0x2271, \ + "TDMTXDFO" }, /* Format unused bits , */ \ + { 0x2291, \ + "TDMTXUS0" }, /* Format unused slots DATAO , */ \ + { 0x2300, \ + "TDMSPKE" }, /* Control audio tdm channel in 0 (spkr + dcdc) , */ \ + { 0x2310, \ + "TDMDCE" }, /* Control audio tdm channel in 1 (dcdc) , */ \ + { 0x2330, \ + "TDMCSE" }, /* current sense vbat temperature and vddp feedback , */ \ + { 0x2340, \ + "TDMVSE" }, /* Voltage sense vbat temperature and vddp feedback , */ \ + { 0x2603, \ + "TDMSPKS" }, /* tdm slot for sink 0 (speaker + dcdc) , */ \ + { 0x2643, \ + "TDMDCS" }, /* tdm slot for sink 1 (dcdc) , */ \ + { 0x26c3, \ + "TDMCSS" }, /* Slot Position of current sense vbat temperature and vddp feedback, */ \ + { 0x2703, \ + "TDMVSS" }, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */ \ + { 0x4000, \ + "ISTVDDS" }, /* Status POR , */ \ + { 0x4010, \ + "ISTBSTOC" }, /* Status DCDC OCP , */ \ + { 0x4020, \ + "ISTOTDS" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "ISTOCPR" }, /* Status ocp alarm , */ \ + { 0x4040, \ + "ISTUVDS" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "ISTMANALARM" }, /* Status nanager Alarm state , */ \ + { 0x4060, \ + "ISTTDMER" }, /* Status tdm error , */ \ + { 0x4070, \ + "ISTNOCLK" }, /* Status lost clock , */ \ + { 0x4400, \ + "ICLVDDS" }, /* Clear POR , */ \ + { 0x4410, \ + "ICLBSTOC" }, /* Clear DCDC OCP , */ \ + { 0x4420, \ + "ICLOTDS" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "ICLOCPR" }, /* Clear ocp alarm , */ \ + { 0x4440, \ + "ICLUVDS" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "ICLMANALARM" }, /* clear nanager Alarm state , */ \ + { 0x4460, \ + "ICLTDMER" }, /* Clear tdm error , */ \ + { 0x4470, \ + "ICLNOCLK" }, /* Clear lost clk , */ \ + { 0x4800, \ + "IEVDDS" }, /* Enable por , */ \ + { 0x4810, \ + "IEBSTOC" }, /* Enable DCDC OCP , */ \ + { 0x4820, \ + "IEOTDS" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "IEOCPR" }, /* Enable ocp alarm , */ \ + { 0x4840, \ + "IEUVDS" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "IEMANALARM" }, /* Enable nanager Alarm state , */ \ + { 0x4860, \ + "IETDMER" }, /* Enable tdm error , */ \ + { 0x4870, \ + "IENOCLK" }, /* Enable lost clk , */ \ + { 0x4c00, \ + "IPOVDDS" }, /* Polarity por , */ \ + { 0x4c10, \ + "IPOBSTOC" }, /* Polarity DCDC OCP , */ \ + { 0x4c20, \ + "IPOOTDS" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "IPOOCPR" }, /* Polarity ocp alarm , */ \ + { 0x4c40, \ + "IPOUVDS" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "IPOMANALARM" }, /* Polarity nanager Alarm state , */ \ + { 0x4c60, \ + "IPOTDMER" }, /* Polarity tdm error , */ \ + { 0x4c70, \ + "IPONOCLK" }, /* Polarity lost clk , */ \ + { 0x5001, \ + "BSSCR" }, /* Battery Safeguard attack time , */ \ + { 0x5023, \ + "BSST" }, /* Battery Safeguard threshold voltage level , */ \ + { 0x5061, \ + "BSSRL" }, /* Battery Safeguard maximum reduction , */ \ + { 0x5080, \ + "VBATFLTL" }, /* vbat filter limit , */ \ + { 0x50e0, \ + "BSSR" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "BSSBY" }, /* Bypass battery safeguard , */ \ + { 0x5100, \ + "BSSS" }, /* Vbat prot steepness , */ \ + { 0x5150, \ + "HPFBYP" }, /* Bypass HPF , */ \ + { 0x5170, \ + "DPSA" }, /* Enable DPSA , */ \ + { 0x5222, \ + "CLIPCTRL" }, /* Clip control setting , */ \ + { 0x5257, \ + "AMPGAIN" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "SLOPEE" }, /* Enables slope control , */ \ + { 0x52e0, \ + "SLOPESET" }, /* Slope speed setting (bin. coded) , */ \ + { 0x6123, \ + "TDMDCG" }, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */ \ + { 0x6163, \ + "TDMSPKG" }, /* Total gain depending on INPLEV setting (channel 0), */ \ + { 0x62e1, \ + "LNMODE" }, /* ctrl select mode , */ \ + { 0x64e1, \ + "LPM1MODE" }, /* low power mode control , */ \ + { 0x6802, \ + "TDMSRCMAP" }, /* tdm source mapping , */ \ + { 0x6831, \ + "TDMSRCAS" }, /* Sensed value A , */ \ + { 0x6851, \ + "TDMSRCBS" }, /* Sensed value B , */ \ + { 0x6871, \ + "TDMSRCACLIP" }, /* clip information (analog /digital) for source0 , */ \ + { 0x6891, \ + "TDMSRCBCLIP" }, /* clip information (analog /digital) for source1 , */ \ + { 0x6e10, \ + "LP1" }, /* low power mode 1 detection , */ \ + { 0x6e20, \ + "LA" }, /* low amplitude detection , */ \ + { 0x6e30, \ + "VDDPH" }, /* vddp greater than vbat , */ \ + { 0x6f02, \ + "DELCURCOMP" }, /* delay to allign compensation signal with current sense signal, */ \ + { 0x6f40, \ + "SIGCURCOMP" }, /* polarity of compensation for current sense , */ \ + { 0x6f50, \ + "ENCURCOMP" }, /* enable current sense compensation , */ \ + { 0x6f72, \ + "LVLCLPPWM" }, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */ \ + { 0x7033, \ + "DCMCC" }, /* Max coil current , */ \ + { 0x7071, \ + "DCCV" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7090, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "DCSR" }, /* Soft ramp up/down , */ \ + { 0x70e0, \ + "DCDIS" }, /* DCDC on/off , */ \ + { 0x70f0, \ + "DCPWM" }, /* DCDC PWM only mode , */ \ + { 0x7430, \ + "DCTRACK" }, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */ \ + { 0x7444, \ + "DCTRIP" }, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7494, \ + "DCHOLD" }, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */ \ + { 0x7534, \ + "DCTRIP2" }, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7584, \ + "DCTRIPT" }, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0x75f0, \ + "DCTRIPHYSTE" }, /* Enable hysteresis on booster trip levels , */ \ + { 0x7635, \ + "DCVOF" }, /* First boost voltage level , */ \ + { 0x7695, \ + "DCVOS" }, /* Second boost voltage level , */ \ + { 0xa107, \ + "MTPK" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "KEY1LOCKED" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "KEY2LOCKED" }, /* Indicates KEY2 is locked , */ \ + { 0xa360, \ + "CIMTP" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa50f, \ + "MTPRDMSB" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "MTPRDLSB" }, /* LSB word of MTP manual read data , */ \ + { 0xb108, \ + "EXTTS" }, /* External temperature (C) , */ \ + { 0xb190, \ + "TROS" }, /* Select temp Speaker calibration , */ \ + { 0xee0f, \ + "SWPROFIL" }, /* Software profile data , */ \ + { 0xef0f, \ + "SWVSTEP" }, /* Software vstep information , */ \ + { 0xf000, \ + "MTPOTC" }, /* Calibration schedule , */ \ + { 0xf010, \ + "MTPEX" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "DCMCCAPI" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "DCMCCSB" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "USERDEF" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "CUSTINFO" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf50f, \ + "R25C" }, /* Ron resistance of speaker coil , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9874_BITNAMETABLE \ + static tfaBfName_t Tfa9874BitNames[] = { \ + { 0x0, \ + "powerdown" }, /* Powerdown selection , */ \ + { 0x10, \ + "reset" }, /* I2C Reset - Auto clear , */ \ + { 0x30, \ + "enbl_amplifier" }, /* Activate Amplifier , */ \ + { 0x40, \ + "enbl_boost" }, /* Activate DC-to-DC converter , */ \ + { 0x71, \ + "int_pad_io" }, /* Interrupt config , */ \ + { 0xb0, \ + "bypass_ocp" }, /* Bypass OCP , */ \ + { 0xc0, \ + "test_ocp" }, /* OCP testing control , */ \ + { 0x120, \ + "src_set_configured" }, /* I2C configured , */ \ + { 0x140, \ + "enbl_osc1m_auto_off" }, /* Internal osc off at PWDN , */ \ + { 0x1d0, \ + "disable_mute_time_out" }, /* Time out SB mute sequence , */ \ + { 0x1e0, \ + "unprotect_faim" }, /* Control for FAIM protection , */ \ + { 0x203, \ + "audio_fs" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "input_level" }, /* TDM output attenuation , */ \ + { 0x255, \ + "cs_frac_delay" }, /* V/I Fractional delay , */ \ + { 0x2d0, \ + "sel_hysteresis" }, /* Select hysteresis for clock range detector , */ \ + { 0x30f, \ + "device_rev" }, /* Revision info , */ \ + { 0x401, \ + "pll_clkin_sel" }, /* PLL external ref clock , */ \ + { 0x420, \ + "pll_clkin_sel_osc" }, /* PLL internal ref clock , */ \ + { 0x5c0, \ + "enbl_faim_ss" }, /* Sub-system FAIM , */ \ + { 0x802, \ + "ctrl_on2off_criterion" }, /* Amplifier on-off criteria for shutdown , */ \ + { 0xe07, \ + "ctrl_digtoana" }, /* Spare control from digital to analog , */ \ + { 0xf0f, \ + "hidden_code" }, /* 5A6Bh, 23147d to access registers (default for engineering), */ \ + { 0x1000, \ + "flag_por" }, /* POR , */ \ + { 0x1010, \ + "flag_bst_ocpok" }, /* DCDC OCP nmos (sticky register , clear on read) , */ \ + { 0x1020, \ + "flag_otpok" }, /* OTP alarm (sticky register , clear on read) , */ \ + { 0x1030, \ + "flag_ocp_alarm" }, /* OCP amplifier (sticky register , clear on read), */ \ + { 0x1040, \ + "flag_uvpok" }, /* UVP alarm (sticky register , clear on read) , */ \ + { 0x1050, \ + "flag_man_alarm_state" }, /* Alarm state , */ \ + { 0x1060, \ + "flag_tdm_error" }, /* TDM error , */ \ + { 0x1070, \ + "flag_lost_clk" }, /* Lost clock (sticky register , clear on read) , */ \ + { 0x1100, \ + "flag_bst_bstcur" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "flag_bst_hiz" }, /* DCDC active (sticky register , clear on read) , */ \ + { 0x1120, \ + "flag_bst_peakcur" }, /* Indicates current is max in DC-to-DC converter , */ \ + { 0x1130, \ + "flag_bst_voutcomp" }, /* DCDC level 1x , */ \ + { 0x1140, \ + "flag_bst_voutcomp86" }, /* DCDC level 1.14x , */ \ + { 0x1150, \ + "flag_bst_voutcomp93" }, /* DCDC level 1.07x , */ \ + { 0x1160, \ + "flag_pll_lock" }, /* PLL lock , */ \ + { 0x1170, \ + "flag_clocks_stable" }, /* Clocks stable , */ \ + { 0x1180, \ + "flag_tdm_lut_error" }, /* TDM LUT error , */ \ + { 0x1192, \ + "flag_tdm_status" }, /* TDM status bits , */ \ + { 0x11c0, \ + "flag_mtp_busy" }, /* MTP busy , */ \ + { 0x11d0, \ + "flag_engage" }, /* Amplifier engage , */ \ + { 0x11e0, \ + "flag_enbl_amp" }, /* Amplifier enable , */ \ + { 0x11f0, \ + "flag_enbl_ref" }, /* References enable , */ \ + { 0x1300, \ + "flag_ocpokap" }, /* OCPOK pmos A , */ \ + { 0x1310, \ + "flag_ocpokan" }, /* OCPOK nmos A , */ \ + { 0x1320, \ + "flag_ocpokbp" }, /* OCPOK pmos B , */ \ + { 0x1330, \ + "flag_ocpokbn" }, /* OCPOK nmos B , */ \ + { 0x1380, \ + "flag_ovpok" }, /* OVP alarm , */ \ + { 0x1390, \ + "flag_clip" }, /* Amplifier clipping , */ \ + { 0x13a0, \ + "flag_adc10_ready" }, /* Control ADC , */ \ + { 0x13c0, \ + "flag_man_wait_src_settings" }, /* Wait HW I2C settings , */ \ + { 0x13e0, \ + "flag_man_start_mute_audio" }, /* Audio mute sequence , */ \ + { 0x13f0, \ + "flag_man_operating_state" }, /* Operating state , */ \ + { 0x1420, \ + "flag_clk_out_of_range" }, /* External clock status , */ \ + { 0x1433, \ + "man_state" }, /* Device manager status , */ \ + { 0x1471, \ + "status_bst_mode" }, /* DCDC mode status bits , */ \ + { 0x1509, \ + "bat_adc" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "temp_adc" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "vddp_adc" }, /* IC VDDP voltage ( 1023*VDDP/13 V) , */ \ + { 0x2040, \ + "tdm_enable" }, /* Enable interface , */ \ + { 0x2050, \ + "tdm_mode" }, /* Slave/master , */ \ + { 0x2060, \ + "tdm_clk_inversion" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "tdm_fs_ws_length" }, /* FS length (master mode only) , */ \ + { 0x20b0, \ + "tdm_fs_ws_polarity" }, /* FS polarity , */ \ + { 0x20c3, \ + "tdm_nbck" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "tdm_nb_of_slots" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "tdm_slot_length" }, /* N-bits in slot , */ \ + { 0x2194, \ + "tdm_bits_remaining" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "tdm_data_delay" }, /* data delay to FS , */ \ + { 0x21f0, \ + "tdm_data_adjustment" }, /* data adjustment , */ \ + { 0x2201, \ + "tdm_audio_sample_compression" }, /* Received audio compression , */ \ + { 0x2224, \ + "tdm_sample_size" }, /* Sample size per slot , */ \ + { 0x2271, \ + "tdm_txdata_format" }, /* Format unused bits , */ \ + { 0x2291, \ + "tdm_txdata_format_unused_slot_sd0" }, /* Format unused slots DATAO , */ \ + { 0x2300, \ + "tdm_sink0_enable" }, /* Control audio tdm channel in 0 (spkr + dcdc) , */ \ + { 0x2310, \ + "tdm_sink1_enable" }, /* Control audio tdm channel in 1 (dcdc) , */ \ + { 0x2330, \ + "tdm_source0_enable" }, /* current sense vbat temperature and vddp feedback , */ \ + { 0x2340, \ + "tdm_source1_enable" }, /* Voltage sense vbat temperature and vddp feedback , */ \ + { 0x2603, \ + "tdm_sink0_slot" }, /* tdm slot for sink 0 (speaker + dcdc) , */ \ + { 0x2643, \ + "tdm_sink1_slot" }, /* tdm slot for sink 1 (dcdc) , */ \ + { 0x26c3, \ + "tdm_source0_slot" }, /* Slot Position of current sense vbat temperature and vddp feedback, */ \ + { 0x2703, \ + "tdm_source1_slot" }, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */ \ + { 0x4000, \ + "int_out_flag_por" }, /* Status POR , */ \ + { 0x4010, \ + "int_out_flag_bst_ocpok" }, /* Status DCDC OCP , */ \ + { 0x4020, \ + "int_out_flag_otpok" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "int_out_flag_ocp_alarm" }, /* Status ocp alarm , */ \ + { 0x4040, \ + "int_out_flag_uvpok" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "int_out_flag_man_alarm_state" }, /* Status nanager Alarm state , */ \ + { 0x4060, \ + "int_out_flag_tdm_error" }, /* Status tdm error , */ \ + { 0x4070, \ + "int_out_flag_lost_clk" }, /* Status lost clock , */ \ + { 0x4400, \ + "int_in_flag_por" }, /* Clear POR , */ \ + { 0x4410, \ + "int_in_flag_bst_ocpok" }, /* Clear DCDC OCP , */ \ + { 0x4420, \ + "int_in_flag_otpok" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "int_in_flag_ocp_alarm" }, /* Clear ocp alarm , */ \ + { 0x4440, \ + "int_in_flag_uvpok" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "int_in_flag_man_alarm_state" }, /* clear nanager Alarm state , */ \ + { 0x4460, \ + "int_in_flag_tdm_error" }, /* Clear tdm error , */ \ + { 0x4470, \ + "int_in_flag_lost_clk" }, /* Clear lost clk , */ \ + { 0x4800, \ + "int_enable_flag_por" }, /* Enable por , */ \ + { 0x4810, \ + "int_enable_flag_bst_ocpok" }, /* Enable DCDC OCP , */ \ + { 0x4820, \ + "int_enable_flag_otpok" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "int_enable_flag_ocp_alarm" }, /* Enable ocp alarm , */ \ + { 0x4840, \ + "int_enable_flag_uvpok" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "int_enable_flag_man_alarm_state" }, /* Enable nanager Alarm state , */ \ + { 0x4860, \ + "int_enable_flag_tdm_error" }, /* Enable tdm error , */ \ + { 0x4870, \ + "int_enable_flag_lost_clk" }, /* Enable lost clk , */ \ + { 0x4c00, \ + "int_polarity_flag_por" }, /* Polarity por , */ \ + { 0x4c10, \ + "int_polarity_flag_bst_ocpok" }, /* Polarity DCDC OCP , */ \ + { 0x4c20, \ + "int_polarity_flag_otpok" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "int_polarity_flag_ocp_alarm" }, /* Polarity ocp alarm , */ \ + { 0x4c40, \ + "int_polarity_flag_uvpok" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "int_polarity_flag_man_alarm_state" }, /* Polarity nanager Alarm state , */ \ + { 0x4c60, \ + "int_polarity_flag_tdm_error" }, /* Polarity tdm error , */ \ + { 0x4c70, \ + "int_polarity_flag_lost_clk" }, /* Polarity lost clk , */ \ + { 0x5001, \ + "vbat_prot_attack_time" }, /* Battery Safeguard attack time , */ \ + { 0x5023, \ + "vbat_prot_thlevel" }, /* Battery Safeguard threshold voltage level , */ \ + { 0x5061, \ + "vbat_prot_max_reduct" }, /* Battery Safeguard maximum reduction , */ \ + { 0x5080, \ + "vbat_flt_limit" }, /* vbat filter limit , */ \ + { 0x50d0, \ + "rst_min_vbat" }, /* Reset clipper - Auto clear , */ \ + { 0x50e0, \ + "sel_vbat" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "bypass_clipper" }, /* Bypass battery safeguard , */ \ + { 0x5100, \ + "batsense_steepness" }, /* Vbat prot steepness , */ \ + { 0x5150, \ + "bypass_hp" }, /* Bypass HPF , */ \ + { 0x5170, \ + "enbl_dpsa" }, /* Enable DPSA , */ \ + { 0x5222, \ + "ctrl_cc" }, /* Clip control setting , */ \ + { 0x5257, \ + "gain" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "ctrl_slopectrl" }, /* Enables slope control , */ \ + { 0x52e0, \ + "ctrl_slope" }, /* Slope speed setting (bin. coded) , */ \ + { 0x5301, \ + "dpsa_level" }, /* DPSA threshold levels , */ \ + { 0x5321, \ + "dpsa_release" }, /* DPSA Release time , */ \ + { 0x5340, \ + "clipfast" }, /* Clock selection for HW clipper for Battery Safeguard, */ \ + { 0x5350, \ + "bypass_lp" }, /* Bypass the low power filter inside temperature sensor, */ \ + { 0x5400, \ + "first_order_mode" }, /* Overrule to 1st order mode of control stage when clipping, */ \ + { 0x5410, \ + "bypass_ctrlloop" }, /* Switch amplifier into open loop configuration , */ \ + { 0x5430, \ + "icomp_engage" }, /* Engage of icomp , */ \ + { 0x5440, \ + "ctrl_kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x5450, \ + "icomp_engage_overrule" }, /* To overrule the functional icomp_engage signal during validation, */ \ + { 0x5503, \ + "ctrl_dem" }, /* Enable DEM icomp and DEM one bit dac , */ \ + { 0x5543, \ + "ctrl_dem_mismatch" }, /* Enable DEM icomp mismatch for testing , */ \ + { 0x5582, \ + "dpsa_drive" }, /* Drive setting (bin. coded) , */ \ + { 0x5690, \ + "sel_pwm_delay_src" }, /* Control for selection for PWM delay line source , */ \ + { 0x56a1, \ + "enbl_odd_up_even_down" }, /* Control for PWM reference sawtooth generartion , */ \ + { 0x570a, \ + "enbl_amp" }, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */ \ + { 0x57b0, \ + "enbl_engage" }, /* Enables/engage power stage and control loop , */ \ + { 0x57c0, \ + "enbl_engage_pst" }, /* Enables/engage power stage and control loop , */ \ + { 0x5810, \ + "hard_mute" }, /* Hard mute - PWM , */ \ + { 0x5820, \ + "pwm_shape" }, /* PWM shape , */ \ + { 0x5844, \ + "pwm_delay" }, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */ \ + { 0x5890, \ + "reclock_pwm" }, /* Reclock the pwm signal inside analog , */ \ + { 0x58a0, \ + "reclock_voltsense" }, /* Reclock the voltage sense pwm signal , */ \ + { 0x58c0, \ + "enbl_pwm_phase_shift" }, /* Control for pwm phase shift , */ \ + { 0x6123, \ + "ctrl_attl" }, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */ \ + { 0x6163, \ + "ctrl_attr" }, /* Total gain depending on INPLEV setting (channel 0), */ \ + { 0x6265, \ + "zero_lvl" }, /* low noise gain switch zero trigger level , */ \ + { 0x62c1, \ + "ctrl_fb_resistor" }, /* Select amplifier feedback resistor connection , */ \ + { 0x62e1, \ + "lownoisegain_mode" }, /* ctrl select mode , */ \ + { 0x6305, \ + "threshold_lvl" }, /* low noise gain switch trigger level , */ \ + { 0x6365, \ + "hold_time" }, /* ctrl hold time before low audio is reckoned to be low audio, */ \ + { 0x6405, \ + "lpm1_cal_offset" }, /* low power mode1 detector ctrl cal_offset from gain module , */ \ + { 0x6465, \ + "lpm1_zero_lvl" }, /* low power mode1 zero crossing detection level , */ \ + { 0x64e1, \ + "lpm1_mode" }, /* low power mode control , */ \ + { 0x6505, \ + "lpm1_threshold_lvl" }, /* low power mode1 amplitude trigger level , */ \ + { 0x6565, \ + "lpm1_hold_time" }, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */ \ + { 0x65c0, \ + "disable_low_power_mode" }, /* low power mode1 detector control , */ \ + { 0x6600, \ + "dcdc_pfm20khz_limit" }, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */ \ + { 0x6611, \ + "dcdc_ctrl_maxzercnt" }, /* DCDC. Number of zero current flags to count before going to pfm mode, */ \ + { 0x6656, \ + "dcdc_vbat_delta_detect" }, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */ \ + { 0x66c0, \ + "dcdc_ignore_vbat" }, /* Ignore an increase on Vbat , */ \ + { 0x6700, \ + "enbl_minion" }, /* Enables minion (small) power stage , */ \ + { 0x6713, \ + "vth_vddpvbat" }, /* select vddp-vbat thres signal , */ \ + { 0x6750, \ + "lpen_vddpvbat" }, /* select vddp-vbat filtred vs unfiltered compare , */ \ + { 0x6761, \ + "ctrl_rfb" }, /* Feedback resistor selection - I2C direct mode , */ \ + { 0x6802, \ + "tdm_source_mapping" }, /* tdm source mapping , */ \ + { 0x6831, \ + "tdm_sourcea_frame_sel" }, /* Sensed value A , */ \ + { 0x6851, \ + "tdm_sourceb_frame_sel" }, /* Sensed value B , */ \ + { 0x6871, \ + "tdm_source0_clip_sel" }, /* clip information (analog /digital) for source0 , */ \ + { 0x6891, \ + "tdm_source1_clip_sel" }, /* clip information (analog /digital) for source1 , */ \ + { 0x6a02, \ + "rst_min_vbat_delay" }, /* rst_min_vbat delay (nb fs) , */ \ + { 0x6b00, \ + "disable_auto_engage" }, /* disable auto engange , */ \ + { 0x6b10, \ + "disable_engage" }, /* disable engange , */ \ + { 0x6c02, \ + "ns_hp2ln_criterion" }, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */ \ + { 0x6c32, \ + "ns_ln2hp_criterion" }, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */ \ + { 0x6c69, \ + "spare_out" }, /* spare_out , */ \ + { 0x6d0f, \ + "spare_in" }, /* spare_in , */ \ + { 0x6e10, \ + "flag_lp_detect_mode1" }, /* low power mode 1 detection , */ \ + { 0x6e20, \ + "flag_low_amplitude" }, /* low amplitude detection , */ \ + { 0x6e30, \ + "flag_vddp_gt_vbat" }, /* vddp greater than vbat , */ \ + { 0x6f02, \ + "cursense_comp_delay" }, /* delay to allign compensation signal with current sense signal, */ \ + { 0x6f40, \ + "cursense_comp_sign" }, /* polarity of compensation for current sense , */ \ + { 0x6f50, \ + "enbl_cursense_comp" }, /* enable current sense compensation , */ \ + { 0x6f72, \ + "pwms_clip_lvl" }, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */ \ + { 0x7033, \ + "boost_cur" }, /* Max coil current , */ \ + { 0x7071, \ + "bst_slpcmplvl" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7090, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "boost_speed" }, /* Soft ramp up/down , */ \ + { 0x70e0, \ + "dcdcoff_mode" }, /* DCDC on/off , */ \ + { 0x70f0, \ + "dcdc_pwmonly" }, /* DCDC PWM only mode , */ \ + { 0x7104, \ + "bst_drive" }, /* Binary coded drive setting for boost converter power stage, */ \ + { 0x7151, \ + "bst_scalecur" }, /* For testing direct control scale current , */ \ + { 0x7174, \ + "bst_slopecur" }, /* For testing direct control slope current , */ \ + { 0x71c1, \ + "bst_slope" }, /* Boost slope speed , */ \ + { 0x71e0, \ + "bst_bypass_bstcur" }, /* Bypass control for boost current settings , */ \ + { 0x71f0, \ + "bst_bypass_bstfoldback" }, /* Bypass control for boost foldback , */ \ + { 0x7200, \ + "enbl_bst_engage" }, /* Enable power stage dcdc controller , */ \ + { 0x7210, \ + "enbl_bst_hizcom" }, /* Enable hiz comparator , */ \ + { 0x7220, \ + "enbl_bst_peak2avg" }, /* Enable boost peak2avg functionality , */ \ + { 0x7230, \ + "enbl_bst_peakcur" }, /* Enable peak current , */ \ + { 0x7240, \ + "enbl_bst_power" }, /* Enable line of the powerstage , */ \ + { 0x7250, \ + "enbl_bst_slopecur" }, /* Enable bit of max-current dac , */ \ + { 0x7260, \ + "enbl_bst_voutcomp" }, /* Enable vout comparators , */ \ + { 0x7270, \ + "enbl_bst_voutcomp86" }, /* Enable vout-86 comparators , */ \ + { 0x7280, \ + "enbl_bst_voutcomp93" }, /* Enable vout-93 comparators , */ \ + { 0x7290, \ + "enbl_bst_windac" }, /* Enable window dac , */ \ + { 0x72a5, \ + "bst_windac" }, /* for testing direct control windac , */ \ + { 0x7300, \ + "boost_alg" }, /* Control for boost adaptive loop gain , */ \ + { 0x7311, \ + "boost_loopgain" }, /* DCDC boost loopgain setting , */ \ + { 0x7331, \ + "bst_freq" }, /* DCDC boost frequency control , */ \ + { 0x7360, \ + "bst_use_new_zercur_detect" }, /* Enable new zero current detection for boost control, */ \ + { 0x7430, \ + "boost_track" }, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */ \ + { 0x7444, \ + "boost_trip_lvl_1st" }, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7494, \ + "boost_hold_time" }, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */ \ + { 0x74e0, \ + "sel_dcdc_envelope_8fs" }, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */ \ + { 0x74f0, \ + "ignore_flag_voutcomp86" }, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */ \ + { 0x7534, \ + "boost_trip_lvl_2nd" }, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7584, \ + "boost_trip_lvl_track" }, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0x75f0, \ + "enbl_trip_hyst" }, /* Enable hysteresis on booster trip levels , */ \ + { 0x7635, \ + "frst_boost_voltage" }, /* First boost voltage level , */ \ + { 0x7695, \ + "scnd_boost_voltage" }, /* Second boost voltage level , */ \ + { 0x8001, \ + "sel_clk_cs" }, /* Current sense clock duty cycle control , */ \ + { 0x8021, \ + "micadc_speed" }, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */ \ + { 0x8050, \ + "cs_gain_control" }, /* Current sense gain control , */ \ + { 0x8060, \ + "cs_bypass_gc" }, /* Bypasses the CS gain correction , */ \ + { 0x8087, \ + "cs_gain" }, /* Current sense gain , */ \ + { 0x8210, \ + "invertpwm" }, /* Current sense common mode feedback pwm invert control, */ \ + { 0x8305, \ + "cs_ktemp" }, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */ \ + { 0x8364, \ + "cs_ktemp2" }, /* Second order temperature compensation coefficient , */ \ + { 0x8400, \ + "cs_adc_bsoinv" }, /* Bitstream inversion for current sense ADC , */ \ + { 0x8421, \ + "cs_adc_hifreq" }, /* Frequency mode current sense ADC , */ \ + { 0x8440, \ + "cs_adc_nortz" }, /* Return to zero for current sense ADC , */ \ + { 0x8453, \ + "cs_adc_offset" }, /* Micadc ADC offset setting , */ \ + { 0x8490, \ + "cs_adc_slowdel" }, /* Select delay for current sense ADC (internal decision circuitry), */ \ + { 0x84a4, \ + "cs_adc_gain" }, /* Gain setting for current sense ADC (two's complement), */ \ + { 0x8500, \ + "cs_resonator_enable" }, /* Enable for resonator to improve SRN , */ \ + { 0x8510, \ + "cs_classd_tran_skip" }, /* Skip current sense connection during a classD amplifier transition, */ \ + { 0x8530, \ + "cs_inn_short" }, /* Short current sense negative to common mode , */ \ + { 0x8540, \ + "cs_inp_short" }, /* Short current sense positive to common mode , */ \ + { 0x8550, \ + "cs_ldo_bypass" }, /* Bypass current sense LDO , */ \ + { 0x8560, \ + "cs_ldo_pulldown" }, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */ \ + { 0x8574, \ + "cs_ldo_voset" }, /* Current sense LDO voltage level setting (two's complement), */ \ + { 0x8700, \ + "enbl_cs_adc" }, /* Enable current sense ADC , */ \ + { 0x8710, \ + "enbl_cs_inn1" }, /* Enable connection of current sense negative1 , */ \ + { 0x8720, \ + "enbl_cs_inn2" }, /* Enable connection of current sense negative2 , */ \ + { 0x8730, \ + "enbl_cs_inp1" }, /* Enable connection of current sense positive1 , */ \ + { 0x8740, \ + "enbl_cs_inp2" }, /* Enable connection of current sense positive2 , */ \ + { 0x8750, \ + "enbl_cs_ldo" }, /* Enable current sense LDO , */ \ + { 0x8780, \ + "enbl_cs_vbatldo" }, /* Enable of current sense LDO , */ \ + { 0x8790, \ + "enbl_dc_filter" }, /* Control for enabling the DC blocking filter for voltage and current sense, */ \ + { 0x8801, \ + "volsense_pwm_sel" }, /* Voltage sense source selection control , */ \ + { 0x8850, \ + "vs_gain_control" }, /* Voltage sense gain control , */ \ + { 0x8860, \ + "vs_bypass_gc" }, /* Bypasses the VS gain correction , */ \ + { 0x8870, \ + "vs_igen_supply" }, /* Switch internal supply of current generator , */ \ + { 0x8887, \ + "vs_gain" }, /* voltage sense gain , */ \ + { 0x8c00, \ + "vs_adc_bsoinv" }, /* Bitstream inversion for voltage sense ADC , */ \ + { 0x8c40, \ + "vs_adc_nortz" }, /* Return to zero for voltage sense ADC , */ \ + { 0x8c90, \ + "vs_adc_slowdel" }, /* Select delay for voltage sense ADC (internal decision circuitry), */ \ + { 0x8d10, \ + "vs_classd_tran_skip" }, /* Skip voltage sense connection during a classD amplifier transition, */ \ + { 0x8d30, \ + "vs_inn_short" }, /* Short voltage sense negative to common mode , */ \ + { 0x8d40, \ + "vs_inp_short" }, /* Short voltage sense positive to common mode , */ \ + { 0x8d50, \ + "vs_ldo_bypass" }, /* Bypass voltage sense LDO , */ \ + { 0x8d60, \ + "vs_ldo_pulldown" }, /* Pull down voltage sense LDO, only valid if left_enbl_cs_ldo is high, */ \ + { 0x8d74, \ + "vs_ldo_voset" }, /* Voltage sense LDO voltage level setting (two's complement), */ \ + { 0x8f00, \ + "enbl_vs_adc" }, /* Enable voltage sense ADC (Direct Control only only others done by manager), */ \ + { 0x8f10, \ + "enbl_vs_inn1" }, /* Enable connection of voltage sense negative1 , */ \ + { 0x8f20, \ + "enbl_vs_inn2" }, /* Enable connection of voltage sense negative2 , */ \ + { 0x8f30, \ + "enbl_vs_inp1" }, /* Enable connection of voltage sense positive1 , */ \ + { 0x8f40, \ + "enbl_vs_inp2" }, /* Enable connection of voltage sense positive2 , */ \ + { 0x8f50, \ + "enbl_vs_ldo" }, /* Enable voltage sense LDO (Direct Control only only others done by manager), */ \ + { 0x8f80, \ + "enbl_vs_vbatldo" }, /* Enable of voltage sense LDO (Direct Control only others done by manager), */ \ + { 0xa007, \ + "mtpkey1" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0xa107, \ + "mtpkey2" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "key01_locked" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "key02_locked" }, /* Indicates KEY2 is locked , */ \ + { 0xa302, \ + "mtp_man_address_in" }, /* MTP address from I2C register for read/writing mtp in manual single word mode, */ \ + { 0xa330, \ + "man_copy_mtp_to_iic" }, /* Start copying single word from mtp to I2C mtp register, */ \ + { 0xa340, \ + "man_copy_iic_to_mtp" }, /* Start copying single word from I2C mtp register to mtp, */ \ + { 0xa350, \ + "auto_copy_mtp_to_iic" }, /* Start copying all the data from mtp to I2C mtp registers, */ \ + { 0xa360, \ + "auto_copy_iic_to_mtp" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa400, \ + "faim_set_clkws" }, /* Sets the faim controller clock wait state register, */ \ + { 0xa410, \ + "faim_sel_evenrows" }, /* All even rows of the faim are selected, active high, */ \ + { 0xa420, \ + "faim_sel_oddrows" }, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */ \ + { 0xa430, \ + "faim_program_only" }, /* Skip the erase access at wr_faim command (write-program-marginread), */ \ + { 0xa440, \ + "faim_erase_only" }, /* Skip the program access at wr_faim command (write-erase-marginread), */ \ + { 0xa50f, \ + "mtp_man_data_out_msb" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "mtp_man_data_out_lsb" }, /* LSB word of MTP manual read data , */ \ + { 0xa70f, \ + "mtp_man_data_in_msb" }, /* MSB word of write data for MTP manual write , */ \ + { 0xa80f, \ + "mtp_man_data_in_lsb" }, /* LSB word of write data for MTP manual write , */ \ + { 0xb010, \ + "bypass_ocpcounter" }, /* Bypass OCP Counter , */ \ + { 0xb020, \ + "bypass_glitchfilter" }, /* Bypass glitch filter , */ \ + { 0xb030, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0xb040, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0xb050, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0xb060, \ + "bypass_lost_clk" }, /* Bypass lost clock detector , */ \ + { 0xb070, \ + "ctrl_vpalarm" }, /* vpalarm (uvp ovp handling) , */ \ + { 0xb087, \ + "ocp_threshold" }, /* OCP threshold level , */ \ + { 0xb108, \ + "ext_temp" }, /* External temperature (C) , */ \ + { 0xb190, \ + "ext_temp_sel" }, /* Select temp Speaker calibration , */ \ + { 0xc000, \ + "use_direct_ctrls" }, /* Direct control to overrule several functions for testing, */ \ + { 0xc010, \ + "rst_datapath" }, /* Direct control for datapath reset , */ \ + { 0xc020, \ + "rst_cgu" }, /* Direct control for cgu reset , */ \ + { 0xc038, \ + "enbl_ref" }, /* Switch on the analog references, each part of the references can be switched on/off individually, */ \ + { 0xc0c0, \ + "use_direct_vs_ctrls" }, /* voltage sense Direct control to overrule several functions for testing, */ \ + { 0xc0d0, \ + "enbl_ringo" }, /* Enable the ring oscillator for test purpose , */ \ + { 0xc0e0, \ + "use_direct_clk_ctrl" }, /* Direct clock control to overrule several functions for testing, */ \ + { 0xc0f0, \ + "use_direct_pll_ctrl" }, /* Direct PLL control to overrule several functions for testing, */ \ + { 0xc100, \ + "enbl_tsense" }, /* Temperature sensor enable control - I2C direct mode, */ \ + { 0xc110, \ + "tsense_hibias" }, /* Bit to set the biasing in temp sensor to high , */ \ + { 0xc120, \ + "enbl_flag_vbg" }, /* Enable flagging of bandgap out of control , */ \ + { 0xc20f, \ + "abist_offset" }, /* Offset control for ABIST testing (two's complement), */ \ + { 0xc300, \ + "bypasslatch" }, /* Bypass latch , */ \ + { 0xc311, \ + "sourcea" }, /* Set OUTA to , */ \ + { 0xc331, \ + "sourceb" }, /* Set OUTB to , */ \ + { 0xc350, \ + "inverta" }, /* Invert pwma test signal , */ \ + { 0xc360, \ + "invertb" }, /* Invert pwmb test signal , */ \ + { 0xc374, \ + "pulselength" }, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */ \ + { 0xc3c0, \ + "tdm_enable_loopback" }, /* TDM loopback test , */ \ + { 0xc400, \ + "bst_bypasslatch" }, /* Bypass latch in boost converter , */ \ + { 0xc411, \ + "bst_source" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0xc430, \ + "bst_invertb" }, /* Invert pwmbst test signal , */ \ + { 0xc444, \ + "bst_pulselength" }, /* Pulse length setting test input for boost converter , */ \ + { 0xc490, \ + "test_bst_ctrlsthv" }, /* Test mode for boost control stage , */ \ + { 0xc4a0, \ + "test_bst_iddq" }, /* IDDQ testing in power stage of boost converter , */ \ + { 0xc4b0, \ + "test_bst_rdson" }, /* RDSON testing - boost power stage , */ \ + { 0xc4c0, \ + "test_bst_cvi" }, /* CVI testing - boost power stage , */ \ + { 0xc4d0, \ + "test_bst_ocp" }, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */ \ + { 0xc4e0, \ + "test_bst_sense" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0xc500, \ + "test_cvi" }, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */ \ + { 0xc510, \ + "test_discrete" }, /* Test function noise measurement , */ \ + { 0xc520, \ + "test_iddq" }, /* Set the power stages in iddq mode for gate stress., */ \ + { 0xc540, \ + "test_rdson" }, /* Analog BIST, switch to enable Rdson measurement , */ \ + { 0xc550, \ + "test_sdelta" }, /* Analog BIST, noise test , */ \ + { 0xc570, \ + "test_enbl_cs" }, /* Enable for digimux mode of current sense , */ \ + { 0xc580, \ + "test_enbl_vs" }, /* Enable for digimux mode of voltage sense , */ \ + { 0xc600, \ + "enbl_pwm_dcc" }, /* Enables direct control of pwm duty cycle for DCDC power stage, */ \ + { 0xc613, \ + "pwm_dcc_cnt" }, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0xc650, \ + "enbl_ldo_stress" }, /* Enable stress of internal supply voltages powerstages, */ \ + { 0xc707, \ + "digimuxa_sel" }, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */ \ + { 0xc787, \ + "digimuxb_sel" }, /* DigimuxB input selection control routed to INT (see Digimux list for details), */ \ + { 0xc807, \ + "digimuxc_sel" }, /* DigimuxC input selection control routed to PDMDAT (see Digimux list for details), */ \ + { 0xc981, \ + "int_ehs" }, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc9c0, \ + "hs_mode" }, /* I2C high speed mode control , */ \ + { 0xca00, \ + "enbl_anamux1" }, /* Enable anamux1 , */ \ + { 0xca10, \ + "enbl_anamux2" }, /* Enable anamux2 , */ \ + { 0xca20, \ + "enbl_anamux3" }, /* Enable anamux3 , */ \ + { 0xca30, \ + "enbl_anamux4" }, /* Enable anamux4 , */ \ + { 0xca74, \ + "anamux1" }, /* Anamux selection control - anamux on TEST1 , */ \ + { 0xcb04, \ + "anamux2" }, /* Anamux selection control - anamux on TEST2 , */ \ + { 0xcb53, \ + "anamux3" }, /* Anamux selection control - anamux on TEST3 , */ \ + { 0xcba3, \ + "anamux4" }, /* Anamux selection control - anamux on TEST4 , */ \ + { 0xcd05, \ + "pll_seli" }, /* PLL SELI - I2C direct PLL control mode only , */ \ + { 0xcd64, \ + "pll_selp" }, /* PLL SELP - I2C direct PLL control mode only , */ \ + { 0xcdb3, \ + "pll_selr" }, /* PLL SELR - I2C direct PLL control mode only , */ \ + { 0xcdf0, \ + "pll_frm" }, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */ \ + { 0xce09, \ + "pll_ndec" }, /* PLL NDEC - I2C direct PLL control mode only , */ \ + { 0xcea0, \ + "pll_mdec_msb" }, /* MSB of pll_mdec - I2C direct PLL control mode only, */ \ + { 0xceb0, \ + "enbl_pll" }, /* Enables PLL in I2C direct PLL control mode only , */ \ + { 0xcec0, \ + "enbl_osc" }, /* Enables OSC1M in I2C direct control mode only , */ \ + { 0xced0, \ + "pll_bypass" }, /* PLL bypass control in I2C direct PLL control mode only, */ \ + { 0xcee0, \ + "pll_directi" }, /* PLL directi control in I2C direct PLL control mode only, */ \ + { 0xcef0, \ + "pll_directo" }, /* PLL directo control in I2C direct PLL control mode only, */ \ + { 0xcf0f, \ + "pll_mdec_lsb" }, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */ \ + { 0xd006, \ + "pll_pdec" }, /* PLL PDEC - I2C direct PLL control mode only , */ \ + { 0xd10f, \ + "tsig_freq_lsb" }, /* Internal sinus test generator frequency control , */ \ + { 0xd202, \ + "tsig_freq_msb" }, /* Select internal sinus test generator, frequency control msb bits, */ \ + { 0xd230, \ + "inject_tsig" }, /* Control bit to switch to internal sinus test generator, */ \ + { 0xd283, \ + "tsig_gain" }, /* Test signal gain , */ \ + { 0xd300, \ + "adc10_reset" }, /* Reset for ADC10 - I2C direct control mode , */ \ + { 0xd311, \ + "adc10_test" }, /* Test mode selection signal for ADC10 - I2C direct control mode, */ \ + { 0xd332, \ + "adc10_sel" }, /* Select the input to convert for ADC10 - I2C direct control mode, */ \ + { 0xd364, \ + "adc10_prog_sample" }, /* ADC10 program sample setting - I2C direct control mode, */ \ + { 0xd3b0, \ + "adc10_enbl" }, /* Enable ADC10 - I2C direct control mode , */ \ + { 0xd3c0, \ + "bypass_lp_vbat" }, /* Bypass control for Low pass filter in batt sensor , */ \ + { 0xd409, \ + "data_adc10_tempbat" }, /* ADC 10 data output data for testing , */ \ + { 0xd507, \ + "ctrl_digtoana_hidden" }, /* Spare digital to analog control bits - Hidden , */ \ + { 0xd580, \ + "enbl_clk_out_of_range" }, /* Clock out of range , */ \ + { 0xd621, \ + "clkdiv_audio_sel" }, /* Audio clock divider selection in direct clock control mode, */ \ + { 0xd641, \ + "clkdiv_muxa_sel" }, /* DCDC MUXA clock divider selection in direct clock control mode, */ \ + { 0xd661, \ + "clkdiv_muxb_sel" }, /* DCDC MUXB clock divider selection in direct clock control mode, */ \ + { 0xd721, \ + "datao_ehs" }, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xd740, \ + "bck_ehs" }, /* High-speed and standard/fast mode selection for BCK IO cell (see IIC3V3 IO cell datasheet), */ \ + { 0xd750, \ + "datai_ehs" }, /* High-speed and standard/fast mode selection for DATAI IO cell (see IIC3V3 IO cell datasheet), */ \ + { 0xd800, \ + "source_in_testmode" }, /* tdm source in test mode (return only current and voltage sense), */ \ + { 0xd810, \ + "gainatt_feedback" }, /* gainatt feedback to tdm , */ \ + { 0xd822, \ + "test_parametric_io" }, /* test io parametric , */ \ + { 0xd850, \ + "ctrl_bst_clk_lp1" }, /* boost clock control in low power mode1 , */ \ + { 0xd861, \ + "test_spare_out1" }, /* test spare out 1 , */ \ + { 0xd880, \ + "bst_dcmbst" }, /* dcm boost , */ \ + { 0xd8c3, \ + "test_spare_out2" }, /* test spare out 1 , */ \ + { 0xee0f, \ + "sw_profile" }, /* Software profile data , */ \ + { 0xef0f, \ + "sw_vstep" }, /* Software vstep information , */ \ + { 0xf000, \ + "calibration_onetime" }, /* Calibration schedule , */ \ + { 0xf010, \ + "calibr_ron_done" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "calibr_dcdc_api_calibrate" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "calibr_dcdc_delta_sign" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "calibr_dcdc_delta" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "calibr_speaker_info" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf105, \ + "calibr_vout_offset" }, /* DCDC offset calibration 2's complement (key1 protected), */ \ + { 0xf169, \ + "spare_mpt1_15_6" }, /* SPARE , */ \ + { 0xf203, \ + "calibr_gain" }, /* HW gain module (2's complement) , */ \ + { 0xf245, \ + "calibr_offset" }, /* Offset for amplifier, HW gain module (2's complement), */ \ + { 0xf2a5, \ + "spare_mtp2_15_10" }, /* SPARE , */ \ + { 0xf307, \ + "calibr_gain_vs" }, /* Voltage sense gain , */ \ + { 0xf387, \ + "calibr_gain_cs" }, /* Current sense gain (signed two's complement format), */ \ + { 0xf407, \ + "spare_mtp4_15_0" }, /* SPARE , */ \ + { 0xf487, \ + "vs_trim" }, /* VS Trimming , */ \ + { 0xf50f, \ + "calibr_R25C_R" }, /* Ron resistance of speaker coil , */ \ + { 0xf60f, \ + "spare_mpt6_6_0" }, /* SPARE , */ \ + { 0xf706, \ + "ctrl_offset_a" }, /* Offset of level shifter A , */ \ + { 0xf770, \ + "spare_mtp7_07" }, /* SPARE , */ \ + { 0xf786, \ + "ctrl_offset_b" }, /* Offset of amplifier level shifter B , */ \ + { 0xf7f0, \ + "spare_mtp7_15" }, /* SPARE , */ \ + { 0xf806, \ + "htol_iic_addr" }, /* 7-bit I2C address to be used during HTOL testing , */ \ + { 0xf870, \ + "htol_iic_addr_en" }, /* HTOL I2C address enable control , */ \ + { 0xf884, \ + "calibr_temp_offset" }, /* Temperature offset 2's compliment (key1 protected), */ \ + { 0xf8d2, \ + "calibr_temp_gain" }, /* Temperature gain 2's compliment (key1 protected) , */ \ + { 0xf900, \ + "mtp_lock_dcdcoff_mode" }, /* Disable function dcdcoff_mode , */ \ + { 0xf910, \ + "spare_mtp9_1" }, /* SPARE , */ \ + { 0xf920, \ + "mtp_lock_bypass_clipper" }, /* Disable function bypass_clipper , */ \ + { 0xf930, \ + "mtp_lock_max_dcdc_voltage" }, /* Force Boost in follower mode , */ \ + { 0xf943, \ + "calibr_vbg_trim" }, /* Bandgap trimming control , */ \ + { 0xf980, \ + "spare_mtp9_8" }, /* SPARE , */ \ + { 0xf990, \ + "mtp_enbl_pwm_delay_clock_gating" }, /* pwm delay clock auto gating , */ \ + { 0xf9a0, \ + "mtp_enbl_ocp_clock_gating" }, /* ocpclock auto gating , */ \ + { 0xf9b0, \ + "mtp_gate_cgu_clock_for_test" }, /* cgu test clock control , */ \ + { 0xf9c0, \ + "mtp_tdm_pad_sel" }, /* tdm pad selection , */ \ + { 0xf9d2, \ + "spare_mtp9_15_12" }, /* MTP-control FW - See Firmware I2C API document for details, */ \ + { 0xfa0f, \ + "mtpdataA" }, /* MTPdataA (key1 protected) , */ \ + { 0xfb0f, \ + "mtpdataB" }, /* MTPdataB (key1 protected) , */ \ + { 0xfc0f, \ + "mtpdataC" }, /* MTPdataC (key1 protected) , */ \ + { 0xfd0f, \ + "mtpdataD" }, /* MTPdataD (key1 protected) , */ \ + { 0xfe0f, \ + "mtpdataE" }, /* MTPdataE (key1 protected) , */ \ + { 0xff07, \ + "calibr_osc_delta_ndiv" }, /* Calibration data for OSC1M, signed number representation, */ \ + { 0xff87, \ + "spare_mtp7_15_08" }, /* SPARE , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +enum tfa9874_irq { + tfa9874_irq_stvdds = 0, + tfa9874_irq_stbstoc = 1, + tfa9874_irq_stotds = 2, + tfa9874_irq_stocpr = 3, + tfa9874_irq_stuvds = 4, + tfa9874_irq_stmanalarm = 5, + tfa9874_irq_sttdmer = 6, + tfa9874_irq_stnoclk = 7, + tfa9874_irq_max = 8, + tfa9874_irq_all = -1 /* all irqs */ +}; + +#define TFA9874_IRQ_NAMETABLE \ + static tfaIrqName_t Tfa9874IrqNames[] = { \ + { 0, "STVDDS" }, { 1, "STBSTOC" }, { 2, "STOTDS" }, \ + { 3, "STOCPR" }, { 4, "STUVDS" }, { 5, "STMANALARM" }, \ + { 6, "STTDMER" }, { 7, "STNOCLK" }, { 8, "8" }, \ + }; +#endif /* _TFA9874_TFAFIELDNAMES_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9887_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9887_tfafieldnames.h new file mode 100644 index 000000000000..1451bb4edabe --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9887_tfafieldnames.h @@ -0,0 +1,109 @@ +/** Filename: Tfa9887_TfaFieldnames.h + * This file was generated automatically on 04/14/15 at 10:23:40. + * Source file: TFA9897N1B_I2C_list_URT_source_v34_87Only.xls + */ +#define TFA9887_I2CVERSION 34 +#define TFA9895_I2CVERSION 34 +#define TFA9887_NAMETABLE \ + static tfaBfName_t Tfa9887DatasheetNames[] = { \ + { 0x402, \ + "I2SF" }, /* I2SFormat data 1 input: , */ \ + { 0x431, \ + "CHS12" }, /* ChannelSelection data1 input (In CoolFlux) , */ \ + { 0x450, \ + "CHS3" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \ + { 0x461, \ + "CHSA" }, /* Input selection for amplifier , */ \ + { 0x4b0, \ + "I2SDOE" }, /* Enable data output , */ \ + { 0x4c3, \ + "I2SSR" }, /* sample rate setting , */ \ + { 0x500, \ + "BSSBY" }, /* , */ \ + { 0x511, \ + "BSSCR" }, /* 00 = 0.56 dB/Sample , */ \ + { 0x532, \ + "BSST" }, /* 000 = 2.92V , */ \ + { 0x5f0, \ + "I2SDOC" }, /* selection data out , */ \ + { 0xa02, \ + "DOLS" }, /* Output selection dataout left channel , */ \ + { 0xa32, \ + "DORS" }, /* Output selection dataout right channel , */ \ + { 0xa62, \ + "SPKL" }, /* Selection speaker induction , */ \ + { 0xa91, \ + "SPKR" }, /* Selection speaker impedance , */ \ + { 0xab3, \ + "DCFG" }, /* DCDC speaker current compensation gain , */ \ + { 0x4134, \ + "PWMDEL" }, /* PWM DelayBits to set the delay , */ \ + { 0x4180, \ + "PWMSH" }, /* PWM Shape , */ \ + { 0x4190, \ + "PWMRE" }, /* PWM Bitlength in noise shaper , */ \ + { 0x48e1, \ + "TCC" }, /* sample & hold track time: , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9887_BITNAMETABLE \ + static tfaBfName_t Tfa9887BitNames[] = { \ + { 0x402, \ + "i2s_seti" }, /* I2SFormat data 1 input: , */ \ + { 0x431, \ + "chan_sel1" }, /* ChannelSelection data1 input (In CoolFlux) , */ \ + { 0x450, \ + "lr_sw_i2si2" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \ + { 0x461, \ + "input_sel" }, /* Input selection for amplifier , */ \ + { 0x4b0, \ + "enbl_datao" }, /* Enable data output , */ \ + { 0x4c3, \ + "i2s_fs" }, /* sample rate setting , */ \ + { 0x500, \ + "bypass_clipper" }, /* , */ \ + { 0x511, \ + "vbat_prot_attacktime[1:0]" }, /* 00 = 0.56 dB/Sample , */ \ + { 0x532, \ + "vbat_prot_thlevel[2:0]" }, /* 000 = 2.92V , */ \ + { 0x5d0, \ + "reset_min_vbat" }, /* to reset the clipper via I2C in case the CF is bypassed, */ \ + { 0x5f0, \ + "datao_sel" }, /* selection data out , */ \ + { 0xa02, \ + "sel_i2so_l" }, /* Output selection dataout left channel , */ \ + { 0xa32, \ + "sel_i2so_r" }, /* Output selection dataout right channel , */ \ + { 0xa62, \ + "ctrl_spkr_coil" }, /* Selection speaker induction , */ \ + { 0xa91, \ + "ctrl_spr_res" }, /* Selection speaker impedance , */ \ + { 0xab3, \ + "ctrl_dcdc_spkr_i_comp_gain" }, /* DCDC speaker current compensation gain , */ \ + { 0xaf0, \ + "ctrl_dcdc_spkr_i_comp_sign" }, /* DCDC speaker current compensation sign , */ \ + { 0x4100, \ + "bypass_hp" }, /* bypass_hp, to bypass the hp filter byhind the CoolFlux, */ \ + { 0x4110, \ + "hard_mute" }, /* hard mute setting in HW , */ \ + { 0x4120, \ + "soft_mute" }, /* Soft mute setting in HW , */ \ + { 0x4134, \ + "PWM_Delay[4:0]" }, /* PWM DelayBits to set the delay , */ \ + { 0x4180, \ + "PWM_Shape" }, /* PWM Shape , */ \ + { 0x4190, \ + "PWM_BitLength" }, /* PWM Bitlength in noise shaper , */ \ + { 0x4800, \ + "ctrl_negin" }, /* , */ \ + { 0x4810, \ + "ctrl_cs_sein" }, /* , */ \ + { 0x4820, \ + "ctrl_coincidencecs" }, /* HIGH => Prevent dcdc switching during clk_cs_clksh, */ \ + { 0x4876, \ + "delay_se_neg[6:0]" }, /* delayshiftse2 , */ \ + { 0x48e1, \ + "ctrl_cs_ttrack[1:0]" }, /* sample & hold track time: , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9890_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9890_tfafieldnames.h new file mode 100644 index 000000000000..baf247451dcd --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9890_tfafieldnames.h @@ -0,0 +1,140 @@ +/** Filename: Tfa9890_TfaFieldnames.h + * This file was generated automatically on 04/07/15 at 14:46:37. + * Source file: TFA9897N1B_I2C_list_URT_source_v34_90Only.xls + */ +#define TFA9890_I2CVERSION 34 +#define TFA9890_NAMETABLE \ + static tfaBfName_t Tfa9890DatasheetNames[] = { \ + { 0x402, \ + "I2SF" }, /* I2SFormat data 1 input: , */ \ + { 0x431, \ + "CHS12" }, /* ChannelSelection data1 input (In CoolFlux) , */ \ + { 0x450, \ + "CHS3" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \ + { 0x461, \ + "CHSA" }, /* Input selection for amplifier , */ \ + { 0x481, \ + "I2SDOC" }, /* selection data out , */ \ + { 0x4a0, \ + "DISP" }, /* idp protection , */ \ + { 0x4b0, \ + "I2SDOE" }, /* Enable data output , */ \ + { 0x4c3, \ + "I2SSR" }, /* sample rate setting , */ \ + { 0x732, \ + "DCMCC" }, /* Max boost coil current - step of 500 mA , */ \ + { 0x9c0, \ + "CCFD" }, /* Selection CoolFlux Clock , */ \ + { 0x9d0, \ + "ISEL" }, /* selection input 1 or 2 , */ \ + { 0xa02, \ + "DOLS" }, /* Output selection dataout left channel , */ \ + { 0xa32, \ + "DORS" }, /* Output selection dataout right channel , */ \ + { 0xa62, \ + "SPKL" }, /* Selection speaker induction , */ \ + { 0xa91, \ + "SPKR" }, /* Selection speaker impedance , */ \ + { 0xab3, \ + "DCFG" }, /* DCDC speaker current compensation gain , */ \ + { 0xf00, \ + "VDDD" }, /* mask flag_por for interupt generation , */ \ + { 0xf10, \ + "OTDD" }, /* mask flag_otpok for interupt generation , */ \ + { 0xf20, \ + "OVDD" }, /* mask flag_ovpok for interupt generation , */ \ + { 0xf30, \ + "UVDD" }, /* mask flag_uvpok for interupt generation , */ \ + { 0xf40, \ + "OCDD" }, /* mask flag_ocp_alarm for interupt generation , */ \ + { 0xf50, \ + "CLKD" }, /* mask flag_clocks_stable for interupt generation , */ \ + { 0xf60, \ + "DCCD" }, /* mask flag_pwrokbst for interupt generation , */ \ + { 0xf70, \ + "SPKD" }, /* mask flag_cf_speakererror for interupt generation , */ \ + { 0xf80, \ + "WDD" }, /* mask flag_watchdog_reset for interupt generation , */ \ + { 0xf90, \ + "LCLK" }, /* mask flag_lost_clk for interupt generation , */ \ + { 0xfe0, \ + "INT" }, /* enabling interrupt , */ \ + { 0xff0, \ + "INTP" }, /* Setting polarity interupt , */ \ + { 0x8f0f, \ + "VERSION" }, /* (key1 protected) , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9890_BITNAMETABLE \ + static tfaBfName_t Tfa9890BitNames[] = { \ + { 0x402, \ + "i2s_seti" }, /* I2SFormat data 1 input: , */ \ + { 0x431, \ + "chan_sel1" }, /* ChannelSelection data1 input (In CoolFlux) , */ \ + { 0x450, \ + "lr_sw_i2si2" }, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \ + { 0x461, \ + "input_sel" }, /* Input selection for amplifier , */ \ + { 0x481, \ + "datao_sel" }, /* selection data out , */ \ + { 0x4a0, \ + "disable_idp" }, /* idp protection , */ \ + { 0x4b0, \ + "enbl_datao" }, /* Enable data output , */ \ + { 0x4c3, \ + "i2s_fs" }, /* sample rate setting , */ \ + { 0x732, \ + "ctrl_bstcur" }, /* Max boost coil current - step of 500 mA , */ \ + { 0x9c0, \ + "sel_cf_clk" }, /* Selection CoolFlux Clock , */ \ + { 0x9d0, \ + "intf_sel" }, /* selection input 1 or 2 , */ \ + { 0xa02, \ + "sel_i2so_l" }, /* Output selection dataout left channel , */ \ + { 0xa32, \ + "sel_i2so_r" }, /* Output selection dataout right channel , */ \ + { 0xa62, \ + "ctrl_spkr_coil" }, /* Selection speaker induction , */ \ + { 0xa91, \ + "ctrl_spr_res" }, /* Selection speaker impedance , */ \ + { 0xab3, \ + "ctrl_dcdc_spkr_i_comp_gain" }, /* DCDC speaker current compensation gain , */ \ + { 0xaf0, \ + "ctrl_dcdc_spkr_i_comp_sign" }, /* DCDC speaker current compensation sign , */ \ + { 0xf00, \ + "flag_por_mask" }, /* mask flag_por for interupt generation , */ \ + { 0xf10, \ + "flag_otpok_mask" }, /* mask flag_otpok for interupt generation , */ \ + { 0xf20, \ + "flag_ovpok_mask" }, /* mask flag_ovpok for interupt generation , */ \ + { 0xf30, \ + "flag_uvpok_mask" }, /* mask flag_uvpok for interupt generation , */ \ + { 0xf40, \ + "flag_ocp_alarm_mask" }, /* mask flag_ocp_alarm for interupt generation , */ \ + { 0xf50, \ + "flag_clocks_stable_mask" }, /* mask flag_clocks_stable for interupt generation , */ \ + { 0xf60, \ + "flag_pwrokbst_mask" }, /* mask flag_pwrokbst for interupt generation , */ \ + { 0xf70, \ + "flag_cf_speakererror_mask" }, /* mask flag_cf_speakererror for interupt generation , */ \ + { 0xf80, \ + "flag_watchdog_reset_mask" }, /* mask flag_watchdog_reset for interupt generation , */ \ + { 0xf90, \ + "flag_lost_clk_mask" }, /* mask flag_lost_clk for interupt generation , */ \ + { 0xfe0, \ + "enable_interrupt" }, /* enabling interrupt , */ \ + { 0xff0, \ + "invert_int_polarity" }, /* Setting polarity interupt , */ \ + { 0x4700, \ + "switch_fb" }, /* switch_fb , */ \ + { 0x4713, \ + "se_hyst" }, /* se_hyst , */ \ + { 0x4754, \ + "se_level" }, /* se_level , */ \ + { 0x47a5, \ + "ktemp" }, /* temperature compensation trimming , */ \ + { 0x8f0f, \ + "production_data6" }, /* (key1 protected) , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_genregs.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_genregs.h new file mode 100644 index 000000000000..3b3ffb9b9bff --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_genregs.h @@ -0,0 +1,1099 @@ +/** Filename: Tfa98xx_genregs.h + * This file was generated automatically on 07/01/15 at 10:25:08. + * Source file: TFA9891_I2C_list_V11.xls + */ + +#ifndef TFA9891_GENREGS_H +#define TFA9891_GENREGS_H + +#define TFA98XX_STATUSREG 0x00 +#define TFA98XX_BATTERYVOLTAGE 0x01 +#define TFA9891_TEMPERATURE 0x02 +#define TFA98XX_REVISIONNUMBER 0x03 +#define TFA98XX_I2SREG 0x04 +#define TFA98XX_BAT_PROT 0x05 +#define TFA98XX_AUDIO_CTR 0x06 +#define TFA98XX_DCDCBOOST 0x07 +#define TFA98XX_SPKR_CALIBRATION 0x08 +#define TFA98XX_SYS_CTRL 0x09 +#define TFA98XX_I2S_SEL_REG 0x0a +#define TFA98XX_HIDDEN_MTP_KEY2 0x0b +#define TFA98XX_INTERRUPT_REG 0x0f +#define TFA98XX_PDM_CTRL 0x10 +#define TFA98XX_PDM_OUT_CTRL 0x11 +#define TFA98XX_PDM_DS4_R 0x12 +#define TFA98XX_PDM_DS4_L 0x13 +#define TFA98XX_CTRL_SAAM_PGA 0x22 +#define TFA98XX_MISC_CTRL 0x25 +#define TFA98XX_CURRENTSENSE1 0x46 +#define TFA98XX_CURRENTSENSE4 0x49 +#define TFA98XX_HIDDEN_MTP_CTRL_REG3 0x62 +#define TFA9891_CF_CONTROLS 0x70 +#define TFA9891_CF_MAD 0x71 +#define TFA9891_CF_MEM 0x72 +#define TFA9891_CF_STATUS 0x73 +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP 0x80 + +/* + * (0x00)-StatusReg + */ + +/* + * POR + */ +#define TFA98XX_STATUSREG_VDDS (0x1 << 0) +#define TFA98XX_STATUSREG_VDDS_POS 0 +#define TFA98XX_STATUSREG_VDDS_LEN 1 +#define TFA98XX_STATUSREG_VDDS_MAX 1 +#define TFA98XX_STATUSREG_VDDS_MSK 0x1 + +/* + * PLL_LOCK + */ +#define TFA98XX_STATUSREG_PLLS (0x1 << 1) +#define TFA98XX_STATUSREG_PLLS_POS 1 +#define TFA98XX_STATUSREG_PLLS_LEN 1 +#define TFA98XX_STATUSREG_PLLS_MAX 1 +#define TFA98XX_STATUSREG_PLLS_MSK 0x2 + +/* + * flag_otpok + */ +#define TFA98XX_STATUSREG_OTDS (0x1 << 2) +#define TFA98XX_STATUSREG_OTDS_POS 2 +#define TFA98XX_STATUSREG_OTDS_LEN 1 +#define TFA98XX_STATUSREG_OTDS_MAX 1 +#define TFA98XX_STATUSREG_OTDS_MSK 0x4 + +/* + * flag_ovpok + */ +#define TFA98XX_STATUSREG_OVDS (0x1 << 3) +#define TFA98XX_STATUSREG_OVDS_POS 3 +#define TFA98XX_STATUSREG_OVDS_LEN 1 +#define TFA98XX_STATUSREG_OVDS_MAX 1 +#define TFA98XX_STATUSREG_OVDS_MSK 0x8 + +/* + * flag_uvpok + */ +#define TFA98XX_STATUSREG_UVDS (0x1 << 4) +#define TFA98XX_STATUSREG_UVDS_POS 4 +#define TFA98XX_STATUSREG_UVDS_LEN 1 +#define TFA98XX_STATUSREG_UVDS_MAX 1 +#define TFA98XX_STATUSREG_UVDS_MSK 0x10 + +/* + * flag_OCP_alarm + */ +#define TFA98XX_STATUSREG_OCDS (0x1 << 5) +#define TFA98XX_STATUSREG_OCDS_POS 5 +#define TFA98XX_STATUSREG_OCDS_LEN 1 +#define TFA98XX_STATUSREG_OCDS_MAX 1 +#define TFA98XX_STATUSREG_OCDS_MSK 0x20 + +/* + * flag_clocks_stable + */ +#define TFA98XX_STATUSREG_CLKS (0x1 << 6) +#define TFA98XX_STATUSREG_CLKS_POS 6 +#define TFA98XX_STATUSREG_CLKS_LEN 1 +#define TFA98XX_STATUSREG_CLKS_MAX 1 +#define TFA98XX_STATUSREG_CLKS_MSK 0x40 + +/* + * CLIP + */ +#define TFA98XX_STATUSREG_CLIPS (0x1 << 7) +#define TFA98XX_STATUSREG_CLIPS_POS 7 +#define TFA98XX_STATUSREG_CLIPS_LEN 1 +#define TFA98XX_STATUSREG_CLIPS_MAX 1 +#define TFA98XX_STATUSREG_CLIPS_MSK 0x80 + +/* + * mtp_busy + */ +#define TFA98XX_STATUSREG_MTPB (0x1 << 8) +#define TFA98XX_STATUSREG_MTPB_POS 8 +#define TFA98XX_STATUSREG_MTPB_LEN 1 +#define TFA98XX_STATUSREG_MTPB_MAX 1 +#define TFA98XX_STATUSREG_MTPB_MSK 0x100 + +/* + * flag_pwrokbst + */ +#define TFA98XX_STATUSREG_DCCS (0x1 << 9) +#define TFA98XX_STATUSREG_DCCS_POS 9 +#define TFA98XX_STATUSREG_DCCS_LEN 1 +#define TFA98XX_STATUSREG_DCCS_MAX 1 +#define TFA98XX_STATUSREG_DCCS_MSK 0x200 + +/* + * flag_cf_speakererror + */ +#define TFA98XX_STATUSREG_SPKS (0x1 << 10) +#define TFA98XX_STATUSREG_SPKS_POS 10 +#define TFA98XX_STATUSREG_SPKS_LEN 1 +#define TFA98XX_STATUSREG_SPKS_MAX 1 +#define TFA98XX_STATUSREG_SPKS_MSK 0x400 + +/* + * flag_cold_started + */ +#define TFA98XX_STATUSREG_ACS (0x1 << 11) +#define TFA98XX_STATUSREG_ACS_POS 11 +#define TFA98XX_STATUSREG_ACS_LEN 1 +#define TFA98XX_STATUSREG_ACS_MAX 1 +#define TFA98XX_STATUSREG_ACS_MSK 0x800 + +/* + * flag_engage + */ +#define TFA98XX_STATUSREG_SWS (0x1 << 12) +#define TFA98XX_STATUSREG_SWS_POS 12 +#define TFA98XX_STATUSREG_SWS_LEN 1 +#define TFA98XX_STATUSREG_SWS_MAX 1 +#define TFA98XX_STATUSREG_SWS_MSK 0x1000 + +/* + * flag_watchdog_reset + */ +#define TFA98XX_STATUSREG_WDS (0x1 << 13) +#define TFA98XX_STATUSREG_WDS_POS 13 +#define TFA98XX_STATUSREG_WDS_LEN 1 +#define TFA98XX_STATUSREG_WDS_MAX 1 +#define TFA98XX_STATUSREG_WDS_MSK 0x2000 + +/* + * flag_enbl_amp + */ +#define TFA98XX_STATUSREG_AMPS (0x1 << 14) +#define TFA98XX_STATUSREG_AMPS_POS 14 +#define TFA98XX_STATUSREG_AMPS_LEN 1 +#define TFA98XX_STATUSREG_AMPS_MAX 1 +#define TFA98XX_STATUSREG_AMPS_MSK 0x4000 + +/* + * flag_enbl_ref + */ +#define TFA98XX_STATUSREG_AREFS (0x1 << 15) +#define TFA98XX_STATUSREG_AREFS_POS 15 +#define TFA98XX_STATUSREG_AREFS_LEN 1 +#define TFA98XX_STATUSREG_AREFS_MAX 1 +#define TFA98XX_STATUSREG_AREFS_MSK 0x8000 + +/* + * (0x01)-BatteryVoltage + */ + +/* + * bat_adc + */ +#define TFA98XX_BATTERYVOLTAGE_BATS (0x3ff << 0) +#define TFA98XX_BATTERYVOLTAGE_BATS_POS 0 +#define TFA98XX_BATTERYVOLTAGE_BATS_LEN 10 +#define TFA98XX_BATTERYVOLTAGE_BATS_MAX 1023 +#define TFA98XX_BATTERYVOLTAGE_BATS_MSK 0x3ff + +/* + * (0x02)-Temperature + */ + +/* + * temp_adc + */ +#define TFA9891_TEMPERATURE_TEMPS (0x1ff << 0) +#define TFA9891_TEMPERATURE_TEMPS_POS 0 +#define TFA9891_TEMPERATURE_TEMPS_LEN 9 +#define TFA9891_TEMPERATURE_TEMPS_MAX 511 +#define TFA9891_TEMPERATURE_TEMPS_MSK 0x1ff + +/* + * (0x03)-RevisionNumber + */ + +/* + * rev_reg + */ +#define TFA98XX_REVISIONNUMBER_REV (0xff << 0) +#define TFA98XX_REVISIONNUMBER_REV_POS 0 +#define TFA98XX_REVISIONNUMBER_REV_LEN 8 +#define TFA98XX_REVISIONNUMBER_REV_MAX 255 +#define TFA98XX_REVISIONNUMBER_REV_MSK 0xff + +/* + * (0x04)-I2SReg + */ + +/* + * i2s_seti + */ +#define TFA98XX_I2SREG_I2SF (0x7 << 0) +#define TFA98XX_I2SREG_I2SF_POS 0 +#define TFA98XX_I2SREG_I2SF_LEN 3 +#define TFA98XX_I2SREG_I2SF_MAX 7 +#define TFA98XX_I2SREG_I2SF_MSK 0x7 + +/* + * chan_sel1 + */ +#define TFA98XX_I2SREG_CHS12 (0x3 << 3) +#define TFA98XX_I2SREG_CHS12_POS 3 +#define TFA98XX_I2SREG_CHS12_LEN 2 +#define TFA98XX_I2SREG_CHS12_MAX 3 +#define TFA98XX_I2SREG_CHS12_MSK 0x18 + +/* + * lr_sw_i2si2 + */ +#define TFA98XX_I2SREG_CHS3 (0x1 << 5) +#define TFA98XX_I2SREG_CHS3_POS 5 +#define TFA98XX_I2SREG_CHS3_LEN 1 +#define TFA98XX_I2SREG_CHS3_MAX 1 +#define TFA98XX_I2SREG_CHS3_MSK 0x20 + +/* + * input_sel + */ +#define TFA98XX_I2SREG_CHSA (0x3 << 6) +#define TFA98XX_I2SREG_CHSA_POS 6 +#define TFA98XX_I2SREG_CHSA_LEN 2 +#define TFA98XX_I2SREG_CHSA_MAX 3 +#define TFA98XX_I2SREG_CHSA_MSK 0xc0 + +/* + * datao_sel + */ +#define TFA98XX_I2SREG_I2SDOC (0x3 << 8) +#define TFA98XX_I2SREG_I2SDOC_POS 8 +#define TFA98XX_I2SREG_I2SDOC_LEN 2 +#define TFA98XX_I2SREG_I2SDOC_MAX 3 +#define TFA98XX_I2SREG_I2SDOC_MSK 0x300 + +/* + * disable_idp + */ +#define TFA98XX_I2SREG_DISP (0x1 << 10) +#define TFA98XX_I2SREG_DISP_POS 10 +#define TFA98XX_I2SREG_DISP_LEN 1 +#define TFA98XX_I2SREG_DISP_MAX 1 +#define TFA98XX_I2SREG_DISP_MSK 0x400 + +/* + * enbl_datao + */ +#define TFA98XX_I2SREG_I2SDOE (0x1 << 11) +#define TFA98XX_I2SREG_I2SDOE_POS 11 +#define TFA98XX_I2SREG_I2SDOE_LEN 1 +#define TFA98XX_I2SREG_I2SDOE_MAX 1 +#define TFA98XX_I2SREG_I2SDOE_MSK 0x800 + +/* + * i2s_fs + */ +#define TFA98XX_I2SREG_I2SSR (0xf << 12) +#define TFA98XX_I2SREG_I2SSR_POS 12 +#define TFA98XX_I2SREG_I2SSR_LEN 4 +#define TFA98XX_I2SREG_I2SSR_MAX 15 +#define TFA98XX_I2SREG_I2SSR_MSK 0xf000 + +/* + * (0x05)-bat_prot + */ + +/* + * vbat_prot_attacktime + */ +#define TFA98XX_BAT_PROT_BSSCR (0x3 << 0) +#define TFA98XX_BAT_PROT_BSSCR_POS 0 +#define TFA98XX_BAT_PROT_BSSCR_LEN 2 +#define TFA98XX_BAT_PROT_BSSCR_MAX 3 +#define TFA98XX_BAT_PROT_BSSCR_MSK 0x3 + +/* + * vbat_prot_thlevel + */ +#define TFA98XX_BAT_PROT_BSST (0xf << 2) +#define TFA98XX_BAT_PROT_BSST_POS 2 +#define TFA98XX_BAT_PROT_BSST_LEN 4 +#define TFA98XX_BAT_PROT_BSST_MAX 15 +#define TFA98XX_BAT_PROT_BSST_MSK 0x3c + +/* + * vbat_prot_max_reduct + */ +#define TFA98XX_BAT_PROT_BSSRL (0x3 << 6) +#define TFA98XX_BAT_PROT_BSSRL_POS 6 +#define TFA98XX_BAT_PROT_BSSRL_LEN 2 +#define TFA98XX_BAT_PROT_BSSRL_MAX 3 +#define TFA98XX_BAT_PROT_BSSRL_MSK 0xc0 + +/* + * vbat_prot_release_t + */ +#define TFA98XX_BAT_PROT_BSSRR (0x7 << 8) +#define TFA98XX_BAT_PROT_BSSRR_POS 8 +#define TFA98XX_BAT_PROT_BSSRR_LEN 3 +#define TFA98XX_BAT_PROT_BSSRR_MAX 7 +#define TFA98XX_BAT_PROT_BSSRR_MSK 0x700 + +/* + * vbat_prot_hysterese + */ +#define TFA98XX_BAT_PROT_BSSHY (0x3 << 11) +#define TFA98XX_BAT_PROT_BSSHY_POS 11 +#define TFA98XX_BAT_PROT_BSSHY_LEN 2 +#define TFA98XX_BAT_PROT_BSSHY_MAX 3 +#define TFA98XX_BAT_PROT_BSSHY_MSK 0x1800 + +/* + * sel_vbat + */ +#define TFA98XX_BAT_PROT_BSSR (0x1 << 14) +#define TFA98XX_BAT_PROT_BSSR_POS 14 +#define TFA98XX_BAT_PROT_BSSR_LEN 1 +#define TFA98XX_BAT_PROT_BSSR_MAX 1 +#define TFA98XX_BAT_PROT_BSSR_MSK 0x4000 + +/* + * bypass_clipper + */ +#define TFA98XX_BAT_PROT_BSSBY (0x1 << 15) +#define TFA98XX_BAT_PROT_BSSBY_POS 15 +#define TFA98XX_BAT_PROT_BSSBY_LEN 1 +#define TFA98XX_BAT_PROT_BSSBY_MAX 1 +#define TFA98XX_BAT_PROT_BSSBY_MSK 0x8000 + +/* + * (0x06)-audio_ctr + */ + +/* + * dpsa + */ +#define TFA98XX_AUDIO_CTR_DPSA (0x1 << 0) +#define TFA98XX_AUDIO_CTR_DPSA_POS 0 +#define TFA98XX_AUDIO_CTR_DPSA_LEN 1 +#define TFA98XX_AUDIO_CTR_DPSA_MAX 1 +#define TFA98XX_AUDIO_CTR_DPSA_MSK 0x1 + +/* + * ctrl_slope + */ +#define TFA98XX_AUDIO_CTR_AMPSL (0xf << 1) +#define TFA98XX_AUDIO_CTR_AMPSL_POS 1 +#define TFA98XX_AUDIO_CTR_AMPSL_LEN 4 +#define TFA98XX_AUDIO_CTR_AMPSL_MAX 15 +#define TFA98XX_AUDIO_CTR_AMPSL_MSK 0x1e + +/* + * cf_mute + */ +#define TFA98XX_AUDIO_CTR_CFSM (0x1 << 5) +#define TFA98XX_AUDIO_CTR_CFSM_POS 5 +#define TFA98XX_AUDIO_CTR_CFSM_LEN 1 +#define TFA98XX_AUDIO_CTR_CFSM_MAX 1 +#define TFA98XX_AUDIO_CTR_CFSM_MSK 0x20 + +/* + * ctrl_batsensesteepness + */ +#define TFA98XX_AUDIO_CTR_BSSS (0x1 << 7) +#define TFA98XX_AUDIO_CTR_BSSS_POS 7 +#define TFA98XX_AUDIO_CTR_BSSS_LEN 1 +#define TFA98XX_AUDIO_CTR_BSSS_MAX 1 +#define TFA98XX_AUDIO_CTR_BSSS_MSK 0x80 + +/* + * vol + */ +#define TFA98XX_AUDIO_CTR_VOL (0xff << 8) +#define TFA98XX_AUDIO_CTR_VOL_POS 8 +#define TFA98XX_AUDIO_CTR_VOL_LEN 8 +#define TFA98XX_AUDIO_CTR_VOL_MAX 255 +#define TFA98XX_AUDIO_CTR_VOL_MSK 0xff00 + +/* + * (0x07)-DCDCboost + */ + +/* + * ctrl_bstvolt + */ +#define TFA98XX_DCDCBOOST_DCVO (0x7 << 0) +#define TFA98XX_DCDCBOOST_DCVO_POS 0 +#define TFA98XX_DCDCBOOST_DCVO_LEN 3 +#define TFA98XX_DCDCBOOST_DCVO_MAX 7 +#define TFA98XX_DCDCBOOST_DCVO_MSK 0x7 + +/* + * ctrl_bstcur + */ +#define TFA98XX_DCDCBOOST_DCMCC (0x7 << 3) +#define TFA98XX_DCDCBOOST_DCMCC_POS 3 +#define TFA98XX_DCDCBOOST_DCMCC_LEN 3 +#define TFA98XX_DCDCBOOST_DCMCC_MAX 7 +#define TFA98XX_DCDCBOOST_DCMCC_MSK 0x38 + +/* + * boost_intel + */ +#define TFA98XX_DCDCBOOST_DCIE (0x1 << 10) +#define TFA98XX_DCDCBOOST_DCIE_POS 10 +#define TFA98XX_DCDCBOOST_DCIE_LEN 1 +#define TFA98XX_DCDCBOOST_DCIE_MAX 1 +#define TFA98XX_DCDCBOOST_DCIE_MSK 0x400 + +/* + * boost_speed + */ +#define TFA98XX_DCDCBOOST_DCSR (0x1 << 11) +#define TFA98XX_DCDCBOOST_DCSR_POS 11 +#define TFA98XX_DCDCBOOST_DCSR_LEN 1 +#define TFA98XX_DCDCBOOST_DCSR_MAX 1 +#define TFA98XX_DCDCBOOST_DCSR_MSK 0x800 + +/* + * (0x08)-spkr_calibration + */ + +/* + * ext_temp_sel + */ +#define TFA98XX_SPKR_CALIBRATION_TROS (0x1 << 0) +#define TFA98XX_SPKR_CALIBRATION_TROS_POS 0 +#define TFA98XX_SPKR_CALIBRATION_TROS_LEN 1 +#define TFA98XX_SPKR_CALIBRATION_TROS_MAX 1 +#define TFA98XX_SPKR_CALIBRATION_TROS_MSK 0x1 + +/* + * ext_temp + */ +#define TFA98XX_SPKR_CALIBRATION_EXTTS (0x1ff << 1) +#define TFA98XX_SPKR_CALIBRATION_EXTTS_POS 1 +#define TFA98XX_SPKR_CALIBRATION_EXTTS_LEN 9 +#define TFA98XX_SPKR_CALIBRATION_EXTTS_MAX 511 +#define TFA98XX_SPKR_CALIBRATION_EXTTS_MSK 0x3fe + +/* + * (0x09)-sys_ctrl + */ + +/* + * PowerDown + */ +#define TFA98XX_SYS_CTRL_PWDN (0x1 << 0) +#define TFA98XX_SYS_CTRL_PWDN_POS 0 +#define TFA98XX_SYS_CTRL_PWDN_LEN 1 +#define TFA98XX_SYS_CTRL_PWDN_MAX 1 +#define TFA98XX_SYS_CTRL_PWDN_MSK 0x1 + +/* + * reset + */ +#define TFA98XX_SYS_CTRL_I2CR (0x1 << 1) +#define TFA98XX_SYS_CTRL_I2CR_POS 1 +#define TFA98XX_SYS_CTRL_I2CR_LEN 1 +#define TFA98XX_SYS_CTRL_I2CR_MAX 1 +#define TFA98XX_SYS_CTRL_I2CR_MSK 0x2 + +/* + * enbl_coolflux + */ +#define TFA98XX_SYS_CTRL_CFE (0x1 << 2) +#define TFA98XX_SYS_CTRL_CFE_POS 2 +#define TFA98XX_SYS_CTRL_CFE_LEN 1 +#define TFA98XX_SYS_CTRL_CFE_MAX 1 +#define TFA98XX_SYS_CTRL_CFE_MSK 0x4 + +/* + * enbl_amplifier + */ +#define TFA98XX_SYS_CTRL_AMPE (0x1 << 3) +#define TFA98XX_SYS_CTRL_AMPE_POS 3 +#define TFA98XX_SYS_CTRL_AMPE_LEN 1 +#define TFA98XX_SYS_CTRL_AMPE_MAX 1 +#define TFA98XX_SYS_CTRL_AMPE_MSK 0x8 + +/* + * enbl_boost + */ +#define TFA98XX_SYS_CTRL_DCA (0x1 << 4) +#define TFA98XX_SYS_CTRL_DCA_POS 4 +#define TFA98XX_SYS_CTRL_DCA_LEN 1 +#define TFA98XX_SYS_CTRL_DCA_MAX 1 +#define TFA98XX_SYS_CTRL_DCA_MSK 0x10 + +/* + * cf_configured + */ +#define TFA98XX_SYS_CTRL_SBSL (0x1 << 5) +#define TFA98XX_SYS_CTRL_SBSL_POS 5 +#define TFA98XX_SYS_CTRL_SBSL_LEN 1 +#define TFA98XX_SYS_CTRL_SBSL_MAX 1 +#define TFA98XX_SYS_CTRL_SBSL_MSK 0x20 + +/* + * sel_enbl_amplifier + */ +#define TFA98XX_SYS_CTRL_AMPC (0x1 << 6) +#define TFA98XX_SYS_CTRL_AMPC_POS 6 +#define TFA98XX_SYS_CTRL_AMPC_LEN 1 +#define TFA98XX_SYS_CTRL_AMPC_MAX 1 +#define TFA98XX_SYS_CTRL_AMPC_MSK 0x40 + +/* + * dcdcoff_mode + */ +#define TFA98XX_SYS_CTRL_DCDIS (0x1 << 7) +#define TFA98XX_SYS_CTRL_DCDIS_POS 7 +#define TFA98XX_SYS_CTRL_DCDIS_LEN 1 +#define TFA98XX_SYS_CTRL_DCDIS_MAX 1 +#define TFA98XX_SYS_CTRL_DCDIS_MSK 0x80 + +/* + * cttr_iddqtest + */ +#define TFA98XX_SYS_CTRL_PSDR (0x1 << 8) +#define TFA98XX_SYS_CTRL_PSDR_POS 8 +#define TFA98XX_SYS_CTRL_PSDR_LEN 1 +#define TFA98XX_SYS_CTRL_PSDR_MAX 1 +#define TFA98XX_SYS_CTRL_PSDR_MSK 0x100 + +/* + * ctrl_coil_value + */ +#define TFA98XX_SYS_CTRL_DCCV (0x3 << 9) +#define TFA98XX_SYS_CTRL_DCCV_POS 9 +#define TFA98XX_SYS_CTRL_DCCV_LEN 2 +#define TFA98XX_SYS_CTRL_DCCV_MAX 3 +#define TFA98XX_SYS_CTRL_DCCV_MSK 0x600 + +/* + * ctrl_sel_cf_clock + */ +#define TFA98XX_SYS_CTRL_CCFD (0x3 << 11) +#define TFA98XX_SYS_CTRL_CCFD_POS 11 +#define TFA98XX_SYS_CTRL_CCFD_LEN 2 +#define TFA98XX_SYS_CTRL_CCFD_MAX 3 +#define TFA98XX_SYS_CTRL_CCFD_MSK 0x1800 + +/* + * intf_sel + */ +#define TFA98XX_SYS_CTRL_ISEL (0x1 << 13) +#define TFA98XX_SYS_CTRL_ISEL_POS 13 +#define TFA98XX_SYS_CTRL_ISEL_LEN 1 +#define TFA98XX_SYS_CTRL_ISEL_MAX 1 +#define TFA98XX_SYS_CTRL_ISEL_MSK 0x2000 + +/* + * sel_ws_bck + */ +#define TFA98XX_SYS_CTRL_IPLL (0x1 << 14) +#define TFA98XX_SYS_CTRL_IPLL_POS 14 +#define TFA98XX_SYS_CTRL_IPLL_LEN 1 +#define TFA98XX_SYS_CTRL_IPLL_MAX 1 +#define TFA98XX_SYS_CTRL_IPLL_MSK 0x4000 + +/* + * (0x0a)-I2S_sel_reg + */ + +/* + * sel_i2so_l + */ +#define TFA98XX_I2S_SEL_REG_DOLS (0x7 << 0) +#define TFA98XX_I2S_SEL_REG_DOLS_POS 0 +#define TFA98XX_I2S_SEL_REG_DOLS_LEN 3 +#define TFA98XX_I2S_SEL_REG_DOLS_MAX 7 +#define TFA98XX_I2S_SEL_REG_DOLS_MSK 0x7 + +/* + * sel_i2so_r + */ +#define TFA98XX_I2S_SEL_REG_DORS (0x7 << 3) +#define TFA98XX_I2S_SEL_REG_DORS_POS 3 +#define TFA98XX_I2S_SEL_REG_DORS_LEN 3 +#define TFA98XX_I2S_SEL_REG_DORS_MAX 7 +#define TFA98XX_I2S_SEL_REG_DORS_MSK 0x38 + +/* + * ctrl_spkr_coil + */ +#define TFA98XX_I2S_SEL_REG_SPKL (0x7 << 6) +#define TFA98XX_I2S_SEL_REG_SPKL_POS 6 +#define TFA98XX_I2S_SEL_REG_SPKL_LEN 3 +#define TFA98XX_I2S_SEL_REG_SPKL_MAX 7 +#define TFA98XX_I2S_SEL_REG_SPKL_MSK 0x1c0 + +/* + * ctrl_spr_res + */ +#define TFA98XX_I2S_SEL_REG_SPKR (0x3 << 9) +#define TFA98XX_I2S_SEL_REG_SPKR_POS 9 +#define TFA98XX_I2S_SEL_REG_SPKR_LEN 2 +#define TFA98XX_I2S_SEL_REG_SPKR_MAX 3 +#define TFA98XX_I2S_SEL_REG_SPKR_MSK 0x600 + +/* + * ctrl_dcdc_spkr_i_comp_gain + */ +#define TFA98XX_I2S_SEL_REG_DCFG (0xf << 11) +#define TFA98XX_I2S_SEL_REG_DCFG_POS 11 +#define TFA98XX_I2S_SEL_REG_DCFG_LEN 4 +#define TFA98XX_I2S_SEL_REG_DCFG_MAX 15 +#define TFA98XX_I2S_SEL_REG_DCFG_MSK 0x7800 + +/* + * (0x0b)-Hidden_mtp_key2 + */ + +/* + * MTP_key2 + */ +#define TFA98XX_HIDDEN_MTP_KEY2_MTPK (0xff << 0) +#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_POS 0 +#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_LEN 8 +#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_MAX 255 +#define TFA98XX_HIDDEN_MTP_KEY2_MTPK_MSK 0xff + +/* + * (0x0f)-interrupt_reg + */ + +/* + * flag_por_mask + */ +#define TFA98XX_INTERRUPT_REG_VDDD (0x1 << 0) +#define TFA98XX_INTERRUPT_REG_VDDD_POS 0 +#define TFA98XX_INTERRUPT_REG_VDDD_LEN 1 +#define TFA98XX_INTERRUPT_REG_VDDD_MAX 1 +#define TFA98XX_INTERRUPT_REG_VDDD_MSK 0x1 + +/* + * flag_otpok_mask + */ +#define TFA98XX_INTERRUPT_REG_OTDD (0x1 << 1) +#define TFA98XX_INTERRUPT_REG_OTDD_POS 1 +#define TFA98XX_INTERRUPT_REG_OTDD_LEN 1 +#define TFA98XX_INTERRUPT_REG_OTDD_MAX 1 +#define TFA98XX_INTERRUPT_REG_OTDD_MSK 0x2 + +/* + * flag_ovpok_mask + */ +#define TFA98XX_INTERRUPT_REG_OVDD (0x1 << 2) +#define TFA98XX_INTERRUPT_REG_OVDD_POS 2 +#define TFA98XX_INTERRUPT_REG_OVDD_LEN 1 +#define TFA98XX_INTERRUPT_REG_OVDD_MAX 1 +#define TFA98XX_INTERRUPT_REG_OVDD_MSK 0x4 + +/* + * flag_uvpok_mask + */ +#define TFA98XX_INTERRUPT_REG_UVDD (0x1 << 3) +#define TFA98XX_INTERRUPT_REG_UVDD_POS 3 +#define TFA98XX_INTERRUPT_REG_UVDD_LEN 1 +#define TFA98XX_INTERRUPT_REG_UVDD_MAX 1 +#define TFA98XX_INTERRUPT_REG_UVDD_MSK 0x8 + +/* + * flag_ocp_alarm_mask + */ +#define TFA98XX_INTERRUPT_REG_OCDD (0x1 << 4) +#define TFA98XX_INTERRUPT_REG_OCDD_POS 4 +#define TFA98XX_INTERRUPT_REG_OCDD_LEN 1 +#define TFA98XX_INTERRUPT_REG_OCDD_MAX 1 +#define TFA98XX_INTERRUPT_REG_OCDD_MSK 0x10 + +/* + * flag_clocks_stable_mask + */ +#define TFA98XX_INTERRUPT_REG_CLKD (0x1 << 5) +#define TFA98XX_INTERRUPT_REG_CLKD_POS 5 +#define TFA98XX_INTERRUPT_REG_CLKD_LEN 1 +#define TFA98XX_INTERRUPT_REG_CLKD_MAX 1 +#define TFA98XX_INTERRUPT_REG_CLKD_MSK 0x20 + +/* + * flag_pwrokbst_mask + */ +#define TFA98XX_INTERRUPT_REG_DCCD (0x1 << 6) +#define TFA98XX_INTERRUPT_REG_DCCD_POS 6 +#define TFA98XX_INTERRUPT_REG_DCCD_LEN 1 +#define TFA98XX_INTERRUPT_REG_DCCD_MAX 1 +#define TFA98XX_INTERRUPT_REG_DCCD_MSK 0x40 + +/* + * flag_cf_speakererror_mask + */ +#define TFA98XX_INTERRUPT_REG_SPKD (0x1 << 7) +#define TFA98XX_INTERRUPT_REG_SPKD_POS 7 +#define TFA98XX_INTERRUPT_REG_SPKD_LEN 1 +#define TFA98XX_INTERRUPT_REG_SPKD_MAX 1 +#define TFA98XX_INTERRUPT_REG_SPKD_MSK 0x80 + +/* + * flag_watchdog_reset_mask + */ +#define TFA98XX_INTERRUPT_REG_WDD (0x1 << 8) +#define TFA98XX_INTERRUPT_REG_WDD_POS 8 +#define TFA98XX_INTERRUPT_REG_WDD_LEN 1 +#define TFA98XX_INTERRUPT_REG_WDD_MAX 1 +#define TFA98XX_INTERRUPT_REG_WDD_MSK 0x100 + +/* + * enable_interrupt + */ +#define TFA98XX_INTERRUPT_REG_INT (0x1 << 14) +#define TFA98XX_INTERRUPT_REG_INT_POS 14 +#define TFA98XX_INTERRUPT_REG_INT_LEN 1 +#define TFA98XX_INTERRUPT_REG_INT_MAX 1 +#define TFA98XX_INTERRUPT_REG_INT_MSK 0x4000 + +/* + * invert_int_polarity + */ +#define TFA98XX_INTERRUPT_REG_INTP (0x1 << 15) +#define TFA98XX_INTERRUPT_REG_INTP_POS 15 +#define TFA98XX_INTERRUPT_REG_INTP_LEN 1 +#define TFA98XX_INTERRUPT_REG_INTP_MAX 1 +#define TFA98XX_INTERRUPT_REG_INTP_MSK 0x8000 + +/* + * (0x10)-pdm_ctrl + */ + +/* + * pdm_i2s_input + */ +#define TFA98XX_PDM_CTRL_PDMSEL (0x1 << 0) +#define TFA98XX_PDM_CTRL_PDMSEL_POS 0 +#define TFA98XX_PDM_CTRL_PDMSEL_LEN 1 +#define TFA98XX_PDM_CTRL_PDMSEL_MAX 1 +#define TFA98XX_PDM_CTRL_PDMSEL_MSK 0x1 + +/* + * I2S_master_ena + */ +#define TFA98XX_PDM_CTRL_I2SMOUTEN (0x1 << 1) +#define TFA98XX_PDM_CTRL_I2SMOUTEN_POS 1 +#define TFA98XX_PDM_CTRL_I2SMOUTEN_LEN 1 +#define TFA98XX_PDM_CTRL_I2SMOUTEN_MAX 1 +#define TFA98XX_PDM_CTRL_I2SMOUTEN_MSK 0x2 + +/* + * pdm_out_sel_r + */ +#define TFA98XX_PDM_CTRL_PDMORSEL (0x3 << 2) +#define TFA98XX_PDM_CTRL_PDMORSEL_POS 2 +#define TFA98XX_PDM_CTRL_PDMORSEL_LEN 2 +#define TFA98XX_PDM_CTRL_PDMORSEL_MAX 3 +#define TFA98XX_PDM_CTRL_PDMORSEL_MSK 0xc + +/* + * pdm_out_sel_l + */ +#define TFA98XX_PDM_CTRL_PDMOLSEL (0x3 << 4) +#define TFA98XX_PDM_CTRL_PDMOLSEL_POS 4 +#define TFA98XX_PDM_CTRL_PDMOLSEL_LEN 2 +#define TFA98XX_PDM_CTRL_PDMOLSEL_MAX 3 +#define TFA98XX_PDM_CTRL_PDMOLSEL_MSK 0x30 + +/* + * micdat_out_sel + */ +#define TFA98XX_PDM_CTRL_PADSEL (0x3 << 6) +#define TFA98XX_PDM_CTRL_PADSEL_POS 6 +#define TFA98XX_PDM_CTRL_PADSEL_LEN 2 +#define TFA98XX_PDM_CTRL_PADSEL_MAX 3 +#define TFA98XX_PDM_CTRL_PADSEL_MSK 0xc0 + +/* + * (0x11)-pdm_out_ctrl + */ + +/* + * secure_dly + */ +#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN (0x1 << 0) +#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_POS 0 +#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_LEN 1 +#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_MAX 1 +#define TFA98XX_PDM_OUT_CTRL_PDMOSDEN_MSK 0x1 + +/* + * d_out_valid_rf_mux + */ +#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF (0x1 << 1) +#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_POS 1 +#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_LEN 1 +#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_MAX 1 +#define TFA98XX_PDM_OUT_CTRL_PDMOSDCF_MSK 0x2 + +/* + * Speak_As_Mic_en + */ +#define TFA98XX_PDM_OUT_CTRL_SAAMEN (0x1 << 4) +#define TFA98XX_PDM_OUT_CTRL_SAAMEN_POS 4 +#define TFA98XX_PDM_OUT_CTRL_SAAMEN_LEN 1 +#define TFA98XX_PDM_OUT_CTRL_SAAMEN_MAX 1 +#define TFA98XX_PDM_OUT_CTRL_SAAMEN_MSK 0x10 + +/* + * speak_as_mic_lp_mode + */ +#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN (0x1 << 5) +#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_POS 5 +#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_LEN 1 +#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_MAX 1 +#define TFA98XX_PDM_OUT_CTRL_SAAMLPEN_MSK 0x20 + +/* + * pdm_out_rate + */ +#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN (0x1 << 6) +#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_POS 6 +#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_LEN 1 +#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_MAX 1 +#define TFA98XX_PDM_OUT_CTRL_PDMOINTEN_MSK 0x40 + +/* + * (0x12)-pdm_ds4_r + */ + +/* + * ds4_g1_r + */ +#define TFA98XX_PDM_DS4_R_PDMORG1 (0xf << 0) +#define TFA98XX_PDM_DS4_R_PDMORG1_POS 0 +#define TFA98XX_PDM_DS4_R_PDMORG1_LEN 4 +#define TFA98XX_PDM_DS4_R_PDMORG1_MAX 15 +#define TFA98XX_PDM_DS4_R_PDMORG1_MSK 0xf + +/* + * ds4_g2_r + */ +#define TFA98XX_PDM_DS4_R_PDMORG2 (0xf << 4) +#define TFA98XX_PDM_DS4_R_PDMORG2_POS 4 +#define TFA98XX_PDM_DS4_R_PDMORG2_LEN 4 +#define TFA98XX_PDM_DS4_R_PDMORG2_MAX 15 +#define TFA98XX_PDM_DS4_R_PDMORG2_MSK 0xf0 + +/* + * (0x13)-pdm_ds4_l + */ + +/* + * ds4_g1_l + */ +#define TFA98XX_PDM_DS4_L_PDMOLG1 (0xf << 0) +#define TFA98XX_PDM_DS4_L_PDMOLG1_POS 0 +#define TFA98XX_PDM_DS4_L_PDMOLG1_LEN 4 +#define TFA98XX_PDM_DS4_L_PDMOLG1_MAX 15 +#define TFA98XX_PDM_DS4_L_PDMOLG1_MSK 0xf + +/* + * ds4_g2_l + */ +#define TFA98XX_PDM_DS4_L_PDMOLG2 (0xf << 4) +#define TFA98XX_PDM_DS4_L_PDMOLG2_POS 4 +#define TFA98XX_PDM_DS4_L_PDMOLG2_LEN 4 +#define TFA98XX_PDM_DS4_L_PDMOLG2_MAX 15 +#define TFA98XX_PDM_DS4_L_PDMOLG2_MSK 0xf0 + +/* + * (0x22)-ctrl_saam_pga + */ + +/* + * Ctrl_saam_pga_gain + */ +#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN (0x7 << 0) +#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_POS 0 +#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_LEN 3 +#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_MAX 7 +#define TFA98XX_CTRL_SAAM_PGA_SAAMGAIN_MSK 0x7 + +/* + * ctrl_saam_pga_src + */ +#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL (0x1 << 5) +#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_POS 5 +#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_LEN 1 +#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_MAX 1 +#define TFA98XX_CTRL_SAAM_PGA_SAAMPGACTRL_MSK 0x20 + +/* + * (0x25)-misc_ctrl + */ + +/* + * pll_fcco + */ +#define TFA98XX_MISC_CTRL_PLLCCOSEL (0x1 << 0) +#define TFA98XX_MISC_CTRL_PLLCCOSEL_POS 0 +#define TFA98XX_MISC_CTRL_PLLCCOSEL_LEN 1 +#define TFA98XX_MISC_CTRL_PLLCCOSEL_MAX 1 +#define TFA98XX_MISC_CTRL_PLLCCOSEL_MSK 0x1 + +/* + * (0x46)-CurrentSense1 + */ + +/* + * bypass_gc + */ +#define TFA98XX_CURRENTSENSE1_CSBYPGC (0x1 << 0) +#define TFA98XX_CURRENTSENSE1_CSBYPGC_POS 0 +#define TFA98XX_CURRENTSENSE1_CSBYPGC_LEN 1 +#define TFA98XX_CURRENTSENSE1_CSBYPGC_MAX 1 +#define TFA98XX_CURRENTSENSE1_CSBYPGC_MSK 0x1 + +/* + * (0x49)-CurrentSense4 + */ + +/* + * ctrl_bypassclip + */ +#define TFA98XX_CURRENTSENSE4_CLIP (0x1 << 0) +#define TFA98XX_CURRENTSENSE4_CLIP_POS 0 +#define TFA98XX_CURRENTSENSE4_CLIP_LEN 1 +#define TFA98XX_CURRENTSENSE4_CLIP_MAX 1 +#define TFA98XX_CURRENTSENSE4_CLIP_MSK 0x1 + +/* + * ctrl_bypassclip2 + */ +#define TFA98XX_CURRENTSENSE4_CLIP2 (0x1 << 1) +#define TFA98XX_CURRENTSENSE4_CLIP2_POS 1 +#define TFA98XX_CURRENTSENSE4_CLIP2_LEN 1 +#define TFA98XX_CURRENTSENSE4_CLIP2_MAX 1 +#define TFA98XX_CURRENTSENSE4_CLIP2_MSK 0x2 + +/* + * (0x62)-Hidden_mtp_ctrl_reg3 + */ + +/* + * (0x70)-cf_controls + */ + +/* + * cf_rst_dsp + */ +#define TFA98XX_CF_CONTROLS_RST (0x1 << 0) +#define TFA98XX_CF_CONTROLS_RST_POS 0 +#define TFA98XX_CF_CONTROLS_RST_LEN 1 +#define TFA98XX_CF_CONTROLS_RST_MAX 1 +#define TFA98XX_CF_CONTROLS_RST_MSK 0x1 + +/* + * cf_dmem + */ +#define TFA98XX_CF_CONTROLS_DMEM (0x3 << 1) +#define TFA98XX_CF_CONTROLS_DMEM_POS 1 +#define TFA98XX_CF_CONTROLS_DMEM_LEN 2 +#define TFA98XX_CF_CONTROLS_DMEM_MAX 3 +#define TFA98XX_CF_CONTROLS_DMEM_MSK 0x6 + +/* + * cf_aif + */ +#define TFA98XX_CF_CONTROLS_AIF (0x1 << 3) +#define TFA98XX_CF_CONTROLS_AIF_POS 3 +#define TFA98XX_CF_CONTROLS_AIF_LEN 1 +#define TFA98XX_CF_CONTROLS_AIF_MAX 1 +#define TFA98XX_CF_CONTROLS_AIF_MSK 0x8 + +/* + * cf_int + */ +#define TFA98XX_CF_CONTROLS_CFINT (0x1 << 4) +#define TFA98XX_CF_CONTROLS_CFINT_POS 4 +#define TFA98XX_CF_CONTROLS_CFINT_LEN 1 +#define TFA98XX_CF_CONTROLS_CFINT_MAX 1 +#define TFA98XX_CF_CONTROLS_CFINT_MSK 0x10 + +/* + * cf_req + */ +#define TFA98XX_CF_CONTROLS_REQ (0xff << 8) +#define TFA98XX_CF_CONTROLS_REQ_POS 8 +#define TFA98XX_CF_CONTROLS_REQ_LEN 8 +#define TFA98XX_CF_CONTROLS_REQ_MAX 255 +#define TFA98XX_CF_CONTROLS_REQ_MSK 0xff00 + +/* + * (0x71)-cf_mad + */ + +/* + * cf_madd + */ +#define TFA9891_CF_MAD_MADD (0xffff << 0) +#define TFA9891_CF_MAD_MADD_POS 0 +#define TFA9891_CF_MAD_MADD_LEN 16 +#define TFA9891_CF_MAD_MADD_MAX 65535 +#define TFA9891_CF_MAD_MADD_MSK 0xffff + +/* + * (0x72)-cf_mem + */ + +/* + * cf_mema + */ +#define TFA9891_CF_MEM_MEMA (0xffff << 0) +#define TFA9891_CF_MEM_MEMA_POS 0 +#define TFA9891_CF_MEM_MEMA_LEN 16 +#define TFA9891_CF_MEM_MEMA_MAX 65535 +#define TFA9891_CF_MEM_MEMA_MSK 0xffff + +/* + * (0x73)-cf_status + */ + +/* + * cf_err + */ +#define TFA9891_CF_STATUS_ERR (0xff << 0) +#define TFA9891_CF_STATUS_ERR_POS 0 +#define TFA9891_CF_STATUS_ERR_LEN 8 +#define TFA9891_CF_STATUS_ERR_MAX 255 +#define TFA9891_CF_STATUS_ERR_MSK 0xff + +/* + * cf_ack + */ +#define TFA9891_CF_STATUS_ACK (0xff << 8) +#define TFA9891_CF_STATUS_ACK_POS 8 +#define TFA9891_CF_STATUS_ACK_LEN 8 +#define TFA9891_CF_STATUS_ACK_MAX 255 +#define TFA9891_CF_STATUS_ACK_MSK 0xff00 + +/* + * (0x80)-Key2Protected_spkr_cal_mtp + */ + +/* + * calibration_onetime + */ +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC (0x1 << 0) +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_POS 0 +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_LEN 1 +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_MAX 1 +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPOTC_MSK 0x1 + +/* + * calibr_ron_done + */ +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX (0x1 << 1) +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_POS 1 +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_LEN 1 +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_MAX 1 +#define TFA98XX_KEY2PROTECTED_SPKR_CAL_MTP_MTPEX_MSK 0x2 + +#endif /* TFA9891_GENREGS_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_tfafieldnames.h new file mode 100644 index 000000000000..943a31d5e900 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_tfafieldnames.h @@ -0,0 +1,1000 @@ +/* + * tfa9891_tfafieldnames.h + * + * Created on: Jul 16, 2015 + * Author: wim + */ + +#ifndef TFA_INC_TFA9891_TFAFIELDNAMES_H_ +#define TFA_INC_TFA9891_TFAFIELDNAMES_H_ + +/** Filename: Tfa9891_TfaFieldnames.h + * This file was generated automatically on 07/16/15 at 15:00:02. + * Source file: TFA9891_I2C_list_V13.xls + */ + +#define TFA9891_I2CVERSION 13 + +#define TFA9891_NAMETABLE \ + static tfaBfName_t Tfa9891DatasheetNames[] = { \ + { 0x0, \ + "VDDS" }, /* POR , */ \ + { 0x10, \ + "PLLS" }, /* PLL , */ \ + { 0x20, \ + "OTDS" }, /* OTP , */ \ + { 0x30, \ + "OVDS" }, /* OVP , */ \ + { 0x40, \ + "UVDS" }, /* UVP , */ \ + { 0x50, \ + "OCDS" }, /* OCP , */ \ + { 0x60, \ + "CLKS" }, /* Clocks , */ \ + { 0x70, \ + "CLIPS" }, /* CLIP , */ \ + { 0x80, \ + "MTPB" }, /* MTP , */ \ + { 0x90, \ + "DCCS" }, /* BOOST , */ \ + { 0xa0, \ + "SPKS" }, /* Speaker , */ \ + { 0xb0, \ + "ACS" }, /* cold start flag , */ \ + { 0xc0, \ + "SWS" }, /* flag engage , */ \ + { 0xd0, \ + "WDS" }, /* flag watchdog reset , */ \ + { 0xe0, \ + "AMPS" }, /* amplifier is enabled by manager , */ \ + { 0xf0, \ + "AREFS" }, /* references are enabled by manager , */ \ + { 0x109, \ + "BATS" }, /* Battery voltage readout; 0[V]..5.5[V] , */ \ + { 0x208, \ + "TEMPS" }, /* Temperature readout , */ \ + { 0x307, \ + "REV" }, /* Device Revision , */ \ + { 0x402, \ + "I2SF" }, /* I2SFormat data 1 input , */ \ + { 0x431, \ + "CHS12" }, /* ChannelSelection data1 input (In CoolFlux) , */ \ + { 0x450, \ + "CHS3" }, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \ + { 0x461, \ + "CHSA" }, /* Input selection for amplifier , */ \ + { 0x481, \ + "I2SDOC" }, /* Selection for I2S data out , */ \ + { 0x4a0, \ + "DISP" }, /* idp protection , */ \ + { 0x4b0, \ + "I2SDOE" }, /* Enable data output , */ \ + { 0x4c3, \ + "I2SSR" }, /* sample rate setting , */ \ + { 0x501, \ + "BSSCR" }, /* ProtectionAttackTime , */ \ + { 0x523, \ + "BSST" }, /* ProtectionThreshold , */ \ + { 0x561, \ + "BSSRL" }, /* ProtectionMaximumReduction , */ \ + { 0x582, \ + "BSSRR" }, /* Protection Release Timer , */ \ + { 0x5b1, \ + "BSSHY" }, /* ProtectionHysterese , */ \ + { 0x5e0, \ + "BSSR" }, /* battery voltage for I2C read out only , */ \ + { 0x5f0, \ + "BSSBY" }, /* bypass clipper battery protection , */ \ + { 0x600, \ + "DPSA" }, /* Enable dynamic powerstage activation , */ \ + { 0x613, \ + "AMPSL" }, /* control slope , */ \ + { 0x650, \ + "CFSM" }, /* Soft mute in CoolFlux , */ \ + { 0x670, \ + "BSSS" }, /* batsensesteepness , */ \ + { 0x687, \ + "VOL" }, /* volume control (in CoolFlux) , */ \ + { 0x702, \ + "DCVO" }, /* Boost voltage , */ \ + { 0x732, \ + "DCMCC" }, /* Max boost coil current , */ \ + { 0x7a0, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x7b0, \ + "DCSR" }, /* Soft RampUp/Down mode for DCDC controller , */ \ + { 0x800, \ + "TROS" }, /* select external temperature also the ext_temp will be put on the temp read out , */ \ + { 0x818, \ + "EXTTS" }, /* external temperature setting to be given by host , */ \ + { 0x900, \ + "PWDN" }, /* ON/OFF , */ \ + { 0x910, \ + "I2CR" }, /* I2CReset , */ \ + { 0x920, \ + "CFE" }, /* EnableCoolFlux , */ \ + { 0x930, \ + "AMPE" }, /* EnableAmplifier , */ \ + { 0x940, \ + "DCA" }, /* EnableBoost , */ \ + { 0x950, \ + "SBSL" }, /* Coolflux configured , */ \ + { 0x960, \ + "AMPC" }, /* Selection on how AmplifierEnabling , */ \ + { 0x970, \ + "DCDIS" }, /* DCDC not connected , */ \ + { 0x980, \ + "PSDR" }, /* Iddq test amplifier , */ \ + { 0x991, \ + "DCCV" }, /* Coil Value , */ \ + { 0x9b1, \ + "CCFD" }, /* Selection CoolFluxClock , */ \ + { 0x9d0, \ + "ISEL" }, /* Interface Selection , */ \ + { 0x9e0, \ + "IPLL" }, /* selection input PLL for lock , */ \ + { 0xa02, \ + "DOLS" }, /* Output selection dataout left channel , */ \ + { 0xa32, \ + "DORS" }, /* Output selection dataout right channel , */ \ + { 0xa62, \ + "SPKL" }, /* Selection speaker induction , */ \ + { 0xa91, \ + "SPKR" }, /* Selection speaker impedance , */ \ + { 0xab3, \ + "DCFG" }, /* DCDC speaker current compensation gain , */ \ + { 0xb07, \ + "MTPK" }, /* MTP KEY2 register , */ \ + { 0xf00, \ + "VDDD" }, /* mask flag_por for interupt generation , */ \ + { 0xf10, \ + "OTDD" }, /* mask flag_otpok for interupt generation , */ \ + { 0xf20, \ + "OVDD" }, /* mask flag_ovpok for interupt generation , */ \ + { 0xf30, \ + "UVDD" }, /* mask flag_uvpok for interupt generation , */ \ + { 0xf40, \ + "OCDD" }, /* mask flag_ocp_alarm for interupt generation , */ \ + { 0xf50, \ + "CLKD" }, /* mask flag_clocks_stable for interupt generation , */ \ + { 0xf60, \ + "DCCD" }, /* mask flag_pwrokbst for interupt generation , */ \ + { 0xf70, \ + "SPKD" }, /* mask flag_cf_speakererror for interupt generation , */ \ + { 0xf80, \ + "WDD" }, /* mask flag_watchdog_reset for interupt generation , */ \ + { 0xfe0, \ + "INT" }, /* enabling interrupt , */ \ + { 0xff0, \ + "INTP" }, /* Setting polarity interupt , */ \ + { 0x1000, \ + "PDMSEL" }, /* Audio input interface mode , */ \ + { 0x1010, \ + "I2SMOUTEN" }, /* I2S Master enable (CLK and WS pads) , */ \ + { 0x1021, \ + "PDMORSEL" }, /* PDM Output right channel source selection , */ \ + { 0x1041, \ + "PDMOLSEL" }, /* PDM Output Left/Mono channel source selection , */ \ + { 0x1061, \ + "PADSEL" }, /* Output interface mode and ball selection , */ \ + { 0x1100, \ + "PDMOSDEN" }, /* Secure delay Cell , */ \ + { 0x1110, \ + "PDMOSDCF" }, /* Rising Falling Resync control Mux , */ \ + { 0x1140, \ + "SAAMEN" }, /* Speaker As a Mic feature ON/OFF , */ \ + { 0x1150, \ + "SAAMLPEN" }, /* speaker_as_mic low power mode (only in PDM_out mode), */ \ + { 0x1160, \ + "PDMOINTEN" }, /* PDM output interpolation ratio , */ \ + { 0x1203, \ + "PDMORG1" }, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */ \ + { 0x1243, \ + "PDMORG2" }, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */ \ + { 0x1303, \ + "PDMOLG1" }, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */ \ + { 0x1343, \ + "PDMOLG2" }, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */ \ + { 0x2202, \ + "SAAMGAIN" }, /* pga gain , */ \ + { 0x2250, \ + "SAAMPGACTRL" }, /* 0 = active input common mode voltage source at the attenuator/PGA level, */ \ + { 0x2500, \ + "PLLCCOSEL" }, /* pll cco frequency , */ \ + { 0x4600, \ + "CSBYPGC" }, /* bypass_gc, bypasses the CS gain correction , */ \ + { 0x4900, \ + "CLIP" }, /* Bypass clip control (function depending on digimux clip_x), */ \ + { 0x4910, \ + "CLIP2" }, /* Bypass clip control (function depending on digimux clip_x), */ \ + { 0x62b0, \ + "CIMTP" }, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */ \ + { 0x7000, \ + "RST" }, /* Reset CoolFlux DSP , */ \ + { 0x7011, \ + "DMEM" }, /* Target memory for access , */ \ + { 0x7030, \ + "AIF" }, /* Autoincrement-flag for memory-address , */ \ + { 0x7040, \ + "CFINT" }, /* Interrupt CoolFlux DSP , */ \ + { 0x7087, \ + "REQ" }, /* request for access (8 channels) , */ \ + { 0x710f, \ + "MADD" }, /* memory-address to be accessed , */ \ + { 0x720f, \ + "MEMA" }, /* activate memory access (24- or 32-bits data is written/read to/from memory, */ \ + { 0x7307, \ + "ERR" }, /* cf error Flags , */ \ + { 0x7387, \ + "ACK" }, /* acknowledge of requests (8 channels")" , */ \ + { 0x8000, \ + "MTPOTC" }, /* Calibration schedule (key2 protected) , */ \ + { 0x8010, \ + "MTPEX" }, /* (key2 protected) calibration of Ron has been executed, */ \ + { 0x8045, "SWPROFIL" }, \ + { 0x80a5, "SWVSTEP" }, \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9891_BITNAMETABLE \ + static tfaBfName_t Tfa9891BitNames[] = { \ + { 0x0, \ + "POR" }, /* POR , */ \ + { 0x10, \ + "PLL_LOCK" }, /* PLL , */ \ + { 0x20, \ + "flag_otpok" }, /* OTP , */ \ + { 0x30, \ + "flag_ovpok" }, /* OVP , */ \ + { 0x40, \ + "flag_uvpok" }, /* UVP , */ \ + { 0x50, \ + "flag_OCP_alarm" }, /* OCP , */ \ + { 0x60, \ + "flag_clocks_stable" }, /* Clocks , */ \ + { 0x70, \ + "CLIP" }, /* CLIP , */ \ + { 0x80, \ + "mtp_busy" }, /* MTP , */ \ + { 0x90, \ + "flag_pwrokbst" }, /* BOOST , */ \ + { 0xa0, \ + "flag_cf_speakererror" }, /* Speaker , */ \ + { 0xb0, \ + "flag_cold_started" }, /* cold start flag , */ \ + { 0xc0, \ + "flag_engage" }, /* flag engage , */ \ + { 0xd0, \ + "flag_watchdog_reset" }, /* flag watchdog reset , */ \ + { 0xe0, \ + "flag_enbl_amp" }, /* amplifier is enabled by manager , */ \ + { 0xf0, \ + "flag_enbl_ref" }, /* references are enabled by manager , */ \ + { 0x109, \ + "bat_adc" }, /* Battery voltage readout; 0[V]..5.5[V] , */ \ + { 0x208, \ + "temp_adc" }, /* Temperature readout , */ \ + { 0x307, \ + "rev_reg" }, /* Device Revision , */ \ + { 0x402, \ + "i2s_seti" }, /* I2SFormat data 1 input , */ \ + { 0x431, \ + "chan_sel1" }, /* ChannelSelection data1 input (In CoolFlux) , */ \ + { 0x450, \ + "lr_sw_i2si2" }, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */ \ + { 0x461, \ + "input_sel" }, /* Input selection for amplifier , */ \ + { 0x481, \ + "datao_sel" }, /* Selection for I2S data out , */ \ + { 0x4a0, \ + "disable_idp" }, /* idp protection , */ \ + { 0x4b0, \ + "enbl_datao" }, /* Enable data output , */ \ + { 0x4c3, \ + "i2s_fs" }, /* sample rate setting , */ \ + { 0x501, \ + "vbat_prot_attacktime" }, /* ProtectionAttackTime , */ \ + { 0x523, \ + "vbat_prot_thlevel" }, /* ProtectionThreshold , */ \ + { 0x561, \ + "vbat_prot_max_reduct" }, /* ProtectionMaximumReduction , */ \ + { 0x582, \ + "vbat_prot_release_t" }, /* Protection Release Timer , */ \ + { 0x5b1, \ + "vbat_prot_hysterese" }, /* ProtectionHysterese , */ \ + { 0x5d0, \ + "reset_min_vbat" }, /* reset clipper , */ \ + { 0x5e0, \ + "sel_vbat" }, /* battery voltage for I2C read out only , */ \ + { 0x5f0, \ + "bypass_clipper" }, /* bypass clipper battery protection , */ \ + { 0x600, \ + "dpsa" }, /* Enable dynamic powerstage activation , */ \ + { 0x613, \ + "ctrl_slope" }, /* control slope , */ \ + { 0x650, \ + "cf_mute" }, /* Soft mute in CoolFlux , */ \ + { 0x660, \ + "sel_other_vamp" }, /* Input selection for the second channel of the DCDC inteligent mode detector, */ \ + { 0x670, \ + "ctrl_batsensesteepness" }, /* batsensesteepness , */ \ + { 0x687, \ + "vol" }, /* volume control (in CoolFlux) , */ \ + { 0x702, \ + "ctrl_bstvolt" }, /* Boost voltage , */ \ + { 0x732, \ + "ctrl_bstcur" }, /* Max boost coil current , */ \ + { 0x761, \ + "ctrl_slopebst_1_0" }, /* Setting for the slope of the boost converter power stage, */ \ + { 0x781, \ + "ctrl_slopebst_3_2" }, /* Setting for the part of the power transistor voltage to be used in peak current mode control, */ \ + { 0x7a0, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x7b0, \ + "boost_speed" }, /* Soft RampUp/Down mode for DCDC controller , */ \ + { 0x7c1, \ + "ctrl_delay_comp_dcdc" }, /* delay compensation in current patg compared to delay in the audio path (relative) , */ \ + { 0x7e0, \ + "boost_input" }, /* Selection intelligent boost detector input , */ \ + { 0x7f0, \ + "ctrl_supplysense" }, /* ADC10 input selection , */ \ + { 0x800, \ + "ext_temp_sel" }, /* select external temperature also the ext_temp will be put on the temp read out , */ \ + { 0x818, \ + "ext_temp" }, /* external temperature setting to be given by host , */ \ + { 0x8a0, \ + "ctrl_spk_coilpvp_bst" }, /* Peak voltage protection boost converter , */ \ + { 0x8b2, \ + "ctrl_dcdc_synchronisation" }, /* DCDC synchronisation off + 7 positions , */ \ + { 0x8e0, \ + "ctrl_cs_samplevalid" }, /* sample valid moment for CS in single sample moment mode, */ \ + { 0x900, \ + "PowerDown" }, /* ON/OFF , */ \ + { 0x910, \ + "reset" }, /* I2CReset , */ \ + { 0x920, \ + "enbl_coolflux" }, /* EnableCoolFlux , */ \ + { 0x930, \ + "enbl_amplifier" }, /* EnableAmplifier , */ \ + { 0x940, \ + "enbl_boost" }, /* EnableBoost , */ \ + { 0x950, \ + "cf_configured" }, /* Coolflux configured , */ \ + { 0x960, \ + "sel_enbl_amplifier" }, /* Selection on how AmplifierEnabling , */ \ + { 0x970, \ + "dcdcoff_mode" }, /* DCDC not connected , */ \ + { 0x980, \ + "cttr_iddqtest" }, /* Iddq test amplifier , */ \ + { 0x991, \ + "ctrl_coil_value" }, /* Coil Value , */ \ + { 0x9b1, \ + "ctrl_sel_cf_clock" }, /* Selection CoolFluxClock , */ \ + { 0x9d0, \ + "intf_sel" }, /* Interface Selection , */ \ + { 0x9e0, \ + "sel_ws_bck" }, /* selection input PLL for lock , */ \ + { 0xa02, \ + "sel_i2so_l" }, /* Output selection dataout left channel , */ \ + { 0xa32, \ + "sel_i2so_r" }, /* Output selection dataout right channel , */ \ + { 0xa62, \ + "ctrl_spkr_coil" }, /* Selection speaker induction , */ \ + { 0xa91, \ + "ctrl_spr_res" }, /* Selection speaker impedance , */ \ + { 0xab3, \ + "ctrl_dcdc_spkr_i_comp_gain" }, /* DCDC speaker current compensation gain , */ \ + { 0xaf0, \ + "ctrl_dcdc_spkr_i_comp_sign" }, /* DCDC speaker current compensation sign , */ \ + { 0xb07, \ + "MTP_key2" }, /* MTP KEY2 register , */ \ + { 0xc0c, \ + "clk_sync_delay" }, /* Delay count for clock synchronisation , */ \ + { 0xcf0, \ + "enbl_clk_sync" }, /* Enable CGU clock synchronisation , */ \ + { 0xd0c, \ + "adc_sync_delay" }, /* Delay count for ADC synchronisation , */ \ + { 0xdf0, \ + "enable_adc_sync" }, /* Enable ADC synchronisation , */ \ + { 0xe00, \ + "bypass_dcdc_curr_prot" }, /* to switch off dcdc reduction with bat prot , */ \ + { 0xe24, \ + "ctrl_digtoana6_2" }, /* for extra connections digital to analog , */ \ + { 0xe70, \ + "switch_on_icomp" }, /* icomp dem switch , */ \ + { 0xe87, \ + "reserve_reg_1_7_0" }, /* reserved , */ \ + { 0xf00, \ + "flag_por_mask" }, /* mask flag_por for interupt generation , */ \ + { 0xf10, \ + "flag_otpok_mask" }, /* mask flag_otpok for interupt generation , */ \ + { 0xf20, \ + "flag_ovpok_mask" }, /* mask flag_ovpok for interupt generation , */ \ + { 0xf30, \ + "flag_uvpok_mask" }, /* mask flag_uvpok for interupt generation , */ \ + { 0xf40, \ + "flag_ocp_alarm_mask" }, /* mask flag_ocp_alarm for interupt generation , */ \ + { 0xf50, \ + "flag_clocks_stable_mask" }, /* mask flag_clocks_stable for interupt generation , */ \ + { 0xf60, \ + "flag_pwrokbst_mask" }, /* mask flag_pwrokbst for interupt generation , */ \ + { 0xf70, \ + "flag_cf_speakererror_mask" }, /* mask flag_cf_speakererror for interupt generation , */ \ + { 0xf80, \ + "flag_watchdog_reset_mask" }, /* mask flag_watchdog_reset for interupt generation , */ \ + { 0xf90, \ + "flag_lost_clk_mask" }, /* mask flag_lost_clk for interupt generation , */ \ + { 0xfe0, \ + "enable_interrupt" }, /* enabling interrupt , */ \ + { 0xff0, \ + "invert_int_polarity" }, /* Setting polarity interupt , */ \ + { 0x1000, \ + "pdm_i2s_input" }, /* Audio input interface mode , */ \ + { 0x1010, \ + "I2S_master_ena" }, /* I2S Master enable (CLK and WS pads) , */ \ + { 0x1021, \ + "pdm_out_sel_r" }, /* PDM Output right channel source selection , */ \ + { 0x1041, \ + "pdm_out_sel_l" }, /* PDM Output Left/Mono channel source selection , */ \ + { 0x1061, \ + "micdat_out_sel" }, /* Output interface mode and ball selection , */ \ + { 0x1100, \ + "secure_dly" }, /* Secure delay Cell , */ \ + { 0x1110, \ + "d_out_valid_rf_mux" }, /* Rising Falling Resync control Mux , */ \ + { 0x1140, \ + "Speak_As_Mic_en" }, /* Speaker As a Mic feature ON/OFF , */ \ + { 0x1150, \ + "speak_as_mic_lp_mode" }, /* speaker_as_mic low power mode (only in PDM_out mode), */ \ + { 0x1160, \ + "pdm_out_rate" }, /* PDM output interpolation ratio , */ \ + { 0x1203, \ + "ds4_g1_r" }, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */ \ + { 0x1243, \ + "ds4_g2_r" }, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */ \ + { 0x1303, \ + "ds4_g1_l" }, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */ \ + { 0x1343, \ + "ds4_g2_l" }, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */ \ + { 0x1400, \ + "clk_secure_dly" }, /* Secure delay Cell on clock path , */ \ + { 0x1410, \ + "data_secure_dly" }, /* Secure delay Cell enable on PDM data path , */ \ + { 0x2202, \ + "Ctrl_saam_pga_gain" }, /* pga gain , */ \ + { 0x2250, \ + "ctrl_saam_pga_src" }, /* 0 = active input common mode voltage source at the attenuator/PGA level, */ \ + { 0x2300, \ + "flag_saam_spare" }, /* spare flag , */ \ + { 0x2400, \ + "ctrl_saam_pga_tm" }, /* enables PGA test mode , */ \ + { 0x2500, \ + "pll_fcco" }, /* pll cco frequency , */ \ + { 0x3000, \ + "flag_hi_small" }, /* positive small window dcdc converter , */ \ + { 0x3010, \ + "flag_hi_large" }, /* positive large window dcdc converter , */ \ + { 0x3020, \ + "flag_lo_small" }, /* negative small window dcdc converter , */ \ + { 0x3030, \ + "flag_lo_large" }, /* negative large window dcdc converter , */ \ + { 0x3040, \ + "flag_voutcomp" }, /* flag_voutcomp, indication Vset is larger than Vbat, */ \ + { 0x3050, \ + "flag_voutcomp93" }, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat , */ \ + { 0x3060, \ + "flag_voutcomp86" }, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat , */ \ + { 0x3070, \ + "flag_hiz" }, /* flag_hiz, indication Vbst is larger than Vbat , */ \ + { 0x3080, \ + "flag_hi_peak" }, /* flag_hi_peak, indication hi_peak , */ \ + { 0x3090, \ + "flag_ocpokbst" }, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */ \ + { 0x30a0, \ + "flag_peakcur" }, /* flag_peakcur, indication current is max in dcdc converter, */ \ + { 0x30b0, \ + "flag_ocpokap" }, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */ \ + { 0x30c0, \ + "flag_ocpokan" }, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */ \ + { 0x30d0, \ + "flag_ocpokbp" }, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */ \ + { 0x30e0, \ + "flag_ocpokbn" }, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */ \ + { 0x30f0, \ + "lost_clk" }, /* lost_clk, lost clock indication CGU , */ \ + { 0x310f, \ + "mtp_man_data_out" }, /* single word read from MTP (manual copy) , */ \ + { 0x3200, \ + "key01_locked" }, /* key01_locked, indication key 1 is locked , */ \ + { 0x3210, \ + "key02_locked" }, /* key02_locked, indication key 2 is locked , */ \ + { 0x3225, \ + "mtp_ecc_tcout" }, /* mtp_ecc_tcout , */ \ + { 0x3280, \ + "mtpctrl_valid_test_rd" }, /* mtp test readout for read , */ \ + { 0x3290, \ + "mtpctrl_valid_test_wr" }, /* mtp test readout for write , */ \ + { 0x32a0, \ + "flag_in_alarm_state" }, /* alarm state , */ \ + { 0x32b0, \ + "mtp_ecc_err2" }, /* two or more bit errors detected in MTP, can not reconstruct value, */ \ + { 0x32c0, \ + "mtp_ecc_err1" }, /* one bit error detected in MTP, reconstructed value, */ \ + { 0x32d0, \ + "mtp_mtp_hvf" }, /* high voltage ready flag for MTP , */ \ + { 0x32f0, \ + "mtp_zero_check_fail" }, /* zero check failed (tbd) for MTP , */ \ + { 0x3300, \ + "flag_adc10_ready" }, /* flag_adc10_ready, indication adc10 is ready , */ \ + { 0x3310, \ + "flag_clipa_high" }, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */ \ + { 0x3320, \ + "flag_clipa_low" }, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */ \ + { 0x3330, \ + "flag_clipb_high" }, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */ \ + { 0x3340, \ + "flag_clipb_low" }, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */ \ + { 0x3359, \ + "data_adc10_tempbat" }, /* adc 10 data output for testing , */ \ + { 0x33f0, \ + "flag_vddd_comp_nok" }, /* power switch flag 2 for testing , */ \ + { 0x400f, \ + "hid_code" }, /* hidden code , */ \ + { 0x4100, \ + "bypass_hp" }, /* Bypass_High Pass Filter , */ \ + { 0x4110, \ + "hard_mute" }, /* Hard Mute , */ \ + { 0x4120, \ + "soft_mute" }, /* Soft Mute , */ \ + { 0x4134, \ + "PWM_Delay" }, /* PWM DelayBits to set the delay , */ \ + { 0x4180, \ + "PWM_Shape" }, /* PWM Shape , */ \ + { 0x4190, \ + "PWM_BitLength" }, /* PWM Bitlength in noise shaper , */ \ + { 0x4207, \ + "ctrl_drive" }, /* drive bits to select amount of power stages amplifier, */ \ + { 0x4281, \ + "dpsalevel" }, /* DPSA Threshold level , */ \ + { 0x42a1, \ + "dpsa_release" }, /* DPSA Release time , */ \ + { 0x42c0, \ + "ctrl_coincidence" }, /* Prevent simultaneously switching of output stage , */ \ + { 0x42d0, \ + "ctrl_kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x42e0, \ + "ctrl_test_sdeltaoffset" }, /* ctrl_test_sdeltaoffset , */ \ + { 0x42f0, \ + "ctrl_test_sdeltaclk" }, /* ctrl_test_sdeltaclk , */ \ + { 0x4309, \ + "ctrl_drivebst" }, /* Drive bits to select the powertransistor sections boost converter, */ \ + { 0x43a0, \ + "ctrl_ocptestbst" }, /* Boost OCP. , */ \ + { 0x43c0, \ + "enbl_hi_peak" }, /* enable for high peak comparator , */ \ + { 0x43d0, \ + "test_abistfft_enbl" }, /* FFT coolflux , */ \ + { 0x43e0, \ + "ctrl_sensetest_amp" }, /* sensetest amplifier , */ \ + { 0x43f0, \ + "test_bcontrol" }, /* test _bcontrol , */ \ + { 0x4400, \ + "ctrl_reversebst" }, /* OverCurrent Protection selection of power stage boost converter, */ \ + { 0x4410, \ + "ctrl_sensetest" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0x4420, \ + "enbl_engagebst" }, /* Enable power stage dcdc controller , */ \ + { 0x4430, \ + "enbl_hi_small" }, /* Enable bit of hi (small) comparator , */ \ + { 0x4440, \ + "enbl_hi_large" }, /* Enable bit of hi (large) comparator , */ \ + { 0x4450, \ + "enbl_lo_small" }, /* Enable bit of lo (small) comparator , */ \ + { 0x4460, \ + "enbl_lo_large" }, /* Enable bit of lo (large) comparator , */ \ + { 0x4470, \ + "enbl_slopecur" }, /* Enable bit of max-current dac , */ \ + { 0x4480, \ + "enbl_voutcomp" }, /* Enable vout comparators , */ \ + { 0x4490, \ + "enbl_voutcomp93" }, /* Enable vout-93 comparators , */ \ + { 0x44a0, \ + "enbl_voutcomp86" }, /* Enable vout-86 comparators , */ \ + { 0x44b0, \ + "enbl_hizcom" }, /* Enable hiz comparator , */ \ + { 0x44c0, \ + "enbl_pcdac" }, /* Enable peak current dac , */ \ + { 0x44d0, \ + "enbl_pccomp" }, /* Enable peak current comparator , */ \ + { 0x44e0, \ + "enbl_windac" }, /* Enable window dac , */ \ + { 0x44f0, \ + "enbl_powerbst" }, /* Enable line of the powerstage , */ \ + { 0x4507, \ + "ocp_thr" }, /* ocp_thr threshold level for OCP , */ \ + { 0x4580, \ + "bypass_glitchfilter" }, /* Bypass glitchfilter , */ \ + { 0x4590, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0x45a0, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0x45b0, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0x45c0, \ + "bypass_ocp" }, /* Bypass OCP , */ \ + { 0x45d0, \ + "bypass_ocpcounter" }, /* BypassOCPCounter , */ \ + { 0x45e0, \ + "bypass_lost_clk" }, /* Bypasslost_clk detector , */ \ + { 0x45f0, \ + "vpalarm" }, /* vpalarm (uvp ovp handling) , */ \ + { 0x4600, \ + "bypass_gc" }, /* bypass_gc, bypasses the CS gain correction , */ \ + { 0x4610, \ + "cs_gain_control" }, /* gain control by means of MTP or i2c , */ \ + { 0x4627, \ + "cs_gain" }, /* + / - 128 steps in steps of 1/4 % 2's compliment , */ \ + { 0x46a0, \ + "bypass_lp" }, /* bypass Low-Pass filter in temperature sensor , */ \ + { 0x46b0, \ + "bypass_pwmcounter" }, /* bypass_pwmcounter , */ \ + { 0x46c0, \ + "ctrl_cs_negfixed" }, /* does not switch to neg , */ \ + { 0x46d2, \ + "ctrl_cs_neghyst" }, /* switches to neg depending on level , */ \ + { 0x4700, \ + "switch_fb" }, /* switch_fb , */ \ + { 0x4713, \ + "se_hyst" }, /* se_hyst , */ \ + { 0x4754, \ + "se_level" }, /* se_level , */ \ + { 0x47a5, \ + "ktemp" }, /* temperature compensation trimming , */ \ + { 0x4800, \ + "ctrl_negin" }, /* negin , */ \ + { 0x4810, \ + "ctrl_cs_sein" }, /* cs_sein , */ \ + { 0x4820, \ + "ctrl_coincidencecs" }, /* Coincidence current sense , */ \ + { 0x4830, \ + "ctrl_iddqtestbst" }, /* for iddq testing in powerstage of boost convertor , */ \ + { 0x4840, \ + "ctrl_coincidencebst" }, /* Switch protection on to prevent simultaniously switching power stages bst and amp, */ \ + { 0x4851, \ + "clock_sh_sel" }, /* Clock SH selection , */ \ + { 0x4876, \ + "delay_se_neg" }, /* delay of se and neg , */ \ + { 0x48e1, \ + "ctrl_cs_ttrack" }, /* sample & hold track time , */ \ + { 0x4900, \ + "ctrl_bypassclip" }, /* Bypass clip control (function depending on digimux clip_x), */ \ + { 0x4910, \ + "ctrl_bypassclip2" }, /* Bypass clip control (function depending on digimux clip_x), */ \ + { 0x4920, \ + "ctrl_clkgateCFoff" }, /* to disable clock gating in the coolflux , */ \ + { 0x4930, \ + "ctrl_testabst" }, /* testabst , */ \ + { 0x4940, \ + "ctrl_clipfast" }, /* clock switch for battery protection clipper, it switches back to old frequency, */ \ + { 0x4950, \ + "ctrl_cs_8ohm" }, /* 8 ohm mode for current sense (gain mode) , */ \ + { 0x4960, \ + "reserved" }, /* reserved , */ \ + { 0x4974, \ + "delay_clock_sh" }, /* delay_sh, tunes S7H delay , */ \ + { 0x49c0, \ + "inv_clksh" }, /* Invert the sample/hold clock for current sense ADC, */ \ + { 0x49d0, \ + "inv_neg" }, /* Invert neg signal , */ \ + { 0x49e0, \ + "inv_se" }, /* Invert se signal , */ \ + { 0x49f0, \ + "setse" }, /* switches between Single Ende and differentail mode, */ \ + { 0x4a12, \ + "ctrl_adc10_sel" }, /* select the input to convert the 10b ADC , */ \ + { 0x4a60, \ + "ctrl_adc10_reset" }, /* Global asynchronous reset (active HIGH) 10 bit ADC, */ \ + { 0x4a81, \ + "ctrl_adc10_test" }, /* Test mode selection signal 10 bit ADC , */ \ + { 0x4aa0, \ + "ctrl_bypass_lp_vbat" }, /* lp filter in batt sensor , */ \ + { 0x4ae0, \ + "ctrl_dc_offset" }, /* switch offset control on/off, is decimator offset control, */ \ + { 0x4af0, \ + "ctrl_tsense_hibias" }, /* bit to set the biasing in temp sensor to high , */ \ + { 0x4b00, \ + "ctrl_adc13_iset" }, /* Micadc Setting of current consumption. Debug use only, */ \ + { 0x4b14, \ + "ctrl_adc13_gain" }, /* Micadc gain setting (2-compl) , */ \ + { 0x4b61, \ + "ctrl_adc13_slowdel" }, /* Micadc Delay setting for internal clock. Debug use only, */ \ + { 0x4b83, \ + "ctrl_adc13_offset" }, /* Micadc ADC offset setting , */ \ + { 0x4bc0, \ + "ctrl_adc13_bsoinv" }, /* Micadc bit stream output invert mode for test , */ \ + { 0x4bd0, \ + "ctrl_adc13_resonator_enable" }, /* Micadc Give extra SNR with less stability. Debug use only, */ \ + { 0x4be0, \ + "ctrl_testmicadc" }, /* Mux at input of MICADC for test purpose , */ \ + { 0x4c0f, \ + "ctrl_offset" }, /* offset control for ABIST testing , */ \ + { 0x4d05, \ + "ctrl_windac" }, /* for testing direct control windac , */ \ + { 0x4d65, \ + "ctrl_peakcur" }, /* Control peakcur , */ \ + { 0x4dc3, \ + "pwm_dcc_cnt" }, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0x4e04, \ + "ctrl_slopecur" }, /* for testing direct control slopecur , */ \ + { 0x4e53, \ + "ctrl_dem" }, /* dyn element matching control, rest of codes are optional, */ \ + { 0x4e93, \ + "ctrl_demmismatch" }, /* dyn element matching add offset , */ \ + { 0x4ed0, \ + "enbl_pwm_dcc" }, /* to enable direct control of pwm duty cycle , */ \ + { 0x5007, \ + "gain" }, /* gain setting of the gain multiplier gain need to increase with factor 1.41 (3dB), */ \ + { 0x5081, \ + "ctrl_sourceb" }, /* Set OUTB to , */ \ + { 0x50a1, \ + "ctrl_sourcea" }, /* Set OUTA to , */ \ + { 0x50c1, \ + "ctrl_sourcebst" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0x50e1, \ + "ctrl_test_mono" }, /* ABIST mode to add both amplifier halfs as stereo or one amplifier half as mono, */ \ + { 0x5104, \ + "pulselengthbst" }, /* pulselength setting test input for boost converter , */ \ + { 0x5150, \ + "ctrl_bypasslatchbst" }, /* bypass_latch in boost converter , */ \ + { 0x5160, \ + "invertbst" }, /* invert pwmbst test signal , */ \ + { 0x5174, \ + "pulselength" }, /* pulselength setting test input for amplifier , */ \ + { 0x51c0, \ + "ctrl_bypasslatch" }, /* bypass_latch in boost convert , */ \ + { 0x51d0, \ + "invertb" }, /* invert pwmb test signal , */ \ + { 0x51e0, \ + "inverta" }, /* invert pwma test signal , */ \ + { 0x51f0, \ + "ctrl_bypass_ctrlloop" }, /* bypass_ctrlloop bypasses the control loop of the amplifier, */ \ + { 0x5200, \ + "ctrl_test_discrete" }, /* tbd for rdson testing , */ \ + { 0x5210, \ + "ctrl_test_rdsona" }, /* tbd for rdson testing , */ \ + { 0x5220, \ + "ctrl_test_rdsonb" }, /* tbd for rdson testing , */ \ + { 0x5230, \ + "ctrl_test_rdsonbst" }, /* tbd for rdson testing , */ \ + { 0x5240, \ + "ctrl_test_cvia" }, /* tbd for rdson testing , */ \ + { 0x5250, \ + "ctrl_test_cvib" }, /* tbd for rdson testing , */ \ + { 0x5260, \ + "ctrl_test_cvibst" }, /* tbd for rdson testing , */ \ + { 0x5290, \ + "test_bypass_pwmdiscretea" }, /* for testing ( ABIST) , */ \ + { 0x52a0, \ + "test_bypass_pwmdiscreteb" }, /* for testing ( ABIST) , */ \ + { 0x52b0, \ + "ctrl_clipc_forcehigh" }, /* test signal for clipcontrol , */ \ + { 0x52c0, \ + "ctrl_clipc_forcelow" }, /* test signal for clipcontrol , */ \ + { 0x52d0, \ + "ctrl_test_sdelta" }, /* for testing ( ABIST) , */ \ + { 0x52e0, \ + "ctrl_test_swhvp" }, /* for testing ( ABIST) , */ \ + { 0x52f0, \ + "test_gain_reduction" }, /* test gain reduction , */ \ + { 0x5303, \ + "ctrl_digimux_out_test1" }, /* Digimux TEST1 out , */ \ + { 0x5343, \ + "ctrl_digimux_out_test2" }, /* Digimux TEST2 out. output flag_clipa_low depending on cntr_bypassclip setting, */ \ + { 0x5383, \ + "ctrl_digimux_out_data1" }, /* Digimux DATA1 out (output flag_clipb_high depending on cntr_bypassclip setting), */ \ + { 0x53c3, \ + "ctrl_digimux_out_data3" }, /* Digimux DATA3 out (output flag_clipx_x depending on cntr_bypassclip setting), */ \ + { 0x5400, \ + "hs_mode" }, /* hs_mode, high speed mode I2C bus , */ \ + { 0x5412, \ + "test_parametric_io" }, /* test_parametric_io for testing pads , */ \ + { 0x5440, \ + "enbl_ringo" }, /* enbl_ringo, for test purpose to check with ringo , */ \ + { 0x5480, \ + "ctrl_cliplevel" }, /* Clip level , */ \ + { 0x5491, \ + "ctrl_anamux_sel" }, /* anamux selection , */ \ + { 0x54b0, \ + "test_vdddsw_dio" }, /* to overrule the power switches for memory , */ \ + { 0x54c0, \ + "ctrl_bypass_diosw_ovp" }, /* To disable the overvoltage protection of vddd_dio_sw, */ \ + { 0x54d0, \ + "test_vddd_sw" }, /* test vdd sw , */ \ + { 0x54e0, \ + "test_vddd_sw_comp" }, /* test vdd sw comp , */ \ + { 0x550e, \ + "enbl_amp" }, /* enbl_amp for testing to enable all analoge blocks in amplifier, */ \ + { 0x55f0, \ + "fr_fsp" }, /* extr free running clock mode for testing , */ \ + { 0x5600, \ + "use_direct_ctrls" }, /* use_direct_ctrls, to overrule several functions direct for testing, */ \ + { 0x5610, \ + "rst_datapath" }, /* rst_datapath, datapath reset , */ \ + { 0x5620, \ + "rst_cgu" }, /* rst_cgu, cgu reset , */ \ + { 0x5637, \ + "enbl_ref" }, /* for testing to enable all analoge blocks in references, */ \ + { 0x56b0, \ + "enbl_engage" }, /* Enable output stage amplifier , */ \ + { 0x56c0, \ + "use_direct_clk_ctrl" }, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */ \ + { 0x56d0, \ + "use_direct_pll_ctrl" }, /* use_direct_pll_ctrl, to overrule several functions direct for test, */ \ + { 0x56e0, \ + "use_direct_ctrls_2" }, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */ \ + { 0x5707, \ + "ctrl_anamux_out_test1" }, /* Anamux control , */ \ + { 0x5782, \ + "ctrl_zero" }, /* Bandwith control feedbackloop , */ \ + { 0x57b0, \ + "enbl_ldo_stress" }, /* LDO stress function frinch capacitors , */ \ + { 0x57c0, \ + "ctrl_ocptest" }, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */ \ + { 0x57e0, \ + "ctrl_otptest" }, /* otptest, test mode otp amplifier , */ \ + { 0x57f0, \ + "ctrl_reverse" }, /* CTRL revers , */ \ + { 0x5802, \ + "pll_mdec_msb" }, /* most significant bits pll_mdec , */ \ + { 0x5833, \ + "pll_selr" }, /* pll_selr , */ \ + { 0x5874, \ + "pll_selp" }, /* pll_selp , */ \ + { 0x58c3, \ + "pll_seli" }, /* pll_seli , */ \ + { 0x5900, \ + "pll_psel" }, /* pll_psel , */ \ + { 0x5910, \ + "use_direct_pll_psel" }, /* use_direct_pll_psel , */ \ + { 0x5923, \ + "nbck" }, /* NBCK , */ \ + { 0x5960, \ + "auto_nbck" }, /* AUTO_NBCK , */ \ + { 0x5970, \ + "pll_frm" }, /* pll_frm , */ \ + { 0x5980, \ + "pll_directi" }, /* pll_directi , */ \ + { 0x5990, \ + "pll_directo" }, /* pll_directo , */ \ + { 0x59a0, \ + "enbl_PLL" }, /* enbl_PLL , */ \ + { 0x59b0, \ + "sel_clkout" }, /* SEL_CLKOUT , */ \ + { 0x59e0, \ + "fr_lost_clk" }, /* fr_lost_clk , */ \ + { 0x59f0, \ + "pll_bypass" }, /* pll_bypass , */ \ + { 0x5a0f, \ + "tsig_freq" }, /* tsig_freq, internal sinus test generator, frequency control, */ \ + { 0x5b02, \ + "tsig_freq_msb" }, /* select internal sinus test generator, frequency control msb bits, */ \ + { 0x5b30, \ + "inject_tsig" }, /* inject_tsig, control bit to switch to internal sinus test generator, */ \ + { 0x5b44, \ + "ctrl_adc10_prog_sample" }, /* control ADC10 , */ \ + { 0x5c01, \ + "pll_ndec_msb" }, /* most significant bits of pll_ndec , */ \ + { 0x5c2d, \ + "pll_mdec" }, /* bits 13..0 of pll_mdec , */ \ + { 0x5d06, \ + "pll_pdec" }, /* pll_pdec , */ \ + { 0x5d87, \ + "pll_ndec" }, /* bits 7..0 of pll_ndec , */ \ + { 0x5e00, \ + "pdm_ch_sel_reg" }, /* PDM channel selection , */ \ + { 0x5e10, \ + "pdm_iis_rst_reg" }, /* PDM Interface reset , */ \ + { 0x5e20, \ + "clk_src_sel_reg" }, /* WS Source Selection , */ \ + { 0x5e70, \ + "pdm_resync_bypass" }, /* PDM resynchronization bypass , */ \ + { 0x6007, \ + "MTP_key1" }, /* MTP Key1 , */ \ + { 0x6185, \ + "mtp_ecc_tcin" }, /* Mtp_ecc_tcin , */ \ + { 0x6203, \ + "mtp_man_address_in" }, /* address from i2cregs for writing one word single mtp, */ \ + { 0x6260, \ + "mtp_ecc_eeb" }, /* enable code bit generation (active low!) , */ \ + { 0x6270, \ + "mtp_ecc_ecb" }, /* enable correction signal (active low!) , */ \ + { 0x6280, \ + "man_copy_mtp_to_iic" }, /* start copying single word from mtp to i2cregs_mtp , */ \ + { 0x6290, \ + "man_copy_iic_to_mtp" }, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */ \ + { 0x62a0, \ + "auto_copy_mtp_to_iic" }, /* start copying all the data from mtp to i2cregs_mtp, */ \ + { 0x62b0, \ + "auto_copy_iic_to_mtp" }, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */ \ + { 0x62d2, \ + "mtp_speed_mode" }, /* Speed mode , */ \ + { 0x6340, \ + "mtp_dircet_enable" }, /* mtp_direct_enable (key1 protected) , */ \ + { 0x6350, \ + "mtp_direct_wr" }, /* mtp_direct_wr (key1 protected) direct value for mtp pin wr. To be enabled via iic2mtp_mtp_direct_enable, */ \ + { 0x6360, \ + "mtp_direct_rd" }, /* mtp_direct_rd (key1 protected) direct value for mtp pin rd. To be enabled via iic2mtp_mtp_direct_enable, */ \ + { 0x6370, \ + "mtp_direct_rst" }, /* mtp_direct_rst (key1 protected) direct value for mtp pin rst. To be enabled via iic2mtp_mtp_direct_enable, */ \ + { 0x6380, \ + "mtp_direct_ers" }, /* mtp_direct_ers (key1 protected) direct value for mtp pin ers. To be enabled via iic2mtp_mtp_direct_enable, */ \ + { 0x6390, \ + "mtp_direct_prg" }, /* mtp_direct_prg (key1 protected) direct value for mtp pin prg. To be enabled via iic2mtp_mtp_direct_enable, */ \ + { 0x63a0, \ + "mtp_direct_epp" }, /* mtp_direct_epp (key1 protected) direct value for mtp pin epp. To be enabled via iic2mtp_mtp_direct_enable, */ \ + { 0x63b4, \ + "mtp_direct_test" }, /* mtp_direct_test (key1 protected) , */ \ + { 0x640f, \ + "mtp_man_data_in" }, /* single wordt be written to MTP (manual copy) , */ \ + { 0x7000, \ + "cf_rst_dsp" }, /* Reset CoolFlux DSP , */ \ + { 0x7011, \ + "cf_dmem" }, /* Target memory for access , */ \ + { 0x7030, \ + "cf_aif" }, /* Autoincrement-flag for memory-address , */ \ + { 0x7040, \ + "cf_int" }, /* Interrupt CoolFlux DSP , */ \ + { 0x7087, \ + "cf_req" }, /* request for access (8 channels) , */ \ + { 0x710f, \ + "cf_madd" }, /* memory-address to be accessed , */ \ + { 0x720f, \ + "cf_mema" }, /* activate memory access (24- or 32-bits data is written/read to/from memory, */ \ + { 0x7307, \ + "cf_err" }, /* cf error Flags , */ \ + { 0x7387, \ + "cf_ack" }, /* acknowledge of requests (8 channels")" , */ \ + { 0x8000, \ + "calibration_onetime" }, /* Calibration schedule (key2 protected) , */ \ + { 0x8010, \ + "calibr_ron_done" }, /* (key2 protected) calibration of Ron has been executed, */ \ + { 0x8105, \ + "calibr_vout_offset" }, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */ \ + { 0x8163, \ + "calibr_delta_gain" }, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */ \ + { 0x81a5, \ + "calibr_offs_amp" }, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */ \ + { 0x8207, \ + "calibr_gain_cs" }, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */ \ + { 0x8284, \ + "calibr_temp_offset" }, /* temperature offset 2's compliment (key1 protected), */ \ + { 0x82d2, \ + "calibr_temp_gain" }, /* temperature gain 2's compliment (key1 protected) , */ \ + { 0x830f, \ + "calibr_ron" }, /* Ron resistance of coil (key1 protected) , */ \ + { 0x8406, \ + "ctrl_offset_a" }, /* Offset of amplifier level shifter , */ \ + { 0x8486, \ + "ctrl_offset_b" }, /* Offset of amplifier level shifter , */ \ + { 0x850f, \ + "type_bits_HW" }, /* HW Bits , */ \ + { 0x860f, \ + "type_bits1_SW" }, /* MTP-control SW1 , */ \ + { 0x870f, \ + "type_bits2_SW" }, /* MTP-control SW2 , */ \ + { 0x8a0f, \ + "production_data1" }, /* (key1 protected) , */ \ + { 0x8b0f, \ + "production_data2" }, /* (key1 protected) , */ \ + { 0x8c0f, \ + "production_data3" }, /* (key1 protected) , */ \ + { 0x8d0f, \ + "production_data4" }, /* (key1 protected) , */ \ + { 0x8e0f, \ + "production_data5" }, /* (key1 protected) , */ \ + { 0x8f0f, \ + "production_data6" }, /* (key1 protected) , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#endif /* TFA_INC_TFA9891_TFAFIELDNAMES_H_ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9894_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9894_tfafieldnames.h new file mode 100644 index 000000000000..6f1df93a17ba --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9894_tfafieldnames.h @@ -0,0 +1,2102 @@ +/** Filename: tfa9894_tfaFieldnames.h + * This file was generated automatically on 09/06/17 at 14:51:37. + * Source file: TFA9894_N1A1_I2C_RegisterMap.xlsx + */ + +#ifndef _TFA9894_TFAFIELDNAMES_H +#define _TFA9894_TFAFIELDNAMES_H + +#define TFA9894_I2CVERSION 7 + +typedef enum nxpTfa9894BfEnumList { + TFA9894_BF_PWDN = + 0x0000, /*!< Powerdown control */ + TFA9894_BF_I2CR = + 0x0010, /*!< I2C Reset - Auto clear */ + TFA9894_BF_CFE = + 0x0020, /*!< Enable CoolFlux DSP */ + TFA9894_BF_AMPE = + 0x0030, /*!< Enable Amplifier */ + TFA9894_BF_DCA = + 0x0040, /*!< Enable DCDC Boost converter */ + TFA9894_BF_SBSL = + 0x0050, /*!< Coolflux configured */ + TFA9894_BF_AMPC = + 0x0060, /*!< CoolFlux control over amplifier */ + TFA9894_BF_INTP = + 0x0071, /*!< Interrupt config */ + TFA9894_BF_FSSSEL = + 0x0090, /*!< Audio sample reference */ + TFA9894_BF_BYPOCP = + 0x00a0, /*!< Bypass OCP */ + TFA9894_BF_TSTOCP = + 0x00b0, /*!< OCP testing control */ + TFA9894_BF_BSSS = + 0x00c0, /*!< Vbat protection steepness */ + TFA9894_BF_HPFBYP = + 0x00d0, /*!< Bypass High Pass Filter */ + TFA9894_BF_DPSA = + 0x00e0, /*!< Enable DPSA */ + TFA9894_BF_AMPINSEL = + 0x0101, /*!< Amplifier input selection */ + TFA9894_BF_MANSCONF = + 0x0120, /*!< Device I2C settings configured */ + TFA9894_BF_MANCOLD = + 0x0130, /*!< Execute cold start */ + TFA9894_BF_MANROBOD = + 0x0140, /*!< Reaction on BOD */ + TFA9894_BF_BODE = + 0x0150, /*!< Enable BOD (only in direct control mode) */ + TFA9894_BF_BODHYS = + 0x0160, /*!< Enable Hysteresis of BOD */ + TFA9894_BF_BODFILT = + 0x0171, /*!< BOD filter */ + TFA9894_BF_BODTHLVL = + 0x0191, /*!< BOD threshold */ + TFA9894_BF_MUTETO = + 0x01b0, /*!< Time out SB mute sequence */ + TFA9894_BF_MANWDE = + 0x01c0, /*!< Watchdog enable */ + TFA9894_BF_OPENMTP = + 0x01e0, /*!< Control for FAIM protection */ + TFA9894_BF_FAIMVBGOVRRL = + 0x01f0, /*!< Overrule the enabling of VBG for faim erase/write access */ + TFA9894_BF_AUDFS = + 0x0203, /*!< Audio sample rate Fs */ + TFA9894_BF_INPLEV = + 0x0240, /*!< TDM output attenuation */ + TFA9894_BF_FRACTDEL = + 0x0255, /*!< Current sense fractional delay */ + TFA9894_BF_TDMPRES = + 0x02b1, /*!< Control for HW manager */ + TFA9894_BF_AMPOCRT = + 0x02d2, /*!< Amplifier on-off criteria for shutdown */ + TFA9894_BF_REV = + 0x030f, /*!< Revision info */ + TFA9894_BF_REFCKEXT = + 0x0401, /*!< PLL external reference clock */ + TFA9894_BF_REFCKSEL = + 0x0420, /*!< PLL internal reference clock */ + TFA9894_BF_MCLKSEL = + 0x0432, /*!< Master Clock Selection */ + TFA9894_BF_MANAOOSC = + 0x0460, /*!< Internal OSC1M off at PWDN */ + TFA9894_BF_ACKCLDDIS = + 0x0470, /*!< Automatic PLL reference clock selection for cold start */ + TFA9894_BF_SPKSSEN = + 0x0510, /*!< Enable speaker sub-system */ + TFA9894_BF_MTPSSEN = + 0x0520, /*!< Enable FAIM sub-system */ + TFA9894_BF_WDTCLKEN = + 0x0530, /*!< Enable Coolflux watchdog clock */ + TFA9894_BF_VDDS = + 0x1000, /*!< POR */ + TFA9894_BF_PLLS = + 0x1010, /*!< PLL Lock */ + TFA9894_BF_OTDS = + 0x1020, /*!< OTP alarm */ + TFA9894_BF_OVDS = + 0x1030, /*!< OVP alarm */ + TFA9894_BF_UVDS = + 0x1040, /*!< UVP alarm */ + TFA9894_BF_OCDS = + 0x1050, /*!< OCP amplifier (sticky register, clear on read) */ + TFA9894_BF_CLKS = + 0x1060, /*!< Clocks stable */ + TFA9894_BF_MTPB = + 0x1070, /*!< MTP busy */ + TFA9894_BF_NOCLK = + 0x1080, /*!< Lost clock */ + TFA9894_BF_ACS = + 0x1090, /*!< Cold Start */ + TFA9894_BF_WDS = + 0x10a0, /*!< Watchdog */ + TFA9894_BF_SWS = + 0x10b0, /*!< Amplifier engage */ + TFA9894_BF_AMPS = + 0x10c0, /*!< Amplifier enable */ + TFA9894_BF_AREFS = + 0x10d0, /*!< References enable */ + TFA9894_BF_ADCCR = + 0x10e0, /*!< Control ADC */ + TFA9894_BF_BODNOK = + 0x10f0, /*!< BOD Flag - VDD NOT OK */ + TFA9894_BF_DCIL = + 0x1100, /*!< DCDC current limiting */ + TFA9894_BF_DCDCA = + 0x1110, /*!< DCDC active (sticky register, clear on read) */ + TFA9894_BF_DCOCPOK = + 0x1120, /*!< DCDC OCP nmos (sticky register, clear on read) */ + TFA9894_BF_DCHVBAT = + 0x1140, /*!< DCDC level 1x */ + TFA9894_BF_DCH114 = + 0x1150, /*!< DCDC level 1.14x */ + TFA9894_BF_DCH107 = + 0x1160, /*!< DCDC level 1.07x */ + TFA9894_BF_SPKS = + 0x1170, /*!< Speaker status */ + TFA9894_BF_CLKOOR = + 0x1180, /*!< External clock status */ + TFA9894_BF_MANALARM = + 0x1190, /*!< Alarm state */ + TFA9894_BF_TDMERR = + 0x11a0, /*!< TDM error */ + TFA9894_BF_TDMLUTER = + 0x11b0, /*!< TDM lookup table error */ + TFA9894_BF_OCPOAP = + 0x1200, /*!< OCPOK pmos A */ + TFA9894_BF_OCPOAN = + 0x1210, /*!< OCPOK nmos A */ + TFA9894_BF_OCPOBP = + 0x1220, /*!< OCPOK pmos B */ + TFA9894_BF_OCPOBN = + 0x1230, /*!< OCPOK nmos B */ + TFA9894_BF_CLIPS = + 0x1240, /*!< Amplifier clipping */ + TFA9894_BF_MANMUTE = + 0x1250, /*!< Audio mute sequence */ + TFA9894_BF_MANOPER = + 0x1260, /*!< Device in Operating state */ + TFA9894_BF_LP1 = + 0x1270, /*!< Low power MODE1 detection */ + TFA9894_BF_LA = + 0x1280, /*!< Low amplitude detection */ + TFA9894_BF_VDDPH = + 0x1290, /*!< VDDP greater than VBAT flag */ + TFA9894_BF_TDMSTAT = + 0x1402, /*!< TDM Status bits */ + TFA9894_BF_MANSTATE = + 0x1433, /*!< Device Manager status */ + TFA9894_BF_DCMODE = + 0x14b1, /*!< DCDC mode status bits */ + TFA9894_BF_BATS = + 0x1509, /*!< Battery voltage (V) */ + TFA9894_BF_TEMPS = + 0x1608, /*!< IC Temperature (C) */ + TFA9894_BF_VDDPS = + 0x1709, /*!< IC VDDP voltage (1023*VDDP/13V) */ + TFA9894_BF_TDME = + 0x2000, /*!< Enable interface */ + TFA9894_BF_TDMSPKE = + 0x2010, /*!< Control audio tdm channel in sink0 */ + TFA9894_BF_TDMDCE = + 0x2020, /*!< Control audio tdm channel in sink1 */ + TFA9894_BF_TDMCSE = + 0x2030, /*!< Source 0 enable */ + TFA9894_BF_TDMVSE = + 0x2040, /*!< Source 1 enable */ + TFA9894_BF_TDMCFE = + 0x2050, /*!< Source 2 enable */ + TFA9894_BF_TDMCF2E = + 0x2060, /*!< Source 3 enable */ + TFA9894_BF_TDMCLINV = + 0x2070, /*!< Reception data to BCK clock */ + TFA9894_BF_TDMFSPOL = + 0x2080, /*!< FS polarity */ + TFA9894_BF_TDMDEL = + 0x2090, /*!< Data delay to FS */ + TFA9894_BF_TDMADJ = + 0x20a0, /*!< Data adjustment */ + TFA9894_BF_TDMOOMP = + 0x20b1, /*!< Received audio compression */ + TFA9894_BF_TDMNBCK = + 0x2103, /*!< TDM NBCK - Bit clock to FS ratio */ + TFA9894_BF_TDMFSLN = + 0x2143, /*!< FS length (master mode only) */ + TFA9894_BF_TDMSLOTS = + 0x2183, /*!< N-slots in Frame */ + TFA9894_BF_TDMTXDFO = + 0x21c1, /*!< Format unused bits */ + TFA9894_BF_TDMTXUS0 = + 0x21e1, /*!< Format unused slots DATAO */ + TFA9894_BF_TDMSLLN = + 0x2204, /*!< N-bits in slot */ + TFA9894_BF_TDMBRMG = + 0x2254, /*!< N-bits remaining */ + TFA9894_BF_TDMSSIZE = + 0x22a4, /*!< Sample size per slot */ + TFA9894_BF_TDMSPKS = + 0x2303, /*!< TDM slot for sink 0 */ + TFA9894_BF_TDMDCS = + 0x2343, /*!< TDM slot for sink 1 */ + TFA9894_BF_TDMCFSEL = + 0x2381, /*!< TDM Source 2 data selection */ + TFA9894_BF_TDMCF2SEL = + 0x23a1, /*!< TDM Source 3 data selection */ + TFA9894_BF_TDMCSS = + 0x2403, /*!< Slot Position of source 0 data */ + TFA9894_BF_TDMVSS = + 0x2443, /*!< Slot Position of source 1 data */ + TFA9894_BF_TDMCFS = + 0x2483, /*!< Slot Position of source 2 data */ + TFA9894_BF_TDMCF2S = + 0x24c3, /*!< Slot Position of source 3 data */ + TFA9894_BF_ISTVDDS = + 0x4000, /*!< Status POR */ + TFA9894_BF_ISTBSTOC = + 0x4010, /*!< Status DCDC OCP */ + TFA9894_BF_ISTOTDS = + 0x4020, /*!< Status OTP alarm */ + TFA9894_BF_ISTOCPR = + 0x4030, /*!< Status OCP alarm */ + TFA9894_BF_ISTUVDS = + 0x4040, /*!< Status UVP alarm */ + TFA9894_BF_ISTMANALARM = + 0x4050, /*!< Status manager alarm state */ + TFA9894_BF_ISTTDMER = + 0x4060, /*!< Status TDM error */ + TFA9894_BF_ISTNOCLK = + 0x4070, /*!< Status lost clock */ + TFA9894_BF_ISTCFMER = + 0x4080, /*!< Status cfma error */ + TFA9894_BF_ISTCFMAC = + 0x4090, /*!< Status cfma ack */ + TFA9894_BF_ISTSPKS = + 0x40a0, /*!< Status coolflux speaker error */ + TFA9894_BF_ISTACS = + 0x40b0, /*!< Status cold started */ + TFA9894_BF_ISTWDS = + 0x40c0, /*!< Status watchdog reset */ + TFA9894_BF_ISTBODNOK = + 0x40d0, /*!< Status brown out detect */ + TFA9894_BF_ISTLP1 = + 0x40e0, /*!< Status low power mode1 detect */ + TFA9894_BF_ISTCLKOOR = + 0x40f0, /*!< Status clock out of range */ + TFA9894_BF_ICLVDDS = + 0x4400, /*!< Clear POR */ + TFA9894_BF_ICLBSTOC = + 0x4410, /*!< Clear DCDC OCP */ + TFA9894_BF_ICLOTDS = + 0x4420, /*!< Clear OTP alarm */ + TFA9894_BF_ICLOCPR = + 0x4430, /*!< Clear OCP alarm */ + TFA9894_BF_ICLUVDS = + 0x4440, /*!< Clear UVP alarm */ + TFA9894_BF_ICLMANALARM = + 0x4450, /*!< Clear manager alarm state */ + TFA9894_BF_ICLTDMER = + 0x4460, /*!< Clear TDM error */ + TFA9894_BF_ICLNOCLK = + 0x4470, /*!< Clear lost clk */ + TFA9894_BF_ICLCFMER = + 0x4480, /*!< Clear cfma err */ + TFA9894_BF_ICLCFMAC = + 0x4490, /*!< Clear cfma ack */ + TFA9894_BF_ICLSPKS = + 0x44a0, /*!< Clear coolflux speaker error */ + TFA9894_BF_ICLACS = + 0x44b0, /*!< Clear cold started */ + TFA9894_BF_ICLWDS = + 0x44c0, /*!< Clear watchdog reset */ + TFA9894_BF_ICLBODNOK = + 0x44d0, /*!< Clear brown out detect */ + TFA9894_BF_ICLLP1 = + 0x44e0, /*!< Clear low power mode1 detect */ + TFA9894_BF_ICLCLKOOR = + 0x44f0, /*!< Clear clock out of range */ + TFA9894_BF_IEVDDS = + 0x4800, /*!< Enable POR */ + TFA9894_BF_IEBSTOC = + 0x4810, /*!< Enable DCDC OCP */ + TFA9894_BF_IEOTDS = + 0x4820, /*!< Enable OTP alarm */ + TFA9894_BF_IEOCPR = + 0x4830, /*!< Enable OCP alarm */ + TFA9894_BF_IEUVDS = + 0x4840, /*!< Enable UVP alarm */ + TFA9894_BF_IEMANALARM = + 0x4850, /*!< Enable Manager Alarm state */ + TFA9894_BF_IETDMER = + 0x4860, /*!< Enable TDM error */ + TFA9894_BF_IENOCLK = + 0x4870, /*!< Enable lost clk */ + TFA9894_BF_IECFMER = + 0x4880, /*!< Enable cfma err */ + TFA9894_BF_IECFMAC = + 0x4890, /*!< Enable cfma ack */ + TFA9894_BF_IESPKS = + 0x48a0, /*!< Enable coolflux speaker error */ + TFA9894_BF_IEACS = + 0x48b0, /*!< Enable cold started */ + TFA9894_BF_IEWDS = + 0x48c0, /*!< Enable watchdog reset */ + TFA9894_BF_IEBODNOK = + 0x48d0, /*!< Enable brown out detect */ + TFA9894_BF_IELP1 = + 0x48e0, /*!< Enable low power mode1 detect */ + TFA9894_BF_IECLKOOR = + 0x48f0, /*!< Enable clock out of range */ + TFA9894_BF_IPOVDDS = + 0x4c00, /*!< Polarity POR */ + TFA9894_BF_IPOBSTOC = + 0x4c10, /*!< Polarity DCDC OCP */ + TFA9894_BF_IPOOTDS = + 0x4c20, /*!< Polarity OTP alarm */ + TFA9894_BF_IPOOCPR = + 0x4c30, /*!< Polarity ocp alarm */ + TFA9894_BF_IPOUVDS = + 0x4c40, /*!< Polarity UVP alarm */ + TFA9894_BF_IPOMANALARM = + 0x4c50, /*!< Polarity manager alarm state */ + TFA9894_BF_IPOTDMER = + 0x4c60, /*!< Polarity TDM error */ + TFA9894_BF_IPONOCLK = + 0x4c70, /*!< Polarity lost clk */ + TFA9894_BF_IPOCFMER = + 0x4c80, /*!< Polarity cfma err */ + TFA9894_BF_IPOCFMAC = + 0x4c90, /*!< Polarity cfma ack */ + TFA9894_BF_IPOSPKS = + 0x4ca0, /*!< Polarity coolflux speaker error */ + TFA9894_BF_IPOACS = + 0x4cb0, /*!< Polarity cold started */ + TFA9894_BF_IPOWDS = + 0x4cc0, /*!< Polarity watchdog reset */ + TFA9894_BF_IPOBODNOK = + 0x4cd0, /*!< Polarity brown out detect */ + TFA9894_BF_IPOLP1 = + 0x4ce0, /*!< Polarity low power mode1 detect */ + TFA9894_BF_IPOCLKOOR = + 0x4cf0, /*!< Polarity clock out of range */ + TFA9894_BF_BSSCR = + 0x5001, /*!< Battery safeguard attack time */ + TFA9894_BF_BSST = + 0x5023, /*!< Battery safeguard threshold voltage level */ + TFA9894_BF_BSSRL = + 0x5061, /*!< Battery safeguard maximum reduction */ + TFA9894_BF_BSSRR = + 0x5082, /*!< Battery safeguard release time */ + TFA9894_BF_BSSHY = + 0x50b1, /*!< Battery Safeguard hysteresis */ + TFA9894_BF_BSSR = + 0x50e0, /*!< Battery voltage read out */ + TFA9894_BF_BSSBY = + 0x50f0, /*!< Bypass HW clipper */ + TFA9894_BF_CFSM = + 0x5130, /*!< Coolflux firmware soft mute control */ + TFA9894_BF_VOL = + 0x5187, /*!< CF firmware volume control */ + TFA9894_BF_CLIPCTRL = + 0x5202, /*!< Clip control setting */ + TFA9894_BF_SLOPEE = + 0x5230, /*!< Enables slope control */ + TFA9894_BF_SLOPESET = + 0x5240, /*!< Slope speed setting (binary coded) */ + TFA9894_BF_AMPGAIN = + 0x5287, /*!< Amplifier gain */ + TFA9894_BF_TDMDCG = + 0x5703, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */ + TFA9894_BF_TDMSPKG = + 0x5743, /*!< Total gain depending on INPLEV setting (channel 0) */ + TFA9894_BF_DCINSEL = + 0x5781, /*!< VAMP_OUT2 input selection */ + TFA9894_BF_LNMODE = + 0x5881, /*!< Low noise gain mode control */ + TFA9894_BF_LPM1MODE = + 0x5ac1, /*!< Low power mode control */ + TFA9894_BF_TDMSRCMAP = + 0x5d02, /*!< TDM source mapping */ + TFA9894_BF_TDMSRCAS = + 0x5d31, /*!< Sensed value A */ + TFA9894_BF_TDMSRCBS = + 0x5d51, /*!< Sensed value B */ + TFA9894_BF_TDMSRCACLIP = + 0x5d71, /*!< Clip information (analog /digital) for source0 */ + TFA9894_BF_TDMSRCBCLIP = + 0x5d91, /*!< Clip information (analog /digital) for source1 */ + TFA9894_BF_DELCURCOMP = + 0x6102, /*!< Delay to allign compensation signal with current sense signal */ + TFA9894_BF_SIGCURCOMP = + 0x6130, /*!< Polarity of compensation for current sense */ + TFA9894_BF_ENCURCOMP = + 0x6140, /*!< Enable current sense compensation */ + TFA9894_BF_LVLCLPPWM = + 0x6152, /*!< Set the amount of pwm pulse that may be skipped before clip-flag is triggered */ + TFA9894_BF_DCVOF = + 0x7005, /*!< First Boost Voltage Level */ + TFA9894_BF_DCVOS = + 0x7065, /*!< Second Boost Voltage Level */ + TFA9894_BF_DCMCC = + 0x70c3, /*!< Max Coil Current */ + TFA9894_BF_DCCV = + 0x7101, /*!< Slope compensation current, represents LxF (inductance x frequency) value */ + TFA9894_BF_DCIE = + 0x7120, /*!< Adaptive boost mode */ + TFA9894_BF_DCSR = + 0x7130, /*!< Soft ramp up/down */ + TFA9894_BF_DCDIS = + 0x7140, /*!< DCDC on/off */ + TFA9894_BF_DCPWM = + 0x7150, /*!< DCDC PWM only mode */ + TFA9894_BF_DCTRACK = + 0x7160, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */ + TFA9894_BF_DCTRIP = + 0x7204, /*!< 1st adaptive boost trip levels, effective only when DCIE is set to 1 */ + TFA9894_BF_DCTRIP2 = + 0x7254, /*!< 2nd adaptive boost trip levels, effective only when DCIE is set to 1 */ + TFA9894_BF_DCTRIPT = + 0x72a4, /*!< Track adaptive boost trip levels, effective only when boost_intelligent is set to 1 */ + TFA9894_BF_DCTRIPHYSTE = + 0x72f0, /*!< Enable hysteresis on booster trip levels */ + TFA9894_BF_DCHOLD = + 0x7304, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */ + TFA9894_BF_RST = + 0x9000, /*!< Reset for Coolflux DSP */ + TFA9894_BF_DMEM = + 0x9011, /*!< Target memory for CFMA using I2C interface */ + TFA9894_BF_AIF = + 0x9030, /*!< Auto increment */ + TFA9894_BF_CFINT = + 0x9040, /*!< Coolflux Interrupt - auto clear */ + TFA9894_BF_CFCGATE = + 0x9050, /*!< Coolflux clock gating disabling control */ + TFA9894_BF_REQCMD = + 0x9080, /*!< Firmware event request rpc command */ + TFA9894_BF_REQRST = + 0x9090, /*!< Firmware event request reset restart */ + TFA9894_BF_REQMIPS = + 0x90a0, /*!< Firmware event request short on mips */ + TFA9894_BF_REQMUTED = + 0x90b0, /*!< Firmware event request mute sequence ready */ + TFA9894_BF_REQVOL = + 0x90c0, /*!< Firmware event request volume ready */ + TFA9894_BF_REQDMG = + 0x90d0, /*!< Firmware event request speaker damage detected */ + TFA9894_BF_REQCAL = + 0x90e0, /*!< Firmware event request calibration completed */ + TFA9894_BF_REQRSV = + 0x90f0, /*!< Firmware event request reserved */ + TFA9894_BF_MADD = + 0x910f, /*!< CF memory address */ + TFA9894_BF_MEMA = + 0x920f, /*!< Activate memory access */ + TFA9894_BF_ERR = + 0x9307, /*!< CF error flags */ + TFA9894_BF_ACKCMD = + 0x9380, /*!< Firmware event acknowledge rpc command */ + TFA9894_BF_ACKRST = + 0x9390, /*!< Firmware event acknowledge reset restart */ + TFA9894_BF_ACKMIPS = + 0x93a0, /*!< Firmware event acknowledge short on mips */ + TFA9894_BF_ACKMUTED = + 0x93b0, /*!< Firmware event acknowledge mute sequence ready */ + TFA9894_BF_ACKVOL = + 0x93c0, /*!< Firmware event acknowledge volume ready */ + TFA9894_BF_ACKDMG = + 0x93d0, /*!< Firmware event acknowledge speaker damage detected */ + TFA9894_BF_ACKCAL = + 0x93e0, /*!< Firmware event acknowledge calibration completed */ + TFA9894_BF_ACKRSV = + 0x93f0, /*!< Firmware event acknowledge reserved */ + TFA9894_BF_MTPK = + 0xa107, /*!< KEY2 to access KEY2 protected registers, customer key */ + TFA9894_BF_KEY1LOCKED = + 0xa200, /*!< Indicates KEY1 is locked */ + TFA9894_BF_KEY2LOCKED = + 0xa210, /*!< Indicates KEY2 is locked */ + TFA9894_BF_CMTPI = + 0xa350, /*!< Start copying all the data from mtp to I2C mtp registers - auto clear */ + TFA9894_BF_CIMTP = + 0xa360, /*!< Start copying data from I2C mtp registers to mtp - auto clear */ + TFA9894_BF_MTPRDMSB = + 0xa50f, /*!< MSB word of MTP manual read data */ + TFA9894_BF_MTPRDLSB = + 0xa60f, /*!< LSB word of MTP manual read data */ + TFA9894_BF_EXTTS = + 0xb108, /*!< External temperature (C) */ + TFA9894_BF_TROS = + 0xb190, /*!< Select temp Speaker calibration */ + TFA9894_BF_SWPROFIL = + 0xe00f, /*!< Software profile data */ + TFA9894_BF_SWVSTEP = + 0xe10f, /*!< Software vstep information */ + TFA9894_BF_MTPOTC = + 0xf000, /*!< Calibration schedule */ + TFA9894_BF_MTPEX = + 0xf010, /*!< Calibration Ron executed */ + TFA9894_BF_DCMCCAPI = + 0xf020, /*!< Calibration current limit DCDC */ + TFA9894_BF_DCMCCSB = + 0xf030, /*!< Sign bit for delta calibration current limit DCDC */ + TFA9894_BF_USERDEF = + 0xf042, /*!< Calibration delta current limit DCDC */ + TFA9894_BF_CUSTINFO = + 0xf078, /*!< Reserved space for allowing customer to store speaker information */ + TFA9894_BF_R25C = + 0xf50f, /*!< Ron resistance of speaker coil */ +} nxpTfa9894BfEnumList_t; +#define TFA9894_NAMETABLE \ + static tfaBfName_t Tfa9894DatasheetNames[] = { \ + { 0x0, \ + "PWDN" }, /* Powerdown control , */ \ + { 0x10, \ + "I2CR" }, /* I2C Reset - Auto clear , */ \ + { 0x20, \ + "CFE" }, /* Enable CoolFlux DSP , */ \ + { 0x30, \ + "AMPE" }, /* Enable Amplifier , */ \ + { 0x40, \ + "DCA" }, /* Enable DCDC Boost converter , */ \ + { 0x50, \ + "SBSL" }, /* Coolflux configured , */ \ + { 0x60, \ + "AMPC" }, /* CoolFlux control over amplifier , */ \ + { 0x71, \ + "INTP" }, /* Interrupt config , */ \ + { 0x90, \ + "FSSSEL" }, /* Audio sample reference , */ \ + { 0xa0, \ + "BYPOCP" }, /* Bypass OCP , */ \ + { 0xb0, \ + "TSTOCP" }, /* OCP testing control , */ \ + { 0xc0, \ + "BSSS" }, /* Vbat protection steepness , */ \ + { 0xd0, \ + "HPFBYP" }, /* Bypass High Pass Filter , */ \ + { 0xe0, \ + "DPSA" }, /* Enable DPSA , */ \ + { 0x101, \ + "AMPINSEL" }, /* Amplifier input selection , */ \ + { 0x120, \ + "MANSCONF" }, /* Device I2C settings configured , */ \ + { 0x130, \ + "MANCOLD" }, /* Execute cold start , */ \ + { 0x140, \ + "MANROBOD" }, /* Reaction on BOD , */ \ + { 0x150, \ + "BODE" }, /* Enable BOD (only in direct control mode) , */ \ + { 0x160, \ + "BODHYS" }, /* Enable Hysteresis of BOD , */ \ + { 0x171, \ + "BODFILT" }, /* BOD filter , */ \ + { 0x191, \ + "BODTHLVL" }, /* BOD threshold , */ \ + { 0x1b0, \ + "MUTETO" }, /* Time out SB mute sequence , */ \ + { 0x1c0, \ + "MANWDE" }, /* Watchdog enable , */ \ + { 0x1e0, \ + "OPENMTP" }, /* Control for FAIM protection , */ \ + { 0x1f0, \ + "FAIMVBGOVRRL" }, /* Overrule the enabling of VBG for faim erase/write access, */ \ + { 0x203, \ + "AUDFS" }, /* Audio sample rate Fs , */ \ + { 0x240, \ + "INPLEV" }, /* TDM output attenuation , */ \ + { 0x255, \ + "FRACTDEL" }, /* Current sense fractional delay , */ \ + { 0x2b1, \ + "TDMPRES" }, /* Control for HW manager , */ \ + { 0x2d2, \ + "AMPOCRT" }, /* Amplifier on-off criteria for shutdown , */ \ + { 0x30f, \ + "REV" }, /* Revision info , */ \ + { 0x401, \ + "REFCKEXT" }, /* PLL external reference clock , */ \ + { 0x420, \ + "REFCKSEL" }, /* PLL internal reference clock , */ \ + { 0x432, \ + "MCLKSEL" }, /* Master Clock Selection , */ \ + { 0x460, \ + "MANAOOSC" }, /* Internal OSC1M off at PWDN , */ \ + { 0x470, \ + "ACKCLDDIS" }, /* Automatic PLL reference clock selection for cold start, */ \ + { 0x510, \ + "SPKSSEN" }, /* Enable speaker sub-system , */ \ + { 0x520, \ + "MTPSSEN" }, /* Enable FAIM sub-system , */ \ + { 0x530, \ + "WDTCLKEN" }, /* Enable Coolflux watchdog clock , */ \ + { 0x1000, \ + "VDDS" }, /* POR , */ \ + { 0x1010, \ + "PLLS" }, /* PLL Lock , */ \ + { 0x1020, \ + "OTDS" }, /* OTP alarm , */ \ + { 0x1030, \ + "OVDS" }, /* OVP alarm , */ \ + { 0x1040, \ + "UVDS" }, /* UVP alarm , */ \ + { 0x1050, \ + "OCDS" }, /* OCP amplifier (sticky register, clear on read) , */ \ + { 0x1060, \ + "CLKS" }, /* Clocks stable , */ \ + { 0x1070, \ + "MTPB" }, /* MTP busy , */ \ + { 0x1080, \ + "NOCLK" }, /* Lost clock , */ \ + { 0x1090, \ + "ACS" }, /* Cold Start , */ \ + { 0x10a0, \ + "WDS" }, /* Watchdog , */ \ + { 0x10b0, \ + "SWS" }, /* Amplifier engage , */ \ + { 0x10c0, \ + "AMPS" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "AREFS" }, /* References enable , */ \ + { 0x10e0, \ + "ADCCR" }, /* Control ADC , */ \ + { 0x10f0, \ + "BODNOK" }, /* BOD Flag - VDD NOT OK , */ \ + { 0x1100, \ + "DCIL" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "DCDCA" }, /* DCDC active (sticky register, clear on read) , */ \ + { 0x1120, \ + "DCOCPOK" }, /* DCDC OCP nmos (sticky register, clear on read) , */ \ + { 0x1140, \ + "DCHVBAT" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "DCH114" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "DCH107" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "SPKS" }, /* Speaker status , */ \ + { 0x1180, \ + "CLKOOR" }, /* External clock status , */ \ + { 0x1190, \ + "MANALARM" }, /* Alarm state , */ \ + { 0x11a0, \ + "TDMERR" }, /* TDM error , */ \ + { 0x11b0, \ + "TDMLUTER" }, /* TDM lookup table error , */ \ + { 0x1200, \ + "OCPOAP" }, /* OCPOK pmos A , */ \ + { 0x1210, \ + "OCPOAN" }, /* OCPOK nmos A , */ \ + { 0x1220, \ + "OCPOBP" }, /* OCPOK pmos B , */ \ + { 0x1230, \ + "OCPOBN" }, /* OCPOK nmos B , */ \ + { 0x1240, \ + "CLIPS" }, /* Amplifier clipping , */ \ + { 0x1250, \ + "MANMUTE" }, /* Audio mute sequence , */ \ + { 0x1260, \ + "MANOPER" }, /* Device in Operating state , */ \ + { 0x1270, \ + "LP1" }, /* Low power MODE1 detection , */ \ + { 0x1280, \ + "LA" }, /* Low amplitude detection , */ \ + { 0x1290, \ + "VDDPH" }, /* VDDP greater than VBAT flag , */ \ + { 0x1402, \ + "TDMSTAT" }, /* TDM Status bits , */ \ + { 0x1433, \ + "MANSTATE" }, /* Device Manager status , */ \ + { 0x14b1, \ + "DCMODE" }, /* DCDC mode status bits , */ \ + { 0x1509, \ + "BATS" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "TEMPS" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "VDDPS" }, /* IC VDDP voltage (1023*VDDP/13V) , */ \ + { 0x2000, \ + "TDME" }, /* Enable interface , */ \ + { 0x2010, \ + "TDMSPKE" }, /* Control audio tdm channel in sink0 , */ \ + { 0x2020, \ + "TDMDCE" }, /* Control audio tdm channel in sink1 , */ \ + { 0x2030, \ + "TDMCSE" }, /* Source 0 enable , */ \ + { 0x2040, \ + "TDMVSE" }, /* Source 1 enable , */ \ + { 0x2050, \ + "TDMCFE" }, /* Source 2 enable , */ \ + { 0x2060, \ + "TDMCF2E" }, /* Source 3 enable , */ \ + { 0x2070, \ + "TDMCLINV" }, /* Reception data to BCK clock , */ \ + { 0x2080, \ + "TDMFSPOL" }, /* FS polarity , */ \ + { 0x2090, \ + "TDMDEL" }, /* Data delay to FS , */ \ + { 0x20a0, \ + "TDMADJ" }, /* Data adjustment , */ \ + { 0x20b1, \ + "TDMOOMP" }, /* Received audio compression , */ \ + { 0x2103, \ + "TDMNBCK" }, /* TDM NBCK - Bit clock to FS ratio , */ \ + { 0x2143, \ + "TDMFSLN" }, /* FS length (master mode only) , */ \ + { 0x2183, \ + "TDMSLOTS" }, /* N-slots in Frame , */ \ + { 0x21c1, \ + "TDMTXDFO" }, /* Format unused bits , */ \ + { 0x21e1, \ + "TDMTXUS0" }, /* Format unused slots DATAO , */ \ + { 0x2204, \ + "TDMSLLN" }, /* N-bits in slot , */ \ + { 0x2254, \ + "TDMBRMG" }, /* N-bits remaining , */ \ + { 0x22a4, \ + "TDMSSIZE" }, /* Sample size per slot , */ \ + { 0x2303, \ + "TDMSPKS" }, /* TDM slot for sink 0 , */ \ + { 0x2343, \ + "TDMDCS" }, /* TDM slot for sink 1 , */ \ + { 0x2381, \ + "TDMCFSEL" }, /* TDM Source 2 data selection , */ \ + { 0x23a1, \ + "TDMCF2SEL" }, /* TDM Source 3 data selection , */ \ + { 0x2403, \ + "TDMCSS" }, /* Slot Position of source 0 data , */ \ + { 0x2443, \ + "TDMVSS" }, /* Slot Position of source 1 data , */ \ + { 0x2483, \ + "TDMCFS" }, /* Slot Position of source 2 data , */ \ + { 0x24c3, \ + "TDMCF2S" }, /* Slot Position of source 3 data , */ \ + { 0x4000, \ + "ISTVDDS" }, /* Status POR , */ \ + { 0x4010, \ + "ISTBSTOC" }, /* Status DCDC OCP , */ \ + { 0x4020, \ + "ISTOTDS" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "ISTOCPR" }, /* Status OCP alarm , */ \ + { 0x4040, \ + "ISTUVDS" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "ISTMANALARM" }, /* Status manager alarm state , */ \ + { 0x4060, \ + "ISTTDMER" }, /* Status TDM error , */ \ + { 0x4070, \ + "ISTNOCLK" }, /* Status lost clock , */ \ + { 0x4080, \ + "ISTCFMER" }, /* Status cfma error , */ \ + { 0x4090, \ + "ISTCFMAC" }, /* Status cfma ack , */ \ + { 0x40a0, \ + "ISTSPKS" }, /* Status coolflux speaker error , */ \ + { 0x40b0, \ + "ISTACS" }, /* Status cold started , */ \ + { 0x40c0, \ + "ISTWDS" }, /* Status watchdog reset , */ \ + { 0x40d0, \ + "ISTBODNOK" }, /* Status brown out detect , */ \ + { 0x40e0, \ + "ISTLP1" }, /* Status low power mode1 detect , */ \ + { 0x40f0, \ + "ISTCLKOOR" }, /* Status clock out of range , */ \ + { 0x4400, \ + "ICLVDDS" }, /* Clear POR , */ \ + { 0x4410, \ + "ICLBSTOC" }, /* Clear DCDC OCP , */ \ + { 0x4420, \ + "ICLOTDS" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "ICLOCPR" }, /* Clear OCP alarm , */ \ + { 0x4440, \ + "ICLUVDS" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "ICLMANALARM" }, /* Clear manager alarm state , */ \ + { 0x4460, \ + "ICLTDMER" }, /* Clear TDM error , */ \ + { 0x4470, \ + "ICLNOCLK" }, /* Clear lost clk , */ \ + { 0x4480, \ + "ICLCFMER" }, /* Clear cfma err , */ \ + { 0x4490, \ + "ICLCFMAC" }, /* Clear cfma ack , */ \ + { 0x44a0, \ + "ICLSPKS" }, /* Clear coolflux speaker error , */ \ + { 0x44b0, \ + "ICLACS" }, /* Clear cold started , */ \ + { 0x44c0, \ + "ICLWDS" }, /* Clear watchdog reset , */ \ + { 0x44d0, \ + "ICLBODNOK" }, /* Clear brown out detect , */ \ + { 0x44e0, \ + "ICLLP1" }, /* Clear low power mode1 detect , */ \ + { 0x44f0, \ + "ICLCLKOOR" }, /* Clear clock out of range , */ \ + { 0x4800, \ + "IEVDDS" }, /* Enable POR , */ \ + { 0x4810, \ + "IEBSTOC" }, /* Enable DCDC OCP , */ \ + { 0x4820, \ + "IEOTDS" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "IEOCPR" }, /* Enable OCP alarm , */ \ + { 0x4840, \ + "IEUVDS" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "IEMANALARM" }, /* Enable Manager Alarm state , */ \ + { 0x4860, \ + "IETDMER" }, /* Enable TDM error , */ \ + { 0x4870, \ + "IENOCLK" }, /* Enable lost clk , */ \ + { 0x4880, \ + "IECFMER" }, /* Enable cfma err , */ \ + { 0x4890, \ + "IECFMAC" }, /* Enable cfma ack , */ \ + { 0x48a0, \ + "IESPKS" }, /* Enable coolflux speaker error , */ \ + { 0x48b0, \ + "IEACS" }, /* Enable cold started , */ \ + { 0x48c0, \ + "IEWDS" }, /* Enable watchdog reset , */ \ + { 0x48d0, \ + "IEBODNOK" }, /* Enable brown out detect , */ \ + { 0x48e0, \ + "IELP1" }, /* Enable low power mode1 detect , */ \ + { 0x48f0, \ + "IECLKOOR" }, /* Enable clock out of range , */ \ + { 0x4c00, \ + "IPOVDDS" }, /* Polarity POR , */ \ + { 0x4c10, \ + "IPOBSTOC" }, /* Polarity DCDC OCP , */ \ + { 0x4c20, \ + "IPOOTDS" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "IPOOCPR" }, /* Polarity ocp alarm , */ \ + { 0x4c40, \ + "IPOUVDS" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "IPOMANALARM" }, /* Polarity manager alarm state , */ \ + { 0x4c60, \ + "IPOTDMER" }, /* Polarity TDM error , */ \ + { 0x4c70, \ + "IPONOCLK" }, /* Polarity lost clk , */ \ + { 0x4c80, \ + "IPOCFMER" }, /* Polarity cfma err , */ \ + { 0x4c90, \ + "IPOCFMAC" }, /* Polarity cfma ack , */ \ + { 0x4ca0, \ + "IPOSPKS" }, /* Polarity coolflux speaker error , */ \ + { 0x4cb0, \ + "IPOACS" }, /* Polarity cold started , */ \ + { 0x4cc0, \ + "IPOWDS" }, /* Polarity watchdog reset , */ \ + { 0x4cd0, \ + "IPOBODNOK" }, /* Polarity brown out detect , */ \ + { 0x4ce0, \ + "IPOLP1" }, /* Polarity low power mode1 detect , */ \ + { 0x4cf0, \ + "IPOCLKOOR" }, /* Polarity clock out of range , */ \ + { 0x5001, \ + "BSSCR" }, /* Battery safeguard attack time , */ \ + { 0x5023, \ + "BSST" }, /* Battery safeguard threshold voltage level , */ \ + { 0x5061, \ + "BSSRL" }, /* Battery safeguard maximum reduction , */ \ + { 0x5082, \ + "BSSRR" }, /* Battery safeguard release time , */ \ + { 0x50b1, \ + "BSSHY" }, /* Battery Safeguard hysteresis , */ \ + { 0x50e0, \ + "BSSR" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "BSSBY" }, /* Bypass HW clipper , */ \ + { 0x5130, \ + "CFSM" }, /* Coolflux firmware soft mute control , */ \ + { 0x5187, \ + "VOL" }, /* CF firmware volume control , */ \ + { 0x5202, \ + "CLIPCTRL" }, /* Clip control setting , */ \ + { 0x5230, \ + "SLOPEE" }, /* Enables slope control , */ \ + { 0x5240, \ + "SLOPESET" }, /* Slope speed setting (binary coded) , */ \ + { 0x5287, \ + "AMPGAIN" }, /* Amplifier gain , */ \ + { 0x5703, \ + "TDMDCG" }, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */ \ + { 0x5743, \ + "TDMSPKG" }, /* Total gain depending on INPLEV setting (channel 0), */ \ + { 0x5781, \ + "DCINSEL" }, /* VAMP_OUT2 input selection , */ \ + { 0x5881, \ + "LNMODE" }, /* Low noise gain mode control , */ \ + { 0x5ac1, \ + "LPM1MODE" }, /* Low power mode control , */ \ + { 0x5d02, \ + "TDMSRCMAP" }, /* TDM source mapping , */ \ + { 0x5d31, \ + "TDMSRCAS" }, /* Sensed value A , */ \ + { 0x5d51, \ + "TDMSRCBS" }, /* Sensed value B , */ \ + { 0x5d71, \ + "TDMSRCACLIP" }, /* Clip information (analog /digital) for source0 , */ \ + { 0x5d91, \ + "TDMSRCBCLIP" }, /* Clip information (analog /digital) for source1 , */ \ + { 0x6102, \ + "DELCURCOMP" }, /* Delay to allign compensation signal with current sense signal, */ \ + { 0x6130, \ + "SIGCURCOMP" }, /* Polarity of compensation for current sense , */ \ + { 0x6140, \ + "ENCURCOMP" }, /* Enable current sense compensation , */ \ + { 0x6152, \ + "LVLCLPPWM" }, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */ \ + { 0x7005, \ + "DCVOF" }, /* First Boost Voltage Level , */ \ + { 0x7065, \ + "DCVOS" }, /* Second Boost Voltage Level , */ \ + { 0x70c3, \ + "DCMCC" }, /* Max Coil Current , */ \ + { 0x7101, \ + "DCCV" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7120, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x7130, \ + "DCSR" }, /* Soft ramp up/down , */ \ + { 0x7140, \ + "DCDIS" }, /* DCDC on/off , */ \ + { 0x7150, \ + "DCPWM" }, /* DCDC PWM only mode , */ \ + { 0x7160, \ + "DCTRACK" }, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */ \ + { 0x7204, \ + "DCTRIP" }, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7254, \ + "DCTRIP2" }, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x72a4, \ + "DCTRIPT" }, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0x72f0, \ + "DCTRIPHYSTE" }, /* Enable hysteresis on booster trip levels , */ \ + { 0x7304, \ + "DCHOLD" }, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */ \ + { 0x9000, \ + "RST" }, /* Reset for Coolflux DSP , */ \ + { 0x9011, \ + "DMEM" }, /* Target memory for CFMA using I2C interface , */ \ + { 0x9030, \ + "AIF" }, /* Auto increment , */ \ + { 0x9040, \ + "CFINT" }, /* Coolflux Interrupt - auto clear , */ \ + { 0x9050, \ + "CFCGATE" }, /* Coolflux clock gating disabling control , */ \ + { 0x9080, \ + "REQCMD" }, /* Firmware event request rpc command , */ \ + { 0x9090, \ + "REQRST" }, /* Firmware event request reset restart , */ \ + { 0x90a0, \ + "REQMIPS" }, /* Firmware event request short on mips , */ \ + { 0x90b0, \ + "REQMUTED" }, /* Firmware event request mute sequence ready , */ \ + { 0x90c0, \ + "REQVOL" }, /* Firmware event request volume ready , */ \ + { 0x90d0, \ + "REQDMG" }, /* Firmware event request speaker damage detected , */ \ + { 0x90e0, \ + "REQCAL" }, /* Firmware event request calibration completed , */ \ + { 0x90f0, \ + "REQRSV" }, /* Firmware event request reserved , */ \ + { 0x910f, \ + "MADD" }, /* CF memory address , */ \ + { 0x920f, \ + "MEMA" }, /* Activate memory access , */ \ + { 0x9307, \ + "ERR" }, /* CF error flags , */ \ + { 0x9380, \ + "ACKCMD" }, /* Firmware event acknowledge rpc command , */ \ + { 0x9390, \ + "ACKRST" }, /* Firmware event acknowledge reset restart , */ \ + { 0x93a0, \ + "ACKMIPS" }, /* Firmware event acknowledge short on mips , */ \ + { 0x93b0, \ + "ACKMUTED" }, /* Firmware event acknowledge mute sequence ready , */ \ + { 0x93c0, \ + "ACKVOL" }, /* Firmware event acknowledge volume ready , */ \ + { 0x93d0, \ + "ACKDMG" }, /* Firmware event acknowledge speaker damage detected, */ \ + { 0x93e0, \ + "ACKCAL" }, /* Firmware event acknowledge calibration completed , */ \ + { 0x93f0, \ + "ACKRSV" }, /* Firmware event acknowledge reserved , */ \ + { 0xa107, \ + "MTPK" }, /* KEY2 to access KEY2 protected registers, customer key, */ \ + { 0xa200, \ + "KEY1LOCKED" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "KEY2LOCKED" }, /* Indicates KEY2 is locked , */ \ + { 0xa350, \ + "CMTPI" }, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */ \ + { 0xa360, \ + "CIMTP" }, /* Start copying data from I2C mtp registers to mtp - auto clear, */ \ + { 0xa50f, \ + "MTPRDMSB" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "MTPRDLSB" }, /* LSB word of MTP manual read data , */ \ + { 0xb108, \ + "EXTTS" }, /* External temperature (C) , */ \ + { 0xb190, \ + "TROS" }, /* Select temp Speaker calibration , */ \ + { 0xe00f, \ + "SWPROFIL" }, /* Software profile data , */ \ + { 0xe10f, \ + "SWVSTEP" }, /* Software vstep information , */ \ + { 0xf000, \ + "MTPOTC" }, /* Calibration schedule , */ \ + { 0xf010, \ + "MTPEX" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "DCMCCAPI" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "DCMCCSB" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "USERDEF" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "CUSTINFO" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf50f, \ + "R25C" }, /* Ron resistance of speaker coil , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9894_BITNAMETABLE \ + static tfaBfName_t Tfa9894BitNames[] = { \ + { 0x0, \ + "powerdown" }, /* Powerdown control , */ \ + { 0x10, \ + "reset" }, /* I2C Reset - Auto clear , */ \ + { 0x20, \ + "enbl_coolflux" }, /* Enable CoolFlux DSP , */ \ + { 0x30, \ + "enbl_amplifier" }, /* Enable Amplifier , */ \ + { 0x40, \ + "enbl_boost" }, /* Enable DCDC Boost converter , */ \ + { 0x50, \ + "coolflux_configured" }, /* Coolflux configured , */ \ + { 0x60, \ + "sel_enbl_amplifier" }, /* CoolFlux control over amplifier , */ \ + { 0x71, \ + "int_pad_io" }, /* Interrupt config , */ \ + { 0x90, \ + "fs_pulse_sel" }, /* Audio sample reference , */ \ + { 0xa0, \ + "bypass_ocp" }, /* Bypass OCP , */ \ + { 0xb0, \ + "test_ocp" }, /* OCP testing control , */ \ + { 0xc0, \ + "batsense_steepness" }, /* Vbat protection steepness , */ \ + { 0xd0, \ + "bypass_hp" }, /* Bypass High Pass Filter , */ \ + { 0xe0, \ + "enbl_dpsa" }, /* Enable DPSA , */ \ + { 0xf0, \ + "sel_hysteresis" }, /* Select hysteresis for clock range detector , */ \ + { 0x101, \ + "vamp_sel1" }, /* Amplifier input selection , */ \ + { 0x120, \ + "src_set_configured" }, /* Device I2C settings configured , */ \ + { 0x130, \ + "execute_cold_start" }, /* Execute cold start , */ \ + { 0x140, \ + "man_enbl_brown_out" }, /* Reaction on BOD , */ \ + { 0x150, \ + "bod_enbl" }, /* Enable BOD (only in direct control mode) , */ \ + { 0x160, \ + "bod_hyst_enbl" }, /* Enable Hysteresis of BOD , */ \ + { 0x171, \ + "bod_delay_set" }, /* BOD filter , */ \ + { 0x191, \ + "bod_lvl_set" }, /* BOD threshold , */ \ + { 0x1b0, \ + "disable_mute_time_out" }, /* Time out SB mute sequence , */ \ + { 0x1c0, \ + "man_enbl_watchdog" }, /* Watchdog enable , */ \ + { 0x1d0, \ + "disable_engage" }, /* Disable Engage , */ \ + { 0x1e0, \ + "unprotect_faim" }, /* Control for FAIM protection , */ \ + { 0x1f0, \ + "faim_enable_vbg" }, /* Overrule the enabling of VBG for faim erase/write access, */ \ + { 0x203, \ + "audio_fs" }, /* Audio sample rate Fs , */ \ + { 0x240, \ + "input_level" }, /* TDM output attenuation , */ \ + { 0x255, \ + "cs_frac_delay" }, /* Current sense fractional delay , */ \ + { 0x2b1, \ + "use_tdm_presence" }, /* Control for HW manager , */ \ + { 0x2d2, \ + "ctrl_on2off_criterion" }, /* Amplifier on-off criteria for shutdown , */ \ + { 0x30f, \ + "device_rev" }, /* Revision info , */ \ + { 0x401, \ + "pll_clkin_sel" }, /* PLL external reference clock , */ \ + { 0x420, \ + "pll_clkin_sel_osc" }, /* PLL internal reference clock , */ \ + { 0x432, \ + "mclk_sel" }, /* Master Clock Selection , */ \ + { 0x460, \ + "enbl_osc1m_auto_off" }, /* Internal OSC1M off at PWDN , */ \ + { 0x470, \ + "disable_auto_sel_refclk" }, /* Automatic PLL reference clock selection for cold start, */ \ + { 0x510, \ + "enbl_spkr_ss" }, /* Enable speaker sub-system , */ \ + { 0x520, \ + "enbl_faim_ss" }, /* Enable FAIM sub-system , */ \ + { 0x530, \ + "enbl_wdt_clk" }, /* Enable Coolflux watchdog clock , */ \ + { 0xe07, \ + "ctrl_digtoana" }, /* Spare control from digital to analog , */ \ + { 0xf0f, \ + "hidden_code" }, /* Hidden code to enable access to hidden register. (0x5A6B/23147 default for engineering), */ \ + { 0x1000, \ + "flag_por" }, /* POR , */ \ + { 0x1010, \ + "flag_pll_lock" }, /* PLL Lock , */ \ + { 0x1020, \ + "flag_otpok" }, /* OTP alarm , */ \ + { 0x1030, \ + "flag_ovpok" }, /* OVP alarm , */ \ + { 0x1040, \ + "flag_uvpok" }, /* UVP alarm , */ \ + { 0x1050, \ + "flag_ocp_alarm" }, /* OCP amplifier (sticky register, clear on read) , */ \ + { 0x1060, \ + "flag_clocks_stable" }, /* Clocks stable , */ \ + { 0x1070, \ + "flag_mtp_busy" }, /* MTP busy , */ \ + { 0x1080, \ + "flag_lost_clk" }, /* Lost clock , */ \ + { 0x1090, \ + "flag_cold_started" }, /* Cold Start , */ \ + { 0x10a0, \ + "flag_watchdog_reset" }, /* Watchdog , */ \ + { 0x10b0, \ + "flag_engage" }, /* Amplifier engage , */ \ + { 0x10c0, \ + "flag_enbl_amp" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "flag_enbl_ref" }, /* References enable , */ \ + { 0x10e0, \ + "flag_adc10_ready" }, /* Control ADC , */ \ + { 0x10f0, \ + "flag_bod_vddd_nok" }, /* BOD Flag - VDD NOT OK , */ \ + { 0x1100, \ + "flag_bst_bstcur" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "flag_bst_hiz" }, /* DCDC active (sticky register, clear on read) , */ \ + { 0x1120, \ + "flag_bst_ocpok" }, /* DCDC OCP nmos (sticky register, clear on read) , */ \ + { 0x1130, \ + "flag_bst_peakcur" }, /* Indicates current is max in DC-to-DC converter , */ \ + { 0x1140, \ + "flag_bst_voutcomp" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "flag_bst_voutcomp86" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "flag_bst_voutcomp93" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "flag_cf_speakererror" }, /* Speaker status , */ \ + { 0x1180, \ + "flag_clk_out_of_range" }, /* External clock status , */ \ + { 0x1190, \ + "flag_man_alarm_state" }, /* Alarm state , */ \ + { 0x11a0, \ + "flag_tdm_error" }, /* TDM error , */ \ + { 0x11b0, \ + "flag_tdm_lut_error" }, /* TDM lookup table error , */ \ + { 0x1200, \ + "flag_ocpokap" }, /* OCPOK pmos A , */ \ + { 0x1210, \ + "flag_ocpokan" }, /* OCPOK nmos A , */ \ + { 0x1220, \ + "flag_ocpokbp" }, /* OCPOK pmos B , */ \ + { 0x1230, \ + "flag_ocpokbn" }, /* OCPOK nmos B , */ \ + { 0x1240, \ + "flag_clip" }, /* Amplifier clipping , */ \ + { 0x1250, \ + "flag_man_start_mute_audio" }, /* Audio mute sequence , */ \ + { 0x1260, \ + "flag_man_operating_state" }, /* Device in Operating state , */ \ + { 0x1270, \ + "flag_lp_detect_mode1" }, /* Low power MODE1 detection , */ \ + { 0x1280, \ + "flag_low_amplitude" }, /* Low amplitude detection , */ \ + { 0x1290, \ + "flag_vddp_gt_vbat" }, /* VDDP greater than VBAT flag , */ \ + { 0x1402, \ + "tdm_status" }, /* TDM Status bits , */ \ + { 0x1433, \ + "man_state" }, /* Device Manager status , */ \ + { 0x1473, \ + "amp_ctrl_state" }, /* Amplifier control status , */ \ + { 0x14b1, \ + "status_bst_mode" }, /* DCDC mode status bits , */ \ + { 0x1509, \ + "bat_adc" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "temp_adc" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "vddp_adc" }, /* IC VDDP voltage (1023*VDDP/13V) , */ \ + { 0x2000, \ + "tdm_enable" }, /* Enable interface , */ \ + { 0x2010, \ + "tdm_sink0_enable" }, /* Control audio tdm channel in sink0 , */ \ + { 0x2020, \ + "tdm_sink1_enable" }, /* Control audio tdm channel in sink1 , */ \ + { 0x2030, \ + "tdm_source0_enable" }, /* Source 0 enable , */ \ + { 0x2040, \ + "tdm_source1_enable" }, /* Source 1 enable , */ \ + { 0x2050, \ + "tdm_source2_enable" }, /* Source 2 enable , */ \ + { 0x2060, \ + "tdm_source3_enable" }, /* Source 3 enable , */ \ + { 0x2070, \ + "tdm_clk_inversion" }, /* Reception data to BCK clock , */ \ + { 0x2080, \ + "tdm_fs_ws_polarity" }, /* FS polarity , */ \ + { 0x2090, \ + "tdm_data_delay" }, /* Data delay to FS , */ \ + { 0x20a0, \ + "tdm_data_adjustment" }, /* Data adjustment , */ \ + { 0x20b1, \ + "tdm_audio_sample_compression" }, /* Received audio compression , */ \ + { 0x2103, \ + "tdm_nbck" }, /* TDM NBCK - Bit clock to FS ratio , */ \ + { 0x2143, \ + "tdm_fs_ws_length" }, /* FS length (master mode only) , */ \ + { 0x2183, \ + "tdm_nb_of_slots" }, /* N-slots in Frame , */ \ + { 0x21c1, \ + "tdm_txdata_format" }, /* Format unused bits , */ \ + { 0x21e1, \ + "tdm_txdata_format_unused_slot" }, /* Format unused slots DATAO , */ \ + { 0x2204, \ + "tdm_slot_length" }, /* N-bits in slot , */ \ + { 0x2254, \ + "tdm_bits_remaining" }, /* N-bits remaining , */ \ + { 0x22a4, \ + "tdm_sample_size" }, /* Sample size per slot , */ \ + { 0x2303, \ + "tdm_sink0_slot" }, /* TDM slot for sink 0 , */ \ + { 0x2343, \ + "tdm_sink1_slot" }, /* TDM slot for sink 1 , */ \ + { 0x2381, \ + "tdm_source2_sel" }, /* TDM Source 2 data selection , */ \ + { 0x23a1, \ + "tdm_source3_sel" }, /* TDM Source 3 data selection , */ \ + { 0x2403, \ + "tdm_source0_slot" }, /* Slot Position of source 0 data , */ \ + { 0x2443, \ + "tdm_source1_slot" }, /* Slot Position of source 1 data , */ \ + { 0x2483, \ + "tdm_source2_slot" }, /* Slot Position of source 2 data , */ \ + { 0x24c3, \ + "tdm_source3_slot" }, /* Slot Position of source 3 data , */ \ + { 0x4000, \ + "int_out_flag_por" }, /* Status POR , */ \ + { 0x4010, \ + "int_out_flag_bst_ocpok" }, /* Status DCDC OCP , */ \ + { 0x4020, \ + "int_out_flag_otpok" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "int_out_flag_ocp_alarm" }, /* Status OCP alarm , */ \ + { 0x4040, \ + "int_out_flag_uvpok" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "int_out_flag_man_alarm_state" }, /* Status manager alarm state , */ \ + { 0x4060, \ + "int_out_flag_tdm_error" }, /* Status TDM error , */ \ + { 0x4070, \ + "int_out_flag_lost_clk" }, /* Status lost clock , */ \ + { 0x4080, \ + "int_out_flag_cfma_err" }, /* Status cfma error , */ \ + { 0x4090, \ + "int_out_flag_cfma_ack" }, /* Status cfma ack , */ \ + { 0x40a0, \ + "int_out_flag_cf_speakererror" }, /* Status coolflux speaker error , */ \ + { 0x40b0, \ + "int_out_flag_cold_started" }, /* Status cold started , */ \ + { 0x40c0, \ + "int_out_flag_watchdog_reset" }, /* Status watchdog reset , */ \ + { 0x40d0, \ + "int_out_flag_bod_vddd_nok" }, /* Status brown out detect , */ \ + { 0x40e0, \ + "int_out_flag_lp_detect_mode1" }, /* Status low power mode1 detect , */ \ + { 0x40f0, \ + "int_out_flag_clk_out_of_range" }, /* Status clock out of range , */ \ + { 0x4400, \ + "int_in_flag_por" }, /* Clear POR , */ \ + { 0x4410, \ + "int_in_flag_bst_ocpok" }, /* Clear DCDC OCP , */ \ + { 0x4420, \ + "int_in_flag_otpok" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "int_in_flag_ocp_alarm" }, /* Clear OCP alarm , */ \ + { 0x4440, \ + "int_in_flag_uvpok" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "int_in_flag_man_alarm_state" }, /* Clear manager alarm state , */ \ + { 0x4460, \ + "int_in_flag_tdm_error" }, /* Clear TDM error , */ \ + { 0x4470, \ + "int_in_flag_lost_clk" }, /* Clear lost clk , */ \ + { 0x4480, \ + "int_in_flag_cfma_err" }, /* Clear cfma err , */ \ + { 0x4490, \ + "int_in_flag_cfma_ack" }, /* Clear cfma ack , */ \ + { 0x44a0, \ + "int_in_flag_cf_speakererror" }, /* Clear coolflux speaker error , */ \ + { 0x44b0, \ + "int_in_flag_cold_started" }, /* Clear cold started , */ \ + { 0x44c0, \ + "int_in_flag_watchdog_reset" }, /* Clear watchdog reset , */ \ + { 0x44d0, \ + "int_in_flag_bod_vddd_nok" }, /* Clear brown out detect , */ \ + { 0x44e0, \ + "int_in_flag_lp_detect_mode1" }, /* Clear low power mode1 detect , */ \ + { 0x44f0, \ + "int_in_flag_clk_out_of_range" }, /* Clear clock out of range , */ \ + { 0x4800, \ + "int_enable_flag_por" }, /* Enable POR , */ \ + { 0x4810, \ + "int_enable_flag_bst_ocpok" }, /* Enable DCDC OCP , */ \ + { 0x4820, \ + "int_enable_flag_otpok" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "int_enable_flag_ocp_alarm" }, /* Enable OCP alarm , */ \ + { 0x4840, \ + "int_enable_flag_uvpok" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "int_enable_flag_man_alarm_state" }, /* Enable Manager Alarm state , */ \ + { 0x4860, \ + "int_enable_flag_tdm_error" }, /* Enable TDM error , */ \ + { 0x4870, \ + "int_enable_flag_lost_clk" }, /* Enable lost clk , */ \ + { 0x4880, \ + "int_enable_flag_cfma_err" }, /* Enable cfma err , */ \ + { 0x4890, \ + "int_enable_flag_cfma_ack" }, /* Enable cfma ack , */ \ + { 0x48a0, \ + "int_enable_flag_cf_speakererror" }, /* Enable coolflux speaker error , */ \ + { 0x48b0, \ + "int_enable_flag_cold_started" }, /* Enable cold started , */ \ + { 0x48c0, \ + "int_enable_flag_watchdog_reset" }, /* Enable watchdog reset , */ \ + { 0x48d0, \ + "int_enable_flag_bod_vddd_nok" }, /* Enable brown out detect , */ \ + { 0x48e0, \ + "int_enable_flag_lp_detect_mode1" }, /* Enable low power mode1 detect , */ \ + { 0x48f0, \ + "int_enable_flag_clk_out_of_range" }, /* Enable clock out of range , */ \ + { 0x4c00, \ + "int_polarity_flag_por" }, /* Polarity POR , */ \ + { 0x4c10, \ + "int_polarity_flag_bst_ocpok" }, /* Polarity DCDC OCP , */ \ + { 0x4c20, \ + "int_polarity_flag_otpok" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "int_polarity_flag_ocp_alarm" }, /* Polarity ocp alarm , */ \ + { 0x4c40, \ + "int_polarity_flag_uvpok" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "int_polarity_flag_man_alarm_state" }, /* Polarity manager alarm state , */ \ + { 0x4c60, \ + "int_polarity_flag_tdm_error" }, /* Polarity TDM error , */ \ + { 0x4c70, \ + "int_polarity_flag_lost_clk" }, /* Polarity lost clk , */ \ + { 0x4c80, \ + "int_polarity_flag_cfma_err" }, /* Polarity cfma err , */ \ + { 0x4c90, \ + "int_polarity_flag_cfma_ack" }, /* Polarity cfma ack , */ \ + { 0x4ca0, \ + "int_polarity_flag_cf_speakererror" }, /* Polarity coolflux speaker error , */ \ + { 0x4cb0, \ + "int_polarity_flag_cold_started" }, /* Polarity cold started , */ \ + { 0x4cc0, \ + "int_polarity_flag_watchdog_reset" }, /* Polarity watchdog reset , */ \ + { 0x4cd0, \ + "int_polarity_flag_bod_vddd_nok" }, /* Polarity brown out detect , */ \ + { 0x4ce0, \ + "int_polarity_flag_lp_detect_mode1" }, /* Polarity low power mode1 detect , */ \ + { 0x4cf0, \ + "int_polarity_flag_clk_out_of_range" }, /* Polarity clock out of range , */ \ + { 0x5001, \ + "vbat_prot_attack_time" }, /* Battery safeguard attack time , */ \ + { 0x5023, \ + "vbat_prot_thlevel" }, /* Battery safeguard threshold voltage level , */ \ + { 0x5061, \ + "vbat_prot_max_reduct" }, /* Battery safeguard maximum reduction , */ \ + { 0x5082, \ + "vbat_prot_release_time" }, /* Battery safeguard release time , */ \ + { 0x50b1, \ + "vbat_prot_hysterese" }, /* Battery Safeguard hysteresis , */ \ + { 0x50d0, \ + "rst_min_vbat" }, /* Reset clipper - auto clear , */ \ + { 0x50e0, \ + "sel_vbat" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "bypass_clipper" }, /* Bypass HW clipper , */ \ + { 0x5130, \ + "cf_mute" }, /* Coolflux firmware soft mute control , */ \ + { 0x5187, \ + "cf_volume" }, /* CF firmware volume control , */ \ + { 0x5202, \ + "ctrl_cc" }, /* Clip control setting , */ \ + { 0x5230, \ + "ctrl_slopectrl" }, /* Enables slope control , */ \ + { 0x5240, \ + "ctrl_slope" }, /* Slope speed setting (binary coded) , */ \ + { 0x5287, \ + "gain" }, /* Amplifier gain , */ \ + { 0x5301, \ + "dpsa_level" }, /* DPSA threshold levels , */ \ + { 0x5321, \ + "dpsa_release" }, /* DPSA Release time , */ \ + { 0x5340, \ + "clipfast" }, /* Clock selection for HW clipper for battery safeguard, */ \ + { 0x5350, \ + "bypass_lp" }, /* Bypass the low power filter inside temperature sensor, */ \ + { 0x5360, \ + "first_order_mode" }, /* Overrule to 1st order mode of control stage when clipping, */ \ + { 0x5370, \ + "icomp_engage" }, /* Engage of icomp , */ \ + { 0x5380, \ + "ctrl_kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x5390, \ + "icomp_engage_overrule" }, /* To overrule the functional icomp_engage signal during validation, */ \ + { 0x53a3, \ + "ctrl_dem" }, /* Enable DEM icomp and DEM one bit dac , */ \ + { 0x5400, \ + "bypass_ctrlloop" }, /* Switch amplifier into open loop configuration , */ \ + { 0x5413, \ + "ctrl_dem_mismatch" }, /* Enable DEM icomp mismatch for testing , */ \ + { 0x5452, \ + "dpsa_drive" }, /* Drive setting (binary coded) , */ \ + { 0x550a, \ + "enbl_amp" }, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */ \ + { 0x55b0, \ + "enbl_engage" }, /* Enables/engage power stage and control loop , */ \ + { 0x55c0, \ + "enbl_engage_pst" }, /* Enables/engage power stage and control loop , */ \ + { 0x5600, \ + "pwm_shape" }, /* PWM shape , */ \ + { 0x5614, \ + "pwm_delay" }, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */ \ + { 0x5660, \ + "reclock_pwm" }, /* Reclock the PWM signal inside analog , */ \ + { 0x5670, \ + "reclock_voltsense" }, /* Reclock the voltage sense PWM signal , */ \ + { 0x5680, \ + "enbl_pwm_phase_shift" }, /* Control for PWM phase shift , */ \ + { 0x5690, \ + "sel_pwm_delay_src" }, /* Control for selection for PWM delay line source , */ \ + { 0x56a1, \ + "enbl_odd_up_even_down" }, /* Control for PWM reference sawtooth generartion , */ \ + { 0x5703, \ + "ctrl_att_dcdc" }, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */ \ + { 0x5743, \ + "ctrl_att_spkr" }, /* Total gain depending on INPLEV setting (channel 0), */ \ + { 0x5781, \ + "vamp_sel2" }, /* VAMP_OUT2 input selection , */ \ + { 0x5805, \ + "zero_lvl" }, /* Low noise gain switch zero trigger level , */ \ + { 0x5861, \ + "ctrl_fb_resistor" }, /* Select amplifier feedback resistor connection , */ \ + { 0x5881, \ + "lownoisegain_mode" }, /* Low noise gain mode control , */ \ + { 0x5905, \ + "threshold_lvl" }, /* Low noise gain switch trigger level , */ \ + { 0x5965, \ + "hold_time" }, /* Low noise mode hold time before entering into low noise mode, */ \ + { 0x5a05, \ + "lpm1_cal_offset" }, /* Low power mode1 detector ctrl cal_offset from gain module , */ \ + { 0x5a65, \ + "lpm1_zero_lvl" }, /* Low power mode1 zero crossing detection level , */ \ + { 0x5ac1, \ + "lpm1_mode" }, /* Low power mode control , */ \ + { 0x5b05, \ + "lpm1_threshold_lvl" }, /* Low power mode1 amplitude trigger level , */ \ + { 0x5b65, \ + "lpm1_hold_time" }, /* Low power mode hold time before entering into low power mode, */ \ + { 0x5bc0, \ + "disable_low_power_mode" }, /* Low power mode1 detector control , */ \ + { 0x5c00, \ + "enbl_minion" }, /* Enables minion (small) power stage , */ \ + { 0x5c13, \ + "vth_vddpvbat" }, /* Select vddp-vbat threshold signal , */ \ + { 0x5c50, \ + "lpen_vddpvbat" }, /* Select vddp-vbat filtred vs unfiltered compare , */ \ + { 0x5c61, \ + "ctrl_rfb" }, /* Feedback resistor selection - I2C direct mode , */ \ + { 0x5d02, \ + "tdm_source_mapping" }, /* TDM source mapping , */ \ + { 0x5d31, \ + "tdm_sourcea_frame_sel" }, /* Sensed value A , */ \ + { 0x5d51, \ + "tdm_sourceb_frame_sel" }, /* Sensed value B , */ \ + { 0x5d71, \ + "tdm_source0_clip_sel" }, /* Clip information (analog /digital) for source0 , */ \ + { 0x5d91, \ + "tdm_source1_clip_sel" }, /* Clip information (analog /digital) for source1 , */ \ + { 0x5e02, \ + "rst_min_vbat_delay" }, /* Delay for reseting the min_vbat value inside HW Clipper (number of Fs pulses), */ \ + { 0x5e30, \ + "rst_min_vbat_sel" }, /* Control for selecting reset signal for min_bat , */ \ + { 0x5f00, \ + "hard_mute" }, /* Hard mute - PWM , */ \ + { 0x5f12, \ + "ns_hp2ln_criterion" }, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */ \ + { 0x5f42, \ + "ns_ln2hp_criterion" }, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */ \ + { 0x5f78, \ + "spare_out" }, /* Spare out register , */ \ + { 0x600f, \ + "spare_in" }, /* Spare IN , */ \ + { 0x6102, \ + "cursense_comp_delay" }, /* Delay to allign compensation signal with current sense signal, */ \ + { 0x6130, \ + "cursense_comp_sign" }, /* Polarity of compensation for current sense , */ \ + { 0x6140, \ + "enbl_cursense_comp" }, /* Enable current sense compensation , */ \ + { 0x6152, \ + "pwms_clip_lvl" }, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */ \ + { 0x7005, \ + "frst_boost_voltage" }, /* First Boost Voltage Level , */ \ + { 0x7065, \ + "scnd_boost_voltage" }, /* Second Boost Voltage Level , */ \ + { 0x70c3, \ + "boost_cur" }, /* Max Coil Current , */ \ + { 0x7101, \ + "bst_slpcmplvl" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7120, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x7130, \ + "boost_speed" }, /* Soft ramp up/down , */ \ + { 0x7140, \ + "dcdcoff_mode" }, /* DCDC on/off , */ \ + { 0x7150, \ + "dcdc_pwmonly" }, /* DCDC PWM only mode , */ \ + { 0x7160, \ + "boost_track" }, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */ \ + { 0x7170, \ + "sel_dcdc_envelope_8fs" }, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */ \ + { 0x7180, \ + "ignore_flag_voutcomp86" }, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */ \ + { 0x7204, \ + "boost_trip_lvl_1st" }, /* 1st adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x7254, \ + "boost_trip_lvl_2nd" }, /* 2nd adaptive boost trip levels, effective only when DCIE is set to 1, */ \ + { 0x72a4, \ + "boost_trip_lvl_track" }, /* Track adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0x72f0, \ + "enbl_trip_hyst" }, /* Enable hysteresis on booster trip levels , */ \ + { 0x7304, \ + "boost_hold_time" }, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */ \ + { 0x7350, \ + "dcdc_pfm20khz_limit" }, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */ \ + { 0x7361, \ + "dcdc_ctrl_maxzercnt" }, /* Number of zero current flags to count before going to pfm mode, */ \ + { 0x7386, \ + "dcdc_vbat_delta_detect" }, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */ \ + { 0x73f0, \ + "dcdc_ignore_vbat" }, /* Ignore an increase on Vbat , */ \ + { 0x7404, \ + "bst_drive" }, /* Binary coded drive setting for boost converter power stage, */ \ + { 0x7451, \ + "bst_scalecur" }, /* For testing direct control scale current , */ \ + { 0x7474, \ + "bst_slopecur" }, /* For testing direct control slope current , */ \ + { 0x74c1, \ + "bst_slope" }, /* Boost slope speed , */ \ + { 0x74e0, \ + "bst_bypass_bstcur" }, /* Bypass control for boost current settings , */ \ + { 0x74f0, \ + "bst_bypass_bstfoldback" }, /* Bypass control for boost foldback , */ \ + { 0x7500, \ + "enbl_bst_engage" }, /* Enable power stage dcdc controller , */ \ + { 0x7510, \ + "enbl_bst_hizcom" }, /* Enable hiz comparator , */ \ + { 0x7520, \ + "enbl_bst_peakcur" }, /* Enable peak current , */ \ + { 0x7530, \ + "enbl_bst_power" }, /* Enable line of the powerstage , */ \ + { 0x7540, \ + "enbl_bst_slopecur" }, /* Enable bit of max-current dac , */ \ + { 0x7550, \ + "enbl_bst_voutcomp" }, /* Enable vout comparators , */ \ + { 0x7560, \ + "enbl_bst_voutcomp86" }, /* Enable vout-86 comparators , */ \ + { 0x7570, \ + "enbl_bst_voutcomp93" }, /* Enable vout-93 comparators , */ \ + { 0x7580, \ + "enbl_bst_windac" }, /* Enable window dac , */ \ + { 0x7595, \ + "bst_windac" }, /* For testing direct control windac , */ \ + { 0x7600, \ + "boost_alg" }, /* Control for boost adaptive loop gain , */ \ + { 0x7611, \ + "boost_loopgain" }, /* DCDC boost loopgain setting , */ \ + { 0x7631, \ + "bst_freq" }, /* DCDC boost frequency control , */ \ + { 0x7650, \ + "enbl_bst_peak2avg" }, /* Enable boost peak2avg functionality , */ \ + { 0x7660, \ + "bst_use_new_zercur_detect" }, /* Enable new zero current detection for boost control, */ \ + { 0x8001, \ + "sel_clk_cs" }, /* Current sense clock duty cycle control , */ \ + { 0x8021, \ + "micadc_speed" }, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */ \ + { 0x8040, \ + "cs_gain_control" }, /* Current sense gain control , */ \ + { 0x8050, \ + "cs_bypass_gc" }, /* Bypasses the CS gain correction , */ \ + { 0x8060, \ + "invertpwm" }, /* Current sense common mode feedback pwm invert control, */ \ + { 0x8087, \ + "cs_gain" }, /* Current sense gain , */ \ + { 0x8105, \ + "cs_ktemp" }, /* Current sense temperature compensation trimming (1 - VALUE*TEMP) * signal, */ \ + { 0x8164, \ + "cs_ktemp2" }, /* Second order temperature compensation coefficient , */ \ + { 0x81b0, \ + "enbl_cs_adc" }, /* Enable current sense ADC , */ \ + { 0x81c0, \ + "enbl_cs_inn1" }, /* Enable connection of current sense negative1 , */ \ + { 0x81d0, \ + "enbl_cs_inn2" }, /* Enable connection of current sense negative2 , */ \ + { 0x81e0, \ + "enbl_cs_inp1" }, /* Enable connection of current sense positive1 , */ \ + { 0x81f0, \ + "enbl_cs_inp2" }, /* Enable connection of current sense positive2 , */ \ + { 0x8200, \ + "enbl_cs_ldo" }, /* Enable current sense LDO , */ \ + { 0x8210, \ + "enbl_cs_vbatldo" }, /* Enable of current sense LDO , */ \ + { 0x8220, \ + "cs_adc_bsoinv" }, /* Bitstream inversion for current sense ADC , */ \ + { 0x8231, \ + "cs_adc_hifreq" }, /* Frequency mode current sense ADC , */ \ + { 0x8250, \ + "cs_adc_nortz" }, /* Return to zero for current sense ADC , */ \ + { 0x8263, \ + "cs_adc_offset" }, /* Micadc ADC offset setting , */ \ + { 0x82a0, \ + "cs_adc_slowdel" }, /* Select delay for current sense ADC (internal decision circuitry), */ \ + { 0x82b4, \ + "cs_adc_gain" }, /* Gain setting for current sense ADC (two's complement), */ \ + { 0x8300, \ + "cs_resonator_enable" }, /* Enable for resonator to improve SRN , */ \ + { 0x8310, \ + "cs_classd_tran_skip" }, /* Skip current sense connection during a classD amplifier transition, */ \ + { 0x8320, \ + "cs_inn_short" }, /* Short current sense negative to common mode , */ \ + { 0x8330, \ + "cs_inp_short" }, /* Short current sense positive to common mode , */ \ + { 0x8340, \ + "cs_ldo_bypass" }, /* Bypass current sense LDO , */ \ + { 0x8350, \ + "cs_ldo_pulldown" }, /* Pull down current sense LDO, only valid if enbl_cs_ldo is high, */ \ + { 0x8364, \ + "cs_ldo_voset" }, /* Current sense LDO voltage level setting (two's complement), */ \ + { 0x8800, \ + "ctrl_vs_igen_supply" }, /* Control for selecting supply for VS current generator, */ \ + { 0x8810, \ + "ctrl_vs_force_div2" }, /* Select input resistive divider gain , */ \ + { 0x8820, \ + "enbl_dc_filter" }, /* Control for enabling the DC blocking filter for voltage and current sense, */ \ + { 0x8901, \ + "volsense_pwm_sel" }, /* Voltage sense source selection control , */ \ + { 0x8920, \ + "vs_gain_control" }, /* Voltage sense gain control , */ \ + { 0x8930, \ + "vs_bypass_gc" }, /* Bypasses the VS gain correction , */ \ + { 0x8940, \ + "vs_adc_bsoinv" }, /* Bitstream inversion for voltage sense ADC , */ \ + { 0x8950, \ + "vs_adc_nortz" }, /* Return to zero for voltage sense ADC , */ \ + { 0x8960, \ + "vs_adc_slowdel" }, /* Select delay for voltage sense ADC (internal decision circuitry), */ \ + { 0x8970, \ + "vs_classd_tran_skip" }, /* Skip voltage sense connection during a classD amplifier transition, */ \ + { 0x8987, \ + "vs_gain" }, /* Voltage sense gain , */ \ + { 0x8a00, \ + "vs_inn_short" }, /* Short voltage sense negative to common mode , */ \ + { 0x8a10, \ + "vs_inp_short" }, /* Short voltage sense positive to common mode , */ \ + { 0x8a20, \ + "vs_ldo_bypass" }, /* Bypass voltage sense LDO , */ \ + { 0x8a30, \ + "vs_ldo_pulldown" }, /* Pull down voltage sense LDO, only valid if enbl_cs_ldo is high, */ \ + { 0x8a44, \ + "vs_ldo_voset" }, /* Voltage sense LDO voltage level setting (two's complement), */ \ + { 0x8a90, \ + "enbl_vs_adc" }, /* Enable voltage sense ADC , */ \ + { 0x8aa0, \ + "enbl_vs_inn1" }, /* Enable connection of voltage sense negative1 , */ \ + { 0x8ab0, \ + "enbl_vs_inn2" }, /* Enable connection of voltage sense negative2 , */ \ + { 0x8ac0, \ + "enbl_vs_inp1" }, /* Enable connection of voltage sense positive1 , */ \ + { 0x8ad0, \ + "enbl_vs_inp2" }, /* Enable connection of voltage sense positive2 , */ \ + { 0x8ae0, \ + "enbl_vs_ldo" }, /* Enable voltage sense LDO , */ \ + { 0x8af0, \ + "enbl_vs_vbatldo" }, /* Enable of voltage sense LDO , */ \ + { 0x9000, \ + "cf_rst_dsp" }, /* Reset for Coolflux DSP , */ \ + { 0x9011, \ + "cf_dmem" }, /* Target memory for CFMA using I2C interface , */ \ + { 0x9030, \ + "cf_aif" }, /* Auto increment , */ \ + { 0x9040, \ + "cf_int" }, /* Coolflux Interrupt - auto clear , */ \ + { 0x9050, \ + "cf_cgate_off" }, /* Coolflux clock gating disabling control , */ \ + { 0x9080, \ + "cf_req_cmd" }, /* Firmware event request rpc command , */ \ + { 0x9090, \ + "cf_req_reset" }, /* Firmware event request reset restart , */ \ + { 0x90a0, \ + "cf_req_mips" }, /* Firmware event request short on mips , */ \ + { 0x90b0, \ + "cf_req_mute_ready" }, /* Firmware event request mute sequence ready , */ \ + { 0x90c0, \ + "cf_req_volume_ready" }, /* Firmware event request volume ready , */ \ + { 0x90d0, \ + "cf_req_damage" }, /* Firmware event request speaker damage detected , */ \ + { 0x90e0, \ + "cf_req_calibrate_ready" }, /* Firmware event request calibration completed , */ \ + { 0x90f0, \ + "cf_req_reserved" }, /* Firmware event request reserved , */ \ + { 0x910f, \ + "cf_madd" }, /* CF memory address , */ \ + { 0x920f, \ + "cf_mema" }, /* Activate memory access , */ \ + { 0x9307, \ + "cf_err" }, /* CF error flags , */ \ + { 0x9380, \ + "cf_ack_cmd" }, /* Firmware event acknowledge rpc command , */ \ + { 0x9390, \ + "cf_ack_reset" }, /* Firmware event acknowledge reset restart , */ \ + { 0x93a0, \ + "cf_ack_mips" }, /* Firmware event acknowledge short on mips , */ \ + { 0x93b0, \ + "cf_ack_mute_ready" }, /* Firmware event acknowledge mute sequence ready , */ \ + { 0x93c0, \ + "cf_ack_volume_ready" }, /* Firmware event acknowledge volume ready , */ \ + { 0x93d0, \ + "cf_ack_damage" }, /* Firmware event acknowledge speaker damage detected, */ \ + { 0x93e0, \ + "cf_ack_calibrate_ready" }, /* Firmware event acknowledge calibration completed , */ \ + { 0x93f0, \ + "cf_ack_reserved" }, /* Firmware event acknowledge reserved , */ \ + { 0xa007, \ + "mtpkey1" }, /* KEY1 To access KEY1 protected registers 0x5A/90d (default for engineering), */ \ + { 0xa107, \ + "mtpkey2" }, /* KEY2 to access KEY2 protected registers, customer key, */ \ + { 0xa200, \ + "key01_locked" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "key02_locked" }, /* Indicates KEY2 is locked , */ \ + { 0xa302, \ + "mtp_man_address_in" }, /* MTP address from I2C register for read/writing mtp in manual single word mode, */ \ + { 0xa330, \ + "man_copy_mtp_to_iic" }, /* Start copying single word from MTP to I2C mtp register - auto clear, */ \ + { 0xa340, \ + "man_copy_iic_to_mtp" }, /* Start copying single word from I2C mtp register to mtp - auto clear, */ \ + { 0xa350, \ + "auto_copy_mtp_to_iic" }, /* Start copying all the data from mtp to I2C mtp registers - auto clear, */ \ + { 0xa360, \ + "auto_copy_iic_to_mtp" }, /* Start copying data from I2C mtp registers to mtp - auto clear, */ \ + { 0xa400, \ + "faim_set_clkws" }, /* Sets the FaIM controller clock wait state register, */ \ + { 0xa410, \ + "faim_sel_evenrows" }, /* All even rows of the FaIM are selected, active high, */ \ + { 0xa420, \ + "faim_sel_oddrows" }, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */ \ + { 0xa430, \ + "faim_program_only" }, /* Skip the erase access at wr_faim command (write-program-marginread), */ \ + { 0xa440, \ + "faim_erase_only" }, /* Skip the program access at wr_faim command (write-erase-marginread), */ \ + { 0xa50f, \ + "mtp_man_data_out_msb" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "mtp_man_data_out_lsb" }, /* LSB word of MTP manual read data , */ \ + { 0xa70f, \ + "mtp_man_data_in_msb" }, /* MSB word of write data for MTP manual write , */ \ + { 0xa80f, \ + "mtp_man_data_in_lsb" }, /* LSB word of write data for MTP manual write , */ \ + { 0xb000, \ + "bypass_ocpcounter" }, /* Bypass OCP Counter , */ \ + { 0xb010, \ + "bypass_glitchfilter" }, /* Bypass glitch filter , */ \ + { 0xb020, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0xb030, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0xb040, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0xb050, \ + "bypass_lost_clk" }, /* Bypass lost clock detector , */ \ + { 0xb060, \ + "ctrl_vpalarm" }, /* vpalarm (uvp ovp handling) , */ \ + { 0xb070, \ + "disable_main_ctrl_change_prot" }, /* Disable main control change protection , */ \ + { 0xb087, \ + "ocp_threshold" }, /* OCP threshold level , */ \ + { 0xb108, \ + "ext_temp" }, /* External temperature (C) , */ \ + { 0xb190, \ + "ext_temp_sel" }, /* Select temp Speaker calibration , */ \ + { 0xc000, \ + "use_direct_ctrls" }, /* Direct control to overrule several functions for testing, */ \ + { 0xc010, \ + "rst_datapath" }, /* Direct control for datapath reset , */ \ + { 0xc020, \ + "rst_cgu" }, /* Direct control for cgu reset , */ \ + { 0xc038, \ + "enbl_ref" }, /* Switch on the analog references, each part of the references can be switched on/off individually, */ \ + { 0xc0c0, \ + "use_direct_vs_ctrls" }, /* Voltage sense direct control to overrule several functions for testing, */ \ + { 0xc0d0, \ + "enbl_ringo" }, /* Enable the ring oscillator for test purpose , */ \ + { 0xc0e0, \ + "use_direct_clk_ctrl" }, /* Direct clock control to overrule several functions for testing, */ \ + { 0xc0f0, \ + "use_direct_pll_ctrl" }, /* Direct PLL control to overrule several functions for testing, */ \ + { 0xc100, \ + "enbl_tsense" }, /* Temperature sensor enable control - I2C direct mode, */ \ + { 0xc110, \ + "tsense_hibias" }, /* Bit to set the biasing in temp sensor to high , */ \ + { 0xc120, \ + "enbl_flag_vbg" }, /* Enable flagging of bandgap out of control , */ \ + { 0xc20f, \ + "abist_offset" }, /* Offset control for ABIST testing (two's complement), */ \ + { 0xc300, \ + "bypasslatch" }, /* Bypass latch , */ \ + { 0xc311, \ + "sourcea" }, /* Set OUTA to , */ \ + { 0xc331, \ + "sourceb" }, /* Set OUTB to , */ \ + { 0xc350, \ + "inverta" }, /* Invert pwma test signal , */ \ + { 0xc360, \ + "invertb" }, /* Invert pwmb test signal , */ \ + { 0xc374, \ + "pulselength" }, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */ \ + { 0xc3d0, \ + "test_abistfft_enbl" }, /* Enable ABIST with FFT on Coolflux DSP , */ \ + { 0xc400, \ + "bst_bypasslatch" }, /* Bypass latch in boost converter , */ \ + { 0xc411, \ + "bst_source" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0xc430, \ + "bst_invertb" }, /* Invert pwmbst test signal , */ \ + { 0xc444, \ + "bst_pulselength" }, /* Pulse length setting test input for boost converter , */ \ + { 0xc490, \ + "test_bst_ctrlsthv" }, /* Test mode for boost control stage , */ \ + { 0xc4a0, \ + "test_bst_iddq" }, /* IDDQ testing in power stage of boost converter , */ \ + { 0xc4b0, \ + "test_bst_rdson" }, /* RDSON testing - boost power stage , */ \ + { 0xc4c0, \ + "test_bst_cvi" }, /* CVI testing - boost power stage , */ \ + { 0xc4d0, \ + "test_bst_ocp" }, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */ \ + { 0xc4e0, \ + "test_bst_sense" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0xc500, \ + "test_cvi" }, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */ \ + { 0xc510, \ + "test_discrete" }, /* Test function noise measurement , */ \ + { 0xc520, \ + "test_iddq" }, /* Set the power stages in iddq mode for gate stress., */ \ + { 0xc530, \ + "test_rdson" }, /* Analog BIST, switch to enable Rdson measurement , */ \ + { 0xc540, \ + "test_sdelta" }, /* Analog BIST, noise test , */ \ + { 0xc550, \ + "test_enbl_cs" }, /* Enable for digimux mode of current sense , */ \ + { 0xc560, \ + "test_enbl_vs" }, /* Enable for digimux mode of voltage sense , */ \ + { 0xc570, \ + "enbl_pwm_dcc" }, /* Enables direct control of pwm duty cycle for DCDC power stage, */ \ + { 0xc583, \ + "pwm_dcc_cnt" }, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0xc5c0, \ + "enbl_ldo_stress" }, /* Enable stress of internal supply voltages powerstages, */ \ + { 0xc607, \ + "digimuxa_sel" }, /* DigimuxA input selection control routed to DATAO , */ \ + { 0xc687, \ + "digimuxb_sel" }, /* DigimuxB input selection control routed to INT , */ \ + { 0xc707, \ + "digimuxc_sel" }, /* DigimuxC input selection control routed to ADS1 , */ \ + { 0xc800, \ + "enbl_anamux1" }, /* Enable anamux1 , */ \ + { 0xc810, \ + "enbl_anamux2" }, /* Enable anamux2 , */ \ + { 0xc820, \ + "enbl_anamux3" }, /* Enable anamux3 , */ \ + { 0xc830, \ + "enbl_anamux4" }, /* Enable anamux4 , */ \ + { 0xc844, \ + "anamux1" }, /* Anamux selection control - anamux on TEST1 , */ \ + { 0xc894, \ + "anamux2" }, /* Anamux selection control - anamux on TEST2 , */ \ + { 0xc903, \ + "anamux3" }, /* Anamux selection control - anamux on TEST3 , */ \ + { 0xc943, \ + "anamux4" }, /* Anamux selection control - anamux on TEST4 , */ \ + { 0xca05, \ + "pll_seli" }, /* PLL SELI - I2C direct PLL control mode only , */ \ + { 0xca64, \ + "pll_selp" }, /* PLL SELP - I2C direct PLL control mode only , */ \ + { 0xcab3, \ + "pll_selr" }, /* PLL SELR - I2C direct PLL control mode only , */ \ + { 0xcaf0, \ + "pll_frm" }, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */ \ + { 0xcb09, \ + "pll_ndec" }, /* PLL NDEC - I2C direct PLL control mode only , */ \ + { 0xcba0, \ + "pll_mdec_msb" }, /* MSB of PLL_mdec - I2C direct PLL control mode only, */ \ + { 0xcbb0, \ + "enbl_pll" }, /* Enables PLL in I2C direct PLL control mode only , */ \ + { 0xcbc0, \ + "enbl_osc" }, /* Enables OSC1M in I2C direct control mode only , */ \ + { 0xcbd0, \ + "pll_bypass" }, /* PLL bypass control in I2C direct PLL control mode only, */ \ + { 0xcbe0, \ + "pll_directi" }, /* PLL directi control in I2C direct PLL control mode only, */ \ + { 0xcbf0, \ + "pll_directo" }, /* PLL directo control in I2C direct PLL control mode only, */ \ + { 0xcc0f, \ + "pll_mdec_lsb" }, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */ \ + { 0xcd06, \ + "pll_pdec" }, /* PLL PDEC - I2C direct PLL control mode only , */ \ + { 0xce0f, \ + "tsig_freq_lsb" }, /* Internal sinus test generator frequency control , */ \ + { 0xcf02, \ + "tsig_freq_msb" }, /* Select internal sinus test generator, frequency control msb bits, */ \ + { 0xcf33, \ + "tsig_gain" }, /* Test signal gain , */ \ + { 0xd000, \ + "adc10_reset" }, /* Reset for ADC10 - I2C direct control mode , */ \ + { 0xd011, \ + "adc10_test" }, /* Test mode selection signal for ADC10 - I2C direct control mode, */ \ + { 0xd032, \ + "adc10_sel" }, /* Select the input to convert for ADC10 - I2C direct control mode, */ \ + { 0xd064, \ + "adc10_prog_sample" }, /* ADC10 program sample setting - I2C direct control mode, */ \ + { 0xd0b0, \ + "adc10_enbl" }, /* Enable ADC10 - I2C direct control mode , */ \ + { 0xd0c0, \ + "bypass_lp_vbat" }, /* Bypass control for Low pass filter in batt sensor , */ \ + { 0xd109, \ + "data_adc10_tempbat" }, /* ADC 10 data output data for testing , */ \ + { 0xd201, \ + "clkdiv_audio_sel" }, /* Audio clock divider selection in direct clock control mode, */ \ + { 0xd221, \ + "clkdiv_muxa_sel" }, /* DCDC MUXA clock divider selection in direct clock control mode, */ \ + { 0xd241, \ + "clkdiv_muxb_sel" }, /* DCDC MUXB clock divider selection in direct clock control mode, */ \ + { 0xd301, \ + "int_ehs" }, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO datasheet), */ \ + { 0xd321, \ + "datao_ehs" }, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO datasheet), */ \ + { 0xd340, \ + "hs_mode" }, /* I2C high speed mode control , */ \ + { 0xd407, \ + "ctrl_digtoana_hidden" }, /* Spare digital to analog control bits - Hidden , */ \ + { 0xd480, \ + "enbl_clk_out_of_range" }, /* Clock out of range , */ \ + { 0xd491, \ + "sel_wdt_clk" }, /* Watch dog clock divider settings , */ \ + { 0xd4b0, \ + "inject_tsig" }, /* Control bit to switch to internal sinus test generator, */ \ + { 0xd500, \ + "source_in_testmode" }, /* TDM source in test mode (return only current and voltage sense), */ \ + { 0xd510, \ + "gainatt_feedback" }, /* Gainatt feedback to tdm , */ \ + { 0xd522, \ + "test_parametric_io" }, /* Test IO parametric , */ \ + { 0xd550, \ + "ctrl_bst_clk_lp1" }, /* Boost clock control in low power mode1 , */ \ + { 0xd561, \ + "test_spare_out1" }, /* Test spare out 1 , */ \ + { 0xd580, \ + "bst_dcmbst" }, /* DCM boost , */ \ + { 0xd593, \ + "test_spare_out2" }, /* Test spare out 2 , */ \ + { 0xe00f, \ + "sw_profile" }, /* Software profile data , */ \ + { 0xe10f, \ + "sw_vstep" }, /* Software vstep information , */ \ + { 0xf000, \ + "calibration_onetime" }, /* Calibration schedule , */ \ + { 0xf010, \ + "calibr_ron_done" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "calibr_dcdc_api_calibrate" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "calibr_dcdc_delta_sign" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "calibr_dcdc_delta" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "calibr_speaker_info" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf105, \ + "calibr_vout_offset" }, /* DCDC offset calibration 2's complement (key1 protected), */ \ + { 0xf163, \ + "calibr_vbg_trim" }, /* Bandgap trimming control , */ \ + { 0xf203, \ + "calibr_gain" }, /* HW gain module (2's complement) , */ \ + { 0xf245, \ + "calibr_offset" }, /* Offset for amplifier, HW gain module (2's complement), */ \ + { 0xf307, \ + "calibr_gain_vs" }, /* Voltage sense gain , */ \ + { 0xf387, \ + "calibr_gain_cs" }, /* Current sense gain (signed two's complement format), */ \ + { 0xf40f, \ + "mtpdata4" }, /* MTP4 data , */ \ + { 0xf50f, \ + "calibr_R25C" }, /* Ron resistance of speaker coil , */ \ + { 0xf60f, \ + "mtpdata6" }, /* MTP6 data , */ \ + { 0xf706, \ + "ctrl_offset_a" }, /* Offset of level shifter A , */ \ + { 0xf786, \ + "ctrl_offset_b" }, /* Offset of amplifier level shifter B , */ \ + { 0xf806, \ + "htol_iic_addr" }, /* 7-bit I2C address to be used during HTOL testing , */ \ + { 0xf870, \ + "htol_iic_addr_en" }, /* HTOL I2C address enable control , */ \ + { 0xf884, \ + "calibr_temp_offset" }, /* Temperature offset 2's compliment (key1 protected), */ \ + { 0xf8d2, \ + "calibr_temp_gain" }, /* Temperature gain 2's compliment (key1 protected) , */ \ + { 0xf900, \ + "mtp_lock_dcdcoff_mode" }, /* Disable functionality of dcdcoff_mode bit , */ \ + { 0xf910, \ + "mtp_lock_enbl_coolflux" }, /* Disable functionality of enbl_coolflux bit , */ \ + { 0xf920, \ + "mtp_lock_bypass_clipper" }, /* Disable function bypass_clipper , */ \ + { 0xf930, \ + "mtp_enbl_pwm_delay_clock_gating" }, /* PWM delay clock auto gating , */ \ + { 0xf940, \ + "mtp_enbl_ocp_clock_gating" }, /* OCP clock auto gating , */ \ + { 0xf950, \ + "mtp_gate_cgu_clock_for_test" }, /* CGU test clock control , */ \ + { 0xf987, \ + "type_bits_fw" }, /* MTP control for firmware features - See Firmware I2C API document for details, */ \ + { 0xfa0f, \ + "mtpdataA" }, /* MTPdataA , */ \ + { 0xfb0f, \ + "mtpdataB" }, /* MTPdataB , */ \ + { 0xfc0f, \ + "mtpdataC" }, /* MTPdataC , */ \ + { 0xfd0f, \ + "mtpdataD" }, /* MTPdataD , */ \ + { 0xfe0f, \ + "mtpdataE" }, /* MTPdataE , */ \ + { 0xff07, \ + "calibr_osc_delta_ndiv" }, /* Calibration data for OSC1M, signed number representation, */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +enum tfa9894_irq { tfa9894_irq_max = -1, tfa9894_irq_all = -1 /* all irqs */ }; + +#define TFA9894_IRQ_NAMETABLE static tfaIrqName_t Tfa9894IrqNames[] = {}; +#endif /* _TFA9894_TFAFIELDNAMES_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9896_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9896_tfafieldnames.h new file mode 100644 index 000000000000..7d0a6fda5108 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9896_tfafieldnames.h @@ -0,0 +1,1732 @@ +/** Filename: tfa9896_tfafieldnames.h + * This file was generated automatically on 08/15/16 at 09:43:38. + * Source file: TFA9896_N1B1_I2C_regmap_V16.xlsx + */ + +#ifndef _TFA9896_TFAFIELDNAMES_H +#define _TFA9896_TFAFIELDNAMES_H + +#define TFA9896_I2CVERSION 16 + +typedef enum nxpTFA9896BfEnumList { + TFA9896_BF_VDDS = + 0x0000, /*!< Power-on-reset flag (auto clear by reading) */ + TFA9896_BF_PLLS = + 0x0010, /*!< PLL lock to programmed frequency */ + TFA9896_BF_OTDS = + 0x0020, /*!< Over Temperature Protection alarm */ + TFA9896_BF_OVDS = + 0x0030, /*!< Over Voltage Protection alarm */ + TFA9896_BF_UVDS = + 0x0040, /*!< Under Voltage Protection alarm */ + TFA9896_BF_OCDS = + 0x0050, /*!< Over Current Protection alarm */ + TFA9896_BF_CLKS = + 0x0060, /*!< Clocks stable flag */ + TFA9896_BF_CLIPS = + 0x0070, /*!< Amplifier clipping */ + TFA9896_BF_MTPB = + 0x0080, /*!< MTP busy copying data to/from I2C registers */ + TFA9896_BF_NOCLK = + 0x0090, /*!< lost clock detection (reference input clock) */ + TFA9896_BF_SPKS = + 0x00a0, /*!< Speaker error */ + TFA9896_BF_ACS = + 0x00b0, /*!< Cold Start required */ + TFA9896_BF_SWS = + 0x00c0, /*!< Amplifier engage (Amp Switching) */ + TFA9896_BF_WDS = + 0x00d0, /*!< watchdog reset (activates reset) */ + TFA9896_BF_AMPS = + 0x00e0, /*!< Amplifier is enabled by manager */ + TFA9896_BF_AREFS = + 0x00f0, /*!< References are enabled by manager */ + TFA9896_BF_BATS = + 0x0109, /*!< Battery voltage from ADC readout */ + TFA9896_BF_TEMPS = + 0x0208, /*!< Temperature readout from the temperature sensor ( C) */ + TFA9896_BF_REV = + 0x030f, /*!< Device revision information */ + TFA9896_BF_RCV = + 0x0420, /*!< Enable receiver mode */ + TFA9896_BF_CHS12 = + 0x0431, /*!< Channel Selection TDM input for Coolflux */ + TFA9896_BF_INPLVL = + 0x0450, /*!< Input level selection attenuator ( */ + TFA9896_BF_CHSA = + 0x0461, /*!< Input selection for amplifier */ + TFA9896_BF_AUDFS = + 0x04c3, /*!< Audio sample rate setting */ + TFA9896_BF_BSSCR = + 0x0501, /*!< Batteery protection attack time */ + TFA9896_BF_BSST = + 0x0523, /*!< Battery protection threshold level */ + TFA9896_BF_BSSRL = + 0x0561, /*!< Battery protection maximum reduction */ + TFA9896_BF_BSSRR = + 0x0582, /*!< Battery protection release time */ + TFA9896_BF_BSSHY = + 0x05b1, /*!< Battery Protection Hysteresis */ + TFA9896_BF_BSSR = + 0x05e0, /*!< Battery voltage value for read out (only) */ + TFA9896_BF_BSSBY = + 0x05f0, /*!< Bypass clipper battery protection */ + TFA9896_BF_DPSA = + 0x0600, /*!< Enable dynamic powerstage activation (DPSA) */ + TFA9896_BF_ATTEN = + 0x0613, /*!< Gain attenuation setting */ + TFA9896_BF_CFSM = + 0x0650, /*!< Soft mute in CoolFlux */ + TFA9896_BF_BSSS = + 0x0670, /*!< Battery sense steepness */ + TFA9896_BF_VOL = + 0x0687, /*!< Coolflux volume control */ + TFA9896_BF_DCVO2 = + 0x0702, /*!< Second Boost Voltage */ + TFA9896_BF_DCMCC = + 0x0733, /*!< Max boost coil current - step of 175 mA */ + TFA9896_BF_DCVO1 = + 0x0772, /*!< First Boost Voltage */ + TFA9896_BF_DCIE = + 0x07a0, /*!< Adaptive boost mode */ + TFA9896_BF_DCSR = + 0x07b0, /*!< Soft Rampup/down mode for DCDC controller */ + TFA9896_BF_DCPAVG = + 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */ + TFA9896_BF_DCPWM = + 0x07d0, /*!< DCDC PWM only mode */ + TFA9896_BF_TROS = + 0x0800, /*!< Selection ambient temperature for speaker calibration */ + TFA9896_BF_EXTTS = + 0x0818, /*!< External temperature for speaker calibration (C) */ + TFA9896_BF_PWDN = + 0x0900, /*!< powerdown selection */ + TFA9896_BF_I2CR = + 0x0910, /*!< All I2C registers reset to default */ + TFA9896_BF_CFE = + 0x0920, /*!< Enable CoolFlux */ + TFA9896_BF_AMPE = + 0x0930, /*!< Enable Amplifier */ + TFA9896_BF_DCA = + 0x0940, /*!< Enable DCDC Boost converter */ + TFA9896_BF_SBSL = + 0x0950, /*!< Coolflux configured */ + TFA9896_BF_AMPC = + 0x0960, /*!< Selection if Coolflux enables amplifier */ + TFA9896_BF_DCDIS = + 0x0970, /*!< DCDC boost converter not connected */ + TFA9896_BF_PSDR = + 0x0980, /*!< IDDQ amplifier test selection */ + TFA9896_BF_INTPAD = + 0x09c1, /*!< INT pad (interrupt bump output) configuration */ + TFA9896_BF_IPLL = + 0x09e0, /*!< PLL input reference clock selection */ + TFA9896_BF_DCTRIP = + 0x0a04, /*!< Adaptive boost trip levels (effective only when boost_intel is set to 1) */ + TFA9896_BF_DCHOLD = + 0x0a54, /*!< Hold time for DCDC booster (effective only when boost_intel is set to 1) */ + TFA9896_BF_MTPK = + 0x0b07, /*!< KEY2 to access key2 protected registers (default for engineering) */ + TFA9896_BF_CVFDLY = + 0x0c25, /*!< Fractional delay adjustment between current and voltage sense */ + TFA9896_BF_OPENMTP = + 0x0ec0, /*!< Enable programming of the MTP memory */ + TFA9896_BF_TDMPRF = + 0x1011, /*!< TDM usecase selection control */ + TFA9896_BF_TDMEN = + 0x1030, /*!< TDM interface enable */ + TFA9896_BF_TDMCKINV = + 0x1040, /*!< TDM clock inversion, receive on */ + TFA9896_BF_TDMFSLN = + 0x1053, /*!< TDM FS length */ + TFA9896_BF_TDMFSPOL = + 0x1090, /*!< TDM FS polarity (start frame) */ + TFA9896_BF_TDMSAMSZ = + 0x10a4, /*!< TDM sample size for all TDM sinks and sources */ + TFA9896_BF_TDMSLOTS = + 0x1103, /*!< TDM number of slots */ + TFA9896_BF_TDMSLLN = + 0x1144, /*!< TDM slot length */ + TFA9896_BF_TDMBRMG = + 0x1194, /*!< TDM bits remaining after the last slot */ + TFA9896_BF_TDMDDEL = + 0x11e0, /*!< TDM data delay */ + TFA9896_BF_TDMDADJ = + 0x11f0, /*!< TDM data adjustment */ + TFA9896_BF_TDMTXFRM = + 0x1201, /*!< TDM TXDATA format */ + TFA9896_BF_TDMUUS0 = + 0x1221, /*!< TDM TXDATA format unused slot SD0 */ + TFA9896_BF_TDMUUS1 = + 0x1241, /*!< TDM TXDATA format unused slot SD1 */ + TFA9896_BF_TDMSI0EN = + 0x1270, /*!< TDM sink0 enable */ + TFA9896_BF_TDMSI1EN = + 0x1280, /*!< TDM sink1 enable */ + TFA9896_BF_TDMSI2EN = + 0x1290, /*!< TDM sink2 enable */ + TFA9896_BF_TDMSO0EN = + 0x12a0, /*!< TDM source0 enable */ + TFA9896_BF_TDMSO1EN = + 0x12b0, /*!< TDM source1 enable */ + TFA9896_BF_TDMSO2EN = + 0x12c0, /*!< TDM source2 enable */ + TFA9896_BF_TDMSI0IO = + 0x12d0, /*!< TDM sink0 IO selection */ + TFA9896_BF_TDMSI1IO = + 0x12e0, /*!< TDM sink1 IO selection */ + TFA9896_BF_TDMSI2IO = + 0x12f0, /*!< TDM sink2 IO selection */ + TFA9896_BF_TDMSO0IO = + 0x1300, /*!< TDM source0 IO selection */ + TFA9896_BF_TDMSO1IO = + 0x1310, /*!< TDM source1 IO selection */ + TFA9896_BF_TDMSO2IO = + 0x1320, /*!< TDM source2 IO selection */ + TFA9896_BF_TDMSI0SL = + 0x1333, /*!< TDM sink0 slot position [GAIN IN] */ + TFA9896_BF_TDMSI1SL = + 0x1373, /*!< TDM sink1 slot position [CH1 IN] */ + TFA9896_BF_TDMSI2SL = + 0x13b3, /*!< TDM sink2 slot position [CH2 IN] */ + TFA9896_BF_TDMSO0SL = + 0x1403, /*!< TDM source0 slot position [GAIN OUT] */ + TFA9896_BF_TDMSO1SL = + 0x1443, /*!< TDM source1 slot position [Voltage Sense] */ + TFA9896_BF_TDMSO2SL = + 0x1483, /*!< TDM source2 slot position [Current Sense] */ + TFA9896_BF_NBCK = + 0x14c3, /*!< TDM NBCK bit clock ratio */ + TFA9896_BF_INTOVDDS = + 0x2000, /*!< flag_por_int_out */ + TFA9896_BF_INTOPLLS = + 0x2010, /*!< flag_pll_lock_int_out */ + TFA9896_BF_INTOOTDS = + 0x2020, /*!< flag_otpok_int_out */ + TFA9896_BF_INTOOVDS = + 0x2030, /*!< flag_ovpok_int_out */ + TFA9896_BF_INTOUVDS = + 0x2040, /*!< flag_uvpok_int_out */ + TFA9896_BF_INTOOCDS = + 0x2050, /*!< flag_ocp_alarm_int_out */ + TFA9896_BF_INTOCLKS = + 0x2060, /*!< flag_clocks_stable_int_out */ + TFA9896_BF_INTOCLIPS = + 0x2070, /*!< flag_clip_int_out */ + TFA9896_BF_INTOMTPB = + 0x2080, /*!< mtp_busy_int_out */ + TFA9896_BF_INTONOCLK = + 0x2090, /*!< flag_lost_clk_int_out */ + TFA9896_BF_INTOSPKS = + 0x20a0, /*!< flag_cf_speakererror_int_out */ + TFA9896_BF_INTOACS = + 0x20b0, /*!< flag_cold_started_int_out */ + TFA9896_BF_INTOSWS = + 0x20c0, /*!< flag_engage_int_out */ + TFA9896_BF_INTOWDS = + 0x20d0, /*!< flag_watchdog_reset_int_out */ + TFA9896_BF_INTOAMPS = + 0x20e0, /*!< flag_enbl_amp_int_out */ + TFA9896_BF_INTOAREFS = + 0x20f0, /*!< flag_enbl_ref_int_out */ + TFA9896_BF_INTOERR = + 0x2200, /*!< flag_cfma_err_int_out */ + TFA9896_BF_INTOACK = + 0x2210, /*!< flag_cfma_ack_int_out */ + TFA9896_BF_INTIVDDS = + 0x2300, /*!< flag_por_int_in */ + TFA9896_BF_INTIPLLS = + 0x2310, /*!< flag_pll_lock_int_in */ + TFA9896_BF_INTIOTDS = + 0x2320, /*!< flag_otpok_int_in */ + TFA9896_BF_INTIOVDS = + 0x2330, /*!< flag_ovpok_int_in */ + TFA9896_BF_INTIUVDS = + 0x2340, /*!< flag_uvpok_int_in */ + TFA9896_BF_INTIOCDS = + 0x2350, /*!< flag_ocp_alarm_int_in */ + TFA9896_BF_INTICLKS = + 0x2360, /*!< flag_clocks_stable_int_in */ + TFA9896_BF_INTICLIPS = + 0x2370, /*!< flag_clip_int_in */ + TFA9896_BF_INTIMTPB = + 0x2380, /*!< mtp_busy_int_in */ + TFA9896_BF_INTINOCLK = + 0x2390, /*!< flag_lost_clk_int_in */ + TFA9896_BF_INTISPKS = + 0x23a0, /*!< flag_cf_speakererror_int_in */ + TFA9896_BF_INTIACS = + 0x23b0, /*!< flag_cold_started_int_in */ + TFA9896_BF_INTISWS = + 0x23c0, /*!< flag_engage_int_in */ + TFA9896_BF_INTIWDS = + 0x23d0, /*!< flag_watchdog_reset_int_in */ + TFA9896_BF_INTIAMPS = + 0x23e0, /*!< flag_enbl_amp_int_in */ + TFA9896_BF_INTIAREFS = + 0x23f0, /*!< flag_enbl_ref_int_in */ + TFA9896_BF_INTIERR = + 0x2500, /*!< flag_cfma_err_int_in */ + TFA9896_BF_INTIACK = + 0x2510, /*!< flag_cfma_ack_int_in */ + TFA9896_BF_INTENVDDS = + 0x2600, /*!< flag_por_int_enable */ + TFA9896_BF_INTENPLLS = + 0x2610, /*!< flag_pll_lock_int_enable */ + TFA9896_BF_INTENOTDS = + 0x2620, /*!< flag_otpok_int_enable */ + TFA9896_BF_INTENOVDS = + 0x2630, /*!< flag_ovpok_int_enable */ + TFA9896_BF_INTENUVDS = + 0x2640, /*!< flag_uvpok_int_enable */ + TFA9896_BF_INTENOCDS = + 0x2650, /*!< flag_ocp_alarm_int_enable */ + TFA9896_BF_INTENCLKS = + 0x2660, /*!< flag_clocks_stable_int_enable */ + TFA9896_BF_INTENCLIPS = + 0x2670, /*!< flag_clip_int_enable */ + TFA9896_BF_INTENMTPB = + 0x2680, /*!< mtp_busy_int_enable */ + TFA9896_BF_INTENNOCLK = + 0x2690, /*!< flag_lost_clk_int_enable */ + TFA9896_BF_INTENSPKS = + 0x26a0, /*!< flag_cf_speakererror_int_enable */ + TFA9896_BF_INTENACS = + 0x26b0, /*!< flag_cold_started_int_enable */ + TFA9896_BF_INTENSWS = + 0x26c0, /*!< flag_engage_int_enable */ + TFA9896_BF_INTENWDS = + 0x26d0, /*!< flag_watchdog_reset_int_enable */ + TFA9896_BF_INTENAMPS = + 0x26e0, /*!< flag_enbl_amp_int_enable */ + TFA9896_BF_INTENAREFS = + 0x26f0, /*!< flag_enbl_ref_int_enable */ + TFA9896_BF_INTENERR = + 0x2800, /*!< flag_cfma_err_int_enable */ + TFA9896_BF_INTENACK = + 0x2810, /*!< flag_cfma_ack_int_enable */ + TFA9896_BF_INTPOLVDDS = + 0x2900, /*!< flag_por_int_pol */ + TFA9896_BF_INTPOLPLLS = + 0x2910, /*!< flag_pll_lock_int_pol */ + TFA9896_BF_INTPOLOTDS = + 0x2920, /*!< flag_otpok_int_pol */ + TFA9896_BF_INTPOLOVDS = + 0x2930, /*!< flag_ovpok_int_pol */ + TFA9896_BF_INTPOLUVDS = + 0x2940, /*!< flag_uvpok_int_pol */ + TFA9896_BF_INTPOLOCDS = + 0x2950, /*!< flag_ocp_alarm_int_pol */ + TFA9896_BF_INTPOLCLKS = + 0x2960, /*!< flag_clocks_stable_int_pol */ + TFA9896_BF_INTPOLCLIPS = + 0x2970, /*!< flag_clip_int_pol */ + TFA9896_BF_INTPOLMTPB = + 0x2980, /*!< mtp_busy_int_pol */ + TFA9896_BF_INTPOLNOCLK = + 0x2990, /*!< flag_lost_clk_int_pol */ + TFA9896_BF_INTPOLSPKS = + 0x29a0, /*!< flag_cf_speakererror_int_pol */ + TFA9896_BF_INTPOLACS = + 0x29b0, /*!< flag_cold_started_int_pol */ + TFA9896_BF_INTPOLSWS = + 0x29c0, /*!< flag_engage_int_pol */ + TFA9896_BF_INTPOLWDS = + 0x29d0, /*!< flag_watchdog_reset_int_pol */ + TFA9896_BF_INTPOLAMPS = + 0x29e0, /*!< flag_enbl_amp_int_pol */ + TFA9896_BF_INTPOLAREFS = + 0x29f0, /*!< flag_enbl_ref_int_pol */ + TFA9896_BF_INTPOLERR = + 0x2b00, /*!< flag_cfma_err_int_pol */ + TFA9896_BF_INTPOLACK = + 0x2b10, /*!< flag_cfma_ack_int_pol */ + TFA9896_BF_CLIP = + 0x4900, /*!< Bypass clip control */ + TFA9896_BF_CIMTP = + 0x62b0, /*!< Start copying data from I2C mtp registers to mtp */ + TFA9896_BF_RST = + 0x7000, /*!< Reset CoolFlux DSP */ + TFA9896_BF_DMEM = + 0x7011, /*!< Target memory for access */ + TFA9896_BF_AIF = + 0x7030, /*!< Auto increment flag for memory-address */ + TFA9896_BF_CFINT = + 0x7040, /*!< CF Interrupt - auto clear */ + TFA9896_BF_REQ = + 0x7087, /*!< CF request for accessing the 8 channels */ + TFA9896_BF_MADD = + 0x710f, /*!< Memory address */ + TFA9896_BF_MEMA = + 0x720f, /*!< Activate memory access */ + TFA9896_BF_ERR = + 0x7307, /*!< CF error flags */ + TFA9896_BF_ACK = + 0x7387, /*!< CF acknowledgement of the requests channels */ + TFA9896_BF_MTPOTC = + 0x8000, /*!< Calibration schedule selection */ + TFA9896_BF_MTPEX = + 0x8010, /*!< Calibration of RON status bit */ +} nxpTFA9896BfEnumList_t; +#define TFA9896_NAMETABLE \ + static tfaBfName_t Tfa9896DatasheetNames[] = { \ + { 0x0, \ + "VDDS" }, /* Power-on-reset flag (auto clear by reading) , */ \ + { 0x10, \ + "PLLS" }, /* PLL lock to programmed frequency , */ \ + { 0x20, \ + "OTDS" }, /* Over Temperature Protection alarm , */ \ + { 0x30, \ + "OVDS" }, /* Over Voltage Protection alarm , */ \ + { 0x40, \ + "UVDS" }, /* Under Voltage Protection alarm , */ \ + { 0x50, \ + "OCDS" }, /* Over Current Protection alarm , */ \ + { 0x60, \ + "CLKS" }, /* Clocks stable flag , */ \ + { 0x70, \ + "CLIPS" }, /* Amplifier clipping , */ \ + { 0x80, \ + "MTPB" }, /* MTP busy copying data to/from I2C registers , */ \ + { 0x90, \ + "NOCLK" }, /* lost clock detection (reference input clock) , */ \ + { 0xa0, \ + "SPKS" }, /* Speaker error , */ \ + { 0xb0, \ + "ACS" }, /* Cold Start required , */ \ + { 0xc0, \ + "SWS" }, /* Amplifier engage (Amp Switching) , */ \ + { 0xd0, \ + "WDS" }, /* watchdog reset (activates reset) , */ \ + { 0xe0, \ + "AMPS" }, /* Amplifier is enabled by manager , */ \ + { 0xf0, \ + "AREFS" }, /* References are enabled by manager , */ \ + { 0x109, \ + "BATS" }, /* Battery voltage from ADC readout , */ \ + { 0x208, \ + "TEMPS" }, /* Temperature readout from the temperature sensor ( C), */ \ + { 0x30f, \ + "REV" }, /* Device revision information , */ \ + { 0x420, \ + "RCV" }, /* Enable receiver mode , */ \ + { 0x431, \ + "CHS12" }, /* Channel Selection TDM input for Coolflux , */ \ + { 0x450, \ + "INPLVL" }, /* Input level selection attenuator ( , */ \ + { 0x461, \ + "CHSA" }, /* Input selection for amplifier , */ \ + { 0x4c3, \ + "AUDFS" }, /* Audio sample rate setting , */ \ + { 0x501, \ + "BSSCR" }, /* Batteery protection attack time , */ \ + { 0x523, \ + "BSST" }, /* Battery protection threshold level , */ \ + { 0x561, \ + "BSSRL" }, /* Battery protection maximum reduction , */ \ + { 0x582, \ + "BSSRR" }, /* Battery protection release time , */ \ + { 0x5b1, \ + "BSSHY" }, /* Battery Protection Hysteresis , */ \ + { 0x5e0, \ + "BSSR" }, /* Battery voltage value for read out (only) , */ \ + { 0x5f0, \ + "BSSBY" }, /* Bypass clipper battery protection , */ \ + { 0x600, \ + "DPSA" }, /* Enable dynamic powerstage activation (DPSA) , */ \ + { 0x613, \ + "ATTEN" }, /* Gain attenuation setting , */ \ + { 0x650, \ + "CFSM" }, /* Soft mute in CoolFlux , */ \ + { 0x670, \ + "BSSS" }, /* Battery sense steepness , */ \ + { 0x687, \ + "VOL" }, /* Coolflux volume control , */ \ + { 0x702, \ + "DCVO2" }, /* Second Boost Voltage , */ \ + { 0x733, \ + "DCMCC" }, /* Max boost coil current - step of 175 mA , */ \ + { 0x772, \ + "DCVO1" }, /* First Boost Voltage , */ \ + { 0x7a0, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x7b0, \ + "DCSR" }, /* Soft Rampup/down mode for DCDC controller , */ \ + { 0x7c0, \ + "DCPAVG" }, /* ctrl_peak2avg for analog part of DCDC , */ \ + { 0x7d0, \ + "DCPWM" }, /* DCDC PWM only mode , */ \ + { 0x800, \ + "TROS" }, /* Selection ambient temperature for speaker calibration , */ \ + { 0x818, \ + "EXTTS" }, /* External temperature for speaker calibration (C) , */ \ + { 0x900, \ + "PWDN" }, /* powerdown selection , */ \ + { 0x910, \ + "I2CR" }, /* All I2C registers reset to default , */ \ + { 0x920, \ + "CFE" }, /* Enable CoolFlux , */ \ + { 0x930, \ + "AMPE" }, /* Enable Amplifier , */ \ + { 0x940, \ + "DCA" }, /* Enable DCDC Boost converter , */ \ + { 0x950, \ + "SBSL" }, /* Coolflux configured , */ \ + { 0x960, \ + "AMPC" }, /* Selection if Coolflux enables amplifier , */ \ + { 0x970, \ + "DCDIS" }, /* DCDC boost converter not connected , */ \ + { 0x980, \ + "PSDR" }, /* IDDQ amplifier test selection , */ \ + { 0x9c1, \ + "INTPAD" }, /* INT pad (interrupt bump output) configuration , */ \ + { 0x9e0, \ + "IPLL" }, /* PLL input reference clock selection , */ \ + { 0xa04, \ + "DCTRIP" }, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */ \ + { 0xa54, \ + "DCHOLD" }, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */ \ + { 0xb07, \ + "MTPK" }, /* KEY2 to access key2 protected registers (default for engineering), */ \ + { 0xc25, \ + "CVFDLY" }, /* Fractional delay adjustment between current and voltage sense, */ \ + { 0xec0, \ + "OPENMTP" }, /* Enable programming of the MTP memory , */ \ + { 0x1011, \ + "TDMPRF" }, /* TDM usecase selection control , */ \ + { 0x1030, \ + "TDMEN" }, /* TDM interface enable , */ \ + { 0x1040, \ + "TDMCKINV" }, /* TDM clock inversion, receive on , */ \ + { 0x1053, \ + "TDMFSLN" }, /* TDM FS length , */ \ + { 0x1090, \ + "TDMFSPOL" }, /* TDM FS polarity (start frame) , */ \ + { 0x10a4, \ + "TDMSAMSZ" }, /* TDM sample size for all TDM sinks and sources , */ \ + { 0x1103, \ + "TDMSLOTS" }, /* TDM number of slots , */ \ + { 0x1144, \ + "TDMSLLN" }, /* TDM slot length , */ \ + { 0x1194, \ + "TDMBRMG" }, /* TDM bits remaining after the last slot , */ \ + { 0x11e0, \ + "TDMDDEL" }, /* TDM data delay , */ \ + { 0x11f0, \ + "TDMDADJ" }, /* TDM data adjustment , */ \ + { 0x1201, \ + "TDMTXFRM" }, /* TDM TXDATA format , */ \ + { 0x1221, \ + "TDMUUS0" }, /* TDM TXDATA format unused slot SD0 , */ \ + { 0x1241, \ + "TDMUUS1" }, /* TDM TXDATA format unused slot SD1 , */ \ + { 0x1270, \ + "TDMSI0EN" }, /* TDM sink0 enable , */ \ + { 0x1280, \ + "TDMSI1EN" }, /* TDM sink1 enable , */ \ + { 0x1290, \ + "TDMSI2EN" }, /* TDM sink2 enable , */ \ + { 0x12a0, \ + "TDMSO0EN" }, /* TDM source0 enable , */ \ + { 0x12b0, \ + "TDMSO1EN" }, /* TDM source1 enable , */ \ + { 0x12c0, \ + "TDMSO2EN" }, /* TDM source2 enable , */ \ + { 0x12d0, \ + "TDMSI0IO" }, /* TDM sink0 IO selection , */ \ + { 0x12e0, \ + "TDMSI1IO" }, /* TDM sink1 IO selection , */ \ + { 0x12f0, \ + "TDMSI2IO" }, /* TDM sink2 IO selection , */ \ + { 0x1300, \ + "TDMSO0IO" }, /* TDM source0 IO selection , */ \ + { 0x1310, \ + "TDMSO1IO" }, /* TDM source1 IO selection , */ \ + { 0x1320, \ + "TDMSO2IO" }, /* TDM source2 IO selection , */ \ + { 0x1333, \ + "TDMSI0SL" }, /* TDM sink0 slot position [GAIN IN] , */ \ + { 0x1373, \ + "TDMSI1SL" }, /* TDM sink1 slot position [CH1 IN] , */ \ + { 0x13b3, \ + "TDMSI2SL" }, /* TDM sink2 slot position [CH2 IN] , */ \ + { 0x1403, \ + "TDMSO0SL" }, /* TDM source0 slot position [GAIN OUT] , */ \ + { 0x1443, \ + "TDMSO1SL" }, /* TDM source1 slot position [Voltage Sense] , */ \ + { 0x1483, \ + "TDMSO2SL" }, /* TDM source2 slot position [Current Sense] , */ \ + { 0x14c3, \ + "NBCK" }, /* TDM NBCK bit clock ratio , */ \ + { 0x2000, \ + "INTOVDDS" }, /* flag_por_int_out , */ \ + { 0x2010, \ + "INTOPLLS" }, /* flag_pll_lock_int_out , */ \ + { 0x2020, \ + "INTOOTDS" }, /* flag_otpok_int_out , */ \ + { 0x2030, \ + "INTOOVDS" }, /* flag_ovpok_int_out , */ \ + { 0x2040, \ + "INTOUVDS" }, /* flag_uvpok_int_out , */ \ + { 0x2050, \ + "INTOOCDS" }, /* flag_ocp_alarm_int_out , */ \ + { 0x2060, \ + "INTOCLKS" }, /* flag_clocks_stable_int_out , */ \ + { 0x2070, \ + "INTOCLIPS" }, /* flag_clip_int_out , */ \ + { 0x2080, \ + "INTOMTPB" }, /* mtp_busy_int_out , */ \ + { 0x2090, \ + "INTONOCLK" }, /* flag_lost_clk_int_out , */ \ + { 0x20a0, \ + "INTOSPKS" }, /* flag_cf_speakererror_int_out , */ \ + { 0x20b0, \ + "INTOACS" }, /* flag_cold_started_int_out , */ \ + { 0x20c0, \ + "INTOSWS" }, /* flag_engage_int_out , */ \ + { 0x20d0, \ + "INTOWDS" }, /* flag_watchdog_reset_int_out , */ \ + { 0x20e0, \ + "INTOAMPS" }, /* flag_enbl_amp_int_out , */ \ + { 0x20f0, \ + "INTOAREFS" }, /* flag_enbl_ref_int_out , */ \ + { 0x2200, \ + "INTOERR" }, /* flag_cfma_err_int_out , */ \ + { 0x2210, \ + "INTOACK" }, /* flag_cfma_ack_int_out , */ \ + { 0x2300, \ + "INTIVDDS" }, /* flag_por_int_in , */ \ + { 0x2310, \ + "INTIPLLS" }, /* flag_pll_lock_int_in , */ \ + { 0x2320, \ + "INTIOTDS" }, /* flag_otpok_int_in , */ \ + { 0x2330, \ + "INTIOVDS" }, /* flag_ovpok_int_in , */ \ + { 0x2340, \ + "INTIUVDS" }, /* flag_uvpok_int_in , */ \ + { 0x2350, \ + "INTIOCDS" }, /* flag_ocp_alarm_int_in , */ \ + { 0x2360, \ + "INTICLKS" }, /* flag_clocks_stable_int_in , */ \ + { 0x2370, \ + "INTICLIPS" }, /* flag_clip_int_in , */ \ + { 0x2380, \ + "INTIMTPB" }, /* mtp_busy_int_in , */ \ + { 0x2390, \ + "INTINOCLK" }, /* flag_lost_clk_int_in , */ \ + { 0x23a0, \ + "INTISPKS" }, /* flag_cf_speakererror_int_in , */ \ + { 0x23b0, \ + "INTIACS" }, /* flag_cold_started_int_in , */ \ + { 0x23c0, \ + "INTISWS" }, /* flag_engage_int_in , */ \ + { 0x23d0, \ + "INTIWDS" }, /* flag_watchdog_reset_int_in , */ \ + { 0x23e0, \ + "INTIAMPS" }, /* flag_enbl_amp_int_in , */ \ + { 0x23f0, \ + "INTIAREFS" }, /* flag_enbl_ref_int_in , */ \ + { 0x2500, \ + "INTIERR" }, /* flag_cfma_err_int_in , */ \ + { 0x2510, \ + "INTIACK" }, /* flag_cfma_ack_int_in , */ \ + { 0x2600, \ + "INTENVDDS" }, /* flag_por_int_enable , */ \ + { 0x2610, \ + "INTENPLLS" }, /* flag_pll_lock_int_enable , */ \ + { 0x2620, \ + "INTENOTDS" }, /* flag_otpok_int_enable , */ \ + { 0x2630, \ + "INTENOVDS" }, /* flag_ovpok_int_enable , */ \ + { 0x2640, \ + "INTENUVDS" }, /* flag_uvpok_int_enable , */ \ + { 0x2650, \ + "INTENOCDS" }, /* flag_ocp_alarm_int_enable , */ \ + { 0x2660, \ + "INTENCLKS" }, /* flag_clocks_stable_int_enable , */ \ + { 0x2670, \ + "INTENCLIPS" }, /* flag_clip_int_enable , */ \ + { 0x2680, \ + "INTENMTPB" }, /* mtp_busy_int_enable , */ \ + { 0x2690, \ + "INTENNOCLK" }, /* flag_lost_clk_int_enable , */ \ + { 0x26a0, \ + "INTENSPKS" }, /* flag_cf_speakererror_int_enable , */ \ + { 0x26b0, \ + "INTENACS" }, /* flag_cold_started_int_enable , */ \ + { 0x26c0, \ + "INTENSWS" }, /* flag_engage_int_enable , */ \ + { 0x26d0, \ + "INTENWDS" }, /* flag_watchdog_reset_int_enable , */ \ + { 0x26e0, \ + "INTENAMPS" }, /* flag_enbl_amp_int_enable , */ \ + { 0x26f0, \ + "INTENAREFS" }, /* flag_enbl_ref_int_enable , */ \ + { 0x2800, \ + "INTENERR" }, /* flag_cfma_err_int_enable , */ \ + { 0x2810, \ + "INTENACK" }, /* flag_cfma_ack_int_enable , */ \ + { 0x2900, \ + "INTPOLVDDS" }, /* flag_por_int_pol , */ \ + { 0x2910, \ + "INTPOLPLLS" }, /* flag_pll_lock_int_pol , */ \ + { 0x2920, \ + "INTPOLOTDS" }, /* flag_otpok_int_pol , */ \ + { 0x2930, \ + "INTPOLOVDS" }, /* flag_ovpok_int_pol , */ \ + { 0x2940, \ + "INTPOLUVDS" }, /* flag_uvpok_int_pol , */ \ + { 0x2950, \ + "INTPOLOCDS" }, /* flag_ocp_alarm_int_pol , */ \ + { 0x2960, \ + "INTPOLCLKS" }, /* flag_clocks_stable_int_pol , */ \ + { 0x2970, \ + "INTPOLCLIPS" }, /* flag_clip_int_pol , */ \ + { 0x2980, \ + "INTPOLMTPB" }, /* mtp_busy_int_pol , */ \ + { 0x2990, \ + "INTPOLNOCLK" }, /* flag_lost_clk_int_pol , */ \ + { 0x29a0, \ + "INTPOLSPKS" }, /* flag_cf_speakererror_int_pol , */ \ + { 0x29b0, \ + "INTPOLACS" }, /* flag_cold_started_int_pol , */ \ + { 0x29c0, \ + "INTPOLSWS" }, /* flag_engage_int_pol , */ \ + { 0x29d0, \ + "INTPOLWDS" }, /* flag_watchdog_reset_int_pol , */ \ + { 0x29e0, \ + "INTPOLAMPS" }, /* flag_enbl_amp_int_pol , */ \ + { 0x29f0, \ + "INTPOLAREFS" }, /* flag_enbl_ref_int_pol , */ \ + { 0x2b00, \ + "INTPOLERR" }, /* flag_cfma_err_int_pol , */ \ + { 0x2b10, \ + "INTPOLACK" }, /* flag_cfma_ack_int_pol , */ \ + { 0x4900, \ + "CLIP" }, /* Bypass clip control , */ \ + { 0x62b0, \ + "CIMTP" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0x7000, \ + "RST" }, /* Reset CoolFlux DSP , */ \ + { 0x7011, \ + "DMEM" }, /* Target memory for access , */ \ + { 0x7030, \ + "AIF" }, /* Auto increment flag for memory-address , */ \ + { 0x7040, \ + "CFINT" }, /* CF Interrupt - auto clear , */ \ + { 0x7087, \ + "REQ" }, /* CF request for accessing the 8 channels , */ \ + { 0x710f, \ + "MADD" }, /* Memory address , */ \ + { 0x720f, \ + "MEMA" }, /* Activate memory access , */ \ + { 0x7307, \ + "ERR" }, /* CF error flags , */ \ + { 0x7387, \ + "ACK" }, /* CF acknowledgement of the requests channels , */ \ + { 0x8000, \ + "MTPOTC" }, /* Calibration schedule selection , */ \ + { 0x8010, \ + "MTPEX" }, /* Calibration of RON status bit , */ \ + { 0x8045, "SWPROFIL" }, \ + { 0x80a5, "SWVSTEP" }, \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9896_BITNAMETABLE \ + static tfaBfName_t Tfa9896BitNames[] = { \ + { 0x0, \ + "flag_por" }, /* Power-on-reset flag (auto clear by reading) , */ \ + { 0x10, \ + "flag_pll_lock" }, /* PLL lock to programmed frequency , */ \ + { 0x20, \ + "flag_otpok" }, /* Over Temperature Protection alarm , */ \ + { 0x30, \ + "flag_ovpok" }, /* Over Voltage Protection alarm , */ \ + { 0x40, \ + "flag_uvpok" }, /* Under Voltage Protection alarm , */ \ + { 0x50, \ + "flag_ocp_alarm" }, /* Over Current Protection alarm , */ \ + { 0x60, \ + "flag_clocks_stable" }, /* Clocks stable flag , */ \ + { 0x70, \ + "flag_clip" }, /* Amplifier clipping , */ \ + { 0x80, \ + "mtp_busy" }, /* MTP busy copying data to/from I2C registers , */ \ + { 0x90, \ + "flag_lost_clk" }, /* lost clock detection (reference input clock) , */ \ + { 0xa0, \ + "flag_cf_speakererror" }, /* Speaker error , */ \ + { 0xb0, \ + "flag_cold_started" }, /* Cold Start required , */ \ + { 0xc0, \ + "flag_engage" }, /* Amplifier engage (Amp Switching) , */ \ + { 0xd0, \ + "flag_watchdog_reset" }, /* watchdog reset (activates reset) , */ \ + { 0xe0, \ + "flag_enbl_amp" }, /* Amplifier is enabled by manager , */ \ + { 0xf0, \ + "flag_enbl_ref" }, /* References are enabled by manager , */ \ + { 0x109, \ + "bat_adc" }, /* Battery voltage from ADC readout , */ \ + { 0x208, \ + "temp_adc" }, /* Temperature readout from the temperature sensor ( C), */ \ + { 0x30f, \ + "device_rev" }, /* Device revision information , */ \ + { 0x420, \ + "ctrl_rcv" }, /* Enable receiver mode , */ \ + { 0x431, \ + "chan_sel" }, /* Channel Selection TDM input for Coolflux , */ \ + { 0x450, \ + "input_level" }, /* Input level selection attenuator ( , */ \ + { 0x461, \ + "vamp_sel" }, /* Input selection for amplifier , */ \ + { 0x4c3, \ + "audio_fs" }, /* Audio sample rate setting , */ \ + { 0x501, \ + "vbat_prot_attacktime" }, /* Batteery protection attack time , */ \ + { 0x523, \ + "vbat_prot_thlevel" }, /* Battery protection threshold level , */ \ + { 0x561, \ + "vbat_prot_max_reduct" }, /* Battery protection maximum reduction , */ \ + { 0x582, \ + "vbat_prot_release_t" }, /* Battery protection release time , */ \ + { 0x5b1, \ + "vbat_prot_hysterese" }, /* Battery Protection Hysteresis , */ \ + { 0x5d0, \ + "reset_min_vbat" }, /* Battery supply safeguard clipper reset ( if CF_DSP is bypassed), */ \ + { 0x5e0, \ + "sel_vbat" }, /* Battery voltage value for read out (only) , */ \ + { 0x5f0, \ + "bypass_clipper" }, /* Bypass clipper battery protection , */ \ + { 0x600, \ + "dpsa" }, /* Enable dynamic powerstage activation (DPSA) , */ \ + { 0x613, \ + "ctrl_att" }, /* Gain attenuation setting , */ \ + { 0x650, \ + "cf_mute" }, /* Soft mute in CoolFlux , */ \ + { 0x670, \ + "batsense_steepness" }, /* Battery sense steepness , */ \ + { 0x687, \ + "vol" }, /* Coolflux volume control , */ \ + { 0x702, \ + "scnd_boost_voltage" }, /* Second Boost Voltage , */ \ + { 0x733, \ + "boost_cur" }, /* Max boost coil current - step of 175 mA , */ \ + { 0x772, \ + "frst_boost_voltage" }, /* First Boost Voltage , */ \ + { 0x7a0, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x7b0, \ + "boost_speed" }, /* Soft Rampup/down mode for DCDC controller , */ \ + { 0x7c0, \ + "boost_peak2avg" }, /* ctrl_peak2avg for analog part of DCDC , */ \ + { 0x7d0, \ + "dcdc_pwmonly" }, /* DCDC PWM only mode , */ \ + { 0x7e0, \ + "ignore_flag_voutcomp86" }, /* Ignore flag_voutcomp86 (flag from analog) , */ \ + { 0x800, \ + "ext_temp_sel" }, /* Selection ambient temperature for speaker calibration , */ \ + { 0x818, \ + "ext_temp" }, /* External temperature for speaker calibration (C) , */ \ + { 0x900, \ + "powerdown" }, /* powerdown selection , */ \ + { 0x910, \ + "reset" }, /* All I2C registers reset to default , */ \ + { 0x920, \ + "enbl_coolflux" }, /* Enable CoolFlux , */ \ + { 0x930, \ + "enbl_amplifier" }, /* Enable Amplifier , */ \ + { 0x940, \ + "enbl_boost" }, /* Enable DCDC Boost converter , */ \ + { 0x950, \ + "coolflux_configured" }, /* Coolflux configured , */ \ + { 0x960, \ + "sel_enbl_amplifier" }, /* Selection if Coolflux enables amplifier , */ \ + { 0x970, \ + "dcdcoff_mode" }, /* DCDC boost converter not connected , */ \ + { 0x980, \ + "iddqtest" }, /* IDDQ amplifier test selection , */ \ + { 0x9c1, \ + "int_pad_io" }, /* INT pad (interrupt bump output) configuration , */ \ + { 0x9e0, \ + "sel_fs_bck" }, /* PLL input reference clock selection , */ \ + { 0x9f0, \ + "sel_scl_cf_clock" }, /* Coolflux sub-system clock selection , */ \ + { 0xa04, \ + "boost_trip_lvl" }, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */ \ + { 0xa54, \ + "boost_hold_time" }, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */ \ + { 0xaa1, \ + "bst_slpcmplvl" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0xb07, \ + "mtpkey2" }, /* KEY2 to access key2 protected registers (default for engineering), */ \ + { 0xc00, \ + "enbl_volt_sense" }, /* Voltage sense enabling control bit , */ \ + { 0xc10, \ + "vsense_pwm_sel" }, /* Voltage sense source selection , */ \ + { 0xc25, \ + "vi_frac_delay" }, /* Fractional delay adjustment between current and voltage sense, */ \ + { 0xc80, \ + "sel_voltsense_out" }, /* TDM output data selection for AEC , */ \ + { 0xc90, \ + "vsense_bypass_avg" }, /* Voltage sense average block bypass , */ \ + { 0xd05, \ + "cf_frac_delay" }, /* Fractional delay adjustment between current and voltage sense by firmware, */ \ + { 0xe00, \ + "bypass_dcdc_curr_prot" }, /* Control to switch off dcdc current reduction with bat protection, */ \ + { 0xe10, \ + "bypass_ocp" }, /* Bypass OCP (digital IP block) , */ \ + { 0xe20, \ + "ocptest" }, /* ocptest (analog IP block) enable , */ \ + { 0xe80, \ + "disable_clock_sh_prot" }, /* Disable clock_sh protection , */ \ + { 0xe92, \ + "reserve_reg_15_09" }, /* Spare control bits for future usage , */ \ + { 0xec0, \ + "unprotect_mtp" }, /* Enable programming of the MTP memory , */ \ + { 0xed2, \ + "reserve_reg_15_13" }, /* Spare control bits for future usage , */ \ + { 0xf00, \ + "dcdc_pfm20khz_limit" }, /* DCDC in PFM mode forcing each 50us a pwm pulse , */ \ + { 0xf11, \ + "dcdc_ctrl_maxzercnt" }, /* DCDC number of zero current flags required to go to pfm mode, */ \ + { 0xf36, \ + "dcdc_vbat_delta_detect" }, /* DCDC threshold required on a delta Vbat (in PFM mode) switching to PWM mode, */ \ + { 0xfa0, \ + "dcdc_ignore_vbat" }, /* Ignore an increase on Vbat , */ \ + { 0x1011, \ + "tdm_usecase" }, /* TDM usecase selection control , */ \ + { 0x1030, \ + "tdm_enable" }, /* TDM interface enable , */ \ + { 0x1040, \ + "tdm_clk_inversion" }, /* TDM clock inversion, receive on , */ \ + { 0x1053, \ + "tdm_fs_ws_length" }, /* TDM FS length , */ \ + { 0x1090, \ + "tdm_fs_ws_polarity" }, /* TDM FS polarity (start frame) , */ \ + { 0x10a4, \ + "tdm_sample_size" }, /* TDM sample size for all TDM sinks and sources , */ \ + { 0x1103, \ + "tdm_nb_of_slots" }, /* TDM number of slots , */ \ + { 0x1144, \ + "tdm_slot_length" }, /* TDM slot length , */ \ + { 0x1194, \ + "tdm_bits_remaining" }, /* TDM bits remaining after the last slot , */ \ + { 0x11e0, \ + "tdm_data_delay" }, /* TDM data delay , */ \ + { 0x11f0, \ + "tdm_data_adjustment" }, /* TDM data adjustment , */ \ + { 0x1201, \ + "tdm_txdata_format" }, /* TDM TXDATA format , */ \ + { 0x1221, \ + "tdm_txdata_format_unused_slot_sd0" }, /* TDM TXDATA format unused slot SD0 , */ \ + { 0x1241, \ + "tdm_txdata_format_unused_slot_sd1" }, /* TDM TXDATA format unused slot SD1 , */ \ + { 0x1270, \ + "tdm_sink0_enable" }, /* TDM sink0 enable , */ \ + { 0x1280, \ + "tdm_sink1_enable" }, /* TDM sink1 enable , */ \ + { 0x1290, \ + "tdm_sink2_enable" }, /* TDM sink2 enable , */ \ + { 0x12a0, \ + "tdm_source0_enable" }, /* TDM source0 enable , */ \ + { 0x12b0, \ + "tdm_source1_enable" }, /* TDM source1 enable , */ \ + { 0x12c0, \ + "tdm_source2_enable" }, /* TDM source2 enable , */ \ + { 0x12d0, \ + "tdm_sink0_io" }, /* TDM sink0 IO selection , */ \ + { 0x12e0, \ + "tdm_sink1_io" }, /* TDM sink1 IO selection , */ \ + { 0x12f0, \ + "tdm_sink2_io" }, /* TDM sink2 IO selection , */ \ + { 0x1300, \ + "tdm_source0_io" }, /* TDM source0 IO selection , */ \ + { 0x1310, \ + "tdm_source1_io" }, /* TDM source1 IO selection , */ \ + { 0x1320, \ + "tdm_source2_io" }, /* TDM source2 IO selection , */ \ + { 0x1333, \ + "tdm_sink0_slot" }, /* TDM sink0 slot position [GAIN IN] , */ \ + { 0x1373, \ + "tdm_sink1_slot" }, /* TDM sink1 slot position [CH1 IN] , */ \ + { 0x13b3, \ + "tdm_sink2_slot" }, /* TDM sink2 slot position [CH2 IN] , */ \ + { 0x1403, \ + "tdm_source0_slot" }, /* TDM source0 slot position [GAIN OUT] , */ \ + { 0x1443, \ + "tdm_source1_slot" }, /* TDM source1 slot position [Voltage Sense] , */ \ + { 0x1483, \ + "tdm_source2_slot" }, /* TDM source2 slot position [Current Sense] , */ \ + { 0x14c3, \ + "tdm_nbck" }, /* TDM NBCK bit clock ratio , */ \ + { 0x1500, \ + "flag_tdm_lut_error" }, /* TDM LUT error flag , */ \ + { 0x1512, \ + "flag_tdm_status" }, /* TDM interface status bits , */ \ + { 0x1540, \ + "flag_tdm_error" }, /* TDM interface error indicator , */ \ + { 0x1551, \ + "status_bst_mode" }, /* DCDC mode status bits , */ \ + { 0x2000, \ + "flag_por_int_out" }, /* flag_por_int_out , */ \ + { 0x2010, \ + "flag_pll_lock_int_out" }, /* flag_pll_lock_int_out , */ \ + { 0x2020, \ + "flag_otpok_int_out" }, /* flag_otpok_int_out , */ \ + { 0x2030, \ + "flag_ovpok_int_out" }, /* flag_ovpok_int_out , */ \ + { 0x2040, \ + "flag_uvpok_int_out" }, /* flag_uvpok_int_out , */ \ + { 0x2050, \ + "flag_ocp_alarm_int_out" }, /* flag_ocp_alarm_int_out , */ \ + { 0x2060, \ + "flag_clocks_stable_int_out" }, /* flag_clocks_stable_int_out , */ \ + { 0x2070, \ + "flag_clip_int_out" }, /* flag_clip_int_out , */ \ + { 0x2080, \ + "mtp_busy_int_out" }, /* mtp_busy_int_out , */ \ + { 0x2090, \ + "flag_lost_clk_int_out" }, /* flag_lost_clk_int_out , */ \ + { 0x20a0, \ + "flag_cf_speakererror_int_out" }, /* flag_cf_speakererror_int_out , */ \ + { 0x20b0, \ + "flag_cold_started_int_out" }, /* flag_cold_started_int_out , */ \ + { 0x20c0, \ + "flag_engage_int_out" }, /* flag_engage_int_out , */ \ + { 0x20d0, \ + "flag_watchdog_reset_int_out" }, /* flag_watchdog_reset_int_out , */ \ + { 0x20e0, \ + "flag_enbl_amp_int_out" }, /* flag_enbl_amp_int_out , */ \ + { 0x20f0, \ + "flag_enbl_ref_int_out" }, /* flag_enbl_ref_int_out , */ \ + { 0x2100, \ + "flag_voutcomp_int_out" }, /* flag_voutcomp_int_out , */ \ + { 0x2110, \ + "flag_voutcomp93_int_out" }, /* flag_voutcomp93_int_out , */ \ + { 0x2120, \ + "flag_voutcomp86_int_out" }, /* flag_voutcomp86_int_out , */ \ + { 0x2130, \ + "flag_hiz_int_out" }, /* flag_hiz_int_out , */ \ + { 0x2140, \ + "flag_ocpokbst_int_out" }, /* flag_ocpokbst_int_out , */ \ + { 0x2150, \ + "flag_peakcur_int_out" }, /* flag_peakcur_int_out , */ \ + { 0x2160, \ + "flag_ocpokap_int_out" }, /* flag_ocpokap_int_out , */ \ + { 0x2170, \ + "flag_ocpokan_int_out" }, /* flag_ocpokan_int_out , */ \ + { 0x2180, \ + "flag_ocpokbp_int_out" }, /* flag_ocpokbp_int_out , */ \ + { 0x2190, \ + "flag_ocpokbn_int_out" }, /* flag_ocpokbn_int_out , */ \ + { 0x21a0, \ + "flag_adc10_ready_int_out" }, /* flag_adc10_ready_int_out , */ \ + { 0x21b0, \ + "flag_clipa_high_int_out" }, /* flag_clipa_high_int_out , */ \ + { 0x21c0, \ + "flag_clipa_low_int_out" }, /* flag_clipa_low_int_out , */ \ + { 0x21d0, \ + "flag_clipb_high_int_out" }, /* flag_clipb_high_int_out , */ \ + { 0x21e0, \ + "flag_clipb_low_int_out" }, /* flag_clipb_low_int_out , */ \ + { 0x21f0, \ + "flag_tdm_error_int_out" }, /* flag_tdm_error_int_out , */ \ + { 0x2200, \ + "flag_cfma_err_int_out" }, /* flag_cfma_err_int_out , */ \ + { 0x2210, \ + "flag_cfma_ack_int_out" }, /* flag_cfma_ack_int_out , */ \ + { 0x2300, \ + "flag_por_int_in" }, /* flag_por_int_in , */ \ + { 0x2310, \ + "flag_pll_lock_int_in" }, /* flag_pll_lock_int_in , */ \ + { 0x2320, \ + "flag_otpok_int_in" }, /* flag_otpok_int_in , */ \ + { 0x2330, \ + "flag_ovpok_int_in" }, /* flag_ovpok_int_in , */ \ + { 0x2340, \ + "flag_uvpok_int_in" }, /* flag_uvpok_int_in , */ \ + { 0x2350, \ + "flag_ocp_alarm_int_in" }, /* flag_ocp_alarm_int_in , */ \ + { 0x2360, \ + "flag_clocks_stable_int_in" }, /* flag_clocks_stable_int_in , */ \ + { 0x2370, \ + "flag_clip_int_in" }, /* flag_clip_int_in , */ \ + { 0x2380, \ + "mtp_busy_int_in" }, /* mtp_busy_int_in , */ \ + { 0x2390, \ + "flag_lost_clk_int_in" }, /* flag_lost_clk_int_in , */ \ + { 0x23a0, \ + "flag_cf_speakererror_int_in" }, /* flag_cf_speakererror_int_in , */ \ + { 0x23b0, \ + "flag_cold_started_int_in" }, /* flag_cold_started_int_in , */ \ + { 0x23c0, \ + "flag_engage_int_in" }, /* flag_engage_int_in , */ \ + { 0x23d0, \ + "flag_watchdog_reset_int_in" }, /* flag_watchdog_reset_int_in , */ \ + { 0x23e0, \ + "flag_enbl_amp_int_in" }, /* flag_enbl_amp_int_in , */ \ + { 0x23f0, \ + "flag_enbl_ref_int_in" }, /* flag_enbl_ref_int_in , */ \ + { 0x2400, \ + "flag_voutcomp_int_in" }, /* flag_voutcomp_int_in , */ \ + { 0x2410, \ + "flag_voutcomp93_int_in" }, /* flag_voutcomp93_int_in , */ \ + { 0x2420, \ + "flag_voutcomp86_int_in" }, /* flag_voutcomp86_int_in , */ \ + { 0x2430, \ + "flag_hiz_int_in" }, /* flag_hiz_int_in , */ \ + { 0x2440, \ + "flag_ocpokbst_int_in" }, /* flag_ocpokbst_int_in , */ \ + { 0x2450, \ + "flag_peakcur_int_in" }, /* flag_peakcur_int_in , */ \ + { 0x2460, \ + "flag_ocpokap_int_in" }, /* flag_ocpokap_int_in , */ \ + { 0x2470, \ + "flag_ocpokan_int_in" }, /* flag_ocpokan_int_in , */ \ + { 0x2480, \ + "flag_ocpokbp_int_in" }, /* flag_ocpokbp_int_in , */ \ + { 0x2490, \ + "flag_ocpokbn_int_in" }, /* flag_ocpokbn_int_in , */ \ + { 0x24a0, \ + "flag_adc10_ready_int_in" }, /* flag_adc10_ready_int_in , */ \ + { 0x24b0, \ + "flag_clipa_high_int_in" }, /* flag_clipa_high_int_in , */ \ + { 0x24c0, \ + "flag_clipa_low_int_in" }, /* flag_clipa_low_int_in , */ \ + { 0x24d0, \ + "flag_clipb_high_int_in" }, /* flag_clipb_high_int_in , */ \ + { 0x24e0, \ + "flag_clipb_low_int_in" }, /* flag_clipb_low_int_in , */ \ + { 0x24f0, \ + "flag_tdm_error_int_in" }, /* flag_tdm_error_int_in , */ \ + { 0x2500, \ + "flag_cfma_err_int_in" }, /* flag_cfma_err_int_in , */ \ + { 0x2510, \ + "flag_cfma_ack_int_in" }, /* flag_cfma_ack_int_in , */ \ + { 0x2600, \ + "flag_por_int_enable" }, /* flag_por_int_enable , */ \ + { 0x2610, \ + "flag_pll_lock_int_enable" }, /* flag_pll_lock_int_enable , */ \ + { 0x2620, \ + "flag_otpok_int_enable" }, /* flag_otpok_int_enable , */ \ + { 0x2630, \ + "flag_ovpok_int_enable" }, /* flag_ovpok_int_enable , */ \ + { 0x2640, \ + "flag_uvpok_int_enable" }, /* flag_uvpok_int_enable , */ \ + { 0x2650, \ + "flag_ocp_alarm_int_enable" }, /* flag_ocp_alarm_int_enable , */ \ + { 0x2660, \ + "flag_clocks_stable_int_enable" }, /* flag_clocks_stable_int_enable , */ \ + { 0x2670, \ + "flag_clip_int_enable" }, /* flag_clip_int_enable , */ \ + { 0x2680, \ + "mtp_busy_int_enable" }, /* mtp_busy_int_enable , */ \ + { 0x2690, \ + "flag_lost_clk_int_enable" }, /* flag_lost_clk_int_enable , */ \ + { 0x26a0, \ + "flag_cf_speakererror_int_enable" }, /* flag_cf_speakererror_int_enable , */ \ + { 0x26b0, \ + "flag_cold_started_int_enable" }, /* flag_cold_started_int_enable , */ \ + { 0x26c0, \ + "flag_engage_int_enable" }, /* flag_engage_int_enable , */ \ + { 0x26d0, \ + "flag_watchdog_reset_int_enable" }, /* flag_watchdog_reset_int_enable , */ \ + { 0x26e0, \ + "flag_enbl_amp_int_enable" }, /* flag_enbl_amp_int_enable , */ \ + { 0x26f0, \ + "flag_enbl_ref_int_enable" }, /* flag_enbl_ref_int_enable , */ \ + { 0x2700, \ + "flag_voutcomp_int_enable" }, /* flag_voutcomp_int_enable , */ \ + { 0x2710, \ + "flag_voutcomp93_int_enable" }, /* flag_voutcomp93_int_enable , */ \ + { 0x2720, \ + "flag_voutcomp86_int_enable" }, /* flag_voutcomp86_int_enable , */ \ + { 0x2730, \ + "flag_hiz_int_enable" }, /* flag_hiz_int_enable , */ \ + { 0x2740, \ + "flag_ocpokbst_int_enable" }, /* flag_ocpokbst_int_enable , */ \ + { 0x2750, \ + "flag_peakcur_int_enable" }, /* flag_peakcur_int_enable , */ \ + { 0x2760, \ + "flag_ocpokap_int_enable" }, /* flag_ocpokap_int_enable , */ \ + { 0x2770, \ + "flag_ocpokan_int_enable" }, /* flag_ocpokan_int_enable , */ \ + { 0x2780, \ + "flag_ocpokbp_int_enable" }, /* flag_ocpokbp_int_enable , */ \ + { 0x2790, \ + "flag_ocpokbn_int_enable" }, /* flag_ocpokbn_int_enable , */ \ + { 0x27a0, \ + "flag_adc10_ready_int_enable" }, /* flag_adc10_ready_int_enable , */ \ + { 0x27b0, \ + "flag_clipa_high_int_enable" }, /* flag_clipa_high_int_enable , */ \ + { 0x27c0, \ + "flag_clipa_low_int_enable" }, /* flag_clipa_low_int_enable , */ \ + { 0x27d0, \ + "flag_clipb_high_int_enable" }, /* flag_clipb_high_int_enable , */ \ + { 0x27e0, \ + "flag_clipb_low_int_enable" }, /* flag_clipb_low_int_enable , */ \ + { 0x27f0, \ + "flag_tdm_error_int_enable" }, /* flag_tdm_error_int_enable , */ \ + { 0x2800, \ + "flag_cfma_err_int_enable" }, /* flag_cfma_err_int_enable , */ \ + { 0x2810, \ + "flag_cfma_ack_int_enable" }, /* flag_cfma_ack_int_enable , */ \ + { 0x2900, \ + "flag_por_int_pol" }, /* flag_por_int_pol , */ \ + { 0x2910, \ + "flag_pll_lock_int_pol" }, /* flag_pll_lock_int_pol , */ \ + { 0x2920, \ + "flag_otpok_int_pol" }, /* flag_otpok_int_pol , */ \ + { 0x2930, \ + "flag_ovpok_int_pol" }, /* flag_ovpok_int_pol , */ \ + { 0x2940, \ + "flag_uvpok_int_pol" }, /* flag_uvpok_int_pol , */ \ + { 0x2950, \ + "flag_ocp_alarm_int_pol" }, /* flag_ocp_alarm_int_pol , */ \ + { 0x2960, \ + "flag_clocks_stable_int_pol" }, /* flag_clocks_stable_int_pol , */ \ + { 0x2970, \ + "flag_clip_int_pol" }, /* flag_clip_int_pol , */ \ + { 0x2980, \ + "mtp_busy_int_pol" }, /* mtp_busy_int_pol , */ \ + { 0x2990, \ + "flag_lost_clk_int_pol" }, /* flag_lost_clk_int_pol , */ \ + { 0x29a0, \ + "flag_cf_speakererror_int_pol" }, /* flag_cf_speakererror_int_pol , */ \ + { 0x29b0, \ + "flag_cold_started_int_pol" }, /* flag_cold_started_int_pol , */ \ + { 0x29c0, \ + "flag_engage_int_pol" }, /* flag_engage_int_pol , */ \ + { 0x29d0, \ + "flag_watchdog_reset_int_pol" }, /* flag_watchdog_reset_int_pol , */ \ + { 0x29e0, \ + "flag_enbl_amp_int_pol" }, /* flag_enbl_amp_int_pol , */ \ + { 0x29f0, \ + "flag_enbl_ref_int_pol" }, /* flag_enbl_ref_int_pol , */ \ + { 0x2a00, \ + "flag_voutcomp_int_pol" }, /* flag_voutcomp_int_pol , */ \ + { 0x2a10, \ + "flag_voutcomp93_int_pol" }, /* flag_voutcomp93_int_pol , */ \ + { 0x2a20, \ + "flag_voutcomp86_int_pol" }, /* flag_voutcomp86_int_pol , */ \ + { 0x2a30, \ + "flag_hiz_int_pol" }, /* flag_hiz_int_pol , */ \ + { 0x2a40, \ + "flag_ocpokbst_int_pol" }, /* flag_ocpokbst_int_pol , */ \ + { 0x2a50, \ + "flag_peakcur_int_pol" }, /* flag_peakcur_int_pol , */ \ + { 0x2a60, \ + "flag_ocpokap_int_pol" }, /* flag_ocpokap_int_pol , */ \ + { 0x2a70, \ + "flag_ocpokan_int_pol" }, /* flag_ocpokan_int_pol , */ \ + { 0x2a80, \ + "flag_ocpokbp_int_pol" }, /* flag_ocpokbp_int_pol , */ \ + { 0x2a90, \ + "flag_ocpokbn_int_pol" }, /* flag_ocpokbn_int_pol , */ \ + { 0x2aa0, \ + "flag_adc10_ready_int_pol" }, /* flag_adc10_ready_int_pol , */ \ + { 0x2ab0, \ + "flag_clipa_high_int_pol" }, /* flag_clipa_high_int_pol , */ \ + { 0x2ac0, \ + "flag_clipa_low_int_pol" }, /* flag_clipa_low_int_pol , */ \ + { 0x2ad0, \ + "flag_clipb_high_int_pol" }, /* flag_clipb_high_int_pol , */ \ + { 0x2ae0, \ + "flag_clipb_low_int_pol" }, /* flag_clipb_low_int_pol , */ \ + { 0x2af0, \ + "flag_tdm_error_int_pol" }, /* flag_tdm_error_int_pol , */ \ + { 0x2b00, \ + "flag_cfma_err_int_pol" }, /* flag_cfma_err_int_pol , */ \ + { 0x2b10, \ + "flag_cfma_ack_int_pol" }, /* flag_cfma_ack_int_pol , */ \ + { 0x3000, \ + "flag_voutcomp" }, /* Status flag_voutcomp, indication Vset is larger than Vbat, */ \ + { 0x3010, \ + "flag_voutcomp93" }, /* Status flag_voutcomp93, indication Vset is larger than 1.07 x Vbat, */ \ + { 0x3020, \ + "flag_voutcomp86" }, /* Status flag voutcomp86, indication Vset is larger than 1.14 x Vbat, */ \ + { 0x3030, \ + "flag_hiz" }, /* Status flag_hiz, indication Vbst is larger than Vbat, */ \ + { 0x3040, \ + "flag_ocpokbst" }, /* Status flag_ocpokbst, indication no over current in boost converter PMOS switch, */ \ + { 0x3050, \ + "flag_peakcur" }, /* Status flag_peakcur, indication current is max in dcdc converter, */ \ + { 0x3060, \ + "flag_ocpokap" }, /* Status flag_ocpokap, indication no over current in amplifier A PMOS output stage, */ \ + { 0x3070, \ + "flag_ocpokan" }, /* Status flag_ocpokan, indication no over current in amplifier A NMOS output stage, */ \ + { 0x3080, \ + "flag_ocpokbp" }, /* Status flag_ocpokbp, indication no over current in amplifier B PMOS output stage, */ \ + { 0x3090, \ + "flag_ocpokbn" }, /* Status flag_ocpokbn, indication no over current in amplifier B NMOS output stage, */ \ + { 0x30a0, \ + "flag_adc10_ready" }, /* Status flag_adc10_ready, indication adc10 is ready, */ \ + { 0x30b0, \ + "flag_clipa_high" }, /* Status flag_clipa_high, indication pmos amplifier A is clipping, */ \ + { 0x30c0, \ + "flag_clipa_low" }, /* Status flag_clipa_low, indication nmos amplifier A is clipping, */ \ + { 0x30d0, \ + "flag_clipb_high" }, /* Status flag_clipb_high, indication pmos amplifier B is clipping, */ \ + { 0x30e0, \ + "flag_clipb_low" }, /* Status flag_clipb_low, indication nmos amplifier B is clipping, */ \ + { 0x310f, \ + "mtp_man_data_out" }, /* MTP manual read out data , */ \ + { 0x3200, \ + "key01_locked" }, /* Indicates KEY1 is locked , */ \ + { 0x3210, \ + "key02_locked" }, /* Indicates KEY2 is locked , */ \ + { 0x3225, \ + "mtp_ecc_tcout" }, /* MTP error correction test data out , */ \ + { 0x3280, \ + "mtpctrl_valid_test_rd" }, /* MTP test readout for read , */ \ + { 0x3290, \ + "mtpctrl_valid_test_wr" }, /* MTP test readout for write , */ \ + { 0x32a0, \ + "flag_in_alarm_state" }, /* Flag alarm state , */ \ + { 0x32b0, \ + "mtp_ecc_err2" }, /* Two or more bit errors detected in MTP, can not reconstruct value, */ \ + { 0x32c0, \ + "mtp_ecc_err1" }, /* One bit error detected in MTP, reconstructed value, */ \ + { 0x32d0, \ + "mtp_mtp_hvf" }, /* High voltage ready flag for MTP , */ \ + { 0x32f0, \ + "mtp_zero_check_fail" }, /* Zero check failed for MTP , */ \ + { 0x3309, \ + "data_adc10_tempbat" }, /* ADC10 data output for testing battery voltage and temperature, */ \ + { 0x400f, \ + "hid_code" }, /* 5A6Bh, 23147d to access hidden registers (default for engineering), */ \ + { 0x4100, \ + "bypass_hp" }, /* Bypass High Pass Filter , */ \ + { 0x4110, \ + "hard_mute" }, /* Hard Mute , */ \ + { 0x4120, \ + "soft_mute" }, /* Soft Mute , */ \ + { 0x4134, \ + "pwm_delay" }, /* PWM delay setting , */ \ + { 0x4180, \ + "pwm_shape" }, /* PWM Shape , */ \ + { 0x4190, \ + "pwm_bitlength" }, /* PWM Bitlength in noise shaper , */ \ + { 0x4203, \ + "drive" }, /* Drive bits to select number of amplifier power stages, */ \ + { 0x4240, \ + "reclock_pwm" }, /* Control for enabling reclocking of PWM signal , */ \ + { 0x4250, \ + "reclock_voltsense" }, /* Control for enabling reclocking of voltage sense signal, */ \ + { 0x4281, \ + "dpsalevel" }, /* DPSA threshold level , */ \ + { 0x42a1, \ + "dpsa_release" }, /* DPSA release time , */ \ + { 0x42c0, \ + "coincidence" }, /* Prevent simultaneously switching of output stage , */ \ + { 0x42d0, \ + "kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x4306, \ + "drivebst" }, /* Drive bits to select the power transistor sections boost converter, */ \ + { 0x4370, \ + "boost_alg" }, /* Control for boost adaptive loop gain , */ \ + { 0x4381, \ + "boost_loopgain" }, /* DCDC boost loopgain setting , */ \ + { 0x43a0, \ + "ocptestbst" }, /* Boost OCP. For old ocp (ctrl_reversebst is 0); For new ocp (ctrl_reversebst is 1), */ \ + { 0x43d0, \ + "test_abistfft_enbl" }, /* FFT Coolflux , */ \ + { 0x43e0, \ + "bst_dcmbst" }, /* DCM mode control for DCDC during I2C direct control mode, */ \ + { 0x43f0, \ + "test_bcontrol" }, /* test_bcontrol , */ \ + { 0x4400, \ + "reversebst" }, /* OverCurrent Protection selection of power stage boost converter, */ \ + { 0x4410, \ + "sensetest" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0x4420, \ + "enbl_engagebst" }, /* Enable power stage of dcdc controller , */ \ + { 0x4470, \ + "enbl_slopecur" }, /* Enable bit of max-current dac , */ \ + { 0x4480, \ + "enbl_voutcomp" }, /* Enable vout comparators , */ \ + { 0x4490, \ + "enbl_voutcomp93" }, /* Enable vout-93 comparators , */ \ + { 0x44a0, \ + "enbl_voutcomp86" }, /* Enable vout-86 comparators , */ \ + { 0x44b0, \ + "enbl_hizcom" }, /* Enable hiz comparator , */ \ + { 0x44c0, \ + "enbl_peakcur" }, /* Enable peak current , */ \ + { 0x44d0, \ + "bypass_ovpglitch" }, /* Bypass OVP Glitch Filter , */ \ + { 0x44e0, \ + "enbl_windac" }, /* Enable window dac , */ \ + { 0x44f0, \ + "enbl_powerbst" }, /* Enable line of the powerstage , */ \ + { 0x4507, \ + "ocp_thr" }, /* OCP threshold level , */ \ + { 0x4580, \ + "bypass_glitchfilter" }, /* Bypass glitch filter , */ \ + { 0x4590, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0x45a0, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0x45b0, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0x45d0, \ + "bypass_ocpcounter" }, /* Bypass OCP counter , */ \ + { 0x45e0, \ + "bypass_lost_clk" }, /* Bypass lost clock detector , */ \ + { 0x45f0, \ + "vpalarm" }, /* vpalarm (UVP/OUP handling) , */ \ + { 0x4600, \ + "bypass_gc" }, /* Bypasses the CS gain correction , */ \ + { 0x4610, \ + "cs_gain_control" }, /* Current sense gain control , */ \ + { 0x4627, \ + "cs_gain" }, /* Current sense gain , */ \ + { 0x46a0, \ + "bypass_lp" }, /* Bypass the low power filter inside temperature sensor, */ \ + { 0x46b0, \ + "bypass_pwmcounter" }, /* Bypass PWM Counter , */ \ + { 0x46c0, \ + "cs_negfixed" }, /* Current sense does not switch to neg , */ \ + { 0x46d2, \ + "cs_neghyst" }, /* Current sense switches to neg depending on hyseteris level, */ \ + { 0x4700, \ + "switch_fb" }, /* Current sense control switch_fb , */ \ + { 0x4713, \ + "se_hyst" }, /* Current sense control se_hyst , */ \ + { 0x4754, \ + "se_level" }, /* Current sense control se_level , */ \ + { 0x47a5, \ + "ktemp" }, /* Current sense control temperature compensation trimming, */ \ + { 0x4800, \ + "cs_negin" }, /* Current sense control negin , */ \ + { 0x4810, \ + "cs_sein" }, /* Current sense control cs_sein , */ \ + { 0x4820, \ + "cs_coincidence" }, /* Coincidence current sense , */ \ + { 0x4830, \ + "iddqtestbst" }, /* IDDQ testing in powerstage of DCDC boost converter, */ \ + { 0x4840, \ + "coincidencebst" }, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */ \ + { 0x4876, \ + "delay_se_neg" }, /* delay of se and neg , */ \ + { 0x48e1, \ + "cs_ttrack" }, /* Sample and hold track time , */ \ + { 0x4900, \ + "bypass_clip" }, /* Bypass clip control , */ \ + { 0x4920, \ + "cf_cgate_off" }, /* Disable clock gating in the coolflux , */ \ + { 0x4940, \ + "clipfast" }, /* Clock selection for HW clipper for battery safeguard, */ \ + { 0x4950, \ + "cs_8ohm" }, /* 8 ohm mode for current sense (gain mode) , */ \ + { 0x4974, \ + "delay_clock_sh" }, /* delay_sh, tunes S7H delay , */ \ + { 0x49c0, \ + "inv_clksh" }, /* Invert the sample/hold clock for current sense ADC, */ \ + { 0x49d0, \ + "inv_neg" }, /* Invert neg signal , */ \ + { 0x49e0, \ + "inv_se" }, /* Invert se signal , */ \ + { 0x49f0, \ + "setse" }, /* Switches between Single Ended and differential mode; 1 is single ended, */ \ + { 0x4a12, \ + "adc10_sel" }, /* Select the input to convert the 10b ADC , */ \ + { 0x4a60, \ + "adc10_reset" }, /* Reset for ADC10 - I2C direct control mode , */ \ + { 0x4a81, \ + "adc10_test" }, /* Test mode selection signal for ADC10 - I2C direct control mode, */ \ + { 0x4aa0, \ + "bypass_lp_vbat" }, /* LP filter in batt sensor , */ \ + { 0x4ae0, \ + "dc_offset" }, /* Current sense decimator offset control , */ \ + { 0x4af0, \ + "tsense_hibias" }, /* Bit to set the biasing in temp sensor to high , */ \ + { 0x4b00, \ + "adc13_iset" }, /* MICADC setting of current consumption (debug use only), */ \ + { 0x4b14, \ + "adc13_gain" }, /* MICADC gain setting (two's complement format) , */ \ + { 0x4b61, \ + "adc13_slowdel" }, /* MICADC delay setting for internal clock (debug use only), */ \ + { 0x4b83, \ + "adc13_offset" }, /* MICADC offset setting , */ \ + { 0x4bc0, \ + "adc13_bsoinv" }, /* MICADC bit stream output invert mode for test , */ \ + { 0x4bd0, \ + "adc13_resonator_enable" }, /* MICADC give extra SNR with less stability (debug use only), */ \ + { 0x4be0, \ + "testmicadc" }, /* Mux at input of MICADC for test purpose , */ \ + { 0x4c0f, \ + "abist_offset" }, /* Offset control for ABIST testing , */ \ + { 0x4d05, \ + "windac" }, /* For testing direct control windac , */ \ + { 0x4dc3, \ + "pwm_dcc_cnt" }, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0x4e04, \ + "slopecur" }, /* For testing direct control slopecur , */ \ + { 0x4e50, \ + "ctrl_dem" }, /* Dynamic element matching control, rest of codes are optional, */ \ + { 0x4ed0, \ + "enbl_pwm_dcc" }, /* Enable direct control of pwm duty cycle , */ \ + { 0x4f00, \ + "bst_bypass_bstcur" }, /* Bypass control for boost current settings , */ \ + { 0x4f10, \ + "bst_bypass_bstfoldback" }, /* Bypass control for boost foldback , */ \ + { 0x4f20, \ + "bst_ctrl_azbst" }, /* Control of auto-zeroing of zero current comparator, */ \ + { 0x5007, \ + "gain" }, /* Gain setting of the gain multiplier , */ \ + { 0x5081, \ + "sourceb" }, /* PWM OUTB selection control , */ \ + { 0x50a1, \ + "sourcea" }, /* PWM OUTA selection control , */ \ + { 0x50c1, \ + "sourcebst" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0x50e0, \ + "tdm_enable_loopback" }, /* TDM loopback test , */ \ + { 0x5104, \ + "pulselengthbst" }, /* Pulse length setting test input for boost converter, */ \ + { 0x5150, \ + "bypasslatchbst" }, /* Bypass latch in boost converter , */ \ + { 0x5160, \ + "invertbst" }, /* Invert pwmbst test signal , */ \ + { 0x5174, \ + "pulselength" }, /* Pulse length setting test input for amplifier , */ \ + { 0x51c0, \ + "bypasslatch" }, /* Bypass latch in PWM source selection module , */ \ + { 0x51d0, \ + "invertb" }, /* invert pwmb test signal , */ \ + { 0x51e0, \ + "inverta" }, /* invert pwma test signal , */ \ + { 0x51f0, \ + "bypass_ctrlloop" }, /* bypass_ctrlloop bypasses the control loop of the amplifier, */ \ + { 0x5210, \ + "test_rdsona" }, /* tbd for rdson testing , */ \ + { 0x5220, \ + "test_rdsonb" }, /* tbd for rdson testing , */ \ + { 0x5230, \ + "test_rdsonbst" }, /* tbd for rdson testing , */ \ + { 0x5240, \ + "test_cvia" }, /* tbd for rdson testing , */ \ + { 0x5250, \ + "test_cvib" }, /* tbd for rdson testing , */ \ + { 0x5260, \ + "test_cvibst" }, /* tbd for rdson testing , */ \ + { 0x5306, \ + "digimuxa_sel" }, /* DigimuxA input selection control (see Digimux list for details), */ \ + { 0x5376, \ + "digimuxb_sel" }, /* DigimuxB input selection control (see Digimux list for details), */ \ + { 0x5400, \ + "hs_mode" }, /* I2C high speed mode selection control , */ \ + { 0x5412, \ + "test_parametric_io" }, /* Control for parametric tests of IO cells , */ \ + { 0x5440, \ + "enbl_ringo" }, /* Enable ring oscillator control, for test purpose to check with ringo, */ \ + { 0x5456, \ + "digimuxc_sel" }, /* DigimuxC input selection control (see Digimux list for details), */ \ + { 0x54c0, \ + "dio_ehs" }, /* Slew control for DIO in output mode , */ \ + { 0x54d0, \ + "gainio_ehs" }, /* Slew control for GAINIO in output mode , */ \ + { 0x550d, \ + "enbl_amp" }, /* enbl_amp for testing to enable all analoge blocks in amplifier, */ \ + { 0x5600, \ + "use_direct_ctrls" }, /* Use direct controls to overrule several functions for testing - I2C direct control mode, */ \ + { 0x5610, \ + "rst_datapath" }, /* Reset datapath during direct control mode , */ \ + { 0x5620, \ + "rst_cgu" }, /* Reset CGU during durect control mode , */ \ + { 0x5637, \ + "enbl_ref" }, /* For testing to enable all analoge blocks in references, */ \ + { 0x56b0, \ + "enbl_engage" }, /* Enable output stage amplifier , */ \ + { 0x56c0, \ + "use_direct_clk_ctrl" }, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */ \ + { 0x56d0, \ + "use_direct_pll_ctrl" }, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */ \ + { 0x5707, \ + "anamux" }, /* Anamux control , */ \ + { 0x57e0, \ + "otptest" }, /* otptest, test mode otp amplifier , */ \ + { 0x57f0, \ + "reverse" }, /* 1b = Normal mode, slope is controlled , */ \ + { 0x5813, \ + "pll_selr" }, /* PLL pll_selr , */ \ + { 0x5854, \ + "pll_selp" }, /* PLL pll_selp , */ \ + { 0x58a5, \ + "pll_seli" }, /* PLL pll_seli , */ \ + { 0x5950, \ + "pll_mdec_msb" }, /* Most significant bits of pll_mdec[16] , */ \ + { 0x5960, \ + "pll_ndec_msb" }, /* Most significant bits of pll_ndec[9] , */ \ + { 0x5970, \ + "pll_frm" }, /* PLL pll_frm , */ \ + { 0x5980, \ + "pll_directi" }, /* PLL pll_directi , */ \ + { 0x5990, \ + "pll_directo" }, /* PLL pll_directo , */ \ + { 0x59a0, \ + "enbl_pll" }, /* PLL enbl_pll , */ \ + { 0x59f0, \ + "pll_bypass" }, /* PLL bypass , */ \ + { 0x5a0f, \ + "tsig_freq" }, /* Internal sinus test generator frequency control LSB bits, */ \ + { 0x5b02, \ + "tsig_freq_msb" }, /* Select internal sine wave generator, frequency control MSB bits, */ \ + { 0x5b30, \ + "inject_tsig" }, /* Control bit to switch to internal sinus test generator, */ \ + { 0x5b44, \ + "adc10_prog_sample" }, /* ADC10 program sample setting - I2C direct control mode, */ \ + { 0x5c0f, \ + "pll_mdec" }, /* PLL MDEC - I2C direct PLL control mode only , */ \ + { 0x5d06, \ + "pll_pdec" }, /* PLL PDEC - I2C direct PLL control mode only , */ \ + { 0x5d78, \ + "pll_ndec" }, /* PLL NDEC - I2C direct PLL control mode only , */ \ + { 0x6007, \ + "mtpkey1" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0x6185, \ + "mtp_ecc_tcin" }, /* MTP ECC TCIN data , */ \ + { 0x6203, \ + "mtp_man_address_in" }, /* MTP address from I2C register for read/writing mtp in manual single word mode, */ \ + { 0x6260, \ + "mtp_ecc_eeb" }, /* Enable code bit generation (active low!) , */ \ + { 0x6270, \ + "mtp_ecc_ecb" }, /* Enable correction signal (active low!) , */ \ + { 0x6280, \ + "man_copy_mtp_to_iic" }, /* Start copying single word from mtp to I2C mtp register, */ \ + { 0x6290, \ + "man_copy_iic_to_mtp" }, /* Start copying single word from I2C mtp register to mtp, */ \ + { 0x62a0, \ + "auto_copy_mtp_to_iic" }, /* Start copying all the data from mtp to I2C mtp registers, */ \ + { 0x62b0, \ + "auto_copy_iic_to_mtp" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0x62d2, \ + "mtp_speed_mode" }, /* MTP speed mode , */ \ + { 0x6340, \ + "mtp_direct_enable" }, /* mtp_direct_enable , */ \ + { 0x6350, \ + "mtp_direct_wr" }, /* mtp_direct_wr , */ \ + { 0x6360, \ + "mtp_direct_rd" }, /* mtp_direct_rd , */ \ + { 0x6370, \ + "mtp_direct_rst" }, /* mtp_direct_rst , */ \ + { 0x6380, \ + "mtp_direct_ers" }, /* mtp_direct_ers , */ \ + { 0x6390, \ + "mtp_direct_prg" }, /* mtp_direct_prg , */ \ + { 0x63a0, \ + "mtp_direct_epp" }, /* mtp_direct_epp , */ \ + { 0x63b4, \ + "mtp_direct_test" }, /* mtp_direct_test , */ \ + { 0x640f, \ + "mtp_man_data_in" }, /* Write data for MTP manual write , */ \ + { 0x7000, \ + "cf_rst_dsp" }, /* Reset CoolFlux DSP , */ \ + { 0x7011, \ + "cf_dmem" }, /* Target memory for access , */ \ + { 0x7030, \ + "cf_aif" }, /* Auto increment flag for memory-address , */ \ + { 0x7040, \ + "cf_int" }, /* CF Interrupt - auto clear , */ \ + { 0x7087, \ + "cf_req" }, /* CF request for accessing the 8 channels , */ \ + { 0x710f, \ + "cf_madd" }, /* Memory address , */ \ + { 0x720f, \ + "cf_mema" }, /* Activate memory access , */ \ + { 0x7307, \ + "cf_err" }, /* CF error flags , */ \ + { 0x7387, \ + "cf_ack" }, /* CF acknowledgement of the requests channels , */ \ + { 0x8000, \ + "calibration_onetime" }, /* Calibration schedule selection , */ \ + { 0x8010, \ + "calibr_ron_done" }, /* Calibration of RON status bit , */ \ + { 0x8105, \ + "calibr_vout_offset" }, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */ \ + { 0x8163, \ + "calibr_delta_gain" }, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */ \ + { 0x81a5, \ + "calibr_offs_amp" }, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */ \ + { 0x8207, \ + "calibr_gain_cs" }, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */ \ + { 0x8284, \ + "calibr_temp_offset" }, /* temperature offset 2's compliment (key1 protected), */ \ + { 0x82d2, \ + "calibr_temp_gain" }, /* temperature gain 2's compliment (key1 protected) , */ \ + { 0x830f, \ + "calibr_ron" }, /* calibration value of the RON resistance of the coil, */ \ + { 0x8505, \ + "type_bits_hw" }, /* bit0 = disable function dcdcoff_mode ($09[7]) , */ \ + { 0x8601, \ + "type_bits_1_0_sw" }, /* MTP control SW , */ \ + { 0x8681, \ + "type_bits_9_8_sw" }, /* MTP control SW , */ \ + { 0x870f, \ + "type_bits2_sw" }, /* MTP-control SW2 , */ \ + { 0x8806, \ + "htol_iic_addr" }, /* 7-bit I2C address to be used during HTOL testing , */ \ + { 0x8870, \ + "htol_iic_addr_en" }, /* HTOL I2C_Address_Enable , */ \ + { 0x8881, \ + "ctrl_ovp_response" }, /* OVP response control , */ \ + { 0x88a0, \ + "disable_ovp_alarm_state" }, /* OVP alarm state control , */ \ + { 0x88b0, \ + "enbl_stretch_ovp" }, /* OVP alram strech control , */ \ + { 0x88c0, \ + "cf_debug_mode" }, /* Coolflux debug mode , */ \ + { 0x8a0f, \ + "production_data1" }, /* production_data1 , */ \ + { 0x8b0f, \ + "production_data2" }, /* production_data2 , */ \ + { 0x8c0f, \ + "production_data3" }, /* production_data3 , */ \ + { 0x8d0f, \ + "production_data4" }, /* production_data4 , */ \ + { 0x8e0f, \ + "production_data5" }, /* production_data5 , */ \ + { 0x8f0f, \ + "production_data6" }, /* production_data6 , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +enum TFA9896_irq { + TFA9896_irq_vdds = 0, + TFA9896_irq_plls = 1, + TFA9896_irq_ds = 2, + TFA9896_irq_vds = 3, + TFA9896_irq_uvds = 4, + TFA9896_irq_cds = 5, + TFA9896_irq_clks = 6, + TFA9896_irq_clips = 7, + TFA9896_irq_mtpb = 8, + TFA9896_irq_clk = 9, + TFA9896_irq_spks = 10, + TFA9896_irq_acs = 11, + TFA9896_irq_sws = 12, + TFA9896_irq_wds = 13, + TFA9896_irq_amps = 14, + TFA9896_irq_arefs = 15, + TFA9896_irq_err = 32, + TFA9896_irq_ack = 33, + TFA9896_irq_max = 34, + TFA9896_irq_all = -1 /* all irqs */ +}; + +#define TFA9896_IRQ_NAMETABLE \ + static tfaIrqName_t TFA9896IrqNames[] = { \ + { 0, "VDDS" }, { 1, "PLLS" }, { 2, "DS" }, { 3, "VDS" }, \ + { 4, "UVDS" }, { 5, "CDS" }, { 6, "CLKS" }, { 7, "CLIPS" }, \ + { 8, "MTPB" }, { 9, "CLK" }, { 10, "SPKS" }, { 11, "ACS" }, \ + { 12, "SWS" }, { 13, "WDS" }, { 14, "AMPS" }, { 15, "AREFS" }, \ + { 16, "16" }, { 17, "17" }, { 18, "18" }, { 19, "19" }, \ + { 20, "20" }, { 21, "21" }, { 22, "22" }, { 23, "23" }, \ + { 24, "24" }, { 25, "25" }, { 26, "26" }, { 27, "27" }, \ + { 28, "28" }, { 29, "29" }, { 30, "30" }, { 31, "31" }, \ + { 32, "ERR" }, { 33, "ACK" }, { 34, "34" }, \ + }; +#endif /* _TFA9896_TFAFIELDNAMES_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx.h new file mode 100644 index 000000000000..c1b7e2f3fc57 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx.h @@ -0,0 +1,189 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __TFA98XX_INC__ +#define __TFA98XX_INC__ + +#include +#include +#include +#include + +#include "tfa_device.h" +#include "tfa_container.h" +#include "config.h" + +/* max. length of a alsa mixer control name */ +#define MAX_CONTROL_NAME 48 + +#define TFA98XX_MAX_REGISTER 0xff + +#define TFA98XX_FLAG_SKIP_INTERRUPTS (1 << 0) +#define TFA98XX_FLAG_SAAM_AVAILABLE (1 << 1) +#define TFA98XX_FLAG_STEREO_DEVICE (1 << 2) +#define TFA98XX_FLAG_MULTI_MIC_INPUTS (1 << 3) +#define TFA98XX_FLAG_TAPDET_AVAILABLE (1 << 4) +#define TFA98XX_FLAG_CALIBRATION_CTL (1 << 5) +#define TFA98XX_FLAG_REMOVE_PLOP_NOISE (1 << 6) +#define TFA98XX_FLAG_LP_MODES (1 << 7) +#define TFA98XX_FLAG_TDM_DEVICE (1 << 8) + +#define TFA98XX_NUM_RATES 9 + +/* DSP init status */ +enum tfa98xx_dsp_init_state { + TFA98XX_DSP_INIT_STOPPED, /* DSP not running */ + TFA98XX_DSP_INIT_RECOVER, /* DSP error detected at runtime */ + TFA98XX_DSP_INIT_FAIL, /* DSP init failed */ + TFA98XX_DSP_INIT_PENDING, /* DSP start requested */ + TFA98XX_DSP_INIT_DONE, /* DSP running */ + TFA98XX_DSP_INIT_INVALIDATED, /* DSP was running, requires re-init */ +}; + +enum tfa98xx_dsp_fw_state { + TFA98XX_DSP_FW_NONE = 0, + TFA98XX_DSP_FW_PENDING, + TFA98XX_DSP_FW_FAIL, + TFA98XX_DSP_FW_OK, +}; + +enum tfa98xx_misc_device_id { + MISC_DEVICE_TFA98XX_REG, + MISC_DEVICE_TFA98XX_RW, + MISC_DEVICE_TFA98XX_RPC, + MISC_DEVICE_TFA98XX_PROFILE, + MISC_DEVICE_TFA98XX_IOCTL, + MISC_DEVICE_MAX +}; + +struct tfa98xx_miscdevice_info { + char devicename[255]; + struct file_operations operations; +}; + +enum TFA_DEVICE_TYPE { + TFA_DEVICE_TYPE_9894, + TFA_DEVICE_TYPE_9874_PRIMARY, + TFA_DEVICE_TYPE_9874_SECONDARY, + TFA_DEVICE_TYPE_MAX +}; + +enum TFA_DEVICE_MUTE { + TFA98XX_DEVICE_MUTE_OFF = 0, + TFA98XX_DEVICE_MUTE_ON, +}; + +enum { + IOCTL_CMD_GET_MEMTRACK_DATA = 0, + IOCTL_CMD_GET_CNT_VERSION, +}; + +enum { + MEMTRACK_ITEM_SPEAKER_F0 = 0, + MEMTRACK_ITEM_SPEAKER_TEMPERATURE, + MEMTRACK_ITEM_SPEAKER_IMPEDANCE, + MEMTRACK_ITEM_MAX +}; + +struct livedata_cfg { + int address; + int track; + int scaler; +}; + +struct tfa98xx_firmware { + void *base; + struct tfa98xx_device *dev; + char name[9]; //TODO get length from tfa parameter defs +}; + +struct tfa98xx_baseprofile { + char basename[MAX_CONTROL_NAME]; /* profile basename */ + int len; /* profile length */ + int item_id; /* profile id */ + int sr_rate_sup + [TFA98XX_NUM_RATES]; /* sample rates supported by this profile */ + struct list_head list; /* list of all profiles */ +}; + +struct tfa98xx { + struct regmap *regmap; + struct i2c_client *i2c; + struct regulator *vdd; + struct snd_soc_codec *codec; + struct workqueue_struct *tfa98xx_wq; + struct delayed_work init_work; + struct delayed_work monitor_work; + struct delayed_work interrupt_work; + struct delayed_work tapdet_work; + struct mutex dsp_lock; + int dsp_init; + int dsp_fw_state; + int sysclk; + int rst_gpio; + u16 rev; + int audio_mode; + struct tfa98xx_firmware fw; + char *fw_name; + int rate; + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ + u8 pcm_format; + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ + wait_queue_head_t wq; + struct device *dev; + unsigned int init_count; + int pstream; + int cstream; + struct input_dev *input; + bool tapdet_enabled; /* service enabled */ + bool tapdet_open; /* device file opened */ + unsigned int tapdet_profiles; /* tapdet profile bitfield */ + bool tapdet_poll; /* tapdet running on polling mode */ + + unsigned int rate_constraint_list[TFA98XX_NUM_RATES]; + struct snd_pcm_hw_constraint_list rate_constraint; + + int reset_gpio; + int power_gpio; + int irq_gpio; + + struct list_head list; + struct tfa_device *tfa; + int vstep; + int profile; + int prof_vsteps + [TFACONT_MAXPROFS]; /* store vstep per profile (single device) */ + +#ifdef CONFIG_DEBUG_FS + struct dentry *dbg_dir; +#endif + u8 reg; + unsigned int flags; + bool set_mtp_cal; + uint16_t cal_data; + enum TFA_DEVICE_MUTE tfa_mute_mode; + + struct device_node *spk_id_gpio_p; + + struct miscdevice tfa98xx_reg; + struct miscdevice tfa98xx_rw; + struct miscdevice tfa98xx_rpc; + struct miscdevice tfa98xx_profile; + struct miscdevice tfa98xx_control; +}; + +#endif /* __TFA98XX_INC__ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_genregs_N1C.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_genregs_N1C.h new file mode 100644 index 000000000000..719f09ef1776 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_genregs_N1C.h @@ -0,0 +1,3795 @@ +/** Filename: Tfa98xx_genregs.h + * This file was generated automatically on 09/01/15 at 09:40:23. + * Source file: TFA9888_N1C_I2C_regmap_V1.xlsx + */ + +#ifndef TFA2_GENREGS_H +#define TFA2_GENREGS_H + +#define TFA98XX_SYS_CONTROL0 0x00 +#define TFA98XX_SYS_CONTROL1 0x01 +#define TFA98XX_SYS_CONTROL2 0x02 +#define TFA98XX_DEVICE_REVISION 0x03 +#define TFA98XX_CLOCK_CONTROL 0x04 +#define TFA98XX_CLOCK_GATING_CONTROL 0x05 +#define TFA98XX_SIDE_TONE_CONFIG 0x0d +#define TFA98XX_CTRL_DIGTOANA_REG 0x0e +#define TFA98XX_STATUS_FLAGS0 0x10 +#define TFA98XX_STATUS_FLAGS1 0x11 +#define TFA98XX_STATUS_FLAGS2 0x12 +#define TFA98XX_STATUS_FLAGS3 0x13 +#define TFA98XX_STATUS_FLAGS4 0x14 +#define TFA98XX_BATTERY_VOLTAGE 0x15 +#define TFA98XX_TEMPERATURE 0x16 +#define TFA98XX_TDM_CONFIG0 0x20 +#define TFA98XX_TDM_CONFIG1 0x21 +#define TFA98XX_TDM_CONFIG2 0x22 +#define TFA98XX_TDM_CONFIG3 0x23 +#define TFA98XX_TDM_CONFIG4 0x24 +#define TFA98XX_TDM_CONFIG5 0x25 +#define TFA98XX_TDM_CONFIG6 0x26 +#define TFA98XX_TDM_CONFIG7 0x27 +#define TFA98XX_TDM_CONFIG8 0x28 +#define TFA98XX_TDM_CONFIG9 0x29 +#define TFA98XX_PDM_CONFIG0 0x31 +#define TFA98XX_PDM_CONFIG1 0x32 +#define TFA98XX_HAPTIC_DRIVER_CONFIG 0x33 +#define TFA98XX_GPIO_DATAIN_REG 0x34 +#define TFA98XX_GPIO_CONFIG 0x35 +#define TFA98XX_INTERRUPT_OUT_REG1 0x40 +#define TFA98XX_INTERRUPT_OUT_REG2 0x41 +#define TFA98XX_INTERRUPT_OUT_REG3 0x42 +#define TFA98XX_INTERRUPT_IN_REG1 0x44 +#define TFA98XX_INTERRUPT_IN_REG2 0x45 +#define TFA98XX_INTERRUPT_IN_REG3 0x46 +#define TFA98XX_INTERRUPT_ENABLE_REG1 0x48 +#define TFA98XX_INTERRUPT_ENABLE_REG2 0x49 +#define TFA98XX_INTERRUPT_ENABLE_REG3 0x4a +#define TFA98XX_STATUS_POLARITY_REG1 0x4c +#define TFA98XX_STATUS_POLARITY_REG2 0x4d +#define TFA98XX_STATUS_POLARITY_REG3 0x4e +#define TFA98XX_BAT_PROT_CONFIG 0x50 +#define TFA98XX_AUDIO_CONTROL 0x51 +#define TFA98XX_AMPLIFIER_CONFIG 0x52 +#define TFA98XX_AUDIO_CONTROL2 0x5a +#define TFA98XX_DCDC_CONTROL0 0x70 +#define TFA98XX_CF_CONTROLS 0x90 +#define TFA98XX_CF_MAD 0x91 +#define TFA98XX_CF_MEM 0x92 +#define TFA98XX_CF_STATUS 0x93 +#define TFA98XX_MTPKEY2_REG 0xa1 +#define TFA98XX_MTP_STATUS 0xa2 +#define TFA98XX_KEY_PROTECTED_MTP_CONTROL 0xa3 +#define TFA98XX_MTP_DATA_OUT_MSB 0xa5 +#define TFA98XX_MTP_DATA_OUT_LSB 0xa6 +#define TFA98XX_TEMP_SENSOR_CONFIG 0xb1 +#define TFA98XX_KEY2_PROTECTED_MTP0 0xf0 +#define TFA98XX_KEY1_PROTECTED_MTP4 0xf4 +#define TFA98XX_KEY1_PROTECTED_MTP5 0xf5 + +/* + * (0x00)-sys_control0 + */ + +/* + * powerdown + */ +#define TFA98XX_SYS_CONTROL0_PWDN (0x1 << 0) +#define TFA98XX_SYS_CONTROL0_PWDN_POS 0 +#define TFA98XX_SYS_CONTROL0_PWDN_LEN 1 +#define TFA98XX_SYS_CONTROL0_PWDN_MAX 1 +#define TFA98XX_SYS_CONTROL0_PWDN_MSK 0x1 + +/* + * reset + */ +#define TFA98XX_SYS_CONTROL0_I2CR (0x1 << 1) +#define TFA98XX_SYS_CONTROL0_I2CR_POS 1 +#define TFA98XX_SYS_CONTROL0_I2CR_LEN 1 +#define TFA98XX_SYS_CONTROL0_I2CR_MAX 1 +#define TFA98XX_SYS_CONTROL0_I2CR_MSK 0x2 + +/* + * enbl_coolflux + */ +#define TFA98XX_SYS_CONTROL0_CFE (0x1 << 2) +#define TFA98XX_SYS_CONTROL0_CFE_POS 2 +#define TFA98XX_SYS_CONTROL0_CFE_LEN 1 +#define TFA98XX_SYS_CONTROL0_CFE_MAX 1 +#define TFA98XX_SYS_CONTROL0_CFE_MSK 0x4 + +/* + * enbl_amplifier + */ +#define TFA98XX_SYS_CONTROL0_AMPE (0x1 << 3) +#define TFA98XX_SYS_CONTROL0_AMPE_POS 3 +#define TFA98XX_SYS_CONTROL0_AMPE_LEN 1 +#define TFA98XX_SYS_CONTROL0_AMPE_MAX 1 +#define TFA98XX_SYS_CONTROL0_AMPE_MSK 0x8 + +/* + * enbl_boost + */ +#define TFA98XX_SYS_CONTROL0_DCA (0x1 << 4) +#define TFA98XX_SYS_CONTROL0_DCA_POS 4 +#define TFA98XX_SYS_CONTROL0_DCA_LEN 1 +#define TFA98XX_SYS_CONTROL0_DCA_MAX 1 +#define TFA98XX_SYS_CONTROL0_DCA_MSK 0x10 + +/* + * coolflux_configured + */ +#define TFA98XX_SYS_CONTROL0_SBSL (0x1 << 5) +#define TFA98XX_SYS_CONTROL0_SBSL_POS 5 +#define TFA98XX_SYS_CONTROL0_SBSL_LEN 1 +#define TFA98XX_SYS_CONTROL0_SBSL_MAX 1 +#define TFA98XX_SYS_CONTROL0_SBSL_MSK 0x20 + +/* + * sel_enbl_amplifier + */ +#define TFA98XX_SYS_CONTROL0_AMPC (0x1 << 6) +#define TFA98XX_SYS_CONTROL0_AMPC_POS 6 +#define TFA98XX_SYS_CONTROL0_AMPC_LEN 1 +#define TFA98XX_SYS_CONTROL0_AMPC_MAX 1 +#define TFA98XX_SYS_CONTROL0_AMPC_MSK 0x40 + +/* + * int_pad_io + */ +#define TFA98XX_SYS_CONTROL0_INTP (0x3 << 7) +#define TFA98XX_SYS_CONTROL0_INTP_POS 7 +#define TFA98XX_SYS_CONTROL0_INTP_LEN 2 +#define TFA98XX_SYS_CONTROL0_INTP_MAX 3 +#define TFA98XX_SYS_CONTROL0_INTP_MSK 0x180 + +/* + * fs_pulse_sel + */ +#define TFA98XX_SYS_CONTROL0_FSSSEL (0x3 << 9) +#define TFA98XX_SYS_CONTROL0_FSSSEL_POS 9 +#define TFA98XX_SYS_CONTROL0_FSSSEL_LEN 2 +#define TFA98XX_SYS_CONTROL0_FSSSEL_MAX 3 +#define TFA98XX_SYS_CONTROL0_FSSSEL_MSK 0x600 + +/* + * bypass_ocp + */ +#define TFA98XX_SYS_CONTROL0_BYPOCP (0x1 << 11) +#define TFA98XX_SYS_CONTROL0_BYPOCP_POS 11 +#define TFA98XX_SYS_CONTROL0_BYPOCP_LEN 1 +#define TFA98XX_SYS_CONTROL0_BYPOCP_MAX 1 +#define TFA98XX_SYS_CONTROL0_BYPOCP_MSK 0x800 + +/* + * test_ocp + */ +#define TFA98XX_SYS_CONTROL0_TSTOCP (0x1 << 12) +#define TFA98XX_SYS_CONTROL0_TSTOCP_POS 12 +#define TFA98XX_SYS_CONTROL0_TSTOCP_LEN 1 +#define TFA98XX_SYS_CONTROL0_TSTOCP_MAX 1 +#define TFA98XX_SYS_CONTROL0_TSTOCP_MSK 0x1000 + +/* + * (0x01)-sys_control1 + */ + +/* + * vamp_sel + */ +#define TFA98XX_SYS_CONTROL1_AMPINSEL (0x3 << 0) +#define TFA98XX_SYS_CONTROL1_AMPINSEL_POS 0 +#define TFA98XX_SYS_CONTROL1_AMPINSEL_LEN 2 +#define TFA98XX_SYS_CONTROL1_AMPINSEL_MAX 3 +#define TFA98XX_SYS_CONTROL1_AMPINSEL_MSK 0x3 + +/* + * src_set_configured + */ +#define TFA98XX_SYS_CONTROL1_MANSCONF (0x1 << 2) +#define TFA98XX_SYS_CONTROL1_MANSCONF_POS 2 +#define TFA98XX_SYS_CONTROL1_MANSCONF_LEN 1 +#define TFA98XX_SYS_CONTROL1_MANSCONF_MAX 1 +#define TFA98XX_SYS_CONTROL1_MANSCONF_MSK 0x4 + +/* + * execute_cold_start + */ +#define TFA98XX_SYS_CONTROL1_MANCOLD (0x1 << 3) +#define TFA98XX_SYS_CONTROL1_MANCOLD_POS 3 +#define TFA98XX_SYS_CONTROL1_MANCOLD_LEN 1 +#define TFA98XX_SYS_CONTROL1_MANCOLD_MAX 1 +#define TFA98XX_SYS_CONTROL1_MANCOLD_MSK 0x8 + +/* + * enbl_osc1m_auto_off + */ +#define TFA98XX_SYS_CONTROL1_MANAOOSC (0x1 << 4) +#define TFA98XX_SYS_CONTROL1_MANAOOSC_POS 4 +#define TFA98XX_SYS_CONTROL1_MANAOOSC_LEN 1 +#define TFA98XX_SYS_CONTROL1_MANAOOSC_MAX 1 +#define TFA98XX_SYS_CONTROL1_MANAOOSC_MSK 0x10 + +/* + * man_enbl_brown_out + */ +#define TFA98XX_SYS_CONTROL1_MANROBOD (0x1 << 5) +#define TFA98XX_SYS_CONTROL1_MANROBOD_POS 5 +#define TFA98XX_SYS_CONTROL1_MANROBOD_LEN 1 +#define TFA98XX_SYS_CONTROL1_MANROBOD_MAX 1 +#define TFA98XX_SYS_CONTROL1_MANROBOD_MSK 0x20 + +/* + * enbl_bod + */ +#define TFA98XX_SYS_CONTROL1_BODE (0x1 << 6) +#define TFA98XX_SYS_CONTROL1_BODE_POS 6 +#define TFA98XX_SYS_CONTROL1_BODE_LEN 1 +#define TFA98XX_SYS_CONTROL1_BODE_MAX 1 +#define TFA98XX_SYS_CONTROL1_BODE_MSK 0x40 + +/* + * enbl_bod_hyst + */ +#define TFA98XX_SYS_CONTROL1_BODHYS (0x1 << 7) +#define TFA98XX_SYS_CONTROL1_BODHYS_POS 7 +#define TFA98XX_SYS_CONTROL1_BODHYS_LEN 1 +#define TFA98XX_SYS_CONTROL1_BODHYS_MAX 1 +#define TFA98XX_SYS_CONTROL1_BODHYS_MSK 0x80 + +/* + * bod_delay + */ +#define TFA98XX_SYS_CONTROL1_BODFILT (0x3 << 8) +#define TFA98XX_SYS_CONTROL1_BODFILT_POS 8 +#define TFA98XX_SYS_CONTROL1_BODFILT_LEN 2 +#define TFA98XX_SYS_CONTROL1_BODFILT_MAX 3 +#define TFA98XX_SYS_CONTROL1_BODFILT_MSK 0x300 + +/* + * bod_lvlsel + */ +#define TFA98XX_SYS_CONTROL1_BODTHLVL (0x3 << 10) +#define TFA98XX_SYS_CONTROL1_BODTHLVL_POS 10 +#define TFA98XX_SYS_CONTROL1_BODTHLVL_LEN 2 +#define TFA98XX_SYS_CONTROL1_BODTHLVL_MAX 3 +#define TFA98XX_SYS_CONTROL1_BODTHLVL_MSK 0xc00 + +/* + * disable_mute_time_out + */ +#define TFA98XX_SYS_CONTROL1_MUTETO (0x1 << 13) +#define TFA98XX_SYS_CONTROL1_MUTETO_POS 13 +#define TFA98XX_SYS_CONTROL1_MUTETO_LEN 1 +#define TFA98XX_SYS_CONTROL1_MUTETO_MAX 1 +#define TFA98XX_SYS_CONTROL1_MUTETO_MSK 0x2000 + +/* + * pwm_sel_rcv_ns + */ +#define TFA98XX_SYS_CONTROL1_RCVNS (0x1 << 14) +#define TFA98XX_SYS_CONTROL1_RCVNS_POS 14 +#define TFA98XX_SYS_CONTROL1_RCVNS_LEN 1 +#define TFA98XX_SYS_CONTROL1_RCVNS_MAX 1 +#define TFA98XX_SYS_CONTROL1_RCVNS_MSK 0x4000 + +/* + * man_enbl_watchdog + */ +#define TFA98XX_SYS_CONTROL1_MANWDE (0x1 << 15) +#define TFA98XX_SYS_CONTROL1_MANWDE_POS 15 +#define TFA98XX_SYS_CONTROL1_MANWDE_LEN 1 +#define TFA98XX_SYS_CONTROL1_MANWDE_MAX 1 +#define TFA98XX_SYS_CONTROL1_MANWDE_MSK 0x8000 + +/* + * (0x02)-sys_control2 + */ + +/* + * audio_fs + */ +#define TFA98XX_SYS_CONTROL2_AUDFS (0xf << 0) +#define TFA98XX_SYS_CONTROL2_AUDFS_POS 0 +#define TFA98XX_SYS_CONTROL2_AUDFS_LEN 4 +#define TFA98XX_SYS_CONTROL2_AUDFS_MAX 15 +#define TFA98XX_SYS_CONTROL2_AUDFS_MSK 0xf + +/* + * input_level + */ +#define TFA98XX_SYS_CONTROL2_INPLEV (0x1 << 4) +#define TFA98XX_SYS_CONTROL2_INPLEV_POS 4 +#define TFA98XX_SYS_CONTROL2_INPLEV_LEN 1 +#define TFA98XX_SYS_CONTROL2_INPLEV_MAX 1 +#define TFA98XX_SYS_CONTROL2_INPLEV_MSK 0x10 + +/* + * cs_frac_delay + */ +#define TFA98XX_SYS_CONTROL2_FRACTDEL (0x3f << 5) +#define TFA98XX_SYS_CONTROL2_FRACTDEL_POS 5 +#define TFA98XX_SYS_CONTROL2_FRACTDEL_LEN 6 +#define TFA98XX_SYS_CONTROL2_FRACTDEL_MAX 63 +#define TFA98XX_SYS_CONTROL2_FRACTDEL_MSK 0x7e0 + +/* + * bypass_hvbat_filter + */ +#define TFA98XX_SYS_CONTROL2_BYPHVBF (0x1 << 11) +#define TFA98XX_SYS_CONTROL2_BYPHVBF_POS 11 +#define TFA98XX_SYS_CONTROL2_BYPHVBF_LEN 1 +#define TFA98XX_SYS_CONTROL2_BYPHVBF_MAX 1 +#define TFA98XX_SYS_CONTROL2_BYPHVBF_MSK 0x800 + +/* + * ctrl_rcvldop_bypass + */ +#define TFA98XX_SYS_CONTROL2_LDOBYP (0x1 << 12) +#define TFA98XX_SYS_CONTROL2_LDOBYP_POS 12 +#define TFA98XX_SYS_CONTROL2_LDOBYP_LEN 1 +#define TFA98XX_SYS_CONTROL2_LDOBYP_MAX 1 +#define TFA98XX_SYS_CONTROL2_LDOBYP_MSK 0x1000 + +/* + * (0x03)-device_revision + */ + +/* + * device_rev + */ +#define TFA98XX_DEVICE_REVISION_REV (0xffff << 0) +#define TFA98XX_DEVICE_REVISION_REV_POS 0 +#define TFA98XX_DEVICE_REVISION_REV_LEN 16 +#define TFA98XX_DEVICE_REVISION_REV_MAX 65535 +#define TFA98XX_DEVICE_REVISION_REV_MSK 0xffff + +/* + * (0x04)-clock_control + */ + +/* + * pll_clkin_sel + */ +#define TFA98XX_CLOCK_CONTROL_REFCKEXT (0x3 << 0) +#define TFA98XX_CLOCK_CONTROL_REFCKEXT_POS 0 +#define TFA98XX_CLOCK_CONTROL_REFCKEXT_LEN 2 +#define TFA98XX_CLOCK_CONTROL_REFCKEXT_MAX 3 +#define TFA98XX_CLOCK_CONTROL_REFCKEXT_MSK 0x3 + +/* + * pll_clkin_sel_osc + */ +#define TFA98XX_CLOCK_CONTROL_REFCKSEL (0x1 << 2) +#define TFA98XX_CLOCK_CONTROL_REFCKSEL_POS 2 +#define TFA98XX_CLOCK_CONTROL_REFCKSEL_LEN 1 +#define TFA98XX_CLOCK_CONTROL_REFCKSEL_MAX 1 +#define TFA98XX_CLOCK_CONTROL_REFCKSEL_MSK 0x4 + +/* + * (0x05)-clock_gating_control + */ + +/* + * enbl_spkr_ss_left + */ +#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE (0x1 << 0) +#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_POS 0 +#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_LEN 1 +#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_MAX 1 +#define TFA98XX_CLOCK_GATING_CONTROL_SSLEFTE_MSK 0x1 + +/* + * enbl_spkr_ss_right + */ +#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE (0x1 << 1) +#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_POS 1 +#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_LEN 1 +#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_MAX 1 +#define TFA98XX_CLOCK_GATING_CONTROL_SSRIGHTE_MSK 0x2 + +/* + * enbl_volsense_left + */ +#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE (0x1 << 2) +#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_POS 2 +#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_LEN 1 +#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_MAX 1 +#define TFA98XX_CLOCK_GATING_CONTROL_VSLEFTE_MSK 0x4 + +/* + * enbl_volsense_right + */ +#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE (0x1 << 3) +#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_POS 3 +#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_LEN 1 +#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_MAX 1 +#define TFA98XX_CLOCK_GATING_CONTROL_VSRIGHTE_MSK 0x8 + +/* + * enbl_cursense_left + */ +#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE (0x1 << 4) +#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_POS 4 +#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_LEN 1 +#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_MAX 1 +#define TFA98XX_CLOCK_GATING_CONTROL_CSLEFTE_MSK 0x10 + +/* + * enbl_cursense_right + */ +#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE (0x1 << 5) +#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_POS 5 +#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_LEN 1 +#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_MAX 1 +#define TFA98XX_CLOCK_GATING_CONTROL_CSRIGHTE_MSK 0x20 + +/* + * enbl_pdm_ss + */ +#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME (0x1 << 6) +#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_POS 6 +#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_LEN 1 +#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_MAX 1 +#define TFA98XX_CLOCK_GATING_CONTROL_SSPDME_MSK 0x40 + +/* + * (0x0d)-side_tone_config + */ + +/* + * side_tone_gain + */ +#define TFA98XX_SIDE_TONE_CONFIG_STGAIN (0x1ff << 1) +#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_POS 1 +#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_LEN 9 +#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_MAX 511 +#define TFA98XX_SIDE_TONE_CONFIG_STGAIN_MSK 0x3fe + +/* + * mute_side_tone + */ +#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE (0x1 << 10) +#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_POS 10 +#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_LEN 1 +#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_MAX 1 +#define TFA98XX_SIDE_TONE_CONFIG_PDMSMUTE_MSK 0x400 + +/* + * (0x0e)-ctrl_digtoana_reg + */ + +/* + * ctrl_digtoana + */ +#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP (0x7f << 0) +#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_POS 0 +#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_LEN 7 +#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_MAX 127 +#define TFA98XX_CTRL_DIGTOANA_REG_SWVSTEP_MSK 0x7f + +/* + * (0x10)-status_flags0 + */ + +/* + * flag_por + */ +#define TFA98XX_STATUS_FLAGS0_VDDS (0x1 << 0) +#define TFA98XX_STATUS_FLAGS0_VDDS_POS 0 +#define TFA98XX_STATUS_FLAGS0_VDDS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_VDDS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_VDDS_MSK 0x1 + +/* + * flag_pll_lock + */ +#define TFA98XX_STATUS_FLAGS0_PLLS (0x1 << 1) +#define TFA98XX_STATUS_FLAGS0_PLLS_POS 1 +#define TFA98XX_STATUS_FLAGS0_PLLS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_PLLS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_PLLS_MSK 0x2 + +/* + * flag_otpok + */ +#define TFA98XX_STATUS_FLAGS0_OTDS (0x1 << 2) +#define TFA98XX_STATUS_FLAGS0_OTDS_POS 2 +#define TFA98XX_STATUS_FLAGS0_OTDS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_OTDS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_OTDS_MSK 0x4 + +/* + * flag_ovpok + */ +#define TFA98XX_STATUS_FLAGS0_OVDS (0x1 << 3) +#define TFA98XX_STATUS_FLAGS0_OVDS_POS 3 +#define TFA98XX_STATUS_FLAGS0_OVDS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_OVDS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_OVDS_MSK 0x8 + +/* + * flag_uvpok + */ +#define TFA98XX_STATUS_FLAGS0_UVDS (0x1 << 4) +#define TFA98XX_STATUS_FLAGS0_UVDS_POS 4 +#define TFA98XX_STATUS_FLAGS0_UVDS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_UVDS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_UVDS_MSK 0x10 + +/* + * flag_clocks_stable + */ +#define TFA98XX_STATUS_FLAGS0_CLKS (0x1 << 6) +#define TFA98XX_STATUS_FLAGS0_CLKS_POS 5 +#define TFA98XX_STATUS_FLAGS0_CLKS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_CLKS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_CLKS_MSK 0x20 + +/* + * flag_mtp_busy + */ +#define TFA98XX_STATUS_FLAGS0_MTPB (0x1 < 7) +#define TFA98XX_STATUS_FLAGS0_MTPB_POS 7 +#define TFA98XX_STATUS_FLAGS0_MTPB_LEN 1 +#define TFA98XX_STATUS_FLAGS0_MTPB_MAX 1 +#define TFA98XX_STATUS_FLAGS0_MTPB_MSK 0x40 + +/* + * flag_lost_clk + */ +#define TFA98XX_STATUS_FLAGS0_NOCLK (0x1 << 8) +#define TFA98XX_STATUS_FLAGS0_NOCLK_POS 8 +#define TFA98XX_STATUS_FLAGS0_NOCLK_LEN 1 +#define TFA98XX_STATUS_FLAGS0_NOCLK_MAX 1 +#define TFA98XX_STATUS_FLAGS0_NOCLK_MSK 0x80 + +#if 0 +/* + * flag_cf_speakererror + */ +#define TFA98XX_STATUS_FLAGS0_SPKS (0x1 << 8) +#define TFA98XX_STATUS_FLAGS0_SPKS_POS 8 +#define TFA98XX_STATUS_FLAGS0_SPKS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_SPKS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_SPKS_MSK 0x100 +#endif + +/* + * flag_cold_started + */ +#define TFA98XX_STATUS_FLAGS0_ACS (0x1 << 9) +#define TFA98XX_STATUS_FLAGS0_ACS_POS 9 +#define TFA98XX_STATUS_FLAGS0_ACS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_ACS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_ACS_MSK 0x200 + +/* + * flag_engage + */ +#define TFA98XX_STATUS_FLAGS0_SWS (0x1 << 11) +#define TFA98XX_STATUS_FLAGS0_SWS_POS 11 +#define TFA98XX_STATUS_FLAGS0_SWS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_SWS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_SWS_MSK 0x400 + +/* + * flag_watchdog_reset + */ +#define TFA98XX_STATUS_FLAGS0_WDS (0x1 << 10) +#define TFA98XX_STATUS_FLAGS0_WDS_POS 10 +#define TFA98XX_STATUS_FLAGS0_WDS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_WDS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_WDS_MSK 0x800 + +/* + * flag_enbl_amp + */ +#define TFA98XX_STATUS_FLAGS0_AMPS (0x1 << 12) +#define TFA98XX_STATUS_FLAGS0_AMPS_POS 12 +#define TFA98XX_STATUS_FLAGS0_AMPS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_AMPS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_AMPS_MSK 0x1000 + +/* + * flag_enbl_ref + */ +#define TFA98XX_STATUS_FLAGS0_AREFS (0x1 << 13) +#define TFA98XX_STATUS_FLAGS0_AREFS_POS 13 +#define TFA98XX_STATUS_FLAGS0_AREFS_LEN 1 +#define TFA98XX_STATUS_FLAGS0_AREFS_MAX 1 +#define TFA98XX_STATUS_FLAGS0_AREFS_MSK 0x2000 + +/* + * flag_adc10_ready + */ +#define TFA98XX_STATUS_FLAGS0_ADCCR (0x1 << 14) +#define TFA98XX_STATUS_FLAGS0_ADCCR_POS 14 +#define TFA98XX_STATUS_FLAGS0_ADCCR_LEN 1 +#define TFA98XX_STATUS_FLAGS0_ADCCR_MAX 1 +#define TFA98XX_STATUS_FLAGS0_ADCCR_MSK 0x4000 + +/* + * flag_bod_vddd_nok + */ +#define TFA98XX_STATUS_FLAGS0_BODNOK (0x1 << 15) +#define TFA98XX_STATUS_FLAGS0_BODNOK_POS 15 +#define TFA98XX_STATUS_FLAGS0_BODNOK_LEN 1 +#define TFA98XX_STATUS_FLAGS0_BODNOK_MAX 1 +#define TFA98XX_STATUS_FLAGS0_BODNOK_MSK 0x8000 + +/* + * (0x11)-status_flags1 + */ + +/* + * flag_bst_bstcur + */ +#define TFA98XX_STATUS_FLAGS1_DCIL (0x1 << 0) +#define TFA98XX_STATUS_FLAGS1_DCIL_POS 0 +#define TFA98XX_STATUS_FLAGS1_DCIL_LEN 1 +#define TFA98XX_STATUS_FLAGS1_DCIL_MAX 1 +#define TFA98XX_STATUS_FLAGS1_DCIL_MSK 0x1 + +/* + * flag_bst_hiz + */ +#define TFA98XX_STATUS_FLAGS1_DCDCA (0x1 << 1) +#define TFA98XX_STATUS_FLAGS1_DCDCA_POS 1 +#define TFA98XX_STATUS_FLAGS1_DCDCA_LEN 1 +#define TFA98XX_STATUS_FLAGS1_DCDCA_MAX 1 +#define TFA98XX_STATUS_FLAGS1_DCDCA_MSK 0x2 + +/* + * flag_bst_ocpok + */ +#define TFA98XX_STATUS_FLAGS1_DCOCPOK (0x1 << 2) +#define TFA98XX_STATUS_FLAGS1_DCOCPOK_POS 2 +#define TFA98XX_STATUS_FLAGS1_DCOCPOK_LEN 1 +#define TFA98XX_STATUS_FLAGS1_DCOCPOK_MAX 1 +#define TFA98XX_STATUS_FLAGS1_DCOCPOK_MSK 0x4 + +/* + * flag_bst_voutcomp + */ +#define TFA98XX_STATUS_FLAGS1_DCHVBAT (0x1 << 4) +#define TFA98XX_STATUS_FLAGS1_DCHVBAT_POS 4 +#define TFA98XX_STATUS_FLAGS1_DCHVBAT_LEN 1 +#define TFA98XX_STATUS_FLAGS1_DCHVBAT_MAX 1 +#define TFA98XX_STATUS_FLAGS1_DCHVBAT_MSK 0x10 + +/* + * flag_bst_voutcomp86 + */ +#define TFA98XX_STATUS_FLAGS1_DCH114 (0x1 << 5) +#define TFA98XX_STATUS_FLAGS1_DCH114_POS 5 +#define TFA98XX_STATUS_FLAGS1_DCH114_LEN 1 +#define TFA98XX_STATUS_FLAGS1_DCH114_MAX 1 +#define TFA98XX_STATUS_FLAGS1_DCH114_MSK 0x20 + +/* + * flag_bst_voutcomp93 + */ +#define TFA98XX_STATUS_FLAGS1_DCH107 (0x1 << 6) +#define TFA98XX_STATUS_FLAGS1_DCH107_POS 6 +#define TFA98XX_STATUS_FLAGS1_DCH107_LEN 1 +#define TFA98XX_STATUS_FLAGS1_DCH107_MAX 1 +#define TFA98XX_STATUS_FLAGS1_DCH107_MSK 0x40 + +/* + * flag_soft_mute_busy + */ +#define TFA98XX_STATUS_FLAGS1_STMUTEB (0x1 << 7) +#define TFA98XX_STATUS_FLAGS1_STMUTEB_POS 7 +#define TFA98XX_STATUS_FLAGS1_STMUTEB_LEN 1 +#define TFA98XX_STATUS_FLAGS1_STMUTEB_MAX 1 +#define TFA98XX_STATUS_FLAGS1_STMUTEB_MSK 0x80 + +/* + * flag_soft_mute_state + */ +#define TFA98XX_STATUS_FLAGS1_STMUTE (0x1 << 8) +#define TFA98XX_STATUS_FLAGS1_STMUTE_POS 8 +#define TFA98XX_STATUS_FLAGS1_STMUTE_LEN 1 +#define TFA98XX_STATUS_FLAGS1_STMUTE_MAX 1 +#define TFA98XX_STATUS_FLAGS1_STMUTE_MSK 0x100 + +/* + * flag_tdm_lut_error + */ +#define TFA98XX_STATUS_FLAGS1_TDMLUTER (0x1 << 9) +#define TFA98XX_STATUS_FLAGS1_TDMLUTER_POS 9 +#define TFA98XX_STATUS_FLAGS1_TDMLUTER_LEN 1 +#define TFA98XX_STATUS_FLAGS1_TDMLUTER_MAX 1 +#define TFA98XX_STATUS_FLAGS1_TDMLUTER_MSK 0x200 + +/* + * flag_tdm_status + */ +#define TFA98XX_STATUS_FLAGS1_TDMSTAT (0x7 << 10) +#define TFA98XX_STATUS_FLAGS1_TDMSTAT_POS 10 +#define TFA98XX_STATUS_FLAGS1_TDMSTAT_LEN 3 +#define TFA98XX_STATUS_FLAGS1_TDMSTAT_MAX 7 +#define TFA98XX_STATUS_FLAGS1_TDMSTAT_MSK 0x1c00 + +/* + * flag_tdm_error + */ +#define TFA98XX_STATUS_FLAGS1_TDMERR (0x1 << 13) +#define TFA98XX_STATUS_FLAGS1_TDMERR_POS 13 +#define TFA98XX_STATUS_FLAGS1_TDMERR_LEN 1 +#define TFA98XX_STATUS_FLAGS1_TDMERR_MAX 1 +#define TFA98XX_STATUS_FLAGS1_TDMERR_MSK 0x2000 + +/* + * flag_haptic_busy + */ +#define TFA98XX_STATUS_FLAGS1_HAPTIC (0x1 << 14) +#define TFA98XX_STATUS_FLAGS1_HAPTIC_POS 14 +#define TFA98XX_STATUS_FLAGS1_HAPTIC_LEN 1 +#define TFA98XX_STATUS_FLAGS1_HAPTIC_MAX 1 +#define TFA98XX_STATUS_FLAGS1_HAPTIC_MSK 0x4000 + +/* + * (0x12)-status_flags2 + */ + +/* + * flag_ocpokap_left + */ +#define TFA98XX_STATUS_FLAGS2_OCPOAPL (0x1 << 0) +#define TFA98XX_STATUS_FLAGS2_OCPOAPL_POS 0 +#define TFA98XX_STATUS_FLAGS2_OCPOAPL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOAPL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOAPL_MSK 0x1 + +/* + * flag_ocpokan_left + */ +#define TFA98XX_STATUS_FLAGS2_OCPOANL (0x1 << 1) +#define TFA98XX_STATUS_FLAGS2_OCPOANL_POS 1 +#define TFA98XX_STATUS_FLAGS2_OCPOANL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOANL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOANL_MSK 0x2 + +/* + * flag_ocpokbp_left + */ +#define TFA98XX_STATUS_FLAGS2_OCPOBPL (0x1 << 2) +#define TFA98XX_STATUS_FLAGS2_OCPOBPL_POS 2 +#define TFA98XX_STATUS_FLAGS2_OCPOBPL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBPL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBPL_MSK 0x4 + +/* + * flag_ocpokbn_left + */ +#define TFA98XX_STATUS_FLAGS2_OCPOBNL (0x1 << 3) +#define TFA98XX_STATUS_FLAGS2_OCPOBNL_POS 3 +#define TFA98XX_STATUS_FLAGS2_OCPOBNL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBNL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBNL_MSK 0x8 + +/* + * flag_clipa_high_left + */ +#define TFA98XX_STATUS_FLAGS2_CLIPAHL (0x1 << 4) +#define TFA98XX_STATUS_FLAGS2_CLIPAHL_POS 4 +#define TFA98XX_STATUS_FLAGS2_CLIPAHL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_CLIPAHL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_CLIPAHL_MSK 0x10 + +/* + * flag_clipa_low_left + */ +#define TFA98XX_STATUS_FLAGS2_CLIPALL (0x1 << 5) +#define TFA98XX_STATUS_FLAGS2_CLIPALL_POS 5 +#define TFA98XX_STATUS_FLAGS2_CLIPALL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_CLIPALL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_CLIPALL_MSK 0x20 + +/* + * flag_clipb_high_left + */ +#define TFA98XX_STATUS_FLAGS2_CLIPBHL (0x1 << 6) +#define TFA98XX_STATUS_FLAGS2_CLIPBHL_POS 6 +#define TFA98XX_STATUS_FLAGS2_CLIPBHL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_CLIPBHL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_CLIPBHL_MSK 0x40 + +/* + * flag_clipb_low_left + */ +#define TFA98XX_STATUS_FLAGS2_CLIPBLL (0x1 << 7) +#define TFA98XX_STATUS_FLAGS2_CLIPBLL_POS 7 +#define TFA98XX_STATUS_FLAGS2_CLIPBLL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_CLIPBLL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_CLIPBLL_MSK 0x80 + +/* + * flag_ocpokap_rcv + */ +#define TFA98XX_STATUS_FLAGS2_OCPOAPRC (0x1 << 8) +#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_POS 8 +#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOAPRC_MSK 0x100 + +/* + * flag_ocpokan_rcv + */ +#define TFA98XX_STATUS_FLAGS2_OCPOANRC (0x1 << 9) +#define TFA98XX_STATUS_FLAGS2_OCPOANRC_POS 9 +#define TFA98XX_STATUS_FLAGS2_OCPOANRC_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOANRC_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOANRC_MSK 0x200 + +/* + * flag_ocpokbp_rcv + */ +#define TFA98XX_STATUS_FLAGS2_OCPOBPRC (0x1 << 10) +#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_POS 10 +#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBPRC_MSK 0x400 + +/* + * flag_ocpokbn_rcv + */ +#define TFA98XX_STATUS_FLAGS2_OCPOBNRC (0x1 << 11) +#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_POS 11 +#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCPOBNRC_MSK 0x800 + +/* + * flag_rcvldop_ready + */ +#define TFA98XX_STATUS_FLAGS2_RCVLDOR (0x1 << 12) +#define TFA98XX_STATUS_FLAGS2_RCVLDOR_POS 12 +#define TFA98XX_STATUS_FLAGS2_RCVLDOR_LEN 1 +#define TFA98XX_STATUS_FLAGS2_RCVLDOR_MAX 1 +#define TFA98XX_STATUS_FLAGS2_RCVLDOR_MSK 0x1000 + +/* + * flag_rcvldop_bypassready + */ +#define TFA98XX_STATUS_FLAGS2_RCVLDOBR (0x1 << 13) +#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_POS 13 +#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_LEN 1 +#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_MAX 1 +#define TFA98XX_STATUS_FLAGS2_RCVLDOBR_MSK 0x2000 + +/* + * flag_ocp_alarm_left + */ +#define TFA98XX_STATUS_FLAGS2_OCDSL (0x1 << 14) +#define TFA98XX_STATUS_FLAGS2_OCDSL_POS 14 +#define TFA98XX_STATUS_FLAGS2_OCDSL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_OCDSL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_OCDSL_MSK 0x4000 + +/* + * flag_clip_left + */ +#define TFA98XX_STATUS_FLAGS2_CLIPSL (0x1 << 15) +#define TFA98XX_STATUS_FLAGS2_CLIPSL_POS 15 +#define TFA98XX_STATUS_FLAGS2_CLIPSL_LEN 1 +#define TFA98XX_STATUS_FLAGS2_CLIPSL_MAX 1 +#define TFA98XX_STATUS_FLAGS2_CLIPSL_MSK 0x8000 + +/* + * (0x13)-status_flags3 + */ + +/* + * flag_ocpokap_right + */ +#define TFA98XX_STATUS_FLAGS3_OCPOAPR (0x1 << 0) +#define TFA98XX_STATUS_FLAGS3_OCPOAPR_POS 0 +#define TFA98XX_STATUS_FLAGS3_OCPOAPR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_OCPOAPR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_OCPOAPR_MSK 0x1 + +/* + * flag_ocpokan_right + */ +#define TFA98XX_STATUS_FLAGS3_OCPOANR (0x1 << 1) +#define TFA98XX_STATUS_FLAGS3_OCPOANR_POS 1 +#define TFA98XX_STATUS_FLAGS3_OCPOANR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_OCPOANR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_OCPOANR_MSK 0x2 + +/* + * flag_ocpokbp_right + */ +#define TFA98XX_STATUS_FLAGS3_OCPOBPR (0x1 << 2) +#define TFA98XX_STATUS_FLAGS3_OCPOBPR_POS 2 +#define TFA98XX_STATUS_FLAGS3_OCPOBPR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_OCPOBPR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_OCPOBPR_MSK 0x4 + +/* + * flag_ocpokbn_right + */ +#define TFA98XX_STATUS_FLAGS3_OCPOBNR (0x1 << 3) +#define TFA98XX_STATUS_FLAGS3_OCPOBNR_POS 3 +#define TFA98XX_STATUS_FLAGS3_OCPOBNR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_OCPOBNR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_OCPOBNR_MSK 0x8 + +/* + * flag_clipa_high_right + */ +#define TFA98XX_STATUS_FLAGS3_CLIPAHR (0x1 << 4) +#define TFA98XX_STATUS_FLAGS3_CLIPAHR_POS 4 +#define TFA98XX_STATUS_FLAGS3_CLIPAHR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_CLIPAHR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_CLIPAHR_MSK 0x10 + +/* + * flag_clipa_low_right + */ +#define TFA98XX_STATUS_FLAGS3_CLIPALR (0x1 << 5) +#define TFA98XX_STATUS_FLAGS3_CLIPALR_POS 5 +#define TFA98XX_STATUS_FLAGS3_CLIPALR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_CLIPALR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_CLIPALR_MSK 0x20 + +/* + * flag_clipb_high_right + */ +#define TFA98XX_STATUS_FLAGS3_CLIPBHR (0x1 << 6) +#define TFA98XX_STATUS_FLAGS3_CLIPBHR_POS 6 +#define TFA98XX_STATUS_FLAGS3_CLIPBHR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_CLIPBHR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_CLIPBHR_MSK 0x40 + +/* + * flag_clipb_low_right + */ +#define TFA98XX_STATUS_FLAGS3_CLIPBLR (0x1 << 7) +#define TFA98XX_STATUS_FLAGS3_CLIPBLR_POS 7 +#define TFA98XX_STATUS_FLAGS3_CLIPBLR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_CLIPBLR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_CLIPBLR_MSK 0x80 + +/* + * flag_ocp_alarm_right + */ +#define TFA98XX_STATUS_FLAGS3_OCDSR (0x1 << 8) +#define TFA98XX_STATUS_FLAGS3_OCDSR_POS 8 +#define TFA98XX_STATUS_FLAGS3_OCDSR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_OCDSR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_OCDSR_MSK 0x100 + +/* + * flag_clip_right + */ +#define TFA98XX_STATUS_FLAGS3_CLIPSR (0x1 << 9) +#define TFA98XX_STATUS_FLAGS3_CLIPSR_POS 9 +#define TFA98XX_STATUS_FLAGS3_CLIPSR_LEN 1 +#define TFA98XX_STATUS_FLAGS3_CLIPSR_MAX 1 +#define TFA98XX_STATUS_FLAGS3_CLIPSR_MSK 0x200 + +/* + * flag_mic_ocpok + */ +#define TFA98XX_STATUS_FLAGS3_OCPOKMC (0x1 << 10) +#define TFA98XX_STATUS_FLAGS3_OCPOKMC_POS 10 +#define TFA98XX_STATUS_FLAGS3_OCPOKMC_LEN 1 +#define TFA98XX_STATUS_FLAGS3_OCPOKMC_MAX 1 +#define TFA98XX_STATUS_FLAGS3_OCPOKMC_MSK 0x400 + +/* + * flag_man_alarm_state + */ +#define TFA98XX_STATUS_FLAGS3_MANALARM (0x1 << 11) +#define TFA98XX_STATUS_FLAGS3_MANALARM_POS 11 +#define TFA98XX_STATUS_FLAGS3_MANALARM_LEN 1 +#define TFA98XX_STATUS_FLAGS3_MANALARM_MAX 1 +#define TFA98XX_STATUS_FLAGS3_MANALARM_MSK 0x800 + +/* + * flag_man_wait_src_settings + */ +#define TFA98XX_STATUS_FLAGS3_MANWAIT1 (0x1 << 12) +#define TFA98XX_STATUS_FLAGS3_MANWAIT1_POS 12 +#define TFA98XX_STATUS_FLAGS3_MANWAIT1_LEN 1 +#define TFA98XX_STATUS_FLAGS3_MANWAIT1_MAX 1 +#define TFA98XX_STATUS_FLAGS3_MANWAIT1_MSK 0x1000 + +/* + * flag_man_wait_cf_config + */ +#define TFA98XX_STATUS_FLAGS3_MANWAIT2 (0x1 << 13) +#define TFA98XX_STATUS_FLAGS3_MANWAIT2_POS 13 +#define TFA98XX_STATUS_FLAGS3_MANWAIT2_LEN 1 +#define TFA98XX_STATUS_FLAGS3_MANWAIT2_MAX 1 +#define TFA98XX_STATUS_FLAGS3_MANWAIT2_MSK 0x2000 + +/* + * flag_man_start_mute_audio + */ +#define TFA98XX_STATUS_FLAGS3_MANMUTE (0x1 << 14) +#define TFA98XX_STATUS_FLAGS3_MANMUTE_POS 14 +#define TFA98XX_STATUS_FLAGS3_MANMUTE_LEN 1 +#define TFA98XX_STATUS_FLAGS3_MANMUTE_MAX 1 +#define TFA98XX_STATUS_FLAGS3_MANMUTE_MSK 0x4000 + +/* + * flag_man_operating_state + */ +#define TFA98XX_STATUS_FLAGS3_MANOPER (0x1 << 15) +#define TFA98XX_STATUS_FLAGS3_MANOPER_POS 15 +#define TFA98XX_STATUS_FLAGS3_MANOPER_LEN 1 +#define TFA98XX_STATUS_FLAGS3_MANOPER_MAX 1 +#define TFA98XX_STATUS_FLAGS3_MANOPER_MSK 0x8000 + +/* + * (0x14)-status_flags4 + */ + +/* + * flag_cf_speakererror_left + */ +#define TFA98XX_STATUS_FLAGS4_SPKSL (0x1 << 0) +#define TFA98XX_STATUS_FLAGS4_SPKSL_POS 0 +#define TFA98XX_STATUS_FLAGS4_SPKSL_LEN 1 +#define TFA98XX_STATUS_FLAGS4_SPKSL_MAX 1 +#define TFA98XX_STATUS_FLAGS4_SPKSL_MSK 0x1 + +/* + * flag_cf_speakererror_right + */ +#define TFA98XX_STATUS_FLAGS4_SPKSR (0x1 << 1) +#define TFA98XX_STATUS_FLAGS4_SPKSR_POS 1 +#define TFA98XX_STATUS_FLAGS4_SPKSR_LEN 1 +#define TFA98XX_STATUS_FLAGS4_SPKSR_MAX 1 +#define TFA98XX_STATUS_FLAGS4_SPKSR_MSK 0x2 + +/* + * flag_clk_out_of_range + */ +#define TFA98XX_STATUS_FLAGS4_CLKOOR (0x1 << 2) +#define TFA98XX_STATUS_FLAGS4_CLKOOR_POS 2 +#define TFA98XX_STATUS_FLAGS4_CLKOOR_LEN 1 +#define TFA98XX_STATUS_FLAGS4_CLKOOR_MAX 1 +#define TFA98XX_STATUS_FLAGS4_CLKOOR_MSK 0x4 + +/* + * man_state + */ +#define TFA98XX_STATUS_FLAGS4_MANSTATE (0xf << 3) +#define TFA98XX_STATUS_FLAGS4_MANSTATE_POS 3 +#define TFA98XX_STATUS_FLAGS4_MANSTATE_LEN 4 +#define TFA98XX_STATUS_FLAGS4_MANSTATE_MAX 15 +#define TFA98XX_STATUS_FLAGS4_MANSTATE_MSK 0x78 + +/* + * (0x15)-battery_voltage + */ + +/* + * bat_adc + */ +#define TFA98XX_BATTERY_VOLTAGE_BATS (0x3ff << 0) +#define TFA98XX_BATTERY_VOLTAGE_BATS_POS 0 +#define TFA98XX_BATTERY_VOLTAGE_BATS_LEN 10 +#define TFA98XX_BATTERY_VOLTAGE_BATS_MAX 1023 +#define TFA98XX_BATTERY_VOLTAGE_BATS_MSK 0x3ff + +/* + * (0x16)-temperature + */ + +/* + * temp_adc + */ +#define TFA98XX_TEMPERATURE_TEMPS (0x1ff << 0) +#define TFA98XX_TEMPERATURE_TEMPS_POS 0 +#define TFA98XX_TEMPERATURE_TEMPS_LEN 9 +#define TFA98XX_TEMPERATURE_TEMPS_MAX 511 +#define TFA98XX_TEMPERATURE_TEMPS_MSK 0x1ff + +/* + * (0x20)-tdm_config0 + */ + +/* + * tdm_usecase + */ +#define TFA98XX_TDM_CONFIG0_TDMUC (0xf << 0) +#define TFA98XX_TDM_CONFIG0_TDMUC_POS 0 +#define TFA98XX_TDM_CONFIG0_TDMUC_LEN 4 +#define TFA98XX_TDM_CONFIG0_TDMUC_MAX 15 +#define TFA98XX_TDM_CONFIG0_TDMUC_MSK 0xf + +/* + * tdm_enable + */ +#define TFA98XX_TDM_CONFIG0_TDME (0x1 << 4) +#define TFA98XX_TDM_CONFIG0_TDME_POS 4 +#define TFA98XX_TDM_CONFIG0_TDME_LEN 1 +#define TFA98XX_TDM_CONFIG0_TDME_MAX 1 +#define TFA98XX_TDM_CONFIG0_TDME_MSK 0x10 + +/* + * tdm_mode + */ +#define TFA98XX_TDM_CONFIG0_TDMMODE (0x1 << 5) +#define TFA98XX_TDM_CONFIG0_TDMMODE_POS 5 +#define TFA98XX_TDM_CONFIG0_TDMMODE_LEN 1 +#define TFA98XX_TDM_CONFIG0_TDMMODE_MAX 1 +#define TFA98XX_TDM_CONFIG0_TDMMODE_MSK 0x20 + +/* + * tdm_clk_inversion + */ +#define TFA98XX_TDM_CONFIG0_TDMCLINV (0x1 << 6) +#define TFA98XX_TDM_CONFIG0_TDMCLINV_POS 6 +#define TFA98XX_TDM_CONFIG0_TDMCLINV_LEN 1 +#define TFA98XX_TDM_CONFIG0_TDMCLINV_MAX 1 +#define TFA98XX_TDM_CONFIG0_TDMCLINV_MSK 0x40 + +/* + * tdm_fs_ws_length + */ +#define TFA98XX_TDM_CONFIG0_TDMFSLN (0xf << 7) +#define TFA98XX_TDM_CONFIG0_TDMFSLN_POS 7 +#define TFA98XX_TDM_CONFIG0_TDMFSLN_LEN 4 +#define TFA98XX_TDM_CONFIG0_TDMFSLN_MAX 15 +#define TFA98XX_TDM_CONFIG0_TDMFSLN_MSK 0x780 + +/* + * tdm_fs_ws_polarity + */ +#define TFA98XX_TDM_CONFIG0_TDMFSPOL (0x1 << 11) +#define TFA98XX_TDM_CONFIG0_TDMFSPOL_POS 11 +#define TFA98XX_TDM_CONFIG0_TDMFSPOL_LEN 1 +#define TFA98XX_TDM_CONFIG0_TDMFSPOL_MAX 1 +#define TFA98XX_TDM_CONFIG0_TDMFSPOL_MSK 0x800 + +/* + * tdm_nbck + */ +#define TFA98XX_TDM_CONFIG0_TDMNBCK (0xf << 12) +#define TFA98XX_TDM_CONFIG0_TDMNBCK_POS 12 +#define TFA98XX_TDM_CONFIG0_TDMNBCK_LEN 4 +#define TFA98XX_TDM_CONFIG0_TDMNBCK_MAX 15 +#define TFA98XX_TDM_CONFIG0_TDMNBCK_MSK 0xf000 + +/* + * (0x21)-tdm_config1 + */ + +/* + * tdm_nb_of_slots + */ +#define TFA98XX_TDM_CONFIG1_TDMSLOTS (0xf << 0) +#define TFA98XX_TDM_CONFIG1_TDMSLOTS_POS 0 +#define TFA98XX_TDM_CONFIG1_TDMSLOTS_LEN 4 +#define TFA98XX_TDM_CONFIG1_TDMSLOTS_MAX 15 +#define TFA98XX_TDM_CONFIG1_TDMSLOTS_MSK 0xf + +/* + * tdm_slot_length + */ +#define TFA98XX_TDM_CONFIG1_TDMSLLN (0x1f << 4) +#define TFA98XX_TDM_CONFIG1_TDMSLLN_POS 4 +#define TFA98XX_TDM_CONFIG1_TDMSLLN_LEN 5 +#define TFA98XX_TDM_CONFIG1_TDMSLLN_MAX 31 +#define TFA98XX_TDM_CONFIG1_TDMSLLN_MSK 0x1f0 + +/* + * tdm_bits_remaining + */ +#define TFA98XX_TDM_CONFIG1_TDMBRMG (0x1f << 9) +#define TFA98XX_TDM_CONFIG1_TDMBRMG_POS 9 +#define TFA98XX_TDM_CONFIG1_TDMBRMG_LEN 5 +#define TFA98XX_TDM_CONFIG1_TDMBRMG_MAX 31 +#define TFA98XX_TDM_CONFIG1_TDMBRMG_MSK 0x3e00 + +/* + * tdm_data_delay + */ +#define TFA98XX_TDM_CONFIG1_TDMDEL (0x1 << 14) +#define TFA98XX_TDM_CONFIG1_TDMDEL_POS 14 +#define TFA98XX_TDM_CONFIG1_TDMDEL_LEN 1 +#define TFA98XX_TDM_CONFIG1_TDMDEL_MAX 1 +#define TFA98XX_TDM_CONFIG1_TDMDEL_MSK 0x4000 + +/* + * tdm_data_adjustment + */ +#define TFA98XX_TDM_CONFIG1_TDMADJ (0x1 << 15) +#define TFA98XX_TDM_CONFIG1_TDMADJ_POS 15 +#define TFA98XX_TDM_CONFIG1_TDMADJ_LEN 1 +#define TFA98XX_TDM_CONFIG1_TDMADJ_MAX 1 +#define TFA98XX_TDM_CONFIG1_TDMADJ_MSK 0x8000 + +/* + * (0x22)-tdm_config2 + */ + +/* + * tdm_audio_sample_compression + */ +#define TFA98XX_TDM_CONFIG2_TDMOOMP (0x3 << 0) +#define TFA98XX_TDM_CONFIG2_TDMOOMP_POS 0 +#define TFA98XX_TDM_CONFIG2_TDMOOMP_LEN 2 +#define TFA98XX_TDM_CONFIG2_TDMOOMP_MAX 3 +#define TFA98XX_TDM_CONFIG2_TDMOOMP_MSK 0x3 + +/* + * tdm_sample_size + */ +#define TFA98XX_TDM_CONFIG2_TDMSSIZE (0x1f << 2) +#define TFA98XX_TDM_CONFIG2_TDMSSIZE_POS 2 +#define TFA98XX_TDM_CONFIG2_TDMSSIZE_LEN 5 +#define TFA98XX_TDM_CONFIG2_TDMSSIZE_MAX 31 +#define TFA98XX_TDM_CONFIG2_TDMSSIZE_MSK 0x7c + +/* + * tdm_txdata_format + */ +#define TFA98XX_TDM_CONFIG2_TDMTXDFO (0x3 << 7) +#define TFA98XX_TDM_CONFIG2_TDMTXDFO_POS 7 +#define TFA98XX_TDM_CONFIG2_TDMTXDFO_LEN 2 +#define TFA98XX_TDM_CONFIG2_TDMTXDFO_MAX 3 +#define TFA98XX_TDM_CONFIG2_TDMTXDFO_MSK 0x180 + +/* + * tdm_txdata_format_unused_slot_sd0 + */ +#define TFA98XX_TDM_CONFIG2_TDMTXUS0 (0x3 << 9) +#define TFA98XX_TDM_CONFIG2_TDMTXUS0_POS 9 +#define TFA98XX_TDM_CONFIG2_TDMTXUS0_LEN 2 +#define TFA98XX_TDM_CONFIG2_TDMTXUS0_MAX 3 +#define TFA98XX_TDM_CONFIG2_TDMTXUS0_MSK 0x600 + +/* + * tdm_txdata_format_unused_slot_sd1 + */ +#define TFA98XX_TDM_CONFIG2_TDMTXUS1 (0x3 << 11) +#define TFA98XX_TDM_CONFIG2_TDMTXUS1_POS 11 +#define TFA98XX_TDM_CONFIG2_TDMTXUS1_LEN 2 +#define TFA98XX_TDM_CONFIG2_TDMTXUS1_MAX 3 +#define TFA98XX_TDM_CONFIG2_TDMTXUS1_MSK 0x1800 + +/* + * tdm_txdata_format_unused_slot_sd2 + */ +#define TFA98XX_TDM_CONFIG2_TDMTXUS2 (0x3 << 13) +#define TFA98XX_TDM_CONFIG2_TDMTXUS2_POS 13 +#define TFA98XX_TDM_CONFIG2_TDMTXUS2_LEN 2 +#define TFA98XX_TDM_CONFIG2_TDMTXUS2_MAX 3 +#define TFA98XX_TDM_CONFIG2_TDMTXUS2_MSK 0x6000 + +/* + * (0x23)-tdm_config3 + */ + +/* + * tdm_sink1_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMLE (0x1 << 1) +#define TFA98XX_TDM_CONFIG3_TDMLE_POS 1 +#define TFA98XX_TDM_CONFIG3_TDMLE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMLE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMLE_MSK 0x2 + +/* + * tdm_sink2_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMRE (0x1 << 2) +#define TFA98XX_TDM_CONFIG3_TDMRE_POS 2 +#define TFA98XX_TDM_CONFIG3_TDMRE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMRE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMRE_MSK 0x4 + +/* + * tdm_source1_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMVSRE (0x1 << 4) +#define TFA98XX_TDM_CONFIG3_TDMVSRE_POS 4 +#define TFA98XX_TDM_CONFIG3_TDMVSRE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMVSRE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMVSRE_MSK 0x10 + +/* + * tdm_source2_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMCSRE (0x1 << 5) +#define TFA98XX_TDM_CONFIG3_TDMCSRE_POS 5 +#define TFA98XX_TDM_CONFIG3_TDMCSRE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMCSRE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMCSRE_MSK 0x20 + +/* + * tdm_source3_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMVSLE (0x1 << 6) +#define TFA98XX_TDM_CONFIG3_TDMVSLE_POS 6 +#define TFA98XX_TDM_CONFIG3_TDMVSLE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMVSLE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMVSLE_MSK 0x40 + +/* + * tdm_source4_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMCSLE (0x1 << 7) +#define TFA98XX_TDM_CONFIG3_TDMCSLE_POS 7 +#define TFA98XX_TDM_CONFIG3_TDMCSLE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMCSLE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMCSLE_MSK 0x80 + +/* + * tdm_source5_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMCFRE (0x1 << 8) +#define TFA98XX_TDM_CONFIG3_TDMCFRE_POS 8 +#define TFA98XX_TDM_CONFIG3_TDMCFRE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMCFRE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMCFRE_MSK 0x100 + +/* + * tdm_source6_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMCFLE (0x1 << 9) +#define TFA98XX_TDM_CONFIG3_TDMCFLE_POS 9 +#define TFA98XX_TDM_CONFIG3_TDMCFLE_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMCFLE_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMCFLE_MSK 0x200 + +/* + * tdm_source7_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMCF3E (0x1 << 10) +#define TFA98XX_TDM_CONFIG3_TDMCF3E_POS 10 +#define TFA98XX_TDM_CONFIG3_TDMCF3E_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMCF3E_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMCF3E_MSK 0x400 + +/* + * tdm_source8_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMCF4E (0x1 << 11) +#define TFA98XX_TDM_CONFIG3_TDMCF4E_POS 11 +#define TFA98XX_TDM_CONFIG3_TDMCF4E_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMCF4E_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMCF4E_MSK 0x800 + +/* + * tdm_source9_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMPD1E (0x1 << 12) +#define TFA98XX_TDM_CONFIG3_TDMPD1E_POS 12 +#define TFA98XX_TDM_CONFIG3_TDMPD1E_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMPD1E_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMPD1E_MSK 0x1000 + +/* + * tdm_source10_enable + */ +#define TFA98XX_TDM_CONFIG3_TDMPD2E (0x1 << 13) +#define TFA98XX_TDM_CONFIG3_TDMPD2E_POS 13 +#define TFA98XX_TDM_CONFIG3_TDMPD2E_LEN 1 +#define TFA98XX_TDM_CONFIG3_TDMPD2E_MAX 1 +#define TFA98XX_TDM_CONFIG3_TDMPD2E_MSK 0x2000 + +/* + * (0x24)-tdm_config4 + */ + +/* + * tdm_sink1_io + */ +#define TFA98XX_TDM_CONFIG4_TDMLIO (0x3 << 2) +#define TFA98XX_TDM_CONFIG4_TDMLIO_POS 2 +#define TFA98XX_TDM_CONFIG4_TDMLIO_LEN 2 +#define TFA98XX_TDM_CONFIG4_TDMLIO_MAX 3 +#define TFA98XX_TDM_CONFIG4_TDMLIO_MSK 0xc + +/* + * tdm_sink2_io + */ +#define TFA98XX_TDM_CONFIG4_TDMRIO (0x3 << 4) +#define TFA98XX_TDM_CONFIG4_TDMRIO_POS 4 +#define TFA98XX_TDM_CONFIG4_TDMRIO_LEN 2 +#define TFA98XX_TDM_CONFIG4_TDMRIO_MAX 3 +#define TFA98XX_TDM_CONFIG4_TDMRIO_MSK 0x30 + +/* + * tdm_source1_io + */ +#define TFA98XX_TDM_CONFIG4_TDMVSRIO (0x3 << 8) +#define TFA98XX_TDM_CONFIG4_TDMVSRIO_POS 8 +#define TFA98XX_TDM_CONFIG4_TDMVSRIO_LEN 2 +#define TFA98XX_TDM_CONFIG4_TDMVSRIO_MAX 3 +#define TFA98XX_TDM_CONFIG4_TDMVSRIO_MSK 0x300 + +/* + * tdm_source2_io + */ +#define TFA98XX_TDM_CONFIG4_TDMCSRIO (0x3 << 10) +#define TFA98XX_TDM_CONFIG4_TDMCSRIO_POS 10 +#define TFA98XX_TDM_CONFIG4_TDMCSRIO_LEN 2 +#define TFA98XX_TDM_CONFIG4_TDMCSRIO_MAX 3 +#define TFA98XX_TDM_CONFIG4_TDMCSRIO_MSK 0xc00 + +/* + * tdm_source3_io + */ +#define TFA98XX_TDM_CONFIG4_TDMVSLIO (0x3 << 12) +#define TFA98XX_TDM_CONFIG4_TDMVSLIO_POS 12 +#define TFA98XX_TDM_CONFIG4_TDMVSLIO_LEN 2 +#define TFA98XX_TDM_CONFIG4_TDMVSLIO_MAX 3 +#define TFA98XX_TDM_CONFIG4_TDMVSLIO_MSK 0x3000 + +/* + * tdm_source4_io + */ +#define TFA98XX_TDM_CONFIG4_TDMCSLIO (0x3 << 14) +#define TFA98XX_TDM_CONFIG4_TDMCSLIO_POS 14 +#define TFA98XX_TDM_CONFIG4_TDMCSLIO_LEN 2 +#define TFA98XX_TDM_CONFIG4_TDMCSLIO_MAX 3 +#define TFA98XX_TDM_CONFIG4_TDMCSLIO_MSK 0xc000 + +/* + * (0x25)-tdm_config5 + */ + +/* + * tdm_source5_io + */ +#define TFA98XX_TDM_CONFIG5_TDMCFRIO (0x3 << 0) +#define TFA98XX_TDM_CONFIG5_TDMCFRIO_POS 0 +#define TFA98XX_TDM_CONFIG5_TDMCFRIO_LEN 2 +#define TFA98XX_TDM_CONFIG5_TDMCFRIO_MAX 3 +#define TFA98XX_TDM_CONFIG5_TDMCFRIO_MSK 0x3 + +/* + * tdm_source6_io + */ +#define TFA98XX_TDM_CONFIG5_TDMCFLIO (0x3 << 2) +#define TFA98XX_TDM_CONFIG5_TDMCFLIO_POS 2 +#define TFA98XX_TDM_CONFIG5_TDMCFLIO_LEN 2 +#define TFA98XX_TDM_CONFIG5_TDMCFLIO_MAX 3 +#define TFA98XX_TDM_CONFIG5_TDMCFLIO_MSK 0xc + +/* + * tdm_source7_io + */ +#define TFA98XX_TDM_CONFIG5_TDMCF3IO (0x3 << 4) +#define TFA98XX_TDM_CONFIG5_TDMCF3IO_POS 4 +#define TFA98XX_TDM_CONFIG5_TDMCF3IO_LEN 2 +#define TFA98XX_TDM_CONFIG5_TDMCF3IO_MAX 3 +#define TFA98XX_TDM_CONFIG5_TDMCF3IO_MSK 0x30 + +/* + * tdm_source8_io + */ +#define TFA98XX_TDM_CONFIG5_TDMCF4IO (0x3 << 6) +#define TFA98XX_TDM_CONFIG5_TDMCF4IO_POS 6 +#define TFA98XX_TDM_CONFIG5_TDMCF4IO_LEN 2 +#define TFA98XX_TDM_CONFIG5_TDMCF4IO_MAX 3 +#define TFA98XX_TDM_CONFIG5_TDMCF4IO_MSK 0xc0 + +/* + * tdm_source9_io + */ +#define TFA98XX_TDM_CONFIG5_TDMPD1IO (0x3 << 8) +#define TFA98XX_TDM_CONFIG5_TDMPD1IO_POS 8 +#define TFA98XX_TDM_CONFIG5_TDMPD1IO_LEN 2 +#define TFA98XX_TDM_CONFIG5_TDMPD1IO_MAX 3 +#define TFA98XX_TDM_CONFIG5_TDMPD1IO_MSK 0x300 + +/* + * tdm_source10_io + */ +#define TFA98XX_TDM_CONFIG5_TDMPD2IO (0x3 << 10) +#define TFA98XX_TDM_CONFIG5_TDMPD2IO_POS 10 +#define TFA98XX_TDM_CONFIG5_TDMPD2IO_LEN 2 +#define TFA98XX_TDM_CONFIG5_TDMPD2IO_MAX 3 +#define TFA98XX_TDM_CONFIG5_TDMPD2IO_MSK 0xc00 + +/* + * (0x26)-tdm_config6 + */ + +/* + * tdm_sink1_slot + */ +#define TFA98XX_TDM_CONFIG6_TDMLS (0xf << 4) +#define TFA98XX_TDM_CONFIG6_TDMLS_POS 4 +#define TFA98XX_TDM_CONFIG6_TDMLS_LEN 4 +#define TFA98XX_TDM_CONFIG6_TDMLS_MAX 15 +#define TFA98XX_TDM_CONFIG6_TDMLS_MSK 0xf0 + +/* + * tdm_sink2_slot + */ +#define TFA98XX_TDM_CONFIG6_TDMRS (0xf << 8) +#define TFA98XX_TDM_CONFIG6_TDMRS_POS 8 +#define TFA98XX_TDM_CONFIG6_TDMRS_LEN 4 +#define TFA98XX_TDM_CONFIG6_TDMRS_MAX 15 +#define TFA98XX_TDM_CONFIG6_TDMRS_MSK 0xf00 + +/* + * (0x27)-tdm_config7 + */ + +/* + * tdm_source1_slot + */ +#define TFA98XX_TDM_CONFIG7_TDMVSRS (0xf << 0) +#define TFA98XX_TDM_CONFIG7_TDMVSRS_POS 0 +#define TFA98XX_TDM_CONFIG7_TDMVSRS_LEN 4 +#define TFA98XX_TDM_CONFIG7_TDMVSRS_MAX 15 +#define TFA98XX_TDM_CONFIG7_TDMVSRS_MSK 0xf + +/* + * tdm_source2_slot + */ +#define TFA98XX_TDM_CONFIG7_TDMCSRS (0xf << 4) +#define TFA98XX_TDM_CONFIG7_TDMCSRS_POS 4 +#define TFA98XX_TDM_CONFIG7_TDMCSRS_LEN 4 +#define TFA98XX_TDM_CONFIG7_TDMCSRS_MAX 15 +#define TFA98XX_TDM_CONFIG7_TDMCSRS_MSK 0xf0 + +/* + * tdm_source3_slot + */ +#define TFA98XX_TDM_CONFIG7_TDMVSLS (0xf << 8) +#define TFA98XX_TDM_CONFIG7_TDMVSLS_POS 8 +#define TFA98XX_TDM_CONFIG7_TDMVSLS_LEN 4 +#define TFA98XX_TDM_CONFIG7_TDMVSLS_MAX 15 +#define TFA98XX_TDM_CONFIG7_TDMVSLS_MSK 0xf00 + +/* + * tdm_source4_slot + */ +#define TFA98XX_TDM_CONFIG7_TDMCSLS (0xf << 12) +#define TFA98XX_TDM_CONFIG7_TDMCSLS_POS 12 +#define TFA98XX_TDM_CONFIG7_TDMCSLS_LEN 4 +#define TFA98XX_TDM_CONFIG7_TDMCSLS_MAX 15 +#define TFA98XX_TDM_CONFIG7_TDMCSLS_MSK 0xf000 + +/* + * (0x28)-tdm_config8 + */ + +/* + * tdm_source5_slot + */ +#define TFA98XX_TDM_CONFIG8_TDMCFRS (0xf << 0) +#define TFA98XX_TDM_CONFIG8_TDMCFRS_POS 0 +#define TFA98XX_TDM_CONFIG8_TDMCFRS_LEN 4 +#define TFA98XX_TDM_CONFIG8_TDMCFRS_MAX 15 +#define TFA98XX_TDM_CONFIG8_TDMCFRS_MSK 0xf + +/* + * tdm_source6_slot + */ +#define TFA98XX_TDM_CONFIG8_TDMCFLS (0xf << 4) +#define TFA98XX_TDM_CONFIG8_TDMCFLS_POS 4 +#define TFA98XX_TDM_CONFIG8_TDMCFLS_LEN 4 +#define TFA98XX_TDM_CONFIG8_TDMCFLS_MAX 15 +#define TFA98XX_TDM_CONFIG8_TDMCFLS_MSK 0xf0 + +/* + * tdm_source7_slot + */ +#define TFA98XX_TDM_CONFIG8_TDMCF3S (0xf << 8) +#define TFA98XX_TDM_CONFIG8_TDMCF3S_POS 8 +#define TFA98XX_TDM_CONFIG8_TDMCF3S_LEN 4 +#define TFA98XX_TDM_CONFIG8_TDMCF3S_MAX 15 +#define TFA98XX_TDM_CONFIG8_TDMCF3S_MSK 0xf00 + +/* + * tdm_source8_slot + */ +#define TFA98XX_TDM_CONFIG8_TDMCF4S (0xf << 12) +#define TFA98XX_TDM_CONFIG8_TDMCF4S_POS 12 +#define TFA98XX_TDM_CONFIG8_TDMCF4S_LEN 4 +#define TFA98XX_TDM_CONFIG8_TDMCF4S_MAX 15 +#define TFA98XX_TDM_CONFIG8_TDMCF4S_MSK 0xf000 + +/* + * (0x29)-tdm_config9 + */ + +/* + * tdm_source9_slot + */ +#define TFA98XX_TDM_CONFIG9_TDMPD1S (0xf << 0) +#define TFA98XX_TDM_CONFIG9_TDMPD1S_POS 0 +#define TFA98XX_TDM_CONFIG9_TDMPD1S_LEN 4 +#define TFA98XX_TDM_CONFIG9_TDMPD1S_MAX 15 +#define TFA98XX_TDM_CONFIG9_TDMPD1S_MSK 0xf + +/* + * tdm_source10_slot + */ +#define TFA98XX_TDM_CONFIG9_TDMPD2S (0xf << 4) +#define TFA98XX_TDM_CONFIG9_TDMPD2S_POS 4 +#define TFA98XX_TDM_CONFIG9_TDMPD2S_LEN 4 +#define TFA98XX_TDM_CONFIG9_TDMPD2S_MAX 15 +#define TFA98XX_TDM_CONFIG9_TDMPD2S_MSK 0xf0 + +/* + * (0x31)-pdm_config0 + */ + +/* + * pdm_mode + */ +#define TFA98XX_PDM_CONFIG0_PDMSM (0x1 << 0) +#define TFA98XX_PDM_CONFIG0_PDMSM_POS 0 +#define TFA98XX_PDM_CONFIG0_PDMSM_LEN 1 +#define TFA98XX_PDM_CONFIG0_PDMSM_MAX 1 +#define TFA98XX_PDM_CONFIG0_PDMSM_MSK 0x1 + +/* + * pdm_side_tone_sel + */ +#define TFA98XX_PDM_CONFIG0_PDMSTSEL (0x3 << 1) +#define TFA98XX_PDM_CONFIG0_PDMSTSEL_POS 1 +#define TFA98XX_PDM_CONFIG0_PDMSTSEL_LEN 2 +#define TFA98XX_PDM_CONFIG0_PDMSTSEL_MAX 3 +#define TFA98XX_PDM_CONFIG0_PDMSTSEL_MSK 0x6 + +/* + * pdm_left_sel + */ +#define TFA98XX_PDM_CONFIG0_PDMLSEL (0x1 << 3) +#define TFA98XX_PDM_CONFIG0_PDMLSEL_POS 3 +#define TFA98XX_PDM_CONFIG0_PDMLSEL_LEN 1 +#define TFA98XX_PDM_CONFIG0_PDMLSEL_MAX 1 +#define TFA98XX_PDM_CONFIG0_PDMLSEL_MSK 0x8 + +/* + * pdm_right_sel + */ +#define TFA98XX_PDM_CONFIG0_PDMRSEL (0x1 << 4) +#define TFA98XX_PDM_CONFIG0_PDMRSEL_POS 4 +#define TFA98XX_PDM_CONFIG0_PDMRSEL_LEN 1 +#define TFA98XX_PDM_CONFIG0_PDMRSEL_MAX 1 +#define TFA98XX_PDM_CONFIG0_PDMRSEL_MSK 0x10 + +/* + * enbl_micvdd + */ +#define TFA98XX_PDM_CONFIG0_MICVDDE (0x1 << 5) +#define TFA98XX_PDM_CONFIG0_MICVDDE_POS 5 +#define TFA98XX_PDM_CONFIG0_MICVDDE_LEN 1 +#define TFA98XX_PDM_CONFIG0_MICVDDE_MAX 1 +#define TFA98XX_PDM_CONFIG0_MICVDDE_MSK 0x20 + +/* + * (0x32)-pdm_config1 + */ + +/* + * pdm_nbck + */ +#define TFA98XX_PDM_CONFIG1_PDMCLRAT (0x3 << 0) +#define TFA98XX_PDM_CONFIG1_PDMCLRAT_POS 0 +#define TFA98XX_PDM_CONFIG1_PDMCLRAT_LEN 2 +#define TFA98XX_PDM_CONFIG1_PDMCLRAT_MAX 3 +#define TFA98XX_PDM_CONFIG1_PDMCLRAT_MSK 0x3 + +/* + * pdm_gain + */ +#define TFA98XX_PDM_CONFIG1_PDMGAIN (0xf << 2) +#define TFA98XX_PDM_CONFIG1_PDMGAIN_POS 2 +#define TFA98XX_PDM_CONFIG1_PDMGAIN_LEN 4 +#define TFA98XX_PDM_CONFIG1_PDMGAIN_MAX 15 +#define TFA98XX_PDM_CONFIG1_PDMGAIN_MSK 0x3c + +/* + * sel_pdm_out_data + */ +#define TFA98XX_PDM_CONFIG1_PDMOSEL (0xf << 6) +#define TFA98XX_PDM_CONFIG1_PDMOSEL_POS 6 +#define TFA98XX_PDM_CONFIG1_PDMOSEL_LEN 4 +#define TFA98XX_PDM_CONFIG1_PDMOSEL_MAX 15 +#define TFA98XX_PDM_CONFIG1_PDMOSEL_MSK 0x3c0 + +/* + * sel_cf_haptic_data + */ +#define TFA98XX_PDM_CONFIG1_SELCFHAPD (0x1 << 10) +#define TFA98XX_PDM_CONFIG1_SELCFHAPD_POS 10 +#define TFA98XX_PDM_CONFIG1_SELCFHAPD_LEN 1 +#define TFA98XX_PDM_CONFIG1_SELCFHAPD_MAX 1 +#define TFA98XX_PDM_CONFIG1_SELCFHAPD_MSK 0x400 + +/* + * (0x33)-haptic_driver_config + */ + +/* + * haptic_duration + */ +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME (0xff << 0) +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_POS 0 +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_LEN 8 +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_MAX 255 +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPTIME_MSK 0xff + +/* + * haptic_data + */ +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL (0xff << 8) +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_POS 8 +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_LEN 8 +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_MAX 255 +#define TFA98XX_HAPTIC_DRIVER_CONFIG_HAPLEVEL_MSK 0xff00 + +/* + * (0x34)-gpio_datain_reg + */ + +/* + * gpio_datain + */ +#define TFA98XX_GPIO_DATAIN_REG_GPIODIN (0xf << 0) +#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_POS 0 +#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_LEN 4 +#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_MAX 15 +#define TFA98XX_GPIO_DATAIN_REG_GPIODIN_MSK 0xf + +/* + * (0x35)-gpio_config + */ + +/* + * gpio_ctrl + */ +#define TFA98XX_GPIO_CONFIG_GPIOCTRL (0x1 << 0) +#define TFA98XX_GPIO_CONFIG_GPIOCTRL_POS 0 +#define TFA98XX_GPIO_CONFIG_GPIOCTRL_LEN 1 +#define TFA98XX_GPIO_CONFIG_GPIOCTRL_MAX 1 +#define TFA98XX_GPIO_CONFIG_GPIOCTRL_MSK 0x1 + +/* + * gpio_dir + */ +#define TFA98XX_GPIO_CONFIG_GPIOCONF (0xf << 1) +#define TFA98XX_GPIO_CONFIG_GPIOCONF_POS 1 +#define TFA98XX_GPIO_CONFIG_GPIOCONF_LEN 4 +#define TFA98XX_GPIO_CONFIG_GPIOCONF_MAX 15 +#define TFA98XX_GPIO_CONFIG_GPIOCONF_MSK 0x1e + +/* + * gpio_dataout + */ +#define TFA98XX_GPIO_CONFIG_GPIODOUT (0xf << 5) +#define TFA98XX_GPIO_CONFIG_GPIODOUT_POS 5 +#define TFA98XX_GPIO_CONFIG_GPIODOUT_LEN 4 +#define TFA98XX_GPIO_CONFIG_GPIODOUT_MAX 15 +#define TFA98XX_GPIO_CONFIG_GPIODOUT_MSK 0x1e0 + +/* + * (0x40)-interrupt_out_reg1 + */ + +/* + * int_out_flag_por + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS (0x1 << 0) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_POS 0 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTVDDS_MSK 0x1 + +/* + * int_out_flag_pll_lock + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS (0x1 << 1) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_POS 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTPLLS_MSK 0x2 + +/* + * int_out_flag_otpok + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS (0x1 << 2) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_POS 2 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOTDS_MSK 0x4 + +/* + * int_out_flag_ovpok + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS (0x1 << 3) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_POS 3 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTOVDS_MSK 0x8 + +/* + * int_out_flag_uvpok + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS (0x1 << 4) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_POS 4 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTUVDS_MSK 0x10 + +/* + * int_out_flag_clocks_stable + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS (0x1 << 5) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_POS 5 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTCLKS_MSK 0x20 + +/* + * int_out_flag_mtp_busy + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB (0x1 << 6) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_POS 6 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTMTPB_MSK 0x40 + +/* + * int_out_flag_lost_clk + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK (0x1 << 7) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_POS 7 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTNOCLK_MSK 0x80 + +/* + * int_out_flag_cf_speakererror + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS (0x1 << 8) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_POS 8 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSPKS_MSK 0x100 + +/* + * int_out_flag_cold_started + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS (0x1 << 9) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_POS 9 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTACS_MSK 0x200 + +/* + * int_out_flag_engage + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS (0x1 << 10) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_POS 10 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTSWS_MSK 0x400 + +/* + * int_out_flag_watchdog_reset + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS (0x1 << 11) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_POS 11 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTWDS_MSK 0x800 + +/* + * int_out_flag_enbl_amp + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS (0x1 << 12) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_POS 12 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAMPS_MSK 0x1000 + +/* + * int_out_flag_enbl_ref + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS (0x1 << 13) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_POS 13 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTAREFS_MSK 0x2000 + +/* + * int_out_flag_adc10_ready + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR (0x1 << 14) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_POS 14 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTADCCR_MSK 0x4000 + +/* + * int_out_flag_bod_vddd_nok + */ +#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK (0x1 << 15) +#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_POS 15 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG1_ISTBODNOK_MSK 0x8000 + +/* + * (0x41)-interrupt_out_reg2 + */ + +/* + * int_out_flag_bst_bstcur + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU (0x1 << 0) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_POS 0 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTCU_MSK 0x1 + +/* + * int_out_flag_bst_hiz + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI (0x1 << 1) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_POS 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTHI_MSK 0x2 + +/* + * int_out_flag_bst_ocpok + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC (0x1 << 2) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_POS 2 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTOC_MSK 0x4 + +/* + * int_out_flag_bst_peakcur + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR (0x1 << 3) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_POS 3 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTPKCUR_MSK 0x8 + +/* + * int_out_flag_bst_voutcomp + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC (0x1 << 4) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_POS 4 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBSTVC_MSK 0x10 + +/* + * int_out_flag_bst_voutcomp86 + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86 (0x1 << 5) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_POS 5 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST86_MSK 0x20 + +/* + * int_out_flag_bst_voutcomp93 + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93 (0x1 << 6) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_POS 6 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTBST93_MSK 0x40 + +/* + * int_out_flag_rcvldop_ready + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD (0x1 << 7) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_POS 7 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTRCVLD_MSK 0x80 + +/* + * int_out_flag_ocp_alarm_left + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL (0x1 << 8) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_POS 8 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPL_MSK 0x100 + +/* + * int_out_flag_ocp_alarm_right + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR (0x1 << 9) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_POS 9 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTOCPR_MSK 0x200 + +/* + * int_out_flag_man_wait_src_settings + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC (0x1 << 10) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_POS 10 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSRC_MSK 0x400 + +/* + * int_out_flag_man_wait_cf_config + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC (0x1 << 11) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_POS 11 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWCFC_MSK 0x800 + +/* + * int_out_flag_man_start_mute_audio + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU (0x1 << 12) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_POS 12 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTMWSMU_MSK 0x1000 + +/* + * int_out_flag_cfma_err + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER (0x1 << 13) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_POS 13 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMER_MSK 0x2000 + +/* + * int_out_flag_cfma_ack + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC (0x1 << 14) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_POS 14 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCFMAC_MSK 0x4000 + +/* + * int_out_flag_clk_out_of_range + */ +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR (0x1 << 15) +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_POS 15 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG2_ISTCLKOOR_MSK 0x8000 + +/* + * (0x42)-interrupt_out_reg3 + */ + +/* + * int_out_flag_tdm_error + */ +#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER (0x1 << 0) +#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_POS 0 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTTDMER_MSK 0x1 + +/* + * int_out_flag_clip_left + */ +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL (0x1 << 1) +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_POS 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPL_MSK 0x2 + +/* + * int_out_flag_clip_right + */ +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR (0x1 << 2) +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_POS 2 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTCLPR_MSK 0x4 + +/* + * int_out_flag_mic_ocpok + */ +#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM (0x1 << 3) +#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_POS 3 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_LEN 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_MAX 1 +#define TFA98XX_INTERRUPT_OUT_REG3_ISTOCPM_MSK 0x8 + +/* + * (0x44)-interrupt_in_reg1 + */ + +/* + * int_in_flag_por + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS (0x1 << 0) +#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_POS 0 +#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLVDDS_MSK 0x1 + +/* + * int_in_flag_pll_lock + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS (0x1 << 1) +#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_POS 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLPLLS_MSK 0x2 + +/* + * int_in_flag_otpok + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS (0x1 << 2) +#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_POS 2 +#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLOTDS_MSK 0x4 + +/* + * int_in_flag_ovpok + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS (0x1 << 3) +#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_POS 3 +#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLOVDS_MSK 0x8 + +/* + * int_in_flag_uvpok + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS (0x1 << 4) +#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_POS 4 +#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLUVDS_MSK 0x10 + +/* + * int_in_flag_clocks_stable + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS (0x1 << 5) +#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_POS 5 +#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLCLKS_MSK 0x20 + +/* + * int_in_flag_mtp_busy + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB (0x1 << 6) +#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_POS 6 +#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLMTPB_MSK 0x40 + +/* + * int_in_flag_lost_clk + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK (0x1 << 7) +#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_POS 7 +#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLNOCLK_MSK 0x80 + +/* + * int_in_flag_cf_speakererror + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS (0x1 << 8) +#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_POS 8 +#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLSPKS_MSK 0x100 + +/* + * int_in_flag_cold_started + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLACS (0x1 << 9) +#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_POS 9 +#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLACS_MSK 0x200 + +/* + * int_in_flag_engage + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS (0x1 << 10) +#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_POS 10 +#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLSWS_MSK 0x400 + +/* + * int_in_flag_watchdog_reset + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS (0x1 << 11) +#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_POS 11 +#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLWDS_MSK 0x800 + +/* + * int_in_flag_enbl_amp + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS (0x1 << 12) +#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_POS 12 +#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLAMPS_MSK 0x1000 + +/* + * int_in_flag_enbl_ref + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS (0x1 << 13) +#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_POS 13 +#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLAREFS_MSK 0x2000 + +/* + * int_in_flag_adc10_ready + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR (0x1 << 14) +#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_POS 14 +#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLADCCR_MSK 0x4000 + +/* + * int_in_flag_bod_vddd_nok + */ +#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK (0x1 << 15) +#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_POS 15 +#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG1_ICLBODNOK_MSK 0x8000 + +/* + * (0x45)-interrupt_in_reg2 + */ + +/* + * int_in_flag_bst_bstcur + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU (0x1 << 0) +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_POS 0 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTCU_MSK 0x1 + +/* + * int_in_flag_bst_hiz + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI (0x1 << 1) +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_POS 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTHI_MSK 0x2 + +/* + * int_in_flag_bst_ocpok + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC (0x1 << 2) +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_POS 2 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTOC_MSK 0x4 + +/* + * int_in_flag_bst_peakcur + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC (0x1 << 3) +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_POS 3 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTPC_MSK 0x8 + +/* + * int_in_flag_bst_voutcomp + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC (0x1 << 4) +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_POS 4 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBSTVC_MSK 0x10 + +/* + * int_in_flag_bst_voutcomp86 + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86 (0x1 << 5) +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_POS 5 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST86_MSK 0x20 + +/* + * int_in_flag_bst_voutcomp93 + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93 (0x1 << 6) +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_POS 6 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLBST93_MSK 0x40 + +/* + * int_in_flag_rcvldop_ready + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD (0x1 << 7) +#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_POS 7 +#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLRCVLD_MSK 0x80 + +/* + * int_in_flag_ocp_alarm_left + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL (0x1 << 8) +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_POS 8 +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPL_MSK 0x100 + +/* + * int_in_flag_ocp_alarm_right + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR (0x1 << 9) +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_POS 9 +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLOCPR_MSK 0x200 + +/* + * int_in_flag_man_wait_src_settings + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC (0x1 << 10) +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_POS 10 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSRC_MSK 0x400 + +/* + * int_in_flag_man_wait_cf_config + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC (0x1 << 11) +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_POS 11 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWCFC_MSK 0x800 + +/* + * int_in_flag_man_start_mute_audio + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU (0x1 << 12) +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_POS 12 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLMWSMU_MSK 0x1000 + +/* + * int_in_flag_cfma_err + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER (0x1 << 13) +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_POS 13 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMER_MSK 0x2000 + +/* + * int_in_flag_cfma_ack + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC (0x1 << 14) +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_POS 14 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCFMAC_MSK 0x4000 + +/* + * int_in_flag_clk_out_of_range + */ +#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR (0x1 << 15) +#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_POS 15 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG2_ICLCLKOOR_MSK 0x8000 + +/* + * (0x46)-interrupt_in_reg3 + */ + +/* + * int_in_flag_tdm_error + */ +#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER (0x1 << 0) +#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_POS 0 +#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLTDMER_MSK 0x1 + +/* + * int_in_flag_clip_left + */ +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL (0x1 << 1) +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_POS 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPL_MSK 0x2 + +/* + * int_in_flag_clip_right + */ +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR (0x1 << 2) +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_POS 2 +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLCLPR_MSK 0x4 + +/* + * int_in_flag_mic_ocpok + */ +#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM (0x1 << 3) +#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_POS 3 +#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_LEN 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_MAX 1 +#define TFA98XX_INTERRUPT_IN_REG3_ICLOCPM_MSK 0x8 + +/* + * (0x48)-interrupt_enable_reg1 + */ + +/* + * int_enable_flag_por + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS (0x1 << 0) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_POS 0 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEVDDS_MSK 0x1 + +/* + * int_enable_flag_pll_lock + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS (0x1 << 1) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_POS 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEPLLS_MSK 0x2 + +/* + * int_enable_flag_otpok + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS (0x1 << 2) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_POS 2 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOTDS_MSK 0x4 + +/* + * int_enable_flag_ovpok + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS (0x1 << 3) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_POS 3 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEOVDS_MSK 0x8 + +/* + * int_enable_flag_uvpok + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS (0x1 << 4) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_POS 4 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEUVDS_MSK 0x10 + +/* + * int_enable_flag_clocks_stable + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS (0x1 << 5) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_POS 5 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IECLKS_MSK 0x20 + +/* + * int_enable_flag_mtp_busy + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB (0x1 << 6) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_POS 6 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEMTPB_MSK 0x40 + +/* + * int_enable_flag_lost_clk + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK (0x1 << 7) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_POS 7 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IENOCLK_MSK 0x80 + +/* + * int_enable_flag_cf_speakererror + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS (0x1 << 8) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_POS 8 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESPKS_MSK 0x100 + +/* + * int_enable_flag_cold_started + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS (0x1 << 9) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_POS 9 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEACS_MSK 0x200 + +/* + * int_enable_flag_engage + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS (0x1 << 10) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_POS 10 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IESWS_MSK 0x400 + +/* + * int_enable_flag_watchdog_reset + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS (0x1 << 11) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_POS 11 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEWDS_MSK 0x800 + +/* + * int_enable_flag_enbl_amp + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS (0x1 << 12) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_POS 12 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAMPS_MSK 0x1000 + +/* + * int_enable_flag_enbl_ref + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS (0x1 << 13) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_POS 13 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEAREFS_MSK 0x2000 + +/* + * int_enable_flag_adc10_ready + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR (0x1 << 14) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_POS 14 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEADCCR_MSK 0x4000 + +/* + * int_enable_flag_bod_vddd_nok + */ +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK (0x1 << 15) +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_POS 15 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG1_IEBODNOK_MSK 0x8000 + +/* + * (0x49)-interrupt_enable_reg2 + */ + +/* + * int_enable_flag_bst_bstcur + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU (0x1 << 0) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_POS 0 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTCU_MSK 0x1 + +/* + * int_enable_flag_bst_hiz + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI (0x1 << 1) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_POS 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTHI_MSK 0x2 + +/* + * int_enable_flag_bst_ocpok + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC (0x1 << 2) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_POS 2 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTOC_MSK 0x4 + +/* + * int_enable_flag_bst_peakcur + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC (0x1 << 3) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_POS 3 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTPC_MSK 0x8 + +/* + * int_enable_flag_bst_voutcomp + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC (0x1 << 4) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_POS 4 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBSTVC_MSK 0x10 + +/* + * int_enable_flag_bst_voutcomp86 + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86 (0x1 << 5) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_POS 5 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST86_MSK 0x20 + +/* + * int_enable_flag_bst_voutcomp93 + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93 (0x1 << 6) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_POS 6 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEBST93_MSK 0x40 + +/* + * int_enable_flag_rcvldop_ready + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD (0x1 << 7) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_POS 7 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IERCVLD_MSK 0x80 + +/* + * int_enable_flag_ocp_alarm_left + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL (0x1 << 8) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_POS 8 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPL_MSK 0x100 + +/* + * int_enable_flag_ocp_alarm_right + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR (0x1 << 9) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_POS 9 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEOCPR_MSK 0x200 + +/* + * int_enable_flag_man_wait_src_settings + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC (0x1 << 10) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_POS 10 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSRC_MSK 0x400 + +/* + * int_enable_flag_man_wait_cf_config + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC (0x1 << 11) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_POS 11 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWCFC_MSK 0x800 + +/* + * int_enable_flag_man_start_mute_audio + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU (0x1 << 12) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_POS 12 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IEMWSMU_MSK 0x1000 + +/* + * int_enable_flag_cfma_err + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER (0x1 << 13) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_POS 13 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMER_MSK 0x2000 + +/* + * int_enable_flag_cfma_ack + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC (0x1 << 14) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_POS 14 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECFMAC_MSK 0x4000 + +/* + * int_enable_flag_clk_out_of_range + */ +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR (0x1 << 15) +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_POS 15 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG2_IECLKOOR_MSK 0x8000 + +/* + * (0x4a)-interrupt_enable_reg3 + */ + +/* + * int_enable_flag_tdm_error + */ +#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER (0x1 << 0) +#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_POS 0 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IETDMER_MSK 0x1 + +/* + * int_enable_flag_clip_left + */ +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL (0x1 << 1) +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_POS 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPL_MSK 0x2 + +/* + * int_enable_flag_clip_right + */ +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR (0x1 << 2) +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_POS 2 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IECLPR_MSK 0x4 + +/* + * int_enable_flag_mic_ocpok + */ +#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1 (0x1 << 3) +#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_POS 3 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_LEN 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_MAX 1 +#define TFA98XX_INTERRUPT_ENABLE_REG3_IEOCPM1_MSK 0x8 + +/* + * (0x4c)-status_polarity_reg1 + */ + +/* + * int_polarity_flag_por + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS (0x1 << 0) +#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_POS 0 +#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOVDDS_MSK 0x1 + +/* + * int_polarity_flag_pll_lock + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS (0x1 << 1) +#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_POS 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOPLLS_MSK 0x2 + +/* + * int_polarity_flag_otpok + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS (0x1 << 2) +#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_POS 2 +#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOOTDS_MSK 0x4 + +/* + * int_polarity_flag_ovpok + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS (0x1 << 3) +#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_POS 3 +#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOOVDS_MSK 0x8 + +/* + * int_polarity_flag_uvpok + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS (0x1 << 4) +#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_POS 4 +#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOUVDS_MSK 0x10 + +/* + * int_polarity_flag_clocks_stable + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS (0x1 << 5) +#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_POS 5 +#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOCLKS_MSK 0x20 + +/* + * int_polarity_flag_mtp_busy + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB (0x1 << 6) +#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_POS 6 +#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOMTPB_MSK 0x40 + +/* + * int_polarity_flag_lost_clk + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK (0x1 << 7) +#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_POS 7 +#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPONOCLK_MSK 0x80 + +/* + * int_polarity_flag_cf_speakererror + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS (0x1 << 8) +#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_POS 8 +#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOSPKS_MSK 0x100 + +/* + * int_polarity_flag_cold_started + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOACS (0x1 << 9) +#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_POS 9 +#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOACS_MSK 0x200 + +/* + * int_polarity_flag_engage + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS (0x1 << 10) +#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_POS 10 +#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOSWS_MSK 0x400 + +/* + * int_polarity_flag_watchdog_reset + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS (0x1 << 11) +#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_POS 11 +#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOWDS_MSK 0x800 + +/* + * int_polarity_flag_enbl_amp + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS (0x1 << 12) +#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_POS 12 +#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOAMPS_MSK 0x1000 + +/* + * int_polarity_flag_enbl_ref + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS (0x1 << 13) +#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_POS 13 +#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOAREFS_MSK 0x2000 + +/* + * int_polarity_flag_adc10_ready + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR (0x1 << 14) +#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_POS 14 +#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOADCCR_MSK 0x4000 + +/* + * int_polarity_flag_bod_vddd_nok + */ +#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK (0x1 << 15) +#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_POS 15 +#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG1_IPOBODNOK_MSK 0x8000 + +/* + * (0x4d)-status_polarity_reg2 + */ + +/* + * int_polarity_flag_bst_bstcur + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU (0x1 << 0) +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_POS 0 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTCU_MSK 0x1 + +/* + * int_polarity_flag_bst_hiz + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI (0x1 << 1) +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_POS 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTHI_MSK 0x2 + +/* + * int_polarity_flag_bst_ocpok + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC (0x1 << 2) +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_POS 2 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTOC_MSK 0x4 + +/* + * int_polarity_flag_bst_peakcur + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC (0x1 << 3) +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_POS 3 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTPC_MSK 0x8 + +/* + * int_polarity_flag_bst_voutcomp + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC (0x1 << 4) +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_POS 4 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBSTVC_MSK 0x10 + +/* + * int_polarity_flag_bst_voutcomp86 + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86 (0x1 << 5) +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_POS 5 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST86_MSK 0x20 + +/* + * int_polarity_flag_bst_voutcomp93 + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93 (0x1 << 6) +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_POS 6 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOBST93_MSK 0x40 + +/* + * int_polarity_flag_rcvldop_ready + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD (0x1 << 7) +#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_POS 7 +#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPORCVLD_MSK 0x80 + +/* + * int_polarity_flag_ocp_alarm_left + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL (0x1 << 8) +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_POS 8 +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPL_MSK 0x100 + +/* + * int_polarity_flag_ocp_alarm_right + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR (0x1 << 9) +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_POS 9 +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOOCPR_MSK 0x200 + +/* + * int_polarity_flag_man_wait_src_settings + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC (0x1 << 10) +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_POS 10 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSRC_MSK 0x400 + +/* + * int_polarity_flag_man_wait_cf_config + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC (0x1 << 11) +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_POS 11 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWCFC_MSK 0x800 + +/* + * int_polarity_flag_man_start_mute_audio + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU (0x1 << 12) +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_POS 12 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOMWSMU_MSK 0x1000 + +/* + * int_polarity_flag_cfma_err + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER (0x1 << 13) +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_POS 13 +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMER_MSK 0x2000 + +/* + * int_polarity_flag_cfma_ack + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC (0x1 << 14) +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_POS 14 +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPOCFMAC_MSK 0x4000 + +/* + * int_polarity_flag_clk_out_of_range + */ +#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR (0x1 << 15) +#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_POS 15 +#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG2_IPCLKOOR_MSK 0x8000 + +/* + * (0x4e)-status_polarity_reg3 + */ + +/* + * int_polarity_flag_tdm_error + */ +#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER (0x1 << 0) +#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_POS 0 +#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOTDMER_MSK 0x1 + +/* + * int_polarity_flag_clip_left + */ +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL (0x1 << 1) +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_POS 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPL_MSK 0x2 + +/* + * int_polarity_flag_clip_right + */ +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR (0x1 << 2) +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_POS 2 +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOCLPR_MSK 0x4 + +/* + * int_polarity_flag_mic_ocpok + */ +#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM (0x1 << 3) +#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_POS 3 +#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_LEN 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_MAX 1 +#define TFA98XX_STATUS_POLARITY_REG3_IPOOCPM_MSK 0x8 + +/* + * (0x50)-bat_prot_config + */ + +/* + * vbat_prot_attack_time + */ +#define TFA98XX_BAT_PROT_CONFIG_BSSCR (0x3 << 0) +#define TFA98XX_BAT_PROT_CONFIG_BSSCR_POS 0 +#define TFA98XX_BAT_PROT_CONFIG_BSSCR_LEN 2 +#define TFA98XX_BAT_PROT_CONFIG_BSSCR_MAX 3 +#define TFA98XX_BAT_PROT_CONFIG_BSSCR_MSK 0x3 + +/* + * vbat_prot_thlevel + */ +#define TFA98XX_BAT_PROT_CONFIG_BSST (0xf << 2) +#define TFA98XX_BAT_PROT_CONFIG_BSST_POS 2 +#define TFA98XX_BAT_PROT_CONFIG_BSST_LEN 4 +#define TFA98XX_BAT_PROT_CONFIG_BSST_MAX 15 +#define TFA98XX_BAT_PROT_CONFIG_BSST_MSK 0x3c + +/* + * vbat_prot_max_reduct + */ +#define TFA98XX_BAT_PROT_CONFIG_BSSRL (0x3 << 6) +#define TFA98XX_BAT_PROT_CONFIG_BSSRL_POS 6 +#define TFA98XX_BAT_PROT_CONFIG_BSSRL_LEN 2 +#define TFA98XX_BAT_PROT_CONFIG_BSSRL_MAX 3 +#define TFA98XX_BAT_PROT_CONFIG_BSSRL_MSK 0xc0 + +/* + * vbat_prot_release_time + */ +#define TFA98XX_BAT_PROT_CONFIG_BSSRR (0x7 << 8) +#define TFA98XX_BAT_PROT_CONFIG_BSSRR_POS 8 +#define TFA98XX_BAT_PROT_CONFIG_BSSRR_LEN 3 +#define TFA98XX_BAT_PROT_CONFIG_BSSRR_MAX 7 +#define TFA98XX_BAT_PROT_CONFIG_BSSRR_MSK 0x700 + +/* + * vbat_prot_hysterese + */ +#define TFA98XX_BAT_PROT_CONFIG_BSSHY (0x3 << 11) +#define TFA98XX_BAT_PROT_CONFIG_BSSHY_POS 11 +#define TFA98XX_BAT_PROT_CONFIG_BSSHY_LEN 2 +#define TFA98XX_BAT_PROT_CONFIG_BSSHY_MAX 3 +#define TFA98XX_BAT_PROT_CONFIG_BSSHY_MSK 0x1800 + +/* + * sel_vbat + */ +#define TFA98XX_BAT_PROT_CONFIG_BSSR (0x1 << 14) +#define TFA98XX_BAT_PROT_CONFIG_BSSR_POS 14 +#define TFA98XX_BAT_PROT_CONFIG_BSSR_LEN 1 +#define TFA98XX_BAT_PROT_CONFIG_BSSR_MAX 1 +#define TFA98XX_BAT_PROT_CONFIG_BSSR_MSK 0x4000 + +/* + * bypass_clipper + */ +#define TFA98XX_BAT_PROT_CONFIG_BSSBY (0x1 << 15) +#define TFA98XX_BAT_PROT_CONFIG_BSSBY_POS 15 +#define TFA98XX_BAT_PROT_CONFIG_BSSBY_LEN 1 +#define TFA98XX_BAT_PROT_CONFIG_BSSBY_MAX 1 +#define TFA98XX_BAT_PROT_CONFIG_BSSBY_MSK 0x8000 + +/* + * (0x51)-audio_control + */ + +/* + * batsense_steepness + */ +#define TFA98XX_AUDIO_CONTROL_BSSS (0x1 << 0) +#define TFA98XX_AUDIO_CONTROL_BSSS_POS 0 +#define TFA98XX_AUDIO_CONTROL_BSSS_LEN 1 +#define TFA98XX_AUDIO_CONTROL_BSSS_MAX 1 +#define TFA98XX_AUDIO_CONTROL_BSSS_MSK 0x1 + +/* + * soft_mute + */ +#define TFA98XX_AUDIO_CONTROL_INTSMUTE (0x1 << 1) +#define TFA98XX_AUDIO_CONTROL_INTSMUTE_POS 1 +#define TFA98XX_AUDIO_CONTROL_INTSMUTE_LEN 1 +#define TFA98XX_AUDIO_CONTROL_INTSMUTE_MAX 1 +#define TFA98XX_AUDIO_CONTROL_INTSMUTE_MSK 0x2 + +/* + * cf_mute_left + */ +#define TFA98XX_AUDIO_CONTROL_CFSML (0x1 << 2) +#define TFA98XX_AUDIO_CONTROL_CFSML_POS 2 +#define TFA98XX_AUDIO_CONTROL_CFSML_LEN 1 +#define TFA98XX_AUDIO_CONTROL_CFSML_MAX 1 +#define TFA98XX_AUDIO_CONTROL_CFSML_MSK 0x4 + +/* + * cf_mute_right + */ +#define TFA98XX_AUDIO_CONTROL_CFSMR (0x1 << 3) +#define TFA98XX_AUDIO_CONTROL_CFSMR_POS 3 +#define TFA98XX_AUDIO_CONTROL_CFSMR_LEN 1 +#define TFA98XX_AUDIO_CONTROL_CFSMR_MAX 1 +#define TFA98XX_AUDIO_CONTROL_CFSMR_MSK 0x8 + +/* + * bypass_hp_left + */ +#define TFA98XX_AUDIO_CONTROL_HPFBYPL (0x1 << 4) +#define TFA98XX_AUDIO_CONTROL_HPFBYPL_POS 4 +#define TFA98XX_AUDIO_CONTROL_HPFBYPL_LEN 1 +#define TFA98XX_AUDIO_CONTROL_HPFBYPL_MAX 1 +#define TFA98XX_AUDIO_CONTROL_HPFBYPL_MSK 0x10 + +/* + * bypass_hp_right + */ +#define TFA98XX_AUDIO_CONTROL_HPFBYPR (0x1 << 5) +#define TFA98XX_AUDIO_CONTROL_HPFBYPR_POS 5 +#define TFA98XX_AUDIO_CONTROL_HPFBYPR_LEN 1 +#define TFA98XX_AUDIO_CONTROL_HPFBYPR_MAX 1 +#define TFA98XX_AUDIO_CONTROL_HPFBYPR_MSK 0x20 + +/* + * enbl_dpsa_left + */ +#define TFA98XX_AUDIO_CONTROL_DPSAL (0x1 << 6) +#define TFA98XX_AUDIO_CONTROL_DPSAL_POS 6 +#define TFA98XX_AUDIO_CONTROL_DPSAL_LEN 1 +#define TFA98XX_AUDIO_CONTROL_DPSAL_MAX 1 +#define TFA98XX_AUDIO_CONTROL_DPSAL_MSK 0x40 + +/* + * enbl_dpsa_right + */ +#define TFA98XX_AUDIO_CONTROL_DPSAR (0x1 << 7) +#define TFA98XX_AUDIO_CONTROL_DPSAR_POS 7 +#define TFA98XX_AUDIO_CONTROL_DPSAR_LEN 1 +#define TFA98XX_AUDIO_CONTROL_DPSAR_MAX 1 +#define TFA98XX_AUDIO_CONTROL_DPSAR_MSK 0x80 + +/* + * cf_volume + */ +#define TFA98XX_AUDIO_CONTROL_VOL (0xff << 8) +#define TFA98XX_AUDIO_CONTROL_VOL_POS 8 +#define TFA98XX_AUDIO_CONTROL_VOL_LEN 8 +#define TFA98XX_AUDIO_CONTROL_VOL_MAX 255 +#define TFA98XX_AUDIO_CONTROL_VOL_MSK 0xff00 + +/* + * (0x52)-amplifier_config + */ + +/* + * ctrl_rcv + */ +#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV (0x1 << 0) +#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_POS 0 +#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_LEN 1 +#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_MAX 1 +#define TFA98XX_AMPLIFIER_CONFIG_HNDSFRCV_MSK 0x1 + +/* + * ctrl_cc + */ +#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL (0x7 << 2) +#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_POS 2 +#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_LEN 3 +#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_MAX 7 +#define TFA98XX_AMPLIFIER_CONFIG_CLIPCTRL_MSK 0x1c + +/* + * gain + */ +#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN (0xff << 5) +#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_POS 5 +#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_LEN 8 +#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_MAX 255 +#define TFA98XX_AMPLIFIER_CONFIG_AMPGAIN_MSK 0x1fe0 + +/* + * ctrl_slopectrl + */ +#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE (0x1 << 13) +#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_POS 13 +#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_LEN 1 +#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_MAX 1 +#define TFA98XX_AMPLIFIER_CONFIG_SLOPEE_MSK 0x2000 + +/* + * ctrl_slope + */ +#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET (0x3 << 14) +#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_POS 14 +#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_LEN 2 +#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_MAX 3 +#define TFA98XX_AMPLIFIER_CONFIG_SLOPESET_MSK 0xc000 + +/* + * (0x5a)-audio_control2 + */ + +/* + * cf_volume_sec + */ +#define TFA98XX_AUDIO_CONTROL2_VOLSEC (0xff << 0) +#define TFA98XX_AUDIO_CONTROL2_VOLSEC_POS 0 +#define TFA98XX_AUDIO_CONTROL2_VOLSEC_LEN 8 +#define TFA98XX_AUDIO_CONTROL2_VOLSEC_MAX 255 +#define TFA98XX_AUDIO_CONTROL2_VOLSEC_MSK 0xff + +/* + * sw_profile + */ +#define TFA98XX_AUDIO_CONTROL2_SWPROFIL (0xff << 8) +#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_POS 8 +#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_LEN 8 +#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_MAX 255 +#define TFA98XX_AUDIO_CONTROL2_SWPROFIL_MSK 0xff00 + +/* + * (0x70)-dcdc_control0 + */ + +/* + * boost_volt + */ +#define TFA98XX_DCDC_CONTROL0_DCVO (0x7 << 0) +#define TFA98XX_DCDC_CONTROL0_DCVO_POS 0 +#define TFA98XX_DCDC_CONTROL0_DCVO_LEN 3 +#define TFA98XX_DCDC_CONTROL0_DCVO_MAX 7 +#define TFA98XX_DCDC_CONTROL0_DCVO_MSK 0x7 + +/* + * boost_cur + */ +#define TFA98XX_DCDC_CONTROL0_DCMCC (0xf << 3) +#define TFA98XX_DCDC_CONTROL0_DCMCC_POS 3 +#define TFA98XX_DCDC_CONTROL0_DCMCC_LEN 4 +#define TFA98XX_DCDC_CONTROL0_DCMCC_MAX 15 +#define TFA98XX_DCDC_CONTROL0_DCMCC_MSK 0x78 + +/* + * bst_coil_value + */ +#define TFA98XX_DCDC_CONTROL0_DCCV (0x3 << 7) +#define TFA98XX_DCDC_CONTROL0_DCCV_POS 7 +#define TFA98XX_DCDC_CONTROL0_DCCV_LEN 2 +#define TFA98XX_DCDC_CONTROL0_DCCV_MAX 3 +#define TFA98XX_DCDC_CONTROL0_DCCV_MSK 0x180 + +/* + * boost_intel + */ +#define TFA98XX_DCDC_CONTROL0_DCIE (0x1 << 9) +#define TFA98XX_DCDC_CONTROL0_DCIE_POS 9 +#define TFA98XX_DCDC_CONTROL0_DCIE_LEN 1 +#define TFA98XX_DCDC_CONTROL0_DCIE_MAX 1 +#define TFA98XX_DCDC_CONTROL0_DCIE_MSK 0x200 + +/* + * boost_speed + */ +#define TFA98XX_DCDC_CONTROL0_DCSR (0x1 << 10) +#define TFA98XX_DCDC_CONTROL0_DCSR_POS 10 +#define TFA98XX_DCDC_CONTROL0_DCSR_LEN 1 +#define TFA98XX_DCDC_CONTROL0_DCSR_MAX 1 +#define TFA98XX_DCDC_CONTROL0_DCSR_MSK 0x400 + +/* + * dcdc_synchronisation + */ +#define TFA98XX_DCDC_CONTROL0_DCSYNCP (0x7 << 11) +#define TFA98XX_DCDC_CONTROL0_DCSYNCP_POS 11 +#define TFA98XX_DCDC_CONTROL0_DCSYNCP_LEN 3 +#define TFA98XX_DCDC_CONTROL0_DCSYNCP_MAX 7 +#define TFA98XX_DCDC_CONTROL0_DCSYNCP_MSK 0x3800 + +/* + * dcdcoff_mode + */ +#define TFA98XX_DCDC_CONTROL0_DCDIS (0x1 << 14) +#define TFA98XX_DCDC_CONTROL0_DCDIS_POS 14 +#define TFA98XX_DCDC_CONTROL0_DCDIS_LEN 1 +#define TFA98XX_DCDC_CONTROL0_DCDIS_MAX 1 +#define TFA98XX_DCDC_CONTROL0_DCDIS_MSK 0x4000 + +/* + * (0x90)-cf_controls + */ + +/* + * cf_rst_dsp + */ +#define TFA98XX_CF_CONTROLS_RST (0x1 << 0) +#define TFA98XX_CF_CONTROLS_RST_POS 0 +#define TFA98XX_CF_CONTROLS_RST_LEN 1 +#define TFA98XX_CF_CONTROLS_RST_MAX 1 +#define TFA98XX_CF_CONTROLS_RST_MSK 0x1 + +/* + * cf_dmem + */ +#define TFA98XX_CF_CONTROLS_DMEM (0x3 << 1) +#define TFA98XX_CF_CONTROLS_DMEM_POS 1 +#define TFA98XX_CF_CONTROLS_DMEM_LEN 2 +#define TFA98XX_CF_CONTROLS_DMEM_MAX 3 +#define TFA98XX_CF_CONTROLS_DMEM_MSK 0x6 + +/* + * cf_aif + */ +#define TFA98XX_CF_CONTROLS_AIF (0x1 << 3) +#define TFA98XX_CF_CONTROLS_AIF_POS 3 +#define TFA98XX_CF_CONTROLS_AIF_LEN 1 +#define TFA98XX_CF_CONTROLS_AIF_MAX 1 +#define TFA98XX_CF_CONTROLS_AIF_MSK 0x8 + +/* + * cf_int + */ +#define TFA98XX_CF_CONTROLS_CFINT (0x1 << 4) +#define TFA98XX_CF_CONTROLS_CFINT_POS 4 +#define TFA98XX_CF_CONTROLS_CFINT_LEN 1 +#define TFA98XX_CF_CONTROLS_CFINT_MAX 1 +#define TFA98XX_CF_CONTROLS_CFINT_MSK 0x10 + +/* + * cf_cgate_off + */ +#define TFA98XX_CF_CONTROLS_CFCGATE (0x1 << 5) +#define TFA98XX_CF_CONTROLS_CFCGATE_POS 5 +#define TFA98XX_CF_CONTROLS_CFCGATE_LEN 1 +#define TFA98XX_CF_CONTROLS_CFCGATE_MAX 1 +#define TFA98XX_CF_CONTROLS_CFCGATE_MSK 0x20 + +/* + * cf_req_cmd + */ +#define TFA98XX_CF_CONTROLS_REQCMD (0x1 << 8) +#define TFA98XX_CF_CONTROLS_REQCMD_POS 8 +#define TFA98XX_CF_CONTROLS_REQCMD_LEN 1 +#define TFA98XX_CF_CONTROLS_REQCMD_MAX 1 +#define TFA98XX_CF_CONTROLS_REQCMD_MSK 0x100 + +/* + * cf_req_reset + */ +#define TFA98XX_CF_CONTROLS_REQRST (0x1 << 9) +#define TFA98XX_CF_CONTROLS_REQRST_POS 9 +#define TFA98XX_CF_CONTROLS_REQRST_LEN 1 +#define TFA98XX_CF_CONTROLS_REQRST_MAX 1 +#define TFA98XX_CF_CONTROLS_REQRST_MSK 0x200 + +/* + * cf_req_mips + */ +#define TFA98XX_CF_CONTROLS_REQMIPS (0x1 << 10) +#define TFA98XX_CF_CONTROLS_REQMIPS_POS 10 +#define TFA98XX_CF_CONTROLS_REQMIPS_LEN 1 +#define TFA98XX_CF_CONTROLS_REQMIPS_MAX 1 +#define TFA98XX_CF_CONTROLS_REQMIPS_MSK 0x400 + +/* + * cf_req_mute_ready + */ +#define TFA98XX_CF_CONTROLS_REQMUTED (0x1 << 11) +#define TFA98XX_CF_CONTROLS_REQMUTED_POS 11 +#define TFA98XX_CF_CONTROLS_REQMUTED_LEN 1 +#define TFA98XX_CF_CONTROLS_REQMUTED_MAX 1 +#define TFA98XX_CF_CONTROLS_REQMUTED_MSK 0x800 + +/* + * cf_req_volume_ready + */ +#define TFA98XX_CF_CONTROLS_REQVOL (0x1 << 12) +#define TFA98XX_CF_CONTROLS_REQVOL_POS 12 +#define TFA98XX_CF_CONTROLS_REQVOL_LEN 1 +#define TFA98XX_CF_CONTROLS_REQVOL_MAX 1 +#define TFA98XX_CF_CONTROLS_REQVOL_MSK 0x1000 + +/* + * cf_req_damage + */ +#define TFA98XX_CF_CONTROLS_REQDMG (0x1 << 13) +#define TFA98XX_CF_CONTROLS_REQDMG_POS 13 +#define TFA98XX_CF_CONTROLS_REQDMG_LEN 1 +#define TFA98XX_CF_CONTROLS_REQDMG_MAX 1 +#define TFA98XX_CF_CONTROLS_REQDMG_MSK 0x2000 + +/* + * cf_req_calibrate_ready + */ +#define TFA98XX_CF_CONTROLS_REQCAL (0x1 << 14) +#define TFA98XX_CF_CONTROLS_REQCAL_POS 14 +#define TFA98XX_CF_CONTROLS_REQCAL_LEN 1 +#define TFA98XX_CF_CONTROLS_REQCAL_MAX 1 +#define TFA98XX_CF_CONTROLS_REQCAL_MSK 0x4000 + +/* + * cf_req_reserved + */ +#define TFA98XX_CF_CONTROLS_REQRSV (0x1 << 15) +#define TFA98XX_CF_CONTROLS_REQRSV_POS 15 +#define TFA98XX_CF_CONTROLS_REQRSV_LEN 1 +#define TFA98XX_CF_CONTROLS_REQRSV_MAX 1 +#define TFA98XX_CF_CONTROLS_REQRSV_MSK 0x8000 + +/* + * (0x91)-cf_mad + */ + +/* + * cf_madd + */ +#define TFA98XX_CF_MAD_MADD (0xffff << 0) +#define TFA98XX_CF_MAD_MADD_POS 0 +#define TFA98XX_CF_MAD_MADD_LEN 16 +#define TFA98XX_CF_MAD_MADD_MAX 65535 +#define TFA98XX_CF_MAD_MADD_MSK 0xffff + +/* + * (0x92)-cf_mem + */ + +/* + * cf_mema + */ +#define TFA98XX_CF_MEM_MEMA (0xffff << 0) +#define TFA98XX_CF_MEM_MEMA_POS 0 +#define TFA98XX_CF_MEM_MEMA_LEN 16 +#define TFA98XX_CF_MEM_MEMA_MAX 65535 +#define TFA98XX_CF_MEM_MEMA_MSK 0xffff + +/* + * (0x93)-cf_status + */ + +/* + * cf_err + */ +#define TFA98XX_CF_STATUS_ERR (0xff << 0) +#define TFA98XX_CF_STATUS_ERR_POS 0 +#define TFA98XX_CF_STATUS_ERR_LEN 8 +#define TFA98XX_CF_STATUS_ERR_MAX 255 +#define TFA98XX_CF_STATUS_ERR_MSK 0xff + +/* + * cf_ack_cmd + */ +#define TFA98XX_CF_STATUS_ACKCMD (0x1 << 8) +#define TFA98XX_CF_STATUS_ACKCMD_POS 8 +#define TFA98XX_CF_STATUS_ACKCMD_LEN 1 +#define TFA98XX_CF_STATUS_ACKCMD_MAX 1 +#define TFA98XX_CF_STATUS_ACKCMD_MSK 0x100 + +/* + * cf_ack_reset + */ +#define TFA98XX_CF_STATUS_ACKRST (0x1 << 9) +#define TFA98XX_CF_STATUS_ACKRST_POS 9 +#define TFA98XX_CF_STATUS_ACKRST_LEN 1 +#define TFA98XX_CF_STATUS_ACKRST_MAX 1 +#define TFA98XX_CF_STATUS_ACKRST_MSK 0x200 + +/* + * cf_ack_mips + */ +#define TFA98XX_CF_STATUS_ACKMIPS (0x1 << 10) +#define TFA98XX_CF_STATUS_ACKMIPS_POS 10 +#define TFA98XX_CF_STATUS_ACKMIPS_LEN 1 +#define TFA98XX_CF_STATUS_ACKMIPS_MAX 1 +#define TFA98XX_CF_STATUS_ACKMIPS_MSK 0x400 + +/* + * cf_ack_mute_ready + */ +#define TFA98XX_CF_STATUS_ACKMUTED (0x1 << 11) +#define TFA98XX_CF_STATUS_ACKMUTED_POS 11 +#define TFA98XX_CF_STATUS_ACKMUTED_LEN 1 +#define TFA98XX_CF_STATUS_ACKMUTED_MAX 1 +#define TFA98XX_CF_STATUS_ACKMUTED_MSK 0x800 + +/* + * cf_ack_volume_ready + */ +#define TFA98XX_CF_STATUS_ACKVOL (0x1 << 12) +#define TFA98XX_CF_STATUS_ACKVOL_POS 12 +#define TFA98XX_CF_STATUS_ACKVOL_LEN 1 +#define TFA98XX_CF_STATUS_ACKVOL_MAX 1 +#define TFA98XX_CF_STATUS_ACKVOL_MSK 0x1000 + +/* + * cf_ack_damage + */ +#define TFA98XX_CF_STATUS_ACKDMG (0x1 << 13) +#define TFA98XX_CF_STATUS_ACKDMG_POS 13 +#define TFA98XX_CF_STATUS_ACKDMG_LEN 1 +#define TFA98XX_CF_STATUS_ACKDMG_MAX 1 +#define TFA98XX_CF_STATUS_ACKDMG_MSK 0x2000 + +/* + * cf_ack_calibrate_ready + */ +#define TFA98XX_CF_STATUS_ACKCAL (0x1 << 14) +#define TFA98XX_CF_STATUS_ACKCAL_POS 14 +#define TFA98XX_CF_STATUS_ACKCAL_LEN 1 +#define TFA98XX_CF_STATUS_ACKCAL_MAX 1 +#define TFA98XX_CF_STATUS_ACKCAL_MSK 0x4000 + +/* + * cf_ack_reserved + */ +#define TFA98XX_CF_STATUS_ACKRSV (0x1 << 15) +#define TFA98XX_CF_STATUS_ACKRSV_POS 15 +#define TFA98XX_CF_STATUS_ACKRSV_LEN 1 +#define TFA98XX_CF_STATUS_ACKRSV_MAX 1 +#define TFA98XX_CF_STATUS_ACKRSV_MSK 0x8000 + +/* + * (0xa1)-mtpkey2_reg + */ + +/* + * mtpkey2 + */ +#define TFA98XX_MTPKEY2_REG_MTPK (0xff << 0) +#define TFA98XX_MTPKEY2_REG_MTPK_POS 0 +#define TFA98XX_MTPKEY2_REG_MTPK_LEN 8 +#define TFA98XX_MTPKEY2_REG_MTPK_MAX 255 +#define TFA98XX_MTPKEY2_REG_MTPK_MSK 0xff + +/* + * (0xa2)-mtp_status + */ + +/* + * key01_locked + */ +#define TFA98XX_MTP_STATUS_KEY1LOCKED (0x1 << 0) +#define TFA98XX_MTP_STATUS_KEY1LOCKED_POS 0 +#define TFA98XX_MTP_STATUS_KEY1LOCKED_LEN 1 +#define TFA98XX_MTP_STATUS_KEY1LOCKED_MAX 1 +#define TFA98XX_MTP_STATUS_KEY1LOCKED_MSK 0x1 + +/* + * key02_locked + */ +#define TFA98XX_MTP_STATUS_KEY2LOCKED (0x1 << 1) +#define TFA98XX_MTP_STATUS_KEY2LOCKED_POS 1 +#define TFA98XX_MTP_STATUS_KEY2LOCKED_LEN 1 +#define TFA98XX_MTP_STATUS_KEY2LOCKED_MAX 1 +#define TFA98XX_MTP_STATUS_KEY2LOCKED_MSK 0x2 + +/* + * (0xa3)-KEY_protected_mtp_control + */ + +/* + * auto_copy_iic_to_mtp + */ +#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP (0x1 << 6) +#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_POS 6 +#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_LEN 1 +#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_MAX 1 +#define TFA98XX_KEY_PROTECTED_MTP_CONTROL_CIMTP_MSK 0x40 + +/* + * (0xa5)-mtp_data_out_msb + */ + +/* + * mtp_man_data_out_msb + */ +#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB (0xffff << 0) +#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_POS 0 +#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_LEN 16 +#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_MAX 65535 +#define TFA98XX_MTP_DATA_OUT_MSB_MTPRDMSB_MSK 0xffff + +/* + * (0xa6)-mtp_data_out_lsb + */ + +/* + * mtp_man_data_out_lsb + */ +#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB (0xffff << 0) +#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_POS 0 +#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_LEN 16 +#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_MAX 65535 +#define TFA98XX_MTP_DATA_OUT_LSB_MTPRDLSB_MSK 0xffff + +/* + * (0xb1)-temp_sensor_config + */ + +/* + * ext_temp + */ +#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS (0x1ff << 0) +#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_POS 0 +#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_LEN 9 +#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_MAX 511 +#define TFA98XX_TEMP_SENSOR_CONFIG_EXTTS_MSK 0x1ff + +/* + * ext_temp_sel + */ +#define TFA98XX_TEMP_SENSOR_CONFIG_TROS (0x1 << 9) +#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_POS 9 +#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_LEN 1 +#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_MAX 1 +#define TFA98XX_TEMP_SENSOR_CONFIG_TROS_MSK 0x200 + +/* + * (0xf0)-KEY2_protected_MTP0 + */ + +/* + * calibration_onetime + */ +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC (0x1 << 0) +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_POS 0 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_LEN 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MAX 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK 0x1 + +/* + * calibr_ron_done + */ +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX (0x1 << 1) +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_LEN 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MAX 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK 0x2 + +/* + * calibr_dcdc_api_calibrate + */ +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI (0x1 << 2) +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_POS 2 +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_LEN 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_MAX 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCAPI_MSK 0x4 + +/* + * calibr_dcdc_delta_sign + */ +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB (0x1 << 3) +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_POS 3 +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_LEN 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_MAX 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_DCMCCSB_MSK 0x8 + +/* + * calibr_dcdc_delta + */ +#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF (0x7 << 4) +#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_POS 4 +#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_LEN 3 +#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_MAX 7 +#define TFA98XX_KEY2_PROTECTED_MTP0_USERDEF_MSK 0x70 + +/* + * (0xf4)-KEY1_protected_MTP4 + */ + +/* + * (0xf5)-KEY1_protected_MTP5 + */ + +#endif /* TFA98XX_GENREGS_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_parameters.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_parameters.h new file mode 100644 index 000000000000..f24745431ed6 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_parameters.h @@ -0,0 +1,744 @@ +/* + * Copyright 2013-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * tfa98xx_parameters.h + * + * Created on: Jul 22, 2013 + * Author: NLV02095 + */ + +#ifndef TFA98XXPARAMETERS_H_ +#define TFA98XXPARAMETERS_H_ + +//#include "config.h" +// workaround for Visual Studio: +// fatal error C1083: Cannot open include file: 'config.h': No such file or directory +#ifdef __KERNEL__ +#include +#else +#include +#endif + +#include "tfa_service.h" + +#if (defined(WIN32) || defined(_X64)) +/* These warnings are disabled because it is only given by Windows and there is no easy fix */ +#pragma warning(disable : 4200) +#pragma warning(disable : 4214) +#endif + +/* + * profiles & volumesteps + * + */ +#define TFA_MAX_PROFILES (64) +#define TFA_MAX_VSTEPS (64) +#define TFA_MAX_VSTEP_MSG_MARKER \ + (100) /* This marker is used to indicate if all msgs need to be written to the device */ +#define TFA_MAX_MSGS (10) + +// the pack pragma is required to make that the size in memory +// matches the actual variable lenghts +// This is to assure that the binary files can be transported between +// different platforms. +#pragma pack(push, 1) + +/* + * typedef for 24 bit value using 3 bytes + */ +typedef struct uint24 { + uint8_t b[3]; +} uint24_t; +/* + * the generic header + * all char types are in ASCII + */ +typedef struct nxpTfaHeader { + uint16_t id; + char version[2]; // "V_" : V=version, vv=subversion + char subversion[2]; // "vv" : vv=subversion + uint16_t size; // data size in bytes following CRC + uint32_t CRC; // 32-bits CRC for following data + char customer[8]; // “name of customer†+ char application[8]; // “application name†+ char type[8]; // “application type name†+} nxpTfaHeader_t; + +typedef enum nxpTfaSamplerate { + fs_8k, // 8kHz + fs_11k025, // 11.025kHz + fs_12k, // 12kHz + fs_16k, // 16kHz + fs_22k05, // 22.05kHz + fs_24k, // 24kHz + fs_32k, // 32kHz + fs_44k1, // 44.1kHz + fs_48k, // 48kHz + fs_96k, // 96kHz + fs_count // Should always be last item. +} nxpTfaSamplerate_t; + +// Keep in sync with nxpTfaSamplerate_t ! +static const int nxpTfaSamplerateHz[fs_count] = { 8000, 11025, 12000, 16000, + 22050, 24000, 32000, 44100, + 48000, 96000 }; + +/* + * coolflux direct memory access + */ +typedef struct nxpTfaDspMem { + uint8_t type; /* 0--3: p, x, y, iomem */ + uint16_t address; /* target address */ + uint8_t size; /* data size in words */ + int words[]; /* payload in signed 32bit integer (two's complement) */ +} nxpTfaDspMem_t; + +/* + * the biquad coefficients for the API together with index in filter + * the biquad_index is the actual index in the equalizer +1 + */ +#define BIQUAD_COEFF_SIZE 6 + +/* +* Output fixed point coeffs structure +*/ +typedef struct { + int a2; + int a1; + int b2; + int b1; + int b0; +} nxpTfaBiquad_t; + +typedef struct nxpTfaBiquadOld { + uint8_t bytes[BIQUAD_COEFF_SIZE * sizeof(uint24_t)]; +} nxpTfaBiquadOld_t; + +typedef struct nxpTfaBiquadFloat { + float headroom; + float b0; + float b1; + float b2; + float a1; + float a2; +} nxpTfaBiquadFloat_t; + +/* +* EQ filter definitions +* Note: This is not in line with smartstudio (JV: 12/12/2016) +*/ +typedef enum nxpTfaFilterType { + fCustom, //User defined biquad coefficients + fFlat, //Vary only gain + fLowpass, //2nd order Butterworth low pass + fHighpass, //2nd order Butterworth high pass + fLowshelf, + fHighshelf, + fNotch, + fPeak, + fBandpass, + f1stLP, + f1stHP, + fElliptic +} nxpTfaFilterType_t; + +/* + * filter parameters for biquad (re-)calculation + */ +typedef struct nxpTfaFilter { + nxpTfaBiquadOld_t biquad; + uint8_t enabled; + uint8_t type; // (== enum FilterTypes, assure 8bits length) + float frequency; + float Q; + float gain; +} nxpTfaFilter_t; //8 * float + int32 + byte == 37 + +/* + * biquad params for calculation +*/ + +#define TFA_BQ_EQ_INDEX 0 +#define TFA_BQ_ANTI_ALIAS_INDEX 10 +#define TFA_BQ_INTEGRATOR_INDEX 13 + +/* +* Loudspeaker Compensation filter definitions +*/ +typedef struct nxpTfaLsCompensationFilter { + nxpTfaBiquad_t biquad; + uint8_t lsCompOn; // Loudspeaker compensation on/off; when 'off', the DSP code doesn't apply the bwExt => bwExtOn GUI flag should be gray to avoid confusion + uint8_t bwExtOn; // Bandwidth extension on/off + float fRes; // [Hz] speaker resonance frequency + float Qt; // Speaker resonance Q-factor + float fBwExt; // [Hz] Band width extension frequency + float samplingFreq; // [Hz] Sampling frequency +} nxpTfaLsCompensationFilter_t; + +/* +* Anti Aliasing Elliptic filter definitions +*/ +typedef struct nxpTfaAntiAliasFilter { + nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */ + uint8_t enabled; + float cutOffFreq; // cut off frequency + float samplingFreq; // sampling frequency + float rippleDb; // range: [0.1 3.0] + float rolloff; // range: [-1.0 1.0] +} nxpTfaAntiAliasFilter_t; + +/** +* Integrator filter input definitions +*/ +typedef struct nxpTfaIntegratorFilter { + nxpTfaBiquad_t biquad; /**< Output results fixed point coeffs */ + uint8_t type; /**< Butterworth filter type: high or low pass */ + float cutOffFreq; /**< cut off frequency in Hertz; range: [100.0 4000.0] */ + float samplingFreq; /**< sampling frequency in Hertz */ + float leakage; /**< leakage factor; range [0.0 1.0] */ +} nxpTfaIntegratorFilter_t; + +typedef struct nxpTfaEqFilter { + nxpTfaBiquad_t biquad; + uint8_t enabled; + uint8_t type; // (== enum FilterTypes, assure 8bits length) + float cutOffFreq; // cut off frequency, // range: [100.0 4000.0] + float samplingFreq; // sampling frequency + float Q; // range: [0.5 5.0] + float gainDb; // range: [-10.0 10.0] +} nxpTfaEqFilter_t; //8 * float + int32 + byte == 37 + +typedef struct nxpTfaContAntiAlias { + int8_t index; /**< index determines destination type; anti-alias, integrator,eq */ + uint8_t type; + float cutOffFreq; // cut off frequency + float samplingFreq; + float rippleDb; // integrator leakage + float rolloff; + uint8_t bytes[5 * 3]; // payload 5*24buts coeffs +} nxpTfaContAntiAlias_t; + +typedef struct nxpTfaContIntegrator { + int8_t index; /**< index determines destination type; anti-alias, integrator,eq */ + uint8_t type; + float cutOffFreq; // cut off frequency + float samplingFreq; + float leakage; // integrator leakage + float reserved; + uint8_t bytes[5 * 3]; // payload 5*24buts coeffs +} nxpTfaContIntegrator_t; + +typedef struct nxpTfaContEq { + int8_t index; + uint8_t type; // (== enum FilterTypes, assure 8bits length) + float cutOffFreq; // cut off frequency, // range: [100.0 4000.0] + float samplingFreq; // sampling frequency + float Q; // range: [0.5 5.0] + float gainDb; // range: [-10.0 10.0] + uint8_t bytes[5 * 3]; // payload 5*24buts coeffs +} nxpTfaContEq_t; //8 * float + int32 + byte == 37 + +typedef union nxpTfaContBiquad { + nxpTfaContEq_t eq; + nxpTfaContAntiAlias_t aa; + nxpTfaContIntegrator_t in; +} nxpTfaContBiquad_t; + +#define TFA_BQ_EQ_INDEX 0 +#define TFA_BQ_ANTI_ALIAS_INDEX 10 +#define TFA_BQ_INTEGRATOR_INDEX 13 +#define TFA98XX_MAX_EQ 10 + +typedef struct nxpTfaEqualizer { + nxpTfaFilter_t filter[TFA98XX_MAX_EQ]; +} nxpTfaEqualizer_t; + +/* + * files + */ +#define HDR(c1, c2) (c2 << 8 | c1) // little endian +typedef enum nxpTfaHeaderType { + paramsHdr = HDR('P', 'M'), /* containter file */ + volstepHdr = HDR('V', 'P'), + patchHdr = HDR('P', 'A'), + speakerHdr = HDR('S', 'P'), + presetHdr = HDR('P', 'R'), + configHdr = HDR('C', 'O'), + equalizerHdr = HDR('E', 'Q'), + drcHdr = HDR('D', 'R'), + msgHdr = HDR('M', 'G'), /* generic message */ + infoHdr = HDR('I', 'N') +} nxpTfaHeaderType_t; + +/* + * equalizer file + */ +#define NXPTFA_EQ_VERSION '1' +#define NXPTFA_EQ_SUBVERSION "00" +typedef struct nxpTfaEqualizerFile { + nxpTfaHeader_t hdr; + uint8_t samplerate; // ==enum samplerates, assure 8 bits + nxpTfaFilter_t + filter[TFA98XX_MAX_EQ]; // note: API index counts from 1..10 +} nxpTfaEqualizerFile_t; + +/* + * patch file + */ +#define NXPTFA_PA_VERSION '1' +#define NXPTFA_PA_SUBVERSION "00" +typedef struct nxpTfaPatchFile { + nxpTfaHeader_t hdr; + uint8_t data[]; +} nxpTfaPatch_t; + +/* + * generic message file + * - the payload of this file includes the opcode and is send straight to the DSP + */ +#define NXPTFA_MG_VERSION '3' +#define NXPTFA_MG_SUBVERSION "00" +typedef struct nxpTfaMsgFile { + nxpTfaHeader_t hdr; + uint8_t data[]; +} nxpTfaMsgFile_t; + +/* + * NOTE the tfa98xx API defines the enum Tfa98xx_config_type that defines + * the subtypes as decribes below. + * tfa98xx_dsp_config_parameter_type() can be used to get the + * supported type for the active device.. + */ +/* + * config file V1 sub 1 + */ +#define NXPTFA_CO_VERSION '1' +#define NXPTFA_CO3_VERSION '3' +#define NXPTFA_CO_SUBVERSION1 "01" +typedef struct nxpTfaConfigS1File { + nxpTfaHeader_t hdr; + uint8_t data[55 * 3]; +} nxpTfaConfigS1_t; + +/* + * config file V1 sub 2 + */ +#define NXPTFA_CO_SUBVERSION2 "02" +typedef struct nxpTfaConfigS2File { + nxpTfaHeader_t hdr; + uint8_t data[67 * 3]; +} nxpTfaConfigS2_t; + +/* + * config file V1 sub 3 + */ +#define NXPTFA_CO_SUBVERSION3 "03" +typedef struct nxpTfaConfigS3File { + nxpTfaHeader_t hdr; + uint8_t data[67 * 3]; +} nxpTfaConfigS3_t; + +/* + * config file V1.0 + */ +#define NXPTFA_CO_SUBVERSION "00" +typedef struct nxpTfaConfigFile { + nxpTfaHeader_t hdr; + uint8_t data[]; +} nxpTfaConfig_t; + +/* + * preset file + */ +#define NXPTFA_PR_VERSION '1' +#define NXPTFA_PR_SUBVERSION "00" +typedef struct nxpTfaPresetFile { + nxpTfaHeader_t hdr; + uint8_t data[]; +} nxpTfaPreset_t; + +/* + * drc file + */ +#define NXPTFA_DR_VERSION '1' +#define NXPTFA_DR_SUBVERSION "00" +typedef struct nxpTfaDrcFile { + nxpTfaHeader_t hdr; + uint8_t data[]; +} nxpTfaDrc_t; + +/* + * drc file + * for tfa 2 there is also a xml-version + */ +#define NXPTFA_DR3_VERSION '3' +#define NXPTFA_DR3_SUBVERSION "00" +typedef struct nxpTfaDrcFile2 { + nxpTfaHeader_t hdr; + uint8_t version[3]; + uint8_t data[]; +} nxpTfaDrc2_t; + +/* + * volume step structures + */ +// VP01 +#define NXPTFA_VP1_VERSION '1' +#define NXPTFA_VP1_SUBVERSION "01" +typedef struct nxpTfaVolumeStep1 { + float attenuation; // IEEE single float + uint8_t preset[TFA98XX_PRESET_LENGTH]; +} nxpTfaVolumeStep1_t; + +// VP02 +#define NXPTFA_VP2_VERSION '2' +#define NXPTFA_VP2_SUBVERSION "01" +typedef struct nxpTfaVolumeStep2 { + float attenuation; // IEEE single float + uint8_t preset[TFA98XX_PRESET_LENGTH]; + nxpTfaFilter_t + filter[TFA98XX_MAX_EQ]; // note: API index counts from 1..10 +} nxpTfaVolumeStep2_t; + +/* + * volumestep file + */ +#define NXPTFA_VP_VERSION '1' +#define NXPTFA_VP_SUBVERSION "00" +typedef struct nxpTfaVolumeStepFile { + nxpTfaHeader_t hdr; + uint8_t vsteps; // can also be calulated from size+type + uint8_t samplerate; // ==enum samplerates, assure 8 bits + uint8_t payload; //start of variable length contents:N times volsteps +} nxpTfaVolumeStepFile_t; +/* + * volumestep2 file + */ +typedef struct nxpTfaVolumeStep2File { + nxpTfaHeader_t hdr; + uint8_t vsteps; // can also be calulated from size+type + uint8_t samplerate; // ==enum samplerates, assure 8 bits + nxpTfaVolumeStep2_t + vstep[]; //start of variable length contents:N times volsteps +} nxpTfaVolumeStep2File_t; + +/* + * volumestepMax2 file + */ +typedef struct nxpTfaVolumeStepMax2File { + nxpTfaHeader_t hdr; + uint8_t version[3]; + uint8_t NrOfVsteps; + uint8_t vstepsBin[]; +} nxpTfaVolumeStepMax2File_t; + +/* + * volumestepMax2 file + * This volumestep should ONLY be used for the use of bin2hdr! + * This can only be used to find the messagetype of the vstep (without header) + */ +typedef struct nxpTfaVolumeStepMax2_1File { + uint8_t version[3]; + uint8_t NrOfVsteps; + uint8_t vstepsBin[]; +} nxpTfaVolumeStepMax2_1File_t; + +struct nxpTfaVolumeStepRegisterInfo { + uint8_t NrOfRegisters; + uint16_t registerInfo[]; +}; + +struct nxpTfaVolumeStepMessageInfo { + uint8_t NrOfMessages; + uint8_t MessageType; + uint24_t MessageLength; + uint8_t CmdId[3]; + uint8_t ParameterData[]; +}; +/**************************old v2 *************************************************/ + +/* + * subv 00 volumestep file + */ +typedef struct nxpTfaOldHeader { + uint16_t id; + char version[2]; // "V_" : V=version, vv=subversion + char subversion[2]; // "vv" : vv=subversion + uint16_t size; // data size in bytes following CRC + uint32_t CRC; // 32-bits CRC for following data +} nxpTfaOldHeader_t; + +typedef struct nxpOldTfaFilter { + double bq[5]; + int32_t type; + double frequency; + double Q; + double gain; + uint8_t enabled; +} nxpTfaOldFilter_t; + +typedef struct nxpTfaOldVolumeStep2 { + float attenuation; // IEEE single float + uint8_t preset[TFA98XX_PRESET_LENGTH]; + nxpTfaOldFilter_t eq[10]; +} nxpTfaOldVolumeStep2_t; + +typedef struct nxpTfaOldVolumeStepFile { + nxpTfaOldHeader_t hdr; + nxpTfaOldVolumeStep2_t step[]; +} nxpTfaOldVolumeStep2File_t; +/**************************end old v2 *************************************************/ + +/* + * speaker file header + */ +struct nxpTfaSpkHeader { + struct nxpTfaHeader hdr; + char name[8]; // speaker nick name (e.g. “dumboâ€) + char vendor[16]; + char type[8]; + // dimensions (mm) + uint8_t height; + uint8_t width; + uint8_t depth; + uint16_t ohm; +}; + +/* + * speaker file + */ +#define NXPTFA_SP_VERSION '1' +#define NXPTFA_SP_SUBVERSION "00" +typedef struct nxpTfaSpeakerFile { + nxpTfaHeader_t hdr; + char name[8]; // speaker nick name (e.g. “dumboâ€) + char vendor[16]; + char type[8]; + // dimensions (mm) + uint8_t height; + uint8_t width; + uint8_t depth; + uint8_t ohm_primary; + uint8_t ohm_secondary; + uint8_t data[]; //payload TFA98XX_SPEAKERPARAMETER_LENGTH +} nxpTfaSpeakerFile_t; + +#define NXPTFA_VP3_VERSION '3' +#define NXPTFA_VP3_SUBVERSION "00" + +struct nxpTfaFWVer { + uint8_t Major; + uint8_t minor; + uint8_t minor_update : 6; + uint8_t Update : 2; +}; + +struct nxpTfaFWMsg { + struct nxpTfaFWVer fwVersion; + struct nxpTfaMsg payload; +}; + +typedef struct nxpTfaLiveData { + char name[25]; + char addrs[25]; + int tracker; + int scalefactor; +} nxpTfaLiveData_t; + +#define NXPTFA_SP3_VERSION '3' +#define NXPTFA_SP3_SUBVERSION "00" +struct nxpTfaSpeakerFileMax2 { + nxpTfaHeader_t hdr; + char name[8]; // speaker nick name (e.g. “dumboâ€) + char vendor[16]; + char type[8]; + // dimensions (mm) + uint8_t height; + uint8_t width; + uint8_t depth; + uint8_t ohm_primary; + uint8_t ohm_secondary; + struct nxpTfaFWMsg FWmsg; //payload including FW ver and Cmd ID +}; + +/* + * parameter container file + */ +/* + * descriptors + * Note 1: append new DescriptorType at the end + * Note 2: add new descriptors to dsc_name[] in tfaContUtil.c + */ +typedef enum nxpTfaDescriptorType { + dscDevice, // device list + dscProfile, // profile list + dscRegister, // register patch + dscString, // ascii, zero terminated string + dscFile, // filename + file contents + dscPatch, // patch file + dscMarker, // marker to indicate end of a list + dscMode, + dscSetInputSelect, + dscSetOutputSelect, + dscSetProgramConfig, + dscSetLagW, + dscSetGains, + dscSetvBatFactors, + dscSetSensesCal, + dscSetSensesDelay, + dscBitfield, + dscDefault, // used to reset bitfields to there default values + dscLiveData, + dscLiveDataString, + dscGroup, + dscCmd, + dscSetMBDrc, + dscFilter, + dscNoInit, + dscFeatures, + dscCfMem, // coolflux memory x,y,io + dscSetFwkUseCase, + dscSetVddpConfig, + dsc_last // trailer +} nxpTfaDescriptorType_t; + +#define TFA_BITFIELDDSCMSK 0x7fffffff +typedef struct nxpTfaDescPtr { + uint32_t offset : 24; + uint32_t type : 8; // (== enum nxpTfaDescriptorType, assure 8bits length) +} nxpTfaDescPtr_t; + +/* + * generic file descriptor + */ +typedef struct nxpTfaFileDsc { + nxpTfaDescPtr_t name; + uint32_t size; // file data length in bytes + uint8_t data[]; //payload +} nxpTfaFileDsc_t; + +/* + * device descriptor list + */ +typedef struct nxpTfaDeviceList { + uint8_t length; // nr of items in the list + uint8_t bus; // bus + uint8_t dev; // device + uint8_t func; // subfunction or subdevice + uint32_t devid; // device hw fw id + nxpTfaDescPtr_t name; // device name + nxpTfaDescPtr_t list[]; // items list +} nxpTfaDeviceList_t; + +/* + * profile descriptor list + */ +typedef struct nxpTfaProfileList { + uint32_t length : 8; // nr of items in the list + name + uint32_t group : 8; // profile group number + uint32_t ID : 16; // profile ID + nxpTfaDescPtr_t name; // profile name + nxpTfaDescPtr_t list[]; // items list (lenght-1 items) +} nxpTfaProfileList_t; +#define TFA_PROFID 0x1234 + +/* + * livedata descriptor list + */ +typedef struct nxpTfaLiveDataList { + uint32_t length : 8; // nr of items in the list + uint32_t ID : 24; // profile ID + nxpTfaDescPtr_t name; // livedata name + nxpTfaDescPtr_t list[]; // items list +} nxpTfaLiveDataList_t; +#define TFA_LIVEDATAID 0x5678 + +/* + * Bitfield descriptor + */ +typedef struct nxpTfaBitfield { + uint16_t value; + uint16_t field; // ==datasheet defined, 16 bits +} nxpTfaBitfield_t; + +/* + * Bitfield enumuration bits descriptor + */ +typedef struct nxpTfaBfEnum { + unsigned int len : 4; // this is the actual length-1 + unsigned int pos : 4; + unsigned int address : 8; +} nxpTfaBfEnum_t; + +/* + * Register patch descriptor + */ +typedef struct nxpTfaRegpatch { + uint8_t address; // register address + uint16_t value; // value to write + uint16_t mask; // mask of bits to write +} nxpTfaRegpatch_t; + +/* + * Mode descriptor + */ +typedef struct nxpTfaUseCase { + int value; // mode value, maps to enum Tfa98xx_Mode +} nxpTfaMode_t; + +/* + * NoInit descriptor + */ +typedef struct nxpTfaNoInit { + uint8_t value; // noInit value +} nxpTfaNoInit_t; + +/* + * Features descriptor + */ +typedef struct nxpTfaFeatures { + uint16_t value[3]; // features value +} nxpTfaFeatures_t; + +/* + * the container file + * - the size field is 32bits long (generic=16) + * - all char types are in ASCII + */ +#define NXPTFA_PM_VERSION '1' +#define NXPTFA_PM3_VERSION '3' +#define NXPTFA_PM_SUBVERSION '1' +typedef struct nxpTfaContainer { + char id[2]; // "XX" : XX=type + char version[2]; // "V_" : V=version, vv=subversion + char subversion[2]; // "vv" : vv=subversion + uint32_t size; // data size in bytes following CRC + uint32_t CRC; // 32-bits CRC for following data + uint16_t rev; // "extra chars for rev nr" + char customer[8]; // “name of customer†+ char application[8]; // “application name†+ char type[8]; // “application type name†+ uint16_t ndev; // "nr of device lists" + uint16_t nprof; // "nr of profile lists" + uint16_t nliveData; // "nr of livedata lists" + nxpTfaDescPtr_t index[]; // start of item index table +} nxpTfaContainer_t; + +#pragma pack(pop) + +#endif /* TFA98XXPARAMETERS_H_ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_tfafieldnames.h new file mode 100644 index 000000000000..4684ae4e69ed --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa98xx_tfafieldnames.h @@ -0,0 +1,149 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +typedef struct TfaBfName { + unsigned short bfEnum; + char *bfName; +} tfaBfName_t; + +typedef struct TfaIrqName { + unsigned short irqEnum; + char *irqName; +} tfaIrqName_t; + +#include "tfa1_tfafieldnames.h" +#include "tfa2_tfafieldnames_N1C.h" +/* diffs for specific devices */ +#include "tfa9887_tfafieldnames.h" +#include "tfa9890_tfafieldnames.h" +#include "tfa9891_tfafieldnames.h" +#include "tfa9872_tfafieldnames.h" +#include "tfa9912_tfafieldnames.h" +#include "tfa9896_tfafieldnames.h" +#include "tfa9874_tfafieldnames.h" +#include "tfa9894_tfafieldnames.h" + +/* missing 'common' defs break the build but unused in TFA1 context */ +#define TFA1_BF_AMPINSEL -1 +#define TFA1_BF_MANSCONF -1 +#define TFA1_BF_MANCOLD -1 +#define TFA1_BF_INTSMUTE -1 +#define TFA1_BF_CFSMR -1 +#define TFA1_BF_CFSML -1 +#define TFA1_BF_DCMCCAPI -1 +#define TFA1_BF_DCMCCSB -1 +#define TFA1_BF_USERDEF -1 +#define TFA1_BF_MANSTATE -1 +#define TFA1_BF_MANOPER -1 +#define TFA1_BF_REFCKSEL -1 +#define TFA1_BF_VOLSEC -1 +#define TFA1_BF_FRACTDEL -1 +#define TFA1_BF_ACKDMG -1 +#define TFA1_BF_SSRIGHTE -1 +#define TFA1_BF_SSLEFTE -1 +#define TFA1_BF_R25CL -1 +#define TFA1_BF_R25CR -1 +#define TFA1_BF_SWPROFIL 0x8045 /*!< profile save */ +#define TFA1_BF_SWVSTEP 0x80a5 /*!< vstep save */ + +#define TFA1_BF_TDMNBCK -1 +#define TFA1_BF_TDMSSIZE -1 + +/* missing 'common' defs break the build */ +#define TFA2_BF_CFSM -1 + +/* MTP access uses registers + * defs are derived from corresponding bitfield names as used in the BF macros + */ +#define MTPKEY2 MTPK /* unlock key2 MTPK */ +#define MTP0 MTPOTC /* MTP data */ +#define MTP_CONTROL CIMTP /* copy i2c to mtp */ + +/* interrupt enable register uses HW name in TFA2 */ +#define TFA2_BF_INTENVDDS TFA2_BF_IEVDDS + +/* TFA9891 specific bit field names */ +#define TFA1_BF_SAAMGAIN 0x2202 +#define TFA2_BF_SAAMGAIN -1 + +/* TFA9872 specific bit field names */ +#define TFA2_BF_IELP0 TFA9872_BF_IELP0 +#define TFA2_BF_ISTLP0 TFA9872_BF_ISTLP0 +#define TFA2_BF_IPOLP0 TFA9872_BF_IPOLP0 +#define TFA2_BF_IELP1 TFA9872_BF_IELP1 +#define TFA2_BF_ISTLP1 TFA9872_BF_ISTLP1 +#define TFA2_BF_IPOLP1 TFA9872_BF_IPOLP1 +#define TFA2_BF_LP0 TFA9872_BF_LP0 +#define TFA2_BF_LP1 TFA9872_BF_LP1 +#define TFA2_BF_R25C TFA9872_BF_R25C +#define TFA2_BF_SAMMODE TFA9872_BF_SAMMODE + +/* interrupt bit field names of TFA2 and TFA1 do not match */ +#define TFA1_BF_IEACS TFA1_BF_INTENACS +#define TFA1_BF_IPOACS TFA1_BF_INTPOLACS +#define TFA1_BF_ISTACS TFA1_BF_INTOACS +#define TFA1_BF_ISTVDDS TFA1_BF_INTOVDDS +#define TFA1_BF_ICLVDDS TFA1_BF_INTIVDDS +#define TFA1_BF_IPOVDDS TFA1_BF_INTPOLVDDS +#define TFA1_BF_IENOCLK TFA1_BF_INTENNOCLK +#define TFA1_BF_ISTNOCLK TFA1_BF_INTONOCLK +#define TFA1_BF_IPONOCLK TFA1_BF_INTPOLNOCLK + +/* interrupt bit fields not available on TFA1 */ +#define TFA1_BF_IECLKOOR -1 +#define TFA1_BF_ISTCLKOOR -1 +#define TFA1_BF_IEMWSRC -1 +#define TFA1_BF_ISTMWSRC -1 +#define TFA1_BF_IPOMWSRC -1 +#define TFA1_BF_IEMWSMU -1 +#define TFA1_BF_ISTMWSMU -1 +#define TFA1_BF_IPOMWSMU -1 +#define TFA1_BF_IEMWCFC -1 +#define TFA1_BF_ISTMWCFC -1 +#define TFA1_BF_IPOMWCFC -1 +#define TFA1_BF_CLKOOR -1 +#define TFA1_BF_MANWAIT1 -1 +#define TFA1_BF_MANWAIT2 -1 +#define TFA1_BF_MANMUTE -1 +#define TFA1_BF_IPCLKOOR -1 +#define TFA1_BF_ICLCLKOOR -1 +#define TFA1_BF_IPOSWS -1 +#define TFA1_BF_IESWS -1 +#define TFA1_BF_ISTSWS -1 +#define TFA1_BF_IESPKS -1 +#define TFA1_BF_ISTSPKS -1 +#define TFA1_BF_IPOSPKS -1 +#define TFA1_BF_IECLKS -1 +#define TFA1_BF_ISTCLKS -1 +#define TFA1_BF_IPOCLKS -1 +#define TFA1_BF_IEAMPS -1 +#define TFA1_BF_ISTAMPS -1 +#define TFA1_BF_IPOAMPS -1 +#define TFA1_BF_IELP0 -1 +#define TFA1_BF_ISTLP0 -1 +#define TFA1_BF_IPOLP0 -1 +#define TFA1_BF_IELP1 -1 +#define TFA1_BF_ISTLP1 -1 +#define TFA1_BF_IPOLP1 -1 +#define TFA1_BF_LP0 -1 +#define TFA1_BF_LP1 -1 +#define TFA1_BF_R25C -1 +#define TFA1_BF_SAMMODE -1 + +/* TDM STATUS fields not available on TFA1 */ +#define TFA1_BF_TDMLUTER -1 +#define TFA1_BF_TDMERR -1 diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9912_tfafieldnames.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9912_tfafieldnames.h new file mode 100644 index 000000000000..26ff9cf8d9e5 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa9912_tfafieldnames.h @@ -0,0 +1,3384 @@ +/** Filename: tfa9912_tfafieldnames.h + * This file was generated automatically on 06/14/17 at 18:04:05. + * Source file: TFA9912_N1A_I2C_regmap_V1.41.xlsx + */ + +#ifndef _TFA9912_TFAFIELDNAMES_H +#define _TFA9912_TFAFIELDNAMES_H + +#define TFA9912_I2CVERSION 1.41 + +typedef enum nxpTfa9912BfEnumList { + TFA9912_BF_PWDN = + 0x0000, /*!< Powerdown selection */ + TFA9912_BF_I2CR = + 0x0010, /*!< I2C Reset - Auto clear */ + TFA9912_BF_CFE = + 0x0020, /*!< Enable CoolFlux */ + TFA9912_BF_AMPE = + 0x0030, /*!< Enables the Amplifier */ + TFA9912_BF_DCA = + 0x0040, /*!< Activate DC-to-DC converter */ + TFA9912_BF_SBSL = + 0x0050, /*!< Coolflux configured */ + TFA9912_BF_AMPC = + 0x0060, /*!< CoolFlux controls amplifier */ + TFA9912_BF_INTP = + 0x0071, /*!< Interrupt config */ + TFA9912_BF_FSSSEL = + 0x0090, /*!< Audio sample reference */ + TFA9912_BF_BYPOCP = + 0x00b0, /*!< Bypass OCP */ + TFA9912_BF_TSTOCP = + 0x00c0, /*!< OCP testing control */ + TFA9912_BF_AMPINSEL = + 0x0101, /*!< Amplifier input selection */ + TFA9912_BF_MANSCONF = + 0x0120, /*!< I2C configured */ + TFA9912_BF_MANCOLD = + 0x0130, /*!< Execute cold start */ + TFA9912_BF_MANAOOSC = + 0x0140, /*!< Internal osc off at PWDN */ + TFA9912_BF_MANROBOD = + 0x0150, /*!< Reaction on BOD */ + TFA9912_BF_BODE = + 0x0160, /*!< BOD Enable */ + TFA9912_BF_BODHYS = + 0x0170, /*!< BOD Hysteresis */ + TFA9912_BF_BODFILT = + 0x0181, /*!< BOD filter */ + TFA9912_BF_BODTHLVL = + 0x01a1, /*!< BOD threshold */ + TFA9912_BF_MUTETO = + 0x01d0, /*!< Time out SB mute sequence */ + TFA9912_BF_RCVNS = + 0x01e0, /*!< Noise shaper selection */ + TFA9912_BF_MANWDE = + 0x01f0, /*!< Watchdog enable */ + TFA9912_BF_AUDFS = + 0x0203, /*!< Sample rate (fs) */ + TFA9912_BF_INPLEV = + 0x0240, /*!< TDM output attenuation */ + TFA9912_BF_FRACTDEL = + 0x0255, /*!< V/I Fractional delay */ + TFA9912_BF_BYPHVBF = + 0x02b0, /*!< Bypass HVBAT filter */ + TFA9912_BF_TDMC = + 0x02c0, /*!< TDM Compatibility with TFA9872 */ + TFA9912_BF_ENBLADC10 = + 0x02e0, /*!< ADC10 Enable - I2C direct mode */ + TFA9912_BF_REV = + 0x030f, /*!< Revision info */ + TFA9912_BF_REFCKEXT = + 0x0401, /*!< PLL external ref clock */ + TFA9912_BF_REFCKSEL = + 0x0420, /*!< PLL internal ref clock */ + TFA9912_BF_ENCFCKSEL = + 0x0430, /*!< Coolflux DSP clock scaling, low power mode */ + TFA9912_BF_CFCKSEL = + 0x0441, /*!< Coolflux DSP clock scaler selection for low power mode */ + TFA9912_BF_TDMINFSEL = + 0x0460, /*!< TDM clock selection */ + TFA9912_BF_DISBLAUTOCLKSEL = + 0x0470, /*!< Disable Automatic dsp clock source selection */ + TFA9912_BF_SELCLKSRC = + 0x0480, /*!< I2C selection of DSP clock when auto select is disabled */ + TFA9912_BF_SELTIMSRC = + 0x0490, /*!< I2C selection of Watchdog and Timer clock */ + TFA9912_BF_SSLEFTE = + 0x0500, /*!< */ + TFA9912_BF_SPKSSEN = + 0x0510, /*!< Enable speaker path */ + TFA9912_BF_VSLEFTE = + 0x0520, /*!< */ + TFA9912_BF_VSRIGHTE = + 0x0530, /*!< Voltage sense */ + TFA9912_BF_CSLEFTE = + 0x0540, /*!< */ + TFA9912_BF_CSRIGHTE = + 0x0550, /*!< Current sense */ + TFA9912_BF_SSPDME = + 0x0560, /*!< Sub-system PDM */ + TFA9912_BF_PGALE = + 0x0570, /*!< Enable PGA chop clock for left channel */ + TFA9912_BF_PGARE = + 0x0580, /*!< Enable PGA chop clock */ + TFA9912_BF_SSTDME = + 0x0590, /*!< Sub-system TDM */ + TFA9912_BF_SSPBSTE = + 0x05a0, /*!< Sub-system boost */ + TFA9912_BF_SSADCE = + 0x05b0, /*!< Sub-system ADC */ + TFA9912_BF_SSFAIME = + 0x05c0, /*!< Sub-system FAIM */ + TFA9912_BF_SSCFTIME = + 0x05d0, /*!< CF Sub-system timer */ + TFA9912_BF_SSCFWDTE = + 0x05e0, /*!< CF Sub-system WDT */ + TFA9912_BF_FAIMVBGOVRRL = + 0x05f0, /*!< Over rule of vbg for FaIM access */ + TFA9912_BF_SAMSPKSEL = + 0x0600, /*!< Input selection for TAP/SAM */ + TFA9912_BF_PDM2IISEN = + 0x0610, /*!< PDM2IIS Bridge enable */ + TFA9912_BF_TAPRSTBYPASS = + 0x0620, /*!< Tap decimator reset bypass - Bypass the decimator reset from tapdec */ + TFA9912_BF_CARDECISEL0 = + 0x0631, /*!< Cardec input 0 sel */ + TFA9912_BF_CARDECISEL1 = + 0x0651, /*!< Cardec input sel */ + TFA9912_BF_TAPDECSEL = + 0x0670, /*!< Select TAP/Cardec for TAP */ + TFA9912_BF_COMPCOUNT = + 0x0680, /*!< Comparator o/p filter selection */ + TFA9912_BF_STARTUPMODE = + 0x0691, /*!< Startup Mode Selection */ + TFA9912_BF_AUTOTAP = + 0x06b0, /*!< Enable auto tap switching */ + TFA9912_BF_COMPINITIME = + 0x06c1, /*!< Comparator initialization time to be used in Tap Machine */ + TFA9912_BF_ANAPINITIME = + 0x06e1, /*!< Analog initialization time to be used in Tap Machine */ + TFA9912_BF_CCHKTH = + 0x0707, /*!< Clock check Higher Threshold */ + TFA9912_BF_CCHKTL = + 0x0787, /*!< Clock check Higher Threshold */ + TFA9912_BF_AMPOCRT = + 0x0802, /*!< Amplifier on-off criteria for shutdown */ + TFA9912_BF_AMPTCRR = + 0x0832, /*!< Amplifier on-off criteria for tap mode entry */ + TFA9912_BF_STGS = + 0x0d00, /*!< PDM side tone gain selector */ + TFA9912_BF_STGAIN = + 0x0d18, /*!< Side tone gain */ + TFA9912_BF_STSMUTE = + 0x0da0, /*!< Side tone soft mute */ + TFA9912_BF_ST1C = + 0x0db0, /*!< side tone one s complement */ + TFA9912_BF_CMFBEL = + 0x0e80, /*!< CMFB enable left */ + TFA9912_BF_VDDS = + 0x1000, /*!< POR */ + TFA9912_BF_PLLS = + 0x1010, /*!< PLL lock */ + TFA9912_BF_OTDS = + 0x1020, /*!< OTP alarm */ + TFA9912_BF_OVDS = + 0x1030, /*!< OVP alarm */ + TFA9912_BF_UVDS = + 0x1040, /*!< UVP alarm */ + TFA9912_BF_CLKS = + 0x1050, /*!< Clocks stable */ + TFA9912_BF_MTPB = + 0x1060, /*!< MTP busy */ + TFA9912_BF_NOCLK = + 0x1070, /*!< Lost clock */ + TFA9912_BF_ACS = + 0x1090, /*!< Cold Start */ + TFA9912_BF_SWS = + 0x10a0, /*!< Amplifier engage */ + TFA9912_BF_WDS = + 0x10b0, /*!< Watchdog */ + TFA9912_BF_AMPS = + 0x10c0, /*!< Amplifier enable */ + TFA9912_BF_AREFS = + 0x10d0, /*!< References enable */ + TFA9912_BF_ADCCR = + 0x10e0, /*!< Control ADC */ + TFA9912_BF_BODNOK = + 0x10f0, /*!< BOD */ + TFA9912_BF_DCIL = + 0x1100, /*!< DCDC current limiting */ + TFA9912_BF_DCDCA = + 0x1110, /*!< DCDC active */ + TFA9912_BF_DCOCPOK = + 0x1120, /*!< DCDC OCP nmos */ + TFA9912_BF_DCPEAKCUR = + 0x1130, /*!< Indicates current is max in DC-to-DC converter */ + TFA9912_BF_DCHVBAT = + 0x1140, /*!< DCDC level 1x */ + TFA9912_BF_DCH114 = + 0x1150, /*!< DCDC level 1.14x */ + TFA9912_BF_DCH107 = + 0x1160, /*!< DCDC level 1.07x */ + TFA9912_BF_STMUTEB = + 0x1170, /*!< side tone (un)mute busy */ + TFA9912_BF_STMUTE = + 0x1180, /*!< side tone mute state */ + TFA9912_BF_TDMLUTER = + 0x1190, /*!< TDM LUT error */ + TFA9912_BF_TDMSTAT = + 0x11a2, /*!< TDM status bits */ + TFA9912_BF_TDMERR = + 0x11d0, /*!< TDM error */ + TFA9912_BF_HAPTIC = + 0x11e0, /*!< Status haptic driver */ + TFA9912_BF_OCPOAP = + 0x1300, /*!< OCPOK pmos A */ + TFA9912_BF_OCPOAN = + 0x1310, /*!< OCPOK nmos A */ + TFA9912_BF_OCPOBP = + 0x1320, /*!< OCPOK pmos B */ + TFA9912_BF_OCPOBN = + 0x1330, /*!< OCPOK nmos B */ + TFA9912_BF_CLIPAH = + 0x1340, /*!< Clipping A to Vddp */ + TFA9912_BF_CLIPAL = + 0x1350, /*!< Clipping A to gnd */ + TFA9912_BF_CLIPBH = + 0x1360, /*!< Clipping B to Vddp */ + TFA9912_BF_CLIPBL = + 0x1370, /*!< Clipping B to gnd */ + TFA9912_BF_OCDS = + 0x1380, /*!< OCP amplifier */ + TFA9912_BF_CLIPS = + 0x1390, /*!< Amplifier clipping */ + TFA9912_BF_TCMPTRG = + 0x13a0, /*!< Status Tap comparator triggered */ + TFA9912_BF_TAPDET = + 0x13b0, /*!< Status Tap detected */ + TFA9912_BF_MANWAIT1 = + 0x13c0, /*!< Wait HW I2C settings */ + TFA9912_BF_MANWAIT2 = + 0x13d0, /*!< Wait CF config */ + TFA9912_BF_MANMUTE = + 0x13e0, /*!< Audio mute sequence */ + TFA9912_BF_MANOPER = + 0x13f0, /*!< Operating state */ + TFA9912_BF_SPKSL = + 0x1400, /*!< Left speaker status */ + TFA9912_BF_SPKS = + 0x1410, /*!< Speaker status */ + TFA9912_BF_CLKOOR = + 0x1420, /*!< External clock status */ + TFA9912_BF_MANSTATE = + 0x1433, /*!< Device manager status */ + TFA9912_BF_DCMODE = + 0x1471, /*!< DCDC mode status bits */ + TFA9912_BF_DSPCLKSRC = + 0x1490, /*!< DSP clock source selected by manager */ + TFA9912_BF_STARTUPMODSTAT = + 0x14a1, /*!< Startup Mode Selected by Manager(Read Only) */ + TFA9912_BF_TSPMSTATE = + 0x14c3, /*!< Tap Machine State */ + TFA9912_BF_BATS = + 0x1509, /*!< Battery voltage (V) */ + TFA9912_BF_TEMPS = + 0x1608, /*!< IC Temperature (C) */ + TFA9912_BF_VDDPS = + 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */ + TFA9912_BF_DCILCF = + 0x17a0, /*!< DCDC current limiting for DSP */ + TFA9912_BF_TDMUC = + 0x2000, /*!< Mode setting */ + TFA9912_BF_DIO4SEL = + 0x2011, /*!< DIO4 Input selection */ + TFA9912_BF_TDME = + 0x2040, /*!< Enable TDM interface */ + TFA9912_BF_TDMMODE = + 0x2050, /*!< Slave/master */ + TFA9912_BF_TDMCLINV = + 0x2060, /*!< Reception data to BCK clock */ + TFA9912_BF_TDMFSLN = + 0x2073, /*!< FS length */ + TFA9912_BF_TDMFSPOL = + 0x20b0, /*!< FS polarity */ + TFA9912_BF_TDMNBCK = + 0x20c3, /*!< N-BCK's in FS */ + TFA9912_BF_TDMSLOTS = + 0x2103, /*!< N-slots in Frame */ + TFA9912_BF_TDMSLLN = + 0x2144, /*!< N-bits in slot */ + TFA9912_BF_TDMBRMG = + 0x2194, /*!< N-bits remaining */ + TFA9912_BF_TDMDEL = + 0x21e0, /*!< data delay to FS */ + TFA9912_BF_TDMADJ = + 0x21f0, /*!< data adjustment */ + TFA9912_BF_TDMOOMP = + 0x2201, /*!< Received audio compression */ + TFA9912_BF_TDMSSIZE = + 0x2224, /*!< Sample size per slot */ + TFA9912_BF_TDMTXDFO = + 0x2271, /*!< Format unused bits in a slot */ + TFA9912_BF_TDMTXUS0 = + 0x2291, /*!< Format unused slots GAINIO */ + TFA9912_BF_TDMTXUS1 = + 0x22b1, /*!< Format unused slots DIO1 */ + TFA9912_BF_TDMTXUS2 = + 0x22d1, /*!< Format unused slots DIO2 */ + TFA9912_BF_TDMGIE = + 0x2300, /*!< Control gain (channel in 0) */ + TFA9912_BF_TDMDCE = + 0x2310, /*!< Control audio left (channel in 1 ) */ + TFA9912_BF_TDMSPKE = + 0x2320, /*!< Control audio right (channel in 2 ) */ + TFA9912_BF_TDMCSE = + 0x2330, /*!< Current sense */ + TFA9912_BF_TDMVSE = + 0x2340, /*!< Voltage sense */ + TFA9912_BF_TDMGOE = + 0x2350, /*!< DSP Gainout */ + TFA9912_BF_TDMCF2E = + 0x2360, /*!< DSP 2 */ + TFA9912_BF_TDMCF3E = + 0x2370, /*!< DSP 3 */ + TFA9912_BF_TDMCFE = + 0x2380, /*!< DSP */ + TFA9912_BF_TDMES6 = + 0x2390, /*!< Loopback of Audio left (channel 1) */ + TFA9912_BF_TDMES7 = + 0x23a0, /*!< Loopback of Audio right (channel 2) */ + TFA9912_BF_TDMCF4E = + 0x23b0, /*!< AEC ref right control */ + TFA9912_BF_TDMPD1E = + 0x23c0, /*!< PDM 1 control */ + TFA9912_BF_TDMPD2E = + 0x23d0, /*!< PDM 2 control */ + TFA9912_BF_TDMGIN = + 0x2401, /*!< IO gainin */ + TFA9912_BF_TDMLIO = + 0x2421, /*!< IO audio left */ + TFA9912_BF_TDMRIO = + 0x2441, /*!< IO audio right */ + TFA9912_BF_TDMCSIO = + 0x2461, /*!< IO Current Sense */ + TFA9912_BF_TDMVSIO = + 0x2481, /*!< IO voltage sense */ + TFA9912_BF_TDMGOIO = + 0x24a1, /*!< IO gain out */ + TFA9912_BF_TDMCFIO2 = + 0x24c1, /*!< IO DSP 2 */ + TFA9912_BF_TDMCFIO3 = + 0x24e1, /*!< IO DSP 3 */ + TFA9912_BF_TDMCFIO = + 0x2501, /*!< IO DSP */ + TFA9912_BF_TDMLPB6 = + 0x2521, /*!< IO Source 6 */ + TFA9912_BF_TDMLPB7 = + 0x2541, /*!< IO Source 7 */ + TFA9912_BF_TDMGS = + 0x2603, /*!< Control gainin */ + TFA9912_BF_TDMDCS = + 0x2643, /*!< tdm slot for audio left (channel 1) */ + TFA9912_BF_TDMSPKS = + 0x2683, /*!< tdm slot for audio right (channel 2) */ + TFA9912_BF_TDMCSS = + 0x26c3, /*!< Slot Position of Current Sense Out */ + TFA9912_BF_TDMVSS = + 0x2703, /*!< Slot Position of Voltage sense */ + TFA9912_BF_TDMCGOS = + 0x2743, /*!< Slot Position of GAIN out */ + TFA9912_BF_TDMCF2S = + 0x2783, /*!< Slot Position DSPout2 */ + TFA9912_BF_TDMCF3S = + 0x27c3, /*!< Slot Position DSPout3 */ + TFA9912_BF_TDMCFS = + 0x2803, /*!< Slot Position of DSPout */ + TFA9912_BF_TDMEDAT6S = + 0x2843, /*!< Slot Position of loopback channel left */ + TFA9912_BF_TDMEDAT7S = + 0x2883, /*!< Slot Position of loopback channel right */ + TFA9912_BF_TDMTXUS3 = + 0x2901, /*!< Format unused slots D3 */ + TFA9912_BF_PDMSM = + 0x3100, /*!< PDM control */ + TFA9912_BF_PDMSTSEL = + 0x3110, /*!< PDM Decimator input selection */ + TFA9912_BF_PDMSTENBL = + 0x3120, /*!< Side tone input enable */ + TFA9912_BF_PDMLSEL = + 0x3130, /*!< PDM data selection for left channel during PDM direct mode */ + TFA9912_BF_PDMRSEL = + 0x3140, /*!< PDM data selection for right channel during PDM direct mode */ + TFA9912_BF_MICVDDE = + 0x3150, /*!< Enable MICVDD */ + TFA9912_BF_PDMCLRAT = + 0x3201, /*!< PDM BCK/Fs ratio */ + TFA9912_BF_PDMGAIN = + 0x3223, /*!< PDM gain */ + TFA9912_BF_PDMOSEL = + 0x3263, /*!< PDM output selection - RE/FE data combination */ + TFA9912_BF_SELCFHAPD = + 0x32a0, /*!< Select the source for haptic data output (not for customer) */ + TFA9912_BF_ISTVDDS = + 0x4000, /*!< Status POR */ + TFA9912_BF_ISTPLLS = + 0x4010, /*!< Status PLL lock */ + TFA9912_BF_ISTOTDS = + 0x4020, /*!< Status OTP alarm */ + TFA9912_BF_ISTOVDS = + 0x4030, /*!< Status OVP alarm */ + TFA9912_BF_ISTUVDS = + 0x4040, /*!< Status UVP alarm */ + TFA9912_BF_ISTCLKS = + 0x4050, /*!< Status clocks stable */ + TFA9912_BF_ISTMTPB = + 0x4060, /*!< Status MTP busy */ + TFA9912_BF_ISTNOCLK = + 0x4070, /*!< Status lost clock */ + TFA9912_BF_ISTSPKS = + 0x4080, /*!< Status speaker error */ + TFA9912_BF_ISTACS = + 0x4090, /*!< Status cold start */ + TFA9912_BF_ISTSWS = + 0x40a0, /*!< Status amplifier engage */ + TFA9912_BF_ISTWDS = + 0x40b0, /*!< Status watchdog */ + TFA9912_BF_ISTAMPS = + 0x40c0, /*!< Status amplifier enable */ + TFA9912_BF_ISTAREFS = + 0x40d0, /*!< Status Ref enable */ + TFA9912_BF_ISTADCCR = + 0x40e0, /*!< Status Control ADC */ + TFA9912_BF_ISTBODNOK = + 0x40f0, /*!< Status BOD */ + TFA9912_BF_ISTBSTCU = + 0x4100, /*!< Status DCDC current limiting */ + TFA9912_BF_ISTBSTHI = + 0x4110, /*!< Status DCDC active */ + TFA9912_BF_ISTBSTOC = + 0x4120, /*!< Status DCDC OCP */ + TFA9912_BF_ISTBSTPKCUR = + 0x4130, /*!< Status bst peakcur */ + TFA9912_BF_ISTBSTVC = + 0x4140, /*!< Status DCDC level 1x */ + TFA9912_BF_ISTBST86 = + 0x4150, /*!< Status DCDC level 1.14x */ + TFA9912_BF_ISTBST93 = + 0x4160, /*!< Status DCDC level 1.07x */ + TFA9912_BF_ISTRCVLD = + 0x4170, /*!< Status rcvldop ready */ + TFA9912_BF_ISTOCPL = + 0x4180, /*!< Status ocp alarm left */ + TFA9912_BF_ISTOCPR = + 0x4190, /*!< Status ocp alarm */ + TFA9912_BF_ISTMWSRC = + 0x41a0, /*!< Status Waits HW I2C settings */ + TFA9912_BF_ISTMWCFC = + 0x41b0, /*!< Status waits CF config */ + TFA9912_BF_ISTMWSMU = + 0x41c0, /*!< Status Audio mute sequence */ + TFA9912_BF_ISTCFMER = + 0x41d0, /*!< Status cfma error */ + TFA9912_BF_ISTCFMAC = + 0x41e0, /*!< Status cfma ack */ + TFA9912_BF_ISTCLKOOR = + 0x41f0, /*!< Status flag_clk_out_of_range */ + TFA9912_BF_ISTTDMER = + 0x4200, /*!< Status tdm error */ + TFA9912_BF_ISTCLPL = + 0x4210, /*!< Status clip left */ + TFA9912_BF_ISTCLPR = + 0x4220, /*!< Status clip */ + TFA9912_BF_ISTOCPM = + 0x4230, /*!< Status mic ocpok */ + TFA9912_BF_ISTLP1 = + 0x4250, /*!< Status low power mode1 */ + TFA9912_BF_ISTLA = + 0x4260, /*!< Status low amplitude detection */ + TFA9912_BF_ISTVDDP = + 0x4270, /*!< Status VDDP greater than VBAT */ + TFA9912_BF_ISTTAPDET = + 0x4280, /*!< Status Tap detected */ + TFA9912_BF_ISTAUDMOD = + 0x4290, /*!< Status Audio Mode activated */ + TFA9912_BF_ISTSAMMOD = + 0x42a0, /*!< Status SAM Mode activated */ + TFA9912_BF_ISTTAPMOD = + 0x42b0, /*!< Status Tap Mode Activated */ + TFA9912_BF_ISTTAPTRG = + 0x42c0, /*!< Status Tap comparator triggered */ + TFA9912_BF_ICLVDDS = + 0x4400, /*!< Clear POR */ + TFA9912_BF_ICLPLLS = + 0x4410, /*!< Clear PLL lock */ + TFA9912_BF_ICLOTDS = + 0x4420, /*!< Clear OTP alarm */ + TFA9912_BF_ICLOVDS = + 0x4430, /*!< Clear OVP alarm */ + TFA9912_BF_ICLUVDS = + 0x4440, /*!< Clear UVP alarm */ + TFA9912_BF_ICLCLKS = + 0x4450, /*!< Clear clocks stable */ + TFA9912_BF_ICLMTPB = + 0x4460, /*!< Clear mtp busy */ + TFA9912_BF_ICLNOCLK = + 0x4470, /*!< Clear lost clk */ + TFA9912_BF_ICLSPKS = + 0x4480, /*!< Clear speaker error */ + TFA9912_BF_ICLACS = + 0x4490, /*!< Clear cold started */ + TFA9912_BF_ICLSWS = + 0x44a0, /*!< Clear amplifier engage */ + TFA9912_BF_ICLWDS = + 0x44b0, /*!< Clear watchdog */ + TFA9912_BF_ICLAMPS = + 0x44c0, /*!< Clear enbl amp */ + TFA9912_BF_ICLAREFS = + 0x44d0, /*!< Clear ref enable */ + TFA9912_BF_ICLADCCR = + 0x44e0, /*!< Clear control ADC */ + TFA9912_BF_ICLBODNOK = + 0x44f0, /*!< Clear BOD */ + TFA9912_BF_ICLBSTCU = + 0x4500, /*!< Clear DCDC current limiting */ + TFA9912_BF_ICLBSTHI = + 0x4510, /*!< Clear DCDC active */ + TFA9912_BF_ICLBSTOC = + 0x4520, /*!< Clear DCDC OCP */ + TFA9912_BF_ICLBSTPC = + 0x4530, /*!< Clear bst peakcur */ + TFA9912_BF_ICLBSTVC = + 0x4540, /*!< Clear DCDC level 1x */ + TFA9912_BF_ICLBST86 = + 0x4550, /*!< Clear DCDC level 1.14x */ + TFA9912_BF_ICLBST93 = + 0x4560, /*!< Clear DCDC level 1.07x */ + TFA9912_BF_ICLRCVLD = + 0x4570, /*!< Clear rcvldop ready */ + TFA9912_BF_ICLOCPL = + 0x4580, /*!< Clear ocp alarm left */ + TFA9912_BF_ICLOCPR = + 0x4590, /*!< Clear ocp alarm */ + TFA9912_BF_ICLMWSRC = + 0x45a0, /*!< Clear wait HW I2C settings */ + TFA9912_BF_ICLMWCFC = + 0x45b0, /*!< Clear wait cf config */ + TFA9912_BF_ICLMWSMU = + 0x45c0, /*!< Clear audio mute sequence */ + TFA9912_BF_ICLCFMER = + 0x45d0, /*!< Clear cfma err */ + TFA9912_BF_ICLCFMAC = + 0x45e0, /*!< Clear cfma ack */ + TFA9912_BF_ICLCLKOOR = + 0x45f0, /*!< Clear flag_clk_out_of_range */ + TFA9912_BF_ICLTDMER = + 0x4600, /*!< Clear tdm error */ + TFA9912_BF_ICLCLPL = + 0x4610, /*!< Clear clip left */ + TFA9912_BF_ICLCLP = + 0x4620, /*!< Clear clip */ + TFA9912_BF_ICLOCPM = + 0x4630, /*!< Clear mic ocpok */ + TFA9912_BF_ICLLP1 = + 0x4650, /*!< Clear low power mode1 */ + TFA9912_BF_ICLLA = + 0x4660, /*!< Clear low amplitude detection */ + TFA9912_BF_ICLVDDP = + 0x4670, /*!< Clear VDDP greater then VBAT */ + TFA9912_BF_ICLTAPDET = + 0x4680, /*!< Clear Tap detected */ + TFA9912_BF_ICLAUDMOD = + 0x4690, /*!< Clear Audio Mode activated */ + TFA9912_BF_ICLSAMMOD = + 0x46a0, /*!< Clear SAM Mode activated */ + TFA9912_BF_ICLTAPMOD = + 0x46b0, /*!< Clear Tap Mode Activated */ + TFA9912_BF_ICLTAPTRG = + 0x46c0, /*!< Clear Comparator Interrupt */ + TFA9912_BF_IEVDDS = + 0x4800, /*!< Enable por */ + TFA9912_BF_IEPLLS = + 0x4810, /*!< Enable pll lock */ + TFA9912_BF_IEOTDS = + 0x4820, /*!< Enable OTP alarm */ + TFA9912_BF_IEOVDS = + 0x4830, /*!< Enable OVP alarm */ + TFA9912_BF_IEUVDS = + 0x4840, /*!< Enable UVP alarm */ + TFA9912_BF_IECLKS = + 0x4850, /*!< Enable clocks stable */ + TFA9912_BF_IEMTPB = + 0x4860, /*!< Enable mtp busy */ + TFA9912_BF_IENOCLK = + 0x4870, /*!< Enable lost clk */ + TFA9912_BF_IESPKS = + 0x4880, /*!< Enable speaker error */ + TFA9912_BF_IEACS = + 0x4890, /*!< Enable cold started */ + TFA9912_BF_IESWS = + 0x48a0, /*!< Enable amplifier engage */ + TFA9912_BF_IEWDS = + 0x48b0, /*!< Enable watchdog */ + TFA9912_BF_IEAMPS = + 0x48c0, /*!< Enable enbl amp */ + TFA9912_BF_IEAREFS = + 0x48d0, /*!< Enable ref enable */ + TFA9912_BF_IEADCCR = + 0x48e0, /*!< Enable Control ADC */ + TFA9912_BF_IEBODNOK = + 0x48f0, /*!< Enable BOD */ + TFA9912_BF_IEBSTCU = + 0x4900, /*!< Enable DCDC current limiting */ + TFA9912_BF_IEBSTHI = + 0x4910, /*!< Enable DCDC active */ + TFA9912_BF_IEBSTOC = + 0x4920, /*!< Enable DCDC OCP */ + TFA9912_BF_IEBSTPC = + 0x4930, /*!< Enable bst peakcur */ + TFA9912_BF_IEBSTVC = + 0x4940, /*!< Enable DCDC level 1x */ + TFA9912_BF_IEBST86 = + 0x4950, /*!< Enable DCDC level 1.14x */ + TFA9912_BF_IEBST93 = + 0x4960, /*!< Enable DCDC level 1.07x */ + TFA9912_BF_IERCVLD = + 0x4970, /*!< Enable rcvldop ready */ + TFA9912_BF_IEOCPL = + 0x4980, /*!< Enable ocp alarm left */ + TFA9912_BF_IEOCPR = + 0x4990, /*!< Enable ocp alarm */ + TFA9912_BF_IEMWSRC = + 0x49a0, /*!< Enable waits HW I2C settings */ + TFA9912_BF_IEMWCFC = + 0x49b0, /*!< Enable man wait cf config */ + TFA9912_BF_IEMWSMU = + 0x49c0, /*!< Enable man Audio mute sequence */ + TFA9912_BF_IECFMER = + 0x49d0, /*!< Enable cfma err */ + TFA9912_BF_IECFMAC = + 0x49e0, /*!< Enable cfma ack */ + TFA9912_BF_IECLKOOR = + 0x49f0, /*!< Enable flag_clk_out_of_range */ + TFA9912_BF_IETDMER = + 0x4a00, /*!< Enable tdm error */ + TFA9912_BF_IECLPL = + 0x4a10, /*!< Enable clip left */ + TFA9912_BF_IECLPR = + 0x4a20, /*!< Enable clip */ + TFA9912_BF_IEOCPM1 = + 0x4a30, /*!< Enable mic ocpok */ + TFA9912_BF_IELP1 = + 0x4a50, /*!< Enable low power mode1 */ + TFA9912_BF_IELA = + 0x4a60, /*!< Enable low amplitude detection */ + TFA9912_BF_IEVDDP = + 0x4a70, /*!< Enable VDDP greater than VBAT */ + TFA9912_BF_IETAPDET = + 0x4a80, /*!< Enable Tap detected */ + TFA9912_BF_IEAUDMOD = + 0x4a90, /*!< Enable Audio Mode activated */ + TFA9912_BF_IESAMMOD = + 0x4aa0, /*!< Enable SAM Mode activated */ + TFA9912_BF_IETAPMOD = + 0x4ab0, /*!< Enable Tap Mode Activated */ + TFA9912_BF_IETAPTRG = + 0x4ac0, /*!< Enable comparator interrupt */ + TFA9912_BF_IPOVDDS = + 0x4c00, /*!< Polarity por */ + TFA9912_BF_IPOPLLS = + 0x4c10, /*!< Polarity pll lock */ + TFA9912_BF_IPOOTDS = + 0x4c20, /*!< Polarity OTP alarm */ + TFA9912_BF_IPOOVDS = + 0x4c30, /*!< Polarity OVP alarm */ + TFA9912_BF_IPOUVDS = + 0x4c40, /*!< Polarity UVP alarm */ + TFA9912_BF_IPOCLKS = + 0x4c50, /*!< Polarity clocks stable */ + TFA9912_BF_IPOMTPB = + 0x4c60, /*!< Polarity mtp busy */ + TFA9912_BF_IPONOCLK = + 0x4c70, /*!< Polarity lost clk */ + TFA9912_BF_IPOSPKS = + 0x4c80, /*!< Polarity speaker error */ + TFA9912_BF_IPOACS = + 0x4c90, /*!< Polarity cold started */ + TFA9912_BF_IPOSWS = + 0x4ca0, /*!< Polarity amplifier engage */ + TFA9912_BF_IPOWDS = + 0x4cb0, /*!< Polarity watchdog */ + TFA9912_BF_IPOAMPS = + 0x4cc0, /*!< Polarity enbl amp */ + TFA9912_BF_IPOAREFS = + 0x4cd0, /*!< Polarity ref enable */ + TFA9912_BF_IPOADCCR = + 0x4ce0, /*!< Polarity Control ADC */ + TFA9912_BF_IPOBODNOK = + 0x4cf0, /*!< Polarity BOD */ + TFA9912_BF_IPOBSTCU = + 0x4d00, /*!< Polarity DCDC current limiting */ + TFA9912_BF_IPOBSTHI = + 0x4d10, /*!< Polarity DCDC active */ + TFA9912_BF_IPOBSTOC = + 0x4d20, /*!< Polarity DCDC OCP */ + TFA9912_BF_IPOBSTPC = + 0x4d30, /*!< Polarity bst peakcur */ + TFA9912_BF_IPOBSTVC = + 0x4d40, /*!< Polarity DCDC level 1x */ + TFA9912_BF_IPOBST86 = + 0x4d50, /*!< Polarity DCDC level 1.14x */ + TFA9912_BF_IPOBST93 = + 0x4d60, /*!< Polarity DCDC level 1.07x */ + TFA9912_BF_IPORCVLD = + 0x4d70, /*!< Polarity rcvldop ready */ + TFA9912_BF_IPOOCPL = + 0x4d80, /*!< Polarity ocp alarm left */ + TFA9912_BF_IPOOCPR = + 0x4d90, /*!< Polarity ocp alarm */ + TFA9912_BF_IPOMWSRC = + 0x4da0, /*!< Polarity waits HW I2C settings */ + TFA9912_BF_IPOMWCFC = + 0x4db0, /*!< Polarity man wait cf config */ + TFA9912_BF_IPOMWSMU = + 0x4dc0, /*!< Polarity man audio mute sequence */ + TFA9912_BF_IPOCFMER = + 0x4dd0, /*!< Polarity cfma err */ + TFA9912_BF_IPOCFMAC = + 0x4de0, /*!< Polarity cfma ack */ + TFA9912_BF_IPOCLKOOR = + 0x4df0, /*!< Polarity flag_clk_out_of_range */ + TFA9912_BF_IPOTDMER = + 0x4e00, /*!< Polarity tdm error */ + TFA9912_BF_IPOCLPL = + 0x4e10, /*!< Polarity clip left */ + TFA9912_BF_IPOCLPR = + 0x4e20, /*!< Polarity clip */ + TFA9912_BF_IPOOCPM = + 0x4e30, /*!< Polarity mic ocpok */ + TFA9912_BF_IPOLP1 = + 0x4e50, /*!< Polarity low power mode1 */ + TFA9912_BF_IPOLA = + 0x4e60, /*!< Polarity low amplitude detection */ + TFA9912_BF_IPOVDDP = + 0x4e70, /*!< Polarity VDDP greater than VBAT */ + TFA9912_BF_IPOLTAPDET = + 0x4e80, /*!< PolarityTap detected */ + TFA9912_BF_IPOLAUDMOD = + 0x4e90, /*!< PolarityAudio Mode activated */ + TFA9912_BF_IPOLSAMMOD = + 0x4ea0, /*!< PolaritySAM Mode activated */ + TFA9912_BF_IPOLTAPMOD = + 0x4eb0, /*!< Polarity Tap Mode Activated */ + TFA9912_BF_IPOLTAPTRG = + 0x4ec0, /*!< PolarityTap Comparator Trigger */ + TFA9912_BF_BSSCR = + 0x5001, /*!< Battery Safeguard attack time */ + TFA9912_BF_BSST = + 0x5023, /*!< Battery Safeguard threshold voltage level */ + TFA9912_BF_BSSRL = + 0x5061, /*!< Battery Safeguard maximum reduction */ + TFA9912_BF_BSSRR = + 0x5082, /*!< Battery Safeguard release time */ + TFA9912_BF_BSSHY = + 0x50b1, /*!< Battery Safeguard hysteresis */ + TFA9912_BF_BSSAC = + 0x50d0, /*!< Reset clipper - Auto clear */ + TFA9912_BF_BSSR = + 0x50e0, /*!< Battery voltage read out */ + TFA9912_BF_BSSBY = + 0x50f0, /*!< Bypass HW clipper */ + TFA9912_BF_BSSS = + 0x5100, /*!< Vbat prot steepness */ + TFA9912_BF_INTSMUTE = + 0x5110, /*!< Soft mute HW */ + TFA9912_BF_CFSML = + 0x5120, /*!< Soft mute FW left */ + TFA9912_BF_CFSM = + 0x5130, /*!< Soft mute FW */ + TFA9912_BF_HPFBYPL = + 0x5140, /*!< Bypass HPF left */ + TFA9912_BF_HPFBYP = + 0x5150, /*!< Bypass HPF */ + TFA9912_BF_DPSAL = + 0x5160, /*!< Enable DPSA left */ + TFA9912_BF_DPSA = + 0x5170, /*!< Enable DPSA */ + TFA9912_BF_VOL = + 0x5187, /*!< FW volume control for primary audio channel */ + TFA9912_BF_HNDSFRCV = + 0x5200, /*!< Selection receiver */ + TFA9912_BF_CLIPCTRL = + 0x5222, /*!< Clip control setting */ + TFA9912_BF_AMPGAIN = + 0x5257, /*!< Amplifier gain */ + TFA9912_BF_SLOPEE = + 0x52d0, /*!< Enables slope control */ + TFA9912_BF_SLOPESET = + 0x52e0, /*!< Slope speed setting (bin. coded) */ + TFA9912_BF_CFTAPPAT = + 0x5c07, /*!< Coolflux tap pattern */ + TFA9912_BF_TAPDBGINFO = + 0x5c83, /*!< Reserved */ + TFA9912_BF_TATPSTAT1 = + 0x5d0f, /*!< Tap Status 1 from CF FW */ + TFA9912_BF_TCOMPTHR = + 0x5f03, /*!< Comparator threshold (in uV) */ + TFA9912_BF_PGAGAIN = + 0x6081, /*!< PGA gain selection */ + TFA9912_BF_TDMSPKG = + 0x6123, /*!< System gain (INPLEV 0) */ + TFA9912_BF_LPM1LVL = + 0x6505, /*!< low power mode1 detector ctrl threshold for low_audio_lvl */ + TFA9912_BF_LPM1HLD = + 0x6565, /*!< Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio */ + TFA9912_BF_LPM1DIS = + 0x65c0, /*!< low power mode1 detector control */ + TFA9912_BF_DCDIS = + 0x6630, /*!< DCDC */ + TFA9912_BF_TDMSRCMAP = + 0x6801, /*!< tdm source mapping */ + TFA9912_BF_TDMSRCAS = + 0x6821, /*!< frame a selection */ + TFA9912_BF_TDMSRCBS = + 0x6841, /*!< frame b selection */ + TFA9912_BF_ANC1C = + 0x68a0, /*!< ANC one s complement */ + TFA9912_BF_SAMMODE = + 0x6901, /*!< Sam mode */ + TFA9912_BF_DCMCC = + 0x7033, /*!< Max coil current */ + TFA9912_BF_DCCV = + 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */ + TFA9912_BF_DCIE = + 0x7090, /*!< Adaptive boost mode */ + TFA9912_BF_DCSR = + 0x70a0, /*!< Soft ramp up/down */ + TFA9912_BF_DCINSEL = + 0x70c1, /*!< DCDC IIR input Selection */ + TFA9912_BF_DCPWM = + 0x70f0, /*!< DCDC PWM only mode */ + TFA9912_BF_DCTRIP = + 0x7504, /*!< Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1 */ + TFA9912_BF_DCTRIP2 = + 0x7554, /*!< Adaptive boost trip level 2, effective only when boost_intelligent is set to 1 */ + TFA9912_BF_DCTRIPT = + 0x75a4, /*!< Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */ + TFA9912_BF_DCVOF = + 0x7635, /*!< First boost voltage level */ + TFA9912_BF_DCVOS = + 0x7695, /*!< Second boost voltage level */ + TFA9912_BF_RST = + 0x9000, /*!< Reset */ + TFA9912_BF_DMEM = + 0x9011, /*!< Target memory */ + TFA9912_BF_AIF = + 0x9030, /*!< Auto increment */ + TFA9912_BF_CFINT = + 0x9040, /*!< Interrupt - auto clear */ + TFA9912_BF_CFCGATE = + 0x9050, /*!< Coolflux clock gating disabling control */ + TFA9912_BF_REQCMD = + 0x9080, /*!< Firmware event request rpc command */ + TFA9912_BF_REQRST = + 0x9090, /*!< Firmware event request reset restart */ + TFA9912_BF_REQMIPS = + 0x90a0, /*!< Firmware event request short on mips */ + TFA9912_BF_REQMUTED = + 0x90b0, /*!< Firmware event request mute sequence ready */ + TFA9912_BF_REQVOL = + 0x90c0, /*!< Firmware event request volume ready */ + TFA9912_BF_REQDMG = + 0x90d0, /*!< Firmware event request speaker damage detected */ + TFA9912_BF_REQCAL = + 0x90e0, /*!< Firmware event request calibration completed */ + TFA9912_BF_REQRSV = + 0x90f0, /*!< Firmware event request reserved */ + TFA9912_BF_MADD = + 0x910f, /*!< Memory address */ + TFA9912_BF_MEMA = + 0x920f, /*!< Activate memory access */ + TFA9912_BF_ERR = + 0x9307, /*!< Error flags */ + TFA9912_BF_ACKCMD = + 0x9380, /*!< Firmware event acknowledge rpc command */ + TFA9912_BF_ACKRST = + 0x9390, /*!< Firmware event acknowledge reset restart */ + TFA9912_BF_ACKMIPS = + 0x93a0, /*!< Firmware event acknowledge short on mips */ + TFA9912_BF_ACKMUTED = + 0x93b0, /*!< Firmware event acknowledge mute sequence ready */ + TFA9912_BF_ACKVOL = + 0x93c0, /*!< Firmware event acknowledge volume ready */ + TFA9912_BF_ACKDMG = + 0x93d0, /*!< Firmware event acknowledge speaker damage detected */ + TFA9912_BF_ACKCAL = + 0x93e0, /*!< Firmware event acknowledge calibration completed */ + TFA9912_BF_ACKRSV = + 0x93f0, /*!< Firmware event acknowledge reserved */ + TFA9912_BF_MTPK = + 0xa107, /*!< MTP KEY2 register */ + TFA9912_BF_KEY1LOCKED = + 0xa200, /*!< Indicates KEY1 is locked */ + TFA9912_BF_KEY2LOCKED = + 0xa210, /*!< Indicates KEY2 is locked */ + TFA9912_BF_CIMTP = + 0xa360, /*!< Start copying data from I2C mtp registers to mtp */ + TFA9912_BF_MTPRDMSB = + 0xa50f, /*!< MSB word of MTP manual read data */ + TFA9912_BF_MTPRDLSB = + 0xa60f, /*!< LSB word of MTP manual read data */ + TFA9912_BF_EXTTS = + 0xb108, /*!< External temperature (C) */ + TFA9912_BF_TROS = + 0xb190, /*!< Select temp Speaker calibration */ + TFA9912_BF_SWPROFIL = + 0xee0f, /*!< Software profile data */ + TFA9912_BF_SWVSTEP = + 0xef0f, /*!< Software vstep information */ + TFA9912_BF_MTPOTC = + 0xf000, /*!< Calibration schedule */ + TFA9912_BF_MTPEX = + 0xf010, /*!< Calibration Ron executed */ + TFA9912_BF_DCMCCAPI = + 0xf020, /*!< Calibration current limit DCDC */ + TFA9912_BF_DCMCCSB = + 0xf030, /*!< Sign bit for delta calibration current limit DCDC */ + TFA9912_BF_DCMCCCL = + 0xf042, /*!< Calibration delta current limit DCDC */ + TFA9912_BF_USERDEF = + 0xf078, /*!< Reserved space for allowing customer to store speaker information */ + TFA9912_BF_R25C = + 0xf40f, /*!< Ron resistance of speaker coil */ +} nxpTfa9912BfEnumList_t; +#define TFA9912_NAMETABLE \ + static tfaBfName_t Tfa9912DatasheetNames[] = { \ + { 0x0, \ + "PWDN" }, /* Powerdown selection , */ \ + { 0x10, \ + "I2CR" }, /* I2C Reset - Auto clear , */ \ + { 0x20, \ + "CFE" }, /* Enable CoolFlux , */ \ + { 0x30, \ + "AMPE" }, /* Enables the Amplifier , */ \ + { 0x40, \ + "DCA" }, /* Activate DC-to-DC converter , */ \ + { 0x50, \ + "SBSL" }, /* Coolflux configured , */ \ + { 0x60, \ + "AMPC" }, /* CoolFlux controls amplifier , */ \ + { 0x71, \ + "INTP" }, /* Interrupt config , */ \ + { 0x90, \ + "FSSSEL" }, /* Audio sample reference , */ \ + { 0xb0, \ + "BYPOCP" }, /* Bypass OCP , */ \ + { 0xc0, \ + "TSTOCP" }, /* OCP testing control , */ \ + { 0x101, \ + "AMPINSEL" }, /* Amplifier input selection , */ \ + { 0x120, \ + "MANSCONF" }, /* I2C configured , */ \ + { 0x130, \ + "MANCOLD" }, /* Execute cold start , */ \ + { 0x140, \ + "MANAOOSC" }, /* Internal osc off at PWDN , */ \ + { 0x150, \ + "MANROBOD" }, /* Reaction on BOD , */ \ + { 0x160, \ + "BODE" }, /* BOD Enable , */ \ + { 0x170, \ + "BODHYS" }, /* BOD Hysteresis , */ \ + { 0x181, \ + "BODFILT" }, /* BOD filter , */ \ + { 0x1a1, \ + "BODTHLVL" }, /* BOD threshold , */ \ + { 0x1d0, \ + "MUTETO" }, /* Time out SB mute sequence , */ \ + { 0x1e0, \ + "RCVNS" }, /* Noise shaper selection , */ \ + { 0x1f0, \ + "MANWDE" }, /* Watchdog enable , */ \ + { 0x203, \ + "AUDFS" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "INPLEV" }, /* TDM output attenuation , */ \ + { 0x255, \ + "FRACTDEL" }, /* V/I Fractional delay , */ \ + { 0x2b0, \ + "BYPHVBF" }, /* Bypass HVBAT filter , */ \ + { 0x2c0, \ + "TDMC" }, /* TDM Compatibility with TFA9872 , */ \ + { 0x2e0, \ + "ENBLADC10" }, /* ADC10 Enable - I2C direct mode , */ \ + { 0x30f, \ + "REV" }, /* Revision info , */ \ + { 0x401, \ + "REFCKEXT" }, /* PLL external ref clock , */ \ + { 0x420, \ + "REFCKSEL" }, /* PLL internal ref clock , */ \ + { 0x430, \ + "ENCFCKSEL" }, /* Coolflux DSP clock scaling, low power mode , */ \ + { 0x441, \ + "CFCKSEL" }, /* Coolflux DSP clock scaler selection for low power mode, */ \ + { 0x460, \ + "TDMINFSEL" }, /* TDM clock selection , */ \ + { 0x470, \ + "DISBLAUTOCLKSEL" }, /* Disable Automatic dsp clock source selection , */ \ + { 0x480, \ + "SELCLKSRC" }, /* I2C selection of DSP clock when auto select is disabled, */ \ + { 0x490, \ + "SELTIMSRC" }, /* I2C selection of Watchdog and Timer clock , */ \ + { 0x500, \ + "SSLEFTE" }, /* , */ \ + { 0x510, \ + "SPKSSEN" }, /* Enable speaker path , */ \ + { 0x520, \ + "VSLEFTE" }, /* , */ \ + { 0x530, \ + "VSRIGHTE" }, /* Voltage sense , */ \ + { 0x540, \ + "CSLEFTE" }, /* , */ \ + { 0x550, \ + "CSRIGHTE" }, /* Current sense , */ \ + { 0x560, \ + "SSPDME" }, /* Sub-system PDM , */ \ + { 0x570, \ + "PGALE" }, /* Enable PGA chop clock for left channel , */ \ + { 0x580, \ + "PGARE" }, /* Enable PGA chop clock , */ \ + { 0x590, \ + "SSTDME" }, /* Sub-system TDM , */ \ + { 0x5a0, \ + "SSPBSTE" }, /* Sub-system boost , */ \ + { 0x5b0, \ + "SSADCE" }, /* Sub-system ADC , */ \ + { 0x5c0, \ + "SSFAIME" }, /* Sub-system FAIM , */ \ + { 0x5d0, \ + "SSCFTIME" }, /* CF Sub-system timer , */ \ + { 0x5e0, \ + "SSCFWDTE" }, /* CF Sub-system WDT , */ \ + { 0x5f0, \ + "FAIMVBGOVRRL" }, /* Over rule of vbg for FaIM access , */ \ + { 0x600, \ + "SAMSPKSEL" }, /* Input selection for TAP/SAM , */ \ + { 0x610, \ + "PDM2IISEN" }, /* PDM2IIS Bridge enable , */ \ + { 0x620, \ + "TAPRSTBYPASS" }, /* Tap decimator reset bypass - Bypass the decimator reset from tapdec, */ \ + { 0x631, \ + "CARDECISEL0" }, /* Cardec input 0 sel , */ \ + { 0x651, \ + "CARDECISEL1" }, /* Cardec input sel , */ \ + { 0x670, \ + "TAPDECSEL" }, /* Select TAP/Cardec for TAP , */ \ + { 0x680, \ + "COMPCOUNT" }, /* Comparator o/p filter selection , */ \ + { 0x691, \ + "STARTUPMODE" }, /* Startup Mode Selection , */ \ + { 0x6b0, \ + "AUTOTAP" }, /* Enable auto tap switching , */ \ + { 0x6c1, \ + "COMPINITIME" }, /* Comparator initialization time to be used in Tap Machine, */ \ + { 0x6e1, \ + "ANAPINITIME" }, /* Analog initialization time to be used in Tap Machine, */ \ + { 0x707, \ + "CCHKTH" }, /* Clock check Higher Threshold , */ \ + { 0x787, \ + "CCHKTL" }, /* Clock check Higher Threshold , */ \ + { 0x802, \ + "AMPOCRT" }, /* Amplifier on-off criteria for shutdown , */ \ + { 0x832, \ + "AMPTCRR" }, /* Amplifier on-off criteria for tap mode entry , */ \ + { 0xd00, \ + "STGS" }, /* PDM side tone gain selector , */ \ + { 0xd18, \ + "STGAIN" }, /* Side tone gain , */ \ + { 0xda0, \ + "STSMUTE" }, /* Side tone soft mute , */ \ + { 0xdb0, \ + "ST1C" }, /* side tone one s complement , */ \ + { 0xe80, \ + "CMFBEL" }, /* CMFB enable left , */ \ + { 0x1000, \ + "VDDS" }, /* POR , */ \ + { 0x1010, \ + "PLLS" }, /* PLL lock , */ \ + { 0x1020, \ + "OTDS" }, /* OTP alarm , */ \ + { 0x1030, \ + "OVDS" }, /* OVP alarm , */ \ + { 0x1040, \ + "UVDS" }, /* UVP alarm , */ \ + { 0x1050, \ + "CLKS" }, /* Clocks stable , */ \ + { 0x1060, \ + "MTPB" }, /* MTP busy , */ \ + { 0x1070, \ + "NOCLK" }, /* Lost clock , */ \ + { 0x1090, \ + "ACS" }, /* Cold Start , */ \ + { 0x10a0, \ + "SWS" }, /* Amplifier engage , */ \ + { 0x10b0, \ + "WDS" }, /* Watchdog , */ \ + { 0x10c0, \ + "AMPS" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "AREFS" }, /* References enable , */ \ + { 0x10e0, \ + "ADCCR" }, /* Control ADC , */ \ + { 0x10f0, \ + "BODNOK" }, /* BOD , */ \ + { 0x1100, \ + "DCIL" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "DCDCA" }, /* DCDC active , */ \ + { 0x1120, \ + "DCOCPOK" }, /* DCDC OCP nmos , */ \ + { 0x1130, \ + "DCPEAKCUR" }, /* Indicates current is max in DC-to-DC converter , */ \ + { 0x1140, \ + "DCHVBAT" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "DCH114" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "DCH107" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "STMUTEB" }, /* side tone (un)mute busy , */ \ + { 0x1180, \ + "STMUTE" }, /* side tone mute state , */ \ + { 0x1190, \ + "TDMLUTER" }, /* TDM LUT error , */ \ + { 0x11a2, \ + "TDMSTAT" }, /* TDM status bits , */ \ + { 0x11d0, \ + "TDMERR" }, /* TDM error , */ \ + { 0x11e0, \ + "HAPTIC" }, /* Status haptic driver , */ \ + { 0x1300, \ + "OCPOAP" }, /* OCPOK pmos A , */ \ + { 0x1310, \ + "OCPOAN" }, /* OCPOK nmos A , */ \ + { 0x1320, \ + "OCPOBP" }, /* OCPOK pmos B , */ \ + { 0x1330, \ + "OCPOBN" }, /* OCPOK nmos B , */ \ + { 0x1340, \ + "CLIPAH" }, /* Clipping A to Vddp , */ \ + { 0x1350, \ + "CLIPAL" }, /* Clipping A to gnd , */ \ + { 0x1360, \ + "CLIPBH" }, /* Clipping B to Vddp , */ \ + { 0x1370, \ + "CLIPBL" }, /* Clipping B to gnd , */ \ + { 0x1380, \ + "OCDS" }, /* OCP amplifier , */ \ + { 0x1390, \ + "CLIPS" }, /* Amplifier clipping , */ \ + { 0x13a0, \ + "TCMPTRG" }, /* Status Tap comparator triggered , */ \ + { 0x13b0, \ + "TAPDET" }, /* Status Tap detected , */ \ + { 0x13c0, \ + "MANWAIT1" }, /* Wait HW I2C settings , */ \ + { 0x13d0, \ + "MANWAIT2" }, /* Wait CF config , */ \ + { 0x13e0, \ + "MANMUTE" }, /* Audio mute sequence , */ \ + { 0x13f0, \ + "MANOPER" }, /* Operating state , */ \ + { 0x1400, \ + "SPKSL" }, /* Left speaker status , */ \ + { 0x1410, \ + "SPKS" }, /* Speaker status , */ \ + { 0x1420, \ + "CLKOOR" }, /* External clock status , */ \ + { 0x1433, \ + "MANSTATE" }, /* Device manager status , */ \ + { 0x1471, \ + "DCMODE" }, /* DCDC mode status bits , */ \ + { 0x1490, \ + "DSPCLKSRC" }, /* DSP clock source selected by manager , */ \ + { 0x14a1, \ + "STARTUPMODSTAT" }, /* Startup Mode Selected by Manager(Read Only) , */ \ + { 0x14c3, \ + "TSPMSTATE" }, /* Tap Machine State , */ \ + { 0x1509, \ + "BATS" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "TEMPS" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "VDDPS" }, /* IC VDDP voltage ( 1023*VDDP/13 V) , */ \ + { 0x17a0, \ + "DCILCF" }, /* DCDC current limiting for DSP , */ \ + { 0x2000, \ + "TDMUC" }, /* Mode setting , */ \ + { 0x2011, \ + "DIO4SEL" }, /* DIO4 Input selection , */ \ + { 0x2040, \ + "TDME" }, /* Enable TDM interface , */ \ + { 0x2050, \ + "TDMMODE" }, /* Slave/master , */ \ + { 0x2060, \ + "TDMCLINV" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "TDMFSLN" }, /* FS length , */ \ + { 0x20b0, \ + "TDMFSPOL" }, /* FS polarity , */ \ + { 0x20c3, \ + "TDMNBCK" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "TDMSLOTS" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "TDMSLLN" }, /* N-bits in slot , */ \ + { 0x2194, \ + "TDMBRMG" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "TDMDEL" }, /* data delay to FS , */ \ + { 0x21f0, \ + "TDMADJ" }, /* data adjustment , */ \ + { 0x2201, \ + "TDMOOMP" }, /* Received audio compression , */ \ + { 0x2224, \ + "TDMSSIZE" }, /* Sample size per slot , */ \ + { 0x2271, \ + "TDMTXDFO" }, /* Format unused bits in a slot , */ \ + { 0x2291, \ + "TDMTXUS0" }, /* Format unused slots GAINIO , */ \ + { 0x22b1, \ + "TDMTXUS1" }, /* Format unused slots DIO1 , */ \ + { 0x22d1, \ + "TDMTXUS2" }, /* Format unused slots DIO2 , */ \ + { 0x2300, \ + "TDMGIE" }, /* Control gain (channel in 0) , */ \ + { 0x2310, \ + "TDMDCE" }, /* Control audio left (channel in 1 ) , */ \ + { 0x2320, \ + "TDMSPKE" }, /* Control audio right (channel in 2 ) , */ \ + { 0x2330, \ + "TDMCSE" }, /* Current sense , */ \ + { 0x2340, \ + "TDMVSE" }, /* Voltage sense , */ \ + { 0x2350, \ + "TDMGOE" }, /* DSP Gainout , */ \ + { 0x2360, \ + "TDMCF2E" }, /* DSP 2 , */ \ + { 0x2370, \ + "TDMCF3E" }, /* DSP 3 , */ \ + { 0x2380, \ + "TDMCFE" }, /* DSP , */ \ + { 0x2390, \ + "TDMES6" }, /* Loopback of Audio left (channel 1) , */ \ + { 0x23a0, \ + "TDMES7" }, /* Loopback of Audio right (channel 2) , */ \ + { 0x23b0, \ + "TDMCF4E" }, /* AEC ref right control , */ \ + { 0x23c0, \ + "TDMPD1E" }, /* PDM 1 control , */ \ + { 0x23d0, \ + "TDMPD2E" }, /* PDM 2 control , */ \ + { 0x2401, \ + "TDMGIN" }, /* IO gainin , */ \ + { 0x2421, \ + "TDMLIO" }, /* IO audio left , */ \ + { 0x2441, \ + "TDMRIO" }, /* IO audio right , */ \ + { 0x2461, \ + "TDMCSIO" }, /* IO Current Sense , */ \ + { 0x2481, \ + "TDMVSIO" }, /* IO voltage sense , */ \ + { 0x24a1, \ + "TDMGOIO" }, /* IO gain out , */ \ + { 0x24c1, \ + "TDMCFIO2" }, /* IO DSP 2 , */ \ + { 0x24e1, \ + "TDMCFIO3" }, /* IO DSP 3 , */ \ + { 0x2501, \ + "TDMCFIO" }, /* IO DSP , */ \ + { 0x2521, \ + "TDMLPB6" }, /* IO Source 6 , */ \ + { 0x2541, \ + "TDMLPB7" }, /* IO Source 7 , */ \ + { 0x2603, \ + "TDMGS" }, /* Control gainin , */ \ + { 0x2643, \ + "TDMDCS" }, /* tdm slot for audio left (channel 1) , */ \ + { 0x2683, \ + "TDMSPKS" }, /* tdm slot for audio right (channel 2) , */ \ + { 0x26c3, \ + "TDMCSS" }, /* Slot Position of Current Sense Out , */ \ + { 0x2703, \ + "TDMVSS" }, /* Slot Position of Voltage sense , */ \ + { 0x2743, \ + "TDMCGOS" }, /* Slot Position of GAIN out , */ \ + { 0x2783, \ + "TDMCF2S" }, /* Slot Position DSPout2 , */ \ + { 0x27c3, \ + "TDMCF3S" }, /* Slot Position DSPout3 , */ \ + { 0x2803, \ + "TDMCFS" }, /* Slot Position of DSPout , */ \ + { 0x2843, \ + "TDMEDAT6S" }, /* Slot Position of loopback channel left , */ \ + { 0x2883, \ + "TDMEDAT7S" }, /* Slot Position of loopback channel right , */ \ + { 0x2901, \ + "TDMTXUS3" }, /* Format unused slots D3 , */ \ + { 0x3100, \ + "PDMSM" }, /* PDM control , */ \ + { 0x3110, \ + "PDMSTSEL" }, /* PDM Decimator input selection , */ \ + { 0x3120, \ + "PDMSTENBL" }, /* Side tone input enable , */ \ + { 0x3130, \ + "PDMLSEL" }, /* PDM data selection for left channel during PDM direct mode, */ \ + { 0x3140, \ + "PDMRSEL" }, /* PDM data selection for right channel during PDM direct mode, */ \ + { 0x3150, \ + "MICVDDE" }, /* Enable MICVDD , */ \ + { 0x3201, \ + "PDMCLRAT" }, /* PDM BCK/Fs ratio , */ \ + { 0x3223, \ + "PDMGAIN" }, /* PDM gain , */ \ + { 0x3263, \ + "PDMOSEL" }, /* PDM output selection - RE/FE data combination , */ \ + { 0x32a0, \ + "SELCFHAPD" }, /* Select the source for haptic data output (not for customer), */ \ + { 0x4000, \ + "ISTVDDS" }, /* Status POR , */ \ + { 0x4010, \ + "ISTPLLS" }, /* Status PLL lock , */ \ + { 0x4020, \ + "ISTOTDS" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "ISTOVDS" }, /* Status OVP alarm , */ \ + { 0x4040, \ + "ISTUVDS" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "ISTCLKS" }, /* Status clocks stable , */ \ + { 0x4060, \ + "ISTMTPB" }, /* Status MTP busy , */ \ + { 0x4070, \ + "ISTNOCLK" }, /* Status lost clock , */ \ + { 0x4080, \ + "ISTSPKS" }, /* Status speaker error , */ \ + { 0x4090, \ + "ISTACS" }, /* Status cold start , */ \ + { 0x40a0, \ + "ISTSWS" }, /* Status amplifier engage , */ \ + { 0x40b0, \ + "ISTWDS" }, /* Status watchdog , */ \ + { 0x40c0, \ + "ISTAMPS" }, /* Status amplifier enable , */ \ + { 0x40d0, \ + "ISTAREFS" }, /* Status Ref enable , */ \ + { 0x40e0, \ + "ISTADCCR" }, /* Status Control ADC , */ \ + { 0x40f0, \ + "ISTBODNOK" }, /* Status BOD , */ \ + { 0x4100, \ + "ISTBSTCU" }, /* Status DCDC current limiting , */ \ + { 0x4110, \ + "ISTBSTHI" }, /* Status DCDC active , */ \ + { 0x4120, \ + "ISTBSTOC" }, /* Status DCDC OCP , */ \ + { 0x4130, \ + "ISTBSTPKCUR" }, /* Status bst peakcur , */ \ + { 0x4140, \ + "ISTBSTVC" }, /* Status DCDC level 1x , */ \ + { 0x4150, \ + "ISTBST86" }, /* Status DCDC level 1.14x , */ \ + { 0x4160, \ + "ISTBST93" }, /* Status DCDC level 1.07x , */ \ + { 0x4170, \ + "ISTRCVLD" }, /* Status rcvldop ready , */ \ + { 0x4180, \ + "ISTOCPL" }, /* Status ocp alarm left , */ \ + { 0x4190, \ + "ISTOCPR" }, /* Status ocp alarm , */ \ + { 0x41a0, \ + "ISTMWSRC" }, /* Status Waits HW I2C settings , */ \ + { 0x41b0, \ + "ISTMWCFC" }, /* Status waits CF config , */ \ + { 0x41c0, \ + "ISTMWSMU" }, /* Status Audio mute sequence , */ \ + { 0x41d0, \ + "ISTCFMER" }, /* Status cfma error , */ \ + { 0x41e0, \ + "ISTCFMAC" }, /* Status cfma ack , */ \ + { 0x41f0, \ + "ISTCLKOOR" }, /* Status flag_clk_out_of_range , */ \ + { 0x4200, \ + "ISTTDMER" }, /* Status tdm error , */ \ + { 0x4210, \ + "ISTCLPL" }, /* Status clip left , */ \ + { 0x4220, \ + "ISTCLPR" }, /* Status clip , */ \ + { 0x4230, \ + "ISTOCPM" }, /* Status mic ocpok , */ \ + { 0x4250, \ + "ISTLP1" }, /* Status low power mode1 , */ \ + { 0x4260, \ + "ISTLA" }, /* Status low amplitude detection , */ \ + { 0x4270, \ + "ISTVDDP" }, /* Status VDDP greater than VBAT , */ \ + { 0x4280, \ + "ISTTAPDET" }, /* Status Tap detected , */ \ + { 0x4290, \ + "ISTAUDMOD" }, /* Status Audio Mode activated , */ \ + { 0x42a0, \ + "ISTSAMMOD" }, /* Status SAM Mode activated , */ \ + { 0x42b0, \ + "ISTTAPMOD" }, /* Status Tap Mode Activated , */ \ + { 0x42c0, \ + "ISTTAPTRG" }, /* Status Tap comparator triggered , */ \ + { 0x4400, \ + "ICLVDDS" }, /* Clear POR , */ \ + { 0x4410, \ + "ICLPLLS" }, /* Clear PLL lock , */ \ + { 0x4420, \ + "ICLOTDS" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "ICLOVDS" }, /* Clear OVP alarm , */ \ + { 0x4440, \ + "ICLUVDS" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "ICLCLKS" }, /* Clear clocks stable , */ \ + { 0x4460, \ + "ICLMTPB" }, /* Clear mtp busy , */ \ + { 0x4470, \ + "ICLNOCLK" }, /* Clear lost clk , */ \ + { 0x4480, \ + "ICLSPKS" }, /* Clear speaker error , */ \ + { 0x4490, \ + "ICLACS" }, /* Clear cold started , */ \ + { 0x44a0, \ + "ICLSWS" }, /* Clear amplifier engage , */ \ + { 0x44b0, \ + "ICLWDS" }, /* Clear watchdog , */ \ + { 0x44c0, \ + "ICLAMPS" }, /* Clear enbl amp , */ \ + { 0x44d0, \ + "ICLAREFS" }, /* Clear ref enable , */ \ + { 0x44e0, \ + "ICLADCCR" }, /* Clear control ADC , */ \ + { 0x44f0, \ + "ICLBODNOK" }, /* Clear BOD , */ \ + { 0x4500, \ + "ICLBSTCU" }, /* Clear DCDC current limiting , */ \ + { 0x4510, \ + "ICLBSTHI" }, /* Clear DCDC active , */ \ + { 0x4520, \ + "ICLBSTOC" }, /* Clear DCDC OCP , */ \ + { 0x4530, \ + "ICLBSTPC" }, /* Clear bst peakcur , */ \ + { 0x4540, \ + "ICLBSTVC" }, /* Clear DCDC level 1x , */ \ + { 0x4550, \ + "ICLBST86" }, /* Clear DCDC level 1.14x , */ \ + { 0x4560, \ + "ICLBST93" }, /* Clear DCDC level 1.07x , */ \ + { 0x4570, \ + "ICLRCVLD" }, /* Clear rcvldop ready , */ \ + { 0x4580, \ + "ICLOCPL" }, /* Clear ocp alarm left , */ \ + { 0x4590, \ + "ICLOCPR" }, /* Clear ocp alarm , */ \ + { 0x45a0, \ + "ICLMWSRC" }, /* Clear wait HW I2C settings , */ \ + { 0x45b0, \ + "ICLMWCFC" }, /* Clear wait cf config , */ \ + { 0x45c0, \ + "ICLMWSMU" }, /* Clear audio mute sequence , */ \ + { 0x45d0, \ + "ICLCFMER" }, /* Clear cfma err , */ \ + { 0x45e0, \ + "ICLCFMAC" }, /* Clear cfma ack , */ \ + { 0x45f0, \ + "ICLCLKOOR" }, /* Clear flag_clk_out_of_range , */ \ + { 0x4600, \ + "ICLTDMER" }, /* Clear tdm error , */ \ + { 0x4610, \ + "ICLCLPL" }, /* Clear clip left , */ \ + { 0x4620, \ + "ICLCLP" }, /* Clear clip , */ \ + { 0x4630, \ + "ICLOCPM" }, /* Clear mic ocpok , */ \ + { 0x4650, \ + "ICLLP1" }, /* Clear low power mode1 , */ \ + { 0x4660, \ + "ICLLA" }, /* Clear low amplitude detection , */ \ + { 0x4670, \ + "ICLVDDP" }, /* Clear VDDP greater then VBAT , */ \ + { 0x4680, \ + "ICLTAPDET" }, /* Clear Tap detected , */ \ + { 0x4690, \ + "ICLAUDMOD" }, /* Clear Audio Mode activated , */ \ + { 0x46a0, \ + "ICLSAMMOD" }, /* Clear SAM Mode activated , */ \ + { 0x46b0, \ + "ICLTAPMOD" }, /* Clear Tap Mode Activated , */ \ + { 0x46c0, \ + "ICLTAPTRG" }, /* Clear Comparator Interrupt , */ \ + { 0x4800, \ + "IEVDDS" }, /* Enable por , */ \ + { 0x4810, \ + "IEPLLS" }, /* Enable pll lock , */ \ + { 0x4820, \ + "IEOTDS" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "IEOVDS" }, /* Enable OVP alarm , */ \ + { 0x4840, \ + "IEUVDS" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "IECLKS" }, /* Enable clocks stable , */ \ + { 0x4860, \ + "IEMTPB" }, /* Enable mtp busy , */ \ + { 0x4870, \ + "IENOCLK" }, /* Enable lost clk , */ \ + { 0x4880, \ + "IESPKS" }, /* Enable speaker error , */ \ + { 0x4890, \ + "IEACS" }, /* Enable cold started , */ \ + { 0x48a0, \ + "IESWS" }, /* Enable amplifier engage , */ \ + { 0x48b0, \ + "IEWDS" }, /* Enable watchdog , */ \ + { 0x48c0, \ + "IEAMPS" }, /* Enable enbl amp , */ \ + { 0x48d0, \ + "IEAREFS" }, /* Enable ref enable , */ \ + { 0x48e0, \ + "IEADCCR" }, /* Enable Control ADC , */ \ + { 0x48f0, \ + "IEBODNOK" }, /* Enable BOD , */ \ + { 0x4900, \ + "IEBSTCU" }, /* Enable DCDC current limiting , */ \ + { 0x4910, \ + "IEBSTHI" }, /* Enable DCDC active , */ \ + { 0x4920, \ + "IEBSTOC" }, /* Enable DCDC OCP , */ \ + { 0x4930, \ + "IEBSTPC" }, /* Enable bst peakcur , */ \ + { 0x4940, \ + "IEBSTVC" }, /* Enable DCDC level 1x , */ \ + { 0x4950, \ + "IEBST86" }, /* Enable DCDC level 1.14x , */ \ + { 0x4960, \ + "IEBST93" }, /* Enable DCDC level 1.07x , */ \ + { 0x4970, \ + "IERCVLD" }, /* Enable rcvldop ready , */ \ + { 0x4980, \ + "IEOCPL" }, /* Enable ocp alarm left , */ \ + { 0x4990, \ + "IEOCPR" }, /* Enable ocp alarm , */ \ + { 0x49a0, \ + "IEMWSRC" }, /* Enable waits HW I2C settings , */ \ + { 0x49b0, \ + "IEMWCFC" }, /* Enable man wait cf config , */ \ + { 0x49c0, \ + "IEMWSMU" }, /* Enable man Audio mute sequence , */ \ + { 0x49d0, \ + "IECFMER" }, /* Enable cfma err , */ \ + { 0x49e0, \ + "IECFMAC" }, /* Enable cfma ack , */ \ + { 0x49f0, \ + "IECLKOOR" }, /* Enable flag_clk_out_of_range , */ \ + { 0x4a00, \ + "IETDMER" }, /* Enable tdm error , */ \ + { 0x4a10, \ + "IECLPL" }, /* Enable clip left , */ \ + { 0x4a20, \ + "IECLPR" }, /* Enable clip , */ \ + { 0x4a30, \ + "IEOCPM1" }, /* Enable mic ocpok , */ \ + { 0x4a50, \ + "IELP1" }, /* Enable low power mode1 , */ \ + { 0x4a60, \ + "IELA" }, /* Enable low amplitude detection , */ \ + { 0x4a70, \ + "IEVDDP" }, /* Enable VDDP greater than VBAT , */ \ + { 0x4a80, \ + "IETAPDET" }, /* Enable Tap detected , */ \ + { 0x4a90, \ + "IEAUDMOD" }, /* Enable Audio Mode activated , */ \ + { 0x4aa0, \ + "IESAMMOD" }, /* Enable SAM Mode activated , */ \ + { 0x4ab0, \ + "IETAPMOD" }, /* Enable Tap Mode Activated , */ \ + { 0x4ac0, \ + "IETAPTRG" }, /* Enable comparator interrupt , */ \ + { 0x4c00, \ + "IPOVDDS" }, /* Polarity por , */ \ + { 0x4c10, \ + "IPOPLLS" }, /* Polarity pll lock , */ \ + { 0x4c20, \ + "IPOOTDS" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "IPOOVDS" }, /* Polarity OVP alarm , */ \ + { 0x4c40, \ + "IPOUVDS" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "IPOCLKS" }, /* Polarity clocks stable , */ \ + { 0x4c60, \ + "IPOMTPB" }, /* Polarity mtp busy , */ \ + { 0x4c70, \ + "IPONOCLK" }, /* Polarity lost clk , */ \ + { 0x4c80, \ + "IPOSPKS" }, /* Polarity speaker error , */ \ + { 0x4c90, \ + "IPOACS" }, /* Polarity cold started , */ \ + { 0x4ca0, \ + "IPOSWS" }, /* Polarity amplifier engage , */ \ + { 0x4cb0, \ + "IPOWDS" }, /* Polarity watchdog , */ \ + { 0x4cc0, \ + "IPOAMPS" }, /* Polarity enbl amp , */ \ + { 0x4cd0, \ + "IPOAREFS" }, /* Polarity ref enable , */ \ + { 0x4ce0, \ + "IPOADCCR" }, /* Polarity Control ADC , */ \ + { 0x4cf0, \ + "IPOBODNOK" }, /* Polarity BOD , */ \ + { 0x4d00, \ + "IPOBSTCU" }, /* Polarity DCDC current limiting , */ \ + { 0x4d10, \ + "IPOBSTHI" }, /* Polarity DCDC active , */ \ + { 0x4d20, \ + "IPOBSTOC" }, /* Polarity DCDC OCP , */ \ + { 0x4d30, \ + "IPOBSTPC" }, /* Polarity bst peakcur , */ \ + { 0x4d40, \ + "IPOBSTVC" }, /* Polarity DCDC level 1x , */ \ + { 0x4d50, \ + "IPOBST86" }, /* Polarity DCDC level 1.14x , */ \ + { 0x4d60, \ + "IPOBST93" }, /* Polarity DCDC level 1.07x , */ \ + { 0x4d70, \ + "IPORCVLD" }, /* Polarity rcvldop ready , */ \ + { 0x4d80, \ + "IPOOCPL" }, /* Polarity ocp alarm left , */ \ + { 0x4d90, \ + "IPOOCPR" }, /* Polarity ocp alarm , */ \ + { 0x4da0, \ + "IPOMWSRC" }, /* Polarity waits HW I2C settings , */ \ + { 0x4db0, \ + "IPOMWCFC" }, /* Polarity man wait cf config , */ \ + { 0x4dc0, \ + "IPOMWSMU" }, /* Polarity man audio mute sequence , */ \ + { 0x4dd0, \ + "IPOCFMER" }, /* Polarity cfma err , */ \ + { 0x4de0, \ + "IPOCFMAC" }, /* Polarity cfma ack , */ \ + { 0x4df0, \ + "IPOCLKOOR" }, /* Polarity flag_clk_out_of_range , */ \ + { 0x4e00, \ + "IPOTDMER" }, /* Polarity tdm error , */ \ + { 0x4e10, \ + "IPOCLPL" }, /* Polarity clip left , */ \ + { 0x4e20, \ + "IPOCLPR" }, /* Polarity clip , */ \ + { 0x4e30, \ + "IPOOCPM" }, /* Polarity mic ocpok , */ \ + { 0x4e50, \ + "IPOLP1" }, /* Polarity low power mode1 , */ \ + { 0x4e60, \ + "IPOLA" }, /* Polarity low amplitude detection , */ \ + { 0x4e70, \ + "IPOVDDP" }, /* Polarity VDDP greater than VBAT , */ \ + { 0x4e80, \ + "IPOLTAPDET" }, /* PolarityTap detected , */ \ + { 0x4e90, \ + "IPOLAUDMOD" }, /* PolarityAudio Mode activated , */ \ + { 0x4ea0, \ + "IPOLSAMMOD" }, /* PolaritySAM Mode activated , */ \ + { 0x4eb0, \ + "IPOLTAPMOD" }, /* Polarity Tap Mode Activated , */ \ + { 0x4ec0, \ + "IPOLTAPTRG" }, /* PolarityTap Comparator Trigger , */ \ + { 0x5001, \ + "BSSCR" }, /* Battery Safeguard attack time , */ \ + { 0x5023, \ + "BSST" }, /* Battery Safeguard threshold voltage level , */ \ + { 0x5061, \ + "BSSRL" }, /* Battery Safeguard maximum reduction , */ \ + { 0x5082, \ + "BSSRR" }, /* Battery Safeguard release time , */ \ + { 0x50b1, \ + "BSSHY" }, /* Battery Safeguard hysteresis , */ \ + { 0x50d0, \ + "BSSAC" }, /* Reset clipper - Auto clear , */ \ + { 0x50e0, \ + "BSSR" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "BSSBY" }, /* Bypass HW clipper , */ \ + { 0x5100, \ + "BSSS" }, /* Vbat prot steepness , */ \ + { 0x5110, \ + "INTSMUTE" }, /* Soft mute HW , */ \ + { 0x5120, \ + "CFSML" }, /* Soft mute FW left , */ \ + { 0x5130, \ + "CFSM" }, /* Soft mute FW , */ \ + { 0x5140, \ + "HPFBYPL" }, /* Bypass HPF left , */ \ + { 0x5150, \ + "HPFBYP" }, /* Bypass HPF , */ \ + { 0x5160, \ + "DPSAL" }, /* Enable DPSA left , */ \ + { 0x5170, \ + "DPSA" }, /* Enable DPSA , */ \ + { 0x5187, \ + "VOL" }, /* FW volume control for primary audio channel , */ \ + { 0x5200, \ + "HNDSFRCV" }, /* Selection receiver , */ \ + { 0x5222, \ + "CLIPCTRL" }, /* Clip control setting , */ \ + { 0x5257, \ + "AMPGAIN" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "SLOPEE" }, /* Enables slope control , */ \ + { 0x52e0, \ + "SLOPESET" }, /* Slope speed setting (bin. coded) , */ \ + { 0x5c07, \ + "CFTAPPAT" }, /* Coolflux tap pattern , */ \ + { 0x5c83, \ + "TAPDBGINFO" }, /* Reserved , */ \ + { 0x5d0f, \ + "TATPSTAT1" }, /* Tap Status 1 from CF FW , */ \ + { 0x5f03, \ + "TCOMPTHR" }, /* Comparator threshold (in uV) , */ \ + { 0x6081, \ + "PGAGAIN" }, /* PGA gain selection , */ \ + { 0x6123, \ + "TDMSPKG" }, /* System gain (INPLEV 0) , */ \ + { 0x6505, \ + "LPM1LVL" }, /* low power mode1 detector ctrl threshold for low_audio_lvl , */ \ + { 0x6565, \ + "LPM1HLD" }, /* Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio, */ \ + { 0x65c0, \ + "LPM1DIS" }, /* low power mode1 detector control , */ \ + { 0x6630, \ + "DCDIS" }, /* DCDC , */ \ + { 0x6801, \ + "TDMSRCMAP" }, /* tdm source mapping , */ \ + { 0x6821, \ + "TDMSRCAS" }, /* frame a selection , */ \ + { 0x6841, \ + "TDMSRCBS" }, /* frame b selection , */ \ + { 0x68a0, \ + "ANC1C" }, /* ANC one s complement , */ \ + { 0x6901, \ + "SAMMODE" }, /* Sam mode , */ \ + { 0x7033, \ + "DCMCC" }, /* Max coil current , */ \ + { 0x7071, \ + "DCCV" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7090, \ + "DCIE" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "DCSR" }, /* Soft ramp up/down , */ \ + { 0x70c1, \ + "DCINSEL" }, /* DCDC IIR input Selection , */ \ + { 0x70f0, \ + "DCPWM" }, /* DCDC PWM only mode , */ \ + { 0x7504, \ + "DCTRIP" }, /* Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1, */ \ + { 0x7554, \ + "DCTRIP2" }, /* Adaptive boost trip level 2, effective only when boost_intelligent is set to 1, */ \ + { 0x75a4, \ + "DCTRIPT" }, /* Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0x7635, \ + "DCVOF" }, /* First boost voltage level , */ \ + { 0x7695, \ + "DCVOS" }, /* Second boost voltage level , */ \ + { 0x9000, \ + "RST" }, /* Reset , */ \ + { 0x9011, \ + "DMEM" }, /* Target memory , */ \ + { 0x9030, \ + "AIF" }, /* Auto increment , */ \ + { 0x9040, \ + "CFINT" }, /* Interrupt - auto clear , */ \ + { 0x9050, \ + "CFCGATE" }, /* Coolflux clock gating disabling control , */ \ + { 0x9080, \ + "REQCMD" }, /* Firmware event request rpc command , */ \ + { 0x9090, \ + "REQRST" }, /* Firmware event request reset restart , */ \ + { 0x90a0, \ + "REQMIPS" }, /* Firmware event request short on mips , */ \ + { 0x90b0, \ + "REQMUTED" }, /* Firmware event request mute sequence ready , */ \ + { 0x90c0, \ + "REQVOL" }, /* Firmware event request volume ready , */ \ + { 0x90d0, \ + "REQDMG" }, /* Firmware event request speaker damage detected , */ \ + { 0x90e0, \ + "REQCAL" }, /* Firmware event request calibration completed , */ \ + { 0x90f0, \ + "REQRSV" }, /* Firmware event request reserved , */ \ + { 0x910f, \ + "MADD" }, /* Memory address , */ \ + { 0x920f, \ + "MEMA" }, /* Activate memory access , */ \ + { 0x9307, \ + "ERR" }, /* Error flags , */ \ + { 0x9380, \ + "ACKCMD" }, /* Firmware event acknowledge rpc command , */ \ + { 0x9390, \ + "ACKRST" }, /* Firmware event acknowledge reset restart , */ \ + { 0x93a0, \ + "ACKMIPS" }, /* Firmware event acknowledge short on mips , */ \ + { 0x93b0, \ + "ACKMUTED" }, /* Firmware event acknowledge mute sequence ready , */ \ + { 0x93c0, \ + "ACKVOL" }, /* Firmware event acknowledge volume ready , */ \ + { 0x93d0, \ + "ACKDMG" }, /* Firmware event acknowledge speaker damage detected, */ \ + { 0x93e0, \ + "ACKCAL" }, /* Firmware event acknowledge calibration completed , */ \ + { 0x93f0, \ + "ACKRSV" }, /* Firmware event acknowledge reserved , */ \ + { 0xa107, \ + "MTPK" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "KEY1LOCKED" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "KEY2LOCKED" }, /* Indicates KEY2 is locked , */ \ + { 0xa360, \ + "CIMTP" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa50f, \ + "MTPRDMSB" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "MTPRDLSB" }, /* LSB word of MTP manual read data , */ \ + { 0xb108, \ + "EXTTS" }, /* External temperature (C) , */ \ + { 0xb190, \ + "TROS" }, /* Select temp Speaker calibration , */ \ + { 0xee0f, \ + "SWPROFIL" }, /* Software profile data , */ \ + { 0xef0f, \ + "SWVSTEP" }, /* Software vstep information , */ \ + { 0xf000, \ + "MTPOTC" }, /* Calibration schedule , */ \ + { 0xf010, \ + "MTPEX" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "DCMCCAPI" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "DCMCCSB" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "DCMCCCL" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "USERDEF" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf40f, \ + "R25C" }, /* Ron resistance of speaker coil , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +#define TFA9912_BITNAMETABLE \ + static tfaBfName_t Tfa9912BitNames[] = { \ + { 0x0, \ + "powerdown" }, /* Powerdown selection , */ \ + { 0x10, \ + "reset" }, /* I2C Reset - Auto clear , */ \ + { 0x20, \ + "enbl_coolflux" }, /* Enable CoolFlux , */ \ + { 0x30, \ + "enbl_amplifier" }, /* Enables the Amplifier , */ \ + { 0x40, \ + "enbl_boost" }, /* Activate DC-to-DC converter , */ \ + { 0x50, \ + "coolflux_configured" }, /* Coolflux configured , */ \ + { 0x60, \ + "sel_enbl_amplifier" }, /* CoolFlux controls amplifier , */ \ + { 0x71, \ + "int_pad_io" }, /* Interrupt config , */ \ + { 0x90, \ + "fs_pulse_sel" }, /* Audio sample reference , */ \ + { 0xb0, \ + "bypass_ocp" }, /* Bypass OCP , */ \ + { 0xc0, \ + "test_ocp" }, /* OCP testing control , */ \ + { 0x101, \ + "vamp_sel" }, /* Amplifier input selection , */ \ + { 0x120, \ + "src_set_configured" }, /* I2C configured , */ \ + { 0x130, \ + "execute_cold_start" }, /* Execute cold start , */ \ + { 0x140, \ + "enbl_fro8m_auto_off" }, /* Internal osc off at PWDN , */ \ + { 0x150, \ + "man_enbl_brown_out" }, /* Reaction on BOD , */ \ + { 0x160, \ + "enbl_bod" }, /* BOD Enable , */ \ + { 0x170, \ + "enbl_bod_hyst" }, /* BOD Hysteresis , */ \ + { 0x181, \ + "bod_delay" }, /* BOD filter , */ \ + { 0x1a1, \ + "bod_lvlsel" }, /* BOD threshold , */ \ + { 0x1d0, \ + "disable_mute_time_out" }, /* Time out SB mute sequence , */ \ + { 0x1e0, \ + "pwm_sel_rcv_ns" }, /* Noise shaper selection , */ \ + { 0x1f0, \ + "man_enbl_watchdog" }, /* Watchdog enable , */ \ + { 0x203, \ + "audio_fs" }, /* Sample rate (fs) , */ \ + { 0x240, \ + "input_level" }, /* TDM output attenuation , */ \ + { 0x255, \ + "cs_frac_delay" }, /* V/I Fractional delay , */ \ + { 0x2b0, \ + "bypass_hvbat_filter" }, /* Bypass HVBAT filter , */ \ + { 0x2c0, \ + "tdm_tfa9872_compatible" }, /* TDM Compatibility with TFA9872 , */ \ + { 0x2d0, \ + "sel_hysteresis" }, /* Select hysteresis for clock range detector , */ \ + { 0x2e0, \ + "enbl_adc10" }, /* ADC10 Enable - I2C direct mode , */ \ + { 0x30f, \ + "device_rev" }, /* Revision info , */ \ + { 0x401, \ + "pll_clkin_sel" }, /* PLL external ref clock , */ \ + { 0x420, \ + "pll_clkin_sel_osc" }, /* PLL internal ref clock , */ \ + { 0x430, \ + "cf_clock_scaling" }, /* Coolflux DSP clock scaling, low power mode , */ \ + { 0x441, \ + "sel_cf_clock" }, /* Coolflux DSP clock scaler selection for low power mode, */ \ + { 0x460, \ + "tdm_intf_sel" }, /* TDM clock selection , */ \ + { 0x470, \ + "disable_auto_sel_refclk" }, /* Disable Automatic dsp clock source selection , */ \ + { 0x480, \ + "sel_clk_src" }, /* I2C selection of DSP clock when auto select is disabled, */ \ + { 0x490, \ + "wdt_tim_clk_src" }, /* I2C selection of Watchdog and Timer clock , */ \ + { 0x510, \ + "enbl_spkr_ss" }, /* Enable speaker path , */ \ + { 0x530, \ + "enbl_volsense" }, /* Voltage sense , */ \ + { 0x550, \ + "enbl_cursense" }, /* Current sense , */ \ + { 0x560, \ + "enbl_pdm_ss" }, /* Sub-system PDM , */ \ + { 0x580, \ + "enbl_pga_chop" }, /* Enable PGA chop clock , */ \ + { 0x590, \ + "enbl_tdm_ss" }, /* Sub-system TDM , */ \ + { 0x5a0, \ + "enbl_bst_ss" }, /* Sub-system boost , */ \ + { 0x5b0, \ + "enbl_adc10_ss" }, /* Sub-system ADC , */ \ + { 0x5c0, \ + "enbl_faim_ss" }, /* Sub-system FAIM , */ \ + { 0x5d0, \ + "enbl_tim_clk" }, /* CF Sub-system timer , */ \ + { 0x5e0, \ + "enbl_wdt_clk" }, /* CF Sub-system WDT , */ \ + { 0x5f0, \ + "faim_enable_vbg" }, /* Over rule of vbg for FaIM access , */ \ + { 0x600, \ + "aux_spkr_sel" }, /* Input selection for TAP/SAM , */ \ + { 0x620, \ + "bypass_tapdec_reset" }, /* Tap decimator reset bypass - Bypass the decimator reset from tapdec, */ \ + { 0x631, \ + "car_dec_in_sel0" }, /* Cardec input 0 sel , */ \ + { 0x651, \ + "car_dec_in_sel1" }, /* Cardec input sel , */ \ + { 0x670, \ + "tapdec_sel" }, /* Select TAP/Cardec for TAP , */ \ + { 0x680, \ + "comp_count" }, /* Comparator o/p filter selection , */ \ + { 0x691, \ + "startup_mode" }, /* Startup Mode Selection , */ \ + { 0x6b0, \ + "enable_auto_tap_switching" }, /* Enable auto tap switching , */ \ + { 0x6c1, \ + "comp_init_time" }, /* Comparator initialization time to be used in Tap Machine, */ \ + { 0x6e1, \ + "ana_init_time" }, /* Analog initialization time to be used in Tap Machine, */ \ + { 0x707, \ + "clkchk_th_hi" }, /* Clock check Higher Threshold , */ \ + { 0x787, \ + "clkchk_th_lo" }, /* Clock check Higher Threshold , */ \ + { 0x802, \ + "ctrl_on2off_criterion" }, /* Amplifier on-off criteria for shutdown , */ \ + { 0x832, \ + "ctrl_on2tap_criterion" }, /* Amplifier on-off criteria for tap mode entry , */ \ + { 0xd00, \ + "side_tone_gain_sel" }, /* PDM side tone gain selector , */ \ + { 0xd18, \ + "side_tone_gain" }, /* Side tone gain , */ \ + { 0xda0, \ + "mute_side_tone" }, /* Side tone soft mute , */ \ + { 0xdb0, \ + "side_tone_1scomplement" }, /* side tone one s complement , */ \ + { 0xe07, \ + "ctrl_digtoana" }, /* Spare control from digital to analog , */ \ + { 0xf0f, \ + "hidden_code" }, /* 5A6Bh, 23147d to access registers (default for engineering), */ \ + { 0x1000, \ + "flag_por" }, /* POR , */ \ + { 0x1010, \ + "flag_pll_lock" }, /* PLL lock , */ \ + { 0x1020, \ + "flag_otpok" }, /* OTP alarm , */ \ + { 0x1030, \ + "flag_ovpok" }, /* OVP alarm , */ \ + { 0x1040, \ + "flag_uvpok" }, /* UVP alarm , */ \ + { 0x1050, \ + "flag_clocks_stable" }, /* Clocks stable , */ \ + { 0x1060, \ + "flag_mtp_busy" }, /* MTP busy , */ \ + { 0x1070, \ + "flag_lost_clk" }, /* Lost clock , */ \ + { 0x1090, \ + "flag_cold_started" }, /* Cold Start , */ \ + { 0x10a0, \ + "flag_engage" }, /* Amplifier engage , */ \ + { 0x10b0, \ + "flag_watchdog_reset" }, /* Watchdog , */ \ + { 0x10c0, \ + "flag_enbl_amp" }, /* Amplifier enable , */ \ + { 0x10d0, \ + "flag_enbl_ref" }, /* References enable , */ \ + { 0x10e0, \ + "flag_adc10_ready" }, /* Control ADC , */ \ + { 0x10f0, \ + "flag_bod_vddd_nok" }, /* BOD , */ \ + { 0x1100, \ + "flag_bst_bstcur" }, /* DCDC current limiting , */ \ + { 0x1110, \ + "flag_bst_hiz" }, /* DCDC active , */ \ + { 0x1120, \ + "flag_bst_ocpok" }, /* DCDC OCP nmos , */ \ + { 0x1130, \ + "flag_bst_peakcur" }, /* Indicates current is max in DC-to-DC converter , */ \ + { 0x1140, \ + "flag_bst_voutcomp" }, /* DCDC level 1x , */ \ + { 0x1150, \ + "flag_bst_voutcomp86" }, /* DCDC level 1.14x , */ \ + { 0x1160, \ + "flag_bst_voutcomp93" }, /* DCDC level 1.07x , */ \ + { 0x1170, \ + "flag_soft_mute_busy" }, /* side tone (un)mute busy , */ \ + { 0x1180, \ + "flag_soft_mute_state" }, /* side tone mute state , */ \ + { 0x1190, \ + "flag_tdm_lut_error" }, /* TDM LUT error , */ \ + { 0x11a2, \ + "flag_tdm_status" }, /* TDM status bits , */ \ + { 0x11d0, \ + "flag_tdm_error" }, /* TDM error , */ \ + { 0x1300, \ + "flag_ocpokap" }, /* OCPOK pmos A , */ \ + { 0x1310, \ + "flag_ocpokan" }, /* OCPOK nmos A , */ \ + { 0x1320, \ + "flag_ocpokbp" }, /* OCPOK pmos B , */ \ + { 0x1330, \ + "flag_ocpokbn" }, /* OCPOK nmos B , */ \ + { 0x1340, \ + "flag_clipa_high" }, /* Clipping A to Vddp , */ \ + { 0x1350, \ + "flag_clipa_low" }, /* Clipping A to gnd , */ \ + { 0x1360, \ + "flag_clipb_high" }, /* Clipping B to Vddp , */ \ + { 0x1370, \ + "flag_clipb_low" }, /* Clipping B to gnd , */ \ + { 0x1380, \ + "flag_ocp_alarm" }, /* OCP amplifier , */ \ + { 0x1390, \ + "flag_clip" }, /* Amplifier clipping , */ \ + { 0x13a0, \ + "flag_tap_comp_trig" }, /* Status Tap comparator triggered , */ \ + { 0x13b0, \ + "flag_cf_tapdetected" }, /* Status Tap detected , */ \ + { 0x13c0, \ + "flag_man_wait_src_settings" }, /* Wait HW I2C settings , */ \ + { 0x13d0, \ + "flag_man_wait_cf_config" }, /* Wait CF config , */ \ + { 0x13e0, \ + "flag_man_start_mute_audio" }, /* Audio mute sequence , */ \ + { 0x1410, \ + "flag_cf_speakererror" }, /* Speaker status , */ \ + { 0x1420, \ + "flag_clk_out_of_range" }, /* External clock status , */ \ + { 0x1433, \ + "man_state" }, /* Device manager status , */ \ + { 0x1471, \ + "status_bst_mode" }, /* DCDC mode status bits , */ \ + { 0x1490, \ + "man_dsp_clk_src" }, /* DSP clock source selected by manager , */ \ + { 0x14a1, \ + "man_startup_mode" }, /* Startup Mode Selected by Manager(Read Only) , */ \ + { 0x14c3, \ + "tap_machine_state" }, /* Tap Machine State , */ \ + { 0x1509, \ + "bat_adc" }, /* Battery voltage (V) , */ \ + { 0x1608, \ + "temp_adc" }, /* IC Temperature (C) , */ \ + { 0x1709, \ + "vddp_adc" }, /* IC VDDP voltage ( 1023*VDDP/13 V) , */ \ + { 0x17a0, \ + "flag_bst_bstcur_cf" }, /* DCDC current limiting for DSP , */ \ + { 0x2000, \ + "tdm_usecase" }, /* Mode setting , */ \ + { 0x2011, \ + "dio4_input_sel" }, /* DIO4 Input selection , */ \ + { 0x2040, \ + "tdm_enable" }, /* Enable TDM interface , */ \ + { 0x2060, \ + "tdm_clk_inversion" }, /* Reception data to BCK clock , */ \ + { 0x2073, \ + "tdm_fs_ws_length" }, /* FS length , */ \ + { 0x20b0, \ + "tdm_fs_ws_polarity" }, /* FS polarity , */ \ + { 0x20c3, \ + "tdm_nbck" }, /* N-BCK's in FS , */ \ + { 0x2103, \ + "tdm_nb_of_slots" }, /* N-slots in Frame , */ \ + { 0x2144, \ + "tdm_slot_length" }, /* N-bits in slot , */ \ + { 0x2194, \ + "tdm_bits_remaining" }, /* N-bits remaining , */ \ + { 0x21e0, \ + "tdm_data_delay" }, /* data delay to FS , */ \ + { 0x21f0, \ + "tdm_data_adjustment" }, /* data adjustment , */ \ + { 0x2201, \ + "tdm_audio_sample_compression" }, /* Received audio compression , */ \ + { 0x2224, \ + "tdm_sample_size" }, /* Sample size per slot , */ \ + { 0x2271, \ + "tdm_txdata_format" }, /* Format unused bits in a slot , */ \ + { 0x2291, \ + "tdm_txdata_format_unused_slot_sd0" }, /* Format unused slots GAINIO , */ \ + { 0x22b1, \ + "tdm_txdata_format_unused_slot_sd1" }, /* Format unused slots DIO1 , */ \ + { 0x22d1, \ + "tdm_txdata_format_unused_slot_sd2" }, /* Format unused slots DIO2 , */ \ + { 0x2300, \ + "tdm_sink0_enable" }, /* Control gain (channel in 0) , */ \ + { 0x2310, \ + "tdm_sink1_enable" }, /* Control audio left (channel in 1 ) , */ \ + { 0x2320, \ + "tdm_sink2_enable" }, /* Control audio right (channel in 2 ) , */ \ + { 0x2330, \ + "tdm_source0_enable" }, /* Current sense , */ \ + { 0x2340, \ + "tdm_source1_enable" }, /* Voltage sense , */ \ + { 0x2350, \ + "tdm_source2_enable" }, /* DSP Gainout , */ \ + { 0x2360, \ + "tdm_source3_enable" }, /* DSP 2 , */ \ + { 0x2370, \ + "tdm_source4_enable" }, /* DSP 3 , */ \ + { 0x2380, \ + "tdm_source5_enable" }, /* DSP , */ \ + { 0x2390, \ + "tdm_source6_enable" }, /* Loopback of Audio left (channel 1) , */ \ + { 0x23a0, \ + "tdm_source7_enable" }, /* Loopback of Audio right (channel 2) , */ \ + { 0x2401, \ + "tdm_sink0_io" }, /* IO gainin , */ \ + { 0x2421, \ + "tdm_sink1_io" }, /* IO audio left , */ \ + { 0x2441, \ + "tdm_sink2_io" }, /* IO audio right , */ \ + { 0x2461, \ + "tdm_source0_io" }, /* IO Current Sense , */ \ + { 0x2481, \ + "tdm_source1_io" }, /* IO voltage sense , */ \ + { 0x24a1, \ + "tdm_source2_io" }, /* IO gain out , */ \ + { 0x24c1, \ + "tdm_source3_io" }, /* IO DSP 2 , */ \ + { 0x24e1, \ + "tdm_source4_io" }, /* IO DSP 3 , */ \ + { 0x2501, \ + "tdm_source5_io" }, /* IO DSP , */ \ + { 0x2521, \ + "tdm_source6_io" }, /* IO Source 6 , */ \ + { 0x2541, \ + "tdm_source7_io" }, /* IO Source 7 , */ \ + { 0x2603, \ + "tdm_sink0_slot" }, /* Control gainin , */ \ + { 0x2643, \ + "tdm_sink1_slot" }, /* tdm slot for audio left (channel 1) , */ \ + { 0x2683, \ + "tdm_sink2_slot" }, /* tdm slot for audio right (channel 2) , */ \ + { 0x26c3, \ + "tdm_source0_slot" }, /* Slot Position of Current Sense Out , */ \ + { 0x2703, \ + "tdm_source1_slot" }, /* Slot Position of Voltage sense , */ \ + { 0x2743, \ + "tdm_source2_slot" }, /* Slot Position of GAIN out , */ \ + { 0x2783, \ + "tdm_source3_slot" }, /* Slot Position DSPout2 , */ \ + { 0x27c3, \ + "tdm_source4_slot" }, /* Slot Position DSPout3 , */ \ + { 0x2803, \ + "tdm_source5_slot" }, /* Slot Position of DSPout , */ \ + { 0x2843, \ + "tdm_source6_slot" }, /* Slot Position of loopback channel left , */ \ + { 0x2883, \ + "tdm_source7_slot" }, /* Slot Position of loopback channel right , */ \ + { 0x2901, \ + "tdm_txdata_format_unused_slot_sd3" }, /* Format unused slots D3 , */ \ + { 0x3100, \ + "pdm_mode" }, /* PDM control , */ \ + { 0x3110, \ + "pdm_input_sel" }, /* PDM Decimator input selection , */ \ + { 0x3120, \ + "enbl_pdm_side_tone" }, /* Side tone input enable , */ \ + { 0x3201, \ + "pdm_nbck" }, /* PDM BCK/Fs ratio , */ \ + { 0x4000, \ + "int_out_flag_por" }, /* Status POR , */ \ + { 0x4010, \ + "int_out_flag_pll_lock" }, /* Status PLL lock , */ \ + { 0x4020, \ + "int_out_flag_otpok" }, /* Status OTP alarm , */ \ + { 0x4030, \ + "int_out_flag_ovpok" }, /* Status OVP alarm , */ \ + { 0x4040, \ + "int_out_flag_uvpok" }, /* Status UVP alarm , */ \ + { 0x4050, \ + "int_out_flag_clocks_stable" }, /* Status clocks stable , */ \ + { 0x4060, \ + "int_out_flag_mtp_busy" }, /* Status MTP busy , */ \ + { 0x4070, \ + "int_out_flag_lost_clk" }, /* Status lost clock , */ \ + { 0x4080, \ + "int_out_flag_cf_speakererror" }, /* Status speaker error , */ \ + { 0x4090, \ + "int_out_flag_cold_started" }, /* Status cold start , */ \ + { 0x40a0, \ + "int_out_flag_engage" }, /* Status amplifier engage , */ \ + { 0x40b0, \ + "int_out_flag_watchdog_reset" }, /* Status watchdog , */ \ + { 0x40c0, \ + "int_out_flag_enbl_amp" }, /* Status amplifier enable , */ \ + { 0x40d0, \ + "int_out_flag_enbl_ref" }, /* Status Ref enable , */ \ + { 0x40e0, \ + "int_out_flag_adc10_ready" }, /* Status Control ADC , */ \ + { 0x40f0, \ + "int_out_flag_bod_vddd_nok" }, /* Status BOD , */ \ + { 0x4100, \ + "int_out_flag_bst_bstcur" }, /* Status DCDC current limiting , */ \ + { 0x4110, \ + "int_out_flag_bst_hiz" }, /* Status DCDC active , */ \ + { 0x4120, \ + "int_out_flag_bst_ocpok" }, /* Status DCDC OCP , */ \ + { 0x4130, \ + "int_out_flag_bst_peakcur" }, /* Status bst peakcur , */ \ + { 0x4140, \ + "int_out_flag_bst_voutcomp" }, /* Status DCDC level 1x , */ \ + { 0x4150, \ + "int_out_flag_bst_voutcomp86" }, /* Status DCDC level 1.14x , */ \ + { 0x4160, \ + "int_out_flag_bst_voutcomp93" }, /* Status DCDC level 1.07x , */ \ + { 0x4190, \ + "int_out_flag_ocp_alarm" }, /* Status ocp alarm , */ \ + { 0x41a0, \ + "int_out_flag_man_wait_src_settings" }, /* Status Waits HW I2C settings , */ \ + { 0x41b0, \ + "int_out_flag_man_wait_cf_config" }, /* Status waits CF config , */ \ + { 0x41c0, \ + "int_out_flag_man_start_mute_audio" }, /* Status Audio mute sequence , */ \ + { 0x41d0, \ + "int_out_flag_cfma_err" }, /* Status cfma error , */ \ + { 0x41e0, \ + "int_out_flag_cfma_ack" }, /* Status cfma ack , */ \ + { 0x41f0, \ + "int_out_flag_clk_out_of_range" }, /* Status flag_clk_out_of_range , */ \ + { 0x4200, \ + "int_out_flag_tdm_error" }, /* Status tdm error , */ \ + { 0x4220, \ + "int_out_flag_clip" }, /* Status clip , */ \ + { 0x4250, \ + "int_out_flag_lp_detect_mode1" }, /* Status low power mode1 , */ \ + { 0x4260, \ + "int_out_flag_low_amplitude" }, /* Status low amplitude detection , */ \ + { 0x4270, \ + "int_out_flag_vddp_gt_vbat" }, /* Status VDDP greater than VBAT , */ \ + { 0x4280, \ + "int_out_newtap" }, /* Status Tap detected , */ \ + { 0x4290, \ + "int_out_audiomodeactive" }, /* Status Audio Mode activated , */ \ + { 0x42a0, \ + "int_out_sammodeactive" }, /* Status SAM Mode activated , */ \ + { 0x42b0, \ + "int_out_tapmodeactive" }, /* Status Tap Mode Activated , */ \ + { 0x42c0, \ + "int_out_flag_tap_comp_trig" }, /* Status Tap comparator triggered , */ \ + { 0x4400, \ + "int_in_flag_por" }, /* Clear POR , */ \ + { 0x4410, \ + "int_in_flag_pll_lock" }, /* Clear PLL lock , */ \ + { 0x4420, \ + "int_in_flag_otpok" }, /* Clear OTP alarm , */ \ + { 0x4430, \ + "int_in_flag_ovpok" }, /* Clear OVP alarm , */ \ + { 0x4440, \ + "int_in_flag_uvpok" }, /* Clear UVP alarm , */ \ + { 0x4450, \ + "int_in_flag_clocks_stable" }, /* Clear clocks stable , */ \ + { 0x4460, \ + "int_in_flag_mtp_busy" }, /* Clear mtp busy , */ \ + { 0x4470, \ + "int_in_flag_lost_clk" }, /* Clear lost clk , */ \ + { 0x4480, \ + "int_in_flag_cf_speakererror" }, /* Clear speaker error , */ \ + { 0x4490, \ + "int_in_flag_cold_started" }, /* Clear cold started , */ \ + { 0x44a0, \ + "int_in_flag_engage" }, /* Clear amplifier engage , */ \ + { 0x44b0, \ + "int_in_flag_watchdog_reset" }, /* Clear watchdog , */ \ + { 0x44c0, \ + "int_in_flag_enbl_amp" }, /* Clear enbl amp , */ \ + { 0x44d0, \ + "int_in_flag_enbl_ref" }, /* Clear ref enable , */ \ + { 0x44e0, \ + "int_in_flag_adc10_ready" }, /* Clear control ADC , */ \ + { 0x44f0, \ + "int_in_flag_bod_vddd_nok" }, /* Clear BOD , */ \ + { 0x4500, \ + "int_in_flag_bst_bstcur" }, /* Clear DCDC current limiting , */ \ + { 0x4510, \ + "int_in_flag_bst_hiz" }, /* Clear DCDC active , */ \ + { 0x4520, \ + "int_in_flag_bst_ocpok" }, /* Clear DCDC OCP , */ \ + { 0x4530, \ + "int_in_flag_bst_peakcur" }, /* Clear bst peakcur , */ \ + { 0x4540, \ + "int_in_flag_bst_voutcomp" }, /* Clear DCDC level 1x , */ \ + { 0x4550, \ + "int_in_flag_bst_voutcomp86" }, /* Clear DCDC level 1.14x , */ \ + { 0x4560, \ + "int_in_flag_bst_voutcomp93" }, /* Clear DCDC level 1.07x , */ \ + { 0x4590, \ + "int_in_flag_ocp_alarm" }, /* Clear ocp alarm , */ \ + { 0x45a0, \ + "int_in_flag_man_wait_src_settings" }, /* Clear wait HW I2C settings , */ \ + { 0x45b0, \ + "int_in_flag_man_wait_cf_config" }, /* Clear wait cf config , */ \ + { 0x45c0, \ + "int_in_flag_man_start_mute_audio" }, /* Clear audio mute sequence , */ \ + { 0x45d0, \ + "int_in_flag_cfma_err" }, /* Clear cfma err , */ \ + { 0x45e0, \ + "int_in_flag_cfma_ack" }, /* Clear cfma ack , */ \ + { 0x45f0, \ + "int_in_flag_clk_out_of_range" }, /* Clear flag_clk_out_of_range , */ \ + { 0x4600, \ + "int_in_flag_tdm_error" }, /* Clear tdm error , */ \ + { 0x4620, \ + "int_in_flag_clip" }, /* Clear clip , */ \ + { 0x4650, \ + "int_in_flag_lp_detect_mode1" }, /* Clear low power mode1 , */ \ + { 0x4660, \ + "int_in_flag_low_amplitude" }, /* Clear low amplitude detection , */ \ + { 0x4670, \ + "int_in_flag_vddp_gt_vbat" }, /* Clear VDDP greater then VBAT , */ \ + { 0x4680, \ + "int_in_newtap" }, /* Clear Tap detected , */ \ + { 0x4690, \ + "int_in_audiomodeactive" }, /* Clear Audio Mode activated , */ \ + { 0x46a0, \ + "int_in_sammodeactive" }, /* Clear SAM Mode activated , */ \ + { 0x46b0, \ + "int_in_tapmodeactive" }, /* Clear Tap Mode Activated , */ \ + { 0x46c0, \ + "int_in_flag_tap_comp_trig" }, /* Clear Comparator Interrupt , */ \ + { 0x4800, \ + "int_enable_flag_por" }, /* Enable por , */ \ + { 0x4810, \ + "int_enable_flag_pll_lock" }, /* Enable pll lock , */ \ + { 0x4820, \ + "int_enable_flag_otpok" }, /* Enable OTP alarm , */ \ + { 0x4830, \ + "int_enable_flag_ovpok" }, /* Enable OVP alarm , */ \ + { 0x4840, \ + "int_enable_flag_uvpok" }, /* Enable UVP alarm , */ \ + { 0x4850, \ + "int_enable_flag_clocks_stable" }, /* Enable clocks stable , */ \ + { 0x4860, \ + "int_enable_flag_mtp_busy" }, /* Enable mtp busy , */ \ + { 0x4870, \ + "int_enable_flag_lost_clk" }, /* Enable lost clk , */ \ + { 0x4880, \ + "int_enable_flag_cf_speakererror" }, /* Enable speaker error , */ \ + { 0x4890, \ + "int_enable_flag_cold_started" }, /* Enable cold started , */ \ + { 0x48a0, \ + "int_enable_flag_engage" }, /* Enable amplifier engage , */ \ + { 0x48b0, \ + "int_enable_flag_watchdog_reset" }, /* Enable watchdog , */ \ + { 0x48c0, \ + "int_enable_flag_enbl_amp" }, /* Enable enbl amp , */ \ + { 0x48d0, \ + "int_enable_flag_enbl_ref" }, /* Enable ref enable , */ \ + { 0x48e0, \ + "int_enable_flag_adc10_ready" }, /* Enable Control ADC , */ \ + { 0x48f0, \ + "int_enable_flag_bod_vddd_nok" }, /* Enable BOD , */ \ + { 0x4900, \ + "int_enable_flag_bst_bstcur" }, /* Enable DCDC current limiting , */ \ + { 0x4910, \ + "int_enable_flag_bst_hiz" }, /* Enable DCDC active , */ \ + { 0x4920, \ + "int_enable_flag_bst_ocpok" }, /* Enable DCDC OCP , */ \ + { 0x4930, \ + "int_enable_flag_bst_peakcur" }, /* Enable bst peakcur , */ \ + { 0x4940, \ + "int_enable_flag_bst_voutcomp" }, /* Enable DCDC level 1x , */ \ + { 0x4950, \ + "int_enable_flag_bst_voutcomp86" }, /* Enable DCDC level 1.14x , */ \ + { 0x4960, \ + "int_enable_flag_bst_voutcomp93" }, /* Enable DCDC level 1.07x , */ \ + { 0x4990, \ + "int_enable_flag_ocp_alarm" }, /* Enable ocp alarm , */ \ + { 0x49a0, \ + "int_enable_flag_man_wait_src_settings" }, /* Enable waits HW I2C settings , */ \ + { 0x49b0, \ + "int_enable_flag_man_wait_cf_config" }, /* Enable man wait cf config , */ \ + { 0x49c0, \ + "int_enable_flag_man_start_mute_audio" }, /* Enable man Audio mute sequence , */ \ + { 0x49d0, \ + "int_enable_flag_cfma_err" }, /* Enable cfma err , */ \ + { 0x49e0, \ + "int_enable_flag_cfma_ack" }, /* Enable cfma ack , */ \ + { 0x49f0, \ + "int_enable_flag_clk_out_of_range" }, /* Enable flag_clk_out_of_range , */ \ + { 0x4a00, \ + "int_enable_flag_tdm_error" }, /* Enable tdm error , */ \ + { 0x4a20, \ + "int_enable_flag_clip" }, /* Enable clip , */ \ + { 0x4a50, \ + "int_enable_flag_lp_detect_mode1" }, /* Enable low power mode1 , */ \ + { 0x4a60, \ + "int_enable_flag_low_amplitude" }, /* Enable low amplitude detection , */ \ + { 0x4a70, \ + "int_enable_flag_vddp_gt_vbat" }, /* Enable VDDP greater than VBAT , */ \ + { 0x4a80, \ + "int_enable_newtap" }, /* Enable Tap detected , */ \ + { 0x4a90, \ + "int_enable_audiomodeactive" }, /* Enable Audio Mode activated , */ \ + { 0x4aa0, \ + "int_enable_sammodeactive" }, /* Enable SAM Mode activated , */ \ + { 0x4ab0, \ + "int_enable_tapmodeactive" }, /* Enable Tap Mode Activated , */ \ + { 0x4ac0, \ + "int_enable_flag_tap_comp_trig" }, /* Enable comparator interrupt , */ \ + { 0x4c00, \ + "int_polarity_flag_por" }, /* Polarity por , */ \ + { 0x4c10, \ + "int_polarity_flag_pll_lock" }, /* Polarity pll lock , */ \ + { 0x4c20, \ + "int_polarity_flag_otpok" }, /* Polarity OTP alarm , */ \ + { 0x4c30, \ + "int_polarity_flag_ovpok" }, /* Polarity OVP alarm , */ \ + { 0x4c40, \ + "int_polarity_flag_uvpok" }, /* Polarity UVP alarm , */ \ + { 0x4c50, \ + "int_polarity_flag_clocks_stable" }, /* Polarity clocks stable , */ \ + { 0x4c60, \ + "int_polarity_flag_mtp_busy" }, /* Polarity mtp busy , */ \ + { 0x4c70, \ + "int_polarity_flag_lost_clk" }, /* Polarity lost clk , */ \ + { 0x4c80, \ + "int_polarity_flag_cf_speakererror" }, /* Polarity speaker error , */ \ + { 0x4c90, \ + "int_polarity_flag_cold_started" }, /* Polarity cold started , */ \ + { 0x4ca0, \ + "int_polarity_flag_engage" }, /* Polarity amplifier engage , */ \ + { 0x4cb0, \ + "int_polarity_flag_watchdog_reset" }, /* Polarity watchdog , */ \ + { 0x4cc0, \ + "int_polarity_flag_enbl_amp" }, /* Polarity enbl amp , */ \ + { 0x4cd0, \ + "int_polarity_flag_enbl_ref" }, /* Polarity ref enable , */ \ + { 0x4ce0, \ + "int_polarity_flag_adc10_ready" }, /* Polarity Control ADC , */ \ + { 0x4cf0, \ + "int_polarity_flag_bod_vddd_nok" }, /* Polarity BOD , */ \ + { 0x4d00, \ + "int_polarity_flag_bst_bstcur" }, /* Polarity DCDC current limiting , */ \ + { 0x4d10, \ + "int_polarity_flag_bst_hiz" }, /* Polarity DCDC active , */ \ + { 0x4d20, \ + "int_polarity_flag_bst_ocpok" }, /* Polarity DCDC OCP , */ \ + { 0x4d30, \ + "int_polarity_flag_bst_peakcur" }, /* Polarity bst peakcur , */ \ + { 0x4d40, \ + "int_polarity_flag_bst_voutcomp" }, /* Polarity DCDC level 1x , */ \ + { 0x4d50, \ + "int_polarity_flag_bst_voutcomp86" }, /* Polarity DCDC level 1.14x , */ \ + { 0x4d60, \ + "int_polarity_flag_bst_voutcomp93" }, /* Polarity DCDC level 1.07x , */ \ + { 0x4d90, \ + "int_polarity_flag_ocp_alarm" }, /* Polarity ocp alarm , */ \ + { 0x4da0, \ + "int_polarity_flag_man_wait_src_settings" }, /* Polarity waits HW I2C settings , */ \ + { 0x4db0, \ + "int_polarity_flag_man_wait_cf_config" }, /* Polarity man wait cf config , */ \ + { 0x4dc0, \ + "int_polarity_flag_man_start_mute_audio" }, /* Polarity man audio mute sequence , */ \ + { 0x4dd0, \ + "int_polarity_flag_cfma_err" }, /* Polarity cfma err , */ \ + { 0x4de0, \ + "int_polarity_flag_cfma_ack" }, /* Polarity cfma ack , */ \ + { 0x4df0, \ + "int_polarity_flag_clk_out_of_range" }, /* Polarity flag_clk_out_of_range , */ \ + { 0x4e00, \ + "int_polarity_flag_tdm_error" }, /* Polarity tdm error , */ \ + { 0x4e20, \ + "int_polarity_flag_clip" }, /* Polarity clip , */ \ + { 0x4e50, \ + "int_polarity_flag_lp_detect_mode1" }, /* Polarity low power mode1 , */ \ + { 0x4e60, \ + "int_polarity_flag_low_amplitude" }, /* Polarity low amplitude detection , */ \ + { 0x4e70, \ + "int_polarity_flag_vddp_gt_vbat" }, /* Polarity VDDP greater than VBAT , */ \ + { 0x4e80, \ + "int_polarity_newtap" }, /* PolarityTap detected , */ \ + { 0x4e90, \ + "int_polarity_audiomodeactive" }, /* PolarityAudio Mode activated , */ \ + { 0x4ea0, \ + "int_polarity_sammodeactive" }, /* PolaritySAM Mode activated , */ \ + { 0x4eb0, \ + "int_polarity_tapmodeactive" }, /* Polarity Tap Mode Activated , */ \ + { 0x4ec0, \ + "int_polarity_flag_tap_comp_trig" }, /* PolarityTap Comparator Trigger , */ \ + { 0x5001, \ + "vbat_prot_attack_time" }, /* Battery Safeguard attack time , */ \ + { 0x5023, \ + "vbat_prot_thlevel" }, /* Battery Safeguard threshold voltage level , */ \ + { 0x5061, \ + "vbat_prot_max_reduct" }, /* Battery Safeguard maximum reduction , */ \ + { 0x5082, \ + "vbat_prot_release_time" }, /* Battery Safeguard release time , */ \ + { 0x50b1, \ + "vbat_prot_hysterese" }, /* Battery Safeguard hysteresis , */ \ + { 0x50d0, \ + "rst_min_vbat" }, /* Reset clipper - Auto clear , */ \ + { 0x50e0, \ + "sel_vbat" }, /* Battery voltage read out , */ \ + { 0x50f0, \ + "bypass_clipper" }, /* Bypass HW clipper , */ \ + { 0x5100, \ + "batsense_steepness" }, /* Vbat prot steepness , */ \ + { 0x5110, \ + "soft_mute" }, /* Soft mute HW , */ \ + { 0x5130, \ + "cf_mute" }, /* Soft mute FW , */ \ + { 0x5150, \ + "bypass_hp" }, /* Bypass HPF , */ \ + { 0x5170, \ + "enbl_dpsa" }, /* Enable DPSA , */ \ + { 0x5187, \ + "cf_volume" }, /* FW volume control for primary audio channel , */ \ + { 0x5222, \ + "ctrl_cc" }, /* Clip control setting , */ \ + { 0x5257, \ + "gain" }, /* Amplifier gain , */ \ + { 0x52d0, \ + "ctrl_slopectrl" }, /* Enables slope control , */ \ + { 0x52e0, \ + "ctrl_slope" }, /* Slope speed setting (bin. coded) , */ \ + { 0x5301, \ + "dpsa_level" }, /* DPSA threshold levels , */ \ + { 0x5321, \ + "dpsa_release" }, /* DPSA Release time , */ \ + { 0x5340, \ + "clipfast" }, /* Clock selection for HW clipper for Battery Safeguard, */ \ + { 0x5350, \ + "bypass_lp" }, /* Bypass the low power filter inside temperature sensor, */ \ + { 0x5360, \ + "enbl_low_latency" }, /* CF low latency outputs for add module , */ \ + { 0x5400, \ + "first_order_mode" }, /* Overrule to 1st order mode of control stage when clipping, */ \ + { 0x5410, \ + "bypass_ctrlloop" }, /* Switch amplifier into open loop configuration , */ \ + { 0x5430, \ + "icomp_engage" }, /* Engage of icomp , */ \ + { 0x5440, \ + "ctrl_kickback" }, /* Prevent double pulses of output stage , */ \ + { 0x5450, \ + "icomp_engage_overrule" }, /* To overrule the functional icomp_engage signal during validation, */ \ + { 0x5503, \ + "ctrl_dem" }, /* Enable DEM icomp and DEM one bit dac , */ \ + { 0x5543, \ + "ctrl_dem_mismatch" }, /* Enable DEM icomp mismatch for testing , */ \ + { 0x5582, \ + "dpsa_drive" }, /* Drive setting (bin. coded) - I2C direct mode , */ \ + { 0x570a, \ + "enbl_amp" }, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually , */ \ + { 0x57b0, \ + "enbl_engage" }, /* Enables/engage power stage and control loop - I2C direct mode, */ \ + { 0x57c0, \ + "enbl_engage_pst" }, /* Enables/engage power stage and control loop , */ \ + { 0x5810, \ + "hard_mute" }, /* Hard mute - PWM , */ \ + { 0x5820, \ + "pwm_shape" }, /* PWM shape , */ \ + { 0x5844, \ + "pwm_delay" }, /* PWM delay bits to set the delay, clock is 1/(k*2048*fs), */ \ + { 0x5890, \ + "reclock_pwm" }, /* Reclock the pwm signal inside analog , */ \ + { 0x58a0, \ + "reclock_voltsense" }, /* Reclock the voltage sense pwm signal , */ \ + { 0x58c0, \ + "enbl_pwm_phase_shift" }, /* Control for pwm phase shift , */ \ + { 0x5c07, \ + "flag_cf_tap_pattern" }, /* Coolflux tap pattern , */ \ + { 0x5c83, \ + "tap_debug_info" }, /* Reserved , */ \ + { 0x5d0f, \ + "tap_status_1" }, /* Tap Status 1 from CF FW , */ \ + { 0x5f03, \ + "tap_comp_threshold" }, /* Comparator threshold (in uV) , */ \ + { 0x6081, \ + "pga_gain_set" }, /* PGA gain selection , */ \ + { 0x60b0, \ + "pga_lowpass_enable" }, /* Lowpass enable , */ \ + { 0x60c0, \ + "pga_pwr_enable" }, /* PGA power enable , */ \ + { 0x60d0, \ + "pga_switch_enable" }, /* PGA switch enable , */ \ + { 0x60e0, \ + "pga_switch_aux_enable" }, /* Switch enable aux , */ \ + { 0x6123, \ + "ctrl_att" }, /* System gain (INPLEV 0) , */ \ + { 0x6265, \ + "zero_lvl" }, /* ctrl threshold for zero X-ing , */ \ + { 0x62c1, \ + "ctrl_fb_resistor" }, /* Select amplifier feedback resistor connection , */ \ + { 0x62e1, \ + "lownoisegain_mode" }, /* ctrl select mode , */ \ + { 0x6305, \ + "threshold_lvl" }, /* ctrl threshold for low_audio_lvl , */ \ + { 0x6365, \ + "hold_time" }, /* ctrl hold time before low audio is reckoned to be low audio, */ \ + { 0x6405, \ + "lpm1_cal_offset" }, /* low power mode1 detector ctrl cal_offset from gain module , */ \ + { 0x6465, \ + "lpm1_zero_lvl" }, /* low power mode1 detector ctrl threshold for zero X-ing , */ \ + { 0x64e1, \ + "lpm1_mode" }, /* low power mode1 detector ctrl select mode , */ \ + { 0x6505, \ + "lpm1_threshold_lvl" }, /* low power mode1 detector ctrl threshold for low_audio_lvl , */ \ + { 0x6565, \ + "lpm1_hold_time" }, /* Low power mode1 detector, ctrl hold time before low audio is reckoned to be low audio, */ \ + { 0x65c0, \ + "disable_low_power_mode" }, /* low power mode1 detector control , */ \ + { 0x6600, \ + "dcdc_pfm20khz_limit" }, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */ \ + { 0x6611, \ + "dcdc_ctrl_maxzercnt" }, /* DCDC. Number of zero current flags to count before going to pfm mode, */ \ + { 0x6630, \ + "dcdcoff_mode" }, /* DCDC , */ \ + { 0x6656, \ + "dcdc_vbat_delta_detect" }, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */ \ + { 0x66c0, \ + "dcdc_ignore_vbat" }, /* Ignore an increase on Vbat , */ \ + { 0x6700, \ + "enbl_minion" }, /* Enables minion (small) power stage - direct ctrl , */ \ + { 0x6713, \ + "vth_vddpvbat" }, /* select vddp-vbat thres signal , */ \ + { 0x6750, \ + "lpen_vddpvbat" }, /* select vddp-vbat filtered vs unfiltered compare , */ \ + { 0x6761, \ + "ctrl_rfb" }, /* Feedback resistor selection - I2C direct mode , */ \ + { 0x6801, \ + "tdm_source_mapping" }, /* tdm source mapping , */ \ + { 0x6821, \ + "tdm_sourcea_frame_sel" }, /* frame a selection , */ \ + { 0x6841, \ + "tdm_sourceb_frame_sel" }, /* frame b selection , */ \ + { 0x6901, \ + "sam_mode" }, /* Sam mode , */ \ + { 0x6931, \ + "pdmdat_h_sel" }, /* pdm out value when pdm_clk is higth , */ \ + { 0x6951, \ + "pdmdat_l_sel" }, /* pdm out value when pdm_clk is low , */ \ + { 0x6970, \ + "cs_sam_set" }, /* Enable SAM input for current sense - I2C Direct Mode, */ \ + { 0x6980, \ + "cs_adc_nortz" }, /* Return to zero for current sense ADC , */ \ + { 0x6990, \ + "sam_spkr_sel" }, /* SAM o/p sel during SAM and audio , */ \ + { 0x6b00, \ + "disable_engage" }, /* Disable auto engage , */ \ + { 0x6c02, \ + "ns_hp2ln_criterion" }, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */ \ + { 0x6c32, \ + "ns_ln2hp_criterion" }, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */ \ + { 0x6c60, \ + "sel_clip_pwms" }, /* To select clip-flags , */ \ + { 0x6c72, \ + "pwms_clip_lvl" }, /* To set the amount of pwm pulse that may be skipped before clip-flag is triggered. , */ \ + { 0x6ca5, \ + "spare_out" }, /* spare_out , */ \ + { 0x6d0f, \ + "spare_in" }, /* spare_in , */ \ + { 0x6e10, \ + "flag_lp_detect_mode1" }, /* low power mode 1 detection , */ \ + { 0x6e20, \ + "flag_low_amplitude" }, /* low amplitude detection , */ \ + { 0x6e30, \ + "flag_vddp_gt_vbat" }, /* vddp greater than vbat , */ \ + { 0x7033, \ + "boost_cur" }, /* Max coil current , */ \ + { 0x7071, \ + "bst_slpcmplvl" }, /* Slope compensation current, represents LxF (inductance x frequency) value , */ \ + { 0x7090, \ + "boost_intel" }, /* Adaptive boost mode , */ \ + { 0x70a0, \ + "boost_speed" }, /* Soft ramp up/down , */ \ + { 0x70c1, \ + "dcdc_sel" }, /* DCDC IIR input Selection , */ \ + { 0x70f0, \ + "dcdc_pwmonly" }, /* DCDC PWM only mode , */ \ + { 0x7104, \ + "bst_drive" }, /* Binary coded drive setting for boost converter power stage, */ \ + { 0x7151, \ + "bst_scalecur" }, /* For testing direct control scale current , */ \ + { 0x7174, \ + "bst_slopecur" }, /* For testing direct control slope current - I2C direct mode, */ \ + { 0x71c1, \ + "bst_slope" }, /* Boost slope speed , */ \ + { 0x71e0, \ + "bst_bypass_bstcur" }, /* Bypass control for boost current settings , */ \ + { 0x71f0, \ + "bst_bypass_bstfoldback" }, /* Bypass control for boost foldback , */ \ + { 0x7200, \ + "enbl_bst_engage" }, /* Enable power stage dcdc controller - I2C direct mode, */ \ + { 0x7210, \ + "enbl_bst_hizcom" }, /* Enable hiz comparator - I2C direct mode , */ \ + { 0x7220, \ + "enbl_bst_peak2avg" }, /* Enable boost peak2avg functionality , */ \ + { 0x7230, \ + "enbl_bst_peakcur" }, /* Enable peak current - I2C direct mode , */ \ + { 0x7240, \ + "enbl_bst_power" }, /* Enable line of the powerstage - I2C direct mode , */ \ + { 0x7250, \ + "enbl_bst_slopecur" }, /* Enable bit of max-current dac - I2C direct mode , */ \ + { 0x7260, \ + "enbl_bst_voutcomp" }, /* Enable vout comparators - I2C direct mode , */ \ + { 0x7270, \ + "enbl_bst_voutcomp86" }, /* Enable vout-86 comparators - I2C direct mode , */ \ + { 0x7280, \ + "enbl_bst_voutcomp93" }, /* Enable vout-93 comparators - I2C direct mode , */ \ + { 0x7290, \ + "enbl_bst_windac" }, /* Enable window dac - I2C direct mode , */ \ + { 0x72a5, \ + "bst_windac" }, /* for testing direct control windac - I2C direct mode, */ \ + { 0x7300, \ + "boost_alg" }, /* Control for boost adaptive loop gain , */ \ + { 0x7311, \ + "boost_loopgain" }, /* DCDC boost loopgain setting , */ \ + { 0x7331, \ + "bst_freq" }, /* DCDC boost frequency control , */ \ + { 0x7430, \ + "boost_track" }, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */ \ + { 0x7494, \ + "boost_hold_time" }, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */ \ + { 0x74e0, \ + "sel_dcdc_envelope_8fs" }, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */ \ + { 0x74f0, \ + "ignore_flag_voutcomp86" }, /* Ignore flag_voutcomp86 , */ \ + { 0x7504, \ + "boost_trip_lvl_1st" }, /* Adaptive boost trip levels 1, effective only when boost_intelligent is set to 1, */ \ + { 0x7554, \ + "boost_trip_lvl_2nd" }, /* Adaptive boost trip level 2, effective only when boost_intelligent is set to 1, */ \ + { 0x75a4, \ + "boost_trip_lvl_track" }, /* Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */ \ + { 0x7602, \ + "track_decay" }, /* DCDC Boost decay speed after a peak value, effective only when boost_track is set to 1, */ \ + { 0x7635, \ + "frst_boost_voltage" }, /* First boost voltage level , */ \ + { 0x7695, \ + "scnd_boost_voltage" }, /* Second boost voltage level , */ \ + { 0x7720, \ + "pga_test_ldo_bypass" }, /* bypass internal PGA LDO , */ \ + { 0x8001, \ + "sel_clk_cs" }, /* Current sense clock duty cycle control , */ \ + { 0x8021, \ + "micadc_speed" }, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */ \ + { 0x8050, \ + "cs_gain_control" }, /* Current sense gain control , */ \ + { 0x8060, \ + "cs_bypass_gc" }, /* Bypasses the CS gain correction , */ \ + { 0x8087, \ + "cs_gain" }, /* Current sense gain , */ \ + { 0x8200, \ + "enbl_cmfb" }, /* Current sense common mode feedback control , */ \ + { 0x8210, \ + "invertpwm" }, /* Current sense common mode feedback pwm invert control, */ \ + { 0x8222, \ + "cmfb_gain" }, /* Current sense common mode feedback control gain , */ \ + { 0x8256, \ + "cmfb_offset" }, /* Current sense common mode feedback control offset , */ \ + { 0x8305, \ + "cs_ktemp" }, /* First order temperature compensation coefficient , */ \ + { 0x8364, \ + "cs_ktemp2" }, /* Second order temperature compensation coefficient , */ \ + { 0x8400, \ + "cs_adc_bsoinv" }, /* Bitstream inversion for current sense ADC , */ \ + { 0x8421, \ + "cs_adc_hifreq" }, /* Frequency mode current sense ADC , */ \ + { 0x8453, \ + "cs_adc_offset" }, /* Micadc ADC offset setting , */ \ + { 0x8490, \ + "cs_adc_slowdel" }, /* Select delay for current sense ADC (internal decision circuitry), */ \ + { 0x84a4, \ + "cs_adc_gain" }, /* Gain setting for current sense ADC (two's complement), */ \ + { 0x8500, \ + "cs_resonator_enable" }, /* Enable for resonator to improve SRN , */ \ + { 0x8510, \ + "cs_classd_tran_skip" }, /* Skip current sense connection during a classD amplifier transition, */ \ + { 0x8530, \ + "cs_inn_short" }, /* Short current sense negative to common mode , */ \ + { 0x8540, \ + "cs_inp_short" }, /* Short current sense positive to common mode , */ \ + { 0x8550, \ + "cs_ldo_bypass" }, /* Bypass current sense LDO , */ \ + { 0x8560, \ + "cs_ldo_pulldown" }, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */ \ + { 0x8574, \ + "cs_ldo_voset" }, /* Current sense LDO voltage level setting (two's complement), */ \ + { 0x8700, \ + "enbl_cs_adc" }, /* Enable current sense ADC - I2C direct mode , */ \ + { 0x8710, \ + "enbl_cs_inn1" }, /* Enable connection of current sense negative1 - I2C direct mode, */ \ + { 0x8720, \ + "enbl_cs_inn2" }, /* Enable connection of current sense negative2 - I2C direct mode, */ \ + { 0x8730, \ + "enbl_cs_inp1" }, /* Enable connection of current sense positive1 , */ \ + { 0x8740, \ + "enbl_cs_inp2" }, /* Enable connection of current sense positive2 - I2C direct mode, */ \ + { 0x8750, \ + "enbl_cs_ldo" }, /* Enable current sense LDO - I2C direct mode , */ \ + { 0x8760, \ + "enbl_cs_nofloating_n" }, /* Connect current sense negative to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8770, \ + "enbl_cs_nofloating_p" }, /* Connect current sense positive to gnda at transitions of booster or classd amplifiers. Otherwise floating (0), */ \ + { 0x8780, \ + "enbl_cs_vbatldo" }, /* Enable of current sense LDO -- I2C direct mode , */ \ + { 0x8800, \ + "volsense_pwm_sel" }, /* Voltage sense PWM source selection control , */ \ + { 0x8810, \ + "vol_cur_sense_dc_offset" }, /* voltage and current sense decimator offset control, */ \ + { 0x8902, \ + "cursense_comp_delay" }, /* To align compensation signal with current sense signal, */ \ + { 0x8930, \ + "cursense_comp_sign" }, /* To change polarity of compensation for current sense compensation, */ \ + { 0x8940, \ + "enbl_cursense_comp" }, /* To enable current sense compensation , */ \ + { 0x9000, \ + "cf_rst_dsp" }, /* Reset , */ \ + { 0x9011, \ + "cf_dmem" }, /* Target memory , */ \ + { 0x9030, \ + "cf_aif" }, /* Auto increment , */ \ + { 0x9040, \ + "cf_int" }, /* Interrupt - auto clear , */ \ + { 0x9050, \ + "cf_cgate_off" }, /* Coolflux clock gating disabling control , */ \ + { 0x9080, \ + "cf_req_cmd" }, /* Firmware event request rpc command , */ \ + { 0x9090, \ + "cf_req_reset" }, /* Firmware event request reset restart , */ \ + { 0x90a0, \ + "cf_req_mips" }, /* Firmware event request short on mips , */ \ + { 0x90b0, \ + "cf_req_mute_ready" }, /* Firmware event request mute sequence ready , */ \ + { 0x90c0, \ + "cf_req_volume_ready" }, /* Firmware event request volume ready , */ \ + { 0x90d0, \ + "cf_req_damage" }, /* Firmware event request speaker damage detected , */ \ + { 0x90e0, \ + "cf_req_calibrate_ready" }, /* Firmware event request calibration completed , */ \ + { 0x90f0, \ + "cf_req_reserved" }, /* Firmware event request reserved , */ \ + { 0x910f, \ + "cf_madd" }, /* Memory address , */ \ + { 0x920f, \ + "cf_mema" }, /* Activate memory access , */ \ + { 0x9307, \ + "cf_err" }, /* Error flags , */ \ + { 0x9380, \ + "cf_ack_cmd" }, /* Firmware event acknowledge rpc command , */ \ + { 0x9390, \ + "cf_ack_reset" }, /* Firmware event acknowledge reset restart , */ \ + { 0x93a0, \ + "cf_ack_mips" }, /* Firmware event acknowledge short on mips , */ \ + { 0x93b0, \ + "cf_ack_mute_ready" }, /* Firmware event acknowledge mute sequence ready , */ \ + { 0x93c0, \ + "cf_ack_volume_ready" }, /* Firmware event acknowledge volume ready , */ \ + { 0x93d0, \ + "cf_ack_damage" }, /* Firmware event acknowledge speaker damage detected, */ \ + { 0x93e0, \ + "cf_ack_calibrate_ready" }, /* Firmware event acknowledge calibration completed , */ \ + { 0x93f0, \ + "cf_ack_reserved" }, /* Firmware event acknowledge reserved , */ \ + { 0xa007, \ + "mtpkey1" }, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */ \ + { 0xa107, \ + "mtpkey2" }, /* MTP KEY2 register , */ \ + { 0xa200, \ + "key01_locked" }, /* Indicates KEY1 is locked , */ \ + { 0xa210, \ + "key02_locked" }, /* Indicates KEY2 is locked , */ \ + { 0xa302, \ + "mtp_man_address_in" }, /* MTP address from I2C register for read/writing mtp in manual single word mode, */ \ + { 0xa330, \ + "man_copy_mtp_to_iic" }, /* Start copying single word from mtp to I2C mtp register, */ \ + { 0xa340, \ + "man_copy_iic_to_mtp" }, /* Start copying single word from I2C mtp register to mtp, */ \ + { 0xa350, \ + "auto_copy_mtp_to_iic" }, /* Start copying all the data from mtp to I2C mtp registers, */ \ + { 0xa360, \ + "auto_copy_iic_to_mtp" }, /* Start copying data from I2C mtp registers to mtp , */ \ + { 0xa400, \ + "faim_set_clkws" }, /* Sets the FaIM controller clock wait state register, */ \ + { 0xa410, \ + "faim_sel_evenrows" }, /* All even rows of the FaIM are selected, active high, */ \ + { 0xa420, \ + "faim_sel_oddrows" }, /* All odd rows of the FaIM are selected, all rows in combination with sel_evenrows, */ \ + { 0xa430, \ + "faim_program_only" }, /* Skip the erase access at wr_faim command (write-program-marginread), */ \ + { 0xa440, \ + "faim_erase_only" }, /* Skip the program access at wr_faim command (write-erase-marginread), */ \ + { 0xa50f, \ + "mtp_man_data_out_msb" }, /* MSB word of MTP manual read data , */ \ + { 0xa60f, \ + "mtp_man_data_out_lsb" }, /* LSB word of MTP manual read data , */ \ + { 0xa70f, \ + "mtp_man_data_in_msb" }, /* MSB word of write data for MTP manual write , */ \ + { 0xa80f, \ + "mtp_man_data_in_lsb" }, /* LSB word of write data for MTP manual write , */ \ + { 0xb010, \ + "bypass_ocpcounter" }, /* Bypass OCP Counter , */ \ + { 0xb020, \ + "bypass_glitchfilter" }, /* Bypass glitch filter , */ \ + { 0xb030, \ + "bypass_ovp" }, /* Bypass OVP , */ \ + { 0xb040, \ + "bypass_uvp" }, /* Bypass UVP , */ \ + { 0xb050, \ + "bypass_otp" }, /* Bypass OTP , */ \ + { 0xb060, \ + "bypass_lost_clk" }, /* Bypass lost clock detector , */ \ + { 0xb070, \ + "ctrl_vpalarm" }, /* vpalarm (uvp ovp handling) , */ \ + { 0xb087, \ + "ocp_threshold" }, /* OCP threshold level , */ \ + { 0xb108, \ + "ext_temp" }, /* External temperature (C) , */ \ + { 0xb190, \ + "ext_temp_sel" }, /* Select temp Speaker calibration , */ \ + { 0xc000, \ + "use_direct_ctrls" }, /* Direct control to overrule several functions for testing, */ \ + { 0xc010, \ + "rst_datapath" }, /* Direct control for datapath reset , */ \ + { 0xc020, \ + "rst_cgu" }, /* Direct control for cgu reset , */ \ + { 0xc038, \ + "enbl_ref" }, /* Switch on the analog references, each part of the references can be switched on/off individually - - I2C direct mode, */ \ + { 0xc0d0, \ + "enbl_ringo" }, /* Enable the ring oscillator for test purpose , */ \ + { 0xc0e0, \ + "use_direct_clk_ctrl" }, /* Direct clock control to overrule several functions for testing, */ \ + { 0xc0f0, \ + "use_direct_pll_ctrl" }, /* Direct PLL control to overrule several functions for testing, */ \ + { 0xc100, \ + "enbl_tsense" }, /* Temperature sensor enable control - I2C direct mode, */ \ + { 0xc110, \ + "tsense_hibias" }, /* Bit to set the biasing in temp sensor to high - I2C direct mode, */ \ + { 0xc120, \ + "enbl_flag_vbg" }, /* Enable flagging of bandgap out of control , */ \ + { 0xc130, \ + "tap_comp_enable" }, /* Tap Comparator enable control - I2C direct mode , */ \ + { 0xc140, \ + "tap_comp_switch_enable" }, /* Tap Comparator Switch enable control - I2C direct mode, */ \ + { 0xc150, \ + "tap_comp_switch_aux_enable" }, /* Tap Comparator Switch enable control - I2C direct mode, */ \ + { 0xc161, \ + "tap_comp_test_enable" }, /* Comparator threshold - fine value , */ \ + { 0xc180, \ + "curdist_enable" }, /* Enable control - I2C direct mode , */ \ + { 0xc190, \ + "vbg2i_enbl" }, /* Enable control - I2C direct mode , */ \ + { 0xc1a0, \ + "bg_filt_bypass_enbl" }, /* Enable control , */ \ + { 0xc20f, \ + "abist_offset" }, /* Offset control for ABIST testing (two's complement), */ \ + { 0xc300, \ + "bypasslatch" }, /* Bypass latch , */ \ + { 0xc311, \ + "sourcea" }, /* Set OUTA to , */ \ + { 0xc331, \ + "sourceb" }, /* Set OUTB to , */ \ + { 0xc350, \ + "inverta" }, /* Invert pwma test signal , */ \ + { 0xc360, \ + "invertb" }, /* Invert pwmb test signal , */ \ + { 0xc374, \ + "pulselength" }, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */ \ + { 0xc3c0, \ + "tdm_enable_loopback" }, /* TDM loopback test , */ \ + { 0xc3d0, \ + "test_abistfft_enbl" }, /* FFT Coolflux , */ \ + { 0xc3e0, \ + "test_pwr_switch" }, /* Test mode for digital power switches core sw/mem sw/micvdd sw, */ \ + { 0xc400, \ + "bst_bypasslatch" }, /* Bypass latch in boost converter , */ \ + { 0xc411, \ + "bst_source" }, /* Sets the source of the pwmbst output to boost converter input for testing, */ \ + { 0xc430, \ + "bst_invertb" }, /* Invert pwmbst test signal , */ \ + { 0xc444, \ + "bst_pulselength" }, /* Pulse length setting test input for boost converter , */ \ + { 0xc490, \ + "test_bst_ctrlsthv" }, /* Test mode for boost control stage , */ \ + { 0xc4a0, \ + "test_bst_iddq" }, /* IDDQ testing in power stage of boost converter , */ \ + { 0xc4b0, \ + "test_bst_rdson" }, /* RDSON testing - boost power stage , */ \ + { 0xc4c0, \ + "test_bst_cvi" }, /* CVI testing - boost power stage , */ \ + { 0xc4d0, \ + "test_bst_ocp" }, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */ \ + { 0xc4e0, \ + "test_bst_sense" }, /* Test option for the sense NMOS in booster for current mode control., */ \ + { 0xc500, \ + "test_cvi" }, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */ \ + { 0xc510, \ + "test_discrete" }, /* Test function noise measurement , */ \ + { 0xc520, \ + "test_iddq" }, /* Set the power stages in iddq mode for gate stress., */ \ + { 0xc540, \ + "test_rdson" }, /* Analog BIST, switch to enable Rdson measurement , */ \ + { 0xc550, \ + "test_sdelta" }, /* Analog BIST, noise test , */ \ + { 0xc560, \ + "bypass_fro8" }, /* Bypass fro8 with pdm_clk , */ \ + { 0xc570, \ + "test_enbl_cs" }, /* Enable for digimux mode of current sense , */ \ + { 0xc5b0, \ + "pga_test_enable" }, /* Enable PGA test mode , */ \ + { 0xc5c0, \ + "pga_test_offset_enable" }, /* Enable PGA test offset , */ \ + { 0xc5d0, \ + "pga_test_shortinput_enable" }, /* Enable PGA test short input , */ \ + { 0xc600, \ + "enbl_pwm_dcc" }, /* Enables direct control of pwm duty cycle for DCDC power stage, */ \ + { 0xc613, \ + "pwm_dcc_cnt" }, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */ \ + { 0xc650, \ + "enbl_ldo_stress" }, /* Enable stress of internal supply voltages powerstages, */ \ + { 0xc660, \ + "enbl_powerswitch" }, /* Vddd core power switch control - overrules the manager control, */ \ + { 0xc707, \ + "digimuxa_sel" }, /* DigimuxA input selection control routed to DIO4 (see Digimux list for details), */ \ + { 0xc787, \ + "digimuxb_sel" }, /* DigimuxB input selection control routed to DIO3 (see Digimux list for details), */ \ + { 0xc807, \ + "digimuxc_sel" }, /* DigimuxC input selection control routed to TDO (see Digimux list for details), */ \ + { 0xc901, \ + "dio1_ehs" }, /* Speed/load setting for DIO1 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc921, \ + "dio2_ehs" }, /* Speed/load setting for DIO2 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc941, \ + "dio3_ehs" }, /* Speed/load setting for DIO3 cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc961, \ + "dio4_ehs" }, /* Speed/load setting for DIO4 IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc981, \ + "spdmo_ehs" }, /* Speed/load setting for PDMO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc9a1, \ + "tdo_ehs" }, /* Speed/load setting for TDM IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */ \ + { 0xc9c0, \ + "int_ehs" }, /* Slew Rate INT IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */ \ + { 0xc9d0, \ + "pdmclk_ehs" }, /* Slew RateBCK2/PDMCLK IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */ \ + { 0xc9e0, \ + "fs2_ehs" }, /* Slew Rate DS2 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */ \ + { 0xc9f0, \ + "hs_mode" }, /* I2C high speed mode control , */ \ + { 0xca00, \ + "enbl_anamux1" }, /* Enable anamux1 , */ \ + { 0xca10, \ + "enbl_anamux2" }, /* Enable anamux2 , */ \ + { 0xca20, \ + "enbl_anamux3" }, /* Enable anamux3 , */ \ + { 0xca30, \ + "enbl_anamux4" }, /* Enable anamux4 , */ \ + { 0xca74, \ + "anamux1" }, /* Anamux selection control - anamux on TEST1 , */ \ + { 0xcb04, \ + "anamux2" }, /* Anamux selection control - anamux on TEST2 , */ \ + { 0xcb54, \ + "anamux3" }, /* Anamux selection control - anamux on TEST3 , */ \ + { 0xcba4, \ + "anamux4" }, /* Anamux selection control - anamux on TEST4 , */ \ + { 0xcc05, \ + "pll_seli_lbw" }, /* PLL SELI - Low B/W PLL control mode or I2C direct PLL control mode only, */ \ + { 0xcc64, \ + "pll_selp_lbw" }, /* PLL SELP - Low B/W PLL control mode or I2C direct PLL control mode only, */ \ + { 0xccb3, \ + "pll_selr_lbw" }, /* PLL SELR - Low B/W PLL control mode or I2C direct PLL control mode only, */ \ + { 0xccf0, \ + "sel_user_pll_bw" }, /* PLL Low Bandwidth Mode control , */ \ + { 0xcdf0, \ + "pll_frm" }, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */ \ + { 0xce09, \ + "pll_ndec" }, /* PLL NDEC - I2C direct PLL control mode only , */ \ + { 0xcea0, \ + "pll_mdec_msb" }, /* MSB of pll_mdec - I2C direct PLL control mode only, */ \ + { 0xceb0, \ + "enbl_pll" }, /* Enables PLL in I2C direct PLL control mode only , */ \ + { 0xcec0, \ + "enbl_fro8" }, /* Enables FRO8M in I2C direct control mode only , */ \ + { 0xced0, \ + "pll_bypass" }, /* PLL bypass control in I2C direct PLL control mode only, */ \ + { 0xcee0, \ + "pll_directi" }, /* PLL directi control in I2C direct PLL control mode only, */ \ + { 0xcef0, \ + "pll_directo" }, /* PLL directo control in I2C direct PLL control mode only, */ \ + { 0xcf0f, \ + "pll_mdec_lsb" }, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */ \ + { 0xd006, \ + "pll_pdec" }, /* PLL PDEC - I2C direct PLL control mode only , */ \ + { 0xd10f, \ + "tsig_freq_lsb" }, /* Internal sinus test generator frequency control , */ \ + { 0xd202, \ + "tsig_freq_msb" }, /* Select internal sinus test generator, frequency control msb bits, */ \ + { 0xd230, \ + "inject_tsig" }, /* Control bit to switch to internal sinus test generator, */ \ + { 0xd283, \ + "tsig_gain" }, /* Test signal gain , */ \ + { 0xd300, \ + "adc10_reset" }, /* Reset for ADC10 - I2C direct control mode , */ \ + { 0xd311, \ + "adc10_test" }, /* Test mode selection signal for ADC10 - I2C direct control mode, */ \ + { 0xd332, \ + "adc10_sel" }, /* Select the input to convert for ADC10 - I2C direct control mode, */ \ + { 0xd364, \ + "adc10_prog_sample" }, /* ADC10 program sample setting - I2C direct control mode, */ \ + { 0xd3b0, \ + "adc10_enbl" }, /* Enable ADC10 - I2C direct control mode , */ \ + { 0xd3c0, \ + "bypass_lp_vbat" }, /* Bypass control for Low pass filter in batt sensor , */ \ + { 0xd409, \ + "data_adc10_tempbat" }, /* ADC 10 data output data for testing , */ \ + { 0xd507, \ + "ctrl_digtoana_hidden" }, /* Spare digital to analog control bits - Hidden , */ \ + { 0xd580, \ + "enbl_clk_range_chk" }, /* Clock out of range , */ \ + { 0xd601, \ + "clkdiv_dsp_sel" }, /* DSP clock divider selection in direct clock control mode, */ \ + { 0xd621, \ + "clkdiv_audio_sel" }, /* Audio clock divider selection in direct clock control mode, */ \ + { 0xd641, \ + "clkdiv_muxa_sel" }, /* DCDC MUXA clock divider selection in direct clock control mode, */ \ + { 0xd661, \ + "clkdiv_muxb_sel" }, /* DCDC MUXB clock divider selection in direct clock control mode, */ \ + { 0xd681, \ + "dsp_tap_clk" }, /* Dsp clock frequency selection in TAP mode; , */ \ + { 0xd6a1, \ + "sel_wdt_clk" }, /* Watch dog clock post divider value , */ \ + { 0xd6c1, \ + "sel_tim_clk" }, /* Timer clock post divider value , */ \ + { 0xd700, \ + "ads1_ehs" }, /* Slew Rate ADS1 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */ \ + { 0xd710, \ + "ads2_ehs" }, /* Slew Rate ADS2 IO cell, clk or data mode range (see IIC3V3 IO cell datasheet), */ \ + { 0xd822, \ + "test_parametric_io" }, /* test io parametric , */ \ + { 0xd850, \ + "ctrl_bst_clk_lp1" }, /* boost clock control in low power mode1 , */ \ + { 0xd861, \ + "test_spare_out1" }, /* test spare out 1 , */ \ + { 0xd880, \ + "bst_dcmbst" }, /* dcm boost - I2C direct mode , */ \ + { 0xd8a1, \ + "force_pga_clock" }, /* force pga clock , */ \ + { 0xd8c3, \ + "test_spare_out2" }, /* test spare out 1 , */ \ + { 0xd900, \ + "overrules_usercase" }, /* Overrule Mode control use , */ \ + { 0xd910, \ + "ovr_switch_ref" }, /* Overrule Value , */ \ + { 0xd920, \ + "ovr_enbl_pll" }, /* Overrule Value , */ \ + { 0xd930, \ + "ovr_switch_amp" }, /* Overrule Value , */ \ + { 0xd940, \ + "ovr_enbl_clk_cs" }, /* Overrule Value , */ \ + { 0xd951, \ + "ovr_sel_clk_cs" }, /* CS clock selection overrule , */ \ + { 0xd970, \ + "ovr_switch_cs" }, /* Overrule Value , */ \ + { 0xd980, \ + "ovr_enbl_csvs_ss" }, /* Overrule Value , */ \ + { 0xd990, \ + "ovr_enbl_comp" }, /* Overrule Value , */ \ + { 0xed00, \ + "enbl_fro8cal" }, /* Enable FRO calibration , */ \ + { 0xed10, \ + "start_fro8_calibration" }, /* Start FRO8 Calibration , */ \ + { 0xed20, \ + "fro8_calibration_done" }, /* FRO8 Calibration done - Read Only , */ \ + { 0xed45, \ + "fro8_auto_trim_val" }, /* Calibration value from Auto Calibration block, to be written into MTP - Read Only, */ \ + { 0xee0f, \ + "sw_profile" }, /* Software profile data , */ \ + { 0xef0f, \ + "sw_vstep" }, /* Software vstep information , */ \ + { 0xf000, \ + "calibration_onetime" }, /* Calibration schedule , */ \ + { 0xf010, \ + "calibr_ron_done" }, /* Calibration Ron executed , */ \ + { 0xf020, \ + "calibr_dcdc_api_calibrate" }, /* Calibration current limit DCDC , */ \ + { 0xf030, \ + "calibr_dcdc_delta_sign" }, /* Sign bit for delta calibration current limit DCDC , */ \ + { 0xf042, \ + "calibr_dcdc_delta" }, /* Calibration delta current limit DCDC , */ \ + { 0xf078, \ + "calibr_speaker_info" }, /* Reserved space for allowing customer to store speaker information, */ \ + { 0xf105, \ + "calibr_vout_offset" }, /* DCDC offset calibration 2's complement (key1 protected), */ \ + { 0xf163, \ + "spare_mtp1_9_6" }, /* HW gain module - left channel (2's complement) , */ \ + { 0xf1a5, \ + "spare_mtp1_15_10" }, /* Offset for amplifier, HW gain module - left channel (2's complement), */ \ + { 0xf203, \ + "calibr_gain" }, /* HW gain module (2's complement) , */ \ + { 0xf245, \ + "calibr_offset" }, /* Offset for amplifier, HW gain module (2's complement), */ \ + { 0xf2a3, \ + "spare_mtp2_13_10" }, /* Trimming of LDO (2.7V) , */ \ + { 0xf307, \ + "spare_mtp3_7_0" }, /* SPARE , */ \ + { 0xf387, \ + "calibr_gain_cs" }, /* Current sense gain (signed two's complement format), */ \ + { 0xf40f, \ + "calibr_R25C" }, /* Ron resistance of speaker coil , */ \ + { 0xf50f, \ + "spare_mtp5_15_0" }, /* SPARE , */ \ + { 0xf600, \ + "mtp_lock_enbl_coolflux" }, /* Disable function dcdcoff_mode , */ \ + { 0xf610, \ + "mtp_pwm_delay_enbl_clk_auto_gating" }, /* Auto clock gating on pwm_delay , */ \ + { 0xf620, \ + "mtp_ocp_enbl_clk_auto_gating" }, /* Auto clock gating on module ocp , */ \ + { 0xf630, \ + "mtp_disable_clk_a_gating" }, /* Disable clock_a gating , */ \ + { 0xf642, \ + "spare_mtp6_6_3" }, /* SPARE , */ \ + { 0xf686, \ + "spare_mtp6_14_8" }, /* Offset of left amplifier level shifter B , */ \ + { 0xf706, \ + "ctrl_offset_a" }, /* Offset of level shifter A , */ \ + { 0xf786, \ + "ctrl_offset_b" }, /* Offset of amplifier level shifter B , */ \ + { 0xf806, \ + "htol_iic_addr" }, /* 7-bit I2C address to be used during HTOL testing , */ \ + { 0xf870, \ + "htol_iic_addr_en" }, /* HTOL I2C address enable control , */ \ + { 0xf884, \ + "calibr_temp_offset" }, /* Temperature offset 2's compliment (key1 protected), */ \ + { 0xf8d2, \ + "calibr_temp_gain" }, /* Temperature gain 2's compliment (key1 protected) , */ \ + { 0xf910, \ + "disable_sam_mode" }, /* Disable sam mode , */ \ + { 0xf920, \ + "mtp_lock_bypass_clipper" }, /* Disable function bypass_clipper , */ \ + { 0xf930, \ + "mtp_lock_max_dcdc_voltage" }, /* Disable programming of max dcdc boost voltage , */ \ + { 0xf943, \ + "calibr_vbg_trim" }, /* Bandgap trimming control , */ \ + { 0xf987, \ + "type_bits_fw" }, /* MTP-control FW - See Firmware I2C API document for details, */ \ + { 0xfa0f, \ + "mtpdataA" }, /* MTPdataA (key1 protected) , */ \ + { 0xfb0f, \ + "mtpdataB" }, /* MTPdataB (key1 protected) , */ \ + { 0xfc0f, \ + "mtpdataC" }, /* MTPdataC (key1 protected) , */ \ + { 0xfd0f, \ + "mtpdataD" }, /* MTPdataD (key1 protected) , */ \ + { 0xfe0f, \ + "mtpdataE" }, /* MTPdataE (key1 protected) , */ \ + { 0xff05, \ + "fro8_trim" }, /* 8 MHz oscillator trim code , */ \ + { 0xff61, \ + "fro8_short_nwell_r" }, /* Short 4 or 6 n-well resistors , */ \ + { 0xff81, \ + "fro8_boost_i" }, /* Self bias current selection , */ \ + { 0xffff, "Unknown bitfield enum" } /* not found */ \ + }; + +enum tfa9912_irq { + tfa9912_irq_stvdds = 0, + tfa9912_irq_stplls = 1, + tfa9912_irq_stotds = 2, + tfa9912_irq_stovds = 3, + tfa9912_irq_stuvds = 4, + tfa9912_irq_stclks = 5, + tfa9912_irq_stmtpb = 6, + tfa9912_irq_stnoclk = 7, + tfa9912_irq_stspks = 8, + tfa9912_irq_stacs = 9, + tfa9912_irq_stsws = 10, + tfa9912_irq_stwds = 11, + tfa9912_irq_stamps = 12, + tfa9912_irq_starefs = 13, + tfa9912_irq_stadccr = 14, + tfa9912_irq_stbodnok = 15, + tfa9912_irq_stbstcu = 16, + tfa9912_irq_stbsthi = 17, + tfa9912_irq_stbstoc = 18, + tfa9912_irq_stbstpkcur = 19, + tfa9912_irq_stbstvc = 20, + tfa9912_irq_stbst86 = 21, + tfa9912_irq_stbst93 = 22, + tfa9912_irq_strcvld = 23, + tfa9912_irq_stocpl = 24, + tfa9912_irq_stocpr = 25, + tfa9912_irq_stmwsrc = 26, + tfa9912_irq_stmwcfc = 27, + tfa9912_irq_stmwsmu = 28, + tfa9912_irq_stcfmer = 29, + tfa9912_irq_stcfmac = 30, + tfa9912_irq_stclkoor = 31, + tfa9912_irq_sttdmer = 32, + tfa9912_irq_stclpl = 33, + tfa9912_irq_stclpr = 34, + tfa9912_irq_stocpm = 35, + tfa9912_irq_stlp1 = 37, + tfa9912_irq_stla = 38, + tfa9912_irq_stvddp = 39, + tfa9912_irq_sttapdet = 40, + tfa9912_irq_staudmod = 41, + tfa9912_irq_stsammod = 42, + tfa9912_irq_sttapmod = 43, + tfa9912_irq_sttaptrg = 44, + tfa9912_irq_max = 45, + tfa9912_irq_all = -1 /* all irqs */ +}; + +#define TFA9912_IRQ_NAMETABLE \ + static tfaIrqName_t Tfa9912IrqNames[] = { \ + { 0, "STVDDS" }, { 1, "STPLLS" }, { 2, "STOTDS" }, \ + { 3, "STOVDS" }, { 4, "STUVDS" }, { 5, "STCLKS" }, \ + { 6, "STMTPB" }, { 7, "STNOCLK" }, { 8, "STSPKS" }, \ + { 9, "STACS" }, { 10, "STSWS" }, { 11, "STWDS" }, \ + { 12, "STAMPS" }, { 13, "STAREFS" }, { 14, "STADCCR" }, \ + { 15, "STBODNOK" }, { 16, "STBSTCU" }, { 17, "STBSTHI" }, \ + { 18, "STBSTOC" }, { 19, "STBSTPKCUR" }, { 20, "STBSTVC" }, \ + { 21, "STBST86" }, { 22, "STBST93" }, { 23, "STRCVLD" }, \ + { 24, "STOCPL" }, { 25, "STOCPR" }, { 26, "STMWSRC" }, \ + { 27, "STMWCFC" }, { 28, "STMWSMU" }, { 29, "STCFMER" }, \ + { 30, "STCFMAC" }, { 31, "STCLKOOR" }, { 32, "STTDMER" }, \ + { 33, "STCLPL" }, { 34, "STCLPR" }, { 35, "STOCPM" }, \ + { 36, "36" }, { 37, "STLP1" }, { 38, "STLA" }, \ + { 39, "STVDDP" }, { 40, "STTAPDET" }, { 41, "STAUDMOD" }, \ + { 42, "STSAMMOD" }, { 43, "STTAPMOD" }, { 44, "STTAPTRG" }, \ + }; +#endif /* _TFA9912_TFAFIELDNAMES_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_container.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_container.h new file mode 100644 index 000000000000..5ec02468884b --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_container.h @@ -0,0 +1,379 @@ +/* + * Copyright 2013-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * tfaContainer.h + * + * Created on: Sep 11, 2013 + * Author: wim + */ + +#ifndef TFACONTAINER_H_ +#define TFACONTAINER_H_ + +/* static limits */ +#define TFACONT_MAXDEVS (4) /* maximum nr of devices */ +#define TFACONT_MAXPROFS (16) /* maximum nr of profiles */ + +#include "tfa98xx_parameters.h" + +/** +* Pass the container buffer, initialize and allocate internal memory. +* +* @param cnt pointer to the start of the buffer holding the container file +* @param length of the data in bytes +* @return +* - tfa_error_ok if normal +* - tfa_error_container invalid container data +* - tfa_error_bad_param invalid parameter +* +*/ +enum tfa_error tfa_load_cnt(void *cnt, int length); + +/** + * Return the descriptor string + * @param cnt pointer to the container struct + * @param dsc pointer to nxpTfa descriptor + * @return descriptor string + */ +char *tfaContGetString(nxpTfaContainer_t *cnt, nxpTfaDescPtr_t *dsc); + +/** + * Gets the string for the given command type number + * @param type number representing a command + * @return string of a command + */ +char *tfaContGetCommandString(uint32_t type); + +/** + * get the device type from the patch in this devicelist + * - find the patch file for this devidx + * - return the devid from the patch or 0 if not found + * @param cnt pointer to container file + * @param dev_idx device index + * @return descriptor string + */ +int tfa_cnt_get_devid(nxpTfaContainer_t *cnt, int dev_idx); + +/** + * Get the slave for the device if it exists. + * @param tfa the device struct pointer + * @param slave_addr the index of the device + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr); + +void tfaContSetSlave(uint8_t slave_addr); + +/** + * Get the index for a skave address. + * @param tfa the device struct pointer + * @return the device index + */ +int tfa_cont_get_idx(struct tfa_device *tfa); + +/** + * Write reg and bitfield items in the devicelist to the target. + * @param tfa the device struct pointer + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa); + +/** + * Write reg and bitfield items in the profilelist to the target. + * @param tfa the device struct pointer + * @param prof_idx the profile index + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx); + +/** + * Write a patchfile in the devicelist to the target. + * @param tfa the device struct pointer + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa); + +/** + * Write all param files in the devicelist to the target. + * @param tfa the device struct pointer + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa); + +/** + * Get sample rate from passed profile index + * @param tfa the device struct pointer + * @param prof_idx the index of the profile + * @return sample rate value + */ +unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa, + unsigned int prof_idx); + +/** + * Get the device name string + * @param cnt the pointer to the container struct + * @param dev_idx the index of the device + * @return device name string or error string if not found + */ +char *tfaContDeviceName(nxpTfaContainer_t *cnt, int dev_idx); + +/** + * Get the application name from the container file application field + * @param tfa the device struct pointer + * @param name the input stringbuffer with size: sizeof(application field)+1 + * @return actual string length + */ +int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name); + +/** + * Get profile index of the calibration profile + * @param tfa the device struct pointer + * @return profile index, -2 if no calibration profile is found or -1 on error + */ +int tfaContGetCalProfile(struct tfa_device *tfa); + +/** + * Is the profile a tap profile ? + * @param tfa the device struct pointer + * @param prof_idx the index of the profile + * @return 1 if the profile is a tap profile or 0 if not + */ +int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx); + +/** + * Get the name of the profile at certain index for a device in the container file + * @param cnt the pointer to the container struct + * @param dev_idx the index of the device + * @param prof_idx the index of the profile + * @return profile name string or error string if not found + */ +char *tfaContProfileName(nxpTfaContainer_t *cnt, int dev_idx, int prof_idx); + +/** + * Process all items in the profilelist + * NOTE an error return during processing will leave the device muted + * @param tfa the device struct pointer + * @param prof_idx index of the profile + * @param vstep_idx index of the vstep + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx, + int vstep_idx); + +/** + * Specify the speaker configurations (cmd id) (Left, right, both, none) + * @param dev_idx index of the device + * @param configuration name string of the configuration + */ +void tfa98xx_set_spkr_select(int dev_idx, char *configuration); + +enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa, + nxpTfaFilter_t *filter); + +/** + * Write all param files in the profilelist to the target + * this is used during startup when maybe ACS is set + * @param tfa the device struct pointer + * @param prof_idx the index of the profile + * @param vstep_idx the index of the vstep + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx, + int vstep_idx); +enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx, + int vstep_idx); +enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size, + uint8_t data[]); + +/** + * Get the device list dsc from the tfaContainer + * @param cont pointer to the tfaContainer + * @param dev_idx the index of the device + * @return device list pointer + */ +nxpTfaDeviceList_t *tfaContGetDevList(nxpTfaContainer_t *cont, int dev_idx); + +/** + * Get the Nth profile for the Nth device + * @param cont pointer to the tfaContainer + * @param dev_idx the index of the device + * @param prof_idx the index of the profile + * @return profile list pointer + */ +nxpTfaProfileList_t *tfaContGetDevProfList(nxpTfaContainer_t *cont, int dev_idx, + int prof_idx); + +/** + * Get the number of profiles for device from contaienr + * @param cont pointer to the tfaContainer + * @param dev_idx the index of the device + * @return device list pointer + */ +int tfa_cnt_get_dev_nprof(struct tfa_device *tfa); + +/** + * Get the Nth livedata for the Nth device + * @param cont pointer to the tfaContainer + * @param dev_idx the index of the device + * @param livedata_idx the index of the livedata + * @return livedata list pointer + */ +nxpTfaLiveDataList_t *tfaContGetDevLiveDataList(nxpTfaContainer_t *cont, + int dev_idx, int livedata_idx); + +/** + * Check CRC for container + * @param cont pointer to the tfaContainer + * @return error value 0 on error + */ +int tfaContCrcCheckContainer(nxpTfaContainer_t *cont); + +/** + * Get the device list pointer + * @param cnt pointer to the container struct + * @param dev_idx the index of the device + * @return pointer to device list + */ +nxpTfaDeviceList_t *tfaContDevice(nxpTfaContainer_t *cnt, int dev_idx); + +/** + * Return the pointer to the first profile in a list from the tfaContainer + * @param cont pointer to the tfaContainer + * @return pointer to first profile in profile list + */ +nxpTfaProfileList_t *tfaContGet1stProfList(nxpTfaContainer_t *cont); + +/** + * Return the pointer to the next profile in a list + * @param prof is the pointer to the profile list + * @return profile list pointer + */ +nxpTfaProfileList_t *tfaContNextProfile(nxpTfaProfileList_t *prof); + +/** + * Return the pointer to the first livedata in a list from the tfaContainer + * @param cont pointer to the tfaContainer + * @return pointer to first livedata in profile list + */ +nxpTfaLiveDataList_t *tfaContGet1stLiveDataList(nxpTfaContainer_t *cont); + +/** + * Return the pointer to the next livedata in a list + * @param livedata_idx is the pointer to the livedata list + * @return livedata list pointer + */ +nxpTfaLiveDataList_t *tfaContNextLiveData(nxpTfaLiveDataList_t *livedata_idx); + +/** + * Write a bit field + * @param tfa the device struct pointer + * @param bf bitfield to write + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa, + nxpTfaBitfield_t bf); + +/** + * Write a parameter file to the device + * @param tfa the device struct pointer + * @param file filedescriptor pointer + * @param vstep_idx index to vstep + * @param vstep_msg_idx index to vstep message + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa, + nxpTfaFileDsc_t *file, int vstep_idx, + int vstep_msg_idx); + +/** + * Get the max volume step associated with Nth profile for the Nth device + * @param tfa the device struct pointer + * @param prof_idx profile index + * @return the number of vsteps + */ +int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx); + +/** + * Get the file contents associated with the device or profile + * Search within the device tree, if not found, search within the profile + * tree. There can only be one type of file within profile or device. + * @param tfa the device struct pointer + * @param prof_idx I2C profile index in the device + * @param type file type + * @return 0 NULL if file type is not found + * @return 1 file contents + */ +nxpTfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx, + enum nxpTfaHeaderType type); + +/** + * Dump the contents of the file header + * @param hdr pointer to file header data + */ +void tfaContShowHeader(nxpTfaHeader_t *hdr); + +/** + * Read a bit field + * @param tfa the device struct pointer + * @param bf bitfield to read out + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa, + nxpTfaBitfield_t *bf); + +/** + * Get hw feature bits from container file + * @param tfa the device struct pointer + * @param hw_feature_register pointer to where hw features are stored + */ +void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register); + +/** + * Get sw feature bits from container file + * @param tfa the device struct pointer + * @param sw_feature_register pointer to where sw features are stored + */ +void get_sw_features_from_cnt(struct tfa_device *tfa, + int sw_feature_register[2]); + +/** + * Factory trimming for the Boost converter + * check if there is a correction needed + * @param tfa the device struct pointer + */ +enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa); + +/** + * Search for filters settings and if found then write them to the device + * @param tfa the device struct pointer + * @param prof_idx profile to look in + * @return Tfa98xx_Error + */ +enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx); + +/** + * Get the firmware version from the patch in the container file + * @param tfa the device struct pointer + * @return firmware version + */ +int tfa_cnt_get_patch_version(struct tfa_device *tfa); + +int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length, + const char *buffer); + +#endif /* TFACONTAINER_H_ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_device.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_device.h new file mode 100644 index 000000000000..6a878c4d5797 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_device.h @@ -0,0 +1,343 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/**\file + * + * The tfa_device interface controls a single I2C device instance by + * referencing to the device specific context provided by means of the + * tfa_device structure pointer. + * Multiple instances of tfa_device structures will be created and maintained + * by the caller. + * + * The API is functionally grouped as: + * - tfa_dev basic codec interface to probe, start/stop and control the device state + * - access to internal MTP storage + * - abstraction for interrupt bits and handling + * - container reading support + */ +#ifndef __TFA_DEVICE_H__ +#define __TFA_DEVICE_H__ + +#include "config.h" + +struct tfa_device; + +/* + * hw/sw feature bit settings in MTP + */ +enum featureSupport { + supportNotSet, /**< default means not set yet */ + supportNo, /**< no support */ + supportYes /**< supported */ +}; +/* + * supported Digital Audio Interfaces bitmap + */ +enum Tfa98xx_DAI { + Tfa98xx_DAI_I2S = 0x01, /**< I2S only */ + Tfa98xx_DAI_TDM = 0x02, /**< TDM, I2S */ + Tfa98xx_DAI_PDM = 0x04, /**< PDM */ +}; + +/* + * device ops function structure + */ +struct tfa_device_ops { + enum Tfa98xx_Error (*dsp_msg)(struct tfa_device *tfa, int length, + const char *buf); + enum Tfa98xx_Error (*dsp_msg_read)(struct tfa_device *tfa, int length, + unsigned char *bytes); + enum Tfa98xx_Error (*reg_read)(struct tfa_device *tfa, + unsigned char subaddress, + unsigned short *value); + enum Tfa98xx_Error (*reg_write)(struct tfa_device *tfa, + unsigned char subaddress, + unsigned short value); + enum Tfa98xx_Error (*mem_read)(struct tfa_device *tfa, + unsigned int start_offset, int num_words, + int *pValues); + enum Tfa98xx_Error (*mem_write)(struct tfa_device *tfa, + unsigned short address, int value, + int memtype); + + enum Tfa98xx_Error (*tfa_init)( + struct tfa_device * + tfa); /**< init typically for loading optimal settings */ + enum Tfa98xx_Error (*dsp_reset)( + struct tfa_device *tfa, + int state); /**< reset the coolflux dsp */ + enum Tfa98xx_Error (*dsp_system_stable)( + struct tfa_device *tfa, + int *ready); /**< ready when clocks are stable to allow DSP subsystem access */ + enum Tfa98xx_Error (*dsp_write_tables)( + struct tfa_device *tfa, + int sample_rate); /**< write the device/type specific delaytables */ + enum Tfa98xx_Error (*auto_copy_mtp_to_iic)( + struct tfa_device *tfa); /**< Set auto_copy_mtp_to_iic */ + enum Tfa98xx_Error (*factory_trimmer)( + struct tfa_device + *tfa); /**< Factory trimming for the Boost converter */ + int (*set_swprof)( + struct tfa_device *tfa, + unsigned short + new_value); /**< Set the sw profile in the struct and the hw register */ + int (*get_swprof)( + struct tfa_device + *tfa); /**< Get the sw profile from the hw register */ + int (*set_swvstep)( + struct tfa_device *tfa, + unsigned short + new_value); /**< Set the sw vstep in the struct and the hw register */ + int (*get_swvstep)( + struct tfa_device + *tfa); /**< Get the sw vstep from the hw register */ + int (*get_mtpb)( + struct tfa_device *tfa); /**< get status of MTB busy bit*/ + enum Tfa98xx_Error (*set_mute)(struct tfa_device *tfa, + int mute); /**< set mute */ + enum Tfa98xx_Error (*faim_protect)( + struct tfa_device *tfa, + int state); /**< Protect FAIM from being corrupted */ + enum Tfa98xx_Error (*set_osc_powerdown)( + struct tfa_device *tfa, + int state); /**< Allow to change internal osc. gating settings */ +}; + +/** + * Device states and modifier flags to allow a device/type independent fine + * grained control of the internal state.\n + * Values below 0x10 are referred to as base states which can be or-ed with + * state modifiers, from 0x10 and higher. + * + */ +enum tfa_state { + TFA_STATE_UNKNOWN, /**< unknown or invalid */ + TFA_STATE_POWERDOWN, /**< PLL in powerdown, Algo is up/warm */ + TFA_STATE_INIT_HW, /**< load I2C/PLL hardware setting (~wait2srcsettings) */ + TFA_STATE_INIT_CF, /**< coolflux HW access possible (~initcf) */ + TFA_STATE_INIT_FW, /**< DSP framework active (~patch loaded) */ + TFA_STATE_OPERATING, /**< Amp and Algo running */ + TFA_STATE_FAULT, /**< An alarm or error occurred */ + TFA_STATE_RESET, /**< I2C reset and ACS set */ + /* --sticky state modifiers-- */ + TFA_STATE_MUTE = 0x10, /**< Algo & Amp mute */ + TFA_STATE_UNMUTE = 0x20, /**< Algo & Amp unmute */ + TFA_STATE_CLOCK_ALWAYS = + 0x40, /**< PLL connect to internal oscillator */ + TFA_STATE_CLOCK_AUDIO = + 0x80, /**< PLL connect to audio clock (BCK/FS) */ + TFA_STATE_LOW_POWER = 0x100, /**< lowest possible power state */ +}; + +/** + * This is the main tfa device context structure, it will carry all information + * that is needed to handle a single I2C device instance. + * All functions dealing with the device will need access to the fields herein. + */ +struct tfa_device { + int dev_idx; /**< device container index */ + int in_use; + int buffer_size; /**< lowest level max buffer size */ + int has_msg; /**< support direct dsp messaging */ + unsigned char slave_address; /**< I2C slave address (not shifted) */ + unsigned short rev; /**< full revid of this device */ + unsigned char tfa_family; /**< tfa1/tfa2 */ + enum featureSupport supportDrc; + enum featureSupport supportFramework; + enum featureSupport support_saam; + int sw_feature_bits[2]; /**< cached copy of sw feature bits */ + int hw_feature_bits; /**< cached copy of hw feature bits */ + int profile; /**< active profile */ + int vstep; /**< active vstep */ + unsigned char spkr_count; + unsigned char spkr_select; + unsigned char support_tcoef; /**< legacy tfa9887, will be removed */ + enum Tfa98xx_DAI daimap; /**< supported audio interface types */ + int mohm[3]; /**< speaker calibration values in milli ohms -1 is error */ + struct tfa_device_ops dev_ops; + uint16_t interrupt_enable[3]; + uint16_t interrupt_status[3]; + int ext_dsp; /**< respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */ + int bus; /* TODO fix ext_dsp and bus handling */ + int tfadsp_event; /**< enum tfadsp_event_en is for external registry */ + int verbose; /**< verbosity level for debug print output */ + enum tfa_state + state; /**< last known state or-ed with optional state_modifier */ + struct nxpTfaContainer *cnt; /**< the loaded container file */ + struct nxpTfaVolumeStepRegisterInfo + *p_regInfo; /**< remember vstep for partial updates */ + int partial_enable; /**< enable partial updates */ + void *data; /**< typically pointing to Linux driver structure owning this device */ + int convert_dsp32; /**< convert 24 bit DSP messages to 32 bit */ + int sync_iv_delay; /**< synchronize I/V delay at cold start */ + int is_probus_device; /**< probus device: device without internal DSP */ + int needs_reset; /**< add the reset trigger for SetAlgoParams and SetMBDrc commands */ + struct kmem_cache *cachep; /**< Memory allocator handle */ +}; + +/** + * The tfa_dev_probe is called before accessing any device accessing functions. + * Access to the tfa device register 3 is attempted and will record the + * returned id for further use. If no device responds the function will abort. + * The recorded id will by used by the query functions to fill the remaining + * relevant data fields of the device structure. + * Data such as MTP features that requires device access will only be read when + * explicitly called and the result will be then cached in the struct. + * + * A structure pointer passed to this device needs to refer to existing memory + * space allocated by the caller. + * + * @param slave = I2C slave address of the target device (not shifted) + * @param tfa struct = points to memory that holds the context for this device + * instance + * + * @return + * - 0 if the I2C device responded to a read of register address 3\n + * when the device responds but with an unknown id a warning will be printed + * - -1 if no response from the I2C device + * + */ +int tfa_dev_probe(int slave, struct tfa_device *tfa); + +/** + * Start this instance at the profile and vstep as provided. + * The profile and vstep will be loaded first in case the current value differs + * from the requested values. + * Note that this call will not change the mute state of the tfa, which means + * that of this instance was called in muted state the caller will have to + * unmute in order to get audio. + * + * @param tfa struct = pointer to context of this device instance + * @param profile the selected profile to run + * @param vstep the selected vstep to use + * @return tfa_error enum + */ +/*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ +#ifdef __KERNEL__ +enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile, + int vstep, u8 pcm_format); +#else +enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile, + int vstep); +#endif +/*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ + +/** + * Stop audio for this instance as gracefully as possible. + * Audio will be muted and the PLL will be shutdown together with any other + * device/type specific settings needed to prevent audio artifacts or + * workarounds. + * + * Note that this call will change state of the tfa to mute and powered down. + * + * @param tfa struct = pointer to context of this device instance + * @return tfa_error enum + */ +enum tfa_error tfa_dev_stop(struct tfa_device *tfa); + +/** + * This interface allows a device/type independent fine grained control of the + * internal state of the instance. + * Whenever a base state is requested an attempt is made to actively bring the device + * into this state. However this may depend on external conditions beyond control of + * this software layer. Therefore in case the state cannot be set an erro will + * be returned and the current state remains unchanged. + * The base states, lower values below 0x10, are all mutually exclusive, they higher ones + * can also function as a sticky modifier which means for example that operating + * state could be in either muted or unmuted state. Or in case of init_cf it can be + * internal clock (always) or external audio clock. + * This function is intended to be used for device mute/unmute synchronization + * when called from higher layers. Mostly internal calls will use this to control + * the startup and profile transitions in a device/type independent way. + * + * @param tfa struct = pointer to context of this device instance + * @param state struct = desired device state after function return + * @return tfa_error enum + */ +enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state, + int is_calibration); + +/** + * Retrieve the current state of this instance in an active way. + * The state field in tfa structure will reflect the result unless an error is + * returned. + * Note that the hardware state may change on external events an as such this + * field should be treated as volatile. + * + * @param tfa struct = pointer to context of this device instance + * @return tfa_error enum + * + */ +enum tfa_state tfa_dev_get_state(struct tfa_device *tfa); + +/*****************************************************************************/ +/*****************************************************************************/ +/** + * MTP support functions + */ +enum tfa_mtp { + TFA_MTP_OTC, /**< */ + TFA_MTP_EX, /**< */ + TFA_MTP_RE25, /**< */ + TFA_MTP_RE25_PRIM, /**< */ + TFA_MTP_RE25_SEC, /**< */ + TFA_MTP_LOCK, /**< */ +}; + +/** + * + */ +int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item); + +/** + * + */ +enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item, + int value); + +//irq +/* tfa2 interrupt support + * !!! enum tfa9912_irq !!!*/ +/* + * interrupt bit function to clear + */ +int tfa_irq_clear(struct tfa_device *tfa, int bit); +/* + * return state of irq or -1 if illegal bit + */ +int tfa_irq_get(struct tfa_device *tfa, int bit); +/* + * interrupt bit function that operates on the shadow regs in the handle + */ +int tfa_irq_ena(struct tfa_device *tfa, int bit, int state); +/* + * interrupt bit function that sets the polarity + */ +int tfa_irq_set_pol(struct tfa_device *tfa, int bit, int state); + +/* + * mask interrupts by disabling them + */ +int tfa_irq_mask(struct tfa_device *tfa); +/* + * unmask interrupts by enabling them again + */ +int tfa_irq_unmask(struct tfa_device *tfa); +//cnt read +//debug? + +#endif /* __TFA_DEVICE_H__ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_dsp_fw.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_dsp_fw.h new file mode 100644 index 000000000000..c7a032cb569b --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_dsp_fw.h @@ -0,0 +1,169 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef TFA98XX_INTERNALS_H +#define TFA98XX_INTERNALS_H + +#include "config.h" + +#include "tfa_service.h" //TODO cleanup for enum Tfa98xx_Status_ID +/* + * tfadsp_fw_api.c + */ +/** + * Return a text version of the firmware status ID code + * @param status the given status ID code + * @return the firmware status ID string + */ +const char *tfadsp_fw_status_string(enum Tfa98xx_Status_ID status); +int tfadsp_fw_start(struct tfa_device *tfa, int prof_idx, int vstep_idx); +int tfadsp_fw_get_api_version(struct tfa_device *tfa, uint8_t *buffer); +#define FW_MAXTAG 150 +int tfadsp_fw_get_tag(struct tfa_device *tfa, uint8_t *buffer); +int tfadsp_fw_get_status_change(struct tfa_device *tfa, uint8_t *buffer); +int tfadsp_fw_set_re25(struct tfa_device *tfa, int prim, int sec); +int tfadsp_fw_get_re25(struct tfa_device *tfa, uint8_t *buffer); + +/* + * the order matches the ACK bits order in TFA98XX_CF_STATUS + */ +enum tfa_fw_event { /* not all available on each device */ + tfa_fw_i2c_cmd_ack, + tfa_fw_reset_start, + tfa_fw_short_on_mips, + tfa_fw_soft_mute_ready, + tfa_fw_volume_ready, + tfa_fw_error_damage, + tfa_fw_calibrate_done, + tfa_fw_max +}; + +/* the following type mappings are compiler specific */ +#define subaddress_t unsigned char + +/* module Ids */ +#define MODULE_FRAMEWORK 0 +#define MODULE_SPEAKERBOOST 1 +#define MODULE_BIQUADFILTERBANK 2 +#define MODULE_TAPTRIGGER 5 +#define MODULE_SETRE 9 + +/* RPC commands */ +/* SET */ +#define FW_PAR_ID_SET_MEMORY 0x03 +#define FW_PAR_ID_SET_SENSES_DELAY 0x04 +#define FW_PAR_ID_SETSENSESCAL 0x05 +#define FW_PAR_ID_SET_INPUT_SELECTOR 0x06 +#define FW_PAR_ID_SET_OUTPUT_SELECTOR 0x08 +#define FW_PAR_ID_SET_PROGRAM_CONFIG 0x09 +#define FW_PAR_ID_SET_GAINS 0x0A +#define FW_PAR_ID_SET_MEMTRACK 0x0B +#define FW_PAR_ID_SET_FWKUSECASE 0x11 +#define TFA1_FW_PAR_ID_SET_CURRENT_DELAY 0x03 +#define TFA1_FW_PAR_ID_SET_CURFRAC_DELAY 0x06 +/* GET */ +#define FW_PAR_ID_GET_MEMORY 0x83 +#define FW_PAR_ID_GLOBAL_GET_INFO 0x84 +#define FW_PAR_ID_GET_FEATURE_INFO 0x85 +#define FW_PAR_ID_GET_MEMTRACK 0x8B +#define FW_PAR_ID_GET_TAG 0xFF +#define FW_PAR_ID_GET_API_VERSION 0xFE +#define FW_PAR_ID_GET_STATUS_CHANGE 0x8D + +/* Load a full model into SpeakerBoost. */ +/* SET */ +#define SB_PARAM_SET_ALGO_PARAMS 0x00 +#define SB_PARAM_SET_LAGW 0x01 +#define SB_PARAM_SET_ALGO_PARAMS_WITHOUT_RESET 0x02 +#define SB_PARAM_SET_RE25C 0x05 +#define SB_PARAM_SET_LSMODEL 0x06 +#define SB_PARAM_SET_MBDRC 0x07 +#define SB_PARAM_SET_MBDRC_WITHOUT_RESET 0x08 +#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A +#define SB_PARAM_SET_DRC 0x0F +/* GET */ +#define SB_PARAM_GET_ALGO_PARAMS 0x80 +#define SB_PARAM_GET_LAGW 0x81 +#define SB_PARAM_GET_RE25C 0x85 +#define SB_PARAM_GET_LSMODEL 0x86 +#define SB_PARAM_GET_MBDRC 0x87 +#define SB_PARAM_GET_MBDRC_DYNAMICS 0x89 +#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A +#define SB_PARAM_GET_TAG 0xFF + +#define SB_PARAM_SET_EQ 0x0A /* 2 Equaliser Filters. */ +#define SB_PARAM_SET_PRESET 0x0D /* Load a preset */ +#define SB_PARAM_SET_CONFIG 0x0E /* Load a config */ +#define SB_PARAM_SET_AGCINS 0x10 +#define SB_PARAM_SET_CURRENT_DELAY 0x03 +#define SB_PARAM_GET_STATE 0xC0 +#define SB_PARAM_GET_XMODEL 0xC1 /* Gets current Excursion Model. */ +#define SB_PARAM_GET_XMODEL_COEFFS 0x8C /* Get coefficients for XModel */ +#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A /* Get excursion filters */ +#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A /* Set excursion filters */ + +/* SET: TAPTRIGGER */ +#define TAP_PARAM_SET_ALGO_PARAMS 0x01 +#define TAP_PARAM_SET_DECIMATION_PARAMS 0x02 + +/* GET: TAPTRIGGER*/ +#define TAP_PARAM_GET_ALGO_PARAMS 0x81 +#define TAP_PARAM_GET_TAP_RESULTS 0x84 + +/* sets the speaker calibration impedance (@25 degrees celsius) */ +#define SB_PARAM_SET_RE0 0x89 + +#define BFB_PAR_ID_SET_COEFS 0x00 +#define BFB_PAR_ID_GET_COEFS 0x80 +#define BFB_PAR_ID_GET_CONFIG 0x81 + +/* for compatibility */ +#define FW_PARAM_GET_STATE FW_PAR_ID_GLOBAL_GET_INFO +#define FW_PARAM_GET_FEATURE_BITS FW_PAR_ID_GET_FEATURE_BITS + +/* RPC Status results */ +#define STATUS_OK 0 +#define STATUS_INVALID_MODULE_ID 2 +#define STATUS_INVALID_PARAM_ID 3 +#define STATUS_INVALID_INFO_ID 4 + +/* the maximum message length in the communication with the DSP */ +#define TFA2_MAX_PARAM_SIZE (507 * 3) /* TFA2 */ +#define TFA1_MAX_PARAM_SIZE (145 * 3) /* TFA1 */ + +#define ROUND_DOWN(a, n) (((a) / (n)) * (n)) + +/* feature bits */ +#define FEATURE1_TCOEF 0x100 /* bit8 set means tCoefA expected */ +#define FEATURE1_DRC 0x200 /* bit9 NOT set means DRC expected */ + +/* DSP firmware xmem defines */ +#define TFA1_FW_XMEM_CALIBRATION_DONE 231 +#define TFA2_FW_XMEM_CALIBRATION_DONE 516 +#define TFA1_FW_XMEM_COUNT_BOOT 0xa1 +#define TFA2_FW_XMEM_COUNT_BOOT 512 +#define TFA2_FW_XMEM_CMD_COUNT 520 + +/* note that the following defs rely on the handle variable */ +#define TFA_FW_XMEM_CALIBRATION_DONE TFA_FAM_FW(tfa, XMEM_CALIBRATION_DONE) +#define TFA_FW_XMEM_COUNT_BOOT TFA_FAM_FW(tfa, XMEM_COUNT_BOOT) +#define TFA_FW_XMEM_CMD_COUNT TFA_FAM_FW(tfa, XMEM_CMD_COUNT) + +#define TFA2_FW_ReZ_SCALE 65536 +#define TFA1_FW_ReZ_SCALE 16384 + +#endif /* TFA98XX_INTERNALS_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_ext.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_ext.h new file mode 100644 index 000000000000..9d0c2ddce12b --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_ext.h @@ -0,0 +1,64 @@ +/* + * Copyright 2016-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * tfa_ext.h + * + * Created on: Jun 8, 2016 + * Author: wim + */ + +#ifndef TFA_SRC_TFA_EXT_H_ +#define TFA_SRC_TFA_EXT_H_ + +#include "tfa_device.h" + +/* + * events + */ +/** Maximum value for enumerator */ +#define LVM_MAXENUM (0xffff) +/** +This enum type specifies the different events that may trigger a callback. +*/ +enum tfadsp_event_en { + TFADSP_CMD_ACK = 1, /**< Command handling is completed */ + TFADSP_SOFT_MUTE_READY = 8, /**< Muting completed */ + TFADSP_VOLUME_READY = 16, /**< Volume change completed */ + TFADSP_DAMAGED_SPEAKER = 32, /**< Damaged speaker was detected */ + TFADSP_CALIBRATE_DONE = 64, /**< Calibration is completed */ + TFADSP_SPARSESIG_DETECTED = 128, /**< Sparse signal detected */ + TFADSP_CMD_READY = 256, /**< Ready to receive commands */ + TFADSP_EXT_PWRUP = 0x8000, /**< DSP API has started, powered up */ + TFADSP_EXT_PWRDOWN = 0x8001, /**< DSP API stopped, power down */ + TFADSP_EVENT_DUMMY = LVM_MAXENUM +}; + +typedef int (*tfa_event_handler_t)(struct tfa_device *tfa, + enum tfadsp_event_en tfadsp_event); +typedef int (*dsp_send_message_t)(struct tfa_device *tfa, int length, + const char *buf); +typedef int (*dsp_read_message_t)(struct tfa_device *tfa, int length, + char *buf); +typedef int (*dsp_write_reg_t)(struct tfa_device *tfa, unsigned char subaddress, + unsigned short value); + +int tfa_ext_register(dsp_write_reg_t tfa_write_reg, + dsp_send_message_t tfa_send_message, + dsp_read_message_t tfa_read_message, + tfa_event_handler_t *tfa_event_handler); + +#endif /* TFA_SRC_TFA_EXT_H_ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_internal.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_internal.h new file mode 100644 index 000000000000..4f7094d13d3a --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_internal.h @@ -0,0 +1,41 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + internal functions for TFA layer (not shared with SRV and HAL layer!) +*/ + +#ifndef __TFA_INTERNAL_H__ +#define __TFA_INTERNAL_H__ + +#include "tfa_dsp_fw.h" +#include "tfa_ext.h" + +#if __GNUC__ >= 4 +#define TFA_INTERNAL __attribute__((visibility("hidden"))) +#else +#define TFA_INTERNAL +#endif + +#define TFA98XX_GENERIC_SLAVE_ADDRESS 0x1C + +TFA_INTERNAL enum Tfa98xx_Error tfa98xx_check_rpc_status(struct tfa_device *tfa, + int *pRpcStatus); +TFA_INTERNAL enum Tfa98xx_Error tfa98xx_wait_result(struct tfa_device *tfa, + int waitRetryCount); + +#endif /* __TFA_INTERNAL_H__ */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_platform_interface_definition.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_platform_interface_definition.h new file mode 100644 index 000000000000..7cf3c68b01bd --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_platform_interface_definition.h @@ -0,0 +1,97 @@ +/* + * Copyright 2015-2018 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _TFA_PLATFORM_INTERFACE_DEFINITION_H_ +#define _TFA_PLATFORM_INTERFACE_DEFINITION_H_ + +#define AFE_MODULE_ID_TFADSP_RX (0x1000B911) +#define AFE_MODULE_ID_TFADSP_TX (0x1000B912) +#define AFE_PARAM_ID_TFADSP_TX_SET_ENABLE (0x1000B920) +#define AFE_PARAM_ID_TFADSP_RX_CFG (0x1000B921) +#define AFE_PARAM_ID_TFADSP_RX_GET_RESULT (0x1000B922) +#define AFE_PARAM_ID_TFADSP_RX_SET_BYPASS (0x1000B923) + +#define TFA_USING_QUATERNARY_MI2S + +#if defined(TFA_USING_SECONDARY_MI2S) +/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX, + AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/ +#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_SECONDARY_MI2S_RX) +#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_SECONDARY_MI2S_TX) + +#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "SEC_MI2S_RX" +#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "SEC_MI2S_TX" +#define PLATFORM_RX_VI_FB_MUX_NAME "SECONDARY_MI2S_RX_VI_FB_MUX" +#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_SECONDARY_MI2S_TX +#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_SECONDARY_MI2S_RX + +#define TFA_TX_HOSTLESS_CODEC_NAME "Secondary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_STREAM_NAME "Secondary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_CPU_DAI_NAME "SEC_MI2S_TX_HOSTLESS" + +#elif defined(TFA_USING_TERTIARY_MI2S) +/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX, + AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/ +#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_TERTIARY_MI2S_RX) +#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_TERTIARY_MI2S_TX) + +#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "TERT_MI2S_RX" +#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "TERT_MI2S_TX" +#define PLATFORM_RX_VI_FB_MUX_NAME "TERTIARY_MI2S_RX_VI_FB_MUX" +#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_TERTIARY_MI2S_TX +#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_TERTIARY_MI2S_RX + +#define TFA_TX_HOSTLESS_CODEC_NAME "Tertiary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_STREAM_NAME "Tertiary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_CPU_DAI_NAME "TERT_MI2S_TX_HOSTLESS" + +#elif defined(TFA_USING_QUATERNARY_MI2S) +/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX, + AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/ +#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUATERNARY_MI2S_RX) +#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUATERNARY_MI2S_TX) + +#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUAT_MI2S_RX" +#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUAT_MI2S_TX" +#define PLATFORM_RX_VI_FB_MUX_NAME "QUATERNARY_MI2S_RX_VI_FB_MUX" +#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUATERNARY_MI2S_TX +#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUATERNARY_MI2S_RX + +#define TFA_TX_HOSTLESS_CODEC_NAME "Quaternary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_STREAM_NAME "Quaternary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUAT_MI2S_TX_HOSTLESS" + +#elif defined(TFA_USING_QUINARY_MI2S) +/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX, + AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/ +#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUINARY_MI2S_RX) +#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUINARY_MI2S_TX) + +#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUIN_MI2S_RX" +#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUIN_MI2S_TX" +#define PLATFORM_RX_VI_FB_MUX_NAME "QUINARY_MI2S_RX_VI_FB_MUX" +#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUINARY_MI2S_TX +#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUINARY_MI2S_RX + +#define TFA_TX_HOSTLESS_CODEC_NAME "Quinary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_STREAM_NAME "Quinary MI2S_TX Hostless" +#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUIN_MI2S_TX_HOSTLESS" + +#else +#error you should define which mi2s will be used for TFA device. +#endif +#endif /* _TFA_PLATFORM_INTERFACE_DEFINITION_H_ */ \ No newline at end of file diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_service.h b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_service.h new file mode 100644 index 000000000000..3fbd938380b5 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/tfa_service.h @@ -0,0 +1,1057 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef TFA_SERVICE_H +#define TFA_SERVICE_H + +//#include "config.h" +// workaround for Visual Studio: +// fatal error C1083: Cannot open include file: 'config.h': No such file or directory +#ifdef __KERNEL__ +#include +#else +#include +#endif +#ifdef __cplusplus +extern "C" { +#include "NXP_I2C.h" +#endif + +/* Linux kernel module defines TFA98XX_GIT_VERSIONS in the linux_driver/Makefile */ +#if !defined(TFA98XX_GIT_VERSIONS) +#include "versions.h" +#endif +#ifdef TFA98XX_GIT_VERSIONS +#define TFA98XX_API_REV_STR TFA98XX_GIT_VERSIONS +#else +#define TFA98XX_API_REV_STR "v6.5.2" +#endif + +#include "tfa_device.h" + +/* + * data previously defined in Tfa9888_dsp.h + */ +#define MEMTRACK_MAX_WORDS 150 +#define LSMODEL_MAX_WORDS 150 +#define TFA98XX_MAXTAG (150) +#define FW_VAR_API_VERSION (521) + +/* Indexes and scaling factors of GetLSmodel */ +#define tfa9888_fs_IDX 128 +#define tfa9888_leakageFactor_IDX 130 +#define tfa9888_ReCorrection_IDX 131 +#define tfa9888_Bl_IDX 132 +#define ReZ_IDX 147 + +#define tfa9872_leakageFactor_IDX 128 +#define tfa9872_ReCorrection_IDX 129 +#define tfa9872_Bl_IDX 130 + +#define fs_SCALE (double)1 +#define leakageFactor_SCALE (double)8388608 +#define ReCorrection_SCALE (double)8388608 +#define Bl_SCALE (double)2097152 +#define tCoef_SCALE (double)8388608 + +/* ---------------------------- Max1 ---------------------------- */ +/* Headroom applied to the main input signal */ +#define SPKRBST_HEADROOM 7 +/* Exponent used for AGC Gain related variables */ +#define SPKRBST_AGCGAIN_EXP SPKRBST_HEADROOM +#define SPKRBST_TEMPERATURE_EXP 9 +/* Exponent used for Gain Corection related variables */ +#define SPKRBST_LIMGAIN_EXP 4 +#define SPKRBST_TIMECTE_EXP 1 +#define DSP_MAX_GAIN_EXP 7 +/* -------------------------------------------------------------- */ + +/* speaker related parameters */ +#define TFA2_SPEAKERPARAMETER_LENGTH (3 * 151) /* MAX2=450 */ +#define TFA1_SPEAKERPARAMETER_LENGTH (3 * 141) /* MAX1=423 */ + +/* vstep related parameters */ +#define TFA2_ALGOPARAMETER_LENGTH \ + (3 * 304) /* N1B = (304) 305 is including the cmd-id */ +#define TFA72_ALGOPARAMETER_LENGTH_MONO (3 * 183) +#define TFA72_ALGOPARAMETER_LENGTH_STEREO (3 * 356) +#define TFA2_MBDRCPARAMETER_LENGTH (3 * 152) /* 154 is including the cmd-id */ +#define TFA72_MBDRCPARAMETER_LENGTH (3 * 98) +#define TFA1_PRESET_LENGTH 87 +#define TFA1_DRC_LENGTH 381 /* 127 words */ +#define TFA2_FILTERCOEFSPARAMETER_LENGTH \ + (3 * 168) /* 170 is including the cmd-id */ +#define TFA72_FILTERCOEFSPARAMETER_LENGTH (3 * 156) + +/* Maximum number of retries for DSP result + * Keep this value low! + * If certain calls require longer wait conditions, the + * application should poll, not the API + * The total wait time depends on device settings. Those + * are application specific. + */ +#define TFA98XX_WAITRESULT_NTRIES 40 +#define TFA98XX_WAITRESULT_NTRIES_LONG 2000 + +/* following lengths are in bytes */ +#define TFA98XX_PRESET_LENGTH 87 +#define TFA98XX_CONFIG_LENGTH 201 +#define TFA98XX_DRC_LENGTH 381 /* 127 words */ + +typedef unsigned char Tfa98xx_Config_t[TFA98XX_CONFIG_LENGTH]; +typedef unsigned char Tfa98xx_Preset_t[TFA98XX_PRESET_LENGTH]; +typedef unsigned char Tfa98xx_DrcParameters_t[TFA98XX_DRC_LENGTH]; + +/* Type containing all the possible errors that can occur + * + */ +enum Tfa98xx_Error { + Tfa98xx_Error_Ok = 0, + Tfa98xx_Error_Device, /* 1. Currently only used to keep in sync with tfa_error */ + Tfa98xx_Error_Bad_Parameter, /* 2. */ + Tfa98xx_Error_Fail, /* 3. generic failure, avoid mislead message */ + Tfa98xx_Error_NoClock, /* 4. no clock detected */ + Tfa98xx_Error_StateTimedOut, /* 5. */ + Tfa98xx_Error_DSP_not_running, /* 6. communication with the DSP failed */ + Tfa98xx_Error_AmpOn, /* 7. amp is still running */ + Tfa98xx_Error_NotOpen, /* 8. the given handle is not open */ + Tfa98xx_Error_InUse, /* 9. too many handles */ + Tfa98xx_Error_Buffer_too_small, /* 10. if a buffer is too small */ + /* the expected response did not occur within the expected time */ + Tfa98xx_Error_RpcBase = 100, + Tfa98xx_Error_RpcBusy = 101, + Tfa98xx_Error_RpcModId = 102, + Tfa98xx_Error_RpcParamId = 103, + Tfa98xx_Error_RpcInvalidCC = 104, + Tfa98xx_Error_RpcInvalidSeq = 105, + Tfa98xx_Error_RpcInvalidParam = 106, + Tfa98xx_Error_RpcBufferOverflow = 107, + Tfa98xx_Error_RpcCalibBusy = 108, + Tfa98xx_Error_RpcCalibFailed = 109, + Tfa98xx_Error_Not_Implemented, + Tfa98xx_Error_Not_Supported, + Tfa98xx_Error_I2C_Fatal, /* Fatal I2C error occurred */ + /* Nonfatal I2C error, and retry count reached */ + Tfa98xx_Error_I2C_NonFatal, + Tfa98xx_Error_Other = 1000 +}; + +/* + * Type containing all the possible msg returns DSP can give + * //TODO move to tfa_dsp_fw.h + */ +enum Tfa98xx_Status_ID { + Tfa98xx_DSP_Not_Running = -1, /* No response from DSP */ + Tfa98xx_I2C_Req_Done = + 0, /* Request executed correctly and result, if any, is available for download */ + Tfa98xx_I2C_Req_Busy = + 1, /* Request is being processed, just wait for result */ + Tfa98xx_I2C_Req_Invalid_M_ID = + 2, /* Provided M-ID does not fit in valid rang [0..2] */ + Tfa98xx_I2C_Req_Invalid_P_ID = + 3, /* Provided P-ID isn�t valid in the given M-ID context */ + Tfa98xx_I2C_Req_Invalid_CC = + 4, /* Invalid channel configuration bits (SC|DS|DP|DC) combination */ + Tfa98xx_I2C_Req_Invalid_Seq = + 5, /* Invalid sequence of commands, in case the DSP expects some commands in a specific order */ + Tfa98xx_I2C_Req_Invalid_Param = 6, /* Generic error */ + Tfa98xx_I2C_Req_Buffer_Overflow = + 7, /* I2C buffer has overflowed: host has sent too many parameters, memory integrity is not guaranteed */ + Tfa98xx_I2C_Req_Calib_Busy = 8, /* Calibration not finished */ + Tfa98xx_I2C_Req_Calib_Failed = 9 /* Calibration failed */ +}; + +/* + * speaker as microphone + */ +enum Tfa98xx_saam { + Tfa98xx_saam_none, /*< SAAM feature not available */ + Tfa98xx_saam /*< SAAM feature available */ +}; + +/* + * config file subtypes + */ +enum Tfa98xx_config_type { + Tfa98xx_config_generic, + Tfa98xx_config_sub1, + Tfa98xx_config_sub2, + Tfa98xx_config_sub3, +}; + +enum Tfa98xx_AmpInputSel { + Tfa98xx_AmpInputSel_I2SLeft, + Tfa98xx_AmpInputSel_I2SRight, + Tfa98xx_AmpInputSel_DSP +}; + +enum Tfa98xx_OutputSel { + Tfa98xx_I2SOutputSel_CurrentSense, + Tfa98xx_I2SOutputSel_DSP_Gain, + Tfa98xx_I2SOutputSel_DSP_AEC, + Tfa98xx_I2SOutputSel_Amp, + Tfa98xx_I2SOutputSel_DataI3R, + Tfa98xx_I2SOutputSel_DataI3L, + Tfa98xx_I2SOutputSel_DcdcFFwdCur, +}; + +enum Tfa98xx_StereoGainSel { + Tfa98xx_StereoGainSel_Left, + Tfa98xx_StereoGainSel_Right +}; + +#define TFA98XX_MAXPATCH_LENGTH (3 * 1024) + +/* the number of biquads supported */ +#define TFA98XX_BIQUAD_NUM 10 + +enum Tfa98xx_Channel { + Tfa98xx_Channel_L, + Tfa98xx_Channel_R, + Tfa98xx_Channel_L_R, + Tfa98xx_Channel_Stereo +}; + +enum Tfa98xx_Mode { Tfa98xx_Mode_Normal = 0, Tfa98xx_Mode_RCV }; + +enum Tfa98xx_Mute { + Tfa98xx_Mute_Off, + Tfa98xx_Mute_Digital, + Tfa98xx_Mute_Amplifier +}; + +enum Tfa98xx_SpeakerBoostStatusFlags { + Tfa98xx_SpeakerBoost_Activity = 0, /* Input signal activity. */ + Tfa98xx_SpeakerBoost_S_Ctrl, /* S Control triggers the limiter */ + Tfa98xx_SpeakerBoost_Muted, /* 1 when signal is muted */ + Tfa98xx_SpeakerBoost_X_Ctrl, /* X Control triggers the limiter */ + Tfa98xx_SpeakerBoost_T_Ctrl, /* T Control triggers the limiter */ + Tfa98xx_SpeakerBoost_NewModel, /* New model is available */ + Tfa98xx_SpeakerBoost_VolumeRdy, /* 0:stable vol, 1:still smoothing */ + Tfa98xx_SpeakerBoost_Damaged, /* Speaker Damage detected */ + Tfa98xx_SpeakerBoost_SignalClipping /* input clipping detected */ +}; + +struct Tfa98xx_DrcStateInfo { + float GRhighDrc1[2]; + float GRhighDrc2[2]; + float GRmidDrc1[2]; + float GRmidDrc2[2]; + float GRlowDrc1[2]; + float GRlowDrc2[2]; + float GRpostDrc1[2]; + float GRpostDrc2[2]; + float GRblDrc[2]; +}; +struct Tfa98xx_StateInfo { + /* SpeakerBoost State */ + float agcGain; /* Current AGC Gain value */ + float limGain; /* Current Limiter Gain value */ + float sMax; /* Current Clip/Lim threshold */ + int T; /* Current Speaker Temperature value */ + int statusFlag; /* Masked bit word */ + float X1; /* estimated excursion caused by Spkrboost gain ctrl */ + float X2; /* estimated excursion caused by manual gain setting */ + float Re; /* Loudspeaker blocked resistance */ + /* Framework state */ + /* increments each time a MIPS problem is detected on the DSP */ + int shortOnMips; + struct Tfa98xx_DrcStateInfo drcState; /* DRC state, when enabled */ +}; + +typedef struct nxpTfaMsg { + uint8_t msg_size; + unsigned char cmdId[3]; + int data[9]; +} nxpTfaMsg_t; + +typedef struct nxp_vstep_msg { + int fw_version; + uint8_t no_of_vsteps; + uint16_t reg_no; + uint8_t *msg_reg; + uint8_t msg_no; + uint32_t algo_param_length; + uint8_t *msg_algo_param; + uint32_t filter_coef_length; + uint8_t *msg_filter_coef; + uint32_t mbdrc_length; + uint8_t *msg_mbdrc; +} nxp_vstep_msg_t; + +typedef struct nxpTfaGroup { + uint8_t msg_size; + uint8_t profileId[64]; +} nxpTfaGroup_t; + +struct nxpTfa98xx_Memtrack_data { + int length; + float mValues[MEMTRACK_MAX_WORDS]; + int mAdresses[MEMTRACK_MAX_WORDS]; + int trackers[MEMTRACK_MAX_WORDS]; + int scalingFactor[MEMTRACK_MAX_WORDS]; +}; + +/* possible memory values for DMEM in CF_CONTROLs */ +enum Tfa98xx_DMEM { + Tfa98xx_DMEM_ERR = -1, + Tfa98xx_DMEM_PMEM = 0, + Tfa98xx_DMEM_XMEM = 1, + Tfa98xx_DMEM_YMEM = 2, + Tfa98xx_DMEM_IOMEM = 3, +}; + +/** + * lookup the device type and return the family type + */ +int tfa98xx_dev2family(int dev_type); + +/** + * register definition structure + */ +struct regdef { + unsigned char offset; /**< subaddress offset */ + unsigned short pwronDefault; /**< register contents after poweron */ + unsigned short pwronTestmask; /**< mask of bits not test */ + char *name; /**< short register name */ +}; + +enum Tfa98xx_DMEM tfa98xx_filter_mem(struct tfa_device *tfa, int filter_index, + unsigned short *address, int channel); + +/** + * Load the default HW settings in the device + * @param tfa the device struct pointer + */ +enum Tfa98xx_Error tfa98xx_init(struct tfa_device *tfa); + +/** + * If needed, this function can be used to get a text version of the status ID code + * @param status the given status ID code + * @return the I2C status ID string + */ +const char *tfa98xx_get_i2c_status_id_string(int status); + +/* control the powerdown bit + * @param tfa the device struct pointer + * @param powerdown must be 1 or 0 + */ +enum Tfa98xx_Error tfa98xx_powerdown(struct tfa_device *tfa, int powerdown); + +/* indicates on which channel of DATAI2 the gain from the IC is set + * @param tfa the device struct pointer + * @param gain_sel, see Tfa98xx_StereoGainSel_t + */ +enum Tfa98xx_Error +tfa98xx_select_stereo_gain_channel(struct tfa_device *tfa, + enum Tfa98xx_StereoGainSel gain_sel); + +/** + * set the mtp with user controllable values + * @param tfa the device struct pointer + * @param value to be written + * @param mask to be applied toi the bits affected + */ +enum Tfa98xx_Error tfa98xx_set_mtp(struct tfa_device *tfa, uint16_t value, + uint16_t mask); +enum Tfa98xx_Error tfa98xx_get_mtp(struct tfa_device *tfa, uint16_t *value); + +/** + * lock or unlock KEY2 + * lock = 1 will lock + * lock = 0 will unlock + * note that on return all the hidden key will be off + */ +void tfa98xx_key2(struct tfa_device *tfa, int lock); + +int tfa_calibrate(struct tfa_device *tfa); +void tfa98xx_set_exttemp(struct tfa_device *tfa, short ext_temp); +short tfa98xx_get_exttemp(struct tfa_device *tfa); + +/* control the volume of the DSP + * @param vol volume in bit field. It must be between 0 and 255 + */ +enum Tfa98xx_Error tfa98xx_set_volume_level(struct tfa_device *tfa, + unsigned short vol); + +/* set the input channel to use + * @param channel see Tfa98xx_Channel_t enumeration + */ +enum Tfa98xx_Error tfa98xx_select_channel(struct tfa_device *tfa, + enum Tfa98xx_Channel channel); + +/* set the mode for normal or receiver mode + * @param mode see Tfa98xx_Mode enumeration + */ +enum Tfa98xx_Error tfa98xx_select_mode(struct tfa_device *tfa, + enum Tfa98xx_Mode mode); + +/* mute/unmute the audio + * @param mute see Tfa98xx_Mute_t enumeration + */ +enum Tfa98xx_Error tfa98xx_set_mute(struct tfa_device *tfa, + enum Tfa98xx_Mute mute); + +/* + * tfa_supported_speakers - required for SmartStudio initialization + * returns the number of the supported speaker count + */ +enum Tfa98xx_Error tfa_supported_speakers(struct tfa_device *tfa, + int *spkr_count); + +/** +* Return the tfa revision +*/ +void tfa98xx_rev(int *major, int *minor, int *revision); + +/* + * Return the feature bits from MTP and cnt file for comparison + */ +enum Tfa98xx_Error tfa98xx_compare_features(struct tfa_device *tfa, + int features_from_MTP[3], + int features_from_cnt[3]); + +/* + * return feature bits + */ +enum Tfa98xx_Error tfa98xx_dsp_get_sw_feature_bits(struct tfa_device *tfa, + int features[2]); +enum Tfa98xx_Error tfa98xx_dsp_get_hw_feature_bits(struct tfa_device *tfa, + int *features); + +/* + * tfa98xx_supported_saam + * returns the speaker as microphone feature + * @param saam enum pointer + * @return error code + */ +enum Tfa98xx_Error tfa98xx_supported_saam(struct tfa_device *tfa, + enum Tfa98xx_saam *saam); + +/* load the tables to the DSP + * called after patch load is done + * @return error code + */ +enum Tfa98xx_Error tfa98xx_dsp_write_tables(struct tfa_device *tfa, + int sample_rate); + +/* set or clear DSP reset signal + * @param new state + * @return error code + */ +enum Tfa98xx_Error tfa98xx_dsp_reset(struct tfa_device *tfa, int state); + +/* check the state of the DSP subsystem + * return ready = 1 when clocks are stable to allow safe DSP subsystem access + * @param tfa the device struct pointer + * @param ready pointer to state flag, non-zero if clocks are not stable + * @return error code + */ +enum Tfa98xx_Error tfa98xx_dsp_system_stable(struct tfa_device *tfa, + int *ready); + +enum Tfa98xx_Error tfa98xx_auto_copy_mtp_to_iic(struct tfa_device *tfa); + +/** + * check the state of the DSP coolflux + * @param tfa the device struct pointer + * @return the value of CFE + */ +int tfa_cf_enabled(struct tfa_device *tfa); + +/* The following functions can only be called when the DSP is running + * - I2S clock must be active, + * - IC must be in operating mode + */ + +/** + * patch the ROM code of the DSP + * @param tfa the device struct pointer + * @param patchLength the number of bytes of patchBytes + * @param patchBytes pointer to the bytes to patch + */ +enum Tfa98xx_Error tfa_dsp_patch(struct tfa_device *tfa, int patchLength, + const unsigned char *patchBytes); + +/** + * load explicitly the speaker parameters in case of free speaker, + * or when using a saved speaker model + */ +enum Tfa98xx_Error +tfa98xx_dsp_write_speaker_parameters(struct tfa_device *tfa, int length, + const unsigned char *pSpeakerBytes); + +/** + * read the speaker parameters as used by the SpeakerBoost processing + */ +enum Tfa98xx_Error +tfa98xx_dsp_read_speaker_parameters(struct tfa_device *tfa, int length, + unsigned char *pSpeakerBytes); + +/** + * read the current status of the DSP, typically used for development, + * not essential to be used in a product + */ +enum Tfa98xx_Error tfa98xx_dsp_get_state_info(struct tfa_device *tfa, + unsigned char bytes[], + unsigned int *statesize); + +/** + * Check whether the DSP supports DRC + * pbSupportDrc=1 when DSP supports DRC, + * pbSupportDrc=0 when DSP doesn't support it + */ +enum Tfa98xx_Error tfa98xx_dsp_support_drc(struct tfa_device *tfa, + int *pbSupportDrc); + +enum Tfa98xx_Error tfa98xx_dsp_support_framework(struct tfa_device *tfa, + int *pbSupportFramework); + +/** + * read the speaker excursion model as used by SpeakerBoost processing + */ +enum Tfa98xx_Error +tfa98xx_dsp_read_excursion_model(struct tfa_device *tfa, int length, + unsigned char *pSpeakerBytes); + +/** + * load all the parameters for a preset from a file + */ +enum Tfa98xx_Error tfa98xx_dsp_write_preset(struct tfa_device *tfa, int length, + const unsigned char *pPresetBytes); + +/** + * wrapper for dsp_msg that adds opcode and only writes + */ +enum Tfa98xx_Error tfa_dsp_cmd_id_write(struct tfa_device *tfa, + unsigned char module_id, + unsigned char param_id, int num_bytes, + const unsigned char data[]); + +/** + * wrapper for dsp_msg that writes opcode and reads back the data + */ +enum Tfa98xx_Error tfa_dsp_cmd_id_write_read(struct tfa_device *tfa, + unsigned char module_id, + unsigned char param_id, + int num_bytes, + unsigned char data[]); + +/** + * wrapper for dsp_msg that adds opcode and 3 bytes required for coefs + */ +enum Tfa98xx_Error tfa_dsp_cmd_id_coefs(struct tfa_device *tfa, + unsigned char module_id, + unsigned char param_id, int num_bytes, + unsigned char data[]); + +/** + * wrapper for dsp_msg that adds opcode and 3 bytes required for MBDrcDynamics + */ +enum Tfa98xx_Error +tfa_dsp_cmd_id_MBDrc_dynamics(struct tfa_device *tfa, unsigned char module_id, + unsigned char param_id, int index_subband, + int num_bytes, unsigned char data[]); + +/** + * Disable a certain biquad. + * @param tfa the device struct pointer + * @param biquad_index: 1-10 of the biquad that needs to be adressed +*/ +enum Tfa98xx_Error Tfa98xx_DspBiquad_Disable(struct tfa_device *tfa, + int biquad_index); + +/** + * fill the calibration value as milli ohms in the struct + * assume that the device has been calibrated + */ +enum Tfa98xx_Error tfa_dsp_get_calibration_impedance(struct tfa_device *tfa); + +/* + * return the mohm value + */ +int tfa_get_calibration_info(struct tfa_device *tfa, int channel); + +/* + * return sign extended tap pattern + */ +int tfa_get_tap_pattern(struct tfa_device *tfa); + +/** + * Reads a number of words from dsp memory + * @param tfa the device struct pointer + * @param subaddress write address to set in address register + * @param pValue pointer to read data +*/ +enum Tfa98xx_Error tfa98xx_read_register16(struct tfa_device *tfa, + unsigned char subaddress, + unsigned short *pValue); + +/** + * Reads a number of words from dsp memory + * @param tfa the device struct pointer + * @param subaddress write address to set in address register + * @param value value to write int the memory +*/ +enum Tfa98xx_Error tfa98xx_write_register16(struct tfa_device *tfa, + unsigned char subaddress, + unsigned short value); + +/** + * Intialise the dsp + * @param tfa the device struct pointer + * @return tfa error enum +*/ +enum Tfa98xx_Error tfa98xx_init_dsp(struct tfa_device *tfa); + +/** + * Get the status of the external DSP + * @param tfa the device struct pointer + * @return status +*/ +int tfa98xx_get_dsp_status(struct tfa_device *tfa); + +/** + * Write a command message (RPC) to the dsp + * @param tfa the device struct pointer + * @param num_bytes command buffer size in bytes + * @param command_buffer + * @return tfa error enum +*/ +enum Tfa98xx_Error tfa98xx_write_dsp(struct tfa_device *tfa, int num_bytes, + const char *command_buffer); + +/** + * Read the result from the last message from the dsp + * @param tfa the device struct pointer + * @param num_bytes result buffer size in bytes + * @param result_buffer + * @return tfa error enum +*/ +enum Tfa98xx_Error tfa98xx_read_dsp(struct tfa_device *tfa, int num_bytes, + unsigned char *result_buffer); + +/** + * Write a command message (RPC) to the dsp and return the result + * @param tfa the device struct pointer + * @param command_length command buffer size in bytes + * @param command_buffer command buffer + * @param result_length result buffer size in bytes + * @param result_buffer result buffer + * @return tfa error enum +*/ +enum Tfa98xx_Error tfa98xx_writeread_dsp(struct tfa_device *tfa, + int command_length, + void *command_buffer, + int result_length, + void *result_buffer); + +/** + * Reads a number of words from dsp memory + * @param tfa the device struct pointer + * @param start_offset offset from where to start reading + * @param num_words number of words to read + * @param pValues pointer to read data +*/ +enum Tfa98xx_Error tfa98xx_dsp_read_mem(struct tfa_device *tfa, + unsigned int start_offset, + int num_words, int *pValues); +/** + * Write a value to dsp memory + * @param tfa the device struct pointer + * @param address write address to set in address register + * @param value value to write int the memory + * @param memtype type of memory to write to +*/ +enum Tfa98xx_Error tfa98xx_dsp_write_mem_word(struct tfa_device *tfa, + unsigned short address, int value, + int memtype); + +/** + * Read data from dsp memory + * @param tfa the device struct pointer + * @param subaddress write address to set in address register + * @param num_bytes number of bytes to read from dsp + * @param data the unsigned char buffer to read data into +*/ +enum Tfa98xx_Error tfa98xx_read_data(struct tfa_device *tfa, + unsigned char subaddress, int num_bytes, + unsigned char data[]); + +/** + * Write all the bytes specified by num_bytes and data to dsp memory + * @param tfa the device struct pointer + * @param subaddress the subaddress to write to + * @param num_bytes number of bytes to write + * @param data actual data to write +*/ +enum Tfa98xx_Error tfa98xx_write_data(struct tfa_device *tfa, + unsigned char subaddress, int num_bytes, + const unsigned char data[]); + +enum Tfa98xx_Error tfa98xx_write_raw(struct tfa_device *tfa, int num_bytes, + const unsigned char data[]); + +/* support for converting error codes into text */ +const char *tfa98xx_get_error_string(enum Tfa98xx_Error error); + +/** + * convert signed 24 bit integers to 32bit aligned bytes + * input: data contains "num_bytes/3" int24 elements + * output: bytes contains "num_bytes" byte elements + * @param num_data length of the input data array + * @param data input data as integer array + * @param bytes output data as unsigned char array +*/ +void tfa98xx_convert_data2bytes(int num_data, const int data[], + unsigned char bytes[]); + +/** + * convert memory bytes to signed 24 bit integers + * input: bytes contains "num_bytes" byte elements + * output: data contains "num_bytes/3" int24 elements + * @param num_bytes length of the input data array + * @param bytes input data as unsigned char array + * @param data output data as integer array +*/ +void tfa98xx_convert_bytes2data(int num_bytes, const unsigned char bytes[], + int data[]); + +/** + * Read a part of the dsp memory + * @param tfa the device struct pointer + * @param memoryType indicator to the memory type + * @param offset from where to start reading + * @param length the number of bytes to read + * @param bytes output data as unsigned char array +*/ +enum Tfa98xx_Error tfa98xx_dsp_get_memory(struct tfa_device *tfa, + int memoryType, int offset, + int length, unsigned char bytes[]); + +/** + * Write a value to the dsp memory + * @param tfa the device struct pointer + * @param memoryType indicator to the memory type + * @param offset from where to start writing + * @param length the number of bytes to write + * @param value the value to write to the dsp +*/ +enum Tfa98xx_Error tfa98xx_dsp_set_memory(struct tfa_device *tfa, + int memoryType, int offset, + int length, int value); + +enum Tfa98xx_Error +tfa98xx_dsp_write_config(struct tfa_device *tfa, int length, + const unsigned char *p_config_bytes); +enum Tfa98xx_Error tfa98xx_dsp_write_drc(struct tfa_device *tfa, int length, + const unsigned char *p_drc_bytes); + +/** + * write/read raw msg functions : + * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes. + * The functions will return immediately and do not not wait for DSP reponse. + * @param tfa the device struct pointer + * @param length length of the character buffer to write + * @param buf character buffer to write +*/ +enum Tfa98xx_Error tfa_dsp_msg(struct tfa_device *tfa, int length, + const char *buf); + +/** + * The wrapper functions to call the dsp msg, register and memory function for tfa or probus + */ +enum Tfa98xx_Error dsp_msg(struct tfa_device *tfa, int length, const char *buf); +enum Tfa98xx_Error dsp_msg_read(struct tfa_device *tfa, int length, + unsigned char *bytes); +enum Tfa98xx_Error reg_write(struct tfa_device *tfa, unsigned char subaddress, + unsigned short value); +enum Tfa98xx_Error reg_read(struct tfa_device *tfa, unsigned char subaddress, + unsigned short *value); +enum Tfa98xx_Error mem_write(struct tfa_device *tfa, unsigned short address, + int value, int memtype); +enum Tfa98xx_Error mem_read(struct tfa_device *tfa, unsigned int start_offset, + int num_words, int *pValues); + +enum Tfa98xx_Error dsp_partial_coefficients(struct tfa_device *tfa, + uint8_t *prev, uint8_t *next); + +/** + * write/read raw msg functions: + * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes. + * The functions will return immediately and do not not wait for DSP reponse. + * An ID is added to modify the command-ID + * @param tfa the device struct pointer + * @param length length of the character buffer to write + * @param buf character buffer to write + * @param cmdid command identifier +*/ +enum Tfa98xx_Error tfa_dsp_msg_id(struct tfa_device *tfa, int length, + const char *buf, uint8_t cmdid[3]); + +/** + * write raw dsp msg functions + * @param tfa the device struct pointer + * @param length length of the character buffer to write + * @param buffer character buffer to write +*/ +enum Tfa98xx_Error tfa_dsp_msg_write(struct tfa_device *tfa, int length, + const char *buffer); + +/** + * write raw dsp msg functions + * @param tfa the device struct pointer + * @param length length of the character buffer to write + * @param buffer character buffer to write + * @param cmdid command identifier +*/ +enum Tfa98xx_Error tfa_dsp_msg_write_id(struct tfa_device *tfa, int length, + const char *buffer, uint8_t cmdid[3]); + +/** + * status function used by tfa_dsp_msg() to retrieve command/msg status: + * return a <0 status of the DSP did not ACK. + * @param tfa the device struct pointer + * @param pRpcStatus status for remote processor communication +*/ +enum Tfa98xx_Error tfa_dsp_msg_status(struct tfa_device *tfa, int *pRpcStatus); + +/** + * Read a message from dsp + * @param tfa the device struct pointer + * @param length number of bytes of the message + * @param bytes pointer to unsigned char buffer +*/ +enum Tfa98xx_Error tfa_dsp_msg_read(struct tfa_device *tfa, int length, + unsigned char *bytes); + +int tfa_set_bf(struct tfa_device *tfa, const uint16_t bf, const uint16_t value); +int tfa_set_bf_volatile(struct tfa_device *tfa, const uint16_t bf, + const uint16_t value); + +/** + * Get the value of a given bitfield + * @param tfa the device struct pointer + * @param bf the value indicating which bitfield + */ +int tfa_get_bf(struct tfa_device *tfa, const uint16_t bf); + +/** + * Set the value of a given bitfield + * @param bf the value indicating which bitfield + * @param bf_value the value of the bitfield + * @param p_reg_value a pointer to the register where to write the bitfield value + */ +int tfa_set_bf_value(const uint16_t bf, const uint16_t bf_value, + uint16_t *p_reg_value); + +uint16_t tfa_get_bf_value(const uint16_t bf, const uint16_t reg_value); +int tfa_write_reg(struct tfa_device *tfa, const uint16_t bf, + const uint16_t reg_value); +int tfa_read_reg(struct tfa_device *tfa, const uint16_t bf); + +/* bitfield */ +/** + * get the datasheet or bitfield name corresponding to the bitfield number + * @param num is the number for which to get the bitfield name + * @param rev is the device type + */ +char *tfaContBfName(uint16_t num, unsigned short rev); + +/** + * get the datasheet name corresponding to the bitfield number + * @param num is the number for which to get the bitfield name + * @param rev is the device type + */ +char *tfaContDsName(uint16_t num, unsigned short rev); + +/** + * get the bitfield name corresponding to the bitfield number + * @param num is the number for which to get the bitfield name + * @param rev is the device type + */ +char *tfaContBitName(uint16_t num, unsigned short rev); + +/** + * get the bitfield number corresponding to the bitfield name + * @param name is the bitfield name for which to get the bitfield number + * @param rev is the device type + */ +uint16_t tfaContBfEnum(const char *name, unsigned short rev); + +/** +* get the bitfield number corresponding to the bitfield name, checks for all devices +* @param name is the bitfield name for which to get the bitfield number + */ +uint16_t tfaContBfEnumAny(const char *name); + +#define TFA_FAM(tfa, fieldname) \ + ((tfa->tfa_family == 1) ? TFA1_BF_##fieldname : TFA2_BF_##fieldname) +#define TFA_FAM_FW(tfa, fwname) \ + ((tfa->tfa_family == 1) ? TFA1_FW_##fwname : TFA2_FW_##fwname) + +/* set/get bit fields to HW register*/ +#define TFA_SET_BF(tfa, fieldname, value) \ + tfa_set_bf(tfa, TFA_FAM(tfa, fieldname), value) +#define TFA_SET_BF_VOLATILE(tfa, fieldname, value) \ + tfa_set_bf_volatile(tfa, TFA_FAM(tfa, fieldname), value) +#define TFA_GET_BF(tfa, fieldname) tfa_get_bf(tfa, TFA_FAM(tfa, fieldname)) + +/* set/get bit field in variable */ +#define TFA_SET_BF_VALUE(tfa, fieldname, bf_value, p_reg_value) \ + tfa_set_bf_value(TFA_FAM(tfa, fieldname), bf_value, p_reg_value) +#define TFA_GET_BF_VALUE(tfa, fieldname, reg_value) \ + tfa_get_bf_value(TFA_FAM(tfa, fieldname), reg_value) + +/* write/read registers using a bit field name to determine the register address */ +#define TFA_WRITE_REG(tfa, fieldname, value) \ + tfa_write_reg(tfa, TFA_FAM(tfa, fieldname), value) +#define TFA_READ_REG(tfa, fieldname) tfa_read_reg(tfa, TFA_FAM(tfa, fieldname)) + +/* FOR CALIBRATION RETRIES */ +#define TFA98XX_API_WAITRESULT_NTRIES 3000 // defined in API + +/** + * run the startup/init sequence and set ACS bit + * @param tfa the device struct pointer + * @param state the cold start state that is requested + */ +enum Tfa98xx_Error tfaRunColdboot(struct tfa_device *tfa, int state); +enum Tfa98xx_Error tfaRunMute(struct tfa_device *tfa); +enum Tfa98xx_Error tfaRunUnmute(struct tfa_device *tfa); + +/** + * wait for calibrateDone + * @param tfa the device struct pointer + * @param calibrateDone pointer to status of calibration + */ +enum Tfa98xx_Error tfaRunWaitCalibration(struct tfa_device *tfa, + int *calibrateDone); + +/** + * run the startup/init sequence and set ACS bit + * @param tfa the device struct pointer + * @param profile the profile that should be loaded + */ +enum Tfa98xx_Error tfaRunColdStartup(struct tfa_device *tfa, int profile); + +/** + * this will load the patch witch will implicitly start the DSP + * if no patch is available the DPS is started immediately + * @param tfa the device struct pointer + */ +enum Tfa98xx_Error tfaRunStartDSP(struct tfa_device *tfa); + +/** + * start the clocks and wait until the AMP is switching + * on return the DSP sub system will be ready for loading + * @param tfa the device struct pointer + * @param profile the profile that should be loaded on startup + */ +enum Tfa98xx_Error tfaRunStartup(struct tfa_device *tfa, int profile); + +/** + * start the maximus speakerboost algorithm + * this implies a full system startup when the system was not already started + * @param tfa the device struct pointer + * @param force indicates wether a full system startup should be allowed + * @param profile the profile that should be loaded + */ +enum Tfa98xx_Error tfaRunSpeakerBoost(struct tfa_device *tfa, int force, + int profile); + +/** + * Startup the device and write all files from device and profile section + * @param tfa the device struct pointer + * @param force indicates wether a full system startup should be allowed + * @param profile the profile that should be loaded on speaker startup + */ +enum Tfa98xx_Error tfaRunSpeakerStartup(struct tfa_device *tfa, int force, + int profile); + +/** + * Run calibration + * @param tfa the device struct pointer + */ +enum Tfa98xx_Error tfaRunSpeakerCalibration(struct tfa_device *tfa); + +/** + * startup all devices. all step until patch loading is handled + * @param tfa the device struct pointer + */ +int tfaRunStartupAll(struct tfa_device *tfa); + +/** + * powerup the coolflux subsystem and wait for it + * @param tfa the device struct pointer + */ +enum Tfa98xx_Error tfa_cf_powerup(struct tfa_device *tfa); + +/* + * print the current device manager state + * @param tfa the device struct pointer + */ +enum Tfa98xx_Error show_current_state(struct tfa_device *tfa); + +/** + * Init registers and coldboot dsp + * @param tfa the device struct pointer + */ +int tfa_reset(struct tfa_device *tfa); + +/** + * Get profile from a register + * @param tfa the device struct pointer + */ +int tfa_dev_get_swprof(struct tfa_device *tfa); + +/** + * Save profile in a register + */ +int tfa_dev_set_swprof(struct tfa_device *tfa, unsigned short new_value); + +int tfa_dev_get_swvstep(struct tfa_device *tfa); + +int tfa_dev_set_swvstep(struct tfa_device *tfa, unsigned short new_value); + +int tfa_needs_reset(struct tfa_device *tfa); + +int tfa_is_cold(struct tfa_device *tfa); + +void tfa_set_query_info(struct tfa_device *tfa); + +int tfa_get_pga_gain(struct tfa_device *tfa); +int tfa_set_pga_gain(struct tfa_device *tfa, uint16_t value); +int tfa_get_noclk(struct tfa_device *tfa); + +/** + * Status of used for monitoring + * @param tfa the device struct pointer + * @return tfa error enum + */ + +enum Tfa98xx_Error tfa_status(struct tfa_device *tfa); + +/* + * function overload for flag_mtp_busy + */ +int tfa_dev_get_mtpb(struct tfa_device *tfa); + +#ifdef __cplusplus +} +#endif +#endif /* TFA_SERVICE_H */ diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/versions.h b/techpack/audio/asoc/codecs/tfa98xx/inc/versions.h new file mode 100644 index 000000000000..4bc866fa6deb --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/inc/versions.h @@ -0,0 +1,4 @@ +#ifndef _VERSIONS_H +#define TFA98XX_GIT_VERSIONS "v6.5.2_xxxxxxxxxx" +#define _VERSIONS_H +#endif diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c new file mode 100644 index 000000000000..f5542c15adb6 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c @@ -0,0 +1,4412 @@ +/* + * tfa98xx.c tfa98xx codec module + * + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define pr_fmt(fmt) "%s(): " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "config.h" +#include "tfa98xx.h" +#include "tfa.h" +#include "tfa_dsp_fw.h" + +/* required for enum tfa9912_irq */ +#include "tfa98xx_tfafieldnames.h" + +#include "spk-id.h" + +#define TFA98XX_VERSION TFA98XX_API_REV_STR + +#define I2C_RETRIES 50 +#define I2C_RETRY_DELAY 5 /* ms */ + +/* Change volume selection behavior: + * Uncomment following line to generate a profile change when updating + * a volume control (also changes to the profile of the modified volume + * control) + */ +/*#define TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL 1 +*/ + +/* Supported rates and data formats */ +#define TFA98XX_RATES SNDRV_PCM_RATE_8000_48000 +#define TFA98XX_FORMATS \ + (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +#define TF98XX_MAX_DSP_START_TRY_COUNT 10 + +#define TFA98XX_AAC_FW_NAME "tfa98xx_aac.cnt" +#define TFA98XX_GOER_FW_NAME "tfa98xx_goer.cnt" + +/* data accessible by all instances */ +static struct kmem_cache *tfa98xx_cache = + NULL; /* Memory pool used for DSP messages */ +/* Mutex protected data */ +static DEFINE_MUTEX(tfa98xx_mutex); +static LIST_HEAD(tfa98xx_device_list); +static int tfa98xx_device_count = 0; +static int tfa98xx_sync_count = 0; +static LIST_HEAD(profile_list); /* list of user selectable profiles */ +static int tfa98xx_mixer_profiles = 0; /* number of user selectable profiles */ +static int tfa98xx_mixer_profile = 0; /* current mixer profile */ +static struct snd_kcontrol_new *tfa98xx_controls; +static nxpTfaContainer_t *tfa98xx_container = NULL; + +static int tfa98xx_kmsg_regs = 0; +static int tfa98xx_ftrace_regs = 0; + +static char *fw_name = "tfa98xx.cnt"; +module_param(fw_name, charp, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(fw_name, "TFA98xx DSP firmware (container file) name."); + +static int trace_level = 0; +module_param(trace_level, int, S_IRUGO); +MODULE_PARM_DESC( + trace_level, + "TFA98xx debug trace level (0=off, bits:1=verbose,2=regdmesg,3=regftrace,4=timing)."); + +static char *dflt_prof_name = ""; +module_param(dflt_prof_name, charp, S_IRUGO); + +static int no_start = 0; +module_param(no_start, int, S_IRUGO); +MODULE_PARM_DESC(no_start, + "do not start the work queue; for debugging via user\n"); + +static int no_reset = 0; +module_param(no_reset, int, S_IRUGO); +MODULE_PARM_DESC(no_reset, + "do not use the reset line; for debugging via user\n"); + +static int pcm_no_constraint = 0; +module_param(pcm_no_constraint, int, S_IRUGO); +MODULE_PARM_DESC(pcm_no_constraint, + "do not use constraints for PCM parameters\n"); + +static void tfa98xx_tapdet_check_update(struct tfa98xx *tfa98xx); +static int tfa98xx_get_fssel(unsigned int rate); +static void tfa98xx_interrupt_enable(struct tfa98xx *tfa98xx, bool enable); + +static int get_profile_from_list(char *buf, int id); +static int get_profile_id_for_sr(int id, unsigned int rate); + +struct tfa98xx_rate { + unsigned int rate; + unsigned int fssel; +}; + +static const struct tfa98xx_rate rate_to_fssel[] = { + { 8000, 0 }, { 11025, 1 }, { 12000, 2 }, { 16000, 3 }, { 22050, 4 }, + { 24000, 5 }, { 32000, 6 }, { 44100, 7 }, { 48000, 8 }, +}; + +int nxp_spk_id_get(struct device_node *np) +{ + int id = VENDOR_ID_UNKNOWN; + int state = 3; + + /*state = spk_id_get_pin_3state(np); + if (state < 0) { + pr_err("%s: Can not get id pin state, %d\n", __func__, state); + return VENDOR_ID_NONE; + }*/ + + switch (state) { + case PIN_PULL_DOWN: + id = VENDOR_ID_GOER; + break; + case PIN_PULL_UP: + id = VENDOR_ID_UNKNOWN; + break; + case PIN_FLOAT: + id = VENDOR_ID_AAC; + break; + default: + id = VENDOR_ID_NONE; + break; + } + return id; +} + +static int nxp_vendor_id_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = VENDOR_ID_NONE; + + if (tfa98xx->spk_id_gpio_p) + ucontrol->value.integer.value[0] = + nxp_spk_id_get(tfa98xx->spk_id_gpio_p); + return 0; +} + +static const char *const nxp_vendor_id_text[] = { "None", "AAC", "SSI", "GOER", + "Unknown" }; + +static const struct soc_enum nxp_vendor_id[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(nxp_vendor_id_text), nxp_vendor_id_text), +}; + +const struct snd_kcontrol_new nxp_spk_id_controls[] = { + SOC_ENUM_EXT("SPK ID", nxp_vendor_id, nxp_vendor_id_get, NULL), +}; + +static inline char *tfa_cont_profile_name(struct tfa98xx *tfa98xx, int prof_idx) +{ + if (tfa98xx->tfa->cnt == NULL) + return NULL; + return tfaContProfileName(tfa98xx->tfa->cnt, tfa98xx->tfa->dev_idx, + prof_idx); +} + +static enum tfa_error tfa98xx_write_re25(struct tfa_device *tfa, int value) +{ + enum tfa_error err; + + /* clear MTPEX */ + err = tfa_dev_mtp_set(tfa, TFA_MTP_EX, 0); + if (err == tfa_error_ok) { + /* set RE25 in shadow regiser */ + err = tfa_dev_mtp_set(tfa, TFA_MTP_RE25_PRIM, value); + } + if (err == tfa_error_ok) { + /* set MTPEX to copy RE25 into MTP */ + err = tfa_dev_mtp_set(tfa, TFA_MTP_EX, 2); + } + + return err; +} + +/* Wrapper for tfa start */ +static enum tfa_error tfa98xx_tfa_start(struct tfa98xx *tfa98xx, + int next_profile, int vstep) +{ + enum tfa_error err; + ktime_t start_time, stop_time; + u64 delta_time; + + pr_debug("%s next_profile=%d vstep=%d\n", __func__, next_profile, + vstep); + if (trace_level & 8) { + start_time = ktime_get_boottime(); + } + + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ +#ifdef __KERNEL__ + err = tfa_dev_start(tfa98xx->tfa, next_profile, vstep, + tfa98xx->pcm_format); +#else + err = tfa_dev_start(tfa98xx->tfa, next_profile, vstep); +#endif + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ + pr_debug("%s after performed tfa_dev_start return (%d)\n", __func__, + err); + + if (trace_level & 8) { + stop_time = ktime_get_boottime(); + delta_time = ktime_to_ns(ktime_sub(stop_time, start_time)); + do_div(delta_time, 1000); + dev_dbg(&tfa98xx->i2c->dev, + "tfa_dev_start(%d,%d) time = %lld us\n", next_profile, + vstep, delta_time); + } + + if ((err == tfa_error_ok) && (tfa98xx->set_mtp_cal)) { + enum tfa_error err_cal; + err_cal = tfa98xx_write_re25(tfa98xx->tfa, tfa98xx->cal_data); + if (err_cal != tfa_error_ok) { + pr_err("Error, setting calibration value in mtp, err=%d\n", + err_cal); + } else { + tfa98xx->set_mtp_cal = false; + pr_info("Calibration value (%d) set in mtp\n", + tfa98xx->cal_data); + } + } + + /* Check and update tap-detection state (in case of profile change) */ + tfa98xx_tapdet_check_update(tfa98xx); + + /* Remove sticky bit by reading it once */ + tfa_get_noclk(tfa98xx->tfa); + + /* A cold start erases the configuration, including interrupts setting. + * Restore it if required + */ + tfa98xx_interrupt_enable(tfa98xx, true); + + return err; +} + +static int tfa98xx_input_open(struct input_dev *dev) +{ + struct tfa98xx *tfa98xx = input_get_drvdata(dev); + dev_dbg(tfa98xx->codec->dev, "opening device file\n"); + + /* note: open function is called only once by the framework. + * No need to count number of open file instances. + */ + if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) { + dev_dbg(&tfa98xx->i2c->dev, + "DSP not loaded, cannot start tap-detection\n"); + return -EIO; + } + + /* enable tap-detection service */ + tfa98xx->tapdet_open = true; + tfa98xx_tapdet_check_update(tfa98xx); + + return 0; +} + +static void tfa98xx_input_close(struct input_dev *dev) +{ + struct tfa98xx *tfa98xx = input_get_drvdata(dev); + + dev_dbg(tfa98xx->codec->dev, "closing device file\n"); + + /* Note: close function is called if the device is unregistered */ + + /* disable tap-detection service */ + tfa98xx->tapdet_open = false; + tfa98xx_tapdet_check_update(tfa98xx); +} + +static int tfa98xx_register_inputdev(struct tfa98xx *tfa98xx) +{ + int err; + struct input_dev *input; + input = input_allocate_device(); + + if (!input) { + dev_err(tfa98xx->codec->dev, + "Unable to allocate input device\n"); + return -ENOMEM; + } + + input->evbit[0] = BIT_MASK(EV_KEY); + input->keybit[BIT_WORD(BTN_0)] |= BIT_MASK(BTN_0); + input->keybit[BIT_WORD(BTN_1)] |= BIT_MASK(BTN_1); + input->keybit[BIT_WORD(BTN_2)] |= BIT_MASK(BTN_2); + input->keybit[BIT_WORD(BTN_3)] |= BIT_MASK(BTN_3); + input->keybit[BIT_WORD(BTN_4)] |= BIT_MASK(BTN_4); + input->keybit[BIT_WORD(BTN_5)] |= BIT_MASK(BTN_5); + input->keybit[BIT_WORD(BTN_6)] |= BIT_MASK(BTN_6); + input->keybit[BIT_WORD(BTN_7)] |= BIT_MASK(BTN_7); + input->keybit[BIT_WORD(BTN_8)] |= BIT_MASK(BTN_8); + input->keybit[BIT_WORD(BTN_9)] |= BIT_MASK(BTN_9); + + input->open = tfa98xx_input_open; + input->close = tfa98xx_input_close; + + input->name = "tfa98xx-tapdetect"; + + input->id.bustype = BUS_I2C; + input_set_drvdata(input, tfa98xx); + + err = input_register_device(input); + if (err) { + dev_err(tfa98xx->codec->dev, + "Unable to register input device\n"); + goto err_free_dev; + } + + dev_dbg(tfa98xx->codec->dev, + "Input device for tap-detection registered: %s\n", input->name); + tfa98xx->input = input; + return 0; + +err_free_dev: + input_free_device(input); + return err; +} + +/* + * Check if an input device for tap-detection can and shall be registered. + * Register it if appropriate. + * If already registered, check if still relevant and remove it if necessary. + * unregister: true to request inputdev unregistration. + */ +static void __tfa98xx_inputdev_check_register(struct tfa98xx *tfa98xx, + bool unregister) +{ + bool tap_profile = false; + unsigned int i; + for (i = 0; i < tfa_cnt_get_dev_nprof(tfa98xx->tfa); i++) { + if (strstr(tfa_cont_profile_name(tfa98xx, i), ".tap")) { + tap_profile = true; + tfa98xx->tapdet_profiles |= 1 << i; + dev_info(tfa98xx->codec->dev, + "found a tap-detection profile (%d - %s)\n", i, + tfa_cont_profile_name(tfa98xx, i)); + } + } + + /* Check for device support: + * - at device level + * - at container (profile) level + */ + if (!(tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) || !tap_profile || + unregister) { + /* No input device supported or required */ + if (tfa98xx->input) { + input_unregister_device(tfa98xx->input); + tfa98xx->input = NULL; + } + return; + } + + /* input device required */ + if (tfa98xx->input) + dev_info(tfa98xx->codec->dev, + "Input device already registered, skipping\n"); + else + tfa98xx_register_inputdev(tfa98xx); +} + +static void tfa98xx_inputdev_check_register(struct tfa98xx *tfa98xx) +{ + __tfa98xx_inputdev_check_register(tfa98xx, false); +} + +static void tfa98xx_inputdev_unregister(struct tfa98xx *tfa98xx) +{ + __tfa98xx_inputdev_check_register(tfa98xx, true); +} + +#ifdef CONFIG_DEBUG_FS +/* OTC reporting + * Returns the MTP0 OTC bit value + */ +static int tfa98xx_dbgfs_otc_get(void *data, u64 *val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + int value; + + mutex_lock(&tfa98xx->dsp_lock); + value = tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_OTC); + mutex_unlock(&tfa98xx->dsp_lock); + + if (value < 0) { + pr_err("[0x%x] Unable to check DSP access: %d\n", + tfa98xx->i2c->addr, value); + return -EIO; + } + + *val = value; + pr_debug("[0x%x] OTC : %d\n", tfa98xx->i2c->addr, value); + + return 0; +} + +static int tfa98xx_dbgfs_otc_set(void *data, u64 val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + enum tfa_error err; + + if (val != 0 && val != 1) { + pr_err("[0x%x] Unexpected value %llu\n", tfa98xx->i2c->addr, + val); + return -EINVAL; + } + + mutex_lock(&tfa98xx->dsp_lock); + err = tfa_dev_mtp_set(tfa98xx->tfa, TFA_MTP_OTC, val); + mutex_unlock(&tfa98xx->dsp_lock); + + if (err != tfa_error_ok) { + pr_err("[0x%x] Unable to check DSP access: %d\n", + tfa98xx->i2c->addr, err); + return -EIO; + } + + pr_debug("[0x%x] OTC < %llu\n", tfa98xx->i2c->addr, val); + + return 0; +} + +static int tfa98xx_dbgfs_mtpex_get(void *data, u64 *val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + int value; + + mutex_lock(&tfa98xx->dsp_lock); + value = tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_EX); + mutex_unlock(&tfa98xx->dsp_lock); + + if (value < 0) { + pr_err("[0x%x] Unable to check DSP access: %d\n", + tfa98xx->i2c->addr, value); + return -EIO; + } + + *val = value; + pr_debug("[0x%x] MTPEX : %d\n", tfa98xx->i2c->addr, value); + + return 0; +} + +static int tfa98xx_dbgfs_mtpex_set(void *data, u64 val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + enum tfa_error err; + + if (val != 0) { + pr_err("[0x%x] Can only clear MTPEX (0 value expected)\n", + tfa98xx->i2c->addr); + return -EINVAL; + } + + mutex_lock(&tfa98xx->dsp_lock); + err = tfa_dev_mtp_set(tfa98xx->tfa, TFA_MTP_EX, val); + mutex_unlock(&tfa98xx->dsp_lock); + + if (err != tfa_error_ok) { + pr_err("[0x%x] Unable to check DSP access: %d\n", + tfa98xx->i2c->addr, err); + return -EIO; + } + + pr_debug("[0x%x] MTPEX < 0\n", tfa98xx->i2c->addr); + + return 0; +} + +static int tfa98xx_dbgfs_temp_get(void *data, u64 *val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + + mutex_lock(&tfa98xx->dsp_lock); + *val = tfa98xx_get_exttemp(tfa98xx->tfa); + mutex_unlock(&tfa98xx->dsp_lock); + + pr_debug("[0x%x] TEMP : %llu\n", tfa98xx->i2c->addr, *val); + + return 0; +} + +static int tfa98xx_dbgfs_temp_set(void *data, u64 val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + + mutex_lock(&tfa98xx->dsp_lock); + tfa98xx_set_exttemp(tfa98xx->tfa, (short)val); + mutex_unlock(&tfa98xx->dsp_lock); + + pr_debug("[0x%x] TEMP < %llu\n", tfa98xx->i2c->addr, val); + + return 0; +} + +static ssize_t tfa98xx_dbgfs_start_set(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct i2c_client *i2c = file->private_data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + enum tfa_error ret; + char buf[32]; + const char ref[] = "please calibrate now"; + int buf_size; + + /* check string length, and account for eol */ + if (count > sizeof(ref) + 1 || count < (sizeof(ref) - 1)) + return -EINVAL; + + buf_size = min(count, (size_t)(sizeof(buf) - 1)); + if (copy_from_user(buf, user_buf, buf_size)) + return -EFAULT; + buf[buf_size] = 0; + + /* Compare string, excluding the trailing \0 and the potentials eol */ + if (strncmp(buf, ref, sizeof(ref) - 1)) + return -EINVAL; + + mutex_lock(&tfa98xx->dsp_lock); + ret = tfa_calibrate(tfa98xx->tfa); + if (ret == tfa_error_ok) + ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, + tfa98xx->vstep); + if (ret == tfa_error_ok) + tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0); + mutex_unlock(&tfa98xx->dsp_lock); + + if (ret) { + pr_info("[0x%x] Calibration start failed (%d)\n", + tfa98xx->i2c->addr, ret); + return -EIO; + } else { + pr_info("[0x%x] Calibration started\n", tfa98xx->i2c->addr); + } + + return count; +} + +static ssize_t tfa98xx_dbgfs_r_read(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct i2c_client *i2c = file->private_data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + char *str; + uint16_t status; + int ret; + + mutex_lock(&tfa98xx->dsp_lock); + + /* Need to ensure DSP is access-able, use mtp read access for this + * purpose + */ + ret = tfa98xx_get_mtp(tfa98xx->tfa, &status); + if (ret) { + ret = -EIO; + pr_err("[0x%x] MTP read failed\n", tfa98xx->i2c->addr); + goto r_c_err; + } + + ret = tfaRunSpeakerCalibration(tfa98xx->tfa); + if (ret) { + ret = -EIO; + pr_err("[0x%x] calibration failed\n", tfa98xx->i2c->addr); + goto r_c_err; + } + + str = kmalloc(PAGE_SIZE, GFP_KERNEL); + if (!str) { + ret = -ENOMEM; + pr_err("[0x%x] memory allocation failed\n", tfa98xx->i2c->addr); + goto r_c_err; + } + + if (tfa98xx->tfa->spkr_count > 1) { + ret = snprintf(str, PAGE_SIZE, "Prim:%d mOhms, Sec:%d mOhms\n", + tfa98xx->tfa->mohm[0], tfa98xx->tfa->mohm[1]); + } else { + ret = snprintf(str, PAGE_SIZE, "Prim:%d mOhms\n", + tfa98xx->tfa->mohm[0]); + } + + pr_debug("[0x%x] calib_done: %s", tfa98xx->i2c->addr, str); + + if (ret < 0) + goto r_err; + + ret = simple_read_from_buffer(user_buf, count, ppos, str, ret); + +r_err: + kfree(str); +r_c_err: + mutex_unlock(&tfa98xx->dsp_lock); + return ret; +} + +static ssize_t tfa98xx_dbgfs_version_read(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + char str[] = TFA98XX_VERSION "\n"; + int ret; + + ret = simple_read_from_buffer(user_buf, count, ppos, str, sizeof(str)); + + return ret; +} + +static ssize_t tfa98xx_dbgfs_dsp_state_get(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct i2c_client *i2c = file->private_data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + int ret = 0; + char *str; + + switch (tfa98xx->dsp_init) { + case TFA98XX_DSP_INIT_STOPPED: + str = "Stopped\n"; + break; + case TFA98XX_DSP_INIT_RECOVER: + str = "Recover requested\n"; + break; + case TFA98XX_DSP_INIT_FAIL: + str = "Failed init\n"; + break; + case TFA98XX_DSP_INIT_PENDING: + str = "Pending init\n"; + break; + case TFA98XX_DSP_INIT_DONE: + str = "Init complete\n"; + break; + default: + str = "Invalid\n"; + } + + pr_debug("[0x%x] dsp_state : %s\n", tfa98xx->i2c->addr, str); + + ret = simple_read_from_buffer(user_buf, count, ppos, str, strlen(str)); + return ret; +} + +static ssize_t tfa98xx_dbgfs_dsp_state_set(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct i2c_client *i2c = file->private_data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + enum tfa_error ret; + char buf[32]; + const char start_cmd[] = "start"; + const char stop_cmd[] = "stop"; + const char mon_start_cmd[] = "monitor start"; + const char mon_stop_cmd[] = "monitor stop"; + int buf_size; + + buf_size = min(count, (size_t)(sizeof(buf) - 1)); + if (copy_from_user(buf, user_buf, buf_size)) + return -EFAULT; + buf[buf_size] = 0; + + /* Compare strings, excluding the trailing \0 */ + if (!strncmp(buf, start_cmd, sizeof(start_cmd) - 1)) { + pr_info("[0x%x] Manual triggering of dsp start...\n", + tfa98xx->i2c->addr); + mutex_lock(&tfa98xx->dsp_lock); + ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, + tfa98xx->vstep); + mutex_unlock(&tfa98xx->dsp_lock); + pr_debug("[0x%x] tfa_dev_start complete: %d\n", + tfa98xx->i2c->addr, ret); + } else if (!strncmp(buf, stop_cmd, sizeof(stop_cmd) - 1)) { + pr_info("[0x%x] Manual triggering of dsp stop...\n", + tfa98xx->i2c->addr); + mutex_lock(&tfa98xx->dsp_lock); + ret = tfa_dev_stop(tfa98xx->tfa); + mutex_unlock(&tfa98xx->dsp_lock); + pr_debug("[0x%x] tfa_dev_stop complete: %d\n", + tfa98xx->i2c->addr, ret); + } else if (!strncmp(buf, mon_start_cmd, sizeof(mon_start_cmd) - 1)) { + pr_info("[0x%x] Manual start of monitor thread...\n", + tfa98xx->i2c->addr); + queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->monitor_work, + HZ); + } else if (!strncmp(buf, mon_stop_cmd, sizeof(mon_stop_cmd) - 1)) { + pr_info("[0x%x] Manual stop of monitor thread...\n", + tfa98xx->i2c->addr); + cancel_delayed_work_sync(&tfa98xx->monitor_work); + } else { + return -EINVAL; + } + + return count; +} + +static ssize_t tfa98xx_dbgfs_fw_state_get(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct i2c_client *i2c = file->private_data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + char *str; + + switch (tfa98xx->dsp_fw_state) { + case TFA98XX_DSP_FW_NONE: + str = "None\n"; + break; + case TFA98XX_DSP_FW_PENDING: + str = "Pending\n"; + break; + case TFA98XX_DSP_FW_FAIL: + str = "Fail\n"; + break; + case TFA98XX_DSP_FW_OK: + str = "Ok\n"; + break; + default: + str = "Invalid\n"; + } + + pr_debug("[0x%x] fw_state : %s", tfa98xx->i2c->addr, str); + + return simple_read_from_buffer(user_buf, count, ppos, str, strlen(str)); +} + +#ifdef TFA_NON_DSP_SOLUTION +extern int send_tfa_cal_apr(void *buf, int cmd_size, bool bRead); +#else +int send_tfa_cal_apr(void *buf, int cmd_size, bool bRead) +{ + return 0; +} +#endif + +static ssize_t tfa98xx_dbgfs_rpc_read(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct i2c_client *i2c = file->private_data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + int ret = 0; + uint8_t *buffer; + enum Tfa98xx_Error error; + + if (tfa98xx->tfa == NULL) { + pr_debug("[0x%x] dsp is not available\n", tfa98xx->i2c->addr); + return -ENODEV; + } + + if (count == 0) + return 0; + + buffer = kmalloc(count, GFP_KERNEL); + if (buffer == NULL) { + pr_debug("[0x%x] can not allocate memory\n", + tfa98xx->i2c->addr); + return -ENOMEM; + } + + mutex_lock(&tfa98xx->dsp_lock); + + if (tfa98xx->tfa->is_probus_device) { + error = send_tfa_cal_apr(buffer, count, true); + } else { + error = dsp_msg_read(tfa98xx->tfa, count, buffer); + } + mutex_unlock(&tfa98xx->dsp_lock); + if (error != Tfa98xx_Error_Ok) { + pr_debug("[0x%x] dsp_msg_read error: %d\n", tfa98xx->i2c->addr, + error); + kfree(buffer); + return -EFAULT; + } + + ret = copy_to_user(user_buf, buffer, count); + kfree(buffer); + if (ret) + return -EFAULT; + + *ppos += count; + return count; +} + +static ssize_t tfa98xx_dbgfs_rpc_send(struct file *file, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct i2c_client *i2c = file->private_data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + nxpTfaFileDsc_t *msg_file; + enum Tfa98xx_Error error; + int err = 0; + + if (tfa98xx->tfa == NULL) { + pr_debug("[0x%x] dsp is not available\n", tfa98xx->i2c->addr); + return -ENODEV; + } + + if (count == 0) + return 0; + + /* msg_file.name is not used */ + msg_file = kmalloc(count + sizeof(nxpTfaFileDsc_t), GFP_KERNEL); + if (msg_file == NULL) { + pr_debug("[0x%x] can not allocate memory\n", + tfa98xx->i2c->addr); + return -ENOMEM; + } + + msg_file->size = count; + if (copy_from_user(msg_file->data, user_buf, count)) + return -EFAULT; + + if (tfa98xx->tfa->is_probus_device) { + mutex_lock(&tfa98xx->dsp_lock); + error = send_tfa_cal_apr(msg_file->data, msg_file->size, false); + if (error != Tfa98xx_Error_Ok) { + pr_debug("[0x%x] dsp_msg error: %d\n", + tfa98xx->i2c->addr, error); + err = -EIO; + } + mutex_unlock(&tfa98xx->dsp_lock); + + mdelay(2); + } else { + mutex_lock(&tfa98xx->dsp_lock); + + if ((msg_file->data[0] == 'M') && (msg_file->data[1] == 'G')) { + error = tfaContWriteFile( + tfa98xx->tfa, msg_file, 0, + 0); /* int vstep_idx, int vstep_msg_idx both 0 */ + if (error != Tfa98xx_Error_Ok) { + pr_debug("[0x%x] tfaContWriteFile error: %d\n", + tfa98xx->i2c->addr, error); + err = -EIO; + } + } else { + error = dsp_msg(tfa98xx->tfa, msg_file->size, + msg_file->data); + if (error != Tfa98xx_Error_Ok) { + pr_debug("[0x%x] dsp_msg error: %d\n", + tfa98xx->i2c->addr, error); + err = -EIO; + } + } + mutex_unlock(&tfa98xx->dsp_lock); + } + + kfree(msg_file); + + if (err) + return err; + return count; +} +/* -- RPC */ + +static int tfa98xx_dbgfs_pga_gain_get(void *data, u64 *val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + unsigned int value; + + value = tfa_get_pga_gain(tfa98xx->tfa); + if (value < 0) + return -EINVAL; + + *val = value; + return 0; +} + +static int tfa98xx_dbgfs_pga_gain_set(void *data, u64 val) +{ + struct i2c_client *i2c = (struct i2c_client *)data; + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + uint16_t value; + int err; + + value = val & 0xffff; + if (value > 7) + return -EINVAL; + + err = tfa_set_pga_gain(tfa98xx->tfa, value); + if (err < 0) + return -EINVAL; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_otc_fops, tfa98xx_dbgfs_otc_get, + tfa98xx_dbgfs_otc_set, "%llu\n"); +DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_mtpex_fops, tfa98xx_dbgfs_mtpex_get, + tfa98xx_dbgfs_mtpex_set, "%llu\n"); +DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_calib_temp_fops, tfa98xx_dbgfs_temp_get, + tfa98xx_dbgfs_temp_set, "%llu\n"); + +DEFINE_SIMPLE_ATTRIBUTE(tfa98xx_dbgfs_pga_gain_fops, tfa98xx_dbgfs_pga_gain_get, + tfa98xx_dbgfs_pga_gain_set, "%llu\n"); + +static const struct file_operations tfa98xx_dbgfs_calib_start_fops = { + .open = simple_open, + .write = tfa98xx_dbgfs_start_set, + .llseek = default_llseek, +}; + +static const struct file_operations tfa98xx_dbgfs_r_fops = { + .open = simple_open, + .read = tfa98xx_dbgfs_r_read, + .llseek = default_llseek, +}; + +static const struct file_operations tfa98xx_dbgfs_version_fops = { + .open = simple_open, + .read = tfa98xx_dbgfs_version_read, + .llseek = default_llseek, +}; + +static const struct file_operations tfa98xx_dbgfs_dsp_state_fops = { + .open = simple_open, + .read = tfa98xx_dbgfs_dsp_state_get, + .write = tfa98xx_dbgfs_dsp_state_set, + .llseek = default_llseek, +}; + +static const struct file_operations tfa98xx_dbgfs_fw_state_fops = { + .open = simple_open, + .read = tfa98xx_dbgfs_fw_state_get, + .llseek = default_llseek, +}; + +static const struct file_operations tfa98xx_dbgfs_rpc_fops = { + .open = simple_open, + .read = tfa98xx_dbgfs_rpc_read, + .write = tfa98xx_dbgfs_rpc_send, + .llseek = default_llseek, +}; + +static void tfa98xx_debug_init(struct tfa98xx *tfa98xx, struct i2c_client *i2c) +{ + char name[50]; + + scnprintf(name, MAX_CONTROL_NAME, "%s-%x", i2c->name, i2c->addr); + tfa98xx->dbg_dir = debugfs_create_dir(name, NULL); + debugfs_create_file("OTC", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir, i2c, + &tfa98xx_dbgfs_calib_otc_fops); + debugfs_create_file("MTPEX", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir, i2c, + &tfa98xx_dbgfs_calib_mtpex_fops); + debugfs_create_file("TEMP", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir, i2c, + &tfa98xx_dbgfs_calib_temp_fops); + debugfs_create_file("calibrate", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir, + i2c, &tfa98xx_dbgfs_calib_start_fops); + debugfs_create_file("R", S_IRUGO, tfa98xx->dbg_dir, i2c, + &tfa98xx_dbgfs_r_fops); + debugfs_create_file("version", S_IRUGO, tfa98xx->dbg_dir, i2c, + &tfa98xx_dbgfs_version_fops); + debugfs_create_file("dsp-state", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir, + i2c, &tfa98xx_dbgfs_dsp_state_fops); + debugfs_create_file("fw-state", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir, + i2c, &tfa98xx_dbgfs_fw_state_fops); + debugfs_create_file("rpc", S_IRUGO | S_IWUGO, tfa98xx->dbg_dir, i2c, + &tfa98xx_dbgfs_rpc_fops); + + if (tfa98xx->flags & TFA98XX_FLAG_SAAM_AVAILABLE) { + dev_dbg(tfa98xx->dev, "Adding pga_gain debug interface\n"); + debugfs_create_file("pga_gain", S_IRUGO, tfa98xx->dbg_dir, + tfa98xx->i2c, &tfa98xx_dbgfs_pga_gain_fops); + } +} + +static void tfa98xx_debug_remove(struct tfa98xx *tfa98xx) +{ + if (tfa98xx->dbg_dir) + debugfs_remove_recursive(tfa98xx->dbg_dir); +} +#endif + +/* copies the profile basename (i.e. part until .) into buf */ +static void get_profile_basename(char *buf, char *profile) +{ + int cp_len = 0, idx = 0; + char *pch; + + pch = strchr(profile, '.'); + idx = pch - profile; + cp_len = (pch != NULL) ? idx : (int)strlen(profile); + memcpy(buf, profile, cp_len); + buf[cp_len] = 0; +} + +/* return the profile name accociated with id from the profile list */ +static int get_profile_from_list(char *buf, int id) +{ + struct tfa98xx_baseprofile *bprof; + + list_for_each_entry (bprof, &profile_list, list) { + if (bprof->item_id == id) { + strcpy(buf, bprof->basename); + return 0; + } + } + + return -1; +} + +/* search for the profile in the profile list */ +static int is_profile_in_list(char *profile, int len) +{ + struct tfa98xx_baseprofile *bprof; + + list_for_each_entry (bprof, &profile_list, list) { + if ((len == bprof->len) && + (0 == strncmp(bprof->basename, profile, len))) + return 1; + } + + return 0; +} + +/* + * for the profile with id, look if the requested samplerate is + * supported, if found return the (container)profile for this + * samplerate, on error or if not found return -1 + */ +static int get_profile_id_for_sr(int id, unsigned int rate) +{ + int idx = 0; + struct tfa98xx_baseprofile *bprof; + + list_for_each_entry (bprof, &profile_list, list) { + if (id == bprof->item_id) { + idx = tfa98xx_get_fssel(rate); + if (idx < 0) { + /* samplerate not supported */ + return -1; + } + + return bprof->sr_rate_sup[idx]; + } + } + + /* profile not found */ + return -1; +} + +static int get_profile_id_by_name(char *profile, int len) +{ + struct tfa98xx_baseprofile *bprof; + int prof_index = -1; + + list_for_each_entry (bprof, &profile_list, list) { + if (strncmp(profile, bprof->basename, len) == 0) { + prof_index = bprof->item_id; + break; + } + } + + return prof_index; +} + +/* check if this profile is a calibration profile */ +static int is_calibration_profile(char *profile) +{ + if (strstr(profile, ".cal") != NULL) + return 1; + return 0; +} + +/* + * adds the (container)profile index of the samplerate found in + * the (container)profile to a fixed samplerate table in the (mixer)profile + */ +static int add_sr_to_profile(struct tfa98xx *tfa98xx, char *basename, int len, + int profile) +{ + struct tfa98xx_baseprofile *bprof; + int idx = 0; + unsigned int sr = 0; + + list_for_each_entry (bprof, &profile_list, list) { + if ((len == bprof->len) && + (0 == strncmp(bprof->basename, basename, len))) { + /* add supported samplerate for this profile */ + sr = tfa98xx_get_profile_sr(tfa98xx->tfa, profile); + if (!sr) { + pr_err("unable to identify supported sample rate for %s\n", + bprof->basename); + return -1; + } + + /* get the index for this samplerate */ + idx = tfa98xx_get_fssel(sr); + if (idx < 0 || idx >= TFA98XX_NUM_RATES) { + pr_err("invalid index for samplerate %d\n", + idx); + return -1; + } + + /* enter the (container)profile for this samplerate at the corresponding index */ + bprof->sr_rate_sup[idx] = profile; + + pr_debug( + "added profile:samplerate = [%d:%d] for mixer profile: %s\n", + profile, sr, bprof->basename); + } + } + + return 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0) +static struct snd_soc_codec * +snd_soc_kcontrol_codec(struct snd_kcontrol *kcontrol) +{ + return snd_kcontrol_chip(kcontrol); +} +#endif + +static int tfa98xx_get_vstep(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + int mixer_profile = kcontrol->private_value; + int ret = 0; + int profile; + + profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate); + if (profile < 0) { + pr_err("tfa98xx: tfa98xx_get_vstep: invalid profile %d (mixer_profile=%d, rate=%d)\n", + profile, mixer_profile, tfa98xx->rate); + return -EINVAL; + } + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + int vstep = tfa98xx->prof_vsteps[profile]; + + ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] = + tfacont_get_max_vstep(tfa98xx->tfa, profile) - vstep - + 1; + } + mutex_unlock(&tfa98xx_mutex); + + return ret; +} + +static int tfa98xx_set_vstep(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + int mixer_profile = kcontrol->private_value; + int profile; + int err = 0; + int change = 0; + + pr_debug("%s no_start=%d\n", __func__, no_start); + if (no_start != 0) + return 0; + + profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate); + if (profile < 0) { + pr_err("tfa98xx: tfa98xx_set_vstep: invalid profile %d (mixer_profile=%d, rate=%d)\n", + profile, mixer_profile, tfa98xx->rate); + return -EINVAL; + } + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + int vstep, vsteps; + int ready = 0; + int new_vstep; + int value = + ucontrol->value.integer.value[tfa98xx->tfa->dev_idx]; + + vstep = tfa98xx->prof_vsteps[profile]; + vsteps = tfacont_get_max_vstep(tfa98xx->tfa, profile); + + if (vstep == vsteps - value - 1) + continue; + + new_vstep = vsteps - value - 1; + + if (new_vstep < 0) + new_vstep = 0; + + tfa98xx->prof_vsteps[profile] = new_vstep; + +#ifndef TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL + if (profile == tfa98xx->profile) { +#endif + /* this is the active profile, program the new vstep */ + tfa98xx->vstep = new_vstep; + mutex_lock(&tfa98xx->dsp_lock); + tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready); + + if (ready) { + err = tfa98xx_tfa_start(tfa98xx, + tfa98xx->profile, + tfa98xx->vstep); + if (err) { + pr_err("Write vstep error: %d\n", err); + } else { + pr_debug( + "Succesfully changed vstep index!\n"); + change = 1; + } + } + + mutex_unlock(&tfa98xx->dsp_lock); +#ifndef TFA98XX_ALSA_CTRL_PROF_CHG_ON_VOL + } +#endif + pr_debug("%d: vstep:%d, (control value: %d) - profile %d\n", + tfa98xx->tfa->dev_idx, new_vstep, value, profile); + } + + if (change) { + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + mutex_lock(&tfa98xx->dsp_lock); + tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0); + mutex_unlock(&tfa98xx->dsp_lock); + } + } + + mutex_unlock(&tfa98xx_mutex); + + return change; +} + +static int tfa98xx_info_vstep(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + + int mixer_profile = tfa98xx_mixer_profile; + int profile = get_profile_id_for_sr(mixer_profile, tfa98xx->rate); + if (profile < 0) { + pr_err("tfa98xx: tfa98xx_info_vstep: invalid profile %d (mixer_profile=%d, rate=%d)\n", + profile, mixer_profile, tfa98xx->rate); + return -EINVAL; + } + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + mutex_lock(&tfa98xx_mutex); + uinfo->count = tfa98xx_device_count; + mutex_unlock(&tfa98xx_mutex); + uinfo->value.integer.min = 0; + uinfo->value.integer.max = + max(0, tfacont_get_max_vstep(tfa98xx->tfa, profile) - 1); + pr_debug("vsteps count: %d [prof=%d]\n", + tfacont_get_max_vstep(tfa98xx->tfa, profile), profile); + return 0; +} + +static int tfa98xx_get_profile(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + mutex_lock(&tfa98xx_mutex); + ucontrol->value.integer.value[0] = tfa98xx_mixer_profile; + mutex_unlock(&tfa98xx_mutex); + + return 0; +} + +static int tfa98xx_set_profile(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + int change = 0; + int new_profile; + int prof_idx; + int profile_count = tfa98xx_mixer_profiles; + int profile = tfa98xx_mixer_profile; + + if (no_start != 0) + return 0; + + new_profile = ucontrol->value.integer.value[0]; + if (new_profile == profile) + return 0; + + if ((new_profile < 0) || (new_profile >= profile_count)) { + pr_err("not existing profile (%d)\n", new_profile); + return -EINVAL; + } + + /* get the container profile for the requested sample rate */ + prof_idx = get_profile_id_for_sr(new_profile, tfa98xx->rate); + if (prof_idx < 0) { + pr_err("tfa98xx: sample rate [%d] not supported for this mixer profile [%d].\n", + tfa98xx->rate, new_profile); + return 0; + } + pr_debug("selected container profile [%d]\n", prof_idx); + + /* update mixer profile */ + tfa98xx_mixer_profile = new_profile; + + /* modified by jiangtao.zeng begin. */ + /* we are updating profile index only if the device is not in operating mode, and will be start in tfa98xx_mute() later. + if the device in operating mode, we will apply new profile now. */ + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + int err; + int ready = 0; + + /* update 'real' profile (container profile) */ + tfa98xx->profile = prof_idx; + tfa98xx->vstep = tfa98xx->prof_vsteps[prof_idx]; + if (!tfa98xx->tfa->is_probus_device) { + /* Don't call tfa_dev_start() if there is no clock. */ + mutex_lock(&tfa98xx->dsp_lock); + tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready); + if (ready && (tfa_dev_get_state(tfa98xx->tfa) == + TFA_STATE_OPERATING)) { + /* Also re-enables the interrupts */ + err = tfa98xx_tfa_start(tfa98xx, prof_idx, + tfa98xx->vstep); + if (err) { + pr_info("Write profile error: %d\n", + err); + } else { + pr_debug( + "Changed to profile %d (vstep = %d)\n", + prof_idx, tfa98xx->vstep); + change = 1; + } + } + mutex_unlock(&tfa98xx->dsp_lock); + /* Flag DSP as invalidated as the profile change may invalidate the + * current DSP configuration. That way, further stream start can + * trigger a tfa_dev_start. + */ + tfa98xx->dsp_init = TFA98XX_DSP_INIT_INVALIDATED; + } + } + + if (change) { + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + mutex_lock(&tfa98xx->dsp_lock); + tfa_dev_set_state(tfa98xx->tfa, TFA_STATE_UNMUTE, 0); + mutex_unlock(&tfa98xx->dsp_lock); + } + } + + mutex_unlock(&tfa98xx_mutex); + + /* modified by jiangtao.zeng end. */ + + return change; +} + +static int tfa98xx_info_profile(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + char profile_name[MAX_CONTROL_NAME] = { 0 }; + int count = tfa98xx_mixer_profiles, err = -1; + + uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; + uinfo->count = 1; + uinfo->value.enumerated.items = count; + + if (uinfo->value.enumerated.item >= count) + uinfo->value.enumerated.item = count - 1; + + err = get_profile_from_list(profile_name, uinfo->value.enumerated.item); + if (err != 0) + return -EINVAL; + + strcpy(uinfo->value.enumerated.name, profile_name); + + return 0; +} + +static int tfa98xx_info_stop_ctl(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + mutex_lock(&tfa98xx_mutex); + uinfo->count = tfa98xx_device_count; + mutex_unlock(&tfa98xx_mutex); + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + + return 0; +} + +static int tfa98xx_get_stop_ctl(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tfa98xx *tfa98xx; + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] = 0; + } + mutex_unlock(&tfa98xx_mutex); + + return 0; +} + +static int tfa98xx_set_stop_ctl(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tfa98xx *tfa98xx; + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + int ready = 0; + int i = tfa98xx->tfa->dev_idx; + + pr_debug("%d: %ld\n", i, ucontrol->value.integer.value[i]); + + tfa98xx_dsp_system_stable(tfa98xx->tfa, &ready); + + if ((ucontrol->value.integer.value[i] != 0) && ready) { + cancel_delayed_work_sync(&tfa98xx->monitor_work); + + cancel_delayed_work_sync(&tfa98xx->init_work); + if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) + continue; + + mutex_lock(&tfa98xx->dsp_lock); + tfa_dev_stop(tfa98xx->tfa); + tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED; + mutex_unlock(&tfa98xx->dsp_lock); + } + + ucontrol->value.integer.value[i] = 0; + } + mutex_unlock(&tfa98xx_mutex); + + return 1; +} + +static int tfa98xx_info_PAmute(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + mutex_lock(&tfa98xx_mutex); + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = tfa98xx_device_count; + uinfo->value.integer.min = TFA98XX_DEVICE_MUTE_OFF; + uinfo->value.integer.max = TFA98XX_DEVICE_MUTE_ON; + mutex_unlock(&tfa98xx_mutex); + + return 0; +} + +static int tfa98xx_get_PAmute(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tfa98xx *tfa98xx = NULL; + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] = + tfa98xx->tfa_mute_mode; + } + mutex_unlock(&tfa98xx_mutex); + + return 0; +} + +static int tfa98xx_set_PAmute(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tfa98xx *tfa98xx = NULL; + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + if (ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] != + TFA98XX_DEVICE_MUTE_OFF) { + tfa98xx->tfa_mute_mode = TFA98XX_DEVICE_MUTE_ON; + } else { + tfa98xx->tfa_mute_mode = TFA98XX_DEVICE_MUTE_OFF; + } + } + mutex_unlock(&tfa98xx_mutex); + + return 1; +} + +static int tfa98xx_info_cal_ctl(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + mutex_lock(&tfa98xx_mutex); + uinfo->count = tfa98xx_device_count; + mutex_unlock(&tfa98xx_mutex); + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 0xffff; /* 16 bit value */ + + return 0; +} + +static int tfa98xx_set_cal_ctl(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tfa98xx *tfa98xx; + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + enum tfa_error err; + int i = tfa98xx->tfa->dev_idx; + + tfa98xx->cal_data = (uint16_t)ucontrol->value.integer.value[i]; + + mutex_lock(&tfa98xx->dsp_lock); + err = tfa98xx_write_re25(tfa98xx->tfa, tfa98xx->cal_data); + tfa98xx->set_mtp_cal = (err != tfa_error_ok); + if (tfa98xx->set_mtp_cal == false) { + pr_info("Calibration value (%d) set in mtp\n", + tfa98xx->cal_data); + } + mutex_unlock(&tfa98xx->dsp_lock); + } + mutex_unlock(&tfa98xx_mutex); + + return 1; +} + +static int tfa98xx_get_cal_ctl(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tfa98xx *tfa98xx; + + mutex_lock(&tfa98xx_mutex); + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + mutex_lock(&tfa98xx->dsp_lock); + ucontrol->value.integer.value[tfa98xx->tfa->dev_idx] = + tfa_dev_mtp_get(tfa98xx->tfa, TFA_MTP_RE25_PRIM); + mutex_unlock(&tfa98xx->dsp_lock); + } + mutex_unlock(&tfa98xx_mutex); + + return 0; +} + +#ifdef TFA_NON_DSP_SOLUTION +static atomic_t g_bypass; +static atomic_t g_Tx_enable; +extern int send_tfa_cal_set_bypass(void *buf, int cmd_size); +extern int send_tfa_cal_set_tx_enable(void *buf, int cmd_size); + +/*************bypass control***************/ +static int tfa987x_algo_get_status(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t ret = 0; + ucontrol->value.integer.value[0] = atomic_read(&g_bypass); + return ret; +} + +static int tfa987x_algo_set_status(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t ret = 0; + u8 buff[56] = { 0 }, *ptr = buff; + ((int32_t *)buff)[0] = ucontrol->value.integer.value[0]; + pr_err("%s:status data %d\n", __func__, ((int32_t *)buff)[0]); + atomic_set(&g_bypass, ((int32_t *)buff)[0]); + ret = send_tfa_cal_set_bypass(ptr, 4); + return ret; +} + +static int tfa987x_algo_set_tx_enable(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t ret = 0; + u8 buff[56] = { 0 }, *ptr = buff; + ((int32_t *)buff)[0] = ucontrol->value.integer.value[0]; + pr_err("%s:set_tx_enable %d\n", __func__, ((int32_t *)buff)[0]); + atomic_set(&g_Tx_enable, ((int32_t *)buff)[0]); + ret = send_tfa_cal_set_tx_enable(ptr, 4); + return ret; +} + +static int tfa987x_algo_get_tx_status(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t ret = 0; + ucontrol->value.integer.value[0] = atomic_read(&g_Tx_enable); + return ret; +} + +static const char *tfa987x_algo_text[] = { "DISABLE", "ENABLE" }; + +static const char *tfa987x_tx_text[] = { "DISABLE", "ENABLE" }; + +static const struct soc_enum tfa987x_algo_enum[] = { SOC_ENUM_SINGLE_EXT( + ARRAY_SIZE(tfa987x_algo_text), tfa987x_algo_text) }; + +static const struct soc_enum tfa987x_tx_enum[] = { SOC_ENUM_SINGLE_EXT( + ARRAY_SIZE(tfa987x_tx_text), tfa987x_tx_text) }; + +const struct snd_kcontrol_new tfa987x_algo_controls[] = { + SOC_ENUM_EXT("TFA987X_ALGO_STATUS", tfa987x_algo_enum[0], + tfa987x_algo_get_status, tfa987x_algo_set_status), + SOC_ENUM_EXT("TFA987X_TX_ENABLE", tfa987x_tx_enum[0], + tfa987x_algo_get_tx_status, tfa987x_algo_set_tx_enable) +}; +#endif + +static int tfa98xx_create_controls(struct tfa98xx *tfa98xx) +{ + int prof, nprof, mix_index = 0; + int nr_controls = 0, id = 0; + char *name; + struct tfa98xx_baseprofile *bprofile; + int ret = 0; + + /* Create the following controls: + * - enum control to select the active profile + * - one volume control for each profile hosting a vstep + * - Stop control on TFA1 devices + */ + + nr_controls = 2; /* Profile and stop control */ + + if (tfa98xx->flags & TFA98XX_FLAG_CALIBRATION_CTL) + nr_controls += 1; /* calibration */ + + /* allocate the tfa98xx_controls base on the nr of profiles */ + nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa); + for (prof = 0; prof < nprof; prof++) { + if (tfacont_get_max_vstep(tfa98xx->tfa, prof)) + nr_controls++; /* Playback Volume control */ + } + if (tfa98xx->tfa->tfa_family == 2) { + nr_controls++; /* Playback Volume control */ + } + + tfa98xx_controls = + devm_kzalloc(tfa98xx->codec->dev, + nr_controls * sizeof(tfa98xx_controls[0]), + GFP_KERNEL); + if (!tfa98xx_controls) + return -ENOMEM; + + /* Create a mixer item for selecting the active profile */ + name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL); + if (!name) + return -ENOMEM; + scnprintf(name, MAX_CONTROL_NAME, "%s Profile", tfa98xx->fw.name); + tfa98xx_controls[mix_index].name = name; + tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + tfa98xx_controls[mix_index].info = tfa98xx_info_profile; + tfa98xx_controls[mix_index].get = tfa98xx_get_profile; + tfa98xx_controls[mix_index].put = tfa98xx_set_profile; + // tfa98xx_controls[mix_index].private_value = profs; /* save number of profiles */ + mix_index++; + /* add new mixer control item 'SmartPA Mute' for MAX2 device. */ + if (tfa98xx->tfa->tfa_family == 2) { + tfa98xx_controls[mix_index].name = "SmartPA Mute"; + tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + tfa98xx_controls[mix_index].info = tfa98xx_info_PAmute; + tfa98xx_controls[mix_index].get = tfa98xx_get_PAmute; + tfa98xx_controls[mix_index].put = tfa98xx_set_PAmute; + mix_index++; + } + + /* create mixer items for each profile that has volume */ + for (prof = 0; prof < nprof; prof++) { + /* create an new empty profile */ + bprofile = devm_kzalloc(tfa98xx->codec->dev, sizeof(*bprofile), + GFP_KERNEL); + if (!bprofile) + return -ENOMEM; + + bprofile->len = 0; + bprofile->item_id = -1; + INIT_LIST_HEAD(&bprofile->list); + + /* copy profile name into basename until the . */ + get_profile_basename(bprofile->basename, + tfa_cont_profile_name(tfa98xx, prof)); + bprofile->len = strlen(bprofile->basename); + + /* + * search the profile list for a profile with basename, if it is not found then + * add it to the list and add a new mixer control (if it has vsteps) + * also, if it is a calibration profile, do not add it to the list + */ + if ((is_profile_in_list(bprofile->basename, bprofile->len) == + 0) && + is_calibration_profile( + tfa_cont_profile_name(tfa98xx, prof)) == 0) { + /* the profile is not present, add it to the list */ + list_add(&bprofile->list, &profile_list); + bprofile->item_id = id++; + + pr_debug("profile added [%d]: %s\n", bprofile->item_id, + bprofile->basename); + + if (tfacont_get_max_vstep(tfa98xx->tfa, prof)) { + name = devm_kzalloc(tfa98xx->codec->dev, + MAX_CONTROL_NAME, + GFP_KERNEL); + if (!name) + return -ENOMEM; + + scnprintf(name, MAX_CONTROL_NAME, + "%s %s Playback Volume", + tfa98xx->fw.name, bprofile->basename); + + tfa98xx_controls[mix_index].name = name; + tfa98xx_controls[mix_index].iface = + SNDRV_CTL_ELEM_IFACE_MIXER; + tfa98xx_controls[mix_index].info = + tfa98xx_info_vstep; + tfa98xx_controls[mix_index].get = + tfa98xx_get_vstep; + tfa98xx_controls[mix_index].put = + tfa98xx_set_vstep; + tfa98xx_controls[mix_index].private_value = + bprofile->item_id; /* save profile index */ + mix_index++; + } + } + + /* look for the basename profile in the list of mixer profiles and add the + container profile index to the supported samplerates of this mixer profile */ + add_sr_to_profile(tfa98xx, bprofile->basename, bprofile->len, + prof); + } + + /* set the number of user selectable profiles in the mixer */ + tfa98xx_mixer_profiles = id; + + /* Create a mixer item for stop control on TFA1 */ + name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, GFP_KERNEL); + if (!name) + return -ENOMEM; + + scnprintf(name, MAX_CONTROL_NAME, "%s Stop", tfa98xx->fw.name); + tfa98xx_controls[mix_index].name = name; + tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + tfa98xx_controls[mix_index].info = tfa98xx_info_stop_ctl; + tfa98xx_controls[mix_index].get = tfa98xx_get_stop_ctl; + tfa98xx_controls[mix_index].put = tfa98xx_set_stop_ctl; + mix_index++; + + if (tfa98xx->flags & TFA98XX_FLAG_CALIBRATION_CTL) { + name = devm_kzalloc(tfa98xx->codec->dev, MAX_CONTROL_NAME, + GFP_KERNEL); + if (!name) + return -ENOMEM; + + scnprintf(name, MAX_CONTROL_NAME, "%s Calibration", + tfa98xx->fw.name); + tfa98xx_controls[mix_index].name = name; + tfa98xx_controls[mix_index].iface = SNDRV_CTL_ELEM_IFACE_MIXER; + tfa98xx_controls[mix_index].info = tfa98xx_info_cal_ctl; + tfa98xx_controls[mix_index].get = tfa98xx_get_cal_ctl; + tfa98xx_controls[mix_index].put = tfa98xx_set_cal_ctl; + mix_index++; + } + + ret = snd_soc_add_codec_controls(tfa98xx->codec, tfa98xx_controls, + mix_index); + pr_info("create tfa98xx_controls ret=%d", ret); + +#ifdef TFA_NON_DSP_SOLUTION + ret = snd_soc_add_codec_controls(tfa98xx->codec, tfa987x_algo_controls, + ARRAY_SIZE(tfa987x_algo_controls)); + pr_info("create tfa987x_algo_controls ret=%d", ret); +#endif + if (!ret) { + ret = snd_soc_add_codec_controls( + tfa98xx->codec, nxp_spk_id_controls, + ARRAY_SIZE(nxp_spk_id_controls)); + } + + return ret; +} + +static void *tfa98xx_devm_kstrdup(struct device *dev, char *buf) +{ + char *str = devm_kzalloc(dev, strlen(buf) + 1, GFP_KERNEL); + if (!str) + return str; + memcpy(str, buf, strlen(buf)); + return str; +} + +static int +tfa98xx_append_i2c_address(struct device *dev, struct i2c_client *i2c, + struct snd_soc_dapm_widget *widgets, int num_widgets, + struct snd_soc_dai_driver *dai_drv, int num_dai) +{ + char buf[50]; + int i; + int i2cbus = i2c->adapter->nr; + int addr = i2c->addr; + if (dai_drv && num_dai > 0) + for (i = 0; i < num_dai; i++) { + memset(buf, 0x00, sizeof(buf)); + snprintf(buf, 50, "%s-%x-%x", dai_drv[i].name, i2cbus, + addr); + dai_drv[i].name = tfa98xx_devm_kstrdup(dev, buf); + pr_info("tfa98xx_append_i2c_address() dai_drv[%d].name = [%s]\n", + i, dai_drv[i].name); + + memset(buf, 0x00, sizeof(buf)); + snprintf(buf, 50, "%s-%x-%x", + dai_drv[i].playback.stream_name, i2cbus, addr); + dai_drv[i].playback.stream_name = + tfa98xx_devm_kstrdup(dev, buf); + pr_info("tfa98xx_append_i2c_address() dai_drv[%d].playback.stream_name = [%s]\n", + i, dai_drv[i].playback.stream_name); + + memset(buf, 0x00, sizeof(buf)); + snprintf(buf, 50, "%s-%x-%x", + dai_drv[i].capture.stream_name, i2cbus, addr); + dai_drv[i].capture.stream_name = + tfa98xx_devm_kstrdup(dev, buf); + pr_info("tfa98xx_append_i2c_address() dai_drv[%d].capture.stream_name = [%s]\n", + i, dai_drv[i].capture.stream_name); + } + + /* the idea behind this is convert: + * SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), + * into: + * SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback-2-36", 0, SND_SOC_NOPM, 0, 0), + */ + if (widgets && num_widgets > 0) + for (i = 0; i < num_widgets; i++) { + if (!widgets[i].sname) + continue; + if ((widgets[i].id == snd_soc_dapm_aif_in) || + (widgets[i].id == snd_soc_dapm_aif_out)) { + snprintf(buf, 50, "%s-%x-%x", widgets[i].sname, + i2cbus, addr); + widgets[i].sname = + tfa98xx_devm_kstrdup(dev, buf); + } + } + + return 0; +} + +static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_common[] = { + /* Stream widgets */ + SND_SOC_DAPM_AIF_IN("AIF IN", "AIF Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF OUT", "AIF Capture", 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_OUTPUT("OUTL"), + SND_SOC_DAPM_INPUT("AEC Loopback"), +}; + +static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_stereo[] = { + SND_SOC_DAPM_OUTPUT("OUTR"), +}; + +static struct snd_soc_dapm_widget tfa98xx_dapm_widgets_saam[] = { + SND_SOC_DAPM_INPUT("SAAM MIC"), +}; + +static struct snd_soc_dapm_widget tfa9888_dapm_inputs[] = { + SND_SOC_DAPM_INPUT("DMIC1"), + SND_SOC_DAPM_INPUT("DMIC2"), + SND_SOC_DAPM_INPUT("DMIC3"), + SND_SOC_DAPM_INPUT("DMIC4"), +}; + +static const struct snd_soc_dapm_route tfa98xx_dapm_routes_common[] = { + { "OUTL", NULL, "AIF IN" }, + { "AIF OUT", NULL, "AEC Loopback" }, +}; + +static const struct snd_soc_dapm_route tfa98xx_dapm_routes_saam[] = { + { "AIF OUT", NULL, "SAAM MIC" }, +}; + +static const struct snd_soc_dapm_route tfa98xx_dapm_routes_stereo[] = { + { "OUTR", NULL, "AIF IN" }, +}; + +static const struct snd_soc_dapm_route tfa9888_input_dapm_routes[] = { + { "AIF OUT", NULL, "DMIC1" }, + { "AIF OUT", NULL, "DMIC2" }, + { "AIF OUT", NULL, "DMIC3" }, + { "AIF OUT", NULL, "DMIC4" }, +}; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0) +static struct snd_soc_dapm_context * +snd_soc_codec_get_dapm(struct snd_soc_codec *codec) +{ + return &codec->dapm; +} +#endif + +static void tfa98xx_add_widgets(struct tfa98xx *tfa98xx) +{ + struct snd_soc_dapm_context *dapm = + snd_soc_codec_get_dapm(tfa98xx->codec); + struct snd_soc_dapm_widget *widgets; + unsigned int num_dapm_widgets = ARRAY_SIZE(tfa98xx_dapm_widgets_common); + + widgets = devm_kzalloc(&tfa98xx->i2c->dev, + sizeof(struct snd_soc_dapm_widget) * + ARRAY_SIZE(tfa98xx_dapm_widgets_common), + GFP_KERNEL); + if (!widgets) + return; + memcpy(widgets, tfa98xx_dapm_widgets_common, + sizeof(struct snd_soc_dapm_widget) * + ARRAY_SIZE(tfa98xx_dapm_widgets_common)); + + tfa98xx_append_i2c_address(&tfa98xx->i2c->dev, tfa98xx->i2c, widgets, + num_dapm_widgets, NULL, 0); + + snd_soc_dapm_new_controls(dapm, widgets, + ARRAY_SIZE(tfa98xx_dapm_widgets_common)); + snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_common, + ARRAY_SIZE(tfa98xx_dapm_routes_common)); + + if (tfa98xx->flags & TFA98XX_FLAG_STEREO_DEVICE) { + snd_soc_dapm_new_controls( + dapm, tfa98xx_dapm_widgets_stereo, + ARRAY_SIZE(tfa98xx_dapm_widgets_stereo)); + snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_stereo, + ARRAY_SIZE(tfa98xx_dapm_routes_stereo)); + } + + if (tfa98xx->flags & TFA98XX_FLAG_MULTI_MIC_INPUTS) { + snd_soc_dapm_new_controls(dapm, tfa9888_dapm_inputs, + ARRAY_SIZE(tfa9888_dapm_inputs)); + snd_soc_dapm_add_routes(dapm, tfa9888_input_dapm_routes, + ARRAY_SIZE(tfa9888_input_dapm_routes)); + } + + if (tfa98xx->flags & TFA98XX_FLAG_SAAM_AVAILABLE) { + snd_soc_dapm_new_controls( + dapm, tfa98xx_dapm_widgets_saam, + ARRAY_SIZE(tfa98xx_dapm_widgets_saam)); + snd_soc_dapm_add_routes(dapm, tfa98xx_dapm_routes_saam, + ARRAY_SIZE(tfa98xx_dapm_routes_saam)); + } +} + +/* I2C wrapper functions */ +enum Tfa98xx_Error tfa98xx_write_register16(struct tfa_device *tfa, + unsigned char subaddress, + unsigned short value) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + struct tfa98xx *tfa98xx; + int ret; + int retries = I2C_RETRIES; + + if (tfa == NULL) { + pr_err("No device available\n"); + return Tfa98xx_Error_Fail; + } + + tfa98xx = (struct tfa98xx *)tfa->data; + if (!tfa98xx || !tfa98xx->regmap) { + pr_err("No tfa98xx regmap available\n"); + return Tfa98xx_Error_Bad_Parameter; + } +retry: + ret = regmap_write(tfa98xx->regmap, subaddress, value); + if (ret < 0) { + pr_warn("i2c error, retries left: %d\n", retries); + if (retries) { + retries--; + msleep(I2C_RETRY_DELAY); + goto retry; + } + return Tfa98xx_Error_Fail; + } + if (tfa98xx_kmsg_regs) + dev_dbg(&tfa98xx->i2c->dev, " WR reg=0x%02x, val=0x%04x %s\n", + subaddress, value, ret < 0 ? "Error!!" : ""); + + if (tfa98xx_ftrace_regs) + tfa98xx_trace_printk("\tWR reg=0x%02x, val=0x%04x %s\n", + subaddress, value, + ret < 0 ? "Error!!" : ""); + return error; +} + +enum Tfa98xx_Error tfa98xx_read_register16(struct tfa_device *tfa, + unsigned char subaddress, + unsigned short *val) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + struct tfa98xx *tfa98xx; + unsigned int value; + int retries = I2C_RETRIES; + int ret; + + if (tfa == NULL) { + pr_err("No device available\n"); + return Tfa98xx_Error_Fail; + } + + tfa98xx = (struct tfa98xx *)tfa->data; + if (!tfa98xx || !tfa98xx->regmap) { + pr_err("No tfa98xx regmap available\n"); + return Tfa98xx_Error_Bad_Parameter; + } +retry: + ret = regmap_read(tfa98xx->regmap, subaddress, &value); + if (ret < 0) { + pr_warn("i2c error at subaddress 0x%x, retries left: %d\n", + subaddress, retries); + if (retries) { + retries--; + msleep(I2C_RETRY_DELAY); + goto retry; + } + return Tfa98xx_Error_Fail; + } + *val = value & 0xffff; + + if (tfa98xx_kmsg_regs) + dev_dbg(&tfa98xx->i2c->dev, "RD reg=0x%02x, val=0x%04x %s\n", + subaddress, *val, ret < 0 ? "Error!!" : ""); + if (tfa98xx_ftrace_regs) + tfa98xx_trace_printk("\tRD reg=0x%02x, val=0x%04x %s\n", + subaddress, *val, + ret < 0 ? "Error!!" : ""); + + return error; +} + +/* + * init external dsp + */ +enum Tfa98xx_Error tfa98xx_init_dsp(struct tfa_device *tfa) +{ + return Tfa98xx_Error_Not_Supported; +} + +int tfa98xx_get_dsp_status(struct tfa_device *tfa) +{ + return 0; +} + +/* + * write external dsp message + */ +enum Tfa98xx_Error tfa98xx_write_dsp(struct tfa_device *tfa, int num_bytes, + const char *command_buffer) +{ + return Tfa98xx_Error_Not_Supported; +} + +/* + * read external dsp message + */ +enum Tfa98xx_Error tfa98xx_read_dsp(struct tfa_device *tfa, int num_bytes, + unsigned char *result_buffer) +{ + return Tfa98xx_Error_Not_Supported; +} +/* + * write/read external dsp message + */ +enum Tfa98xx_Error tfa98xx_writeread_dsp(struct tfa_device *tfa, + int command_length, + void *command_buffer, + int result_length, void *result_buffer) +{ + return Tfa98xx_Error_Not_Supported; +} + +enum Tfa98xx_Error tfa98xx_read_data(struct tfa_device *tfa, unsigned char reg, + int len, unsigned char value[]) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + struct tfa98xx *tfa98xx; + struct i2c_client *tfa98xx_client; + int err; + int tries = 0; + struct i2c_msg msgs[] = { + { + .flags = 0, + .len = 1, + .buf = ®, + }, + { + .flags = I2C_M_RD, + .len = len, + .buf = value, + }, + }; + + if (tfa == NULL) { + pr_err("No device available\n"); + return Tfa98xx_Error_Fail; + } + + tfa98xx = (struct tfa98xx *)tfa->data; + if (tfa98xx->i2c) { + tfa98xx_client = tfa98xx->i2c; + msgs[0].addr = tfa98xx_client->addr; + msgs[1].addr = tfa98xx_client->addr; + + do { + err = i2c_transfer(tfa98xx_client->adapter, msgs, + ARRAY_SIZE(msgs)); + if (err != ARRAY_SIZE(msgs)) + msleep_interruptible(I2C_RETRY_DELAY); + } while ((err != ARRAY_SIZE(msgs)) && (++tries < I2C_RETRIES)); + + if (err != ARRAY_SIZE(msgs)) { + dev_err(&tfa98xx_client->dev, + "read transfer error %d\n", err); + error = Tfa98xx_Error_Fail; + } + + if (tfa98xx_kmsg_regs) + dev_dbg(&tfa98xx_client->dev, + "RD-DAT reg=0x%02x, len=%d\n", reg, len); + if (tfa98xx_ftrace_regs) + tfa98xx_trace_printk("\t\tRD-DAT reg=0x%02x, len=%d\n", + reg, len); + } else { + pr_err("No device available\n"); + error = Tfa98xx_Error_Fail; + } + return error; +} + +enum Tfa98xx_Error tfa98xx_write_raw(struct tfa_device *tfa, int len, + const unsigned char data[]) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + struct tfa98xx *tfa98xx; + int ret; + int retries = I2C_RETRIES; + + if (tfa == NULL) { + pr_err("No device available\n"); + return Tfa98xx_Error_Fail; + } + + tfa98xx = (struct tfa98xx *)tfa->data; + +retry: + ret = i2c_master_send(tfa98xx->i2c, data, len); + if (ret < 0) { + pr_warn("i2c error, retries left: %d\n", retries); + if (retries) { + retries--; + msleep(I2C_RETRY_DELAY); + goto retry; + } + } + + if (ret == len) { + if (tfa98xx_kmsg_regs) + dev_dbg(&tfa98xx->i2c->dev, " WR-RAW len=%d\n", len); + if (tfa98xx_ftrace_regs) + tfa98xx_trace_printk("\t\tWR-RAW len=%d\n", len); + return Tfa98xx_Error_Ok; + } + pr_err(" WR-RAW (len=%d) Error I2C send size mismatch %d\n", len, ret); + error = Tfa98xx_Error_Fail; + + return error; +} + +/* Interrupts management */ + +static void tfa98xx_interrupt_enable_tfa2(struct tfa98xx *tfa98xx, bool enable) +{ + /* Only for 0x72 we need to enable NOCLK interrupts */ + if (tfa98xx->flags & TFA98XX_FLAG_REMOVE_PLOP_NOISE) + tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_stnoclk, enable); + + if (tfa98xx->flags & TFA98XX_FLAG_LP_MODES) { + tfa_irq_ena(tfa98xx->tfa, 36, + enable); /* FIXME: IELP0 does not excist for 9912 */ + tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_stclpr, enable); + } +} + +/* Check if tap-detection can and shall be enabled. + * Configure SPK interrupt accordingly or setup polling mode + * Tap-detection shall be active if: + * - the service is enabled (tapdet_open), AND + * - the current profile is a tap-detection profile + * On TFA1 familiy of devices, activating tap-detection means enabling the SPK + * interrupt if available. + * We also update the tapdet_enabled and tapdet_poll variables. + */ +static void tfa98xx_tapdet_check_update(struct tfa98xx *tfa98xx) +{ + unsigned int enable = false; + + /* Support tap-detection on TFA1 family of devices */ + if ((tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) == 0) + return; + + if (tfa98xx->tapdet_open && + (tfa98xx->tapdet_profiles & (1 << tfa98xx->profile))) + enable = true; + + if (!gpio_is_valid(tfa98xx->irq_gpio)) { + /* interrupt not available, setup polling mode */ + tfa98xx->tapdet_poll = true; + if (enable) + queue_delayed_work(tfa98xx->tfa98xx_wq, + &tfa98xx->tapdet_work, HZ / 10); + else + cancel_delayed_work_sync(&tfa98xx->tapdet_work); + dev_dbg(tfa98xx->codec->dev, + "Polling for tap-detection: %s (%d; 0x%x, %d)\n", + enable ? "enabled" : "disabled", tfa98xx->tapdet_open, + tfa98xx->tapdet_profiles, tfa98xx->profile); + + } else { + dev_dbg(tfa98xx->codec->dev, + "Interrupt for tap-detection: %s (%d; 0x%x, %d)\n", + enable ? "enabled" : "disabled", tfa98xx->tapdet_open, + tfa98xx->tapdet_profiles, tfa98xx->profile); + /* enabled interrupt */ + tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_sttapdet, enable); + } + + /* check disabled => enabled transition to clear pending events */ + if (!tfa98xx->tapdet_enabled && enable) { + /* clear pending event if any */ + tfa_irq_clear(tfa98xx->tfa, tfa9912_irq_sttapdet); + } + + if (!tfa98xx->tapdet_poll) + tfa_irq_ena(tfa98xx->tfa, tfa9912_irq_sttapdet, + 1); /* enable again */ +} + +/* global enable / disable interrupts */ +static void tfa98xx_interrupt_enable(struct tfa98xx *tfa98xx, bool enable) +{ + if (tfa98xx->flags & TFA98XX_FLAG_SKIP_INTERRUPTS) + return; + + if (tfa98xx->tfa->tfa_family == 2) + tfa98xx_interrupt_enable_tfa2(tfa98xx, enable); +} + +/* Firmware management */ +static void tfa98xx_container_loaded(const struct firmware *cont, void *context) +{ + nxpTfaContainer_t *container; + struct tfa98xx *tfa98xx = context; + enum tfa_error tfa_err; + int container_size; + int ret; + + tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL; + + if (!cont) { + pr_err("Failed to read %s\n", fw_name); + return; + } + + pr_debug("loaded %s - size: %zu\n", fw_name, cont->size); + + if (tfa98xx_container == NULL) { + container = kzalloc(cont->size, GFP_KERNEL); + if (container == NULL) { + pr_err("Error allocating memory\n"); + return; + } + + container_size = cont->size; + memcpy(container, cont->data, container_size); + + pr_debug("%.2s%.2s\n", container->version, + container->subversion); + pr_debug("%.8s\n", container->customer); + pr_debug("%.8s\n", container->application); + pr_debug("%.8s\n", container->type); + pr_debug("%d ndev\n", container->ndev); + pr_debug("%d nprof\n", container->nprof); + + tfa_err = tfa_load_cnt(container, container_size); + if (tfa_err != tfa_error_ok) { + kfree(container); + dev_err(tfa98xx->dev, + "Cannot load container file, aborting\n"); + return; + } + + tfa98xx_container = container; + } else { + pr_debug("container file already loaded...\n"); + container = tfa98xx_container; + } + + tfa98xx->tfa->cnt = container; + + /* + i2c transaction limited to 64k + (Documentation/i2c/writing-clients) + */ + tfa98xx->tfa->buffer_size = 65536; + + if (tfa_dev_probe(tfa98xx->i2c->addr, tfa98xx->tfa) != 0) { + dev_err(tfa98xx->dev, "Failed to probe TFA98xx @ 0x%.2x\n", + tfa98xx->i2c->addr); + return; + } + + /* once the device without internal DSP, we should be using DSP HAL to send msg to host DSP. */ + if (1 == tfa98xx->tfa->is_probus_device) { + tfa98xx->tfa->has_msg = 1; + } else { + tfa98xx->tfa->has_msg = 0; + } + + tfa98xx->tfa->dev_idx = tfa_cont_get_idx(tfa98xx->tfa); + if (tfa98xx->tfa->dev_idx < 0) { + dev_err(tfa98xx->dev, + "Failed to find TFA98xx @ 0x%.2x in container file\n", + tfa98xx->i2c->addr); + return; + } + + /* Enable debug traces */ + tfa98xx->tfa->verbose = trace_level & 1; + + /* prefix is the application name from the cnt */ + tfa_cnt_get_app_name(tfa98xx->tfa, tfa98xx->fw.name); + + /* set default profile/vstep */ + tfa98xx->profile = 0; + tfa98xx->vstep = 0; + + /* Override default profile if requested */ + if (strcmp(dflt_prof_name, "")) { + unsigned int i; + int nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa); + for (i = 0; i < nprof; i++) { + if (strcmp(tfa_cont_profile_name(tfa98xx, i), + dflt_prof_name) == 0) { + tfa98xx->profile = i; + dev_info( + tfa98xx->dev, + "changing default profile to %s (%d)\n", + dflt_prof_name, tfa98xx->profile); + break; + } + } + if (i >= nprof) + dev_info( + tfa98xx->dev, + "Default profile override failed (%s profile not found)\n", + dflt_prof_name); + } + + tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_OK; + pr_debug("Firmware init complete\n"); + + if (no_start != 0) + return; + + /* Only controls for master device */ + if (tfa98xx->tfa->dev_idx == 0) + tfa98xx_create_controls(tfa98xx); + + tfa98xx_inputdev_check_register(tfa98xx); + + if (tfa_is_cold(tfa98xx->tfa) == 0) { + pr_debug("Warning: device 0x%.2x is still warm\n", + tfa98xx->i2c->addr); + tfa_reset(tfa98xx->tfa); + } + + /* Preload settings using internal clock on TFA2 */ + if ((tfa98xx->tfa->tfa_family == 2) && + (0 == tfa98xx->tfa->is_probus_device)) { + mutex_lock(&tfa98xx->dsp_lock); + pr_info("will be using internal clock to preload MAX2 TFA settings.\n"); + ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, + tfa98xx->vstep); + if (ret == Tfa98xx_Error_Not_Supported) + tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL; + + /* we should be power-down device when parameter is loaded. */ + tfa_dev_stop(tfa98xx->tfa); + ret = tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED; + + mutex_unlock(&tfa98xx->dsp_lock); + } + + tfa98xx_interrupt_enable(tfa98xx, true); +} + +static int tfa98xx_load_container(struct tfa98xx *tfa98xx) +{ + const struct firmware *firmware; + int rc = 0; + + tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_PENDING; + mutex_lock(&tfa98xx_mutex); + rc = request_firmware(&firmware, fw_name, tfa98xx->dev); + if (rc < 0) { + mutex_unlock(&tfa98xx_mutex); + return rc; + } + tfa98xx_container_loaded(firmware, tfa98xx); + release_firmware(firmware); + mutex_unlock(&tfa98xx_mutex); + + return rc; +} + +static void tfa98xx_tapdet(struct tfa98xx *tfa98xx) +{ + unsigned int tap_pattern; + int btn; + + /* check tap pattern (BTN_0 is "error" wrong tap indication */ + tap_pattern = tfa_get_tap_pattern(tfa98xx->tfa); + switch (tap_pattern) { + case 0xffffffff: + pr_info("More than 4 taps detected! (flagTapPattern = -1)\n"); + btn = BTN_0; + break; + case 0xfffffffe: + case 0xfe: + pr_info("Illegal tap detected!\n"); + btn = BTN_0; + break; + case 0: + pr_info("Unrecognized pattern! (flagTapPattern = 0)\n"); + btn = BTN_0; + break; + default: + pr_info("Detected pattern: %d\n", tap_pattern); + btn = BTN_0 + tap_pattern; + break; + } + + input_report_key(tfa98xx->input, btn, 1); + input_report_key(tfa98xx->input, btn, 0); + input_sync(tfa98xx->input); + + /* acknowledge event done by clearing interrupt */ +} + +static void tfa98xx_tapdet_work(struct work_struct *work) +{ + struct tfa98xx *tfa98xx; + + //TODO check is this is still needed for tap polling + tfa98xx = container_of(work, struct tfa98xx, tapdet_work.work); + + if (tfa_irq_get(tfa98xx->tfa, tfa9912_irq_sttapdet)) + tfa98xx_tapdet(tfa98xx); + + queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->tapdet_work, HZ / 10); +} + +static void tfa98xx_monitor(struct work_struct *work) +{ +#if 0 + struct tfa98xx *tfa98xx; + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + tfa98xx = container_of(work, struct tfa98xx, monitor_work.work); + + /* Check for tap-detection - bypass monitor if it is active */ + if (!tfa98xx->input) { + mutex_lock(&tfa98xx->dsp_lock); + error = tfa_status(tfa98xx->tfa); + mutex_unlock(&tfa98xx->dsp_lock); + if (error == Tfa98xx_Error_DSP_not_running) { + if (tfa98xx->dsp_init == TFA98XX_DSP_INIT_DONE) { + tfa98xx->dsp_init = TFA98XX_DSP_INIT_RECOVER; + queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->init_work, 0); + } + } + } + + /* reschedule */ + queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->monitor_work, 5*HZ); +#endif +} + +static void tfa98xx_dsp_init(struct tfa98xx *tfa98xx) +{ + int ret; + bool failed = false; + bool reschedule = false; + bool sync = false; + + if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) { + pr_debug("%s Skipping tfa_dev_start (no FW: %d)\n", __func__, + tfa98xx->dsp_fw_state); + return; + } + + if (tfa98xx->dsp_init == TFA98XX_DSP_INIT_DONE) { + pr_debug("%s Stream already started, skipping DSP power-on\n", + __func__); + return; + } + + mutex_lock(&tfa98xx->dsp_lock); + + tfa98xx->dsp_init = TFA98XX_DSP_INIT_PENDING; + + pr_debug("[NXP] %s init_count=%d\n", __func__, tfa98xx->init_count); + if (tfa98xx->init_count < TF98XX_MAX_DSP_START_TRY_COUNT) { + /* directly try to start DSP */ + ret = tfa98xx_tfa_start(tfa98xx, tfa98xx->profile, + tfa98xx->vstep); + if (ret == Tfa98xx_Error_Not_Supported) { + tfa98xx->dsp_fw_state = TFA98XX_DSP_FW_FAIL; + dev_err(&tfa98xx->i2c->dev, "Failed starting device\n"); + failed = true; + } else if (ret != Tfa98xx_Error_Ok) { + /* It may fail as we may not have a valid clock at that + * time, so re-schedule and re-try later. + */ + dev_err(&tfa98xx->i2c->dev, + "tfa_dev_start failed! (err %d) - %d\n", ret, + tfa98xx->init_count); + reschedule = true; + } else { + sync = true; + + /* Subsystem ready, tfa init complete */ + tfa98xx->dsp_init = TFA98XX_DSP_INIT_DONE; + dev_dbg(&tfa98xx->i2c->dev, + "tfa_dev_start success (%d)\n", + tfa98xx->init_count); + /* cancel other pending init works */ + cancel_delayed_work(&tfa98xx->init_work); + tfa98xx->init_count = 0; + } + } else { + /* exceeded max number ot start tentatives, cancel start */ + dev_err(&tfa98xx->i2c->dev, "Failed starting device (%d)\n", + tfa98xx->init_count); + failed = true; + } + if (reschedule) { + /* reschedule this init work for later */ + queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->init_work, + msecs_to_jiffies(5)); + tfa98xx->init_count++; + } + if (failed) { + tfa98xx->dsp_init = TFA98XX_DSP_INIT_FAIL; + /* cancel other pending init works */ + cancel_delayed_work(&tfa98xx->init_work); + tfa98xx->init_count = 0; + } + mutex_unlock(&tfa98xx->dsp_lock); + + if (sync) { + /* check if all devices have started */ + bool do_sync; + mutex_lock(&tfa98xx_mutex); + + if (tfa98xx_sync_count < tfa98xx_device_count) + tfa98xx_sync_count++; + + do_sync = (tfa98xx_sync_count >= tfa98xx_device_count); + mutex_unlock(&tfa98xx_mutex); + + /* when all devices have started then unmute */ + if (do_sync) { + tfa98xx_sync_count = 0; + list_for_each_entry (tfa98xx, &tfa98xx_device_list, + list) { + mutex_lock(&tfa98xx->dsp_lock); + tfa_dev_set_state(tfa98xx->tfa, + TFA_STATE_UNMUTE, 0); + + /* + * start monitor thread to check IC status bit + * periodically, and re-init IC to recover if + * needed. + */ + if (tfa98xx->tfa->tfa_family == 1) + queue_delayed_work( + tfa98xx->tfa98xx_wq, + &tfa98xx->monitor_work, 1 * HZ); + mutex_unlock(&tfa98xx->dsp_lock); + } + } + } + + return; +} + +static void tfa98xx_dsp_init_work(struct work_struct *work) +{ + struct tfa98xx *tfa98xx = + container_of(work, struct tfa98xx, init_work.work); + + tfa98xx_dsp_init(tfa98xx); +} + +static void tfa98xx_interrupt(struct work_struct *work) +{ + struct tfa98xx *tfa98xx = + container_of(work, struct tfa98xx, interrupt_work.work); + + if (tfa98xx->flags & TFA98XX_FLAG_TAPDET_AVAILABLE) { + /* check for tap interrupt */ + if (tfa_irq_get(tfa98xx->tfa, tfa9912_irq_sttapdet)) { + tfa98xx_tapdet(tfa98xx); + + /* clear interrupt */ + tfa_irq_clear(tfa98xx->tfa, tfa9912_irq_sttapdet); + } + } /* TFA98XX_FLAG_TAPDET_AVAILABLE */ + + if (tfa98xx->flags & TFA98XX_FLAG_REMOVE_PLOP_NOISE) { + int start_triggered; + + mutex_lock(&tfa98xx->dsp_lock); + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ + start_triggered = + tfa_plop_noise_interrupt(tfa98xx->tfa, tfa98xx->profile, + tfa98xx->vstep, + tfa98xx->pcm_format); + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ + /* Only enable when the return value is 1, otherwise the interrupt is triggered twice */ + if (start_triggered) + tfa98xx_interrupt_enable(tfa98xx, true); + mutex_unlock(&tfa98xx->dsp_lock); + } /* TFA98XX_FLAG_REMOVE_PLOP_NOISE */ + + if (tfa98xx->flags & TFA98XX_FLAG_LP_MODES) { + tfa_lp_mode_interrupt(tfa98xx->tfa); + } /* TFA98XX_FLAG_LP_MODES */ + + /* unmask interrupts masked in IRQ handler */ + tfa_irq_unmask(tfa98xx->tfa); +} + +static int tfa98xx_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + unsigned int sr; + int len, prof, nprof, idx = 0; + char *basename; + + /* + * Support CODEC to CODEC links, + * these are called with a NULL runtime pointer. + */ + if (!substream->runtime) + return 0; + + if (pcm_no_constraint != 0) + return 0; + + if (no_start != 0) + return 0; + + if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) { + dev_info(codec->dev, "Container file not loaded\n"); + return -EINVAL; + } + + basename = kzalloc(MAX_CONTROL_NAME, GFP_KERNEL); + if (!basename) + return -ENOMEM; + + /* copy profile name into basename until the . */ + get_profile_basename(basename, + tfa_cont_profile_name(tfa98xx, tfa98xx->profile)); + len = strlen(basename); + + /* loop over all profiles and get the supported samples rate(s) from + * the profiles with the same basename + */ + nprof = tfa_cnt_get_dev_nprof(tfa98xx->tfa); + tfa98xx->rate_constraint.list = &tfa98xx->rate_constraint_list[0]; + tfa98xx->rate_constraint.count = 0; + for (prof = 0; prof < nprof; prof++) { + if (0 == strncmp(basename, tfa_cont_profile_name(tfa98xx, prof), + len)) { + /* Check which sample rate is supported with current profile, + * and enforce this. + */ + sr = tfa98xx_get_profile_sr(tfa98xx->tfa, prof); + if (!sr) + dev_info( + codec->dev, + "Unable to identify supported sample rate\n"); + + if (tfa98xx->rate_constraint.count >= + TFA98XX_NUM_RATES) { + dev_err(codec->dev, "too many sample rates\n"); + } else { + tfa98xx->rate_constraint_list[idx++] = sr; + tfa98xx->rate_constraint.count += 1; + } + } + } + + kfree(basename); + + /* as QUALCOMM FAE suggested, we don't need to calling 'snd_pcm_hw_constraint_list' on QUALCOMM platform. */ + return 0; +} + +static int tfa98xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, + unsigned int freq, int dir) +{ + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec_dai->codec); + + tfa98xx->sysclk = freq; + return 0; +} + +static int tfa98xx_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int slot_width) +{ + pr_debug("\n"); + return 0; +} + +static int tfa98xx_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(dai->codec); + struct snd_soc_codec *codec = dai->codec; + + pr_debug("fmt=0x%x\n", fmt); + + /* Supported mode: regular I2S, slave, or PDM */ + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != + SND_SOC_DAIFMT_CBS_CFS) { + dev_err(codec->dev, "Invalid Codec master mode\n"); + return -EINVAL; + } + break; + case SND_SOC_DAIFMT_PDM: + break; + default: + dev_err(codec->dev, "Unsupported DAI format %d\n", + fmt & SND_SOC_DAIFMT_FORMAT_MASK); + return -EINVAL; + } + + tfa98xx->audio_mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK; + + return 0; +} + +static int tfa98xx_get_fssel(unsigned int rate) +{ + int i; + for (i = 0; i < ARRAY_SIZE(rate_to_fssel); i++) { + if (rate_to_fssel[i].rate == rate) { + return rate_to_fssel[i].fssel; + } + } + return -EINVAL; +} + +static int tfa98xx_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + unsigned int rate; + int prof_idx; + + /* Supported */ + rate = params_rate(params); + pr_debug("Requested rate: %d, sample size: %d, physical size: %d\n", + rate, snd_pcm_format_width(params_format(params)), + snd_pcm_format_physical_width(params_format(params))); + + if (no_start != 0) + return 0; + + /* check if samplerate is supported for this mixer profile */ + prof_idx = get_profile_id_for_sr(tfa98xx_mixer_profile, rate); + if (prof_idx < 0) { + pr_err("tfa98xx: invalid sample rate %d.\n", rate); + return -EINVAL; + } + pr_debug("mixer profile:container profile = [%d:%d]\n", + tfa98xx_mixer_profile, prof_idx); + + /* update 'real' profile (container profile) */ + tfa98xx->profile = prof_idx; + + /* update to new rate */ + tfa98xx->rate = rate; + + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ + tfa98xx->pcm_format = snd_pcm_format_width(params_format(params)); + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ + + return 0; +} + +#ifdef TFA_NON_DSP_SOLUTION +extern int send_tfa_cal_in_band(void *buf, int cmd_size); +static uint8_t bytes[3 * 3 + 1] = { 0 }; + +enum Tfa98xx_Error tfa98xx_adsp_send_calib_values(void) +{ + struct tfa98xx *tfa98xx; + int ret = 0; + int value = 0, nr, dsp_cal_value = 0; + + /* if the calibration value was sent to host DSP, we clear flag only (stereo case). */ + if ((tfa98xx_device_count > 1) && (tfa98xx_device_count == bytes[0])) { + pr_info("The calibration value was sent to host DSP.\n"); + bytes[0] = 0; + return Tfa98xx_Error_Ok; + } + + nr = 4; + /* read calibrated impendance from all devices. */ + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + struct tfa_device *tfa = tfa98xx->tfa; + if (TFA_GET_BF(tfa, MTPEX) == 1) { + value = tfa_dev_mtp_get(tfa, TFA_MTP_RE25); + dsp_cal_value = (value * 65536) / 1000; + pr_info("Device 0x%x cal value is 0x%d\n", + tfa98xx->i2c->addr, dsp_cal_value); + + bytes[nr++] = (uint8_t)((dsp_cal_value >> 16) & 0xff); + bytes[nr++] = (uint8_t)((dsp_cal_value >> 8) & 0xff); + bytes[nr++] = (uint8_t)(dsp_cal_value & 0xff); + bytes[0] += 1; + } + } + + /*for mono case, we will copy primary channel data to secondary channel. */ + if (1 == tfa98xx_device_count) { + memcpy(&bytes[7], &bytes[4], sizeof(char) * 3); + } + pr_info("tfa98xx_device_count=%d bytes[0]=%d\n", tfa98xx_device_count, + bytes[0]); + + /* we will send it to host DSP algorithm once calibraion value loaded from all device. */ + if (tfa98xx_device_count == bytes[0]) { + bytes[1] = 0x00; + bytes[2] = 0x81; + bytes[3] = 0x05; + + pr_info("calibration value send to host DSP.\n"); + ret = send_tfa_cal_in_band(&bytes[1], sizeof(bytes) - 1); + msleep(10); + + /* for mono case, we should clear flag here. */ + if (1 == tfa98xx_device_count) + bytes[0] = 0; + + } else { + pr_err("load calibration data from device failed.\n"); + ret = Tfa98xx_Error_Bad_Parameter; + } + + return ret; +} + +static int tfa98xx_send_mute_cmd(void) +{ + uint8_t cmd[9] = { + 0x04, 0x81, 0x04, 0x00, 0x00, 0xff, 0x00, 0x00, 0xff + }; + pr_info("send mute command to host DSP.\n"); + return send_tfa_cal_in_band(&cmd[0], sizeof(cmd)); +} +#endif + +static int tfa98xx_mute(struct snd_soc_dai *dai, int mute, int stream) +{ + struct snd_soc_codec *codec = dai->codec; + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + + dev_dbg(&tfa98xx->i2c->dev, "%s: state: %d\n", __func__, mute); + + if (no_start) { + pr_debug( + "no_start parameter set no tfa_dev_start or tfa_dev_stop, returning\n"); + return 0; + } + if (TFA98XX_DEVICE_MUTE_ON == tfa98xx->tfa_mute_mode) { + pr_debug( + "%s: if Mute mode is enalbed, we don't need to power-on device. \n", + __func__); + return 0; + } + + if (mute) { + /* stop DSP only when both playback and capture streams + * are deactivated + */ + if (stream == SNDRV_PCM_STREAM_PLAYBACK) + tfa98xx->pstream = 0; + else + tfa98xx->cstream = 0; + if (tfa98xx->pstream != 0 || tfa98xx->cstream != 0) + return 0; + + mutex_lock(&tfa98xx_mutex); + tfa98xx_sync_count = 0; + mutex_unlock(&tfa98xx_mutex); + + cancel_delayed_work_sync(&tfa98xx->monitor_work); + + cancel_delayed_work_sync(&tfa98xx->init_work); + if (tfa98xx->dsp_fw_state != TFA98XX_DSP_FW_OK) + return 0; + mutex_lock(&tfa98xx->dsp_lock); +#ifdef TFA_NON_DSP_SOLUTION + tfa98xx_send_mute_cmd(); + msleep(60); +#endif + tfa_dev_stop(tfa98xx->tfa); + tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED; + mutex_unlock(&tfa98xx->dsp_lock); + } else { + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + tfa98xx->pstream = 1; +#ifdef TFA_NON_DSP_SOLUTION + if (tfa98xx->tfa->is_probus_device) { + tfa98xx_adsp_send_calib_values(); + } +#endif + } else { + tfa98xx->cstream = 1; + } + +#if 0 + /* Start DSP with async mode.*/ + if (tfa98xx->dsp_init != TFA98XX_DSP_INIT_PENDING) + queue_delayed_work(tfa98xx->tfa98xx_wq, + &tfa98xx->init_work, 0); +#else + /* Start DSP with sync mode.*/ + pr_debug("[NXP] %s dsp_init=%d\n", __func__, tfa98xx->dsp_init); + if (tfa98xx->dsp_init != TFA98XX_DSP_INIT_PENDING) + tfa98xx_dsp_init(tfa98xx); +#endif + } + + return 0; +} + +static const struct snd_soc_dai_ops tfa98xx_dai_ops = { + .startup = tfa98xx_startup, + .set_fmt = tfa98xx_set_fmt, + .set_sysclk = tfa98xx_set_dai_sysclk, + .set_tdm_slot = tfa98xx_set_tdm_slot, + .hw_params = tfa98xx_hw_params, + .mute_stream = tfa98xx_mute, +}; + +static struct snd_soc_dai_driver tfa98xx_dai[] = { + { + .name = "tfa98xx-aif", + .id = 1, + .playback = { + .stream_name = "AIF Playback", + .channels_min = 1, + .channels_max = 4, + .rates = TFA98XX_RATES, + .formats = TFA98XX_FORMATS, + }, + .capture = { + .stream_name = "AIF Capture", + .channels_min = 1, + .channels_max = 4, + .rates = TFA98XX_RATES, + .formats = TFA98XX_FORMATS, + }, + .ops = &tfa98xx_dai_ops, +/* .symmetric_rates = 1, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) + .symmetric_channels = 1, + .symmetric_samplebits = 1, +#endif*/ + }, +}; + +static int tfa98xx_probe(struct snd_soc_codec *codec) +{ + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + int ret; + + pr_debug("\n"); + + /* setup work queue, will be used to initial DSP on first boot up */ + tfa98xx->tfa98xx_wq = create_singlethread_workqueue("tfa98xx"); + if (!tfa98xx->tfa98xx_wq) + return -ENOMEM; + + INIT_DELAYED_WORK(&tfa98xx->init_work, tfa98xx_dsp_init_work); + INIT_DELAYED_WORK(&tfa98xx->monitor_work, tfa98xx_monitor); + INIT_DELAYED_WORK(&tfa98xx->interrupt_work, tfa98xx_interrupt); + INIT_DELAYED_WORK(&tfa98xx->tapdet_work, tfa98xx_tapdet_work); + + tfa98xx->codec = codec; + + ret = tfa98xx_load_container(tfa98xx); + pr_debug("Container loading requested: %d\n", ret); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0) + codec->control_data = tfa98xx->regmap; + ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP); + if (ret != 0) { + dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); + return ret; + } +#endif + tfa98xx_add_widgets(tfa98xx); + + dev_info(codec->dev, "tfa98xx codec registered (%s)", tfa98xx->fw.name); + + return ret; +} + +static int tfa98xx_remove(struct snd_soc_codec *codec) +{ + struct tfa98xx *tfa98xx = snd_soc_codec_get_drvdata(codec); + pr_debug("\n"); + + tfa98xx_interrupt_enable(tfa98xx, false); + + tfa98xx_inputdev_unregister(tfa98xx); + + cancel_delayed_work_sync(&tfa98xx->interrupt_work); + cancel_delayed_work_sync(&tfa98xx->monitor_work); + cancel_delayed_work_sync(&tfa98xx->init_work); + cancel_delayed_work_sync(&tfa98xx->tapdet_work); + + if (tfa98xx->tfa98xx_wq) + destroy_workqueue(tfa98xx->tfa98xx_wq); + + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0) +static struct regmap *tfa98xx_get_regmap(struct device *dev) +{ + struct tfa98xx *tfa98xx = dev_get_drvdata(dev); + + return tfa98xx->regmap; +} +#endif +static struct snd_soc_codec_driver soc_codec_dev_tfa98xx = { + .probe = tfa98xx_probe, + .remove = tfa98xx_remove, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0) + .get_regmap = tfa98xx_get_regmap, +#endif +}; + +static bool tfa98xx_writeable_register(struct device *dev, unsigned int reg) +{ + /* enable read access for all registers */ + return 1; +} + +static bool tfa98xx_readable_register(struct device *dev, unsigned int reg) +{ + /* enable read access for all registers */ + return 1; +} + +static bool tfa98xx_volatile_register(struct device *dev, unsigned int reg) +{ + /* enable read access for all registers */ + return 1; +} + +static const struct regmap_config tfa98xx_regmap = { + .reg_bits = 8, + .val_bits = 16, + + .max_register = TFA98XX_MAX_REGISTER, + .writeable_reg = tfa98xx_writeable_register, + .readable_reg = tfa98xx_readable_register, + .volatile_reg = tfa98xx_volatile_register, + .cache_type = REGCACHE_NONE, +}; + +static void tfa98xx_irq_tfa2(struct tfa98xx *tfa98xx) +{ + /* + * mask interrupts + * will be unmasked after handling interrupts in workqueue + */ + tfa_irq_mask(tfa98xx->tfa); + queue_delayed_work(tfa98xx->tfa98xx_wq, &tfa98xx->interrupt_work, 0); +} + +static irqreturn_t tfa98xx_irq(int irq, void *data) +{ + struct tfa98xx *tfa98xx = data; + + if (tfa98xx->tfa->tfa_family == 2) + tfa98xx_irq_tfa2(tfa98xx); + + return IRQ_HANDLED; +} + +static int tfa98xx_ext_reset(struct tfa98xx *tfa98xx) +{ + if (tfa98xx && gpio_is_valid(tfa98xx->reset_gpio)) { + gpio_set_value_cansleep(tfa98xx->reset_gpio, 1); + msleep(10); + gpio_set_value_cansleep(tfa98xx->reset_gpio, 0); + msleep(10); + } + return 0; +} + +static int tfa98xx_parse_dt(struct device *dev, struct tfa98xx *tfa98xx, + struct device_node *np) +{ + tfa98xx->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); + if (tfa98xx->reset_gpio < 0) + dev_dbg(dev, + "No reset GPIO provided, will not HW reset device\n"); + + tfa98xx->irq_gpio = of_get_named_gpio(np, "irq-gpio", 0); + if (tfa98xx->irq_gpio < 0) + dev_dbg(dev, "No IRQ GPIO provided.\n"); + + return 0; +} + +static ssize_t tfa98xx_reg_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tfa98xx *tfa98xx = dev_get_drvdata(dev); + + if (count != 1) { + pr_debug("invalid register address"); + return -EINVAL; + } + + tfa98xx->reg = buf[0]; + + return 1; +} + +static ssize_t tfa98xx_rw_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tfa98xx *tfa98xx = dev_get_drvdata(dev); + u8 *data; + int ret; + int retries = I2C_RETRIES; + + data = kmalloc(count + 1, GFP_KERNEL); + if (data == NULL) { + pr_debug("can not allocate memory\n"); + return -ENOMEM; + } + + data[0] = tfa98xx->reg; + memcpy(&data[1], buf, count); + +retry: + ret = i2c_master_send(tfa98xx->i2c, data, count + 1); + if (ret < 0) { + pr_warn("i2c error, retries left: %d\n", retries); + if (retries) { + retries--; + msleep(I2C_RETRY_DELAY); + goto retry; + } + } + + kfree(data); + + /* the number of data bytes written without the register address */ + return ((ret > 1) ? count : -EIO); +} + +static ssize_t tfa98xx_rw_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, + loff_t off, size_t count) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct tfa98xx *tfa98xx = dev_get_drvdata(dev); + struct i2c_msg msgs[] = { + { + .addr = tfa98xx->i2c->addr, + .flags = 0, + .len = 1, + .buf = &tfa98xx->reg, + }, + { + .addr = tfa98xx->i2c->addr, + .flags = I2C_M_RD, + .len = count, + .buf = buf, + }, + }; + int ret; + int retries = I2C_RETRIES; +retry: + ret = i2c_transfer(tfa98xx->i2c->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret < 0) { + pr_warn("i2c error, retries left: %d\n", retries); + if (retries) { + retries--; + msleep(I2C_RETRY_DELAY); + goto retry; + } + return ret; + } + /* ret contains the number of i2c transaction */ + /* return the number of bytes read */ + return ((ret > 1) ? count : -EIO); +} + +static struct bin_attribute dev_attr_rw = { + .attr = { + .name = "rw", + .mode = S_IRUSR | S_IWUSR, + }, + .size = 0, + .read = tfa98xx_rw_read, + .write = tfa98xx_rw_write, +}; + +static struct bin_attribute dev_attr_reg = { + .attr = { + .name = "reg", + .mode = S_IWUSR, + }, + .size = 0, + .read = NULL, + .write = tfa98xx_reg_write, +}; + +static int tfa98xx_misc_device_profile_open(struct inode *inode, + struct file *file) +{ + struct tfa98xx *tfa98xx = container_of(file->private_data, + struct tfa98xx, tfa98xx_profile); + //pr_info("entry tfa98xx=%p\n", tfa98xx); + if (tfa98xx) { + file->private_data = tfa98xx; + return 0; + } else { + file->private_data = NULL; + return -EINVAL; + } +} + +static ssize_t tfa98xx_misc_device_profile_write(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct tfa98xx *tfa98xx = file->private_data; + char name[100] = { 0 }; + int ret = 0; + int profileID = 0; + + //pr_info("entry count=%d\n", (int)count); + + if (NULL == tfa98xx) { + pr_err("%s tfa98xx is NULL.\n", __func__); + return -EINVAL; + } + /*if (count != 1) { + pr_err("%s invalid register address\n", __func__); + return -EINVAL; + }*/ + memset(name, 0x00, sizeof(name)); + ret = copy_from_user(name, user_buf, count); + //pr_info("profile name=%s\n", name); + + /* search profile name and return ID. */ + profileID = get_profile_id_by_name(name, strlen(name)); + if (profileID < 0) { + pr_err("didn't find profile from list.\n"); + return 0; + } else { + int prof_idx = get_profile_id_for_sr(profileID, tfa98xx->rate); + if (prof_idx < 0) { + pr_err("sample rate [%d] not supported for this profile(%d).\n", + tfa98xx->rate, profileID); + return 0; + } else { + tfa98xx_mixer_profile = profileID; + tfa98xx->profile = prof_idx; + tfa98xx->vstep = tfa98xx->prof_vsteps[prof_idx]; + //pr_info("update profile index (%d:%d) succeeded\n", profileID, prof_idx); + } + } + + return count; +} + +static int tfa98xx_misc_device_reg_open(struct inode *inode, struct file *file) +{ + struct tfa98xx *tfa98xx = + container_of(file->private_data, struct tfa98xx, tfa98xx_reg); + if (tfa98xx) { + file->private_data = tfa98xx; + return 0; + } else { + file->private_data = NULL; + return -EINVAL; + } +} + +static ssize_t tfa98xx_misc_device_reg_write(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct tfa98xx *tfa98xx = file->private_data; + u8 address = 0; + int ret = 0; + + //pr_info("entry count=%d\n", (int)count); + + if (NULL == tfa98xx) { + pr_err("tfa98xx is NULL.\n"); + return -EINVAL; + } + + if (count != 1) { + pr_err("invalid register address\n"); + return -EINVAL; + } + + ret = copy_from_user(&address, user_buf, count); + if (ret) { + pr_err("copy data from user space failed.\n"); + } + + tfa98xx->reg = address; + //pr_info("tfa98xx->reg=0x%x\n", tfa98xx->reg); + + return count; +} + +static int tfa98xx_misc_device_rw_open(struct inode *inode, struct file *file) +{ + struct tfa98xx *tfa98xx = + container_of(file->private_data, struct tfa98xx, tfa98xx_rw); + if (tfa98xx) { + file->private_data = tfa98xx; + return 0; + } else { + file->private_data = NULL; + return -EINVAL; + } +} + +static ssize_t tfa98xx_misc_device_rw_read(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct tfa98xx *tfa98xx = file->private_data; + struct i2c_msg msgs[] = { + { + .addr = tfa98xx->i2c->addr, + .flags = 0, + .len = 1, + .buf = &tfa98xx->reg, + }, + { + .addr = tfa98xx->i2c->addr, + .flags = I2C_M_RD, + .len = count, + .buf = NULL, + }, + }; + + u8 *data; + int ret; + int retries = I2C_RETRIES; + + //pr_info("entry count=%d\n", (int)count); + + data = kmalloc(count + 1, GFP_KERNEL); + if (data == NULL) { + pr_debug("can not allocate memory\n"); + return -ENOMEM; + } + + msgs[1].buf = data; + +retry: + ret = i2c_transfer(tfa98xx->i2c->adapter, msgs, ARRAY_SIZE(msgs)); + //pr_info("i2c_transfer ret=%d\n", ret); + + if (ret < 0) { + pr_warn("i2c error, retries left: %d\n", retries); + if (retries) { + retries--; + msleep(I2C_RETRY_DELAY); + goto retry; + } + + kfree(data); + return ret; + } else if (ret > 1) { + int ret_cpy = copy_to_user(user_buf, data, count); + if (ret_cpy) { + pr_err("copy to user space failed.\n"); + } + } + + /* ret contains the number of i2c transaction */ + /* return the number of bytes read */ + kfree(data); + return ((ret > 1) ? count : -EIO); +} + +static ssize_t tfa98xx_misc_device_rw_write(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct tfa98xx *tfa98xx = file->private_data; + u8 *data; + int ret; + int retries = I2C_RETRIES; + //pr_info("entry count=%d\n", (int)count); + + data = kmalloc(count + 1, GFP_KERNEL); + if (data == NULL) { + pr_debug("can not allocate memory\n"); + return -ENOMEM; + } + + //pr_info("tfa98xx->reg=0x%x\n", tfa98xx->reg); + + data[0] = tfa98xx->reg; + if (copy_from_user(&data[1], user_buf, count)) { + pr_err("copy to user space failed.\n"); + } + +retry: + ret = i2c_master_send(tfa98xx->i2c, data, count + 1); + if (ret < 0) { + pr_warn("i2c error, retries left: %d\n", retries); + if (retries) { + retries--; + msleep(I2C_RETRY_DELAY); + goto retry; + } + } + + kfree(data); + + /* the number of data bytes written without the register address */ + return ((ret > 1) ? count : -EIO); +} + +static int tfa98xx_misc_device_rpc_open(struct inode *inode, struct file *file) +{ + struct tfa98xx *tfa98xx = + container_of(file->private_data, struct tfa98xx, tfa98xx_rpc); + if (tfa98xx) { + file->private_data = tfa98xx; + return 0; + } else { + file->private_data = NULL; + return -EINVAL; + } +} + +static ssize_t tfa98xx_misc_device_rpc_read(struct file *file, + char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct tfa98xx *tfa98xx = file->private_data; + uint8_t *buffer = NULL; + int ret = 0; + + buffer = kmalloc(count, GFP_KERNEL); + if (buffer == NULL) { + pr_err("[0x%x] can not allocate memory\n", tfa98xx->i2c->addr); + return -ENOMEM; + } + + mutex_lock(&tfa98xx->dsp_lock); + + ret = send_tfa_cal_apr(buffer, count, true); + + mutex_unlock(&tfa98xx->dsp_lock); + if (ret) { + pr_err("[0x%x] dsp_msg_read error: %d\n", tfa98xx->i2c->addr, + ret); + kfree(buffer); + return -EFAULT; + } + + ret = copy_to_user(user_buf, buffer, count); + kfree(buffer); + if (ret) + return -EFAULT; + + *ppos += count; + return count; +} + +static ssize_t tfa98xx_misc_device_rpc_write(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct tfa98xx *tfa98xx = file->private_data; + uint8_t *buffer; + int err = 0; + + if (count == 0) + return 0; + + /* msg_file.name is not used */ + buffer = kmalloc(count, GFP_KERNEL); + if (buffer == NULL) { + pr_err("[0x%x] can not allocate memory\n", tfa98xx->i2c->addr); + return -ENOMEM; + } + if (copy_from_user(buffer, user_buf, count)) + return -EFAULT; + + mutex_lock(&tfa98xx->dsp_lock); + + err = send_tfa_cal_apr(buffer, count, false); + if (err) { + pr_err("[0x%x] dsp_msg error: %d\n", tfa98xx->i2c->addr, err); + } + + mdelay(2); + + mutex_unlock(&tfa98xx->dsp_lock); + + kfree(buffer); + + if (err) + return err; + return count; +} + +enum Tfa98xx_Error tfa98xx_read_data_from_hostdsp(struct tfa_device *tfa, + unsigned char module_id, + unsigned char param_id, + int num_bytes, + unsigned char data[]) +{ + int error; + unsigned char buffer[3]; + int nr = 0; + + if (num_bytes <= 0) { + pr_debug( + "Error: The number of READ bytes is smaller or equal to 0! \n"); + return Tfa98xx_Error_Fail; + } + + if ((tfa->cnt->ndev == 1) && (param_id == SB_PARAM_GET_RE25C || + param_id == SB_PARAM_GET_LSMODEL || + param_id == SB_PARAM_GET_ALGO_PARAMS)) { + /* Modifying the ID for GetRe25C */ + buffer[nr++] = 4; + } else { + buffer[nr++] = tfa->spkr_select; + } + buffer[nr++] = module_id + 128; + buffer[nr++] = param_id; + + error = send_tfa_cal_apr(buffer, sizeof(buffer), false); + if (error) + return Tfa98xx_Error_Bad_Parameter; + mdelay(5); + + /* read the data from the dsp */ + error = send_tfa_cal_apr(data, sizeof(num_bytes), true); + if (error) + return Tfa98xx_Error_Bad_Parameter; + return Tfa98xx_Error_Ok; +} + +static uint8_t send_to_dsp_count = 0; +static int tfa98xx_read_memtrack_data(struct tfa98xx *tfa98xx, int *pLivedata) +{ + enum Tfa98xx_Error ret = Tfa98xx_Error_Ok; + /* the buffer is for stereo usecase. */ + char buffer[(2 + (MEMTRACK_ITEM_MAX * 2)) * 3] = { 0 }; + int item_bytes = MEMTRACK_ITEM_MAX * 3; /* mono case by default.*/ + + enum TFA_DEVICE_TYPE pri_devcie = TFA_DEVICE_TYPE_MAX; + enum TFA_DEVICE_TYPE sec_devcie = TFA_DEVICE_TYPE_MAX; + /* TFA device memory map. */ + struct livedata_cfg + livedata_table[TFA_DEVICE_TYPE_MAX][MEMTRACK_ITEM_MAX] = { + /* for TFA9894 device */ + { + { 0x6fc, 0x02, 0x0001 }, /* fRes_P */ + { 0x705, 0x02, 0x4000 }, /* T_P */ + { 0x70b, 0x02, 0x10000 }, /* ReT_P */ + }, + + /* for TFA9874 primary channel */ + { + { 0x310, 0x02, 0x0001 }, /* fRes_P */ + { 0x319, 0x02, 0x4000 }, /* T_P */ + { 0x31f, 0x02, 0x10000 }, /* ReT_P */ + }, + + /* for TFA9874 secondary channel */ + { + { 0x64c, 0x02, 0x0001 }, /* fRes_S */ + { 0x655, 0x02, 0x4000 }, /* T_S */ + { 0x65b, 0x02, 0x10000 }, /* ReT_S */ + }, + }; + + pr_info("entry tfa_family=%d rev=0x%x\n", tfa98xx->tfa->tfa_family, + tfa98xx->tfa->rev); + mutex_lock(&tfa98xx->dsp_lock); + switch (tfa98xx->tfa->rev & 0xff) { + case 0x74: + pri_devcie = TFA_DEVICE_TYPE_9874_PRIMARY; + sec_devcie = TFA_DEVICE_TYPE_9874_SECONDARY; + break; + case 0x94: + pri_devcie = TFA_DEVICE_TYPE_9894; + break; + default: + pr_err("Un-support device type 0x%x\n", tfa98xx->tfa->rev); + ret = Tfa98xx_Error_Device; + goto err; + } + + /* check DSP status. we can read memtrack data once DSP is running. */ + if ((TFA_GET_BF(tfa98xx->tfa, MANSTATE) != 9) || + (TFA_GET_BF(tfa98xx->tfa, CFE) == 0)) { + pr_err("The DSP is not running.\n"); + ret = Tfa98xx_Error_DSP_not_running; + goto err; + } + + if (2 == tfa98xx->tfa->tfa_family) { + int i = 0, j = 0; + + /* step 1: set livedata items. */ + memset(&buffer[0], 0x00, sizeof(buffer)); + + /* For every item take the tracker and add this infront of the adress */ + if (tfa98xx->tfa->is_probus_device) { /* for none-dsp device. */ + /* because our algorithm can support mono/stereo use case. + if device count is more than 1, we will build stereo struct and send to dsp next time. */ + if ((tfa98xx_device_count > 1) && + (0 == send_to_dsp_count)) { + send_to_dsp_count++; + ret = Tfa98xx_Error_Ok; + goto err; + } + } + + /* build primary channel struct. */ + for (i = 0; i < MEMTRACK_ITEM_MAX * 3; i += 3) { + buffer[i + 6] = + (uint8_t)(livedata_table[pri_devcie][j].track & + 0xff); + buffer[i + 7] = (uint8_t)((livedata_table[pri_devcie][j] + .address >> + 8) & + 0xff); + buffer[i + 8] = + (uint8_t)(livedata_table[pri_devcie][j].address & + 0xff); + j++; + } + + /* build secondary channel struct. */ + if (tfa98xx_device_count > 1) { + j = 0; + for (i = MEMTRACK_ITEM_MAX * 3; + i < MEMTRACK_ITEM_MAX * 6; i += 3) { + buffer[i + 6] = + (uint8_t)(livedata_table[sec_devcie][j] + .track & + 0xff); + buffer[i + 7] = + (uint8_t)((livedata_table[sec_devcie][j] + .address >> + 8) & + 0xff); + buffer[i + 8] = + (uint8_t)(livedata_table[sec_devcie][j] + .address & + 0xff); + j++; + } + + item_bytes *= + 2; /* re-calculate item length for stereo usecase. */ + } + + /* copy the msg_id to buffer */ + buffer[0] = 0; + buffer[1] = MODULE_FRAMEWORK + 128; + buffer[2] = FW_PAR_ID_SET_MEMTRACK; + + /* Then copy the length (number of memtrack items) */ + buffer[3] = (uint8_t)((item_bytes >> 16) & 0xffff); + buffer[4] = (uint8_t)((item_bytes >> 8) & 0xff); + buffer[5] = (uint8_t)(item_bytes & 0xff); + + pr_info("send command to dsp to build memtrack structure.\n"); + /* send command to host dsp. */ + if (tfa98xx->tfa->is_probus_device) { + send_tfa_cal_apr(buffer, item_bytes + 6, false); + send_to_dsp_count = 0; + mdelay(5); + } else { + ret = dsp_msg(tfa98xx->tfa, item_bytes + 6, buffer); + } + + if (Tfa98xx_Error_Ok == ret) { + /* step 2: read livedata from dsp. */ + memset(&buffer[0], 0x00, sizeof(buffer)); + + /*Length = nr of items * 3 bytes (24bit dsp) + 3 bytes for Elapsed time (first 3 bytes)*/ + if (tfa98xx->tfa->is_probus_device) { + ret = tfa98xx_read_data_from_hostdsp( + tfa98xx->tfa, MODULE_FRAMEWORK, + FW_PAR_ID_GET_MEMTRACK, item_bytes + 3, + buffer); + } else { + ret = tfa_dsp_cmd_id_write_read( + tfa98xx->tfa, MODULE_FRAMEWORK, + FW_PAR_ID_GET_MEMTRACK, item_bytes + 3, + buffer); + } + + pr_info("read memtrack data. ret=%d\n", ret); + + if (Tfa98xx_Error_Ok == ret) { + /* Skip the first 3 bytes (this is the Elapsed time, not memtrack data) */ + tfa98xx_convert_bytes2data( + item_bytes, &buffer[3], pLivedata); + } else { + pr_err("get memtrack data failed from device.\n"); + ret = Tfa98xx_Error_Other; + } + } else { + pr_err("set memtrack item failed.\n"); + ret = Tfa98xx_Error_Other; + } + } else { + pr_err("The funciton doesn't support other device family(%d).\n", + tfa98xx->tfa->tfa_family); + ret = Tfa98xx_Error_Other; + } + +err: + mutex_unlock(&tfa98xx->dsp_lock); + return ret; +} + +static int tfa98xx_misc_device_control_open(struct inode *inode, + struct file *file) +{ + struct tfa98xx *tfa98xx = container_of(file->private_data, + struct tfa98xx, tfa98xx_control); + if (tfa98xx) { + file->private_data = tfa98xx; + return 0; + } else { + file->private_data = NULL; + return -EINVAL; + } +} + +static long tfa98xx_misc_device_control_ioctl(struct file *file, + unsigned int cmd, + unsigned long arg) +{ + struct tfa98xx *tfa98xx = NULL; + int result = 0; + + //pr_info("entry cmd=%d arg=%p\n", cmd, (void*)arg); + if (!arg) { + pr_err("arg is NULL!\n"); + return -EINVAL; + } + + switch (cmd) { + case IOCTL_CMD_GET_MEMTRACK_DATA: { + int livedata[MEMTRACK_ITEM_MAX * 2]; + int livedata_length_bytes = 0; + void *pUserData = (void *)arg; + list_for_each_entry (tfa98xx, &tfa98xx_device_list, list) { + /* clear buffer and read livedata from dsp.*/ + memset((char *)(&livedata[0]), 0x00, sizeof(livedata)); + /* read original memtrack data from device. */ + if (Tfa98xx_Error_Ok == + tfa98xx_read_memtrack_data(tfa98xx, &livedata[0])) { + pr_info("Device 0x%x read memtrack data sucessed.\n", + tfa98xx->i2c->addr); + } else { + pr_err("Device 0x%x read memtrack data failed.\n", + tfa98xx->i2c->addr); + } + + /* copy data to user spcace. if copied is successed, + will be returned actual size to user space. */ + livedata_length_bytes = sizeof(int) * MEMTRACK_ITEM_MAX; + if ((tfa98xx->tfa->is_probus_device) && + (tfa98xx_device_count > 1)) { + /* for stereo usecase, if the condition is true, we have already got livedata from host DSP. + otherwise, we don't need do anything. */ + if (send_to_dsp_count == 0) { + livedata_length_bytes *= 2; + } else { + livedata_length_bytes = 0; + } + } + + if (livedata_length_bytes != 0) { + result = copy_to_user((void __user *)pUserData, + &livedata[0], + livedata_length_bytes); + if (result) { + pr_err("copy to user space failed(%d).\n", + result); + result = -EINVAL; + break; + } else { + result += livedata_length_bytes; + } + pUserData += livedata_length_bytes; + } + } + break; + } + case IOCTL_CMD_GET_CNT_VERSION: { + void *pUserData = (void *)arg; + + if (NULL != tfa98xx_container) { + result = copy_to_user((void __user *)pUserData, + tfa98xx_container->type, + strlen(tfa98xx_container->type)); + if (result) { + pr_err("copy to user space failed(%d).\n", + result); + } else { + result = strlen(tfa98xx_container->type); + } + } else { + pr_err("get cnt version failed.\n"); + result = -EINVAL; + } + break; + } + default: + result = -EINVAL; + pr_err("un-supported command. (%d)\n", cmd); + break; + } + + //pr_info("exit result=%d\n", result); + return result; +} + +#ifdef CONFIG_COMPAT +static long tfa98xx_misc_device_control_compat_ioctl(struct file *file, + unsigned int cmd, + unsigned long arg) +{ + //pr_info("%s entry cmd=%d arg=%p\n", __func__, cmd, (void*)arg); + + if (!arg) { + pr_err("%s No data send to driver!\n", __func__); + return -EINVAL; + } + + return tfa98xx_misc_device_control_ioctl(file, cmd, arg); +} +#endif + +static const struct tfa98xx_miscdevice_info miscdevice_info[MISC_DEVICE_MAX] = { + { + .devicename = "tfa_reg", + .operations.owner = THIS_MODULE, + .operations.open = tfa98xx_misc_device_reg_open, + .operations.write = tfa98xx_misc_device_reg_write, + }, + { + .devicename = "tfa_rw", + .operations.owner = THIS_MODULE, + .operations.open = tfa98xx_misc_device_rw_open, + .operations.read = tfa98xx_misc_device_rw_read, + .operations.write = tfa98xx_misc_device_rw_write, + }, + { + .devicename = "tfa_rpc", + .operations.owner = THIS_MODULE, + .operations.open = tfa98xx_misc_device_rpc_open, + .operations.read = tfa98xx_misc_device_rpc_read, + .operations.write = tfa98xx_misc_device_rpc_write, + }, + { + .devicename = "tfa_profile", + .operations.owner = THIS_MODULE, + .operations.open = tfa98xx_misc_device_profile_open, + .operations.write = tfa98xx_misc_device_profile_write, + }, + { + .devicename = "tfa_control", + .operations.owner = THIS_MODULE, + .operations.open = tfa98xx_misc_device_control_open, + .operations.unlocked_ioctl = tfa98xx_misc_device_control_ioctl, +#ifdef CONFIG_COMPAT + .operations.compat_ioctl = + tfa98xx_misc_device_control_compat_ioctl, +#endif + }, +}; + +int tfa98xx_init_misc_device(struct tfa98xx *tfa98xx) +{ + int ret = 0; + + pr_info("entry\n"); + if (NULL == tfa98xx) { + pr_err("tfa98xx is NULL.\n"); + return -EINVAL; + } + + //pr_info("I2C bus=0x%x address=0x%x\n", tfa98xx->i2c->adapter->nr, tfa98xx->i2c->addr); + /* create device node "tfa_reg_X" for write sub address. */ + tfa98xx->tfa98xx_reg.minor = MISC_DYNAMIC_MINOR; + tfa98xx->tfa98xx_reg.name = + miscdevice_info[MISC_DEVICE_TFA98XX_REG].devicename; + tfa98xx->tfa98xx_reg.fops = + &miscdevice_info[MISC_DEVICE_TFA98XX_REG].operations; + ret = misc_register(&tfa98xx->tfa98xx_reg); + if (ret) { + pr_err("tfa98xx_init_misc_device: register misc device [%s] failed\n", + tfa98xx->tfa98xx_reg.name); + } + + /* create device node "tfa_rw_X" for read/write i2c device. */ + tfa98xx->tfa98xx_rw.minor = MISC_DYNAMIC_MINOR; + tfa98xx->tfa98xx_rw.name = + miscdevice_info[MISC_DEVICE_TFA98XX_RW].devicename; + tfa98xx->tfa98xx_rw.fops = + &miscdevice_info[MISC_DEVICE_TFA98XX_RW].operations; + ret = misc_register(&tfa98xx->tfa98xx_rw); + if (ret) { + pr_err("tfa98xx_init_misc_device: register misc device [%s] failed\n", + tfa98xx->tfa98xx_rw.name); + } + + /* create device node "tfa_rpc_X" for switching profile. */ + tfa98xx->tfa98xx_rpc.minor = MISC_DYNAMIC_MINOR; + tfa98xx->tfa98xx_rpc.name = + miscdevice_info[MISC_DEVICE_TFA98XX_RPC].devicename; + tfa98xx->tfa98xx_rpc.fops = + &miscdevice_info[MISC_DEVICE_TFA98XX_RPC].operations; + ret = misc_register(&tfa98xx->tfa98xx_rpc); + if (ret) { + pr_err("tfa98xx_init_misc_device: register misc device [%s] failed\n", + tfa98xx->tfa98xx_rpc.name); + } + + /* create device node "tfa_profile_X" for switching profile. */ + tfa98xx->tfa98xx_profile.minor = MISC_DYNAMIC_MINOR; + tfa98xx->tfa98xx_profile.name = + miscdevice_info[MISC_DEVICE_TFA98XX_PROFILE].devicename; + tfa98xx->tfa98xx_profile.fops = + &miscdevice_info[MISC_DEVICE_TFA98XX_PROFILE].operations; + ret = misc_register(&tfa98xx->tfa98xx_profile); + if (ret) { + pr_err("tfa98xx_init_misc_device: register misc device [%s] failed\n", + tfa98xx->tfa98xx_profile.name); + } + + /* create device node "tfa_control_X" for IO control. */ + tfa98xx->tfa98xx_control.minor = MISC_DYNAMIC_MINOR; + tfa98xx->tfa98xx_control.name = + miscdevice_info[MISC_DEVICE_TFA98XX_IOCTL].devicename; + tfa98xx->tfa98xx_control.fops = + &miscdevice_info[MISC_DEVICE_TFA98XX_IOCTL].operations; + ret = misc_register(&tfa98xx->tfa98xx_control); + if (ret) { + pr_err("tfa98xx_init_misc_device: register misc device [%s] failed\n", + tfa98xx->tfa98xx_control.name); + } + + if (0 == ret) + pr_info("register misc device successed.\n"); + return ret; +} + +void tfa98xx_remove_misc_device(struct tfa98xx *tfa98xx) +{ + pr_info("entry\n"); + if (NULL == tfa98xx) { + pr_err("tfa98xx is NULL.\n"); + return; + } + + misc_deregister(&tfa98xx->tfa98xx_reg); + misc_deregister(&tfa98xx->tfa98xx_rw); + misc_deregister(&tfa98xx->tfa98xx_rpc); + misc_deregister(&tfa98xx->tfa98xx_profile); + misc_deregister(&tfa98xx->tfa98xx_control); + return; +} + +static int tfa98xx_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) +{ + struct snd_soc_dai_driver *dai; + struct tfa98xx *tfa98xx; + struct device_node *np = i2c->dev.of_node; + int irq_flags; + unsigned int reg; + int ret; + int spk_name; + + pr_info("addr=0x%x\n", i2c->addr); + + if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) { + dev_err(&i2c->dev, "check_functionality failed\n"); + return -EIO; + } + + tfa98xx = devm_kzalloc(&i2c->dev, sizeof(struct tfa98xx), GFP_KERNEL); + if (tfa98xx == NULL) + return -ENOMEM; + + tfa98xx->dev = &i2c->dev; + tfa98xx->i2c = i2c; + tfa98xx->dsp_init = TFA98XX_DSP_INIT_STOPPED; + tfa98xx->rate = 48000; /* init to the default sample rate (48kHz) */ + tfa98xx->tfa = NULL; + tfa98xx->tfa_mute_mode = + TFA98XX_DEVICE_MUTE_OFF; /* the mute mode is disabled by default. */ + tfa98xx->regmap = devm_regmap_init_i2c(i2c, &tfa98xx_regmap); + if (IS_ERR(tfa98xx->regmap)) { + ret = PTR_ERR(tfa98xx->regmap); + dev_err(&i2c->dev, "Failed to allocate register map: %d\n", + ret); + return ret; + } + + i2c_set_clientdata(i2c, tfa98xx); + mutex_init(&tfa98xx->dsp_lock); + init_waitqueue_head(&tfa98xx->wq); + + if (np) { + ret = tfa98xx_parse_dt(&i2c->dev, tfa98xx, np); + if (ret) { + dev_err(&i2c->dev, "Failed to parse DT node\n"); + return ret; + } + if (no_start) + tfa98xx->irq_gpio = -1; + if (no_reset) + tfa98xx->reset_gpio = -1; + } else { + tfa98xx->reset_gpio = -1; + tfa98xx->irq_gpio = -1; + } + + if (gpio_is_valid(tfa98xx->reset_gpio)) { + ret = devm_gpio_request_one(&i2c->dev, tfa98xx->reset_gpio, + GPIOF_OUT_INIT_LOW, "TFA98XX_RST"); + if (ret) + return ret; + } + + if (gpio_is_valid(tfa98xx->irq_gpio)) { + ret = devm_gpio_request_one(&i2c->dev, tfa98xx->irq_gpio, + GPIOF_DIR_IN, "TFA98XX_INT"); + if (ret) + return ret; + } + + tfa98xx->spk_id_gpio_p = of_parse_phandle(np, "nxp,spk-id-pin", 0); + + if (!tfa98xx->spk_id_gpio_p) { + dev_err(&i2c->dev, "property %s not detected in node %s", + "nxp,spk-id-pin", np->full_name); + } else { + spk_name = nxp_spk_id_get(tfa98xx->spk_id_gpio_p); + if (spk_name == VENDOR_ID_AAC) { + fw_name = TFA98XX_AAC_FW_NAME; + } + + if (spk_name == VENDOR_ID_GOER) { + fw_name = TFA98XX_GOER_FW_NAME; + } + + dev_err(&i2c->dev, "spk is %d, fw_name =%s\n", spk_name, + fw_name); + } + + /* Power up! */ + tfa98xx_ext_reset(tfa98xx); + + if ((no_start == 0) && (no_reset == 0)) { + ret = regmap_read(tfa98xx->regmap, 0x03, ®); + if (ret < 0) { + dev_err(&i2c->dev, + "Failed to read Revision register: %d\n", ret); + return -EIO; + } + switch (reg & 0xff) { + case 0x72: /* tfa9872 */ + pr_info("TFA9872 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS; + tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL; + tfa98xx->flags |= TFA98XX_FLAG_REMOVE_PLOP_NOISE; + /* tfa98xx->flags |= TFA98XX_FLAG_LP_MODES; */ + tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE; + break; + case 0x74: /* tfa9874 */ + pr_info("TFA9874 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS; + tfa98xx->flags |= TFA98XX_FLAG_CALIBRATION_CTL; + tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE; + break; + case 0x88: /* tfa9888 */ + pr_info("TFA9888 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_STEREO_DEVICE; + tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS; + tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE; + break; + case 0x13: /* tfa9912 */ + pr_info("TFA9912 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS; + tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE; + /* tfa98xx->flags |= TFA98XX_FLAG_TAPDET_AVAILABLE; */ + break; + case 0x94: /* tfa9894 */ + pr_info("TFA9894 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_MULTI_MIC_INPUTS; + tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE; + tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS; + break; + case 0x80: /* tfa9890 */ + case 0x81: /* tfa9890 */ + pr_info("TFA9890 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS; + break; + case 0x92: /* tfa9891 */ + pr_info("TFA9891 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_SAAM_AVAILABLE; + tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS; + break; + case 0x12: /* tfa9895 */ + pr_info("TFA9895 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS; + break; + case 0x97: + pr_info("TFA9897 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS; + tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE; + break; + case 0x96: + pr_info("TFA9896 detected\n"); + tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS; + tfa98xx->flags |= TFA98XX_FLAG_TDM_DEVICE; + break; + default: + pr_info("Unsupported device revision (0x%x)\n", + reg & 0xff); + return -EINVAL; + } + } + + tfa98xx->tfa = + devm_kzalloc(&i2c->dev, sizeof(struct tfa_device), GFP_KERNEL); + if (tfa98xx->tfa == NULL) + return -ENOMEM; + + tfa98xx->tfa->data = (void *)tfa98xx; + tfa98xx->tfa->cachep = tfa98xx_cache; + + /* Modify the stream names, by appending the i2c device address. + * This is used with multicodec, in order to discriminate the devices. + * Stream names appear in the dai definition and in the stream . + * We create copies of original structures because each device will + * have its own instance of this structure, with its own address. + */ + dai = devm_kzalloc(&i2c->dev, sizeof(tfa98xx_dai), GFP_KERNEL); + if (!dai) + return -ENOMEM; + memcpy(dai, tfa98xx_dai, sizeof(tfa98xx_dai)); + + tfa98xx_append_i2c_address(&i2c->dev, i2c, NULL, 0, dai, + ARRAY_SIZE(tfa98xx_dai)); + + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tfa98xx, dai, + ARRAY_SIZE(tfa98xx_dai)); + + if (ret < 0) { + dev_err(&i2c->dev, "Failed to register TFA98xx: %d\n", ret); + return ret; + } + + if (gpio_is_valid(tfa98xx->irq_gpio) && + !(tfa98xx->flags & TFA98XX_FLAG_SKIP_INTERRUPTS)) { + /* register irq handler */ + irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT; + ret = devm_request_threaded_irq(&i2c->dev, + gpio_to_irq(tfa98xx->irq_gpio), + NULL, tfa98xx_irq, irq_flags, + "tfa98xx", tfa98xx); + if (ret != 0) { + dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n", + gpio_to_irq(tfa98xx->irq_gpio), ret); + return ret; + } + } else { + dev_info(&i2c->dev, "Skipping IRQ registration\n"); + /* disable feature support if gpio was invalid */ + tfa98xx->flags |= TFA98XX_FLAG_SKIP_INTERRUPTS; + } + +#ifdef CONFIG_DEBUG_FS + if (no_start == 0) + tfa98xx_debug_init(tfa98xx, i2c); +#endif + /* Register the sysfs files for climax backdoor access */ + ret = device_create_bin_file(&i2c->dev, &dev_attr_rw); + if (ret) + dev_info(&i2c->dev, "error creating sysfs files\n"); + ret = device_create_bin_file(&i2c->dev, &dev_attr_reg); + if (ret) + dev_info(&i2c->dev, "error creating sysfs files\n"); + if (0 == tfa98xx_device_count) + tfa98xx_init_misc_device(tfa98xx); + pr_info("%s Probe completed successfully!\n", __func__); + + INIT_LIST_HEAD(&tfa98xx->list); + + mutex_lock(&tfa98xx_mutex); + tfa98xx_device_count++; + list_add(&tfa98xx->list, &tfa98xx_device_list); + mutex_unlock(&tfa98xx_mutex); + + return 0; +} + +static int tfa98xx_i2c_remove(struct i2c_client *i2c) +{ + struct tfa98xx *tfa98xx = i2c_get_clientdata(i2c); + + pr_debug("addr=0x%x\n", i2c->addr); + + tfa98xx_interrupt_enable(tfa98xx, false); + + cancel_delayed_work_sync(&tfa98xx->interrupt_work); + cancel_delayed_work_sync(&tfa98xx->monitor_work); + cancel_delayed_work_sync(&tfa98xx->init_work); + cancel_delayed_work_sync(&tfa98xx->tapdet_work); + + device_remove_bin_file(&i2c->dev, &dev_attr_reg); + device_remove_bin_file(&i2c->dev, &dev_attr_rw); +#ifdef CONFIG_DEBUG_FS + tfa98xx_debug_remove(tfa98xx); +#endif + tfa98xx_remove_misc_device(tfa98xx); + + snd_soc_unregister_codec(&i2c->dev); + + if (gpio_is_valid(tfa98xx->irq_gpio)) + devm_gpio_free(&i2c->dev, tfa98xx->irq_gpio); + if (gpio_is_valid(tfa98xx->reset_gpio)) + devm_gpio_free(&i2c->dev, tfa98xx->reset_gpio); + + mutex_lock(&tfa98xx_mutex); + list_del(&tfa98xx->list); + tfa98xx_device_count--; + if (tfa98xx_device_count == 0) { + kfree(tfa98xx_container); + tfa98xx_container = NULL; + } + mutex_unlock(&tfa98xx_mutex); + + return 0; +} + +static const struct i2c_device_id tfa98xx_i2c_id[] = { + { "tfa98xx", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(i2c, tfa98xx_i2c_id); + +#ifdef CONFIG_OF +static struct of_device_id tfa98xx_dt_match[] = { + { .compatible = "nxp,tfa98xx" }, { .compatible = "nxp,tfa9872" }, + { .compatible = "nxp,tfa9874" }, { .compatible = "nxp,tfa9888" }, + { .compatible = "nxp,tfa9890" }, { .compatible = "nxp,tfa9891" }, + { .compatible = "nxp,tfa9894" }, { .compatible = "nxp,tfa9895" }, + { .compatible = "nxp,tfa9896" }, { .compatible = "nxp,tfa9897" }, + { .compatible = "nxp,tfa9912" }, {}, +}; +#endif + +static struct i2c_driver tfa98xx_i2c_driver = { + .driver = { + .name = "tfa98xx", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(tfa98xx_dt_match), + }, + .probe = tfa98xx_i2c_probe, + .remove = tfa98xx_i2c_remove, + .id_table = tfa98xx_i2c_id, +}; + +static int __init tfa98xx_i2c_init(void) +{ + int ret = 0; + + pr_info("TFA98XX driver version %s\n", TFA98XX_VERSION); + + /* Enable debug traces */ + tfa98xx_kmsg_regs = trace_level & 2; + tfa98xx_ftrace_regs = trace_level & 4; + + /* Initialize kmem_cache */ + tfa98xx_cache = kmem_cache_create( + "tfa98xx_cache", /* Cache name /proc/slabinfo */ + PAGE_SIZE, /* Structure size, we should fit in single page */ + 0, /* Structure alignment */ + (SLAB_HWCACHE_ALIGN | SLAB_RECLAIM_ACCOUNT | + SLAB_MEM_SPREAD), /* Cache property */ + NULL); /* Object constructor */ + if (!tfa98xx_cache) { + pr_err("tfa98xx can't create memory pool\n"); + ret = -ENOMEM; + } + + ret = i2c_add_driver(&tfa98xx_i2c_driver); + + return ret; +} +module_init(tfa98xx_i2c_init); + +static void __exit tfa98xx_i2c_exit(void) +{ + i2c_del_driver(&tfa98xx_i2c_driver); + kmem_cache_destroy(tfa98xx_cache); +} +module_exit(tfa98xx_i2c_exit); + +MODULE_DESCRIPTION("ASoC TFA98XX driver"); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c new file mode 100644 index 000000000000..7207069dacc2 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c @@ -0,0 +1,2570 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dbgprint.h" +#include "tfa_container.h" +#include "tfa.h" +#include "tfa98xx_tfafieldnames.h" +#include "tfa_internal.h" + +/* defines */ +#define MODULE_BIQUADFILTERBANK 2 +#define BIQUAD_COEFF_SIZE 6 + +/* module globals */ +static uint8_t gslave_address = + 0; /* This is used to SET the slave with the --slave option */ + +static int float_to_int(uint32_t x) +{ + unsigned e = (0x7F + 31) - ((*(unsigned *)&x & 0x7F800000) >> 23); + unsigned m = 0x80000000 | (*(unsigned *)&x << 8); + return -(int)((m >> e) & -(e < 32)); +} + +/* + * check the container file +*/ +enum tfa_error tfa_load_cnt(void *cnt, int length) +{ + nxpTfaContainer_t *cntbuf = (nxpTfaContainer_t *)cnt; + + if (length > TFA_MAX_CNT_LENGTH) { + pr_err("incorrect length\n"); + return tfa_error_container; + } + + if (HDR(cntbuf->id[0], cntbuf->id[1]) == 0) { + pr_err("header is 0\n"); + return tfa_error_container; + } + + if ((HDR(cntbuf->id[0], cntbuf->id[1])) != paramsHdr) { + pr_err("wrong header type: 0x%02x 0x%02x\n", cntbuf->id[0], + cntbuf->id[1]); + return tfa_error_container; + } + + if (cntbuf->size == 0) { + pr_err("data size is 0\n"); + return tfa_error_container; + } + + /* check CRC */ + if (tfaContCrcCheckContainer(cntbuf)) { + pr_err("CRC error\n"); + return tfa_error_container; + } + + /* check sub version level */ + if ((cntbuf->subversion[1] != NXPTFA_PM_SUBVERSION) && + (cntbuf->subversion[0] != '0')) { + pr_err("container sub-version not supported: %c%c\n", + cntbuf->subversion[0], cntbuf->subversion[1]); + return tfa_error_container; + } + + return tfa_error_ok; +} + +/* + * Dump the contents of the file header + */ +void tfaContShowHeader(nxpTfaHeader_t *hdr) +{ + char _id[2]; + + pr_debug("File header\n"); + + _id[1] = hdr->id >> 8; + _id[0] = hdr->id & 0xff; + pr_debug("\tid:%.2s version:%.2s subversion:%.2s\n", _id, hdr->version, + hdr->subversion); + pr_debug("\tsize:%d CRC:0x%08x \n", hdr->size, hdr->CRC); + pr_debug("\tcustomer:%.8s application:%.8s type:%.8s\n", hdr->customer, + hdr->application, hdr->type); +} + +/* + * return device list dsc from index + */ +nxpTfaDeviceList_t *tfaContGetDevList(nxpTfaContainer_t *cont, int dev_idx) +{ + uint8_t *base = (uint8_t *)cont; + + if (cont == NULL) + return NULL; + + if ((dev_idx < 0) || (dev_idx >= cont->ndev)) + return NULL; + + if (cont->index[dev_idx].type != dscDevice) + return NULL; + + base += cont->index[dev_idx].offset; + return (nxpTfaDeviceList_t *)base; +} + +/* + * get the Nth profile for the Nth device + */ +nxpTfaProfileList_t *tfaContGetDevProfList(nxpTfaContainer_t *cont, int devIdx, + int profIdx) +{ + nxpTfaDeviceList_t *dev; + int idx, hit; + uint8_t *base = (uint8_t *)cont; + + dev = tfaContGetDevList(cont, devIdx); + if (dev) { + for (idx = 0, hit = 0; idx < dev->length; idx++) { + if (dev->list[idx].type == dscProfile) { + if (profIdx == hit++) + return (nxpTfaProfileList_t + *)(dev->list[idx].offset + + base); + } + } + } + + return NULL; +} + +/* + * get the number of profiles for the Nth device + */ +int tfa_cnt_get_dev_nprof(struct tfa_device *tfa) +{ + nxpTfaDeviceList_t *dev; + int idx, nprof = 0; + + if (tfa->cnt == NULL) + return 0; + + if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev)) + return 0; + + dev = tfaContGetDevList(tfa->cnt, tfa->dev_idx); + if (dev) { + for (idx = 0; idx < dev->length; idx++) { + if (dev->list[idx].type == dscProfile) { + nprof++; + } + } + } + + return nprof; +} + +/* + * get the Nth lifedata for the Nth device + */ +nxpTfaLiveDataList_t *tfaContGetDevLiveDataList(nxpTfaContainer_t *cont, + int devIdx, int lifeDataIdx) +{ + nxpTfaDeviceList_t *dev; + int idx, hit; + uint8_t *base = (uint8_t *)cont; + + dev = tfaContGetDevList(cont, devIdx); + if (dev) { + for (idx = 0, hit = 0; idx < dev->length; idx++) { + if (dev->list[idx].type == dscLiveData) { + if (lifeDataIdx == hit++) + return (nxpTfaLiveDataList_t + *)(dev->list[idx].offset + + base); + } + } + } + + return NULL; +} + +/* + * Get the max volume step associated with Nth profile for the Nth device + */ +int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx) +{ + nxpTfaVolumeStep2File_t *vp; + struct nxpTfaVolumeStepMax2File *vp3; + int vstep_count = 0; + vp = (nxpTfaVolumeStep2File_t *)tfacont_getfiledata(tfa, prof_idx, + volstepHdr); + if (vp == NULL) + return 0; + /* check the header type to load different NrOfVStep appropriately */ + if (tfa->tfa_family == 2) { + /* this is actually tfa2, so re-read the buffer*/ + vp3 = (struct nxpTfaVolumeStepMax2File *)tfacont_getfiledata( + tfa, prof_idx, volstepHdr); + if (vp3) { + vstep_count = vp3->NrOfVsteps; + } + } else { + /* this is max1*/ + if (vp) { + vstep_count = vp->vsteps; + } + } + return vstep_count; +} + +/** + * Get the file contents associated with the device or profile + * Search within the device tree, if not found, search within the profile + * tree. There can only be one type of file within profile or device. + */ +nxpTfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx, + enum nxpTfaHeaderType type) +{ + nxpTfaDeviceList_t *dev; + nxpTfaProfileList_t *prof; + nxpTfaFileDsc_t *file; + nxpTfaHeader_t *hdr; + unsigned int i; + + if (tfa->cnt == NULL) { + pr_err("invalid pointer to container file\n"); + return NULL; + } + + dev = tfaContGetDevList(tfa->cnt, tfa->dev_idx); + if (dev == NULL) { + pr_err("invalid pointer to container file device list\n"); + return NULL; + } + + /* process the device list until a file type is encountered */ + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == dscFile) { + file = (nxpTfaFileDsc_t *)(dev->list[i].offset + + (uint8_t *)tfa->cnt); + if (file != NULL) { + hdr = (nxpTfaHeader_t *)file->data; + /* check for file type */ + if (hdr->id == type) { + return (nxpTfaFileDsc_t *)&file->data; + } + } + } + } + + /* File not found in device tree. + * So, look in the profile list until the file type is encountered + */ + prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + if (prof == NULL) { + pr_err("invalid pointer to container file profile list\n"); + return NULL; + } + + for (i = 0; i < prof->length; i++) { + if (prof->list[i].type == dscFile) { + file = (nxpTfaFileDsc_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + if (file != NULL) { + hdr = (nxpTfaHeader_t *)file->data; + if (hdr != NULL) { + /* check for file type */ + if (hdr->id == type) { + return (nxpTfaFileDsc_t *)&file + ->data; + } + } + } + } + } + + if (tfa->verbose) + pr_debug("%s: no file found of type %d\n", __FUNCTION__, type); + + return NULL; +} + +/* + * write a parameter file to the device + */ +static enum Tfa98xx_Error tfaContWriteVstep(struct tfa_device *tfa, + nxpTfaVolumeStep2File_t *vp, + int vstep) +{ + enum Tfa98xx_Error err; + unsigned short vol; + + if (vstep < vp->vsteps) { + /* vol = (unsigned short)(voldB / (-0.5f)); */ + vol = (unsigned short)(-2 * + float_to_int( + *((uint32_t *)&vp->vstep[vstep] + .attenuation))); + if (vol > 255) /* restricted to 8 bits */ + vol = 255; + + err = tfa98xx_set_volume_level(tfa, vol); + if (err != Tfa98xx_Error_Ok) + return err; + + err = tfa98xx_dsp_write_preset(tfa, sizeof(vp->vstep[0].preset), + vp->vstep[vstep].preset); + if (err != Tfa98xx_Error_Ok) + return err; + err = tfa_cont_write_filterbank(tfa, vp->vstep[vstep].filter); + + } else { + pr_err("Incorrect volume given. The value vstep[%d] >= %d\n", + vstep, vp->vsteps); + err = Tfa98xx_Error_Bad_Parameter; + } + + if (tfa->verbose) + pr_debug("vstep[%d][%d]\n", tfa->dev_idx, vstep); + + return err; +} + +static struct nxpTfaVolumeStepMessageInfo * +tfaContGetmsgInfoFromReg(struct nxpTfaVolumeStepRegisterInfo *regInfo) +{ + char *p = (char *)regInfo; + p += sizeof(regInfo->NrOfRegisters) + + (regInfo->NrOfRegisters * sizeof(uint32_t)); + return (struct nxpTfaVolumeStepMessageInfo *)p; +} + +static int tfaContGetmsgLen(struct nxpTfaVolumeStepMessageInfo *msgInfo) +{ + return (msgInfo->MessageLength.b[0] << 16) + + (msgInfo->MessageLength.b[1] << 8) + msgInfo->MessageLength.b[2]; +} + +static struct nxpTfaVolumeStepMessageInfo * +tfaContGetNextmsgInfo(struct nxpTfaVolumeStepMessageInfo *msgInfo) +{ + char *p = (char *)msgInfo; + int msgLen = tfaContGetmsgLen(msgInfo); + int type = msgInfo->MessageType; + + p += sizeof(msgInfo->MessageType) + sizeof(msgInfo->MessageLength); + if (type == 3) + p += msgLen; + else + p += msgLen * 3; + + return (struct nxpTfaVolumeStepMessageInfo *)p; +} + +static struct nxpTfaVolumeStepRegisterInfo * +tfaContGetNextRegFromEndInfo(struct nxpTfaVolumeStepMessageInfo *msgInfo) +{ + char *p = (char *)msgInfo; + p += sizeof(msgInfo->NrOfMessages); + return (struct nxpTfaVolumeStepRegisterInfo *)p; +} + +static struct nxpTfaVolumeStepRegisterInfo * +tfaContGetRegForVstep(nxpTfaVolumeStepMax2File_t *vp, int idx) +{ + int i, j, nrMessage; + + struct nxpTfaVolumeStepRegisterInfo *regInfo = + (struct nxpTfaVolumeStepRegisterInfo *)vp->vstepsBin; + struct nxpTfaVolumeStepMessageInfo *msgInfo = NULL; + + for (i = 0; i < idx; i++) { + msgInfo = tfaContGetmsgInfoFromReg(regInfo); + nrMessage = msgInfo->NrOfMessages; + + for (j = 0; j < nrMessage; j++) { + msgInfo = tfaContGetNextmsgInfo(msgInfo); + } + regInfo = tfaContGetNextRegFromEndInfo(msgInfo); + } + + return regInfo; +} + +#pragma pack(push, 1) +struct tfa_partial_msg_block { + uint8_t offset; + uint16_t change; + uint8_t update[16][3]; +}; +#pragma pack(pop) + +static enum Tfa98xx_Error tfaContWriteVstepMax2_One( + struct tfa_device *tfa, struct nxpTfaVolumeStepMessageInfo *new_msg, + struct nxpTfaVolumeStepMessageInfo *old_msg, int enable_partial_update) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int len = (tfaContGetmsgLen(new_msg) - 1) * 3; + char *buf = (char *)new_msg->ParameterData; + uint8_t *partial = NULL; + uint8_t cmdid[3]; + int use_partial_coeff = 0; + + if (enable_partial_update) { + if (new_msg->MessageType != old_msg->MessageType) { + pr_debug( + "Message type differ - Disable Partial Update\n"); + enable_partial_update = 0; + } else if (tfaContGetmsgLen(new_msg) != + tfaContGetmsgLen(old_msg)) { + pr_debug( + "Message Length differ - Disable Partial Update\n"); + enable_partial_update = 0; + } + } + + if ((enable_partial_update) && (new_msg->MessageType == 1)) { + /* No patial updates for message type 1 (Coefficients) */ + enable_partial_update = 0; + if ((tfa->rev & 0xff) == 0x88) { + use_partial_coeff = 1; + } else if ((tfa->rev & 0xff) == 0x13) { + use_partial_coeff = 1; + } + } + + /* Change Message Len to the actual buffer len */ + memcpy(cmdid, new_msg->CmdId, sizeof(cmdid)); + + /* The algoparams and mbdrc msg id will be changed to the reset type when SBSL=0 + * if SBSL=1 the msg will remain unchanged. It's up to the tuning engineer to choose the 'without_reset' + * types inside the vstep. In other words: the reset msg is applied during SBSL==0 else it remains unchanged. + */ + if (tfa_needs_reset(tfa) == 1) { + if (new_msg->MessageType == 0) { + cmdid[2] = SB_PARAM_SET_ALGO_PARAMS; + if (tfa->verbose) + pr_debug("P-ID for SetAlgoParams modified!\n"); + } else if (new_msg->MessageType == 2) { + cmdid[2] = SB_PARAM_SET_MBDRC; + if (tfa->verbose) + pr_debug("P-ID for SetMBDrc modified!\n"); + } + } + + /* + * +sizeof(struct tfa_partial_msg_block) will allow to fit one + * additonnal partial block If the partial update goes over the len of + * a regular message ,we can safely write our block and check afterward + * that we are over the size of a usual update + */ + if (enable_partial_update) { + partial = kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + if (!partial) + pr_debug("Partial update memory error - Disabling\n"); + } + + if (partial) { + uint8_t offset = 0, i = 0; + uint16_t *change; + uint8_t *n = new_msg->ParameterData; + uint8_t *o = old_msg->ParameterData; + uint8_t *p = partial; + uint8_t *trim = partial; + + /* set dspFiltersReset */ + *p++ = 0x02; + *p++ = 0x00; + *p++ = 0x00; + + while ((o < (old_msg->ParameterData + len)) && + (p < (partial + len - 3))) { + if ((offset == 0xff) || + (memcmp(n, o, 3 * sizeof(uint8_t)))) { + *p++ = offset; + change = (uint16_t *)p; + *change = 0; + p += 2; + + for (i = 0; + (i < 16) && + (o < (old_msg->ParameterData + len)); + i++, n += 3, o += 3) { + if (memcmp(n, o, 3 * sizeof(uint8_t))) { + *change |= BIT(i); + memcpy(p, n, 3); + p += 3; + trim = p; + } + } + + offset = 0; + *change = cpu_to_be16(*change); + } else { + n += 3; + o += 3; + offset++; + } + } + + if (trim == partial) { + pr_debug("No Change in message - discarding %d bytes\n", + len); + len = 0; + + } else if (trim < (partial + len - 3)) { + pr_debug("Using partial update: %d -> %d bytes\n", len, + (int)(trim - partial + 3)); + + /* Add the termination marker */ + memset(trim, 0x00, 3); + trim += 3; + + /* Signal This will be a partial update */ + cmdid[2] |= BIT(6); + buf = (char *)partial; + len = (int)(trim - partial); + } else { + pr_debug("Partial too big - use regular update\n"); + } + } + + if (use_partial_coeff) { + err = dsp_partial_coefficients(tfa, old_msg->ParameterData, + new_msg->ParameterData); + } else if (len) { + uint8_t *buffer; + + if (tfa->verbose) + pr_debug("Command-ID used: 0x%02x%02x%02x \n", cmdid[0], + cmdid[1], cmdid[2]); + + buffer = kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + if (buffer == NULL) { + err = Tfa98xx_Error_Fail; + } else { + memcpy(&buffer[0], cmdid, 3); + memcpy(&buffer[3], buf, len); + err = dsp_msg(tfa, 3 + len, (char *)buffer); + kmem_cache_free(tfa->cachep, buffer); + } + } + + if (partial) + kmem_cache_free(tfa->cachep, partial); + + return err; +} + +static enum Tfa98xx_Error tfaContWriteVstepMax2(struct tfa_device *tfa, + nxpTfaVolumeStepMax2File_t *vp, + int vstep_idx, + int vstep_msg_idx) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + struct nxpTfaVolumeStepRegisterInfo *regInfo = NULL; + struct nxpTfaVolumeStepMessageInfo *msgInfo = NULL, *p_msgInfo = NULL; + nxpTfaBitfield_t bitF; + int i, nrMessages, enp = tfa->partial_enable; + + if (vstep_idx >= vp->NrOfVsteps) { + pr_debug("Volumestep %d is not available \n", vstep_idx); + return Tfa98xx_Error_Bad_Parameter; + } + + if (tfa->p_regInfo == NULL) { + if (tfa->verbose) + pr_debug("Inital vstep write\n"); + enp = 0; + } + + regInfo = tfaContGetRegForVstep(vp, vstep_idx); + + msgInfo = tfaContGetmsgInfoFromReg(regInfo); + nrMessages = msgInfo->NrOfMessages; + + if (enp) { + p_msgInfo = tfaContGetmsgInfoFromReg(tfa->p_regInfo); + if (nrMessages != p_msgInfo->NrOfMessages) { + pr_debug( + "Message different - Disable partial update\n"); + enp = 0; + } + } + + for (i = 0; i < nrMessages; i++) { + /* Messagetype(3) is Smartstudio Info! Dont send this! */ + if (msgInfo->MessageType == 3) { + /* MessageLength is in bytes */ + msgInfo = tfaContGetNextmsgInfo(msgInfo); + if (enp) + p_msgInfo = tfaContGetNextmsgInfo(p_msgInfo); + continue; + } + + /* If no vstepMsgIndex is passed on, all message needs to be send */ + if ((vstep_msg_idx >= TFA_MAX_VSTEP_MSG_MARKER) || + (vstep_msg_idx == i)) { + err = tfaContWriteVstepMax2_One(tfa, msgInfo, p_msgInfo, + enp); + if (err != Tfa98xx_Error_Ok) { + /* + * Force a full update for the next write + * As the current status of the DSP is unknown + */ + tfa->p_regInfo = NULL; + return err; + } + } + + msgInfo = tfaContGetNextmsgInfo(msgInfo); + if (enp) + p_msgInfo = tfaContGetNextmsgInfo(p_msgInfo); + } + + tfa->p_regInfo = regInfo; + + for (i = 0; i < regInfo->NrOfRegisters * 2; i++) { + /* Byte swap the datasheetname */ + bitF.field = (uint16_t)(regInfo->registerInfo[i] >> 8) | + (regInfo->registerInfo[i] << 8); + i++; + bitF.value = (uint16_t)regInfo->registerInfo[i] >> 8; + err = tfaRunWriteBitfield(tfa, bitF); + if (err != Tfa98xx_Error_Ok) + return err; + } + + /* Save the current vstep */ + tfa_dev_set_swvstep(tfa, (unsigned short)vstep_idx); + + return err; +} + +/* + * Write DRC message to the dsp + * If needed modify the cmd-id + */ + +enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size, + uint8_t data[]) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + uint8_t *msg = NULL; + + msg = kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + if (msg == NULL) + return Tfa98xx_Error_Fail; + memcpy(msg, data, size); + + if (TFA_GET_BF(tfa, SBSL) == 0) { + /* Only do this when not set already */ + if (msg[2] != SB_PARAM_SET_MBDRC) { + msg[2] = SB_PARAM_SET_MBDRC; + + if (tfa->verbose) { + pr_debug("P-ID for SetMBDrc modified!: "); + pr_debug("Command-ID used: 0x%02x%02x%02x \n", + msg[0], msg[1], msg[2]); + } + } + } + + /* Send cmdId + payload to dsp */ + err = dsp_msg(tfa, size, (const char *)msg); + + kmem_cache_free(tfa->cachep, msg); + + return err; +} + +/* + * write a parameter file to the device + * The VstepIndex and VstepMsgIndex are only used to write a specific msg from the vstep file. + */ +enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa, + nxpTfaFileDsc_t *file, int vstep_idx, + int vstep_msg_idx) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaHeader_t *hdr = (nxpTfaHeader_t *)file->data; + nxpTfaHeaderType_t type; + int size; + + if (tfa->verbose) { + tfaContShowHeader(hdr); + } + + type = (nxpTfaHeaderType_t)hdr->id; + + switch (type) { + case msgHdr: /* generic DSP message */ + size = hdr->size - sizeof(nxpTfaMsgFile_t); + err = dsp_msg(tfa, size, + (const char *)((nxpTfaMsgFile_t *)hdr)->data); + break; + case volstepHdr: + if (tfa->tfa_family == 2) { + err = tfaContWriteVstepMax2( + tfa, (nxpTfaVolumeStepMax2File_t *)hdr, + vstep_idx, vstep_msg_idx); + } else { + err = tfaContWriteVstep( + tfa, (nxpTfaVolumeStep2File_t *)hdr, vstep_idx); + } + break; + case speakerHdr: + if (tfa->tfa_family == 2) { + /* Remove header and xml_id */ + size = hdr->size - sizeof(struct nxpTfaSpkHeader) - + sizeof(struct nxpTfaFWVer); + + err = dsp_msg( + tfa, size, + (const char *)(((nxpTfaSpeakerFile_t *)hdr) + ->data + + (sizeof(struct nxpTfaFWVer)))); + } else { + size = hdr->size - sizeof(nxpTfaSpeakerFile_t); + err = tfa98xx_dsp_write_speaker_parameters( + tfa, size, + (const unsigned char *)((nxpTfaSpeakerFile_t *) + hdr) + ->data); + } + break; + case presetHdr: + size = hdr->size - sizeof(nxpTfaPreset_t); + err = tfa98xx_dsp_write_preset( + tfa, size, + (const unsigned char *)((nxpTfaPreset_t *)hdr)->data); + break; + case equalizerHdr: + err = tfa_cont_write_filterbank( + tfa, ((nxpTfaEqualizerFile_t *)hdr)->filter); + break; + case patchHdr: + size = hdr->size - + sizeof(nxpTfaPatch_t); // size is total length + err = tfa_dsp_patch( + tfa, size, + (const unsigned char *)((nxpTfaPatch_t *)hdr)->data); + break; + case configHdr: + size = hdr->size - sizeof(nxpTfaConfig_t); + err = tfa98xx_dsp_write_config( + tfa, size, + (const unsigned char *)((nxpTfaConfig_t *)hdr)->data); + break; + case drcHdr: + if (hdr->version[0] == NXPTFA_DR3_VERSION) { + /* Size is total size - hdrsize(36) - xmlversion(3) */ + size = hdr->size - sizeof(nxpTfaDrc2_t); + err = tfaContWriteDrcFile(tfa, size, + ((nxpTfaDrc2_t *)hdr)->data); + } else { + /* + * The DRC file is split as: + * 36 bytes for generic header (customer, application, and type) + * 127x3 (381) bytes first block contains the device and sample rate + * independent settings + * 127x3 (381) bytes block the device and sample rate specific values. + * The second block can always be recalculated from the first block, + * if vlsCal and the sample rate are known. + */ + //size = hdr->size - sizeof(nxpTfaDrc_t); + size = 381; /* fixed size for first block */ + + //+381 is done to only send the second part of the drc block + err = tfa98xx_dsp_write_drc( + tfa, size, + ((const unsigned char *)((nxpTfaDrc_t *)hdr) + ->data + + 381)); + } + break; + case infoHdr: + /* Ignore */ + break; + default: + pr_err("Header is of unknown type: 0x%x\n", type); + return Tfa98xx_Error_Bad_Parameter; + } + + return err; +} + +/** + * get the 1st of this dsc type this devicelist + */ +static nxpTfaDescPtr_t *tfa_cnt_get_dsc(nxpTfaContainer_t *cnt, + nxpTfaDescriptorType_t type, + int dev_idx) +{ + nxpTfaDeviceList_t *dev = tfaContDevice(cnt, dev_idx); + nxpTfaDescPtr_t *_this; + int i; + + if (!dev) { + return NULL; + } + /* process the list until a the type is encountered */ + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == (uint32_t)type) { + _this = (nxpTfaDescPtr_t *)(dev->list[i].offset + + (uint8_t *)cnt); + return _this; + } + } + + return NULL; +} + +/** + * get the device type from the patch in this devicelist + * - find the patch file for this devidx + * - return the devid from the patch or 0 if not found + */ +int tfa_cnt_get_devid(nxpTfaContainer_t *cnt, int dev_idx) +{ + nxpTfaPatch_t *patchfile; + nxpTfaDescPtr_t *patchdsc; + uint8_t *patchheader; + unsigned short devid, checkaddress; + int checkvalue; + + patchdsc = tfa_cnt_get_dsc(cnt, dscPatch, dev_idx); + if (!patchdsc) /* no patch for this device, assume non-i2c */ + return 0; + patchdsc += 2; /* first the filename dsc and filesize, so skip them */ + patchfile = (nxpTfaPatch_t *)patchdsc; + + patchheader = patchfile->data; + + checkaddress = (patchheader[1] << 8) + patchheader[2]; + checkvalue = + (patchheader[3] << 16) + (patchheader[4] << 8) + patchheader[5]; + + devid = patchheader[0]; + + if (checkaddress == 0xFFFF && checkvalue != 0xFFFFFF && + checkvalue != 0) { + devid = patchheader[5] << 8 | patchheader[0]; /* full revid */ + } + + return devid; +} + +/** + * get the firmware version from the patch in this devicelist + */ +int tfa_cnt_get_patch_version(struct tfa_device *tfa) +{ + nxpTfaPatch_t *patchfile; + nxpTfaDescPtr_t *patchdsc; + uint8_t *data; + int size, version; + + if (tfa->cnt == NULL) + return -1; + + patchdsc = tfa_cnt_get_dsc(tfa->cnt, dscPatch, tfa->dev_idx); + patchdsc += 2; /* first the filename dsc and filesize, so skip them */ + patchfile = (nxpTfaPatch_t *)patchdsc; + + size = patchfile->hdr.size - sizeof(nxpTfaPatch_t); + data = patchfile->data; + + version = + (data[size - 3] << 16) + (data[size - 2] << 8) + data[size - 1]; + + return version; +} + +/* + * get the slave for the device if it exists + */ +enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr) +{ + nxpTfaDeviceList_t *dev = NULL; + + /* Make sure the cnt file is loaded */ + if (tfa->cnt != NULL) { + dev = tfaContDevice(tfa->cnt, tfa->dev_idx); + } + + if (dev == NULL) { + /* Check if slave argument is used! */ + if (gslave_address == 0) { + return Tfa98xx_Error_Bad_Parameter; + } else { + *slave_addr = gslave_address; + return Tfa98xx_Error_Ok; + } + } + + *slave_addr = dev->dev; + return Tfa98xx_Error_Ok; +} + +/* If no container file is given, we can always have used the slave argument */ +void tfaContSetSlave(uint8_t slave_addr) +{ + gslave_address = slave_addr; +} + +/* + * lookup slave and return device index + */ +int tfa_cont_get_idx(struct tfa_device *tfa) +{ + nxpTfaDeviceList_t *dev = NULL; + int i; + + for (i = 0; i < tfa->cnt->ndev; i++) { + dev = tfaContDevice(tfa->cnt, i); + if (dev->dev == tfa->slave_address) + break; + } + if (i == tfa->cnt->ndev) + return -1; + + return i; +} + +/* + * write a bit field + */ +enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa, + nxpTfaBitfield_t bf) +{ + enum Tfa98xx_Error error; + uint16_t value; + union { + uint16_t field; + nxpTfaBfEnum_t Enum; + } bfUni; + + value = bf.value; + bfUni.field = bf.field; +#ifdef TFA_DEBUG + if (tfa->verbose) + pr_debug("bitfield: %s=0x%x (0x%x[%d..%d]=0x%x)\n", + tfaContBfName(bfUni.field, tfa->rev), value, + bfUni.Enum.address, bfUni.Enum.pos, + bfUni.Enum.pos + bfUni.Enum.len, value); +#endif + error = tfa_set_bf(tfa, bfUni.field, value); + + return error; +} + +/* + * read a bit field + */ +enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa, + nxpTfaBitfield_t *bf) +{ + enum Tfa98xx_Error error; + union { + uint16_t field; + nxpTfaBfEnum_t Enum; + } bfUni; + uint16_t regvalue, msk; + + bfUni.field = bf->field; + + error = reg_read(tfa, (unsigned char)(bfUni.Enum.address), ®value); + if (error) + return error; + + msk = ((1 << (bfUni.Enum.len + 1)) - 1) << bfUni.Enum.pos; + + regvalue &= msk; + bf->value = regvalue >> bfUni.Enum.pos; + + return error; +} + +/* + dsp mem direct write + */ +static enum Tfa98xx_Error tfaRunWriteDspMem(struct tfa_device *tfa, + nxpTfaDspMem_t *cfmem) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int i; + + for (i = 0; i < cfmem->size; i++) { + if (tfa->verbose) + pr_debug("dsp mem (%d): 0x%02x=0x%04x\n", cfmem->type, + cfmem->address, cfmem->words[i]); + + error = mem_write(tfa, cfmem->address++, cfmem->words[i], + cfmem->type); + if (error) + return error; + } + + return error; +} + +/* + * write filter payload to DSP + * note that the data is in an aligned union for all filter variants + * the aa data is used but it's the same for all of them + */ +static enum Tfa98xx_Error tfaRunWriteFilter(struct tfa_device *tfa, + nxpTfaContBiquad_t *bq) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + enum Tfa98xx_DMEM dmem; + uint16_t address; + uint8_t data[3 * 3 + sizeof(bq->aa.bytes)]; + int i, channel = 0, runs = 1; + int8_t saved_index = + bq->aa.index; /* This is used to set back the index */ + + /* Channel=1 is primary, Channel=2 is secondary*/ + if (bq->aa.index > 100) { + bq->aa.index -= 100; + channel = 2; + } else if (bq->aa.index > 50) { + bq->aa.index -= 50; + channel = 1; + } else if ((tfa->rev & 0xff) == 0x88) { + runs = 2; + } + + if (tfa->verbose) { + if (channel == 2) + pr_debug("filter[%d,S]", bq->aa.index); + else if (channel == 1) + pr_debug("filter[%d,P]", bq->aa.index); + else + pr_debug("filter[%d]", bq->aa.index); + } + + for (i = 0; i < runs; i++) { + if (runs == 2) + channel++; + + /* get the target address for the filter on this device */ + dmem = tfa98xx_filter_mem(tfa, bq->aa.index, &address, channel); + if (dmem == Tfa98xx_DMEM_ERR) { + if (tfa->verbose) { + pr_debug( + "Warning: XFilter settings are applied via msg file (ini filter[x] format is skipped).\n"); + } + /* Dont exit with an error here, We could continue without problems */ + return Tfa98xx_Error_Ok; + } + + /* send a DSP memory message that targets the devices specific memory for the filter + * msg params: which_mem, start_offset, num_words + */ + memset(data, 0, 3 * 3); + data[2] = dmem; /* output[0] = which_mem */ + data[4] = address >> 8; /* output[1] = start_offset */ + data[5] = address & 0xff; + data[8] = sizeof(bq->aa.bytes) / 3; /*output[2] = num_words */ + memcpy(&data[9], bq->aa.bytes, + sizeof(bq->aa.bytes)); /* payload */ + + if (tfa->tfa_family == 2) { + error = tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, + FW_PAR_ID_SET_MEMORY, + sizeof(data), data); + } else { + error = tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, + 4 /* param */, + sizeof(data), data); + } + } + +#ifdef TFA_DEBUG + if (tfa->verbose) { + if (bq->aa.index == 13) { + pr_debug("=%d,%.0f,%.2f \n", bq->in.type, + bq->in.cutOffFreq, bq->in.leakage); + } else if (bq->aa.index >= 10 && bq->aa.index <= 12) { + pr_debug("=%d,%.0f,%.1f,%.1f \n", bq->aa.type, + bq->aa.cutOffFreq, bq->aa.rippleDb, + bq->aa.rolloff); + } else { + pr_debug("= unsupported filter index \n"); + } + } +#endif + + /* Because we can load the same filters multiple times + * For example: When we switch profile we re-write in operating mode. + * We then need to remember the index (primary, secondary or both) + */ + bq->aa.index = saved_index; + + return error; +} + +/* + * write the register based on the input address, value and mask + * only the part that is masked will be updated + */ +static enum Tfa98xx_Error tfaRunWriteRegister(struct tfa_device *tfa, + nxpTfaRegpatch_t *reg) +{ + enum Tfa98xx_Error error; + uint16_t value, newvalue; + + if (tfa->verbose) + pr_debug("register: 0x%02x=0x%04x (msk=0x%04x)\n", reg->address, + reg->value, reg->mask); + + error = reg_read(tfa, reg->address, &value); + if (error) + return error; + + value &= ~reg->mask; + newvalue = reg->value & reg->mask; + + value |= newvalue; + error = reg_write(tfa, reg->address, value); + + return error; +} + +// write reg and bitfield items in the devicelist to the target +enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa) +{ + nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx); + nxpTfaBitfield_t *bitF; + int i; + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + if (!dev) { + return Tfa98xx_Error_Bad_Parameter; + } + + /* process the list until a patch, file of profile is encountered */ + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == dscPatch || + dev->list[i].type == dscFile || + dev->list[i].type == dscProfile) + break; + + if (dev->list[i].type == dscBitfield) { + bitF = (nxpTfaBitfield_t *)(dev->list[i].offset + + (uint8_t *)tfa->cnt); + err = tfaRunWriteBitfield(tfa, *bitF); + } + if (dev->list[i].type == dscRegister) { + err = tfaRunWriteRegister( + tfa, (nxpTfaRegpatch_t *)(dev->list[i].offset + + (char *)tfa->cnt)); + } + + if (err) + break; + } + + return err; +} + +// write reg and bitfield items in the profilelist the target +enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx) +{ + nxpTfaProfileList_t *prof = + tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + nxpTfaBitfield_t *bitf; + unsigned int i; + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + if (!prof) { + return Tfa98xx_Error_Bad_Parameter; + } + + if (tfa->verbose) + pr_debug("----- profile: %s (%d) -----\n", + tfaContGetString(tfa->cnt, &prof->name), prof_idx); + + /* process the list until the end of the profile or the default section */ + for (i = 0; i < prof->length; i++) { + /* We only want to write the values before the default section when we switch profile */ + if (prof->list[i].type == dscDefault) + break; + + if (prof->list[i].type == dscBitfield) { + bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + err = tfaRunWriteBitfield(tfa, *bitf); + } + if (prof->list[i].type == dscRegister) { + err = tfaRunWriteRegister( + tfa, (nxpTfaRegpatch_t *)(prof->list[i].offset + + (char *)tfa->cnt)); + } + if (err) + break; + } + return err; +} + +// write patchfile in the devicelist to the target +enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx); + nxpTfaFileDsc_t *file; + nxpTfaPatch_t *patchfile; + int size, i; + + if (!dev) { + return Tfa98xx_Error_Bad_Parameter; + } + /* process the list until a patch is encountered */ + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == dscPatch) { + file = (nxpTfaFileDsc_t *)(dev->list[i].offset + + (uint8_t *)tfa->cnt); + patchfile = (nxpTfaPatch_t *)&file->data; + if (tfa->verbose) + tfaContShowHeader(&patchfile->hdr); + size = patchfile->hdr.size - + sizeof(nxpTfaPatch_t); // size is total length + err = tfa_dsp_patch( + tfa, size, + (const unsigned char *)patchfile->data); + if (err) + return err; + } + } + + return Tfa98xx_Error_Ok; +} + +/** + * Create a buffer which can be used to send to the dsp. + */ +static void create_dsp_buffer_msg(struct tfa_device *tfa, nxpTfaMsg_t *msg, + char *buffer, int *size) +{ + int i, nr = 0; + + (void)tfa; + + /* Copy cmdId. Remember that the cmdId is reversed */ + buffer[nr++] = msg->cmdId[2]; + buffer[nr++] = msg->cmdId[1]; + buffer[nr++] = msg->cmdId[0]; + + /* Copy the data to the buffer */ + for (i = 0; i < msg->msg_size; i++) { + buffer[nr++] = (uint8_t)((msg->data[i] >> 16) & 0xffff); + buffer[nr++] = (uint8_t)((msg->data[i] >> 8) & 0xff); + buffer[nr++] = (uint8_t)(msg->data[i] & 0xff); + } + + *size = nr; +} + +// write all param files in the devicelist to the target +enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa) +{ + nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx); + nxpTfaFileDsc_t *file; + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + char buffer[(MEMTRACK_MAX_WORDS * 3) + 3] = { + 0 + }; //every word requires 3 and 3 is the msg + int i, size = 0; + + if (!dev) { + return Tfa98xx_Error_Bad_Parameter; + } + /* process the list and write all files */ + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == dscFile) { + file = (nxpTfaFileDsc_t *)(dev->list[i].offset + + (uint8_t *)tfa->cnt); + if (tfaContWriteFile(tfa, file, 0, + TFA_MAX_VSTEP_MSG_MARKER)) { + return Tfa98xx_Error_Bad_Parameter; + } + } + + if (dev->list[i].type == dscSetInputSelect || + dev->list[i].type == dscSetOutputSelect || + dev->list[i].type == dscSetProgramConfig || + dev->list[i].type == dscSetLagW || + dev->list[i].type == dscSetGains || + dev->list[i].type == dscSetvBatFactors || + dev->list[i].type == dscSetSensesCal || + dev->list[i].type == dscSetSensesDelay || + dev->list[i].type == dscSetMBDrc || + dev->list[i].type == dscSetFwkUseCase || + dev->list[i].type == dscSetVddpConfig) { + create_dsp_buffer_msg( + tfa, + (nxpTfaMsg_t *)(dev->list[i].offset + + (char *)tfa->cnt), + buffer, &size); + if (tfa->verbose) { + pr_debug("command: %s=0x%02x%02x%02x \n", + tfaContGetCommandString( + dev->list[i].type), + (unsigned char)buffer[0], + (unsigned char)buffer[1], + (unsigned char)buffer[2]); + } + + err = dsp_msg(tfa, size, buffer); + } + + if (dev->list[i].type == dscCmd) { + size = *(uint16_t *)(dev->list[i].offset + + (char *)tfa->cnt); + + err = dsp_msg(tfa, size, + dev->list[i].offset + 2 + + (char *)tfa->cnt); + if (tfa->verbose) { + const char *cmd_id = dev->list[i].offset + 2 + + (char *)tfa->cnt; + pr_debug("Writing cmd=0x%02x%02x%02x \n", + (uint8_t)cmd_id[0], (uint8_t)cmd_id[1], + (uint8_t)cmd_id[2]); + } + } + if (err != Tfa98xx_Error_Ok) + break; + + if (dev->list[i].type == dscCfMem) { + err = tfaRunWriteDspMem( + tfa, (nxpTfaDspMem_t *)(dev->list[i].offset + + (uint8_t *)tfa->cnt)); + } + + if (err != Tfa98xx_Error_Ok) + break; + } + + return err; +} + +/* + * write all param files in the profilelist to the target + * this is used during startup when maybe ACS is set + */ +enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx, + int vstep_idx) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaProfileList_t *prof = + tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + char buffer[(MEMTRACK_MAX_WORDS * 3) + 3] = { + 0 + }; //every word requires 3 and 3 is the msg + unsigned int i; + nxpTfaFileDsc_t *file; + nxpTfaPatch_t *patchfile; + int size; + + if (!prof) { + return Tfa98xx_Error_Bad_Parameter; + } + + /* process the list and write all files */ + for (i = 0; i < prof->length; i++) { + switch (prof->list[i].type) { + case dscFile: + file = (nxpTfaFileDsc_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + err = tfaContWriteFile(tfa, file, vstep_idx, + TFA_MAX_VSTEP_MSG_MARKER); + break; + case dscPatch: + file = (nxpTfaFileDsc_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + patchfile = (nxpTfaPatch_t *)&file->data; + if (tfa->verbose) + tfaContShowHeader(&patchfile->hdr); + size = patchfile->hdr.size - + sizeof(nxpTfaPatch_t); // size is total length + err = tfa_dsp_patch( + tfa, size, + (const unsigned char *)patchfile->data); + break; + case dscCfMem: + err = tfaRunWriteDspMem( + tfa, (nxpTfaDspMem_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt)); + break; + case dscSetInputSelect: + case dscSetOutputSelect: + case dscSetProgramConfig: + case dscSetLagW: + case dscSetGains: + case dscSetvBatFactors: + case dscSetSensesCal: + case dscSetSensesDelay: + case dscSetMBDrc: + case dscSetFwkUseCase: + case dscSetVddpConfig: + create_dsp_buffer_msg( + tfa, + (nxpTfaMsg_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt), + buffer, &size); + if (tfa->verbose) { + pr_debug("command: %s=0x%02x%02x%02x \n", + tfaContGetCommandString( + prof->list[i].type), + (unsigned char)buffer[0], + (unsigned char)buffer[1], + (unsigned char)buffer[2]); + } + + err = dsp_msg(tfa, size, buffer); + break; + default: + /* ignore any other type */ + break; + } + } + + return err; +} + +static enum Tfa98xx_Error tfaContWriteItem(struct tfa_device *tfa, + nxpTfaDescPtr_t *dsc) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaRegpatch_t *reg; + nxpTfaMode_t *cas; + nxpTfaBitfield_t *bitf; + + // When no DSP should only write to HW registers. + if (tfa->ext_dsp == 0 && + !(dsc->type == dscBitfield || dsc->type == dscRegister)) { + return Tfa98xx_Error_Ok; + } + + switch (dsc->type) { + case dscDefault: + case dscDevice: // ignore + case dscProfile: // profile list + break; + case dscRegister: // register patch + reg = (nxpTfaRegpatch_t *)(dsc->offset + (uint8_t *)tfa->cnt); + return tfaRunWriteRegister(tfa, reg); + //pr_debug("$0x%2x=0x%02x,0x%02x\n", reg->address, reg->mask, reg->value); + break; + case dscString: // ascii: zero terminated string + pr_debug(";string: %s\n", tfaContGetString(tfa->cnt, dsc)); + break; + case dscFile: // filename + file contents + case dscPatch: + break; + case dscMode: + cas = (nxpTfaMode_t *)(dsc->offset + (uint8_t *)tfa->cnt); + if (cas->value == Tfa98xx_Mode_RCV) + tfa98xx_select_mode(tfa, Tfa98xx_Mode_RCV); + else + tfa98xx_select_mode(tfa, Tfa98xx_Mode_Normal); + break; + case dscCfMem: + err = tfaRunWriteDspMem( + tfa, + (nxpTfaDspMem_t *)(dsc->offset + (uint8_t *)tfa->cnt)); + break; + case dscBitfield: + bitf = (nxpTfaBitfield_t *)(dsc->offset + (uint8_t *)tfa->cnt); + return tfaRunWriteBitfield(tfa, *bitf); + break; + case dscFilter: + return tfaRunWriteFilter( + tfa, (nxpTfaContBiquad_t *)(dsc->offset + + (uint8_t *)tfa->cnt)); + break; + } + + return err; +} + +static unsigned int tfa98xx_sr_from_field(unsigned int field) +{ + switch (field) { + case 0: + return 8000; + case 1: + return 11025; + case 2: + return 12000; + case 3: + return 16000; + case 4: + return 22050; + case 5: + return 24000; + case 6: + return 32000; + case 7: + return 44100; + case 8: + return 48000; + default: + return 0; + } +} + +enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaProfileList_t *prof = + tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + unsigned int i; + int status; + + if (!prof) { + return Tfa98xx_Error_Bad_Parameter; + } + + if (tfa->verbose) { + pr_debug("----- profile: %s (%d) -----\n", + tfaContGetString(tfa->cnt, &prof->name), prof_idx); + pr_debug("Waiting for CLKS... \n"); + } + + for (i = 10; i > 0; i--) { + err = tfa98xx_dsp_system_stable(tfa, &status); + if (status) + break; + else + msleep_interruptible(10); + } + + if (i == 0) { + if (tfa->verbose) + pr_err("Unable to write filters, CLKS=0 \n"); + + return Tfa98xx_Error_StateTimedOut; + } + + /* process the list until the end of the profile or the default section */ + for (i = 0; i < prof->length; i++) { + if (prof->list[i].type == dscFilter) { + if (tfaContWriteItem(tfa, &prof->list[i]) != + Tfa98xx_Error_Ok) + return Tfa98xx_Error_Bad_Parameter; + } + } + + return err; +} + +unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa, + unsigned int prof_idx) +{ + nxpTfaBitfield_t *bitf; + unsigned int i; + nxpTfaDeviceList_t *dev; + nxpTfaProfileList_t *prof; + int fs_profile = -1; + + dev = tfaContDevice(tfa->cnt, tfa->dev_idx); + if (!dev) + return 0; + + prof = tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + if (!prof) + return 0; + + /* Check profile fields first */ + for (i = 0; i < prof->length; i++) { + if (prof->list[i].type == dscDefault) + break; + + /* check for profile settingd (AUDFS) */ + if (prof->list[i].type == dscBitfield) { + bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + if (bitf->field == TFA_FAM(tfa, AUDFS)) { + fs_profile = bitf->value; + break; + } + } + } + + if (tfa->verbose) + pr_debug("%s - profile fs: 0x%x = %dHz (%d - %d)\n", + __FUNCTION__, fs_profile, + tfa98xx_sr_from_field(fs_profile), tfa->dev_idx, + prof_idx); + + if (fs_profile != -1) + return tfa98xx_sr_from_field(fs_profile); + + /* Check for container default setting */ + /* process the list until a patch, file of profile is encountered */ + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == dscPatch || + dev->list[i].type == dscFile || + dev->list[i].type == dscProfile) + break; + + if (dev->list[i].type == dscBitfield) { + bitf = (nxpTfaBitfield_t *)(dev->list[i].offset + + (uint8_t *)tfa->cnt); + if (bitf->field == TFA_FAM(tfa, AUDFS)) { + fs_profile = bitf->value; + break; + } + } + /* Ignore register case */ + } + + if (tfa->verbose) + pr_debug("%s - default fs: 0x%x = %dHz (%d - %d)\n", + __FUNCTION__, fs_profile, + tfa98xx_sr_from_field(fs_profile), tfa->dev_idx, + prof_idx); + + if (fs_profile != -1) + return tfa98xx_sr_from_field(fs_profile); + + return 48000; /* default of HW */ +} + +static enum Tfa98xx_Error +get_sample_rate_info(struct tfa_device *tfa, nxpTfaProfileList_t *prof, + nxpTfaProfileList_t *previous_prof, + int fs_previous_profile) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaBitfield_t *bitf; + unsigned int i; + int fs_default_profile = 8; /* default is 48kHz */ + int fs_next_profile = 8; /* default is 48kHz */ + + /* ---------- default settings previous profile ---------- */ + for (i = 0; i < previous_prof->length; i++) { + /* Search for the default section */ + if (i == 0) { + while (previous_prof->list[i].type != dscDefault && + i < previous_prof->length) { + i++; + } + i++; + } + + /* Only if we found the default section search for AUDFS */ + if (i < previous_prof->length) { + if (previous_prof->list[i].type == dscBitfield) { + bitf = (nxpTfaBitfield_t *)(previous_prof + ->list[i] + .offset + + (uint8_t *)tfa->cnt); + if (bitf->field == TFA_FAM(tfa, AUDFS)) { + fs_default_profile = bitf->value; + break; + } + } + } + } + + /* ---------- settings next profile ---------- */ + for (i = 0; i < prof->length; i++) { + /* We only want to write the values before the default section */ + if (prof->list[i].type == dscDefault) + break; + /* search for AUDFS */ + if (prof->list[i].type == dscBitfield) { + bitf = (nxpTfaBitfield_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + if (bitf->field == TFA_FAM(tfa, AUDFS)) { + fs_next_profile = bitf->value; + break; + } + } + } + + /* Enable if needed for debugging! + if (tfa->verbose) { + pr_debug("sample rate from the previous profile: %d \n", fs_previous_profile); + pr_debug("sample rate in the default section: %d \n", fs_default_profile); + pr_debug("sample rate for the next profile: %d \n", fs_next_profile); + } + */ + + if (fs_next_profile != fs_default_profile) { + if (tfa->verbose) + pr_debug("Writing delay tables for AUDFS=%d \n", + fs_next_profile); + + /* If the AUDFS from the next profile is not the same as + * the AUDFS from the default we need to write new delay tables + */ + err = tfa98xx_dsp_write_tables(tfa, fs_next_profile); + } else if (fs_default_profile != fs_previous_profile) { + if (tfa->verbose) + pr_debug("Writing delay tables for AUDFS=%d \n", + fs_default_profile); + + /* But if we do not have a new AUDFS in the next profile and + * the AUDFS from the default profile is not the same as the AUDFS + * from the previous profile we also need to write new delay tables + */ + err = tfa98xx_dsp_write_tables(tfa, fs_default_profile); + } + + return err; +} + +/* + * process all items in the profilelist + * NOTE an error return during processing will leave the device muted + * + */ +enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx, + int vstep_idx) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaProfileList_t *prof = + tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + nxpTfaProfileList_t *previous_prof = tfaContGetDevProfList( + tfa->cnt, tfa->dev_idx, tfa_dev_get_swprof(tfa)); + char buffer[(MEMTRACK_MAX_WORDS * 4) + 4] = { + 0 + }; //every word requires 3 or 4 bytes, and 3 or 4 is the msg + unsigned int i, k = 0, j = 0, tries = 0; + nxpTfaFileDsc_t *file; + int size = 0, ready, fs_previous_profile = 8; /* default fs is 48kHz*/ + + if (!prof || !previous_prof) { + pr_err("Error trying to get the (previous) swprofile \n"); + return Tfa98xx_Error_Bad_Parameter; + } + + if (tfa->verbose) { + tfa98xx_trace_printk("device:%s profile:%s vstep:%d\n", + tfaContDeviceName(tfa->cnt, tfa->dev_idx), + tfaContProfileName(tfa->cnt, tfa->dev_idx, + prof_idx), + vstep_idx); + } + + /* We only make a power cycle when the profiles are not in the same group */ + if (prof->group == previous_prof->group && prof->group != 0) { + if (tfa->verbose) { + pr_debug( + "The new profile (%s) is in the same group as the current profile (%s) \n", + tfaContGetString(tfa->cnt, &prof->name), + tfaContGetString(tfa->cnt, + &previous_prof->name)); + } + } else { + /* mute */ + err = tfaRunMute(tfa); + if (err) + return err; + + /* Get current sample rate before we start switching */ + fs_previous_profile = TFA_GET_BF(tfa, AUDFS); + + /* clear SBSL to make sure we stay in initCF state */ + if (tfa->tfa_family == 2) { + TFA_SET_BF_VOLATILE(tfa, SBSL, 0); + } + + /* When we switch profile we first power down the subsystem + * This should only be done when we are in operating mode + */ + if (((tfa->tfa_family == 2) && + (TFA_GET_BF(tfa, MANSTATE) >= 6)) || + (tfa->tfa_family != 2)) { + err = tfa98xx_powerdown(tfa, 1); + if (err) + return err; + + /* Wait until we are in PLL powerdown */ + do { + err = tfa98xx_dsp_system_stable(tfa, &ready); + if (!ready) + break; + else + msleep_interruptible( + 10); /* wait 10ms to avoid busload */ + tries++; + } while (tries <= 100); + + if (tries > 100) { + pr_debug("Wait for PLL powerdown timed out!\n"); + return Tfa98xx_Error_StateTimedOut; + } + } else { + pr_debug("No need to go to powerdown now \n"); + } + } + + /* set all bitfield settings */ + /* First set all default settings */ + if (tfa->verbose) { + pr_debug( + "---------- default settings profile: %s (%d) ---------- \n", + tfaContGetString(tfa->cnt, &previous_prof->name), + tfa_dev_get_swprof(tfa)); + } + + err = show_current_state(tfa); + + /* Loop profile length */ + for (i = 0; i < previous_prof->length; i++) { + /* Search for the default section */ + if (i == 0) { + while (previous_prof->list[i].type != dscDefault && + i < previous_prof->length) { + i++; + } + i++; + } + + /* Only if we found the default section try writing the items */ + if (i < previous_prof->length) { + if (tfaContWriteItem(tfa, &previous_prof->list[i]) != + Tfa98xx_Error_Ok) + return Tfa98xx_Error_Bad_Parameter; + } + } + + if (tfa->verbose) + pr_debug( + "---------- new settings profile: %s (%d) ---------- \n", + tfaContGetString(tfa->cnt, &prof->name), prof_idx); + + /* set new settings */ + for (i = 0; i < prof->length; i++) { + /* Remember where we currently are with writing items*/ + j = i; + + /* We only want to write the values before the default section when we switch profile */ + /* process and write all non-file items */ + switch (prof->list[i].type) { + case dscFile: + case dscPatch: + case dscSetInputSelect: + case dscSetOutputSelect: + case dscSetProgramConfig: + case dscSetLagW: + case dscSetGains: + case dscSetvBatFactors: + case dscSetSensesCal: + case dscSetSensesDelay: + case dscSetMBDrc: + case dscSetFwkUseCase: + case dscSetVddpConfig: + case dscCmd: + case dscFilter: + case dscDefault: + /* When one of these files are found, we exit */ + i = prof->length; + break; + default: + err = tfaContWriteItem(tfa, &prof->list[i]); + if (err != Tfa98xx_Error_Ok) + return Tfa98xx_Error_Bad_Parameter; + break; + } + } + + if (prof->group != previous_prof->group || prof->group == 0) { + if (tfa->tfa_family == 2) + TFA_SET_BF_VOLATILE(tfa, MANSCONF, 1); + + /* Leave powerdown state */ + err = tfa_cf_powerup(tfa); + if (err) + return err; + + err = show_current_state(tfa); + + if (tfa->tfa_family == 2) { + /* Reset SBSL to 0 (workaround of enbl_powerswitch=0) */ + TFA_SET_BF_VOLATILE(tfa, SBSL, 0); + /* Sending commands to DSP we need to make sure RST is 0 (otherwise we get no response)*/ + TFA_SET_BF(tfa, RST, 0); + } + } + + /* Check if there are sample rate changes */ + err = get_sample_rate_info(tfa, prof, previous_prof, + fs_previous_profile); + if (err) + return err; + + /* Write files from previous profile (default section) + * Should only be used for the patch&trap patch (file) + */ + if (tfa->ext_dsp != 0) { + if (tfa->tfa_family == 2) { + for (i = 0; i < previous_prof->length; i++) { + /* Search for the default section */ + if (i == 0) { + while (previous_prof->list[i].type != + dscDefault && + i < previous_prof->length) { + i++; + } + i++; + } + + /* Only if we found the default section try writing the file */ + if (i < previous_prof->length) { + if (previous_prof->list[i].type == + dscFile || + previous_prof->list[i].type == + dscPatch) { + /* Only write this once */ + if (tfa->verbose && k == 0) { + pr_debug( + "---------- files default profile: %s (%d) ---------- \n", + tfaContGetString( + tfa->cnt, + &previous_prof + ->name), + prof_idx); + k++; + } + file = (nxpTfaFileDsc_t + *)(previous_prof + ->list[i] + .offset + + (uint8_t *)tfa + ->cnt); + err = tfaContWriteFile( + tfa, file, vstep_idx, + TFA_MAX_VSTEP_MSG_MARKER); + } + } + } + } + + if (tfa->verbose) { + pr_debug( + "---------- files new profile: %s (%d) ---------- \n", + tfaContGetString(tfa->cnt, &prof->name), + prof_idx); + } + } + + /* write everything until end or the default section starts + * Start where we currenly left */ + for (i = j; i < prof->length; i++) { + /* We only want to write the values before the default section when we switch profile */ + + if (prof->list[i].type == dscDefault) { + break; + } + + switch (prof->list[i].type) { + case dscFile: + case dscPatch: + /* For tiberius stereo 1 device does not have a dsp! */ + if (tfa->ext_dsp != 0) { + file = (nxpTfaFileDsc_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + err = tfaContWriteFile( + tfa, file, vstep_idx, + TFA_MAX_VSTEP_MSG_MARKER); + } + break; + case dscSetInputSelect: + case dscSetOutputSelect: + case dscSetProgramConfig: + case dscSetLagW: + case dscSetGains: + case dscSetvBatFactors: + case dscSetSensesCal: + case dscSetSensesDelay: + case dscSetMBDrc: + case dscSetFwkUseCase: + case dscSetVddpConfig: + /* For tiberius stereo 1 device does not have a dsp! */ + if (tfa->ext_dsp != 0) { + create_dsp_buffer_msg( + tfa, + (nxpTfaMsg_t *)(prof->list[i].offset + + (char *)tfa->cnt), + buffer, &size); + err = dsp_msg(tfa, size, buffer); + + if (tfa->verbose) { + pr_debug( + "command: %s=0x%02x%02x%02x \n", + tfaContGetCommandString( + prof->list[i].type), + (unsigned char)buffer[0], + (unsigned char)buffer[1], + (unsigned char)buffer[2]); + } + } + break; + case dscCmd: + /* For tiberius stereo 1 device does not have a dsp! */ + if (tfa->ext_dsp != 0) { + size = *(uint16_t *)(prof->list[i].offset + + (char *)tfa->cnt); + err = dsp_msg(tfa, size, + prof->list[i].offset + 2 + + (char *)tfa->cnt); + if (tfa->verbose) { + const char *cmd_id = + prof->list[i].offset + 2 + + (char *)tfa->cnt; + pr_debug( + "Writing cmd=0x%02x%02x%02x \n", + (uint8_t)cmd_id[0], + (uint8_t)cmd_id[1], + (uint8_t)cmd_id[2]); + } + } + break; + default: + /* This allows us to write bitfield, registers or xmem after files */ + if (tfaContWriteItem(tfa, &prof->list[i]) != + Tfa98xx_Error_Ok) { + return Tfa98xx_Error_Bad_Parameter; + } + break; + } + + if (err != Tfa98xx_Error_Ok) { + return err; + } + } + + if ((prof->group != previous_prof->group || prof->group == 0) && + (tfa->tfa_family == 2)) { + if (TFA_GET_BF(tfa, REFCKSEL) == 0) { + /* set SBSL to go to operation mode */ + TFA_SET_BF_VOLATILE(tfa, SBSL, 1); + } + } + + return err; +} + +/* + * process only vstep in the profilelist + * + */ +enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx, + int vstep_idx) +{ + nxpTfaProfileList_t *prof = + tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + unsigned int i; + nxpTfaFileDsc_t *file; + nxpTfaHeader_t *hdr; + nxpTfaHeaderType_t type; + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + if (!prof) + return Tfa98xx_Error_Bad_Parameter; + + if (tfa->verbose) + tfa98xx_trace_printk("device:%s profile:%s vstep:%d\n", + tfaContDeviceName(tfa->cnt, tfa->dev_idx), + tfaContProfileName(tfa->cnt, tfa->dev_idx, + prof_idx), + vstep_idx); + + /* write vstep file only! */ + for (i = 0; i < prof->length; i++) { + if (prof->list[i].type == dscFile) { + file = (nxpTfaFileDsc_t *)(prof->list[i].offset + + (uint8_t *)tfa->cnt); + hdr = (nxpTfaHeader_t *)file->data; + type = (nxpTfaHeaderType_t)hdr->id; + + switch (type) { + case volstepHdr: + if (tfaContWriteFile(tfa, file, vstep_idx, + TFA_MAX_VSTEP_MSG_MARKER)) + return Tfa98xx_Error_Bad_Parameter; + break; + default: + break; + } + } + } + + return err; +} + +char *tfaContGetString(nxpTfaContainer_t *cnt, nxpTfaDescPtr_t *dsc) +{ + if (dsc->type != dscString) + return "Undefined string"; + + return dsc->offset + (char *)cnt; +} + +char *tfaContGetCommandString(uint32_t type) +{ + if (type == dscSetInputSelect) + return "SetInputSelector"; + else if (type == dscSetOutputSelect) + return "SetOutputSelector"; + else if (type == dscSetProgramConfig) + return "SetProgramConfig"; + else if (type == dscSetLagW) + return "SetLagW"; + else if (type == dscSetGains) + return "SetGains"; + else if (type == dscSetvBatFactors) + return "SetvBatFactors"; + else if (type == dscSetSensesCal) + return "SetSensesCal"; + else if (type == dscSetSensesDelay) + return "SetSensesDelay"; + else if (type == dscSetMBDrc) + return "SetMBDrc"; + else if (type == dscSetFwkUseCase) + return "SetFwkUseCase"; + else if (type == dscSetVddpConfig) + return "SetVddpConfig"; + else if (type == dscFilter) + return "filter"; + else + return "Undefined string"; +} + +/* + * Get the name of the device at a certain index in the container file + * return device name + */ +char *tfaContDeviceName(nxpTfaContainer_t *cnt, int dev_idx) +{ + nxpTfaDeviceList_t *dev; + + dev = tfaContDevice(cnt, dev_idx); + if (dev == NULL) + return "!ERROR!"; + + return tfaContGetString(cnt, &dev->name); +} + +/* + * Get the application name from the container file application field + * note that the input stringbuffer should be sizeof(application field)+1 + * + */ +int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name) +{ + unsigned int i; + int len = 0; + + for (i = 0; i < sizeof(tfa->cnt->application); i++) { + if (isalnum(tfa->cnt->application[i])) /* copy char if valid */ + name[len++] = tfa->cnt->application[i]; + if (tfa->cnt->application[i] == '\0') + break; + } + name[len++] = '\0'; + + return len; +} + +/* + * Get profile index of the calibration profile. + * Returns: (profile index) if found, (-2) if no + * calibration profile is found or (-1) on error + */ +int tfaContGetCalProfile(struct tfa_device *tfa) +{ + int prof, cal_idx = -2; + + if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev)) + return -1; + + /* search for the calibration profile in the list of profiles */ + for (prof = 0; prof < tfa->cnt->nprof; prof++) { + if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, prof), + ".cal") != NULL) { + cal_idx = prof; + pr_debug("Using calibration profile: '%s'\n", + tfaContProfileName(tfa->cnt, tfa->dev_idx, + prof)); + break; + } + } + + return cal_idx; +} + +/** + * Is the profile a tap profile + */ +int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx) +{ + if ((tfa->dev_idx < 0) || (tfa->dev_idx >= tfa->cnt->ndev)) + return -1; + + /* Check if next profile is tap profile */ + if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx), + ".tap") != NULL) { + pr_debug("Using Tap profile: '%s'\n", + tfaContProfileName(tfa->cnt, tfa->dev_idx, prof_idx)); + return 1; + } + + return 0; +} + +/* + * Get the name of the profile at certain index for a device in the container file + * return profile name + */ +char *tfaContProfileName(nxpTfaContainer_t *cnt, int dev_idx, int prof_idx) +{ + nxpTfaProfileList_t *prof = NULL; + + /* the Nth profiles for this device */ + prof = tfaContGetDevProfList(cnt, dev_idx, prof_idx); + + /* If the index is out of bound */ + if (prof == NULL) + return "NONE"; + + return tfaContGetString(cnt, &prof->name); +} + +/* + * return 1st profile list + */ +nxpTfaProfileList_t *tfaContGet1stProfList(nxpTfaContainer_t *cont) +{ + nxpTfaProfileList_t *prof; + uint8_t *b = (uint8_t *)cont; + + int maxdev = 0; + nxpTfaDeviceList_t *dev; + + // get nr of devlists + maxdev = cont->ndev; + // get last devlist + dev = tfaContGetDevList(cont, maxdev - 1); + if (dev == NULL) + return NULL; + // the 1st profile starts after the last device list + b = (uint8_t *)dev + sizeof(nxpTfaDeviceList_t) + + dev->length * (sizeof(nxpTfaDescPtr_t)); + prof = (nxpTfaProfileList_t *)b; + return prof; +} + +/* + * return 1st livedata list + */ +nxpTfaLiveDataList_t *tfaContGet1stLiveDataList(nxpTfaContainer_t *cont) +{ + nxpTfaLiveDataList_t *ldata; + nxpTfaProfileList_t *prof; + nxpTfaDeviceList_t *dev; + uint8_t *b = (uint8_t *)cont; + int maxdev, maxprof; + + // get nr of devlists+1 + maxdev = cont->ndev; + // get nr of proflists + maxprof = cont->nprof; + + // get last devlist + dev = tfaContGetDevList(cont, maxdev - 1); + // the 1st livedata starts after the last device list + b = (uint8_t *)dev + sizeof(nxpTfaDeviceList_t) + + dev->length * (sizeof(nxpTfaDescPtr_t)); + + while (maxprof != 0) { + // get last proflist + prof = (nxpTfaProfileList_t *)b; + b += sizeof(nxpTfaProfileList_t) + + ((prof->length - 1) * (sizeof(nxpTfaDescPtr_t))); + maxprof--; + } + + /* Else the marker falls off */ + b += 4; //bytes + + ldata = (nxpTfaLiveDataList_t *)b; + return ldata; +} + +/* + * return the device list pointer + */ +nxpTfaDeviceList_t *tfaContDevice(nxpTfaContainer_t *cnt, int dev_idx) +{ + return tfaContGetDevList(cnt, dev_idx); +} + +/* + * return the next profile: + * - assume that all profiles are adjacent + * - calculate the total length of the input + * - the input profile + its length is the next profile + */ +nxpTfaProfileList_t *tfaContNextProfile(nxpTfaProfileList_t *prof) +{ + uint8_t *this, *next; /* byte pointers for byte pointer arithmetic */ + nxpTfaProfileList_t *nextprof; + int listlength; /* total length of list in bytes */ + + if (prof == NULL) + return NULL; + + if (prof->ID != TFA_PROFID) + return NULL; /* invalid input */ + + this = (uint8_t *)prof; + /* nr of items in the list, length includes name dsc so - 1*/ + listlength = (prof->length - 1) * sizeof(nxpTfaDescPtr_t); + /* the sizeof(nxpTfaProfileList_t) includes the list[0] length */ + next = this + listlength + + sizeof(nxpTfaProfileList_t); // - sizeof(nxpTfaDescPtr_t); + nextprof = (nxpTfaProfileList_t *)next; + + if (nextprof->ID != TFA_PROFID) + return NULL; + + return nextprof; +} + +/* + * return the next livedata + */ +nxpTfaLiveDataList_t *tfaContNextLiveData(nxpTfaLiveDataList_t *livedata) +{ + nxpTfaLiveDataList_t *nextlivedata = + (nxpTfaLiveDataList_t *)((char *)livedata + + (livedata->length * 4) + + sizeof(nxpTfaLiveDataList_t) - 4); + + if (nextlivedata->ID == TFA_LIVEDATAID) + return nextlivedata; + + return NULL; +} + +/* + * check CRC for container + * CRC is calculated over the bytes following the CRC field + * + * return non zero value on error + */ +int tfaContCrcCheckContainer(nxpTfaContainer_t *cont) +{ + uint8_t *base; + size_t size; + uint32_t crc; + + base = (uint8_t *)&cont->CRC + + 4; // ptr to bytes following the CRC field + size = (size_t)(cont->size - + (base - + (uint8_t *) + cont)); // nr of bytes following the CRC field + crc = ~crc32_le(~0u, base, size); + + return crc != cont->CRC; +} + +static void get_all_features_from_cnt(struct tfa_device *tfa, + int *hw_feature_register, + int sw_feature_register[2]) +{ + nxpTfaFeatures_t *features; + int i; + + nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx); + + /* Init values in case no keyword is defined in cnt file: */ + *hw_feature_register = -1; + sw_feature_register[0] = -1; + sw_feature_register[1] = -1; + + if (dev == NULL) + return; + + // process the device list + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == dscFeatures) { + features = (nxpTfaFeatures_t *)(dev->list[i].offset + + (uint8_t *)tfa->cnt); + *hw_feature_register = features->value[0]; + sw_feature_register[0] = features->value[1]; + sw_feature_register[1] = features->value[2]; + break; + } + } +} + +/* wrapper function */ +void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register) +{ + int sw_feature_register[2]; + get_all_features_from_cnt(tfa, hw_feature_register, + sw_feature_register); +} + +/* wrapper function */ +void get_sw_features_from_cnt(struct tfa_device *tfa, + int sw_feature_register[2]) +{ + int hw_feature_register; + get_all_features_from_cnt(tfa, &hw_feature_register, + sw_feature_register); +} + +enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa) +{ + return (tfa->dev_ops.factory_trimmer)(tfa); +} + +enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaProfileList_t *prof = + tfaContGetDevProfList(tfa->cnt, tfa->dev_idx, prof_idx); + unsigned int i; + + if (!prof) + return Tfa98xx_Error_Bad_Parameter; + + /* If we are in powerdown there is no need to set filters */ + if (TFA_GET_BF(tfa, PWDN) == 1) + return Tfa98xx_Error_Ok; + + /* loop the profile to find filter settings */ + for (i = 0; i < prof->length; i++) { + /* We only want to write the values before the default section */ + if (prof->list[i].type == dscDefault) + break; + + /* write all filter settings */ + if (prof->list[i].type == dscFilter) { + if (tfaContWriteItem(tfa, &prof->list[i]) != + Tfa98xx_Error_Ok) + return err; + } + } + + return err; +} + +int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length, const char *buffer) +{ + uint8_t *buf = (uint8_t *)buffer; + static uint8_t *blob = NULL, *blobptr; /* TODO: not multi-thread safe */ + static int total = 0; /* TODO: not multi-thread safe */ + int post_len = 0; + + /* checks for 24b_BE or 32_LE */ + int len_word_in_bytes = (tfa->convert_dsp32) ? 4 : 3; + /* TODO: get rid of these magic constants max size should depend on the tfa device type */ + int tfadsp_max_msg_size = (tfa->convert_dsp32) ? 5336 : 4000; + + /* No data found*/ + if (length == -1 && blob == NULL) { + return -1; + } + + if (length == -1) { + int i; + /* set last length field to zero */ + for (i = total; i < (total + len_word_in_bytes); i++) { + blob[i] = 0; + } + total += len_word_in_bytes; + memcpy(buf, blob, total); + + kfree(blob); + blob = NULL; /* Set to NULL pointer, otherwise no new malloc is done! */ + return total; + } + + if (blob == NULL) { + if (tfa->verbose) + pr_debug("%s, Creating the multi-message \n\n", + __FUNCTION__); + + blob = kmalloc(tfadsp_max_msg_size, GFP_KERNEL); + /* add command ID for multi-msg = 0x008015 */ + if (tfa->convert_dsp32) { + blob[0] = 0x15; + blob[1] = 0x80; + blob[2] = 0x0; + blob[3] = 0x0; + } else { + blob[0] = 0x0; + blob[1] = 0x80; + blob[2] = 0x15; + } + blobptr = blob; + blobptr += len_word_in_bytes; + total = len_word_in_bytes; + } + + if (tfa->verbose) { + pr_debug("%s, id:0x%02x%02x%02x, length:%d \n", __FUNCTION__, + buf[0], buf[1], buf[2], length); + } + + /* check total message size after concatination */ + post_len = total + length + (2 * len_word_in_bytes); + if (post_len > tfadsp_max_msg_size) { + //pr_debug("New multi-message too large! (%d >= %d (max.)), current length: %d\n", post_len, tfadsp_max_msg_size, total); + return Tfa98xx_Error_Buffer_too_small; + } + + /* add length field (length in words) to the multi message */ + if (tfa->convert_dsp32) { + *blobptr++ = (uint8_t)((length / len_word_in_bytes) & + 0xff); /* lsb */ + *blobptr++ = + (uint8_t)(((length / len_word_in_bytes) & 0xff00) >> + 8); /* msb */ + *blobptr++ = 0x0; + *blobptr++ = 0x0; + } else { + *blobptr++ = 0x0; + *blobptr++ = + (uint8_t)(((length / len_word_in_bytes) & 0xff00) >> + 8); /* msb */ + *blobptr++ = (uint8_t)((length / len_word_in_bytes) & + 0xff); /* lsb */ + } + memcpy(blobptr, buf, length); + blobptr += length; + total += (length + len_word_in_bytes); + + /* SetRe25 message is always the last message of the multi-msg */ + if (tfa->convert_dsp32) { + if (buf[1] == 0x81 && buf[0] == SB_PARAM_SET_RE25C) { + return 1; /* 1 means last message is done! */ + } + } else { + if (buf[1] == 0x81 && buf[2] == SB_PARAM_SET_RE25C) { + return 1; /* 1 means last message is done! */ + } + } + + return 0; +} diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c new file mode 100644 index 000000000000..b02098326cb2 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c @@ -0,0 +1,439 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dbgprint.h" +#include "tfa_service.h" +#include "tfa98xx_tfafieldnames.h" + +/* support for error code translation into text */ +static char latest_errorstr[64]; + +const char *tfa98xx_get_error_string(enum Tfa98xx_Error error) +{ + const char *pErrStr; + + switch (error) { + case Tfa98xx_Error_Ok: + pErrStr = "Ok"; + break; + case Tfa98xx_Error_DSP_not_running: + pErrStr = "DSP_not_running"; + break; + case Tfa98xx_Error_Bad_Parameter: + pErrStr = "Bad_Parameter"; + break; + case Tfa98xx_Error_NotOpen: + pErrStr = "NotOpen"; + break; + case Tfa98xx_Error_InUse: + pErrStr = "InUse"; + break; + case Tfa98xx_Error_RpcBusy: + pErrStr = "RpcBusy"; + break; + case Tfa98xx_Error_RpcModId: + pErrStr = "RpcModId"; + break; + case Tfa98xx_Error_RpcParamId: + pErrStr = "RpcParamId"; + break; + case Tfa98xx_Error_RpcInvalidCC: + pErrStr = "RpcInvalidCC"; + break; + case Tfa98xx_Error_RpcInvalidSeq: + pErrStr = "RpcInvalidSeq"; + break; + case Tfa98xx_Error_RpcInvalidParam: + pErrStr = "RpcInvalidParam"; + break; + case Tfa98xx_Error_RpcBufferOverflow: + pErrStr = "RpcBufferOverflow"; + break; + case Tfa98xx_Error_RpcCalibBusy: + pErrStr = "RpcCalibBusy"; + break; + case Tfa98xx_Error_RpcCalibFailed: + pErrStr = "RpcCalibFailed"; + break; + case Tfa98xx_Error_Not_Supported: + pErrStr = "Not_Supported"; + break; + case Tfa98xx_Error_I2C_Fatal: + pErrStr = "I2C_Fatal"; + break; + case Tfa98xx_Error_I2C_NonFatal: + pErrStr = "I2C_NonFatal"; + break; + case Tfa98xx_Error_StateTimedOut: + pErrStr = "WaitForState_TimedOut"; + break; + default: + sprintf(latest_errorstr, "Unspecified error (%d)", (int)error); + pErrStr = latest_errorstr; + } + return pErrStr; +} +/*****************************************************************************/ +/* bitfield lookups */ +/* + * generic table lookup functions + */ +/** + * lookup bf in table + * return 'unkown' if not found + */ +static char *tfa_bf2name(tfaBfName_t *table, uint16_t bf) +{ + int n = 0; + + do { + if ((table[n].bfEnum & 0xfff0) == (bf & 0xfff0)) { + return table[n].bfName; + } + } while (table[n++].bfEnum != 0xffff); + + return table[n - 1].bfName; /* last name says unkown */ +} +/** + * lookup name in table + * return 0xffff if not found + */ +static uint16_t tfa_name2bf(tfaBfName_t *table, const char *name) +{ + int n = 0; + + do { + if (strcasecmp(name, table[n].bfName) == 0) + return table[n].bfEnum; + } while (table[n++].bfEnum != 0xffff); + + return 0xffff; +} + +/* + * tfa2 bitfield name table + */ +TFA2_NAMETABLE +TFA2_BITNAMETABLE + +/* + * tfa1 bitfield name tables + */ +TFA1_NAMETABLE +TFA9896_NAMETABLE +TFA9872_NAMETABLE +TFA9874_NAMETABLE +TFA9890_NAMETABLE +TFA9891_NAMETABLE +TFA9887_NAMETABLE +TFA1_BITNAMETABLE +TFA9912_NAMETABLE +TFA9894_NAMETABLE +TFA9896_BITNAMETABLE +TFA9872_BITNAMETABLE +TFA9874_BITNAMETABLE +TFA9912_BITNAMETABLE +TFA9890_BITNAMETABLE +TFA9891_BITNAMETABLE +TFA9887_BITNAMETABLE +TFA9894_BITNAMETABLE + +char *tfaContBitName(uint16_t num, unsigned short rev) +{ + char *name; + /* end of list for the unknown string */ + int tableLength = sizeof(Tfa1DatasheetNames) / sizeof(tfaBfName_t); + const char *unknown = Tfa1DatasheetNames[tableLength - 1].bfName; + + switch (rev & 0xff) { + case 0x88: + name = tfa_bf2name(Tfa2BitNames, num); + break; + case 0x97: + name = tfa_bf2name(Tfa1BitNames, num); + break; + case 0x96: + name = tfa_bf2name(Tfa9896BitNames, num); + break; + case 0x72: + name = tfa_bf2name(Tfa9872BitNames, num); + break; + case 0x74: + name = tfa_bf2name(Tfa9874BitNames, num); + break; + case 0x92: + name = tfa_bf2name(Tfa9891BitNames, num); + break; + case 0x91: + case 0x80: + case 0x81: + name = tfa_bf2name(Tfa9890BitNames, num); /* my tabel 1st */ + if (strcmp(unknown, name) == 0) + name = tfa_bf2name(Tfa1BitNames, + num); /* try generic table */ + break; + case 0x12: + name = tfa_bf2name(Tfa9887BitNames, num); /* my tabel 1st */ + if (strcmp(unknown, name) == 0) + name = tfa_bf2name(Tfa1BitNames, + num); /* try generic table */ + break; + case 0x13: + name = tfa_bf2name(Tfa9912BitNames, num); + break; + case 0x94: + name = tfa_bf2name(Tfa9894BitNames, num); + break; + default: + PRINT_ERROR("unknown REVID:0x%0x\n", rev); + tableLength = sizeof(Tfa1BitNames) / + sizeof(tfaBfName_t); /* end of list */ + name = (char *)unknown; + break; + } + return name; +} + +char *tfaContDsName(uint16_t num, unsigned short rev) +{ + char *name; + /* end of list for the unknown string */ + int tableLength = sizeof(Tfa1DatasheetNames) / sizeof(tfaBfName_t); + const char *unknown = Tfa1DatasheetNames[tableLength - 1].bfName; + + switch (rev & 0xff) { + case 0x88: + name = tfa_bf2name(Tfa2DatasheetNames, num); + break; + case 0x97: + name = tfa_bf2name(Tfa1DatasheetNames, num); + break; + case 0x96: + name = tfa_bf2name(Tfa9896DatasheetNames, num); + break; + case 0x72: + name = tfa_bf2name(Tfa9872DatasheetNames, num); + break; + case 0x74: + name = tfa_bf2name(Tfa9874DatasheetNames, num); + break; + case 0x92: + name = tfa_bf2name(Tfa9891DatasheetNames, num); + break; + case 0x91: + case 0x80: + case 0x81: + name = tfa_bf2name(Tfa9890DatasheetNames, + num); /* my tabel 1st */ + if (strcmp(unknown, name) == 0) + name = tfa_bf2name(Tfa1DatasheetNames, + num); /* try generic table */ + break; + case 0x12: + name = tfa_bf2name(Tfa9887DatasheetNames, + num); /* my tabel 1st */ + if (strcmp(unknown, name) == 0) + name = tfa_bf2name(Tfa1DatasheetNames, + num); /* try generic table */ + break; + case 0x13: + name = tfa_bf2name(Tfa9912DatasheetNames, num); + break; + case 0x94: + name = tfa_bf2name(Tfa9894DatasheetNames, num); + break; + default: + PRINT_ERROR("unknown REVID:0x%0x\n", rev); + tableLength = sizeof(Tfa1DatasheetNames) / + sizeof(tfaBfName_t); /* end of list */ + name = (char *)unknown; + break; + } + return name; +} + +char *tfaContBfName(uint16_t num, unsigned short rev) +{ + char *name; + /* end of list for the unknown string */ + int tableLength = sizeof(Tfa1DatasheetNames) / sizeof(tfaBfName_t); + const char *unknown = Tfa1DatasheetNames[tableLength - 1].bfName; + + /* if datasheet name does not exist look for bitfieldname */ + name = tfaContDsName(num, rev); + if (strcmp(unknown, name) == 0) + name = tfaContBitName(num, rev); + + return name; +} + +uint16_t tfaContBfEnum(const char *name, unsigned short rev) +{ + uint16_t bfnum; + + switch (rev & 0xff) { + case 0x88: + bfnum = tfa_name2bf(Tfa2DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa2BitNames, + name); /* try long bitname table */ + break; + case 0x97: + bfnum = tfa_name2bf(Tfa1DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa1BitNames, + name); /* try generic table */ + break; + case 0x96: + bfnum = tfa_name2bf(Tfa9896DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa9896BitNames, + name); /* try generic table */ + break; + case 0x72: + bfnum = tfa_name2bf(Tfa9872DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa9872BitNames, + name); /* try long bitname table */ + break; + case 0x74: + bfnum = tfa_name2bf(Tfa9874DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa9874BitNames, + name); /* try long bitname table */ + break; + case 0x92: + bfnum = tfa_name2bf(Tfa9891DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa9891BitNames, + name); /* try long bitname table */ + break; + case 0x91: + case 0x80: + case 0x81: + bfnum = tfa_name2bf(Tfa9890DatasheetNames, + name); /* my tabel 1st */ + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa1DatasheetNames, + name); /* try generic table */ + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa1BitNames, + name); /* try 2nd generic table */ + break; + case 0x12: + bfnum = tfa_name2bf(Tfa9887DatasheetNames, + name); /* my tabel 1st */ + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa1DatasheetNames, + name); /* try generic table */ + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa1BitNames, + name); /* try 2nd generic table */ + break; + case 0x13: + bfnum = tfa_name2bf(Tfa9912DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa9912BitNames, + name); /* try long bitname table */ + break; + case 0x94: + bfnum = tfa_name2bf(Tfa9894DatasheetNames, name); + if (bfnum == 0xffff) + bfnum = tfa_name2bf(Tfa9894BitNames, + name); /* try long bitname table */ + break; + + default: + PRINT_ERROR("unknown REVID:0x%0x\n", rev); + bfnum = 0xffff; + break; + } + + return bfnum; +} + +/* + * check all lists for a hit + * this is for the parser to know if it's an existing bitname + */ +uint16_t tfaContBfEnumAny(const char *name) +{ + uint16_t bfnum; + + /* datasheet names first */ + bfnum = tfa_name2bf(Tfa2DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa1DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9891DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9890DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9887DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9872DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9874DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9896DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9912DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9894DatasheetNames, name); + if (bfnum != 0xffff) + return bfnum; + /* and then bitfield names */ + bfnum = tfa_name2bf(Tfa2BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa1BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9891BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9890BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9887BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9872BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9874BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9896BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9912BitNames, name); + if (bfnum != 0xffff) + return bfnum; + bfnum = tfa_name2bf(Tfa9894BitNames, name); + + return bfnum; +} diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c new file mode 100644 index 000000000000..eb4045710829 --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c @@ -0,0 +1,4165 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dbgprint.h" +#include "tfa_container.h" +#include "tfa.h" +#include "tfa98xx_tfafieldnames.h" +#include "tfa_internal.h" + +#ifdef __KERNEL__ +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "%s(): " fmt, __func__ +#endif +/* handle macro for bitfield */ +#define TFA_MK_BF(reg, pos, len) ((reg << 8) | (pos << 4) | (len - 1)) + +/* abstract family for register */ +#define FAM_TFA98XX_CF_CONTROLS (TFA_FAM(tfa, RST) >> 8) +#define FAM_TFA98XX_CF_MEM (TFA_FAM(tfa, MEMA) >> 8) +#define FAM_TFA98XX_MTP0 (TFA_FAM(tfa, MTPOTC) >> 8) +#define FAM_TFA98xx_INT_EN (TFA_FAM(tfa, INTENVDDS) >> 8) + +#define CF_STATUS_I2C_CMD_ACK 0x01 + +/* Defines below are used for irq function (this removed the genregs include) */ +#define TFA98XX_INTERRUPT_ENABLE_REG1 0x48 +#define TFA98XX_INTERRUPT_IN_REG1 0x44 +#define TFA98XX_INTERRUPT_OUT_REG1 0x40 +#define TFA98XX_STATUS_POLARITY_REG1 0x4c +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK 0x2 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK 0x1 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS 1 +#define TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_POS 0 + +void tfanone_ops(struct tfa_device_ops *ops); +void tfa9872_ops(struct tfa_device_ops *ops); +void tfa9874_ops(struct tfa_device_ops *ops); +void tfa9912_ops(struct tfa_device_ops *ops); +void tfa9888_ops(struct tfa_device_ops *ops); +void tfa9891_ops(struct tfa_device_ops *ops); +void tfa9897_ops(struct tfa_device_ops *ops); +void tfa9896_ops(struct tfa_device_ops *ops); +void tfa9890_ops(struct tfa_device_ops *ops); +void tfa9895_ops(struct tfa_device_ops *ops); +void tfa9894_ops(struct tfa_device_ops *ops); + +#ifndef MIN +#define MIN(A, B) (A < B ? A : B) +#endif + +/* retry values */ +#define CFSTABLE_TRIES 10 +#define AMPOFFWAIT_TRIES 50 +#define MTPBWAIT_TRIES 50 +#define MTPEX_WAIT_NTRIES 50 + +/* calibration done executed */ +#define TFA_MTPEX_POS TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_POS /**/ + +int tfa_get_calibration_info(struct tfa_device *tfa, int channel) +{ + return tfa->mohm[channel]; +} + +/* return sign extended tap pattern */ +int tfa_get_tap_pattern(struct tfa_device *tfa) +{ + int value = tfa_get_bf(tfa, TFA9912_BF_CFTAPPAT); + int bitshift; + uint8_t field_len = + 1 + (TFA9912_BF_CFTAPPAT & 0x0f); /* length of bitfield */ + + bitshift = 8 * sizeof(int) - field_len; + /* signextend */ + value = (value << bitshift) >> bitshift; + + return value; +} +/* + * interrupt bit function to clear + */ +int tfa_irq_clear(struct tfa_device *tfa, enum tfa9912_irq bit) +{ + unsigned char reg; + + /* make bitfield enum */ + if (bit == tfa9912_irq_all) { + /* operate on all bits */ + for (reg = TFA98XX_INTERRUPT_IN_REG1; + reg < TFA98XX_INTERRUPT_IN_REG1 + 3; reg++) + reg_write(tfa, reg, 0xffff); /* all bits */ + } else if (bit < tfa9912_irq_max) { + reg = (unsigned char)(TFA98XX_INTERRUPT_IN_REG1 + (bit >> 4)); + reg_write(tfa, reg, 1 << (bit & 0x0f)); /* only this bit */ + } else + return -1; + + return 0; +} +/* + * return state of irq or -1 if illegal bit + */ +int tfa_irq_get(struct tfa_device *tfa, enum tfa9912_irq bit) +{ + uint16_t value; + int reg, mask; + + if (bit < tfa9912_irq_max) { + /* only this bit */ + reg = TFA98XX_INTERRUPT_OUT_REG1 + (bit >> 4); + mask = 1 << (bit & 0x0f); + reg_read(tfa, (unsigned char)reg, &value); + } else + return -1; + + return (value & mask) != 0; +} +/* + * interrupt bit function that operates on the shadow regs in the handle + */ + +int tfa_irq_ena(struct tfa_device *tfa, enum tfa9912_irq bit, int state) +{ + uint16_t value, new_value; + int reg = 0, mask; + /* */ + if (bit == tfa9912_irq_all) { + /* operate on all bits */ + for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; + reg <= + TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; + reg++) { + reg_write(tfa, (unsigned char)reg, + state ? 0xffff : 0); /* all bits */ + tfa->interrupt_enable[reg - + TFA98XX_INTERRUPT_ENABLE_REG1] = + state ? 0xffff : 0; /* all bits */ + } + } else if (bit < tfa9912_irq_max) { + /* only this bit */ + reg = TFA98XX_INTERRUPT_ENABLE_REG1 + (bit >> 4); + mask = 1 << (bit & 0x0f); + reg_read(tfa, (unsigned char)reg, &value); + if (state) //set + new_value = (uint16_t)(value | mask); + else // clear + new_value = value & ~mask; + if (new_value != value) { + reg_write(tfa, (unsigned char)reg, + new_value); /* only this bit */ + tfa->interrupt_enable[reg - + TFA98XX_INTERRUPT_ENABLE_REG1] = + new_value; + } + } else + return -1; + + return 0; +} + +/* + * mask interrupts by disabling them + */ +int tfa_irq_mask(struct tfa_device *tfa) +{ + int reg; + + /* operate on all bits */ + for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; + reg <= TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++) + reg_write(tfa, (unsigned char)reg, 0); + + return 0; +} + +/* + * unmask interrupts by enabling them again + */ +int tfa_irq_unmask(struct tfa_device *tfa) +{ + int reg; + + /* operate on all bits */ + for (reg = TFA98XX_INTERRUPT_ENABLE_REG1; + reg <= TFA98XX_INTERRUPT_ENABLE_REG1 + tfa9912_irq_max / 16; reg++) + reg_write(tfa, (unsigned char)reg, + tfa->interrupt_enable[reg - + TFA98XX_INTERRUPT_ENABLE_REG1]); + + return 0; +} + +/* + * interrupt bit function that sets the polarity + */ + +int tfa_irq_set_pol(struct tfa_device *tfa, enum tfa9912_irq bit, int state) +{ + uint16_t value, new_value; + int reg = 0, mask; + + if (bit == tfa9912_irq_all) { + /* operate on all bits */ + for (reg = TFA98XX_STATUS_POLARITY_REG1; + reg <= TFA98XX_STATUS_POLARITY_REG1 + tfa9912_irq_max / 16; + reg++) { + reg_write(tfa, (unsigned char)reg, + state ? 0xffff : 0); /* all bits */ + } + } else if (bit < tfa9912_irq_max) { + /* only this bit */ + reg = TFA98XX_STATUS_POLARITY_REG1 + (bit >> 4); + mask = 1 << (bit & 0x0f); + reg_read(tfa, (unsigned char)reg, &value); + if (state) /* Active High */ + new_value = (uint16_t)(value | mask); + else /* Active Low */ + new_value = value & ~mask; + if (new_value != value) { + reg_write(tfa, (unsigned char)reg, + new_value); /* only this bit */ + } + } else + return -1; + + return 0; +} + +/* + * set device info and register device ops + */ +void tfa_set_query_info(struct tfa_device *tfa) +{ + /* invalidate device struct cached values */ + tfa->hw_feature_bits = -1; + tfa->sw_feature_bits[0] = -1; + tfa->sw_feature_bits[1] = -1; + tfa->profile = -1; + tfa->vstep = -1; + /* defaults */ + tfa->is_probus_device = 0; + tfa->tfa_family = 1; + tfa->daimap = Tfa98xx_DAI_I2S; /* all others */ + tfa->spkr_count = 1; + tfa->spkr_select = 0; + tfa->support_tcoef = supportYes; + tfa->supportDrc = supportNotSet; + tfa->support_saam = supportNotSet; + tfa->ext_dsp = + -1; /* respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */ + tfa->bus = 0; + tfa->partial_enable = 0; + tfa->convert_dsp32 = 0; + tfa->sync_iv_delay = 0; + + /* TODO use the getfeatures() for retrieving the features [artf103523] + tfa->supportDrc = supportNotSet;*/ + + switch (tfa->rev & 0xff) { + case 0: /* tfanone : non-i2c external DSP device */ + /* e.g. qc adsp */ + tfa->supportDrc = supportYes; + tfa->tfa_family = 0; + tfa->spkr_count = 0; + tfa->daimap = 0; + tfanone_ops( + &tfa->dev_ops); /* register device operations via tfa hal*/ + tfa->bus = 1; + break; + case 0x72: + /* tfa9872 */ + tfa->supportDrc = supportYes; + tfa->tfa_family = 2; + tfa->spkr_count = 1; + tfa->is_probus_device = 1; + tfa->daimap = Tfa98xx_DAI_TDM; + tfa9872_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x74: + /* tfa9874 */ + tfa->supportDrc = supportYes; + tfa->tfa_family = 2; + tfa->spkr_count = 1; + tfa->is_probus_device = 1; + tfa->daimap = Tfa98xx_DAI_TDM; + tfa9874_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x88: + /* tfa9888 */ + tfa->tfa_family = 2; + tfa->spkr_count = 2; + tfa->daimap = Tfa98xx_DAI_TDM; + tfa9888_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x97: + /* tfa9897 */ + tfa->supportDrc = supportNo; + tfa->spkr_count = 1; + tfa->daimap = Tfa98xx_DAI_TDM; + tfa9897_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x96: + /* tfa9896 */ + tfa->supportDrc = supportNo; + tfa->spkr_count = 1; + tfa->daimap = Tfa98xx_DAI_TDM; + tfa9896_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x92: + /* tfa9891 */ + tfa->spkr_count = 1; + tfa->daimap = (Tfa98xx_DAI_PDM | Tfa98xx_DAI_I2S); + tfa9891_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x91: + /* tfa9890B */ + tfa->spkr_count = 1; + tfa->daimap = (Tfa98xx_DAI_PDM | Tfa98xx_DAI_I2S); + break; + case 0x80: + case 0x81: + /* tfa9890 */ + tfa->spkr_count = 1; + tfa->daimap = Tfa98xx_DAI_I2S; + tfa->supportDrc = supportNo; + tfa->supportFramework = supportNo; + tfa9890_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x12: + /* tfa9895 */ + tfa->spkr_count = 1; + tfa->daimap = Tfa98xx_DAI_I2S; + tfa9895_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x13: + /* tfa9912 */ + tfa->tfa_family = 2; + tfa->spkr_count = 1; + tfa->daimap = Tfa98xx_DAI_TDM; + tfa9912_ops(&tfa->dev_ops); /* register device operations */ + break; + case 0x94: + /* tfa9894 */ + tfa->tfa_family = 2; + tfa->spkr_count = 1; + tfa->daimap = Tfa98xx_DAI_TDM; + tfa9894_ops(&tfa->dev_ops); /* register device operations */ + break; + + default: + pr_err("unknown device type : 0x%02x\n", tfa->rev); + _ASSERT(0); + break; + } +} + +/* + * lookup the device type and return the family type + */ +int tfa98xx_dev2family(int dev_type) +{ + /* only look at the die ID part (lsb byte) */ + switch (dev_type & 0xff) { + case 0x12: + case 0x80: + case 0x81: + case 0x91: + case 0x92: + case 0x97: + case 0x96: + return 1; + case 0x88: + case 0x72: + case 0x13: + case 0x74: + case 0x94: + return 2; + case 0x50: + return 3; + default: + return 0; + } +} + +/* + * return the target address for the filter on this device + + filter_index: + [0..9] reserved for EQ (not deployed, calc. is available) + [10..12] anti-alias filter + [13] integrator filter + + */ +enum Tfa98xx_DMEM tfa98xx_filter_mem(struct tfa_device *tfa, int filter_index, + unsigned short *address, int channel) +{ + enum Tfa98xx_DMEM dmem = -1; + int idx; + unsigned short bq_table[7][4] = { + /* index: 10, 11, 12, 13 */ + { 346, 351, 356, 288 }, //87 BRA_MAX_MRA4-2_7.00 + { 346, 351, 356, 288 }, //90 BRA_MAX_MRA6_9.02 + { 467, 472, 477, 409 }, //95 BRA_MAX_MRA7_10.02 + { 406, 411, 416, 348 }, //97 BRA_MAX_MRA9_12.01 + { 467, 472, 477, 409 }, //91 BRA_MAX_MRAA_13.02 + { 8832, 8837, 8842, 8847 }, //88 part1 + { 8853, 8858, 8863, 8868 } //88 part2 + /* Since the 88 is stereo we have 2 parts. + * Every index has 5 values except index 13 this one has 6 values + */ + }; + + if ((10 <= filter_index) && (filter_index <= 13)) { + dmem = Tfa98xx_DMEM_YMEM; /* for all devices */ + idx = filter_index - 10; + + switch (tfa->rev & 0xff) { // only compare lower byte + case 0x12: + *address = bq_table[2][idx]; + break; + case 0x97: + *address = bq_table[3][idx]; + break; + case 0x96: + *address = bq_table[3][idx]; + break; + case 0x80: + case 0x81: // for the RAM version + case 0x91: + *address = bq_table[1][idx]; + break; + case 0x92: + *address = bq_table[4][idx]; + break; + case 0x88: + /* Channel 1 = primary, 2 = secondary */ + if (channel == 1) + *address = bq_table[5][idx]; + else + *address = bq_table[6][idx]; + break; + case 0x72: + case 0x74: + case 0x13: + default: + /* unsupported case, possibly intermediate version */ + return -1; + _ASSERT(0); + } + } + return dmem; +} + +/************************ query functions ********************************************************/ +/** +* return revision +* Used by the LTT +*/ +void tfa98xx_rev(int *major, int *minor, int *revision) +{ + char version_str[] = TFA98XX_API_REV_STR; + sscanf(version_str, "v%d.%d.%d", major, minor, revision); +} + +/** + * tfa_supported_speakers + * returns the number of the supported speaker count + */ +enum Tfa98xx_Error tfa_supported_speakers(struct tfa_device *tfa, + int *spkr_count) +{ + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + else + *spkr_count = tfa->spkr_count; + + return Tfa98xx_Error_Ok; +} + +/* + * tfa98xx_supported_saam + * returns the supportedspeaker as microphone feature + */ +enum Tfa98xx_Error tfa98xx_supported_saam(struct tfa_device *tfa, + enum Tfa98xx_saam *saam) +{ + int features; + enum Tfa98xx_Error error; + + if (tfa->support_saam == supportNotSet) { + error = tfa98xx_dsp_get_hw_feature_bits(tfa, &features); + if (error != Tfa98xx_Error_Ok) + return error; + tfa->support_saam = (features & 0x8000) ? + supportYes : + supportNo; /* SAAM is bit15 */ + } + *saam = tfa->support_saam == supportYes ? Tfa98xx_saam : + Tfa98xx_saam_none; + + return Tfa98xx_Error_Ok; +} + +/* + * tfa98xx_compare_features + * Obtains features_from_MTP and features_from_cnt + */ +enum Tfa98xx_Error tfa98xx_compare_features(struct tfa_device *tfa, + int features_from_MTP[3], + int features_from_cnt[3]) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + uint32_t value; + uint16_t mtpbf; + unsigned char bytes[3 * 2]; + int status; + + tfa98xx_dsp_system_stable(tfa, &status); + if (!status) + return Tfa98xx_Error_NoClock; // Only test when we have a clock. + + /* Set proper MTP location per device: */ + if (tfa->tfa_family == 1) { + mtpbf = 0x850f; /* MTP5 for tfa1,16 bits */ + } else { + mtpbf = 0xf907; /* MTP9 for tfa2, 8 bits */ + } + + /* Read HW features from MTP: */ + value = tfa_read_reg(tfa, mtpbf) & 0xffff; + features_from_MTP[0] = tfa->hw_feature_bits = value; + + /* Read SW features: */ + error = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK, + FW_PAR_ID_GET_FEATURE_INFO, + sizeof(bytes), bytes); + if (error != Tfa98xx_Error_Ok) + return error; /* old ROM code may respond with Tfa98xx_Error_RpcParamId */ + + tfa98xx_convert_bytes2data(sizeof(bytes), bytes, &features_from_MTP[1]); + + /* check if feature bits from MTP match feature bits from cnt file: */ + get_hw_features_from_cnt(tfa, &features_from_cnt[0]); + get_sw_features_from_cnt(tfa, &features_from_cnt[1]); + + return error; +} + +/********************************* device specific ops ************************************************/ +/* the wrapper for DspReset, in case of full */ +enum Tfa98xx_Error tfa98xx_dsp_reset(struct tfa_device *tfa, int state) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + error = (tfa->dev_ops.dsp_reset)(tfa, state); + + return error; +} + +/* the ops wrapper for tfa98xx_dsp_SystemStable */ +enum Tfa98xx_Error tfa98xx_dsp_system_stable(struct tfa_device *tfa, int *ready) +{ + enum Tfa98xx_Error error = (tfa->dev_ops.dsp_system_stable)(tfa, ready); + pr_debug("%s error=%d ready=%d\n", __func__, error, *ready); + return error; +} + +/* the ops wrapper for tfa98xx_dsp_system_stable */ +enum Tfa98xx_Error tfa98xx_auto_copy_mtp_to_iic(struct tfa_device *tfa) +{ + return (tfa->dev_ops.auto_copy_mtp_to_iic)(tfa); +} + +/* the ops wrapper for tfa98xx_faim_protect */ +enum Tfa98xx_Error tfa98xx_faim_protect(struct tfa_device *tfa, int state) +{ + return (tfa->dev_ops.faim_protect)(tfa, state); +} + +/* + * bring the device into a state similar to reset + */ +enum Tfa98xx_Error tfa98xx_init(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + uint16_t value = 0; + + /* reset all i2C registers to default + * Write the register directly to avoid the read in the bitfield function. + * The I2CR bit may overwrite the full register because it is reset anyway. + * This will save a reg read transaction. + */ + TFA_SET_BF_VALUE(tfa, I2CR, 1, &value); + TFA_WRITE_REG(tfa, I2CR, value); + + /* Put DSP in reset */ + tfa98xx_dsp_reset(tfa, 1); /* in pair of tfaRunStartDSP() */ + + /* some other registers must be set for optimal amplifier behaviour + * This is implemented in a file specific for the type number + */ + if (tfa->dev_ops.tfa_init) + error = (tfa->dev_ops.tfa_init)(tfa); + + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_write_tables(struct tfa_device *tfa, + int sample_rate) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + error = (tfa->dev_ops.dsp_write_tables)(tfa, sample_rate); + + return error; +} + +/** Set internal oscillator into power down mode. +* +* @param[in] tfa device description structure +* @param[in] state new state 0 - oscillator is on, 1 oscillator is off. +* +* @return Tfa98xx_Error_Ok when successfull, error otherwise. +*/ +enum Tfa98xx_Error tfa98xx_set_osc_powerdown(struct tfa_device *tfa, int state) +{ + if (tfa->dev_ops.set_osc_powerdown) { + return tfa->dev_ops.set_osc_powerdown(tfa, state); + } + + return Tfa98xx_Error_Not_Implemented; +} + +/** Check presence of powerswitch=1 in configuration and optimal setting. +* +* @param[in] tfa device description structure +* +* @return -1 when error, 0 or 1 depends on switch settings. +*/ +int tfa98xx_powerswitch_is_enabled(struct tfa_device *tfa) +{ + uint16_t value; + enum Tfa98xx_Error ret; + + if (((tfa->rev & 0xff) == 0x13) || ((tfa->rev & 0xff) == 0x88)) { + ret = reg_read(tfa, 0xc6, &value); + if (ret != Tfa98xx_Error_Ok) { + return -1; + } + /* PLMA5539: Check actual value of powerswitch. TODO: regmap v1.40 should make this bit public. */ + + return (int)(value & (1u << 6)); + } + + return 1; +} + +/********************* new tfa2 *********************************************************************/ +/* newly added messaging for tfa2 tfa1? */ +enum Tfa98xx_Error tfa98xx_dsp_get_memory(struct tfa_device *tfa, + int memoryType, int offset, + int length, unsigned char bytes[]) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + char msg[4 * 3]; + int nr = 0; + + msg[nr++] = 8; + msg[nr++] = MODULE_FRAMEWORK + 128; + msg[nr++] = FW_PAR_ID_GET_MEMORY; + + msg[nr++] = 0; + msg[nr++] = 0; + msg[nr++] = (char)memoryType; + + msg[nr++] = 0; + msg[nr++] = (offset >> 8) & 0xff; + msg[nr++] = offset & 0xff; + + msg[nr++] = 0; + msg[nr++] = (length >> 8) & 0xff; + msg[nr++] = length & 0xff; + + /* send msg */ + error = dsp_msg(tfa, nr, (char *)msg); + + if (error != Tfa98xx_Error_Ok) + return error; + + /* read the data from the device (length * 3) */ + error = dsp_msg_read(tfa, length * 3, bytes); + + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_set_memory(struct tfa_device *tfa, + int memoryType, int offset, + int length, int value) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int nr = 0; + char msg[5 * 3]; + + msg[nr++] = 8; + msg[nr++] = MODULE_FRAMEWORK + 128; + msg[nr++] = FW_PAR_ID_SET_MEMORY; + + msg[nr++] = 0; + msg[nr++] = 0; + msg[nr++] = (char)memoryType; + + msg[nr++] = 0; + msg[nr++] = (offset >> 8) & 0xff; + msg[nr++] = offset & 0xff; + + msg[nr++] = 0; + msg[nr++] = (length >> 8) & 0xff; + msg[nr++] = length & 0xff; + + msg[nr++] = (value >> 16) & 0xff; + msg[nr++] = (value >> 8) & 0xff; + msg[nr++] = value & 0xff; + + /* send msg */ + error = dsp_msg(tfa, nr, (char *)msg); + + return error; +} +/****************************** calibration support **************************/ +/* + * get/set the mtp with user controllable values + * + * check if the relevant clocks are available + */ +enum Tfa98xx_Error tfa98xx_get_mtp(struct tfa_device *tfa, uint16_t *value) +{ + int status; + int result; + + /* not possible if PLL in powerdown */ + if (TFA_GET_BF(tfa, PWDN)) { + pr_debug("PLL in powerdown\n"); + return Tfa98xx_Error_NoClock; + } + + tfa98xx_dsp_system_stable(tfa, &status); + if (status == 0) { + pr_debug("PLL not running\n"); + return Tfa98xx_Error_NoClock; + } + + result = TFA_READ_REG(tfa, MTP0); + if (result < 0) { + return -result; + } + *value = (uint16_t)result; + + return Tfa98xx_Error_Ok; +} + +/* + * lock or unlock KEY2 + * lock = 1 will lock + * lock = 0 will unlock + * + * note that on return all the hidden key will be off + */ +void tfa98xx_key2(struct tfa_device *tfa, int lock) +{ + /* unhide lock registers */ + reg_write(tfa, (tfa->tfa_family == 1) ? 0x40 : 0x0F, 0x5A6B); + /* lock/unlock key2 MTPK */ + TFA_WRITE_REG(tfa, MTPKEY2, lock ? 0 : 0x5A); + /* unhide lock registers */ + reg_write(tfa, (tfa->tfa_family == 1) ? 0x40 : 0x0F, 0); +} + +enum Tfa98xx_Error tfa98xx_set_mtp(struct tfa_device *tfa, uint16_t value, + uint16_t mask) +{ + unsigned short mtp_old, mtp_new; + int loop, status; + enum Tfa98xx_Error error; + + error = tfa98xx_get_mtp(tfa, &mtp_old); + + if (error != Tfa98xx_Error_Ok) + return error; + + mtp_new = (value & mask) | (mtp_old & ~mask); + + if (mtp_old == mtp_new) /* no change */ { + if (tfa->verbose) + pr_info("No change in MTP. Value not written! \n"); + return Tfa98xx_Error_Ok; + } + + /* Assure FAIM is enabled (enable it when neccesery) */ + error = tfa98xx_faim_protect(tfa, 1); + if (error) { + return error; + } + if (tfa->verbose) { + pr_debug("MTP clock enabled.\n"); + } + + /* assure that the clock is up, else we can't write MTP */ + error = tfa98xx_dsp_system_stable(tfa, &status); + if (error) { + return error; + } + if (status == 0) { + return Tfa98xx_Error_NoClock; + } + + tfa98xx_key2(tfa, 0); /* unlock */ + TFA_WRITE_REG(tfa, MTP0, mtp_new); /* write to i2c shadow reg */ + /* CIMTP=1 start copying all the data from i2c regs_mtp to mtp*/ + TFA_SET_BF(tfa, CIMTP, 1); + /* no check for MTPBUSY here, i2c delay assumed to be enough */ + tfa98xx_key2(tfa, 1); /* lock */ + + /* wait until MTP write is done */ + error = Tfa98xx_Error_StateTimedOut; + for (loop = 0; loop < 100 /*x10ms*/; loop++) { + msleep_interruptible(10); /* wait 10ms to avoid busload */ + if (tfa_dev_get_mtpb(tfa) == 0) { + error = Tfa98xx_Error_Ok; + break; + } + } + /* MTP setting failed due to timeout ?*/ + if (error) { + return error; + } + + /* Disable the FAIM, if this is neccessary */ + error = tfa98xx_faim_protect(tfa, 0); + if (error) { + return error; + } + if (tfa->verbose) { + pr_debug("MTP clock disabled.\n"); + } + + return error; +} +/* + * clear mtpex + * set ACS + * start tfa + */ +int tfa_calibrate(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error; + + /* clear mtpex */ + error = tfa98xx_set_mtp(tfa, 0, TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK); + if (error) + return error; + + /* set RST=1 to put the DSP in Reset */ + TFA_SET_BF(tfa, RST, 1); + + /* set ACS/coldboot state */ + error = tfaRunColdboot(tfa, 1); + + /* start tfa by playing */ + return error; +} + +static short twos(short x) +{ + return (x < 0) ? x + 512 : x; +} + +void tfa98xx_set_exttemp(struct tfa_device *tfa, short ext_temp) +{ + if ((-256 <= ext_temp) && (ext_temp <= 255)) { + /* make twos complement */ + pr_debug("Using ext temp %d C\n", twos(ext_temp)); + TFA_SET_BF(tfa, TROS, 1); + TFA_SET_BF(tfa, EXTTS, twos(ext_temp)); + } else { + pr_debug("Clearing ext temp settings\n"); + TFA_SET_BF(tfa, TROS, 0); + } +} +short tfa98xx_get_exttemp(struct tfa_device *tfa) +{ + short ext_temp = (short)TFA_GET_BF(tfa, EXTTS); + return (twos(ext_temp)); +} + +/************************** tfa simple bitfield interfacing ***************************************/ +/* convenience functions */ +enum Tfa98xx_Error tfa98xx_set_volume_level(struct tfa_device *tfa, + unsigned short vol) +{ + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + if (vol > 255) /* restricted to 8 bits */ + vol = 255; + + /* 0x00 -> 0.0 dB + * 0x01 -> -0.5 dB + * ... + * 0xFE -> -127dB + * 0xFF -> muted + */ + + /* volume value is in the top 8 bits of the register */ + return -TFA_SET_BF(tfa, VOL, (uint16_t)vol); +} + +static enum Tfa98xx_Error tfa98xx_set_mute_tfa2(struct tfa_device *tfa, + enum Tfa98xx_Mute mute) +{ + enum Tfa98xx_Error error; + + if (tfa->dev_ops.set_mute == NULL) + return Tfa98xx_Error_Not_Supported; + + switch (mute) { + case Tfa98xx_Mute_Off: + error = tfa->dev_ops.set_mute(tfa, 0); + TFA_SET_BF(tfa, AMPE, 1); + break; + case Tfa98xx_Mute_Amplifier: + case Tfa98xx_Mute_Digital: + error = tfa->dev_ops.set_mute(tfa, 1); + TFA_SET_BF(tfa, AMPE, 0); + break; + default: + return Tfa98xx_Error_Bad_Parameter; + } + + return error; +} + +static enum Tfa98xx_Error tfa98xx_set_mute_tfa1(struct tfa_device *tfa, + enum Tfa98xx_Mute mute) +{ + enum Tfa98xx_Error error; + unsigned short audioctrl_value; + unsigned short sysctrl_value; + int value; + + value = TFA_READ_REG(tfa, CFSM); /* audio control register */ + if (value < 0) + return -value; + audioctrl_value = (unsigned short)value; + value = TFA_READ_REG(tfa, AMPE); /* system control register */ + if (value < 0) + return -value; + sysctrl_value = (unsigned short)value; + + switch (mute) { + case Tfa98xx_Mute_Off: + /* previous state can be digital or amplifier mute, + * clear the cf_mute and set the enbl_amplifier bits + * + * To reduce PLOP at power on it is needed to switch the + * amplifier on with the DCDC in follower mode + * (enbl_boost = 0 ?). + * This workaround is also needed when toggling the + * powerdown bit! + */ + TFA_SET_BF_VALUE(tfa, CFSM, 0, &audioctrl_value); + TFA_SET_BF_VALUE(tfa, AMPE, 1, &sysctrl_value); + TFA_SET_BF_VALUE(tfa, DCA, 1, &sysctrl_value); + break; + case Tfa98xx_Mute_Digital: + /* expect the amplifier to run */ + /* set the cf_mute bit */ + TFA_SET_BF_VALUE(tfa, CFSM, 1, &audioctrl_value); + /* set the enbl_amplifier bit */ + TFA_SET_BF_VALUE(tfa, AMPE, 1, &sysctrl_value); + /* clear active mode */ + TFA_SET_BF_VALUE(tfa, DCA, 0, &sysctrl_value); + break; + case Tfa98xx_Mute_Amplifier: + /* clear the cf_mute bit */ + TFA_SET_BF_VALUE(tfa, CFSM, 0, &audioctrl_value); + /* clear the enbl_amplifier bit and active mode */ + TFA_SET_BF_VALUE(tfa, AMPE, 0, &sysctrl_value); + TFA_SET_BF_VALUE(tfa, DCA, 0, &sysctrl_value); + break; + default: + return Tfa98xx_Error_Bad_Parameter; + } + + error = -TFA_WRITE_REG(tfa, CFSM, audioctrl_value); + if (error) + return error; + error = -TFA_WRITE_REG(tfa, AMPE, sysctrl_value); + return error; +} + +enum Tfa98xx_Error tfa98xx_set_mute(struct tfa_device *tfa, + enum Tfa98xx_Mute mute) +{ + if (tfa->in_use == 0) { + pr_err("device is not opened \n"); + return Tfa98xx_Error_NotOpen; + } + + if (tfa->tfa_family == 1) + return tfa98xx_set_mute_tfa1(tfa, mute); + else + return tfa98xx_set_mute_tfa2(tfa, mute); +} + +/****************** patching **********************************************************/ +static enum Tfa98xx_Error tfa98xx_process_patch_file(struct tfa_device *tfa, + int length, + const unsigned char *bytes) +{ + unsigned short size; + int index = 0; + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + while (index < length) { + size = bytes[index] + bytes[index + 1] * 256; + index += 2; + if ((index + size) > length) { + /* outside the buffer, error in the input data */ + return Tfa98xx_Error_Bad_Parameter; + } + + if (size > tfa->buffer_size) { + /* too big, must fit buffer */ + return Tfa98xx_Error_Bad_Parameter; + } + + error = tfa98xx_write_raw(tfa, size, &bytes[index]); + if (error != Tfa98xx_Error_Ok) + break; + index += size; + } + return error; +} + +/* the patch contains a header with the following + * IC revision register: 1 byte, 0xFF means don't care + * XMEM address to check: 2 bytes, big endian, 0xFFFF means don't care + * XMEM value to expect: 3 bytes, big endian + */ +static enum Tfa98xx_Error +tfa98xx_check_ic_rom_version(struct tfa_device *tfa, + const unsigned char patchheader[]) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short checkrev, revid; + unsigned char lsb_revid; + unsigned short checkaddress; + int checkvalue; + int value = 0; + int status; + checkrev = patchheader[0]; + lsb_revid = tfa->rev & 0xff; /* only compare lower byte */ + + if ((checkrev != 0xFF) && (checkrev != lsb_revid)) + return Tfa98xx_Error_Not_Supported; + + checkaddress = (patchheader[1] << 8) + patchheader[2]; + checkvalue = + (patchheader[3] << 16) + (patchheader[4] << 8) + patchheader[5]; + if (checkaddress != 0xFFFF) { + /* before reading XMEM, check if we can access the DSP */ + error = tfa98xx_dsp_system_stable(tfa, &status); + if (error == Tfa98xx_Error_Ok) { + if (!status) { + /* DSP subsys not running */ + error = Tfa98xx_Error_DSP_not_running; + } + } + /* read register to check the correct ROM version */ + if (error == Tfa98xx_Error_Ok) { + error = mem_read(tfa, checkaddress, 1, &value); + } + if (error == Tfa98xx_Error_Ok) { + if (value != checkvalue) { + pr_err("patch file romid type check failed [0x%04x]: expected 0x%02x, actual 0x%02x\n", + checkaddress, value, checkvalue); + error = Tfa98xx_Error_Not_Supported; + } + } + } else { /* == 0xffff */ + /* check if the revid subtype is in there */ + if (checkvalue != 0xFFFFFF && checkvalue != 0) { + revid = patchheader[5] << 8 | + patchheader[0]; /* full revid */ + if (revid != tfa->rev) { + pr_err("patch file device type check failed: expected 0x%02x, actual 0x%02x\n", + tfa->rev, revid); + return Tfa98xx_Error_Not_Supported; + } + } + } + + return error; +} + +#define PATCH_HEADER_LENGTH 6 +enum Tfa98xx_Error tfa_dsp_patch(struct tfa_device *tfa, int patchLength, + const unsigned char *patchBytes) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int status; + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + if (patchLength < PATCH_HEADER_LENGTH) + return Tfa98xx_Error_Bad_Parameter; + + error = tfa98xx_check_ic_rom_version(tfa, patchBytes); + if (Tfa98xx_Error_Ok != error) { + return error; + } + + /* for non-dsp solution, we don't need to check ACS. */ + if (tfa->is_probus_device == 0) { + tfa98xx_dsp_system_stable(tfa, &status); + if (!status) + return Tfa98xx_Error_NoClock; + + /******MCH_TO_TEST**************/ + if (error == Tfa98xx_Error_Ok) { + pr_info("tfa cold boot patch\n"); + error = tfaRunColdboot(tfa, 1); + if (error) { + pr_err("tfa_dsp_patch DSP_not_running\n"); + return Tfa98xx_Error_DSP_not_running; + } + } + /**************************/ + } + error = tfa98xx_process_patch_file(tfa, + patchLength - PATCH_HEADER_LENGTH, + patchBytes + PATCH_HEADER_LENGTH); + + return error; +} + +/****************** end patching **********************************************************/ + +TFA_INTERNAL enum Tfa98xx_Error tfa98xx_wait_result(struct tfa_device *tfa, + int wait_retry_count) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int cf_status; /* the contents of the CF_STATUS register */ + int tries = 0; + do { + cf_status = TFA_GET_BF(tfa, ACK); + if (cf_status < 0) + error = -cf_status; + tries++; + } + // i2c_cmd_ack + /* don't wait forever, DSP is pretty quick to respond (< 1ms) */ + while ((error == Tfa98xx_Error_Ok) && + ((cf_status & CF_STATUS_I2C_CMD_ACK) == 0) && + (tries < wait_retry_count)); + if (tries >= wait_retry_count) { + /* something wrong with communication with DSP */ + error = Tfa98xx_Error_DSP_not_running; + } + return error; +} + +/* + * * support functions for data conversion + */ +/** + convert memory bytes to signed 24 bit integers + input: bytes contains "num_bytes" byte elements + output: data contains "num_bytes/3" int24 elements +*/ +void tfa98xx_convert_bytes2data(int num_bytes, const unsigned char bytes[], + int data[]) +{ + int i; /* index for data */ + int k; /* index for bytes */ + int d; + int num_data = num_bytes / 3; + _ASSERT((num_bytes % 3) == 0); + for (i = 0, k = 0; i < num_data; ++i, k += 3) { + d = (bytes[k] << 16) | (bytes[k + 1] << 8) | (bytes[k + 2]); + _ASSERT(d >= 0); + _ASSERT(d < (1 << 24)); /* max 24 bits in use */ + if (bytes[k] & 0x80) /* sign bit was set */ + d = -((1 << 24) - d); + + data[i] = d; + } +} + +/** + convert signed 32 bit integers to 24 bit aligned bytes + input: data contains "num_data" int elements + output: bytes contains "3 * num_data" byte elements +*/ +void tfa98xx_convert_data2bytes(int num_data, const int data[], + unsigned char bytes[]) +{ + int i; /* index for data */ + int k; /* index for bytes */ + int d; + /* note: cannot just take the lowest 3 bytes from the 32 bit + * integer, because also need to take care of clipping any + * value > 2&23 */ + for (i = 0, k = 0; i < num_data; ++i, k += 3) { + if (data[i] >= 0) + d = MIN(data[i], (1 << 23) - 1); + else { + /* 2's complement */ + d = (1 << 24) - MIN(-data[i], 1 << 23); + } + _ASSERT(d >= 0); + _ASSERT(d < (1 << 24)); /* max 24 bits in use */ + bytes[k] = (d >> 16) & 0xFF; /* MSB */ + bytes[k + 1] = (d >> 8) & 0xFF; + bytes[k + 2] = (d) & 0xFF; /* LSB */ + } +} + +/* + * DSP RPC message support functions + * depending on framework to be up and running + * need base i2c of memaccess (tfa1=0x70/tfa2=0x90) + */ + +/* write dsp messages in function tfa_dsp_msg() */ +/* note the 'old' write_parameter() was more efficient because all i2c was in one burst transaction */ + +//TODO properly handle bitfields: state should be restored! (now it will change eg dmesg field to xmem) +enum Tfa98xx_Error tfa_dsp_msg_write(struct tfa_device *tfa, int length, + const char *buffer) +{ + int offset = 0; + int chunk_size = ROUND_DOWN(tfa->buffer_size, 3); /* XMEM word size */ + int remaining_bytes = length; + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + uint16_t cfctl; + int value; + + value = TFA_READ_REG(tfa, DMEM); + if (value < 0) { + error = -value; + return error; + } + cfctl = (uint16_t)value; + /* assume no I2C errors from here */ + + TFA_SET_BF_VALUE(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM, + &cfctl); /* set cf ctl to DMEM */ + TFA_SET_BF_VALUE(tfa, AIF, 0, &cfctl); /* set to autoincrement */ + TFA_WRITE_REG(tfa, DMEM, cfctl); + + /* xmem[1] is start of message + * direct write to register to save cycles avoiding read-modify-write + */ + TFA_WRITE_REG(tfa, MADD, 1); + + /* due to autoincrement in cf_ctrl, next write will happen at + * the next address */ + while ((error == Tfa98xx_Error_Ok) && (remaining_bytes > 0)) { + if (remaining_bytes < chunk_size) + chunk_size = remaining_bytes; + /* else chunk_size remains at initialize value above */ + error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, chunk_size, + (const unsigned char *)buffer + + offset); + remaining_bytes -= chunk_size; + offset += chunk_size; + } + + /* notify the DSP */ + if (error == Tfa98xx_Error_Ok) { + /* cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */ + /* set the cf_req1 and cf_int bit */ + TFA_SET_BF_VALUE(tfa, REQCMD, 0x01, &cfctl); /* bit 0 */ + TFA_SET_BF_VALUE(tfa, CFINT, 1, &cfctl); + error = -TFA_WRITE_REG(tfa, CFINT, cfctl); + } + + return error; +} + +enum Tfa98xx_Error tfa_dsp_msg_write_id(struct tfa_device *tfa, int length, + const char *buffer, uint8_t cmdid[3]) +{ + int offset = 0; + int chunk_size = ROUND_DOWN(tfa->buffer_size, 3); /* XMEM word size */ + int remaining_bytes = length; + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + uint16_t cfctl; + int value; + + value = TFA_READ_REG(tfa, DMEM); + if (value < 0) { + error = -value; + return error; + } + cfctl = (uint16_t)value; + /* assume no I2C errors from here */ + + TFA_SET_BF_VALUE(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM, + &cfctl); /* set cf ctl to DMEM */ + TFA_SET_BF_VALUE(tfa, AIF, 0, &cfctl); /* set to autoincrement */ + TFA_WRITE_REG(tfa, DMEM, cfctl); + + /* xmem[1] is start of message + * direct write to register to save cycles avoiding read-modify-write + */ + TFA_WRITE_REG(tfa, MADD, 1); + + /* write cmd-id */ + error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, 3, + (const unsigned char *)cmdid); + + /* due to autoincrement in cf_ctrl, next write will happen at + * the next address */ + while ((error == Tfa98xx_Error_Ok) && (remaining_bytes > 0)) { + if (remaining_bytes < chunk_size) + chunk_size = remaining_bytes; + /* else chunk_size remains at initialize value above */ + error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, chunk_size, + (const unsigned char *)buffer + + offset); + remaining_bytes -= chunk_size; + offset += chunk_size; + } + + /* notify the DSP */ + if (error == Tfa98xx_Error_Ok) { + /* cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */ + /* set the cf_req1 and cf_int bit */ + TFA_SET_BF_VALUE(tfa, REQCMD, 0x01, &cfctl); /* bit 0 */ + TFA_SET_BF_VALUE(tfa, CFINT, 1, &cfctl); + error = -TFA_WRITE_REG(tfa, CFINT, cfctl); + } + + return error; +} + +/* +* status function used by tfa_dsp_msg() to retrieve command/msg status: +* return a <0 status of the DSP did not ACK. +*/ +enum Tfa98xx_Error tfa_dsp_msg_status(struct tfa_device *tfa, int *pRpcStatus) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + error = tfa98xx_wait_result(tfa, 2); /* 2 is only one try */ + if (error == Tfa98xx_Error_DSP_not_running) { + *pRpcStatus = -1; + return Tfa98xx_Error_Ok; + } else if (error != Tfa98xx_Error_Ok) + return error; + + error = tfa98xx_check_rpc_status(tfa, pRpcStatus); + + return error; +} + +const char *tfa98xx_get_i2c_status_id_string(int status) +{ + const char *p_id_str; + + switch (status) { + case Tfa98xx_DSP_Not_Running: + p_id_str = "No response from DSP"; + break; + case Tfa98xx_I2C_Req_Done: + p_id_str = "Ok"; + break; + case Tfa98xx_I2C_Req_Busy: + p_id_str = "Request is being processed"; + break; + case Tfa98xx_I2C_Req_Invalid_M_ID: + p_id_str = "Provided M-ID does not fit in valid rang [0..2]"; + break; + case Tfa98xx_I2C_Req_Invalid_P_ID: + p_id_str = + "Provided P-ID is not valid in the given M-ID context"; + break; + case Tfa98xx_I2C_Req_Invalid_CC: + p_id_str = + "Invalid channel configuration bits (SC|DS|DP|DC) combination"; + break; + case Tfa98xx_I2C_Req_Invalid_Seq: + p_id_str = + "Invalid sequence of commands, in case the DSP expects some commands in a specific order"; + break; + case Tfa98xx_I2C_Req_Invalid_Param: + p_id_str = "Generic error, invalid parameter"; + break; + case Tfa98xx_I2C_Req_Buffer_Overflow: + p_id_str = + "I2C buffer has overflowed: host has sent too many parameters, memory integrity is not guaranteed"; + break; + case Tfa98xx_I2C_Req_Calib_Busy: + p_id_str = "Calibration not completed"; + break; + case Tfa98xx_I2C_Req_Calib_Failed: + p_id_str = "Calibration failed"; + break; + + default: + p_id_str = "Unspecified error"; + } + + return p_id_str; +} + +enum Tfa98xx_Error tfa_dsp_msg_read(struct tfa_device *tfa, int length, + unsigned char *bytes) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int burst_size; /* number of words per burst size */ + int bytes_per_word = 3; + int num_bytes; + int offset = 0; + unsigned short start_offset = 2; /* msg starts @xmem[2] ,[1]=cmd */ + + if (length > TFA2_MAX_PARAM_SIZE) + return Tfa98xx_Error_Bad_Parameter; + + TFA_SET_BF(tfa, DMEM, (uint16_t)Tfa98xx_DMEM_XMEM); + error = -TFA_WRITE_REG(tfa, MADD, start_offset); + if (error != Tfa98xx_Error_Ok) + return error; + + num_bytes = length; /* input param */ + while (num_bytes > 0) { + burst_size = ROUND_DOWN(tfa->buffer_size, bytes_per_word); + if (num_bytes < burst_size) + burst_size = num_bytes; + error = tfa98xx_read_data(tfa, FAM_TFA98XX_CF_MEM, burst_size, + bytes + offset); + if (error != Tfa98xx_Error_Ok) + return error; + + num_bytes -= burst_size; + offset += burst_size; + } + + return error; +} + +enum Tfa98xx_Error dsp_msg(struct tfa_device *tfa, int length24, + const char *buf24) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int lastmessage = 0; + uint8_t *blob; + int i; + int *intbuf = NULL; + char *buf = (char *)buf24; + int length = length24; + + if (tfa->convert_dsp32) { + int idx = 0; + + length = 4 * length24 / 3; + intbuf = kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + buf = (char *)intbuf; + + /* convert 24 bit DSP messages to a 32 bit integer */ + for (i = 0; i < length24; i += 3) { + int tmp = (buf24[i] << 16) + (buf24[i + 1] << 8) + + buf24[i + 2]; + /* Sign extend to 32-bit from 24-bit */ + intbuf[idx++] = ((int32_t)tmp << 8) >> 8; + } + } + + /* Only create multi-msg when the dsp is cold */ + if (tfa->ext_dsp == 1) { + /* Creating the multi-msg */ + error = tfa_tib_dsp_msgmulti(tfa, length, buf); + if (error == Tfa98xx_Error_Fail) + return Tfa98xx_Error_Fail; + + /* if the buffer is full we need to send the existing message and add the current message */ + if (error == Tfa98xx_Error_Buffer_too_small) { + int len; + + /* (a) send the existing (full) message */ + blob = kmalloc(64 * 1024, + GFP_KERNEL); // max length is 64k + len = tfa_tib_dsp_msgmulti(tfa, -1, (const char *)blob); + if (tfa->verbose) { + pr_debug( + "Multi-message buffer full. Sending multi-message, length=%d \n", + len); + } + if (tfa->has_msg == 0) /* via i2c */ { + /* Send tot the target selected */ + error = (tfa->dev_ops.dsp_msg)( + tfa, len, (const char *)blob); + } else { /* via msg hal */ + error = tfa98xx_write_dsp(tfa, len, + (const char *)blob); + } + kfree(blob); + + /* (b) add the current DSP message to a new multi-message */ + error = tfa_tib_dsp_msgmulti(tfa, length, buf); + if (error == Tfa98xx_Error_Fail) { + return Tfa98xx_Error_Fail; + } + } + + lastmessage = error; + + /* When the lastmessage is done we can send the multi-msg to the target */ + if (lastmessage == 1) { + /* Get the full multi-msg data */ + blob = kmalloc(64 * 1024, + GFP_KERNEL); //max length is 64k + length = tfa_tib_dsp_msgmulti(tfa, -1, + (const char *)blob); + + if (tfa->verbose) + pr_debug( + "Last message for the multi-message received. Multi-message length=%d \n", + length); + + if (tfa->has_msg == 0) /* via i2c */ { + /* Send tot the target selected */ + error = (tfa->dev_ops.dsp_msg)( + tfa, length, (const char *)blob); + } else { /* via msg hal */ + error = tfa98xx_write_dsp(tfa, length, + (const char *)blob); + } + + kfree(blob); /* Free the kmalloc blob */ + lastmessage = 0; /* reset to be able to re-start */ + } + } else { + if (tfa->has_msg == 0) /* via i2c */ { + error = (tfa->dev_ops.dsp_msg)(tfa, length, buf); + } else { /* via msg hal */ + error = tfa98xx_write_dsp(tfa, length, + (const char *)buf); + } + } + + if (error != Tfa98xx_Error_Ok) + error = (enum Tfa98xx_Error)( + error + + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */ + + /* DSP verbose has argument 0x04 */ + if ((tfa->verbose & 0x04) != 0) { + pr_debug("DSP w [%d]: ", length); + for (i = 0; i < length; i++) + pr_debug("0x%02x ", (uint8_t)buf[i]); + pr_debug("\n"); + } + + if (tfa->convert_dsp32) { + kmem_cache_free(tfa->cachep, intbuf); + } + + return error; +} + +enum Tfa98xx_Error dsp_msg_read(struct tfa_device *tfa, int length24, + unsigned char *bytes24) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int i; + int length = length24; + unsigned char *bytes = bytes24; + + if (tfa->convert_dsp32) { + length = 4 * length24 / 3; + bytes = kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + } + + if (tfa->has_msg == 0) /* via i2c */ { + error = (tfa->dev_ops.dsp_msg_read)(tfa, length, bytes); + } else { /* via msg hal */ + error = tfa98xx_read_dsp(tfa, length, bytes); + } + + if (error != Tfa98xx_Error_Ok) + error = (enum Tfa98xx_Error)( + error + + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */ + + /* DSP verbose has argument 0x04 */ + if ((tfa->verbose & 0x04) != 0) { + pr_debug("DSP R [%d]: ", length); + for (i = 0; i < length; i++) + pr_debug("0x%02x ", (uint8_t)bytes[i]); + pr_debug("\n"); + } + + if (tfa->convert_dsp32) { + int idx = 0; + + /* convert 32 bit LE to 24 bit BE */ + for (i = 0; i < length; i += 4) { + bytes24[idx++] = bytes[i + 2]; + bytes24[idx++] = bytes[i + 1]; + bytes24[idx++] = bytes[i + 0]; + } + + kmem_cache_free(tfa->cachep, bytes); + } + + return error; +} + +enum Tfa98xx_Error reg_read(struct tfa_device *tfa, unsigned char subaddress, + unsigned short *value) +{ + enum Tfa98xx_Error error; + + error = (tfa->dev_ops.reg_read)(tfa, subaddress, value); + if (error != Tfa98xx_Error_Ok) + error = (enum Tfa98xx_Error)( + error + + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */ + + return error; +} + +enum Tfa98xx_Error reg_write(struct tfa_device *tfa, unsigned char subaddress, + unsigned short value) +{ + enum Tfa98xx_Error error; + + error = (tfa->dev_ops.reg_write)(tfa, subaddress, value); + if (error != Tfa98xx_Error_Ok) + error = (enum Tfa98xx_Error)( + error + + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */ + + return error; +} + +enum Tfa98xx_Error mem_read(struct tfa_device *tfa, unsigned int start_offset, + int num_words, int *pValues) +{ + enum Tfa98xx_Error error; + + error = (tfa->dev_ops.mem_read)(tfa, start_offset, num_words, pValues); + if (error != Tfa98xx_Error_Ok) + error = (enum Tfa98xx_Error)( + error + + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */ + + return error; +} + +enum Tfa98xx_Error mem_write(struct tfa_device *tfa, unsigned short address, + int value, int memtype) +{ + enum Tfa98xx_Error error; + + error = (tfa->dev_ops.mem_write)(tfa, address, value, memtype); + if (error != Tfa98xx_Error_Ok) + error = (enum Tfa98xx_Error)( + error + + Tfa98xx_Error_RpcBase); /* Get actual error code from softDSP */ + + return error; +} + +/* + * write/read raw msg functions : + * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes. + * The functions will return immediately and do not not wait for DSP reponse. + */ +#define MAX_WORDS (300) +enum Tfa98xx_Error tfa_dsp_msg(struct tfa_device *tfa, int length, + const char *buf) +{ + enum Tfa98xx_Error error; + int tries, rpc_status = Tfa98xx_I2C_Req_Done; + + /* write the message and notify the DSP */ + error = tfa_dsp_msg_write(tfa, length, buf); + if (error != Tfa98xx_Error_Ok) + return error; + + /* get the result from the DSP (polling) */ + for (tries = TFA98XX_WAITRESULT_NTRIES; tries > 0; tries--) { + error = tfa_dsp_msg_status(tfa, &rpc_status); + if (error == Tfa98xx_Error_Ok && + rpc_status == Tfa98xx_I2C_Req_Done) + break; + /* If the rpc status is a specific error we want to know it. + * If it is busy or not running it should retry + */ + if (rpc_status != Tfa98xx_I2C_Req_Busy && + rpc_status != Tfa98xx_DSP_Not_Running) + break; + } + + if (rpc_status != Tfa98xx_I2C_Req_Done) { + /* DSP RPC call returned an error */ + error = (enum Tfa98xx_Error)(rpc_status + + Tfa98xx_Error_RpcBase); + pr_debug("DSP msg status: %d (%s)\n", rpc_status, + tfa98xx_get_i2c_status_id_string(rpc_status)); + } + return error; +} + +/** + * write/read raw msg functions: + * the buffer is provided in little endian format, each word occupying 3 bytes, length is in bytes. + * The functions will return immediately and do not not wait for DSP reponse. + * An ID is added to modify the command-ID + */ +enum Tfa98xx_Error tfa_dsp_msg_id(struct tfa_device *tfa, int length, + const char *buf, uint8_t cmdid[3]) +{ + enum Tfa98xx_Error error; + int tries, rpc_status = Tfa98xx_I2C_Req_Done; + + /* write the message and notify the DSP */ + error = tfa_dsp_msg_write_id(tfa, length, buf, cmdid); + if (error != Tfa98xx_Error_Ok) + return error; + + /* get the result from the DSP (polling) */ + for (tries = TFA98XX_WAITRESULT_NTRIES; tries > 0; tries--) { + error = tfa_dsp_msg_status(tfa, &rpc_status); + if (error == Tfa98xx_Error_Ok && + rpc_status == Tfa98xx_I2C_Req_Done) + break; + } + + if (rpc_status != Tfa98xx_I2C_Req_Done) { + /* DSP RPC call returned an error */ + error = (enum Tfa98xx_Error)(rpc_status + + Tfa98xx_Error_RpcBase); + pr_debug("DSP msg status: %d (%s)\n", rpc_status, + tfa98xx_get_i2c_status_id_string(rpc_status)); + } + return error; +} + +/* read the return code for the RPC call */ +TFA_INTERNAL enum Tfa98xx_Error tfa98xx_check_rpc_status(struct tfa_device *tfa, + int *pRpcStatus) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + /* the value to sent to the * CF_CONTROLS register: cf_req=00000000, + * cf_int=0, cf_aif=0, cf_dmem=XMEM=01, cf_rst_dsp=0 */ + unsigned short cf_ctrl = 0x0002; + /* memory address to be accessed (0: Status, 1: ID, 2: parameters) */ + unsigned short cf_mad = 0x0000; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + if (pRpcStatus == NULL) + return Tfa98xx_Error_Bad_Parameter; + + /* 1) write DMEM=XMEM to the DSP XMEM */ + { + /* minimize the number of I2C transactions by making use of the autoincrement in I2C */ + unsigned char buffer[4]; + /* first the data for CF_CONTROLS */ + buffer[0] = (unsigned char)((cf_ctrl >> 8) & 0xFF); + buffer[1] = (unsigned char)(cf_ctrl & 0xFF); + /* write the contents of CF_MAD which is the subaddress following CF_CONTROLS */ + buffer[2] = (unsigned char)((cf_mad >> 8) & 0xFF); + buffer[3] = (unsigned char)(cf_mad & 0xFF); + error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_CONTROLS, + sizeof(buffer), buffer); + } + if (error == Tfa98xx_Error_Ok) { + /* read 1 word (24 bit) from XMEM */ + error = tfa98xx_dsp_read_mem(tfa, 0, 1, pRpcStatus); + } + + return error; +} + +/***************************** xmem only **********************************/ +enum Tfa98xx_Error tfa98xx_dsp_read_mem(struct tfa_device *tfa, + unsigned int start_offset, + int num_words, int *pValues) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned char *bytes; + int burst_size; /* number of words per burst size */ + const int bytes_per_word = 3; + int dmem; + int num_bytes; + int *p; + + bytes = (unsigned char *)kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + if (bytes == NULL) + return Tfa98xx_Error_Fail; + + /* If no offset is given, assume XMEM! */ + if (((start_offset >> 16) & 0xf) > 0) + dmem = (start_offset >> 16) & 0xf; + else + dmem = Tfa98xx_DMEM_XMEM; + + /* Remove offset from adress */ + start_offset = start_offset & 0xffff; + num_bytes = num_words * bytes_per_word; + p = pValues; + + TFA_SET_BF(tfa, DMEM, (uint16_t)dmem); + error = -TFA_WRITE_REG(tfa, MADD, (unsigned short)start_offset); + if (error != Tfa98xx_Error_Ok) + goto tfa98xx_dsp_read_mem_exit; + + for (; num_bytes > 0;) { + burst_size = ROUND_DOWN(tfa->buffer_size, bytes_per_word); + if (num_bytes < burst_size) + burst_size = num_bytes; + + _ASSERT(burst_size <= sizeof(bytes)); + error = tfa98xx_read_data(tfa, FAM_TFA98XX_CF_MEM, burst_size, + bytes); + if (error != Tfa98xx_Error_Ok) + goto tfa98xx_dsp_read_mem_exit; + + tfa98xx_convert_bytes2data(burst_size, bytes, p); + + num_bytes -= burst_size; + p += burst_size / bytes_per_word; + } + +tfa98xx_dsp_read_mem_exit: + kmem_cache_free(tfa->cachep, bytes); + + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_write_mem_word(struct tfa_device *tfa, + unsigned short address, int value, + int memtype) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned char bytes[3]; + + TFA_SET_BF(tfa, DMEM, (uint16_t)memtype); + + error = -TFA_WRITE_REG(tfa, MADD, address); + if (error != Tfa98xx_Error_Ok) + return error; + + tfa98xx_convert_data2bytes(1, &value, bytes); + error = tfa98xx_write_data(tfa, FAM_TFA98XX_CF_MEM, 3, bytes); + + return error; +} + +enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa, + nxpTfaFilter_t *filter) +{ + unsigned char biquad_index; + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + for (biquad_index = 0; biquad_index < 10; biquad_index++) { + if (filter[biquad_index].enabled) { + error = tfa_dsp_cmd_id_write( + tfa, MODULE_BIQUADFILTERBANK, + biquad_index + 1, //start @1 + sizeof(filter[biquad_index].biquad.bytes), + filter[biquad_index].biquad.bytes); + } else { + error = Tfa98xx_DspBiquad_Disable(tfa, + biquad_index + 1); + } + if (error) + return error; + } + + return error; +} + +enum Tfa98xx_Error Tfa98xx_DspBiquad_Disable(struct tfa_device *tfa, + int biquad_index) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int coeff_buffer[BIQUAD_COEFF_SIZE]; + unsigned char bytes[3 + BIQUAD_COEFF_SIZE * 3]; + int nr = 0; + + if (biquad_index > TFA98XX_BIQUAD_NUM) + return Tfa98xx_Error_Bad_Parameter; + if (biquad_index < 1) + return Tfa98xx_Error_Bad_Parameter; + + /* make opcode */ + bytes[nr++] = 0; + bytes[nr++] = MODULE_BIQUADFILTERBANK + 128; + bytes[nr++] = (unsigned char)biquad_index; + + /* set in correct order and format for the DSP */ + coeff_buffer[0] = (int)-8388608; /* -1.0f */ + coeff_buffer[1] = 0; + coeff_buffer[2] = 0; + coeff_buffer[3] = 0; + coeff_buffer[4] = 0; + coeff_buffer[5] = 0; + + /* convert to packed 24 */ + tfa98xx_convert_data2bytes(BIQUAD_COEFF_SIZE, coeff_buffer, &bytes[nr]); + nr += BIQUAD_COEFF_SIZE * 3; + + error = dsp_msg(tfa, nr, (char *)bytes); + + return error; +} + +/* wrapper for dsp_msg that adds opcode */ +enum Tfa98xx_Error tfa_dsp_cmd_id_write(struct tfa_device *tfa, + unsigned char module_id, + unsigned char param_id, int num_bytes, + const unsigned char data[]) +{ + enum Tfa98xx_Error error; + unsigned char *buffer; + int nr = 0; + + buffer = kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + if (buffer == NULL) + return Tfa98xx_Error_Fail; + + buffer[nr++] = tfa->spkr_select; + buffer[nr++] = module_id + 128; + buffer[nr++] = param_id; + + memcpy(&buffer[nr], data, num_bytes); + nr += num_bytes; + + error = dsp_msg(tfa, nr, (char *)buffer); + + kmem_cache_free(tfa->cachep, buffer); + + return error; +} + +/* wrapper for dsp_msg that adds opcode */ +/* this is as the former tfa98xx_dsp_get_param() */ +enum Tfa98xx_Error tfa_dsp_cmd_id_write_read(struct tfa_device *tfa, + unsigned char module_id, + unsigned char param_id, + int num_bytes, + unsigned char data[]) +{ + enum Tfa98xx_Error error; + unsigned char buffer[3]; + int nr = 0; + + if (num_bytes <= 0) { + pr_debug( + "Error: The number of READ bytes is smaller or equal to 0! \n"); + return Tfa98xx_Error_Fail; + } + + if ((tfa->is_probus_device) && (tfa->cnt->ndev == 1) && + (param_id == SB_PARAM_GET_RE25C || + param_id == SB_PARAM_GET_LSMODEL || + param_id == SB_PARAM_GET_ALGO_PARAMS)) { + /* Modifying the ID for GetRe25C */ + buffer[nr++] = 4; + } else { + buffer[nr++] = tfa->spkr_select; + } + buffer[nr++] = module_id + 128; + buffer[nr++] = param_id; + + error = dsp_msg(tfa, nr, (char *)buffer); + if (error != Tfa98xx_Error_Ok) + return error; + + /* read the data from the dsp */ + error = dsp_msg_read(tfa, num_bytes, data); + return error; +} + +/* wrapper for dsp_msg that adds opcode and 3 bytes required for coefs */ +enum Tfa98xx_Error tfa_dsp_cmd_id_coefs(struct tfa_device *tfa, + unsigned char module_id, + unsigned char param_id, int num_bytes, + unsigned char data[]) +{ + enum Tfa98xx_Error error; + unsigned char buffer[2 * 3]; + int nr = 0; + + buffer[nr++] = tfa->spkr_select; + buffer[nr++] = module_id + 128; + buffer[nr++] = param_id; + + buffer[nr++] = 0; + buffer[nr++] = 0; + buffer[nr++] = 0; + + error = dsp_msg(tfa, nr, (char *)buffer); + if (error != Tfa98xx_Error_Ok) + return error; + + /* read the data from the dsp */ + error = dsp_msg_read(tfa, num_bytes, data); + + return error; +} + +/* wrapper for dsp_msg that adds opcode and 3 bytes required for MBDrcDynamics */ +enum Tfa98xx_Error +tfa_dsp_cmd_id_MBDrc_dynamics(struct tfa_device *tfa, unsigned char module_id, + unsigned char param_id, int index_subband, + int num_bytes, unsigned char data[]) +{ + enum Tfa98xx_Error error; + unsigned char buffer[2 * 3]; + int nr = 0; + + buffer[nr++] = tfa->spkr_select; + buffer[nr++] = module_id + 128; + buffer[nr++] = param_id; + + buffer[nr++] = 0; + buffer[nr++] = 0; + buffer[nr++] = (unsigned char)index_subband; + + error = dsp_msg(tfa, nr, (char *)buffer); + if (error != Tfa98xx_Error_Ok) + return error; + + /* read the data from the dsp */ + error = dsp_msg_read(tfa, num_bytes, data); + + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_write_preset(struct tfa_device *tfa, int length, + const unsigned char *p_preset_bytes) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + if (p_preset_bytes != NULL) { + /* by design: keep the data opaque and no + * interpreting/calculation */ + error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST, + SB_PARAM_SET_PRESET, length, + p_preset_bytes); + } else { + error = Tfa98xx_Error_Bad_Parameter; + } + return error; +} + +/* + * get features from MTP + */ +enum Tfa98xx_Error tfa98xx_dsp_get_hw_feature_bits(struct tfa_device *tfa, + int *features) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + uint32_t value; + uint16_t mtpbf; + + /* return the cache data if it's valid */ + if (tfa->hw_feature_bits != -1) { + *features = tfa->hw_feature_bits; + } else { + /* for tfa1 check if we have clock */ + if (tfa->tfa_family == 1) { + int status; + tfa98xx_dsp_system_stable(tfa, &status); + if (!status) { + get_hw_features_from_cnt(tfa, features); + /* skip reading MTP: */ + return (*features == -1) ? Tfa98xx_Error_Fail : + Tfa98xx_Error_Ok; + } + mtpbf = 0x850f; /* MTP5 for tfa1,16 bits */ + } else + mtpbf = 0xf907; /* MTP9 for tfa2, 8 bits */ + value = tfa_read_reg(tfa, mtpbf) & 0xffff; + *features = tfa->hw_feature_bits = value; + } + + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_get_sw_feature_bits(struct tfa_device *tfa, + int features[2]) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + const int byte_size = 2 * 3; + unsigned char bytes[2 * 3]; + + /* return the cache data if it's valid */ + if (tfa->sw_feature_bits[0] != -1) { + features[0] = tfa->sw_feature_bits[0]; + features[1] = tfa->sw_feature_bits[1]; + } else { + /* for tfa1 check if we have clock */ + if (tfa->tfa_family == 1) { + int status; + tfa98xx_dsp_system_stable(tfa, &status); + if (!status) { + get_sw_features_from_cnt(tfa, features); + /* skip reading MTP: */ + return (features[0] == -1) ? + Tfa98xx_Error_Fail : + Tfa98xx_Error_Ok; + } + } + error = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK, + FW_PAR_ID_GET_FEATURE_INFO, + byte_size, bytes); + + if (error != Tfa98xx_Error_Ok) { + /* old ROM code may respond with Tfa98xx_Error_RpcParamId */ + return error; + } + + tfa98xx_convert_bytes2data(byte_size, bytes, features); + } + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_get_state_info(struct tfa_device *tfa, + unsigned char bytes[], + unsigned int *statesize) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int bSupportFramework = 0; + unsigned int stateSize = 9; + + err = tfa98xx_dsp_support_framework(tfa, &bSupportFramework); + if (err == Tfa98xx_Error_Ok) { + if (bSupportFramework) { + err = tfa_dsp_cmd_id_write_read(tfa, MODULE_FRAMEWORK, + FW_PARAM_GET_STATE, + 3 * stateSize, bytes); + } else { + /* old ROM code, ask SpeakerBoost and only do first portion */ + stateSize = 8; + err = tfa_dsp_cmd_id_write_read(tfa, + MODULE_SPEAKERBOOST, + SB_PARAM_GET_STATE, + 3 * stateSize, bytes); + } + } + + *statesize = stateSize; + + return err; +} + +enum Tfa98xx_Error tfa98xx_dsp_support_drc(struct tfa_device *tfa, + int *pbSupportDrc) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + *pbSupportDrc = 0; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + if (tfa->supportDrc != supportNotSet) { + *pbSupportDrc = (tfa->supportDrc == supportYes); + } else { + int featureBits[2]; + + error = tfa98xx_dsp_get_sw_feature_bits(tfa, featureBits); + if (error == Tfa98xx_Error_Ok) { + /* easy case: new API available */ + /* bit=0 means DRC enabled */ + *pbSupportDrc = (featureBits[0] & FEATURE1_DRC) == 0; + } else if (error == Tfa98xx_Error_RpcParamId) { + /* older ROM code, doesn't support it */ + *pbSupportDrc = 0; + error = Tfa98xx_Error_Ok; + } + /* else some other error, return transparently */ + /* pbSupportDrc only changed when error == Tfa98xx_Error_Ok */ + + if (error == Tfa98xx_Error_Ok) { + tfa->supportDrc = + *pbSupportDrc ? supportYes : supportNo; + } + } + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_support_framework(struct tfa_device *tfa, + int *pbSupportFramework) +{ + int featureBits[2] = { 0, 0 }; + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + _ASSERT(pbSupportFramework != 0); + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + if (tfa->supportFramework != supportNotSet) { + if (tfa->supportFramework == supportNo) + *pbSupportFramework = 0; + else + *pbSupportFramework = 1; + } else { + error = tfa98xx_dsp_get_sw_feature_bits(tfa, featureBits); + if (error == Tfa98xx_Error_Ok) { + *pbSupportFramework = 1; + tfa->supportFramework = supportYes; + } else { + *pbSupportFramework = 0; + tfa->supportFramework = supportNo; + error = Tfa98xx_Error_Ok; + } + } + + /* *pbSupportFramework only changed when error == Tfa98xx_Error_Ok */ + return error; +} + +enum Tfa98xx_Error +tfa98xx_dsp_write_speaker_parameters(struct tfa_device *tfa, int length, + const unsigned char *p_speaker_bytes) +{ + enum Tfa98xx_Error error; + int bSupportDrc; + + if (p_speaker_bytes != NULL) { + /* by design: keep the data opaque and no + * interpreting/calculation */ + /* Use long WaitResult retry count */ + error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST, + SB_PARAM_SET_LSMODEL, length, + p_speaker_bytes); + } else { + error = Tfa98xx_Error_Bad_Parameter; + } + + if (error != Tfa98xx_Error_Ok) + return error; + + error = tfa98xx_dsp_support_drc(tfa, &bSupportDrc); + if (error != Tfa98xx_Error_Ok) + return error; + + if (bSupportDrc) { + /* Need to set AgcGainInsert back to PRE, + * as the SetConfig forces it to POST */ + uint8_t bytes[3] = { 0, 0, 0 }; + + error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST, + SB_PARAM_SET_AGCINS, 3, bytes); + } + + return error; +} + +enum Tfa98xx_Error tfa98xx_dsp_write_config(struct tfa_device *tfa, int length, + const unsigned char *p_config_bytes) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int bSupportDrc; + + error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST, + SB_PARAM_SET_CONFIG, length, + p_config_bytes); + if (error != Tfa98xx_Error_Ok) + return error; + + error = tfa98xx_dsp_support_drc(tfa, &bSupportDrc); + if (error != Tfa98xx_Error_Ok) + return error; + + if (bSupportDrc) { + /* Need to set AgcGainInsert back to PRE, + * as the SetConfig forces it to POST */ + uint8_t bytes[3] = { 0, 0, 0 }; + + error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST, + SB_PARAM_SET_AGCINS, 3, bytes); + } + + return error; +} + +/* load all the parameters for the DRC settings from a file */ +enum Tfa98xx_Error tfa98xx_dsp_write_drc(struct tfa_device *tfa, int length, + const unsigned char *p_drc_bytes) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + if (p_drc_bytes != NULL) { + error = tfa_dsp_cmd_id_write(tfa, MODULE_SPEAKERBOOST, + SB_PARAM_SET_DRC, length, + p_drc_bytes); + + } else { + error = Tfa98xx_Error_Bad_Parameter; + } + return error; +} + +enum Tfa98xx_Error tfa98xx_powerdown(struct tfa_device *tfa, int powerdown) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + error = TFA_SET_BF(tfa, PWDN, (uint16_t)powerdown); + + if (powerdown) { + /* Workaround for ticket PLMA5337 */ + if (tfa->tfa_family == 2) { + TFA_SET_BF_VOLATILE(tfa, AMPE, 0); + } + } + + return error; +} + +enum Tfa98xx_Error tfa98xx_select_mode(struct tfa_device *tfa, + enum Tfa98xx_Mode mode) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + if (error == Tfa98xx_Error_Ok) { + switch (mode) { + default: + error = Tfa98xx_Error_Bad_Parameter; + } + } + + return error; +} + +int tfa_set_bf(struct tfa_device *tfa, const uint16_t bf, const uint16_t value) +{ + enum Tfa98xx_Error err; + uint16_t regvalue, msk, oldvalue; + + /* + * bitfield enum: + * - 0..3 : len + * - 4..7 : pos + * - 8..15 : address + */ + uint8_t len = bf & 0x0f; + uint8_t pos = (bf >> 4) & 0x0f; + uint8_t address = (bf >> 8) & 0xff; + + err = reg_read(tfa, address, ®value); + if (err) { + pr_err("Error getting bf :%d \n", -err); + return -err; + } + + oldvalue = regvalue; + msk = ((1 << (len + 1)) - 1) << pos; + regvalue &= ~msk; + regvalue |= value << pos; + + /* Only write when the current register value is not the same as the new value */ + if (oldvalue != regvalue) { + err = reg_write(tfa, address, regvalue); + if (err) { + pr_err("Error setting bf :%d \n", -err); + return -err; + } + } + + return 0; +} + +int tfa_set_bf_volatile(struct tfa_device *tfa, const uint16_t bf, + const uint16_t value) +{ + enum Tfa98xx_Error err; + uint16_t regvalue, msk; + + /* + * bitfield enum: + * - 0..3 : len + * - 4..7 : pos + * - 8..15 : address + */ + uint8_t len = bf & 0x0f; + uint8_t pos = (bf >> 4) & 0x0f; + uint8_t address = (bf >> 8) & 0xff; + + err = reg_read(tfa, address, ®value); + if (err) { + pr_err("Error getting bf :%d \n", -err); + return -err; + } + + msk = ((1 << (len + 1)) - 1) << pos; + regvalue &= ~msk; + regvalue |= value << pos; + + err = reg_write(tfa, address, regvalue); + if (err) { + pr_err("Error setting bf :%d \n", -err); + return -err; + } + + return 0; +} + +int tfa_get_bf(struct tfa_device *tfa, const uint16_t bf) +{ + enum Tfa98xx_Error err; + uint16_t regvalue, msk; + uint16_t value; + + /* + * bitfield enum: + * - 0..3 : len + * - 4..7 : pos + * - 8..15 : address + */ + uint8_t len = bf & 0x0f; + uint8_t pos = (bf >> 4) & 0x0f; + uint8_t address = (bf >> 8) & 0xff; + + err = reg_read(tfa, address, ®value); + if (err) { + pr_err("Error getting bf :%d \n", -err); + return -err; + } + + msk = ((1 << (len + 1)) - 1) << pos; + regvalue &= msk; + value = regvalue >> pos; + + return value; +} + +int tfa_set_bf_value(const uint16_t bf, const uint16_t bf_value, + uint16_t *p_reg_value) +{ + uint16_t regvalue, msk; + + /* + * bitfield enum: + * - 0..3 : len + * - 4..7 : pos + * - 8..15 : address + */ + uint8_t len = bf & 0x0f; + uint8_t pos = (bf >> 4) & 0x0f; + + regvalue = *p_reg_value; + + msk = ((1 << (len + 1)) - 1) << pos; + regvalue &= ~msk; + regvalue |= bf_value << pos; + + *p_reg_value = regvalue; + + return 0; +} + +uint16_t tfa_get_bf_value(const uint16_t bf, const uint16_t reg_value) +{ + uint16_t msk, value; + + /* + * bitfield enum: + * - 0..3 : len + * - 4..7 : pos + * - 8..15 : address + */ + uint8_t len = bf & 0x0f; + uint8_t pos = (bf >> 4) & 0x0f; + + msk = ((1 << (len + 1)) - 1) << pos; + value = (reg_value & msk) >> pos; + + return value; +} + +int tfa_write_reg(struct tfa_device *tfa, const uint16_t bf, + const uint16_t reg_value) +{ + enum Tfa98xx_Error err; + + /* bitfield enum - 8..15 : address */ + uint8_t address = (bf >> 8) & 0xff; + + err = reg_write(tfa, address, reg_value); + if (err) + return -err; + + return 0; +} + +int tfa_read_reg(struct tfa_device *tfa, const uint16_t bf) +{ + enum Tfa98xx_Error err; + uint16_t regvalue; + + /* bitfield enum - 8..15 : address */ + uint8_t address = (bf >> 8) & 0xff; + + err = reg_read(tfa, address, ®value); + if (err) + return -err; + + return regvalue; +} + +/* + * powerup the coolflux subsystem and wait for it + */ +enum Tfa98xx_Error tfa_cf_powerup(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int tries, status; + + /* power on the sub system */ + TFA_SET_BF_VOLATILE(tfa, PWDN, 0); + + // wait until everything is stable, in case clock has been off + if (tfa->verbose) + pr_info("Waiting for DSP system stable...\n"); + for (tries = CFSTABLE_TRIES; tries > 0; tries--) { + err = tfa98xx_dsp_system_stable(tfa, &status); + _ASSERT(err == Tfa98xx_Error_Ok); + if (status) + break; + else + msleep_interruptible( + 10); /* wait 10ms to avoid busload */ + } + if (tries == 0) { // timedout + pr_err("DSP subsystem start timed out\n"); + return Tfa98xx_Error_StateTimedOut; + } + + return err; +} + +/* + * Enable/Disable the I2S output for TFA1 devices + * without TDM interface + */ +static enum Tfa98xx_Error tfa98xx_aec_output(struct tfa_device *tfa, int enable) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + if ((tfa->daimap & Tfa98xx_DAI_TDM) == Tfa98xx_DAI_TDM) + return err; + + if (tfa->tfa_family == 1) + err = -tfa_set_bf(tfa, TFA1_BF_I2SDOE, (enable != 0)); + else { + pr_err("I2SDOE on unsupported family\n"); + err = Tfa98xx_Error_Not_Supported; + } + + return err; +} + +/* + * Print the current state of the hardware manager + * Device manager status information, man_state from TFA9888_N1B_I2C_regmap_V12 + */ +enum Tfa98xx_Error show_current_state(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int manstate = -1; + + if (tfa->tfa_family == 2 +#ifndef __KERNEL__ + && tfa->verbose +#endif + ) { + manstate = TFA_GET_BF(tfa, MANSTATE); + if (manstate < 0) + return -manstate; + + pr_debug("Current HW manager state: "); + + switch (manstate) { + case 0: + pr_debug("power_down_state \n"); + break; + case 1: + pr_debug("wait_for_source_settings_state \n"); + break; + case 2: + pr_debug("connnect_pll_input_state \n"); + break; + case 3: + pr_debug("disconnect_pll_input_state \n"); + break; + case 4: + pr_debug("enable_pll_state \n"); + break; + case 5: + pr_debug("enable_cgu_state \n"); + break; + case 6: + pr_debug("init_cf_state \n"); + break; + case 7: + pr_debug("enable_amplifier_state \n"); + break; + case 8: + pr_debug("alarm_state \n"); + break; + case 9: + pr_debug("operating_state \n"); + break; + case 10: + pr_debug("mute_audio_state \n"); + break; + case 11: + pr_debug("disable_cgu_pll_state \n"); + break; + default: + pr_debug("Unable to find current state \n"); + break; + } + } + + return err; +} + +/* + * start the speakerboost algorithm + * this implies a full system startup when the system was not already started + * + */ +enum Tfa98xx_Error tfaRunSpeakerBoost(struct tfa_device *tfa, int force, + int profile) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int value; + + if (force) { + err = tfaRunColdStartup(tfa, profile); + if (err) + return err; + } + + /* Returns 1 when device is "cold" and 0 when device is warm */ + value = tfa_is_cold(tfa); + + pr_debug("Startup of device [%s] is a %sstart\n", + tfaContDeviceName(tfa->cnt, tfa->dev_idx), + value ? "cold" : "warm"); + + /* cold start and not tap profile */ + if (value) { + /* Run startup and write all files */ + err = tfaRunSpeakerStartup(tfa, force, profile); + if (err) { + pr_err("tfaRunSpeakerStartup error %d\n", err); + return err; + } + /* Save the current profile and set the vstep to 0 */ + /* This needs to be overwriten even in CF bypass */ + tfa_dev_set_swprof(tfa, (unsigned short)profile); + tfa_dev_set_swvstep(tfa, 0); + + /* Synchonize I/V delay on 96/97 at cold start */ + if ((tfa->tfa_family == 1) && (tfa->daimap == Tfa98xx_DAI_TDM)) + tfa->sync_iv_delay = 1; + } + + return err; +} + +enum Tfa98xx_Error tfaRunSpeakerStartup(struct tfa_device *tfa, int force, + int profile) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + pr_debug("%s force=%d profile=%d\n", __func__, force, profile); + if (!force) { // in case of force CF already runnning + err = tfaRunStartup(tfa, profile); + PRINT_ASSERT(err); + if (err) { + pr_err("tfaRunStartup failed %d\n", err); + return err; + } + /* Startup with CF in bypass then return here */ + if (tfa_cf_enabled(tfa) == 0) { + pr_err("tfa_cf_enabled==0\n"); + return err; + } + + /* respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */ + if (tfa->ext_dsp == -1) { + err = tfaRunStartDSP(tfa); + if (err) { + pr_err("tfaRunStartup failed %d\n", err); + return err; + } + } + } + + /* Set auto_copy_mtp_to_iic (bit 5 of A3) to 1 */ + tfa98xx_auto_copy_mtp_to_iic(tfa); + + /* write all the files from the device list */ + err = tfaContWriteFiles(tfa); + if (err) { + pr_debug("[%s] tfaContWriteFiles error = %d \n", __FUNCTION__, + err); + return err; + } + + /* write all the files from the profile list (use volumstep 0) */ + err = tfaContWriteFilesProf(tfa, profile, 0); + if (err) { + pr_debug("[%s] tfaContWriteFilesProf error = %d \n", + __FUNCTION__, err); + return err; + } + + return err; +} + +/* + * Run calibration + */ +enum Tfa98xx_Error tfaRunSpeakerCalibration(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int calibrateDone; + + /* return if there is no audio running */ + if ((tfa->tfa_family == 2) && TFA_GET_BF(tfa, NOCLK)) + return Tfa98xx_Error_NoClock; + + /* When MTPOTC is set (cal=once) unlock key2 */ + if (TFA_GET_BF(tfa, MTPOTC) == 1) { + tfa98xx_key2(tfa, 0); + } + + /* await calibration, this should return ok */ + err = tfaRunWaitCalibration(tfa, &calibrateDone); + if (err == Tfa98xx_Error_Ok) { + err = tfa_dsp_get_calibration_impedance(tfa); + PRINT_ASSERT(err); + } + + /* When MTPOTC is set (cal=once) re-lock key2 */ + if (TFA_GET_BF(tfa, MTPOTC) == 1) { + tfa98xx_key2(tfa, 1); + } + + return err; +} + +enum Tfa98xx_Error tfaRunColdboot(struct tfa_device *tfa, int state) +{ +#define CF_CONTROL 0x8100 + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int tries = 10; + + /* repeat set ACS bit until set as requested */ + while (state != TFA_GET_BF(tfa, ACS)) { + /* set colstarted in CF_CONTROL to force ACS */ + err = mem_write(tfa, CF_CONTROL, state, Tfa98xx_DMEM_IOMEM); + PRINT_ASSERT(err); + + if (tries-- == 0) { + pr_debug("coldboot (ACS) did not %s\n", + state ? "set" : "clear"); + return Tfa98xx_Error_Other; + } + } + + return err; +} + +/* + * load the patch if any + * else tell no loaded + */ +static enum Tfa98xx_Error tfa_run_load_patch(struct tfa_device *tfa) +{ + return tfaContWritePatch(tfa); +} + +/* + * this will load the patch witch will implicitly start the DSP + * if no patch is available the DPS is started immediately + */ +enum Tfa98xx_Error tfaRunStartDSP(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + err = tfa_run_load_patch(tfa); + if (err) { /* patch load is fatal so return immediately*/ + return err; + } + + /* Clear count_boot, should be reset to 0 before the DSP reset is released */ + err = mem_write(tfa, 512, 0, Tfa98xx_DMEM_XMEM); + PRINT_ASSERT(err); + + /* Reset DSP once for sure after initializing */ + if (err == Tfa98xx_Error_Ok) { + err = tfa98xx_dsp_reset(tfa, 0); + PRINT_ASSERT(err); + } + + /* Sample rate is needed to set the correct tables */ + err = tfa98xx_dsp_write_tables(tfa, TFA_GET_BF(tfa, AUDFS)); + PRINT_ASSERT(err); + + return err; +} + +/* + * start the clocks and wait until the AMP is switching + * on return the DSP sub system will be ready for loading + */ +enum Tfa98xx_Error tfaRunStartup(struct tfa_device *tfa, int profile) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + nxpTfaDeviceList_t *dev = tfaContDevice(tfa->cnt, tfa->dev_idx); + int i, noinit = 0; + + if (dev == NULL) + return Tfa98xx_Error_Fail; + + if (dev->bus) /* no i2c device, do nothing */ + return Tfa98xx_Error_Ok; + + /* process the device list to see if the user implemented the noinit */ + for (i = 0; i < dev->length; i++) { + if (dev->list[i].type == dscNoInit) { + noinit = 1; + break; + } + } + + if (!noinit) { + /* load the optimal TFA98XX in HW settings */ + err = tfa98xx_init(tfa); + PRINT_ASSERT(err); + } else { + pr_debug( + "\nWarning: No init keyword found in the cnt file. Init is skipped! \n"); + } + + /* I2S settings to define the audio input properties + * these must be set before the subsys is up */ + // this will run the list until a non-register item is encountered + err = tfaContWriteRegsDev(tfa); // write device register settings + PRINT_ASSERT(err); + // also write register the settings from the default profile + // NOTE we may still have ACS=1 so we can switch sample rate here + err = tfaContWriteRegsProf(tfa, profile); + PRINT_ASSERT(err); + + /* Factory trimming for the Boost converter */ + tfa98xx_factory_trimmer(tfa); + + /* Go to the initCF state */ + tfa_dev_set_state( + tfa, TFA_STATE_INIT_CF, + strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, profile), + ".cal") != NULL); + + err = show_current_state(tfa); + + return err; +} + +/* + * run the startup/init sequence and set ACS bit + */ +enum Tfa98xx_Error tfaRunColdStartup(struct tfa_device *tfa, int profile) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + err = tfaRunStartup(tfa, profile); + PRINT_ASSERT(err); + if (err) + return err; + + if (!tfa->is_probus_device) { + /* force cold boot */ + err = tfaRunColdboot(tfa, 1); // set ACS + PRINT_ASSERT(err); + if (err) + return err; + } + + /* start */ + err = tfaRunStartDSP(tfa); + PRINT_ASSERT(err); + + return err; +} + +/* + * + */ +enum Tfa98xx_Error tfaRunMute(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int status; + int tries = 0; + + /* signal the TFA98XX to mute */ + if (tfa->tfa_family == 1) { + err = tfa98xx_set_mute(tfa, Tfa98xx_Mute_Amplifier); + + if (err == Tfa98xx_Error_Ok) { + /* now wait for the amplifier to turn off */ + do { + status = TFA_GET_BF(tfa, SWS); + if (status != 0) + msleep_interruptible( + 10); /* wait 10ms to avoid busload */ + else + break; + tries++; + } while (tries < AMPOFFWAIT_TRIES); + + if (tfa->verbose) + pr_debug( + "-------------------- muted --------------------\n"); + + /*The amplifier is always switching*/ + if (tries == AMPOFFWAIT_TRIES) + return Tfa98xx_Error_Other; + } + } + + return err; +} +/* + * + */ +enum Tfa98xx_Error tfaRunUnmute(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + /* signal the TFA98XX to mute */ + err = tfa98xx_set_mute(tfa, Tfa98xx_Mute_Off); + + if (tfa->verbose) + pr_debug("-------------------unmuted ------------------\n"); + + return err; +} + +static void individual_calibration_results(struct tfa_device *tfa) +{ + int value_P, value_S; + + /* Read the calibration result in xmem (529=primary channel) (530=secondary channel) */ + mem_read(tfa, 529, 1, &value_P); + mem_read(tfa, 530, 1, &value_S); + + if (value_P != 1 && value_S != 1) + pr_debug("Calibration failed on both channels! \n"); + else if (value_P != 1) { + pr_debug("Calibration failed on Primary (Left) channel! \n"); + TFA_SET_BF_VOLATILE( + tfa, SSLEFTE, + 0); /* Disable the sound for the left speaker */ + } else if (value_S != 1) { + pr_debug("Calibration failed on Secondary (Right) channel! \n"); + TFA_SET_BF_VOLATILE( + tfa, SSRIGHTE, + 0); /* Disable the sound for the right speaker */ + } + + TFA_SET_BF_VOLATILE(tfa, AMPINSEL, 0); /* Set amplifier input to TDM */ + TFA_SET_BF_VOLATILE(tfa, SBSL, 1); +} + +/* + * wait for calibrateDone + */ +enum Tfa98xx_Error tfaRunWaitCalibration(struct tfa_device *tfa, + int *calibrateDone) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int tries = 0, mtp_busy = 1, tries_mtp_busy = 0; + + *calibrateDone = 0; + + /* in case of calibrate once wait for MTPEX */ + if (TFA_GET_BF(tfa, MTPOTC)) { + // Check if MTP_busy is clear! + while (tries_mtp_busy < MTPBWAIT_TRIES) { + mtp_busy = tfa_dev_get_mtpb(tfa); + if (mtp_busy == 1) + msleep_interruptible( + 10); /* wait 10ms to avoid busload */ + else + break; + tries_mtp_busy++; + } + + if (tries_mtp_busy < MTPBWAIT_TRIES) { + /* Because of the msleep TFA98XX_API_WAITRESULT_NTRIES is way to long! + * Setting this to 25 will take it atleast 25*50ms = 1.25 sec + */ + while ((*calibrateDone == 0) && + (tries < MTPEX_WAIT_NTRIES)) { + *calibrateDone = TFA_GET_BF(tfa, MTPEX); + if (*calibrateDone == 1) + break; + msleep_interruptible( + 50); /* wait 50ms to avoid busload */ + tries++; + } + + if (tries >= MTPEX_WAIT_NTRIES) { + tries = TFA98XX_API_WAITRESULT_NTRIES; + } + } else { + pr_err("MTP bussy after %d tries\n", MTPBWAIT_TRIES); + } + } + + /* poll xmem for calibrate always + * calibrateDone = 0 means "calibrating", + * calibrateDone = -1 (or 0xFFFFFF) means "fails" + * calibrateDone = 1 means calibration done + */ + while ((*calibrateDone != 1) && + (tries < TFA98XX_API_WAITRESULT_NTRIES)) { + err = mem_read(tfa, TFA_FW_XMEM_CALIBRATION_DONE, 1, + calibrateDone); + if (*calibrateDone == -1) + break; + tries++; + } + + if (*calibrateDone != 1) { + pr_err("Calibration failed! \n"); + err = Tfa98xx_Error_Bad_Parameter; + } else if (tries == TFA98XX_API_WAITRESULT_NTRIES) { + pr_debug("Calibration has timedout! \n"); + err = Tfa98xx_Error_StateTimedOut; + } else if (tries_mtp_busy == 1000) { + pr_err("Calibrate Failed: MTP_busy stays high! \n"); + err = Tfa98xx_Error_StateTimedOut; + } + + /* Give reason why calibration failed! */ + if (err != Tfa98xx_Error_Ok) { + if ((tfa->tfa_family == 2) && + (TFA_GET_BF(tfa, REFCKSEL) == 1)) { + pr_err("Unable to calibrate the device with the internal clock! \n"); + } + } + + /* Check which speaker calibration failed. Only for 88C */ + if ((err != Tfa98xx_Error_Ok) && ((tfa->rev & 0x0FFF) == 0xc88)) { + individual_calibration_results(tfa); + } + + return err; +} + +/* + * tfa_dev_start will only do the basics: Going from powerdown to operating or a profile switch. + * for calibrating or akoustic shock handling use the tfa98xxCalibration function. + */ +/*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ +#ifdef __KERNEL__ +enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile, + int vstep, u8 pcm_format) +#else +enum tfa_error tfa_dev_start(struct tfa_device *tfa, int next_profile, + int vstep) +#endif +/*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int active_profile = -1; + + pr_debug("entry...\n"); + /* Get currentprofile */ + active_profile = tfa_dev_get_swprof(tfa); + if (active_profile == 0xff) + active_profile = -1; + + /* TfaRun_SpeakerBoost implies un-mute */ + pr_debug("Active_profile:%s, next_profile:%s\n", + tfaContProfileName(tfa->cnt, tfa->dev_idx, active_profile), + tfaContProfileName(tfa->cnt, tfa->dev_idx, next_profile)); + + err = show_current_state(tfa); + + if (tfa->tfa_family == 1) { /* TODO move this to ini file */ + /* Enable I2S output on TFA1 devices without TDM */ + err = tfa98xx_aec_output(tfa, 1); + if (err != Tfa98xx_Error_Ok) + goto error_exit; + } + + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. begin*/ +#ifdef __KERNEL__ + if ((2 == tfa->tfa_family) && (tfa->daimap & Tfa98xx_DAI_TDM)) { + //TFA_SET_BF(tfa, TDMSRCMAP, 2); /*the TDMSRCMAP should be set in cnt file.*/ + /* we should remove below settings from cnt file, otherwise will be overwrite by cnt file later.*/ + if (16 == pcm_format) { + TFA_SET_BF(tfa, TDMNBCK, 0); + TFA_SET_BF(tfa, TDMSLLN, 15); + TFA_SET_BF(tfa, TDMSSIZE, 15); + } else if ((24 == pcm_format) || (32 == pcm_format)) { + TFA_SET_BF(tfa, TDMNBCK, 2); + TFA_SET_BF(tfa, TDMSLLN, 31); + TFA_SET_BF(tfa, TDMSSIZE, 31); + } else { + err = Tfa98xx_Error_Bad_Parameter; + goto error_exit; + } + } +#endif + /*[nxp34663] CR: support 16bit/24bit/32bit audio data. end*/ + + if (tfa->bus != 0) { /* non i2c */ +#ifndef __KERNEL__ + tfadsp_fw_start(tfa, next_profile, vstep); +#endif /* __KERNEL__ */ + } else { + /* Check if we need coldstart or ACS is set */ + err = show_current_state(tfa); + err = tfaRunSpeakerBoost(tfa, 0, next_profile); + if (err != Tfa98xx_Error_Ok) { + pr_err("RunSpeakerBoost failed %d\n", err); + goto error_exit; + } + /* Make sure internal oscillator is running for DSP devices (non-dsp and max1 this is no-op) */ + tfa98xx_set_osc_powerdown(tfa, 0); + pr_debug("[NXP] %s after osc_powerdown\n", __func__); + + /* Go to the Operating state */ +#if 0 + tfa_dev_set_state(tfa, TFA_STATE_OPERATING | TFA_STATE_MUTE, 0); +#else + tfa_dev_set_state(tfa, TFA_STATE_OPERATING, 0); +#endif + pr_debug("[NXP] %s after implemented tfa_dev_set_state()\n", + __func__); + } + + active_profile = tfa_dev_get_swprof(tfa); + + /* Profile switching */ + if ((next_profile != active_profile && active_profile >= 0)) { + err = tfaContWriteProfile(tfa, next_profile, vstep); + if (err != Tfa98xx_Error_Ok) { + pr_err("tfaContWriteProfile failed %d\n", err); + goto error_exit; + } + } + pr_debug("[NXP] %s after implemented tfaContWriteProfile()\n", + __func__); + + /* If the profile contains the .standby suffix go to powerdown + * else we should be in operating state + */ + if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, next_profile), + ".standby") != NULL) { + tfa_dev_set_swprof(tfa, (unsigned short)next_profile); + tfa_dev_set_swvstep(tfa, (unsigned short)tfa->vstep); + goto error_exit; + } + + err = show_current_state(tfa); +#ifndef __KERNEL__ + /* get current vstep*/ + tfa->vstep = tfa_dev_get_swvstep(tfa); +#endif + if ((TFA_GET_BF(tfa, CFE) != 0) && (vstep != tfa->vstep) && + (vstep != -1)) { + err = tfaContWriteFilesVstep(tfa, next_profile, vstep); + if (err != Tfa98xx_Error_Ok) { + pr_err("tfaContWriteFilesVstep failed %d\n", err); + goto error_exit; + } + pr_debug("after implemented tfaContWriteFilesVstep()\n"); + } + + /* Always search and apply filters after a startup */ + err = tfa_set_filters(tfa, next_profile); + if (err != Tfa98xx_Error_Ok) { + pr_err("tfaContWriteFilesVstep failed %d\n", err); + goto error_exit; + } + + tfa_dev_set_swprof(tfa, (unsigned short)next_profile); + tfa_dev_set_swvstep(tfa, (unsigned short)tfa->vstep); + + /* PLMA5539: Gives information about current setting of powerswitch */ + if (tfa->verbose) { + if (!tfa98xx_powerswitch_is_enabled(tfa)) + pr_info("Device start without powerswitch enabled!\n"); + } + +error_exit: + pr_debug("[NXP] %s end...\n", __func__); + show_current_state(tfa); + if (err != Tfa98xx_Error_Ok) { + pr_err("TFA98xx Error code is %d\n", err); + return tfa_error_max; + } + + return tfa_error_ok; +} + +enum tfa_error tfa_dev_stop(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + int manstate = 0, retry = 0; + + /* mute */ + tfaRunMute(tfa); + + /* Make sure internal oscillator is not running for DSP devices (non-dsp and max1 this is no-op) */ + tfa98xx_set_osc_powerdown(tfa, 1); + + /* powerdown CF */ + err = tfa98xx_powerdown(tfa, 1); + if (err != Tfa98xx_Error_Ok) + goto error_exit; + + /* disable I2S output on TFA1 devices without TDM */ + err = tfa98xx_aec_output(tfa, 0); + + /* added by nxp34663 beging. */ + /* we should ensure the state machine in powerdown mode here. */ + manstate = TFA_GET_BF(tfa, MANSTATE); + while ((manstate >= 4) && (retry < 100)) { + pr_debug( + "%s waitting state machine goto powerdown. MANSTATE=%d\n", + __func__, manstate); + msleep_interruptible(10); + manstate = TFA_GET_BF(tfa, MANSTATE); + retry++; + } + /* added by nxp34663 end. */ +error_exit: + if (err != Tfa98xx_Error_Ok) { + pr_err("TFA98xx Error code is %d\n", err); + return tfa_error_max; + } + + return tfa_error_ok; +} + +/* + * int registers and coldboot dsp + */ +int tfa_reset(struct tfa_device *tfa) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + err = -TFA_SET_BF_VOLATILE(tfa, I2CR, 1); + if (err) + return err; + + if (tfa->tfa_family == 2) { + /* restore MANSCONF to POR state */ + TFA_SET_BF_VOLATILE(tfa, MANSCONF, 0); + } + + if (!tfa->is_probus_device) { + if (tfa->tfa_family == 2) { + /* restore MANCOLD to POR state */ + TFA_SET_BF_VOLATILE(tfa, MANCOLD, 1); + } + + /* powerup CF to access CF io */ + tfa98xx_powerdown(tfa, 0); + /* for clock */ + err = tfa_cf_powerup(tfa); + PRINT_ASSERT(err); + + /* force cold boot */ + err = tfaRunColdboot(tfa, 1); // set ACS + PRINT_ASSERT(err); + + /* reset all i2C registers to default */ + err = -TFA_SET_BF(tfa, I2CR, 1); + PRINT_ASSERT(err); + } else { + if (tfa->ext_dsp > 0) + tfa98xx_init_dsp(tfa); + } + + return err; +} + +/* + * Write all the bytes specified by num_bytes and data + */ +enum Tfa98xx_Error tfa98xx_write_data(struct tfa_device *tfa, + unsigned char subaddress, int num_bytes, + const unsigned char data[]) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + /* subaddress followed by data */ + const int bytes2write = num_bytes + 1; + unsigned char *write_data; + + if (num_bytes > TFA2_MAX_PARAM_SIZE) + return Tfa98xx_Error_Bad_Parameter; + + write_data = (unsigned char *)kmem_cache_alloc(tfa->cachep, GFP_KERNEL); + if (write_data == NULL) + return Tfa98xx_Error_Fail; + + write_data[0] = subaddress; + memcpy(&write_data[1], data, num_bytes); + + error = tfa98xx_write_raw(tfa, bytes2write, write_data); + + kmem_cache_free(tfa->cachep, write_data); + return error; +} + +/* + * fill the calibration value as milli ohms in the struct + * + * assume that the device has been calibrated + */ +enum Tfa98xx_Error tfa_dsp_get_calibration_impedance(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned char bytes[3 * 2] = { 0 }; + int nr_bytes, i, data[2], calibrateDone, spkr_count = 0, cal_idx = 0; + unsigned int scaled_data; + int tries = 0; + + error = tfa_supported_speakers(tfa, &spkr_count); + + if (tfa_dev_mtp_get(tfa, TFA_MTP_OTC) && + tfa_dev_mtp_get(tfa, TFA_MTP_EX)) { + pr_debug("Getting calibration values from MTP\n"); + + if ((tfa->rev & 0xFF) == 0x88) { + for (i = 0; i < spkr_count; i++) { + if (i == 0) + tfa->mohm[i] = tfa_dev_mtp_get( + tfa, TFA_MTP_RE25_PRIM); + else + tfa->mohm[i] = tfa_dev_mtp_get( + tfa, TFA_MTP_RE25_SEC); + } + } else { + tfa->mohm[0] = tfa_dev_mtp_get(tfa, TFA_MTP_RE25); + } + } else if ((tfa_dev_mtp_get(tfa, TFA_MTP_OTC) == 0) && + (tfa_dev_mtp_get(tfa, TFA_MTP_EX) == 0)) { + pr_debug("Getting calibration values from Speakerboost\n"); + + /* Make sure the calibrateDone bit is set before getting the values from speakerboost! + * This does not work for 72 (because the dsp cannot set this bit) + */ + if (!tfa->is_probus_device) { + /* poll xmem for calibrate always + * calibrateDone = 0 means "calibrating", + * calibrateDone = -1 (or 0xFFFFFF) means "fails" + * calibrateDone = 1 means calibration done + */ + calibrateDone = 0; + while ((calibrateDone != 1) && + (tries < TFA98XX_API_WAITRESULT_NTRIES)) { + error = mem_read(tfa, + TFA_FW_XMEM_CALIBRATION_DONE, + 1, &calibrateDone); + if ((calibrateDone == 1) || + (Tfa98xx_Error_Ok != error)) + break; + tries++; + } + + if (calibrateDone == 1) + pr_debug("Calibration successed!!!\n"); + else if ((calibrateDone != 1) || + (Tfa98xx_Error_Ok != error)) { + pr_err("Calibration failed! calibrateDone=%d error=%d\n", + calibrateDone, error); + error = Tfa98xx_Error_Bad_Parameter; + } else if (tries == TFA98XX_API_WAITRESULT_NTRIES) { + pr_debug("Calibration has timedout! \n"); + error = Tfa98xx_Error_StateTimedOut; + } + } else { + /* dsp inside of TFA device. */ + calibrateDone = 1; + } + + /* SoftDSP interface differs from hw-dsp interfaces */ + if (tfa->is_probus_device && tfa->cnt->ndev > 1) { + spkr_count = tfa->cnt->ndev; + } + + if (1 == calibrateDone) { + nr_bytes = spkr_count * 3; + error = tfa_dsp_cmd_id_write_read(tfa, + MODULE_SPEAKERBOOST, + SB_PARAM_GET_RE25C, + nr_bytes, bytes); + if (error == Tfa98xx_Error_Ok) { + tfa98xx_convert_bytes2data(nr_bytes, bytes, + data); + + for (i = 0; i < spkr_count; i++) { + /* for probus devices, calibration values coming from soft-dsp speakerboost, + are ordered in a different way. Re-align to standard representation. */ + cal_idx = i; + if ((tfa->is_probus_device && + tfa->dev_idx >= 1)) { + cal_idx = 0; + } + + /* signed data has a limit of 30 Ohm */ + scaled_data = data[i]; + + if (tfa->tfa_family == 2) + tfa->mohm[cal_idx] = + (scaled_data * 1000) / + TFA2_FW_ReZ_SCALE; + else + tfa->mohm[cal_idx] = + (scaled_data * 1000) / + TFA1_FW_ReZ_SCALE; + } + } + } + } else { + for (i = 0; i < spkr_count; i++) { + tfa->mohm[i] = 0; + } + pr_err("Please run calibration command first.\n"); + error = Tfa98xx_Error_Bad_Parameter; + } + + return error; +} + +/* start count from 1, 0 is invalid */ +int tfa_dev_get_swprof(struct tfa_device *tfa) +{ + return (tfa->dev_ops.get_swprof)(tfa); +} + +int tfa_dev_set_swprof(struct tfa_device *tfa, unsigned short new_value) +{ + return (tfa->dev_ops.set_swprof)(tfa, new_value + 1); +} + +/* same value for all channels + * start count from 1, 0 is invalid */ +int tfa_dev_get_swvstep(struct tfa_device *tfa) +{ + return (tfa->dev_ops.get_swvstep)(tfa); +} + +int tfa_dev_set_swvstep(struct tfa_device *tfa, unsigned short new_value) +{ + return (tfa->dev_ops.set_swvstep)(tfa, new_value + 1); +} + +/* + function overload for MTPB + */ +int tfa_dev_get_mtpb(struct tfa_device *tfa) +{ + return (tfa->dev_ops.get_mtpb)(tfa); +} + +int tfa_is_cold(struct tfa_device *tfa) +{ + int value; + + /* + * check for cold boot status + */ + if (tfa->is_probus_device) { + if (tfa->ext_dsp > 0) { + if (tfa->ext_dsp == 2) + value = 0; // warm + else /* no dsp or cold */ + value = 1; // cold + } else { + value = (TFA_GET_BF(tfa, MANSCONF) == 0); + } + } else { + value = TFA_GET_BF(tfa, ACS); + } + + return value; +} + +int tfa_needs_reset(struct tfa_device *tfa) +{ + int value; + + /* checks if the DSP commands SetAlgoParams and SetMBDrc + * need a DSP reset (now: at coldstart or during calibration) + */ + if (tfa_is_cold(tfa) == 1 || tfa->needs_reset == 1) + value = 1; + else + value = 0; + + return value; +} + +int tfa_cf_enabled(struct tfa_device *tfa) +{ + int value; + + /* For 72 there is no CF */ + if (tfa->is_probus_device) { + value = (tfa->ext_dsp != 0); + } else { + value = TFA_GET_BF(tfa, CFE); + } + + return value; +} + +#define NR_COEFFS 6 +#define NR_BIQUADS 28 +#define BQ_SIZE (3 * NR_COEFFS) +#define DSP_MSG_OVERHEAD 27 + +#pragma pack(push, 1) +struct dsp_msg_all_coeff { + uint8_t select_eq[3]; + uint8_t biquad[NR_BIQUADS][NR_COEFFS][3]; +}; +#pragma pack(pop) + +/* number of biquads for each equalizer */ +static const int eq_biquads[] = { 10, 10, 2, 2, 2, 2 }; + +#define NR_EQ (int)(sizeof(eq_biquads) / sizeof(int)) + +enum Tfa98xx_Error dsp_partial_coefficients(struct tfa_device *tfa, + uint8_t *prev, uint8_t *next) +{ + uint8_t bq, eq; + int eq_offset; + int new_cost, old_cost; + uint32_t eq_biquad_mask[NR_EQ]; + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + struct dsp_msg_all_coeff *data1 = (struct dsp_msg_all_coeff *)prev; + struct dsp_msg_all_coeff *data2 = (struct dsp_msg_all_coeff *)next; + + old_cost = DSP_MSG_OVERHEAD + 3 + sizeof(struct dsp_msg_all_coeff); + new_cost = 0; + + eq_offset = 0; + for (eq = 0; eq < NR_EQ; eq++) { + uint8_t *eq1 = &data1->biquad[eq_offset][0][0]; + uint8_t *eq2 = &data2->biquad[eq_offset][0][0]; + + eq_biquad_mask[eq] = 0; + + if (memcmp(eq1, eq2, BQ_SIZE * eq_biquads[eq]) != 0) { + int nr_bq = 0; + int bq_sz, eq_sz; + + for (bq = 0; bq < eq_biquads[eq]; bq++) { + uint8_t *bq1 = &eq1[bq * BQ_SIZE]; + uint8_t *bq2 = &eq2[bq * BQ_SIZE]; + + if (memcmp(bq1, bq2, BQ_SIZE) != 0) { + eq_biquad_mask[eq] |= (1 << bq); + nr_bq++; + } + } + + bq_sz = (2 * 3 + BQ_SIZE) * nr_bq; + eq_sz = 2 * 3 + BQ_SIZE * eq_biquads[eq]; + + /* dsp message i2c transaction overhead */ + bq_sz += DSP_MSG_OVERHEAD * nr_bq; + eq_sz += DSP_MSG_OVERHEAD; + + if (bq_sz >= eq_sz) { + eq_biquad_mask[eq] = 0xffffffff; + + new_cost += eq_sz; + + } else { + new_cost += bq_sz; + } + } + pr_debug("eq_biquad_mask[%d] = 0x%.8x\n", eq, + eq_biquad_mask[eq]); + + eq_offset += eq_biquads[eq]; + } + + pr_debug("cost for writing all coefficients = %d\n", old_cost); + pr_debug("cost for writing changed coefficients = %d\n", new_cost); + + if (new_cost >= old_cost) { + const int buffer_sz = 3 + sizeof(struct dsp_msg_all_coeff); + uint8_t *buffer; + + buffer = kmalloc(buffer_sz, GFP_KERNEL); + if (buffer == NULL) + return Tfa98xx_Error_Fail; + + /* cmd id */ + buffer[0] = 0x00; + buffer[1] = 0x82; + buffer[2] = 0x00; + + /* parameters */ + memcpy(&buffer[3], data2, sizeof(struct dsp_msg_all_coeff)); + + err = dsp_msg(tfa, buffer_sz, (const char *)buffer); + + kfree(buffer); + if (err) + return err; + + } else { + eq_offset = 0; + for (eq = 0; eq < NR_EQ; eq++) { + uint8_t *eq2 = &data2->biquad[eq_offset][0][0]; + + if (eq_biquad_mask[eq] == 0xffffffff) { + const int msg_sz = 6 + BQ_SIZE * eq_biquads[eq]; + uint8_t *msg; + + msg = kmalloc(msg_sz, GFP_KERNEL); + if (msg == NULL) + return Tfa98xx_Error_Fail; + + /* cmd id */ + msg[0] = 0x00; + msg[1] = 0x82; + msg[2] = 0x00; + + /* select eq and bq */ + msg[3] = 0x00; + msg[4] = eq + 1; + msg[5] = 0x00; /* all biquads */ + + /* biquad parameters */ + memcpy(&msg[6], eq2, BQ_SIZE * eq_biquads[eq]); + + err = dsp_msg(tfa, msg_sz, (const char *)msg); + + kfree(msg); + if (err) + return err; + + } else if (eq_biquad_mask[eq] != 0) { + for (bq = 0; bq < eq_biquads[eq]; bq++) { + if (eq_biquad_mask[eq] & (1 << bq)) { + uint8_t *bq2 = + &eq2[bq * BQ_SIZE]; + const int msg_sz = 6 + BQ_SIZE; + uint8_t *msg; + + msg = kmem_cache_alloc( + tfa->cachep, + GFP_KERNEL); + if (msg == NULL) + return Tfa98xx_Error_Fail; + + /* cmd id */ + msg[0] = 0x00; + msg[1] = 0x82; + msg[2] = 0x00; + + /* select eq and bq*/ + msg[3] = 0x00; + msg[4] = eq + 1; + msg[5] = bq + 1; + + /* biquad parameters */ + memcpy(&msg[6], bq2, BQ_SIZE); + + err = dsp_msg( + tfa, msg_sz, + (const char *)msg); + + kmem_cache_free(tfa->cachep, + msg); + if (err) + return err; + } + } + } + eq_offset += eq_biquads[eq]; + } + } + + return err; +} + +/* fill context info */ +int tfa_dev_probe(int slave, struct tfa_device *tfa) +{ + uint16_t rev; + + tfa->slave_address = (unsigned char)slave; + + /* read revid via low level hal, register 3 */ + if (tfa98xx_read_register16(tfa, 3, &rev) != Tfa98xx_Error_Ok) { + PRINT("\nError: Unable to read revid from slave:0x%02x \n", + slave); + return -1; + } + + tfa->rev = rev; + tfa->dev_idx = -1; + tfa->state = TFA_STATE_UNKNOWN; + tfa->p_regInfo = NULL; + + tfa_set_query_info(tfa); + + tfa->in_use = 1; + + return 0; +} + +enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state, + int is_calibration) +{ + enum tfa_error err = tfa_error_ok; + int loop = 50, ready = 0; + int count; + + pr_debug("tfa_dev_set_state() state=%d is_calibration=%d\n", state, + is_calibration); + /* Base states */ + /* Do not change the order of setting bits as this is important! */ + switch (state & 0x0f) { + case TFA_STATE_POWERDOWN: /* PLL in powerdown, Algo up */ + break; + case TFA_STATE_INIT_HW: /* load I2C/PLL hardware setting (~wait2srcsettings) */ + break; + case TFA_STATE_INIT_CF: /* coolflux HW access possible (~initcf) */ + /* Start with SBSL=0 to stay in initCF state */ + if (!tfa->is_probus_device) { + TFA_SET_BF(tfa, SBSL, 0); + } + /* We want to leave Wait4SrcSettings state for max2 */ + if (tfa->tfa_family == 2) + TFA_SET_BF(tfa, MANSCONF, 1); + + /* And finally set PWDN to 0 to leave powerdown state */ + TFA_SET_BF(tfa, PWDN, 0); + + /* Make sure the DSP is running! */ + do { + if (tfa98xx_dsp_system_stable(tfa, &ready) != + Tfa98xx_Error_Ok) + return tfa_error_max; + + if (ready) + break; + } while (loop--); + pr_debug( + "after performed tfa98xx_dsp_system_stable() err=%d ready=%d loop=%d\n", + err, ready, loop); + if ((!tfa->is_probus_device) && (is_calibration)) { + /* Enable FAIM when clock is stable, to avoid MTP corruption */ + err = (enum tfa_error)tfa98xx_faim_protect(tfa, 1); + if (tfa->verbose) { + pr_debug("FAIM enabled (err:%d).\n", err); + } + } + break; + case TFA_STATE_INIT_FW: /* DSP framework active (~patch loaded) */ + break; + case TFA_STATE_OPERATING: /* Amp and Algo running */ + /* Depending on our previous state we need to set 3 bits */ + TFA_SET_BF(tfa, PWDN, 0); /* Coming from state 0 */ + TFA_SET_BF(tfa, MANSCONF, 1); /* Coming from state 1 */ + pr_debug("tfa->is_probus_device=%d is_calibration=%d\n", + tfa->is_probus_device, is_calibration); + /* we should set AMPE as 1 for NON-DSP device, otherwise will be setting SBSL as 1 */ + if (tfa->is_probus_device) { + TFA_SET_BF(tfa, AMPE, 1); /* Coming from state 6 */ + } else { + TFA_SET_BF(tfa, SBSL, 1); /* Coming from state 6 */ + } + + /* + * Disable MTP clock to protect memory. + * However in case of calibration wait for DSP! (This should be case only during calibration). + */ + if ((TFA_GET_BF(tfa, MTPOTC) == 1) && (tfa->tfa_family == 2) && + is_calibration) { + count = MTPEX_WAIT_NTRIES * + 4; /* Calibration takes a lot of time */ + while ((TFA_GET_BF(tfa, MTPEX) != 1) && count) { + msleep_interruptible(10); + count--; + } + } + if ((!tfa->is_probus_device) && (is_calibration)) { + err = (enum tfa_error)tfa98xx_faim_protect(tfa, 0); + if (tfa->verbose) { + pr_debug("FAIM disabled (err:%d).\n", err); + } + } + /* Synchonize I/V delay on 96/97 at cold start */ + if (tfa->sync_iv_delay) { + if (tfa->verbose) + pr_debug("syncing I/V delay for %x\n", + (tfa->rev & 0xff)); + + /* wait for ACS to be cleared */ + count = 10; + while ((TFA_GET_BF(tfa, ACS) == 1) && (count-- > 0)) { + msleep_interruptible(1); + } + + tfa98xx_dsp_reset(tfa, 1); + tfa98xx_dsp_reset(tfa, 0); + tfa->sync_iv_delay = 0; + } + break; + case TFA_STATE_FAULT: /* An alarm or error occurred */ + break; + case TFA_STATE_RESET: /* I2C reset and ACS set */ + tfa98xx_init(tfa); + break; + default: + if (state & 0x0f) + return tfa_error_bad_param; + } + + /* state modifiers */ + + if (state & TFA_STATE_MUTE) + tfa98xx_set_mute(tfa, Tfa98xx_Mute_Amplifier); + + if (state & TFA_STATE_UNMUTE) + tfa98xx_set_mute(tfa, Tfa98xx_Mute_Off); + + tfa->state = state; + + return tfa_error_ok; +} + +enum tfa_state tfa_dev_get_state(struct tfa_device *tfa) +{ + int cold = 0; + int manstate; + + /* different per family type */ + if (tfa->tfa_family == 1) { + cold = TFA_GET_BF(tfa, ACS); + if (cold && TFA_GET_BF(tfa, PWDN)) + tfa->state = TFA_STATE_RESET; + else if (!cold && TFA_GET_BF(tfa, SWS)) + tfa->state = TFA_STATE_OPERATING; + } else /* family 2 */ { + manstate = TFA_GET_BF(tfa, MANSTATE); + switch (manstate) { + case 0: + tfa->state = TFA_STATE_POWERDOWN; + break; + case 8: /* if dsp reset if off assume framework is running */ + tfa->state = TFA_GET_BF(tfa, RST) ? TFA_STATE_INIT_CF : + TFA_STATE_INIT_FW; + break; + case 9: + tfa->state = TFA_STATE_OPERATING; + break; + default: + break; + } + } + + return tfa->state; +} + +int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item) +{ + int value = 0; + + switch (item) { + case TFA_MTP_OTC: + value = TFA_GET_BF(tfa, MTPOTC); + break; + case TFA_MTP_EX: + value = TFA_GET_BF(tfa, MTPEX); + break; + case TFA_MTP_RE25: + case TFA_MTP_RE25_PRIM: + if (tfa->tfa_family == 2) { + if ((tfa->rev & 0xFF) == 0x88) + value = TFA_GET_BF(tfa, R25CL); + else if ((tfa->rev & 0xFF) == 0x13) + value = tfa_get_bf(tfa, TFA9912_BF_R25C); + else + value = TFA_GET_BF(tfa, R25C); + } else { + reg_read(tfa, 0x83, (unsigned short *)&value); + } + break; + case TFA_MTP_RE25_SEC: + if ((tfa->rev & 0xFF) == 0x88) { + value = TFA_GET_BF(tfa, R25CR); + } else { + pr_debug( + "Error: Current device has no secondary Re25 channel \n"); + } + break; + case TFA_MTP_LOCK: + break; + } + + return value; +} + +enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item, + int value) +{ + enum Tfa98xx_Error err = Tfa98xx_Error_Ok; + + switch (item) { + case TFA_MTP_OTC: + err = tfa98xx_set_mtp(tfa, (uint16_t)value, + TFA98XX_KEY2_PROTECTED_MTP0_MTPOTC_MSK); + break; + case TFA_MTP_EX: + err = tfa98xx_set_mtp(tfa, (uint16_t)value, + TFA98XX_KEY2_PROTECTED_MTP0_MTPEX_MSK); + break; + case TFA_MTP_RE25: + case TFA_MTP_RE25_PRIM: + if (tfa->tfa_family == 2) { + if ((tfa->rev & 0xFF) == 0x88) + TFA_SET_BF(tfa, R25CL, (uint16_t)value); + else + TFA_SET_BF(tfa, R25C, (uint16_t)value); + } + break; + case TFA_MTP_RE25_SEC: + if ((tfa->rev & 0xFF) == 0x88) { + TFA_SET_BF(tfa, R25CR, (uint16_t)value); + } else { + pr_debug( + "Error: Current device has no secondary Re25 channel \n"); + err = Tfa98xx_Error_Bad_Parameter; + } + break; + case TFA_MTP_LOCK: + break; + } + + if (err != Tfa98xx_Error_Ok) { + pr_err("TFA98xx Error code is %d\n", err); + return tfa_error_max; + } + return tfa_error_ok; +} + +int tfa_get_pga_gain(struct tfa_device *tfa) +{ + return TFA_GET_BF(tfa, SAAMGAIN); +} + +int tfa_set_pga_gain(struct tfa_device *tfa, uint16_t value) +{ + return TFA_SET_BF(tfa, SAAMGAIN, value); +} + +int tfa_get_noclk(struct tfa_device *tfa) +{ + return TFA_GET_BF(tfa, NOCLK); +} + +enum Tfa98xx_Error tfa_status(struct tfa_device *tfa) +{ + int value; + uint16_t val; + + /* + * check IC status bits: cold start + * and DSP watch dog bit to re init + */ + value = TFA_READ_REG(tfa, VDDS); /* STATUSREG */ + if (value < 0) + return -value; + val = (uint16_t)value; + + /* pr_debug("SYS_STATUS0: 0x%04x\n", val); */ + if (TFA_GET_BF_VALUE(tfa, ACS, val) || + TFA_GET_BF_VALUE(tfa, WDS, val)) { + if (TFA_GET_BF_VALUE(tfa, ACS, val)) + pr_err("ERROR: ACS\n"); + if (TFA_GET_BF_VALUE(tfa, WDS, val)) + pr_err("ERROR: WDS\n"); + + return Tfa98xx_Error_DSP_not_running; + } + + if (TFA_GET_BF_VALUE(tfa, SPKS, val)) + pr_err("ERROR: SPKS\n"); + if (!TFA_GET_BF_VALUE(tfa, SWS, val)) + pr_err("ERROR: SWS\n"); + + /* Check secondary errors */ + if (!TFA_GET_BF_VALUE(tfa, CLKS, val) || + !TFA_GET_BF_VALUE(tfa, UVDS, val) || + !TFA_GET_BF_VALUE(tfa, OVDS, val) || + !TFA_GET_BF_VALUE(tfa, OTDS, val) || + !TFA_GET_BF_VALUE(tfa, PLLS, val) || + (!(tfa->daimap & Tfa98xx_DAI_TDM) && + !TFA_GET_BF_VALUE(tfa, VDDS, val))) + pr_err("Misc errors detected: STATUS_FLAG0 = 0x%x\n", val); + + if ((tfa->daimap & Tfa98xx_DAI_TDM) && (tfa->tfa_family == 2)) { + value = TFA_READ_REG(tfa, TDMERR); /* STATUS_FLAGS1 */ + if (value < 0) + return -value; + val = (uint16_t)value; + if (TFA_GET_BF_VALUE(tfa, TDMERR, val) || + TFA_GET_BF_VALUE(tfa, TDMLUTER, val)) + pr_err("TDM related errors: STATUS_FLAG1 = 0x%x\n", + val); + } + + return Tfa98xx_Error_Ok; +} + +#ifdef __KERNEL__ +int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep, + u8 pcm_format) +#else +int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep) +#endif +{ + enum tfa_error err; + int no_clk = 0; + + /* Remove sticky bit by reading it once */ + TFA_GET_BF(tfa, NOCLK); + + /* No clock detected */ + if (tfa_irq_get(tfa, tfa9912_irq_stnoclk)) { + no_clk = TFA_GET_BF(tfa, NOCLK); + + /* Detect for clock is lost! (clock is not stable) */ + if (no_clk == 1) { + /* Clock is lost. Set I2CR to remove POP noise */ + pr_info("No clock detected. Resetting the I2CR to avoid pop on 72! \n"); +#ifdef __KERNEL__ + err = tfa_dev_start(tfa, profile, vstep, pcm_format); +#else + err = tfa_dev_start(tfa, profile, vstep); +#endif + if (err != tfa_error_ok) { + pr_err("Error loading i2c registers (tfa_dev_start), err=%d\n", + err); + } else { + pr_info("Setting i2c registers after I2CR succesfull\n"); + tfa_dev_set_state(tfa, TFA_STATE_UNMUTE, 0); + } + + /* Remove sticky bit by reading it once */ + tfa_get_noclk(tfa); + + /* This is only for SAAM on the 72. + Since the NOCLK interrupt is only enabled for 72 this is the place + However: Not tested yet! But also does not harm normal flow! + */ + if (strstr(tfaContProfileName(tfa->cnt, tfa->dev_idx, + profile), + ".saam")) { + pr_info("Powering down from a SAAM profile, workaround PLMA4766 used! \n"); + TFA_SET_BF(tfa, PWDN, 1); + TFA_SET_BF(tfa, AMPE, 0); + TFA_SET_BF(tfa, SAMMODE, 0); + } + } + + /* If clk is stable set polarity to check for LOW (no clock)*/ + tfa_irq_set_pol(tfa, tfa9912_irq_stnoclk, (no_clk == 0)); + + /* clear interrupt */ + tfa_irq_clear(tfa, tfa9912_irq_stnoclk); + } + + /* return no_clk to know we called tfa_dev_start */ + return no_clk; +} + +void tfa_lp_mode_interrupt(struct tfa_device *tfa) +{ + const int irq_stclp0 = + 36; /* FIXME: this 72 interrupt does not excist for 9912 */ + int lp0, lp1; + + if (tfa_irq_get(tfa, irq_stclp0)) { + lp0 = TFA_GET_BF(tfa, LP0); + if (lp0 > 0) { + pr_info("lowpower mode 0 detected\n"); + } else { + pr_info("lowpower mode 0 not detected\n"); + } + + tfa_irq_set_pol(tfa, irq_stclp0, (lp0 == 0)); + + /* clear interrupt */ + tfa_irq_clear(tfa, irq_stclp0); + } + + if (tfa_irq_get(tfa, tfa9912_irq_stclpr)) { + lp1 = TFA_GET_BF(tfa, LP1); + if (lp1 > 0) { + pr_info("lowpower mode 1 detected\n"); + } else { + pr_info("lowpower mode 1 not detected\n"); + } + + tfa_irq_set_pol(tfa, tfa9912_irq_stclpr, (lp1 == 0)); + + /* clear interrupt */ + tfa_irq_clear(tfa, tfa9912_irq_stclpr); + } +} diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c new file mode 100644 index 000000000000..8bd5167f889a --- /dev/null +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c @@ -0,0 +1,1727 @@ +/* + * Copyright 2014-2017 NXP Semiconductors + * Copyright (C) 2019 XiaoMi, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dbgprint.h" +#include "tfa_service.h" +#include "tfa_internal.h" +#include "tfa_container.h" +#include "tfa98xx_tfafieldnames.h" + +/* The CurrentSense4 registers are not in the datasheet */ +#define TFA98XX_CURRENTSENSE4_CTRL_CLKGATECFOFF (1 << 2) +#define TFA98XX_CURRENTSENSE4 0x49 + +/***********************************************************************************/ +/* GLOBAL (Defaults) */ +/***********************************************************************************/ +static enum Tfa98xx_Error no_overload_function_available(struct tfa_device *tfa, + int not_used) +{ + (void)tfa; + (void)not_used; + + return Tfa98xx_Error_Ok; +} + +static enum Tfa98xx_Error +no_overload_function_available2(struct tfa_device *tfa) +{ + (void)tfa; + + return Tfa98xx_Error_Ok; +} + +/* tfa98xx_dsp_system_stable +* return: *ready = 1 when clocks are stable to allow DSP subsystem access +*/ +static enum Tfa98xx_Error tfa_dsp_system_stable(struct tfa_device *tfa, + int *ready) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short status; + int value; + + /* check the contents of the STATUS register */ + value = TFA_READ_REG(tfa, AREFS); + if (value < 0) { + error = -value; + *ready = 0; + _ASSERT(error); /* an error here can be fatal */ + return error; + } + status = (unsigned short)value; + + /* check AREFS and CLKS: not ready if either is clear */ + *ready = !((TFA_GET_BF_VALUE(tfa, AREFS, status) == 0) || + (TFA_GET_BF_VALUE(tfa, CLKS, status) == 0)); + + return error; +} + +/* tfa98xx_toggle_mtp_clock + * Allows to stop clock for MTP/FAim needed for PLMA5505 */ +static enum Tfa98xx_Error tfa_faim_protect(struct tfa_device *tfa, int state) +{ + (void)tfa; + (void)state; + + return Tfa98xx_Error_Ok; +} + +/** Set internal oscillator into power down mode. + * + * This function is a worker for tfa98xx_set_osc_powerdown(). + * + * @param[in] tfa device description structure + * @param[in] state new state 0 - oscillator is on, 1 oscillator is off. + * + * @return Tfa98xx_Error_Ok when successfull, error otherwise. + */ +static enum Tfa98xx_Error tfa_set_osc_powerdown(struct tfa_device *tfa, + int state) +{ + /* This function has no effect in general case, only for tfa9912 */ + (void)tfa; + (void)state; + + return Tfa98xx_Error_Ok; +} + +static enum Tfa98xx_Error tfa_dsp_reset(struct tfa_device *tfa, int state) +{ + /* generic function */ + TFA_SET_BF_VOLATILE(tfa, RST, (uint16_t)state); + + return Tfa98xx_Error_Ok; +} + +int tfa_set_swprofile(struct tfa_device *tfa, unsigned short new_value) +{ + int mtpk, active_value = tfa->profile; + + /* Also set the new value in the struct */ + tfa->profile = new_value - 1; + + /* for TFA1 devices */ + /* it's in MTP shadow, so unlock if not done already */ + mtpk = TFA_GET_BF(tfa, MTPK); /* get current key */ + TFA_SET_BF_VOLATILE(tfa, MTPK, 0x5a); + TFA_SET_BF_VOLATILE(tfa, SWPROFIL, new_value); /* set current profile */ + TFA_SET_BF_VOLATILE(tfa, MTPK, (uint16_t)mtpk); /* restore key */ + + return active_value; +} + +static int tfa_get_swprofile(struct tfa_device *tfa) +{ + return TFA_GET_BF(tfa, SWPROFIL) - 1; +} + +static int tfa_set_swvstep(struct tfa_device *tfa, unsigned short new_value) +{ + int mtpk, active_value = tfa->vstep; + + /* Also set the new value in the struct */ + tfa->vstep = new_value - 1; + + /* for TFA1 devices */ + /* it's in MTP shadow, so unlock if not done already */ + mtpk = TFA_GET_BF(tfa, MTPK); /* get current key */ + TFA_SET_BF_VOLATILE(tfa, MTPK, 0x5a); + TFA_SET_BF_VOLATILE(tfa, SWVSTEP, new_value); /* set current vstep */ + TFA_SET_BF_VOLATILE(tfa, MTPK, (uint16_t)mtpk); /* restore key */ + + return active_value; +} + +static int tfa_get_swvstep(struct tfa_device *tfa) +{ + int value = 0; + /* Set the new value in the hw register */ + value = TFA_GET_BF(tfa, SWVSTEP); + + /* Also set the new value in the struct */ + tfa->vstep = value; + + return value - 1; /* invalid if 0 */ +} + +static int tfa_get_mtpb(struct tfa_device *tfa) +{ + int value = 0; + + /* Set the new value in the hw register */ + value = TFA_GET_BF(tfa, MTPB); + + return value; +} + +static enum Tfa98xx_Error tfa_set_mute_nodsp(struct tfa_device *tfa, int mute) +{ + (void)tfa; + (void)mute; + + return Tfa98xx_Error_Ok; +} + +void set_ops_defaults(struct tfa_device_ops *ops) +{ + /* defaults */ + ops->reg_read = tfa98xx_read_register16; + ops->reg_write = tfa98xx_write_register16; + ops->mem_read = tfa98xx_dsp_read_mem; + ops->mem_write = tfa98xx_dsp_write_mem_word; + ops->dsp_msg = tfa_dsp_msg; + ops->dsp_msg_read = tfa_dsp_msg_read; + ops->dsp_write_tables = no_overload_function_available; + ops->dsp_reset = tfa_dsp_reset; + ops->dsp_system_stable = tfa_dsp_system_stable; + ops->auto_copy_mtp_to_iic = no_overload_function_available2; + ops->factory_trimmer = no_overload_function_available2; + ops->set_swprof = tfa_set_swprofile; + ops->get_swprof = tfa_get_swprofile; + ops->set_swvstep = tfa_set_swvstep; + ops->get_swvstep = tfa_get_swvstep; + ops->get_mtpb = tfa_get_mtpb; + ops->set_mute = tfa_set_mute_nodsp; + ops->faim_protect = tfa_faim_protect; + ops->set_osc_powerdown = tfa_set_osc_powerdown; +} + +/***********************************************************************************/ +/* no TFA + * external DSP SB instance */ +/***********************************************************************************/ +static short tfanone_swvstep, swprof; //TODO emulate in hal plugin +static enum Tfa98xx_Error tfanone_dsp_system_stable(struct tfa_device *tfa, + int *ready) +{ + (void)tfa; /* suppress warning */ + *ready = 1; /* assume always ready */ + + return Tfa98xx_Error_Ok; +} + +static int tfanone_set_swprofile(struct tfa_device *tfa, + unsigned short new_value) +{ + int active_value = tfa_dev_get_swprof(tfa); + + /* Set the new value in the struct */ + tfa->profile = new_value - 1; + + /* Set the new value in the hw register */ + swprof = new_value; + + return active_value; +} + +static int tfanone_get_swprofile(struct tfa_device *tfa) +{ + (void)tfa; /* suppress warning */ + return swprof; +} + +static int tfanone_set_swvstep(struct tfa_device *tfa, unsigned short new_value) +{ + /* Set the new value in the struct */ + tfa->vstep = new_value - 1; + + /* Set the new value in the hw register */ + tfanone_swvstep = new_value; + + return new_value; +} + +static int tfanone_get_swvstep(struct tfa_device *tfa) +{ + (void)tfa; /* suppress warning */ + return tfanone_swvstep; +} + +void tfanone_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->dsp_system_stable = tfanone_dsp_system_stable; + ops->set_swprof = tfanone_set_swprofile; + ops->get_swprof = tfanone_get_swprofile; + ops->set_swvstep = tfanone_set_swvstep; + ops->get_swvstep = tfanone_get_swvstep; +} + +/***********************************************************************************/ +/* TFA9912 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9912_faim_protect(struct tfa_device *tfa, + int status) +{ + enum Tfa98xx_Error ret = Tfa98xx_Error_Fail; + + if (tfa) { + if (status == 0 || status == 1) { + ret = -(tfa_set_bf(tfa, TFA9912_BF_SSFAIME, + (uint16_t)status)); + } + } + + return ret; +} + +static enum Tfa98xx_Error tfa9912_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short value, xor; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* Unlock keys to write settings */ + error = reg_write(tfa, 0x0F, 0x5A6B); + error = reg_read(tfa, 0xFB, &value); + xor = value ^ 0x005A; + error = reg_write(tfa, 0xA0, xor); + + /* The optimal settings */ + if (tfa->rev == 0x1a13) { + /* ----- generated code start ----- */ + /* ----- version 1.41 ----- */ + reg_write(tfa, 0x00, 0x0255); //POR=0x0245 + reg_write(tfa, 0x01, 0x838a); //POR=0x83ca + reg_write(tfa, 0x02, 0x2dc8); //POR=0x2828 + reg_write(tfa, 0x05, 0x762a); //POR=0x766a + reg_write(tfa, 0x22, 0x543c); //POR=0x545c + reg_write(tfa, 0x26, 0x0100); //POR=0x0010 + reg_write(tfa, 0x51, 0x0000); //POR=0x0080 + reg_write(tfa, 0x52, 0x551c); //POR=0x1afc + reg_write(tfa, 0x53, 0x003e); //POR=0x001e + reg_write(tfa, 0x61, 0x000c); //POR=0x0018 + reg_write(tfa, 0x63, 0x0a96); //POR=0x0a9a + reg_write(tfa, 0x65, 0x0a82); //POR=0x0a8b + reg_write(tfa, 0x66, 0x0701); //POR=0x0700 + reg_write(tfa, 0x6c, 0x00d5); //POR=0x02d5 + reg_write(tfa, 0x70, 0x26f8); //POR=0x06e0 + reg_write(tfa, 0x71, 0x3074); //POR=0x2074 + reg_write(tfa, 0x75, 0x4484); //POR=0x4585 + reg_write(tfa, 0x76, 0x72ea); //POR=0x54a2 + reg_write(tfa, 0x83, 0x0716); //POR=0x0617 + reg_write(tfa, 0x89, 0x0013); //POR=0x0014 + reg_write(tfa, 0xb0, 0x4c08); //POR=0x4c00 + reg_write( + tfa, 0xc6, + 0x004e); //POR=0x000e /* PLMA5539: Please make sure bit 6 is always on! */ + /* ----- generated code end ----- */ + + /* PLMA5505: MTP key open makes vulanable for MTP corruption */ + tfa9912_faim_protect(tfa, 0); + } else { + pr_info("Warning: Optimal settings not found for device with revid = 0x%x \n", + tfa->rev); + } + + return error; +} + +static enum Tfa98xx_Error tfa9912_tfa_dsp_write_tables(struct tfa_device *tfa, + int sample_rate) +{ + unsigned char buffer[15] = { 0 }; + int size = 15 * sizeof(char); + + /* Write the fractional delay in the hardware register 'cs_frac_delay' */ + switch (sample_rate) { + case 0: /* 8kHz */ + TFA_SET_BF(tfa, FRACTDEL, 40); + break; + case 1: /* 11.025KHz */ + TFA_SET_BF(tfa, FRACTDEL, 38); + break; + case 2: /* 12kHz */ + TFA_SET_BF(tfa, FRACTDEL, 37); + break; + case 3: /* 16kHz */ + TFA_SET_BF(tfa, FRACTDEL, 59); + break; + case 4: /* 22.05KHz */ + TFA_SET_BF(tfa, FRACTDEL, 56); + break; + case 5: /* 24kHz */ + TFA_SET_BF(tfa, FRACTDEL, 56); + break; + case 6: /* 32kHz */ + TFA_SET_BF(tfa, FRACTDEL, 52); + break; + case 7: /* 44.1kHz */ + TFA_SET_BF(tfa, FRACTDEL, 48); + break; + case 8: + default: /* 48kHz */ + TFA_SET_BF(tfa, FRACTDEL, 46); + break; + } + + /* First copy the msg_id to the buffer */ + buffer[0] = (uint8_t)0; + buffer[1] = (uint8_t)MODULE_FRAMEWORK + 128; + buffer[2] = (uint8_t)FW_PAR_ID_SET_SENSES_DELAY; + + /* Required for all FS exept 8kHz (8kHz is all zero) */ + if (sample_rate != 0) { + buffer[5] = 1; /* Vdelay_P */ + buffer[8] = 0; /* Idelay_P */ + buffer[11] = 1; /* Vdelay_S */ + buffer[14] = 0; /* Idelay_S */ + } + + /* send SetSensesDelay msg */ + return dsp_msg(tfa, size, (char *)buffer); +} + +static enum Tfa98xx_Error tfa9912_factory_trimmer(struct tfa_device *tfa) +{ + unsigned short currentValue, delta; + int result; + + /* Factory trimming for the Boost converter */ + /* check if there is a correction needed */ + result = TFA_GET_BF(tfa, DCMCCAPI); + if (result) { + /* Get currentvalue of DCMCC and the Delta value */ + currentValue = (unsigned short)TFA_GET_BF(tfa, DCMCC); + delta = (unsigned short)TFA_GET_BF(tfa, USERDEF); + + /* check the sign bit (+/-) */ + result = TFA_GET_BF(tfa, DCMCCSB); + if (result == 0) { + /* Do not exceed the maximum value of 15 */ + if (currentValue + delta < 15) { + TFA_SET_BF_VOLATILE(tfa, DCMCC, + currentValue + delta); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: %d \n", + currentValue + delta); + } else { + TFA_SET_BF_VOLATILE(tfa, DCMCC, 15); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: 15 \n"); + } + } else if (result == 1) { + /* Do not exceed the minimum value of 0 */ + if (currentValue - delta > 0) { + TFA_SET_BF_VOLATILE(tfa, DCMCC, + currentValue - delta); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: %d \n", + currentValue - delta); + } else { + TFA_SET_BF_VOLATILE(tfa, DCMCC, 0); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: 0 \n"); + } + } + } + + return Tfa98xx_Error_Ok; +} + +static enum Tfa98xx_Error tfa9912_auto_copy_mtp_to_iic(struct tfa_device *tfa) +{ + /* Set auto_copy_mtp_to_iic (bit 5 of A3) to 1. Workaround for 72, 88 and 9912/9892(see PLMA5290) */ + return reg_write(tfa, 0xA3, 0x20); +} + +static int tfa9912_set_swprofile(struct tfa_device *tfa, + unsigned short new_value) +{ + int active_value = tfa_dev_get_swprof(tfa); + + /* Set the new value in the struct */ + tfa->profile = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9912_BF_SWPROFIL, new_value); + + return active_value; +} + +static int tfa9912_get_swprofile(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9912_BF_SWPROFIL) - 1; +} + +static int tfa9912_set_swvstep(struct tfa_device *tfa, unsigned short new_value) +{ + /* Set the new value in the struct */ + tfa->vstep = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9912_BF_SWVSTEP, new_value); + + return new_value; +} + +static int tfa9912_get_swvstep(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9912_BF_SWVSTEP) - 1; +} + +static enum Tfa98xx_Error tfa9912_set_mute(struct tfa_device *tfa, int mute) +{ + tfa_set_bf(tfa, TFA9912_BF_CFSM, (const uint16_t)mute); + + return Tfa98xx_Error_Ok; +} + +/* Maksimum value for combination of boost_voltage and vout calibration offset (see PLMA5322, PLMA5528). */ +#define TFA9912_VBOOST_MAX 57 +#define TFA9912_CALIBR_BOOST_MAX 63 +#define TFA9912_DCDCCNT6_REG (TFA9912_BF_DCVOF >> 8) +#define TFA9912_CALIBR_REG 0xf1 + +static uint16_t tfa9912_vboost_fixup(struct tfa_device *tfa, uint16_t dcdc_cnt6) +{ + unsigned short cal_offset; + unsigned short boost_v_1st, boost_v_2nd; + uint16_t new_dcdc_cnt6; + + /* Get current calibr_vout_offset, this register is not supported by bitfields */ + reg_read(tfa, TFA9912_CALIBR_REG, &cal_offset); + cal_offset = (cal_offset & 0x001f); + new_dcdc_cnt6 = dcdc_cnt6; + + /* Get current boost_volatage values */ + boost_v_1st = tfa_get_bf_value(TFA9912_BF_DCVOF, new_dcdc_cnt6); + boost_v_2nd = tfa_get_bf_value(TFA9912_BF_DCVOS, new_dcdc_cnt6); + + /* Check boost voltages */ + if (boost_v_1st > TFA9912_VBOOST_MAX) + boost_v_1st = TFA9912_VBOOST_MAX; + + if (boost_v_2nd > TFA9912_VBOOST_MAX) + boost_v_2nd = TFA9912_VBOOST_MAX; + + /* Recalculate values, max for the sum is TFA9912_CALIBR_BOOST_MAX */ + if (boost_v_1st + cal_offset > TFA9912_CALIBR_BOOST_MAX) + boost_v_1st = TFA9912_CALIBR_BOOST_MAX - cal_offset; + + if (boost_v_2nd + cal_offset > TFA9912_CALIBR_BOOST_MAX) + boost_v_2nd = TFA9912_CALIBR_BOOST_MAX - cal_offset; + + tfa_set_bf_value(TFA9912_BF_DCVOF, boost_v_1st, &new_dcdc_cnt6); + tfa_set_bf_value(TFA9912_BF_DCVOS, boost_v_2nd, &new_dcdc_cnt6); + + /* Change register value only when it's neccesary */ + if (new_dcdc_cnt6 != dcdc_cnt6) { + if (tfa->verbose) + pr_debug( + "tfa9912: V boost fixup applied. Old 0x%04x, new 0x%04x\n", + dcdc_cnt6, new_dcdc_cnt6); + dcdc_cnt6 = new_dcdc_cnt6; + } + + return dcdc_cnt6; +} + +/* PLMA5322, PLMA5528 - Limit values of DCVOS and DCVOF to range specified in datasheet. */ +enum Tfa98xx_Error tfa9912_reg_write(struct tfa_device *tfa, + unsigned char subaddress, + unsigned short value) +{ + if (subaddress == TFA9912_DCDCCNT6_REG) { + /* Correct V boost (first and secondary) to ensure 12V is not exceeded. */ + value = tfa9912_vboost_fixup(tfa, value); + } + + return tfa98xx_write_register16(tfa, subaddress, value); +} + +/** Set internal oscillator into power down mode for TFA9912. +* +* This function is a worker for tfa98xx_set_osc_powerdown(). +* +* @param[in] tfa device description structure +* @param[in] state new state 0 - oscillator is on, 1 oscillator is off. +* +* @return Tfa98xx_Error_Ok when successfull, error otherwise. +*/ +static enum Tfa98xx_Error tfa9912_set_osc_powerdown(struct tfa_device *tfa, + int state) +{ + if (state == 1 || state == 0) { + return -tfa_set_bf(tfa, TFA9912_BF_MANAOOSC, (uint16_t)state); + } + + return Tfa98xx_Error_Bad_Parameter; +} + +void tfa9912_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9912_specific; + /* PLMA5322, PLMA5528 - Limits values of DCVOS and DCVOF. */ + ops->reg_write = tfa9912_reg_write; + ops->dsp_write_tables = tfa9912_tfa_dsp_write_tables; + ops->factory_trimmer = tfa9912_factory_trimmer; + ops->auto_copy_mtp_to_iic = tfa9912_auto_copy_mtp_to_iic; + ops->set_swprof = tfa9912_set_swprofile; + ops->get_swprof = tfa9912_get_swprofile; + ops->set_swvstep = tfa9912_set_swvstep; + ops->get_swvstep = tfa9912_get_swvstep; + ops->set_mute = tfa9912_set_mute; + ops->faim_protect = tfa9912_faim_protect; + ops->set_osc_powerdown = tfa9912_set_osc_powerdown; +} + +/***********************************************************************************/ +/* TFA9872 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9872_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + uint16_t MANAOOSC = 0x0140; /* version 17 */ + unsigned short value, xor; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* Unlock key 1 and 2 */ + error = reg_write(tfa, 0x0F, 0x5A6B); + error = reg_read(tfa, 0xFB, &value); + xor = value ^ 0x005A; + error = reg_write(tfa, 0xA0, xor); + tfa98xx_key2(tfa, 0); + + switch (tfa->rev) { + case 0x1a72: + case 0x2a72: + /* ----- generated code start ----- */ + /* ----- version 26 ----- */ + reg_write(tfa, 0x00, 0x1801); //POR=0x0001 + reg_write(tfa, 0x02, 0x2dc8); //POR=0x2028 + reg_write(tfa, 0x20, 0x0890); //POR=0x2890 + reg_write(tfa, 0x22, 0x043c); //POR=0x045c + reg_write(tfa, 0x51, 0x0000); //POR=0x0080 + reg_write(tfa, 0x52, 0x1a1c); //POR=0x7ae8 + reg_write(tfa, 0x58, 0x161c); //POR=0x101c + reg_write(tfa, 0x61, 0x0198); //POR=0x0000 + reg_write(tfa, 0x65, 0x0a8b); //POR=0x0a9a + reg_write(tfa, 0x70, 0x07f5); //POR=0x06e6 + reg_write(tfa, 0x74, 0xcc84); //POR=0xd823 + reg_write(tfa, 0x82, 0x01ed); //POR=0x000d + reg_write(tfa, 0x83, 0x0014); //POR=0x0013 + reg_write(tfa, 0x84, 0x0021); //POR=0x0020 + reg_write(tfa, 0x85, 0x0001); //POR=0x0003 + /* ----- generated code end ----- */ + break; + case 0x1b72: + case 0x2b72: + case 0x3b72: + /* ----- generated code start ----- */ + /* ----- TFA9872 Probus Registers map N1B2 - Version 21 (10/19/2016) ----- */ + reg_write(tfa, 0x02, 0x2dc8); //POR=0x2828 + reg_write(tfa, 0x20, 0x0890); //POR=0x2890 + reg_write(tfa, 0x22, 0x043c); //POR=0x045c + reg_write(tfa, 0x23, 0x0001); //POR=0x0003 + reg_write(tfa, 0x51, 0x0000); //POR=0x0080 + reg_write(tfa, 0x52, 0x5a1c); //POR=0x7a08 + reg_write(tfa, 0x61, 0x0198); //POR=0x0000 + reg_write(tfa, 0x63, 0x0a9a); //POR=0x0a93 + reg_write(tfa, 0x65, 0x0a82); //POR=0x0a8d + reg_write(tfa, 0x6f, 0x01e3); //POR=0x02e4 + reg_write(tfa, 0x70, 0x06fd); //POR=0x06e6 + reg_write(tfa, 0x71, 0x307e); //POR=0x207e + reg_write(tfa, 0x74, 0xcc84); //POR=0xd913 + reg_write(tfa, 0x75, 0x1132); //POR=0x118a + reg_write(tfa, 0x82, 0x01ed); //POR=0x000d + reg_write(tfa, 0x83, 0x001a); //POR=0x0013 + /* ----- generated code end ----- */ + break; + default: + pr_info("\nWarning: Optimal settings not found for device with revid = 0x%x \n", + tfa->rev); + break; + } + + /* Turn off the osc1m to save power: PLMA4928 */ + error = tfa_set_bf(tfa, MANAOOSC, 1); + + /* Bypass OVP by setting bit 3 from register 0xB0 (bypass_ovp=1): PLMA5258 */ + error = reg_read(tfa, 0xB0, &value); + value |= 1 << 3; + error = reg_write(tfa, 0xB0, value); + + return error; +} + +static enum Tfa98xx_Error tfa9872_auto_copy_mtp_to_iic(struct tfa_device *tfa) +{ + /* Set auto_copy_mtp_to_iic (bit 5 of A3) to 1. Workaround for 72 and 88 (see PLMA5290) */ + return reg_write(tfa, 0xA3, 0x20); +} + +static int tfa9872_set_swprofile(struct tfa_device *tfa, + unsigned short new_value) +{ + int active_value = tfa_dev_get_swprof(tfa); + + /* Set the new value in the struct */ + tfa->profile = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9872_BF_SWPROFIL, new_value); + + return active_value; +} + +static int tfa9872_get_swprofile(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9872_BF_SWPROFIL) - 1; +} + +static int tfa9872_set_swvstep(struct tfa_device *tfa, unsigned short new_value) +{ + /* Set the new value in the struct */ + tfa->vstep = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9872_BF_SWVSTEP, new_value); + + return new_value; +} + +static int tfa9872_get_swvstep(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9872_BF_SWVSTEP) - 1; +} + +void tfa9872_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9872_specific; + ops->auto_copy_mtp_to_iic = tfa9872_auto_copy_mtp_to_iic; + ops->set_swprof = tfa9872_set_swprofile; + ops->get_swprof = tfa9872_get_swprofile; + ops->set_swvstep = tfa9872_set_swvstep; + ops->get_swvstep = tfa9872_get_swvstep; + ops->set_mute = tfa_set_mute_nodsp; +} + +/***********************************************************************************/ +/* TFA9874 */ +/***********************************************************************************/ + +static enum Tfa98xx_Error tfa9874_faim_protect(struct tfa_device *tfa, + int status) +{ + enum Tfa98xx_Error ret = Tfa98xx_Error_Ok; + /* 0b = FAIM protection enabled 1b = FAIM protection disabled*/ + ret = tfa_set_bf_volatile(tfa, TFA9874_BF_OPENMTP, (uint16_t)(status)); + return ret; +} + +static enum Tfa98xx_Error tfa9874_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short value, xor; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* Unlock key 1 and 2 */ + error = reg_write(tfa, 0x0F, 0x5A6B); + error = reg_read(tfa, 0xFB, &value); + xor = value ^ 0x005A; + error = reg_write(tfa, 0xA0, xor); + tfa98xx_key2(tfa, 0); + + switch (tfa->rev) { + case 0x0a74: /* Initial revision ID */ + /* ----- generated code start ----- */ + /* V25 */ + reg_write(tfa, 0x02, 0x22a8); //POR=0x25c8 + reg_write(tfa, 0x51, 0x0020); //POR=0x0000 + reg_write(tfa, 0x52, 0x57dc); //POR=0x56dc + reg_write(tfa, 0x58, 0x16a4); //POR=0x1614 + reg_write(tfa, 0x61, 0x0110); //POR=0x0198 + reg_write(tfa, 0x66, 0x0701); //POR=0x0700 + reg_write(tfa, 0x6f, 0x00a3); //POR=0x01a3 + reg_write(tfa, 0x70, 0x07f8); //POR=0x06f8 + reg_write(tfa, 0x73, 0x0007); //POR=0x0005 + reg_write(tfa, 0x74, 0x5068); //POR=0xcc80 + reg_write(tfa, 0x75, 0x0d28); //POR=0x1138 + reg_write(tfa, 0x83, 0x0594); //POR=0x061a + reg_write(tfa, 0x84, 0x0001); //POR=0x0021 + reg_write(tfa, 0x85, 0x0001); //POR=0x0003 + reg_write(tfa, 0x88, 0x0000); //POR=0x0002 + reg_write(tfa, 0xc4, 0x2001); //POR=0x0001 + /* ----- generated code end ----- */ + break; + case 0x0b74: + /* ----- generated code start ----- */ + /* V1.6 */ + reg_write(tfa, 0x02, 0x22a8); //POR=0x25c8 + reg_write(tfa, 0x51, 0x0020); //POR=0x0000 + reg_write(tfa, 0x52, 0x57dc); //POR=0x56dc + reg_write(tfa, 0x58, 0x16a4); //POR=0x1614 + reg_write(tfa, 0x61, 0x0110); //POR=0x0198 + reg_write(tfa, 0x66, 0x0701); //POR=0x0700 + reg_write(tfa, 0x6f, 0x00a3); //POR=0x01a3 + reg_write(tfa, 0x70, 0x07f8); //POR=0x06f8 + reg_write(tfa, 0x73, 0x0047); //POR=0x0045 + reg_write(tfa, 0x74, 0x5068); //POR=0xcc80 + reg_write(tfa, 0x75, 0x0d28); //POR=0x1138 + reg_write(tfa, 0x83, 0x0595); //POR=0x061a + reg_write(tfa, 0x84, 0x0001); //POR=0x0021 + reg_write(tfa, 0x85, 0x0001); //POR=0x0003 + reg_write(tfa, 0x88, 0x0000); //POR=0x0002 + reg_write(tfa, 0xc4, 0x2001); //POR=0x0001 + /* ----- generated code end ----- */ + break; + case 0x0c74: + /* ----- generated code start ----- */ + /* V1.14 */ + reg_write(tfa, 0x02, 0x22c8); //POR=0x25c8 + reg_write(tfa, 0x52, 0x57dc); //POR=0x56dc + reg_write(tfa, 0x53, 0x003e); //POR=0x001e + reg_write(tfa, 0x56, 0x0400); //POR=0x0600 + reg_write(tfa, 0x61, 0x0110); //POR=0x0198 + reg_write(tfa, 0x6f, 0x00a5); //POR=0x01a3 + reg_write(tfa, 0x70, 0x07f8); //POR=0x06f8 + reg_write(tfa, 0x73, 0x0047); //POR=0x0045 + reg_write(tfa, 0x74, 0x5098); //POR=0xcc80 + reg_write(tfa, 0x75, 0x8d28); //POR=0x1138 + reg_write(tfa, 0x80, 0x0000); //POR=0x0003 + reg_write(tfa, 0x83, 0x0799); //POR=0x061a + reg_write(tfa, 0x84, 0x0081); //POR=0x0021 + /* ----- generated code end ----- */ + break; + default: + pr_info("\nWarning: Optimal settings not found for device with revid = 0x%x \n", + tfa->rev); + break; + } + + return error; +} + +static int tfa9874_set_swprofile(struct tfa_device *tfa, + unsigned short new_value) +{ + int active_value = tfa_dev_get_swprof(tfa); + + /* Set the new value in the struct */ + tfa->profile = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9874_BF_SWPROFIL, new_value); + + return active_value; +} + +static int tfa9874_get_swprofile(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9874_BF_SWPROFIL) - 1; +} + +static int tfa9874_set_swvstep(struct tfa_device *tfa, unsigned short new_value) +{ + /* Set the new value in the struct */ + tfa->vstep = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9874_BF_SWVSTEP, new_value); + + return new_value; +} + +static int tfa9874_get_swvstep(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9874_BF_SWVSTEP) - 1; +} + +/* tfa98xx_dsp_system_stable +* return: *ready = 1 when clocks are stable to allow DSP subsystem access +*/ +static enum Tfa98xx_Error tfa9874_dsp_system_stable(struct tfa_device *tfa, + int *ready) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + /* check CLKS: ready if set */ + *ready = tfa_get_bf(tfa, TFA9874_BF_CLKS) == 1; + + return error; +} + +static int tfa9874_get_mtpb(struct tfa_device *tfa) +{ + int value; + value = tfa_get_bf(tfa, TFA9874_BF_MTPB); + return value; +} + +void tfa9874_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9874_specific; + ops->set_swprof = tfa9874_set_swprofile; + ops->get_swprof = tfa9874_get_swprofile; + ops->set_swvstep = tfa9874_set_swvstep; + ops->get_swvstep = tfa9874_get_swvstep; + ops->dsp_system_stable = tfa9874_dsp_system_stable; + ops->faim_protect = tfa9874_faim_protect; + ops->get_mtpb = tfa9874_get_mtpb; + ops->set_mute = tfa_set_mute_nodsp; +} + +/***********************************************************************************/ +/* TFA9888 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9888_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short value, xor; + int patch_version; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* Unlock keys to write settings */ + error = reg_write(tfa, 0x0F, 0x5A6B); + error = reg_read(tfa, 0xFB, &value); + xor = value ^ 0x005A; + error = reg_write(tfa, 0xA0, xor); + + /* Only N1C2 is supported */ + /* ----- generated code start ----- */ + /* --------- Version v1 ---------- */ + if (tfa->rev == 0x2c88) { + reg_write(tfa, 0x00, 0x164d); //POR=0x064d + reg_write(tfa, 0x01, 0x828b); //POR=0x92cb + reg_write(tfa, 0x02, 0x1dc8); //POR=0x1828 + reg_write(tfa, 0x0e, 0x0080); //POR=0x0000 + reg_write(tfa, 0x20, 0x089e); //POR=0x0890 + reg_write(tfa, 0x22, 0x543c); //POR=0x545c + reg_write(tfa, 0x23, 0x0006); //POR=0x0000 + reg_write(tfa, 0x24, 0x0014); //POR=0x0000 + reg_write(tfa, 0x25, 0x000a); //POR=0x0000 + reg_write(tfa, 0x26, 0x0100); //POR=0x0000 + reg_write(tfa, 0x28, 0x1000); //POR=0x0000 + reg_write(tfa, 0x51, 0x0000); //POR=0x00c0 + reg_write(tfa, 0x52, 0xfafe); //POR=0xbaf6 + reg_write(tfa, 0x70, 0x3ee4); //POR=0x3ee6 + reg_write(tfa, 0x71, 0x1074); //POR=0x3074 + reg_write(tfa, 0x83, 0x0014); //POR=0x0013 + /* ----- generated code end ----- */ + } else { + pr_info("Warning: Optimal settings not found for device with revid = 0x%x \n", + tfa->rev); + } + + patch_version = tfa_cnt_get_patch_version(tfa); + if (patch_version >= 0x060401) + tfa->partial_enable = 1; + + return error; +} + +static enum Tfa98xx_Error tfa9888_tfa_dsp_write_tables(struct tfa_device *tfa, + int sample_rate) +{ + unsigned char buffer[15] = { 0 }; + int size = 15 * sizeof(char); + + /* Write the fractional delay in the hardware register 'cs_frac_delay' */ + switch (sample_rate) { + case 0: /* 8kHz */ + TFA_SET_BF(tfa, FRACTDEL, 40); + break; + case 1: /* 11.025KHz */ + TFA_SET_BF(tfa, FRACTDEL, 38); + break; + case 2: /* 12kHz */ + TFA_SET_BF(tfa, FRACTDEL, 37); + break; + case 3: /* 16kHz */ + TFA_SET_BF(tfa, FRACTDEL, 59); + break; + case 4: /* 22.05KHz */ + TFA_SET_BF(tfa, FRACTDEL, 56); + break; + case 5: /* 24kHz */ + TFA_SET_BF(tfa, FRACTDEL, 56); + break; + case 6: /* 32kHz */ + TFA_SET_BF(tfa, FRACTDEL, 52); + break; + case 7: /* 44.1kHz */ + TFA_SET_BF(tfa, FRACTDEL, 48); + break; + case 8: + default: /* 48kHz */ + TFA_SET_BF(tfa, FRACTDEL, 46); + break; + } + + /* First copy the msg_id to the buffer */ + buffer[0] = (uint8_t)0; + buffer[1] = (uint8_t)MODULE_FRAMEWORK + 128; + buffer[2] = (uint8_t)FW_PAR_ID_SET_SENSES_DELAY; + + /* Required for all FS exept 8kHz (8kHz is all zero) */ + if (sample_rate != 0) { + buffer[5] = 1; /* Vdelay_P */ + buffer[8] = 0; /* Idelay_P */ + buffer[11] = 1; /* Vdelay_S */ + buffer[14] = 0; /* Idelay_S */ + } + + /* send SetSensesDelay msg */ + return dsp_msg(tfa, size, (char *)buffer); +} + +static enum Tfa98xx_Error tfa9888_auto_copy_mtp_to_iic(struct tfa_device *tfa) +{ + /* Set auto_copy_mtp_to_iic (bit 5 of A3) to 1. Workaround for 72 and 88 (see PLMA5290) */ + return reg_write(tfa, 0xA3, 0x20); +} + +static enum Tfa98xx_Error tfa9888_factory_trimmer(struct tfa_device *tfa) +{ + unsigned short currentValue, delta; + int result; + + /* Factory trimming for the Boost converter */ + /* check if there is a correction needed */ + result = TFA_GET_BF(tfa, DCMCCAPI); + if (result) { + /* Get currentvalue of DCMCC and the Delta value */ + currentValue = (unsigned short)TFA_GET_BF(tfa, DCMCC); + delta = (unsigned short)TFA_GET_BF(tfa, USERDEF); + + /* check the sign bit (+/-) */ + result = TFA_GET_BF(tfa, DCMCCSB); + if (result == 0) { + /* Do not exceed the maximum value of 15 */ + if (currentValue + delta < 15) { + TFA_SET_BF_VOLATILE(tfa, DCMCC, + currentValue + delta); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: %d \n", + currentValue + delta); + } else { + TFA_SET_BF_VOLATILE(tfa, DCMCC, 15); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: 15 \n"); + } + } else if (result == 1) { + /* Do not exceed the minimum value of 0 */ + if (currentValue - delta > 0) { + TFA_SET_BF_VOLATILE(tfa, DCMCC, + currentValue - delta); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: %d \n", + currentValue - delta); + } else { + TFA_SET_BF_VOLATILE(tfa, DCMCC, 0); + if (tfa->verbose) + pr_debug( + "Max coil current is set to: 0 \n"); + } + } + } + + return Tfa98xx_Error_Ok; +} + +static enum Tfa98xx_Error tfa9888_set_mute(struct tfa_device *tfa, int mute) +{ + TFA_SET_BF(tfa, CFSMR, (const uint16_t)mute); + TFA_SET_BF(tfa, CFSML, (const uint16_t)mute); + + return Tfa98xx_Error_Ok; +} + +void tfa9888_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9888_specific; + ops->dsp_write_tables = tfa9888_tfa_dsp_write_tables; + ops->auto_copy_mtp_to_iic = tfa9888_auto_copy_mtp_to_iic; + ops->factory_trimmer = tfa9888_factory_trimmer; + ops->set_mute = tfa9888_set_mute; +} + +/***********************************************************************************/ +/* TFA9896 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9896_faim_protect(struct tfa_device *tfa, + int status) +{ + enum Tfa98xx_Error ret = Tfa98xx_Error_Ok; + + if ((tfa->rev == 0x2b96) || (tfa->rev == 0x3b96)) { + ret = tfa_set_bf_volatile(tfa, TFA9896_BF_OPENMTP, + (uint16_t)status); + } + + return ret; +} + +/***********************************************************************************/ +/* TFA9896 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9896_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short check_value; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* all i2C registers must already set to default POR value */ + + /* $48:[3] - 1 ==> 0; iddqtestbst - default value changed. + * When Iddqtestbst is set to "0", the slewrate is reduced. + * This will lower the overshoot on IN-B to avoid NMOS damage of booster. + */ + if (tfa->rev == 0x1b96) { + /* ----- generated code start v17 ----- */ + reg_write(tfa, 0x06, 0x000b); //POR=0x0001 + reg_write(tfa, 0x07, 0x3e7f); //POR=0x1e7f + reg_write(tfa, 0x0a, 0x0d8a); //POR=0x0592 + reg_write(tfa, 0x48, 0x0300); //POR=0x0308 + reg_write(tfa, 0x88, 0x0100); //POR=0x0000 + /* ----- generated code end ----- */ + } else if (tfa->rev == 0x2b96) { + /* ----- generated code start ----- v1*/ + reg_write(tfa, 0x06, 0x000b); //POR=0x0001 + reg_write(tfa, 0x07, 0x3e7f); //POR=0x1e7f + reg_write(tfa, 0x0a, 0x0d8a); //POR=0x0592 + reg_write(tfa, 0x48, 0x0300); //POR=0x0308 + reg_write(tfa, 0x88, 0x0100); //POR=0x0000 + /* ----- generated code end ----- */ + } else if (tfa->rev == 0x3b96) { + /* ----- generated code start ----- v1*/ + reg_write(tfa, 0x06, 0x000b); //POR=0x0001 + reg_write(tfa, 0x07, 0x3e7f); //POR=0x1e7f + reg_write(tfa, 0x0a, 0x0d8a); //POR=0x0592 + reg_write(tfa, 0x48, 0x0300); //POR=0x0308 + reg_write(tfa, 0x88, 0x0100); //POR=0x0000 + /* ----- generated code end ----- */ + } + /* $49:[0] - 1 ==> 0; CLIP - default value changed. 0 means CLIPPER on */ + error = reg_read(tfa, 0x49, &check_value); + check_value &= ~0x1; + error = reg_write(tfa, 0x49, check_value); + return error; +} + +/* +* the int24 values for the vsfw delay table +*/ +static unsigned char tfa9896_vsfwdelay_table[] = { + 0, 0, 2, /* Index 0 - Current/Volt Fractional Delay for 8KHz */ + 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */ + 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */ + 0, 0, 2, /* Index 3 - Current/Volt Fractional Delay for 16KHz */ + 0, 0, 2, /* Index 4 - Current/Volt Fractional Delay for 22KHz */ + 0, 0, 2, /* Index 5 - Current/Volt Fractional Delay for 24KHz */ + 0, 0, 2, /* Index 6 - Current/Volt Fractional Delay for 32KHz */ + 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */ + 0, 0, 3 /* Index 8 - Current/Volt Fractional Delay for 48KHz */ +}; + +/* +* TODO make this tfa98xx +* Note that the former products write this table via the patch +* so moving this to the tfa98xx API requires also updating all patches +*/ +static enum Tfa98xx_Error +tfa9896_dsp_write_vsfwdelay_table(struct tfa_device *tfa) +{ + return tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, + TFA1_FW_PAR_ID_SET_CURRENT_DELAY, + sizeof(tfa9896_vsfwdelay_table), + tfa9896_vsfwdelay_table); +} + +/* +* The int24 values for the fracdelay table +* For now applicable only for 8 and 48 kHz +*/ +static unsigned char tfa9896_cvfracdelay_table[] = { + 0, 0, 51, /* Index 0 - Current/Volt Fractional Delay for 8KHz */ + 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */ + 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */ + 0, 0, 38, /* Index 3 - Current/Volt Fractional Delay for 16KHz */ + 0, 0, 34, /* Index 4 - Current/Volt Fractional Delay for 22KHz */ + 0, 0, 33, /* Index 5 - Current/Volt Fractional Delay for 24KHz */ + 0, 0, 11, /* Index 6 - Current/Volt Fractional Delay for 32KHz */ + 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */ + 0, 0, 62 /* Index 8 - Current/Volt Fractional Delay for 48KHz */ +}; + +static enum Tfa98xx_Error +tfa9896_dsp_write_cvfracdelay_table(struct tfa_device *tfa) +{ + return tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, + TFA1_FW_PAR_ID_SET_CURFRAC_DELAY, + sizeof(tfa9896_cvfracdelay_table), + tfa9896_cvfracdelay_table); + ; +} + +static enum Tfa98xx_Error tfa9896_tfa_dsp_write_tables(struct tfa_device *tfa, + int sample_rate) +{ + enum Tfa98xx_Error error; + + /* Not used for max1! */ + (void)sample_rate; + + error = tfa9896_dsp_write_vsfwdelay_table(tfa); + if (error == Tfa98xx_Error_Ok) { + error = tfa9896_dsp_write_cvfracdelay_table(tfa); + } + + return error; +} + +void tfa9896_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9896_specific; + ops->dsp_write_tables = tfa9896_tfa_dsp_write_tables; + ops->faim_protect = tfa9896_faim_protect; +} + +/***********************************************************************************/ +/* TFA9897 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9897_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short check_value; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* all i2C registers must already set to default POR value */ + + /* $48:[3] - 1 ==> 0; iddqtestbst - default value changed. + * When Iddqtestbst is set to "0", the slewrate is reduced. + * This will lower the overshoot on IN-B to avoid NMOS damage of booster */ + error = reg_write(tfa, 0x48, 0x0300); /* POR value = 0x308 */ + + /* $49:[0] - 1 ==> 0; CLIP - default value changed. 0 means CLIPPER on */ + error = reg_read(tfa, 0x49, &check_value); + check_value &= ~0x1; + error = reg_write(tfa, 0x49, check_value); + + return error; +} + +/* +* the int24 values for the vsfw delay table +*/ +static unsigned char tfa9897_vsfwdelay_table[] = { + 0, 0, 2, /* Index 0 - Current/Volt Fractional Delay for 8KHz */ + 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */ + 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */ + 0, 0, 2, /* Index 3 - Current/Volt Fractional Delay for 16KHz */ + 0, 0, 2, /* Index 4 - Current/Volt Fractional Delay for 22KHz */ + 0, 0, 2, /* Index 5 - Current/Volt Fractional Delay for 24KHz */ + 0, 0, 2, /* Index 6 - Current/Volt Fractional Delay for 32KHz */ + 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */ + 0, 0, 3 /* Index 8 - Current/Volt Fractional Delay for 48KHz */ +}; + +/* +* TODO make this tfa98xx +* Note that the former products write this table via the patch +* so moving this to the tfa98xx API requires also updating all patches +*/ +static enum Tfa98xx_Error +tfa9897_dsp_write_vsfwdelay_table(struct tfa_device *tfa) +{ + return tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, + TFA1_FW_PAR_ID_SET_CURRENT_DELAY, + sizeof(tfa9897_vsfwdelay_table), + tfa9897_vsfwdelay_table); + ; +} + +/* +* The int24 values for the fracdelay table +* For now applicable only for 8 and 48 kHz +*/ +static unsigned char tfa9897_cvfracdelay_table[] = { + 0, 0, 51, /* Index 0 - Current/Volt Fractional Delay for 8KHz */ + 0, 0, 0, /* Index 1 - Current/Volt Fractional Delay for 11KHz */ + 0, 0, 0, /* Index 2 - Current/Volt Fractional Delay for 12KHz */ + 0, 0, 38, /* Index 3 - Current/Volt Fractional Delay for 16KHz */ + 0, 0, 34, /* Index 4 - Current/Volt Fractional Delay for 22KHz */ + 0, 0, 33, /* Index 5 - Current/Volt Fractional Delay for 24KHz */ + 0, 0, 11, /* Index 6 - Current/Volt Fractional Delay for 32KHz */ + 0, 0, 2, /* Index 7 - Current/Volt Fractional Delay for 44KHz */ + 0, 0, 62 /* Index 8 - Current/Volt Fractional Delay for 48KHz */ +}; + +static enum Tfa98xx_Error +tfa9897_dsp_write_cvfracdelay_table(struct tfa_device *tfa) +{ + return tfa_dsp_cmd_id_write(tfa, MODULE_FRAMEWORK, + TFA1_FW_PAR_ID_SET_CURFRAC_DELAY, + sizeof(tfa9897_cvfracdelay_table), + tfa9897_cvfracdelay_table); + ; +} + +static enum Tfa98xx_Error tfa9897_tfa_dsp_write_tables(struct tfa_device *tfa, + int sample_rate) +{ + enum Tfa98xx_Error error; + + /* Not used for max1! */ + (void)sample_rate; + + error = tfa9897_dsp_write_vsfwdelay_table(tfa); + if (error == Tfa98xx_Error_Ok) { + error = tfa9897_dsp_write_cvfracdelay_table(tfa); + } + + return error; +} + +void tfa9897_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9897_specific; + ops->dsp_write_tables = tfa9897_tfa_dsp_write_tables; +} + +/***********************************************************************************/ +/* TFA9895 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9895_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + int result; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* all i2C registers are already set to default */ + + result = TFA_SET_BF(tfa, AMPE, 1); + if (result < 0) + return -result; + + /* some other registers must be set for optimal amplifier behaviour */ + reg_write(tfa, 0x05, 0x13AB); + reg_write(tfa, 0x06, 0x001F); + /* peak voltage protection is always on, but may be written */ + reg_write(tfa, 0x08, 0x3C4E); + /*TFA98XX_SYSCTRL_DCA=0*/ + reg_write(tfa, 0x09, 0x024D); + reg_write(tfa, 0x41, 0x0308); + error = reg_write(tfa, 0x49, 0x0E82); + + return error; +} + +void tfa9895_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9895_specific; +} + +/***********************************************************************************/ +/* TFA9891 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9891_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* ----- generated code start ----- */ + /* ----- version 18.0 ----- */ + reg_write(tfa, 0x09, 0x025d); //POR=0x024d + reg_write(tfa, 0x10, 0x0018); //POR=0x0024 + reg_write(tfa, 0x22, 0x0003); //POR=0x0023 + reg_write(tfa, 0x25, 0x0001); //POR=0x0000 + reg_write(tfa, 0x46, 0x0000); //POR=0x4000 + reg_write(tfa, 0x55, 0x3ffb); //POR=0x7fff + /* ----- generated code end ----- */ + + return error; +} + +void tfa9891_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9891_specific; +} + +/***********************************************************************************/ +/* TFA9890 */ +/***********************************************************************************/ +static enum Tfa98xx_Error tfa9890_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short regRead = 0; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* all i2C registers are already set to default for N1C2 */ + + /* some PLL registers must be set optimal for amplifier behaviour */ + error = reg_write(tfa, 0x40, 0x5a6b); + if (error) + return error; + reg_read(tfa, 0x59, ®Read); + regRead |= 0x3; + reg_write(tfa, 0x59, regRead); + error = reg_write(tfa, 0x40, 0x0000); + error = reg_write(tfa, 0x47, 0x7BE1); + + return error; +} + +/* +* Disable clock gating +*/ +static enum Tfa98xx_Error tfa9890_clockgating(struct tfa_device *tfa, int on) +{ + enum Tfa98xx_Error error; + unsigned short value; + + /* for TFA9890 temporarily disable clock gating when dsp reset is used */ + error = reg_read(tfa, TFA98XX_CURRENTSENSE4, &value); + if (error) + return error; + + if (Tfa98xx_Error_Ok == error) { + if (on) /* clock gating on - clear the bit */ + value &= ~TFA98XX_CURRENTSENSE4_CTRL_CLKGATECFOFF; + else /* clock gating off - set the bit */ + value |= TFA98XX_CURRENTSENSE4_CTRL_CLKGATECFOFF; + + error = reg_write(tfa, TFA98XX_CURRENTSENSE4, value); + } + + return error; +} + +/* +* Tfa9890_DspReset will deal with clock gating control in order +* to reset the DSP for warm state restart +*/ +static enum Tfa98xx_Error tfa9890_dsp_reset(struct tfa_device *tfa, int state) +{ + enum Tfa98xx_Error error; + + /* for TFA9890 temporarily disable clock gating + when dsp reset is used */ + tfa9890_clockgating(tfa, 0); + + TFA_SET_BF(tfa, RST, (uint16_t)state); + + /* clock gating restore */ + error = tfa9890_clockgating(tfa, 1); + + return error; +} + +/* + * Tfa9890_DspSystemStable will compensate for the wrong behavior of CLKS + * to determine if the DSP subsystem is ready for patch and config loading. + * + * A MTP calibration register is checked for non-zero. + * + * Note: This only works after i2c reset as this will clear the MTP contents. + * When we are configured then the DSP communication will synchronize access. + * + */ +static enum Tfa98xx_Error tfa9890_dsp_system_stable(struct tfa_device *tfa, + int *ready) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short status, mtp0; + int result, tries; + + /* check the contents of the STATUS register */ + result = TFA_READ_REG(tfa, AREFS); + if (result < 0) { + error = -result; + goto errorExit; + } + status = (unsigned short)result; + + /* if AMPS is set then we were already configured and running + * no need to check further + */ + *ready = (TFA_GET_BF_VALUE(tfa, AMPS, status) == 1); + if (*ready) /* if ready go back */ + return error; /* will be Tfa98xx_Error_Ok */ + + /* check AREFS and CLKS: not ready if either is clear */ + *ready = !((TFA_GET_BF_VALUE(tfa, AREFS, status) == 0) || + (TFA_GET_BF_VALUE(tfa, CLKS, status) == 0)); + if (!*ready) /* if not ready go back */ + return error; /* will be Tfa98xx_Error_Ok */ + + /* check MTPB + * mtpbusy will be active when the subsys copies MTP to I2C + * 2 times retry avoids catching this short mtpbusy active period + */ + for (tries = 2; tries > 0; tries--) { + result = TFA_GET_BF(tfa, MTPB); /*TODO_MTPB*/ + if (result < 0) { + error = -result; + goto errorExit; + } + status = (unsigned short)result; + + /* check the contents of the STATUS register */ + *ready = (result == 0); + if (*ready) /* if ready go on */ + break; + } + if (tries == 0) /* ready will be 0 if retries exausted */ + return Tfa98xx_Error_Ok; + + /* check the contents of MTP register for non-zero, + * this indicates that the subsys is ready */ + + error = reg_read(tfa, 0x84, &mtp0); + if (error) + goto errorExit; + + *ready = (mtp0 != 0); /* The MTP register written? */ + + return error; + +errorExit: + *ready = 0; + return error; +} + +void tfa9890_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9890_specific; + ops->dsp_reset = tfa9890_dsp_reset; + ops->dsp_system_stable = tfa9890_dsp_system_stable; +} + +/***********************************************************************************/ +/* TFA9894 */ +/***********************************************************************************/ +static int tfa9894_set_swprofile(struct tfa_device *tfa, + unsigned short new_value) +{ + int active_value = tfa_dev_get_swprof(tfa); + + /* Set the new value in the struct */ + tfa->profile = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9894_BF_SWPROFIL, new_value); + + return active_value; +} + +static int tfa9894_get_swprofile(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9894_BF_SWPROFIL) - 1; +} + +static int tfa9894_set_swvstep(struct tfa_device *tfa, unsigned short new_value) +{ + /* Set the new value in the struct */ + tfa->vstep = new_value - 1; + + /* Set the new value in the hw register */ + tfa_set_bf_volatile(tfa, TFA9894_BF_SWVSTEP, new_value); + + return new_value; +} + +static int tfa9894_get_swvstep(struct tfa_device *tfa) +{ + return tfa_get_bf(tfa, TFA9894_BF_SWVSTEP) - 1; +} + +static int tfa9894_get_mtpb(struct tfa_device *tfa) +{ + int value = 0; + + /* Set the new value in the hw register */ + value = tfa_get_bf(tfa, TFA9894_BF_MTPB); + + return value; +} + +/** Set internal oscillator into power down mode for TFA9894. +* +* This function is a worker for tfa98xx_set_osc_powerdown(). +* +* @param[in] tfa device description structure +* @param[in] state new state 0 - oscillator is on, 1 oscillator is off. +* +* @return Tfa98xx_Error_Ok when successfull, error otherwise. +*/ +static enum Tfa98xx_Error tfa9894_set_osc_powerdown(struct tfa_device *tfa, + int state) +{ + if (state == 1 || state == 0) { + return -tfa_set_bf(tfa, TFA9894_BF_MANAOOSC, (uint16_t)state); + } + + return Tfa98xx_Error_Bad_Parameter; +} + +static enum Tfa98xx_Error tfa9894_faim_protect(struct tfa_device *tfa, + int status) +{ + enum Tfa98xx_Error ret = Tfa98xx_Error_Ok; + /* 0b = FAIM protection enabled 1b = FAIM protection disabled*/ + ret = tfa_set_bf_volatile(tfa, TFA9894_BF_OPENMTP, (uint16_t)(status)); + return ret; +} + +static enum Tfa98xx_Error tfa9894_specific(struct tfa_device *tfa) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + unsigned short value, xor; + + if (tfa->in_use == 0) + return Tfa98xx_Error_NotOpen; + + /* Unlock keys to write settings */ + error = reg_write(tfa, 0x0F, 0x5A6B); + error = reg_read(tfa, 0xFB, &value); + xor = value ^ 0x005A; + error = reg_write(tfa, 0xA0, xor); + + /* The optimal settings */ + if (tfa->rev == 0x0a94) { + /* V36 */ + /* ----- generated code start ----- */ + reg_write(tfa, 0x00, 0xa245); //POR=0x8245 + reg_write(tfa, 0x02, 0x51e8); //POR=0x55c8 + reg_write(tfa, 0x52, 0xbe17); //POR=0xb617 + reg_write(tfa, 0x57, 0x0344); //POR=0x0366 + reg_write(tfa, 0x61, 0x0033); //POR=0x0073 + reg_write(tfa, 0x71, 0x00cf); //POR=0x018d + reg_write(tfa, 0x72, 0x34a9); //POR=0x44e8 + reg_write(tfa, 0x73, 0x3808); //POR=0x3806 + reg_write(tfa, 0x76, 0x0067); //POR=0x0065 + reg_write(tfa, 0x80, 0x0000); //POR=0x0003 + reg_write(tfa, 0x81, 0x5715); //POR=0x561a + reg_write(tfa, 0x82, 0x0104); //POR=0x0044 + /* ----- generated code end ----- */ + } else if (tfa->rev == 0x1a94) { + /* V14 */ + /* ----- generated code start ----- */ + reg_write(tfa, 0x00, 0xa245); //POR=0x8245 + reg_write(tfa, 0x01, 0x15da); //POR=0x11ca + reg_write(tfa, 0x02, 0x5288); //POR=0x55c8 + reg_write(tfa, 0x52, 0xbe17); //POR=0xb617 + reg_write(tfa, 0x53, 0x0dbe); //POR=0x0d9e + reg_write(tfa, 0x56, 0x05c3); //POR=0x07c3 + reg_write(tfa, 0x57, 0x0344); //POR=0x0366 + reg_write(tfa, 0x61, 0x0032); //POR=0x0073 + reg_write(tfa, 0x71, 0x00cf); //POR=0x018d + reg_write(tfa, 0x72, 0x34a9); //POR=0x44e8 + reg_write(tfa, 0x73, 0x38c8); //POR=0x3806 + reg_write(tfa, 0x76, 0x0067); //POR=0x0065 + reg_write(tfa, 0x80, 0x0000); //POR=0x0003 + reg_write(tfa, 0x81, 0x5799); //POR=0x561a + reg_write(tfa, 0x82, 0x0104); //POR=0x0044 + /* ----- generated code end ----- */ + } + + return error; +} + +static enum Tfa98xx_Error tfa9894_set_mute(struct tfa_device *tfa, int mute) +{ + tfa_set_bf(tfa, TFA9894_BF_CFSM, (const uint16_t)mute); + + return Tfa98xx_Error_Ok; +} + +static enum Tfa98xx_Error tfa9894_dsp_system_stable(struct tfa_device *tfa, + int *ready) +{ + enum Tfa98xx_Error error = Tfa98xx_Error_Ok; + + /* check CLKS: ready if set */ + *ready = tfa_get_bf(tfa, TFA9894_BF_CLKS) == 1; + + return error; +} + +void tfa9894_ops(struct tfa_device_ops *ops) +{ + /* Set defaults for ops */ + set_ops_defaults(ops); + + ops->tfa_init = tfa9894_specific; + ops->dsp_system_stable = tfa9894_dsp_system_stable; + ops->set_mute = tfa9894_set_mute; + ops->faim_protect = tfa9894_faim_protect; + ops->get_mtpb = tfa9894_get_mtpb; + ops->set_swprof = tfa9894_set_swprofile; + ops->get_swprof = tfa9894_get_swprofile; + ops->set_swvstep = tfa9894_set_swvstep; + ops->get_swvstep = tfa9894_get_swvstep; + //ops->auto_copy_mtp_to_iic = tfa9894_auto_copy_mtp_to_iic; + ops->set_osc_powerdown = tfa9894_set_osc_powerdown; +} diff --git a/techpack/audio/dsp/Kbuild b/techpack/audio/dsp/Kbuild index 7620628cbcf4..aaddbd54bb80 100644 --- a/techpack/audio/dsp/Kbuild +++ b/techpack/audio/dsp/Kbuild @@ -107,6 +107,24 @@ ifdef CONFIG_SND_SOC_MSM_QDSP6V2_INTF Q6_OBJS += msm_audio_ion.o Q6_OBJS += avtimer.o Q6_OBJS += q6_init.o + Q6_OBJS += apr_elliptic.o + Q6_OBJS += elliptic/elliptic.o + Q6_OBJS += elliptic/elliptic_sysfs.o + Q6_OBJS += elliptic/elliptic_mixer_controls.o + Q6_OBJS += elliptic/io_modules/msm/elliptic_data_msm_io.o + Q6_OBJS += elliptic/io_modules/userspace/elliptic_data_userspace_io.o + Q6_OBJS += elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.o +# for mius start +ifdef CONFIG_US_PROXIMITY + Q6_OBJS += apr_mius.o + Q6_OBJS += mius/mius.o + Q6_OBJS += mius/mius_sysfs.o + Q6_OBJS += mius/mius_mixer_controls.o + Q6_OBJS += mius/io_modules/msm/mius_data_msm_io.o + Q6_OBJS += mius/io_modules/userspace/mius_data_userspace_io.o + Q6_OBJS += mius/io_modules/userspace/mius_data_userspace_ctrl.o +endif +# for mius end endif ifdef CONFIG_XT_LOGGING @@ -141,6 +159,14 @@ ifdef CONFIG_MSM_MDF Q6_OBJS += msm_mdf.o endif +ifdef CONFIG_MSM_CSPL + Q6_OBJS += msm-cirrus-playback.o +endif + +ifdef CONFIG_MSM_CSPL_V2 + Q6_OBJS += msm-cirrus-playback-v2.o +endif + ifdef CONFIG_VOICE_MHI Q6_OBJS += voice_mhi.o endif diff --git a/techpack/audio/dsp/Kconfig b/techpack/audio/dsp/Kconfig index 9d6601d1e644..c4c239f6454e 100644 --- a/techpack/audio/dsp/Kconfig +++ b/techpack/audio/dsp/Kconfig @@ -1,3 +1,13 @@ menu "Qualcomm DSP" +config MSM_CSPL + tristate "Cirrus Playback driver" + help + Say Y here if you want to enable the Cirrus Playback driver. + +config MSM_CSPL_V2 + tristate "Cirrus Playback driver" + help + Say Y here if you want to enable the Cirrus Playback driver. + endmenu diff --git a/techpack/audio/dsp/apr_elliptic.c b/techpack/audio/dsp/apr_elliptic.c new file mode 100644 index 000000000000..668e8368ca60 --- /dev/null +++ b/techpack/audio/dsp/apr_elliptic.c @@ -0,0 +1,435 @@ +/** + * Elliptic Labs + */ + +#include +#include +#include +#include +#include +#include +#include "../asoc/msm-pcm-routing-v2.h" +#include +#include +#include +#include +#include +#include + +#ifndef min +#define min(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +enum { + HALL_SLIDER_UP = 4, + HALL_SLIDER_DOWN = 5, + HALL_SLIDING = 6, +}; + +enum driver_sensor_type { + DRIVER_SENSOR_HALL = 35, +}; + +struct driver_sensor_event { + enum driver_sensor_type type; + union { + int32_t event; + int32_t reserved[2]; + }; +}; + +static int afe_set_parameter(int port, int param_id, int module_id, + struct afe_ultrasound_set_params_t *prot_config, + uint32_t length) +{ + struct afe_port_cmd_set_param_v2 *set_param_v2 = NULL; + uint32_t set_param_v2_size = sizeof(struct afe_port_cmd_set_param_v2); + struct afe_port_cmd_set_param_v3 *set_param_v3 = NULL; + uint32_t set_param_v3_size = sizeof(struct afe_port_cmd_set_param_v3); + struct param_hdr_v3 param_hdr = { 0 }; + u16 port_id = 0; + int index = 0; + u8 *packed_param_data = NULL; + int packed_data_size = sizeof(union param_hdrs) + length; + int ret = 0; + + pr_debug("[ELUS]: inside %s\n", __func__); + + port_id = q6audio_get_port_id(port); + ret = q6audio_validate_port(port_id); + if (ret < 0) { + pr_err("%s: Not a valid port id = 0x%x ret %d\n", __func__, + port_id, ret); + return -EINVAL; + } + index = q6audio_get_port_index(port); + + param_hdr.module_id = module_id; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = length; + pr_debug("[ELUS]: param_size %d\n", length); + + packed_param_data = kzalloc(packed_data_size, GFP_KERNEL); + if (packed_param_data == NULL) + return -ENOMEM; + + ret = q6common_pack_pp_params(packed_param_data, ¶m_hdr, + (u8 *)prot_config, &packed_data_size); + if (ret) { + pr_err("%s: Failed to pack param header and data, error %d\n", + __func__, ret); + goto fail_cmd; + } + + if (q6common_is_instance_id_supported()) { + set_param_v3_size += packed_data_size; + set_param_v3 = kzalloc(set_param_v3_size, GFP_KERNEL); + if (set_param_v3 == NULL) { + ret = -ENOMEM; + goto fail_cmd; + } + + set_param_v3->apr_hdr.hdr_field = + APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + set_param_v3->apr_hdr.pkt_size = + sizeof(struct afe_port_cmd_set_param_v3) + + packed_data_size; + set_param_v3->apr_hdr.src_port = 0; + set_param_v3->apr_hdr.dest_port = 0; + set_param_v3->apr_hdr.token = index; + set_param_v3->apr_hdr.opcode = AFE_PORT_CMD_SET_PARAM_V3; + set_param_v3->port_id = port_id; + set_param_v3->payload_size = packed_data_size; + memcpy(&set_param_v3->param_data, packed_param_data, + packed_data_size); + + atomic_set(elus_afe.ptr_state, 1); + ret = apr_send_pkt(*elus_afe.ptr_apr, (uint32_t *)set_param_v3); + } else { + set_param_v2_size += packed_data_size; + set_param_v2 = kzalloc(set_param_v2_size, GFP_KERNEL); + if (set_param_v2 == NULL) { + ret = -ENOMEM; + goto fail_cmd; + } + + set_param_v2->apr_hdr.hdr_field = + APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + set_param_v2->apr_hdr.pkt_size = + sizeof(struct afe_port_cmd_set_param_v2) + + packed_data_size; + set_param_v2->apr_hdr.src_port = 0; + set_param_v2->apr_hdr.dest_port = 0; + set_param_v2->apr_hdr.token = index; + set_param_v2->apr_hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; + set_param_v2->port_id = port_id; + set_param_v2->payload_size = packed_data_size; + memcpy(&set_param_v2->param_data, packed_param_data, + packed_data_size); + + atomic_set(elus_afe.ptr_state, 1); + ret = apr_send_pkt(*elus_afe.ptr_apr, (uint32_t *)set_param_v2); + } + if (ret < 0) { + pr_err("%s: Setting param for port %d param[0x%x]failed\n", + __func__, port, param_id); + goto fail_cmd; + } + ret = wait_event_timeout(elus_afe.ptr_wait[index], + (atomic_read(elus_afe.ptr_state) == 0), + msecs_to_jiffies(elus_afe.timeout_ms)); + if (!ret) { + pr_err("%s: wait_event timeout\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + if (atomic_read(elus_afe.ptr_status) != 0) { + pr_err("%s: set param cmd failed\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + ret = 0; +fail_cmd: + pr_debug("%s param_id %x status %d\n", __func__, param_id, ret); + kfree(set_param_v2); + kfree(set_param_v3); + kfree(packed_param_data); + return ret; +} + +int32_t ultrasound_apr_set_parameter(int32_t port_id, uint32_t param_id, + u8 *user_params, int32_t length) +{ + int32_t ret = 0; + uint32_t module_id; + + if (port_id == ELLIPTIC_PORT_ID) + module_id = ELLIPTIC_ULTRASOUND_MODULE_TX; + else + module_id = ELLIPTIC_ULTRASOUND_MODULE_RX; + + ret = afe_set_parameter( + port_id, param_id, module_id, + (struct afe_ultrasound_set_params_t *)user_params, length); + + return ret; +} + +static int32_t process_version_msg(uint32_t *payload, uint32_t payload_size) +{ + struct elliptic_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[ELUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= ELLIPTIC_VERSION_INFO_SIZE) { + pr_debug("[ELUS]: elliptic_version copied to local AP cache"); + data_block = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_VERSION_INFO); + copy_size = min_t(size_t, data_block->size, + (size_t)ELLIPTIC_VERSION_INFO_SIZE); + + memcpy((u8 *)data_block->buffer, &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_branch_msg(uint32_t *payload, uint32_t payload_size) +{ + struct elliptic_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[ELUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= ELLIPTIC_BRANCH_INFO_SIZE) { + pr_debug("[ELUS]: elliptic_branch copied to local AP cache"); + data_block = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_BRANCH_INFO); + copy_size = min_t(size_t, data_block->size, + (size_t)ELLIPTIC_BRANCH_INFO_MAX_SIZE); + + memcpy((u8 *)data_block->buffer, &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_tag_msg(uint32_t *payload, uint32_t payload_size) +{ + struct elliptic_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[ELUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= ELLIPTIC_TAG_INFO_SIZE) { + pr_debug("[ELUS]: elliptic_tag copied to local AP cache"); + data_block = elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_TAG_INFO); + copy_size = min_t(size_t, data_block->size, + (size_t)ELLIPTIC_TAG_INFO_SIZE); + + memcpy((u8 *)data_block->buffer, &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_calibration_msg(uint32_t *payload, uint32_t payload_size) +{ + struct elliptic_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[ELUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= ELLIPTIC_CALIBRATION_DATA_SIZE) { + pr_debug("[ELUS]: calibration_data copied to local AP cache"); + + data_block = elliptic_get_shared_obj( + ELLIPTIC_OBJ_ID_CALIBRATION_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)ELLIPTIC_CALIBRATION_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, &payload[3], copy_size); + elliptic_set_calibration_data((u8 *)&payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_calibration_v2_msg(uint32_t *payload, + uint32_t payload_size) +{ + struct elliptic_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[ELUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= ELLIPTIC_CALIBRATION_V2_DATA_SIZE) { + pr_debug("[ELUS]: calibration_data copied to local AP cache"); + + data_block = elliptic_get_shared_obj( + ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)ELLIPTIC_CALIBRATION_V2_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, &payload[3], copy_size); + elliptic_set_calibration_data((u8 *)&payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_ml_msg(uint32_t *payload, uint32_t payload_size) +{ + struct elliptic_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[ELUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= ELLIPTIC_ML_DATA_SIZE) { + pr_debug("[ELUS]: ml_data copied to local AP cache"); + + data_block = elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_ML_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)ELLIPTIC_ML_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_diagnostics_msg(uint32_t *payload, uint32_t payload_size) +{ + struct elliptic_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[ELUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= ELLIPTIC_DIAGNOSTICS_DATA_SIZE) { + pr_debug("[ELUS]: diagnostics_data copied to local AP cache"); + + data_block = elliptic_get_shared_obj( + ELLIPTIC_OBJ_ID_DIAGNOSTICS_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)ELLIPTIC_DIAGNOSTICS_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_sensorhub_msg(uint32_t *payload, uint32_t payload_size) +{ + int32_t ret = 0; + + pr_err("[ELUS]: %s, paramId:%u, size:%d\n", __func__, payload[1], + payload_size); + + return ret; +} + +int32_t elliptic_process_apr_payload(uint32_t *payload) +{ + uint32_t payload_size = 0; + int32_t ret = -1; + + if (payload[0] == ELLIPTIC_ULTRASOUND_MODULE_TX) { + /* payload format + * payload[0] = Module ID + * payload[1] = Param ID + * payload[2] = LSB - payload size + * MSB - reserved(TBD) + * payload[3] = US data payload starts from here + */ + payload_size = payload[2] & 0xFFFF; + + switch (payload[1]) { + case ELLIPTIC_ULTRASOUND_PARAM_ID_ENGINE_VERSION: + ret = process_version_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_BUILD_BRANCH: + ret = process_branch_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_TAG: + ret = process_tag_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_CALIBRATION_DATA: + ret = process_calibration_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_CALIBRATION_V2_DATA: + ret = process_calibration_v2_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_ML_DATA: + ret = process_ml_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_DIAGNOSTICS_DATA: + ret = process_diagnostics_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_SENSORHUB: + ret = process_sensorhub_msg(payload, payload_size); + break; + case ELLIPTIC_ULTRASOUND_PARAM_ID_ENGINE_DATA: + ret = elliptic_data_push( + ELLIPTIC_ALL_DEVICES, (const char *)&payload[3], + (size_t)payload_size, + ELLIPTIC_DATA_PUSH_FROM_KERNEL); + + if (ret != 0) { + pr_err("[ELUS] : failed to push apr payload to elliptic device"); + return ret; + } + ret = payload_size; + break; + default: { + pr_err("[ELUS] : elliptic_process_apr_payload, Illegal paramId:%u", + payload[1]); + } break; + } + } else { + pr_debug("[ELUS]: Invalid Ultrasound Module ID %d\n", + payload[0]); + } + return ret; +} + +int elliptic_set_hall_state(int state) +{ + struct driver_sensor_event dse; + int ret = -1; + + dse.type = DRIVER_SENSOR_HALL; + + switch (state) { + case 0: + dse.event = HALL_SLIDER_UP; + break; + case 1: + dse.event = HALL_SLIDER_DOWN; + break; + case 2: + dse.event = HALL_SLIDING; + break; + default: + pr_err("%s Invalid HALL state:%d\n", __func__, state); + return ret; + } + + ret = afe_set_parameter(ELLIPTIC_PORT_ID, 2, + ELLIPTIC_ULTRASOUND_MODULE_TX, + (struct afe_ultrasound_set_params_t *)&dse, + sizeof(dse)); + return ret; +} +EXPORT_SYMBOL(elliptic_set_hall_state); diff --git a/techpack/audio/dsp/apr_mius.c b/techpack/audio/dsp/apr_mius.c new file mode 100644 index 000000000000..6239bf751160 --- /dev/null +++ b/techpack/audio/dsp/apr_mius.c @@ -0,0 +1,464 @@ +/** + * Mi + */ + +#include +#include +#include +#include +#include +#include +#include "../asoc/msm-pcm-routing-v2.h" +#include +#include +#include +#include +#include +#include + +#ifndef min +#define min(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +enum { + HALL_SLIDER_UP = 4, + HALL_SLIDER_DOWN = 5, + HALL_SLIDING = 6, +}; + +enum driver_sensor_type { + DRIVER_SENSOR_HALL = 35, +}; + +struct driver_sensor_event { + enum driver_sensor_type type; + union { + int32_t event; + int32_t reserved[2]; + }; +}; + +static int afe_set_parameter(int port, int param_id, int module_id, + struct afe_mi_ultrasound_set_params_t *prot_config, + uint32_t length) +{ + struct afe_port_cmd_set_param_v2 *set_param_v2 = NULL; + uint32_t set_param_v2_size = sizeof(struct afe_port_cmd_set_param_v2); + struct afe_port_cmd_set_param_v3 *set_param_v3 = NULL; + uint32_t set_param_v3_size = sizeof(struct afe_port_cmd_set_param_v3); + struct param_hdr_v3 param_hdr = { 0 }; + u16 port_id = 0; + int index = 0; + u8 *packed_param_data = NULL; + int packed_data_size = sizeof(union param_hdrs) + length; + int ret = 0; + + pr_debug("[MIUS]: inside %s\n", __func__); + + port_id = q6audio_get_port_id(port); + ret = q6audio_validate_port(port_id); + if (ret < 0) { + pr_err("%s: Not a valid port id = 0x%x ret %d\n", __func__, + port_id, ret); + return -EINVAL; + } + index = q6audio_get_port_index(port); + + param_hdr.module_id = module_id; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = length; + pr_debug("[MIUS]: param_size %d\n", length); + + packed_param_data = kzalloc(packed_data_size, GFP_KERNEL); + if (packed_param_data == NULL) + return -ENOMEM; + + ret = q6common_pack_pp_params(packed_param_data, ¶m_hdr, + (u8 *)prot_config, &packed_data_size); + if (ret) { + pr_err("%s: Failed to pack param header and data, error %d\n", + __func__, ret); + goto fail_cmd; + } + + if (q6common_is_instance_id_supported()) { + set_param_v3_size += packed_data_size; + set_param_v3 = kzalloc(set_param_v3_size, GFP_KERNEL); + if (set_param_v3 == NULL) { + ret = -ENOMEM; + goto fail_cmd; + } + + set_param_v3->apr_hdr.hdr_field = + APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + set_param_v3->apr_hdr.pkt_size = + sizeof(struct afe_port_cmd_set_param_v3) + + packed_data_size; + set_param_v3->apr_hdr.src_port = 0; + set_param_v3->apr_hdr.dest_port = 0; + set_param_v3->apr_hdr.token = index; + set_param_v3->apr_hdr.opcode = AFE_PORT_CMD_SET_PARAM_V3; + set_param_v3->port_id = port_id; + set_param_v3->payload_size = packed_data_size; + memcpy(&set_param_v3->param_data, packed_param_data, + packed_data_size); + + atomic_set(mius_afe.ptr_state, 1); + ret = apr_send_pkt(*mius_afe.ptr_apr, (uint32_t *)set_param_v3); + } else { + set_param_v2_size += packed_data_size; + set_param_v2 = kzalloc(set_param_v2_size, GFP_KERNEL); + if (set_param_v2 == NULL) { + ret = -ENOMEM; + goto fail_cmd; + } + + set_param_v2->apr_hdr.hdr_field = + APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + set_param_v2->apr_hdr.pkt_size = + sizeof(struct afe_port_cmd_set_param_v2) + + packed_data_size; + set_param_v2->apr_hdr.src_port = 0; + set_param_v2->apr_hdr.dest_port = 0; + set_param_v2->apr_hdr.token = index; + set_param_v2->apr_hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; + set_param_v2->port_id = port_id; + set_param_v2->payload_size = packed_data_size; + memcpy(&set_param_v2->param_data, packed_param_data, + packed_data_size); + + atomic_set(mius_afe.ptr_state, 1); + ret = apr_send_pkt(*mius_afe.ptr_apr, (uint32_t *)set_param_v2); + } + if (ret < 0) { + pr_err("%s: Setting param for port %d param[0x%x]failed\n", + __func__, port, param_id); + goto fail_cmd; + } + ret = wait_event_timeout(mius_afe.ptr_wait[index], + (atomic_read(mius_afe.ptr_state) == 0), + msecs_to_jiffies(mius_afe.timeout_ms * 10)); + if (!ret) { + pr_err("%s: wait_event timeout\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + if (atomic_read(mius_afe.ptr_status) != 0) { + pr_err("%s: set param cmd failed\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + ret = 0; +fail_cmd: + pr_debug("%s param_id %x status %d\n", __func__, param_id, ret); + kfree(set_param_v2); + kfree(set_param_v3); + kfree(packed_param_data); + return ret; +} + +int32_t mi_ultrasound_apr_set_parameter(int32_t port_id, uint32_t param_id, + u8 *user_params, int32_t length) +{ + int32_t ret = 0; + uint32_t module_id; + + if (port_id == MIUS_PORT_ID) + module_id = MIUS_ULTRASOUND_MODULE_TX; + else + module_id = MIUS_ULTRASOUND_MODULE_RX; + + ret = afe_set_parameter( + port_id, param_id, module_id, + (struct afe_mi_ultrasound_set_params_t *)user_params, length); + + return ret; +} + +#if 0 +static int32_t process_version_msg(uint32_t *payload, uint32_t payload_size) +{ + struct mius_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[MIUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= MIUS_VERSION_INFO_SIZE) { + pr_debug("[MIUS]: mius_version copied to local AP cache"); + data_block = + mius_get_shared_obj( + MIUS_OBJ_ID_VERSION_INFO); + copy_size = min_t(size_t, data_block->size, + (size_t)MIUS_VERSION_INFO_SIZE); + + memcpy((u8 *)data_block->buffer, + &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_branch_msg(uint32_t *payload, uint32_t payload_size) +{ + struct mius_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[MIUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= MIUS_BRANCH_INFO_SIZE) { + pr_debug("[MIUS]: mius_branch copied to local AP cache"); + data_block = + mius_get_shared_obj( + MIUS_OBJ_ID_BRANCH_INFO); + copy_size = min_t(size_t, data_block->size, + (size_t)MIUS_BRANCH_INFO_MAX_SIZE); + + memcpy((u8 *)data_block->buffer, + &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_tag_msg(uint32_t *payload, uint32_t payload_size) +{ + struct mius_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[MIUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= MIUS_TAG_INFO_SIZE) { + pr_debug("[MIUS]: mius_tag copied to local AP cache"); + data_block = + mius_get_shared_obj( + MIUS_OBJ_ID_TAG_INFO); + copy_size = min_t(size_t, data_block->size, + (size_t)MIUS_TAG_INFO_SIZE); + + memcpy((u8 *)data_block->buffer, + &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_calibration_msg(uint32_t *payload, uint32_t payload_size) +{ + struct mius_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[MIUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= MIUS_CALIBRATION_DATA_SIZE) { + pr_debug("[MIUS]: calibration_data copied to local AP cache"); + + data_block = mius_get_shared_obj( + MIUS_OBJ_ID_CALIBRATION_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)MIUS_CALIBRATION_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, + &payload[3], copy_size); + mius_set_calibration_data((u8 *)&payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_calibration_v2_msg(uint32_t *payload, uint32_t payload_size) +{ + struct mius_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[MIUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= MIUS_CALIBRATION_V2_DATA_SIZE) { + pr_debug("[MIUS]: calibration_data copied to local AP cache"); + + data_block = mius_get_shared_obj( + MIUS_OBJ_ID_CALIBRATION_V2_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)MIUS_CALIBRATION_V2_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, + &payload[3], copy_size); + mius_set_calibration_data((u8 *)&payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_ml_msg(uint32_t *payload, uint32_t payload_size) +{ + struct mius_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[MIUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= MIUS_ML_DATA_SIZE) { + pr_debug("[MIUS]: ml_data copied to local AP cache"); + + data_block = mius_get_shared_obj( + MIUS_OBJ_ID_ML_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)MIUS_ML_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, + &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_diagnostics_msg(uint32_t *payload, uint32_t payload_size) +{ + struct mius_shared_data_block *data_block = NULL; + size_t copy_size = 0; + int32_t ret = -1; + + pr_err("[MIUS]: %s() size:%d\n", __func__, payload_size); + + if (payload_size >= MIUS_DIAGNOSTICS_DATA_SIZE) { + pr_debug("[MIUS]: diagnostics_data copied to local AP cache"); + + data_block = mius_get_shared_obj( + MIUS_OBJ_ID_DIAGNOSTICS_DATA); + copy_size = min_t(size_t, data_block->size, + (size_t)MIUS_DIAGNOSTICS_DATA_SIZE); + + memcpy((u8 *)data_block->buffer, + &payload[3], copy_size); + ret = (int32_t)copy_size; + } + return ret; +} + +static int32_t process_sensorhub_msg(uint32_t *payload, uint32_t payload_size) +{ + int32_t ret = 0; + + pr_err("[MIUS]: %s, paramId:%u, size:%d\n", + __func__, payload[1], payload_size); + + return ret; +} + +#endif + +extern int us_afe_callback(int data); +static int ups_event = 0; + +int32_t mius_process_apr_payload(uint32_t *payload) +{ + uint32_t payload_size = 0; + int32_t ret = -1; + + //if (payload[0] == MIUS_ULTRASOUND_MODULE_TX) { + if (true) { + /* payload format + * payload[0] = Module ID + * payload[1] = Param ID + * payload[2] = LSB - payload size + * MSB - reserved(TBD) + * payload[3] = US data payload starts from here + */ + payload_size = payload[2] & 0xFFFF; +#if 0 + switch (payload[1]) { + case MIUS_ULTRASOUND_PARAM_ID_ENGINE_VERSION: + ret = process_version_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_BUILD_BRANCH: + ret = process_branch_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_TAG: + ret = process_tag_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_CALIBRATION_DATA: + ret = process_calibration_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_CALIBRATION_V2_DATA: + ret = process_calibration_v2_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_ML_DATA: + ret = process_ml_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_DIAGNOSTICS_DATA: + ret = process_diagnostics_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_SENSORHUB: + ret = process_sensorhub_msg(payload, payload_size); + break; + case MIUS_ULTRASOUND_PARAM_ID_ENGINE_DATA: +#endif + printk(KERN_DEBUG "[MIUS] mi us payload[3] = %d", + (int)payload[3]); + if (payload[3] == 0 || payload[3] == 1) { + ups_event = payload[3]; + ret = (int32_t)us_afe_callback( + (const uint32_t)payload[3]); + } else { + ups_event = ups_event ^ 1; + printk(KERN_DEBUG "[MIUS] >> change ups to %d", + ups_event); + ret = (int32_t)us_afe_callback((uint32_t)ups_event); + } + + if (ret != 0) { + pr_err("[MIUS] : failed to push apr payload to mius device"); + return ret; + } + ret = payload_size; +#if 0 + break; + default: + { + pr_err("[MIUS] : mius_process_apr_payload, Illegal paramId:%u", payload[1]); + } + break; + } +#endif + } else { + pr_debug("[MIUS]: Invalid Ultrasound Module ID %d\n", + payload[0]); + } + return ret; +} + +int mius_set_hall_state(int state) +{ + struct driver_sensor_event dse; + int ret = -1; + + dse.type = DRIVER_SENSOR_HALL; + + switch (state) { + case 0: + dse.event = HALL_SLIDER_UP; + break; + case 1: + dse.event = HALL_SLIDER_DOWN; + break; + case 2: + dse.event = HALL_SLIDING; + break; + default: + pr_err("%s Invalid HALL state:%d\n", __func__, state); + return ret; + } + + ret = afe_set_parameter(MIUS_PORT_ID, 2, MIUS_ULTRASOUND_MODULE_TX, + (struct afe_mi_ultrasound_set_params_t *)&dse, + sizeof(dse)); + return ret; +} +EXPORT_SYMBOL(mius_set_hall_state); diff --git a/techpack/audio/dsp/elliptic/Makefile b/techpack/audio/dsp/elliptic/Makefile new file mode 100644 index 000000000000..b31a89b246a7 --- /dev/null +++ b/techpack/audio/dsp/elliptic/Makefile @@ -0,0 +1,28 @@ +ccflags-y := -I$(src) -Wall -Werror +IO_MODULE := msm + +# EXTRA_CFLAGS += -DDEBUG + +# Need to add include paths: +LINUXINCLUDE += \ + -I$(srctree)techpack/audio/include/dsp + -I$(srctree)techpack/audio/include/uapi + -I$(srctree)techpack/aduio/include + +obj-y += elliptic.o +obj-y += elliptic_mixer_controls.o +obj-y += io_modules/$(IO_MODULE)/elliptic_data_$(IO_MODULE)_io.o +obj-y += io_modules/userspace/elliptic_data_userspace_io.o +obj-y += io_modules/userspace/elliptic_data_userspace_ctrl.o +obj-y += elliptic_sysfs.o + +# elliptic_driver-y := elliptic.o +# elliptic_driver-y += io_modules/$(IO_MODULE)/elliptic_data_io.o +# elliptic_driver-y += mixer_controls/$(MIXER_MODULE)/elliptic_mixer_controls.o +# elliptic_driver-y += elliptic_sysfs.o + +# .PHONY: clean +# all: +# make -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) modules +# clean: +# rm *.o *.ko \ No newline at end of file diff --git a/techpack/audio/dsp/elliptic/elliptic.c b/techpack/audio/dsp/elliptic/elliptic.c new file mode 100644 index 000000000000..f646f03db0b3 --- /dev/null +++ b/techpack/audio/dsp/elliptic/elliptic.c @@ -0,0 +1,776 @@ +/** +* Copyright Elliptic Labs +* Copyright (C) 2019 XiaoMi, Inc. +* +*/ +/* #define DEBUG */ +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* Alternative mechanism to load calibration data. +* Read calibration data during driver initialization +* and send message to the DSP +* +* #define ELLIPTIC_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM 1 +*/ +#ifdef ELLIPTIC_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM +#include +#include +#include +#endif + +static struct elliptic_device *elliptic_devices; + +/* Global variable for the device class*/ +struct class *elliptic_class; + +typedef uint32_t el_fifo_size_t; + +/* Major number provided by the kernel*/ +static dev_t elliptic_major; + +static struct wakeup_source *wake_source; + +void elliptic_data_cancel(struct elliptic_data *elliptic_data) +{ + atomic_set(&elliptic_data->abort_io, 1); + wake_up_interruptible(&elliptic_data->fifo_isr_not_empty); +} + +void elliptic_data_reset_debug_counters(struct elliptic_data *elliptic_data) +{ + elliptic_data->isr_fifo_discard = 0; +} + +void elliptic_data_print_debug_counters(struct elliptic_data *elliptic_data) +{ + if (elliptic_data->isr_fifo_discard > 0) { + EL_PRINT_E("isr fifo discarded %u frames", + elliptic_data->isr_fifo_discard); + } + + if (elliptic_data->userspace_read_total != + elliptic_data->isr_write_total) { + EL_PRINT_I("user space reads / isr writes : %u / %u", + elliptic_data->userspace_read_total, + elliptic_data->isr_write_total); + } + + EL_PRINT_I("total isr fifo discarded frame count : %u", + elliptic_data->isr_fifo_discard_total); +} + +void elliptic_data_update_debug_counters(struct elliptic_data *elliptic_data) +{ + elliptic_data->isr_fifo_discard_total += + elliptic_data->isr_fifo_discard; +} + +/* spin lock for isr must be held prior to calling */ +static void elliptic_data_flush_isr_fifo(struct elliptic_data *elliptic_data) +{ + kfifo_reset(&elliptic_data->fifo_isr); +} + +/* spin lock for isr must be held prior to calling */ +static void elliptic_data_isr_fifo_pop(struct elliptic_data *elliptic_data, + size_t size) +{ + unsigned int fifo_result; + static uint8_t temp_buffer[ELLIPTIC_MSG_BUF_SIZE]; + + if (size > ELLIPTIC_MSG_BUF_SIZE) + EL_PRINT_E("pop size %zu too large", size); + + fifo_result = kfifo_out(&elliptic_data->fifo_isr, temp_buffer, size); + + if (size != fifo_result) + EL_PRINT_E("failed to pop element"); +} + +int elliptic_notify_gain_change_msg(int component_id, int gaindb) +{ + int32_t msg[3] = { ESCPT_COMPONENT_GAIN_CHANGE, component_id, gaindb }; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} + +/* inode refers to the actual file on disk */ +static int device_open(struct inode *inode, struct file *filp) +{ + unsigned int major; + unsigned int minor; + struct elliptic_device *dev; + struct elliptic_data *elliptic_data; + + major = imajor(inode); + minor = iminor(inode); + + if (major != elliptic_major || minor < 0 || + minor >= ELLIPTIC_NUM_DEVICES) { + EL_PRINT_W("no device found with minor=%d and major=%d", major, + minor); + return -ENODEV; /* No such device */ + } + + dev = NULL; + dev = &elliptic_devices[minor]; + filp->private_data = dev; + + if (inode->i_cdev != &dev->cdev) { + EL_PRINT_W("dev pointer mismatch"); + return -ENODEV; /* No such device */ + } + + if (down_interruptible(&dev->sem) != 0) { + EL_PRINT_E("the device has been opened, unable to open lock"); + return -EINVAL; + } + + elliptic_data = &dev->el_data; + spin_lock(&elliptic_data->fifo_isr_spinlock); + elliptic_data_flush_isr_fifo(elliptic_data); + spin_unlock(&elliptic_data->fifo_isr_spinlock); + + atomic_set(&elliptic_data->abort_io, 0); + elliptic_data_reset_debug_counters(elliptic_data); + + EL_PRINT_I("Opened device elliptic%u", minor); + dev->opened = 1; + return 0; +} + +int elliptic_data_initialize(struct elliptic_data *elliptic_data, + size_t queue_size, unsigned int wakeup_timeout, + int id) +{ + int is_power_of_two; + + is_power_of_two = (queue_size != 0) && !(queue_size & (queue_size - 1)); + + if (is_power_of_two != 1) { + EL_PRINT_E("non power of 2 fifo size"); + return -EINVAL; + } + + if (kfifo_alloc(&elliptic_data->fifo_isr, queue_size, GFP_KERNEL) != + 0) { + EL_PRINT_E("failed to allocate fifo isr"); + return -EINVAL; + } + + atomic_set(&elliptic_data->abort_io, 0); + spin_lock_init(&elliptic_data->fifo_isr_spinlock); + + elliptic_data->wakeup_timeout = wakeup_timeout; + + mutex_init(&elliptic_data->user_buffer_lock); + init_waitqueue_head(&elliptic_data->fifo_isr_not_empty); + + return 0; +} + +int elliptic_data_cleanup(struct elliptic_data *elliptic_data) +{ + spin_unlock(&elliptic_data->fifo_isr_spinlock); + kfifo_free(&elliptic_data->fifo_isr); + return 0; +} + +size_t elliptic_data_pop(struct elliptic_data *elliptic_data, + char __user *user_buffer, size_t buffer_size) +{ + int result; + unsigned long num_copied; + unsigned int fifo_result; + unsigned long flags; + + if (buffer_size < ELLIPTIC_MSG_BUF_SIZE) { + EL_PRINT_E("buffer_size : %lu smaller than %lu", buffer_size, + (size_t)ELLIPTIC_MSG_BUF_SIZE); + return 0; + } + + result = wait_event_interruptible( + elliptic_data->fifo_isr_not_empty, + (kfifo_is_empty(&elliptic_data->fifo_isr) == 0) || + (atomic_read(&elliptic_data->abort_io) == 1)); + + if (atomic_read(&elliptic_data->abort_io) == 1) { + atomic_set(&elliptic_data->abort_io, 0); + EL_PRINT_D("pop cancelled"); + return 0; + } + + if (result == 0) { + spin_lock_irqsave(&elliptic_data->fifo_isr_spinlock, flags); + + fifo_result = kfifo_out(&elliptic_data->fifo_isr, + elliptic_data->isr_swap_buffer, + ELLIPTIC_MSG_BUF_SIZE); + + spin_unlock_irqrestore(&elliptic_data->fifo_isr_spinlock, + flags); + + if (fifo_result == 0) { + EL_PRINT_E("failed to copy: fifo isr -> swap buffer %u", + fifo_result); + return 0; + } + + mutex_lock(&elliptic_data->user_buffer_lock); + + num_copied = copy_to_user(user_buffer, + elliptic_data->isr_swap_buffer, + ELLIPTIC_MSG_BUF_SIZE); + + mutex_unlock(&elliptic_data->user_buffer_lock); + + if (num_copied != 0) { + EL_PRINT_E("failed copy to user"); + return 0; + } + ++elliptic_data->userspace_read_total; + } else { + if (-ERESTARTSYS == result) + EL_PRINT_I("wait interrupted"); + else + EL_PRINT_E("wait error = %d", result); + + return 0; + } + + return (size_t)ELLIPTIC_MSG_BUF_SIZE; +} + +/* push data to specific device or all devices */ +int elliptic_data_push(int deviceid, const char *buffer, size_t buffer_size, + elliptic_data_push_t data_source) +{ + size_t available_space; + size_t space_required; + size_t zeros_to_pad; + unsigned int copied_from_user; + int copy_from_user_result; + int err; + int i; + int i_max; + + unsigned long flags; + struct elliptic_device *device; + struct elliptic_data *elliptic_data; + unsigned int fifo_result; + static uint8_t zero_pad_buffer[ELLIPTIC_MSG_BUF_SIZE]; + + err = 0; + fifo_result = 0; + copied_from_user = 0; + copy_from_user_result = 0; + if (buffer_size > ELLIPTIC_MSG_BUF_SIZE) + return -EINVAL; + + zeros_to_pad = ELLIPTIC_MSG_BUF_SIZE - buffer_size; + + i = 0; + i_max = ELLIPTIC_NUM_DEVICES; + + if (deviceid != ELLIPTIC_ALL_DEVICES) { + /* Copy to specific device */ + i = deviceid; + i_max = i + 1; + } + + for (; i < i_max; ++i) { + device = &elliptic_devices[i]; + elliptic_data = &device->el_data; + + if ((!device->opened)) + continue; + + available_space = kfifo_avail(&elliptic_data->fifo_isr); + space_required = ELLIPTIC_MSG_BUF_SIZE; + + spin_lock_irqsave(&elliptic_data->fifo_isr_spinlock, flags); + + if (available_space < space_required) { + ++elliptic_data->isr_fifo_discard; + elliptic_data_isr_fifo_pop(elliptic_data, + ELLIPTIC_MSG_BUF_SIZE); + } + + if (data_source == ELLIPTIC_DATA_PUSH_FROM_KERNEL) { + fifo_result = kfifo_in(&elliptic_data->fifo_isr, buffer, + buffer_size); + + if (fifo_result == 0) { + spin_unlock_irqrestore( + &elliptic_data->fifo_isr_spinlock, + flags); + continue; + } + } else if (data_source == ELLIPTIC_DATA_PUSH_FROM_USERSPACE) { + copy_from_user_result = + kfifo_from_user(&elliptic_data->fifo_isr, + buffer, buffer_size, + &copied_from_user); + + if (-EFAULT == copy_from_user_result) { + spin_unlock_irqrestore( + &elliptic_data->fifo_isr_spinlock, + flags); + continue; + } + } + + if (zeros_to_pad > 0) { + fifo_result = kfifo_in(&elliptic_data->fifo_isr, + zero_pad_buffer, zeros_to_pad); + + if (fifo_result == 0) { + elliptic_data_isr_fifo_pop(elliptic_data, + buffer_size); + + spin_unlock_irqrestore( + &elliptic_data->fifo_isr_spinlock, + flags); + + ++elliptic_data->isr_fifo_discard; + continue; + } + } + + ++elliptic_data->isr_write_total; + spin_unlock_irqrestore(&elliptic_data->fifo_isr_spinlock, + flags); + wake_up_interruptible(&elliptic_data->fifo_isr_not_empty); + __pm_wakeup_event(wake_source, elliptic_data->wakeup_timeout); + } + + return err; +} + +int elliptic_open_port(int portid) +{ + return elliptic_io_open_port(portid); +} + +int elliptic_close_port(int portid) +{ + return elliptic_io_close_port(portid); +} + +int32_t elliptic_data_write(uint32_t message_id, const char *data, + size_t data_size) +{ + int32_t err_dsp; + /* int32_t err_us; */ + + err_dsp = 0; + err_dsp = elliptic_data_io_write(message_id, data, data_size); + if (err_dsp) + EL_PRINT_E("Failed write to DSP"); + return err_dsp; + + /* + * err_us = 0; + * err_us = elliptic_userspace_ctrl_write(message_id, data, data_size); + * if(err_us){ + * EL_PRINT_E("Failed write to user space"); + *} + * + *return (err_dsp | err_us); + */ +} + +/** +* +* @return Number of bytes read. +*/ +static ssize_t device_read(struct file *fp, char __user *buff, size_t length, + loff_t *ppos) +{ + ssize_t bytes_read = 0; + struct elliptic_device *elliptic_device; + struct elliptic_data *elliptic_data; + + elliptic_device = (struct elliptic_device *)fp->private_data; + elliptic_data = (struct elliptic_data *)&elliptic_device->el_data; + + bytes_read = elliptic_data_pop(elliptic_data, buff, length); + + return bytes_read; +} + +/** +* +* @return number of bytes actually written +*/ +static ssize_t device_write(struct file *fp, const char *buff, size_t length, + loff_t *ppos) +{ + ssize_t ret_val; + + ret_val = 0; + if ((buff != NULL) && (length != 0)) + ret_val = elliptic_data_io_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + buff, length); + + return ret_val >= 0 ? (ssize_t)length : 0; +} + +static long device_ioctl(struct file *fp, unsigned int number, + unsigned long param) +{ + struct elliptic_device *device; + struct elliptic_data *elliptic_data; + int err; + unsigned int mirror_tag, mirror_payload_size; + unsigned char *data_ptr; + + device = (struct elliptic_device *)(fp->private_data); + elliptic_data = &device->el_data; + + switch (number) { + case IOCTL_ELLIPTIC_DATA_IO_CANCEL: + EL_PRINT_D("IOCTL_ELLIPTIC_CANCEL_READ %ld", param); + elliptic_data_cancel(elliptic_data); + break; + + case IOCTL_ELLIPTIC_DATA_IO_MIRROR: + data_ptr = (unsigned char *)param; + mirror_tag = *(unsigned int *)data_ptr; + mirror_payload_size = *((unsigned int *)data_ptr + 1); + + if ((mirror_tag == MIRROR_TAG) && (mirror_payload_size != 0) && + (mirror_payload_size <= (ELLIPTIC_SET_PARAMS_SIZE * 4))) { + err = elliptic_data_io_write( + ELLIPTIC_ULTRASOUND_SET_PARAMS, (data_ptr + 8), + mirror_payload_size); + + if (err != 0) { + EL_PRINT_E("elliptic_data_io_write failed"); + return err; + } + + } else { + EL_PRINT_E("TAG or Length is not valid"); + } + + break; + + default: + EL_PRINT_W("UNKNOWN IOCTL number=%d", number); + break; + } + + return 0; +} + +static unsigned int device_poll(struct file *file, + struct poll_table_struct *poll_table) +{ + unsigned int mask; + + struct elliptic_device *device; + struct elliptic_data *elliptic_data; + + mask = 0; + device = (struct elliptic_device *)file->private_data; + elliptic_data = (struct elliptic_data *)&device->el_data; + + poll_wait(file, &elliptic_data->fifo_isr_not_empty, poll_table); + + if (!kfifo_is_empty(&elliptic_data->fifo_isr)) + mask = POLLIN | POLLRDNORM; + + return mask; +} + +static int device_close(struct inode *inode, struct file *filp) +{ + struct elliptic_device *device; + struct elliptic_data *elliptic_data; + unsigned int minor; + + device = filp->private_data; + elliptic_data = &device->el_data; + minor = iminor(inode); + if (device == NULL) { + EL_PRINT_E("device not found"); + return -ENODEV; + } + + device->opened = 0; + elliptic_data_update_debug_counters(elliptic_data); + elliptic_data_print_debug_counters(elliptic_data); + elliptic_data_cancel(elliptic_data); + up(&device->sem); + + EL_PRINT_I("Closed device elliptic%u", minor); + return 0; +} + +/* defines the file operations provided by the driver */ +static const struct file_operations elliptic_fops = { + .owner = THIS_MODULE, /* prevents unloading when operations are in use*/ + .open = device_open, /*to open the device*/ + .write = device_write, /*to write to the device*/ + .read = device_read, /*to read the device*/ + .poll = device_poll, + .unlocked_ioctl = device_ioctl, /* IOCTL calls */ + .release = device_close, /*to close the device*/ +}; + +static int elliptic_device_initialize(struct elliptic_device *elliptic_device, + int minor, struct class *class) +{ + int err; + dev_t device_number; + struct device *device; + + BUG_ON(elliptic_device == NULL || class == NULL); + + err = 0; + device = NULL; + device_number = MKDEV(elliptic_major, minor); + /* Memory is to be allocated when the device is opened the first time */ + sema_init(&elliptic_device->sem, 1); + cdev_init(&elliptic_device->cdev, &elliptic_fops); + elliptic_device->cdev.owner = THIS_MODULE; + + err = cdev_add(&elliptic_device->cdev, device_number, 1); + + if (err) { + EL_PRINT_E("error %d while trying to add %s%d", err, + ELLIPTIC_DEVICENAME, minor); + return err; + } + + device = device_create(class, NULL, device_number, NULL, + ELLIPTIC_DEVICENAME "%d", minor); + + if (IS_ERR(device)) { + err = PTR_ERR(device); + EL_PRINT_E("error %d while trying to create %s%d", err, + ELLIPTIC_DEVICENAME, minor); + cdev_del(&elliptic_device->cdev); + return err; + } + + if (err) { + EL_PRINT_E("failed device initialize"); + return err; + } + + return 0; +} + +static void elliptic_device_cleanup(struct elliptic_device *dev, int minor, + struct class *class) + +{ + BUG_ON(dev == NULL || class == NULL); + device_destroy(class, MKDEV(elliptic_major, minor)); + cdev_del(&dev->cdev); + up(&dev->sem); +} + +static void elliptic_driver_cleanup(int devices_to_destroy) +{ + int i; + + if (elliptic_devices) { + elliptic_data_io_cleanup(); + + for (i = 0; i < devices_to_destroy; ++i) { + elliptic_data_cleanup(&elliptic_devices[i].el_data); + elliptic_device_cleanup(&elliptic_devices[i], i, + elliptic_class); + } + + kfree(elliptic_devices); + } + + if (elliptic_class) + class_destroy(elliptic_class); + + unregister_chrdev_region(MKDEV(elliptic_major, 0), + ELLIPTIC_NUM_DEVICES); +} + +#ifdef ELLIPTIC_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM + +#define ELLIPTIC_CALIBRATION_MAX_DATA_SIZE \ + (ELLIPTIC_CALIBRATION_V2_DATA_SIZE + ELLIPTIC_CALIBRATION_DATA_SIZE) +static unsigned char calibration_data[ELLIPTIC_CALIBRATION_MAX_DATA_SIZE]; +static char *calibration_filename = "/persist/audio/elliptic_calibration"; + +/* function to load the calibration from a file (if possible) */ +static size_t load_calibration_data(char *filename) +{ + size_t ret = 0; + int fd; + + mm_segment_t old_fs = get_fs(); + + set_fs(KERNEL_DS); + + fd = sys_open(filename, O_RDONLY, 0); + if (fd >= 0) { + size_t bytes_read = + sys_read(fd, calibration_data, + ELLIPTIC_CALIBRATION_MAX_DATA_SIZE); + + if (bytes_read == ELLIPTIC_CALIBRATION_DATA_SIZE || + bytes_read == ELLIPTIC_CALIBRATION_V2_DATA_SIZE) { + ret = bytes_read; + } + sys_close(fd); + } + set_fs(old_fs); + return ret; +} + +static int32_t elliptic_send_calibration_to_engine(size_t calib_data_size) +{ + elliptic_set_calibration_data(calibration_data, calib_data_size); + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)calibration_data, + calib_data_size); +} + +#endif + +int __init elliptic_driver_init(void) +{ + int err; + int i; + int devices_to_destroy; + dev_t device_number; + + err = alloc_chrdev_region(&device_number, 0, ELLIPTIC_NUM_DEVICES, + ELLIPTIC_DEVICENAME); + + devices_to_destroy = 0; + + if (err < 0) { + EL_PRINT_E("Failed to allocate cdev region"); + return err; + } + + elliptic_major = MAJOR(device_number); + elliptic_class = class_create(THIS_MODULE, "chardev"); + + if (elliptic_class == NULL) { + EL_PRINT_E("Class creation failed"); + goto fail; + } + + err = elliptic_initialize_sysfs(); + + if (err) + goto fail; + + elliptic_devices = (struct elliptic_device *)kzalloc( + sizeof(struct elliptic_device) * ELLIPTIC_NUM_DEVICES, + GFP_KERNEL); + + if (elliptic_devices == NULL) { + err = -ENOMEM; + goto fail; + } + + for (i = 0; i < ELLIPTIC_NUM_DEVICES; ++i) { + if (elliptic_device_initialize(&elliptic_devices[i], i, + elliptic_class)) { + devices_to_destroy = i; + goto fail; + } + + if (elliptic_data_initialize(&elliptic_devices[i].el_data, + ELLIPTIC_DATA_FIFO_SIZE, + ELLIPTIC_WAKEUP_TIMEOUT, i)) { + goto fail; + } + } + + if (elliptic_data_io_initialize()) + goto fail; + + if (elliptic_userspace_io_driver_init()) + goto fail; + + if (elliptic_userspace_ctrl_driver_init()) + goto fail; + + wake_source = kmalloc(sizeof(struct wakeup_source), GFP_KERNEL); + + if (!wake_source) { + EL_PRINT_E("failed to allocate wake source"); + return -ENOMEM; + } + + wakeup_source_init(wake_source, "elliptic_wake_source"); + +#ifdef ELLIPTIC_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM + /* Code to send calibration to engine */ + { + size_t calib_data_size = + load_calibration_data(calibration_filename); + if (calib_data_size > 0) + elliptic_send_calibration_to_engine(calib_data_size); + } +#endif + return 0; + +fail: + elliptic_driver_cleanup(devices_to_destroy); + return err; +} + +void elliptic_driver_exit(void) +{ + if (wake_source) { + wakeup_source_trash(wake_source); + kfree(wake_source); + } + + elliptic_cleanup_sysfs(); + elliptic_driver_cleanup(ELLIPTIC_NUM_DEVICES); + elliptic_userspace_io_driver_exit(); + elliptic_userspace_ctrl_driver_exit(); +} + +MODULE_AUTHOR("Elliptic Labs"); +MODULE_DESCRIPTION("Providing Interface to UPS data"); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/dsp/elliptic/elliptic_mixer_controls.c b/techpack/audio/dsp/elliptic/elliptic_mixer_controls.c new file mode 100644 index 000000000000..089f1b91212e --- /dev/null +++ b/techpack/audio/dsp/elliptic/elliptic_mixer_controls.c @@ -0,0 +1,1367 @@ +/** + * Elliptic Labs + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct elliptic_system_configuration { + union { + uint8_t reserved[ELLIPTIC_SYSTEM_CONFIGURATION_SIZE]; + }; +}; + +struct elliptic_system_configuration elliptic_system_configuration; + +struct elliptic_system_configuration_parameter { + enum elliptic_system_configuration_parameter_type type; + union { + int32_t speaker_scaling[2]; + int32_t sensitivity; + int32_t latency; + int32_t microphone_index; + int32_t operation_mode; + int32_t operation_mode_flags; + int32_t component_gain_change; + int32_t calibration_state; + int32_t engine_version; + int32_t calibration_profile; + int32_t ultrasound_gain; + int32_t log_level; + int32_t custom_setting; + int32_t engine_suspend; + int32_t input_enabled; + int32_t output_enabled; + int32_t external_event; + struct { + int32_t calibration_method; + int32_t calibration_timestamp; + }; + int32_t debug_mode; + int32_t context; + int32_t capture; + int32_t input_channels; + }; +}; + +struct elliptic_system_configuration_parameters_cache + elliptic_system_configuration_cache = { { 0 }, 0 }; + +static struct elliptic_engine_version_info elliptic_engine_version_cache = { + 0xde, 0xad, 0xbe, 0xef +}; + +struct elliptic_engine_calibration_data { + union { + uint8_t reserved[ELLIPTIC_CALIBRATION_DATA_SIZE]; + }; +}; + +static struct elliptic_engine_calibration_data + elliptic_engine_calibration_data_cache = { .reserved = { + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef } }; + +struct elliptic_engine_calibration_v2_data { + union { + uint8_t reserved[ELLIPTIC_CALIBRATION_V2_DATA_SIZE]; + }; +}; + +static struct elliptic_engine_calibration_v2_data + elliptic_engine_calibration_v2_data_cache = { .reserved = { + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + } }; + +struct elliptic_engine_diagnostics_data { + union { + uint8_t reserved[ELLIPTIC_DIAGNOSTICS_DATA_SIZE]; + uint32_t values32[ELLIPTIC_DIAGNOSTICS_DATA_SIZE >> 2]; + }; +}; + +static struct elliptic_engine_diagnostics_data + elliptic_engine_diagnostics_data_cache = { .reserved = { 0 } }; + +struct elliptic_engine_ml_data { + union { + uint8_t reserved[ELLIPTIC_ML_DATA_SIZE]; + uint32_t u32[ELLIPTIC_ML_DATA_SIZE >> 2]; + }; +}; + +static struct elliptic_engine_ml_data elliptic_engine_ml_data_cache = { + .reserved = { 0 } +}; + +struct elliptic_engine_sensor_data { + union { + uint8_t reserved[ELLIPTIC_SENSOR_DATA_SIZE]; + uint32_t values32[ELLIPTIC_SENSOR_DATA_SIZE >> 2]; + }; +}; + +static struct elliptic_engine_sensor_data elliptic_engine_sensor_data_cache = { + .reserved = { 0 } +}; + +struct elliptic_engine_branch_info { + char build_branch[ELLIPTIC_BRANCH_INFO_MAX_SIZE]; +}; + +static struct elliptic_engine_branch_info elliptic_engine_branch_cache = { + { 0 } +}; + +struct elliptic_engine_tag_info { + char engine_tag[ELLIPTIC_TAG_INFO_SIZE]; +}; + +static struct elliptic_engine_tag_info elliptic_engine_tag_cache = { { 0 } }; + +static struct elliptic_shared_data_block shared_data_blocks[] = { + { ELLIPTIC_OBJ_ID_CALIBRATION_DATA, ELLIPTIC_CALIBRATION_DATA_SIZE, + &elliptic_engine_calibration_data_cache }, + + { ELLIPTIC_OBJ_ID_VERSION_INFO, ELLIPTIC_VERSION_INFO_SIZE, + &elliptic_engine_version_cache }, + { ELLIPTIC_OBJ_ID_BRANCH_INFO, ELLIPTIC_BRANCH_INFO_MAX_SIZE, + &elliptic_engine_branch_cache }, + { ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA, + ELLIPTIC_CALIBRATION_V2_DATA_SIZE, + &elliptic_engine_calibration_v2_data_cache }, + { ELLIPTIC_OBJ_ID_DIAGNOSTICS_DATA, ELLIPTIC_DIAGNOSTICS_DATA_SIZE, + &elliptic_engine_diagnostics_data_cache }, + { ELLIPTIC_OBJ_ID_TAG_INFO, ELLIPTIC_TAG_INFO_SIZE, + &elliptic_engine_tag_cache }, + { ELLIPTIC_OBJ_ID_ML_DATA, ELLIPTIC_ML_DATA_SIZE, + &elliptic_engine_ml_data_cache }, +}; + +void elliptic_set_calibration_data(uint8_t *calib_data, size_t size) +{ + struct elliptic_shared_data_block *calibration_obj = NULL; + + if (size == ELLIPTIC_CALIBRATION_DATA_SIZE) { + calibration_obj = elliptic_get_shared_obj( + ELLIPTIC_OBJ_ID_CALIBRATION_DATA); + memcpy((uint8_t *)&elliptic_engine_calibration_data_cache, + calib_data, size); + } + if (size == ELLIPTIC_CALIBRATION_V2_DATA_SIZE) { + calibration_obj = elliptic_get_shared_obj( + ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA); + memcpy((uint8_t *)&elliptic_engine_calibration_v2_data_cache, + calib_data, size); + } + if (calibration_obj == NULL) { + EL_PRINT_E("ell..set_calibration_data() calib=NULL (%zu)", + size); + return; + } + memcpy((u8 *)calibration_obj->buffer, calib_data, size); +} + +void elliptic_set_diagnostics_data(uint8_t *diag_data, size_t size) +{ + struct elliptic_shared_data_block *diagnostics_obj = NULL; + + if (size <= ELLIPTIC_DIAGNOSTICS_DATA_SIZE) { + diagnostics_obj = elliptic_get_shared_obj( + ELLIPTIC_OBJ_ID_DIAGNOSTICS_DATA); + if (diagnostics_obj == NULL) { + EL_PRINT_E("el..set_diagnostics_data() NULL (%zu)", + size); + return; + } + memcpy((uint8_t *)&elliptic_engine_diagnostics_data_cache, + diag_data, size); + memcpy((u8 *)diagnostics_obj->buffer, diag_data, size); + } +} + +static const size_t NUM_SHARED_RW_OBJS = + sizeof(shared_data_blocks) / sizeof(struct elliptic_shared_data_block); + +struct elliptic_shared_data_block *elliptic_get_shared_obj(uint32_t object_id) +{ + size_t i; + + for (i = 0; i < NUM_SHARED_RW_OBJS; ++i) { + if (shared_data_blocks[i].object_id == object_id) + return &shared_data_blocks[i]; + } + + return NULL; +} + +static const char *const ultrasound_enable_texts[] = { "Off", "On" }; + +static const struct soc_enum elliptic_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ultrasound_enable_texts), + ultrasound_enable_texts), +}; + +int get_elliptic_calibration_data(uint8_t *caldata, uint32_t max_size) +{ + uint32_t copied; + + copied = ELLIPTIC_CALIBRATION_DATA_SIZE; + if (max_size < ELLIPTIC_CALIBRATION_DATA_SIZE) { + copied = max_size; + EL_PRINT_D("size mismatch : %u vs %u", + (uint32_t)ELLIPTIC_CALIBRATION_DATA_SIZE, max_size); + } + + memcpy(caldata, (uint8_t *)&elliptic_engine_calibration_data_cache, + max_size); + return copied; +} + +int get_elliptic_calibration_v2_data(uint8_t *caldata, uint32_t max_size) +{ + uint32_t copied; + + copied = ELLIPTIC_CALIBRATION_V2_DATA_SIZE; + if (max_size < ELLIPTIC_CALIBRATION_V2_DATA_SIZE) { + copied = max_size; + EL_PRINT_D("size mismatch : %u vs %u", + (uint32_t)ELLIPTIC_CALIBRATION_V2_DATA_SIZE, + max_size); + } + + memcpy(caldata, (uint8_t *)&elliptic_engine_calibration_v2_data_cache, + max_size); + return copied; +} + +int get_elliptic_diagnostics_data(uint8_t *diagdata, uint32_t max_size) +{ + uint32_t copied; + + copied = ELLIPTIC_DIAGNOSTICS_DATA_SIZE; + if (max_size < ELLIPTIC_DIAGNOSTICS_DATA_SIZE) { + copied = max_size; + EL_PRINT_D("size mismatch : %u vs %u", + (uint32_t)ELLIPTIC_DIAGNOSTICS_DATA_SIZE, max_size); + } + + memcpy(diagdata, (uint8_t *)&elliptic_engine_diagnostics_data_cache, + max_size); + return copied; +} + +static uint32_t ultrasound_enable_cache; + +int elliptic_ultrasound_enable_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ultrasound_enable_cache; + return 0; +} + +int elliptic_ultrasound_enable_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + static bool triggered_engine_info; + int32_t msg[4] = { 0, 0, 0, 0 }; + + ultrasound_enable_cache = ucontrol->value.integer.value[0]; + + if (!triggered_engine_info && ultrasound_enable_cache) { + triggered_engine_info = true; + elliptic_trigger_version_msg(); + elliptic_trigger_branch_msg(); + elliptic_trigger_tag_msg(); + } + + msg[0] = ultrasound_enable_cache ? 1 : 0; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} + +static uint32_t ultrasound_tx_port_cache; + +int elliptic_ultrasound_tx_port_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ultrasound_tx_port_cache; + return 0; +} + +int elliptic_ultrasound_tx_port_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret; + + if (ultrasound_tx_port_cache == ucontrol->value.integer.value[0]) { + EL_PRINT_E( + "ultrasound_tx_port_set: ignoring duplicate request"); + return 0; + } + + ultrasound_tx_port_cache = ucontrol->value.integer.value[0]; + if (ultrasound_tx_port_cache) + ret = elliptic_open_port(ULTRASOUND_TX_PORT_ID); + else + ret = elliptic_close_port(ULTRASOUND_TX_PORT_ID); + + EL_PRINT_E("ultrasound_tx_port: enable=%d ret=%d", + ultrasound_tx_port_cache, ret); + + return ret; +} + +static uint32_t ultrasound_rx_port_cache; + +int elliptic_ultrasound_rx_port_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ultrasound_rx_port_cache; + return 0; +} + +int elliptic_ultrasound_rx_port_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret; + + if (ultrasound_rx_port_cache == ucontrol->value.integer.value[0]) { + EL_PRINT_E( + "ultrasound_rx_port_set: ignoring duplicate request"); + return 0; + } + + ultrasound_rx_port_cache = ucontrol->value.integer.value[0]; + if (ultrasound_rx_port_cache) + ret = elliptic_open_port(ULTRASOUND_RX_PORT_ID); + else + ret = elliptic_close_port(ULTRASOUND_RX_PORT_ID); + + EL_PRINT_E("ultrasound_rx_port: enable=%d ret=%d", + ultrasound_tx_port_cache, ret); + + return 0; +} + +int elliptic_ultrasound_rampdown_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* Rampdown is a strobe, so always return Off */ + ucontrol->value.integer.value[0] = 0; + return 0; +} + +int elliptic_ultrasound_rampdown_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t msg[4] = { -1, 0, 0, 0 }; + + if (ucontrol->value.integer.value[0] == 0) + return 0; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} + +int elliptic_ultrasound_diagnostics_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* Diagnostics is a strobe, so always return Off */ + ucontrol->value.integer.value[0] = 0; + return 0; +} + +int elliptic_ultrasound_request_diagnostics(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t msg[3] = { ESCPT_ENGINE_DIAGNOSTICS, 0, 0 }; + + if (ucontrol->value.integer.value[0] == 0) + return 0; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} + +int elliptic_system_configuration_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &elliptic_system_configuration, + ELLIPTIC_SYSTEM_CONFIGURATION_SIZE); + return 0; +} + +int elliptic_system_configuration_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&elliptic_system_configuration, ucontrol->value.bytes.data, + ELLIPTIC_SYSTEM_CONFIGURATION_SIZE); + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)&elliptic_system_configuration, + ELLIPTIC_SYSTEM_CONFIGURATION_SIZE); +} + +int elliptic_calibration_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, + &elliptic_engine_calibration_data_cache, + ELLIPTIC_CALIBRATION_DATA_SIZE); + return 0; +} + +int elliptic_calibration_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&elliptic_engine_calibration_data_cache, + ucontrol->value.bytes.data, ELLIPTIC_CALIBRATION_DATA_SIZE); + + return elliptic_data_write( + ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)&elliptic_engine_calibration_data_cache, + ELLIPTIC_CALIBRATION_DATA_SIZE); +} + +int elliptic_calibration_v2_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct elliptic_shared_data_block *calibration_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA); + + if (calibration_obj == NULL) { + EL_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + memcpy(ucontrol->value.bytes.data, calibration_obj->buffer, + ELLIPTIC_CALIBRATION_V2_DATA_SIZE); + return 0; +} + +int elliptic_calibration_v2_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&elliptic_engine_calibration_v2_data_cache, + ucontrol->value.bytes.data, ELLIPTIC_CALIBRATION_V2_DATA_SIZE); + + return elliptic_data_write( + ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)&elliptic_engine_calibration_v2_data_cache, + ELLIPTIC_CALIBRATION_V2_DATA_SIZE); +} + +int elliptic_diagnostics_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, + &elliptic_engine_diagnostics_data_cache, + ELLIPTIC_DIAGNOSTICS_DATA_SIZE); + return 0; +} + +int elliptic_diagnostics_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int elliptic_ml_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct elliptic_shared_data_block *ml_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_ML_DATA); + + if (ml_obj == NULL) { + EL_PRINT_E("ml_obj is NULL"); + return -EINVAL; + } + + memcpy(ucontrol->value.bytes.data, ml_obj->buffer, + ELLIPTIC_ML_DATA_SIZE); + return 0; +} + +int elliptic_ml_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)ucontrol->value.bytes.data, + ELLIPTIC_ML_DATA_SIZE); +} + +int elliptic_sensor_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &elliptic_engine_sensor_data_cache, + ELLIPTIC_SENSOR_DATA_SIZE); + return 0; +} + +int elliptic_sensor_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&elliptic_engine_sensor_data_cache, ucontrol->value.bytes.data, + ELLIPTIC_SENSOR_DATA_SIZE); + + return elliptic_data_write( + ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)&elliptic_engine_sensor_data_cache, + ELLIPTIC_SENSOR_DATA_SIZE); +} + +int elliptic_version_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &elliptic_engine_version_cache, + ELLIPTIC_VERSION_INFO_SIZE); + return 0; +} + +int elliptic_version_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int elliptic_branch_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &elliptic_engine_branch_cache, + ELLIPTIC_BRANCH_INFO_MAX_SIZE); + return 0; +} + +int elliptic_branch_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int elliptic_tag_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &elliptic_engine_tag_cache, + ELLIPTIC_TAG_INFO_SIZE); + return 0; +} + +int elliptic_tag_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int elliptic_calibration_param_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + if (mc->reg != ELLIPTIC_CALIBRATION) + return -EINVAL; + + switch (mc->shift) { + case ELLIPTIC_CALIBRATION_STATE: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.calibration_state; + break; + + case ELLIPTIC_CALIBRATION_PROFILE: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.calibration_profile; + break; + + case ELLIPTIC_ULTRASOUND_GAIN: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.ultrasound_gain; + break; + + default: + return -EINVAL; + } + + return 1; +} + +int elliptic_calibration_param_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct elliptic_system_configuration_parameter param; + + if (mc->reg != ELLIPTIC_CALIBRATION) + return -EINVAL; + + switch (mc->shift) { + case ELLIPTIC_CALIBRATION_STATE: + elliptic_system_configuration_cache.calibration_state = + ucontrol->value.integer.value[0]; + + param.type = ESCPT_CALIBRATION_STATE; + param.calibration_state = + elliptic_system_configuration_cache.calibration_state; + break; + + case ELLIPTIC_CALIBRATION_PROFILE: + elliptic_system_configuration_cache.calibration_profile = + ucontrol->value.integer.value[0]; + + param.type = ESCPT_CALIBRATION_PROFILE; + param.calibration_profile = + elliptic_system_configuration_cache.calibration_profile; + break; + + case ELLIPTIC_ULTRASOUND_GAIN: + elliptic_system_configuration_cache.ultrasound_gain = + ucontrol->value.integer.value[0]; + param.type = ESCPT_ULTRASOUND_GAIN; + param.ultrasound_gain = + elliptic_system_configuration_cache.ultrasound_gain; + break; + + default: + return -EINVAL; + } + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, (u8 *)¶m, + sizeof(param)); +} + +int elliptic_system_configuration_param_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + pr_err("%s: reg: %d shift: %d\n", __func__, mc->reg, mc->shift); + + if (mc->reg != ELLIPTIC_SYSTEM_CONFIGURATION) + return -EINVAL; + + if (mc->shift >= ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0 && + mc->shift <= ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15) { + EL_PRINT_E( + "get ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_%02d", + mc->shift - + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0); + ucontrol->value.integer.value[0] = 0; + return 1; + } + + switch (mc->shift) { + case ELLIPTIC_SYSTEM_CONFIGURATION_LATENCY: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.latency; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_SENSITIVITY: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.sensitivity; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_SPEAKER_SCALING: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.speaker_scaling[0]; + ucontrol->value.integer.value[1] = + elliptic_system_configuration_cache.speaker_scaling[1]; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_MICROPHONE_INDEX: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.microphone_index; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.operation_mode; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.operation_mode_flags; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_LOG_LEVEL: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.log_level; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_SUSPEND: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.engine_suspend; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_ENABLED: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.input_enabled; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_OUTPUT_ENABLED: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.output_enabled; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_EXTERNAL_EVENT: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.external_event; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_CALIBRATION_METHOD: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.calibration_method; + case ELLIPTIC_SYSTEM_CONFIGURATION_DEBUG_MODE: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.debug_mode; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_CONTEXT: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.context; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_CAPTURE: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.capture; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_CHANNELS: + ucontrol->value.integer.value[0] = + elliptic_system_configuration_cache.input_channels; + break; + + default: + EL_PRINT_E("Invalid mixer control"); + return -EINVAL; + } + + return 1; +} + +int elliptic_system_configuration_param_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct elliptic_system_configuration_parameter param; + struct timeval tv; + + if (mc->reg != ELLIPTIC_SYSTEM_CONFIGURATION) + return -EINVAL; + + if (mc->shift >= ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0 && + mc->shift <= ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15) { + const size_t csi = + mc->shift - + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0; + EL_PRINT_E( + "ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_XX csi:%zu", + csi); + if (csi >= ARRAY_SIZE(elliptic_system_configuration_cache + .custom_settings)) + return -EINVAL; + EL_PRINT_E("ucontrol->value.integer.value[0]:%ld", + ucontrol->value.integer.value[0]); + elliptic_system_configuration_cache.custom_settings[csi] = + ucontrol->value.integer.value[0]; + param.type = ESCPT_ENGINE_CUSTOM_SETTING_0 + csi; + param.custom_setting = ucontrol->value.integer.value[0]; + EL_PRINT_E( + "calling elliptic_data_write(custom_setting) csi:%zu", + csi); + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)¶m, sizeof(param)); + } + + switch (mc->shift) { + case ELLIPTIC_SYSTEM_CONFIGURATION_LATENCY: + elliptic_system_configuration_cache.latency = + ucontrol->value.integer.value[0]; + param.type = ESCPT_LATENCY; + param.latency = elliptic_system_configuration_cache.latency; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_SENSITIVITY: + elliptic_system_configuration_cache.sensitivity = + ucontrol->value.integer.value[0]; + param.type = ESCPT_CHANNEL_SENSITIVITY; + param.sensitivity = + elliptic_system_configuration_cache.sensitivity; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_SPEAKER_SCALING: + elliptic_system_configuration_cache.speaker_scaling[0] = + ucontrol->value.integer.value[0]; + elliptic_system_configuration_cache.speaker_scaling[1] = + ucontrol->value.integer.value[1]; + param.type = ESCPT_SPEAKER_SCALING; + param.speaker_scaling[0] = + elliptic_system_configuration_cache.speaker_scaling[0]; + param.speaker_scaling[1] = + elliptic_system_configuration_cache.speaker_scaling[1]; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_MICROPHONE_INDEX: + elliptic_system_configuration_cache.microphone_index = + ucontrol->value.integer.value[0]; + param.type = ESCPT_MICROPHONE_INDEX; + param.microphone_index = + elliptic_system_configuration_cache.microphone_index; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE: + elliptic_system_configuration_cache.operation_mode = + ucontrol->value.integer.value[0]; + param.type = ESCPT_OPERATION_MODE; + param.operation_mode = + elliptic_system_configuration_cache.operation_mode; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS: + elliptic_system_configuration_cache.operation_mode_flags = + ucontrol->value.integer.value[0]; + param.type = ESCPT_OPERATION_MODE_FLAGS; + param.operation_mode_flags = + elliptic_system_configuration_cache.operation_mode_flags; + break; + + case ELLIPTIC_SYSTEM_CONFIGURATION_LOG_LEVEL: + elliptic_system_configuration_cache.log_level = + ucontrol->value.integer.value[0]; + param.type = ESCPT_LOG_LEVEL; + param.log_level = elliptic_system_configuration_cache.log_level; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_ENABLED: + elliptic_system_configuration_cache.input_enabled = + ucontrol->value.integer.value[0]; + param.type = ESCPT_INPUT_ENABLED; + param.input_enabled = + elliptic_system_configuration_cache.input_enabled; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_OUTPUT_ENABLED: + elliptic_system_configuration_cache.output_enabled = + ucontrol->value.integer.value[0]; + param.type = ESCPT_OUTPUT_ENABLED; + param.output_enabled = + elliptic_system_configuration_cache.output_enabled; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_SUSPEND: + elliptic_system_configuration_cache.engine_suspend = + ucontrol->value.integer.value[0]; + param.type = ESCPT_SUSPEND; + param.engine_suspend = + elliptic_system_configuration_cache.engine_suspend; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_EXTERNAL_EVENT: + elliptic_system_configuration_cache.external_event = + ucontrol->value.integer.value[0]; + param.type = ESCPT_EXTERNAL_EVENT; + param.external_event = + elliptic_system_configuration_cache.external_event; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_CALIBRATION_METHOD: + elliptic_system_configuration_cache.calibration_method = + ucontrol->value.integer.value[0]; + param.type = ESCPT_CALIBRATION_METHOD; + param.calibration_method = + elliptic_system_configuration_cache.calibration_method; + do_gettimeofday(&tv); + param.calibration_timestamp = (int32_t)tv.tv_sec; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_DEBUG_MODE: + elliptic_system_configuration_cache.debug_mode = + ucontrol->value.integer.value[0]; + param.type = ESCPT_DEBUG_MODE; + param.debug_mode = + elliptic_system_configuration_cache.debug_mode; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_CONTEXT: + elliptic_system_configuration_cache.context = + ucontrol->value.integer.value[0]; + param.type = ESCPT_CONTEXT; + param.context = elliptic_system_configuration_cache.context; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_CAPTURE: + elliptic_system_configuration_cache.capture = + ucontrol->value.integer.value[0]; + param.type = ESCPT_CAPTURE; + param.context = elliptic_system_configuration_cache.capture; + break; + case ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_CHANNELS: + elliptic_system_configuration_cache.input_channels = + ucontrol->value.integer.value[0]; + param.type = ESCPT_INPUT_CHANNELS; + param.context = + elliptic_system_configuration_cache.input_channels; + break; + + default: + return -EINVAL; + } + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)¶m, sizeof(param)); +} + +static const struct snd_kcontrol_new ultrasound_filter_mixer_controls[] = { + SOC_ENUM_EXT("Ultrasound Enable", elliptic_enum[0], + elliptic_ultrasound_enable_get, + elliptic_ultrasound_enable_set), + SOC_ENUM_EXT("Ultrasound RampDown", elliptic_enum[0], + elliptic_ultrasound_rampdown_get, + elliptic_ultrasound_rampdown_set), + SOC_SINGLE_EXT("Ultrasound Latency", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_LATENCY, 10000, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Sensitivity", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_SENSITIVITY, 1000000, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_DOUBLE_EXT("Ultrasound Speaker Scaling", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_SPEAKER_SCALING, 0, + 1000000, 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Microphone Index", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_MICROPHONE_INDEX, 20, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Mode", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE, 255, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Mode Flags", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS, 256, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Calibration Profile", ELLIPTIC_CALIBRATION, + ELLIPTIC_CALIBRATION_PROFILE, 256, 0, + elliptic_calibration_param_get, + elliptic_calibration_param_put), + SOC_SINGLE_EXT("Ultrasound Gain", ELLIPTIC_CALIBRATION, + ELLIPTIC_ULTRASOUND_GAIN, 256, 0, + elliptic_calibration_param_get, + elliptic_calibration_param_put), + + SOC_SINGLE_EXT("Ultrasound Calibration State", ELLIPTIC_CALIBRATION, + ELLIPTIC_CALIBRATION_STATE, 256, 0, + elliptic_calibration_param_get, + elliptic_calibration_param_put), + + SND_SOC_BYTES_EXT("Ultrasound System Configuration", + ELLIPTIC_SYSTEM_CONFIGURATION_SIZE, + elliptic_system_configuration_get, + elliptic_system_configuration_put), + SND_SOC_BYTES_EXT( + "Ultrasound Calibration Data", ELLIPTIC_CALIBRATION_DATA_SIZE, + elliptic_calibration_data_get, elliptic_calibration_data_put), + SND_SOC_BYTES_EXT("Ultrasound Version", ELLIPTIC_VERSION_INFO_SIZE, + elliptic_version_data_get, elliptic_version_data_put), + SND_SOC_BYTES_EXT("Ultrasound Branch", ELLIPTIC_BRANCH_INFO_MAX_SIZE, + elliptic_branch_data_get, elliptic_branch_data_put), + SND_SOC_BYTES_EXT("Ultrasound Tag", ELLIPTIC_TAG_INFO_SIZE, + elliptic_tag_data_get, elliptic_tag_data_put), + SOC_SINGLE_EXT("Ultrasound Log Level", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_LOG_LEVEL, 7, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + + SND_SOC_BYTES_EXT("Ultrasound Calibration Ext Data", + ELLIPTIC_CALIBRATION_V2_DATA_SIZE, + elliptic_calibration_v2_data_get, + elliptic_calibration_v2_data_put), + + SND_SOC_BYTES_EXT( + "Ultrasound Diagnostics Data", ELLIPTIC_DIAGNOSTICS_DATA_SIZE, + elliptic_diagnostics_data_get, elliptic_diagnostics_data_put), + + SOC_ENUM_EXT("Ultrasound Diagnostics Request", elliptic_enum[0], + elliptic_ultrasound_diagnostics_get, + elliptic_ultrasound_request_diagnostics), + + SOC_SINGLE_EXT("Ultrasound Custom Setting 0", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 1", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_1, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 2", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_2, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 3", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_3, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 4", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_4, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 5", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_5, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 6", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_6, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 7", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_7, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 8", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_8, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 9", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_9, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 10", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_10, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 11", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_11, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 12", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_12, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 13", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_13, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 14", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_14, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Custom Setting 15", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15, + ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, + 0, elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_ENUM_EXT("Ultrasound Tx Port", elliptic_enum[0], + elliptic_ultrasound_tx_port_get, + elliptic_ultrasound_tx_port_set), + SOC_ENUM_EXT("Ultrasound Rx Port", elliptic_enum[0], + elliptic_ultrasound_rx_port_get, + elliptic_ultrasound_rx_port_set), + SOC_SINGLE_EXT("Ultrasound Suspend", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_SUSPEND, 1, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Input", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_ENABLED, 1, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Output", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_OUTPUT_ENABLED, 1, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Event", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_EXTERNAL_EVENT, 256, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Calibration Method", + ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CALIBRATION_METHOD, 256, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + + SND_SOC_BYTES_EXT("Ultrasound ML", ELLIPTIC_ML_DATA_SIZE, + elliptic_ml_data_get, elliptic_ml_data_put), + + SOC_SINGLE_EXT("Ultrasound Debug Mode", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_DEBUG_MODE, 256, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SOC_SINGLE_EXT("Ultrasound Context", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CONTEXT, + ELLIPTIC_SYSTEM_CONFIGURATION_MAX_CONTEXT_VALUE, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + SND_SOC_BYTES_EXT("Ultrasound Sensor Data", ELLIPTIC_SENSOR_DATA_SIZE, + elliptic_sensor_data_get, elliptic_sensor_data_put), + + SOC_SINGLE_EXT("Ultrasound Capture", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_CAPTURE, 256, -1, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + + SOC_SINGLE_EXT("Ultrasound Tx Channels", ELLIPTIC_SYSTEM_CONFIGURATION, + ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_CHANNELS, 16, 0, + elliptic_system_configuration_param_get, + elliptic_system_configuration_param_put), + +}; + +unsigned int elliptic_add_platform_controls(void *platform) +{ + const unsigned int num_controls = + ARRAY_SIZE(ultrasound_filter_mixer_controls); + + if (platform != NULL) { + snd_soc_add_platform_controls( + (struct snd_soc_platform *)platform, + ultrasound_filter_mixer_controls, num_controls); + } else { + EL_PRINT_E("pointer is NULL"); + } + + return num_controls; +} +EXPORT_SYMBOL(elliptic_add_platform_controls); + +int elliptic_trigger_version_msg(void) +{ + int32_t msg[3] = { ESCPT_ENGINE_VERSION, 0, 0 }; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} + +int elliptic_trigger_branch_msg(void) +{ + int32_t msg[3] = { ESCPT_BUILD_BRANCH, 0, 0 }; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} + +int elliptic_trigger_tag_msg(void) +{ + int32_t msg[3] = { ESCPT_ENGINE_TAG, 0, 0 }; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} + +int elliptic_trigger_diagnostics_msg(void) +{ + int32_t msg[3] = { ESCPT_ENGINE_DIAGNOSTICS, 0, 0 }; + + return elliptic_data_write(ELLIPTIC_ULTRASOUND_SET_PARAMS, + (const char *)msg, sizeof(msg)); +} diff --git a/techpack/audio/dsp/elliptic/elliptic_sysfs.c b/techpack/audio/dsp/elliptic/elliptic_sysfs.c new file mode 100644 index 000000000000..27c5aecbc0d1 --- /dev/null +++ b/techpack/audio/dsp/elliptic/elliptic_sysfs.c @@ -0,0 +1,648 @@ +#include +#include +#include +#include +#include +#include +#include +#include "elliptic_version.h" +#include + +#define ELLIPTIC_DIAGNOSTICS_DATA_SECTION_COUNT 16 +#define ELLIPTIC_CALIBRATION_MAX_DISPLAY_COUNT 96 +#define ELLIPTIC_ML_DISPLAY_COUNT 16 + +static int kobject_create_and_add_failed; +static int sysfs_create_group_failed; + +extern struct elliptic_system_configuration_parameters_cache + elliptic_system_configuration_cache; + +static ssize_t calibration_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + ssize_t result; + + struct elliptic_shared_data_block *calibration_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_CALIBRATION_DATA); + + if (calibration_obj == NULL) { + EL_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (count > calibration_obj->size) { + EL_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(calibration_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t calibration_v2_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t result; + + struct elliptic_shared_data_block *calibration_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA); + + if (calibration_obj == NULL) { + EL_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (count > calibration_obj->size) { + EL_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(calibration_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t diagnostics_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + ssize_t result; + + struct elliptic_shared_data_block *diagnostics_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_DIAGNOSTICS_DATA); + + if (diagnostics_obj == NULL) { + EL_PRINT_E("diagnostics_obj is NULL"); + return -EINVAL; + } + + if (count > diagnostics_obj->size) { + EL_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(diagnostics_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t ml_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t result; + + struct elliptic_shared_data_block *ml_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_ML_DATA); + + if (ml_obj == NULL) { + EL_PRINT_E("ml_obj is NULL"); + return -EINVAL; + } + + if (count > ml_obj->size) { + EL_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(ml_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t calibration_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + ssize_t result; + int length; + int i; + uint8_t *caldata; + + struct elliptic_shared_data_block *calibration_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_CALIBRATION_DATA); + + if (kobject_create_and_add_failed) + EL_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + EL_PRINT_E("sysfs_create_group_failed"); + + if (calibration_obj == NULL) { + EL_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (calibration_obj->size > PAGE_SIZE) { + EL_PRINT_E("calibration_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + caldata = (uint8_t *)calibration_obj->buffer; + length = 0; + if (pretty) { + if (caldata[0] == 0xDE && caldata[1] == 0xAD) { + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Data: not loaded"); + } else { + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Data: "); + for (i = 0; i < calibration_obj->size; ++i) + length += snprintf(buf + length, + PAGE_SIZE - length, + "0x%02x ", caldata[i]); + } + } else { + for (i = 0; i < calibration_obj->size; ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + "0x%02x ", caldata[i]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t calibration_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return calibration_show_core(dev, attr, buf, 0); +} + +static ssize_t calibration_v2_show_core(struct device *dev, + struct device_attribute *attr, + char *buf, int pretty) +{ + ssize_t result; + int length; + int i; + uint8_t *caldata; + + struct elliptic_shared_data_block *calibration_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA); + + if (kobject_create_and_add_failed) + EL_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + EL_PRINT_E("sysfs_create_group_failed"); + + if (calibration_obj == NULL) { + EL_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (calibration_obj->size > PAGE_SIZE) { + EL_PRINT_E("calibration_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + caldata = (uint8_t *)calibration_obj->buffer; + length = 0; + if (pretty) { + if (caldata[0] == 0xDE && caldata[1] == 0xAD) { + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Ext Data: not loaded"); + } else { + int j = (ELLIPTIC_CALIBRATION_V2_DATA_SIZE >> 2) - 1; + + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Ext Data: "); + for (i = 0; i < ELLIPTIC_CALIBRATION_MAX_DISPLAY_COUNT; + ++i) + length += snprintf(buf + length, + PAGE_SIZE - length, + "0x%02x ", caldata[i]); + length += snprintf( + buf + length, PAGE_SIZE - length, + "\nTruncated at %d", + ELLIPTIC_CALIBRATION_MAX_DISPLAY_COUNT); + length += snprintf(buf + length, PAGE_SIZE - length, + "\nmisc: %u %u %u %u %u %u %u %u\n", + caldata[j - 7], caldata[j - 6], + caldata[j - 5], caldata[j - 4], + caldata[j - 3], caldata[j - 2], + caldata[j - 1], caldata[j]); + } + } else { + for (i = 0; i < calibration_obj->size; ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + "0x%02x ", caldata[i]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t calibration_v2_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return calibration_v2_show_core(dev, attr, buf, 0); +} + +static ssize_t diagnostics_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + ssize_t result; + int length; + uint32_t *data32; + int i; + + struct elliptic_shared_data_block *diagnostics_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_DIAGNOSTICS_DATA); + + if (kobject_create_and_add_failed) + EL_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + EL_PRINT_E("sysfs_create_group_failed"); + + if (diagnostics_obj == NULL) { + EL_PRINT_E("diagnostics_obj is NULL"); + return -EINVAL; + } + + if (diagnostics_obj->size > PAGE_SIZE) { + EL_PRINT_E("diagnostics_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + length = 0; + data32 = (uint32_t *)diagnostics_obj->buffer; + + if (pretty) { + length += snprintf(buf + length, PAGE_SIZE - length, + "Diagnostics:\n counters:\n"); + for (i = 0; i < ELLIPTIC_DIAGNOSTICS_DATA_SECTION_COUNT; i++) + length += snprintf(buf + length, PAGE_SIZE - length, + " %u %u %u %u\n", data32[4 * i], + data32[4 * i + 1], data32[4 * i + 2], + data32[4 * i + 3]); + } else { + for (i = 0; i < (diagnostics_obj->size >> 4); ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + " %u %u %u %u\n", data32[4 * i], + data32[4 * i + 1], data32[4 * i + 2], + data32[4 * i + 3]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t diagnostics_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return diagnostics_show_core(dev, attr, buf, 0); +} + +static ssize_t ml_show_core(struct device *dev, struct device_attribute *attr, + char *buf, int pretty) +{ + ssize_t result; + int length; + int i; + uint32_t *mldata; + + struct elliptic_shared_data_block *ml_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_ML_DATA); + + if (kobject_create_and_add_failed) + EL_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + EL_PRINT_E("sysfs_create_group_failed"); + + if (ml_obj == NULL) { + EL_PRINT_E("ml_obj is NULL"); + return -EINVAL; + } + + if (ml_obj->size > PAGE_SIZE) { + EL_PRINT_E("ml_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + mldata = (uint32_t *)ml_obj->buffer; + length = 0; + if (pretty) { + if (mldata[0] == 0x0 && mldata[1] == 0x0) { + length += snprintf(buf + length, PAGE_SIZE - length, + "ML Data: not loaded"); + } else { + length += snprintf(buf + length, PAGE_SIZE - length, + "ML Data: "); + for (i = 0; i < ELLIPTIC_ML_DISPLAY_COUNT; ++i) + length += snprintf(buf + length, + PAGE_SIZE - length, + "0x%08x ", mldata[i]); + length += snprintf(buf + length, PAGE_SIZE - length, + "\nTruncated at %d", + ELLIPTIC_ML_DISPLAY_COUNT); + } + } else { + int values = ml_obj->size >> 2; + + for (i = 0; i < values; ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + "0x%08x ", mldata[i]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t ml_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return ml_show_core(dev, attr, buf, 0); +} + +static ssize_t version_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + ssize_t result; + struct elliptic_engine_version_info *version_info; + int length; + + struct elliptic_shared_data_block *version_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_VERSION_INFO); + + if (kobject_create_and_add_failed) + EL_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + EL_PRINT_E("sysfs_create_group_failed"); + + if (version_obj == NULL) { + EL_PRINT_E("version_obj is NULL"); + return -EINVAL; + } + + if (version_obj->size > PAGE_SIZE) { + EL_PRINT_E("version_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + version_info = + (struct elliptic_engine_version_info *)version_obj->buffer; + + if (pretty) { + if (version_info->major == 0xDE && + version_info->minor == 0xAD) { + length = snprintf(buf, PAGE_SIZE, "Version: unknown\n"); + } else { + length = snprintf( + buf, PAGE_SIZE, "Version: %d.%d.%d.%d\n", + version_info->major, version_info->minor, + version_info->build, version_info->revision); + } + } else { + length = snprintf(buf, PAGE_SIZE, "%d.%d.%d.%d\n", + version_info->major, version_info->minor, + version_info->build, version_info->revision); + } + result = (ssize_t)length; + return result; +} + +static ssize_t version_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return version_show_core(dev, attr, buf, 0); +} + +static ssize_t branch_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + int length; + + struct elliptic_shared_data_block *branch_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_BRANCH_INFO); + + if (branch_obj == NULL) { + EL_PRINT_E("branch_obj not found"); + return 0; + } + + if (branch_obj->size > PAGE_SIZE) { + EL_PRINT_E("branch_obj->size > PAGE_SIZE"); + return -EINVAL; + } + if (pretty) { + length = snprintf(buf, PAGE_SIZE - 1, "Branch: %s\n", + (const char *)(branch_obj->buffer)); + } else { + length = snprintf(buf, PAGE_SIZE - 1, "%s\n", + (const char *)(branch_obj->buffer)); + } + + return (ssize_t)length; +} + +static ssize_t branch_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return branch_show_core(dev, attr, buf, 0); +} + +static ssize_t tag_show_core(struct device *dev, struct device_attribute *attr, + char *buf, int pretty) +{ + int length; + + struct elliptic_shared_data_block *tag_obj = + elliptic_get_shared_obj(ELLIPTIC_OBJ_ID_TAG_INFO); + + if (tag_obj == NULL) { + EL_PRINT_E("tag_obj not found"); + return 0; + } + + if (tag_obj->size > PAGE_SIZE) { + EL_PRINT_E("tag_obj->size > PAGE_SIZE"); + return -EINVAL; + } + if (pretty) { + length = snprintf(buf, PAGE_SIZE - 1, "Tag: %s\n", + (const char *)(tag_obj->buffer)); + } else { + length = snprintf(buf, PAGE_SIZE - 1, "%s\n", + (const char *)(tag_obj->buffer)); + } + + return (ssize_t)length; +} + +static ssize_t tag_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return tag_show_core(dev, attr, buf, 0); +} + +static ssize_t cache_show(char *buf, int pretty) +{ + struct elliptic_system_configuration_parameters_cache *cache = + &elliptic_system_configuration_cache; + + int length; + + length = snprintf(buf, PAGE_SIZE - 1, "Cache:\n"); + length += snprintf(buf + length, PAGE_SIZE - 1, " mi:%d\n", + cache->microphone_index); + length += snprintf(buf + length, PAGE_SIZE - 1, " om:%d\n", + cache->operation_mode); + length += snprintf(buf + length, PAGE_SIZE - 1, " omf:%d\n", + cache->operation_mode_flags); + length += snprintf(buf + length, PAGE_SIZE - 1, " cs:%d\n", + cache->calibration_state); + length += snprintf(buf + length, PAGE_SIZE - 1, " cp:%d\n", + cache->calibration_profile); + length += snprintf(buf + length, PAGE_SIZE - 1, " ug:%d\n", + cache->ultrasound_gain); + length += snprintf(buf + length, PAGE_SIZE - 1, " ll:%d\n", + cache->log_level); + length += snprintf(buf + length, PAGE_SIZE - 1, " es:%d\n", + cache->engine_suspend); + + return (ssize_t)length; +} + +static ssize_t opmode_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int length; + ssize_t result; + + struct elliptic_system_configuration_parameters_cache *cache = + &elliptic_system_configuration_cache; + + length += snprintf(buf + length, PAGE_SIZE - 1, "%d\n", + cache->operation_mode); + result = (ssize_t)length; + return result; +} + +static ssize_t opmode_flags_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int length; + ssize_t result; + struct elliptic_system_configuration_parameters_cache *cache = + &elliptic_system_configuration_cache; + + length += snprintf(buf + length, PAGE_SIZE - 1, "%d\n", + cache->operation_mode_flags); + result = (ssize_t)length; + return result; +} + +static ssize_t driver_version_show(char *buf) +{ + int length; + + length = snprintf(buf, PAGE_SIZE, "Driver version: %s-%s (%s)\n", + build_name, build_number, build_source_version); + + return (ssize_t)length; +} + +static ssize_t state_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int length = 0; + + length += driver_version_show(buf + length); + length += version_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += branch_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += tag_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += calibration_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += calibration_v2_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += diagnostics_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += ml_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += cache_show(buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + return (ssize_t)length; +} + +static struct device_attribute calibration_attr = __ATTR_RW(calibration); +static struct device_attribute version_attr = __ATTR_RO(version); +static struct device_attribute branch_attr = __ATTR_RO(branch); +static struct device_attribute calibration_v2_attr = __ATTR_RW(calibration_v2); +static struct device_attribute diagnostics_attr = __ATTR_RW(diagnostics); +static struct device_attribute state_attr = __ATTR_RO(state); +static struct device_attribute tag_attr = __ATTR_RO(tag); +static struct device_attribute ml_attr = __ATTR_RW(ml); +static struct device_attribute opmode_attr = __ATTR_RO(opmode); +static struct device_attribute opmode_flags_attr = __ATTR_RO(opmode_flags); + +static struct attribute *elliptic_attrs[] = { + &calibration_attr.attr, + &version_attr.attr, + &branch_attr.attr, + &calibration_v2_attr.attr, + &diagnostics_attr.attr, + &state_attr.attr, + &tag_attr.attr, + &ml_attr.attr, + &opmode_attr.attr, + &opmode_flags_attr.attr, + NULL, +}; + +static struct attribute_group elliptic_attr_group = { + .name = ELLIPTIC_SYSFS_ENGINE_FOLDER, + .attrs = elliptic_attrs, +}; + +static struct kobject *elliptic_sysfs_kobj; + +int elliptic_initialize_sysfs(void) +{ + int err; + + elliptic_sysfs_kobj = kobject_create_and_add(ELLIPTIC_SYSFS_ROOT_FOLDER, + kernel_kobj->parent); + + if (!elliptic_sysfs_kobj) { + kobject_create_and_add_failed = 1; + EL_PRINT_E("failed to create kobj"); + return -ENOMEM; + } + + err = sysfs_create_group(elliptic_sysfs_kobj, &elliptic_attr_group); + + if (err) { + sysfs_create_group_failed = 1; + EL_PRINT_E("failed to create sysfs group"); + kobject_put(elliptic_sysfs_kobj); + return -ENOMEM; + } + + return 0; +} + +void elliptic_cleanup_sysfs(void) +{ + kobject_put(elliptic_sysfs_kobj); +} diff --git a/techpack/audio/dsp/elliptic/elliptic_version.h b/techpack/audio/dsp/elliptic/elliptic_version.h new file mode 100755 index 000000000000..1c8eb9af005d --- /dev/null +++ b/techpack/audio/dsp/elliptic/elliptic_version.h @@ -0,0 +1,8 @@ +#ifndef ELLIPTIC_VERSION_H +#define ELLIPTIC_VERSION_H + +#define build_name "Elliptic.LinuxKernelDriver.VendorDLKM.master" +#define build_number "20181016.1" +#define build_source_version "e5e26691554bba9b1438ec3d7e0cc55dfb296bb8" + +#endif //ELLIPTIC_VERSION_H diff --git a/techpack/audio/dsp/elliptic/io_modules/Makefile b/techpack/audio/dsp/elliptic/io_modules/Makefile new file mode 100644 index 000000000000..66ee789be57f --- /dev/null +++ b/techpack/audio/dsp/elliptic/io_modules/Makefile @@ -0,0 +1,2 @@ +# TODO: add config parameter for which io module to build +#obj-y += userspace/ diff --git a/techpack/audio/dsp/elliptic/io_modules/msm/elliptic_data_msm_io.c b/techpack/audio/dsp/elliptic/io_modules/msm/elliptic_data_msm_io.c new file mode 100644 index 000000000000..c237ad973dfd --- /dev/null +++ b/techpack/audio/dsp/elliptic/io_modules/msm/elliptic_data_msm_io.c @@ -0,0 +1,105 @@ +/** + * Copyright Elliptic Labs + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define IO_PING_PONG_BUFFER_SIZE 512 +#define AFE_MSM_RX_PSEUDOPORT_ID 0x8001 +#define AFE_MSM_TX_PSEUDOPORT_ID 0x8002 + +struct elliptic_msm_io_device {}; + +/* static struct elliptic_msm_io_device io_device;*/ + +int elliptic_data_io_initialize(void) +{ + return 0; +} + +int elliptic_data_io_cleanup(void) +{ + return 0; +} +int elliptic_io_open_port(int portid) +{ + if (portid == ULTRASOUND_RX_PORT_ID) + return afe_start_pseudo_port(AFE_MSM_RX_PSEUDOPORT_ID); + else + return afe_start_pseudo_port(AFE_MSM_TX_PSEUDOPORT_ID); +} + +int elliptic_io_close_port(int portid) +{ + if (portid == ULTRASOUND_RX_PORT_ID) + return afe_stop_pseudo_port(AFE_MSM_RX_PSEUDOPORT_ID); + else + return afe_stop_pseudo_port(AFE_MSM_TX_PSEUDOPORT_ID); +} + +int32_t elliptic_data_io_write(uint32_t message_id, const char *data, + size_t data_size) +{ + int32_t result = 0; + + /* msm_pcm_routing_acquire_lock(); */ + + result = ultrasound_apr_set_parameter(ELLIPTIC_PORT_ID, message_id, + (u8 *)data, (int32_t)data_size); + + /* msm_pcm_routing_release_lock();*/ + return result; +} + +int32_t elliptic_data_io_transact(uint32_t message_id, const char *data, + size_t data_size, char *output_data, + size_t output_data_size) +{ + pr_err("%s : unimplemented\n", __func__); + return -EINVAL; +} diff --git a/techpack/audio/dsp/elliptic/io_modules/userspace/Makefile b/techpack/audio/dsp/elliptic/io_modules/userspace/Makefile new file mode 100644 index 000000000000..907ddc20a1d9 --- /dev/null +++ b/techpack/audio/dsp/elliptic/io_modules/userspace/Makefile @@ -0,0 +1,2 @@ +# TODO: add config parameter for which io module to build +#obj-y += elliptic_data_io.o diff --git a/techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c b/techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c new file mode 100644 index 000000000000..24892b7e3faa --- /dev/null +++ b/techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c @@ -0,0 +1,263 @@ +/** + * Copyright Elliptic Labs + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static dev_t elliptic_userspace_ctrl_major; +#define USERSPACE_CTRL_IO_DEVICE_NAME "elliptic_us_ctrl_io" +struct elliptic_userspace_ctrl_device { + struct cdev cdev; + struct semaphore sem; + int ping_pong_idx; + size_t ping_pong_buffer_size[2]; + uint8_t ping_pong_buffer[2][ELLIPTIC_MSG_BUF_SIZE]; + wait_queue_head_t data_available; + struct mutex data_lock; + atomic_t data_state; +}; + +static struct elliptic_userspace_ctrl_device ctrl_device; + +static uint8_t *get_ping_buffer(struct elliptic_userspace_ctrl_device *dev, + /*out parameter*/ size_t *data_size) +{ + if (data_size != NULL) + *data_size = dev->ping_pong_buffer_size[dev->ping_pong_idx]; + + return dev->ping_pong_buffer[dev->ping_pong_idx]; +} + +static uint8_t *get_pong_buffer(struct elliptic_userspace_ctrl_device *dev, + /*out parameter*/ size_t *data_size) +{ + if (data_size != NULL) + *data_size = dev->ping_pong_buffer_size[1 - dev->ping_pong_idx]; + + return dev->ping_pong_buffer[1 - dev->ping_pong_idx]; +} + +static void set_pong_buffer_size(struct elliptic_userspace_ctrl_device *dev, + size_t data_size) +{ + dev->ping_pong_buffer_size[1 - dev->ping_pong_idx] = data_size; +} + +static void swap_ping_pong(struct elliptic_userspace_ctrl_device *dev) +{ + dev->ping_pong_idx = 1 - dev->ping_pong_idx; +} + +static int device_open(struct inode *inode, struct file *filp) +{ + if (inode->i_cdev != &ctrl_device.cdev) { + pr_warn("elliptic : dev pointer mismatch\n"); + return -ENODEV; /* No such device */ + } + + if (down_interruptible(&ctrl_device.sem) != 0) + return -EEXIST; + EL_PRINT_I("Opened device %s", USERSPACE_CTRL_IO_DEVICE_NAME); + return 0; +} + +static ssize_t device_read(struct file *fp, char __user *buff, + size_t user_buf_length, loff_t *ppos) +{ + size_t bytes_read; + unsigned long copy_result; + uint8_t *ping_buffer; + int result; + + if (user_buf_length < ELLIPTIC_MSG_BUF_SIZE) + EL_PRINT_E("user space buffer user_buf_length too small : %zu", + user_buf_length); + + bytes_read = 0; + copy_result = 0; + ping_buffer = NULL; + + result = wait_event_interruptible( + ctrl_device.data_available, + atomic_read(&ctrl_device.data_state) != 0); + if (result == 0) { + const int state = atomic_read(&ctrl_device.data_state); + + if (state > 0) { + result = mutex_lock_interruptible( + &ctrl_device.data_lock); + if (result == 0) { + swap_ping_pong(&ctrl_device); + + ping_buffer = get_ping_buffer(&ctrl_device, + &bytes_read); + + if (bytes_read > user_buf_length) { + EL_PRINT_E( + "ping buffer size %zu larger than user buffer", + bytes_read); + goto fail; + } + + copy_result = copy_to_user(buff, ping_buffer, + bytes_read); + if (copy_result > 0) { + EL_PRINT_E("Failed copy to user"); + goto fail; + } + + atomic_set(&ctrl_device.data_state, 0); + + mutex_unlock(&ctrl_device.data_lock); + } else if (result == -EINTR) { + EL_PRINT_E("lock interrupted"); + } else { + EL_PRINT_E("lock error = %d", result); + } + } else { + EL_PRINT_W("state = %d", state); + atomic_set(&ctrl_device.data_state, 0); + } + } else if (result == -ERESTARTSYS) { + EL_PRINT_E("interrupted"); + } else { + EL_PRINT_E("wait_event error = %d", result); + } + return bytes_read; +fail: + atomic_set(&ctrl_device.data_state, 0); + mutex_unlock(&ctrl_device.data_lock); + return 0; +} + +static int device_close(struct inode *inode, struct file *filp) +{ + up(&ctrl_device.sem); + EL_PRINT_I("Closed device %s", USERSPACE_CTRL_IO_DEVICE_NAME); + return 0; +} + +static const struct file_operations elliptic_userspace_ctrl_fops = { + .owner = THIS_MODULE, + .open = device_open, + .read = device_read, + .release = device_close, +}; + +int elliptic_userspace_ctrl_driver_init(void) +{ + struct device *device; + dev_t device_number; + int err; + + err = alloc_chrdev_region(&device_number, 0, 1, + USERSPACE_CTRL_IO_DEVICE_NAME); + + if (err < 0) { + pr_err("failed to allocate chrdev region\n"); + return err; + } + + elliptic_userspace_ctrl_major = MAJOR(device_number); + + device_number = MKDEV(elliptic_userspace_ctrl_major, 0); + device = device_create(elliptic_class, NULL, device_number, NULL, + USERSPACE_CTRL_IO_DEVICE_NAME); + + if (IS_ERR(device)) { + unregister_chrdev(elliptic_userspace_ctrl_major, + USERSPACE_CTRL_IO_DEVICE_NAME); + EL_PRINT_E("Failed to create the device\n"); + return PTR_ERR(device); + } + + cdev_init(&ctrl_device.cdev, &elliptic_userspace_ctrl_fops); + ctrl_device.cdev.owner = THIS_MODULE; + err = cdev_add(&ctrl_device.cdev, device_number, 1); + if (err) { + EL_PRINT_W("error %d while trying to add %s%d", err, + ELLIPTIC_DEVICENAME, 0); + return err; + } + + sema_init(&ctrl_device.sem, 1); + mutex_init(&ctrl_device.data_lock); + init_waitqueue_head(&ctrl_device.data_available); + return 0; +} + +void elliptic_userspace_ctrl_driver_exit(void) +{ + BUG_ON(elliptic_class == NULL); + device_destroy(elliptic_class, MKDEV(elliptic_userspace_ctrl_major, 0)); + cdev_del(&ctrl_device.cdev); + unregister_chrdev(elliptic_userspace_ctrl_major, + USERSPACE_CTRL_IO_DEVICE_NAME); + up(&ctrl_device.sem); +} + +int32_t elliptic_userspace_ctrl_write(uint32_t message_id, const char *data, + size_t data_size) +{ + uint8_t *pong_buffer; + + if (data_size > ELLIPTIC_MSG_BUF_SIZE) { + EL_PRINT_E("data size : %zu larger than buf size : %zu", + data_size, (size_t)ELLIPTIC_MSG_BUF_SIZE); + + return -EINVAL; + } + mutex_lock(&ctrl_device.data_lock); + + pong_buffer = get_pong_buffer(&ctrl_device, NULL); + set_pong_buffer_size(&ctrl_device, data_size); + + memcpy(pong_buffer, data, data_size); + wake_up_interruptible(&ctrl_device.data_available); + atomic_set(&ctrl_device.data_state, 1); + mutex_unlock(&ctrl_device.data_lock); + + return 0; +} diff --git a/techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_io.c b/techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_io.c new file mode 100644 index 000000000000..65e860081279 --- /dev/null +++ b/techpack/audio/dsp/elliptic/io_modules/userspace/elliptic_data_userspace_io.c @@ -0,0 +1,143 @@ +/** + * Copyright Elliptic Labs + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static dev_t elliptic_userspace_major; +#define USERSPACE_IO_DEVICE_NAME "elliptic_us_io" +struct elliptic_userspace_device { + struct cdev cdev; + struct semaphore sem; +}; + +static struct elliptic_userspace_device io_device; + +static int device_open(struct inode *inode, struct file *filp) +{ + if (inode->i_cdev != &io_device.cdev) { + pr_warn("elliptic : dev pointer mismatch\n"); + return -ENODEV; /* No such device */ + } + + if (down_interruptible(&io_device.sem) != 0) + return -EEXIST; + EL_PRINT_I("Opened device %s", USERSPACE_IO_DEVICE_NAME); + return 0; +} + +static ssize_t device_write(struct file *fp, const char __user *buff, + size_t length, loff_t *ppos) +{ + int push_result; + + push_result = elliptic_data_push(ELLIPTIC_ALL_DEVICES, buff, length, + ELLIPTIC_DATA_PUSH_FROM_USERSPACE); + + return push_result == 0 ? (ssize_t)length : (ssize_t)(-1); +} + +static int device_close(struct inode *inode, struct file *filp) +{ + up(&io_device.sem); + EL_PRINT_I("Closed device %s", USERSPACE_IO_DEVICE_NAME); + return 0; +} + +static const struct file_operations elliptic_userspace_fops = { + .owner = THIS_MODULE, + .open = device_open, + .write = device_write, + .release = device_close, +}; + +int elliptic_userspace_io_driver_init(void) +{ + struct device *device; + dev_t device_number; + int err; + + err = alloc_chrdev_region(&device_number, 0, 1, + USERSPACE_IO_DEVICE_NAME); + + if (err < 0) { + pr_err("failed to allocate chrdev region\n"); + return err; + } + + elliptic_userspace_major = MAJOR(device_number); + + device_number = MKDEV(elliptic_userspace_major, 0); + device = device_create(elliptic_class, NULL, device_number, NULL, + USERSPACE_IO_DEVICE_NAME); + + if (IS_ERR(device)) { + unregister_chrdev(elliptic_userspace_major, + USERSPACE_IO_DEVICE_NAME); + pr_err("Failed to create the device\n"); + return PTR_ERR(device); + } + + cdev_init(&io_device.cdev, &elliptic_userspace_fops); + io_device.cdev.owner = THIS_MODULE; + err = cdev_add(&io_device.cdev, device_number, 1); + if (err) { + EL_PRINT_W("error %d while trying to add %s%d", err, + ELLIPTIC_DEVICENAME, 0); + return err; + } + + sema_init(&io_device.sem, 1); + return 0; +} + +void elliptic_userspace_io_driver_exit(void) +{ + BUG_ON(elliptic_class == NULL); + device_destroy(elliptic_class, MKDEV(elliptic_userspace_major, 0)); + cdev_del(&io_device.cdev); + unregister_chrdev(elliptic_userspace_major, USERSPACE_IO_DEVICE_NAME); + up(&io_device.sem); +} diff --git a/techpack/audio/dsp/elliptic/io_modules/userspace_test/Makefile b/techpack/audio/dsp/elliptic/io_modules/userspace_test/Makefile new file mode 100644 index 000000000000..907ddc20a1d9 --- /dev/null +++ b/techpack/audio/dsp/elliptic/io_modules/userspace_test/Makefile @@ -0,0 +1,2 @@ +# TODO: add config parameter for which io module to build +#obj-y += elliptic_data_io.o diff --git a/techpack/audio/dsp/elliptic/io_modules/userspace_test/elliptic_data_io.c b/techpack/audio/dsp/elliptic/io_modules/userspace_test/elliptic_data_io.c new file mode 100644 index 000000000000..8f7c370c5d72 --- /dev/null +++ b/techpack/audio/dsp/elliptic/io_modules/userspace_test/elliptic_data_io.c @@ -0,0 +1,121 @@ +/** + * Copyright Elliptic Labs + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#define USE_IRQ 11 + +static struct task_struct *simulating_task; +static atomic_t cancel; + +struct elliptic_data_io_state {}; +#define BUFFER_SIZE 128 + +static int32_t output_buffer[BUFFER_SIZE]; + +irqreturn_t irq_handler(int irq, void *dev_id) +{ + int result; + + result = elliptic_data_push(ELLIPTIC_ALL_DEVICES, + (const char *)output_buffer, + BUFFER_SIZE * sizeof(int32_t)); + return 0; +} + +static void fill_buffer(int32_t *buffer, size_t len, int32_t value) +{ + size_t i; + + for (i = 0; i < len; ++i) + buffer[i] = value; +} + +int simulating_thread(void *context) +{ + static int32_t count; + int result; + + count = 0; + msleep(100); + + pr_debug("%s\n", __func__); + while (atomic_read(&cancel) == 0) { + if (kthread_should_stop()) + do_exit(0); + + fill_buffer(output_buffer, BUFFER_SIZE, count); + + ++count; + if (result != 0) { + pr_warn("failed to push data\n"); + } + asm("int $0x3B"); /* Corresponding to irq 11 */ + msleep(0); + } + return 0; +} + +int32_t elliptic_data_io_write(uint32_t message_id, const char *data, + size_t data_size) +{ + return 0; +} + +int32_t elliptic_data_io_transact(uint32_t message_id, const char *data, + size_t data_size, char *output_data, + size_t output_data_size) +{ + return 0; +} + +void elliptic_data_io_cancel(struct elliptic_data *elliptic_data) +{ + atomic_set(&elliptic_data->abort_io, 1); + wake_up_interruptible(&elliptic_data->fifo_isr_not_empty); +} + +int elliptic_data_io_initialize(void) +{ + pr_debug("%s\n", __func__); + atomic_set(&cancel, 0); + simulating_task = + kthread_run(&simulating_thread, NULL, "el_simulating_thread"); + + if (request_irq(USE_IRQ, irq_handler, IRQF_SHARED, "my_device", + (void *)(irq_handler))) { + pr_debug("my_device: cannot register IRQ "); + return -EPERM; + } + + return 0; +} + +int elliptic_data_io_cleanup(void) +{ + free_irq(USE_IRQ, (void *)(irq_handler)); + kthread_stop(simulating_task); + atomic_set(&cancel, 1); + msleep(200); + return 0; +} diff --git a/techpack/audio/dsp/mius/Makefile b/techpack/audio/dsp/mius/Makefile new file mode 100644 index 000000000000..1a0cd5f4608b --- /dev/null +++ b/techpack/audio/dsp/mius/Makefile @@ -0,0 +1,28 @@ +ccflags-y := -I$(src) -Wall -Werror +IO_MODULE := msm + +# EXTRA_CFLAGS += -DDEBUG + +# Need to add include paths: +LINUXINCLUDE += \ + -I$(srctree)techpack/audio/include/dsp + -I$(srctree)techpack/audio/include/uapi + -I$(srctree)techpack/aduio/include + +obj-y += mius.o +obj-y += mius_mixer_controls.o +obj-y += io_modules/$(IO_MODULE)/mius_data_$(IO_MODULE)_io.o +obj-y += io_modules/userspace/mius_data_userspace_io.o +obj-y += io_modules/userspace/mius_data_userspace_ctrl.o +obj-y += mius_sysfs.o + +# mius_driver-y := mius.o +# mius_driver-y += io_modules/$(IO_MODULE)/mius_data_io.o +# mius_driver-y += mixer_controls/$(MIXER_MODULE)/mius_mixer_controls.o +# mius_driver-y += mius_sysfs.o + +# .PHONY: clean +# all: +# make -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) modules +# clean: +# rm *.o *.ko diff --git a/techpack/audio/dsp/mius/io_modules/Makefile b/techpack/audio/dsp/mius/io_modules/Makefile new file mode 100644 index 000000000000..66ee789be57f --- /dev/null +++ b/techpack/audio/dsp/mius/io_modules/Makefile @@ -0,0 +1,2 @@ +# TODO: add config parameter for which io module to build +#obj-y += userspace/ diff --git a/techpack/audio/dsp/mius/io_modules/msm/mius_data_msm_io.c b/techpack/audio/dsp/mius/io_modules/msm/mius_data_msm_io.c new file mode 100644 index 000000000000..fbfcb613d82c --- /dev/null +++ b/techpack/audio/dsp/mius/io_modules/msm/mius_data_msm_io.c @@ -0,0 +1,105 @@ +/** + * Copyright MI + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define IO_PING_PONG_BUFFER_SIZE 512 +#define AFE_MSM_RX_PSEUDOPORT_ID 0x8001 +#define AFE_MSM_TX_PSEUDOPORT_ID 0x8002 + +struct mius_msm_io_device {}; + +/* static struct mius_msm_io_device io_device;*/ + +int mius_data_io_initialize(void) +{ + return 0; +} + +int mius_data_io_cleanup(void) +{ + return 0; +} +int mius_io_open_port(int portid) +{ + if (portid == ULTRASOUND_RX_PORT_ID) + return afe_start_pseudo_port(AFE_MSM_RX_PSEUDOPORT_ID); + else + return afe_start_pseudo_port(AFE_MSM_TX_PSEUDOPORT_ID); +} + +int mius_io_close_port(int portid) +{ + if (portid == ULTRASOUND_RX_PORT_ID) + return afe_stop_pseudo_port(AFE_MSM_RX_PSEUDOPORT_ID); + else + return afe_stop_pseudo_port(AFE_MSM_TX_PSEUDOPORT_ID); +} + +int32_t mius_data_io_write(uint32_t message_id, const char *data, + size_t data_size) +{ + int32_t result = 0; + + /* msm_pcm_routing_acquire_lock(); */ + + result = mi_ultrasound_apr_set_parameter( + MIUS_PORT_ID, message_id, (u8 *)data, (int32_t)data_size); + + /* msm_pcm_routing_release_lock();*/ + return result; +} + +int32_t mius_data_io_transact(uint32_t message_id, const char *data, + size_t data_size, char *output_data, + size_t output_data_size) +{ + pr_err("%s : unimplemented\n", __func__); + return -EINVAL; +} diff --git a/techpack/audio/dsp/mius/io_modules/userspace/Makefile b/techpack/audio/dsp/mius/io_modules/userspace/Makefile new file mode 100644 index 000000000000..34d76dde1eb9 --- /dev/null +++ b/techpack/audio/dsp/mius/io_modules/userspace/Makefile @@ -0,0 +1,2 @@ +# TODO: add config parameter for which io module to build +#obj-y += mius_data_io.o diff --git a/techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_ctrl.c b/techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_ctrl.c new file mode 100644 index 000000000000..ea81488cf492 --- /dev/null +++ b/techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_ctrl.c @@ -0,0 +1,263 @@ +/** + * Copyright MI + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static dev_t mius_userspace_ctrl_major; +#define USERSPACE_CTRL_IO_DEVICE_NAME "mius_us_ctrl_io" +struct mius_userspace_ctrl_device { + struct cdev cdev; + struct semaphore sem; + int ping_pong_idx; + size_t ping_pong_buffer_size[2]; + uint8_t ping_pong_buffer[2][MIUS_MSG_BUF_SIZE]; + wait_queue_head_t data_available; + struct mutex data_lock; + atomic_t data_state; +}; + +static struct mius_userspace_ctrl_device ctrl_device; + +static uint8_t *get_ping_buffer(struct mius_userspace_ctrl_device *dev, + /*out parameter*/ size_t *data_size) +{ + if (data_size != NULL) + *data_size = dev->ping_pong_buffer_size[dev->ping_pong_idx]; + + return dev->ping_pong_buffer[dev->ping_pong_idx]; +} + +static uint8_t *get_pong_buffer(struct mius_userspace_ctrl_device *dev, + /*out parameter*/ size_t *data_size) +{ + if (data_size != NULL) + *data_size = dev->ping_pong_buffer_size[1 - dev->ping_pong_idx]; + + return dev->ping_pong_buffer[1 - dev->ping_pong_idx]; +} + +static void set_pong_buffer_size(struct mius_userspace_ctrl_device *dev, + size_t data_size) +{ + dev->ping_pong_buffer_size[1 - dev->ping_pong_idx] = data_size; +} + +static void swap_ping_pong(struct mius_userspace_ctrl_device *dev) +{ + dev->ping_pong_idx = 1 - dev->ping_pong_idx; +} + +static int device_open(struct inode *inode, struct file *filp) +{ + if (inode->i_cdev != &ctrl_device.cdev) { + pr_warn("mius : dev pointer mismatch\n"); + return -ENODEV; /* No such device */ + } + + if (down_interruptible(&ctrl_device.sem) != 0) + return -EEXIST; + MI_PRINT_I("Opened device %s", USERSPACE_CTRL_IO_DEVICE_NAME); + return 0; +} + +static ssize_t device_read(struct file *fp, char __user *buff, + size_t user_buf_length, loff_t *ppos) +{ + size_t bytes_read; + unsigned long copy_result; + uint8_t *ping_buffer; + int result; + + if (user_buf_length < MIUS_MSG_BUF_SIZE) + MI_PRINT_E("user space buffer user_buf_length too small : %zu", + user_buf_length); + + bytes_read = 0; + copy_result = 0; + ping_buffer = NULL; + + result = wait_event_interruptible( + ctrl_device.data_available, + atomic_read(&ctrl_device.data_state) != 0); + if (result == 0) { + const int state = atomic_read(&ctrl_device.data_state); + + if (state > 0) { + result = mutex_lock_interruptible( + &ctrl_device.data_lock); + if (result == 0) { + swap_ping_pong(&ctrl_device); + + ping_buffer = get_ping_buffer(&ctrl_device, + &bytes_read); + + if (bytes_read > user_buf_length) { + MI_PRINT_E( + "ping buffer size %zu larger than user buffer", + bytes_read); + goto fail; + } + + copy_result = copy_to_user(buff, ping_buffer, + bytes_read); + if (copy_result > 0) { + MI_PRINT_E("Failed copy to user"); + goto fail; + } + + atomic_set(&ctrl_device.data_state, 0); + + mutex_unlock(&ctrl_device.data_lock); + } else if (result == -EINTR) { + MI_PRINT_E("lock interrupted"); + } else { + MI_PRINT_E("lock error = %d", result); + } + } else { + MI_PRINT_W("state = %d", state); + atomic_set(&ctrl_device.data_state, 0); + } + } else if (result == -ERESTARTSYS) { + MI_PRINT_E("interrupted"); + } else { + MI_PRINT_E("wait_event error = %d", result); + } + return bytes_read; +fail: + atomic_set(&ctrl_device.data_state, 0); + mutex_unlock(&ctrl_device.data_lock); + return 0; +} + +static int device_close(struct inode *inode, struct file *filp) +{ + up(&ctrl_device.sem); + MI_PRINT_I("Closed device %s", USERSPACE_CTRL_IO_DEVICE_NAME); + return 0; +} + +static const struct file_operations mius_userspace_ctrl_fops = { + .owner = THIS_MODULE, + .open = device_open, + .read = device_read, + .release = device_close, +}; + +int mius_userspace_ctrl_driver_init(void) +{ + struct device *device; + dev_t device_number; + int err; + + err = alloc_chrdev_region(&device_number, 0, 1, + USERSPACE_CTRL_IO_DEVICE_NAME); + + if (err < 0) { + pr_err("failed to allocate chrdev region\n"); + return err; + } + + mius_userspace_ctrl_major = MAJOR(device_number); + + device_number = MKDEV(mius_userspace_ctrl_major, 0); + device = device_create(mius_class, NULL, device_number, NULL, + USERSPACE_CTRL_IO_DEVICE_NAME); + + if (IS_ERR(device)) { + unregister_chrdev(mius_userspace_ctrl_major, + USERSPACE_CTRL_IO_DEVICE_NAME); + MI_PRINT_E("Failed to create the device\n"); + return PTR_ERR(device); + } + + cdev_init(&ctrl_device.cdev, &mius_userspace_ctrl_fops); + ctrl_device.cdev.owner = THIS_MODULE; + err = cdev_add(&ctrl_device.cdev, device_number, 1); + if (err) { + MI_PRINT_W("error %d while trying to add %s%d", err, + MIUS_DEVICENAME, 0); + return err; + } + + sema_init(&ctrl_device.sem, 1); + mutex_init(&ctrl_device.data_lock); + init_waitqueue_head(&ctrl_device.data_available); + return 0; +} + +void mius_userspace_ctrl_driver_exit(void) +{ + BUG_ON(mius_class == NULL); + device_destroy(mius_class, MKDEV(mius_userspace_ctrl_major, 0)); + cdev_del(&ctrl_device.cdev); + unregister_chrdev(mius_userspace_ctrl_major, + USERSPACE_CTRL_IO_DEVICE_NAME); + up(&ctrl_device.sem); +} + +int32_t mius_userspace_ctrl_write(uint32_t message_id, const char *data, + size_t data_size) +{ + uint8_t *pong_buffer; + + if (data_size > MIUS_MSG_BUF_SIZE) { + MI_PRINT_E("data size : %zu larger than buf size : %zu", + data_size, (size_t)MIUS_MSG_BUF_SIZE); + + return -EINVAL; + } + mutex_lock(&ctrl_device.data_lock); + + pong_buffer = get_pong_buffer(&ctrl_device, NULL); + set_pong_buffer_size(&ctrl_device, data_size); + + memcpy(pong_buffer, data, data_size); + wake_up_interruptible(&ctrl_device.data_available); + atomic_set(&ctrl_device.data_state, 1); + mutex_unlock(&ctrl_device.data_lock); + + return 0; +} diff --git a/techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_io.c b/techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_io.c new file mode 100644 index 000000000000..a87e1b6357c0 --- /dev/null +++ b/techpack/audio/dsp/mius/io_modules/userspace/mius_data_userspace_io.c @@ -0,0 +1,143 @@ +/** + * Copyright MI + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static dev_t mius_userspace_major; +#define USERSPACE_IO_DEVICE_NAME "mius_us_io" +struct mius_userspace_device { + struct cdev cdev; + struct semaphore sem; +}; + +static struct mius_userspace_device io_device; + +static int device_open(struct inode *inode, struct file *filp) +{ + if (inode->i_cdev != &io_device.cdev) { + pr_warn("mius : dev pointer mismatch\n"); + return -ENODEV; /* No such device */ + } + + if (down_interruptible(&io_device.sem) != 0) + return -EEXIST; + MI_PRINT_I("Opened device %s", USERSPACE_IO_DEVICE_NAME); + return 0; +} + +static ssize_t device_write(struct file *fp, const char __user *buff, + size_t length, loff_t *ppos) +{ + int push_result; + + push_result = mius_data_push(MIUS_ALL_DEVICES, buff, length, + MIUS_DATA_PUSH_FROM_USERSPACE); + + return push_result == 0 ? (ssize_t)length : (ssize_t)(-1); +} + +static int device_close(struct inode *inode, struct file *filp) +{ + up(&io_device.sem); + MI_PRINT_I("Closed device %s", USERSPACE_IO_DEVICE_NAME); + return 0; +} + +static const struct file_operations mius_userspace_fops = { + .owner = THIS_MODULE, + .open = device_open, + .write = device_write, + .release = device_close, +}; + +int mius_userspace_io_driver_init(void) +{ + struct device *device; + dev_t device_number; + int err; + + err = alloc_chrdev_region(&device_number, 0, 1, + USERSPACE_IO_DEVICE_NAME); + + if (err < 0) { + pr_err("failed to allocate chrdev region\n"); + return err; + } + + mius_userspace_major = MAJOR(device_number); + + device_number = MKDEV(mius_userspace_major, 0); + device = device_create(mius_class, NULL, device_number, NULL, + USERSPACE_IO_DEVICE_NAME); + + if (IS_ERR(device)) { + unregister_chrdev(mius_userspace_major, + USERSPACE_IO_DEVICE_NAME); + pr_err("Failed to create the device\n"); + return PTR_ERR(device); + } + + cdev_init(&io_device.cdev, &mius_userspace_fops); + io_device.cdev.owner = THIS_MODULE; + err = cdev_add(&io_device.cdev, device_number, 1); + if (err) { + MI_PRINT_W("error %d while trying to add %s%d", err, + MIUS_DEVICENAME, 0); + return err; + } + + sema_init(&io_device.sem, 1); + return 0; +} + +void mius_userspace_io_driver_exit(void) +{ + BUG_ON(mius_class == NULL); + device_destroy(mius_class, MKDEV(mius_userspace_major, 0)); + cdev_del(&io_device.cdev); + unregister_chrdev(mius_userspace_major, USERSPACE_IO_DEVICE_NAME); + up(&io_device.sem); +} diff --git a/techpack/audio/dsp/mius/io_modules/userspace_test/Makefile b/techpack/audio/dsp/mius/io_modules/userspace_test/Makefile new file mode 100644 index 000000000000..34d76dde1eb9 --- /dev/null +++ b/techpack/audio/dsp/mius/io_modules/userspace_test/Makefile @@ -0,0 +1,2 @@ +# TODO: add config parameter for which io module to build +#obj-y += mius_data_io.o diff --git a/techpack/audio/dsp/mius/io_modules/userspace_test/mius_data_io.c b/techpack/audio/dsp/mius/io_modules/userspace_test/mius_data_io.c new file mode 100644 index 000000000000..7f4f60037912 --- /dev/null +++ b/techpack/audio/dsp/mius/io_modules/userspace_test/mius_data_io.c @@ -0,0 +1,120 @@ +/** + * Copyright MI + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#define USE_IRQ 11 + +static struct task_struct *simulating_task; +static atomic_t cancel; + +struct mius_data_io_state {}; +#define BUFFER_SIZE 128 + +static int32_t output_buffer[BUFFER_SIZE]; + +irqreturn_t irq_handler(int irq, void *dev_id) +{ + int result; + + result = mius_data_push(MIUS_ALL_DEVICES, (const char *)output_buffer, + BUFFER_SIZE * sizeof(int32_t)); + return 0; +} + +static void fill_buffer(int32_t *buffer, size_t len, int32_t value) +{ + size_t i; + + for (i = 0; i < len; ++i) + buffer[i] = value; +} + +int simulating_thread(void *context) +{ + static int32_t count; + int result; + + count = 0; + msleep(100); + + pr_debug("%s\n", __func__); + while (atomic_read(&cancel) == 0) { + if (kthread_should_stop()) + do_exit(0); + + fill_buffer(output_buffer, BUFFER_SIZE, count); + + ++count; + if (result != 0) { + pr_warn("failed to push data\n"); + } + asm("int $0x3B"); /* Corresponding to irq 11 */ + msleep(0); + } + return 0; +} + +int32_t mius_data_io_write(uint32_t message_id, const char *data, + size_t data_size) +{ + return 0; +} + +int32_t mius_data_io_transact(uint32_t message_id, const char *data, + size_t data_size, char *output_data, + size_t output_data_size) +{ + return 0; +} + +void mius_data_io_cancel(struct mius_data *mius_data) +{ + atomic_set(&mius_data->abort_io, 1); + wake_up_interruptible(&mius_data->fifo_isr_not_empty); +} + +int mius_data_io_initialize(void) +{ + pr_debug("%s\n", __func__); + atomic_set(&cancel, 0); + simulating_task = + kthread_run(&simulating_thread, NULL, "el_simulating_thread"); + + if (request_irq(USE_IRQ, irq_handler, IRQF_SHARED, "my_device", + (void *)(irq_handler))) { + pr_debug("my_device: cannot register IRQ "); + return -EPERM; + } + + return 0; +} + +int mius_data_io_cleanup(void) +{ + free_irq(USE_IRQ, (void *)(irq_handler)); + kthread_stop(simulating_task); + atomic_set(&cancel, 1); + msleep(200); + return 0; +} diff --git a/techpack/audio/dsp/mius/mius.c b/techpack/audio/dsp/mius/mius.c new file mode 100644 index 000000000000..6f8d13a6671e --- /dev/null +++ b/techpack/audio/dsp/mius/mius.c @@ -0,0 +1,752 @@ +/** +* Copyright MI +* Copyright (C) 2019 XiaoMi, Inc. +* +*/ +/* #define DEBUG */ +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* Alternative mechanism to load calibration data. +* Read calibration data during driver initialization +* and send message to the DSP +* +* #define MIUS_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM 1 +*/ +#ifdef MIUS_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM +#include +#include +#include +#endif + +static struct mius_device *mius_devices; + +/* Global variable for the device class*/ +struct class *mius_class; + +typedef uint32_t el_fifo_size_t; + +/* Major number provided by the kernel*/ +static dev_t mius_major; + +static struct wakeup_source *wake_source; + +void mius_data_cancel(struct mius_data *mius_data) +{ + atomic_set(&mius_data->abort_io, 1); + wake_up_interruptible(&mius_data->fifo_isr_not_empty); +} + +void mius_data_reset_debug_counters(struct mius_data *mius_data) +{ + mius_data->isr_fifo_discard = 0; +} + +void mius_data_print_debug_counters(struct mius_data *mius_data) +{ + if (mius_data->isr_fifo_discard > 0) { + MI_PRINT_E("isr fifo discarded %u frames", + mius_data->isr_fifo_discard); + } + + if (mius_data->userspace_read_total != mius_data->isr_write_total) { + MI_PRINT_I("user space reads / isr writes : %u / %u", + mius_data->userspace_read_total, + mius_data->isr_write_total); + } + + MI_PRINT_I("total isr fifo discarded frame count : %u", + mius_data->isr_fifo_discard_total); +} + +void mius_data_update_debug_counters(struct mius_data *mius_data) +{ + mius_data->isr_fifo_discard_total += mius_data->isr_fifo_discard; +} + +/* spin lock for isr must be held prior to calling */ +static void mius_data_flush_isr_fifo(struct mius_data *mius_data) +{ + kfifo_reset(&mius_data->fifo_isr); +} + +/* spin lock for isr must be held prior to calling */ +static void mius_data_isr_fifo_pop(struct mius_data *mius_data, size_t size) +{ + unsigned int fifo_result; + static uint8_t temp_buffer[MIUS_MSG_BUF_SIZE]; + + if (size > MIUS_MSG_BUF_SIZE) + MI_PRINT_E("pop size %zu too large", size); + + fifo_result = kfifo_out(&mius_data->fifo_isr, temp_buffer, size); + + if (size != fifo_result) + MI_PRINT_E("failed to pop element"); +} + +int mius_notify_gain_change_msg(int component_id, int gaindb) +{ + int32_t msg[3] = { MSC_COMPONENT_GAIN_CHANGE, component_id, gaindb }; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} + +/* inode refers to the actual file on disk */ +static int device_open(struct inode *inode, struct file *filp) +{ + unsigned int major; + unsigned int minor; + struct mius_device *dev; + struct mius_data *mius_data; + + major = imajor(inode); + minor = iminor(inode); + + if (major != mius_major || minor < 0 || minor >= MIUS_NUM_DEVICES) { + MI_PRINT_W("no device found with minor=%d and major=%d", major, + minor); + return -ENODEV; /* No such device */ + } + + dev = NULL; + dev = &mius_devices[minor]; + filp->private_data = dev; + + if (inode->i_cdev != &dev->cdev) { + MI_PRINT_W("dev pointer mismatch"); + return -ENODEV; /* No such device */ + } + + if (down_interruptible(&dev->sem) != 0) { + MI_PRINT_E("the device has been opened, unable to open lock"); + return -EINVAL; + } + + mius_data = &dev->el_data; + spin_lock(&mius_data->fifo_isr_spinlock); + mius_data_flush_isr_fifo(mius_data); + spin_unlock(&mius_data->fifo_isr_spinlock); + + atomic_set(&mius_data->abort_io, 0); + mius_data_reset_debug_counters(mius_data); + + MI_PRINT_I("Opened device mius%u", minor); + dev->opened = 1; + return 0; +} + +int mius_data_initialize(struct mius_data *mius_data, size_t queue_size, + unsigned int wakeup_timeout, int id) +{ + int is_power_of_two; + + is_power_of_two = (queue_size != 0) && !(queue_size & (queue_size - 1)); + + if (is_power_of_two != 1) { + MI_PRINT_E("non power of 2 fifo size"); + return -EINVAL; + } + + if (kfifo_alloc(&mius_data->fifo_isr, queue_size, GFP_KERNEL) != 0) { + MI_PRINT_E("failed to allocate fifo isr"); + return -EINVAL; + } + + atomic_set(&mius_data->abort_io, 0); + spin_lock_init(&mius_data->fifo_isr_spinlock); + + mius_data->wakeup_timeout = wakeup_timeout; + + mutex_init(&mius_data->user_buffer_lock); + init_waitqueue_head(&mius_data->fifo_isr_not_empty); + + return 0; +} + +int mius_data_cleanup(struct mius_data *mius_data) +{ + spin_unlock(&mius_data->fifo_isr_spinlock); + kfifo_free(&mius_data->fifo_isr); + return 0; +} + +size_t mius_data_pop(struct mius_data *mius_data, char __user *user_buffer, + size_t buffer_size) +{ + int result; + unsigned long num_copied; + unsigned int fifo_result; + unsigned long flags; + + if (buffer_size < MIUS_MSG_BUF_SIZE) { + MI_PRINT_E("buffer_size : %lu smaller than %lu", buffer_size, + (size_t)MIUS_MSG_BUF_SIZE); + return 0; + } + + result = wait_event_interruptible( + mius_data->fifo_isr_not_empty, + (kfifo_is_empty(&mius_data->fifo_isr) == 0) || + (atomic_read(&mius_data->abort_io) == 1)); + + if (atomic_read(&mius_data->abort_io) == 1) { + atomic_set(&mius_data->abort_io, 0); + MI_PRINT_D("pop cancelled"); + return 0; + } + + if (result == 0) { + spin_lock_irqsave(&mius_data->fifo_isr_spinlock, flags); + + fifo_result = kfifo_out(&mius_data->fifo_isr, + mius_data->isr_swap_buffer, + MIUS_MSG_BUF_SIZE); + + spin_unlock_irqrestore(&mius_data->fifo_isr_spinlock, flags); + + if (fifo_result == 0) { + MI_PRINT_E("failed to copy: fifo isr -> swap buffer %u", + fifo_result); + return 0; + } + + mutex_lock(&mius_data->user_buffer_lock); + + num_copied = + copy_to_user(user_buffer, mius_data->isr_swap_buffer, + MIUS_MSG_BUF_SIZE); + + mutex_unlock(&mius_data->user_buffer_lock); + + if (num_copied != 0) { + MI_PRINT_E("failed copy to user"); + return 0; + } + ++mius_data->userspace_read_total; + } else { + if (-ERESTARTSYS == result) + MI_PRINT_I("wait interrupted"); + else + MI_PRINT_E("wait error = %d", result); + + return 0; + } + + return (size_t)MIUS_MSG_BUF_SIZE; +} + +/* push data to specific device or all devices */ +int mius_data_push(int deviceid, const char *buffer, size_t buffer_size, + mius_data_push_t data_source) +{ + size_t available_space; + size_t space_required; + size_t zeros_to_pad; + unsigned int copied_from_user; + int copy_from_user_result; + int err; + int i; + int i_max; + + unsigned long flags; + struct mius_device *device; + struct mius_data *mius_data; + unsigned int fifo_result; + static uint8_t zero_pad_buffer[MIUS_MSG_BUF_SIZE]; + + err = 0; + fifo_result = 0; + copied_from_user = 0; + copy_from_user_result = 0; + if (buffer_size > MIUS_MSG_BUF_SIZE) + return -EINVAL; + + zeros_to_pad = MIUS_MSG_BUF_SIZE - buffer_size; + + i = 0; + i_max = MIUS_NUM_DEVICES; + + if (deviceid != MIUS_ALL_DEVICES) { + /* Copy to specific device */ + i = deviceid; + i_max = i + 1; + } + + for (; i < i_max; ++i) { + device = &mius_devices[i]; + mius_data = &device->el_data; + + if ((!device->opened)) + continue; + + available_space = kfifo_avail(&mius_data->fifo_isr); + space_required = MIUS_MSG_BUF_SIZE; + + spin_lock_irqsave(&mius_data->fifo_isr_spinlock, flags); + + if (available_space < space_required) { + ++mius_data->isr_fifo_discard; + mius_data_isr_fifo_pop(mius_data, MIUS_MSG_BUF_SIZE); + } + + if (data_source == MIUS_DATA_PUSH_FROM_KERNEL) { + fifo_result = kfifo_in(&mius_data->fifo_isr, buffer, + buffer_size); + + if (fifo_result == 0) { + spin_unlock_irqrestore( + &mius_data->fifo_isr_spinlock, flags); + continue; + } + } else if (data_source == MIUS_DATA_PUSH_FROM_USERSPACE) { + copy_from_user_result = + kfifo_from_user(&mius_data->fifo_isr, buffer, + buffer_size, &copied_from_user); + + if (-EFAULT == copy_from_user_result) { + spin_unlock_irqrestore( + &mius_data->fifo_isr_spinlock, flags); + continue; + } + } + + if (zeros_to_pad > 0) { + fifo_result = kfifo_in(&mius_data->fifo_isr, + zero_pad_buffer, zeros_to_pad); + + if (fifo_result == 0) { + mius_data_isr_fifo_pop(mius_data, buffer_size); + + spin_unlock_irqrestore( + &mius_data->fifo_isr_spinlock, flags); + + ++mius_data->isr_fifo_discard; + continue; + } + } + + ++mius_data->isr_write_total; + spin_unlock_irqrestore(&mius_data->fifo_isr_spinlock, flags); + wake_up_interruptible(&mius_data->fifo_isr_not_empty); + __pm_wakeup_event(wake_source, mius_data->wakeup_timeout); + } + + return err; +} + +int mius_open_port(int portid) +{ + return mius_io_open_port(portid); +} + +int mius_close_port(int portid) +{ + return mius_io_close_port(portid); +} + +int32_t mius_data_write(uint32_t message_id, const char *data, size_t data_size) +{ + int32_t err_dsp; + /* int32_t err_us; */ + + err_dsp = 0; + err_dsp = mius_data_io_write(message_id, data, data_size); + if (err_dsp) + MI_PRINT_E("Failed write to DSP"); + return err_dsp; + + /* + * err_us = 0; + * err_us = mius_userspace_ctrl_write(message_id, data, data_size); + * if(err_us){ + * MI_PRINT_E("Failed write to user space"); + *} + * + *return (err_dsp | err_us); + */ +} + +/** +* +* @return Number of bytes read. +*/ +static ssize_t device_read(struct file *fp, char __user *buff, size_t length, + loff_t *ppos) +{ + ssize_t bytes_read = 0; + struct mius_device *mius_device; + struct mius_data *mius_data; + + mius_device = (struct mius_device *)fp->private_data; + mius_data = (struct mius_data *)&mius_device->el_data; + + bytes_read = mius_data_pop(mius_data, buff, length); + + return bytes_read; +} + +/** +* +* @return number of bytes actually written +*/ +static ssize_t device_write(struct file *fp, const char *buff, size_t length, + loff_t *ppos) +{ + ssize_t ret_val; + + ret_val = 0; + if ((buff != NULL) && (length != 0)) + ret_val = mius_data_io_write(MIUS_ULTRASOUND_SET_PARAMS, buff, + length); + + return ret_val >= 0 ? (ssize_t)length : 0; +} + +static long device_ioctl(struct file *fp, unsigned int number, + unsigned long param) +{ + struct mius_device *device; + struct mius_data *mius_data; + int err; + unsigned int mirror_tag, mirror_payload_size; + unsigned char *data_ptr; + + device = (struct mius_device *)(fp->private_data); + mius_data = &device->el_data; + + switch (number) { + case IOCTL_MIUS_DATA_IO_CANCEL: + MI_PRINT_D("IOCTL_MIUS_CANCEL_READ %ld", param); + mius_data_cancel(mius_data); + break; + + case IOCTL_MIUS_DATA_IO_MIRROR: + data_ptr = (unsigned char *)param; + mirror_tag = *(unsigned int *)data_ptr; + mirror_payload_size = *((unsigned int *)data_ptr + 1); + + if ((mirror_tag == MIRROR_TAG) && (mirror_payload_size != 0) && + (mirror_payload_size <= (MIUS_SET_PARAMS_SIZE * 4))) { + err = mius_data_io_write(MIUS_ULTRASOUND_SET_PARAMS, + (data_ptr + 8), + mirror_payload_size); + + if (err != 0) { + MI_PRINT_E("mius_data_io_write failed"); + return err; + } + + } else { + MI_PRINT_E("TAG or Length is not valid"); + } + + break; + + default: + MI_PRINT_W("UNKNOWN IOCTL number=%d", number); + break; + } + + return 0; +} + +static unsigned int device_poll(struct file *file, + struct poll_table_struct *poll_table) +{ + unsigned int mask; + + struct mius_device *device; + struct mius_data *mius_data; + + mask = 0; + device = (struct mius_device *)file->private_data; + mius_data = (struct mius_data *)&device->el_data; + + poll_wait(file, &mius_data->fifo_isr_not_empty, poll_table); + + if (!kfifo_is_empty(&mius_data->fifo_isr)) + mask = POLLIN | POLLRDNORM; + + return mask; +} + +static int device_close(struct inode *inode, struct file *filp) +{ + struct mius_device *device; + struct mius_data *mius_data; + unsigned int minor; + + device = filp->private_data; + mius_data = &device->el_data; + minor = iminor(inode); + if (device == NULL) { + MI_PRINT_E("device not found"); + return -ENODEV; + } + + device->opened = 0; + mius_data_update_debug_counters(mius_data); + mius_data_print_debug_counters(mius_data); + mius_data_cancel(mius_data); + up(&device->sem); + + MI_PRINT_I("Closed device mius%u", minor); + return 0; +} + +/* defines the file operations provided by the driver */ +static const struct file_operations mius_fops = { + .owner = THIS_MODULE, /* prevents unloading when operations are in use*/ + .open = device_open, /*to open the device*/ + .write = device_write, /*to write to the device*/ + .read = device_read, /*to read the device*/ + .poll = device_poll, + .unlocked_ioctl = device_ioctl, /* IOCTL calls */ + .release = device_close, /*to close the device*/ +}; + +static int mius_device_initialize(struct mius_device *mius_device, int minor, + struct class *class) +{ + int err; + dev_t device_number; + struct device *device; + + BUG_ON(mius_device == NULL || class == NULL); + + err = 0; + device = NULL; + device_number = MKDEV(mius_major, minor); + /* Memory is to be allocated when the device is opened the first time */ + sema_init(&mius_device->sem, 1); + cdev_init(&mius_device->cdev, &mius_fops); + mius_device->cdev.owner = THIS_MODULE; + + err = cdev_add(&mius_device->cdev, device_number, 1); + + if (err) { + MI_PRINT_E("error %d while trying to add %s%d", err, + MIUS_DEVICENAME, minor); + return err; + } + + device = device_create(class, NULL, device_number, NULL, + MIUS_DEVICENAME "%d", minor); + + if (IS_ERR(device)) { + err = PTR_ERR(device); + MI_PRINT_E("error %d while trying to create %s%d", err, + MIUS_DEVICENAME, minor); + cdev_del(&mius_device->cdev); + return err; + } + + if (err) { + MI_PRINT_E("failed device initialize"); + return err; + } + + return 0; +} + +static void mius_device_cleanup(struct mius_device *dev, int minor, + struct class *class) + +{ + BUG_ON(dev == NULL || class == NULL); + device_destroy(class, MKDEV(mius_major, minor)); + cdev_del(&dev->cdev); + up(&dev->sem); +} + +static void mius_driver_cleanup(int devices_to_destroy) +{ + int i; + + if (mius_devices) { + mius_data_io_cleanup(); + + for (i = 0; i < devices_to_destroy; ++i) { + mius_data_cleanup(&mius_devices[i].el_data); + mius_device_cleanup(&mius_devices[i], i, mius_class); + } + + kfree(mius_devices); + } + + if (mius_class) + class_destroy(mius_class); + + unregister_chrdev_region(MKDEV(mius_major, 0), MIUS_NUM_DEVICES); +} + +#ifdef MIUS_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM + +#define MIUS_CALIBRATION_MAX_DATA_SIZE \ + (MIUS_CALIBRATION_V2_DATA_SIZE + MIUS_CALIBRATION_DATA_SIZE) +static unsigned char calibration_data[MIUS_CALIBRATION_MAX_DATA_SIZE]; +static char *calibration_filename = "/persist/audio/mius_calibration"; + +/* function to load the calibration from a file (if possible) */ +static size_t load_calibration_data(char *filename) +{ + size_t bytes_read = 0; + int rc = -ENOENT; + + rc = kernel_read_file_from_path(filename, calibration_data, &bytes_read, + MIUS_CALIBRATION_MAX_DATA_SIZE, + READING_FIRMWARE); + if (rc) { + if (rc == -ENOENT) + MI_PRINT_E("loading %s failed with error %d\n", + filename, rc); + else + MI_PRINT_E("loading %s failed with error %d\n", + filename, rc); + } + MI_PRINT_I("loading %s\n", filename); + + return bytes_read; +} + +static int32_t mius_send_calibration_to_engine(size_t calib_data_size) +{ + mius_set_calibration_data(calibration_data, calib_data_size); + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, + (const char *)calibration_data, calib_data_size); +} + +#endif + +int __init mius_driver_init(void) +{ + int err; + int i; + int devices_to_destroy; + dev_t device_number; + + err = alloc_chrdev_region(&device_number, 0, MIUS_NUM_DEVICES, + MIUS_DEVICENAME); + + devices_to_destroy = 0; + + if (err < 0) { + MI_PRINT_E("Failed to allocate cdev region"); + return err; + } + + mius_major = MAJOR(device_number); + mius_class = class_create(THIS_MODULE, "mius_chardev"); + + if (mius_class == NULL) { + MI_PRINT_E("Class creation failed"); + goto fail; + } + + err = mius_initialize_sysfs(); + + if (err) + goto fail; + + mius_devices = (struct mius_device *)kzalloc( + sizeof(struct mius_device) * MIUS_NUM_DEVICES, GFP_KERNEL); + + if (mius_devices == NULL) { + err = -ENOMEM; + goto fail; + } + + for (i = 0; i < MIUS_NUM_DEVICES; ++i) { + if (mius_device_initialize(&mius_devices[i], i, mius_class)) { + devices_to_destroy = i; + goto fail; + } + + if (mius_data_initialize(&mius_devices[i].el_data, + MIUS_DATA_FIFO_SIZE, + MIUS_WAKEUP_TIMEOUT, i)) { + goto fail; + } + } + + if (mius_data_io_initialize()) + goto fail; + + if (mius_userspace_io_driver_init()) + goto fail; + + if (mius_userspace_ctrl_driver_init()) + goto fail; + + wake_source = kmalloc(sizeof(struct wakeup_source), GFP_KERNEL); + + if (!wake_source) { + MI_PRINT_E("failed to allocate wake source"); + return -ENOMEM; + } + + wakeup_source_init(wake_source, "mius_wake_source"); + +#ifdef MIUS_LOAD_CALIBRATION_DATA_FROM_FILESYSTEM + /* Code to send calibration to engine */ + { + size_t calib_data_size = + load_calibration_data(calibration_filename); + if (calib_data_size > 0) + mius_send_calibration_to_engine(calib_data_size); + } +#endif + return 0; + +fail: + mius_driver_cleanup(devices_to_destroy); + return err; +} + +void mius_driver_exit(void) +{ + if (wake_source) { + wakeup_source_trash(wake_source); + kfree(wake_source); + } + + mius_cleanup_sysfs(); + mius_driver_cleanup(MIUS_NUM_DEVICES); + mius_userspace_io_driver_exit(); + mius_userspace_ctrl_driver_exit(); +} + +MODULE_AUTHOR("MI"); +MODULE_DESCRIPTION("Providing Interface to UPS data"); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/dsp/mius/mius_mixer_controls.c b/techpack/audio/dsp/mius/mius_mixer_controls.c new file mode 100644 index 000000000000..c4ea9e3ecb1b --- /dev/null +++ b/techpack/audio/dsp/mius/mius_mixer_controls.c @@ -0,0 +1,1344 @@ +/** + * MI + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct mius_system_configuration { + union { + uint8_t reserved[MIUS_SYSTEM_CONFIGURATION_SIZE]; + }; +}; + +struct mius_system_configuration mius_system_configuration; + +struct mius_system_configuration_parameter { + enum mius_system_configuration_parameter_type type; + union { + int32_t speaker_scaling[2]; + int32_t sensitivity; + int32_t latency; + int32_t microphone_index; + int32_t operation_mode; + int32_t operation_mode_flags; + int32_t component_gain_change; + int32_t calibration_state; + int32_t engine_version; + int32_t calibration_profile; + int32_t ultrasound_gain; + int32_t log_level; + int32_t custom_setting; + int32_t engine_suspend; + int32_t input_enabled; + int32_t output_enabled; + int32_t external_event; + struct { + int32_t calibration_method; + int32_t calibration_timestamp; + }; + int32_t debug_mode; + int32_t context; + int32_t capture; + int32_t input_channels; + }; +}; + +struct mius_system_configuration_parameters_cache + mius_system_configuration_cache = { { 0 }, 0 }; + +static struct mius_engine_version_info mius_engine_version_cache = { 0xde, 0xad, + 0xbe, + 0xef }; + +struct mius_engine_calibration_data { + union { + uint8_t reserved[MIUS_CALIBRATION_DATA_SIZE]; + }; +}; + +static struct mius_engine_calibration_data + mius_engine_calibration_data_cache = { .reserved = { + + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, 0xef } }; + +struct mius_engine_calibration_v2_data { + union { + uint8_t reserved[MIUS_CALIBRATION_V2_DATA_SIZE]; + }; +}; + +static struct mius_engine_calibration_v2_data + mius_engine_calibration_v2_data_cache = { .reserved = { + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, 0xde, 0xad, + 0xbe, 0xef, 0xde, + 0xad, 0xbe, 0xef, + 0xde, 0xad, 0xbe, + 0xef, + } }; + +struct mius_engine_diagnostics_data { + union { + uint8_t reserved[MIUS_DIAGNOSTICS_DATA_SIZE]; + uint32_t values32[MIUS_DIAGNOSTICS_DATA_SIZE >> 2]; + }; +}; + +static struct mius_engine_diagnostics_data mius_engine_diagnostics_data_cache = { + .reserved = { 0 } +}; + +struct mius_engine_ml_data { + union { + uint8_t reserved[MIUS_ML_DATA_SIZE]; + uint32_t u32[MIUS_ML_DATA_SIZE >> 2]; + }; +}; + +static struct mius_engine_ml_data mius_engine_ml_data_cache = { .reserved = { + 0 } }; + +struct mius_engine_sensor_data { + union { + uint8_t reserved[MIUS_SENSOR_DATA_SIZE]; + uint32_t values32[MIUS_SENSOR_DATA_SIZE >> 2]; + }; +}; + +static struct mius_engine_sensor_data mius_engine_sensor_data_cache = { + .reserved = { 0 } +}; + +struct mius_engine_branch_info { + char build_branch[MIUS_BRANCH_INFO_MAX_SIZE]; +}; + +static struct mius_engine_branch_info mius_engine_branch_cache = { { 0 } }; + +struct mius_engine_tag_info { + char engine_tag[MIUS_TAG_INFO_SIZE]; +}; + +static struct mius_engine_tag_info mius_engine_tag_cache = { { 0 } }; + +static struct mius_shared_data_block shared_data_blocks[] = { + { MIUS_OBJ_ID_CALIBRATION_DATA, MIUS_CALIBRATION_DATA_SIZE, + &mius_engine_calibration_data_cache }, + + { MIUS_OBJ_ID_VERSION_INFO, MIUS_VERSION_INFO_SIZE, + &mius_engine_version_cache }, + { MIUS_OBJ_ID_BRANCH_INFO, MIUS_BRANCH_INFO_MAX_SIZE, + &mius_engine_branch_cache }, + { MIUS_OBJ_ID_CALIBRATION_V2_DATA, MIUS_CALIBRATION_V2_DATA_SIZE, + &mius_engine_calibration_v2_data_cache }, + { MIUS_OBJ_ID_DIAGNOSTICS_DATA, MIUS_DIAGNOSTICS_DATA_SIZE, + &mius_engine_diagnostics_data_cache }, + { MIUS_OBJ_ID_TAG_INFO, MIUS_TAG_INFO_SIZE, &mius_engine_tag_cache }, + { MIUS_OBJ_ID_ML_DATA, MIUS_ML_DATA_SIZE, &mius_engine_ml_data_cache }, +}; + +void mius_set_calibration_data(uint8_t *calib_data, size_t size) +{ + struct mius_shared_data_block *calibration_obj = NULL; + + if (size == MIUS_CALIBRATION_DATA_SIZE) { + calibration_obj = + mius_get_shared_obj(MIUS_OBJ_ID_CALIBRATION_DATA); + memcpy((uint8_t *)&mius_engine_calibration_data_cache, + calib_data, size); + } + if (size == MIUS_CALIBRATION_V2_DATA_SIZE) { + calibration_obj = + mius_get_shared_obj(MIUS_OBJ_ID_CALIBRATION_V2_DATA); + memcpy((uint8_t *)&mius_engine_calibration_v2_data_cache, + calib_data, size); + } + if (calibration_obj == NULL) { + MI_PRINT_E("ell..set_calibration_data() calib=NULL (%zu)", + size); + return; + } + memcpy((u8 *)calibration_obj->buffer, calib_data, size); +} + +void mius_set_diagnostics_data(uint8_t *diag_data, size_t size) +{ + struct mius_shared_data_block *diagnostics_obj = NULL; + + if (size <= MIUS_DIAGNOSTICS_DATA_SIZE) { + diagnostics_obj = + mius_get_shared_obj(MIUS_OBJ_ID_DIAGNOSTICS_DATA); + if (diagnostics_obj == NULL) { + MI_PRINT_E("el..set_diagnostics_data() NULL (%zu)", + size); + return; + } + memcpy((uint8_t *)&mius_engine_diagnostics_data_cache, + diag_data, size); + memcpy((u8 *)diagnostics_obj->buffer, diag_data, size); + } +} + +static const size_t NUM_SHARED_RW_OBJS = + sizeof(shared_data_blocks) / sizeof(struct mius_shared_data_block); + +struct mius_shared_data_block *mius_get_shared_obj(uint32_t object_id) +{ + size_t i; + + for (i = 0; i < NUM_SHARED_RW_OBJS; ++i) { + if (shared_data_blocks[i].object_id == object_id) + return &shared_data_blocks[i]; + } + + return NULL; +} + +static const char *const ultrasound_enable_texts[] = { "Off", "On" }; + +static const struct soc_enum mius_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ultrasound_enable_texts), + ultrasound_enable_texts), +}; + +int get_mius_calibration_data(uint8_t *caldata, uint32_t max_size) +{ + uint32_t copied; + + copied = MIUS_CALIBRATION_DATA_SIZE; + if (max_size < MIUS_CALIBRATION_DATA_SIZE) { + copied = max_size; + MI_PRINT_D("size mismatch : %u vs %u", + (uint32_t)MIUS_CALIBRATION_DATA_SIZE, max_size); + } + + memcpy(caldata, (uint8_t *)&mius_engine_calibration_data_cache, + max_size); + return copied; +} + +int get_mius_calibration_v2_data(uint8_t *caldata, uint32_t max_size) +{ + uint32_t copied; + + copied = MIUS_CALIBRATION_V2_DATA_SIZE; + if (max_size < MIUS_CALIBRATION_V2_DATA_SIZE) { + copied = max_size; + MI_PRINT_D("size mismatch : %u vs %u", + (uint32_t)MIUS_CALIBRATION_V2_DATA_SIZE, max_size); + } + + memcpy(caldata, (uint8_t *)&mius_engine_calibration_v2_data_cache, + max_size); + return copied; +} + +int get_mius_diagnostics_data(uint8_t *diagdata, uint32_t max_size) +{ + uint32_t copied; + + copied = MIUS_DIAGNOSTICS_DATA_SIZE; + if (max_size < MIUS_DIAGNOSTICS_DATA_SIZE) { + copied = max_size; + MI_PRINT_D("size mismatch : %u vs %u", + (uint32_t)MIUS_DIAGNOSTICS_DATA_SIZE, max_size); + } + + memcpy(diagdata, (uint8_t *)&mius_engine_diagnostics_data_cache, + max_size); + return copied; +} + +static uint32_t ultrasound_enable_cache; + +int mius_ultrasound_enable_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ultrasound_enable_cache; + return 0; +} + +int mius_ultrasound_enable_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + static bool triggered_engine_info; + int32_t msg[4] = { 0, 0, 0, 0 }; + + ultrasound_enable_cache = ucontrol->value.integer.value[0]; + + if (!triggered_engine_info && ultrasound_enable_cache) { + triggered_engine_info = true; + mius_trigger_version_msg(); + mius_trigger_branch_msg(); + mius_trigger_tag_msg(); + } + + msg[0] = ultrasound_enable_cache ? 1 : 0; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} + +static uint32_t ultrasound_tx_port_cache; + +int mius_ultrasound_tx_port_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ultrasound_tx_port_cache; + return 0; +} + +int mius_ultrasound_tx_port_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret; + + if (ultrasound_tx_port_cache == ucontrol->value.integer.value[0]) { + MI_PRINT_E( + "ultrasound_tx_port_set: ignoring duplicate request"); + return 0; + } + + ultrasound_tx_port_cache = ucontrol->value.integer.value[0]; + printk(KERN_DEBUG "[MIUS] Via ULTRASOUND_TX_PORT_ID enable=%d", + ultrasound_tx_port_cache); + if (ultrasound_tx_port_cache) + ret = mius_open_port(ULTRASOUND_TX_PORT_ID); + else + ret = mius_close_port(ULTRASOUND_TX_PORT_ID); + + MI_PRINT_E("ultrasound_tx_port: enable=%d ret=%d", + ultrasound_tx_port_cache, ret); + + return ret; +} + +static uint32_t ultrasound_rx_port_cache; + +int mius_ultrasound_rx_port_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ultrasound_rx_port_cache; + return 0; +} + +int mius_ultrasound_rx_port_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret; + + if (ultrasound_rx_port_cache == ucontrol->value.integer.value[0]) { + MI_PRINT_E( + "mi ultrasound_rx_port_set: ignoring duplicate request"); + return 0; + } + + ultrasound_rx_port_cache = ucontrol->value.integer.value[0]; + printk(KERN_DEBUG + "[MIUS] if we are here, it is wrong for mius, enable=%d", + ultrasound_rx_port_cache); + if (ultrasound_rx_port_cache) + ret = mius_open_port(ULTRASOUND_RX_PORT_ID); + else + ret = mius_close_port(ULTRASOUND_RX_PORT_ID); + + MI_PRINT_E("mi ultrasound_rx_port: enable=%d ret=%d", + ultrasound_rx_port_cache, ret); + + return 0; +} + +int mius_ultrasound_rampdown_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* Rampdown is a strobe, so always return Off */ + ucontrol->value.integer.value[0] = 0; + return 0; +} + +int mius_ultrasound_rampdown_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t msg[4] = { -1, 0, 0, 0 }; + + if (ucontrol->value.integer.value[0] == 0) + return 0; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} + +int mius_ultrasound_diagnostics_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* Diagnostics is a strobe, so always return Off */ + ucontrol->value.integer.value[0] = 0; + return 0; +} + +int mius_ultrasound_request_diagnostics(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int32_t msg[3] = { MSC_ENGINE_DIAGNOSTICS, 0, 0 }; + + if (ucontrol->value.integer.value[0] == 0) + return 0; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} + +int mius_system_configuration_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &mius_system_configuration, + MIUS_SYSTEM_CONFIGURATION_SIZE); + return 0; +} + +int mius_system_configuration_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&mius_system_configuration, ucontrol->value.bytes.data, + MIUS_SYSTEM_CONFIGURATION_SIZE); + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, + (const char *)&mius_system_configuration, + MIUS_SYSTEM_CONFIGURATION_SIZE); +} + +int mius_calibration_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &mius_engine_calibration_data_cache, + MIUS_CALIBRATION_DATA_SIZE); + return 0; +} + +int mius_calibration_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&mius_engine_calibration_data_cache, ucontrol->value.bytes.data, + MIUS_CALIBRATION_DATA_SIZE); + + return mius_data_write( + MIUS_ULTRASOUND_SET_PARAMS, + (const char *)&mius_engine_calibration_data_cache, + MIUS_CALIBRATION_DATA_SIZE); +} + +int mius_calibration_v2_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct mius_shared_data_block *calibration_obj = + mius_get_shared_obj(MIUS_OBJ_ID_CALIBRATION_V2_DATA); + + if (calibration_obj == NULL) { + MI_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + memcpy(ucontrol->value.bytes.data, calibration_obj->buffer, + MIUS_CALIBRATION_V2_DATA_SIZE); + return 0; +} + +int mius_calibration_v2_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&mius_engine_calibration_v2_data_cache, + ucontrol->value.bytes.data, MIUS_CALIBRATION_V2_DATA_SIZE); + + return mius_data_write( + MIUS_ULTRASOUND_SET_PARAMS, + (const char *)&mius_engine_calibration_v2_data_cache, + MIUS_CALIBRATION_V2_DATA_SIZE); +} + +int mius_diagnostics_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &mius_engine_diagnostics_data_cache, + MIUS_DIAGNOSTICS_DATA_SIZE); + return 0; +} + +int mius_diagnostics_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int mius_ml_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct mius_shared_data_block *ml_obj = + mius_get_shared_obj(MIUS_OBJ_ID_ML_DATA); + + if (ml_obj == NULL) { + MI_PRINT_E("ml_obj is NULL"); + return -EINVAL; + } + + memcpy(ucontrol->value.bytes.data, ml_obj->buffer, MIUS_ML_DATA_SIZE); + return 0; +} + +int mius_ml_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, + (const char *)ucontrol->value.bytes.data, + MIUS_ML_DATA_SIZE); +} + +int mius_sensor_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &mius_engine_sensor_data_cache, + MIUS_SENSOR_DATA_SIZE); + return 0; +} + +int mius_sensor_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(&mius_engine_sensor_data_cache, ucontrol->value.bytes.data, + MIUS_SENSOR_DATA_SIZE); + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, + (const char *)&mius_engine_sensor_data_cache, + MIUS_SENSOR_DATA_SIZE); +} + +int mius_version_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &mius_engine_version_cache, + MIUS_VERSION_INFO_SIZE); + return 0; +} + +int mius_version_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int mius_branch_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &mius_engine_branch_cache, + MIUS_BRANCH_INFO_MAX_SIZE); + return 0; +} + +int mius_branch_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int mius_tag_data_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + memcpy(ucontrol->value.bytes.data, &mius_engine_tag_cache, + MIUS_TAG_INFO_SIZE); + return 0; +} + +int mius_tag_data_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +int mius_calibration_param_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + if (mc->reg != MIUS_CALIBRATION) + return -EINVAL; + + switch (mc->shift) { + case MIUS_CALIBRATION_STATE: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.calibration_state; + break; + + case MIUS_CALIBRATION_PROFILE: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.calibration_profile; + break; + + case MIUS_ULTRASOUND_GAIN: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.ultrasound_gain; + break; + + default: + return -EINVAL; + } + + return 1; +} + +int mius_calibration_param_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct mius_system_configuration_parameter param; + + if (mc->reg != MIUS_CALIBRATION) + return -EINVAL; + + switch (mc->shift) { + case MIUS_CALIBRATION_STATE: + mius_system_configuration_cache.calibration_state = + ucontrol->value.integer.value[0]; + + param.type = MSC_CALIBRATION_STATE; + param.calibration_state = + mius_system_configuration_cache.calibration_state; + break; + + case MIUS_CALIBRATION_PROFILE: + mius_system_configuration_cache.calibration_profile = + ucontrol->value.integer.value[0]; + + param.type = MSC_CALIBRATION_PROFILE; + param.calibration_profile = + mius_system_configuration_cache.calibration_profile; + break; + + case MIUS_ULTRASOUND_GAIN: + mius_system_configuration_cache.ultrasound_gain = + ucontrol->value.integer.value[0]; + param.type = MSC_ULTRASOUND_GAIN; + param.ultrasound_gain = + mius_system_configuration_cache.ultrasound_gain; + break; + + default: + return -EINVAL; + } + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (u8 *)¶m, + sizeof(param)); +} + +int mius_system_configuration_param_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + + pr_err("%s: reg: %d shift: %d\n", __func__, mc->reg, mc->shift); + + if (mc->reg != MIUS_SYSTEM_CONFIGURATION) + return -EINVAL; + + if (mc->shift >= MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0 && + mc->shift <= MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15) { + MI_PRINT_E("get MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_%02d", + mc->shift - + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0); + ucontrol->value.integer.value[0] = 0; + return 1; + } + + switch (mc->shift) { + case MIUS_SYSTEM_CONFIGURATION_LATENCY: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.latency; + break; + + case MIUS_SYSTEM_CONFIGURATION_SENSITIVITY: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.sensitivity; + break; + + case MIUS_SYSTEM_CONFIGURATION_SPEAKER_SCALING: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.speaker_scaling[0]; + ucontrol->value.integer.value[1] = + mius_system_configuration_cache.speaker_scaling[1]; + break; + + case MIUS_SYSTEM_CONFIGURATION_MICROPHONE_INDEX: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.microphone_index; + break; + + case MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.operation_mode; + break; + + case MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.operation_mode_flags; + break; + + case MIUS_SYSTEM_CONFIGURATION_LOG_LEVEL: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.log_level; + break; + case MIUS_SYSTEM_CONFIGURATION_SUSPEND: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.engine_suspend; + break; + case MIUS_SYSTEM_CONFIGURATION_INPUT_ENABLED: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.input_enabled; + break; + case MIUS_SYSTEM_CONFIGURATION_OUTPUT_ENABLED: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.output_enabled; + break; + case MIUS_SYSTEM_CONFIGURATION_EXTERNAL_EVENT: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.external_event; + break; + case MIUS_SYSTEM_CONFIGURATION_CALIBRATION_METHOD: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.calibration_method; + case MIUS_SYSTEM_CONFIGURATION_DEBUG_MODE: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.debug_mode; + break; + case MIUS_SYSTEM_CONFIGURATION_CONTEXT: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.context; + break; + case MIUS_SYSTEM_CONFIGURATION_CAPTURE: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.capture; + break; + case MIUS_SYSTEM_CONFIGURATION_INPUT_CHANNELS: + ucontrol->value.integer.value[0] = + mius_system_configuration_cache.input_channels; + break; + + default: + MI_PRINT_E("Invalid mixer control"); + return -EINVAL; + } + + return 1; +} + +int mius_system_configuration_param_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct mius_system_configuration_parameter param; + struct timeval tv; + + if (mc->reg != MIUS_SYSTEM_CONFIGURATION) + return -EINVAL; + + if (mc->shift >= MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0 && + mc->shift <= MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15) { + const size_t csi = + mc->shift - MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0; + MI_PRINT_E( + "MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_XX csi:%zu", + csi); + if (csi >= + ARRAY_SIZE(mius_system_configuration_cache.custom_settings)) + return -EINVAL; + MI_PRINT_E("ucontrol->value.integer.value[0]:%ld", + ucontrol->value.integer.value[0]); + mius_system_configuration_cache.custom_settings[csi] = + ucontrol->value.integer.value[0]; + param.type = MSC_ENGINE_CUSTOM_SETTING_0 + csi; + param.custom_setting = ucontrol->value.integer.value[0]; + MI_PRINT_E("calling mius_data_write(custom_setting) csi:%zu", + csi); + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, + (const char *)¶m, sizeof(param)); + } + + switch (mc->shift) { + case MIUS_SYSTEM_CONFIGURATION_LATENCY: + mius_system_configuration_cache.latency = + ucontrol->value.integer.value[0]; + param.type = MSC_LATENCY; + param.latency = mius_system_configuration_cache.latency; + break; + + case MIUS_SYSTEM_CONFIGURATION_SENSITIVITY: + mius_system_configuration_cache.sensitivity = + ucontrol->value.integer.value[0]; + param.type = MSC_CHANNEL_SENSITIVITY; + param.sensitivity = mius_system_configuration_cache.sensitivity; + break; + + case MIUS_SYSTEM_CONFIGURATION_SPEAKER_SCALING: + mius_system_configuration_cache.speaker_scaling[0] = + ucontrol->value.integer.value[0]; + mius_system_configuration_cache.speaker_scaling[1] = + ucontrol->value.integer.value[1]; + param.type = MSC_SPEAKER_SCALING; + param.speaker_scaling[0] = + mius_system_configuration_cache.speaker_scaling[0]; + param.speaker_scaling[1] = + mius_system_configuration_cache.speaker_scaling[1]; + break; + + case MIUS_SYSTEM_CONFIGURATION_MICROPHONE_INDEX: + mius_system_configuration_cache.microphone_index = + ucontrol->value.integer.value[0]; + param.type = MSC_MICROPHONE_INDEX; + param.microphone_index = + mius_system_configuration_cache.microphone_index; + break; + + case MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE: + mius_system_configuration_cache.operation_mode = + ucontrol->value.integer.value[0]; + param.type = MSC_OPERATION_MODE; + param.operation_mode = + mius_system_configuration_cache.operation_mode; + break; + + case MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS: + mius_system_configuration_cache.operation_mode_flags = + ucontrol->value.integer.value[0]; + param.type = MSC_OPERATION_MODE_FLAGS; + param.operation_mode_flags = + mius_system_configuration_cache.operation_mode_flags; + break; + + case MIUS_SYSTEM_CONFIGURATION_LOG_LEVEL: + mius_system_configuration_cache.log_level = + ucontrol->value.integer.value[0]; + param.type = MSC_LOG_LEVEL; + param.log_level = mius_system_configuration_cache.log_level; + break; + case MIUS_SYSTEM_CONFIGURATION_INPUT_ENABLED: + mius_system_configuration_cache.input_enabled = + ucontrol->value.integer.value[0]; + param.type = MSC_INPUT_ENABLED; + param.input_enabled = + mius_system_configuration_cache.input_enabled; + break; + case MIUS_SYSTEM_CONFIGURATION_OUTPUT_ENABLED: + mius_system_configuration_cache.output_enabled = + ucontrol->value.integer.value[0]; + param.type = MSC_OUTPUT_ENABLED; + param.output_enabled = + mius_system_configuration_cache.output_enabled; + break; + case MIUS_SYSTEM_CONFIGURATION_SUSPEND: + mius_system_configuration_cache.engine_suspend = + ucontrol->value.integer.value[0]; + param.type = MSC_SUSPEND; + param.engine_suspend = + mius_system_configuration_cache.engine_suspend; + break; + case MIUS_SYSTEM_CONFIGURATION_EXTERNAL_EVENT: + mius_system_configuration_cache.external_event = + ucontrol->value.integer.value[0]; + param.type = MSC_EXTERNAL_EVENT; + param.external_event = + mius_system_configuration_cache.external_event; + break; + case MIUS_SYSTEM_CONFIGURATION_CALIBRATION_METHOD: + mius_system_configuration_cache.calibration_method = + ucontrol->value.integer.value[0]; + param.type = MSC_CALIBRATION_METHOD; + param.calibration_method = + mius_system_configuration_cache.calibration_method; + do_gettimeofday(&tv); + param.calibration_timestamp = (int32_t)tv.tv_sec; + break; + case MIUS_SYSTEM_CONFIGURATION_DEBUG_MODE: + mius_system_configuration_cache.debug_mode = + ucontrol->value.integer.value[0]; + param.type = MSC_DEBUG_MODE; + param.debug_mode = mius_system_configuration_cache.debug_mode; + break; + case MIUS_SYSTEM_CONFIGURATION_CONTEXT: + mius_system_configuration_cache.context = + ucontrol->value.integer.value[0]; + param.type = MSC_CONTEXT; + param.context = mius_system_configuration_cache.context; + break; + case MIUS_SYSTEM_CONFIGURATION_CAPTURE: + mius_system_configuration_cache.capture = + ucontrol->value.integer.value[0]; + param.type = MSC_CAPTURE; + param.context = mius_system_configuration_cache.capture; + break; + case MIUS_SYSTEM_CONFIGURATION_INPUT_CHANNELS: + mius_system_configuration_cache.input_channels = + ucontrol->value.integer.value[0]; + param.type = MSC_INPUT_CHANNELS; + param.context = mius_system_configuration_cache.input_channels; + break; + + default: + return -EINVAL; + } + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)¶m, + sizeof(param)); +} + +static const struct snd_kcontrol_new ultrasound_filter_mixer_controls[] = { + SOC_ENUM_EXT("Mi_Ultrasound Enable", mius_enum[0], + mius_ultrasound_enable_get, mius_ultrasound_enable_set), + SOC_ENUM_EXT("Mi_Ultrasound RampDown", mius_enum[0], + mius_ultrasound_rampdown_get, + mius_ultrasound_rampdown_set), + SOC_SINGLE_EXT("Mi_Ultrasound Latency", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_LATENCY, 10000, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Sensitivity", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_SENSITIVITY, 1000000, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_DOUBLE_EXT("Mi_Ultrasound Speaker Scaling", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_SPEAKER_SCALING, 0, 1000000, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Microphone Index", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_MICROPHONE_INDEX, 20, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Mode", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE, 255, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Mode Flags", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS, 256, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Calibration Profile", MIUS_CALIBRATION, + MIUS_CALIBRATION_PROFILE, 256, 0, + mius_calibration_param_get, mius_calibration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Gain", MIUS_CALIBRATION, + MIUS_ULTRASOUND_GAIN, 256, 0, mius_calibration_param_get, + mius_calibration_param_put), + + SOC_SINGLE_EXT("Mi_Ultrasound Calibration State", MIUS_CALIBRATION, + MIUS_CALIBRATION_STATE, 256, 0, + mius_calibration_param_get, mius_calibration_param_put), + + SND_SOC_BYTES_EXT("Mi_Ultrasound System Configuration", + MIUS_SYSTEM_CONFIGURATION_SIZE, + mius_system_configuration_get, + mius_system_configuration_put), + SND_SOC_BYTES_EXT("Mi_Ultrasound Calibration Data", + MIUS_CALIBRATION_DATA_SIZE, mius_calibration_data_get, + mius_calibration_data_put), + SND_SOC_BYTES_EXT("Mi_Ultrasound Version", MIUS_VERSION_INFO_SIZE, + mius_version_data_get, mius_version_data_put), + SND_SOC_BYTES_EXT("Mi_Ultrasound Branch", MIUS_BRANCH_INFO_MAX_SIZE, + mius_branch_data_get, mius_branch_data_put), + SND_SOC_BYTES_EXT("Mi_Ultrasound Tag", MIUS_TAG_INFO_SIZE, + mius_tag_data_get, mius_tag_data_put), + SOC_SINGLE_EXT("Mi_Ultrasound Log Level", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_LOG_LEVEL, 7, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + + SND_SOC_BYTES_EXT("Mi_Ultrasound Calibration Ext Data", + MIUS_CALIBRATION_V2_DATA_SIZE, + mius_calibration_v2_data_get, + mius_calibration_v2_data_put), + + SND_SOC_BYTES_EXT("Mi_Ultrasound Diagnostics Data", + MIUS_DIAGNOSTICS_DATA_SIZE, mius_diagnostics_data_get, + mius_diagnostics_data_put), + + SOC_ENUM_EXT("Mi_Ultrasound Diagnostics Request", mius_enum[0], + mius_ultrasound_diagnostics_get, + mius_ultrasound_request_diagnostics), + + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 0", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 1", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_1, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 2", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_2, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 3", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_3, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 4", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_4, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 5", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_5, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 6", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_6, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 7", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_7, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 8", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_8, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 9", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_9, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 10", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_10, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 11", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_11, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 12", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_12, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 13", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_13, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 14", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_14, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Custom Setting 15", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15, + MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_ENUM_EXT("Mi_Ultrasound Tx Port", mius_enum[0], + mius_ultrasound_tx_port_get, mius_ultrasound_tx_port_set), + SOC_ENUM_EXT("Mi_Ultrasound Rx Port", mius_enum[0], + mius_ultrasound_rx_port_get, mius_ultrasound_rx_port_set), + SOC_SINGLE_EXT("Mi_Ultrasound Suspend", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_SUSPEND, 1, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Input", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_INPUT_ENABLED, 1, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Output", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_OUTPUT_ENABLED, 1, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Event", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_EXTERNAL_EVENT, 256, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Calibration Method", + MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CALIBRATION_METHOD, 256, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + + SND_SOC_BYTES_EXT("Mi_Ultrasound ML", MIUS_ML_DATA_SIZE, + mius_ml_data_get, mius_ml_data_put), + + SOC_SINGLE_EXT("Mi_Ultrasound Debug Mode", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_DEBUG_MODE, 256, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SOC_SINGLE_EXT("Mi_Ultrasound Context", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CONTEXT, + MIUS_SYSTEM_CONFIGURATION_MAX_CONTEXT_VALUE, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + SND_SOC_BYTES_EXT("Mi_Ultrasound Sensor Data", MIUS_SENSOR_DATA_SIZE, + mius_sensor_data_get, mius_sensor_data_put), + + SOC_SINGLE_EXT("Mi_Ultrasound Capture", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_CAPTURE, 256, -1, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + + SOC_SINGLE_EXT("Mi_Ultrasound Tx Channels", MIUS_SYSTEM_CONFIGURATION, + MIUS_SYSTEM_CONFIGURATION_INPUT_CHANNELS, 16, 0, + mius_system_configuration_param_get, + mius_system_configuration_param_put), + +}; + +unsigned int mius_add_platform_controls(void *platform) +{ + const unsigned int num_controls = + ARRAY_SIZE(ultrasound_filter_mixer_controls); + + if (platform != NULL) { + snd_soc_add_platform_controls( + (struct snd_soc_platform *)platform, + ultrasound_filter_mixer_controls, num_controls); + } else { + MI_PRINT_E("pointer is NULL"); + } + + return num_controls; +} +EXPORT_SYMBOL(mius_add_platform_controls); + +int mius_trigger_version_msg(void) +{ + int32_t msg[3] = { MSC_ENGINE_VERSION, 0, 0 }; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} + +int mius_trigger_branch_msg(void) +{ + int32_t msg[3] = { MSC_BUILD_BRANCH, 0, 0 }; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} + +int mius_trigger_tag_msg(void) +{ + int32_t msg[3] = { MSC_ENGINE_TAG, 0, 0 }; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} + +int mius_trigger_diagnostics_msg(void) +{ + int32_t msg[3] = { MSC_ENGINE_DIAGNOSTICS, 0, 0 }; + + return mius_data_write(MIUS_ULTRASOUND_SET_PARAMS, (const char *)msg, + sizeof(msg)); +} diff --git a/techpack/audio/dsp/mius/mius_sysfs.c b/techpack/audio/dsp/mius/mius_sysfs.c new file mode 100644 index 000000000000..145dd699a470 --- /dev/null +++ b/techpack/audio/dsp/mius/mius_sysfs.c @@ -0,0 +1,645 @@ +#include +#include +#include +#include +#include +#include +#include +#include "mius_version.h" +#include + +#define MIUS_DIAGNOSTICS_DATA_SECTION_COUNT 16 +#define MIUS_CALIBRATION_MAX_DISPLAY_COUNT 96 +#define MIUS_ML_DISPLAY_COUNT 16 + +static int kobject_create_and_add_failed; +static int sysfs_create_group_failed; + +extern struct mius_system_configuration_parameters_cache + mius_system_configuration_cache; + +static ssize_t calibration_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + ssize_t result; + + struct mius_shared_data_block *calibration_obj = + mius_get_shared_obj(MIUS_OBJ_ID_CALIBRATION_DATA); + + if (calibration_obj == NULL) { + MI_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (count > calibration_obj->size) { + MI_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(calibration_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t calibration_v2_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t result; + + struct mius_shared_data_block *calibration_obj = + mius_get_shared_obj(MIUS_OBJ_ID_CALIBRATION_V2_DATA); + + if (calibration_obj == NULL) { + MI_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (count > calibration_obj->size) { + MI_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(calibration_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t diagnostics_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + ssize_t result; + + struct mius_shared_data_block *diagnostics_obj = + mius_get_shared_obj(MIUS_OBJ_ID_DIAGNOSTICS_DATA); + + if (diagnostics_obj == NULL) { + MI_PRINT_E("diagnostics_obj is NULL"); + return -EINVAL; + } + + if (count > diagnostics_obj->size) { + MI_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(diagnostics_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t ml_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t result; + + struct mius_shared_data_block *ml_obj = + mius_get_shared_obj(MIUS_OBJ_ID_ML_DATA); + + if (ml_obj == NULL) { + MI_PRINT_E("ml_obj is NULL"); + return -EINVAL; + } + + if (count > ml_obj->size) { + MI_PRINT_E("write length %zu larger than buffer", count); + return 0; + } + + memcpy(ml_obj->buffer, buf, count); + result = (ssize_t)count; + return result; +} + +static ssize_t calibration_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + ssize_t result; + int length; + int i; + uint8_t *caldata; + + struct mius_shared_data_block *calibration_obj = + mius_get_shared_obj(MIUS_OBJ_ID_CALIBRATION_DATA); + + if (kobject_create_and_add_failed) + MI_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + MI_PRINT_E("sysfs_create_group_failed"); + + if (calibration_obj == NULL) { + MI_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (calibration_obj->size > PAGE_SIZE) { + MI_PRINT_E("calibration_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + caldata = (uint8_t *)calibration_obj->buffer; + length = 0; + if (pretty) { + if (caldata[0] == 0xDE && caldata[1] == 0xAD) { + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Data: not loaded"); + } else { + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Data: "); + for (i = 0; i < calibration_obj->size; ++i) + length += snprintf(buf + length, + PAGE_SIZE - length, + "0x%02x ", caldata[i]); + } + } else { + for (i = 0; i < calibration_obj->size; ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + "0x%02x ", caldata[i]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t calibration_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return calibration_show_core(dev, attr, buf, 0); +} + +static ssize_t calibration_v2_show_core(struct device *dev, + struct device_attribute *attr, + char *buf, int pretty) +{ + ssize_t result; + int length; + int i; + uint8_t *caldata; + + struct mius_shared_data_block *calibration_obj = + mius_get_shared_obj(MIUS_OBJ_ID_CALIBRATION_V2_DATA); + + if (kobject_create_and_add_failed) + MI_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + MI_PRINT_E("sysfs_create_group_failed"); + + if (calibration_obj == NULL) { + MI_PRINT_E("calibration_obj is NULL"); + return -EINVAL; + } + + if (calibration_obj->size > PAGE_SIZE) { + MI_PRINT_E("calibration_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + caldata = (uint8_t *)calibration_obj->buffer; + length = 0; + if (pretty) { + if (caldata[0] == 0xDE && caldata[1] == 0xAD) { + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Ext Data: not loaded"); + } else { + int j = (MIUS_CALIBRATION_V2_DATA_SIZE >> 2) - 1; + + length += snprintf(buf + length, PAGE_SIZE - length, + "Calibration Ext Data: "); + for (i = 0; i < MIUS_CALIBRATION_MAX_DISPLAY_COUNT; ++i) + length += snprintf(buf + length, + PAGE_SIZE - length, + "0x%02x ", caldata[i]); + length += snprintf(buf + length, PAGE_SIZE - length, + "\nTruncated at %d", + MIUS_CALIBRATION_MAX_DISPLAY_COUNT); + length += snprintf(buf + length, PAGE_SIZE - length, + "\nmisc: %u %u %u %u %u %u %u %u\n", + caldata[j - 7], caldata[j - 6], + caldata[j - 5], caldata[j - 4], + caldata[j - 3], caldata[j - 2], + caldata[j - 1], caldata[j]); + } + } else { + for (i = 0; i < calibration_obj->size; ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + "0x%02x ", caldata[i]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t calibration_v2_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return calibration_v2_show_core(dev, attr, buf, 0); +} + +static ssize_t diagnostics_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + ssize_t result; + int length; + uint32_t *data32; + int i; + + struct mius_shared_data_block *diagnostics_obj = + mius_get_shared_obj(MIUS_OBJ_ID_DIAGNOSTICS_DATA); + + if (kobject_create_and_add_failed) + MI_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + MI_PRINT_E("sysfs_create_group_failed"); + + if (diagnostics_obj == NULL) { + MI_PRINT_E("diagnostics_obj is NULL"); + return -EINVAL; + } + + if (diagnostics_obj->size > PAGE_SIZE) { + MI_PRINT_E("diagnostics_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + length = 0; + data32 = (uint32_t *)diagnostics_obj->buffer; + + if (pretty) { + length += snprintf(buf + length, PAGE_SIZE - length, + "Diagnostics:\n counters:\n"); + for (i = 0; i < MIUS_DIAGNOSTICS_DATA_SECTION_COUNT; i++) + length += snprintf(buf + length, PAGE_SIZE - length, + " %u %u %u %u\n", data32[4 * i], + data32[4 * i + 1], data32[4 * i + 2], + data32[4 * i + 3]); + } else { + for (i = 0; i < (diagnostics_obj->size >> 4); ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + " %u %u %u %u\n", data32[4 * i], + data32[4 * i + 1], data32[4 * i + 2], + data32[4 * i + 3]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t diagnostics_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return diagnostics_show_core(dev, attr, buf, 0); +} + +static ssize_t ml_show_core(struct device *dev, struct device_attribute *attr, + char *buf, int pretty) +{ + ssize_t result; + int length; + int i; + uint32_t *mldata; + + struct mius_shared_data_block *ml_obj = + mius_get_shared_obj(MIUS_OBJ_ID_ML_DATA); + + if (kobject_create_and_add_failed) + MI_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + MI_PRINT_E("sysfs_create_group_failed"); + + if (ml_obj == NULL) { + MI_PRINT_E("ml_obj is NULL"); + return -EINVAL; + } + + if (ml_obj->size > PAGE_SIZE) { + MI_PRINT_E("ml_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + mldata = (uint32_t *)ml_obj->buffer; + length = 0; + if (pretty) { + if (mldata[0] == 0x0 && mldata[1] == 0x0) { + length += snprintf(buf + length, PAGE_SIZE - length, + "ML Data: not loaded"); + } else { + length += snprintf(buf + length, PAGE_SIZE - length, + "ML Data: "); + for (i = 0; i < MIUS_ML_DISPLAY_COUNT; ++i) + length += snprintf(buf + length, + PAGE_SIZE - length, + "0x%08x ", mldata[i]); + length += snprintf(buf + length, PAGE_SIZE - length, + "\nTruncated at %d", + MIUS_ML_DISPLAY_COUNT); + } + } else { + int values = ml_obj->size >> 2; + + for (i = 0; i < values; ++i) + length += snprintf(buf + length, PAGE_SIZE - length, + "0x%08x ", mldata[i]); + } + length += snprintf(buf + length, PAGE_SIZE - length, "\n\n"); + result = (ssize_t)length; + return result; +} + +static ssize_t ml_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return ml_show_core(dev, attr, buf, 0); +} + +static ssize_t version_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + ssize_t result; + struct mius_engine_version_info *version_info; + int length; + + struct mius_shared_data_block *version_obj = + mius_get_shared_obj(MIUS_OBJ_ID_VERSION_INFO); + + if (kobject_create_and_add_failed) + MI_PRINT_E("kobject_create_and_add_failed"); + + if (sysfs_create_group_failed) + MI_PRINT_E("sysfs_create_group_failed"); + + if (version_obj == NULL) { + MI_PRINT_E("version_obj is NULL"); + return -EINVAL; + } + + if (version_obj->size > PAGE_SIZE) { + MI_PRINT_E("version_obj->size > PAGE_SIZE"); + return -EINVAL; + } + + version_info = (struct mius_engine_version_info *)version_obj->buffer; + + if (pretty) { + if (version_info->major == 0xDE && + version_info->minor == 0xAD) { + length = snprintf(buf, PAGE_SIZE, "Version: unknown\n"); + } else { + length = snprintf( + buf, PAGE_SIZE, "Version: %d.%d.%d.%d\n", + version_info->major, version_info->minor, + version_info->build, version_info->revision); + } + } else { + length = snprintf(buf, PAGE_SIZE, "%d.%d.%d.%d\n", + version_info->major, version_info->minor, + version_info->build, version_info->revision); + } + result = (ssize_t)length; + return result; +} + +static ssize_t version_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return version_show_core(dev, attr, buf, 0); +} + +static ssize_t branch_show_core(struct device *dev, + struct device_attribute *attr, char *buf, + int pretty) +{ + int length; + + struct mius_shared_data_block *branch_obj = + mius_get_shared_obj(MIUS_OBJ_ID_BRANCH_INFO); + + if (branch_obj == NULL) { + MI_PRINT_E("branch_obj not found"); + return 0; + } + + if (branch_obj->size > PAGE_SIZE) { + MI_PRINT_E("branch_obj->size > PAGE_SIZE"); + return -EINVAL; + } + if (pretty) { + length = snprintf(buf, PAGE_SIZE - 1, "Branch: %s\n", + (const char *)(branch_obj->buffer)); + } else { + length = snprintf(buf, PAGE_SIZE - 1, "%s\n", + (const char *)(branch_obj->buffer)); + } + + return (ssize_t)length; +} + +static ssize_t branch_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return branch_show_core(dev, attr, buf, 0); +} + +static ssize_t tag_show_core(struct device *dev, struct device_attribute *attr, + char *buf, int pretty) +{ + int length; + + struct mius_shared_data_block *tag_obj = + mius_get_shared_obj(MIUS_OBJ_ID_TAG_INFO); + + if (tag_obj == NULL) { + MI_PRINT_E("tag_obj not found"); + return 0; + } + + if (tag_obj->size > PAGE_SIZE) { + MI_PRINT_E("tag_obj->size > PAGE_SIZE"); + return -EINVAL; + } + if (pretty) { + length = snprintf(buf, PAGE_SIZE - 1, "Tag: %s\n", + (const char *)(tag_obj->buffer)); + } else { + length = snprintf(buf, PAGE_SIZE - 1, "%s\n", + (const char *)(tag_obj->buffer)); + } + + return (ssize_t)length; +} + +static ssize_t tag_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return tag_show_core(dev, attr, buf, 0); +} + +static ssize_t cache_show(char *buf, int pretty) +{ + struct mius_system_configuration_parameters_cache *cache = + &mius_system_configuration_cache; + + int length; + + length = snprintf(buf, PAGE_SIZE - 1, "Cache:\n"); + length += snprintf(buf + length, PAGE_SIZE - 1, " mi:%d\n", + cache->microphone_index); + length += snprintf(buf + length, PAGE_SIZE - 1, " om:%d\n", + cache->operation_mode); + length += snprintf(buf + length, PAGE_SIZE - 1, " omf:%d\n", + cache->operation_mode_flags); + length += snprintf(buf + length, PAGE_SIZE - 1, " cs:%d\n", + cache->calibration_state); + length += snprintf(buf + length, PAGE_SIZE - 1, " cp:%d\n", + cache->calibration_profile); + length += snprintf(buf + length, PAGE_SIZE - 1, " ug:%d\n", + cache->ultrasound_gain); + length += snprintf(buf + length, PAGE_SIZE - 1, " ll:%d\n", + cache->log_level); + length += snprintf(buf + length, PAGE_SIZE - 1, " es:%d\n", + cache->engine_suspend); + + return (ssize_t)length; +} + +static ssize_t opmode_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int length; + ssize_t result; + + struct mius_system_configuration_parameters_cache *cache = + &mius_system_configuration_cache; + + length += snprintf(buf + length, PAGE_SIZE - 1, "%d\n", + cache->operation_mode); + result = (ssize_t)length; + return result; +} + +static ssize_t opmode_flags_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int length; + ssize_t result; + struct mius_system_configuration_parameters_cache *cache = + &mius_system_configuration_cache; + + length += snprintf(buf + length, PAGE_SIZE - 1, "%d\n", + cache->operation_mode_flags); + result = (ssize_t)length; + return result; +} + +static ssize_t driver_version_show(char *buf) +{ + int length; + + length = snprintf(buf, PAGE_SIZE, "Driver version: %s-%s (%s)\n", + build_name, build_number, build_source_version); + + return (ssize_t)length; +} + +static ssize_t state_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int length = 0; + + length += driver_version_show(buf + length); + length += version_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += branch_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += tag_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += calibration_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += calibration_v2_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += diagnostics_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += ml_show_core(dev, attr, buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + length += cache_show(buf + length, 1); + if (length > PAGE_SIZE) + return (ssize_t)0; + return (ssize_t)length; +} + +static struct device_attribute calibration_attr = __ATTR_RW(calibration); +static struct device_attribute version_attr = __ATTR_RO(version); +static struct device_attribute branch_attr = __ATTR_RO(branch); +static struct device_attribute calibration_v2_attr = __ATTR_RW(calibration_v2); +static struct device_attribute diagnostics_attr = __ATTR_RW(diagnostics); +static struct device_attribute state_attr = __ATTR_RO(state); +static struct device_attribute tag_attr = __ATTR_RO(tag); +static struct device_attribute ml_attr = __ATTR_RW(ml); +static struct device_attribute opmode_attr = __ATTR_RO(opmode); +static struct device_attribute opmode_flags_attr = __ATTR_RO(opmode_flags); + +static struct attribute *mius_attrs[] = { + &calibration_attr.attr, + &version_attr.attr, + &branch_attr.attr, + &calibration_v2_attr.attr, + &diagnostics_attr.attr, + &state_attr.attr, + &tag_attr.attr, + &ml_attr.attr, + &opmode_attr.attr, + &opmode_flags_attr.attr, + NULL, +}; + +static struct attribute_group mius_attr_group = { + .name = MIUS_SYSFS_ENGINE_FOLDER, + .attrs = mius_attrs, +}; + +static struct kobject *mius_sysfs_kobj; + +int mius_initialize_sysfs(void) +{ + int err; + + mius_sysfs_kobj = kobject_create_and_add(MIUS_SYSFS_ROOT_FOLDER, + kernel_kobj->parent); + + if (!mius_sysfs_kobj) { + kobject_create_and_add_failed = 1; + MI_PRINT_E("failed to create kobj"); + return -ENOMEM; + } + + err = sysfs_create_group(mius_sysfs_kobj, &mius_attr_group); + + if (err) { + sysfs_create_group_failed = 1; + MI_PRINT_E("failed to create sysfs group"); + kobject_put(mius_sysfs_kobj); + return -ENOMEM; + } + + return 0; +} + +void mius_cleanup_sysfs(void) +{ + kobject_put(mius_sysfs_kobj); +} diff --git a/techpack/audio/dsp/mius/mius_version.h b/techpack/audio/dsp/mius/mius_version.h new file mode 100644 index 000000000000..ae6be14654ed --- /dev/null +++ b/techpack/audio/dsp/mius/mius_version.h @@ -0,0 +1,8 @@ +#ifndef MIUS_VERSION_H +#define MIUS_VERSION_H + +#define build_name "Mi.LinuxKernelDriver.VendorDLKM.master" +#define build_number "20181016.1" +#define build_source_version "e5e26691554bba9b1438ec3d7e0cc55dfb296bb8" + +#endif //MIUS_VERSION_H diff --git a/techpack/audio/dsp/msm-cirrus-playback-v2.c b/techpack/audio/dsp/msm-cirrus-playback-v2.c new file mode 100644 index 000000000000..aa0b5946f0fb --- /dev/null +++ b/techpack/audio/dsp/msm-cirrus-playback-v2.c @@ -0,0 +1,1405 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +* Copyright (C) 2021 XiaoMi, Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#undef CONFIG_OF +#define CRUS_AMP_FACTOR 71498 +#define CRUS_MATERIAL_FACTOR 250 +#define CRUS_T_SCALE_FACTOR 100000 +#define CRUS_Z_SCALE_FACTOR 100000000 +#define CIRRUS_NONE 0 +#define CIRRUS_COPP 1 +#define CIRRUS_AFE 2 + +#undef pr_info +#undef pr_err +#undef pr_debug +#define pr_debug(fmt, args...) printk(KERN_INFO "[CSPL] " pr_fmt(fmt), ##args) +#define pr_info(fmt, args...) printk(KERN_INFO "[CSPL] " pr_fmt(fmt), ##args) +#define pr_err(fmt, args...) printk(KERN_ERR "[CSPL] " pr_fmt(fmt), ##args) +#define CRUS_TX_CONFIG "crus_sp_tx%d.bin" +#define CRUS_RX_CONFIG "crus_sp_rx%d.bin" + +#define CIRRUS_RX_GET_IODATA 0x00A1AF09 +#define CIRRUS_TX_GET_IODATA 0x00A1BF09 + +static struct crus_sp_ioctl_header crus_sp_hdr; +#define xCACHE_COMMANDS +static struct crus_control_t this = { + .module_id = CIRRUS_SP, + .fb_port = AFE_PORT_ID_QUATERNARY_TDM_TX, + .ff_port = AFE_PORT_ID_QUATERNARY_TDM_RX, + .usecase_dt_count = MAX_TUNING_CONFIGS, + .usecase = 0, + .conf_index = 0, + .delta_index = 0, + .swap_duration = 30, + .location = CIRRUS_COPP, + .sp_enable = 1, // enable by default + .vol_atten = 0, + .resistance_en = true, + .prot_en = false, + .copp_idx = 0, + .copp_ids = { INVALID_COPPID, INVALID_COPPID, INVALID_COPPID }, + + .swap = 0, + .initialized = false, +}; + +#define CHAR_BIT 8 +unsigned int crc32(int *message) +{ /* Only supports 32-bit for now */ + int i, j; + unsigned int crc; + + crc = ~0; + for (i = 0; i < message[0] - 1; + i++) /* Loop through the array, excluding the CRC */ + { + crc = crc ^ message[i]; + for (j = 0; j < sizeof(*message) * CHAR_BIT; j++) { + crc = (crc >> 1) ^ (0xEDB88320 & -(crc & 1)); + } + } + return ~crc; +} + +static int crc_check(int *params, int size) +{ + int crc, crc_idx, ret = 0, i = 0; + + for (i = 0; i < size; i += params[i]) { + crc_idx = i + params[i] - 1; + crc = crc32(¶ms[i]); + if (crc != params[crc_idx]) { + pr_err("crc failed: %d != %d\n", crc, params[crc_idx]); + ret = -1; + } + } + + return ret; +} + +#define IS_DIGIT(number) ((number) >= '0' && (number) <= '9') +#define IS_PARAM_CHAR(number) ((number) == '-' || (IS_DIGIT(number))) +static bool is_params_str(char *str) +{ + int i = 0, start = 0; + bool ret = true; + + if (strlen(str) <= 0) + return -1; + + if (str[0] == '-') + start = 1; + for (i = start; i < strlen(str); i++) { + if (!IS_DIGIT(str[start])) { + ret = false; + break; + } + } + + return ret; +} + +static int tuning_parser(const char *bytes, int size_byte, int *params, + int *size) +{ + int i = 0, n, ret = 0; + char buf[24] = { + 0, + }; + + *size = 0; + for (i = 0; bytes[i] != '\0' && i < size_byte; i++) { + if (!IS_PARAM_CHAR(bytes[i])) + continue; + n = 0; + for (; bytes[i] != ',' && bytes[i] != '\n' && bytes[i] != '\0'; + i++) { + if (!IS_PARAM_CHAR(bytes[i])) + break; + buf[n++] = bytes[i]; + } + + buf[n] = '\0'; + if (!is_params_str(buf)) + continue; + + if (kstrtos32(buf, 10, params++) < 0) + continue; + + *size += 1; + pr_info("%d: %s\n", *size, buf); + } + + return ret; +} + +#ifdef CACHE_COMMANDS +LIST_HEAD(cache_list); +static void cache_block_destroy(void *block) +{ + kfree(block); +} + +static struct cache_block * +crus_block_initial(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol, snd_kcontrol_put_t *put) +{ + struct cache_block *db = + kzalloc(sizeof(struct cache_block), GFP_KERNEL); + + if (db == NULL) { + pr_info("%s: Fail to alloc for: '%s'\n", __func__, + kcontrol->id.name); + return NULL; + } + + memcpy(&db->kcontrol, kcontrol, sizeof(struct snd_kcontrol)); + memcpy(&db->ucontrol, ucontrol, sizeof(struct snd_ctl_elem_value)); + db->destroy = cache_block_destroy; + + return db; +} + +static bool crus_cache_push(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol, + snd_kcontrol_put_t *put) +{ + struct cache_block *db; + struct list_head *cursor, *head; + + if (atomic_read(&this.qdsp_start_count[this.location]) == 0) { + pr_info("%s: port started, no need cache: '%s'\n", __func__, + kcontrol->id.name); + return false; + } + + list_for_each_safe (cursor, head, &cache_list) { + db = list_entry(cursor, struct cache_block, entry); + if (db == NULL) + continue; + if (!strcmp(db->kcontrol.id.name, kcontrol->id.name)) { + pr_info("%s: cache block remove duplicated one: '%s'\n", + __func__, kcontrol->id.name); + list_del(cursor); + cache_block_destroy(db); + break; + } + } + + db = crus_block_initial(kcontrol, ucontrol, put); + if (db == NULL) + return false; + + pr_info("%s: cache block: %p, '%s'\n", __func__, db, kcontrol->id.name); + db->put = put; + list_add_tail(&db->entry, &cache_list); + + return true; +} + +static void crus_cache_pop_execute(void) +{ + struct cache_block *db; + struct list_head *cursor, *head; + + if (list_empty(&cache_list)) + return; + + list_for_each_safe (cursor, head, &cache_list) { + db = list_last_entry(&cache_list, struct cache_block, entry); + if (db == NULL) + continue; + + pr_info("%s:%p - put '%s'\n", __func__, db, + db->kcontrol.id.name); + + if (db->put) { + this.cache_execute = true; + db->put(&db->kcontrol, &db->ucontrol); + this.cache_execute = false; + } + + list_del(cursor); + cache_block_destroy(db); + db = NULL; + } + + INIT_LIST_HEAD(&cache_list); +} +#endif +static int crus_get_copp_id(void) +{ + int i = 0; + for (i = 0; i < 3; i++) { + if (this.copp_ids[i] != INVALID_COPPID) + return this.copp_ids[i]; + } + + return 0; +} +static int crus_get_param(int port_id, int param_id, void *data, int length) +{ + int copp_idx = 0; + + if (atomic_read(&this.qdsp_start_count[this.location]) == 0) { + pr_info("%s: port '0x%x' not yet start!\n", __func__, port_id); + return 0; + } + + switch (this.location) { + case CIRRUS_AFE: + crus_afe_get_params(port_id, this.module_id, param_id, data, + length); + break; + case CIRRUS_COPP: + copp_idx = crus_get_copp_id(); + crus_adm_get_params(port_id, copp_idx, this.instance_id, + this.module_id, param_id, data, length, 0); + break; + default: + break; + } + return 0; +} +static int crus_set_param(int port_id, int param_id, void *data, int length) +{ + int copp_idx = 0; + if (atomic_read(&this.qdsp_start_count[this.location]) == 0) { + pr_info("%s: port '0x%x' not yet start!\n", __func__, port_id); + return 0; + } + + switch (this.location) { + case CIRRUS_AFE: + crus_afe_set_params(port_id, this.module_id, param_id, data, + length); + break; + case CIRRUS_COPP: + copp_idx = crus_get_copp_id(); + crus_adm_set_params(port_id, copp_idx, this.instance_id, + this.module_id, param_id, data, length); + break; + default: + break; + } + return 0; +} + +#define CONF_HEADER(buf, total_bytes, chunk_bytes, done) \ + do { \ + buf[0] = (total_bytes) * sizeof(int); \ + buf[1] = (chunk_bytes) * sizeof(int); \ + buf[2] = (done); \ + buf[3] = 0; \ + buf[4] = 4; \ + } while (0) + +static int crus_send_config(const char *data, int32_t length, int32_t port) +{ + int i = 0, ret = 0, chunk = 90, head_size = 5; + int rest, last_index, total_size; + int *payload = this.apr_payload; + int *params = this.tuning; + int param_id, payload_size; + + pr_err("Wing: Invalid port %d\n", port); + /* Destination settings for message */ + if (port == this.ff_port) + param_id = CRUS_PARAM_RX_SET_EXT_CONFIG; + else if (port == this.fb_port) + param_id = CRUS_PARAM_TX_SET_EXT_CONFIG; + else { + pr_err("Invalid port %d\n", port); + return -EINVAL; + } + + memset(params, 0x00, TUNING_MAX_SIZE * sizeof(int)); + memset(payload, 0x00, APR_CHUNK_SIZE * sizeof(int)); + + //firmware_request("delta0_raw_full.txt", &bytes, &size_byte); + if (tuning_parser(data, length, params, &total_size) < 0) + return -1; + if (crc_check(params, total_size) < 0) + return -1; + + rest = total_size % chunk; + if (rest == 0) { + last_index = total_size / chunk - 1; + rest = chunk; + } else { + last_index = total_size / chunk; + } + + pr_info("rest = %d, last_index=%d, total_size=%d\n", rest, last_index, + total_size); + + payload_size = chunk + head_size; + for (i = 0; i <= last_index - 1; i++) { + CONF_HEADER(payload, total_size, chunk, 0); + memcpy(&payload[head_size], ¶ms[i * chunk], + chunk * sizeof(int)); + crus_set_param(port, param_id, payload, + payload_size * sizeof(int)); + } + + /* send last chunk */ + payload_size = rest + head_size; + CONF_HEADER(payload, total_size, rest, 1 /*done*/); + memcpy(&payload[head_size], ¶ms[i * chunk], rest * sizeof(int)); + crus_set_param(port, param_id, payload, payload_size * sizeof(int)); + + return ret; +} + +#define DELTA_HEADER(buf, total_bytes, chunk_bytes, done, index) \ + do { \ + buf[0] = (total_bytes) * sizeof(int); \ + buf[1] = (chunk_bytes) * sizeof(int); \ + buf[2] = (done); \ + buf[3] = index; \ + buf[4] = 0; \ + buf[5] = 4; \ + } while (0) + +static int crus_send_delta(const char *data, uint32_t length) +{ + int i = 0, ret = 0, chunk = 90, head_size = 6; + int rest, last_index, total_size, payload_size; + int param_id = CRUS_PARAM_RX_SET_DELTA_CONFIG; + int *payload = this.apr_payload; + int *params = this.tuning; + int port = this.ff_port; + + memset(params, 0x00, TUNING_MAX_SIZE * sizeof(int)); + memset(payload, 0x00, APR_CHUNK_SIZE * sizeof(int)); + //firmware_request("delta0_raw_full.txt", &bytes, &size_byte); + if (tuning_parser(data, length, params, &total_size) < 0) + return -1; + if (crc_check(params, total_size) < 0) + return -1; + + rest = total_size % chunk; + if (rest == 0) { + last_index = total_size / chunk - 1; + rest = chunk; + } else { + last_index = total_size / chunk; + } + + pr_info("rest = %d, last_index=%d, total_size=%d\n", rest, last_index, + total_size); + + payload_size = chunk + head_size; + for (i = 0; i <= last_index - 1; i++) { + DELTA_HEADER(payload, total_size, chunk, 0, 0); + memcpy(&payload[head_size], ¶ms[i * chunk], + chunk * sizeof(int)); + crus_set_param(port, param_id, payload, + payload_size * sizeof(int)); + } + + /* send last chunk */ + payload_size = rest + head_size; + DELTA_HEADER(payload, total_size, rest, 1 /*done*/, 0); + memcpy(&payload[head_size], ¶ms[i * chunk], rest * sizeof(int)); + crus_set_param(port, param_id, payload, payload_size * sizeof(int)); + + return ret; +} + +static int crus_location_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int location = ucontrol->value.integer.value[0]; + + pr_info("%s: %d\n", __func__, location); + + switch (location) { + case CIRRUS_AFE: + case CIRRUS_COPP: + case CIRRUS_NONE: + this.location = location; + break; + default: + break; + } + + return 0; +} + +static int crus_location_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: this.location= %d", __func__, this.location); + ucontrol->value.integer.value[0] = this.location; + return 0; +} + +static int crus_rx_port_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + this.ff_port = ucontrol->value.integer.value[0]; + pr_info("%s: set rx port: %d\n", __func__, this.ff_port); + return 0; +} + +static int crus_rx_port_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this.ff_port; + return 0; +} +static int crus_tx_port_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + this.fb_port = ucontrol->value.integer.value[0]; + pr_info("%s: set tx port: %d\n", __func__, this.fb_port); + return 0; +} + +static int crus_tx_port_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this.fb_port; + return 0; +} + +static int crus_enable_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + this.sp_enable = ucontrol->value.integer.value[0]; + + crus_set_param(this.ff_port, CIRRUS_SP_ENABLE, (void *)&this.sp_enable, + sizeof(struct crus_single_data_t)); + + if (this.prot_en) + crus_set_param(this.fb_port, CIRRUS_SP_ENABLE, + (void *)&this.sp_enable, + sizeof(struct crus_single_data_t)); + + return 0; +} + +static int crus_enable_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this.sp_enable; + return 0; +} + +static int crus_prot_enable_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_err("Cirrus SP Protection Enable is set via DT\n"); + return 0; +} + +static int crus_prot_enable_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this.prot_en ? 1 : 0; + return 0; +} + +static int crus_usecase_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + const int index = ucontrol->value.integer.value[0]; + struct crus_rx_run_case_ctrl_t case_ctrl; + struct crus_rx_temperature_t rx_temp; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + + if (index >= e->items) { + pr_err("Config index out of bounds (%d)\n", index); + return -EINVAL; + } + + pr_info("%s: '%s' <-- '%s'\n", __func__, kcontrol->id.name, + e->texts[index]); + + this.usecase = index; + +#ifdef CACHE_COMMANDS + if (!this.cache_execute && + crus_cache_push(kcontrol, ucontrol, crus_usecase_put)) + return 0; +#endif + + crus_get_param(this.ff_port, CRUS_PARAM_RX_GET_TEMP, buffer, + CRUS_MAX_BUFFER_SIZE); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + case_ctrl.status_l = 1; + case_ctrl.status_r = 1; + case_ctrl.z_l = rx_temp.z_l; + case_ctrl.z_r = rx_temp.z_r; + case_ctrl.checksum_l = rx_temp.z_l + 1; + case_ctrl.checksum_r = rx_temp.z_r + 1; + case_ctrl.atemp = rx_temp.amb_temp_l; + case_ctrl.value = this.usecase; + + if (this.prot_en) { + crus_set_param(this.fb_port, CRUS_PARAM_TX_SET_USECASE, + (void *)&this.usecase, sizeof(this.usecase)); + } + + crus_set_param(this.ff_port, CRUS_PARAM_RX_SET_USECASE, + (void *)&case_ctrl, sizeof(case_ctrl)); + + return 0; +} + +static int crus_usecase_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_info("%s: %d\n", __func__, this.usecase); + ucontrol->value.integer.value[0] = this.usecase; + + return 0; +} +static int crus_load_rx_config_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct soc_enum *soc_enum = (struct soc_enum *)kcontrol->private_value; + unsigned int i = ucontrol->value.enumerated.item[0]; + const struct firmware *firmware; + + if (i >= soc_enum->items) { + pr_err("Invalid mixer input (%u)\n", i); + return -EINVAL; + } + + if (request_firmware(&firmware, soc_enum->texts[i], component->dev) != + 0) { + pr_err("Request firmware '%s' failed!\n", soc_enum->texts[i]); + this.delta_index = 0; + return -EINVAL; + } + + pr_info("Requestd:%s, value=%d\n", soc_enum->texts[i], + soc_enum->values[i]); + crus_send_config(firmware->data, firmware->size, this.ff_port); + this.conf_index = i; + + release_firmware(firmware); + + return 0; +} + +static int crus_load_rx_config_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: %d\n", __func__, this.conf_index); + ucontrol->value.integer.value[0] = this.conf_index; + return 0; +} + +static int crus_load_delta_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: %d\n", __func__, this.conf_index); + ucontrol->value.enumerated.item[0] = this.delta_index; + + return 0; +} + +static int crus_load_delta_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct soc_enum *soc_enum = (struct soc_enum *)kcontrol->private_value; + unsigned int i = ucontrol->value.enumerated.item[0]; + const struct firmware *firmware; + struct crus_single_data_t data; + + if (i >= soc_enum->items) { + pr_err("Invalid mixer input (%u)\n", i); + return -EINVAL; + } + + if (request_firmware(&firmware, soc_enum->texts[i], component->dev) != + 0) { + pr_err("Request firmware '%s' failed!\n", soc_enum->texts[i]); + this.delta_index = 0; + return -EINVAL; + } + + pr_info("Requestd: '%s'\n", soc_enum->texts[i]); + crus_send_delta(firmware->data, firmware->size); + + this.delta_index = i; + release_firmware(firmware); + + data.value = 0; + crus_set_param(this.ff_port, CRUS_PARAM_RX_RUN_DELTA_CONFIG, &data, + sizeof(struct crus_single_data_t)); + + return 0; +} +#if 0 +static int crus_vol_attn_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + const int crus_set = ucontrol->value.integer.value[0]; + struct crus_dual_data_t data; + + //mutex_lock(&this.sp_lock); + + this.vol_atten = crus_set; + + switch (crus_set) { + case 0: /* 0dB */ + data.data1 = VOL_ATTN_MAX; + data.data2 = VOL_ATTN_MAX; + break; + case 1: /* -18dB */ + data.data1 = VOL_ATTN_18DB; + data.data2 = VOL_ATTN_18DB; + break; + case 2: /* -24dB */ + data.data1 = VOL_ATTN_24DB; + data.data2 = VOL_ATTN_24DB; + break; + default: + return -EINVAL; + } + + crus_set_param(this.ff_port, CRUS_PARAM_RX_SET_ATTENUATION, &data, + sizeof(struct crus_dual_data_t)); + + //mutex_unlock(&this.sp_lock); + + return 0; +} + +static int crus_vol_attn_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("Starting Cirrus SP Volume Attenuation Get function call\n"); + ucontrol->value.integer.value[0] = this.vol_atten; + + return 0; +} +#endif + +static int crus_chan_swap_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct crus_dual_data_t data; + const int crus_set = ucontrol->value.integer.value[0]; + + switch (crus_set) { + case 0: /* L/R */ + data.data1 = 1; + break; + case 1: /* R/L */ + data.data1 = 2; + break; + default: + return -EINVAL; + } + + data.data2 = this.swap; + + crus_set_param(this.ff_port, CRUS_PARAM_RX_CHANNEL_SWAP, &data, + sizeof(struct crus_dual_data_t)); + + this.swap = !!crus_set; + + return 0; +} +static int crus_chan_swap_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct crus_single_data_t data; + pr_debug("%s: %d\n", __func__, this.swap); + crus_get_param(this.ff_port, CRUS_PARAM_RX_GET_CHANNEL_SWAP, &data, + sizeof(struct crus_single_data_t)); + + ucontrol->value.integer.value[0] = this.swap; + + return 0; +} + +static int crus_chan_swap_dur_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int crus_set = ucontrol->value.integer.value[0]; + + if ((crus_set < 0) || (crus_set > MAX_CHAN_SWAP_SAMPLES)) { + pr_err("Value out of range (%d)\n", crus_set); + return -EINVAL; + } + + if (crus_set < MIN_CHAN_SWAP_SAMPLES) { + pr_info("Received %d, round up to min value %d\n", crus_set, + MIN_CHAN_SWAP_SAMPLES); + crus_set = MIN_CHAN_SWAP_SAMPLES; + } + + this.swap_duration = crus_set; + + return 0; +} + +static int crus_chan_swap_dur_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: %d\n", __func__, this.swap_duration); + + ucontrol->value.integer.value[0] = this.swap_duration; + + return 0; +} +static int crus_fail_det_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + this.fail_det = ucontrol->value.integer.value[0]; + return 0; +} + +static int crus_fail_det_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this.fail_det; + return 0; +} + +static int crus_resistance_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct crus_single_data_t data; + const int crus_set = ucontrol->value.integer.value[0]; + + if (!this.prot_en) { + pr_err("CRUS_SP: Need feedback module to enable resistance calculation\n"); + return -EINVAL; + } + + switch (crus_set) { + case 0: /* Disable */ + this.resistance_en = false; + data.value = 0; + break; + case 1: /* Enable */ + this.resistance_en = true; + data.value = 1; + break; + default: + return -EINVAL; + } + + // crus_set_param(this.fb_port, CRUS_PARAM_TX_RESISTANCE, + // &data, sizeof(struct crus_single_data_t)); + + return 0; +} + +static int crus_resistance_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this.resistance_en ? 1 : 0; + return 0; +} + +static const char *const crus_en_text[] = { "Disable", "Enable" }; +static const char *const crus_prot_en_text[] = { "Disable", "Enable" }; +static const char *const crus_usecase_text[] = { "Music", "Game", "Handsfree", + "Movie" }; +static const char *const crus_conf_load_text[] = { "Idle", "Load RX", + "Load TX" }; +static const char *const crus_conf_load_no_prot_text[] = { "Idle", "Load" }; +static const char *const crus_chan_swap_text[] = { "LR", "RL" }; +static const char *const crus_resistance_text[] = { "Disable", "Enable" }; +static const char *const cirrus_location_text[] = { "NONE", "COPP", "AFE" }; + +static const struct soc_enum cirrus_location_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(cirrus_location_text), + cirrus_location_text), +}; +static struct soc_enum crus_usecase_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(crus_usecase_text), crus_usecase_text); +static const char *const crus_dt_text[] = { + "delta_0.txt", "delta_1.txt", "delta_2.txt", "delta_3.txt", + "delta_4.txt", "delta_5.txt", "delta_6.txt", "delta_7.txt", + "delta_8.txt", "delta_9.txt", "delta_10.txt", "delta_11.txt", + "delta_12.txt", "delta_13.txt", "delta_14.txt", "delta_15.txt", + "delta_16.txt", "delta_17.txt", "delta_18.txt", "delta_19.txt", + "delta_20.txt", "delta_21.txt", "delta_22.txt", "delta_23.txt", + "delta_24.txt", "delta_25.txt", "delta_26.txt", "delta_27.txt", + "delta_28.txt", "delta_29.txt", +}; + +static struct soc_enum crus_dt_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(crus_dt_text), crus_dt_text); +static const char *const crus_conf_text[] = { + "config_0.txt", "config_1.txt", "config_2.txt", "config_3.txt", + "config_4.txt", "config_5.txt", "config_6.txt", "config_7.txt", + "config_8.txt", "config_9.txt", "config_10.txt", "config_11.txt", + "config_12.txt", "config_13.txt", "config_14.txt", "config_15.txt", + "config_16.txt", "config_17.txt", "config_18.txt", "config_19.txt", + "config_20.txt", "config_21.txt", "config_22.txt", "config_23.txt", + "config_24.txt", "config_25.txt", "config_26.txt", "config_27.txt", + "config_28.txt", "config_29.txt", +}; + +static struct soc_enum crus_conf_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(crus_conf_text), crus_conf_text); + +static const struct snd_kcontrol_new crus_core_controls[] = { + SOC_SINGLE_EXT("Cirrus SP Rx Port", SND_SOC_NOPM, 0, 0x7FFFFFF, 0, + crus_rx_port_get, crus_rx_port_put), + SOC_SINGLE_EXT("Cirrus SP Tx Port", SND_SOC_NOPM, 0, 0x7FFFFFF, 0, + crus_tx_port_get, crus_tx_port_put), + SOC_ENUM_EXT("Cirrus SP Module", + (struct soc_enum)SOC_ENUM_SINGLE_EXT( + ARRAY_SIZE(crus_en_text), crus_en_text), + crus_enable_get, crus_enable_put), + SOC_ENUM_EXT("Cirrus SP Protection", + (struct soc_enum)SOC_ENUM_SINGLE_EXT( + ARRAY_SIZE(crus_prot_en_text), crus_prot_en_text), + crus_prot_enable_get, crus_prot_enable_put), + + SOC_ENUM_EXT("Cirrus SP Channel Swap", + (struct soc_enum)SOC_ENUM_SINGLE_EXT( + ARRAY_SIZE(crus_chan_swap_text), + crus_chan_swap_text), + crus_chan_swap_get, crus_chan_swap_put), + SOC_ENUM_EXT("Cirrus SP Usecase", crus_usecase_enum, crus_usecase_get, + crus_usecase_put), + SOC_SINGLE_EXT("Cirrus SP Channel Swap Duration", SND_SOC_NOPM, 0, + MAX_CHAN_SWAP_SAMPLES, 0, crus_chan_swap_dur_get, + crus_chan_swap_dur_put), + SOC_ENUM_EXT("Cirrus SP Resistance", + (struct soc_enum)SOC_ENUM_SINGLE_EXT( + ARRAY_SIZE(crus_resistance_text), + crus_resistance_text), + crus_resistance_get, crus_resistance_put), + SOC_ENUM_EXT("Cirrus SP Location", cirrus_location_enum[0], + crus_location_get, crus_location_put), + SOC_ENUM_EXT("Cirrus SP Delta", crus_dt_enum, crus_load_delta_get, + crus_load_delta_put), + SOC_ENUM_EXT("Cirrus SP Load Rx Config", crus_conf_enum, + crus_load_rx_config_get, crus_load_rx_config_put), +}; +static const struct snd_kcontrol_new crus_prot_controls[] = { + SOC_SINGLE_BOOL_EXT("Cirrus SP Failure Detection", 0, crus_fail_det_get, + crus_fail_det_put), +}; + +static const struct snd_kcontrol_new crus_no_prot_controls[] = {}; +#if 0 +static int crus_status_dump(int module_id, int param_id) +{ + int port; + int i = 0; + short *vmon0, *vmon1, *imon0, *imon1; + static int param_buf[1024] = { 0 }; + + switch (module_id) { + case CRUS_MODULE_ID_TX: + port = this.fb_port; + break; + case CRUS_MODULE_ID_RX: + port = this.ff_port; + break; + default: + pr_info("%s: Unrecognized port ID (%d)\n", __func__, + crus_sp_hdr.module_id); + port = this.ff_port; + break; + } + + memset(param_buf, 0x0, sizeof(param_buf)); + + crus_get_param(port, this.module, param_id, param_buf, 96*4); + vmon0 = (short *)&(param_buf[0]); + imon1 = (short *)&(param_buf[24]); + vmon1 = (short *)&(param_buf[24*2]); + imon0 = (short *)&(param_buf[24*3]); + + for(i = 0; i < 48; i ++) { + pr_info("%d, %d, %d, %d\n", vmon0[i], imon0[i], vmon1[i], imon1[i]); + } + + return 0; +} +#endif +void msm_crus_pb_set_copp_idx(int port_id, int copp_idx) +{ + if (port_id != this.ff_port) + return; + + pr_info("%s: port_id = 0x%x, copp_idx = %d\n", __func__, port_id, + copp_idx); + this.copp_idx = copp_idx; +} +EXPORT_SYMBOL(msm_crus_pb_set_copp_idx); + +void msm_crus_pb_add_controls(struct snd_soc_component *component) +{ + pr_err("Wing: %s: \n", __func__); + snd_soc_add_component_controls(component, crus_core_controls, + ARRAY_SIZE(crus_core_controls)); + pr_info("%s: end\n", __func__); +} + +EXPORT_SYMBOL(msm_crus_pb_add_controls); + +int crus_qdsp_port_start(u16 port_id, int copp_id) +{ + if (port_id != this.ff_port) + return 0; + + /* copp_id = -1 in AFE*/ + if (copp_id == INVALID_COPPID && this.location == CIRRUS_COPP) + return 0; + + atomic_inc(&this.qdsp_start_count[this.location]); + pr_info("%s:port_id = 0x%x, copp_id = %d, count = %d\n", __func__, + port_id, copp_id, this.qdsp_start_count[this.location]); + + if (this.location == CIRRUS_COPP) + this.copp_ids[copp_id] = copp_id; + +#ifdef CACHE_COMMANDS + crus_cache_pop_execute(); +#endif + return 0; +} +EXPORT_SYMBOL(crus_qdsp_port_start); + +int crus_qdsp_port_close(u16 port_id, int copp_id) +{ + if (port_id != this.ff_port) + return 0; + + /* copp_id = -1 in AFE*/ + if (copp_id == -1 && this.location == CIRRUS_COPP) + return 0; + + if (atomic_dec_return(&this.qdsp_start_count[this.location]) == 0) { + pr_info("%s: all stream on '0x%x' closed\n", __func__, port_id); + } + + pr_info("%s: port_id = 0x%x, copp_id = %d, count = %d\n", __func__, + port_id, copp_id, this.qdsp_start_count[this.location]); + + if (this.location == CIRRUS_COPP) { + this.copp_ids[copp_id] = INVALID_COPPID; + } + + return 0; +} +EXPORT_SYMBOL(crus_qdsp_port_close); + +static long crus_sp_shared_ioctl(struct file *f, unsigned int cmd, + void __user *arg) +{ + int result = 0, port, n; + uint32_t bufsize = 0, size; + void *io_data = NULL; + + pr_info("%s\n", __func__); + + if (copy_from_user(&size, arg, sizeof(size))) { + pr_err("%s: copy_from_user (size) failed\n", __func__); + result = -EFAULT; + goto exit; + } + + /* Copy IOCTL header from usermode */ + if (copy_from_user(&crus_sp_hdr, arg, size)) { + pr_err("%s: copy_from_user (struct) failed\n", __func__); + result = -EFAULT; + goto exit; + } + + switch (crus_sp_hdr.module_id) { + case CRUS_MODULE_ID_TX: + port = this.fb_port; + break; + case CRUS_MODULE_ID_RX: + port = this.ff_port; + break; + default: + pr_info("Unrecognized port ID (%d)\n", crus_sp_hdr.module_id); + port = this.ff_port; + } + + bufsize = crus_sp_hdr.data_length; + io_data = kzalloc(bufsize, GFP_KERNEL); + + switch (cmd) { + case CRUS_SP_IOCTL_GET: + crus_get_param(port, crus_sp_hdr.param_id, io_data, bufsize); + result = copy_to_user(crus_sp_hdr.data, io_data, bufsize); + if (result) { + pr_err("copy_to_user failed (%d)\n", result); + result = -EFAULT; + } else { + result = bufsize; + } + break; + case CRUS_SP_IOCTL_SET: + result = copy_from_user(io_data, (void *)crus_sp_hdr.data, + bufsize); + if (result) { + pr_err("copy_from_user failed (%d)\n", result); + result = -EFAULT; + goto exit_io; + } +#if 1 + for (n = 0; n < bufsize / sizeof(int); n++) { + pr_info("iodata[%d]=%d\n", n, ((int *)io_data)[n]); + } +#endif + crus_set_param(port, crus_sp_hdr.param_id, io_data, bufsize); + break; + default: + pr_err("Invalid IOCTL, command = %d\n", cmd); + result = -EINVAL; + break; + } + +exit_io: + kfree(io_data); +exit: + return result; +} + +static long crus_sp_ioctl(struct file *f, unsigned int cmd, unsigned long arg) +{ + pr_info("%s\n", __func__); + + return crus_sp_shared_ioctl(f, cmd, (void __user *)arg); +} + +static long crus_compat_ioctl(struct file *f, unsigned int cmd, + unsigned long arg) +{ + unsigned int cmd64; + + pr_info("%s\n", __func__); + + switch (cmd) { + case CRUS_SP_IOCTL_GET32: + cmd64 = CRUS_SP_IOCTL_GET; + break; + case CRUS_SP_IOCTL_SET32: + cmd64 = CRUS_SP_IOCTL_SET; + break; + default: + pr_err("%s: Invalid IOCTL, command = %d!\n", __func__, cmd); + return -EINVAL; + } + + return crus_sp_shared_ioctl(f, cmd64, compat_ptr(arg)); +} + +static int crus_ioctl_open(struct inode *inode, struct file *f) +{ + pr_debug("%s\n", __func__); + + atomic_inc(&this.ioctl_count); + return 0; +} + +static int crus_ioctl_release(struct inode *inode, struct file *f) +{ + atomic_dec(&this.ioctl_count); + + return 0; +} + +static ssize_t temperature_left_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int z, r, t, temp0; + + crus_get_param(this.ff_port, CRUS_PARAM_RX_GET_TEMP, buffer, + CRUS_MAX_BUFFER_SIZE); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + if ((rx_temp.hp_status_l != 2) || (rx_temp.full_status_l != 2)) + return snprintf(buf, PAGE_SIZE, "Calibration is not done\n"); + + z = rx_temp.z_l; + r = rx_temp.temp_l; + temp0 = rx_temp.amb_temp_l; + + t = (CRUS_MATERIAL_FACTOR * CRUS_T_SCALE_FACTOR * (r - z) / z) + + (temp0 * CRUS_T_SCALE_FACTOR); + + return snprintf(buf, PAGE_SIZE, "%d.%05dc\n", t / CRUS_T_SCALE_FACTOR, + t % CRUS_T_SCALE_FACTOR); +} + +static DEVICE_ATTR_RO(temperature_left); + +static ssize_t temperature_right_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int z, r, t, temp0; + + crus_get_param(this.ff_port, CRUS_PARAM_RX_GET_TEMP, buffer, + CRUS_MAX_BUFFER_SIZE); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + if ((rx_temp.hp_status_r != 2) || (rx_temp.full_status_r != 2)) + return snprintf(buf, PAGE_SIZE, "Calibration is not done\n"); + + z = rx_temp.z_r; + r = rx_temp.temp_r; + temp0 = rx_temp.amb_temp_r; + + t = (CRUS_MATERIAL_FACTOR * CRUS_T_SCALE_FACTOR * (r - z) / z) + + (temp0 * CRUS_T_SCALE_FACTOR); + + return snprintf(buf, PAGE_SIZE, "%d.%05dc\n", t / CRUS_T_SCALE_FACTOR, + t % CRUS_T_SCALE_FACTOR); +} +static DEVICE_ATTR_RO(temperature_right); +#if 0 +static ssize_t resistance_left_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + struct crus_resistance_t res; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int r; + + if (this.resistance_en) { + crus_get_param(this.fb_port, CRUS_PARAM_TX_RESISTANCE, &res, + sizeof(struct crus_resistance_t)); + + if (!res.status_l) + return snprintf(buf, PAGE_SIZE, + "Invalid status for left channel\n"); + + if (res.r_l == 0) + return snprintf(buf, PAGE_SIZE, + "Short circuit detected\n"); + + if (res.r_l >= CRUS_RES_OPEN_CIRCUIT) + return snprintf(buf, PAGE_SIZE, + "Open circuit detected\n"); + + r = res.r_l * CRUS_AMP_FACTOR; + } else { + crus_get_param(this.ff_port, CRUS_PARAM_RX_GET_TEMP, + buffer, CRUS_MAX_BUFFER_SIZE); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + if ((rx_temp.hp_status_l != 2) || (rx_temp.full_status_l != 2)) + return snprintf(buf, PAGE_SIZE, + "Calibration is not done\n"); + + r = rx_temp.temp_l * CRUS_AMP_FACTOR; + } + + return snprintf(buf, PAGE_SIZE, "%d.%08d ohms\n", + r / CRUS_Z_SCALE_FACTOR, r % CRUS_Z_SCALE_FACTOR); +} +static DEVICE_ATTR_RO(resistance_left); + +static ssize_t resistance_right_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + struct crus_resistance_t res; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int r; + + if (this.resistance_en) { + crus_get_param(this.fb_port, CRUS_PARAM_TX_RESISTANCE, &res, + sizeof(struct crus_resistance_t)); + + if (!res.status_r) + return snprintf(buf, PAGE_SIZE, + "Invalid status for right channel\n"); + + if (res.r_r == 0) + return snprintf(buf, PAGE_SIZE, + "Short circuit detected\n"); + + if (res.r_r >= CRUS_RES_OPEN_CIRCUIT) + return snprintf(buf, PAGE_SIZE, + "Open circuit detected\n"); + + r = res.r_r * CRUS_AMP_FACTOR; + } else { + crus_get_param(this.ff_port, CRUS_PARAM_RX_GET_TEMP, + buffer, CRUS_MAX_BUFFER_SIZE); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + if ((rx_temp.hp_status_r != 2) || (rx_temp.full_status_r != 2)) + return snprintf(buf, PAGE_SIZE, + "Calibration is not done\n"); + + r = rx_temp.temp_r * CRUS_AMP_FACTOR; + } + + return snprintf(buf, PAGE_SIZE, "%d.%08d ohms\n", + r / CRUS_Z_SCALE_FACTOR, r % CRUS_Z_SCALE_FACTOR); +} +static DEVICE_ATTR_RO(resistance_right); +#endif +static struct attribute *crus_sp_attrs[] = { + &dev_attr_temperature_left.attr, + &dev_attr_temperature_right.attr, +#if 0 + &dev_attr_resistance_left.attr, + &dev_attr_resistance_right.attr, +#endif + NULL, +}; + +static const struct attribute_group crus_sp_group = { + .attrs = crus_sp_attrs, +}; + +static const struct attribute_group *crus_sp_groups[] = { + &crus_sp_group, + NULL, +}; + +#ifdef CONFIG_OF +static int msm_cirrus_playback_probe(struct platform_device *pdev) +{ + int i; + + pr_err("Wing: Initializing platform device\n"); + + this.usecase_dt_count = + of_property_count_strings(pdev->dev.of_node, "usecase-names"); + if (this.usecase_dt_count <= 0) { + pr_debug("Usecase names not found\n"); + this.usecase_dt_count = 0; + return 0; + } + + if ((this.usecase_dt_count > 0) && + (this.usecase_dt_count <= MAX_TUNING_CONFIGS)) + of_property_read_string_array(pdev->dev.of_node, + "usecase-names", + crus_sp_usecase_dt_text, + this.usecase_dt_count); + else if (this.usecase_dt_count > MAX_TUNING_CONFIGS) { + pr_err("Max of %d usecase configs allowed\n", + MAX_TUNING_CONFIGS); + return -EINVAL; + } + + for (i = 0; i < this.usecase_dt_count; i++) + pr_info("Usecase[%d] = %s\n", i, crus_sp_usecase_dt_text[i]); + + this.prot_en = of_property_read_bool(pdev->dev.of_node, "protect-en"); + + return 0; +} + +static const struct of_device_id msm_cirrus_playback_dt_match[] = { + { .compatible = "cirrus,msm-cirrus-playback" }, + {} +}; +MODULE_DEVICE_TABLE(of, msm_cirrus_playback_dt_match); + +static struct platform_driver msm_cirrus_playback_driver = { + .driver = { + .name = "msm-cirrus-playback", + .owner = THIS_MODULE, + .of_match_table = msm_cirrus_playback_dt_match, + }, + .probe = msm_cirrus_playback_probe, +}; +#endif + +static const struct file_operations crus_sp_fops = { + .owner = THIS_MODULE, + .open = crus_ioctl_open, + .release = crus_ioctl_release, + .unlocked_ioctl = crus_sp_ioctl, + .compat_ioctl = crus_compat_ioctl, +}; + +struct miscdevice crus_sp_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = "msm_cirrus_playback", + .fops = &crus_sp_fops, +}; + +int __init crus_sp_init(void) +{ + if (this.initialized) + return 0; + pr_info("Initializing misc device\n"); + + misc_register(&crus_sp_misc); + + if (sysfs_create_groups(&crus_sp_misc.this_device->kobj, + crus_sp_groups)) + pr_err("%s: Could not create sysfs groups\n", __func__); + +#ifdef CONFIG_OF + platform_driver_register(&msm_cirrus_playback_driver); +#endif + + this.initialized = true; + pr_info("Initializing misc device end\n"); + return 0; +} + +void __exit crus_sp_exit(void) +{ + if (!this.initialized) + return; + +#ifdef CONFIG_OF + platform_driver_unregister(&msm_cirrus_playback_driver); +#endif + sysfs_remove_groups(&crus_sp_misc.this_device->kobj, crus_sp_groups); + + misc_deregister(&crus_sp_misc); +} + +//MODULE_AUTHOR("Cirrus SP"); +//MODULE_DESCRIPTION("Providing Interface to Cirrus SP"); +//MODULE_LICENSE("GPL"); diff --git a/techpack/audio/dsp/msm-cirrus-playback.c b/techpack/audio/dsp/msm-cirrus-playback.c new file mode 100644 index 000000000000..6855ad1b7b6d --- /dev/null +++ b/techpack/audio/dsp/msm-cirrus-playback.c @@ -0,0 +1,1550 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2019 XiaoMi, Inc. +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +/* includes the file structure, that is, file open read close */ +#include + +/* include the character device, makes cdev avilable */ +#include +#include + +/* includes copy_user vice versa */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "../asoc/msm-pcm-routing-v2.h" +#include +#include +#include +#include +#include + +#undef CONFIG_OF + +#undef pr_info +#undef pr_err +#undef pr_debug +#define pr_debug(fmt, args...) printk(KERN_INFO "[CSPL] " pr_fmt(fmt), ##args) +#define pr_info(fmt, args...) printk(KERN_INFO "[CSPL] " pr_fmt(fmt), ##args) +#define pr_err(fmt, args...) printk(KERN_ERR "[CSPL] " pr_fmt(fmt), ##args) + +#define CRUS_TX_CONFIG "crus_sp_tx%d.bin" +#define CRUS_RX_CONFIG "crus_sp_rx%d.bin" + +#define CIRRUS_RX_GET_IODATA 0x00A1AF09 +#define CIRRUS_TX_GET_IODATA 0x00A1BF09 + +static struct crus_sp_ioctl_header crus_sp_hdr; + +static struct crus_control_t this_ctrl = { + .fb_port_index = 3, + .fb_port = AFE_PORT_ID_QUATERNARY_MI2S_TX, + .ff_port = AFE_PORT_ID_QUATERNARY_MI2S_RX, + .usecase_dt_count = MAX_TUNING_CONFIGS, + .ch_sw_duration = 30, + .ch_sw = 0, + .vol_atten = 0, + .prot_en = false, + .q6afe_rev = 3, // V3 as default +}; + +static void *crus_gen_afe_get_header(int length, int port, int module, + int param) +{ + struct afe_custom_crus_get_config_v2_t *config = NULL; + int size = sizeof(struct afe_custom_crus_get_config_v2_t); + int index = afe_get_port_index(port); + uint16_t payload_size = sizeof(struct param_hdr_v2) + length; + + /* Allocate memory for the message */ + config = kzalloc(size, GFP_KERNEL); + if (!config) + return NULL; + + /* Set header section */ + config->hdr.hdr_field = APR_HDR_FIELD( + APR_MSG_TYPE_SEQ_CMD, APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + config->hdr.pkt_size = size; + config->hdr.src_svc = APR_SVC_AFE; + config->hdr.src_domain = APR_DOMAIN_APPS; + config->hdr.src_port = 0; + config->hdr.dest_svc = APR_SVC_AFE; + config->hdr.dest_domain = APR_DOMAIN_ADSP; + config->hdr.dest_port = 0; + config->hdr.token = index; + config->hdr.opcode = AFE_PORT_CMD_GET_PARAM_V2; + + /* Set param section */ + config->param.port_id = (uint16_t)port; + + config->param.mem_hdr.data_payload_addr_lsw = 0; + config->param.mem_hdr.data_payload_addr_msw = 0; + config->param.mem_hdr.mem_map_handle = 0; + config->param.module_id = (uint32_t)module; + config->param.param_id = (uint32_t)param; + /* max data size of the param_ID/module_ID combination */ + config->param.payload_size = payload_size; + + /* Set data section */ + config->data.module_id = (uint32_t)module; + config->data.param_id = (uint32_t)param; + + /*remove for 855*/ + //config->data.reserved = 0; /* Must be set to 0 */ + /* actual size of the data for the module_ID/param_ID pair */ + config->data.param_size = length; + + return (void *)config; +} + +static void *crus_gen_afe_set_header(int length, int port, int module, + int param) +{ + struct afe_custom_crus_set_config_v2_t *config = NULL; + int size = sizeof(struct afe_custom_crus_set_config_v2_t) + length; + int index = afe_get_port_index(port); + uint16_t payload_size = sizeof(struct param_hdr_v2) + length; + + /* Allocate memory for the message */ + config = kzalloc(size, GFP_KERNEL); + if (!config) + return NULL; + + /* Set header section */ + config->hdr.hdr_field = APR_HDR_FIELD( + APR_MSG_TYPE_SEQ_CMD, APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + config->hdr.pkt_size = size; + config->hdr.src_svc = APR_SVC_AFE; + config->hdr.src_domain = APR_DOMAIN_APPS; + config->hdr.src_port = 0; + config->hdr.dest_svc = APR_SVC_AFE; + config->hdr.dest_domain = APR_DOMAIN_ADSP; + config->hdr.dest_port = 0; + config->hdr.token = index; + config->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; + + /* Set param section */ + config->param.port_id = (uint16_t)port; + config->param.mem_hdr.data_payload_addr_lsw = 0; + config->param.mem_hdr.data_payload_addr_msw = 0; + config->param.mem_hdr.mem_map_handle = 0; + /* max data size of the param_ID/module_ID combination */ + config->param.payload_size = payload_size; + + /* Set data section */ + config->data.module_id = (uint32_t)module; + config->data.param_id = (uint32_t)param; + + /*remove for 855*/ + //config->data.reserved = 0; /* Must be set to 0 */ + + /* actual size of the data for the module_ID/param_ID pair */ + config->data.param_size = length; + + return (void *)config; +} + +static int crus_afe_get_param(int port, int module, int param, int length, + void *data) +{ + struct afe_custom_crus_get_config_v2_t *config = NULL; + int index = afe_get_port_index(port); + int ret = 0, count = 0; + + pr_info("CRUS_SP: (get_param) module = 0x%08x, port = 0x%08x, param = 0x%08x\n", + module, port, param); + + config = (struct afe_custom_crus_get_config_v2_t *) + crus_gen_afe_get_header(length, port, module, param); + if (config == NULL) { + pr_err("CRUS_SP: Memory allocation failed\n"); + return -ENOMEM; + } + + mutex_lock(&this_ctrl.param_lock); + atomic_set(&this_ctrl.callback_wait, 0); + + this_ctrl.user_buffer = + kzalloc(config->param.payload_size + 16, GFP_KERNEL); + + ret = afe_apr_send_pkt_crus(config, index, 0); + if (ret) + pr_err("CRUS_SP: (get_param) failed with code %d\n", ret); + + /* Wait for afe callback to populate data */ + while (!atomic_read(&this_ctrl.callback_wait)) { + usleep_range(800, 1200); + if (count++ >= 1000) { + pr_err("CRUS_SP: AFE callback timeout\n"); + atomic_set(&this_ctrl.callback_wait, 1); + ret = -EINVAL; + goto exit; + } + } + + /* Copy from dynamic buffer to return buffer */ + memcpy((u8 *)data, &this_ctrl.user_buffer[4], length); + +exit: + kfree(this_ctrl.user_buffer); + mutex_unlock(&this_ctrl.param_lock); + kfree(config); + return ret; +} + +static int crus_afe_set_param(int port, int module, int param, int length, + void *data_ptr) +{ + struct afe_custom_crus_set_config_v2_t *config = NULL; + int index = afe_get_port_index(port); + int ret = 0; + + pr_info("CRUS_SP: (set_param) module = 0x%08x, port = 0x%08x, param = 0x%08x\n", + module, port, param); + + config = crus_gen_afe_set_header(length, port, module, param); + if (config == NULL) { + pr_err("CRUS_SP: Memory allocation failed\n"); + return -ENOMEM; + } + + memcpy((u8 *)config + sizeof(struct afe_custom_crus_set_config_v2_t), + (u8 *)data_ptr, length); + + ret = afe_apr_send_pkt_crus(config, index, 1); + if (ret) + pr_err("CRUS_SP: (set_param) failed with code %d\n", ret); + + kfree(config); + return ret; +} + +static int crus_afe_get_param_v3(int port, int module_id, int param_id, + uint32_t length, void *data) +{ + struct afe_port_cmd_get_param_v3 afe_get_param; + struct param_hdr_v3 param_hdr; + u16 port_id = 0; + int index = 0; + int ret = 0; + + pr_info("%s: port=0x%x, module=0x%x, param_id=0x%x, size=%d\n", + __func__, port, module_id, param_id, length); + + param_hdr.module_id = module_id; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = length; + + port_id = q6audio_get_port_id(port); + ret = q6audio_validate_port(port_id); + if (ret < 0) { + pr_err("%s: Not a valid port id = 0x%x ret %d\n", __func__, + port_id, ret); + return -EINVAL; + } + index = q6audio_get_port_index(port); + + //q6afe_get_params_v3 + memset(&afe_get_param, 0, sizeof(afe_get_param)); + afe_get_param.apr_hdr.hdr_field = APR_HDR_FIELD( + APR_MSG_TYPE_SEQ_CMD, APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + afe_get_param.apr_hdr.pkt_size = sizeof(afe_get_param); + afe_get_param.apr_hdr.src_port = 0; + afe_get_param.apr_hdr.dest_port = 0; + afe_get_param.apr_hdr.token = index; + afe_get_param.apr_hdr.opcode = AFE_PORT_CMD_GET_PARAM_V3; + afe_get_param.port_id = port_id; + //if (mem_hdr != NULL) + // afe_get_param.mem_hdr = *mem_hdr; + /* Set param header in command, no payload in V3 */ + afe_get_param.param_hdr = param_hdr; + //q6afe_get_params_v3 end + + mutex_lock(&this_ctrl.param_lock); + atomic_set(&this_ctrl.callback_wait, 0); + this_ctrl.user_buffer = kzalloc(length + 64, GFP_KERNEL); + atomic_set(cspl_afe.status, 0); + ret = apr_send_pkt(*cspl_afe.apr, (uint32_t *)&afe_get_param); + if (ret < 0) { + pr_err("%s: Setting param for port %d param[0x%x]failed\n", + __func__, port, param_id); + goto fail_cmd; + } + /* Wait for afe callback to populate data */ + while (!atomic_read(&this_ctrl.callback_wait)) + msleep(1); + +#if 0 + for (index = 0; index < length; index ++) + pr_info("[%d]=%d\n", index, this_ctrl.user_buffer[index]); + + pr_info("[5]=%s\n", &this_ctrl.user_buffer[5]); +#endif + /* copy from dynamic buffer to return buffer */ + memcpy((u8 *)data, &this_ctrl.user_buffer[5], length); + pr_info("%s: Copied %d bytes data \n", __func__, length); + + ret = 0; +fail_cmd: + pr_info("%s: param_id %x status %d\n", __func__, param_id, ret); + mutex_unlock(&this_ctrl.param_lock); + kfree(this_ctrl.user_buffer); + return ret; +} + +static int crus_afe_set_param_v3(int port, int module_id, int param_id, + uint32_t length, void *data) +{ + struct afe_port_cmd_set_param_v3 *set_param = NULL; + uint32_t set_param_size = sizeof(struct afe_port_cmd_set_param_v3); + struct param_hdr_v3 param_hdr; + u16 port_id = 0; + int index = 0; + u8 *packed_param_data = NULL; + int packed_data_size = sizeof(union param_hdrs) + length; + int ret = 0; + + pr_info("%s: port=0x%x, module=0x%x, param_id=0x%x, size=%d\n", + __func__, port, module_id, param_id, length); + + port_id = q6audio_get_port_id(port); + ret = q6audio_validate_port(port_id); + if (ret < 0) { + pr_err("%s: Not a valid port id = 0x%x ret %d\n", __func__, + port_id, ret); + return -EINVAL; + } + index = q6audio_get_port_index(port); + + memset(¶m_hdr, 0, sizeof(param_hdr)); + param_hdr.module_id = module_id; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = length; + pr_debug("CRUS: param_size %d\n", length); + + packed_param_data = kzalloc(packed_data_size, GFP_KERNEL); + if (packed_param_data == NULL) + return -ENOMEM; + + ret = q6common_pack_pp_params(packed_param_data, ¶m_hdr, (u8 *)data, + &packed_data_size); + if (ret) { + pr_err("%s: Failed to pack param header and data, error %d\n", + __func__, ret); + goto fail_cmd; + } + + set_param_size += packed_data_size; + set_param = kzalloc(set_param_size, GFP_KERNEL); + if (set_param == NULL) { + ret = -ENOMEM; + goto fail_cmd; + } + + set_param->apr_hdr.hdr_field = APR_HDR_FIELD( + APR_MSG_TYPE_SEQ_CMD, APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + set_param->apr_hdr.pkt_size = + sizeof(struct afe_port_cmd_set_param_v3) + packed_data_size; + set_param->apr_hdr.src_port = 0; + set_param->apr_hdr.dest_port = 0; + set_param->apr_hdr.token = index; + set_param->apr_hdr.opcode = AFE_PORT_CMD_SET_PARAM_V3; + set_param->port_id = port_id; + set_param->payload_size = packed_data_size; + memcpy(&set_param->param_data, packed_param_data, packed_data_size); + + atomic_set(cspl_afe.state, 1); + //atomic_set(&this_ctrl.callback_wait, 0); + ret = apr_send_pkt(*cspl_afe.apr, (uint32_t *)set_param); + if (ret < 0) { + pr_err("%s: Setting param for port %d param[0x%x]failed\n", + __func__, port, param_id); + goto fail_cmd; + } + + ret = wait_event_timeout(cspl_afe.wait[index], + (atomic_read(cspl_afe.state) == 0), + msecs_to_jiffies(cspl_afe.timeout_ms * 10)); + + if (!ret) { + pr_err("%s: wait_event timeout\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + + if (atomic_read(cspl_afe.status) != 0) { + pr_err("%s: set param cmd failed\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + + ret = 0; +fail_cmd: + pr_info("[CSPL]%s param_id %x status %d\n", __func__, param_id, ret); + kfree(set_param); + kfree(packed_param_data); + return ret; +} + +static int crus_afe_send_config(const char *data, int32_t length, int32_t port, + int32_t module) +{ + struct afe_custom_crus_set_config_v2_t *config = NULL; + struct crus_external_config_t *payload = NULL; + int size = sizeof(struct crus_external_config_t); + int chars_to_send, mem_size, sent = 0, ret = 0; + int index = afe_get_port_index(port); + uint32_t param = 0; + + pr_info("CRUS_SP: (send_config) module = 0x%08x, port = 0x%08x\n", + module, port); + + /* Destination settings for message */ + if (port == this_ctrl.ff_port) + param = CRUS_PARAM_RX_SET_EXT_CONFIG; + else if (port == this_ctrl.fb_port) + param = CRUS_PARAM_TX_SET_EXT_CONFIG; + else { + pr_err("CRUS_SP: Received invalid port parameter %d\n", port); + return -EINVAL; + } + + if (length > APR_CHUNK_SIZE) + mem_size = APR_CHUNK_SIZE; + else + mem_size = length; + + config = crus_gen_afe_set_header(size, port, module, param); + if (config == NULL) { + pr_err("CRUS_SP: Memory allocation failed\n"); + return -ENOMEM; + } + + payload = (struct crus_external_config_t + *)((u8 *)config + + sizeof(struct afe_custom_crus_set_config_v2_t)); + payload->total_size = (uint32_t)length; + payload->reserved = 0; + payload->config = PAYLOAD_FOLLOWS_CONFIG; + /* ^ This tells the algorithm to expect array */ + /* immediately following the header */ + + /* Send config string in chunks of APR_CHUNK_SIZE bytes */ + while (sent < length) { + chars_to_send = length - sent; + if (chars_to_send > APR_CHUNK_SIZE) { + chars_to_send = APR_CHUNK_SIZE; + payload->done = 0; + } else { + payload->done = 1; + } + + /* Configure per message parameter settings */ + memcpy(payload->data, data + sent, chars_to_send); + payload->chunk_size = chars_to_send; + + /* Send the actual message */ + ret = afe_apr_send_pkt_crus(config, index, 1); + + if (ret) { + pr_err("CRUS_SP: (send_config) failure code %d\n", ret); + break; + } + + sent += chars_to_send; + } + + kfree(config); + return ret; +} + +static int crus_afe_send_delta(const char *data, uint32_t length) +{ + struct afe_custom_crus_set_config_t *config = NULL; + struct crus_delta_config_t *payload = NULL; + int size = sizeof(struct crus_delta_config_t); + int port = this_ctrl.ff_port; + int param = CRUS_PARAM_RX_SET_DELTA_CONFIG; + int module = CIRRUS_SP; + int chars_to_send, mem_size, sent = 0, ret = 0; + int index = afe_get_port_index(port); + + pr_info("CRUS_SP: (send_delta) module = 0x%08x, port = 0x%08x\n", + module, port); + + if (length > APR_CHUNK_SIZE) + mem_size = APR_CHUNK_SIZE; + else + mem_size = length; + + config = crus_gen_afe_set_header(size, port, module, param); + if (config == NULL) { + pr_err("CRUS_SP: Memory allocation failed\n"); + return -ENOMEM; + } + + payload = (struct crus_delta_config_t + *)((u8 *)config + + sizeof(struct afe_custom_crus_set_config_t)); + payload->total_size = length; + payload->index = 0; + payload->reserved = 0; + payload->config = PAYLOAD_FOLLOWS_CONFIG; + /* ^ This tells the algorithm to expect array */ + /* immediately following the header */ + + /* Send config string in chunks of APR_CHUNK_SIZE bytes */ + while (sent < length) { + chars_to_send = length - sent; + if (chars_to_send > APR_CHUNK_SIZE) { + chars_to_send = APR_CHUNK_SIZE; + payload->done = 0; + } else + payload->done = 1; + + /* Configure per message parameter settings */ + memcpy(payload->data, data + sent, chars_to_send); + payload->chunk_size = chars_to_send; + + /* Send the actual message */ + ret = afe_apr_send_pkt_crus(config, index, 1); + + if (ret) { + pr_err("CRUS_SP: (send_delta) failure code %d\n", ret); + break; + } + + sent += chars_to_send; + } + + kfree(config); + return ret; +} + +extern int crus_afe_callback(void *payload, int size) +{ + uint32_t *payload32 = payload; + + pr_debug("%s: module=0x%x size = %d\n", __func__, (int)payload32[1], + size); + + switch (payload32[1]) { + case CIRRUS_SP: + memcpy(this_ctrl.user_buffer, payload32, size); + atomic_set(&this_ctrl.callback_wait, 1); + break; + default: + return -EINVAL; + } + + return 0; +} + +int msm_routing_cirrus_fbport_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + this_ctrl.fb_port_index = ucontrol->value.integer.value[0]; + pr_info("%s: %d\n", __func__, this_ctrl.fb_port); + + switch (this_ctrl.fb_port_index) { + case 0: + this_ctrl.fb_port = AFE_PORT_ID_PRIMARY_MI2S_TX; + this_ctrl.ff_port = AFE_PORT_ID_PRIMARY_MI2S_RX; + break; + case 1: + this_ctrl.fb_port = AFE_PORT_ID_SECONDARY_MI2S_TX; + this_ctrl.ff_port = AFE_PORT_ID_SECONDARY_MI2S_RX; + break; + case 2: + this_ctrl.fb_port = AFE_PORT_ID_TERTIARY_MI2S_TX; + this_ctrl.ff_port = AFE_PORT_ID_TERTIARY_MI2S_RX; + break; + case 3: + this_ctrl.fb_port = AFE_PORT_ID_QUATERNARY_MI2S_TX; + this_ctrl.ff_port = AFE_PORT_ID_QUATERNARY_MI2S_RX; + break; + default: + /* Default port to QUATERNARY */ + this_ctrl.fb_port = AFE_PORT_ID_QUATERNARY_MI2S_TX; + this_ctrl.ff_port = AFE_PORT_ID_QUATERNARY_MI2S_RX; + break; + } + return 0; +} + +int msm_routing_cirrus_fbport_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: this_ctrl.fb_port = %d", __func__, this_ctrl.fb_port); + ucontrol->value.integer.value[0] = this_ctrl.fb_port_index; + return 0; +} + +static int msm_routing_crus_sp_enable_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + const int crus_set = ucontrol->value.integer.value[0]; + + this_ctrl.enable = crus_set; + + return 0; +} + +static int msm_routing_crus_sp_enable_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_info("%s: %d\n", __func__, this_ctrl.enable); + ucontrol->value.integer.value[0] = this_ctrl.enable; + + return 0; +} +static int +msm_routing_crus_sp_prot_enable_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_err("CRUS_SP: Cirrus SP Protection Enable is set via DT\n"); + return 0; +} + +static int +msm_routing_crus_sp_prot_enable_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this_ctrl.prot_en ? 1 : 0; + return 0; +} + +static int msm_routing_crus_sp_usecase_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct crus_rx_run_case_ctrl_t case_ctrl; + struct crus_rx_temperature_t rx_temp; + const int crus_set = ucontrol->value.integer.value[0]; + //struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + //uint32_t max_index = e->items; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + + if (crus_set >= 4) { + pr_err("CRUS_SP: Config index out of bounds (%d)\n", crus_set); + return -EINVAL; + } + + if (this_ctrl.q6afe_rev == 2) + crus_afe_get_param(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_GET_TEMP, CRUS_MAX_BUFFER_SIZE, + buffer); + else + crus_afe_get_param_v3(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_GET_TEMP, + CRUS_MAX_BUFFER_SIZE, buffer); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + this_ctrl.usecase = crus_set; + + case_ctrl.status_l = 1; + case_ctrl.status_r = 1; + case_ctrl.z_l = rx_temp.z_l; + case_ctrl.z_r = rx_temp.z_r; + case_ctrl.checksum_l = rx_temp.z_l + 1; + case_ctrl.checksum_r = rx_temp.z_r + 1; + case_ctrl.atemp = rx_temp.amb_temp_l; + case_ctrl.value = this_ctrl.usecase; + + if (this_ctrl.prot_en) { + if (this_ctrl.q6afe_rev == 2) { + crus_afe_set_param(this_ctrl.fb_port, CIRRUS_SP, + CRUS_PARAM_TX_SET_USECASE, + sizeof(this_ctrl.usecase), + (void *)&this_ctrl.usecase); + } else { + crus_afe_set_param_v3(this_ctrl.fb_port, CIRRUS_SP, + CRUS_PARAM_TX_SET_USECASE, + sizeof(this_ctrl.usecase), + (void *)&this_ctrl.usecase); + } + } + + if (this_ctrl.q6afe_rev == 2) { + crus_afe_set_param(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_SET_USECASE, sizeof(case_ctrl), + (void *)&case_ctrl); + } else { + crus_afe_set_param_v3(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_SET_USECASE, + sizeof(case_ctrl), (void *)&case_ctrl); + } + + return 0; +} + +static int msm_routing_crus_sp_usecase_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_info("%s: %d\n", __func__, this_ctrl.usecase); + ucontrol->value.integer.value[0] = this_ctrl.usecase; + + return 0; +} + +static int msm_routing_crus_load_config_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_platform *plat = snd_soc_kcontrol_platform(kcontrol); + const int crus_set = ucontrol->value.integer.value[0]; + char config[CONFIG_FILE_SIZE]; + const struct firmware *firmware; + + pr_debug("%s: %d\n", __func__, crus_set); + this_ctrl.conf_sel = crus_set; + + switch (crus_set) { + case 0: /* "None" */ + break; + case 1: /* Load RX Config */ + snprintf(config, CONFIG_FILE_SIZE, CRUS_RX_CONFIG, + this_ctrl.usecase); + + if (request_firmware(&firmware, config, plat->dev) != 0) { + pr_err("CRUS_SP: Request firmware failed\n"); + return -EINVAL; + } + + pr_info("CRUS_SP: Sending RX config...\n"); + + crus_afe_send_config(firmware->data, firmware->size, + this_ctrl.ff_port, CIRRUS_SP); + release_firmware(firmware); + break; + case 2: /* Load TX Config */ + if (this_ctrl.prot_en == false) + return -EINVAL; + + snprintf(config, CONFIG_FILE_SIZE, CRUS_TX_CONFIG, + this_ctrl.usecase); + + if (request_firmware(&firmware, config, plat->dev) != 0) { + pr_err("CRUS_SP: Request firmware failed\n"); + return -EINVAL; + } + + pr_info("CRUS_SP: Sending TX config...\n"); + + crus_afe_send_config(firmware->data, firmware->size, + this_ctrl.fb_port, CIRRUS_SP); + release_firmware(firmware); + break; + default: + return -EINVAL; + } + + this_ctrl.conf_sel = 0; + + return 0; +} + +static int msm_routing_crus_load_config_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: %d\n", __func__, this_ctrl.conf_sel); + ucontrol->value.integer.value[0] = this_ctrl.conf_sel; + return 0; +} + +static int +msm_routing_crus_delta_config_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_platform *plat = snd_soc_kcontrol_platform(kcontrol); + struct crus_single_data_t data; + const int crus_set = ucontrol->value.integer.value[0]; + const struct firmware *firmware; + + switch (crus_set) { + case 0: + break; + case 1: /* Load delta config over AFE */ + this_ctrl.delta_sel = crus_set; + + if (request_firmware(&firmware, "crus_sp_delta_config.bin", + plat->dev) != 0) { + pr_err("CRUS_SP: Request firmware failed\n"); + this_ctrl.delta_sel = 0; + return -EINVAL; + } + + pr_info("CRUS_SP: Sending delta config...\n"); + + crus_afe_send_delta(firmware->data, firmware->size); + release_firmware(firmware); + break; + case 2: /* Run delta transition */ + this_ctrl.delta_sel = crus_set; + data.value = 0; + crus_afe_set_param(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_RUN_DELTA_CONFIG, + sizeof(struct crus_single_data_t), &data); + break; + default: + return -EINVAL; + } + + this_ctrl.delta_sel = 0; + return 0; +} + +static int +msm_routing_crus_delta_config_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = this_ctrl.delta_sel; + return 0; +} + +static int msm_routing_crus_vol_attn_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + const int crus_set = ucontrol->value.integer.value[0]; + struct crus_dual_data_t data; + + mutex_lock(&this_ctrl.sp_lock); + + this_ctrl.vol_atten = crus_set; + + switch (crus_set) { + case 0: /* 0dB */ + data.data1 = VOL_ATTN_MAX; + data.data2 = VOL_ATTN_MAX; + break; + case 1: /* -18dB */ + data.data1 = VOL_ATTN_18DB; + data.data2 = VOL_ATTN_18DB; + break; + case 2: /* -24dB */ + data.data1 = VOL_ATTN_24DB; + data.data2 = VOL_ATTN_24DB; + break; + default: + return -EINVAL; + } + + if (this_ctrl.q6afe_rev == 2) { + crus_afe_set_param(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_SET_ATTENUATION, + sizeof(struct crus_dual_data_t), &data); + } else { + crus_afe_set_param_v3(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_SET_ATTENUATION, + sizeof(struct crus_dual_data_t), &data); + } + + mutex_unlock(&this_ctrl.sp_lock); + + return 0; +} + +static int msm_routing_crus_vol_attn_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("Starting Cirrus SP Volume Attenuation Get function call\n"); + ucontrol->value.integer.value[0] = this_ctrl.vol_atten; + + return 0; +} + +static int msm_routing_crus_chan_swap_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct crus_dual_data_t data; + const int crus_set = ucontrol->value.integer.value[0]; + + switch (crus_set) { + case 0: /* L/R */ + data.data1 = 1; + break; + case 1: /* R/L */ + data.data1 = 2; + break; + default: + return -EINVAL; + } + + data.data2 = this_ctrl.ch_sw_duration; + + mutex_lock(&this_ctrl.sp_lock); + + this_ctrl.ch_sw = crus_set; + + if (this_ctrl.q6afe_rev == 2) + crus_afe_set_param(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_CHANNEL_SWAP, + sizeof(struct crus_dual_data_t), &data); + else + crus_afe_set_param_v3(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_CHANNEL_SWAP, + sizeof(struct crus_dual_data_t), &data); + + mutex_unlock(&this_ctrl.sp_lock); + + return 0; +} + +static int msm_routing_crus_chan_swap_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct crus_single_data_t data; + pr_debug("%s: %d\n", __func__, this_ctrl.ch_sw); + crus_afe_get_param(this_ctrl.ff_port, CIRRUS_SP, + CRUS_PARAM_RX_GET_CHANNEL_SWAP, + sizeof(struct crus_single_data_t), &data); + + ucontrol->value.integer.value[0] = this_ctrl.ch_sw; + + return 0; +} + +static int +msm_routing_crus_chan_swap_dur_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int crus_set = ucontrol->value.integer.value[0]; + + pr_debug("%s: %d\n", __func__, crus_set); + + if ((crus_set < 0) || (crus_set > MAX_CHAN_SWAP_SAMPLES)) { + pr_err("CRUS_SP: Value out of range (%d)\n", crus_set); + return -EINVAL; + } + + if (crus_set < MIN_CHAN_SWAP_SAMPLES) { + pr_info("CRUS_SP: Received %d, round up to min value %d\n", + crus_set, MIN_CHAN_SWAP_SAMPLES); + crus_set = MIN_CHAN_SWAP_SAMPLES; + } + + this_ctrl.ch_sw_duration = crus_set; + + return 0; +} + +static int +msm_routing_crus_chan_swap_dur_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: %d\n", __func__, this_ctrl.ch_sw_duration); + + ucontrol->value.integer.value[0] = this_ctrl.ch_sw_duration; + + return 0; +} +static int msm_routing_crus_fail_det(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +static int msm_routing_crus_fail_det_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +static const char *const cirrus_fb_port_text[] = { + "PRI_MI2S_RX", "SEC_MI2S_RX", "TERT_MI2S_RX", + "QUAT_MI2S_RX", "QUAT_TDM_RX_0", "SLIMBUS_0_RX" +}; + +static const char *const crus_en_text[] = { "Config SP Disable", + "Config SP Enable" }; + +static const char *const crus_prot_en_text[] = { "Disable", "Enable" }; + +static const char *const crus_conf_load_text[] = { "Idle", "Load RX", + "Load TX" }; + +static const char *const crus_conf_load_no_prot_text[] = { "Idle", "Load" }; + +static const char *const crus_delta_text[] = { "Idle", "Load", "Run" }; + +static const char *const crus_chan_swap_text[] = { "LR", "RL" }; +static const char *crus_sp_usecase_dt_text[MAX_TUNING_CONFIGS] = { + "Music", "Voice", "Headset", "Handsfree" +}; + +static const char *const crus_vol_attn_text[] = { "0dB", "-18dB", "-24dB" }; + +static const struct soc_enum cirrus_fb_controls_enum[] = { + SOC_ENUM_SINGLE_EXT(6, cirrus_fb_port_text), +}; + +static const struct soc_enum crus_en_enum[] = { + SOC_ENUM_SINGLE_EXT(2, crus_en_text), +}; + +static const struct soc_enum crus_prot_en_enum[] = { + SOC_ENUM_SINGLE_EXT(2, crus_prot_en_text), +}; + +static struct soc_enum crus_sp_usecase_enum[] = { + SOC_ENUM_SINGLE_EXT(MAX_TUNING_CONFIGS, crus_sp_usecase_dt_text), +}; + +static const struct soc_enum crus_conf_load_enum[] = { + SOC_ENUM_SINGLE_EXT(3, crus_conf_load_text), +}; + +static const struct soc_enum crus_conf_load_no_prot_enum[] = { + SOC_ENUM_SINGLE_EXT(2, crus_conf_load_no_prot_text), +}; + +static const struct soc_enum crus_delta_enum[] = { + SOC_ENUM_SINGLE_EXT(3, crus_delta_text), +}; + +static const struct soc_enum crus_chan_swap_enum[] = { + SOC_ENUM_SINGLE_EXT(2, crus_chan_swap_text), +}; + +static const struct soc_enum crus_vol_attn_enum[] = { + SOC_ENUM_SINGLE_EXT(3, crus_vol_attn_text), +}; +static const struct snd_kcontrol_new crus_protect_controls[] = { + SOC_ENUM_EXT("Cirrus SP FBPort", cirrus_fb_controls_enum[0], + msm_routing_cirrus_fbport_get, + msm_routing_cirrus_fbport_put), + SOC_ENUM_EXT("Cirrus SP", crus_en_enum[0], + msm_routing_crus_sp_enable_get, + msm_routing_crus_sp_enable_put), + SOC_ENUM_EXT("Cirrus SP Protection", crus_prot_en_enum[0], + msm_routing_crus_sp_prot_enable_get, + msm_routing_crus_sp_prot_enable_put), + SOC_ENUM_EXT("Cirrus SP Usecase", crus_sp_usecase_enum[0], + msm_routing_crus_sp_usecase_get, + msm_routing_crus_sp_usecase_put), + SOC_ENUM_EXT("Cirrus SP Load Config", crus_conf_load_enum[0], + msm_routing_crus_load_config_get, + msm_routing_crus_load_config_put), + SOC_ENUM_EXT("Cirrus SP Delta Config", crus_delta_enum[0], + msm_routing_crus_delta_config_get, + msm_routing_crus_delta_config_put), + SOC_ENUM_EXT("Cirrus SP Channel Swap", crus_chan_swap_enum[0], + msm_routing_crus_chan_swap_get, + msm_routing_crus_chan_swap_put), + SOC_SINGLE_EXT("Cirrus SP Channel Swap Duration", SND_SOC_NOPM, 0, + MAX_CHAN_SWAP_SAMPLES, 0, + msm_routing_crus_chan_swap_dur_get, + msm_routing_crus_chan_swap_dur_put), + SOC_SINGLE_BOOL_EXT("Cirrus SP Failure Detection", 0, + msm_routing_crus_fail_det_get, + msm_routing_crus_fail_det), +}; +static const struct snd_kcontrol_new crus_no_protect_controls[] = { + SOC_ENUM_EXT("Cirrus SP FBPort", cirrus_fb_controls_enum[0], + msm_routing_cirrus_fbport_get, + msm_routing_cirrus_fbport_put), + SOC_ENUM_EXT("Cirrus SP", crus_en_enum[0], + msm_routing_crus_sp_enable_get, + msm_routing_crus_sp_enable_put), + SOC_ENUM_EXT("Cirrus SP Protection", crus_prot_en_enum[0], + msm_routing_crus_sp_prot_enable_get, + msm_routing_crus_sp_prot_enable_put), + SOC_ENUM_EXT("Cirrus SP Usecase", crus_sp_usecase_enum[0], + msm_routing_crus_sp_usecase_get, + msm_routing_crus_sp_usecase_put), + SOC_ENUM_EXT("Cirrus SP Load Config", crus_conf_load_no_prot_enum[0], + msm_routing_crus_load_config_get, + msm_routing_crus_load_config_put), + SOC_ENUM_EXT("Cirrus SP Delta Config", crus_delta_enum[0], + msm_routing_crus_delta_config_get, + msm_routing_crus_delta_config_put), + SOC_ENUM_EXT("Cirrus SP Channel Swap", crus_chan_swap_enum[0], + msm_routing_crus_chan_swap_get, + msm_routing_crus_chan_swap_put), + SOC_SINGLE_EXT("Cirrus SP Channel Swap Duration", SND_SOC_NOPM, 0, + MAX_CHAN_SWAP_SAMPLES, 0, + msm_routing_crus_chan_swap_dur_get, + msm_routing_crus_chan_swap_dur_put), + SOC_ENUM_EXT("Cirrus SP Volume Attenuation", crus_vol_attn_enum[0], + msm_routing_crus_vol_attn_get, + msm_routing_crus_vol_attn_put), +}; + +void msm_crus_pb_add_controls(struct snd_soc_platform *platform) +{ + if (this_ctrl.usecase_dt_count == 0) + pr_info("CRUS_SP: Usecase config not specified\n"); + + crus_sp_usecase_enum[0].items = this_ctrl.usecase_dt_count; + crus_sp_usecase_enum[0].texts = crus_sp_usecase_dt_text; + + if (this_ctrl.prot_en) + snd_soc_add_platform_controls( + platform, crus_protect_controls, + ARRAY_SIZE(crus_protect_controls)); + else + snd_soc_add_platform_controls( + platform, crus_no_protect_controls, + ARRAY_SIZE(crus_no_protect_controls)); +} + +EXPORT_SYMBOL(msm_crus_pb_add_controls); +int crus_afe_port_start(u16 port_id) +{ + pr_info("%s: 0x%x\n", __func__, port_id); + +//CSPL do not be involved in AFE +#if 0 + struct snd_kcontrol kcontrol; + struct snd_ctl_elem_value ucontrol; + + if (port_id != this_ctrl.ff_port) + return 0; + + this_ctrl.afe_start = true; + pr_info("%s: 0x%x\n", __func__, port_id); + + mutex_lock(&this_ctrl.sp_lock); + msm_routing_crus_sp_usecase_get(&kcontrol, + &ucontrol); + msm_routing_crus_sp_usecase_put(&kcontrol, + &ucontrol); + mutex_unlock(&this_ctrl.sp_lock); +#endif + return 0; +} +EXPORT_SYMBOL(crus_afe_port_start); +int crus_afe_port_close(u16 port_id) +{ + pr_info("%s: 0x%x\n", __func__, port_id); + +//CSPL do not be involved in AFE +#if 0 + if (port_id != this_ctrl.ff_port) + return 0; + + this_ctrl.afe_start = false; + pr_info("%s: 0x%x\n", __func__, port_id); +#endif + return 0; +} +EXPORT_SYMBOL(crus_afe_port_close); +static long crus_sp_shared_ioctl(struct file *f, unsigned int cmd, + void __user *arg) +{ + int result = 0, port; + uint32_t bufsize = 0, size; + void *io_data = NULL; + + pr_info("%s\n", __func__); + + if (copy_from_user(&size, arg, sizeof(size))) { + pr_err("CRUS_SP: copy_from_user (size) failed\n"); + result = -EFAULT; + goto exit; + } + + /* Copy IOCTL header from usermode */ + if (copy_from_user(&crus_sp_hdr, arg, size)) { + pr_err("CRUS_SP: copy_from_user (struct) failed\n"); + result = -EFAULT; + goto exit; + } + + bufsize = crus_sp_hdr.data_length; + io_data = kzalloc(bufsize, GFP_KERNEL); + + switch (cmd) { + case CRUS_SP_IOCTL_GET: + switch (crus_sp_hdr.module_id) { + case CRUS_MODULE_ID_TX: + port = this_ctrl.fb_port; + break; + case CRUS_MODULE_ID_RX: + port = this_ctrl.ff_port; + break; + default: + pr_info("CRUS_SP: Unrecognized port ID (%d)\n", + crus_sp_hdr.module_id); + port = this_ctrl.ff_port; + } + if (this_ctrl.q6afe_rev == 2) + crus_afe_get_param(port, CIRRUS_SP, + crus_sp_hdr.param_id, bufsize, + io_data); + else + crus_afe_get_param_v3(port, CIRRUS_SP, + crus_sp_hdr.param_id, bufsize, + io_data); + result = copy_to_user(crus_sp_hdr.data, io_data, bufsize); + if (result) { + pr_err("CRUS_SP: copy_to_user failed (%d)\n", result); + result = -EFAULT; + } else + result = bufsize; + break; + case CRUS_SP_IOCTL_SET: + result = copy_from_user(io_data, (void *)crus_sp_hdr.data, + bufsize); + if (result) { + pr_err("CRUS_SP: copy_from_user failed (%d)\n", result); + result = -EFAULT; + goto exit_io; + } + + switch (crus_sp_hdr.module_id) { + case CRUS_MODULE_ID_TX: + port = this_ctrl.fb_port; + break; + case CRUS_MODULE_ID_RX: + port = this_ctrl.ff_port; + break; + default: + pr_info("%s: Unrecognized port ID (%d)\n", __func__, + crus_sp_hdr.module_id); + port = this_ctrl.ff_port; + } + + if (this_ctrl.q6afe_rev == 2) { + crus_afe_set_param(port, CIRRUS_SP, + crus_sp_hdr.param_id, bufsize, + io_data); + } else { + crus_afe_set_param_v3(port, CIRRUS_SP, + crus_sp_hdr.param_id, bufsize, + io_data); + } + break; + + default: + pr_err("CRUS_SP: Invalid IOCTL, command = %d\n", cmd); + result = -EINVAL; + break; + } + +exit_io: + kfree(io_data); +exit: + return result; +} + +static long crus_sp_ioctl(struct file *f, unsigned int cmd, unsigned long arg) +{ + pr_info("%s\n", __func__); + + return crus_sp_shared_ioctl(f, cmd, (void __user *)arg); +} + +static long crus_sp_compat_ioctl(struct file *f, unsigned int cmd, + unsigned long arg) +{ + unsigned int cmd64; + + pr_info("%s\n", __func__); + + switch (cmd) { + case CRUS_SP_IOCTL_GET32: + cmd64 = CRUS_SP_IOCTL_GET; + break; + case CRUS_SP_IOCTL_SET32: + cmd64 = CRUS_SP_IOCTL_SET; + break; + default: + pr_err("CRUS_SP: Invalid IOCTL, command = %d\n", cmd); + return -EINVAL; + } + + return crus_sp_shared_ioctl(f, cmd64, compat_ptr(arg)); +} + +static int crus_sp_open(struct inode *inode, struct file *f) +{ + pr_debug("%s\n", __func__); + + atomic_inc(&this_ctrl.count_wait); + return 0; +} + +static int crus_sp_release(struct inode *inode, struct file *f) +{ + atomic_dec(&this_ctrl.count_wait); + return 0; +} + +static ssize_t temperature_left_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + static const int material = 250; + static const int scale_factor = 100000; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int out_cal0; + int out_cal1; + int z, r, t; + int temp0; + + crus_afe_get_param(this_ctrl.ff_port, CIRRUS_SP, CRUS_PARAM_RX_GET_TEMP, + CRUS_MAX_BUFFER_SIZE, buffer); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + out_cal0 = rx_temp.hp_status_l; + out_cal1 = rx_temp.full_status_l; + + z = rx_temp.z_l; + + temp0 = rx_temp.amb_temp_l; + + if ((out_cal0 != 2) || (out_cal1 != 2)) + return snprintf(buf, PAGE_SIZE, "Calibration is not done\n"); + + r = rx_temp.temp_l; + t = (material * scale_factor * (r - z) / z) + (temp0 * scale_factor); + + return snprintf(buf, PAGE_SIZE, "%d.%05dc\n", t / scale_factor, + t % scale_factor); +} +static DEVICE_ATTR_RO(temperature_left); + +static ssize_t temperature_right_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + static const int material = 250; + static const int scale_factor = 100000; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int out_cal0; + int out_cal1; + int z, r, t; + int temp0; + + crus_afe_get_param(this_ctrl.ff_port, CIRRUS_SP, CRUS_PARAM_RX_GET_TEMP, + CRUS_MAX_BUFFER_SIZE, buffer); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + out_cal0 = rx_temp.hp_status_r; + out_cal1 = rx_temp.full_status_r; + + z = rx_temp.z_r; + + temp0 = rx_temp.amb_temp_r; + + if ((out_cal0 != 2) || (out_cal1 != 2)) + return snprintf(buf, PAGE_SIZE, "Calibration is not done\n"); + + r = rx_temp.temp_r; + t = (material * scale_factor * (r - z) / z) + (temp0 * scale_factor); + + return snprintf(buf, PAGE_SIZE, "%d.%05dc\n", t / scale_factor, + t % scale_factor); +} +static DEVICE_ATTR_RO(temperature_right); + +static ssize_t resistance_left_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + static const int scale_factor = 100000000; + static const int amp_factor = 71498; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int out_cal0; + int out_cal1; + int r; + + crus_afe_get_param(this_ctrl.ff_port, CIRRUS_SP, CRUS_PARAM_RX_GET_TEMP, + CRUS_MAX_BUFFER_SIZE, buffer); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + out_cal0 = rx_temp.hp_status_l; + out_cal1 = rx_temp.full_status_l; + + if ((out_cal0 != 2) || (out_cal1 != 2)) + return snprintf(buf, PAGE_SIZE, "Calibration is not done\n"); + + r = rx_temp.temp_l * amp_factor; + + return snprintf(buf, PAGE_SIZE, "%d.%08d ohms\n", r / scale_factor, + r % scale_factor); +} +static DEVICE_ATTR_RO(resistance_left); + +static ssize_t resistance_right_show(struct device *dev, + struct device_attribute *a, char *buf) +{ + struct crus_rx_temperature_t rx_temp; + static const int scale_factor = 100000000; + static const int amp_factor = 71498; + int buffer[CRUS_MAX_BUFFER_SIZE / 4]; + int out_cal0; + int out_cal1; + int r; + + crus_afe_get_param(this_ctrl.ff_port, CIRRUS_SP, CRUS_PARAM_RX_GET_TEMP, + CRUS_MAX_BUFFER_SIZE, buffer); + + memcpy(&rx_temp, buffer, sizeof(rx_temp)); + + out_cal0 = rx_temp.hp_status_r; + out_cal1 = rx_temp.full_status_r; + + if ((out_cal0 != 2) || (out_cal1 != 2)) + return snprintf(buf, PAGE_SIZE, "Calibration is not done\n"); + + r = rx_temp.temp_r * amp_factor; + + return snprintf(buf, PAGE_SIZE, "%d.%08d ohms\n", r / scale_factor, + r % scale_factor); +} +static DEVICE_ATTR_RO(resistance_right); + +static struct attribute *crus_sp_attrs[] = { + &dev_attr_temperature_left.attr, + &dev_attr_temperature_right.attr, + &dev_attr_resistance_left.attr, + &dev_attr_resistance_right.attr, + NULL, +}; + +static const struct attribute_group crus_sp_group = { + .attrs = crus_sp_attrs, +}; + +static const struct attribute_group *crus_sp_groups[] = { + &crus_sp_group, + NULL, +}; + +#ifdef CONFIG_OF +static int msm_cirrus_playback_probe(struct platform_device *pdev) +{ + int i; + + pr_info("CRUS_SP: Initializing platform device\n"); + + this_ctrl.usecase_dt_count = + of_property_count_strings(pdev->dev.of_node, "usecase-names"); + if (this_ctrl.usecase_dt_count <= 0) { + pr_debug("CRUS_SP: Usecase names not found\n"); + this_ctrl.usecase_dt_count = 0; + return 0; + } + + if ((this_ctrl.usecase_dt_count > 0) && + (this_ctrl.usecase_dt_count <= MAX_TUNING_CONFIGS)) + of_property_read_string_array(pdev->dev.of_node, + "usecase-names", + crus_sp_usecase_dt_text, + this_ctrl.usecase_dt_count); + else if (this_ctrl.usecase_dt_count > MAX_TUNING_CONFIGS) { + pr_err("CRUS_SP: Max of %d usecase configs allowed\n", + MAX_TUNING_CONFIGS); + return -EINVAL; + } + + for (i = 0; i < this_ctrl.usecase_dt_count; i++) + pr_info("CRUS_SP: Usecase[%d] = %s\n", i, + crus_sp_usecase_dt_text[i]); + + this_ctrl.prot_en = + of_property_read_bool(pdev->dev.of_node, "protect-en"); + + return 0; +} + +static const struct of_device_id msm_cirrus_playback_dt_match[] = { + { .compatible = "cirrus,msm-cirrus-playback" }, + {} +}; +MODULE_DEVICE_TABLE(of, msm_cirrus_playback_dt_match); + +static struct platform_driver msm_cirrus_playback_driver = { + .driver = { + .name = "msm-cirrus-playback", + .owner = THIS_MODULE, + .of_match_table = msm_cirrus_playback_dt_match, + }, + .probe = msm_cirrus_playback_probe, +}; +#endif + +static const struct file_operations crus_sp_fops = { + .owner = THIS_MODULE, + .open = crus_sp_open, + .release = crus_sp_release, + .unlocked_ioctl = crus_sp_ioctl, + .compat_ioctl = crus_sp_compat_ioctl, +}; + +struct miscdevice crus_sp_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = "msm_cirrus_playback", + .fops = &crus_sp_fops, +}; + +int __init crus_sp_init(void) +{ + pr_info("Initializing misc device\n"); + atomic_set(&this_ctrl.callback_wait, 0); + atomic_set(&this_ctrl.count_wait, 0); + mutex_init(&this_ctrl.param_lock); + mutex_init(&this_ctrl.sp_lock); + + misc_register(&crus_sp_misc); + + if (sysfs_create_groups(&crus_sp_misc.this_device->kobj, + crus_sp_groups)) + pr_err("%s: Could not create sysfs groups\n", __func__); + +#ifdef CONFIG_OF + platform_driver_register(&msm_cirrus_playback_driver); +#endif + return 0; +} + +void __exit crus_sp_exit(void) +{ + pr_debug("%s\n", __func__); + mutex_destroy(&this_ctrl.param_lock); + +#ifdef CONFIG_OF + platform_driver_unregister(&msm_cirrus_playback_driver); +#endif +} + +MODULE_AUTHOR("Cirrus SP"); +MODULE_DESCRIPTION("Providing Interface to Cirrus SP"); +MODULE_LICENSE("GPL"); diff --git a/techpack/audio/include/dsp/apr_elliptic.h b/techpack/audio/include/dsp/apr_elliptic.h new file mode 100644 index 000000000000..624fc6c8fde1 --- /dev/null +++ b/techpack/audio/include/dsp/apr_elliptic.h @@ -0,0 +1,41 @@ +#pragma once + +#include +#include +#include +#include + +#define ELLIPTIC_SET_PARAMS_SIZE 114 +#define ELLIPTIC_ULTRASOUND_MODULE_TX 0x0F010201 +#define ELLIPTIC_ULTRASOUND_MODULE_RX 0x0FF10202 +#define ULTRASOUND_OPCODE 0x0FF10204 + +/* This need to be updated for all platforms */ +#define ELLIPTIC_PORT_ID SLIMBUS_2_TX + +/** Sequence of Elliptic Labs Ultrasound module parameters */ +struct afe_ultrasound_set_params_t { + uint32_t payload[ELLIPTIC_SET_PARAMS_SIZE]; +} __packed; + +/** Sequence of Elliptic Labs Ultrasound module parameters */ + +/** Elliptic APR public */ + +int32_t ultrasound_apr_set_parameter(int32_t port_id, uint32_t param_id, + u8 *user_params, int32_t length); + +int32_t elliptic_process_apr_payload(uint32_t *payload); + +int elliptic_notify_gain_change_msg(int component_id, int gaindb); + +typedef struct afe_ultrasound_state { + atomic_t us_apr_state; + void **ptr_apr; + atomic_t *ptr_status; + atomic_t *ptr_state; + wait_queue_head_t *ptr_wait; + int timeout_ms; +} afe_ultrasound_state_t; + +extern afe_ultrasound_state_t elus_afe; diff --git a/techpack/audio/include/dsp/apr_mius.h b/techpack/audio/include/dsp/apr_mius.h new file mode 100644 index 000000000000..cd7c07196739 --- /dev/null +++ b/techpack/audio/include/dsp/apr_mius.h @@ -0,0 +1,41 @@ +#pragma once + +#include +#include +#include +#include + +#define MIUS_SET_PARAMS_SIZE 114 +#define MIUS_ULTRASOUND_MODULE_TX 0x0F010201 +#define MIUS_ULTRASOUND_MODULE_RX 0x0FF10202 +#define MI_ULTRASOUND_OPCODE 0x0FF10208 + +/* This need to be updated for all platforms */ +#define MIUS_PORT_ID SLIMBUS_2_TX + +/** Sequence of MI Ultrasound module parameters */ +struct afe_mi_ultrasound_set_params_t { + uint32_t payload[MIUS_SET_PARAMS_SIZE]; +} __packed; + +/** Sequence of MI Ultrasound module parameters */ + +/** Elliptic APR public */ + +int32_t mi_ultrasound_apr_set_parameter(int32_t port_id, uint32_t param_id, + u8 *user_params, int32_t length); + +int32_t mius_process_apr_payload(uint32_t *payload); + +int mius_notify_gain_change_msg(int component_id, int gaindb); + +typedef struct afe_mi_ultrasound_state { + atomic_t us_apr_state; + void **ptr_apr; + atomic_t *ptr_status; + atomic_t *ptr_state; + wait_queue_head_t *ptr_wait; + int timeout_ms; +} afe_mi_ultrasound_state_t; + +extern afe_mi_ultrasound_state_t mius_afe; diff --git a/techpack/audio/include/dsp/msm-cirrus-playback-v2.h b/techpack/audio/include/dsp/msm-cirrus-playback-v2.h new file mode 100644 index 000000000000..045b2d7572c9 --- /dev/null +++ b/techpack/audio/include/dsp/msm-cirrus-playback-v2.h @@ -0,0 +1,177 @@ +/* Copyright (c) 2015 Cirrus Logic, Inc. + * Copyright (C) 2021 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef MSM_CIRRUS_PLAYBACK_H +#define MSM_CIRRUS_PLAYBACK_H +#include +#include +#include +#include +#include + +#define VOL_ATTN_MAX 0x7FFFFFFF +#define VOL_ATTN_18DB 257698038 +#define VOL_ATTN_24DB 128849019 +#define CONFIG_FILE_SIZE 128 +#define PAYLOAD_FOLLOWS_CONFIG 4 +#define MAX_TUNING_CONFIGS 4 +#define MIN_CHAN_SWAP_SAMPLES 48 +#define MAX_CHAN_SWAP_SAMPLES 9600 +#define CRUS_MAX_BUFFER_SIZE 384 +#define CRUS_RES_OPEN_CIRCUIT 65535 +#define CRUS_BUF_SIZE 256 +#define INVALID_COPPID (-1) + +/* Payload struct for getting or setting one integer value from/to the DSP + * module + */ +struct crus_single_data_t { + int32_t value; +}; + +/* Payload struct for getting or setting two integer values from/to the DSP + * module + */ +struct crus_dual_data_t { + int32_t data1; + int32_t data2; +}; + +/* Payload struct for getting or setting three integer values from/to the DSP + * module + */ +struct crus_triple_data_t { + int32_t data1; + int32_t data2; + int32_t data3; +}; + +/* Payload struct for setting the RX and TX use cases */ +struct crus_rx_run_case_ctrl_t { + int32_t value; + int32_t status_l; + int32_t checksum_l; + int32_t z_l; + int32_t status_r; + int32_t checksum_r; + int32_t z_r; + int32_t atemp; +}; + +#define APR_CHUNK_SIZE 256 +#define TUNING_MAX_SIZE 2048 + +/* Payload struct for sending an external configuration string to the DSP + * module + */ +struct crus_external_config_t { + uint32_t total_size; + uint32_t chunk_size; + int32_t done; + int32_t reserved; + int32_t config; + char data[APR_CHUNK_SIZE]; +}; +/* Payload struct for sending an external tuning transition string to the DSP + * module + */ +struct crus_delta_config_t { + uint32_t total_size; + uint32_t chunk_size; + int32_t done; + int32_t index; + int32_t reserved; + int32_t config; + char data[APR_CHUNK_SIZE]; +}; + +struct crus_rx_temperature_t { + uint32_t cal_status_l; + uint32_t temp_r; + uint32_t z_r; + uint32_t temp_l; + uint32_t z_l; + uint32_t cal_status_r; + uint32_t amb_temp_l; + uint32_t excur_model_r; + uint32_t excur_model_l; + uint32_t cksum_r; + uint32_t amb_temp_r; + uint32_t cksum_l; + uint32_t hp_status_l; + uint32_t full_status_l; + uint32_t hp_status_r; + uint32_t full_status_r; +}; + +struct crus_resistance_t { + uint32_t status_l; + uint32_t status_r; + uint32_t r_l; + uint32_t r_r; +}; + +struct cache_block { + struct snd_kcontrol kcontrol; + struct snd_ctl_elem_value ucontrol; + snd_kcontrol_put_t *put; + void (*destroy)(void *block); + struct list_head entry; +}; + +typedef struct cache_block cache_block_t; + +struct crus_control_t { + struct device *device; + int32_t module_id; + int32_t fb_port; + int32_t ff_port; + bool qdsp_start; + int32_t sp_enable; + bool cache_execute; + bool prot_en; + int32_t copp_idx; + int instance_id; + int copp_ids[3]; + atomic_t qdsp_start_count[3]; + int32_t vol_atten; + int32_t usecase; + int32_t location; + int32_t swap_duration; + int32_t swap; + int32_t usecase_dt_count; + bool resistance_en; + bool fail_det; + atomic_t ioctl_count; + int32_t conf_index; + int32_t delta_index; + int32_t apr_payload[APR_CHUNK_SIZE]; + int32_t tuning[TUNING_MAX_SIZE]; + bool initialized; +}; + +int crus_afe_get_params(u16 port_id, uint32_t module_id, uint32_t param_id, + void *data, int size); +int crus_afe_set_params(u16 port_id, uint32_t module_id, uint32_t param_id, + void *data, int size); +int crus_adm_set_params(int port_id, int copp_idx, int instance_id, + uint32_t module_id, uint32_t param_id, char *params, + uint32_t length); +int crus_adm_get_params(int port_id, int copp_idx, int instance_id, + uint32_t module_id, uint32_t param_id, char *params, + uint32_t length, uint32_t client_id); +int crus_qdsp_port_start(u16 port_id, int copp_id); +int crus_qdsp_port_close(u16 port_id, int copp_id); +int crus_afe_callback(uint32_t opcode, void *payload, int size); + +void msm_crus_pb_add_controls(struct snd_soc_component *component); +#endif /* _MSM_CIRRUS_PLAYBACK_H */ diff --git a/techpack/audio/include/dsp/msm-cirrus-playback.h b/techpack/audio/include/dsp/msm-cirrus-playback.h new file mode 100644 index 000000000000..7f2f3f175e2c --- /dev/null +++ b/techpack/audio/include/dsp/msm-cirrus-playback.h @@ -0,0 +1,183 @@ +/* Copyright (c) 2015 Cirrus Logic, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef MSM_CIRRUS_PLAYBACK_H +#define MSM_CIRRUS_PLAYBACK_H +#define DEBUG +#include +#include +#include +#include +#include +#include + +#define MIN_CHAN_SWAP_SAMPLES 48 +#define MAX_CHAN_SWAP_SAMPLES 9600 +#define VOL_ATTN_MAX 0x7FFFFFFF +#define VOL_ATTN_18DB 257698038 +#define VOL_ATTN_24DB 128849019 + +struct afe_cspl_state { + void **apr; + atomic_t *status; + atomic_t *state; + wait_queue_head_t *wait; + int timeout_ms; +}; + +extern struct afe_cspl_state cspl_afe; + +struct afe_custom_crus_set_config_v2_t { + struct apr_hdr hdr; + struct afe_port_cmd_set_param_v2 param; + struct param_hdr_v2 data; +} __packed; + +struct afe_custom_crus_get_config_v2_t { + struct apr_hdr hdr; + struct afe_port_cmd_get_param_v2 param; + struct param_hdr_v2 data; +} __packed; + +struct afe_custom_crus_set_config_t { + struct apr_hdr hdr; + struct afe_port_cmd_set_param_v3 param; + struct param_hdr_v3 data; +} __packed; + +struct afe_custom_crus_get_config_t { + struct apr_hdr hdr; + struct afe_port_cmd_get_param_v3 param; + struct param_hdr_v3 data; +} __packed; + +/* Payload struct for getting or setting one integer value from/to the DSP module */ +struct crus_single_data_t { + int32_t value; +}; + +/* Payload struct for getting or setting two integer values from/to the DSP module */ +struct crus_dual_data_t { + int32_t data1; + int32_t data2; +}; + +/* Payload struct for getting or setting three integer values from/to the DSP module */ +struct crus_triple_data_t { + int32_t data1; + int32_t data2; + int32_t data3; +}; + +/* Payload struct for setting the RX and TX use cases */ +struct crus_rx_run_case_ctrl_t { + int32_t value; + int32_t status_l; + int32_t checksum_l; + int32_t z_l; + int32_t status_r; + int32_t checksum_r; + int32_t z_r; + int32_t atemp; +}; + +/* Payload struct for getting calibration result from DSP module */ +struct cirrus_cal_result_t { + int32_t status_l; + int32_t checksum_l; + int32_t z_l; + int32_t status_r; + int32_t checksum_r; + int32_t z_r; +}; + +#define APR_CHUNK_SIZE 256 + +/* Payload struct for sending an external configuration string to the DSP + * module + */ +struct crus_external_config_t { + uint32_t total_size; + uint32_t chunk_size; + int32_t done; + int32_t reserved; + int32_t config; + char data[APR_CHUNK_SIZE]; +}; +/* Payload struct for sending an external tuning transition string to the DSP + * module + */ +struct crus_delta_config_t { + uint32_t total_size; + uint32_t chunk_size; + int32_t done; + int32_t index; + int32_t reserved; + int32_t config; + char data[APR_CHUNK_SIZE]; +}; + +struct crus_rx_temperature_t { + uint32_t cal_status_l; + uint32_t temp_r; + uint32_t z_r; + uint32_t temp_l; + uint32_t z_l; + uint32_t cal_status_r; + uint32_t amb_temp_l; + uint32_t excur_model_r; + uint32_t excur_model_l; + uint32_t cksum_r; + uint32_t amb_temp_r; + uint32_t cksum_l; + uint32_t hp_status_l; + uint32_t full_status_l; + uint32_t hp_status_r; + uint32_t full_status_r; +}; + +#define CONFIG_FILE_SIZE 128 +#define PAYLOAD_FOLLOWS_CONFIG 4 +#define MAX_TUNING_CONFIGS 4 +#define MIN_CHAN_SWAP_SAMPLES 48 +#define MAX_CHAN_SWAP_SAMPLES 9600 +#define CRUS_MAX_BUFFER_SIZE 384 + +struct crus_control_t { + struct device *device; + int32_t q6afe_rev; + bool afe_start; + bool enable; + bool prot_en; + int32_t fb_port_index; + int32_t fb_port; + int32_t ff_port; + int ch_sw_duration; + int32_t ch_sw; + int32_t vol_atten; + atomic_t callback_wait; + atomic_t count_wait; + struct mutex param_lock; + struct mutex sp_lock; + int32_t *user_buffer; + int32_t usecase; + int32_t config; + int32_t conf_sel; + int32_t delta_sel; + int32_t usecase_dt_count; +}; + +//extern int afe_apr_send_pkt_crus(void *data, int index, int set); + +int crus_afe_callback(void *payload, int size); +void msm_crus_pb_add_controls(struct snd_soc_platform *platform); +#endif /* _MSM_CIRRUS_PLAYBACK_H */ diff --git a/techpack/audio/include/dsp/tas_smart_amp_v2.h b/techpack/audio/include/dsp/tas_smart_amp_v2.h new file mode 100644 index 000000000000..4aa3b230bdcf --- /dev/null +++ b/techpack/audio/include/dsp/tas_smart_amp_v2.h @@ -0,0 +1,177 @@ +#ifndef __TAS_SMART_AMP__ +#define __TAS_SMART_AMP__ + +/*Should be defined in configuration file*/ +//#define CONFIG_TAS25XX_ALGO +#define CONFIG_TAS25XX_ALGO_STEREO +#define CONFIG_SET_RE_IN_KERNEL + +//FIXME +//update this value at OEM/ODM +//#pragma message ("########### FIXME ################") +#define SMARTAMP_SPEAKER_CALIBDATA_FILE \ + "/mnt/vendor/persist/audio/tas25xx_calib.bin" +//#define SMARTAMP_SPEAKER_CALIBDATA_FILE "/persist/audio/smartamp_calib.bin" + +#define APR_VERSION_V2 0 +#define APR_VERSION_V3 1 + +#include +//#if APR_VERSION_V2 +#include +#include +//#else +//#endif +#include + +#define AFE_SMARTAMP_MODULE_RX 0x11111112 +#define AFE_SMARTAMP_MODULE_TX 0x11111111 + +#define CAPI_V2_TAS_TX_ENABLE 0x10012D14 +#define CAPI_V2_TAS_TX_CFG 0x10012D16 +#define CAPI_V2_TAS_RX_ENABLE 0x10012D13 +#define CAPI_V2_TAS_RX_CFG 0x10012D15 + +#define MAX_DSP_PARAM_INDEX 2048 + +#define TAS_PAYLOAD_SIZE 14 +#define TAS_GET_PARAM 1 +#define TAS_SET_PARAM 0 + +//FIXME +//Update as needed +#define TAS_RX_PORT AFE_PORT_ID_QUATERNARY_MI2S_RX +#define TAS_TX_PORT AFE_PORT_ID_QUATERNARY_MI2S_TX + +#define CHANNEL0 1 +#define CHANNEL1 2 + +#define TRUE 1 +#define FALSE 0 + +#define TAS_SA_GET_F0 3810 +#define TAS_SA_GET_Q 3811 +#define TAS_SA_GET_TV 3812 +#define TAS_SA_GET_RE 3813 +#define TAS_SA_CALIB_INIT 3814 +#define TAS_SA_CALIB_DEINIT 3815 +#define TAS_SA_SET_RE 3816 +#define TAS_SA_F0_TEST_INIT 3817 +#define TAS_SA_F0_TEST_DEINIT 3818 +#define TAS_SA_SET_PROFILE 3819 +#define TAS_SA_GET_STATUS 3821 +#define TAS_SA_SET_SPKID 3822 +#define TAS_SA_SET_TCAL 3823 + +#define TAS_SA_IV_VBAT_FMT 3825 +/*Added for DC Detection*/ +#define CAPI_V2_TAS_SA_DC_DETECT 0x40404040 + +#define CALIB_START 1 +#define CALIB_STOP 2 +#define TEST_START 3 +#define TEST_STOP 4 + +#define SLAVE1 0x98 +#define SLAVE2 0x9A +#define SLAVE3 0x9C +#define SLAVE4 0x9E + +#define CHANNEL0 1 +#define CHANNEL1 2 + +#define TAS_SA_IS_SPL_IDX(X) ((((X) >= 3810) && ((X) < 3899)) ? 1 : 0) +#define TAS_CALC_PARAM_IDX(I, LEN, CH) ((I) | (LEN << 16) | (CH << 24)) +#define AFE_SA_IS_SPL_IDX(X) ((((X) >= 3810) && ((X) < 3899)) ? 1 : 0) +/* To Decode the Param ID */ +#define TAS_PARAM_IDX_GET_ID(X) (0xFFFF & (X)) +#define TAS_PARAM_IDX_GET_LEN(X) ((0x0FFF0000 & (X)) >> 16) +#define TAS_PARAM_IDX_GET_CH(X) ((0xF0000000 & (X)) >> 24) + +typedef enum { + IV_SENSE_FORMAT_NO_VBAT = 0, + IV_SENSE_FORMAT_12_BIT_WITH_8BIT_VBAT = 1, + IV_SENSE_FORMAT_8_BIT_WITH_8BIT_VBAT = 2, +} ti_smartamp_iv_vbat_format_t; + +/* + * List all the other profiles other than none and calibration. + */ +#define TAS_ALGO_PROFILE_LIST "MUSIC", "VOICE", "VOIP", "RINGTONE" + +struct afe_smartamp_get_set_params_t { + uint32_t payload[TAS_PAYLOAD_SIZE]; +} __packed; + +#if APR_VERSION_V2 +struct afe_smartamp_config_command { + struct apr_hdr hdr; + struct afe_port_cmd_set_param_v2 param; + struct afe_port_param_data_v2 pdata; + struct afe_smartamp_get_set_params_t prot_config; +} __packed; + +struct afe_smartamp_get_calib { + struct apr_hdr hdr; + struct afe_port_cmd_get_param_v2 get_param; + struct afe_port_param_data_v2 pdata; + struct afe_smartamp_get_set_params_t res_cfg; +} __packed; + +struct afe_smartamp_calib_get_resp { + uint32_t status; + struct afe_port_param_data_v2 pdata; + struct afe_smartamp_get_set_params_t res_cfg; +} __packed; + +#elif APR_VERSION_V3 + +//#define BUILD_STUB +/* only for build test */ +#ifdef BUILD_STUB +#define INSTANCE_ID_0 0 +#define AFE_PORT_CMDRSP_GET_PARAM_V3 0 +struct param_hdr_v3 { + int module_id; + int instance_id; + int param_id; + int param_size; +}; + +struct mem_mapping_hdr {}; + +#endif + +struct afe_smartamp_get_calib { + struct apr_hdr hdr; + struct mem_mapping_hdr mem_hdr; + struct param_hdr_v3 pdata; + struct afe_smartamp_get_set_params_t res_cfg; +} __packed; + +struct afe_smartamp_calib_get_resp { + uint32_t status; + struct param_hdr_v3 pdata; + struct afe_smartamp_get_set_params_t res_cfg; +} __packed; +#endif + +typedef struct { + int channel; +} dc_detection_data_t; + +void register_tas256x_reset_func(void *fptr, dc_detection_data_t *data); +int afe_tas_smartamp_get_calib_data(uint32_t module_id, uint32_t param_id, + int32_t length, uint8_t *data); +int afe_tas_smartamp_set_calib_data(uint32_t module_id, uint32_t param_id, + int32_t length, uint8_t *data); + +int tas25xx_smartamp_algo_ctrl(u8 *user_data, uint32_t param_id, + uint8_t get_set, uint32_t length, + uint32_t module_id); + +void tas_smartamp_add_algo_controls(struct snd_soc_codec *codec); +//void tas_smartamp_add_algo_controls_for_platform (struct snd_soc_platform *platform); +void tas_smartamp_remove_algo_controls(struct snd_soc_codec *codec); +bool tas25xx_set_iv_bit_fomat(int iv_data_with, int vbat, int update_now); +#endif diff --git a/techpack/audio/include/elliptic/elliptic_data_io.h b/techpack/audio/include/elliptic/elliptic_data_io.h new file mode 100644 index 000000000000..b9f642595dfe --- /dev/null +++ b/techpack/audio/include/elliptic/elliptic_data_io.h @@ -0,0 +1,155 @@ +/** +* Copyright Elliptic Labs 2015-2016 +* Copyright (C) 2019 XiaoMi, Inc. +* +*/ + +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +#define ELLIPTIC_DATA_IO_AP_TO_DSP 0 +#define ELLIPTIC_DATA_IO_DSP_TO_AP 1 + +#define ELLIPTIC_DATA_IO_READ_OK 0 +#define ELLIPTIC_DATA_IO_READ_BUSY 1 +#define ELLIPTIC_DATA_IO_READ_CANCEL 2 + +#define ELLIPTIC_MSG_BUF_SIZE 512 + +/* wake source timeout in ms*/ +#define ELLIPTIC_WAKEUP_TIMEOUT 250 + +#define ELLIPTIC_DATA_FIFO_SIZE (PAGE_SIZE) + +#define ULTRASOUND_RX_PORT_ID 0 +#define ULTRASOUND_TX_PORT_ID 1 + +/* Elliptic Labs UltraSound Module */ +#define ELLIPTIC_ULTRASOUND_DISABLE 0 +#define ELLIPTIC_ULTRASOUND_ENABLE 1 +#define ELLIPTIC_ULTRASOUND_SET_PARAMS 2 +#define ELLIPTIC_ULTRASOUND_GET_PARAMS 3 +#define ELLIPTIC_ULTRASOUND_RAMP_DOWN 4 + +/** Param ID definition */ +#define ELLIPTIC_ULTRASOUND_PARAM_ID_ENGINE_DATA 3 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_CALIBRATION_DATA 11 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_ENGINE_VERSION 12 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_BUILD_BRANCH 14 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_CALIBRATION_V2_DATA 15 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_SENSORHUB 16 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_DIAGNOSTICS_DATA 17 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_TAG 18 +#define ELLIPTIC_ULTRASOUND_PARAM_ID_ML_DATA 19 + +#define ELLIPTIC_DATA_READ_BUSY 0 +#define ELLIPTIC_DATA_READ_OK 1 +#define ELLIPTIC_DATA_READ_CANCEL 2 + +#define ELLIPTIC_ALL_DEVICES -1 +#define ELLIPTIC_DEVICE_0 0 +#define ELLIPTIC_DEVICE_1 1 + +enum elliptic_message_id { + ELLIPTIC_MESSAGE_PAYLOAD, /* Input to AP*/ + ELLIPTIC_MESSAGE_RAW, /* Output from AP*/ + ELLIPTIC_MESSAGE_CALIBRATION, + ELLIPTIC_MESSAGE_CALIBRATION_V2, + ELLIPTIC_MESSAGE_DIAGNOSTICS, + ELLIPTIC_MAX_MESSAGE_IDS +}; + +typedef enum { + ELLIPTIC_DATA_PUSH_FROM_KERNEL, + ELLIPTIC_DATA_PUSH_FROM_USERSPACE +} elliptic_data_push_t; + +struct elliptic_data { + /* wake lock timeout */ + unsigned int wakeup_timeout; + + /* members for top half interrupt handling */ + struct kfifo fifo_isr; + spinlock_t fifo_isr_spinlock; + wait_queue_head_t fifo_isr_not_empty; + struct mutex user_buffer_lock; + + /* buffer to swap data from isr fifo to userspace */ + uint8_t isr_swap_buffer[ELLIPTIC_MSG_BUF_SIZE]; + + atomic_t abort_io; + + /* debug counters, reset between open/close */ + uint32_t isr_fifo_discard; + + /* debug counters, persistent */ + uint32_t isr_fifo_discard_total; + uint32_t userspace_read_total; + uint32_t isr_write_total; +}; + +/* Elliptic IO module API (implemented by IO module)*/ + +int elliptic_data_io_initialize(void); +int elliptic_data_io_cleanup(void); + +int32_t elliptic_data_io_write(uint32_t message_id, const char *data, + size_t data_size); + +int32_t elliptic_data_io_transact(uint32_t message_id, const char *data, + size_t data_size, char *output_data, + size_t output_data_size); + +/* Elliptic driver API (implemented by main driver)*/ +int elliptic_data_initialize(struct elliptic_data *, size_t max_queue_size, + unsigned int wakeup_timeout, int id); + +int elliptic_data_cleanup(struct elliptic_data *); + +void elliptic_data_reset_debug_counters(struct elliptic_data *); +void elliptic_data_update_debug_counters(struct elliptic_data *); +void elliptic_data_print_debug_counters(struct elliptic_data *); + +/* Called from elliptic device read */ +size_t elliptic_data_pop(struct elliptic_data *, char __user *buffer, + size_t buffer_size); + +/* Used for cancelling a blocking read */ +void elliptic_data_cancel(struct elliptic_data *); + +/* Called from IO module*/ +int elliptic_data_push(int deviceid, const char *buffer, size_t buffer_size, + elliptic_data_push_t); + +/* Writes to io module and user space control */ +int32_t elliptic_data_write(uint32_t message_id, const char *data, + size_t data_size); + +/* Opens port */ +int elliptic_open_port(int portid); + +/* Closes port */ +int elliptic_close_port(int portid); + +/* Opens port */ +int elliptic_io_open_port(int portid); + +/* Closes port */ +int elliptic_io_close_port(int portid); + +/* Create device node for userspace io driver*/ +int elliptic_userspace_io_driver_init(void); +void elliptic_userspace_io_driver_exit(void); + +/* Create device node for userspace io driver*/ +int elliptic_userspace_ctrl_driver_init(void); +void elliptic_userspace_ctrl_driver_exit(void); +int32_t elliptic_userspace_ctrl_write(uint32_t message_id, const char *data, + size_t data_size); diff --git a/techpack/audio/include/elliptic/elliptic_device.h b/techpack/audio/include/elliptic/elliptic_device.h new file mode 100644 index 000000000000..6ebf208e8a28 --- /dev/null +++ b/techpack/audio/include/elliptic/elliptic_device.h @@ -0,0 +1,50 @@ +/** + * Copyright Elliptic Labs + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#pragma once + +#include +#include +#include +#include + +#define ELLIPTIC_DEVICENAME "elliptic" +#define ELLIPTIC_NUM_DEVICES 2 + +#define IOCTL_ELLIPTIC_APP 197 +#define MIRROR_TAG 0x3D0A4842 + +#define IOCTL_ELLIPTIC_DATA_IO_CANCEL _IO(IOCTL_ELLIPTIC_APP, 2) + +#define IOCTL_ELLIPTIC_ACTIVATE_ENGINE _IOW(IOCTL_ELLIPTIC_APP, 3, int) + +#define IOCTL_ELLIPTIC_SET_RAMP_DOWN _IO(IOCTL_ELLIPTIC_APP, 4) + +#define IOCTL_ELLIPTIC_SYSTEM_CONFIGURATION _IOW(IOCTL_ELLIPTIC_APP, 5, int) + +#define IOCTL_ELLIPTIC_DATA_IO_MIRROR \ + _IOW(IOCTL_ELLIPTIC_APP, 117, unsigned char *) + +struct elliptic_device { + int opened; + struct cdev cdev; + struct semaphore sem; + struct elliptic_data el_data; +}; + +extern struct class *elliptic_class; + +#define EL_PRINT_E(string, arg...) \ + pr_err("[ELUS] : (%s) : " string "\n", __func__, ##arg) + +#define EL_PRINT_W(string, arg...) \ + pr_warn("[ELUS] : (%s) : " string "\n", __func__, ##arg) + +#define EL_PRINT_I(string, arg...) \ + pr_info("[ELUS] : (%s) : " string "\n", __func__, ##arg) + +#define EL_PRINT_D(string, arg...) \ + pr_debug("[ELUS] : (%s) : " string "\n", __func__, ##arg) diff --git a/techpack/audio/include/elliptic/elliptic_mixer_controls.h b/techpack/audio/include/elliptic/elliptic_mixer_controls.h new file mode 100644 index 000000000000..552c38d80409 --- /dev/null +++ b/techpack/audio/include/elliptic/elliptic_mixer_controls.h @@ -0,0 +1,185 @@ +#pragma once +#include +#include +#include +#include + +#define ELLIPTIC_OBJ_ID_CALIBRATION_DATA 1 +#define ELLIPTIC_OBJ_ID_VERSION_INFO 2 +#define ELLIPTIC_OBJ_ID_BRANCH_INFO 3 +#define ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA 4 +#define ELLIPTIC_OBJ_ID_DIAGNOSTICS_DATA 5 +#define ELLIPTIC_OBJ_ID_TAG_INFO 6 +#define ELLIPTIC_OBJ_ID_ML_DATA 7 + +#define ELLIPTIC_SYSTEM_CONFIGURATION_SIZE 96 +#define ELLIPTIC_CALIBRATION_DATA_SIZE 64 +#define ELLIPTIC_CALIBRATION_V2_DATA_SIZE 448 +#define ELLIPTIC_DIAGNOSTICS_DATA_SIZE 448 +#define ELLIPTIC_DIAGNOSTICS_U32_DATA_VALUES \ + (ELLIPTIC_DIAGNOSTICS_DATA_SIZE >> 2) +#define ELLIPTIC_SENSOR_DATA_SIZE 68 +#define ELLIPTIC_SENSOR_U32_DATA_VALUES (ELLIPTIC_SENSOR_DATA_SIZE >> 2) +#define ELLIPTIC_VERSION_INFO_SIZE 16 +#define ELLIPTIC_BRANCH_INFO_SIZE 32 +#define ELLIPTIC_BRANCH_INFO_MAX_SIZE 128 +#define ELLIPTIC_TAG_INFO_SIZE 32 +#define ELLIPTIC_ML_DATA_SIZE 432 + +#define ELLIPTIC_ULTRASOUND_DISABLE 0 +#define ELLIPTIC_ULTRASOUND_ENABLE 1 +#define ELLIPTIC_ULTRASOUND_SET_PARAMS 2 +#define ELLIPTIC_ULTRASOUND_GET_PARAMS 3 +#define ELLIPTIC_ULTRASOUND_RAMP_DOWN 4 + +/** register */ +#define ELLIPTIC_CALIBRATION 1 +/** bits */ +#define ELLIPTIC_CALIBRATION_STATE 0 +#define ELLIPTIC_CALIBRATION_PROFILE 1 +#define ELLIPTIC_ULTRASOUND_GAIN 2 + +/** custom settings */ +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_COUNT 16 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE 0x7FFFFFFF + +/** register */ +#define ELLIPTIC_SYSTEM_CONFIGURATION 0 +/** bits */ +#define ELLIPTIC_SYSTEM_CONFIGURATION_LATENCY 0 +#define ELLIPTIC_SYSTEM_CONFIGURATION_SENSITIVITY 1 +#define ELLIPTIC_SYSTEM_CONFIGURATION_SPEAKER_SCALING 2 +#define ELLIPTIC_SYSTEM_CONFIGURATION_MICROPHONE_INDEX 3 +#define ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE 4 +#define ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS 5 +#define ELLIPTIC_SYSTEM_CONFIGURATION_LOG_LEVEL 6 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0 7 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_1 8 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_2 9 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_3 10 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_4 11 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_5 12 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_6 13 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_7 14 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_8 15 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_9 16 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_10 17 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_11 18 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_12 19 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_13 20 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_14 21 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15 22 + +#define ELLIPTIC_SYSTEM_CONFIGURATION_SUSPEND 23 +#define ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_ENABLED 24 +#define ELLIPTIC_SYSTEM_CONFIGURATION_OUTPUT_ENABLED 25 +#define ELLIPTIC_SYSTEM_CONFIGURATION_EXTERNAL_EVENT 26 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CALIBRATION_METHOD 27 +#define ELLIPTIC_SYSTEM_CONFIGURATION_DEBUG_MODE 28 +#define ELLIPTIC_SYSTEM_CONFIGURATION_NUMBER_OF_RUNS 29 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CONTEXT 30 +#define ELLIPTIC_SYSTEM_CONFIGURATION_CAPTURE 31 +#define ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_CHANNELS 32 + +#define ELLIPTIC_SYSTEM_CONFIGURATION_MAX_CONTEXT_VALUE 0x7FFFFFFF + +struct elliptic_engine_version_info { + uint32_t major; + uint32_t minor; + uint32_t build; + uint32_t revision; +}; + +struct elliptic_shared_data_block { + uint32_t object_id; + size_t size; + void *buffer; +}; + +struct elliptic_shared_data_block *elliptic_get_shared_obj(uint32_t object_id); + +extern unsigned int elliptic_add_platform_controls(void *platform); + +void elliptic_set_calibration_data(uint8_t *calib_data, size_t size); + +enum elliptic_system_configuration_parameter_type { + + ESCPT_SPEAKER_SCALING = 1, + ESCPT_CHANNEL_SENSITIVITY, + ESCPT_LATENCY, + ESCPT_MICROPHONE_INDEX, + ESCPT_OPERATION_MODE, + ESCPT_OPERATION_MODE_FLAGS, + ESCPT_COMPONENT_GAIN_CHANGE, + ESCPT_CALIBRATION_STATE, + ESCPT_ENGINE_VERSION, + ESCPT_CALIBRATION_PROFILE, + ESCPT_ULTRASOUND_GAIN, + ESCPT_LOG_LEVEL, + ESCPT_BUILD_BRANCH, //13 + + ESCPT_FSELECTION, + ESCPT_ENGINE_DIAGNOSTICS, + ESCPT_ENGINE_CUSTOM_SETTING_0, + ESCPT_ENGINE_CUSTOM_SETTING_1, + ESCPT_ENGINE_CUSTOM_SETTING_2, + ESCPT_ENGINE_CUSTOM_SETTING_3, + ESCPT_ENGINE_CUSTOM_SETTING_4, + ESCPT_ENGINE_CUSTOM_SETTING_5, + ESCPT_ENGINE_CUSTOM_SETTING_6, + ESCPT_ENGINE_CUSTOM_SETTING_7, + ESCPT_ENGINE_CUSTOM_SETTING_8, + ESCPT_ENGINE_CUSTOM_SETTING_9, + ESCPT_ENGINE_CUSTOM_SETTING_10, + ESCPT_ENGINE_CUSTOM_SETTING_11, + ESCPT_ENGINE_CUSTOM_SETTING_12, + ESCPT_ENGINE_CUSTOM_SETTING_13, + ESCPT_ENGINE_CUSTOM_SETTING_14, + ESCPT_ENGINE_CUSTOM_SETTING_15, + ESCPT_SUSPEND, // 32 + ESCPT_INPUT_ENABLED, + ESCPT_OUTPUT_ENABLED, + ESCPT_EXTERNAL_EVENT, + ESCPT_ENGINE_TAG, //36 + ESCPT_CALIBRATION_METHOD, + ESCPT_DEBUG_MODE, + ESCPT_NUMBER_OF_RUNS, + ESCPT_CONTEXT, + ESCPT_CAPTURE, + ESCPT_INPUT_CHANNELS, +}; + +struct elliptic_system_configuration_parameters_cache { + int32_t speaker_scaling[2]; + int32_t sensitivity; + int32_t latency; + int32_t microphone_index; + int32_t operation_mode; + int32_t operation_mode_flags; + int32_t component_gain_change; + int32_t calibration_state; + int32_t engine_version; + int32_t calibration_profile; + int32_t ultrasound_gain; + int32_t log_level; + int32_t custom_settings + [ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_COUNT]; + int32_t engine_suspend; + int32_t input_enabled; + int32_t output_enabled; + int32_t external_event; + int32_t calibration_method; + int32_t debug_mode; + int32_t number_of_runs; + int32_t context; + int32_t capture; + int32_t input_channels; +}; + +int elliptic_trigger_version_msg(void); + +int elliptic_trigger_branch_msg(void); + +int elliptic_trigger_tag_msg(void); + +int elliptic_trigger_diagnostics_msg(void); diff --git a/techpack/audio/include/elliptic/elliptic_sysfs.h b/techpack/audio/include/elliptic/elliptic_sysfs.h new file mode 100644 index 000000000000..def9e027d395 --- /dev/null +++ b/techpack/audio/include/elliptic/elliptic_sysfs.h @@ -0,0 +1,14 @@ +#pragma once + +#define ELLIPTIC_SYSFS_ENGINE_FOLDER "engine" +#define ELLIPTIC_SYSFS_ROOT_FOLDER "elliptic" +#define ELLIPTIC_SYSFS_CALIBRATION_FILENAME "calibration" +#define ELLIPTIC_SYSFS_VERSION_FILENAME "version" +#define ELLIPTIC_SYSFS_CALIBRATION_V2_FILENAME "calibration_v2" +#define ELLIPTIC_SYSFS_STATE_FILENAME "state" +#define ELLIPTIC_SYSFS_TAG_FILENAME "tag" +#define ELLIPTIC_SYSFS_OPMODE_FILENAME "opmode" +#define ELLIPTIC_SYSFS_OPMODE_FLAGS_FILENAME "opmode_flags" + +int elliptic_initialize_sysfs(void); +void elliptic_cleanup_sysfs(void); diff --git a/techpack/audio/include/mius/mius_data_io.h b/techpack/audio/include/mius/mius_data_io.h new file mode 100644 index 000000000000..6cce52797383 --- /dev/null +++ b/techpack/audio/include/mius/mius_data_io.h @@ -0,0 +1,155 @@ +/** +* Copyright MI 2015-2016 +* Copyright (C) 2019 XiaoMi, Inc. +* +*/ + +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +#define MIUS_DATA_IO_AP_TO_DSP 0 +#define MIUS_DATA_IO_DSP_TO_AP 1 + +#define MIUS_DATA_IO_READ_OK 0 +#define MIUS_DATA_IO_READ_BUSY 1 +#define MIUS_DATA_IO_READ_CANCEL 2 + +#define MIUS_MSG_BUF_SIZE 512 + +/* wake source timeout in ms*/ +#define MIUS_WAKEUP_TIMEOUT 250 + +#define MIUS_DATA_FIFO_SIZE (PAGE_SIZE) + +#define ULTRASOUND_RX_PORT_ID 0 +#define ULTRASOUND_TX_PORT_ID 1 + +/* MI UltraSound Module */ +#define MIUS_ULTRASOUND_DISABLE 0 +#define MIUS_ULTRASOUND_ENABLE 1 +#define MIUS_ULTRASOUND_SET_PARAMS 2 +#define MIUS_ULTRASOUND_GET_PARAMS 3 +#define MIUS_ULTRASOUND_RAMP_DOWN 4 + +/** Param ID definition */ +#define MIUS_ULTRASOUND_PARAM_ID_ENGINE_DATA 3 +#define MIUS_ULTRASOUND_PARAM_ID_CALIBRATION_DATA 11 +#define MIUS_ULTRASOUND_PARAM_ID_ENGINE_VERSION 12 +#define MIUS_ULTRASOUND_PARAM_ID_BUILD_BRANCH 14 +#define MIUS_ULTRASOUND_PARAM_ID_CALIBRATION_V2_DATA 15 +#define MIUS_ULTRASOUND_PARAM_ID_SENSORHUB 16 +#define MIUS_ULTRASOUND_PARAM_ID_DIAGNOSTICS_DATA 17 +#define MIUS_ULTRASOUND_PARAM_ID_TAG 18 +#define MIUS_ULTRASOUND_PARAM_ID_ML_DATA 19 + +#define MIUS_DATA_READ_BUSY 0 +#define MIUS_DATA_READ_OK 1 +#define MIUS_DATA_READ_CANCEL 2 + +#define MIUS_ALL_DEVICES -1 +#define MIUS_DEVICE_0 0 +#define MIUS_DEVICE_1 1 + +enum mius_message_id { + MIUS_MESSAGE_PAYLOAD, /* Input to AP*/ + MIUS_MESSAGE_RAW, /* Output from AP*/ + MIUS_MESSAGE_CALIBRATION, + MIUS_MESSAGE_CALIBRATION_V2, + MIUS_MESSAGE_DIAGNOSTICS, + MIUS_MAX_MESSAGE_IDS +}; + +typedef enum { + MIUS_DATA_PUSH_FROM_KERNEL, + MIUS_DATA_PUSH_FROM_USERSPACE +} mius_data_push_t; + +struct mius_data { + /* wake lock timeout */ + unsigned int wakeup_timeout; + + /* members for top half interrupt handling */ + struct kfifo fifo_isr; + spinlock_t fifo_isr_spinlock; + wait_queue_head_t fifo_isr_not_empty; + struct mutex user_buffer_lock; + + /* buffer to swap data from isr fifo to userspace */ + uint8_t isr_swap_buffer[MIUS_MSG_BUF_SIZE]; + + atomic_t abort_io; + + /* debug counters, reset between open/close */ + uint32_t isr_fifo_discard; + + /* debug counters, persistent */ + uint32_t isr_fifo_discard_total; + uint32_t userspace_read_total; + uint32_t isr_write_total; +}; + +/* Elliptic IO module API (implemented by IO module)*/ + +int mius_data_io_initialize(void); +int mius_data_io_cleanup(void); + +int32_t mius_data_io_write(uint32_t message_id, const char *data, + size_t data_size); + +int32_t mius_data_io_transact(uint32_t message_id, const char *data, + size_t data_size, char *output_data, + size_t output_data_size); + +/* Elliptic driver API (implemented by main driver)*/ +int mius_data_initialize(struct mius_data *, size_t max_queue_size, + unsigned int wakeup_timeout, int id); + +int mius_data_cleanup(struct mius_data *); + +void mius_data_reset_debug_counters(struct mius_data *); +void mius_data_update_debug_counters(struct mius_data *); +void mius_data_print_debug_counters(struct mius_data *); + +/* Called from mius device read */ +size_t mius_data_pop(struct mius_data *, char __user *buffer, + size_t buffer_size); + +/* Used for cancelling a blocking read */ +void mius_data_cancel(struct mius_data *); + +/* Called from IO module*/ +int mius_data_push(int deviceid, const char *buffer, size_t buffer_size, + mius_data_push_t); + +/* Writes to io module and user space control */ +int32_t mius_data_write(uint32_t message_id, const char *data, + size_t data_size); + +/* Opens port */ +int mius_open_port(int portid); + +/* Closes port */ +int mius_close_port(int portid); + +/* Opens port */ +int mius_io_open_port(int portid); + +/* Closes port */ +int mius_io_close_port(int portid); + +/* Create device node for userspace io driver*/ +int mius_userspace_io_driver_init(void); +void mius_userspace_io_driver_exit(void); + +/* Create device node for userspace io driver*/ +int mius_userspace_ctrl_driver_init(void); +void mius_userspace_ctrl_driver_exit(void); +int32_t mius_userspace_ctrl_write(uint32_t message_id, const char *data, + size_t data_size); diff --git a/techpack/audio/include/mius/mius_device.h b/techpack/audio/include/mius/mius_device.h new file mode 100644 index 000000000000..9559340bcad9 --- /dev/null +++ b/techpack/audio/include/mius/mius_device.h @@ -0,0 +1,49 @@ +/** + * Copyright MI + * Copyright (C) 2019 XiaoMi, Inc. + * + */ + +#pragma once + +#include +#include +#include +#include + +#define MIUS_DEVICENAME "mius" +#define MIUS_NUM_DEVICES 2 + +#define IOCTL_MIUS_APP 197 +#define MIRROR_TAG 0x3D0A4842 + +#define IOCTL_MIUS_DATA_IO_CANCEL _IO(IOCTL_MIUS_APP, 2) + +#define IOCTL_MIUS_ACTIVATE_ENGINE _IOW(IOCTL_MIUS_APP, 3, int) + +#define IOCTL_MIUS_SET_RAMP_DOWN _IO(IOCTL_MIUS_APP, 4) + +#define IOCTL_MIUS_SYSTEM_CONFIGURATION _IOW(IOCTL_MIUS_APP, 5, int) + +#define IOCTL_MIUS_DATA_IO_MIRROR _IOW(IOCTL_MIUS_APP, 117, unsigned char *) + +struct mius_device { + int opened; + struct cdev cdev; + struct semaphore sem; + struct mius_data el_data; +}; + +extern struct class *mius_class; + +#define MI_PRINT_E(string, arg...) \ + pr_err("[MIUS] : (%s) : " string "\n", __func__, ##arg) + +#define MI_PRINT_W(string, arg...) \ + pr_warn("[MIUS] : (%s) : " string "\n", __func__, ##arg) + +#define MI_PRINT_I(string, arg...) \ + pr_info("[MIUS] : (%s) : " string "\n", __func__, ##arg) + +#define MI_PRINT_D(string, arg...) \ + pr_debug("[MIUS] : (%s) : " string "\n", __func__, ##arg) diff --git a/techpack/audio/include/mius/mius_mixer_controls.h b/techpack/audio/include/mius/mius_mixer_controls.h new file mode 100644 index 000000000000..f79900aff8dc --- /dev/null +++ b/techpack/audio/include/mius/mius_mixer_controls.h @@ -0,0 +1,183 @@ +#pragma once +#include +#include +#include +#include + +#define MIUS_OBJ_ID_CALIBRATION_DATA 1 +#define MIUS_OBJ_ID_VERSION_INFO 2 +#define MIUS_OBJ_ID_BRANCH_INFO 3 +#define MIUS_OBJ_ID_CALIBRATION_V2_DATA 4 +#define MIUS_OBJ_ID_DIAGNOSTICS_DATA 5 +#define MIUS_OBJ_ID_TAG_INFO 6 +#define MIUS_OBJ_ID_ML_DATA 7 + +#define MIUS_SYSTEM_CONFIGURATION_SIZE 96 +#define MIUS_CALIBRATION_DATA_SIZE 64 +#define MIUS_CALIBRATION_V2_DATA_SIZE 448 +#define MIUS_DIAGNOSTICS_DATA_SIZE 448 +#define MIUS_DIAGNOSTICS_U32_DATA_VALUES (MIUS_DIAGNOSTICS_DATA_SIZE >> 2) +#define MIUS_SENSOR_DATA_SIZE 68 +#define MIUS_SENSOR_U32_DATA_VALUES (MIUS_SENSOR_DATA_SIZE >> 2) +#define MIUS_VERSION_INFO_SIZE 16 +#define MIUS_BRANCH_INFO_SIZE 32 +#define MIUS_BRANCH_INFO_MAX_SIZE 128 +#define MIUS_TAG_INFO_SIZE 32 +#define MIUS_ML_DATA_SIZE 432 + +#define MIUS_ULTRASOUND_DISABLE 0 +#define MIUS_ULTRASOUND_ENABLE 1 +#define MIUS_ULTRASOUND_SET_PARAMS 2 +#define MIUS_ULTRASOUND_GET_PARAMS 3 +#define MIUS_ULTRASOUND_RAMP_DOWN 4 + +/** register */ +#define MIUS_CALIBRATION 1 +/** bits */ +#define MIUS_CALIBRATION_STATE 0 +#define MIUS_CALIBRATION_PROFILE 1 +#define MIUS_ULTRASOUND_GAIN 2 + +/** custom settings */ +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_COUNT 16 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE 0x7FFFFFFF + +/** register */ +#define MIUS_SYSTEM_CONFIGURATION 0 +/** bits */ +#define MIUS_SYSTEM_CONFIGURATION_LATENCY 0 +#define MIUS_SYSTEM_CONFIGURATION_SENSITIVITY 1 +#define MIUS_SYSTEM_CONFIGURATION_SPEAKER_SCALING 2 +#define MIUS_SYSTEM_CONFIGURATION_MICROPHONE_INDEX 3 +#define MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE 4 +#define MIUS_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS 5 +#define MIUS_SYSTEM_CONFIGURATION_LOG_LEVEL 6 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0 7 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_1 8 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_2 9 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_3 10 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_4 11 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_5 12 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_6 13 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_7 14 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_8 15 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_9 16 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_10 17 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_11 18 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_12 19 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_13 20 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_14 21 +#define MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15 22 + +#define MIUS_SYSTEM_CONFIGURATION_SUSPEND 23 +#define MIUS_SYSTEM_CONFIGURATION_INPUT_ENABLED 24 +#define MIUS_SYSTEM_CONFIGURATION_OUTPUT_ENABLED 25 +#define MIUS_SYSTEM_CONFIGURATION_EXTERNAL_EVENT 26 +#define MIUS_SYSTEM_CONFIGURATION_CALIBRATION_METHOD 27 +#define MIUS_SYSTEM_CONFIGURATION_DEBUG_MODE 28 +#define MIUS_SYSTEM_CONFIGURATION_NUMBER_OF_RUNS 29 +#define MIUS_SYSTEM_CONFIGURATION_CONTEXT 30 +#define MIUS_SYSTEM_CONFIGURATION_CAPTURE 31 +#define MIUS_SYSTEM_CONFIGURATION_INPUT_CHANNELS 32 + +#define MIUS_SYSTEM_CONFIGURATION_MAX_CONTEXT_VALUE 0x7FFFFFFF + +struct mius_engine_version_info { + uint32_t major; + uint32_t minor; + uint32_t build; + uint32_t revision; +}; + +struct mius_shared_data_block { + uint32_t object_id; + size_t size; + void *buffer; +}; + +struct mius_shared_data_block *mius_get_shared_obj(uint32_t object_id); + +extern unsigned int mius_add_platform_controls(void *platform); + +void mius_set_calibration_data(uint8_t *calib_data, size_t size); + +enum mius_system_configuration_parameter_type { + + MSC_SPEAKER_SCALING = 1, + MSC_CHANNEL_SENSITIVITY, + MSC_LATENCY, + MSC_MICROPHONE_INDEX, + MSC_OPERATION_MODE, + MSC_OPERATION_MODE_FLAGS, + MSC_COMPONENT_GAIN_CHANGE, + MSC_CALIBRATION_STATE, + MSC_ENGINE_VERSION, + MSC_CALIBRATION_PROFILE, + MSC_ULTRASOUND_GAIN, + MSC_LOG_LEVEL, + MSC_BUILD_BRANCH, //13 + + MSC_FSELECTION, + MSC_ENGINE_DIAGNOSTICS, + MSC_ENGINE_CUSTOM_SETTING_0, + MSC_ENGINE_CUSTOM_SETTING_1, + MSC_ENGINE_CUSTOM_SETTING_2, + MSC_ENGINE_CUSTOM_SETTING_3, + MSC_ENGINE_CUSTOM_SETTING_4, + MSC_ENGINE_CUSTOM_SETTING_5, + MSC_ENGINE_CUSTOM_SETTING_6, + MSC_ENGINE_CUSTOM_SETTING_7, + MSC_ENGINE_CUSTOM_SETTING_8, + MSC_ENGINE_CUSTOM_SETTING_9, + MSC_ENGINE_CUSTOM_SETTING_10, + MSC_ENGINE_CUSTOM_SETTING_11, + MSC_ENGINE_CUSTOM_SETTING_12, + MSC_ENGINE_CUSTOM_SETTING_13, + MSC_ENGINE_CUSTOM_SETTING_14, + MSC_ENGINE_CUSTOM_SETTING_15, + MSC_SUSPEND, // 32 + MSC_INPUT_ENABLED, + MSC_OUTPUT_ENABLED, + MSC_EXTERNAL_EVENT, + MSC_ENGINE_TAG, //36 + MSC_CALIBRATION_METHOD, + MSC_DEBUG_MODE, + MSC_NUMBER_OF_RUNS, + MSC_CONTEXT, + MSC_CAPTURE, + MSC_INPUT_CHANNELS, +}; + +struct mius_system_configuration_parameters_cache { + int32_t speaker_scaling[2]; + int32_t sensitivity; + int32_t latency; + int32_t microphone_index; + int32_t operation_mode; + int32_t operation_mode_flags; + int32_t component_gain_change; + int32_t calibration_state; + int32_t engine_version; + int32_t calibration_profile; + int32_t ultrasound_gain; + int32_t log_level; + int32_t custom_settings[MIUS_SYSTEM_CONFIGURATION_CUSTOM_SETTING_COUNT]; + int32_t engine_suspend; + int32_t input_enabled; + int32_t output_enabled; + int32_t external_event; + int32_t calibration_method; + int32_t debug_mode; + int32_t number_of_runs; + int32_t context; + int32_t capture; + int32_t input_channels; +}; + +int mius_trigger_version_msg(void); + +int mius_trigger_branch_msg(void); + +int mius_trigger_tag_msg(void); + +int mius_trigger_diagnostics_msg(void); diff --git a/techpack/audio/include/mius/mius_sysfs.h b/techpack/audio/include/mius/mius_sysfs.h new file mode 100644 index 000000000000..7f850c67e5c3 --- /dev/null +++ b/techpack/audio/include/mius/mius_sysfs.h @@ -0,0 +1,14 @@ +#pragma once + +#define MIUS_SYSFS_ENGINE_FOLDER "engine" +#define MIUS_SYSFS_ROOT_FOLDER "mius" +#define MIUS_SYSFS_CALIBRATION_FILENAME "calibration" +#define MIUS_SYSFS_VERSION_FILENAME "version" +#define MIUS_SYSFS_CALIBRATION_V2_FILENAME "calibration_v2" +#define MIUS_SYSFS_STATE_FILENAME "state" +#define MIUS_SYSFS_TAG_FILENAME "tag" +#define MIUS_SYSFS_OPMODE_FILENAME "opmode" +#define MIUS_SYSFS_OPMODE_FLAGS_FILENAME "opmode_flags" + +int mius_initialize_sysfs(void); +void mius_cleanup_sysfs(void); diff --git a/techpack/audio/include/uapi/sound/cs35l41.h b/techpack/audio/include/uapi/sound/cs35l41.h new file mode 100644 index 000000000000..39f6df1a17ba --- /dev/null +++ b/techpack/audio/include/uapi/sound/cs35l41.h @@ -0,0 +1,84 @@ +/* + * linux/sound/cs35l41.h -- Platform data for CS35L41 + * + * Copyright (c) 2018 Cirrus Logic Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __CS35L41_H +#define __CS35L41_H + +struct classh_cfg { + bool classh_bst_override; + bool classh_algo_enable; + int classh_bst_max_limit; + int classh_mem_depth; + int classh_release_rate; + int classh_headroom; + int classh_wk_fet_delay; + int classh_wk_fet_thld; +}; + +struct irq_cfg { + bool is_present; + bool irq_pol_inv; + bool irq_out_en; + int irq_src_sel; +}; + +struct cs35l41_platform_data { + bool sclk_frc; + bool lrclk_frc; + bool right_channel; + bool amp_gain_zc; + bool ng_enable; + int bst_ind; + int bst_vctrl; + int bst_ipk; + int bst_cap; + int temp_warn_thld; + int ng_pcm_thld; + int ng_delay; + int dout_hiz; + struct irq_cfg irq_config1; + struct irq_cfg irq_config2; + struct classh_cfg classh_config; + int mnSpkType; + struct device_node *spk_id_gpio_p; +}; + +struct cs35l41_private { + struct wm_adsp dsp; /* needs to be first member */ + struct snd_soc_codec *codec; + struct cs35l41_platform_data pdata; + struct device *dev; + struct regmap *regmap; + struct regulator_bulk_data supplies[2]; + int num_supplies; + int irq; + int clksrc; + int extclk_freq; + int extclk_cfg; + int sclk; + unsigned int cspl_cmd; + bool dspa_mode; + bool i2s_mode; + bool swire_mode; + bool halo_booted; + bool bus_spi; + /* GPIO for /RST */ + //struct gpio_desc *reset_gpio; + int reset_gpio; + struct completion global_pup_done; + struct completion global_pdn_done; + struct completion mbox_cmd; +}; + +int cs35l41_probe(struct cs35l41_private *cs35l41, + struct cs35l41_platform_data *pdata); +int spk_id_get(struct device_node *np); +#endif /* __CS35L41_H */ diff --git a/techpack/audio/include/uapi/sound/cs35l41_v2.h b/techpack/audio/include/uapi/sound/cs35l41_v2.h new file mode 100644 index 000000000000..e5bb86a795be --- /dev/null +++ b/techpack/audio/include/uapi/sound/cs35l41_v2.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* + * linux/sound/cs35l41.h -- Platform data for CS35L41 + * + * Copyright (c) 2018 Cirrus Logic Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __CS35L41_H +#define __CS35L41_H + +struct classh_cfg { + bool classh_bst_override; + bool classh_algo_enable; + int classh_bst_max_limit; + int classh_mem_depth; + int classh_release_rate; + int classh_headroom; + int classh_wk_fet_delay; + int classh_wk_fet_thld; +}; + +struct irq_cfg { + bool is_present; + bool irq_pol_inv; + bool irq_out_en; + int irq_src_sel; +}; + +struct cs35l41_platform_data { + bool sclk_frc; + bool lrclk_frc; + bool right_channel; + bool amp_gain_zc; + bool dsp_ng_enable; + bool tuning_has_prefix; + bool invert_pcm; + bool hibernate_enable; + bool fwname_use_revid; + int bst_ind; + int bst_vctrl; + int bst_ipk; + int bst_cap; + int temp_warn_thld; + int dsp_ng_pcm_thld; + int dsp_ng_delay; + unsigned int hw_ng_sel; + unsigned int hw_ng_delay; + unsigned int hw_ng_thld; + int dout_hiz; + struct irq_cfg irq_config1; + struct irq_cfg irq_config2; + struct classh_cfg classh_config; +}; + +struct cs35l41_rst_cache { + bool extclk_cfg; + int asp_width; + int asp_wl; + int asp_fmt; + int lrclk_fmt; + int sclk_fmt; + int slave_mode; + int fs_cfg; +}; + +struct cs35l41_vol_ctl { + struct workqueue_struct *ramp_wq; + struct work_struct ramp_work; + struct mutex vol_mutex; /* Protect set volume */ + atomic_t manual_ramp; /* boolean */ + atomic_t ramp_abort; /* boolean */ + atomic_t vol_ramp; /* boolean */ + atomic_t playback; /* boolean */ + int ramp_init_att; + int ramp_knee_att; + unsigned int ramp_knee_time; + unsigned int ramp_end_time; + int dig_vol; + unsigned int auto_ramp_timeout; + unsigned int output_dev; + unsigned int prev_active_dev; + ktime_t dev_timestamp; +}; + +struct cs35l41_private { + struct wm_adsp dsp; /* needs to be first member */ + struct snd_soc_codec *codec; + struct cs35l41_platform_data pdata; + struct device *dev; + struct regmap *regmap; + struct regulator_bulk_data supplies[2]; + int num_supplies; + int irq; + int clksrc; + int extclk_freq; + int extclk_cfg; + int sclk; + int lrclk_fmt; + int sclk_fmt; + int amp_hibernate; + bool reload_tuning; + bool dspa_mode; + bool i2s_mode; + bool swire_mode; + bool halo_booted; + bool skip_codec_probe; + bool bus_spi; + bool fast_switch_en; + bool force_int; + bool hibernate_force_wake; + /* GPIO for /RST */ + struct gpio_desc *reset_gpio; + /* Run-time mixer */ + unsigned int fast_switch_file_idx; + struct soc_enum fast_switch_enum; + const char **fast_switch_names; + struct delayed_work hb_work; + struct workqueue_struct *wq; + struct mutex hb_lock; + struct cs35l41_rst_cache reset_cache; + struct mutex rate_lock; + struct mutex force_int_lock; + struct cs35l41_vol_ctl vol_ctl; + unsigned int ctl_cache[CS35L41_CTRL_CACHE_SIZE]; + u32 trim_cache[CS35L41_TRIM_CACHE_SIZE]; +}; + +int cs35l41_probe(struct cs35l41_private *cs35l41, + struct cs35l41_platform_data *pdata); +int cs35l41_remove(struct cs35l41_private *cs35l41); + +#endif /* __CS35L41_H */ diff --git a/techpack/audio/include/uapi/sound/msm-cirrus-playback.h b/techpack/audio/include/uapi/sound/msm-cirrus-playback.h new file mode 100644 index 000000000000..825a03fb5122 --- /dev/null +++ b/techpack/audio/include/uapi/sound/msm-cirrus-playback.h @@ -0,0 +1,119 @@ +/* Copyright (c) 2016 Cirrus Logic, Inc. + * Copyright (C) 2019 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _UAPI_MSM_CIRRUS_SPK_PR_H +#define _UAPI_MSM_CIRRUS_SPK_PR_H + +#include +#include + +#define CIRRUS_SP 0x10027053 +#define CIRRUS_SP_ENABLE 0x10002001 + +#define CRUS_MODULE_ID_TX 0x00000002 +#define CRUS_MODULE_ID_RX 0x00000001 + +/* + * CRUS_PARAM_RX/TX_SET_USECASE + * 0 = Music Playback in firmware + * 1 = VOICE Playback in firmware + * 2 = Tuning file loaded using external + * config load command + * + * uses crus_rx_run_case_ctrl for RX apr pckt + * uses crus_single_data_ctrl for TX apr pckt + * + */ +#define CRUS_PARAM_RX_SET_USECASE 0x00A1AF02 +#define CRUS_PARAM_TX_SET_USECASE 0x00A1BF0A +/* + * CRUS_PARAM_RX/TX_SET_CALIB + * Non-zero value to run speaker + * calibration sequence + * + * uses crus_single_data_t apr pckt + */ +#define CRUS_PARAM_RX_SET_CALIB 0x00A1AF03 +#define CRUS_PARAM_TX_SET_CALIB 0x00A1BF03 +/* + * CRUS_PARAM_RX/TX_SET_EXT_CONFIG + * config string loaded from libfirmware + * max of 7K paramters + * + * uses crus_external_config_t apr pckt + */ +#define CRUS_PARAM_RX_SET_EXT_CONFIG 0x00A1AF05 +#define CRUS_PARAM_TX_SET_EXT_CONFIG 0x00A1BF08 +/* + * CRUS_PARAM_RX_GET_TEMP + * get current Temp and calibration data + * + * CRUS_PARAM_TX_GET_TEMP_CAL + * get results of calibration sequence + * + * uses cirrus_cal_result_t apr pckt + */ +#define CRUS_PARAM_RX_GET_TEMP 0x00A1AF07 +#define CRUS_PARAM_TX_GET_TEMP_CAL 0x00A1BF06 +/* + * CRUS_PARAM_RX_SET_DELTA_CONFIG + * load seamless transition config string + * + * CRUS_PARAM_RX_RUN_DELTA_CONFIG + * execute the loaded seamless transition + */ +#define CRUS_PARAM_RX_SET_DELTA_CONFIG 0x00A1AF0D +#define CRUS_PARAM_RX_RUN_DELTA_CONFIG 0x00A1AF0E +/* + * CRUS_PARAM_RX_CHANNEL_SWAP + * initiate l/r channel swap transition + */ +#define CRUS_PARAM_RX_CHANNEL_SWAP 0x00A1AF12 +#define CRUS_PARAM_RX_GET_CHANNEL_SWAP 0x00A1AF13 +/* + * CRUS_PARAM_RX_SET_ATTENUATION + * set volume attenuation in volume control blocks 1 & 2 + */ +#define CRUS_PARAM_RX_SET_ATTENUATION 0x00A1AF0A +#define CRUS_AFE_PARAM_ID_ENABLE 0x00010203 + +#define SPK_PROT_IOCTL_MAGIC 'a' + +#define CRUS_SP_IOCTL_GET _IOWR(SPK_PROT_IOCTL_MAGIC, 219, void *) +#define CRUS_SP_IOCTL_SET _IOWR(SPK_PROT_IOCTL_MAGIC, 220, void *) +#define CRUS_SP_IOCTL_GET_CALIB _IOWR(SPK_PROT_IOCTL_MAGIC, 221, void *) +#define CRUS_SP_IOCTL_SET_CALIB _IOWR(SPK_PROT_IOCTL_MAGIC, 222, void *) +#define CRUS_SP_IOCTL_READ_CALIB_FROM_SLOT \ + _IOWR(SPK_PROT_IOCTL_MAGIC, 223, void *) +#define CRUS_SP_IOCTL_WRITE_CALIB_TO_SLOT \ + _IOWR(SPK_PROT_IOCTL_MAGIC, 224, void *) + +#define CRUS_SP_IOCTL_GET32 _IOWR(SPK_PROT_IOCTL_MAGIC, 219, compat_uptr_t) +#define CRUS_SP_IOCTL_SET32 _IOWR(SPK_PROT_IOCTL_MAGIC, 220, compat_uptr_t) +#define CRUS_SP_IOCTL_GET_CALIB32 \ + _IOWR(SPK_PROT_IOCTL_MAGIC, 221, compat_uptr_t) +#define CRUS_SP_IOCTL_SET_CALIB32 \ + _IOWR(SPK_PROT_IOCTL_MAGIC, 222, compat_uptr_t) +#define CRUS_SP_IOCTL_READ_CALIB_FROM_SLOT32 \ + _IOWR(SPK_PROT_IOCTL_MAGIC, 223, compat_uptr_t) +#define CRUS_SP_IOCTL_WRITE_CALIB_TO_SLOT32 \ + _IOWR(SPK_PROT_IOCTL_MAGIC, 224, compat_uptr_t) + +struct crus_sp_ioctl_header { + uint32_t size; + uint32_t module_id; + uint32_t param_id; + uint32_t data_length; + void *data; +}; + +#endif /* _UAPI_MSM_CIRRUS_SPK_PR_H */ From b85b66accf32e9ff2176390e2e6c224aa1f23607 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Thu, 8 Jul 2021 21:06:13 +0200 Subject: [PATCH 101/226] techpack: audio: asoc: codecs: tas256x: Shut up Change-Id: I4beed107b75999e6f909467062bccb0a0e3229eb Signed-off-by: firebird11 --- techpack/audio/asoc/codecs/tas256x/tas256x-codec.c | 1 + techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c | 1 + techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c | 1 + techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c | 1 + techpack/audio/asoc/codecs/tas256x/tas25xx-debug.h | 9 +++++++++ 5 files changed, 13 insertions(+) create mode 100644 techpack/audio/asoc/codecs/tas256x/tas25xx-debug.h diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x-codec.c b/techpack/audio/asoc/codecs/tas256x/tas256x-codec.c index b95e7e03a3ca..6bb7bf9b5966 100644 --- a/techpack/audio/asoc/codecs/tas256x/tas256x-codec.c +++ b/techpack/audio/asoc/codecs/tas256x/tas256x-codec.c @@ -53,6 +53,7 @@ #endif /*CONFIG_PLATFORM_EXYNOS*/ #include "tas25xx-calib.h" #endif /*CONFIG_TAS25XX_ALGO*/ +#include "tas25xx-debug.h" #define TAS256X_MDELAY 0xFFFFFFFE #define TAS256X_MSLEEP 0xFFFFFFFD diff --git a/techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c b/techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c index 02f8090cbf13..4f817d9add70 100644 --- a/techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c +++ b/techpack/audio/asoc/codecs/tas256x/tas256x-regmap.c @@ -42,6 +42,7 @@ #include "tas2564.h" #include "tas256x-device.h" #include "tas256x-codec.h" +#include "tas25xx-debug.h" #ifdef CONFIG_TAS25XX_ALGO #ifdef CONFIG_PLATFORM_EXYNOS diff --git a/techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c b/techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c index 4da82e22090d..90f01be0e431 100644 --- a/techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c +++ b/techpack/audio/asoc/codecs/tas256x/tas25xx-algo.c @@ -4,6 +4,7 @@ #include #include #include "tas25xx-calib.h" +#include "tas25xx-debug.h" #define USE_VFS 1 #define CODEC_CONTROL 1 diff --git a/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c b/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c index 862025d74c0b..b1b21f92c75c 100644 --- a/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c +++ b/techpack/audio/asoc/codecs/tas256x/tas25xx-calib.c @@ -32,6 +32,7 @@ #include #include #include +#include "tas25xx-debug.h" /* Holds the Packet data required for processing */ struct tas_dsp_pkt { diff --git a/techpack/audio/asoc/codecs/tas256x/tas25xx-debug.h b/techpack/audio/asoc/codecs/tas256x/tas25xx-debug.h new file mode 100644 index 000000000000..87a11a717e93 --- /dev/null +++ b/techpack/audio/asoc/codecs/tas256x/tas25xx-debug.h @@ -0,0 +1,9 @@ +//#define DEBUG + +#ifndef DEBUG +#undef dev_info +#undef pr_info + +#define dev_info(...) dev_dbg(__VA_ARGS__) +#define pr_info(...) pr_debug(__VA_ARGS__) +#endif From 5ebd6f21875deed7ed1d144cf95a0ac2541a8e91 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 17 Apr 2024 17:22:40 +0200 Subject: [PATCH 102/226] techpack: audio: asoc: codecs: tfa98xx: Fix includes Change-Id: If34b42dc06c36b9663b8422ee6d2746d4f54b285 Signed-off-by: firebird11 --- techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c | 12 ++++++------ .../audio/asoc/codecs/tfa98xx/src/tfa_container.c | 10 +++++----- techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c | 6 +++--- techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c | 10 +++++----- techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c | 10 +++++----- 5 files changed, 24 insertions(+), 24 deletions(-) diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c index f5542c15adb6..f66ad24493fe 100644 --- a/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c @@ -32,15 +32,15 @@ #include #include #include -#include "config.h" -#include "tfa98xx.h" -#include "tfa.h" -#include "tfa_dsp_fw.h" +#include "../inc/config.h" +#include "../inc/tfa98xx.h" +#include "../inc/tfa.h" +#include "../inc/tfa_dsp_fw.h" /* required for enum tfa9912_irq */ -#include "tfa98xx_tfafieldnames.h" +#include "../inc/tfa98xx_tfafieldnames.h" -#include "spk-id.h" +#include "../inc/spk-id.h" #define TFA98XX_VERSION TFA98XX_API_REV_STR diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c index 7207069dacc2..284dfa6cbbb0 100644 --- a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_container.c @@ -15,11 +15,11 @@ * limitations under the License. */ -#include "dbgprint.h" -#include "tfa_container.h" -#include "tfa.h" -#include "tfa98xx_tfafieldnames.h" -#include "tfa_internal.h" +#include "../inc/dbgprint.h" +#include "../inc/tfa_container.h" +#include "../inc/tfa.h" +#include "../inc/tfa98xx_tfafieldnames.h" +#include "../inc/tfa_internal.h" /* defines */ #define MODULE_BIQUADFILTERBANK 2 diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c index b02098326cb2..d04309791ded 100644 --- a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_debug.c @@ -15,9 +15,9 @@ * limitations under the License. */ -#include "dbgprint.h" -#include "tfa_service.h" -#include "tfa98xx_tfafieldnames.h" +#include "../inc/dbgprint.h" +#include "../inc/tfa_service.h" +#include "../inc/tfa98xx_tfafieldnames.h" /* support for error code translation into text */ static char latest_errorstr[64]; diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c index eb4045710829..f875e15bddc2 100644 --- a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_dsp.c @@ -15,11 +15,11 @@ * limitations under the License. */ -#include "dbgprint.h" -#include "tfa_container.h" -#include "tfa.h" -#include "tfa98xx_tfafieldnames.h" -#include "tfa_internal.h" +#include "../inc/dbgprint.h" +#include "../inc/tfa_container.h" +#include "../inc/tfa.h" +#include "../inc/tfa98xx_tfafieldnames.h" +#include "../inc/tfa_internal.h" #ifdef __KERNEL__ #ifdef pr_fmt diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c index 8bd5167f889a..164514c91cbb 100644 --- a/techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa_init.c @@ -15,11 +15,11 @@ * limitations under the License. */ -#include "dbgprint.h" -#include "tfa_service.h" -#include "tfa_internal.h" -#include "tfa_container.h" -#include "tfa98xx_tfafieldnames.h" +#include "../inc/dbgprint.h" +#include "../inc/tfa_service.h" +#include "../inc/tfa_internal.h" +#include "../inc/tfa_container.h" +#include "../inc/tfa98xx_tfafieldnames.h" /* The CurrentSense4 registers are not in the datasheet */ #define TFA98XX_CURRENTSENSE4_CTRL_CLKGATECFOFF (1 << 2) From e8bcaae5c315a82243a678ac92976e987bbea6af Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 9 Jun 2024 19:19:36 +0200 Subject: [PATCH 103/226] techpack: audio: asoc: codecs: tfa98xx: Make it compile without debugfs Change-Id: Ia04686616f8f2b0b5fa5eb810025811970d624d5 Signed-off-by: firebird11 --- .../audio/asoc/codecs/tfa98xx/src/tfa98xx.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c index f66ad24493fe..384d2e54b07a 100644 --- a/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c @@ -404,6 +404,15 @@ static void tfa98xx_inputdev_unregister(struct tfa98xx *tfa98xx) __tfa98xx_inputdev_check_register(tfa98xx, true); } +#ifdef TFA_NON_DSP_SOLUTION +extern int send_tfa_cal_apr(void *buf, int cmd_size, bool bRead); +#else +int send_tfa_cal_apr(void *buf, int cmd_size, bool bRead) +{ + return 0; +} +#endif + #ifdef CONFIG_DEBUG_FS /* OTC reporting * Returns the MTP0 OTC bit value @@ -765,15 +774,6 @@ static ssize_t tfa98xx_dbgfs_fw_state_get(struct file *file, return simple_read_from_buffer(user_buf, count, ppos, str, strlen(str)); } -#ifdef TFA_NON_DSP_SOLUTION -extern int send_tfa_cal_apr(void *buf, int cmd_size, bool bRead); -#else -int send_tfa_cal_apr(void *buf, int cmd_size, bool bRead) -{ - return 0; -} -#endif - static ssize_t tfa98xx_dbgfs_rpc_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { From 1e5bd8aa016e2512689b89b253638209a6326344 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sun, 9 Jun 2024 19:21:31 +0200 Subject: [PATCH 104/226] techpack: audio: asoc: codecs: Use spk-id standard driver Change-Id: I4093c026405398b752b183bc4a8639e3eccf49fc Signed-off-by: firebird11 --- techpack/audio/asoc/codecs/cs35l41/cs35l41.c | 28 ---------------- .../audio/asoc/codecs/tas2557/tas2557-core.c | 28 ---------------- .../audio/asoc/codecs/tas2557/tas2557-core.h | 1 - .../asoc/codecs/tas2557/tas2557-regmap.c | 2 +- .../audio/asoc/codecs/tfa98xx/inc/spk-id.h | 33 ------------------- .../audio/asoc/codecs/tfa98xx/src/tfa98xx.c | 2 +- techpack/audio/include/uapi/sound/cs35l41.h | 1 - 7 files changed, 2 insertions(+), 93 deletions(-) delete mode 100644 techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h diff --git a/techpack/audio/asoc/codecs/cs35l41/cs35l41.c b/techpack/audio/asoc/codecs/cs35l41/cs35l41.c index 47150d81329d..89b542efb9df 100644 --- a/techpack/audio/asoc/codecs/cs35l41/cs35l41.c +++ b/techpack/audio/asoc/codecs/cs35l41/cs35l41.c @@ -1583,34 +1583,6 @@ static struct snd_soc_codec_driver soc_codec_dev_cs35l41 = { .idle_bias_off = true, }; -int spk_id_get(struct device_node *np) -{ - int id; - int state; - - state = spk_id_get_pin_3state(np); - if (state < 0) { - pr_err("%s: Can not get id pin state, %d\n", __func__, state); - return VENDOR_ID_NONE; - } - - switch (state) { - case PIN_PULL_DOWN: - id = VENDOR_ID_AAC; - break; - case PIN_PULL_UP: - id = VENDOR_ID_UNKNOWN; - break; - case PIN_FLOAT: - id = VENDOR_ID_GOER; - break; - default: - id = VENDOR_ID_UNKNOWN; - break; - } - return id; -} - static int cs35l41_handle_of_data(struct device *dev, struct cs35l41_platform_data *pdata) { diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-core.c b/techpack/audio/asoc/codecs/tas2557/tas2557-core.c index 45f6e9b3264e..5eaa3bdcba49 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-core.c +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-core.c @@ -2309,34 +2309,6 @@ bool tas2557_get_Cali_prm_r0(struct tas2557_priv *pTAS2557, int *prm_r0) return bFound; } -int spk_id_get(struct device_node *np) -{ - int id; - int state; - - state = spk_id_get_pin_3state(np); - if (state < 0) { - pr_err("%s: Can not get id pin state, %d\n", __func__, state); - return VENDOR_ID_NONE; - } - - switch (state) { - case PIN_PULL_DOWN: - id = VENDOR_ID_AAC; - break; - case PIN_PULL_UP: - id = VENDOR_ID_UNKNOWN; - break; - case PIN_FLOAT: - id = VENDOR_ID_GOER; - break; - default: - id = VENDOR_ID_UNKNOWN; - break; - } - return id; -} - int tas2557_parse_dt(struct device *dev, struct tas2557_priv *pTAS2557) { struct device_node *np = dev->of_node; diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-core.h b/techpack/audio/asoc/codecs/tas2557/tas2557-core.h index 95a544f45547..a3e6df6e36f2 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-core.h +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-core.h @@ -81,6 +81,5 @@ int tas2557_parse_dt(struct device *dev, struct tas2557_priv *pTAS2557); int tas2557_get_DAC_gain(struct tas2557_priv *pTAS2557, unsigned char *pnGain); int tas2557_set_DAC_gain(struct tas2557_priv *pTAS2557, unsigned int nGain); int tas2557_configIRQ(struct tas2557_priv *pTAS2557); -int spk_id_get(struct device_node *np); #endif /* _TAS2557_CORE_H */ diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c b/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c index 9923660efa97..2f66744d8cfd 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c @@ -56,7 +56,7 @@ #ifdef ENABLE_TILOAD #include "tiload.h" #endif -#include "../spk-id.h" +#include #define LOW_TEMPERATURE_GAIN 6 #define LOW_TEMPERATURE_COUNTER 12 diff --git a/techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h b/techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h deleted file mode 100644 index 8303b93c3498..000000000000 --- a/techpack/audio/asoc/codecs/tfa98xx/inc/spk-id.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SPK_ID_H_ -#define __SPK_ID_H_ - -#include -#include - -#define PIN_PULL_DOWN 0 -#define PIN_PULL_UP 1 -#define PIN_FLOAT 2 - -#define VENDOR_ID_NONE 0 -#define VENDOR_ID_AAC 1 -#define VENDOR_ID_SSI 2 -#define VENDOR_ID_GOER 3 - -#define VENDOR_ID_UNKNOWN 4 - -extern int spk_id_get_pin_3state(struct device_node *np); - -#endif diff --git a/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c index 384d2e54b07a..d6f094725000 100644 --- a/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c +++ b/techpack/audio/asoc/codecs/tfa98xx/src/tfa98xx.c @@ -40,7 +40,7 @@ /* required for enum tfa9912_irq */ #include "../inc/tfa98xx_tfafieldnames.h" -#include "../inc/spk-id.h" +#include #define TFA98XX_VERSION TFA98XX_API_REV_STR diff --git a/techpack/audio/include/uapi/sound/cs35l41.h b/techpack/audio/include/uapi/sound/cs35l41.h index 39f6df1a17ba..17d02a568dd3 100644 --- a/techpack/audio/include/uapi/sound/cs35l41.h +++ b/techpack/audio/include/uapi/sound/cs35l41.h @@ -80,5 +80,4 @@ struct cs35l41_private { int cs35l41_probe(struct cs35l41_private *cs35l41, struct cs35l41_platform_data *pdata); -int spk_id_get(struct device_node *np); #endif /* __CS35L41_H */ From 9cbd018a8f1ea01d832ca5957ea81e6b397e6310 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Wed, 17 Apr 2024 13:09:41 +0200 Subject: [PATCH 105/226] techpack: audio: Import Xiaomi changes Change-Id: I52e78d6fe17834ffecf5cd269b07b1bd53d9790d Signed-off-by: firebird11 --- techpack/audio/asoc/Kbuild | 8 + techpack/audio/asoc/codecs/bolero/tx-macro.c | 8 + techpack/audio/asoc/codecs/wcd-dsp-mgr.c | 56 ++ techpack/audio/asoc/codecs/wcd-mbhc-adc.c | 36 + techpack/audio/asoc/codecs/wcd-mbhc-v2.c | 243 +++++ techpack/audio/asoc/codecs/wcd-mbhc-v2.h | 37 + techpack/audio/asoc/codecs/wcd-spi.c | 18 + .../audio/asoc/codecs/wcd934x/wcd934x-mbhc.c | 32 + .../audio/asoc/codecs/wcd934x/wcd934x-mbhc.h | 11 + techpack/audio/asoc/codecs/wcd934x/wcd934x.c | 88 ++ techpack/audio/asoc/codecs/wcd937x/internal.h | 3 + techpack/audio/asoc/codecs/wcd937x/wcd937x.c | 14 + .../audio/asoc/codecs/wcd9xxx-common-v2.c | 3 + techpack/audio/asoc/msm-compress-q6-v2.c | 14 + techpack/audio/asoc/msm-dai-fe.c | 66 ++ techpack/audio/asoc/msm-dai-q6-v2.c | 25 + techpack/audio/asoc/msm-pcm-loopback-v2.c | 6 + techpack/audio/asoc/msm-pcm-q6-v2.c | 6 + techpack/audio/asoc/msm-pcm-routing-v2.c | 188 ++++ techpack/audio/asoc/msm-pcm-routing-v2.h | 3 + techpack/audio/asoc/sm8150.c | 557 +++++++++++ techpack/audio/dsp/Kbuild | 8 + techpack/audio/dsp/q6_init.c | 22 + techpack/audio/dsp/q6_init.h | 22 + techpack/audio/dsp/q6adm.c | 180 ++++ techpack/audio/dsp/q6afe.c | 925 ++++++++++++++++++ techpack/audio/dsp/q6asm.c | 8 + techpack/audio/dsp/q6audio-v2.c | 7 + techpack/audio/dsp/q6voice.c | 4 + techpack/audio/include/dsp/apr_audio-v2.h | 5 +- techpack/audio/include/dsp/q6afe-v2.h | 10 + techpack/audio/soc/pinctrl-lpi.c | 5 + techpack/audio/soc/swr-mstr-ctrl.c | 18 + techpack/audio/soc/swr-mstr-ctrl.h | 3 + 34 files changed, 2638 insertions(+), 1 deletion(-) diff --git a/techpack/audio/asoc/Kbuild b/techpack/audio/asoc/Kbuild index 164cce6a2542..c93a95c5cfd7 100644 --- a/techpack/audio/asoc/Kbuild +++ b/techpack/audio/asoc/Kbuild @@ -186,6 +186,14 @@ CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ -Werror\ -D__linux__ +ifeq (y, $(filter y,$(CONFIG_MACH_XIAOMI_CEPHEUS))) + CDEFINES += -DCONFIG_SND_SOC_CS35L41_FOR_CEPH +endif + +ifeq (y, $(filter y,$(CONFIG_MACH_XIAOMI_RAPHAEL))) + CDEFINES += -DCONFIG_SND_SOC_TFA9874_FOR_DAVI +endif + KBUILD_CPPFLAGS += $(CDEFINES) # Currently, for versions of gcc which support it, the kernel Makefile diff --git a/techpack/audio/asoc/codecs/bolero/tx-macro.c b/techpack/audio/asoc/codecs/bolero/tx-macro.c index 8fc8a2ad23d3..9f9588c89338 100644 --- a/techpack/audio/asoc/codecs/bolero/tx-macro.c +++ b/techpack/audio/asoc/codecs/bolero/tx-macro.c @@ -47,7 +47,11 @@ #define TX_MACRO_SWR_MIC_MUX_SEL_MASK 0xF #define TX_MACRO_ADC_MUX_CFG_OFFSET 0x2 +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define TX_MACRO_TX_UNMUTE_DELAY_MS 150 +#else #define TX_MACRO_TX_UNMUTE_DELAY_MS 40 +#endif static int tx_unmute_delay = TX_MACRO_TX_UNMUTE_DELAY_MS; module_param(tx_unmute_delay, int, 0664); @@ -752,7 +756,11 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, CF_MIN_3DB_150HZ) { schedule_delayed_work( &tx_priv->tx_hpf_work[decimator].dwork, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + msecs_to_jiffies(50)); +#else msecs_to_jiffies(300)); +#endif snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x02); /* * Minimum 1 clk cycle delay is required as per HW spec diff --git a/techpack/audio/asoc/codecs/wcd-dsp-mgr.c b/techpack/audio/asoc/codecs/wcd-dsp-mgr.c index b45a9b3b7516..4e1312e05699 100644 --- a/techpack/audio/asoc/codecs/wcd-dsp-mgr.c +++ b/techpack/audio/asoc/codecs/wcd-dsp-mgr.c @@ -85,6 +85,9 @@ static char *wdsp_get_cmpnt_type_string(enum wdsp_cmpnt_type); #define WDSP_SSR_STATUS_READY \ (WDSP_SSR_STATUS_WDSP_READY | WDSP_SSR_STATUS_CDC_READY) #define WDSP_SSR_READY_WAIT_TIMEOUT (10 * HZ) +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define WDSP_FW_LOAD_RETRY_COUNT 5 +#endif enum wdsp_ssr_type { @@ -384,6 +387,9 @@ static int wdsp_download_segments(struct wdsp_mgr_priv *wdsp, enum wdsp_event_type pre, post; long status; int ret; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int retry_cnt = 0; +#endif ctl = WDSP_GET_COMPONENT(wdsp, WDSP_CMPNT_CONTROL); @@ -416,7 +422,14 @@ static int wdsp_download_segments(struct wdsp_mgr_priv *wdsp, /* Go through the list of segments and download one by one */ list_for_each_entry(seg, wdsp->seg_list, list) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + retry_cnt = WDSP_FW_LOAD_RETRY_COUNT; + do { +#endif ret = wdsp_load_each_segment(wdsp, seg); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } while (ret < 0 && --retry_cnt > 0); +#endif if (ret) goto dload_error; } @@ -433,6 +446,12 @@ static int wdsp_download_segments(struct wdsp_mgr_priv *wdsp, dload_error: wdsp_flush_segment_list(wdsp->seg_list); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (type == WDSP_ELF_FLAG_RE) { + wdsp_broadcast_event_downseq(wdsp, post, NULL); + ret = 0; + } else +#endif wdsp_broadcast_event_downseq(wdsp, WDSP_EVENT_DLOAD_FAILED, NULL); return ret; } @@ -483,18 +502,40 @@ static void wdsp_load_fw_image(struct work_struct *work) static int wdsp_enable_dsp(struct wdsp_mgr_priv *wdsp) { int ret; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int retry_cnt = WDSP_FW_LOAD_RETRY_COUNT; +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + WDSP_MGR_MUTEX_LOCK(wdsp, wdsp->ssr_mutex); +#endif /* Make sure wdsp is in good state */ if (!WDSP_STATUS_IS_SET(wdsp, WDSP_STATUS_CODE_DLOADED)) { WDSP_ERR(wdsp, "WDSP in invalid state 0x%x", wdsp->status); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + ret = wdsp_init_and_dload_code_sections(wdsp); + if (ret < 0) { + WDSP_ERR(wdsp, "Retry code dload failed %d", + ret); + goto done; + } +#else return -EINVAL; +#endif } +#ifndef CONFIG_MACH_XIAOMI_SM8150 /* * Acquire SSR mutex lock to make sure enablement of DSP * does not race with SSR handling. */ WDSP_MGR_MUTEX_LOCK(wdsp, wdsp->ssr_mutex); +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +retry: +#endif /* Download the read-write sections of image */ ret = wdsp_download_segments(wdsp, WDSP_ELF_FLAG_WRITE); if (ret < 0) { @@ -509,6 +550,17 @@ static int wdsp_enable_dsp(struct wdsp_mgr_priv *wdsp) if (ret < 0) { WDSP_ERR(wdsp, "Failed to boot dsp, err = %d", ret); WDSP_CLEAR_STATUS(wdsp, WDSP_STATUS_DATA_DLOADED); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (retry_cnt-- >= 0) { + ret = wdsp_init_and_dload_code_sections(wdsp); + if (ret < 0) { + WDSP_ERR(wdsp, "Retry code dload failed %d", + ret); + goto done; + } + goto retry; + } +#endif goto done; } @@ -1203,6 +1255,10 @@ static int wdsp_mgr_parse_dt_entries(struct wdsp_mgr_priv *wdsp) return ret; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + wdsp->img_fname = "cpe_intl"; +#endif + ret = of_count_phandle_with_args(dev->of_node, "qcom,wdsp-components", NULL); diff --git a/techpack/audio/asoc/codecs/wcd-mbhc-adc.c b/techpack/audio/asoc/codecs/wcd-mbhc-adc.c index 96d1c8266764..d536aa45cc54 100644 --- a/techpack/audio/asoc/codecs/wcd-mbhc-adc.c +++ b/techpack/audio/asoc/codecs/wcd-mbhc-adc.c @@ -31,10 +31,17 @@ #include "wcd-mbhc-v2.h" #include "pdata.h" +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define WCD_MBHC_ADC_HS_THRESHOLD_MV 2600 +#define WCD_MBHC_ADC_HPH_THRESHOLD_MV 50 +#define WCD_MBHC_ADC_MICBIAS_MV 2700 +#define WCD_MBHC_FAKE_INS_RETRY 4 +#else #define WCD_MBHC_ADC_HS_THRESHOLD_MV 1700 #define WCD_MBHC_ADC_HPH_THRESHOLD_MV 75 #define WCD_MBHC_ADC_MICBIAS_MV 1800 #define WCD_MBHC_FAKE_INS_RETRY 4 +#endif static int wcd_mbhc_get_micbias(struct wcd_mbhc *mbhc) { @@ -503,18 +510,28 @@ static bool wcd_is_special_headset(struct wcd_mbhc *mbhc) static void wcd_mbhc_adc_update_fsm_source(struct wcd_mbhc *mbhc, enum wcd_mbhc_plug_type plug_type) { +#ifndef CONFIG_MACH_XIAOMI_SM8150 bool micbias2; +#endif +#ifndef CONFIG_MACH_XIAOMI_SM8150 micbias2 = mbhc->mbhc_cb->micbias_enable_status(mbhc, MIC_BIAS_2); +#endif switch (plug_type) { case MBHC_PLUG_TYPE_HEADPHONE: WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 3); break; case MBHC_PLUG_TYPE_HEADSET: case MBHC_PLUG_TYPE_ANC_HEADPHONE: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 0); + mbhc->mbhc_cb->mbhc_micbias_control(mbhc->codec, + MIC_BIAS_2, MICB_PULLUP_ENABLE); +#else if (!mbhc->is_hs_recording && !micbias2) WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 3); +#endif break; default: WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 0); @@ -705,6 +722,16 @@ static void wcd_correct_swch_plug(struct work_struct *work) } msleep(180); + +#ifdef CONFIG_MACH_XIAOMI_NABU + /* In the case of system bootup with headset pluged, mbhc + * begin to detect without sound card registered. delay + * about 150ms to wait sound card registe. + */ + if ((mbhc->mbhc_cfg->swap_gnd_mic == NULL) && (mbhc->mbhc_cfg->enable_usbc_analog)) + msleep(600); +#endif + /* * Use ADC single mode to minimize the chance of missing out * btn press/release for HEADSET type during correct work. @@ -990,8 +1017,13 @@ static irqreturn_t wcd_mbhc_adc_hs_rem_irq(int irq, void *data) hphpa_on = true; WCD_MBHC_REG_UPDATE_BITS( WCD_MBHC_HPHL_PA_EN, 0); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + WCD_MBHC_REG_UPDATE_BITS( + WCD_MBHC_HPHR_PA_EN, 0); +#else WCD_MBHC_REG_UPDATE_BITS( WCD_MBHC_HPH_PA_EN, 0); +#endif } WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHR_GND, 1); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHL_GND, 1); @@ -1035,7 +1067,11 @@ static irqreturn_t wcd_mbhc_adc_hs_rem_irq(int irq, void *data) if (hphpa_on) { hphpa_on = false; WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHL_PA_EN, 1); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHR_PA_EN, 1); +#else WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPH_PA_EN, 1); +#endif } } exit: diff --git a/techpack/audio/asoc/codecs/wcd-mbhc-v2.c b/techpack/audio/asoc/codecs/wcd-mbhc-v2.c index b5e26d7467e2..f0965acf212d 100644 --- a/techpack/audio/asoc/codecs/wcd-mbhc-v2.c +++ b/techpack/audio/asoc/codecs/wcd-mbhc-v2.c @@ -214,7 +214,9 @@ static int wcd_event_notify(struct notifier_block *self, unsigned long val, struct snd_soc_codec *codec = mbhc->codec; bool micbias2 = false; bool micbias1 = false; +#ifndef CONFIG_MACH_XIAOMI_SM8150 u8 fsm_en = 0; +#endif pr_debug("%s: event %s (%d)\n", __func__, wcd_mbhc_get_event_string(event), event); @@ -256,10 +258,12 @@ static int wcd_event_notify(struct notifier_block *self, unsigned long val, out_micb_en: /* Disable current source if micbias enabled */ if (mbhc->mbhc_cb->mbhc_micbias_control) { +#ifndef CONFIG_MACH_XIAOMI_SM8150 WCD_MBHC_REG_READ(WCD_MBHC_FSM_EN, fsm_en); if (fsm_en) WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 0); +#endif } else { mbhc->is_hs_recording = true; wcd_enable_curr_micbias(mbhc, WCD_MBHC_EN_MB); @@ -269,6 +273,7 @@ static int wcd_event_notify(struct notifier_block *self, unsigned long val, mbhc->mbhc_cb->set_cap_mode(codec, micbias1, true); break; case WCD_EVENT_PRE_MICBIAS_2_OFF: +#ifndef CONFIG_MACH_XIAOMI_SM8150 /* * Before MICBIAS_2 is turned off, if FSM is enabled, * make sure current source is enabled so as to detect @@ -281,6 +286,7 @@ static int wcd_event_notify(struct notifier_block *self, unsigned long val, WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 3); } +#endif break; /* MICBIAS usage change */ case WCD_EVENT_POST_DAPM_MICBIAS_2_OFF: @@ -600,6 +606,10 @@ void wcd_mbhc_report_plug(struct wcd_mbhc *mbhc, int insertion, mbhc->zl = mbhc->zr = 0; pr_debug("%s: Reporting removal %d(%x)\n", __func__, jack_type, mbhc->hph_status); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (mbhc->mbhc_cb->mbhc_mute_hs_tx && jack_type == SND_JACK_HEADSET) + mbhc->mbhc_cb->mbhc_mute_hs_tx(codec); +#endif wcd_mbhc_jack_report(mbhc, &mbhc->headset_jack, mbhc->hph_status, WCD_MBHC_JACK_MASK); wcd_mbhc_set_and_turnoff_hph_padac(mbhc); @@ -695,6 +705,7 @@ void wcd_mbhc_report_plug(struct wcd_mbhc *mbhc, int insertion, &mbhc->zl, &mbhc->zr); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_FSM_EN, fsm_en); +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) if ((mbhc->zl > mbhc->mbhc_cfg->linein_th && mbhc->zl < MAX_IMPED) && (mbhc->zr > mbhc->mbhc_cfg->linein_th && @@ -715,6 +726,7 @@ void wcd_mbhc_report_plug(struct wcd_mbhc *mbhc, int insertion, pr_debug("%s: Marking jack type as SND_JACK_LINEOUT\n", __func__); } +#endif } /* Do not calculate impedance again for lineout @@ -814,6 +826,11 @@ void wcd_mbhc_find_plug_and_report(struct wcd_mbhc *mbhc, * Nothing was reported previously * report a headphone or unsupported */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADSET) + wcd_mbhc_report_plug(mbhc, 0, SND_JACK_HEADSET); +#endif + wcd_mbhc_report_plug(mbhc, 1, SND_JACK_HEADPHONE); } else if (plug_type == MBHC_PLUG_TYPE_GND_MIC_SWAP) { if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADPHONE) @@ -828,6 +845,11 @@ void wcd_mbhc_find_plug_and_report(struct wcd_mbhc *mbhc, mbhc->mbhc_fn->wcd_mbhc_detect_anc_plug_type(mbhc); jack_type = SND_JACK_HEADSET; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc->current_plug == MBHC_PLUG_TYPE_HEADPHONE) + wcd_mbhc_report_plug(mbhc, 0, SND_JACK_HEADPHONE); +#endif + /* * If Headphone was reported previously, this will * only report the mic line @@ -843,6 +865,10 @@ void wcd_mbhc_find_plug_and_report(struct wcd_mbhc *mbhc, /* Disable HW FSM and current source */ WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_FSM_EN, 0); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 0); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + mbhc->mbhc_cb->mbhc_micbias_control(mbhc->codec, + MIC_BIAS_2, MICB_PULLUP_DISABLE); +#endif /* Setup for insertion detection */ WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_ELECT_DETECTION_TYPE, 1); @@ -902,6 +928,10 @@ static void wcd_mbhc_swch_irq_handler(struct wcd_mbhc *mbhc) bool micbias1 = false; struct snd_soc_codec *codec = mbhc->codec; enum snd_jack_types jack_type; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct usbc_ana_audio_config *config = + &mbhc->mbhc_cfg->usbc_analog_cfg; +#endif dev_dbg(codec->dev, "%s: enter\n", __func__); WCD_MBHC_RSC_LOCK(mbhc); @@ -973,6 +1003,10 @@ static void wcd_mbhc_swch_irq_handler(struct wcd_mbhc *mbhc) /* Disable HW FSM */ WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_FSM_EN, 0); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_ISRC_CTL, 0); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + mbhc->mbhc_cb->mbhc_micbias_control(mbhc->codec, + MIC_BIAS_2, MICB_PULLUP_DISABLE); +#endif if (mbhc->mbhc_cb->mbhc_common_micb_ctrl) mbhc->mbhc_cb->mbhc_common_micb_ctrl(codec, MBHC_COMMON_MICB_TAIL_CURR, false); @@ -982,6 +1016,9 @@ static void wcd_mbhc_swch_irq_handler(struct wcd_mbhc *mbhc) mbhc->btn_press_intr = false; mbhc->is_btn_press = false; +#ifdef CONFIG_MACH_XIAOMI_NABU + mbhc->mbhc_cfg->flip_switch = false; +#endif switch (mbhc->current_plug) { case MBHC_PLUG_TYPE_HEADPHONE: jack_type = SND_JACK_HEADPHONE; @@ -1014,10 +1051,19 @@ static void wcd_mbhc_swch_irq_handler(struct wcd_mbhc *mbhc) WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_ELECT_DETECTION_TYPE, 1); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_ELECT_SCHMT_ISRC, 0); mbhc->extn_cable_hph_rem = false; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (config->usbc_en1_gpio_p) { + msm_cdc_pinctrl_select_sleep_state(config->usbc_en1_gpio_p); + } +#endif wcd_mbhc_report_plug(mbhc, 0, jack_type); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc->mbhc_cfg->enable_usbc_analog) { +#else if (mbhc->mbhc_cfg->enable_usbc_analog && mbhc->mbhc_cfg->fsa_enable) { +#endif WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_L_DET_EN, 0); if (mbhc->mbhc_cb->clk_setup) mbhc->mbhc_cb->clk_setup(mbhc->codec, false); @@ -1372,6 +1418,11 @@ static int wcd_mbhc_initialise(struct wcd_mbhc *mbhc) * by an external source */ if (mbhc->mbhc_cfg->enable_usbc_analog) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + mbhc->hphl_swh = 0; + mbhc->gnd_swh = 0; +#endif + if (mbhc->mbhc_cb->hph_pull_up_control_v2) mbhc->mbhc_cb->hph_pull_up_control_v2(codec, HS_PULLUP_I_OFF); @@ -1394,7 +1445,11 @@ static int wcd_mbhc_initialise(struct wcd_mbhc *mbhc) * when a non-audio accessory is inserted. L_DET_EN sets to 1 when FSA * I2C driver notifies that ANALOG_AUDIO_ADAPTER is inserted */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc->mbhc_cfg->enable_usbc_analog) +#else if (mbhc->mbhc_cfg->enable_usbc_analog && mbhc->mbhc_cfg->fsa_enable) +#endif WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_L_DET_EN, 0); else WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_L_DET_EN, 1); @@ -1404,21 +1459,31 @@ static int wcd_mbhc_initialise(struct wcd_mbhc *mbhc) WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_INSREM_DBNC, 4); } else { /* Insertion debounce set to 96ms */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_INSREM_DBNC, 9); +#else WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_INSREM_DBNC, 6); +#endif } /* Button Debounce set to 16ms */ WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_BTN_DBNC, 2); +#ifndef CONFIG_MACH_XIAOMI_SM8150 /* Enable micbias ramp */ if (mbhc->mbhc_cb->mbhc_micb_ramp_control) mbhc->mbhc_cb->mbhc_micb_ramp_control(codec, true); +#endif /* enable bias */ mbhc->mbhc_cb->mbhc_bias(codec, true); /* enable MBHC clock */ if (mbhc->mbhc_cb->clk_setup) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc->mbhc_cfg->enable_usbc_analog) +#else if (mbhc->mbhc_cfg->enable_usbc_analog && mbhc->mbhc_cfg->fsa_enable) +#endif mbhc->mbhc_cb->clk_setup(codec, false); else mbhc->mbhc_cb->clk_setup(codec, true); @@ -1624,14 +1689,22 @@ static int wcd_mbhc_usb_c_analog_setup_gpios(struct wcd_mbhc *mbhc, bool active) int rc = 0; struct usbc_ana_audio_config *config = &mbhc->mbhc_cfg->usbc_analog_cfg; +#ifndef CONFIG_MACH_XIAOMI_SM8150 union power_supply_propval pval; +#endif dev_dbg(mbhc->codec->dev, "%s: setting GPIOs active = %d\n", __func__, active); +#ifndef CONFIG_MACH_XIAOMI_SM8150 memset(&pval, 0, sizeof(pval)); +#endif if (active) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_MIC_CLAMP_CTL, 2); + mbhc->mbhc_cfg->enable_dual_adc_gpio(mbhc->mbhc_cfg->dual_adc_gpio_node, 0); +#else pval.intval = POWER_SUPPLY_TYPEC_PR_SOURCE; if (power_supply_set_property(mbhc->usb_psy, POWER_SUPPLY_PROP_TYPEC_POWER_ROLE, &pval)) @@ -1639,22 +1712,32 @@ static int wcd_mbhc_usb_c_analog_setup_gpios(struct wcd_mbhc *mbhc, bool active) __func__); else mbhc->usbc_force_pr_mode = true; +#endif if (config->usbc_en1_gpio_p) rc = msm_cdc_pinctrl_select_active_state( config->usbc_en1_gpio_p); +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (rc == 0 && config->usbc_en2n_gpio_p) rc = msm_cdc_pinctrl_select_active_state( config->usbc_en2n_gpio_p); +#endif if (rc == 0 && config->usbc_force_gpio_p) rc = msm_cdc_pinctrl_select_active_state( config->usbc_force_gpio_p); mbhc->usbc_mode = POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc->mbhc_cb->clk_setup) + mbhc->mbhc_cb->clk_setup(mbhc->codec, true); + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_L_DET_EN, 1); +#endif } else { /* no delay is required when disabling GPIOs */ +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (config->usbc_en2n_gpio_p) msm_cdc_pinctrl_select_sleep_state( config->usbc_en2n_gpio_p); +#endif if (config->usbc_en1_gpio_p) msm_cdc_pinctrl_select_sleep_state( config->usbc_en1_gpio_p); @@ -1662,6 +1745,9 @@ static int wcd_mbhc_usb_c_analog_setup_gpios(struct wcd_mbhc *mbhc, bool active) msm_cdc_pinctrl_select_sleep_state( config->usbc_force_gpio_p); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + mbhc->mbhc_cfg->enable_dual_adc_gpio(mbhc->mbhc_cfg->dual_adc_gpio_node, 1); +#else if (mbhc->usbc_force_pr_mode) { pval.intval = POWER_SUPPLY_TYPEC_PR_DUAL; if (power_supply_set_property(mbhc->usb_psy, @@ -1670,7 +1756,13 @@ static int wcd_mbhc_usb_c_analog_setup_gpios(struct wcd_mbhc *mbhc, bool active) __func__); mbhc->usbc_force_pr_mode = false; } +#endif mbhc->usbc_mode = POWER_SUPPLY_TYPEC_NONE; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_MIC_CLAMP_CTL, 0); + if (mbhc->mbhc_cfg->swap_gnd_mic) + mbhc->mbhc_cfg->swap_gnd_mic(mbhc->codec, false); +#endif } return rc; @@ -1759,6 +1851,7 @@ static int wcd_mbhc_usb_c_analog_init(struct wcd_mbhc *mbhc) goto err; } +#ifndef CONFIG_MACH_XIAOMI_SM8150 mbhc->psy_nb.notifier_call = wcd_mbhc_usb_c_event_changed; mbhc->psy_nb.priority = 0; ret = power_supply_reg_notifier(&mbhc->psy_nb); @@ -1778,6 +1871,7 @@ static int wcd_mbhc_usb_c_analog_init(struct wcd_mbhc *mbhc) PSY_EVENT_PROP_CHANGED, mbhc->usb_psy); +#endif err: return ret; } @@ -1791,6 +1885,46 @@ static int wcd_mbhc_usb_c_analog_deinit(struct wcd_mbhc *mbhc) return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int wcd_mbhc_non_usb_c_event_changed(struct notifier_block *nb, + unsigned long evt, void *ptr) +{ + int ret; + union power_supply_propval mode; + struct wcd_mbhc *mbhc = container_of(nb, struct wcd_mbhc, fsa_nb); + + ret = power_supply_get_property(ptr, + POWER_SUPPLY_PROP_TYPEC_MODE, &mode); + + switch (mode.intval) { + case POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER: + dev_err(mbhc->codec->dev, "%s: report Type-C usb headphone\n", __func__); + if (mbhc->usbc_mode == mode.intval) + break; /* filter notifications received before */ + wcd_mbhc_jack_report(mbhc, &mbhc->usb_3_5_jack, + (SND_JACK_HEADSET | SND_JACK_UNSUPPORTED), + WCD_MBHC_JACK_USB_3_5_MASK); + mbhc->usbc_mode = mode.intval; + break; + case POWER_SUPPLY_TYPEC_NONE: + if (mbhc->usbc_mode == mode.intval) + break; /* filter notifications received before */ + if (mbhc->usbc_mode == POWER_SUPPLY_TYPEC_SINK_AUDIO_ADAPTER) { + mbhc->usbc_mode = mode.intval - 1; + break; + } + wcd_mbhc_jack_report(mbhc, &mbhc->usb_3_5_jack, 0, + WCD_MBHC_JACK_USB_3_5_MASK); + mbhc->usbc_mode = mode.intval; + break; + default: + break; + } + + return ret; +} +#endif + int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) { int rc = 0; @@ -1798,6 +1932,9 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) struct snd_soc_codec *codec; struct snd_soc_card *card; const char *usb_c_dt = "qcom,msm-mbhc-usbc-audio-supported"; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + const char *fsa4476_dt = "qcom,fsa4476-gpio-support"; +#endif if (!mbhc || !mbhc_cfg) return -EINVAL; @@ -1830,6 +1967,7 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) dev_dbg(mbhc->codec->dev, "%s: usbc analog enabled\n", __func__); mbhc->swap_thr = GND_MIC_USBC_SWAP_THRESHOLD; +#ifndef CONFIG_MACH_XIAOMI_SM8150 mbhc->fsa_np = of_parse_phandle(card->dev->of_node, "fsa4480-i2c-handle", 0); if (mbhc->fsa_np) { @@ -1839,6 +1977,22 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) __func__); mbhc_cfg->fsa_enable = false; +#endif + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + mbhc_cfg->use_fsa4476_gpio = 0; + if (of_find_property(card->dev->of_node, fsa4476_dt, NULL)) { + rc = of_property_read_u32(card->dev->of_node, fsa4476_dt, + &mbhc_cfg->use_fsa4476_gpio); + if (rc != 0) { + dev_dbg(card->dev, + "%s: %s in dt node is missing or false\n", + __func__, fsa4476_dt); + } + } + + if (mbhc_cfg->use_fsa4476_gpio != 0) { +#endif rc = wcd_mbhc_init_gpio(mbhc, mbhc_cfg, "qcom,usbc-analog-en1_gpio", &config->usbc_en1_gpio, @@ -1846,6 +2000,7 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) if (rc) goto err; +#ifndef CONFIG_MACH_XIAOMI_SM8150 rc = wcd_mbhc_init_gpio(mbhc, mbhc_cfg, "qcom,usbc-analog-en2_n_gpio", &config->usbc_en2n_gpio, @@ -1863,6 +2018,7 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) if (rc) goto err; } +#endif dev_dbg(mbhc->codec->dev, "%s: calling usb_c_analog_init\n", __func__); @@ -1872,6 +2028,17 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) rc = EPROBE_DEFER; goto err; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } else { + mbhc->fsa_np = of_parse_phandle(card->dev->of_node, + "fsa4480-i2c-handle", 0); + if (!mbhc->fsa_np) { + dev_err(card->dev, "%s: fsa4480 i2c node not found\n", + __func__); + rc = -EINVAL; + goto err; + } // git +#endif } } /* Set btn key code */ @@ -1897,14 +2064,62 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) __func__, mbhc->mbhc_fw, mbhc->mbhc_cal); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc_cfg->enable_usbc_analog) { + if (mbhc_cfg->use_fsa4476_gpio == 0) { +#else if (mbhc_cfg->enable_usbc_analog && mbhc_cfg->fsa_enable) { +#endif mbhc->fsa_nb.notifier_call = wcd_mbhc_usbc_ana_event_handler; mbhc->fsa_nb.priority = 0; rc = fsa4480_reg_notifier(&mbhc->fsa_nb, mbhc->fsa_np); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } else { + mbhc->psy_nb.notifier_call = wcd_mbhc_usb_c_event_changed; + mbhc->psy_nb.priority = 0; + rc = power_supply_reg_notifier(&mbhc->psy_nb); + if (rc) { + dev_err(codec->dev, "%s: power supply registration failed\n", + __func__); + goto err; + } + + /* + * as part of the init sequence check if there is a connected + * USB C analog adapter + */ + dev_dbg(mbhc->codec->dev, "%s: verify if USB adapter is already inserted\n", + __func__); + rc = wcd_mbhc_usb_c_event_changed(&mbhc->psy_nb, + PSY_EVENT_PROP_CHANGED, + mbhc->usb_psy); + } // git + } else { + mbhc->fsa_nb.notifier_call = wcd_mbhc_non_usb_c_event_changed; + mbhc->fsa_nb.priority = 0; + rc = power_supply_reg_notifier(&mbhc->fsa_nb); + if (rc) { + dev_err(card->dev, "%s: power supply registration failed\n", + __func__); + goto err; + } // git +#endif } return rc; err: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (config->usbc_en1_gpio > 0) { + dev_dbg(card->dev, "%s free usb en1 gpio %d\n", + __func__, config->usbc_en1_gpio); + gpio_free(config->usbc_en1_gpio); + config->usbc_en1_gpio = 0; + } + if (config->usbc_en1_gpio_p) + of_node_put(config->usbc_en1_gpio_p); + if (config->usbc_force_gpio_p) + of_node_put(config->usbc_force_gpio_p); +#endif dev_dbg(mbhc->codec->dev, "%s: leave %d\n", __func__, rc); return rc; } @@ -1941,24 +2156,42 @@ void wcd_mbhc_stop(struct wcd_mbhc *mbhc) } if (mbhc->mbhc_cfg->enable_usbc_analog) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (mbhc->mbhc_cfg->use_fsa4476_gpio == 0) { +#else if (mbhc->mbhc_cfg->fsa_enable) { +#endif fsa4480_unreg_notifier(&mbhc->fsa_nb, mbhc->fsa_np); } else { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } +#endif wcd_mbhc_usb_c_analog_deinit(mbhc); /* free GPIOs */ if (config->usbc_en1_gpio > 0) gpio_free(config->usbc_en1_gpio); +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (config->usbc_en2n_gpio > 0) gpio_free(config->usbc_en2n_gpio); if (config->usbc_force_gpio) gpio_free(config->usbc_force_gpio); +#endif if (config->usbc_en1_gpio_p) of_node_put(config->usbc_en1_gpio_p); +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (config->usbc_en2n_gpio_p) of_node_put(config->usbc_en2n_gpio_p); if (config->usbc_force_gpio_p) of_node_put(config->usbc_force_gpio_p); +#endif +#ifndef CONFIG_MACH_XIAOMI_SM8150 } +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } else { + if (mbhc->fsa_nb.notifier_call != NULL) + power_supply_unreg_notifier(&mbhc->fsa_nb); +#endif } @@ -2096,6 +2329,16 @@ int wcd_mbhc_init(struct wcd_mbhc *mbhc, struct snd_soc_codec *codec, return ret; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + ret = snd_soc_card_jack_new(codec->component.card, + "USB_3_5 Jack", WCD_MBHC_JACK_USB_3_5_MASK, + &mbhc->usb_3_5_jack, NULL, 0); + if (ret) { + pr_err("%s: Failed to create new jack USB_3_5 Jack\n", __func__); + return ret; + } +#endif + INIT_DELAYED_WORK(&mbhc->mbhc_firmware_dwork, wcd_mbhc_fw_read); INIT_DELAYED_WORK(&mbhc->mbhc_btn_dwork, wcd_btn_lpress_fn); diff --git a/techpack/audio/asoc/codecs/wcd-mbhc-v2.h b/techpack/audio/asoc/codecs/wcd-mbhc-v2.h index 6be73e220265..9a449e2c942e 100644 --- a/techpack/audio/asoc/codecs/wcd-mbhc-v2.h +++ b/techpack/audio/asoc/codecs/wcd-mbhc-v2.h @@ -137,12 +137,25 @@ do { \ #define WCD_MBHC_JACK_BUTTON_MASK (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ SND_JACK_BTN_2 | SND_JACK_BTN_3 | \ SND_JACK_BTN_4 | SND_JACK_BTN_5) + +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define WCD_MBHC_JACK_USB_3_5_MASK (SND_JACK_UNSUPPORTED | SND_JACK_HEADSET) +#endif + #define OCP_ATTEMPT 20 +#ifdef CONFIG_MACH_XIAOMI_NABU +#define HS_DETECT_PLUG_TIME_MS (3 * 1200) +#else #define HS_DETECT_PLUG_TIME_MS (3 * 1000) +#endif #define SPECIAL_HS_DETECT_TIME_MS (2 * 1000) #define MBHC_BUTTON_PRESS_THRESHOLD_MIN 250 #define GND_MIC_SWAP_THRESHOLD 4 +#ifdef CONFIG_MACH_XIAOMI_NABU +#define GND_MIC_USBC_SWAP_THRESHOLD 4 +#else #define GND_MIC_USBC_SWAP_THRESHOLD 2 +#endif #define WCD_FAKE_REMOVAL_MIN_PERIOD_MS 100 #define HS_VREF_MIN_VAL 1400 #define FW_READ_ATTEMPTS 15 @@ -420,9 +433,19 @@ struct usbc_ana_audio_config { int usbc_en1_gpio; int usbc_en2n_gpio; int usbc_force_gpio; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int euro_us_hw_switch_gpio; + int uart_audio_switch_gpio; + int subpcb_id_gpio; +#endif struct device_node *usbc_en1_gpio_p; /* used by pinctrl API */ struct device_node *usbc_en2n_gpio_p; /* used by pinctrl API */ struct device_node *usbc_force_gpio_p; /* used by pinctrl API */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct device_node *euro_us_hw_switch_gpio_p; /* used by pinctrl API */ + struct device_node *uart_audio_switch_gpio_p; /* used by pinctrl API */ + struct device_node *subpcb_id_gpio_p; /* used by pinctrl API */ +#endif }; enum mbhc_moisture_rref { @@ -449,7 +472,15 @@ struct wcd_mbhc_config { u32 enable_usbc_analog; bool moisture_duty_cycle_en; struct usbc_ana_audio_config usbc_analog_cfg; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + u32 use_fsa4476_gpio; + void (*enable_dual_adc_gpio)(struct device_node *node, bool en); + struct device_node *dual_adc_gpio_node; +#endif bool fsa_enable; +#ifdef CONFIG_MACH_XIAOMI_NABU + bool flip_switch; +#endif }; struct wcd_mbhc_intr { @@ -520,6 +551,9 @@ struct wcd_mbhc_cb { bool (*mbhc_get_moisture_status)(struct wcd_mbhc *); void (*mbhc_moisture_polling_ctrl)(struct wcd_mbhc *, bool); void (*mbhc_moisture_detect_en)(struct wcd_mbhc *, bool); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + void (*mbhc_mute_hs_tx)(struct snd_soc_codec *); +#endif }; struct wcd_mbhc_fn { @@ -587,6 +621,9 @@ struct wcd_mbhc { struct snd_soc_jack headset_jack; struct snd_soc_jack button_jack; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct snd_soc_jack usb_3_5_jack; +#endif struct mutex codec_resource_lock; /* Holds codec specific interrupt mapping */ diff --git a/techpack/audio/asoc/codecs/wcd-spi.c b/techpack/audio/asoc/codecs/wcd-spi.c index 7a56d6fdbc69..afb3550641ff 100644 --- a/techpack/audio/asoc/codecs/wcd-spi.c +++ b/techpack/audio/asoc/codecs/wcd-spi.c @@ -1045,6 +1045,15 @@ static int wcd_spi_bus_gwrite(void *context, const void *reg, return -EINVAL; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (wcd_spi_is_suspended(wcd_spi)) { + dev_err(&spi->dev, + "%s: SPI suspended, cannot enable clk\n", + __func__); + return -EIO; + } +#endif + memset(tx_buf, 0, WCD_SPI_CMD_IRW_LEN); tx_buf[0] = WCD_SPI_CMD_IRW; tx_buf[1] = *((u8 *)reg); @@ -1094,6 +1103,15 @@ static int wcd_spi_bus_read(void *context, const void *reg, return -EINVAL; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (wcd_spi_is_suspended(wcd_spi)) { + dev_err(&spi->dev, + "%s: SPI suspended, cannot enable clk\n", + __func__); + return -EIO; + } +#endif + memset(tx_buf, 0, WCD_SPI_CMD_IRR_LEN); tx_buf[0] = WCD_SPI_CMD_IRR; tx_buf[1] = *((u8 *)reg); diff --git a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c index 3aa8fe7aea1c..adbd94852973 100644 --- a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c +++ b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c @@ -863,6 +863,13 @@ static bool tavil_is_anc_on(struct wcd_mbhc *mbhc) return anc_on; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static void tavil_mute_hs_tx(struct snd_soc_codec *codec) +{ + snd_soc_update_bits(codec, WCD934X_CDC_TX0_TX_PATH_CTL, 0x10, 0x10); +} +#endif + static const struct wcd_mbhc_cb mbhc_cb = { .request_irq = tavil_mbhc_request_irq, .irq_control = tavil_mbhc_irq_control, @@ -888,6 +895,9 @@ static const struct wcd_mbhc_cb mbhc_cb = { .hph_register_recovery = tavil_hph_register_recovery, .update_anc_state = tavil_update_anc_state, .is_anc_on = tavil_is_anc_on, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + .mbhc_mute_hs_tx = tavil_mute_hs_tx, +#endif }; static struct regulator *tavil_codec_find_ondemand_regulator( @@ -987,6 +997,28 @@ int tavil_mbhc_get_impedance(struct wcd934x_mbhc *wcd934x_mbhc, } EXPORT_SYMBOL(tavil_mbhc_get_impedance); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int tavil_mb_pull_down(struct snd_soc_codec *codec, bool active, + int value) +{ + int oldv = 0; + + if (active) { + oldv = snd_soc_read(codec, WCD934X_ANA_MICB2); + snd_soc_update_bits(codec, WCD934X_ANA_MBHC_ELECT, + 0x80, 0x00); + snd_soc_update_bits(codec, WCD934X_ANA_MICB2, 0xC0, 0xC0); + } else { + snd_soc_write(codec, WCD934X_ANA_MICB2, value); + snd_soc_update_bits(codec, WCD934X_ANA_MBHC_ELECT, + 0x80, 0x80); + } + + return oldv; +} +EXPORT_SYMBOL(tavil_mb_pull_down); +#endif + /* * tavil_mbhc_hs_detect: starts mbhc insertion/removal functionality * @codec: handle to snd_soc_codec * diff --git a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h index 53c886da0f6b..cde9799b9c4b 100644 --- a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h +++ b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h @@ -47,6 +47,10 @@ extern int tavil_mbhc_post_ssr_init(struct wcd934x_mbhc *mbhc, struct snd_soc_codec *codec); extern int tavil_mbhc_get_impedance(struct wcd934x_mbhc *wcd934x_mbhc, uint32_t *zl, uint32_t *zr); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +extern int tavil_mb_pull_down(struct snd_soc_codec *codec, bool active, + int value); +#endif #else static inline int tavil_mbhc_init(struct wcd934x_mbhc **mbhc, struct snd_soc_codec *codec, @@ -79,6 +83,13 @@ static inline int tavil_mbhc_get_impedance(struct wcd934x_mbhc *wcd934x_mbhc, *zr = 0; return -EINVAL; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static inline int tavil_mb_pull_down(struct snd_soc_codec *codec, bool active, + int value) +{ + return 0; +} +#endif #endif #endif /* __WCD934X_MBHC_H__ */ diff --git a/techpack/audio/asoc/codecs/wcd934x/wcd934x.c b/techpack/audio/asoc/codecs/wcd934x/wcd934x.c index aae438092a4c..16741c570fe9 100644 --- a/techpack/audio/asoc/codecs/wcd934x/wcd934x.c +++ b/techpack/audio/asoc/codecs/wcd934x/wcd934x.c @@ -644,6 +644,9 @@ struct tavil_priv { struct platform_device *pdev_child_devices [WCD934X_CHILD_DEVICES_MAX]; int child_count; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int micbias_num; +#endif struct regulator *micb_load; int micb_load_low; int micb_load_high; @@ -5674,10 +5677,28 @@ static int tavil_compander_put(struct snd_kcontrol *kcontrol, /* Set Gain Source Select based on compander enable/disable */ snd_soc_update_bits(codec, WCD934X_HPH_L_EN, 0x20, (value ? 0x00:0x20)); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* Disable Compander Clock */ + snd_soc_update_bits(codec, WCD934X_CDC_RX1_RX_PATH_CFG0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x04, 0x04); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x02, 0x02); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x01, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x04, 0x00); +#endif break; case COMPANDER_2: snd_soc_update_bits(codec, WCD934X_HPH_R_EN, 0x20, (value ? 0x00:0x20)); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + /* Disable Compander Clock */ + snd_soc_update_bits(codec, WCD934X_CDC_RX2_RX_PATH_CFG0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x04, 0x04); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x02, 0x02); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x01, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x04, 0x00); +#endif break; case COMPANDER_3: case COMPANDER_4: @@ -6025,6 +6046,60 @@ static int tavil_mad_input_put(struct snd_kcontrol *kcontrol, return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static const char *const tavil_micbias_text[] = { + "OFF", "MICBIAS1", "MICBIAS2", "MICBIAS3", "MICBIAS4" +}; + +static const struct soc_enum tavil_micbias_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tavil_micbias_text), + tavil_micbias_text); + +static int tavil_micb_status_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tavil_priv *priv = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = priv->micbias_num;; + + return 0; +} + +static int tavil_micb_status_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct tavil_priv *priv = snd_soc_codec_get_drvdata(codec); + u8 tavil_micbias_num; + + tavil_micbias_num = ucontrol->value.integer.value[0]; + + if (tavil_micbias_num >= sizeof(tavil_micbias_text)/ + sizeof(tavil_micbias_text[0])) { + dev_err(codec->dev, + "%s: tavil_micbias_num = %d out of bounds\n", + __func__, tavil_micbias_num); + return -EINVAL; + } + priv->micbias_num = tavil_micbias_num; + + if (tavil_micbias_num == 0) { + tavil_codec_enable_standalone_micbias(codec, 1, false); + tavil_codec_enable_standalone_micbias(codec, 2, false); + tavil_codec_enable_standalone_micbias(codec, 3, false); + tavil_codec_enable_standalone_micbias(codec, 4, false); + dev_err(codec->dev, "====>PFT: %s: turn off all micbias.\n", __func__); + } else { + tavil_codec_enable_standalone_micbias(codec, tavil_micbias_num, true); + dev_err(codec->dev, "====>PFT: %s: turn on micbias %d.\n", + __func__, tavil_micbias_num); + } + + return 0; +} +#endif + static int tavil_ear_pa_gain_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -6328,8 +6403,13 @@ static const struct snd_kcontrol_new tavil_snd_controls[] = { SOC_ENUM_EXT("SPKR Right Boost Max State", tavil_spkr_boost_stage_enum, tavil_spkr_right_boost_stage_get, tavil_spkr_right_boost_stage_put), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain), + SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain), +#else SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 20, 1, line_gain), SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 20, 1, line_gain), +#endif SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER, 3, 16, 1, line_gain), SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER, @@ -6524,6 +6604,11 @@ static const struct snd_kcontrol_new tavil_snd_controls[] = { SOC_ENUM_EXT("MAD Input", tavil_conn_mad_enum, tavil_mad_input_get, tavil_mad_input_put), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + SOC_ENUM_EXT("Mic Bias", tavil_micbias_enum, + tavil_micb_status_get, tavil_micb_status_put), +#endif + SOC_SINGLE_EXT("DMIC1_CLK_PIN_MODE", SND_SOC_NOPM, 17, 1, 0, tavil_dmic_pin_mode_get, tavil_dmic_pin_mode_put), @@ -11145,6 +11230,9 @@ static int tavil_probe(struct platform_device *pdev) tavil->swr.plat_data.clk = tavil_swrm_clock; tavil->swr.plat_data.handle_irq = tavil_swrm_handle_irq; tavil->swr.spkr_gain_offset = WCD934X_RX_GAIN_OFFSET_0_DB; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + tavil->micbias_num = 0; +#endif /* Register for Clock */ wcd_ext_clk = clk_get(tavil->wcd9xxx->dev, "wcd_clk"); diff --git a/techpack/audio/asoc/codecs/wcd937x/internal.h b/techpack/audio/asoc/codecs/wcd937x/internal.h index bc335a565ed3..c6f524231b1c 100644 --- a/techpack/audio/asoc/codecs/wcd937x/internal.h +++ b/techpack/audio/asoc/codecs/wcd937x/internal.h @@ -92,6 +92,9 @@ struct wcd937x_priv { struct snd_info_entry *version_entry; /*Entry for Variant info*/ struct snd_info_entry *variant_entry; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int ear_rx_path; +#endif int ana_clk_count; struct mutex ana_tx_clk_lock; }; diff --git a/techpack/audio/asoc/codecs/wcd937x/wcd937x.c b/techpack/audio/asoc/codecs/wcd937x/wcd937x.c index 64a48e34a5f0..7ea1f1b2b6bd 100644 --- a/techpack/audio/asoc/codecs/wcd937x/wcd937x.c +++ b/techpack/audio/asoc/codecs/wcd937x/wcd937x.c @@ -1248,6 +1248,9 @@ static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00); snd_soc_update_bits(codec, WCD937X_ANA_TX_CH2, 0x40, 0x40); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + snd_soc_update_bits(codec, WCD937X_ANA_TX_CH3, 0x40, 0x40); +#endif snd_soc_update_bits(codec, WCD937X_ANA_TX_CH3_HPF, 0x40, 0x40); snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x70, 0x70); @@ -1255,11 +1258,17 @@ static int wcd937x_enable_req(struct snd_soc_dapm_widget *w, snd_soc_update_bits(codec, WCD937X_ANA_TX_CH2, 0x40, 0x00); snd_soc_update_bits(codec, WCD937X_ANA_TX_CH2, 0x80, 0x80); snd_soc_update_bits(codec, WCD937X_ANA_TX_CH3, 0x80, 0x80); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + snd_soc_update_bits(codec, WCD937X_ANA_TX_CH3_HPF, 0x80, 0x80); +#endif break; case SND_SOC_DAPM_POST_PMD: snd_soc_update_bits(codec, WCD937X_ANA_TX_CH1, 0x80, 0x00); snd_soc_update_bits(codec, WCD937X_ANA_TX_CH2, 0x80, 0x00); snd_soc_update_bits(codec, WCD937X_ANA_TX_CH3, 0x80, 0x00); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + snd_soc_update_bits(codec, WCD937X_ANA_TX_CH3_HPF, 0x80, 0x00); +#endif snd_soc_update_bits(codec, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00); mutex_lock(&wcd937x->ana_tx_clk_lock); @@ -1716,8 +1725,13 @@ static const struct snd_kcontrol_new wcd937x_snd_controls[] = { SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0, wcd937x_get_compander, wcd937x_set_compander), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 24, 1, line_gain), + SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 24, 1, line_gain), +#else SOC_SINGLE_TLV("HPHL Volume", WCD937X_HPH_L_EN, 0, 20, 1, line_gain), SOC_SINGLE_TLV("HPHR Volume", WCD937X_HPH_R_EN, 0, 20, 1, line_gain), +#endif SOC_SINGLE_TLV("ADC1 Volume", WCD937X_ANA_TX_CH1, 0, 20, 0, analog_gain), SOC_SINGLE_TLV("ADC2 Volume", WCD937X_ANA_TX_CH2, 0, 20, 0, analog_gain), SOC_SINGLE_TLV("ADC3 Volume", WCD937X_ANA_TX_CH3, 0, 20, 0, analog_gain), diff --git a/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c b/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c index 478c0c6d72e6..1b5ea88b5485 100644 --- a/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c +++ b/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c @@ -794,6 +794,9 @@ static void wcd_clsh_state_hph_ear(struct snd_soc_codec *codec, wcd_clsh_set_gain_path(codec, mode); wcd_clsh_set_flyback_mode(codec, mode); wcd_clsh_set_buck_mode(codec, mode); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + wcd_clsh_set_hph_mode(codec, mode); +#endif } } else { if (req_state == WCD_CLSH_STATE_EAR) { diff --git a/techpack/audio/asoc/msm-compress-q6-v2.c b/techpack/audio/asoc/msm-compress-q6-v2.c index 26731e180d20..26aaa85e3b8b 100644 --- a/techpack/audio/asoc/msm-compress-q6-v2.c +++ b/techpack/audio/asoc/msm-compress-q6-v2.c @@ -1291,7 +1291,11 @@ static int msm_compr_configure_dsp_for_playback struct snd_compr_runtime *runtime = cstream->runtime; struct msm_compr_audio *prtd = runtime->private_data; struct snd_soc_pcm_runtime *soc_prtd = cstream->private_data; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + uint16_t bits_per_sample = 24; +#else uint16_t bits_per_sample = 16; +#endif int dir = IN, ret = 0; struct audio_client *ac = prtd->audio_client; uint32_t stream_index; @@ -2253,7 +2257,11 @@ static int msm_compr_trigger(struct snd_compr_stream *cstream, int cmd) unsigned long flags; int stream_id; uint32_t stream_index; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + uint16_t bits_per_sample = 24; +#else uint16_t bits_per_sample = 16; +#endif spin_lock_irqsave(&prtd->lock, flags); if (atomic_read(&prtd->error)) { @@ -3615,6 +3623,9 @@ static int msm_compr_playback_app_type_cfg_put(struct snd_kcontrol *kcontrol, cfg_data.acdb_dev_id = ucontrol->value.integer.value[1]; if (ucontrol->value.integer.value[2] != 0) cfg_data.sample_rate = ucontrol->value.integer.value[2]; +#ifdef CONFIG_MACH_XIAOMI_NABU + cfg_data.channel = ucontrol->value.integer.value[4]; +#endif pr_debug("%s: fe_id- %llu session_type- %d be_id- %d app_type- %d acdb_dev_id- %d sample_rate- %d\n", __func__, fe_id, session_type, be_id, cfg_data.app_type, cfg_data.acdb_dev_id, cfg_data.sample_rate); @@ -3648,6 +3659,9 @@ static int msm_compr_playback_app_type_cfg_get(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[1] = cfg_data.acdb_dev_id; ucontrol->value.integer.value[2] = cfg_data.sample_rate; ucontrol->value.integer.value[3] = be_id; +#ifdef CONFIG_MACH_XIAOMI_NABU + ucontrol->value.integer.value[4] = cfg_data.channel; +#endif pr_debug("%s: fedai_id %llu, session_type %d, be_id %d, app_type %d, acdb_dev_id %d, sample_rate %d\n", __func__, fe_id, session_type, be_id, cfg_data.app_type, cfg_data.acdb_dev_id, cfg_data.sample_rate); diff --git a/techpack/audio/asoc/msm-dai-fe.c b/techpack/audio/asoc/msm-dai-fe.c index 8020929f680a..b330bcf81a12 100644 --- a/techpack/audio/asoc/msm-dai-fe.c +++ b/techpack/audio/asoc/msm-dai-fe.c @@ -575,6 +575,54 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .name = "CDC_DMA_HOSTLESS", .probe = fe_dai_probe, }, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + { + .playback = { + .stream_name = "ULTRAOUND_HOSTLESS Playback", + .aif_name = "RX1_CDC_DMA_DL_US", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_352800 | + SNDRV_PCM_RATE_384000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S24_3LE, + .channels_min = 1, + .channels_max = 4, + .rate_min = 8000, + .rate_max = 384000, + }, + .ops = &msm_fe_dai_ops, + .name = "CDC_DMA_HOSTLESS_USRX", + .probe = fe_dai_probe, + }, + { + .capture = { + .stream_name = "ULTRAOUND_HOSTLESS Capture", + .aif_name = "TX4_CDC_DMA_UL_US", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_352800 | + SNDRV_PCM_RATE_384000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S24_3LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 384000, + }, + .ops = &msm_fe_dai_ops, + .name = "CDC_DMA_HOSTLESS_USTX", + .probe = fe_dai_probe, + }, +#endif { .capture = { .stream_name = "TX3_CDC_DMA_HOSTLESS Capture", @@ -863,6 +911,9 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .aif_name = "PRI_MI2S_UL_HL", .rates = SNDRV_PCM_RATE_8000_48000, .formats = (SNDRV_PCM_FMTBIT_S16_LE | +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SNDRV_PCM_FMTBIT_S24_3LE | +#endif SNDRV_PCM_FMTBIT_S24_LE), .channels_min = 1, .channels_max = 2, @@ -879,6 +930,9 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .aif_name = "PRI_MI2S_DL_HL", .rates = SNDRV_PCM_RATE_8000_384000, .formats = (SNDRV_PCM_FMTBIT_S16_LE | +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SNDRV_PCM_FMTBIT_S24_3LE | +#endif SNDRV_PCM_FMTBIT_S24_LE), .channels_min = 1, .channels_max = 2, @@ -927,6 +981,9 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .aif_name = "TERT_MI2S_UL_HL", .rates = SNDRV_PCM_RATE_8000_48000, .formats = (SNDRV_PCM_FMTBIT_S16_LE | +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SNDRV_PCM_FMTBIT_S24_3LE | +#endif SNDRV_PCM_FMTBIT_S24_LE), .channels_min = 1, .channels_max = 2, @@ -943,6 +1000,9 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .aif_name = "TERT_MI2S_DL_HL", .rates = SNDRV_PCM_RATE_8000_384000, .formats = SNDRV_PCM_FMTBIT_S16_LE | +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SNDRV_PCM_FMTBIT_S24_3LE | +#endif SNDRV_PCM_FMTBIT_S24_LE, .channels_min = 1, .channels_max = 2, @@ -959,6 +1019,9 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .aif_name = "QUAT_MI2S_UL_HL", .rates = SNDRV_PCM_RATE_8000_48000, .formats = (SNDRV_PCM_FMTBIT_S16_LE | +#ifdef CONFIG_MACH_XIAOMI_SM8150 + SNDRV_PCM_FMTBIT_S24_3LE | +#endif SNDRV_PCM_FMTBIT_S24_LE), .channels_min = 1, .channels_max = 2, @@ -975,6 +1038,9 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .aif_name = "QUAT_MI2S_DL_HL", .rates = SNDRV_PCM_RATE_8000_384000, .formats = SNDRV_PCM_FMTBIT_S16_LE | +#ifdef CONFIG_MACH_XIAOMI_SM8150 + SNDRV_PCM_FMTBIT_S24_3LE | +#endif SNDRV_PCM_FMTBIT_S24_LE, .channels_min = 1, .channels_max = 8, diff --git a/techpack/audio/asoc/msm-dai-q6-v2.c b/techpack/audio/asoc/msm-dai-q6-v2.c index 7aae0dbe83f5..f314c860b225 100644 --- a/techpack/audio/asoc/msm-dai-q6-v2.c +++ b/techpack/audio/asoc/msm-dai-q6-v2.c @@ -28,6 +28,9 @@ #include #include "msm-dai-q6-v2.h" #include "codecs/core.h" +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI +#include "codecs/tfa98xx/inc/tfa_platform_interface_definition.h" +#endif #define MSM_DAI_PRI_AUXPCM_DT_DEV_ID 1 #define MSM_DAI_SEC_AUXPCM_DT_DEV_ID 2 @@ -5057,6 +5060,18 @@ static int msm_dai_q6_mi2s_hw_params(struct snd_pcm_substream *substream, &mi2s_dai_data->rx_dai : &mi2s_dai_data->tx_dai); struct msm_dai_q6_dai_data *dai_data = &mi2s_dai_config->mi2s_dai_data; struct afe_param_id_i2s_cfg *i2s = &dai_data->port_config.i2s; +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + u16 port_id = 0; +#endif + +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + if (msm_mi2s_get_port_id(dai->id, substream->stream, + &port_id) != 0) { + dev_err(dai->dev, "%s: Invalid Port ID 0x%x\n", + __func__, port_id); + return -EINVAL; + } +#endif dai_data->channels = params_channels(params); switch (dai_data->channels) { @@ -5243,6 +5258,12 @@ static int msm_dai_q6_mi2s_hw_params(struct snd_pcm_substream *substream, mi2s_dai_data->tx_dai.mi2s_dai_data.status_mask) && test_bit(STATUS_PORT_STARTED, mi2s_dai_data->tx_dai.mi2s_dai_data.hwfree_status))) { +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + if (AFE_PORT_ID_TFADSP_RX == port_id || + AFE_PORT_ID_TFADSP_TX == port_id) { + dev_dbg(dai->dev, "%s, port_id = 0x%x\n", __func__, port_id); + } else +#endif if ((mi2s_dai_data->tx_dai.mi2s_dai_data.rate != mi2s_dai_data->rx_dai.mi2s_dai_data.rate) || (mi2s_dai_data->rx_dai.mi2s_dai_data.bitwidth != @@ -8309,7 +8330,11 @@ static int msm_dai_q6_tdm_prepare(struct snd_pcm_substream *substream, * if only one port, don't do group enable as there * is no group need for only one port */ +#ifdef CONFIG_MACH_XIAOMI_NABU + if (dai_data->num_group_ports >= 1) { +#else if (dai_data->num_group_ports > 1) { +#endif rc = afe_port_group_enable(group_id, &dai_data->group_cfg, true); if (rc < 0) { diff --git a/techpack/audio/asoc/msm-pcm-loopback-v2.c b/techpack/audio/asoc/msm-pcm-loopback-v2.c index aa2d8faf0c4f..fca810529788 100644 --- a/techpack/audio/asoc/msm-pcm-loopback-v2.c +++ b/techpack/audio/asoc/msm-pcm-loopback-v2.c @@ -596,6 +596,9 @@ static int msm_pcm_playback_app_type_cfg_ctl_put(struct snd_kcontrol *kcontrol, cfg_data.acdb_dev_id = ucontrol->value.integer.value[1]; if (ucontrol->value.integer.value[2] != 0) cfg_data.sample_rate = ucontrol->value.integer.value[2]; +#ifdef CONFIG_MACH_XIAOMI_NABU + cfg_data.channel = ucontrol->value.integer.value[4]; +#endif pr_debug("%s: fe_id- %llu session_type- %d be_id- %d app_type- %d acdb_dev_id- %d sample_rate- %d\n", __func__, fe_id, session_type, be_id, cfg_data.app_type, cfg_data.acdb_dev_id, cfg_data.sample_rate); @@ -629,6 +632,9 @@ static int msm_pcm_playback_app_type_cfg_ctl_get(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[1] = cfg_data.acdb_dev_id; ucontrol->value.integer.value[2] = cfg_data.sample_rate; ucontrol->value.integer.value[3] = be_id; +#ifdef CONFIG_MACH_XIAOMI_NABU + ucontrol->value.integer.value[4] = cfg_data.channel; +#endif pr_debug("%s: fedai_id %llu, session_type %d, be_id %d, app_type %d, acdb_dev_id %d, sample_rate %d\n", __func__, fe_id, session_type, be_id, cfg_data.app_type, cfg_data.acdb_dev_id, cfg_data.sample_rate); diff --git a/techpack/audio/asoc/msm-pcm-q6-v2.c b/techpack/audio/asoc/msm-pcm-q6-v2.c index e18c88296b0a..972bec329e03 100644 --- a/techpack/audio/asoc/msm-pcm-q6-v2.c +++ b/techpack/audio/asoc/msm-pcm-q6-v2.c @@ -1792,6 +1792,9 @@ static int msm_pcm_playback_app_type_cfg_ctl_put(struct snd_kcontrol *kcontrol, cfg_data.acdb_dev_id = ucontrol->value.integer.value[1]; if (ucontrol->value.integer.value[2] != 0) cfg_data.sample_rate = ucontrol->value.integer.value[2]; +#ifdef CONFIG_MACH_XIAOMI_NABU + cfg_data.channel = ucontrol->value.integer.value[4]; +#endif pr_debug("%s: fe_id- %llu session_type- %d be_id- %d app_type- %d acdb_dev_id- %d sample_rate- %d\n", __func__, fe_id, session_type, be_id, cfg_data.app_type, cfg_data.acdb_dev_id, cfg_data.sample_rate); @@ -1825,6 +1828,9 @@ static int msm_pcm_playback_app_type_cfg_ctl_get(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[1] = cfg_data.acdb_dev_id; ucontrol->value.integer.value[2] = cfg_data.sample_rate; ucontrol->value.integer.value[3] = be_id; +#ifdef CONFIG_MACH_XIAOMI_NABU + ucontrol->value.integer.value[4] = cfg_data.channel; +#endif pr_debug("%s: fedai_id %llu, session_type %d, be_id %d, app_type %d, acdb_dev_id %d, sample_rate %d\n", __func__, fe_id, session_type, be_id, cfg_data.app_type, cfg_data.acdb_dev_id, cfg_data.sample_rate); diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.c b/techpack/audio/asoc/msm-pcm-routing-v2.c index 10f81d246168..28cbaa899fc7 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.c +++ b/techpack/audio/asoc/msm-pcm-routing-v2.c @@ -39,12 +39,33 @@ #include #include #include +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include +#include +#endif +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY +#include +#include +#endif +/* for mius end */ #include "msm-pcm-routing-v2.h" #include "msm-pcm-routing-devdep.h" #include "msm-qti-pp-config.h" #include "msm-dolby-dap-config.h" #include "msm-ds2-dap-config.h" +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI +#include "codecs/tfa98xx/inc/tfa_platform_interface_definition.h" +#endif + +#ifdef CONFIG_MSM_CSPL +#include +#endif + +#ifdef CONFIG_MSM_CSPL_V2 +#include +#endif #ifndef CONFIG_DOLBY_DAP #undef DOLBY_ADM_COPP_TOPOLOGY_ID @@ -85,6 +106,10 @@ static int msm_ec_ref_bit_format = SNDRV_PCM_FORMAT_S16_LE; static int msm_ec_ref_sampling_rate = 48000; static uint32_t voc_session_id = ALL_SESSION_VSID; static int msm_route_ext_ec_ref; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int wakeup_ext_ec_ref = 0; +static int voip_ext_ec_common_ref = 0; +#endif static bool is_custom_stereo_on; static bool is_ds2_on; static bool swap_ch; @@ -1132,6 +1157,13 @@ static int msm_routing_get_adm_topology(int fedai_id, int session_type, { int topology = NULL_COPP_TOPOLOGY; int app_type = 0, acdb_dev_id = 0; +#ifdef CONFIG_MACH_XIAOMI_NABU + bool is_afe_proxy; +#endif + +#ifdef CONFIG_MACH_XIAOMI_NABU + is_afe_proxy = (be_id == MSM_BACKEND_DAI_AFE_PCM_RX); +#endif pr_debug("%s: fedai_id %d, session_type %d, be_id %d\n", __func__, fedai_id, session_type, be_id); @@ -1155,7 +1187,11 @@ static int msm_routing_get_adm_topology(int fedai_id, int session_type, app_type, acdb_dev_id, ADM_TOPOLOGY_CAL_TYPE_IDX, +#ifdef CONFIG_MACH_XIAOMI_NABU + is_afe_proxy /*exact*/); +#else false /*exact*/); +#endif if (topology < 0) topology = NULL_COPP_TOPOLOGY; } @@ -1661,6 +1697,12 @@ int msm_pcm_routing_reg_phy_stream(int fedai_id, int perf_mode, && be_bit_width == 32) bits_per_sample = msm_routing_get_bit_width( SNDRV_PCM_FORMAT_S32_LE); +#ifdef AUDIO_SPEAKER_3D + if((i == 103) && (fe_dai_app_type_cfg[fedai_id][session_type][i].channel != 0)){ + channels = fe_dai_app_type_cfg[fedai_id][session_type][i].channel; + pr_debug("%s before adm_open change fe_dai_app_type_cfg-> channel to %d!!\n",__func__, channels); + } +#endif copp_idx = adm_open(msm_bedais[i].port_id, path_type, sample_rate, channels, topology, perf_mode, bits_per_sample, @@ -3895,9 +3937,23 @@ static const struct snd_kcontrol_new ec_ref_param_controls[] = { static int msm_routing_ec_ref_rx_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct snd_soc_dapm_widget *widget = + snd_soc_dapm_kcontrol_widget(kcontrol); +#endif + pr_debug("%s: ec_ref_rx = %d", __func__, msm_route_ec_ref_rx); mutex_lock(&routing_lock); + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!strncmp(widget->name, "AUDIO_REF_EC_UL10 MUX", strlen("AUDIO_REF_EC_UL10 MUX"))) + ucontrol->value.integer.value[0] = voip_ext_ec_common_ref; + else + ucontrol->value.integer.value[0] = wakeup_ext_ec_ref; +#else ucontrol->value.integer.value[0] = msm_route_ec_ref_rx; +#endif + mutex_unlock(&routing_lock); return 0; } @@ -3910,6 +3966,9 @@ static int msm_routing_ec_ref_rx_put(struct snd_kcontrol *kcontrol, snd_soc_dapm_kcontrol_widget(kcontrol); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; struct snd_soc_dapm_update *update = NULL; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + bool state = true; +#endif mutex_lock(&routing_lock); @@ -3917,6 +3976,9 @@ static int msm_routing_ec_ref_rx_put(struct snd_kcontrol *kcontrol, case 0: msm_route_ec_ref_rx = 0; ec_ref_port_id = AFE_PORT_INVALID; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + state = false; +#endif break; case 1: msm_route_ec_ref_rx = 1; @@ -4063,14 +4125,39 @@ static int msm_routing_ec_ref_rx_put(struct snd_kcontrol *kcontrol, pr_err("%s EC ref rx %ld not valid\n", __func__, ucontrol->value.integer.value[0]); ec_ref_port_id = AFE_PORT_INVALID; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + state = false; +#endif break; } +#ifndef CONFIG_MACH_XIAOMI_SM8150 adm_ec_ref_rx_id(ec_ref_port_id); +#endif pr_debug("%s: msm_route_ec_ref_rx = %d\n", __func__, msm_route_ec_ref_rx); + +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (!strncmp(widget->name, "AUDIO_REF_EC_UL10 MUX", strlen("AUDIO_REF_EC_UL10 MUX"))) + voip_ext_ec_common_ref = msm_route_ec_ref_rx; + else + wakeup_ext_ec_ref = msm_route_ec_ref_rx; +#endif + +#ifndef CONFIG_MACH_XIAOMI_SM8150 mutex_unlock(&routing_lock); snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, msm_route_ec_ref_rx, e, update); +#else + if (state || (!state && wakeup_ext_ec_ref == 0 && voip_ext_ec_common_ref == 0)) { + adm_ec_ref_rx_id(ec_ref_port_id); + mutex_unlock(&routing_lock); + snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, + msm_route_ec_ref_rx, e, update); + } else { + mutex_unlock(&routing_lock); + } +#endif + return 0; } @@ -5744,6 +5831,12 @@ static const struct snd_kcontrol_new tert_mi2s_rx_port_mixer_controls[] = { MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif }; static const struct snd_kcontrol_new quin_mi2s_rx_port_mixer_controls[] = { @@ -17358,7 +17451,18 @@ static const struct snd_kcontrol_new cdc_dma_wsa_switch_mixer_controls = 0, 1, 0, msm_routing_get_switch_mixer, msm_routing_put_switch_mixer); +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static const struct snd_kcontrol_new cdc_dma_rx0_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); +#endif + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static const struct snd_kcontrol_new cdc_dma_rx1_switch_mixer_controls = +#else static const struct snd_kcontrol_new cdc_dma_rx_switch_mixer_controls = +#endif SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, 0, 1, 0, msm_routing_get_switch_mixer, msm_routing_put_switch_mixer); @@ -17643,6 +17747,9 @@ static int msm_routing_put_app_type_cfg_control(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[i++]; } +#ifdef CONFIG_MACH_XIAOMI_NABU + mutex_unlock(&routing_lock); +#endif return 0; } @@ -17804,6 +17911,9 @@ static int msm_routing_get_lsm_app_type_cfg_control( struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { +#ifdef CONFIG_MACH_XIAOMI_NABU + mutex_unlock(&routing_lock); +#endif return 0; } @@ -18562,7 +18672,11 @@ static const char * const wsa_rx_0_vi_fb_tx_rch_mux_text[] = { }; static const char * const mi2s_rx_vi_fb_tx_mux_text[] = { +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + "ZERO", PLATFORM_RX_VI_FB_TX_MUX_TEXT +#else "ZERO", "SENARY_TX" +#endif }; static const char * const int4_mi2s_rx_vi_fb_tx_mono_mux_text[] = { @@ -18591,7 +18705,11 @@ static const int wsa_rx_0_vi_fb_tx_rch_value[] = { static const int mi2s_rx_vi_fb_tx_value[] = { +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + MSM_BACKEND_DAI_MAX, PLATFORM_RX_VI_FB_TX_VALUE +#else MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SENARY_MI2S_TX +#endif }; static const int int4_mi2s_rx_vi_fb_tx_mono_ch_value[] = { @@ -18623,7 +18741,11 @@ static const struct soc_enum wsa_rx_0_vi_fb_rch_mux_enum = wsa_rx_0_vi_fb_tx_rch_mux_text, wsa_rx_0_vi_fb_tx_rch_value); static const struct soc_enum mi2s_rx_vi_fb_mux_enum = +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + SOC_VALUE_ENUM_DOUBLE(SND_SOC_NOPM, PLATFORM_RX_VI_FB_MUX_ENUM, 0, 0, +#else SOC_VALUE_ENUM_DOUBLE(SND_SOC_NOPM, MSM_BACKEND_DAI_PRI_MI2S_RX, 0, 0, +#endif ARRAY_SIZE(mi2s_rx_vi_fb_tx_mux_text), mi2s_rx_vi_fb_tx_mux_text, mi2s_rx_vi_fb_tx_value); @@ -18660,7 +18782,11 @@ static const struct snd_kcontrol_new wsa_rx_0_vi_fb_rch_mux = spkr_prot_put_vi_rch_port); static const struct snd_kcontrol_new mi2s_rx_vi_fb_mux = +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + SOC_DAPM_ENUM_EXT(PLATFORM_RX_VI_FB_MUX_NAME, +#else SOC_DAPM_ENUM_EXT("PRI_MI2S_RX_VI_FB_MUX", +#endif mi2s_rx_vi_fb_mux_enum, spkr_prot_get_vi_lch_port, spkr_prot_put_vi_lch_port); @@ -18738,6 +18864,12 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("TX3_CDC_DMA_UL_HL", "TX3_CDC_DMA_HOSTLESS Capture", 0, 0, 0, 0), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SND_SOC_DAPM_AIF_OUT("TX4_CDC_DMA_UL_US", "ULTRAOUND_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("RX1_CDC_DMA_DL_US", "ULTRAOUND_HOSTLESS Playback", + 0, 0, 0, 0), +#endif SND_SOC_DAPM_AIF_OUT("CPE_LSM_UL_HL", "CPE LSM capture", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SLIM1_DL_HL", "SLIMBUS1_HOSTLESS Playback", @@ -18950,8 +19082,15 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { &a2dp_slim7_switch_mixer_controls), SND_SOC_DAPM_SWITCH("WSA_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_wsa_switch_mixer_controls), +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, // git + &cdc_dma_rx0_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_1_DL_HL", SND_SOC_NOPM, 0, 0, // git + &cdc_dma_rx1_switch_mixer_controls), +#else SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_rx_switch_mixer_controls), +#endif /* Mixer definitions */ SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Audio Mixer", SND_SOC_NOPM, 0, 0, slimbus_rx_mixer_controls, ARRAY_SIZE(slimbus_rx_mixer_controls)), @@ -19569,7 +19708,11 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_mi2s[] = { /* lsm mixer definitions */ /* Virtual Pins to force backends ON atm */ +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + SND_SOC_DAPM_MUX(PLATFORM_RX_VI_FB_MUX_NAME, SND_SOC_NOPM, 0, 0, +#else SND_SOC_DAPM_MUX("PRI_MI2S_RX_VI_FB_MUX", SND_SOC_NOPM, 0, 0, +#endif &mi2s_rx_vi_fb_mux), SND_SOC_DAPM_MUX("INT4_MI2S_RX_VI_FB_MONO_CH_MUX", SND_SOC_NOPM, 0, 0, &int4_mi2s_rx_vi_fb_mono_ch_mux), @@ -21165,7 +21308,15 @@ static const struct snd_soc_dapm_route intercon[] = { {"CDC_DMA_UL_HL", NULL, "VA_CDC_DMA_TX_0"}, {"RX_CDC_DMA_RX_0_DL_HL", "Switch", "CDC_DMA_DL_HL"}, {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0_DL_HL"}, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + {"RX_CDC_DMA_RX_1_DL_HL", "Switch", "CDC_DMA_DL_HL"}, + {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_DL_HL"}, + {"RX_CDC_DMA_RX_1", NULL, "RX1_CDC_DMA_DL_US"}, +#endif {"TX3_CDC_DMA_UL_HL", NULL, "TX_CDC_DMA_TX_3"}, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + {"TX4_CDC_DMA_UL_US", NULL, "TX_CDC_DMA_TX_4"}, +#endif {"LSM1 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, {"LSM1 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, {"LSM1 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, @@ -23525,11 +23676,19 @@ static const struct snd_soc_dapm_route intercon_mi2s[] = { {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX_DL_HL"}, {"INT4_MI2S_RX_DL_HL", "Switch", "INT4_MI2S_DL_HL"}, {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_DL_HL"}, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + {"PRI_MI2S_RX_DL_HL", "Switch", "CDC_DMA_DL_HL"}, +#else {"PRI_MI2S_RX_DL_HL", "Switch", "PRI_MI2S_DL_HL"}, +#endif {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX_DL_HL"}, {"SEC_MI2S_RX_DL_HL", "Switch", "SEC_MI2S_DL_HL"}, {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX_DL_HL"}, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + {"TERT_MI2S_RX_DL_HL", "Switch", "CDC_DMA_DL_HL"}, +#else {"TERT_MI2S_RX_DL_HL", "Switch", "TERT_MI2S_DL_HL"}, +#endif {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX_DL_HL"}, {"QUAT_MI2S_RX_DL_HL", "Switch", "QUAT_MI2S_DL_HL"}, @@ -23657,6 +23816,9 @@ static const struct snd_soc_dapm_route intercon_mi2s[] = { {"TERT_MI2S_RX Port Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, {"TERT_MI2S_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"TERT_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + {"TERT_MI2S_RX Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX Port Mixer"}, {"QUAT_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, @@ -23712,10 +23874,18 @@ static const struct snd_soc_dapm_route intercon_mi2s[] = { {"INT5_MI2S_TX", NULL, "BE_IN"}, {"SEC_MI2S_TX", NULL, "BE_IN"}, {"SENARY_MI2S_TX", NULL, "BE_IN"}, +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + {PLATFORM_RX_VI_FB_MUX_NAME, PLATFORM_RX_VI_FB_TX_MUX_TEXT, PLATFORM_RX_VI_FB_TX_MUX_TEXT}, +#else {"PRI_MI2S_RX_VI_FB_MUX", "SENARY_TX", "SENARY_TX"}, +#endif {"INT4_MI2S_RX_VI_FB_MONO_CH_MUX", "INT5_MI2S_TX", "INT5_MI2S_TX"}, {"INT4_MI2S_RX_VI_FB_STEREO_CH_MUX", "INT5_MI2S_TX", "INT5_MI2S_TX"}, +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + {PLATFORM_RX_VI_FB_RX_MUX_TEXT, NULL, PLATFORM_RX_VI_FB_MUX_NAME}, +#else {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX_VI_FB_MUX"}, +#endif {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_VI_FB_MONO_CH_MUX"}, {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_VI_FB_STEREO_CH_MUX"}, }; @@ -23935,6 +24105,12 @@ static int msm_pcm_routing_prepare(struct snd_pcm_substream *substream) be_bit_width == 32) bits_per_sample = msm_routing_get_bit_width( SNDRV_PCM_FORMAT_S32_LE); +#ifdef AUDIO_SPEAKER_3D + if((be_id == 103) && (fe_dai_app_type_cfg[i][session_type][be_id].channel != 0)){ + channels = fe_dai_app_type_cfg[i][session_type][be_id].channel; + pr_debug("%s before adm_open change fe_dai_app_type_cfg-> channel to %d!!\n",__func__, channels); + } +#endif copp_idx = adm_open(bedai->port_id, path_type, sample_rate, channels, topology, fdai->perf_mode, bits_per_sample, @@ -24629,6 +24805,10 @@ static int msm_routing_probe(struct snd_soc_platform *platform) msm_routing_be_dai_name_table_mixer_controls, ARRAY_SIZE(msm_routing_be_dai_name_table_mixer_controls)); +#ifdef CONFIG_MSM_CSPL_V2 + msm_crus_pb_add_controls(&platform->component); +#endif + snd_soc_add_platform_controls(platform, msm_source_tracking_controls, ARRAY_SIZE(msm_source_tracking_controls)); snd_soc_add_platform_controls(platform, adm_channel_config_controls, @@ -24644,6 +24824,14 @@ static int msm_routing_probe(struct snd_soc_platform *platform) snd_soc_add_platform_controls(platform, port_multi_channel_map_mixer_controls, ARRAY_SIZE(port_multi_channel_map_mixer_controls)); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + elliptic_add_platform_controls(platform); +#endif + /* for mius start */ +#ifdef CONFIG_US_PROXIMITY + mius_add_platform_controls(platform); +#endif + /* for mius end */ return 0; } diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.h b/techpack/audio/asoc/msm-pcm-routing-v2.h index 8f56c1f947d9..a597042b26c3 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.h +++ b/techpack/audio/asoc/msm-pcm-routing-v2.h @@ -564,6 +564,9 @@ struct msm_pcm_stream_app_type_cfg { int app_type; int acdb_dev_id; int sample_rate; +#ifdef CONFIG_MACH_XIAOMI_NABU + int channel; +#endif }; /* dai_id: front-end ID, diff --git a/techpack/audio/asoc/sm8150.c b/techpack/audio/asoc/sm8150.c index 14d65162c5a5..634b2da74335 100644 --- a/techpack/audio/asoc/sm8150.c +++ b/techpack/audio/asoc/sm8150.c @@ -39,6 +39,12 @@ #include "codecs/wcd9360/wcd9360.h" #include "codecs/wsa881x.h" #include "codecs/wcd-mbhc-v2.h" +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +#include +#endif +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI +#include "codecs/tfa98xx/inc/tfa_platform_interface_definition.h" +#endif #define DRV_NAME "sm8150-asoc-snd" @@ -68,6 +74,10 @@ #define WCN_CDC_SLIM_RX_CH_MAX 2 #define WCN_CDC_SLIM_TX_CH_MAX 3 +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) +#define CS35L41_CODEC_NAME "cs35l41.0-0040" +#endif + #define ADSP_STATE_READY_TIMEOUT_MS 3000 #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */ #define MSM_HIFI_ON 1 @@ -75,6 +85,52 @@ #define TDM_MAX_SLOTS 8 #define TDM_SLOT_WIDTH_BITS 32 +#ifdef CONFIG_MACH_XIAOMI_NABU +#define CS35L41_PA_TL_NAME "cs35l41.2-0043" +#define CS35L41_PA_TR_NAME "cs35l41.2-0041" +#define CS35L41_PA_BL_NAME "cs35l41.2-0042" +#define CS35L41_PA_BR_NAME "cs35l41.2-0040" + +struct snd_soc_dai_link_component cs35l41_codec_components[] = { + { + .name = CS35L41_PA_TL_NAME, + .dai_name = CS35L41_PA_TL_NAME, + }, + { + .name = CS35L41_PA_TR_NAME, + .dai_name = CS35L41_PA_TR_NAME, + }, + { + .name = CS35L41_PA_BL_NAME, + .dai_name = CS35L41_PA_BL_NAME, + }, + { + .name = CS35L41_PA_BR_NAME, + .dai_name = CS35L41_PA_BR_NAME, + }, + +}; + +static struct snd_soc_codec_conf cs35l41_codec_conf[] = { + { + .dev_name = CS35L41_PA_TL_NAME, + .name_prefix = "TL", + }, + { + .dev_name = CS35L41_PA_TR_NAME, + .name_prefix = "TR", + }, + { + .dev_name = CS35L41_PA_BL_NAME, + .name_prefix = "BL", + }, + { + .dev_name = CS35L41_PA_BR_NAME, + .name_prefix = "BR", + }, +}; +#endif + enum { SLIM_RX_0 = 0, SLIM_RX_1, @@ -170,10 +226,19 @@ struct msm_pinctrl_info { struct msm_asoc_mach_data { struct snd_info_entry *codec_root; struct msm_pinctrl_info pinctrl_info; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + int usbc_en2_gpio; /* used by gpio driver API */ +#endif struct device_node *us_euro_gpio_p; /* used by pinctrl API */ +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */ +#endif struct device_node *hph_en1_gpio_p; /* used by pinctrl API */ struct device_node *hph_en0_gpio_p; /* used by pinctrl API */ struct device_node *fsa_handle; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + struct device_node *adc2_sel_gpio_p; /* used by pinctrl API */ +#endif struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */ struct snd_soc_codec *codec; struct work_struct adsp_power_up_work; @@ -410,7 +475,11 @@ static struct tdm_dev_config tdm_cfg[TDM_INTERFACE_MAX * 2] { {0xFFFF} }, /* TX_7 */ }, { /* QUAT TDM */ +#ifdef CONFIG_MACH_XIAOMI_NABU + { {0, 4, 8, 12, 0xFFFF} }, /* RX_0 */ +#else { {0, 4, 0xFFFF} }, /* RX_0 */ +#endif { {8, 12, 0xFFFF} }, /* RX_1 */ { {16, 20, 0xFFFF} }, /* RX_2 */ { {24, 28, 0xFFFF} }, /* RX_3 */ @@ -467,7 +536,11 @@ static struct dev_config mi2s_tx_cfg[] = { [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, +#else [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, +#endif [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, }; @@ -636,9 +709,15 @@ static struct wcd_mbhc_config wcd_mbhc_cfg = { .swap_gnd_mic = NULL, .hs_ext_micbias = true, .key_code[0] = KEY_MEDIA, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + .key_code[1] = BTN_1, + .key_code[2] = BTN_2, + .key_code[3] = 0, +#else .key_code[1] = KEY_VOICECOMMAND, .key_code[2] = KEY_VOLUMEUP, .key_code[3] = KEY_VOLUMEDOWN, +#endif .key_code[4] = 0, .key_code[5] = 0, .key_code[6] = 0, @@ -2950,6 +3029,41 @@ static int msm_hifi_put(struct snd_kcontrol *kcontrol, return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static int usbhs_direction_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ +#ifdef CONFIG_MACH_XIAOMI_NABU + if (wcd_mbhc_cfg.flip_switch) + ucontrol->value.integer.value[0] = 1; + else + ucontrol->value.integer.value[0] = 0; +#else + struct snd_soc_codec *codec = NULL; + struct snd_soc_card *card = NULL; + struct msm_asoc_mach_data *pdata = NULL; + + ucontrol->value.integer.value[0] = 0; + + codec = snd_soc_kcontrol_codec(kcontrol); + if (codec) { + card = codec->component.card; + if (card) { + pdata = snd_soc_card_get_drvdata(card); + if (pdata){ + if (pdata->usbc_en2_gpio_p) { + ucontrol->value.integer.value[0] = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + } else if (pdata->usbc_en2_gpio > 0) { + ucontrol->value.integer.value[0] = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + } + } + } + } +#endif + return 0; +} +#endif + static const struct snd_kcontrol_new msm_snd_controls[] = { SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs, slim_rx_ch_get, slim_rx_ch_put), @@ -3236,6 +3350,10 @@ static const struct snd_kcontrol_new msm_snd_controls[] = { msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put), SOC_ENUM_EXT("HiFi Function", hifi_function, msm_hifi_get, msm_hifi_put), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + SOC_SINGLE_EXT("USB Headset Direction", 0, 0, UINT_MAX, 0, + usbhs_direction_get, NULL), +#endif SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0, 4, NULL, tdm_slot_map_put), @@ -3342,6 +3460,52 @@ static int msm_hifi_ctrl_event(struct snd_soc_dapm_widget *w, return 0; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static void external_enable_dual_adc_gpio(struct device_node *np, bool val) +{ + if (!np) { + pr_err("%s: device node is NULL!", __func__); + return; + } + + if (val == 1) { + msm_cdc_pinctrl_select_active_state(np); + pr_info("%s: enable Dual ADC \n", __func__); + } else { + msm_cdc_pinctrl_select_sleep_state(np); + pr_info("%s: disable Dual ADC \n", __func__); + } +} + +static int external_amic2_sel_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct snd_soc_card *card = dapm->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + unsigned int val; + + val = ucontrol->value.enumerated.item[0]; + + if (!pdata || !pdata->adc2_sel_gpio_p) { + pr_err("%s: adc2_sel_gpio is invalid\n", __func__); + return -EINVAL; + } + + pr_info("external_amic2_sel_put %u \n", val); + + return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); +} + +static const char *const external_AMIC2_enum_text[] = {"default", "Dual_ADC"}; + +static SOC_ENUM_SINGLE_VIRT_DECL(external_AMIC2_enum, external_AMIC2_enum_text); + +static const struct snd_kcontrol_new ext_amc2_mux = + SOC_DAPM_ENUM_EXT("External AMIC2 sel", external_AMIC2_enum, + snd_soc_dapm_get_enum_double, external_amic2_sel_put); +#endif + static const struct snd_soc_dapm_widget msm_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, @@ -3390,8 +3554,25 @@ static const struct snd_soc_dapm_widget msm_dapm_widgets_tavil[] = { SND_SOC_DAPM_MIC("Digital Mic3", NULL), SND_SOC_DAPM_MIC("Digital Mic4", NULL), SND_SOC_DAPM_MIC("Digital Mic5", NULL), +#ifdef CONFIG_MACH_XIAOMI_SM8150 + SND_SOC_DAPM_MIC("Headset Mic2", NULL), +#endif }; +#ifdef CONFIG_MACH_XIAOMI_SM8150 +static const struct snd_soc_dapm_widget msm_dualadc_dapm_widgets[] = { + SND_SOC_DAPM_MUX("External AMIC2 Mux", SND_SOC_NOPM, 0, 0, &ext_amc2_mux), + SND_SOC_DAPM_INPUT("AMIC2_EXT_0"), + SND_SOC_DAPM_INPUT("AMIC2_EXT_1"), +}; // git + +static const struct snd_soc_dapm_route msm_dualadc_dapm_routes[] = { + {"AMIC2", NULL, "External AMIC2 Mux"}, + {"External AMIC2 Mux", "default", "AMIC2_EXT_0"}, + {"External AMIC2 Mux", "Dual_ADC", "AMIC2_EXT_1"}, +}; // git +#endif + static inline int param_is_mask(int p) { return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && @@ -3870,10 +4051,116 @@ static bool msm_usbc_swap_gnd_mic(struct snd_soc_codec *codec, bool active) struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !defined(CONFIG_MACH_XIAOMI_NABU) + struct pinctrl_state *en2_pinctrl_active; + struct pinctrl_state *en2_pinctrl_sleep; + int value = 0; + bool ret = 0; + int oldv; + + if (wcd_mbhc_cfg.use_fsa4476_gpio != 0) { + if (!pdata->usbc_en2_gpio_p) { + if (active) { + /* if active and usbc_en2_gpio undefined, get pin */ + pdata->usbc_en2_gpio_p = devm_pinctrl_get(card->dev); + if (IS_ERR_OR_NULL(pdata->usbc_en2_gpio_p)) { + dev_err(card->dev, + "%s: Can't get EN2 gpio pinctrl:%ld\n", + __func__, + PTR_ERR(pdata->usbc_en2_gpio_p)); + pdata->usbc_en2_gpio_p = NULL; + return false; + } + } else + /* if not active and usbc_en2_gpio undefined, return */ + return false; + } + + pdata->usbc_en2_gpio = of_get_named_gpio(card->dev->of_node, + "qcom,usbc-analog-en2-gpio", 0); + if (!gpio_is_valid(pdata->usbc_en2_gpio)) { + dev_err(card->dev, "%s, property %s not in node %s", + __func__, "qcom,usbc-analog-en2-gpio", + card->dev->of_node->full_name); + return false; + } + + en2_pinctrl_active = pinctrl_lookup_state( + pdata->usbc_en2_gpio_p, "aud_active"); + if (IS_ERR_OR_NULL(en2_pinctrl_active)) { + dev_err(card->dev, + "%s: Cannot get aud_active pinctrl state:%ld\n", + __func__, PTR_ERR(en2_pinctrl_active)); + ret = false; + goto err_lookup_state; + } + + en2_pinctrl_sleep = pinctrl_lookup_state( + pdata->usbc_en2_gpio_p, "aud_sleep"); + if (IS_ERR_OR_NULL(en2_pinctrl_sleep)) { + dev_err(card->dev, + "%s: Cannot get aud_sleep pinctrl state:%ld\n", + __func__, PTR_ERR(en2_pinctrl_sleep)); + ret = false; + goto err_lookup_state; + } + + /* if active and usbc_en2_gpio_p defined, swap using usbc_en2_gpio_p */ + if (active) { + dev_dbg(codec->dev, "%s: enter\n", __func__); + oldv = tavil_mb_pull_down(codec, true, 0); + if (wcd_mbhc_cfg.usbc_analog_cfg.euro_us_hw_switch_gpio_p) { + value = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + if (value) + msm_cdc_pinctrl_select_sleep_state( + wcd_mbhc_cfg.usbc_analog_cfg.euro_us_hw_switch_gpio_p); + else + msm_cdc_pinctrl_select_active_state( + wcd_mbhc_cfg.usbc_analog_cfg.euro_us_hw_switch_gpio_p); + } + else if (pdata->usbc_en2_gpio_p) { + value = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + if (value) + pinctrl_select_state(pdata->usbc_en2_gpio_p, + en2_pinctrl_sleep); + else + pinctrl_select_state(pdata->usbc_en2_gpio_p, + en2_pinctrl_active); + } else if (pdata->usbc_en2_gpio >= 0) { + value = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + gpio_set_value_cansleep(pdata->usbc_en2_gpio, !value); + } + tavil_mb_pull_down(codec, false, oldv); + pr_info("%s: swap select switch %d to %d\n", __func__, + value, !value); + ret = true; + } else { + /* if not active, release usbc_en2_gpio_p pin */ + pinctrl_select_state(pdata->usbc_en2_gpio_p, + en2_pinctrl_sleep); + } + } else { +#endif if (!pdata->fsa_handle) return false; +#ifdef CONFIG_MACH_XIAOMI_NABU + wcd_mbhc_cfg.flip_switch = true; +#endif + return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP); +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !defined(CONFIG_MACH_XIAOMI_NABU) + } // git + + +err_lookup_state: + if (wcd_mbhc_cfg.use_fsa4476_gpio != 0) { + devm_pinctrl_put(pdata->usbc_en2_gpio_p); + pdata->usbc_en2_gpio_p = NULL; + } // git + + return ret; +#endif } static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active) @@ -4146,6 +4433,17 @@ static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) ARRAY_SIZE(wcd_audio_paths)); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (pdata->adc2_sel_gpio_p) { + pr_info("add the External AMIC2 Mux\n"); + snd_soc_dapm_new_controls(dapm, msm_dualadc_dapm_widgets, + ARRAY_SIZE(msm_dualadc_dapm_widgets)); + + snd_soc_dapm_add_routes(dapm, msm_dualadc_dapm_routes, + ARRAY_SIZE(msm_dualadc_dapm_routes)); + } +#endif + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0"); snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); @@ -4166,6 +4464,14 @@ static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) snd_soc_dapm_ignore_suspend(dapm, "WDMA3_OUT"); if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) { +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (pdata->adc2_sel_gpio_p) { + snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2_EXT_0"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2_EXT_1"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic2"); + } +#endif snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); snd_soc_dapm_ignore_suspend(dapm, "ANCRight Headset Mic"); snd_soc_dapm_ignore_suspend(dapm, "ANCLeft Headset Mic"); @@ -4306,6 +4612,25 @@ static void *def_wcd_mbhc_cal(void) btn_high = ((void *)&btn_cfg->_v_btn_low) + (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); +#ifdef CONFIG_MACH_XIAOMI_NABU + btn_high[0] = 75; + btn_high[1] = 225; + btn_high[2] = 450; + btn_high[3] = 500; + btn_high[4] = 500; + btn_high[5] = 500; + btn_high[6] = 500; + btn_high[7] = 500; +#elif defined(CONFIG_MACH_XIAOMI_SM8150) + btn_high[0] = 75; + btn_high[1] = 260; + btn_high[2] = 750; + btn_high[3] = 750; + btn_high[4] = 750; + btn_high[5] = 750; + btn_high[6] = 750; + btn_high[7] = 750; +#else btn_high[0] = 75; btn_high[1] = 150; btn_high[2] = 237; @@ -4314,6 +4639,7 @@ static void *def_wcd_mbhc_cal(void) btn_high[5] = 500; btn_high[6] = 500; btn_high[7] = 500; +#endif return wcd_mbhc_cal; } @@ -5063,6 +5389,12 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) } } } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + snd_soc_codec_set_sysclk(rtd->codec_dai->codec, 0, 0, + mi2s_clk[index].clk_freq_in_hz, + SND_SOC_CLOCK_IN); +#endif + clk_off: if (ret < 0) msm_mi2s_set_sclk(substream, false); @@ -5744,6 +6076,25 @@ static struct snd_soc_dai_link msm_pahu_fe_dai_links[] = { }; static struct snd_soc_dai_link msm_tavil_fe_dai_links[] = { +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + { + .name = TFA_TX_HOSTLESS_CODEC_NAME, + .stream_name = TFA_TX_HOSTLESS_STREAM_NAME, + .cpu_dai_name = TFA_TX_HOSTLESS_CPU_DAI_NAME, + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, +#else { .name = LPASS_BE_SLIMBUS_4_TX, .stream_name = "Slimbus4 Capture", @@ -5757,6 +6108,7 @@ static struct snd_soc_dai_link msm_tavil_fe_dai_links[] = { .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, .ignore_suspend = 1, }, +#endif /* Ultrasound RX DAI Link */ { .name = "SLIMBUS_2 Hostless Playback", @@ -5849,6 +6201,38 @@ static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = { .ignore_pmdown_time = 1, .id = MSM_FRONTEND_DAI_MULTIMEDIA17, }, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + { + .name = "Quaternary MI2S_RX Hostless Playback", + .stream_name = "Quaternary MI2S_RX Hostless Playback", + .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { + .name = "Quaternary MI2S_TX Hostless Capture", + .stream_name = "Quaternary MI2S_TX Hostless Capture", + .cpu_dai_name = "QUAT_MI2S_TX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, +#endif { .name = "MultiMedia30 Playback", .stream_name = "MultiMedia30", @@ -5879,6 +6263,7 @@ static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = { .ignore_pmdown_time = 1, .id = MSM_FRONTEND_DAI_MULTIMEDIA31, }, +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) { .name = "Quaternary MI2S_RX Hostless Playback", .stream_name = "Quaternary MI2S_RX Hostless Playback", @@ -5909,6 +6294,7 @@ static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = { .codec_dai_name = "snd-soc-dummy-dai", .codec_name = "snd-soc-dummy", }, +#endif /* Voice Stub */ { .name = "Voice Stub", @@ -6158,6 +6544,7 @@ static struct snd_soc_dai_link msm_common_be_dai_links[] = { .ops = &sm8150_tdm_be_ops, .ignore_suspend = 1, }, +#ifndef CONFIG_MACH_XIAOMI_NABU { .name = LPASS_BE_QUAT_TDM_RX_0, .stream_name = "Quaternary TDM0 Playback", @@ -6173,6 +6560,7 @@ static struct snd_soc_dai_link msm_common_be_dai_links[] = { .ignore_suspend = 1, .ignore_pmdown_time = 1, }, +#endif { .name = LPASS_BE_QUAT_TDM_TX_0, .stream_name = "Quaternary TDM0 Capture", @@ -6751,13 +7139,19 @@ static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { .ops = &msm_mi2s_be_ops, .ignore_suspend = 1, }, +#if !defined(CONFIG_MACH_XIAOMI_SM8150) || defined(CONFIG_MACH_XIAOMI_VAYU) { .name = LPASS_BE_QUAT_MI2S_RX, .stream_name = "Quaternary MI2S Playback", .cpu_dai_name = "msm-dai-q6-mi2s.3", .platform_name = "msm-pcm-routing", +#ifdef CONFIG_SND_SOC_TAS256X + .codec_name = "tas256x.1-004c", + .codec_dai_name = "tas256x ASI1", +#else .codec_name = "msm-stub-codec.1", .codec_dai_name = "msm-stub-rx", +#endif .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, @@ -6766,13 +7160,20 @@ static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { .ignore_suspend = 1, .ignore_pmdown_time = 1, }, +#endif +#ifndef CONFIG_MACH_XIAOMI_NABU { .name = LPASS_BE_QUAT_MI2S_TX, .stream_name = "Quaternary MI2S Capture", .cpu_dai_name = "msm-dai-q6-mi2s.3", .platform_name = "msm-pcm-routing", +#ifdef CONFIG_SND_SOC_TAS256X + .codec_name = "tas256x.1-004c", + .codec_dai_name = "tas256x ASI1", +#else .codec_name = "msm-stub-codec.1", .codec_dai_name = "msm-stub-tx", +#endif .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, @@ -6780,6 +7181,7 @@ static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { .ops = &msm_mi2s_be_ops, .ignore_suspend = 1, }, +#endif { .name = LPASS_BE_QUIN_MI2S_RX, .stream_name = "Quinary MI2S Playback", @@ -6812,6 +7214,80 @@ static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { }; +#ifdef CONFIG_MACH_XIAOMI_NABU +static struct snd_soc_dai_link quat_mi2s_rx_cs35l41_dai_links[] = { + { + .name = LPASS_BE_QUAT_TDM_RX_0, + .stream_name = "Quaternary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36912", + .platform_name = "msm-pcm-routing", + .codecs = cs35l41_codec_components, + .num_codecs = ARRAY_SIZE(cs35l41_codec_components), + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &sm8150_tdm_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, +}; +#elif defined(CONFIG_MACH_XIAOMI_SM8150) && !defined(CONFIG_MACH_XIAOMI_VAYU) +static struct snd_soc_dai_link quat_mi2s_rx_tas2557_dai_links[] = { + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_name = "tas2557.1-004c", + .codec_dai_name = "tas2557 ASI1", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, +}; + +static struct snd_soc_dai_link quat_mi2s_rx_tfa9874_dai_links[] = { + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_name = "tfa98xx.1-0034", + .codec_dai_name = "tfa98xx-aif-1-34", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, +}; + +static struct snd_soc_dai_link quat_mi2s_rx_cs35l41_dai_links[] = { + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_name = CS35L41_CODEC_NAME, + .codec_dai_name = "cs35l41-pcm", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, +}; +#endif + static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = { /* Primary AUX PCM Backend DAI Links */ { @@ -6974,6 +7450,11 @@ static struct snd_soc_dai_link msm_tavil_dai_links[ ARRAY_SIZE(msm_wcn_be_dai_links) + ARRAY_SIZE(ext_disp_be_dai_link) + ARRAY_SIZE(msm_mi2s_be_dai_links) + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + ARRAY_SIZE(quat_mi2s_rx_tas2557_dai_links) + + ARRAY_SIZE(quat_mi2s_rx_tfa9874_dai_links) + + ARRAY_SIZE(quat_mi2s_rx_cs35l41_dai_links) + +#endif ARRAY_SIZE(msm_auxpcm_be_dai_links)]; static int msm_snd_card_tavil_late_probe(struct snd_soc_card *card) @@ -6982,6 +7463,11 @@ static int msm_snd_card_tavil_late_probe(struct snd_soc_card *card) struct snd_soc_pcm_runtime *rtd; int ret = 0; void *mbhc_calibration; +#ifdef CONFIG_SND_SOC_CS35L41_FOR_CEPH + struct snd_soc_dai_link *dai_link; + struct snd_soc_codec *cs35l41_codec; + struct snd_soc_dapm_context * cs35l41_dapm; +#endif rtd = snd_soc_get_pcm_runtime(card, be_dl_name); if (!rtd) { @@ -7004,6 +7490,28 @@ static int msm_snd_card_tavil_late_probe(struct snd_soc_card *card) __func__, ret); goto err_hs_detect; } + +#ifdef CONFIG_SND_SOC_CS35L41_FOR_CEPH + dai_link = rtd->dai_link; + if (dai_link && dai_link->codec_name) { + if (!strcmp(dai_link->codec_name, CS35L41_CODEC_NAME)) { + dev_info(card->dev, "%s: found codec[%s]\n", __func__, CS35L41_CODEC_NAME); + cs35l41_codec = rtd->codec; + cs35l41_dapm = snd_soc_codec_get_dapm(cs35l41_codec); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "AMP Playback"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "AMP Capture"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "DSP1"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "Main AMP"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "ASPRX1"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "ASPRX2"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "ASPTX1"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "ASPTX2"); + snd_soc_dapm_ignore_suspend(cs35l41_dapm, "SPK"); + snd_soc_dapm_sync(cs35l41_dapm); + } + } +#endif + return 0; err_hs_detect: @@ -7019,6 +7527,10 @@ struct snd_soc_card snd_soc_card_pahu_msm = { struct snd_soc_card snd_soc_card_tavil_msm = { .name = "sm8150-tavil-snd-card", +#ifdef CONFIG_MACH_XIAOMI_NABU + .codec_conf = cs35l41_codec_conf, + .num_configs = ARRAY_SIZE(cs35l41_codec_conf), +#endif .late_probe = msm_snd_card_tavil_late_probe, }; @@ -7378,6 +7890,30 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev) msm_mi2s_be_dai_links, sizeof(msm_mi2s_be_dai_links)); total_links += ARRAY_SIZE(msm_mi2s_be_dai_links); + +#if defined(CONFIG_MACH_XIAOMI_SM8150) && !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) + if (get_hw_version_platform() == HARDWARE_PLATFORM_ANDROMEDA) { + memcpy(msm_tavil_dai_links + total_links, + quat_mi2s_rx_tas2557_dai_links, + sizeof(quat_mi2s_rx_tas2557_dai_links)); + total_links += ARRAY_SIZE(quat_mi2s_rx_tas2557_dai_links); + } else if (get_hw_version_platform() == HARDWARE_PLATFORM_CEPHEUS) { + memcpy(msm_tavil_dai_links + total_links, + quat_mi2s_rx_cs35l41_dai_links, + sizeof(quat_mi2s_rx_cs35l41_dai_links)); + total_links += ARRAY_SIZE(quat_mi2s_rx_cs35l41_dai_links); + } else if (get_hw_version_platform() == HARDWARE_PLATFORM_RAPHAEL) { + memcpy(msm_tavil_dai_links + total_links, + quat_mi2s_rx_tfa9874_dai_links, + sizeof(quat_mi2s_rx_tfa9874_dai_links)); + total_links += ARRAY_SIZE(quat_mi2s_rx_tfa9874_dai_links); + } +#elif defined(CONFIG_MACH_XIAOMI_NABU) + memcpy(msm_tavil_dai_links + total_links, + quat_mi2s_rx_cs35l41_dai_links, + sizeof(quat_mi2s_rx_cs35l41_dai_links)); + total_links += ARRAY_SIZE(quat_mi2s_rx_cs35l41_dai_links); +#endif } ret = of_property_read_u32(dev->of_node, @@ -7715,6 +8251,27 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) platform_set_drvdata(pdev, card); snd_soc_card_set_drvdata(card, pdata); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + pdata->adc2_sel_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,adc2-switch-gpio", 0); + if (!pdata->adc2_sel_gpio_p) { + dev_err(&pdev->dev, "property %s not detected in node %s", + "qcom,adc2-switch-gpio", + pdev->dev.of_node->full_name); + } + + wcd_mbhc_cfg.dual_adc_gpio_node = pdata->adc2_sel_gpio_p; + wcd_mbhc_cfg.enable_dual_adc_gpio = external_enable_dual_adc_gpio; + + pdata->usbc_en2_gpio = of_get_named_gpio(card->dev->of_node, + "qcom,usbc-analog-en2-gpio", 0); + if (!gpio_is_valid(pdata->usbc_en2_gpio)) { + dev_err(card->dev, "%s, property %s not in node %s", + __func__, "qcom,usbc-analog-en2-gpio", + card->dev->of_node->full_name); + } +#endif + ret = snd_soc_of_parse_card_name(card, "qcom,model"); if (ret) { dev_err(&pdev->dev, "parse card name failed, err:%d\n", diff --git a/techpack/audio/dsp/Kbuild b/techpack/audio/dsp/Kbuild index aaddbd54bb80..6927d36c064b 100644 --- a/techpack/audio/dsp/Kbuild +++ b/techpack/audio/dsp/Kbuild @@ -189,6 +189,14 @@ CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ -Werror\ -D__linux__ +ifeq (y, $(filter y,$(CONFIG_MACH_XIAOMI_RAPHAEL))) + CDEFINES += -DCONFIG_SND_SOC_TFA9874_FOR_DAVI +endif + +ifeq (y, $(filter y,$(CONFIG_MACH_XIAOMI_NABU))) + CDEFINES += -DAUDIO_FORCE_RESTART_ADSP +endif + KBUILD_CPPFLAGS += $(CDEFINES) # Currently, for versions of gcc which support it, the kernel Makefile diff --git a/techpack/audio/dsp/q6_init.c b/techpack/audio/dsp/q6_init.c index 202955a96040..3f9f7963cae7 100644 --- a/techpack/audio/dsp/q6_init.c +++ b/techpack/audio/dsp/q6_init.c @@ -31,14 +31,28 @@ static int __init audio_q6_init(void) msm_audio_ion_init(); audio_slimslave_init(); avtimer_init(); +#if defined(CONFIG_MSM_CSPL) || defined(CONFIG_MSM_CSPL_V2) + crus_sp_init(); +#endif msm_mdf_init(); voice_mhi_init(); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + elliptic_driver_init(); +#endif +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY + mius_driver_init(); +#endif +/* for mius end */ return 0; } static void __exit audio_q6_exit(void) { msm_mdf_exit(); +#if defined(CONFIG_MSM_CSPL) || defined(CONFIG_MSM_CSPL_V2) + crus_sp_exit(); +#endif avtimer_exit(); audio_slimslave_exit(); msm_audio_ion_exit(); @@ -53,6 +67,14 @@ static void __exit audio_q6_exit(void) audio_cal_exit(); adsp_err_exit(); voice_mhi_exit(); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + elliptic_driver_exit(); +#endif +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY + mius_driver_exit(); +#endif +/* for mius end */ } module_init(audio_q6_init); diff --git a/techpack/audio/dsp/q6_init.h b/techpack/audio/dsp/q6_init.h index 5014c37a6c32..8ad91d7d7237 100644 --- a/techpack/audio/dsp/q6_init.h +++ b/techpack/audio/dsp/q6_init.h @@ -26,6 +26,17 @@ int rtac_init(void); int msm_audio_ion_init(void); int audio_slimslave_init(void); int avtimer_init(void); +#if defined(CONFIG_MSM_CSPL) || defined(CONFIG_MSM_CSPL_V2) +int crus_sp_init(void); +#endif +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int elliptic_driver_init(void); +#endif +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY +int mius_driver_init(void); +#endif +/* for mius end */ #ifdef CONFIG_MSM_MDF int msm_mdf_init(void); void msm_mdf_exit(void); @@ -53,6 +64,9 @@ static inline void spk_params_exit(void) } #endif +#if defined(CONFIG_MSM_CSPL) || defined(CONFIG_MSM_CSPL_V2) +void crus_sp_exit(void); +#endif void avtimer_exit(void); void audio_slimslave_exit(void); void msm_audio_ion_exit(void); @@ -65,6 +79,14 @@ void q6asm_exit(void); void afe_exit(void); void adm_exit(void); void adsp_err_exit(void); +#ifdef CONFIG_MACH_XIAOMI_SM8150 +int elliptic_driver_exit(void); +#endif +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY +int mius_driver_exit(void); +#endif +/* for mius end */ #ifdef CONFIG_VOICE_MHI int voice_mhi_init(void); diff --git a/techpack/audio/dsp/q6adm.c b/techpack/audio/dsp/q6adm.c index 183fef90c764..9c02cf3e7191 100644 --- a/techpack/audio/dsp/q6adm.c +++ b/techpack/audio/dsp/q6adm.c @@ -29,6 +29,10 @@ #include #include "adsp_err.h" +#ifdef CONFIG_MSM_CSPL_V2 +#include +#endif + #define TIMEOUT_MS 1000 #define RESET_COPP_ID 99 @@ -56,6 +60,11 @@ enum adm_cal_status { ADM_STATUS_MAX, }; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +static bool is_usb_timeout = false; +static bool close_usb = false; +#endif + struct adm_copp { atomic_t id[AFE_MAX_PORTS][MAX_COPPS_PER_PORT]; @@ -900,6 +909,88 @@ int adm_set_custom_chmix_cfg(int port_id, int copp_idx, } EXPORT_SYMBOL(adm_set_custom_chmix_cfg); +#ifdef CONFIG_MSM_CSPL_V2 +int crus_adm_set_params(int port_id, int copp_idx, int instance_id, + uint32_t module_id, uint32_t param_id, char *params, + uint32_t length) +{ + struct param_hdr_v3 param_hdr; + int port_idx = 0; + int rc = 0; + + pr_info("[CSPL] %s: port_idx: 0x%x, copp_idx: %d, module: 0x%x, len: %d\n", + __func__, port_idx, copp_idx, module_id, length); + + port_id = q6audio_convert_virtual_to_portid(port_id); + port_idx = adm_validate_and_get_port_index(port_id); + + if (port_idx < 0) { + pr_err("[CSPL] %s: Invalid port_id %#x\n", __func__, port_id); + goto fail_cmd; + } + + if (copp_idx < 0 || copp_idx >= MAX_COPPS_PER_PORT) { + pr_err("[CSPL] %s: Invalid copp_num: %d\n", __func__, copp_idx); + goto fail_cmd; + } + + memset(¶m_hdr, 0, sizeof(param_hdr)); + + param_hdr.module_id = module_id; + param_hdr.instance_id = instance_id; + param_hdr.param_id = param_id; + param_hdr.param_size = length; + + atomic_set(&this_adm.copp.stat[port_idx][copp_idx], -1); + + pr_info("[CSPL] %s: port_idx: 0x%x, copp_idx: %d, copp rate: %d, len: %d\n", + __func__, port_idx, copp_idx, + atomic_read(&this_adm.copp.rate[port_idx][copp_idx]), + length); + + rc = adm_pack_and_set_one_pp_param(port_id, copp_idx, param_hdr, + (uint8_t *) params); + if (rc) + pr_err("%s: Failed to set media format configuration data, err %d\n", + __func__, rc); + +fail_cmd: + return 0; +} +EXPORT_SYMBOL(crus_adm_set_params); + +int crus_adm_get_params(int port_id, int copp_idx, int instance_id, + uint32_t module_id, uint32_t param_id, char *params, + uint32_t length, uint32_t client_id) +{ + int ret = 0; + struct param_hdr_v3 param_hdr; + + pr_info("[CSPL] %s: Enter, port_id %x, copp_idx: %d, len: %d\n", + __func__, port_id, copp_idx, length); + + memset(¶m_hdr, 0, sizeof(param_hdr)); + param_hdr.module_id = module_id; + param_hdr.instance_id = instance_id; + param_hdr.param_id = param_id; + param_hdr.param_size = length; + ret = adm_get_pp_params(port_id, copp_idx, + client_id, NULL, ¶m_hdr, + params); + if (ret) { + pr_err("%s: get parameters failed ret:%d\n", __func__, ret); + ret = -EINVAL; + goto done; + } + +done: + pr_debug("%s: Exit, ret = %d\n", __func__, ret); + + return ret; +} +EXPORT_SYMBOL(crus_adm_get_params); +#endif + /* * With pre-packed data, only the opcode differes from V5 and V6. * Use q6common_pack_pp_params to pack the data correctly. @@ -1759,6 +1850,15 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) open->copp_id); pr_debug("%s: coppid rxed=%d\n", __func__, open->copp_id); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (is_usb_timeout && (IDX_AFE_PORT_ID_USB_RX == port_idx)) + close_usb = true; + + if (close_usb && (IDX_AFE_PORT_ID_QUATERNARY_MI2S_RX == port_idx)) + is_usb_timeout = false; +#endif + wake_up(&this_adm.copp.wait[port_idx][copp_idx]); } break; @@ -2852,6 +2952,12 @@ int adm_open(int port_id, int path, int rate, int channel_mode, int topology, port_id = q6audio_convert_virtual_to_portid(port_id); port_idx = adm_validate_and_get_port_index(port_id); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (is_usb_timeout && (AFE_PORT_ID_USB_RX == port_id)) + return -EINVAL; +#endif + if (port_idx < 0) { pr_err("%s: Invalid port_id 0x%x\n", __func__, port_id); return -EINVAL; @@ -2919,7 +3025,12 @@ int adm_open(int port_id, int path, int rate, int channel_mode, int topology, this_adm.ffecns_port_id); } +#ifdef CONFIG_MACH_XIAOMI_SM8150 + if (topology == VPM_TX_VOICE_SMECNS_V2_COPP_TOPOLOGY || + topology == ADM_TOPOLOGY_ID_AUDIO_RX_FVSAM) +#else if (topology == VPM_TX_VOICE_SMECNS_V2_COPP_TOPOLOGY) +#endif channel_mode = 1; /* @@ -3214,6 +3325,12 @@ int adm_open(int port_id, int path, int rate, int channel_mode, int topology, if (!ret) { pr_err("%s: ADM open timedout for port_id: 0x%x for [0x%x]\n", __func__, tmp_port, port_id); + +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (AFE_PORT_ID_USB_RX == port_id) + is_usb_timeout = true; +#endif + return -EINVAL; } else if (atomic_read(&this_adm.copp.stat [port_idx][copp_idx]) > 0) { @@ -3227,6 +3344,9 @@ int adm_open(int port_id, int path, int rate, int channel_mode, int topology, } } atomic_inc(&this_adm.copp.cnt[port_idx][copp_idx]); +#ifdef CONFIG_MSM_CSPL_V2 + crus_qdsp_port_start(port_id, copp_idx); +#endif return copp_idx; } EXPORT_SYMBOL(adm_open); @@ -3573,6 +3693,12 @@ int adm_close(int port_id, int perf_mode, int copp_idx) int ret = 0, port_idx; int copp_id = RESET_COPP_ID; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + int usb_copp_id = RESET_COPP_ID; + int usb_copp_idx = 0; + struct apr_hdr usb_close; +#endif + pr_debug("%s: port_id=0x%x perf_mode: %d copp_idx: %d\n", __func__, port_id, perf_mode, copp_idx); @@ -3639,6 +3765,56 @@ int adm_close(int port_id, int perf_mode, int copp_idx) ADM_MEM_MAP_INDEX_SOURCE_TRACKING], 0); } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (close_usb) { + for (usb_copp_idx = 0; usb_copp_idx < 8; usb_copp_idx++) { + usb_copp_id = adm_get_copp_id(IDX_AFE_PORT_ID_USB_RX, usb_copp_idx); + + if (usb_copp_id == RESET_COPP_ID) + continue; + + usb_close.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), + APR_PKT_VER); + usb_close.pkt_size = sizeof(usb_close); + usb_close.src_svc = APR_SVC_ADM; + usb_close.src_domain = APR_DOMAIN_APPS; + usb_close.src_port = AFE_PORT_ID_USB_RX; + usb_close.dest_svc = APR_SVC_ADM; + usb_close.dest_domain = APR_DOMAIN_ADSP; + usb_close.dest_port = usb_copp_id; + usb_close.token = IDX_AFE_PORT_ID_USB_RX << 16 | usb_copp_idx; + usb_close.opcode = ADM_CMD_DEVICE_CLOSE_V5; + + atomic_set(&this_adm.copp.id[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], + RESET_COPP_ID); + atomic_set(&this_adm.copp.cnt[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], 0); + atomic_set(&this_adm.copp.topology[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], 0); + atomic_set(&this_adm.copp.mode[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], 0); + atomic_set(&this_adm.copp.stat[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], -1); + atomic_set(&this_adm.copp.rate[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], 0); + atomic_set(&this_adm.copp.channels[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], 0); + atomic_set(&this_adm.copp.bit_width[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], 0); + atomic_set(&this_adm.copp.app_type[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx], 0); + + clear_bit(ADM_STATUS_CALIBRATION_REQUIRED, + (void *)&this_adm.copp.adm_status[IDX_AFE_PORT_ID_USB_RX][usb_copp_idx]); + + ret = apr_send_pkt(this_adm.apr, (uint32_t *)&usb_close); + if (ret < 0) + pr_err("%s: ADM close failed %d\n", __func__, ret); + } + + close_usb = false; + + if (AFE_PORT_ID_USB_RX == port_id) { + if (perf_mode != ULTRA_LOW_LATENCY_PCM_MODE) + rtac_remove_adm_device(port_id, copp_id); + return 0; + } + } +#endif + close.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); @@ -3700,6 +3876,10 @@ int adm_close(int port_id, int perf_mode, int copp_idx) if (port_id == this_adm.ffecns_port_id) this_adm.ffecns_port_id = -1; +#ifdef CONFIG_MSM_CSPL_V2 + crus_qdsp_port_close(port_id, copp_idx); +#endif + return 0; } EXPORT_SYMBOL(adm_close); diff --git a/techpack/audio/dsp/q6afe.c b/techpack/audio/dsp/q6afe.c index 48b89b853c13..29dc411afc01 100644 --- a/techpack/audio/dsp/q6afe.c +++ b/techpack/audio/dsp/q6afe.c @@ -19,10 +19,47 @@ #include #include #include +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#include +#endif +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY +#include +#endif +/* for mius end */ #include #include "adsp_err.h" #include "q6afecal-hwdep.h" +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI +#include "../asoc/codecs/tfa98xx/inc/tfa_platform_interface_definition.h" +#endif + +#ifdef CONFIG_MSM_CSPL +#include +#endif + +#ifdef CONFIG_MSM_CSPL_V2 +#include +#endif + +#ifdef CONFIG_TAS25XX_ALGO +#include +#ifdef INSTANCE_ID_0 /*APR Version 3*/ +static int32_t tas_smartamp_algo_callback(uint32_t opcode, uint32_t *payload, + uint32_t payload_size); +#else /*APR Version 2*/ +static int32_t tas_smartamp_algo_callback(uint32_t *payload, + uint32_t payload_size); +#endif /*INSTANCE_ID_0*/ +#endif /*CONFIG_TAS25XX_ALGO*/ + +#ifdef AUDIO_FORCE_RESTART_ADSP +#include +#define ADSP_ERR_LIMITED_COUNT (3) +static int err_count = 0; +#endif + #define WAKELOCK_TIMEOUT 5000 enum { AFE_COMMON_RX_CAL = 0, @@ -146,6 +183,9 @@ struct afe_ctl { int set_custom_topology; int dev_acdb_id[AFE_MAX_PORTS]; routing_cb rt_cb; +#ifdef CONFIG_TAS25XX_ALGO + struct afe_smartamp_calib_get_resp tas_calib_data; +#endif /*CONFIG_TAS25XX_ALGO*/ struct audio_uevent_data *uevent_data; /* cal info for AFE */ struct afe_fw_info *fw_data; @@ -153,6 +193,10 @@ struct afe_ctl { struct vad_config vad_cfg[AFE_MAX_PORTS]; struct work_struct afe_dc_work; struct notifier_block event_notifier; +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + struct rtac_cal_block_data tfa_cal; + atomic_t tfa_state; +#endif /*CONFIG_SND_SOC_TFA9874_FOR_DAVI*/ /* FTM spk params */ uint32_t initial_cal; uint32_t v_vali_flag; @@ -177,6 +221,17 @@ static int afe_get_cal_hw_delay(int32_t path, struct audio_cal_hw_delay_entry *entry); static int remap_cal_data(struct cal_block_data *cal_block, int cal_index); +#ifdef CONFIG_MSM_CSPL +struct afe_cspl_state cspl_afe = { + .apr= &this_afe.apr, + .status= &this_afe.status, + .state= &this_afe.state, + .wait= this_afe.wait, + .timeout_ms= TIMEOUT_MS, +}; +EXPORT_SYMBOL(cspl_afe); +#endif + int afe_get_spk_initial_cal(void) { return this_afe.initial_cal; @@ -282,8 +337,10 @@ static void av_dev_drift_afe_cb_handler(uint32_t opcode, uint32_t *payload, uint32_t payload_size) { u32 param_id; +#if !defined(CONFIG_MACH_XIAOMI_SM8150) || defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) size_t expected_size = sizeof(u32) + sizeof(struct afe_param_id_dev_timing_stats); +#endif /* Get param ID depending on command type */ param_id = (opcode == AFE_PORT_CMDRSP_GET_PARAM_V3) ? payload[3] : @@ -295,12 +352,14 @@ static void av_dev_drift_afe_cb_handler(uint32_t opcode, uint32_t *payload, switch (opcode) { case AFE_PORT_CMDRSP_GET_PARAM_V2: +#if !defined(CONFIG_MACH_XIAOMI_SM8150) || defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) expected_size += sizeof(struct param_hdr_v1); if (payload_size < expected_size) { pr_err("%s: Error: received size %d, expected size %zu\n", __func__, payload_size, expected_size); return; } +#endif /* Repack response to add IID */ this_afe.av_dev_drift_resp.status = payload[0]; this_afe.av_dev_drift_resp.pdata.module_id = payload[1]; @@ -311,12 +370,14 @@ static void av_dev_drift_afe_cb_handler(uint32_t opcode, uint32_t *payload, sizeof(struct afe_param_id_dev_timing_stats)); break; case AFE_PORT_CMDRSP_GET_PARAM_V3: +#if !defined(CONFIG_MACH_XIAOMI_SM8150) || defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) expected_size += sizeof(struct param_hdr_v3); if (payload_size < expected_size) { pr_err("%s: Error: received size %d, expected size %zu\n", __func__, payload_size, expected_size); return; } +#endif memcpy(&this_afe.av_dev_drift_resp, payload, sizeof(this_afe.av_dev_drift_resp)); break; @@ -347,11 +408,13 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, /* Set command specific details */ switch (opcode) { case AFE_PORT_CMDRSP_GET_PARAM_V2: +#if !(defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) if (payload_size < (5 * sizeof(uint32_t))) { pr_err("%s: Error: size %d is less than expected\n", __func__, payload_size); return -EINVAL; } +#endif expected_size += sizeof(struct param_hdr_v1); param_hdr.module_id = payload[1]; param_hdr.instance_id = INSTANCE_ID_0; @@ -360,11 +423,13 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, data_start = &payload[4]; break; case AFE_PORT_CMDRSP_GET_PARAM_V3: +#if !defined(CONFIG_MACH_XIAOMI_SM8150) || (defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU)) if (payload_size < (6 * sizeof(uint32_t))) { pr_err("%s: Error: size %d is less than expected\n", __func__, payload_size); return -EINVAL; } +#endif expected_size += sizeof(struct param_hdr_v3); if (payload_size < expected_size) { pr_err("%s: Error: size %d is less than expected\n", @@ -584,7 +649,23 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) data->opcode == AFE_PORT_CMDRSP_GET_PARAM_V3) { uint32_t *payload = data->payload; uint32_t param_id; +#ifndef CONFIG_MACH_XIAOMI_SM8150 uint32_t param_id_pos = 0; +#endif + +#ifdef CONFIG_MSM_CSPL + if (crus_afe_callback(data->payload, data->payload_size) == 0) { + return 0; + } +#endif + +#ifdef CONFIG_MSM_CSPL_V2 + if (crus_afe_callback(data->opcode, data->payload, data->payload_size) == 0){ + if (afe_token_is_valid(data->token)) + wake_up(&this_afe.wait[data->token]); + return 0; + } +#endif if (!payload || (data->token >= AFE_MAX_PORTS)) { pr_err("%s: Error: size %d payload %pK token %d\n", @@ -597,6 +678,11 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) data->payload_size)) return 0; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + param_id = (data->opcode == AFE_PORT_CMDRSP_GET_PARAM_V3) ? + payload[3] : + payload[2]; +#else if (data->opcode == AFE_PORT_CMDRSP_GET_PARAM_V3) param_id_pos = 4; else @@ -609,19 +695,69 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) __func__, data->payload_size); return -EINVAL; } +#endif if (param_id == AFE_PARAM_ID_DEV_TIMING_STATS) { av_dev_drift_afe_cb_handler(data->opcode, data->payload, data->payload_size); } else { +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + if (atomic_read(&this_afe.tfa_state) == 1 && + data->payload_size == sizeof(uint32_t)) { + + atomic_set(&this_afe.status, payload[0]); + if (payload[0]) + atomic_set(&this_afe.state, -1); + else + atomic_set(&this_afe.state, 0); + + atomic_set(&this_afe.tfa_state, 0); + wake_up(&this_afe.wait[data->token]); + + return 0; + } +#endif /*CONFIG_SND_SOC_TFA9874_FOR_DAVI*/ +#ifdef CONFIG_TAS25XX_ALGO + { + u32 *payload32 = data->payload; + pr_info ("TI-SmartPA: payload1 = 0x%x, 0x%x", payload32[0], payload32[1]); + + if((payload32[1] == AFE_SMARTAMP_MODULE_RX) || + (payload32[1] == AFE_SMARTAMP_MODULE_TX)) + { +#ifdef INSTANCE_ID_0 /*APR Version 3*/ + if (tas_smartamp_algo_callback(data->opcode, data->payload, data->payload_size)) + return -EINVAL; +#else /*APR Version 2*/ + if (tas_smartamp_algo_callback(data->payload, data->payload_size)) + return -EINVAL; +#endif /* INSTANCE_ID_0 */ + } else if (sp_make_afe_callback(data->opcode,data->payload, data->payload_size)) { + return -EINVAL; + } + } +#else if (sp_make_afe_callback(data->opcode, data->payload, data->payload_size)) return -EINVAL; +#endif } if (afe_token_is_valid(data->token)) wake_up(&this_afe.wait[data->token]); else return -EINVAL; +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY + } else if (data->opcode == MI_ULTRASOUND_OPCODE) { + if (NULL != data->payload) + { + printk(KERN_DEBUG "[MIUS] mi ultrasound afe afe cb"); + mius_process_apr_payload(data->payload); + } + else + pr_err("[EXPORT_SYMBOLLUS]: payload ptr is Invalid"); +#endif +/* for mius end */ } else if (data->opcode == AFE_EVENT_MBHC_DETECTION_SW_WA) { msm_aud_evt_notifier_call_chain(SWR_WAKE_IRQ_EVENT, NULL); } else if (data->opcode == @@ -634,17 +770,38 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) atomic_set(&this_afe.state, 0); atomic_set(&this_afe.status, 0); wake_up(&this_afe.lpass_core_hw_wait); +#ifdef CONFIG_MACH_XIAOMI_SM8150 + } else if (data->opcode == ULTRASOUND_OPCODE) { + if (NULL != data->payload) + elliptic_process_apr_payload(data->payload); + else + pr_err("[EXPORT_SYMBOLLUS]: payload ptr is Invalid"); +#endif + /* for mius start */ +#ifdef CONFIG_US_PROXIMITY + } else if (data->opcode == MI_ULTRASOUND_OPCODE) { + if (NULL != data->payload) + { + printk(KERN_DEBUG "[MIUS] mi ultrasound afe afe cb"); + mius_process_apr_payload(data->payload); + } + else + pr_err("[EXPORT_SYMBOLLUS]: payload ptr is Invalid"); +#endif + /* for mius end */ } else if (data->payload_size) { uint32_t *payload; uint16_t port_id = 0; payload = data->payload; if (data->opcode == APR_BASIC_RSP_RESULT) { +#ifndef CONFIG_MACH_XIAOMI_SM8150 if (data->payload_size < (2 * sizeof(uint32_t))) { pr_err("%s: Error: size %d is less than expected\n", __func__, data->payload_size); return -EINVAL; } +#endif pr_debug("%s:opcode = 0x%x cmd = 0x%x status = 0x%x token=%d\n", __func__, data->opcode, payload[0], payload[1], data->token); @@ -1020,11 +1177,26 @@ static int afe_apr_send_pkt(void *data, wait_queue_head_t *wait) &this_afe.status))); ret = adsp_err_get_lnx_err_code( atomic_read(&this_afe.status)); +#ifdef AUDIO_FORCE_RESTART_ADSP + if (atomic_read(&this_afe.status) == ADSP_ENEEDMORE) + err_count++; + else + err_count = 0; + + if (err_count >= ADSP_ERR_LIMITED_COUNT) { + err_count = 0; + pr_err("%s: DSP returned error more than limited, restart now !\n", __func__); + subsystem_restart("adsp"); + } +#endif } else { ret = 0; } } else { ret = 0; +#ifdef AUDIO_FORCE_RESTART_ADSP + err_count = 0; +#endif } } else if (ret == 0) { pr_err("%s: packet not transmitted\n", __func__); @@ -1037,6 +1209,21 @@ static int afe_apr_send_pkt(void *data, wait_queue_head_t *wait) return ret; } +#ifdef CONFIG_MSM_CSPL +int afe_apr_send_pkt_crus(void *data, int index, int set) +{ + pr_info("[CSPL] %s: index = %d, set=%d, data = %p\n", + __func__, index, set, data); + + if (set) + return afe_apr_send_pkt(data, &this_afe.wait[index]); + else /* get */ + return afe_apr_send_pkt(data, 0); +} + +EXPORT_SYMBOL(afe_apr_send_pkt_crus); +#endif + /* This function shouldn't be called directly. Instead call q6afe_set_params. */ static int q6afe_set_params_v2(u16 port_id, int index, struct mem_mapping_hdr *mem_hdr, @@ -1697,6 +1884,15 @@ static int afe_spk_prot_prepare(int src_port, int dst_port, int param_id, case AFE_PARAM_ID_SP_V2_EX_VI_FTM_CFG: param_info.module_id = AFE_MODULE_SPEAKER_PROTECTION_V2_EX_VI; break; +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + case AFE_PARAM_ID_TFADSP_RX_CFG: + case AFE_PARAM_ID_TFADSP_RX_SET_BYPASS: + param_info.module_id = AFE_MODULE_ID_TFADSP_RX; + break; + case AFE_PARAM_ID_TFADSP_TX_SET_ENABLE: + param_info.module_id = AFE_MODULE_ID_TFADSP_TX; + break; +#endif /*CONFIG_SND_SOC_TFA9874_FOR_DAVI*/ default: pr_err("%s: default case 0x%x\n", __func__, param_id); goto fail_cmd; @@ -1765,6 +1961,30 @@ static int afe_spkr_prot_reg_event_cfg(u16 port_id) return ret; } +#ifdef CONFIG_MACH_XIAOMI_SM8150 +afe_ultrasound_state_t elus_afe = { + .ptr_apr= &this_afe.apr, + .ptr_status= &this_afe.status, + .ptr_state= &this_afe.state, + .ptr_wait= this_afe.wait, + .timeout_ms= TIMEOUT_MS, +}; +EXPORT_SYMBOL(elus_afe); +#endif + +/* for mius start */ +#ifdef CONFIG_US_PROXIMITY +afe_mi_ultrasound_state_t mius_afe = { + .ptr_apr= &this_afe.apr, + .ptr_status= &this_afe.status, + .ptr_state= &this_afe.state, + .ptr_wait= this_afe.wait, + .timeout_ms= TIMEOUT_MS, +}; +EXPORT_SYMBOL(mius_afe); +#endif +/* for mius end */ + static void afe_send_cal_spkr_prot_tx(int port_id) { union afe_spkr_prot_config afe_spk_config; @@ -1960,6 +2180,110 @@ static void afe_send_cal_spkr_prot_rx(int port_id) return; } +#ifdef CONFIG_MSM_CSPL_V2 +static int crus_cb_buffer[CRUS_BUF_SIZE]; +int crus_afe_callback(uint32_t opcode, void* payload, int size) +{ + uint32_t* payload32 = payload; + + pr_debug("%s: module=0x%x size = %d\n", __func__, + (int)payload32[1], size); + + if (payload32[1]!= CIRRUS_SP) + return -EINVAL; + + if (size > CRUS_BUF_SIZE*sizeof(int)) { + pr_err("%s: module=0x%x, size(%d) > buf(%d), error!\n", + __func__,(int)payload32[1], size, + CRUS_BUF_SIZE*sizeof(int)); + return -EINVAL; + } + + memset(crus_cb_buffer, 0, CRUS_BUF_SIZE*sizeof(int)); + if(opcode==AFE_PORT_CMDRSP_GET_PARAM_V2) { + memcpy(crus_cb_buffer, &payload32[4], size); + } else if(opcode==AFE_PORT_CMDRSP_GET_PARAM_V3) { + memcpy(crus_cb_buffer, &payload32[5], size); + } else { + pr_info("%s:opcode %d no surport!\n",__func__, opcode); + memcpy(crus_cb_buffer, &payload32[5], size); + } + + atomic_set(&this_afe.state, 0); + + return 0; +} + +int crus_afe_get_params(u16 port_id, uint32_t module, uint32_t param_id, + void* data, int size) { + struct param_hdr_v3 param_hdr; + int ret = -EINVAL; + + //mutex_lock(&this_afe.afe_cmd_lock); + pr_info("%s: enter ++, size=%d; module = 0x%08x, port = 0x%04x, param = 0x%08x\n", + __func__, size, module, port_id, param_id); + + memset(¶m_hdr, 0, sizeof(param_hdr)); + + param_hdr.module_id = module; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = size; + + ret = q6afe_get_params(port_id, NULL, ¶m_hdr); + if (ret) { + pr_err("%s: Failed to get CSPL data\n", __func__); + goto done; + } + + memcpy((u8 *)data, crus_cb_buffer, size); + ret = 0; +done: + //mutex_unlock(&this_afe.afe_cmd_lock); + pr_info("%s: exit --\n", __func__); + return ret; +} +EXPORT_SYMBOL(crus_afe_get_params); +int crus_afe_set_params(u16 port_id, uint32_t module_id, uint32_t param_id, + void* data, int size) +{ + int ret = 0; + struct param_hdr_v3 param_hdr; + + + //mutex_lock(&this_afe.afe_cmd_lock); + pr_info("%s: enter ++; module = 0x%08x, port = 0x%04x, param = 0x%08x\n", + __func__, module_id, port_id, param_id); + + memset(¶m_hdr, 0, sizeof(param_hdr)); + + /* Set stream index */ + param_hdr.module_id = module_id; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = size; + + ret = q6afe_pack_and_set_param_in_band(port_id, + q6audio_get_port_index(port_id), + param_hdr, (u8 *) data); + if (ret) { + pr_err("%s: Failed to set cmd duration param, err %d\n", + __func__, ret); + goto fail_cmd; + } + + //mutex_unlock(&this_afe.afe_cmd_lock); + ret = 0; +fail_cmd: + pr_debug("%s: param_id = 0x%x ret = %d\n", __func__, + param_id, ret); + pr_info("%s: exit --\n", __func__); + return ret; + +} +EXPORT_SYMBOL(crus_afe_set_params); +#endif + static int afe_send_hw_delay(u16 port_id, u32 rate) { struct audio_cal_hw_delay_entry delay_entry; @@ -4408,6 +4732,14 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, } ret = afe_send_cmd_port_start(port_id); +#ifdef CONFIG_MSM_CSPL + if (ret == 0) + crus_afe_port_start(port_id); +#elif defined(CONFIG_MSM_CSPL_V2) + if (ret == 0) + crus_qdsp_port_start(port_id, -1); +#endif + fail_cmd: mutex_unlock(&this_afe.afe_cmd_lock); return ret; @@ -5129,6 +5461,386 @@ int afe_loopback_gain(u16 port_id, u16 volume) } EXPORT_SYMBOL(afe_loopback_gain); +#ifdef CONFIG_TAS25XX_ALGO +/*For DC Detection*/ +void (*tas256x_sw_reset)(void *data); +dc_detection_data_t *s_dc_detect = NULL; +void register_tas256x_reset_func(void *fptr, dc_detection_data_t* data) +{ + pr_err("[TI-SmartPA:%s] ", __func__); + tas256x_sw_reset = fptr; + s_dc_detect = data; +} + +EXPORT_SYMBOL(register_tas256x_reset_func); +#ifdef INSTANCE_ID_0 /* APR Version 3 */ +static int32_t tas_smartamp_algo_callback(uint32_t opcode, uint32_t *payload, + uint32_t payload_size) +{ + struct param_hdr_v3 param_hdr; + u32 *data_dest = NULL; + u32 *data_start = NULL; + + pr_debug("[TI-SmartPA:%s] ", __func__); + memset(¶m_hdr, 0, sizeof(param_hdr)); + switch (opcode) { + case AFE_PORT_CMDRSP_GET_PARAM_V2: + param_hdr.module_id = payload[1]; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = payload[2]; + param_hdr.param_size = payload[3]; + data_start = &payload[4]; + break; + case AFE_PORT_CMDRSP_GET_PARAM_V3: + memcpy(¶m_hdr, &payload[1], sizeof(struct param_hdr_v3)); + data_start = &payload[5]; + break; + default: + pr_err("[TI-SmartPA:%s] Unrecognized command %d\n", __func__, opcode); + return -EINVAL; + } + data_dest = (u32 *) &this_afe.tas_calib_data; + data_dest[0] = payload[0]; + memcpy(&data_dest[1], ¶m_hdr, sizeof(struct param_hdr_v3)); + memcpy(&data_dest[5], data_start, param_hdr.param_size); + if (param_hdr.param_id == CAPI_V2_TAS_SA_DC_DETECT) { + pr_err("[TI-SmartPA:%s] Detected DC, Calling TAS256X Software Reset \n", __func__); + s_dc_detect->channel = this_afe.tas_calib_data.res_cfg.payload[0]; + tas256x_sw_reset(s_dc_detect); + } + if (!data_dest[0]) { + atomic_set(&this_afe.state, 0); + } else { + pr_debug("[TI-SmartPA:%s] status: %d", __func__, data_dest[0]); + atomic_set(&this_afe.state, -1); + } + return 0; +} + +int afe_tas_smartamp_get_calib_data(uint32_t module_id, uint32_t param_id, + int32_t length, uint8_t *data) +{ + int ret = -EINVAL; + struct param_hdr_v3 param_hdr; + uint32_t port = 0x0; + + if (!data || length <= 0) { + pr_err("[TI-SmartPA:%s] Invalid params, length: %d\n", + __func__, length); + goto fail_cmd; + } + + pr_info("[TI-SmartPA:%s] module id : 0x%x ", __func__, module_id); + if (module_id == AFE_SMARTAMP_MODULE_RX) { + port = TAS_RX_PORT; + } else if (module_id == AFE_SMARTAMP_MODULE_TX) { + port = TAS_TX_PORT; + } else { + pr_err("[TI-SmartPA:%s] Invalid module id 0x%x\n", __func__, module_id); + goto fail_cmd; + } + + memset(¶m_hdr, 0, sizeof(param_hdr)); + param_hdr.module_id = module_id; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = sizeof(struct afe_smartamp_get_calib); + ret = q6afe_get_params(port, NULL, ¶m_hdr); + if (ret < 0) { + pr_err("[TI-SmartPA:%s] get param port 0x%x param id[0x%x]failed %d\n", + __func__, port, param_hdr.param_id, ret); + goto fail_cmd; + } + + memcpy(data, &this_afe.tas_calib_data.res_cfg, length); + + ret = 0; +fail_cmd: + return ret; +} +EXPORT_SYMBOL(afe_tas_smartamp_get_calib_data); + +int afe_tas_smartamp_set_calib_data(uint32_t module_id, uint32_t param_id, + int32_t length, uint8_t* data) +{ + int ret = -EINVAL; + uint32_t port = 0x0; + struct param_hdr_v3 param_hdr; + + u8 *packed_param_data = NULL; + u32 packed_param_size = 0; + u32 single_param_size = 0; + pr_info("[TI-SmartPA:%s] length: %d\n", __func__, length); + if (!data || (length < 0)) { + pr_err("[TI-SmartPA:%s] Invalid params\n", __func__); + return ret; + } + + pr_info("[TI-SmartPA:%s] module id : 0x%x \n", __func__, module_id); + if (module_id == AFE_SMARTAMP_MODULE_RX) { + port = TAS_RX_PORT; + } else if (module_id == AFE_SMARTAMP_MODULE_TX) { + port = TAS_TX_PORT; + } else { + pr_err("[TI-SmartPA:%s] Invalid module id 0x%x\n", __func__, module_id); + return ret; + } + packed_param_size = sizeof(param_hdr) + length; + packed_param_data = kzalloc(packed_param_size, GFP_KERNEL); + if (!packed_param_data) + return -ENOMEM; + packed_param_size = 0; + param_hdr.module_id = module_id; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = param_id; + param_hdr.param_size = length; + ret = q6common_pack_pp_params(packed_param_data, ¶m_hdr, + (u8 *) data, &single_param_size); + if (ret) { + pr_err("[TI-SmartPA:%s] Failed to pack param data, error %d\n", __func__, + ret); + goto done; + } + packed_param_size += single_param_size; + ret = q6afe_set_params(port, q6audio_get_port_index(port), + NULL, packed_param_data, packed_param_size); +done: + kfree(packed_param_data); + return ret; +} +EXPORT_SYMBOL(afe_tas_smartamp_set_calib_data); + +#else /* APR Version 2 */ +static int32_t tas_smartamp_algo_callback(uint32_t *payload, uint32_t payload_size) +{ + struct afe_smartamp_calib_get_resp *resp = + (struct afe_smartamp_calib_get_resp *) payload; + + pr_debug("[TI-SmartPA:%s] callback\n", __func__); + + if (!(&(resp->pdata))) { + pr_err("[TI-SmartPA:%s] Error: resp pdata is NULL", __func__); + return -EINVAL; + } + + memcpy(&this_afe.tas_calib_data, payload, + sizeof(this_afe.tas_calib_data)); + + pr_debug("[TI-SmartPA:%s] callback, 0x%x\n", __func__, resp->pdata.param_id); + + if(resp->pdata.param_id == CAPI_V2_TAS_SA_DC_DETECT) { + s_dc_detect->channel = resp->res_cfg.payload[0]; + pr_err("[TI-SmartPA:%s] Detected DC, Calling TAS256X Software Reset Channel-%s\n", __func__, + (s_dc_detect->channel == 0)?"Left":"Right"); + tas256x_sw_reset(s_dc_detect); + } + if (!this_afe.tas_calib_data.status) { + atomic_set(&this_afe.state, 0); + } else { + pr_debug("[TI-SmartPA:%s] calib resp status: %d", __func__, + this_afe.tas_calib_data.status); + atomic_set(&this_afe.state, -1); + } + + return 0; +} + +/* +* data is writable memroy +* length is the max size of the data +* retuns number of bytes returned by the algorithm +* -ve error number in case of failure. +*/ +int afe_tas_smartamp_get_calib_data(uint32_t module_id, uint32_t param_id, + int32_t length, uint8_t *data) +{ + int ret = -EINVAL; + int index = 0, port_id = TAS_RX_PORT; + struct afe_smartamp_get_calib calib_resp_o; + struct afe_smartamp_get_calib* calib_resp = &calib_resp_o; + + if (!data || (length <= 0)) { + pr_err("[TI-SmartPA: %s] Invalid params\n", __func__); + goto fail_cmd; + } + if ((q6audio_validate_port(port_id) < 0)) { + pr_err("%s invalid port %d\n", __func__, port_id); + goto fail_cmd; + } + + index = q6audio_get_port_index(port_id); + + memset (calib_resp, 0, sizeof(*calib_resp)); + + //header + calib_resp->hdr.hdr_field = + APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + calib_resp->hdr.src_svc = APR_SVC_AFE; + calib_resp->hdr.src_domain = APR_DOMAIN_APPS; + calib_resp->hdr.dest_svc = APR_SVC_AFE; + calib_resp->hdr.dest_domain = APR_DOMAIN_ADSP; + calib_resp->hdr.pkt_size = sizeof(*calib_resp); + calib_resp->hdr.src_port = 0; + calib_resp->hdr.dest_port = 0; + calib_resp->hdr.token = index; + calib_resp->hdr.opcode = AFE_PORT_CMD_GET_PARAM_V2; + + //parameter + calib_resp->get_param.mem_map_handle = 0; + calib_resp->get_param.module_id = module_id; + calib_resp->get_param.param_id = param_id; + calib_resp->get_param.payload_address_lsw = 0; + calib_resp->get_param.payload_address_msw = 0; + calib_resp->get_param.payload_size = sizeof(*calib_resp) + - sizeof(calib_resp->hdr) + - sizeof(calib_resp->get_param); + calib_resp->get_param.port_id = q6audio_get_port_id(port_id); + + //data + calib_resp->pdata.module_id = module_id; + calib_resp->pdata.param_id = param_id; + calib_resp->pdata.param_size = sizeof(calib_resp->res_cfg); + calib_resp->pdata.reserved = 0; + atomic_set(&this_afe.state, 1); + + ret = apr_send_pkt(this_afe.apr, (uint32_t *)calib_resp); + + if (ret < 0) { + pr_err("[TI-SmartPA %s]: get param port %d param id[0x%x]failed", + __func__, port_id, calib_resp->get_param.param_id); + goto fail_cmd; + } + + ret = wait_event_timeout(this_afe.wait[index], + (atomic_read(&this_afe.state) == 0), + msecs_to_jiffies(TIMEOUT_MS * 5)); + if (!ret) { + pr_err("[TI-SmartPA %s]: wait_event timeout", __func__); + ret = -EINVAL; + goto fail_cmd; + } + if (atomic_read(&this_afe.status) != 0) { + pr_err("[TI-SmartPA %s]: config cmd failed", __func__); + ret = -EINVAL; + goto fail_cmd; + } + + if (length <= sizeof (this_afe.tas_calib_data.res_cfg)) { + memcpy(data, &this_afe.tas_calib_data.res_cfg, length); + ret = 0; + } else { + ret = -EINVAL; + memcpy(data, &this_afe.tas_calib_data.res_cfg, length); + } + pr_info("[TI-SmartPA: %s] ret=%d", __func__, ret); + +fail_cmd: + return ret; +} +EXPORT_SYMBOL(afe_tas_smartamp_get_calib_data); + +/* +* length -> length in bytes of 'data' +*/ +int afe_tas_smartamp_set_calib_data(uint32_t module_id, uint32_t param_id, + int32_t length, uint8_t* data) +{ + int ret = -EINVAL; + int index = 0 , port_id = 0; + struct afe_smartamp_config_command configV; + struct afe_smartamp_config_command *config; + + + config = &configV; + memset(config, 0 , sizeof(struct afe_smartamp_config_command)); + if (!data) { + pr_err("[TI-SmartPA:%s] Invalid params\n", __func__); + goto fail_cmd; + } + + if (module_id == AFE_SMARTAMP_MODULE_RX){ + port_id = TAS_RX_PORT; + } else if(module_id == AFE_SMARTAMP_MODULE_TX) { + port_id = TAS_TX_PORT; + } else { + pr_err("[TI-SmartPA: %s] unknown module id %d", __func__, module_id); + } + + if ((q6audio_validate_port(port_id) < 0)) { + pr_err("[TI-SmartPA: %s] invalid port %d", __func__, port_id); + goto fail_cmd; + } + + + index = q6audio_get_port_index(port_id); + + //header + config->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + config->hdr.pkt_size = sizeof(struct afe_smartamp_config_command) + - sizeof(struct afe_smartamp_get_set_params_t) + + length; + config->hdr.src_port = 0; + config->hdr.dest_port = 0; + config->hdr.token = index; + config->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; + + //param + config->param.port_id = q6audio_get_port_id(port_id); + config->param.payload_size = sizeof(struct afe_smartamp_config_command) + - sizeof(struct apr_hdr) + - sizeof(struct afe_port_cmd_set_param_v2) + - sizeof(struct afe_smartamp_get_set_params_t) + + length; + + //data + config->pdata.module_id = module_id; + config->pdata.param_id = param_id; + config->pdata.param_size = length; //should be same as + /* + sizeof(struct afe_smartamp_config_command) + - sizeof(struct apr_hdr) + - sizeof(struct afe_port_cmd_set_param_v2) + - sizeof(struct afe_port_param_data_v2); + */ + + memcpy(config->prot_config.payload, data, length); + atomic_set(&this_afe.state, 1); + ret = apr_send_pkt(this_afe.apr, (uint32_t *) config); + + + if (ret < 0) { + pr_err("[TI-SmartPA %s]: Setting param for port %d param[0x%x]failed\n", + __func__, port_id, param_id); + goto fail_cmd; + } + + ret = wait_event_timeout(this_afe.wait[index], + (atomic_read(&this_afe.state) == 0), + msecs_to_jiffies(TIMEOUT_MS*10)); + if (!ret) { + pr_err("[TI-SmartPA %s]: wait_event timeout\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + if (atomic_read(&this_afe.status) != 0) { + pr_err("[TI-SmartPA %s]: config cmd failed\n", __func__); + ret = -EINVAL; + goto fail_cmd; + } + ret = 0; + +fail_cmd: + pr_info("[TI-SmartPA %s]: config->pdata.param_id %x status %d\n", + __func__, config->pdata.param_id, ret); + return ret; + +} +EXPORT_SYMBOL(afe_tas_smartamp_set_calib_data); +#endif /* INSTANCE_ID_0 */ +#endif /*CONFIG_TAS25XX_ALGO*/ + int afe_pseudo_port_start_nowait(u16 port_id) { struct afe_pseudoport_start_command start; @@ -7118,6 +7830,12 @@ int afe_close(int port_id) if (ret) pr_err("%s: AFE close failed %d\n", __func__, ret); +#ifdef CONFIG_MSM_CSPL + crus_afe_port_close(port_id); +#elif defined(CONFIG_MSM_CSPL_V2) + crus_qdsp_port_close(port_id, -1); +#endif + fail_cmd: mutex_unlock(&this_afe.afe_cmd_lock); return ret; @@ -8555,6 +9273,209 @@ static void afe_release_uevent_data(struct kobject *kobj) kfree(data); } +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI +int send_tfa_cal_apr(void *buf, int cmd_size, bool bRead) +{ + int32_t result, port_id = AFE_PORT_ID_TFADSP_RX; + uint32_t port_index = 0, payload_size = 0; + size_t len; + struct rtac_cal_block_data *tfa_cal = &(this_afe.tfa_cal); + struct mem_mapping_hdr mem_hdr; + struct param_hdr_v3 param_hdr; + + pr_debug("%s\n", __func__); + + memset(&mem_hdr, 0x00, sizeof(mem_hdr)); + memset(¶m_hdr, 0x00, sizeof(param_hdr)); + + if (0 == tfa_cal->map_data.dma_buf ) { + /*Minimal chunk size is 4K*/ + tfa_cal->map_data.map_size = SZ_4K; + result = msm_audio_ion_alloc(&(tfa_cal->map_data.dma_buf), + tfa_cal->map_data.map_size, + &(tfa_cal->cal_data.paddr), + &len, + &(tfa_cal->cal_data.kvaddr)); + if (result < 0) { + pr_err("%s: allocate buffer failed! ret = %d\n", + __func__, result); + goto err; + } + pr_debug("%s: paddr 0x%pK, kvaddr 0x%pK, map_size 0x%x\n", + __func__, + &tfa_cal->cal_data.paddr, + tfa_cal->cal_data.kvaddr, + tfa_cal->map_data.map_size); + } + + if (0 == tfa_cal->map_data.map_handle ) { + result = afe_map_rtac_block(tfa_cal); + if (result < 0) { + pr_err("%s: map buffer failed! ret = %d\n", + __func__, result); + goto err; + } + } + + port_index = q6audio_get_port_index(port_id); + if (port_index >= AFE_MAX_PORTS) { + pr_err("%s: Invalid AFE port = 0x%x\n", __func__, port_id); + goto err; + } + + if (cmd_size > (SZ_4K - sizeof(struct param_hdr_v3))) { + pr_err("%s: Invalid payload size = %d\n", __func__, cmd_size); + result = -EINVAL; + goto err; + } + + /* Pack message header with data */ + param_hdr.module_id = AFE_MODULE_ID_TFADSP_RX; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_size = cmd_size; + + if (!bRead) { + param_hdr.param_id = AFE_PARAM_ID_TFADSP_RX_CFG; + + q6common_pack_pp_params(tfa_cal->cal_data.kvaddr, + ¶m_hdr, + buf, + &payload_size); + tfa_cal->cal_data.size = payload_size; + } + else { + param_hdr.param_id = AFE_PARAM_ID_TFADSP_RX_GET_RESULT; + tfa_cal->cal_data.size = cmd_size + sizeof(struct param_hdr_v3) ; + } + + /*Send/Get package to/from ADSP*/ + mem_hdr.data_payload_addr_lsw = + lower_32_bits(tfa_cal->cal_data.paddr); + mem_hdr.data_payload_addr_msw = + msm_audio_populate_upper_32_bits(tfa_cal->cal_data.paddr); + mem_hdr.mem_map_handle = + tfa_cal->map_data.map_handle; + + pr_debug("%s: Sending tfa_cal port = 0x%x, cal size = %zd, cal addr = 0x%pK\n", + __func__, port_id, tfa_cal->cal_data.size, &tfa_cal->cal_data.paddr); + + result = afe_q6_interface_prepare(); + if (result != 0) { + pr_err("%s: Q6 interface prepare failed %d\n", __func__, result); + goto err; + } + + if (!bRead) { + if (q6common_is_instance_id_supported()) + result = q6afe_set_params_v3(port_id, port_index, &mem_hdr, NULL, payload_size); + else + result = q6afe_set_params_v2(port_id, port_index, &mem_hdr, NULL, payload_size); + } else { + int8_t *resp = (int8_t *)tfa_cal->cal_data.kvaddr; + + atomic_set(&this_afe.tfa_state, 1); + if (q6common_is_instance_id_supported()){ + result = q6afe_get_params_v3(port_id, port_index, &mem_hdr, ¶m_hdr); + resp += sizeof(struct param_hdr_v3); + } + else { + result = q6afe_get_params_v2(port_id, port_index, &mem_hdr, ¶m_hdr); + resp += sizeof(struct param_hdr_v1); + } + + if (result) { + pr_err("%s: get response from port 0x%x failed %d\n", __func__, port_id, result); + goto err; + } + else { + /*Copy response data to command buffer*/ + memcpy(buf, resp, cmd_size); + } + } + +err: + return result; +} +EXPORT_SYMBOL(send_tfa_cal_apr); + +void send_tfa_cal_unmap_memory(void) +{ + int result = 0; + + if (this_afe.tfa_cal.map_data.map_handle) { + result = afe_unmap_rtac_block(&this_afe.tfa_cal.map_data.map_handle); + + /*Force to remap after unmap failed*/ + if (result) + this_afe.tfa_cal.map_data.map_handle = 0; + } +} +EXPORT_SYMBOL(send_tfa_cal_unmap_memory); + +int send_tfa_cal_in_band(void *buf, int cmd_size) +{ + union afe_spkr_prot_config afe_spk_config; + int32_t port_id = AFE_PORT_ID_TFADSP_RX; + + if (cmd_size > sizeof(afe_spk_config)) + return -EINVAL; + + memcpy(&afe_spk_config, buf, cmd_size); + + if (afe_spk_prot_prepare(port_id, 0, + AFE_PARAM_ID_TFADSP_RX_CFG, + &afe_spk_config)) { + pr_err("%s: AFE_PARAM_ID_TFADSP_RX_CFG failed\n", + __func__); + } + + return 0; +} +EXPORT_SYMBOL(send_tfa_cal_in_band); + +int send_tfa_cal_set_bypass(void *buf, int cmd_size) +{ + union afe_spkr_prot_config afe_spk_config; + int32_t port_id = AFE_PORT_ID_TFADSP_RX; + + if (cmd_size > sizeof(afe_spk_config)) + return -EINVAL; + + memcpy(&afe_spk_config, buf, cmd_size); + + if (afe_spk_prot_prepare(port_id, 0, + AFE_PARAM_ID_TFADSP_RX_SET_BYPASS, + &afe_spk_config)) { + pr_err("%s: AFE_PARAM_ID_TFADSP_RX_SET_BYPASS failed\n", + __func__); + } + + return 0; +} +EXPORT_SYMBOL(send_tfa_cal_set_bypass); + +int send_tfa_cal_set_tx_enable(void *buf, int cmd_size) +{ + union afe_spkr_prot_config afe_spk_config; + int32_t port_id = AFE_PORT_ID_TFADSP_TX; + + if (cmd_size > sizeof(afe_spk_config)) + return -EINVAL; + + memcpy(&afe_spk_config, buf, cmd_size); + + if (afe_spk_prot_prepare(port_id, 0, + AFE_PARAM_ID_TFADSP_TX_SET_ENABLE, + &afe_spk_config)) { + pr_err("%s: AFE_PARAM_ID_TFADSP_TX_SET_ENABLE failed\n", + __func__); + } + + return 0; +} +EXPORT_SYMBOL(send_tfa_cal_set_tx_enable); +#endif /*CONFIG_SND_SOC_TFA9874_FOR_DAVI*/ + int __init afe_init(void) { int i = 0, ret; @@ -8613,6 +9534,10 @@ int __init afe_init(void) void afe_exit(void) { +#ifdef CONFIG_SND_SOC_TFA9874_FOR_DAVI + afe_unmap_rtac_block(&this_afe.tfa_cal.map_data.map_handle); +#endif /*CONFIG_SND_SOC_TFA9874_FOR_DAVI*/ + if (this_afe.apr) { apr_reset(this_afe.apr); atomic_set(&this_afe.state, 0); diff --git a/techpack/audio/dsp/q6asm.c b/techpack/audio/dsp/q6asm.c index 6040e1ceade7..6ade0fdb7423 100644 --- a/techpack/audio/dsp/q6asm.c +++ b/techpack/audio/dsp/q6asm.c @@ -10839,6 +10839,14 @@ static int q6asm_get_asm_topology_apptype(struct q6asm_cal_info *cal_info) cal_info->app_type = ((struct audio_cal_info_asm_top *) cal_block->cal_info)->app_type; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + if (0 == cal_info->topology_id) { + cal_info->topology_id = 0x10c68;; + pr_err("%s: Correct using topology %d app_type %d\n", __func__, + cal_info->topology_id, cal_info->app_type); + } +#endif + cal_utils_mark_cal_used(cal_block); unlock: diff --git a/techpack/audio/dsp/q6audio-v2.c b/techpack/audio/dsp/q6audio-v2.c index 773cef67bb1f..d6081bc78584 100644 --- a/techpack/audio/dsp/q6audio-v2.c +++ b/techpack/audio/dsp/q6audio-v2.c @@ -352,6 +352,10 @@ int q6audio_get_port_index(u16 port_id) return IDX_AFE_PORT_ID_RX_CODEC_DMA_RX_6; case AFE_PORT_ID_RX_CODEC_DMA_RX_7: return IDX_AFE_PORT_ID_RX_CODEC_DMA_RX_7; +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case AFE_PORT_ID_PSEUDOPORT_01: + return IDX_AFE_PORT_ID_PSEUDOPORT_01; +#endif case RT_PROXY_PORT_002_RX: return IDX_RT_PROXY_PORT_002_RX; case RT_PROXY_PORT_002_TX: @@ -1091,6 +1095,9 @@ int q6audio_validate_port(u16 port_id) case AFE_PORT_ID_TX_CODEC_DMA_TX_5: case AFE_PORT_ID_RX_CODEC_DMA_RX_6: case AFE_PORT_ID_RX_CODEC_DMA_RX_7: +#ifdef CONFIG_MACH_XIAOMI_SM8150 + case AFE_PORT_ID_PSEUDOPORT_01: +#endif case RT_PROXY_PORT_002_RX: case RT_PROXY_PORT_002_TX: { diff --git a/techpack/audio/dsp/q6voice.c b/techpack/audio/dsp/q6voice.c index d9b444715f9e..b8b1cd3a707d 100644 --- a/techpack/audio/dsp/q6voice.c +++ b/techpack/audio/dsp/q6voice.c @@ -24,7 +24,11 @@ #include "adsp_err.h" #include +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) +#define TIMEOUT_MS 1000 +#else #define TIMEOUT_MS 300 +#endif #define CMD_STATUS_SUCCESS 0 diff --git a/techpack/audio/include/dsp/apr_audio-v2.h b/techpack/audio/include/dsp/apr_audio-v2.h index 6a4a5bc95ed6..2b0626cdc7c0 100644 --- a/techpack/audio/include/dsp/apr_audio-v2.h +++ b/techpack/audio/include/dsp/apr_audio-v2.h @@ -5085,6 +5085,9 @@ struct afe_param_id_lpass_core_shared_clk_cfg { #define ADM_CMD_COPP_OPEN_TOPOLOGY_ID_DTS_HPX 0x10015002 #define ADM_CMD_COPP_OPEN_TOPOLOGY_ID_AUDIOSPHERE 0x10028000 #define VPM_TX_DM_FLUENCE_EF_COPP_TOPOLOGY 0x10000005 +#ifdef CONFIG_MACH_XIAOMI_SM8150 +#define ADM_TOPOLOGY_ID_AUDIO_RX_FVSAM 0x1000FFF0 +#endif /* Memory map regions command payload used by the * #ASM_CMD_SHARED_MEM_MAP_REGIONS ,#ADM_CMD_SHARED_MEM_MAP_REGIONS @@ -11381,7 +11384,7 @@ struct afe_clk_set { * for enable and disable clock. * "clk_freq_in_hz", "clk_attri", and "clk_root" * are ignored in disable clock case. - * @values  + * @values� * - 0 -- Disabled * - 1 -- Enabled @tablebulletend */ diff --git a/techpack/audio/include/dsp/q6afe-v2.h b/techpack/audio/include/dsp/q6afe-v2.h index 9ffbd110f4fb..1eda0371c795 100644 --- a/techpack/audio/include/dsp/q6afe-v2.h +++ b/techpack/audio/include/dsp/q6afe-v2.h @@ -265,6 +265,9 @@ enum { /* IDX 187 -> 188 */ IDX_AFE_PORT_ID_SENARY_PCM_RX, IDX_AFE_PORT_ID_SENARY_PCM_TX, +#ifdef CONFIG_MACH_XIAOMI_SM8150 + IDX_AFE_PORT_ID_PSEUDOPORT_01, +#endif /* IDX 189 -> 190 */ IDX_RT_PROXY_PORT_002_RX, IDX_RT_PROXY_PORT_002_TX, @@ -459,6 +462,13 @@ int afe_get_sp_rx_tmax_xmax_logging_data( u16 port_id); int afe_cal_init_hwdep(void *card); int afe_send_port_island_mode(u16 port_id); + +#ifdef CONFIG_MSM_CSPL +int afe_apr_send_pkt_crus(void *data, int index, int set); +int crus_afe_port_close(u16 port_id); +int crus_afe_port_start(u16 port_id); +#endif + int afe_send_cmd_wakeup_register(void *handle, bool enable); void afe_register_wakeup_irq_callback( void (*afe_cb_wakeup_irq)(void *handle)); diff --git a/techpack/audio/soc/pinctrl-lpi.c b/techpack/audio/soc/pinctrl-lpi.c index 5b0539944af3..900e0aa30b1a 100644 --- a/techpack/audio/soc/pinctrl-lpi.c +++ b/techpack/audio/soc/pinctrl-lpi.c @@ -487,6 +487,11 @@ static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) unsigned int i; for (i = 0; i < chip->ngpio; i++, gpio++) { +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* skip lpi gpio 0~7 and 12 ~ 17 */ + if (i < 8 || (i > 11 && i < 18)) + continue; +#endif lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio); seq_puts(s, "\n"); } diff --git a/techpack/audio/soc/swr-mstr-ctrl.c b/techpack/audio/soc/swr-mstr-ctrl.c index 838fd7d94592..945f7cd87f5b 100644 --- a/techpack/audio/soc/swr-mstr-ctrl.c +++ b/techpack/audio/soc/swr-mstr-ctrl.c @@ -1918,6 +1918,18 @@ static int swrm_probe(struct platform_device *pdev) goto err_pdata_fail; } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* Make inband tx interrupts as wakeup capable for slave irq */ + swrm->swr_tx_wakeup_capable = false; + if (of_property_read_bool(swrm->dev->of_node, + "qcom,swr-mstr-tx-wakeup-capable")) { + swrm->swr_tx_wakeup_capable = true; + irq_set_irq_wake(swrm->irq, 1); + } else + dev_dbg(swrm->dev, "%s: swrm tx wakeup capable not defined", + __func__); +#endif + for (i = 0; i < map_length; i++) { port_num = temp[3 * i]; port_type = temp[3 * i + 1]; @@ -2059,6 +2071,12 @@ static int swrm_probe(struct platform_device *pdev) &swrm_debug_ops); } +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + /* Make inband tx interrupts as wakeup capable for slave irq */ + if (swrm->master_id == MASTER_ID_TX) + irq_set_irq_wake(swrm->irq, 1); +#endif + ret = device_init_wakeup(swrm->dev, true); if (ret) { dev_err(swrm->dev, "Device wakeup init failed: %d\n", ret); diff --git a/techpack/audio/soc/swr-mstr-ctrl.h b/techpack/audio/soc/swr-mstr-ctrl.h index 76bdb3eb90f3..ff1481067c2d 100644 --- a/techpack/audio/soc/swr-mstr-ctrl.h +++ b/techpack/audio/soc/swr-mstr-ctrl.h @@ -173,6 +173,9 @@ struct swr_mstr_ctrl { int wlock_holders; u32 intr_mask; u32 swr_irq_wakeup_capable; +#if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) + bool swr_tx_wakeup_capable; +#endif }; #endif /* _SWR_WCD_CTRL_H */ From 66cfba5521c5a6f6edffb63db75b082114f59e35 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sat, 18 Nov 2023 14:54:27 +0100 Subject: [PATCH 106/226] arch: arm64: configs: xiaomi: Enable device-specific drivers Change-Id: I4dd54e21df54f5a104e8d86c0b0aab3baf0f382c Signed-off-by: firebird11 --- .../configs/vendor/xiaomi/andromeda.config | 13 ++++ .../configs/vendor/xiaomi/cepheus.config | 16 ++++ arch/arm64/configs/vendor/xiaomi/crux.config | 19 +++++ arch/arm64/configs/vendor/xiaomi/nabu.config | 15 ++++ .../configs/vendor/xiaomi/raphael.config | 7 ++ .../vendor/xiaomi/sm8150-common.config | 77 +++++++++++++++++++ arch/arm64/configs/vendor/xiaomi/vayu.config | 13 ++++ 7 files changed, 160 insertions(+) diff --git a/arch/arm64/configs/vendor/xiaomi/andromeda.config b/arch/arm64/configs/vendor/xiaomi/andromeda.config index 6981d04735d1..501339f6ed33 100644 --- a/arch/arm64/configs/vendor/xiaomi/andromeda.config +++ b/arch/arm64/configs/vendor/xiaomi/andromeda.config @@ -1,2 +1,15 @@ # Platform CONFIG_MACH_XIAOMI_ANDROMEDA=y + +# Audio +CONFIG_SND_SOC_CS35L41=y +CONFIG_MSM_CSPL=y + +# Camera +CONFIG_USE_ROHM_BU64753=y + +# Touchscreen +CONFIG_TOUCHSCREEN_ST_FTS_V521=y +CONFIG_FTS_FOD_AREA_REPORT=y +CONFIG_SECURE_TOUCH=y +CONFIG_I2C_BY_DMA=y diff --git a/arch/arm64/configs/vendor/xiaomi/cepheus.config b/arch/arm64/configs/vendor/xiaomi/cepheus.config index b237760c457f..600752df98aa 100644 --- a/arch/arm64/configs/vendor/xiaomi/cepheus.config +++ b/arch/arm64/configs/vendor/xiaomi/cepheus.config @@ -1,2 +1,18 @@ # Platform CONFIG_MACH_XIAOMI_CEPHEUS=y + +# Audio +CONFIG_SND_SOC_CS35L41=y +CONFIG_MSM_CSPL=y + +# Camera +CONFIG_VCM_AK7374=y + +# Power +CONFIG_IDT_P9220=y + +# Touchscreen +CONFIG_TOUCHSCREEN_ST_FTS_V521=y +CONFIG_FTS_FOD_AREA_REPORT=y +CONFIG_SECURE_TOUCH=y +CONFIG_I2C_BY_DMA=y diff --git a/arch/arm64/configs/vendor/xiaomi/crux.config b/arch/arm64/configs/vendor/xiaomi/crux.config index 0611ff82cdd4..9b0be13a4bcf 100644 --- a/arch/arm64/configs/vendor/xiaomi/crux.config +++ b/arch/arm64/configs/vendor/xiaomi/crux.config @@ -1,2 +1,21 @@ # Platform CONFIG_MACH_XIAOMI_CRUX=y + +# Audio +CONFIG_SND_SOC_CS35L41=y +CONFIG_MSM_CSPL=y + +# Camera +CONFIG_USE_ROHM_BU64753=y +CONFIG_VCM_AK7374=y + +# Power +CONFIG_RX1619=y +CONFIG_RX1619_TRIM=y +CONFIG_LN8282=y +CONFIG_IDT_P9220=y +CONFIG_HALO_7221=y + +# Touchscreen +CONFIG_TOUCHSCREEN_ST_FTS_V521=y +CONFIG_FTS_FOD_AREA_REPORT=y diff --git a/arch/arm64/configs/vendor/xiaomi/nabu.config b/arch/arm64/configs/vendor/xiaomi/nabu.config index 39bd6a435189..cea9413451d6 100644 --- a/arch/arm64/configs/vendor/xiaomi/nabu.config +++ b/arch/arm64/configs/vendor/xiaomi/nabu.config @@ -1,2 +1,17 @@ # Platform CONFIG_MACH_XIAOMI_NABU=y + +# Audio +CONFIG_SND_SOC_CS35L41_V2=y +CONFIG_MSM_CSPL_V2=y + +# Power +CONFIG_BATT_VERIFY_BY_DS28E16_NABU=y +CONFIG_ONEWIRE_GPIO_NABU=y +CONFIG_IDT_P9418=y +CONFIG_BQ2597X_CHARGE_PUMP=y +CONFIG_CHARGER_LN8000=y + +# Touchscreen +CONFIG_TOUCHSCREEN_NT36523_HOSTDL_SPI=y +CONFIG_TOUCHSCREEN_NVT_DEBUG_FS=y diff --git a/arch/arm64/configs/vendor/xiaomi/raphael.config b/arch/arm64/configs/vendor/xiaomi/raphael.config index 89de85dcf84d..a8db1f76d035 100644 --- a/arch/arm64/configs/vendor/xiaomi/raphael.config +++ b/arch/arm64/configs/vendor/xiaomi/raphael.config @@ -1,2 +1,9 @@ # Platform CONFIG_MACH_XIAOMI_RAPHAEL=y + +# Audio +CONFIG_SND_SOC_CS35L41=y +CONFIG_MSM_CSPL=y + +# Touchscreen +CONFIG_TOUCHSCREEN_GOODIX_GTX8=y diff --git a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config index 78436de13ed3..610d5f699132 100644 --- a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config +++ b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config @@ -9,3 +9,80 @@ CONFIG_EXFAT_FS=y # EROFS CONFIG_EROFS_FS=y + +# pstore +CONFIG_CMDLINE="ramoops_memreserve=4M" +CONFIG_CMDLINE_EXTEND=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_SQ=y +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_OOPS=y +CONFIG_MTD_BLOCK2MTD=y + +# Audio +CONFIG_SND_SOC_TAS256X=y +CONFIG_TAS256X_CODEC=y +CONFIG_TAS256X_REGMAP=y +CONFIG_TAS25XX_ALGO=y +CONFIG_SND_SOC_TAS2557=y +CONFIG_TAS2557_REGMAP=y +CONFIG_TAS2557_CODEC=y +CONFIG_TAS2557_MISC=y +CONFIG_SND_SOC_TFA9874=y + +# Backlight +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTZ8866=y + +# Camera motor +CONFIG_TI_DRV8846=y + +# Fingerprint +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_FPC_TEE=y +CONFIG_FINGERPRINT_GOODIX_TA=y + +# Haptics +CONFIG_INPUT_AW8697_XM_HAPTIC=y + +# IR +CONFIG_IR_SPI=y +CONFIG_LIRC=y +CONFIG_RC_CORE=y +CONFIG_RC_DECODERS=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_RC_DEVICES=y + +# Keyboard +CONFIG_XIAOMI_KEYBOARD=y + +# Power +# CONFIG_SMB1355_SLAVE_CHARGER is not set +# CONFIG_SMB1390_CHARGE_PUMP_PSY is not set +CONFIG_SMB1390_CHARGE_PUMP=y +CONFIG_FRAME_WARN=4096 + +# Proximity +CONFIG_US_PROXIMITY=y + +# Sensors +CONFIG_AKM09970=y + +# Simtray +CONFIG_SIMTRAY_STATUS=y + +# spk-id +CONFIG_HAS_IOMEM=y +CONFIG_MFD_SPK_ID=y + +# TEE +CONFIG_TRUSTY=y + +# Touchscreen +# CONFIG_TOUCHSCREEN_ST is not set diff --git a/arch/arm64/configs/vendor/xiaomi/vayu.config b/arch/arm64/configs/vendor/xiaomi/vayu.config index 96c16e9b2cf6..a3342fc69b97 100644 --- a/arch/arm64/configs/vendor/xiaomi/vayu.config +++ b/arch/arm64/configs/vendor/xiaomi/vayu.config @@ -1,2 +1,15 @@ # Platform CONFIG_MACH_XIAOMI_VAYU=y + +# Audio +CONFIG_SND_SOC_CS35L41=y +CONFIG_MSM_CSPL=y + +# Power +CONFIG_BATT_VERIFY_BY_DS28E16=y +CONFIG_ONEWIRE_GPIO=y +CONFIG_BQ2597X_CHARGE_PUMP=y + +# Touchscreen +CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI=y +CONFIG_TOUCHSCREEN_NVT_DEBUG_FS=y From 7b576f9ed86d01e61f7adbb4957b93b3a514ae62 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Mon, 4 Jul 2022 17:18:25 +0200 Subject: [PATCH 107/226] arch: arm64: boot: dts: xiaomi: Move to 2si Change-Id: Iaca6c96f165cf300289761abf4e178eb64371ffd Signed-off-by: firebird11 --- arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi index bf0f93ebbec2..2bdfd8672fff 100644 --- a/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/xiaomi/base/sm8150.dtsi @@ -4,6 +4,12 @@ }; }; +&firmware { + android { + boot_devices = "soc/1d84000.ufshc"; + }; +}; + &shared_meta { parts = "vbmeta,boot,system,vendor,dtbo"; }; @@ -13,7 +19,7 @@ status = "disabled"; }; vendor { - fsmgr_flags = "wait,avb"; + status = "disabled"; }; }; From f25b72774abac691d78f403740d94e12bdcc200e Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 28 Jun 2022 23:10:29 +0200 Subject: [PATCH 108/226] init: Add CONFIG_INITRAMFS_IGNORE_SKIP_FLAG * Ignoring an ignore flag, yikes * Also replace skip_initramfs with want_initramfs Co-authored-by: Erfan Abdi Change-Id: Ifdf726f128bc66bf860bbb71024f94f56879710f Signed-off-by: firebird11 --- fs/proc/cmdline.c | 31 +++++++++++++++++++++++++++++++ init/initramfs.c | 2 +- usr/Kconfig | 11 +++++++++++ 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/fs/proc/cmdline.c b/fs/proc/cmdline.c index 403cbb12a6e9..01e1f0eebf66 100644 --- a/fs/proc/cmdline.c +++ b/fs/proc/cmdline.c @@ -3,10 +3,37 @@ #include #include #include +#ifdef CONFIG_INITRAMFS_IGNORE_SKIP_FLAG +#include +#endif + +#ifdef CONFIG_INITRAMFS_IGNORE_SKIP_FLAG +#define INITRAMFS_STR_FIND "skip_initramfs" +#define INITRAMFS_STR_REPLACE "want_initramfs" +#define INITRAMFS_STR_LEN (sizeof(INITRAMFS_STR_FIND) - 1) + +static char proc_command_line[COMMAND_LINE_SIZE]; + +static void proc_command_line_init(void) { + char *offset_addr; + + strcpy(proc_command_line, saved_command_line); + + offset_addr = strstr(proc_command_line, INITRAMFS_STR_FIND); + if (!offset_addr) + return; + + memcpy(offset_addr, INITRAMFS_STR_REPLACE, INITRAMFS_STR_LEN); +} +#endif static int cmdline_proc_show(struct seq_file *m, void *v) { +#ifdef CONFIG_INITRAMFS_IGNORE_SKIP_FLAG + seq_printf(m, "%s\n", proc_command_line); +#else seq_printf(m, "%s\n", saved_command_line); +#endif return 0; } @@ -24,6 +51,10 @@ static const struct file_operations cmdline_proc_fops = { static int __init proc_cmdline_init(void) { +#ifdef CONFIG_INITRAMFS_IGNORE_SKIP_FLAG + proc_command_line_init(); +#endif + proc_create("cmdline", 0, NULL, &cmdline_proc_fops); return 0; } diff --git a/init/initramfs.c b/init/initramfs.c index 33fdbdc19ad7..431ea8fa60cf 100644 --- a/init/initramfs.c +++ b/init/initramfs.c @@ -614,7 +614,7 @@ static int __init skip_initramfs_param(char *str) { if (*str) return 0; - do_skip_initramfs = 1; + do_skip_initramfs = !IS_ENABLED(CONFIG_INITRAMFS_IGNORE_SKIP_FLAG); return 1; } __setup("skip_initramfs", skip_initramfs_param); diff --git a/usr/Kconfig b/usr/Kconfig index 8b4826de1189..de9d04f2c0be 100644 --- a/usr/Kconfig +++ b/usr/Kconfig @@ -32,6 +32,17 @@ config INITRAMFS_FORCE and is useful if you cannot or don't want to change the image your bootloader passes to the kernel. +config INITRAMFS_IGNORE_SKIP_FLAG + bool "Force initramfs even when skip_initramfs is set" + default n + help + Ignore skip_initramfs cmdline flag. + + This should only be used if you have no control over cmdline + passed by your bootloader yet you can't use CMDLINE_FORCE. + + If unsure say N. + config INITRAMFS_ROOT_UID int "User ID to map to 0 (user root)" depends on INITRAMFS_SOURCE!="" From 804f527ef1a8e2cc58dec11ec04a38c423a0e984 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Tue, 28 Jun 2022 23:14:51 +0200 Subject: [PATCH 109/226] arch: arm64: configs: xiaomi: Enable CONFIG_INITRAMFS_IGNORE_SKIP_FLAG Change-Id: I22b5eb981c886d9280957f6bd1047fc76ac9916b Signed-off-by: firebird11 --- arch/arm64/configs/vendor/xiaomi/sm8150-common.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config index 610d5f699132..942ae66bdf56 100644 --- a/arch/arm64/configs/vendor/xiaomi/sm8150-common.config +++ b/arch/arm64/configs/vendor/xiaomi/sm8150-common.config @@ -10,6 +10,9 @@ CONFIG_EXFAT_FS=y # EROFS CONFIG_EROFS_FS=y +# initramfs +CONFIG_INITRAMFS_IGNORE_SKIP_FLAG=y + # pstore CONFIG_CMDLINE="ramoops_memreserve=4M" CONFIG_CMDLINE_EXTEND=y From fb6f8155fcf4cd0fbbe8b9bc1f3a92f97e1a2a02 Mon Sep 17 00:00:00 2001 From: map220v Date: Wed, 31 May 2023 18:37:30 +0300 Subject: [PATCH 110/226] drivers: gpu: dsi-staging: Disable dynamic fps and set refresh rate to 104 * Fixes issue with drm render in recovery and charger [SebaUbuntu]: Don't export the symbols, guard for nabu only Co-authored-by: Cyber Knight Change-Id: Ibff4d92d054c302b75e6a2bf7ddaf0e88f1fa43f Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 34 +++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 450f1ac0a369..ab7aa8c80dea 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -49,6 +49,26 @@ #define DEFAULT_PANEL_PREFILL_LINES 25 #define TICKS_IN_MICRO_SECOND 1000000 +#ifdef CONFIG_MACH_XIAOMI_NABU +static bool is_normal_boot = false; +static int __init read_is_normal_boot(char *s) +{ + strtobool(s, &is_normal_boot); + return 1; +} +__setup("androidboot.force_normal_boot=", read_is_normal_boot); + +static bool is_charger_boot = false; +static int __init read_boot_mode(char *s) +{ + if (strcmp(s, "charger") == 0) { + is_charger_boot = true; + } + return 1; +} +__setup("androidboot.mode=", read_boot_mode); +#endif + enum dsi_dsc_ratio_type { DSC_8BPC_8BPP, DSC_10BPC_8BPP, @@ -1347,6 +1367,13 @@ static int dsi_panel_parse_timing(struct dsi_mode_info *mode, rc = utils->read_u32(utils->data, "qcom,mdss-dsi-panel-framerate", &mode->refresh_rate); + +#ifdef CONFIG_MACH_XIAOMI_NABU + if (!is_normal_boot || is_charger_boot) { + mode->refresh_rate = 104; + } +#endif + if (rc) { pr_err("failed to read qcom,mdss-dsi-panel-framerate, rc=%d\n", rc); @@ -1899,6 +1926,13 @@ static int dsi_panel_parse_dfps_caps(struct dsi_panel *panel) const char *type; u32 i; +#ifdef CONFIG_MACH_XIAOMI_NABU + if (!is_normal_boot || is_charger_boot) { + dfps_caps->dfps_support = false; + return rc; + } +#endif + supported = utils->read_bool(utils->data, "qcom,mdss-dsi-pan-enable-dynamic-fps"); From 1b1591a5b14b4c1c7cc1e50647533ffd32fdad74 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sat, 3 Aug 2024 02:10:13 +0200 Subject: [PATCH 111/226] drivers: hid: Implement keyboard driver Will remove the keyboard from the input when disconnected Change-Id: Ide873402a0ebc1b4844f6c4e6666c03fff3f5ba4 Signed-off-by: firebird11 --- drivers/hid/Makefile | 2 + drivers/hid/hid-core.c | 3 + drivers/hid/hid-ids.h | 2 + drivers/hid/hid-xiaomi.c | 215 ++++++++++++++++++ .../misc/xiaomi_keyboard/xiaomi_keyboard.c | 95 +++++++- .../misc/xiaomi_keyboard/xiaomi_keyboard.h | 2 + include/linux/input/usbkbd-xiaomi.h | 15 ++ 7 files changed, 330 insertions(+), 4 deletions(-) create mode 100644 drivers/hid/hid-xiaomi.c create mode 100644 include/linux/input/usbkbd-xiaomi.h diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile index 94b39817f5c6..351176547d08 100644 --- a/drivers/hid/Makefile +++ b/drivers/hid/Makefile @@ -118,6 +118,8 @@ obj-$(CONFIG_HID_WIIMOTE) += hid-wiimote.o obj-$(CONFIG_HID_SENSOR_HUB) += hid-sensor-hub.o obj-$(CONFIG_HID_SENSOR_CUSTOM_SENSOR) += hid-sensor-custom.o +obj-$(CONFIG_XIAOMI_KEYBOARD) += hid-xiaomi.o + obj-$(CONFIG_USB_HID) += usbhid/ obj-$(CONFIG_USB_MOUSE) += usbhid/ obj-$(CONFIG_USB_KBD) += usbhid/ diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index 0e5db253db44..fc107ba4e2fa 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -2510,6 +2510,9 @@ static const struct hid_device_id hid_have_special_driver[] = { #endif #if IS_ENABLED(CONFIG_HID_ZYDACRON) { HID_USB_DEVICE(USB_VENDOR_ID_ZYDACRON, USB_DEVICE_ID_ZYDACRON_REMOTE_CONTROL) }, +#endif +#if IS_ENABLED(CONFIG_XIAOMI_KEYBOARD) + { HID_USB_DEVICE(USB_VENDOR_ID_NANO_IC, 0x3FFC) }, #endif { } }; diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index cbd40d59bb20..f6bf0b497a6a 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -1160,6 +1160,8 @@ #define USB_VENDOR_ID_XAT 0x2505 #define USB_DEVICE_ID_XAT_CSR 0x0220 +#define USB_VENDOR_ID_NANO_IC 0x3206 + #define USB_VENDOR_ID_XIN_MO 0x16c0 #define USB_DEVICE_ID_XIN_MO_DUAL_ARCADE 0x05e1 #define USB_DEVICE_ID_THT_2P_ARCADE 0x75e1 diff --git a/drivers/hid/hid-xiaomi.c b/drivers/hid/hid-xiaomi.c new file mode 100644 index 000000000000..c6a8d256bcf2 --- /dev/null +++ b/drivers/hid/hid-xiaomi.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * HID driver for the Xiaomi Mi Pad 5 keyboard. + * + * Copyright (c) 2024 Sebastiano Barezzi + */ + +/** + * This driver is needed to support the Xiaomi Mi Pad 5 keyboard due to their engineering mess. + * The keyboard controller is in the tablet, and the keyboard connects through pogo pins. + * The controllers appears as a USB HID device, but without being aware of its presence. + * The driver, thanks to the original Xiaomi driver needed for power juice, will add and remove the + * Linux input device when the keyboard is connected and disconnected. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "hid-ids.h" + +/** + * Wait interval for the connection check to let the IRQ handler to settle down. + */ +#define CONNECTION_WAIT_INTERVAL 1000 /* msec */ + +struct xiaomi_priv { + struct list_head list; + + struct hid_device *hdev; + + bool enabled; + struct mutex enabled_lock; + + struct workqueue_struct *connection_wq; + struct delayed_work connection_work; +}; + +// List of all instances +static struct list_head instances = LIST_HEAD_INIT(instances); +static DEFINE_MUTEX(instances_lock); + +// Keyboard connection status, true by default +static bool connected = true; + +// Called by vendor driver +void xiaomi_keyboard_connection_change(bool _connected) +{ + struct xiaomi_priv *instance; + + connected = _connected; + + mutex_lock(&instances_lock); + list_for_each_entry(instance, &instances, list) { + // Schedule the work, wait a sec before toggling the keyboard + mod_delayed_work(instance->connection_wq, + &instance->connection_work, + msecs_to_jiffies(CONNECTION_WAIT_INTERVAL)); + } + mutex_unlock(&instances_lock); +} + +/** + * Updates the HID device status in a safe way. + * Needed to avoid a double-free in the HID core. + */ +static int xiaomi_safe_toggle(struct hid_device *hdev, bool enable) +{ + struct xiaomi_priv *priv = hid_get_drvdata(hdev); + int ret = 0; + + mutex_lock(&priv->enabled_lock); + + if (priv->enabled == enable) { + goto done; + } + + if (enable) { + ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT); + if (ret) { + hid_err(hdev, "hid_hw_start failed\n"); + goto done; + } + } else { + hid_hw_stop(hdev); + } + + priv->enabled = enable; + +done: + mutex_unlock(&priv->enabled_lock); + + return ret; +} + +static void xiaomi_connection_work(struct work_struct *work) +{ + struct xiaomi_priv *priv = container_of( + to_delayed_work(work), struct xiaomi_priv, connection_work); + struct hid_device *hdev = priv->hdev; + + xiaomi_safe_toggle(hdev, connected); +} + +static int xiaomi_probe(struct hid_device *hdev, const struct hid_device_id *id) +{ + struct xiaomi_priv *priv; + int ret; + + if (!hid_is_usb(hdev)) { + ret = -EINVAL; + goto err_1; + } + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto err_1; + } + + // Setup workqueue + priv->connection_wq = create_singlethread_workqueue("hid-xiaomi"); + if (!priv->connection_wq) { + ret = -ENOMEM; + goto err_2; + } + INIT_DELAYED_WORK(&priv->connection_work, xiaomi_connection_work); + + priv->hdev = hdev; + priv->enabled = false; + + // Setup the mutex + mutex_init(&priv->enabled_lock); + + hid_set_drvdata(hdev, priv); + + ret = hid_parse(hdev); + if (ret) { + hid_err(hdev, "hid_parse failed\n"); + goto err_3; + } + + ret = xiaomi_safe_toggle(hdev, true); + if (ret) { + hid_err(hdev, "hid_hw_start failed\n"); + goto err_3; + } + + // Schedule an update to keep the keyboard in sync + mod_delayed_work(priv->connection_wq, &priv->connection_work, + msecs_to_jiffies(CONNECTION_WAIT_INTERVAL)); + + // Add the instance to the list + mutex_lock(&instances_lock); + list_add(&priv->list, &instances); + mutex_unlock(&instances_lock); + + return 0; + +err_3: + mutex_destroy(&priv->enabled_lock); + destroy_workqueue(priv->connection_wq); +err_2: + kfree(priv); +err_1: + return ret; +} + +static void xiaomi_remove(struct hid_device *hdev) +{ + struct xiaomi_priv *priv = hid_get_drvdata(hdev); + + // Remove the instance from the list + mutex_lock(&instances_lock); + list_del(&priv->list); + mutex_unlock(&instances_lock); + + // Wait for the work to finish + cancel_delayed_work_sync(&priv->connection_work); + + // Stop the HID device + xiaomi_safe_toggle(hdev, false); + + // Destroy the mutex + mutex_destroy(&priv->enabled_lock); + + // Destroy the workqueue + destroy_workqueue(priv->connection_wq); + + kfree(priv); +} + +static const struct hid_device_id xiaomi_devices[] = { + { + HID_USB_DEVICE(USB_VENDOR_ID_NANO_IC, 0x3FFC), + }, + {} +}; +MODULE_DEVICE_TABLE(hid, xiaomi_devices); + +static struct hid_driver hid_xiaomi = { + .name = "hid-xiaomi", + .id_table = xiaomi_devices, + .probe = xiaomi_probe, + .remove = xiaomi_remove, +}; +module_hid_driver(hid_xiaomi); + +MODULE_AUTHOR("Sebastiano Barezzi "); +MODULE_DESCRIPTION("Xiaomi Mi Pad 5 keyboard HID driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c index 98d41b8eaeb2..8e91dc92f73b 100644 --- a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c +++ b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c @@ -15,6 +15,7 @@ #include "xiaomi_keyboard.h" #include #include +#include static struct xiaomi_keyboard_data *mdata; @@ -92,6 +93,91 @@ DEVICE_ATTR(xiaomi_keyboard_conn_status, (S_IRUGO | S_IWUSR | S_IWGRP), xiaomi_keyboard_conn_status_show, xiaomi_keyboard_conn_status_store); +static ssize_t xiaomi_keyboard_connected_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + if (!mdata) + return -EINVAL; + + return scnprintf(buf, PAGE_SIZE, "%d", mdata->connected); +} + +static ssize_t xiaomi_keyboard_connected_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + if (!mdata) + return -EINVAL; + + mdata->connected = !!val; + + sysfs_notify(&mdata->pdev->dev.kobj, NULL, "xiaomi_keyboard_connected"); + + // Notify the input driver + xiaomi_keyboard_connection_change( + !!(mdata->connected && mdata->user_enabled)); + + return count; +} + +DEVICE_ATTR(xiaomi_keyboard_connected, (S_IRUGO | S_IWUSR | S_IWGRP), + xiaomi_keyboard_connected_show, xiaomi_keyboard_connected_store); + +static ssize_t xiaomi_keyboard_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + if (!mdata) + return -EINVAL; + + return scnprintf(buf, PAGE_SIZE, "%d", mdata->user_enabled); +} + +static ssize_t xiaomi_keyboard_enabled_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + if (!mdata) + return -EINVAL; + + mdata->user_enabled = !!val; + + sysfs_notify(&mdata->pdev->dev.kobj, NULL, "xiaomi_keyboard_enabled"); + + // Notify the input driver + xiaomi_keyboard_connection_change( + !!(mdata->connected && mdata->user_enabled)); + + return count; +} + +DEVICE_ATTR(xiaomi_keyboard_enabled, (S_IRUGO | S_IWUSR | S_IWGRP), + xiaomi_keyboard_enabled_show, xiaomi_keyboard_enabled_store); + +static struct attribute *sysfs_attrs[] = { + &dev_attr_xiaomi_keyboard_conn_status.attr, + &dev_attr_xiaomi_keyboard_connected.attr, + &dev_attr_xiaomi_keyboard_enabled.attr, + NULL, +}; + +static const struct attribute_group xiaomi_attribute_group = { + .attrs = sysfs_attrs, +}; + static irqreturn_t xiaomi_keyboard_irq_func(int irq, void *data) { int value = 0; @@ -533,12 +619,13 @@ static int xiaomi_keyboard_probe(struct platform_device *pdev) mdata->dev_pm_suspend = false; mdata->keyboard_is_enable = false; mdata->is_in_suspend = false; + mdata->connected = true; + mdata->user_enabled = true; - ret = sysfs_create_file(&mdata->pdev->dev.kobj, - &dev_attr_xiaomi_keyboard_conn_status.attr); + ret = sysfs_create_group(&mdata->pdev->dev.kobj, + &xiaomi_attribute_group); if (ret < 0) { - MI_KB_ERR( - "Create sysfs attribute xiaomi_keyboard_conn_status Failed\n"); + MI_KB_ERR("Create sysfs group Failed\n"); goto err_pinctrl_select; } diff --git a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h index 32bb8c0dcbd4..914b094b866d 100644 --- a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h +++ b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.h @@ -43,5 +43,7 @@ struct xiaomi_keyboard_data { int is_usb_exist; bool keyboard_is_enable; bool is_in_suspend; + bool connected; + bool user_enabled; }; #endif diff --git a/include/linux/input/usbkbd-xiaomi.h b/include/linux/input/usbkbd-xiaomi.h new file mode 100644 index 000000000000..7af82a271785 --- /dev/null +++ b/include/linux/input/usbkbd-xiaomi.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Sebastiano Barezzi + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#include + +#ifdef CONFIG_XIAOMI_KEYBOARD +void xiaomi_keyboard_connection_change(bool connected); +#else +static inline void xiaomi_keyboard_connection_change(bool connected) { } +#endif From a8328d5458710ba08a1d21e0de13ec124ca0aefe Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sat, 3 Aug 2024 04:56:03 +0200 Subject: [PATCH 112/226] drivers: hid: hid-xiaomi: Drop touchpad reporting The keyboard doesn't have one Change-Id: Ieab11b2019e14bf22d2b76990e4fbd0dabc86e9a Signed-off-by: firebird11 --- drivers/hid/hid-xiaomi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/hid/hid-xiaomi.c b/drivers/hid/hid-xiaomi.c index c6a8d256bcf2..88e67e9958e8 100644 --- a/drivers/hid/hid-xiaomi.c +++ b/drivers/hid/hid-xiaomi.c @@ -106,6 +106,17 @@ static void xiaomi_connection_work(struct work_struct *work) xiaomi_safe_toggle(hdev, connected); } +static int xiaomi_input_configured(struct hid_device *hdev, + struct hid_input *hi) +{ + struct input_dev *input = hi->input; + + // Drop EV_REL, the keyboard doesn't have a touchpad + __clear_bit(EV_REL, input->evbit); + + return 0; +} + static int xiaomi_probe(struct hid_device *hdev, const struct hid_device_id *id) { struct xiaomi_priv *priv; @@ -207,6 +218,7 @@ static struct hid_driver hid_xiaomi = { .id_table = xiaomi_devices, .probe = xiaomi_probe, .remove = xiaomi_remove, + .input_configured = xiaomi_input_configured, }; module_hid_driver(hid_xiaomi); From 051b2f6ade84fca6db31375e2c4cd6eb8e45b3b7 Mon Sep 17 00:00:00 2001 From: Sebastiano Barezzi Date: Sat, 3 Aug 2024 02:12:26 +0200 Subject: [PATCH 113/226] drivers: input: misc: xiaomi_keyboard: Enable by default Change-Id: I1425db25797ab1379a914572f4234f13a58c9b62 Signed-off-by: firebird11 --- drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c index 8e91dc92f73b..7883bf111c45 100644 --- a/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c +++ b/drivers/input/misc/xiaomi_keyboard/xiaomi_keyboard.c @@ -656,6 +656,10 @@ static int xiaomi_keyboard_probe(struct platform_device *pdev) goto err_register_power_supply_notif_failed; } + // Enable the keyboard by default + set_keyboard_status(1); + xiaomi_keyboard_reset(); + MI_KB_INFO("Success\n"); return ret; From a744fd8c6d6b4a9ede95498408535b59a708c461 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 31 Oct 2022 12:23:22 +0200 Subject: [PATCH 114/226] display: translate PCC to CSC PCC cannot be applied per-plane, but CSC can. Translate PCC to CSC to allow skipping it for some planes. Change-Id: I76fa04fed6bcc9426cf2a38c58c23e49e27b8750 [@RealJohnGalt] adapt for k4.14 Signed-off-by: onettboots Signed-off-by: firebird11 --- .../gpu/drm/msm/sde/sde_color_processing.c | 25 +++ .../gpu/drm/msm/sde/sde_color_processing.h | 3 + drivers/gpu/drm/msm/sde/sde_hw_sspp.c | 34 ++-- drivers/gpu/drm/msm/sde/sde_hw_sspp.h | 3 +- drivers/gpu/drm/msm/sde/sde_plane.c | 192 +++++++++++++++++- 5 files changed, 229 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c index 7782dffc7e33..29435986477d 100644 --- a/drivers/gpu/drm/msm/sde/sde_color_processing.c +++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c @@ -24,6 +24,7 @@ #include "sde_ad4.h" #include "sde_hw_interrupts.h" #include "sde_core_irq.h" +#include "sde_plane.h" #include "dsi_panel.h" struct sde_cp_node { @@ -646,6 +647,9 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, hw_cfg.num_of_mixers = sde_crtc->num_mixers; hw_cfg.last_feature = 0; + if (prop_node->feature == SDE_CP_CRTC_DSPP_PCC) + return; + for (i = 0; i < num_mixers && !ret; i++) { hw_lm = sde_crtc->mixers[i].hw_lm; hw_dspp = sde_crtc->mixers[i].hw_dspp; @@ -2109,3 +2113,24 @@ int sde_cp_hist_interrupt(struct drm_crtc *crtc_drm, bool en, exit: return ret; } + +const struct drm_msm_pcc *sde_cp_crtc_get_pcc_cfg(struct drm_crtc *drm_crtc) +{ + struct drm_property_blob *blob = NULL; + struct sde_cp_node *prop_node = NULL; + struct sde_crtc *crtc; + + crtc = to_sde_crtc(drm_crtc); + + mutex_lock(&crtc->crtc_cp_lock); + list_for_each_entry(prop_node, &crtc->feature_list, feature_list) { + if (prop_node->feature == SDE_CP_CRTC_DSPP_PCC) { + blob = prop_node->blob_ptr; + break; + } + } + + mutex_unlock(&crtc->crtc_cp_lock); + + return blob ? blob->data : NULL; +} diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.h b/drivers/gpu/drm/msm/sde/sde_color_processing.h index 7481a594f4fc..900afc687d2a 100644 --- a/drivers/gpu/drm/msm/sde/sde_color_processing.h +++ b/drivers/gpu/drm/msm/sde/sde_color_processing.h @@ -152,4 +152,7 @@ void sde_cp_crtc_post_ipc(struct drm_crtc *crtc); */ int sde_cp_hist_interrupt(struct drm_crtc *crtc_drm, bool en, struct sde_irq_callback *hist_irq); + +const struct drm_msm_pcc *sde_cp_crtc_get_pcc_cfg(struct drm_crtc *crtc); + #endif /*_SDE_COLOR_PROCESSING_H */ diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c index 35b1e099fcbe..25feafec3d20 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c +++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c @@ -231,7 +231,7 @@ static void sde_hw_sspp_setup_multirect(struct sde_hw_pipe *ctx, } static void _sspp_setup_opmode(struct sde_hw_pipe *ctx, - u32 mask, u8 en) + bool csc_en, bool yuv_en) { u32 idx; u32 opmode; @@ -242,17 +242,18 @@ static void _sspp_setup_opmode(struct sde_hw_pipe *ctx, return; opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); + opmode &= ~(VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT); + if (csc_en) + opmode |= VIG_OP_CSC_EN; - if (en) - opmode |= mask; - else - opmode &= ~mask; + if (yuv_en) + opmode |= VIG_OP_CSC_SRC_DATAFMT; SDE_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); } static void _sspp_setup_csc10_opmode(struct sde_hw_pipe *ctx, - u32 mask, u8 en) + bool csc_en, bool yuv_en) { u32 idx; u32 opmode; @@ -261,10 +262,12 @@ static void _sspp_setup_csc10_opmode(struct sde_hw_pipe *ctx, return; opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); - if (en) - opmode |= mask; - else - opmode &= ~mask; + opmode &= ~(VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT); + if (csc_en) + opmode |= VIG_CSC_10_EN; + + if (yuv_en) + opmode |= VIG_CSC_10_SRC_DATAFMT; SDE_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); } @@ -300,7 +303,8 @@ static void sde_hw_sspp_set_src_split_order(struct sde_hw_pipe *ctx, static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, const struct sde_format *fmt, bool const_alpha_en, u32 flags, - enum sde_sspp_multirect_index rect_mode) + enum sde_sspp_multirect_index rect_mode, + bool force_csc) { struct sde_hw_blk_reg_map *c; u32 chroma_samp, unpack, src_format; @@ -308,6 +312,7 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, u32 alpha_en_mask = 0; u32 op_mode_off, unpack_pat_off, format_off; u32 idx; + bool csc_en = force_csc || SDE_FORMAT_IS_YUV(fmt); if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !fmt) return; @@ -395,12 +400,9 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, /* update scaler opmode, if appropriate */ if (test_bit(SDE_SSPP_CSC, &ctx->cap->features)) - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, - SDE_FORMAT_IS_YUV(fmt)); + _sspp_setup_opmode(ctx, csc_en, SDE_FORMAT_IS_YUV(fmt)); else if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features)) - _sspp_setup_csc10_opmode(ctx, - VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, - SDE_FORMAT_IS_YUV(fmt)); + _sspp_setup_csc10_opmode(ctx, csc_en, SDE_FORMAT_IS_YUV(fmt)); SDE_REG_WRITE(c, format_off + idx, src_format); SDE_REG_WRITE(c, unpack_pat_off + idx, unpack); diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h index e9efb7ef98b8..93697e39971f 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h @@ -322,7 +322,8 @@ struct sde_hw_sspp_ops { void (*setup_format)(struct sde_hw_pipe *ctx, const struct sde_format *fmt, bool blend_enabled, u32 flags, - enum sde_sspp_multirect_index index); + enum sde_sspp_multirect_index index, + bool force_csc); /** * setup_rects - setup pipe ROI rectangles diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 285ebf05394b..8f3a4edf570c 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -125,8 +125,12 @@ struct sde_plane { bool revalidate; bool xin_halt_forced_clk; + const struct drm_msm_pcc *pcc_cfg; + uint32_t pcc_coeff[9]; struct sde_csc_cfg csc_cfg; + struct sde_csc_cfg csc_pcc_cfg; struct sde_csc_cfg *csc_usr_ptr; + struct sde_csc_cfg *csc_pcc_ptr; struct sde_csc_cfg *csc_ptr; const struct sde_sspp_sub_blks *pipe_sblk; @@ -1399,6 +1403,113 @@ static inline void _sde_plane_setup_csc(struct sde_plane *psde) psde->csc_ptr->csc_mv[2]); } +#define CSC_MASK 0x7fffff +#define CSC_ONE (1 << 16) +#define CSC_DGM_ONE (1 << 9) +#define CSC_10BIT_LIMIT 0x3ff +#define CSC_8BIT_LIMIT 0xff +#define PCC_MASK 0x3ffff +#define PCC_ONE (1 << 15) + +#define CSC_BIAS_CLAMP(value) \ + { 0, 0, 0 }, \ + { 0, 0, 0 }, \ + { 0, value, 0, value, 0, value }, \ + { 0, value, 0, value, 0, value } + +static const struct sde_csc_cfg sde_identity_csc_cfg = { + { + CSC_ONE, 0, 0, + 0, CSC_ONE, 0, + 0, 0, CSC_ONE, + }, + CSC_BIAS_CLAMP(CSC_8BIT_LIMIT), +}; +static const struct sde_csc_cfg sde_identity_csc10_cfg = { + { + CSC_ONE, 0, 0, + 0, CSC_ONE, 0, + 0, 0, CSC_ONE, + }, + CSC_BIAS_CLAMP(CSC_10BIT_LIMIT), +}; +static const struct sde_csc_cfg sde_identity_csc_dgm_cfg = { + { + CSC_DGM_ONE, 0, 0, + 0, CSC_DGM_ONE, 0, + 0, 0, CSC_DGM_ONE, + }, +}; + +static inline s32 csc_to_signed(u32 v) +{ + return sign_extend32(v, __fls(CSC_MASK)); +} + +static inline u32 csc_to_unsigned(s32 v) +{ + return ((u32) v) & CSC_MASK; +} + +static inline s32 pcc_to_signed(u32 v) +{ + return sign_extend32(v, __fls(PCC_MASK)); +} + +static inline void _sde_plane_mul_csc_pcc(struct sde_plane *psde, + const struct sde_csc_cfg *csc_cfg) +{ + unsigned int i, j, u; + + memcpy(&psde->csc_pcc_cfg, csc_cfg, sizeof(psde->csc_pcc_cfg)); + + for (i = 0; i < 3; i++) { + for (j = 0; j < 3; j++) { + unsigned int ij = i * 3 + j; + s64 sum = 0; + + for (u = 0; u < 3; u++) { + unsigned int iu = i * 3 + u; + unsigned int uj = u * 3 + j; + s64 csc = csc_to_signed(csc_cfg->csc_mv[uj]); + s64 pcc = pcc_to_signed(psde->pcc_coeff[iu]); + + sum += csc * pcc; + } + + sum = div_s64(sum, PCC_ONE); + + psde->csc_pcc_cfg.csc_mv[ij] = csc_to_unsigned(sum); + } + } +} + +static inline void _sde_plane_setup_csc_pcc(struct sde_plane *psde) +{ + const struct sde_csc_cfg *csc_ptr = psde->csc_ptr; + + psde->csc_pcc_ptr = NULL; + + if (!psde->pcc_cfg) + return; + + if (!csc_ptr) { + if (psde->features & BIT(SDE_SSPP_CSC_10BIT)) { + csc_ptr = &sde_identity_csc10_cfg; + } else if (psde->features & BIT(SDE_SSPP_CSC)) { + csc_ptr = &sde_identity_csc_cfg; + } else if (psde->features & BIT(SDE_SSPP_DGM_CSC)) { + csc_ptr = &sde_identity_csc_dgm_cfg; + } else { + return; + } + } + + _sde_plane_mul_csc_pcc(psde, csc_ptr); + + psde->csc_pcc_ptr = &psde->csc_pcc_cfg; +} + static void sde_color_process_plane_setup(struct drm_plane *plane) { struct sde_plane *psde; @@ -1683,7 +1794,8 @@ static int _sde_plane_color_fill(struct sde_plane *psde, psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, blend_enable, SDE_SSPP_SOLID_FILL, - pstate->multirect_index); + pstate->multirect_index, + false); if (psde->pipe_hw->ops.setup_rects) psde->pipe_hw->ops.setup_rects(psde->pipe_hw, @@ -3830,10 +3942,28 @@ static int sde_plane_atomic_check(struct drm_plane *plane, return ret; } +struct sde_csc_cfg *sde_plane_get_csc_cfg(struct drm_plane *plane) +{ + struct sde_plane_state *pstate; + struct sde_csc_cfg *csc_ptr; + struct sde_plane *psde; + + psde = to_sde_plane(plane); + pstate = to_sde_plane_state(plane->state); + + if (psde->csc_pcc_ptr) + csc_ptr = psde->csc_pcc_ptr; + else + csc_ptr = psde->csc_ptr; + + return csc_ptr; +} + void sde_plane_flush(struct drm_plane *plane) { struct sde_plane *psde; struct sde_plane_state *pstate; + struct sde_csc_cfg *csc_ptr; if (!plane || !plane->state) { SDE_ERROR("invalid plane\n"); @@ -3843,6 +3973,8 @@ void sde_plane_flush(struct drm_plane *plane) psde = to_sde_plane(plane); pstate = to_sde_plane_state(plane->state); + csc_ptr = sde_plane_get_csc_cfg(&psde->base); + /* * These updates have to be done immediately before the plane flush * timing, and may not be moved to the atomic_update/mode_set functions. @@ -3853,8 +3985,8 @@ void sde_plane_flush(struct drm_plane *plane) else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _sde_plane_color_fill(psde, psde->color_fill, 0xFF); - else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc) - psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr); + else if (psde->pipe_hw && csc_ptr && psde->pipe_hw->ops.setup_csc) + psde->pipe_hw->ops.setup_csc(psde->pipe_hw, csc_ptr); /* flag h/w flush complete */ if (plane->state) @@ -3876,10 +4008,42 @@ void sde_plane_set_error(struct drm_plane *plane, bool error) psde->is_error = error; } +static inline void _sde_plane_set_csc_pcc(struct sde_plane *psde, + struct sde_plane_state *pstate, + struct drm_crtc *crtc) +{ + const struct drm_msm_pcc *pcc_cfg = sde_cp_crtc_get_pcc_cfg(crtc); + + if (pcc_cfg == psde->pcc_cfg) + return; + + psde->pcc_cfg = pcc_cfg; + + if (pcc_cfg) { + unsigned int i = 0; + +#define set_coeff(m) \ + psde->pcc_coeff[i++] = psde->pcc_cfg->m; + + set_coeff(r.r); + set_coeff(r.g); + set_coeff(r.b); + set_coeff(g.r); + set_coeff(g.g); + set_coeff(g.b); + set_coeff(b.r); + set_coeff(b.g); + set_coeff(b.b); + } + + pstate->dirty |= SDE_PLANE_DIRTY_RECTS; +} + static int sde_plane_sspp_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { uint32_t nplanes, src_flags = 0; + struct sde_csc_cfg *csc_ptr; struct sde_plane *psde; struct drm_plane_state *state; struct sde_plane_state *pstate; @@ -4024,6 +4188,8 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, _sde_plane_sspp_atomic_check_mode_changed(psde, state, old_state); + _sde_plane_set_csc_pcc(psde, pstate, crtc); + /* re-program the output rects always if partial update roi changed */ if (sde_crtc_is_crtc_roi_dirty(crtc->state)) pstate->dirty |= SDE_PLANE_DIRTY_RECTS; @@ -4147,6 +4313,16 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, &pstate->line_insertion_cfg); } + /* update csc */ + if (SDE_FORMAT_IS_YUV(fmt)) + _sde_plane_setup_csc(psde); + else + psde->csc_ptr = 0; + + _sde_plane_setup_csc_pcc(psde); + + csc_ptr = sde_plane_get_csc_cfg(&psde->base); + if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT || pstate->dirty & SDE_PLANE_DIRTY_RECTS) && psde->pipe_hw->ops.setup_format) { @@ -4159,7 +4335,7 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, /* update format */ psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, pstate->const_alpha_en, src_flags, - pstate->multirect_index); + pstate->multirect_index, !!csc_ptr); if (psde->pipe_hw->ops.setup_cdp) { struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; @@ -4211,12 +4387,6 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, psde->pipe_hw, &pstate->sc_cfg); } - /* update csc */ - if (SDE_FORMAT_IS_YUV(fmt)) - _sde_plane_setup_csc(psde); - else - psde->csc_ptr = 0; - if (psde->pipe_hw->ops.setup_inverse_pma) { uint32_t pma_mode = 0; @@ -4230,7 +4400,7 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, if (psde->pipe_hw->ops.setup_dgm_csc) psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw, - pstate->multirect_index, psde->csc_usr_ptr); + pstate->multirect_index, csc_ptr); } sde_color_process_plane_setup(plane); From 21047b4ef925884772a3486d452c93b24e077d15 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 18 Dec 2022 21:40:00 +0200 Subject: [PATCH 115/226] techpack: display: ignore CSC config on FOD layer FOD performance decreases if the color of the icon is not exactly white, which happens when night light is enabled. Skip CSC for the FOD layer. Change-Id: Icb202690ec58e807b612fffe479c8e7c5c3b5d03 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_plane.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 8f3a4edf570c..7c55067c5469 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -3951,7 +3951,9 @@ struct sde_csc_cfg *sde_plane_get_csc_cfg(struct drm_plane *plane) psde = to_sde_plane(plane); pstate = to_sde_plane_state(plane->state); - if (psde->csc_pcc_ptr) + if (sde_plane_is_fod_layer(&pstate->base)) + csc_ptr = NULL; + else if (psde->csc_pcc_ptr) csc_ptr = psde->csc_pcc_ptr; else csc_ptr = psde->csc_ptr; From bf3b8bb804ea0d27949804c5f6175f16fa22b7d0 Mon Sep 17 00:00:00 2001 From: Demon000 Date: Tue, 27 Dec 2022 15:57:35 +0200 Subject: [PATCH 116/226] display:Fix -Wincompatible-pointer-types warning ../drivers/gpu/drm/msm/sde/sde_color_processing.c:892:9: error: incompatible pointer types returning 'unsigned char *' from a function with result type 'struct drm_msm_pcc *' [-Werror,-Wincompatible-pointer-types] return blob ? blob->data : NULL; ^~~~~~~~ 1 error generated. Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_color_processing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c index 29435986477d..0c5c4af4b309 100644 --- a/drivers/gpu/drm/msm/sde/sde_color_processing.c +++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c @@ -2132,5 +2132,5 @@ const struct drm_msm_pcc *sde_cp_crtc_get_pcc_cfg(struct drm_crtc *drm_crtc) mutex_unlock(&crtc->crtc_cp_lock); - return blob ? blob->data : NULL; + return blob ? (struct drm_msm_pcc *) blob->data : NULL; } From 4b7921c78ac63a01a0961b9635238691838ac318 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 1 Jan 2023 23:08:44 +0200 Subject: [PATCH 117/226] display: skip marking null blob changes as dirty Change-Id: I89ed0d7b59d020ee269c7b400ae1db2bb8b62984 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/msm_prop.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_prop.c b/drivers/gpu/drm/msm/msm_prop.c index f463fbfc9390..5cb6b458614a 100644 --- a/drivers/gpu/drm/msm/msm_prop.c +++ b/drivers/gpu/drm/msm/msm_prop.c @@ -379,16 +379,18 @@ int msm_property_atomic_set(struct msm_property_info *info, if ((property_idx == -EINVAL) || !property_state->values) { DRM_ERROR("invalid argument(s)\n"); } else { + bool is_blob = (property->flags & DRM_MODE_PROP_BLOB) && + (property_idx < info->blob_count); + struct drm_property_blob *prev_blob; + /* extra handling for incoming properties */ mutex_lock(&info->property_lock); - if ((property->flags & DRM_MODE_PROP_BLOB) && - (property_idx < info->blob_count)) { + if (is_blob) { + prev_blob = property_state->values[property_idx].blob; /* need to clear previous ref */ - if (property_state->values[property_idx].blob) - drm_property_blob_put( - property_state->values[ - property_idx].blob); + if (prev_blob) + drm_property_blob_put(prev_blob); /* DRM lookup also takes a reference */ blob = drm_property_lookup_blob(info->dev, @@ -409,6 +411,9 @@ int msm_property_atomic_set(struct msm_property_info *info, } } + if (is_blob && !prev_blob && !blob) + goto skip_mark_dirty; + /* update value and flag as dirty */ if (property_state->values[property_idx].value != val || info->property_data[property_idx].force_dirty) { @@ -418,6 +423,8 @@ int msm_property_atomic_set(struct msm_property_info *info, DBG("%s - %lld", property->name, val); } + +skip_mark_dirty: mutex_unlock(&info->property_lock); rc = 0; } From 3c8bbe1230f560a61ae0344617e1aa8ee67c6041 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 1 Jan 2023 23:20:43 +0200 Subject: [PATCH 118/226] display: optimize exclusion rects dirty marking Change-Id: I461f6e8a06cf0d47d5867d9fb6dcdeb23d1dfa38 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_plane.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 7c55067c5469..6cdca037e782 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -4827,6 +4827,12 @@ static void _sde_plane_install_properties(struct drm_plane *plane, PLANE_PROP_FB_TRANSLATION_MODE); } +#define cmp_and_set(old, new) \ + if ((old) != (new)) { \ + (old) = (new); \ + changed = true; \ + } + static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void __user *usr_ptr) { @@ -4991,6 +4997,7 @@ static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde, struct sde_plane_state *pstate, void __user *usr_ptr) { struct drm_clip_rect excl_rect_v1; + bool changed = false; if (!psde || !pstate) { SDE_ERROR("invalid argument(s)\n"); @@ -5009,10 +5016,13 @@ static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde, } /* populate from user space */ - pstate->excl_rect.x = excl_rect_v1.x1; - pstate->excl_rect.y = excl_rect_v1.y1; - pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1; - pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1; + cmp_and_set(pstate->excl_rect.x, excl_rect_v1.x1); + cmp_and_set(pstate->excl_rect.y, excl_rect_v1.y1); + cmp_and_set(pstate->excl_rect.w, excl_rect_v1.x2 - excl_rect_v1.x1); + cmp_and_set(pstate->excl_rect.h, excl_rect_v1.y2 - excl_rect_v1.y1); + + if (!changed) + return; SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n", pstate->excl_rect.x, pstate->excl_rect.y, From 7beeee2ed21f3af5eeb4bc18ed0af5ac36d7e516 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 4 Jan 2023 02:40:17 +0200 Subject: [PATCH 119/226] display: do not create virtual planes for VIG planes Multirect virtual planes have an issue with CSC causing apparent non-CSC flashes. Without smart DMA, SDE doesn't register any multirect virtual planes. This is a very hacky solution, that might cause some performance defficits. Change-Id: I84d90c7cbb7661e99831b158e81c88de84f87d3f Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_hw_catalog.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h index 95c267021de5..8e0ea22262a6 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h @@ -1350,9 +1350,11 @@ void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg); */ static inline bool sde_hw_sspp_multirect_enabled(const struct sde_sspp_cfg *cfg) { - return test_bit(SDE_SSPP_SMART_DMA_V1, &cfg->features) || + return (test_bit(SDE_SSPP_SMART_DMA_V1, &cfg->features) || test_bit(SDE_SSPP_SMART_DMA_V2, &cfg->features) || - test_bit(SDE_SSPP_SMART_DMA_V2p5, &cfg->features); + test_bit(SDE_SSPP_SMART_DMA_V2p5, &cfg->features)) + && !(test_bit(SDE_SSPP_CSC_10BIT, &cfg->features) || + test_bit(SDE_SSPP_CSC, &cfg->features)); } static inline bool sde_hw_intf_te_supported(const struct sde_mdss_cfg *sde_cfg) From b2746a23b500e60dd72b37c5d3ec09c6fd25eb58 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 18 Dec 2022 06:34:39 +0200 Subject: [PATCH 120/226] Revert "display: sde_hw_mdss: Increase sde stage to map zpos changes" This reverts commit 278de1c2b2ace0b809fa7215ee8df2f0b9f92493. Change-Id: I68fe99e9e9602b65685b4b55b50ee5a87c166c3c Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_hw_mdss.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h index fbbec709a569..bd3ef45df834 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h @@ -174,7 +174,6 @@ enum sde_stage { SDE_STAGE_8, SDE_STAGE_9, SDE_STAGE_10, - SDE_STAGE_11, SDE_STAGE_MAX }; enum sde_dspp { From 9529ca38181b4635204b61046f72ffde6065a771 Mon Sep 17 00:00:00 2001 From: pwnrazr <1644943+pwnrazr@users.noreply.github.com> Date: Thu, 5 Jan 2023 14:46:31 +0800 Subject: [PATCH 121/226] Revert "disp: msm: Notify sysfs for fod ui changes" This reverts commit ef1691701b1474756b9862089bbb6b4735bd6f8f. Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 72 +++++++++++++------ drivers/gpu/drm/msm/dsi-staging/dsi_display.h | 4 -- drivers/gpu/drm/msm/sde/sde_connector.c | 2 - 3 files changed, 51 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 4db608879026..5ad46bc1c4fb 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -5046,29 +5046,67 @@ static int dsi_display_validate_split_link(struct dsi_display *display) return rc; } -static ssize_t sysfs_fod_ui_read(struct device *dev, - struct device_attribute *attr, char *buf) +static ssize_t sysfs_hbm_read(struct device *dev, + struct device_attribute *attr, char *buf) { - struct dsi_display *display; - bool status; + struct dsi_display *display = dev_get_drvdata(dev); + if (!display->panel) + return 0; - display = dev_get_drvdata(dev); - if (!display) { - pr_err("Invalid display\n"); + return scnprintf(buf, PAGE_SIZE, "%d\n", display->panel->hbm_mode); +} + +static ssize_t sysfs_hbm_write(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct dsi_display *display = dev_get_drvdata(dev); + int ret, hbm_mode; + + if (!display->panel) return -EINVAL; + + ret = kstrtoint(buf, 10, &hbm_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + mutex_lock(&display->display_lock); + + display->panel->hbm_mode = hbm_mode; + if (!dsi_panel_initialized(display->panel)) + goto error; + + ret = dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (ret) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + display->name, ret); + goto error; } - status = atomic_read(&display->fod_ui); + ret = dsi_panel_apply_hbm_mode(display->panel); + if (ret) + pr_err("unable to set hbm mode\n"); - return snprintf(buf, PAGE_SIZE, "%d\n", status); + ret = dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (ret) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + display->name, ret); + goto error; + } +error: + mutex_unlock(&display->display_lock); + return ret == 0 ? count : ret; } -static DEVICE_ATTR(fod_ui, 0444, - sysfs_fod_ui_read, - NULL); +static DEVICE_ATTR(hbm, 0644, + sysfs_hbm_read, + sysfs_hbm_write); static struct attribute *display_fs_attrs[] = { - &dev_attr_fod_ui.attr, + &dev_attr_hbm.attr, NULL, }; static struct attribute_group display_fs_attrs_group = { @@ -5104,13 +5142,6 @@ static int dsi_display_sysfs_deinit(struct dsi_display *display) } -void dsi_display_set_fod_ui(struct dsi_display *display, bool status) -{ - struct device *dev = &display->pdev->dev; - atomic_set(&display->fod_ui, status); - sysfs_notify(&dev->kobj, NULL, "fod_ui"); -} - /** * dsi_display_bind - bind dsi device with controlling device * @dev: Pointer to base of platform device @@ -5407,7 +5438,6 @@ static void dsi_display_unbind(struct device *dev, } atomic_set(&display->clkrate_change_pending, 0); - atomic_set(&display->fod_ui, false); (void)dsi_display_sysfs_deinit(display); (void)dsi_display_debugfs_deinit(display); diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 0331f097321e..6546e60cf083 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -284,8 +284,6 @@ struct dsi_display { struct dsi_display_boot_param *boot_disp; u32 te_source; - - atomic_t fod_ui; }; int dsi_display_dev_probe(struct platform_device *pdev); @@ -719,8 +717,6 @@ int dsi_display_get_panel_vfp(void *display, struct dsi_display *get_main_display(void); -void dsi_display_set_fod_ui(struct dsi_display *display, bool status); - int dsi_display_cmd_engine_enable(struct dsi_display *display); int dsi_display_cmd_engine_disable(struct dsi_display *display); diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index 398fb943a8fc..55c740c916f1 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -617,8 +617,6 @@ void sde_connector_update_fod_hbm(struct drm_connector *connector) mutex_lock(&display->panel->panel_lock); dsi_panel_set_fod_hbm(display->panel, status); mutex_unlock(&display->panel->panel_lock); - - dsi_display_set_fod_ui(display, status); } int sde_connector_pre_kickoff(struct drm_connector *connector) From 409c31b589a283d3696e520f16c68c3546522f77 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sat, 17 Dec 2022 18:18:30 +0200 Subject: [PATCH 122/226] Revert "display: sde_connector: update FOD HBM on dim layer change" This reverts commit 81d581e862ca5e176c8ca665dff709262f991c1b. Change-Id: Iefe2abbb8e3b1f82c353036a734941203fa9bab4 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_connector.c | 35 ------------------------- 1 file changed, 35 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index 55c740c916f1..f35a7a71ae7a 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -586,39 +586,6 @@ static int _sde_connector_update_dirty_properties( return 0; } -void sde_connector_update_fod_hbm(struct drm_connector *connector) -{ - static atomic_t effective_status = ATOMIC_INIT(false); - struct sde_crtc_state *cstate; - struct sde_connector *c_conn; - struct dsi_display *display; - bool status; - - if (!connector) { - SDE_ERROR("invalid connector\n"); - return; - } - - c_conn = to_sde_connector(connector); - if (c_conn->connector_type != DRM_MODE_CONNECTOR_DSI) - return; - - display = (struct dsi_display *) c_conn->display; - - if (!c_conn->encoder || !c_conn->encoder->crtc || - !c_conn->encoder->crtc->state) - return; - - cstate = to_sde_crtc_state(c_conn->encoder->crtc->state); - status = cstate->fod_dim_layer != NULL; - if (atomic_xchg(&effective_status, status) == status) - return; - - mutex_lock(&display->panel->panel_lock); - dsi_panel_set_fod_hbm(display->panel, status); - mutex_unlock(&display->panel->panel_lock); -} - int sde_connector_pre_kickoff(struct drm_connector *connector) { struct sde_connector *c_conn; @@ -652,8 +619,6 @@ int sde_connector_pre_kickoff(struct drm_connector *connector) SDE_EVT32_VERBOSE(connector->base.id); - sde_connector_update_fod_hbm(connector); - rc = c_conn->ops.pre_kickoff(connector, c_conn->display, ¶ms); end: From fca96657eb4ca6034ac6fad954103c2e98b6920e Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sat, 17 Dec 2022 18:18:34 +0200 Subject: [PATCH 123/226] Revert "display: sde_crtc: setup dim layer" This reverts commit eb8c3fdd8fac2dafb220058a3efef6a5567008c8. Change-Id: Ia452d135c32136b0e856431c4604c8bfa5aee72c Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_crtc.c | 87 ------------------------------ drivers/gpu/drm/msm/sde/sde_crtc.h | 1 - 2 files changed, 88 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index 39e8d9605b0c..f39c40c86b98 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -42,7 +42,6 @@ #include "sde_power_handle.h" #include "sde_core_perf.h" #include "sde_trace.h" -#include "dsi_display.h" #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4) #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2) @@ -2188,10 +2187,6 @@ static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc, for (i = 0; i < cstate->num_dim_layers; i++) _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc, mixer, &cstate->dim_layer[i]); - - if (cstate->fod_dim_layer) - _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc, - mixer, cstate->fod_dim_layer); } _sde_crtc_program_lm_output_roi(crtc); @@ -5306,86 +5301,6 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, return 0; } -static struct sde_hw_dim_layer* sde_crtc_setup_fod_dim_layer( - struct sde_crtc_state *cstate, - uint32_t stage) -{ - struct drm_crtc_state *crtc_state = &cstate->base; - struct drm_display_mode *mode = &crtc_state->adjusted_mode; - struct sde_hw_dim_layer *dim_layer = NULL; - struct dsi_display *display; - struct sde_kms *kms; - uint32_t layer_stage; - uint32_t alpha; - - kms = _sde_crtc_get_kms(crtc_state->crtc); - if (!kms || !kms->catalog) { - SDE_ERROR("Invalid kms\n"); - goto error; - } - - layer_stage = SDE_STAGE_0 + stage; - if (layer_stage >= kms->catalog->mixer[0].sblk->maxblendstages) { - SDE_ERROR("Stage too large %u vs max %u\n", layer_stage, - kms->catalog->mixer[0].sblk->maxblendstages); - goto error; - } - - if (cstate->num_dim_layers == SDE_MAX_DIM_LAYERS) { - SDE_ERROR("Max dim layers reached\n"); - goto error; - } - - display = get_main_display(); - if (!display || !display->panel) { - SDE_ERROR("Invalid primary display\n"); - goto error; - } - - mutex_lock(&display->panel->panel_lock); - alpha = dsi_panel_get_fod_dim_alpha(display->panel); - mutex_unlock(&display->panel->panel_lock); - - dim_layer = &cstate->dim_layer[cstate->num_dim_layers]; - dim_layer->flags = SDE_DRM_DIM_LAYER_INCLUSIVE; - dim_layer->stage = layer_stage; - dim_layer->rect.x = 0; - dim_layer->rect.y = 0; - dim_layer->rect.w = mode->hdisplay; - dim_layer->rect.h = mode->vdisplay; - dim_layer->color_fill = - (struct sde_mdss_color) {0, 0, 0, alpha}; - -error: - return dim_layer; -} - -static void sde_crtc_fod_atomic_check(struct sde_crtc_state *cstate, - struct plane_state *pstates, int cnt) -{ - uint32_t dim_layer_stage; - int plane_idx; - - for (plane_idx = 0; plane_idx < cnt; plane_idx++) - if (sde_plane_is_fod_layer(pstates[plane_idx].drm_pstate)) - break; - - if (plane_idx == cnt) { - cstate->fod_dim_layer = NULL; - } else { - dim_layer_stage = pstates[plane_idx].stage; - cstate->fod_dim_layer = sde_crtc_setup_fod_dim_layer(cstate, - dim_layer_stage); - } - - if (!cstate->fod_dim_layer) - return; - - for (plane_idx = 0; plane_idx < cnt; plane_idx++) - if (pstates[plane_idx].stage >= dim_layer_stage) - pstates[plane_idx].stage++; -} - static int sde_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -5581,8 +5496,6 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, } } - sde_crtc_fod_atomic_check(cstate, pstates, cnt); - /* assign mixer stages based on sorted zpos property */ if (cnt > 0) sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h index b4f52df21cc7..0357ab4f4dfe 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.h +++ b/drivers/gpu/drm/msm/sde/sde_crtc.h @@ -422,7 +422,6 @@ struct sde_crtc_state { uint64_t input_fence_timeout_ns; uint32_t num_dim_layers; struct sde_hw_dim_layer dim_layer[SDE_MAX_DIM_LAYERS]; - struct sde_hw_dim_layer *fod_dim_layer; uint32_t num_ds; uint32_t num_ds_enabled; bool ds_dirty; From be7cf6f6b92daa9800ae572c1324c4e9e61bbf5a Mon Sep 17 00:00:00 2001 From: pwnrazr <1644943+pwnrazr@users.noreply.github.com> Date: Thu, 5 Jan 2023 21:36:08 +0800 Subject: [PATCH 124/226] drivers: dsi_panel: prepare for new fod stuff Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 99 --------------------- drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 13 +-- 2 files changed, 3 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index ab7aa8c80dea..8c0f3b8f103d 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -753,39 +753,6 @@ static int dsi_panel_update_pwm_backlight(struct dsi_panel *panel, return rc; } -static u32 dsi_panel_get_backlight(struct dsi_panel *panel) -{ - return panel->bl_config.bl_level; -} - -static u32 interpolate(uint32_t x, uint32_t xa, uint32_t xb, uint32_t ya, uint32_t yb) -{ - return ya - (ya - yb) * (x - xa) / (xb - xa); -} - -u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) -{ - u32 brightness = dsi_panel_get_backlight(panel); - int i; - - if (!panel->fod_dim_lut) - return 0; - - for (i = 0; i < panel->fod_dim_lut_count; i++) - if (panel->fod_dim_lut[i].brightness >= brightness) - break; - - if (i == 0) - return panel->fod_dim_lut[i].alpha; - - if (i == panel->fod_dim_lut_count) - return panel->fod_dim_lut[i - 1].alpha; - - return interpolate(brightness, - panel->fod_dim_lut[i - 1].brightness, panel->fod_dim_lut[i].brightness, - panel->fod_dim_lut[i - 1].alpha, panel->fod_dim_lut[i].alpha); -} - int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status) { int rc = 0; @@ -2783,68 +2750,6 @@ static int dsi_panel_parse_bl_pwm_config(struct dsi_panel *panel) return rc; } -static int dsi_panel_parse_fod_dim_lut(struct dsi_panel *panel, - struct dsi_parser_utils *utils) -{ - struct brightness_alpha_pair *lut; - u32 *array; - int count; - int len; - int rc; - int i; - - len = utils->count_u32_elems(utils->data, "qcom,disp-fod-dim-lut"); - if (len <= 0 || len % BRIGHTNESS_ALPHA_PAIR_LEN) { - pr_err("[%s] invalid number of elements, rc=%d\n", - panel->name, rc); - rc = -EINVAL; - goto count_fail; - } - - array = kcalloc(len, sizeof(u32), GFP_KERNEL); - if (!array) { - pr_err("[%s] failed to allocate memory, rc=%d\n", - panel->name, rc); - rc = -ENOMEM; - goto alloc_array_fail; - } - - rc = utils->read_u32_array(utils->data, - "qcom,disp-fod-dim-lut", array, len); - if (rc) { - pr_err("[%s] failed to allocate memory, rc=%d\n", - panel->name, rc); - goto read_fail; - } - - count = len / BRIGHTNESS_ALPHA_PAIR_LEN; - lut = kcalloc(count, sizeof(*lut), GFP_KERNEL); - if (!lut) { - rc = -ENOMEM; - goto alloc_lut_fail; - } - - for (i = 0; i < count; i++) { - struct brightness_alpha_pair *pair = &lut[i]; - pair->brightness = array[i * BRIGHTNESS_ALPHA_PAIR_LEN + 0]; - pair->alpha = array[i * BRIGHTNESS_ALPHA_PAIR_LEN + 1]; - } - - panel->fod_dim_lut = lut; - panel->fod_dim_lut_count = count; - -alloc_lut_fail: -read_fail: - kfree(array); -alloc_array_fail: -count_fail: - if (rc) { - panel->fod_dim_lut = NULL; - panel->fod_dim_lut_count = 0; - } - return rc; -} - static int dsi_panel_parse_bl_config(struct dsi_panel *panel) { int rc = 0; @@ -2934,10 +2839,6 @@ static int dsi_panel_parse_bl_config(struct dsi_panel *panel) panel->bl_config.bl_inverted_dbv = utils->read_bool(utils->data, "qcom,mdss-dsi-bl-inverted-dbv"); - rc = dsi_panel_parse_fod_dim_lut(panel, utils); - if (rc) - pr_err("[%s failed to parse fod dim lut\n", panel->name); - if (panel->bl_config.type == DSI_BACKLIGHT_PWM) { rc = dsi_panel_parse_bl_pwm_config(panel); if (rc) { diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index b8e0aa5b2b0e..b801a1c42d52 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -179,12 +179,6 @@ struct drm_panel_esd_config { #endif }; -#define BRIGHTNESS_ALPHA_PAIR_LEN 2 -struct brightness_alpha_pair { - u32 brightness; - u32 alpha; -}; - #if defined(CONFIG_MACH_XIAOMI_VAYU) || defined(CONFIG_MACH_XIAOMI_NABU) struct lockdowninfo_cfg { u8 lockdowninfo[16]; @@ -251,7 +245,6 @@ struct dsi_panel { int power_mode; enum dsi_panel_physical_type panel_type; - struct brightness_alpha_pair *fod_dim_lut; u32 fod_dim_lut_count; bool cphy_esd_check; @@ -266,6 +259,8 @@ struct dsi_panel { struct lockdowninfo_cfg lockdowninfo_read; #endif + int hbm_mode; + bool resend_ea; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -386,9 +381,6 @@ int dsi_panel_parse_esd_reg_read_configs(struct dsi_panel *panel); void dsi_panel_ext_bridge_put(struct dsi_panel *panel); -int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status); - -u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel); int dsi_panel_set_esd_check(struct dsi_panel *panel); @@ -408,5 +400,6 @@ void dsi_panel_doubleclick_enable(bool on); int dsi_panel_lockdowninfo_param_read(struct dsi_panel *panel); #endif +int dsi_panel_apply_hbm_mode(struct dsi_panel *panel); #endif /* _DSI_PANEL_H_ */ From 7097c6f24a4f8fd0d79ced120ea7a6dad28e2882 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Thu, 10 Feb 2022 15:08:04 +0200 Subject: [PATCH 125/226] display: dsi_panel: read FOD dimming LUT Change-Id: I23f7914ce0adf6c1942c09212516ed5f6b22d289 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 58 +++++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 9 ++++ 2 files changed, 67 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 8c0f3b8f103d..ea80048cc494 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -2750,6 +2750,60 @@ static int dsi_panel_parse_bl_pwm_config(struct dsi_panel *panel) return rc; } +static int dsi_panel_parse_fod_dim_lut(struct dsi_panel *panel, + struct dsi_parser_utils *utils) +{ + const char *prop_name = "qcom,fod-dim-lut"; + unsigned int i; + u32 *array; + int count; + int rc; + + count = utils->count_u32_elems(utils->data, prop_name); + if (count <= 0 || count % BRIGHTNESS_ALPHA_PAIR_LEN) { + pr_err("[%s] invalid number of elements %d\n", + panel->name, count); + rc = -EINVAL; + goto count_fail; + } + + array = kcalloc(count, sizeof(u32), GFP_KERNEL); + if (!array) { + rc = -ENOMEM; + goto alloc_array_fail; + } + + rc = utils->read_u32_array(utils->data, prop_name, array, count); + if (rc) { + pr_err("[%s] failed to read array, rc=%d\n", panel->name, rc); + goto read_fail; + } + + count /= BRIGHTNESS_ALPHA_PAIR_LEN; + panel->fod_dim_lut = kcalloc(count, sizeof(*panel->fod_dim_lut), + GFP_KERNEL); + if (!panel->fod_dim_lut) { + rc = -ENOMEM; + goto alloc_lut_fail; + } + + panel->fod_dim_lut_len = count; + + for (i = 0; i < count; i++) { + struct brightness_alpha_pair *pair = &panel->fod_dim_lut[i]; + pair->brightness = array[i * BRIGHTNESS_ALPHA_PAIR_LEN + 0]; + pair->alpha = array[i * BRIGHTNESS_ALPHA_PAIR_LEN + 1]; + } + +alloc_lut_fail: +read_fail: + kfree(array); +alloc_array_fail: +count_fail: + + return rc; +} + static int dsi_panel_parse_bl_config(struct dsi_panel *panel) { int rc = 0; @@ -2839,6 +2893,10 @@ static int dsi_panel_parse_bl_config(struct dsi_panel *panel) panel->bl_config.bl_inverted_dbv = utils->read_bool(utils->data, "qcom,mdss-dsi-bl-inverted-dbv"); + rc = dsi_panel_parse_fod_dim_lut(panel, utils); + if (rc) + pr_err("[%s] failed to parse fod dim lut\n", panel->name); + if (panel->bl_config.type == DSI_BACKLIGHT_PWM) { rc = dsi_panel_parse_bl_pwm_config(panel); if (rc) { diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index b801a1c42d52..f7a6229aee82 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -194,6 +194,12 @@ struct dsi_read_config { }; #endif +#define BRIGHTNESS_ALPHA_PAIR_LEN 2 +struct brightness_alpha_pair { + u16 brightness; + u8 alpha; +}; + struct dsi_panel { const char *name; const char *type; @@ -261,6 +267,9 @@ struct dsi_panel { #endif int hbm_mode; bool resend_ea; + + struct brightness_alpha_pair *fod_dim_lut; + unsigned int fod_dim_lut_len; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) From e402d376669d2e95e3368a616c56c630d4580ced Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 18 Dec 2022 04:47:12 +0200 Subject: [PATCH 126/226] display: use CSC for FOD dimming Change-Id: I713646b79c6fafda14614ff9eca742f2724420e3 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_crtc.c | 38 +++++++++++++++++++++++++++++ drivers/gpu/drm/msm/sde/sde_crtc.h | 5 ++++ drivers/gpu/drm/msm/sde/sde_plane.c | 32 +++++++++++++++++++++++- drivers/gpu/drm/msm/sde/sde_plane.h | 4 +++ 4 files changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index f39c40c86b98..0ae0d9eef458 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -42,6 +42,7 @@ #include "sde_power_handle.h" #include "sde_core_perf.h" #include "sde_trace.h" +#include "dsi_display.h" #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4) #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2) @@ -5301,6 +5302,34 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, return 0; } +static void sde_crtc_fod_atomic_check(struct sde_crtc_state *cstate, + struct plane_state *pstates, int cnt) +{ + unsigned int fod_plane_idx, plane_idx; + u8 alpha = 0; + + for (plane_idx = 0; plane_idx < cnt; plane_idx++) + if (sde_plane_is_fod_layer(pstates[plane_idx].drm_pstate)) + break; + + fod_plane_idx = plane_idx; + + if (fod_plane_idx != cnt) { + struct dsi_display *display = get_main_display(); + alpha = dsi_panel_get_fod_dim_alpha(display->panel); + } + + cstate->fod_dim_alpha = alpha; + + for (plane_idx = 0; plane_idx < cnt; plane_idx++) { + if (plane_idx == fod_plane_idx) + continue; + + sde_plane_set_fod_dim_alpha(pstates[plane_idx].sde_pstate, + alpha); + } +} + static int sde_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { @@ -5496,6 +5525,8 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, } } + sde_crtc_fod_atomic_check(cstate, pstates, cnt); + /* assign mixer stages based on sorted zpos property */ if (cnt > 0) sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); @@ -5603,6 +5634,13 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, return rc; } +bool sde_crtc_is_fod_enabled(struct drm_crtc_state *state) +{ + struct sde_crtc_state *cstate = to_sde_crtc_state(state); + + return cstate->fod_dim_alpha != 0; +} + /** * sde_crtc_get_num_datapath - get the number of datapath active * of primary connector diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h index 0357ab4f4dfe..428af58cd407 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.h +++ b/drivers/gpu/drm/msm/sde/sde_crtc.h @@ -439,6 +439,8 @@ struct sde_crtc_state { u32 padding_dummy; struct sde_crtc_respool rp; + + u8 fod_dim_alpha; }; enum sde_crtc_irq_state { @@ -866,4 +868,7 @@ int sde_crtc_get_num_datapath(struct drm_crtc *crtc, * @cstate: Pointer to drm crtc state */ void _sde_crtc_clear_dim_layers_v1(struct drm_crtc_state *state); + +bool sde_crtc_is_fod_enabled(struct drm_crtc_state *state); + #endif /* _SDE_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 6cdca037e782..743552ab169f 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -148,6 +148,8 @@ struct sde_plane { struct sde_debugfs_regset32 debugfs_scaler; struct sde_debugfs_regset32 debugfs_csc; bool debugfs_default_scale; + + u8 fod_dim_alpha; }; #define to_sde_plane(x) container_of(x, struct sde_plane, base) @@ -1410,6 +1412,7 @@ static inline void _sde_plane_setup_csc(struct sde_plane *psde) #define CSC_8BIT_LIMIT 0xff #define PCC_MASK 0x3ffff #define PCC_ONE (1 << 15) +#define FOD_DIM_ALPHA_MAX 255 #define CSC_BIAS_CLAMP(value) \ { 0, 0, 0 }, \ @@ -1417,6 +1420,11 @@ static inline void _sde_plane_setup_csc(struct sde_plane *psde) { 0, value, 0, value, 0, value }, \ { 0, value, 0, value, 0, value } +static const struct drm_msm_pcc sde_identity_pcc_cfg = { + .r = { .r = PCC_ONE }, + .g = { .g = PCC_ONE }, + .b = { .b = PCC_ONE }, +}; static const struct sde_csc_cfg sde_identity_csc_cfg = { { CSC_ONE, 0, 0, @@ -1459,6 +1467,7 @@ static inline s32 pcc_to_signed(u32 v) static inline void _sde_plane_mul_csc_pcc(struct sde_plane *psde, const struct sde_csc_cfg *csc_cfg) { + unsigned int fod_dim_scale = FOD_DIM_ALPHA_MAX - psde->fod_dim_alpha; unsigned int i, j, u; memcpy(&psde->csc_pcc_cfg, csc_cfg, sizeof(psde->csc_pcc_cfg)); @@ -1477,7 +1486,8 @@ static inline void _sde_plane_mul_csc_pcc(struct sde_plane *psde, sum += csc * pcc; } - sum = div_s64(sum, PCC_ONE); + sum = mult_frac(sum, fod_dim_scale, + PCC_ONE * FOD_DIM_ALPHA_MAX); psde->csc_pcc_cfg.csc_mv[ij] = csc_to_unsigned(sum); } @@ -4010,12 +4020,26 @@ void sde_plane_set_error(struct drm_plane *plane, bool error) psde->is_error = error; } +static inline void _set_plane_set_fod_dim_alpha(struct sde_plane *psde, + struct sde_plane_state *pstate) +{ + if (psde->fod_dim_alpha == pstate->fod_dim_alpha) + return; + + psde->fod_dim_alpha = pstate->fod_dim_alpha; + + pstate->dirty |= SDE_PLANE_DIRTY_RECTS; +} + static inline void _sde_plane_set_csc_pcc(struct sde_plane *psde, struct sde_plane_state *pstate, struct drm_crtc *crtc) { const struct drm_msm_pcc *pcc_cfg = sde_cp_crtc_get_pcc_cfg(crtc); + if (!pcc_cfg && psde->fod_dim_alpha) + pcc_cfg = &sde_identity_pcc_cfg; + if (pcc_cfg == psde->pcc_cfg) return; @@ -4190,6 +4214,7 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, _sde_plane_sspp_atomic_check_mode_changed(psde, state, old_state); + _set_plane_set_fod_dim_alpha(psde, pstate); _sde_plane_set_csc_pcc(psde, pstate, crtc); /* re-program the output rects always if partial update roi changed */ @@ -4482,6 +4507,11 @@ int sde_plane_is_fod_layer(const struct drm_plane_state *drm_state) return sde_plane_get_property(pstate, PLANE_PROP_FOD); } +void sde_plane_set_fod_dim_alpha(struct sde_plane_state *pstate, u8 alpha) +{ + pstate->fod_dim_alpha = alpha; +} + static void sde_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { diff --git a/drivers/gpu/drm/msm/sde/sde_plane.h b/drivers/gpu/drm/msm/sde/sde_plane.h index bd8b633e2375..b49ac780edfd 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.h +++ b/drivers/gpu/drm/msm/sde/sde_plane.h @@ -171,6 +171,8 @@ struct sde_plane_state { struct sde_hw_pipe_cdp_cfg cdp_cfg; struct sde_hw_pipe_line_insertion_cfg line_insertion_cfg; + + u8 fod_dim_alpha; }; /** @@ -400,4 +402,6 @@ void sde_plane_setup_src_split_order(struct drm_plane *plane, int sde_plane_is_fod_layer(const struct drm_plane_state *drm_state); +void sde_plane_set_fod_dim_alpha(struct sde_plane_state *pstatem, u8 alpha); + #endif /* _SDE_PLANE_H_ */ From 13dd5bf4134a6244651ad38d0d220ad508e7a5b0 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 19 Dec 2022 16:33:16 +0200 Subject: [PATCH 127/226] display: dsi_panel: expose FOD dim alpha Change-Id: I2c4431105df6082fcfbaacdbab9165f89720824b Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 11 +++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 3 ++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index ea80048cc494..82f58a321679 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -753,6 +753,17 @@ static int dsi_panel_update_pwm_backlight(struct dsi_panel *panel, return rc; } +u8 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) +{ + u8 alpha; + + mutex_lock(&panel->panel_lock); + alpha = panel->fod_dim_alpha; + mutex_unlock(&panel->panel_lock); + + return alpha; +} + int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status) { int rc = 0; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index f7a6229aee82..613f1acbe583 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -390,7 +390,6 @@ int dsi_panel_parse_esd_reg_read_configs(struct dsi_panel *panel); void dsi_panel_ext_bridge_put(struct dsi_panel *panel); - int dsi_panel_set_esd_check(struct dsi_panel *panel); int dsi_panel_sync_pen_fps(struct dsi_panel *panel, @@ -409,6 +408,8 @@ void dsi_panel_doubleclick_enable(bool on); int dsi_panel_lockdowninfo_param_read(struct dsi_panel *panel); #endif +u8 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel); + int dsi_panel_apply_hbm_mode(struct dsi_panel *panel); #endif /* _DSI_PANEL_H_ */ From 89ffacaeaceaba781e704acb3578221a93569cf7 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Thu, 10 Feb 2022 15:15:59 +0200 Subject: [PATCH 128/226] display: dsi_panel: expose FOD dim Change-Id: I439f536efefb7b338462ccf6d03b078cea76c1c3 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 40 +++++++++++++++++++-- drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 4 +++ 2 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 82f58a321679..e6fc3725cb4e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -764,6 +764,42 @@ u8 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) return alpha; } +static u32 dsi_panel_get_backlight(struct dsi_panel *panel) +{ + return panel->bl_config.real_bl_level; +} + +static u32 interpolate(uint32_t x, uint32_t xa, uint32_t xb, + uint32_t ya, uint32_t yb) +{ + return ya - (ya - yb) * (x - xa) / (xb - xa); +} + +static u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) +{ + u32 brightness = dsi_panel_get_backlight(panel); + int i; + + if (!panel->fod_dim_lut) + return 0; + + for (i = 0; i < panel->fod_dim_lut_len; i++) + if (panel->fod_dim_lut[i].brightness >= brightness) + break; + + if (i == 0) + return panel->fod_dim_lut[i].alpha; + + if (i == panel->fod_dim_lut_len) + return panel->fod_dim_lut[i - 1].alpha; + + return interpolate(brightness, + panel->fod_dim_lut[i - 1].brightness, + panel->fod_dim_lut[i].brightness, + panel->fod_dim_lut[i - 1].alpha, + panel->fod_dim_lut[i].alpha); +} + int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status) { int rc = 0; @@ -1182,9 +1218,7 @@ int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) rc = -ENOTSUPP; } - if (last_backlight == 0 && panel->cphy_esd_check) { - schedule_delayed_work(&panel->esd_work, msecs_to_jiffies(300)); - } + panel->fod_dim_alpha = dsi_panel_get_fod_dim_alpha(panel); return rc; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index 613f1acbe583..4ec3bda5432d 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -270,6 +270,8 @@ struct dsi_panel { struct brightness_alpha_pair *fod_dim_lut; unsigned int fod_dim_lut_len; + u8 fod_dim_alpha; + bool fod_hbm_enabled; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -412,4 +414,6 @@ u8 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel); int dsi_panel_apply_hbm_mode(struct dsi_panel *panel); +int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status); + #endif /* _DSI_PANEL_H_ */ From ba9069f01bf6102254e638ba292c6dc657e4ea37 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 10 Sep 2021 00:47:53 +0300 Subject: [PATCH 129/226] display: dsi_panel: track real backlight value Change-Id: I5b6d71687cc6c208381c285187eaa1a6bfffecc7 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 2 ++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index e6fc3725cb4e..e15a59324cd2 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -1218,6 +1218,7 @@ int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) rc = -ENOTSUPP; } + bl->real_bl_level = bl_lvl; panel->fod_dim_alpha = dsi_panel_get_fod_dim_alpha(panel); return rc; @@ -2896,6 +2897,7 @@ static int dsi_panel_parse_bl_config(struct dsi_panel *panel) panel->bl_config.bl_scale = MAX_BL_SCALE_LEVEL; panel->bl_config.bl_scale_ad = MAX_AD_BL_SCALE_LEVEL; + panel->bl_config.real_bl_level = 0; rc = utils->read_u32(utils->data, "qcom,mdss-dsi-bl-min-level", &val); if (rc) { diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index 4ec3bda5432d..e5379c6b0e48 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -124,6 +124,7 @@ struct dsi_backlight_config { u32 bl_scale; u32 bl_scale_ad; bool bl_inverted_dbv; + u32 real_bl_level; int en_gpio; bool dcs_type_ss; From 11d920e8a159cf059d0f11956a2014204d440af7 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sat, 17 Dec 2022 18:37:26 +0200 Subject: [PATCH 130/226] display: dsi_panel_get_fod_dim_alpha -> dsi_panel_calc_fod_dim_alpha Change-Id: I7d27bb9ff4d2f5eebb7a1cf4365ac1850b264b37 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index e15a59324cd2..27e945ca38e7 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -764,27 +764,21 @@ u8 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) return alpha; } -static u32 dsi_panel_get_backlight(struct dsi_panel *panel) -{ - return panel->bl_config.real_bl_level; -} - static u32 interpolate(uint32_t x, uint32_t xa, uint32_t xb, uint32_t ya, uint32_t yb) { return ya - (ya - yb) * (x - xa) / (xb - xa); } -static u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) +static u32 dsi_panel_calc_fod_dim_alpha(struct dsi_panel *panel, u32 bl_level) { - u32 brightness = dsi_panel_get_backlight(panel); int i; if (!panel->fod_dim_lut) return 0; for (i = 0; i < panel->fod_dim_lut_len; i++) - if (panel->fod_dim_lut[i].brightness >= brightness) + if (panel->fod_dim_lut[i].brightness >= bl_level) break; if (i == 0) @@ -793,7 +787,7 @@ static u32 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel) if (i == panel->fod_dim_lut_len) return panel->fod_dim_lut[i - 1].alpha; - return interpolate(brightness, + return interpolate(bl_level, panel->fod_dim_lut[i - 1].brightness, panel->fod_dim_lut[i].brightness, panel->fod_dim_lut[i - 1].alpha, @@ -1219,7 +1213,7 @@ int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) } bl->real_bl_level = bl_lvl; - panel->fod_dim_alpha = dsi_panel_get_fod_dim_alpha(panel); + panel->fod_dim_alpha = dsi_panel_calc_fod_dim_alpha(panel, bl_lvl); return rc; } From 9a8905814e8ede76154bb92909a8fe77992030ca Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Thu, 10 Feb 2022 10:35:42 +0200 Subject: [PATCH 131/226] display: dsi_panel: create empty ettributes group Change-Id: Ia1e747272240d380c82843d9faeeedac7bc58d9b Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 37 +++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 27e945ca38e7..7f596326bee5 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -4070,8 +4070,34 @@ struct dsi_panel *dsi_panel_get(struct device *parent, return ERR_PTR(rc); } +static struct attribute *panel_attrs[] = { + NULL, +}; + +static struct attribute_group panel_attrs_group = { + .attrs = panel_attrs, +}; + +static int dsi_panel_sysfs_init(struct dsi_panel *panel) +{ + int rc = 0; + + rc = sysfs_create_group(&panel->parent->kobj, &panel_attrs_group); + if (rc) + pr_err("failed to create panel sysfs attributes\n"); + + return rc; +} + +static void dsi_panel_sysfs_deinit(struct dsi_panel *panel) +{ + sysfs_remove_group(&panel->parent->kobj, &panel_attrs_group); +} + void dsi_panel_put(struct dsi_panel *panel) { + dsi_panel_sysfs_deinit(panel); + /* free resources allocated for ESD check */ dsi_panel_esd_config_deinit(&panel->esd_config); @@ -4131,6 +4157,17 @@ int dsi_panel_drv_init(struct dsi_panel *panel, goto error_gpio_release; } + rc = dsi_panel_sysfs_init(panel); + if (rc) + goto exit; + +#ifdef CONFIG_EXPOSURE_ADJUSTMENT + rc = sysfs_create_group(&(panel->parent->kobj), &mdss_fb_attr_group); + if (rc) + pr_err("sysfs group creation failed, rc=%d\n", rc); + set_panel = panel; +#endif + goto exit; error_gpio_release: From 239f4edd3bfb249d36ed9dfb9ee5d24bc89796d0 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Thu, 10 Feb 2022 16:37:05 +0200 Subject: [PATCH 132/226] display: dsi_panel: expose attribute to notify of fod changes Change-Id: I6bdb767567c09e1a4cbd3b2d626e1173baf9089f Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 29 +++++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 3 +++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 7f596326bee5..c419e61738a3 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -1270,6 +1270,18 @@ static int dsi_panel_pwm_register(struct dsi_panel *panel) return 0; } +bool dsi_panel_get_fod_ui(struct dsi_panel *panel) +{ + return panel->fod_ui; +} + +void dsi_panel_set_fod_ui(struct dsi_panel *panel, bool status) +{ + panel->fod_ui = status; + + sysfs_notify(&panel->parent->kobj, NULL, "fod_ui"); +} + static int dsi_panel_bl_register(struct dsi_panel *panel) { int rc = 0; @@ -4070,7 +4082,24 @@ struct dsi_panel *dsi_panel_get(struct device *parent, return ERR_PTR(rc); } +static ssize_t sysfs_fod_ui_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dsi_display *display = dev_get_drvdata(dev); + struct dsi_panel *panel = display->panel; + bool status; + + mutex_lock(&panel->panel_lock); + status = panel->fod_ui; + mutex_unlock(&panel->panel_lock); + + return snprintf(buf, PAGE_SIZE, "%u\n", status); +} + +static DEVICE_ATTR(fod_ui, 0444, sysfs_fod_ui_read, NULL); + static struct attribute *panel_attrs[] = { + &dev_attr_fod_ui.attr, NULL, }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index e5379c6b0e48..dd27c08aba28 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -273,6 +273,7 @@ struct dsi_panel { unsigned int fod_dim_lut_len; u8 fod_dim_alpha; bool fod_hbm_enabled; + bool fod_ui; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -416,5 +417,7 @@ u8 dsi_panel_get_fod_dim_alpha(struct dsi_panel *panel); int dsi_panel_apply_hbm_mode(struct dsi_panel *panel); int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status); +bool dsi_panel_get_fod_ui(struct dsi_panel *panel); +void dsi_panel_set_fod_ui(struct dsi_panel *panel, bool status); #endif /* _DSI_PANEL_H_ */ From acf23581abf00ba011e5b421e52681804d0ecfd2 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 13 May 2022 09:33:09 +0300 Subject: [PATCH 133/226] display: expose forcing FOD UI for debugging Change-Id: I1f1b5344c9f98b541dc5c99e5d6f9c5560d8340c Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 29 +++++++++++++++++++++ drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 2 ++ drivers/gpu/drm/msm/sde/sde_crtc.c | 6 ++++- 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index c419e61738a3..697db6c49c89 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -1282,6 +1282,11 @@ void dsi_panel_set_fod_ui(struct dsi_panel *panel, bool status) sysfs_notify(&panel->parent->kobj, NULL, "fod_ui"); } +bool dsi_panel_get_force_fod_ui(struct dsi_panel *panel) +{ + return panel->force_fod_ui; +} + static int dsi_panel_bl_register(struct dsi_panel *panel) { int rc = 0; @@ -4096,10 +4101,34 @@ static ssize_t sysfs_fod_ui_read(struct device *dev, return snprintf(buf, PAGE_SIZE, "%u\n", status); } +static ssize_t sysfs_force_fod_ui_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dsi_display *display = dev_get_drvdata(dev); + struct dsi_panel *panel = display->panel; + + return snprintf(buf, PAGE_SIZE, "%u\n", panel->force_fod_ui); +} + +ssize_t sysfs_force_fod_ui_write(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct dsi_display *display = dev_get_drvdata(dev); + struct dsi_panel *panel = display->panel; + + kstrtobool(buf, &panel->force_fod_ui); + + return count; +} + static DEVICE_ATTR(fod_ui, 0444, sysfs_fod_ui_read, NULL); +static DEVICE_ATTR(force_fod_ui, 0644, + sysfs_force_fod_ui_read, + sysfs_force_fod_ui_write); static struct attribute *panel_attrs[] = { &dev_attr_fod_ui.attr, + &dev_attr_force_fod_ui.attr, NULL, }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index dd27c08aba28..b831f230767b 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -274,6 +274,7 @@ struct dsi_panel { u8 fod_dim_alpha; bool fod_hbm_enabled; bool fod_ui; + bool force_fod_ui; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) @@ -419,5 +420,6 @@ int dsi_panel_apply_hbm_mode(struct dsi_panel *panel); int dsi_panel_set_fod_hbm(struct dsi_panel *panel, bool status); bool dsi_panel_get_fod_ui(struct dsi_panel *panel); void dsi_panel_set_fod_ui(struct dsi_panel *panel, bool status); +bool dsi_panel_get_force_fod_ui(struct dsi_panel *panel); #endif /* _DSI_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index 0ae0d9eef458..516452fc1d62 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -5305,7 +5305,9 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, static void sde_crtc_fod_atomic_check(struct sde_crtc_state *cstate, struct plane_state *pstates, int cnt) { + struct dsi_display *display = get_main_display(); unsigned int fod_plane_idx, plane_idx; + bool force_fod_ui; u8 alpha = 0; for (plane_idx = 0; plane_idx < cnt; plane_idx++) @@ -5314,7 +5316,9 @@ static void sde_crtc_fod_atomic_check(struct sde_crtc_state *cstate, fod_plane_idx = plane_idx; - if (fod_plane_idx != cnt) { + force_fod_ui = dsi_panel_get_force_fod_ui(display->panel); + + if (fod_plane_idx != cnt || force_fod_ui) { struct dsi_display *display = get_main_display(); alpha = dsi_panel_get_fod_dim_alpha(display->panel); } From 1ba001dc88ff89eb223aba1ab1040321d7fe4ce2 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 1 Jun 2022 11:35:11 +0300 Subject: [PATCH 134/226] display: expose dim alpha for debugging Change-Id: I474cf172c14f7a49225ff9a386bffde8f21916cc Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 40 ++++++++++++++++++++- drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 1 + 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index 697db6c49c89..af198fdcd4c2 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -1213,7 +1213,9 @@ int dsi_panel_set_backlight(struct dsi_panel *panel, u32 bl_lvl) } bl->real_bl_level = bl_lvl; - panel->fod_dim_alpha = dsi_panel_calc_fod_dim_alpha(panel, bl_lvl); + + if (!panel->force_fod_dim_alpha) + panel->fod_dim_alpha = dsi_panel_calc_fod_dim_alpha(panel, bl_lvl); return rc; } @@ -4121,13 +4123,49 @@ ssize_t sysfs_force_fod_ui_write(struct device *dev, return count; } +static ssize_t sysfs_fod_dim_alpha_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dsi_display *display = dev_get_drvdata(dev); + struct dsi_panel *panel = display->panel; + + return snprintf(buf, PAGE_SIZE, "%u\n", panel->fod_dim_alpha); +} + +ssize_t sysfs_fod_dim_alpha_write(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct dsi_display *display = dev_get_drvdata(dev); + struct dsi_panel *panel = display->panel; + int value; + + sscanf(buf, "%d", &value); + + if (value > 255) + return -EINVAL; + + panel->force_fod_dim_alpha = value >= 0; + + if (!panel->force_fod_dim_alpha) + goto exit; + + panel->fod_dim_alpha = value; + +exit: + return count; +} + static DEVICE_ATTR(fod_ui, 0444, sysfs_fod_ui_read, NULL); static DEVICE_ATTR(force_fod_ui, 0644, sysfs_force_fod_ui_read, sysfs_force_fod_ui_write); +static DEVICE_ATTR(fod_dim_alpha, 0644, + sysfs_fod_dim_alpha_read, + sysfs_fod_dim_alpha_write); static struct attribute *panel_attrs[] = { &dev_attr_fod_ui.attr, + &dev_attr_fod_dim_alpha.attr, &dev_attr_force_fod_ui.attr, NULL, }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h index b831f230767b..063619f98658 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.h @@ -275,6 +275,7 @@ struct dsi_panel { bool fod_hbm_enabled; bool fod_ui; bool force_fod_ui; + bool force_fod_dim_alpha; }; static inline bool dsi_panel_ulps_feature_enabled(struct dsi_panel *panel) From 12b717f30188ad8101ff991b55ea19471c378824 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Thu, 10 Feb 2022 16:37:55 +0200 Subject: [PATCH 135/226] display: sde_connector: update FOD HBM on FOD status change Change-Id: Ifd50bfe7996c70d03c9bf41b72da1893a90137c0 Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_connector.c | 44 +++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index f35a7a71ae7a..e9ea6e434b6a 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -586,6 +586,47 @@ static int _sde_connector_update_dirty_properties( return 0; } +static bool sde_connector_is_fod_enabled(struct sde_connector *c_conn) +{ + struct drm_connector *connector = &c_conn->base; + + if (!connector->state || !connector->state->crtc) + return false; + + return sde_crtc_is_fod_enabled(connector->state->crtc->state); +} + +struct dsi_panel *sde_connector_panel(struct sde_connector *c_conn) +{ + struct dsi_display *display = (struct dsi_display *)c_conn->display; + + return display ? display->panel : NULL; +} + +static void sde_connector_pre_update_fod_hbm(struct sde_connector *c_conn) +{ + struct dsi_panel *panel; + bool status; + + panel = sde_connector_panel(c_conn); + if (!panel) + return; + + status = sde_connector_is_fod_enabled(c_conn); + if (status == dsi_panel_get_fod_ui(panel)) + return; + + if (status) + sde_encoder_wait_for_event(c_conn->encoder, MSM_ENC_VBLANK); + + dsi_panel_set_fod_hbm(panel, status); + + if (!status) + sde_encoder_wait_for_event(c_conn->encoder, MSM_ENC_VBLANK); + + dsi_panel_set_fod_ui(panel, status); +} + int sde_connector_pre_kickoff(struct drm_connector *connector) { struct sde_connector *c_conn; @@ -619,6 +660,9 @@ int sde_connector_pre_kickoff(struct drm_connector *connector) SDE_EVT32_VERBOSE(connector->base.id); + if (c_conn->connector_type == DRM_MODE_CONNECTOR_DSI) + sde_connector_pre_update_fod_hbm(c_conn); + rc = c_conn->ops.pre_kickoff(connector, c_conn->display, ¶ms); end: From 9a6619e370ddb4d699eaa4964630d1c2eb0e2eac Mon Sep 17 00:00:00 2001 From: John Galt Date: Tue, 20 Dec 2022 09:52:16 -0500 Subject: [PATCH 136/226] sde_plane: correctly set PLANE_PROP_FOD to dirty rects [pwnrazr:we use PLANE_PROP_FOD in raphael] Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c index 743552ab169f..53f1abf39352 100644 --- a/drivers/gpu/drm/msm/sde/sde_plane.c +++ b/drivers/gpu/drm/msm/sde/sde_plane.c @@ -4149,6 +4149,7 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, case PLANE_PROP_V_DECIMATE: case PLANE_PROP_SRC_CONFIG: case PLANE_PROP_ZPOS: + case PLANE_PROP_FOD: case PLANE_PROP_EXCL_RECT_V1: pstate->dirty |= SDE_PLANE_DIRTY_RECTS; break; @@ -4166,7 +4167,6 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, case PLANE_PROP_ALPHA: case PLANE_PROP_INPUT_FENCE: case PLANE_PROP_BLEND_OP: - case PLANE_PROP_FOD: /* no special action required */ break; case PLANE_PROP_FB_TRANSLATION_MODE: From f4c60d14b1b747b62ebd6b3da8db82169c8d916e Mon Sep 17 00:00:00 2001 From: John Galt Date: Tue, 3 Jan 2023 15:58:51 -0500 Subject: [PATCH 137/226] sde_connector: fix off by one frame on press hbm for dim Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/sde/sde_connector.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index e9ea6e434b6a..c37d994dd54d 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -616,14 +616,8 @@ static void sde_connector_pre_update_fod_hbm(struct sde_connector *c_conn) if (status == dsi_panel_get_fod_ui(panel)) return; - if (status) - sde_encoder_wait_for_event(c_conn->encoder, MSM_ENC_VBLANK); - dsi_panel_set_fod_hbm(panel, status); - if (!status) - sde_encoder_wait_for_event(c_conn->encoder, MSM_ENC_VBLANK); - dsi_panel_set_fod_ui(panel, status); } From 2575efb7c205d3c07ebaf412bc877b002df53d02 Mon Sep 17 00:00:00 2001 From: pwnrazr <1644943+pwnrazr@users.noreply.github.com> Date: Thu, 5 Jan 2023 17:50:04 +0800 Subject: [PATCH 138/226] display: dsi_panel: include dsi_display Signed-off-by: onettboots Signed-off-by: firebird11 --- drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c index af198fdcd4c2..9b163a1a51d6 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -20,6 +20,7 @@ #include #include