A single-channel biopotential recorder designed for educational demonstration. The analog front end is built entirely from discrete components, and recorded data can be exported in CSV and BDF formats.
- Analog front end built from discrete components — no monolithic ASIC, making it well-suited for teaching and demonstration
- Gain of 61.78 dB (×1228)
- Equivalent input noise density of 18.8 nV/√Hz; 266 nV RMS over a 200 Hz bandwidth
- Full-scale input of 2 mVpp
- Bandwidth 0.05–200 Hz; high-pass cutoff switchable between 0.05 Hz and 1.5 Hz; multiple digital filter modes available
- Isolated power supply for common-mode interference rejection
- FPGA-based FIR/IIR filtering and Pan-Tompkins heart rate detection
├── hardware/ # EasyEDA Pro projects, schematics, Gerber files
│ ├── afe/ # Analog front-end module
│ ├── power-iso/ # ±5 V isolated power supply module
│ └── mainboard/ # Main board
├── firmware/ # FPGA (Gowin IDE) and MCU (ESP-IDF) projects, with flashing guide
└── examples/ # Sample CSV/BDF files
Main components: main board, AFE module, isolated power supply module (3 PCBs total); display module; Tang Nano 9K development board .
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Go to the
hardware/directory, order PCBs for each of the three subdirectories, and purchase and solder components according to the EasyEDA Pro projects. -
Go to the
firmware/directory and flash the FPGA and MCU firmware following the flashing guide. -
Fabricate electrodes: wet electrodes are recommended for better contact impedance. See Section 3.3.3 — Practical Electrodes for details.
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Display module: ST7789V2, 2-inch, 240×320. Verify the pin assignment before purchasing.
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Assembly: a brass standoff can be soldered at one corner of the display for support; four brass standoffs soldered into the main board mounting holes serve as feet.
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Once assembly is complete, refer to 07 — User Guide.
ECG Measurement Fundamentals / DIY Single-Channel Biopotential Recorder
- 01 — Background
- 02 — Goals and Motivation
- 03 — ECG Measurement Principles
- 04 — System Architecture
- 05 — Hardware Design
- 06 — FPGA Implementation
- 07 — User Guide
- 08 — Conclusion and Future Work
This project is licensed under a multi-license model to cover hardware, software, and documentation.
All hardware design files are released under the CERN-OHL-P v2 license.
Copyright (c) 2026 Zihang Shi (ChirpyJay)
This source describes Open Hardware and is licensed under the CERN-OHL-P v2. You may redistribute and modify this documentation and make products using it under the terms of the CERN-OHL-P v2 (https://cern.ch/cern-ohl).
All software and firmware code are released under the MIT License.
Copyright (c) 2026 Zihang Shi (ChirpyJay)
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
All documentation and Wiki content are released under Creative Commons Attribution 4.0 International (CC BY 4.0).
You are free to Share and Adapt the material for any purpose, even commercially, provided that you give appropriate attribution (give credit, provide a link to the license, and indicate if changes were made).
This project is intended for educational and demonstration purposes only. It does not constitute medical advice and must not be used for clinical diagnosis or any medical purpose.
This device has not been certified as a medical device. The author accepts no liability for personal injury, property damage, or other safety incidents arising from reproducing, using, or modifying this project. Ensure you have the necessary electronics and safety knowledge before attempting to build this device.