FPGA_Autonomous_Testing/Controller.stx at main · ayseidman/FPGA_Autonomous_Testing · GitHub

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Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s

-->
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx92i/DTSD_LabWork2/Counter.vhd" in Library work.
Architecture behavioral of Entity counter is up to date.
Compiling vhdl file "C:/Xilinx92i/DTSD_LabWork2/Controller.vhd" in Library work.
Entity <controller> compiled.
Entity <controller> (Architecture <behavioral>) compiled.
CPU : 0.05 / 0.13 s | Elapsed : 0.00 / 0.00 s

-->

Total memory usage is 175416 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)