From 8fdc7d1a32818bbeb6b1c9d576dac24721aad5c9 Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Thu, 5 Nov 2026 17:49:14 +0000 Subject: [PATCH 1/3] dt-bindings: nvmem: apple,spmi-nvmem: Add the Chapel PMIC t6030.dtsi and t6031-die0.dtsi already use apple,chapel-pmic, and the M4 Max's main PMIC is a Chapel too. Signed-off-by: AxxzyWasTaken --- Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml index 2eecc48c9b061..1a1051584e8fa 100644 --- a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml @@ -20,6 +20,7 @@ properties: - enum: - apple,abbey-pmic - apple,baku-pmic + - apple,chapel-pmic - apple,maverick-pmic - apple,sera-pmic - apple,stowe-pmic From d2236d956cb327445fa959431d1bfb854f986545 Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Thu, 5 Nov 2026 17:49:18 +0000 Subject: [PATCH 2/3] arm64: dts: apple: t6041: The main PMIC is a Chapel at 0xb The tree inherits the J616s's Abbey at 0xe on nub-spmi0, which doesn't exist here: the J616C ADT has a Chapel at 0xb (spmi-chapelL1-b), so the SMC RTC offset, boot stage and shutdown cells point at nothing. The cells and the RTC alarm registers are at the Abbey offsets (ADT info-rtc_alarm_*). Describe the Chapel with those cells and its RTC, and keep nub-spmi0's interrupt controller, which the RTC's alarm uses. Signed-off-by: AxxzyWasTaken --- arch/arm64/boot/dts/apple/t6041.dtsi | 53 +++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t6041.dtsi b/arch/arm64/boot/dts/apple/t6041.dtsi index 62c2f817f3096..6e97eadb2ee43 100644 --- a/arch/arm64/boot/dts/apple/t6041.dtsi +++ b/arch/arm64/boot/dts/apple/t6041.dtsi @@ -207,11 +207,56 @@ /delete-property/ power-domain-names; }; +/* + * The main PMIC is a Chapel at 0xb (ADT nub-spmi0 spmi-chapelL1-b), not the + * J616s's Abbey at 0xe. Its nvmem cells and RTC alarm registers are at the + * Abbey offsets (ADT info-rtc_alarm_*). + */ &nub_spmi0 { - /delete-property/ interrupt-controller; - /delete-property/ #interrupt-cells; - /delete-property/ interrupt-parent; - /delete-property/ interrupts; + /delete-node/ pmic@e; + + pmic@b { + compatible = "apple,chapel-pmic", "apple,spmi-nvmem"; + reg = <0xb SPMI_USID>; + + pmu_rtc: rtc { + compatible = "apple,t6041-pmu-rtc"; + interrupt-parent = <&nub_spmi0>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + wakeup-source; + }; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + rtc_offset: rtc-offset@2100 { + reg = <0x2100 0x6>; + }; + + boot_stage: boot-stage@f801 { + reg = <0xf801 0x1>; + }; + + boot_error_count: boot-error-count@f802,0 { + reg = <0xf802 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@f802,4 { + reg = <0xf802 0x1>; + bits = <4 4>; + }; + + shutdown_flag: shutdown-flag@f80f,3 { + reg = <0xf80f 0x1>; + bits = <3 1>; + }; + }; + }; }; &usb_drd0_dart_0 { From f0dccd8cac482e95b8d732ba89e56f672346ecfe Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Thu, 5 Nov 2026 17:49:21 +0000 Subject: [PATCH 3/3] arm64: dts: apple: t6041-j616c: Enable the cache on 24 planes T6041 has up to eight AMCCs with four cache planes each, six on the binned part (ADT amcc-enable-mask 0x3f). List the 24 planes every T6041 has, which the MCC driver takes since the plane limit went to 32, and enable it on the J616C, where it was left disabled. Signed-off-by: AxxzyWasTaken --- arch/arm64/boot/dts/apple/t6041-j616c.dts | 4 +++ arch/arm64/boot/dts/apple/t6041.dtsi | 31 +++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6041-j616c.dts b/arch/arm64/boot/dts/apple/t6041-j616c.dts index 96cb5281c8b59..423e8b28c7bfe 100644 --- a/arch/arm64/boot/dts/apple/t6041-j616c.dts +++ b/arch/arm64/boot/dts/apple/t6041-j616c.dts @@ -158,6 +158,10 @@ status = "okay"; }; +&mcc { + status = "okay"; +}; + &smc_hwmon { temperature-TCMz { apple,key-id = "TCMz"; diff --git a/arch/arm64/boot/dts/apple/t6041.dtsi b/arch/arm64/boot/dts/apple/t6041.dtsi index 6e97eadb2ee43..094a7c4bd8fa6 100644 --- a/arch/arm64/boot/dts/apple/t6041.dtsi +++ b/arch/arm64/boot/dts/apple/t6041.dtsi @@ -633,3 +633,34 @@ apple,always-on; apple,no-auto-pm; }; + +/* + * Four cache planes per AMCC, eight AMCCs on the full part and six on the + * binned one (ADT amcc-enable-mask 0x3f). List the six every T6041 has. + */ +&mcc { + reg = <0x2 0x20000000 0x0 0x4000>, + <0x2 0x20040000 0x0 0x4000>, + <0x2 0x20080000 0x0 0x4000>, + <0x2 0x200c0000 0x0 0x4000>, + <0x2 0x22000000 0x0 0x4000>, + <0x2 0x22040000 0x0 0x4000>, + <0x2 0x22080000 0x0 0x4000>, + <0x2 0x220c0000 0x0 0x4000>, + <0x2 0x24000000 0x0 0x4000>, + <0x2 0x24040000 0x0 0x4000>, + <0x2 0x24080000 0x0 0x4000>, + <0x2 0x240c0000 0x0 0x4000>, + <0x2 0x26000000 0x0 0x4000>, + <0x2 0x26040000 0x0 0x4000>, + <0x2 0x26080000 0x0 0x4000>, + <0x2 0x260c0000 0x0 0x4000>, + <0x2 0x28000000 0x0 0x4000>, + <0x2 0x28040000 0x0 0x4000>, + <0x2 0x28080000 0x0 0x4000>, + <0x2 0x280c0000 0x0 0x4000>, + <0x2 0x2a000000 0x0 0x4000>, + <0x2 0x2a040000 0x0 0x4000>, + <0x2 0x2a080000 0x0 0x4000>, + <0x2 0x2a0c0000 0x0 0x4000>; +};