From 71e6a1892361d0f802315999622ca6427570a0ec Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Tue, 3 Nov 2026 17:47:07 +0000 Subject: [PATCH 1/6] dt-bindings: nvmem: apple,spmi-nvmem: Add apple,chapel-pmic The Chapel PMIC is on the T6030 and T6031 (M3 Pro/Max) SPMI buses, whose trees already use this compatible, and on the T6041 (M4 Max). Signed-off-by: AxxzyWasTaken --- Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml index 2eecc48c9b061..1a1051584e8fa 100644 --- a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml @@ -20,6 +20,7 @@ properties: - enum: - apple,abbey-pmic - apple,baku-pmic + - apple,chapel-pmic - apple,maverick-pmic - apple,sera-pmic - apple,stowe-pmic From c54dcf8e53246d9258c32a2bb9744a75bd13f9a8 Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Tue, 3 Nov 2026 17:47:11 +0000 Subject: [PATCH 2/6] arm64: dts: apple: Add the T6041 (M4 Max) SoC T6041 has the blocks t6040.dtsi describes at the same addresses and interrupts (checked against a J616C ADT). Three things differ: - Two clusters of six P cores instead of five. The boot loader matches the DT's CPU nodes to the ADT's by MPIDR and drops the ones a binned part leaves out (the 14-core J616C has exactly the J616s's cores), so t6040.dtsi adds the sixth core of each cluster when t6041.dtsi asks for them. - The main PMIC is a Chapel at SPMI address 0xb (ADT nub-spmi0 spmi-chapelL1-b), not an Abbey at 0xe. Its nvmem cells and RTC alarm registers (ADT info-rtc_alarm_*) sit at the Abbey offsets. - Up to eight AMCCs with four cache planes each, six on the binned part (ADT amcc-enable-mask 0x3f): the MCC lists the 24 planes every T6041 has, which needs the mcc driver to take more than 16. t6040.dtb files do not change. Signed-off-by: AxxzyWasTaken --- arch/arm64/boot/dts/apple/t6040.dtsi | 32 ++++++++ arch/arm64/boot/dts/apple/t6041.dtsi | 117 +++++++++++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6041.dtsi diff --git a/arch/arm64/boot/dts/apple/t6040.dtsi b/arch/arm64/boot/dts/apple/t6040.dtsi index b84630694e100..d9c3afec4a0fa 100644 --- a/arch/arm64/boot/dts/apple/t6040.dtsi +++ b/arch/arm64/boot/dts/apple/t6040.dtsi @@ -205,6 +205,22 @@ #cooling-cells = <2>; }; +#ifdef T6041_SIX_CORE_P_CLUSTERS + /* T6041 (t6041.dtsi): the sixth core, in ADT order */ + cpu_p05: cpu@10105 { + compatible = "apple,brava-p"; + device_type = "cpu"; + reg = <0x0 0x10105>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_p0>; + operating-points-v2 = <&opp_p0>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + #cooling-cells = <2>; + }; +#endif + cpu_p10: cpu@10200 { compatible = "apple,brava-p"; device_type = "cpu"; @@ -269,6 +285,22 @@ performance-domains = <&cpufreq_p1>; #cooling-cells = <2>; }; + +#ifdef T6041_SIX_CORE_P_CLUSTERS + /* T6041 (t6041.dtsi): the sixth core, in ADT order */ + cpu_p15: cpu@10205 { + compatible = "apple,brava-p"; + device_type = "cpu"; + reg = <0x0 0x10205>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_p1>; + operating-points-v2 = <&opp_p1>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + #cooling-cells = <2>; + }; +#endif }; l2_cache_e: l2-cache-cluster0 { diff --git a/arch/arm64/boot/dts/apple/t6041.dtsi b/arch/arm64/boot/dts/apple/t6041.dtsi new file mode 100644 index 0000000000000..a54d12d155671 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6041.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6041 "M4 Max" SoC + * + * The blocks t6040.dtsi describes sit at the same addresses, with the same + * interrupts, on T6041 (checked against a J616C ADT). The CPUs differ: two + * clusters of six P cores instead of five. Binned parts leave cores out of + * the ADT (the 14-core part has no cpu9 and no cpu15); the boot loader + * matches the DT's CPU nodes to the ADT's in order and disables those it + * does not find, so t6040.dtsi adds the sixth core of each cluster in place. + * + * The main PMIC is a Chapel at SPMI address 0xb (ADT nub-spmi0 + * spmi-chapelL1-b), not T6040's Abbey at 0xe; its nvmem cells sit at the + * same offsets. + * + * Copyright The Asahi Linux Contributors + */ + +#define T6041_SIX_CORE_P_CLUSTERS +#include "t6040.dtsi" + +/ { + cpus { + cpu-map { + cluster1 { + core5 { + cpu = <&cpu_p05>; + }; + }; + + cluster2 { + core5 { + cpu = <&cpu_p15>; + }; + }; + }; + }; +}; + +&nub_spmi0 { + /delete-node/ pmic@e; + + pmic@b { + compatible = "apple,chapel-pmic", "apple,spmi-nvmem"; + reg = <0xb SPMI_USID>; + + /* ADT pmu,chapel info-rtc_alarm_*: the Abbey layout at 0x2000 */ + pmu_rtc: rtc { + compatible = "apple,t6041-pmu-rtc"; + interrupt-parent = <&nub_spmi0>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + wakeup-source; + }; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + rtc_offset: rtc-offset@2100 { + reg = <0x2100 0x6>; + }; + + boot_stage: boot-stage@f801 { + reg = <0xf801 0x1>; + }; + + boot_error_count: boot-error-count@f802,0 { + reg = <0xf802 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@f802,4 { + reg = <0xf802 0x1>; + bits = <4 4>; + }; + + shutdown_flag: shutdown-flag@f80f,3 { + reg = <0xf80f 0x1>; + bits = <3 1>; + }; + }; + }; +}; + +/* + * Four cache planes per AMCC, eight AMCCs on the full part and six on the + * binned one (ADT amcc-enable-mask 0x3f). List the six every T6041 has. + */ +&mcc { + reg = <0x2 0x20000000 0x0 0x4000>, + <0x2 0x20040000 0x0 0x4000>, + <0x2 0x20080000 0x0 0x4000>, + <0x2 0x200c0000 0x0 0x4000>, + <0x2 0x22000000 0x0 0x4000>, + <0x2 0x22040000 0x0 0x4000>, + <0x2 0x22080000 0x0 0x4000>, + <0x2 0x220c0000 0x0 0x4000>, + <0x2 0x24000000 0x0 0x4000>, + <0x2 0x24040000 0x0 0x4000>, + <0x2 0x24080000 0x0 0x4000>, + <0x2 0x240c0000 0x0 0x4000>, + <0x2 0x26000000 0x0 0x4000>, + <0x2 0x26040000 0x0 0x4000>, + <0x2 0x26080000 0x0 0x4000>, + <0x2 0x260c0000 0x0 0x4000>, + <0x2 0x28000000 0x0 0x4000>, + <0x2 0x28040000 0x0 0x4000>, + <0x2 0x28080000 0x0 0x4000>, + <0x2 0x280c0000 0x0 0x4000>, + <0x2 0x2a000000 0x0 0x4000>, + <0x2 0x2a040000 0x0 0x4000>, + <0x2 0x2a080000 0x0 0x4000>, + <0x2 0x2a0c0000 0x0 0x4000>; +}; From a52c873416c886ee1f351232cf128551d1831bf5 Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Tue, 3 Nov 2026 17:48:43 +0000 Subject: [PATCH 3/6] arm64: dts: apple: Add the MacBook Pro 16-inch M4 Max (J616C) J616C is the J616s chassis with the T6041. Checked against a J616C ADT (macOS 26.6.2, iBoot mBoot-18000.161.10): every power domain of t6040-pmgr.dtsi, the display block, AVD, PMP, AOP, MTP, SMC, NVMe and USB sit at the same addresses, with the same interrupts and DART streams. What differs from J616s: - the trackpad firmware is tpmtfw-j616c.bin, and the factory data mesacal-j616c.bin and msrk-j616c.bin; - nub-spmi1 holds a Chapel at 0xb and a Spitfire at 0x9, nub-spmi2 Portiers at 0xa and 0xb, not Abbeys at 0xe; nothing on nub-spmi2 has a binding yet, so that bus is left out; - five per-unit USB3 PHY values (auspll, cio4pll, aus40cmn-shm), from this machine's ADT; every other tunable matches J616s; - iBoot moves the ISP firmware from boot to boot, so the ISP stays off until the boot loader fills in its placement; - the GPU (ADT gpu,t6041) is not described yet and stays off. Signed-off-by: AxxzyWasTaken --- arch/arm64/boot/dts/apple/Makefile | 1 + arch/arm64/boot/dts/apple/t6041-j616c.dts | 135 ++++++++++++++++++++++ 2 files changed, 136 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6041-j616c.dts diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index c7487bcac3d35..52b15f4bdb8cb 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_APPLE) += t6034-j516m.dtb dtb-$(CONFIG_ARCH_APPLE) += t6040-j614s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6040-j616s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6040-j616s-tether.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6041-j616c.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb diff --git a/arch/arm64/boot/dts/apple/t6041-j616c.dts b/arch/arm64/boot/dts/apple/t6041-j616c.dts new file mode 100644 index 0000000000000..55380b18b15dc --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6041-j616c.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M4 Max) + * + * target-type: J616C + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6041.dtsi" +#include "t604x-j614-j616.dtsi" + +/ { + compatible = "apple,j616c", "apple,t6041", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M4 Max)"; +}; + +/* ADT /arm-io/wlan module-instance */ +&wifi0 { + brcm,board-type = "apple,hostomel"; +}; + +&bluetooth0 { + brcm,board-type = "apple,hostomel"; +}; + +&panel { + compatible = "apple,panel-j616", "apple,panel-mini-led", "apple,panel"; + width-mm = <345>; + height-mm = <223>; + adj-height-mm = <216>; +}; + +&aop_audio { + apple,chassis-name = "J616"; +}; + +&sound { + compatible = "apple,j616-macaudio", "apple,macaudio"; + model = "MacBook Pro J616"; +}; + +&sound_jack { + compatible = "apple,j616-macaudio-jack", "apple,macaudio"; + model = "MacBook Pro J616 Jack"; +}; + +&mtp_mt { + firmware-name = "apple/tpmtfw-j616c.bin"; +}; + +/* + * Per-device factory data from this Mac's own iBoot system container: the + * sealed calibration and the sealed root key. + */ +&mesa { + firmware-name = "apple/mesacal-j616c.bin", "apple/msrk-j616c.bin"; +}; + +/* + * The other NUB SPMI buses hold a Chapel at 0xb and a Spitfire at 0x9 + * (nub-spmi1), and Portiers at 0xa and 0xb (nub-spmi2), not the J616s's + * Abbeys at 0xe. + */ +&nub_spmi1 { + /delete-node/ pmic@e; + + pmic@b { + compatible = "apple,chapel-pmic", "apple,spmi-nvmem"; + reg = <0xb SPMI_USID>; + }; +}; + +/* Nothing on nub-spmi2 has a binding yet. */ +/delete-node/ &nub_spmi2; + +/* + * iBoot moves the ISP firmware from boot to boot on this machine, so the + * J616s placement does not hold. Keep the camera off until the boot loader + * fills it in. + */ +&isp { + status = "disabled"; +}; + +/* The GPU (ADT gpu,t6041) is not described yet. */ +&gpu { + status = "disabled"; +}; + +&gfx_mbox { + status = "disabled"; +}; + +/* + * The per-unit USB3 PHY values of this machine's ADT (auspll, cio4pll, + * aus40cmn-shm); every other tunable is the J616s's. + */ + +&atcphy0 { + apple,tunable-auspll = + <0x3224 0x00000c00 0x00000800>, + <0x3230 0x0000001f 0x0000000f>, + <0x3240 0x07d8007f 0x04000049>, + <0x32b0 0x0b800000 0x01800000>, + <0x32e8 0x00060001 0x00040001>, + <0x3338 0x0f800000 0x07800000>; + + apple,tunable-cio4pll = + <0x3a30 0x0000001f 0x0000000f>, + <0x3a4c 0x0000fe7f 0x00005421>, + <0x3ab0 0x00700000 0x00300000>, + <0x3ae8 0x00060000 0x00020000>; +}; + +&atcphy1 { + apple,tunable-cio4pll = + <0x3a30 0x0000001f 0x0000000f>, + <0x3a4c 0x0000fe7f 0x00005421>, + <0x3ab0 0x00700000 0x00300000>, + <0x3ae8 0x00060000 0x00020000>; +}; + +&atcphy2 { + apple,tunable-aus40cmn-shm = + <0xa04 0x0000007c 0x00000050>; + + apple,tunable-cio4pll = + <0x3a30 0x0000001f 0x0000000f>, + <0x3a4c 0x0000fe7f 0x00005420>, + <0x3ab0 0x00700000 0x00300000>, + <0x3ae8 0x00060000 0x00020000>; +}; From bd73f99d289a29dc28c270cc69c2284d9edde96f Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Tue, 3 Nov 2026 17:44:12 +0000 Subject: [PATCH 4/6] arm64: dts: apple: t6041-j616c: describe the GPU J616C uses the shared T604x GPU description with the T6041 compatible. T6041 has four GPU clusters, so the operating points carry one voltage cell per cluster (ADT /arm-io/sgx perf-states to perf-states3). The boot loader fills these, the CS and AFR tables and the six memory regions; the GPU stays unusable without that handoff. --- arch/arm64/boot/dts/apple/t6041-j616c.dts | 59 +++++++++++++++++++++-- 1 file changed, 55 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t6041-j616c.dts b/arch/arm64/boot/dts/apple/t6041-j616c.dts index 55380b18b15dc..fd3a1f80a5337 100644 --- a/arch/arm64/boot/dts/apple/t6041-j616c.dts +++ b/arch/arm64/boot/dts/apple/t6041-j616c.dts @@ -85,13 +85,64 @@ status = "disabled"; }; -/* The GPU (ADT gpu,t6041) is not described yet. */ +/* + * The GPU (ADT gpu,t6041) has four clusters: one opp-microvolt cell per + * cluster (ADT /arm-io/sgx perf-states to perf-states3). The loader fills + * these placeholders, the CS and AFR tables and the memory regions. + */ &gpu { - status = "disabled"; + compatible = "apple,agx-t6041"; }; -&gfx_mbox { - status = "disabled"; +&gpu_opp { + opp00 { + opp-microvolt = <0 0 0 0>; + }; + opp01 { + opp-microvolt = <0 0 0 0>; + }; + opp02 { + opp-microvolt = <0 0 0 0>; + }; + opp03 { + opp-microvolt = <0 0 0 0>; + }; + opp04 { + opp-microvolt = <0 0 0 0>; + }; + opp05 { + opp-microvolt = <0 0 0 0>; + }; + opp06 { + opp-microvolt = <0 0 0 0>; + }; + opp07 { + opp-microvolt = <0 0 0 0>; + }; + opp08 { + opp-microvolt = <0 0 0 0>; + }; + opp09 { + opp-microvolt = <0 0 0 0>; + }; + opp10 { + opp-microvolt = <0 0 0 0>; + }; + opp11 { + opp-microvolt = <0 0 0 0>; + }; + opp12 { + opp-microvolt = <0 0 0 0>; + }; + opp13 { + opp-microvolt = <0 0 0 0>; + }; + opp14 { + opp-microvolt = <0 0 0 0>; + }; + opp15 { + opp-microvolt = <0 0 0 0>; + }; }; /* From 1ca2e4e12bcdfd437029daf093939d308f3ed228 Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Wed, 4 Nov 2026 18:10:49 +0000 Subject: [PATCH 5/6] arm64: dts: apple: t6041-j616c: Fix the MTP and AOP bring-up Booting the J616C on 7.3 left the keyboard, trackpad and audio dead: RTKit timed out on the MTP and AOP, and dockchannel-hid failed its AFE preflight. - aura only programs a co-processor's DAPF if the device tree has its alias. The shared J614s/J616s file has only pmp, so add aop and mtp. - The J616C has no gp1c key. Its AFE and STM resets are lines 25 and 26 of the SMC's low GPIO block, so describe that block, drop apple,afe-smc and use power method 2. - Use the plain dockchannel-hid compatible: this Mac's MTP firmware runs without the J616s's ring transport on our daily tree. Signed-off-by: AxxzyWasTaken --- arch/arm64/boot/dts/apple/t6041-j616c.dts | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6041-j616c.dts b/arch/arm64/boot/dts/apple/t6041-j616c.dts index 55380b18b15dc..b66e5763ed7ce 100644 --- a/arch/arm64/boot/dts/apple/t6041-j616c.dts +++ b/arch/arm64/boot/dts/apple/t6041-j616c.dts @@ -15,6 +15,20 @@ / { compatible = "apple,j616c", "apple,t6041", "apple,arm-platform"; model = "Apple MacBook Pro (16-inch, M4 Max)"; + + /* aura opens a co-processor's DAPF only if it finds its alias here. */ + aliases { + aop = &aop; + mtp = &mtp; + }; +}; + +&smc { + smc_gpio_low: gpio@67700000 { + compatible = "apple,smc-low-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; }; /* ADT /arm-io/wlan module-instance */ @@ -47,8 +61,20 @@ model = "MacBook Pro J616 Jack"; }; +/* + * The AFE and STM resets are SMC GPIOs here, not the J616s's gp1c sequence, and + * the MTP works without the J616s's ring transport. + */ +&mtp_hid { + /delete-property/ apple,afe-smc; + compatible = "apple,dockchannel-hid"; + apple,afe-reset-gpios = <&smc_gpio_low 0x19 GPIO_ACTIVE_LOW>; + apple,stm-reset-gpios = <&smc_gpio_low 0x1a GPIO_ACTIVE_LOW>; +}; + &mtp_mt { firmware-name = "apple/tpmtfw-j616c.bin"; + apple,power-method = <2>; }; /* From a53c4689fa41e4059568b3a6b41affb8e6a79b40 Mon Sep 17 00:00:00 2001 From: AxxzyWasTaken Date: Wed, 4 Nov 2026 19:29:12 +0000 Subject: [PATCH 6/6] arm64: dts: apple: t6041-j616c: Add the ISP alias aura only opens a co-processor's DAPF if the device tree has its alias, as with the AOP and MTP. The ISP stays disabled here for now, so this changes nothing yet, but the camera can't start without it once the ISP is enabled. Signed-off-by: AxxzyWasTaken --- arch/arm64/boot/dts/apple/t6041-j616c.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apple/t6041-j616c.dts b/arch/arm64/boot/dts/apple/t6041-j616c.dts index b66e5763ed7ce..11f6a49b2a03f 100644 --- a/arch/arm64/boot/dts/apple/t6041-j616c.dts +++ b/arch/arm64/boot/dts/apple/t6041-j616c.dts @@ -19,6 +19,7 @@ /* aura opens a co-processor's DAPF only if it finds its alias here. */ aliases { aop = &aop; + isp = &isp; mtp = &mtp; }; };