From 7d9d949f6bc63869a8caa69924ba88653836583d Mon Sep 17 00:00:00 2001 From: Jeff Queisser Date: Mon, 2 Nov 2026 16:24:38 -0800 Subject: [PATCH 1/5] dt-bindings: arm: apple: Add the Mac Studio (M5 Ultra, 2026) Add the J775D board and its T6050 (M5 Ultra) SoC. Signed-off-by: Jeff Queisser Co-Authored-By: Claude Opus 5.5 --- Documentation/devicetree/bindings/arm/apple.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index f0061e05acbef..f3b2dfbc3ef93 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -472,6 +472,12 @@ properties: - const: apple,t6041 - const: apple,arm-platform + - description: Apple M5 Ultra SoC based platforms + items: + - const: apple,j775d # Mac Studio (M5 Ultra, 2026) + - const: apple,t6050 + - const: apple,arm-platform + aurora,minimal-boot: type: boolean description: From 074dda5aa673e9f86be35a320ad920d89da18771 Mon Sep 17 00:00:00 2001 From: Jeff Queisser Date: Mon, 2 Nov 2026 16:24:39 -0800 Subject: [PATCH 2/5] dt-bindings: interrupt-controller: apple,aic2: Add T6050 T6050's AIC3 is the T8122 one with two dies, so it takes the T8122 fallback and, like T6031's, four interrupt cells (the second is the die). Signed-off-by: Jeff Queisser Co-Authored-By: Claude Opus 5.5 --- .../devicetree/bindings/interrupt-controller/apple,aic2.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml index f8ea935999a1e..d118f35b28ff4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -47,6 +47,7 @@ properties: - apple,t6030-aic3 - apple,t6031-aic3 - apple,t6041-aic3 + - apple,t6050-aic3 - apple,t8132-aic3 - apple,t8140-aic3 - apple,t8142-aic3 @@ -138,6 +139,7 @@ allOf: - apple,t6000-aic - apple,t6020-aic - apple,t6031-aic3 + - apple,t6050-aic3 then: properties: '#interrupt-cells': From fbd102cfb848221b592980816baf592455aee3a2 Mon Sep 17 00:00:00 2001 From: Jeff Queisser Date: Mon, 2 Nov 2026 16:24:39 -0800 Subject: [PATCH 3/5] dt-bindings: watchdog: apple,wdt: Add T6050 T6050's watchdog is compatible with T8103's. Signed-off-by: Jeff Queisser Co-Authored-By: Claude Opus 5.5 --- Documentation/devicetree/bindings/watchdog/apple,wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml index 00b0f2ec2bdb4..d09fb81bd506b 100644 --- a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -21,6 +21,7 @@ properties: - apple,t6030-wdt - apple,t6031-wdt - apple,t6041-wdt + - apple,t6050-wdt - apple,t8122-wdt - apple,t8132-wdt - apple,t8140-wdt From f8112509bd9a5e3f71e1e3b1a5bb873076b94b18 Mon Sep 17 00:00:00 2001 From: Jeff Queisser Date: Mon, 2 Nov 2026 16:24:40 -0800 Subject: [PATCH 4/5] dt-bindings: mailbox: apple,mailbox: Add T6050 ASC mailboxes T6050's coprocessors (ANS among them) use the ASC v4 mailbox. Signed-off-by: Jeff Queisser Co-Authored-By: Claude Opus 5.5 --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index a1dfa81a65014..7bb65a558d288 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -38,6 +38,7 @@ properties: - apple,t6020-asc-mailbox - apple,t6030-asc-mailbox - apple,t6041-asc-mailbox + - apple,t6050-asc-mailbox - const: apple,asc-mailbox-v4 - description: From 9e0ee6b2f23399cfa868110513bb0205fbf45106 Mon Sep 17 00:00:00 2001 From: Jeff Queisser Date: Mon, 2 Nov 2026 16:24:54 -0800 Subject: [PATCH 5/5] arm64: dts: apple: Add the T6050 SoC and the J775D Mac Studio (M5 Ultra) Add a first device tree for the M5 Ultra and its Mac Studio: enough to boot a distribution from the internal disk with the console on the USB debug link and networking on the onboard Ethernet. t6050.dtsi describes the 30 CPUs (spin-table, started by the boot loader), the AIC3 for both dies, the timer, the DockChannel UART, the watchdog (the restart handler), the storage SART, the ANS mailbox and the NVMe controller, the DARTs of PCIe ports 2 and 3, and one empty bus per die. t6050-j775d.dts adds the PCIe host with the two root ports the boot loader trained: port 2 with the RTL8127A 10 Gb Ethernet and port 3 with the ASM3142 xHCI behind the rear USB-A ports. It enables the console with apple,tx-never-wait: the debug link drains only while a host reads it, and the machine boots unattended with nothing attached there. Not yet described: the SMC (RTC, power off, sensors), the PMU, the GPU, the display and the Type-C ports. Until the SMC is described, the watchdog restarts the machine and the RTC is not available. Signed-off-by: Jeff Queisser Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/Makefile | 1 + arch/arm64/boot/dts/apple/t6050-j775d.dts | 140 ++++++++ arch/arm64/boot/dts/apple/t6050.dtsi | 413 ++++++++++++++++++++++ 3 files changed, 554 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6050-j775d.dts create mode 100644 arch/arm64/boot/dts/apple/t6050.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index 007e204fdbc56..7124023454575 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -95,6 +95,7 @@ dtb-$(CONFIG_ARCH_APPLE) += t6032-j575d.dtb dtb-$(CONFIG_ARCH_APPLE) += t6034-j514m.dtb dtb-$(CONFIG_ARCH_APPLE) += t6034-j516m.dtb dtb-$(CONFIG_ARCH_APPLE) += t6040-j616s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6050-j775d.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb diff --git a/arch/arm64/boot/dts/apple/t6050-j775d.dts b/arch/arm64/boot/dts/apple/t6050-j775d.dts new file mode 100644 index 0000000000000..67c2dad5e4884 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6050-j775d.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M5 Ultra, 2026) + * + * target-type: J775D + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6050.dtsi" + +/ { + compatible = "apple,j775d", "apple,t6050", "apple,arm-platform"; + model = "Apple Mac Studio (M5 Ultra, 2026)"; + chassis-type = "desktop"; + + aliases { + serial0 = &dockchannel; + /* the boot loader fills in the MAC address through this alias */ + ethernet0 = ðernet0; + }; + + /* + * No stdout-path: the boot loader passes the console on the command + * line when it wants one. + */ + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + + /* + * PCIe ports 2 (the onboard 10 Gb Ethernet) and 3 (the rear USB-A + * xHCI). The boot loader powers and trains both links and keeps power, + * clocks, the PHYs and PERST; Linux owns the routing, MSI and the + * DARTs. The boot loader disables a port, and its DART, whose link did + * not come up. + */ + pcie0: pcie@1cb0000000 { + compatible = "apple,t6050-pcie"; + device_type = "pci"; + reg = <0x1c 0xb0000000 0x0 0x10000000>, + <0x4 0x14000000 0x0 0x4000>, + <0x4 0x12028000 0x0 0x8000>, + <0x4 0x17018000 0x0 0x4000>, + <0x4 0x12024000 0x0 0x4000>, + <0x4 0x13028000 0x0 0x8000>, + <0x4 0x1701c000 0x0 0x4000>, + <0x4 0x13024000 0x0 0x4000>; + reg-names = "config", "rc", "port2", "phy2", "intr2axi2", + "port3", "phy3", "intr2axi3"; + nonposted-mmio; + interrupts = , + ; + interrupt-names = "port2", "port3"; + + /* One MSI domain for both ports: vectors 64-127 */ + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 0 1888 IRQ_TYPE_EDGE_RISING 64>; + apple,msi-vector-base = <64>; + + /* The boot loader numbers port 2's secondary bus 1 and port 3's 2 */ + iommu-map = <0x100 &dart_apcie2 1 1>, + <0x200 &dart_apcie3 1 1>; + iommu-map-mask = <0xffff>; + dma-coherent; + linux,pci-domain = <0>; + bus-range = <0 2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x0 0x80000000 0xb 0x80000000 0x0 0x40000000>, + <0x43000000 0xb 0xc0000000 0xb 0xc0000000 0x0 0x20000000>; + + port02: pci@2,0 { + device_type = "pci"; + reg = <0x1000 0 0 0 0>; + bus-range = <1 1>; + apple,link-trained-by-bootloader; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + + /* The RTL8127A keeps no MAC address of its own */ + ethernet0: ethernet@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + + port03: pci@3,0 { + device_type = "pci"; + reg = <0x1800 0 0 0 0>; + bus-range = <2 2>; + apple,link-trained-by-bootloader; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + }; + }; +}; + +/* + * The console is on the USB debug link, which drains only while a host reads + * it; the machine also boots with nothing attached there. + */ +&dockchannel { + apple,tx-never-wait; + status = "okay"; +}; + +&dart_apcie2 { + status = "okay"; +}; + +&dart_apcie3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t6050.dtsi b/arch/arm64/boot/dts/apple/t6050.dtsi new file mode 100644 index 0000000000000..5e59f595c2bb6 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6050.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6050 "M5 Ultra" SoC + * + * Two dies. Die 0's MMIO window is 0x2_00000000 and die 1's 0x42_00000000 + * (die stride 0x40_00000000); each has its own simple-bus, which the boot + * loader looks up by unit address. Unit addresses are CPU physical + * addresses. The boot loader starts the secondary CPUs and fills in their + * release addresses, the memory node and its own reservations. + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include + +/ { + compatible = "apple,t6050", "apple,arm-platform"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&aic>; + + /* The boot loader replaces reg with the usable RAM. */ + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0x0 0x0 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* The boot loader adds its own reservations. */ + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * Die d, cluster c, core n has MPIDR Aff2 4 for the two M-tier + * (apple,sawtooth) clusters and 1 for the P-tier (apple,everest) + * cluster, Aff1 0x10 * d + c and Aff0 n. Labels number the cores + * 18 * d + 6 * c + n. Die 0 comes first, so nr_cpus= brings the + * CPUs up in that order. The boot loader removes the nodes of the + * cores it did not start. + */ + cpu0: cpu@40000 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by the loader */ + }; + + cpu1: cpu@40001 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu2: cpu@40002 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40002>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu3: cpu@40003 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40003>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu4: cpu@40004 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40004>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu6: cpu@40100 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu7: cpu@40101 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu8: cpu@40102 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu9: cpu@40103 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu10: cpu@40104 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x40104>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu12: cpu@10200 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10200>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu13: cpu@10201 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10201>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu14: cpu@10202 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10202>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu15: cpu@10203 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10203>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu16: cpu@10204 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10204>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu18: cpu@41000 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu19: cpu@41001 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu20: cpu@41002 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41002>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu21: cpu@41003 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41003>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu22: cpu@41004 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41004>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu24: cpu@41100 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu25: cpu@41101 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu26: cpu@41102 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu27: cpu@41103 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu28: cpu@41104 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x41104>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu30: cpu@11200 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x11200>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu31: cpu@11201 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x11201>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu32: cpu@11202 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x11202>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu33: cpu@11203 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x11203>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + + cpu34: cpu@11204 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x11204>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; + }; + }; + + /* The 24 MHz reference clock of the watchdog */ + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = , + , + , + ; + }; + + /* Die 0 MMIO */ + soc@200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x2 0x0 0x2 0x0 0x3 0xc0000000>; + nonposted-mmio; + + /* One AIC3 for both dies, 3104 interrupts each */ + aic: interrupt-controller@280400000 { + compatible = "apple,t6050-aic3", "apple,t8122-aic3"; + interrupt-controller; + #interrupt-cells = <4>; + reg = <0x2 0x80400000 0x0 0x1cc000>, + <0x2 0x80440000 0x0 0x4000>; + reg-names = "core", "event"; + }; + + /* + * DockChannel channel 1, the one the USB debug link carries. + * Its FIFO raises no interrupt on receive, so it is drained in + * software. + */ + dockchannel: serial@288e3c000 { + compatible = "apple,dockchannel-uart"; + reg = <0x2 0x88e3c000 0x0 0x30>, + <0x2 0x88e38000 0x0 0x8>, + <0x2 0x88e0c000 0x0 0x18>; + reg-names = "data", "config", "irq"; + interrupts = ; + apple,channel = <1>; + apple,sw-drain; + status = "disabled"; + }; + + wdt: watchdog@28836c000 { + compatible = "apple,t6050-wdt", "apple,t8103-wdt"; + reg = <0x2 0x8836c000 0x0 0x4000>; + clocks = <&clkref>; + interrupts = ; + }; + + /* + * The storage SART. The boot loader's entries (outside the + * kernel's memory) stay in place. + */ + ans_sart: iommu@41dc50000 { + compatible = "apple,t6050-sart"; + reg = <0x4 0x1dc50000 0x0 0xc000>; + }; + + ans_mbox: mailbox@419608000 { + compatible = "apple,t6050-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x4 0x19608000 0x0 0x4000>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + + /* + * The boot loader leaves ANS running with the controller shut + * down. Its power stays with the firmware, and post-M4 ANS is + * never reset through PMGR, so the node names no power domain + * and no reset. + */ + nvme: nvme@45dcc0000 { + compatible = "apple,t6050-nvme-ans2"; + reg = <0x4 0x5dcc0000 0x0 0x10000>, + <0x4 0x19600000 0x0 0x4000>, + <0x4 0x1dcc0000 0x0 0x60000>; + reg-names = "nvme", "ans", "nvmmu"; + interrupts = ; + mboxes = <&ans_mbox>; + apple,sart = <&ans_sart>; + }; + + /* The DARTs of PCIe ports 2 and 3 */ + dart_apcie2: iommu@412000000 { + compatible = "apple,t6050-dart", "apple,t8110-dart"; + reg = <0x4 0x12000000 0x0 0x20000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + dart_apcie3: iommu@413000000 { + compatible = "apple,t6050-dart", "apple,t8110-dart"; + reg = <0x4 0x13000000 0x0 0x20000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + }; + + /* Die 1 MMIO. The boot loader needs each die's bus. */ + soc@4200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x42 0x0 0x42 0x0 0x3 0xc0000000>; + nonposted-mmio; + }; +};