From 18b66412170c4655731b3b884eef8a2e48c5e7e3 Mon Sep 17 00:00:00 2001 From: Joshua Warren <816217+joshuaswarren@users.noreply.github.com> Date: Fri, 13 Nov 2026 08:23:21 -0600 Subject: [PATCH] arm64: dts: apple: t6050-k114c: describe the USB4/Thunderbolt router on the right USB-C port Share the J714c ATC2 router description (acio2, its DART, NHI and PCIe tunnel) with the K114c by splitting it into t6050-max-atc2-router.dtsi, and enable the five router power domains (atc2-cio, -cio-pcie, -cio-usb, -cio-auss, atc2-pcie) on the K114c. They are disabled in the inventory, and a disabled pmgr child never registers as a power domain, so the router deferred with "Unable to attach PM domains" (-110). The J714s and J716c already enable them. The board also turns acio2 and its mailbox on and names all five domains and the PCIe tunnel itself, so it keeps the fifth domain if acio2 later becomes available to every Max board, disabled by default. Values checked against the K114c ADT. The J714c, J714s, J716c and J716s device trees are unchanged. --- arch/arm64/boot/dts/apple/t6050-k114c.dts | 58 +++- .../boot/dts/apple/t6050-max-atc2-router.dtsi | 279 ++++++++++++++++++ arch/arm64/boot/dts/apple/t6050-max-atc2.dtsi | 272 +---------------- arch/arm64/boot/dts/apple/t6050-max.dtsi | 2 +- .../boot/dts/apple/t6050-peripherals.dtsi | 2 +- 5 files changed, 336 insertions(+), 277 deletions(-) create mode 100644 arch/arm64/boot/dts/apple/t6050-max-atc2-router.dtsi diff --git a/arch/arm64/boot/dts/apple/t6050-k114c.dts b/arch/arm64/boot/dts/apple/t6050-k114c.dts index f221052019041..13ea865ba58e1 100644 --- a/arch/arm64/boot/dts/apple/t6050-k114c.dts +++ b/arch/arm64/boot/dts/apple/t6050-k114c.dts @@ -9,6 +9,8 @@ * Copyright The Asahi Linux Contributors */ +/* Defined before the includes: t6050-max.dtsi guards the ATC2 router on it. */ +#define T6050_K114C #include "t6050-k114-k116.dtsi" / { @@ -20,7 +22,6 @@ firmware-name = "apple/tpmtfw-k114c.bin"; }; -#define T6050_K114C #include "t6050-peripherals.dtsi" / { @@ -432,14 +433,14 @@ }; /* - * ==== The right USB-C port (ATC2), USB only ==== + * ==== The right USB-C port (ATC2) ==== * * ADT /arm-io/nub-spmi-a1/hpm2 (SN201202x, SPMI address 0xc, port-number 3, port-location * "right", acio-parent acio2), with atc-phy2, usb-drd2 and dart-usb2. The HPM is on its own * bus, nub-spmi-a1, and nothing hands the port off, so the power domains, the PHY mailbox, the * PHY, the DWC3 and its DARTs are enabled outright, as t6050-max-atc2.dtsi does for the J714c - * and J716c. The USB4/Thunderbolt router (acio2), the PCIe tunnel and the DisplayPort route - * are not described; the PHY runs in USB mode. + * and J716c. Its USB4/Thunderbolt router (acio2) and PCIe tunnel are + * t6050-max-atc2-router.dtsi, included below; the DisplayPort route is not described. */ / { aliases { @@ -531,3 +532,52 @@ }; }; }; + +#include "t6050-max-atc2-router.dtsi" + +/* The host DROM from the K114cAP ADT (/arm-io/acio2 thunderbolt-drom); the boot loader replaces it */ +&acio2_nhi { + apple,thunderbolt-drom = [fd 02 00 00 00 00 00 00 00 90 19 c3 8c 00 5c 00 + 00 00 00 00 00 00 08 81 82 02 82 00 00 00 08 82 + 92 01 82 00 00 00 03 83 20 08 84 00 00 00 00 00 + 00 08 85 00 00 00 00 00 00 05 86 09 01 00 08 87 + 00 00 00 00 00 00 05 88 09 01 00 05 89 09 01 00 + 05 8a 09 01 00 0e 01 41 70 70 6c 65 2c 20 49 6e + 63 2e 00 06 02 69 4f 53 00 00 00 00]; +}; + +/* The right router's suppliers, disabled in the inventory (as t6050-j714s-display.dtsi enables them) */ +&ps_atc2_cio { + status = "okay"; +}; + +&ps_atc2_cio_pcie { + status = "okay"; +}; + +&ps_atc2_cio_usb { + status = "okay"; +}; + +&ps_atc2_cio_auss { + status = "okay"; +}; + +&ps_atc2_pcie { + status = "okay"; +}; + +/* + * The router and its mailbox are on, with all five domains and the PCIe tunnel, whether or not + * t6050-max.dtsi leaves acio2 disabled and without the fifth domain for boards outside its list. + */ +&acio2_mbox { + status = "okay"; +}; + +&acio2 { + status = "okay"; + power-domains = <&ps_atc2_cio>, <&ps_atc2_cio_pcie>, + <&ps_atc2_cio_usb>, <&ps_atc2_cio_auss>, <&ps_atc2_pcie>; + apple,pcie-tunnel = <&acio2_pcie_tunnel>; +}; diff --git a/arch/arm64/boot/dts/apple/t6050-max-atc2-router.dtsi b/arch/arm64/boot/dts/apple/t6050-max-atc2-router.dtsi new file mode 100644 index 0000000000000..b61c623c5c36b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6050-max-atc2-router.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * The M5 Max MacBook Pros' right USB-C port router (ATC2): the CIO reset, the PD controller's USB4 port, + * the router, NHI, DART and PCIe tunnel tunables. A board file includes this after + * t6050-peripherals.dtsi, with hpm2 and the ATC2 PHY and DWC3 nodes enabled, and sets its own host + * DROM (apple,thunderbolt-drom) on &acio2_nhi; the boot loader replaces it. + */ + +/* + * ==== The right USB-C port's USB4/Thunderbolt router (ATC2) ==== + * + * Until the boot loader fills them, the router, NHI, PHY CIO and DART tunables and the host + * DROM are this board's, from its ADT (the DROM's router UUID from an earlier boot). + */ +/* ATC2_CIO_AUSS's other parent; kept as the boot loader leaves it */ +&ps_auss { + status = "okay"; +}; + +/* The CIO reconfig request, port 2 (clock gate CIO2_RECONFIG_V) */ +&cio_reconfig0 { + status = "okay"; +}; + +/* The PHY's CIO80 RX_TOP tunables (ADT tunable_LN0/LN1_RX_TOP_CIO_DFLT); the other three are empty */ +&atc2_phy { + apple,tunable-lane0-rx-top-cio = <0x35c 0xe00 0x0>; + apple,tunable-lane1-rx-top-cio = <0x35c 0xe00 0x0>; +}; + +/* Only the router's LSTX pin (81) of the AOP GPIO controller is exposed. */ +&pinctrl_aop { + gpio-reserved-ranges = <0 81>, <82 3>; + status = "okay"; +}; + +&hpm2 { + connector { + ports { + port@3 { + reg = <3>; + hpm2_usb4: endpoint { + remote-endpoint = <&acio2_tbt>; + }; + }; + }; + }; +}; + +&acio2 { + apple,tunable-rc = <0x0 0xfff0 0x4020>, + <0x2c 0x4 0x0>, + <0x4004 0x1ff01ff 0x1000100>, + <0x4008 0x801f 0x4>, + <0x4010 0x7f 0x40>, + <0x4014 0x801f 0x4>, + <0x401c 0x7f 0x40>, + <0x4024 0x801f 0x4>, + <0x402c 0x7f 0x40>, + <0x4030 0x801f 0x4>, + <0x4038 0xffffffff 0x1010101>, + <0x403c 0xffff 0x101>, + <0x4040 0x1 0x1>, + <0x4044 0xffffffff 0x1010101>, + <0x4048 0x1 0x1>, + <0x404c 0x801f 0x4>, + <0x8004 0x70007 0x40004>, + <0x8008 0x801f 0x4>, + <0x8010 0x70007 0x40004>, + <0x8018 0x801f 0x4>, + <0x8020 0x70007 0x40004>, + <0x8028 0x801f 0x4>, + <0x8030 0x801f 0x4>, + <0x8038 0x801f 0x4>, + <0x8040 0x801f 0x4>, + <0x8048 0x801f 0x4>, + <0x8050 0x801f 0x4>, + <0x8058 0x801f 0x4>, + <0x8060 0x801f 0x4>; + apple,tunable-pcie-adapter = <0x1008 0x6 0x6>; + apple,tunable-router-ap-fw = <0x8 0xff2 0x482>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + acio2_tbt: endpoint { + remote-endpoint = <&hpm2_usb4>; + }; + }; + }; +}; + +&acio2_dart { + apple,tunable = <0x20c 0x80000121 0x80000121>, + <0x220 0xf0f 0xf0f>, + <0x224 0xffff 0x909>, + <0x300 0x1f31 0x1>, + <0x308 0x3ffffffc 0x10000000>, + <0x310 0x3ffffffc 0x3ffffffc>, + <0x800 0xf003f 0x10000>, + <0x804 0xf003f 0x10002>, + <0x808 0xf003f 0x10004>, + <0x80c 0xf003f 0x20006>, + <0x810 0xf003f 0x2000a>, + <0x814 0xf003f 0x2000e>, + <0x818 0xf003f 0x20012>, + <0x81c 0xf003f 0x20016>, + <0x820 0xf003f 0x2001a>, + <0x824 0xf003f 0x2001e>, + <0x828 0xf003f 0x20022>, + <0x82c 0xf003f 0x20026>, + <0x830 0xf003f 0x2002a>, + <0x834 0xf003f 0x2002e>, + <0x838 0xf003f 0x20032>, + <0x83c 0xf003f 0x10036>; +}; + +&acio2_nhi { + apple,tunable-nhi = <0xf8004 0xff 0x80>, + <0xf8008 0x801f 0x4>, + <0xf8010 0x3f 0x20>, + <0xf8014 0x801f 0x4>, + <0xf801c 0x1f 0x10>, + <0xf8020 0x801f 0x4>, + <0xf8028 0xff 0x80>, + <0xf802c 0x801f 0x4>, + <0xf8034 0xff 0x80>, + <0xf8038 0x801f 0x4>, + <0xf8040 0x3f 0x20>, + <0xf8044 0x801f 0x4>, + <0xf804c 0x8007 0x1>, + <0xfc004 0x3 0x2>, + <0xfc008 0x801f 0x4>, + <0xfc010 0x7 0x4>, + <0xfc014 0x801f 0x4>, + <0xfc01c 0x7 0x4>, + <0xfc020 0x801f 0x4>, + <0xfc028 0x7 0x4>, + <0xfc02c 0x801f 0x4>, + <0xfc034 0x7 0x4>, + <0xfc038 0x801f 0x4>, + <0xfc040 0x3 0x2>, + <0xfc044 0x801f 0x4>, + <0xfc04c 0x8007 0x1>, + <0x4000 0x1000000f 0x10000002>, + <0x4004 0x1000000f 0x10000002>, + <0x4008 0x1000000f 0x10000002>, + <0x400c 0x1000000f 0x10000002>, + <0x4010 0x1000000f 0x10000002>, + <0x4014 0x1000000f 0x10000002>, + <0x4018 0x1000000f 0x10000002>, + <0x401c 0x1000000f 0x10000002>, + <0x4020 0x1000000f 0x10000002>, + <0x4024 0x1000000f 0x10000002>, + <0x4028 0x1000000f 0x10000002>, + <0x402c 0x1000000f 0x10000002>, + <0x4040 0x1000000f 0x10000002>, + <0x4044 0x1000000f 0x10000002>, + <0x4048 0x1000000f 0x10000002>, + <0x404c 0x1000000f 0x10000002>, + <0x4050 0x1000000f 0x10000002>, + <0x4054 0x1000000f 0x10000002>, + <0x4058 0x1000000f 0x10000002>, + <0x405c 0x1000000f 0x10000002>, + <0x4060 0x1000000f 0x10000002>, + <0x4064 0x1000000f 0x10000002>, + <0x4068 0x1000000f 0x10000002>, + <0x406c 0x1000000f 0x10000002>, + <0x4080 0x1000000f 0x10000002>, + <0x4084 0x1000000f 0x10000002>, + <0x4088 0x1000000f 0x10000002>, + <0x408c 0x1000000f 0x10000002>, + <0x4090 0x1000000f 0x10000002>, + <0x4094 0x1000000f 0x10000002>, + <0x4098 0x1000000f 0x10000002>, + <0x409c 0x1000000f 0x10000002>, + <0x40a0 0x1000000f 0x10000002>, + <0x40a4 0x1000000f 0x10000002>, + <0x40a8 0x1000000f 0x10000002>, + <0x40ac 0x1000000f 0x10000002>, + <0x40c0 0x1000000f 0x10000002>, + <0x40c4 0x1000000f 0x10000002>, + <0x40c8 0x1000000f 0x10000002>, + <0x40cc 0x1000000f 0x10000002>, + <0x40d0 0x1000000f 0x10000002>, + <0x40d4 0x1000000f 0x10000002>, + <0x40d8 0x1000000f 0x10000002>, + <0x40dc 0x1000000f 0x10000002>, + <0x40e0 0x1000000f 0x10000002>, + <0x40e4 0x1000000f 0x10000002>, + <0x40e8 0x1000000f 0x10000002>, + <0x40ec 0x1000000f 0x10000002>, + <0x4100 0x1000000f 0x10000002>, + <0x4104 0x1000000f 0x10000002>, + <0x4108 0x1000000f 0x10000002>, + <0x410c 0x1000000f 0x10000002>, + <0x4110 0x1000000f 0x10000002>, + <0x4114 0x1000000f 0x10000002>, + <0x4118 0x1000000f 0x10000002>, + <0x411c 0x1000000f 0x10000002>, + <0x4120 0x1000000f 0x10000002>, + <0x4124 0x1000000f 0x10000002>, + <0x4128 0x1000000f 0x10000002>, + <0x412c 0x1000000f 0x10000002>, + <0x4140 0x1000000f 0x10000002>, + <0x4144 0x1000000f 0x10000002>, + <0x4148 0x1000000f 0x10000002>, + <0x414c 0x1000000f 0x10000002>, + <0x4150 0x1000000f 0x10000002>, + <0x4154 0x1000000f 0x10000002>, + <0x4158 0x1000000f 0x10000002>, + <0x415c 0x1000000f 0x10000002>, + <0x4160 0x1000000f 0x10000002>, + <0x4164 0x1000000f 0x10000002>, + <0x4168 0x1000000f 0x10000002>, + <0x416c 0x1000000f 0x10000002>, + <0x43e4 0x7 0x7>; +}; + +/* ==== The right USB-C port's PCIe tunnel (ATC2): this board's tunables ==== */ +&apciec2_dart { + apple,tunable = <0x20c 0x80000121 0x80000121>, + <0x220 0xf0f 0xf0f>, + <0x224 0xffff 0x909>, + <0x300 0x1f31 0x1>, + <0x308 0x3ffffffc 0x10000000>, + <0x310 0x3ffffffc 0x3ffffffc>; +}; + +&apciec2 { + apple,tunable-debug = <0x1000 0x1 0x0>; + apple,tunable-rc = <0x78 0x7000 0x0>, + <0x718 0x7c000 0x0>, + <0x814 0xffffffff 0x2020f060>, + <0x8bc 0x1 0x0>; + apple,tunable-fabric = <0x4 0x3f003f 0x240024>, + <0x8 0x1 0x1>, + <0xc 0x1 0x1>, + <0x10 0x801f 0x4>, + <0x18 0x1ff 0x1e0>, + <0x1c 0x1 0x1>, + <0x20 0x801f 0x4>, + <0x28 0x1f 0x10>, + <0x2c 0x801f 0x4>, + <0x34 0x3f 0x20>, + <0x38 0x801f 0x4>, + <0x40 0x3f 0x20>, + <0x44 0x801f 0x4>, + <0x4c 0x10001 0x10001>, + <0x50 0x1 0x1>, + <0x54 0x1 0x1>, + <0x58 0x801f 0x4>, + <0x60 0x7f007f 0x450045>, + <0x64 0x801f 0x4>, + <0x6c 0x1f001f 0x100010>, + <0x70 0xf1 0x1>, + <0x74 0x801f 0x4>, + <0x7c 0x801f 0x4>, + <0x84 0x1 0x1>, + <0x88 0x1 0x1>, + <0x8c 0x801f 0x4>, + <0x94 0x1 0x1>, + <0x98 0x801f 0x4>, + <0xa0 0x1 0x1>, + <0xa4 0x801f 0x4>, + <0xac 0x1 0x1>, + <0xb0 0x1 0x1>, + <0xb4 0x801f 0x4>, + <0xbc 0x801f 0x4>, + <0xc4 0x801f 0x4>; +}; + +&apciec2_port { + apple,tunable = <0x140 0x1 0x1>, + <0x2a0 0x7e 0xa>; +}; diff --git a/arch/arm64/boot/dts/apple/t6050-max-atc2.dtsi b/arch/arm64/boot/dts/apple/t6050-max-atc2.dtsi index 40bcd58cd843f..e179d9e761d79 100644 --- a/arch/arm64/boot/dts/apple/t6050-max-atc2.dtsi +++ b/arch/arm64/boot/dts/apple/t6050-max-atc2.dtsi @@ -125,274 +125,4 @@ }; }; -/* - * ==== The right USB-C port's USB4/Thunderbolt router (ATC2) ==== - * - * Until the boot loader fills them, the router, NHI, PHY CIO and DART tunables and the host - * DROM are this board's, from its ADT (the DROM's router UUID from an earlier boot). - */ -/* ATC2_CIO_AUSS's other parent; kept as the boot loader leaves it */ -&ps_auss { - status = "okay"; -}; - -/* The CIO reconfig request, port 2 (clock gate CIO2_RECONFIG_V) */ -&cio_reconfig0 { - status = "okay"; -}; - -/* The PHY's CIO80 RX_TOP tunables (ADT tunable_LN0/LN1_RX_TOP_CIO_DFLT); the other three are empty */ -&atc2_phy { - apple,tunable-lane0-rx-top-cio = <0x35c 0xe00 0x0>; - apple,tunable-lane1-rx-top-cio = <0x35c 0xe00 0x0>; -}; - -/* Only the router's LSTX pin (81) of the AOP GPIO controller is exposed. */ -&pinctrl_aop { - gpio-reserved-ranges = <0 81>, <82 3>; - status = "okay"; -}; - -&hpm2 { - connector { - ports { - port@3 { - reg = <3>; - hpm2_usb4: endpoint { - remote-endpoint = <&acio2_tbt>; - }; - }; - }; - }; -}; - -&acio2 { - apple,tunable-rc = <0x0 0xfff0 0x4020>, - <0x2c 0x4 0x0>, - <0x4004 0x1ff01ff 0x1000100>, - <0x4008 0x801f 0x4>, - <0x4010 0x7f 0x40>, - <0x4014 0x801f 0x4>, - <0x401c 0x7f 0x40>, - <0x4024 0x801f 0x4>, - <0x402c 0x7f 0x40>, - <0x4030 0x801f 0x4>, - <0x4038 0xffffffff 0x1010101>, - <0x403c 0xffff 0x101>, - <0x4040 0x1 0x1>, - <0x4044 0xffffffff 0x1010101>, - <0x4048 0x1 0x1>, - <0x404c 0x801f 0x4>, - <0x8004 0x70007 0x40004>, - <0x8008 0x801f 0x4>, - <0x8010 0x70007 0x40004>, - <0x8018 0x801f 0x4>, - <0x8020 0x70007 0x40004>, - <0x8028 0x801f 0x4>, - <0x8030 0x801f 0x4>, - <0x8038 0x801f 0x4>, - <0x8040 0x801f 0x4>, - <0x8048 0x801f 0x4>, - <0x8050 0x801f 0x4>, - <0x8058 0x801f 0x4>, - <0x8060 0x801f 0x4>; - apple,tunable-pcie-adapter = <0x1008 0x6 0x6>; - apple,tunable-router-ap-fw = <0x8 0xff2 0x482>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - acio2_tbt: endpoint { - remote-endpoint = <&hpm2_usb4>; - }; - }; - }; -}; - -&acio2_dart { - apple,tunable = <0x20c 0x80000121 0x80000121>, - <0x220 0xf0f 0xf0f>, - <0x224 0xffff 0x909>, - <0x300 0x1f31 0x1>, - <0x308 0x3ffffffc 0x10000000>, - <0x310 0x3ffffffc 0x3ffffffc>, - <0x800 0xf003f 0x10000>, - <0x804 0xf003f 0x10002>, - <0x808 0xf003f 0x10004>, - <0x80c 0xf003f 0x20006>, - <0x810 0xf003f 0x2000a>, - <0x814 0xf003f 0x2000e>, - <0x818 0xf003f 0x20012>, - <0x81c 0xf003f 0x20016>, - <0x820 0xf003f 0x2001a>, - <0x824 0xf003f 0x2001e>, - <0x828 0xf003f 0x20022>, - <0x82c 0xf003f 0x20026>, - <0x830 0xf003f 0x2002a>, - <0x834 0xf003f 0x2002e>, - <0x838 0xf003f 0x20032>, - <0x83c 0xf003f 0x10036>; -}; - -&acio2_nhi { - apple,tunable-nhi = <0xf8004 0xff 0x80>, - <0xf8008 0x801f 0x4>, - <0xf8010 0x3f 0x20>, - <0xf8014 0x801f 0x4>, - <0xf801c 0x1f 0x10>, - <0xf8020 0x801f 0x4>, - <0xf8028 0xff 0x80>, - <0xf802c 0x801f 0x4>, - <0xf8034 0xff 0x80>, - <0xf8038 0x801f 0x4>, - <0xf8040 0x3f 0x20>, - <0xf8044 0x801f 0x4>, - <0xf804c 0x8007 0x1>, - <0xfc004 0x3 0x2>, - <0xfc008 0x801f 0x4>, - <0xfc010 0x7 0x4>, - <0xfc014 0x801f 0x4>, - <0xfc01c 0x7 0x4>, - <0xfc020 0x801f 0x4>, - <0xfc028 0x7 0x4>, - <0xfc02c 0x801f 0x4>, - <0xfc034 0x7 0x4>, - <0xfc038 0x801f 0x4>, - <0xfc040 0x3 0x2>, - <0xfc044 0x801f 0x4>, - <0xfc04c 0x8007 0x1>, - <0x4000 0x1000000f 0x10000002>, - <0x4004 0x1000000f 0x10000002>, - <0x4008 0x1000000f 0x10000002>, - <0x400c 0x1000000f 0x10000002>, - <0x4010 0x1000000f 0x10000002>, - <0x4014 0x1000000f 0x10000002>, - <0x4018 0x1000000f 0x10000002>, - <0x401c 0x1000000f 0x10000002>, - <0x4020 0x1000000f 0x10000002>, - <0x4024 0x1000000f 0x10000002>, - <0x4028 0x1000000f 0x10000002>, - <0x402c 0x1000000f 0x10000002>, - <0x4040 0x1000000f 0x10000002>, - <0x4044 0x1000000f 0x10000002>, - <0x4048 0x1000000f 0x10000002>, - <0x404c 0x1000000f 0x10000002>, - <0x4050 0x1000000f 0x10000002>, - <0x4054 0x1000000f 0x10000002>, - <0x4058 0x1000000f 0x10000002>, - <0x405c 0x1000000f 0x10000002>, - <0x4060 0x1000000f 0x10000002>, - <0x4064 0x1000000f 0x10000002>, - <0x4068 0x1000000f 0x10000002>, - <0x406c 0x1000000f 0x10000002>, - <0x4080 0x1000000f 0x10000002>, - <0x4084 0x1000000f 0x10000002>, - <0x4088 0x1000000f 0x10000002>, - <0x408c 0x1000000f 0x10000002>, - <0x4090 0x1000000f 0x10000002>, - <0x4094 0x1000000f 0x10000002>, - <0x4098 0x1000000f 0x10000002>, - <0x409c 0x1000000f 0x10000002>, - <0x40a0 0x1000000f 0x10000002>, - <0x40a4 0x1000000f 0x10000002>, - <0x40a8 0x1000000f 0x10000002>, - <0x40ac 0x1000000f 0x10000002>, - <0x40c0 0x1000000f 0x10000002>, - <0x40c4 0x1000000f 0x10000002>, - <0x40c8 0x1000000f 0x10000002>, - <0x40cc 0x1000000f 0x10000002>, - <0x40d0 0x1000000f 0x10000002>, - <0x40d4 0x1000000f 0x10000002>, - <0x40d8 0x1000000f 0x10000002>, - <0x40dc 0x1000000f 0x10000002>, - <0x40e0 0x1000000f 0x10000002>, - <0x40e4 0x1000000f 0x10000002>, - <0x40e8 0x1000000f 0x10000002>, - <0x40ec 0x1000000f 0x10000002>, - <0x4100 0x1000000f 0x10000002>, - <0x4104 0x1000000f 0x10000002>, - <0x4108 0x1000000f 0x10000002>, - <0x410c 0x1000000f 0x10000002>, - <0x4110 0x1000000f 0x10000002>, - <0x4114 0x1000000f 0x10000002>, - <0x4118 0x1000000f 0x10000002>, - <0x411c 0x1000000f 0x10000002>, - <0x4120 0x1000000f 0x10000002>, - <0x4124 0x1000000f 0x10000002>, - <0x4128 0x1000000f 0x10000002>, - <0x412c 0x1000000f 0x10000002>, - <0x4140 0x1000000f 0x10000002>, - <0x4144 0x1000000f 0x10000002>, - <0x4148 0x1000000f 0x10000002>, - <0x414c 0x1000000f 0x10000002>, - <0x4150 0x1000000f 0x10000002>, - <0x4154 0x1000000f 0x10000002>, - <0x4158 0x1000000f 0x10000002>, - <0x415c 0x1000000f 0x10000002>, - <0x4160 0x1000000f 0x10000002>, - <0x4164 0x1000000f 0x10000002>, - <0x4168 0x1000000f 0x10000002>, - <0x416c 0x1000000f 0x10000002>, - <0x43e4 0x7 0x7>; -}; - -/* ==== The right USB-C port's PCIe tunnel (ATC2): this board's tunables ==== */ -&apciec2_dart { - apple,tunable = <0x20c 0x80000121 0x80000121>, - <0x220 0xf0f 0xf0f>, - <0x224 0xffff 0x909>, - <0x300 0x1f31 0x1>, - <0x308 0x3ffffffc 0x10000000>, - <0x310 0x3ffffffc 0x3ffffffc>; -}; - -&apciec2 { - apple,tunable-debug = <0x1000 0x1 0x0>; - apple,tunable-rc = <0x78 0x7000 0x0>, - <0x718 0x7c000 0x0>, - <0x814 0xffffffff 0x2020f060>, - <0x8bc 0x1 0x0>; - apple,tunable-fabric = <0x4 0x3f003f 0x240024>, - <0x8 0x1 0x1>, - <0xc 0x1 0x1>, - <0x10 0x801f 0x4>, - <0x18 0x1ff 0x1e0>, - <0x1c 0x1 0x1>, - <0x20 0x801f 0x4>, - <0x28 0x1f 0x10>, - <0x2c 0x801f 0x4>, - <0x34 0x3f 0x20>, - <0x38 0x801f 0x4>, - <0x40 0x3f 0x20>, - <0x44 0x801f 0x4>, - <0x4c 0x10001 0x10001>, - <0x50 0x1 0x1>, - <0x54 0x1 0x1>, - <0x58 0x801f 0x4>, - <0x60 0x7f007f 0x450045>, - <0x64 0x801f 0x4>, - <0x6c 0x1f001f 0x100010>, - <0x70 0xf1 0x1>, - <0x74 0x801f 0x4>, - <0x7c 0x801f 0x4>, - <0x84 0x1 0x1>, - <0x88 0x1 0x1>, - <0x8c 0x801f 0x4>, - <0x94 0x1 0x1>, - <0x98 0x801f 0x4>, - <0xa0 0x1 0x1>, - <0xa4 0x801f 0x4>, - <0xac 0x1 0x1>, - <0xb0 0x1 0x1>, - <0xb4 0x801f 0x4>, - <0xbc 0x801f 0x4>, - <0xc4 0x801f 0x4>; -}; - -&apciec2_port { - apple,tunable = <0x140 0x1 0x1>, - <0x2a0 0x7e 0xa>; -}; +#include "t6050-max-atc2-router.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6050-max.dtsi b/arch/arm64/boot/dts/apple/t6050-max.dtsi index 1d9532af1675a..7952525ab1d3c 100644 --- a/arch/arm64/boot/dts/apple/t6050-max.dtsi +++ b/arch/arm64/boot/dts/apple/t6050-max.dtsi @@ -199,7 +199,7 @@ #endif }; -#if defined(T6050_J714C) || defined(T6050_J714S) || defined(T6050_J716C) +#if defined(T6050_J714C) || defined(T6050_J714S) || defined(T6050_J716C) || defined(T6050_K114C) /* * ATC2's USB4/Thunderbolt router (ADT /arm-io/acio2, acio-cpu2 and dart-acio2), powered per * connection: the PHY enters CIO mode, then the router's domains come on (ATC2_CIO, _PCIE, _USB, diff --git a/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi b/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi index 596ed95d4501a..6755790ecd529 100644 --- a/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi +++ b/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi @@ -1549,7 +1549,7 @@ status = "disabled"; }; -#if !defined(T6050_J714C) && !defined(T6050_J714S) && !defined(T6050_J716C) +#if !defined(T6050_J714C) && !defined(T6050_J714S) && !defined(T6050_J716C) && !defined(T6050_K114C) apciec2_dart: iommu@384000000 { compatible = "apple,t6050-dart", "apple,t8110-dart"; reg = <0x3 0x84000000 0x0 0x20000>;