From fbfb50c364083ae6a529a3b5e728af7bed9aa291 Mon Sep 17 00:00:00 2001 From: DjDeveloperr Date: Fri, 13 Nov 2026 02:56:53 -0500 Subject: [PATCH] arm64: dts: apple: t6050-j714s: Add the left-front port's USB4 router The left-front USB-C port (ATC1) had only its PD controller, USB 2/3 and DisplayPort alt mode described. A USB4 device there got a PD contract and the PHY switched to USB4, but with no router nothing trained the link, so there was no tunnel and no fallback. Describe ATC1's USB4/Thunderbolt router (acio1, its CPU mailbox, DART and NHI) and its PCIe tunnel (apciec1 and its DART) as the right port's, with the J714sAP ADT's addresses, interrupts, tunables and host DROM, and link hpm1's connector to the router. The router, DART and tunnel tunables equal ATC2's. The PHY's CIO RX_TOP lane tunables differ from ATC2's and are this port's. The router's LSTX pin, AOP GPIO 79, is exposed next to ATC2's 81. The shared inventory's disabled apciec1 DART now stays out of J714s, as it does for J716c, which describes the same nodes. Signed-off-by: Diljit Singh --- .../boot/dts/apple/t6050-j714s-left-usb4.dtsi | 497 ++++++++++++++++++ arch/arm64/boot/dts/apple/t6050-j714s.dts | 3 + .../boot/dts/apple/t6050-peripherals.dtsi | 2 +- 3 files changed, 501 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/apple/t6050-j714s-left-usb4.dtsi diff --git a/arch/arm64/boot/dts/apple/t6050-j714s-left-usb4.dtsi b/arch/arm64/boot/dts/apple/t6050-j714s-left-usb4.dtsi new file mode 100644 index 000000000000..016432b78a47 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6050-j714s-left-usb4.dtsi @@ -0,0 +1,497 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * J714s left-front USB-C port (ATC1): the USB4/Thunderbolt router and its PCIe tunnel. + * + * The same router and tunnel as J716c's ATC1 (t6050-j716c-left-usb4.dtsi), at the J714sAP ADT's + * addresses and interrupts (/arm-io/acio1, acio-cpu1, dart-acio1, apciec1, dart-apciec1). Like + * the right port's (t6050-max-atc2.dtsi), it is powered per connection and nothing is touched at + * boot. The router, DART and tunnel tunables are this board's, from its ADT; they equal ATC2's. + */ + +&ps_atc1_cio { + power-domains = <&ps_atc1_common>; + status = "okay"; +}; + +&ps_atc1_cio_pcie { + power-domains = <&ps_atc1_cio>; + status = "okay"; +}; + +&ps_atc1_cio_usb { + power-domains = <&ps_atc1_cio>; + status = "okay"; +}; + +&ps_atc1_cio_auss { + power-domains = <&ps_atc1_cio>, <&ps_auss>; + status = "okay"; +}; + +/* With the ATC1 USB always-on clock gate, as ATC2_PCIE */ +&ps_atc1_pcie { + power-domains = <&ps_atc1_common>, <&ps_atc1_usb_aon>; + status = "okay"; +}; + +/* LSTX: /arm-io/acio1 gpio-lstx, AOP GPIO pin 79 (0x4f), function 1 for the router */ +&pinctrl_aop { + acio1_lstx_pins: acio1-lstx-pins { + pinmux = <0x1004f>; /* APPLE_PINMUX(79, 1) */ + }; +}; + +/* The two routers' LSTX pins (79 and 81) are the only AOP GPIOs exposed. */ +&pinctrl_aop { + gpio-reserved-ranges = <0 79>, <80 1>, <82 3>; +}; + +&{/soc@200000000} { + /* /arm-io/acio-cpu1 reg[0]: the router CPU's mailbox, inside its wrapper */ + acio1_mbox: mailbox@2a9108000 { + compatible = "apple,t6050-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0xa9108000 0x0 0x4000>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + + acio1: acio@2a9ac0000 { + compatible = "apple,t6050-usb4-acio"; + reg = <0x2 0xa9ac0000 0x0 0xc000>, + <0x2 0xa9080000 0x0 0x26000>, + <0x2 0xa9e44000 0x0 0x4000>, + <0x2 0xa9100000 0x0 0x4000>, + <0x2 0xa9c80000 0x0 0x4000>; + reg-names = "rc", "sram", "pcie-adapter", "cpu", "router-ap-fw"; + mboxes = <&acio1_mbox>; + resets = <&cio_reconfig0 1>; + /* ATC1_PCIE last: the PCIe tunnel root port, set up before it is populated */ + power-domains = <&ps_atc1_cio>, <&ps_atc1_cio_pcie>, + <&ps_atc1_cio_usb>, <&ps_atc1_cio_auss>, <&ps_atc1_pcie>; + thunderbolt-switch; + apple,pcie-tunnel = <&acio1_pcie_tunnel>; + pinctrl-0 = <&acio1_lstx_pins>; + pinctrl-names = "lstx"; + lstx-gpios = <&pinctrl_aop 79 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2 0xa9000000 0x1000000>; + nonposted-mmio; + + acio1_dart: iommu@a80000 { + compatible = "apple,t6050-dart", "apple,t8110-dart"; + reg = <0xa80000 0xc000>; + interrupts = ; + power-domains = <&ps_atc1_cio>; + #iommu-cells = <1>; + apple,dma-range = <0x100 0x4000 0x0 0xffff0000>; + apple,bypass-sids = <15>; + apple,full-error-reporting; + apple,ctc-flush; + }; + + /* Interrupts 0x64b.. are the TX rings and 0x657.. the RX rings */ + acio1_nhi: nhi@f00000 { + compatible = "apple,t6050-usb4-nhi"; + reg = <0xf00000 0x100000>; + reg-names = "nhi"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "txring0", "txring1", "txring2", "txring3", + "txring4", "txring5", "txring6", "txring7", + "txring8", "txring9", "txring10", "txring11", + "rxring0", "rxring1", "rxring2", "rxring3", + "rxring4", "rxring5", "rxring6", "rxring7", + "rxring8", "rxring9", "rxring10", "rxring11", + "parity"; + iommus = <&acio1_dart 0>, + <&acio1_dart 1>, + <&acio1_dart 2>, + <&acio1_dart 3>, + <&acio1_dart 4>, + <&acio1_dart 5>, + <&acio1_dart 6>, + <&acio1_dart 7>, + <&acio1_dart 8>, + <&acio1_dart 9>, + <&acio1_dart 10>, + <&acio1_dart 11>, + <&acio1_dart 16>, + <&acio1_dart 17>, + <&acio1_dart 18>, + <&acio1_dart 19>, + <&acio1_dart 20>, + <&acio1_dart 21>, + <&acio1_dart 22>, + <&acio1_dart 23>, + <&acio1_dart 24>, + <&acio1_dart 25>, + <&acio1_dart 26>, + <&acio1_dart 27>; + }; + }; +}; + +/* + * ATC1's PCIe tunnel: /arm-io/apciec1 and dart-apciec1, the PCIe-C root port behind the router's + * PCIe down adapter, set up as ATC2's. MSIs use the bridge's 32-vector slice (160-191). + */ +/ { + acio1_pcie_tunnel: pcie-tunnel-1 { + #address-cells = <2>; + #size-cells = <2>; + ranges; + nonposted-mmio; + + apciec1_dart: iommu@2ac000000 { + compatible = "apple,t6050-dart", "apple,t8110-dart"; + reg = <0x2 0xac000000 0x0 0x20000>; + interrupts = ; + power-domains = <&ps_atc1_pcie>; + #iommu-cells = <1>; + apple,bypass-sids = <253 255>; + apple,full-error-reporting; + apple,ctc-flush; + }; + + apciec1: pcie@1c60000000 { + compatible = "apple,t6050-pciec"; + device_type = "pci"; + reg = <0x1c 0x60000000 0x0 0x10000000>, + <0x2 0xac034000 0x0 0x4000>, + <0x2 0xac020000 0x0 0x8000>, + <0x2 0xac038000 0x0 0x4000>, + <0x2 0xac060000 0x0 0x4000>, + <0x2 0xac02c000 0x0 0x4000>, + <0x2 0xac028000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "fabric", "debug", "ltssm", "intr2axi"; + /* The port's: link events and INTx */ + interrupts = ; + interrupt-names = "port0"; + power-domains = <&ps_atc1_pcie>; + /* No boot loader hands the port over: the kernel cold-initializes it. */ + apple,pciec-kernel-init; + + msi-controller; + msi-parent = <&apciec1>; + msi-ranges = <&aic AIC_IRQ 0 1984 IRQ_TYPE_EDGE_RISING 32>; + apple,msi-vector-base = <160>; + + iommu-map = <0x0 &apciec1_dart 0x0 0x40>; + iommu-map-mask = <0x3f>; + linux,pci-domain = <2>; + bus-range = <0x0 0x7f>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0xc 0x0 0xc 0x0 0x2 0x0>, + <0x02000000 0x0 0x00100000 0xe 0x00100000 0x0 0x3ff00000>, + <0x42000000 0x0 0x40000000 0xe 0x40000000 0x0 0x40000000>; + + apciec1_port: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + external-facing; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &apciec1_port 0 0 0 0>, + <0 0 0 2 &apciec1_port 0 0 0 1>, + <0 0 0 3 &apciec1_port 0 0 0 2>, + <0 0 0 4 &apciec1_port 0 0 0 3>; + }; + }; + }; +}; + +/* + * The PHY's CIO80 RX_TOP tunables (ADT atc-phy1 tunable_LN0/LN1_RX_TOP_CIO_DFLT). Unlike + * ATC2's, this port's set the field to 0x200. + */ +&atc1_phy { + apple,tunable-lane0-rx-top-cio = <0x35c 0xe00 0x200>; + apple,tunable-lane1-rx-top-cio = <0x35c 0xe00 0x200>; +}; + +&typec1 { + ports { + port@3 { + reg = <3>; + typec1_usb4: endpoint { + remote-endpoint = <&acio1_tbt>; + }; + }; + }; +}; + +&acio1 { + apple,tunable-rc = <0x0 0xfff0 0x4020>, + <0x2c 0x4 0x0>, + <0x4004 0x1ff01ff 0x1000100>, + <0x4008 0x801f 0x4>, + <0x4010 0x7f 0x40>, + <0x4014 0x801f 0x4>, + <0x401c 0x7f 0x40>, + <0x4024 0x801f 0x4>, + <0x402c 0x7f 0x40>, + <0x4030 0x801f 0x4>, + <0x4038 0xffffffff 0x1010101>, + <0x403c 0xffff 0x101>, + <0x4040 0x1 0x1>, + <0x4044 0xffffffff 0x1010101>, + <0x4048 0x1 0x1>, + <0x404c 0x801f 0x4>, + <0x8004 0x70007 0x40004>, + <0x8008 0x801f 0x4>, + <0x8010 0x70007 0x40004>, + <0x8018 0x801f 0x4>, + <0x8020 0x70007 0x40004>, + <0x8028 0x801f 0x4>, + <0x8030 0x801f 0x4>, + <0x8038 0x801f 0x4>, + <0x8040 0x801f 0x4>, + <0x8048 0x801f 0x4>, + <0x8050 0x801f 0x4>, + <0x8058 0x801f 0x4>, + <0x8060 0x801f 0x4>; + apple,tunable-pcie-adapter = <0x1008 0x6 0x6>; + apple,tunable-router-ap-fw = <0x8 0xff2 0x482>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + acio1_tbt: endpoint { + remote-endpoint = <&typec1_usb4>; + }; + }; + }; +}; + +&acio1_dart { + apple,tunable = <0x20c 0x80000121 0x80000121>, + <0x220 0xf0f 0xf0f>, + <0x224 0xffff 0x909>, + <0x300 0x1f31 0x1>, + <0x308 0x3ffffffc 0x10000000>, + <0x310 0x3ffffffc 0x3ffffffc>, + <0x800 0xf003f 0x10000>, + <0x804 0xf003f 0x10002>, + <0x808 0xf003f 0x10004>, + <0x80c 0xf003f 0x20006>, + <0x810 0xf003f 0x2000a>, + <0x814 0xf003f 0x2000e>, + <0x818 0xf003f 0x20012>, + <0x81c 0xf003f 0x20016>, + <0x820 0xf003f 0x2001a>, + <0x824 0xf003f 0x2001e>, + <0x828 0xf003f 0x20022>, + <0x82c 0xf003f 0x20026>, + <0x830 0xf003f 0x2002a>, + <0x834 0xf003f 0x2002e>, + <0x838 0xf003f 0x20032>, + <0x83c 0xf003f 0x10036>; +}; + +/* The host DROM: the J714sAP ADT's /arm-io/acio1 thunderbolt-drom; the boot loader replaces it */ +&acio1_nhi { + apple,tunable-nhi = <0xf8004 0xff 0x80>, + <0xf8008 0x801f 0x4>, + <0xf8010 0x3f 0x20>, + <0xf8014 0x801f 0x4>, + <0xf801c 0x1f 0x10>, + <0xf8020 0x801f 0x4>, + <0xf8028 0xff 0x80>, + <0xf802c 0x801f 0x4>, + <0xf8034 0xff 0x80>, + <0xf8038 0x801f 0x4>, + <0xf8040 0x3f 0x20>, + <0xf8044 0x801f 0x4>, + <0xf804c 0x8007 0x1>, + <0xfc004 0x3 0x2>, + <0xfc008 0x801f 0x4>, + <0xfc010 0x7 0x4>, + <0xfc014 0x801f 0x4>, + <0xfc01c 0x7 0x4>, + <0xfc020 0x801f 0x4>, + <0xfc028 0x7 0x4>, + <0xfc02c 0x801f 0x4>, + <0xfc034 0x7 0x4>, + <0xfc038 0x801f 0x4>, + <0xfc040 0x3 0x2>, + <0xfc044 0x801f 0x4>, + <0xfc04c 0x8007 0x1>, + <0x4000 0x1000000f 0x10000002>, + <0x4004 0x1000000f 0x10000002>, + <0x4008 0x1000000f 0x10000002>, + <0x400c 0x1000000f 0x10000002>, + <0x4010 0x1000000f 0x10000002>, + <0x4014 0x1000000f 0x10000002>, + <0x4018 0x1000000f 0x10000002>, + <0x401c 0x1000000f 0x10000002>, + <0x4020 0x1000000f 0x10000002>, + <0x4024 0x1000000f 0x10000002>, + <0x4028 0x1000000f 0x10000002>, + <0x402c 0x1000000f 0x10000002>, + <0x4040 0x1000000f 0x10000002>, + <0x4044 0x1000000f 0x10000002>, + <0x4048 0x1000000f 0x10000002>, + <0x404c 0x1000000f 0x10000002>, + <0x4050 0x1000000f 0x10000002>, + <0x4054 0x1000000f 0x10000002>, + <0x4058 0x1000000f 0x10000002>, + <0x405c 0x1000000f 0x10000002>, + <0x4060 0x1000000f 0x10000002>, + <0x4064 0x1000000f 0x10000002>, + <0x4068 0x1000000f 0x10000002>, + <0x406c 0x1000000f 0x10000002>, + <0x4080 0x1000000f 0x10000002>, + <0x4084 0x1000000f 0x10000002>, + <0x4088 0x1000000f 0x10000002>, + <0x408c 0x1000000f 0x10000002>, + <0x4090 0x1000000f 0x10000002>, + <0x4094 0x1000000f 0x10000002>, + <0x4098 0x1000000f 0x10000002>, + <0x409c 0x1000000f 0x10000002>, + <0x40a0 0x1000000f 0x10000002>, + <0x40a4 0x1000000f 0x10000002>, + <0x40a8 0x1000000f 0x10000002>, + <0x40ac 0x1000000f 0x10000002>, + <0x40c0 0x1000000f 0x10000002>, + <0x40c4 0x1000000f 0x10000002>, + <0x40c8 0x1000000f 0x10000002>, + <0x40cc 0x1000000f 0x10000002>, + <0x40d0 0x1000000f 0x10000002>, + <0x40d4 0x1000000f 0x10000002>, + <0x40d8 0x1000000f 0x10000002>, + <0x40dc 0x1000000f 0x10000002>, + <0x40e0 0x1000000f 0x10000002>, + <0x40e4 0x1000000f 0x10000002>, + <0x40e8 0x1000000f 0x10000002>, + <0x40ec 0x1000000f 0x10000002>, + <0x4100 0x1000000f 0x10000002>, + <0x4104 0x1000000f 0x10000002>, + <0x4108 0x1000000f 0x10000002>, + <0x410c 0x1000000f 0x10000002>, + <0x4110 0x1000000f 0x10000002>, + <0x4114 0x1000000f 0x10000002>, + <0x4118 0x1000000f 0x10000002>, + <0x411c 0x1000000f 0x10000002>, + <0x4120 0x1000000f 0x10000002>, + <0x4124 0x1000000f 0x10000002>, + <0x4128 0x1000000f 0x10000002>, + <0x412c 0x1000000f 0x10000002>, + <0x4140 0x1000000f 0x10000002>, + <0x4144 0x1000000f 0x10000002>, + <0x4148 0x1000000f 0x10000002>, + <0x414c 0x1000000f 0x10000002>, + <0x4150 0x1000000f 0x10000002>, + <0x4154 0x1000000f 0x10000002>, + <0x4158 0x1000000f 0x10000002>, + <0x415c 0x1000000f 0x10000002>, + <0x4160 0x1000000f 0x10000002>, + <0x4164 0x1000000f 0x10000002>, + <0x4168 0x1000000f 0x10000002>, + <0x416c 0x1000000f 0x10000002>, + <0x43e4 0x7 0x7>; + apple,thunderbolt-drom = [c8 01 00 00 00 00 00 00 00 e8 61 95 b3 00 5c 00 + 00 00 00 00 00 00 08 81 81 02 81 00 00 00 08 82 + 91 01 81 00 00 00 03 83 20 08 84 00 00 00 00 00 + 00 08 85 00 00 00 00 00 00 05 86 09 01 00 08 87 + 00 00 00 00 00 00 05 88 09 01 00 05 89 09 01 00 + 05 8a 09 01 00 0e 01 41 70 70 6c 65 2c 20 49 6e + 63 2e 00 06 02 69 4f 53 00 00 00 00]; +}; + +/* The tunnel's tunables: this board's, equal to ATC2's */ +&apciec1_dart { + apple,tunable = <0x20c 0x80000121 0x80000121>, + <0x220 0xf0f 0xf0f>, + <0x224 0xffff 0x909>, + <0x300 0x1f31 0x1>, + <0x308 0x3ffffffc 0x10000000>, + <0x310 0x3ffffffc 0x3ffffffc>; +}; + +&apciec1 { + apple,tunable-debug = <0x1000 0x1 0x0>; + apple,tunable-rc = <0x78 0x7000 0x0>, + <0x718 0x7c000 0x0>, + <0x814 0xffffffff 0x2020f060>, + <0x8bc 0x1 0x0>; + apple,tunable-fabric = <0x4 0x3f003f 0x240024>, + <0x8 0x1 0x1>, + <0xc 0x1 0x1>, + <0x10 0x801f 0x4>, + <0x18 0x1ff 0x1e0>, + <0x1c 0x1 0x1>, + <0x20 0x801f 0x4>, + <0x28 0x1f 0x10>, + <0x2c 0x801f 0x4>, + <0x34 0x3f 0x20>, + <0x38 0x801f 0x4>, + <0x40 0x3f 0x20>, + <0x44 0x801f 0x4>, + <0x4c 0x10001 0x10001>, + <0x50 0x1 0x1>, + <0x54 0x1 0x1>, + <0x58 0x801f 0x4>, + <0x60 0x7f007f 0x450045>, + <0x64 0x801f 0x4>, + <0x6c 0x1f001f 0x100010>, + <0x70 0xf1 0x1>, + <0x74 0x801f 0x4>, + <0x7c 0x801f 0x4>, + <0x84 0x1 0x1>, + <0x88 0x1 0x1>, + <0x8c 0x801f 0x4>, + <0x94 0x1 0x1>, + <0x98 0x801f 0x4>, + <0xa0 0x1 0x1>, + <0xa4 0x801f 0x4>, + <0xac 0x1 0x1>, + <0xb0 0x1 0x1>, + <0xb4 0x801f 0x4>, + <0xbc 0x801f 0x4>, + <0xc4 0x801f 0x4>; +}; + +&apciec1_port { + apple,tunable = <0x140 0x1 0x1>, + <0x2a0 0x7e 0xa>; +}; diff --git a/arch/arm64/boot/dts/apple/t6050-j714s.dts b/arch/arm64/boot/dts/apple/t6050-j714s.dts index b6c7675864b9..05ab1405599b 100644 --- a/arch/arm64/boot/dts/apple/t6050-j714s.dts +++ b/arch/arm64/boot/dts/apple/t6050-j714s.dts @@ -421,6 +421,9 @@ 63 2e 00 06 02 69 4f 53 00 00 00 00]; }; +/* Left-front port (ATC1): the USB4/Thunderbolt router and its PCIe tunnel */ +#include "t6050-j714s-left-usb4.dtsi" + /* * The PMP (ADT pmp0, /chosen, /arm-io/pmgr). iBoot loads its firmware and the driver starts it * with these boot arguments and the firmware properties below. Its report tells it which devices diff --git a/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi b/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi index 596ed95d4501..2f4da05c29b1 100644 --- a/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi +++ b/arch/arm64/boot/dts/apple/t6050-peripherals.dtsi @@ -1528,7 +1528,7 @@ status = "disabled"; }; -#ifndef T6050_J716C +#if !defined(T6050_J714S) && !defined(T6050_J716C) apciec1_dart: iommu@2ac000000 { compatible = "apple,t6050-dart", "apple,t8110-dart"; reg = <0x2 0xac000000 0x0 0x20000>;