From f8c7547ef29eae71436808226b86601f7d112f80 Mon Sep 17 00:00:00 2001 From: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> Date: Mon, 9 Nov 2026 09:47:08 +1100 Subject: [PATCH] arm64: dts: apple: j616s: enable USB4/Thunderbolt on the left front and right ports Enable ACIO1 (typec1, left front) and ACIO2 (typec2, right) the same way as ACIO0: router, its DART with the ACIO0 DVA window, NHI, mailbox and power domains, PCIe tunnel off. The routers' resets, LSTX pins, ring interrupts and Type-C graph links are already described. The loader hands every router its tuning and DROM. Assisted-by: LLM Signed-off-by: Ryan Murray <81541646+RyanTheTide@users.noreply.github.com> --- arch/arm64/boot/dts/apple/t6040-j616s.dts | 77 ++++++++++++++++++++++- 1 file changed, 74 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t6040-j616s.dts b/arch/arm64/boot/dts/apple/t6040-j616s.dts index 0e29b6291ed9f..0d7c60454d480 100644 --- a/arch/arm64/boot/dts/apple/t6040-j616s.dts +++ b/arch/arm64/boot/dts/apple/t6040-j616s.dts @@ -167,9 +167,10 @@ }; /* - * USB4/Thunderbolt on the left back port (typec0, ACIO0). The loader hands - * the router, adapter and NHI tuning and the DROM over. No PCIe tunnel yet: - * host-to-host (XDomain, thunderbolt-net) and USB4 links only. + * USB4/Thunderbolt on all three Type-C ports: typec0 (left back, ACIO0), + * typec1 (left front, ACIO1) and typec2 (right, ACIO2). The loader hands + * each router its router, adapter and NHI tuning and its DROM over. No PCIe + * tunnels yet: host-to-host (XDomain, thunderbolt-net) and USB4 links only. */ &pmgr_cio { status = "okay"; @@ -209,3 +210,73 @@ &usb4_0_nhi { status = "okay"; }; + +&ps_atc1_cio { + status = "okay"; +}; + +&ps_atc1_pcie { + status = "okay"; +}; + +&ps_atc1_cio_pcie { + status = "okay"; +}; + +&ps_atc1_cio_usb { + status = "okay"; +}; + +&usb4_1_mbox { + status = "okay"; +}; + +&usb4_1_acio { + /delete-property/ apple,pcie-tunnel; + status = "okay"; +}; + +&usb4_1_dart { + /* The same DVA window as the ACIO0 router DART. */ + apple,dma-range = <0x100 0x4000 0x0 0xffff0000>; + status = "okay"; +}; + +&usb4_1_nhi { + status = "okay"; +}; + +&ps_atc2_cio { + status = "okay"; +}; + +&ps_atc2_pcie { + status = "okay"; +}; + +&ps_atc2_cio_pcie { + status = "okay"; +}; + +&ps_atc2_cio_usb { + status = "okay"; +}; + +&usb4_2_mbox { + status = "okay"; +}; + +&usb4_2_acio { + /delete-property/ apple,pcie-tunnel; + status = "okay"; +}; + +&usb4_2_dart { + /* The same DVA window as the ACIO0 router DART. */ + apple,dma-range = <0x100 0x4000 0x0 0xffff0000>; + status = "okay"; +}; + +&usb4_2_nhi { + status = "okay"; +};