From 4ab73fc57fe9a5aeac2caf2bd3c455b9fc246820 Mon Sep 17 00:00:00 2001 From: Kevin Zhuang Date: Sun, 20 Sep 2026 05:15:42 +0000 Subject: [PATCH 1/4] arm64: dts: rockchip: mixtile-blade3: rename the DT and fix the power tree, supplies and suspend Rename rk3588-blade3-v101-linux.dts to rk3588-mixtile-blade3.dts and drop the PCB revision from the board identity. The file describes the Blade 3 as a product, not one PCB spin: model "Mixtile Blade 3 v1.0.1" -> "Mixtile Blade 3" compatible "rockchip,rk3588-blade3-v101-linux" -> "mixtile,blade3" The DTB name changes with it. armbian/build still points the vendor branch at rockchip/rk3588-blade3-v101-linux.dtb in config/boards/mixtile-blade3.csc and needs a matching update; its edge branch already uses rockchip/rk3588-mixtile-blade3.dtb. The rest is a review of the file against the Blade 3 schematic rev V1.1.0. Power tree. The board takes a 12-20V PD/barrel input rather than a fixed 12V rail, and the RK806 and the three RK860x are fed from the 4.0V buck, not from VCC5V0_SYS. Add vin_12_20v and vcc4v0_sys and repoint the consumers, including the RK806 vcc1..vcc10, vcc12 and vcca inputs, which had no supply at all. Drop vcc5v0_usbdcin and vcc5v0_usb, which described rails the board does not have, and the four pcie*_avdd* fixed regulators, which duplicated PMIC outputs and had no consumer. Add vcc3v3_minipcie on GPIO3_C6 and give pcie2x1l1 a vpcie3v3-supply. vcc_3v3_sd_s0 is enabled by a low level on GPIO0_B7 but carried enable-active-high and no voltage constraints; fix the polarity and add the constraints, the startup delay and the vcc_3v3_s3 parent. Supplies. Add venc-supply and mem-supply to rkvenc0 and rkvenc1 and vop-supply to vop. Without them rockchip_init_opp_table() finds no regulator through regulator_get_optional(), so no OPP table is built and both blocks stay at their boot voltage. saradc takes its reference from AVCC_1V8_S0, not VCC_1V8_S0. Memory. The cma node pinned the 256MB pool at a fixed address through reg; use size and let the allocator place it. Buses and peripherals. J7 routes i2c3 with external pull-ups; add it with a matching pinctrl group. Add i2c7 and i2c8. can2 has no transceiver on this board, and leaving it enabled only muxes two expansion-header pins away from GPIO, so disable it. Drop the i2s0_8ch node and the duplicate hdptxphy0 node. Use gpu_panthor. Make cec-enable the boolean it is rather than a string, and spell status = "disabled" correctly on the mini-PCIe USB3 combo nodes. Suspend. Replace the raw 0x4000024 with the RKPM_SLP_* macros. The board has no external 32.768kHz oscillator, so RKPM_SLP_32K_EXT must not be set; ARMOFF_DDRPD, PMU_PMUALIVE_32K and PMU_DIS_OSC remain. Rename the fan pinctrl groups to match the rest of the file and drop the unreferenced vcc5v0_host_en group and a commented-out pwrkey node. Also add a metadata node to the mixtile-blade3-sata2 overlay, so it shows up with a description in the overlay picker, and add a new mixtile-blade3-camera-imx415 overlay for the J7 FPC connector. Signed-off-by: Kevin Zhuang --- arch/arm64/boot/dts/rockchip/Makefile | 2 +- arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 + .../overlay/mixtile-blade3-camera-imx415.dts | 237 ++++++++++++++ .../rockchip/overlay/mixtile-blade3-sata2.dts | 8 + ...01-linux.dts => rk3588-mixtile-blade3.dts} | 303 +++++++++--------- 5 files changed, 393 insertions(+), 158 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-camera-imx415.dts rename arch/arm64/boot/dts/rockchip/{rk3588-blade3-v101-linux.dts => rk3588-mixtile-blade3.dts} (83%) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d54b28b3fedae..2b61dcf65cecb 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -532,7 +532,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-aim7-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-bananapi-m7.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blade3-v101-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v12-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v12-maizhuo-linux.dtb @@ -548,6 +547,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-fxblox-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-hinlink-h88k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mixtile-blade3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mixtile-core3588e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6-lts-plus.dtb diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index 37e6f70063ea0..d5aeb6adeff7d 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -109,6 +109,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ radxa-nx5-io-rpi-camera-v2-cam1.dtbo \ rk3588s-roc-pc-sata0.dtbo \ turing-rk1-sata2.dtbo \ + mixtile-blade3-camera-imx415.dtbo \ mixtile-blade3-sata2.dtbo \ radxa-zero3-rpi-camera-v2.dtbo \ radxa-zero3-rpi-camera-v1.3.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-camera-imx415.dts b/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-camera-imx415.dts new file mode 100644 index 0000000000000..17afd093c054e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-camera-imx415.dts @@ -0,0 +1,237 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title = "Enable IMX415 camera on CSI0"; + compatible = "mixtile,blade3"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable a Sony IMX415 camera module on the J7 FPC connector."; + }; + + fragment@0 { + target-path = "/"; + + __overlay__ { + /* generated on the module from the J7 3.3V/5V pins */ + vcc_cam_avdd: vcc-cam-avdd { + compatible = "regulator-fixed"; + regulator-name = "vcc_cam_avdd"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + fragment@1 { + target = <&i2c3>; + + __overlay__ { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera2_clk &cam_ctl_pins>; + power-domains = <&power RK3588_PD_VI>; + reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + power-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_cam_avdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + status = "okay"; + + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + }; + }; + + fragment@2 { + target = <&pinctrl>; + + __overlay__ { + cam { + cam_ctl_pins: cam-ctl-pins { + rockchip,pins = + <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + }; + }; + + fragment@3 { + target = <&csi2_dphy0_hw>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&csi2_dphy0>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@5 { + target = <&mipi2_csi2>; + + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@6 { + target = <&rkcif>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&rkcif_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@8 { + target = <&rkcif_mipi_lvds2>; + + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@9 { + target = <&rkcif_mipi_lvds2_sditf>; + + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@10 { + target = <&rkisp0>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@11 { + target = <&isp0_mmu>; + + __overlay__ { + status = "okay"; + }; + }; + + fragment@12 { + target = <&rkisp0_vir0>; + + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-sata2.dts b/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-sata2.dts index c68e11dc16049..fcaa8eb42a3fe 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-sata2.dts +++ b/arch/arm64/boot/dts/rockchip/overlay/mixtile-blade3-sata2.dts @@ -2,6 +2,14 @@ /plugin/; / { + metadata { + title = "mini-PCIe socket as SATA"; + compatible = "mixtile,blade3"; + category = "misc"; + exclusive = "combphy2_psu"; + description = "Enable SATA2 on the mini-PCIe socket.\nWhen SATA2 is enabled, PCIe cannot be enabled on the same port."; + }; + fragment@0 { target = <&pcie2x1l1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-blade3.dts similarity index 83% rename from arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts rename to arch/arm64/boot/dts/rockchip/rk3588-mixtile-blade3.dts index 9a4c535f3f6dc..67402ad155946 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-blade3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2022 Mixtile Limited + * Copyright (c) 2026 Mixtile Limited * */ @@ -20,8 +20,8 @@ #include "rk3588-linux.dtsi" / { - model = "Mixtile Blade 3 v1.0.1"; - compatible = "rockchip,rk3588-blade3-v101-linux", "rockchip,rk3588"; + model = "Mixtile Blade 3"; + compatible = "mixtile,blade3", "rockchip,rk3588"; /delete-node/ chosen; aliases { @@ -39,7 +39,7 @@ cma { compatible = "shared-dma-pool"; reusable; - reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + size = <0x0 (256 * 0x100000)>; linux,cma-default; }; }; @@ -86,64 +86,27 @@ rockchip,jack-det; }; - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - vcc3v3_pcie30: vcc3v3-pcie30 { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie30"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; + vin-supply = <&vcc4v0_sys>; }; vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + startup-delay-us = <2000>; pinctrl-names = "default"; pinctrl-0 = <&sd_s0_pwr>; - regulator-name = "vcc_3v3_sd_s0"; - enable-active-high; + vin-supply = <&vcc_3v3_s3>; }; vbus5v0_typec0: vbus5v0-typec0 { @@ -153,9 +116,9 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; pinctrl-names = "default"; pinctrl-0 = <&typec5v_pwren0>; + vin-supply = <&vcc5v0_sys>; }; vbus5v0_typec1: vbus5v0-typec1 { @@ -165,18 +128,41 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; pinctrl-names = "default"; pinctrl-0 = <&typec5v_pwren1>; + vin-supply = <&vcc5v0_sys>; + }; + + vin_12_20v: vin-12-20v { + compatible = "regulator-fixed"; + regulator-name = "vin_12_20v"; + regulator-boot-on; + regulator-always-on; }; - vcc12v_dcin: vcc12v-dcin { + vcc4v0_sys: vcc4v0-sys { compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; + regulator-name = "vcc4v0_sys"; + regulator-boot-on; regulator-always-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vin_12_20v>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_minipcie"; regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pwren>; + vin-supply = <&vin_12_20v>; }; vcc5v0_fan: vcc5v0-fan { @@ -187,63 +173,41 @@ enable-active-high; gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&fan_en_pin>; + pinctrl-0 = <&fan_pwren>; vin-supply = <&vcc5v0_sys>; }; vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; + vin-supply = <&vin_12_20v>; }; vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { compatible = "regulator-fixed"; regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc4v0_sys>; }; fan: pwm-fan { compatible = "pwm-fan"; - interrupt-parent = <&gpio3>; interrupts = ; pulses-per-revolution = <2>; - #cooling-cells = <2>; + cooling-levels = <0 35 70 100 125 150>; pwms = <&pwm8 0 40000 0>; /* 40000 meant for Noctua */ - fan-supply = <&vcc5v0_fan>; pinctrl-names = "default"; - pinctrl-0 = <&fan_tach_pin>; /* for the pull-up on the tacho input */ - cooling-levels = <0 35 70 100 125 150>; + pinctrl-0 = <&fan_tach>; /* for the pull-up on the tacho input */ + fan-supply = <&vcc5v0_fan>; rockchip,temp-trips = < 30000 1 45000 2 @@ -251,13 +215,9 @@ 55000 4 60000 5 >; - }; + }; }; -/*&pwrkey { - status = "disabled"; -};*/ - &av1d { status = "okay"; }; @@ -285,20 +245,11 @@ mem-supply = <&vdd_cpu_big1_mem_s0>; }; -&gpu { +&gpu_panthor { mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; status = "okay"; }; -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - &i2s7_8ch { status = "okay"; }; @@ -418,6 +369,8 @@ }; &rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; status = "okay"; }; @@ -426,6 +379,8 @@ }; &rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; status = "okay"; }; @@ -436,12 +391,18 @@ &rockchip_suspend { status = "okay"; rockchip,sleep-debug-en = <1>; - rockchip,sleep-mode-config = <0x4000024>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + ) + >; }; &saradc { status = "okay"; - vref-supply = <&vcc_1v8_s0>; + vref-supply = <&avcc_1v8_s0>; }; &sdhci { @@ -499,7 +460,7 @@ rockchip,typec-vbus-det; }; -&u2phy2_host { // 30PIN GPIO +&u2phy2_host { status = "okay"; }; @@ -523,12 +484,12 @@ status = "okay"; }; -&usbhost3_0 { // miniPCIe combo - status = "disable"; +&usbhost3_0 { + status = "disabled"; }; -&usbhost_dwc3_0 { // miniPCIe combo - status = "disable"; +&usbhost_dwc3_0 { + status = "disabled"; }; &usbdp_phy0 { @@ -566,7 +527,7 @@ status = "okay"; orientation-switch; - svid = <0xff01>; // linux/usb/typec_dp.h:USB_TYPEC_DP_SID + svid = <0xff01>; sbu1-dc-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; sbu2-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; @@ -590,7 +551,6 @@ }; &usbdp_phy1_u3 { - maximum-speed = "high-speed"; status = "okay"; }; @@ -599,9 +559,9 @@ }; &usbdrd_dwc3_0 { - dr_mode = "otg"; status = "okay"; + dr_mode = "otg"; usb-role-switch; port { #address-cells = <1>; @@ -647,6 +607,7 @@ &vop { assigned-clocks = <&cru ACLK_VOP>; assigned-clock-rates = <800000000>; + vop-supply = <&vdd_log_s0>; status = "okay"; }; @@ -700,7 +661,7 @@ }; &spdif_tx2 { - status = "okay"; + status = "okay"; }; &dp1 { @@ -712,13 +673,13 @@ }; &spdif_tx5 { - status = "okay"; + status = "okay"; }; &hdmi0 { enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + cec-enable; status = "okay"; - cec-enable = "true"; }; &hdmi0_in_vp0 { @@ -728,20 +689,14 @@ /* Should work with at least 128MB cma reserved above. */ &hdmirx_ctrler { status = "okay"; - #sound-dai-cells = <1>; /* Effective level used to trigger HPD: 0-low, 1-high */ hpd-trigger-level = <1>; hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; pinctrl-names = "default"; }; -&hdptxphy0 { - status = "okay"; -}; - &i2c0 { status = "okay"; pinctrl-names = "default"; @@ -750,7 +705,7 @@ vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { compatible = "rockchip,rk8602"; reg = <0x42>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc4v0_sys>; regulator-compatible = "rk860x-reg"; regulator-name = "vdd_cpu_big0_s0"; regulator-min-microvolt = <550000>; @@ -767,7 +722,7 @@ vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { compatible = "rockchip,rk8603"; reg = <0x43>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc4v0_sys>; regulator-compatible = "rk860x-reg"; regulator-name = "vdd_cpu_big1_s0"; regulator-min-microvolt = <550000>; @@ -790,7 +745,7 @@ vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { compatible = "rockchip,rk8602"; reg = <0x42>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc4v0_sys>; regulator-compatible = "rk860x-reg"; regulator-name = "vdd_npu_s0"; regulator-min-microvolt = <550000>; @@ -835,7 +790,6 @@ faster-pd-negotiation; op-sink-microwatt = <15000000>; sink-pdos = - // ; ; @@ -875,12 +829,17 @@ }; }; -&i2c4 { // U.2 port +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3m3_xfer_pull_up>; +}; + +&i2c4 { status = "okay"; pinctrl-0 = <&i2c4m0_xfer>; }; -&i2c6 { // USB Type-C 0 +&i2c6 { status = "okay"; pinctrl-0 = <&i2c6m0_xfer>; @@ -916,7 +875,7 @@ sink-pdos = ; source-pdos = - ; + ; altmodes { #address-cells = <1>; @@ -951,51 +910,58 @@ }; }; -&i2c5 { // 30PIN GPIO +&i2c7 { status = "okay"; - pinctrl-0 = <&i2c5m3_xfer>; + pinctrl-0 = <&i2c7m3_xfer>; }; -&pwm8 { // 30PIN GPIO - pinctrl-names = "active"; +&i2c8 { status = "okay"; - pinctrl-0 = <&pwm8m2_pins>; + pinctrl-0 = <&i2c8m4_xfer>; }; -&pwm14 { // 30PIN GPIO +&pwm8 { status = "okay"; - pinctrl-0 = <&pwm14m2_pins>; + pinctrl-0 = <&pwm8m2_pins>; }; -&pwm15 { // 30PIN GPIO +&can2 { status = "disabled"; - pinctrl-0 = <&pwm15m3_pins>; }; -&spi4 { // 30PIN GPIO +&i2c5 { status = "okay"; + pinctrl-0 = <&i2c5m3_xfer>; +}; +&i2s2_2ch { + status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>; - num-cs = <1>; + pinctrl-0 = <&i2s2m1_mclk + &i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; }; -&i2s2_2ch { // 30PIN GPIO +&pwm14 { status = "okay"; + pinctrl-0 = <&pwm14m2_pins>; +}; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_mclk - &i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; +&pwm15 { + status = "okay"; + pinctrl-0 = <&pwm15m3_pins>; }; -&can2 { // 30PIN GPIO +&spi4 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>; + num-cs = <1>; }; -&pcie2x1l0 { // combphy1, to ASM1182e +&pcie2x1l0 { reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -1057,29 +1023,30 @@ }; }; -&pcie2x1l1 { // combphy2, to miniPCIe socket +&pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; status = "okay"; }; &pcie30phy { -rockchip,pcie30-phymode = ; /* P1:PCIe3x2 + P0:PCIe3x2 */ -status = "okay"; + rockchip,pcie30-phymode = ; + status = "okay"; }; &pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; }; &pinctrl { fan { - fan_tach_pin: fan-tach-pin { + fan_tach: fan-tach { rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; - fan_en_pin: fan-en-pin { + fan_pwren: fan-pwren { rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -1090,9 +1057,16 @@ status = "okay"; }; }; - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + i2c3 { + i2c3m3_xfer_pull_up: i2c3m3-xfer-pull-up { + rockchip,pins = <2 RK_PB2 9 &pcfg_pull_up_smt>, + <2 RK_PB3 9 &pcfg_pull_up_smt>; + }; + }; + + minipcie { + minipcie_pwren: minipcie-pwren { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -1121,6 +1095,21 @@ status = "okay"; }; }; +&rk806single { + vcc1-supply = <&vcc4v0_sys>; + vcc2-supply = <&vcc4v0_sys>; + vcc3-supply = <&vcc4v0_sys>; + vcc4-supply = <&vcc4v0_sys>; + vcc5-supply = <&vcc4v0_sys>; + vcc6-supply = <&vcc4v0_sys>; + vcc7-supply = <&vcc4v0_sys>; + vcc8-supply = <&vcc4v0_sys>; + vcc9-supply = <&vcc4v0_sys>; + vcc10-supply = <&vcc4v0_sys>; + vcc12-supply = <&vcc4v0_sys>; + vcca-supply = <&vcc4v0_sys>; +}; + &route_hdmi0 { status = "okay"; }; From b26ca807aad9f782cb3cb3bbe4909a5a1c8f2ab4 Mon Sep 17 00:00:00 2001 From: Kevin Zhuang Date: Sun, 20 Sep 2026 05:15:42 +0000 Subject: [PATCH 2/4] arm64: dts: rockchip: mixtile-core3588e: fix SD, USB 3.1, DP and suspend Review the Core3588E board file against the module schematic. The Core3588E is a Jetson-Nano-compatible SoM, so everything described here is on the module itself or on the pins it brings out on the 260-pin connector. Displays and audio. Add a dp-connector for the DP output carried on edp1 and wire it up through a new edp1 port@1, and add the rockchip-edp1-sound card fed from spdif_tx4. Rename the HDMI card to rockchip-hdmi0-sound to match. Add vcc_hdmi on GPIO0_C4, and move the HDMI HPD pin to hdmim1_tx0_hpd, which is the group the module routes. Storage. The SD card interface is wired 4-bit with no card-detect line, so use bus-width = <4> with the sdmmc_bus4 group, add broken-cd and drop the cd-gpios and the sdmmc_det group. Add no-sdio, no-mmc, cap-sd-highspeed and sd-uhs-sdr104 to describe what the slot supports. USB. The module brings out the second USB 3.1 controller, not the USB 2.0 host pair, so enable usbdrd3_1 and usbdrd_dwc3_1 and drop the u2phy3, u2phy3_host, usb_host1_ehci and usb_host1_ohci nodes. Suspend. Replace the raw 0x4000024 sleep-mode-config with the RKPM_SLP_* macros and add a wakeup-config of RKPM_GPIO_WKUP_EN and RKPM_CPU0_WKUP_EN. Keep vdd_log_s0 up across suspend by deleting the off-in-suspend and suspend-microvolt properties it inherits and setting regulator-on-in-suspend instead; the logic rail has to stay alive for the DDR to be self-refreshed with the PD off. Also: use gpu_panthor; take the saradc reference from AVCC_1V8_S0; give the SPI controller its second chip select and a spidev for each; replace the adc-keys node, which described keys this board does not have, with a recovery gpio-key, and add sys_status_led; drop pcie2x1l1, which is not routed on the module; and drop the hdmirx CMA reservation and the unused dt-bindings/usb/pd.h include. The two IMX219 camera overlays are the RPi camera v2 configurations for the CAM0 and CAM1 FPC connectors on the carrier. CAM0 is GPIO3_C4 PWDN with MIPI_CAM0_MCLK_M1 on GPIO3_A5 and the CSI0 lanes; CAM1 is GPIO3_C5 with MIPI_CAM1_MCLK_M1 on GPIO3_A6 and the CSI2 lanes. Signed-off-by: Kevin Zhuang --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 2 + .../mixtile-core3588e-camera-imx219-cam0.dts | 235 ++++++++++++++++ .../mixtile-core3588e-camera-imx219-cam1.dts | 226 +++++++++++++++ .../dts/rockchip/rk3588-mixtile-core3588e.dts | 259 ++++++++---------- 4 files changed, 578 insertions(+), 144 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam0.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam1.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index d5aeb6adeff7d..6b52c62f3b1d5 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -111,6 +111,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ turing-rk1-sata2.dtbo \ mixtile-blade3-camera-imx415.dtbo \ mixtile-blade3-sata2.dtbo \ + mixtile-core3588e-camera-imx219-cam0.dtbo \ + mixtile-core3588e-camera-imx219-cam1.dtbo \ radxa-zero3-rpi-camera-v2.dtbo \ radxa-zero3-rpi-camera-v1.3.dtbo \ radxa-zero3-external-antenna.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam0.dts b/arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam0.dts new file mode 100644 index 0000000000000..23128d480a728 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam0.dts @@ -0,0 +1,235 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title = "Enable IMX219 camera on CAM0"; + compatible = "mixtile,core3588e"; + category = "camera"; + exclusive = "csi2_dphy0"; + description = "Enable a Sony IMX219 camera module on CAM0."; + }; + + fragment@0 { + target-path = "/"; + __overlay__ { + camera0_pwdn_gpio: camera0-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera0_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + i2cmux1:i2cmux1 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c2>; + mux-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + + i2c_cam0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c2>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + }; + }; + + fragment@2 { + target = <&i2cmux1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&isp0_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c_cam0>; + __overlay__ { + camera0_imx219: camera0-imx219@10 { + status = "okay"; + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M0>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera0_clk>; + power-domains = <&power RK3588_PD_VI>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + }; + + fragment@8 { + target = <&csi2_dphy0>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx219_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; + }; + }; + + fragment@9 { + target = <&csi2_dphy0_hw>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&mipi2_csi2>; + __overlay__ { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; + }; + }; + + fragment@11 { + target = <&rkcif_mipi_lvds2>; + __overlay__ { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; + }; + }; + + fragment@12 { + target = <&rkcif_mipi_lvds2_sditf>; + __overlay__ { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; + }; + }; + + fragment@13 { + target = <&rkisp0_vir0>; + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam1.dts b/arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam1.dts new file mode 100644 index 0000000000000..fcbfc416676cd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/mixtile-core3588e-camera-imx219-cam1.dts @@ -0,0 +1,226 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +/ { + metadata { + title = "Enable IMX219 camera on CAM1"; + compatible = "mixtile,core3588e"; + category = "camera"; + exclusive = "csi2_dcphy0"; + description = "Enable a Sony IMX219 camera module on CAM1."; + }; + + fragment@0 { + target-path = "/"; + __overlay__ { + camera1_pwdn_gpio: camera1-pwdn-gpio { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "camera1_pwdn_gpio"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + + i2cmux1:i2cmux1 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c2>; + mux-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + + i2c_cam1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + fragment@1 { + target = <&i2c2>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + }; + }; + + fragment@2 { + target = <&i2cmux1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@3 { + target = <&rkcif>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@4 { + target = <&rkcif_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@5 { + target = <&rkisp1>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@6 { + target = <&isp1_mmu>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@7 { + target = <&i2c_cam1>; + __overlay__ { + camera1_imx219: camera1-imx219@10 { + status = "okay"; + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + power-domains = <&power RK3588_PD_VI>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "rpi-camera-v2"; + rockchip,camera-module-lens-name = "default"; + + port { + imx219_out1: endpoint { + remote-endpoint = <&mipi_in_1_ucam0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + }; + }; + + fragment@8 { + target = <&csi2_dcphy0>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_1_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx219_out1>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; + }; + }; + + fragment@9 { + target = <&mipi_dcphy0>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@10 { + target = <&mipi0_csi2>; + __overlay__ { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; + }; + }; + + fragment@11 { + target = <&rkcif_mipi_lvds>; + __overlay__ { + status = "okay"; + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; + }; + }; + + fragment@12 { + target = <&rkcif_mipi_lvds_sditf>; + __overlay__ { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; + }; + }; + + fragment@13 { + target = <&rkisp1_vir0>; + __overlay__ { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts index 2ce379c523ebe..7a20ec364a06f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-core3588e.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2022 Mixtile Limited + * Copyright (c) 2026 Mixtile Limited * */ @@ -14,7 +14,6 @@ #include #include -#include "dt-bindings/usb/pd.h" #include "rk3588.dtsi" #include "rk3588-rk806-single.dtsi" #include "rk3588-linux.dtsi" @@ -35,81 +34,64 @@ spi1 = &spi0; }; - /* If hdmirx node is disabled, delete the reserved-memory node here. */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ - cma { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; - linux,cma-default; - }; - }; - - adc_keys: adc-keys { + recovery_key: recovery-key { compatible = "adc-keys"; io-channels = <&saradc 1>; io-channel-names = "buttons"; keyup-threshold-microvolt = <1800000>; poll-interval = <100>; - vol-up-key { - label = "volume up"; + recovery { + label = "recovery"; linux,code = ; press-threshold-microvolt = <17000>; }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <890000>; - }; - - back-key { - label = "back"; - linux,code = ; - press-threshold-microvolt = <1235000>; - }; }; gpio-leds { compatible = "gpio-leds"; - pwr-led { + sys_status_led: sys-status-led { + label = "sys_status_led"; gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; default-state = "on"; linux,default-trigger = "heartbeat"; }; }; + dp-con { + compatible = "dp-connector"; + type = "full-size"; + status = "okay"; + + port { + dp_con_in_edp1: endpoint { + remote-endpoint = <&edp1_out_dp_con>; + }; + }; + }; + hdmi0_sound: hdmi0-sound { status = "okay"; compatible = "rockchip,hdmi"; rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; + rockchip,card-name = "rockchip-hdmi0-sound"; rockchip,cpu = <&i2s5_8ch>; rockchip,codec = <&hdmi0>; rockchip,jack-det; }; edp1_sound: edp1-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,card-name = "rockchip-edp1"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&edp1>; - rockchip,jack-det; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip-edp1-sound"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx4>; + }; + + simple-audio-card,codec { + sound-dai = <&edp1 1>; + }; }; pcie20_avdd0v85: pcie20-avdd0v85 { @@ -147,7 +129,6 @@ regulator-name = "pcie30_avdd1v8"; regulator-boot-on; regulator-always-on; - gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&avcc_1v8_s0>; @@ -156,20 +137,32 @@ vcc3v3_pcie30: vcc3v3-pcie30 { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie30"; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - regulator-always-on; gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; startup-delay-us = <10000>; vin-supply = <&vcc12v_dcin>; }; + vcc_hdmi: vcc-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vcc_hdmi"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + }; + vcc12v_dcin: vcc12v-dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; @@ -177,38 +170,18 @@ vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; - regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&vcc12v_dcin>; }; - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { compatible = "regulator-fixed"; regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; vin-supply = <&vcc5v0_sys>; @@ -258,9 +231,8 @@ mem-supply = <&vdd_cpu_big1_mem_s0>; }; -&gpu { +&gpu_panthor { mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; status = "okay"; }; @@ -393,12 +365,40 @@ &rockchip_suspend { status = "okay"; rockchip,sleep-debug-en = <1>; - rockchip,sleep-mode-config = <0x4000024>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_CPU0_WKUP_EN + ) + >; +}; + +&vdd_log_s0 { + regulator-state-mem { + /delete-property/ regulator-off-in-suspend; + /delete-property/ regulator-suspend-microvolt; + regulator-on-in-suspend; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + /delete-property/ regulator-off-in-suspend; + /delete-property/ regulator-suspend-microvolt; + regulator-on-in-suspend; + }; }; &saradc { status = "okay"; - vref-supply = <&vcc_1v8_s0>; + vref-supply = <&avcc_1v8_s0>; }; &sdhci { @@ -417,11 +417,16 @@ &sdmmc { max-frequency = <150000000>; - bus-width = <1>; + bus-width = <4>; + no-sdio; + no-mmc; + cap-sd-highspeed; + sd-uhs-sdr104; disable-wp; + broken-cd; vqmmc-supply = <&vccio_sd_s0>; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd>; status = "okay"; }; @@ -445,14 +450,6 @@ status = "okay"; }; -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - &usb_host0_ehci { status = "okay"; }; @@ -461,24 +458,12 @@ status = "okay"; }; -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - &usbhost3_0 { - status = "okay"; + status = "disabled"; }; &usbhost_dwc3_0 { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; + status = "disabled"; }; &u2phy1 { @@ -489,11 +474,11 @@ status = "okay"; }; -&usbdrd3_1{ +&usbdrd3_1 { status = "okay"; }; -&usbdrd_dwc3_1{ +&usbdrd_dwc3_1 { status = "okay"; }; @@ -574,27 +559,15 @@ clock-names = "hdmi0_phy_pll"; }; -&hdptxphy0 { - status = "okay"; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - &combphy1_ps { status = "okay"; }; -&combphy2_psu { +&spdif_tx2 { status = "okay"; }; -&spdif_tx2 { +&spdif_tx4 { status = "okay"; }; @@ -633,6 +606,8 @@ }; &hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim1_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; status = "okay"; }; @@ -656,8 +631,17 @@ pinctrl-names = "default"; pinctrl-0 = <&edp1_hpd>; hpd-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - //force-hpd; + #sound-dai-cells = <1>; status = "okay"; + + ports { + port@1 { + reg = <1>; + edp1_out_dp_con: endpoint { + remote-endpoint = <&dp_con_in_edp1>; + }; + }; + }; }; &edp1_in_vp2 { @@ -741,18 +725,19 @@ regulator-off-in-suspend; }; }; - }; -&i2c3 { +&i2c3 { status = "okay"; + pinctrl-names = "default"; pinctrl-0 = <&i2c3m0_xfer>; }; -&i2c4 { +&i2c4 { status = "okay"; + pinctrl-names = "default"; pinctrl-0 = <&i2c4m3_xfer>; - + hym8563: hym8563@51 { compatible = "haoyu,hym8563"; reg = <0x51>; @@ -760,7 +745,7 @@ clock-frequency = <32768>; clock-output-names = "hym8563"; pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; + pinctrl-0 = <&rtc_int>; interrupt-parent = <&gpio0>; interrupts = ; status = "okay"; @@ -773,7 +758,7 @@ pinctrl-0 = <&i2c5m2_xfer>; }; -&pwm2 { +&pwm2 { pinctrl-names = "active"; pinctrl-0 = <&pwm2m1_pins>; status = "okay"; @@ -783,11 +768,11 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0m3_cs1 &spi0m3_pins>; - num-cs = <1>; - - spi_dev@0 { + num-cs = <2>; + + spidev@1 { compatible = "rockchip,spidev"; - reg = <0>; + reg = <1>; spi-max-frequency = <50000000>; }; }; @@ -797,8 +782,8 @@ pinctrl-names = "default"; pinctrl-0 = <&spi1m2_cs0 &spi1m2_pins>; num-cs = <1>; - - spi_dev@0 { + + spidev@0 { compatible = "rockchip,spidev"; reg = <0>; spi-max-frequency = <50000000>; @@ -822,16 +807,11 @@ status = "okay"; }; -&pcie2x1l0 { +&pcie2x1l0 { reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; status = "okay"; }; -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - &pcie30phy { rockchip,pcie30-phymode = ; status = "okay"; @@ -840,19 +820,11 @@ &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x4m1_pins>; supports-clkreq; status = "okay"; }; &pinctrl { - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - edp { edp1_hpd: edp1-hpd { rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; @@ -971,7 +943,6 @@ /* GPIO3_D0-D3 */ "", "", "", "", /* GPIO3_D4-D7 */ - "", "", "", ""; }; From 812c30edddb329beecc57e8a46f5c47bd56add06 Mon Sep 17 00:00:00 2001 From: Kevin Zhuang Date: Sun, 20 Sep 2026 05:15:43 +0000 Subject: [PATCH 3/4] arm64: dts: rockchip: mixtile-edge2: switch Wi-Fi/BT to standard bindings and drop unused audio Review the Edge 2 board file against the schematic and switch it to the board's real identity. Identity. The compatible still carried focalcrest,mixtile-edge2 from before the product was named; use mixtile,edge2. Add the missing SPDX line. WiFi and Bluetooth. Replace the Rockchip-specific wlan-platdata and bluetooth-platdata nodes with the standard bindings: an sdio_pwrseq for the WiFi side and a bluetooth child node on uart8 using brcm,bcm43438-bt with shutdown, device-wakeup and host-wakeup GPIOs, max-speed and vddio-supply. Wire uart8 up with its CTS and RTS pins so the module's flow control works. The AP6275S takes its 32.768kHz LPO from Y8 on the board, not from RK809 CLK32KOUT2: R142, which would have connected clkout2 to the module, is DNP. Drop the clkout2 references, correct the comment that claimed otherwise, and drop rockchip,clk-32k-always-on, which made clk-rk808 register clkout2 as CLK_IS_CRITICAL. With no consumer on this board it only kept an unused output powered. This reverses commit 5aa56286b496 ("arm64: dts: rockchip: keep RK809 clkout2 on for WiFi on Mixtile Edge 2"), which read the LPO source from the device tree rather than from the board. Audio. Drop the audiopwmout_diff, pdm_mic_array, spdif-sound and vad_sound cards and the dummy codecs they used, and disable spdif_8ch, pdm and vad. None of those interfaces are brought out on this board. Add headphone detection on GPIO3_A7 to the remaining card. Regulators. Add m2_lane1_sel on GPIO1_D0, which selects between PCIe and USB 3.0 on the M.2 slot's second lane, and usb_hub_reset on GPIO3_B4. Rename vcc3v3_pcie to vcc3v3_pi6c, after the PI6C clock generator it actually powers, and point the PCIe controller's vpcie3v3-supply at vcc3v3_m2. Rename the vcc1v8_m2_pin pinctrl group to vcc1v8_m2_en, matching the vcc5v0_host_en naming already used here. eMMC. The device reports STROBE_SUPPORT and the data strobe is routed, so add mmc-hs400-1_8v and mmc-hs400-enhanced-strobe. USB. The OTG port is device-only on this board; set dr_mode to peripheral, give it its phy and cap it at high-speed. Also replace the adc-keys node with a recovery gpio-key and drop the generic RK3566/RK3568 IO-domain comment block. Add a mixtile-edge2-m2-usb3 overlay that flips m2_lane1_sel so the M.2 slot's second lane is USB 3.0 instead of PCIe. Signed-off-by: Kevin Zhuang --- arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 + .../overlay/mixtile-edge2-m2-usb3.dts | 26 + .../dts/rockchip/rk3568-mixtile-edge2.dts | 541 +++++++----------- 3 files changed, 247 insertions(+), 321 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/overlay/mixtile-edge2-m2-usb3.dts diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile index 6b52c62f3b1d5..9e18cdda2fec1 100644 --- a/arch/arm64/boot/dts/rockchip/overlay/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile @@ -113,6 +113,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ mixtile-blade3-sata2.dtbo \ mixtile-core3588e-camera-imx219-cam0.dtbo \ mixtile-core3588e-camera-imx219-cam1.dtbo \ + mixtile-edge2-m2-usb3.dtbo \ radxa-zero3-rpi-camera-v2.dtbo \ radxa-zero3-rpi-camera-v1.3.dtbo \ radxa-zero3-external-antenna.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlay/mixtile-edge2-m2-usb3.dts b/arch/arm64/boot/dts/rockchip/overlay/mixtile-edge2-m2-usb3.dts new file mode 100644 index 0000000000000..4b99133868447 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlay/mixtile-edge2-m2-usb3.dts @@ -0,0 +1,26 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title = "M.2 Key-B as USB 3.0"; + compatible = "mixtile,edge2"; + category = "misc"; + exclusive = "pcie3x2"; + description = "Route M.2 Key-B lane 1 to the USB 3.0 hub instead of PCIe.\nPCIe then trains x1 on lane 0; USB 2.0 is unaffected."; + }; + + /* Q16 inverts the mux SEL, so enable-active-high pulls SEL low and + * selects the hub's USB 3.0 outputs. */ + fragment@0 { + target = <&m2_lane1_sel>; + + __overlay__ { + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-mixtile-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3568-mixtile-edge2.dts index 5f7afad78d3f4..ce1156c069a9b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-mixtile-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-mixtile-edge2.dts @@ -1,3 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Mixtile Limited + * + */ + /dts-v1/; #include #include @@ -10,76 +16,37 @@ #include "rk3568-linux.dtsi" / { - model = "Mixtile Edge 2"; - compatible = "focalcrest,mixtile-edge2", "rockchip,rk3568"; + compatible = "mixtile,edge2", "rockchip,rk3568"; /delete-node/ chosen; leds: leds { compatible = "gpio-leds"; + work_led: work { gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - }; keys: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; status = "okay"; - button@0 { + recovery { gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - label = "GPIO Loader"; + label = "recovery"; linux,code = ; }; }; - audiopwmout_diff: audiopwmout-diff { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,audiopwmout-diff"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,bitclock-master = <&master>; - simple-audio-card,frame-master = <&master>; - simple-audio-card,cpu { - sound-dai = <&i2s3_2ch>; - }; - master: simple-audio-card,codec { - sound-dai = <&dig_acodec>; - }; - }; - - hdmi_sound: hdmi-sound { - status = "okay"; compatible = "rockchip,hdmi"; rockchip,mclk-fs = <128>; rockchip,card-name = "rockchip-hdmi-sound"; rockchip,cpu = <&i2s0_8ch>; rockchip,codec = <&hdmi>; - }; - - - pdmics: dummy-codec { - status = "disabled"; - compatible = "rockchip,dummy-codec"; - #sound-dai-cells = <0>; - }; - - pdm_mic_array: pdm-mic-array { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,pdm-mic-array"; - simple-audio-card,cpu { - sound-dai = <&pdm>; - }; - simple-audio-card,codec { - sound-dai = <&pdmics>; - }; + status = "okay"; }; reserved-memory { @@ -97,11 +64,15 @@ }; rk809_sound: rk809-sound { - status = "okay"; compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,name = "rockchip,rk809-codec"; simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = "Headphone", "Headphones"; + simple-audio-card,hp-det-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + status = "okay"; simple-audio-card,cpu { sound-dai = <&i2s1_8ch>; @@ -111,46 +82,20 @@ }; }; - spdif-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,name = "ROCKCHIP,SPDIF"; - simple-audio-card,cpu { - sound-dai = <&spdif_8ch>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - status = "okay"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - vad_sound: vad-sound { - status = "disabled"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip,rk3568-vad"; - rockchip,cpu = <&i2s1_8ch>; - rockchip,codec = <&rk809_codec>, <&vad>; - }; - dc_12v: dc-12v { compatible = "regulator-fixed"; regulator-name = "dc_12v"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; vcc2v5_sys: vcc2v5-ddr { compatible = "regulator-fixed"; - regulator-name = "vcc2v5-sys"; - regulator-always-on; + regulator-name = "vcc2v5_sys"; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; vin-supply = <&vcc3v3_sys>; @@ -159,8 +104,8 @@ vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&dc_12v>; @@ -169,8 +114,8 @@ vcc5v0_sys: vcc5v0-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&dc_12v>; @@ -179,14 +124,35 @@ vcc5v0_usb: vcc5v0-usb { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; vin-supply = <&dc_12v>; }; + m2_lane1_sel: m2-lane1-sel { + compatible = "regulator-fixed"; + regulator-name = "m2_lane1_sel"; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&m2_lane1_sel_h>; + }; + + usb_hub_reset: usb-hub-reset { + compatible = "regulator-fixed"; + regulator-name = "usb_hub_reset"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_hub_reset_h>; + }; + vcc5v0_host: vcc5v0-host { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host"; @@ -196,16 +162,16 @@ regulator-max-microvolt = <5000000>; enable-active-high; gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_usb>; }; pcie30_avdd0v9: pcie30-avdd0v9 { compatible = "regulator-fixed"; regulator-name = "pcie30_avdd0v9"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; vin-supply = <&vcc3v3_sys>; @@ -214,110 +180,72 @@ pcie30_avdd1v8: pcie30-avdd1v8 { compatible = "regulator-fixed"; regulator-name = "pcie30_avdd1v8"; - regulator-always-on; regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&vcc3v3_sys>; }; - vcc3v3_pcie: vcc3v3-pcie { + vcc3v3_pi6c: vcc3v3-pi6c { compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; + regulator-name = "vcc3v3_pi6c"; + regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - regulator-always-on; - regulator-boot-on; gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - vin-supply = <&dc_12v>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_m2: vcc3v3-m2 { compatible = "regulator-fixed"; regulator-name = "vcc3v3_m2"; + regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; - regulator-always-on; - regulator-boot-on; gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - + vin-supply = <&dc_12v>; }; vcc1v8_m2: vcc1v8-m2 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_m2"; + regulator-boot-on; + regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&vcc1v8_m2_pin>; gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; - + pinctrl-names = "default"; + pinctrl-0 = <&vcc1v8_m2_en>; }; vcc3v3_minipcie: vcc3v3-minipcie { compatible = "regulator-fixed"; regulator-name = "vcc3v3_minipcie"; - regulator-always-on; regulator-boot-on; - enable-active-high; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + enable-active-high; gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&dc_12v>; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ post-power-on-delay-ms = <200>; reset-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; }; - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - clocks = <&rk809 1>; - clock-names = "clk_wifi"; - rockchip,grf = <&grf>; - wifi_chip_type = "ap6275s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&rk809 1>; - clock-names = "ext_clock"; - //wifi-bt-power-toggle; - uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m0_rtsn>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - test-power { status = "okay"; }; - }; &bus_npu { @@ -326,21 +254,36 @@ status = "okay"; }; -&combphy0_us { +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; status = "okay"; }; +&combphy0_us { + status = "disabled"; +}; + &combphy1_usq { status = "okay"; }; &combphy2_psq { + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { status = "okay"; }; -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; +&dmc { + center-supply = <&vdd_logic>; status = "okay"; }; @@ -378,107 +321,12 @@ }; }; -&pcie30phy { - status = "okay"; -}; - -&pcie3x2 { - rockchip,bifurcation; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - status = "okay"; -}; - -&can1 { - assigned-clocks = <&cru CLK_CAN1>; - assigned-clock-rates = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&can1m1_pins>; - status = "okay"; -}; - -&uart3 { - status = "okay"; - pinctrl-0 = <&uart3m1_xfer>; -}; - -&uart4 { - status = "okay"; - pinctrl-0 = <&uart4m1_xfer>; -}; - -&uart5 { - status = "okay"; - pinctrl-0 = <&uart5m1_xfer>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; -}; - -&sdmmc2 { - max-frequency = <150000000>; - supports-sdio; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - center-supply = <&vdd_logic>; - status = "okay"; -}; - -&pdm { - pinctrl-0 = <&pdmm0_clk - &pdmm0_clk1 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - - interrupt-parent = <&gpio0>; - interrupts = ; - status = "okay"; - }; -}; - &gpu { mali-supply = <&vdd_gpu>; status = "okay"; }; &hdmi { - status = "okay"; rockchip,phy-table = <92812500 0x8009 0x0000 0x0270>, <165000000 0x800b 0x0000 0x026d>, @@ -486,6 +334,7 @@ <297000000 0x800b 0x0000 0x01ad>, <594000000 0x8029 0x0000 0x0088>, <000000000 0x0000 0x0000 0x0000>; + status = "okay"; }; &hdmi_in_vp0 { @@ -502,16 +351,17 @@ vdd_cpu: tcs4525@1c { compatible = "tcs,tcs452x"; reg = <0x1c>; - vin-supply = <&vcc5v0_sys>; regulator-compatible = "fan53555-reg"; regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1390000>; regulator-init-microvolt = <900000>; regulator-ramp-delay = <2300>; fcs,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; + vin-supply = <&vcc5v0_sys>; + regulator-state-mem { regulator-off-in-suspend; }; @@ -534,9 +384,7 @@ wakeup-source; #clock-cells = <1>; clock-output-names = "rk808-clkout1", "rk808-clkout2"; - /* clkout2 is the 32.768kHz LPO for the AP6275S WiFi/BT module */ - rockchip,clk-32k-always-on; - //fb-inner-reg-idxs = <2>; + /* clkout2 is unused: the WiFi/BT 32.768kHz LPO comes from Y8 (R142 is DNP) */ /* 1: rst regs (default in codes), 0: rst the pmic */ pmic-reset-func = <0>; /* not save the PMIC_POWER_EN register in uboot */ @@ -767,8 +615,8 @@ }; rk809_codec: codec { - #sound-dai-cells = <0>; compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + #sound-dai-cells = <0>; clocks = <&cru I2S1_MCLKOUT>; clock-names = "mclk"; assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; @@ -784,6 +632,20 @@ }; }; +&i2c3 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + status = "okay"; + }; +}; + &i2s0_8ch { status = "okay"; }; @@ -818,25 +680,17 @@ status = "okay"; }; +&pcie30phy { + status = "okay"; +}; - /* - * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. - * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; - * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages - * must be consistent with the software configuration correspondingly - * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration - * should also be configured to 1.8V accordingly; - * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration - * should also be configured to 3.3V accordingly; - * 3/ VCCIO2 voltage control selection (0xFDC20140) - * BIT[0]: 0x0: from GPIO_0A7 (default) - * BIT[0]: 0x1: from GRF - * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: - * L:VCCIO2 must supply 3.3V - * H:VCCIO2 must supply 1.8V - */ -&pmu_io_domains { +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_m2>; status = "okay"; +}; + +&pmu_io_domains { pmuio2-supply = <&vcc3v3_pmu>; vccio1-supply = <&vccio_acodec>; vccio3-supply = <&vccio_sd>; @@ -844,11 +698,11 @@ vccio5-supply = <&vcc_3v3>; vccio6-supply = <&vcc_1v8>; vccio7-supply = <&vcc_3v3>; + status = "okay"; }; &pwm7 { status = "okay"; - compatible = "rockchip,remotectl-pwm"; remote_pwm_id = <3>; handle_cpu_id = <1>; @@ -955,29 +809,29 @@ status = "okay"; }; -&rkvdec { +&rknpu { + rknpu-supply = <&vdd_npu>; status = "okay"; }; -&rkvdec_mmu { +&rknpu_mmu { status = "okay"; }; -&rkvenc { - venc-supply = <&vdd_logic>; +&rkvdec { status = "okay"; }; -&rkvenc_mmu { +&rkvdec_mmu { status = "okay"; }; -&rknpu { - rknpu-supply = <&vdd_npu>; +&rkvenc { + venc-supply = <&vdd_logic>; status = "okay"; }; -&rknpu_mmu { +&rkvenc_mmu { status = "okay"; }; @@ -996,6 +850,8 @@ supports-emmc; non-removable; max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; status = "okay"; }; @@ -1014,15 +870,29 @@ status = "okay"; }; -&sfc { - status = "disabled"; +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + status = "okay"; }; -&spdif_8ch { - status = "okay"; +&sfc { + status = "disabled"; }; &tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; status = "okay"; }; @@ -1045,6 +915,38 @@ status = "okay"; }; +&uart3 { + status = "okay"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + device-wakeup-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + vddio-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + }; +}; + &usb2phy0 { status = "okay"; }; @@ -1069,17 +971,16 @@ status = "okay"; }; -&usbdrd_dwc3 { - dr_mode = "otg"; - extcon = <&usb2phy0>; - status = "okay"; -}; - &usbdrd30 { status = "okay"; }; -&usbhost_dwc3 { +&usbdrd_dwc3 { + dr_mode = "peripheral"; + extcon = <&usb2phy0>; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; status = "okay"; }; @@ -1087,11 +988,8 @@ status = "okay"; }; -&vad { - rockchip,audio-src = <&i2s1_8ch>; - rockchip,buffer-time-ms = <128>; - rockchip,det-channel = <0>; - rockchip,mode = <0>; +&usbhost_dwc3 { + status = "okay"; }; &vdpu { @@ -1111,9 +1009,9 @@ }; &vop { - status = "okay"; assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; }; &vop_mmu { @@ -1121,6 +1019,41 @@ }; &pinctrl { + bluetooth { + bt_enable: bt-enable { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake: bt-host-wake { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + m2 { + m2_lane1_sel_h: m2-lane1-sel-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc1v8_m2_en: vcc1v8-m2-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; pmic { pmic_int: pmic_int { @@ -1150,47 +1083,13 @@ }; }; - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + usb { + usb_hub_reset_h: usb-hub-reset-h { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; - }; - - bt { - bt_enable: bt-enable { - rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_host_wake: bt-host-wake { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; - }; - bt_wake: bt-wake { - rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vcc1v8-m2-pin { - vcc1v8_m2_pin: vcc1v8-m2-pin { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; \ No newline at end of file +}; From 8bf48c55c2df96652c055a12817087f8bd5c84be Mon Sep 17 00:00:00 2001 From: Kevin Zhuang Date: Sun, 20 Sep 2026 07:18:38 +0000 Subject: [PATCH 4/4] arm64: dts: rockchip: mixtile-blade3: keep rk3588-blade3-v101-linux.dtb as an alias Renaming the board file changes the DTB name, which breaks existing installations that boot rk3588-blade3-v101-linux.dtb, and the vendor BOOT_FDT_FILE in armbian/build that points at it. Keep the old name as a wrapper that only includes the new file, and build both DTBs, the way rk3588-nanopc-cm3588-nas.dts does for rk3588-friendlyelec-cm3588-nas.dts. Both DTBs come out byte-identical, so nothing outside this tree has to change. Signed-off-by: Kevin Zhuang --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts | 9 +++++++++ 2 files changed, 10 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 2b61dcf65cecb..852dbe3201867 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -532,6 +532,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-aim7-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-bananapi-m7.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blade3-v101-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v12-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-blueberry-edge-v12-maizhuo-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts new file mode 100644 index 0000000000000..cbf313f77bb75 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-blade3-v101-linux.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588-mixtile-blade3.dts" + +// DO NOT ADD ANYTHING TO THIS DTS! +// This file only exists for backwards compatibility with existing +// installations that boot rk3588-blade3-v101-linux.dtb.