11#include "irq.h"
22
3+ #include "stm32_fdcan.h"
4+
35#include <assert.h>
46
57#include <mios/eventlog.h>
1416
1517#include <mios/bytestream.h>
1618
19+ #define FDCAN_TDCR 0x048
20+
1721#define FDCAN_FLSSA (x ) (0x000 + 4 * (x))
1822#define FDCAN_FLESA 0x070
1923#define FDCAN_RXFIFO0 (x ,y ) (0x0b0 + 72 * (x) + 4 * (y))
@@ -343,7 +347,8 @@ stm32_fdcan_init(fdcan_t *fc, const char *name,
343347 uint32_t nominal_bitrate , uint32_t data_bitrate ,
344348 uint32_t clockfreq ,
345349 const struct dsig_filter * dif ,
346- const struct dsig_filter * dof )
350+ const struct dsig_filter * dof ,
351+ uint32_t flags )
347352{
348353 int stdidx = 0 ;
349354
@@ -396,6 +401,7 @@ stm32_fdcan_init(fdcan_t *fc, const char *name,
396401
397402 can_timing_t nom , data ;
398403 error_t err ;
404+
399405 err = fdcan_calculate_timings (clockfreq , nominal_bitrate , 75 ,
400406 512 , 256 , 128 , & nom , "nominal" );
401407 if (err )
@@ -406,12 +412,22 @@ stm32_fdcan_init(fdcan_t *fc, const char *name,
406412 if (err )
407413 return err ;
408414
409- reg_wr (fc -> reg_base + FDCAN_DBTP ,
410- ((data .prescaler - 1 ) << 16 ) |
411- ((data .t1 - 1 ) << 8 ) |
412- ((data .t2 - 1 ) << 4 ) |
413- ((data .t2 - 1 ) << 0 ) |
414- 0 );
415+ uint32_t dbtp =
416+ ((data .prescaler - 1 ) << 16 ) |
417+ ((data .t1 - 1 ) << 8 ) |
418+ ((data .t2 - 1 ) << 4 ) |
419+ ((data .t2 - 1 ) << 0 ) |
420+ 0 ;
421+
422+ if (flags & FDCAN_ENABLE_TDC ) {
423+ // TDCO: SSP offset in CAN clock cycles = sample point position
424+ const int tdco = (1 + data .t1 ) * data .prescaler ;
425+ reg_wr (fc -> reg_base + FDCAN_TDCR , tdco << 8 );
426+
427+ dbtp |= (1 << 23 ); // TDC: Transceiver Delay Compensation;
428+ }
429+
430+ reg_wr (fc -> reg_base + FDCAN_DBTP , dbtp );
415431
416432 reg_wr (fc -> reg_base + FDCAN_NBTP ,
417433 ((nom .prescaler - 1 ) << 16 ) |
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