From 90460050dbd2f406ae7ce19671615a374bcce63c Mon Sep 17 00:00:00 2001 From: GitHub Actions Date: Tue, 13 Oct 2026 03:20:09 +0000 Subject: [PATCH] Auto PR: Differences detected --- catalog/list.json | 211 +++++++--------------------------------------- 1 file changed, 29 insertions(+), 182 deletions(-) diff --git a/catalog/list.json b/catalog/list.json index 8671992..3ad734d 100644 --- a/catalog/list.json +++ b/catalog/list.json @@ -1,5 +1,5 @@ { - "num": 162, + "num": 153, "designs": [ { "id": "-", @@ -869,17 +869,17 @@ "devkit": "Agilex 5 FPGA ESeries 065B Premium Development Kit DKA5E065BB32AES1", "device_part": "A5ED065BB32AE6SR0", "description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 5 FPGA.", - "rich_description": "

This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) DK-A5E065BB32AES1.

\"image\"

", + "rich_description": "

This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex™ 5 FPGA E-Series 065B Premium Development Kit (ES1) DK-A5E065BB32AES1.

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", "category": "AI", - "url": "https://github.com/intel-innersource/applications.fpga.niosv-example-designs.niosv-example-designs/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT", + "url": "https://github.com/altera-fpga/agilex5-ed-niosv/blob/rel/25.3.1/niosv_g/tinyml_liteRT", "downloadUrl": "agilex5_niosv_g_tinyml_liteRT.zip", "documentations": [ { "title": "Design Document", - "downloadUrl": "https://github.com/intel-innersource/applications.fpga.niosv-example-designs.niosv-example-designs/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png" + "downloadUrl": "https://github.com/altera-fpga/agilex5-ed-niosv/blob/rel/25.3.1/niosv_g/tinyml_liteRT/img/block_diagram.png" } ], - "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-niosv/releases/assets/349981796", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-niosv/releases/assets/618127813", "Q_GITHUB_RELEASE": "25.3.1", "Q_VALIDATED": true }, @@ -3234,73 +3234,73 @@ }, { "id": "-", - "title": "Terasic Atum A3 Nano FPGA - TinyML LiteRT System Example Design Example on Nios® V/g Processor", + "title": "Nios® V/g Baseline Design", "source": "GitHub", "family": "Agilex 3", "quartus_version": "26.1.1", "patch_number": "Unknown", "devkit": "Atum Nios V Starter Kit", "device_part": "A3CZ135BB18AE7S", - "description": "Nios® V/g Processor-based TinyML LiteRT System Example Design on the Terasic Atum A3 Nano FPGA.", - "rich_description": "

This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor on the Atum A3 Nano FPGA board.

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This example design includes a Nios® V/g processor connected to the On Chip RAM-II, JTAG UART IP, Parallel- IO and System ID peripheral core.

The objective of the design is to accomplish data transfer between the processor and on chip memory and toggling the on board LEDs with and without using the Push Button.

\"image\"

", + "category": "Nios V", + "url": "https://github.com/altera-fpga/agilex3-ed-niosv/releases/download/26.1.1/niosv_g_baseline_design.zip", + "downloadUrl": "niosv_g_baseline_design.zip", "documentations": [ { "title": "Design Document", - "downloadUrl": "https://github.com/altera-fpga/agilex3-ed-niosv/blob/rel/26.1.1/terasic_atum_a3_nano/niosv_g/niosv_g_tinyml_liteRT/docs/Niosv_g_Processor_TinyML_Design_on_Terasic_Atum_A3_Nano_FPGA.md" + "downloadUrl": "https://github.com/altera-fpga/agilex3-ed-niosv/blob/rel/26.1.1/niosv_g/niosv_g_baseline_design/docs/Niosvg_processor_Baseline_Design_on_Atum_A3_Nano_FPGA.md" } ], - "Q_DOWNLOAD_URL": "", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex3-ed-niosv/releases/assets/618013289", "Q_GITHUB_RELEASE": "26.1.1", "Q_VALIDATED": true }, { "id": "-", - "title": "Nios® V/g Ping System Example Design", + "title": "Terasic Atum A3 Nano FPGA - TinyML LiteRT System Example Design Example on Nios® V/g Processor", "source": "GitHub", "family": "Agilex 3", "quartus_version": "26.1.1", "patch_number": "Unknown", "devkit": "Atum Nios V Starter Kit", "device_part": "A3CZ135BB18AE7S", - "description": "The System Example Design demonstrates ping application. The Nios V/g acts as the core. The Triple Speed Ethernet (TSE) IP is configured in RGMII mode and connectes to the onboard DP83867IR TI PHY via RGMII interface.", - "rich_description": "The design has 2 MSGDMA IPs configured in Memory Mapped to Stream (MM2S) mode for Transmission and Stream to Memory Mapped (S2MM) mode for Reception. To test the application, connect the RGMII Interface of the Atum A3 Nano FPGA board to the Link Partner using RJ-45 cable", - "category": "Networking", - "url": "https://github.com/altera-fpga/agilex3-ed-niosv/releases/download/26.1.1/atum_a3_nano_niosv_g_webserver_ping.zip", - "downloadUrl": "atum_a3_nano_niosv_g_webserver_ping.zip", + "description": "Nios® V/g Processor-based TinyML LiteRT System Example Design on the Terasic Atum A3 Nano FPGA.", + "rich_description": "

This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor on the Atum A3 Nano FPGA board.

\"image\"

", + "category": "AI", + "url": "https://github.com/altera-fpga/agilex3-ed-niosv/releases/download/26.1.1/niosv_g_tinyml_liteRT.zip", + "downloadUrl": "niosv_g_tinyml_liteRT.zip", "documentations": [ { "title": "Design Document", - "downloadUrl": "https://github.com/altera-fpga/agilex3-ed-niosv/blob/rel/26.1.1/terasic_atum_a3_nano/niosv_g/niosv_g_webserver_ping/docs/Nios_Vg_Processor_Webserver_Ping_Design_on_Atum_A3_Nano_FPGA.md" + "downloadUrl": "https://github.com/altera-fpga/agilex3-ed-niosv/blob/rel/26.1.1/terasic_atum_a3_nano/niosv_g/niosv_g_tinyml_liteRT/docs/Niosv_g_Processor_TinyML_Design_on_Terasic_Atum_A3_Nano_FPGA.md" } ], - "Q_DOWNLOAD_URL": "", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex3-ed-niosv/releases/assets/618012963", "Q_GITHUB_RELEASE": "26.1.1", "Q_VALIDATED": true }, { "id": "-", - "title": "Nios® V/g Baseline Design", + "title": "Nios® V/g Ping System Example Design", "source": "GitHub", "family": "Agilex 3", "quartus_version": "26.1.1", "patch_number": "Unknown", "devkit": "Atum Nios V Starter Kit", "device_part": "A3CZ135BB18AE7S", - "description": "This design demonstrates the Baseline Design for a Nios® V/g processor with basic bare minimum peripherals required for any application execution", - "rich_description": "

This example design includes a Nios® V/g processor connected to the On Chip RAM-II, JTAG UART IP, Parallel- IO and System ID peripheral core.

The objective of the design is to accomplish data transfer between the processor and on chip memory and toggling the on board LEDs with and without using the Push Button.

\"image\"

", - "category": "Nios V", - "url": "https://github.com/altera-fpga/agilex3-ed-niosv/releases/download/26.1.1/atum_niosv_g_baseline_design.zip", - "downloadUrl": "atum_niosv_g_Baseline_Design.zip", + "description": "The System Example Design demonstrates ping application. The Nios V/g acts as the core. The Triple Speed Ethernet (TSE) IP is configured in RGMII mode and connectes to the onboard DP83867IR TI PHY via RGMII interface.", + "rich_description": "The design has 2 MSGDMA IPs configured in Memory Mapped to Stream (MM2S) mode for Transmission and Stream to Memory Mapped (S2MM) mode for Reception. To test the application, connect the RGMII Interface of the Atum A3 Nano FPGA board to the Link Partner using RJ-45 cable", + "category": "Networking", + "url": "https://github.com/altera-fpga/agilex3-ed-niosv/releases/download/26.1.1/niosv_g_webserver_ping.zip", + "downloadUrl": "niosv_g_webserver_ping.zip", "documentations": [ { "title": "Design Document", - "downloadUrl": "https://github.com/altera-fpga/agilex3-ed-niosv/blob/rel/26.1.1/niosv_g/niosv_g_baseline_design/docs/Niosvg_processor_Baseline_Design_on_Atum_A3_Nano_FPGA.md" + "downloadUrl": "https://github.com/altera-fpga/agilex3-ed-niosv/blob/rel/26.1.1/terasic_atum_a3_nano/niosv_g/niosv_g_webserver_ping/docs/Nios_Vg_Processor_Webserver_Ping_Design_on_Atum_A3_Nano_FPGA.md" } ], - "Q_DOWNLOAD_URL": "", + "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex3-ed-niosv/releases/assets/618012554", "Q_GITHUB_RELEASE": "26.1.1", "Q_VALIDATED": true }, @@ -3483,159 +3483,6 @@ "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-pcie-rp/releases/assets/261042143", "Q_GITHUB_RELEASE": "25.1-1", "Q_VALIDATED": true - }, - { - "id": "-", - "title": "Agilex™ 5 E-Series(Group A) 25G/10G Ethernet System Example Design", - "source": "GitHub", - "family": "Agilex 5", - "quartus_version": "26.1.1 Pro Edition", - "devkit": "Agilex™ 5 FPGA and SoC E-Series 065A Modular Development Kit [MK-A5E065AB32AEA]", - "device_part": "A5ED065AB32AE1V", - "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support upto 25G/10Gbps.", - "rich_description": "

This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (25G/10G) using User Logic (Packet Client) through the L2 Packet Switch.

Repository Structure

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This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.

Repository Structure

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This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.

Repository Structure

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This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.

Repository Structure

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This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.

Repository Structure

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This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.

Repository Structure

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The Agilex™ 5 2x10GbE Precision Time Protocol(PTP1588v2) System Example Design includes two Ethernet ports with built-in two-step hardware PTP timestamping capabilities. The integrated Agilex™ 5 Hard Processor System (HPS) runs a PTP software stack that complements the hardware-based timestamping functionality. The System Example Design (SED) provides the necessary drivers and user applications to support the Linux Network stack, the Linux PTP stack, and Layer 2 Packet Switch through the Linux kernel Traffic Control (TC) system.", - "category": "PTP-IEEE1588v2", - "url": "https://github.com/altera-fpga/agilex5-ed-ptp", - "downloadUrl": "source_code.zip", - "Q_DOWNLOAD_URL": "", - "Q_GITHUB_RELEASE": "SED-2X10GE_PTP-a5e065b-pdk-Q26.1-Rel1.1", - "Q_VALIDATED": true - }, - { - "id": "-", - "title": "Agilex™ 5 FPGA E-Series Premium Development Kit 2x10G PTP1588 System Example Design ", - "source": "GitHub", - "family": "Agilex 5", - "quartus_version": "25.3 Pro Edition", - "devkit": "Agilex™ 5 FPGA and SoC E-Series Premium Development Kit (ES) (DK-A5E065BB32AES1)", - "device_part": "A5ED065BB32AE6SR0", - "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps with support for PTP IEEE-1588v2.", - "rich_description": "

The Agilex™ 5 2x10GbE Precision Time Protocol(PTP1588v2) System Example Design includes two Ethernet ports with built-in two-step hardware PTP timestamping capabilities. The integrated Agilex™ 5 Hard Processor System (HPS) runs a PTP software stack that complements the hardware-based timestamping functionality. The System Example Design (SED) provides the necessary drivers and user applications to support the Linux Network stack, the Linux PTP stack, and Layer 2 Packet Switch through the Linux kernel Traffic Control (TC) system.", - "category": "PTP-IEEE1588v2", - "url": "https://github.com/altera-fpga/agilex5-ed-ptp", - "downloadUrl": "source_code.zip", - "Q_DOWNLOAD_URL": "", - "Q_GITHUB_RELEASE": "SED-2X10GE_PTP-agilex5_dk_a5e065bb32aes1-Q25.3-Rel1.1", - "Q_VALIDATED": true } ], "force_always_regenerate": []