diff --git a/catalog/list.json b/catalog/list.json
index f195c65..e216b26 100644
--- a/catalog/list.json
+++ b/catalog/list.json
@@ -1,5 +1,5 @@
 {
-    "num": 149,
+    "num": 162,
     "designs": [
         {
             "id": "-",
@@ -3411,6 +3411,231 @@
             "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex3-ed-niosv/releases/assets/247410476",
             "Q_GITHUB_RELEASE": "25.1.0-v1.0",
             "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 PCIe Root Port System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "26.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AEA",
+            "device_part": "A5ED065BB32AE4S",
+            "description": "This system example design demonstrates a PCIe root port running on theAgilex™ 5 FPGA E-Series 065B Modular Development Kitconnected to a Non-Volatile Memory express (NVMe) endpoint. The PCIe root port is capable of Gen4x4 speeds. The design is intended to serve as a reference to customers on how to implement and run a performant root port system using the Agilex™ 5 SoC and relevant IP.",
+            "rich_description": "<p>The PCIe root port example design is based on the Agilex™ 5 Golden System Reference Design (GSRD) with the following components added:</p><ul>\n<li>Linux driver for PCIe root port IP that runs on HPS, enumerates the PCIe endpoint(s) and configures the PCIe root port Hard IP (HIP) through a dedicated reconfiguration AXI-Lite interface.</li>\n<li>The Multichannel DMA (MCDMA) bridge which interfaces between the SoC's AXI-MM interface on one end and the AXI-ST interface on the PCIe root port IP (carrying PCIe TLP traffic) on the other.</li>\n<li>Various bridges, interconnects and adapters to handle clock crossing, data path and control path.</li>\n</ul><p>The system block diagram is shown below:</p><p><img alt=\"Agilex™ 5 Root Port block diagram\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5-ed-pcie-rp/rel/26.1/images/SM_RP_MDK.png\"/></p><ul>\n<li>The HPS-to-FPGA (H2F) lightweight AXI4 interface on the HPS is used for accessing the control and status (CSR) interface of various blocks on the design. It connects to the reconfiguration interface on the PCIe root port HIP as well as the Configuration Slave (CS) interface on the MCDMA bridge.</li>\n<li>Configuration of the PCIe Endpoint (as part of Enumeration) is done via the CS interface. This interface supports only one outstanding configuration write/read transaction, as the number of PCIe tags allotted to this interface is only one (inside the MCDMA bridge).</li>\n<li>The connection to the HIP reconfiguration interface allows for updating the Type1 configuration space fields such as Primary, Secondary and Subordinate Bus numbers as well as Memory ranges to support different addressing schemes, i.e., Route by ID or Route by Address. PCIe root port configuration and status register accesses for IRQ and error status are also done via the same path.</li>\n<li>Transfer of large memory transactions between the SoC's H2F AXI4 interface and the PCIe endpoint occurs via the Bursting AXI-MM Slave (BAS) interface on the MCDMA bridge. This interface theoretically supports 64 outstanding read transactions. </li>\n<li>MSI/MSI-X interrupts from the PCIe endpoint are handled through the Bursting AXI-MM Master (BAM) interface on the bridge IP.</li>\n<li>The bridge IP also supports memory requests (Read/Write) initiated by the endpoint (DMA bus mastering) targeting System Memory. These transactions are routed via the HPS's FPGA-to-HPS (F2H) AXI4 interface as shown in the diagram.</li>\n</ul>",
+            "category": "HPS, PCIe",
+            "url": "https://github.com/altera-fpga/agilex5-ed-pcie-rp/tree/rel/26.1",
+            "downloadUrl": "a5ed065b-modular-devkit-pcie-rp-gen4x4.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-pcie-rp/releases/assets/480618998",
+            "Q_GITHUB_RELEASE": "26.1-2",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 PCIe Root Port System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE4SR0",
+            "description": "This system example design demonstrates a PCIe root port running on theAgilex™ 5 FPGA E-Series 065B Premium Development Kitconnected to a Non-Volatile Memory express (NVMe) endpoint. The PCIe root port is capable of Gen4x4 speeds. The design is intended to serve as a reference to customers on how to implement and run a performant root port system using the Agilex™ 5 SoC and relevant IP.",
+            "rich_description": "<p>The PCIe root port example design is based on the Agilex™ 5 Golden System Reference Design (GSRD) with the following components added:</p><ul>\n<li>Linux driver for PCIe root port IP that runs on HPS, enumerates the PCIe endpoint(s) and configures the PCIe root port Hard IP (HIP) through a dedicated reconfiguration AXI-Lite interface.</li>\n<li>The Multichannel DMA (MCDMA) bridge which interfaces between the SoC's AXI-MM interface on one end and the AXI-ST interface on the PCIe root port IP (carrying PCIe TLP traffic) on the other.</li>\n<li>Various bridges, interconnects and adapters to handle clock crossing, data path and control path.</li>\n</ul><p>The system block diagram is shown below:</p><p><img alt=\"Agilex™ 5 Root Port block diagram\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5-ed-pcie-rp/rel/25.1/images/SM_RP.png\"/></p><ul>\n<li>The HPS-to-FPGA (H2F) lightweight AXI4 interface on the HPS is used for accessing the control and status (CSR) interface of various blocks on the design. It connects to the reconfiguration interface on the PCIe root port HIP as well as the Configuration Slave (CS) interface on the MCDMA bridge.</li>\n<li>Configuration of the PCIe Endpoint (as part of Enumeration) is done via the CS interface. This interface supports only one outstanding configuration write/read transaction, as the number of PCIe tags allotted to this interface is only one (inside the MCDMA bridge).</li>\n<li>The connection to the HIP reconfiguration interface allows for updating the Type1 configuration space fields such as Primary, Secondary and Subordinate Bus numbers as well as Memory ranges to support different addressing schemes, i.e., Route by ID or Route by Address. PCIe root port configuration and status register accesses for IRQ and error status are also done via the same path.</li>\n<li>Transfer of large memory transactions between the SoC's H2F AXI4 interface and the PCIe endpoint occurs via the Bursting AXI-MM Slave (BAS) interface on the MCDMA bridge. This interface theoretically supports 64 outstanding read transactions. </li>\n<li>MSI/MSI-X interrupts from the PCIe endpoint are handled through the Bursting AXI-MM Master (BAM) interface on the bridge IP.</li>\n<li>The bridge IP also supports memory requests (Read/Write) initiated by the endpoint (DMA bus mastering) targeting System Memory. These transactions are routed via the HPS's FPGA-to-HPS (F2H) AXI4 interface as shown in the diagram.</li>\n</ul>",
+            "category": "HPS, PCIe",
+            "url": "https://github.com/altera-fpga/agilex5-ed-pcie-rp",
+            "downloadUrl": "a5ed065es-premium-devkit-pcie-rp-gen4x4.zip",
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-pcie-rp/releases/assets/293975793",
+            "Q_GITHUB_RELEASE": "25.1-2",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 PCIe Root Port System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "26.1",
+            "patch_number": "Unknown",
+            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AEA",
+            "device_part": "A5ED065BB32AE4S",
+            "description": "This system example design demonstrates a PCIe root port running on theAgilex™ 5 FPGA E-Series 065B Modular Development Kitconnected to a Non-Volatile Memory express (NVMe) endpoint. The PCIe root port is capable of Gen4x4 speeds. The design is intended to serve as a reference to customers on how to implement and run a performant root port system using the Agilex™ 5 SoC and relevant IP.",
+            "rich_description": "<p>The PCIe root port example design is based on the Agilex™ 5 Golden System Reference Design (GSRD) with the following components added:</p><ul>\n<li>Linux driver for PCIe root port IP that runs on HPS, enumerates the PCIe endpoint(s) and configures the PCIe root port Hard IP (HIP) through a dedicated reconfiguration AXI-Lite interface.</li>\n<li>The Multichannel DMA (MCDMA) bridge which interfaces between the SoC's AXI-MM interface on one end and the AXI-ST interface on the PCIe root port IP (carrying PCIe TLP traffic) on the other.</li>\n<li>Various bridges, interconnects and adapters to handle clock crossing, data path and control path.</li>\n</ul><p>The system block diagram is shown below:</p><p><img alt=\"Agilex™ 5 Root Port block diagram\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5-ed-pcie-rp/rel/26.1/images/SM_RP_MDK.png\"/></p><ul>\n<li>The HPS-to-FPGA (H2F) lightweight AXI4 interface on the HPS is used for accessing the control and status (CSR) interface of various blocks on the design. It connects to the reconfiguration interface on the PCIe root port HIP as well as the Configuration Slave (CS) interface on the MCDMA bridge.</li>\n<li>Configuration of the PCIe Endpoint (as part of Enumeration) is done via the CS interface. This interface supports only one outstanding configuration write/read transaction, as the number of PCIe tags allotted to this interface is only one (inside the MCDMA bridge).</li>\n<li>The connection to the HIP reconfiguration interface allows for updating the Type1 configuration space fields such as Primary, Secondary and Subordinate Bus numbers as well as Memory ranges to support different addressing schemes, i.e., Route by ID or Route by Address. PCIe root port configuration and status register accesses for IRQ and error status are also done via the same path.</li>\n<li>Transfer of large memory transactions between the SoC's H2F AXI4 interface and the PCIe endpoint occurs via the Bursting AXI-MM Slave (BAS) interface on the MCDMA bridge. This interface theoretically supports 64 outstanding read transactions. </li>\n<li>MSI/MSI-X interrupts from the PCIe endpoint are handled through the Bursting AXI-MM Master (BAM) interface on the bridge IP.</li>\n<li>The bridge IP also supports memory requests (Read/Write) initiated by the endpoint (DMA bus mastering) targeting System Memory. These transactions are routed via the HPS's FPGA-to-HPS (F2H) AXI4 interface as shown in the diagram.</li>\n</ul>",
+            "category": "HPS, PCIe",
+            "url": "https://github.com/altera-fpga/agilex5-ed-pcie-rp/tree/rel/26.1",
+            "downloadUrl": "a5ed065b-modular-devkit-pcie-rp-gen4x4.zip",
+            "documentations": [],
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-pcie-rp/releases/assets/448501494",
+            "Q_GITHUB_RELEASE": "26.1-1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 PCIe Root Port System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1",
+            "devkit": "Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE4SR0",
+            "description": "This system example design demonstrates a PCIe root port running on theAgilex™ 5 FPGA E-Series 065B Premium Development Kitconnected to a Non-Volatile Memory express (NVMe) endpoint. The PCIe root port is capable of Gen4x4 speeds. The design is intended to serve as a reference to customers on how to implement and run a performant root port system using the Agilex™ 5 SoC and relevant IP.",
+            "rich_description": "<p>The PCIe root port example design is based on the Agilex™ 5 Golden System Reference Design (GSRD) with the following components added:</p><ul>\n<li>Linux driver for PCIe root port IP that runs on HPS, enumerates the PCIe endpoint(s) and configures the PCIe root port Hard IP (HIP) through a dedicated reconfiguration AXI-Lite interface.</li>\n<li>The Multichannel DMA (MCDMA) bridge which interfaces between the SoC's AXI-MM interface on one end and the AXI-ST interface on the PCIe root port IP (carrying PCIe TLP traffic) on the other.</li>\n<li>Various bridges, interconnects and adapters to handle clock crossing, data path and control path.</li>\n</ul><p>The system block diagram is shown below:</p><p><img alt=\"Agilex™ 5 Root Port block diagram\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex5-ed-pcie-rp/rel/25.1/images/SM_RP.png\"/></p><ul>\n<li>The HPS-to-FPGA (H2F) lightweight AXI4 interface on the HPS is used for accessing the control and status (CSR) interface of various blocks on the design. It connects to the reconfiguration interface on the PCIe root port HIP as well as the Configuration Slave (CS) interface on the MCDMA bridge.</li>\n<li>Configuration of the PCIe Endpoint (as part of Enumeration) is done via the CS interface. This interface supports only one outstanding configuration write/read transaction, as the number of PCIe tags allotted to this interface is only one (inside the MCDMA bridge).</li>\n<li>The connection to the HIP reconfiguration interface allows for updating the Type1 configuration space fields such as Primary, Secondary and Subordinate Bus numbers as well as Memory ranges to support different addressing schemes, i.e., Route by ID or Route by Address. PCIe root port configuration and status register accesses for IRQ and error status are also done via the same path.</li>\n<li>Transfer of large memory transactions between the SoC's H2F AXI4 interface and the PCIe endpoint occurs via the Bursting AXI-MM Slave (BAS) interface on the MCDMA bridge. This interface theoretically supports 64 outstanding read transactions. </li>\n<li>MSI/MSI-X interrupts from the PCIe endpoint are handled through the Bursting AXI-MM Master (BAM) interface on the bridge IP.</li>\n<li>The bridge IP also supports memory requests (Read/Write) initiated by the endpoint (DMA bus mastering) targeting System Memory. These transactions are routed via the HPS's FPGA-to-HPS (F2H) AXI4 interface as shown in the diagram.</li>\n</ul>",
+            "category": "HPS, PCIe",
+            "url": "https://github.com/altera-fpga/agilex5-ed-pcie-rp",
+            "downloadUrl": "a5ed065es-premium-devkit-pcie-rp-gen4x4.zip",
+            "Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex5-ed-pcie-rp/releases/assets/261042143",
+            "Q_GITHUB_RELEASE": "25.1-1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 E-Series(Group A) 25G/10G Ethernet System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "26.1.1 Pro Edition",
+            "devkit": "Agilex™ 5 FPGA and SoC E-Series 065A Modular Development Kit [MK-A5E065AB32AEA]",
+            "device_part": "A5ED065AB32AE1V",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support upto 25G/10Gbps.",
+            "rich_description": "<p>This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (25G/10G) using User Logic (Packet Client) through the L2 Packet Switch.  </p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- a5e065a-mod-devkit-prod-es  \n        |--- src\n        |   |--- hw \n        |   |--- sw</code></li>\n</ul>",
+            "category": "Ethernet",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ethernet",
+            "downloadUrl": "agilex5-ed-ethernet-SED-1xETH-a5e065a-mdk-Q26.1.1-Rel-1.1.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-1xETH-a5e065a-mdk-Q26.1.1-Rel-1.1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 1x10G Ethernet System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "26.1 Pro Edition",
+            "devkit": "Agilex™ 5 FPGA and SoC E-Series 065B Modular Development Kit MK-A5E065BB32AEA",
+            "device_part": "A5ED065BB32AE4S",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps.",
+            "rich_description": "<p>This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.  </p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- a5e065b-mod-devkit-prod-es  \n        |--- src\n        |   |--- hw \n        |   |--- sw</code></li>\n</ul>",
+            "category": "Unknown",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ethernet",
+            "downloadUrl": "SED-1x10GE-a5e065b-mdk-Q26.1-Rel-1.2.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-1x10GE-a5e065b-mdk-Q26.1-Rel-1.2",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 1x10G Ethernet System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "26.1 Pro Edition",
+            "devkit": "Agilex™ 5 FPGA and SoC E-Series 065B Modular Development Kit MK-A5E065BB32AEA",
+            "device_part": "A5ED065BB32AE4S",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps.",
+            "rich_description": "<p>This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.  </p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- a5e065b-mod-devkit-prod-es  \n        |--- src\n        |   |--- hw \n        |   |--- sw</code></li>\n</ul>",
+            "category": "Unknown",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ethernet",
+            "downloadUrl": "source_code.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-1x10GE-a5e065b-mdk-Q26.1-Rel-1.1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 1x10G Ethernet System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.3 Pro Edition",
+            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps.",
+            "rich_description": "<p>This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.  </p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- a5e065b-mod-devkit-exp-es  \n        |--- src\n        |   |--- hw \n        |   |--- sw</code></li>\n</ul>",
+            "category": "Unknown",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ethernet",
+            "downloadUrl": "source_code.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-1x10GE-a5e065b-mdk-Q25.3-Rel-1.1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 FPGA E-Series Modular Development Kit 1x10G Ethernet System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1 Pro Edition",
+            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps.",
+            "rich_description": "<p>This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.  </p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- a5e065b-mod-devkit-exp-es  \n        |--- src\n        |   |--- hw \n        |   |--- sw</code></li>\n</ul>",
+            "category": "Unknown",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ethernet",
+            "downloadUrl": "source_code.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-1x10GE-a5e065b-mdk-Q25.1-Rel-1.1p1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 FPGA E-Series Modular Development Kit 1x10G Ethernet System Example Design",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.1 Pro Edition",
+            "devkit": "Agilex 5 FPGA E-Series 065B Modular Development Kit MK-A5E065BB32AES1",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps.",
+            "rich_description": "<p>This design is based on base GHRD with the following feature additions: \n-Important features of the design include,\n-Single Ethernet port working at 10G speed.\n-Configurable L2 Packet Switch supporting multiple source streams to Ethernet port and packet rerouting from Ethernet port to multiple destinations like HPS or User Logic(Packet client).\n-Separate DMA channel per direction for HPS system memory accesses.\n-Performance achievability matching the lane rate (10G) using User Logic (Packet Client) through the L2 Packet Switch.  </p><h2>Repository Structure</h2><ul>\n<li>Directory Structure used in this example design\n <code>bash\n    |--- a5e065b-mod-devkit-exp-es  \n        |--- src\n        |   |--- hw \n        |   |--- sw</code></li>\n</ul>",
+            "category": "Unknown",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ethernet",
+            "downloadUrl": "source_code.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-1x10GE-a5e065b-mdk-Q25.1-Rel-1.1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": " Agilex™ 5 SoC 2x25GbE PTP1588 System Example Design ",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "26.1 Pro Edition",
+            "devkit": "Agilex™ 5 FPGA E-Series 065A Premium Development Kit(DK-A5E065AB32AEA)",
+            "device_part": "A5ED065AB32AE1V",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps with support for PTP IEEE-1588v2.",
+            "rich_description": "<p>The Agilex™ 5 2x125GbE Precision Time Protocol(PTP1588v2) System Example Design includes two Ethernet ports with built-in two-step hardware PTP timestamping capabilities. The integrated Agilex™ 5 Hard Processor System (HPS) runs a PTP software stack that complements the hardware-based timestamping functionality. The System Example Design (SED) provides the necessary drivers and user applications to support the Linux Network stack, the Linux PTP stack, and Layer 2 Packet Switch through the Linux kernel Traffic Control (TC) system.",
+            "category": "PTP-IEEE1588v2",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ptp",
+            "downloadUrl": "source_code.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-2X25GE_PTP-a5e065a-pdk-Q26.1-Rel1.1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": " Agilex™ 5 SoC 2x10GbE PTP1588 System Example Design ",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "26.1 Pro Edition",
+            "devkit": "Agilex™ 5 FPGA E-Series 065B Premium Development Kit(DK-A5E065BB32AEA)",
+            "device_part": "A5ED065BB32AE4S",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps with support for PTP IEEE-1588v2.",
+            "rich_description": "<p>The Agilex™ 5 2x10GbE Precision Time Protocol(PTP1588v2) System Example Design includes two Ethernet ports with built-in two-step hardware PTP timestamping capabilities. The integrated Agilex™ 5 Hard Processor System (HPS) runs a PTP software stack that complements the hardware-based timestamping functionality. The System Example Design (SED) provides the necessary drivers and user applications to support the Linux Network stack, the Linux PTP stack, and Layer 2 Packet Switch through the Linux kernel Traffic Control (TC) system.",
+            "category": "PTP-IEEE1588v2",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ptp",
+            "downloadUrl": "source_code.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-2X10GE_PTP-a5e065b-pdk-Q26.1-Rel1.1",
+            "Q_VALIDATED": true
+        },
+        {
+            "id": "-",
+            "title": "Agilex™ 5 FPGA E-Series Premium Development Kit 2x10G PTP1588 System Example Design ",
+            "source": "GitHub",
+            "family": "Agilex 5",
+            "quartus_version": "25.3 Pro Edition",
+            "devkit": "Agilex™ 5 FPGA and SoC E-Series Premium Development Kit (ES) (DK-A5E065BB32AES1)",
+            "device_part": "A5ED065BB32AE6SR0",
+            "description": "This design is based on the Agilex 5 SoC Golden Hardware Reference Design (GHRD) which is part of the Golden System Reference Design (GSRD), enhanced with additional components such as ethernet interface with GTS Ethernet Hard IP, L2 Packet Switch and Custom Packet generator the traffic data rate support 10Gbps with support for PTP IEEE-1588v2.",
+            "rich_description": "<p>The Agilex™ 5 2x10GbE Precision Time Protocol(PTP1588v2) System Example Design includes two Ethernet ports with built-in two-step hardware PTP timestamping capabilities. The integrated Agilex™ 5 Hard Processor System (HPS) runs a PTP software stack that complements the hardware-based timestamping functionality. The System Example Design (SED) provides the necessary drivers and user applications to support the Linux Network stack, the Linux PTP stack, and Layer 2 Packet Switch through the Linux kernel Traffic Control (TC) system.",
+            "category": "PTP-IEEE1588v2",
+            "url": "https://github.com/altera-fpga/agilex5-ed-ptp",
+            "downloadUrl": "source_code.zip",
+            "Q_DOWNLOAD_URL": "",
+            "Q_GITHUB_RELEASE": "SED-2X10GE_PTP-agilex5_dk_a5e065bb32aes1-Q25.3-Rel1.1",
+            "Q_VALIDATED": true
         }
     ],
     "force_always_regenerate": []