msg_file.log

SCUBA, Version Diamond (64-bit) 3.7.1.502
Wed Aug 31 17:51:40 2016
  
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
  
BEGIN SCUBA Module Synthesis
  
    Issued command   : D:\dev\lattice\lscc\diamond\3.7_x64\ispfpga\bin\nt64\scuba.exe -w -n vga_pll -lang verilog -synth synplify -arch xo2c00 -type pll -fin 50 -fclkop 135 -fclkop_tol 5.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -fracn 819 
    Circuit name     : vga_pll
    Module type      : pll
    Module Version   : 5.7
    Ports            : 
    Inputs       : CLKI
    Outputs      : CLKOP
    I/O buffer       : not inserted
    EDIF output      : vga_pll.edn
    Verilog output   : vga_pll.v
    Verilog template : vga_pll_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : vga_pll.srp
    Estimated Resource Usage:
  
END   SCUBA Module Synthesis