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and b/PCB1.PcbDoc differ diff --git a/PCB1.PcbDoc.htm b/PCB1.PcbDoc.htm new file mode 100644 index 0000000..7a3f88a --- /dev/null +++ b/PCB1.PcbDoc.htm @@ -0,0 +1,155 @@ + +
+ + + + + + + + Reporting Options +| Date | +: | +2020-04-06 | +
| Time | +: | +00:04:49 | +
| Filename | +: | +C:\Users\M\workspace\TIsupervisorycontroller\PCB1.PcbDoc | +
| Version | +Warning | +
|---|
This file was generated by an earlier version of the software
+ + diff --git a/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.drc b/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.drc index fe88148..98806da 100644 --- a/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.drc +++ b/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.drc @@ -1,10 +1,14 @@ Protel Design System Design Rule Check -PCB File : C:\Users\Hybrid\Documents\GitHub\TISupervisoryController\PCB1.PcbDoc -Date : 13/03/2020 -Time : 2:15:08 PM +PCB File : C:\Users\M\workspace\TIsupervisorycontroller\PCB1.PcbDoc +Date : 2020-04-08 +Time : 16:04:38 Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All) -Rule Violations :0 + Violation between Clearance Constraint: (Collision < 0.254mm) Between Area Fill (-0.306mm,124.628mm) (8.174mm,133.023mm) on Keep-Out Layer And Pad Free-1(3.85mm,128.79mm) on Multi-Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Area Fill (-0.325mm,-7.405mm) (8.155mm,0.99mm) on Keep-Out Layer And Pad Free-1(3.85mm,-3.21mm) on Multi-Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Area Fill (83.694mm,124.628mm) (92.174mm,133.023mm) on Keep-Out Layer And Pad Free-1(87.85mm,128.79mm) on Multi-Layer + Violation between Clearance Constraint: (Collision < 0.254mm) Between Area Fill (83.704mm,-7.373mm) (92.184mm,1.022mm) on Keep-Out Layer And Pad Free-1(87.86mm,-3.21mm) on Multi-Layer +Rule Violations :4 Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) Rule Violations :0 @@ -25,7 +29,11 @@ Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) ( Rule Violations :0 Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) -Rule Violations :0 + Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(3.85mm,128.79mm) on Multi-Layer Actual Hole Size = 3.4mm + Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(3.85mm,-3.21mm) on Multi-Layer Actual Hole Size = 3.4mm + Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(87.85mm,128.79mm) on Multi-Layer Actual Hole Size = 3.4mm + Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(87.86mm,-3.21mm) on Multi-Layer Actual Hole Size = 3.4mm +Rule Violations :4 Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) Rule Violations :0 @@ -34,126 +42,126 @@ Processing Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) Rule Violations :0 Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C4-2(14.62mm,16.039mm) on Top Layer And Text "P1" (13.47mm,14.434mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad D1-3(74mm,90.509mm) on Top Layer And Track (72.016mm,88.484mm)(77.978mm,88.484mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad D1-3(74mm,90.509mm) on Top Layer And Track (72.016mm,92.534mm)(77.978mm,92.534mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-1(50.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-1(50.025mm,72.117mm) on Top Layer And Track (50.525mm,71.379mm)(50.525mm,72.854mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-10(45.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-11(45.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-12(44.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-13(44.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-14(43.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-15(43.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-16(42.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-17(42.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-18(41.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-19(41.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-2(49.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-20(40.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-21(40.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-22(39.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-23(39.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-24(38.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad IC1-25(38.525mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-25(38.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-26(39.025mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-26(39.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-27(39.525mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-27(39.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-28(40.025mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-28(40.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-29(40.525mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-29(40.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-3(49.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.145mm < 0.254mm) Between Pad IC1-30(41.025mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.145mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-30(41.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-31(41.525mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-31(41.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-32(42.025mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-32(42.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-33(42.525mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-33(42.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.108mm < 0.254mm) Between Pad IC1-34(43.025mm,64.541mm) on Top Layer And Text "R13" (38.831mm,63.701mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.108mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-34(43.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-35(43.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-36(44.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-37(44.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-38(45.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-39(45.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-4(48.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-40(46.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-41(46.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-42(47.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-43(47.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-44(48.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-45(48.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-46(49.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-47(49.525mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-48(50.025mm,64.541mm) on Top Layer And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-5(48.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-6(47.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-7(47.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-8(46.525mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-9(46.025mm,72.117mm) on Top Layer And Track (38.025mm,71.029mm)(50.525mm,71.029mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-1(17.063mm,64.634mm) on Top Layer And Track (16.3mm,65.309mm)(17.825mm,65.309mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-1(17.063mm,64.634mm) on Top Layer And Track (18.175mm,60.279mm)(18.175mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-2(17.063mm,63.364mm) on Top Layer And Track (18.175mm,60.279mm)(18.175mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-3(17.063mm,62.094mm) on Top Layer And Track (18.175mm,60.279mm)(18.175mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-4(17.063mm,60.824mm) on Top Layer And Track (18.175mm,60.279mm)(18.175mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-5(22.487mm,60.824mm) on Top Layer And Track (21.375mm,60.279mm)(21.375mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-6(22.487mm,62.094mm) on Top Layer And Track (21.375mm,60.279mm)(21.375mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-7(22.487mm,63.364mm) on Top Layer And Track (21.375mm,60.279mm)(21.375mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-8(22.487mm,64.634mm) on Top Layer And Track (21.375mm,60.279mm)(21.375mm,65.179mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R10-1(21.635mm,30.029mm) on Bottom Layer And Text "R7" (22.047mm,28.448mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.096mm < 0.254mm) Between Pad R10-2(18.735mm,30.029mm) on Bottom Layer And Text "R7" (22.047mm,28.448mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.096mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R1-1(18.81mm,38.764mm) on Top Layer And Text "R21" (18.237mm,37.643mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R11-1(21.79mm,38.764mm) on Bottom Layer And Text "R15" (22.352mm,37.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R11-2(18.89mm,38.764mm) on Bottom Layer And Text "R15" (22.352mm,37.643mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R1-2(21.71mm,38.764mm) on Top Layer And Text "R21" (18.237mm,37.643mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R12-1(52.055mm,48.739mm) on Bottom Layer And Text "R14" (52.68mm,47.523mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.119mm < 0.254mm) Between Pad R15-1(18.89mm,35.754mm) on Bottom Layer And Text "R8" (22.225mm,34.773mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.119mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R15-2(21.79mm,35.754mm) on Bottom Layer And Text "R8" (22.225mm,34.773mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R16-1(18.56mm,91.014mm) on Bottom Layer And Text "R18" (22.149mm,89.941mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R16-2(21.46mm,91.014mm) on Bottom Layer And Text "R18" (22.149mm,89.941mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R17-1(18.67mm,98.569mm) on Bottom Layer And Text "R19" (22.022mm,97.561mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R17-2(21.57mm,98.569mm) on Bottom Layer And Text "R19" (22.022mm,97.561mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R2-1(18.755mm,29.954mm) on Top Layer And Text "R6" (18.009mm,28.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R21-1(18.81mm,35.754mm) on Top Layer And Text "R5" (18.161mm,34.773mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R22-1(18.56mm,91.014mm) on Top Layer And Text "R25" (18.034mm,89.941mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R22-2(21.46mm,91.014mm) on Top Layer And Text "R25" (18.034mm,89.941mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R24-1(18.67mm,98.569mm) on Top Layer And Text "R26" (17.983mm,97.561mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R24-2(21.57mm,98.569mm) on Top Layer And Text "R26" (17.983mm,97.561mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R4-2(55.13mm,48.739mm) on Top Layer And Text "J4" (53.95mm,47.625mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R4-2(55.13mm,48.739mm) on Top Layer And Text "R23" (50.927mm,47.447mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R5-1(18.73mm,32.889mm) on Top Layer And Text "R2" (18.186mm,31.852mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.227mm < 0.254mm) Between Pad R5-2(21.63mm,32.889mm) on Top Layer And Text "R2" (18.186mm,31.852mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.227mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R6-1(18.585mm,26.644mm) on Top Layer And Text "R3" (18.161mm,25.146mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (0.108mm < 0.254mm) Between Pad R6-2(21.485mm,26.644mm) on Top Layer And Text "R3" (18.161mm,25.146mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.108mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R7-1(21.485mm,26.569mm) on Bottom Layer And Text "R9" (22.276mm,25.146mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R8-1(21.655mm,32.894mm) on Bottom Layer And Text "R10" (22.2mm,31.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] - Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R8-2(18.755mm,32.894mm) on Bottom Layer And Text "R10" (22.2mm,31.928mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad C4-2(10.48mm,4.999mm) on Top Layer And Text "P1" (9.33mm,3.394mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad D1-3(67.69mm,77.299mm) on Top Layer And Track (65.706mm,75.274mm)(71.668mm,75.274mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.245mm < 0.254mm) Between Pad D1-3(67.69mm,77.299mm) on Top Layer And Track (65.706mm,79.324mm)(71.668mm,79.324mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.245mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-1(45.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-1(45.885mm,61.077mm) on Top Layer And Track (46.385mm,60.339mm)(46.385mm,61.814mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-10(41.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-11(40.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-12(40.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-13(39.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-14(39.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-15(38.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-16(38.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-17(37.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-18(37.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-19(36.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-2(45.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-20(36.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-21(35.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-22(35.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-23(34.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-24(34.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.029mm < 0.254mm) Between Pad IC1-25(34.385mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.029mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-25(34.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-26(34.885mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-26(34.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-27(35.385mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-27(35.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-28(35.885mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-28(35.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-29(36.385mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-29(36.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-3(44.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.145mm < 0.254mm) Between Pad IC1-30(36.885mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.145mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-30(36.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-31(37.385mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-31(37.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-32(37.885mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-32(37.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad IC1-33(38.385mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-33(38.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.108mm < 0.254mm) Between Pad IC1-34(38.885mm,53.501mm) on Top Layer And Text "R13" (34.691mm,52.661mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.108mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-34(38.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-35(39.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-36(39.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-37(40.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-38(40.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-39(41.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-4(44.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-40(41.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-41(42.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-42(42.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-43(43.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-44(43.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-45(44.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-46(44.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-47(45.385mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.251mm < 0.254mm) Between Pad IC1-48(45.885mm,53.501mm) on Top Layer And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.251mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-5(43.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-6(43.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-7(42.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-8(42.385mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC1-9(41.885mm,61.077mm) on Top Layer And Track (33.885mm,59.989mm)(46.385mm,59.989mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-1(12.923mm,53.594mm) on Top Layer And Track (12.16mm,54.269mm)(13.685mm,54.269mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-1(12.923mm,53.594mm) on Top Layer And Track (14.035mm,49.239mm)(14.035mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-2(12.923mm,52.324mm) on Top Layer And Track (14.035mm,49.239mm)(14.035mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-3(12.923mm,51.054mm) on Top Layer And Track (14.035mm,49.239mm)(14.035mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-4(12.923mm,49.784mm) on Top Layer And Track (14.035mm,49.239mm)(14.035mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-5(18.347mm,49.784mm) on Top Layer And Track (17.235mm,49.239mm)(17.235mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-6(18.347mm,51.054mm) on Top Layer And Track (17.235mm,49.239mm)(17.235mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-7(18.347mm,52.324mm) on Top Layer And Track (17.235mm,49.239mm)(17.235mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.25mm < 0.254mm) Between Pad IC2-8(18.347mm,53.594mm) on Top Layer And Track (17.235mm,49.239mm)(17.235mm,54.139mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.25mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R10-1(17.495mm,18.989mm) on Bottom Layer And Text "R7" (17.907mm,17.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.096mm < 0.254mm) Between Pad R10-2(14.595mm,18.989mm) on Bottom Layer And Text "R7" (17.907mm,17.408mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.096mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R1-1(14.67mm,27.724mm) on Top Layer And Text "R21" (14.097mm,26.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R11-1(17.65mm,27.724mm) on Bottom Layer And Text "R15" (18.212mm,26.603mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R11-2(14.75mm,27.724mm) on Bottom Layer And Text "R15" (18.212mm,26.603mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R1-2(17.57mm,27.724mm) on Top Layer And Text "R21" (14.097mm,26.603mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R12-1(47.915mm,37.699mm) on Bottom Layer And Text "R14" (48.54mm,36.483mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.119mm < 0.254mm) Between Pad R15-1(14.75mm,24.714mm) on Bottom Layer And Text "R8" (18.085mm,23.733mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0.119mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R15-2(17.65mm,24.714mm) on Bottom Layer And Text "R8" (18.085mm,23.733mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R16-1(14.42mm,79.974mm) on Bottom Layer And Text "R18" (18.009mm,78.901mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R16-2(17.32mm,79.974mm) on Bottom Layer And Text "R18" (18.009mm,78.901mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R17-1(14.53mm,87.529mm) on Bottom Layer And Text "R19" (17.882mm,86.521mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R17-2(17.43mm,87.529mm) on Bottom Layer And Text "R19" (17.882mm,86.521mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R2-1(14.615mm,18.914mm) on Top Layer And Text "R6" (13.869mm,17.484mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R21-1(14.67mm,24.714mm) on Top Layer And Text "R5" (14.021mm,23.733mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R22-1(14.42mm,79.974mm) on Top Layer And Text "R25" (13.894mm,78.901mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R22-2(17.32mm,79.974mm) on Top Layer And Text "R25" (13.894mm,78.901mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R24-1(14.53mm,87.529mm) on Top Layer And Text "R26" (13.843mm,86.521mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R24-2(17.43mm,87.529mm) on Top Layer And Text "R26" (13.843mm,86.521mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R4-2(50.99mm,37.699mm) on Top Layer And Text "J4" (49.81mm,36.585mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R4-2(50.99mm,37.699mm) on Top Layer And Text "R23" (46.787mm,36.407mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R5-1(14.59mm,21.849mm) on Top Layer And Text "R2" (14.046mm,20.812mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.227mm < 0.254mm) Between Pad R5-2(17.49mm,21.849mm) on Top Layer And Text "R2" (14.046mm,20.812mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.227mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R6-1(14.445mm,15.604mm) on Top Layer And Text "R3" (14.021mm,14.106mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.108mm < 0.254mm) Between Pad R6-2(17.345mm,15.604mm) on Top Layer And Text "R3" (14.021mm,14.106mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.108mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R7-1(17.345mm,15.529mm) on Bottom Layer And Text "R9" (18.136mm,14.106mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R8-1(17.515mm,21.854mm) on Bottom Layer And Text "R10" (18.06mm,20.888mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.254mm) Between Pad R8-2(14.615mm,21.854mm) on Bottom Layer And Text "R10" (18.06mm,20.888mm) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mm] Rule Violations :99 Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All) - Violation between Silk To Silk Clearance Constraint: (0.107mm < 0.254mm) Between Text "IC2" (16.281mm,66.269mm) on Top Overlay And Text "R27" (12.441mm,67.256mm) on Top Overlay Silk Text to Silk Clearance [0.107mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "J4" (53.95mm,47.625mm) on Top Overlay And Text "R23" (50.927mm,47.447mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "J4" (53.95mm,47.625mm) on Top Overlay And Track (56.58mm,48.064mm)(56.58mm,49.414mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R10" (22.2mm,31.928mm) on Bottom Overlay And Track (20.205mm,32.219mm)(20.205mm,33.569mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (0.177mm < 0.254mm) Between Text "R13" (38.831mm,63.701mm) on Top Overlay And Track (38.025mm,65.629mm)(50.525mm,65.629mm) on Top Overlay Silk Text to Silk Clearance [0.177mm] - Violation between Silk To Silk Clearance Constraint: (0.008mm < 0.254mm) Between Text "R15" (22.352mm,37.643mm) on Bottom Overlay And Track (20.34mm,38.089mm)(20.34mm,39.439mm) on Bottom Overlay Silk Text to Silk Clearance [0.008mm] - Violation between Silk To Silk Clearance Constraint: (0.134mm < 0.254mm) Between Text "R18" (22.149mm,89.941mm) on Bottom Overlay And Track (20.01mm,90.339mm)(20.01mm,91.689mm) on Bottom Overlay Silk Text to Silk Clearance [0.134mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R19" (22.022mm,97.561mm) on Bottom Overlay And Track (20.12mm,97.894mm)(20.12mm,99.244mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (18.186mm,31.852mm) on Top Overlay And Track (20.18mm,32.214mm)(20.18mm,33.564mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R21" (18.237mm,37.643mm) on Top Overlay And Track (20.26mm,38.089mm)(20.26mm,39.439mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R25" (18.034mm,89.941mm) on Top Overlay And Track (20.01mm,90.339mm)(20.01mm,91.689mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R26" (17.983mm,97.561mm) on Top Overlay And Track (20.12mm,97.894mm)(20.12mm,99.244mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (18.161mm,25.146mm) on Top Overlay And Track (20.035mm,25.969mm)(20.035mm,27.319mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R5" (18.161mm,34.773mm) on Top Overlay And Track (20.26mm,35.079mm)(20.26mm,36.429mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R6" (18.009mm,28.524mm) on Top Overlay And Track (20.205mm,29.279mm)(20.205mm,30.629mm) on Top Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R7" (22.047mm,28.448mm) on Bottom Overlay And Track (20.185mm,29.354mm)(20.185mm,30.704mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R8" (22.225mm,34.773mm) on Bottom Overlay And Track (20.34mm,35.079mm)(20.34mm,36.429mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] - Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R9" (22.276mm,25.146mm) on Bottom Overlay And Track (20.035mm,25.894mm)(20.035mm,27.244mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.107mm < 0.254mm) Between Text "IC2" (12.141mm,55.229mm) on Top Overlay And Text "R27" (8.301mm,56.216mm) on Top Overlay Silk Text to Silk Clearance [0.107mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "J4" (49.81mm,36.585mm) on Top Overlay And Text "R23" (46.787mm,36.407mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "J4" (49.81mm,36.585mm) on Top Overlay And Track (52.44mm,37.024mm)(52.44mm,38.374mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R10" (18.06mm,20.888mm) on Bottom Overlay And Track (16.065mm,21.179mm)(16.065mm,22.529mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (0.177mm < 0.254mm) Between Text "R13" (34.691mm,52.661mm) on Top Overlay And Track (33.885mm,54.589mm)(46.385mm,54.589mm) on Top Overlay Silk Text to Silk Clearance [0.177mm] + Violation between Silk To Silk Clearance Constraint: (0.008mm < 0.254mm) Between Text "R15" (18.212mm,26.603mm) on Bottom Overlay And Track (16.2mm,27.049mm)(16.2mm,28.399mm) on Bottom Overlay Silk Text to Silk Clearance [0.008mm] + Violation between Silk To Silk Clearance Constraint: (0.134mm < 0.254mm) Between Text "R18" (18.009mm,78.901mm) on Bottom Overlay And Track (15.87mm,79.299mm)(15.87mm,80.649mm) on Bottom Overlay Silk Text to Silk Clearance [0.134mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R19" (17.882mm,86.521mm) on Bottom Overlay And Track (15.98mm,86.854mm)(15.98mm,88.204mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R2" (14.046mm,20.812mm) on Top Overlay And Track (16.04mm,21.174mm)(16.04mm,22.524mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R21" (14.097mm,26.603mm) on Top Overlay And Track (16.12mm,27.049mm)(16.12mm,28.399mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R25" (13.894mm,78.901mm) on Top Overlay And Track (15.87mm,79.299mm)(15.87mm,80.649mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R26" (13.843mm,86.521mm) on Top Overlay And Track (15.98mm,86.854mm)(15.98mm,88.204mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R3" (14.021mm,14.106mm) on Top Overlay And Track (15.895mm,14.929mm)(15.895mm,16.279mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R5" (14.021mm,23.733mm) on Top Overlay And Track (16.12mm,24.039mm)(16.12mm,25.389mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R6" (13.869mm,17.484mm) on Top Overlay And Track (16.065mm,18.239mm)(16.065mm,19.589mm) on Top Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R7" (17.907mm,17.408mm) on Bottom Overlay And Track (16.045mm,18.314mm)(16.045mm,19.664mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R8" (18.085mm,23.733mm) on Bottom Overlay And Track (16.2mm,24.039mm)(16.2mm,25.389mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] + Violation between Silk To Silk Clearance Constraint: (Collision < 0.254mm) Between Text "R9" (18.136mm,14.106mm) on Bottom Overlay And Track (15.895mm,14.854mm)(15.895mm,16.204mm) on Bottom Overlay Silk Text to Silk Clearance [0mm] Rule Violations :18 Processing Rule : Net Antennae (Tolerance=0mm) (All) @@ -163,31 +171,26 @@ Processing Rule : Height Constraint (Min=0mm) (Max=50mm) (Prefered=12.7mm) (All) Rule Violations :0 Waived Violations Of Rule : Un-Routed Net Constraint ( (All) ) - Waived Violation between Un-Routed Net Constraint: Net +5V Between Pad P1-1(14.575mm,12.309mm) on Multi-Layer And Track (14.593mm,45.347mm)(18.112mm,45.347mm) on Top Layer Waived by Jules Pare at 13/03/2020 2:08:34 PM - Waived Violation between Un-Routed Net Constraint: Net +5V Between Track (17.645mm,108.829mm)(17.68mm,108.864mm) on Bottom Layer And Track (22.62mm,66.684mm)(22.765mm,66.829mm) on Top Layer Waived by Jules Pare at 13/03/2020 2:11:01 PM + Waived Violation between Un-Routed Net Constraint: Net +5V Between Pad P1-1(10.435mm,1.269mm) on Multi-Layer And Track (10.464mm,34.26mm)(13.926mm,34.26mm) on Top Layer Waived by Miles Ransaw at 2020-04-08 15:47:25 + Waived Violation between Un-Routed Net Constraint: Net +5V Between Track (13.505mm,97.789mm)(13.54mm,97.824mm) on Bottom Layer And Track (17.835mm,53.519mm)(18.272mm,53.519mm) on Top Layer Waived by Miles Ransaw at 2020-04-08 15:47:25 Waived Violations :2 Waived Violations Of Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) - Waived Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(10.16mm,10mm) on Multi-Layer Actual Hole Size = 3.4mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(10.16mm,142mm) on Multi-Layer Actual Hole Size = 3.4mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(198.595mm,148.495mm) on Multi-Layer Actual Hole Size = 3.4mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(94.16mm,10mm) on Multi-Layer Actual Hole Size = 3.4mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(94.16mm,142mm) on Multi-Layer Actual Hole Size = 3.4mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J5-MH1(96.7mm,91.776mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J5-MH2(96.7mm,132.777mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J6-MH1(96.7mm,19.576mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 13/03/2020 1:34:14 PM - Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J6-MH2(96.7mm,60.577mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 13/03/2020 1:34:14 PM -Waived Violations :9 + Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J5-MH1(90.39mm,78.567mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 2020-03-13 13:34:14 + Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J5-MH2(90.39mm,119.567mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 2020-03-13 13:34:14 + Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J6-MH1(90.39mm,6.366mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 2020-03-13 13:34:14 + Waived Violation between Hole Size Constraint: (2.93mm > 2.54mm) Pad J6-MH2(90.39mm,47.367mm) on Multi-Layer Actual Hole Size = 2.93mmWaived by Jules Pare at 2020-03-13 13:34:14 +Waived Violations :4 Waived Violations Of Rule : Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) - Waived Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad D1-1(77.982mm,89.589mm) on Top Layer And Pad D1-2(77.982mm,91.429mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]Waived by Jules Pare at 13/03/2020 1:34:26 PM - Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-1(71.6mm,75.509mm) on Multi-Layer And Pad PS1-2(73.3mm,75.509mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 13/03/2020 1:35:46 PM - Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-2(73.3mm,75.509mm) on Multi-Layer And Pad PS1-3(75mm,75.509mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 13/03/2020 1:35:46 PM - Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-3(75mm,75.509mm) on Multi-Layer And Pad PS1-4(76.7mm,75.509mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 13/03/2020 1:35:46 PM - Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-4(76.7mm,75.509mm) on Multi-Layer And Pad PS1-5(78.4mm,75.509mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 13/03/2020 1:35:46 PM + Waived Violation between Minimum Solder Mask Sliver Constraint: (0.247mm < 0.254mm) Between Pad D1-1(71.672mm,76.379mm) on Top Layer And Pad D1-2(71.672mm,78.219mm) on Top Layer [Top Solder] Mask Sliver [0.247mm]Waived by Jules Pare at 2020-03-13 13:34:26 + Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-1(65.29mm,62.299mm) on Multi-Layer And Pad PS1-2(66.99mm,62.299mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 2020-03-13 13:35:46 + Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-2(66.99mm,62.299mm) on Multi-Layer And Pad PS1-3(68.69mm,62.299mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 2020-03-13 13:35:46 + Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-3(68.69mm,62.299mm) on Multi-Layer And Pad PS1-4(70.39mm,62.299mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 2020-03-13 13:35:46 + Waived Violation between Minimum Solder Mask Sliver Constraint: (0.097mm < 0.254mm) Between Pad PS1-4(70.39mm,62.299mm) on Multi-Layer And Pad PS1-5(72.09mm,62.299mm) on Multi-Layer [Top Solder] Mask Sliver [0.097mm] / [Bottom Solder] Mask Sliver [0.097mm]Waived by Jules Pare at 2020-03-13 13:35:46 Waived Violations :5 -Violations Detected : 117 -Waived Violations : 16 -Time Elapsed : 00:00:00 \ No newline at end of file +Violations Detected : 125 +Waived Violations : 11 +Time Elapsed : 00:00:02 \ No newline at end of file diff --git a/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.html b/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.html index e6d4643..705fff4 100644 --- a/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.html +++ b/Project Outputs for TiSupervisoryController/Design Rule Check - PCB1.html @@ -211,7 +211,7 @@
| @@ -219,22 +219,22 @@ | |||
| Date: | - | 13/03/2020 | +2020-04-08 |
| Time: | - | 2:15:08 PM | +16:04:38 |
| Elapsed Time: | - | 00:00:00 | +00:00:02 |
| Filename: | - | C:\Users\Hybrid\Documents\GitHub\TISupervisoryController\PCB1.PcbDoc | +C:\Users\M\workspace\TIsupervisorycontroller\PCB1.PcbDoc |
| Un-Routed Net Constraint ( (All) ) | |
|---|---|
| Hole Size Constraint: (3.4mm > 2.54mm) Pad Free-1(94.16mm,142mm) on Multi-Layer Actual Hole Size = 3.4mm Waived by Jules Pare at 13/03/2020 1:34:14 PM |
+Un-Routed Net Constraint: Net +5V Between Pad P1-1(10.435mm,1.269mm) on Multi-Layer And Track (10.464mm,34.26mm)(13.926mm,34.26mm) on Top Layer Waived by Miles Ransaw at 2020-04-08 15:47:25 |
| Hole Size Constraint: (2.93mm > 2.54mm) Pad J5-MH1(96.7mm,91.776mm) on Multi-Layer Actual Hole Size = 2.93mm Waived by Jules Pare at 13/03/2020 1:34:14 PM |
+Un-Routed Net Constraint: Net +5V Between Track (13.505mm,97.789mm)(13.54mm,97.824mm) on Bottom Layer And Track (17.835mm,53.519mm)(18.272mm,53.519mm) on Top Layer Waived by Miles Ransaw at 2020-04-08 15:47:25 |
+